diff --git a/PLLJ_PLLSPE_INFO.txt b/PLLJ_PLLSPE_INFO.txt index e371ee0..7c986dc 100644 --- a/PLLJ_PLLSPE_INFO.txt +++ b/PLLJ_PLLSPE_INFO.txt @@ -1,3 +1,8 @@ +PLL_Name sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 +PLLJITTER 35 +PLLSPEmax 84 +PLLSPEmin -53 + PLL_Name ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 PLLJITTER NA PLLSPEmax 84 diff --git a/db/.cmp.kpt b/db/.cmp.kpt index 8d7e5c6..eda2417 100644 Binary files a/db/.cmp.kpt and b/db/.cmp.kpt differ diff --git a/db/logic_util_heursitic.dat b/db/logic_util_heursitic.dat index e1be902..a9de2b0 100644 Binary files a/db/logic_util_heursitic.dat and b/db/logic_util_heursitic.dat differ diff --git a/db/prev_cmp_spectrum.qmsg b/db/prev_cmp_spectrum.qmsg index 950cfe7..2f381ab 100644 --- a/db/prev_cmp_spectrum.qmsg +++ b/db/prev_cmp_spectrum.qmsg @@ -1,65 +1,329 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828489178 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828489179 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 1 18:54:49 2022 " "Processing started: Fri Apr 1 18:54:49 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828489179 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648828489179 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648828489179 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648828489379 ""} -{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\".\"; expecting a direction spectrum.sv(6) " "Verilog HDL syntax error at spectrum.sv(6) near text \".\"; expecting a direction" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 6 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0 "Quartus II" 0 -1 1648828489447 ""} -{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "spectrum spectrum.sv(1) " "Ignored design unit \"spectrum\" at spectrum.sv(1) due to previous errors" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1648828489448 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.sv 0 0 " "Found 0 design units, including 0 entities, in source file spectrum.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489449 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489454 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489454 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram16.v 1 1 " "Found 1 design units, including 1 entities, in source file ram16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram16 " "Found entity 1: ram16" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489455 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489455 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram32.v 1 1 " "Found 1 design units, including 1 entities, in source file ram32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram32 " "Found entity 1: ram32" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489456 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489456 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Found entity 1: pll" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489457 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489457 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Found entity 1: alu" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489459 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489459 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_bit_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_bit_select " "Found entity 1: alu_bit_select" { } { { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489459 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489459 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_control " "Found entity 1: alu_control" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489460 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489460 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_core " "Found entity 1: alu_core" { } { { "cpu/alu/alu_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489461 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489461 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_flags.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_flags " "Found entity 1: alu_flags" { } { { "cpu/alu/alu_flags.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489462 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489462 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2 " "Found entity 1: alu_mux_2" { } { { "cpu/alu/alu_mux_2.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489463 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489463 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2z " "Found entity 1: alu_mux_2z" { } { { "cpu/alu/alu_mux_2z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489464 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489464 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_3z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_3z " "Found entity 1: alu_mux_3z" { } { { "cpu/alu/alu_mux_3z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_3z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489464 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489464 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_4.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_4 " "Found entity 1: alu_mux_4" { } { { "cpu/alu/alu_mux_4.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_4.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489465 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489465 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_8.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_8 " "Found entity 1: alu_mux_8" { } { { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489466 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489466 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_prep_daa.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_prep_daa " "Found entity 1: alu_prep_daa" { } { { "cpu/alu/alu_prep_daa.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_prep_daa.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489466 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489466 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_select " "Found entity 1: alu_select" { } { { "cpu/alu/alu_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489467 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_shifter_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_shifter_core " "Found entity 1: alu_shifter_core" { } { { "cpu/alu/alu_shifter_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_shifter_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489468 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489468 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_slice.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_slice " "Found entity 1: alu_slice" { } { { "cpu/alu/alu_slice.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_slice.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489469 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489469 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/clk_delay.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_delay " "Found entity 1: clk_delay" { } { { "cpu/control/clk_delay.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/clk_delay.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489470 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489470 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/decode_state.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode_state " "Found entity 1: decode_state" { } { { "cpu/control/decode_state.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/decode_state.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489471 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489471 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/execute.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/execute.v" { { "Info" "ISGN_ENTITY_NAME" "1 execute " "Found entity 1: execute" { } { { "cpu/control/execute.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/execute.v" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489497 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489497 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/interrupts.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v" { { "Info" "ISGN_ENTITY_NAME" "1 interrupts " "Found entity 1: interrupts" { } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489498 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489498 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/ir.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/ir.v" { { "Info" "ISGN_ENTITY_NAME" "1 ir " "Found entity 1: ir" { } { { "cpu/control/ir.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/ir.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489499 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489499 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/memory_ifc.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v" { { "Info" "ISGN_ENTITY_NAME" "1 memory_ifc " "Found entity 1: memory_ifc" { } { { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489500 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489500 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pin_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 pin_control " "Found entity 1: pin_control" { } { { "cpu/control/pin_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pin_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489501 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489501 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pla_decode.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v" { { "Info" "ISGN_ENTITY_NAME" "1 pla_decode " "Found entity 1: pla_decode" { } { { "cpu/control/pla_decode.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pla_decode.v" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489502 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489502 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/resets.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/resets.v" { { "Info" "ISGN_ENTITY_NAME" "1 resets " "Found entity 1: resets" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489503 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489503 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/sequencer.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v" { { "Info" "ISGN_ENTITY_NAME" "1 sequencer " "Found entity 1: sequencer" { } { { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489504 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489504 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_latch " "Found entity 1: address_latch" { } { { "cpu/bus/address_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489505 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489505 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_mux.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_mux " "Found entity 1: address_mux" { } { { "cpu/bus/address_mux.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_mux.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489506 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489506 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_pins " "Found entity 1: address_pins" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489506 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489506 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_control " "Found entity 1: bus_control" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489507 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489507 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_switch " "Found entity 1: bus_switch" { } { { "cpu/bus/bus_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_switch.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489508 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489508 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/control_pins_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_pins_n " "Found entity 1: control_pins_n" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489509 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489509 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_pins " "Found entity 1: data_pins" { } { { "cpu/bus/data_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489510 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489510 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch " "Found entity 1: data_switch" { } { { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489510 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489510 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch_mask.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch_mask " "Found entity 1: data_switch_mask" { } { { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489511 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489511 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec " "Found entity 1: inc_dec" { } { { "cpu/bus/inc_dec.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489512 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489512 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec_2bit.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec_2bit " "Found entity 1: inc_dec_2bit" { } { { "cpu/bus/inc_dec_2bit.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec_2bit.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489513 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489513 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "nRESET nreset z80_top_direct_n.v(19) " "Verilog HDL Declaration information at z80_top_direct_n.v(19): object \"nRESET\" differs only in case from object \"nreset\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 19 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648828489515 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CLK clk z80_top_direct_n.v(22) " "Verilog HDL Declaration information at z80_top_direct_n.v(22): object \"CLK\" differs only in case from object \"clk\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648828489515 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/toplevel/z80_top_direct_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 z80_top_direct_n " "Found entity 1: z80_top_direct_n" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489515 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489515 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_control " "Found entity 1: reg_control" { } { { "cpu/registers/reg_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489516 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489516 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_file.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_file " "Found entity 1: reg_file" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489518 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489518 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_latch " "Found entity 1: reg_latch" { } { { "cpu/registers/reg_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489519 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489519 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/clocks.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/clocks.sv" { { "Info" "ISGN_ENTITY_NAME" "1 clocks " "Found entity 1: clocks" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489519 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489519 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/zx_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 zx_keyboard " "Found entity 1: zx_keyboard" { } { { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489520 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489520 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/video.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/video.sv" { { "Info" "ISGN_ENTITY_NAME" "1 video " "Found entity 1: video" { } { { "ula/video.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/video.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489521 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489521 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ula.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ula.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ula " "Found entity 1: ula" { } { { "ula/ula.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489522 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489522 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ps2_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ps2_keyboard " "Found entity 1: ps2_keyboard" { } { { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489523 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489523 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2c_loader.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_loader-i2c_loader_arch " "Found design unit 1: i2c_loader-i2c_loader_arch" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489823 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2c_loader " "Found entity 1: i2c_loader" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489823 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489823 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2s_intf.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2s_intf-i2s_intf_arch " "Found design unit 1: i2s_intf-i2s_intf_arch" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489824 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2s_intf " "Found entity 1: i2s_intf" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489824 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489824 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_scr.v 1 1 " "Found 1 design units, including 1 entities, in source file rom_scr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_scr " "Found entity 1: rom_scr" { } { { "rom_scr.v" "" { Text "/home/benny/work/fpga/spectrum/rom_scr.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489827 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489827 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_video.v 1 1 " "Found 1 design units, including 1 entities, in source file pll_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_video " "Found entity 1: pll_video" { } { { "pll_video.v" "" { Text "/home/benny/work/fpga/spectrum/pll_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489828 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489828 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_video.v 1 1 " "Found 1 design units, including 1 entities, in source file ram_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram_video " "Found entity 1: ram_video" { } { { "ram_video.v" "" { Text "/home/benny/work/fpga/spectrum/ram_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489829 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489829 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1648828489902 ""} -{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 1 Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "397 " "Peak virtual memory: 397 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828489948 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Apr 1 18:54:49 2022 " "Processing ended: Fri Apr 1 18:54:49 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828489948 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828489948 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828489948 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648828489948 ""} -{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 4 s 1 " "Quartus II Full Compilation was unsuccessful. 4 errors, 1 warning" { } { } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648828490035 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648899774991 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648899774992 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:42:54 2022 " "Processing started: Sat Apr 2 14:42:54 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648899774992 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648899774992 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648899774992 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648899775174 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.sv 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.sv" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775242 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775242 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775243 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775243 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram16.v 1 1 " "Found 1 design units, including 1 entities, in source file ram16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram16 " "Found entity 1: ram16" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775244 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775244 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram32.v 1 1 " "Found 1 design units, including 1 entities, in source file ram32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram32 " "Found entity 1: ram32" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775245 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775245 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Found entity 1: pll" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775246 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775246 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Found entity 1: alu" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775248 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775248 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_bit_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_bit_select " "Found entity 1: alu_bit_select" { } { { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775249 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775249 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_control " "Found entity 1: alu_control" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775250 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775250 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_core " "Found entity 1: alu_core" { } { { "cpu/alu/alu_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775250 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775250 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_flags.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_flags " "Found entity 1: alu_flags" { } { { "cpu/alu/alu_flags.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775252 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775252 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2 " "Found entity 1: alu_mux_2" { } { { "cpu/alu/alu_mux_2.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775252 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775252 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2z " "Found entity 1: alu_mux_2z" { } { { "cpu/alu/alu_mux_2z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775253 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775253 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_3z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_3z " "Found entity 1: alu_mux_3z" { } { { "cpu/alu/alu_mux_3z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_3z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775254 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775254 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_4.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_4 " "Found entity 1: alu_mux_4" { } { { "cpu/alu/alu_mux_4.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_4.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775254 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775254 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_8.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_8 " "Found entity 1: alu_mux_8" { } { { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775255 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775255 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_prep_daa.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_prep_daa " "Found entity 1: alu_prep_daa" { } { { "cpu/alu/alu_prep_daa.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_prep_daa.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775256 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775256 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_select " "Found entity 1: alu_select" { } { { "cpu/alu/alu_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775257 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775257 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_shifter_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_shifter_core " "Found entity 1: alu_shifter_core" { } { { "cpu/alu/alu_shifter_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_shifter_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775258 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775258 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_slice.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_slice " "Found entity 1: alu_slice" { } { { "cpu/alu/alu_slice.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_slice.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775258 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775258 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/clk_delay.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_delay " "Found entity 1: clk_delay" { } { { "cpu/control/clk_delay.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/clk_delay.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775259 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775259 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/decode_state.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode_state " "Found entity 1: decode_state" { } { { "cpu/control/decode_state.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/decode_state.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775260 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775260 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/execute.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/execute.v" { { "Info" "ISGN_ENTITY_NAME" "1 execute " "Found entity 1: execute" { } { { "cpu/control/execute.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/execute.v" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775286 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775286 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/interrupts.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v" { { "Info" "ISGN_ENTITY_NAME" "1 interrupts " "Found entity 1: interrupts" { } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775287 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775287 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/ir.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/ir.v" { { "Info" "ISGN_ENTITY_NAME" "1 ir " "Found entity 1: ir" { } { { "cpu/control/ir.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/ir.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775288 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775288 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/memory_ifc.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v" { { "Info" "ISGN_ENTITY_NAME" "1 memory_ifc " "Found entity 1: memory_ifc" { } { { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775289 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775289 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pin_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 pin_control " "Found entity 1: pin_control" { } { { "cpu/control/pin_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pin_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775290 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775290 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pla_decode.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v" { { "Info" "ISGN_ENTITY_NAME" "1 pla_decode " "Found entity 1: pla_decode" { } { { "cpu/control/pla_decode.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pla_decode.v" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775291 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775291 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/resets.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/resets.v" { { "Info" "ISGN_ENTITY_NAME" "1 resets " "Found entity 1: resets" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775292 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775292 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/sequencer.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v" { { "Info" "ISGN_ENTITY_NAME" "1 sequencer " "Found entity 1: sequencer" { } { { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775293 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775293 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_latch " "Found entity 1: address_latch" { } { { "cpu/bus/address_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775294 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775294 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_mux.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_mux " "Found entity 1: address_mux" { } { { "cpu/bus/address_mux.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_mux.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775295 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775295 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_pins " "Found entity 1: address_pins" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775296 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775296 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_control " "Found entity 1: bus_control" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775296 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775296 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_switch " "Found entity 1: bus_switch" { } { { "cpu/bus/bus_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_switch.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775297 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775297 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/control_pins_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_pins_n " "Found entity 1: control_pins_n" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775298 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775298 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_pins " "Found entity 1: data_pins" { } { { "cpu/bus/data_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775299 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775299 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch " "Found entity 1: data_switch" { } { { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775300 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775300 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch_mask.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch_mask " "Found entity 1: data_switch_mask" { } { { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775301 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775301 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec " "Found entity 1: inc_dec" { } { { "cpu/bus/inc_dec.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775302 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775302 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec_2bit.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec_2bit " "Found entity 1: inc_dec_2bit" { } { { "cpu/bus/inc_dec_2bit.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec_2bit.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775302 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775302 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "nRESET nreset z80_top_direct_n.v(19) " "Verilog HDL Declaration information at z80_top_direct_n.v(19): object \"nRESET\" differs only in case from object \"nreset\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 19 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648899775305 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CLK clk z80_top_direct_n.v(22) " "Verilog HDL Declaration information at z80_top_direct_n.v(22): object \"CLK\" differs only in case from object \"clk\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648899775305 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/toplevel/z80_top_direct_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 z80_top_direct_n " "Found entity 1: z80_top_direct_n" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775305 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775305 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_control " "Found entity 1: reg_control" { } { { "cpu/registers/reg_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775306 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775306 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_file.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_file " "Found entity 1: reg_file" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775308 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775308 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_latch " "Found entity 1: reg_latch" { } { { "cpu/registers/reg_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775308 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775308 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/clocks.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/clocks.sv" { { "Info" "ISGN_ENTITY_NAME" "1 clocks " "Found entity 1: clocks" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775309 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775309 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/zx_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 zx_keyboard " "Found entity 1: zx_keyboard" { } { { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775310 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775310 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/video.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/video.sv" { { "Info" "ISGN_ENTITY_NAME" "1 video " "Found entity 1: video" { } { { "ula/video.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/video.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775311 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775311 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ula.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ula.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ula " "Found entity 1: ula" { } { { "ula/ula.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775312 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775312 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ps2_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ps2_keyboard " "Found entity 1: ps2_keyboard" { } { { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775313 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775313 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2c_loader.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_loader-i2c_loader_arch " "Found design unit 1: i2c_loader-i2c_loader_arch" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775612 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2c_loader " "Found entity 1: i2c_loader" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775612 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775612 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2s_intf.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2s_intf-i2s_intf_arch " "Found design unit 1: i2s_intf-i2s_intf_arch" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775613 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2s_intf " "Found entity 1: i2s_intf" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775613 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775613 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_scr.v 1 1 " "Found 1 design units, including 1 entities, in source file rom_scr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_scr " "Found entity 1: rom_scr" { } { { "rom_scr.v" "" { Text "/home/benny/work/fpga/spectrum/rom_scr.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775616 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775616 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_video.v 1 1 " "Found 1 design units, including 1 entities, in source file pll_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_video " "Found entity 1: pll_video" { } { { "pll_video.v" "" { Text "/home/benny/work/fpga/spectrum/pll_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775617 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775617 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_video.v 1 1 " "Found 1 design units, including 1 entities, in source file ram_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram_video " "Found entity 1: ram_video" { } { { "ram_video.v" "" { Text "/home/benny/work/fpga/spectrum/ram_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775618 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775618 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram.vhdl 2 1 " "Found 2 design units, including 1 entities, in source file sdram.vhdl" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sdram_controller-rtl " "Found design unit 1: sdram_controller-rtl" { } { { "sdram.vhdl" "" { Text "/home/benny/work/fpga/spectrum/sdram.vhdl" 42 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775620 ""} { "Info" "ISGN_ENTITY_NAME" "1 sdram_controller " "Found entity 1: sdram_controller" { } { { "sdram.vhdl" "" { Text "/home/benny/work/fpga/spectrum/sdram.vhdl" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775620 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775620 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_clk_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_clk_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_clk_gen " "Found entity 1: sdram_clk_gen" { } { { "sdram_clk_gen.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775621 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775621 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648899775785 ""} +{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[7..4\] spectrum.sv(1) " "Output port \"LED\[7..4\]\" at spectrum.sv(1) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648899775790 "|spectrum"} +{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[1\] spectrum.sv(1) " "Output port \"LED\[1\]\" at spectrum.sv(1) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648899775790 "|spectrum"} +{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "GPIO_1\[33..32\] spectrum.sv(20) " "Output port \"GPIO_1\[33..32\]\" at spectrum.sv(20) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648899775790 "|spectrum"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.sv" "rom" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 147 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775804 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775853 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom/gw03.hex " "Parameter \"init_file\" = \"./rom/gw03.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648899775854 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qh91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qh91 " "Found entity 1: altsyncram_qh91" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775905 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775905 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qh91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated " "Elaborating entity \"altsyncram_qh91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775906 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_c8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_c8a " "Found entity 1: decode_c8a" { } { { "db/decode_c8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_c8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775949 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775949 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_c8a rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode " "Elaborating entity \"decode_c8a\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode\"" { } { { "db/altsyncram_qh91.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 40 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775949 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3nb " "Found entity 1: mux_3nb" { } { { "db/mux_3nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_3nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775993 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775993 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_3nb rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2 " "Elaborating entity \"mux_3nb\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2\"" { } { { "db/altsyncram_qh91.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 41 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775993 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram16 ram16:ram0 " "Elaborating entity \"ram16\" for hierarchy \"ram16:ram0\"" { } { { "spectrum.sv" "ram0" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775997 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram16:ram0\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776001 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "ram16:ram0\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram16:ram0\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram16:ram0\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ula/test_scr.hex " "Parameter \"init_file\" = \"ula/test_scr.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 16384 " "Parameter \"numwords_b\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_b NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_b\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 14 " "Parameter \"widthad_b\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 8 " "Parameter \"width_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648899776002 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_7ti2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_7ti2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_7ti2 " "Found entity 1: altsyncram_7ti2" { } { { "db/altsyncram_7ti2.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776052 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776052 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_7ti2 ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated " "Elaborating entity \"altsyncram_7ti2\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776052 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_jsa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_jsa " "Found entity 1: decode_jsa" { } { { "db/decode_jsa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_jsa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776096 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776096 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_jsa ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2 " "Elaborating entity \"decode_jsa\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2\"" { } { { "db/altsyncram_7ti2.tdf" "decode2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776096 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram32 ram32:ram1 " "Elaborating entity \"ram32\" for hierarchy \"ram32:ram1\"" { } { { "spectrum.sv" "ram1" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776102 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram32:ram1\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776106 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "ram32:ram1\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram32:ram1\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram32:ram1\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32768 " "Parameter \"numwords_a\" = \"32768\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 15 " "Parameter \"widthad_a\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648899776107 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_g9i1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_g9i1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_g9i1 " "Found entity 1: altsyncram_g9i1" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776158 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776158 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_g9i1 ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated " "Elaborating entity \"altsyncram_g9i1\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776158 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_msa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_msa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_msa " "Found entity 1: decode_msa" { } { { "db/decode_msa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_msa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776202 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776202 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_msa ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3 " "Elaborating entity \"decode_msa\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3\"" { } { { "db/altsyncram_g9i1.tdf" "decode3" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776203 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_f8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_f8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_f8a " "Found entity 1: decode_f8a" { } { { "db/decode_f8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_f8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776246 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776246 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_f8a ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode " "Elaborating entity \"decode_f8a\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode\"" { } { { "db/altsyncram_g9i1.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 45 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776247 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_6nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_6nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_6nb " "Found entity 1: mux_6nb" { } { { "db/mux_6nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_6nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776291 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776291 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_6nb ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2 " "Elaborating entity \"mux_6nb\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2\"" { } { { "db/altsyncram_g9i1.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 46 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776291 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_controller sdram_controller:sdram_ " "Elaborating entity \"sdram_controller\" for hierarchy \"sdram_controller:sdram_\"" { } { { "spectrum.sv" "sdram_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776293 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_clk_gen sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll " "Elaborating entity \"sdram_clk_gen\" for hierarchy \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\"" { } { { "sdram.vhdl" "sdram_clk_pll" { Text "/home/benny/work/fpga/spectrum/sdram.vhdl" 145 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776297 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\"" { } { { "sdram_clk_gen.v" "altpll_component" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 94 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776326 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component " "Elaborated megafunction instantiation \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\"" { } { { "sdram_clk_gen.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 94 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component " "Instantiated megafunction \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Parameter \"clk0_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 2 " "Parameter \"clk0_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 1 " "Parameter \"clk1_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 2 " "Parameter \"clk1_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 3000 " "Parameter \"clk1_phase_shift\" = \"3000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=sdram_clk_gen " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=sdram_clk_gen\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Parameter \"port_locked\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} } { { "sdram_clk_gen.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 94 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648899776330 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sdram_clk_gen_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/sdram_clk_gen_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_clk_gen_altpll " "Found entity 1: sdram_clk_gen_altpll" { } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776381 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776381 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_clk_gen_altpll sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated " "Elaborating entity \"sdram_clk_gen_altpll\" for hierarchy \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776382 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ula ula:ula_ " "Elaborating entity \"ula\" for hierarchy \"ula:ula_\"" { } { { "spectrum.sv" "ula_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 303 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776384 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll ula:ula_\|pll:pll_ " "Elaborating entity \"pll\" for hierarchy \"ula:ula_\|pll:pll_\"" { } { { "ula/ula.sv" "pll_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776385 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "altpll_component" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776395 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborated megafunction instantiation \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776398 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Instantiated megafunction \"ula:ula_\|pll:pll_\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 2000 " "Parameter \"clk0_divide_by\" = \"2000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 1007 " "Parameter \"clk0_multiply_by\" = \"1007\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 25 " "Parameter \"clk1_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 7 " "Parameter \"clk1_multiply_by\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 25 " "Parameter \"clk2_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_duty_cycle 50 " "Parameter \"clk2_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 12 " "Parameter \"clk2_multiply_by\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_USED " "Parameter \"port_clk2\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock OFF " "Parameter \"self_reset_on_loss_lock\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648899776399 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pll_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_altpll " "Found entity 1: pll_altpll" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776448 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776448 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_altpll ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated " "Elaborating entity \"pll_altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776449 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clocks ula:ula_\|clocks:clocks_ " "Elaborating entity \"clocks\" for hierarchy \"ula:ula_\|clocks:clocks_\"" { } { { "ula/ula.sv" "clocks_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776450 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_loader ula:ula_\|i2c_loader:i2c_loader_ " "Elaborating entity \"i2c_loader\" for hierarchy \"ula:ula_\|i2c_loader:i2c_loader_\"" { } { { "ula/ula.sv" "i2c_loader_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 124 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776451 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2s_intf ula:ula_\|i2s_intf:i2s_intf_ " "Elaborating entity \"i2s_intf\" for hierarchy \"ula:ula_\|i2s_intf:i2s_intf_\"" { } { { "ula/ula.sv" "i2s_intf_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 144 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776453 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "video ula:ula_\|video:video_ " "Elaborating entity \"video\" for hierarchy \"ula:ula_\|video:video_\"" { } { { "ula/ula.sv" "video_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 158 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776454 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ps2_keyboard ula:ula_\|ps2_keyboard:ps2_keyboard_ " "Elaborating entity \"ps2_keyboard\" for hierarchy \"ula:ula_\|ps2_keyboard:ps2_keyboard_\"" { } { { "ula/ula.sv" "ps2_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 167 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776456 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zx_keyboard ula:ula_\|zx_keyboard:zx_keyboard_ " "Elaborating entity \"zx_keyboard\" for hierarchy \"ula:ula_\|zx_keyboard:zx_keyboard_\"" { } { { "ula/ula.sv" "zx_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776457 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "z80_top_direct_n z80_top_direct_n:z80_ " "Elaborating entity \"z80_top_direct_n\" for hierarchy \"z80_top_direct_n:z80_\"" { } { { "spectrum.sv" "z80_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 347 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776460 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_delay z80_top_direct_n:z80_\|clk_delay:clk_delay_ " "Elaborating entity \"clk_delay\" for hierarchy \"z80_top_direct_n:z80_\|clk_delay:clk_delay_\"" { } { { "cpu/toplevel/coremodules.vh" "clk_delay_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 20 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776463 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_state z80_top_direct_n:z80_\|decode_state:decode_state_ " "Elaborating entity \"decode_state\" for hierarchy \"z80_top_direct_n:z80_\|decode_state:decode_state_\"" { } { { "cpu/toplevel/coremodules.vh" "decode_state_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 46 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776464 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "execute z80_top_direct_n:z80_\|execute:execute_ " "Elaborating entity \"execute\" for hierarchy \"z80_top_direct_n:z80_\|execute:execute_\"" { } { { "cpu/toplevel/coremodules.vh" "execute_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 180 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776465 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "interrupts z80_top_direct_n:z80_\|interrupts:interrupts_ " "Elaborating entity \"interrupts\" for hierarchy \"z80_top_direct_n:z80_\|interrupts:interrupts_\"" { } { { "cpu/toplevel/coremodules.vh" "interrupts_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 199 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776479 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ir z80_top_direct_n:z80_\|ir:ir_ " "Elaborating entity \"ir\" for hierarchy \"z80_top_direct_n:z80_\|ir:ir_\"" { } { { "cpu/toplevel/coremodules.vh" "ir_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 208 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776480 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pin_control z80_top_direct_n:z80_\|pin_control:pin_control_ " "Elaborating entity \"pin_control\" for hierarchy \"z80_top_direct_n:z80_\|pin_control:pin_control_\"" { } { { "cpu/toplevel/coremodules.vh" "pin_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 223 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776481 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pla_decode z80_top_direct_n:z80_\|pla_decode:pla_decode_ " "Elaborating entity \"pla_decode\" for hierarchy \"z80_top_direct_n:z80_\|pla_decode:pla_decode_\"" { } { { "cpu/toplevel/coremodules.vh" "pla_decode_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 229 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776481 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "resets z80_top_direct_n:z80_\|resets:resets_ " "Elaborating entity \"resets\" for hierarchy \"z80_top_direct_n:z80_\|resets:resets_\"" { } { { "cpu/toplevel/coremodules.vh" "resets_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 240 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776483 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "memory_ifc z80_top_direct_n:z80_\|memory_ifc:memory_ifc_ " "Elaborating entity \"memory_ifc\" for hierarchy \"z80_top_direct_n:z80_\|memory_ifc:memory_ifc_\"" { } { { "cpu/toplevel/coremodules.vh" "memory_ifc_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 264 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776484 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sequencer z80_top_direct_n:z80_\|sequencer:sequencer_ " "Elaborating entity \"sequencer\" for hierarchy \"z80_top_direct_n:z80_\|sequencer:sequencer_\"" { } { { "cpu/toplevel/coremodules.vh" "sequencer_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 286 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776485 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_control z80_top_direct_n:z80_\|alu_control:alu_control_ " "Elaborating entity \"alu_control\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 326 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776486 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_4 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux " "Elaborating entity \"alu_mux_4\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_cond_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 205 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776487 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_8 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux " "Elaborating entity \"alu_mux_8\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_shift_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 227 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776488 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_select z80_top_direct_n:z80_\|alu_select:alu_select_ " "Elaborating entity \"alu_select\" for hierarchy \"z80_top_direct_n:z80_\|alu_select:alu_select_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_select_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 363 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776489 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_flags z80_top_direct_n:z80_\|alu_flags:alu_flags_ " "Elaborating entity \"alu_flags\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_flags_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 405 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776489 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2 z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf " "Elaborating entity \"alu_mux_2\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf\"" { } { { "cpu/alu/alu_flags.v" "b2v_inst_mux_cf" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 344 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776490 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu z80_top_direct_n:z80_\|alu:alu_ " "Elaborating entity \"alu\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 448 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776491 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_core z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core " "Elaborating entity \"alu_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\"" { } { { "cpu/alu/alu.v" "b2v_core" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776493 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_slice z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0 " "Elaborating entity \"alu_slice\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0\"" { } { { "cpu/alu/alu_core.v" "b2v_alu_slice_bit_0" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 61 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776493 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_bit_select z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select " "Elaborating entity \"alu_bit_select\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\"" { } { { "cpu/alu/alu.v" "b2v_input_bit_select" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 186 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776496 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_shifter_core z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift " "Elaborating entity \"alu_shifter_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\"" { } { { "cpu/alu/alu.v" "b2v_input_shift" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 197 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776496 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high " "Elaborating entity \"alu_mux_2z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_high" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 318 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776497 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_3z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low " "Elaborating entity \"alu_mux_3z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_low" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 328 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776498 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_prep_daa z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa " "Elaborating entity \"alu_prep_daa\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa\"" { } { { "cpu/alu/alu.v" "b2v_prep_daa" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 364 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776499 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_file z80_top_direct_n:z80_\|reg_file:reg_file_ " "Elaborating entity \"reg_file\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_file_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 484 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776500 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_latch z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi " "Elaborating entity \"reg_latch\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\"" { } { { "cpu/registers/reg_file.v" "b2v_latch_af2_hi" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 279 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776502 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_control z80_top_direct_n:z80_\|reg_control:reg_control_ " "Elaborating entity \"reg_control\" for hierarchy \"z80_top_direct_n:z80_\|reg_control:reg_control_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 531 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776514 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_latch z80_top_direct_n:z80_\|address_latch:address_latch_ " "Elaborating entity \"address_latch\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\"" { } { { "cpu/toplevel/coremodules.vh" "address_latch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 547 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776515 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_mux z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7 " "Elaborating entity \"address_mux\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7\"" { } { { "cpu/bus/address_latch.v" "b2v_inst7" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 106 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776517 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec " "Elaborating entity \"inc_dec\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\"" { } { { "cpu/bus/address_latch.v" "b2v_inst_inc_dec" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776518 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec_2bit z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0 " "Elaborating entity \"inc_dec_2bit\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0\"" { } { { "cpu/bus/inc_dec.v" "b2v_dual_adder_0" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 80 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776519 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_control z80_top_direct_n:z80_\|bus_control:bus_control_ " "Elaborating entity \"bus_control\" for hierarchy \"z80_top_direct_n:z80_\|bus_control:bus_control_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 553 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776522 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_switch z80_top_direct_n:z80_\|bus_switch:bus_switch_ " "Elaborating entity \"bus_switch\" for hierarchy \"z80_top_direct_n:z80_\|bus_switch:bus_switch_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_switch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 566 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776523 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch z80_top_direct_n:z80_\|data_switch:sw2_ " "Elaborating entity \"data_switch\" for hierarchy \"z80_top_direct_n:z80_\|data_switch:sw2_\"" { } { { "cpu/toplevel/core.vh" "sw2_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 36 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776524 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch_mask z80_top_direct_n:z80_\|data_switch_mask:sw1_ " "Elaborating entity \"data_switch_mask\" for hierarchy \"z80_top_direct_n:z80_\|data_switch_mask:sw1_\"" { } { { "cpu/toplevel/core.vh" "sw1_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 39 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776524 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_pins z80_top_direct_n:z80_\|address_pins:address_pins_ " "Elaborating entity \"address_pins\" for hierarchy \"z80_top_direct_n:z80_\|address_pins:address_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "address_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 41 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776525 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_pins z80_top_direct_n:z80_\|data_pins:data_pins_ " "Elaborating entity \"data_pins\" for hierarchy \"z80_top_direct_n:z80_\|data_pins:data_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "data_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 51 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776526 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_pins_n z80_top_direct_n:z80_\|control_pins_n:control_pins_ " "Elaborating entity \"control_pins_n\" for hierarchy \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "control_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776527 ""} +{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a0 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a0\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 47 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a1 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a1\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 72 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a2 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a2\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 97 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a3 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a3\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 122 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a4 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a4\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 147 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a5 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a5\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 172 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a6 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a6\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 197 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a7 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a7\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 222 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a8 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a8\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 247 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a9 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a9\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 272 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a10 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a10\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 297 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a11 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a11\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 322 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a12 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a12\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 347 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a13 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a13\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 372 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a14 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a14\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 397 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a15 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a15\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 422 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a16 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a16\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 447 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a17 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a17\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 472 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a18 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a18\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 497 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a19 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a19\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 522 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a20 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a20\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 547 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a21 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a21\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 572 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a22 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a22\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 597 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a23 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a23\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 622 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a24 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a24\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 647 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a25 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a25\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 672 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a26 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a26\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 697 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a27 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a27\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 722 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a28 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a28\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 747 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a29 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a29\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 772 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a30 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a30\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 797 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a31 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a31\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 822 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31"} } { } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Quartus II" 0 -1 1648899776831 ""} } { } 0 14284 "Synthesized away the following node(s):" 0 0 "Quartus II" 0 -1 1648899776831 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1648899781398 ""} +{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\]\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\] RamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\]\" to the node \"RamWE\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\] RamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\]\" to the node \"RamWE\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR RamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR\" to the node \"RamWE\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 77 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD Equal1 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD\" to the node \"Equal1\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ Equal1 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ\" to the node \"Equal1\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1648899781498 ""} +{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[7\] z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[0\] z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[6\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[0\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"D\[0\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[1\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1 " "Converted the fan-out from the tri-state buffer \"D\[1\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[2\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2 " "Converted the fan-out from the tri-state buffer \"D\[2\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[3\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3 " "Converted the fan-out from the tri-state buffer \"D\[3\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[4\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4 " "Converted the fan-out from the tri-state buffer \"D\[4\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[5\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5 " "Converted the fan-out from the tri-state buffer \"D\[5\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[6\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6 " "Converted the fan-out from the tri-state buffer \"D\[6\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[7\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7 " "Converted the fan-out from the tri-state buffer \"D\[7\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1648899781504 ""} +{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 127 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 201 -1 0 } } { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 93 -1 0 } } { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 97 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 108 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 109 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 33 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 59 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1648899781529 ""} +{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1648899781529 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[1\] GND " "Pin \"LED\[1\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|LED[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[4\] GND " "Pin \"LED\[4\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|LED[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[5\] GND " "Pin \"LED\[5\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|LED[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[6\] GND " "Pin \"LED\[6\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|LED[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[7\] GND " "Pin \"LED\[7\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|LED[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[24\] VCC " "Pin \"GPIO_1\[24\]\" is stuck at VCC" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|GPIO_1[24]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[32\] GND " "Pin \"GPIO_1\[32\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|GPIO_1[32]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[33\] GND " "Pin \"GPIO_1\[33\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|GPIO_1[33]"} { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CKE VCC " "Pin \"DRAM_CKE\" is stuck at VCC" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 27 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|DRAM_CKE"} { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CS_N GND " "Pin \"DRAM_CS_N\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 30 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|DRAM_CS_N"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1648899784991 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648899785379 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1648899788636 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1648899788723 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "2 0 2 0 0 " "Adding 2 node(s), including 0 DDIO, 2 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648899788976 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899788976 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[0\] " "No output dependent on input pin \"SW\[0\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899789231 "|spectrum|SW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "No output dependent on input pin \"SW\[3\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899789231 "|spectrum|SW[3]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1648899789231 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "2957 " "Implemented 2957 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648899789231 ""} { "Info" "ICUT_CUT_TM_OPINS" "85 " "Implemented 85 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648899789231 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "18 " "Implemented 18 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1648899789231 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2809 " "Implemented 2809 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648899789231 ""} { "Info" "ICUT_CUT_TM_RAMS" "32 " "Implemented 32 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648899789231 ""} { "Info" "ICUT_CUT_TM_PLLS" "2 " "Implemented 2 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Quartus II" 0 -1 1648899789231 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648899789231 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 146 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 146 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "457 " "Peak virtual memory: 457 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648899789255 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:43:09 2022 " "Processing ended: Sat Apr 2 14:43:09 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648899789255 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648899789255 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:14 " "Total CPU time (on all processors): 00:00:14" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648899789255 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648899789255 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648899790598 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648899790599 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:43:10 2022 " "Processing started: Sat Apr 2 14:43:10 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648899790599 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1648899790599 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1648899790599 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1648899790623 ""} +{ "Info" "0" "" "Project = spectrum" { } { } 0 0 "Project = spectrum" 0 0 "Fitter" 0 0 1648899790624 ""} +{ "Info" "0" "" "Revision = spectrum" { } { } 0 0 "Revision = spectrum" 0 0 "Fitter" 0 0 1648899790624 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648899790713 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648899790729 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648899790766 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648899790767 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648899790767 ""} +{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] 2 1 0 0 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1261 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648899790833 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] 2 1 108 3000 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of 108 degrees (3000 ps) for sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1262 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648899790833 ""} } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1261 9662 10382 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1648899790833 ""} +{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] 141 280 0 0 " "Implementing clock multiplication of 141, clock division of 280, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1229 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648899790835 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] 47 168 0 0 " "Implementing clock multiplication of 47, clock division of 168, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1230 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648899790835 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] 47 98 0 0 " "Implementing clock multiplication of 47, clock division of 98, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1231 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648899790835 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1229 9662 10382 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1648899790835 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648899790913 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648899790924 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648899791139 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648899791139 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648899791139 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648899791139 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5104 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648899791146 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5106 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648899791146 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5108 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648899791146 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5110 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648899791146 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5112 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648899791146 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648899791146 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648899791149 ""} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648899791155 ""} +{ "Warning" "WFSAC_FSAC_PLL_MERGING_PARAMETERS_MISMATCH_WARNING" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 " "The parameters of the PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 and the PLL sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 do not have the same values - hence these PLLs cannot be merged" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "M sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"M\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "M sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 10 " "The value of the parameter \"M\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 10" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "M ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 141 " "The value of the parameter \"M\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 141" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "N sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"N\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "N sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 1 " "The value of the parameter \"N\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 1" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "N ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 7 " "The value of the parameter \"N\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 7" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "LOOP FILTER R sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"LOOP FILTER R\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "LOOP FILTER R sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 4000 " "The value of the parameter \"LOOP FILTER R\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 4000" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "LOOP FILTER R ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 12000 " "The value of the parameter \"LOOP FILTER R\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 12000" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "VCO POST SCALE sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"VCO POST SCALE\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "VCO POST SCALE sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 2 " "The value of the parameter \"VCO POST SCALE\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 2" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "VCO POST SCALE ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 1 " "The value of the parameter \"VCO POST SCALE\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 1" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Min VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Min VCO Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 1538 " "The value of the parameter \"Min VCO Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 1538" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min VCO Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 769 " "The value of the parameter \"Min VCO Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 769" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Max VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Max VCO Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 3333 " "The value of the parameter \"Max VCO Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 3333" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max VCO Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 1666 " "The value of the parameter \"Max VCO Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 1666" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Center VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Center VCO Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Center VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 1538 " "The value of the parameter \"Center VCO Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 1538" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Center VCO Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 769 " "The value of the parameter \"Center VCO Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 769" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Min Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Min Lock Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 15380 " "The value of the parameter \"Min Lock Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 15380" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min Lock Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 15489 " "The value of the parameter \"Min Lock Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 15489" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Max Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Max Lock Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 33330 " "The value of the parameter \"Max Lock Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 33330" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max Lock Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 26455 " "The value of the parameter \"Max Lock Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 26455" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1229 9662 10382 0} { 0 { 0 ""} 0 1261 9662 10382 0} } } } { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } } 0 176127 "The parameters of the PLL %1!s! and the PLL %2!s! do not have the same values - hence these PLLs cannot be merged" 0 0 "Fitter" 0 -1 1648899791688 ""} +{ "Critical Warning" "WFSAC_FSAC_PLL_FED_BY_REMOTE_CLOCK_PIN_NOT_COMPENSATED" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 0 Pin_R8 " "PLL \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1\" input clock inclk\[0\] is not fully compensated because it is fed by a remote clock pin \"Pin_R8\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 216 0 0 } } { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1261 9662 10382 0} } } } } 1 176598 "PLL \"%1!s!\" input clock inclk\[%2!d!\] is not fully compensated because it is fed by a remote clock pin \"%3!s!\"" 0 0 "Fitter" 0 -1 1648899791706 ""} +{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1648899792341 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648899792349 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792349 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648899792349 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792351 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792351 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792351 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792351 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792351 ""} } { } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1648899792351 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648899792352 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792352 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648899792352 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1648899792352 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648899792353 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648899792353 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648899792353 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648899792353 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648899792353 ""} +{ "Warning" "WSTA_SCC_LOOP" "507 " "Found combinational loop of 507 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|combout " "Node \"z80_\|bus_control_\|db\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|datab " "Node \"z80_\|alu_\|db_high\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|combout " "Node \"z80_\|alu_\|db_high\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|combout " "Node \"z80_\|alu_\|db_high\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|combout " "Node \"z80_\|alu_\|db_high\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|datab " "Node \"z80_\|alu_\|db\[4\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|combout " "Node \"z80_\|alu_\|db\[4\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datab " "Node \"z80_\|alu_\|db_high\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|combout " "Node \"z80_\|alu_\|db_high\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|datac " "Node \"z80_\|alu_\|db_high\[0\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~53\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~53\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~55\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~55\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~56\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~56\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~14\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~15\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~15\|dataa " "Node \"z80_\|alu_\|db\[4\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~15\|combout " "Node \"z80_\|alu_\|db\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|dataa " "Node \"z80_\|alu_\|db\[4\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~5\|datab " "Node \"z80_\|alu_\|db_high\[1\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~5\|combout " "Node \"z80_\|alu_\|db_high\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~6\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~6\|combout " "Node \"z80_\|alu_\|db_high\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~9\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~9\|combout " "Node \"z80_\|alu_\|db_high\[1\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~12\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~12\|combout " "Node \"z80_\|alu_\|db_high\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~12\|datab " "Node \"z80_\|alu_\|db\[5\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~12\|combout " "Node \"z80_\|alu_\|db\[5\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|datab " "Node \"z80_\|alu_control_\|db\[5\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|combout " "Node \"z80_\|alu_control_\|db\[5\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~69\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~69\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~69\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~69\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|datac " "Node \"z80_\|alu_control_\|db\[5\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|combout " "Node \"z80_\|alu_control_\|db\[5\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~11\|datab " "Node \"z80_\|alu_\|db\[5\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~11\|combout " "Node \"z80_\|alu_\|db\[5\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~12\|dataa " "Node \"z80_\|alu_\|db\[5\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|datab " "Node \"z80_\|bus_control_\|db\[5\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|combout " "Node \"z80_\|bus_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|dataa " "Node \"z80_\|sw1_\|db_down\[5\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|combout " "Node \"z80_\|sw1_\|db_down\[5\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~16\|datab " "Node \"z80_\|alu_\|db_high\[3\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~16\|combout " "Node \"z80_\|alu_\|db_high\[3\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~17\|datab " "Node \"z80_\|alu_\|db_high\[3\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~17\|combout " "Node \"z80_\|alu_\|db_high\[3\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~24\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~24\|combout " "Node \"z80_\|alu_\|db_high\[3\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~10\|datab " "Node \"z80_\|alu_\|db\[7\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~10\|combout " "Node \"z80_\|alu_\|db\[7\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~14\|datab " "Node \"z80_\|alu_\|db_high\[3\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~14\|combout " "Node \"z80_\|alu_\|db_high\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~17\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~0\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~0\|combout " "Node \"z80_\|alu_\|db_high\[2\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~1\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~1\|combout " "Node \"z80_\|alu_\|db_high\[2\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~4\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~4\|combout " "Node \"z80_\|alu_\|db_high\[2\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~25\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~25\|combout " "Node \"z80_\|alu_\|db_high\[2\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~14\|datab " "Node \"z80_\|alu_\|db\[6\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~14\|combout " "Node \"z80_\|alu_\|db\[6\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~13\|datab " "Node \"z80_\|alu_\|db_high\[3\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~13\|combout " "Node \"z80_\|alu_\|db_high\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~14\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~1\|datab " "Node \"z80_\|alu_\|db_high\[2\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~5\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~17\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~17\|combout " "Node \"z80_\|alu_control_\|db\[6\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|datad " "Node \"z80_\|alu_control_\|db\[6\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|combout " "Node \"z80_\|alu_control_\|db\[6\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~19\|datad " "Node \"z80_\|alu_control_\|db\[6\]~19\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~19\|combout " "Node \"z80_\|alu_control_\|db\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|datab " "Node \"z80_\|bus_control_\|db\[6\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|combout " "Node \"z80_\|bus_control_\|db\[6\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|dataa " "Node \"z80_\|bus_control_\|db\[6\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|combout " "Node \"z80_\|bus_control_\|db\[6\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~78\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~78\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~78\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~78\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~19\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~13\|dataa " "Node \"z80_\|alu_\|db\[6\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~13\|combout " "Node \"z80_\|alu_\|db\[6\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~14\|dataa " "Node \"z80_\|alu_\|db\[6\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~13\|datab " "Node \"z80_\|alu_\|db\[6\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~18\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~13\|datac " "Node \"z80_\|alu_control_\|db\[7\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~13\|combout " "Node \"z80_\|alu_control_\|db\[7\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|datac " "Node \"z80_\|alu_control_\|db\[7\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|combout " "Node \"z80_\|alu_control_\|db\[7\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|datab " "Node \"z80_\|bus_control_\|db\[7\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|combout " "Node \"z80_\|bus_control_\|db\[7\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|dataa " "Node \"z80_\|bus_control_\|db\[7\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|combout " "Node \"z80_\|bus_control_\|db\[7\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|combout " "Node \"z80_\|alu_control_\|db\[7\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|datad " "Node \"z80_\|alu_control_\|db\[7\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~88\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~88\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~88\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~88\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|datad " "Node \"z80_\|alu_control_\|db\[7\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~8\|dataa " "Node \"z80_\|alu_\|db\[7\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~8\|combout " "Node \"z80_\|alu_\|db\[7\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~10\|dataa " "Node \"z80_\|alu_\|db\[7\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~13\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datab " "Node \"z80_\|alu_\|db_low\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|combout " "Node \"z80_\|alu_\|db_low\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|combout " "Node \"z80_\|alu_\|db_low\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datab " "Node \"z80_\|alu_\|db_low\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|combout " "Node \"z80_\|alu_\|db_low\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|datab " "Node \"z80_\|alu_\|db\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|combout " "Node \"z80_\|alu_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|dataa " "Node \"z80_\|alu_\|db\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|combout " "Node \"z80_\|alu_\|db\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|dataa " "Node \"z80_\|sw2_\|db_up\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|combout " "Node \"z80_\|sw2_\|db_up\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|combout " "Node \"z80_\|alu_control_\|db\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~26\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~26\|combout " "Node \"z80_\|alu_control_\|db\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|datac " "Node \"z80_\|alu_control_\|db\[0\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datab " "Node \"z80_\|alu_\|db\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|datab " "Node \"z80_\|bus_control_\|db\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|combout " "Node \"z80_\|bus_control_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~24\|datab " "Node \"z80_\|alu_control_\|db\[0\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~24\|combout " "Node \"z80_\|alu_control_\|db\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|datab " "Node \"z80_\|alu_control_\|db\[0\]~25\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|dataa " "Node \"z80_\|alu_\|db\[0\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datab " "Node \"z80_\|alu_\|db_low\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|combout " "Node \"z80_\|alu_\|db_low\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|combout " "Node \"z80_\|alu_\|db_low\[1\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|combout " "Node \"z80_\|alu_\|db_low\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~24\|datab " "Node \"z80_\|alu_\|db\[1\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~24\|combout " "Node \"z80_\|alu_\|db\[1\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~21\|datac " "Node \"z80_\|alu_control_\|db\[1\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~21\|combout " "Node \"z80_\|alu_control_\|db\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~23\|datac " "Node \"z80_\|alu_control_\|db\[1\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~23\|combout " "Node \"z80_\|alu_control_\|db\[1\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|datab " "Node \"z80_\|bus_control_\|db\[1\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|combout " "Node \"z80_\|bus_control_\|db\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|dataa " "Node \"z80_\|bus_control_\|db\[1\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|combout " "Node \"z80_\|bus_control_\|db\[1\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|combout " "Node \"z80_\|alu_control_\|db\[1\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~23\|datad " "Node \"z80_\|alu_control_\|db\[1\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~23\|dataa " "Node \"z80_\|alu_\|db\[1\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~23\|combout " "Node \"z80_\|alu_\|db\[1\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~24\|dataa " "Node \"z80_\|alu_\|db\[1\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|datad " "Node \"z80_\|alu_control_\|db\[1\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|datab " "Node \"z80_\|alu_\|db_low\[1\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|datab " "Node \"z80_\|alu_\|db_low\[2\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|combout " "Node \"z80_\|alu_\|db_low\[2\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|combout " "Node \"z80_\|alu_\|db_low\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|combout " "Node \"z80_\|alu_\|db_low\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~20\|datab " "Node \"z80_\|alu_\|db\[2\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~20\|combout " "Node \"z80_\|alu_\|db\[2\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|datac " "Node \"z80_\|alu_control_\|db\[2\]~27\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|combout " "Node \"z80_\|alu_control_\|db\[2\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datac " "Node \"z80_\|alu_control_\|db\[2\]~29\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|combout " "Node \"z80_\|alu_control_\|db\[2\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|datab " "Node \"z80_\|bus_control_\|db\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|combout " "Node \"z80_\|bus_control_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|dataa " "Node \"z80_\|bus_control_\|db\[2\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|combout " "Node \"z80_\|bus_control_\|db\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~28\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|combout " "Node \"z80_\|alu_control_\|db\[2\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datad " "Node \"z80_\|alu_control_\|db\[2\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|datad " "Node \"z80_\|alu_control_\|db\[2\]~28\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~19\|dataa " "Node \"z80_\|alu_\|db\[2\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~19\|combout " "Node \"z80_\|alu_\|db\[2\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~20\|dataa " "Node \"z80_\|alu_\|db\[2\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~10\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~19\|datab " "Node \"z80_\|alu_\|db\[2\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|datab " "Node \"z80_\|alu_\|db_low\[2\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|datab " "Node \"z80_\|alu_\|db_low\[3\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|combout " "Node \"z80_\|alu_\|db_low\[3\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|combout " "Node \"z80_\|alu_\|db_low\[3\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|combout " "Node \"z80_\|alu_\|db_low\[3\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|combout " "Node \"z80_\|alu_\|db_low\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~21\|datab " "Node \"z80_\|alu_\|db\[3\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~21\|combout " "Node \"z80_\|alu_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~22\|dataa " "Node \"z80_\|alu_\|db\[3\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~22\|combout " "Node \"z80_\|alu_\|db\[3\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datab " "Node \"z80_\|alu_control_\|db\[3\]~35\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|datac " "Node \"z80_\|alu_control_\|db\[3\]~34\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|combout " "Node \"z80_\|alu_control_\|db\[3\]~34\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~22\|datab " "Node \"z80_\|alu_\|db\[3\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|datab " "Node \"z80_\|bus_control_\|db\[3\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|combout " "Node \"z80_\|bus_control_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~1\|dataa " "Node \"z80_\|sw1_\|db_down\[3\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~1\|combout " "Node \"z80_\|sw1_\|db_down\[3\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~34\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|datac " "Node \"z80_\|alu_\|db_high\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datac " "Node \"z80_\|alu_\|db_low\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|combout " "Node \"z80_\|alu_\|db_low\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|combout " "Node \"z80_\|alu_\|db_low\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|combout " "Node \"z80_\|alu_\|db_low\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|combout " "Node \"z80_\|alu_\|db_low\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datab " "Node \"z80_\|alu_\|db_low\[1\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~3\|datac " "Node \"z80_\|alu_\|db_high\[2\]~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~3\|combout " "Node \"z80_\|alu_\|db_high\[2\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~4\|datab " "Node \"z80_\|alu_\|db_high\[2\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|datab " "Node \"z80_\|alu_\|db_low\[2\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|combout " "Node \"z80_\|alu_\|db_low\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|datac " "Node \"z80_\|alu_\|db_low\[2\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|datab " "Node \"z80_\|alu_\|db_high\[1\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|combout " "Node \"z80_\|alu_\|db_high\[1\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~9\|datac " "Node \"z80_\|alu_\|db_high\[1\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~16\|datac " "Node \"z80_\|alu_\|db_high\[3\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|datab " "Node \"z80_\|alu_\|db_low\[3\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|combout " "Node \"z80_\|alu_\|db_low\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|datab " "Node \"z80_\|alu_\|db_low\[3\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datab " "Node \"z80_\|alu_\|db_high\[0\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|combout " "Node \"z80_\|alu_\|db_high\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|datab " "Node \"z80_\|alu_\|db_low\[3\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~21\|dataa " "Node \"z80_\|alu_\|db\[3\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~7\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~23\|datab " "Node \"z80_\|alu_\|db\[1\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datab " "Node \"z80_\|alu_\|db_low\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~64\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~64\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~65\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~65\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~8\|datab " "Node \"z80_\|alu_\|db\[7\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~16\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~17\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~23\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~3\|datab " "Node \"z80_\|alu_\|db_high\[2\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|datab " "Node \"z80_\|alu_\|db_low\[1\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|datac " "Node \"z80_\|alu_\|db_low\[2\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|datac " "Node \"z80_\|alu_\|db_low\[3\]~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~0\|datab " "Node \"z80_\|alu_\|db_high\[2\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~80\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~80\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~82\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~82\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~83\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~83\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~20\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~21\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~22\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~11\|dataa " "Node \"z80_\|alu_\|db\[5\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~6\|datab " "Node \"z80_\|alu_\|db_high\[1\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|combout " "Node \"z80_\|alu_control_\|db\[4\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~15\|datab " "Node \"z80_\|alu_\|db\[4\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|combout " "Node \"z80_\|alu_control_\|db\[4\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datad " "Node \"z80_\|alu_control_\|db\[4\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datad " "Node \"z80_\|alu_control_\|db\[4\]~32\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|datab " "Node \"z80_\|bus_control_\|db\[4\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datab " "Node \"z80_\|alu_\|db_low\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|datac " "Node \"z80_\|alu_\|db_low\[1\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|datad " "Node \"z80_\|alu_\|db_high\[1\]~8\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datab " "Node \"z80_\|alu_control_\|db\[4\]~31\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 31 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 30 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Fitter" 0 -1 1648899792360 ""} +{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "507 " "Design contains combinational loop of 507 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Fitter" 0 -1 1648899792376 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648899792410 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648899792410 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1648899792425 ""} +{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1648899792427 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 7 clocks " "Found 7 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 beep " " 10.000 beep" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1648899792427 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G15 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792619 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5089 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792619 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1) " "Automatically promoted node sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792619 ""} } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1261 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792619 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C0 of PLL_1) " "Automatically promoted node sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792619 ""} { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations External Clock Output CLKCTRL_PLL1E0 " "Automatically promoted destinations to use location or clock signal External Clock Output CLKCTRL_PLL1E0" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792619 ""} } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1261 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792619 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1229 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792620 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1229 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792620 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1229 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792620 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|clocks:clocks_\|clk_cpu " "Automatically promoted node ula:ula_\|clocks:clocks_\|clk_cpu " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ula:ula_\|clocks:clocks_\|clk_cpu~0 " "Destination node ula:ula_\|clocks:clocks_\|clk_cpu~0" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 2809 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1227 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792620 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset " "Automatically promoted node reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "z80_top_direct_n:z80_\|resets:resets_\|x1~0 " "Destination node z80_top_direct_n:z80_\|resets:resets_\|x1~0" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|x1~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4150 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 73 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1471 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792620 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[30\]~output " "Destination node GPIO_1\[30\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4185 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[0\]~output " "Destination node GPIO_1\[0\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4158 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[1\]~output " "Destination node GPIO_1\[1\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4159 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[2\]~output " "Destination node GPIO_1\[2\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4160 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[3\]~output " "Destination node GPIO_1\[3\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4161 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[4\]~output " "Destination node GPIO_1\[4\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4162 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[5\]~output " "Destination node GPIO_1\[5\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4163 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[6\]~output " "Destination node GPIO_1\[6\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4164 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[7\]~output " "Destination node GPIO_1\[7\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4165 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[8\]~output " "Destination node GPIO_1\[8\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4166 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 683 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792620 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|fpga_reset " "Automatically promoted node z80_top_direct_n:z80_\|fpga_reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792621 ""} } { { "cpu/toplevel/core.vh" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 13 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|fpga_reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 917 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792621 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792621 ""} } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 76 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 754 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792621 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648899793449 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648899793453 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648899793453 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648899793457 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648899793462 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648899793466 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648899793466 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648899793469 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648899794289 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "8 I/O Input Buffer " "Packed 8 registers into blocks of type I/O Input Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1648899794293 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "29 I/O Output Buffer " "Packed 29 registers into blocks of type I/O Output Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1648899794293 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "15 " "Created 15 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "Quartus II" 0 -1 1648899794293 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648899794293 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648899794431 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648899794433 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648899795941 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648899796762 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648899796784 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648899799543 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648899799543 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648899800437 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "4 " "Router estimated average interconnect usage is 4% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "21 X21_Y11 X31_Y22 " "Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22" { } { { "loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 1 { 0 "Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} 21 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648899803211 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648899803211 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:05 " "Fitter routing operations ending: elapsed time is 00:00:05" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648899805930 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648899805932 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648899805932 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "1.88 " "Total time spent on timing analysis during the Fitter is 1.88 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648899806074 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648899806133 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648899806898 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648899806949 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648899807650 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648899808810 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648899809279 ""} +{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "57 Cyclone IV E " "57 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[0\] 3.3-V LVTTL M1 " "Pin SW\[0\] uses I/O standard 3.3-V LVTTL at M1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 149 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[3\] 3.3-V LVTTL M15 " "Pin SW\[3\] uses I/O standard 3.3-V LVTTL at M15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 152 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[0\] 3.3-V LVTTL F13 " "Pin GPIO_1\[0\] uses I/O standard 3.3-V LVTTL at F13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 153 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[1\] 3.3-V LVTTL T15 " "Pin GPIO_1\[1\] uses I/O standard 3.3-V LVTTL at T15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 154 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[2\] 3.3-V LVTTL T14 " "Pin GPIO_1\[2\] uses I/O standard 3.3-V LVTTL at T14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 155 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[3\] 3.3-V LVTTL T13 " "Pin GPIO_1\[3\] uses I/O standard 3.3-V LVTTL at T13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 156 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[4\] 3.3-V LVTTL R13 " "Pin GPIO_1\[4\] uses I/O standard 3.3-V LVTTL at R13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[4] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 157 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[5\] 3.3-V LVTTL T12 " "Pin GPIO_1\[5\] uses I/O standard 3.3-V LVTTL at T12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[5] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 158 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[6\] 3.3-V LVTTL R12 " "Pin GPIO_1\[6\] uses I/O standard 3.3-V LVTTL at R12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[6] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 159 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[7\] 3.3-V LVTTL T11 " "Pin GPIO_1\[7\] uses I/O standard 3.3-V LVTTL at T11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[7] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 160 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[8\] 3.3-V LVTTL T10 " "Pin GPIO_1\[8\] uses I/O standard 3.3-V LVTTL at T10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[8] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 161 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[9\] 3.3-V LVTTL R11 " "Pin GPIO_1\[9\] uses I/O standard 3.3-V LVTTL at R11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[9] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 162 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[10\] 3.3-V LVTTL P11 " "Pin GPIO_1\[10\] uses I/O standard 3.3-V LVTTL at P11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[10] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 163 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[11\] 3.3-V LVTTL R10 " "Pin GPIO_1\[11\] uses I/O standard 3.3-V LVTTL at R10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[11] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 164 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[12\] 3.3-V LVTTL N12 " "Pin GPIO_1\[12\] uses I/O standard 3.3-V LVTTL at N12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[12] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 165 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[13\] 3.3-V LVTTL P9 " "Pin GPIO_1\[13\] uses I/O standard 3.3-V LVTTL at P9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[13] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 166 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[14\] 3.3-V LVTTL N9 " "Pin GPIO_1\[14\] uses I/O standard 3.3-V LVTTL at N9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[14] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 167 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[15\] 3.3-V LVTTL N11 " "Pin GPIO_1\[15\] uses I/O standard 3.3-V LVTTL at N11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[15] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 168 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[16\] 3.3-V LVTTL L16 " "Pin GPIO_1\[16\] uses I/O standard 3.3-V LVTTL at L16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[16] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 169 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[17\] 3.3-V LVTTL K16 " "Pin GPIO_1\[17\] uses I/O standard 3.3-V LVTTL at K16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[17] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 170 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[18\] 3.3-V LVTTL R16 " "Pin GPIO_1\[18\] uses I/O standard 3.3-V LVTTL at R16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[18] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 171 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[19\] 3.3-V LVTTL L15 " "Pin GPIO_1\[19\] uses I/O standard 3.3-V LVTTL at L15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[19] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 172 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[20\] 3.3-V LVTTL P15 " "Pin GPIO_1\[20\] uses I/O standard 3.3-V LVTTL at P15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[20] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 173 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[21\] 3.3-V LVTTL P16 " "Pin GPIO_1\[21\] uses I/O standard 3.3-V LVTTL at P16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[21] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 174 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[22\] 3.3-V LVTTL R14 " "Pin GPIO_1\[22\] uses I/O standard 3.3-V LVTTL at R14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[22] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 175 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[23\] 3.3-V LVTTL N16 " "Pin GPIO_1\[23\] uses I/O standard 3.3-V LVTTL at N16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[23] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 176 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[27\] 3.3-V LVTTL N14 " "Pin GPIO_1\[27\] uses I/O standard 3.3-V LVTTL at N14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[27] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 180 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[28\] 3.3-V LVTTL M10 " "Pin GPIO_1\[28\] uses I/O standard 3.3-V LVTTL at M10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[28] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 181 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[29\] 3.3-V LVTTL L13 " "Pin GPIO_1\[29\] uses I/O standard 3.3-V LVTTL at L13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[29] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 182 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[30\] 3.3-V LVTTL J16 " "Pin GPIO_1\[30\] uses I/O standard 3.3-V LVTTL at J16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[30] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 183 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SCLK 3.3-V LVTTL F2 " "Pin I2C_SCLK uses I/O standard 3.3-V LVTTL at F2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SCLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 6 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SCLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 223 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SDAT 3.3-V LVTTL F1 " "Pin I2C_SDAT uses I/O standard 3.3-V LVTTL at F1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 7 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 224 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[0\] 3.3-V LVTTL G2 " "Pin DRAM_DQ\[0\] uses I/O standard 3.3-V LVTTL at G2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 191 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[1\] 3.3-V LVTTL G1 " "Pin DRAM_DQ\[1\] uses I/O standard 3.3-V LVTTL at G1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 192 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[2\] 3.3-V LVTTL L8 " "Pin DRAM_DQ\[2\] uses I/O standard 3.3-V LVTTL at L8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 193 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[3\] 3.3-V LVTTL K5 " "Pin DRAM_DQ\[3\] uses I/O standard 3.3-V LVTTL at K5" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 194 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[4\] 3.3-V LVTTL K2 " "Pin DRAM_DQ\[4\] uses I/O standard 3.3-V LVTTL at K2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[4] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 195 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[5\] 3.3-V LVTTL J2 " "Pin DRAM_DQ\[5\] uses I/O standard 3.3-V LVTTL at J2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[5] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 196 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[6\] 3.3-V LVTTL J1 " "Pin DRAM_DQ\[6\] uses I/O standard 3.3-V LVTTL at J1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[6] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 197 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[7\] 3.3-V LVTTL R7 " "Pin DRAM_DQ\[7\] uses I/O standard 3.3-V LVTTL at R7" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[7] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 198 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[8\] 3.3-V LVTTL T4 " "Pin DRAM_DQ\[8\] uses I/O standard 3.3-V LVTTL at T4" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[8] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 199 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[9\] 3.3-V LVTTL T2 " "Pin DRAM_DQ\[9\] uses I/O standard 3.3-V LVTTL at T2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[9] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 200 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[10\] 3.3-V LVTTL T3 " "Pin DRAM_DQ\[10\] uses I/O standard 3.3-V LVTTL at T3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[10] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 201 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[11\] 3.3-V LVTTL R3 " "Pin DRAM_DQ\[11\] uses I/O standard 3.3-V LVTTL at R3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[11] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 202 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[12\] 3.3-V LVTTL R5 " "Pin DRAM_DQ\[12\] uses I/O standard 3.3-V LVTTL at R5" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[12] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 203 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[13\] 3.3-V LVTTL P3 " "Pin DRAM_DQ\[13\] uses I/O standard 3.3-V LVTTL at P3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[13] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 204 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[14\] 3.3-V LVTTL N3 " "Pin DRAM_DQ\[14\] uses I/O standard 3.3-V LVTTL at N3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[14] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 205 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[15\] 3.3-V LVTTL K1 " "Pin DRAM_DQ\[15\] uses I/O standard 3.3-V LVTTL at K1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[15] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 206 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[1\] 3.3-V LVTTL T8 " "Pin SW\[1\] uses I/O standard 3.3-V LVTTL at T8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 150 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[2\] 3.3-V LVTTL B9 " "Pin SW\[2\] uses I/O standard 3.3-V LVTTL at B9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 151 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "raw_loader_in 3.3-V LVTTL B6 " "Pin raw_loader_in uses I/O standard 3.3-V LVTTL at B6" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { raw_loader_in } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "raw_loader_in" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 22 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { raw_loader_in } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 234 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[0\] 3.3-V LVTTL J15 " "Pin KEY\[0\] uses I/O standard 3.3-V LVTTL at J15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 135 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 220 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[1\] 3.3-V LVTTL E1 " "Pin KEY\[1\] uses I/O standard 3.3-V LVTTL at E1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 136 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_DAT 3.3-V LVTTL B7 " "Pin PS2_DAT uses I/O standard 3.3-V LVTTL at B7" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_DAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 5 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_DAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 222 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_CLK 3.3-V LVTTL D6 " "Pin PS2_CLK uses I/O standard 3.3-V LVTTL at D6" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_CLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 4 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 221 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "AUD_ADCDAT 3.3-V LVTTL D8 " "Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { AUD_ADCDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 13 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { AUD_ADCDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 230 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648899809297 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648899809632 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 568 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 568 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "639 " "Peak virtual memory: 639 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648899810355 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:43:30 2022 " "Processing ended: Sat Apr 2 14:43:30 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648899810355 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:20 " "Elapsed time: 00:00:20" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648899810355 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:20 " "Total CPU time (on all processors): 00:00:20" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648899810355 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648899810355 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1648899812346 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648899812347 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:43:32 2022 " "Processing started: Sat Apr 2 14:43:32 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648899812347 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648899812347 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648899812347 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648899813443 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648899813473 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "375 " "Peak virtual memory: 375 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648899813776 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:43:33 2022 " "Processing ended: Sat Apr 2 14:43:33 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648899813776 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648899813776 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648899813776 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648899813776 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1648899814393 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1648899815598 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648899815599 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:43:35 2022 " "Processing started: Sat Apr 2 14:43:35 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648899815599 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648899815599 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648899815599 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648899815626 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648899815806 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648899815807 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648899815847 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648899815848 ""} +{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1648899816257 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648899816265 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816266 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1648899816266 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Quartus II" 0 -1 1648899816268 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648899816269 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648899816269 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648899816269 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648899816269 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648899816269 ""} +{ "Warning" "WSTA_SCC_LOOP" "507 " "Found combinational loop of 507 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|combout " "Node \"z80_\|bus_control_\|db\[1\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|datad " "Node \"z80_\|alu_control_\|db\[1\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|combout " "Node \"z80_\|alu_control_\|db\[1\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~23\|datac " "Node \"z80_\|alu_control_\|db\[1\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~23\|combout " "Node \"z80_\|alu_control_\|db\[1\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~23\|dataa " "Node \"z80_\|alu_\|db\[1\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~23\|combout " "Node \"z80_\|alu_\|db\[1\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~24\|datab " "Node \"z80_\|alu_\|db\[1\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~24\|combout " "Node \"z80_\|alu_\|db\[1\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|datac " "Node \"z80_\|alu_\|db_low\[1\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|combout " "Node \"z80_\|alu_\|db_low\[1\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datac " "Node \"z80_\|alu_\|db_low\[1\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|combout " "Node \"z80_\|alu_\|db_low\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~24\|datac " "Node \"z80_\|alu_\|db\[1\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datab " "Node \"z80_\|alu_\|db_low\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|combout " "Node \"z80_\|alu_\|db_low\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datad " "Node \"z80_\|alu_\|db_low\[0\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|combout " "Node \"z80_\|alu_\|db_low\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|combout " "Node \"z80_\|alu_\|db_low\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|datac " "Node \"z80_\|alu_\|db\[0\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|combout " "Node \"z80_\|alu_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datab " "Node \"z80_\|alu_\|db\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|combout " "Node \"z80_\|alu_\|db\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|datac " "Node \"z80_\|sw2_\|db_up\[0\]~0\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|combout " "Node \"z80_\|sw2_\|db_up\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|combout " "Node \"z80_\|alu_control_\|db\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~26\|datad " "Node \"z80_\|alu_control_\|db\[0\]~26\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~26\|combout " "Node \"z80_\|alu_control_\|db\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|dataa " "Node \"z80_\|alu_\|db\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|datac " "Node \"z80_\|alu_control_\|db\[0\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|datad " "Node \"z80_\|bus_control_\|db\[0\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|combout " "Node \"z80_\|bus_control_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~24\|datad " "Node \"z80_\|alu_control_\|db\[0\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~24\|combout " "Node \"z80_\|alu_control_\|db\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~25\|datab " "Node \"z80_\|alu_control_\|db\[0\]~25\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datac " "Node \"z80_\|alu_\|db_low\[0\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|dataa " "Node \"z80_\|alu_\|db\[0\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datad " "Node \"z80_\|alu_\|db_low\[0\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~13\|datad " "Node \"z80_\|alu_\|db_high\[3\]~13\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~13\|combout " "Node \"z80_\|alu_\|db_high\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~14\|datab " "Node \"z80_\|alu_\|db_high\[3\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~14\|combout " "Node \"z80_\|alu_\|db_high\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~17\|datad " "Node \"z80_\|alu_\|db_high\[3\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~17\|combout " "Node \"z80_\|alu_\|db_high\[3\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~24\|datad " "Node \"z80_\|alu_\|db_high\[3\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~24\|combout " "Node \"z80_\|alu_\|db_high\[3\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~10\|datac " "Node \"z80_\|alu_\|db\[7\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~10\|combout " "Node \"z80_\|alu_\|db\[7\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~0\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~0\|combout " "Node \"z80_\|alu_\|db_high\[2\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~1\|datad " "Node \"z80_\|alu_\|db_high\[2\]~1\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~1\|combout " "Node \"z80_\|alu_\|db_high\[2\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~4\|datad " "Node \"z80_\|alu_\|db_high\[2\]~4\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~4\|combout " "Node \"z80_\|alu_\|db_high\[2\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~25\|datad " "Node \"z80_\|alu_\|db_high\[2\]~25\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~25\|combout " "Node \"z80_\|alu_\|db_high\[2\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~14\|datac " "Node \"z80_\|alu_\|db\[6\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~14\|combout " "Node \"z80_\|alu_\|db\[6\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~1\|datac " "Node \"z80_\|alu_\|db_high\[2\]~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~5\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~5\|combout " "Node \"z80_\|alu_\|db_high\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~6\|datab " "Node \"z80_\|alu_\|db_high\[1\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~6\|combout " "Node \"z80_\|alu_\|db_high\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~9\|datac " "Node \"z80_\|alu_\|db_high\[1\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~9\|combout " "Node \"z80_\|alu_\|db_high\[1\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~12\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~12\|combout " "Node \"z80_\|alu_\|db_high\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~12\|datac " "Node \"z80_\|alu_\|db\[5\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~12\|combout " "Node \"z80_\|alu_\|db\[5\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~6\|datad " "Node \"z80_\|alu_\|db_high\[1\]~6\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|datac " "Node \"z80_\|alu_control_\|db\[5\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|combout " "Node \"z80_\|alu_control_\|db\[5\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|datac " "Node \"z80_\|bus_control_\|db\[5\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|combout " "Node \"z80_\|bus_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~3\|datab " "Node \"z80_\|alu_\|db_high\[2\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~3\|combout " "Node \"z80_\|alu_\|db_high\[2\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~4\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|datab " "Node \"z80_\|alu_\|db_high\[1\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|combout " "Node \"z80_\|alu_\|db_high\[1\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~9\|datab " "Node \"z80_\|alu_\|db_high\[1\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~16\|datac " "Node \"z80_\|alu_\|db_high\[3\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~16\|combout " "Node \"z80_\|alu_\|db_high\[3\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~17\|datab " "Node \"z80_\|alu_\|db_high\[3\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|dataa " "Node \"z80_\|sw1_\|db_down\[5\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|combout " "Node \"z80_\|sw1_\|db_down\[5\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|datac " "Node \"z80_\|alu_control_\|db\[5\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|combout " "Node \"z80_\|alu_control_\|db\[5\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~12\|datab " "Node \"z80_\|alu_control_\|db\[5\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|datab " "Node \"z80_\|alu_\|db_low\[2\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|combout " "Node \"z80_\|alu_\|db_low\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|combout " "Node \"z80_\|alu_\|db_low\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~20\|datab " "Node \"z80_\|alu_\|db\[2\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~20\|combout " "Node \"z80_\|alu_\|db\[2\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|combout " "Node \"z80_\|alu_\|db_low\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|datad " "Node \"z80_\|alu_\|db_low\[1\]~13\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|datac " "Node \"z80_\|alu_\|db_low\[2\]~7\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|combout " "Node \"z80_\|alu_\|db_low\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~11\|datac " "Node \"z80_\|alu_\|db_low\[2\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|combout " "Node \"z80_\|alu_\|db_low\[3\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|datad " "Node \"z80_\|alu_\|db_low\[3\]~1\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|combout " "Node \"z80_\|alu_\|db_low\[3\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|combout " "Node \"z80_\|alu_\|db_low\[3\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|datad " "Node \"z80_\|alu_\|db_low\[3\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|combout " "Node \"z80_\|alu_\|db_low\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~21\|datac " "Node \"z80_\|alu_\|db\[3\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~21\|combout " "Node \"z80_\|alu_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~22\|datab " "Node \"z80_\|alu_\|db\[3\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~22\|combout " "Node \"z80_\|alu_\|db\[3\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datab " "Node \"z80_\|alu_control_\|db\[3\]~35\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|datab " "Node \"z80_\|bus_control_\|db\[3\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|combout " "Node \"z80_\|bus_control_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|datac " "Node \"z80_\|alu_\|db_high\[1\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~1\|dataa " "Node \"z80_\|sw1_\|db_down\[3\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~1\|combout " "Node \"z80_\|sw1_\|db_down\[3\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~34\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|combout " "Node \"z80_\|alu_control_\|db\[3\]~34\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datad " "Node \"z80_\|alu_control_\|db\[3\]~35\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|datac " "Node \"z80_\|alu_\|db_high\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|combout " "Node \"z80_\|alu_\|db_high\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|datab " "Node \"z80_\|alu_\|db_high\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|combout " "Node \"z80_\|alu_\|db_high\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datac " "Node \"z80_\|alu_\|db_high\[0\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|combout " "Node \"z80_\|alu_\|db_high\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|datac " "Node \"z80_\|alu_\|db\[4\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|combout " "Node \"z80_\|alu_\|db\[4\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~53\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~53\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~55\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~55\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~56\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~56\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~15\|datab " "Node \"z80_\|alu_\|db\[4\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~15\|combout " "Node \"z80_\|alu_\|db\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|datab " "Node \"z80_\|alu_\|db\[4\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~14\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~15\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~5\|datad " "Node \"z80_\|alu_\|db_high\[1\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~0\|datad " "Node \"z80_\|alu_\|db_low\[3\]~0\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datad " "Node \"z80_\|alu_\|db_high\[0\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|combout " "Node \"z80_\|alu_\|db_high\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datad " "Node \"z80_\|alu_control_\|db\[4\]~32\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|combout " "Node \"z80_\|alu_control_\|db\[4\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~15\|dataa " "Node \"z80_\|alu_\|db\[4\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|datad " "Node \"z80_\|alu_control_\|db\[4\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|combout " "Node \"z80_\|alu_control_\|db\[4\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datad " "Node \"z80_\|alu_control_\|db\[4\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datab " "Node \"z80_\|alu_control_\|db\[4\]~32\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|datac " "Node \"z80_\|bus_control_\|db\[4\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|combout " "Node \"z80_\|bus_control_\|db\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datab " "Node \"z80_\|alu_control_\|db\[4\]~31\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~8\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|combout " "Node \"z80_\|alu_\|db_low\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|datad " "Node \"z80_\|alu_\|db_low\[0\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|combout " "Node \"z80_\|alu_\|db_low\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datad " "Node \"z80_\|alu_\|db_low\[0\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|combout " "Node \"z80_\|alu_\|db_low\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|datab " "Node \"z80_\|alu_\|db_low\[1\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|combout " "Node \"z80_\|alu_\|db_low\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datad " "Node \"z80_\|alu_\|db_low\[1\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~3\|datac " "Node \"z80_\|alu_\|db_high\[2\]~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|datac " "Node \"z80_\|alu_\|db_low\[2\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~16\|datab " "Node \"z80_\|alu_\|db_high\[3\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|datab " "Node \"z80_\|alu_\|db_low\[3\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|combout " "Node \"z80_\|alu_\|db_low\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|datab " "Node \"z80_\|alu_\|db_low\[3\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datac " "Node \"z80_\|alu_\|db_low\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|datac " "Node \"z80_\|alu_\|db_low\[1\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datac " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datac " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|datad " "Node \"z80_\|alu_control_\|db\[3\]~34\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~22\|datad " "Node \"z80_\|alu_\|db\[3\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|datab " "Node \"z80_\|alu_\|db_low\[2\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|combout " "Node \"z80_\|alu_\|db_low\[2\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~7\|datad " "Node \"z80_\|alu_\|db_low\[2\]~7\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~1\|datac " "Node \"z80_\|alu_\|db_low\[3\]~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~21\|datab " "Node \"z80_\|alu_\|db\[3\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~7\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datab " "Node \"z80_\|alu_\|db_high\[0\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|combout " "Node \"z80_\|alu_\|db_high\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datab " "Node \"z80_\|alu_\|db_high\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~10\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~19\|datad " "Node \"z80_\|alu_\|db\[2\]~19\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~19\|combout " "Node \"z80_\|alu_\|db\[2\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~20\|datac " "Node \"z80_\|alu_\|db\[2\]~20\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~27\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|combout " "Node \"z80_\|alu_control_\|db\[2\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datac " "Node \"z80_\|alu_control_\|db\[2\]~29\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|combout " "Node \"z80_\|alu_control_\|db\[2\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|datac " "Node \"z80_\|bus_control_\|db\[2\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|combout " "Node \"z80_\|bus_control_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|datab " "Node \"z80_\|bus_control_\|db\[2\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|combout " "Node \"z80_\|bus_control_\|db\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|datad " "Node \"z80_\|alu_control_\|db\[2\]~28\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|combout " "Node \"z80_\|alu_control_\|db\[2\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datab " "Node \"z80_\|alu_control_\|db\[2\]~29\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~19\|datab " "Node \"z80_\|alu_\|db\[2\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|datad " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|datab " "Node \"z80_\|alu_control_\|db\[2\]~28\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~3\|datad " "Node \"z80_\|alu_\|db_low\[3\]~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|datab " "Node \"z80_\|alu_\|db_high\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datab " "Node \"z80_\|alu_\|db_low\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|datab " "Node \"z80_\|alu_\|db_low\[1\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~11\|datad " "Node \"z80_\|alu_\|db\[5\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~11\|combout " "Node \"z80_\|alu_\|db\[5\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~12\|datab " "Node \"z80_\|alu_\|db\[5\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~69\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~69\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~69\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~69\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~9\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~80\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~80\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~82\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~82\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~83\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~83\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~11\|datab " "Node \"z80_\|alu_\|db\[5\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~20\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~21\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~22\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datad " "Node \"z80_\|alu_\|db_high\[0\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~0\|datad " "Node \"z80_\|alu_\|db_high\[2\]~0\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~17\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~17\|combout " "Node \"z80_\|alu_control_\|db\[6\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|combout " "Node \"z80_\|alu_control_\|db\[6\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~19\|datac " "Node \"z80_\|alu_control_\|db\[6\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~19\|combout " "Node \"z80_\|alu_control_\|db\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|dataa " "Node \"z80_\|bus_control_\|db\[6\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|combout " "Node \"z80_\|bus_control_\|db\[6\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|datab " "Node \"z80_\|bus_control_\|db\[6\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|combout " "Node \"z80_\|bus_control_\|db\[6\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~18\|datab " "Node \"z80_\|alu_control_\|db\[6\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~78\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~78\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~78\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~78\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~19\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~13\|datab " "Node \"z80_\|alu_\|db\[6\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~13\|combout " "Node \"z80_\|alu_\|db\[6\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~14\|datab " "Node \"z80_\|alu_\|db\[6\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~18\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~19\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~19\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~13\|datad " "Node \"z80_\|alu_\|db\[6\]~13\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~13\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~64\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~64\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~65\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~65\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~16\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~17\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~23\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~8\|datac " "Node \"z80_\|alu_\|db\[7\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~8\|combout " "Node \"z80_\|alu_\|db\[7\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~10\|datab " "Node \"z80_\|alu_\|db\[7\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~14\|datad " "Node \"z80_\|alu_\|db_high\[3\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~13\|datab " "Node \"z80_\|alu_control_\|db\[7\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~13\|combout " "Node \"z80_\|alu_control_\|db\[7\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|datad " "Node \"z80_\|alu_control_\|db\[7\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|combout " "Node \"z80_\|alu_control_\|db\[7\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|dataa " "Node \"z80_\|bus_control_\|db\[7\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|combout " "Node \"z80_\|bus_control_\|db\[7\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|datab " "Node \"z80_\|bus_control_\|db\[7\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|combout " "Node \"z80_\|bus_control_\|db\[7\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|datad " "Node \"z80_\|alu_control_\|db\[7\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|combout " "Node \"z80_\|alu_control_\|db\[7\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~15\|datac " "Node \"z80_\|alu_control_\|db\[7\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~8\|datab " "Node \"z80_\|alu_\|db\[7\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~88\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~88\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~88\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~88\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~0\|datad " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~0\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~14\|datac " "Node \"z80_\|alu_control_\|db\[7\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datab " "Node \"z80_\|alu_\|db_low\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~21\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~21\|combout " "Node \"z80_\|alu_control_\|db\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~23\|datab " "Node \"z80_\|alu_control_\|db\[1\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|datac " "Node \"z80_\|alu_\|db_low\[2\]~6\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~23\|datab " "Node \"z80_\|alu_\|db\[1\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|datab " "Node \"z80_\|bus_control_\|db\[1\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|combout " "Node \"z80_\|bus_control_\|db\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|datac " "Node \"z80_\|bus_control_\|db\[1\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|datad " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|datab " "Node \"z80_\|alu_control_\|db\[1\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 30 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 31 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1648899816276 ""} +{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "507 " "Design contains combinational loop of 507 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Quartus II" 0 -1 1648899816292 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648899816322 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648899816322 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816452 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648899816455 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648899816475 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648899816506 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648899816506 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -18.375 " "Worst-case setup slack is -18.375" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -18.375 -543.462 CLOCK_50 " " -18.375 -543.462 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.723 -41.132 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.723 -41.132 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.035 -48.241 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -3.035 -48.241 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.914 -2.914 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.914 -2.914 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.057 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.057 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.477 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 3.477 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.953 " "Worst-case hold slack is -0.953" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.953 -14.699 CLOCK_50 " " -0.953 -14.699 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.358 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.358 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 7.936 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 7.936 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -6.224 " "Worst-case recovery slack is -6.224" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816513 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816513 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.224 -458.974 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -6.224 -458.974 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816513 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899816513 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.682 " "Worst-case removal slack is 3.682" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816514 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816514 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.682 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.682 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816514 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899816514 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.752 " "Worst-case minimum pulse width slack is 4.752" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.752 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.752 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.776 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 4.776 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.488 0.000 CLOCK_50 " " 9.488 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.603 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.603 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.593 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.593 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648899816659 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648899816695 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648899817630 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648899817793 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648899817793 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817795 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648899817812 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648899817812 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -17.547 " "Worst-case setup slack is -17.547" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -17.547 -513.385 CLOCK_50 " " -17.547 -513.385 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.416 -38.471 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.416 -38.471 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.785 -2.785 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.785 -2.785 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.660 -42.274 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -2.660 -42.274 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.134 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.134 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.130 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.130 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.767 " "Worst-case hold slack is -0.767" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.767 -11.715 CLOCK_50 " " -0.767 -11.715 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.312 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.312 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 7.928 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 7.928 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -5.744 " "Worst-case recovery slack is -5.744" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817828 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817828 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.744 -423.185 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -5.744 -423.185 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817828 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899817828 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.356 " "Worst-case removal slack is 3.356" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817832 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817832 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.356 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.356 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817832 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899817832 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.748 " "Worst-case minimum pulse width slack is 4.748" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.748 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.748 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.792 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 4.792 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.487 0.000 CLOCK_50 " " 9.487 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.598 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.598 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.588 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.588 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.491 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.491 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648899818028 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648899818319 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648899818319 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818321 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648899818328 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648899818328 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -15.145 " "Worst-case setup slack is -15.145" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -15.145 -411.914 CLOCK_50 " " -15.145 -411.914 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.764 -34.680 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -3.764 -34.680 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.784 -2.784 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.784 -2.784 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.778 -28.278 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -1.778 -28.278 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.051 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.051 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.528 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 5.528 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.677 " "Worst-case hold slack is -0.677" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.677 -10.405 CLOCK_50 " " -0.677 -10.405 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.178 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.178 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.186 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 7.892 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 7.892 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.692 " "Worst-case recovery slack is -4.692" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818353 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818353 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.692 -358.022 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.692 -358.022 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818353 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899818353 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.517 " "Worst-case removal slack is 2.517" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.517 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 2.517 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818360 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899818360 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.784 " "Worst-case minimum pulse width slack is 4.784" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.784 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.784 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.790 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 4.790 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.208 0.000 CLOCK_50 " " 9.208 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.640 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.640 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.535 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.535 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648899819047 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648899819047 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 528 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 528 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "445 " "Peak virtual memory: 445 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648899819312 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:43:39 2022 " "Processing ended: Sat Apr 2 14:43:39 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648899819312 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648899819312 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648899819312 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648899819312 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648899821564 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648899821565 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:43:41 2022 " "Processing started: Sat Apr 2 14:43:41 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648899821565 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648899821565 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648899821566 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899822459 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899822787 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899823112 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899823439 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899823700 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899823957 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899824212 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899824471 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "380 " "Peak virtual memory: 380 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648899824563 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:43:44 2022 " "Processing ended: Sat Apr 2 14:43:44 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648899824563 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648899824563 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648899824563 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648899824563 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 1242 s " "Quartus II Full Compilation was successful. 0 errors, 1242 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648899825249 ""} diff --git a/db/sdram_clk_gen_altpll.v b/db/sdram_clk_gen_altpll.v new file mode 100644 index 0000000..54ab905 --- /dev/null +++ b/db/sdram_clk_gen_altpll.v @@ -0,0 +1,96 @@ +//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=2 clk0_phase_shift="0" clk1_divide_by=1 clk1_duty_cycle=50 clk1_multiply_by=2 clk1_phase_shift="3000" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=sdram_clk_gen" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +//VERSION_BEGIN 13.1 cbx_altclkbuf 2013:10:17:09:48:19:SJ cbx_altiobuf_bidir 2013:10:17:09:48:19:SJ cbx_altiobuf_in 2013:10:17:09:48:19:SJ cbx_altiobuf_out 2013:10:17:09:48:19:SJ cbx_altpll 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_counter 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ VERSION_END +//CBXI_INSTANCE_NAME="spectrum_sdram_controller_sdram_sdram_clk_gen_sdram_clk_pll_altpll_altpll_component" +// synthesis VERILOG_INPUT_VERSION VERILOG_2001 +// altera message_off 10463 + + + +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + + +//synthesis_resources = cycloneive_pll 1 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module sdram_clk_gen_altpll + ( + clk, + inclk) /* synthesis synthesis_clearbox=1 */; + output [4:0] clk; + input [1:0] inclk; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 [1:0] inclk; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [4:0] wire_pll1_clk; + wire wire_pll1_fbout; + + cycloneive_pll pll1 + ( + .activeclock(), + .clk(wire_pll1_clk), + .clkbad(), + .fbin(wire_pll1_fbout), + .fbout(wire_pll1_fbout), + .inclk(inclk), + .locked(), + .phasedone(), + .scandataout(), + .scandone(), + .vcooverrange(), + .vcounderrange() + `ifndef FORMAL_VERIFICATION + // synopsys translate_off + `endif + , + .areset(1'b0), + .clkswitch(1'b0), + .configupdate(1'b0), + .pfdena(1'b1), + .phasecounterselect({3{1'b0}}), + .phasestep(1'b0), + .phaseupdown(1'b0), + .scanclk(1'b0), + .scanclkena(1'b1), + .scandata(1'b0) + `ifndef FORMAL_VERIFICATION + // synopsys translate_on + `endif + ); + defparam + pll1.bandwidth_type = "auto", + pll1.clk0_divide_by = 1, + pll1.clk0_duty_cycle = 50, + pll1.clk0_multiply_by = 2, + pll1.clk0_phase_shift = "0", + pll1.clk1_divide_by = 1, + pll1.clk1_duty_cycle = 50, + pll1.clk1_multiply_by = 2, + pll1.clk1_phase_shift = "3000", + pll1.compensate_clock = "clk0", + pll1.inclk0_input_frequency = 20000, + pll1.operation_mode = "normal", + pll1.pll_type = "auto", + pll1.lpm_type = "cycloneive_pll"; + assign + clk = {wire_pll1_clk[4:0]}; +endmodule //sdram_clk_gen_altpll +//VALID FILE diff --git a/db/spectrum.(0).cnf.cdb b/db/spectrum.(0).cnf.cdb index b7d6ba3..4bd46bb 100644 Binary files a/db/spectrum.(0).cnf.cdb and b/db/spectrum.(0).cnf.cdb differ diff --git a/db/spectrum.(0).cnf.hdb b/db/spectrum.(0).cnf.hdb index 9fe7f0d..afee0b5 100644 Binary files a/db/spectrum.(0).cnf.hdb and b/db/spectrum.(0).cnf.hdb differ diff --git a/db/spectrum.(80).cnf.cdb b/db/spectrum.(80).cnf.cdb new file mode 100644 index 0000000..52c36e4 Binary files /dev/null and b/db/spectrum.(80).cnf.cdb differ diff --git a/db/spectrum.(80).cnf.hdb b/db/spectrum.(80).cnf.hdb new file mode 100644 index 0000000..c439373 Binary files /dev/null and b/db/spectrum.(80).cnf.hdb differ diff --git a/db/spectrum.(81).cnf.cdb b/db/spectrum.(81).cnf.cdb new file mode 100644 index 0000000..f344c84 Binary files /dev/null and b/db/spectrum.(81).cnf.cdb differ diff --git a/db/spectrum.(81).cnf.hdb b/db/spectrum.(81).cnf.hdb new file mode 100644 index 0000000..1d4b759 Binary files /dev/null and b/db/spectrum.(81).cnf.hdb differ diff --git a/db/spectrum.(82).cnf.cdb b/db/spectrum.(82).cnf.cdb new file mode 100644 index 0000000..fbfdc70 Binary files /dev/null and b/db/spectrum.(82).cnf.cdb differ diff --git a/db/spectrum.(82).cnf.hdb b/db/spectrum.(82).cnf.hdb new file mode 100644 index 0000000..3f60974 Binary files /dev/null and b/db/spectrum.(82).cnf.hdb differ diff --git a/db/spectrum.(83).cnf.cdb b/db/spectrum.(83).cnf.cdb new file mode 100644 index 0000000..a1dddf8 Binary files /dev/null and b/db/spectrum.(83).cnf.cdb differ diff --git a/db/spectrum.(83).cnf.hdb b/db/spectrum.(83).cnf.hdb new file mode 100644 index 0000000..c775d09 Binary files /dev/null and b/db/spectrum.(83).cnf.hdb differ diff --git a/db/spectrum.asm.qmsg b/db/spectrum.asm.qmsg index efa6ad6..1efcd5f 100644 --- a/db/spectrum.asm.qmsg +++ b/db/spectrum.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828541709 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828541710 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 1 18:55:41 2022 " "Processing started: Fri Apr 1 18:55:41 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828541710 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648828541710 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648828541710 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648828542963 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648828542993 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "385 " "Peak virtual memory: 385 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828543318 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 1 18:55:43 2022 " "Processing ended: Fri Apr 1 18:55:43 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828543318 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828543318 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828543318 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648828543318 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648900269993 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648900269994 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:51:09 2022 " "Processing started: Sat Apr 2 14:51:09 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648900269994 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648900269994 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648900269994 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648900271169 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648900271197 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648900271509 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:51:11 2022 " "Processing ended: Sat Apr 2 14:51:11 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648900271509 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648900271509 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648900271509 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648900271509 ""} diff --git a/db/spectrum.asm.rdb b/db/spectrum.asm.rdb index efa9242..89f0c36 100644 Binary files a/db/spectrum.asm.rdb and b/db/spectrum.asm.rdb differ diff --git a/db/spectrum.asm_labs.ddb b/db/spectrum.asm_labs.ddb index 2d8a18e..779674f 100644 Binary files a/db/spectrum.asm_labs.ddb and b/db/spectrum.asm_labs.ddb differ diff --git a/db/spectrum.cbx.xml b/db/spectrum.cbx.xml index 6eb6174..ad13bbe 100644 --- a/db/spectrum.cbx.xml +++ b/db/spectrum.cbx.xml @@ -4,6 +4,7 @@ + diff --git a/db/spectrum.cmp.bpm b/db/spectrum.cmp.bpm index e4349f1..d979dcc 100644 Binary files a/db/spectrum.cmp.bpm and b/db/spectrum.cmp.bpm differ diff --git a/db/spectrum.cmp.cdb b/db/spectrum.cmp.cdb index decd773..b0c9443 100644 Binary files a/db/spectrum.cmp.cdb and b/db/spectrum.cmp.cdb differ diff --git a/db/spectrum.cmp.hdb b/db/spectrum.cmp.hdb index 8694cf0..e0a5d80 100644 Binary files a/db/spectrum.cmp.hdb and b/db/spectrum.cmp.hdb differ diff --git a/db/spectrum.cmp.idb b/db/spectrum.cmp.idb index 756f6f1..c595e18 100644 Binary files a/db/spectrum.cmp.idb and b/db/spectrum.cmp.idb differ diff --git a/db/spectrum.cmp.logdb b/db/spectrum.cmp.logdb index c19a906..c9b0d34 100644 --- a/db/spectrum.cmp.logdb +++ b/db/spectrum.cmp.logdb @@ -30,9 +30,9 @@ IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000 IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, -IO_RULES_MATRIX,Total Pass,75;9;75;0;0;75;75;0;75;75;0;0;0;0;41;0;0;41;0;0;2;0;0;0;0;0;0;75;0;0, +IO_RULES_MATRIX,Total Pass,114;29;114;0;0;114;114;0;114;114;0;0;0;0;57;0;0;57;0;0;10;0;0;0;0;0;0;114;0;0, IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, -IO_RULES_MATRIX,Total Inapplicable,0;66;0;75;75;0;0;75;0;0;75;75;75;75;34;75;75;34;75;75;73;75;75;75;75;75;75;0;75;75, +IO_RULES_MATRIX,Total Inapplicable,0;85;0;114;114;0;0;114;0;0;114;114;114;114;57;114;114;57;114;114;104;114;114;114;114;114;114;0;114;114, IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, IO_RULES_MATRIX,LED[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,LED[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, @@ -98,8 +98,47 @@ IO_RULES_MATRIX,GPIO_1[31],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass IO_RULES_MATRIX,GPIO_1[32],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,GPIO_1[33],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,buzzer_out,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_BA[0],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_BA[1],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQM[0],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQM[1],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_RAS_N,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_CAS_N,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_CKE,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_CLK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_WE_N,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_CS_N,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[0],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[1],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[2],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[3],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[4],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[5],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[6],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[7],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[8],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[9],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[10],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[11],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[12],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,I2C_SCLK,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,I2C_SDAT,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[12],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[13],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[14],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[15],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, IO_RULES_MATRIX,raw_loader_in,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, diff --git a/db/spectrum.cmp.rdb b/db/spectrum.cmp.rdb index 5f8f53f..4536bbc 100644 Binary files a/db/spectrum.cmp.rdb and b/db/spectrum.cmp.rdb differ diff --git a/db/spectrum.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/db/spectrum.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd index 678201a..ff393bd 100644 Binary files a/db/spectrum.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd and b/db/spectrum.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd differ diff --git a/db/spectrum.db_info b/db/spectrum.db_info index 6bfcc88..cf5f9fd 100644 --- a/db/spectrum.db_info +++ b/db/spectrum.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Version_Index = 318808576 -Creation_Time = Wed Mar 30 18:55:53 2022 +Creation_Time = Sat Apr 2 13:37:52 2022 diff --git a/db/spectrum.eda.qmsg b/db/spectrum.eda.qmsg index 0d8b1e0..6331e6f 100644 --- a/db/spectrum.eda.qmsg +++ b/db/spectrum.eda.qmsg @@ -1,12 +1,12 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828550447 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 1 18:55:50 2022 " "Processing started: Fri Apr 1 18:55:50 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828551371 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828551694 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552017 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552344 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552617 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552883 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828553143 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828553404 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "380 " "Peak virtual memory: 380 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828553503 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 1 18:55:53 2022 " "Processing ended: Fri Apr 1 18:55:53 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648900279498 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648900279499 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:51:19 2022 " "Processing started: Sat Apr 2 14:51:19 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648900279499 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648900279499 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648900279499 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900280426 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900280767 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900281107 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900281449 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900281719 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900281988 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900282253 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648900282522 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "379 " "Peak virtual memory: 379 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648900282622 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:51:22 2022 " "Processing ended: Sat Apr 2 14:51:22 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648900282622 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648900282622 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648900282622 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648900282622 ""} diff --git a/db/spectrum.fit.qmsg b/db/spectrum.fit.qmsg index db1e7f9..1afde46 100644 --- a/db/spectrum.fit.qmsg +++ b/db/spectrum.fit.qmsg @@ -1,72 +1,77 @@ -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648828519240 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648828519256 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648828519297 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648828519298 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648828519298 ""} -{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] 141 280 0 0 " "Implementing clock multiplication of 141, clock division of 280, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1221 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648828519365 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] 47 168 0 0 " "Implementing clock multiplication of 47, clock division of 168, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1222 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648828519365 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] 47 98 0 0 " "Implementing clock multiplication of 47, clock division of 98, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1223 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648828519365 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1221 9662 10382 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1648828519365 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648828519447 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648828519460 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648828519687 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648828519687 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648828519687 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648828519687 ""} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5274 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648828519694 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5276 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648828519694 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5278 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648828519694 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5280 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648828519694 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5282 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648828519694 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648828519694 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648828519697 ""} -{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648828519704 ""} -{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1648828520881 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520890 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520890 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648828520890 ""} -{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520892 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520892 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520892 ""} } { } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1648828520892 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520892 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520892 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648828520892 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1648828520893 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520893 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520893 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520894 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520894 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520894 ""} -{ "Warning" "WSTA_SCC_LOOP" "511 " "Found combinational loop of 511 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datac " "Node \"z80_\|alu_control_\|db\[0\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|combout " "Node \"z80_\|alu_control_\|db\[0\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|combout " "Node \"z80_\|alu_control_\|db\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~19\|datab " "Node \"z80_\|alu_\|db\[0\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~19\|combout " "Node \"z80_\|alu_\|db\[0\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|dataa " "Node \"z80_\|sw2_\|db_up\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|combout " "Node \"z80_\|sw2_\|db_up\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|combout " "Node \"z80_\|alu_\|db_high\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|combout " "Node \"z80_\|alu_\|db_high\[3\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|datac " "Node \"z80_\|alu_\|db_high\[3\]~7\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|combout " "Node \"z80_\|alu_\|db_high\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~8\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~8\|combout " "Node \"z80_\|alu_\|db_high\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~21\|datab " "Node \"z80_\|alu_\|db\[7\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~21\|combout " "Node \"z80_\|alu_\|db\[7\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|combout " "Node \"z80_\|alu_\|db_high\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|combout " "Node \"z80_\|alu_\|db_high\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|datac " "Node \"z80_\|alu_\|db_high\[2\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|combout " "Node \"z80_\|alu_\|db_high\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~14\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~14\|combout " "Node \"z80_\|alu_\|db_high\[2\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|datab " "Node \"z80_\|alu_\|db\[6\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|combout " "Node \"z80_\|alu_\|db\[6\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|datab " "Node \"z80_\|alu_\|db_high\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datab " "Node \"z80_\|alu_\|db_high\[3\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~20\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~20\|combout " "Node \"z80_\|alu_control_\|db\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~21\|datad " "Node \"z80_\|alu_control_\|db\[6\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~21\|combout " "Node \"z80_\|alu_control_\|db\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|datad " "Node \"z80_\|alu_control_\|db\[6\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|combout " "Node \"z80_\|alu_control_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|datab " "Node \"z80_\|bus_control_\|db\[6\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|combout " "Node \"z80_\|bus_control_\|db\[6\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|dataa " "Node \"z80_\|bus_control_\|db\[6\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|combout " "Node \"z80_\|bus_control_\|db\[6\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~21\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|dataa " "Node \"z80_\|alu_\|db\[6\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|combout " "Node \"z80_\|alu_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|dataa " "Node \"z80_\|alu_\|db\[6\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~80\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~80\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~82\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~82\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~83\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~83\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~23\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datab " "Node \"z80_\|alu_\|db\[6\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|combout " "Node \"z80_\|alu_\|db_high\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|combout " "Node \"z80_\|alu_\|db_high\[1\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|datac " "Node \"z80_\|alu_\|db_high\[1\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|combout " "Node \"z80_\|alu_\|db_high\[1\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~20\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~20\|combout " "Node \"z80_\|alu_\|db_high\[1\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~25\|datab " "Node \"z80_\|alu_\|db\[5\]~25\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~25\|combout " "Node \"z80_\|alu_\|db\[5\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|datab " "Node \"z80_\|alu_\|db_high\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|combout " "Node \"z80_\|alu_\|db_high\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|combout " "Node \"z80_\|alu_\|db_high\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|datac " "Node \"z80_\|alu_\|db_high\[0\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|combout " "Node \"z80_\|alu_\|db_high\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~26\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~26\|combout " "Node \"z80_\|alu_\|db_high\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|datab " "Node \"z80_\|alu_\|db\[4\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|combout " "Node \"z80_\|alu_\|db\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|combout " "Node \"z80_\|alu_\|db_low\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|combout " "Node \"z80_\|alu_\|db_low\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~11\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~11\|combout " "Node \"z80_\|alu_\|db_low\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~25\|datac " "Node \"z80_\|alu_\|db_low\[3\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~25\|combout " "Node \"z80_\|alu_\|db_low\[3\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~10\|datab " "Node \"z80_\|alu_\|db\[3\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~10\|combout " "Node \"z80_\|alu_\|db\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~11\|dataa " "Node \"z80_\|alu_\|db\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~11\|combout " "Node \"z80_\|alu_\|db\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|datab " "Node \"z80_\|alu_\|db_low\[3\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datab " "Node \"z80_\|alu_\|db_high\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~44\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~44\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~46\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~46\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~47\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~47\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~10\|dataa " "Node \"z80_\|alu_\|db\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~11\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~12\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~2\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~2\|combout " "Node \"z80_\|alu_\|db_low\[2\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~3\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~3\|combout " "Node \"z80_\|alu_\|db_low\[2\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~24\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~24\|combout " "Node \"z80_\|alu_\|db_low\[2\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|datab " "Node \"z80_\|alu_\|db\[2\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|combout " "Node \"z80_\|alu_\|db\[2\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|datab " "Node \"z80_\|alu_\|db_low\[3\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|datac " "Node \"z80_\|alu_control_\|db\[2\]~27\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|combout " "Node \"z80_\|alu_control_\|db\[2\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datac " "Node \"z80_\|alu_control_\|db\[2\]~29\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|combout " "Node \"z80_\|alu_control_\|db\[2\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|datab " "Node \"z80_\|bus_control_\|db\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|combout " "Node \"z80_\|bus_control_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|dataa " "Node \"z80_\|bus_control_\|db\[2\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|combout " "Node \"z80_\|bus_control_\|db\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~28\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|combout " "Node \"z80_\|alu_control_\|db\[2\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datad " "Node \"z80_\|alu_control_\|db\[2\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|datad " "Node \"z80_\|alu_control_\|db\[2\]~28\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~14\|dataa " "Node \"z80_\|alu_\|db\[2\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~14\|combout " "Node \"z80_\|alu_\|db\[2\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|dataa " "Node \"z80_\|alu_\|db\[2\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~35\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~37\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~37\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~38\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~38\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~8\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~9\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~14\|datab " "Node \"z80_\|alu_\|db\[2\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~3\|datab " "Node \"z80_\|alu_\|db_low\[2\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|combout " "Node \"z80_\|alu_\|db_low\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|combout " "Node \"z80_\|alu_\|db_low\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datab " "Node \"z80_\|alu_\|db_low\[1\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|combout " "Node \"z80_\|alu_\|db_low\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~13\|datab " "Node \"z80_\|alu_\|db\[1\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~13\|combout " "Node \"z80_\|alu_\|db\[1\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|combout " "Node \"z80_\|alu_\|db_low\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|combout " "Node \"z80_\|alu_\|db_low\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datab " "Node \"z80_\|alu_\|db_low\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|combout " "Node \"z80_\|alu_\|db_low\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datab " "Node \"z80_\|alu_\|db\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|combout " "Node \"z80_\|alu_\|db\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~19\|dataa " "Node \"z80_\|alu_\|db\[0\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~12\|datab " "Node \"z80_\|alu_\|db\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~12\|combout " "Node \"z80_\|alu_\|db\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~13\|dataa " "Node \"z80_\|alu_\|db\[1\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~2\|datab " "Node \"z80_\|alu_\|db_low\[2\]~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|datab " "Node \"z80_\|alu_\|db_low\[1\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|datac " "Node \"z80_\|alu_control_\|db\[1\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|combout " "Node \"z80_\|alu_control_\|db\[1\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|datac " "Node \"z80_\|alu_control_\|db\[1\]~26\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|combout " "Node \"z80_\|alu_control_\|db\[1\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|datab " "Node \"z80_\|bus_control_\|db\[1\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|combout " "Node \"z80_\|bus_control_\|db\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|dataa " "Node \"z80_\|bus_control_\|db\[1\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|combout " "Node \"z80_\|bus_control_\|db\[1\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|combout " "Node \"z80_\|alu_control_\|db\[1\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|datad " "Node \"z80_\|alu_control_\|db\[1\]~26\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~12\|dataa " "Node \"z80_\|alu_\|db\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|datad " "Node \"z80_\|alu_control_\|db\[1\]~25\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datab " "Node \"z80_\|alu_control_\|db\[3\]~35\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|datac " "Node \"z80_\|alu_control_\|db\[3\]~34\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|combout " "Node \"z80_\|alu_control_\|db\[3\]~34\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~11\|datab " "Node \"z80_\|alu_\|db\[3\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|datab " "Node \"z80_\|bus_control_\|db\[3\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|combout " "Node \"z80_\|bus_control_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~1\|dataa " "Node \"z80_\|sw1_\|db_down\[3\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~1\|combout " "Node \"z80_\|sw1_\|db_down\[3\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~34\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datac " "Node \"z80_\|alu_\|db_high\[2\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|combout " "Node \"z80_\|alu_\|db_high\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|datab " "Node \"z80_\|alu_\|db_high\[3\]~27\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|combout " "Node \"z80_\|alu_\|db_high\[3\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datac " "Node \"z80_\|alu_\|db_high\[0\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|combout " "Node \"z80_\|alu_\|db_high\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datac " "Node \"z80_\|alu_\|db_low\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|combout " "Node \"z80_\|alu_\|db_low\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|combout " "Node \"z80_\|alu_\|db_low\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|combout " "Node \"z80_\|alu_\|db_low\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|combout " "Node \"z80_\|alu_\|db_low\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|datab " "Node \"z80_\|alu_\|db_high\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|combout " "Node \"z80_\|alu_\|db_high\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|datac " "Node \"z80_\|alu_\|db_low\[2\]~4\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|combout " "Node \"z80_\|alu_\|db_low\[2\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|combout " "Node \"z80_\|alu_\|db_low\[2\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~24\|datab " "Node \"z80_\|alu_\|db_low\[2\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~10\|datab " "Node \"z80_\|alu_\|db_low\[3\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~10\|combout " "Node \"z80_\|alu_\|db_low\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~11\|datab " "Node \"z80_\|alu_\|db_low\[3\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|datab " "Node \"z80_\|alu_\|db_high\[0\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|datab " "Node \"z80_\|alu_\|db_high\[1\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~16\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|dataa " "Node \"z80_\|alu_\|db\[4\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|combout " "Node \"z80_\|alu_\|db\[4\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|dataa " "Node \"z80_\|alu_\|db\[4\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|combout " "Node \"z80_\|alu_control_\|db\[4\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datad " "Node \"z80_\|alu_control_\|db\[4\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datad " "Node \"z80_\|alu_control_\|db\[4\]~32\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|combout " "Node \"z80_\|alu_control_\|db\[4\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|datab " "Node \"z80_\|bus_control_\|db\[4\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|combout " "Node \"z80_\|bus_control_\|db\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datab " "Node \"z80_\|alu_\|db_high\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~27\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datab " "Node \"z80_\|alu_\|db_high\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datab " "Node \"z80_\|alu_\|db_low\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datac " "Node \"z80_\|alu_\|db_low\[1\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|datac " "Node \"z80_\|alu_\|db_high\[1\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|datab " "Node \"z80_\|alu_\|db\[4\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|datac " "Node \"z80_\|alu_control_\|db\[4\]~30\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~13\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|dataa " "Node \"z80_\|alu_\|db\[5\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|combout " "Node \"z80_\|alu_\|db\[5\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~25\|dataa " "Node \"z80_\|alu_\|db\[5\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|datab " "Node \"z80_\|alu_control_\|db\[5\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|combout " "Node \"z80_\|alu_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|datab " "Node \"z80_\|bus_control_\|db\[5\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|combout " "Node \"z80_\|bus_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~10\|datac " "Node \"z80_\|alu_\|db_low\[3\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|datac " "Node \"z80_\|alu_\|db_high\[3\]~27\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datab " "Node \"z80_\|alu_\|db_low\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|dataa " "Node \"z80_\|sw1_\|db_down\[5\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|combout " "Node \"z80_\|sw1_\|db_down\[5\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|combout " "Node \"z80_\|alu_control_\|db\[5\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|datab " "Node \"z80_\|alu_\|db_low\[2\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|datac " "Node \"z80_\|alu_control_\|db\[5\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|datab " "Node \"z80_\|alu_\|db\[5\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|datab " "Node \"z80_\|alu_\|db_high\[1\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~73\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~73\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~74\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~74\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~19\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~20\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~21\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|datab " "Node \"z80_\|alu_\|db\[7\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|combout " "Node \"z80_\|alu_\|db\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~21\|dataa " "Node \"z80_\|alu_\|db\[7\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~16\|datac " "Node \"z80_\|alu_control_\|db\[7\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~16\|combout " "Node \"z80_\|alu_control_\|db\[7\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|datac " "Node \"z80_\|alu_control_\|db\[7\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|combout " "Node \"z80_\|alu_control_\|db\[7\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|datab " "Node \"z80_\|bus_control_\|db\[7\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|combout " "Node \"z80_\|bus_control_\|db\[7\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|dataa " "Node \"z80_\|bus_control_\|db\[7\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|combout " "Node \"z80_\|bus_control_\|db\[7\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|combout " "Node \"z80_\|alu_control_\|db\[7\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|datad " "Node \"z80_\|alu_control_\|db\[7\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|dataa " "Node \"z80_\|alu_\|db\[7\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|datad " "Node \"z80_\|alu_control_\|db\[7\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datab " "Node \"z80_\|alu_\|db_high\[3\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datab " "Node \"z80_\|alu_\|db_low\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|dataa " "Node \"z80_\|alu_\|db\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|datab " "Node \"z80_\|alu_\|db_low\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datab " "Node \"z80_\|alu_\|db_low\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|datab " "Node \"z80_\|bus_control_\|db\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|combout " "Node \"z80_\|bus_control_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|datab " "Node \"z80_\|alu_control_\|db\[0\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|combout " "Node \"z80_\|alu_control_\|db\[0\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datab " "Node \"z80_\|alu_control_\|db\[0\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 30 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 31 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Fitter" 0 -1 1648828520900 ""} -{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "511 " "Design contains combinational loop of 511 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Fitter" 0 -1 1648828520917 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648828520949 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648828520949 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1648828520963 ""} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1648828520965 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 5 clocks " "Found 5 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520966 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520966 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 beep " " 10.000 beep" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520966 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520966 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520966 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520966 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520966 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1648828520966 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G15 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5262 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521150 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1221 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521150 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1221 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521150 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1221 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521150 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|clocks:clocks_\|clk_cpu " "Automatically promoted node ula:ula_\|clocks:clocks_\|clk_cpu " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ula:ula_\|clocks:clocks_\|clk_cpu~0 " "Destination node ula:ula_\|clocks:clocks_\|clk_cpu~0" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 2620 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1219 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521150 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset " "Automatically promoted node reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "z80_top_direct_n:z80_\|resets:resets_\|x1~0 " "Destination node z80_top_direct_n:z80_\|resets:resets_\|x1~0" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|x1~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3836 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 62 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1372 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521150 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[30\]~output " "Destination node GPIO_1\[30\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3869 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[0\]~output " "Destination node GPIO_1\[0\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3842 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[1\]~output " "Destination node GPIO_1\[1\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3843 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[2\]~output " "Destination node GPIO_1\[2\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3844 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[3\]~output " "Destination node GPIO_1\[3\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3845 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[4\]~output " "Destination node GPIO_1\[4\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3846 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[5\]~output " "Destination node GPIO_1\[5\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3847 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[6\]~output " "Destination node GPIO_1\[6\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3848 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[7\]~output " "Destination node GPIO_1\[7\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3849 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[8\]~output " "Destination node GPIO_1\[8\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3850 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Quartus II" 0 -1 1648828521151 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648828521151 ""} } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 675 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521151 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|fpga_reset " "Automatically promoted node z80_top_direct_n:z80_\|fpga_reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} } { { "cpu/toplevel/core.vh" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 13 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|fpga_reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 909 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521151 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521152 ""} } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 76 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 747 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521152 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648828521943 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648828521946 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648828521947 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648828521951 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648828521956 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648828521959 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648828521959 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648828521962 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648828522730 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "9 I/O Output Buffer " "Packed 9 registers into blocks of type I/O Output Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1648828522734 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "8 " "Created 8 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "Quartus II" 0 -1 1648828522734 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648828522734 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648828522858 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648828522862 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648828524399 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648828525162 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648828525183 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648828528419 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648828528419 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648828529288 ""} -{ "Info" "IFITAPI_FITAPI_VPR_STATUS_DELAY_ADDED_FOR_HOLD" "7e+02 ns 1.5% " "7e+02 ns of routing delay (approximately 1.5% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." { } { } 0 170089 "%1!s! of routing delay (approximately %2!s! of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." 0 0 "Fitter" 0 -1 1648828531514 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "4 " "Router estimated average interconnect usage is 4% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "26 X32_Y11 X42_Y22 " "Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X32_Y11 to location X42_Y22" { } { { "loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 1 { 0 "Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X32_Y11 to location X42_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X32_Y11 to location X42_Y22"} 32 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648828532126 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648828532126 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:06 " "Fitter routing operations ending: elapsed time is 00:00:06" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648828535524 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648828535527 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648828535527 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "1.92 " "Total time spent on timing analysis during the Fitter is 1.92 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648828535674 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648828535735 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648828536500 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648828536554 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648828537249 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648828538397 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648828538877 ""} -{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "41 Cyclone IV E " "41 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[0\] 3.3-V LVTTL M1 " "Pin SW\[0\] uses I/O standard 3.3-V LVTTL at M1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 141 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[3\] 3.3-V LVTTL M15 " "Pin SW\[3\] uses I/O standard 3.3-V LVTTL at M15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 144 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[0\] 3.3-V LVTTL F13 " "Pin GPIO_1\[0\] uses I/O standard 3.3-V LVTTL at F13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 145 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[1\] 3.3-V LVTTL T15 " "Pin GPIO_1\[1\] uses I/O standard 3.3-V LVTTL at T15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 146 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[2\] 3.3-V LVTTL T14 " "Pin GPIO_1\[2\] uses I/O standard 3.3-V LVTTL at T14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 147 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[3\] 3.3-V LVTTL T13 " "Pin GPIO_1\[3\] uses I/O standard 3.3-V LVTTL at T13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 148 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[4\] 3.3-V LVTTL R13 " "Pin GPIO_1\[4\] uses I/O standard 3.3-V LVTTL at R13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[4] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 149 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[5\] 3.3-V LVTTL T12 " "Pin GPIO_1\[5\] uses I/O standard 3.3-V LVTTL at T12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[5] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 150 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[6\] 3.3-V LVTTL R12 " "Pin GPIO_1\[6\] uses I/O standard 3.3-V LVTTL at R12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[6] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 151 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[7\] 3.3-V LVTTL T11 " "Pin GPIO_1\[7\] uses I/O standard 3.3-V LVTTL at T11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[7] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 152 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[8\] 3.3-V LVTTL T10 " "Pin GPIO_1\[8\] uses I/O standard 3.3-V LVTTL at T10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[8] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 153 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[9\] 3.3-V LVTTL R11 " "Pin GPIO_1\[9\] uses I/O standard 3.3-V LVTTL at R11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[9] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 154 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[10\] 3.3-V LVTTL P11 " "Pin GPIO_1\[10\] uses I/O standard 3.3-V LVTTL at P11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[10] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 155 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[11\] 3.3-V LVTTL R10 " "Pin GPIO_1\[11\] uses I/O standard 3.3-V LVTTL at R10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[11] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 156 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[12\] 3.3-V LVTTL N12 " "Pin GPIO_1\[12\] uses I/O standard 3.3-V LVTTL at N12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[12] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 157 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[13\] 3.3-V LVTTL P9 " "Pin GPIO_1\[13\] uses I/O standard 3.3-V LVTTL at P9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[13] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 158 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[14\] 3.3-V LVTTL N9 " "Pin GPIO_1\[14\] uses I/O standard 3.3-V LVTTL at N9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[14] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 159 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[15\] 3.3-V LVTTL N11 " "Pin GPIO_1\[15\] uses I/O standard 3.3-V LVTTL at N11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[15] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 160 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[16\] 3.3-V LVTTL L16 " "Pin GPIO_1\[16\] uses I/O standard 3.3-V LVTTL at L16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[16] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 161 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[17\] 3.3-V LVTTL K16 " "Pin GPIO_1\[17\] uses I/O standard 3.3-V LVTTL at K16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[17] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 162 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[18\] 3.3-V LVTTL R16 " "Pin GPIO_1\[18\] uses I/O standard 3.3-V LVTTL at R16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[18] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 163 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[19\] 3.3-V LVTTL L15 " "Pin GPIO_1\[19\] uses I/O standard 3.3-V LVTTL at L15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[19] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 164 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[20\] 3.3-V LVTTL P15 " "Pin GPIO_1\[20\] uses I/O standard 3.3-V LVTTL at P15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[20] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 165 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[21\] 3.3-V LVTTL P16 " "Pin GPIO_1\[21\] uses I/O standard 3.3-V LVTTL at P16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[21] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 166 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[22\] 3.3-V LVTTL R14 " "Pin GPIO_1\[22\] uses I/O standard 3.3-V LVTTL at R14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[22] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 167 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[23\] 3.3-V LVTTL N16 " "Pin GPIO_1\[23\] uses I/O standard 3.3-V LVTTL at N16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[23] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 168 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[27\] 3.3-V LVTTL N14 " "Pin GPIO_1\[27\] uses I/O standard 3.3-V LVTTL at N14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[27] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 172 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[28\] 3.3-V LVTTL M10 " "Pin GPIO_1\[28\] uses I/O standard 3.3-V LVTTL at M10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[28] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 173 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[29\] 3.3-V LVTTL L13 " "Pin GPIO_1\[29\] uses I/O standard 3.3-V LVTTL at L13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[29] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 174 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[30\] 3.3-V LVTTL J16 " "Pin GPIO_1\[30\] uses I/O standard 3.3-V LVTTL at J16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[30] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 175 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SCLK 3.3-V LVTTL F2 " "Pin I2C_SCLK uses I/O standard 3.3-V LVTTL at F2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SCLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 6 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SCLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 182 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SDAT 3.3-V LVTTL F1 " "Pin I2C_SDAT uses I/O standard 3.3-V LVTTL at F1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 7 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 183 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[1\] 3.3-V LVTTL T8 " "Pin SW\[1\] uses I/O standard 3.3-V LVTTL at T8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 142 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[2\] 3.3-V LVTTL B9 " "Pin SW\[2\] uses I/O standard 3.3-V LVTTL at B9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 143 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "raw_loader_in 3.3-V LVTTL B6 " "Pin raw_loader_in uses I/O standard 3.3-V LVTTL at B6" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { raw_loader_in } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "raw_loader_in" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 23 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { raw_loader_in } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 193 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[0\] 3.3-V LVTTL J15 " "Pin KEY\[0\] uses I/O standard 3.3-V LVTTL at J15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 127 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 179 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_DAT 3.3-V LVTTL B7 " "Pin PS2_DAT uses I/O standard 3.3-V LVTTL at B7" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_DAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 5 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_DAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 181 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[1\] 3.3-V LVTTL E1 " "Pin KEY\[1\] uses I/O standard 3.3-V LVTTL at E1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 128 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_CLK 3.3-V LVTTL D6 " "Pin PS2_CLK uses I/O standard 3.3-V LVTTL at D6" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_CLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 4 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 180 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "AUD_ADCDAT 3.3-V LVTTL D8 " "Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { AUD_ADCDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 13 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { AUD_ADCDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 189 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648828538892 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648828539248 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 609 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 609 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "639 " "Peak virtual memory: 639 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828540068 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 1 18:55:40 2022 " "Processing ended: Fri Apr 1 18:55:40 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828540068 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:22 " "Elapsed time: 00:00:22" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828540068 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828540068 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648828540068 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648900247191 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648900247208 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648900247247 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648900247248 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648900247248 ""} +{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] 2 1 0 0 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1255 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648900247311 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] 2 1 108 3000 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of 108 degrees (3000 ps) for sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1256 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648900247311 ""} } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1255 9662 10382 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1648900247311 ""} +{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] 141 280 0 0 " "Implementing clock multiplication of 141, clock division of 280, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1223 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648900247312 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] 47 168 0 0 " "Implementing clock multiplication of 47, clock division of 168, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1224 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648900247312 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] 47 98 0 0 " "Implementing clock multiplication of 47, clock division of 98, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1225 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648900247312 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1223 9662 10382 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1648900247312 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648900247395 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648900247407 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648900247623 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648900247623 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648900247623 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648900247623 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5702 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648900247630 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5704 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648900247630 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5706 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648900247630 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5708 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648900247630 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5710 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648900247630 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648900247630 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648900247633 ""} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648900247640 ""} +{ "Warning" "WFSAC_FSAC_PLL_MERGING_PARAMETERS_MISMATCH_WARNING" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 " "The parameters of the PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 and the PLL sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 do not have the same values - hence these PLLs cannot be merged" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "M sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"M\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "M sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 10 " "The value of the parameter \"M\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 10" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "M ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 141 " "The value of the parameter \"M\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 141" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "N sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"N\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "N sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 1 " "The value of the parameter \"N\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 1" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "N ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 7 " "The value of the parameter \"N\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 7" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "LOOP FILTER R sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"LOOP FILTER R\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "LOOP FILTER R sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 4000 " "The value of the parameter \"LOOP FILTER R\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 4000" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "LOOP FILTER R ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 12000 " "The value of the parameter \"LOOP FILTER R\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 12000" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "VCO POST SCALE sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"VCO POST SCALE\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "VCO POST SCALE sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 2 " "The value of the parameter \"VCO POST SCALE\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 2" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "VCO POST SCALE ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 1 " "The value of the parameter \"VCO POST SCALE\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 1" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Min VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Min VCO Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 1538 " "The value of the parameter \"Min VCO Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 1538" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min VCO Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 769 " "The value of the parameter \"Min VCO Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 769" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Max VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Max VCO Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 3333 " "The value of the parameter \"Max VCO Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 3333" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max VCO Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 1666 " "The value of the parameter \"Max VCO Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 1666" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Center VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Center VCO Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Center VCO Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 1538 " "The value of the parameter \"Center VCO Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 1538" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Center VCO Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 769 " "The value of the parameter \"Center VCO Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 769" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Min Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Min Lock Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 15380 " "The value of the parameter \"Min Lock Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 15380" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min Lock Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 15489 " "The value of the parameter \"Min Lock Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 15489" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Max Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Max Lock Period\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max Lock Period sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 33330 " "The value of the parameter \"Max Lock Period\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 33330" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max Lock Period ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 26455 " "The value of the parameter \"Max Lock Period\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 26455" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648900248191 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1223 9662 10382 0} { 0 { 0 ""} 0 1255 9662 10382 0} } } } { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } } 0 176127 "The parameters of the PLL %1!s! and the PLL %2!s! do not have the same values - hence these PLLs cannot be merged" 0 0 "Fitter" 0 -1 1648900248191 ""} +{ "Critical Warning" "WFSAC_FSAC_PLL_FED_BY_REMOTE_CLOCK_PIN_NOT_COMPENSATED" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 0 Pin_R8 " "PLL \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1\" input clock inclk\[0\] is not fully compensated because it is fed by a remote clock pin \"Pin_R8\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 216 0 0 } } { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1255 9662 10382 0} } } } } 1 176598 "PLL \"%1!s!\" input clock inclk\[%2!d!\] is not fully compensated because it is fed by a remote clock pin \"%3!s!\"" 0 0 "Fitter" 0 -1 1648900248210 ""} +{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1648900248866 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648900248875 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248875 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648900248875 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248877 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248877 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248877 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248877 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248877 ""} } { } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1648900248877 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648900248878 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248878 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648900248878 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1648900248878 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648900248879 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648900248879 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648900248879 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648900248879 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648900248879 ""} +{ "Warning" "WSTA_SCC_LOOP" "513 " "Found combinational loop of 513 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|combout " "Node \"z80_\|bus_control_\|db\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~33\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~33\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~33\|combout " "Node \"z80_\|alu_control_\|db\[4\]~33\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~53\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~53\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~60\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~60\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~60\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~60\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datac " "Node \"z80_\|alu_control_\|db\[4\]~31\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datad " "Node \"z80_\|alu_control_\|db\[4\]~32\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|combout " "Node \"z80_\|alu_control_\|db\[4\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~33\|datad " "Node \"z80_\|alu_control_\|db\[4\]~33\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|datab " "Node \"z80_\|alu_\|db\[4\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|combout " "Node \"z80_\|alu_\|db\[4\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|dataa " "Node \"z80_\|alu_\|db\[4\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|combout " "Node \"z80_\|alu_\|db\[4\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~31\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~53\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~53\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~55\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~55\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~56\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~56\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~14\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~15\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|dataa " "Node \"z80_\|alu_\|db\[4\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~16\|datab " "Node \"z80_\|alu_\|db_high\[1\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~16\|combout " "Node \"z80_\|alu_\|db_high\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|combout " "Node \"z80_\|alu_\|db_high\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|datac " "Node \"z80_\|alu_\|db_high\[1\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|combout " "Node \"z80_\|alu_\|db_high\[1\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|combout " "Node \"z80_\|alu_\|db_high\[1\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|datab " "Node \"z80_\|alu_\|db\[5\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|combout " "Node \"z80_\|alu_\|db\[5\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~17\|datab " "Node \"z80_\|alu_control_\|db\[5\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~17\|combout " "Node \"z80_\|alu_control_\|db\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~65\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~65\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~69\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~69\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~69\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~69\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~16\|datac " "Node \"z80_\|alu_control_\|db\[5\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~16\|combout " "Node \"z80_\|alu_control_\|db\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~17\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|datab " "Node \"z80_\|alu_\|db\[5\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|combout " "Node \"z80_\|alu_\|db\[5\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|dataa " "Node \"z80_\|alu_\|db\[5\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|datab " "Node \"z80_\|bus_control_\|db\[5\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|combout " "Node \"z80_\|bus_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|dataa " "Node \"z80_\|sw1_\|db_down\[5\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|combout " "Node \"z80_\|sw1_\|db_down\[5\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~16\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|combout " "Node \"z80_\|alu_\|db_high\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datac " "Node \"z80_\|alu_\|db_high\[3\]~6\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|combout " "Node \"z80_\|alu_\|db_high\[3\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|combout " "Node \"z80_\|alu_\|db_high\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|datab " "Node \"z80_\|alu_\|db\[7\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|combout " "Node \"z80_\|alu_\|db\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|datab " "Node \"z80_\|alu_\|db_high\[3\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|combout " "Node \"z80_\|alu_\|db_high\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~8\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~8\|combout " "Node \"z80_\|alu_\|db_high\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|combout " "Node \"z80_\|alu_\|db_high\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|combout " "Node \"z80_\|alu_\|db_high\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|combout " "Node \"z80_\|alu_\|db_high\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datab " "Node \"z80_\|alu_\|db\[6\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|combout " "Node \"z80_\|alu_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|datab " "Node \"z80_\|alu_\|db_high\[3\]~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|combout " "Node \"z80_\|alu_\|db_high\[3\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datab " "Node \"z80_\|alu_\|db_high\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|datab " "Node \"z80_\|alu_control_\|db\[6\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|combout " "Node \"z80_\|alu_control_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~23\|datac " "Node \"z80_\|alu_control_\|db\[6\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~23\|combout " "Node \"z80_\|alu_control_\|db\[6\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|datab " "Node \"z80_\|bus_control_\|db\[6\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|combout " "Node \"z80_\|bus_control_\|db\[6\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|dataa " "Node \"z80_\|bus_control_\|db\[6\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|combout " "Node \"z80_\|bus_control_\|db\[6\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[6\]~1\|dataa " "Node \"z80_\|sw1_\|db_down\[6\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[6\]~1\|combout " "Node \"z80_\|sw1_\|db_down\[6\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~23\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~77\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~77\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~77\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~77\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~78\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~78\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~78\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~78\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~23\|datab " "Node \"z80_\|alu_control_\|db\[6\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|dataa " "Node \"z80_\|alu_\|db\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|combout " "Node \"z80_\|alu_\|db\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|dataa " "Node \"z80_\|alu_\|db\[6\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~20\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~21\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|datab " "Node \"z80_\|alu_\|db\[6\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~16\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datab " "Node \"z80_\|alu_\|db_low\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|combout " "Node \"z80_\|alu_\|db_low\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|combout " "Node \"z80_\|alu_\|db_low\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~27\|datac " "Node \"z80_\|alu_\|db_low\[0\]~27\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~27\|combout " "Node \"z80_\|alu_\|db_low\[0\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|datab " "Node \"z80_\|alu_\|db\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|combout " "Node \"z80_\|alu_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|dataa " "Node \"z80_\|alu_\|db\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|combout " "Node \"z80_\|alu_\|db\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|dataa " "Node \"z80_\|sw2_\|db_up\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|combout " "Node \"z80_\|sw2_\|db_up\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~11\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~11\|combout " "Node \"z80_\|alu_control_\|db\[0\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~14\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~14\|combout " "Node \"z80_\|alu_control_\|db\[0\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~11\|datac " "Node \"z80_\|alu_control_\|db\[0\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datab " "Node \"z80_\|alu_\|db\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|datab " "Node \"z80_\|bus_control_\|db\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|combout " "Node \"z80_\|bus_control_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~10\|datab " "Node \"z80_\|alu_control_\|db\[0\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~10\|combout " "Node \"z80_\|alu_control_\|db\[0\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~11\|datab " "Node \"z80_\|alu_control_\|db\[0\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datab " "Node \"z80_\|alu_\|db_low\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|dataa " "Node \"z80_\|alu_\|db\[0\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~18\|datab " "Node \"z80_\|alu_\|db_low\[1\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~18\|combout " "Node \"z80_\|alu_\|db_low\[1\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~19\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~19\|combout " "Node \"z80_\|alu_\|db_low\[1\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~20\|datab " "Node \"z80_\|alu_\|db_low\[1\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~20\|combout " "Node \"z80_\|alu_\|db_low\[1\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|datab " "Node \"z80_\|alu_\|db\[1\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|combout " "Node \"z80_\|alu_\|db\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|datab " "Node \"z80_\|alu_\|db\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|combout " "Node \"z80_\|alu_\|db\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|dataa " "Node \"z80_\|alu_\|db\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|datab " "Node \"z80_\|alu_\|db_low\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|combout " "Node \"z80_\|alu_\|db_low\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|combout " "Node \"z80_\|alu_\|db_low\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~14\|combout " "Node \"z80_\|alu_\|db_low\[2\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|datab " "Node \"z80_\|alu_\|db\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|combout " "Node \"z80_\|alu_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~18\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~10\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|datab " "Node \"z80_\|alu_\|db\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|combout " "Node \"z80_\|alu_\|db\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|dataa " "Node \"z80_\|alu_\|db\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|datab " "Node \"z80_\|alu_\|db_low\[3\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|combout " "Node \"z80_\|alu_\|db_low\[3\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|combout " "Node \"z80_\|alu_\|db_low\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|combout " "Node \"z80_\|alu_\|db_low\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~26\|datac " "Node \"z80_\|alu_\|db_low\[3\]~26\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~26\|combout " "Node \"z80_\|alu_\|db_low\[3\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|datab " "Node \"z80_\|alu_\|db\[3\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|combout " "Node \"z80_\|alu_\|db\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|dataa " "Node \"z80_\|alu_\|db\[3\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|combout " "Node \"z80_\|alu_\|db\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|datab " "Node \"z80_\|alu_\|db_high\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|combout " "Node \"z80_\|alu_\|db_high\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|combout " "Node \"z80_\|alu_\|db_high\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|datac " "Node \"z80_\|alu_\|db_high\[0\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|combout " "Node \"z80_\|alu_\|db_high\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|combout " "Node \"z80_\|alu_\|db_high\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|datab " "Node \"z80_\|alu_\|db\[4\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~7\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|dataa " "Node \"z80_\|alu_\|db\[3\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|datab " "Node \"z80_\|alu_\|db_low\[3\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~36\|datab " "Node \"z80_\|alu_control_\|db\[3\]~36\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~36\|combout " "Node \"z80_\|alu_control_\|db\[3\]~36\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|datab " "Node \"z80_\|bus_control_\|db\[3\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|combout " "Node \"z80_\|bus_control_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datac " "Node \"z80_\|alu_\|db_high\[3\]~5\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|datad " "Node \"z80_\|alu_\|db_high\[2\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|combout " "Node \"z80_\|alu_\|db_high\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|datac " "Node \"z80_\|alu_\|db_high\[2\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|combout " "Node \"z80_\|alu_\|db_low\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|combout " "Node \"z80_\|alu_\|db_low\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~20\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datac " "Node \"z80_\|alu_\|db_low\[0\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|combout " "Node \"z80_\|alu_\|db_low\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~25\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~25\|combout " "Node \"z80_\|alu_\|db_low\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~27\|datad " "Node \"z80_\|alu_\|db_low\[0\]~27\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datac " "Node \"z80_\|alu_\|db_high\[0\]~20\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|combout " "Node \"z80_\|alu_\|db_high\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|datab " "Node \"z80_\|alu_\|db_high\[1\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|combout " "Node \"z80_\|alu_\|db_high\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~3\|dataa " "Node \"z80_\|sw1_\|db_down\[3\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~3\|combout " "Node \"z80_\|sw1_\|db_down\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~36\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~36\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~13\|datab " "Node \"z80_\|alu_\|db_low\[2\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~13\|combout " "Node \"z80_\|alu_\|db_low\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~14\|datac " "Node \"z80_\|alu_\|db_low\[2\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|datab " "Node \"z80_\|alu_\|db_low\[3\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|combout " "Node \"z80_\|alu_\|db_low\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|datab " "Node \"z80_\|alu_\|db_low\[3\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~45\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~45\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~45\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~45\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~49\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~49\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~49\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~49\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datac " "Node \"z80_\|alu_control_\|db\[3\]~35\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|datab " "Node \"z80_\|alu_\|db\[3\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|datab " "Node \"z80_\|alu_\|db_low\[2\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|datac " "Node \"z80_\|alu_control_\|db\[2\]~28\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|combout " "Node \"z80_\|alu_control_\|db\[2\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~30\|datac " "Node \"z80_\|alu_control_\|db\[2\]~30\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~30\|combout " "Node \"z80_\|alu_control_\|db\[2\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|datab " "Node \"z80_\|bus_control_\|db\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|combout " "Node \"z80_\|bus_control_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|dataa " "Node \"z80_\|bus_control_\|db\[2\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|combout " "Node \"z80_\|bus_control_\|db\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~29\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|combout " "Node \"z80_\|alu_control_\|db\[2\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~30\|datad " "Node \"z80_\|alu_control_\|db\[2\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|dataa " "Node \"z80_\|alu_\|db\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~38\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~38\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datad " "Node \"z80_\|alu_control_\|db\[2\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~19\|datab " "Node \"z80_\|alu_\|db_low\[1\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|datac " "Node \"z80_\|alu_control_\|db\[1\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|combout " "Node \"z80_\|alu_control_\|db\[1\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|datad " "Node \"z80_\|alu_control_\|db\[1\]~26\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|combout " "Node \"z80_\|alu_control_\|db\[1\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~27\|datab " "Node \"z80_\|alu_control_\|db\[1\]~27\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~27\|combout " "Node \"z80_\|alu_control_\|db\[1\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|datab " "Node \"z80_\|bus_control_\|db\[1\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|combout " "Node \"z80_\|bus_control_\|db\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|dataa " "Node \"z80_\|bus_control_\|db\[1\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|combout " "Node \"z80_\|bus_control_\|db\[1\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[1\]~2\|dataa " "Node \"z80_\|sw1_\|db_down\[1\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[1\]~2\|combout " "Node \"z80_\|sw1_\|db_down\[1\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~27\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~27\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|dataa " "Node \"z80_\|alu_\|db\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|datab " "Node \"z80_\|alu_control_\|db\[1\]~26\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|datac " "Node \"z80_\|alu_control_\|db\[7\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|combout " "Node \"z80_\|alu_control_\|db\[7\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~19\|datad " "Node \"z80_\|alu_control_\|db\[7\]~19\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~19\|combout " "Node \"z80_\|alu_control_\|db\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~20\|datad " "Node \"z80_\|alu_control_\|db\[7\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~20\|combout " "Node \"z80_\|alu_control_\|db\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~37\|datad " "Node \"z80_\|alu_control_\|db\[7\]~37\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~37\|combout " "Node \"z80_\|alu_control_\|db\[7\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|datab " "Node \"z80_\|bus_control_\|db\[7\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|combout " "Node \"z80_\|bus_control_\|db\[7\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|dataa " "Node \"z80_\|bus_control_\|db\[7\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|combout " "Node \"z80_\|bus_control_\|db\[7\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~20\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~87\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~87\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~87\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~87\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~88\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~88\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~88\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~88\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~19\|datab " "Node \"z80_\|alu_control_\|db\[7\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|dataa " "Node \"z80_\|alu_\|db\[7\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|combout " "Node \"z80_\|alu_\|db\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|dataa " "Node \"z80_\|alu_\|db\[7\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~64\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~64\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~65\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~65\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~16\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~17\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~18\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|datab " "Node \"z80_\|alu_\|db\[7\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|datab " "Node \"z80_\|alu_\|db_low\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|datac " "Node \"z80_\|alu_\|db_low\[3\]~7\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~13\|datac " "Node \"z80_\|alu_\|db_low\[2\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~8\|datab " "Node \"z80_\|alu_\|db_high\[2\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|datab " "Node \"z80_\|alu_\|db_high\[1\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~80\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~80\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~82\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~82\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~83\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~83\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|dataa " "Node \"z80_\|alu_\|db\[5\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~22\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~23\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~24\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datab " "Node \"z80_\|alu_\|db_high\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|datab " "Node \"z80_\|bus_control_\|db\[4\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datab " "Node \"z80_\|alu_\|db_high\[3\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|datab " "Node \"z80_\|alu_\|db_high\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|datac " "Node \"z80_\|alu_\|db_low\[1\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datab " "Node \"z80_\|alu_\|db_low\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datab " "Node \"z80_\|alu_\|db_high\[0\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|datac " "Node \"z80_\|alu_\|db_high\[1\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900248886 ""} } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 31 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 30 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Fitter" 0 -1 1648900248886 ""} +{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "513 " "Design contains combinational loop of 513 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Fitter" 0 -1 1648900248903 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648900248934 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648900248934 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1648900248949 ""} +{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1648900248951 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 7 clocks " "Found 7 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248951 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248951 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 beep " " 10.000 beep" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248951 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248951 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248951 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248951 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248951 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248951 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648900248951 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1648900248951 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G15 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648900249144 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5687 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648900249144 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1) " "Automatically promoted node sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1255 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648900249145 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C0 of PLL_1) " "Automatically promoted node sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations External Clock Output CLKCTRL_PLL1E0 " "Automatically promoted destinations to use location or clock signal External Clock Output CLKCTRL_PLL1E0" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1255 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648900249145 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1223 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648900249145 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1223 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648900249145 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1223 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648900249145 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|clocks:clocks_\|clk_cpu " "Automatically promoted node ula:ula_\|clocks:clocks_\|clk_cpu " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ula:ula_\|clocks:clocks_\|clk_cpu~0 " "Destination node ula:ula_\|clocks:clocks_\|clk_cpu~0" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 2863 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648900249145 ""} } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1221 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648900249145 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset " "Automatically promoted node reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "z80_top_direct_n:z80_\|resets:resets_\|x1~0 " "Destination node z80_top_direct_n:z80_\|resets:resets_\|x1~0" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|x1~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4204 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648900249145 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 73 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1499 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648900249145 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[30\]~output " "Destination node GPIO_1\[30\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4239 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[0\]~output " "Destination node GPIO_1\[0\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4212 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[1\]~output " "Destination node GPIO_1\[1\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4213 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[2\]~output " "Destination node GPIO_1\[2\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4214 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[3\]~output " "Destination node GPIO_1\[3\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4215 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[4\]~output " "Destination node GPIO_1\[4\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4216 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[5\]~output " "Destination node GPIO_1\[5\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4217 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[6\]~output " "Destination node GPIO_1\[6\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4218 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[7\]~output " "Destination node GPIO_1\[7\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4219 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[8\]~output " "Destination node GPIO_1\[8\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4220 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648900249145 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Quartus II" 0 -1 1648900249145 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648900249145 ""} } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 675 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648900249145 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|fpga_reset " "Automatically promoted node z80_top_direct_n:z80_\|fpga_reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648900249146 ""} } { { "cpu/toplevel/core.vh" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 13 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|fpga_reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 912 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648900249146 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648900249146 ""} } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 76 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 747 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648900249146 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648900249996 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648900250000 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648900250000 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648900250004 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648900250009 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648900250013 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648900250013 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648900250016 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648900250850 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "29 I/O Output Buffer " "Packed 29 registers into blocks of type I/O Output Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1648900250854 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "15 " "Created 15 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "Quartus II" 0 -1 1648900250854 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648900250854 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648900251001 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648900251001 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648900251003 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648900252550 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648900253381 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648900253404 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648900256519 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648900256519 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648900257442 ""} +{ "Info" "IFITAPI_FITAPI_VPR_STATUS_DELAY_ADDED_FOR_HOLD" "7e+02 ns 1.5% " "7e+02 ns of routing delay (approximately 1.5% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." { } { } 0 170089 "%1!s! of routing delay (approximately %2!s! of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." 0 0 "Fitter" 0 -1 1648900259807 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "5 " "Router estimated average interconnect usage is 5% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "18 X21_Y11 X31_Y22 " "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22" { } { { "loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 1 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} 21 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648900260438 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648900260438 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:06 " "Fitter routing operations ending: elapsed time is 00:00:06" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648900263821 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648900263823 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648900263823 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "1.84 " "Total time spent on timing analysis during the Fitter is 1.84 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648900263969 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648900264030 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648900264828 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648900264880 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648900265610 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648900266817 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648900267295 ""} +{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "57 Cyclone IV E " "57 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[0\] 3.3-V LVTTL M1 " "Pin SW\[0\] uses I/O standard 3.3-V LVTTL at M1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 149 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[3\] 3.3-V LVTTL M15 " "Pin SW\[3\] uses I/O standard 3.3-V LVTTL at M15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 152 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[0\] 3.3-V LVTTL F13 " "Pin GPIO_1\[0\] uses I/O standard 3.3-V LVTTL at F13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 153 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[1\] 3.3-V LVTTL T15 " "Pin GPIO_1\[1\] uses I/O standard 3.3-V LVTTL at T15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 154 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[2\] 3.3-V LVTTL T14 " "Pin GPIO_1\[2\] uses I/O standard 3.3-V LVTTL at T14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 155 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[3\] 3.3-V LVTTL T13 " "Pin GPIO_1\[3\] uses I/O standard 3.3-V LVTTL at T13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 156 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[4\] 3.3-V LVTTL R13 " "Pin GPIO_1\[4\] uses I/O standard 3.3-V LVTTL at R13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[4] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 157 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[5\] 3.3-V LVTTL T12 " "Pin GPIO_1\[5\] uses I/O standard 3.3-V LVTTL at T12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[5] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 158 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[6\] 3.3-V LVTTL R12 " "Pin GPIO_1\[6\] uses I/O standard 3.3-V LVTTL at R12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[6] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 159 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[7\] 3.3-V LVTTL T11 " "Pin GPIO_1\[7\] uses I/O standard 3.3-V LVTTL at T11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[7] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 160 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[8\] 3.3-V LVTTL T10 " "Pin GPIO_1\[8\] uses I/O standard 3.3-V LVTTL at T10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[8] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 161 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[9\] 3.3-V LVTTL R11 " "Pin GPIO_1\[9\] uses I/O standard 3.3-V LVTTL at R11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[9] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 162 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[10\] 3.3-V LVTTL P11 " "Pin GPIO_1\[10\] uses I/O standard 3.3-V LVTTL at P11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[10] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 163 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[11\] 3.3-V LVTTL R10 " "Pin GPIO_1\[11\] uses I/O standard 3.3-V LVTTL at R10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[11] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 164 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[12\] 3.3-V LVTTL N12 " "Pin GPIO_1\[12\] uses I/O standard 3.3-V LVTTL at N12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[12] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 165 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[13\] 3.3-V LVTTL P9 " "Pin GPIO_1\[13\] uses I/O standard 3.3-V LVTTL at P9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[13] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 166 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[14\] 3.3-V LVTTL N9 " "Pin GPIO_1\[14\] uses I/O standard 3.3-V LVTTL at N9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[14] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 167 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[15\] 3.3-V LVTTL N11 " "Pin GPIO_1\[15\] uses I/O standard 3.3-V LVTTL at N11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[15] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 168 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[16\] 3.3-V LVTTL L16 " "Pin GPIO_1\[16\] uses I/O standard 3.3-V LVTTL at L16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[16] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 169 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[17\] 3.3-V LVTTL K16 " "Pin GPIO_1\[17\] uses I/O standard 3.3-V LVTTL at K16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[17] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 170 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[18\] 3.3-V LVTTL R16 " "Pin GPIO_1\[18\] uses I/O standard 3.3-V LVTTL at R16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[18] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 171 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[19\] 3.3-V LVTTL L15 " "Pin GPIO_1\[19\] uses I/O standard 3.3-V LVTTL at L15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[19] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 172 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[20\] 3.3-V LVTTL P15 " "Pin GPIO_1\[20\] uses I/O standard 3.3-V LVTTL at P15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[20] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 173 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[21\] 3.3-V LVTTL P16 " "Pin GPIO_1\[21\] uses I/O standard 3.3-V LVTTL at P16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[21] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 174 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[22\] 3.3-V LVTTL R14 " "Pin GPIO_1\[22\] uses I/O standard 3.3-V LVTTL at R14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[22] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 175 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[23\] 3.3-V LVTTL N16 " "Pin GPIO_1\[23\] uses I/O standard 3.3-V LVTTL at N16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[23] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 176 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[27\] 3.3-V LVTTL N14 " "Pin GPIO_1\[27\] uses I/O standard 3.3-V LVTTL at N14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[27] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 180 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[28\] 3.3-V LVTTL M10 " "Pin GPIO_1\[28\] uses I/O standard 3.3-V LVTTL at M10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[28] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 181 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[29\] 3.3-V LVTTL L13 " "Pin GPIO_1\[29\] uses I/O standard 3.3-V LVTTL at L13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[29] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 182 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[30\] 3.3-V LVTTL J16 " "Pin GPIO_1\[30\] uses I/O standard 3.3-V LVTTL at J16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[30] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 183 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SCLK 3.3-V LVTTL F2 " "Pin I2C_SCLK uses I/O standard 3.3-V LVTTL at F2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SCLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 6 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SCLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 223 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SDAT 3.3-V LVTTL F1 " "Pin I2C_SDAT uses I/O standard 3.3-V LVTTL at F1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 7 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 224 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[0\] 3.3-V LVTTL G2 " "Pin DRAM_DQ\[0\] uses I/O standard 3.3-V LVTTL at G2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 191 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[1\] 3.3-V LVTTL G1 " "Pin DRAM_DQ\[1\] uses I/O standard 3.3-V LVTTL at G1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 192 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[2\] 3.3-V LVTTL L8 " "Pin DRAM_DQ\[2\] uses I/O standard 3.3-V LVTTL at L8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 193 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[3\] 3.3-V LVTTL K5 " "Pin DRAM_DQ\[3\] uses I/O standard 3.3-V LVTTL at K5" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 194 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[4\] 3.3-V LVTTL K2 " "Pin DRAM_DQ\[4\] uses I/O standard 3.3-V LVTTL at K2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[4] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 195 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[5\] 3.3-V LVTTL J2 " "Pin DRAM_DQ\[5\] uses I/O standard 3.3-V LVTTL at J2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[5] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 196 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[6\] 3.3-V LVTTL J1 " "Pin DRAM_DQ\[6\] uses I/O standard 3.3-V LVTTL at J1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[6] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 197 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[7\] 3.3-V LVTTL R7 " "Pin DRAM_DQ\[7\] uses I/O standard 3.3-V LVTTL at R7" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[7] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 198 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[8\] 3.3-V LVTTL T4 " "Pin DRAM_DQ\[8\] uses I/O standard 3.3-V LVTTL at T4" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[8] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 199 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[9\] 3.3-V LVTTL T2 " "Pin DRAM_DQ\[9\] uses I/O standard 3.3-V LVTTL at T2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[9] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 200 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[10\] 3.3-V LVTTL T3 " "Pin DRAM_DQ\[10\] uses I/O standard 3.3-V LVTTL at T3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[10] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 201 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[11\] 3.3-V LVTTL R3 " "Pin DRAM_DQ\[11\] uses I/O standard 3.3-V LVTTL at R3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[11] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 202 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[12\] 3.3-V LVTTL R5 " "Pin DRAM_DQ\[12\] uses I/O standard 3.3-V LVTTL at R5" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[12] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 203 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[13\] 3.3-V LVTTL P3 " "Pin DRAM_DQ\[13\] uses I/O standard 3.3-V LVTTL at P3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[13] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 204 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[14\] 3.3-V LVTTL N3 " "Pin DRAM_DQ\[14\] uses I/O standard 3.3-V LVTTL at N3" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[14] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 205 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[15\] 3.3-V LVTTL K1 " "Pin DRAM_DQ\[15\] uses I/O standard 3.3-V LVTTL at K1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { DRAM_DQ[15] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 31 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 206 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[1\] 3.3-V LVTTL T8 " "Pin SW\[1\] uses I/O standard 3.3-V LVTTL at T8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 150 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[2\] 3.3-V LVTTL B9 " "Pin SW\[2\] uses I/O standard 3.3-V LVTTL at B9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 151 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "raw_loader_in 3.3-V LVTTL B6 " "Pin raw_loader_in uses I/O standard 3.3-V LVTTL at B6" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { raw_loader_in } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "raw_loader_in" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 22 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { raw_loader_in } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 234 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[0\] 3.3-V LVTTL J15 " "Pin KEY\[0\] uses I/O standard 3.3-V LVTTL at J15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 135 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 220 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_DAT 3.3-V LVTTL B7 " "Pin PS2_DAT uses I/O standard 3.3-V LVTTL at B7" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_DAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 5 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_DAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 222 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[1\] 3.3-V LVTTL E1 " "Pin KEY\[1\] uses I/O standard 3.3-V LVTTL at E1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 136 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_CLK 3.3-V LVTTL D6 " "Pin PS2_CLK uses I/O standard 3.3-V LVTTL at D6" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_CLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 4 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 221 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "AUD_ADCDAT 3.3-V LVTTL D8 " "Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { AUD_ADCDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 13 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { AUD_ADCDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 230 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648900267314 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648900267314 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648900267670 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 574 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 574 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "641 " "Peak virtual memory: 641 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648900268503 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:51:08 2022 " "Processing ended: Sat Apr 2 14:51:08 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648900268503 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:22 " "Elapsed time: 00:00:22" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648900268503 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648900268503 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648900268503 ""} diff --git a/db/spectrum.hier_info b/db/spectrum.hier_info index 92a74a1..da0c20c 100644 --- a/db/spectrum.hier_info +++ b/db/spectrum.hier_info @@ -1,80 +1,119 @@ |spectrum -LED[0] << SW[1].DB_MAX_OUTPUT_PORT_TYPE -LED[1] << -LED[2] << SW[2].DB_MAX_OUTPUT_PORT_TYPE -LED[3] << raw_loader_in.DB_MAX_OUTPUT_PORT_TYPE -LED[4] << -LED[5] << -LED[6] << -LED[7] << -CLOCK_50 => CLOCK_50.IN3 +LED[0] <= SW[1].DB_MAX_OUTPUT_PORT_TYPE +LED[1] <= +LED[2] <= SW[2].DB_MAX_OUTPUT_PORT_TYPE +LED[3] <= raw_loader_in.DB_MAX_OUTPUT_PORT_TYPE +LED[4] <= +LED[5] <= +LED[6] <= +LED[7] <= +CLOCK_50 => CLOCK_50.IN4 KEY[0] => reset.IN1 KEY[1] => nNMI.IN1 PS2_CLK => PS2_CLK.IN1 PS2_DAT => PS2_DAT.IN1 I2C_SCLK <> ula:ula_.I2C_SCLK I2C_SDAT <> ula:ula_.I2C_SDAT -AUD_XCK << ula:ula_.AUD_XCK -AUD_ADCLRCK << ula:ula_.AUD_ADCLRCK -AUD_DACLRCK << ula:ula_.AUD_DACLRCK -AUD_BCLK << ula:ula_.AUD_BCLK -AUD_DACDAT << ula:ula_.AUD_DACDAT +AUD_XCK <= ula:ula_.AUD_XCK +AUD_ADCLRCK <= ula:ula_.AUD_ADCLRCK +AUD_DACLRCK <= ula:ula_.AUD_DACLRCK +AUD_BCLK <= ula:ula_.AUD_BCLK +AUD_DACDAT <= ula:ula_.AUD_DACDAT AUD_ADCDAT => AUD_ADCDAT.IN1 -VGA_R[0] << ula:ula_.VGA_R -VGA_R[1] << ula:ula_.VGA_R -VGA_R[2] << ula:ula_.VGA_R -VGA_R[3] << ula:ula_.VGA_R -VGA_G[0] << ula:ula_.VGA_G -VGA_G[1] << ula:ula_.VGA_G -VGA_G[2] << ula:ula_.VGA_G -VGA_G[3] << ula:ula_.VGA_G -VGA_B[0] << ula:ula_.VGA_B -VGA_B[1] << ula:ula_.VGA_B -VGA_B[2] << ula:ula_.VGA_B -VGA_B[3] << ula:ula_.VGA_B -VGA_HS << ula:ula_.VGA_HS -VGA_VS << ula:ula_.VGA_VS +VGA_R[0] <= ula:ula_.VGA_R +VGA_R[1] <= ula:ula_.VGA_R +VGA_R[2] <= ula:ula_.VGA_R +VGA_R[3] <= ula:ula_.VGA_R +VGA_G[0] <= ula:ula_.VGA_G +VGA_G[1] <= ula:ula_.VGA_G +VGA_G[2] <= ula:ula_.VGA_G +VGA_G[3] <= ula:ula_.VGA_G +VGA_B[0] <= ula:ula_.VGA_B +VGA_B[1] <= ula:ula_.VGA_B +VGA_B[2] <= ula:ula_.VGA_B +VGA_B[3] <= ula:ula_.VGA_B +VGA_HS <= ula:ula_.VGA_HS +VGA_VS <= ula:ula_.VGA_VS SW[0] => ~NO_FANOUT~ SW[1] => LED[0].DATAIN SW[1] => comb.OUTPUTSELECT SW[2] => SW[2].IN1 SW[3] => ~NO_FANOUT~ -GPIO_1[0] << A[0].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[1] << A[1].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[2] << A[2].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[3] << A[3].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[4] << A[4].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[5] << A[5].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[6] << A[6].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[7] << A[7].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[8] << A[8].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[9] << A[9].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[10] << A[10].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[11] << A[11].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[12] << A[12].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[13] << A[13].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[14] << A[14].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[15] << A[15].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[16] << D[0].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[17] << D[1].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[18] << D[2].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[19] << D[3].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[20] << D[4].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[21] << D[5].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[22] << D[6].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[23] << D[7].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[24] << z80_top_direct_n:z80_.nBUSACK -GPIO_1[25] << z80_top_direct_n:z80_.nHALT -GPIO_1[26] << z80_top_direct_n:z80_.nRFSH -GPIO_1[27] << z80_top_direct_n:z80_.nWR -GPIO_1[28] << z80_top_direct_n:z80_.nRD -GPIO_1[29] << z80_top_direct_n:z80_.nIORQ -GPIO_1[30] << z80_top_direct_n:z80_.nMREQ -GPIO_1[31] << z80_top_direct_n:z80_.nM1 -GPIO_1[32] << -GPIO_1[33] << -buzzer_out << ula:ula_.beep +GPIO_1[0] <= A[0].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[1] <= A[1].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[2] <= A[2].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[3] <= A[3].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[4] <= A[4].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[5] <= A[5].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[6] <= A[6].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[7] <= A[7].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[8] <= A[8].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[9] <= A[9].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[10] <= A[10].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[11] <= A[11].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[12] <= A[12].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[13] <= A[13].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[14] <= A[14].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[15] <= A[15].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[16] <= D[0].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[17] <= D[1].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[18] <= D[2].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[19] <= D[3].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[20] <= D[4].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[21] <= D[5].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[22] <= D[6].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[23] <= D[7].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[24] <= z80_top_direct_n:z80_.nBUSACK +GPIO_1[25] <= z80_top_direct_n:z80_.nHALT +GPIO_1[26] <= z80_top_direct_n:z80_.nRFSH +GPIO_1[27] <= z80_top_direct_n:z80_.nWR +GPIO_1[28] <= z80_top_direct_n:z80_.nRD +GPIO_1[29] <= z80_top_direct_n:z80_.nIORQ +GPIO_1[30] <= z80_top_direct_n:z80_.nMREQ +GPIO_1[31] <= z80_top_direct_n:z80_.nM1 +GPIO_1[32] <= +GPIO_1[33] <= +buzzer_out <= ula:ula_.beep raw_loader_in => raw_loader_in.IN1 +DRAM_BA[0] <= sdram_controller:sdram_.DRAM_BA +DRAM_BA[1] <= sdram_controller:sdram_.DRAM_BA +DRAM_DQM[0] <= sdram_controller:sdram_.DRAM_DQM +DRAM_DQM[1] <= sdram_controller:sdram_.DRAM_DQM +DRAM_RAS_N <= sdram_controller:sdram_.DRAM_RAS_N +DRAM_CAS_N <= sdram_controller:sdram_.DRAM_CAS_N +DRAM_CKE <= sdram_controller:sdram_.DRAM_CKE +DRAM_CLK <= sdram_controller:sdram_.DRAM_CLK +DRAM_WE_N <= sdram_controller:sdram_.DRAM_WE_N +DRAM_CS_N <= sdram_controller:sdram_.DRAM_CS_N +DRAM_DQ[0] <> sdram_controller:sdram_.DRAM_DQ +DRAM_DQ[1] <> sdram_controller:sdram_.DRAM_DQ +DRAM_DQ[2] <> sdram_controller:sdram_.DRAM_DQ +DRAM_DQ[3] <> sdram_controller:sdram_.DRAM_DQ +DRAM_DQ[4] <> sdram_controller:sdram_.DRAM_DQ +DRAM_DQ[5] <> sdram_controller:sdram_.DRAM_DQ +DRAM_DQ[6] <> sdram_controller:sdram_.DRAM_DQ +DRAM_DQ[7] <> sdram_controller:sdram_.DRAM_DQ +DRAM_DQ[8] <> sdram_controller:sdram_.DRAM_DQ +DRAM_DQ[9] <> sdram_controller:sdram_.DRAM_DQ +DRAM_DQ[10] <> sdram_controller:sdram_.DRAM_DQ +DRAM_DQ[11] <> sdram_controller:sdram_.DRAM_DQ +DRAM_DQ[12] <> sdram_controller:sdram_.DRAM_DQ +DRAM_DQ[13] <> sdram_controller:sdram_.DRAM_DQ +DRAM_DQ[14] <> sdram_controller:sdram_.DRAM_DQ +DRAM_DQ[15] <> sdram_controller:sdram_.DRAM_DQ +DRAM_ADDR[0] <= sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[1] <= sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[2] <= sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[3] <= sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[4] <= sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[5] <= sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[6] <= sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[7] <= sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[8] <= sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[9] <= sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[10] <= sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[11] <= sdram_controller:sdram_.DRAM_ADDR +DRAM_ADDR[12] <= sdram_controller:sdram_.DRAM_ADDR |spectrum|rom0:rom @@ -1991,6 +2030,296 @@ sel[1] => _.IN0 sel[1] => _.IN0 +|spectrum|sdram_controller:sdram_ +CLOCK_50 => sdram_clk_gen:sdram_clk_pll.inclk0 +DRAM_ADDR[0] <= r.address[0].DB_MAX_OUTPUT_PORT_TYPE +DRAM_ADDR[1] <= r.address[1].DB_MAX_OUTPUT_PORT_TYPE +DRAM_ADDR[2] <= r.address[2].DB_MAX_OUTPUT_PORT_TYPE +DRAM_ADDR[3] <= r.address[3].DB_MAX_OUTPUT_PORT_TYPE +DRAM_ADDR[4] <= r.address[4].DB_MAX_OUTPUT_PORT_TYPE +DRAM_ADDR[5] <= r.address[5].DB_MAX_OUTPUT_PORT_TYPE +DRAM_ADDR[6] <= r.address[6].DB_MAX_OUTPUT_PORT_TYPE +DRAM_ADDR[7] <= r.address[7].DB_MAX_OUTPUT_PORT_TYPE +DRAM_ADDR[8] <= r.address[8].DB_MAX_OUTPUT_PORT_TYPE +DRAM_ADDR[9] <= r.address[9].DB_MAX_OUTPUT_PORT_TYPE +DRAM_ADDR[10] <= r.address[10].DB_MAX_OUTPUT_PORT_TYPE +DRAM_ADDR[11] <= r.address[11].DB_MAX_OUTPUT_PORT_TYPE +DRAM_ADDR[12] <= r.address[12].DB_MAX_OUTPUT_PORT_TYPE +DRAM_BA[0] <= r.bank[0].DB_MAX_OUTPUT_PORT_TYPE +DRAM_BA[1] <= r.bank[1].DB_MAX_OUTPUT_PORT_TYPE +DRAM_CAS_N <= r.state[1].DB_MAX_OUTPUT_PORT_TYPE +DRAM_CKE <= +DRAM_CLK <= sdram_clk_gen:sdram_clk_pll.c1 +DRAM_CS_N <= r.state[3].DB_MAX_OUTPUT_PORT_TYPE +DRAM_DQ[0] <> DRAM_DQ[0] +DRAM_DQ[1] <> DRAM_DQ[1] +DRAM_DQ[2] <> DRAM_DQ[2] +DRAM_DQ[3] <> DRAM_DQ[3] +DRAM_DQ[4] <> DRAM_DQ[4] +DRAM_DQ[5] <> DRAM_DQ[5] +DRAM_DQ[6] <> DRAM_DQ[6] +DRAM_DQ[7] <> DRAM_DQ[7] +DRAM_DQ[8] <> DRAM_DQ[8] +DRAM_DQ[9] <> DRAM_DQ[9] +DRAM_DQ[10] <> DRAM_DQ[10] +DRAM_DQ[11] <> DRAM_DQ[11] +DRAM_DQ[12] <> DRAM_DQ[12] +DRAM_DQ[13] <> DRAM_DQ[13] +DRAM_DQ[14] <> DRAM_DQ[14] +DRAM_DQ[15] <> DRAM_DQ[15] +DRAM_DQM[0] <= r.dq_masks[0].DB_MAX_OUTPUT_PORT_TYPE +DRAM_DQM[1] <= r.dq_masks[1].DB_MAX_OUTPUT_PORT_TYPE +DRAM_RAS_N <= r.state[2].DB_MAX_OUTPUT_PORT_TYPE +DRAM_WE_N <= r.state[0].DB_MAX_OUTPUT_PORT_TYPE +address[0] => ~NO_FANOUT~ +address[1] => n.DATAB +address[1] => n.DATAB +address[1] => Mux22.IN36 +address[2] => n.DATAB +address[2] => n.DATAB +address[2] => Mux21.IN36 +address[3] => n.DATAB +address[3] => n.DATAB +address[3] => Mux20.IN36 +address[4] => n.DATAB +address[4] => n.DATAB +address[4] => Mux19.IN36 +address[5] => n.DATAB +address[5] => n.DATAB +address[5] => Mux18.IN36 +address[6] => n.DATAB +address[6] => n.DATAB +address[6] => Mux17.IN36 +address[7] => n.DATAB +address[7] => n.DATAB +address[7] => Mux16.IN36 +address[8] => n.DATAB +address[8] => n.DATAB +address[8] => Mux15.IN36 +address[9] => n.DATAB +address[9] => n.DATAB +address[9] => n.DATAB +address[9] => Mux26.IN36 +address[10] => n.DATAB +address[10] => n.DATAB +address[10] => n.DATAB +address[10] => Mux25.IN36 +address[11] => Equal7.IN25 +address[11] => n.DATAB +address[11] => n.DATAB +address[12] => Equal7.IN24 +address[12] => n.DATAB +address[12] => n.DATAB +address[13] => Equal7.IN23 +address[13] => n.DATAB +address[13] => n.DATAB +address[14] => Equal7.IN22 +address[14] => n.DATAB +address[14] => n.DATAB +address[15] => Equal7.IN21 +address[15] => n.DATAB +address[15] => n.DATAB +address[16] => Equal7.IN20 +address[16] => n.DATAB +address[16] => n.DATAB +address[17] => Equal7.IN19 +address[17] => n.DATAB +address[17] => n.DATAB +address[18] => Equal7.IN18 +address[18] => n.DATAB +address[18] => n.DATAB +address[19] => Equal7.IN17 +address[19] => n.DATAB +address[19] => n.DATAB +address[20] => Equal7.IN16 +address[20] => n.DATAB +address[20] => n.DATAB +address[21] => Equal7.IN15 +address[21] => n.DATAB +address[21] => n.DATAB +address[22] => Equal7.IN14 +address[22] => n.DATAB +address[22] => n.DATAB +address[23] => Equal7.IN13 +address[23] => n.DATAB +address[23] => n.DATAB +req_read => n.OUTPUTSELECT +req_write => n.OUTPUTSELECT +data_out[0] <= r.data_out_low[0].DB_MAX_OUTPUT_PORT_TYPE +data_out[1] <= r.data_out_low[1].DB_MAX_OUTPUT_PORT_TYPE +data_out[2] <= r.data_out_low[2].DB_MAX_OUTPUT_PORT_TYPE +data_out[3] <= r.data_out_low[3].DB_MAX_OUTPUT_PORT_TYPE +data_out[4] <= r.data_out_low[4].DB_MAX_OUTPUT_PORT_TYPE +data_out[5] <= r.data_out_low[5].DB_MAX_OUTPUT_PORT_TYPE +data_out[6] <= r.data_out_low[6].DB_MAX_OUTPUT_PORT_TYPE +data_out[7] <= r.data_out_low[7].DB_MAX_OUTPUT_PORT_TYPE +data_out[8] <= r.data_out_low[8].DB_MAX_OUTPUT_PORT_TYPE +data_out[9] <= r.data_out_low[9].DB_MAX_OUTPUT_PORT_TYPE +data_out[10] <= r.data_out_low[10].DB_MAX_OUTPUT_PORT_TYPE +data_out[11] <= r.data_out_low[11].DB_MAX_OUTPUT_PORT_TYPE +data_out[12] <= r.data_out_low[12].DB_MAX_OUTPUT_PORT_TYPE +data_out[13] <= r.data_out_low[13].DB_MAX_OUTPUT_PORT_TYPE +data_out[14] <= r.data_out_low[14].DB_MAX_OUTPUT_PORT_TYPE +data_out[15] <= r.data_out_low[15].DB_MAX_OUTPUT_PORT_TYPE +data_out[16] <= captured[0].DB_MAX_OUTPUT_PORT_TYPE +data_out[17] <= captured[1].DB_MAX_OUTPUT_PORT_TYPE +data_out[18] <= captured[2].DB_MAX_OUTPUT_PORT_TYPE +data_out[19] <= captured[3].DB_MAX_OUTPUT_PORT_TYPE +data_out[20] <= captured[4].DB_MAX_OUTPUT_PORT_TYPE +data_out[21] <= captured[5].DB_MAX_OUTPUT_PORT_TYPE +data_out[22] <= captured[6].DB_MAX_OUTPUT_PORT_TYPE +data_out[23] <= captured[7].DB_MAX_OUTPUT_PORT_TYPE +data_out[24] <= captured[8].DB_MAX_OUTPUT_PORT_TYPE +data_out[25] <= captured[9].DB_MAX_OUTPUT_PORT_TYPE +data_out[26] <= captured[10].DB_MAX_OUTPUT_PORT_TYPE +data_out[27] <= captured[11].DB_MAX_OUTPUT_PORT_TYPE +data_out[28] <= captured[12].DB_MAX_OUTPUT_PORT_TYPE +data_out[29] <= captured[13].DB_MAX_OUTPUT_PORT_TYPE +data_out[30] <= captured[14].DB_MAX_OUTPUT_PORT_TYPE +data_out[31] <= captured[15].DB_MAX_OUTPUT_PORT_TYPE +data_out_valid <= r.data_out_valid.DB_MAX_OUTPUT_PORT_TYPE +data_in[0] => Mux72.IN30 +data_in[0] => Mux72.IN31 +data_in[1] => Mux3.IN30 +data_in[1] => Mux3.IN31 +data_in[2] => Mux2.IN30 +data_in[2] => Mux2.IN31 +data_in[3] => Mux1.IN30 +data_in[3] => Mux1.IN31 +data_in[4] => Mux0.IN30 +data_in[4] => Mux0.IN31 +data_in[5] => Mux73.IN30 +data_in[5] => Mux73.IN31 +data_in[6] => Mux74.IN30 +data_in[6] => Mux74.IN31 +data_in[7] => Mux75.IN30 +data_in[7] => Mux75.IN31 +data_in[8] => Mux76.IN30 +data_in[8] => Mux76.IN31 +data_in[9] => Mux77.IN30 +data_in[9] => Mux77.IN31 +data_in[10] => Mux78.IN30 +data_in[10] => Mux78.IN31 +data_in[11] => Mux79.IN30 +data_in[11] => Mux79.IN31 +data_in[12] => Mux80.IN30 +data_in[12] => Mux80.IN31 +data_in[13] => Mux81.IN30 +data_in[13] => Mux81.IN31 +data_in[14] => Mux82.IN30 +data_in[14] => Mux82.IN31 +data_in[15] => Mux83.IN30 +data_in[15] => Mux83.IN31 +data_in[16] => Mux72.IN28 +data_in[16] => Mux72.IN29 +data_in[17] => Mux3.IN28 +data_in[17] => Mux3.IN29 +data_in[18] => Mux2.IN28 +data_in[18] => Mux2.IN29 +data_in[19] => Mux1.IN28 +data_in[19] => Mux1.IN29 +data_in[20] => Mux0.IN28 +data_in[20] => Mux0.IN29 +data_in[21] => Mux73.IN28 +data_in[21] => Mux73.IN29 +data_in[22] => Mux74.IN28 +data_in[22] => Mux74.IN29 +data_in[23] => Mux75.IN28 +data_in[23] => Mux75.IN29 +data_in[24] => Mux76.IN28 +data_in[24] => Mux76.IN29 +data_in[25] => Mux77.IN28 +data_in[25] => Mux77.IN29 +data_in[26] => Mux78.IN28 +data_in[26] => Mux78.IN29 +data_in[27] => Mux79.IN28 +data_in[27] => Mux79.IN29 +data_in[28] => Mux80.IN28 +data_in[28] => Mux80.IN29 +data_in[29] => Mux81.IN28 +data_in[29] => Mux81.IN29 +data_in[30] => Mux82.IN28 +data_in[30] => Mux82.IN29 +data_in[31] => Mux83.IN28 +data_in[31] => Mux83.IN29 + + +|spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll +inclk0 => sub_wire4[0].IN1 +c0 <= altpll:altpll_component.clk +c1 <= altpll:altpll_component.clk + + +|spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component +inclk[0] => sdram_clk_gen_altpll:auto_generated.inclk[0] +inclk[1] => sdram_clk_gen_altpll:auto_generated.inclk[1] +fbin => ~NO_FANOUT~ +pllena => ~NO_FANOUT~ +clkswitch => ~NO_FANOUT~ +areset => ~NO_FANOUT~ +pfdena => ~NO_FANOUT~ +clkena[0] => ~NO_FANOUT~ +clkena[1] => ~NO_FANOUT~ +clkena[2] => ~NO_FANOUT~ +clkena[3] => ~NO_FANOUT~ +clkena[4] => ~NO_FANOUT~ +clkena[5] => ~NO_FANOUT~ +extclkena[0] => ~NO_FANOUT~ +extclkena[1] => ~NO_FANOUT~ +extclkena[2] => ~NO_FANOUT~ +extclkena[3] => ~NO_FANOUT~ +scanclk => ~NO_FANOUT~ +scanclkena => ~NO_FANOUT~ +scanaclr => ~NO_FANOUT~ +scanread => ~NO_FANOUT~ +scanwrite => ~NO_FANOUT~ +scandata => ~NO_FANOUT~ +phasecounterselect[0] => ~NO_FANOUT~ +phasecounterselect[1] => ~NO_FANOUT~ +phasecounterselect[2] => ~NO_FANOUT~ +phasecounterselect[3] => ~NO_FANOUT~ +phaseupdown => ~NO_FANOUT~ +phasestep => ~NO_FANOUT~ +configupdate => ~NO_FANOUT~ +fbmimicbidir <> +clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE +clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE +clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE +clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE +clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE +extclk[0] <= +extclk[1] <= +extclk[2] <= +extclk[3] <= +clkbad[0] <= +clkbad[1] <= +enable1 <= +enable0 <= +activeclock <= +clkloss <= +locked <= +scandataout <= +scandone <= +sclkout0 <= +sclkout1 <= +phasedone <= +vcooverrange <= +vcounderrange <= +fbout <= +fref <= +icdrclk <= + + +|spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated +clk[0] <= pll1.CLK +clk[1] <= pll1.CLK1 +clk[2] <= pll1.CLK2 +clk[3] <= pll1.CLK3 +clk[4] <= pll1.CLK4 +inclk[0] => pll1.CLK +inclk[1] => pll1.CLK1 + + |spectrum|ula:ula_ CLOCK_50 => CLOCK_50.IN1 turbo => clocks:clocks_.turbo diff --git a/db/spectrum.hif b/db/spectrum.hif index 1ef198c..49fd970 100644 Binary files a/db/spectrum.hif and b/db/spectrum.hif differ diff --git a/db/spectrum.ipinfo b/db/spectrum.ipinfo index 22d055f..7280a98 100644 Binary files a/db/spectrum.ipinfo and b/db/spectrum.ipinfo differ diff --git a/db/spectrum.lpc.html b/db/spectrum.lpc.html index d9c37b6..ada819b 100644 --- a/db/spectrum.lpc.html +++ b/db/spectrum.lpc.html @@ -1424,6 +1424,54 @@ 0 +sdram_|sdram_clk_pll|altpll_component|auto_generated +2 +0 +0 +0 +5 +0 +0 +0 +0 +0 +0 +0 +0 + + +sdram_|sdram_clk_pll +1 +0 +0 +0 +2 +0 +0 +0 +0 +0 +0 +0 +0 + + +sdram_ +59 +33 +1 +33 +56 +33 +33 +33 +16 +0 +0 +0 +0 + + ram1|altsyncram_component|auto_generated|mux2 34 0 diff --git a/db/spectrum.lpc.rdb b/db/spectrum.lpc.rdb index 3423430..7019611 100644 Binary files a/db/spectrum.lpc.rdb and b/db/spectrum.lpc.rdb differ diff --git a/db/spectrum.lpc.txt b/db/spectrum.lpc.txt index f3098a2..ef961e3 100644 --- a/db/spectrum.lpc.txt +++ b/db/spectrum.lpc.txt @@ -1321,6 +1321,51 @@ Unused Bidir : 0 Input only Bidir : 0 Output only Bidir : 0 +Hierarchy : sdram_|sdram_clk_pll|altpll_component|auto_generated +Input : 2 +Constant Input : 0 +Unused Input : 0 +Floating Input : 0 +Output : 5 +Constant Output : 0 +Unused Output : 0 +Floating Output : 0 +Bidir : 0 +Constant Bidir : 0 +Unused Bidir : 0 +Input only Bidir : 0 +Output only Bidir : 0 + +Hierarchy : sdram_|sdram_clk_pll +Input : 1 +Constant Input : 0 +Unused Input : 0 +Floating Input : 0 +Output : 2 +Constant Output : 0 +Unused Output : 0 +Floating Output : 0 +Bidir : 0 +Constant Bidir : 0 +Unused Bidir : 0 +Input only Bidir : 0 +Output only Bidir : 0 + +Hierarchy : sdram_ +Input : 59 +Constant Input : 33 +Unused Input : 1 +Floating Input : 33 +Output : 56 +Constant Output : 33 +Unused Output : 33 +Floating Output : 33 +Bidir : 16 +Constant Bidir : 0 +Unused Bidir : 0 +Input only Bidir : 0 +Output only Bidir : 0 + Hierarchy : ram1|altsyncram_component|auto_generated|mux2 Input : 34 Constant Input : 0 diff --git a/db/spectrum.map.bpm b/db/spectrum.map.bpm index 2eeb07a..00ac7a9 100644 Binary files a/db/spectrum.map.bpm and b/db/spectrum.map.bpm differ diff --git a/db/spectrum.map.cdb b/db/spectrum.map.cdb index 0aaf4b3..7a78eb8 100644 Binary files a/db/spectrum.map.cdb and b/db/spectrum.map.cdb differ diff --git a/db/spectrum.map.hdb b/db/spectrum.map.hdb index e01f3b5..9e8549c 100644 Binary files a/db/spectrum.map.hdb and b/db/spectrum.map.hdb differ diff --git a/db/spectrum.map.kpt b/db/spectrum.map.kpt index ca4b38c..c4fb4be 100644 Binary files a/db/spectrum.map.kpt and b/db/spectrum.map.kpt differ diff --git a/db/spectrum.map.qmsg b/db/spectrum.map.qmsg index 5e06b04..7cedb0f 100644 --- a/db/spectrum.map.qmsg +++ b/db/spectrum.map.qmsg @@ -1,159 +1,168 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828504365 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828504366 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 1 18:55:04 2022 " "Processing started: Fri Apr 1 18:55:04 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828504366 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648828504366 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648828504367 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648828504551 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.sv 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.sv" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504625 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504625 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504626 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504626 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram16.v 1 1 " "Found 1 design units, including 1 entities, in source file ram16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram16 " "Found entity 1: ram16" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504627 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504627 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram32.v 1 1 " "Found 1 design units, including 1 entities, in source file ram32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram32 " "Found entity 1: ram32" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504628 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504628 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Found entity 1: pll" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504629 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504629 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Found entity 1: alu" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504630 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504630 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_bit_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_bit_select " "Found entity 1: alu_bit_select" { } { { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504631 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504631 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_control " "Found entity 1: alu_control" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504632 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504632 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_core " "Found entity 1: alu_core" { } { { "cpu/alu/alu_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504633 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504633 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_flags.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_flags " "Found entity 1: alu_flags" { } { { "cpu/alu/alu_flags.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504634 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504634 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2 " "Found entity 1: alu_mux_2" { } { { "cpu/alu/alu_mux_2.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504635 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504635 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2z " "Found entity 1: alu_mux_2z" { } { { "cpu/alu/alu_mux_2z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504635 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504635 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_3z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_3z " "Found entity 1: alu_mux_3z" { } { { "cpu/alu/alu_mux_3z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_3z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504636 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504636 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_4.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_4 " "Found entity 1: alu_mux_4" { } { { "cpu/alu/alu_mux_4.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_4.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504637 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504637 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_8.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_8 " "Found entity 1: alu_mux_8" { } { { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504638 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504638 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_prep_daa.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_prep_daa " "Found entity 1: alu_prep_daa" { } { { "cpu/alu/alu_prep_daa.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_prep_daa.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504639 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504639 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_select " "Found entity 1: alu_select" { } { { "cpu/alu/alu_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504639 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504639 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_shifter_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_shifter_core " "Found entity 1: alu_shifter_core" { } { { "cpu/alu/alu_shifter_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_shifter_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504640 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504640 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_slice.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_slice " "Found entity 1: alu_slice" { } { { "cpu/alu/alu_slice.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_slice.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504641 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504641 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/clk_delay.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_delay " "Found entity 1: clk_delay" { } { { "cpu/control/clk_delay.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/clk_delay.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504642 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504642 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/decode_state.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode_state " "Found entity 1: decode_state" { } { { "cpu/control/decode_state.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/decode_state.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504643 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504643 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/execute.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/execute.v" { { "Info" "ISGN_ENTITY_NAME" "1 execute " "Found entity 1: execute" { } { { "cpu/control/execute.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/execute.v" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504669 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504669 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/interrupts.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v" { { "Info" "ISGN_ENTITY_NAME" "1 interrupts " "Found entity 1: interrupts" { } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504670 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504670 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/ir.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/ir.v" { { "Info" "ISGN_ENTITY_NAME" "1 ir " "Found entity 1: ir" { } { { "cpu/control/ir.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/ir.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504671 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504671 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/memory_ifc.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v" { { "Info" "ISGN_ENTITY_NAME" "1 memory_ifc " "Found entity 1: memory_ifc" { } { { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504672 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504672 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pin_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 pin_control " "Found entity 1: pin_control" { } { { "cpu/control/pin_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pin_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504673 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504673 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pla_decode.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v" { { "Info" "ISGN_ENTITY_NAME" "1 pla_decode " "Found entity 1: pla_decode" { } { { "cpu/control/pla_decode.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pla_decode.v" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504675 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504675 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/resets.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/resets.v" { { "Info" "ISGN_ENTITY_NAME" "1 resets " "Found entity 1: resets" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504675 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504675 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/sequencer.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v" { { "Info" "ISGN_ENTITY_NAME" "1 sequencer " "Found entity 1: sequencer" { } { { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504676 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504676 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_latch " "Found entity 1: address_latch" { } { { "cpu/bus/address_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504677 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504677 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_mux.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_mux " "Found entity 1: address_mux" { } { { "cpu/bus/address_mux.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_mux.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504678 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504678 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_pins " "Found entity 1: address_pins" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504679 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504679 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_control " "Found entity 1: bus_control" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504680 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504680 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_switch " "Found entity 1: bus_switch" { } { { "cpu/bus/bus_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_switch.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504680 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504680 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/control_pins_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_pins_n " "Found entity 1: control_pins_n" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504681 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504681 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_pins " "Found entity 1: data_pins" { } { { "cpu/bus/data_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504682 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504682 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch " "Found entity 1: data_switch" { } { { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504683 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504683 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch_mask.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch_mask " "Found entity 1: data_switch_mask" { } { { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504684 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504684 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec " "Found entity 1: inc_dec" { } { { "cpu/bus/inc_dec.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504685 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504685 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec_2bit.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec_2bit " "Found entity 1: inc_dec_2bit" { } { { "cpu/bus/inc_dec_2bit.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec_2bit.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504685 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504685 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "nRESET nreset z80_top_direct_n.v(19) " "Verilog HDL Declaration information at z80_top_direct_n.v(19): object \"nRESET\" differs only in case from object \"nreset\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 19 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648828504688 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CLK clk z80_top_direct_n.v(22) " "Verilog HDL Declaration information at z80_top_direct_n.v(22): object \"CLK\" differs only in case from object \"clk\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648828504688 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/toplevel/z80_top_direct_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 z80_top_direct_n " "Found entity 1: z80_top_direct_n" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504688 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504688 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_control " "Found entity 1: reg_control" { } { { "cpu/registers/reg_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504689 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504689 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_file.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_file " "Found entity 1: reg_file" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504691 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504691 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_latch " "Found entity 1: reg_latch" { } { { "cpu/registers/reg_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504692 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504692 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/clocks.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/clocks.sv" { { "Info" "ISGN_ENTITY_NAME" "1 clocks " "Found entity 1: clocks" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504692 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504692 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/zx_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 zx_keyboard " "Found entity 1: zx_keyboard" { } { { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504693 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504693 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/video.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/video.sv" { { "Info" "ISGN_ENTITY_NAME" "1 video " "Found entity 1: video" { } { { "ula/video.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/video.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504695 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504695 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ula.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ula.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ula " "Found entity 1: ula" { } { { "ula/ula.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504695 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504695 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ps2_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ps2_keyboard " "Found entity 1: ps2_keyboard" { } { { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504696 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504696 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2c_loader.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_loader-i2c_loader_arch " "Found design unit 1: i2c_loader-i2c_loader_arch" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505020 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2c_loader " "Found entity 1: i2c_loader" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505020 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505020 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2s_intf.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2s_intf-i2s_intf_arch " "Found design unit 1: i2s_intf-i2s_intf_arch" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505021 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2s_intf " "Found entity 1: i2s_intf" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505021 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505021 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_scr.v 1 1 " "Found 1 design units, including 1 entities, in source file rom_scr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_scr " "Found entity 1: rom_scr" { } { { "rom_scr.v" "" { Text "/home/benny/work/fpga/spectrum/rom_scr.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505024 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505024 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_video.v 1 1 " "Found 1 design units, including 1 entities, in source file pll_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_video " "Found entity 1: pll_video" { } { { "pll_video.v" "" { Text "/home/benny/work/fpga/spectrum/pll_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505025 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505025 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_video.v 1 1 " "Found 1 design units, including 1 entities, in source file ram_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram_video " "Found entity 1: ram_video" { } { { "ram_video.v" "" { Text "/home/benny/work/fpga/spectrum/ram_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505026 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505026 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648828505193 ""} -{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[7..4\] spectrum.sv(1) " "Output port \"LED\[7..4\]\" at spectrum.sv(1) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648828505195 "|spectrum"} -{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[1\] spectrum.sv(1) " "Output port \"LED\[1\]\" at spectrum.sv(1) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648828505195 "|spectrum"} -{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "GPIO_1\[33..32\] spectrum.sv(20) " "Output port \"GPIO_1\[33..32\]\" at spectrum.sv(20) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648828505195 "|spectrum"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.sv" "rom" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 135 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505197 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505251 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom/gw03.hex " "Parameter \"init_file\" = \"./rom/gw03.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648828505252 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qh91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qh91 " "Found entity 1: altsyncram_qh91" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505305 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505305 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qh91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated " "Elaborating entity \"altsyncram_qh91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505305 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_c8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_c8a " "Found entity 1: decode_c8a" { } { { "db/decode_c8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_c8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505350 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505350 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_c8a rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode " "Elaborating entity \"decode_c8a\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode\"" { } { { "db/altsyncram_qh91.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 40 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505350 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3nb " "Found entity 1: mux_3nb" { } { { "db/mux_3nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_3nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505395 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505395 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_3nb rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2 " "Elaborating entity \"mux_3nb\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2\"" { } { { "db/altsyncram_qh91.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 41 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505396 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram16 ram16:ram0 " "Elaborating entity \"ram16\" for hierarchy \"ram16:ram0\"" { } { { "spectrum.sv" "ram0" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 157 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505400 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram16:ram0\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505404 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "ram16:ram0\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828505405 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram16:ram0\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram16:ram0\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ula/test_scr.hex " "Parameter \"init_file\" = \"ula/test_scr.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 16384 " "Parameter \"numwords_b\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_b NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_b\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 14 " "Parameter \"widthad_b\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 8 " "Parameter \"width_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648828505406 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_7ti2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_7ti2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_7ti2 " "Found entity 1: altsyncram_7ti2" { } { { "db/altsyncram_7ti2.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505460 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505460 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_7ti2 ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated " "Elaborating entity \"altsyncram_7ti2\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505460 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_jsa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_jsa " "Found entity 1: decode_jsa" { } { { "db/decode_jsa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_jsa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505507 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505507 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_jsa ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2 " "Elaborating entity \"decode_jsa\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2\"" { } { { "db/altsyncram_7ti2.tdf" "decode2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505508 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram32 ram32:ram1 " "Elaborating entity \"ram32\" for hierarchy \"ram32:ram1\"" { } { { "spectrum.sv" "ram1" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505514 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram32:ram1\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505518 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "ram32:ram1\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram32:ram1\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram32:ram1\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32768 " "Parameter \"numwords_a\" = \"32768\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 15 " "Parameter \"widthad_a\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648828505519 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_g9i1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_g9i1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_g9i1 " "Found entity 1: altsyncram_g9i1" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505573 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505573 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_g9i1 ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated " "Elaborating entity \"altsyncram_g9i1\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505573 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_msa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_msa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_msa " "Found entity 1: decode_msa" { } { { "db/decode_msa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_msa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505618 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505618 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_msa ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3 " "Elaborating entity \"decode_msa\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3\"" { } { { "db/altsyncram_g9i1.tdf" "decode3" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505619 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_f8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_f8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_f8a " "Found entity 1: decode_f8a" { } { { "db/decode_f8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_f8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505662 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505662 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_f8a ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode " "Elaborating entity \"decode_f8a\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode\"" { } { { "db/altsyncram_g9i1.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 45 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505662 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_6nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_6nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_6nb " "Found entity 1: mux_6nb" { } { { "db/mux_6nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_6nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505706 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505706 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_6nb ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2 " "Elaborating entity \"mux_6nb\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2\"" { } { { "db/altsyncram_g9i1.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 46 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505707 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ula ula:ula_ " "Elaborating entity \"ula\" for hierarchy \"ula:ula_\"" { } { { "spectrum.sv" "ula_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 229 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505709 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll ula:ula_\|pll:pll_ " "Elaborating entity \"pll\" for hierarchy \"ula:ula_\|pll:pll_\"" { } { { "ula/ula.sv" "pll_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505711 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "altpll_component" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505739 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborated megafunction instantiation \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Instantiated megafunction \"ula:ula_\|pll:pll_\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 2000 " "Parameter \"clk0_divide_by\" = \"2000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 1007 " "Parameter \"clk0_multiply_by\" = \"1007\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 25 " "Parameter \"clk1_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 7 " "Parameter \"clk1_multiply_by\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 25 " "Parameter \"clk2_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_duty_cycle 50 " "Parameter \"clk2_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 12 " "Parameter \"clk2_multiply_by\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_USED " "Parameter \"port_clk2\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock OFF " "Parameter \"self_reset_on_loss_lock\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648828505744 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pll_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_altpll " "Found entity 1: pll_altpll" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505797 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505797 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_altpll ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated " "Elaborating entity \"pll_altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505798 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clocks ula:ula_\|clocks:clocks_ " "Elaborating entity \"clocks\" for hierarchy \"ula:ula_\|clocks:clocks_\"" { } { { "ula/ula.sv" "clocks_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505800 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_loader ula:ula_\|i2c_loader:i2c_loader_ " "Elaborating entity \"i2c_loader\" for hierarchy \"ula:ula_\|i2c_loader:i2c_loader_\"" { } { { "ula/ula.sv" "i2c_loader_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 124 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505801 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2s_intf ula:ula_\|i2s_intf:i2s_intf_ " "Elaborating entity \"i2s_intf\" for hierarchy \"ula:ula_\|i2s_intf:i2s_intf_\"" { } { { "ula/ula.sv" "i2s_intf_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 144 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505803 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "video ula:ula_\|video:video_ " "Elaborating entity \"video\" for hierarchy \"ula:ula_\|video:video_\"" { } { { "ula/ula.sv" "video_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 158 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505805 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ps2_keyboard ula:ula_\|ps2_keyboard:ps2_keyboard_ " "Elaborating entity \"ps2_keyboard\" for hierarchy \"ula:ula_\|ps2_keyboard:ps2_keyboard_\"" { } { { "ula/ula.sv" "ps2_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 167 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505806 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zx_keyboard ula:ula_\|zx_keyboard:zx_keyboard_ " "Elaborating entity \"zx_keyboard\" for hierarchy \"ula:ula_\|zx_keyboard:zx_keyboard_\"" { } { { "ula/ula.sv" "zx_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505807 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "z80_top_direct_n z80_top_direct_n:z80_ " "Elaborating entity \"z80_top_direct_n\" for hierarchy \"z80_top_direct_n:z80_\"" { } { { "spectrum.sv" "z80_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 273 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505811 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_delay z80_top_direct_n:z80_\|clk_delay:clk_delay_ " "Elaborating entity \"clk_delay\" for hierarchy \"z80_top_direct_n:z80_\|clk_delay:clk_delay_\"" { } { { "cpu/toplevel/coremodules.vh" "clk_delay_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 20 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505814 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_state z80_top_direct_n:z80_\|decode_state:decode_state_ " "Elaborating entity \"decode_state\" for hierarchy \"z80_top_direct_n:z80_\|decode_state:decode_state_\"" { } { { "cpu/toplevel/coremodules.vh" "decode_state_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 46 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505814 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "execute z80_top_direct_n:z80_\|execute:execute_ " "Elaborating entity \"execute\" for hierarchy \"z80_top_direct_n:z80_\|execute:execute_\"" { } { { "cpu/toplevel/coremodules.vh" "execute_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 180 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505815 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "interrupts z80_top_direct_n:z80_\|interrupts:interrupts_ " "Elaborating entity \"interrupts\" for hierarchy \"z80_top_direct_n:z80_\|interrupts:interrupts_\"" { } { { "cpu/toplevel/coremodules.vh" "interrupts_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 199 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505830 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ir z80_top_direct_n:z80_\|ir:ir_ " "Elaborating entity \"ir\" for hierarchy \"z80_top_direct_n:z80_\|ir:ir_\"" { } { { "cpu/toplevel/coremodules.vh" "ir_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 208 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505830 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pin_control z80_top_direct_n:z80_\|pin_control:pin_control_ " "Elaborating entity \"pin_control\" for hierarchy \"z80_top_direct_n:z80_\|pin_control:pin_control_\"" { } { { "cpu/toplevel/coremodules.vh" "pin_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 223 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505831 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pla_decode z80_top_direct_n:z80_\|pla_decode:pla_decode_ " "Elaborating entity \"pla_decode\" for hierarchy \"z80_top_direct_n:z80_\|pla_decode:pla_decode_\"" { } { { "cpu/toplevel/coremodules.vh" "pla_decode_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 229 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505832 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "resets z80_top_direct_n:z80_\|resets:resets_ " "Elaborating entity \"resets\" for hierarchy \"z80_top_direct_n:z80_\|resets:resets_\"" { } { { "cpu/toplevel/coremodules.vh" "resets_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 240 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505834 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "memory_ifc z80_top_direct_n:z80_\|memory_ifc:memory_ifc_ " "Elaborating entity \"memory_ifc\" for hierarchy \"z80_top_direct_n:z80_\|memory_ifc:memory_ifc_\"" { } { { "cpu/toplevel/coremodules.vh" "memory_ifc_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 264 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505835 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sequencer z80_top_direct_n:z80_\|sequencer:sequencer_ " "Elaborating entity \"sequencer\" for hierarchy \"z80_top_direct_n:z80_\|sequencer:sequencer_\"" { } { { "cpu/toplevel/coremodules.vh" "sequencer_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 286 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505836 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_control z80_top_direct_n:z80_\|alu_control:alu_control_ " "Elaborating entity \"alu_control\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 326 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505836 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_4 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux " "Elaborating entity \"alu_mux_4\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_cond_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 205 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505837 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_8 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux " "Elaborating entity \"alu_mux_8\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_shift_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 227 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505839 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_select z80_top_direct_n:z80_\|alu_select:alu_select_ " "Elaborating entity \"alu_select\" for hierarchy \"z80_top_direct_n:z80_\|alu_select:alu_select_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_select_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 363 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505839 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_flags z80_top_direct_n:z80_\|alu_flags:alu_flags_ " "Elaborating entity \"alu_flags\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_flags_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 405 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505840 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2 z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf " "Elaborating entity \"alu_mux_2\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf\"" { } { { "cpu/alu/alu_flags.v" "b2v_inst_mux_cf" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 344 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505841 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu z80_top_direct_n:z80_\|alu:alu_ " "Elaborating entity \"alu\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 448 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505842 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_core z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core " "Elaborating entity \"alu_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\"" { } { { "cpu/alu/alu.v" "b2v_core" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505844 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_slice z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0 " "Elaborating entity \"alu_slice\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0\"" { } { { "cpu/alu/alu_core.v" "b2v_alu_slice_bit_0" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 61 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505845 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_bit_select z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select " "Elaborating entity \"alu_bit_select\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\"" { } { { "cpu/alu/alu.v" "b2v_input_bit_select" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 186 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505847 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_shifter_core z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift " "Elaborating entity \"alu_shifter_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\"" { } { { "cpu/alu/alu.v" "b2v_input_shift" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 197 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505848 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high " "Elaborating entity \"alu_mux_2z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_high" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 318 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505848 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_3z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low " "Elaborating entity \"alu_mux_3z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_low" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 328 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505849 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_prep_daa z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa " "Elaborating entity \"alu_prep_daa\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa\"" { } { { "cpu/alu/alu.v" "b2v_prep_daa" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 364 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505851 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_file z80_top_direct_n:z80_\|reg_file:reg_file_ " "Elaborating entity \"reg_file\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_file_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 484 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505852 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_latch z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi " "Elaborating entity \"reg_latch\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\"" { } { { "cpu/registers/reg_file.v" "b2v_latch_af2_hi" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 279 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505853 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_control z80_top_direct_n:z80_\|reg_control:reg_control_ " "Elaborating entity \"reg_control\" for hierarchy \"z80_top_direct_n:z80_\|reg_control:reg_control_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 531 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505866 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_latch z80_top_direct_n:z80_\|address_latch:address_latch_ " "Elaborating entity \"address_latch\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\"" { } { { "cpu/toplevel/coremodules.vh" "address_latch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 547 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505867 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_mux z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7 " "Elaborating entity \"address_mux\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7\"" { } { { "cpu/bus/address_latch.v" "b2v_inst7" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 106 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505869 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec " "Elaborating entity \"inc_dec\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\"" { } { { "cpu/bus/address_latch.v" "b2v_inst_inc_dec" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505870 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec_2bit z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0 " "Elaborating entity \"inc_dec_2bit\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0\"" { } { { "cpu/bus/inc_dec.v" "b2v_dual_adder_0" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 80 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505871 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_control z80_top_direct_n:z80_\|bus_control:bus_control_ " "Elaborating entity \"bus_control\" for hierarchy \"z80_top_direct_n:z80_\|bus_control:bus_control_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 553 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505875 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_switch z80_top_direct_n:z80_\|bus_switch:bus_switch_ " "Elaborating entity \"bus_switch\" for hierarchy \"z80_top_direct_n:z80_\|bus_switch:bus_switch_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_switch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 566 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505876 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch z80_top_direct_n:z80_\|data_switch:sw2_ " "Elaborating entity \"data_switch\" for hierarchy \"z80_top_direct_n:z80_\|data_switch:sw2_\"" { } { { "cpu/toplevel/core.vh" "sw2_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 36 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505876 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch_mask z80_top_direct_n:z80_\|data_switch_mask:sw1_ " "Elaborating entity \"data_switch_mask\" for hierarchy \"z80_top_direct_n:z80_\|data_switch_mask:sw1_\"" { } { { "cpu/toplevel/core.vh" "sw1_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 39 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505877 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_pins z80_top_direct_n:z80_\|address_pins:address_pins_ " "Elaborating entity \"address_pins\" for hierarchy \"z80_top_direct_n:z80_\|address_pins:address_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "address_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 41 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505878 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_pins z80_top_direct_n:z80_\|data_pins:data_pins_ " "Elaborating entity \"data_pins\" for hierarchy \"z80_top_direct_n:z80_\|data_pins:data_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "data_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 51 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505879 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_pins_n z80_top_direct_n:z80_\|control_pins_n:control_pins_ " "Elaborating entity \"control_pins_n\" for hierarchy \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "control_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505880 ""} -{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1648828510554 ""} -{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\]\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\] ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|address_reg_a\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\]\" to the node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|address_reg_a\[1\]\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\] ExtRamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\]\" to the node \"ExtRamWE\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR RamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR\" to the node \"RamWE\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 77 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD Equal2 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD\" to the node \"Equal2\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ Equal2 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ\" to the node \"Equal2\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1648828510655 ""} -{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[7\] z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[0\] z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[6\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[0\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"D\[0\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[1\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1 " "Converted the fan-out from the tri-state buffer \"D\[1\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[2\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2 " "Converted the fan-out from the tri-state buffer \"D\[2\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[3\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3 " "Converted the fan-out from the tri-state buffer \"D\[3\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[4\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4 " "Converted the fan-out from the tri-state buffer \"D\[4\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[5\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5 " "Converted the fan-out from the tri-state buffer \"D\[5\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[6\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6 " "Converted the fan-out from the tri-state buffer \"D\[6\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[7\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7 " "Converted the fan-out from the tri-state buffer \"D\[7\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1648828510661 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 127 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 201 -1 0 } } { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 93 -1 0 } } { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 97 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 108 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 109 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 33 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 59 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1648828510688 ""} -{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1648828510688 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[1\] GND " "Pin \"LED\[1\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|LED[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[4\] GND " "Pin \"LED\[4\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|LED[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[5\] GND " "Pin \"LED\[5\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|LED[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[6\] GND " "Pin \"LED\[6\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|LED[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[7\] GND " "Pin \"LED\[7\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|LED[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[24\] VCC " "Pin \"GPIO_1\[24\]\" is stuck at VCC" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|GPIO_1[24]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[32\] GND " "Pin \"GPIO_1\[32\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|GPIO_1[32]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[33\] GND " "Pin \"GPIO_1\[33\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|GPIO_1[33]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1648828513991 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648828514385 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1648828517029 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1648828517124 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648828517378 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828517378 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[0\] " "No output dependent on input pin \"SW\[0\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828517630 "|spectrum|SW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "No output dependent on input pin \"SW\[3\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828517630 "|spectrum|SW[3]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1648828517630 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "2747 " "Implemented 2747 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648828517630 ""} { "Info" "ICUT_CUT_TM_OPINS" "62 " "Implemented 62 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648828517630 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "2 " "Implemented 2 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1648828517630 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2607 " "Implemented 2607 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648828517630 ""} { "Info" "ICUT_CUT_TM_RAMS" "64 " "Implemented 64 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648828517630 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Quartus II" 0 -1 1648828517630 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648828517630 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 110 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 110 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "441 " "Peak virtual memory: 441 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828517650 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 1 18:55:17 2022 " "Processing ended: Fri Apr 1 18:55:17 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828517650 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828517650 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828517650 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648828517650 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648900231311 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648900231312 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:50:31 2022 " "Processing started: Sat Apr 2 14:50:31 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648900231312 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648900231312 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648900231312 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648900231497 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.sv 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.sv" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231565 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231565 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231566 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231566 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram16.v 1 1 " "Found 1 design units, including 1 entities, in source file ram16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram16 " "Found entity 1: ram16" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231567 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231567 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram32.v 1 1 " "Found 1 design units, including 1 entities, in source file ram32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram32 " "Found entity 1: ram32" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231568 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231568 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Found entity 1: pll" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231569 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231569 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Found entity 1: alu" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231570 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231570 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_bit_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_bit_select " "Found entity 1: alu_bit_select" { } { { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231571 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231571 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_control " "Found entity 1: alu_control" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231572 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231572 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_core " "Found entity 1: alu_core" { } { { "cpu/alu/alu_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231573 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231573 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_flags.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_flags " "Found entity 1: alu_flags" { } { { "cpu/alu/alu_flags.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231574 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231574 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2 " "Found entity 1: alu_mux_2" { } { { "cpu/alu/alu_mux_2.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231575 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231575 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2z " "Found entity 1: alu_mux_2z" { } { { "cpu/alu/alu_mux_2z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231575 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231575 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_3z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_3z " "Found entity 1: alu_mux_3z" { } { { "cpu/alu/alu_mux_3z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_3z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231576 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231576 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_4.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_4 " "Found entity 1: alu_mux_4" { } { { "cpu/alu/alu_mux_4.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_4.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231577 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231577 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_8.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_8 " "Found entity 1: alu_mux_8" { } { { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231577 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231577 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_prep_daa.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_prep_daa " "Found entity 1: alu_prep_daa" { } { { "cpu/alu/alu_prep_daa.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_prep_daa.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231578 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231578 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_select " "Found entity 1: alu_select" { } { { "cpu/alu/alu_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231579 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231579 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_shifter_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_shifter_core " "Found entity 1: alu_shifter_core" { } { { "cpu/alu/alu_shifter_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_shifter_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231580 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231580 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_slice.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_slice " "Found entity 1: alu_slice" { } { { "cpu/alu/alu_slice.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_slice.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231581 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231581 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/clk_delay.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_delay " "Found entity 1: clk_delay" { } { { "cpu/control/clk_delay.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/clk_delay.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231581 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231581 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/decode_state.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode_state " "Found entity 1: decode_state" { } { { "cpu/control/decode_state.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/decode_state.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231582 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231582 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/execute.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/execute.v" { { "Info" "ISGN_ENTITY_NAME" "1 execute " "Found entity 1: execute" { } { { "cpu/control/execute.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/execute.v" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231607 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231607 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/interrupts.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v" { { "Info" "ISGN_ENTITY_NAME" "1 interrupts " "Found entity 1: interrupts" { } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231608 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231608 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/ir.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/ir.v" { { "Info" "ISGN_ENTITY_NAME" "1 ir " "Found entity 1: ir" { } { { "cpu/control/ir.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/ir.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231609 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231609 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/memory_ifc.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v" { { "Info" "ISGN_ENTITY_NAME" "1 memory_ifc " "Found entity 1: memory_ifc" { } { { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231610 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231610 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pin_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 pin_control " "Found entity 1: pin_control" { } { { "cpu/control/pin_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pin_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231611 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231611 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pla_decode.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v" { { "Info" "ISGN_ENTITY_NAME" "1 pla_decode " "Found entity 1: pla_decode" { } { { "cpu/control/pla_decode.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pla_decode.v" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231612 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231612 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/resets.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/resets.v" { { "Info" "ISGN_ENTITY_NAME" "1 resets " "Found entity 1: resets" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231613 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231613 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/sequencer.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v" { { "Info" "ISGN_ENTITY_NAME" "1 sequencer " "Found entity 1: sequencer" { } { { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231614 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231614 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_latch " "Found entity 1: address_latch" { } { { "cpu/bus/address_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231615 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231615 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_mux.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_mux " "Found entity 1: address_mux" { } { { "cpu/bus/address_mux.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_mux.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231615 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231615 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_pins " "Found entity 1: address_pins" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231616 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231616 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_control " "Found entity 1: bus_control" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231617 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231617 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_switch " "Found entity 1: bus_switch" { } { { "cpu/bus/bus_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_switch.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231618 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231618 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/control_pins_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_pins_n " "Found entity 1: control_pins_n" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231618 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231618 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_pins " "Found entity 1: data_pins" { } { { "cpu/bus/data_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231619 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231619 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch " "Found entity 1: data_switch" { } { { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231620 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231620 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch_mask.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch_mask " "Found entity 1: data_switch_mask" { } { { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231621 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231621 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec " "Found entity 1: inc_dec" { } { { "cpu/bus/inc_dec.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231622 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231622 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec_2bit.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec_2bit " "Found entity 1: inc_dec_2bit" { } { { "cpu/bus/inc_dec_2bit.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec_2bit.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231622 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231622 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "nRESET nreset z80_top_direct_n.v(19) " "Verilog HDL Declaration information at z80_top_direct_n.v(19): object \"nRESET\" differs only in case from object \"nreset\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 19 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648900231625 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CLK clk z80_top_direct_n.v(22) " "Verilog HDL Declaration information at z80_top_direct_n.v(22): object \"CLK\" differs only in case from object \"clk\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648900231625 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/toplevel/z80_top_direct_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 z80_top_direct_n " "Found entity 1: z80_top_direct_n" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231625 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231625 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_control " "Found entity 1: reg_control" { } { { "cpu/registers/reg_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231626 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231626 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_file.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_file " "Found entity 1: reg_file" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231627 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231627 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_latch " "Found entity 1: reg_latch" { } { { "cpu/registers/reg_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231628 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231628 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/clocks.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/clocks.sv" { { "Info" "ISGN_ENTITY_NAME" "1 clocks " "Found entity 1: clocks" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231629 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231629 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/zx_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 zx_keyboard " "Found entity 1: zx_keyboard" { } { { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231630 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231630 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/video.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/video.sv" { { "Info" "ISGN_ENTITY_NAME" "1 video " "Found entity 1: video" { } { { "ula/video.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/video.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231631 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231631 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ula.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ula.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ula " "Found entity 1: ula" { } { { "ula/ula.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231632 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231632 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ps2_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ps2_keyboard " "Found entity 1: ps2_keyboard" { } { { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231633 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231633 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2c_loader.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_loader-i2c_loader_arch " "Found design unit 1: i2c_loader-i2c_loader_arch" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231920 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2c_loader " "Found entity 1: i2c_loader" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231920 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231920 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2s_intf.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2s_intf-i2s_intf_arch " "Found design unit 1: i2s_intf-i2s_intf_arch" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231921 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2s_intf " "Found entity 1: i2s_intf" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231921 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231921 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_scr.v 1 1 " "Found 1 design units, including 1 entities, in source file rom_scr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_scr " "Found entity 1: rom_scr" { } { { "rom_scr.v" "" { Text "/home/benny/work/fpga/spectrum/rom_scr.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231924 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231924 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_video.v 1 1 " "Found 1 design units, including 1 entities, in source file pll_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_video " "Found entity 1: pll_video" { } { { "pll_video.v" "" { Text "/home/benny/work/fpga/spectrum/pll_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231925 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231925 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_video.v 1 1 " "Found 1 design units, including 1 entities, in source file ram_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram_video " "Found entity 1: ram_video" { } { { "ram_video.v" "" { Text "/home/benny/work/fpga/spectrum/ram_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231926 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231926 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram.vhdl 2 1 " "Found 2 design units, including 1 entities, in source file sdram.vhdl" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sdram_controller-rtl " "Found design unit 1: sdram_controller-rtl" { } { { "sdram.vhdl" "" { Text "/home/benny/work/fpga/spectrum/sdram.vhdl" 42 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231928 ""} { "Info" "ISGN_ENTITY_NAME" "1 sdram_controller " "Found entity 1: sdram_controller" { } { { "sdram.vhdl" "" { Text "/home/benny/work/fpga/spectrum/sdram.vhdl" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231928 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231928 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_clk_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_clk_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_clk_gen " "Found entity 1: sdram_clk_gen" { } { { "sdram_clk_gen.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900231929 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900231929 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648900232089 ""} +{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[7..4\] spectrum.sv(1) " "Output port \"LED\[7..4\]\" at spectrum.sv(1) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648900232093 "|spectrum"} +{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[1\] spectrum.sv(1) " "Output port \"LED\[1\]\" at spectrum.sv(1) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648900232093 "|spectrum"} +{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "GPIO_1\[33..32\] spectrum.sv(20) " "Output port \"GPIO_1\[33..32\]\" at spectrum.sv(20) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648900232093 "|spectrum"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.sv" "rom" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 147 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232106 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232153 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom/gw03.hex " "Parameter \"init_file\" = \"./rom/gw03.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232154 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648900232154 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qh91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qh91 " "Found entity 1: altsyncram_qh91" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900232201 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900232201 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qh91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated " "Elaborating entity \"altsyncram_qh91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232202 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_c8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_c8a " "Found entity 1: decode_c8a" { } { { "db/decode_c8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_c8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900232243 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900232243 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_c8a rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode " "Elaborating entity \"decode_c8a\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode\"" { } { { "db/altsyncram_qh91.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 40 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232244 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3nb " "Found entity 1: mux_3nb" { } { { "db/mux_3nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_3nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900232285 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900232285 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_3nb rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2 " "Elaborating entity \"mux_3nb\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2\"" { } { { "db/altsyncram_qh91.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 41 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232285 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram16 ram16:ram0 " "Elaborating entity \"ram16\" for hierarchy \"ram16:ram0\"" { } { { "spectrum.sv" "ram0" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232288 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram16:ram0\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232293 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "ram16:ram0\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram16:ram0\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram16:ram0\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ula/test_scr.hex " "Parameter \"init_file\" = \"ula/test_scr.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 16384 " "Parameter \"numwords_b\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_b NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_b\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 14 " "Parameter \"widthad_b\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 8 " "Parameter \"width_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232294 ""} } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648900232294 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_7ti2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_7ti2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_7ti2 " "Found entity 1: altsyncram_7ti2" { } { { "db/altsyncram_7ti2.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900232342 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900232342 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_7ti2 ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated " "Elaborating entity \"altsyncram_7ti2\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232342 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_jsa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_jsa " "Found entity 1: decode_jsa" { } { { "db/decode_jsa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_jsa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900232384 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900232384 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_jsa ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2 " "Elaborating entity \"decode_jsa\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2\"" { } { { "db/altsyncram_7ti2.tdf" "decode2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232384 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram32 ram32:ram1 " "Elaborating entity \"ram32\" for hierarchy \"ram32:ram1\"" { } { { "spectrum.sv" "ram1" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232390 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram32:ram1\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232394 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "ram32:ram1\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram32:ram1\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram32:ram1\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32768 " "Parameter \"numwords_a\" = \"32768\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 15 " "Parameter \"widthad_a\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232395 ""} } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648900232395 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_g9i1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_g9i1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_g9i1 " "Found entity 1: altsyncram_g9i1" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900232444 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900232444 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_g9i1 ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated " "Elaborating entity \"altsyncram_g9i1\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232444 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_msa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_msa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_msa " "Found entity 1: decode_msa" { } { { "db/decode_msa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_msa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900232486 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900232486 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_msa ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3 " "Elaborating entity \"decode_msa\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3\"" { } { { "db/altsyncram_g9i1.tdf" "decode3" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232486 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_f8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_f8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_f8a " "Found entity 1: decode_f8a" { } { { "db/decode_f8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_f8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900232526 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900232526 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_f8a ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode " "Elaborating entity \"decode_f8a\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode\"" { } { { "db/altsyncram_g9i1.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 45 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232527 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_6nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_6nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_6nb " "Found entity 1: mux_6nb" { } { { "db/mux_6nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_6nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900232568 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900232568 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_6nb ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2 " "Elaborating entity \"mux_6nb\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2\"" { } { { "db/altsyncram_g9i1.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 46 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232568 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_controller sdram_controller:sdram_ " "Elaborating entity \"sdram_controller\" for hierarchy \"sdram_controller:sdram_\"" { } { { "spectrum.sv" "sdram_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232570 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_clk_gen sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll " "Elaborating entity \"sdram_clk_gen\" for hierarchy \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\"" { } { { "sdram.vhdl" "sdram_clk_pll" { Text "/home/benny/work/fpga/spectrum/sdram.vhdl" 145 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232574 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\"" { } { { "sdram_clk_gen.v" "altpll_component" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 94 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232601 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component " "Elaborated megafunction instantiation \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\"" { } { { "sdram_clk_gen.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 94 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component " "Instantiated megafunction \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Parameter \"clk0_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 2 " "Parameter \"clk0_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 1 " "Parameter \"clk1_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 2 " "Parameter \"clk1_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 3000 " "Parameter \"clk1_phase_shift\" = \"3000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=sdram_clk_gen " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=sdram_clk_gen\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Parameter \"port_locked\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232605 ""} } { { "sdram_clk_gen.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 94 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648900232605 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sdram_clk_gen_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/sdram_clk_gen_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_clk_gen_altpll " "Found entity 1: sdram_clk_gen_altpll" { } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900232653 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900232653 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_clk_gen_altpll sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated " "Elaborating entity \"sdram_clk_gen_altpll\" for hierarchy \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232654 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ula ula:ula_ " "Elaborating entity \"ula\" for hierarchy \"ula:ula_\"" { } { { "spectrum.sv" "ula_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 303 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232656 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll ula:ula_\|pll:pll_ " "Elaborating entity \"pll\" for hierarchy \"ula:ula_\|pll:pll_\"" { } { { "ula/ula.sv" "pll_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232658 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "altpll_component" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232666 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborated megafunction instantiation \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Instantiated megafunction \"ula:ula_\|pll:pll_\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 2000 " "Parameter \"clk0_divide_by\" = \"2000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 1007 " "Parameter \"clk0_multiply_by\" = \"1007\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 25 " "Parameter \"clk1_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 7 " "Parameter \"clk1_multiply_by\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 25 " "Parameter \"clk2_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_duty_cycle 50 " "Parameter \"clk2_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 12 " "Parameter \"clk2_multiply_by\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_USED " "Parameter \"port_clk2\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock OFF " "Parameter \"self_reset_on_loss_lock\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232670 ""} } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648900232670 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pll_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_altpll " "Found entity 1: pll_altpll" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648900232717 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648900232717 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_altpll ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated " "Elaborating entity \"pll_altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232718 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clocks ula:ula_\|clocks:clocks_ " "Elaborating entity \"clocks\" for hierarchy \"ula:ula_\|clocks:clocks_\"" { } { { "ula/ula.sv" "clocks_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232719 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_loader ula:ula_\|i2c_loader:i2c_loader_ " "Elaborating entity \"i2c_loader\" for hierarchy \"ula:ula_\|i2c_loader:i2c_loader_\"" { } { { "ula/ula.sv" "i2c_loader_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 124 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232720 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2s_intf ula:ula_\|i2s_intf:i2s_intf_ " "Elaborating entity \"i2s_intf\" for hierarchy \"ula:ula_\|i2s_intf:i2s_intf_\"" { } { { "ula/ula.sv" "i2s_intf_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 144 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232722 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "video ula:ula_\|video:video_ " "Elaborating entity \"video\" for hierarchy \"ula:ula_\|video:video_\"" { } { { "ula/ula.sv" "video_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 158 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232723 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ps2_keyboard ula:ula_\|ps2_keyboard:ps2_keyboard_ " "Elaborating entity \"ps2_keyboard\" for hierarchy \"ula:ula_\|ps2_keyboard:ps2_keyboard_\"" { } { { "ula/ula.sv" "ps2_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 167 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232725 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zx_keyboard ula:ula_\|zx_keyboard:zx_keyboard_ " "Elaborating entity \"zx_keyboard\" for hierarchy \"ula:ula_\|zx_keyboard:zx_keyboard_\"" { } { { "ula/ula.sv" "zx_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232726 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "z80_top_direct_n z80_top_direct_n:z80_ " "Elaborating entity \"z80_top_direct_n\" for hierarchy \"z80_top_direct_n:z80_\"" { } { { "spectrum.sv" "z80_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 347 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232729 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_delay z80_top_direct_n:z80_\|clk_delay:clk_delay_ " "Elaborating entity \"clk_delay\" for hierarchy \"z80_top_direct_n:z80_\|clk_delay:clk_delay_\"" { } { { "cpu/toplevel/coremodules.vh" "clk_delay_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 20 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232732 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_state z80_top_direct_n:z80_\|decode_state:decode_state_ " "Elaborating entity \"decode_state\" for hierarchy \"z80_top_direct_n:z80_\|decode_state:decode_state_\"" { } { { "cpu/toplevel/coremodules.vh" "decode_state_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 46 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232733 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "execute z80_top_direct_n:z80_\|execute:execute_ " "Elaborating entity \"execute\" for hierarchy \"z80_top_direct_n:z80_\|execute:execute_\"" { } { { "cpu/toplevel/coremodules.vh" "execute_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 180 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232733 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "interrupts z80_top_direct_n:z80_\|interrupts:interrupts_ " "Elaborating entity \"interrupts\" for hierarchy \"z80_top_direct_n:z80_\|interrupts:interrupts_\"" { } { { "cpu/toplevel/coremodules.vh" "interrupts_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 199 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232747 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ir z80_top_direct_n:z80_\|ir:ir_ " "Elaborating entity \"ir\" for hierarchy \"z80_top_direct_n:z80_\|ir:ir_\"" { } { { "cpu/toplevel/coremodules.vh" "ir_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 208 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232748 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pin_control z80_top_direct_n:z80_\|pin_control:pin_control_ " "Elaborating entity \"pin_control\" for hierarchy \"z80_top_direct_n:z80_\|pin_control:pin_control_\"" { } { { "cpu/toplevel/coremodules.vh" "pin_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 223 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232748 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pla_decode z80_top_direct_n:z80_\|pla_decode:pla_decode_ " "Elaborating entity \"pla_decode\" for hierarchy \"z80_top_direct_n:z80_\|pla_decode:pla_decode_\"" { } { { "cpu/toplevel/coremodules.vh" "pla_decode_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 229 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232749 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "resets z80_top_direct_n:z80_\|resets:resets_ " "Elaborating entity \"resets\" for hierarchy \"z80_top_direct_n:z80_\|resets:resets_\"" { } { { "cpu/toplevel/coremodules.vh" "resets_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 240 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232751 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "memory_ifc z80_top_direct_n:z80_\|memory_ifc:memory_ifc_ " "Elaborating entity \"memory_ifc\" for hierarchy \"z80_top_direct_n:z80_\|memory_ifc:memory_ifc_\"" { } { { "cpu/toplevel/coremodules.vh" "memory_ifc_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 264 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232752 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sequencer z80_top_direct_n:z80_\|sequencer:sequencer_ " "Elaborating entity \"sequencer\" for hierarchy \"z80_top_direct_n:z80_\|sequencer:sequencer_\"" { } { { "cpu/toplevel/coremodules.vh" "sequencer_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 286 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232753 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_control z80_top_direct_n:z80_\|alu_control:alu_control_ " "Elaborating entity \"alu_control\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 326 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232753 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_4 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux " "Elaborating entity \"alu_mux_4\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_cond_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 205 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232754 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_8 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux " "Elaborating entity \"alu_mux_8\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_shift_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 227 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232755 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_select z80_top_direct_n:z80_\|alu_select:alu_select_ " "Elaborating entity \"alu_select\" for hierarchy \"z80_top_direct_n:z80_\|alu_select:alu_select_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_select_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 363 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232756 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_flags z80_top_direct_n:z80_\|alu_flags:alu_flags_ " "Elaborating entity \"alu_flags\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_flags_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 405 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232757 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2 z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf " "Elaborating entity \"alu_mux_2\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf\"" { } { { "cpu/alu/alu_flags.v" "b2v_inst_mux_cf" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 344 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232758 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu z80_top_direct_n:z80_\|alu:alu_ " "Elaborating entity \"alu\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 448 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232759 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_core z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core " "Elaborating entity \"alu_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\"" { } { { "cpu/alu/alu.v" "b2v_core" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232760 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_slice z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0 " "Elaborating entity \"alu_slice\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0\"" { } { { "cpu/alu/alu_core.v" "b2v_alu_slice_bit_0" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 61 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232761 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_bit_select z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select " "Elaborating entity \"alu_bit_select\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\"" { } { { "cpu/alu/alu.v" "b2v_input_bit_select" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 186 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232763 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_shifter_core z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift " "Elaborating entity \"alu_shifter_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\"" { } { { "cpu/alu/alu.v" "b2v_input_shift" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 197 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232764 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high " "Elaborating entity \"alu_mux_2z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_high" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 318 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232765 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_3z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low " "Elaborating entity \"alu_mux_3z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_low" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 328 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232765 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_prep_daa z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa " "Elaborating entity \"alu_prep_daa\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa\"" { } { { "cpu/alu/alu.v" "b2v_prep_daa" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 364 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232767 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_file z80_top_direct_n:z80_\|reg_file:reg_file_ " "Elaborating entity \"reg_file\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_file_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 484 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232768 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_latch z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi " "Elaborating entity \"reg_latch\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\"" { } { { "cpu/registers/reg_file.v" "b2v_latch_af2_hi" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 279 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232769 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_control z80_top_direct_n:z80_\|reg_control:reg_control_ " "Elaborating entity \"reg_control\" for hierarchy \"z80_top_direct_n:z80_\|reg_control:reg_control_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 531 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232781 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_latch z80_top_direct_n:z80_\|address_latch:address_latch_ " "Elaborating entity \"address_latch\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\"" { } { { "cpu/toplevel/coremodules.vh" "address_latch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 547 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232782 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_mux z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7 " "Elaborating entity \"address_mux\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7\"" { } { { "cpu/bus/address_latch.v" "b2v_inst7" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 106 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232784 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec " "Elaborating entity \"inc_dec\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\"" { } { { "cpu/bus/address_latch.v" "b2v_inst_inc_dec" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232784 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec_2bit z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0 " "Elaborating entity \"inc_dec_2bit\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0\"" { } { { "cpu/bus/inc_dec.v" "b2v_dual_adder_0" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 80 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232785 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_control z80_top_direct_n:z80_\|bus_control:bus_control_ " "Elaborating entity \"bus_control\" for hierarchy \"z80_top_direct_n:z80_\|bus_control:bus_control_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 553 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232789 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_switch z80_top_direct_n:z80_\|bus_switch:bus_switch_ " "Elaborating entity \"bus_switch\" for hierarchy \"z80_top_direct_n:z80_\|bus_switch:bus_switch_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_switch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 566 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232790 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch z80_top_direct_n:z80_\|data_switch:sw2_ " "Elaborating entity \"data_switch\" for hierarchy \"z80_top_direct_n:z80_\|data_switch:sw2_\"" { } { { "cpu/toplevel/core.vh" "sw2_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 36 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232790 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch_mask z80_top_direct_n:z80_\|data_switch_mask:sw1_ " "Elaborating entity \"data_switch_mask\" for hierarchy \"z80_top_direct_n:z80_\|data_switch_mask:sw1_\"" { } { { "cpu/toplevel/core.vh" "sw1_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 39 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232791 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_pins z80_top_direct_n:z80_\|address_pins:address_pins_ " "Elaborating entity \"address_pins\" for hierarchy \"z80_top_direct_n:z80_\|address_pins:address_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "address_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 41 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232792 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_pins z80_top_direct_n:z80_\|data_pins:data_pins_ " "Elaborating entity \"data_pins\" for hierarchy \"z80_top_direct_n:z80_\|data_pins:data_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "data_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 51 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232793 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_pins_n z80_top_direct_n:z80_\|control_pins_n:control_pins_ " "Elaborating entity \"control_pins_n\" for hierarchy \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "control_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648900232794 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1648900237557 ""} +{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\]\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\] ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|address_reg_a\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\]\" to the node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|address_reg_a\[1\]\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\] RamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\]\" to the node \"RamWE\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR RamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR\" to the node \"RamWE\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 77 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD Equal1 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD\" to the node \"Equal1\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ Equal1 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ\" to the node \"Equal1\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237657 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1648900237657 ""} +{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[7\] z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[0\] z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[6\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[0\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"D\[0\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[1\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1 " "Converted the fan-out from the tri-state buffer \"D\[1\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[2\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2 " "Converted the fan-out from the tri-state buffer \"D\[2\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[3\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3 " "Converted the fan-out from the tri-state buffer \"D\[3\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[4\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4 " "Converted the fan-out from the tri-state buffer \"D\[4\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[5\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5 " "Converted the fan-out from the tri-state buffer \"D\[5\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[6\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6 " "Converted the fan-out from the tri-state buffer \"D\[6\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[7\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7 " "Converted the fan-out from the tri-state buffer \"D\[7\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648900237663 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1648900237663 ""} +{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 127 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 201 -1 0 } } { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 93 -1 0 } } { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 97 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 108 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 109 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 33 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 59 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1648900237687 ""} +{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1648900237688 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[1\] GND " "Pin \"LED\[1\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648900241055 "|spectrum|LED[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[4\] GND " "Pin \"LED\[4\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648900241055 "|spectrum|LED[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[5\] GND " "Pin \"LED\[5\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648900241055 "|spectrum|LED[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[6\] GND " "Pin \"LED\[6\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648900241055 "|spectrum|LED[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[7\] GND " "Pin \"LED\[7\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648900241055 "|spectrum|LED[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[24\] VCC " "Pin \"GPIO_1\[24\]\" is stuck at VCC" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648900241055 "|spectrum|GPIO_1[24]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[32\] GND " "Pin \"GPIO_1\[32\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648900241055 "|spectrum|GPIO_1[32]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[33\] GND " "Pin \"GPIO_1\[33\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648900241055 "|spectrum|GPIO_1[33]"} { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CKE VCC " "Pin \"DRAM_CKE\" is stuck at VCC" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 27 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648900241055 "|spectrum|DRAM_CKE"} { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CS_N GND " "Pin \"DRAM_CS_N\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 30 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648900241055 "|spectrum|DRAM_CS_N"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1648900241055 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648900241438 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1648900245124 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1648900245212 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "2 0 2 0 0 " "Adding 2 node(s), including 0 DDIO, 2 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648900245470 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900245470 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[0\] " "No output dependent on input pin \"SW\[0\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900245726 "|spectrum|SW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "No output dependent on input pin \"SW\[3\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900245726 "|spectrum|SW[3]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1648900245726 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "3006 " "Implemented 3006 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648900245726 ""} { "Info" "ICUT_CUT_TM_OPINS" "85 " "Implemented 85 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648900245726 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "18 " "Implemented 18 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1648900245726 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2826 " "Implemented 2826 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648900245726 ""} { "Info" "ICUT_CUT_TM_RAMS" "64 " "Implemented 64 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648900245726 ""} { "Info" "ICUT_CUT_TM_PLLS" "2 " "Implemented 2 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Quartus II" 0 -1 1648900245726 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648900245726 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 112 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 112 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "446 " "Peak virtual memory: 446 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648900245751 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:50:45 2022 " "Processing ended: Sat Apr 2 14:50:45 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648900245751 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Elapsed time: 00:00:14" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648900245751 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:15 " "Total CPU time (on all processors): 00:00:15" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648900245751 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648900245751 ""} diff --git a/db/spectrum.map.rdb b/db/spectrum.map.rdb index 354cdc8..52f00df 100644 Binary files a/db/spectrum.map.rdb and b/db/spectrum.map.rdb differ diff --git a/db/spectrum.map_bb.cdb b/db/spectrum.map_bb.cdb index ae2f98f..41cb0c6 100644 Binary files a/db/spectrum.map_bb.cdb and b/db/spectrum.map_bb.cdb differ diff --git a/db/spectrum.map_bb.hdb b/db/spectrum.map_bb.hdb index 49a27df..dfad412 100644 Binary files a/db/spectrum.map_bb.hdb and b/db/spectrum.map_bb.hdb differ diff --git a/db/spectrum.pplq.rdb b/db/spectrum.pplq.rdb index 9e9f17c..9ea6ac9 100644 Binary files a/db/spectrum.pplq.rdb and b/db/spectrum.pplq.rdb differ diff --git a/db/spectrum.pre_map.hdb b/db/spectrum.pre_map.hdb index ff19523..8ef606a 100644 Binary files a/db/spectrum.pre_map.hdb and b/db/spectrum.pre_map.hdb differ diff --git a/db/spectrum.quiproj.1163158.rdr.flock b/db/spectrum.quiproj.9074.rdr.flock similarity index 100% rename from db/spectrum.quiproj.1163158.rdr.flock rename to db/spectrum.quiproj.9074.rdr.flock diff --git a/db/spectrum.root_partition.map.reg_db.cdb b/db/spectrum.root_partition.map.reg_db.cdb index 923edc0..97d5738 100644 Binary files a/db/spectrum.root_partition.map.reg_db.cdb and b/db/spectrum.root_partition.map.reg_db.cdb differ diff --git a/db/spectrum.routing.rdb b/db/spectrum.routing.rdb index c862e9f..6c009f6 100644 Binary files a/db/spectrum.routing.rdb and b/db/spectrum.routing.rdb differ diff --git a/db/spectrum.rtlv.hdb b/db/spectrum.rtlv.hdb index 2740a45..1d7f141 100644 Binary files a/db/spectrum.rtlv.hdb and b/db/spectrum.rtlv.hdb differ diff --git a/db/spectrum.rtlv_sg.cdb b/db/spectrum.rtlv_sg.cdb index ec5faa5..428ce67 100644 Binary files a/db/spectrum.rtlv_sg.cdb and b/db/spectrum.rtlv_sg.cdb differ diff --git a/db/spectrum.rtlv_sg_swap.cdb b/db/spectrum.rtlv_sg_swap.cdb index b2ef264..ef445e7 100644 Binary files a/db/spectrum.rtlv_sg_swap.cdb and b/db/spectrum.rtlv_sg_swap.cdb differ diff --git a/db/spectrum.sgdiff.cdb b/db/spectrum.sgdiff.cdb index 6061989..b843ee9 100644 Binary files a/db/spectrum.sgdiff.cdb and b/db/spectrum.sgdiff.cdb differ diff --git a/db/spectrum.sgdiff.hdb b/db/spectrum.sgdiff.hdb index 5eedc1c..f5da734 100644 Binary files a/db/spectrum.sgdiff.hdb and b/db/spectrum.sgdiff.hdb differ diff --git a/db/spectrum.sta.qmsg b/db/spectrum.sta.qmsg index cd2bc04..267d834 100644 --- a/db/spectrum.sta.qmsg +++ b/db/spectrum.sta.qmsg @@ -1,58 +1,58 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828544821 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828544822 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 1 18:55:44 2022 " "Processing started: Fri Apr 1 18:55:44 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828544822 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648828544822 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648828544822 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648828544853 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648828545066 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648828545068 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648828545118 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648828545118 ""} -{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1648828545540 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648828545549 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545549 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1648828545549 ""} -{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545550 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545550 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545550 ""} } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545550 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648828545550 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545551 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1648828545551 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Quartus II" 0 -1 1648828545551 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648828545552 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648828545552 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648828545552 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648828545552 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648828545552 ""} -{ "Warning" "WSTA_SCC_LOOP" "511 " "Found combinational loop of 511 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datab " "Node \"z80_\|alu_control_\|db\[0\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|combout " "Node \"z80_\|alu_control_\|db\[0\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|datac " "Node \"z80_\|alu_control_\|db\[0\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|combout " "Node \"z80_\|alu_control_\|db\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|datab " "Node \"z80_\|bus_control_\|db\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|combout " "Node \"z80_\|bus_control_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|datac " "Node \"z80_\|alu_control_\|db\[0\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|combout " "Node \"z80_\|alu_control_\|db\[0\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~19\|datac " "Node \"z80_\|alu_\|db\[0\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~19\|combout " "Node \"z80_\|alu_\|db\[0\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|combout " "Node \"z80_\|alu_\|db_low\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|combout " "Node \"z80_\|alu_\|db_low\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datac " "Node \"z80_\|alu_\|db_low\[1\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|combout " "Node \"z80_\|alu_\|db_low\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~13\|datac " "Node \"z80_\|alu_\|db\[1\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~13\|combout " "Node \"z80_\|alu_\|db\[1\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|datac " "Node \"z80_\|alu_\|db_low\[1\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datac " "Node \"z80_\|alu_\|db_low\[0\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|combout " "Node \"z80_\|alu_\|db_low\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datab " "Node \"z80_\|alu_\|db_low\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|combout " "Node \"z80_\|alu_\|db_low\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|combout " "Node \"z80_\|alu_\|db_low\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datab " "Node \"z80_\|alu_\|db\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|combout " "Node \"z80_\|alu_\|db\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~19\|dataa " "Node \"z80_\|alu_\|db\[0\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~12\|datac " "Node \"z80_\|alu_\|db\[1\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~12\|combout " "Node \"z80_\|alu_\|db\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~13\|dataa " "Node \"z80_\|alu_\|db\[1\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~2\|datac " "Node \"z80_\|alu_\|db_low\[2\]~2\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~2\|combout " "Node \"z80_\|alu_\|db_low\[2\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~3\|datac " "Node \"z80_\|alu_\|db_low\[2\]~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~3\|combout " "Node \"z80_\|alu_\|db_low\[2\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~24\|datab " "Node \"z80_\|alu_\|db_low\[2\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~24\|combout " "Node \"z80_\|alu_\|db_low\[2\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|dataa " "Node \"z80_\|alu_\|db\[2\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|combout " "Node \"z80_\|alu_\|db\[2\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|datad " "Node \"z80_\|alu_\|db_low\[1\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~35\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~37\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~37\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~38\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~38\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~8\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~9\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~9\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~14\|datad " "Node \"z80_\|alu_\|db\[2\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~14\|combout " "Node \"z80_\|alu_\|db\[2\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|datac " "Node \"z80_\|alu_\|db\[2\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|datab " "Node \"z80_\|alu_control_\|db\[2\]~27\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|combout " "Node \"z80_\|alu_control_\|db\[2\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datad " "Node \"z80_\|alu_control_\|db\[2\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|combout " "Node \"z80_\|alu_control_\|db\[2\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|datab " "Node \"z80_\|bus_control_\|db\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|combout " "Node \"z80_\|bus_control_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|datad " "Node \"z80_\|bus_control_\|db\[2\]~13\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|combout " "Node \"z80_\|bus_control_\|db\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~28\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|combout " "Node \"z80_\|alu_control_\|db\[2\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datac " "Node \"z80_\|alu_control_\|db\[2\]~29\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~14\|datac " "Node \"z80_\|alu_\|db\[2\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|datad " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|datad " "Node \"z80_\|alu_control_\|db\[2\]~28\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~3\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|datad " "Node \"z80_\|alu_\|db_low\[3\]~7\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|combout " "Node \"z80_\|alu_\|db_low\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|datac " "Node \"z80_\|alu_\|db_low\[3\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|combout " "Node \"z80_\|alu_\|db_low\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~11\|datad " "Node \"z80_\|alu_\|db_low\[3\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~11\|combout " "Node \"z80_\|alu_\|db_low\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~25\|datac " "Node \"z80_\|alu_\|db_low\[3\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~25\|combout " "Node \"z80_\|alu_\|db_low\[3\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~10\|datad " "Node \"z80_\|alu_\|db\[3\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~10\|combout " "Node \"z80_\|alu_\|db\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~11\|dataa " "Node \"z80_\|alu_\|db\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~11\|combout " "Node \"z80_\|alu_\|db\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~34\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|combout " "Node \"z80_\|alu_control_\|db\[3\]~34\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datad " "Node \"z80_\|alu_control_\|db\[3\]~35\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~11\|datac " "Node \"z80_\|alu_\|db\[3\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|datad " "Node \"z80_\|bus_control_\|db\[3\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|combout " "Node \"z80_\|bus_control_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datad " "Node \"z80_\|alu_\|db_low\[1\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|combout " "Node \"z80_\|alu_\|db_low\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|combout " "Node \"z80_\|alu_\|db_low\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datad " "Node \"z80_\|alu_\|db_low\[1\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~10\|datad " "Node \"z80_\|alu_\|db_low\[3\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~10\|combout " "Node \"z80_\|alu_\|db_low\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~11\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datad " "Node \"z80_\|alu_\|db_high\[0\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|combout " "Node \"z80_\|alu_\|db_high\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|datab " "Node \"z80_\|alu_\|db_high\[0\]~25\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|combout " "Node \"z80_\|alu_\|db_high\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~26\|datac " "Node \"z80_\|alu_\|db_high\[0\]~26\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~26\|combout " "Node \"z80_\|alu_\|db_high\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|datac " "Node \"z80_\|alu_\|db\[4\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|combout " "Node \"z80_\|alu_\|db\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|datad " "Node \"z80_\|alu_\|db\[4\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|combout " "Node \"z80_\|alu_\|db\[4\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|dataa " "Node \"z80_\|alu_\|db\[4\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~16\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|datac " "Node \"z80_\|alu_\|db_high\[0\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|combout " "Node \"z80_\|alu_\|db_high\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|datad " "Node \"z80_\|alu_\|db_high\[1\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|combout " "Node \"z80_\|alu_\|db_high\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|datab " "Node \"z80_\|alu_\|db_high\[1\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|combout " "Node \"z80_\|alu_\|db_high\[1\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|datad " "Node \"z80_\|alu_\|db_high\[1\]~19\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|combout " "Node \"z80_\|alu_\|db_high\[1\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~20\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~20\|combout " "Node \"z80_\|alu_\|db_high\[1\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~25\|dataa " "Node \"z80_\|alu_\|db\[5\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~25\|combout " "Node \"z80_\|alu_\|db\[5\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|datab " "Node \"z80_\|alu_control_\|db\[5\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|combout " "Node \"z80_\|alu_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|datac " "Node \"z80_\|bus_control_\|db\[5\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|combout " "Node \"z80_\|bus_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datac " "Node \"z80_\|alu_\|db_low\[1\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~10\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|datab " "Node \"z80_\|sw1_\|db_down\[5\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|combout " "Node \"z80_\|sw1_\|db_down\[5\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|combout " "Node \"z80_\|alu_control_\|db\[5\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|datad " "Node \"z80_\|alu_control_\|db\[5\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datac " "Node \"z80_\|alu_\|db_high\[0\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datac " "Node \"z80_\|alu_\|db_low\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|combout " "Node \"z80_\|alu_\|db_low\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|combout " "Node \"z80_\|alu_\|db_low\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datad " "Node \"z80_\|alu_\|db_low\[0\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datac " "Node \"z80_\|alu_\|db_high\[2\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|combout " "Node \"z80_\|alu_\|db_high\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|combout " "Node \"z80_\|alu_\|db_high\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~14\|datad " "Node \"z80_\|alu_\|db_high\[2\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~14\|combout " "Node \"z80_\|alu_\|db_high\[2\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|dataa " "Node \"z80_\|alu_\|db\[6\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|combout " "Node \"z80_\|alu_\|db\[6\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datac " "Node \"z80_\|alu_\|db_high\[3\]~5\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|combout " "Node \"z80_\|alu_\|db_high\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datab " "Node \"z80_\|alu_\|db_high\[3\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|combout " "Node \"z80_\|alu_\|db_high\[3\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|combout " "Node \"z80_\|alu_\|db_high\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~8\|datac " "Node \"z80_\|alu_\|db_high\[3\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~8\|combout " "Node \"z80_\|alu_\|db_high\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~21\|datac " "Node \"z80_\|alu_\|db\[7\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~21\|combout " "Node \"z80_\|alu_\|db\[7\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datac " "Node \"z80_\|alu_\|db_high\[3\]~6\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~73\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~73\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~74\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~74\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~19\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~20\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~21\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|datac " "Node \"z80_\|alu_\|db\[7\]~20\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|combout " "Node \"z80_\|alu_\|db\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~21\|dataa " "Node \"z80_\|alu_\|db\[7\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datab " "Node \"z80_\|alu_\|db_high\[3\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datad " "Node \"z80_\|alu_\|db_low\[0\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|datad " "Node \"z80_\|alu_\|db_high\[2\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|combout " "Node \"z80_\|alu_\|db_high\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|datab " "Node \"z80_\|alu_\|db_high\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|combout " "Node \"z80_\|alu_\|db_high\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|datac " "Node \"z80_\|alu_\|db_high\[2\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~16\|datac " "Node \"z80_\|alu_control_\|db\[7\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~16\|combout " "Node \"z80_\|alu_control_\|db\[7\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|datad " "Node \"z80_\|alu_control_\|db\[7\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|combout " "Node \"z80_\|alu_control_\|db\[7\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|datab " "Node \"z80_\|bus_control_\|db\[7\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|combout " "Node \"z80_\|bus_control_\|db\[7\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|datad " "Node \"z80_\|bus_control_\|db\[7\]~7\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|combout " "Node \"z80_\|bus_control_\|db\[7\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|datad " "Node \"z80_\|alu_control_\|db\[7\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|combout " "Node \"z80_\|alu_control_\|db\[7\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|datad " "Node \"z80_\|alu_\|db\[7\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~0\|datac " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~0\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~20\|datab " "Node \"z80_\|alu_control_\|db\[6\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~20\|combout " "Node \"z80_\|alu_control_\|db\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~21\|datac " "Node \"z80_\|alu_control_\|db\[6\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~21\|combout " "Node \"z80_\|alu_control_\|db\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|datab " "Node \"z80_\|alu_control_\|db\[6\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|combout " "Node \"z80_\|alu_control_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|datab " "Node \"z80_\|bus_control_\|db\[6\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|combout " "Node \"z80_\|bus_control_\|db\[6\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|dataa " "Node \"z80_\|bus_control_\|db\[6\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|combout " "Node \"z80_\|bus_control_\|db\[6\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~21\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|datac " "Node \"z80_\|alu_control_\|db\[6\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datad " "Node \"z80_\|alu_\|db\[6\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|combout " "Node \"z80_\|alu_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|datac " "Node \"z80_\|alu_\|db\[6\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|datac " "Node \"z80_\|alu_\|db_high\[2\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~80\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~80\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~82\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~82\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~83\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~83\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datac " "Node \"z80_\|alu_\|db\[6\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~23\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|datac " "Node \"z80_\|alu_\|db_low\[2\]~4\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|combout " "Node \"z80_\|alu_\|db_low\[2\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|combout " "Node \"z80_\|alu_\|db_low\[2\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~24\|datac " "Node \"z80_\|alu_\|db_low\[2\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|datac " "Node \"z80_\|alu_\|db_high\[1\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|combout " "Node \"z80_\|alu_\|db_high\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|datac " "Node \"z80_\|alu_\|db_high\[3\]~27\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|combout " "Node \"z80_\|alu_\|db_high\[3\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|datac " "Node \"z80_\|alu_\|db_high\[3\]~7\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|datab " "Node \"z80_\|alu_\|db\[5\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|combout " "Node \"z80_\|alu_\|db\[5\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~25\|datac " "Node \"z80_\|alu_\|db\[5\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|datac " "Node \"z80_\|alu_control_\|db\[5\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datac " "Node \"z80_\|alu_\|db_high\[0\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|combout " "Node \"z80_\|alu_\|db_high\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|datac " "Node \"z80_\|alu_\|db_high\[2\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~13\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|datac " "Node \"z80_\|alu_\|db\[5\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|datac " "Node \"z80_\|alu_\|db_high\[1\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|combout " "Node \"z80_\|alu_control_\|db\[4\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datad " "Node \"z80_\|alu_control_\|db\[4\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datad " "Node \"z80_\|alu_control_\|db\[4\]~32\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|combout " "Node \"z80_\|alu_control_\|db\[4\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|datab " "Node \"z80_\|bus_control_\|db\[4\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|combout " "Node \"z80_\|bus_control_\|db\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datab " "Node \"z80_\|alu_\|db_low\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datab " "Node \"z80_\|alu_\|db_high\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datab " "Node \"z80_\|alu_\|db_low\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datab " "Node \"z80_\|alu_\|db_high\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|datab " "Node \"z80_\|alu_\|db_low\[2\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|datab " "Node \"z80_\|alu_\|db_high\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|datab " "Node \"z80_\|alu_\|db_high\[3\]~27\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|datac " "Node \"z80_\|alu_\|db\[4\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|datac " "Node \"z80_\|alu_control_\|db\[4\]~30\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datad " "Node \"z80_\|alu_\|db_low\[0\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datad " "Node \"z80_\|alu_\|db_high\[2\]~9\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|datad " "Node \"z80_\|alu_\|db_low\[2\]~4\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|datad " "Node \"z80_\|alu_\|db_high\[1\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|datad " "Node \"z80_\|alu_\|db_high\[3\]~27\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~1\|datad " "Node \"z80_\|sw1_\|db_down\[3\]~1\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~1\|combout " "Node \"z80_\|sw1_\|db_down\[3\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|datad " "Node \"z80_\|alu_control_\|db\[3\]~34\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datab " "Node \"z80_\|alu_\|db_high\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~44\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~44\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~46\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~46\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~47\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~47\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~11\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~12\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~10\|datac " "Node \"z80_\|alu_\|db\[3\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~2\|datab " "Node \"z80_\|alu_\|db_low\[2\]~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|datad " "Node \"z80_\|alu_control_\|db\[1\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|combout " "Node \"z80_\|alu_control_\|db\[1\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|datad " "Node \"z80_\|alu_control_\|db\[1\]~26\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|combout " "Node \"z80_\|alu_control_\|db\[1\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|datab " "Node \"z80_\|bus_control_\|db\[1\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|combout " "Node \"z80_\|bus_control_\|db\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|datac " "Node \"z80_\|bus_control_\|db\[1\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|combout " "Node \"z80_\|bus_control_\|db\[1\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|combout " "Node \"z80_\|alu_control_\|db\[1\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~12\|datab " "Node \"z80_\|alu_\|db\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|datac " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|datab " "Node \"z80_\|alu_control_\|db\[1\]~25\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datac " "Node \"z80_\|alu_\|db_low\[0\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datac " "Node \"z80_\|alu_\|db\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|datad " "Node \"z80_\|sw2_\|db_up\[0\]~0\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|combout " "Node \"z80_\|sw2_\|db_up\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datad " "Node \"z80_\|alu_control_\|db\[0\]~9\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 31 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 30 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1648828545559 ""} -{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "511 " "Design contains combinational loop of 511 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Quartus II" 0 -1 1648828545577 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648828545610 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648828545610 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545745 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648828545747 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648828545777 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648828545819 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648828545819 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -18.123 " "Worst-case setup slack is -18.123" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545820 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545820 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -18.123 -549.338 CLOCK_50 " " -18.123 -549.338 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545820 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -7.533 -284.813 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -7.533 -284.813 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545820 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.740 -42.810 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.740 -42.810 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545820 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.914 -2.914 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.914 -2.914 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545820 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828545820 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.210 " "Worst-case hold slack is 0.210" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545826 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545826 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.210 0.000 CLOCK_50 " " 0.210 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545826 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545826 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.344 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.344 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545826 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545826 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828545826 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -6.223 " "Worst-case recovery slack is -6.223" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545827 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545827 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.223 -459.348 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -6.223 -459.348 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545827 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828545827 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.698 " "Worst-case removal slack is 3.698" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545828 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545828 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.698 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.698 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545828 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828545828 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.488 " "Worst-case minimum pulse width slack is 9.488" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545829 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545829 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.488 0.000 CLOCK_50 " " 9.488 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545829 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.602 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.602 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545829 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.595 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.595 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545829 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545829 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828545829 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648828545969 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648828546007 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648828546952 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648828547129 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648828547129 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547131 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648828547148 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648828547148 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -17.311 " "Worst-case setup slack is -17.311" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547151 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547151 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -17.311 -526.609 CLOCK_50 " " -17.311 -526.609 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547151 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.686 -253.661 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -6.686 -253.661 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547151 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.428 -40.009 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.428 -40.009 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547151 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.785 -2.785 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.785 -2.785 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547151 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547151 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.298 " "Worst-case hold slack is 0.298" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547159 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547159 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547159 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.300 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.300 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547159 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.304 0.000 CLOCK_50 " " 0.304 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547159 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547159 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547159 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -5.744 " "Worst-case recovery slack is -5.744" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547162 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547162 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.744 -423.582 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -5.744 -423.582 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547162 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547162 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.374 " "Worst-case removal slack is 3.374" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547165 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547165 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.374 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.374 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547165 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547165 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.489 " "Worst-case minimum pulse width slack is 9.489" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.489 0.000 CLOCK_50 " " 9.489 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.591 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.591 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.491 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.491 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547168 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547168 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648828547327 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648828547608 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648828547608 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547610 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648828547617 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648828547617 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -14.971 " "Worst-case setup slack is -14.971" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547622 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547622 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -14.971 -442.545 CLOCK_50 " " -14.971 -442.545 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547622 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.979 -171.124 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -4.979 -171.124 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547622 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.775 -35.541 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -3.775 -35.541 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547622 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.784 -2.784 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.784 -2.784 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547622 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547622 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.053 " "Worst-case hold slack is -0.053" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547632 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547632 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.053 -0.089 CLOCK_50 " " -0.053 -0.089 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547632 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547632 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.178 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.178 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547632 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547632 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547632 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.693 " "Worst-case recovery slack is -4.693" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.693 -358.284 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.693 -358.284 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547637 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547637 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.518 " "Worst-case removal slack is 2.518" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547642 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547642 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.518 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 2.518 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547642 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547642 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.208 " "Worst-case minimum pulse width slack is 9.208" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547647 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547647 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.208 0.000 CLOCK_50 " " 9.208 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547647 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.609 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.609 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547647 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547647 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.535 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.535 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547647 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547647 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648828548217 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648828548217 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 532 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 532 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "437 " "Peak virtual memory: 437 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828548454 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 1 18:55:48 2022 " "Processing ended: Fri Apr 1 18:55:48 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828548454 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828548454 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828548454 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648828548454 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648900273361 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648900273361 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:51:13 2022 " "Processing started: Sat Apr 2 14:51:13 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648900273361 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648900273361 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648900273362 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648900273389 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648900273585 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648900273586 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648900273629 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648900273629 ""} +{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1648900274051 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648900274060 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274060 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1648900274060 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274062 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274062 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274062 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274062 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274062 ""} } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274062 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648900274062 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274062 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1648900274062 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Quartus II" 0 -1 1648900274062 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648900274063 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648900274064 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648900274064 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648900274064 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648900274064 ""} +{ "Warning" "WSTA_SCC_LOOP" "513 " "Found combinational loop of 513 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|combout " "Node \"z80_\|bus_control_\|db\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datad " "Node \"z80_\|alu_control_\|db\[2\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|combout " "Node \"z80_\|alu_control_\|db\[2\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~30\|datad " "Node \"z80_\|alu_control_\|db\[2\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~30\|combout " "Node \"z80_\|alu_control_\|db\[2\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~38\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~38\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~1\|datab " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datab " "Node \"z80_\|alu_control_\|db\[2\]~29\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|datac " "Node \"z80_\|bus_control_\|db\[2\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|combout " "Node \"z80_\|bus_control_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|datac " "Node \"z80_\|bus_control_\|db\[2\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|datad " "Node \"z80_\|alu_\|db\[2\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|combout " "Node \"z80_\|alu_\|db\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|datac " "Node \"z80_\|alu_\|db\[2\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|combout " "Node \"z80_\|alu_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~18\|datad " "Node \"z80_\|alu_\|db_low\[1\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~18\|combout " "Node \"z80_\|alu_\|db_low\[1\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~19\|datac " "Node \"z80_\|alu_\|db_low\[1\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~19\|combout " "Node \"z80_\|alu_\|db_low\[1\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~20\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~20\|combout " "Node \"z80_\|alu_\|db_low\[1\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|datac " "Node \"z80_\|alu_\|db\[1\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|combout " "Node \"z80_\|alu_\|db\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|combout " "Node \"z80_\|alu_control_\|db\[1\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|combout " "Node \"z80_\|alu_control_\|db\[1\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~27\|datab " "Node \"z80_\|alu_control_\|db\[1\]~27\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~27\|combout " "Node \"z80_\|alu_control_\|db\[1\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|dataa " "Node \"z80_\|bus_control_\|db\[1\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|combout " "Node \"z80_\|bus_control_\|db\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|dataa " "Node \"z80_\|bus_control_\|db\[1\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|combout " "Node \"z80_\|bus_control_\|db\[1\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[1\]~2\|dataa " "Node \"z80_\|sw1_\|db_down\[1\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[1\]~2\|combout " "Node \"z80_\|sw1_\|db_down\[1\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~27\|datad " "Node \"z80_\|alu_control_\|db\[1\]~27\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|dataa " "Node \"z80_\|alu_\|db\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|combout " "Node \"z80_\|alu_\|db\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~16\|datad " "Node \"z80_\|alu_\|db\[1\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|datac " "Node \"z80_\|alu_control_\|db\[1\]~26\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~19\|datab " "Node \"z80_\|alu_\|db_low\[1\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datac " "Node \"z80_\|alu_\|db_low\[0\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|combout " "Node \"z80_\|alu_\|db_low\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datad " "Node \"z80_\|alu_\|db_low\[0\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|combout " "Node \"z80_\|alu_\|db_low\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~27\|datab " "Node \"z80_\|alu_\|db_low\[0\]~27\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~27\|combout " "Node \"z80_\|alu_\|db_low\[0\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|datac " "Node \"z80_\|alu_\|db\[0\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|combout " "Node \"z80_\|alu_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datab " "Node \"z80_\|alu_\|db\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|combout " "Node \"z80_\|alu_\|db\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datac " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datad " "Node \"z80_\|alu_\|db_low\[0\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|datad " "Node \"z80_\|alu_\|db_high\[3\]~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|combout " "Node \"z80_\|alu_\|db_high\[3\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|datac " "Node \"z80_\|alu_\|db_high\[3\]~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|combout " "Node \"z80_\|alu_\|db_high\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datab " "Node \"z80_\|alu_\|db_high\[3\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|combout " "Node \"z80_\|alu_\|db_high\[3\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|datad " "Node \"z80_\|alu_\|db_high\[3\]~7\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|combout " "Node \"z80_\|alu_\|db_high\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|datad " "Node \"z80_\|alu_\|db\[7\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|combout " "Node \"z80_\|alu_\|db\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~3\|datab " "Node \"z80_\|alu_\|db_high\[3\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~8\|datab " "Node \"z80_\|alu_\|db_high\[2\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~8\|combout " "Node \"z80_\|alu_\|db_high\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datad " "Node \"z80_\|alu_\|db_high\[2\]~9\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|combout " "Node \"z80_\|alu_\|db_high\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|datac " "Node \"z80_\|alu_\|db_high\[2\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|combout " "Node \"z80_\|alu_\|db_high\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|combout " "Node \"z80_\|alu_\|db_high\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datac " "Node \"z80_\|alu_\|db\[6\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|combout " "Node \"z80_\|alu_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|datac " "Node \"z80_\|alu_\|db_high\[3\]~2\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~16\|datac " "Node \"z80_\|alu_\|db_high\[1\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~16\|combout " "Node \"z80_\|alu_\|db_high\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|datad " "Node \"z80_\|alu_\|db_high\[1\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|combout " "Node \"z80_\|alu_\|db_high\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|combout " "Node \"z80_\|alu_\|db_high\[1\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|datac " "Node \"z80_\|alu_\|db_high\[1\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|combout " "Node \"z80_\|alu_\|db_high\[1\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|dataa " "Node \"z80_\|alu_\|db\[5\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|combout " "Node \"z80_\|alu_\|db\[5\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|datab " "Node \"z80_\|alu_\|db_high\[1\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~8\|datad " "Node \"z80_\|alu_\|db_high\[2\]~8\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~80\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~80\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~82\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~82\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~83\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~83\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|dataa " "Node \"z80_\|alu_\|db\[5\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|combout " "Node \"z80_\|alu_\|db\[5\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|datac " "Node \"z80_\|alu_\|db\[5\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~22\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~23\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~24\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~84\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~84\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~17\|datad " "Node \"z80_\|alu_control_\|db\[5\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~17\|combout " "Node \"z80_\|alu_control_\|db\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|dataa " "Node \"z80_\|bus_control_\|db\[5\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|combout " "Node \"z80_\|bus_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|datad " "Node \"z80_\|alu_\|db_high\[1\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|combout " "Node \"z80_\|alu_\|db_high\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|datac " "Node \"z80_\|alu_\|db_high\[1\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|datad " "Node \"z80_\|alu_\|db_low\[1\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|combout " "Node \"z80_\|alu_\|db_low\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datab " "Node \"z80_\|alu_\|db_low\[1\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|combout " "Node \"z80_\|alu_\|db_low\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~20\|datad " "Node \"z80_\|alu_\|db_low\[1\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|datac " "Node \"z80_\|sw1_\|db_down\[5\]~0\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|combout " "Node \"z80_\|sw1_\|db_down\[5\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~16\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~16\|combout " "Node \"z80_\|alu_control_\|db\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~17\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|datab " "Node \"z80_\|alu_\|db_high\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|combout " "Node \"z80_\|alu_\|db_high\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|datad " "Node \"z80_\|alu_\|db_high\[2\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|datab " "Node \"z80_\|alu_\|db_low\[3\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|combout " "Node \"z80_\|alu_\|db_low\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|datad " "Node \"z80_\|alu_\|db_low\[3\]~8\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|combout " "Node \"z80_\|alu_\|db_low\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~26\|datad " "Node \"z80_\|alu_\|db_low\[3\]~26\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~26\|combout " "Node \"z80_\|alu_\|db_low\[3\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|dataa " "Node \"z80_\|alu_\|db\[3\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|combout " "Node \"z80_\|alu_\|db\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|datab " "Node \"z80_\|alu_\|db\[3\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|combout " "Node \"z80_\|alu_\|db\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~36\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~36\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~36\|combout " "Node \"z80_\|alu_control_\|db\[3\]~36\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~45\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~45\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~45\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~45\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~49\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~49\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~49\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~49\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datad " "Node \"z80_\|alu_control_\|db\[3\]~35\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~36\|datad " "Node \"z80_\|alu_control_\|db\[3\]~36\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~14\|datad " "Node \"z80_\|alu_\|db\[3\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|datac " "Node \"z80_\|bus_control_\|db\[3\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|combout " "Node \"z80_\|bus_control_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~3\|datab " "Node \"z80_\|sw1_\|db_down\[3\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~3\|combout " "Node \"z80_\|sw1_\|db_down\[3\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datac " "Node \"z80_\|alu_control_\|db\[3\]~35\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|datab " "Node \"z80_\|alu_\|db_high\[1\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~13\|datad " "Node \"z80_\|alu_\|db_low\[2\]~13\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~13\|combout " "Node \"z80_\|alu_\|db_low\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~14\|datad " "Node \"z80_\|alu_\|db_low\[2\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~14\|combout " "Node \"z80_\|alu_\|db_low\[2\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~12\|dataa " "Node \"z80_\|alu_\|db\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datab " "Node \"z80_\|alu_\|db_high\[0\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|combout " "Node \"z80_\|alu_\|db_high\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|datad " "Node \"z80_\|alu_\|db_high\[0\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|combout " "Node \"z80_\|alu_\|db_high\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|datac " "Node \"z80_\|alu_\|db_high\[0\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|combout " "Node \"z80_\|alu_\|db_high\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|datad " "Node \"z80_\|alu_\|db\[4\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|combout " "Node \"z80_\|alu_\|db\[4\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datad " "Node \"z80_\|alu_control_\|db\[4\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datac " "Node \"z80_\|alu_control_\|db\[4\]~32\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|combout " "Node \"z80_\|alu_control_\|db\[4\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~33\|datad " "Node \"z80_\|alu_control_\|db\[4\]~33\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~33\|combout " "Node \"z80_\|alu_control_\|db\[4\]~33\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~53\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~53\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~60\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~60\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~60\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~60\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datac " "Node \"z80_\|alu_control_\|db\[4\]~31\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|datac " "Node \"z80_\|alu_\|db\[4\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|combout " "Node \"z80_\|alu_\|db\[4\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~10\|datac " "Node \"z80_\|alu_\|db\[4\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|datac " "Node \"z80_\|bus_control_\|db\[4\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|combout " "Node \"z80_\|bus_control_\|db\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~33\|datac " "Node \"z80_\|alu_control_\|db\[4\]~33\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|datab " "Node \"z80_\|alu_\|db_low\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|datad " "Node \"z80_\|alu_\|db_high\[2\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datab " "Node \"z80_\|alu_\|db_low\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|combout " "Node \"z80_\|alu_\|db_low\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~25\|datad " "Node \"z80_\|alu_\|db_low\[0\]~25\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~25\|combout " "Node \"z80_\|alu_\|db_low\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~27\|datac " "Node \"z80_\|alu_\|db_low\[0\]~27\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|datad " "Node \"z80_\|alu_\|db_low\[3\]~7\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datad " "Node \"z80_\|alu_\|db_high\[3\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|combout " "Node \"z80_\|alu_\|db_high\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datad " "Node \"z80_\|alu_\|db_high\[3\]~6\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~16\|datad " "Node \"z80_\|alu_\|db_high\[1\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|combout " "Node \"z80_\|alu_\|db_high\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|datac " "Node \"z80_\|alu_\|db_high\[0\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~53\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~53\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~55\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~55\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~56\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~56\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~14\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~15\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~8\|datad " "Node \"z80_\|alu_\|db\[4\]~8\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|datad " "Node \"z80_\|alu_\|db_low\[3\]~4\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|combout " "Node \"z80_\|alu_\|db_low\[3\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|datad " "Node \"z80_\|alu_\|db_low\[3\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|combout " "Node \"z80_\|alu_\|db_low\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|datac " "Node \"z80_\|alu_\|db_high\[0\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|combout " "Node \"z80_\|alu_\|db_high\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datad " "Node \"z80_\|alu_\|db_high\[0\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~5\|datab " "Node \"z80_\|alu_\|db_low\[3\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~7\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~7\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~39\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~13\|datac " "Node \"z80_\|alu_\|db\[3\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|datad " "Node \"z80_\|alu_\|db_low\[2\]~9\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|combout " "Node \"z80_\|alu_\|db_low\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|datad " "Node \"z80_\|alu_\|db_low\[2\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|combout " "Node \"z80_\|alu_\|db_low\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~13\|datab " "Node \"z80_\|alu_\|db_low\[2\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datad " "Node \"z80_\|alu_\|db_high\[0\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datad " "Node \"z80_\|alu_\|db_low\[0\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datab " "Node \"z80_\|alu_\|db_high\[3\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~65\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~65\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~69\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~69\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~69\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~69\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~16\|datac " "Node \"z80_\|alu_control_\|db\[5\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|datac " "Node \"z80_\|alu_\|db\[5\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|datad " "Node \"z80_\|alu_\|db_high\[0\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datac " "Node \"z80_\|alu_\|db_high\[2\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~20\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~20\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~21\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~75\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|datac " "Node \"z80_\|alu_\|db\[6\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|combout " "Node \"z80_\|alu_\|db\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datad " "Node \"z80_\|alu_\|db\[6\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|datac " "Node \"z80_\|alu_control_\|db\[6\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|combout " "Node \"z80_\|alu_control_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~23\|datab " "Node \"z80_\|alu_control_\|db\[6\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~23\|combout " "Node \"z80_\|alu_control_\|db\[6\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|datad " "Node \"z80_\|bus_control_\|db\[6\]~8\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|combout " "Node \"z80_\|bus_control_\|db\[6\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|dataa " "Node \"z80_\|bus_control_\|db\[6\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|combout " "Node \"z80_\|bus_control_\|db\[6\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[6\]~1\|datac " "Node \"z80_\|sw1_\|db_down\[6\]~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[6\]~1\|combout " "Node \"z80_\|sw1_\|db_down\[6\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~23\|datad " "Node \"z80_\|alu_control_\|db\[6\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|dataa " "Node \"z80_\|alu_\|db\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~77\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~77\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~77\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~77\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~78\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~78\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~78\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~78\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~0\|datab " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~23\|datac " "Node \"z80_\|alu_control_\|db\[6\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~64\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~64\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~65\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~65\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~16\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~17\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~18\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~66\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~66\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|dataa " "Node \"z80_\|alu_\|db\[7\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|combout " "Node \"z80_\|alu_\|db\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|datac " "Node \"z80_\|alu_\|db\[7\]~20\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|combout " "Node \"z80_\|alu_control_\|db\[7\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~19\|datad " "Node \"z80_\|alu_control_\|db\[7\]~19\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~19\|combout " "Node \"z80_\|alu_control_\|db\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~20\|datad " "Node \"z80_\|alu_control_\|db\[7\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~20\|combout " "Node \"z80_\|alu_control_\|db\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~37\|datad " "Node \"z80_\|alu_control_\|db\[7\]~37\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~37\|combout " "Node \"z80_\|alu_control_\|db\[7\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|datab " "Node \"z80_\|bus_control_\|db\[7\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|combout " "Node \"z80_\|bus_control_\|db\[7\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|dataa " "Node \"z80_\|bus_control_\|db\[7\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|combout " "Node \"z80_\|bus_control_\|db\[7\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~20\|datab " "Node \"z80_\|alu_control_\|db\[7\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~19\|datac " "Node \"z80_\|alu_\|db\[7\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~87\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~87\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~87\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~87\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~88\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~88\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~88\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~88\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~19\|datac " "Node \"z80_\|alu_control_\|db\[7\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|dataa " "Node \"z80_\|sw2_\|db_up\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|combout " "Node \"z80_\|sw2_\|db_up\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~11\|datad " "Node \"z80_\|alu_control_\|db\[0\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~11\|combout " "Node \"z80_\|alu_control_\|db\[0\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~14\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~14\|combout " "Node \"z80_\|alu_control_\|db\[0\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|datab " "Node \"z80_\|bus_control_\|db\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|combout " "Node \"z80_\|bus_control_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~10\|datad " "Node \"z80_\|alu_control_\|db\[0\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~10\|combout " "Node \"z80_\|alu_control_\|db\[0\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~11\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|dataa " "Node \"z80_\|alu_\|db\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~11\|datab " "Node \"z80_\|alu_control_\|db\[0\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~18\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datab " "Node \"z80_\|alu_\|db_low\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|dataa " "Node \"z80_\|alu_\|db\[0\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~9\|datab " "Node \"z80_\|alu_\|db_low\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~15\|datac " "Node \"z80_\|alu_\|db\[1\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~10\|datac " "Node \"z80_\|alu_\|db_low\[2\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~28\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|combout " "Node \"z80_\|alu_control_\|db\[2\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~30\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~11\|datac " "Node \"z80_\|alu_\|db\[2\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~10\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~48\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~4\|datac " "Node \"z80_\|alu_\|db_low\[3\]~4\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648900274071 ""} } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 31 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 30 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1648900274071 ""} +{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "513 " "Design contains combinational loop of 513 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Quartus II" 0 -1 1648900274088 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648900274118 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648900274118 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274248 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648900274250 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648900274279 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648900274329 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648900274329 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -18.571 " "Worst-case setup slack is -18.571" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274330 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274330 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -18.571 -821.372 CLOCK_50 " " -18.571 -821.372 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274330 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -7.747 -287.138 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -7.747 -287.138 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274330 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.731 -41.432 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.731 -41.432 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274330 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.915 -2.915 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.915 -2.915 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274330 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.503 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 3.503 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274330 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900274330 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.342 " "Worst-case hold slack is 0.342" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274337 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274337 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274337 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274337 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274337 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.359 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.359 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274337 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.373 0.000 CLOCK_50 " " 0.373 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274337 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900274337 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -6.212 " "Worst-case recovery slack is -6.212" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274338 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274338 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.212 -460.730 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -6.212 -460.730 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274338 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900274338 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.666 " "Worst-case removal slack is 3.666" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274339 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274339 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.666 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.666 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274339 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900274339 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.752 " "Worst-case minimum pulse width slack is 4.752" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274340 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274340 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.752 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.752 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274340 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.488 0.000 CLOCK_50 " " 9.488 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274340 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.602 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.602 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274340 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.597 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.597 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274340 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900274340 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900274340 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648900274504 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648900274542 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648900275511 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648900275682 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648900275682 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275685 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648900275705 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648900275705 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -17.727 " "Worst-case setup slack is -17.727" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275708 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275708 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -17.727 -781.205 CLOCK_50 " " -17.727 -781.205 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275708 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.896 -255.894 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -6.896 -255.894 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275708 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.422 -38.759 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.422 -38.759 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275708 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.786 -2.786 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.786 -2.786 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275708 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.148 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.148 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275708 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900275708 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.298 " "Worst-case hold slack is 0.298" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275717 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275717 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275717 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275717 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275717 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.312 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.312 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275717 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.339 0.000 CLOCK_50 " " 0.339 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275717 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900275717 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -5.735 " "Worst-case recovery slack is -5.735" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.735 -424.927 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -5.735 -424.927 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275721 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900275721 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.339 " "Worst-case removal slack is 3.339" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275725 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275725 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.339 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.339 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275725 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900275725 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.748 " "Worst-case minimum pulse width slack is 4.748" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275728 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275728 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.748 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.748 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275728 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.489 0.000 CLOCK_50 " " 9.489 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275728 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.596 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.596 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275728 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.591 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.591 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275728 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.491 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.491 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900275728 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900275728 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648900275928 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648900276228 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648900276228 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276230 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648900276238 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648900276238 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -15.243 " "Worst-case setup slack is -15.243" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276245 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276245 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -15.243 -641.328 CLOCK_50 " " -15.243 -641.328 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276245 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.921 -171.346 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -4.921 -171.346 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276245 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.770 -34.841 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -3.770 -34.841 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276245 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.784 -2.784 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.784 -2.784 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276245 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.261 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 6.261 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276245 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900276245 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.098 " "Worst-case hold slack is 0.098" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276257 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276257 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.098 0.000 CLOCK_50 " " 0.098 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276257 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276257 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276257 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.186 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276257 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276257 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900276257 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.684 " "Worst-case recovery slack is -4.684" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276264 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276264 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.684 -358.844 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.684 -358.844 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276264 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900276264 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.507 " "Worst-case removal slack is 2.507" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.507 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 2.507 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276270 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900276270 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.783 " "Worst-case minimum pulse width slack is 4.783" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276276 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276276 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.783 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.783 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276276 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.208 0.000 CLOCK_50 " " 9.208 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276276 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.609 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.609 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276276 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276276 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.535 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.535 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648900276276 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648900276276 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648900276955 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648900276955 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 534 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 534 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "445 " "Peak virtual memory: 445 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648900277219 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:51:17 2022 " "Processing ended: Sat Apr 2 14:51:17 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648900277219 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648900277219 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648900277219 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648900277219 ""} diff --git a/db/spectrum.sta.rdb b/db/spectrum.sta.rdb index 1bbdc89..b97bc3f 100644 Binary files a/db/spectrum.sta.rdb and b/db/spectrum.sta.rdb differ diff --git a/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb b/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb index 2eb24bc..3281638 100644 Binary files a/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb and b/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb differ diff --git a/db/spectrum.tiscmp.fast_1200mv_0c.ddb b/db/spectrum.tiscmp.fast_1200mv_0c.ddb index 964cd81..e1687d8 100644 Binary files a/db/spectrum.tiscmp.fast_1200mv_0c.ddb and b/db/spectrum.tiscmp.fast_1200mv_0c.ddb differ diff --git a/db/spectrum.tiscmp.slow_1200mv_0c.ddb b/db/spectrum.tiscmp.slow_1200mv_0c.ddb index 4eb861d..897fa00 100644 Binary files a/db/spectrum.tiscmp.slow_1200mv_0c.ddb and b/db/spectrum.tiscmp.slow_1200mv_0c.ddb differ diff --git a/db/spectrum.tiscmp.slow_1200mv_85c.ddb b/db/spectrum.tiscmp.slow_1200mv_85c.ddb index 865cf09..f730213 100644 Binary files a/db/spectrum.tiscmp.slow_1200mv_85c.ddb and b/db/spectrum.tiscmp.slow_1200mv_85c.ddb differ diff --git a/db/spectrum.vpr.ammdb b/db/spectrum.vpr.ammdb index 1f2e0e9..f447e9d 100644 Binary files a/db/spectrum.vpr.ammdb and b/db/spectrum.vpr.ammdb differ diff --git a/greybox_tmp/cbx_args.txt b/greybox_tmp/cbx_args.txt index 2b81d66..483f345 100644 --- a/greybox_tmp/cbx_args.txt +++ b/greybox_tmp/cbx_args.txt @@ -1,16 +1,12 @@ BANDWIDTH_TYPE=AUTO -CLK0_DIVIDE_BY=143 +CLK0_DIVIDE_BY=1 CLK0_DUTY_CYCLE=50 -CLK0_MULTIPLY_BY=72 +CLK0_MULTIPLY_BY=2 CLK0_PHASE_SHIFT=0 -CLK1_DIVIDE_BY=25 +CLK1_DIVIDE_BY=1 CLK1_DUTY_CYCLE=50 -CLK1_MULTIPLY_BY=7 -CLK1_PHASE_SHIFT=0 -CLK2_DIVIDE_BY=25 -CLK2_DUTY_CYCLE=50 -CLK2_MULTIPLY_BY=12 -CLK2_PHASE_SHIFT=0 +CLK1_MULTIPLY_BY=2 +CLK1_PHASE_SHIFT=3000 COMPENSATE_CLOCK=CLK0 INCLK0_INPUT_FREQUENCY=20000 INTENDED_DEVICE_FAMILY="Cyclone IV E" @@ -27,7 +23,7 @@ PORT_CONFIGUPDATE=PORT_UNUSED PORT_FBIN=PORT_UNUSED PORT_INCLK0=PORT_USED PORT_INCLK1=PORT_UNUSED -PORT_LOCKED=PORT_USED +PORT_LOCKED=PORT_UNUSED PORT_PFDENA=PORT_UNUSED PORT_PHASECOUNTERSELECT=PORT_UNUSED PORT_PHASEDONE=PORT_UNUSED @@ -44,7 +40,7 @@ PORT_SCANREAD=PORT_UNUSED PORT_SCANWRITE=PORT_UNUSED PORT_clk0=PORT_USED PORT_clk1=PORT_USED -PORT_clk2=PORT_USED +PORT_clk2=PORT_UNUSED PORT_clk3=PORT_UNUSED PORT_clk4=PORT_UNUSED PORT_clk5=PORT_UNUSED @@ -58,7 +54,6 @@ PORT_extclk0=PORT_UNUSED PORT_extclk1=PORT_UNUSED PORT_extclk2=PORT_UNUSED PORT_extclk3=PORT_UNUSED -SELF_RESET_ON_LOSS_LOCK=OFF WIDTH_CLOCK=5 DEVICE_FAMILY="Cyclone IV E" CBX_AUTO_BLACKBOX=ALL @@ -66,5 +61,3 @@ inclk inclk clk clk -clk -locked diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb index d33caa1..2442bd6 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb index 11d8ad5..24f6d67 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb index 25ab810..d39007a 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb index da66c56..931c0df 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb index 428a347..e5f3fe1 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi b/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi index 33139a1..b83c11a 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi and b/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb index 67df2f3..3b0c0cc 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hb_info b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hb_info index 7e6bec8..4d6b0af 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hb_info and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hb_info differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb index 110b4e6..e39484c 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.sig b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.sig index 3c3090d..f570527 100644 --- a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.sig +++ b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.sig @@ -1 +1 @@ -10e1a0c80ecdc93e9346871a78e4d333 \ No newline at end of file +fddacec392eaa469e7503e0701c963ef \ No newline at end of file diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb index 9b6563d..abe150d 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt b/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt index d4f8b41..7674f9d 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt and b/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt differ diff --git a/output_files/spectrum.asm.rpt b/output_files/spectrum.asm.rpt index 0b03803..44a85f8 100644 --- a/output_files/spectrum.asm.rpt +++ b/output_files/spectrum.asm.rpt @@ -1,5 +1,5 @@ Assembler report for spectrum -Fri Apr 1 18:55:43 2022 +Sat Apr 2 14:51:11 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -37,7 +37,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Fri Apr 1 18:55:43 2022 ; +; Assembler Status ; Successful - Sat Apr 2 14:51:11 2022 ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; @@ -162,8 +162,8 @@ Default Value : On ; Option ; Setting ; +----------------+-----------------------+ ; Device ; EP4CE22F17C6 ; -; JTAG usercode ; 0x0056423F ; -; Checksum ; 0x0056423F ; +; JTAG usercode ; 0x0058B9EB ; +; Checksum ; 0x0058B9EB ; +----------------+-----------------------+ @@ -173,13 +173,13 @@ Default Value : On Info: ******************************************************************* Info: Running Quartus II 32-bit Assembler Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Fri Apr 1 18:55:41 2022 + Info: Processing started: Sat Apr 2 14:51:09 2022 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 385 megabytes - Info: Processing ended: Fri Apr 1 18:55:43 2022 + Info: Peak virtual memory: 383 megabytes + Info: Processing ended: Sat Apr 2 14:51:11 2022 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:02 diff --git a/output_files/spectrum.done b/output_files/spectrum.done index a426016..b81c623 100644 --- a/output_files/spectrum.done +++ b/output_files/spectrum.done @@ -1 +1 @@ -Fri Apr 1 18:55:53 2022 +Sat Apr 2 14:51:22 2022 diff --git a/output_files/spectrum.eda.rpt b/output_files/spectrum.eda.rpt index 32ae12e..c7835b6 100644 --- a/output_files/spectrum.eda.rpt +++ b/output_files/spectrum.eda.rpt @@ -1,5 +1,5 @@ EDA Netlist Writer report for spectrum -Fri Apr 1 18:55:53 2022 +Sat Apr 2 14:51:22 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -36,7 +36,7 @@ applicable agreement for further details. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Fri Apr 1 18:55:53 2022 ; +; EDA Netlist Writer Status ; Successful - Sat Apr 2 14:51:22 2022 ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; @@ -88,7 +88,7 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II 32-bit EDA Netlist Writer Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Fri Apr 1 18:55:50 2022 + Info: Processing started: Sat Apr 2 14:51:19 2022 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool @@ -99,8 +99,8 @@ Info (204019): Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder "/home/b Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 380 megabytes - Info: Processing ended: Fri Apr 1 18:55:53 2022 + Info: Peak virtual memory: 379 megabytes + Info: Processing ended: Sat Apr 2 14:51:22 2022 Info: Elapsed time: 00:00:03 Info: Total CPU time (on all processors): 00:00:03 diff --git a/output_files/spectrum.fit.rpt b/output_files/spectrum.fit.rpt index 21ded4a..c20f174 100644 --- a/output_files/spectrum.fit.rpt +++ b/output_files/spectrum.fit.rpt @@ -1,5 +1,5 @@ Fitter report for spectrum -Fri Apr 1 18:55:39 2022 +Sat Apr 2 14:51:07 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -34,9 +34,9 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 26. Global & Other Fast Signals 27. Non-Global High Fan-Out Signals 28. Fitter RAM Summary - 29. |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM + 29. |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM 30. |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM - 31. |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM + 31. |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM 32. Routing Usage Summary 33. LAB Logic Elements 34. LAB-wide Signals @@ -77,22 +77,22 @@ applicable agreement for further details. +---------------------------------------------------------------------------------+ ; Fitter Summary ; +------------------------------------+--------------------------------------------+ -; Fitter Status ; Successful - Fri Apr 1 18:55:39 2022 ; +; Fitter Status ; Successful - Sat Apr 2 14:51:07 2022 ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; ; Device ; EP4CE22F17C6 ; ; Timing Models ; Final ; -; Total logic elements ; 2,396 / 22,320 ( 11 % ) ; -; Total combinational functions ; 2,272 / 22,320 ( 10 % ) ; -; Dedicated logic registers ; 591 / 22,320 ( 3 % ) ; -; Total registers ; 600 ; -; Total pins ; 75 / 154 ( 49 % ) ; +; Total logic elements ; 2,609 / 22,320 ( 12 % ) ; +; Total combinational functions ; 2,490 / 22,320 ( 11 % ) ; +; Dedicated logic registers ; 635 / 22,320 ( 3 % ) ; +; Total registers ; 664 ; +; Total pins ; 114 / 154 ( 74 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 524,288 / 608,256 ( 86 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; -; Total PLLs ; 1 / 4 ( 25 % ) ; +; Total PLLs ; 2 / 4 ( 50 % ) ; +------------------------------------+--------------------------------------------+ @@ -321,81 +321,460 @@ Parallel compilation was disabled, but you have multiple processors available. E +----------------------------+--------+ -+--------------------------------------+ -; I/O Assignment Warnings ; -+-------------+------------------------+ -; Pin Name ; Reason ; -+-------------+------------------------+ -; LED[0] ; Missing drive strength ; -; LED[1] ; Missing drive strength ; -; LED[2] ; Missing drive strength ; -; LED[3] ; Missing drive strength ; -; LED[4] ; Missing drive strength ; -; LED[5] ; Missing drive strength ; -; LED[6] ; Missing drive strength ; -; LED[7] ; Missing drive strength ; -; AUD_XCK ; Missing drive strength ; -; AUD_ADCLRCK ; Missing drive strength ; -; AUD_DACLRCK ; Missing drive strength ; -; AUD_BCLK ; Missing drive strength ; -; AUD_DACDAT ; Missing drive strength ; -; VGA_R[0] ; Missing drive strength ; -; VGA_R[1] ; Missing drive strength ; -; VGA_R[2] ; Missing drive strength ; -; VGA_R[3] ; Missing drive strength ; -; VGA_G[0] ; Missing drive strength ; -; VGA_G[1] ; Missing drive strength ; -; VGA_G[2] ; Missing drive strength ; -; VGA_G[3] ; Missing drive strength ; -; VGA_B[0] ; Missing drive strength ; -; VGA_B[1] ; Missing drive strength ; -; VGA_B[2] ; Missing drive strength ; -; VGA_B[3] ; Missing drive strength ; -; VGA_HS ; Missing drive strength ; -; VGA_VS ; Missing drive strength ; -; GPIO_1[0] ; Missing drive strength ; -; GPIO_1[1] ; Missing drive strength ; -; GPIO_1[2] ; Missing drive strength ; -; GPIO_1[3] ; Missing drive strength ; -; GPIO_1[4] ; Missing drive strength ; -; GPIO_1[5] ; Missing drive strength ; -; GPIO_1[6] ; Missing drive strength ; -; GPIO_1[7] ; Missing drive strength ; -; GPIO_1[8] ; Missing drive strength ; -; GPIO_1[9] ; Missing drive strength ; -; GPIO_1[10] ; Missing drive strength ; -; GPIO_1[11] ; Missing drive strength ; -; GPIO_1[12] ; Missing drive strength ; -; GPIO_1[13] ; Missing drive strength ; -; GPIO_1[14] ; Missing drive strength ; -; GPIO_1[15] ; Missing drive strength ; -; GPIO_1[16] ; Missing drive strength ; -; GPIO_1[17] ; Missing drive strength ; -; GPIO_1[18] ; Missing drive strength ; -; GPIO_1[19] ; Missing drive strength ; -; GPIO_1[20] ; Missing drive strength ; -; GPIO_1[21] ; Missing drive strength ; -; GPIO_1[22] ; Missing drive strength ; -; GPIO_1[23] ; Missing drive strength ; -; GPIO_1[24] ; Missing drive strength ; -; GPIO_1[25] ; Missing drive strength ; -; GPIO_1[26] ; Missing drive strength ; -; GPIO_1[27] ; Missing drive strength ; -; GPIO_1[28] ; Missing drive strength ; -; GPIO_1[29] ; Missing drive strength ; -; GPIO_1[30] ; Missing drive strength ; -; GPIO_1[31] ; Missing drive strength ; -; GPIO_1[32] ; Missing drive strength ; -; GPIO_1[33] ; Missing drive strength ; -; buzzer_out ; Missing drive strength ; -; I2C_SCLK ; Missing drive strength ; -; I2C_SDAT ; Missing drive strength ; -+-------------+------------------------+ ++----------------------------------------+ +; I/O Assignment Warnings ; ++---------------+------------------------+ +; Pin Name ; Reason ; ++---------------+------------------------+ +; LED[0] ; Missing drive strength ; +; LED[1] ; Missing drive strength ; +; LED[2] ; Missing drive strength ; +; LED[3] ; Missing drive strength ; +; LED[4] ; Missing drive strength ; +; LED[5] ; Missing drive strength ; +; LED[6] ; Missing drive strength ; +; LED[7] ; Missing drive strength ; +; AUD_XCK ; Missing drive strength ; +; AUD_ADCLRCK ; Missing drive strength ; +; AUD_DACLRCK ; Missing drive strength ; +; AUD_BCLK ; Missing drive strength ; +; AUD_DACDAT ; Missing drive strength ; +; VGA_R[0] ; Missing drive strength ; +; VGA_R[1] ; Missing drive strength ; +; VGA_R[2] ; Missing drive strength ; +; VGA_R[3] ; Missing drive strength ; +; VGA_G[0] ; Missing drive strength ; +; VGA_G[1] ; Missing drive strength ; +; VGA_G[2] ; Missing drive strength ; +; VGA_G[3] ; Missing drive strength ; +; VGA_B[0] ; Missing drive strength ; +; VGA_B[1] ; Missing drive strength ; +; VGA_B[2] ; Missing drive strength ; +; VGA_B[3] ; Missing drive strength ; +; VGA_HS ; Missing drive strength ; +; VGA_VS ; Missing drive strength ; +; GPIO_1[0] ; Missing drive strength ; +; GPIO_1[1] ; Missing drive strength ; +; GPIO_1[2] ; Missing drive strength ; +; GPIO_1[3] ; Missing drive strength ; +; GPIO_1[4] ; Missing drive strength ; +; GPIO_1[5] ; Missing drive strength ; +; GPIO_1[6] ; Missing drive strength ; +; GPIO_1[7] ; Missing drive strength ; +; GPIO_1[8] ; Missing drive strength ; +; GPIO_1[9] ; Missing drive strength ; +; GPIO_1[10] ; Missing drive strength ; +; GPIO_1[11] ; Missing drive strength ; +; GPIO_1[12] ; Missing drive strength ; +; GPIO_1[13] ; Missing drive strength ; +; GPIO_1[14] ; Missing drive strength ; +; GPIO_1[15] ; Missing drive strength ; +; GPIO_1[16] ; Missing drive strength ; +; GPIO_1[17] ; Missing drive strength ; +; GPIO_1[18] ; Missing drive strength ; +; GPIO_1[19] ; Missing drive strength ; +; GPIO_1[20] ; Missing drive strength ; +; GPIO_1[21] ; Missing drive strength ; +; GPIO_1[22] ; Missing drive strength ; +; GPIO_1[23] ; Missing drive strength ; +; GPIO_1[24] ; Missing drive strength ; +; GPIO_1[25] ; Missing drive strength ; +; GPIO_1[26] ; Missing drive strength ; +; GPIO_1[27] ; Missing drive strength ; +; GPIO_1[28] ; Missing drive strength ; +; GPIO_1[29] ; Missing drive strength ; +; GPIO_1[30] ; Missing drive strength ; +; GPIO_1[31] ; Missing drive strength ; +; GPIO_1[32] ; Missing drive strength ; +; GPIO_1[33] ; Missing drive strength ; +; buzzer_out ; Missing drive strength ; +; DRAM_BA[0] ; Missing drive strength ; +; DRAM_BA[1] ; Missing drive strength ; +; DRAM_DQM[0] ; Missing drive strength ; +; DRAM_DQM[1] ; Missing drive strength ; +; DRAM_RAS_N ; Missing drive strength ; +; DRAM_CAS_N ; Missing drive strength ; +; DRAM_CKE ; Missing drive strength ; +; DRAM_CLK ; Missing drive strength ; +; DRAM_WE_N ; Missing drive strength ; +; DRAM_CS_N ; Missing drive strength ; +; DRAM_ADDR[0] ; Missing drive strength ; +; DRAM_ADDR[1] ; Missing drive strength ; +; DRAM_ADDR[2] ; Missing drive strength ; +; DRAM_ADDR[3] ; Missing drive strength ; +; DRAM_ADDR[4] ; Missing drive strength ; +; DRAM_ADDR[5] ; Missing drive strength ; +; DRAM_ADDR[6] ; Missing drive strength ; +; DRAM_ADDR[7] ; Missing drive strength ; +; DRAM_ADDR[8] ; Missing drive strength ; +; DRAM_ADDR[9] ; Missing drive strength ; +; DRAM_ADDR[10] ; Missing drive strength ; +; DRAM_ADDR[11] ; Missing drive strength ; +; DRAM_ADDR[12] ; Missing drive strength ; +; I2C_SCLK ; Missing drive strength ; +; I2C_SDAT ; Missing drive strength ; +; DRAM_DQ[0] ; Missing drive strength ; +; DRAM_DQ[1] ; Missing drive strength ; +; DRAM_DQ[2] ; Missing drive strength ; +; DRAM_DQ[3] ; Missing drive strength ; +; DRAM_DQ[4] ; Missing drive strength ; +; DRAM_DQ[5] ; Missing drive strength ; +; DRAM_DQ[6] ; Missing drive strength ; +; DRAM_DQ[7] ; Missing drive strength ; +; DRAM_DQ[8] ; Missing drive strength ; +; DRAM_DQ[9] ; Missing drive strength ; +; DRAM_DQ[10] ; Missing drive strength ; +; DRAM_DQ[11] ; Missing drive strength ; +; DRAM_DQ[12] ; Missing drive strength ; +; DRAM_DQ[13] ; Missing drive strength ; +; DRAM_DQ[14] ; Missing drive strength ; +; DRAM_DQ[15] ; Missing drive strength ; ++---------------+------------------------+ +--------------------------------------------------------------------------------+ ; Fitter Netlist Optimizations ; +--------------------------------------------------------------------------------+ +Node : sdram_controller:sdram_|r.address[0] +Action : Duplicated +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1 +Destination Port : Q +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[0] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[0]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[0]~SLOAD_MUX +Action : Created +Operation : Register Packing +Reason : Timing optimization +Node Port : COMBOUT +Node Port Name : +Destination Node : +Destination Port : +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[1] +Action : Duplicated +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : sdram_controller:sdram_|r.address[1]~_Duplicate_1 +Destination Port : Q +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[1] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[1]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[1]~SLOAD_MUX +Action : Created +Operation : Register Packing +Reason : Timing optimization +Node Port : COMBOUT +Node Port Name : +Destination Node : +Destination Port : +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[2] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[2]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[3] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[3]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[4] +Action : Duplicated +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : sdram_controller:sdram_|r.address[4]~_Duplicate_1 +Destination Port : Q +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[4] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[4]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[4]~SLOAD_MUX +Action : Created +Operation : Register Packing +Reason : Timing optimization +Node Port : COMBOUT +Node Port Name : +Destination Node : +Destination Port : +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[5] +Action : Duplicated +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 +Destination Port : Q +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[5] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[5]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[5]~SLOAD_MUX +Action : Created +Operation : Register Packing +Reason : Timing optimization +Node Port : COMBOUT +Node Port Name : +Destination Node : +Destination Port : +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[6] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[6]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[7] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[7]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[8] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[8]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[9] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[9]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[10] +Action : Duplicated +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : sdram_controller:sdram_|r.address[10]~_Duplicate_1 +Destination Port : Q +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[10] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[10]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[10]~SLOAD_MUX +Action : Created +Operation : Register Packing +Reason : Timing optimization +Node Port : COMBOUT +Node Port Name : +Destination Node : +Destination Port : +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[11] +Action : Duplicated +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1 +Destination Port : Q +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[11] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[11]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[11]~SLOAD_MUX +Action : Created +Operation : Register Packing +Reason : Timing optimization +Node Port : COMBOUT +Node Port Name : +Destination Node : +Destination Port : +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1 +Action : Duplicated +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2 +Destination Port : Q +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1 +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_ADDR[12]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.address[11]~_Duplicate_1SLOAD_MUX +Action : Created +Operation : Register Packing +Reason : Timing optimization +Node Port : COMBOUT +Node Port Name : +Destination Node : +Destination Port : +Destination Port Name : + +Node : sdram_controller:sdram_|r.bank[0] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_BA[0]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.bank[1] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_BA[1]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.dq_masks[0] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_DQM[0]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.dq_masks[1] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_DQM[1]~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.state[0] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_WE_N~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.state[1] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_CAS_N~output +Destination Port : I +Destination Port Name : + +Node : sdram_controller:sdram_|r.state[2] +Action : Packed Register +Operation : Register Packing +Reason : Timing optimization +Node Port : Q +Node Port Name : +Destination Node : DRAM_RAS_N~output +Destination Port : I +Destination Port Name : + Node : ula:ula_|i2c_loader:i2c_loader_|scl_out Action : Duplicated Operation : Register Packing @@ -620,279 +999,6 @@ Ignored To : ADC_SDAT Ignored Value : PIN_A9 Ignored Source : QSF Assignment -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_ADDR[0] -Ignored Value : PIN_P2 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_ADDR[10] -Ignored Value : PIN_N2 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_ADDR[11] -Ignored Value : PIN_N1 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_ADDR[12] -Ignored Value : PIN_L4 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_ADDR[1] -Ignored Value : PIN_N5 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_ADDR[2] -Ignored Value : PIN_N6 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_ADDR[3] -Ignored Value : PIN_M8 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_ADDR[4] -Ignored Value : PIN_P8 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_ADDR[5] -Ignored Value : PIN_T7 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_ADDR[6] -Ignored Value : PIN_N8 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_ADDR[7] -Ignored Value : PIN_T6 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_ADDR[8] -Ignored Value : PIN_R1 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_ADDR[9] -Ignored Value : PIN_P1 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_BA[0] -Ignored Value : PIN_M7 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_BA[1] -Ignored Value : PIN_M6 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_CAS_N -Ignored Value : PIN_L1 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_CKE -Ignored Value : PIN_L7 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_CLK -Ignored Value : PIN_R4 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_CS_N -Ignored Value : PIN_P6 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_DQM[0] -Ignored Value : PIN_R6 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_DQM[1] -Ignored Value : PIN_T5 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_DQ[0] -Ignored Value : PIN_G2 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_DQ[10] -Ignored Value : PIN_T3 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_DQ[11] -Ignored Value : PIN_R3 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_DQ[12] -Ignored Value : PIN_R5 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_DQ[13] -Ignored Value : PIN_P3 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_DQ[14] -Ignored Value : PIN_N3 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_DQ[15] -Ignored Value : PIN_K1 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_DQ[1] -Ignored Value : PIN_G1 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_DQ[2] -Ignored Value : PIN_L8 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_DQ[3] -Ignored Value : PIN_K5 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_DQ[4] -Ignored Value : PIN_K2 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_DQ[5] -Ignored Value : PIN_J2 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_DQ[6] -Ignored Value : PIN_J1 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_DQ[7] -Ignored Value : PIN_R7 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_DQ[8] -Ignored Value : PIN_T4 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_DQ[9] -Ignored Value : PIN_T2 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_RAS_N -Ignored Value : PIN_L2 -Ignored Source : QSF Assignment - -Name : Location -Ignored Entity : -Ignored From : -Ignored To : DRAM_WE_N -Ignored Value : PIN_C2 -Ignored Source : QSF Assignment - Name : Location Ignored Entity : Ignored From : @@ -1173,279 +1279,6 @@ Ignored To : ADC_SDAT Ignored Value : 3.3-V LVTTL Ignored Source : QSF Assignment -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_ADDR[0] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_ADDR[10] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_ADDR[11] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_ADDR[12] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_ADDR[1] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_ADDR[2] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_ADDR[3] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_ADDR[4] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_ADDR[5] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_ADDR[6] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_ADDR[7] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_ADDR[8] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_ADDR[9] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_BA[0] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_BA[1] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_CAS_N -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_CKE -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_CLK -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_CS_N -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_DQM[0] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_DQM[1] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_DQ[0] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_DQ[10] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_DQ[11] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_DQ[12] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_DQ[13] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_DQ[14] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_DQ[15] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_DQ[1] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_DQ[2] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_DQ[3] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_DQ[4] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_DQ[5] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_DQ[6] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_DQ[7] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_DQ[8] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_DQ[9] -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_RAS_N -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - -Name : I/O Standard -Ignored Entity : spectrum -Ignored From : -Ignored To : DRAM_WE_N -Ignored Value : 3.3-V LVTTL -Ignored Source : QSF Assignment - Name : I/O Standard Ignored Entity : spectrum Ignored From : @@ -1710,14 +1543,14 @@ From Design Partitions [A] : From Rapid Recompile [B] : Type : -- Requested -Total [A + B] : 0.00 % ( 0 / 3097 ) -From Design Partitions [A] : 0.00 % ( 0 / 3097 ) -From Rapid Recompile [B] : 0.00 % ( 0 / 3097 ) +Total [A + B] : 0.00 % ( 0 / 3462 ) +From Design Partitions [A] : 0.00 % ( 0 / 3462 ) +From Rapid Recompile [B] : 0.00 % ( 0 / 3462 ) Type : -- Achieved -Total [A + B] : 0.00 % ( 0 / 3097 ) -From Design Partitions [A] : 0.00 % ( 0 / 3097 ) -From Rapid Recompile [B] : 0.00 % ( 0 / 3097 ) +Total [A + B] : 0.00 % ( 0 / 3462 ) +From Design Partitions [A] : 0.00 % ( 0 / 3462 ) +From Rapid Recompile [B] : 0.00 % ( 0 / 3462 ) Type : Total [A + B] : @@ -1768,14 +1601,14 @@ Contents : hard_block:auto_generated_inst ; Incremental Compilation Placement Preservation ; +--------------------------------------------------------------------------------+ Partition Name : Top -Preservation Achieved : 0.00 % ( 0 / 3083 ) +Preservation Achieved : 0.00 % ( 0 / 3445 ) Preservation Level Used : N/A Netlist Type Used : Source File Preservation Method : N/A Notes : Partition Name : hard_block:auto_generated_inst -Preservation Achieved : 0.00 % ( 0 / 14 ) +Preservation Achieved : 0.00 % ( 0 / 17 ) Preservation Level Used : N/A Netlist Type Used : Source File Preservation Method : N/A @@ -1795,48 +1628,48 @@ The pin-out file can be found in /home/benny/work/fpga/spectrum/output_files/spe +---------------------------------------------+----------------------------+ ; Resource ; Usage ; +---------------------------------------------+----------------------------+ -; Total logic elements ; 2,396 / 22,320 ( 11 % ) ; -; -- Combinational with no register ; 1805 ; -; -- Register only ; 124 ; -; -- Combinational with a register ; 467 ; +; Total logic elements ; 2,609 / 22,320 ( 12 % ) ; +; -- Combinational with no register ; 1974 ; +; -- Register only ; 119 ; +; -- Combinational with a register ; 516 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 1640 ; -; -- 3 input functions ; 385 ; -; -- <=2 input functions ; 247 ; -; -- Register only ; 124 ; +; -- 4 input functions ; 1776 ; +; -- 3 input functions ; 423 ; +; -- <=2 input functions ; 291 ; +; -- Register only ; 119 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 2219 ; -; -- arithmetic mode ; 53 ; +; -- normal mode ; 2414 ; +; -- arithmetic mode ; 76 ; ; ; ; -; Total registers* ; 600 / 23,018 ( 3 % ) ; -; -- Dedicated logic registers ; 591 / 22,320 ( 3 % ) ; -; -- I/O registers ; 9 / 698 ( 1 % ) ; +; Total registers* ; 664 / 23,018 ( 3 % ) ; +; -- Dedicated logic registers ; 635 / 22,320 ( 3 % ) ; +; -- I/O registers ; 29 / 698 ( 4 % ) ; ; ; ; -; Total LABs: partially or completely used ; 185 / 1,395 ( 13 % ) ; +; Total LABs: partially or completely used ; 204 / 1,395 ( 15 % ) ; ; Virtual pins ; 0 ; -; I/O pins ; 75 / 154 ( 49 % ) ; +; I/O pins ; 114 / 154 ( 74 % ) ; ; -- Clock pins ; 5 / 7 ( 71 % ) ; ; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; ; ; ; -; Global signals ; 9 ; +; Global signals ; 10 ; ; M9Ks ; 64 / 66 ( 97 % ) ; ; Total block memory bits ; 524,288 / 608,256 ( 86 % ) ; ; Total block memory implementation bits ; 589,824 / 608,256 ( 97 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; -; PLLs ; 1 / 4 ( 25 % ) ; -; Global clocks ; 9 / 20 ( 45 % ) ; +; PLLs ; 2 / 4 ( 50 % ) ; +; Global clocks ; 10 / 20 ( 50 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; ; CRC blocks ; 0 / 1 ( 0 % ) ; ; ASMI blocks ; 0 / 1 ( 0 % ) ; ; Impedance control blocks ; 0 / 4 ( 0 % ) ; ; Average interconnect usage (total/H/V) ; 5% / 5% / 6% ; -; Peak interconnect usage (total/H/V) ; 29% / 26% / 33% ; +; Peak interconnect usage (total/H/V) ; 20% / 16% / 25% ; ; Maximum fan-out ; 435 ; -; Highest non-global fan-out ; 69 ; -; Total fan-out ; 11636 ; -; Average fan-out ; 3.66 ; +; Highest non-global fan-out ; 78 ; +; Total fan-out ; 12653 ; +; Average fan-out ; 3.56 ; +---------------------------------------------+----------------------------+ * Register count does not include registers inside RAM blocks or DSP blocks. @@ -1854,19 +1687,19 @@ Top : hard_block:auto_generated_inst : Statistic : Total logic elements -Top : 2396 / 22320 ( 11 % ) +Top : 2609 / 22320 ( 12 % ) hard_block:auto_generated_inst : 0 / 22320 ( 0 % ) Statistic : -- Combinational with no register -Top : 1805 +Top : 1974 hard_block:auto_generated_inst : 0 Statistic : -- Register only -Top : 124 +Top : 119 hard_block:auto_generated_inst : 0 Statistic : -- Combinational with a register -Top : 467 +Top : 516 hard_block:auto_generated_inst : 0 Statistic : @@ -1878,19 +1711,19 @@ Top : hard_block:auto_generated_inst : Statistic : -- 4 input functions -Top : 1640 +Top : 1776 hard_block:auto_generated_inst : 0 Statistic : -- 3 input functions -Top : 385 +Top : 423 hard_block:auto_generated_inst : 0 Statistic : -- <=2 input functions -Top : 247 +Top : 291 hard_block:auto_generated_inst : 0 Statistic : -- Register only -Top : 124 +Top : 119 hard_block:auto_generated_inst : 0 Statistic : @@ -1902,11 +1735,11 @@ Top : hard_block:auto_generated_inst : Statistic : -- normal mode -Top : 2219 +Top : 2414 hard_block:auto_generated_inst : 0 Statistic : -- arithmetic mode -Top : 53 +Top : 76 hard_block:auto_generated_inst : 0 Statistic : @@ -1914,15 +1747,15 @@ Top : hard_block:auto_generated_inst : Statistic : Total registers -Top : 600 +Top : 664 hard_block:auto_generated_inst : 0 Statistic : -- Dedicated logic registers -Top : 591 / 22320 ( 3 % ) +Top : 635 / 22320 ( 3 % ) hard_block:auto_generated_inst : 0 / 22320 ( 0 % ) Statistic : -- I/O registers -Top : 18 +Top : 58 hard_block:auto_generated_inst : 0 Statistic : @@ -1930,7 +1763,7 @@ Top : hard_block:auto_generated_inst : Statistic : Total LABs: partially or completely used -Top : 185 / 1395 ( 13 % ) +Top : 204 / 1395 ( 15 % ) hard_block:auto_generated_inst : 0 / 1395 ( 0 % ) Statistic : @@ -1942,7 +1775,7 @@ Top : 0 hard_block:auto_generated_inst : 0 Statistic : I/O pins -Top : 75 +Top : 114 hard_block:auto_generated_inst : 0 Statistic : Embedded Multiplier 9-bit elements @@ -1959,7 +1792,7 @@ hard_block:auto_generated_inst : 0 Statistic : PLL Top : 0 / 4 ( 0 % ) -hard_block:auto_generated_inst : 1 / 4 ( 25 % ) +hard_block:auto_generated_inst : 2 / 4 ( 50 % ) Statistic : M9K Top : 64 / 66 ( 96 % ) @@ -1967,10 +1800,10 @@ hard_block:auto_generated_inst : 0 / 66 ( 0 % ) Statistic : Clock control block Top : 6 / 24 ( 25 % ) -hard_block:auto_generated_inst : 3 / 24 ( 12 % ) +hard_block:auto_generated_inst : 5 / 24 ( 20 % ) Statistic : Double Data Rate I/O output circuitry -Top : 9 / 220 ( 4 % ) +Top : 29 / 220 ( 13 % ) hard_block:auto_generated_inst : 0 / 220 ( 0 % ) Statistic : @@ -1982,16 +1815,16 @@ Top : hard_block:auto_generated_inst : Statistic : -- Input Connections -Top : 197 -hard_block:auto_generated_inst : 1 +Top : 278 +hard_block:auto_generated_inst : 2 Statistic : -- Registered Input Connections -Top : 194 +Top : 258 hard_block:auto_generated_inst : 0 Statistic : -- Output Connections -Top : 3 -hard_block:auto_generated_inst : 195 +Top : 20 +hard_block:auto_generated_inst : 260 Statistic : -- Registered Output Connections Top : 0 @@ -2006,11 +1839,11 @@ Top : hard_block:auto_generated_inst : Statistic : -- Total Connections -Top : 11643 -hard_block:auto_generated_inst : 205 +Top : 12657 +hard_block:auto_generated_inst : 274 Statistic : -- Registered Connections -Top : 2921 +Top : 3469 hard_block:auto_generated_inst : 0 Statistic : @@ -2022,11 +1855,11 @@ Top : hard_block:auto_generated_inst : Statistic : -- Top -Top : 4 -hard_block:auto_generated_inst : 196 +Top : 36 +hard_block:auto_generated_inst : 262 Statistic : -- hard_block:auto_generated_inst -Top : 196 +Top : 262 hard_block:auto_generated_inst : 0 Statistic : @@ -2039,14 +1872,14 @@ hard_block:auto_generated_inst : Statistic : -- Input Ports Top : 11 -hard_block:auto_generated_inst : 1 +hard_block:auto_generated_inst : 2 Statistic : -- Output Ports -Top : 62 -hard_block:auto_generated_inst : 4 +Top : 85 +hard_block:auto_generated_inst : 6 Statistic : -- Bidir Ports -Top : 2 +Top : 18 hard_block:auto_generated_inst : 0 Statistic : @@ -2099,7 +1932,7 @@ hard_block:auto_generated_inst : 0 Statistic : -- Input Ports with no Fanout Top : 0 -hard_block:auto_generated_inst : 0 +hard_block:auto_generated_inst : 1 Statistic : -- Output Ports with no Fanout Top : 0 @@ -2135,7 +1968,7 @@ I/O Bank : 3 X coordinate : 27 Y coordinate : 0 Z coordinate : 21 -Combinational Fan-Out : 51 +Combinational Fan-Out : 52 Registered Fan-Out : 0 Global : yes Input Register : no @@ -2440,6 +2273,581 @@ Location assigned by : User Output Enable Source : - Output Enable Group : - +Name : DRAM_ADDR[0] +Pin # : P2 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 4 +Z coordinate : 14 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[10] +Pin # : N2 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 8 +Z coordinate : 21 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[11] +Pin # : N1 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 7 +Z coordinate : 0 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[12] +Pin # : L4 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 6 +Z coordinate : 14 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[1] +Pin # : N5 +I/O Bank : 3 +X coordinate : 5 +Y coordinate : 0 +Z coordinate : 7 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[2] +Pin # : N6 +I/O Bank : 3 +X coordinate : 5 +Y coordinate : 0 +Z coordinate : 0 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[3] +Pin # : M8 +I/O Bank : 3 +X coordinate : 20 +Y coordinate : 0 +Z coordinate : 7 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[4] +Pin # : P8 +I/O Bank : 3 +X coordinate : 25 +Y coordinate : 0 +Z coordinate : 14 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[5] +Pin # : T7 +I/O Bank : 3 +X coordinate : 18 +Y coordinate : 0 +Z coordinate : 21 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[6] +Pin # : N8 +I/O Bank : 3 +X coordinate : 20 +Y coordinate : 0 +Z coordinate : 0 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[7] +Pin # : T6 +I/O Bank : 3 +X coordinate : 14 +Y coordinate : 0 +Z coordinate : 0 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[8] +Pin # : R1 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 5 +Z coordinate : 21 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_ADDR[9] +Pin # : P1 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 4 +Z coordinate : 21 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_BA[0] +Pin # : M7 +I/O Bank : 3 +X coordinate : 11 +Y coordinate : 0 +Z coordinate : 14 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_BA[1] +Pin # : M6 +I/O Bank : 3 +X coordinate : 7 +Y coordinate : 0 +Z coordinate : 7 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_CAS_N +Pin # : L1 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 11 +Z coordinate : 7 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_CKE +Pin # : L7 +I/O Bank : 3 +X coordinate : 16 +Y coordinate : 0 +Z coordinate : 21 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_CLK +Pin # : R4 +I/O Bank : 3 +X coordinate : 5 +Y coordinate : 0 +Z coordinate : 21 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_CS_N +Pin # : P6 +I/O Bank : 3 +X coordinate : 11 +Y coordinate : 0 +Z coordinate : 21 +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_DQM[0] +Pin # : R6 +I/O Bank : 3 +X coordinate : 14 +Y coordinate : 0 +Z coordinate : 7 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_DQM[1] +Pin # : T5 +I/O Bank : 3 +X coordinate : 14 +Y coordinate : 0 +Z coordinate : 14 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_RAS_N +Pin # : L2 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 11 +Z coordinate : 0 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + +Name : DRAM_WE_N +Pin # : C2 +I/O Bank : 1 +X coordinate : 0 +Y coordinate : 27 +Z coordinate : 0 +Output Register : yes +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : no +Open Drain : no +TRI Primitive : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Termination : Off +Termination Control Block : -- +Output Buffer Pre-emphasis : no +Voltage Output Differential : no +Location assigned by : User +Output Enable Source : - +Output Enable Group : - + Name : GPIO_1[0] Pin # : F13 I/O Bank : 6 @@ -3871,6 +4279,438 @@ Output Enable Group : - +--------------------------------------------------------------------------------+ ; Bidir Pins ; +--------------------------------------------------------------------------------+ +Name : DRAM_DQ[0] +Pin # : G2 +I/O Bank : 1 +X coordinate : 0 +Y coordinate : 23 +Z coordinate : 14 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 (inverted) +Output Enable Group : - + +Name : DRAM_DQ[10] +Pin # : T3 +I/O Bank : 3 +X coordinate : 1 +Y coordinate : 0 +Z coordinate : 0 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 +Output Enable Group : - + +Name : DRAM_DQ[11] +Pin # : R3 +I/O Bank : 3 +X coordinate : 1 +Y coordinate : 0 +Z coordinate : 7 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 +Output Enable Group : - + +Name : DRAM_DQ[12] +Pin # : R5 +I/O Bank : 3 +X coordinate : 14 +Y coordinate : 0 +Z coordinate : 21 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 +Output Enable Group : - + +Name : DRAM_DQ[13] +Pin # : P3 +I/O Bank : 3 +X coordinate : 1 +Y coordinate : 0 +Z coordinate : 14 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 +Output Enable Group : - + +Name : DRAM_DQ[14] +Pin # : N3 +I/O Bank : 3 +X coordinate : 1 +Y coordinate : 0 +Z coordinate : 21 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 +Output Enable Group : - + +Name : DRAM_DQ[15] +Pin # : K1 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 12 +Z coordinate : 7 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 +Output Enable Group : - + +Name : DRAM_DQ[1] +Pin # : G1 +I/O Bank : 1 +X coordinate : 0 +Y coordinate : 23 +Z coordinate : 21 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 (inverted) +Output Enable Group : - + +Name : DRAM_DQ[2] +Pin # : L8 +I/O Bank : 3 +X coordinate : 18 +Y coordinate : 0 +Z coordinate : 7 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 (inverted) +Output Enable Group : - + +Name : DRAM_DQ[3] +Pin # : K5 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 7 +Z coordinate : 7 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 (inverted) +Output Enable Group : - + +Name : DRAM_DQ[4] +Pin # : K2 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 12 +Z coordinate : 0 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 (inverted) +Output Enable Group : - + +Name : DRAM_DQ[5] +Pin # : J2 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 15 +Z coordinate : 0 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 (inverted) +Output Enable Group : - + +Name : DRAM_DQ[6] +Pin # : J1 +I/O Bank : 2 +X coordinate : 0 +Y coordinate : 15 +Z coordinate : 7 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 (inverted) +Output Enable Group : - + +Name : DRAM_DQ[7] +Pin # : R7 +I/O Bank : 3 +X coordinate : 16 +Y coordinate : 0 +Z coordinate : 14 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : no +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 (inverted) +Output Enable Group : - + +Name : DRAM_DQ[8] +Pin # : T4 +I/O Bank : 3 +X coordinate : 5 +Y coordinate : 0 +Z coordinate : 14 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 +Output Enable Group : - + +Name : DRAM_DQ[9] +Pin # : T2 +I/O Bank : 3 +X coordinate : 3 +Y coordinate : 0 +Z coordinate : 0 +Combinational Fan-Out : 0 +Registered Fan-Out : 0 +Global : no +Input Register : no +Output Register : no +Output Enable Register : no +Power Up High : no +Slew Rate : 2 +PCI I/O Enabled : yes +Open Drain : yes +Bus Hold : no +Weak Pull Up : Off +I/O Standard : 3.3-V LVTTL +Current Strength : 8mA +Output Termination : Off +Termination Control Block : -- +Location assigned by : User +Load : 0 pF +Output Enable Source : sdram_controller:sdram_|Mux84~1 +Output Enable Group : - + Name : I2C_SCLK Pin # : F2 I/O Bank : 1 @@ -4124,17 +4964,17 @@ Pin Type : Dual Purpose Pin ; I/O Bank Usage ; +--------------------------------------------------------------------------------+ I/O Bank : 1 -Usage : 10 / 14 ( 71 % ) +Usage : 13 / 14 ( 93 % ) VCCIO Voltage : 3.3V VREF Voltage : -- I/O Bank : 2 -Usage : 2 / 16 ( 13 % ) +Usage : 15 / 16 ( 94 % ) VCCIO Voltage : 3.3V VREF Voltage : -- I/O Bank : 3 -Usage : 2 / 25 ( 8 % ) +Usage : 25 / 25 ( 100 % ) VCCIO Voltage : 3.3V VREF Voltage : -- @@ -4568,14 +5408,14 @@ Weak Pull Up : On Location : C2 Pad Number : 6 I/O Bank : 1 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_WE_N +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Row I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : C3 Pad Number : 245 @@ -5324,26 +6164,26 @@ Weak Pull Up : Off Location : G1 Pad Number : 16 I/O Bank : 1 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_DQ[1] +Dir. : bidir +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Row I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : G2 Pad Number : 15 I/O Bank : 1 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_DQ[0] +Dir. : bidir +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Row I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : G3 Pad Number : @@ -5720,26 +6560,26 @@ Weak Pull Up : -- Location : J1 Pad Number : 30 I/O Bank : 2 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_DQ[6] +Dir. : bidir +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Row I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : J2 Pad Number : 29 I/O Bank : 2 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_DQ[5] +Dir. : bidir +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Row I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : J3 Pad Number : 24 @@ -5912,26 +6752,26 @@ Weak Pull Up : Off Location : K1 Pad Number : 37 I/O Bank : 2 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_DQ[15] +Dir. : bidir +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Row I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : K2 Pad Number : 36 I/O Bank : 2 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_DQ[4] +Dir. : bidir +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Row I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : K3 Pad Number : @@ -5960,14 +6800,14 @@ Weak Pull Up : -- Location : K5 Pad Number : 45 I/O Bank : 2 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_DQ[3] +Dir. : bidir +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Row I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : K6 Pad Number : @@ -6104,26 +6944,26 @@ Weak Pull Up : Off Location : L1 Pad Number : 39 I/O Bank : 2 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_CAS_N +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Row I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : L2 Pad Number : 38 I/O Bank : 2 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_RAS_N +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Row I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : L3 Pad Number : 40 @@ -6140,14 +6980,14 @@ Weak Pull Up : Off Location : L4 Pad Number : 46 I/O Bank : 2 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_ADDR[12] +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Row I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : L5 Pad Number : @@ -6176,26 +7016,26 @@ Weak Pull Up : -- Location : L7 Pad Number : 75 I/O Bank : 3 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_CKE +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : L8 Pad Number : 79 I/O Bank : 3 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_DQ[2] +Dir. : bidir +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : L9 Pad Number : @@ -6356,38 +7196,38 @@ Weak Pull Up : -- Location : M6 Pad Number : 64 I/O Bank : 3 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_BA[1] +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : M7 Pad Number : 68 I/O Bank : 3 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_BA[0] +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : M8 Pad Number : 81 I/O Bank : 3 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_ADDR[3] +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : M9 Pad Number : @@ -6488,38 +7328,38 @@ Weak Pull Up : -- Location : N1 Pad Number : 44 I/O Bank : 2 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_ADDR[11] +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Row I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : N2 Pad Number : 43 I/O Bank : 2 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_ADDR[10] +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Row I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : N3 Pad Number : 52 I/O Bank : 3 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_DQ[14] +Dir. : bidir +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : N4 Pad Number : @@ -6536,26 +7376,26 @@ Weak Pull Up : -- Location : N5 Pad Number : 62 I/O Bank : 3 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_ADDR[1] +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : N6 Pad Number : 63 I/O Bank : 3 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_ADDR[2] +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : N7 Pad Number : @@ -6572,14 +7412,14 @@ Weak Pull Up : -- Location : N8 Pad Number : 82 I/O Bank : 3 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_ADDR[6] +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : N9 Pad Number : 93 @@ -6680,38 +7520,38 @@ Weak Pull Up : Off Location : P1 Pad Number : 51 I/O Bank : 2 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_ADDR[9] +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Row I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : P2 Pad Number : 50 I/O Bank : 2 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_ADDR[0] +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Row I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : P3 Pad Number : 53 I/O Bank : 3 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_DQ[13] +Dir. : bidir +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : P4 Pad Number : @@ -6740,14 +7580,14 @@ Weak Pull Up : -- Location : P6 Pad Number : 67 I/O Bank : 3 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_CS_N +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : -Bus Hold : -- -Weak Pull Up : -- +User Assignment : Y +Bus Hold : no +Weak Pull Up : Off Location : P7 Pad Number : @@ -6764,14 +7604,14 @@ Weak Pull Up : -- Location : P8 Pad Number : 85 I/O Bank : 3 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_ADDR[4] +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : P9 Pad Number : 105 @@ -6872,14 +7712,14 @@ Weak Pull Up : Off Location : R1 Pad Number : 49 I/O Bank : 2 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_ADDR[8] +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Row I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : R2 Pad Number : @@ -6896,62 +7736,62 @@ Weak Pull Up : -- Location : R3 Pad Number : 54 I/O Bank : 3 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_DQ[11] +Dir. : bidir +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : R4 Pad Number : 60 I/O Bank : 3 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_CLK +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : R5 Pad Number : 71 I/O Bank : 3 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_DQ[12] +Dir. : bidir +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : R6 Pad Number : 73 I/O Bank : 3 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_DQM[0] +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : R7 Pad Number : 76 I/O Bank : 3 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_DQ[7] +Dir. : bidir +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : R8 Pad Number : 86 @@ -7076,74 +7916,74 @@ Weak Pull Up : -- Location : T2 Pad Number : 59 I/O Bank : 3 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_DQ[9] +Dir. : bidir +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : T3 Pad Number : 55 I/O Bank : 3 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_DQ[10] +Dir. : bidir +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : T4 Pad Number : 61 I/O Bank : 3 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_DQ[8] +Dir. : bidir +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : T5 Pad Number : 72 I/O Bank : 3 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_DQM[1] +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : T6 Pad Number : 74 I/O Bank : 3 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_ADDR[7] +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : T7 Pad Number : 77 I/O Bank : 3 -Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP -Dir. : -I/O Standard : +Pin Name/Usage : DRAM_ADDR[5] +Dir. : output +I/O Standard : 3.3-V LVTTL Voltage : I/O Type : Column I/O -User Assignment : +User Assignment : Y Bus Hold : no -Weak Pull Up : On +Weak Pull Up : Off Location : T8 Pad Number : 87 @@ -7257,50 +8097,179 @@ Weak Pull Up : -- Note: Pin directions (input, output or bidir) are based on device operating in user mode. -+----------------------------------------------------------------------------------------------------------+ -; PLL Summary ; -+-------------------------------+--------------------------------------------------------------------------+ -; Name ; ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 ; -+-------------------------------+--------------------------------------------------------------------------+ -; SDC pin name ; ula_|pll_|altpll_component|auto_generated|pll1 ; -; PLL mode ; Normal ; -; Compensate clock ; clock0 ; -; Compensated input/output pins ; -- ; -; Switchover type ; -- ; -; Input frequency 0 ; 50.0 MHz ; -; Input frequency 1 ; -- ; -; Nominal PFD frequency ; 7.1 MHz ; -; Nominal VCO frequency ; 1007.1 MHz ; -; VCO post scale K counter ; -- ; -; VCO frequency control ; Auto ; -; VCO phase shift step ; 124 ps ; -; VCO multiply ; -- ; -; VCO divide ; -- ; -; Freq min lock ; 37.8 MHz ; -; Freq max lock ; 64.56 MHz ; -; M VCO Tap ; 0 ; -; M Initial ; 1 ; -; M value ; 141 ; -; N value ; 7 ; -; Charge pump current ; setting 1 ; -; Loop filter resistance ; setting 16 ; -; Loop filter capacitance ; setting 0 ; -; Bandwidth ; 340 kHz to 540 kHz ; -; Bandwidth type ; Medium ; -; Real time reconfigurable ; Off ; -; Scan chain MIF file ; -- ; -; Preserve PLL counter order ; Off ; -; PLL location ; PLL_4 ; -; Inclk0 signal ; CLOCK_50 ; -; Inclk1 signal ; -- ; -; Inclk0 signal type ; Dedicated Pin ; -; Inclk1 signal type ; -- ; -+-------------------------------+--------------------------------------------------------------------------+ ++--------------------------------------------------------------------------------+ +; PLL Summary ; ++--------------------------------------------------------------------------------+ +Name : SDC pin name +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : ula_|pll_|altpll_component|auto_generated|pll1 + +Name : PLL mode +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : Normal +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : Normal + +Name : Compensate clock +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : clock0 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : clock0 + +Name : Compensated input/output pins +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : -- +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : -- + +Name : Switchover type +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : -- +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : -- + +Name : Input frequency 0 +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 50.0 MHz +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : 50.0 MHz + +Name : Input frequency 1 +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : -- +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : -- + +Name : Nominal PFD frequency +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 50.0 MHz +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : 7.1 MHz + +Name : Nominal VCO frequency +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 500.0 MHz +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : 1007.1 MHz + +Name : VCO post scale K counter +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 2 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : -- + +Name : VCO frequency control +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : Auto +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : Auto + +Name : VCO phase shift step +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 250 ps +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : 124 ps + +Name : VCO multiply +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : -- +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : -- + +Name : VCO divide +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : -- +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : -- + +Name : Freq min lock +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 30.0 MHz +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : 37.8 MHz + +Name : Freq max lock +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 65.02 MHz +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : 64.56 MHz + +Name : M VCO Tap +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 0 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : 0 + +Name : M Initial +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 1 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : 1 + +Name : M value +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 10 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : 141 + +Name : N value +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 1 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : 7 + +Name : Charge pump current +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : setting 1 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : setting 1 + +Name : Loop filter resistance +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : setting 27 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : setting 16 + +Name : Loop filter capacitance +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : setting 0 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : setting 0 + +Name : Bandwidth +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : 1.03 MHz to 1.97 MHz +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : 340 kHz to 540 kHz + +Name : Bandwidth type +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : Medium +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : Medium + +Name : Real time reconfigurable +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : Off +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : Off + +Name : Scan chain MIF file +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : -- +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : -- + +Name : Preserve PLL counter order +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : Off +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : Off + +Name : PLL location +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : PLL_1 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : PLL_4 + +Name : Inclk0 signal +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : CLOCK_50 +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : CLOCK_50 + +Name : Inclk1 signal +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : -- +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : -- + +Name : Inclk0 signal type +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : Dedicated Pin +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : Dedicated Pin + +Name : Inclk1 signal type +sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 : -- +ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 : -- ++--------------------------------------------------------------------------------+ + +--------------------------------------------------------------------------------+ ; PLL Usage ; +--------------------------------------------------------------------------------+ +Name : sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] +Output Clock : clock0 +Mult : 2 +Div : 1 +Output Frequency : 100.0 MHz +Phase Shift : 0 (0 ps) +Phase Shift Step : 9.00 (250 ps) +Duty Cycle : 50/50 +Counter : C1 +Counter Value : 5 +High / Low : 3/2 Odd +Cascade Input : -- +Initial : 1 +VCO Tap : 0 +SDC Pin Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Name : sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[1] +Output Clock : clock1 +Mult : 2 +Div : 1 +Output Frequency : 100.0 MHz +Phase Shift : 108 (3000 ps) +Phase Shift Step : 9.00 (250 ps) +Duty Cycle : 50/50 +Counter : C0 +Counter Value : 5 +High / Low : 3/2 Odd +Cascade Input : -- +Initial : 2 +VCO Tap : 4 +SDC Pin Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + Name : ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] Output Clock : clock0 Mult : 141 @@ -7356,19 +8325,19 @@ SDC Pin Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] ; Fitter Resource Utilization by Entity ; +--------------------------------------------------------------------------------+ Compilation Hierarchy Node : |spectrum -Logic Cells : 2396 (98) -Dedicated Logic Registers : 591 (0) -I/O Registers : 9 (9) +Logic Cells : 2609 (106) +Dedicated Logic Registers : 635 (0) +I/O Registers : 29 (29) Memory Bits : 524288 M9Ks : 64 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 -Pins : 75 +Pins : 114 Virtual Pins : 0 -LUT-Only LCs : 1805 (96) -Register-Only LCs : 124 (0) -LUT/Register LCs : 467 (2) +LUT-Only LCs : 1974 (105) +Register-Only LCs : 119 (0) +LUT/Register LCs : 516 (3) Full Hierarchy Name : |spectrum Library Name : work @@ -7384,8 +8353,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 2 (0) -Register-Only LCs : 1 (0) -LUT/Register LCs : 1 (0) +Register-Only LCs : 2 (0) +LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|ram16:ram0 Library Name : work @@ -7401,8 +8370,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 2 (0) -Register-Only LCs : 1 (0) -LUT/Register LCs : 1 (0) +Register-Only LCs : 2 (0) +LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component Library Name : work @@ -7418,8 +8387,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 2 (0) -Register-Only LCs : 1 (1) -LUT/Register LCs : 1 (1) +Register-Only LCs : 2 (2) +LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated Library Name : work @@ -7441,7 +8410,7 @@ Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_componen Library Name : work Compilation Hierarchy Node : |ram32:ram1| -Logic Cells : 19 (0) +Logic Cells : 16 (0) Dedicated Logic Registers : 4 (0) I/O Registers : 0 (0) Memory Bits : 262144 @@ -7451,14 +8420,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 15 (0) -Register-Only LCs : 0 (0) -LUT/Register LCs : 4 (0) +LUT-Only LCs : 12 (0) +Register-Only LCs : 1 (0) +LUT/Register LCs : 3 (0) Full Hierarchy Name : |spectrum|ram32:ram1 Library Name : work Compilation Hierarchy Node : |altsyncram:altsyncram_component| -Logic Cells : 19 (0) +Logic Cells : 16 (0) Dedicated Logic Registers : 4 (0) I/O Registers : 0 (0) Memory Bits : 262144 @@ -7468,14 +8437,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 15 (0) -Register-Only LCs : 0 (0) -LUT/Register LCs : 4 (0) +LUT-Only LCs : 12 (0) +Register-Only LCs : 1 (0) +LUT/Register LCs : 3 (0) Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component Library Name : work Compilation Hierarchy Node : |altsyncram_g9i1:auto_generated| -Logic Cells : 19 (4) +Logic Cells : 16 (4) Dedicated Logic Registers : 4 (4) I/O Registers : 0 (0) Memory Bits : 262144 @@ -7485,9 +8454,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 15 (0) -Register-Only LCs : 0 (0) -LUT/Register LCs : 4 (3) +LUT-Only LCs : 12 (0) +Register-Only LCs : 1 (1) +LUT/Register LCs : 3 (3) Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated Library Name : work @@ -7526,7 +8495,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_componen Library Name : work Compilation Hierarchy Node : |mux_6nb:mux2| -Logic Cells : 8 (8) +Logic Cells : 4 (4) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -7536,9 +8505,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 7 (7) +LUT-Only LCs : 4 (4) Register-Only LCs : 0 (0) -LUT/Register LCs : 1 (1) +LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|mux_6nb:mux2 Library Name : work @@ -7593,8 +8562,76 @@ LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated Library Name : work +Compilation Hierarchy Node : |sdram_controller:sdram_| +Logic Cells : 229 (229) +Dedicated Logic Registers : 44 (44) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 185 (185) +Register-Only LCs : 4 (4) +LUT/Register LCs : 40 (40) +Full Hierarchy Name : |spectrum|sdram_controller:sdram_ +Library Name : work + +Compilation Hierarchy Node : |sdram_clk_gen:sdram_clk_pll| +Logic Cells : 0 (0) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll +Library Name : work + +Compilation Hierarchy Node : |altpll:altpll_component| +Logic Cells : 0 (0) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component +Library Name : work + +Compilation Hierarchy Node : |sdram_clk_gen_altpll:auto_generated| +Logic Cells : 0 (0) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated +Library Name : work + Compilation Hierarchy Node : |ula:ula_| -Logic Cells : 458 (9) +Logic Cells : 456 (9) Dedicated Logic Registers : 223 (7) I/O Registers : 0 (0) Memory Bits : 0 @@ -7604,9 +8641,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 235 (2) -Register-Only LCs : 36 (3) -LUT/Register LCs : 187 (3) +LUT-Only LCs : 233 (2) +Register-Only LCs : 37 (5) +LUT/Register LCs : 186 (2) Full Hierarchy Name : |spectrum|ula:ula_ Library Name : work @@ -7655,9 +8692,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 27 (27) +LUT-Only LCs : 28 (28) Register-Only LCs : 1 (1) -LUT/Register LCs : 41 (41) +LUT/Register LCs : 40 (40) Full Hierarchy Name : |spectrum|ula:ula_|i2s_intf:i2s_intf_ Library Name : work @@ -7713,7 +8750,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|pll:pll_|altpll:altpll_component Library Name : work Compilation Hierarchy Node : |ps2_keyboard:ps2_keyboard_| -Logic Cells : 31 (31) +Logic Cells : 30 (30) Dedicated Logic Registers : 24 (24) I/O Registers : 0 (0) Memory Bits : 0 @@ -7723,14 +8760,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 7 (7) -Register-Only LCs : 7 (7) -LUT/Register LCs : 17 (17) +LUT-Only LCs : 6 (6) +Register-Only LCs : 8 (8) +LUT/Register LCs : 16 (16) Full Hierarchy Name : |spectrum|ula:ula_|ps2_keyboard:ps2_keyboard_ Library Name : work Compilation Hierarchy Node : |video:video_| -Logic Cells : 124 (124) +Logic Cells : 122 (122) Dedicated Logic Registers : 72 (72) I/O Registers : 0 (0) Memory Bits : 0 @@ -7740,14 +8777,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 52 (52) -Register-Only LCs : 25 (25) -LUT/Register LCs : 47 (47) +LUT-Only LCs : 50 (50) +Register-Only LCs : 23 (23) +LUT/Register LCs : 49 (49) Full Hierarchy Name : |spectrum|ula:ula_|video:video_ Library Name : work Compilation Hierarchy Node : |zx_keyboard:zx_keyboard_| -Logic Cells : 150 (150) +Logic Cells : 148 (148) Dedicated Logic Registers : 43 (43) I/O Registers : 0 (0) Memory Bits : 0 @@ -7759,12 +8796,12 @@ Pins : 0 Virtual Pins : 0 LUT-Only LCs : 99 (99) Register-Only LCs : 0 (0) -LUT/Register LCs : 51 (51) +LUT/Register LCs : 49 (49) Full Hierarchy Name : |spectrum|ula:ula_|zx_keyboard:zx_keyboard_ Library Name : work Compilation Hierarchy Node : |z80_top_direct_n:z80_| -Logic Cells : 1822 (2) +Logic Cells : 1800 (2) Dedicated Logic Registers : 362 (1) I/O Registers : 0 (0) Memory Bits : 0 @@ -7774,14 +8811,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 1457 (1) -Register-Only LCs : 87 (0) -LUT/Register LCs : 278 (2) +LUT-Only LCs : 1437 (1) +Register-Only LCs : 75 (0) +LUT/Register LCs : 288 (2) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_ Library Name : work Compilation Hierarchy Node : |address_latch:address_latch_| -Logic Cells : 57 (26) +Logic Cells : 47 (18) Dedicated Logic Registers : 16 (16) I/O Registers : 0 (0) Memory Bits : 0 @@ -7791,14 +8828,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 41 (10) -Register-Only LCs : 7 (7) -LUT/Register LCs : 9 (8) +LUT-Only LCs : 29 (0) +Register-Only LCs : 2 (2) +LUT/Register LCs : 16 (16) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_ Library Name : work Compilation Hierarchy Node : |inc_dec:b2v_inst_inc_dec| -Logic Cells : 32 (14) +Logic Cells : 29 (12) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -7808,14 +8845,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 31 (13) +LUT-Only LCs : 29 (12) Register-Only LCs : 0 (0) -LUT/Register LCs : 1 (1) +LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec Library Name : work Compilation Hierarchy Node : |inc_dec_2bit:b2v_dual_adder_0| -Logic Cells : 4 (4) +Logic Cells : 3 (3) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -7825,7 +8862,7 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 4 (4) +LUT-Only LCs : 3 (3) Register-Only LCs : 0 (0) LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_0 @@ -7927,14 +8964,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 13 (13) +LUT-Only LCs : 15 (15) Register-Only LCs : 0 (0) -LUT/Register LCs : 19 (19) +LUT/Register LCs : 17 (17) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_pins:address_pins_ Library Name : work Compilation Hierarchy Node : |alu:alu_| -Logic Cells : 130 (95) +Logic Cells : 128 (91) Dedicated Logic Registers : 20 (20) I/O Registers : 0 (0) Memory Bits : 0 @@ -7944,9 +8981,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 107 (74) +LUT-Only LCs : 107 (70) Register-Only LCs : 0 (0) -LUT/Register LCs : 23 (3) +LUT/Register LCs : 21 (5) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_ Library Name : work @@ -7961,9 +8998,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 0 (0) +LUT-Only LCs : 2 (2) Register-Only LCs : 0 (0) -LUT/Register LCs : 2 (2) +LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_bit_select:b2v_input_bit_select Library Name : work @@ -7978,9 +9015,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 18 (0) +LUT-Only LCs : 20 (0) Register-Only LCs : 0 (0) -LUT/Register LCs : 2 (0) +LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core Library Name : work @@ -8002,24 +9039,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b Library Name : work Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_1| -Logic Cells : 4 (4) -Dedicated Logic Registers : 0 (0) -I/O Registers : 0 (0) -Memory Bits : 0 -M9Ks : 0 -DSP Elements : 0 -DSP 9x9 : 0 -DSP 18x18 : 0 -Pins : 0 -Virtual Pins : 0 -LUT-Only LCs : 4 (4) -Register-Only LCs : 0 (0) -LUT/Register LCs : 0 (0) -Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1 -Library Name : work - -Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_2| -Logic Cells : 6 (6) +Logic Cells : 5 (5) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -8031,12 +9051,12 @@ Pins : 0 Virtual Pins : 0 LUT-Only LCs : 5 (5) Register-Only LCs : 0 (0) -LUT/Register LCs : 1 (1) -Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2 +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1 Library Name : work -Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_3| -Logic Cells : 5 (5) +Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_2| +Logic Cells : 7 (7) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -8046,9 +9066,26 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 4 (4) +LUT-Only LCs : 7 (7) Register-Only LCs : 0 (0) -LUT/Register LCs : 1 (1) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2 +Library Name : work + +Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_3| +Logic Cells : 3 (3) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 3 (3) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3 Library Name : work @@ -8131,9 +9168,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 39 (34) +LUT-Only LCs : 38 (33) Register-Only LCs : 0 (0) -LUT/Register LCs : 2 (2) +LUT/Register LCs : 3 (3) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_control:alu_control_ Library Name : work @@ -8172,7 +9209,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_control:alu_con Library Name : work Compilation Hierarchy Node : |alu_flags:alu_flags_| -Logic Cells : 63 (63) +Logic Cells : 61 (61) Dedicated Logic Registers : 10 (10) I/O Registers : 0 (0) Memory Bits : 0 @@ -8182,7 +9219,7 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 53 (53) +LUT-Only LCs : 51 (51) Register-Only LCs : 0 (0) LUT/Register LCs : 10 (10) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_flags:alu_flags_ @@ -8199,9 +9236,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 14 (14) +LUT-Only LCs : 12 (12) Register-Only LCs : 0 (0) -LUT/Register LCs : 4 (4) +LUT/Register LCs : 6 (6) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|bus_control:bus_control_ Library Name : work @@ -8222,6 +9259,23 @@ LUT/Register LCs : 1 (1) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|clk_delay:clk_delay_ Library Name : work +Compilation Hierarchy Node : |control_pins_n:control_pins_| +Logic Cells : 1 (1) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 1 (1) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|control_pins_n:control_pins_ +Library Name : work + Compilation Hierarchy Node : |data_pins:data_pins_| Logic Cells : 9 (9) Dedicated Logic Registers : 8 (8) @@ -8257,7 +9311,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_switch:sw2_ Library Name : work Compilation Hierarchy Node : |data_switch_mask:sw1_| -Logic Cells : 2 (2) +Logic Cells : 4 (4) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -8267,9 +9321,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 2 (2) +LUT-Only LCs : 3 (3) Register-Only LCs : 0 (0) -LUT/Register LCs : 0 (0) +LUT/Register LCs : 1 (1) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_switch_mask:sw1_ Library Name : work @@ -8284,14 +9338,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 7 (7) +LUT-Only LCs : 8 (8) Register-Only LCs : 0 (0) -LUT/Register LCs : 7 (7) +LUT/Register LCs : 6 (6) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|decode_state:decode_state_ Library Name : work Compilation Hierarchy Node : |execute:execute_| -Logic Cells : 933 (933) +Logic Cells : 926 (926) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -8301,14 +9355,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 923 (923) +LUT-Only LCs : 917 (917) Register-Only LCs : 0 (0) -LUT/Register LCs : 10 (10) +LUT/Register LCs : 9 (9) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|execute:execute_ Library Name : work Compilation Hierarchy Node : |interrupts:interrupts_| -Logic Cells : 15 (15) +Logic Cells : 14 (14) Dedicated Logic Registers : 8 (8) I/O Registers : 0 (0) Memory Bits : 0 @@ -8318,9 +9372,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 7 (7) -Register-Only LCs : 1 (1) -LUT/Register LCs : 7 (7) +LUT-Only LCs : 6 (6) +Register-Only LCs : 0 (0) +LUT/Register LCs : 8 (8) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|interrupts:interrupts_ Library Name : work @@ -8336,13 +9390,13 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 3 (3) -LUT/Register LCs : 5 (5) +Register-Only LCs : 1 (1) +LUT/Register LCs : 7 (7) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|ir:ir_ Library Name : work Compilation Hierarchy Node : |memory_ifc:memory_ifc_| -Logic Cells : 22 (22) +Logic Cells : 26 (26) Dedicated Logic Registers : 20 (20) I/O Registers : 0 (0) Memory Bits : 0 @@ -8352,14 +9406,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 2 (2) -Register-Only LCs : 6 (6) -LUT/Register LCs : 14 (14) +LUT-Only LCs : 6 (6) +Register-Only LCs : 9 (9) +LUT/Register LCs : 11 (11) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|memory_ifc:memory_ifc_ Library Name : work Compilation Hierarchy Node : |pin_control:pin_control_| -Logic Cells : 19 (19) +Logic Cells : 20 (20) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -8369,7 +9423,7 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 19 (19) +LUT-Only LCs : 20 (20) Register-Only LCs : 0 (0) LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|pin_control:pin_control_ @@ -8386,14 +9440,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 74 (74) +LUT-Only LCs : 73 (73) Register-Only LCs : 0 (0) -LUT/Register LCs : 0 (0) +LUT/Register LCs : 1 (1) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|pla_decode:pla_decode_ Library Name : work Compilation Hierarchy Node : |reg_control:reg_control_| -Logic Cells : 29 (29) +Logic Cells : 30 (30) Dedicated Logic Registers : 4 (4) I/O Registers : 0 (0) Memory Bits : 0 @@ -8403,14 +9457,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 25 (25) +LUT-Only LCs : 26 (26) Register-Only LCs : 0 (0) LUT/Register LCs : 4 (4) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_control:reg_control_ Library Name : work Compilation Hierarchy Node : |reg_file:reg_file_| -Logic Cells : 350 (128) +Logic Cells : 344 (124) Dedicated Logic Registers : 224 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -8420,9 +9474,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 126 (126) -Register-Only LCs : 68 (0) -LUT/Register LCs : 156 (147) +LUT-Only LCs : 120 (120) +Register-Only LCs : 61 (0) +LUT/Register LCs : 163 (150) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_ Library Name : work @@ -8489,8 +9543,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 6 (6) -LUT/Register LCs : 2 (2) +Register-Only LCs : 7 (7) +LUT/Register LCs : 1 (1) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af_lo Library Name : work @@ -8557,8 +9611,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 5 (5) -LUT/Register LCs : 3 (3) +Register-Only LCs : 3 (3) +LUT/Register LCs : 5 (5) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_bc_lo Library Name : work @@ -8693,8 +9747,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 7 (7) -LUT/Register LCs : 1 (1) +Register-Only LCs : 5 (5) +LUT/Register LCs : 3 (3) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_hl_lo Library Name : work @@ -8778,8 +9832,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 7 (7) -LUT/Register LCs : 1 (1) +Register-Only LCs : 6 (6) +LUT/Register LCs : 2 (2) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_iy_hi Library Name : work @@ -8795,8 +9849,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 5 (5) -LUT/Register LCs : 3 (3) +Register-Only LCs : 3 (3) +LUT/Register LCs : 5 (5) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_iy_lo Library Name : work @@ -8846,8 +9900,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 1 (1) -LUT/Register LCs : 7 (7) +Register-Only LCs : 2 (2) +LUT/Register LCs : 6 (6) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_sp_hi Library Name : work @@ -8863,8 +9917,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 3 (3) -LUT/Register LCs : 5 (5) +Register-Only LCs : 1 (1) +LUT/Register LCs : 7 (7) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_sp_lo Library Name : work @@ -8880,8 +9934,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 0 (0) -LUT/Register LCs : 8 (8) +Register-Only LCs : 1 (1) +LUT/Register LCs : 7 (7) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_wz_hi Library Name : work @@ -8897,8 +9951,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 1 (1) -LUT/Register LCs : 7 (7) +Register-Only LCs : 0 (0) +LUT/Register LCs : 8 (8) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_wz_lo Library Name : work @@ -9455,6 +10509,190 @@ Pad to Input Register : -- TCO : -- TCOE : -- +Name : DRAM_BA[0] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_BA[1] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_DQM[0] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_DQM[1] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_RAS_N +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_CAS_N +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_CKE +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_CLK +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_WE_N +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_CS_N +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_ADDR[0] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[1] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[2] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[3] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[4] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[5] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[6] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[7] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[8] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[9] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[10] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[11] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + +Name : DRAM_ADDR[12] +Pin Type : Output +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : (0) 0 ps +TCOE : -- + Name : I2C_SCLK Pin Type : Bidir Pad to Core 0 : -- @@ -9466,11 +10704,139 @@ TCOE : -- Name : I2C_SDAT Pin Type : Bidir Pad to Core 0 : (0) 0 ps -Pad to Core 1 : -- +Pad to Core 1 : (0) 0 ps Pad to Input Register : -- TCO : (0) 0 ps TCOE : -- +Name : DRAM_DQ[0] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[1] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[2] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[3] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[4] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[5] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[6] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[7] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[8] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[9] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[10] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[11] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[12] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[13] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[14] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + +Name : DRAM_DQ[15] +Pin Type : Bidir +Pad to Core 0 : -- +Pad to Core 1 : -- +Pad to Input Register : -- +TCO : -- +TCOE : -- + Name : SW[1] Pin Type : Input Pad to Core 0 : (0) 0 ps @@ -9513,8 +10879,8 @@ TCOE : -- Name : PS2_DAT Pin Type : Input -Pad to Core 0 : (6) 1314 ps -Pad to Core 1 : -- +Pad to Core 0 : -- +Pad to Core 1 : (6) 1314 ps Pad to Input Register : -- TCO : -- TCOE : -- @@ -9574,9 +10940,73 @@ Pad To Core Index : 0 Setting : 0 Source Pin / Fanout : - ula:ula_|i2c_loader:i2c_loader_|nbyte[1]~5 -Pad To Core Index : 0 +Pad To Core Index : 1 Setting : 0 +Source Pin / Fanout : DRAM_DQ[0] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[1] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[2] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[3] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[4] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[5] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[6] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[7] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[8] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[9] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[10] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[11] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[12] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[13] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[14] +Pad To Core Index : +Setting : + +Source Pin / Fanout : DRAM_DQ[15] +Pad To Core Index : +Setting : + Source Pin / Fanout : SW[1] Pad To Core Index : Setting : @@ -9589,7 +11019,7 @@ Source Pin / Fanout : raw_loader_in Pad To Core Index : Setting : -Source Pin / Fanout : - D[6]~86 +Source Pin / Fanout : - D[6]~99 Pad To Core Index : 1 Setting : 0 @@ -9618,15 +11048,15 @@ Pad To Core Index : Setting : Source Pin / Fanout : - ula:ula_|ps2_keyboard:ps2_keyboard_|always1~0 -Pad To Core Index : 0 +Pad To Core Index : 1 Setting : 6 Source Pin / Fanout : - ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[8] -Pad To Core Index : 0 +Pad To Core Index : 1 Setting : 6 Source Pin / Fanout : - ula:ula_|ps2_keyboard:ps2_keyboard_|scan_code_ready~0 -Pad To Core Index : 0 +Pad To Core Index : 1 Setting : 6 Source Pin / Fanout : KEY[1] @@ -9655,6 +11085,15 @@ Setting : 0 +--------------------------------------------------------------------------------+ ; Control Signals ; +--------------------------------------------------------------------------------+ +Name : CLOCK_50 +Location : PIN_R8 +Fan-Out : 3 +Usage : Clock +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + Name : CLOCK_50 Location : PIN_R8 Fan-Out : 34 @@ -9664,18 +11103,9 @@ Global Resource Used : Global Clock Global Line Name : GCLK15 Enable Signal Source Name : -- -Name : CLOCK_50 -Location : PIN_R8 -Fan-Out : 2 -Usage : Clock -Global : no -Global Resource Used : -- -Global Line Name : -- -Enable Signal Source Name : -- - -Name : D[0]~107 -Location : LCCOMB_X31_Y12_N10 -Fan-Out : 10 +Name : D[0]~121 +Location : LCCOMB_X25_Y17_N24 +Fan-Out : 8 Usage : Output enable Global : no Global Resource Used : -- @@ -9692,7 +11122,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[0]~0 -Location : LCCOMB_X32_Y14_N2 +Location : LCCOMB_X21_Y13_N24 Fan-Out : 8 Usage : Write enable Global : no @@ -9701,7 +11131,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[1]~1 -Location : LCCOMB_X32_Y14_N10 +Location : LCCOMB_X23_Y18_N0 Fan-Out : 8 Usage : Write enable Global : no @@ -9710,7 +11140,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode|w_anode284w[2]~0 -Location : LCCOMB_X32_Y14_N22 +Location : LCCOMB_X25_Y8_N4 Fan-Out : 8 Usage : Clock enable Global : no @@ -9719,7 +11149,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode223w[2] -Location : LCCOMB_X32_Y14_N12 +Location : LCCOMB_X23_Y15_N22 Fan-Out : 8 Usage : Write enable Global : no @@ -9728,7 +11158,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode223w[2]~0 -Location : LCCOMB_X32_Y14_N18 +Location : LCCOMB_X25_Y8_N10 Fan-Out : 8 Usage : Clock enable Global : no @@ -9737,7 +11167,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode236w[2] -Location : LCCOMB_X32_Y14_N8 +Location : LCCOMB_X21_Y13_N0 Fan-Out : 8 Usage : Write enable Global : no @@ -9746,7 +11176,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode244w[2] -Location : LCCOMB_X32_Y14_N24 +Location : LCCOMB_X21_Y13_N6 Fan-Out : 8 Usage : Write enable Global : no @@ -9755,7 +11185,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode244w[2]~0 -Location : LCCOMB_X32_Y14_N26 +Location : LCCOMB_X25_Y8_N0 Fan-Out : 8 Usage : Clock enable Global : no @@ -9764,7 +11194,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode252w[2] -Location : LCCOMB_X32_Y14_N20 +Location : LCCOMB_X21_Y13_N14 Fan-Out : 8 Usage : Write enable Global : no @@ -9773,7 +11203,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode252w[2]~0 -Location : LCCOMB_X32_Y14_N6 +Location : LCCOMB_X25_Y8_N22 Fan-Out : 8 Usage : Clock enable Global : no @@ -9782,16 +11212,97 @@ Global Line Name : -- Enable Signal Source Name : -- Name : reset -Location : LCCOMB_X52_Y14_N4 +Location : LCCOMB_X52_Y14_N12 Fan-Out : 149 Usage : Async. clear, Async. load Global : yes Global Resource Used : Global Clock -Global Line Name : GCLK5 +Global Line Name : GCLK9 +Enable Signal Source Name : -- + +Name : sdram_controller:sdram_|Mux13~5 +Location : LCCOMB_X20_Y7_N2 +Fan-Out : 7 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : sdram_controller:sdram_|Mux19~0 +Location : LCCOMB_X21_Y11_N2 +Fan-Out : 6 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : sdram_controller:sdram_|Mux84~1 +Location : LCCOMB_X19_Y15_N2 +Fan-Out : 16 +Usage : Output enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : sdram_controller:sdram_|r.act_row[1]~1 +Location : LCCOMB_X21_Y12_N0 +Fan-Out : 5 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : sdram_controller:sdram_|r.address[3]~17 +Location : LCCOMB_X19_Y8_N26 +Fan-Out : 6 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : sdram_controller:sdram_|r.bank[0]~9 +Location : LCCOMB_X19_Y8_N2 +Fan-Out : 2 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : sdram_controller:sdram_|r.rf_counter[3]~32 +Location : LCCOMB_X20_Y13_N26 +Fan-Out : 10 +Usage : Sync. clear +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : sdram_controller:sdram_|r.state[7] +Location : FF_X19_Y15_N21 +Fan-Out : 45 +Usage : Sync. load +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] +Location : PLL_1 +Fan-Out : 64 +Usage : Clock +Global : yes +Global Resource Used : Global Clock +Global Line Name : GCLK4 Enable Signal Source Name : -- Name : ula:ula_|always0~3 -Location : LCCOMB_X31_Y12_N20 +Location : LCCOMB_X23_Y19_N2 Fan-Out : 7 Usage : Clock enable Global : no @@ -9800,7 +11311,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|clocks:clocks_|clk_cpu -Location : FF_X25_Y33_N11 +Location : FF_X25_Y33_N5 Fan-Out : 435 Usage : Clock Global : yes @@ -9809,7 +11320,7 @@ Global Line Name : GCLK14 Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|WideAnd0 -Location : LCCOMB_X4_Y24_N8 +Location : LCCOMB_X1_Y24_N30 Fan-Out : 17 Usage : Clock enable Global : no @@ -9817,8 +11328,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : ula:ula_|i2c_loader:i2c_loader_|nbit[0]~4 -Location : LCCOMB_X1_Y24_N4 +Name : ula:ula_|i2c_loader:i2c_loader_|nbit[0]~3 +Location : LCCOMB_X2_Y23_N26 Fan-Out : 3 Usage : Clock enable Global : no @@ -9827,7 +11338,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]~3 -Location : LCCOMB_X1_Y23_N24 +Location : LCCOMB_X1_Y23_N20 Fan-Out : 2 Usage : Clock enable Global : no @@ -9836,8 +11347,8 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Location : FF_X1_Y23_N5 -Fan-Out : 23 +Location : FF_X2_Y24_N9 +Fan-Out : 22 Usage : Sync. load Global : no Global Resource Used : -- @@ -9845,7 +11356,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]~8 -Location : LCCOMB_X1_Y24_N10 +Location : LCCOMB_X2_Y24_N0 Fan-Out : 2 Usage : Clock enable Global : no @@ -9853,8 +11364,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]~11 -Location : LCCOMB_X2_Y24_N24 +Name : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]~12 +Location : LCCOMB_X2_Y24_N14 Fan-Out : 6 Usage : Clock enable Global : no @@ -9863,7 +11374,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|state.Start -Location : FF_X1_Y24_N31 +Location : FF_X2_Y24_N31 Fan-Out : 20 Usage : Sync. clear, Sync. load Global : no @@ -9872,7 +11383,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]~18 -Location : LCCOMB_X2_Y23_N8 +Location : LCCOMB_X3_Y23_N2 Fan-Out : 5 Usage : Clock enable Global : no @@ -9881,7 +11392,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2s_intf:i2s_intf_|Equal0~2 -Location : LCCOMB_X29_Y23_N30 +Location : LCCOMB_X20_Y31_N2 Fan-Out : 37 Usage : Sync. load Global : no @@ -9890,7 +11401,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]~15 -Location : LCCOMB_X31_Y22_N28 +Location : LCCOMB_X24_Y32_N28 Fan-Out : 5 Usage : Clock enable Global : no @@ -9898,8 +11409,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]~2 -Location : LCCOMB_X31_Y22_N30 +Name : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]~2 +Location : LCCOMB_X24_Y32_N10 Fan-Out : 17 Usage : Clock enable Global : no @@ -9935,7 +11446,7 @@ Global Line Name : GCLK19 Enable Signal Source Name : -- Name : ula:ula_|ps2_keyboard:ps2_keyboard_|clk_edge -Location : FF_X20_Y26_N5 +Location : FF_X17_Y27_N17 Fan-Out : 6 Usage : Clock enable Global : no @@ -9944,8 +11455,8 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|ps2_keyboard:ps2_keyboard_|scan_code_ready -Location : FF_X26_Y21_N9 -Fan-Out : 7 +Location : FF_X18_Y12_N25 +Fan-Out : 8 Usage : Clock enable Global : no Global Resource Used : -- @@ -9953,7 +11464,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[0]~0 -Location : LCCOMB_X26_Y21_N6 +Location : LCCOMB_X18_Y12_N6 Fan-Out : 9 Usage : Clock enable Global : no @@ -9962,7 +11473,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|video:video_|Decoder0~0 -Location : LCCOMB_X34_Y31_N12 +Location : LCCOMB_X30_Y29_N10 Fan-Out : 16 Usage : Clock enable Global : no @@ -9971,7 +11482,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|video:video_|Decoder0~1 -Location : LCCOMB_X34_Y31_N10 +Location : LCCOMB_X30_Y29_N20 Fan-Out : 8 Usage : Clock enable Global : no @@ -9980,7 +11491,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|video:video_|Decoder0~2 -Location : LCCOMB_X34_Y31_N8 +Location : LCCOMB_X30_Y29_N14 Fan-Out : 8 Usage : Clock enable Global : no @@ -9989,7 +11500,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|video:video_|Equal3~1 -Location : LCCOMB_X37_Y33_N18 +Location : LCCOMB_X32_Y30_N16 Fan-Out : 16 Usage : Clock enable Global : no @@ -9997,8 +11508,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : ula:ula_|video:video_|vram_address[9]~1 -Location : LCCOMB_X34_Y31_N14 +Name : ula:ula_|video:video_|vram_address[8]~1 +Location : LCCOMB_X30_Y29_N2 Fan-Out : 4 Usage : Clock enable Global : no @@ -10007,7 +11518,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|video:video_|vram_address~0 -Location : LCCOMB_X34_Y31_N4 +Location : LCCOMB_X30_Y29_N8 Fan-Out : 8 Usage : Clock enable Global : no @@ -10015,9 +11526,9 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : z80_top_direct_n:z80_|address_pins:address_pins_|abus[13]~20 -Location : LCCOMB_X32_Y14_N0 -Fan-Out : 45 +Name : z80_top_direct_n:z80_|address_pins:address_pins_|abus[13]~23 +Location : LCCOMB_X23_Y9_N30 +Fan-Out : 47 Usage : Clock enable Global : no Global Resource Used : -- @@ -10025,7 +11536,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|alu:alu_|alu_mux_2z:b2v_op1_latch_mux_high|ena~0 -Location : LCCOMB_X36_Y10_N2 +Location : LCCOMB_X28_Y10_N28 Fan-Out : 4 Usage : Clock enable Global : no @@ -10034,7 +11545,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op1_latch_mux_low|ena -Location : LCCOMB_X36_Y10_N12 +Location : LCCOMB_X28_Y10_N0 Fan-Out : 4 Usage : Clock enable Global : no @@ -10043,7 +11554,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op2_latch_mux_high|ena -Location : LCCOMB_X37_Y10_N16 +Location : LCCOMB_X26_Y9_N22 Fan-Out : 8 Usage : Clock enable Global : no @@ -10052,7 +11563,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|clk_delay:clk_delay_|hold_clk_iorq -Location : LCCOMB_X43_Y15_N20 +Location : LCCOMB_X39_Y14_N4 Fan-Out : 24 Usage : Clock enable Global : no @@ -10061,7 +11572,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|data_pins:data_pins_|SYNTHESIZED_WIRE_2 -Location : LCCOMB_X32_Y13_N16 +Location : LCCOMB_X28_Y12_N16 Fan-Out : 8 Usage : Clock enable Global : no @@ -10070,7 +11581,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_al_we~12 -Location : LCCOMB_X41_Y18_N4 +Location : LCCOMB_X36_Y12_N8 Fan-Out : 16 Usage : Clock enable Global : no @@ -10079,7 +11590,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low -Location : LCCOMB_X39_Y11_N30 +Location : LCCOMB_X29_Y7_N4 Fan-Out : 17 Usage : Clock enable Global : no @@ -10088,7 +11599,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux2~0 -Location : LCCOMB_X31_Y16_N0 +Location : LCCOMB_X30_Y12_N6 Fan-Out : 16 Usage : Sync. load Global : no @@ -10097,7 +11608,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~8 -Location : LCCOMB_X37_Y9_N22 +Location : LCCOMB_X29_Y10_N0 Fan-Out : 2 Usage : Clock enable Global : no @@ -10105,8 +11616,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~15 -Location : LCCOMB_X36_Y11_N20 +Name : z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~16 +Location : LCCOMB_X29_Y10_N20 Fan-Out : 2 Usage : Clock enable Global : no @@ -10115,7 +11626,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_im_we -Location : LCCOMB_X35_Y13_N16 +Location : LCCOMB_X30_Y12_N16 Fan-Out : 3 Usage : Clock enable Global : no @@ -10124,7 +11635,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~13 -Location : LCCOMB_X35_Y12_N8 +Location : LCCOMB_X37_Y9_N10 Fan-Out : 8 Usage : Clock enable Global : no @@ -10133,7 +11644,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_state_ixiy_we~2 -Location : LCCOMB_X37_Y15_N0 +Location : LCCOMB_X37_Y7_N14 Fan-Out : 2 Usage : Clock enable Global : no @@ -10142,7 +11653,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_state_tbl_we~8 -Location : LCCOMB_X41_Y17_N2 +Location : LCCOMB_X37_Y7_N16 Fan-Out : 2 Usage : Clock enable Global : no @@ -10151,16 +11662,16 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|fpga_reset -Location : FF_X25_Y33_N1 +Location : FF_X26_Y32_N9 Fan-Out : 2 Usage : Async. clear Global : yes Global Resource Used : Global Clock -Global Line Name : GCLK12 +Global Line Name : GCLK10 Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 -Location : LCCOMB_X32_Y15_N28 +Location : LCCOMB_X30_Y11_N4 Fan-Out : 2 Usage : Async. clear Global : yes @@ -10169,7 +11680,7 @@ Global Line Name : GCLK16 Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_15 -Location : LCCOMB_X38_Y18_N12 +Location : LCCOMB_X30_Y11_N24 Fan-Out : 1 Usage : Async. clear Global : no @@ -10178,7 +11689,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_9 -Location : LCCOMB_X32_Y15_N2 +Location : LCCOMB_X30_Y11_N30 Fan-Out : 1 Usage : Async. clear Global : no @@ -10187,7 +11698,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|interrupts:interrupts_|test1~3 -Location : LCCOMB_X43_Y15_N26 +Location : LCCOMB_X30_Y12_N30 Fan-Out : 2 Usage : Clock enable Global : no @@ -10196,7 +11707,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|pin_control:pin_control_|bus_ab_pin_we~3 -Location : LCCOMB_X31_Y16_N2 +Location : LCCOMB_X32_Y12_N12 Fan-Out : 16 Usage : Clock enable Global : no @@ -10205,7 +11716,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_29 -Location : LCCOMB_X28_Y11_N12 +Location : LCCOMB_X26_Y13_N2 Fan-Out : 8 Usage : Clock enable Global : no @@ -10214,7 +11725,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_31 -Location : LCCOMB_X28_Y10_N10 +Location : LCCOMB_X27_Y17_N6 Fan-Out : 8 Usage : Clock enable Global : no @@ -10223,7 +11734,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_33 -Location : LCCOMB_X28_Y14_N26 +Location : LCCOMB_X26_Y13_N28 Fan-Out : 8 Usage : Clock enable Global : no @@ -10232,7 +11743,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_35 -Location : LCCOMB_X28_Y14_N8 +Location : LCCOMB_X29_Y14_N22 Fan-Out : 8 Usage : Clock enable Global : no @@ -10241,7 +11752,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_37~0 -Location : LCCOMB_X29_Y15_N16 +Location : LCCOMB_X28_Y14_N18 Fan-Out : 8 Usage : Clock enable Global : no @@ -10250,7 +11761,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_39~0 -Location : LCCOMB_X30_Y12_N8 +Location : LCCOMB_X30_Y13_N6 Fan-Out : 8 Usage : Clock enable Global : no @@ -10259,7 +11770,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_41~0 -Location : LCCOMB_X29_Y15_N6 +Location : LCCOMB_X28_Y14_N12 Fan-Out : 8 Usage : Clock enable Global : no @@ -10268,7 +11779,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_43~0 -Location : LCCOMB_X30_Y12_N14 +Location : LCCOMB_X29_Y14_N30 Fan-Out : 8 Usage : Clock enable Global : no @@ -10277,7 +11788,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_45 -Location : LCCOMB_X26_Y13_N4 +Location : LCCOMB_X27_Y17_N22 Fan-Out : 8 Usage : Clock enable Global : no @@ -10286,7 +11797,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_47 -Location : LCCOMB_X30_Y13_N14 +Location : LCCOMB_X27_Y17_N24 Fan-Out : 8 Usage : Clock enable Global : no @@ -10295,7 +11806,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_49 -Location : LCCOMB_X26_Y13_N6 +Location : LCCOMB_X27_Y17_N8 Fan-Out : 8 Usage : Clock enable Global : no @@ -10304,7 +11815,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_51 -Location : LCCOMB_X30_Y13_N28 +Location : LCCOMB_X27_Y17_N18 Fan-Out : 8 Usage : Clock enable Global : no @@ -10313,7 +11824,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_53 -Location : LCCOMB_X26_Y13_N16 +Location : LCCOMB_X27_Y17_N26 Fan-Out : 8 Usage : Clock enable Global : no @@ -10322,7 +11833,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_55 -Location : LCCOMB_X26_Y13_N26 +Location : LCCOMB_X30_Y13_N24 Fan-Out : 8 Usage : Clock enable Global : no @@ -10331,7 +11842,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_57 -Location : LCCOMB_X26_Y13_N18 +Location : LCCOMB_X27_Y17_N12 Fan-Out : 8 Usage : Clock enable Global : no @@ -10340,69 +11851,6 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_59 -Location : LCCOMB_X26_Y13_N0 -Fan-Out : 8 -Usage : Clock enable -Global : no -Global Resource Used : -- -Global Line Name : -- -Enable Signal Source Name : -- - -Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_61 -Location : LCCOMB_X28_Y15_N16 -Fan-Out : 8 -Usage : Clock enable -Global : no -Global Resource Used : -- -Global Line Name : -- -Enable Signal Source Name : -- - -Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_63 -Location : LCCOMB_X31_Y15_N28 -Fan-Out : 8 -Usage : Clock enable -Global : no -Global Resource Used : -- -Global Line Name : -- -Enable Signal Source Name : -- - -Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_65~0 -Location : LCCOMB_X30_Y12_N4 -Fan-Out : 8 -Usage : Clock enable -Global : no -Global Resource Used : -- -Global Line Name : -- -Enable Signal Source Name : -- - -Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_67~0 -Location : LCCOMB_X30_Y12_N16 -Fan-Out : 8 -Usage : Clock enable -Global : no -Global Resource Used : -- -Global Line Name : -- -Enable Signal Source Name : -- - -Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_69 -Location : LCCOMB_X27_Y12_N12 -Fan-Out : 8 -Usage : Clock enable -Global : no -Global Resource Used : -- -Global Line Name : -- -Enable Signal Source Name : -- - -Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_71 -Location : LCCOMB_X30_Y10_N24 -Fan-Out : 8 -Usage : Clock enable -Global : no -Global Resource Used : -- -Global Line Name : -- -Enable Signal Source Name : -- - -Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_73 Location : LCCOMB_X28_Y15_N10 Fan-Out : 8 Usage : Clock enable @@ -10411,8 +11859,71 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_61 +Location : LCCOMB_X30_Y16_N0 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_63 +Location : LCCOMB_X30_Y16_N12 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_65~0 +Location : LCCOMB_X28_Y14_N0 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_67~0 +Location : LCCOMB_X28_Y14_N14 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_69 +Location : LCCOMB_X27_Y14_N26 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_71 +Location : LCCOMB_X27_Y14_N0 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_73 +Location : LCCOMB_X30_Y16_N2 +Fan-Out : 8 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_75 -Location : LCCOMB_X31_Y15_N18 +Location : LCCOMB_X30_Y16_N30 Fan-Out : 8 Usage : Clock enable Global : no @@ -10421,7 +11932,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_77~0 -Location : LCCOMB_X30_Y12_N22 +Location : LCCOMB_X28_Y14_N26 Fan-Out : 8 Usage : Clock enable Global : no @@ -10430,7 +11941,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_79~0 -Location : LCCOMB_X30_Y12_N6 +Location : LCCOMB_X29_Y15_N30 Fan-Out : 8 Usage : Clock enable Global : no @@ -10439,7 +11950,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_81 -Location : LCCOMB_X28_Y15_N4 +Location : LCCOMB_X30_Y16_N18 Fan-Out : 8 Usage : Clock enable Global : no @@ -10448,7 +11959,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_83 -Location : LCCOMB_X31_Y15_N30 +Location : LCCOMB_X30_Y16_N28 Fan-Out : 8 Usage : Clock enable Global : no @@ -10457,8 +11968,8 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 -Location : FF_X35_Y13_N11 -Fan-Out : 67 +Location : FF_X31_Y14_N1 +Fan-Out : 79 Usage : Output enable Global : no Global Resource Used : -- @@ -10466,7 +11977,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 -Location : FF_X35_Y13_N11 +Location : FF_X31_Y14_N1 Fan-Out : 72 Usage : Async. clear Global : yes @@ -10483,21 +11994,29 @@ Enable Signal Source Name : -- Name : CLOCK_50 Location : PIN_R8 Fan-Out : 34 -Fan-Out Using Intentional Clock Skew : 1 +Fan-Out Using Intentional Clock Skew : 0 Global Resource Used : Global Clock Global Line Name : GCLK15 Enable Signal Source Name : -- Name : reset -Location : LCCOMB_X52_Y14_N4 +Location : LCCOMB_X52_Y14_N12 Fan-Out : 149 Fan-Out Using Intentional Clock Skew : 0 Global Resource Used : Global Clock -Global Line Name : GCLK5 +Global Line Name : GCLK9 +Enable Signal Source Name : -- + +Name : sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] +Location : PLL_1 +Fan-Out : 64 +Fan-Out Using Intentional Clock Skew : 0 +Global Resource Used : Global Clock +Global Line Name : GCLK4 Enable Signal Source Name : -- Name : ula:ula_|clocks:clocks_|clk_cpu -Location : FF_X25_Y33_N11 +Location : FF_X25_Y33_N5 Fan-Out : 435 Fan-Out Using Intentional Clock Skew : 0 Global Resource Used : Global Clock @@ -10507,7 +12026,7 @@ Enable Signal Source Name : -- Name : ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] Location : PLL_4 Fan-Out : 110 -Fan-Out Using Intentional Clock Skew : 17 +Fan-Out Using Intentional Clock Skew : 18 Global Resource Used : Global Clock Global Line Name : GCLK18 Enable Signal Source Name : -- @@ -10523,21 +12042,21 @@ Enable Signal Source Name : -- Name : ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] Location : PLL_4 Fan-Out : 82 -Fan-Out Using Intentional Clock Skew : 33 +Fan-Out Using Intentional Clock Skew : 26 Global Resource Used : Global Clock Global Line Name : GCLK19 Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|fpga_reset -Location : FF_X25_Y33_N1 +Location : FF_X26_Y32_N9 Fan-Out : 2 Fan-Out Using Intentional Clock Skew : 0 Global Resource Used : Global Clock -Global Line Name : GCLK12 +Global Line Name : GCLK10 Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 -Location : LCCOMB_X32_Y15_N28 +Location : LCCOMB_X30_Y11_N4 Fan-Out : 2 Fan-Out Using Intentional Clock Skew : 0 Global Resource Used : Global Clock @@ -10545,7 +12064,7 @@ Global Line Name : GCLK16 Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 -Location : FF_X35_Y13_N11 +Location : FF_X31_Y14_N1 Fan-Out : 72 Fan-Out Using Intentional Clock Skew : 0 Global Resource Used : Global Clock @@ -10560,103 +12079,116 @@ Enable Signal Source Name : -- +---------------------------------------------------------------------------------------------------------------------------------+---------+ ; Name ; Fan-Out ; +---------------------------------------------------------------------------------------------------------------------------------+---------+ -; z80_top_direct_n:z80_|ir:ir_|opcode[3] ; 69 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[8]~18 ; 69 ; +; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 78 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[11]~19 ; 73 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[12]~24 ; 71 ; ; z80_top_direct_n:z80_|address_pins:address_pins_|abus[9]~17 ; 69 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M1_ff ; 68 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[10]~24 ; 68 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[12]~21 ; 68 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[11]~19 ; 68 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[3] ; 68 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[10]~20 ; 68 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[8]~18 ; 68 ; ; z80_top_direct_n:z80_|address_pins:address_pins_|abus[0]~16 ; 68 ; -; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 66 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff ; 67 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[4]~28 ; 66 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[3]~27 ; 66 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[2]~26 ; 65 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[1]~25 ; 65 ; +; sdram_controller:sdram_|r.state[4] ; 65 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M1_ff ; 65 ; ; z80_top_direct_n:z80_|address_pins:address_pins_|abus[7]~31 ; 64 ; ; z80_top_direct_n:z80_|address_pins:address_pins_|abus[6]~30 ; 64 ; ; z80_top_direct_n:z80_|address_pins:address_pins_|abus[5]~29 ; 64 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[4]~28 ; 64 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[3]~27 ; 64 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[2]~26 ; 64 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[1]~25 ; 64 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff ; 59 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T2_ff ; 59 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T2_ff ; 62 ; ; z80_top_direct_n:z80_|ir:ir_|opcode[5] ; 58 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T3_ff ; 53 ; +; sdram_controller:sdram_|r.state[8] ; 57 ; +; sdram_controller:sdram_|r.state[6] ; 55 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T3_ff ; 55 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_eval_cond~0 ; 52 ; -; z80_top_direct_n:z80_|nM1_int~2 ; 51 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[0] ; 51 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~5 ; 47 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[13]~20 ; 45 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M2_ff ; 44 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~7 ; 42 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~6 ; 41 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T4_ff ; 41 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[2] ; 39 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[3] ; 39 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[0] ; 52 ; +; z80_top_direct_n:z80_|nM1_int~2 ; 48 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[13]~23 ; 47 ; +; sdram_controller:sdram_|r.state[7] ; 45 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~5 ; 42 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~8 ; 41 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~7 ; 41 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M2_ff ; 41 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T4_ff ; 40 ; ; z80_top_direct_n:z80_|execute:execute_|ixy_d~6 ; 39 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[4] ; 39 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M3_ff ; 39 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~2 ; 39 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[2] ; 38 ; ; ula:ula_|zx_keyboard:zx_keyboard_|released ; 38 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[4] ; 38 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[3] ; 37 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal6~0 ; 37 ; ; ula:ula_|i2s_intf:i2s_intf_|Equal0~2 ; 37 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[1] ; 36 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M3_ff ; 36 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~8 ; 36 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~4 ; 36 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[0] ; 35 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[4] ; 35 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_1M1T3_3 ; 35 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[2] ; 35 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[6] ; 34 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[5] ; 33 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[1] ; 31 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~36 ; 30 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~0 ; 30 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~4 ; 30 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M4_ff ; 30 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~0 ; 29 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~6 ; 27 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal11~0 ; 25 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal55~0 ; 25 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~2 ; 25 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[2] ; 36 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[1] ; 34 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[4] ; 34 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[1] ; 34 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[6] ; 33 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[0] ; 33 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_1M1T3_3 ; 33 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M4_ff ; 33 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~14 ; 33 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[5] ; 32 ; +; z80_top_direct_n:z80_|pin_control:pin_control_|bus_db_pin_oe~16 ; 31 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~0 ; 31 ; +; sdram_controller:sdram_|r.state[5] ; 29 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~0 ; 29 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~4 ; 29 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal55~0 ; 29 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~4 ; 28 ; +; Equal2~1 ; 28 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|M5 ; 27 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~34 ; 26 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~4 ; 26 ; +; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_11 ; 25 ; ; ~GND ; 24 ; -; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_11 ; 24 ; ; z80_top_direct_n:z80_|clk_delay:clk_delay_|hold_clk_iorq ; 24 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal10~0 ; 24 ; -; ula:ula_|i2c_loader:i2c_loader_|phase[0] ; 23 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal11~0 ; 24 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~46 ; 23 ; +; sdram_controller:sdram_|r.rd_pending ; 23 ; +; sdram_controller:sdram_|r.wr_pending ; 23 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~2 ; 23 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[14]~22 ; 23 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[15]~21 ; 23 ; ; ula:ula_|i2c_loader:i2c_loader_|state.Data ; 23 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~9 ; 22 ; +; ula:ula_|i2c_loader:i2c_loader_|phase[0] ; 22 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~14 ; 22 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal9~1 ; 22 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~3 ; 22 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~35 ; 21 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~31 ; 21 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal21~1 ; 21 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|M5 ; 21 ; +; sdram_controller:sdram_|Equal7~2 ; 21 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~9 ; 21 ; ; ula:ula_|i2c_loader:i2c_loader_|state.Start ; 20 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~35 ; 20 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal47~0 ; 20 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~5 ; 20 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal21~1 ; 20 ; ; z80_top_direct_n:z80_|ir:ir_|opcode[7] ; 20 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal10~0 ; 19 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal47~0 ; 19 ; ; z80_top_direct_n:z80_|ir:ir_|opcode[6] ; 19 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[14]~23 ; 19 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~16 ; 18 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~6 ; 18 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~38 ; 18 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_we~7 ; 18 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~41 ; 18 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~44 ; 18 ; +; sdram_controller:sdram_|r.rf_pending ; 18 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~12 ; 18 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~9 ; 18 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal63~0 ; 18 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~10 ; 18 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal3~1 ; 18 ; -; Equal2~1 ; 18 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~8 ; 18 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~1 ; 18 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~17 ; 17 ; ; ula:ula_|i2c_loader:i2c_loader_|WideAnd0 ; 17 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low ; 17 ; ; ula:ula_|video:video_|vram_address[10] ; 17 ; ; ula:ula_|zx_keyboard:zx_keyboard_|extended ; 17 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~11 ; 17 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~11 ; 17 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal6~1 ; 17 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~1 ; 17 ; -; ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]~2 ; 17 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal19~0 ; 17 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal34~0 ; 17 ; +; ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]~2 ; 17 ; ; z80_top_direct_n:z80_|pin_control:pin_control_|bus_ab_pin_we~3 ; 16 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~12 ; 16 ; +; sdram_controller:sdram_|Mux84~1 ; 16 ; ; ula:ula_|video:video_|vram_address[12] ; 16 ; ; ula:ula_|video:video_|vram_address[11] ; 16 ; ; ula:ula_|video:video_|vram_address[9] ; 16 ; @@ -10672,101 +12204,103 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux2~0 ; 16 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux~2 ; 16 ; ; z80_top_direct_n:z80_|resets:resets_|clrpc~0 ; 16 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~52 ; 16 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~12 ; 16 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~53 ; 16 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal6~1 ; 16 ; ; z80_top_direct_n:z80_|decode_state:decode_state_|use_ixiy ; 16 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal32~0 ; 16 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal34~0 ; 16 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~3 ; 16 ; ; z80_top_direct_n:z80_|interrupts:interrupts_|in_nmi_ALTERA_SYNTHESIZED ; 16 ; -; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] ; 16 ; ; ula:ula_|video:video_|Decoder0~0 ; 16 ; ; ula:ula_|video:video_|Equal3~1 ; 16 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~14 ; 15 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|bank_exx ; 15 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~15 ; 15 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal41~2 ; 15 ; -; z80_top_direct_n:z80_|pin_control:pin_control_|bus_db_pin_oe~14 ; 15 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~6 ; 15 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal56~0 ; 15 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~10 ; 15 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~7 ; 15 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~6 ; 15 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal2~0 ; 15 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[15]~22 ; 15 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~4 ; 15 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal3~1 ; 15 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~5 ; 15 ; +; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] ; 15 ; ; ula:ula_|video:video_|Equal1~0 ; 15 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_sel_daa ; 14 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~15 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[7]~92 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[6]~82 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[5]~72 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[4]~62 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[3]~52 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[2]~42 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[7]~90 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[6]~80 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[5]~71 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[4]~61 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[3]~51 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[2]~41 ; 14 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[1]~32 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[6]~84 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[7]~75 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[4]~66 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[5]~57 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[3]~48 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[2]~39 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[5]~84 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[6]~75 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[7]~66 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[4]~57 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[2]~48 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[3]~39 ; 14 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[0]~30 ; 14 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[1]~21 ; 14 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[0]~22 ; 14 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T5_ff ; 14 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~5 ; 14 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~9 ; 14 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~8 ; 14 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~4 ; 14 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal19~0 ; 14 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal21~0 ; 14 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~6 ; 14 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_inst4 ; 14 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~6 ; 14 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal32~0 ; 14 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal2~0 ; 14 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] ; 14 ; ; z80_top_direct_n:z80_|decode_state:decode_state_|in_halt ; 14 ; ; ula:ula_|video:video_|vga_hc[2] ; 14 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_sel_daa ; 13 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal1~7 ; 13 ; -; ula:ula_|i2c_loader:i2c_loader_|phase[1] ; 13 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~43 ; 13 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~15 ; 13 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~5 ; 13 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal56~0 ; 13 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~9 ; 13 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~7 ; 13 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~8 ; 13 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~5 ; 13 ; -; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_inst4 ; 13 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~2 ; 13 ; +; Equal2~0 ; 13 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal21~0 ; 13 ; ; ula:ula_|video:video_|vga_hc[1] ; 13 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~14 ; 12 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[3]~21 ; 12 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[4]~19 ; 12 ; +; ula:ula_|i2c_loader:i2c_loader_|phase[1] ; 12 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_af~0 ; 12 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~43 ; 12 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal69~0 ; 12 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~17 ; 12 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal52~1 ; 12 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal40~1 ; 12 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal39~0 ; 12 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~12 ; 12 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~2 ; 12 ; -; Equal2~0 ; 12 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T5_ff ; 12 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal3~0 ; 12 ; ; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instCB ; 12 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal1~4 ; 12 ; -; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] ; 12 ; ; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] ; 12 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[15] ; 12 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[3]~21 ; 11 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[4]~19 ; 11 ; ; z80_top_direct_n:z80_|bus_control:bus_control_|db[5]~15 ; 11 ; ; z80_top_direct_n:z80_|execute:execute_|nextM~14 ; 11 ; ; ula:ula_|zx_keyboard:zx_keyboard_|shifted ; 11 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~11 ; 11 ; +; sdram_controller:sdram_|process_0~2 ; 11 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~15 ; 11 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~13 ; 11 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal39~0 ; 11 ; ; z80_top_direct_n:z80_|execute:execute_|nextM~2 ; 11 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~7 ; 11 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal20~0 ; 11 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~2 ; 11 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~5 ; 11 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal52~0 ; 11 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal3~0 ; 11 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~2 ; 11 ; ; ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] ; 11 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe ; 10 ; -; D[0]~107 ; 10 ; +; sdram_controller:sdram_|r.rf_counter[3]~32 ; 10 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_zero ; 10 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~15 ; 10 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_sel_shift~4 ; 10 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~16 ; 10 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_res_oe~2 ; 10 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe ; 10 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_sel_shift~4 ; 10 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_66_oe~2 ; 10 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4d~6 ; 10 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal8~0 ; 10 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal35~0 ; 10 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal49~0 ; 10 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~12 ; 10 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal40~1 ; 10 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal24~0 ; 10 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instIY1 ; 10 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal9~0 ; 10 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[15] ; 10 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_28 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_68 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_56 ; 9 ; @@ -10779,20 +12313,21 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_50 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_46 ; 9 ; ; ula:ula_|i2c_loader:i2c_loader_|state.Idle ; 9 ; +; ula:ula_|i2c_loader:i2c_loader_|Mux42~0 ; 9 ; ; ula:ula_|i2c_loader:i2c_loader_|state.Ack ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_zero ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~8 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~9 ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_lq ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2d~13 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~14 ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_hi~7 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2d~13 ; 9 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[0]~0 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_80 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_76~0 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~12 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~11 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_64~0 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_40~0 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_36~0 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_82 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_78~0 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_42~0 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_66~0 ; 9 ; @@ -10800,28 +12335,25 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_38~0 ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_oe~2 ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2u~7 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~12 ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_oe~1 ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_oe~0 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~15 ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe ; 9 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][0]~15 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~11 ; 9 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[7] ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_72 ; 9 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sw_4d_hi~0 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_60 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_62 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_74 ; 9 ; -; D[4]~98 ; 9 ; -; D[3]~96 ; 9 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal8~0 ; 9 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal25~0 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~14 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~7 ; 9 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_lo ; 9 ; +; sdram_controller:sdram_|r.init_counter[0] ; 9 ; +; D[4]~111 ; 9 ; +; D[3]~109 ; 9 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal49~0 ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ixy_d~8 ; 9 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal20~0 ; 9 ; -; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instIY1 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~5 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~4 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~18 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~17 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~3 ; 9 ; ; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instED ; 9 ; ; z80_top_direct_n:z80_|interrupts:interrupts_|DFFE_inst44 ; 9 ; ; ula:ula_|video:video_|vga_hc[3] ; 9 ; @@ -10836,14 +12368,12 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_71 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_31 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_35 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_59 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_55 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_59 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_47 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_51 ; 8 ; -; z80_top_direct_n:z80_|alu:alu_|db[7]~26 ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_58 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel~36 ; 8 ; -; ula:ula_|i2c_loader:i2c_loader_|Mux42~0 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_54 ; 8 ; +; D[0]~121 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_77~0 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_81 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_65~0 ; 8 ; @@ -10855,7 +12385,7 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_43~0 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_39~0 ; 8 ; ; z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op2_latch_mux_high|ena ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~14 ; 8 ; +; z80_top_direct_n:z80_|alu:alu_|db[7]~9 ; 8 ; ; ula:ula_|video:video_|vram_address~0 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_73 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_61 ; 8 ; @@ -10863,112 +12393,125 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_63 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_75 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[0]~21 ; 8 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[6]~11 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~12 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~8 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~7 ; 8 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus ; 8 ; +; D[7]~117 ; 8 ; ; z80_top_direct_n:z80_|data_pins:data_pins_|SYNTHESIZED_WIRE_2 ; 8 ; ; z80_top_direct_n:z80_|pin_control:pin_control_|bus_db_pin_re ; 8 ; ; z80_top_direct_n:z80_|bus_control:bus_control_|db[0]~6 ; 8 ; ; z80_top_direct_n:z80_|bus_control:bus_control_|db[0]~4 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_66_oe~2 ; 8 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~13 ; 8 ; -; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[1]~1 ; 8 ; -; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[0]~0 ; 8 ; ; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode252w[2]~0 ; 8 ; ; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode252w[2] ; 8 ; -; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode223w[2]~0 ; 8 ; -; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode223w[2] ; 8 ; ; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode|w_anode284w[2]~0 ; 8 ; ; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode236w[2] ; 8 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode223w[2]~0 ; 8 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode223w[2] ; 8 ; ; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode244w[2]~0 ; 8 ; ; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode244w[2] ; 8 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[7] ; 8 ; +; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[1]~1 ; 8 ; +; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[0]~0 ; 8 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][0]~11 ; 8 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|scan_code_ready ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[0]~2 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[0]~2 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~38 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~14 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~25 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[0]~29 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~20 ; 8 ; ; ula:ula_|video:video_|Decoder0~2 ; 8 ; ; ula:ula_|video:video_|Decoder0~1 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~13 ; 8 ; +; sdram_controller:sdram_|r.init_counter[1] ; 8 ; +; sdram_controller:sdram_|r.init_counter[7] ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~19 ; 8 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal48~0 ; 8 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal25~0 ; 8 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal12~1 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~9 ; 8 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|flags_cond_true ; 8 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~3 ; 8 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal37~0 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~11 ; 8 ; -; D[0]~58 ; 8 ; -; D[2]~46 ; 8 ; -; D[1]~34 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~5 ; 8 ; +; D[0]~65 ; 8 ; +; D[2]~53 ; 8 ; +; D[1]~41 ; 8 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal77~0 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~2 ; 8 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|table_xx~0 ; 8 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal41~0 ; 8 ; ; ula:ula_|video:video_|vga_hc[0] ; 8 ; ; ula:ula_|video:video_|vga_hc[6] ; 8 ; ; ula:ula_|video:video_|vga_vc[5] ; 8 ; ; ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] ; 8 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_54 ; 7 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[14] ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_58 ; 7 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal38~2 ; 7 ; ; ula:ula_|always0~3 ; 7 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_iorw~11 ; 7 ; ; ula:ula_|i2c_loader:i2c_loader_|nbyte[0] ; 7 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~7 ; 7 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_82 ; 7 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[6]~13 ; 7 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|SYNTHESIZED_WIRE_2~0 ; 7 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[3]~8 ; 7 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~8 ; 7 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[3]~3 ; 7 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[3]~2 ; 7 ; -; D[7]~102 ; 7 ; -; D[6]~101 ; 7 ; -; D[5]~99 ; 7 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1]~23 ; 7 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|scan_code_ready ; 7 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[3]~7 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~19 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel~7 ; 7 ; +; D[6]~115 ; 7 ; +; D[5]~113 ; 7 ; +; ExtRamWE~0 ; 7 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~33 ; 7 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~33 ; 7 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~5 ; 7 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_lo ; 7 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|flags_cond_true ; 7 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~1 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~6 ; 7 ; +; sdram_controller:sdram_|r.address[3]~8 ; 7 ; +; sdram_controller:sdram_|Mux13~5 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~7 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|comb~0 ; 7 ; ; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|nWR_out~0 ; 7 ; ; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|nRD_out~2 ; 7 ; -; z80_top_direct_n:z80_|decode_state:decode_state_|table_xx~0 ; 7 ; ; ula:ula_|video:video_|vga_hc[8] ; 7 ; ; ula:ula_|video:video_|vga_hc[7] ; 7 ; ; ula:ula_|video:video_|vga_vc[9] ; 7 ; ; ula:ula_|video:video_|vga_vc[1] ; 7 ; ; ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] ; 7 ; ; ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] ; 7 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[14] ; 7 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[13] ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel[0]~13 ; 6 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_lo~9 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel[0]~3 ; 6 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal61~2 ; 6 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla77M1T1_3 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~49 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~33 ; 6 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~47 ; 6 ; -; ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]~11 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_iorw~10 ; 6 ; +; ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]~12 ; 6 ; ; ula:ula_|i2c_loader:i2c_loader_|nbyte[1] ; 6 ; -; z80_top_direct_n:z80_|alu:alu_|db[7]~21 ; 6 ; -; z80_top_direct_n:z80_|alu:alu_|db[0]~19 ; 6 ; +; z80_top_direct_n:z80_|alu:alu_|db[7]~20 ; 6 ; +; z80_top_direct_n:z80_|alu:alu_|db[0]~18 ; 6 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[3] ; 6 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[1] ; 6 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[2] ; 6 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_edge ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~18 ; 6 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~6 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~8 ; 6 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_hl2~0 ; 6 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_hl~0 ; 6 ; ; z80_top_direct_n:z80_|execute:execute_|rsel3 ; 6 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[1]~20 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~27 ; 6 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[1]~19 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~34 ; 6 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf ; 6 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla82M1T1_16 ; 6 ; -; ExtRamWE~0 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~24 ; 6 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1]~19 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~9 ; 6 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_hi ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~6 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[0]~29 ; 6 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~1 ; 6 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~3 ; 6 ; +; sdram_controller:sdram_|r.address[3]~17 ; 6 ; +; sdram_controller:sdram_|Mux19~0 ; 6 ; +; sdram_controller:sdram_|Equal2~2 ; 6 ; +; sdram_controller:sdram_|r.address[3]~6 ; 6 ; ; z80_top_direct_n:z80_|execute:execute_|ixy_d~10 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~16 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_zero~4 ; 6 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal44~0 ; 6 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_39 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|comb~0 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~8 ; 6 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~1 ; 6 ; ; ula:ula_|i2s_intf:i2s_intf_|bdivider[0] ; 6 ; ; ula:ula_|video:video_|screen_en~1 ; 6 ; ; ula:ula_|video:video_|vga_hc[9] ; 6 ; @@ -10979,97 +12522,90 @@ Enable Signal Source Name : -- ; ula:ula_|video:video_|vga_vc[3] ; 6 ; ; ula:ula_|video:video_|vga_vc[2] ; 6 ; ; ula:ula_|video:video_|vga_vc[0] ; 6 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[13] ; 6 ; ; ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]~18 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla89M1T2_3 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_high ; 5 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal61~2 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[0]~27 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[3]~26 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ixy_d~16 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~13 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_iorw~10 ; 5 ; ; ula:ula_|i2c_loader:i2c_loader_|nbit[0] ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[5]~25 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[6]~23 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|cy_out~0 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[4]~17 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[5]~24 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[6]~22 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[1]~16 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_low ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[2]~15 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[1]~13 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[3]~11 ; 5 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[4]~32 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[3]~14 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[2]~12 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[4]~10 ; 5 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[4]~33 ; 5 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[0] ; 5 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_68~2 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~7 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~40 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_mask543_en~0 ; 5 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_hl~0 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~19 ; 5 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_hl2~0 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~20 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2u~5 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[0]~26 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[2]~14 ; 5 ; +; sdram_controller:sdram_|r.act_row[1]~1 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[0]~25 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[2]~13 ; 5 ; ; z80_top_direct_n:z80_|alu:alu_|op1_high[1] ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~9 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~18 ; 5 ; ; z80_top_direct_n:z80_|alu:alu_|op1_high[2] ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~23 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~19 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~4 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|op1_high[3] ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[0]~23 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[1]~17 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~30 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~27 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~15 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_high ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[1]~20 ; 5 ; ; z80_top_direct_n:z80_|alu:alu_|op1_low[1] ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|op1_low[3] ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[2]~14 ; 5 ; ; z80_top_direct_n:z80_|alu:alu_|op1_low[2] ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[3]~1 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[3]~0 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~38 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~15 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~26 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla11M1T1_11 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|nextM~11 ; 5 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[13] ; 5 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[11] ; 5 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[7] ; 5 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[1] ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~10 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~9 ; 5 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[2] ; 5 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[4] ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~7 ; 5 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[9] ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~5 ; 5 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[0] ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_ir~1 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_hi~4 ; 5 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~3 ; 5 ; ; ula:ula_|i2s_intf:i2s_intf_|bitcount[4]~15 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~18 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~16 ; 5 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal12~0 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~13 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_zero~4 ; 5 ; +; sdram_controller:sdram_|Mux24~2 ; 5 ; +; sdram_controller:sdram_|n~3 ; 5 ; +; sdram_controller:sdram_|n~2 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~8 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~14 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~11 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~0 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~15 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~8 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~7 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~5 ; 5 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal40~0 ; 5 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal29~0 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~6 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla56M3T3_6 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|fMWrite~3 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~0 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|fMWrite~0 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux~0 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|fMRead~0 ; 5 ; -; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|nIORQ_out~0 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~9 ; 5 ; -; ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]~1 ; 5 ; +; z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nIORQ~1 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|fMRead~2 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~15 ; 5 ; +; ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]~1 ; 5 ; ; ula:ula_|i2s_intf:i2s_intf_|Equal1~0 ; 5 ; ; ula:ula_|video:video_|vga_hc[5] ; 5 ; ; ula:ula_|video:video_|vga_hc[4] ; 5 ; ; ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 ; 5 ; ; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[0] ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~41 ; 4 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal62~3 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[7]~37 ; 4 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_iy~2 ; 4 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de2~6 ; 4 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de2~5 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~34 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~33 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla11M1T1_11 ; 4 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de2~4 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~40 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_hf2_we ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~8 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~14 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla57M1T4_4 ; 4 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal68~2 ; 4 ; ; ula:ula_|i2c_loader:i2c_loader_|state.Pause ; 4 ; ; ula:ula_|i2c_loader:i2c_loader_|nbit[1] ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_69~2 ; 4 ; @@ -11077,35 +12613,37 @@ Enable Signal Source Name : -- ; ula:ula_|i2c_loader:i2c_loader_|state.Stop ; 4 ; ; z80_top_direct_n:z80_|alu:alu_|alu_mux_2z:b2v_op1_latch_mux_high|ena~0 ; 4 ; ; z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op1_latch_mux_low|ena ; 4 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[3]~35 ; 4 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[2]~29 ; 4 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[1]~26 ; 4 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[6]~22 ; 4 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[7]~18 ; 4 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[5]~15 ; 4 ; -; ula:ula_|video:video_|vram_address[9]~1 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~17 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[3]~36 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[2]~30 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[1]~27 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[6]~23 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[5]~17 ; 4 ; +; ula:ula_|video:video_|vram_address[8]~1 ; 4 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_af2~0 ; 4 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[0]~12 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~5 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[0]~14 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~7 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~40 ; 4 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de~0 ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_70~2 ; 4 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de2~4 ; 4 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de2~3 ; 4 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de2~2 ; 4 ; +; sdram_controller:sdram_|Mux4~0 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~12 ; 4 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|cy_out~0 ; 4 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ; 4 ; +; z80_top_direct_n:z80_|alu:alu_|op1_high[0] ; 4 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|flags_cf ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla66npla53M1T1_15 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R ; 4 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal62~2 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~3 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~8 ; 4 ; +; z80_top_direct_n:z80_|alu:alu_|op1_high[3] ; 4 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_cf ; 4 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[3]~11 ; 4 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[2]~6 ; 4 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[2]~3 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~7 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~5 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~4 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel[0]~2 ; 4 ; +; z80_top_direct_n:z80_|alu:alu_|op1_low[3] ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~9 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~3 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~0 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~23 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel[0]~10 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~1 ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[7]~24 ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[6]~21 ; 4 ; @@ -11114,102 +12652,124 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[3]~12 ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[2]~9 ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[1]~6 ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][0]~73 ; 4 ; ; ula:ula_|zx_keyboard:zx_keyboard_|Equal0~2 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|nextM~11 ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4]~44 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~6 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[6]~24 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[7]~21 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~25 ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][1]~39 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[5]~24 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[6]~21 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[7]~18 ; 4 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[14] ; 4 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][1]~36 ; 4 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][2]~32 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[4]~18 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[5]~15 ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][2]~28 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[4]~15 ; 4 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[12] ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[3]~12 ; 4 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4]~25 ; 4 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[2]~9 ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4]~21 ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4]~20 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[2]~12 ; 4 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[3]~9 ; 4 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[10] ; 4 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4]~19 ; 4 ; ; ula:ula_|zx_keyboard:zx_keyboard_|Equal0~1 ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[0]~6 ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[1]~3 ; 4 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[8] ; 4 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[6] ; 4 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[2] ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_2|carry_borrow_out~0 ; 4 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[3] ; 4 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[4] ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[1] ; 4 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[5] ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~7 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~5 ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[0]~3 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~5 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~85 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~53 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~34 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~31 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~43 ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[0] ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~24 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~21 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~20 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~17 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~5 ; 4 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_pc ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~1 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~34 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo~20 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~8 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_ixy_dT5_7 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~0 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|fMRead~3 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[0]~11 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~4 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~28 ; 4 ; +; sdram_controller:sdram_|Mux23~0 ; 4 ; +; sdram_controller:sdram_|process_0~3 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~14 ; 4 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~2 ; 4 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal50~0 ; 4 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal12~0 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla42M3T3_6 ; 4 ; ; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instNonRep ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~0 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~4 ; 4 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal2~1 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~4 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~8 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~2 ; 4 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|dout[6] ; 4 ; +; D[5]~97 ; 4 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|dout[5] ; 4 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|dout[4] ; 4 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|dout[3] ; 4 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|dout[0] ; 4 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|dout[2] ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla56M3T3_6 ; 4 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal50~0 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~6 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~0 ; 4 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|dout[1] ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ixy_d~4 ; 4 ; +; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|iorq~0 ; 4 ; ; ula:ula_|i2s_intf:i2s_intf_|Equal1~1 ; 4 ; ; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|SYNTHESIZED_WIRE_16 ; 4 ; ; ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 ; 4 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[12] ; 4 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[10] ; 4 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[8] ; 4 ; ; ula:ula_|i2s_intf:i2s_intf_|bitcount[4] ; 4 ; +; sdram_controller:sdram_|r.address[0]~_Duplicate_1 ; 4 ; ; PS2_DAT~input ; 3 ; ; raw_loader_in~input ; 3 ; ; I2C_SDAT~input ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_use_cf2~13 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~94 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[3]~25 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~15 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~14 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~99 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~13 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal73~2 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~12 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~39 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_hf_we~5 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~18 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_im_we ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~9 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~16 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~10 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~21 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~20 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~50 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~19 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~34 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~21 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ixy_d~17 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~18 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~16 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~94 ; 3 ; +; sdram_controller:sdram_|n~5 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal68~2 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~17 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~35 ; 3 ; -; ula:ula_|i2c_loader:i2c_loader_|nbit[0]~4 ; 3 ; +; ula:ula_|i2c_loader:i2c_loader_|nbit[0]~3 ; 3 ; ; ula:ula_|i2c_loader:i2c_loader_|state~24 ; 3 ; ; ula:ula_|i2c_loader:i2c_loader_|nbit[2] ; 3 ; ; ula:ula_|i2c_loader:i2c_loader_|shiftreg~4 ; 3 ; ; ula:ula_|i2c_loader:i2c_loader_|divider[0] ; 3 ; ; ula:ula_|i2c_loader:i2c_loader_|scl_out~0 ; 3 ; ; z80_top_direct_n:z80_|interrupts:interrupts_|DFFE_instIFF2 ; 3 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_cf~0 ; 3 ; ; z80_top_direct_n:z80_|bus_control:bus_control_|db[0]~17 ; 3 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|out[6]~2 ; 3 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|bank_af ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~9 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~5 ; 3 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|bank_hl_de1 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|rsel0 ; 3 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|bank_hl_de2 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~30 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_oe~1 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~26 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~4 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~20 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~5 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~12 ; 3 ; ; ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] ; 3 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_pf ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~6 ; 3 ; @@ -11217,206 +12777,205 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0|result~0 ; 3 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1|result~0 ; 3 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|result~0 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|result~0 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~5 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_op2[3]~2 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|result~1 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|cy_out~0 ; 3 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0|cy_out~0 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ; 3 ; ; z80_top_direct_n:z80_|alu:alu_|op2_high[0] ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_op1[0]~1 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|op1_high[0] ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_hf~14 ; 3 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_0~15 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~35 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~28 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_op2[1]~1 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_op2[2]~0 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op2[3]~0 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_ixy_dT4_2 ; 3 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_sf ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_nop3pla68M3T1_20 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~10 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~20 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~6 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~13 ; 3 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf~6 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~11 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~9 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~12 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~4 ; 3 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf~12 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal62~2 ; 3 ; ; z80_top_direct_n:z80_|alu:alu_|op2_low[0] ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|op1_low[0] ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~7 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~17 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~25 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~6 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~10 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~28 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~1 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~0 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~9 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~1 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~0 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~20 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~12 ; 3 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][0]~78 ; 3 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4]~51 ; 3 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4]~47 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~10 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4]~59 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4]~48 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4]~43 ; 3 ; ; z80_top_direct_n:z80_|bus_control:bus_control_|db[2]~13 ; 3 ; ; z80_top_direct_n:z80_|bus_control:bus_control_|db[1]~11 ; 3 ; ; z80_top_direct_n:z80_|bus_control:bus_control_|db[6]~9 ; 3 ; ; z80_top_direct_n:z80_|bus_control:bus_control_|db[7]~7 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~27 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~3 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~9 ; 3 ; -; ula:ula_|zx_keyboard:zx_keyboard_|WideOr16~2 ; 3 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][1]~41 ; 3 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[15] ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~7 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|WideOr16~1 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][1]~32 ; 3 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ; 3 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[15] ; 3 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_9|carry_borrow_out~0 ; 3 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4]~24 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4]~15 ; 3 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_7|carry_borrow_out~0 ; 3 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ; 3 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_2|carry_borrow_out~0 ; 3 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ; 3 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ; 3 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|fMRead~35 ; 3 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_0|carry_borrow_out~0 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fMRead~36 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|nextM~4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~10 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~6 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~25 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|nextM~3 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~23 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|nextM~3 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~21 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~5 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla10M5T4_2 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~77 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~43 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~45 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~36 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~35 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~30 ; 3 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal11~1 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~93 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~81 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~61 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~52 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~15 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~4 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~4 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|fMRead~5 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~29 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~30 ; 3 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_lo~6 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~22 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~35 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fMRead~7 ; 3 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_lo~4 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~5 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~4 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~8 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~6 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~3 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~42 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~48 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~3 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fMRead~6 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~50 ; 3 ; +; sdram_controller:sdram_|Mux13~6 ; 3 ; +; sdram_controller:sdram_|Mux23~7 ; 3 ; +; sdram_controller:sdram_|r.init_counter[4] ; 3 ; +; sdram_controller:sdram_|r.init_counter[5] ; 3 ; +; sdram_controller:sdram_|r.init_counter[6] ; 3 ; +; sdram_controller:sdram_|r.init_counter[3] ; 3 ; +; sdram_controller:sdram_|r.init_counter[2] ; 3 ; +; sdram_controller:sdram_|r.init_counter[8] ; 3 ; +; sdram_controller:sdram_|r.init_counter[9] ; 3 ; +; sdram_controller:sdram_|r.init_counter[10] ; 3 ; +; sdram_controller:sdram_|Mux71~0 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~49 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~47 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|setM1~46 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~45 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~19 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~40 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~17 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~41 ; 3 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal4~0 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~36 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fMRead~4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~37 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~10 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~29 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~29 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~12 ; 3 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal1~5 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~30 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~10 ; 3 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal2~2 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal21~2 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal1~5 ; 3 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal79~0 ; 3 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal3~2 ; 3 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_pc~2 ; 3 ; -; z80_top_direct_n:z80_|data_pins:data_pins_|dout[6] ; 3 ; -; z80_top_direct_n:z80_|data_pins:data_pins_|dout[4] ; 3 ; -; z80_top_direct_n:z80_|data_pins:data_pins_|dout[3] ; 3 ; -; z80_top_direct_n:z80_|data_pins:data_pins_|dout[0] ; 3 ; -; z80_top_direct_n:z80_|data_pins:data_pins_|dout[2] ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~4 ; 3 ; +; z80_top_direct_n:z80_|data_pins:data_pins_|dout[7] ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~8 ; 3 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal46~0 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~6 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~24 ; 3 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal19~1 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~34 ; 3 ; -; z80_top_direct_n:z80_|data_pins:data_pins_|dout[1] ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~28 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~44 ; 3 ; +; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_iorqinta ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|fIOWrite~5 ; 3 ; ; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_mrd ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|fIORead~3 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|fIOWrite~0 ; 3 ; -; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|iorq~0 ; 3 ; ; ula:ula_|i2s_intf:i2s_intf_|LessThan0~0 ; 3 ; ; ula:ula_|i2s_intf:i2s_intf_|lrclk_r~0 ; 3 ; ; ula:ula_|video:video_|VGA_B[0]~1 ; 3 ; ; ula:ula_|video:video_|VGA_G[0]~0 ; 3 ; ; ula:ula_|video:video_|VGA_B[1]~0 ; 3 ; ; ula:ula_|video:video_|VGA_R[0]~0 ; 3 ; -; ula:ula_|video:video_|cindex[1]~0 ; 3 ; +; ula:ula_|video:video_|cindex[2]~0 ; 3 ; ; ula:ula_|video:video_|disp_enable~1 ; 3 ; ; ula:ula_|video:video_|Equal2~0 ; 3 ; ; ula:ula_|video:video_|LessThan6~0 ; 3 ; ; ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 ; 3 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[12] ; 3 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[11] ; 3 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[10] ; 3 ; +; sdram_controller:sdram_|r.address[11]~5 ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[7] ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[6] ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[5] ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[3] ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[9] ; 3 ; +; sdram_controller:sdram_|r.address[10]~_Duplicate_1 ; 3 ; +; sdram_controller:sdram_|r.address[5]~_Duplicate_1 ; 3 ; +; sdram_controller:sdram_|r.address[4]~_Duplicate_1 ; 3 ; +; CLOCK_50~input ; 2 ; ; SW[2]~input ; 2 ; ; SW[1]~input ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_state_tbl_we~8 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~52 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~47 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~92 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~36 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~51 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~97 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~96 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_66_oe ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~53 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~52 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~13 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~12 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~9 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~49 ; 2 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_0~22 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~17 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~11 ; 2 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal71~2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~21 ; 2 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal73~2 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~46 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~18 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~16 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~10 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~19 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~17 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~11 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf_we~7 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~10 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_hf_we~5 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~48 ; 2 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf~11 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][4]~130 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla12M1T1_12~2 ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][4]~127 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_state_ixiy_we~2 ; 2 ; ; z80_top_direct_n:z80_|pin_control:pin_control_|bus_db_pin_re~2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~32 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~44 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~18 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~22 ; 2 ; ; z80_top_direct_n:z80_|interrupts:interrupts_|test1~3 ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~17 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~46 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~44 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~91 ; 2 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~50 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~49 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla9M1T5_2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_pc~20 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~17 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~87 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~35 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla12M3T1_2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_pc~19 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~18 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~20 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~9 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~54 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~31 ; 2 ; +; sdram_controller:sdram_|Mux10~11 ; 2 ; +; sdram_controller:sdram_|r.bank[0]~11 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~56 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~38 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla6M1T4_4 ; 2 ; -; D[6]~111 ; 2 ; -; D[4]~109 ; 2 ; -; D[3]~108 ; 2 ; -; D[0]~106 ; 2 ; -; D[2]~105 ; 2 ; -; D[2]~104 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|fMWrite~11 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~43 ; 2 ; -; D[1]~103 ; 2 ; +; D[6]~127 ; 2 ; +; D[4]~125 ; 2 ; +; D[3]~122 ; 2 ; +; D[0]~120 ; 2 ; +; D[2]~119 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~45 ; 2 ; +; D[1]~118 ; 2 ; ; ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] ; 2 ; -; ula:ula_|i2c_loader:i2c_loader_|shiftreg~14 ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|shiftreg~15 ; 2 ; ; ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] ; 2 ; ; ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|Mux35~0 ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|nbyte[0]~3 ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]~8 ; 2 ; -; ula:ula_|i2c_loader:i2c_loader_|state.Done~1 ; 2 ; -; ula:ula_|i2c_loader:i2c_loader_|state.Done~0 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~15 ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|state.Pause~1 ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|state.Pause~0 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~16 ; 2 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|ps2_clk_in ; 2 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|Equal0~1 ; 2 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[1] ; 2 ; @@ -11431,135 +12990,95 @@ Enable Signal Source Name : -- ; ula:ula_|i2c_loader:i2c_loader_|sda_out~1 ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|scl_out~2 ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|alu_parity_out ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~9 ; 2 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf~8 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_we~3 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~10 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_we~5 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_hf_we~2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~14 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[2]~24 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~13 ; 2 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[2]~23 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~15 ; 2 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[2]~24 ; 2 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|flags_hf2 ; 2 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|out[6]~0 ; 2 ; ; z80_top_direct_n:z80_|interrupts:interrupts_|iff1 ; 2 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[8] ; 2 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|LessThan0~0 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~16 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~10 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~17 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~9 ; 2 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[6]~12 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~39 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_hi~6 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~10 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~8 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~5 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~7 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~4 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~3 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~37 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~35 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~33 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~31 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~24 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~34 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~32 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~30 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~23 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~27 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~1 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~3 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~22 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~7 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~8 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~25 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~24 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~22 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~14 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~3 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~20 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~19 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 ; 2 ; +; sdram_controller:sdram_|Equal0~2 ; 2 ; +; sdram_controller:sdram_|Mux39~1 ; 2 ; +; sdram_controller:sdram_|Mux9~9 ; 2 ; +; sdram_controller:sdram_|Mux9~8 ; 2 ; +; sdram_controller:sdram_|Mux13~7 ; 2 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|sel[1]~0 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~8 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~7 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_op1[3]~3 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_op1[2]~2 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op2[1]~2 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|op2_high[1] ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op1[0]~1 ; 2 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|alu_core_cf_in~0 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_hf~20 ; 2 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|flags_hf ; 2 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_hf ; 2 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_cf2 ; 2 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal64~0 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_ixy_dT2_2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_nf_we~1 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_op1[1]~0 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|op2_high[1] ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~17 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_nf_we~0 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~16 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_hf~18 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~13 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~12 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~8 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op2[2]~1 ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|op2_high[2] ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~26 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~24 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~22 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~8 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op1[3]~0 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~33 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~31 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~29 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~14 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~13 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_hf~12 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~10 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~9 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~10 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~4 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~11 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~10 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~8 ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|op2_high[3] ; 2 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_8:b2v_inst_shift_mux|out~2 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|op1_low[0] ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|op2_low[1] ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_bit_select:b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|op2_low[3] ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_bit_select:b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|op2_low[2] ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[3]~8 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~5 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~4 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~3 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf_we~2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~10 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~41 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~5 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~11 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~31 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~14 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla25M1T1_3 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~11 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~10 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~3 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~7 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~5 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~6 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla12M1T1_12~0 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4]~126 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4]~111 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4]~97 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][4]~95 ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|abusz[7] ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_7|d0_out ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|abusz[6] ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|address[6] ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|abusz[5] ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_4|d1_out ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|abusz[4] ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_4|d0_out ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|abusz[3] ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_2|d1_out ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_0|carry_borrow_out~0 ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|abusz[2] ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_2|d0_out ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|abusz[1] ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_0|d1_out ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|shifted~1 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][0]~67 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4]~63 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][2]~61 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|Selector13~0 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][2]~53 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][3]~48 ; 2 ; -; ula:ula_|clocks:clocks_|counter[0] ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~30 ; 2 ; +---------------------------------------------------------------------------------------------------------------------------------+---------+ @@ -11586,7 +13105,7 @@ Implementation Port B Width : 8 Implementation Bits : 131072 M9Ks : 16 MIF : ula/test_scr.hex -Location : M9K_X33_Y22_N0, M9K_X33_Y24_N0, M9K_X33_Y31_N0, M9K_X33_Y28_N0, M9K_X22_Y28_N0, M9K_X22_Y27_N0, M9K_X22_Y31_N0, M9K_X22_Y23_N0, M9K_X22_Y25_N0, M9K_X22_Y22_N0, M9K_X33_Y29_N0, M9K_X22_Y26_N0, M9K_X33_Y27_N0, M9K_X33_Y25_N0, M9K_X33_Y26_N0, M9K_X22_Y24_N0 +Location : M9K_X33_Y28_N0, M9K_X22_Y28_N0, M9K_X22_Y27_N0, M9K_X22_Y23_N0, M9K_X33_Y29_N0, M9K_X22_Y29_N0, M9K_X33_Y23_N0, M9K_X33_Y26_N0, M9K_X22_Y22_N0, M9K_X22_Y21_N0, M9K_X33_Y24_N0, M9K_X22_Y24_N0, M9K_X22_Y26_N0, M9K_X22_Y25_N0, M9K_X33_Y25_N0, M9K_X33_Y21_N0 Mixed Width RDW Mode : Don't care Port A RDW Mode : Old data Port B RDW Mode : Old data @@ -11612,7 +13131,7 @@ Implementation Port B Width : -- Implementation Bits : 262144 M9Ks : 32 MIF : led_patterns.mif -Location : M9K_X33_Y19_N0, M9K_X33_Y18_N0, M9K_X33_Y15_N0, M9K_X33_Y20_N0, M9K_X33_Y12_N0, M9K_X33_Y8_N0, M9K_X22_Y12_N0, M9K_X33_Y9_N0, M9K_X22_Y13_N0, M9K_X33_Y16_N0, M9K_X33_Y13_N0, M9K_X33_Y14_N0, M9K_X22_Y11_N0, M9K_X22_Y5_N0, M9K_X22_Y15_N0, M9K_X22_Y18_N0, M9K_X22_Y8_N0, M9K_X22_Y16_N0, M9K_X22_Y3_N0, M9K_X22_Y14_N0, M9K_X22_Y6_N0, M9K_X22_Y7_N0, M9K_X22_Y9_N0, M9K_X33_Y23_N0, M9K_X33_Y11_N0, M9K_X33_Y6_N0, M9K_X33_Y10_N0, M9K_X22_Y10_N0, M9K_X33_Y5_N0, M9K_X33_Y7_N0, M9K_X33_Y4_N0, M9K_X22_Y4_N0 +Location : M9K_X33_Y15_N0, M9K_X33_Y7_N0, M9K_X22_Y7_N0, M9K_X22_Y11_N0, M9K_X33_Y19_N0, M9K_X33_Y8_N0, M9K_X22_Y5_N0, M9K_X22_Y3_N0, M9K_X22_Y14_N0, M9K_X33_Y9_N0, M9K_X22_Y9_N0, M9K_X22_Y12_N0, M9K_X22_Y13_N0, M9K_X33_Y14_N0, M9K_X33_Y13_N0, M9K_X22_Y15_N0, M9K_X22_Y18_N0, M9K_X22_Y16_N0, M9K_X22_Y10_N0, M9K_X22_Y20_N0, M9K_X33_Y5_N0, M9K_X33_Y10_N0, M9K_X33_Y18_N0, M9K_X22_Y2_N0, M9K_X22_Y8_N0, M9K_X22_Y17_N0, M9K_X22_Y6_N0, M9K_X22_Y19_N0, M9K_X22_Y4_N0, M9K_X33_Y17_N0, M9K_X33_Y16_N0, M9K_X22_Y1_N0 Mixed Width RDW Mode : Don't care Port A RDW Mode : Old data Port B RDW Mode : Old data @@ -11638,7 +13157,7 @@ Implementation Port B Width : -- Implementation Bits : 131072 M9Ks : 16 MIF : ./rom/gw03.hex -Location : M9K_X33_Y32_N0, M9K_X33_Y21_N0, M9K_X22_Y17_N0, M9K_X33_Y17_N0, M9K_X22_Y30_N0, M9K_X22_Y20_N0, M9K_X22_Y19_N0, M9K_X22_Y21_N0, M9K_X22_Y1_N0, M9K_X33_Y3_N0, M9K_X22_Y29_N0, M9K_X33_Y2_N0, M9K_X33_Y33_N0, M9K_X33_Y1_N0, M9K_X33_Y30_N0, M9K_X22_Y2_N0 +Location : M9K_X22_Y31_N0, M9K_X33_Y2_N0, M9K_X33_Y20_N0, M9K_X33_Y32_N0, M9K_X33_Y4_N0, M9K_X33_Y11_N0, M9K_X22_Y32_N0, M9K_X33_Y12_N0, M9K_X22_Y33_N0, M9K_X33_Y30_N0, M9K_X33_Y33_N0, M9K_X33_Y6_N0, M9K_X22_Y30_N0, M9K_X33_Y22_N0, M9K_X33_Y3_N0, M9K_X33_Y27_N0 Mixed Width RDW Mode : Don't care Port A RDW Mode : Old data Port B RDW Mode : Old data @@ -11648,6 +13167,4118 @@ Fits in MLABs : No - Unknown Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. +RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; |spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Addr ; +0 ; +1 ; +2 ; +3 ; +4 ; +5 ; +6 ; +7 ; ++----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+ +;0;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ; +;8;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ; +;16;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ; +;24;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ; +;32;(11000001) (301) (193) (C1) ;(11000001) (301) (193) (C1) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000011) (3) (3) (03) ; +;40;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000011) (3) (3) (03) ; +;48;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000011) (3) (3) (03) ;(10000000) (200) (128) (80) ; +;56;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000011) (3) (3) (03) ;(10000011) (203) (131) (83) ;(10000011) (203) (131) (83) ; +;64;(11000001) (301) (193) (C1) ;(10000001) (201) (129) (81) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;72;(00000011) (3) (3) (03) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111110) (376) (254) (FE) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;80;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ; +;88;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(00000011) (3) (3) (03) ;(10000001) (201) (129) (81) ;(11000011) (303) (195) (C3) ; +;96;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000010) (2) (2) (02) ;(10000000) (200) (128) (80) ;(01000000) (100) (64) (40) ; +;104;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11111111) (377) (255) (FF) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(11111111) (377) (255) (FF) ; +;112;(11111111) (377) (255) (FF) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;120;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ; +;128;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(01000010) (102) (66) (42) ;(10000111) (207) (135) (87) ;(01111111) (177) (127) (7F) ; +;136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11111110) (376) (254) (FE) ;(11101110) (356) (238) (EE) ;(00000000) (0) (0) (00) ;(11111111) (377) (255) (FF) ;(11110000) (360) (240) (F0) ;(00000000) (0) (0) (00) ; +;144;(11110001) (361) (241) (F1) ;(11111111) (377) (255) (FF) ;(11100001) (341) (225) (E1) ;(00000000) (0) (0) (00) ;(00000011) (3) (3) (03) ;(10000001) (201) (129) (81) ;(11111110) (376) (254) (FE) ;(00001111) (17) (15) (0F) ; +;152;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ; +;160;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ;(00000001) (1) (1) (01) ;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00011110) (36) (30) (1E) ; +;168;(00000000) (0) (0) (00) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(10000000) (200) (128) (80) ;(00100100) (44) (36) (24) ;(00001111) (17) (15) (0F) ;(11111100) (374) (252) (FC) ;(00000000) (0) (0) (00) ; +;176;(00000000) (0) (0) (00) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;184;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11111111) (377) (255) (FF) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ; +;192;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ;(00000100) (4) (4) (04) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00111111) (77) (63) (3F) ; +;200;(01111100) (174) (124) (7C) ;(00000000) (0) (0) (00) ;(11110000) (360) (240) (F0) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000011) (3) (3) (03) ;(11111000) (370) (248) (F8) ; +;208;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(01100011) (143) (99) (63) ;(00001100) (14) (12) (0C) ;(00110001) (61) (49) (31) ;(10101110) (256) (174) (AE) ;(11000011) (303) (195) (C3) ;(11001111) (317) (207) (CF) ; +;216;(01100011) (143) (99) (63) ;(10011111) (237) (159) (9F) ;(11111111) (377) (255) (FF) ;(00001111) (17) (15) (0F) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ; +;224;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ;(00000100) (4) (4) (04) ;(00000000) (0) (0) (00) ;(00000111) (7) (7) (07) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(00000001) (1) (1) (01) ; +;232;(11111111) (377) (255) (FF) ;(11111000) (370) (248) (F8) ;(00000000) (0) (0) (00) ;(11000000) (300) (192) (C0) ;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000001) (1) (1) (01) ;(11111111) (377) (255) (FF) ; +;240;(00000000) (0) (0) (00) ;(11100000) (340) (224) (E0) ;(10000000) (200) (128) (80) ;(11111110) (376) (254) (FE) ;(01100100) (144) (100) (64) ;(01111001) (171) (121) (79) ;(00011100) (34) (28) (1C) ;(10000111) (207) (135) (87) ; +;248;(00011001) (31) (25) (19) ;(10011000) (230) (152) (98) ;(00110000) (60) (48) (30) ;(00001111) (17) (15) (0F) ;(10000000) (200) (128) (80) ;(00000000) (0) (0) (00) ;(11001100) (314) (204) (CC) ;(00110011) (63) (51) (33) ; +;256;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ; +;264;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ; +;272;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ; +;280;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ; +;288;(11000011) (303) (195) (C3) ;(10000110) (206) (134) (86) ;(11100000) (340) (224) (E0) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000111) (7) (7) (07) ; +;296;(01100000) (140) (96) (60) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000111) (7) (7) (07) ; +;304;(01100000) (140) (96) (60) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000111) (7) (7) (07) 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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM ; @@ -15752,4282 +21383,169 @@ RAM content values are presented in the following format: (Binary) (Octal) (Deci ;32760;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM ; -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Addr ; +0 ; +1 ; +2 ; +3 ; +4 ; +5 ; +6 ; +7 ; -+----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+ -;0;(11110011) (363) (243) (F3) ;(10101111) (257) (175) (AF) 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;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;16216;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;16224;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;16232;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;16240;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;16248;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;16256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;16264;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;16272;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;16280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;16288;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;16296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;16304;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;16312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;16320;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;16328;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;16336;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;16344;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;16352;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;16360;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;16368;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; -;16376;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; - - +------------------------------------------------+ ; Routing Usage Summary ; +-----------------------+------------------------+ ; Routing Resource Type ; Usage ; +-----------------------+------------------------+ -; Block interconnects ; 5,027 / 71,559 ( 7 % ) ; -; C16 interconnects ; 124 / 2,597 ( 5 % ) ; -; C4 interconnects ; 2,759 / 46,848 ( 6 % ) ; -; Direct links ; 421 / 71,559 ( < 1 % ) ; -; Global clocks ; 9 / 20 ( 45 % ) ; -; Local interconnects ; 1,200 / 24,624 ( 5 % ) ; -; R24 interconnects ; 107 / 2,496 ( 4 % ) ; -; R4 interconnects ; 2,921 / 62,424 ( 5 % ) ; +; Block interconnects ; 5,364 / 71,559 ( 7 % ) ; +; C16 interconnects ; 115 / 2,597 ( 4 % ) ; +; C4 interconnects ; 2,916 / 46,848 ( 6 % ) ; +; Direct links ; 467 / 71,559 ( < 1 % ) ; +; Global clocks ; 10 / 20 ( 50 % ) ; +; Local interconnects ; 1,335 / 24,624 ( 5 % ) ; +; R24 interconnects ; 123 / 2,496 ( 5 % ) ; +; R4 interconnects ; 3,116 / 62,424 ( 5 % ) ; +-----------------------+------------------------+ +-----------------------------------------------------------------------------+ ; LAB Logic Elements ; +---------------------------------------------+-------------------------------+ -; Number of Logic Elements (Average = 12.95) ; Number of LABs (Total = 185) ; +; Number of Logic Elements (Average = 12.79) ; Number of LABs (Total = 204) ; +---------------------------------------------+-------------------------------+ -; 1 ; 17 ; -; 2 ; 5 ; -; 3 ; 4 ; -; 4 ; 2 ; -; 5 ; 2 ; -; 6 ; 1 ; -; 7 ; 0 ; -; 8 ; 5 ; -; 9 ; 1 ; +; 1 ; 16 ; +; 2 ; 7 ; +; 3 ; 3 ; +; 4 ; 3 ; +; 5 ; 4 ; +; 6 ; 2 ; +; 7 ; 1 ; +; 8 ; 4 ; +; 9 ; 3 ; ; 10 ; 1 ; -; 11 ; 3 ; -; 12 ; 2 ; -; 13 ; 7 ; +; 11 ; 2 ; +; 12 ; 8 ; +; 13 ; 11 ; ; 14 ; 7 ; -; 15 ; 20 ; -; 16 ; 108 ; +; 15 ; 21 ; +; 16 ; 111 ; +---------------------------------------------+-------------------------------+ +--------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+-------------------------------+ -; LAB-wide Signals (Average = 1.12) ; Number of LABs (Total = 185) ; +; LAB-wide Signals (Average = 1.16) ; Number of LABs (Total = 204) ; +------------------------------------+-------------------------------+ -; 1 Async. clear ; 49 ; -; 1 Clock ; 94 ; -; 1 Clock enable ; 35 ; +; 1 Async. clear ; 50 ; +; 1 Clock ; 111 ; +; 1 Clock enable ; 43 ; ; 1 Sync. clear ; 1 ; -; 1 Sync. load ; 4 ; +; 1 Sync. load ; 8 ; ; 2 Async. clears ; 2 ; ; 2 Clock enables ; 19 ; -; 2 Clocks ; 3 ; +; 2 Clocks ; 2 ; +------------------------------------+-------------------------------+ +------------------------------------------------------------------------------+ ; LAB Signals Sourced ; +----------------------------------------------+-------------------------------+ -; Number of Signals Sourced (Average = 15.85) ; Number of LABs (Total = 185) ; +; Number of Signals Sourced (Average = 15.63) ; Number of LABs (Total = 204) ; +----------------------------------------------+-------------------------------+ ; 0 ; 0 ; ; 1 ; 11 ; -; 2 ; 9 ; -; 3 ; 2 ; -; 4 ; 1 ; -; 5 ; 3 ; +; 2 ; 7 ; +; 3 ; 5 ; +; 4 ; 3 ; +; 5 ; 2 ; ; 6 ; 2 ; ; 7 ; 0 ; -; 8 ; 4 ; +; 8 ; 5 ; ; 9 ; 2 ; -; 10 ; 1 ; -; 11 ; 1 ; -; 12 ; 2 ; -; 13 ; 6 ; -; 14 ; 5 ; -; 15 ; 8 ; -; 16 ; 55 ; -; 17 ; 7 ; -; 18 ; 8 ; +; 10 ; 3 ; +; 11 ; 3 ; +; 12 ; 3 ; +; 13 ; 3 ; +; 14 ; 9 ; +; 15 ; 15 ; +; 16 ; 53 ; +; 17 ; 10 ; +; 18 ; 10 ; ; 19 ; 6 ; -; 20 ; 5 ; -; 21 ; 6 ; -; 22 ; 8 ; -; 23 ; 5 ; -; 24 ; 9 ; -; 25 ; 8 ; -; 26 ; 1 ; -; 27 ; 4 ; -; 28 ; 1 ; -; 29 ; 1 ; -; 30 ; 3 ; -; 31 ; 0 ; -; 32 ; 1 ; +; 20 ; 12 ; +; 21 ; 7 ; +; 22 ; 3 ; +; 23 ; 1 ; +; 24 ; 7 ; +; 25 ; 2 ; +; 26 ; 4 ; +; 27 ; 6 ; +; 28 ; 4 ; +; 29 ; 2 ; +; 30 ; 1 ; +; 31 ; 1 ; +; 32 ; 2 ; +----------------------------------------------+-------------------------------+ +---------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+-------------------------------+ -; Number of Signals Sourced Out (Average = 8.41) ; Number of LABs (Total = 185) ; +; Number of Signals Sourced Out (Average = 8.04) ; Number of LABs (Total = 204) ; +-------------------------------------------------+-------------------------------+ ; 0 ; 0 ; -; 1 ; 24 ; -; 2 ; 8 ; -; 3 ; 3 ; -; 4 ; 6 ; -; 5 ; 7 ; -; 6 ; 9 ; -; 7 ; 15 ; -; 8 ; 19 ; -; 9 ; 13 ; -; 10 ; 18 ; -; 11 ; 10 ; -; 12 ; 20 ; -; 13 ; 10 ; -; 14 ; 4 ; -; 15 ; 9 ; -; 16 ; 6 ; +; 1 ; 22 ; +; 2 ; 10 ; +; 3 ; 7 ; +; 4 ; 8 ; +; 5 ; 11 ; +; 6 ; 13 ; +; 7 ; 14 ; +; 8 ; 23 ; +; 9 ; 18 ; +; 10 ; 21 ; +; 11 ; 16 ; +; 12 ; 8 ; +; 13 ; 7 ; +; 14 ; 10 ; +; 15 ; 5 ; +; 16 ; 8 ; ; 17 ; 2 ; ; 18 ; 1 ; -; 19 ; 0 ; -; 20 ; 1 ; +-------------------------------------------------+-------------------------------+ +------------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +----------------------------------------------+-------------------------------+ -; Number of Distinct Inputs (Average = 19.44) ; Number of LABs (Total = 185) ; +; Number of Distinct Inputs (Average = 18.75) ; Number of LABs (Total = 204) ; +----------------------------------------------+-------------------------------+ ; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 4 ; -; 3 ; 5 ; +; 1 ; 1 ; +; 2 ; 5 ; +; 3 ; 9 ; ; 4 ; 10 ; ; 5 ; 3 ; -; 6 ; 5 ; -; 7 ; 5 ; -; 8 ; 1 ; -; 9 ; 4 ; -; 10 ; 2 ; -; 11 ; 3 ; -; 12 ; 4 ; -; 13 ; 5 ; -; 14 ; 9 ; +; 6 ; 3 ; +; 7 ; 3 ; +; 8 ; 4 ; +; 9 ; 5 ; +; 10 ; 4 ; +; 11 ; 8 ; +; 12 ; 7 ; +; 13 ; 11 ; +; 14 ; 5 ; ; 15 ; 6 ; ; 16 ; 4 ; -; 17 ; 5 ; -; 18 ; 9 ; -; 19 ; 3 ; -; 20 ; 5 ; -; 21 ; 4 ; -; 22 ; 2 ; -; 23 ; 6 ; -; 24 ; 6 ; -; 25 ; 10 ; -; 26 ; 6 ; -; 27 ; 5 ; -; 28 ; 8 ; +; 17 ; 6 ; +; 18 ; 8 ; +; 19 ; 4 ; +; 20 ; 8 ; +; 21 ; 2 ; +; 22 ; 6 ; +; 23 ; 4 ; +; 24 ; 4 ; +; 25 ; 7 ; +; 26 ; 2 ; +; 27 ; 6 ; +; 28 ; 7 ; ; 29 ; 8 ; -; 30 ; 9 ; -; 31 ; 14 ; -; 32 ; 14 ; +; 30 ; 12 ; +; 31 ; 11 ; +; 32 ; 19 ; +; 33 ; 2 ; +----------------------------------------------+-------------------------------+ @@ -20324,34 +21842,34 @@ Extra Information : ; I/O Rules Matrix ; +--------------------------------------------------------------------------------+ Pin/Rules : Total Pass -IO_000001 : 75 -IO_000002 : 9 -IO_000003 : 75 +IO_000001 : 114 +IO_000002 : 29 +IO_000003 : 114 IO_000004 : 0 IO_000005 : 0 -IO_000006 : 75 -IO_000007 : 75 +IO_000006 : 114 +IO_000007 : 114 IO_000008 : 0 -IO_000009 : 75 -IO_000010 : 75 +IO_000009 : 114 +IO_000010 : 114 IO_000011 : 0 IO_000012 : 0 IO_000013 : 0 IO_000014 : 0 -IO_000015 : 41 +IO_000015 : 57 IO_000018 : 0 IO_000019 : 0 -IO_000020 : 41 +IO_000020 : 57 IO_000021 : 0 IO_000022 : 0 -IO_000023 : 2 +IO_000023 : 10 IO_000024 : 0 IO_000026 : 0 IO_000027 : 0 IO_000045 : 0 IO_000046 : 0 IO_000047 : 0 -IO_000033 : 75 +IO_000033 : 114 IO_000034 : 0 IO_000042 : 0 @@ -20389,35 +21907,35 @@ IO_000042 : 0 Pin/Rules : Total Inapplicable IO_000001 : 0 -IO_000002 : 66 +IO_000002 : 85 IO_000003 : 0 -IO_000004 : 75 -IO_000005 : 75 +IO_000004 : 114 +IO_000005 : 114 IO_000006 : 0 IO_000007 : 0 -IO_000008 : 75 +IO_000008 : 114 IO_000009 : 0 IO_000010 : 0 -IO_000011 : 75 -IO_000012 : 75 -IO_000013 : 75 -IO_000014 : 75 -IO_000015 : 34 -IO_000018 : 75 -IO_000019 : 75 -IO_000020 : 34 -IO_000021 : 75 -IO_000022 : 75 -IO_000023 : 73 -IO_000024 : 75 -IO_000026 : 75 -IO_000027 : 75 -IO_000045 : 75 -IO_000046 : 75 -IO_000047 : 75 +IO_000011 : 114 +IO_000012 : 114 +IO_000013 : 114 +IO_000014 : 114 +IO_000015 : 57 +IO_000018 : 114 +IO_000019 : 114 +IO_000020 : 57 +IO_000021 : 114 +IO_000022 : 114 +IO_000023 : 104 +IO_000024 : 114 +IO_000026 : 114 +IO_000027 : 114 +IO_000045 : 114 +IO_000046 : 114 +IO_000047 : 114 IO_000033 : 0 -IO_000034 : 75 -IO_000042 : 75 +IO_000034 : 114 +IO_000042 : 114 Pin/Rules : Total Fail IO_000001 : 0 @@ -22499,6 +24017,742 @@ IO_000033 : Pass IO_000034 : Inapplicable IO_000042 : Inapplicable +Pin/Rules : DRAM_BA[0] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_BA[1] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQM[0] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQM[1] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_RAS_N +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_CAS_N +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_CKE +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_CLK +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_WE_N +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_CS_N +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[0] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[1] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[2] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[3] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[4] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[5] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[6] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[7] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[8] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[9] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[10] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[11] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_ADDR[12] +IO_000001 : Pass +IO_000002 : Pass +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Inapplicable +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Inapplicable +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + Pin/Rules : I2C_SCLK IO_000001 : Pass IO_000002 : Pass @@ -22563,6 +24817,518 @@ IO_000033 : Pass IO_000034 : Inapplicable IO_000042 : Inapplicable +Pin/Rules : DRAM_DQ[0] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[1] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[2] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[3] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[4] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[5] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[6] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[7] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Inapplicable +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[8] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Pass +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[9] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Pass +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[10] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Pass +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[11] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Pass +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[12] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Pass +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[13] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Pass +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[14] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Pass +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + +Pin/Rules : DRAM_DQ[15] +IO_000001 : Pass +IO_000002 : Inapplicable +IO_000003 : Pass +IO_000004 : Inapplicable +IO_000005 : Inapplicable +IO_000006 : Pass +IO_000007 : Pass +IO_000008 : Inapplicable +IO_000009 : Pass +IO_000010 : Pass +IO_000011 : Inapplicable +IO_000012 : Inapplicable +IO_000013 : Inapplicable +IO_000014 : Inapplicable +IO_000015 : Pass +IO_000018 : Inapplicable +IO_000019 : Inapplicable +IO_000020 : Pass +IO_000021 : Inapplicable +IO_000022 : Inapplicable +IO_000023 : Pass +IO_000024 : Inapplicable +IO_000026 : Inapplicable +IO_000027 : Inapplicable +IO_000045 : Inapplicable +IO_000046 : Inapplicable +IO_000047 : Inapplicable +IO_000033 : Pass +IO_000034 : Inapplicable +IO_000042 : Inapplicable + Pin/Rules : SW[1] IO_000001 : Pass IO_000002 : Inapplicable @@ -22896,11 +25662,11 @@ IO_000042 : Inapplicable +--------------------------------------------------------------------------------+ Source Clock(s) : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Destination Clock(s) : CLOCK_50 -Delay Added in ns : 646.3 +Delay Added in ns : 662.4 Source Clock(s) : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Destination Clock(s) : CLOCK_50,ula_|pll_|altpll_component|auto_generated|pll1|clk[0],I/O -Delay Added in ns : 20.5 +Delay Added in ns : 29.2 +--------------------------------------------------------------------------------+ Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. @@ -22910,405 +25676,405 @@ This will disable optimization of problematic paths and expose them for further +--------------------------------------------------------------------------------+ ; Estimated Delay Added for Hold Timing Details ; +--------------------------------------------------------------------------------+ -Source Register : ula:ula_|video:video_|vram_address[8] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.927 +Source Register : ula:ula_|video:video_|vram_address[9] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Delay Added in ns : 3.698 Source Register : ula:ula_|video:video_|vram_address[12] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.927 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Delay Added in ns : 3.698 -Source Register : ula:ula_|video:video_|vram_address[9] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.925 +Source Register : ula:ula_|video:video_|vram_address[8] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Delay Added in ns : 3.695 Source Register : ula:ula_|video:video_|vram_address[11] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.925 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Delay Added in ns : 3.695 Source Register : ula:ula_|video:video_|vram_address[10] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.878 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Delay Added in ns : 3.688 Source Register : ula:ula_|video:video_|vram_address[5] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.683 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Delay Added in ns : 3.647 Source Register : ula:ula_|video:video_|vram_address[6] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.680 - -Source Register : ula:ula_|video:video_|vram_address[7] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.680 - -Source Register : ula:ula_|video:video_|vram_address[0] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.437 - -Source Register : ula:ula_|video:video_|vram_address[2] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.437 - -Source Register : ula:ula_|video:video_|vram_address[4] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.437 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Delay Added in ns : 3.646 Source Register : ula:ula_|video:video_|vram_address[1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.435 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Delay Added in ns : 3.641 Source Register : ula:ula_|video:video_|vram_address[3] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Delay Added in ns : 3.431 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Delay Added in ns : 3.641 + +Source Register : ula:ula_|video:video_|vram_address[0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Delay Added in ns : 3.638 + +Source Register : ula:ula_|video:video_|vram_address[2] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Delay Added in ns : 3.638 + +Source Register : ula:ula_|video:video_|vram_address[4] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Delay Added in ns : 3.638 + +Source Register : ula:ula_|video:video_|vram_address[7] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Delay Added in ns : 3.615 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 1.924 Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Delay Added in ns : 1.522 +Delay Added in ns : 1.919 -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Delay Added in ns : 1.458 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 1.037 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 0.918 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 0.881 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 0.865 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.761 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +Destination Register : DRAM_DQ[6] +Delay Added in ns : 0.728 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.708 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.693 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.686 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.686 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +Destination Register : DRAM_DQ[6] +Delay Added in ns : 0.639 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.633 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_intr_ff3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_iorqinta +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_m1_ff3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_mrd +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_mrd_ff3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|mwr_wr +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|SYNTHESIZED_WIRE_15 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_iorq +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_iorq_ff4 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|interrupts:interrupts_|in_nmi_ALTERA_SYNTHESIZED +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|interrupts:interrupts_|DFFE_inst44 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M3_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[1] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[5] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instCB +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T3_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instED +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M2_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[6] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[7] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[3] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[2] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[4] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T4_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T2_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.605 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.603 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Delay Added in ns : 0.592 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.577 Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Delay Added in ns : 1.233 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Delay Added in ns : 1.069 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Delay Added in ns : 1.013 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Delay Added in ns : 0.967 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Delay Added in ns : 0.882 +Delay Added in ns : 0.577 Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.847 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.827 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Delay Added in ns : 0.798 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Delay Added in ns : 0.755 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Delay Added in ns : 0.563 Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.743 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Delay Added in ns : 0.530 -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.724 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.519 -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Delay Added in ns : 0.719 +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 0.495 -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 -Delay Added in ns : 0.718 +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 0.495 -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 -Delay Added in ns : 0.681 +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 0.495 -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Delay Added in ns : 0.671 +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 0.495 -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Delay Added in ns : 0.627 +Source Register : z80_top_direct_n:z80_|data_pins:data_pins_|dout[7] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 0.495 -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 -Delay Added in ns : 0.613 +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 0.495 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[15] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 0.495 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[14] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 0.495 + +Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|in_halt +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 0.495 + +Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_inst4 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 0.495 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M4_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 0.495 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|M5 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 0.495 + +Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instIY1 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 0.495 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.481 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.479 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +Destination Register : DRAM_DQ[6] +Delay Added in ns : 0.457 Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 -Delay Added in ns : 0.597 +Delay Added in ns : 0.450 -Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Delay Added in ns : 0.592 - -Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Delay Added in ns : 0.592 - -Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Delay Added in ns : 0.592 - -Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Delay Added in ns : 0.592 - -Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[15] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Delay Added in ns : 0.592 - -Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[14] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Delay Added in ns : 0.592 - -Source Register : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Delay Added in ns : 0.592 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Delay Added in ns : 0.581 - -Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Delay Added in ns : 0.581 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 -Delay Added in ns : 0.573 - -Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.524 - -Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.524 - -Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.524 - -Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.524 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 -Delay Added in ns : 0.521 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 -Delay Added in ns : 0.518 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 -Delay Added in ns : 0.495 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Delay Added in ns : 0.490 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 -Delay Added in ns : 0.436 - -Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Delay Added in ns : 0.433 - -Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Delay Added in ns : 0.433 - -Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Delay Added in ns : 0.433 - -Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Delay Added in ns : 0.433 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Delay Added in ns : 0.448 Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 -Delay Added in ns : 0.433 +Delay Added in ns : 0.444 -Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[0][1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Delay Added in ns : 0.444 -Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[1][1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Delay Added in ns : 0.443 -Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[2][1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.414 -Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[3][1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Delay Added in ns : 0.400 -Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[4][1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.399 -Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[5][1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.380 -Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[6][1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.380 -Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.380 -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.380 -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_m1_ff3 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Delay Added in ns : 0.366 -Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[13] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Delay Added in ns : 0.366 -Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[8] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Delay Added in ns : 0.366 -Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[9] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.354 -Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[10] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Delay Added in ns : 0.350 -Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[11] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.314 -Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[12] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Delay Added in ns : 0.314 -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_intr_ff3 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.312 -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_iorqinta -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_mrd -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_mrd_ff3 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|mwr_wr -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|SYNTHESIZED_WIRE_15 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_iorq -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_iorq_ff4 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|interrupts:interrupts_|in_nmi_ALTERA_SYNTHESIZED -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|interrupts:interrupts_|DFFE_inst44 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M3_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[6] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T4_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[0] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T3_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instCB -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instED -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M2_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[2] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[7] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[5] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[4] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T2_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[3] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[0] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Delay Added in ns : 0.312 +--------------------------------------------------------------------------------+ Note: This table only shows the top 100 path(s) that have the largest delay added for hold. @@ -23322,6 +26088,9 @@ Info (119006): Selected device EP4CE22F17C6 for design "spectrum" Info (21077): Core supply voltage is 1.2V Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C +Info (15535): Implemented PLL "sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1" as Cyclone IV E PLL type + Info (15099): Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] port + Info (15099): Implementing clock multiplication of 2, clock division of 1, and phase shift of 108 degrees (3000 ps) for sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[1] port Info (15535): Implemented PLL "ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1" as Cyclone IV E PLL type Info (15099): Implementing clock multiplication of 141, clock division of 280, and phase shift of 0 degrees (0 ps) for ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] port Info (15099): Implementing clock multiplication of 47, clock division of 168, and phase shift of 0 degrees (0 ps) for ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] port @@ -23340,6 +26109,35 @@ Info (169124): Fitter converted 5 user pins into dedicated programming pins Info (169125): Pin ~ALTERA_nCEO~ is reserved at location F16 Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. +Warning (176127): The parameters of the PLL ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 and the PLL sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 do not have the same values - hence these PLLs cannot be merged + Info (176120): The values of the parameter "M" do not match for the PLL atoms sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 and PLL ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 + Info (176121): The value of the parameter "M" for the PLL atom sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 is 10 + Info (176121): The value of the parameter "M" for the PLL atom ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 is 141 + Info (176120): The values of the parameter "N" do not match for the PLL atoms sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 and PLL ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 + Info (176121): The value of the parameter "N" for the PLL atom sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 is 1 + Info (176121): The value of the parameter "N" for the PLL atom ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 is 7 + Info (176120): The values of the parameter "LOOP FILTER R" do not match for the PLL atoms sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 and PLL ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 + Info (176121): The value of the parameter "LOOP FILTER R" for the PLL atom sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 is 4000 + Info (176121): The value of the parameter "LOOP FILTER R" for the PLL atom ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 is 12000 + Info (176120): The values of the parameter "VCO POST SCALE" do not match for the PLL atoms sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 and PLL ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 + Info (176121): The value of the parameter "VCO POST SCALE" for the PLL atom sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 is 2 + Info (176121): The value of the parameter "VCO POST SCALE" for the PLL atom ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 is 1 + Info (176120): The values of the parameter "Min VCO Period" do not match for the PLL atoms sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 and PLL ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 + Info (176121): The value of the parameter "Min VCO Period" for the PLL atom sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 is 1538 + Info (176121): The value of the parameter "Min VCO Period" for the PLL atom ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 is 769 + Info (176120): The values of the parameter "Max VCO Period" do not match for the PLL atoms sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 and PLL ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 + Info (176121): The value of the parameter "Max VCO Period" for the PLL atom sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 is 3333 + Info (176121): The value of the parameter "Max VCO Period" for the PLL atom ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 is 1666 + Info (176120): The values of the parameter "Center VCO Period" do not match for the PLL atoms sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 and PLL ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 + Info (176121): The value of the parameter "Center VCO Period" for the PLL atom sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 is 1538 + Info (176121): The value of the parameter "Center VCO Period" for the PLL atom ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 is 769 + Info (176120): The values of the parameter "Min Lock Period" do not match for the PLL atoms sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 and PLL ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 + Info (176121): The value of the parameter "Min Lock Period" for the PLL atom sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 is 15380 + Info (176121): The value of the parameter "Min Lock Period" for the PLL atom ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 is 15489 + Info (176120): The values of the parameter "Max Lock Period" do not match for the PLL atoms sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 and PLL ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 + Info (176121): The value of the parameter "Max Lock Period" for the PLL atom sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1 is 33330 + Info (176121): The value of the parameter "Max Lock Period" for the PLL atom ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|pll1 is 26455 +Critical Warning (176598): PLL "sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|pll1" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_R8" Info (332104): Reading SDC File: 'spectrum.sdc' Warning (332174): Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port Warning (332049): Ignored create_clock at spectrum.sdc(12): Argument is an empty collection @@ -23348,6 +26146,8 @@ Info (332110): Deriving PLL clocks Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[0]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[0]} Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[1]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[1]} Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[2]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[2]} + Info (332110): create_generated_clock -source {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]} {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]} + Info (332110): create_generated_clock -source {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]} {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]} Warning (332174): Ignored filter at spectrum.sdc(21): ula_|clocks_|clk_cpu|regout could not be matched with a pin Warning (332049): Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection Info (332050): create_generated_clock -name clk_cpu -source [get_pins {ula_|clocks_|clk_cpu|clk}] -divide_by 4 [get_pins {ula_|clocks_|clk_cpu|regout}] @@ -23357,490 +26157,206 @@ Warning (332174): Ignored filter at spectrum.sdc(57): KEY1 could not be matched Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[0] could not be matched with a clock Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[1] could not be matched with a clock Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[2] could not be matched with a clock -Warning (332125): Found combinational loop of 511 nodes - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~9|datac" - Warning (332126): Node "z80_|alu_control_|db[0]~9|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~12|dataa" - Warning (332126): Node "z80_|alu_control_|db[0]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|dataa" - Warning (332126): Node "z80_|alu_|db[0]~19|datab" - Warning (332126): Node "z80_|alu_|db[0]~19|combout" - Warning (332126): Node "z80_|sw2_|db_up[0]~0|dataa" - Warning (332126): Node "z80_|sw2_|db_up[0]~0|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~9|dataa" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|datac" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|combout" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|datab" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~5|dataa" - Warning (332126): Node "z80_|alu_|db_high[3]~5|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~6|dataa" - Warning (332126): Node "z80_|alu_|db_high[3]~6|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~7|datac" - Warning (332126): Node "z80_|alu_|db_high[3]~7|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~8|dataa" - Warning (332126): Node "z80_|alu_|db_high[3]~8|combout" - Warning (332126): Node "z80_|alu_|db[7]~21|datab" - Warning (332126): Node "z80_|alu_|db[7]~21|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~11|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~11|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~12|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~12|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~13|datac" - Warning (332126): Node "z80_|alu_|db_high[2]~13|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~14|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~14|combout" - Warning (332126): Node "z80_|alu_|db[6]~23|datab" - Warning (332126): Node "z80_|alu_|db[6]~23|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~12|datab" - Warning (332126): Node "z80_|alu_|db_high[3]~5|datab" - Warning (332126): Node "z80_|alu_control_|db[6]~20|dataa" - Warning (332126): Node "z80_|alu_control_|db[6]~20|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~21|datad" - Warning (332126): Node "z80_|alu_control_|db[6]~21|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~22|datad" - Warning (332126): Node "z80_|alu_control_|db[6]~22|combout" - Warning (332126): Node "z80_|bus_control_|db[6]~8|datab" - Warning (332126): Node "z80_|bus_control_|db[6]~8|combout" - Warning (332126): Node "z80_|bus_control_|db[6]~9|dataa" - Warning (332126): Node "z80_|bus_control_|db[6]~9|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~21|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|datab" - Warning (332126): Node "z80_|alu_control_|db[6]~22|dataa" - Warning (332126): Node "z80_|alu_|db[6]~22|dataa" - Warning (332126): Node "z80_|alu_|db[6]~22|combout" - Warning (332126): Node "z80_|alu_|db[6]~23|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~23|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~23|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|datab" - Warning (332126): Node "z80_|alu_|db[6]~22|datab" - Warning (332126): Node "z80_|alu_|db_high[1]~17|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~17|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~18|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~18|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~19|datac" - Warning (332126): Node "z80_|alu_|db_high[1]~19|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~20|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~20|combout" - Warning (332126): Node "z80_|alu_|db[5]~25|datab" - Warning (332126): Node "z80_|alu_|db[5]~25|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~11|datab" - Warning (332126): Node "z80_|alu_|db_high[0]~23|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~23|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~24|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~24|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~25|datac" - Warning (332126): Node "z80_|alu_|db_high[0]~25|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~26|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~26|combout" - Warning (332126): Node "z80_|alu_|db[4]~17|datab" - Warning (332126): Node "z80_|alu_|db[4]~17|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~7|dataa" - Warning (332126): Node "z80_|alu_|db_low[3]~7|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~8|dataa" - Warning (332126): Node "z80_|alu_|db_low[3]~8|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~11|dataa" - Warning (332126): Node "z80_|alu_|db_low[3]~11|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~25|datac" - Warning (332126): Node "z80_|alu_|db_low[3]~25|combout" - Warning (332126): Node "z80_|alu_|db[3]~10|datab" - Warning (332126): Node "z80_|alu_|db[3]~10|combout" - Warning (332126): Node "z80_|alu_|db[3]~11|dataa" - Warning (332126): Node "z80_|alu_|db[3]~11|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~8|datab" - Warning (332126): Node "z80_|alu_|db_high[0]~23|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|combout" - Warning (332126): Node "z80_|alu_|db[3]~10|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|datab" - Warning (332126): Node "z80_|alu_|db_low[2]~2|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~2|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~3|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~3|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~24|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~24|combout" - Warning (332126): Node "z80_|alu_|db[2]~15|datab" - Warning (332126): Node "z80_|alu_|db[2]~15|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~7|datab" - Warning (332126): Node "z80_|alu_control_|db[2]~27|datac" - Warning (332126): Node "z80_|alu_control_|db[2]~27|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~29|datac" - Warning (332126): Node "z80_|alu_control_|db[2]~29|combout" - Warning (332126): Node "z80_|bus_control_|db[2]~12|datab" - Warning (332126): Node "z80_|bus_control_|db[2]~12|combout" - Warning (332126): Node "z80_|bus_control_|db[2]~13|dataa" - Warning (332126): Node "z80_|bus_control_|db[2]~13|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~28|dataa" - Warning (332126): Node "z80_|alu_control_|db[2]~28|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~29|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~2|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~2|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~28|datad" - Warning (332126): Node "z80_|alu_|db[2]~14|dataa" - Warning (332126): Node "z80_|alu_|db[2]~14|combout" - Warning (332126): Node "z80_|alu_|db[2]~15|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~37|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~37|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~38|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~38|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~7|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~7|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~8|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~8|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|datab" - Warning (332126): Node "z80_|alu_|db[2]~14|datab" - Warning (332126): Node "z80_|alu_|db_low[2]~3|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~15|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~15|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~16|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~16|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~17|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~17|combout" - Warning (332126): Node "z80_|alu_|db[1]~13|datab" - Warning (332126): Node "z80_|alu_|db[1]~13|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~21|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~21|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~22|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~22|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~23|datab" - Warning (332126): Node "z80_|alu_|db_low[0]~23|combout" - Warning (332126): Node "z80_|alu_|db[0]~18|datab" - Warning (332126): Node "z80_|alu_|db[0]~18|combout" - Warning (332126): Node "z80_|alu_|db[0]~19|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|combout" - Warning (332126): Node "z80_|alu_|db[1]~12|datab" - Warning (332126): Node "z80_|alu_|db[1]~12|combout" - Warning (332126): Node "z80_|alu_|db[1]~13|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datab" - Warning (332126): Node "z80_|alu_|db_low[2]~2|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~16|datab" - Warning (332126): Node "z80_|alu_control_|db[1]~24|datac" - Warning (332126): Node "z80_|alu_control_|db[1]~24|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~26|datac" - Warning (332126): Node "z80_|alu_control_|db[1]~26|combout" - Warning (332126): Node "z80_|bus_control_|db[1]~10|datab" - Warning (332126): Node "z80_|bus_control_|db[1]~10|combout" - Warning (332126): Node "z80_|bus_control_|db[1]~11|dataa" - Warning (332126): Node "z80_|bus_control_|db[1]~11|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~25|dataa" - Warning (332126): Node "z80_|alu_control_|db[1]~25|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~26|datad" - Warning (332126): Node "z80_|alu_|db[1]~12|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~1|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~1|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~25|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datab" - Warning (332126): Node "z80_|alu_control_|db[3]~35|datab" - Warning (332126): Node "z80_|alu_control_|db[3]~35|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~34|datac" - Warning (332126): Node "z80_|alu_control_|db[3]~34|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~35|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|datab" - Warning (332126): Node "z80_|alu_|db[3]~11|datab" - Warning (332126): Node "z80_|bus_control_|db[3]~21|datab" - Warning (332126): Node "z80_|bus_control_|db[3]~21|combout" - Warning (332126): Node "z80_|sw1_|db_down[3]~1|dataa" - Warning (332126): Node "z80_|sw1_|db_down[3]~1|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~34|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~9|datac" - Warning (332126): Node "z80_|alu_|db_high[2]~9|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~13|dataa" - Warning (332126): Node "z80_|alu_|db_high[3]~27|datab" - Warning (332126): Node "z80_|alu_|db_high[3]~27|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~7|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~21|datac" - Warning (332126): Node "z80_|alu_|db_high[0]~21|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~25|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~18|datac" - Warning (332126): Node "z80_|alu_|db_low[0]~18|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~20|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~20|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~23|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~12|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~12|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~14|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~14|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~17|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~15|datab" - Warning (332126): Node "z80_|alu_|db_high[1]~15|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~19|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~4|datac" - Warning (332126): Node "z80_|alu_|db_low[2]~4|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~6|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~6|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~24|datab" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datab" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~10|datab" - Warning (332126): Node "z80_|alu_|db_low[3]~10|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~11|datab" - Warning (332126): Node "z80_|alu_|db_high[0]~24|datab" - Warning (332126): Node "z80_|alu_|db_high[1]~17|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~16|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~16|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|datab" - Warning (332126): Node "z80_|alu_|db[4]~16|dataa" - Warning (332126): Node "z80_|alu_|db[4]~16|combout" - Warning (332126): Node "z80_|alu_|db[4]~17|dataa" - Warning (332126): Node "z80_|alu_control_|db[4]~30|dataa" - Warning (332126): Node "z80_|alu_control_|db[4]~30|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~31|datad" - Warning (332126): Node "z80_|alu_control_|db[4]~31|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~32|datad" - Warning (332126): Node "z80_|alu_control_|db[4]~32|combout" - Warning (332126): Node "z80_|bus_control_|db[4]~19|datab" +Warning (332125): Found combinational loop of 513 nodes Warning (332126): Node "z80_|bus_control_|db[4]~19|combout" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~9|datab" - Warning (332126): Node "z80_|alu_|db_high[3]~27|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~21|datab" - Warning (332126): Node "z80_|alu_|db_low[0]~18|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~12|datac" - Warning (332126): Node "z80_|alu_|db_high[1]~15|datac" - Warning (332126): Node "z80_|alu_control_|db[4]~32|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~4|dataa" - Warning (332126): Node "z80_|alu_|db[4]~16|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~33|dataa" + Warning (332126): Node "z80_|alu_control_|db[4]~33|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~53|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~53|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~60|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~60|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~30|datac" Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|combout" Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|combout" Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|datab" - Warning (332126): Node "z80_|alu_|db[5]~24|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|datab" + Warning (332126): Node "z80_|alu_control_|db[4]~31|datac" + Warning (332126): Node "z80_|alu_control_|db[4]~31|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~32|datad" + Warning (332126): Node "z80_|alu_control_|db[4]~32|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~33|datad" + Warning (332126): Node "z80_|alu_|db[4]~8|datab" + Warning (332126): Node "z80_|alu_|db[4]~8|combout" + Warning (332126): Node "z80_|alu_|db[4]~10|dataa" + Warning (332126): Node "z80_|alu_|db[4]~10|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~31|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~53|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~53|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~55|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~55|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~56|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~56|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~57|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~57|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~13|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~13|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~14|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~14|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~15|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~15|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~57|datab" + Warning (332126): Node "z80_|alu_|db[4]~8|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~16|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~16|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~17|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~17|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~18|datac" + Warning (332126): Node "z80_|alu_|db_high[1]~18|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~19|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~19|combout" + Warning (332126): Node "z80_|alu_|db[5]~24|datab" Warning (332126): Node "z80_|alu_|db[5]~24|combout" - Warning (332126): Node "z80_|alu_|db[5]~25|dataa" - Warning (332126): Node "z80_|alu_control_|db[5]~15|datab" - Warning (332126): Node "z80_|alu_control_|db[5]~15|combout" - Warning (332126): Node "z80_|bus_control_|db[5]~15|datab" - Warning (332126): Node "z80_|bus_control_|db[5]~15|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~10|datac" - Warning (332126): Node "z80_|alu_|db_high[2]~9|dataa" - Warning (332126): Node "z80_|alu_|db_high[3]~27|datac" - Warning (332126): Node "z80_|alu_|db_high[0]~21|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~18|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~12|datab" - Warning (332126): Node "z80_|alu_|db_high[1]~15|dataa" - Warning (332126): Node "z80_|sw1_|db_down[5]~0|dataa" - Warning (332126): Node "z80_|sw1_|db_down[5]~0|combout" - Warning (332126): Node "z80_|alu_control_|db[5]~14|dataa" - Warning (332126): Node "z80_|alu_control_|db[5]~14|combout" - Warning (332126): Node "z80_|alu_control_|db[5]~15|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~4|datab" + Warning (332126): Node "z80_|alu_control_|db[5]~17|datab" + Warning (332126): Node "z80_|alu_control_|db[5]~17|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~65|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~65|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~67|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~67|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~69|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~69|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|datac" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|combout" + Warning (332126): Node "z80_|alu_control_|db[5]~16|datac" + Warning (332126): Node "z80_|alu_control_|db[5]~16|combout" + Warning (332126): Node "z80_|alu_control_|db[5]~17|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|combout" Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|combout" Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|datab" - Warning (332126): Node "z80_|alu_control_|db[5]~14|datac" - Warning (332126): Node "z80_|alu_|db[5]~24|datab" - Warning (332126): Node "z80_|alu_|db_high[1]~18|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~73|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~73|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~74|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~74|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~19|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~19|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~20|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~20|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|datab" + Warning (332126): Node "z80_|alu_|db[5]~23|datab" + Warning (332126): Node "z80_|alu_|db[5]~23|combout" + Warning (332126): Node "z80_|alu_|db[5]~24|dataa" + Warning (332126): Node "z80_|bus_control_|db[5]~15|datab" + Warning (332126): Node "z80_|bus_control_|db[5]~15|combout" + Warning (332126): Node "z80_|sw1_|db_down[5]~0|dataa" + Warning (332126): Node "z80_|sw1_|db_down[5]~0|combout" + Warning (332126): Node "z80_|alu_control_|db[5]~16|dataa" + Warning (332126): Node "z80_|alu_|db_high[3]~5|dataa" + Warning (332126): Node "z80_|alu_|db_high[3]~5|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~6|datac" + Warning (332126): Node "z80_|alu_|db_high[3]~6|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~7|dataa" + Warning (332126): Node "z80_|alu_|db_high[3]~7|combout" Warning (332126): Node "z80_|alu_|db[7]~20|datab" Warning (332126): Node "z80_|alu_|db[7]~20|combout" - Warning (332126): Node "z80_|alu_|db[7]~21|dataa" + Warning (332126): Node "z80_|alu_|db_high[3]~3|datab" + Warning (332126): Node "z80_|alu_|db_high[3]~3|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~6|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~8|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~8|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~9|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~9|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~12|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~12|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~13|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~13|combout" + Warning (332126): Node "z80_|alu_|db[6]~22|datab" + Warning (332126): Node "z80_|alu_|db[6]~22|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~2|datab" + Warning (332126): Node "z80_|alu_|db_high[3]~2|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~3|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~9|datab" + Warning (332126): Node "z80_|alu_control_|db[6]~22|datab" + Warning (332126): Node "z80_|alu_control_|db[6]~22|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~23|datac" + Warning (332126): Node "z80_|alu_control_|db[6]~23|combout" + Warning (332126): Node "z80_|bus_control_|db[6]~8|datab" + Warning (332126): Node "z80_|bus_control_|db[6]~8|combout" + Warning (332126): Node "z80_|bus_control_|db[6]~9|dataa" + Warning (332126): Node "z80_|bus_control_|db[6]~9|combout" + Warning (332126): Node "z80_|sw1_|db_down[6]~1|dataa" + Warning (332126): Node "z80_|sw1_|db_down[6]~1|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~23|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~77|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~77|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~78|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~78|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~0|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~0|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~23|datab" + Warning (332126): Node "z80_|alu_|db[6]~21|dataa" + Warning (332126): Node "z80_|alu_|db[6]~21|combout" + Warning (332126): Node "z80_|alu_|db[6]~22|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~71|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~71|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~73|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~73|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~74|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~74|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~19|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~19|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~20|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~20|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~21|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~21|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|datab" + Warning (332126): Node "z80_|alu_|db[6]~21|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~16|dataa" Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|dataa" - Warning (332126): Node "z80_|alu_control_|db[7]~16|datac" - Warning (332126): Node "z80_|alu_control_|db[7]~16|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~18|datac" - Warning (332126): Node "z80_|alu_control_|db[7]~18|combout" - Warning (332126): Node "z80_|bus_control_|db[7]~5|datab" - Warning (332126): Node "z80_|bus_control_|db[7]~5|combout" - Warning (332126): Node "z80_|bus_control_|db[7]~7|dataa" - Warning (332126): Node "z80_|bus_control_|db[7]~7|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~17|dataa" - Warning (332126): Node "z80_|alu_control_|db[7]~17|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~18|datad" - Warning (332126): Node "z80_|alu_|db[7]~20|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~0|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~0|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~17|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|datab" - Warning (332126): Node "z80_|alu_|db_high[3]~6|datab" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|combout" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|datab" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~2|dataa" Warning (332126): Node "z80_|alu_|db_low[0]~21|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~21|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~22|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~22|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~27|datac" + Warning (332126): Node "z80_|alu_|db_low[0]~27|combout" + Warning (332126): Node "z80_|alu_|db[0]~17|datab" + Warning (332126): Node "z80_|alu_|db[0]~17|combout" + Warning (332126): Node "z80_|alu_|db[0]~18|dataa" + Warning (332126): Node "z80_|alu_|db[0]~18|combout" + Warning (332126): Node "z80_|sw2_|db_up[0]~0|dataa" + Warning (332126): Node "z80_|sw2_|db_up[0]~0|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~11|dataa" + Warning (332126): Node "z80_|alu_control_|db[0]~11|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~14|dataa" + Warning (332126): Node "z80_|alu_control_|db[0]~14|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~11|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datab" + Warning (332126): Node "z80_|alu_|db[0]~18|datab" + Warning (332126): Node "z80_|bus_control_|db[0]~17|datab" + Warning (332126): Node "z80_|bus_control_|db[0]~17|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~10|datab" + Warning (332126): Node "z80_|alu_control_|db[0]~10|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~11|datab" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|datac" + Warning (332126): Node "z80_|alu_|db_low[0]~22|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|datac" @@ -23849,6 +26365,7 @@ Warning (332125): Found combinational loop of 511 nodes Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|combout" + Warning (332126): Node "z80_|alu_|db[0]~17|dataa" Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|dataa" Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|combout" Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|dataa" @@ -23856,34 +26373,325 @@ Warning (332125): Found combinational loop of 511 nodes Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|dataa" Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|datab" - Warning (332126): Node "z80_|alu_|db[0]~18|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~18|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~18|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~19|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~19|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~20|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~20|combout" + Warning (332126): Node "z80_|alu_|db[1]~16|datab" + Warning (332126): Node "z80_|alu_|db[1]~16|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~21|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|combout" + Warning (332126): Node "z80_|alu_|db[1]~15|datab" + Warning (332126): Node "z80_|alu_|db[1]~15|combout" + Warning (332126): Node "z80_|alu_|db[1]~16|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~9|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~9|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~10|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~10|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~14|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~14|combout" + Warning (332126): Node "z80_|alu_|db[2]~12|datab" + Warning (332126): Node "z80_|alu_|db[2]~12|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~18|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~44|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~44|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~46|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~46|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~47|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~47|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~10|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~10|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~11|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~11|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~12|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|datab" + Warning (332126): Node "z80_|alu_|db[2]~11|datab" + Warning (332126): Node "z80_|alu_|db[2]~11|combout" + Warning (332126): Node "z80_|alu_|db[2]~12|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~4|datab" + Warning (332126): Node "z80_|alu_|db_low[3]~4|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~5|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~5|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~8|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~8|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~26|datac" + Warning (332126): Node "z80_|alu_|db_low[3]~26|combout" + Warning (332126): Node "z80_|alu_|db[3]~13|datab" + Warning (332126): Node "z80_|alu_|db[3]~13|combout" + Warning (332126): Node "z80_|alu_|db[3]~14|dataa" + Warning (332126): Node "z80_|alu_|db[3]~14|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~22|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~22|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~23|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~23|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~24|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~24|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~25|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~25|combout" + Warning (332126): Node "z80_|alu_|db[4]~10|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~35|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~35|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~37|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~37|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~38|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~38|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~39|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~39|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~7|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~7|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~8|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~8|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~9|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~9|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~39|datab" + Warning (332126): Node "z80_|alu_|db[3]~13|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~5|datab" + Warning (332126): Node "z80_|alu_control_|db[3]~36|datab" + Warning (332126): Node "z80_|alu_control_|db[3]~36|combout" + Warning (332126): Node "z80_|bus_control_|db[3]~21|datab" + Warning (332126): Node "z80_|bus_control_|db[3]~21|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~5|datac" + Warning (332126): Node "z80_|alu_|db_high[2]~11|datad" + Warning (332126): Node "z80_|alu_|db_high[2]~11|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~12|datac" + Warning (332126): Node "z80_|alu_|db_low[1]~15|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~15|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~17|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~17|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~20|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~23|datac" + Warning (332126): Node "z80_|alu_|db_low[0]~23|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~25|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~25|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~27|datad" + Warning (332126): Node "z80_|alu_|db_high[0]~20|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~20|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~24|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~14|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~14|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~18|dataa" + Warning (332126): Node "z80_|sw1_|db_down[3]~3|dataa" + Warning (332126): Node "z80_|sw1_|db_down[3]~3|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~35|dataa" + Warning (332126): Node "z80_|alu_control_|db[3]~35|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~36|dataa" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|datad" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~13|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~13|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~14|datac" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datab" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~7|datab" + Warning (332126): Node "z80_|alu_|db_low[3]~7|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~8|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~45|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~45|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~49|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~49|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|datab" + Warning (332126): Node "z80_|alu_control_|db[3]~35|datac" + Warning (332126): Node "z80_|alu_|db[3]~14|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~9|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~10|datab" + Warning (332126): Node "z80_|alu_control_|db[2]~28|datac" + Warning (332126): Node "z80_|alu_control_|db[2]~28|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~30|datac" + Warning (332126): Node "z80_|alu_control_|db[2]~30|combout" + Warning (332126): Node "z80_|bus_control_|db[2]~12|datab" + Warning (332126): Node "z80_|bus_control_|db[2]~12|combout" + Warning (332126): Node "z80_|bus_control_|db[2]~13|dataa" + Warning (332126): Node "z80_|bus_control_|db[2]~13|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~29|dataa" + Warning (332126): Node "z80_|alu_control_|db[2]~29|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~30|datad" + Warning (332126): Node "z80_|alu_|db[2]~11|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~38|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~38|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~1|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~1|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~29|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~19|datab" + Warning (332126): Node "z80_|alu_control_|db[1]~25|datac" + Warning (332126): Node "z80_|alu_control_|db[1]~25|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~26|datad" + Warning (332126): Node "z80_|alu_control_|db[1]~26|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~27|datab" + Warning (332126): Node "z80_|alu_control_|db[1]~27|combout" + Warning (332126): Node "z80_|bus_control_|db[1]~10|datab" + Warning (332126): Node "z80_|bus_control_|db[1]~10|combout" + Warning (332126): Node "z80_|bus_control_|db[1]~11|dataa" + Warning (332126): Node "z80_|bus_control_|db[1]~11|combout" + Warning (332126): Node "z80_|sw1_|db_down[1]~2|dataa" + Warning (332126): Node "z80_|sw1_|db_down[1]~2|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~27|dataa" + Warning (332126): Node "z80_|alu_|db[1]~15|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~26|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datab" + Warning (332126): Node "z80_|alu_control_|db[7]~18|datac" + Warning (332126): Node "z80_|alu_control_|db[7]~18|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~19|datad" + Warning (332126): Node "z80_|alu_control_|db[7]~19|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~20|datad" + Warning (332126): Node "z80_|alu_control_|db[7]~20|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~37|datad" + Warning (332126): Node "z80_|alu_control_|db[7]~37|combout" + Warning (332126): Node "z80_|bus_control_|db[7]~5|datab" + Warning (332126): Node "z80_|bus_control_|db[7]~5|combout" + Warning (332126): Node "z80_|bus_control_|db[7]~7|dataa" + Warning (332126): Node "z80_|bus_control_|db[7]~7|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~20|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~87|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~87|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~88|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~88|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|datab" + Warning (332126): Node "z80_|alu_control_|db[7]~19|datab" + Warning (332126): Node "z80_|alu_|db[7]~19|dataa" + Warning (332126): Node "z80_|alu_|db[7]~19|combout" + Warning (332126): Node "z80_|alu_|db[7]~20|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~62|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~62|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~64|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~64|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~65|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~65|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~66|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~66|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~16|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~16|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~17|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~17|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~18|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~18|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~66|datab" + Warning (332126): Node "z80_|alu_|db[7]~19|datab" + Warning (332126): Node "z80_|alu_|db_high[2]~11|dataa" Warning (332126): Node "z80_|alu_|db_low[1]~15|datab" - Warning (332126): Node "z80_|alu_|db_low[0]~22|datab" - Warning (332126): Node "z80_|bus_control_|db[0]~17|datab" - Warning (332126): Node "z80_|bus_control_|db[0]~17|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~8|datab" - Warning (332126): Node "z80_|alu_control_|db[0]~8|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~9|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|dataa" -Critical Warning (332081): Design contains combinational loop of 511 nodes. Estimating the delays through the loop. + Warning (332126): Node "z80_|alu_|db_low[0]~23|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~20|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~14|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~7|datac" + Warning (332126): Node "z80_|alu_|db_low[2]~13|datac" + Warning (332126): Node "z80_|alu_|db_high[2]~8|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~22|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~17|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~80|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~80|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~82|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~82|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~83|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~83|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~84|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~84|combout" + Warning (332126): Node "z80_|alu_|db[5]~23|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~22|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~22|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~23|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~23|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~24|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~24|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~84|datab" + Warning (332126): Node "z80_|alu_|db_low[3]~4|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~23|datab" + Warning (332126): Node "z80_|bus_control_|db[4]~19|datab" + Warning (332126): Node "z80_|alu_|db_high[3]~5|datab" + Warning (332126): Node "z80_|alu_|db_high[2]~11|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~15|datac" + Warning (332126): Node "z80_|alu_|db_low[0]~23|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~20|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~14|datac" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|dataa" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|dataa" +Critical Warning (332081): Design contains combinational loop of 513 nodes. Estimating the delays through the loop. Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment. Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment. Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements -Info (332111): Found 5 clocks +Info (332111): Found 7 clocks Info (332111): Period Clock Name Info (332111): ======== ============ Info (332111): 10.000 beep Info (332111): 20.000 CLOCK_50 + Info (332111): 10.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + Info (332111): 10.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] Info (332111): 39.716 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Info (332111): 71.489 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Info (332111): 41.702 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (176353): Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15 +Info (176353): Automatically promoted node sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C1 of PLL_1) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4 +Info (176353): Automatically promoted node sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[1] (placed in counter C0 of PLL_1) + Info (176355): Automatically promoted destinations to use location or clock signal External Clock Output CLKCTRL_PLL1E0 Info (176353): Automatically promoted node ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C0 of PLL_4) Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18 Info (176353): Automatically promoted node ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] (placed in counter C2 of PLL_4) @@ -23918,52 +26726,13 @@ Info (176353): Automatically promoted node z80_top_direct_n:z80_|interrupts:inte Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176233): Starting register packing Info (176235): Finished register packing - Extra Info (176218): Packed 9 registers into blocks of type I/O Output Buffer - Extra Info (176220): Created 8 register duplicates + Extra Info (176218): Packed 29 registers into blocks of type I/O Output Buffer + Extra Info (176220): Created 15 register duplicates Warning (15705): Ignored locations or region assignments to the following nodes Warning (15706): Node "ADC_CS_N" is assigned to location or region, but does not exist in design Warning (15706): Node "ADC_SADDR" is assigned to location or region, but does not exist in design Warning (15706): Node "ADC_SCLK" is assigned to location or region, but does not exist in design Warning (15706): Node "ADC_SDAT" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design Warning (15706): Node "EPCS_ASDO" is assigned to location or region, but does not exist in design Warning (15706): Node "EPCS_DATA0" is assigned to location or region, but does not exist in design Warning (15706): Node "EPCS_DCLK" is assigned to location or region, but does not exist in design @@ -24008,19 +26777,19 @@ Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:03 Info (170193): Fitter routing operations beginning Info (170089): 7e+02 ns of routing delay (approximately 1.5% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report. -Info (170195): Router estimated average interconnect usage is 4% of the available device resources - Info (170196): Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X32_Y11 to location X42_Y22 +Info (170195): Router estimated average interconnect usage is 5% of the available device resources + Info (170196): Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22 Info (170194): Fitter routing operations ending: elapsed time is 00:00:06 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped -Info (11888): Total time spent on timing analysis during the Fitter is 1.92 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 1.84 seconds. Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:03 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. -Warning (169177): 41 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. +Warning (169177): 57 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. Info (169178): Pin SW[0] uses I/O standard 3.3-V LVTTL at M1 Info (169178): Pin SW[3] uses I/O standard 3.3-V LVTTL at M15 Info (169178): Pin GPIO_1[0] uses I/O standard 3.3-V LVTTL at F13 @@ -24053,6 +26822,22 @@ Warning (169177): 41 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5- Info (169178): Pin GPIO_1[30] uses I/O standard 3.3-V LVTTL at J16 Info (169178): Pin I2C_SCLK uses I/O standard 3.3-V LVTTL at F2 Info (169178): Pin I2C_SDAT uses I/O standard 3.3-V LVTTL at F1 + Info (169178): Pin DRAM_DQ[0] uses I/O standard 3.3-V LVTTL at G2 + Info (169178): Pin DRAM_DQ[1] uses I/O standard 3.3-V LVTTL at G1 + Info (169178): Pin DRAM_DQ[2] uses I/O standard 3.3-V LVTTL at L8 + Info (169178): Pin DRAM_DQ[3] uses I/O standard 3.3-V LVTTL at K5 + Info (169178): Pin DRAM_DQ[4] uses I/O standard 3.3-V LVTTL at K2 + Info (169178): Pin DRAM_DQ[5] uses I/O standard 3.3-V LVTTL at J2 + Info (169178): Pin DRAM_DQ[6] uses I/O standard 3.3-V LVTTL at J1 + Info (169178): Pin DRAM_DQ[7] uses I/O standard 3.3-V LVTTL at R7 + Info (169178): Pin DRAM_DQ[8] uses I/O standard 3.3-V LVTTL at T4 + Info (169178): Pin DRAM_DQ[9] uses I/O standard 3.3-V LVTTL at T2 + Info (169178): Pin DRAM_DQ[10] uses I/O standard 3.3-V LVTTL at T3 + Info (169178): Pin DRAM_DQ[11] uses I/O standard 3.3-V LVTTL at R3 + Info (169178): Pin DRAM_DQ[12] uses I/O standard 3.3-V LVTTL at R5 + Info (169178): Pin DRAM_DQ[13] uses I/O standard 3.3-V LVTTL at P3 + Info (169178): Pin DRAM_DQ[14] uses I/O standard 3.3-V LVTTL at N3 + Info (169178): Pin DRAM_DQ[15] uses I/O standard 3.3-V LVTTL at K1 Info (169178): Pin SW[1] uses I/O standard 3.3-V LVTTL at T8 Info (169178): Pin SW[2] uses I/O standard 3.3-V LVTTL at B9 Info (169178): Pin raw_loader_in uses I/O standard 3.3-V LVTTL at B6 @@ -24063,11 +26848,11 @@ Warning (169177): 41 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5- Info (169178): Pin PS2_CLK uses I/O standard 3.3-V LVTTL at D6 Info (169178): Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D8 Info (144001): Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg -Info: Quartus II 32-bit Fitter was successful. 0 errors, 609 warnings - Info: Peak virtual memory: 639 megabytes - Info: Processing ended: Fri Apr 1 18:55:40 2022 +Info: Quartus II 32-bit Fitter was successful. 0 errors, 574 warnings + Info: Peak virtual memory: 641 megabytes + Info: Processing ended: Sat Apr 2 14:51:08 2022 Info: Elapsed time: 00:00:22 - Info: Total CPU time (on all processors): 00:00:21 + Info: Total CPU time (on all processors): 00:00:22 +----------------------------+ diff --git a/output_files/spectrum.fit.summary b/output_files/spectrum.fit.summary index 8b9bb67..1bed494 100644 --- a/output_files/spectrum.fit.summary +++ b/output_files/spectrum.fit.summary @@ -1,16 +1,16 @@ -Fitter Status : Successful - Fri Apr 1 18:55:39 2022 +Fitter Status : Successful - Sat Apr 2 14:51:07 2022 Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition Revision Name : spectrum Top-level Entity Name : spectrum Family : Cyclone IV E Device : EP4CE22F17C6 Timing Models : Final -Total logic elements : 2,396 / 22,320 ( 11 % ) - Total combinational functions : 2,272 / 22,320 ( 10 % ) - Dedicated logic registers : 591 / 22,320 ( 3 % ) -Total registers : 600 -Total pins : 75 / 154 ( 49 % ) +Total logic elements : 2,609 / 22,320 ( 12 % ) + Total combinational functions : 2,490 / 22,320 ( 11 % ) + Dedicated logic registers : 635 / 22,320 ( 3 % ) +Total registers : 664 +Total pins : 114 / 154 ( 74 % ) Total virtual pins : 0 Total memory bits : 524,288 / 608,256 ( 86 % ) Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % ) -Total PLLs : 1 / 4 ( 25 % ) +Total PLLs : 2 / 4 ( 50 % ) diff --git a/output_files/spectrum.flow.rpt b/output_files/spectrum.flow.rpt index da73600..d85d42d 100644 --- a/output_files/spectrum.flow.rpt +++ b/output_files/spectrum.flow.rpt @@ -1,5 +1,5 @@ Flow report for spectrum -Fri Apr 1 18:55:53 2022 +Sat Apr 2 14:51:22 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -40,22 +40,22 @@ applicable agreement for further details. +---------------------------------------------------------------------------------+ ; Flow Summary ; +------------------------------------+--------------------------------------------+ -; Flow Status ; Successful - Fri Apr 1 18:55:53 2022 ; +; Flow Status ; Successful - Sat Apr 2 14:51:22 2022 ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; ; Device ; EP4CE22F17C6 ; ; Timing Models ; Final ; -; Total logic elements ; 2,396 / 22,320 ( 11 % ) ; -; Total combinational functions ; 2,272 / 22,320 ( 10 % ) ; -; Dedicated logic registers ; 591 / 22,320 ( 3 % ) ; -; Total registers ; 600 ; -; Total pins ; 75 / 154 ( 49 % ) ; +; Total logic elements ; 2,609 / 22,320 ( 12 % ) ; +; Total combinational functions ; 2,490 / 22,320 ( 11 % ) ; +; Dedicated logic registers ; 635 / 22,320 ( 3 % ) ; +; Total registers ; 664 ; +; Total pins ; 114 / 154 ( 74 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 524,288 / 608,256 ( 86 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; -; Total PLLs ; 1 / 4 ( 25 % ) ; +; Total PLLs ; 2 / 4 ( 50 % ) ; +------------------------------------+--------------------------------------------+ @@ -64,7 +64,7 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 04/01/2022 18:55:04 ; +; Start date & time ; 04/02/2022 14:50:31 ; ; Main task ; Compilation ; ; Revision Name ; spectrum ; +-------------------+---------------------+ @@ -74,7 +74,7 @@ applicable agreement for further details. ; Flow Non-Default Global Settings ; +--------------------------------------------------------------------------------+ Assignment Name : COMPILER_SIGNATURE_ID -Value : 0.164882850457192 +Value : 0.164890023113286 Default Value : -- Entity Name : -- Section Id : -- @@ -133,6 +133,12 @@ Default Value : -- Entity Name : -- Section Id : -- +Assignment Name : IP_TOOL_NAME +Value : ALTPLL +Default Value : -- +Entity Name : -- +Section Id : -- + Assignment Name : IP_TOOL_VERSION Value : 13.1 Default Value : -- @@ -175,6 +181,12 @@ Default Value : -- Entity Name : -- Section Id : -- +Assignment Name : IP_TOOL_VERSION +Value : 13.1 +Default Value : -- +Entity Name : -- +Section Id : -- + Assignment Name : MAX_CORE_JUNCTION_TEMP Value : 85 Default Value : -- @@ -241,6 +253,18 @@ Default Value : -- Entity Name : -- Section Id : -- +Assignment Name : MISC_FILE +Value : sdram_clk_gen_bb.v +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : MISC_FILE +Value : sdram_clk_gen.ppf +Default Value : -- +Entity Name : -- +Section Id : -- + Assignment Name : NOMINAL_CORE_SUPPLY_VOLTAGE Value : 1.2V Default Value : -- @@ -278,40 +302,40 @@ Section Id : -- ; Flow Elapsed Time ; +--------------------------------------------------------------------------------+ Module Name : Analysis & Synthesis -Elapsed Time : 00:00:13 +Elapsed Time : 00:00:14 Average Processors Used : 1.0 -Peak Virtual Memory : 441 MB -Total CPU Time (on all processors) : 00:00:13 +Peak Virtual Memory : 446 MB +Total CPU Time (on all processors) : 00:00:14 Module Name : Fitter Elapsed Time : 00:00:21 Average Processors Used : 1.0 -Peak Virtual Memory : 639 MB +Peak Virtual Memory : 641 MB Total CPU Time (on all processors) : 00:00:21 Module Name : Assembler Elapsed Time : 00:00:02 Average Processors Used : 1.0 -Peak Virtual Memory : 385 MB +Peak Virtual Memory : 383 MB Total CPU Time (on all processors) : 00:00:02 Module Name : TimeQuest Timing Analyzer -Elapsed Time : 00:00:04 +Elapsed Time : 00:00:03 Average Processors Used : 1.0 -Peak Virtual Memory : 437 MB +Peak Virtual Memory : 445 MB Total CPU Time (on all processors) : 00:00:04 Module Name : EDA Netlist Writer Elapsed Time : 00:00:03 Average Processors Used : 1.0 -Peak Virtual Memory : 372 MB +Peak Virtual Memory : 371 MB Total CPU Time (on all processors) : 00:00:03 Module Name : Total Elapsed Time : 00:00:43 Average Processors Used : -- Peak Virtual Memory : -- -Total CPU Time (on all processors) : 00:00:43 +Total CPU Time (on all processors) : 00:00:44 +--------------------------------------------------------------------------------+ diff --git a/output_files/spectrum.jdi b/output_files/spectrum.jdi index 72b6f13..846186e 100644 --- a/output_files/spectrum.jdi +++ b/output_files/spectrum.jdi @@ -1,6 +1,6 @@ - + diff --git a/output_files/spectrum.map.rpt b/output_files/spectrum.map.rpt index a963b5f..102053a 100644 --- a/output_files/spectrum.map.rpt +++ b/output_files/spectrum.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for spectrum -Fri Apr 1 18:55:17 2022 +Sat Apr 2 14:50:45 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -27,24 +27,26 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 19. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component 20. Parameter Settings for User Entity Instance: ram16:ram0|altsyncram:altsyncram_component 21. Parameter Settings for User Entity Instance: ram32:ram1|altsyncram:altsyncram_component - 22. Parameter Settings for User Entity Instance: ula:ula_|pll:pll_|altpll:altpll_component - 23. Parameter Settings for User Entity Instance: ula:ula_|i2c_loader:i2c_loader_ - 24. Parameter Settings for User Entity Instance: ula:ula_|i2s_intf:i2s_intf_ - 25. altsyncram Parameter Settings by Entity Instance - 26. altpll Parameter Settings by Entity Instance - 27. Port Connectivity Checks: "z80_top_direct_n:z80_|alu:alu_" - 28. Port Connectivity Checks: "z80_top_direct_n:z80_|alu_flags:alu_flags_|alu_mux_4:b2v_inst_mux_cf2" - 29. Port Connectivity Checks: "z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_8:b2v_inst_shift_mux" - 30. Port Connectivity Checks: "z80_top_direct_n:z80_|memory_ifc:memory_ifc_" - 31. Port Connectivity Checks: "z80_top_direct_n:z80_" - 32. Port Connectivity Checks: "ula:ula_|i2s_intf:i2s_intf_" - 33. Port Connectivity Checks: "ula:ula_|i2c_loader:i2c_loader_" - 34. Port Connectivity Checks: "ula:ula_" - 35. Port Connectivity Checks: "ram16:ram0" - 36. Port Connectivity Checks: "rom0:rom" - 37. Elapsed Time Per Partition - 38. Analysis & Synthesis Messages - 39. Analysis & Synthesis Suppressed Messages + 22. Parameter Settings for User Entity Instance: sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component + 23. Parameter Settings for User Entity Instance: ula:ula_|pll:pll_|altpll:altpll_component + 24. Parameter Settings for User Entity Instance: ula:ula_|i2c_loader:i2c_loader_ + 25. Parameter Settings for User Entity Instance: ula:ula_|i2s_intf:i2s_intf_ + 26. altsyncram Parameter Settings by Entity Instance + 27. altpll Parameter Settings by Entity Instance + 28. Port Connectivity Checks: "z80_top_direct_n:z80_|alu:alu_" + 29. Port Connectivity Checks: "z80_top_direct_n:z80_|alu_flags:alu_flags_|alu_mux_4:b2v_inst_mux_cf2" + 30. Port Connectivity Checks: "z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_8:b2v_inst_shift_mux" + 31. Port Connectivity Checks: "z80_top_direct_n:z80_|memory_ifc:memory_ifc_" + 32. Port Connectivity Checks: "z80_top_direct_n:z80_" + 33. Port Connectivity Checks: "ula:ula_|i2s_intf:i2s_intf_" + 34. Port Connectivity Checks: "ula:ula_|i2c_loader:i2c_loader_" + 35. Port Connectivity Checks: "ula:ula_" + 36. Port Connectivity Checks: "sdram_controller:sdram_" + 37. Port Connectivity Checks: "ram16:ram0" + 38. Port Connectivity Checks: "rom0:rom" + 39. Elapsed Time Per Partition + 40. Analysis & Synthesis Messages + 41. Analysis & Synthesis Suppressed Messages @@ -70,20 +72,20 @@ applicable agreement for further details. +---------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+--------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Fri Apr 1 18:55:17 2022 ; +; Analysis & Synthesis Status ; Successful - Sat Apr 2 14:50:45 2022 ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; -; Total logic elements ; 2,537 ; -; Total combinational functions ; 2,269 ; -; Dedicated logic registers ; 592 ; -; Total registers ; 592 ; -; Total pins ; 75 ; +; Total logic elements ; 2,751 ; +; Total combinational functions ; 2,480 ; +; Dedicated logic registers ; 649 ; +; Total registers ; 649 ; +; Total pins ; 114 ; ; Total virtual pins ; 0 ; ; Total memory bits ; 524,288 ; ; Embedded Multiplier 9-bit elements ; 0 ; -; Total PLLs ; 1 ; +; Total PLLs ; 2 ; +------------------------------------+--------------------------------------------+ @@ -735,6 +737,18 @@ File Type : User VHDL File File Name with Absolute Path : /home/benny/work/fpga/spectrum/ula/i2s_intf.vhd Library : +File Name with User-Entered Path : sdram.vhdl +Used in Netlist : yes +File Type : User VHDL File +File Name with Absolute Path : /home/benny/work/fpga/spectrum/sdram.vhdl +Library : + +File Name with User-Entered Path : sdram_clk_gen.v +Used in Netlist : yes +File Type : User Wizard-Generated File +File Name with Absolute Path : /home/benny/work/fpga/spectrum/sdram_clk_gen.v +Library : + File Name with User-Entered Path : cpu/toplevel/globals.vh Used in Netlist : yes File Type : Auto-Found Unspecified File @@ -921,6 +935,12 @@ File Type : Megafunction File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/cycloneii_pll.inc Library : +File Name with User-Entered Path : db/sdram_clk_gen_altpll.v +Used in Netlist : yes +File Type : Auto-Generated Megafunction +File Name with Absolute Path : /home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v +Library : + File Name with User-Entered Path : db/pll_altpll.v Used in Netlist : yes File Type : Auto-Generated Megafunction @@ -935,32 +955,32 @@ Library : +---------------------------------------------+---------------------------------+ ; Resource ; Usage ; +---------------------------------------------+---------------------------------+ -; Estimated Total logic elements ; 2,537 ; +; Estimated Total logic elements ; 2,751 ; ; ; ; -; Total combinational functions ; 2269 ; +; Total combinational functions ; 2480 ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 1640 ; -; -- 3 input functions ; 385 ; -; -- <=2 input functions ; 244 ; +; -- 4 input functions ; 1776 ; +; -- 3 input functions ; 416 ; +; -- <=2 input functions ; 288 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 2216 ; -; -- arithmetic mode ; 53 ; +; -- normal mode ; 2404 ; +; -- arithmetic mode ; 76 ; ; ; ; -; Total registers ; 592 ; -; -- Dedicated logic registers ; 592 ; +; Total registers ; 649 ; +; -- Dedicated logic registers ; 649 ; ; -- I/O registers ; 0 ; ; ; ; -; I/O pins ; 75 ; +; I/O pins ; 114 ; ; Total memory bits ; 524288 ; ; Embedded Multiplier 9-bit elements ; 0 ; -; Total PLLs ; 1 ; -; -- PLLs ; 1 ; +; Total PLLs ; 2 ; +; -- PLLs ; 2 ; ; ; ; ; Maximum fan-out node ; ula:ula_|clocks:clocks_|clk_cpu ; ; Maximum fan-out ; 436 ; -; Total fan-out ; 11524 ; -; Average fan-out ; 3.74 ; +; Total fan-out ; 12502 ; +; Average fan-out ; 3.63 ; +---------------------------------------------+---------------------------------+ @@ -968,13 +988,13 @@ Library : ; Analysis & Synthesis Resource Utilization by Entity ; +--------------------------------------------------------------------------------+ Compilation Hierarchy Node : |spectrum -LC Combinationals : 2269 (98) -LC Registers : 592 (0) +LC Combinationals : 2480 (108) +LC Registers : 649 (0) Memory Bits : 524288 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 -Pins : 75 +Pins : 114 Virtual Pins : 0 Full Hierarchy Name : |spectrum Library Name : work @@ -1028,7 +1048,7 @@ Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_componen Library Name : work Compilation Hierarchy Node : |ram32:ram1| -LC Combinationals : 16 (0) +LC Combinationals : 12 (0) LC Registers : 4 (0) Memory Bits : 262144 DSP Elements : 0 @@ -1040,7 +1060,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1 Library Name : work Compilation Hierarchy Node : |altsyncram:altsyncram_component| -LC Combinationals : 16 (0) +LC Combinationals : 12 (0) LC Registers : 4 (0) Memory Bits : 262144 DSP Elements : 0 @@ -1052,7 +1072,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_componen Library Name : work Compilation Hierarchy Node : |altsyncram_g9i1:auto_generated| -LC Combinationals : 16 (0) +LC Combinationals : 12 (0) LC Registers : 4 (4) Memory Bits : 262144 DSP Elements : 0 @@ -1088,7 +1108,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_componen Library Name : work Compilation Hierarchy Node : |mux_6nb:mux2| -LC Combinationals : 8 (8) +LC Combinationals : 4 (4) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1135,8 +1155,56 @@ Virtual Pins : 0 Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated Library Name : work +Compilation Hierarchy Node : |sdram_controller:sdram_| +LC Combinationals : 217 (217) +LC Registers : 57 (57) +Memory Bits : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +Full Hierarchy Name : |spectrum|sdram_controller:sdram_ +Library Name : work + +Compilation Hierarchy Node : |sdram_clk_gen:sdram_clk_pll| +LC Combinationals : 0 (0) +LC Registers : 0 (0) +Memory Bits : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +Full Hierarchy Name : |spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll +Library Name : work + +Compilation Hierarchy Node : |altpll:altpll_component| +LC Combinationals : 0 (0) +LC Registers : 0 (0) +Memory Bits : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +Full Hierarchy Name : |spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component +Library Name : work + +Compilation Hierarchy Node : |sdram_clk_gen_altpll:auto_generated| +LC Combinationals : 0 (0) +LC Registers : 0 (0) +Memory Bits : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +Full Hierarchy Name : |spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated +Library Name : work + Compilation Hierarchy Node : |ula:ula_| -LC Combinationals : 420 (4) +LC Combinationals : 418 (4) LC Registers : 224 (7) Memory Bits : 0 DSP Elements : 0 @@ -1244,7 +1312,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|video:video_ Library Name : work Compilation Hierarchy Node : |zx_keyboard:zx_keyboard_| -LC Combinationals : 150 (150) +LC Combinationals : 148 (148) LC Registers : 43 (43) Memory Bits : 0 DSP Elements : 0 @@ -1256,7 +1324,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|zx_keyboard:zx_keyboard_ Library Name : work Compilation Hierarchy Node : |z80_top_direct_n:z80_| -LC Combinationals : 1733 (2) +LC Combinationals : 1723 (2) LC Registers : 362 (1) Memory Bits : 0 DSP Elements : 0 @@ -1268,7 +1336,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_ Library Name : work Compilation Hierarchy Node : |address_latch:address_latch_| -LC Combinationals : 48 (16) +LC Combinationals : 45 (16) LC Registers : 16 (16) Memory Bits : 0 DSP Elements : 0 @@ -1280,7 +1348,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:addre Library Name : work Compilation Hierarchy Node : |inc_dec:b2v_inst_inc_dec| -LC Combinationals : 32 (14) +LC Combinationals : 29 (12) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1292,7 +1360,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:addre Library Name : work Compilation Hierarchy Node : |inc_dec_2bit:b2v_dual_adder_0| -LC Combinationals : 4 (4) +LC Combinationals : 3 (3) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1376,7 +1444,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_pins:addres Library Name : work Compilation Hierarchy Node : |alu:alu_| -LC Combinationals : 130 (77) +LC Combinationals : 128 (75) LC Registers : 20 (20) Memory Bits : 0 DSP Elements : 0 @@ -1424,7 +1492,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b Library Name : work Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_1| -LC Combinationals : 4 (4) +LC Combinationals : 5 (5) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1436,7 +1504,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b Library Name : work Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_2| -LC Combinationals : 6 (6) +LC Combinationals : 7 (7) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1448,7 +1516,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b Library Name : work Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_3| -LC Combinationals : 5 (5) +LC Combinationals : 3 (3) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1544,7 +1612,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_control:alu_con Library Name : work Compilation Hierarchy Node : |alu_flags:alu_flags_| -LC Combinationals : 63 (63) +LC Combinationals : 61 (61) LC Registers : 10 (10) Memory Bits : 0 DSP Elements : 0 @@ -1579,6 +1647,18 @@ Virtual Pins : 0 Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|clk_delay:clk_delay_ Library Name : work +Compilation Hierarchy Node : |control_pins_n:control_pins_| +LC Combinationals : 1 (1) +LC Registers : 0 (0) +Memory Bits : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|control_pins_n:control_pins_ +Library Name : work + Compilation Hierarchy Node : |data_pins:data_pins_| LC Combinationals : 9 (9) LC Registers : 8 (8) @@ -1604,7 +1684,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_switch:sw2_ Library Name : work Compilation Hierarchy Node : |data_switch_mask:sw1_| -LC Combinationals : 2 (2) +LC Combinationals : 4 (4) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1628,7 +1708,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|decode_state:decode Library Name : work Compilation Hierarchy Node : |execute:execute_| -LC Combinationals : 933 (933) +LC Combinationals : 926 (926) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1676,7 +1756,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|memory_ifc:memory_i Library Name : work Compilation Hierarchy Node : |pin_control:pin_control_| -LC Combinationals : 19 (19) +LC Combinationals : 20 (20) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1700,7 +1780,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|pla_decode:pla_deco Library Name : work Compilation Hierarchy Node : |reg_control:reg_control_| -LC Combinationals : 29 (29) +LC Combinationals : 30 (30) LC Registers : 4 (4) Memory Bits : 0 DSP Elements : 0 @@ -1712,7 +1792,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_control:reg_con Library Name : work Compilation Hierarchy Node : |reg_file:reg_file_| -LC Combinationals : 282 (273) +LC Combinationals : 281 (270) LC Registers : 224 (0) Memory Bits : 0 DSP Elements : 0 @@ -1880,7 +1960,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_| Library Name : work Compilation Hierarchy Node : |reg_latch:b2v_latch_hl2_lo| -LC Combinationals : 1 (1) +LC Combinationals : 0 (0) LC Registers : 8 (8) Memory Bits : 0 DSP Elements : 0 @@ -1904,7 +1984,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_| Library Name : work Compilation Hierarchy Node : |reg_latch:b2v_latch_hl_lo| -LC Combinationals : 0 (0) +LC Combinationals : 1 (1) LC Registers : 8 (8) Memory Bits : 0 DSP Elements : 0 @@ -2048,7 +2128,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_| Library Name : work Compilation Hierarchy Node : |reg_latch:b2v_latch_wz_lo| -LC Combinationals : 0 (0) +LC Combinationals : 2 (2) LC Registers : 8 (8) Memory Bits : 0 DSP Elements : 0 @@ -2150,6 +2230,14 @@ License Type : N/A Entity Instance : |spectrum|rom0:rom IP Include File : /home/benny/work/fpga/spectrum/rom0.v +Vendor : Altera +IP Core Name : ALTPLL +Version : 13.1 +Release Date : N/A +License Type : N/A +Entity Instance : |spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll +IP Include File : /home/benny/work/fpga/spectrum/sdram_clk_gen.v + Vendor : Altera IP Core Name : ALTPLL Version : 13.0 @@ -2239,8 +2327,11 @@ state.Idle : 1 ; z80_top_direct_n:z80_|clk_delay:clk_delay_|SYNTHESIZED_WIRE_9 ; Stuck at GND due to stuck port data_in ; ; z80_top_direct_n:z80_|clk_delay:clk_delay_|SYNTHESIZED_WIRE_8 ; Stuck at GND due to stuck port data_in ; ; z80_top_direct_n:z80_|clk_delay:clk_delay_|hold_clk_busrq_ALTERA_SYNTHESIZED ; Stuck at GND due to stuck port data_in ; +; sdram_controller:sdram_|r.state[3] ; Stuck at GND due to stuck port data_in ; ; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_b[0] ; Stuck at GND due to stuck port data_in ; ; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_b[0] ; Stuck at GND due to stuck port data_in ; +; sdram_controller:sdram_|r.address[12] ; Merged with sdram_controller:sdram_|r.address[11] ; +; sdram_controller:sdram_|r.act_row[5..9,11,12] ; Merged with sdram_controller:sdram_|r.act_row[10] ; ; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] ; Merged with ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] ; ; ula:ula_|pcm_outr[14] ; Merged with ula:ula_|pcm_outl[14] ; ; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] ; Merged with ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0] ; @@ -2249,8 +2340,9 @@ state.Idle : 1 ; ula:ula_|i2c_loader:i2c_loader_|retries ; Stuck at GND due to stuck port data_in ; ; ula:ula_|i2c_loader:i2c_loader_|nak ; Lost fanout ; ; ula:ula_|i2c_loader:i2c_loader_|state.Done ; Lost fanout ; +; sdram_controller:sdram_|r.act_row[10] ; Stuck at GND due to stuck port data_in ; ; ula:ula_|i2s_intf:i2s_intf_|lrdivider[0] ; Merged with ula:ula_|i2s_intf:i2s_intf_|mclk_r ; -; Total Number of Removed Registers = 14 ; ; +; Total Number of Removed Registers = 24 ; ; +------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ @@ -2273,12 +2365,12 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ -; Total registers ; 592 ; -; Number of registers using Synchronous Clear ; 3 ; -; Number of registers using Synchronous Load ; 28 ; +; Total registers ; 649 ; +; Number of registers using Synchronous Clear ; 13 ; +; Number of registers using Synchronous Load ; 34 ; ; Number of registers using Asynchronous Clear ; 221 ; ; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 445 ; +; Number of registers using Clock Enable ; 464 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ @@ -2290,7 +2382,7 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak +----------------------------------------------------------+---------+ ; ula:ula_|i2s_intf:i2s_intf_|bitcount[4] ; 4 ; ; ula:ula_|i2s_intf:i2s_intf_|bitcount[0] ; 2 ; -; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 138 ; +; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 150 ; ; ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] ; 2 ; ; ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] ; 2 ; ; ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] ; 2 ; @@ -2305,22 +2397,22 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak ; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][1] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][1] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][1] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][1] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][1] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1] ; 2 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff ; 59 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][1] ; 2 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff ; 67 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][2] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][2] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][2] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][2] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][2] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][2] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][2] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][2] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][0] ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][2] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][0] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][0] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][0] ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][0] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][0] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][0] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][0] ; 2 ; @@ -2331,25 +2423,26 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak ; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][3] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][3] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][3] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][3] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][3] ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][3] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][4] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][4] ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][4] ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][4] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4] ; 2 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M1_ff ; 68 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M1_ff ; 65 ; ; z80_top_direct_n:z80_|resets:resets_|x1 ; 2 ; ; z80_top_direct_n:z80_|fpga_reset ; 2 ; +; sdram_controller:sdram_|r.init_counter[3] ; 3 ; ; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_m1_ff1 ; 1 ; ; ula:ula_|i2c_loader:i2c_loader_|scl_out ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|sda_out ; 3 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[0] ; 2 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|ps2_clk_in ; 2 ; -; Total number of inverted registers = 61 ; ; +; Total number of inverted registers = 62 ; ; +----------------------------------------------------------+---------+ @@ -2362,7 +2455,7 @@ Baseline Area : 20 LEs Area if Restructured : 10 LEs Saving if Restructured : 10 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vga_vc[2] +Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vga_vc[5] Multiplexer Inputs : 3:1 Bus Width : 4 bits @@ -2370,7 +2463,7 @@ Baseline Area : 8 LEs Area if Restructured : 4 LEs Saving if Restructured : 4 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[1] +Example Multiplexer Output : |spectrum|ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[3] Multiplexer Inputs : 4:1 Bus Width : 2 bits @@ -2378,7 +2471,15 @@ Baseline Area : 4 LEs Area if Restructured : 2 LEs Saving if Restructured : 2 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|bdivider[3] + +Multiplexer Inputs : 4:1 +Bus Width : 10 bits +Baseline Area : 20 LEs +Area if Restructured : 10 LEs +Saving if Restructured : 10 LEs +Registered : Yes +Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.rf_counter[3] Multiplexer Inputs : 6:1 Bus Width : 5 bits @@ -2386,7 +2487,7 @@ Baseline Area : 20 LEs Area if Restructured : 5 LEs Saving if Restructured : 15 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Multiplexer Inputs : 5:1 Bus Width : 3 bits @@ -2394,7 +2495,7 @@ Baseline Area : 9 LEs Area if Restructured : 3 LEs Saving if Restructured : 6 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|bitcount[3] Multiplexer Inputs : 5:1 Bus Width : 14 bits @@ -2402,7 +2503,7 @@ Baseline Area : 42 LEs Area if Restructured : 14 LEs Saving if Restructured : 28 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] Multiplexer Inputs : 5:1 Bus Width : 3 bits @@ -2410,7 +2511,7 @@ Baseline Area : 9 LEs Area if Restructured : 3 LEs Saving if Restructured : 6 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Example Multiplexer Output : |spectrum|ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] Multiplexer Inputs : 10:1 Bus Width : 2 bits @@ -2418,7 +2519,7 @@ Baseline Area : 12 LEs Area if Restructured : 2 LEs Saving if Restructured : 10 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vram_address[12] +Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vram_address[11] Multiplexer Inputs : 10:1 Bus Width : 2 bits @@ -2426,7 +2527,15 @@ Baseline Area : 12 LEs Area if Restructured : 2 LEs Saving if Restructured : 10 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vram_address[9] +Example Multiplexer Output : |spectrum|ula:ula_|video:video_|vram_address[8] + +Multiplexer Inputs : 32:1 +Bus Width : 5 bits +Baseline Area : 105 LEs +Area if Restructured : 0 LEs +Saving if Restructured : 105 LEs +Registered : Yes +Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.act_row[1] Multiplexer Inputs : 8:1 Bus Width : 2 bits @@ -2436,6 +2545,30 @@ Saving if Restructured : 6 LEs Registered : Yes Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Multiplexer Inputs : 32:1 +Bus Width : 2 bits +Baseline Area : 42 LEs +Area if Restructured : 2 LEs +Saving if Restructured : 40 LEs +Registered : Yes +Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.bank[0] + +Multiplexer Inputs : 31:1 +Bus Width : 4 bits +Baseline Area : 80 LEs +Area if Restructured : 4 LEs +Saving if Restructured : 76 LEs +Registered : Yes +Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.address[8] + +Multiplexer Inputs : 31:1 +Bus Width : 2 bits +Baseline Area : 40 LEs +Area if Restructured : 4 LEs +Saving if Restructured : 36 LEs +Registered : Yes +Example Multiplexer Output : |spectrum|sdram_controller:sdram_|r.address[3] + Multiplexer Inputs : 10:1 Bus Width : 2 bits Baseline Area : 12 LEs @@ -2458,7 +2591,7 @@ Baseline Area : 72 LEs Area if Restructured : 52 LEs Saving if Restructured : 20 LEs Registered : Yes -Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Multiplexer Inputs : 3:1 Bus Width : 16 bits @@ -2466,7 +2599,7 @@ Baseline Area : 32 LEs Area if Restructured : 32 LEs Saving if Restructured : 0 LEs Registered : Yes -Example Multiplexer Output : |spectrum|z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[5] +Example Multiplexer Output : |spectrum|z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[0] Multiplexer Inputs : 4:1 Bus Width : 3 bits @@ -2490,7 +2623,7 @@ Baseline Area : 9 LEs Area if Restructured : 6 LEs Saving if Restructured : 3 LEs Registered : No -Example Multiplexer Output : |spectrum|ula:ula_|video:video_|cindex[1] +Example Multiplexer Output : |spectrum|ula:ula_|video:video_|cindex[2] Multiplexer Inputs : 6:1 Bus Width : 2 bits @@ -2498,7 +2631,15 @@ Baseline Area : 8 LEs Area if Restructured : 6 LEs Saving if Restructured : 2 LEs Registered : No -Example Multiplexer Output : |spectrum|Mux2 +Example Multiplexer Output : |spectrum|Mux0 + +Multiplexer Inputs : 4:1 +Bus Width : 8 bits +Baseline Area : 16 LEs +Area if Restructured : 8 LEs +Saving if Restructured : 8 LEs +Registered : No +Example Multiplexer Output : |spectrum|sdram_controller:sdram_|Mux74 Multiplexer Inputs : 8:1 Bus Width : 6 bits @@ -2506,7 +2647,7 @@ Baseline Area : 30 LEs Area if Restructured : 24 LEs Saving if Restructured : 6 LEs Registered : No -Example Multiplexer Output : |spectrum|Selector3 +Example Multiplexer Output : |spectrum|Selector0 Multiplexer Inputs : 9:1 Bus Width : 2 bits @@ -2522,7 +2663,7 @@ Baseline Area : 14 LEs Area if Restructured : 4 LEs Saving if Restructured : 10 LEs Registered : No -Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|state.Done +Example Multiplexer Output : |spectrum|ula:ula_|i2c_loader:i2c_loader_|state.Pause +--------------------------------------------------------------------------------+ @@ -3205,6 +3346,1473 @@ Type : Untyped Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". ++--------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component ; ++--------------------------------------------------------------------------------+ +Parameter Name : OPERATION_MODE +Value : NORMAL +Type : Untyped + +Parameter Name : PLL_TYPE +Value : AUTO +Type : Untyped + +Parameter Name : LPM_HINT +Value : CBX_MODULE_PREFIX=sdram_clk_gen +Type : Untyped + +Parameter Name : QUALIFY_CONF_DONE +Value : OFF +Type : Untyped + +Parameter Name : COMPENSATE_CLOCK +Value : CLK0 +Type : Untyped + +Parameter Name : SCAN_CHAIN +Value : LONG +Type : Untyped + +Parameter Name : PRIMARY_CLOCK +Value : INCLK0 +Type : Untyped + +Parameter Name : INCLK0_INPUT_FREQUENCY +Value : 20000 +Type : Signed Integer + +Parameter Name : INCLK1_INPUT_FREQUENCY +Value : 0 +Type : Untyped + +Parameter Name : GATE_LOCK_SIGNAL +Value : NO +Type : Untyped + +Parameter Name : GATE_LOCK_COUNTER +Value : 0 +Type : Untyped + +Parameter Name : LOCK_HIGH +Value : 1 +Type : Untyped + +Parameter Name : LOCK_LOW +Value : 1 +Type : Untyped + +Parameter Name : VALID_LOCK_MULTIPLIER +Value : 1 +Type : Untyped + +Parameter Name : INVALID_LOCK_MULTIPLIER +Value : 5 +Type : Untyped + +Parameter Name : SWITCH_OVER_ON_LOSSCLK +Value : OFF +Type : Untyped + +Parameter Name : SWITCH_OVER_ON_GATED_LOCK +Value : OFF +Type : Untyped + +Parameter Name : ENABLE_SWITCH_OVER_COUNTER +Value : OFF +Type : Untyped + +Parameter Name : SKIP_VCO +Value : OFF +Type : Untyped + +Parameter Name : SWITCH_OVER_COUNTER +Value : 0 +Type : Untyped + +Parameter Name : SWITCH_OVER_TYPE +Value : AUTO +Type : Untyped + +Parameter Name : FEEDBACK_SOURCE +Value : EXTCLK0 +Type : Untyped + +Parameter Name : BANDWIDTH +Value : 0 +Type : Untyped + +Parameter Name : BANDWIDTH_TYPE +Value : AUTO +Type : Untyped + +Parameter Name : SPREAD_FREQUENCY +Value : 0 +Type : Untyped + +Parameter Name : DOWN_SPREAD +Value : 0 +Type : Untyped + +Parameter Name : SELF_RESET_ON_GATED_LOSS_LOCK +Value : OFF +Type : Untyped + +Parameter Name : SELF_RESET_ON_LOSS_LOCK +Value : OFF +Type : Untyped + +Parameter Name : CLK9_MULTIPLY_BY +Value : 0 +Type : Untyped + +Parameter Name : CLK8_MULTIPLY_BY +Value : 0 +Type : Untyped + +Parameter Name : CLK7_MULTIPLY_BY +Value : 0 +Type : Untyped + +Parameter Name : CLK6_MULTIPLY_BY +Value : 0 +Type : Untyped + +Parameter Name : CLK5_MULTIPLY_BY +Value : 1 +Type : Untyped + +Parameter Name : CLK4_MULTIPLY_BY +Value : 1 +Type : Untyped + +Parameter Name : CLK3_MULTIPLY_BY +Value : 1 +Type : Untyped + +Parameter Name : CLK2_MULTIPLY_BY +Value : 1 +Type : Untyped + +Parameter Name : CLK1_MULTIPLY_BY +Value : 2 +Type : Signed Integer + +Parameter Name : CLK0_MULTIPLY_BY +Value : 2 +Type : Signed Integer + +Parameter Name : CLK9_DIVIDE_BY +Value : 0 +Type : Untyped + +Parameter Name : CLK8_DIVIDE_BY +Value : 0 +Type : Untyped + +Parameter Name : CLK7_DIVIDE_BY +Value : 0 +Type : Untyped + +Parameter Name : CLK6_DIVIDE_BY +Value : 0 +Type : Untyped + +Parameter Name : CLK5_DIVIDE_BY +Value : 1 +Type : Untyped + +Parameter Name : CLK4_DIVIDE_BY +Value : 1 +Type : Untyped + +Parameter Name : CLK3_DIVIDE_BY +Value : 1 +Type : Untyped + +Parameter Name : CLK2_DIVIDE_BY +Value : 1 +Type : Untyped + +Parameter Name : CLK1_DIVIDE_BY +Value : 1 +Type : Signed Integer + +Parameter Name : CLK0_DIVIDE_BY +Value : 1 +Type : Signed Integer + +Parameter Name : CLK9_PHASE_SHIFT +Value : 0 +Type : Untyped + +Parameter Name : CLK8_PHASE_SHIFT +Value : 0 +Type : Untyped + +Parameter Name : CLK7_PHASE_SHIFT +Value : 0 +Type : Untyped + +Parameter Name : CLK6_PHASE_SHIFT +Value : 0 +Type : Untyped + +Parameter Name : CLK5_PHASE_SHIFT +Value : 0 +Type : Untyped + +Parameter Name : CLK4_PHASE_SHIFT +Value : 0 +Type : Untyped + +Parameter Name : CLK3_PHASE_SHIFT +Value : 0 +Type : Untyped + +Parameter Name : CLK2_PHASE_SHIFT +Value : 0 +Type : Untyped + +Parameter Name : CLK1_PHASE_SHIFT +Value : 3000 +Type : Untyped + +Parameter Name : CLK0_PHASE_SHIFT +Value : 0 +Type : Untyped + +Parameter Name : CLK5_TIME_DELAY +Value : 0 +Type : Untyped + +Parameter Name : CLK4_TIME_DELAY +Value : 0 +Type : Untyped + +Parameter Name : CLK3_TIME_DELAY +Value : 0 +Type : Untyped + +Parameter Name : CLK2_TIME_DELAY +Value : 0 +Type : Untyped + +Parameter Name : CLK1_TIME_DELAY +Value : 0 +Type : Untyped + +Parameter Name : CLK0_TIME_DELAY +Value : 0 +Type : Untyped + +Parameter Name : CLK9_DUTY_CYCLE +Value : 50 +Type : Untyped + +Parameter Name : CLK8_DUTY_CYCLE +Value : 50 +Type : Untyped + +Parameter Name : CLK7_DUTY_CYCLE +Value : 50 +Type : Untyped + +Parameter Name : CLK6_DUTY_CYCLE +Value : 50 +Type : Untyped + +Parameter Name : CLK5_DUTY_CYCLE +Value : 50 +Type : Untyped + +Parameter Name : CLK4_DUTY_CYCLE +Value : 50 +Type : Untyped + +Parameter Name : CLK3_DUTY_CYCLE +Value : 50 +Type : Untyped + +Parameter Name : CLK2_DUTY_CYCLE +Value : 50 +Type : Untyped + +Parameter Name : CLK1_DUTY_CYCLE +Value : 50 +Type : Signed Integer + +Parameter Name : CLK0_DUTY_CYCLE +Value : 50 +Type : Signed Integer + +Parameter Name : CLK9_USE_EVEN_COUNTER_MODE +Value : OFF +Type : Untyped + +Parameter Name : CLK8_USE_EVEN_COUNTER_MODE +Value : OFF +Type : Untyped + +Parameter Name : CLK7_USE_EVEN_COUNTER_MODE +Value : OFF +Type : Untyped + +Parameter Name : CLK6_USE_EVEN_COUNTER_MODE +Value : OFF +Type : Untyped + +Parameter Name : CLK5_USE_EVEN_COUNTER_MODE +Value : OFF +Type : Untyped + +Parameter Name : CLK4_USE_EVEN_COUNTER_MODE +Value : OFF +Type : Untyped + +Parameter Name : CLK3_USE_EVEN_COUNTER_MODE +Value : OFF +Type : Untyped + +Parameter Name : CLK2_USE_EVEN_COUNTER_MODE +Value : OFF +Type : Untyped + +Parameter Name : CLK1_USE_EVEN_COUNTER_MODE +Value : OFF +Type : Untyped + +Parameter Name : CLK0_USE_EVEN_COUNTER_MODE +Value : OFF +Type : Untyped + +Parameter Name : CLK9_USE_EVEN_COUNTER_VALUE +Value : OFF +Type : Untyped + +Parameter Name : CLK8_USE_EVEN_COUNTER_VALUE +Value : OFF +Type : Untyped + +Parameter Name : CLK7_USE_EVEN_COUNTER_VALUE +Value : OFF +Type : Untyped + +Parameter Name : CLK6_USE_EVEN_COUNTER_VALUE +Value : OFF +Type : Untyped + +Parameter Name : CLK5_USE_EVEN_COUNTER_VALUE +Value : OFF +Type : Untyped + +Parameter Name : CLK4_USE_EVEN_COUNTER_VALUE +Value : OFF +Type : Untyped + +Parameter Name : CLK3_USE_EVEN_COUNTER_VALUE +Value : OFF +Type : Untyped + +Parameter Name : CLK2_USE_EVEN_COUNTER_VALUE +Value : OFF +Type : Untyped + +Parameter Name : CLK1_USE_EVEN_COUNTER_VALUE +Value : OFF +Type : Untyped + +Parameter Name : CLK0_USE_EVEN_COUNTER_VALUE +Value : OFF +Type : Untyped + +Parameter Name : LOCK_WINDOW_UI +Value : 0.05 +Type : Untyped + +Parameter Name : LOCK_WINDOW_UI_BITS +Value : UNUSED +Type : Untyped + +Parameter Name : VCO_RANGE_DETECTOR_LOW_BITS +Value : UNUSED +Type : Untyped + +Parameter Name : VCO_RANGE_DETECTOR_HIGH_BITS +Value : UNUSED +Type : Untyped + +Parameter Name : DPA_MULTIPLY_BY +Value : 0 +Type : Untyped + +Parameter Name : DPA_DIVIDE_BY +Value : 1 +Type : Untyped + +Parameter Name : DPA_DIVIDER +Value : 0 +Type : Untyped + +Parameter Name : EXTCLK3_MULTIPLY_BY +Value : 1 +Type : Untyped + +Parameter Name : EXTCLK2_MULTIPLY_BY +Value : 1 +Type : Untyped + +Parameter Name : EXTCLK1_MULTIPLY_BY +Value : 1 +Type : Untyped + +Parameter Name : EXTCLK0_MULTIPLY_BY +Value : 1 +Type : Untyped + +Parameter Name : EXTCLK3_DIVIDE_BY +Value : 1 +Type : Untyped + +Parameter Name : EXTCLK2_DIVIDE_BY +Value : 1 +Type : Untyped + +Parameter Name : EXTCLK1_DIVIDE_BY +Value : 1 +Type : Untyped + +Parameter Name : EXTCLK0_DIVIDE_BY +Value : 1 +Type : Untyped + +Parameter Name : EXTCLK3_PHASE_SHIFT +Value : 0 +Type : Untyped + +Parameter Name : EXTCLK2_PHASE_SHIFT +Value : 0 +Type : Untyped + +Parameter Name : EXTCLK1_PHASE_SHIFT +Value : 0 +Type : Untyped + +Parameter Name : EXTCLK0_PHASE_SHIFT +Value : 0 +Type : Untyped + +Parameter Name : EXTCLK3_TIME_DELAY +Value : 0 +Type : Untyped + +Parameter Name : EXTCLK2_TIME_DELAY +Value : 0 +Type : Untyped + +Parameter Name : EXTCLK1_TIME_DELAY +Value : 0 +Type : Untyped + +Parameter Name : EXTCLK0_TIME_DELAY +Value : 0 +Type : Untyped + +Parameter Name : EXTCLK3_DUTY_CYCLE +Value : 50 +Type : Untyped + +Parameter Name : EXTCLK2_DUTY_CYCLE +Value : 50 +Type : Untyped + +Parameter Name : EXTCLK1_DUTY_CYCLE +Value : 50 +Type : Untyped + +Parameter Name : EXTCLK0_DUTY_CYCLE +Value : 50 +Type : Untyped + +Parameter Name : VCO_MULTIPLY_BY +Value : 0 +Type : Untyped + +Parameter Name : VCO_DIVIDE_BY +Value : 0 +Type : Untyped + +Parameter Name : SCLKOUT0_PHASE_SHIFT +Value : 0 +Type : Untyped + +Parameter Name : SCLKOUT1_PHASE_SHIFT +Value : 0 +Type : Untyped + +Parameter Name : VCO_MIN +Value : 0 +Type : Untyped + +Parameter Name : VCO_MAX +Value : 0 +Type : Untyped + +Parameter Name : VCO_CENTER +Value : 0 +Type : Untyped + +Parameter Name : PFD_MIN +Value : 0 +Type : Untyped + +Parameter Name : PFD_MAX +Value : 0 +Type : Untyped + +Parameter Name : M_INITIAL +Value : 0 +Type : Untyped + +Parameter Name : M +Value : 0 +Type : Untyped + +Parameter Name : N +Value : 1 +Type : Untyped + +Parameter Name : M2 +Value : 1 +Type : Untyped + +Parameter Name : N2 +Value : 1 +Type : Untyped + +Parameter Name : SS +Value : 1 +Type : Untyped + +Parameter Name : C0_HIGH +Value : 0 +Type : Untyped + +Parameter Name : C1_HIGH +Value : 0 +Type : Untyped + +Parameter Name : C2_HIGH +Value : 0 +Type : Untyped + +Parameter Name : C3_HIGH +Value : 0 +Type : Untyped + +Parameter Name : C4_HIGH +Value : 0 +Type : Untyped + +Parameter Name : C5_HIGH +Value : 0 +Type : Untyped + +Parameter Name : C6_HIGH +Value : 0 +Type : Untyped + +Parameter Name : C7_HIGH +Value : 0 +Type : Untyped + +Parameter Name : C8_HIGH +Value : 0 +Type : Untyped + +Parameter Name : C9_HIGH +Value : 0 +Type : Untyped + +Parameter Name : C0_LOW +Value : 0 +Type : Untyped + +Parameter Name : C1_LOW +Value : 0 +Type : Untyped + +Parameter Name : C2_LOW +Value : 0 +Type : Untyped + +Parameter Name : C3_LOW +Value : 0 +Type : Untyped + +Parameter Name : C4_LOW +Value : 0 +Type : Untyped + +Parameter Name : C5_LOW +Value : 0 +Type : Untyped + +Parameter Name : C6_LOW +Value : 0 +Type : Untyped + +Parameter Name : C7_LOW +Value : 0 +Type : Untyped + +Parameter Name : C8_LOW +Value : 0 +Type : Untyped + +Parameter Name : C9_LOW +Value : 0 +Type : Untyped + +Parameter Name : C0_INITIAL +Value : 0 +Type : Untyped + +Parameter Name : C1_INITIAL +Value : 0 +Type : Untyped + +Parameter Name : C2_INITIAL +Value : 0 +Type : Untyped + +Parameter Name : C3_INITIAL +Value : 0 +Type : Untyped + +Parameter Name : C4_INITIAL +Value : 0 +Type : Untyped + +Parameter Name : C5_INITIAL +Value : 0 +Type : Untyped + +Parameter Name : C6_INITIAL +Value : 0 +Type : Untyped + +Parameter Name : C7_INITIAL +Value : 0 +Type : Untyped + +Parameter Name : C8_INITIAL +Value : 0 +Type : Untyped + +Parameter Name : C9_INITIAL +Value : 0 +Type : Untyped + +Parameter Name : C0_MODE +Value : BYPASS +Type : Untyped + +Parameter Name : C1_MODE +Value : BYPASS +Type : Untyped + +Parameter Name : C2_MODE +Value : BYPASS +Type : Untyped + +Parameter Name : C3_MODE +Value : BYPASS +Type : Untyped + +Parameter Name : C4_MODE +Value : BYPASS +Type : Untyped + +Parameter Name : C5_MODE +Value : BYPASS +Type : Untyped + +Parameter Name : C6_MODE +Value : BYPASS +Type : Untyped + +Parameter Name : C7_MODE +Value : BYPASS +Type : Untyped + +Parameter Name : C8_MODE +Value : BYPASS +Type : Untyped + +Parameter Name : C9_MODE +Value : BYPASS +Type : Untyped + +Parameter Name : C0_PH +Value : 0 +Type : Untyped + +Parameter Name : C1_PH +Value : 0 +Type : Untyped + +Parameter Name : C2_PH +Value : 0 +Type : Untyped + +Parameter Name : C3_PH +Value : 0 +Type : Untyped + +Parameter Name : C4_PH +Value : 0 +Type : Untyped + +Parameter Name : C5_PH +Value : 0 +Type : Untyped + +Parameter Name : C6_PH +Value : 0 +Type : Untyped + +Parameter Name : C7_PH +Value : 0 +Type : Untyped + +Parameter Name : C8_PH +Value : 0 +Type : Untyped + +Parameter Name : C9_PH +Value : 0 +Type : Untyped + +Parameter Name : L0_HIGH +Value : 1 +Type : Untyped + +Parameter Name : L1_HIGH +Value : 1 +Type : Untyped + +Parameter Name : G0_HIGH +Value : 1 +Type : Untyped + +Parameter Name : G1_HIGH +Value : 1 +Type : Untyped + +Parameter Name : G2_HIGH +Value : 1 +Type : Untyped + +Parameter Name : G3_HIGH +Value : 1 +Type : Untyped + +Parameter Name : E0_HIGH +Value : 1 +Type : Untyped + +Parameter Name : E1_HIGH +Value : 1 +Type : Untyped + +Parameter Name : E2_HIGH +Value : 1 +Type : Untyped + +Parameter Name : E3_HIGH +Value : 1 +Type : Untyped + +Parameter Name : L0_LOW +Value : 1 +Type : Untyped + +Parameter Name : L1_LOW +Value : 1 +Type : Untyped + +Parameter Name : G0_LOW +Value : 1 +Type : Untyped + +Parameter Name : G1_LOW +Value : 1 +Type : Untyped + +Parameter Name : G2_LOW +Value : 1 +Type : Untyped + +Parameter Name : G3_LOW +Value : 1 +Type : Untyped + +Parameter Name : E0_LOW +Value : 1 +Type : Untyped + +Parameter Name : E1_LOW +Value : 1 +Type : Untyped + +Parameter Name : E2_LOW +Value : 1 +Type : Untyped + +Parameter Name : E3_LOW +Value : 1 +Type : Untyped + +Parameter Name : L0_INITIAL +Value : 1 +Type : Untyped + +Parameter Name : L1_INITIAL +Value : 1 +Type : Untyped + +Parameter Name : G0_INITIAL +Value : 1 +Type : Untyped + +Parameter Name : G1_INITIAL +Value : 1 +Type : Untyped + +Parameter Name : G2_INITIAL +Value : 1 +Type : Untyped + +Parameter Name : G3_INITIAL +Value : 1 +Type : Untyped + +Parameter Name : E0_INITIAL +Value : 1 +Type : Untyped + +Parameter Name : E1_INITIAL +Value : 1 +Type : Untyped + +Parameter Name : E2_INITIAL +Value : 1 +Type : Untyped + +Parameter Name : E3_INITIAL +Value : 1 +Type : Untyped + +Parameter Name : L0_MODE +Value : BYPASS +Type : Untyped + +Parameter Name : L1_MODE +Value : BYPASS +Type : Untyped + +Parameter Name : G0_MODE +Value : BYPASS +Type : Untyped + +Parameter Name : G1_MODE +Value : BYPASS +Type : Untyped + +Parameter Name : G2_MODE +Value : BYPASS +Type : Untyped + +Parameter Name : G3_MODE +Value : BYPASS +Type : Untyped + +Parameter Name : E0_MODE +Value : BYPASS +Type : Untyped + +Parameter Name : E1_MODE +Value : BYPASS +Type : Untyped + +Parameter Name : E2_MODE +Value : BYPASS +Type : Untyped + +Parameter Name : E3_MODE +Value : BYPASS +Type : Untyped + +Parameter Name : L0_PH +Value : 0 +Type : Untyped + +Parameter Name : L1_PH +Value : 0 +Type : Untyped + +Parameter Name : G0_PH +Value : 0 +Type : Untyped + +Parameter Name : G1_PH +Value : 0 +Type : Untyped + +Parameter Name : G2_PH +Value : 0 +Type : Untyped + +Parameter Name : G3_PH +Value : 0 +Type : Untyped + +Parameter Name : E0_PH +Value : 0 +Type : Untyped + +Parameter Name : E1_PH +Value : 0 +Type : Untyped + +Parameter Name : E2_PH +Value : 0 +Type : Untyped + +Parameter Name : E3_PH +Value : 0 +Type : Untyped + +Parameter Name : M_PH +Value : 0 +Type : Untyped + +Parameter Name : C1_USE_CASC_IN +Value : OFF +Type : Untyped + +Parameter Name : C2_USE_CASC_IN +Value : OFF +Type : Untyped + +Parameter Name : C3_USE_CASC_IN +Value : OFF +Type : Untyped + +Parameter Name : C4_USE_CASC_IN +Value : OFF +Type : Untyped + +Parameter Name : C5_USE_CASC_IN +Value : OFF +Type : Untyped + +Parameter Name : C6_USE_CASC_IN +Value : OFF +Type : Untyped + +Parameter Name : C7_USE_CASC_IN +Value : OFF +Type : Untyped + +Parameter Name : C8_USE_CASC_IN +Value : OFF +Type : Untyped + +Parameter Name : C9_USE_CASC_IN +Value : OFF +Type : Untyped + +Parameter Name : CLK0_COUNTER +Value : G0 +Type : Untyped + +Parameter Name : CLK1_COUNTER +Value : G0 +Type : Untyped + +Parameter Name : CLK2_COUNTER +Value : G0 +Type : Untyped + +Parameter Name : CLK3_COUNTER +Value : G0 +Type : Untyped + +Parameter Name : CLK4_COUNTER +Value : G0 +Type : Untyped + +Parameter Name : CLK5_COUNTER +Value : G0 +Type : Untyped + +Parameter Name : CLK6_COUNTER +Value : E0 +Type : Untyped + +Parameter Name : CLK7_COUNTER +Value : E1 +Type : Untyped + +Parameter Name : CLK8_COUNTER +Value : E2 +Type : Untyped + +Parameter Name : CLK9_COUNTER +Value : E3 +Type : Untyped + +Parameter Name : L0_TIME_DELAY +Value : 0 +Type : Untyped + +Parameter Name : L1_TIME_DELAY +Value : 0 +Type : Untyped + +Parameter Name : G0_TIME_DELAY +Value : 0 +Type : Untyped + +Parameter Name : G1_TIME_DELAY +Value : 0 +Type : Untyped + +Parameter Name : G2_TIME_DELAY +Value : 0 +Type : Untyped + +Parameter Name : G3_TIME_DELAY +Value : 0 +Type : Untyped + +Parameter Name : E0_TIME_DELAY +Value : 0 +Type : Untyped + +Parameter Name : E1_TIME_DELAY +Value : 0 +Type : Untyped + +Parameter Name : E2_TIME_DELAY +Value : 0 +Type : Untyped + +Parameter Name : E3_TIME_DELAY +Value : 0 +Type : Untyped + +Parameter Name : M_TIME_DELAY +Value : 0 +Type : Untyped + +Parameter Name : N_TIME_DELAY +Value : 0 +Type : Untyped + +Parameter Name : EXTCLK3_COUNTER +Value : E3 +Type : Untyped + +Parameter Name : EXTCLK2_COUNTER +Value : E2 +Type : Untyped + +Parameter Name : EXTCLK1_COUNTER +Value : E1 +Type : Untyped + +Parameter Name : EXTCLK0_COUNTER +Value : E0 +Type : Untyped + +Parameter Name : ENABLE0_COUNTER +Value : L0 +Type : Untyped + +Parameter Name : ENABLE1_COUNTER +Value : L0 +Type : Untyped + +Parameter Name : CHARGE_PUMP_CURRENT +Value : 2 +Type : Untyped + +Parameter Name : LOOP_FILTER_R +Value : 1.000000 +Type : Untyped + +Parameter Name : LOOP_FILTER_C +Value : 5 +Type : Untyped + +Parameter Name : CHARGE_PUMP_CURRENT_BITS +Value : 9999 +Type : Untyped + +Parameter Name : LOOP_FILTER_R_BITS +Value : 9999 +Type : Untyped + +Parameter Name : LOOP_FILTER_C_BITS +Value : 9999 +Type : Untyped + +Parameter Name : VCO_POST_SCALE +Value : 0 +Type : Untyped + +Parameter Name : CLK2_OUTPUT_FREQUENCY +Value : 0 +Type : Untyped + +Parameter Name : CLK1_OUTPUT_FREQUENCY +Value : 0 +Type : Untyped + +Parameter Name : CLK0_OUTPUT_FREQUENCY +Value : 0 +Type : Untyped + +Parameter Name : INTENDED_DEVICE_FAMILY +Value : Cyclone IV E +Type : Untyped + +Parameter Name : PORT_CLKENA0 +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_CLKENA1 +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_CLKENA2 +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_CLKENA3 +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_CLKENA4 +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_CLKENA5 +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_EXTCLKENA0 +Value : PORT_CONNECTIVITY +Type : Untyped + +Parameter Name : PORT_EXTCLKENA1 +Value : PORT_CONNECTIVITY +Type : Untyped + +Parameter Name : PORT_EXTCLKENA2 +Value : PORT_CONNECTIVITY +Type : Untyped + +Parameter Name : PORT_EXTCLKENA3 +Value : PORT_CONNECTIVITY +Type : Untyped + +Parameter Name : PORT_EXTCLK0 +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_EXTCLK1 +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_EXTCLK2 +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_EXTCLK3 +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_CLKBAD0 +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_CLKBAD1 +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_CLK0 +Value : PORT_USED +Type : Untyped + +Parameter Name : PORT_CLK1 +Value : PORT_USED +Type : Untyped + +Parameter Name : PORT_CLK2 +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_CLK3 +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_CLK4 +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_CLK5 +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_CLK6 +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_CLK7 +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_CLK8 +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_CLK9 +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_SCANDATA +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_SCANDATAOUT +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_SCANDONE +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_SCLKOUT1 +Value : PORT_CONNECTIVITY +Type : Untyped + +Parameter Name : PORT_SCLKOUT0 +Value : PORT_CONNECTIVITY +Type : Untyped + +Parameter Name : PORT_ACTIVECLOCK +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_CLKLOSS +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_INCLK1 +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_INCLK0 +Value : PORT_USED +Type : Untyped + +Parameter Name : PORT_FBIN +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_PLLENA +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_CLKSWITCH +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_ARESET +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_PFDENA +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_SCANCLK +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_SCANACLR +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_SCANREAD +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_SCANWRITE +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_ENABLE0 +Value : PORT_CONNECTIVITY +Type : Untyped + +Parameter Name : PORT_ENABLE1 +Value : PORT_CONNECTIVITY +Type : Untyped + +Parameter Name : PORT_LOCKED +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_CONFIGUPDATE +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_FBOUT +Value : PORT_CONNECTIVITY +Type : Untyped + +Parameter Name : PORT_PHASEDONE +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_PHASESTEP +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_PHASEUPDOWN +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_SCANCLKENA +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_PHASECOUNTERSELECT +Value : PORT_UNUSED +Type : Untyped + +Parameter Name : PORT_VCOOVERRANGE +Value : PORT_CONNECTIVITY +Type : Untyped + +Parameter Name : PORT_VCOUNDERRANGE +Value : PORT_CONNECTIVITY +Type : Untyped + +Parameter Name : M_TEST_SOURCE +Value : 5 +Type : Untyped + +Parameter Name : C0_TEST_SOURCE +Value : 5 +Type : Untyped + +Parameter Name : C1_TEST_SOURCE +Value : 5 +Type : Untyped + +Parameter Name : C2_TEST_SOURCE +Value : 5 +Type : Untyped + +Parameter Name : C3_TEST_SOURCE +Value : 5 +Type : Untyped + +Parameter Name : C4_TEST_SOURCE +Value : 5 +Type : Untyped + +Parameter Name : C5_TEST_SOURCE +Value : 5 +Type : Untyped + +Parameter Name : C6_TEST_SOURCE +Value : 5 +Type : Untyped + +Parameter Name : C7_TEST_SOURCE +Value : 5 +Type : Untyped + +Parameter Name : C8_TEST_SOURCE +Value : 5 +Type : Untyped + +Parameter Name : C9_TEST_SOURCE +Value : 5 +Type : Untyped + +Parameter Name : CBXI_PARAMETER +Value : sdram_clk_gen_altpll +Type : Untyped + +Parameter Name : VCO_FREQUENCY_CONTROL +Value : AUTO +Type : Untyped + +Parameter Name : VCO_PHASE_SHIFT_STEP +Value : 0 +Type : Untyped + +Parameter Name : WIDTH_CLOCK +Value : 5 +Type : Signed Integer + +Parameter Name : WIDTH_PHASECOUNTERSELECT +Value : 4 +Type : Untyped + +Parameter Name : USING_FBMIMICBIDIR_PORT +Value : OFF +Type : Untyped + +Parameter Name : DEVICE_FAMILY +Value : Cyclone IV E +Type : Untyped + +Parameter Name : SCAN_CHAIN_MIF_FILE +Value : UNUSED +Type : Untyped + +Parameter Name : SIM_GATE_LOCK_DEVICE_BEHAVIOR +Value : OFF +Type : Untyped + +Parameter Name : AUTO_CARRY_CHAINS +Value : ON +Type : AUTO_CARRY + +Parameter Name : IGNORE_CARRY_BUFFERS +Value : OFF +Type : IGNORE_CARRY + +Parameter Name : AUTO_CASCADE_CHAINS +Value : ON +Type : AUTO_CASCADE + +Parameter Name : IGNORE_CASCADE_BUFFERS +Value : OFF +Type : IGNORE_CASCADE ++--------------------------------------------------------------------------------+ + +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + +--------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: ula:ula_|pll:pll_|altpll:altpll_component ; +--------------------------------------------------------------------------------+ @@ -4756,21 +6364,29 @@ Note: In order to hide this table in the UI and the text report file, please set +-------------------------------------------+--------------------------------------------+ -+---------------------------------------------------------------------------+ -; altpll Parameter Settings by Entity Instance ; -+-------------------------------+-------------------------------------------+ -; Name ; Value ; -+-------------------------------+-------------------------------------------+ -; Number of entity instances ; 1 ; -; Entity Instance ; ula:ula_|pll:pll_|altpll:altpll_component ; -; -- OPERATION_MODE ; NORMAL ; -; -- PLL_TYPE ; AUTO ; -; -- PRIMARY_CLOCK ; INCLK0 ; -; -- INCLK0_INPUT_FREQUENCY ; 20000 ; -; -- INCLK1_INPUT_FREQUENCY ; 0 ; -; -- VCO_MULTIPLY_BY ; 0 ; -; -- VCO_DIVIDE_BY ; 0 ; -+-------------------------------+-------------------------------------------+ ++-------------------------------------------------------------------------------------------------------------+ +; altpll Parameter Settings by Entity Instance ; ++-------------------------------+-----------------------------------------------------------------------------+ +; Name ; Value ; ++-------------------------------+-----------------------------------------------------------------------------+ +; Number of entity instances ; 2 ; +; Entity Instance ; sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component ; +; -- OPERATION_MODE ; NORMAL ; +; -- PLL_TYPE ; AUTO ; +; -- PRIMARY_CLOCK ; INCLK0 ; +; -- INCLK0_INPUT_FREQUENCY ; 20000 ; +; -- INCLK1_INPUT_FREQUENCY ; 0 ; +; -- VCO_MULTIPLY_BY ; 0 ; +; -- VCO_DIVIDE_BY ; 0 ; +; Entity Instance ; ula:ula_|pll:pll_|altpll:altpll_component ; +; -- OPERATION_MODE ; NORMAL ; +; -- PLL_TYPE ; AUTO ; +; -- PRIMARY_CLOCK ; INCLK0 ; +; -- INCLK0_INPUT_FREQUENCY ; 20000 ; +; -- INCLK1_INPUT_FREQUENCY ; 0 ; +; -- VCO_MULTIPLY_BY ; 0 ; +; -- VCO_DIVIDE_BY ; 0 ; ++-------------------------------+-----------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+ @@ -4896,6 +6512,32 @@ Details : Connected to dangling logic. Logic that only feeds a dangling port wi ++--------------------------------------------------------------------------------+ +; Port Connectivity Checks: "sdram_controller:sdram_" ; ++--------------------------------------------------------------------------------+ +Port : address[23..16] +Type : Input +Severity : Info +Details : Stuck at GND + +Port : data_out +Type : Output +Severity : Info +Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed. + +Port : data_out_valid +Type : Output +Severity : Info +Details : Connected to dangling logic. Logic that only feeds a dangling port will be removed. + +Port : data_in[31..8] +Type : Input +Severity : Info +Details : Stuck at GND ++--------------------------------------------------------------------------------+ + + + +--------------------------------------------------------------------------------+ ; Port Connectivity Checks: "ram16:ram0" ; +--------------------------------------------------------------------------------+ @@ -4938,7 +6580,7 @@ Details : Input port expression (16 bits) is wider than the input port (14 bits +----------------+--------------+ ; Partition Name ; Elapsed Time ; +----------------+--------------+ -; Top ; 00:00:10 ; +; Top ; 00:00:11 ; +----------------+--------------+ @@ -4948,7 +6590,7 @@ Details : Input port expression (16 bits) is wider than the input port (14 bits Info: ******************************************************************* Info: Running Quartus II 32-bit Analysis & Synthesis Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Fri Apr 1 18:55:04 2022 + Info: Processing started: Sat Apr 2 14:50:31 2022 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum Warning (20028): Parallel compilation is not licensed and has been disabled Info (12021): Found 1 design units, including 1 entities, in source file spectrum.sv @@ -5061,6 +6703,11 @@ Info (12021): Found 1 design units, including 1 entities, in source file pll_vid Info (12023): Found entity 1: pll_video Info (12021): Found 1 design units, including 1 entities, in source file ram_video.v Info (12023): Found entity 1: ram_video +Info (12021): Found 2 design units, including 1 entities, in source file sdram.vhdl + Info (12022): Found design unit 1: sdram_controller-rtl + Info (12023): Found entity 1: sdram_controller +Info (12021): Found 1 design units, including 1 entities, in source file sdram_clk_gen.v + Info (12023): Found entity 1: sdram_clk_gen Info (12127): Elaborating entity "spectrum" for the top level hierarchy Warning (10034): Output port "LED[7..4]" at spectrum.sv(1) has no driver Warning (10034): Output port "LED[1]" at spectrum.sv(1) has no driver @@ -5160,6 +6807,72 @@ Info (12128): Elaborating entity "decode_f8a" for hierarchy "ram32:ram1|altsyncr Info (12021): Found 1 design units, including 1 entities, in source file db/mux_6nb.tdf Info (12023): Found entity 1: mux_6nb Info (12128): Elaborating entity "mux_6nb" for hierarchy "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|mux_6nb:mux2" +Info (12128): Elaborating entity "sdram_controller" for hierarchy "sdram_controller:sdram_" +Info (12128): Elaborating entity "sdram_clk_gen" for hierarchy "sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll" +Info (12128): Elaborating entity "altpll" for hierarchy "sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component" +Info (12130): Elaborated megafunction instantiation "sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component" +Info (12133): Instantiated megafunction "sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component" with the following parameter: + Info (12134): Parameter "bandwidth_type" = "AUTO" + Info (12134): Parameter "clk0_divide_by" = "1" + Info (12134): Parameter "clk0_duty_cycle" = "50" + Info (12134): Parameter "clk0_multiply_by" = "2" + Info (12134): Parameter "clk0_phase_shift" = "0" + Info (12134): Parameter "clk1_divide_by" = "1" + Info (12134): Parameter "clk1_duty_cycle" = "50" + Info (12134): Parameter "clk1_multiply_by" = "2" + Info (12134): Parameter "clk1_phase_shift" = "3000" + Info (12134): Parameter "compensate_clock" = "CLK0" + Info (12134): Parameter "inclk0_input_frequency" = "20000" + Info (12134): Parameter "intended_device_family" = "Cyclone IV E" + Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=sdram_clk_gen" + Info (12134): Parameter "lpm_type" = "altpll" + Info (12134): Parameter "operation_mode" = "NORMAL" + Info (12134): Parameter "pll_type" = "AUTO" + Info (12134): Parameter "port_activeclock" = "PORT_UNUSED" + Info (12134): Parameter "port_areset" = "PORT_UNUSED" + Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED" + Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED" + Info (12134): Parameter "port_clkloss" = "PORT_UNUSED" + Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED" + Info (12134): Parameter "port_configupdate" = "PORT_UNUSED" + Info (12134): Parameter "port_fbin" = "PORT_UNUSED" + Info (12134): Parameter "port_inclk0" = "PORT_USED" + Info (12134): Parameter "port_inclk1" = "PORT_UNUSED" + Info (12134): Parameter "port_locked" = "PORT_UNUSED" + Info (12134): Parameter "port_pfdena" = "PORT_UNUSED" + Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED" + Info (12134): Parameter "port_phasedone" = "PORT_UNUSED" + Info (12134): Parameter "port_phasestep" = "PORT_UNUSED" + Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED" + Info (12134): Parameter "port_pllena" = "PORT_UNUSED" + Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED" + Info (12134): Parameter "port_scanclk" = "PORT_UNUSED" + Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED" + Info (12134): Parameter "port_scandata" = "PORT_UNUSED" + Info (12134): Parameter "port_scandataout" = "PORT_UNUSED" + Info (12134): Parameter "port_scandone" = "PORT_UNUSED" + Info (12134): Parameter "port_scanread" = "PORT_UNUSED" + Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED" + Info (12134): Parameter "port_clk0" = "PORT_USED" + Info (12134): Parameter "port_clk1" = "PORT_USED" + Info (12134): Parameter "port_clk2" = "PORT_UNUSED" + Info (12134): Parameter "port_clk3" = "PORT_UNUSED" + Info (12134): Parameter "port_clk4" = "PORT_UNUSED" + Info (12134): Parameter "port_clk5" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena0" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena1" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena2" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena3" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena4" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena5" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk0" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk1" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk2" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk3" = "PORT_UNUSED" + Info (12134): Parameter "width_clock" = "5" +Info (12021): Found 1 design units, including 1 entities, in source file db/sdram_clk_gen_altpll.v + Info (12023): Found entity 1: sdram_clk_gen_altpll +Info (12128): Elaborating entity "sdram_clk_gen_altpll" for hierarchy "sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated" Info (12128): Elaborating entity "ula" for hierarchy "ula:ula_" Info (12128): Elaborating entity "pll" for hierarchy "ula:ula_|pll:pll_" Info (12128): Elaborating entity "altpll" for hierarchy "ula:ula_|pll:pll_|altpll:altpll_component" @@ -5293,10 +7006,10 @@ Warning (13046): Tri-state node(s) do not directly drive top-level pin(s) Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[12]" to the node "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0" into an OR gate Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[13]" to the node "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0]" into an OR gate Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[14]" to the node "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]" into an OR gate - Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[15]" to the node "ExtRamWE" into an OR gate + Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|address_pins:address_pins_|abus[15]" to the node "RamWE" into an OR gate Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nWR" to the node "RamWE" into an OR gate - Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nRD" to the node "Equal2" into an OR gate - Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nIORQ" to the node "Equal2" into an OR gate + Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nRD" to the node "Equal1" into an OR gate + Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|control_pins_n:control_pins_|pin_nIORQ" to the node "Equal1" into an OR gate Warning (13046): Tri-state node(s) do not directly drive top-level pin(s) Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|bus_control:bus_control_|db[0]" to the node "z80_top_direct_n:z80_|ir:ir_|opcode[0]" into an OR gate Warning (13047): Converted the fan-out from the tri-state buffer "z80_top_direct_n:z80_|bus_control:bus_control_|db[7]" to the node "z80_top_direct_n:z80_|ir:ir_|opcode[7]" into an OR gate @@ -5381,26 +7094,28 @@ Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "GPIO_1[24]" is stuck at VCC Warning (13410): Pin "GPIO_1[32]" is stuck at GND Warning (13410): Pin "GPIO_1[33]" is stuck at GND + Warning (13410): Pin "DRAM_CKE" is stuck at VCC + Warning (13410): Pin "DRAM_CS_N" is stuck at GND Info (286030): Timing-Driven Synthesis is running Info (17049): 2 registers lost all their fanouts during netlist optimizations. Info (144001): Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" - Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL + Info (16011): Adding 2 node(s), including 0 DDIO, 2 PLL, 0 transceiver and 0 LCELL Warning (21074): Design contains 2 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "SW[0]" Warning (15610): No output dependent on input pin "SW[3]" -Info (21057): Implemented 2747 device resources after synthesis - the final resource count might be different +Info (21057): Implemented 3006 device resources after synthesis - the final resource count might be different Info (21058): Implemented 11 input pins - Info (21059): Implemented 62 output pins - Info (21060): Implemented 2 bidirectional pins - Info (21061): Implemented 2607 logic cells + Info (21059): Implemented 85 output pins + Info (21060): Implemented 18 bidirectional pins + Info (21061): Implemented 2826 logic cells Info (21064): Implemented 64 RAM segments - Info (21065): Implemented 1 PLLs -Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 110 warnings - Info: Peak virtual memory: 441 megabytes - Info: Processing ended: Fri Apr 1 18:55:17 2022 - Info: Elapsed time: 00:00:13 - Info: Total CPU time (on all processors): 00:00:13 + Info (21065): Implemented 2 PLLs +Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 112 warnings + Info: Peak virtual memory: 446 megabytes + Info: Processing ended: Sat Apr 2 14:50:45 2022 + Info: Elapsed time: 00:00:14 + Info: Total CPU time (on all processors): 00:00:15 +------------------------------------------+ diff --git a/output_files/spectrum.map.summary b/output_files/spectrum.map.summary index 24e537b..547a1c8 100644 --- a/output_files/spectrum.map.summary +++ b/output_files/spectrum.map.summary @@ -1,14 +1,14 @@ -Analysis & Synthesis Status : Successful - Fri Apr 1 18:55:17 2022 +Analysis & Synthesis Status : Successful - Sat Apr 2 14:50:45 2022 Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition Revision Name : spectrum Top-level Entity Name : spectrum Family : Cyclone IV E -Total logic elements : 2,537 - Total combinational functions : 2,269 - Dedicated logic registers : 592 -Total registers : 592 -Total pins : 75 +Total logic elements : 2,751 + Total combinational functions : 2,480 + Dedicated logic registers : 649 +Total registers : 649 +Total pins : 114 Total virtual pins : 0 Total memory bits : 524,288 Embedded Multiplier 9-bit elements : 0 -Total PLLs : 1 +Total PLLs : 2 diff --git a/output_files/spectrum.pin b/output_files/spectrum.pin index 265825f..23d60f8 100644 --- a/output_files/spectrum.pin +++ b/output_files/spectrum.pin @@ -101,7 +101,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : GND : B15 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 6 : ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : input : 3.3-V LVTTL : : 1 : N -RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 : +DRAM_WE_N : C2 : output : 3.3-V LVTTL : : 1 : Y RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : VCCIO8 : C4 : power : : 3.3V : 8 : GND : C5 : gnd : : : : @@ -164,8 +164,8 @@ GPIO_1[0] : F13 : output : 3.3-V LVTTL : RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 6 : RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 6 : ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : F16 : output : 3.3-V LVTTL : : 6 : N -RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 : +DRAM_DQ[1] : G1 : bidir : 3.3-V LVTTL : : 1 : Y +DRAM_DQ[0] : G2 : bidir : 3.3-V LVTTL : : 1 : Y VCCIO1 : G3 : power : : 3.3V : 1 : GND : G4 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 : @@ -196,8 +196,8 @@ MSEL0 : H13 : : : CONF_DONE : H14 : : : : 6 : GND : H15 : gnd : : : : GND : H16 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : J2 : : : : 2 : +DRAM_DQ[6] : J1 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[5] : J2 : bidir : 3.3-V LVTTL : : 2 : Y nCE : J3 : : : : 1 : TDO : J4 : output : : : 1 : TMS : J5 : input : : : 1 : @@ -212,11 +212,11 @@ GPIO_1[32] : J13 : output : 3.3-V LVTTL : GPIO_1[33] : J14 : output : 3.3-V LVTTL : : 5 : Y KEY[0] : J15 : input : 3.3-V LVTTL : : 5 : Y GPIO_1[30] : J16 : output : 3.3-V LVTTL : : 5 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 2 : +DRAM_DQ[15] : K1 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[4] : K2 : bidir : 3.3-V LVTTL : : 2 : Y VCCIO2 : K3 : power : : 3.3V : 2 : GND : K4 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 2 : +DRAM_DQ[3] : K5 : bidir : 3.3-V LVTTL : : 2 : Y GND : K6 : gnd : : : : VCCINT : K7 : power : : 1.2V : : GND : K8 : gnd : : : : @@ -228,14 +228,14 @@ GND : K13 : gnd : : VCCIO5 : K14 : power : : 3.3V : 5 : GPIO_1[31] : K15 : output : 3.3-V LVTTL : : 5 : Y GPIO_1[17] : K16 : output : 3.3-V LVTTL : : 5 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 2 : +DRAM_CAS_N : L1 : output : 3.3-V LVTTL : : 2 : Y +DRAM_RAS_N : L2 : output : 3.3-V LVTTL : : 2 : Y LED[7] : L3 : output : 3.3-V LVTTL : : 2 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 2 : +DRAM_ADDR[12] : L4 : output : 3.3-V LVTTL : : 2 : Y VCCA1 : L5 : power : : 2.5V : : VCCINT : L6 : power : : 1.2V : : -RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 3 : +DRAM_CKE : L7 : output : 3.3-V LVTTL : : 3 : Y +DRAM_DQ[2] : L8 : bidir : 3.3-V LVTTL : : 3 : Y GND : L9 : gnd : : : : GND : L10 : gnd : : : : GND : L11 : gnd : : : : @@ -249,9 +249,9 @@ GND+ : M2 : : : VCCIO2 : M3 : power : : 3.3V : 2 : GND : M4 : gnd : : : : GNDA1 : M5 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : M6 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 3 : +DRAM_BA[1] : M6 : output : 3.3-V LVTTL : : 3 : Y +DRAM_BA[0] : M7 : output : 3.3-V LVTTL : : 3 : Y +DRAM_ADDR[3] : M8 : output : 3.3-V LVTTL : : 3 : Y VCCINT : M9 : power : : 1.2V : : GPIO_1[28] : M10 : output : 3.3-V LVTTL : : 4 : Y VCCINT : M11 : power : : 1.2V : : @@ -260,14 +260,14 @@ GND : M13 : gnd : : VCCIO5 : M14 : power : : 3.3V : 5 : SW[3] : M15 : input : 3.3-V LVTTL : : 5 : Y GND+ : M16 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 3 : +DRAM_ADDR[11] : N1 : output : 3.3-V LVTTL : : 2 : Y +DRAM_ADDR[10] : N2 : output : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[14] : N3 : bidir : 3.3-V LVTTL : : 3 : Y VCCD_PLL1 : N4 : power : : 1.2V : : -RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : N6 : : : : 3 : +DRAM_ADDR[1] : N5 : output : 3.3-V LVTTL : : 3 : Y +DRAM_ADDR[2] : N6 : output : 3.3-V LVTTL : : 3 : Y GND : N7 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 3 : +DRAM_ADDR[6] : N8 : output : 3.3-V LVTTL : : 3 : Y GPIO_1[14] : N9 : output : 3.3-V LVTTL : : 4 : Y GND : N10 : gnd : : : : GPIO_1[15] : N11 : output : 3.3-V LVTTL : : 4 : Y @@ -276,14 +276,14 @@ VCCD_PLL4 : N13 : power : : 1.2V GPIO_1[27] : N14 : output : 3.3-V LVTTL : : 5 : Y GPIO_1[24] : N15 : output : 3.3-V LVTTL : : 5 : Y GPIO_1[23] : N16 : output : 3.3-V LVTTL : : 5 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 3 : +DRAM_ADDR[9] : P1 : output : 3.3-V LVTTL : : 2 : Y +DRAM_ADDR[0] : P2 : output : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[13] : P3 : bidir : 3.3-V LVTTL : : 3 : Y VCCIO3 : P4 : power : : 3.3V : 3 : GND : P5 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : P6 : : : : 3 : +DRAM_CS_N : P6 : output : 3.3-V LVTTL : : 3 : Y VCCIO3 : P7 : power : : 3.3V : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 3 : +DRAM_ADDR[4] : P8 : output : 3.3-V LVTTL : : 3 : Y GPIO_1[13] : P9 : output : 3.3-V LVTTL : : 4 : Y VCCIO4 : P10 : power : : 3.3V : 4 : GPIO_1[10] : P11 : output : 3.3-V LVTTL : : 4 : Y @@ -292,13 +292,13 @@ VCCIO4 : P13 : power : : 3.3V GPIO_1[25] : P14 : output : 3.3-V LVTTL : : 4 : Y GPIO_1[20] : P15 : output : 3.3-V LVTTL : : 5 : Y GPIO_1[21] : P16 : output : 3.3-V LVTTL : : 5 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : +DRAM_ADDR[8] : R1 : output : 3.3-V LVTTL : : 2 : Y GND : R2 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 3 : +DRAM_DQ[11] : R3 : bidir : 3.3-V LVTTL : : 3 : Y +DRAM_CLK : R4 : output : 3.3-V LVTTL : : 3 : Y +DRAM_DQ[12] : R5 : bidir : 3.3-V LVTTL : : 3 : Y +DRAM_DQM[0] : R6 : output : 3.3-V LVTTL : : 3 : Y +DRAM_DQ[7] : R7 : bidir : 3.3-V LVTTL : : 3 : Y CLOCK_50 : R8 : input : 3.3-V LVTTL : : 3 : Y GND+ : R9 : : : : 4 : GPIO_1[11] : R10 : output : 3.3-V LVTTL : : 4 : Y @@ -309,12 +309,12 @@ GPIO_1[22] : R14 : output : 3.3-V LVTTL : GND : R15 : gnd : : : : GPIO_1[18] : R16 : output : 3.3-V LVTTL : : 5 : Y VCCIO3 : T1 : power : : 3.3V : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 3 : +DRAM_DQ[9] : T2 : bidir : 3.3-V LVTTL : : 3 : Y +DRAM_DQ[10] : T3 : bidir : 3.3-V LVTTL : : 3 : Y +DRAM_DQ[8] : T4 : bidir : 3.3-V LVTTL : : 3 : Y +DRAM_DQM[1] : T5 : output : 3.3-V LVTTL : : 3 : Y +DRAM_ADDR[7] : T6 : output : 3.3-V LVTTL : : 3 : Y +DRAM_ADDR[5] : T7 : output : 3.3-V LVTTL : : 3 : Y SW[1] : T8 : input : 3.3-V LVTTL : : 3 : Y GND+ : T9 : : : : 4 : GPIO_1[8] : T10 : output : 3.3-V LVTTL : : 4 : Y diff --git a/output_files/spectrum.sof b/output_files/spectrum.sof index 7a2f56c..89c7aaf 100644 Binary files a/output_files/spectrum.sof and b/output_files/spectrum.sof differ diff --git a/output_files/spectrum.sta.rpt b/output_files/spectrum.sta.rpt index a84d05a..2fe65db 100644 --- a/output_files/spectrum.sta.rpt +++ b/output_files/spectrum.sta.rpt @@ -1,5 +1,5 @@ TimeQuest Timing Analyzer report for spectrum -Fri Apr 1 18:55:48 2022 +Sat Apr 2 14:51:17 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -22,96 +22,117 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 14. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' 15. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' 16. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' - 17. Slow 1200mV 85C Model Hold: 'CLOCK_50' + 17. Slow 1200mV 85C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' 18. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' 19. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' 20. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' - 21. Slow 1200mV 85C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 22. Slow 1200mV 85C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 23. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50' - 24. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' - 25. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 26. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' - 27. Setup Times - 28. Hold Times - 29. Clock to Output Times - 30. Minimum Clock to Output Times - 31. Propagation Delay - 32. Minimum Propagation Delay - 33. Slow 1200mV 85C Model Metastability Report - 34. Slow 1200mV 0C Model Fmax Summary - 35. Slow 1200mV 0C Model Setup Summary - 36. Slow 1200mV 0C Model Hold Summary - 37. Slow 1200mV 0C Model Recovery Summary - 38. Slow 1200mV 0C Model Removal Summary - 39. Slow 1200mV 0C Model Minimum Pulse Width Summary - 40. Slow 1200mV 0C Model Setup: 'CLOCK_50' - 41. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' - 42. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 43. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' - 44. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' - 45. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 46. Slow 1200mV 0C Model Hold: 'CLOCK_50' - 47. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' - 48. Slow 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 49. Slow 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 50. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' - 51. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' - 52. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 53. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' - 54. Setup Times - 55. Hold Times - 56. Clock to Output Times - 57. Minimum Clock to Output Times - 58. Propagation Delay - 59. Minimum Propagation Delay - 60. Slow 1200mV 0C Model Metastability Report - 61. Fast 1200mV 0C Model Setup Summary - 62. Fast 1200mV 0C Model Hold Summary - 63. Fast 1200mV 0C Model Recovery Summary - 64. Fast 1200mV 0C Model Removal Summary - 65. Fast 1200mV 0C Model Minimum Pulse Width Summary - 66. Fast 1200mV 0C Model Setup: 'CLOCK_50' - 67. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' - 68. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 69. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' - 70. Fast 1200mV 0C Model Hold: 'CLOCK_50' - 71. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' - 72. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 73. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' - 74. Fast 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 75. Fast 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 76. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' - 77. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' - 78. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 79. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' - 80. Setup Times - 81. Hold Times - 82. Clock to Output Times - 83. Minimum Clock to Output Times - 84. Propagation Delay - 85. Minimum Propagation Delay - 86. Fast 1200mV 0C Model Metastability Report - 87. Multicorner Timing Analysis Summary - 88. Setup Times - 89. Hold Times - 90. Clock to Output Times - 91. Minimum Clock to Output Times - 92. Propagation Delay - 93. Minimum Propagation Delay - 94. Board Trace Model Assignments - 95. Input Transition Times - 96. Signal Integrity Metrics (Slow 1200mv 0c Model) - 97. Signal Integrity Metrics (Slow 1200mv 85c Model) - 98. Signal Integrity Metrics (Fast 1200mv 0c Model) - 99. Setup Transfers -100. Hold Transfers -101. Recovery Transfers -102. Removal Transfers -103. Report TCCS -104. Report RSKM -105. Unconstrained Paths -106. TimeQuest Timing Analyzer Messages + 21. Slow 1200mV 85C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' + 22. Slow 1200mV 85C Model Hold: 'CLOCK_50' + 23. Slow 1200mV 85C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 24. Slow 1200mV 85C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 25. Slow 1200mV 85C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' + 26. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50' + 27. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 28. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 29. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' + 30. Setup Times + 31. Hold Times + 32. Clock to Output Times + 33. Minimum Clock to Output Times + 34. Propagation Delay + 35. Minimum Propagation Delay + 36. Output Enable Times + 37. Minimum Output Enable Times + 38. Output Disable Times + 39. Minimum Output Disable Times + 40. Slow 1200mV 85C Model Metastability Report + 41. Slow 1200mV 0C Model Fmax Summary + 42. Slow 1200mV 0C Model Setup Summary + 43. Slow 1200mV 0C Model Hold Summary + 44. Slow 1200mV 0C Model Recovery Summary + 45. Slow 1200mV 0C Model Removal Summary + 46. Slow 1200mV 0C Model Minimum Pulse Width Summary + 47. Slow 1200mV 0C Model Setup: 'CLOCK_50' + 48. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 49. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 50. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' + 51. Slow 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' + 52. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' + 53. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 54. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 55. Slow 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' + 56. Slow 1200mV 0C Model Hold: 'CLOCK_50' + 57. Slow 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 58. Slow 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 59. Slow 1200mV 0C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' + 60. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' + 61. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 62. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 63. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' + 64. Setup Times + 65. Hold Times + 66. Clock to Output Times + 67. Minimum Clock to Output Times + 68. Propagation Delay + 69. Minimum Propagation Delay + 70. Output Enable Times + 71. Minimum Output Enable Times + 72. Output Disable Times + 73. Minimum Output Disable Times + 74. Slow 1200mV 0C Model Metastability Report + 75. Fast 1200mV 0C Model Setup Summary + 76. Fast 1200mV 0C Model Hold Summary + 77. Fast 1200mV 0C Model Recovery Summary + 78. Fast 1200mV 0C Model Removal Summary + 79. Fast 1200mV 0C Model Minimum Pulse Width Summary + 80. Fast 1200mV 0C Model Setup: 'CLOCK_50' + 81. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 82. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 83. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' + 84. Fast 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' + 85. Fast 1200mV 0C Model Hold: 'CLOCK_50' + 86. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' + 87. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 88. Fast 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' + 89. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 90. Fast 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 91. Fast 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 92. Fast 1200mV 0C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' + 93. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' + 94. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 95. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 96. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' + 97. Setup Times + 98. Hold Times + 99. Clock to Output Times +100. Minimum Clock to Output Times +101. Propagation Delay +102. Minimum Propagation Delay +103. Output Enable Times +104. Minimum Output Enable Times +105. Output Disable Times +106. Minimum Output Disable Times +107. Fast 1200mV 0C Model Metastability Report +108. Multicorner Timing Analysis Summary +109. Setup Times +110. Hold Times +111. Clock to Output Times +112. Minimum Clock to Output Times +113. Propagation Delay +114. Minimum Propagation Delay +115. Board Trace Model Assignments +116. Input Transition Times +117. Signal Integrity Metrics (Slow 1200mv 0c Model) +118. Signal Integrity Metrics (Slow 1200mv 85c Model) +119. Signal Integrity Metrics (Fast 1200mv 0c Model) +120. Setup Transfers +121. Hold Transfers +122. Recovery Transfers +123. Removal Transfers +124. Report TCCS +125. Report RSKM +126. Unconstrained Paths +127. TimeQuest Timing Analyzer Messages @@ -163,7 +184,7 @@ Parallel compilation was disabled, but you have multiple processors available. E +--------------------------------------------------------------------------------+ SDC File Path : spectrum.sdc Status : OK -Read at : Fri Apr 1 18:55:45 2022 +Read at : Sat Apr 2 14:51:14 2022 +--------------------------------------------------------------------------------+ @@ -207,6 +228,42 @@ Master : Source : Targets : { CLOCK_50 } +Clock Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Type : Generated +Period : 10.000 +Frequency : 100.0 MHz +Rise : 0.000 +Fall : 5.000 +Duty Cycle : 50.00 +Divide by : 1 +Multiply by : 2 +Phase : +Offset : +Edge List : +Edge Shift : +Inverted : false +Master : CLOCK_50 +Source : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0] +Targets : { sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] } + +Clock Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] +Type : Generated +Period : 10.000 +Frequency : 100.0 MHz +Rise : 3.000 +Fall : 8.000 +Duty Cycle : 50.00 +Divide by : 1 +Multiply by : 2 +Phase : 108.0 +Offset : +Edge List : +Edge Shift : +Inverted : false +Master : CLOCK_50 +Source : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0] +Targets : { sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] } + Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Type : Generated Period : 39.716 @@ -267,22 +324,27 @@ Targets : { ula_|pll_|altpll_component|auto_generated|pll1|clk[2] } +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Fmax Summary ; +--------------------------------------------------------------------------------+ -Fmax : 49.07 MHz -Restricted Fmax : 49.07 MHz +Fmax : 48.03 MHz +Restricted Fmax : 48.03 MHz Clock Name : CLOCK_50 Note : -Fmax : 124.66 MHz -Restricted Fmax : 124.66 MHz +Fmax : 118.6 MHz +Restricted Fmax : 118.6 MHz Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Note : -Fmax : 161.45 MHz -Restricted Fmax : 161.45 MHz +Fmax : 153.92 MHz +Restricted Fmax : 153.92 MHz +Clock Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Note : + +Fmax : 163.48 MHz +Restricted Fmax : 163.48 MHz Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Note : -Fmax : 938.97 MHz +Fmax : 940.73 MHz Restricted Fmax : 500.0 MHz Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Note : limit due to minimum period restriction (tmin) @@ -301,20 +363,24 @@ HTML report is unavailable in plain text report export. ; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -18.123 -End Point TNS : -549.338 +Slack : -18.571 +End Point TNS : -821.372 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Slack : -7.533 -End Point TNS : -284.813 +Slack : -7.747 +End Point TNS : -287.138 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : -4.740 -End Point TNS : -42.810 +Slack : -4.731 +End Point TNS : -41.432 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Slack : -2.914 -End Point TNS : -2.914 +Slack : -2.915 +End Point TNS : -2.915 + +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Slack : 3.503 +End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -322,21 +388,25 @@ End Point TNS : -2.914 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold Summary ; +--------------------------------------------------------------------------------+ -Clock : CLOCK_50 -Slack : 0.210 -End Point TNS : 0.000 - Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Slack : 0.342 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 0.344 +Slack : 0.342 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Slack : 0.357 End Point TNS : 0.000 + +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Slack : 0.359 +End Point TNS : 0.000 + +Clock : CLOCK_50 +Slack : 0.373 +End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -345,8 +415,8 @@ End Point TNS : 0.000 ; Slow 1200mV 85C Model Recovery Summary ; +--------------------------------------------------------------------------------+ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : -6.223 -End Point TNS : -459.348 +Slack : -6.212 +End Point TNS : -460.730 +--------------------------------------------------------------------------------+ @@ -355,7 +425,7 @@ End Point TNS : -459.348 ; Slow 1200mV 85C Model Removal Summary ; +--------------------------------------------------------------------------------+ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 3.698 +Slack : 3.666 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -364,6 +434,10 @@ End Point TNS : 0.000 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +--------------------------------------------------------------------------------+ +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Slack : 4.752 +End Point TNS : 0.000 + Clock : CLOCK_50 Slack : 9.488 End Point TNS : 0.000 @@ -373,7 +447,7 @@ Slack : 19.602 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 20.595 +Slack : 20.597 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] @@ -386,905 +460,905 @@ End Point TNS : 0.000 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -18.123 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 7.954 - -Slack : -18.117 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 7.948 - -Slack : -18.075 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 7.905 - -Slack : -18.071 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 7.902 - -Slack : -18.067 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 7.897 - -Slack : -18.052 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 7.883 - -Slack : -18.038 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 7.868 - -Slack : -17.978 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 7.809 - -Slack : -17.977 -From Node : ula:ula_|video:video_|bits[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.803 - -Slack : -17.957 +Slack : -18.571 From Node : ula:ula_|video:video_|vga_hc[1] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.783 +Clock Skew : -0.252 +Data Delay : 8.393 -Slack : -17.929 -From Node : ula:ula_|video:video_|vga_vc[6] +Slack : -18.455 +From Node : ula:ula_|video:video_|vga_vc[9] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 7.760 +Clock Skew : -0.252 +Data Delay : 8.277 -Slack : -17.924 -From Node : ula:ula_|video:video_|vga_vc[4] +Slack : -18.451 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 8.292 + +Slack : -18.439 +From Node : ula:ula_|video:video_|bits[5] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 7.755 +Clock Skew : -0.252 +Data Delay : 8.261 -Slack : -17.912 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 -To Node : GPIO_1[20] +Slack : -18.432 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 +To Node : DRAM_DQ[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.514 -Data Delay : 7.472 +Clock Skew : -0.505 +Data Delay : 8.001 -Slack : -17.909 +Slack : -18.426 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 8.267 + +Slack : -18.398 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 7.956 + +Slack : -18.391 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 7.950 + +Slack : -18.389 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 -To Node : GPIO_1[22] +To Node : DRAM_DQ[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.509 -Data Delay : 7.474 +Data Delay : 7.954 -Slack : -17.904 -From Node : ula:ula_|video:video_|vga_vc[7] +Slack : -18.372 +From Node : ula:ula_|video:video_|vga_hc[2] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 7.735 +Clock Skew : -0.252 +Data Delay : 8.194 -Slack : -17.882 +Slack : -18.364 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.252 +Data Delay : 8.186 + +Slack : -18.356 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.252 +Data Delay : 8.178 + +Slack : -18.353 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 8.194 + +Slack : -18.347 From Node : ula:ula_|video:video_|vga_hc[5] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 7.712 +Clock Skew : -0.252 +Data Delay : 8.169 -Slack : -17.861 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 7.692 - -Slack : -17.852 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.241 -Data Delay : 7.685 - -Slack : -17.852 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.242 -Data Delay : 7.684 - -Slack : -17.810 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.518 -Data Delay : 7.366 - -Slack : -17.798 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.241 -Data Delay : 7.631 - -Slack : -17.790 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 7.621 - -Slack : -17.747 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 7.297 - -Slack : -17.716 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 7.266 - -Slack : -17.709 -From Node : ula:ula_|video:video_|bits[1] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.535 - -Slack : -17.708 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.247 -Data Delay : 7.535 - -Slack : -17.700 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.241 -Data Delay : 7.533 - -Slack : -17.676 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 7.506 - -Slack : -17.657 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 7.487 - -Slack : -17.622 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 -To Node : GPIO_1[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.514 -Data Delay : 7.182 - -Slack : -17.617 -From Node : ula:ula_|video:video_|bits[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.443 - -Slack : -17.612 +Slack : -18.345 From Node : ula:ula_|video:video_|frame[4] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.249 -Data Delay : 7.437 +Data Delay : 8.170 -Slack : -17.578 -From Node : ula:ula_|video:video_|bits[7] +Slack : -18.344 +From Node : ula:ula_|video:video_|vga_hc[7] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.404 +Clock Skew : -0.252 +Data Delay : 8.166 -Slack : -17.576 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +Slack : -18.335 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.252 +Data Delay : 8.157 + +Slack : -18.314 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.252 +Data Delay : 8.136 + +Slack : -18.303 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.515 -Data Delay : 7.135 +Clock Skew : -0.233 +Data Delay : 8.144 -Slack : -17.567 +Slack : -18.300 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.252 +Data Delay : 8.122 + +Slack : -18.275 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.505 -Data Delay : 7.136 +Clock Skew : -0.516 +Data Delay : 7.833 -Slack : -17.554 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 -To Node : GPIO_1[20] +Slack : -18.250 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +To Node : DRAM_DQ[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.515 -Data Delay : 7.113 +Clock Skew : -0.516 +Data Delay : 7.808 -Slack : -17.492 +Slack : -18.211 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.252 +Data Delay : 8.033 + +Slack : -18.206 +From Node : ula:ula_|video:video_|bits[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.252 +Data Delay : 8.028 + +Slack : -18.202 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.252 +Data Delay : 8.024 + +Slack : -18.186 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.520 -Data Delay : 7.046 +Clock Skew : -0.505 +Data Delay : 7.755 -Slack : -17.483 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 7.041 - -Slack : -17.477 -From Node : ula:ula_|video:video_|bits[2] +Slack : -18.180 +From Node : ula:ula_|video:video_|vga_vc[3] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.303 +Clock Skew : -0.252 +Data Delay : 8.002 -Slack : -17.475 +Slack : -18.178 +From Node : ula:ula_|video:video_|bits[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.252 +Data Delay : 8.000 + +Slack : -18.177 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 8.018 + +Slack : -18.155 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.252 +Data Delay : 7.977 + +Slack : -18.153 +From Node : ula:ula_|video:video_|bits[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.252 +Data Delay : 7.975 + +Slack : -18.147 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.514 +Data Delay : 7.707 + +Slack : -18.145 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.518 -Data Delay : 7.031 - -Slack : -17.460 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[21] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.241 -Data Delay : 7.293 - -Slack : -17.458 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.511 -Data Delay : 7.021 - -Slack : -17.448 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.241 -Data Delay : 7.281 - -Slack : -17.445 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.242 -Data Delay : 7.277 - -Slack : -17.442 -From Node : ula:ula_|video:video_|bits[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.268 - -Slack : -17.441 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[21] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.242 -Data Delay : 7.273 - -Slack : -17.429 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 -To Node : GPIO_1[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.523 -Data Delay : 6.980 - -Slack : -17.425 -From Node : ula:ula_|video:video_|attr[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.251 - -Slack : -17.393 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 -To Node : GPIO_1[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 6.943 - -Slack : -17.368 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 6.918 - -Slack : -17.351 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.523 -Data Delay : 6.902 - -Slack : -17.350 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.241 -Data Delay : 7.183 - -Slack : -17.328 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.511 -Data Delay : 6.891 - -Slack : -17.322 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 Clock Skew : -0.515 -Data Delay : 6.881 +Data Delay : 7.704 -Slack : -17.316 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 -To Node : GPIO_1[21] +Slack : -18.143 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.507 -Data Delay : 6.883 +Clock Skew : -0.509 +Data Delay : 7.708 -Slack : -17.314 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[18] +Slack : -18.107 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.241 -Data Delay : 7.147 +Clock Skew : -0.233 +Data Delay : 7.948 -Slack : -17.300 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 -To Node : GPIO_1[16] +Slack : -18.102 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +To Node : DRAM_DQ[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 6.850 +Clock Skew : -0.509 +Data Delay : 7.667 -Slack : -17.296 -From Node : ula:ula_|video:video_|vga_hc[3] +Slack : -18.073 +From Node : ula:ula_|video:video_|vga_vc[5] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.122 +Clock Skew : -0.252 +Data Delay : 7.895 -Slack : -17.274 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.242 -Data Delay : 7.106 - -Slack : -17.267 -From Node : ula:ula_|video:video_|bits[4] +Slack : -18.071 +From Node : ula:ula_|video:video_|vga_vc[0] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.093 +Clock Skew : -0.252 +Data Delay : 7.893 -Slack : -17.247 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 -To Node : GPIO_1[18] +Slack : -18.024 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.513 -Data Delay : 6.808 +Clock Skew : -0.514 +Data Delay : 7.584 -Slack : -17.239 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[16] +Slack : -18.018 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +To Node : DRAM_DQ[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.242 -Data Delay : 7.071 +Clock Skew : -0.514 +Data Delay : 7.578 -Slack : -17.229 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[23] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.241 -Data Delay : 7.062 - -Slack : -17.199 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.522 -Data Delay : 6.751 - -Slack : -17.188 +Slack : -18.010 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 -To Node : GPIO_1[21] +To Node : DRAM_DQ[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.507 -Data Delay : 6.755 +Clock Skew : -0.518 +Data Delay : 7.566 -Slack : -17.162 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 -To Node : GPIO_1[18] +Slack : -18.004 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.516 -Data Delay : 6.720 +Data Delay : 7.562 -Slack : -17.128 -From Node : ula:ula_|video:video_|bits[0] +Slack : -18.001 +From Node : ula:ula_|video:video_|vga_hc[8] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 6.954 +Clock Skew : -0.252 +Data Delay : 7.823 -Slack : -17.120 +Slack : -17.982 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.514 +Data Delay : 7.542 + +Slack : -17.978 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.819 + +Slack : -17.976 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.509 +Data Delay : 7.541 + +Slack : -17.956 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.514 -Data Delay : 6.680 +Data Delay : 7.516 -Slack : -17.110 +Slack : -17.947 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.514 +Data Delay : 7.507 + +Slack : -17.932 +From Node : ula:ula_|video:video_|vga_hc[9] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.252 +Data Delay : 7.754 + +Slack : -17.932 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.514 +Data Delay : 7.492 + +Slack : -17.925 +From Node : ula:ula_|video:video_|bits[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.252 +Data Delay : 7.747 + +Slack : -17.903 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.744 + +Slack : -17.890 +From Node : ula:ula_|video:video_|bits[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.252 +Data Delay : 7.712 + +Slack : -17.876 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.520 +Data Delay : 7.430 + +Slack : -17.873 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 7.423 + +Slack : -17.872 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 7.431 + +Slack : -17.864 +From Node : ula:ula_|video:video_|attr[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.252 +Data Delay : 7.686 + +Slack : -17.859 +From Node : ula:ula_|video:video_|bits[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.252 +Data Delay : 7.681 + +Slack : -17.850 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 7.400 + +Slack : -17.841 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.682 + +Slack : -17.827 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.668 + +Slack : -17.807 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 7.366 + +Slack : -17.805 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.513 +Data Delay : 7.366 + +Slack : -17.804 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.645 + +Slack : -17.794 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 7.344 + +Slack : -17.788 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 7.338 + +Slack : -17.757 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 7.316 + +Slack : -17.746 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 7.305 + +Slack : -17.732 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 7.282 + +Slack : -17.731 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.572 + +Slack : -17.706 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.547 + +Slack : -17.698 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.539 + +Slack : -17.680 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.521 + +Slack : -17.670 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 7.220 + +Slack : -17.660 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.511 +Data Delay : 7.223 + +Slack : -17.659 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.500 + +Slack : -17.636 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.242 -Data Delay : 6.942 +Clock Skew : -0.233 +Data Delay : 7.477 -Slack : -17.095 +Slack : -17.620 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.514 +Data Delay : 7.180 + +Slack : -17.610 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.511 +Data Delay : 7.173 + +Slack : -17.600 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 7.159 + +Slack : -17.593 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.511 +Data Delay : 7.156 + +Slack : -17.587 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 7.146 + +Slack : -17.580 +From Node : ula:ula_|video:video_|bits[0] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.252 +Data Delay : 7.402 + +Slack : -17.569 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 To Node : GPIO_1[21] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.519 -Data Delay : 6.650 +Clock Skew : -0.518 +Data Delay : 7.125 -Slack : -17.083 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 -To Node : GPIO_1[23] +Slack : -17.563 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : DRAM_DQ[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.522 -Data Delay : 6.635 +Clock Skew : -0.523 +Data Delay : 7.114 -Slack : -17.035 +Slack : -17.546 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.387 + +Slack : -17.538 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 7.088 + +Slack : -17.528 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.513 +Data Delay : 7.089 + +Slack : -17.490 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.507 +Data Delay : 7.057 + +Slack : -17.487 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 7.045 + +Slack : -17.486 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.327 + +Slack : -17.477 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.318 + +Slack : -17.452 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.293 + +Slack : -17.450 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 7.009 + +Slack : -17.443 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.233 +Data Delay : 7.284 + +Slack : -17.435 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 To Node : GPIO_1[21] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.509 -Data Delay : 6.600 - -Slack : -16.837 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 -To Node : GPIO_1[23] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 Clock Skew : -0.520 -Data Delay : 6.391 +Data Delay : 6.989 -Slack : -16.833 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 -To Node : GPIO_1[23] +Slack : -17.430 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.513 -Data Delay : 6.394 +Clock Skew : -0.515 +Data Delay : 6.989 -Slack : -16.800 -From Node : ula:ula_|video:video_|attr[0] -To Node : VGA_B[0] +Slack : -17.401 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : DRAM_DQ[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.247 -Data Delay : 6.627 +Clock Skew : -0.524 +Data Delay : 6.951 -Slack : -16.774 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[23] +Slack : -17.399 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +To Node : GPIO_1[17] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.242 -Data Delay : 6.606 +Clock Skew : -0.511 +Data Delay : 6.962 -Slack : -16.762 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_B[3] +Slack : -17.396 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.593 - -Slack : -16.756 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.587 - -Slack : -16.714 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 6.544 - -Slack : -16.710 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.541 - -Slack : -16.706 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 6.536 - -Slack : -16.702 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 -To Node : GPIO_1[23] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 6.260 - -Slack : -16.691 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.522 - -Slack : -16.677 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 6.507 - -Slack : -16.617 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.448 - -Slack : -16.616 -From Node : ula:ula_|video:video_|bits[5] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 6.442 - -Slack : -16.596 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 6.422 - -Slack : -16.590 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.421 - -Slack : -16.589 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.420 - -Slack : -16.568 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.399 - -Slack : -16.567 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 6.397 - -Slack : -16.563 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.394 - -Slack : -16.549 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 6.379 - -Slack : -16.543 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.374 - -Slack : -16.523 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.354 - -Slack : -16.521 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 6.351 - -Slack : -16.500 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.331 - -Slack : -16.495 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.326 - -Slack : -16.484 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : VGA_G[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 6.314 - -Slack : -16.460 -From Node : ula:ula_|video:video_|attr[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 6.286 +Clock Skew : -0.233 +Data Delay : 7.237 +--------------------------------------------------------------------------------+ @@ -1292,905 +1366,905 @@ Data Delay : 6.286 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : -7.533 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.293 -Data Delay : 5.348 - -Slack : -7.427 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.284 -Data Delay : 5.251 - -Slack : -7.365 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.290 -Data Delay : 5.183 - -Slack : -7.307 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.284 -Data Delay : 5.131 - -Slack : -7.245 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.245 -Data Delay : 5.108 - -Slack : -7.233 +Slack : -7.747 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.307 -Data Delay : 5.034 - -Slack : -7.228 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.251 -Data Delay : 5.085 - -Slack : -7.218 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.284 -Data Delay : 5.042 - -Slack : -7.217 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.283 -Data Delay : 5.042 - -Slack : -7.215 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.263 -Data Delay : 5.060 - -Slack : -7.206 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.299 -Data Delay : 5.015 - -Slack : -7.130 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.245 -Data Delay : 4.993 - -Slack : -7.122 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.282 -Data Delay : 4.948 - -Slack : -7.122 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.242 -Data Delay : 4.988 - -Slack : -7.092 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.244 -Data Delay : 4.956 - -Slack : -7.063 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.292 -Data Delay : 4.879 - -Slack : -7.057 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 Clock Skew : -2.297 -Data Delay : 4.868 +Data Delay : 5.558 -Slack : -7.054 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.299 -Data Delay : 4.863 - -Slack : -7.052 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.257 -Data Delay : 4.903 - -Slack : -7.042 +Slack : -7.745 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.299 -Data Delay : 4.851 - -Slack : -7.025 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.249 -Data Delay : 4.884 - -Slack : -7.023 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.283 -Data Delay : 4.848 - -Slack : -7.020 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.262 -Data Delay : 4.866 - -Slack : -7.020 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.281 -Data Delay : 4.847 - -Slack : -7.017 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.260 -Data Delay : 4.865 - -Slack : -7.009 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.285 -Data Delay : 4.832 - -Slack : -7.002 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.242 -Data Delay : 4.868 - -Slack : -6.982 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.295 -Data Delay : 4.795 - -Slack : -6.955 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.287 -Data Delay : 4.776 - -Slack : -6.943 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.009 -Data Delay : 5.042 - -Slack : -6.934 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.254 -Data Delay : 4.788 - -Slack : -6.930 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.283 -Data Delay : 4.755 - -Slack : -6.927 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.274 -Data Delay : 4.761 - -Slack : -6.927 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.276 -Data Delay : 4.759 - -Slack : -6.914 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.283 -Data Delay : 4.739 - -Slack : -6.912 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.241 -Data Delay : 4.779 - -Slack : -6.876 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.247 -Data Delay : 4.737 - -Slack : -6.862 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.245 -Data Delay : 4.725 - -Slack : -6.861 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.249 -Data Delay : 4.720 - -Slack : -6.857 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.260 -Data Delay : 4.705 - -Slack : -6.837 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.000 -Data Delay : 4.945 - -Slack : -6.836 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.267 -Data Delay : 4.677 - -Slack : -6.834 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.289 -Data Delay : 4.653 - -Slack : -6.811 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.291 -Data Delay : 4.628 - -Slack : -6.810 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.271 -Data Delay : 4.647 - -Slack : -6.806 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.285 -Data Delay : 4.629 - -Slack : -6.804 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.240 -Data Delay : 4.672 - -Slack : -6.798 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.253 -Data Delay : 4.653 - -Slack : -6.792 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.241 -Data Delay : 4.659 - -Slack : -6.791 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.287 -Data Delay : 4.612 - -Slack : -6.789 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.232 -Data Delay : 4.665 - -Slack : -6.789 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.234 -Data Delay : 4.663 - -Slack : -6.781 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.253 -Data Delay : 4.636 - -Slack : -6.770 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.269 -Data Delay : 4.609 - -Slack : -6.768 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.275 -Data Delay : 4.601 - -Slack : -6.765 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.254 -Data Delay : 4.619 - -Slack : -6.761 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.286 -Data Delay : 4.583 - -Slack : -6.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.293 -Data Delay : 4.571 - -Slack : -6.756 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.999 -Data Delay : 4.865 - -Slack : -6.751 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.271 -Data Delay : 4.588 - -Slack : -6.748 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.257 -Data Delay : 4.599 - -Slack : -6.745 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.248 -Data Delay : 4.605 - -Slack : -6.745 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.250 -Data Delay : 4.603 - -Slack : -6.741 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.285 -Data Delay : 4.564 - -Slack : -6.739 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.012 -Data Delay : 4.835 - -Slack : -6.737 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.292 -Data Delay : 4.553 - -Slack : -6.727 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.292 -Data Delay : 4.543 - -Slack : -6.720 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.281 -Data Delay : 4.547 - -Slack : -6.717 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.000 -Data Delay : 4.825 - -Slack : -6.714 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.244 -Data Delay : 4.578 - -Slack : -6.714 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.297 -Data Delay : 4.525 - -Slack : -6.693 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.009 -Data Delay : 4.792 - -Slack : -6.692 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.244 -Data Delay : 4.556 - -Slack : -6.689 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.239 -Data Delay : 4.558 - -Slack : -6.683 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.280 -Data Delay : 4.511 - -Slack : -6.681 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 Clock Skew : -2.302 -Data Delay : 4.487 +Data Delay : 5.551 -Slack : -6.678 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.293 -Data Delay : 4.493 - -Slack : -6.678 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.295 -Data Delay : 4.491 - -Slack : -6.674 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.295 -Data Delay : 4.487 - -Slack : -6.658 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.261 -Data Delay : 4.505 - -Slack : -6.655 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.297 -Data Delay : 4.466 - -Slack : -6.646 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.283 -Data Delay : 4.471 - -Slack : -6.641 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.266 -Data Delay : 4.483 - -Slack : -6.638 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.264 -Data Delay : 4.482 - -Slack : -6.629 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.280 -Data Delay : 4.457 - -Slack : -6.629 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +Slack : -7.636 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.264 -Data Delay : 4.473 +Clock Skew : -2.249 +Data Delay : 5.495 -Slack : -6.627 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Slack : -7.634 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.999 -Data Delay : 4.736 +Clock Skew : -2.254 +Data Delay : 5.488 -Slack : -6.620 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.243 -Data Delay : 4.485 - -Slack : -6.614 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.272 -Data Delay : 4.450 - -Slack : -6.604 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.279 -Data Delay : 4.433 - -Slack : -6.602 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.256 -Data Delay : 4.454 - -Slack : -6.591 +Slack : -7.563 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.281 -Data Delay : 4.418 +Clock Skew : -2.298 +Data Delay : 5.373 -Slack : -6.588 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Slack : -7.492 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.278 -Data Delay : 4.418 +Clock Skew : -2.297 +Data Delay : 5.303 -Slack : -6.573 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +Slack : -7.475 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.287 +Data Delay : 5.296 + +Slack : -7.464 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.305 +Data Delay : 5.267 + +Slack : -7.437 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.254 -Data Delay : 4.427 +Clock Skew : -2.299 +Data Delay : 5.246 -Slack : -6.572 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Slack : -7.436 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.244 -Data Delay : 4.436 +Clock Skew : -2.279 +Data Delay : 5.265 -Slack : -6.561 +Slack : -7.401 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.291 +Data Delay : 5.218 + +Slack : -7.381 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.281 +Data Delay : 5.208 + +Slack : -7.356 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.243 -Data Delay : 4.426 +Clock Skew : -2.249 +Data Delay : 5.215 -Slack : -6.546 +Slack : -7.345 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.302 +Data Delay : 5.151 + +Slack : -7.333 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.291 +Data Delay : 5.150 + +Slack : -7.320 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.292 -Data Delay : 4.362 +Clock Skew : -2.302 +Data Delay : 5.126 -Slack : -6.533 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +Slack : -7.316 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.299 +Data Delay : 5.125 + +Slack : -7.296 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.295 +Data Delay : 5.109 + +Slack : -7.289 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.284 +Data Delay : 5.113 + +Slack : -7.233 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.289 +Data Delay : 5.052 + +Slack : -7.232 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.252 -Data Delay : 4.389 +Clock Skew : -2.243 +Data Delay : 5.097 -Slack : -6.514 +Slack : -7.222 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.243 +Data Delay : 5.087 + +Slack : -7.177 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.245 +Data Delay : 5.040 + +Slack : -7.165 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.305 +Data Delay : 4.968 + +Slack : -7.163 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.263 +Data Delay : 5.008 + +Slack : -7.159 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.293 +Data Delay : 4.974 + +Slack : -7.148 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.297 +Data Delay : 4.959 + +Slack : -7.147 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.283 +Data Delay : 4.972 + +Slack : -7.143 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.302 +Data Delay : 4.949 + +Slack : -7.136 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.293 +Data Delay : 4.951 + +Slack : -7.117 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.292 +Data Delay : 4.933 + +Slack : -7.103 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.275 +Data Delay : 4.936 + +Slack : -7.093 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.254 +Data Delay : 4.947 + +Slack : -7.091 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.290 +Data Delay : 4.909 + +Slack : -7.085 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.248 +Data Delay : 4.945 + +Slack : -7.072 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.290 +Data Delay : 4.890 + +Slack : -7.066 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.292 +Data Delay : 4.882 + +Slack : -7.062 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.247 +Data Delay : 4.923 + +Slack : -7.059 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.293 +Data Delay : 4.874 + +Slack : -7.038 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.247 +Data Delay : 4.899 + +Slack : -7.037 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.300 +Data Delay : 4.845 + +Slack : -7.020 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.296 +Data Delay : 4.832 + +Slack : -7.018 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.299 +Data Delay : 4.827 + +Slack : -7.015 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.288 +Data Delay : 4.835 + +Slack : -7.006 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.242 +Data Delay : 4.872 + +Slack : -6.994 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.296 +Data Delay : 4.806 + +Slack : -6.987 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.291 +Data Delay : 4.804 + +Slack : -6.984 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.271 +Data Delay : 4.821 + +Slack : -6.978 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.281 +Data Delay : 4.805 + +Slack : -6.978 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.243 -Data Delay : 4.379 +Clock Skew : -2.260 +Data Delay : 4.826 -Slack : -6.514 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Slack : -6.960 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.294 +Data Delay : 4.774 + +Slack : -6.960 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.300 +Data Delay : 4.768 + +Slack : -6.959 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.256 +Data Delay : 4.811 + +Slack : -6.955 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.244 +Data Delay : 4.819 + +Slack : -6.953 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 Clock Skew : -2.254 -Data Delay : 4.368 +Data Delay : 4.807 + +Slack : -6.953 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.289 +Data Delay : 4.772 + +Slack : -6.945 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.004 +Data Delay : 5.049 + +Slack : -6.929 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.244 +Data Delay : 4.793 + +Slack : -6.919 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.252 +Data Delay : 4.775 + +Slack : -6.917 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.293 +Data Delay : 4.732 + +Slack : -6.914 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.262 +Data Delay : 4.760 + +Slack : -6.910 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.243 +Data Delay : 4.775 + +Slack : -6.909 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.251 +Data Delay : 4.766 + +Slack : -6.899 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.239 +Data Delay : 4.768 + +Slack : -6.895 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.290 +Data Delay : 4.713 + +Slack : -6.893 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.268 +Data Delay : 4.733 + +Slack : -6.886 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.285 +Data Delay : 4.709 + +Slack : -6.860 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.284 +Data Delay : 4.684 + +Slack : -6.856 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.252 +Data Delay : 4.712 + +Slack : -6.854 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.257 +Data Delay : 4.705 + +Slack : -6.852 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.244 +Data Delay : 4.716 + +Slack : -6.852 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.294 +Data Delay : 4.666 + +Slack : -6.851 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.245 +Data Delay : 4.714 + +Slack : -6.836 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.284 +Data Delay : 4.660 + +Slack : -6.829 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.242 +Data Delay : 4.695 + +Slack : -6.825 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.234 +Data Delay : 4.699 + +Slack : -6.824 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.292 +Data Delay : 4.640 + +Slack : -6.824 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.259 +Data Delay : 4.673 + +Slack : -6.822 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.297 +Data Delay : 4.633 + +Slack : -6.807 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.280 +Data Delay : 4.635 + +Slack : -6.783 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.280 +Data Delay : 4.611 + +Slack : -6.779 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.266 +Data Delay : 4.621 + +Slack : -6.770 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.236 +Data Delay : 4.642 + +Slack : -6.757 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.293 +Data Delay : 4.572 + +Slack : -6.723 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.252 +Data Delay : 4.579 + +Slack : -6.709 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.257 +Data Delay : 4.560 + +Slack : -6.707 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.293 +Data Delay : 4.522 + +Slack : -6.705 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.255 +Data Delay : 4.558 + +Slack : -6.704 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.289 +Data Delay : 4.523 + +Slack : -6.703 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.264 +Data Delay : 4.547 + +Slack : -6.678 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.239 +Data Delay : 4.547 + +Slack : -6.655 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.243 +Data Delay : 4.520 + +Slack : -6.649 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.285 +Data Delay : 4.472 + +Slack : -6.642 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.251 +Data Delay : 4.499 + +Slack : -6.642 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.280 +Data Delay : 4.470 + +Slack : -6.633 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.255 +Data Delay : 4.486 + +Slack : -6.617 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.292 +Data Delay : 4.433 + +Slack : -6.608 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.243 +Data Delay : 4.473 + +Slack : -6.605 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.242 +Data Delay : 4.471 + +Slack : -6.597 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.265 +Data Delay : 4.440 +--------------------------------------------------------------------------------+ @@ -2198,905 +2272,905 @@ Data Delay : 4.368 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : -4.740 +Slack : -4.731 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.193 -Data Delay : 2.831 +Data Delay : 2.822 -Slack : -4.581 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 2.799 - -Slack : -4.581 +Slack : -4.573 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 2.799 +Data Delay : 2.791 -Slack : -4.362 +Slack : -4.573 From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 2.580 +Data Delay : 2.791 -Slack : -4.362 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 2.580 - -Slack : -4.362 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 2.580 - -Slack : -4.362 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 2.580 - -Slack : -4.362 +Slack : -4.102 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 2.580 +Clock Skew : 0.190 +Data Delay : 2.671 -Slack : -3.957 +Slack : -4.102 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 2.671 + +Slack : -4.102 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 2.671 + +Slack : -4.102 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 2.671 + +Slack : -4.102 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 2.671 + +Slack : -3.948 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 2.175 +Data Delay : 2.166 -Slack : -3.141 +Slack : -3.097 From Node : AUD_ADCDAT To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.170 -Data Delay : 1.690 +Clock Skew : 0.199 +Data Delay : 1.675 -Slack : 16.840 +Slack : 16.635 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.577 +Clock Skew : -0.432 +Data Delay : 3.779 -Slack : 16.845 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Slack : 16.649 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 +Clock Skew : -0.432 +Data Delay : 3.765 + +Slack : 16.792 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 3.622 + +Slack : 16.818 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.428 +Data Delay : 3.600 + +Slack : 16.818 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.428 +Data Delay : 3.600 + +Slack : 16.832 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.428 +Data Delay : 3.586 + +Slack : 16.832 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.428 +Data Delay : 3.586 + +Slack : 16.842 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 Data Delay : 3.572 -Slack : 16.978 +Slack : 16.842 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 3.572 + +Slack : 16.842 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 3.572 + +Slack : 16.842 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 3.572 + +Slack : 16.842 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 3.572 + +Slack : 16.851 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.439 +Clock Skew : -0.432 +Data Delay : 3.563 -Slack : 16.978 +Slack : 16.851 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.439 +Clock Skew : -0.432 +Data Delay : 3.563 -Slack : 16.983 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Slack : 16.856 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.434 +Clock Skew : -0.432 +Data Delay : 3.558 -Slack : 16.983 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.434 - -Slack : 16.986 +Slack : 16.856 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.431 +Clock Skew : -0.432 +Data Delay : 3.558 -Slack : 17.051 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.366 - -Slack : 17.051 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Slack : 16.856 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.366 +Clock Skew : -0.432 +Data Delay : 3.558 -Slack : 17.051 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Slack : 16.856 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.366 +Clock Skew : -0.432 +Data Delay : 3.558 -Slack : 17.051 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Slack : 16.856 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.366 +Clock Skew : -0.432 +Data Delay : 3.558 -Slack : 17.056 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.361 - -Slack : 17.056 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.361 - -Slack : 17.056 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.361 - -Slack : 17.056 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.361 - -Slack : 17.086 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.331 - -Slack : 17.117 +Slack : 16.865 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.300 +Clock Skew : -0.432 +Data Delay : 3.549 -Slack : 17.117 +Slack : 16.865 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.300 +Clock Skew : -0.432 +Data Delay : 3.549 -Slack : 17.140 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.277 - -Slack : 17.140 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.277 - -Slack : 17.145 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.272 - -Slack : 17.145 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.272 - -Slack : 17.159 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 3.256 - -Slack : 17.159 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 3.256 - -Slack : 17.164 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 3.251 - -Slack : 17.164 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 3.251 - -Slack : 17.189 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.228 - -Slack : 17.189 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.228 - -Slack : 17.189 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.228 - -Slack : 17.189 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.228 - -Slack : 17.224 +Slack : 16.889 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.193 - -Slack : 17.224 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.193 - -Slack : 17.256 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.161 - -Slack : 17.259 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.158 - -Slack : 17.259 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.158 - -Slack : 17.259 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.158 - -Slack : 17.259 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.158 - -Slack : 17.259 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.158 - -Slack : 17.264 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.153 - -Slack : 17.264 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.153 - -Slack : 17.264 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.153 - -Slack : 17.264 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.153 - -Slack : 17.264 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.153 - -Slack : 17.289 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.128 - -Slack : 17.289 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.128 - -Slack : 17.297 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.120 - -Slack : 17.297 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.120 - -Slack : 17.297 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.120 - -Slack : 17.297 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.120 - -Slack : 17.308 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 3.107 - -Slack : 17.308 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 3.107 - -Slack : 17.386 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.031 - -Slack : 17.386 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.031 - -Slack : 17.394 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.023 - -Slack : 17.394 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.023 - -Slack : 17.405 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 3.010 - -Slack : 17.405 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 3.010 - -Slack : 17.408 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.009 - -Slack : 17.408 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.009 - -Slack : 17.408 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.009 - -Slack : 17.408 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.009 - -Slack : 17.408 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.009 - -Slack : 17.432 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 2.983 +Clock Skew : -0.432 +Data Delay : 3.525 -Slack : 17.437 +Slack : 16.975 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 2.978 +Clock Skew : -0.428 +Data Delay : 3.443 -Slack : 17.467 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 16.975 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.428 +Data Delay : 3.443 + +Slack : 16.999 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.950 +Clock Skew : -0.432 +Data Delay : 3.415 -Slack : 17.467 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 16.999 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 3.415 + +Slack : 16.999 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.950 +Clock Skew : -0.432 +Data Delay : 3.415 -Slack : 17.467 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 16.999 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.950 +Clock Skew : -0.432 +Data Delay : 3.415 -Slack : 17.467 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 16.999 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.950 +Clock Skew : -0.432 +Data Delay : 3.415 -Slack : 17.501 +Slack : 17.004 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 3.410 + +Slack : 17.004 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 3.410 + +Slack : 17.072 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.428 +Data Delay : 3.346 + +Slack : 17.072 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.428 +Data Delay : 3.346 + +Slack : 17.096 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 3.318 + +Slack : 17.096 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 3.318 + +Slack : 17.096 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 3.318 + +Slack : 17.096 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 3.318 + +Slack : 17.096 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 3.318 + +Slack : 17.105 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 3.309 + +Slack : 17.105 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 3.309 + +Slack : 17.223 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.073 +Data Delay : 3.550 + +Slack : 17.237 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.073 +Data Delay : 3.536 + +Slack : 17.246 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 3.170 + +Slack : 17.246 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 3.170 + +Slack : 17.260 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 3.156 + +Slack : 17.260 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 3.156 + +Slack : 17.297 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 +Clock Skew : -0.432 +Data Delay : 3.117 + +Slack : 17.377 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.073 +Data Delay : 3.396 + +Slack : 17.399 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 3.015 + +Slack : 17.403 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 3.013 + +Slack : 17.403 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 3.013 + +Slack : 17.477 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.073 +Data Delay : 3.296 + +Slack : 17.480 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.428 +Data Delay : 2.938 + +Slack : 17.480 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.428 +Data Delay : 2.938 + +Slack : 17.500 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 Data Delay : 2.916 -Slack : 17.505 +Slack : 17.500 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.912 - -Slack : 17.505 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.912 - -Slack : 17.505 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.912 - -Slack : 17.505 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.912 - -Slack : 17.505 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.912 - -Slack : 17.556 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.861 - -Slack : 17.556 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.861 +Clock Skew : -0.430 +Data Delay : 2.916 -Slack : 17.563 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Slack : 17.504 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.076 -Data Delay : 3.207 +Clock Skew : -0.432 +Data Delay : 2.910 -Slack : 17.568 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Slack : 17.504 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.076 -Data Delay : 3.202 +Clock Skew : -0.432 +Data Delay : 2.910 -Slack : 17.575 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Slack : 17.504 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 2.840 +Clock Skew : -0.432 +Data Delay : 2.910 -Slack : 17.575 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Slack : 17.504 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 2.840 +Clock Skew : -0.432 +Data Delay : 2.910 -Slack : 17.581 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Slack : 17.504 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 2.834 +Clock Skew : -0.432 +Data Delay : 2.910 -Slack : 17.639 +Slack : 17.513 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.778 +Clock Skew : -0.432 +Data Delay : 2.901 -Slack : 17.639 +Slack : 17.513 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.778 +Clock Skew : -0.432 +Data Delay : 2.901 -Slack : 17.675 +Slack : 17.559 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 2.855 + +Slack : 17.559 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 2.855 + +Slack : 17.559 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 2.855 + +Slack : 17.559 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 2.855 + +Slack : 17.573 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 2.841 + +Slack : 17.573 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 2.841 + +Slack : 17.573 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 2.841 + +Slack : 17.573 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 2.841 + +Slack : 17.582 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.428 +Data Delay : 2.836 + +Slack : 17.582 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.428 +Data Delay : 2.836 + +Slack : 17.606 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 2.808 + +Slack : 17.606 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 2.808 + +Slack : 17.606 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 2.808 + +Slack : 17.606 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 2.808 + +Slack : 17.606 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 2.808 + +Slack : 17.615 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 2.799 + +Slack : 17.615 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 2.799 + +Slack : 17.623 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.742 +Clock Skew : -0.079 +Data Delay : 3.144 -Slack : 17.675 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.623 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.742 +Clock Skew : -0.079 +Data Delay : 3.144 -Slack : 17.675 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.623 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.742 +Clock Skew : -0.079 +Data Delay : 3.144 -Slack : 17.675 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.623 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.742 +Clock Skew : -0.079 +Data Delay : 3.144 -Slack : 17.675 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.623 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.742 +Clock Skew : -0.079 +Data Delay : 3.144 -Slack : 17.678 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 2.737 - -Slack : 17.710 +Slack : 17.637 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.076 -Data Delay : 3.060 +Clock Skew : -0.079 +Data Delay : 3.130 + +Slack : 17.637 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 3.130 + +Slack : 17.637 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 3.130 + +Slack : 17.637 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 3.130 + +Slack : 17.637 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 3.130 +--------------------------------------------------------------------------------+ @@ -3104,23 +3178,23 @@ Data Delay : 3.060 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; +--------------------------------------------------------------------------------+ -Slack : -2.914 +Slack : -2.915 From Node : SW[2] To Node : ula:ula_|clocks:clocks_|clk_cpu Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Relationship : 0.423 Clock Skew : 0.216 -Data Delay : 1.508 +Data Delay : 1.509 -Slack : 70.424 +Slack : 70.426 From Node : ula:ula_|clocks:clocks_|counter[0] To Node : ula:ula_|clocks:clocks_|clk_cpu Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Relationship : 71.489 Clock Skew : -0.078 -Data Delay : 0.982 +Data Delay : 0.980 Slack : 70.747 From Node : ula:ula_|clocks:clocks_|counter[0] @@ -3144,907 +3218,907 @@ Data Delay : 0.659 +--------------------------------------------------------------------------------+ -; Slow 1200mV 85C Model Hold: 'CLOCK_50' ; +; Slow 1200mV 85C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : 0.210 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.627 -Data Delay : 3.128 - -Slack : 0.266 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.628 -Data Delay : 3.185 - -Slack : 1.266 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.574 -Data Delay : 4.131 - -Slack : 1.277 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.575 -Data Delay : 4.143 - -Slack : 1.289 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.571 -Data Delay : 4.151 - -Slack : 1.310 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.163 - -Slack : 1.311 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.164 - -Slack : 1.311 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.574 -Data Delay : 4.176 - -Slack : 1.313 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.558 -Data Delay : 4.162 - -Slack : 1.318 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.565 -Data Delay : 4.174 - -Slack : 1.328 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.575 -Data Delay : 4.194 - -Slack : 1.332 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.185 - -Slack : 1.333 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.565 -Data Delay : 4.189 - -Slack : 1.370 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.565 -Data Delay : 4.226 - -Slack : 1.390 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.560 -Data Delay : 4.241 - -Slack : 1.397 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.557 -Data Delay : 4.245 - -Slack : 1.404 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.567 -Data Delay : 4.262 - -Slack : 1.406 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.554 -Data Delay : 4.251 - -Slack : 1.412 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.549 -Data Delay : 4.252 - -Slack : 1.417 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.553 -Data Delay : 4.261 - -Slack : 1.418 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.271 - -Slack : 1.422 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.275 - -Slack : 1.426 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.551 -Data Delay : 4.268 - -Slack : 1.427 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.280 - -Slack : 1.431 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.569 -Data Delay : 4.291 - -Slack : 1.438 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.291 - -Slack : 1.443 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.551 -Data Delay : 4.285 - -Slack : 1.446 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.560 -Data Delay : 4.297 - -Slack : 1.449 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.302 - -Slack : 1.455 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.560 -Data Delay : 4.306 - -Slack : 1.456 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.558 -Data Delay : 4.305 - -Slack : 1.460 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.553 -Data Delay : 4.304 - -Slack : 1.470 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.571 -Data Delay : 4.332 - -Slack : 1.472 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.551 -Data Delay : 4.314 - -Slack : 1.474 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.549 -Data Delay : 4.314 - -Slack : 1.474 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.553 -Data Delay : 4.318 - -Slack : 1.476 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.625 -Data Delay : 4.392 - -Slack : 1.477 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.554 -Data Delay : 4.322 - -Slack : 1.479 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.649 -Data Delay : 4.419 - -Slack : 1.483 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.336 - -Slack : 1.489 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.571 -Data Delay : 4.351 - -Slack : 1.492 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.633 -Data Delay : 4.416 - -Slack : 1.496 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.553 -Data Delay : 4.340 - -Slack : 1.496 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.555 -Data Delay : 4.342 - -Slack : 1.497 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.567 -Data Delay : 4.355 - -Slack : 1.499 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.557 -Data Delay : 4.347 - -Slack : 1.502 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.378 -Data Delay : 4.171 - -Slack : 1.505 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.358 - -Slack : 1.507 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.557 -Data Delay : 4.355 - -Slack : 1.508 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.569 -Data Delay : 4.368 - -Slack : 1.509 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.554 -Data Delay : 4.354 - -Slack : 1.512 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.365 - -Slack : 1.517 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.560 -Data Delay : 4.368 - -Slack : 1.517 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.554 -Data Delay : 4.362 - -Slack : 1.519 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.569 -Data Delay : 4.379 - -Slack : 1.522 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.632 -Data Delay : 4.445 - -Slack : 1.523 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.551 -Data Delay : 4.365 - -Slack : 1.525 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.551 -Data Delay : 4.367 - -Slack : 1.525 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.549 -Data Delay : 4.365 - -Slack : 1.525 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.565 -Data Delay : 4.381 - -Slack : 1.527 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.380 - -Slack : 1.528 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 4.382 - -Slack : 1.529 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.571 -Data Delay : 4.391 - -Slack : 1.531 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.645 -Data Delay : 4.467 - -Slack : 1.531 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.552 -Data Delay : 4.374 - -Slack : 1.532 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.557 -Data Delay : 4.380 - -Slack : 1.533 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.641 -Data Delay : 4.465 - -Slack : 1.533 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.558 -Data Delay : 4.382 - -Slack : 1.534 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.551 -Data Delay : 4.376 - -Slack : 1.534 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.552 -Data Delay : 4.377 - -Slack : 1.538 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.561 -Data Delay : 4.390 - -Slack : 1.540 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.554 -Data Delay : 4.385 - -Slack : 1.542 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.568 -Data Delay : 4.401 - -Slack : 1.543 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.549 -Data Delay : 4.383 - -Slack : 1.544 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.558 -Data Delay : 4.393 - -Slack : 1.545 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.574 -Data Delay : 4.410 - -Slack : 1.547 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.569 -Data Delay : 4.407 - -Slack : 1.547 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.550 -Data Delay : 4.388 - -Slack : 1.547 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.554 -Data Delay : 4.392 - -Slack : 1.548 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.558 -Data Delay : 4.397 - -Slack : 1.549 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.565 -Data Delay : 4.405 - -Slack : 1.549 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.558 -Data Delay : 4.398 - -Slack : 1.551 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 4.405 - -Slack : 1.553 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.574 -Data Delay : 4.418 - -Slack : 1.553 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.554 -Data Delay : 4.398 - -Slack : 1.555 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.575 -Data Delay : 4.421 - -Slack : 1.555 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 4.409 - -Slack : 1.557 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.549 -Data Delay : 4.397 - -Slack : 1.558 -From Node : ula:ula_|video:video_|vram_address[8] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 4.412 - -Slack : 1.562 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.550 -Data Delay : 4.403 - -Slack : 1.563 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.416 - -Slack : 1.565 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.557 -Data Delay : 4.413 - -Slack : 1.565 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.367 -Data Delay : 4.223 - -Slack : 1.567 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.558 -Data Delay : 4.416 - -Slack : 1.569 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.422 - -Slack : 1.572 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 4.429 - -Slack : 1.578 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 4.432 - -Slack : 1.578 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.431 - -Slack : 1.579 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.558 -Data Delay : 4.428 - -Slack : 1.580 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.554 -Data Delay : 4.425 +Slack : 3.503 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 6.345 + +Slack : 3.528 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 6.320 + +Slack : 3.604 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.060 +Data Delay : 6.234 + +Slack : 3.637 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 6.211 + +Slack : 3.639 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.060 +Data Delay : 6.199 + +Slack : 3.658 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.060 +Data Delay : 6.180 + +Slack : 3.662 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 6.186 + +Slack : 3.687 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.058 +Data Delay : 6.153 + +Slack : 3.712 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 6.136 + +Slack : 3.722 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.058 +Data Delay : 6.118 + +Slack : 3.741 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.058 +Data Delay : 6.099 + +Slack : 3.768 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.060 +Data Delay : 6.070 + +Slack : 3.768 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.060 +Data Delay : 6.070 + +Slack : 3.785 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.060 +Data Delay : 6.053 + +Slack : 3.804 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.060 +Data Delay : 6.034 + +Slack : 3.851 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.058 +Data Delay : 5.989 + +Slack : 3.851 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.058 +Data Delay : 5.989 + +Slack : 3.868 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.058 +Data Delay : 5.972 + +Slack : 3.887 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.058 +Data Delay : 5.953 + +Slack : 3.892 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.060 +Data Delay : 5.946 + +Slack : 3.936 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.060 +Data Delay : 5.902 + +Slack : 3.975 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.058 +Data Delay : 5.865 + +Slack : 3.988 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.057 +Data Delay : 5.853 + +Slack : 4.000 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.070 +Data Delay : 5.830 + +Slack : 4.007 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.060 +Data Delay : 5.831 + +Slack : 4.019 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.058 +Data Delay : 5.821 + +Slack : 4.023 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.057 +Data Delay : 5.818 + +Slack : 4.041 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.060 +Data Delay : 5.797 + +Slack : 4.042 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.057 +Data Delay : 5.799 + +Slack : 4.052 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.070 +Data Delay : 5.778 + +Slack : 4.055 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 5.790 + +Slack : 4.068 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.085 +Data Delay : 5.747 + +Slack : 4.080 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 5.765 + +Slack : 4.090 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.058 +Data Delay : 5.750 + +Slack : 4.103 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.085 +Data Delay : 5.712 + +Slack : 4.107 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.070 +Data Delay : 5.723 + +Slack : 4.122 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.085 +Data Delay : 5.693 + +Slack : 4.124 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.058 +Data Delay : 5.716 + +Slack : 4.130 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.048 +Data Delay : 5.720 + +Slack : 4.142 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 5.703 + +Slack : 4.152 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.057 +Data Delay : 5.689 + +Slack : 4.152 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.057 +Data Delay : 5.689 + +Slack : 4.164 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 5.679 + +Slack : 4.167 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.070 +Data Delay : 5.663 + +Slack : 4.167 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 5.678 + +Slack : 4.169 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.057 +Data Delay : 5.672 + +Slack : 4.176 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.078 +Data Delay : 5.646 + +Slack : 4.188 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.057 +Data Delay : 5.653 + +Slack : 4.189 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 5.656 + +Slack : 4.196 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.070 +Data Delay : 5.634 + +Slack : 4.214 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 5.631 + +Slack : 4.232 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.085 +Data Delay : 5.583 + +Slack : 4.232 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.085 +Data Delay : 5.583 + +Slack : 4.236 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.078 +Data Delay : 5.586 + +Slack : 4.241 +From Node : sdram_controller:sdram_|r.rd_pending +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.048 +Data Delay : 5.609 + +Slack : 4.243 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.094 +Data Delay : 5.563 + +Slack : 4.249 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.085 +Data Delay : 5.566 + +Slack : 4.258 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.094 +Data Delay : 5.548 + +Slack : 4.262 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.094 +Data Delay : 5.544 + +Slack : 4.264 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 5.581 + +Slack : 4.268 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.085 +Data Delay : 5.547 + +Slack : 4.276 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.057 +Data Delay : 5.565 + +Slack : 4.276 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 5.569 + +Slack : 4.283 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.078 +Data Delay : 5.539 + +Slack : 4.301 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 5.544 + +Slack : 4.320 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.052 +Data Delay : 5.526 + +Slack : 4.320 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.057 +Data Delay : 5.521 + +Slack : 4.343 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.078 +Data Delay : 5.479 + +Slack : 4.345 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.094 +Data Delay : 5.461 + +Slack : 4.345 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.052 +Data Delay : 5.501 + +Slack : 4.351 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 5.494 + +Slack : 4.353 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.094 +Data Delay : 5.453 + +Slack : 4.356 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.085 +Data Delay : 5.459 + +Slack : 4.361 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.056 +Data Delay : 5.481 + +Slack : 4.361 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.056 +Data Delay : 5.481 + +Slack : 4.361 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.058 +Data Delay : 5.479 + +Slack : 4.372 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.078 +Data Delay : 5.450 + +Slack : 4.389 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.068 +Data Delay : 5.443 + +Slack : 4.391 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.057 +Data Delay : 5.450 + +Slack : 4.400 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.085 +Data Delay : 5.415 + +Slack : 4.406 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.094 +Data Delay : 5.400 + +Slack : 4.423 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.070 +Data Delay : 5.407 + +Slack : 4.425 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.057 +Data Delay : 5.416 + +Slack : 4.426 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.052 +Data Delay : 5.420 + +Slack : 4.430 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.094 +Data Delay : 5.376 + +Slack : 4.454 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.052 +Data Delay : 5.392 + +Slack : 4.471 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.085 +Data Delay : 5.344 + +Slack : 4.479 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.052 +Data Delay : 5.367 + +Slack : 4.480 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.057 +Data Delay : 5.361 + +Slack : 4.502 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.060 +Data Delay : 5.336 + +Slack : 4.505 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.085 +Data Delay : 5.310 + +Slack : 4.507 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.094 +Data Delay : 5.299 + +Slack : 4.509 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.074 +Data Delay : 5.317 + +Slack : 4.512 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.094 +Data Delay : 5.294 + +Slack : 4.529 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.052 +Data Delay : 5.317 + +Slack : 4.535 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 5.309 + +Slack : 4.546 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.075 +Data Delay : 5.279 + +Slack : 4.573 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.087 +Data Delay : 5.240 + +Slack : 4.583 +From Node : sdram_controller:sdram_|r.rd_pending +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.051 +Data Delay : 5.264 + +Slack : 4.585 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.058 +Data Delay : 5.255 +--------------------------------------------------------------------------------+ @@ -4070,23 +4144,23 @@ Relationship : 0.000 Clock Skew : 0.078 Data Delay : 0.580 -Slack : 0.576 +Slack : 0.575 From Node : ula:ula_|clocks:clocks_|counter[0] To Node : ula:ula_|clocks:clocks_|clk_cpu Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Relationship : 0.000 Clock Skew : 0.078 -Data Delay : 0.811 +Data Delay : 0.810 -Slack : 1.324 +Slack : 1.322 From Node : SW[2] To Node : ula:ula_|clocks:clocks_|clk_cpu Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Relationship : -0.017 Clock Skew : 0.636 -Data Delay : 1.190 +Data Delay : 1.188 +--------------------------------------------------------------------------------+ @@ -4094,15 +4168,42 @@ Data Delay : 1.190 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 0.344 +Slack : 0.342 From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.076 +Clock Skew : 0.078 Data Delay : 0.577 +Slack : 0.342 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.577 + +Slack : 0.342 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.577 + +Slack : 0.345 +From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.580 + Slack : 0.345 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] @@ -4121,94 +4222,13 @@ Relationship : 0.000 Clock Skew : 0.077 Data Delay : 0.580 -Slack : 0.347 -From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.076 -Data Delay : 0.580 - Slack : 0.357 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.577 - -Slack : 0.357 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.577 - -Slack : 0.357 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.577 - -Slack : 0.357 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.577 - -Slack : 0.358 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.577 - -Slack : 0.358 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.577 - -Slack : 0.358 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.577 - -Slack : 0.358 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.577 - -Slack : 0.358 From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 +Clock Skew : 0.063 Data Delay : 0.577 Slack : 0.358 @@ -4230,22 +4250,58 @@ Clock Skew : 0.062 Data Delay : 0.577 Slack : 0.358 -From Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.577 -Slack : 0.361 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Slack : 0.358 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.580 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 Slack : 0.361 From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] @@ -4274,122 +4330,167 @@ Relationship : 0.000 Clock Skew : 0.078 Data Delay : 0.597 +Slack : 0.371 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.591 + +Slack : 0.372 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.592 + +Slack : 0.372 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.592 + +Slack : 0.373 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.593 + +Slack : 0.373 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.593 + +Slack : 0.373 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.593 + +Slack : 0.373 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.593 + Slack : 0.374 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.593 -Slack : 0.384 +Slack : 0.374 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.593 + +Slack : 0.375 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.595 + +Slack : 0.376 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.595 + +Slack : 0.386 From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.603 +Data Delay : 0.605 -Slack : 0.384 +Slack : 0.386 From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.603 - -Slack : 0.386 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 Data Delay : 0.605 -Slack : 0.399 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Slack : 0.439 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.618 +Clock Skew : 0.425 +Data Delay : 1.021 -Slack : 0.401 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Slack : 0.460 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.620 +Clock Skew : 0.436 +Data Delay : 1.053 -Slack : 0.463 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.698 - -Slack : 0.463 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.698 - -Slack : 0.464 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.699 - -Slack : 0.464 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.699 - -Slack : 0.466 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.701 - -Slack : 0.513 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.732 - -Slack : 0.515 +Slack : 0.510 From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.060 -Data Delay : 0.732 +Clock Skew : 0.062 +Data Delay : 0.729 + +Slack : 0.534 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.753 + +Slack : 0.542 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.762 Slack : 0.542 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] @@ -4401,35 +4502,89 @@ Clock Skew : 0.078 Data Delay : 0.777 Slack : 0.544 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.779 - -Slack : 0.547 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.078 -Data Delay : 0.782 +Data Delay : 0.779 -Slack : 0.548 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Slack : 0.545 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.106 -Data Delay : 0.811 +Clock Skew : 0.078 +Data Delay : 0.780 + +Slack : 0.550 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.769 + +Slack : 0.551 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.771 + +Slack : 0.552 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.772 + +Slack : 0.552 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.772 + +Slack : 0.553 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.773 + +Slack : 0.553 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.773 + +Slack : 0.553 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.772 Slack : 0.554 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -4437,16 +4592,7 @@ Clock Skew : 0.062 Data Delay : 0.773 Slack : 0.555 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.774 - -Slack : 0.555 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] @@ -4454,176 +4600,104 @@ Relationship : 0.000 Clock Skew : 0.078 Data Delay : 0.790 -Slack : 0.557 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.792 - Slack : 0.558 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.777 -Slack : 0.559 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.778 - -Slack : 0.559 +Slack : 0.561 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.778 +Data Delay : 0.780 -Slack : 0.561 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Slack : 0.562 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.780 +Data Delay : 0.781 -Slack : 0.564 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 0.782 - -Slack : 0.567 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Slack : 0.570 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.063 -Data Delay : 0.787 +Data Delay : 0.790 Slack : 0.574 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.809 - -Slack : 0.574 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.809 - -Slack : 0.575 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.810 - -Slack : 0.575 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.432 -Data Delay : 1.164 - -Slack : 0.576 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.811 - -Slack : 0.576 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.811 - -Slack : 0.576 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.811 - -Slack : 0.576 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.811 - -Slack : 0.577 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.812 - -Slack : 0.577 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.796 +Data Delay : 0.793 -Slack : 0.580 +Slack : 0.575 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.794 + +Slack : 0.582 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.801 + +Slack : 0.583 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.799 +Data Delay : 0.802 -Slack : 0.590 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Slack : 0.585 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.809 +Clock Skew : 0.077 +Data Delay : 0.819 + +Slack : 0.588 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.822 + +Slack : 0.589 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.823 Slack : 0.590 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data @@ -4631,197 +4705,224 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.809 +Clock Skew : 0.459 +Data Delay : 1.206 -Slack : 0.597 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.816 - -Slack : 0.604 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.823 - -Slack : 0.612 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.831 - -Slack : 0.613 +Slack : 0.591 From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.832 +Clock Skew : 0.077 +Data Delay : 0.825 -Slack : 0.627 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Slack : 0.607 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.846 +Data Delay : 0.826 -Slack : 0.636 +Slack : 0.610 From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.855 +Clock Skew : 0.077 +Data Delay : 0.844 -Slack : 0.639 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Slack : 0.697 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.457 +Data Delay : 1.311 + +Slack : 0.701 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.858 - -Slack : 0.680 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.899 - -Slack : 0.686 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.905 +Data Delay : 0.920 Slack : 0.703 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.922 -Slack : 0.747 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : -0.293 -Data Delay : 0.611 - -Slack : 0.763 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.064 -Data Delay : 0.984 - -Slack : 0.764 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.064 -Data Delay : 0.985 - -Slack : 0.771 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.064 -Data Delay : 0.992 - -Slack : 0.780 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Slack : 0.704 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.999 +Data Delay : 0.923 -Slack : 0.785 +Slack : 0.704 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.939 + +Slack : 0.708 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.943 + +Slack : 0.708 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.927 + +Slack : 0.710 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.929 + +Slack : 0.712 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.931 + +Slack : 0.722 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : -0.285 +Data Delay : 0.594 + +Slack : 0.733 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.952 + +Slack : 0.734 From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.004 +Data Delay : 0.953 -Slack : 0.786 +Slack : 0.740 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.457 +Data Delay : 1.354 + +Slack : 0.753 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.973 + +Slack : 0.755 From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.005 +Data Delay : 0.974 -Slack : 0.788 +Slack : 0.769 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.051 +Data Delay : 0.977 + +Slack : 0.774 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.993 + +Slack : 0.789 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.063 +Clock Skew : 0.062 Data Delay : 1.008 -Slack : 0.799 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Slack : 0.807 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.018 +Clock Skew : 0.051 +Data Delay : 1.015 -Slack : 0.808 +Slack : 0.809 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.063 +Clock Skew : 0.062 Data Delay : 1.028 -Slack : 0.814 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Slack : 0.816 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.033 +Data Delay : 1.035 Slack : 0.817 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] @@ -4832,71 +4933,44 @@ Relationship : 0.000 Clock Skew : 0.078 Data Delay : 1.052 -Slack : 0.818 +Slack : 0.819 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.078 -Data Delay : 1.053 +Data Delay : 1.054 -Slack : 0.831 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Slack : 0.820 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.050 +Data Delay : 1.039 -Slack : 0.831 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Slack : 0.830 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.049 + +Slack : 0.832 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.078 -Data Delay : 1.066 - -Slack : 0.832 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.051 - -Slack : 0.832 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.051 - -Slack : 0.833 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : -0.291 -Data Delay : 0.699 +Data Delay : 1.067 Slack : 0.833 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 1.068 - -Slack : 0.833 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] @@ -4904,9 +4978,18 @@ Relationship : 0.000 Clock Skew : 0.078 Data Delay : 1.068 +Slack : 0.834 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.053 + Slack : 0.834 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -4914,16 +4997,16 @@ Clock Skew : 0.078 Data Delay : 1.069 Slack : 0.835 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.069 +Clock Skew : 0.062 +Data Delay : 1.054 Slack : 0.835 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] @@ -4931,36 +5014,45 @@ Relationship : 0.000 Clock Skew : 0.078 Data Delay : 1.070 -Slack : 0.836 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 1.071 - -Slack : 0.845 -From Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Slack : 0.840 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.064 +Data Delay : 1.059 -Slack : 0.848 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Slack : 0.841 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.067 +Data Delay : 1.060 + +Slack : 0.844 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.063 + +Slack : 0.847 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.066 Slack : 0.850 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -4968,30 +5060,12 @@ Clock Skew : 0.062 Data Delay : 1.069 Slack : 0.852 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.071 - -Slack : 0.854 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.073 - -Slack : 0.854 -From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 +Clock Skew : 0.064 Data Delay : 1.073 +--------------------------------------------------------------------------------+ @@ -5009,6 +5083,15 @@ Relationship : 0.000 Clock Skew : 0.063 Data Delay : 0.577 +Slack : 0.357 +From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.577 + Slack : 0.357 From Node : ula:ula_|video:video_|vram_address[10] To Node : ula:ula_|video:video_|vram_address[10] @@ -5019,103 +5102,103 @@ Clock Skew : 0.063 Data Delay : 0.577 Slack : 0.357 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[0] +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|vga_vc[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.063 Data Delay : 0.577 -Slack : 0.358 -From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.577 - -Slack : 0.358 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : ula:ula_|video:video_|vga_vc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.577 - -Slack : 0.358 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vga_vc[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.577 - -Slack : 0.358 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.577 - -Slack : 0.358 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.577 - -Slack : 0.358 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : ula:ula_|video:video_|vga_vc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.577 - -Slack : 0.358 +Slack : 0.357 From Node : ula:ula_|video:video_|vga_vc[4] To Node : ula:ula_|video:video_|vga_vc[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 +Clock Skew : 0.063 Data Delay : 0.577 -Slack : 0.358 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|vga_vc[6] +Slack : 0.357 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vga_vc[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 +Clock Skew : 0.063 Data Delay : 0.577 -Slack : 0.358 +Slack : 0.357 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vga_vc[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.577 + +Slack : 0.357 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vga_vc[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.577 + +Slack : 0.357 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vga_vc[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.577 + +Slack : 0.357 From Node : ula:ula_|video:video_|vga_vc[7] To Node : ula:ula_|video:video_|vga_vc[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 +Clock Skew : 0.063 Data Delay : 0.577 -Slack : 0.549 +Slack : 0.357 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vga_vc[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.577 + +Slack : 0.357 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vga_vc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.577 + +Slack : 0.357 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vga_vc[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.577 + +Slack : 0.551 From Node : ula:ula_|video:video_|frame[2] To Node : ula:ula_|video:video_|frame[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.768 +Clock Skew : 0.063 +Data Delay : 0.771 Slack : 0.553 From Node : ula:ula_|video:video_|frame[3] @@ -5123,782 +5206,2585 @@ To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.772 +Clock Skew : 0.063 +Data Delay : 0.773 -Slack : 0.563 +Slack : 0.587 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.807 + +Slack : 0.702 From Node : ula:ula_|video:video_|frame[1] To Node : ula:ula_|video:video_|frame[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.782 +Clock Skew : 0.063 +Data Delay : 0.922 -Slack : 0.570 -From Node : ula:ula_|video:video_|frame[4] -To Node : ula:ula_|video:video_|frame[4] +Slack : 0.804 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.789 +Clock Skew : 0.076 +Data Delay : 1.037 -Slack : 0.657 +Slack : 0.825 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.045 + +Slack : 0.877 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.095 + +Slack : 0.886 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.876 +Data Delay : 1.105 -Slack : 0.728 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.948 - -Slack : 0.821 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.047 - -Slack : 0.824 -From Node : ula:ula_|video:video_|frame[2] -To Node : ula:ula_|video:video_|frame[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.043 - -Slack : 0.840 -From Node : ula:ula_|video:video_|frame[3] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.059 - -Slack : 0.841 -From Node : ula:ula_|video:video_|frame[1] -To Node : ula:ula_|video:video_|frame[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.060 - -Slack : 0.843 -From Node : ula:ula_|video:video_|frame[1] -To Node : ula:ula_|video:video_|frame[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.062 - -Slack : 0.860 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.080 - -Slack : 0.919 +Slack : 0.897 From Node : ula:ula_|video:video_|frame[0] To Node : ula:ula_|video:video_|frame[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.138 +Clock Skew : -0.264 +Data Delay : 0.790 -Slack : 0.934 -From Node : ula:ula_|video:video_|frame[2] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.153 - -Slack : 0.953 -From Node : ula:ula_|video:video_|frame[1] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.172 - -Slack : 0.967 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.193 - -Slack : 0.980 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.206 - -Slack : 1.030 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.066 -Data Delay : 1.253 - -Slack : 1.074 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 1.299 - -Slack : 1.074 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 1.299 - -Slack : 1.077 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 1.302 - -Slack : 1.078 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 1.303 - -Slack : 1.111 -From Node : ula:ula_|video:video_|bits_prefetch[6] -To Node : ula:ula_|video:video_|bits[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.300 -Data Delay : 0.968 - -Slack : 1.117 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.343 - -Slack : 1.118 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.344 - -Slack : 1.129 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vram_address[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.355 - -Slack : 1.140 -From Node : ula:ula_|video:video_|bits_prefetch[2] -To Node : ula:ula_|video:video_|bits[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.300 -Data Delay : 0.997 - -Slack : 1.143 -From Node : ula:ula_|video:video_|bits_prefetch[1] -To Node : ula:ula_|video:video_|bits[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.300 -Data Delay : 1.000 - -Slack : 1.151 -From Node : ula:ula_|video:video_|bits_prefetch[5] -To Node : ula:ula_|video:video_|bits[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.300 -Data Delay : 1.008 - -Slack : 1.159 +Slack : 0.937 From Node : ula:ula_|video:video_|vga_hc[4] To Node : ula:ula_|video:video_|vram_address[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.385 +Clock Skew : 0.061 +Data Delay : 1.155 -Slack : 1.193 +Slack : 0.976 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.196 + +Slack : 0.978 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.198 + +Slack : 1.003 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.221 + +Slack : 1.010 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vram_address[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.228 + +Slack : 1.014 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vram_address[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.232 + +Slack : 1.103 +From Node : ula:ula_|video:video_|frame[4] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.323 + +Slack : 1.108 +From Node : ula:ula_|video:video_|bits_prefetch[1] +To Node : ula:ula_|video:video_|bits[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.265 +Data Delay : 1.000 + +Slack : 1.110 +From Node : ula:ula_|video:video_|bits_prefetch[2] +To Node : ula:ula_|video:video_|bits[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.265 +Data Delay : 1.002 + +Slack : 1.115 +From Node : ula:ula_|video:video_|bits_prefetch[5] +To Node : ula:ula_|video:video_|bits[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.265 +Data Delay : 1.007 + +Slack : 1.141 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.359 + +Slack : 1.148 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.366 + +Slack : 1.157 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.375 + +Slack : 1.175 From Node : ula:ula_|video:video_|frame[0] To Node : ula:ula_|video:video_|frame[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.412 +Clock Skew : -0.264 +Data Delay : 1.068 -Slack : 1.195 +Slack : 1.177 From Node : ula:ula_|video:video_|frame[0] To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.414 +Clock Skew : -0.264 +Data Delay : 1.070 -Slack : 1.201 +Slack : 1.195 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.413 + +Slack : 1.203 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : ula:ula_|video:video_|vga_hc[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.422 + +Slack : 1.222 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.441 + +Slack : 1.229 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.448 + +Slack : 1.231 From Node : ula:ula_|video:video_|vga_hc[6] To Node : ula:ula_|video:video_|vram_address[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.427 +Clock Skew : 0.061 +Data Delay : 1.449 -Slack : 1.241 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[6] +Slack : 1.232 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[12] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.467 +Clock Skew : 0.061 +Data Delay : 1.450 -Slack : 1.248 +Slack : 1.237 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.455 + +Slack : 1.239 From Node : ula:ula_|video:video_|vga_vc[6] To Node : ula:ula_|video:video_|vram_address[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.474 +Clock Skew : 0.062 +Data Delay : 1.458 -Slack : 1.262 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vga_hc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.482 - -Slack : 1.265 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.485 - -Slack : 1.265 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.485 - -Slack : 1.265 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.485 - -Slack : 1.265 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.485 - -Slack : 1.269 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.495 - -Slack : 1.279 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.505 - -Slack : 1.281 -From Node : ula:ula_|video:video_|bits_prefetch[0] -To Node : ula:ula_|video:video_|bits[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.300 -Data Delay : 1.138 - -Slack : 1.281 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.507 - -Slack : 1.291 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.511 - -Slack : 1.291 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|vram_address[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.064 -Data Delay : 1.512 - -Slack : 1.296 -From Node : ula:ula_|video:video_|attr_prefetch[3] -To Node : ula:ula_|video:video_|attr[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.328 -Data Delay : 1.125 - -Slack : 1.299 +Slack : 1.240 From Node : ula:ula_|video:video_|bits_prefetch[4] To Node : ula:ula_|video:video_|bits[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.300 -Data Delay : 1.156 +Clock Skew : -0.265 +Data Delay : 1.132 -Slack : 1.305 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.524 - -Slack : 1.310 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.529 - -Slack : 1.312 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : ula:ula_|video:video_|vga_hc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.531 - -Slack : 1.314 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.540 - -Slack : 1.316 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.542 - -Slack : 1.323 -From Node : ula:ula_|video:video_|attr_prefetch[5] -To Node : ula:ula_|video:video_|attr[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.328 -Data Delay : 1.152 - -Slack : 1.339 -From Node : ula:ula_|video:video_|attr_prefetch[7] -To Node : ula:ula_|video:video_|attr[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.328 -Data Delay : 1.168 - -Slack : 1.342 -From Node : ula:ula_|video:video_|attr_prefetch[4] -To Node : ula:ula_|video:video_|attr[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.329 -Data Delay : 1.170 - -Slack : 1.351 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.577 - -Slack : 1.355 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vga_hc[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.575 - -Slack : 1.360 -From Node : ula:ula_|video:video_|attr_prefetch[0] -To Node : ula:ula_|video:video_|attr[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.329 -Data Delay : 1.188 - -Slack : 1.378 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.604 - -Slack : 1.380 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.606 - -Slack : 1.387 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vga_hc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.066 -Data Delay : 1.610 - -Slack : 1.391 +Slack : 1.256 From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.617 - -Slack : 1.398 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.066 -Data Delay : 1.621 - -Slack : 1.405 -From Node : ula:ula_|video:video_|vga_vc[1] To Node : ula:ula_|video:video_|vram_address[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.631 +Clock Skew : 0.062 +Data Delay : 1.475 -Slack : 1.406 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.626 - -Slack : 1.407 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.633 - -Slack : 1.426 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.652 - -Slack : 1.450 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.469 -Data Delay : 2.076 - -Slack : 1.450 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.469 -Data Delay : 2.076 - -Slack : 1.450 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.469 -Data Delay : 2.076 - -Slack : 1.450 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.469 -Data Delay : 2.076 - -Slack : 1.450 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.469 -Data Delay : 2.076 - -Slack : 1.450 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.469 -Data Delay : 2.076 - -Slack : 1.450 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.469 -Data Delay : 2.076 - -Slack : 1.450 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.469 -Data Delay : 2.076 - -Slack : 1.479 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.440 -Data Delay : 2.076 - -Slack : 1.479 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.440 -Data Delay : 2.076 - -Slack : 1.479 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.440 -Data Delay : 2.076 - -Slack : 1.479 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.440 -Data Delay : 2.076 - -Slack : 1.479 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.440 -Data Delay : 2.076 - -Slack : 1.479 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.440 -Data Delay : 2.076 - -Slack : 1.479 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.440 -Data Delay : 2.076 - -Slack : 1.479 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.440 -Data Delay : 2.076 - -Slack : 1.490 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.716 - -Slack : 1.500 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.720 - -Slack : 1.509 +Slack : 1.258 From Node : ula:ula_|video:video_|bits_prefetch[7] To Node : ula:ula_|video:video_|bits[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.300 -Data Delay : 1.366 +Clock Skew : -0.265 +Data Delay : 1.150 -Slack : 1.517 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|vga_hc[9] +Slack : 1.258 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.066 -Data Delay : 1.740 +Clock Skew : 0.061 +Data Delay : 1.476 + +Slack : 1.258 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.477 + +Slack : 1.266 +From Node : ula:ula_|video:video_|attr_prefetch[6] +To Node : ula:ula_|video:video_|attr[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.293 +Data Delay : 1.130 + +Slack : 1.268 +From Node : ula:ula_|video:video_|attr_prefetch[0] +To Node : ula:ula_|video:video_|attr[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.293 +Data Delay : 1.132 + +Slack : 1.270 +From Node : ula:ula_|video:video_|attr_prefetch[3] +To Node : ula:ula_|video:video_|attr[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.293 +Data Delay : 1.134 + +Slack : 1.292 +From Node : ula:ula_|video:video_|attr_prefetch[1] +To Node : ula:ula_|video:video_|attr[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.293 +Data Delay : 1.156 + +Slack : 1.294 +From Node : ula:ula_|video:video_|attr_prefetch[4] +To Node : ula:ula_|video:video_|attr[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.293 +Data Delay : 1.158 + +Slack : 1.294 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.513 + +Slack : 1.295 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.514 + +Slack : 1.304 +From Node : ula:ula_|video:video_|attr_prefetch[5] +To Node : ula:ula_|video:video_|attr[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.293 +Data Delay : 1.168 + +Slack : 1.322 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.541 + +Slack : 1.324 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.543 + +Slack : 1.326 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.545 + +Slack : 1.332 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.551 + +Slack : 1.356 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|vga_vc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.576 + +Slack : 1.356 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|vga_vc[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.576 + +Slack : 1.364 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.582 + +Slack : 1.368 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.587 + +Slack : 1.404 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.624 + +Slack : 1.414 +From Node : ula:ula_|video:video_|bits_prefetch[3] +To Node : ula:ula_|video:video_|bits[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.265 +Data Delay : 1.306 + +Slack : 1.414 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.633 + +Slack : 1.416 +From Node : ula:ula_|video:video_|frame[3] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.636 + +Slack : 1.416 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.635 + +Slack : 1.431 +From Node : ula:ula_|video:video_|attr_prefetch[7] +To Node : ula:ula_|video:video_|attr[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.293 +Data Delay : 1.295 + +Slack : 1.436 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.655 + +Slack : 1.486 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vga_hc[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.705 + +Slack : 1.496 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.715 + +Slack : 1.505 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.724 + +Slack : 1.511 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.731 + +Slack : 1.518 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.737 + +Slack : 1.526 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.745 + +Slack : 1.532 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vga_vc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.752 + +Slack : 1.533 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vga_vc[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.753 + +Slack : 1.558 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.776 + +Slack : 1.562 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|vga_vc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.782 + +Slack : 1.575 +From Node : ula:ula_|video:video_|bits_prefetch[6] +To Node : ula:ula_|video:video_|bits[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.265 +Data Delay : 1.467 + +Slack : 1.582 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.800 + +Slack : 1.584 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.804 + +Slack : 1.584 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.804 + +Slack : 1.584 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.804 + +Slack : 1.584 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.804 + +Slack : 1.584 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.804 + +Slack : 1.588 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.808 + +Slack : 1.596 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.815 + +Slack : 1.610 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.829 + +Slack : 1.613 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.435 +Data Delay : 2.205 + +Slack : 1.613 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.435 +Data Delay : 2.205 + +Slack : 1.613 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.435 +Data Delay : 2.205 + +Slack : 1.613 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.435 +Data Delay : 2.205 + +Slack : 1.613 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.435 +Data Delay : 2.205 + +Slack : 1.613 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.435 +Data Delay : 2.205 + +Slack : 1.613 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|attr_prefetch[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.435 +Data Delay : 2.205 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : 0.359 +From Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1 +To Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.577 + +Slack : 0.359 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.wr_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.577 + +Slack : 0.359 +From Node : sdram_controller:sdram_|r.rd_pending +To Node : sdram_controller:sdram_|r.rd_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.577 + +Slack : 0.359 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.state[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.577 + +Slack : 0.359 +From Node : sdram_controller:sdram_|r.rf_pending +To Node : sdram_controller:sdram_|r.rf_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.577 + +Slack : 0.362 +From Node : sdram_controller:sdram_|r.init_counter[0] +To Node : sdram_controller:sdram_|r.init_counter[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.580 + +Slack : 0.379 +From Node : sdram_controller:sdram_|r.rf_counter[9] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.597 + +Slack : 0.521 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.state[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.739 + +Slack : 0.557 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.775 + +Slack : 0.558 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.776 + +Slack : 0.558 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.776 + +Slack : 0.559 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.777 + +Slack : 0.559 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.777 + +Slack : 0.560 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.778 + +Slack : 0.561 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.779 + +Slack : 0.561 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.779 + +Slack : 0.562 +From Node : sdram_controller:sdram_|r.rf_counter[7] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.780 + +Slack : 0.562 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.780 + +Slack : 0.563 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.781 + +Slack : 0.564 +From Node : sdram_controller:sdram_|r.rf_counter[8] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.782 + +Slack : 0.570 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.788 + +Slack : 0.571 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.789 + +Slack : 0.571 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.789 + +Slack : 0.572 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.790 + +Slack : 0.573 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.791 + +Slack : 0.573 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.791 + +Slack : 0.575 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.793 + +Slack : 0.580 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.798 + +Slack : 0.592 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.810 + +Slack : 0.594 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.812 + +Slack : 0.608 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.state[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.826 + +Slack : 0.612 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.state[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.830 + +Slack : 0.612 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.state[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 0.830 + +Slack : 0.818 +From Node : sdram_controller:sdram_|r.address[4]~_Duplicate_1 +To Node : sdram_controller:sdram_|r.address[4]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.037 + +Slack : 0.822 +From Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 +To Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.041 + +Slack : 0.829 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.state[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.047 + +Slack : 0.832 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.050 + +Slack : 0.832 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.050 + +Slack : 0.833 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.051 + +Slack : 0.834 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.052 + +Slack : 0.834 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.052 + +Slack : 0.836 +From Node : sdram_controller:sdram_|r.rf_counter[7] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.054 + +Slack : 0.846 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.064 + +Slack : 0.847 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.065 + +Slack : 0.847 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.065 + +Slack : 0.847 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.065 + +Slack : 0.848 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.066 + +Slack : 0.848 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.066 + +Slack : 0.849 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.067 + +Slack : 0.849 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.067 + +Slack : 0.850 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.068 + +Slack : 0.850 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.068 + +Slack : 0.850 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.068 + +Slack : 0.851 +From Node : sdram_controller:sdram_|r.rf_counter[8] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.069 + +Slack : 0.852 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.070 + +Slack : 0.860 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.078 + +Slack : 0.860 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.078 + +Slack : 0.861 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.079 + +Slack : 0.862 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.080 + +Slack : 0.862 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.080 + +Slack : 0.862 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.080 + +Slack : 0.862 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.080 + +Slack : 0.864 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.082 + +Slack : 0.864 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.082 + +Slack : 0.864 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.082 + +Slack : 0.866 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.084 + +Slack : 0.894 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.state[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.112 + +Slack : 0.909 +From Node : sdram_controller:sdram_|r.rf_counter[9] +To Node : sdram_controller:sdram_|r.rf_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.127 + +Slack : 0.909 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.state[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.127 + +Slack : 0.942 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.160 + +Slack : 0.942 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.160 + +Slack : 0.944 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.162 + +Slack : 0.944 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.162 + +Slack : 0.944 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.162 + +Slack : 0.944 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.162 + +Slack : 0.946 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.164 + +Slack : 0.946 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.164 + +Slack : 0.946 +From Node : sdram_controller:sdram_|r.rf_counter[7] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.164 + +Slack : 0.956 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.174 + +Slack : 0.957 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.175 + +Slack : 0.958 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.176 + +Slack : 0.959 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.177 + +Slack : 0.959 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.177 + +Slack : 0.960 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.178 + +Slack : 0.960 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.178 + +Slack : 0.961 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.179 + +Slack : 0.962 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.180 + +Slack : 0.962 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.180 + +Slack : 0.964 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.182 + +Slack : 0.970 +From Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2 +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.189 + +Slack : 0.971 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.189 + +Slack : 0.972 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.190 + +Slack : 0.972 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.190 + +Slack : 0.973 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.191 + +Slack : 0.974 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.192 + +Slack : 0.974 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.192 + +Slack : 0.974 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.192 + +Slack : 0.974 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.192 + +Slack : 0.976 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.194 + +Slack : 0.976 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.194 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'CLOCK_50' ; ++--------------------------------------------------------------------------------+ +Slack : 0.373 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.592 + +Slack : 0.577 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.637 +Data Delay : 3.505 + +Slack : 0.605 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.640 +Data Delay : 3.536 + +Slack : 0.812 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.636 +Data Delay : 3.739 + +Slack : 0.837 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.637 +Data Delay : 3.765 + +Slack : 1.263 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.357 +Data Delay : 3.911 + +Slack : 1.267 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.643 +Data Delay : 4.201 + +Slack : 1.304 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.648 +Data Delay : 4.243 + +Slack : 1.329 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.561 +Data Delay : 4.181 + +Slack : 1.335 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.645 +Data Delay : 4.271 + +Slack : 1.345 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.654 +Data Delay : 4.290 + +Slack : 1.345 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.641 +Data Delay : 4.277 + +Slack : 1.346 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.348 +Data Delay : 3.985 + +Slack : 1.356 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.646 +Data Delay : 4.293 + +Slack : 1.359 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.348 +Data Delay : 3.998 + +Slack : 1.360 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.557 +Data Delay : 4.208 + +Slack : 1.372 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.643 +Data Delay : 4.306 + +Slack : 1.378 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.351 +Data Delay : 4.020 + +Slack : 1.379 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.641 +Data Delay : 4.311 + +Slack : 1.381 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.645 +Data Delay : 4.317 + +Slack : 1.385 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.561 +Data Delay : 4.237 + +Slack : 1.402 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.646 +Data Delay : 4.339 + +Slack : 1.405 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.573 +Data Delay : 4.269 + +Slack : 1.407 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.363 +Data Delay : 4.061 + +Slack : 1.409 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.648 +Data Delay : 4.348 + +Slack : 1.411 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.636 +Data Delay : 4.338 + +Slack : 1.413 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.361 +Data Delay : 4.065 + +Slack : 1.415 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.570 +Data Delay : 4.276 + +Slack : 1.415 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.356 +Data Delay : 4.062 + +Slack : 1.421 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.564 +Data Delay : 4.276 + +Slack : 1.423 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.557 +Data Delay : 4.271 + +Slack : 1.426 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.570 +Data Delay : 4.287 + +Slack : 1.428 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.632 +Data Delay : 4.351 + +Slack : 1.428 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.364 +Data Delay : 4.083 + +Slack : 1.429 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.559 +Data Delay : 4.279 + +Slack : 1.429 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.352 +Data Delay : 4.072 + +Slack : 1.431 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.556 +Data Delay : 4.278 + +Slack : 1.433 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.570 +Data Delay : 4.294 + +Slack : 1.434 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.362 +Data Delay : 4.087 + +Slack : 1.436 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.637 +Data Delay : 4.364 + +Slack : 1.438 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.573 +Data Delay : 4.302 + +Slack : 1.438 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.557 +Data Delay : 4.286 + +Slack : 1.442 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.339 +Data Delay : 4.072 + +Slack : 1.443 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.573 +Data Delay : 4.307 + +Slack : 1.443 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.564 +Data Delay : 4.298 + +Slack : 1.444 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.548 +Data Delay : 4.283 + +Slack : 1.447 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.570 +Data Delay : 4.308 + +Slack : 1.448 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.553 +Data Delay : 4.292 + +Slack : 1.450 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.557 +Data Delay : 4.298 + +Slack : 1.450 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.353 +Data Delay : 4.094 + +Slack : 1.453 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.552 +Data Delay : 4.296 + +Slack : 1.457 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.573 +Data Delay : 4.321 + +Slack : 1.458 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.559 +Data Delay : 4.308 + +Slack : 1.459 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.564 +Data Delay : 4.314 + +Slack : 1.460 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.561 +Data Delay : 4.312 + +Slack : 1.462 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.562 +Data Delay : 4.315 + +Slack : 1.462 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.632 +Data Delay : 4.385 + +Slack : 1.463 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.561 +Data Delay : 4.315 + +Slack : 1.464 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.564 +Data Delay : 4.319 + +Slack : 1.465 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.654 +Data Delay : 4.410 + +Slack : 1.468 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.645 +Data Delay : 4.404 + +Slack : 1.474 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.553 +Data Delay : 4.318 + +Slack : 1.477 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.634 +Data Delay : 4.402 + +Slack : 1.477 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.548 +Data Delay : 4.316 + +Slack : 1.479 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.564 +Data Delay : 4.334 + +Slack : 1.479 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.550 +Data Delay : 4.320 + +Slack : 1.487 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.559 +Data Delay : 4.337 + +Slack : 1.489 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.564 +Data Delay : 4.344 + +Slack : 1.494 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.548 +Data Delay : 4.333 + +Slack : 1.497 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.341 +Data Delay : 4.129 + +Slack : 1.500 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.561 +Data Delay : 4.352 + +Slack : 1.504 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.561 +Data Delay : 4.356 + +Slack : 1.506 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.573 +Data Delay : 4.370 + +Slack : 1.508 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.562 +Data Delay : 4.361 + +Slack : 1.508 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.354 +Data Delay : 4.153 + +Slack : 1.510 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.561 +Data Delay : 4.362 + +Slack : 1.510 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.553 +Data Delay : 4.354 + +Slack : 1.513 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.564 +Data Delay : 4.368 + +Slack : 1.513 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.552 +Data Delay : 4.356 + +Slack : 1.518 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.553 +Data Delay : 4.362 + +Slack : 1.519 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.559 +Data Delay : 4.369 + +Slack : 1.519 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.553 +Data Delay : 4.363 + +Slack : 1.519 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.550 +Data Delay : 4.360 + +Slack : 1.520 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.643 +Data Delay : 4.454 + +Slack : 1.521 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.351 +Data Delay : 4.163 + +Slack : 1.523 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.559 +Data Delay : 4.373 + +Slack : 1.523 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.553 +Data Delay : 4.367 + +Slack : 1.523 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.352 +Data Delay : 4.166 + +Slack : 1.524 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.548 +Data Delay : 4.363 + +Slack : 1.525 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.557 +Data Delay : 4.373 + +Slack : 1.526 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.548 +Data Delay : 4.365 + +Slack : 1.527 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.561 +Data Delay : 4.379 + +Slack : 1.527 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.553 +Data Delay : 4.371 + +Slack : 1.527 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.564 +Data Delay : 4.382 + +Slack : 1.527 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.561 +Data Delay : 4.379 + +Slack : 1.529 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.556 +Data Delay : 4.376 + +Slack : 1.530 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.550 +Data Delay : 4.371 + +Slack : 1.531 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.377 +Data Delay : 4.199 + +Slack : 1.534 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.556 +Data Delay : 4.381 + +Slack : 1.534 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.550 +Data Delay : 4.375 +--------------------------------------------------------------------------------+ @@ -5906,743 +7792,743 @@ Data Delay : 1.740 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : -6.223 +Slack : -6.212 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 4.344 +Data Delay : 4.333 -Slack : -6.223 +Slack : -6.212 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.163 -Data Delay : 4.342 +Data Delay : 4.331 -Slack : -6.223 +Slack : -6.212 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.164 -Data Delay : 4.341 +Data Delay : 4.330 -Slack : -6.223 +Slack : -6.212 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.165 -Data Delay : 4.340 +Data Delay : 4.329 -Slack : -6.222 +Slack : -6.211 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.164 -Data Delay : 4.340 +Data Delay : 4.329 -Slack : -5.985 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.193 -Data Delay : 4.076 - -Slack : -5.971 +Slack : -5.960 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.195 -Data Delay : 4.060 +Data Delay : 4.049 -Slack : -5.707 +Slack : -5.959 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.923 +Clock Skew : -0.193 +Data Delay : 4.050 -Slack : -5.707 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.923 - -Slack : -5.707 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.923 - -Slack : -5.707 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.923 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 +Slack : -5.696 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 Clock Skew : -0.163 -Data Delay : 3.922 +Data Delay : 3.912 -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.922 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 +Slack : -5.695 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 3.924 +Data Delay : 3.913 -Slack : -5.706 +Slack : -5.695 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.922 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 3.924 +Data Delay : 3.913 -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.922 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 +Slack : -5.695 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 3.924 +Data Delay : 3.913 -Slack : -5.706 +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.160 +Data Delay : 3.914 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.160 +Data Delay : 3.914 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.160 +Data Delay : 3.914 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.160 +Data Delay : 3.914 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.160 +Data Delay : 3.914 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.160 +Data Delay : 3.914 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.160 +Data Delay : 3.914 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.160 +Data Delay : 3.914 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.160 +Data Delay : 3.914 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.160 +Data Delay : 3.914 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.160 +Data Delay : 3.914 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.911 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.911 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.159 +Data Delay : 3.915 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.159 +Data Delay : 3.915 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.911 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.911 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.911 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.911 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.911 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.911 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.911 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.911 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.911 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.911 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.911 + +Slack : -5.695 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.913 + +Slack : -5.695 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 +Clock Skew : -0.160 +Data Delay : 3.914 -Slack : -5.706 +Slack : -5.695 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 +Clock Skew : -0.160 +Data Delay : 3.914 -Slack : -5.706 +Slack : -5.695 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 +Clock Skew : -0.160 +Data Delay : 3.914 -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.165 -Data Delay : 3.920 - -Slack : -5.375 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.170 -Data Delay : 3.924 - -Slack : -5.356 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.190 -Data Delay : 3.922 - -Slack : -5.356 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.190 -Data Delay : 3.922 - -Slack : -5.356 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.190 -Data Delay : 3.922 - -Slack : -5.356 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.190 -Data Delay : 3.922 - -Slack : -5.356 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.190 -Data Delay : 3.922 - -Slack : -5.356 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.190 -Data Delay : 3.922 - -Slack : -5.355 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.184 -Data Delay : 3.918 - -Slack : -5.355 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.184 -Data Delay : 3.918 - -Slack : -5.355 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.184 -Data Delay : 3.918 - -Slack : -5.355 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.184 -Data Delay : 3.918 - -Slack : -5.355 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.184 -Data Delay : 3.918 - -Slack : -5.355 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.184 -Data Delay : 3.918 - -Slack : -5.355 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.184 -Data Delay : 3.918 - -Slack : -5.355 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.184 -Data Delay : 3.918 - -Slack : -5.355 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.184 -Data Delay : 3.918 - -Slack : -5.354 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.185 -Data Delay : 3.918 - -Slack : -5.353 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.188 -Data Delay : 3.920 - -Slack : -5.351 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.192 -Data Delay : 3.922 - -Slack : -5.347 +Slack : -5.686 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.149 +Data Delay : 3.916 -Slack : -5.347 +Slack : -5.686 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.149 +Data Delay : 3.916 -Slack : -5.347 +Slack : -5.686 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.149 +Data Delay : 3.916 -Slack : -5.347 +Slack : -5.686 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.149 +Data Delay : 3.916 -Slack : -5.347 +Slack : -5.686 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.149 +Data Delay : 3.916 -Slack : -5.347 +Slack : -5.686 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.149 +Data Delay : 3.916 -Slack : -5.347 +Slack : -5.686 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.149 +Data Delay : 3.916 -Slack : -5.347 +Slack : -5.686 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.149 +Data Delay : 3.916 -Slack : -5.347 +Slack : -5.686 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.149 +Data Delay : 3.916 -Slack : -5.347 +Slack : -5.686 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.149 +Data Delay : 3.916 -Slack : -5.347 +Slack : -5.686 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.149 +Data Delay : 3.916 -Slack : -5.347 +Slack : -5.686 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.149 +Data Delay : 3.916 -Slack : -5.347 +Slack : -5.686 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.149 +Data Delay : 3.916 -Slack : -5.347 +Slack : -5.686 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.149 +Data Delay : 3.916 + +Slack : -5.686 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.149 +Data Delay : 3.916 + +Slack : -5.345 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.187 +Data Delay : 3.911 + +Slack : -5.345 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.187 +Data Delay : 3.911 + +Slack : -5.345 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.187 +Data Delay : 3.911 + +Slack : -5.345 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.187 +Data Delay : 3.911 + +Slack : -5.345 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.191 +Data Delay : 3.912 + +Slack : -5.345 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.191 +Data Delay : 3.912 + +Slack : -5.345 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.191 +Data Delay : 3.912 + +Slack : -5.345 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.191 +Data Delay : 3.912 + +Slack : -5.345 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.191 +Data Delay : 3.912 + +Slack : -5.345 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.191 +Data Delay : 3.912 + +Slack : -5.344 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 3.913 + +Slack : -5.344 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 3.913 + +Slack : -5.344 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 3.913 + +Slack : -5.344 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 3.913 + +Slack : -5.344 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 3.913 + +Slack : -5.344 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.187 +Data Delay : 3.910 + +Slack : -5.344 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.187 +Data Delay : 3.910 + +Slack : -5.344 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.187 +Data Delay : 3.910 + +Slack : -5.344 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.186 +Data Delay : 3.909 + +Slack : -5.340 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.196 +Data Delay : 3.915 + +Slack : -5.338 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.199 +Data Delay : 3.916 + +Slack : -5.335 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.199 +Data Delay : 3.913 + +Slack : -5.320 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.212 +Data Delay : 3.911 + +Slack : -5.320 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.212 +Data Delay : 3.911 + +Slack : -5.316 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.218 +Data Delay : 3.913 + +Slack : -5.316 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.218 +Data Delay : 3.913 +--------------------------------------------------------------------------------+ @@ -6650,743 +8536,1549 @@ Data Delay : 3.924 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.703 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.609 -Data Delay : 3.556 - -Slack : 3.703 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.609 -Data Delay : 3.556 - -Slack : 3.703 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.609 -Data Delay : 3.556 - -Slack : 3.703 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.609 -Data Delay : 3.556 - -Slack : 3.703 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.609 -Data Delay : 3.556 - -Slack : 3.703 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.609 -Data Delay : 3.556 - -Slack : 3.705 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.611 -Data Delay : 3.557 - -Slack : 3.707 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.606 -Data Delay : 3.554 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.603 -Data Delay : 3.553 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.603 -Data Delay : 3.553 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.603 -Data Delay : 3.553 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.603 -Data Delay : 3.553 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.603 -Data Delay : 3.553 - -Slack : 3.710 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.603 -Data Delay : 3.554 - -Slack : 3.710 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.603 -Data Delay : 3.554 - -Slack : 3.710 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.603 -Data Delay : 3.554 - -Slack : 3.710 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.603 -Data Delay : 3.554 - -Slack : 3.710 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.603 -Data Delay : 3.554 - -Slack : 3.728 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.588 -Data Delay : 3.557 - -Slack : 4.074 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.553 - -Slack : 4.074 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.553 - -Slack : 4.074 +Slack : 3.666 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.242 -Data Delay : 3.557 +Clock Skew : 0.638 +Data Delay : 3.545 -Slack : 4.074 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.242 -Data Delay : 3.557 - -Slack : 4.074 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.242 -Data Delay : 3.557 - -Slack : 4.074 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.242 -Data Delay : 3.557 - -Slack : 4.074 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.553 - -Slack : 4.074 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.553 - -Slack : 4.074 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.553 - -Slack : 4.074 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.239 -Data Delay : 3.554 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.554 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.554 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.554 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.554 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.554 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.554 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.554 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.554 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.554 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.559 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.559 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.559 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.557 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.557 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.559 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.559 - -Slack : 4.075 +Slack : 3.666 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.557 +Clock Skew : 0.638 +Data Delay : 3.545 -Slack : 4.075 +Slack : 3.668 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.559 +Clock Skew : 0.632 +Data Delay : 3.541 -Slack : 4.075 +Slack : 3.668 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.559 +Clock Skew : 0.632 +Data Delay : 3.541 -Slack : 4.075 +Slack : 3.684 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.559 +Clock Skew : 0.618 +Data Delay : 3.543 -Slack : 4.075 +Slack : 3.687 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.559 +Clock Skew : 0.619 +Data Delay : 3.547 -Slack : 4.075 +Slack : 3.689 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.610 +Data Delay : 3.543 + +Slack : 3.689 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.610 +Data Delay : 3.543 + +Slack : 3.689 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.610 +Data Delay : 3.543 + +Slack : 3.689 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.610 +Data Delay : 3.543 + +Slack : 3.689 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.610 +Data Delay : 3.543 + +Slack : 3.689 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.610 +Data Delay : 3.543 + +Slack : 3.690 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.615 +Data Delay : 3.546 + +Slack : 3.693 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.606 +Data Delay : 3.540 + +Slack : 3.693 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.606 +Data Delay : 3.540 + +Slack : 3.693 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.606 +Data Delay : 3.540 + +Slack : 3.694 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.559 +Clock Skew : 0.609 +Data Delay : 3.544 -Slack : 4.075 +Slack : 3.694 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.609 +Data Delay : 3.544 + +Slack : 3.694 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.609 +Data Delay : 3.544 + +Slack : 3.694 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.609 +Data Delay : 3.544 + +Slack : 3.694 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.609 +Data Delay : 3.544 + +Slack : 3.694 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.606 +Data Delay : 3.541 + +Slack : 3.694 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.606 +Data Delay : 3.541 + +Slack : 3.694 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.606 +Data Delay : 3.541 + +Slack : 3.694 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.606 +Data Delay : 3.541 + +Slack : 3.694 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.604 +Data Delay : 3.539 + +Slack : 4.050 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.256 +Data Delay : 3.547 + +Slack : 4.050 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.256 +Data Delay : 3.547 + +Slack : 4.050 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.256 +Data Delay : 3.547 + +Slack : 4.050 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.256 +Data Delay : 3.547 + +Slack : 4.050 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.256 +Data Delay : 3.547 + +Slack : 4.050 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.256 +Data Delay : 3.547 + +Slack : 4.050 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.256 +Data Delay : 3.547 + +Slack : 4.050 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.256 +Data Delay : 3.547 + +Slack : 4.050 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.256 +Data Delay : 3.547 + +Slack : 4.050 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.256 +Data Delay : 3.547 + +Slack : 4.050 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.256 +Data Delay : 3.547 + +Slack : 4.050 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.256 +Data Delay : 3.547 + +Slack : 4.050 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.256 +Data Delay : 3.547 + +Slack : 4.050 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.256 +Data Delay : 3.547 + +Slack : 4.050 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.256 +Data Delay : 3.547 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.244 +Data Delay : 3.544 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.244 +Data Delay : 3.544 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.244 +Data Delay : 3.544 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.244 +Data Delay : 3.544 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.244 +Data Delay : 3.544 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.244 +Data Delay : 3.544 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.244 +Data Delay : 3.544 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.244 +Data Delay : 3.544 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.244 +Data Delay : 3.544 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.244 +Data Delay : 3.544 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.244 +Data Delay : 3.544 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.244 +Data Delay : 3.544 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.244 +Data Delay : 3.544 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.244 +Data Delay : 3.544 + +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.241 +Data Delay : 3.542 + +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.241 +Data Delay : 3.542 + +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.242 +Data Delay : 3.543 + +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.245 +Data Delay : 3.546 + +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.245 +Data Delay : 3.546 + +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.241 +Data Delay : 3.542 + +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.241 +Data Delay : 3.542 + +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.241 +Data Delay : 3.542 + +Slack : 4.060 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.559 +Clock Skew : 0.241 +Data Delay : 3.542 -Slack : 4.075 +Slack : 4.060 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.559 +Clock Skew : 0.241 +Data Delay : 3.542 -Slack : 4.075 +Slack : 4.060 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.559 +Clock Skew : 0.241 +Data Delay : 3.542 -Slack : 4.075 +Slack : 4.060 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.559 +Clock Skew : 0.241 +Data Delay : 3.542 -Slack : 4.075 +Slack : 4.060 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.559 +Clock Skew : 0.241 +Data Delay : 3.542 -Slack : 4.075 +Slack : 4.060 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.241 -Data Delay : 3.557 +Data Delay : 3.542 -Slack : 4.075 +Slack : 4.060 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.559 +Clock Skew : 0.241 +Data Delay : 3.542 -Slack : 4.075 +Slack : 4.060 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.559 +Clock Skew : 0.241 +Data Delay : 3.542 -Slack : 4.075 +Slack : 4.061 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.559 +Data Delay : 3.545 -Slack : 4.075 +Slack : 4.061 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.545 + +Slack : 4.061 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.559 +Data Delay : 3.545 -Slack : 4.294 +Slack : 4.061 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.190 -Data Delay : 3.669 +Clock Skew : 0.243 +Data Delay : 3.545 -Slack : 4.309 +Slack : 4.280 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.192 -Data Delay : 3.686 +Data Delay : 3.657 -Slack : 4.519 +Slack : 4.280 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.222 -Data Delay : 3.922 +Clock Skew : 0.190 +Data Delay : 3.655 -Slack : 4.520 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.225 -Data Delay : 3.926 - -Slack : 4.520 +Slack : 4.505 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.223 -Data Delay : 3.924 +Data Delay : 3.909 -Slack : 4.520 +Slack : 4.505 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.222 -Data Delay : 3.923 +Data Delay : 3.908 -Slack : 4.520 +Slack : 4.505 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.221 -Data Delay : 3.922 +Data Delay : 3.907 + +Slack : 4.506 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.225 +Data Delay : 3.912 + +Slack : 4.506 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.222 +Data Delay : 3.909 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[0] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[1] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[2] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[3] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[4] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[10] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[11] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[12] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[13] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[14] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[1] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[2] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[4] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[5] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[6] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[7] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[8] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[9] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[4] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[5] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[6] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[7] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[8] + +Slack : 4.753 +Actual Width : 4.969 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1 + +Slack : 4.753 +Actual Width : 4.969 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[3] + +Slack : 4.753 +Actual Width : 4.969 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rd_pending + +Slack : 4.753 +Actual Width : 4.969 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[0] + +Slack : 4.753 +Actual Width : 4.969 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[1] + +Slack : 4.753 +Actual Width : 4.969 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[2] + +Slack : 4.753 +Actual Width : 4.969 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[3] + +Slack : 4.753 +Actual Width : 4.969 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[4] + +Slack : 4.753 +Actual Width : 4.969 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[5] + +Slack : 4.753 +Actual Width : 4.969 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[6] + +Slack : 4.753 +Actual Width : 4.969 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[7] + +Slack : 4.753 +Actual Width : 4.969 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[8] + +Slack : 4.753 +Actual Width : 4.969 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[9] + +Slack : 4.753 +Actual Width : 4.969 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_pending + +Slack : 4.753 +Actual Width : 4.969 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.wr_pending + +Slack : 4.755 +Actual Width : 4.971 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[0] + +Slack : 4.758 +Actual Width : 4.974 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1 + +Slack : 4.758 +Actual Width : 4.974 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1 + +Slack : 4.759 +Actual Width : 4.975 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2 + +Slack : 4.759 +Actual Width : 4.975 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 + +Slack : 4.759 +Actual Width : 4.975 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1 + +Slack : 4.830 +Actual Width : 4.985 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[1] + +Slack : 4.830 +Actual Width : 4.985 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[2] + +Slack : 4.833 +Actual Width : 4.988 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11] + +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0] + +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10] + +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1 + +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[4] + +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[5] + +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[8] + +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[9] + +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.bank[0] + +Slack : 4.836 +Actual Width : 4.991 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[0] + +Slack : 4.837 +Actual Width : 4.992 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[1] + +Slack : 4.837 +Actual Width : 4.992 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[2] + +Slack : 4.837 +Actual Width : 4.992 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[3] + +Slack : 4.837 +Actual Width : 4.992 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[6] + +Slack : 4.837 +Actual Width : 4.992 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[7] + +Slack : 4.837 +Actual Width : 4.992 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.bank[1] + +Slack : 4.837 +Actual Width : 4.992 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.dq_masks[0] + +Slack : 4.837 +Actual Width : 4.992 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.dq_masks[1] + +Slack : 4.840 +Actual Width : 5.024 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1 + +Slack : 4.840 +Actual Width : 5.024 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1 + +Slack : 4.840 +Actual Width : 5.024 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2 + +Slack : 4.840 +Actual Width : 5.024 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 + +Slack : 4.840 +Actual Width : 5.024 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1 + +Slack : 4.843 +Actual Width : 5.027 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[0] + +Slack : 4.845 +Actual Width : 5.029 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rd_pending + +Slack : 4.845 +Actual Width : 5.029 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.wr_pending + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[0] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[1] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[2] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[3] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[4] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1 + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[10] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[11] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[12] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[13] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[14] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[1] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[2] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[4] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[5] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[6] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[7] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[8] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[9] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[0] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[1] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[2] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[3] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[4] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[5] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[6] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[7] + +Slack : 4.846 +Actual Width : 5.030 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[8] +--------------------------------------------------------------------------------+ @@ -7400,7 +10092,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0 Slack : 9.488 Actual Width : 9.718 @@ -7408,64 +10100,64 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 + +Slack : 9.488 +Actual Width : 9.718 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg + +Slack : 9.488 +Actual Width : 9.718 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : 9.488 +Actual Width : 9.718 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 + +Slack : 9.488 +Actual Width : 9.718 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Slack : 9.488 -Actual Width : 9.718 +Slack : 9.489 +Actual Width : 9.719 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg -Slack : 9.488 -Actual Width : 9.718 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0 - -Slack : 9.488 -Actual Width : 9.718 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 - -Slack : 9.488 -Actual Width : 9.718 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg - Slack : 9.489 Actual Width : 9.719 Required Width : 0.230 @@ -7490,30 +10182,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg - Slack : 9.489 Actual Width : 9.719 Required Width : 0.230 @@ -7538,6 +10206,78 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg + Slack : 9.489 Actual Width : 9.719 Required Width : 0.230 @@ -7562,6 +10302,54 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg + Slack : 9.489 Actual Width : 9.719 Required Width : 0.230 @@ -7586,30 +10374,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg - Slack : 9.489 Actual Width : 9.719 Required Width : 0.230 @@ -7634,86 +10398,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg - Slack : 9.490 Actual Width : 9.720 Required Width : 0.230 @@ -7744,47 +10428,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 Slack : 9.490 Actual Width : 9.720 @@ -7800,7 +10444,39 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 Slack : 9.490 Actual Width : 9.720 @@ -7824,7 +10500,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 Slack : 9.491 Actual Width : 9.721 @@ -7832,7 +10508,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0 Slack : 9.491 Actual Width : 9.721 @@ -7840,7 +10516,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 Slack : 9.491 Actual Width : 9.721 @@ -7848,7 +10524,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg Slack : 9.491 Actual Width : 9.721 @@ -7856,7 +10532,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0 Slack : 9.491 Actual Width : 9.721 @@ -7864,7 +10540,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 Slack : 9.491 Actual Width : 9.721 @@ -7872,7 +10548,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg Slack : 9.491 Actual Width : 9.721 @@ -7896,7 +10572,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 Slack : 9.491 Actual Width : 9.721 @@ -7906,62 +10590,30 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 -Slack : 9.493 -Actual Width : 9.723 +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 + +Slack : 9.494 +Actual Width : 9.724 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 -Slack : 9.493 -Actual Width : 9.723 +Slack : 9.494 +Actual Width : 9.724 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 -Slack : 9.493 -Actual Width : 9.723 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 - -Slack : 9.493 -Actual Width : 9.723 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 - -Slack : 9.493 -Actual Width : 9.723 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 - -Slack : 9.493 -Actual Width : 9.723 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 - -Slack : 9.493 -Actual Width : 9.723 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 - Slack : 9.494 Actual Width : 9.724 Required Width : 0.230 @@ -7976,7 +10628,31 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 + +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 + +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 + +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 Slack : 9.494 Actual Width : 9.724 @@ -8000,7 +10676,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 Slack : 9.495 Actual Width : 9.725 @@ -8024,7 +10700,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 + +Slack : 9.495 +Actual Width : 9.725 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 Slack : 9.495 Actual Width : 9.725 @@ -8034,13 +10718,13 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -Slack : 9.498 -Actual Width : 9.728 +Slack : 9.495 +Actual Width : 9.725 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 Slack : 9.498 Actual Width : 9.728 @@ -8048,7 +10732,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 + +Slack : 9.498 +Actual Width : 9.728 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 Slack : 9.499 Actual Width : 9.729 @@ -8056,7 +10748,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 Slack : 9.499 Actual Width : 9.729 @@ -8072,7 +10764,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 Slack : 9.499 Actual Width : 9.729 @@ -8080,7 +10772,23 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 Slack : 9.499 Actual Width : 9.729 @@ -8096,7 +10804,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 Slack : 9.499 Actual Width : 9.729 @@ -8104,7 +10812,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 Slack : 9.499 Actual Width : 9.729 @@ -8114,14 +10830,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 -Slack : 9.500 -Actual Width : 9.730 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0 - Slack : 9.500 Actual Width : 9.730 Required Width : 0.230 @@ -8136,7 +10844,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0 Slack : 9.500 Actual Width : 9.730 @@ -8144,7 +10852,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0 Slack : 9.500 Actual Width : 9.730 @@ -8160,7 +10868,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0 + +Slack : 9.500 +Actual Width : 9.730 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~PORTBDATAOUT0 Slack : 9.500 Actual Width : 9.730 @@ -8169,30 +10885,6 @@ Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~PORTBDATAOUT0 - -Slack : 9.501 -Actual Width : 9.731 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 - -Slack : 9.501 -Actual Width : 9.731 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 - -Slack : 9.501 -Actual Width : 9.731 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0 +--------------------------------------------------------------------------------+ @@ -8206,7 +10898,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0 Slack : 19.602 Actual Width : 19.832 @@ -8214,7 +10906,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 Slack : 19.602 Actual Width : 19.832 @@ -8222,7 +10914,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg Slack : 19.602 Actual Width : 19.832 @@ -8230,7 +10922,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0 Slack : 19.602 Actual Width : 19.832 @@ -8238,7 +10930,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 Slack : 19.602 Actual Width : 19.832 @@ -8246,7 +10938,55 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg Slack : 19.602 Actual Width : 19.832 @@ -8296,30 +11036,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0 - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg - Slack : 19.602 Actual Width : 19.832 Required Width : 0.230 @@ -8344,6 +11060,54 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg + Slack : 19.602 Actual Width : 19.832 Required Width : 0.230 @@ -8422,7 +11186,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 Slack : 19.602 Actual Width : 19.832 @@ -8430,7 +11194,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 Slack : 19.602 Actual Width : 19.832 @@ -8438,7 +11202,31 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg Slack : 19.602 Actual Width : 19.832 @@ -8560,6 +11348,30 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_we_reg +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg + Slack : 19.603 Actual Width : 19.833 Required Width : 0.230 @@ -8590,7 +11402,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0 Slack : 19.603 Actual Width : 19.833 @@ -8598,7 +11410,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 Slack : 19.603 Actual Width : 19.833 @@ -8606,7 +11418,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg Slack : 19.603 Actual Width : 19.833 @@ -8614,7 +11426,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0 Slack : 19.603 Actual Width : 19.833 @@ -8622,7 +11434,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 Slack : 19.603 Actual Width : 19.833 @@ -8630,31 +11442,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_we_reg - -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0 - -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 - -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg Slack : 19.603 Actual Width : 19.833 @@ -8680,30 +11468,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_we_reg -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0 - -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 - -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg - Slack : 19.603 Actual Width : 19.833 Required Width : 0.230 @@ -8728,6 +11492,30 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_we_reg +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg + Slack : 19.603 Actual Width : 19.833 Required Width : 0.230 @@ -8776,54 +11564,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_we_reg -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0 - -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 - -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg - -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 - -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 - -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg - Slack : 19.603 Actual Width : 19.833 Required Width : 0.230 @@ -8854,7 +11594,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0 Slack : 19.603 Actual Width : 19.833 @@ -8862,7 +11602,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 Slack : 19.603 Actual Width : 19.833 @@ -8870,31 +11610,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg - -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0 - -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 - -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg Slack : 19.603 Actual Width : 19.833 @@ -8920,85 +11636,61 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg -Slack : 19.604 -Actual Width : 19.834 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0 - -Slack : 19.604 -Actual Width : 19.834 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 - -Slack : 19.604 -Actual Width : 19.834 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg - -Slack : 19.604 -Actual Width : 19.834 +Slack : 19.603 +Actual Width : 19.833 Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0 -Slack : 19.604 -Actual Width : 19.834 +Slack : 19.603 +Actual Width : 19.833 Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Slack : 19.604 -Actual Width : 19.834 +Slack : 19.603 +Actual Width : 19.833 Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_we_reg -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|VGA_HS~_Duplicate_1 - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[0] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[1] - -Slack : 19.604 -Actual Width : 19.820 +Slack : 19.603 +Actual Width : 19.819 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|attr[2] + +Slack : 19.603 +Actual Width : 19.819 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr[3] + +Slack : 19.603 +Actual Width : 19.819 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr[4] + +Slack : 19.603 +Actual Width : 19.819 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr[5] +--------------------------------------------------------------------------------+ @@ -9006,13 +11698,117 @@ Target : ula:ula_|video:video_|attr[2] +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 20.595 -Actual Width : 20.811 +Slack : 20.597 +Actual Width : 20.813 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 Slack : 20.598 Actual Width : 20.814 @@ -9036,7 +11832,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Slack : 20.598 Actual Width : 20.814 @@ -9044,7 +11840,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Slack : 20.598 Actual Width : 20.814 @@ -9052,7 +11848,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Slack : 20.598 Actual Width : 20.814 @@ -9060,7 +11856,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Slack : 20.598 Actual Width : 20.814 @@ -9068,7 +11864,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Slack : 20.598 Actual Width : 20.814 @@ -9076,7 +11872,23 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Slack : 20.599 Actual Width : 20.815 @@ -9126,78 +11938,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack - Slack : 20.599 Actual Width : 20.815 Required Width : 0.216 @@ -9230,125 +11970,165 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|state.Start -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop - -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.601 +Actual Width : 20.817 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.601 +Actual Width : 20.817 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.601 +Actual Width : 20.817 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.601 +Actual Width : 20.817 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.601 +Actual Width : 20.817 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.601 +Actual Width : 20.817 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.601 +Actual Width : 20.817 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.601 +Actual Width : 20.817 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.601 +Actual Width : 20.817 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.601 +Actual Width : 20.817 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.601 +Actual Width : 20.817 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.601 +Actual Width : 20.817 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.601 +Actual Width : 20.817 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.601 +Actual Width : 20.817 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] + +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] Slack : 20.604 Actual Width : 20.820 @@ -9358,13 +12138,13 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Slack : 20.607 -Actual Width : 20.823 +Slack : 20.605 +Actual Width : 20.821 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Slack : 20.607 Actual Width : 20.823 @@ -9372,7 +12152,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] Slack : 20.607 Actual Width : 20.823 @@ -9380,7 +12160,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] Slack : 20.607 Actual Width : 20.823 @@ -9388,7 +12168,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] Slack : 20.607 Actual Width : 20.823 @@ -9396,79 +12176,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] - -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] - -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] - -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] - -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] - -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] - -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] - -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] - -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] - -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] Slack : 20.608 Actual Width : 20.824 @@ -9476,7 +12184,15 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack + +Slack : 20.608 +Actual Width : 20.824 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop Slack : 20.608 Actual Width : 20.824 @@ -9492,7 +12208,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] Slack : 20.608 Actual Width : 20.824 @@ -9500,7 +12216,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] Slack : 20.608 Actual Width : 20.824 @@ -9510,53 +12226,29 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Slack : 20.608 -Actual Width : 20.824 +Slack : 20.609 +Actual Width : 20.825 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Slack : 20.609 -Actual Width : 20.825 +Slack : 20.610 +Actual Width : 20.826 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] -Slack : 20.609 -Actual Width : 20.825 +Slack : 20.610 +Actual Width : 20.826 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] - -Slack : 20.609 -Actual Width : 20.825 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] - -Slack : 20.609 -Actual Width : 20.825 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] - -Slack : 20.615 -Actual Width : 20.831 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 Slack : 20.647 Actual Width : 20.863 @@ -9654,13 +12346,21 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Fall Target : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Slack : 20.684 -Actual Width : 20.868 +Slack : 20.690 +Actual Width : 20.874 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] + +Slack : 20.690 +Actual Width : 20.874 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 Slack : 20.691 Actual Width : 20.846 @@ -9678,6 +12378,14 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|sda_out +Slack : 20.691 +Actual Width : 20.875 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] + Slack : 20.692 Actual Width : 20.847 Required Width : 0.155 @@ -9694,62 +12402,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 -Slack : 20.692 -Actual Width : 20.876 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] - -Slack : 20.692 -Actual Width : 20.876 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] - -Slack : 20.692 -Actual Width : 20.876 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] - -Slack : 20.692 -Actual Width : 20.876 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] - -Slack : 20.692 -Actual Width : 20.876 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] - -Slack : 20.692 -Actual Width : 20.876 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] - -Slack : 20.692 -Actual Width : 20.876 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] - Slack : 20.692 Actual Width : 20.847 Required Width : 0.155 @@ -9758,14 +12410,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r -Slack : 20.692 -Actual Width : 20.876 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 - Slack : 20.692 Actual Width : 20.847 Required Width : 0.155 @@ -9774,6 +12418,22 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] +Slack : 20.693 +Actual Width : 20.877 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack + +Slack : 20.693 +Actual Width : 20.877 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop + Slack : 20.693 Actual Width : 20.848 Required Width : 0.155 @@ -9790,6 +12450,22 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Slack : 20.693 +Actual Width : 20.877 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] + +Slack : 20.693 +Actual Width : 20.877 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] + Slack : 20.693 Actual Width : 20.877 Required Width : 0.184 @@ -9798,13 +12474,29 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Slack : 20.693 +Actual Width : 20.877 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] + Slack : 20.694 Actual Width : 20.878 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] + +Slack : 20.694 +Actual Width : 20.878 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +--------------------------------------------------------------------------------+ @@ -9932,43 +12624,43 @@ Target : ula:ula_|clocks:clocks_|counter[0] +--------------------------------------------------------------------------------+ Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : 1.981 -Fall : 2.458 +Rise : 1.548 +Fall : 1.931 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : 3.874 -Fall : 4.319 +Rise : 3.846 +Fall : 4.271 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : SW[*] Clock Port : CLOCK_50 -Rise : 1.011 -Fall : 1.277 +Rise : 1.010 +Fall : 1.278 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : SW[2] Clock Port : CLOCK_50 -Rise : 1.011 -Fall : 1.277 +Rise : 1.010 +Fall : 1.278 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : 1.262 -Fall : 1.505 +Rise : 1.221 +Fall : 1.461 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : 2.823 -Fall : 3.104 +Rise : 2.814 +Fall : 3.095 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -9980,43 +12672,43 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : -1.568 -Fall : -2.042 +Rise : -1.154 +Fall : -1.552 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : -2.986 -Fall : -3.436 +Rise : -2.539 +Fall : -2.918 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : SW[*] Clock Port : CLOCK_50 -Rise : -0.397 -Fall : -0.660 +Rise : -0.395 +Fall : -0.661 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : SW[2] Clock Port : CLOCK_50 -Rise : -0.397 -Fall : -0.660 +Rise : -0.395 +Fall : -0.661 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : -0.645 -Fall : -0.878 +Rise : -0.602 +Fall : -0.833 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : -1.355 -Fall : -1.593 +Rise : -1.346 +Fall : -1.585 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -10026,199 +12718,619 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ ; Clock to Output Times ; +--------------------------------------------------------------------------------+ -Data Port : GPIO_1[*] +Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 10.359 -Fall : 10.359 +Rise : 10.801 +Fall : 10.789 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[16] +Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 10.359 -Fall : 10.359 +Rise : 10.164 +Fall : 10.160 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[17] +Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 9.229 -Fall : 9.317 +Rise : 10.350 +Fall : 10.351 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[18] +Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 10.015 -Fall : 9.971 +Rise : 10.114 +Fall : 10.074 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[19] +Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 9.628 -Fall : 9.644 +Rise : 10.072 +Fall : 10.237 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[20] +Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 9.826 -Fall : 9.843 +Rise : 10.376 +Fall : 10.386 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[21] +Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 9.397 -Fall : 9.318 +Rise : 10.482 +Fall : 10.574 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[22] +Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 9.972 -Fall : 9.975 +Rise : 10.801 +Fall : 10.789 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[23] +Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 9.201 -Fall : 9.152 +Rise : 10.294 +Fall : 10.222 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 7.986 -Fall : 7.983 +Rise : 10.527 +Fall : 10.543 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 10.022 +Fall : 10.010 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 10.153 +Fall : 10.157 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 10.039 +Fall : 10.024 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 9.790 +Fall : 9.910 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 10.258 +Fall : 10.260 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 10.080 +Fall : 10.129 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 10.527 +Fall : 10.543 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 9.684 +Fall : 9.676 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_ADDR[*] +Clock Port : CLOCK_50 +Rise : 3.430 +Fall : 3.345 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[0] +Clock Port : CLOCK_50 +Rise : 3.425 +Fall : 3.340 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[1] +Clock Port : CLOCK_50 +Rise : 3.320 +Fall : 3.233 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[2] +Clock Port : CLOCK_50 +Rise : 3.320 +Fall : 3.233 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[3] +Clock Port : CLOCK_50 +Rise : 3.319 +Fall : 3.232 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[4] +Clock Port : CLOCK_50 +Rise : 3.321 +Fall : 3.234 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[5] +Clock Port : CLOCK_50 +Rise : 3.318 +Fall : 3.231 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[6] +Clock Port : CLOCK_50 +Rise : 3.319 +Fall : 3.232 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[7] +Clock Port : CLOCK_50 +Rise : 3.317 +Fall : 3.230 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[8] +Clock Port : CLOCK_50 +Rise : 3.296 +Fall : 3.214 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[9] +Clock Port : CLOCK_50 +Rise : 3.425 +Fall : 3.340 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[10] +Clock Port : CLOCK_50 +Rise : 3.416 +Fall : 3.331 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[11] +Clock Port : CLOCK_50 +Rise : 3.430 +Fall : 3.345 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[12] +Clock Port : CLOCK_50 +Rise : 3.294 +Fall : 3.212 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[*] +Clock Port : CLOCK_50 +Rise : 3.320 +Fall : 3.233 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[0] +Clock Port : CLOCK_50 +Rise : 3.318 +Fall : 3.231 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[1] +Clock Port : CLOCK_50 +Rise : 3.320 +Fall : 3.233 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CAS_N +Clock Port : CLOCK_50 +Rise : 3.426 +Fall : 3.341 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 6.248 +Fall : 6.300 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 5.552 +Fall : 5.647 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 5.839 +Fall : 5.898 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 5.545 +Fall : 5.576 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 5.269 +Fall : 5.330 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 5.626 +Fall : 5.683 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 5.718 +Fall : 5.830 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 5.584 +Fall : 5.653 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 5.733 +Fall : 5.777 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[8] +Clock Port : CLOCK_50 +Rise : 6.248 +Fall : 6.299 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[9] +Clock Port : CLOCK_50 +Rise : 6.038 +Fall : 6.073 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[10] +Clock Port : CLOCK_50 +Rise : 6.021 +Fall : 6.053 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[11] +Clock Port : CLOCK_50 +Rise : 6.021 +Fall : 6.053 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[12] +Clock Port : CLOCK_50 +Rise : 6.215 +Fall : 6.300 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[13] +Clock Port : CLOCK_50 +Rise : 6.241 +Fall : 6.286 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[14] +Clock Port : CLOCK_50 +Rise : 6.241 +Fall : 6.286 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[15] +Clock Port : CLOCK_50 +Rise : 5.859 +Fall : 5.918 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[*] +Clock Port : CLOCK_50 +Rise : 3.317 +Fall : 3.230 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[0] +Clock Port : CLOCK_50 +Rise : 3.317 +Fall : 3.230 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[1] +Clock Port : CLOCK_50 +Rise : 3.317 +Fall : 3.230 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_RAS_N +Clock Port : CLOCK_50 +Rise : 3.426 +Fall : 3.341 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_WE_N +Clock Port : CLOCK_50 +Rise : 3.423 +Fall : 3.338 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : 4.576 +Fall : +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : +Fall : 4.505 +Clock Edge : Fall +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 8.525 +Fall : 8.506 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 7.614 +Fall : 7.674 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 7.796 +Fall : 7.806 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 8.092 +Fall : 8.080 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 7.910 +Fall : 8.021 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 8.495 +Fall : 8.500 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 8.018 +Fall : 8.084 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 8.525 +Fall : 8.506 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 7.947 +Fall : 7.936 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 8.377 +Fall : 8.374 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 7.696 -Fall : 7.696 +Rise : 7.472 +Fall : 7.524 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 7.783 -Fall : 7.821 +Rise : 7.599 +Fall : 7.612 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 7.371 -Fall : 7.388 +Rise : 8.017 +Fall : 8.030 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 7.739 -Fall : 7.774 +Rise : 7.628 +Fall : 7.694 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 7.986 -Fall : 7.975 +Rise : 8.377 +Fall : 8.374 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 7.534 -Fall : 7.528 +Rise : 7.619 +Fall : 7.643 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 7.914 -Fall : 7.983 +Rise : 8.251 +Fall : 8.260 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 7.285 -Fall : 7.303 +Rise : 7.224 +Fall : 7.248 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 8.197 -Fall : 7.907 +Rise : 8.645 +Fall : 8.352 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 8.197 -Fall : 7.907 +Rise : 8.645 +Fall : 8.352 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 6.071 -Fall : 5.974 +Rise : 7.356 +Fall : 7.355 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 6.410 -Fall : 6.400 +Rise : 6.643 +Fall : 6.643 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 6.836 -Fall : 6.810 +Rise : 6.647 +Fall : 6.639 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 6.558 -Fall : 6.425 +Rise : 6.988 +Fall : 6.893 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 6.558 -Fall : 6.425 +Rise : 6.282 +Fall : 6.183 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 6.366 -Fall : 6.305 +Rise : 6.690 +Fall : 6.712 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 6.429 -Fall : 6.279 +Rise : 6.988 +Fall : 6.893 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 6.429 -Fall : 6.279 +Rise : 6.988 +Fall : 6.893 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -10231,36 +13343,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 6.621 -Fall : 6.664 +Rise : 7.297 +Fall : 7.345 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 6.621 -Fall : 6.664 +Rise : 6.937 +Fall : 6.925 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 6.426 -Fall : 6.412 +Rise : 7.297 +Fall : 7.345 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 6.231 -Fall : 6.211 +Rise : 6.690 +Fall : 6.631 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 6.443 -Fall : 6.428 +Rise : 6.641 +Fall : 6.567 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -10326,199 +13438,619 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ ; Minimum Clock to Output Times ; +--------------------------------------------------------------------------------+ -Data Port : GPIO_1[*] +Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 7.669 -Fall : 7.651 +Rise : 7.830 +Fall : 7.818 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[16] +Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 8.267 -Fall : 8.296 +Rise : 8.061 +Fall : 8.083 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[17] +Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 8.307 -Fall : 8.286 +Rise : 8.174 +Fall : 8.205 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[18] +Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 7.669 -Fall : 7.651 +Rise : 7.830 +Fall : 7.818 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[19] +Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 8.069 -Fall : 8.077 +Rise : 8.228 +Fall : 8.280 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[20] +Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 8.420 -Fall : 8.430 +Rise : 8.428 +Fall : 8.466 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[21] +Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 7.905 -Fall : 7.819 +Rise : 8.693 +Fall : 8.718 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[22] +Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 7.716 -Fall : 7.719 +Rise : 8.284 +Fall : 8.302 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[23] +Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 7.805 -Fall : 7.751 +Rise : 8.683 +Fall : 8.600 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 5.460 -Fall : 5.452 +Rise : 7.760 +Fall : 7.774 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 7.924 +Fall : 7.938 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 7.985 +Fall : 8.020 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 7.760 +Fall : 7.774 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 7.962 +Fall : 7.971 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 8.306 +Fall : 8.338 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 8.306 +Fall : 8.291 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 8.017 +Fall : 8.062 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 8.101 +Fall : 8.081 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_ADDR[*] +Clock Port : CLOCK_50 +Rise : 2.874 +Fall : 2.792 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[0] +Clock Port : CLOCK_50 +Rise : 3.004 +Fall : 2.919 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[1] +Clock Port : CLOCK_50 +Rise : 2.900 +Fall : 2.813 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[2] +Clock Port : CLOCK_50 +Rise : 2.900 +Fall : 2.813 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[3] +Clock Port : CLOCK_50 +Rise : 2.899 +Fall : 2.812 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[4] +Clock Port : CLOCK_50 +Rise : 2.901 +Fall : 2.814 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[5] +Clock Port : CLOCK_50 +Rise : 2.898 +Fall : 2.811 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[6] +Clock Port : CLOCK_50 +Rise : 2.899 +Fall : 2.812 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[7] +Clock Port : CLOCK_50 +Rise : 2.897 +Fall : 2.810 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[8] +Clock Port : CLOCK_50 +Rise : 2.876 +Fall : 2.794 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[9] +Clock Port : CLOCK_50 +Rise : 3.004 +Fall : 2.919 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[10] +Clock Port : CLOCK_50 +Rise : 2.996 +Fall : 2.911 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[11] +Clock Port : CLOCK_50 +Rise : 3.009 +Fall : 2.924 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[12] +Clock Port : CLOCK_50 +Rise : 2.874 +Fall : 2.792 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[*] +Clock Port : CLOCK_50 +Rise : 2.898 +Fall : 2.811 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[0] +Clock Port : CLOCK_50 +Rise : 2.898 +Fall : 2.811 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[1] +Clock Port : CLOCK_50 +Rise : 2.899 +Fall : 2.812 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CAS_N +Clock Port : CLOCK_50 +Rise : 3.006 +Fall : 2.921 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 4.562 +Fall : 4.614 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 4.973 +Fall : 5.061 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 5.248 +Fall : 5.301 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 4.963 +Fall : 4.991 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 4.700 +Fall : 4.753 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 5.044 +Fall : 5.095 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 5.134 +Fall : 5.235 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 4.945 +Fall : 5.002 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 5.145 +Fall : 5.183 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[8] +Clock Port : CLOCK_50 +Rise : 4.931 +Fall : 4.977 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[9] +Clock Port : CLOCK_50 +Rise : 4.730 +Fall : 4.760 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[10] +Clock Port : CLOCK_50 +Rise : 4.713 +Fall : 4.741 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[11] +Clock Port : CLOCK_50 +Rise : 4.713 +Fall : 4.741 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[12] +Clock Port : CLOCK_50 +Rise : 4.900 +Fall : 4.977 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[13] +Clock Port : CLOCK_50 +Rise : 4.924 +Fall : 4.965 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[14] +Clock Port : CLOCK_50 +Rise : 4.924 +Fall : 4.965 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[15] +Clock Port : CLOCK_50 +Rise : 4.562 +Fall : 4.614 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[*] +Clock Port : CLOCK_50 +Rise : 2.897 +Fall : 2.810 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[0] +Clock Port : CLOCK_50 +Rise : 2.897 +Fall : 2.810 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[1] +Clock Port : CLOCK_50 +Rise : 2.897 +Fall : 2.810 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_RAS_N +Clock Port : CLOCK_50 +Rise : 3.006 +Fall : 2.921 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_WE_N +Clock Port : CLOCK_50 +Rise : 3.003 +Fall : 2.918 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : 4.164 +Fall : +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : +Fall : 4.093 +Clock Edge : Fall +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 6.189 +Fall : 6.209 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 6.676 +Fall : 6.693 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 6.674 +Fall : 6.676 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 7.005 +Fall : 6.988 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 6.630 +Fall : 6.784 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 6.357 +Fall : 6.415 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 6.848 +Fall : 6.958 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 6.189 +Fall : 6.209 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 7.027 +Fall : 7.015 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 5.922 +Fall : 5.969 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 6.523 -Fall : 6.572 +Rise : 6.539 +Fall : 6.548 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 6.581 -Fall : 6.660 +Rise : 6.485 +Fall : 6.491 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 6.318 -Fall : 6.325 +Rise : 6.935 +Fall : 6.944 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 6.316 -Fall : 6.388 +Rise : 6.364 +Fall : 6.475 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 5.460 -Fall : 5.452 +Rise : 6.235 +Fall : 6.287 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 6.325 -Fall : 6.358 +Rise : 6.464 +Fall : 6.535 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 6.708 -Fall : 6.750 +Rise : 5.922 +Fall : 5.969 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 6.065 -Fall : 6.060 +Rise : 6.372 +Fall : 6.397 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 3.938 -Fall : 3.816 +Rise : 4.408 +Fall : 4.397 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 5.979 -Fall : 5.590 +Rise : 6.411 +Fall : 6.112 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 3.938 -Fall : 3.816 +Rise : 4.636 +Fall : 4.572 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 4.183 -Fall : 4.073 +Rise : 4.408 +Fall : 4.401 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 4.592 -Fall : 4.467 +Rise : 4.413 +Fall : 4.397 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 4.007 -Fall : 3.940 +Rise : 3.788 +Fall : 3.713 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 4.406 -Fall : 4.287 +Rise : 3.811 +Fall : 3.715 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 4.007 -Fall : 3.940 +Rise : 3.788 +Fall : 3.713 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 4.282 -Fall : 4.147 +Rise : 4.488 +Fall : 4.397 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 4.282 -Fall : 4.147 +Rise : 4.488 +Fall : 4.397 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -10531,36 +14063,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 3.864 -Fall : 3.753 +Rise : 4.158 +Fall : 4.085 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 4.238 -Fall : 4.188 +Rise : 4.442 +Fall : 4.429 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 4.151 -Fall : 4.091 +Rise : 4.462 +Fall : 4.423 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 3.864 -Fall : 3.753 +Rise : 4.205 +Fall : 4.147 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 4.068 -Fall : 3.961 +Rise : 4.158 +Fall : 4.085 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -10635,24 +14167,31 @@ FF : 4.693 Input Port : SW[2] Output Port : LED[2] -RR : 4.044 +RR : 4.045 RF : FR : FF : 4.195 Input Port : raw_loader_in -Output Port : GPIO_1[22] -RR : 6.626 +Output Port : DRAM_DQ[6] +RR : 6.893 RF : FR : -FF : 7.003 +FF : 7.253 + +Input Port : raw_loader_in +Output Port : GPIO_1[22] +RR : 7.004 +RF : +FR : +FF : 7.359 Input Port : raw_loader_in Output Port : LED[3] -RR : 4.318 +RR : 4.487 RF : FR : -FF : 4.517 +FF : 4.751 +--------------------------------------------------------------------------------+ @@ -10665,28 +14204,311 @@ Output Port : LED[0] RR : 4.491 RF : FR : -FF : 4.559 +FF : 4.560 Input Port : SW[2] Output Port : LED[2] -RR : 3.930 +RR : 3.931 RF : FR : -FF : 4.081 +FF : 4.082 + +Input Port : raw_loader_in +Output Port : DRAM_DQ[6] +RR : 6.662 +RF : +FR : +FF : 7.012 Input Port : raw_loader_in Output Port : GPIO_1[22] -RR : 6.402 +RR : 6.765 RF : FR : -FF : 6.769 +FF : 7.110 Input Port : raw_loader_in Output Port : LED[3] -RR : 4.186 +RR : 4.348 RF : FR : -FF : 4.384 +FF : 4.609 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Output Enable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 5.921 +Fall : 5.799 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 6.438 +Fall : 6.316 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 6.438 +Fall : 6.316 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 6.070 +Fall : 5.937 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 6.069 +Fall : 5.949 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 5.921 +Fall : 5.799 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 6.085 +Fall : 5.963 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 6.085 +Fall : 5.963 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 6.061 +Fall : 5.928 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 4.617 +Fall : 4.495 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 5.113 +Fall : 4.991 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 5.113 +Fall : 4.991 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 4.732 +Fall : 4.599 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 4.754 +Fall : 4.634 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 4.617 +Fall : 4.495 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 4.775 +Fall : 4.653 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 4.775 +Fall : 4.653 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 4.723 +Fall : 4.590 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Output Disable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.820 +1 to Hi-Z : 5.942 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +0 to Hi-Z : 6.366 +1 to Hi-Z : 6.488 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +0 to Hi-Z : 6.366 +1 to Hi-Z : 6.488 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.976 +1 to Hi-Z : 6.109 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +0 to Hi-Z : 6.042 +1 to Hi-Z : 6.162 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.820 +1 to Hi-Z : 5.942 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.919 +1 to Hi-Z : 6.041 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.919 +1 to Hi-Z : 6.041 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.948 +1 to Hi-Z : 6.081 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Minimum Output Disable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.523 +1 to Hi-Z : 4.645 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.047 +1 to Hi-Z : 5.169 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.047 +1 to Hi-Z : 5.169 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.644 +1 to Hi-Z : 4.777 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.731 +1 to Hi-Z : 4.851 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.523 +1 to Hi-Z : 4.645 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.617 +1 to Hi-Z : 4.739 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.617 +1 to Hi-Z : 4.739 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.617 +1 to Hi-Z : 4.750 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +--------------------------------------------------------------------------------+ @@ -10700,22 +14522,27 @@ No synchronizer chains to report. +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Fmax Summary ; +--------------------------------------------------------------------------------+ -Fmax : 51.79 MHz -Restricted Fmax : 51.79 MHz +Fmax : 50.7 MHz +Restricted Fmax : 50.7 MHz Clock Name : CLOCK_50 Note : -Fmax : 138.35 MHz -Restricted Fmax : 138.35 MHz +Fmax : 132.1 MHz +Restricted Fmax : 132.1 MHz Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Note : -Fmax : 177.12 MHz -Restricted Fmax : 177.12 MHz +Fmax : 170.88 MHz +Restricted Fmax : 170.88 MHz +Clock Name : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Note : + +Fmax : 180.38 MHz +Restricted Fmax : 180.38 MHz Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Note : -Fmax : 1052.63 MHz +Fmax : 1054.85 MHz Restricted Fmax : 500.0 MHz Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Note : limit due to minimum period restriction (tmin) @@ -10728,20 +14555,24 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp ; Slow 1200mV 0C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -17.311 -End Point TNS : -526.609 +Slack : -17.727 +End Point TNS : -781.205 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Slack : -6.686 -End Point TNS : -253.661 +Slack : -6.896 +End Point TNS : -255.894 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : -4.428 -End Point TNS : -40.009 +Slack : -4.422 +End Point TNS : -38.759 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Slack : -2.785 -End Point TNS : -2.785 +Slack : -2.786 +End Point TNS : -2.786 + +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Slack : 4.148 +End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -10754,16 +14585,20 @@ Slack : 0.298 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 0.300 -End Point TNS : 0.000 - -Clock : CLOCK_50 -Slack : 0.304 +Slack : 0.298 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Slack : 0.311 End Point TNS : 0.000 + +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Slack : 0.312 +End Point TNS : 0.000 + +Clock : CLOCK_50 +Slack : 0.339 +End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -10772,8 +14607,8 @@ End Point TNS : 0.000 ; Slow 1200mV 0C Model Recovery Summary ; +--------------------------------------------------------------------------------+ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : -5.744 -End Point TNS : -423.582 +Slack : -5.735 +End Point TNS : -424.927 +--------------------------------------------------------------------------------+ @@ -10782,7 +14617,7 @@ End Point TNS : -423.582 ; Slow 1200mV 0C Model Removal Summary ; +--------------------------------------------------------------------------------+ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 3.374 +Slack : 3.339 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -10791,12 +14626,16 @@ End Point TNS : 0.000 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +--------------------------------------------------------------------------------+ +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Slack : 4.748 +End Point TNS : 0.000 + Clock : CLOCK_50 Slack : 9.489 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Slack : 19.600 +Slack : 19.596 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] @@ -10813,905 +14652,905 @@ End Point TNS : 0.000 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -17.311 -From Node : ula:ula_|video:video_|vga_vc[2] +Slack : -17.727 +From Node : ula:ula_|video:video_|vga_hc[1] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 7.112 +Clock Skew : -0.281 +Data Delay : 7.520 -Slack : -17.306 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_B[0] +Slack : -17.668 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 7.107 +Clock Skew : -0.263 +Data Delay : 7.479 -Slack : -17.281 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 7.081 - -Slack : -17.275 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 7.075 - -Slack : -17.265 +Slack : -17.643 From Node : ula:ula_|video:video_|vga_vc[9] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 7.066 +Clock Skew : -0.281 +Data Delay : 7.436 -Slack : -17.249 -From Node : ula:ula_|video:video_|vga_vc[8] +Slack : -17.634 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 7.192 + +Slack : -17.631 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.504 +Data Delay : 7.201 + +Slack : -17.617 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.263 +Data Delay : 7.428 + +Slack : -17.598 +From Node : ula:ula_|video:video_|bits[5] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 7.050 +Clock Skew : -0.281 +Data Delay : 7.391 -Slack : -17.244 +Slack : -17.595 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 7.153 + +Slack : -17.581 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.510 +Data Delay : 7.145 + +Slack : -17.546 From Node : ula:ula_|video:video_|vga_hc[2] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 7.044 +Clock Skew : -0.282 +Data Delay : 7.338 -Slack : -17.196 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 -To Node : GPIO_1[20] +Slack : -17.546 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.515 -Data Delay : 6.755 +Clock Skew : -0.263 +Data Delay : 7.357 -Slack : -17.190 -From Node : ula:ula_|video:video_|vga_vc[1] +Slack : -17.544 +From Node : ula:ula_|video:video_|vga_vc[8] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 6.991 +Clock Skew : -0.281 +Data Delay : 7.337 -Slack : -17.182 +Slack : -17.540 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.282 +Data Delay : 7.332 + +Slack : -17.535 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.984 +Clock Skew : -0.263 +Data Delay : 7.346 -Slack : -17.176 +Slack : -17.533 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.282 +Data Delay : 7.325 + +Slack : -17.529 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.281 +Data Delay : 7.322 + +Slack : -17.521 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.281 +Data Delay : 7.314 + +Slack : -17.521 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.282 +Data Delay : 7.313 + +Slack : -17.513 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 7.071 + +Slack : -17.502 +From Node : ula:ula_|video:video_|frame[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.278 +Data Delay : 7.298 + +Slack : -17.481 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.281 +Data Delay : 7.274 + +Slack : -17.452 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 7.010 + +Slack : -17.448 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.263 +Data Delay : 7.259 + +Slack : -17.426 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.281 +Data Delay : 7.219 + +Slack : -17.414 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.972 + +Slack : -17.411 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.504 +Data Delay : 6.981 + +Slack : -17.406 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.282 +Data Delay : 7.198 + +Slack : -17.384 +From Node : ula:ula_|video:video_|bits[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.281 +Data Delay : 7.177 + +Slack : -17.380 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.939 + +Slack : -17.371 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.281 +Data Delay : 7.164 + +Slack : -17.363 +From Node : ula:ula_|video:video_|bits[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.281 +Data Delay : 7.156 + +Slack : -17.361 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.510 +Data Delay : 6.925 + +Slack : -17.361 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.510 -Data Delay : 6.740 +Data Delay : 6.925 -Slack : -17.176 -From Node : ula:ula_|video:video_|bits[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 6.973 - -Slack : -17.172 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 6.969 - -Slack : -17.142 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.944 - -Slack : -17.140 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 6.941 - -Slack : -17.136 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 6.937 - -Slack : -17.114 +Slack : -17.359 From Node : ula:ula_|video:video_|vga_vc[7] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 6.915 +Clock Skew : -0.281 +Data Delay : 7.152 -Slack : -17.106 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 6.906 - -Slack : -17.082 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 6.883 - -Slack : -17.075 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.518 -Data Delay : 6.631 - -Slack : -17.061 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.863 - -Slack : -17.022 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 6.823 - -Slack : -16.969 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 6.519 - -Slack : -16.953 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 6.750 - -Slack : -16.941 +Slack : -17.343 From Node : ula:ula_|video:video_|bits[1] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 6.738 +Clock Skew : -0.281 +Data Delay : 7.136 -Slack : -16.939 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 -To Node : GPIO_1[17] +Slack : -17.326 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 6.489 +Clock Skew : -0.263 +Data Delay : 7.137 -Slack : -16.921 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.723 - -Slack : -16.917 -From Node : ula:ula_|video:video_|vga_hc[8] +Slack : -17.298 +From Node : ula:ula_|video:video_|vga_vc[5] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 6.717 +Clock Skew : -0.281 +Data Delay : 7.091 -Slack : -16.916 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 -To Node : GPIO_1[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.515 -Data Delay : 6.475 - -Slack : -16.906 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 6.706 - -Slack : -16.904 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 6.462 - -Slack : -16.894 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.504 -Data Delay : 6.464 - -Slack : -16.865 +Slack : -17.298 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 6.423 +Clock Skew : -0.515 +Data Delay : 6.857 -Slack : -16.857 -From Node : ula:ula_|video:video_|bits[6] +Slack : -17.289 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.848 + +Slack : -17.281 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.263 +Data Delay : 7.092 + +Slack : -17.279 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.510 +Data Delay : 6.843 + +Slack : -17.279 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.512 +Data Delay : 6.841 + +Slack : -17.275 +From Node : ula:ula_|video:video_|vga_vc[0] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 6.654 +Clock Skew : -0.281 +Data Delay : 7.068 -Slack : -16.852 -From Node : ula:ula_|video:video_|frame[4] +Slack : -17.236 +From Node : ula:ula_|video:video_|vga_hc[8] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.279 -Data Delay : 6.647 +Clock Skew : -0.282 +Data Delay : 7.028 -Slack : -16.821 -From Node : ula:ula_|video:video_|bits[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 6.618 - -Slack : -16.820 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +Slack : -17.232 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.790 + +Slack : -17.227 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 Clock Skew : -0.518 -Data Delay : 6.376 +Data Delay : 6.783 -Slack : -16.761 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 -To Node : GPIO_1[22] +Slack : -17.181 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +To Node : DRAM_DQ[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.521 -Data Delay : 6.314 +Clock Skew : -0.524 +Data Delay : 6.731 -Slack : -16.737 +Slack : -17.178 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.737 + +Slack : -17.170 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[21] +To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.539 +Clock Skew : -0.263 +Data Delay : 6.981 -Slack : -16.733 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[21] +Slack : -17.168 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.535 +Clock Skew : -0.512 +Data Delay : 6.730 -Slack : -16.727 +Slack : -17.162 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.721 + +Slack : -17.152 +From Node : ula:ula_|video:video_|vga_hc[9] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.282 +Data Delay : 6.944 + +Slack : -17.134 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.684 + +Slack : -17.131 From Node : ula:ula_|video:video_|bits[2] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 6.524 +Clock Skew : -0.281 +Data Delay : 6.924 -Slack : -16.721 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 -To Node : GPIO_1[16] +Slack : -17.128 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +To Node : DRAM_DQ[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.523 -Data Delay : 6.272 +Clock Skew : -0.524 +Data Delay : 6.678 -Slack : -16.719 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 -To Node : GPIO_1[19] +Slack : -17.124 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.513 -Data Delay : 6.280 +Clock Skew : -0.263 +Data Delay : 6.935 -Slack : -16.716 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 6.274 - -Slack : -16.702 +Slack : -17.107 From Node : ula:ula_|video:video_|bits[3] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 6.499 +Clock Skew : -0.281 +Data Delay : 6.900 -Slack : -16.700 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[17] +Slack : -17.106 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +To Node : DRAM_DQ[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.502 +Clock Skew : -0.521 +Data Delay : 6.659 -Slack : -16.698 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[17] +Slack : -17.104 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +To Node : DRAM_DQ[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.500 +Clock Skew : -0.516 +Data Delay : 6.662 -Slack : -16.679 +Slack : -17.077 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.635 + +Slack : -17.075 +From Node : ula:ula_|video:video_|bits[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.281 +Data Delay : 6.868 + +Slack : -17.075 From Node : ula:ula_|video:video_|attr[7] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 6.476 +Clock Skew : -0.281 +Data Delay : 6.868 -Slack : -16.665 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 -To Node : GPIO_1[16] +Slack : -17.073 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.514 +Data Delay : 6.633 + +Slack : -17.054 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.263 +Data Delay : 6.865 + +Slack : -17.045 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.263 +Data Delay : 6.856 + +Slack : -17.023 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.524 -Data Delay : 6.215 +Data Delay : 6.573 -Slack : -16.650 +Slack : -17.022 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.580 + +Slack : -17.014 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.263 +Data Delay : 6.825 + +Slack : -16.999 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.263 +Data Delay : 6.810 + +Slack : -16.991 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.549 + +Slack : -16.989 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.513 +Data Delay : 6.550 + +Slack : -16.987 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.537 + +Slack : -16.979 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.263 +Data Delay : 6.790 + +Slack : -16.941 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.263 +Data Delay : 6.752 + +Slack : -16.938 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.263 +Data Delay : 6.749 + +Slack : -16.920 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.470 + +Slack : -16.903 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.263 +Data Delay : 6.714 + +Slack : -16.878 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.513 +Data Delay : 6.439 + +Slack : -16.876 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.435 + +Slack : -16.854 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 To Node : GPIO_1[21] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.508 -Data Delay : 6.216 +Clock Skew : -0.518 +Data Delay : 6.410 -Slack : -16.637 +Slack : -16.847 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.405 + +Slack : -16.844 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 -To Node : GPIO_1[17] +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.513 +Data Delay : 6.405 + +Slack : -16.832 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : DRAM_DQ[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.523 -Data Delay : 6.188 +Data Delay : 6.383 -Slack : -16.629 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[16] +Slack : -16.823 +From Node : ula:ula_|video:video_|bits[0] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.431 +Clock Skew : -0.281 +Data Delay : 6.616 -Slack : -16.615 +Slack : -16.817 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.263 +Data Delay : 6.628 + +Slack : -16.814 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.372 + +Slack : -16.809 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.367 + +Slack : -16.805 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.508 +Data Delay : 6.371 + +Slack : -16.794 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 To Node : GPIO_1[17] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.524 -Data Delay : 6.165 +Data Delay : 6.344 -Slack : -16.606 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.513 -Data Delay : 6.167 - -Slack : -16.595 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.397 - -Slack : -16.582 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 -To Node : GPIO_1[18] +Slack : -16.780 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 +To Node : DRAM_DQ[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.514 -Data Delay : 6.142 +Data Delay : 6.340 -Slack : -16.567 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 6.364 - -Slack : -16.565 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 6.123 - -Slack : -16.554 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 -To Node : GPIO_1[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 6.104 - -Slack : -16.544 -From Node : ula:ula_|video:video_|bits[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 6.341 - -Slack : -16.541 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.522 -Data Delay : 6.093 - -Slack : -16.539 +Slack : -16.748 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[19] +To Node : GPIO_1[17] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.341 +Clock Skew : -0.263 +Data Delay : 6.559 -Slack : -16.529 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 -To Node : GPIO_1[21] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.508 -Data Delay : 6.095 - -Slack : -16.512 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[23] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.314 - -Slack : -16.511 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.313 - -Slack : -16.483 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 6.041 - -Slack : -16.443 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 -To Node : GPIO_1[21] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.517 -Data Delay : 6.000 - -Slack : -16.425 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.227 - -Slack : -16.422 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.512 -Data Delay : 5.984 - -Slack : -16.415 -From Node : ula:ula_|video:video_|bits[0] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 6.212 - -Slack : -16.393 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 -To Node : GPIO_1[23] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.522 -Data Delay : 5.945 - -Slack : -16.347 +Slack : -16.733 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 To Node : GPIO_1[21] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.510 -Data Delay : 5.911 - -Slack : -16.212 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 -To Node : GPIO_1[23] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.514 -Data Delay : 5.772 - -Slack : -16.157 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.958 - -Slack : -16.155 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 -To Node : GPIO_1[23] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 Clock Skew : -0.521 -Data Delay : 5.708 +Data Delay : 6.286 -Slack : -16.152 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.953 - -Slack : -16.143 -From Node : ula:ula_|video:video_|attr[0] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 5.940 - -Slack : -16.127 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 5.927 - -Slack : -16.121 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 5.921 - -Slack : -16.113 +Slack : -16.722 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[23] +To Node : DRAM_DQ[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 5.915 +Clock Skew : -0.263 +Data Delay : 6.533 -Slack : -16.111 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.912 - -Slack : -16.095 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.896 - -Slack : -16.090 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 5.890 - -Slack : -16.052 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 -To Node : GPIO_1[23] +Slack : -16.718 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : GPIO_1[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.516 -Data Delay : 5.610 +Data Delay : 6.276 -Slack : -16.036 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_B[3] +Slack : -16.715 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : DRAM_DQ[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.837 +Clock Skew : -0.524 +Data Delay : 6.265 -Slack : -16.022 -From Node : ula:ula_|video:video_|bits[5] -To Node : VGA_B[3] +Slack : -16.713 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 5.819 +Clock Skew : -0.263 +Data Delay : 6.524 -Slack : -16.018 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : VGA_B[3] +Slack : -16.712 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 5.815 +Clock Skew : -0.263 +Data Delay : 6.523 -Slack : -15.986 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_B[3] +Slack : -16.705 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.787 +Clock Skew : -0.516 +Data Delay : 6.263 -Slack : -15.982 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : VGA_B[3] +Slack : -16.688 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.783 +Clock Skew : -0.263 +Data Delay : 6.499 -Slack : -15.961 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_R[0] +Slack : -16.672 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[21] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.762 - -Slack : -15.960 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.761 - -Slack : -15.956 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.757 - -Slack : -15.952 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 5.752 - -Slack : -15.931 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 5.731 - -Slack : -15.928 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.729 - -Slack : -15.925 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 5.725 - -Slack : -15.918 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : VGA_G[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 5.718 - -Slack : -15.915 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.716 - -Slack : -15.899 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.700 - -Slack : -15.868 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.669 +Clock Skew : -0.263 +Data Delay : 6.483 +--------------------------------------------------------------------------------+ @@ -11719,905 +15558,905 @@ Data Delay : 5.669 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : -6.686 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.012 -Data Delay : 4.774 - -Slack : -6.590 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.004 -Data Delay : 4.686 - -Slack : -6.554 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.010 -Data Delay : 4.644 - -Slack : -6.499 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.983 -Data Delay : 4.616 - -Slack : -6.497 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.004 -Data Delay : 4.593 - -Slack : -6.479 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.027 -Data Delay : 4.552 - -Slack : -6.476 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.003 -Data Delay : 4.573 - -Slack : -6.457 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.019 -Data Delay : 4.538 - -Slack : -6.451 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.965 -Data Delay : 4.586 - -Slack : -6.417 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.971 -Data Delay : 4.546 - -Slack : -6.411 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.003 -Data Delay : 4.508 - -Slack : -6.338 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.963 -Data Delay : 4.475 - -Slack : -6.321 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.963 -Data Delay : 4.458 - -Slack : -6.320 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.003 -Data Delay : 4.417 - -Slack : -6.306 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.021 -Data Delay : 4.385 - -Slack : -6.299 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.964 -Data Delay : 4.435 - -Slack : -6.296 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.985 -Data Delay : 4.411 - -Slack : -6.294 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.006 -Data Delay : 4.388 - -Slack : -6.293 +Slack : -6.896 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.016 -Data Delay : 4.377 +Clock Skew : -2.023 +Data Delay : 4.973 -Slack : -6.292 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.978 -Data Delay : 4.414 - -Slack : -6.291 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.981 -Data Delay : 4.410 - -Slack : -6.289 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.002 -Data Delay : 4.387 - -Slack : -6.278 +Slack : -6.891 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.019 -Data Delay : 4.359 - -Slack : -6.270 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.970 -Data Delay : 4.400 - -Slack : -6.264 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.013 -Data Delay : 4.351 - -Slack : -6.253 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.005 -Data Delay : 4.348 - -Slack : -6.237 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.016 -Data Delay : 4.321 +Clock Skew : -2.017 +Data Delay : 4.974 -Slack : -6.215 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.008 -Data Delay : 4.307 - -Slack : -6.207 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.962 -Data Delay : 4.345 - -Slack : -6.203 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Slack : -6.815 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 Clock Skew : -1.976 -Data Delay : 4.327 +Data Delay : 4.939 -Slack : -6.198 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.759 -Data Delay : 4.539 - -Slack : -6.179 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.004 -Data Delay : 4.275 - -Slack : -6.173 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.987 -Data Delay : 4.286 - -Slack : -6.161 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.996 -Data Delay : 4.265 - -Slack : -6.145 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.997 -Data Delay : 4.248 - -Slack : -6.145 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.003 -Data Delay : 4.242 - -Slack : -6.142 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.962 -Data Delay : 4.280 - -Slack : -6.128 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.981 -Data Delay : 4.247 - -Slack : -6.124 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.963 -Data Delay : 4.261 - -Slack : -6.106 +Slack : -6.810 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.967 -Data Delay : 4.239 +Clock Skew : -1.970 +Data Delay : 4.940 -Slack : -6.102 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Slack : -6.744 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.751 -Data Delay : 4.451 +Clock Skew : -2.019 +Data Delay : 4.825 -Slack : -6.091 +Slack : -6.718 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.009 -Data Delay : 4.182 +Clock Skew : -2.025 +Data Delay : 4.793 -Slack : -6.091 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.989 -Data Delay : 4.202 - -Slack : -6.091 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.970 -Data Delay : 4.221 - -Slack : -6.072 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.014 -Data Delay : 4.158 - -Slack : -6.065 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.988 -Data Delay : 4.177 - -Slack : -6.064 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.975 -Data Delay : 4.189 - -Slack : -6.063 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.960 -Data Delay : 4.203 - -Slack : -6.062 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.996 -Data Delay : 4.166 - -Slack : -6.055 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.989 -Data Delay : 4.166 - -Slack : -6.051 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.975 -Data Delay : 4.176 - -Slack : -6.051 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.005 -Data Delay : 4.146 - -Slack : -6.040 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.962 -Data Delay : 4.178 - -Slack : -6.039 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.005 -Data Delay : 4.134 - -Slack : -6.036 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.008 -Data Delay : 4.128 - -Slack : -6.026 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.973 -Data Delay : 4.153 - -Slack : -6.022 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.954 -Data Delay : 4.168 - -Slack : -6.019 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.977 -Data Delay : 4.142 - -Slack : -6.009 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.750 -Data Delay : 4.359 - -Slack : -6.006 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.955 -Data Delay : 4.151 - -Slack : -6.004 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.014 -Data Delay : 4.090 - -Slack : -6.004 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.002 -Data Delay : 4.102 - -Slack : -6.004 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.761 -Data Delay : 4.343 - -Slack : -6.001 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.969 -Data Delay : 4.132 - -Slack : -6.000 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.008 -Data Delay : 4.092 - -Slack : -5.988 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.964 -Data Delay : 4.124 - -Slack : -5.988 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.750 -Data Delay : 4.338 - -Slack : -5.985 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.970 -Data Delay : 4.115 - -Slack : -5.983 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.013 -Data Delay : 4.070 - -Slack : -5.978 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.002 -Data Delay : 4.076 - -Slack : -5.973 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.021 -Data Delay : 4.052 - -Slack : -5.972 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.014 -Data Delay : 4.058 - -Slack : -5.970 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.989 -Data Delay : 4.081 - -Slack : -5.965 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.985 -Data Delay : 4.080 - -Slack : -5.963 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.016 -Data Delay : 4.047 - -Slack : -5.955 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.013 -Data Delay : 4.042 - -Slack : -5.952 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.960 -Data Delay : 4.092 - -Slack : -5.950 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.980 -Data Delay : 4.070 - -Slack : -5.939 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.014 -Data Delay : 4.025 - -Slack : -5.937 +Slack : -6.681 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.015 -Data Delay : 4.022 - -Slack : -5.933 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.759 -Data Delay : 4.274 - -Slack : -5.931 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.003 -Data Delay : 4.028 - -Slack : -5.930 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.965 -Data Delay : 4.065 - -Slack : -5.927 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 Clock Skew : -2.016 -Data Delay : 4.011 +Data Delay : 4.765 -Slack : -5.923 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.750 -Data Delay : 4.273 - -Slack : -5.908 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +Slack : -6.673 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.994 -Data Delay : 4.014 +Clock Skew : -2.008 +Data Delay : 4.765 -Slack : -5.896 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Slack : -6.636 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.984 -Data Delay : 4.012 +Clock Skew : -2.019 +Data Delay : 4.717 -Slack : -5.887 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Slack : -6.634 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.999 +Data Delay : 4.735 + +Slack : -6.589 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 Clock Skew : -2.002 -Data Delay : 3.985 +Data Delay : 4.687 -Slack : -5.884 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +Slack : -6.588 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.000 -Data Delay : 3.984 +Clock Skew : -2.012 +Data Delay : 4.676 -Slack : -5.884 +Slack : -6.564 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.011 +Data Delay : 4.653 + +Slack : -6.561 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.012 -Data Delay : 3.972 +Clock Skew : -2.025 +Data Delay : 4.636 -Slack : -5.877 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.966 -Data Delay : 4.011 - -Slack : -5.874 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.976 -Data Delay : 3.998 - -Slack : -5.870 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.000 -Data Delay : 3.970 - -Slack : -5.857 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.002 -Data Delay : 3.955 - -Slack : -5.836 +Slack : -6.556 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.963 -Data Delay : 3.973 +Clock Skew : -1.971 +Data Delay : 4.685 -Slack : -5.826 -From Node : raw_loader_in -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Slack : -6.555 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : 0.180 -Data Delay : 4.106 +Clock Skew : -2.021 +Data Delay : 4.634 -Slack : -5.816 +Slack : -6.518 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.019 +Data Delay : 4.599 + +Slack : -6.511 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.004 +Data Delay : 4.607 + +Slack : -6.503 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.015 +Data Delay : 4.588 + +Slack : -6.483 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.964 +Data Delay : 4.619 + +Slack : -6.444 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.963 +Data Delay : 4.581 + +Slack : -6.437 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.010 +Data Delay : 4.527 + +Slack : -6.417 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.013 +Data Delay : 4.504 + +Slack : -6.405 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.004 +Data Delay : 4.501 + +Slack : -6.399 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.966 +Data Delay : 4.533 + +Slack : -6.395 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.982 +Data Delay : 4.513 + +Slack : -6.389 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.024 +Data Delay : 4.465 + +Slack : -6.385 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.013 +Data Delay : 4.472 + +Slack : -6.378 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.017 +Data Delay : 4.461 + +Slack : -6.374 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.022 +Data Delay : 4.452 + +Slack : -6.370 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.996 +Data Delay : 4.474 + +Slack : -6.359 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.019 +Data Delay : 4.440 + +Slack : -6.351 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.013 +Data Delay : 4.438 + +Slack : -6.342 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.013 +Data Delay : 4.429 + +Slack : -6.325 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.019 +Data Delay : 4.406 + +Slack : -6.323 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.974 +Data Delay : 4.449 + +Slack : -6.315 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.010 +Data Delay : 4.405 + +Slack : -6.313 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.968 +Data Delay : 4.445 + +Slack : -6.307 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.968 +Data Delay : 4.439 + +Slack : -6.301 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.011 +Data Delay : 4.390 + +Slack : -6.289 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.967 +Data Delay : 4.422 + +Slack : -6.286 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.964 +Data Delay : 4.422 + +Slack : -6.282 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.014 +Data Delay : 4.368 + +Slack : -6.264 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.974 +Data Delay : 4.390 + +Slack : -6.256 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.020 +Data Delay : 4.336 + +Slack : -6.254 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.002 +Data Delay : 4.352 + +Slack : -6.253 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.015 +Data Delay : 4.338 + +Slack : -6.252 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.008 +Data Delay : 4.344 + +Slack : -6.252 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.015 +Data Delay : 4.337 + +Slack : -6.240 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.972 +Data Delay : 4.368 + +Slack : -6.229 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.013 +Data Delay : 4.316 + +Slack : -6.226 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.964 -Data Delay : 3.952 +Clock Skew : -1.989 +Data Delay : 4.337 -Slack : -5.814 +Slack : -6.220 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.964 +Data Delay : 4.356 + +Slack : -6.213 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.976 +Data Delay : 4.337 + +Slack : -6.198 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.011 +Data Delay : 4.287 + +Slack : -6.197 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.965 +Data Delay : 4.332 + +Slack : -6.192 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.755 +Data Delay : 4.537 + +Slack : -6.188 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.981 +Data Delay : 4.307 + +Slack : -6.180 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.960 +Data Delay : 4.320 + +Slack : -6.174 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.009 +Data Delay : 4.265 + +Slack : -6.170 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.012 +Data Delay : 4.258 + +Slack : -6.163 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.965 +Data Delay : 4.298 + +Slack : -6.155 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.010 +Data Delay : 4.245 + +Slack : -6.154 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.006 +Data Delay : 4.248 + +Slack : -6.154 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.981 +Data Delay : 4.273 + +Slack : -6.134 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.972 +Data Delay : 4.262 + +Slack : -6.129 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.018 +Data Delay : 4.211 + +Slack : -6.129 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.988 +Data Delay : 4.241 + +Slack : -6.128 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.005 +Data Delay : 4.223 + +Slack : -6.126 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.007 +Data Delay : 4.219 + +Slack : -6.124 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.012 +Data Delay : 4.212 + +Slack : -6.114 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.963 +Data Delay : 4.251 + +Slack : -6.112 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.013 +Data Delay : 4.199 + +Slack : -6.099 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.961 +Data Delay : 4.238 + +Slack : -6.098 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.979 +Data Delay : 4.219 + +Slack : -6.094 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.966 +Data Delay : 4.228 + +Slack : -6.093 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.973 +Data Delay : 4.220 + +Slack : -6.076 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.001 +Data Delay : 4.175 + +Slack : -6.072 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.979 +Data Delay : 4.193 + +Slack : -6.058 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.000 +Data Delay : 4.158 + +Slack : -6.049 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.955 +Data Delay : 4.194 + +Slack : -6.038 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.984 +Data Delay : 4.154 + +Slack : -6.027 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.014 +Data Delay : 4.113 + +Slack : -6.012 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.974 -Data Delay : 3.940 +Clock Skew : -1.958 +Data Delay : 4.154 -Slack : -5.804 -From Node : raw_loader_in -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Slack : -6.002 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : 0.188 -Data Delay : 4.092 +Clock Skew : -1.973 +Data Delay : 4.129 -Slack : -5.794 +Slack : -5.982 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.009 +Data Delay : 4.073 + +Slack : -5.975 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.982 +Data Delay : 4.093 + +Slack : -5.974 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.975 +Data Delay : 4.099 + +Slack : -5.966 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.976 +Data Delay : 4.090 + +Slack : -5.952 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.993 -Data Delay : 3.901 +Clock Skew : -2.014 +Data Delay : 4.038 + +Slack : -5.951 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.964 +Data Delay : 4.087 + +Slack : -5.949 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.964 +Data Delay : 4.085 + +Slack : -5.945 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.014 +Data Delay : 4.031 + +Slack : -5.938 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.005 +Data Delay : 4.033 + +Slack : -5.936 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.960 +Data Delay : 4.076 + +Slack : -5.925 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.974 +Data Delay : 4.051 + +Slack : -5.903 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.974 +Data Delay : 4.029 + +Slack : -5.892 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.001 +Data Delay : 3.991 + +Slack : -5.883 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.961 +Data Delay : 4.022 + +Slack : -5.875 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.969 +Data Delay : 4.006 +--------------------------------------------------------------------------------+ @@ -12625,815 +16464,734 @@ Data Delay : 3.901 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : -4.428 +Slack : -4.422 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.115 -Data Delay : 2.602 +Data Delay : 2.596 -Slack : -4.267 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 2.559 - -Slack : -4.267 +Slack : -4.259 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 2.559 +Data Delay : 2.551 -Slack : -4.074 +Slack : -4.259 From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 2.366 +Data Delay : 2.551 -Slack : -4.074 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 2.366 - -Slack : -4.074 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 2.366 - -Slack : -4.074 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 2.366 - -Slack : -4.074 +Slack : -3.838 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 2.366 +Clock Skew : 0.229 +Data Delay : 2.446 -Slack : -3.711 +Slack : -3.838 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 2.446 + +Slack : -3.838 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 2.446 + +Slack : -3.838 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 2.446 + +Slack : -3.838 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 2.446 + +Slack : -3.705 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 2.003 +Data Delay : 1.997 -Slack : -2.966 +Slack : -2.924 From Node : AUD_ADCDAT To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.208 -Data Delay : 1.553 +Clock Skew : 0.235 +Data Delay : 1.538 -Slack : 17.237 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.241 - -Slack : 17.242 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.236 - -Slack : 17.361 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.117 - -Slack : 17.361 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.117 - -Slack : 17.362 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.116 - -Slack : 17.366 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.112 - -Slack : 17.366 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.112 - -Slack : 17.421 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.057 - -Slack : 17.421 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.057 - -Slack : 17.421 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.057 - -Slack : 17.421 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.057 - -Slack : 17.426 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.052 - -Slack : 17.426 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.052 - -Slack : 17.426 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.052 - -Slack : 17.426 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.052 - -Slack : 17.453 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.025 - -Slack : 17.488 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.990 - -Slack : 17.488 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.990 - -Slack : 17.495 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.983 - -Slack : 17.495 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.983 - -Slack : 17.500 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.978 - -Slack : 17.500 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.978 - -Slack : 17.528 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.949 - -Slack : 17.528 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.949 - -Slack : 17.533 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.944 - -Slack : 17.533 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.944 - -Slack : 17.548 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.930 - -Slack : 17.548 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.930 - -Slack : 17.548 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.930 - -Slack : 17.548 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.930 - -Slack : 17.577 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.901 - -Slack : 17.577 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.901 - -Slack : 17.604 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.874 - -Slack : 17.604 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.874 - -Slack : 17.604 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.874 - -Slack : 17.604 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.874 - -Slack : 17.604 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.874 - -Slack : 17.609 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.869 - -Slack : 17.609 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.869 - -Slack : 17.609 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.869 - -Slack : 17.609 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.869 - -Slack : 17.609 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.869 - -Slack : 17.618 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.860 - -Slack : 17.622 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.856 - -Slack : 17.622 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.856 - -Slack : 17.637 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.841 - -Slack : 17.637 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.841 - -Slack : 17.637 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.841 - -Slack : 17.637 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.841 - -Slack : 17.655 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.822 - -Slack : 17.655 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.822 - -Slack : 17.711 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.767 - -Slack : 17.711 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.767 - -Slack : 17.731 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.747 - -Slack : 17.731 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.747 - -Slack : 17.731 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.747 - -Slack : 17.731 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.747 - -Slack : 17.731 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.747 - -Slack : 17.742 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.736 - -Slack : 17.742 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.736 - -Slack : 17.744 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.733 - -Slack : 17.744 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.733 - -Slack : 17.770 +Slack : 17.066 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.707 +Clock Skew : -0.370 +Data Delay : 3.410 -Slack : 17.775 +Slack : 17.078 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 3.398 + +Slack : 17.200 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.702 +Clock Skew : -0.370 +Data Delay : 3.276 -Slack : 17.802 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.223 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.365 +Data Delay : 3.258 + +Slack : 17.223 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.365 +Data Delay : 3.258 + +Slack : 17.235 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.365 +Data Delay : 3.246 + +Slack : 17.235 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.365 +Data Delay : 3.246 + +Slack : 17.246 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.676 +Clock Skew : -0.370 +Data Delay : 3.230 -Slack : 17.802 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.246 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 3.230 + +Slack : 17.246 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.676 +Clock Skew : -0.370 +Data Delay : 3.230 -Slack : 17.802 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.246 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.676 +Clock Skew : -0.370 +Data Delay : 3.230 -Slack : 17.802 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.246 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.676 +Clock Skew : -0.370 +Data Delay : 3.230 -Slack : 17.820 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Slack : 17.255 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.658 +Clock Skew : -0.370 +Data Delay : 3.221 -Slack : 17.820 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Slack : 17.255 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.658 +Clock Skew : -0.370 +Data Delay : 3.221 -Slack : 17.820 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Slack : 17.258 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.658 +Clock Skew : -0.370 +Data Delay : 3.218 -Slack : 17.820 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Slack : 17.258 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.658 +Clock Skew : -0.370 +Data Delay : 3.218 -Slack : 17.820 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Slack : 17.258 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.658 +Clock Skew : -0.370 +Data Delay : 3.218 -Slack : 17.831 +Slack : 17.258 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 3.218 + +Slack : 17.258 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 3.218 + +Slack : 17.267 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 3.209 + +Slack : 17.267 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 3.209 + +Slack : 17.289 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 3.187 + +Slack : 17.357 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.365 +Data Delay : 3.124 + +Slack : 17.357 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.365 +Data Delay : 3.124 + +Slack : 17.380 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 3.096 + +Slack : 17.380 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 3.096 + +Slack : 17.380 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 3.096 + +Slack : 17.380 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 3.096 + +Slack : 17.380 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 3.096 + +Slack : 17.389 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 3.087 + +Slack : 17.389 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 3.087 + +Slack : 17.446 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.365 +Data Delay : 3.035 + +Slack : 17.446 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.365 +Data Delay : 3.035 + +Slack : 17.469 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 3.007 + +Slack : 17.469 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 3.007 + +Slack : 17.469 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 3.007 + +Slack : 17.469 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 3.007 + +Slack : 17.469 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 3.007 + +Slack : 17.478 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.998 + +Slack : 17.478 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.998 + +Slack : 17.585 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.046 +Data Delay : 3.215 + +Slack : 17.597 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.046 +Data Delay : 3.203 + +Slack : 17.613 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.864 + +Slack : 17.613 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.864 + +Slack : 17.625 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.852 + +Slack : 17.625 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.852 + +Slack : 17.658 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.818 + +Slack : 17.719 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.046 +Data Delay : 3.081 + +Slack : 17.747 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.730 + +Slack : 17.747 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.730 + +Slack : 17.752 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.724 + +Slack : 17.808 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.046 +Data Delay : 2.992 + +Slack : 17.815 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.365 +Data Delay : 2.666 + +Slack : 17.815 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.365 +Data Delay : 2.666 + +Slack : 17.836 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.641 + +Slack : 17.836 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.641 + +Slack : 17.838 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.638 + +Slack : 17.838 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.647 +Clock Skew : -0.370 +Data Delay : 2.638 -Slack : 17.876 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Slack : 17.838 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.602 +Clock Skew : -0.370 +Data Delay : 2.638 -Slack : 17.876 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Slack : 17.838 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.602 +Clock Skew : -0.370 +Data Delay : 2.638 -Slack : 17.890 +Slack : 17.838 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.638 + +Slack : 17.847 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.629 + +Slack : 17.847 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.629 + +Slack : 17.894 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.049 -Data Delay : 2.907 +Clock Skew : -0.370 +Data Delay : 2.582 -Slack : 17.895 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Slack : 17.894 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.049 -Data Delay : 2.902 +Clock Skew : -0.370 +Data Delay : 2.582 -Slack : 17.897 +Slack : 17.894 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.582 + +Slack : 17.894 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.582 + +Slack : 17.906 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.580 +Clock Skew : -0.370 +Data Delay : 2.570 -Slack : 17.909 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Slack : 17.906 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.568 +Clock Skew : -0.370 +Data Delay : 2.570 + +Slack : 17.906 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.570 + +Slack : 17.906 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.570 Slack : 17.909 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] @@ -13441,89 +17199,170 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.568 +Clock Skew : -0.365 +Data Delay : 2.572 -Slack : 17.955 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Slack : 17.909 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.365 +Data Delay : 2.572 + +Slack : 17.932 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.544 + +Slack : 17.932 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.544 + +Slack : 17.932 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.544 + +Slack : 17.932 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.544 + +Slack : 17.932 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.544 + +Slack : 17.941 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.523 +Clock Skew : -0.370 +Data Delay : 2.535 -Slack : 17.955 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Slack : 17.941 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.523 +Clock Skew : -0.370 +Data Delay : 2.535 -Slack : 17.985 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.949 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.493 +Clock Skew : -0.053 +Data Delay : 2.844 -Slack : 17.985 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.949 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.493 +Clock Skew : -0.053 +Data Delay : 2.844 -Slack : 17.985 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.949 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.493 +Clock Skew : -0.053 +Data Delay : 2.844 -Slack : 17.985 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.949 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.493 +Clock Skew : -0.053 +Data Delay : 2.844 -Slack : 17.985 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.949 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.493 +Clock Skew : -0.053 +Data Delay : 2.844 -Slack : 17.986 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Slack : 17.961 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.491 +Clock Skew : -0.053 +Data Delay : 2.832 -Slack : 18.007 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +Slack : 17.961 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.396 -Data Delay : 2.353 +Clock Skew : -0.053 +Data Delay : 2.832 + +Slack : 17.961 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.832 + +Slack : 17.961 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.832 + +Slack : 17.961 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.832 +--------------------------------------------------------------------------------+ @@ -13531,23 +17370,23 @@ Data Delay : 2.353 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; +--------------------------------------------------------------------------------+ -Slack : -2.785 +Slack : -2.786 From Node : SW[2] To Node : ula:ula_|clocks:clocks_|clk_cpu Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Relationship : 0.423 Clock Skew : 0.254 -Data Delay : 1.417 +Data Delay : 1.418 -Slack : 70.539 +Slack : 70.541 From Node : ula:ula_|clocks:clocks_|counter[0] To Node : ula:ula_|clocks:clocks_|clk_cpu Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Relationship : 71.489 Clock Skew : -0.069 -Data Delay : 0.876 +Data Delay : 0.874 Slack : 70.832 From Node : ula:ula_|clocks:clocks_|counter[0] @@ -13570,6 +17409,912 @@ Data Delay : 0.583 ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : 4.148 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.047 +Data Delay : 5.708 + +Slack : 4.171 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.047 +Data Delay : 5.685 + +Slack : 4.243 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.047 +Data Delay : 5.613 + +Slack : 4.282 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.057 +Data Delay : 5.564 + +Slack : 4.293 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.047 +Data Delay : 5.563 + +Slack : 4.315 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.057 +Data Delay : 5.531 + +Slack : 4.332 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.047 +Data Delay : 5.524 + +Slack : 4.335 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.057 +Data Delay : 5.511 + +Slack : 4.351 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 5.497 + +Slack : 4.384 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 5.464 + +Slack : 4.404 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 5.444 + +Slack : 4.444 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.057 +Data Delay : 5.402 + +Slack : 4.446 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.057 +Data Delay : 5.400 + +Slack : 4.446 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.057 +Data Delay : 5.400 + +Slack : 4.463 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.057 +Data Delay : 5.383 + +Slack : 4.513 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 5.335 + +Slack : 4.515 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 5.333 + +Slack : 4.515 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 5.333 + +Slack : 4.532 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 5.316 + +Slack : 4.541 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.057 +Data Delay : 5.305 + +Slack : 4.571 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.060 +Data Delay : 5.274 + +Slack : 4.595 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.057 +Data Delay : 5.251 + +Slack : 4.610 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 5.238 + +Slack : 4.617 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 5.232 + +Slack : 4.628 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.060 +Data Delay : 5.217 + +Slack : 4.650 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 5.199 + +Slack : 4.661 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 5.192 + +Slack : 4.662 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 5.186 + +Slack : 4.664 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.056 +Data Delay : 5.183 + +Slack : 4.664 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.060 +Data Delay : 5.181 + +Slack : 4.670 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 5.179 + +Slack : 4.679 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 5.174 + +Slack : 4.684 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 5.169 + +Slack : 4.690 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.075 +Data Delay : 5.140 + +Slack : 4.691 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.057 +Data Delay : 5.155 + +Slack : 4.701 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 5.152 + +Slack : 4.712 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 5.141 + +Slack : 4.721 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.060 +Data Delay : 5.124 + +Slack : 4.723 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.075 +Data Delay : 5.107 + +Slack : 4.727 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.068 +Data Delay : 5.110 + +Slack : 4.728 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.045 +Data Delay : 5.130 + +Slack : 4.733 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 5.116 + +Slack : 4.743 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.075 +Data Delay : 5.087 + +Slack : 4.753 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.060 +Data Delay : 5.092 + +Slack : 4.756 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 5.092 + +Slack : 4.772 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 5.081 + +Slack : 4.772 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 5.077 + +Slack : 4.780 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 5.069 + +Slack : 4.781 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 5.068 + +Slack : 4.783 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 5.070 + +Slack : 4.784 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.068 +Data Delay : 5.053 + +Slack : 4.798 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 5.051 + +Slack : 4.806 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 5.047 + +Slack : 4.820 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.068 +Data Delay : 5.017 + +Slack : 4.822 +From Node : sdram_controller:sdram_|r.rd_pending +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.045 +Data Delay : 5.036 + +Slack : 4.825 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.048 +Data Delay : 5.030 + +Slack : 4.829 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 5.024 + +Slack : 4.848 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.048 +Data Delay : 5.007 + +Slack : 4.850 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.075 +Data Delay : 4.980 + +Slack : 4.852 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 5.001 + +Slack : 4.854 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.075 +Data Delay : 4.976 + +Slack : 4.854 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.075 +Data Delay : 4.976 + +Slack : 4.858 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.082 +Data Delay : 4.965 + +Slack : 4.861 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 4.992 + +Slack : 4.871 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.075 +Data Delay : 4.959 + +Slack : 4.871 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.082 +Data Delay : 4.952 + +Slack : 4.873 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.082 +Data Delay : 4.950 + +Slack : 4.876 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 4.973 + +Slack : 4.877 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.068 +Data Delay : 4.960 + +Slack : 4.888 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 4.962 + +Slack : 4.892 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.051 +Data Delay : 4.960 + +Slack : 4.892 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.051 +Data Delay : 4.960 + +Slack : 4.909 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.068 +Data Delay : 4.928 + +Slack : 4.913 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 4.936 + +Slack : 4.925 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.082 +Data Delay : 4.898 + +Slack : 4.933 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.082 +Data Delay : 4.890 + +Slack : 4.947 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.048 +Data Delay : 4.908 + +Slack : 4.949 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.075 +Data Delay : 4.881 + +Slack : 4.953 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.046 +Data Delay : 4.904 + +Slack : 4.961 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.058 +Data Delay : 4.886 + +Slack : 4.970 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.048 +Data Delay : 4.885 + +Slack : 4.991 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.075 +Data Delay : 4.839 + +Slack : 4.994 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.082 +Data Delay : 4.829 + +Slack : 4.999 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.053 +Data Delay : 4.851 + +Slack : 5.007 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.058 +Data Delay : 4.840 + +Slack : 5.007 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 4.842 + +Slack : 5.015 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.082 +Data Delay : 4.808 + +Slack : 5.016 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.048 +Data Delay : 4.839 + +Slack : 5.034 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.062 +Data Delay : 4.809 + +Slack : 5.059 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.052 +Data Delay : 4.792 + +Slack : 5.066 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.063 +Data Delay : 4.776 + +Slack : 5.066 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.082 +Data Delay : 4.757 + +Slack : 5.072 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.074 +Data Delay : 4.759 + +Slack : 5.083 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.057 +Data Delay : 4.763 + +Slack : 5.085 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.075 +Data Delay : 4.745 + +Slack : 5.087 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.082 +Data Delay : 4.736 + +Slack : 5.106 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.049 +Data Delay : 4.748 + +Slack : 5.118 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.045 +Data Delay : 4.740 + +Slack : 5.126 +From Node : sdram_controller:sdram_|r.rd_pending +To Node : sdram_controller:sdram_|r.state[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.050 +Data Delay : 4.819 + +Slack : 5.139 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.state[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.059 +Data Delay : 4.797 ++--------------------------------------------------------------------------------+ + + + +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; +--------------------------------------------------------------------------------+ @@ -13591,23 +18336,23 @@ Relationship : 0.000 Clock Skew : 0.069 Data Delay : 0.519 -Slack : 0.518 +Slack : 0.517 From Node : ula:ula_|clocks:clocks_|counter[0] To Node : ula:ula_|clocks:clocks_|clk_cpu Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Relationship : 0.000 Clock Skew : 0.069 -Data Delay : 0.731 +Data Delay : 0.730 -Slack : 1.248 +Slack : 1.246 From Node : SW[2] To Node : ula:ula_|clocks:clocks_|clk_cpu Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Relationship : -0.017 Clock Skew : 0.626 -Data Delay : 1.091 +Data Delay : 1.089 +--------------------------------------------------------------------------------+ @@ -13615,15 +18360,42 @@ Data Delay : 1.091 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 0.300 +Slack : 0.298 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.511 + +Slack : 0.298 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.511 + +Slack : 0.299 From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.067 +Clock Skew : 0.068 Data Delay : 0.511 +Slack : 0.306 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.519 + Slack : 0.306 From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 @@ -13642,18 +18414,18 @@ Relationship : 0.000 Clock Skew : 0.069 Data Delay : 0.519 -Slack : 0.307 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Slack : 0.311 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.519 +Clock Skew : 0.056 +Data Delay : 0.511 Slack : 0.311 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -13670,8 +18442,8 @@ Clock Skew : 0.056 Data Delay : 0.511 Slack : 0.311 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -13679,8 +18451,8 @@ Clock Skew : 0.056 Data Delay : 0.511 Slack : 0.312 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -13688,8 +18460,8 @@ Clock Skew : 0.055 Data Delay : 0.511 Slack : 0.312 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -13715,59 +18487,14 @@ Clock Skew : 0.055 Data Delay : 0.511 Slack : 0.312 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.511 -Slack : 0.312 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - -Slack : 0.312 -From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - -Slack : 0.312 -From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - -Slack : 0.312 -From Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - -Slack : 0.319 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.519 - Slack : 0.319 From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] @@ -13786,131 +18513,158 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.519 -Slack : 0.322 +Slack : 0.323 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.069 -Data Delay : 0.535 +Data Delay : 0.536 + +Slack : 0.337 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.537 + +Slack : 0.338 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.538 + +Slack : 0.338 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.538 + +Slack : 0.338 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.538 Slack : 0.339 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.539 + +Slack : 0.339 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.539 + +Slack : 0.339 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.539 + +Slack : 0.339 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.538 -Slack : 0.342 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Slack : 0.340 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.540 + +Slack : 0.340 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.541 +Data Delay : 0.539 -Slack : 0.342 +Slack : 0.341 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.540 + +Slack : 0.344 From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.541 +Data Delay : 0.543 -Slack : 0.344 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Slack : 0.345 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.543 +Data Delay : 0.544 -Slack : 0.361 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Slack : 0.414 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.561 +Clock Skew : 0.393 +Data Delay : 0.951 -Slack : 0.363 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Slack : 0.415 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.563 +Clock Skew : 0.380 +Data Delay : 0.939 -Slack : 0.418 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.631 - -Slack : 0.418 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.631 - -Slack : 0.419 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.632 - -Slack : 0.419 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.632 - -Slack : 0.421 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.634 - -Slack : 0.469 +Slack : 0.473 From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.668 - -Slack : 0.474 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.673 +Data Delay : 0.672 Slack : 0.487 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] @@ -13921,6 +18675,15 @@ Relationship : 0.000 Clock Skew : 0.069 Data Delay : 0.700 +Slack : 0.489 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.702 + Slack : 0.490 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] @@ -13931,52 +18694,97 @@ Clock Skew : 0.069 Data Delay : 0.703 Slack : 0.491 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.096 -Data Delay : 0.731 - -Slack : 0.492 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.705 - -Slack : 0.498 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.055 +Data Delay : 0.690 + +Slack : 0.492 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.692 + +Slack : 0.494 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.694 + +Slack : 0.495 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.695 + +Slack : 0.496 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.696 + +Slack : 0.497 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 Data Delay : 0.697 -Slack : 0.499 +Slack : 0.497 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.696 + +Slack : 0.497 From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.698 +Data Delay : 0.696 -Slack : 0.501 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Slack : 0.497 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.700 +Clock Skew : 0.056 +Data Delay : 0.697 + +Slack : 0.498 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.698 Slack : 0.501 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] @@ -13990,359 +18798,323 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.701 +Clock Skew : 0.056 +Data Delay : 0.702 -Slack : 0.503 +Slack : 0.505 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.702 +Clock Skew : 0.056 +Data Delay : 0.705 -Slack : 0.503 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.716 - -Slack : 0.507 +Slack : 0.506 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.055 +Clock Skew : 0.056 Data Delay : 0.706 -Slack : 0.508 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Slack : 0.511 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.707 +Clock Skew : 0.056 +Data Delay : 0.711 -Slack : 0.514 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.727 - -Slack : 0.515 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.728 - -Slack : 0.516 +Slack : 0.511 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.715 +Clock Skew : 0.056 +Data Delay : 0.711 -Slack : 0.518 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Slack : 0.516 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.731 - -Slack : 0.518 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.731 - -Slack : 0.518 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.731 - -Slack : 0.518 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.731 - -Slack : 0.518 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.731 - -Slack : 0.518 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.717 - -Slack : 0.519 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.732 +Clock Skew : 0.056 +Data Delay : 0.716 Slack : 0.520 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.719 - -Slack : 0.529 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.728 - -Slack : 0.532 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.387 -Data Delay : 1.063 - -Slack : 0.537 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.736 - -Slack : 0.538 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.737 - -Slack : 0.539 From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.738 +Clock Skew : 0.068 +Data Delay : 0.732 -Slack : 0.547 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Slack : 0.521 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.746 +Clock Skew : 0.056 +Data Delay : 0.721 -Slack : 0.548 +Slack : 0.521 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.721 + +Slack : 0.528 From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.747 +Clock Skew : 0.068 +Data Delay : 0.740 -Slack : 0.561 +Slack : 0.529 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.741 + +Slack : 0.532 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.744 + +Slack : 0.544 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.743 + +Slack : 0.546 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.758 + +Slack : 0.550 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.413 +Data Delay : 1.107 + +Slack : 0.625 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.824 + +Slack : 0.627 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.412 +Data Delay : 1.183 + +Slack : 0.627 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.826 + +Slack : 0.628 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.827 + +Slack : 0.632 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.831 + +Slack : 0.638 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.837 + +Slack : 0.642 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.841 + +Slack : 0.644 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.857 + +Slack : 0.648 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.861 + +Slack : 0.651 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : -0.255 +Data Delay : 0.540 + +Slack : 0.669 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.412 +Data Delay : 1.225 + +Slack : 0.670 From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.056 -Data Delay : 0.761 +Data Delay : 0.870 -Slack : 0.563 +Slack : 0.671 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.870 + +Slack : 0.684 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.883 + +Slack : 0.690 From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.056 -Data Delay : 0.763 +Data Delay : 0.890 -Slack : 0.565 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Slack : 0.694 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.047 +Data Delay : 0.885 + +Slack : 0.697 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.764 +Data Delay : 0.896 -Slack : 0.599 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.799 - -Slack : 0.605 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.805 - -Slack : 0.630 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.829 - -Slack : 0.668 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : -0.265 -Data Delay : 0.547 - -Slack : 0.701 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.901 - -Slack : 0.701 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.901 - -Slack : 0.706 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.905 - -Slack : 0.709 +Slack : 0.707 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.908 - -Slack : 0.709 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.054 +Clock Skew : 0.056 Data Delay : 0.907 -Slack : 0.710 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 0.908 - -Slack : 0.714 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.914 - -Slack : 0.721 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.921 - -Slack : 0.728 +Slack : 0.724 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.927 +Clock Skew : 0.056 +Data Delay : 0.924 -Slack : 0.729 +Slack : 0.727 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.047 +Data Delay : 0.918 + +Slack : 0.730 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.928 +Data Delay : 0.929 Slack : 0.731 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] @@ -14363,16 +19135,34 @@ Clock Skew : 0.069 Data Delay : 0.948 Slack : 0.738 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.937 + +Slack : 0.738 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.069 Data Delay : 0.951 +Slack : 0.739 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.939 + Slack : 0.740 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] @@ -14380,53 +19170,17 @@ Relationship : 0.000 Clock Skew : 0.069 Data Delay : 0.953 -Slack : 0.741 +Slack : 0.745 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.954 - -Slack : 0.744 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.943 - -Slack : 0.745 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.944 - -Slack : 0.745 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.069 Data Delay : 0.958 -Slack : 0.746 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.945 - Slack : 0.747 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] @@ -14435,31 +19189,31 @@ Clock Skew : 0.069 Data Delay : 0.960 Slack : 0.748 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.961 +Clock Skew : 0.056 +Data Delay : 0.948 -Slack : 0.749 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Slack : 0.748 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : -0.261 -Data Delay : 0.632 +Clock Skew : 0.056 +Data Delay : 0.948 -Slack : 0.750 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Slack : 0.752 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.962 +Clock Skew : 0.055 +Data Delay : 0.951 Slack : 0.753 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] @@ -14467,8 +19221,26 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.953 + +Slack : 0.755 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.952 +Data Delay : 0.954 + +Slack : 0.759 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.959 Slack : 0.760 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] @@ -14476,950 +19248,17 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.959 - -Slack : 0.764 -From Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 Clock Skew : 0.056 -Data Delay : 0.964 +Data Delay : 0.960 -Slack : 0.770 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Slack : 0.761 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.969 - -Slack : 0.772 -From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.972 - -Slack : 0.773 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.972 -+--------------------------------------------------------------------------------+ - - - -+--------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Hold: 'CLOCK_50' ; -+--------------------------------------------------------------------------------+ -Slack : 0.304 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.304 -Data Delay : 2.881 - -Slack : 0.359 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.305 -Data Delay : 2.937 - -Slack : 1.206 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.252 -Data Delay : 3.731 - -Slack : 1.215 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.251 -Data Delay : 3.739 - -Slack : 1.221 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.255 -Data Delay : 3.749 - -Slack : 1.229 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.744 - -Slack : 1.234 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.252 -Data Delay : 3.759 - -Slack : 1.240 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 3.758 - -Slack : 1.262 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 3.773 - -Slack : 1.264 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.255 -Data Delay : 3.792 - -Slack : 1.266 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 3.784 - -Slack : 1.278 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.793 - -Slack : 1.287 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.802 - -Slack : 1.332 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.248 -Data Delay : 3.853 - -Slack : 1.340 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 3.858 - -Slack : 1.351 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.240 -Data Delay : 3.864 - -Slack : 1.367 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.241 -Data Delay : 3.881 - -Slack : 1.373 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.251 -Data Delay : 3.897 - -Slack : 1.373 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.237 -Data Delay : 3.883 - -Slack : 1.378 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 3.898 - -Slack : 1.378 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.881 - -Slack : 1.379 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.894 - -Slack : 1.379 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.240 -Data Delay : 3.892 - -Slack : 1.383 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.886 - -Slack : 1.384 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.234 -Data Delay : 3.891 - -Slack : 1.389 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.904 - -Slack : 1.393 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.896 - -Slack : 1.394 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.909 - -Slack : 1.396 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.911 - -Slack : 1.400 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 3.911 - -Slack : 1.401 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.904 - -Slack : 1.402 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.233 -Data Delay : 3.908 - -Slack : 1.405 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 3.925 - -Slack : 1.407 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.241 -Data Delay : 3.921 - -Slack : 1.410 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.240 -Data Delay : 3.923 - -Slack : 1.410 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.241 -Data Delay : 3.924 - -Slack : 1.412 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.927 - -Slack : 1.413 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.233 -Data Delay : 3.919 - -Slack : 1.417 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.240 -Data Delay : 3.930 - -Slack : 1.417 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.920 - -Slack : 1.425 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.251 -Data Delay : 3.949 - -Slack : 1.433 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.248 -Data Delay : 3.954 - -Slack : 1.434 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.234 -Data Delay : 3.941 - -Slack : 1.435 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.938 - -Slack : 1.435 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 3.953 - -Slack : 1.436 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 3.947 - -Slack : 1.440 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.237 -Data Delay : 3.950 - -Slack : 1.442 -From Node : ula:ula_|video:video_|vram_address[8] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.243 -Data Delay : 3.958 - -Slack : 1.449 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 3.960 - -Slack : 1.451 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.234 -Data Delay : 3.958 - -Slack : 1.452 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.310 -Data Delay : 4.035 - -Slack : 1.452 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.237 -Data Delay : 3.962 - -Slack : 1.453 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 3.964 - -Slack : 1.454 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.233 -Data Delay : 3.960 - -Slack : 1.455 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.326 -Data Delay : 4.054 - -Slack : 1.455 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.090 -Data Delay : 3.818 - -Slack : 1.455 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.248 -Data Delay : 3.976 - -Slack : 1.458 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.248 -Data Delay : 3.979 - -Slack : 1.460 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.975 - -Slack : 1.460 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.243 -Data Delay : 3.976 - -Slack : 1.460 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.241 -Data Delay : 3.974 - -Slack : 1.460 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.235 -Data Delay : 3.968 - -Slack : 1.461 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.233 -Data Delay : 3.967 - -Slack : 1.465 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.253 -Data Delay : 3.991 - -Slack : 1.465 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.234 -Data Delay : 3.972 - -Slack : 1.466 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.231 -Data Delay : 3.970 - -Slack : 1.467 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.231 -Data Delay : 3.971 - -Slack : 1.471 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.252 -Data Delay : 3.996 - -Slack : 1.473 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.976 - -Slack : 1.476 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 3.987 - -Slack : 1.480 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.251 -Data Delay : 4.004 - -Slack : 1.481 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.301 -Data Delay : 4.055 - -Slack : 1.482 -From Node : ula:ula_|video:video_|vram_address[8] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.997 - -Slack : 1.485 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.988 - -Slack : 1.485 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 4.003 - -Slack : 1.487 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.234 -Data Delay : 3.994 - -Slack : 1.487 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.309 -Data Delay : 4.069 - -Slack : 1.489 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 4.004 - -Slack : 1.490 -From Node : ula:ula_|video:video_|vram_address[8] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.239 -Data Delay : 4.002 - -Slack : 1.492 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.995 - -Slack : 1.493 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 4.008 - -Slack : 1.494 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.237 -Data Delay : 4.004 - -Slack : 1.494 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.241 -Data Delay : 4.008 - -Slack : 1.496 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.234 -Data Delay : 4.003 - -Slack : 1.498 -From Node : ula:ula_|video:video_|vram_address[8] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 4.009 - -Slack : 1.498 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 4.009 - -Slack : 1.499 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.322 -Data Delay : 4.094 - -Slack : 1.502 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 4.005 - -Slack : 1.503 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 4.014 - -Slack : 1.504 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.231 -Data Delay : 4.008 - -Slack : 1.505 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.248 -Data Delay : 4.026 - -Slack : 1.507 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.252 -Data Delay : 4.032 - -Slack : 1.508 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.246 -Data Delay : 4.027 - -Slack : 1.509 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 4.024 - -Slack : 1.510 -From Node : ula:ula_|video:video_|vram_address[8] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.252 -Data Delay : 4.035 - -Slack : 1.510 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.081 -Data Delay : 3.864 - -Slack : 1.511 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.233 -Data Delay : 4.017 - -Slack : 1.513 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.237 -Data Delay : 4.023 - -Slack : 1.513 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.234 -Data Delay : 4.020 - -Slack : 1.520 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.234 -Data Delay : 4.027 +Data Delay : 0.960 +--------------------------------------------------------------------------------+ @@ -15446,8 +19285,8 @@ Clock Skew : 0.056 Data Delay : 0.511 Slack : 0.311 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ula:ula_|video:video_|vram_address[10] +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vga_vc[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -15455,14 +19294,59 @@ Clock Skew : 0.056 Data Delay : 0.511 Slack : 0.311 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[0] +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vga_vc[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.056 Data Delay : 0.511 +Slack : 0.311 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vga_vc[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.511 + +Slack : 0.311 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vga_vc[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.511 + +Slack : 0.311 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vga_vc[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.511 + +Slack : 0.311 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vga_vc[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + Slack : 0.312 From Node : ula:ula_|video:video_|vga_vc[9] To Node : ula:ula_|video:video_|vga_vc[9] @@ -15473,44 +19357,8 @@ Clock Skew : 0.055 Data Delay : 0.511 Slack : 0.312 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vga_vc[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - -Slack : 0.312 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vga_vc[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - -Slack : 0.312 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - -Slack : 0.312 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : ula:ula_|video:video_|vga_vc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - -Slack : 0.312 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vga_vc[4] +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vga_vc[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -15527,22 +19375,22 @@ Clock Skew : 0.055 Data Delay : 0.511 Slack : 0.312 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|vga_vc[7] +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vga_vc[8] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.511 -Slack : 0.493 +Slack : 0.496 From Node : ula:ula_|video:video_|frame[2] To Node : ula:ula_|video:video_|frame[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.692 +Clock Skew : 0.056 +Data Delay : 0.696 Slack : 0.498 From Node : ula:ula_|video:video_|frame[3] @@ -15550,782 +19398,2585 @@ To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.697 +Clock Skew : 0.056 +Data Delay : 0.698 -Slack : 0.509 +Slack : 0.528 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.728 + +Slack : 0.640 From Node : ula:ula_|video:video_|frame[1] To Node : ula:ula_|video:video_|frame[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.708 +Clock Skew : 0.056 +Data Delay : 0.840 -Slack : 0.512 -From Node : ula:ula_|video:video_|frame[4] -To Node : ula:ula_|video:video_|frame[4] +Slack : 0.727 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.711 +Clock Skew : 0.067 +Data Delay : 0.938 -Slack : 0.596 +Slack : 0.741 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.941 + +Slack : 0.808 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.053 +Data Delay : 1.005 + +Slack : 0.808 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.237 +Data Delay : 0.715 + +Slack : 0.813 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.795 +Data Delay : 1.012 -Slack : 0.652 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.852 - -Slack : 0.737 -From Node : ula:ula_|video:video_|frame[2] -To Node : ula:ula_|video:video_|frame[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.936 - -Slack : 0.747 -From Node : ula:ula_|video:video_|frame[3] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.946 - -Slack : 0.748 -From Node : ula:ula_|video:video_|frame[1] -To Node : ula:ula_|video:video_|frame[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.947 - -Slack : 0.751 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.957 - -Slack : 0.755 -From Node : ula:ula_|video:video_|frame[1] -To Node : ula:ula_|video:video_|frame[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.954 - -Slack : 0.778 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.978 - -Slack : 0.826 -From Node : ula:ula_|video:video_|frame[2] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.025 - -Slack : 0.839 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.038 - -Slack : 0.844 -From Node : ula:ula_|video:video_|frame[1] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.043 - -Slack : 0.885 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.091 - -Slack : 0.901 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.107 - -Slack : 0.911 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 1.114 - -Slack : 0.986 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.191 - -Slack : 0.987 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.192 - -Slack : 0.996 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.201 - -Slack : 0.996 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.201 - -Slack : 1.019 -From Node : ula:ula_|video:video_|bits_prefetch[6] -To Node : ula:ula_|video:video_|bits[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.271 -Data Delay : 0.892 - -Slack : 1.022 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.228 - -Slack : 1.025 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.231 - -Slack : 1.039 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vram_address[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.245 - -Slack : 1.040 -From Node : ula:ula_|video:video_|bits_prefetch[2] -To Node : ula:ula_|video:video_|bits[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.271 -Data Delay : 0.913 - -Slack : 1.041 -From Node : ula:ula_|video:video_|bits_prefetch[1] -To Node : ula:ula_|video:video_|bits[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.271 -Data Delay : 0.914 - -Slack : 1.050 -From Node : ula:ula_|video:video_|bits_prefetch[5] -To Node : ula:ula_|video:video_|bits[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.271 -Data Delay : 0.923 - -Slack : 1.062 +Slack : 0.859 From Node : ula:ula_|video:video_|vga_hc[4] To Node : ula:ula_|video:video_|vram_address[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.268 +Clock Skew : 0.053 +Data Delay : 1.056 -Slack : 1.070 +Slack : 0.875 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.075 + +Slack : 0.882 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.082 + +Slack : 0.922 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.053 +Data Delay : 1.119 + +Slack : 0.925 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vram_address[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.053 +Data Delay : 1.122 + +Slack : 0.925 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vram_address[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.053 +Data Delay : 1.122 + +Slack : 1.003 +From Node : ula:ula_|video:video_|frame[4] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.203 + +Slack : 1.008 +From Node : ula:ula_|video:video_|bits_prefetch[2] +To Node : ula:ula_|video:video_|bits[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.237 +Data Delay : 0.915 + +Slack : 1.015 +From Node : ula:ula_|video:video_|bits_prefetch[1] +To Node : ula:ula_|video:video_|bits[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.237 +Data Delay : 0.922 + +Slack : 1.018 +From Node : ula:ula_|video:video_|bits_prefetch[5] +To Node : ula:ula_|video:video_|bits[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.237 +Data Delay : 0.925 + +Slack : 1.030 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.053 +Data Delay : 1.227 + +Slack : 1.035 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.053 +Data Delay : 1.232 + +Slack : 1.047 From Node : ula:ula_|video:video_|frame[0] To Node : ula:ula_|video:video_|frame[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.269 +Clock Skew : -0.237 +Data Delay : 0.954 -Slack : 1.082 +Slack : 1.052 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.053 +Data Delay : 1.249 + +Slack : 1.054 From Node : ula:ula_|video:video_|frame[0] To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.281 +Clock Skew : -0.237 +Data Delay : 0.961 -Slack : 1.106 +Slack : 1.096 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.053 +Data Delay : 1.293 + +Slack : 1.104 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : ula:ula_|video:video_|vga_hc[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.303 + +Slack : 1.115 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.313 + +Slack : 1.118 From Node : ula:ula_|video:video_|vga_hc[6] To Node : ula:ula_|video:video_|vram_address[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.312 +Clock Skew : 0.053 +Data Delay : 1.315 -Slack : 1.130 -From Node : ula:ula_|video:video_|vga_vc[4] +Slack : 1.119 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.053 +Data Delay : 1.316 + +Slack : 1.124 +From Node : ula:ula_|video:video_|bits_prefetch[4] +To Node : ula:ula_|video:video_|bits[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.237 +Data Delay : 1.031 + +Slack : 1.124 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.053 +Data Delay : 1.321 + +Slack : 1.124 +From Node : ula:ula_|video:video_|vga_vc[5] To Node : ula:ula_|video:video_|vram_address[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.336 +Clock Skew : 0.054 +Data Delay : 1.322 -Slack : 1.143 +Slack : 1.126 From Node : ula:ula_|video:video_|vga_vc[6] To Node : ula:ula_|video:video_|vram_address[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.349 +Clock Skew : 0.053 +Data Delay : 1.323 -Slack : 1.145 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.345 - -Slack : 1.145 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.345 - -Slack : 1.145 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.345 - -Slack : 1.145 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.345 - -Slack : 1.151 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.357 - -Slack : 1.153 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vga_hc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.353 - -Slack : 1.154 +Slack : 1.134 From Node : ula:ula_|video:video_|vga_vc[3] To Node : ula:ula_|video:video_|vram_address[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.360 +Clock Skew : 0.054 +Data Delay : 1.332 -Slack : 1.166 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[4] +Slack : 1.140 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.365 +Clock Skew : 0.053 +Data Delay : 1.337 -Slack : 1.168 +Slack : 1.141 From Node : ula:ula_|video:video_|vga_vc[3] To Node : ula:ula_|video:video_|vram_address[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.374 +Clock Skew : 0.054 +Data Delay : 1.339 -Slack : 1.170 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|vram_address[10] +Slack : 1.151 +From Node : ula:ula_|video:video_|bits_prefetch[7] +To Node : ula:ula_|video:video_|bits[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.057 -Data Delay : 1.371 +Clock Skew : -0.237 +Data Delay : 1.058 -Slack : 1.172 -From Node : ula:ula_|video:video_|bits_prefetch[0] -To Node : ula:ula_|video:video_|bits[0] +Slack : 1.155 +From Node : ula:ula_|video:video_|attr_prefetch[0] +To Node : ula:ula_|video:video_|attr[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.271 -Data Delay : 1.045 +Clock Skew : -0.263 +Data Delay : 1.036 -Slack : 1.174 -From Node : ula:ula_|video:video_|vga_hc[9] +Slack : 1.156 +From Node : ula:ula_|video:video_|attr_prefetch[3] +To Node : ula:ula_|video:video_|attr[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.264 +Data Delay : 1.036 + +Slack : 1.157 +From Node : ula:ula_|video:video_|attr_prefetch[6] +To Node : ula:ula_|video:video_|attr[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.264 +Data Delay : 1.037 + +Slack : 1.178 +From Node : ula:ula_|video:video_|attr_prefetch[4] +To Node : ula:ula_|video:video_|attr[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.264 +Data Delay : 1.058 + +Slack : 1.180 +From Node : ula:ula_|video:video_|attr_prefetch[1] +To Node : ula:ula_|video:video_|attr[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.263 +Data Delay : 1.061 + +Slack : 1.182 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.380 + +Slack : 1.183 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.053 +Data Delay : 1.380 + +Slack : 1.183 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.053 +Data Delay : 1.380 + +Slack : 1.186 +From Node : ula:ula_|video:video_|attr_prefetch[5] +To Node : ula:ula_|video:video_|attr[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.264 +Data Delay : 1.066 + +Slack : 1.202 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.400 + +Slack : 1.208 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.406 + +Slack : 1.221 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.419 + +Slack : 1.228 +From Node : ula:ula_|video:video_|vga_hc[4] To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.374 +Clock Skew : 0.054 +Data Delay : 1.426 -Slack : 1.176 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : ula:ula_|video:video_|vga_hc[9] +Slack : 1.230 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.428 + +Slack : 1.233 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|vga_vc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.432 + +Slack : 1.233 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|vga_vc[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.432 + +Slack : 1.257 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.455 + +Slack : 1.267 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.466 + +Slack : 1.268 +From Node : ula:ula_|video:video_|frame[3] +To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.056 -Data Delay : 1.376 +Data Delay : 1.468 -Slack : 1.176 +Slack : 1.278 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.476 + +Slack : 1.280 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.478 + +Slack : 1.298 +From Node : ula:ula_|video:video_|bits_prefetch[3] +To Node : ula:ula_|video:video_|bits[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.237 +Data Delay : 1.205 + +Slack : 1.316 +From Node : ula:ula_|video:video_|attr_prefetch[7] +To Node : ula:ula_|video:video_|attr[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.264 +Data Delay : 1.196 + +Slack : 1.351 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.551 + +Slack : 1.353 From Node : ula:ula_|video:video_|vga_hc[2] To Node : ula:ula_|video:video_|vga_hc[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.056 -Data Delay : 1.376 +Data Delay : 1.553 -Slack : 1.182 -From Node : ula:ula_|video:video_|attr_prefetch[3] -To Node : ula:ula_|video:video_|attr[3] +Slack : 1.353 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.298 -Data Delay : 1.028 +Clock Skew : 0.054 +Data Delay : 1.551 -Slack : 1.183 +Slack : 1.353 From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[5] +To Node : ula:ula_|video:video_|vram_address[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.389 +Clock Skew : 0.054 +Data Delay : 1.551 -Slack : 1.184 -From Node : ula:ula_|video:video_|bits_prefetch[4] -To Node : ula:ula_|video:video_|bits[4] +Slack : 1.370 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.271 -Data Delay : 1.057 +Clock Skew : 0.054 +Data Delay : 1.568 -Slack : 1.200 -From Node : ula:ula_|video:video_|vga_vc[2] +Slack : 1.373 +From Node : ula:ula_|video:video_|vga_vc[4] To Node : ula:ula_|video:video_|vram_address[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.406 +Clock Skew : 0.054 +Data Delay : 1.571 -Slack : 1.207 -From Node : ula:ula_|video:video_|attr_prefetch[5] -To Node : ula:ula_|video:video_|attr[5] +Slack : 1.382 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vga_vc[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.298 -Data Delay : 1.053 +Clock Skew : 0.056 +Data Delay : 1.582 -Slack : 1.219 +Slack : 1.385 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vga_vc[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.585 + +Slack : 1.413 From Node : ula:ula_|video:video_|vga_vc[4] To Node : ula:ula_|video:video_|vram_address[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.425 +Clock Skew : 0.054 +Data Delay : 1.611 -Slack : 1.223 -From Node : ula:ula_|video:video_|attr_prefetch[7] -To Node : ula:ula_|video:video_|attr[7] +Slack : 1.413 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vram_address[10] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.298 -Data Delay : 1.069 +Clock Skew : 0.053 +Data Delay : 1.610 -Slack : 1.225 -From Node : ula:ula_|video:video_|attr_prefetch[4] -To Node : ula:ula_|video:video_|attr[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.298 -Data Delay : 1.071 - -Slack : 1.240 -From Node : ula:ula_|video:video_|attr_prefetch[0] -To Node : ula:ula_|video:video_|attr[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.298 -Data Delay : 1.086 - -Slack : 1.242 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vga_hc[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.442 - -Slack : 1.243 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.449 - -Slack : 1.250 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.456 - -Slack : 1.250 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.456 - -Slack : 1.257 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.457 - -Slack : 1.261 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.467 - -Slack : 1.264 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vga_hc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 1.467 - -Slack : 1.268 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.474 - -Slack : 1.277 -From Node : ula:ula_|video:video_|vga_hc[6] +Slack : 1.414 +From Node : ula:ula_|video:video_|vga_hc[8] To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 1.480 +Clock Skew : 0.054 +Data Delay : 1.612 -Slack : 1.279 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[7] +Slack : 1.421 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|vga_vc[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.485 +Clock Skew : 0.055 +Data Delay : 1.620 -Slack : 1.320 +Slack : 1.426 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.626 + +Slack : 1.437 +From Node : ula:ula_|video:video_|bits_prefetch[6] +To Node : ula:ula_|video:video_|bits[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.237 +Data Delay : 1.344 + +Slack : 1.446 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.645 + +Slack : 1.446 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.645 + +Slack : 1.446 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.645 + +Slack : 1.446 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.645 + +Slack : 1.446 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.645 + +Slack : 1.463 From Node : ula:ula_|video:video_|vga_hc[0] To Node : ula:ula_|video:video_|attr_prefetch[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.422 -Data Delay : 1.886 +Clock Skew : 0.390 +Data Delay : 1.997 -Slack : 1.320 +Slack : 1.463 From Node : ula:ula_|video:video_|vga_hc[0] To Node : ula:ula_|video:video_|attr_prefetch[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.422 -Data Delay : 1.886 +Clock Skew : 0.390 +Data Delay : 1.997 -Slack : 1.320 +Slack : 1.463 From Node : ula:ula_|video:video_|vga_hc[0] To Node : ula:ula_|video:video_|attr_prefetch[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.422 -Data Delay : 1.886 +Clock Skew : 0.390 +Data Delay : 1.997 -Slack : 1.320 +Slack : 1.463 From Node : ula:ula_|video:video_|vga_hc[0] To Node : ula:ula_|video:video_|attr_prefetch[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.422 -Data Delay : 1.886 +Clock Skew : 0.390 +Data Delay : 1.997 -Slack : 1.320 +Slack : 1.463 From Node : ula:ula_|video:video_|vga_hc[0] To Node : ula:ula_|video:video_|attr_prefetch[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.422 -Data Delay : 1.886 +Clock Skew : 0.390 +Data Delay : 1.997 -Slack : 1.320 +Slack : 1.463 From Node : ula:ula_|video:video_|vga_hc[0] To Node : ula:ula_|video:video_|attr_prefetch[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.422 -Data Delay : 1.886 +Clock Skew : 0.390 +Data Delay : 1.997 -Slack : 1.320 +Slack : 1.463 From Node : ula:ula_|video:video_|vga_hc[0] To Node : ula:ula_|video:video_|attr_prefetch[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.422 -Data Delay : 1.886 +Clock Skew : 0.390 +Data Delay : 1.997 -Slack : 1.320 +Slack : 1.463 From Node : ula:ula_|video:video_|vga_hc[0] To Node : ula:ula_|video:video_|attr_prefetch[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.422 -Data Delay : 1.886 +Clock Skew : 0.390 +Data Delay : 1.997 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : 0.312 +From Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1 +To Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : sdram_controller:sdram_|r.rf_pending +To Node : sdram_controller:sdram_|r.rf_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.313 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.wr_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.511 + +Slack : 0.313 +From Node : sdram_controller:sdram_|r.rd_pending +To Node : sdram_controller:sdram_|r.rd_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.511 + +Slack : 0.313 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.state[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.511 + +Slack : 0.321 +From Node : sdram_controller:sdram_|r.init_counter[0] +To Node : sdram_controller:sdram_|r.init_counter[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.519 + +Slack : 0.337 +From Node : sdram_controller:sdram_|r.rf_counter[9] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.536 + +Slack : 0.470 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.state[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.668 + +Slack : 0.500 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.699 + +Slack : 0.500 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.698 + +Slack : 0.501 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.700 + +Slack : 0.502 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.701 + +Slack : 0.502 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.701 + +Slack : 0.502 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.700 + +Slack : 0.503 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.702 + +Slack : 0.503 +From Node : sdram_controller:sdram_|r.rf_counter[7] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.702 + +Slack : 0.505 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.704 + +Slack : 0.505 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.703 + +Slack : 0.505 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.703 + +Slack : 0.506 +From Node : sdram_controller:sdram_|r.rf_counter[8] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.705 + +Slack : 0.512 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.710 + +Slack : 0.513 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.711 + +Slack : 0.513 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.711 + +Slack : 0.514 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.712 + +Slack : 0.516 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.714 + +Slack : 0.516 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.714 + +Slack : 0.518 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.717 + +Slack : 0.518 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.716 + +Slack : 0.533 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.731 + +Slack : 0.535 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.733 + +Slack : 0.544 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.state[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.742 + +Slack : 0.547 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.state[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.745 + +Slack : 0.548 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.state[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.746 + +Slack : 0.744 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.943 + +Slack : 0.746 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.945 + +Slack : 0.746 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.945 + +Slack : 0.748 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.946 + +Slack : 0.748 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.946 + +Slack : 0.748 +From Node : sdram_controller:sdram_|r.rf_counter[7] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.947 + +Slack : 0.749 +From Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 +To Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.947 + +Slack : 0.749 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.state[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.947 + +Slack : 0.750 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.948 + +Slack : 0.751 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.950 + +Slack : 0.751 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.950 + +Slack : 0.752 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.951 + +Slack : 0.754 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.953 + +Slack : 0.755 +From Node : sdram_controller:sdram_|r.rf_counter[8] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.954 + +Slack : 0.757 +From Node : sdram_controller:sdram_|r.address[4]~_Duplicate_1 +To Node : sdram_controller:sdram_|r.address[4]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.955 + +Slack : 0.757 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.955 + +Slack : 0.757 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.955 + +Slack : 0.758 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.957 + +Slack : 0.758 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.957 + +Slack : 0.759 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.958 + +Slack : 0.761 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.959 + +Slack : 0.761 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.960 + +Slack : 0.763 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.961 + +Slack : 0.763 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.961 + +Slack : 0.767 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.965 + +Slack : 0.767 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.965 + +Slack : 0.769 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.967 + +Slack : 0.770 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.968 + +Slack : 0.770 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.968 + +Slack : 0.774 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.972 + +Slack : 0.774 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.972 + +Slack : 0.776 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.974 + +Slack : 0.778 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.976 + +Slack : 0.808 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.state[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.006 + +Slack : 0.813 +From Node : sdram_controller:sdram_|r.rf_counter[9] +To Node : sdram_controller:sdram_|r.rf_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.012 + +Slack : 0.818 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.state[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.016 + +Slack : 0.833 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.032 + +Slack : 0.835 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.034 + +Slack : 0.835 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.034 + +Slack : 0.837 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.035 + +Slack : 0.837 +From Node : sdram_controller:sdram_|r.rf_counter[7] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.036 + +Slack : 0.840 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.039 + +Slack : 0.842 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.041 + +Slack : 0.842 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.041 + +Slack : 0.844 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.042 + +Slack : 0.846 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.044 + +Slack : 0.847 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.046 + +Slack : 0.847 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.046 + +Slack : 0.848 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.047 + +Slack : 0.850 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.048 + +Slack : 0.850 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.049 + +Slack : 0.853 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.051 + +Slack : 0.854 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.053 + +Slack : 0.855 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.054 + +Slack : 0.857 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.055 + +Slack : 0.857 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.056 + +Slack : 0.858 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.056 + +Slack : 0.859 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.057 + +Slack : 0.859 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.057 + +Slack : 0.863 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.061 + +Slack : 0.863 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.061 + +Slack : 0.865 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.063 + +Slack : 0.866 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.064 + +Slack : 0.866 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.064 + +Slack : 0.867 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.065 + +Slack : 0.870 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.068 + +Slack : 0.870 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.068 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'CLOCK_50' ; ++--------------------------------------------------------------------------------+ +Slack : 0.339 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.538 + +Slack : 0.616 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.314 +Data Delay : 3.203 + +Slack : 0.649 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.317 +Data Delay : 3.239 + +Slack : 0.837 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.313 +Data Delay : 3.423 + +Slack : 0.859 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.315 +Data Delay : 3.447 + +Slack : 1.264 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.318 +Data Delay : 3.855 + +Slack : 1.268 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.070 +Data Delay : 3.611 + +Slack : 1.292 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 3.807 + +Slack : 1.306 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.325 +Data Delay : 3.904 + +Slack : 1.317 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.318 +Data Delay : 3.908 + +Slack : 1.319 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.322 +Data Delay : 3.914 + +Slack : 1.324 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.238 +Data Delay : 3.835 + +Slack : 1.328 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.062 +Data Delay : 3.663 + +Slack : 1.331 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.251 +Data Delay : 3.855 + +Slack : 1.332 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.331 +Data Delay : 3.936 + +Slack : 1.335 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.323 +Data Delay : 3.931 + +Slack : 1.337 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.245 +Data Delay : 3.855 Slack : 1.339 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vram_address[7] +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.545 +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.238 +Data Delay : 3.850 -Slack : 1.345 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|vga_hc[9] +Slack : 1.342 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 1.548 +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.062 +Data Delay : 3.677 + +Slack : 1.348 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.245 +Data Delay : 3.866 Slack : 1.349 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[6] +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.394 -Data Delay : 1.887 +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 3.864 -Slack : 1.349 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[5] +Slack : 1.356 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.394 -Data Delay : 1.887 +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.062 +Data Delay : 3.691 -Slack : 1.349 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[7] +Slack : 1.358 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.394 -Data Delay : 1.887 +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.251 +Data Delay : 3.882 -Slack : 1.349 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[4] +Slack : 1.358 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.394 -Data Delay : 1.887 +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.238 +Data Delay : 3.869 -Slack : 1.349 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[2] +Slack : 1.360 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.394 -Data Delay : 1.887 +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.318 +Data Delay : 3.951 -Slack : 1.349 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[1] +Slack : 1.364 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.394 -Data Delay : 1.887 +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.252 +Data Delay : 3.889 -Slack : 1.349 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[3] +Slack : 1.365 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.394 -Data Delay : 1.887 +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.252 +Data Delay : 3.890 -Slack : 1.349 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[0] +Slack : 1.375 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.394 -Data Delay : 1.887 +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.066 +Data Delay : 3.714 -Slack : 1.357 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[7] +Slack : 1.375 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.563 +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.322 +Data Delay : 3.970 -Slack : 1.362 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[8] +Slack : 1.376 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.562 +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.076 +Data Delay : 3.725 + +Slack : 1.381 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.251 +Data Delay : 3.905 + +Slack : 1.383 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.238 +Data Delay : 3.894 + +Slack : 1.383 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.318 +Data Delay : 3.974 + +Slack : 1.384 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.074 +Data Delay : 3.731 + +Slack : 1.385 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.252 +Data Delay : 3.910 + +Slack : 1.385 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.310 +Data Delay : 3.968 + +Slack : 1.386 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.243 +Data Delay : 3.902 + +Slack : 1.391 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.067 +Data Delay : 3.731 + +Slack : 1.391 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.323 +Data Delay : 3.987 + +Slack : 1.392 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.077 +Data Delay : 3.742 + +Slack : 1.395 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.313 +Data Delay : 3.981 + +Slack : 1.396 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.054 +Data Delay : 3.723 + +Slack : 1.397 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.055 +Data Delay : 3.725 + +Slack : 1.398 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.069 +Data Delay : 3.740 + +Slack : 1.400 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.075 +Data Delay : 3.748 + +Slack : 1.401 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 3.916 + +Slack : 1.402 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.325 +Data Delay : 4.000 + +Slack : 1.405 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.244 +Data Delay : 3.922 + +Slack : 1.405 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.908 + +Slack : 1.408 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.252 +Data Delay : 3.933 + +Slack : 1.408 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.244 +Data Delay : 3.925 + +Slack : 1.411 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 3.926 + +Slack : 1.419 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.238 +Data Delay : 3.930 + +Slack : 1.421 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.315 +Data Delay : 4.009 + +Slack : 1.423 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.237 +Data Delay : 3.933 + +Slack : 1.427 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.251 +Data Delay : 3.951 + +Slack : 1.427 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.310 +Data Delay : 4.010 + +Slack : 1.430 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.238 +Data Delay : 3.941 + +Slack : 1.432 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.234 +Data Delay : 3.939 + +Slack : 1.434 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.937 + +Slack : 1.436 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.331 +Data Delay : 4.040 + +Slack : 1.438 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 3.953 + +Slack : 1.442 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.252 +Data Delay : 3.967 + +Slack : 1.442 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.245 +Data Delay : 3.960 + +Slack : 1.449 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.952 + +Slack : 1.449 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.233 +Data Delay : 3.955 + +Slack : 1.450 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.322 +Data Delay : 4.045 + +Slack : 1.451 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.245 +Data Delay : 3.969 + +Slack : 1.451 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.310 +Data Delay : 4.034 + +Slack : 1.451 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.065 +Data Delay : 3.789 + +Slack : 1.454 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.244 +Data Delay : 3.971 + +Slack : 1.456 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.233 +Data Delay : 3.962 + +Slack : 1.456 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 3.971 + +Slack : 1.458 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.971 + +Slack : 1.459 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.243 +Data Delay : 3.975 + +Slack : 1.461 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.238 +Data Delay : 3.972 + +Slack : 1.462 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 3.977 + +Slack : 1.466 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.243 +Data Delay : 3.982 + +Slack : 1.468 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.971 + +Slack : 1.469 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.235 +Data Delay : 3.977 + +Slack : 1.470 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.066 +Data Delay : 3.809 + +Slack : 1.471 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.974 + +Slack : 1.474 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.238 +Data Delay : 3.985 + +Slack : 1.475 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.235 +Data Delay : 3.983 + +Slack : 1.477 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 3.992 + +Slack : 1.481 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.244 +Data Delay : 3.998 + +Slack : 1.481 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.234 +Data Delay : 3.988 + +Slack : 1.481 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.235 +Data Delay : 3.989 + +Slack : 1.481 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 3.996 + +Slack : 1.484 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.235 +Data Delay : 3.992 + +Slack : 1.486 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 4.001 + +Slack : 1.486 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.067 +Data Delay : 3.826 + +Slack : 1.487 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.084 +Data Delay : 3.844 + +Slack : 1.487 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.065 +Data Delay : 3.825 + +Slack : 1.487 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.230 +Data Delay : 3.990 + +Slack : 1.487 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 4.002 + +Slack : 1.488 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.237 +Data Delay : 3.998 + +Slack : 1.488 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.238 +Data Delay : 3.999 + +Slack : 1.488 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.233 +Data Delay : 3.994 + +Slack : 1.488 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.063 +Data Delay : 3.824 +--------------------------------------------------------------------------------+ @@ -16333,743 +21984,743 @@ Data Delay : 1.562 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : -5.744 +Slack : -5.735 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.088 -Data Delay : 3.943 +Data Delay : 3.934 -Slack : -5.744 +Slack : -5.735 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.090 -Data Delay : 3.941 +Data Delay : 3.932 -Slack : -5.744 +Slack : -5.735 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.091 -Data Delay : 3.940 +Data Delay : 3.931 -Slack : -5.743 +Slack : -5.734 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.091 -Data Delay : 3.939 +Data Delay : 3.930 -Slack : -5.743 +Slack : -5.734 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.092 -Data Delay : 3.938 +Data Delay : 3.929 -Slack : -5.507 +Slack : -5.485 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.115 -Data Delay : 3.681 +Data Delay : 3.659 -Slack : -5.494 +Slack : -5.485 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.116 -Data Delay : 3.667 +Data Delay : 3.658 -Slack : -5.257 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.549 - -Slack : -5.257 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.549 - -Slack : -5.257 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.549 - -Slack : -5.257 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.549 - -Slack : -5.257 +Slack : -5.248 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 3.549 +Data Delay : 3.540 -Slack : -5.257 +Slack : -5.248 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.088 -Data Delay : 3.548 - -Slack : -5.257 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.088 -Data Delay : 3.548 - -Slack : -5.257 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 3.549 +Data Delay : 3.540 -Slack : -5.257 +Slack : -5.248 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 3.549 +Data Delay : 3.540 -Slack : -5.256 +Slack : -5.248 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.090 -Data Delay : 3.545 +Clock Skew : -0.084 +Data Delay : 3.543 -Slack : -5.256 +Slack : -5.248 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.090 -Data Delay : 3.545 +Clock Skew : -0.084 +Data Delay : 3.543 -Slack : -5.256 +Slack : -5.248 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.090 -Data Delay : 3.545 +Clock Skew : -0.084 +Data Delay : 3.543 -Slack : -5.256 +Slack : -5.248 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.090 -Data Delay : 3.545 +Clock Skew : -0.084 +Data Delay : 3.543 -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.090 -Data Delay : 3.545 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.091 -Data Delay : 3.544 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.090 -Data Delay : 3.545 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.091 -Data Delay : 3.544 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.090 -Data Delay : 3.545 - -Slack : -5.256 +Slack : -5.248 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.090 -Data Delay : 3.545 +Clock Skew : -0.084 +Data Delay : 3.543 -Slack : -5.256 +Slack : -5.248 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.090 -Data Delay : 3.545 +Clock Skew : -0.084 +Data Delay : 3.543 -Slack : -5.256 +Slack : -5.248 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.088 -Data Delay : 3.547 +Data Delay : 3.539 -Slack : -5.256 +Slack : -5.248 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.088 -Data Delay : 3.547 +Data Delay : 3.539 -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.548 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.548 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.548 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.548 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.548 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.548 - -Slack : -5.256 +Slack : -5.248 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.548 +Clock Skew : -0.088 +Data Delay : 3.539 -Slack : -5.256 +Slack : -5.248 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.548 +Clock Skew : -0.088 +Data Delay : 3.539 -Slack : -5.256 +Slack : -5.248 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.548 +Clock Skew : -0.088 +Data Delay : 3.539 -Slack : -5.256 +Slack : -5.248 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.540 + +Slack : -5.247 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.084 +Data Delay : 3.542 + +Slack : -5.247 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.084 +Data Delay : 3.542 + +Slack : -5.247 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.084 +Data Delay : 3.542 + +Slack : -5.247 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.084 +Data Delay : 3.542 + +Slack : -5.247 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.084 +Data Delay : 3.542 + +Slack : -5.247 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.539 + +Slack : -5.247 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.083 +Data Delay : 3.543 + +Slack : -5.247 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.083 +Data Delay : 3.543 + +Slack : -5.247 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.548 +Clock Skew : -0.088 +Data Delay : 3.538 -Slack : -5.256 +Slack : -5.247 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.548 +Clock Skew : -0.088 +Data Delay : 3.538 -Slack : -5.256 +Slack : -5.247 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.548 +Clock Skew : -0.088 +Data Delay : 3.538 -Slack : -5.256 +Slack : -5.247 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.548 +Clock Skew : -0.088 +Data Delay : 3.538 -Slack : -5.256 +Slack : -5.247 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.548 +Clock Skew : -0.088 +Data Delay : 3.538 -Slack : -5.256 +Slack : -5.247 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.088 +Data Delay : 3.538 + +Slack : -5.247 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.548 +Clock Skew : -0.088 +Data Delay : 3.538 -Slack : -5.256 +Slack : -5.247 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.548 +Clock Skew : -0.088 +Data Delay : 3.538 -Slack : -5.256 +Slack : -5.247 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.091 -Data Delay : 3.544 +Clock Skew : -0.084 +Data Delay : 3.542 -Slack : -5.256 +Slack : -5.247 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.091 -Data Delay : 3.544 +Clock Skew : -0.084 +Data Delay : 3.542 -Slack : -5.256 +Slack : -5.247 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.091 -Data Delay : 3.544 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.089 -Data Delay : 3.546 - -Slack : -4.963 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.208 -Data Delay : 3.550 - -Slack : -4.959 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.212 -Data Delay : 3.547 - -Slack : -4.959 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.212 -Data Delay : 3.547 - -Slack : -4.959 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.212 -Data Delay : 3.547 - -Slack : -4.959 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.212 -Data Delay : 3.547 - -Slack : -4.959 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.212 -Data Delay : 3.547 - -Slack : -4.959 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.212 -Data Delay : 3.547 - -Slack : -4.941 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.223 -Data Delay : 3.543 - -Slack : -4.941 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.223 -Data Delay : 3.543 - -Slack : -4.941 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.223 -Data Delay : 3.543 - -Slack : -4.941 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.223 -Data Delay : 3.543 - -Slack : -4.941 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.223 -Data Delay : 3.543 - -Slack : -4.940 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.223 +Clock Skew : -0.084 Data Delay : 3.542 -Slack : -4.940 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.223 -Data Delay : 3.542 - -Slack : -4.940 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.223 -Data Delay : 3.542 - -Slack : -4.940 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.223 -Data Delay : 3.542 - -Slack : -4.940 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.223 -Data Delay : 3.542 - -Slack : -4.940 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.227 -Data Delay : 3.546 - -Slack : -4.936 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.232 -Data Delay : 3.547 - -Slack : -4.936 +Slack : -5.242 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 +Clock Skew : -0.076 +Data Delay : 3.545 -Slack : -4.936 +Slack : -5.242 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 +Clock Skew : -0.076 +Data Delay : 3.545 -Slack : -4.936 +Slack : -5.242 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 +Clock Skew : -0.076 +Data Delay : 3.545 -Slack : -4.936 +Slack : -5.242 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 +Clock Skew : -0.076 +Data Delay : 3.545 -Slack : -4.936 +Slack : -5.242 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 +Clock Skew : -0.076 +Data Delay : 3.545 -Slack : -4.936 +Slack : -5.242 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 +Clock Skew : -0.076 +Data Delay : 3.545 -Slack : -4.936 +Slack : -5.242 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 +Clock Skew : -0.076 +Data Delay : 3.545 -Slack : -4.936 +Slack : -5.242 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 +Clock Skew : -0.076 +Data Delay : 3.545 -Slack : -4.936 +Slack : -5.242 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 +Clock Skew : -0.076 +Data Delay : 3.545 -Slack : -4.936 +Slack : -5.242 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 +Clock Skew : -0.076 +Data Delay : 3.545 -Slack : -4.936 +Slack : -5.242 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 +Clock Skew : -0.076 +Data Delay : 3.545 -Slack : -4.936 +Slack : -5.242 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 +Clock Skew : -0.076 +Data Delay : 3.545 -Slack : -4.936 +Slack : -5.242 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 +Clock Skew : -0.076 +Data Delay : 3.545 -Slack : -4.936 +Slack : -5.242 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 +Clock Skew : -0.076 +Data Delay : 3.545 + +Slack : -5.242 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.076 +Data Delay : 3.545 + +Slack : -4.950 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.213 +Data Delay : 3.539 + +Slack : -4.950 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.213 +Data Delay : 3.539 + +Slack : -4.950 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.213 +Data Delay : 3.539 + +Slack : -4.950 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.213 +Data Delay : 3.539 + +Slack : -4.950 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.213 +Data Delay : 3.539 + +Slack : -4.950 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.213 +Data Delay : 3.539 + +Slack : -4.934 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.226 +Data Delay : 3.539 + +Slack : -4.934 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.226 +Data Delay : 3.539 + +Slack : -4.934 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.226 +Data Delay : 3.539 + +Slack : -4.934 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.226 +Data Delay : 3.539 + +Slack : -4.934 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.226 +Data Delay : 3.539 + +Slack : -4.934 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.226 +Data Delay : 3.539 + +Slack : -4.934 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.226 +Data Delay : 3.539 + +Slack : -4.934 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.224 +Data Delay : 3.537 + +Slack : -4.931 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 3.539 + +Slack : -4.931 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 3.539 + +Slack : -4.931 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 3.539 + +Slack : -4.931 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 3.539 + +Slack : -4.931 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 3.539 + +Slack : -4.931 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 Clock Skew : 0.235 -Data Delay : 3.550 +Data Delay : 3.545 + +Slack : -4.928 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.236 +Data Delay : 3.543 + +Slack : -4.927 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.235 +Data Delay : 3.541 + +Slack : -4.910 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.250 +Data Delay : 3.539 + +Slack : -4.910 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.250 +Data Delay : 3.539 + +Slack : -4.904 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.256 +Data Delay : 3.539 + +Slack : -4.904 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.256 +Data Delay : 3.539 +--------------------------------------------------------------------------------+ @@ -17077,743 +22728,1549 @@ Data Delay : 3.550 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.603 -Data Delay : 3.205 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.378 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.599 -Data Delay : 3.205 - -Slack : 3.380 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.595 -Data Delay : 3.203 - -Slack : 3.381 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.594 -Data Delay : 3.203 - -Slack : 3.381 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.594 -Data Delay : 3.203 - -Slack : 3.381 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.594 -Data Delay : 3.203 - -Slack : 3.381 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.594 -Data Delay : 3.203 - -Slack : 3.381 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.594 -Data Delay : 3.203 - -Slack : 3.381 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.594 -Data Delay : 3.203 - -Slack : 3.381 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.594 -Data Delay : 3.203 - -Slack : 3.381 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.594 -Data Delay : 3.203 - -Slack : 3.381 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.594 -Data Delay : 3.203 - -Slack : 3.391 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.583 -Data Delay : 3.205 - -Slack : 3.391 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.583 -Data Delay : 3.205 - -Slack : 3.391 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.583 -Data Delay : 3.205 - -Slack : 3.391 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.583 -Data Delay : 3.205 - -Slack : 3.391 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.583 -Data Delay : 3.205 - -Slack : 3.391 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.583 -Data Delay : 3.205 - -Slack : 3.403 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.578 -Data Delay : 3.209 - -Slack : 3.707 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.270 -Data Delay : 3.205 - -Slack : 3.707 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.270 -Data Delay : 3.205 - -Slack : 3.707 +Slack : 3.339 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.206 +Clock Skew : 0.628 +Data Delay : 3.195 -Slack : 3.707 +Slack : 3.339 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.206 +Clock Skew : 0.628 +Data Delay : 3.195 -Slack : 3.707 +Slack : 3.344 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.622 +Data Delay : 3.194 + +Slack : 3.344 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.622 +Data Delay : 3.194 + +Slack : 3.361 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.607 +Data Delay : 3.196 + +Slack : 3.362 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.608 +Data Delay : 3.198 + +Slack : 3.365 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.606 +Data Delay : 3.199 + +Slack : 3.367 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.600 +Data Delay : 3.195 + +Slack : 3.367 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.600 +Data Delay : 3.195 + +Slack : 3.367 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.600 +Data Delay : 3.195 + +Slack : 3.367 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.600 +Data Delay : 3.195 + +Slack : 3.367 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.600 +Data Delay : 3.195 + +Slack : 3.369 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.597 +Data Delay : 3.194 + +Slack : 3.369 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.597 +Data Delay : 3.194 + +Slack : 3.369 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.597 +Data Delay : 3.194 + +Slack : 3.369 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.597 +Data Delay : 3.194 + +Slack : 3.369 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.597 +Data Delay : 3.194 + +Slack : 3.369 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.597 +Data Delay : 3.194 + +Slack : 3.369 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.597 +Data Delay : 3.194 + +Slack : 3.369 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.596 +Data Delay : 3.193 + +Slack : 3.378 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.584 +Data Delay : 3.193 + +Slack : 3.378 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.584 +Data Delay : 3.193 + +Slack : 3.378 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.584 +Data Delay : 3.193 + +Slack : 3.378 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.584 +Data Delay : 3.193 + +Slack : 3.378 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.584 +Data Delay : 3.193 + +Slack : 3.378 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.584 +Data Delay : 3.193 + +Slack : 3.688 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.283 +Data Delay : 3.199 + +Slack : 3.688 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.283 +Data Delay : 3.199 + +Slack : 3.688 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.283 +Data Delay : 3.199 + +Slack : 3.688 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.283 +Data Delay : 3.199 + +Slack : 3.688 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.283 +Data Delay : 3.199 + +Slack : 3.688 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.283 +Data Delay : 3.199 + +Slack : 3.688 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.283 +Data Delay : 3.199 + +Slack : 3.688 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.283 +Data Delay : 3.199 + +Slack : 3.688 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.283 +Data Delay : 3.199 + +Slack : 3.688 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.283 +Data Delay : 3.199 + +Slack : 3.688 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.283 +Data Delay : 3.199 + +Slack : 3.688 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.283 +Data Delay : 3.199 + +Slack : 3.688 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.283 +Data Delay : 3.199 + +Slack : 3.688 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.283 +Data Delay : 3.199 + +Slack : 3.688 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.283 +Data Delay : 3.199 + +Slack : 3.694 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.193 + +Slack : 3.694 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.193 + +Slack : 3.694 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.193 + +Slack : 3.694 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.271 -Data Delay : 3.206 +Data Delay : 3.193 -Slack : 3.707 +Slack : 3.694 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.271 -Data Delay : 3.206 +Data Delay : 3.193 -Slack : 3.707 +Slack : 3.694 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.271 -Data Delay : 3.206 +Data Delay : 3.193 -Slack : 3.707 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.206 - -Slack : 3.708 +Slack : 3.695 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.268 -Data Delay : 3.204 +Clock Skew : 0.275 +Data Delay : 3.198 -Slack : 3.708 +Slack : 3.695 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.268 -Data Delay : 3.204 +Clock Skew : 0.275 +Data Delay : 3.198 -Slack : 3.708 +Slack : 3.695 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.268 -Data Delay : 3.204 +Clock Skew : 0.275 +Data Delay : 3.198 -Slack : 3.708 +Slack : 3.695 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.268 -Data Delay : 3.204 +Clock Skew : 0.275 +Data Delay : 3.198 -Slack : 3.708 +Slack : 3.695 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.268 -Data Delay : 3.204 +Clock Skew : 0.274 +Data Delay : 3.197 -Slack : 3.708 +Slack : 3.695 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.197 + +Slack : 3.695 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.268 -Data Delay : 3.204 +Clock Skew : 0.274 +Data Delay : 3.197 -Slack : 3.708 +Slack : 3.695 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.197 + +Slack : 3.695 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.268 -Data Delay : 3.204 +Clock Skew : 0.274 +Data Delay : 3.197 -Slack : 3.708 +Slack : 3.695 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.268 -Data Delay : 3.204 +Clock Skew : 0.275 +Data Delay : 3.198 -Slack : 3.708 +Slack : 3.695 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.268 -Data Delay : 3.204 +Clock Skew : 0.275 +Data Delay : 3.198 -Slack : 3.708 +Slack : 3.695 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.272 -Data Delay : 3.208 +Clock Skew : 0.275 +Data Delay : 3.198 -Slack : 3.708 +Slack : 3.695 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.272 -Data Delay : 3.208 +Clock Skew : 0.275 +Data Delay : 3.198 -Slack : 3.708 +Slack : 3.695 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.272 -Data Delay : 3.208 +Clock Skew : 0.270 +Data Delay : 3.193 -Slack : 3.708 +Slack : 3.695 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.272 -Data Delay : 3.208 +Clock Skew : 0.270 +Data Delay : 3.193 -Slack : 3.708 +Slack : 3.695 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.270 +Data Delay : 3.193 + +Slack : 3.695 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.270 +Data Delay : 3.193 + +Slack : 3.695 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.270 +Data Delay : 3.193 + +Slack : 3.695 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.270 +Data Delay : 3.193 + +Slack : 3.695 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.270 +Data Delay : 3.193 + +Slack : 3.695 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.270 +Data Delay : 3.193 + +Slack : 3.695 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.197 + +Slack : 3.695 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.197 + +Slack : 3.695 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.197 + +Slack : 3.696 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.272 -Data Delay : 3.208 +Data Delay : 3.196 -Slack : 3.708 +Slack : 3.696 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.272 -Data Delay : 3.208 +Data Delay : 3.196 -Slack : 3.708 +Slack : 3.696 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.272 -Data Delay : 3.208 +Data Delay : 3.196 -Slack : 3.708 +Slack : 3.696 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.269 -Data Delay : 3.205 +Clock Skew : 0.272 +Data Delay : 3.196 -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.267 -Data Delay : 3.204 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.267 -Data Delay : 3.204 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.267 -Data Delay : 3.204 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.267 -Data Delay : 3.204 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.267 -Data Delay : 3.204 - -Slack : 3.895 +Slack : 3.883 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.226 -Data Delay : 3.294 +Data Delay : 3.282 -Slack : 3.909 +Slack : 3.884 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.227 -Data Delay : 3.309 +Data Delay : 3.284 -Slack : 4.117 +Slack : 4.105 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.254 -Data Delay : 3.541 +Data Delay : 3.529 -Slack : 4.117 +Slack : 4.105 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.252 -Data Delay : 3.539 +Data Delay : 3.527 -Slack : 4.117 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.251 -Data Delay : 3.538 - -Slack : 4.117 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.250 -Data Delay : 3.537 - -Slack : 4.118 +Slack : 4.105 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.250 -Data Delay : 3.538 +Data Delay : 3.525 + +Slack : 4.105 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.251 +Data Delay : 3.526 + +Slack : 4.105 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.250 +Data Delay : 3.525 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[0] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[1] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[2] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[3] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[4] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1 + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[0] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[1] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[2] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[3] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[4] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[5] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[6] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[7] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[8] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[9] + +Slack : 4.748 +Actual Width : 4.964 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_pending + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[10] + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[11] + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[12] + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[13] + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[14] + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[1] + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[2] + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[3] + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[4] + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[5] + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[6] + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[7] + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[8] + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[9] + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rd_pending + +Slack : 4.749 +Actual Width : 4.965 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.wr_pending + +Slack : 4.750 +Actual Width : 4.966 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[4] + +Slack : 4.750 +Actual Width : 4.966 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[5] + +Slack : 4.750 +Actual Width : 4.966 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[6] + +Slack : 4.750 +Actual Width : 4.966 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[7] + +Slack : 4.750 +Actual Width : 4.966 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[8] + +Slack : 4.751 +Actual Width : 4.967 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[0] + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1 + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1 + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2 + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 + +Slack : 4.752 +Actual Width : 4.968 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1 + +Slack : 4.841 +Actual Width : 4.996 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[7] + +Slack : 4.841 +Actual Width : 4.996 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.bank[1] + +Slack : 4.841 +Actual Width : 4.996 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.dq_masks[0] + +Slack : 4.841 +Actual Width : 4.996 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.dq_masks[1] + +Slack : 4.842 +Actual Width : 4.997 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[1] + +Slack : 4.842 +Actual Width : 4.997 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[2] + +Slack : 4.842 +Actual Width : 4.997 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[3] + +Slack : 4.842 +Actual Width : 4.997 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[4] + +Slack : 4.842 +Actual Width : 4.997 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[5] + +Slack : 4.842 +Actual Width : 4.997 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[6] + +Slack : 4.842 +Actual Width : 4.997 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.bank[0] + +Slack : 4.843 +Actual Width : 4.998 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[1] + +Slack : 4.843 +Actual Width : 4.998 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[2] + +Slack : 4.844 +Actual Width : 4.999 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11] + +Slack : 4.846 +Actual Width : 5.001 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0] + +Slack : 4.846 +Actual Width : 5.001 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[8] + +Slack : 4.846 +Actual Width : 5.001 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[9] + +Slack : 4.847 +Actual Width : 5.031 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1 + +Slack : 4.847 +Actual Width : 5.002 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10] + +Slack : 4.847 +Actual Width : 5.031 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1 + +Slack : 4.847 +Actual Width : 4.997 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1 + +Slack : 4.847 +Actual Width : 5.002 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1 + +Slack : 4.847 +Actual Width : 5.031 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 + +Slack : 4.847 +Actual Width : 5.031 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1 + +Slack : 4.847 +Actual Width : 4.997 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[0] + +Slack : 4.847 +Actual Width : 5.002 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[0] + +Slack : 4.848 +Actual Width : 4.998 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10] + +Slack : 4.848 +Actual Width : 5.032 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2 + +Slack : 4.848 +Actual Width : 4.998 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[8] + +Slack : 4.848 +Actual Width : 5.032 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[0] + +Slack : 4.849 +Actual Width : 4.999 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0] + +Slack : 4.849 +Actual Width : 4.999 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[9] + +Slack : 4.850 +Actual Width : 5.034 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[3] + +Slack : 4.850 +Actual Width : 5.034 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[4] + +Slack : 4.850 +Actual Width : 5.034 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[5] + +Slack : 4.850 +Actual Width : 5.034 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[6] + +Slack : 4.850 +Actual Width : 5.034 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[7] + +Slack : 4.850 +Actual Width : 5.034 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[8] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[0] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[1] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[2] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[3] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[4] + +Slack : 4.851 +Actual Width : 5.001 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1 + +Slack : 4.851 +Actual Width : 5.001 +Required Width : 0.150 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.bank[1] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[10] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[11] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[12] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[13] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[14] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[1] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[2] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[4] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[5] + +Slack : 4.851 +Actual Width : 5.035 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[6] +--------------------------------------------------------------------------------+ @@ -17827,7 +24284,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0 Slack : 9.489 Actual Width : 9.719 @@ -17835,7 +24292,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg Slack : 9.489 Actual Width : 9.719 @@ -17859,7 +24316,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0 Slack : 9.489 Actual Width : 9.719 @@ -17867,56 +24324,80 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg - Slack : 9.490 Actual Width : 9.720 Required Width : 0.230 @@ -17949,22 +24430,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg - Slack : 9.490 Actual Width : 9.720 Required Width : 0.230 @@ -17987,7 +24452,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0 Slack : 9.490 Actual Width : 9.720 @@ -17995,23 +24460,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg Slack : 9.490 Actual Width : 9.720 @@ -18051,7 +24500,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0 Slack : 9.490 Actual Width : 9.720 @@ -18059,7 +24508,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg Slack : 9.490 Actual Width : 9.720 @@ -18067,7 +24516,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Slack : 9.490 Actual Width : 9.720 @@ -18075,7 +24524,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 Slack : 9.490 Actual Width : 9.720 @@ -18083,15 +24532,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 Slack : 9.490 Actual Width : 9.720 @@ -18107,7 +24548,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 Slack : 9.491 Actual Width : 9.721 @@ -18115,7 +24556,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 Slack : 9.491 Actual Width : 9.721 @@ -18131,7 +24572,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0 Slack : 9.491 Actual Width : 9.721 @@ -18139,7 +24580,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg Slack : 9.491 Actual Width : 9.721 @@ -18147,7 +24588,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 Slack : 9.491 Actual Width : 9.721 @@ -18155,7 +24596,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 Slack : 9.491 Actual Width : 9.721 @@ -18163,7 +24604,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0 Slack : 9.491 Actual Width : 9.721 @@ -18171,7 +24612,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg Slack : 9.491 Actual Width : 9.721 @@ -18179,7 +24620,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 Slack : 9.491 Actual Width : 9.721 @@ -18187,7 +24628,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 Slack : 9.491 Actual Width : 9.721 @@ -18203,15 +24652,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 Slack : 9.491 Actual Width : 9.721 @@ -18221,6 +24662,30 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 + Slack : 9.491 Actual Width : 9.721 Required Width : 0.230 @@ -18235,7 +24700,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 + +Slack : 9.492 +Actual Width : 9.722 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 Slack : 9.492 Actual Width : 9.722 @@ -18253,14 +24726,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 -Slack : 9.492 -Actual Width : 9.722 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 - Slack : 9.492 Actual Width : 9.722 Required Width : 0.230 @@ -18275,15 +24740,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 - -Slack : 9.492 -Actual Width : 9.722 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 Slack : 9.492 Actual Width : 9.722 @@ -18307,7 +24764,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 + +Slack : 9.492 +Actual Width : 9.722 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 Slack : 9.493 Actual Width : 9.723 @@ -18315,7 +24780,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 Slack : 9.493 Actual Width : 9.723 @@ -18323,7 +24788,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 Slack : 9.493 Actual Width : 9.723 @@ -18331,72 +24796,32 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 - -Slack : 9.493 -Actual Width : 9.723 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 - -Slack : 9.493 -Actual Width : 9.723 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 + +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 + +Slack : 9.494 +Actual Width : 9.724 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 + Slack : 9.494 Actual Width : 9.724 Required Width : 0.230 @@ -18411,7 +24836,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 Slack : 9.495 Actual Width : 9.725 @@ -18419,7 +24844,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 + +Slack : 9.495 +Actual Width : 9.725 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 Slack : 9.495 Actual Width : 9.725 @@ -18435,7 +24868,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 Slack : 9.495 Actual Width : 9.725 @@ -18445,6 +24878,30 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +Slack : 9.495 +Actual Width : 9.725 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 + +Slack : 9.495 +Actual Width : 9.725 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 + +Slack : 9.495 +Actual Width : 9.725 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 + Slack : 9.495 Actual Width : 9.725 Required Width : 0.230 @@ -18459,7 +24916,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 Slack : 9.497 Actual Width : 9.727 @@ -18467,7 +24924,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 Slack : 9.497 Actual Width : 9.727 @@ -18483,7 +24940,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 Slack : 9.497 Actual Width : 9.727 @@ -18491,7 +24948,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 + +Slack : 9.497 +Actual Width : 9.727 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 Slack : 9.498 Actual Width : 9.728 @@ -18499,15 +24964,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0 - -Slack : 9.498 -Actual Width : 9.728 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 Slack : 9.498 Actual Width : 9.728 @@ -18523,7 +24980,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 Slack : 9.498 Actual Width : 9.728 @@ -18539,7 +24996,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 Slack : 9.498 Actual Width : 9.728 @@ -18563,7 +25020,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0 Slack : 9.498 Actual Width : 9.728 @@ -18571,7 +25028,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 Slack : 9.498 Actual Width : 9.728 @@ -18579,7 +25036,23 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 + +Slack : 9.498 +Actual Width : 9.728 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0 + +Slack : 9.498 +Actual Width : 9.728 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 Slack : 9.498 Actual Width : 9.728 @@ -18603,23 +25076,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 - -Slack : 9.499 -Actual Width : 9.729 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 - -Slack : 9.499 -Actual Width : 9.729 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +--------------------------------------------------------------------------------+ @@ -18627,237 +25084,85 @@ Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|VGA_HS~_Duplicate_1 - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|VGA_VS~_Duplicate_1 - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[0] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[1] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[4] - -Slack : 19.600 -Actual Width : 19.816 +Slack : 19.596 +Actual Width : 19.812 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|bits_prefetch[0] -Slack : 19.600 -Actual Width : 19.816 +Slack : 19.596 +Actual Width : 19.812 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|bits_prefetch[1] -Slack : 19.600 -Actual Width : 19.816 +Slack : 19.596 +Actual Width : 19.812 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|bits_prefetch[2] -Slack : 19.600 -Actual Width : 19.816 +Slack : 19.596 +Actual Width : 19.812 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|bits_prefetch[3] -Slack : 19.600 -Actual Width : 19.816 +Slack : 19.596 +Actual Width : 19.812 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|bits_prefetch[4] -Slack : 19.600 -Actual Width : 19.816 +Slack : 19.596 +Actual Width : 19.812 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|bits_prefetch[5] -Slack : 19.600 -Actual Width : 19.816 +Slack : 19.596 +Actual Width : 19.812 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|bits_prefetch[6] -Slack : 19.600 -Actual Width : 19.816 +Slack : 19.596 +Actual Width : 19.812 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|bits_prefetch[7] -Slack : 19.600 -Actual Width : 19.816 +Slack : 19.598 +Actual Width : 19.814 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|frame[0] -Slack : 19.600 -Actual Width : 19.816 +Slack : 19.601 +Actual Width : 19.817 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[2] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[4] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[5] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[6] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[7] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[8] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[9] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[0] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[1] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[2] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[3] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[4] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[5] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[6] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[7] +Target : ula:ula_|video:video_|VGA_VS~_Duplicate_1 Slack : 19.601 Actual Width : 19.817 @@ -18865,7 +25170,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +Target : ula:ula_|video:video_|attr[0] Slack : 19.601 Actual Width : 19.817 @@ -18873,23 +25178,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr[2] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[3] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[5] +Target : ula:ula_|video:video_|attr[1] Slack : 19.601 Actual Width : 19.817 @@ -18899,78 +25188,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|attr[6] -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[7] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[0] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[1] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[2] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[3] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[4] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[5] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[6] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits[7] - Slack : 19.601 Actual Width : 19.817 Required Width : 0.216 @@ -19009,7 +25226,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[0] +Target : ula:ula_|video:video_|vga_hc[2] Slack : 19.601 Actual Width : 19.817 @@ -19017,7 +25234,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[1] +Target : ula:ula_|video:video_|vga_hc[4] Slack : 19.601 Actual Width : 19.817 @@ -19025,7 +25242,39 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[3] +Target : ula:ula_|video:video_|vga_hc[5] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[6] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[7] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[8] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[9] Slack : 19.601 Actual Width : 19.817 @@ -19107,46 +25356,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|vga_vc[9] -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[10] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[11] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[12] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[8] - -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[9] - Slack : 19.602 Actual Width : 19.818 Required Width : 0.216 @@ -19155,6 +25364,14 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] + Slack : 19.602 Actual Width : 19.818 Required Width : 0.216 @@ -19163,13 +25380,245 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0 +Target : ula:ula_|video:video_|VGA_HS~_Duplicate_1 + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr[2] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr[3] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr[4] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr[5] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr[7] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits[0] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits[1] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits[2] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits[3] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits[4] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits[5] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits[6] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits[7] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[0] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[1] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[3] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[0] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[10] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[11] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[12] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[1] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[2] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[3] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[4] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[5] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[6] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[7] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[8] + +Slack : 19.602 +Actual Width : 19.818 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[9] Slack : 19.603 Actual Width : 19.833 @@ -19177,15 +25626,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0 -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg Slack : 19.604 Actual Width : 19.834 @@ -19193,7 +25642,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0 Slack : 19.604 Actual Width : 19.834 @@ -19201,71 +25650,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[0] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[1] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[2] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[3] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[4] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[5] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[6] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[7] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg Slack : 19.605 Actual Width : 19.835 @@ -19273,7 +25658,39 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg Slack : 19.605 Actual Width : 19.835 @@ -19291,22 +25708,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0 - -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg - Slack : 19.605 Actual Width : 19.835 Required Width : 0.230 @@ -19329,7 +25730,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 Slack : 19.605 Actual Width : 19.835 @@ -19337,7 +25738,23 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg Slack : 19.605 Actual Width : 19.835 @@ -19361,7 +25778,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0 Slack : 19.605 Actual Width : 19.835 @@ -19369,23 +25786,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg - -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0 - -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg Slack : 19.605 Actual Width : 19.835 @@ -19403,22 +25804,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0 - -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg - Slack : 19.605 Actual Width : 19.835 Required Width : 0.230 @@ -19426,6 +25811,78 @@ Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[0] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[1] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[2] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[3] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[4] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[5] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[6] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[7] +--------------------------------------------------------------------------------+ @@ -19439,7 +25896,39 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] + +Slack : 20.591 +Actual Width : 20.807 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] + +Slack : 20.591 +Actual Width : 20.807 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] + +Slack : 20.591 +Actual Width : 20.807 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] + +Slack : 20.591 +Actual Width : 20.807 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Slack : 20.592 Actual Width : 20.808 @@ -19465,6 +25954,62 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|phase[0] + +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|phase[1] + +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] + +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] + +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] + +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] + +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] + Slack : 20.594 Actual Width : 20.810 Required Width : 0.216 @@ -19473,6 +26018,22 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] + +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] + Slack : 20.594 Actual Width : 20.810 Required Width : 0.216 @@ -19489,6 +26050,14 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|state.Data +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle + Slack : 20.594 Actual Width : 20.810 Required Width : 0.216 @@ -19513,6 +26082,54 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 + +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] + +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] + +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] + +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] + +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] + Slack : 20.595 Actual Width : 20.811 Required Width : 0.216 @@ -19529,22 +26146,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|phase[0] - -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|phase[1] - Slack : 20.595 Actual Width : 20.811 Required Width : 0.216 @@ -19561,14 +26162,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle - Slack : 20.595 Actual Width : 20.811 Required Width : 0.216 @@ -19585,14 +26178,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 - Slack : 20.595 Actual Width : 20.811 Required Width : 0.216 @@ -19633,46 +26218,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] - -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] - -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] - -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] - -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] - Slack : 20.595 Actual Width : 20.811 Required Width : 0.216 @@ -19681,110 +26226,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Slack : 20.595 -Actual Width : 20.811 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] - Slack : 20.598 Actual Width : 20.814 Required Width : 0.216 @@ -19793,14 +26234,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -Slack : 20.598 -Actual Width : 20.814 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] - Slack : 20.598 Actual Width : 20.814 Required Width : 0.216 @@ -19815,7 +26248,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] Slack : 20.598 Actual Width : 20.814 @@ -19823,15 +26256,15 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Slack : 20.598 -Actual Width : 20.814 +Slack : 20.599 +Actual Width : 20.815 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] Slack : 20.599 Actual Width : 20.815 @@ -19841,6 +26274,14 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] + Slack : 20.599 Actual Width : 20.815 Required Width : 0.216 @@ -19855,7 +26296,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] Slack : 20.599 Actual Width : 20.815 @@ -19863,127 +26304,143 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] +Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.600 +Actual Width : 20.816 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] + +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Slack : 20.601 +Actual Width : 20.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] + Slack : 20.603 Actual Width : 20.819 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] Slack : 20.633 Actual Width : 20.817 @@ -20105,14 +26562,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r -Slack : 20.697 -Actual Width : 20.881 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] - Slack : 20.698 Actual Width : 20.853 Required Width : 0.155 @@ -20137,6 +26586,14 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r +Slack : 20.698 +Actual Width : 20.882 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] + Slack : 20.698 Actual Width : 20.853 Required Width : 0.155 @@ -20193,40 +26650,40 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|sda_out -Slack : 20.702 -Actual Width : 20.857 -Required Width : 0.155 +Slack : 20.701 +Actual Width : 20.885 +Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|scl_out +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Slack : 20.702 -Actual Width : 20.886 +Slack : 20.701 +Actual Width : 20.885 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Slack : 20.702 -Actual Width : 20.886 +Slack : 20.701 +Actual Width : 20.885 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Slack : 20.702 -Actual Width : 20.886 +Slack : 20.701 +Actual Width : 20.885 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Slack : 20.702 -Actual Width : 20.886 +Slack : 20.701 +Actual Width : 20.885 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] @@ -20359,43 +26816,43 @@ Target : ula:ula_|clocks:clocks_|counter[0] +--------------------------------------------------------------------------------+ Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : 1.911 -Fall : 2.250 +Rise : 1.514 +Fall : 1.791 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : 3.553 -Fall : 3.886 +Rise : 3.526 +Fall : 3.809 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : SW[*] Clock Port : CLOCK_50 -Rise : 0.869 -Fall : 1.148 +Rise : 0.868 +Fall : 1.149 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : SW[2] Clock Port : CLOCK_50 -Rise : 0.869 -Fall : 1.148 +Rise : 0.868 +Fall : 1.149 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : 1.127 -Fall : 1.330 +Rise : 1.088 +Fall : 1.288 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : 2.508 -Fall : 2.792 +Rise : 2.501 +Fall : 2.786 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -20407,43 +26864,43 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : -1.524 -Fall : -1.860 +Rise : -1.142 +Fall : -1.415 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : -2.737 -Fall : -3.061 +Rise : -2.326 +Fall : -2.595 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : SW[*] Clock Port : CLOCK_50 -Rise : -0.321 -Fall : -0.592 +Rise : -0.319 +Fall : -0.593 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : SW[2] Clock Port : CLOCK_50 -Rise : -0.321 -Fall : -0.592 +Rise : -0.319 +Fall : -0.593 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : -0.576 -Fall : -0.776 +Rise : -0.536 +Fall : -0.733 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : -1.192 -Fall : -1.416 +Rise : -1.185 +Fall : -1.411 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -20453,199 +26910,619 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ ; Clock to Output Times ; +--------------------------------------------------------------------------------+ -Data Port : GPIO_1[*] +Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 9.288 -Fall : 9.190 +Rise : 9.704 +Fall : 9.567 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[16] +Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 9.288 -Fall : 9.190 +Rise : 9.147 +Fall : 9.032 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[17] +Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 8.334 -Fall : 8.266 +Rise : 9.316 +Fall : 9.197 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[18] +Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 9.015 -Fall : 8.878 +Rise : 9.155 +Fall : 9.002 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[19] +Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 8.651 -Fall : 8.566 +Rise : 9.152 +Fall : 9.158 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[20] +Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 8.878 -Fall : 8.812 +Rise : 9.351 +Fall : 9.246 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[21] +Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 8.466 -Fall : 8.329 +Rise : 9.507 +Fall : 9.411 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[22] +Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 9.024 -Fall : 8.945 +Rise : 9.704 +Fall : 9.567 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[23] +Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 8.255 -Fall : 8.139 +Rise : 9.309 +Fall : 9.150 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 7.270 -Fall : 7.175 +Rise : 9.484 +Fall : 9.425 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 9.018 +Fall : 8.912 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 9.123 +Fall : 9.045 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 9.044 +Fall : 8.917 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 8.866 +Fall : 8.821 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 9.269 +Fall : 9.179 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 9.131 +Fall : 9.026 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 9.484 +Fall : 9.425 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 8.703 +Fall : 8.604 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_ADDR[*] +Clock Port : CLOCK_50 +Rise : 3.063 +Fall : 2.969 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[0] +Clock Port : CLOCK_50 +Rise : 3.059 +Fall : 2.965 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[1] +Clock Port : CLOCK_50 +Rise : 2.991 +Fall : 2.916 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[2] +Clock Port : CLOCK_50 +Rise : 2.991 +Fall : 2.916 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[3] +Clock Port : CLOCK_50 +Rise : 2.990 +Fall : 2.915 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[4] +Clock Port : CLOCK_50 +Rise : 2.992 +Fall : 2.917 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[5] +Clock Port : CLOCK_50 +Rise : 2.989 +Fall : 2.914 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[6] +Clock Port : CLOCK_50 +Rise : 2.990 +Fall : 2.915 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[7] +Clock Port : CLOCK_50 +Rise : 2.987 +Fall : 2.912 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[8] +Clock Port : CLOCK_50 +Rise : 2.974 +Fall : 2.902 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[9] +Clock Port : CLOCK_50 +Rise : 3.059 +Fall : 2.965 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[10] +Clock Port : CLOCK_50 +Rise : 3.050 +Fall : 2.956 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[11] +Clock Port : CLOCK_50 +Rise : 3.063 +Fall : 2.969 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[12] +Clock Port : CLOCK_50 +Rise : 2.972 +Fall : 2.900 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[*] +Clock Port : CLOCK_50 +Rise : 2.990 +Fall : 2.915 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[0] +Clock Port : CLOCK_50 +Rise : 2.989 +Fall : 2.914 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[1] +Clock Port : CLOCK_50 +Rise : 2.990 +Fall : 2.915 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CAS_N +Clock Port : CLOCK_50 +Rise : 3.059 +Fall : 2.965 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 5.612 +Fall : 5.736 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 5.021 +Fall : 5.022 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 5.298 +Fall : 5.247 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 5.067 +Fall : 5.018 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 4.792 +Fall : 4.786 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 5.108 +Fall : 5.074 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 5.184 +Fall : 5.190 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 5.057 +Fall : 5.041 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 5.242 +Fall : 5.220 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[8] +Clock Port : CLOCK_50 +Rise : 5.612 +Fall : 5.736 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[9] +Clock Port : CLOCK_50 +Rise : 5.433 +Fall : 5.528 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[10] +Clock Port : CLOCK_50 +Rise : 5.415 +Fall : 5.507 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[11] +Clock Port : CLOCK_50 +Rise : 5.415 +Fall : 5.507 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[12] +Clock Port : CLOCK_50 +Rise : 5.584 +Fall : 5.735 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[13] +Clock Port : CLOCK_50 +Rise : 5.606 +Fall : 5.727 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[14] +Clock Port : CLOCK_50 +Rise : 5.606 +Fall : 5.727 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[15] +Clock Port : CLOCK_50 +Rise : 5.216 +Fall : 5.338 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[*] +Clock Port : CLOCK_50 +Rise : 2.987 +Fall : 2.912 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[0] +Clock Port : CLOCK_50 +Rise : 2.987 +Fall : 2.912 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[1] +Clock Port : CLOCK_50 +Rise : 2.987 +Fall : 2.912 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_RAS_N +Clock Port : CLOCK_50 +Rise : 3.059 +Fall : 2.965 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_WE_N +Clock Port : CLOCK_50 +Rise : 3.057 +Fall : 2.963 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : 4.468 +Fall : +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : +Fall : 4.400 +Clock Edge : Fall +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 7.742 +Fall : 7.609 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 6.921 +Fall : 6.836 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 7.061 +Fall : 6.953 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 7.363 +Fall : 7.240 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 7.236 +Fall : 7.218 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 7.691 +Fall : 7.577 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 7.301 +Fall : 7.220 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 7.742 +Fall : 7.609 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 7.255 +Fall : 7.167 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 7.609 +Fall : 7.510 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 6.990 -Fall : 6.892 +Rise : 6.792 +Fall : 6.716 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 7.043 -Fall : 6.987 +Rise : 6.868 +Fall : 6.801 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 6.669 -Fall : 6.593 +Rise : 7.252 +Fall : 7.155 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 6.995 -Fall : 6.959 +Rise : 6.950 +Fall : 6.881 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 7.270 -Fall : 7.174 +Rise : 7.609 +Fall : 7.510 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 6.811 -Fall : 6.729 +Rise : 6.928 +Fall : 6.839 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 7.250 -Fall : 7.175 +Rise : 7.522 +Fall : 7.467 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 6.586 -Fall : 6.535 +Rise : 6.553 +Fall : 6.501 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 7.385 -Fall : 6.991 +Rise : 7.801 +Fall : 7.387 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 7.385 -Fall : 6.991 +Rise : 7.801 +Fall : 7.387 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 5.536 -Fall : 5.411 +Rise : 6.721 +Fall : 6.643 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 5.836 -Fall : 5.758 +Rise : 6.058 +Fall : 5.994 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 6.231 -Fall : 6.124 +Rise : 6.058 +Fall : 5.988 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 5.992 -Fall : 5.815 +Rise : 6.378 +Fall : 6.216 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 5.992 -Fall : 5.815 +Rise : 5.722 +Fall : 5.601 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 5.802 -Fall : 5.684 +Rise : 6.100 +Fall : 6.052 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 5.868 -Fall : 5.672 +Rise : 6.378 +Fall : 6.216 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 5.868 -Fall : 5.672 +Rise : 6.378 +Fall : 6.216 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -20658,36 +27535,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 6.035 -Fall : 5.996 +Rise : 6.652 +Fall : 6.631 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 6.035 -Fall : 5.996 +Rise : 6.325 +Fall : 6.242 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 5.858 -Fall : 5.798 +Rise : 6.652 +Fall : 6.631 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 5.672 -Fall : 5.600 +Rise : 6.096 +Fall : 5.995 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 5.870 -Fall : 5.793 +Rise : 6.056 +Fall : 5.943 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -20753,199 +27630,619 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ ; Minimum Clock to Output Times ; +--------------------------------------------------------------------------------+ -Data Port : GPIO_1[*] +Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 6.905 -Fall : 6.797 +Rise : 7.096 +Fall : 6.975 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[16] +Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 7.457 -Fall : 7.377 +Rise : 7.264 +Fall : 7.182 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[17] +Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 7.475 -Fall : 7.384 +Rise : 7.371 +Fall : 7.296 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[18] +Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 6.905 -Fall : 6.797 +Rise : 7.096 +Fall : 6.975 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[19] +Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 7.286 -Fall : 7.208 +Rise : 7.441 +Fall : 7.404 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[20] +Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 7.618 -Fall : 7.567 +Rise : 7.615 +Fall : 7.537 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[21] +Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 7.138 -Fall : 6.996 +Rise : 7.847 +Fall : 7.749 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[22] +Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 6.984 -Fall : 6.911 +Rise : 7.468 +Fall : 7.367 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[23] +Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 7.037 -Fall : 6.924 +Rise : 7.876 +Fall : 7.722 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 5.004 -Fall : 4.912 +Rise : 6.991 +Fall : 6.894 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 7.141 +Fall : 7.067 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 7.186 +Fall : 7.151 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 6.991 +Fall : 6.894 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 7.168 +Fall : 7.083 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 7.533 +Fall : 7.468 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 7.485 +Fall : 7.379 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 7.255 +Fall : 7.231 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 7.296 +Fall : 7.199 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_ADDR[*] +Clock Port : CLOCK_50 +Rise : 2.600 +Fall : 2.528 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[0] +Clock Port : CLOCK_50 +Rise : 2.686 +Fall : 2.592 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[1] +Clock Port : CLOCK_50 +Rise : 2.620 +Fall : 2.544 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[2] +Clock Port : CLOCK_50 +Rise : 2.620 +Fall : 2.544 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[3] +Clock Port : CLOCK_50 +Rise : 2.619 +Fall : 2.543 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[4] +Clock Port : CLOCK_50 +Rise : 2.621 +Fall : 2.545 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[5] +Clock Port : CLOCK_50 +Rise : 2.618 +Fall : 2.542 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[6] +Clock Port : CLOCK_50 +Rise : 2.619 +Fall : 2.543 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[7] +Clock Port : CLOCK_50 +Rise : 2.617 +Fall : 2.541 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[8] +Clock Port : CLOCK_50 +Rise : 2.602 +Fall : 2.530 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[9] +Clock Port : CLOCK_50 +Rise : 2.686 +Fall : 2.592 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[10] +Clock Port : CLOCK_50 +Rise : 2.678 +Fall : 2.584 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[11] +Clock Port : CLOCK_50 +Rise : 2.690 +Fall : 2.596 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[12] +Clock Port : CLOCK_50 +Rise : 2.600 +Fall : 2.528 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[*] +Clock Port : CLOCK_50 +Rise : 2.618 +Fall : 2.542 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[0] +Clock Port : CLOCK_50 +Rise : 2.618 +Fall : 2.542 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[1] +Clock Port : CLOCK_50 +Rise : 2.620 +Fall : 2.544 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CAS_N +Clock Port : CLOCK_50 +Rise : 2.686 +Fall : 2.592 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 4.046 +Fall : 4.162 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 4.494 +Fall : 4.492 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 4.759 +Fall : 4.708 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 4.536 +Fall : 4.486 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 4.273 +Fall : 4.266 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 4.576 +Fall : 4.543 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 4.651 +Fall : 4.654 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 4.474 +Fall : 4.453 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 4.705 +Fall : 4.681 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[8] +Clock Port : CLOCK_50 +Rise : 4.425 +Fall : 4.542 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[9] +Clock Port : CLOCK_50 +Rise : 4.254 +Fall : 4.343 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[10] +Clock Port : CLOCK_50 +Rise : 4.236 +Fall : 4.323 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[11] +Clock Port : CLOCK_50 +Rise : 4.236 +Fall : 4.323 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[12] +Clock Port : CLOCK_50 +Rise : 4.398 +Fall : 4.541 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[13] +Clock Port : CLOCK_50 +Rise : 4.419 +Fall : 4.534 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[14] +Clock Port : CLOCK_50 +Rise : 4.419 +Fall : 4.534 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[15] +Clock Port : CLOCK_50 +Rise : 4.046 +Fall : 4.162 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[*] +Clock Port : CLOCK_50 +Rise : 2.617 +Fall : 2.541 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[0] +Clock Port : CLOCK_50 +Rise : 2.617 +Fall : 2.541 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[1] +Clock Port : CLOCK_50 +Rise : 2.617 +Fall : 2.541 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_RAS_N +Clock Port : CLOCK_50 +Rise : 2.686 +Fall : 2.592 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_WE_N +Clock Port : CLOCK_50 +Rise : 2.685 +Fall : 2.591 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : 4.091 +Fall : +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : +Fall : 4.022 +Clock Edge : Fall +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 5.643 +Fall : 5.545 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 6.051 +Fall : 5.942 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 6.097 +Fall : 5.993 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 6.444 +Fall : 6.297 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 6.074 +Fall : 6.074 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 5.795 +Fall : 5.719 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 6.263 +Fall : 6.207 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 5.643 +Fall : 5.545 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 6.436 +Fall : 6.340 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 5.430 +Fall : 5.409 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 5.924 -Fall : 5.881 +Rise : 5.928 +Fall : 5.827 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 5.978 -Fall : 5.952 +Rise : 5.912 +Fall : 5.848 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 5.763 -Fall : 5.676 +Rise : 6.339 +Fall : 6.216 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 5.765 -Fall : 5.720 +Rise : 5.801 +Fall : 5.753 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 5.004 -Fall : 4.912 +Rise : 5.713 +Fall : 5.650 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 5.746 -Fall : 5.674 +Rise : 5.904 +Fall : 5.840 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 6.140 -Fall : 6.075 +Rise : 5.430 +Fall : 5.409 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 5.512 -Fall : 5.440 +Rise : 5.794 +Fall : 5.736 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 3.609 -Fall : 3.472 +Rise : 4.034 +Fall : 3.964 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 5.390 -Fall : 4.913 +Rise : 5.778 +Fall : 5.365 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 3.609 -Fall : 3.472 +Rise : 4.250 +Fall : 4.133 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 3.832 -Fall : 3.672 +Rise : 4.034 +Fall : 3.970 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 4.210 -Fall : 4.023 +Rise : 4.034 +Fall : 3.964 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 3.660 -Fall : 3.561 +Rise : 3.467 +Fall : 3.356 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 4.048 -Fall : 3.884 +Rise : 3.489 +Fall : 3.376 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 3.660 -Fall : 3.561 +Rise : 3.467 +Fall : 3.356 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 3.929 -Fall : 3.746 +Rise : 4.119 +Fall : 3.966 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 3.929 -Fall : 3.746 +Rise : 4.119 +Fall : 3.966 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -20958,36 +28255,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 3.534 -Fall : 3.394 +Rise : 3.812 +Fall : 3.704 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 3.882 -Fall : 3.774 +Rise : 4.071 +Fall : 3.991 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 3.799 -Fall : 3.710 +Rise : 4.084 +Fall : 4.001 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 3.534 -Fall : 3.394 +Rise : 3.851 +Fall : 3.754 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 3.723 -Fall : 3.578 +Rise : 3.812 +Fall : 3.704 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -21055,31 +28352,38 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 4.171 +RR : 4.172 RF : FR : FF : 4.298 Input Port : SW[2] Output Port : LED[2] -RR : 3.640 +RR : 3.641 RF : FR : FF : 3.830 Input Port : raw_loader_in -Output Port : GPIO_1[22] -RR : 6.058 +Output Port : DRAM_DQ[6] +RR : 6.274 RF : FR : -FF : 6.293 +FF : 6.463 + +Input Port : raw_loader_in +Output Port : GPIO_1[22] +RR : 6.413 +RF : +FR : +FF : 6.634 Input Port : raw_loader_in Output Port : LED[3] -RR : 3.926 +RR : 4.080 RF : FR : -FF : 4.082 +FF : 4.294 +--------------------------------------------------------------------------------+ @@ -21092,28 +28396,311 @@ Output Port : LED[0] RR : 4.037 RF : FR : -FF : 4.164 +FF : 4.165 Input Port : SW[2] Output Port : LED[2] RR : 3.527 RF : FR : -FF : 3.715 +FF : 3.716 + +Input Port : raw_loader_in +Output Port : DRAM_DQ[6] +RR : 6.051 +RF : +FR : +FF : 6.240 Input Port : raw_loader_in Output Port : GPIO_1[22] -RR : 5.841 +RR : 6.182 RF : FR : -FF : 6.076 +FF : 6.405 Input Port : raw_loader_in Output Port : LED[3] -RR : 3.796 +RR : 3.944 RF : FR : -FF : 3.952 +FF : 4.156 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Output Enable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 5.323 +Fall : 5.181 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 5.805 +Fall : 5.663 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 5.805 +Fall : 5.663 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 5.488 +Fall : 5.363 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 5.500 +Fall : 5.389 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 5.323 +Fall : 5.181 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 5.512 +Fall : 5.370 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 5.512 +Fall : 5.370 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 5.495 +Fall : 5.370 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 4.160 +Fall : 4.018 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 4.623 +Fall : 4.481 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 4.623 +Fall : 4.481 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 4.286 +Fall : 4.161 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 4.326 +Fall : 4.215 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 4.160 +Fall : 4.018 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 4.341 +Fall : 4.199 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 4.341 +Fall : 4.199 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 4.293 +Fall : 4.168 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Output Disable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.156 +1 to Hi-Z : 5.298 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.644 +1 to Hi-Z : 5.786 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.644 +1 to Hi-Z : 5.786 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.349 +1 to Hi-Z : 5.474 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.397 +1 to Hi-Z : 5.508 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.156 +1 to Hi-Z : 5.298 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.257 +1 to Hi-Z : 5.399 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.257 +1 to Hi-Z : 5.399 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +0 to Hi-Z : 5.335 +1 to Hi-Z : 5.460 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Minimum Output Disable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +0 to Hi-Z : 3.999 +1 to Hi-Z : 4.141 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.467 +1 to Hi-Z : 4.609 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.467 +1 to Hi-Z : 4.609 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.153 +1 to Hi-Z : 4.278 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.229 +1 to Hi-Z : 4.340 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +0 to Hi-Z : 3.999 +1 to Hi-Z : 4.141 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.096 +1 to Hi-Z : 4.238 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.096 +1 to Hi-Z : 4.238 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +0 to Hi-Z : 4.139 +1 to Hi-Z : 4.264 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +--------------------------------------------------------------------------------+ @@ -21128,20 +28715,24 @@ No synchronizer chains to report. ; Fast 1200mV 0C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -14.971 -End Point TNS : -442.545 +Slack : -15.243 +End Point TNS : -641.328 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Slack : -4.979 -End Point TNS : -171.124 +Slack : -4.921 +End Point TNS : -171.346 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : -3.775 -End Point TNS : -35.541 +Slack : -3.770 +End Point TNS : -34.841 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Slack : -2.784 End Point TNS : -2.784 + +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Slack : 6.261 +End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -21150,15 +28741,19 @@ End Point TNS : -2.784 ; Fast 1200mV 0C Model Hold Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -0.053 -End Point TNS : -0.089 +Slack : 0.098 +End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Slack : 0.177 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 0.178 +Slack : 0.177 +End Point TNS : 0.000 + +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Slack : 0.186 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -21172,8 +28767,8 @@ End Point TNS : 0.000 ; Fast 1200mV 0C Model Recovery Summary ; +--------------------------------------------------------------------------------+ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : -4.693 -End Point TNS : -358.284 +Slack : -4.684 +End Point TNS : -358.844 +--------------------------------------------------------------------------------+ @@ -21182,7 +28777,7 @@ End Point TNS : -358.284 ; Fast 1200mV 0C Model Removal Summary ; +--------------------------------------------------------------------------------+ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 2.518 +Slack : 2.507 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -21191,6 +28786,10 @@ End Point TNS : 0.000 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +--------------------------------------------------------------------------------+ +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Slack : 4.783 +End Point TNS : 0.000 + Clock : CLOCK_50 Slack : 9.208 End Point TNS : 0.000 @@ -21213,905 +28812,905 @@ End Point TNS : 0.000 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -14.971 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 5.024 - -Slack : -14.965 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 5.018 - -Slack : -14.951 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 5.004 - -Slack : -14.940 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 4.993 - -Slack : -14.933 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 4.985 - -Slack : -14.932 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 4.984 - -Slack : -14.927 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 4.979 - -Slack : -14.893 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 4.946 - -Slack : -14.893 -From Node : ula:ula_|video:video_|bits[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.942 - -Slack : -14.880 +Slack : -15.243 From Node : ula:ula_|video:video_|vga_hc[1] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.929 +Clock Skew : -0.028 +Data Delay : 5.289 -Slack : -14.864 -From Node : ula:ula_|video:video_|vga_vc[7] +Slack : -15.162 +From Node : ula:ula_|video:video_|bits[5] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 4.917 +Clock Skew : -0.028 +Data Delay : 5.208 -Slack : -14.860 -From Node : ula:ula_|video:video_|vga_vc[6] +Slack : -15.156 +From Node : ula:ula_|video:video_|vga_vc[9] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 4.913 +Clock Skew : -0.028 +Data Delay : 5.202 -Slack : -14.853 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 4.906 - -Slack : -14.842 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 4.894 - -Slack : -14.824 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 4.877 - -Slack : -14.800 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 4.853 - -Slack : -14.761 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.811 - -Slack : -14.737 -From Node : ula:ula_|video:video_|bits[1] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.786 - -Slack : -14.728 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 4.780 - -Slack : -14.718 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 4.770 - -Slack : -14.694 +Slack : -15.144 From Node : ula:ula_|video:video_|frame[4] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.743 +Clock Skew : -0.024 +Data Delay : 5.194 -Slack : -14.690 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 -To Node : GPIO_1[20] +Slack : -15.131 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.178 -Data Delay : 4.586 +Clock Skew : -0.028 +Data Delay : 5.177 -Slack : -14.685 +Slack : -15.128 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 5.174 + +Slack : -15.126 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 5.172 + +Slack : -15.110 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 5.156 + +Slack : -15.104 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 5.150 + +Slack : -15.097 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 5.143 + +Slack : -15.090 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 5.136 + +Slack : -15.069 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 5.115 + +Slack : -15.047 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 5.093 + +Slack : -15.044 From Node : ula:ula_|video:video_|bits[6] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.734 +Clock Skew : -0.028 +Data Delay : 5.090 -Slack : -14.667 +Slack : -15.028 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 5.074 + +Slack : -15.022 From Node : ula:ula_|video:video_|bits[7] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.716 +Clock Skew : -0.028 +Data Delay : 5.068 -Slack : -14.623 +Slack : -15.021 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 5.067 + +Slack : -15.008 +From Node : ula:ula_|video:video_|bits[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 5.054 + +Slack : -15.005 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 5.051 + +Slack : -14.970 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 5.016 + +Slack : -14.969 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.013 +Data Delay : 5.030 + +Slack : -14.959 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.174 +Data Delay : 4.859 + +Slack : -14.952 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.169 +Data Delay : 4.857 + +Slack : -14.952 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.178 +Data Delay : 4.848 + +Slack : -14.948 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 4.994 + +Slack : -14.919 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.013 +Data Delay : 4.980 + +Slack : -14.911 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.178 +Data Delay : 4.807 + +Slack : -14.908 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 4.954 + +Slack : -14.900 +From Node : ula:ula_|video:video_|vga_hc[9] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 4.946 + +Slack : -14.886 +From Node : ula:ula_|video:video_|bits[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 4.932 + +Slack : -14.886 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.013 +Data Delay : 4.947 + +Slack : -14.874 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +To Node : DRAM_DQ[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.178 +Data Delay : 4.770 + +Slack : -14.869 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.013 +Data Delay : 4.930 + +Slack : -14.866 +From Node : ula:ula_|video:video_|bits[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 4.912 + +Slack : -14.859 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.174 -Data Delay : 4.523 +Data Delay : 4.759 -Slack : -14.609 -From Node : ula:ula_|video:video_|bits[2] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.658 - -Slack : -14.606 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.019 -Data Delay : 4.661 - -Slack : -14.593 -From Node : ula:ula_|video:video_|bits[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.642 - -Slack : -14.587 +Slack : -14.853 From Node : ula:ula_|video:video_|attr[7] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.636 +Clock Skew : -0.028 +Data Delay : 4.899 -Slack : -14.564 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.019 -Data Delay : 4.619 - -Slack : -14.561 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.020 -Data Delay : 4.615 - -Slack : -14.543 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.179 -Data Delay : 4.438 - -Slack : -14.517 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.185 -Data Delay : 4.406 - -Slack : -14.515 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.564 - -Slack : -14.515 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.184 -Data Delay : 4.405 - -Slack : -14.501 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.179 -Data Delay : 4.396 - -Slack : -14.497 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.169 -Data Delay : 4.402 - -Slack : -14.494 +Slack : -14.852 From Node : ula:ula_|video:video_|bits[4] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.543 +Clock Skew : -0.028 +Data Delay : 4.898 -Slack : -14.474 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.019 -Data Delay : 4.529 - -Slack : -14.462 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 -To Node : GPIO_1[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.178 -Data Delay : 4.358 - -Slack : -14.459 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.179 -Data Delay : 4.354 - -Slack : -14.425 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.179 -Data Delay : 4.320 - -Slack : -14.420 -From Node : ula:ula_|video:video_|bits[0] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.469 - -Slack : -14.413 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.176 -Data Delay : 4.311 - -Slack : -14.388 +Slack : -14.852 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.181 -Data Delay : 4.281 +Clock Skew : -0.169 +Data Delay : 4.757 -Slack : -14.372 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 -To Node : GPIO_1[19] +Slack : -14.852 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.178 -Data Delay : 4.268 +Data Delay : 4.748 -Slack : -14.341 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.183 -Data Delay : 4.232 - -Slack : -14.340 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.183 -Data Delay : 4.231 - -Slack : -14.337 +Slack : -14.846 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[21] +To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.019 -Data Delay : 4.392 +Clock Skew : -0.013 +Data Delay : 4.907 -Slack : -14.335 +Slack : -14.838 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.178 +Data Delay : 4.734 + +Slack : -14.800 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.174 +Data Delay : 4.700 + +Slack : -14.786 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[21] +To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.020 -Data Delay : 4.389 +Clock Skew : -0.013 +Data Delay : 4.847 -Slack : -14.333 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[17] +Slack : -14.774 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.020 -Data Delay : 4.387 +Clock Skew : -0.178 +Data Delay : 4.670 -Slack : -14.325 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 -To Node : GPIO_1[16] +Slack : -14.769 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +To Node : DRAM_DQ[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.184 -Data Delay : 4.215 +Clock Skew : -0.177 +Data Delay : 4.666 -Slack : -14.310 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.019 -Data Delay : 4.365 - -Slack : -14.285 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.019 -Data Delay : 4.340 - -Slack : -14.285 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 -To Node : GPIO_1[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.184 -Data Delay : 4.175 - -Slack : -14.284 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.176 -Data Delay : 4.182 - -Slack : -14.281 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 -To Node : GPIO_1[21] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.171 -Data Delay : 4.184 - -Slack : -14.271 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.019 -Data Delay : 4.326 - -Slack : -14.259 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 -To Node : GPIO_1[19] +Slack : -14.749 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 +To Node : DRAM_DQ[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.179 -Data Delay : 4.154 +Data Delay : 4.644 -Slack : -14.250 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 -To Node : GPIO_1[16] +Slack : -14.733 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +To Node : DRAM_DQ[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.185 -Data Delay : 4.139 +Clock Skew : -0.174 +Data Delay : 4.633 -Slack : -14.247 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[19] +Slack : -14.729 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +To Node : DRAM_DQ[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.020 -Data Delay : 4.301 +Clock Skew : -0.178 +Data Delay : 4.625 -Slack : -14.221 -From Node : ula:ula_|video:video_|attr[0] +Slack : -14.727 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.174 +Data Delay : 4.627 + +Slack : -14.700 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.181 +Data Delay : 4.593 + +Slack : -14.697 +From Node : ula:ula_|video:video_|bits[0] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.271 +Clock Skew : -0.028 +Data Delay : 4.743 -Slack : -14.206 +Slack : -14.696 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.177 +Data Delay : 4.593 + +Slack : -14.689 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.177 -Data Delay : 4.103 +Clock Skew : -0.174 +Data Delay : 4.589 -Slack : -14.203 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 -To Node : GPIO_1[21] +Slack : -14.685 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.171 -Data Delay : 4.106 +Clock Skew : -0.178 +Data Delay : 4.581 -Slack : -14.195 +Slack : -14.681 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.013 +Data Delay : 4.742 + +Slack : -14.644 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.013 +Data Delay : 4.705 + +Slack : -14.637 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.013 +Data Delay : 4.698 + +Slack : -14.636 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.531 + +Slack : -14.632 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.185 +Data Delay : 4.521 + +Slack : -14.625 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.178 +Data Delay : 4.521 + +Slack : -14.614 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +To Node : DRAM_DQ[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.509 + +Slack : -14.611 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.013 +Data Delay : 4.672 + +Slack : -14.607 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.177 +Data Delay : 4.504 + +Slack : -14.582 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.183 +Data Delay : 4.473 + +Slack : -14.567 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.184 +Data Delay : 4.457 + +Slack : -14.544 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.013 +Data Delay : 4.605 + +Slack : -14.542 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.013 +Data Delay : 4.603 + +Slack : -14.541 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.436 + +Slack : -14.541 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.013 +Data Delay : 4.602 + +Slack : -14.538 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.183 -Data Delay : 4.086 +Data Delay : 4.429 -Slack : -14.189 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[23] +Slack : -14.536 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : DRAM_DQ[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.019 -Data Delay : 4.244 +Clock Skew : -0.176 +Data Delay : 4.434 -Slack : -14.183 +Slack : -14.535 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 4.581 + +Slack : -14.517 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[16] +To Node : DRAM_DQ[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.020 -Data Delay : 4.237 +Clock Skew : -0.013 +Data Delay : 4.578 -Slack : -14.169 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 -To Node : GPIO_1[21] +Slack : -14.504 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +To Node : DRAM_DQ[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.178 -Data Delay : 4.065 +Clock Skew : -0.179 +Data Delay : 4.399 -Slack : -14.155 +Slack : -14.502 +From Node : ula:ula_|video:video_|attr[0] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.028 +Data Delay : 4.548 + +Slack : -14.499 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.184 +Data Delay : 4.389 + +Slack : -14.499 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.013 +Data Delay : 4.560 + +Slack : -14.492 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.177 -Data Delay : 4.052 +Clock Skew : -0.176 +Data Delay : 4.390 -Slack : -14.138 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +Slack : -14.488 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : DRAM_DQ[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.383 + +Slack : -14.472 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.185 +Data Delay : 4.361 + +Slack : -14.462 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.357 + +Slack : -14.455 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.174 -Data Delay : 4.038 +Clock Skew : -0.013 +Data Delay : 4.516 -Slack : -14.126 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 -To Node : GPIO_1[23] +Slack : -14.439 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : DRAM_DQ[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.183 -Data Delay : 4.017 +Clock Skew : -0.184 +Data Delay : 4.329 -Slack : -14.124 +Slack : -14.438 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.178 +Data Delay : 4.334 + +Slack : -14.438 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.013 +Data Delay : 4.499 + +Slack : -14.415 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.310 + +Slack : -14.413 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 To Node : GPIO_1[21] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.174 -Data Delay : 4.024 +Clock Skew : -0.181 +Data Delay : 4.306 -Slack : -14.114 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[18] +Slack : -14.401 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +To Node : DRAM_DQ[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.020 -Data Delay : 4.168 +Clock Skew : -0.176 +Data Delay : 4.299 -Slack : -14.045 +Slack : -14.389 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.185 +Data Delay : 4.278 + +Slack : -14.387 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.177 +Data Delay : 4.284 + +Slack : -14.382 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.177 +Data Delay : 4.279 + +Slack : -14.380 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +To Node : DRAM_DQ[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.171 +Data Delay : 4.283 + +Slack : -14.374 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : DRAM_DQ[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.013 +Data Delay : 4.435 + +Slack : -14.357 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.013 +Data Delay : 4.418 + +Slack : -14.355 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.013 +Data Delay : 4.416 + +Slack : -14.350 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : DRAM_DQ[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.184 +Data Delay : 4.240 + +Slack : -14.346 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.241 + +Slack : -14.330 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.013 +Data Delay : 4.391 + +Slack : -14.328 From Node : ula:ula_|video:video_|attr[3] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.094 +Clock Skew : -0.028 +Data Delay : 4.374 -Slack : -14.020 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 -To Node : GPIO_1[23] +Slack : -14.325 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 +To Node : DRAM_DQ[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.177 -Data Delay : 3.917 - -Slack : -13.997 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 -To Node : GPIO_1[23] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.181 -Data Delay : 3.890 - -Slack : -13.949 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[23] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.020 -Data Delay : 4.003 - -Slack : -13.888 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.941 - -Slack : -13.887 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.940 - -Slack : -13.882 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 3.934 - -Slack : -13.881 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 -To Node : GPIO_1[23] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.177 -Data Delay : 3.778 - -Slack : -13.868 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 3.920 - -Slack : -13.841 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.894 - -Slack : -13.826 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.879 - -Slack : -13.816 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.869 - -Slack : -13.812 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.865 - -Slack : -13.811 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.864 - -Slack : -13.806 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 3.858 - -Slack : -13.792 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 3.844 - -Slack : -13.784 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 3.836 - -Slack : -13.765 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.818 - -Slack : -13.750 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.803 - -Slack : -13.747 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.800 - -Slack : -13.744 -From Node : ula:ula_|video:video_|bits[5] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 3.793 - -Slack : -13.742 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.795 - -Slack : -13.742 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.795 - -Slack : -13.740 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.793 - -Slack : -13.738 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.791 - -Slack : -13.731 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 3.783 - -Slack : -13.731 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 3.780 +Clock Skew : -0.171 +Data Delay : 4.228 +--------------------------------------------------------------------------------+ @@ -22119,905 +29718,905 @@ Data Delay : 3.780 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : -4.979 +Slack : -4.921 From Node : raw_loader_in To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 Clock Skew : -0.058 -Data Delay : 3.010 +Data Delay : 2.952 -Slack : -4.977 -From Node : raw_loader_in -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -0.052 -Data Delay : 3.014 - -Slack : -4.861 +Slack : -4.920 From Node : raw_loader_in To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -0.051 -Data Delay : 2.899 +Clock Skew : -0.062 +Data Delay : 2.947 -Slack : -4.849 +Slack : -4.682 From Node : raw_loader_in To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -0.052 -Data Delay : 2.886 +Clock Skew : -0.053 +Data Delay : 2.718 -Slack : -4.418 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.376 -Data Delay : 3.131 - -Slack : -4.378 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.374 -Data Delay : 3.093 - -Slack : -4.335 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.371 -Data Delay : 3.053 - -Slack : -4.297 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.340 -Data Delay : 3.046 - -Slack : -4.275 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.355 -Data Delay : 3.009 - -Slack : -4.272 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.370 -Data Delay : 2.991 - -Slack : -4.269 +Slack : -4.553 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.390 -Data Delay : 2.968 +Clock Skew : -1.381 +Data Delay : 3.261 -Slack : -4.267 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.384 -Data Delay : 2.972 - -Slack : -4.253 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.369 -Data Delay : 2.973 - -Slack : -4.232 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.346 -Data Delay : 2.975 - -Slack : -4.230 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.369 -Data Delay : 2.950 - -Slack : -4.220 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.370 -Data Delay : 2.939 - -Slack : -4.204 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.339 -Data Delay : 2.954 - -Slack : -4.200 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.378 -Data Delay : 2.911 - -Slack : -4.196 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.383 -Data Delay : 2.902 - -Slack : -4.194 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.341 -Data Delay : 2.942 - -Slack : -4.159 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.351 -Data Delay : 2.897 - -Slack : -4.157 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.345 -Data Delay : 2.901 - -Slack : -4.153 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.358 -Data Delay : 2.884 - -Slack : -4.152 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.355 -Data Delay : 2.886 - -Slack : -4.151 +Slack : -4.552 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.383 -Data Delay : 2.857 +Clock Skew : -1.385 +Data Delay : 3.256 -Slack : -4.149 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.341 -Data Delay : 2.897 - -Slack : -4.139 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.384 -Data Delay : 2.844 - -Slack : -4.131 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.372 -Data Delay : 2.848 - -Slack : -4.130 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.369 -Data Delay : 2.850 - -Slack : -4.126 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.380 -Data Delay : 2.835 - -Slack : -4.124 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +Slack : -4.500 +From Node : raw_loader_in To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.374 -Data Delay : 2.839 +Clock Skew : -0.054 +Data Delay : 2.535 -Slack : -4.115 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Slack : -4.470 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.349 -Data Delay : 2.855 +Clock Skew : -1.383 +Data Delay : 3.176 -Slack : -4.109 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.371 -Data Delay : 2.827 - -Slack : -4.086 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.340 -Data Delay : 2.835 - -Slack : -4.073 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.370 -Data Delay : 2.792 - -Slack : -4.071 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.365 -Data Delay : 2.795 - -Slack : -4.071 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.359 -Data Delay : 2.801 - -Slack : -4.061 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.367 -Data Delay : 2.783 - -Slack : -4.059 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.356 -Data Delay : 2.792 - -Slack : -4.056 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.210 -Data Delay : 2.935 - -Slack : -4.055 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.369 -Data Delay : 2.775 - -Slack : -4.048 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.378 -Data Delay : 2.759 - -Slack : -4.044 +Slack : -4.454 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.373 -Data Delay : 2.760 +Clock Skew : -1.387 +Data Delay : 3.156 -Slack : -4.041 +Slack : -4.454 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.345 +Data Delay : 3.198 + +Slack : -4.453 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.384 +Data Delay : 3.158 + +Slack : -4.453 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.344 -Data Delay : 2.786 +Clock Skew : -1.349 +Data Delay : 3.193 -Slack : -4.035 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.341 -Data Delay : 2.783 - -Slack : -4.034 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.340 -Data Delay : 2.783 - -Slack : -4.029 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.345 -Data Delay : 2.773 - -Slack : -4.022 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.348 -Data Delay : 2.763 - -Slack : -4.021 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +Slack : -4.451 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.363 -Data Delay : 2.747 +Clock Skew : -1.384 +Data Delay : 3.156 -Slack : -4.018 +Slack : -4.427 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.367 +Data Delay : 3.149 + +Slack : -4.427 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.374 +Data Delay : 3.142 + +Slack : -4.408 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.368 +Data Delay : 3.129 + +Slack : -4.386 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.375 -Data Delay : 2.732 +Clock Skew : -1.385 +Data Delay : 3.090 -Slack : -4.010 +Slack : -4.363 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.379 +Data Delay : 3.073 + +Slack : -4.346 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.388 +Data Delay : 3.047 + +Slack : -4.343 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.369 +Data Delay : 3.063 + +Slack : -4.320 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 Clock Skew : -1.380 -Data Delay : 2.719 +Data Delay : 3.029 -Slack : -4.008 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.373 -Data Delay : 2.724 - -Slack : -4.003 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.348 -Data Delay : 2.744 - -Slack : -4.002 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.361 -Data Delay : 2.730 - -Slack : -4.001 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.336 -Data Delay : 2.754 - -Slack : -3.999 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.331 -Data Delay : 2.757 - -Slack : -3.999 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.338 -Data Delay : 2.750 - -Slack : -3.996 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.374 -Data Delay : 2.711 - -Slack : -3.994 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.350 -Data Delay : 2.733 - -Slack : -3.993 +Slack : -4.320 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.379 -Data Delay : 2.703 +Clock Skew : -1.385 +Data Delay : 3.024 -Slack : -3.989 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Slack : -4.314 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.333 -Data Delay : 2.745 +Clock Skew : -1.376 +Data Delay : 3.027 -Slack : -3.985 +Slack : -4.312 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.346 +Data Delay : 3.055 + +Slack : -4.292 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.375 +Data Delay : 3.006 + +Slack : -4.280 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.339 +Data Delay : 3.030 + +Slack : -4.269 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.380 +Data Delay : 2.978 + +Slack : -4.265 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.357 +Data Delay : 2.997 + +Slack : -4.261 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.340 +Data Delay : 3.010 + +Slack : -4.249 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.381 +Data Delay : 2.957 + +Slack : -4.233 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.387 +Data Delay : 2.935 + +Slack : -4.226 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.364 +Data Delay : 2.951 + +Slack : -4.221 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.384 +Data Delay : 2.926 + +Slack : -4.215 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.340 +Data Delay : 2.964 + +Slack : -4.205 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.379 -Data Delay : 2.695 +Clock Skew : -1.372 +Data Delay : 2.922 -Slack : -3.985 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Slack : -4.200 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.363 -Data Delay : 2.711 +Clock Skew : -1.381 +Data Delay : 2.908 -Slack : -3.982 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.350 -Data Delay : 2.721 - -Slack : -3.980 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.382 -Data Delay : 2.687 - -Slack : -3.980 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.345 -Data Delay : 2.724 - -Slack : -3.975 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.367 -Data Delay : 2.697 - -Slack : -3.973 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.383 -Data Delay : 2.679 - -Slack : -3.973 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.205 -Data Delay : 2.857 - -Slack : -3.972 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.364 -Data Delay : 2.697 - -Slack : -3.971 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Slack : -4.199 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 Clock Skew : -1.378 -Data Delay : 2.682 +Data Delay : 2.910 -Slack : -3.970 +Slack : -4.196 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.341 +Data Delay : 2.944 + +Slack : -4.178 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.375 +Data Delay : 2.892 + +Slack : -4.177 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.374 +Data Delay : 2.892 + +Slack : -4.173 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.382 +Data Delay : 2.880 + +Slack : -4.172 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.379 +Data Delay : 2.882 + +Slack : -4.168 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.351 +Data Delay : 2.906 + +Slack : -4.164 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.377 +Data Delay : 2.876 + +Slack : -4.163 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.344 +Data Delay : 2.908 + +Slack : -4.162 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.377 +Data Delay : 2.874 + +Slack : -4.159 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.373 +Data Delay : 2.875 + +Slack : -4.158 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.363 +Data Delay : 2.884 + +Slack : -4.158 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.355 +Data Delay : 2.892 + +Slack : -4.155 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 Clock Skew : -1.347 -Data Delay : 2.712 +Data Delay : 2.897 -Slack : -3.963 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.339 -Data Delay : 2.713 - -Slack : -3.961 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.380 -Data Delay : 2.670 - -Slack : -3.961 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.380 -Data Delay : 2.670 - -Slack : -3.960 +Slack : -4.146 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.356 -Data Delay : 2.693 +Clock Skew : -1.343 +Data Delay : 2.892 -Slack : -3.954 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Slack : -4.143 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.204 +Clock Skew : -1.375 +Data Delay : 2.857 + +Slack : -4.136 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.345 +Data Delay : 2.880 + +Slack : -4.134 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.368 +Data Delay : 2.855 + +Slack : -4.133 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.383 Data Delay : 2.839 -Slack : -3.953 +Slack : -4.132 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.380 +Data Delay : 2.841 + +Slack : -4.132 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.377 +Data Delay : 2.844 + +Slack : -4.132 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.373 +Data Delay : 2.848 + +Slack : -4.129 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.381 +Data Delay : 2.837 + +Slack : -4.115 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.342 +Data Delay : 2.862 + +Slack : -4.115 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.361 +Data Delay : 2.843 + +Slack : -4.095 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.349 +Data Delay : 2.835 + +Slack : -4.079 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.336 +Data Delay : 2.832 + +Slack : -4.065 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.335 -Data Delay : 2.707 +Clock Skew : -1.349 +Data Delay : 2.805 -Slack : -3.950 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Slack : -4.061 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.371 -Data Delay : 2.668 +Clock Skew : -1.357 +Data Delay : 2.793 -Slack : -3.949 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.362 -Data Delay : 2.676 - -Slack : -3.948 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.359 -Data Delay : 2.678 - -Slack : -3.944 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.382 -Data Delay : 2.651 - -Slack : -3.936 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.343 -Data Delay : 2.682 - -Slack : -3.932 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +Slack : -4.058 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.210 -Data Delay : 2.811 +Clock Skew : -1.340 +Data Delay : 2.807 -Slack : -3.926 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Slack : -4.058 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.213 -Data Delay : 2.802 +Clock Skew : -1.377 +Data Delay : 2.770 -Slack : -3.920 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.343 -Data Delay : 2.666 - -Slack : -3.916 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.356 -Data Delay : 2.649 - -Slack : -3.914 +Slack : -4.057 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.368 -Data Delay : 2.635 +Clock Skew : -1.373 +Data Delay : 2.773 -Slack : -3.914 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.350 -Data Delay : 2.653 - -Slack : -3.910 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.204 -Data Delay : 2.795 - -Slack : -3.898 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.350 -Data Delay : 2.637 - -Slack : -3.896 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.368 -Data Delay : 2.617 - -Slack : -3.896 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.369 -Data Delay : 2.616 - -Slack : -3.892 +Slack : -4.052 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.362 -Data Delay : 2.619 +Clock Skew : -1.372 +Data Delay : 2.769 -Slack : -3.879 +Slack : -4.051 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.376 +Data Delay : 2.764 + +Slack : -4.046 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 +Clock Skew : -1.333 +Data Delay : 2.802 + +Slack : -4.043 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 Clock Skew : -1.348 -Data Delay : 2.620 +Data Delay : 2.784 -Slack : -3.878 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Slack : -4.042 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.366 -Data Delay : 2.601 +Clock Skew : -1.352 +Data Delay : 2.779 -Slack : -3.875 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Slack : -4.040 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.370 -Data Delay : 2.594 +Clock Skew : -1.372 +Data Delay : 2.757 -Slack : -3.870 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +Slack : -4.039 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.373 +Data Delay : 2.755 + +Slack : -4.036 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.338 -Data Delay : 2.621 +Clock Skew : -1.208 +Data Delay : 2.917 -Slack : -3.862 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Slack : -4.033 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.350 -Data Delay : 2.601 +Clock Skew : -1.341 +Data Delay : 2.781 -Slack : -3.860 +Slack : -4.031 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.341 +Data Delay : 2.779 + +Slack : -4.027 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.334 +Data Delay : 2.782 + +Slack : -4.022 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.355 +Data Delay : 2.756 + +Slack : -4.021 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.375 +Data Delay : 2.735 + +Slack : -4.020 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.379 +Data Delay : 2.730 + +Slack : -4.015 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.357 +Data Delay : 2.747 + +Slack : -4.002 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.341 +Data Delay : 2.750 + +Slack : -4.000 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.348 +Data Delay : 2.741 + +Slack : -3.996 From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.366 -Data Delay : 2.583 +Clock Skew : -1.368 +Data Delay : 2.717 + +Slack : -3.991 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.342 +Data Delay : 2.738 + +Slack : -3.990 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.338 +Data Delay : 2.741 + +Slack : -3.989 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.378 +Data Delay : 2.700 + +Slack : -3.979 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.368 +Data Delay : 2.700 + +Slack : -3.979 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.367 +Data Delay : 2.701 + +Slack : -3.970 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.356 +Data Delay : 2.703 + +Slack : -3.963 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.370 +Data Delay : 2.682 + +Slack : -3.962 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.335 +Data Delay : 2.716 + +Slack : -3.956 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.340 +Data Delay : 2.705 + +Slack : -3.945 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.378 +Data Delay : 2.656 + +Slack : -3.937 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.350 +Data Delay : 2.676 + +Slack : -3.929 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.348 +Data Delay : 2.670 + +Slack : -3.928 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.373 +Data Delay : 2.644 + +Slack : -3.924 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.357 +Data Delay : 2.656 + +Slack : -3.918 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.351 +Data Delay : 2.656 +--------------------------------------------------------------------------------+ @@ -23025,905 +30624,905 @@ Data Delay : 2.583 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : -3.775 +Slack : -3.770 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.248 -Data Delay : 1.851 +Data Delay : 1.846 -Slack : -3.717 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 1.862 - -Slack : -3.717 +Slack : -3.712 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.226 -Data Delay : 1.862 +Data Delay : 1.857 -Slack : -3.603 +Slack : -3.712 From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.226 -Data Delay : 1.748 +Data Delay : 1.857 -Slack : -3.603 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 1.748 - -Slack : -3.603 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 1.748 - -Slack : -3.603 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 1.748 - -Slack : -3.603 +Slack : -3.473 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 1.748 +Clock Skew : -0.039 +Data Delay : 1.805 -Slack : -3.360 +Slack : -3.473 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 1.805 + +Slack : -3.473 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 1.805 + +Slack : -3.473 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 1.805 + +Slack : -3.473 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 1.805 + +Slack : -3.355 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.226 -Data Delay : 1.505 +Data Delay : 1.500 -Slack : -2.957 +Slack : -2.927 From Node : AUD_ADCDAT To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.044 -Data Delay : 1.284 +Clock Skew : -0.029 +Data Delay : 1.269 -Slack : 18.580 +Slack : 18.452 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.984 +Clock Skew : -0.278 +Data Delay : 2.108 -Slack : 18.583 +Slack : 18.460 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 2.100 + +Slack : 18.530 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.981 +Clock Skew : -0.278 +Data Delay : 2.030 -Slack : 18.654 +Slack : 18.563 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.273 +Data Delay : 2.002 + +Slack : 18.563 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.273 +Data Delay : 2.002 + +Slack : 18.563 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.910 +Clock Skew : -0.278 +Data Delay : 1.997 -Slack : 18.654 +Slack : 18.563 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.910 +Clock Skew : -0.278 +Data Delay : 1.997 -Slack : 18.657 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Slack : 18.565 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.995 + +Slack : 18.565 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.995 + +Slack : 18.565 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.995 + +Slack : 18.565 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.995 + +Slack : 18.565 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.995 + +Slack : 18.571 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.273 +Data Delay : 1.994 + +Slack : 18.571 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.273 +Data Delay : 1.994 + +Slack : 18.571 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.907 +Clock Skew : -0.278 +Data Delay : 1.989 -Slack : 18.657 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Slack : 18.571 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.907 +Clock Skew : -0.278 +Data Delay : 1.989 -Slack : 18.675 +Slack : 18.573 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.987 + +Slack : 18.573 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.889 +Clock Skew : -0.278 +Data Delay : 1.987 -Slack : 18.700 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.864 - -Slack : 18.700 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Slack : 18.573 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.864 +Clock Skew : -0.278 +Data Delay : 1.987 -Slack : 18.700 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Slack : 18.573 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.864 +Clock Skew : -0.278 +Data Delay : 1.987 -Slack : 18.700 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Slack : 18.573 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.864 +Clock Skew : -0.278 +Data Delay : 1.987 -Slack : 18.703 +Slack : 18.588 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.972 + +Slack : 18.641 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.919 + +Slack : 18.641 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.919 + +Slack : 18.643 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.861 +Clock Skew : -0.278 +Data Delay : 1.917 -Slack : 18.703 +Slack : 18.643 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.917 + +Slack : 18.643 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.861 +Clock Skew : -0.278 +Data Delay : 1.917 -Slack : 18.703 +Slack : 18.643 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.861 +Clock Skew : -0.278 +Data Delay : 1.917 -Slack : 18.703 +Slack : 18.643 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 +Clock Skew : -0.278 +Data Delay : 1.917 + +Slack : 18.651 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.273 +Data Delay : 1.914 + +Slack : 18.651 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.273 +Data Delay : 1.914 + +Slack : 18.699 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 Data Delay : 1.861 -Slack : 18.725 +Slack : 18.699 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.861 + +Slack : 18.701 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.859 + +Slack : 18.701 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 +Clock Skew : -0.278 +Data Delay : 1.859 + +Slack : 18.701 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.859 + +Slack : 18.701 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.859 + +Slack : 18.701 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.859 + +Slack : 18.709 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.273 +Data Delay : 1.856 + +Slack : 18.709 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.273 +Data Delay : 1.856 + +Slack : 18.780 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.083 +Data Delay : 1.975 + +Slack : 18.788 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.083 +Data Delay : 1.967 + +Slack : 18.815 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.748 + +Slack : 18.815 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.748 + +Slack : 18.823 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.740 + +Slack : 18.823 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.740 + +Slack : 18.839 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.721 + +Slack : 18.858 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.083 +Data Delay : 1.897 + +Slack : 18.893 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.670 + +Slack : 18.893 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.670 + +Slack : 18.898 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.662 + +Slack : 18.916 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.083 Data Delay : 1.839 -Slack : 18.739 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Slack : 18.936 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.825 +Clock Skew : -0.273 +Data Delay : 1.629 -Slack : 18.739 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Slack : 18.936 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.825 +Clock Skew : -0.273 +Data Delay : 1.629 -Slack : 18.740 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.824 - -Slack : 18.740 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.824 - -Slack : 18.750 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Slack : 18.950 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.814 +Clock Skew : -0.278 +Data Delay : 1.610 -Slack : 18.750 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Slack : 18.950 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.814 +Clock Skew : -0.278 +Data Delay : 1.610 -Slack : 18.769 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.792 - -Slack : 18.769 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.792 - -Slack : 18.772 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.789 - -Slack : 18.772 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.789 - -Slack : 18.774 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.790 - -Slack : 18.774 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.790 - -Slack : 18.774 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.790 - -Slack : 18.774 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.790 - -Slack : 18.799 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.765 - -Slack : 18.799 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.765 - -Slack : 18.803 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.761 - -Slack : 18.811 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.753 - -Slack : 18.811 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.753 - -Slack : 18.823 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.741 - -Slack : 18.823 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.741 - -Slack : 18.823 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.741 - -Slack : 18.823 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.741 - -Slack : 18.823 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.741 - -Slack : 18.824 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.740 - -Slack : 18.824 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.740 - -Slack : 18.824 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.740 - -Slack : 18.824 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.740 - -Slack : 18.824 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.740 - -Slack : 18.831 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.733 - -Slack : 18.831 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.733 - -Slack : 18.831 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.733 - -Slack : 18.831 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.733 - -Slack : 18.865 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.696 - -Slack : 18.865 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.696 - -Slack : 18.868 +Slack : 18.951 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.696 +Clock Skew : -0.275 +Data Delay : 1.612 -Slack : 18.868 +Slack : 18.951 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.696 +Clock Skew : -0.275 +Data Delay : 1.612 -Slack : 18.877 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.687 - -Slack : 18.877 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.687 - -Slack : 18.895 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.669 - -Slack : 18.895 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.669 - -Slack : 18.895 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.669 - -Slack : 18.895 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.669 - -Slack : 18.895 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.669 - -Slack : 18.909 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.652 - -Slack : 18.910 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.651 - -Slack : 18.914 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.647 - -Slack : 18.914 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.647 - -Slack : 18.923 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 18.952 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.641 +Clock Skew : -0.278 +Data Delay : 1.608 -Slack : 18.923 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.641 - -Slack : 18.923 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.641 - -Slack : 18.923 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.641 - -Slack : 18.947 +Slack : 18.952 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.617 +Clock Skew : -0.278 +Data Delay : 1.608 Slack : 18.952 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.612 - -Slack : 18.952 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.612 - -Slack : 18.952 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.612 - -Slack : 18.952 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.612 - -Slack : 18.952 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.612 - -Slack : 18.981 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.580 - -Slack : 18.989 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.087 -Data Delay : 1.762 - -Slack : 18.991 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.573 - -Slack : 18.991 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.573 - -Slack : 18.992 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.569 - -Slack : 18.992 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.569 - -Slack : 18.992 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.087 -Data Delay : 1.759 - -Slack : 19.021 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.543 - -Slack : 19.021 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.543 - -Slack : 19.038 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.523 - -Slack : 19.067 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.497 - -Slack : 19.067 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.497 +Clock Skew : -0.278 +Data Delay : 1.608 -Slack : 19.067 +Slack : 18.952 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.497 +Clock Skew : -0.278 +Data Delay : 1.608 -Slack : 19.067 +Slack : 18.952 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.497 +Clock Skew : -0.278 +Data Delay : 1.608 -Slack : 19.074 +Slack : 18.970 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.590 + +Slack : 18.970 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.590 + +Slack : 18.970 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.590 + +Slack : 18.970 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.590 + +Slack : 18.978 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.582 + +Slack : 18.978 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.582 + +Slack : 18.978 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.582 + +Slack : 18.978 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.582 + +Slack : 18.988 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.273 +Data Delay : 1.577 + +Slack : 18.988 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.273 +Data Delay : 1.577 + +Slack : 19.006 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.490 +Clock Skew : -0.088 +Data Delay : 1.744 -Slack : 19.074 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 19.006 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.490 +Clock Skew : -0.088 +Data Delay : 1.744 + +Slack : 19.006 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.088 +Data Delay : 1.744 + +Slack : 19.006 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.088 +Data Delay : 1.744 + +Slack : 19.006 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.088 +Data Delay : 1.744 + +Slack : 19.009 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.551 + +Slack : 19.009 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.551 + +Slack : 19.011 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.549 + +Slack : 19.011 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.549 + +Slack : 19.011 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.549 + +Slack : 19.011 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.549 + +Slack : 19.011 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.549 + +Slack : 19.014 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.088 +Data Delay : 1.736 + +Slack : 19.014 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.088 +Data Delay : 1.736 + +Slack : 19.014 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.088 +Data Delay : 1.736 + +Slack : 19.014 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.088 +Data Delay : 1.736 + +Slack : 19.014 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.088 +Data Delay : 1.736 +--------------------------------------------------------------------------------+ @@ -23940,14 +31539,14 @@ Relationship : 0.423 Clock Skew : -0.021 Data Delay : 1.133 -Slack : 70.890 +Slack : 70.891 From Node : ula:ula_|clocks:clocks_|counter[0] To Node : ula:ula_|clocks:clocks_|clk_cpu Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Relationship : 71.489 Clock Skew : -0.046 -Data Delay : 0.540 +Data Delay : 0.539 Slack : 71.071 From Node : ula:ula_|clocks:clocks_|counter[0] @@ -23970,908 +31569,1814 @@ Data Delay : 0.359 ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : 6.261 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.031 +Data Delay : 3.647 + +Slack : 6.273 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.031 +Data Delay : 3.635 + +Slack : 6.330 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.031 +Data Delay : 3.578 + +Slack : 6.342 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.031 +Data Delay : 3.566 + +Slack : 6.363 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.040 +Data Delay : 3.536 + +Slack : 6.366 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.031 +Data Delay : 3.542 + +Slack : 6.378 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.040 +Data Delay : 3.521 + +Slack : 6.388 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.040 +Data Delay : 3.511 + +Slack : 6.390 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.039 +Data Delay : 3.510 + +Slack : 6.405 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.039 +Data Delay : 3.495 + +Slack : 6.415 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.039 +Data Delay : 3.485 + +Slack : 6.437 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.040 +Data Delay : 3.462 + +Slack : 6.438 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.040 +Data Delay : 3.461 + +Slack : 6.456 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.040 +Data Delay : 3.443 + +Slack : 6.464 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.040 +Data Delay : 3.435 + +Slack : 6.464 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.039 +Data Delay : 3.436 + +Slack : 6.465 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.039 +Data Delay : 3.435 + +Slack : 6.483 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.039 +Data Delay : 3.417 + +Slack : 6.491 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.039 +Data Delay : 3.409 + +Slack : 6.513 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.040 +Data Delay : 3.386 + +Slack : 6.524 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.040 +Data Delay : 3.375 + +Slack : 6.540 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.039 +Data Delay : 3.360 + +Slack : 6.551 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.039 +Data Delay : 3.349 + +Slack : 6.561 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.038 +Data Delay : 3.340 + +Slack : 6.566 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.039 +Data Delay : 3.334 + +Slack : 6.576 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.038 +Data Delay : 3.325 + +Slack : 6.578 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.041 +Data Delay : 3.321 + +Slack : 6.581 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.040 +Data Delay : 3.318 + +Slack : 6.586 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.038 +Data Delay : 3.315 + +Slack : 6.590 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.041 +Data Delay : 3.309 + +Slack : 6.593 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.038 +Data Delay : 3.308 + +Slack : 6.606 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 3.279 + +Slack : 6.608 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.033 +Data Delay : 3.298 + +Slack : 6.608 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.address[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.039 +Data Delay : 3.292 + +Slack : 6.614 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.036 +Data Delay : 3.289 + +Slack : 6.615 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.029 +Data Delay : 3.295 + +Slack : 6.620 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.033 +Data Delay : 3.286 + +Slack : 6.621 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 3.264 + +Slack : 6.631 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 3.254 + +Slack : 6.635 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.038 +Data Delay : 3.266 + +Slack : 6.636 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.038 +Data Delay : 3.265 + +Slack : 6.647 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.041 +Data Delay : 3.252 + +Slack : 6.654 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.038 +Data Delay : 3.247 + +Slack : 6.659 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.041 +Data Delay : 3.240 + +Slack : 6.662 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.038 +Data Delay : 3.239 + +Slack : 6.671 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.034 +Data Delay : 3.234 + +Slack : 6.677 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.033 +Data Delay : 3.229 + +Slack : 6.680 +From Node : sdram_controller:sdram_|r.rd_pending +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.029 +Data Delay : 3.230 + +Slack : 6.680 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 3.205 + +Slack : 6.681 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 3.204 + +Slack : 6.682 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.033 +Data Delay : 3.224 + +Slack : 6.683 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.041 +Data Delay : 3.216 + +Slack : 6.683 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.034 +Data Delay : 3.222 + +Slack : 6.688 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.039 +Data Delay : 3.212 + +Slack : 6.689 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.033 +Data Delay : 3.217 + +Slack : 6.699 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 3.186 + +Slack : 6.707 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 3.178 + +Slack : 6.711 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.038 +Data Delay : 3.190 + +Slack : 6.713 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.033 +Data Delay : 3.193 + +Slack : 6.714 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.state[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.043 +Data Delay : 3.183 + +Slack : 6.722 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.038 +Data Delay : 3.179 + +Slack : 6.732 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.061 +Data Delay : 3.147 + +Slack : 6.737 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.061 +Data Delay : 3.142 + +Slack : 6.738 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.037 +Data Delay : 3.164 + +Slack : 6.738 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.037 +Data Delay : 3.164 + +Slack : 6.739 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.041 +Data Delay : 3.160 + +Slack : 6.740 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.034 +Data Delay : 3.165 + +Slack : 6.741 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.061 +Data Delay : 3.138 + +Slack : 6.750 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.048 +Data Delay : 3.142 + +Slack : 6.752 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.034 +Data Delay : 3.153 + +Slack : 6.756 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 3.129 + +Slack : 6.762 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.048 +Data Delay : 3.130 + +Slack : 6.764 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.037 +Data Delay : 3.138 + +Slack : 6.767 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 3.118 + +Slack : 6.768 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.033 +Data Delay : 3.138 + +Slack : 6.776 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.035 +Data Delay : 3.128 + +Slack : 6.776 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.bank[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.034 +Data Delay : 3.129 + +Slack : 6.779 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.address[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.038 +Data Delay : 3.122 + +Slack : 6.780 +From Node : sdram_controller:sdram_|r.act_row[3] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.033 +Data Delay : 3.126 + +Slack : 6.799 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.037 +Data Delay : 3.103 + +Slack : 6.804 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.061 +Data Delay : 3.075 + +Slack : 6.809 +From Node : sdram_controller:sdram_|r.init_counter[3] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 3.077 + +Slack : 6.812 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.061 +Data Delay : 3.067 + +Slack : 6.814 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.048 +Data Delay : 3.078 + +Slack : 6.824 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.055 +Data Delay : 3.061 + +Slack : 6.825 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.045 +Data Delay : 3.070 + +Slack : 6.829 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.061 +Data Delay : 3.050 + +Slack : 6.831 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.048 +Data Delay : 3.061 + +Slack : 6.837 +From Node : sdram_controller:sdram_|r.act_row[0] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.033 +Data Delay : 3.069 + +Slack : 6.842 +From Node : sdram_controller:sdram_|r.state[4] +To Node : sdram_controller:sdram_|r.address[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.046 +Data Delay : 3.052 + +Slack : 6.842 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.061 +Data Delay : 3.037 + +Slack : 6.849 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.address[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.048 +Data Delay : 3.043 + +Slack : 6.849 +From Node : sdram_controller:sdram_|r.act_row[1] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.033 +Data Delay : 3.057 + +Slack : 6.850 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.state[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.040 +Data Delay : 3.097 + +Slack : 6.852 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.address[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.040 +Data Delay : 3.047 + +Slack : 6.863 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.address[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.041 +Data Delay : 3.036 + +Slack : 6.865 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.state[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.040 +Data Delay : 3.082 + +Slack : 6.867 +From Node : sdram_controller:sdram_|r.act_row[2] +To Node : sdram_controller:sdram_|r.state[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.054 +Data Delay : 3.019 + +Slack : 6.873 +From Node : sdram_controller:sdram_|r.act_row[4] +To Node : sdram_controller:sdram_|r.bank[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.033 +Data Delay : 3.033 + +Slack : 6.875 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.state[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 10.000 +Clock Skew : -0.040 +Data Delay : 3.072 ++--------------------------------------------------------------------------------+ + + + +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Hold: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -0.053 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Slack : 0.098 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.556 -Data Delay : 1.711 +Clock Skew : 1.563 +Data Delay : 1.869 -Slack : -0.036 +Slack : 0.136 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.566 +Data Delay : 1.910 + +Slack : 0.194 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.314 + +Slack : 0.237 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.557 -Data Delay : 1.729 +Clock Skew : 1.562 +Data Delay : 2.007 -Slack : 0.540 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.522 -Data Delay : 2.270 - -Slack : 0.548 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.524 -Data Delay : 2.280 - -Slack : 0.558 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.517 -Data Delay : 2.283 - -Slack : 0.559 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.281 - -Slack : 0.561 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.524 -Data Delay : 2.293 - -Slack : 0.564 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.526 -Data Delay : 2.298 - -Slack : 0.575 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.526 -Data Delay : 2.309 - -Slack : 0.603 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.516 -Data Delay : 2.327 - -Slack : 0.606 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.517 -Data Delay : 2.331 - -Slack : 0.606 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.509 -Data Delay : 2.323 - -Slack : 0.610 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.332 - -Slack : 0.618 +Slack : 0.244 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.575 -Data Delay : 2.401 +Clock Skew : 1.564 +Data Delay : 2.016 -Slack : 0.620 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.555 -Data Delay : 2.383 - -Slack : 0.623 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.558 -Data Delay : 2.389 - -Slack : 0.626 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.517 -Data Delay : 2.351 - -Slack : 0.637 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.571 -Data Delay : 2.416 - -Slack : 0.637 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.522 -Data Delay : 2.367 - -Slack : 0.638 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.519 -Data Delay : 2.365 - -Slack : 0.641 +Slack : 0.537 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.570 -Data Delay : 2.419 +Clock Skew : 1.572 +Data Delay : 2.317 -Slack : 0.646 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.513 -Data Delay : 2.367 - -Slack : 0.650 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.506 -Data Delay : 2.364 - -Slack : 0.650 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.372 - -Slack : 0.651 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.516 -Data Delay : 2.375 - -Slack : 0.651 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.516 -Data Delay : 2.375 - -Slack : 0.651 +Slack : 0.538 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.558 -Data Delay : 2.417 +Clock Skew : 1.566 +Data Delay : 2.312 -Slack : 0.653 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.375 - -Slack : 0.654 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.511 -Data Delay : 2.373 - -Slack : 0.655 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.513 -Data Delay : 2.376 - -Slack : 0.660 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.521 -Data Delay : 2.389 - -Slack : 0.661 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.521 -Data Delay : 2.390 - -Slack : 0.662 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.513 -Data Delay : 2.383 - -Slack : 0.665 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.387 - -Slack : 0.665 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.387 - -Slack : 0.666 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.508 -Data Delay : 2.382 - -Slack : 0.667 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.389 - -Slack : 0.669 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +Slack : 0.544 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.426 -Data Delay : 2.303 +Clock Skew : 1.406 +Data Delay : 2.158 -Slack : 0.669 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Slack : 0.545 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.506 -Data Delay : 2.383 +Clock Skew : 1.569 +Data Delay : 2.322 -Slack : 0.669 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.507 -Data Delay : 2.384 - -Slack : 0.669 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.507 -Data Delay : 2.384 - -Slack : 0.671 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.509 -Data Delay : 2.388 - -Slack : 0.675 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.516 -Data Delay : 2.399 - -Slack : 0.675 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.503 -Data Delay : 2.386 - -Slack : 0.677 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.517 -Data Delay : 2.402 - -Slack : 0.677 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.419 -Data Delay : 2.304 - -Slack : 0.681 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.509 -Data Delay : 2.398 - -Slack : 0.683 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.511 -Data Delay : 2.402 - -Slack : 0.687 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.507 -Data Delay : 2.402 - -Slack : 0.688 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.519 -Data Delay : 2.415 - -Slack : 0.688 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.506 -Data Delay : 2.402 - -Slack : 0.689 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.519 -Data Delay : 2.416 - -Slack : 0.689 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.507 -Data Delay : 2.404 - -Slack : 0.690 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.412 - -Slack : 0.690 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.503 -Data Delay : 2.401 - -Slack : 0.691 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.522 -Data Delay : 2.421 - -Slack : 0.691 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.503 -Data Delay : 2.402 - -Slack : 0.693 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.427 -Data Delay : 2.328 - -Slack : 0.695 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.563 -Data Delay : 2.466 - -Slack : 0.695 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.522 -Data Delay : 2.425 - -Slack : 0.695 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.507 -Data Delay : 2.410 - -Slack : 0.695 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.508 -Data Delay : 2.411 - -Slack : 0.696 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.418 - -Slack : 0.696 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.415 -Data Delay : 2.319 - -Slack : 0.698 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.517 -Data Delay : 2.423 - -Slack : 0.698 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.515 -Data Delay : 2.421 - -Slack : 0.698 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.508 -Data Delay : 2.414 - -Slack : 0.699 +Slack : 0.551 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.562 -Data Delay : 2.469 +Clock Skew : 1.577 +Data Delay : 2.336 -Slack : 0.699 -From Node : ula:ula_|video:video_|vram_address[5] +Slack : 0.556 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.564 +Data Delay : 2.328 + +Slack : 0.567 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.401 +Data Delay : 2.176 + +Slack : 0.568 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.569 +Data Delay : 2.345 + +Slack : 0.574 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.570 +Data Delay : 2.352 + +Slack : 0.577 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.562 +Data Delay : 2.347 + +Slack : 0.584 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.564 +Data Delay : 2.356 + +Slack : 0.591 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.561 +Data Delay : 2.360 + +Slack : 0.593 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.400 +Data Delay : 2.201 + +Slack : 0.596 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.564 +Data Delay : 2.368 + +Slack : 0.597 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.570 +Data Delay : 2.375 + +Slack : 0.599 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.572 +Data Delay : 2.379 + +Slack : 0.599 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.408 +Data Delay : 2.215 + +Slack : 0.600 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.566 +Data Delay : 2.374 + +Slack : 0.600 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.402 +Data Delay : 2.210 + +Slack : 0.605 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.558 +Data Delay : 2.371 + +Slack : 0.609 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.398 +Data Delay : 2.215 + +Slack : 0.610 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.406 +Data Delay : 2.224 + +Slack : 0.613 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.514 +Data Delay : 2.335 + +Slack : 0.616 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.395 +Data Delay : 2.219 + +Slack : 0.627 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.517 +Data Delay : 2.352 + +Slack : 0.628 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.412 +Data Delay : 2.248 + +Slack : 0.631 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.509 +Data Delay : 2.348 + +Slack : 0.632 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.509 +Data Delay : 2.349 + +Slack : 0.633 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.577 +Data Delay : 2.418 + +Slack : 0.637 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.521 +Data Delay : 2.366 + +Slack : 0.639 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.522 +Data Delay : 2.369 + +Slack : 0.639 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.407 +Data Delay : 2.254 + +Slack : 0.640 +From Node : ula:ula_|video:video_|vram_address[12] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.506 -Data Delay : 2.413 +Clock Skew : 1.511 +Data Delay : 2.359 -Slack : 0.699 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Slack : 0.642 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.504 +Clock Skew : 1.571 +Data Delay : 2.421 + +Slack : 0.642 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.569 +Data Delay : 2.419 + +Slack : 0.645 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.558 Data Delay : 2.411 -Slack : 0.700 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.508 -Data Delay : 2.416 - -Slack : 0.701 +Slack : 0.646 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.565 -Data Delay : 2.474 +Clock Skew : 1.579 +Data Delay : 2.433 -Slack : 0.702 +Slack : 0.647 From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.509 -Data Delay : 2.419 +Clock Skew : 1.513 +Data Delay : 2.368 -Slack : 0.703 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Slack : 0.649 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.506 -Data Delay : 2.417 +Clock Skew : 1.410 +Data Delay : 2.267 -Slack : 0.703 -From Node : ula:ula_|video:video_|vram_address[8] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Slack : 0.650 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.512 -Data Delay : 2.423 +Clock Skew : 1.524 +Data Delay : 2.382 -Slack : 0.704 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Slack : 0.655 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.515 +Data Delay : 2.378 + +Slack : 0.657 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.523 +Data Delay : 2.388 + +Slack : 0.657 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.413 +Data Delay : 2.278 + +Slack : 0.660 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 Clock Skew : 1.406 -Data Delay : 2.318 +Data Delay : 2.274 -Slack : 0.705 -From Node : ula:ula_|video:video_|vram_address[11] +Slack : 0.661 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.406 +Data Delay : 2.275 + +Slack : 0.666 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.405 +Data Delay : 2.279 + +Slack : 0.669 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.516 +Data Delay : 2.393 + +Slack : 0.669 +From Node : ula:ula_|video:video_|vram_address[10] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.525 -Data Delay : 2.438 +Clock Skew : 1.508 +Data Delay : 2.385 + +Slack : 0.671 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.513 +Data Delay : 2.392 + +Slack : 0.678 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.411 +Data Delay : 2.297 + +Slack : 0.679 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.503 +Data Delay : 2.390 + +Slack : 0.682 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.421 +Data Delay : 2.311 + +Slack : 0.685 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.524 +Data Delay : 2.417 + +Slack : 0.685 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.426 +Data Delay : 2.319 + +Slack : 0.686 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.510 +Data Delay : 2.404 + +Slack : 0.687 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.521 +Data Delay : 2.416 + +Slack : 0.687 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.518 +Data Delay : 2.413 + +Slack : 0.687 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.561 +Data Delay : 2.456 + +Slack : 0.688 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.523 +Data Delay : 2.419 + +Slack : 0.688 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.409 +Data Delay : 2.305 + +Slack : 0.688 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.420 +Data Delay : 2.316 + +Slack : 0.689 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.403 +Data Delay : 2.300 + +Slack : 0.690 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.579 +Data Delay : 2.477 + +Slack : 0.691 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.522 +Data Delay : 2.421 + +Slack : 0.691 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.516 +Data Delay : 2.415 + +Slack : 0.693 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.404 +Data Delay : 2.305 + +Slack : 0.694 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.518 +Data Delay : 2.420 + +Slack : 0.694 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.507 +Data Delay : 2.409 + +Slack : 0.694 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.508 +Data Delay : 2.410 + +Slack : 0.695 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.406 +Data Delay : 2.309 + +Slack : 0.696 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.573 +Data Delay : 2.477 + +Slack : 0.697 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.502 +Data Delay : 2.407 + +Slack : 0.698 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.422 +Data Delay : 2.328 + +Slack : 0.700 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.406 +Data Delay : 2.314 + +Slack : 0.701 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.403 +Data Delay : 2.312 + +Slack : 0.703 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.422 +Data Delay : 2.333 + +Slack : 0.705 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.513 +Data Delay : 2.426 Slack : 0.706 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 Clock Skew : 1.524 Data Delay : 2.438 -Slack : 0.706 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.509 -Data Delay : 2.423 - -Slack : 0.706 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.509 -Data Delay : 2.423 - -Slack : 0.707 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.509 -Data Delay : 2.424 - -Slack : 0.709 +Slack : 0.708 From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.506 -Data Delay : 2.423 +Clock Skew : 1.517 +Data Delay : 2.433 + +Slack : 0.708 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.405 +Data Delay : 2.321 Slack : 0.709 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.513 -Data Delay : 2.430 +Clock Skew : 1.516 +Data Delay : 2.433 Slack : 0.710 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.503 -Data Delay : 2.421 +Clock Skew : 1.515 +Data Delay : 2.433 Slack : 0.711 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 Clock Skew : 1.517 Data Delay : 2.436 -Slack : 0.712 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.511 -Data Delay : 2.431 - -Slack : 0.712 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.512 -Data Delay : 2.432 - -Slack : 0.712 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.423 -Data Delay : 2.343 - -Slack : 0.713 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.511 -Data Delay : 2.432 - -Slack : 0.713 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.575 -Data Delay : 2.496 - -Slack : 0.714 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.508 -Data Delay : 2.430 - -Slack : 0.714 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.508 -Data Delay : 2.430 - -Slack : 0.715 -From Node : ula:ula_|video:video_|vram_address[8] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.515 -Data Delay : 2.438 - -Slack : 0.716 +Slack : 0.711 From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.522 -Data Delay : 2.446 +Clock Skew : 1.510 +Data Delay : 2.429 -Slack : 0.719 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.441 - -Slack : 0.720 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.442 - -Slack : 0.724 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.524 -Data Delay : 2.456 - -Slack : 0.724 +Slack : 0.712 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.424 -Data Delay : 2.356 +Clock Skew : 1.414 +Data Delay : 2.334 -Slack : 0.725 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Slack : 0.713 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.421 -Data Delay : 2.354 +Clock Skew : 1.506 +Data Delay : 2.427 -Slack : 0.726 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Slack : 0.714 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.421 +Clock Skew : 1.522 +Data Delay : 2.444 + +Slack : 0.716 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.514 +Data Delay : 2.438 + +Slack : 0.717 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.413 +Data Delay : 2.338 + +Slack : 0.718 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.516 +Data Delay : 2.442 + +Slack : 0.718 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.516 +Data Delay : 2.442 + +Slack : 0.719 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.521 +Data Delay : 2.448 + +Slack : 0.719 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.517 +Data Delay : 2.444 + +Slack : 0.719 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.428 Data Delay : 2.355 + +Slack : 0.721 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.508 +Data Delay : 2.437 +--------------------------------------------------------------------------------+ @@ -24921,6 +33426,24 @@ Data Delay : 0.576 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ +Slack : 0.177 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.046 +Data Delay : 0.307 + +Slack : 0.177 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.046 +Data Delay : 0.307 + Slack : 0.178 From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] @@ -24930,15 +33453,33 @@ Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.307 -Slack : 0.184 +Slack : 0.183 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 +Clock Skew : 0.047 +Data Delay : 0.314 + +Slack : 0.184 +From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 Clock Skew : 0.046 Data Delay : 0.314 +Slack : 0.185 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.314 + Slack : 0.186 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data @@ -24958,17 +33499,17 @@ Clock Skew : 0.037 Data Delay : 0.307 Slack : 0.186 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.044 -Data Delay : 0.314 +Clock Skew : 0.037 +Data Delay : 0.307 Slack : 0.186 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -24985,68 +33526,23 @@ Clock Skew : 0.037 Data Delay : 0.307 Slack : 0.186 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.307 - -Slack : 0.186 -From Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.307 - -Slack : 0.186 -From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.044 -Data Delay : 0.314 - -Slack : 0.187 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.307 - -Slack : 0.187 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.307 - -Slack : 0.187 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.307 - -Slack : 0.187 From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.036 +Clock Skew : 0.037 Data Delay : 0.307 +Slack : 0.186 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.047 +Data Delay : 0.317 + Slack : 0.187 From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] @@ -25065,18 +33561,72 @@ Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.307 -Slack : 0.188 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 0.187 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.318 +Clock Skew : 0.036 +Data Delay : 0.307 + +Slack : 0.192 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.313 Slack : 0.193 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.314 + +Slack : 0.193 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.314 + +Slack : 0.193 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.314 + +Slack : 0.193 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.314 + +Slack : 0.193 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.314 + +Slack : 0.193 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -25084,8 +33634,17 @@ Clock Skew : 0.037 Data Delay : 0.314 Slack : 0.194 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.315 + +Slack : 0.194 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -25093,175 +33652,211 @@ Clock Skew : 0.036 Data Delay : 0.314 Slack : 0.194 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.314 -Slack : 0.195 +Slack : 0.194 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.314 + +Slack : 0.196 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.317 + +Slack : 0.197 From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.315 +Data Delay : 0.317 -Slack : 0.200 +Slack : 0.203 From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.320 +Data Delay : 0.323 -Slack : 0.201 +Slack : 0.203 From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.321 +Data Delay : 0.323 -Slack : 0.204 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Slack : 0.226 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.231 +Data Delay : 0.541 + +Slack : 0.243 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.240 +Data Delay : 0.567 + +Slack : 0.261 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.324 +Data Delay : 0.381 -Slack : 0.208 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Slack : 0.271 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.328 +Data Delay : 0.391 -Slack : 0.210 +Slack : 0.278 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.330 +Clock Skew : 0.037 +Data Delay : 0.399 -Slack : 0.243 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Slack : 0.287 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.372 +Clock Skew : 0.047 +Data Delay : 0.418 -Slack : 0.244 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Slack : 0.288 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.373 +Clock Skew : 0.037 +Data Delay : 0.409 -Slack : 0.244 +Slack : 0.288 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.047 +Data Delay : 0.419 + +Slack : 0.289 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.410 + +Slack : 0.289 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.047 +Data Delay : 0.420 + +Slack : 0.293 From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.373 +Clock Skew : 0.037 +Data Delay : 0.414 -Slack : 0.244 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.373 - -Slack : 0.245 +Slack : 0.294 From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.374 +Clock Skew : 0.037 +Data Delay : 0.415 -Slack : 0.262 +Slack : 0.294 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.415 + +Slack : 0.294 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.415 + +Slack : 0.294 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.415 + +Slack : 0.295 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.047 +Data Delay : 0.426 + +Slack : 0.296 From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.382 - -Slack : 0.266 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.034 -Data Delay : 0.384 - -Slack : 0.288 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.418 - -Slack : 0.289 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.419 - -Slack : 0.291 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.421 - -Slack : 0.292 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.060 -Data Delay : 0.436 - -Slack : 0.292 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.412 +Data Delay : 0.416 Slack : 0.296 From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] @@ -25272,464 +33867,401 @@ Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.416 -Slack : 0.296 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.426 - -Slack : 0.296 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.426 - -Slack : 0.297 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.417 - -Slack : 0.298 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.034 -Data Delay : 0.416 - -Slack : 0.298 +Slack : 0.299 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.419 +Data Delay : 0.420 -Slack : 0.298 +Slack : 0.299 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.419 +Data Delay : 0.420 -Slack : 0.298 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Slack : 0.304 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.419 +Data Delay : 0.425 -Slack : 0.302 +Slack : 0.306 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.423 - -Slack : 0.303 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.424 - -Slack : 0.305 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.623 +Clock Skew : 0.249 +Data Delay : 0.639 Slack : 0.307 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.436 - -Slack : 0.307 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.436 - -Slack : 0.307 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.436 - -Slack : 0.307 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.436 - -Slack : 0.308 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.437 - -Slack : 0.308 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.437 - -Slack : 0.308 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.437 - -Slack : 0.308 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.429 +Data Delay : 0.428 -Slack : 0.309 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Slack : 0.307 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.438 +Clock Skew : 0.037 +Data Delay : 0.428 -Slack : 0.309 +Slack : 0.310 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.430 +Data Delay : 0.431 -Slack : 0.317 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Slack : 0.311 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.437 +Clock Skew : 0.037 +Data Delay : 0.432 -Slack : 0.320 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.440 - -Slack : 0.325 +Slack : 0.315 From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.445 +Clock Skew : 0.044 +Data Delay : 0.443 -Slack : 0.328 +Slack : 0.319 From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.448 +Clock Skew : 0.044 +Data Delay : 0.447 -Slack : 0.332 +Slack : 0.320 From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.452 +Clock Skew : 0.044 +Data Delay : 0.448 -Slack : 0.341 +Slack : 0.321 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.044 +Data Delay : 0.449 + +Slack : 0.325 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.446 + +Slack : 0.328 From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.461 +Clock Skew : 0.044 +Data Delay : 0.456 -Slack : 0.341 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Slack : 0.369 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.461 - -Slack : 0.346 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.466 - -Slack : 0.370 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.490 +Clock Skew : 0.047 +Data Delay : 0.500 Slack : 0.371 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.491 -Slack : 0.373 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Slack : 0.372 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.046 +Data Delay : 0.502 + +Slack : 0.374 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.493 +Data Delay : 0.494 -Slack : 0.397 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Slack : 0.375 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : -0.154 -Data Delay : 0.327 +Clock Skew : 0.246 +Data Delay : 0.705 -Slack : 0.398 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Slack : 0.375 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.039 -Data Delay : 0.521 +Clock Skew : 0.036 +Data Delay : 0.495 -Slack : 0.402 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Slack : 0.375 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.039 -Data Delay : 0.525 +Clock Skew : 0.036 +Data Delay : 0.495 -Slack : 0.404 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Slack : 0.378 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.498 + +Slack : 0.380 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.500 + +Slack : 0.381 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : -0.149 +Data Delay : 0.316 + +Slack : 0.386 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.039 -Data Delay : 0.527 - -Slack : 0.409 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.529 +Data Delay : 0.506 -Slack : 0.410 +Slack : 0.388 From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.530 +Data Delay : 0.508 -Slack : 0.411 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.531 - -Slack : 0.424 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Slack : 0.395 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.545 +Data Delay : 0.516 -Slack : 0.427 +Slack : 0.396 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.246 +Data Delay : 0.726 + +Slack : 0.401 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.521 + +Slack : 0.402 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.030 +Data Delay : 0.516 + +Slack : 0.412 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.532 + +Slack : 0.424 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.030 +Data Delay : 0.538 + +Slack : 0.426 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.548 +Data Delay : 0.547 -Slack : 0.430 +Slack : 0.427 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.551 +Data Delay : 0.548 -Slack : 0.432 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Slack : 0.435 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.552 +Data Delay : 0.555 -Slack : 0.437 +Slack : 0.435 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.556 + +Slack : 0.436 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.556 + +Slack : 0.436 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.046 +Clock Skew : 0.047 Data Delay : 0.567 -Slack : 0.438 +Slack : 0.437 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.046 +Clock Skew : 0.047 Data Delay : 0.568 Slack : 0.443 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : -0.155 -Data Delay : 0.372 +Clock Skew : 0.039 +Data Delay : 0.566 -Slack : 0.446 +Slack : 0.444 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.039 +Data Delay : 0.567 + +Slack : 0.447 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.567 +Data Delay : 0.568 -Slack : 0.446 +Slack : 0.447 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.567 - -Slack : 0.446 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.567 - -Slack : 0.447 -From Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.567 - -Slack : 0.448 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 Data Delay : 0.568 -Slack : 0.448 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Slack : 0.447 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.039 -Data Delay : 0.571 +Clock Skew : 0.047 +Data Delay : 0.578 Slack : 0.448 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] @@ -25737,35 +34269,26 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.578 +Clock Skew : 0.047 +Data Delay : 0.579 -Slack : 0.449 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.044 -Data Delay : 0.577 - -Slack : 0.449 +Slack : 0.450 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.579 +Clock Skew : 0.047 +Data Delay : 0.581 -Slack : 0.449 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Slack : 0.451 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.579 +Clock Skew : 0.036 +Data Delay : 0.571 Slack : 0.451 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] @@ -25773,53 +34296,941 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.581 +Clock Skew : 0.047 +Data Delay : 0.582 -Slack : 0.452 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Slack : 0.453 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.572 +Data Delay : 0.573 -Slack : 0.452 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.582 - -Slack : 0.452 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.582 - -Slack : 0.457 +Slack : 0.455 From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.577 +Data Delay : 0.575 -Slack : 0.457 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Slack : 0.455 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.576 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : 0.186 +From Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1 +To Node : sdram_controller:sdram_|r.address[0]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.state[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.187 +From Node : sdram_controller:sdram_|r.wr_pending +To Node : sdram_controller:sdram_|r.wr_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.307 + +Slack : 0.187 +From Node : sdram_controller:sdram_|r.rd_pending +To Node : sdram_controller:sdram_|r.rd_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.307 + +Slack : 0.187 +From Node : sdram_controller:sdram_|r.rf_pending +To Node : sdram_controller:sdram_|r.rf_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.307 + +Slack : 0.193 +From Node : sdram_controller:sdram_|r.init_counter[0] +To Node : sdram_controller:sdram_|r.init_counter[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.314 + +Slack : 0.198 +From Node : sdram_controller:sdram_|r.rf_counter[9] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.318 + +Slack : 0.276 +From Node : sdram_controller:sdram_|r.state[8] +To Node : sdram_controller:sdram_|r.state[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.397 + +Slack : 0.296 +From Node : sdram_controller:sdram_|r.init_counter[14] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.417 + +Slack : 0.296 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.417 + +Slack : 0.297 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.417 + +Slack : 0.298 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.418 + +Slack : 0.298 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.419 + +Slack : 0.299 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.419 + +Slack : 0.299 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.419 + +Slack : 0.299 +From Node : sdram_controller:sdram_|r.rf_counter[7] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.419 + +Slack : 0.299 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.420 + +Slack : 0.300 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.420 + +Slack : 0.301 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.421 + +Slack : 0.301 +From Node : sdram_controller:sdram_|r.rf_counter[8] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.421 + +Slack : 0.304 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.425 + +Slack : 0.304 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.425 + +Slack : 0.304 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.425 + +Slack : 0.305 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.426 + +Slack : 0.305 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.426 + +Slack : 0.305 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.426 + +Slack : 0.307 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.428 + +Slack : 0.309 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[0] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.429 + +Slack : 0.317 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.438 + +Slack : 0.318 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.439 + +Slack : 0.324 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.state[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.445 + +Slack : 0.328 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.state[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.449 + +Slack : 0.328 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.state[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.449 + +Slack : 0.424 +From Node : sdram_controller:sdram_|r.address[4]~_Duplicate_1 +To Node : sdram_controller:sdram_|r.address[4]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.545 + +Slack : 0.427 +From Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 +To Node : sdram_controller:sdram_|r.address[5]~_Duplicate_1 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.548 + +Slack : 0.440 +From Node : sdram_controller:sdram_|r.state[7] +To Node : sdram_controller:sdram_|r.state[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.561 + +Slack : 0.446 +From Node : sdram_controller:sdram_|r.init_counter[13] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.567 + +Slack : 0.446 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.566 + +Slack : 0.447 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.568 + +Slack : 0.447 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.567 + +Slack : 0.448 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.568 + +Slack : 0.448 +From Node : sdram_controller:sdram_|r.rf_counter[7] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.568 + +Slack : 0.453 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.574 + +Slack : 0.455 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.576 + +Slack : 0.455 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.576 + +Slack : 0.456 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[1] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.576 + +Slack : 0.457 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.577 + +Slack : 0.458 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.578 + +Slack : 0.458 +From Node : sdram_controller:sdram_|r.init_counter[12] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.579 + +Slack : 0.459 +From Node : sdram_controller:sdram_|r.rf_counter[8] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.579 + +Slack : 0.459 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.579 + +Slack : 0.459 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.579 + +Slack : 0.460 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.580 + +Slack : 0.461 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.581 + +Slack : 0.462 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.582 + +Slack : 0.463 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.584 + +Slack : 0.463 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.584 + +Slack : 0.464 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.585 + +Slack : 0.464 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.585 + +Slack : 0.465 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[2] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.586 + +Slack : 0.466 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.587 + +Slack : 0.466 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.587 + +Slack : 0.466 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.587 + +Slack : 0.466 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.587 + +Slack : 0.467 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.588 + +Slack : 0.467 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.588 + +Slack : 0.473 +From Node : sdram_controller:sdram_|r.state[5] +To Node : sdram_controller:sdram_|r.state[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.594 + +Slack : 0.483 +From Node : sdram_controller:sdram_|r.state[6] +To Node : sdram_controller:sdram_|r.state[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.604 + +Slack : 0.497 +From Node : sdram_controller:sdram_|r.rf_counter[9] +To Node : sdram_controller:sdram_|r.rf_pending +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.617 + +Slack : 0.509 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.629 + +Slack : 0.510 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.631 + +Slack : 0.510 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.630 + +Slack : 0.511 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.631 + +Slack : 0.511 +From Node : sdram_controller:sdram_|r.rf_counter[7] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.631 + +Slack : 0.512 +From Node : sdram_controller:sdram_|r.rf_counter[1] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.632 + +Slack : 0.513 +From Node : sdram_controller:sdram_|r.init_counter[11] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.634 + +Slack : 0.513 +From Node : sdram_controller:sdram_|r.rf_counter[3] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.633 + +Slack : 0.514 +From Node : sdram_controller:sdram_|r.rf_counter[5] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.634 + +Slack : 0.516 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.637 + +Slack : 0.518 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.639 + +Slack : 0.519 +From Node : sdram_controller:sdram_|r.init_counter[5] +To Node : sdram_controller:sdram_|r.init_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.640 + +Slack : 0.521 +From Node : sdram_controller:sdram_|r.init_counter[9] +To Node : sdram_controller:sdram_|r.init_counter[12] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.642 + +Slack : 0.522 +From Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2 +To Node : sdram_controller:sdram_|r.address[11]~_Duplicate_2 +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.643 + +Slack : 0.522 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[3] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.642 + +Slack : 0.523 +From Node : sdram_controller:sdram_|r.rf_counter[6] +To Node : sdram_controller:sdram_|r.rf_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.643 + +Slack : 0.524 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.644 + +Slack : 0.525 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.645 + +Slack : 0.525 +From Node : sdram_controller:sdram_|r.rf_counter[0] +To Node : sdram_controller:sdram_|r.rf_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.645 + +Slack : 0.527 +From Node : sdram_controller:sdram_|r.rf_counter[2] +To Node : sdram_controller:sdram_|r.rf_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.647 + +Slack : 0.528 +From Node : sdram_controller:sdram_|r.rf_counter[4] +To Node : sdram_controller:sdram_|r.rf_counter[8] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.648 + +Slack : 0.529 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[5] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.650 + +Slack : 0.529 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.650 + +Slack : 0.529 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[13] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.650 + +Slack : 0.529 +From Node : sdram_controller:sdram_|r.init_counter[4] +To Node : sdram_controller:sdram_|r.init_counter[7] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.650 + +Slack : 0.530 +From Node : sdram_controller:sdram_|r.init_counter[8] +To Node : sdram_controller:sdram_|r.init_counter[11] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.651 + +Slack : 0.530 +From Node : sdram_controller:sdram_|r.init_counter[6] +To Node : sdram_controller:sdram_|r.init_counter[9] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.651 + +Slack : 0.531 +From Node : sdram_controller:sdram_|r.init_counter[1] +To Node : sdram_controller:sdram_|r.init_counter[4] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.652 + +Slack : 0.532 +From Node : sdram_controller:sdram_|r.init_counter[2] +To Node : sdram_controller:sdram_|r.init_counter[6] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.653 + +Slack : 0.532 +From Node : sdram_controller:sdram_|r.init_counter[7] +To Node : sdram_controller:sdram_|r.init_counter[10] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.653 + +Slack : 0.532 +From Node : sdram_controller:sdram_|r.init_counter[10] +To Node : sdram_controller:sdram_|r.init_counter[14] +Launch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.653 +--------------------------------------------------------------------------------+ @@ -25855,8 +35266,8 @@ Clock Skew : 0.037 Data Delay : 0.307 Slack : 0.186 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[0] +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|vga_vc[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -25864,8 +35275,8 @@ Clock Skew : 0.037 Data Delay : 0.307 Slack : 0.186 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : ula:ula_|video:video_|vga_vc[9] +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vga_vc[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -25900,8 +35311,8 @@ Clock Skew : 0.037 Data Delay : 0.307 Slack : 0.186 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : ula:ula_|video:video_|vga_vc[8] +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vga_vc[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -25909,8 +35320,17 @@ Clock Skew : 0.037 Data Delay : 0.307 Slack : 0.186 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vga_vc[4] +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vga_vc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vga_vc[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -25927,121 +35347,85 @@ Clock Skew : 0.037 Data Delay : 0.307 Slack : 0.186 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|vga_vc[7] +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vga_vc[8] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.307 -Slack : 0.293 +Slack : 0.294 From Node : ula:ula_|video:video_|frame[2] To Node : ula:ula_|video:video_|frame[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.414 - -Slack : 0.294 -From Node : ula:ula_|video:video_|frame[3] -To Node : ula:ula_|video:video_|frame[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 Data Delay : 0.415 -Slack : 0.300 +Slack : 0.295 +From Node : ula:ula_|video:video_|frame[3] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.416 + +Slack : 0.319 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.440 + +Slack : 0.368 From Node : ula:ula_|video:video_|frame[1] To Node : ula:ula_|video:video_|frame[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.421 +Data Delay : 0.489 -Slack : 0.303 -From Node : ula:ula_|video:video_|frame[4] -To Node : ula:ula_|video:video_|frame[4] +Slack : 0.418 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.424 +Clock Skew : 0.045 +Data Delay : 0.547 -Slack : 0.336 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.457 - -Slack : 0.400 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.521 - -Slack : 0.442 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.568 - -Slack : 0.442 +Slack : 0.443 From Node : ula:ula_|video:video_|frame[2] To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.563 - -Slack : 0.452 -From Node : ula:ula_|video:video_|frame[3] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.573 - -Slack : 0.453 -From Node : ula:ula_|video:video_|frame[1] -To Node : ula:ula_|video:video_|frame[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.574 - -Slack : 0.456 -From Node : ula:ula_|video:video_|frame[1] -To Node : ula:ula_|video:video_|frame[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.577 +Data Delay : 0.564 Slack : 0.457 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|vga_hc[8] +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.578 +Clock Skew : 0.036 +Data Delay : 0.577 + +Slack : 0.465 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.585 Slack : 0.481 From Node : ula:ula_|video:video_|frame[0] @@ -26049,224 +35433,269 @@ To Node : ula:ula_|video:video_|frame[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.601 +Clock Skew : -0.140 +Data Delay : 0.425 -Slack : 0.505 -From Node : ula:ula_|video:video_|frame[2] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.626 - -Slack : 0.519 -From Node : ula:ula_|video:video_|frame[1] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.640 - -Slack : 0.524 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.650 - -Slack : 0.534 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.660 - -Slack : 0.544 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.039 -Data Delay : 0.667 - -Slack : 0.581 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.040 -Data Delay : 0.705 - -Slack : 0.582 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.040 -Data Delay : 0.706 - -Slack : 0.582 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.040 -Data Delay : 0.706 - -Slack : 0.582 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.040 -Data Delay : 0.706 - -Slack : 0.592 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.041 -Data Delay : 0.717 - -Slack : 0.595 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.041 -Data Delay : 0.720 - -Slack : 0.597 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vram_address[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.041 -Data Delay : 0.722 - -Slack : 0.598 -From Node : ula:ula_|video:video_|bits_prefetch[6] -To Node : ula:ula_|video:video_|bits[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.160 -Data Delay : 0.522 - -Slack : 0.610 -From Node : ula:ula_|video:video_|bits_prefetch[1] -To Node : ula:ula_|video:video_|bits[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.160 -Data Delay : 0.534 - -Slack : 0.611 +Slack : 0.494 From Node : ula:ula_|video:video_|vga_hc[4] To Node : ula:ula_|video:video_|vram_address[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.041 -Data Delay : 0.736 +Clock Skew : 0.036 +Data Delay : 0.614 -Slack : 0.613 +Slack : 0.520 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.641 + +Slack : 0.523 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.644 + +Slack : 0.531 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vram_address[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.651 + +Slack : 0.535 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.655 + +Slack : 0.535 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vram_address[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.655 + +Slack : 0.567 +From Node : ula:ula_|video:video_|frame[4] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.688 + +Slack : 0.593 +From Node : ula:ula_|video:video_|bits_prefetch[1] +To Node : ula:ula_|video:video_|bits[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.140 +Data Delay : 0.537 + +Slack : 0.594 From Node : ula:ula_|video:video_|bits_prefetch[2] To Node : ula:ula_|video:video_|bits[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.160 -Data Delay : 0.537 +Clock Skew : -0.140 +Data Delay : 0.538 -Slack : 0.619 +Slack : 0.594 From Node : ula:ula_|video:video_|bits_prefetch[5] To Node : ula:ula_|video:video_|bits[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.160 -Data Delay : 0.543 +Clock Skew : -0.140 +Data Delay : 0.538 -Slack : 0.633 +Slack : 0.603 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.723 + +Slack : 0.608 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.728 + +Slack : 0.613 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.732 + +Slack : 0.626 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : ula:ula_|video:video_|vga_hc[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.747 + +Slack : 0.634 From Node : ula:ula_|video:video_|frame[0] To Node : ula:ula_|video:video_|frame[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.753 +Clock Skew : -0.140 +Data Delay : 0.578 -Slack : 0.636 +Slack : 0.637 From Node : ula:ula_|video:video_|frame[0] To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.756 +Clock Skew : -0.140 +Data Delay : 0.581 -Slack : 0.641 +Slack : 0.637 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.757 + +Slack : 0.648 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.767 + +Slack : 0.656 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.775 + +Slack : 0.656 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.775 + +Slack : 0.656 From Node : ula:ula_|video:video_|vga_hc[6] To Node : ula:ula_|video:video_|vram_address[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.041 -Data Delay : 0.766 +Clock Skew : 0.036 +Data Delay : 0.776 -Slack : 0.652 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vga_hc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.773 - -Slack : 0.661 +Slack : 0.659 From Node : ula:ula_|video:video_|vga_vc[6] To Node : ula:ula_|video:video_|vram_address[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.787 +Clock Skew : 0.035 +Data Delay : 0.778 -Slack : 0.673 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[6] +Slack : 0.662 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[8] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.799 +Clock Skew : 0.035 +Data Delay : 0.781 + +Slack : 0.664 +From Node : ula:ula_|video:video_|bits_prefetch[4] +To Node : ula:ula_|video:video_|bits[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.140 +Data Delay : 0.608 + +Slack : 0.669 +From Node : ula:ula_|video:video_|bits_prefetch[7] +To Node : ula:ula_|video:video_|bits[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.140 +Data Delay : 0.613 + +Slack : 0.669 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.788 Slack : 0.674 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[2] +From Node : ula:ula_|video:video_|attr_prefetch[6] +To Node : ula:ula_|video:video_|attr[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.795 +Clock Skew : -0.154 +Data Delay : 0.604 + +Slack : 0.676 +From Node : ula:ula_|video:video_|attr_prefetch[0] +To Node : ula:ula_|video:video_|attr[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.154 +Data Delay : 0.606 + +Slack : 0.679 +From Node : ula:ula_|video:video_|attr_prefetch[3] +To Node : ula:ula_|video:video_|attr[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.154 +Data Delay : 0.609 Slack : 0.680 From Node : ula:ula_|video:video_|vga_vc[3] @@ -26274,8 +35703,8 @@ To Node : ula:ula_|video:video_|vram_address[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.806 +Clock Skew : 0.035 +Data Delay : 0.799 Slack : 0.683 From Node : ula:ula_|video:video_|vga_vc[3] @@ -26283,206 +35712,107 @@ To Node : ula:ula_|video:video_|vram_address[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.809 +Clock Skew : 0.035 +Data Delay : 0.802 Slack : 0.686 -From Node : ula:ula_|video:video_|bits_prefetch[0] -To Node : ula:ula_|video:video_|bits[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.160 -Data Delay : 0.610 - -Slack : 0.691 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.812 - -Slack : 0.691 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.812 - -Slack : 0.691 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.812 - -Slack : 0.691 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.812 - -Slack : 0.693 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.819 - -Slack : 0.694 -From Node : ula:ula_|video:video_|attr_prefetch[3] -To Node : ula:ula_|video:video_|attr[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.174 -Data Delay : 0.604 - -Slack : 0.695 -From Node : ula:ula_|video:video_|bits_prefetch[4] -To Node : ula:ula_|video:video_|bits[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.160 -Data Delay : 0.619 - -Slack : 0.699 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.819 - -Slack : 0.702 -From Node : ula:ula_|video:video_|attr_prefetch[5] -To Node : ula:ula_|video:video_|attr[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.174 -Data Delay : 0.612 - -Slack : 0.703 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|vram_address[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.824 - -Slack : 0.707 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vga_hc[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.828 - -Slack : 0.709 -From Node : ula:ula_|video:video_|attr_prefetch[7] -To Node : ula:ula_|video:video_|attr[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.174 -Data Delay : 0.619 - -Slack : 0.709 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : ula:ula_|video:video_|vga_hc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.830 - -Slack : 0.709 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.835 - -Slack : 0.710 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.831 - -Slack : 0.712 From Node : ula:ula_|video:video_|attr_prefetch[4] To Node : ula:ula_|video:video_|attr[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.175 -Data Delay : 0.621 +Clock Skew : -0.154 +Data Delay : 0.616 -Slack : 0.712 +Slack : 0.686 +From Node : ula:ula_|video:video_|attr_prefetch[1] +To Node : ula:ula_|video:video_|attr[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.154 +Data Delay : 0.616 + +Slack : 0.689 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.808 + +Slack : 0.689 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.808 + +Slack : 0.697 +From Node : ula:ula_|video:video_|attr_prefetch[5] +To Node : ula:ula_|video:video_|attr[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.154 +Data Delay : 0.627 + +Slack : 0.701 From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.820 + +Slack : 0.705 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.824 + +Slack : 0.711 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.830 + +Slack : 0.714 +From Node : ula:ula_|video:video_|vga_vc[1] To Node : ula:ula_|video:video_|vram_address[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.042 +Clock Skew : 0.035 +Data Delay : 0.833 + +Slack : 0.717 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|vga_vc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 Data Delay : 0.838 -Slack : 0.729 -From Node : ula:ula_|video:video_|attr_prefetch[0] -To Node : ula:ula_|video:video_|attr[0] +Slack : 0.717 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|vga_vc[8] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.175 -Data Delay : 0.638 - -Slack : 0.736 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vga_hc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.039 -Data Delay : 0.859 - -Slack : 0.736 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.862 - -Slack : 0.744 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.039 -Data Delay : 0.867 +Clock Skew : 0.037 +Data Delay : 0.838 Slack : 0.746 From Node : ula:ula_|video:video_|vga_vc[3] @@ -26490,242 +35820,323 @@ To Node : ula:ula_|video:video_|vram_address[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.872 +Clock Skew : 0.035 +Data Delay : 0.865 -Slack : 0.755 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[5] +Slack : 0.748 +From Node : ula:ula_|video:video_|frame[3] +To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.876 +Data Delay : 0.869 -Slack : 0.755 -From Node : ula:ula_|video:video_|vga_vc[0] +Slack : 0.749 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.869 + +Slack : 0.754 +From Node : ula:ula_|video:video_|bits_prefetch[3] +To Node : ula:ula_|video:video_|bits[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.140 +Data Delay : 0.698 + +Slack : 0.760 +From Node : ula:ula_|video:video_|vga_vc[2] To Node : ula:ula_|video:video_|vram_address[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.881 +Clock Skew : 0.035 +Data Delay : 0.879 -Slack : 0.758 -From Node : ula:ula_|video:video_|vga_vc[0] +Slack : 0.763 +From Node : ula:ula_|video:video_|vga_vc[2] To Node : ula:ula_|video:video_|vram_address[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.884 +Clock Skew : 0.035 +Data Delay : 0.882 -Slack : 0.771 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[5] +Slack : 0.765 +From Node : ula:ula_|video:video_|attr_prefetch[7] +To Node : ula:ula_|video:video_|attr[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.042 +Clock Skew : -0.154 +Data Delay : 0.695 + +Slack : 0.773 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.894 + +Slack : 0.776 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vga_hc[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 Data Delay : 0.897 -Slack : 0.774 +Slack : 0.777 From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.896 + +Slack : 0.797 +From Node : ula:ula_|video:video_|vga_vc[4] To Node : ula:ula_|video:video_|vram_address[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.900 +Clock Skew : 0.035 +Data Delay : 0.916 -Slack : 0.775 +Slack : 0.797 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.916 + +Slack : 0.801 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.922 + +Slack : 0.815 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.934 + +Slack : 0.825 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.945 + +Slack : 0.826 From Node : ula:ula_|video:video_|vga_vc[2] To Node : ula:ula_|video:video_|vram_address[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.901 +Clock Skew : 0.035 +Data Delay : 0.945 -Slack : 0.794 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vga_hc[8] +Slack : 0.827 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|vga_vc[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.915 +Data Delay : 0.948 -Slack : 0.803 -From Node : ula:ula_|video:video_|bits_prefetch[7] -To Node : ula:ula_|video:video_|bits[7] +Slack : 0.837 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vga_vc[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.160 -Data Delay : 0.727 +Clock Skew : 0.037 +Data Delay : 0.958 -Slack : 0.809 +Slack : 0.837 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vga_vc[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.958 + +Slack : 0.849 +From Node : ula:ula_|video:video_|bits_prefetch[6] +To Node : ula:ula_|video:video_|bits[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.140 +Data Delay : 0.793 + +Slack : 0.857 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.977 + +Slack : 0.859 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.980 + +Slack : 0.859 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.980 + +Slack : 0.859 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.980 + +Slack : 0.859 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.980 + +Slack : 0.859 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.980 + +Slack : 0.859 From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|vga_hc[9] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.039 -Data Delay : 0.932 +Clock Skew : 0.036 +Data Delay : 0.979 -Slack : 0.811 -From Node : ula:ula_|video:video_|attr_prefetch[2] -To Node : ula:ula_|video:video_|attr[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.174 -Data Delay : 0.721 - -Slack : 0.821 -From Node : ula:ula_|video:video_|vga_vc[0] +Slack : 0.860 +From Node : ula:ula_|video:video_|vga_vc[4] To Node : ula:ula_|video:video_|vram_address[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.947 +Clock Skew : 0.035 +Data Delay : 0.979 -Slack : 0.824 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[8] +Slack : 0.875 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.945 +Data Delay : 0.996 -Slack : 0.828 -From Node : ula:ula_|video:video_|attr_prefetch[6] -To Node : ula:ula_|video:video_|attr[6] +Slack : 0.881 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.178 -Data Delay : 0.734 +Clock Skew : 0.037 +Data Delay : 1.002 -Slack : 0.832 +Slack : 0.885 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vga_hc[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 1.006 + +Slack : 0.886 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vga_hc[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 1.007 + +Slack : 0.888 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vga_hc[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 1.008 + +Slack : 0.888 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 1.008 + +Slack : 0.894 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vga_hc[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.038 +Data Delay : 1.016 + +Slack : 0.899 From Node : ula:ula_|video:video_|vga_hc[2] To Node : ula:ula_|video:video_|vga_hc[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.953 - -Slack : 0.833 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vram_address[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.041 -Data Delay : 0.958 - -Slack : 0.833 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vram_address[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.041 -Data Delay : 0.958 - -Slack : 0.834 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.039 -Data Delay : 0.957 - -Slack : 0.836 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.957 - -Slack : 0.837 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.963 - -Slack : 0.841 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|vga_hc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.039 -Data Delay : 0.964 - -Slack : 0.845 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.257 -Data Delay : 1.186 - -Slack : 0.845 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.257 -Data Delay : 1.186 - -Slack : 0.845 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.257 -Data Delay : 1.186 - -Slack : 0.845 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.257 -Data Delay : 1.186 - -Slack : 0.845 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.257 -Data Delay : 1.186 - -Slack : 0.845 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.257 -Data Delay : 1.186 +Data Delay : 1.020 +--------------------------------------------------------------------------------+ @@ -26733,743 +36144,743 @@ Data Delay : 1.186 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : -4.693 +Slack : -4.684 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.225 -Data Delay : 2.791 +Data Delay : 2.782 -Slack : -4.693 +Slack : -4.684 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.227 -Data Delay : 2.789 +Data Delay : 2.780 -Slack : -4.693 +Slack : -4.684 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.230 -Data Delay : 2.786 +Data Delay : 2.777 -Slack : -4.692 +Slack : -4.683 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.226 -Data Delay : 2.789 +Data Delay : 2.780 -Slack : -4.692 +Slack : -4.683 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.228 -Data Delay : 2.787 +Data Delay : 2.778 -Slack : -4.583 +Slack : -4.566 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.248 -Data Delay : 2.659 +Data Delay : 2.642 -Slack : -4.575 +Slack : -4.566 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.251 -Data Delay : 2.648 +Data Delay : 2.639 -Slack : -4.430 +Slack : -4.421 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 +Clock Skew : -0.221 +Data Delay : 2.571 -Slack : -4.430 +Slack : -4.421 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 +Clock Skew : -0.221 +Data Delay : 2.571 -Slack : -4.430 +Slack : -4.421 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 +Clock Skew : -0.221 +Data Delay : 2.571 -Slack : -4.430 +Slack : -4.421 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 +Clock Skew : -0.221 +Data Delay : 2.571 -Slack : -4.430 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 - -Slack : -4.430 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 - -Slack : -4.430 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 - -Slack : -4.430 +Slack : -4.421 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 +Clock Skew : -0.221 +Data Delay : 2.571 -Slack : -4.430 +Slack : -4.421 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 +Clock Skew : -0.221 +Data Delay : 2.571 -Slack : -4.430 +Slack : -4.421 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.229 -Data Delay : 2.572 +Data Delay : 2.563 -Slack : -4.430 +Slack : -4.421 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.229 -Data Delay : 2.572 +Data Delay : 2.563 -Slack : -4.430 +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.563 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.224 +Data Delay : 2.568 + +Slack : -4.421 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.224 +Data Delay : 2.568 + +Slack : -4.421 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.229 -Data Delay : 2.572 +Data Delay : 2.563 -Slack : -4.430 +Slack : -4.421 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.229 -Data Delay : 2.572 +Data Delay : 2.563 -Slack : -4.430 +Slack : -4.421 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.229 -Data Delay : 2.572 +Data Delay : 2.563 -Slack : -4.430 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.571 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.571 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.571 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.571 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 +Slack : -4.420 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.226 -Data Delay : 2.574 +Data Delay : 2.565 -Slack : -4.429 +Slack : -4.420 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.226 -Data Delay : 2.574 +Data Delay : 2.565 -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 +Slack : -4.420 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.226 -Data Delay : 2.574 +Data Delay : 2.565 -Slack : -4.429 +Slack : -4.420 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.221 +Data Delay : 2.570 + +Slack : -4.420 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.221 +Data Delay : 2.570 + +Slack : -4.420 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.221 +Data Delay : 2.570 + +Slack : -4.420 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.221 +Data Delay : 2.570 + +Slack : -4.420 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.221 +Data Delay : 2.570 + +Slack : -4.420 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.562 + +Slack : -4.420 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.562 + +Slack : -4.420 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.562 + +Slack : -4.420 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.562 + +Slack : -4.420 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.562 + +Slack : -4.420 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.562 + +Slack : -4.420 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.562 + +Slack : -4.420 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.229 +Data Delay : 2.562 + +Slack : -4.420 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.565 + +Slack : -4.420 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.571 +Clock Skew : -0.221 +Data Delay : 2.570 -Slack : -4.429 +Slack : -4.420 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.571 +Clock Skew : -0.221 +Data Delay : 2.570 -Slack : -4.429 +Slack : -4.420 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.571 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.228 -Data Delay : 2.572 - -Slack : -4.251 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.044 -Data Delay : 2.578 - -Slack : -4.240 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.041 +Clock Skew : -0.221 Data Delay : 2.570 -Slack : -4.240 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.041 -Data Delay : 2.570 - -Slack : -4.239 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.040 -Data Delay : 2.570 - -Slack : -4.239 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.040 -Data Delay : 2.570 - -Slack : -4.239 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.040 -Data Delay : 2.570 - -Slack : -4.239 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.040 -Data Delay : 2.570 - -Slack : -4.239 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.040 -Data Delay : 2.570 - -Slack : -4.239 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.040 -Data Delay : 2.570 - -Slack : -4.239 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.040 -Data Delay : 2.570 - -Slack : -4.239 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.040 -Data Delay : 2.570 - -Slack : -4.239 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.039 -Data Delay : 2.571 - -Slack : -4.238 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.037 -Data Delay : 2.572 - -Slack : -4.236 +Slack : -4.417 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.215 +Data Delay : 2.573 -Slack : -4.236 +Slack : -4.417 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.215 +Data Delay : 2.573 -Slack : -4.236 +Slack : -4.417 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.215 +Data Delay : 2.573 -Slack : -4.236 +Slack : -4.417 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.215 +Data Delay : 2.573 -Slack : -4.236 +Slack : -4.417 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.215 +Data Delay : 2.573 -Slack : -4.236 +Slack : -4.417 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.215 +Data Delay : 2.573 -Slack : -4.236 +Slack : -4.417 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.215 +Data Delay : 2.573 -Slack : -4.236 +Slack : -4.417 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.215 +Data Delay : 2.573 -Slack : -4.236 +Slack : -4.417 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.215 +Data Delay : 2.573 -Slack : -4.236 +Slack : -4.417 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.215 +Data Delay : 2.573 -Slack : -4.236 +Slack : -4.417 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.215 +Data Delay : 2.573 -Slack : -4.236 +Slack : -4.417 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.215 +Data Delay : 2.573 -Slack : -4.236 +Slack : -4.417 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.215 +Data Delay : 2.573 -Slack : -4.236 +Slack : -4.417 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.215 +Data Delay : 2.573 -Slack : -4.201 +Slack : -4.417 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.215 +Data Delay : 2.573 + +Slack : -4.233 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 2.565 + +Slack : -4.233 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 2.565 + +Slack : -4.233 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 2.565 + +Slack : -4.233 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 2.565 + +Slack : -4.233 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.039 +Data Delay : 2.565 + +Slack : -4.232 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.036 +Data Delay : 2.567 + +Slack : -4.232 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.036 +Data Delay : 2.567 + +Slack : -4.232 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.036 +Data Delay : 2.567 + +Slack : -4.231 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.035 +Data Delay : 2.567 + +Slack : -4.231 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.035 +Data Delay : 2.567 + +Slack : -4.231 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.035 +Data Delay : 2.567 + +Slack : -4.231 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.035 +Data Delay : 2.567 + +Slack : -4.231 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.036 +Data Delay : 2.566 + +Slack : -4.231 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.034 +Data Delay : 2.568 + +Slack : -4.231 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.029 +Data Delay : 2.573 + +Slack : -4.227 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.029 +Data Delay : 2.569 + +Slack : -4.221 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.025 +Data Delay : 2.567 + +Slack : -4.221 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.025 +Data Delay : 2.567 + +Slack : -4.220 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.026 +Data Delay : 2.565 + +Slack : -4.220 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.026 +Data Delay : 2.565 + +Slack : -4.193 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.571 +Data Delay : 2.563 -Slack : -4.201 +Slack : -4.193 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.571 +Data Delay : 2.563 -Slack : -4.201 +Slack : -4.193 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.571 +Data Delay : 2.563 -Slack : -4.201 +Slack : -4.193 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.571 +Data Delay : 2.563 -Slack : -4.201 +Slack : -4.193 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.571 +Data Delay : 2.563 -Slack : -4.201 +Slack : -4.193 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.571 +Data Delay : 2.563 +--------------------------------------------------------------------------------+ @@ -27477,743 +36888,1549 @@ Data Delay : 2.571 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 2.518 +Slack : 2.507 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.256 -Data Delay : 1.945 +Clock Skew : 0.257 +Data Delay : 1.935 -Slack : 2.518 +Slack : 2.507 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.256 -Data Delay : 1.945 +Clock Skew : 0.257 +Data Delay : 1.935 -Slack : 2.518 +Slack : 2.507 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.256 -Data Delay : 1.945 +Clock Skew : 0.257 +Data Delay : 1.935 -Slack : 2.518 +Slack : 2.507 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.256 -Data Delay : 1.945 +Clock Skew : 0.257 +Data Delay : 1.935 -Slack : 2.518 +Slack : 2.507 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.256 -Data Delay : 1.945 +Clock Skew : 0.257 +Data Delay : 1.935 -Slack : 2.518 +Slack : 2.507 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.256 -Data Delay : 1.945 +Clock Skew : 0.257 +Data Delay : 1.935 -Slack : 2.559 +Slack : 2.541 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 +Clock Skew : 0.228 +Data Delay : 1.937 -Slack : 2.559 +Slack : 2.541 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 +Clock Skew : 0.228 +Data Delay : 1.937 -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.562 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.215 -Data Delay : 1.945 - -Slack : 2.563 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.212 -Data Delay : 1.943 - -Slack : 2.563 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.212 -Data Delay : 1.943 - -Slack : 2.564 +Slack : 2.542 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.212 -Data Delay : 1.944 +Clock Skew : 0.229 +Data Delay : 1.939 -Slack : 2.564 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.212 -Data Delay : 1.944 - -Slack : 2.564 +Slack : 2.542 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.212 -Data Delay : 1.944 +Clock Skew : 0.229 +Data Delay : 1.939 -Slack : 2.564 +Slack : 2.548 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.212 -Data Delay : 1.944 +Clock Skew : 0.224 +Data Delay : 1.940 -Slack : 2.564 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.212 -Data Delay : 1.944 - -Slack : 2.564 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.212 -Data Delay : 1.944 - -Slack : 2.564 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.212 -Data Delay : 1.944 - -Slack : 2.564 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.212 -Data Delay : 1.944 - -Slack : 2.565 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.213 -Data Delay : 1.946 - -Slack : 2.574 +Slack : 2.551 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.209 -Data Delay : 1.951 +Clock Skew : 0.224 +Data Delay : 1.943 -Slack : 2.761 +Slack : 2.552 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.219 +Data Delay : 1.939 + +Slack : 2.553 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.217 +Data Delay : 1.938 + +Slack : 2.553 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.217 +Data Delay : 1.938 + +Slack : 2.553 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.217 +Data Delay : 1.938 + +Slack : 2.553 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.217 +Data Delay : 1.938 + +Slack : 2.553 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.217 +Data Delay : 1.938 + +Slack : 2.553 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.217 +Data Delay : 1.938 + +Slack : 2.553 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.217 +Data Delay : 1.938 + +Slack : 2.554 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.216 +Data Delay : 1.938 + +Slack : 2.556 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.213 +Data Delay : 1.937 + +Slack : 2.556 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.213 +Data Delay : 1.937 + +Slack : 2.556 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.213 +Data Delay : 1.937 + +Slack : 2.556 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.213 +Data Delay : 1.937 + +Slack : 2.556 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.213 +Data Delay : 1.937 + +Slack : 2.745 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.030 +Data Delay : 1.943 + +Slack : 2.745 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.030 +Data Delay : 1.943 + +Slack : 2.745 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.030 +Data Delay : 1.943 + +Slack : 2.745 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.030 +Data Delay : 1.943 + +Slack : 2.745 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.030 +Data Delay : 1.943 + +Slack : 2.745 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.030 +Data Delay : 1.943 + +Slack : 2.745 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.030 +Data Delay : 1.943 + +Slack : 2.745 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.030 +Data Delay : 1.943 + +Slack : 2.745 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.030 +Data Delay : 1.943 + +Slack : 2.745 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.030 +Data Delay : 1.943 + +Slack : 2.745 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.030 +Data Delay : 1.943 + +Slack : 2.745 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.030 +Data Delay : 1.943 + +Slack : 2.745 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.030 +Data Delay : 1.943 + +Slack : 2.745 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.030 +Data Delay : 1.943 + +Slack : 2.745 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.030 +Data Delay : 1.943 + +Slack : 2.750 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.945 +Clock Skew : 0.024 +Data Delay : 1.942 -Slack : 2.761 +Slack : 2.750 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.945 +Clock Skew : 0.024 +Data Delay : 1.942 -Slack : 2.761 +Slack : 2.750 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.945 +Clock Skew : 0.024 +Data Delay : 1.942 -Slack : 2.761 +Slack : 2.750 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.945 +Clock Skew : 0.024 +Data Delay : 1.942 -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.945 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.015 -Data Delay : 1.944 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.945 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.015 -Data Delay : 1.944 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.945 - -Slack : 2.761 +Slack : 2.750 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.945 +Clock Skew : 0.024 +Data Delay : 1.942 -Slack : 2.761 +Slack : 2.750 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.945 +Clock Skew : 0.024 +Data Delay : 1.942 -Slack : 2.761 +Slack : 2.750 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 +Clock Skew : 0.021 +Data Delay : 1.939 -Slack : 2.761 +Slack : 2.750 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 +Clock Skew : 0.021 +Data Delay : 1.939 -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 - -Slack : 2.761 +Slack : 2.751 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.018 -Data Delay : 1.947 +Data Delay : 1.937 -Slack : 2.761 +Slack : 2.751 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.018 -Data Delay : 1.947 +Data Delay : 1.937 -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 - -Slack : 2.761 +Slack : 2.751 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.018 -Data Delay : 1.947 +Data Delay : 1.937 -Slack : 2.761 +Slack : 2.751 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.015 -Data Delay : 1.944 +Clock Skew : 0.023 +Data Delay : 1.942 -Slack : 2.761 +Slack : 2.751 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.015 -Data Delay : 1.944 +Clock Skew : 0.023 +Data Delay : 1.942 -Slack : 2.761 +Slack : 2.751 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.015 -Data Delay : 1.944 +Clock Skew : 0.023 +Data Delay : 1.942 -Slack : 2.761 +Slack : 2.751 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.942 + +Slack : 2.751 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.942 + +Slack : 2.751 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.016 -Data Delay : 1.945 +Data Delay : 1.935 -Slack : 2.762 +Slack : 2.751 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.016 -Data Delay : 1.946 +Data Delay : 1.935 -Slack : 2.762 +Slack : 2.751 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.016 -Data Delay : 1.946 +Data Delay : 1.935 -Slack : 2.762 +Slack : 2.751 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.016 -Data Delay : 1.946 +Data Delay : 1.935 -Slack : 2.762 +Slack : 2.751 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.016 -Data Delay : 1.946 +Data Delay : 1.935 -Slack : 2.762 +Slack : 2.751 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.016 -Data Delay : 1.946 +Data Delay : 1.935 -Slack : 2.762 +Slack : 2.751 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.937 + +Slack : 2.751 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.942 + +Slack : 2.751 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.942 + +Slack : 2.751 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.942 + +Slack : 2.752 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.015 +Data Delay : 1.935 + +Slack : 2.752 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.015 +Data Delay : 1.935 + +Slack : 2.752 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.015 +Data Delay : 1.935 + +Slack : 2.752 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.015 +Data Delay : 1.935 + +Slack : 2.752 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.015 +Data Delay : 1.935 + +Slack : 2.752 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.946 +Clock Skew : 0.015 +Data Delay : 1.935 -Slack : 2.763 +Slack : 2.752 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.015 -Data Delay : 1.946 +Data Delay : 1.935 -Slack : 2.763 +Slack : 2.752 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.015 -Data Delay : 1.946 +Data Delay : 1.935 -Slack : 2.897 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : -0.019 -Data Delay : 2.020 - -Slack : 2.902 +Slack : 2.884 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : -0.016 -Data Delay : 2.028 +Data Delay : 2.010 -Slack : 3.008 +Slack : 2.886 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : -0.019 +Data Delay : 2.009 + +Slack : 2.997 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.009 -Data Delay : 2.157 +Data Delay : 2.146 -Slack : 3.008 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.007 -Data Delay : 2.155 - -Slack : 3.008 +Slack : 2.997 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.007 -Data Delay : 2.155 +Data Delay : 2.144 -Slack : 3.008 +Slack : 2.998 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.004 -Data Delay : 2.152 +Clock Skew : 0.007 +Data Delay : 2.145 -Slack : 3.009 +Slack : 2.998 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.005 -Data Delay : 2.154 +Data Delay : 2.143 + +Slack : 2.998 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.004 +Data Delay : 2.142 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width: 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' ; ++--------------------------------------------------------------------------------+ +Slack : 4.783 +Actual Width : 4.999 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[3] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[10] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[11] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[12] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[13] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[14] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[1] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[2] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[4] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[5] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[6] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[7] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[8] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[9] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rd_pending + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[4] + +Slack : 4.784 +Actual Width : 5.000 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.wr_pending + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[0] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[1] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[2] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[3] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[4] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1 + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[0] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[1] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[2] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[3] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[4] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[5] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[6] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[7] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[8] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[9] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_pending + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[5] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[6] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[7] + +Slack : 4.785 +Actual Width : 5.001 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[8] + +Slack : 4.787 +Actual Width : 5.003 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2 + +Slack : 4.787 +Actual Width : 5.003 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 + +Slack : 4.787 +Actual Width : 5.003 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1 + +Slack : 4.787 +Actual Width : 5.003 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[0] + +Slack : 4.788 +Actual Width : 5.004 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1 + +Slack : 4.788 +Actual Width : 5.004 +Required Width : 0.216 +Type : High Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1 + +Slack : 4.810 +Actual Width : 4.994 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0]~_Duplicate_1 + +Slack : 4.810 +Actual Width : 4.994 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10]~_Duplicate_1 + +Slack : 4.810 +Actual Width : 4.994 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[4]~_Duplicate_1 + +Slack : 4.810 +Actual Width : 4.994 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[5]~_Duplicate_1 + +Slack : 4.810 +Actual Width : 4.994 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[0] + +Slack : 4.811 +Actual Width : 4.995 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_2 + +Slack : 4.812 +Actual Width : 4.996 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[0] + +Slack : 4.812 +Actual Width : 4.996 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[1] + +Slack : 4.812 +Actual Width : 4.996 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[2] + +Slack : 4.812 +Actual Width : 4.996 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[3] + +Slack : 4.812 +Actual Width : 4.996 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[4] + +Slack : 4.812 +Actual Width : 4.996 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[5] + +Slack : 4.812 +Actual Width : 4.996 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[6] + +Slack : 4.812 +Actual Width : 4.996 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[7] + +Slack : 4.812 +Actual Width : 4.996 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[8] + +Slack : 4.812 +Actual Width : 4.996 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_counter[9] + +Slack : 4.812 +Actual Width : 4.996 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rf_pending + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[0] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[1] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[2] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[3] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.act_row[4] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[1]~_Duplicate_1 + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[3] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.rd_pending + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[5] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[6] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[7] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[8] + +Slack : 4.813 +Actual Width : 4.997 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.wr_pending + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[10] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[11] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[12] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[13] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[14] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[1] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[2] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[4] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[5] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[6] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[7] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[8] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.init_counter[9] + +Slack : 4.814 +Actual Width : 4.998 +Required Width : 0.184 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[4] + +Slack : 4.815 +Actual Width : 4.970 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11] + +Slack : 4.815 +Actual Width : 4.970 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[1] + +Slack : 4.815 +Actual Width : 4.970 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[2] + +Slack : 4.817 +Actual Width : 4.972 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[0] + +Slack : 4.817 +Actual Width : 4.972 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[10] + +Slack : 4.817 +Actual Width : 4.972 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[11]~_Duplicate_1 + +Slack : 4.817 +Actual Width : 4.972 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[9] + +Slack : 4.817 +Actual Width : 4.972 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.state[0] + +Slack : 4.818 +Actual Width : 4.973 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[3] + +Slack : 4.818 +Actual Width : 4.973 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[6] + +Slack : 4.818 +Actual Width : 4.973 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.address[8] + +Slack : 4.818 +Actual Width : 4.973 +Required Width : 0.155 +Type : Low Pulse Width +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : sdram_controller:sdram_|r.bank[0] +--------------------------------------------------------------------------------+ @@ -28221,22 +38438,6 @@ Data Delay : 2.154 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : 9.208 -Actual Width : 9.438 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0 - -Slack : 9.208 -Actual Width : 9.438 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg - Slack : 9.208 Actual Width : 9.438 Required Width : 0.230 @@ -28259,7 +38460,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0 Slack : 9.208 Actual Width : 9.438 @@ -28267,7 +38468,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg Slack : 9.208 Actual Width : 9.438 @@ -28275,7 +38476,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0 Slack : 9.208 Actual Width : 9.438 @@ -28283,7 +38484,23 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg + +Slack : 9.208 +Actual Width : 9.438 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 9.208 +Actual Width : 9.438 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg Slack : 9.208 Actual Width : 9.438 @@ -28301,6 +38518,22 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg +Slack : 9.208 +Actual Width : 9.438 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 + +Slack : 9.208 +Actual Width : 9.438 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 + Slack : 9.209 Actual Width : 9.439 Required Width : 0.230 @@ -28333,22 +38566,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0 - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg - Slack : 9.209 Actual Width : 9.439 Required Width : 0.230 @@ -28365,6 +38582,22 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg + Slack : 9.209 Actual Width : 9.439 Required Width : 0.230 @@ -28381,22 +38614,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0 - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg - Slack : 9.209 Actual Width : 9.439 Required Width : 0.230 @@ -28429,22 +38646,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0 - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg - Slack : 9.209 Actual Width : 9.439 Required Width : 0.230 @@ -28467,7 +38668,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0 Slack : 9.209 Actual Width : 9.439 @@ -28475,7 +38676,23 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 Slack : 9.209 Actual Width : 9.439 @@ -28509,14 +38726,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 - Slack : 9.209 Actual Width : 9.439 Required Width : 0.230 @@ -28525,6 +38734,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 + Slack : 9.209 Actual Width : 9.439 Required Width : 0.230 @@ -28533,6 +38750,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 + Slack : 9.209 Actual Width : 9.439 Required Width : 0.230 @@ -28571,7 +38796,31 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0 + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg Slack : 9.210 Actual Width : 9.440 @@ -28587,7 +38836,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 Slack : 9.210 Actual Width : 9.440 @@ -28595,7 +38844,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 Slack : 9.210 Actual Width : 9.440 @@ -28603,15 +38852,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 Slack : 9.210 Actual Width : 9.440 @@ -28627,31 +38868,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 Slack : 9.210 Actual Width : 9.440 @@ -28685,6 +38902,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +Slack : 9.210 +Actual Width : 9.440 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 + Slack : 9.210 Actual Width : 9.440 Required Width : 0.230 @@ -28699,7 +38924,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 Slack : 9.210 Actual Width : 9.440 @@ -28715,7 +38940,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 Slack : 9.210 Actual Width : 9.440 @@ -28771,7 +38996,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 + +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 Slack : 9.211 Actual Width : 9.441 @@ -28787,15 +39020,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 - -Slack : 9.211 -Actual Width : 9.441 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 Slack : 9.211 Actual Width : 9.441 @@ -28805,14 +39030,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Slack : 9.211 -Actual Width : 9.441 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 - Slack : 9.211 Actual Width : 9.441 Required Width : 0.230 @@ -28829,14 +39046,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Slack : 9.211 -Actual Width : 9.441 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 - Slack : 9.211 Actual Width : 9.441 Required Width : 0.230 @@ -28851,7 +39060,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 Slack : 9.211 Actual Width : 9.441 @@ -28859,7 +39068,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 Slack : 9.211 Actual Width : 9.441 @@ -28867,7 +39076,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 Slack : 9.212 Actual Width : 9.442 @@ -28875,7 +39084,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 Slack : 9.212 Actual Width : 9.442 @@ -28883,7 +39092,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 Slack : 9.212 Actual Width : 9.442 @@ -28891,7 +39100,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 Slack : 9.212 Actual Width : 9.442 @@ -28915,7 +39124,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 Slack : 9.212 Actual Width : 9.442 @@ -28923,7 +39132,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 Slack : 9.212 Actual Width : 9.442 @@ -28979,7 +39196,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 Slack : 9.212 Actual Width : 9.442 @@ -28987,7 +39204,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0 Slack : 9.212 Actual Width : 9.442 @@ -28995,7 +39212,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~PORTBDATAOUT0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 Slack : 9.212 Actual Width : 9.442 @@ -29003,7 +39220,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 Slack : 9.212 Actual Width : 9.442 @@ -29011,15 +39228,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Slack : 9.212 -Actual Width : 9.442 +Slack : 9.213 +Actual Width : 9.443 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +--------------------------------------------------------------------------------+ @@ -29027,38 +39244,6 @@ Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : 19.609 -Actual Width : 19.839 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0 - -Slack : 19.609 -Actual Width : 19.839 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg - -Slack : 19.609 -Actual Width : 19.839 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0 - -Slack : 19.609 -Actual Width : 19.839 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg - Slack : 19.609 Actual Width : 19.839 Required Width : 0.230 @@ -29075,6 +39260,38 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0 + +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg + +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0 + +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg + Slack : 19.609 Actual Width : 19.839 Required Width : 0.230 @@ -29113,7 +39330,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0 Slack : 19.609 Actual Width : 19.839 @@ -29121,7 +39338,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg Slack : 19.609 Actual Width : 19.839 @@ -29129,7 +39346,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0 Slack : 19.609 Actual Width : 19.839 @@ -29137,23 +39354,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg - -Slack : 19.609 -Actual Width : 19.839 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0 - -Slack : 19.609 -Actual Width : 19.839 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_we_reg Slack : 19.610 Actual Width : 19.840 @@ -29209,7 +39410,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0 Slack : 19.610 Actual Width : 19.840 @@ -29217,7 +39418,23 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg Slack : 19.610 Actual Width : 19.840 @@ -29243,6 +39460,14 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_we_reg +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 + Slack : 19.610 Actual Width : 19.840 Required Width : 0.230 @@ -29275,22 +39500,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg -Slack : 19.610 -Actual Width : 19.840 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0 - -Slack : 19.610 -Actual Width : 19.840 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg - Slack : 19.610 Actual Width : 19.840 Required Width : 0.230 @@ -29313,7 +39522,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 Slack : 19.610 Actual Width : 19.840 @@ -29321,7 +39530,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 Slack : 19.610 Actual Width : 19.840 @@ -29345,7 +39554,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_we_reg Slack : 19.610 Actual Width : 19.840 @@ -29369,7 +39586,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg Slack : 19.610 Actual Width : 19.840 @@ -29387,22 +39612,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg -Slack : 19.610 -Actual Width : 19.840 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0 - -Slack : 19.610 -Actual Width : 19.840 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg - Slack : 19.610 Actual Width : 19.840 Required Width : 0.230 @@ -29419,22 +39628,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_we_reg -Slack : 19.610 -Actual Width : 19.840 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0 - -Slack : 19.610 -Actual Width : 19.840 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg - Slack : 19.610 Actual Width : 19.840 Required Width : 0.230 @@ -29473,7 +39666,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0 Slack : 19.610 Actual Width : 19.840 @@ -29481,7 +39674,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg Slack : 19.610 Actual Width : 19.840 @@ -29489,7 +39682,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg Slack : 19.610 Actual Width : 19.840 @@ -29529,7 +39730,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0 Slack : 19.610 Actual Width : 19.840 @@ -29537,7 +39738,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 Slack : 19.611 Actual Width : 19.841 @@ -29577,7 +39786,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 Slack : 19.611 Actual Width : 19.841 @@ -29585,7 +39794,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 Slack : 19.611 Actual Width : 19.841 @@ -29609,15 +39818,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0 - -Slack : 19.611 -Actual Width : 19.841 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 Slack : 19.611 Actual Width : 19.841 @@ -29641,7 +39842,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0 Slack : 19.611 Actual Width : 19.841 @@ -29649,7 +39850,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg Slack : 19.611 Actual Width : 19.841 @@ -29657,7 +39858,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 Slack : 19.611 Actual Width : 19.841 @@ -29681,7 +39882,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 Slack : 19.611 Actual Width : 19.841 @@ -29697,7 +39898,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 Slack : 19.611 Actual Width : 19.841 @@ -29705,7 +39906,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 Slack : 19.611 Actual Width : 19.841 @@ -29713,7 +39914,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg Slack : 19.611 Actual Width : 19.841 @@ -29729,7 +39930,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg Slack : 19.611 Actual Width : 19.841 @@ -29745,7 +39954,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 Slack : 19.611 Actual Width : 19.841 @@ -29769,7 +39978,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0 Slack : 19.611 Actual Width : 19.841 @@ -29777,7 +39986,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg Slack : 19.611 Actual Width : 19.841 @@ -29785,7 +39994,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 Slack : 19.611 Actual Width : 19.841 @@ -29809,7 +40026,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 Slack : 19.611 Actual Width : 19.841 @@ -29817,15 +40034,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 -Slack : 19.611 -Actual Width : 19.841 +Slack : 19.612 +Actual Width : 19.842 Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +--------------------------------------------------------------------------------+ @@ -29881,6 +40098,22 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Fall Target : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2] + Slack : 20.633 Actual Width : 20.849 Required Width : 0.216 @@ -29897,22 +40130,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|phase[0] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|phase[1] - Slack : 20.633 Actual Width : 20.849 Required Width : 0.216 @@ -29929,110 +40146,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] - Slack : 20.633 Actual Width : 20.849 Required Width : 0.216 @@ -30145,13 +40258,13 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Slack : 20.633 -Actual Width : 20.849 +Slack : 20.634 +Actual Width : 20.850 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Target : ula:ula_|i2c_loader:i2c_loader_|phase[0] Slack : 20.634 Actual Width : 20.850 @@ -30159,7 +40272,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Target : ula:ula_|i2c_loader:i2c_loader_|phase[1] Slack : 20.634 Actual Width : 20.850 @@ -30167,7 +40280,39 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] + +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] + +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] + +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] + +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Slack : 20.634 Actual Width : 20.850 @@ -30183,7 +40328,15 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] + +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Slack : 20.634 Actual Width : 20.850 @@ -30193,6 +40346,14 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|state.Data +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle + Slack : 20.634 Actual Width : 20.850 Required Width : 0.216 @@ -30209,13 +40370,125 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|state.Start -Slack : 20.634 -Actual Width : 20.850 +Slack : 20.636 +Actual Width : 20.852 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] + +Slack : 20.636 +Actual Width : 20.852 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] Slack : 20.639 Actual Width : 20.823 @@ -30223,287 +40496,215 @@ Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] -Slack : 20.641 -Actual Width : 20.825 +Slack : 20.639 +Actual Width : 20.823 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 + +Slack : 20.640 +Actual Width : 20.824 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack + +Slack : 20.640 +Actual Width : 20.824 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop + +Slack : 20.640 +Actual Width : 20.824 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] + +Slack : 20.642 +Actual Width : 20.826 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] + +Slack : 20.643 +Actual Width : 20.827 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] - -Slack : 20.643 -Actual Width : 20.827 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] - -Slack : 20.643 -Actual Width : 20.827 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] - -Slack : 20.643 -Actual Width : 20.827 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] - -Slack : 20.643 -Actual Width : 20.827 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] - -Slack : 20.643 -Actual Width : 20.827 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] - -Slack : 20.643 -Actual Width : 20.827 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] - -Slack : 20.643 -Actual Width : 20.827 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] - -Slack : 20.643 -Actual Width : 20.827 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] - -Slack : 20.643 -Actual Width : 20.827 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] - -Slack : 20.643 -Actual Width : 20.827 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 - -Slack : 20.649 -Actual Width : 20.865 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] - -Slack : 20.651 -Actual Width : 20.835 +Slack : 20.645 +Actual Width : 20.829 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Slack : 20.656 -Actual Width : 20.872 -Required Width : 0.216 -Type : High Pulse Width +Slack : 20.647 +Actual Width : 20.831 +Required Width : 0.184 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Slack : 20.656 -Actual Width : 20.872 -Required Width : 0.216 -Type : High Pulse Width +Slack : 20.647 +Actual Width : 20.831 +Required Width : 0.184 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Slack : 20.656 -Actual Width : 20.872 -Required Width : 0.216 -Type : High Pulse Width +Slack : 20.647 +Actual Width : 20.831 +Required Width : 0.184 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Slack : 20.656 -Actual Width : 20.872 -Required Width : 0.216 -Type : High Pulse Width +Slack : 20.647 +Actual Width : 20.831 +Required Width : 0.184 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Slack : 20.656 -Actual Width : 20.872 -Required Width : 0.216 -Type : High Pulse Width +Slack : 20.647 +Actual Width : 20.831 +Required Width : 0.184 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Slack : 20.656 -Actual Width : 20.872 +Slack : 20.652 +Actual Width : 20.868 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Slack : 20.656 -Actual Width : 20.872 +Slack : 20.652 +Actual Width : 20.868 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Slack : 20.656 -Actual Width : 20.872 +Slack : 20.652 +Actual Width : 20.868 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] + +Slack : 20.652 +Actual Width : 20.868 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] + +Slack : 20.652 +Actual Width : 20.868 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] + +Slack : 20.655 +Actual Width : 20.871 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] + +Slack : 20.657 +Actual Width : 20.873 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Slack : 20.657 Actual Width : 20.873 @@ -30513,6 +40714,22 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Slack : 20.657 +Actual Width : 20.873 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] + +Slack : 20.657 +Actual Width : 20.873 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] + Slack : 20.657 Actual Width : 20.873 Required Width : 0.216 @@ -30521,117 +40738,117 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Slack : 20.657 +Actual Width : 20.873 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] + Slack : 20.658 Actual Width : 20.874 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -Slack : 20.659 -Actual Width : 20.875 +Slack : 20.658 +Actual Width : 20.874 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] + +Slack : 20.658 +Actual Width : 20.874 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] + +Slack : 20.660 +Actual Width : 20.876 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] + +Slack : 20.661 +Actual Width : 20.877 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack + +Slack : 20.661 +Actual Width : 20.877 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop + +Slack : 20.661 +Actual Width : 20.877 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] + +Slack : 20.661 +Actual Width : 20.877 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 + +Slack : 20.664 +Actual Width : 20.848 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width +Slack : 20.664 +Actual Width : 20.848 +Required Width : 0.184 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width +Slack : 20.664 +Actual Width : 20.848 +Required Width : 0.184 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width +Slack : 20.664 +Actual Width : 20.848 +Required Width : 0.184 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width +Slack : 20.664 +Actual Width : 20.848 +Required Width : 0.184 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] - -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] - -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] - -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] - -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] - -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] - -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] - -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] - -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +--------------------------------------------------------------------------------+ @@ -30759,43 +40976,43 @@ Target : ula:ula_|clocks:clocks_|counter[0] +--------------------------------------------------------------------------------+ Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : 1.079 -Fall : 1.946 +Rise : 0.815 +Fall : 1.610 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : 2.221 -Fall : 3.039 +Rise : 2.160 +Fall : 2.981 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : SW[*] Clock Port : CLOCK_50 -Rise : 0.623 +Rise : 0.624 Fall : 1.147 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : SW[2] Clock Port : CLOCK_50 -Rise : 0.623 +Rise : 0.624 Fall : 1.147 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : 0.728 -Fall : 1.321 +Rise : 0.702 +Fall : 1.291 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : 1.575 -Fall : 2.139 +Rise : 1.571 +Fall : 2.134 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -30807,43 +41024,43 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : -0.841 -Fall : -1.690 +Rise : -0.561 +Fall : -1.355 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : -1.690 -Fall : -2.493 +Rise : -1.405 +Fall : -2.156 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : SW[*] Clock Port : CLOCK_50 Rise : -0.259 -Fall : -0.787 +Fall : -0.788 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : SW[2] Clock Port : CLOCK_50 Rise : -0.259 -Fall : -0.787 +Fall : -0.788 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : -0.368 -Fall : -0.952 +Rise : -0.342 +Fall : -0.923 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : -0.742 -Fall : -1.295 +Rise : -0.737 +Fall : -1.290 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -30853,199 +41070,619 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ ; Clock to Output Times ; +--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 6.253 +Fall : 6.386 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 5.922 +Fall : 6.005 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 5.981 +Fall : 6.082 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 5.884 +Fall : 5.994 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 5.749 +Fall : 6.050 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 6.022 +Fall : 6.135 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 6.138 +Fall : 6.337 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 6.253 +Fall : 6.386 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 5.955 +Fall : 6.115 +Clock Edge : Rise +Clock Reference : CLOCK_50 + Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 6.008 -Fall : 6.095 +Rise : 6.140 +Fall : 6.286 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 6.008 -Fall : 6.095 +Rise : 5.857 +Fall : 5.936 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 5.342 -Fall : 5.537 +Rise : 5.902 +Fall : 5.999 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 5.828 -Fall : 5.903 +Rise : 5.854 +Fall : 5.950 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 5.590 -Fall : 5.692 +Rise : 5.617 +Fall : 5.863 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 5.726 -Fall : 5.854 +Rise : 5.936 +Fall : 6.062 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 5.482 -Fall : 5.521 +Rise : 5.889 +Fall : 6.045 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 5.820 -Fall : 5.903 +Rise : 6.140 +Fall : 6.286 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 5.363 -Fall : 5.393 +Rise : 5.639 +Fall : 5.759 Clock Edge : Rise Clock Reference : CLOCK_50 +Data Port : DRAM_ADDR[*] +Clock Port : CLOCK_50 +Rise : 2.061 +Fall : 1.989 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[0] +Clock Port : CLOCK_50 +Rise : 2.060 +Fall : 1.988 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[1] +Clock Port : CLOCK_50 +Rise : 2.000 +Fall : 1.945 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[2] +Clock Port : CLOCK_50 +Rise : 2.000 +Fall : 1.945 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[3] +Clock Port : CLOCK_50 +Rise : 1.999 +Fall : 1.944 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[4] +Clock Port : CLOCK_50 +Rise : 2.001 +Fall : 1.946 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[5] +Clock Port : CLOCK_50 +Rise : 1.999 +Fall : 1.944 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[6] +Clock Port : CLOCK_50 +Rise : 1.999 +Fall : 1.944 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[7] +Clock Port : CLOCK_50 +Rise : 1.997 +Fall : 1.942 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[8] +Clock Port : CLOCK_50 +Rise : 1.979 +Fall : 1.928 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[9] +Clock Port : CLOCK_50 +Rise : 2.060 +Fall : 1.988 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[10] +Clock Port : CLOCK_50 +Rise : 2.052 +Fall : 1.980 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[11] +Clock Port : CLOCK_50 +Rise : 2.061 +Fall : 1.989 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[12] +Clock Port : CLOCK_50 +Rise : 1.977 +Fall : 1.926 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[*] +Clock Port : CLOCK_50 +Rise : 1.999 +Fall : 1.944 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[0] +Clock Port : CLOCK_50 +Rise : 1.998 +Fall : 1.943 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[1] +Clock Port : CLOCK_50 +Rise : 1.999 +Fall : 1.944 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CAS_N +Clock Port : CLOCK_50 +Rise : 2.059 +Fall : 1.987 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 3.748 +Fall : 3.683 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 3.219 +Fall : 3.327 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 3.352 +Fall : 3.462 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 3.199 +Fall : 3.311 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 3.049 +Fall : 3.160 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 3.251 +Fall : 3.356 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 3.329 +Fall : 3.459 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 3.243 +Fall : 3.342 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 3.337 +Fall : 3.469 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[8] +Clock Port : CLOCK_50 +Rise : 3.748 +Fall : 3.683 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[9] +Clock Port : CLOCK_50 +Rise : 3.617 +Fall : 3.572 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[10] +Clock Port : CLOCK_50 +Rise : 3.607 +Fall : 3.563 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[11] +Clock Port : CLOCK_50 +Rise : 3.607 +Fall : 3.563 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[12] +Clock Port : CLOCK_50 +Rise : 3.738 +Fall : 3.680 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[13] +Clock Port : CLOCK_50 +Rise : 3.739 +Fall : 3.675 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[14] +Clock Port : CLOCK_50 +Rise : 3.739 +Fall : 3.675 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[15] +Clock Port : CLOCK_50 +Rise : 3.495 +Fall : 3.473 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[*] +Clock Port : CLOCK_50 +Rise : 1.997 +Fall : 1.942 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[0] +Clock Port : CLOCK_50 +Rise : 1.997 +Fall : 1.942 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[1] +Clock Port : CLOCK_50 +Rise : 1.997 +Fall : 1.942 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_RAS_N +Clock Port : CLOCK_50 +Rise : 2.059 +Fall : 1.987 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_WE_N +Clock Port : CLOCK_50 +Rise : 2.057 +Fall : 1.985 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : 3.958 +Fall : +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : +Fall : 3.905 +Clock Edge : Fall +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 4.941 +Fall : 5.043 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 4.372 +Fall : 4.489 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 4.445 +Fall : 4.546 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 4.681 +Fall : 4.807 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 4.459 +Fall : 4.699 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 4.870 +Fall : 4.993 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 4.675 +Fall : 4.823 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 4.941 +Fall : 5.043 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 4.571 +Fall : 4.718 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 4.649 -Fall : 4.764 +Rise : 4.828 +Fall : 4.943 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 4.449 +Rise : 4.307 +Fall : 4.420 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 4.366 +Fall : 4.463 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 4.651 +Fall : 4.763 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 4.327 +Fall : 4.512 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 4.784 +Fall : 4.920 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 4.430 Fall : 4.536 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Data Port : GPIO_1[17] -Clock Port : CLOCK_50 -Rise : 4.487 -Fall : 4.591 -Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] - -Data Port : GPIO_1[18] -Clock Port : CLOCK_50 -Rise : 4.253 -Fall : 4.359 -Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] - -Data Port : GPIO_1[19] -Clock Port : CLOCK_50 -Rise : 4.439 -Fall : 4.548 -Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] - -Data Port : GPIO_1[20] -Clock Port : CLOCK_50 -Rise : 4.649 -Fall : 4.764 -Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] - -Data Port : GPIO_1[21] -Clock Port : CLOCK_50 -Rise : 4.334 -Fall : 4.411 -Clock Edge : Rise -Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] - Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 4.547 -Fall : 4.697 +Rise : 4.828 +Fall : 4.943 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 4.198 -Fall : 4.263 +Rise : 4.190 +Fall : 4.281 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 5.045 -Fall : 4.866 +Rise : 5.317 +Fall : 5.146 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 5.045 -Fall : 4.866 +Rise : 5.317 +Fall : 5.146 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 3.467 -Fall : 3.470 +Rise : 4.196 +Fall : 4.364 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 3.638 -Fall : 3.715 +Rise : 3.803 +Fall : 3.875 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 3.865 -Fall : 3.962 +Rise : 3.804 +Fall : 3.876 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 3.736 -Fall : 3.757 +Rise : 3.981 +Fall : 4.019 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 3.736 -Fall : 3.757 +Rise : 3.588 +Fall : 3.585 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 3.606 -Fall : 3.673 +Rise : 3.818 +Fall : 3.952 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 3.656 -Fall : 3.658 +Rise : 3.981 +Fall : 4.019 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 3.656 -Fall : 3.658 +Rise : 3.981 +Fall : 4.019 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -31058,36 +41695,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 3.764 -Fall : 3.886 +Rise : 4.161 +Fall : 4.356 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 3.764 -Fall : 3.886 +Rise : 3.960 +Fall : 4.022 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 3.693 -Fall : 3.752 +Rise : 4.161 +Fall : 4.356 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 3.523 -Fall : 3.590 +Rise : 3.817 +Fall : 3.844 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 3.653 -Fall : 3.739 +Rise : 3.782 +Fall : 3.804 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -31153,199 +41790,619 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ ; Minimum Clock to Output Times ; +--------------------------------------------------------------------------------+ -Data Port : GPIO_1[*] +Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 4.404 -Fall : 4.492 +Rise : 4.488 +Fall : 4.607 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[16] +Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 4.714 -Fall : 4.811 +Rise : 4.624 +Fall : 4.719 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[17] +Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 4.756 -Fall : 4.806 +Rise : 4.670 +Fall : 4.779 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[18] +Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 4.404 -Fall : 4.492 +Rise : 4.488 +Fall : 4.607 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[19] +Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 4.619 -Fall : 4.708 +Rise : 4.700 +Fall : 4.843 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[20] +Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 4.805 -Fall : 4.924 +Rise : 4.819 +Fall : 4.940 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[21] +Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 4.528 -Fall : 4.559 +Rise : 4.988 +Fall : 5.131 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[22] +Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 4.418 -Fall : 4.501 +Rise : 4.747 +Fall : 4.889 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[23] +Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 4.478 -Fall : 4.502 +Rise : 4.935 +Fall : 5.065 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 3.074 -Fall : 3.195 +Rise : 4.461 +Fall : 4.568 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 4.562 +Fall : 4.652 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 4.593 +Fall : 4.698 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 4.461 +Fall : 4.568 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 4.577 +Fall : 4.666 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 4.732 +Fall : 4.867 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 4.749 +Fall : 4.851 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 4.636 +Fall : 4.789 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 4.637 +Fall : 4.728 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_ADDR[*] +Clock Port : CLOCK_50 +Rise : 1.724 +Fall : 1.674 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[0] +Clock Port : CLOCK_50 +Rise : 1.807 +Fall : 1.736 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[1] +Clock Port : CLOCK_50 +Rise : 1.747 +Fall : 1.692 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[2] +Clock Port : CLOCK_50 +Rise : 1.747 +Fall : 1.692 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[3] +Clock Port : CLOCK_50 +Rise : 1.746 +Fall : 1.691 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[4] +Clock Port : CLOCK_50 +Rise : 1.748 +Fall : 1.693 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[5] +Clock Port : CLOCK_50 +Rise : 1.746 +Fall : 1.691 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[6] +Clock Port : CLOCK_50 +Rise : 1.746 +Fall : 1.691 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[7] +Clock Port : CLOCK_50 +Rise : 1.744 +Fall : 1.689 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[8] +Clock Port : CLOCK_50 +Rise : 1.726 +Fall : 1.676 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[9] +Clock Port : CLOCK_50 +Rise : 1.807 +Fall : 1.736 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[10] +Clock Port : CLOCK_50 +Rise : 1.800 +Fall : 1.729 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[11] +Clock Port : CLOCK_50 +Rise : 1.808 +Fall : 1.737 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[12] +Clock Port : CLOCK_50 +Rise : 1.724 +Fall : 1.674 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[*] +Clock Port : CLOCK_50 +Rise : 1.745 +Fall : 1.690 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[0] +Clock Port : CLOCK_50 +Rise : 1.745 +Fall : 1.690 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[1] +Clock Port : CLOCK_50 +Rise : 1.746 +Fall : 1.691 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CAS_N +Clock Port : CLOCK_50 +Rise : 1.805 +Fall : 1.734 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 2.705 +Fall : 2.683 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 2.876 +Fall : 2.979 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 3.004 +Fall : 3.108 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 2.854 +Fall : 2.959 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 2.709 +Fall : 2.815 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 2.908 +Fall : 3.006 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 2.981 +Fall : 3.104 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 2.865 +Fall : 2.958 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 2.986 +Fall : 3.112 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[8] +Clock Port : CLOCK_50 +Rise : 2.944 +Fall : 2.881 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[9] +Clock Port : CLOCK_50 +Rise : 2.819 +Fall : 2.774 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[10] +Clock Port : CLOCK_50 +Rise : 2.809 +Fall : 2.765 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[11] +Clock Port : CLOCK_50 +Rise : 2.809 +Fall : 2.765 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[12] +Clock Port : CLOCK_50 +Rise : 2.935 +Fall : 2.878 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[13] +Clock Port : CLOCK_50 +Rise : 2.936 +Fall : 2.874 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[14] +Clock Port : CLOCK_50 +Rise : 2.936 +Fall : 2.874 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[15] +Clock Port : CLOCK_50 +Rise : 2.705 +Fall : 2.683 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[*] +Clock Port : CLOCK_50 +Rise : 1.744 +Fall : 1.689 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[0] +Clock Port : CLOCK_50 +Rise : 1.744 +Fall : 1.689 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[1] +Clock Port : CLOCK_50 +Rise : 1.744 +Fall : 1.689 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_RAS_N +Clock Port : CLOCK_50 +Rise : 1.805 +Fall : 1.734 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_WE_N +Clock Port : CLOCK_50 +Rise : 1.804 +Fall : 1.733 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : 3.708 +Fall : +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : +Fall : 3.654 +Clock Edge : Fall +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 3.484 +Fall : 3.630 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 3.729 +Fall : 3.823 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 3.734 +Fall : 3.824 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 3.908 +Fall : 4.032 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 3.717 +Fall : 3.979 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 3.578 +Fall : 3.745 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 3.905 +Fall : 4.039 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 3.484 +Fall : 3.630 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 3.918 +Fall : 4.056 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 3.373 +Fall : 3.530 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 3.656 -Fall : 3.753 +Rise : 3.667 +Fall : 3.756 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 3.705 -Fall : 3.857 +Rise : 3.657 +Fall : 3.743 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 3.537 -Fall : 3.607 +Rise : 3.881 +Fall : 3.993 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 3.562 -Fall : 3.684 +Rise : 3.594 +Fall : 3.802 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 3.074 -Fall : 3.195 +Rise : 3.491 +Fall : 3.672 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 3.587 -Fall : 3.750 +Rise : 3.669 +Fall : 3.764 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 3.787 -Fall : 3.888 +Rise : 3.373 +Fall : 3.530 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 3.402 -Fall : 3.449 +Rise : 3.578 +Fall : 3.660 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 2.246 -Fall : 2.250 +Rise : 2.537 +Fall : 2.596 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 3.784 -Fall : 3.550 +Rise : 4.052 +Fall : 3.869 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 2.246 -Fall : 2.250 +Rise : 2.650 +Fall : 2.713 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 2.373 -Fall : 2.393 +Rise : 2.537 +Fall : 2.596 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 2.590 -Fall : 2.631 +Rise : 2.538 +Fall : 2.597 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 2.286 -Fall : 2.308 +Rise : 2.171 +Fall : 2.177 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 2.504 -Fall : 2.535 +Rise : 2.181 +Fall : 2.190 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 2.286 -Fall : 2.308 +Rise : 2.171 +Fall : 2.177 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 2.428 -Fall : 2.440 +Rise : 2.558 +Fall : 2.607 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 2.428 -Fall : 2.440 +Rise : 2.558 +Fall : 2.607 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -31358,36 +42415,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 2.190 -Fall : 2.191 +Rise : 2.368 +Fall : 2.401 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 2.422 -Fall : 2.474 +Rise : 2.539 +Fall : 2.610 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 2.385 -Fall : 2.429 +Rise : 2.549 +Fall : 2.620 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 2.190 -Fall : 2.191 +Rise : 2.402 +Fall : 2.440 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 2.315 -Fall : 2.333 +Rise : 2.368 +Fall : 2.401 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -31455,31 +42512,38 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 2.818 +RR : 2.819 RF : FR : FF : 3.181 Input Port : SW[2] Output Port : LED[2] -RR : 2.437 +RR : 2.438 RF : FR : -FF : 2.866 +FF : 2.867 + +Input Port : raw_loader_in +Output Port : DRAM_DQ[6] +RR : 3.977 +RF : +FR : +FF : 4.754 Input Port : raw_loader_in Output Port : GPIO_1[22] -RR : 3.838 +RR : 4.061 RF : FR : -FF : 4.613 +FF : 4.868 Input Port : raw_loader_in Output Port : LED[3] -RR : 2.537 +RR : 2.656 RF : FR : -FF : 3.123 +FF : 3.282 +--------------------------------------------------------------------------------+ @@ -31489,31 +42553,314 @@ FF : 3.123 +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 2.732 +RR : 2.733 RF : FR : -FF : 3.100 +FF : 3.101 Input Port : SW[2] Output Port : LED[2] -RR : 2.366 +RR : 2.367 RF : FR : -FF : 2.798 +FF : 2.799 + +Input Port : raw_loader_in +Output Port : DRAM_DQ[6] +RR : 3.843 +RF : +FR : +FF : 4.611 Input Port : raw_loader_in Output Port : GPIO_1[22] -RR : 3.707 +RR : 3.920 RF : FR : -FF : 4.473 +FF : 4.717 Input Port : raw_loader_in Output Port : LED[3] -RR : 2.459 +RR : 2.572 RF : FR : -FF : 3.040 +FF : 3.193 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Output Enable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 3.466 +Fall : 3.373 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 3.753 +Fall : 3.660 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 3.753 +Fall : 3.660 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 3.566 +Fall : 3.492 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 3.562 +Fall : 3.497 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 3.466 +Fall : 3.373 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 3.529 +Fall : 3.436 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 3.529 +Fall : 3.436 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 3.532 +Fall : 3.458 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 2.680 +Fall : 2.587 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 2.956 +Fall : 2.863 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 2.956 +Fall : 2.863 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 2.767 +Fall : 2.693 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 2.769 +Fall : 2.704 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 2.680 +Fall : 2.587 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 2.741 +Fall : 2.648 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 2.741 +Fall : 2.648 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 2.734 +Fall : 2.660 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Output Disable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +0 to Hi-Z : 3.461 +1 to Hi-Z : 3.554 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +0 to Hi-Z : 3.795 +1 to Hi-Z : 3.888 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +0 to Hi-Z : 3.795 +1 to Hi-Z : 3.888 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +0 to Hi-Z : 3.575 +1 to Hi-Z : 3.649 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +0 to Hi-Z : 3.611 +1 to Hi-Z : 3.676 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +0 to Hi-Z : 3.461 +1 to Hi-Z : 3.554 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +0 to Hi-Z : 3.506 +1 to Hi-Z : 3.599 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +0 to Hi-Z : 3.506 +1 to Hi-Z : 3.599 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +0 to Hi-Z : 3.554 +1 to Hi-Z : 3.628 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Minimum Output Disable Times ; ++--------------------------------------------------------------------------------+ +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +0 to Hi-Z : 2.675 +1 to Hi-Z : 2.768 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +0 to Hi-Z : 2.996 +1 to Hi-Z : 3.089 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +0 to Hi-Z : 2.996 +1 to Hi-Z : 3.089 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +0 to Hi-Z : 2.775 +1 to Hi-Z : 2.849 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +0 to Hi-Z : 2.817 +1 to Hi-Z : 2.882 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +0 to Hi-Z : 2.675 +1 to Hi-Z : 2.768 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +0 to Hi-Z : 2.718 +1 to Hi-Z : 2.811 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +0 to Hi-Z : 2.718 +1 to Hi-Z : 2.811 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +0 to Hi-Z : 2.755 +1 to Hi-Z : 2.829 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +--------------------------------------------------------------------------------+ @@ -31528,72 +42875,86 @@ No synchronizer chains to report. ; Multicorner Timing Analysis Summary ; +--------------------------------------------------------------------------------+ Clock : Worst-case Slack -Setup : -18.123 -Hold : -0.053 -Recovery : -6.223 -Removal : 2.518 -Minimum Pulse Width : 9.208 +Setup : -18.571 +Hold : 0.098 +Recovery : -6.212 +Removal : 2.507 +Minimum Pulse Width : 4.748 Clock : CLOCK_50 -Setup : -18.123 -Hold : -0.053 +Setup : -18.571 +Hold : 0.098 Recovery : N/A Removal : N/A Minimum Pulse Width : 9.208 -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Setup : -7.533 +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Setup : 3.503 Hold : 0.186 Recovery : N/A Removal : N/A -Minimum Pulse Width : 19.600 +Minimum Pulse Width : 4.748 + +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Setup : -7.747 +Hold : 0.186 +Recovery : N/A +Removal : N/A +Minimum Pulse Width : 19.596 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Setup : -2.914 +Setup : -2.915 Hold : 0.177 Recovery : N/A Removal : N/A Minimum Pulse Width : 35.491 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Setup : -4.740 -Hold : 0.178 -Recovery : -6.223 -Removal : 2.518 +Setup : -4.731 +Hold : 0.177 +Recovery : -6.212 +Removal : 2.507 Minimum Pulse Width : 20.591 Clock : Design-wide TNS -Setup : -879.875 -Hold : -0.089 -Recovery : -459.348 +Setup : -1152.857 +Hold : 0.0 +Recovery : -460.73 Removal : 0.0 Minimum Pulse Width : 0.0 Clock : CLOCK_50 -Setup : -549.338 -Hold : -0.089 +Setup : -821.372 +Hold : 0.000 +Recovery : N/A +Removal : N/A +Minimum Pulse Width : 0.000 + +Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Setup : 0.000 +Hold : 0.000 Recovery : N/A Removal : N/A Minimum Pulse Width : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Setup : -284.813 +Setup : -287.138 Hold : 0.000 Recovery : N/A Removal : N/A Minimum Pulse Width : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Setup : -2.914 +Setup : -2.915 Hold : 0.000 Recovery : N/A Removal : N/A Minimum Pulse Width : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Setup : -42.810 +Setup : -41.432 Hold : 0.000 -Recovery : -459.348 +Recovery : -460.730 Removal : 0.000 Minimum Pulse Width : 0.000 +--------------------------------------------------------------------------------+ @@ -31605,43 +42966,43 @@ Minimum Pulse Width : 0.000 +--------------------------------------------------------------------------------+ Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : 1.981 -Fall : 2.458 +Rise : 1.548 +Fall : 1.931 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : 3.874 -Fall : 4.319 +Rise : 3.846 +Fall : 4.271 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : SW[*] Clock Port : CLOCK_50 -Rise : 1.011 -Fall : 1.277 +Rise : 1.010 +Fall : 1.278 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : SW[2] Clock Port : CLOCK_50 -Rise : 1.011 -Fall : 1.277 +Rise : 1.010 +Fall : 1.278 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : 1.262 -Fall : 1.505 +Rise : 1.221 +Fall : 1.461 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : 2.823 -Fall : 3.104 +Rise : 2.814 +Fall : 3.095 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -31653,43 +43014,43 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : -0.841 -Fall : -1.690 +Rise : -0.561 +Fall : -1.355 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : -1.690 -Fall : -2.493 +Rise : -1.405 +Fall : -2.156 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : SW[*] Clock Port : CLOCK_50 Rise : -0.259 -Fall : -0.592 +Fall : -0.593 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : SW[2] Clock Port : CLOCK_50 Rise : -0.259 -Fall : -0.592 +Fall : -0.593 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : -0.368 -Fall : -0.776 +Rise : -0.342 +Fall : -0.733 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : -0.742 -Fall : -1.295 +Rise : -0.737 +Fall : -1.290 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -31699,199 +43060,619 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ ; Clock to Output Times ; +--------------------------------------------------------------------------------+ -Data Port : GPIO_1[*] +Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 10.359 -Fall : 10.359 +Rise : 10.801 +Fall : 10.789 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[16] +Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 10.359 -Fall : 10.359 +Rise : 10.164 +Fall : 10.160 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[17] +Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 9.229 -Fall : 9.317 +Rise : 10.350 +Fall : 10.351 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[18] +Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 10.015 -Fall : 9.971 +Rise : 10.114 +Fall : 10.074 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[19] +Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 9.628 -Fall : 9.644 +Rise : 10.072 +Fall : 10.237 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[20] +Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 9.826 -Fall : 9.843 +Rise : 10.376 +Fall : 10.386 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[21] +Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 9.397 -Fall : 9.318 +Rise : 10.482 +Fall : 10.574 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[22] +Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 9.972 -Fall : 9.975 +Rise : 10.801 +Fall : 10.789 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[23] +Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 9.201 -Fall : 9.152 +Rise : 10.294 +Fall : 10.222 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 7.986 -Fall : 7.983 +Rise : 10.527 +Fall : 10.543 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 10.022 +Fall : 10.010 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 10.153 +Fall : 10.157 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 10.039 +Fall : 10.024 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 9.790 +Fall : 9.910 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 10.258 +Fall : 10.260 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 10.080 +Fall : 10.129 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 10.527 +Fall : 10.543 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 9.684 +Fall : 9.676 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_ADDR[*] +Clock Port : CLOCK_50 +Rise : 3.430 +Fall : 3.345 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[0] +Clock Port : CLOCK_50 +Rise : 3.425 +Fall : 3.340 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[1] +Clock Port : CLOCK_50 +Rise : 3.320 +Fall : 3.233 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[2] +Clock Port : CLOCK_50 +Rise : 3.320 +Fall : 3.233 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[3] +Clock Port : CLOCK_50 +Rise : 3.319 +Fall : 3.232 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[4] +Clock Port : CLOCK_50 +Rise : 3.321 +Fall : 3.234 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[5] +Clock Port : CLOCK_50 +Rise : 3.318 +Fall : 3.231 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[6] +Clock Port : CLOCK_50 +Rise : 3.319 +Fall : 3.232 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[7] +Clock Port : CLOCK_50 +Rise : 3.317 +Fall : 3.230 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[8] +Clock Port : CLOCK_50 +Rise : 3.296 +Fall : 3.214 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[9] +Clock Port : CLOCK_50 +Rise : 3.425 +Fall : 3.340 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[10] +Clock Port : CLOCK_50 +Rise : 3.416 +Fall : 3.331 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[11] +Clock Port : CLOCK_50 +Rise : 3.430 +Fall : 3.345 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[12] +Clock Port : CLOCK_50 +Rise : 3.294 +Fall : 3.212 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[*] +Clock Port : CLOCK_50 +Rise : 3.320 +Fall : 3.233 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[0] +Clock Port : CLOCK_50 +Rise : 3.318 +Fall : 3.231 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[1] +Clock Port : CLOCK_50 +Rise : 3.320 +Fall : 3.233 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CAS_N +Clock Port : CLOCK_50 +Rise : 3.426 +Fall : 3.341 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 6.248 +Fall : 6.300 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 5.552 +Fall : 5.647 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 5.839 +Fall : 5.898 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 5.545 +Fall : 5.576 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 5.269 +Fall : 5.330 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 5.626 +Fall : 5.683 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 5.718 +Fall : 5.830 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 5.584 +Fall : 5.653 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 5.733 +Fall : 5.777 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[8] +Clock Port : CLOCK_50 +Rise : 6.248 +Fall : 6.299 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[9] +Clock Port : CLOCK_50 +Rise : 6.038 +Fall : 6.073 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[10] +Clock Port : CLOCK_50 +Rise : 6.021 +Fall : 6.053 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[11] +Clock Port : CLOCK_50 +Rise : 6.021 +Fall : 6.053 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[12] +Clock Port : CLOCK_50 +Rise : 6.215 +Fall : 6.300 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[13] +Clock Port : CLOCK_50 +Rise : 6.241 +Fall : 6.286 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[14] +Clock Port : CLOCK_50 +Rise : 6.241 +Fall : 6.286 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[15] +Clock Port : CLOCK_50 +Rise : 5.859 +Fall : 5.918 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[*] +Clock Port : CLOCK_50 +Rise : 3.317 +Fall : 3.230 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[0] +Clock Port : CLOCK_50 +Rise : 3.317 +Fall : 3.230 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[1] +Clock Port : CLOCK_50 +Rise : 3.317 +Fall : 3.230 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_RAS_N +Clock Port : CLOCK_50 +Rise : 3.426 +Fall : 3.341 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_WE_N +Clock Port : CLOCK_50 +Rise : 3.423 +Fall : 3.338 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : 4.576 +Fall : +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : +Fall : 4.505 +Clock Edge : Fall +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 8.525 +Fall : 8.506 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 7.614 +Fall : 7.674 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 7.796 +Fall : 7.806 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 8.092 +Fall : 8.080 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 7.910 +Fall : 8.021 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 8.495 +Fall : 8.500 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 8.018 +Fall : 8.084 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 8.525 +Fall : 8.506 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 7.947 +Fall : 7.936 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 8.377 +Fall : 8.374 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 7.696 -Fall : 7.696 +Rise : 7.472 +Fall : 7.524 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 7.783 -Fall : 7.821 +Rise : 7.599 +Fall : 7.612 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 7.371 -Fall : 7.388 +Rise : 8.017 +Fall : 8.030 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 7.739 -Fall : 7.774 +Rise : 7.628 +Fall : 7.694 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 7.986 -Fall : 7.975 +Rise : 8.377 +Fall : 8.374 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 7.534 -Fall : 7.528 +Rise : 7.619 +Fall : 7.643 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 7.914 -Fall : 7.983 +Rise : 8.251 +Fall : 8.260 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 7.285 -Fall : 7.303 +Rise : 7.224 +Fall : 7.248 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 8.197 -Fall : 7.907 +Rise : 8.645 +Fall : 8.352 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 8.197 -Fall : 7.907 +Rise : 8.645 +Fall : 8.352 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 6.071 -Fall : 5.974 +Rise : 7.356 +Fall : 7.355 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 6.410 -Fall : 6.400 +Rise : 6.643 +Fall : 6.643 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 6.836 -Fall : 6.810 +Rise : 6.647 +Fall : 6.639 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 6.558 -Fall : 6.425 +Rise : 6.988 +Fall : 6.893 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 6.558 -Fall : 6.425 +Rise : 6.282 +Fall : 6.183 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 6.366 -Fall : 6.305 +Rise : 6.690 +Fall : 6.712 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 6.429 -Fall : 6.279 +Rise : 6.988 +Fall : 6.893 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 6.429 -Fall : 6.279 +Rise : 6.988 +Fall : 6.893 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -31904,36 +43685,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 6.621 -Fall : 6.664 +Rise : 7.297 +Fall : 7.345 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 6.621 -Fall : 6.664 +Rise : 6.937 +Fall : 6.925 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 6.426 -Fall : 6.412 +Rise : 7.297 +Fall : 7.345 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 6.231 -Fall : 6.211 +Rise : 6.690 +Fall : 6.631 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 6.443 -Fall : 6.428 +Rise : 6.641 +Fall : 6.567 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -31999,199 +43780,619 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ ; Minimum Clock to Output Times ; +--------------------------------------------------------------------------------+ -Data Port : GPIO_1[*] +Data Port : DRAM_DQ[*] Clock Port : CLOCK_50 -Rise : 4.404 -Fall : 4.492 +Rise : 4.488 +Fall : 4.607 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[16] +Data Port : DRAM_DQ[0] Clock Port : CLOCK_50 -Rise : 4.714 -Fall : 4.811 +Rise : 4.624 +Fall : 4.719 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[17] +Data Port : DRAM_DQ[1] Clock Port : CLOCK_50 -Rise : 4.756 -Fall : 4.806 +Rise : 4.670 +Fall : 4.779 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[18] +Data Port : DRAM_DQ[2] Clock Port : CLOCK_50 -Rise : 4.404 -Fall : 4.492 +Rise : 4.488 +Fall : 4.607 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[19] +Data Port : DRAM_DQ[3] Clock Port : CLOCK_50 -Rise : 4.619 -Fall : 4.708 +Rise : 4.700 +Fall : 4.843 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[20] +Data Port : DRAM_DQ[4] Clock Port : CLOCK_50 -Rise : 4.805 -Fall : 4.924 +Rise : 4.819 +Fall : 4.940 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[21] +Data Port : DRAM_DQ[5] Clock Port : CLOCK_50 -Rise : 4.528 -Fall : 4.559 +Rise : 4.988 +Fall : 5.131 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[22] +Data Port : DRAM_DQ[6] Clock Port : CLOCK_50 -Rise : 4.418 -Fall : 4.501 +Rise : 4.747 +Fall : 4.889 Clock Edge : Rise Clock Reference : CLOCK_50 -Data Port : GPIO_1[23] +Data Port : DRAM_DQ[7] Clock Port : CLOCK_50 -Rise : 4.478 -Fall : 4.502 +Rise : 4.935 +Fall : 5.065 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 3.074 -Fall : 3.195 +Rise : 4.461 +Fall : 4.568 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[16] +Clock Port : CLOCK_50 +Rise : 4.562 +Fall : 4.652 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[17] +Clock Port : CLOCK_50 +Rise : 4.593 +Fall : 4.698 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[18] +Clock Port : CLOCK_50 +Rise : 4.461 +Fall : 4.568 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[19] +Clock Port : CLOCK_50 +Rise : 4.577 +Fall : 4.666 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[20] +Clock Port : CLOCK_50 +Rise : 4.732 +Fall : 4.867 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[21] +Clock Port : CLOCK_50 +Rise : 4.749 +Fall : 4.851 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[22] +Clock Port : CLOCK_50 +Rise : 4.636 +Fall : 4.789 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : GPIO_1[23] +Clock Port : CLOCK_50 +Rise : 4.637 +Fall : 4.728 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : DRAM_ADDR[*] +Clock Port : CLOCK_50 +Rise : 1.724 +Fall : 1.674 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[0] +Clock Port : CLOCK_50 +Rise : 1.807 +Fall : 1.736 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[1] +Clock Port : CLOCK_50 +Rise : 1.747 +Fall : 1.692 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[2] +Clock Port : CLOCK_50 +Rise : 1.747 +Fall : 1.692 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[3] +Clock Port : CLOCK_50 +Rise : 1.746 +Fall : 1.691 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[4] +Clock Port : CLOCK_50 +Rise : 1.748 +Fall : 1.693 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[5] +Clock Port : CLOCK_50 +Rise : 1.746 +Fall : 1.691 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[6] +Clock Port : CLOCK_50 +Rise : 1.746 +Fall : 1.691 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[7] +Clock Port : CLOCK_50 +Rise : 1.744 +Fall : 1.689 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[8] +Clock Port : CLOCK_50 +Rise : 1.726 +Fall : 1.676 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[9] +Clock Port : CLOCK_50 +Rise : 1.807 +Fall : 1.736 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[10] +Clock Port : CLOCK_50 +Rise : 1.800 +Fall : 1.729 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[11] +Clock Port : CLOCK_50 +Rise : 1.808 +Fall : 1.737 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_ADDR[12] +Clock Port : CLOCK_50 +Rise : 1.724 +Fall : 1.674 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[*] +Clock Port : CLOCK_50 +Rise : 1.745 +Fall : 1.690 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[0] +Clock Port : CLOCK_50 +Rise : 1.745 +Fall : 1.690 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_BA[1] +Clock Port : CLOCK_50 +Rise : 1.746 +Fall : 1.691 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CAS_N +Clock Port : CLOCK_50 +Rise : 1.805 +Fall : 1.734 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 2.705 +Fall : 2.683 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 2.876 +Fall : 2.979 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 3.004 +Fall : 3.108 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 2.854 +Fall : 2.959 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 2.709 +Fall : 2.815 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 2.908 +Fall : 3.006 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 2.981 +Fall : 3.104 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 2.865 +Fall : 2.958 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 2.986 +Fall : 3.112 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[8] +Clock Port : CLOCK_50 +Rise : 2.944 +Fall : 2.881 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[9] +Clock Port : CLOCK_50 +Rise : 2.819 +Fall : 2.774 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[10] +Clock Port : CLOCK_50 +Rise : 2.809 +Fall : 2.765 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[11] +Clock Port : CLOCK_50 +Rise : 2.809 +Fall : 2.765 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[12] +Clock Port : CLOCK_50 +Rise : 2.935 +Fall : 2.878 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[13] +Clock Port : CLOCK_50 +Rise : 2.936 +Fall : 2.874 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[14] +Clock Port : CLOCK_50 +Rise : 2.936 +Fall : 2.874 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[15] +Clock Port : CLOCK_50 +Rise : 2.705 +Fall : 2.683 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[*] +Clock Port : CLOCK_50 +Rise : 1.744 +Fall : 1.689 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[0] +Clock Port : CLOCK_50 +Rise : 1.744 +Fall : 1.689 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQM[1] +Clock Port : CLOCK_50 +Rise : 1.744 +Fall : 1.689 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_RAS_N +Clock Port : CLOCK_50 +Rise : 1.805 +Fall : 1.734 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_WE_N +Clock Port : CLOCK_50 +Rise : 1.804 +Fall : 1.733 +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : 3.708 +Fall : +Clock Edge : Rise +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_CLK +Clock Port : CLOCK_50 +Rise : +Fall : 3.654 +Clock Edge : Fall +Clock Reference : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] + +Data Port : DRAM_DQ[*] +Clock Port : CLOCK_50 +Rise : 3.484 +Fall : 3.630 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[0] +Clock Port : CLOCK_50 +Rise : 3.729 +Fall : 3.823 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[1] +Clock Port : CLOCK_50 +Rise : 3.734 +Fall : 3.824 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[2] +Clock Port : CLOCK_50 +Rise : 3.908 +Fall : 4.032 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[3] +Clock Port : CLOCK_50 +Rise : 3.717 +Fall : 3.979 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[4] +Clock Port : CLOCK_50 +Rise : 3.578 +Fall : 3.745 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[5] +Clock Port : CLOCK_50 +Rise : 3.905 +Fall : 4.039 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[6] +Clock Port : CLOCK_50 +Rise : 3.484 +Fall : 3.630 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : DRAM_DQ[7] +Clock Port : CLOCK_50 +Rise : 3.918 +Fall : 4.056 +Clock Edge : Rise +Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + +Data Port : GPIO_1[*] +Clock Port : CLOCK_50 +Rise : 3.373 +Fall : 3.530 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 3.656 -Fall : 3.753 +Rise : 3.667 +Fall : 3.756 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 3.705 -Fall : 3.857 +Rise : 3.657 +Fall : 3.743 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 3.537 -Fall : 3.607 +Rise : 3.881 +Fall : 3.993 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 3.562 -Fall : 3.684 +Rise : 3.594 +Fall : 3.802 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 3.074 -Fall : 3.195 +Rise : 3.491 +Fall : 3.672 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 3.587 -Fall : 3.750 +Rise : 3.669 +Fall : 3.764 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 3.787 -Fall : 3.888 +Rise : 3.373 +Fall : 3.530 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 3.402 -Fall : 3.449 +Rise : 3.578 +Fall : 3.660 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 2.246 -Fall : 2.250 +Rise : 2.537 +Fall : 2.596 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 3.784 -Fall : 3.550 +Rise : 4.052 +Fall : 3.869 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 2.246 -Fall : 2.250 +Rise : 2.650 +Fall : 2.713 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 2.373 -Fall : 2.393 +Rise : 2.537 +Fall : 2.596 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 2.590 -Fall : 2.631 +Rise : 2.538 +Fall : 2.597 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 2.286 -Fall : 2.308 +Rise : 2.171 +Fall : 2.177 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 2.504 -Fall : 2.535 +Rise : 2.181 +Fall : 2.190 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 2.286 -Fall : 2.308 +Rise : 2.171 +Fall : 2.177 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 2.428 -Fall : 2.440 +Rise : 2.558 +Fall : 2.607 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 2.428 -Fall : 2.440 +Rise : 2.558 +Fall : 2.607 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -32204,36 +44405,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 2.190 -Fall : 2.191 +Rise : 2.368 +Fall : 2.401 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 2.422 -Fall : 2.474 +Rise : 2.539 +Fall : 2.610 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 2.385 -Fall : 2.429 +Rise : 2.549 +Fall : 2.620 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 2.190 -Fall : 2.191 +Rise : 2.402 +Fall : 2.440 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 2.315 -Fall : 2.333 +Rise : 2.368 +Fall : 2.401 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -32308,24 +44509,31 @@ FF : 4.693 Input Port : SW[2] Output Port : LED[2] -RR : 4.044 +RR : 4.045 RF : FR : FF : 4.195 Input Port : raw_loader_in -Output Port : GPIO_1[22] -RR : 6.626 +Output Port : DRAM_DQ[6] +RR : 6.893 RF : FR : -FF : 7.003 +FF : 7.253 + +Input Port : raw_loader_in +Output Port : GPIO_1[22] +RR : 7.004 +RF : +FR : +FF : 7.359 Input Port : raw_loader_in Output Port : LED[3] -RR : 4.318 +RR : 4.487 RF : FR : -FF : 4.517 +FF : 4.751 +--------------------------------------------------------------------------------+ @@ -32335,31 +44543,38 @@ FF : 4.517 +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 2.732 +RR : 2.733 RF : FR : -FF : 3.100 +FF : 3.101 Input Port : SW[2] Output Port : LED[2] -RR : 2.366 +RR : 2.367 RF : FR : -FF : 2.798 +FF : 2.799 + +Input Port : raw_loader_in +Output Port : DRAM_DQ[6] +RR : 3.843 +RF : +FR : +FF : 4.611 Input Port : raw_loader_in Output Port : GPIO_1[22] -RR : 3.707 +RR : 3.920 RF : FR : -FF : 4.473 +FF : 4.717 Input Port : raw_loader_in Output Port : LED[3] -RR : 2.459 +RR : 2.572 RF : FR : -FF : 3.040 +FF : 3.193 +--------------------------------------------------------------------------------+ @@ -33793,6 +46008,535 @@ EBD File Name : n/a EBD Signal Name : n/a EBD Far-end : n/a +Pin : DRAM_BA[0] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_BA[1] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQM[0] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQM[1] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_RAS_N +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_CAS_N +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_CKE +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_CLK +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_WE_N +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_CS_N +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[0] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[1] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[2] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[3] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[4] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[5] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[6] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[7] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[8] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[9] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[10] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[11] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_ADDR[12] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + Pin : I2C_SCLK I/O Standard : 3.3-V LVTTL Near Tline Length : 0 in @@ -33839,6 +46583,374 @@ EBD File Name : n/a EBD Signal Name : n/a EBD Far-end : n/a +Pin : DRAM_DQ[0] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[1] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[2] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[3] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[4] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[5] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[6] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[7] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[8] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[9] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[10] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[11] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[12] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[13] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[14] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + +Pin : DRAM_DQ[15] +I/O Standard : 3.3-V LVTTL +Near Tline Length : 0 in +Near Tline L per Length : 0 H/in +Near Tline C per Length : 0 F/in +Near Series R : short +Near Differential R : - +Near Pull-up R : open +Near Pull-down R : open +Near C : open +Far Tline Length : 0 in +Far Tline L per Length : 0 H/in +Far Tline C per Length : 0 F/in +Far Series R : short +Far Pull-up R : open +Far Pull-down R : open +Far C : open +Termination Voltage : 0 V +Far Differential R : - +EBD File Name : n/a +EBD Signal Name : n/a +EBD Far-end : n/a + Pin : ~ALTERA_DCLK~ I/O Standard : 3.3-V LVTTL Near Tline Length : 0 in @@ -33911,6 +47023,86 @@ I/O Standard : 3.3-V LVTTL 10-90 Rise Time : 2640 ps 90-10 Fall Time : 2640 ps +Pin : DRAM_DQ[0] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[1] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[2] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[3] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[4] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[5] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[6] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[7] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[8] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[9] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[10] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[11] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[12] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[13] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[14] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + +Pin : DRAM_DQ[15] +I/O Standard : 3.3-V LVTTL +10-90 Rise Time : 2640 ps +90-10 Fall Time : 2640 ps + Pin : SW[1] I/O Standard : 3.3-V LVTTL 10-90 Rise Time : 2640 ps @@ -35527,6 +48719,581 @@ Ringback Voltage on Fall at Far-end : 0.241 V Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No +Pin : DRAM_BA[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_BA[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQM[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQM[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_RAS_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_CAS_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_CKE +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_CLK +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_WE_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_CS_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.09 V +Vol Min at FPGA Pin : -0.0123 V +Ringback Voltage on Rise at FPGA Pin : 0.281 V +Ringback Voltage on Fall at FPGA Pin : 0.305 V +10-90 Rise Time at FPGA Pin : 4.54e-09 s +90-10 Fall Time at FPGA Pin : 3.32e-09 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.09 V +Vol Min at Far-end : -0.0123 V +Ringback Voltage on Rise at Far-end : 0.281 V +Ringback Voltage on Fall at Far-end : 0.305 V +10-90 Rise Time at Far-end : 4.54e-09 s +90-10 Fall Time at Far-end : 3.32e-09 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[4] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[5] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[6] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[7] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[8] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.16 V +Vol Min at FPGA Pin : -0.11 V +Ringback Voltage on Rise at FPGA Pin : 0.302 V +Ringback Voltage on Fall at FPGA Pin : 0.22 V +10-90 Rise Time at FPGA Pin : 4.82e-10 s +90-10 Fall Time at FPGA Pin : 4.27e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.16 V +Vol Min at Far-end : -0.11 V +Ringback Voltage on Rise at Far-end : 0.302 V +Ringback Voltage on Fall at Far-end : 0.22 V +10-90 Rise Time at Far-end : 4.82e-10 s +90-10 Fall Time at Far-end : 4.27e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[9] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[10] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[11] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[12] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.16 V +Vol Min at FPGA Pin : -0.11 V +Ringback Voltage on Rise at FPGA Pin : 0.302 V +Ringback Voltage on Fall at FPGA Pin : 0.22 V +10-90 Rise Time at FPGA Pin : 4.82e-10 s +90-10 Fall Time at FPGA Pin : 4.27e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.16 V +Vol Min at Far-end : -0.11 V +Ringback Voltage on Rise at Far-end : 0.302 V +Ringback Voltage on Fall at Far-end : 0.22 V +10-90 Rise Time at Far-end : 4.82e-10 s +90-10 Fall Time at Far-end : 4.27e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + Pin : I2C_SCLK I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s @@ -35577,6 +49344,406 @@ Ringback Voltage on Fall at Far-end : 0.194 V Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No +Pin : DRAM_DQ[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.16 V +Vol Min at FPGA Pin : -0.11 V +Ringback Voltage on Rise at FPGA Pin : 0.302 V +Ringback Voltage on Fall at FPGA Pin : 0.22 V +10-90 Rise Time at FPGA Pin : 4.82e-10 s +90-10 Fall Time at FPGA Pin : 4.27e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.16 V +Vol Min at Far-end : -0.11 V +Ringback Voltage on Rise at Far-end : 0.302 V +Ringback Voltage on Fall at Far-end : 0.22 V +10-90 Rise Time at Far-end : 4.82e-10 s +90-10 Fall Time at Far-end : 4.27e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[4] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[5] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[6] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[7] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[8] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[9] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[10] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[11] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[12] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[13] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[14] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.24e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.115 V +Ringback Voltage on Rise at FPGA Pin : 0.31 V +Ringback Voltage on Fall at FPGA Pin : 0.241 V +10-90 Rise Time at FPGA Pin : 5.06e-10 s +90-10 Fall Time at FPGA Pin : 4.37e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.24e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.115 V +Ringback Voltage on Rise at Far-end : 0.31 V +Ringback Voltage on Fall at Far-end : 0.241 V +10-90 Rise Time at Far-end : 5.06e-10 s +90-10 Fall Time at Far-end : 4.37e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[15] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 1.54e-08 V +Voh Max at FPGA Pin : 3.14 V +Vol Min at FPGA Pin : -0.074 V +Ringback Voltage on Rise at FPGA Pin : 0.343 V +Ringback Voltage on Fall at FPGA Pin : 0.194 V +10-90 Rise Time at FPGA Pin : 7.35e-10 s +90-10 Fall Time at FPGA Pin : 6.36e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 1.54e-08 V +Voh Max at Far-end : 3.14 V +Vol Min at Far-end : -0.074 V +Ringback Voltage on Rise at Far-end : 0.343 V +Ringback Voltage on Fall at Far-end : 0.194 V +10-90 Rise Time at Far-end : 7.35e-10 s +90-10 Fall Time at Far-end : 6.36e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + Pin : ~ALTERA_DCLK~ I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s @@ -37183,6 +51350,581 @@ Ringback Voltage on Fall at Far-end : 0.168 V Monotonic Rise at Far-end : Yes Monotonic Fall at Far-end : No +Pin : DRAM_BA[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_BA[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQM[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQM[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_RAS_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_CAS_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_CKE +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_CLK +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_WE_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_CS_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.08 V +Vol Min at FPGA Pin : -0.00675 V +Ringback Voltage on Rise at FPGA Pin : 0.232 V +Ringback Voltage on Fall at FPGA Pin : 0.283 V +10-90 Rise Time at FPGA Pin : 5.31e-09 s +90-10 Fall Time at FPGA Pin : 4.2e-09 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.08 V +Vol Min at Far-end : -0.00675 V +Ringback Voltage on Rise at Far-end : 0.232 V +Ringback Voltage on Fall at Far-end : 0.283 V +10-90 Rise Time at Far-end : 5.31e-09 s +90-10 Fall Time at Far-end : 4.2e-09 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[4] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[5] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[6] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[7] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[8] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.13 V +Vol Min at FPGA Pin : -0.0781 V +Ringback Voltage on Rise at FPGA Pin : 0.202 V +Ringback Voltage on Fall at FPGA Pin : 0.359 V +10-90 Rise Time at FPGA Pin : 6.54e-10 s +90-10 Fall Time at FPGA Pin : 5e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.13 V +Vol Min at Far-end : -0.0781 V +Ringback Voltage on Rise at Far-end : 0.202 V +Ringback Voltage on Fall at Far-end : 0.359 V +10-90 Rise Time at Far-end : 6.54e-10 s +90-10 Fall Time at Far-end : 5e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[9] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[10] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[11] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[12] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.13 V +Vol Min at FPGA Pin : -0.0781 V +Ringback Voltage on Rise at FPGA Pin : 0.202 V +Ringback Voltage on Fall at FPGA Pin : 0.359 V +10-90 Rise Time at FPGA Pin : 6.54e-10 s +90-10 Fall Time at FPGA Pin : 5e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.13 V +Vol Min at Far-end : -0.0781 V +Ringback Voltage on Rise at Far-end : 0.202 V +Ringback Voltage on Fall at Far-end : 0.359 V +10-90 Rise Time at Far-end : 6.54e-10 s +90-10 Fall Time at Far-end : 5e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + Pin : I2C_SCLK I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s @@ -37233,6 +51975,406 @@ Ringback Voltage on Fall at Far-end : 0.181 V Monotonic Rise at Far-end : Yes Monotonic Fall at Far-end : No +Pin : DRAM_DQ[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.13 V +Vol Min at FPGA Pin : -0.0781 V +Ringback Voltage on Rise at FPGA Pin : 0.202 V +Ringback Voltage on Fall at FPGA Pin : 0.359 V +10-90 Rise Time at FPGA Pin : 6.54e-10 s +90-10 Fall Time at FPGA Pin : 5e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.13 V +Vol Min at Far-end : -0.0781 V +Ringback Voltage on Rise at Far-end : 0.202 V +Ringback Voltage on Fall at Far-end : 0.359 V +10-90 Rise Time at Far-end : 6.54e-10 s +90-10 Fall Time at Far-end : 5e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[4] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[5] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[6] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[7] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[8] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[9] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[10] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[11] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[12] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[13] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[14] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2.99e-06 V +Voh Max at FPGA Pin : 3.11 V +Vol Min at FPGA Pin : -0.0717 V +Ringback Voltage on Rise at FPGA Pin : 0.209 V +Ringback Voltage on Fall at FPGA Pin : 0.168 V +10-90 Rise Time at FPGA Pin : 6.66e-10 s +90-10 Fall Time at FPGA Pin : 6.19e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2.99e-06 V +Voh Max at Far-end : 3.11 V +Vol Min at Far-end : -0.0717 V +Ringback Voltage on Rise at Far-end : 0.209 V +Ringback Voltage on Fall at Far-end : 0.168 V +10-90 Rise Time at Far-end : 6.66e-10 s +90-10 Fall Time at Far-end : 6.19e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[15] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.08 V +Steady State Vol at FPGA Pin : 2e-06 V +Voh Max at FPGA Pin : 3.12 V +Vol Min at FPGA Pin : -0.0547 V +Ringback Voltage on Rise at FPGA Pin : 0.276 V +Ringback Voltage on Fall at FPGA Pin : 0.181 V +10-90 Rise Time at FPGA Pin : 9.17e-10 s +90-10 Fall Time at FPGA Pin : 8.31e-10 s +Monotonic Rise at FPGA Pin : Yes +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.08 V +Steady State Vol at Far-end : 2e-06 V +Voh Max at Far-end : 3.12 V +Vol Min at Far-end : -0.0547 V +Ringback Voltage on Rise at Far-end : 0.276 V +Ringback Voltage on Fall at Far-end : 0.181 V +10-90 Rise Time at Far-end : 9.17e-10 s +90-10 Fall Time at Far-end : 8.31e-10 s +Monotonic Rise at Far-end : Yes +Monotonic Fall at Far-end : No + Pin : ~ALTERA_DCLK~ I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s @@ -38839,6 +53981,581 @@ Ringback Voltage on Fall at Far-end : 0.239 V Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No +Pin : DRAM_BA[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_BA[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQM[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQM[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_RAS_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_CAS_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_CKE +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_CLK +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_WE_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_CS_N +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.48 V +Vol Min at FPGA Pin : -0.0173 V +Ringback Voltage on Rise at FPGA Pin : 0.356 V +Ringback Voltage on Fall at FPGA Pin : 0.324 V +10-90 Rise Time at FPGA Pin : 3.89e-09 s +90-10 Fall Time at FPGA Pin : 3.06e-09 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.48 V +Vol Min at Far-end : -0.0173 V +Ringback Voltage on Rise at Far-end : 0.356 V +Ringback Voltage on Fall at Far-end : 0.324 V +10-90 Rise Time at Far-end : 3.89e-09 s +90-10 Fall Time at Far-end : 3.06e-09 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[4] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[5] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[6] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[7] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[8] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.6 V +Vol Min at FPGA Pin : -0.127 V +Ringback Voltage on Rise at FPGA Pin : 0.302 V +Ringback Voltage on Fall at FPGA Pin : 0.21 V +10-90 Rise Time at FPGA Pin : 4.55e-10 s +90-10 Fall Time at FPGA Pin : 4.11e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.6 V +Vol Min at Far-end : -0.127 V +Ringback Voltage on Rise at Far-end : 0.302 V +Ringback Voltage on Fall at Far-end : 0.21 V +10-90 Rise Time at Far-end : 4.55e-10 s +90-10 Fall Time at Far-end : 4.11e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[9] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[10] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[11] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_ADDR[12] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.6 V +Vol Min at FPGA Pin : -0.127 V +Ringback Voltage on Rise at FPGA Pin : 0.302 V +Ringback Voltage on Fall at FPGA Pin : 0.21 V +10-90 Rise Time at FPGA Pin : 4.55e-10 s +90-10 Fall Time at FPGA Pin : 4.11e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.6 V +Vol Min at Far-end : -0.127 V +Ringback Voltage on Rise at Far-end : 0.302 V +Ringback Voltage on Fall at Far-end : 0.21 V +10-90 Rise Time at Far-end : 4.55e-10 s +90-10 Fall Time at Far-end : 4.11e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + Pin : I2C_SCLK I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s @@ -38889,6 +54606,406 @@ Ringback Voltage on Fall at Far-end : 0.175 V Monotonic Rise at Far-end : No Monotonic Fall at Far-end : No +Pin : DRAM_DQ[0] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[1] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[2] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[3] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.6 V +Vol Min at FPGA Pin : -0.127 V +Ringback Voltage on Rise at FPGA Pin : 0.302 V +Ringback Voltage on Fall at FPGA Pin : 0.21 V +10-90 Rise Time at FPGA Pin : 4.55e-10 s +90-10 Fall Time at FPGA Pin : 4.11e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.6 V +Vol Min at Far-end : -0.127 V +Ringback Voltage on Rise at Far-end : 0.302 V +Ringback Voltage on Fall at Far-end : 0.21 V +10-90 Rise Time at Far-end : 4.55e-10 s +90-10 Fall Time at Far-end : 4.11e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[4] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[5] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[6] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[7] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[8] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[9] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[10] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[11] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[12] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[13] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[14] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.85e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.141 V +Ringback Voltage on Rise at FPGA Pin : 0.301 V +Ringback Voltage on Fall at FPGA Pin : 0.239 V +10-90 Rise Time at FPGA Pin : 4.61e-10 s +90-10 Fall Time at FPGA Pin : 4.2e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.85e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.141 V +Ringback Voltage on Rise at Far-end : 0.301 V +Ringback Voltage on Fall at Far-end : 0.239 V +10-90 Rise Time at Far-end : 4.61e-10 s +90-10 Fall Time at Far-end : 4.2e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + +Pin : DRAM_DQ[15] +I/O Standard : 3.3-V LVTTL +Board Delay on Rise : 0 s +Board Delay on Fall : 0 s +Steady State Voh at FPGA Pin : 3.46 V +Steady State Vol at FPGA Pin : 1.25e-07 V +Voh Max at FPGA Pin : 3.57 V +Vol Min at FPGA Pin : -0.0855 V +Ringback Voltage on Rise at FPGA Pin : 0.315 V +Ringback Voltage on Fall at FPGA Pin : 0.175 V +10-90 Rise Time at FPGA Pin : 6.79e-10 s +90-10 Fall Time at FPGA Pin : 6.15e-10 s +Monotonic Rise at FPGA Pin : No +Monotonic Fall at FPGA Pin : No +Steady State Voh at Far-end : 3.46 V +Steady State Vol at Far-end : 1.25e-07 V +Voh Max at Far-end : 3.57 V +Vol Min at Far-end : -0.0855 V +Ringback Voltage on Rise at Far-end : 0.315 V +Ringback Voltage on Fall at Far-end : 0.175 V +10-90 Rise Time at Far-end : 6.79e-10 s +90-10 Fall Time at Far-end : 6.15e-10 s +Monotonic Rise at Far-end : No +Monotonic Fall at Far-end : No + Pin : ~ALTERA_DCLK~ I/O Standard : 3.3-V LVTTL Board Delay on Rise : 0 s @@ -38961,14 +55078,28 @@ FF Paths : 0 From Clock : CLOCK_50 To Clock : CLOCK_50 -RR Paths : 227 +RR Paths : 300 FR Paths : 0 RF Paths : 0 FF Paths : 0 +From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +To Clock : CLOCK_50 +RR Paths : 108 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + +From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] +To Clock : CLOCK_50 +RR Paths : 1 +FR Paths : 1 +RF Paths : 0 +FF Paths : 0 + From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] To Clock : CLOCK_50 -RR Paths : 1125 +RR Paths : 1201 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -38980,16 +55111,23 @@ FR Paths : 0 RF Paths : 0 FF Paths : 0 +From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +To Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +RR Paths : 1926 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + From Clock : CLOCK_50 To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -RR Paths : 260 +RR Paths : 272 FR Paths : 0 RF Paths : 0 FF Paths : 0 From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -RR Paths : 1054 +RR Paths : 1070 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -39017,7 +55155,7 @@ FF Paths : 0 From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -RR Paths : 1428 +RR Paths : 1437 FR Paths : 180 RF Paths : 0 FF Paths : 21 @@ -39045,14 +55183,28 @@ FF Paths : 0 From Clock : CLOCK_50 To Clock : CLOCK_50 -RR Paths : 227 +RR Paths : 300 FR Paths : 0 RF Paths : 0 FF Paths : 0 +From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +To Clock : CLOCK_50 +RR Paths : 108 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + +From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1] +To Clock : CLOCK_50 +RR Paths : 1 +FR Paths : 1 +RF Paths : 0 +FF Paths : 0 + From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] To Clock : CLOCK_50 -RR Paths : 1125 +RR Paths : 1201 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -39064,16 +55216,23 @@ FR Paths : 0 RF Paths : 0 FF Paths : 0 +From Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +To Clock : sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +RR Paths : 1926 +FR Paths : 0 +RF Paths : 0 +FF Paths : 0 + From Clock : CLOCK_50 To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -RR Paths : 260 +RR Paths : 272 FR Paths : 0 RF Paths : 0 FF Paths : 0 From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -RR Paths : 1054 +RR Paths : 1070 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -39101,7 +55260,7 @@ FF Paths : 0 From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -RR Paths : 1428 +RR Paths : 1437 FR Paths : 180 RF Paths : 0 FF Paths : 21 @@ -39186,7 +55345,7 @@ Hold : 0 Info: ******************************************************************* Info: Running Quartus II 32-bit TimeQuest Timing Analyzer Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Fri Apr 1 18:55:44 2022 + Info: Processing started: Sat Apr 2 14:51:13 2022 Info: Command: quartus_sta spectrum -c spectrum Info: qsta_default_script.tcl version: #1 Warning (20028): Parallel compilation is not licensed and has been disabled @@ -39201,6 +55360,8 @@ Info (332110): Deriving PLL clocks Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[0]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[0]} Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[1]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[1]} Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[2]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[2]} + Info (332110): create_generated_clock -source {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]} {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]} + Info (332110): create_generated_clock -source {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]} {sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[1]} Warning (332174): Ignored filter at spectrum.sdc(21): ula_|clocks_|clk_cpu|regout could not be matched with a pin Warning (332049): Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection Info (332050): create_generated_clock -name clk_cpu -source [get_pins {ula_|clocks_|clk_cpu|clk}] -divide_by 4 [get_pins {ula_|clocks_|clk_cpu|regout}] @@ -39210,519 +55371,521 @@ Warning (332174): Ignored filter at spectrum.sdc(57): KEY1 could not be matched Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[0] could not be matched with a clock Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[1] could not be matched with a clock Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[2] could not be matched with a clock -Warning (332125): Found combinational loop of 511 nodes - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~9|datab" - Warning (332126): Node "z80_|alu_control_|db[0]~9|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~12|datac" - Warning (332126): Node "z80_|alu_control_|db[0]~12|combout" - Warning (332126): Node "z80_|bus_control_|db[0]~17|datab" - Warning (332126): Node "z80_|bus_control_|db[0]~17|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~8|datac" - Warning (332126): Node "z80_|alu_control_|db[0]~8|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~9|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datab" - Warning (332126): Node "z80_|alu_|db[0]~19|datac" - Warning (332126): Node "z80_|alu_|db[0]~19|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~15|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~15|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~16|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~16|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~17|datac" - Warning (332126): Node "z80_|alu_|db_low[1]~17|combout" - Warning (332126): Node "z80_|alu_|db[1]~13|datac" - Warning (332126): Node "z80_|alu_|db[1]~13|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~16|datac" - Warning (332126): Node "z80_|alu_|db_low[0]~21|datac" - Warning (332126): Node "z80_|alu_|db_low[0]~21|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~22|datab" - Warning (332126): Node "z80_|alu_|db_low[0]~22|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~23|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~23|combout" - Warning (332126): Node "z80_|alu_|db[0]~18|datab" - Warning (332126): Node "z80_|alu_|db[0]~18|combout" - Warning (332126): Node "z80_|alu_|db[0]~19|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|combout" - Warning (332126): Node "z80_|alu_|db[1]~12|datac" - Warning (332126): Node "z80_|alu_|db[1]~12|combout" - Warning (332126): Node "z80_|alu_|db[1]~13|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|datac" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datac" - Warning (332126): Node "z80_|alu_|db_low[2]~2|datac" - Warning (332126): Node "z80_|alu_|db_low[2]~2|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~3|datac" - Warning (332126): Node "z80_|alu_|db_low[2]~3|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~24|datab" - Warning (332126): Node "z80_|alu_|db_low[2]~24|combout" - Warning (332126): Node "z80_|alu_|db[2]~15|dataa" - Warning (332126): Node "z80_|alu_|db[2]~15|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~15|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~37|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~37|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~38|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~38|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~7|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~7|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~8|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~8|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|datab" - Warning (332126): Node "z80_|alu_|db[2]~14|datad" - Warning (332126): Node "z80_|alu_|db[2]~14|combout" - Warning (332126): Node "z80_|alu_|db[2]~15|datac" - Warning (332126): Node "z80_|alu_control_|db[2]~27|datab" - Warning (332126): Node "z80_|alu_control_|db[2]~27|combout" +Warning (332125): Found combinational loop of 513 nodes + Warning (332126): Node "z80_|bus_control_|db[2]~13|combout" Warning (332126): Node "z80_|alu_control_|db[2]~29|datad" Warning (332126): Node "z80_|alu_control_|db[2]~29|combout" - Warning (332126): Node "z80_|bus_control_|db[2]~12|datab" - Warning (332126): Node "z80_|bus_control_|db[2]~12|combout" - Warning (332126): Node "z80_|bus_control_|db[2]~13|datad" - Warning (332126): Node "z80_|bus_control_|db[2]~13|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~28|dataa" - Warning (332126): Node "z80_|alu_control_|db[2]~28|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~29|datac" - Warning (332126): Node "z80_|alu_|db[2]~14|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|dataa" + Warning (332126): Node "z80_|alu_control_|db[2]~30|datad" + Warning (332126): Node "z80_|alu_control_|db[2]~30|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~38|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~38|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~2|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~2|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~28|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~1|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~1|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~29|datab" Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|datab" Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|datad" Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|datad" - Warning (332126): Node "z80_|alu_|db_low[2]~3|dataa" - Warning (332126): Node "z80_|alu_|db_low[3]~7|datad" - Warning (332126): Node "z80_|alu_|db_low[3]~7|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~8|datac" - Warning (332126): Node "z80_|alu_|db_low[3]~8|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~11|datad" - Warning (332126): Node "z80_|alu_|db_low[3]~11|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~25|datac" - Warning (332126): Node "z80_|alu_|db_low[3]~25|combout" - Warning (332126): Node "z80_|alu_|db[3]~10|datad" - Warning (332126): Node "z80_|alu_|db[3]~10|combout" - Warning (332126): Node "z80_|alu_|db[3]~11|dataa" - Warning (332126): Node "z80_|alu_|db[3]~11|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~35|dataa" - Warning (332126): Node "z80_|alu_control_|db[3]~35|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~34|dataa" - Warning (332126): Node "z80_|alu_control_|db[3]~34|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~35|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|dataa" - Warning (332126): Node "z80_|alu_|db[3]~11|datac" - Warning (332126): Node "z80_|bus_control_|db[3]~21|datad" - Warning (332126): Node "z80_|bus_control_|db[3]~21|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~12|datad" - Warning (332126): Node "z80_|alu_|db_low[1]~12|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~14|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~14|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~17|datad" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datad" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~10|datad" - Warning (332126): Node "z80_|alu_|db_low[3]~10|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~11|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~21|datad" - Warning (332126): Node "z80_|alu_|db_high[0]~21|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~25|datab" - Warning (332126): Node "z80_|alu_|db_high[0]~25|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~26|datac" - Warning (332126): Node "z80_|alu_|db_high[0]~26|combout" - Warning (332126): Node "z80_|alu_|db[4]~17|datac" - Warning (332126): Node "z80_|alu_|db[4]~17|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|combout" - Warning (332126): Node "z80_|alu_|db[4]~16|datad" - Warning (332126): Node "z80_|alu_|db[4]~16|combout" - Warning (332126): Node "z80_|alu_|db[4]~17|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~16|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~16|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|datab" - Warning (332126): Node "z80_|alu_|db_low[3]~7|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~24|datac" - Warning (332126): Node "z80_|alu_|db_high[0]~24|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~25|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~17|datad" - Warning (332126): Node "z80_|alu_|db_high[1]~17|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~18|datab" - Warning (332126): Node "z80_|alu_|db_high[1]~18|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~19|datad" - Warning (332126): Node "z80_|alu_|db_high[1]~19|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~20|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~20|combout" - Warning (332126): Node "z80_|alu_|db[5]~25|dataa" - Warning (332126): Node "z80_|alu_|db[5]~25|combout" - Warning (332126): Node "z80_|alu_control_|db[5]~15|datab" - Warning (332126): Node "z80_|alu_control_|db[5]~15|combout" - Warning (332126): Node "z80_|bus_control_|db[5]~15|datac" - Warning (332126): Node "z80_|bus_control_|db[5]~15|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~12|datac" - Warning (332126): Node "z80_|alu_|db_low[3]~10|dataa" - Warning (332126): Node "z80_|sw1_|db_down[5]~0|datab" - Warning (332126): Node "z80_|sw1_|db_down[5]~0|combout" - Warning (332126): Node "z80_|alu_control_|db[5]~14|dataa" - Warning (332126): Node "z80_|alu_control_|db[5]~14|combout" - Warning (332126): Node "z80_|alu_control_|db[5]~15|datad" - Warning (332126): Node "z80_|alu_|db_high[0]~21|datac" - Warning (332126): Node "z80_|alu_|db_low[0]~18|datac" - Warning (332126): Node "z80_|alu_|db_low[0]~18|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~20|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~20|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~23|datad" - Warning (332126): Node "z80_|alu_|db_high[2]~9|datac" - Warning (332126): Node "z80_|alu_|db_high[2]~9|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~13|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~13|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~14|datad" - Warning (332126): Node "z80_|alu_|db_high[2]~14|combout" - Warning (332126): Node "z80_|alu_|db[6]~23|dataa" - Warning (332126): Node "z80_|alu_|db[6]~23|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~5|datac" - Warning (332126): Node "z80_|alu_|db_high[3]~5|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~6|datab" - Warning (332126): Node "z80_|alu_|db_high[3]~6|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~7|dataa" - Warning (332126): Node "z80_|alu_|db_high[3]~7|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~8|datac" - Warning (332126): Node "z80_|alu_|db_high[3]~8|combout" - Warning (332126): Node "z80_|alu_|db[7]~21|datac" - Warning (332126): Node "z80_|alu_|db[7]~21|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~6|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~73|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~73|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~74|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~74|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~19|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~19|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~20|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~20|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|datac" - Warning (332126): Node "z80_|alu_|db[7]~20|datac" - Warning (332126): Node "z80_|alu_|db[7]~20|combout" - Warning (332126): Node "z80_|alu_|db[7]~21|dataa" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|dataa" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|combout" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|dataa" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~5|datab" - Warning (332126): Node "z80_|alu_|db_low[0]~21|datad" - Warning (332126): Node "z80_|alu_|db_high[2]~11|datad" - Warning (332126): Node "z80_|alu_|db_high[2]~11|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~12|datab" - Warning (332126): Node "z80_|alu_|db_high[2]~12|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~13|datac" - Warning (332126): Node "z80_|alu_control_|db[7]~16|datac" - Warning (332126): Node "z80_|alu_control_|db[7]~16|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~18|datad" - Warning (332126): Node "z80_|alu_control_|db[7]~18|combout" - Warning (332126): Node "z80_|bus_control_|db[7]~5|datab" - Warning (332126): Node "z80_|bus_control_|db[7]~5|combout" - Warning (332126): Node "z80_|bus_control_|db[7]~7|datad" - Warning (332126): Node "z80_|bus_control_|db[7]~7|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~17|datad" - Warning (332126): Node "z80_|alu_control_|db[7]~17|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~18|dataa" - Warning (332126): Node "z80_|alu_|db[7]~20|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~0|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~0|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~17|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|dataa" - Warning (332126): Node "z80_|alu_control_|db[6]~20|datab" - Warning (332126): Node "z80_|alu_control_|db[6]~20|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~21|datac" - Warning (332126): Node "z80_|alu_control_|db[6]~21|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~22|datab" - Warning (332126): Node "z80_|alu_control_|db[6]~22|combout" - Warning (332126): Node "z80_|bus_control_|db[6]~8|datab" - Warning (332126): Node "z80_|bus_control_|db[6]~8|combout" - Warning (332126): Node "z80_|bus_control_|db[6]~9|dataa" - Warning (332126): Node "z80_|bus_control_|db[6]~9|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~21|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|datab" - Warning (332126): Node "z80_|alu_control_|db[6]~22|datac" - Warning (332126): Node "z80_|alu_|db[6]~22|datad" - Warning (332126): Node "z80_|alu_|db[6]~22|combout" - Warning (332126): Node "z80_|alu_|db[6]~23|datac" - Warning (332126): Node "z80_|alu_|db_high[2]~12|datac" - Warning (332126): Node "z80_|alu_|db_high[1]~17|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|combout" - Warning (332126): Node "z80_|alu_|db[6]~22|datac" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~23|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~23|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|datac" - Warning (332126): Node "z80_|alu_|db_low[2]~4|datac" - Warning (332126): Node "z80_|alu_|db_low[2]~4|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~6|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~6|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~24|datac" - Warning (332126): Node "z80_|alu_|db_high[1]~15|datac" - Warning (332126): Node "z80_|alu_|db_high[1]~15|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~19|dataa" - Warning (332126): Node "z80_|alu_|db_high[3]~27|datac" - Warning (332126): Node "z80_|alu_|db_high[3]~27|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~7|datac" - Warning (332126): Node "z80_|alu_|db[5]~24|datab" - Warning (332126): Node "z80_|alu_|db[5]~24|combout" - Warning (332126): Node "z80_|alu_|db[5]~25|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~67|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~67|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|combout" - Warning (332126): Node "z80_|alu_control_|db[5]~14|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|datab" - Warning (332126): Node "z80_|alu_|db_high[0]~23|datac" - Warning (332126): Node "z80_|alu_|db_high[0]~23|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~24|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~11|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|datac" - Warning (332126): Node "z80_|alu_|db[5]~24|datac" - Warning (332126): Node "z80_|alu_|db_high[1]~18|datac" - Warning (332126): Node "z80_|alu_control_|db[4]~30|dataa" - Warning (332126): Node "z80_|alu_control_|db[4]~30|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~31|datad" - Warning (332126): Node "z80_|alu_control_|db[4]~31|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~32|datad" - Warning (332126): Node "z80_|alu_control_|db[4]~32|combout" - Warning (332126): Node "z80_|bus_control_|db[4]~19|datab" - Warning (332126): Node "z80_|bus_control_|db[4]~19|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~12|datab" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datab" - Warning (332126): Node "z80_|alu_control_|db[4]~32|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~21|datab" - Warning (332126): Node "z80_|alu_|db_low[0]~18|datab" - Warning (332126): Node "z80_|alu_|db_high[2]~9|datab" - Warning (332126): Node "z80_|alu_|db_low[2]~4|datab" - Warning (332126): Node "z80_|alu_|db_high[1]~15|datab" - Warning (332126): Node "z80_|alu_|db_high[3]~27|datab" - Warning (332126): Node "z80_|alu_|db[4]~16|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~30|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|datac" - Warning (332126): Node "z80_|alu_|db_low[0]~18|datad" - Warning (332126): Node "z80_|alu_|db_high[2]~9|datad" - Warning (332126): Node "z80_|alu_|db_low[2]~4|datad" - Warning (332126): Node "z80_|alu_|db_high[1]~15|datad" - Warning (332126): Node "z80_|alu_|db_high[3]~27|datad" - Warning (332126): Node "z80_|sw1_|db_down[3]~1|datad" - Warning (332126): Node "z80_|sw1_|db_down[3]~1|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~34|datad" - Warning (332126): Node "z80_|alu_|db_low[3]~8|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~23|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|datac" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|datac" - Warning (332126): Node "z80_|alu_|db[3]~10|datac" - Warning (332126): Node "z80_|alu_|db_low[2]~2|datab" - Warning (332126): Node "z80_|alu_control_|db[1]~24|datad" - Warning (332126): Node "z80_|alu_control_|db[1]~24|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~26|datad" - Warning (332126): Node "z80_|alu_control_|db[1]~26|combout" - Warning (332126): Node "z80_|bus_control_|db[1]~10|datab" - Warning (332126): Node "z80_|bus_control_|db[1]~10|combout" - Warning (332126): Node "z80_|bus_control_|db[1]~11|datac" - Warning (332126): Node "z80_|bus_control_|db[1]~11|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|datac" + Warning (332126): Node "z80_|bus_control_|db[2]~12|datac" + Warning (332126): Node "z80_|bus_control_|db[2]~12|combout" + Warning (332126): Node "z80_|bus_control_|db[2]~13|datac" + Warning (332126): Node "z80_|alu_|db[2]~11|datad" + Warning (332126): Node "z80_|alu_|db[2]~11|combout" + Warning (332126): Node "z80_|alu_|db[2]~12|datac" + Warning (332126): Node "z80_|alu_|db[2]~12|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~18|datad" + Warning (332126): Node "z80_|alu_|db_low[1]~18|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~19|datac" + Warning (332126): Node "z80_|alu_|db_low[1]~19|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~20|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~20|combout" + Warning (332126): Node "z80_|alu_|db[1]~16|datac" + Warning (332126): Node "z80_|alu_|db[1]~16|combout" Warning (332126): Node "z80_|alu_control_|db[1]~25|dataa" Warning (332126): Node "z80_|alu_control_|db[1]~25|combout" Warning (332126): Node "z80_|alu_control_|db[1]~26|dataa" - Warning (332126): Node "z80_|alu_|db[1]~12|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|datac" + Warning (332126): Node "z80_|alu_control_|db[1]~26|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~27|datab" + Warning (332126): Node "z80_|alu_control_|db[1]~27|combout" + Warning (332126): Node "z80_|bus_control_|db[1]~10|dataa" + Warning (332126): Node "z80_|bus_control_|db[1]~10|combout" + Warning (332126): Node "z80_|bus_control_|db[1]~11|dataa" + Warning (332126): Node "z80_|bus_control_|db[1]~11|combout" + Warning (332126): Node "z80_|sw1_|db_down[1]~2|dataa" + Warning (332126): Node "z80_|sw1_|db_down[1]~2|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~27|datad" + Warning (332126): Node "z80_|alu_|db[1]~15|dataa" + Warning (332126): Node "z80_|alu_|db[1]~15|combout" + Warning (332126): Node "z80_|alu_|db[1]~16|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~1|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~1|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~25|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|dataa" + Warning (332126): Node "z80_|alu_control_|db[1]~26|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|datab" Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|combout" Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|datad" Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|datad" Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~19|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~21|datac" + Warning (332126): Node "z80_|alu_|db_low[0]~21|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~22|datad" + Warning (332126): Node "z80_|alu_|db_low[0]~22|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~27|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~27|combout" + Warning (332126): Node "z80_|alu_|db[0]~17|datac" + Warning (332126): Node "z80_|alu_|db[0]~17|combout" + Warning (332126): Node "z80_|alu_|db[0]~18|datab" + Warning (332126): Node "z80_|alu_|db[0]~18|combout" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|dataa" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|combout" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|datac" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~21|datad" + Warning (332126): Node "z80_|alu_|db_high[3]~2|datad" + Warning (332126): Node "z80_|alu_|db_high[3]~2|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~3|datac" + Warning (332126): Node "z80_|alu_|db_high[3]~3|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~6|datab" + Warning (332126): Node "z80_|alu_|db_high[3]~6|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~7|datad" + Warning (332126): Node "z80_|alu_|db_high[3]~7|combout" + Warning (332126): Node "z80_|alu_|db[7]~20|datad" + Warning (332126): Node "z80_|alu_|db[7]~20|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~3|datab" Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|datac" - Warning (332126): Node "z80_|alu_|db_low[0]~22|datac" + Warning (332126): Node "z80_|alu_|db_high[2]~8|datab" + Warning (332126): Node "z80_|alu_|db_high[2]~8|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~9|datad" + Warning (332126): Node "z80_|alu_|db_high[2]~9|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~12|datac" + Warning (332126): Node "z80_|alu_|db_high[2]~12|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~13|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~13|combout" + Warning (332126): Node "z80_|alu_|db[6]~22|datac" + Warning (332126): Node "z80_|alu_|db[6]~22|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~2|datac" + Warning (332126): Node "z80_|alu_|db_high[1]~16|datac" + Warning (332126): Node "z80_|alu_|db_high[1]~16|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~17|datad" + Warning (332126): Node "z80_|alu_|db_high[1]~17|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~18|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~18|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~19|datac" + Warning (332126): Node "z80_|alu_|db_high[1]~19|combout" + Warning (332126): Node "z80_|alu_|db[5]~24|dataa" + Warning (332126): Node "z80_|alu_|db[5]~24|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~17|datab" + Warning (332126): Node "z80_|alu_|db_high[2]~8|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~80|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~80|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~82|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~82|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~83|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~83|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~84|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~84|combout" + Warning (332126): Node "z80_|alu_|db[5]~23|dataa" + Warning (332126): Node "z80_|alu_|db[5]~23|combout" + Warning (332126): Node "z80_|alu_|db[5]~24|datac" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~22|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~22|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~23|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~23|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~24|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~24|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~84|dataa" + Warning (332126): Node "z80_|alu_control_|db[5]~17|datad" + Warning (332126): Node "z80_|alu_control_|db[5]~17|combout" + Warning (332126): Node "z80_|bus_control_|db[5]~15|dataa" + Warning (332126): Node "z80_|bus_control_|db[5]~15|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~14|datad" + Warning (332126): Node "z80_|alu_|db_high[1]~14|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~18|datac" + Warning (332126): Node "z80_|alu_|db_low[1]~15|datad" + Warning (332126): Node "z80_|alu_|db_low[1]~15|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~17|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~17|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~20|datad" + Warning (332126): Node "z80_|sw1_|db_down[5]~0|datac" + Warning (332126): Node "z80_|sw1_|db_down[5]~0|combout" + Warning (332126): Node "z80_|alu_control_|db[5]~16|dataa" + Warning (332126): Node "z80_|alu_control_|db[5]~16|combout" + Warning (332126): Node "z80_|alu_control_|db[5]~17|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~11|datab" + Warning (332126): Node "z80_|alu_|db_high[2]~11|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~12|datad" + Warning (332126): Node "z80_|alu_|db_low[3]~7|datab" + Warning (332126): Node "z80_|alu_|db_low[3]~7|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~8|datad" + Warning (332126): Node "z80_|alu_|db_low[3]~8|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~26|datad" + Warning (332126): Node "z80_|alu_|db_low[3]~26|combout" + Warning (332126): Node "z80_|alu_|db[3]~13|dataa" + Warning (332126): Node "z80_|alu_|db[3]~13|combout" + Warning (332126): Node "z80_|alu_|db[3]~14|datab" + Warning (332126): Node "z80_|alu_|db[3]~14|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~36|dataa" + Warning (332126): Node "z80_|alu_control_|db[3]~36|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~45|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~45|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~49|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~49|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|datad" + Warning (332126): Node "z80_|alu_control_|db[3]~35|datad" + Warning (332126): Node "z80_|alu_control_|db[3]~35|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~36|datad" + Warning (332126): Node "z80_|alu_|db[3]~14|datad" + Warning (332126): Node "z80_|bus_control_|db[3]~21|datac" + Warning (332126): Node "z80_|bus_control_|db[3]~21|combout" + Warning (332126): Node "z80_|sw1_|db_down[3]~3|datab" + Warning (332126): Node "z80_|sw1_|db_down[3]~3|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~35|datac" + Warning (332126): Node "z80_|alu_|db_high[1]~14|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~15|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~11|dataa" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|dataa" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~13|datad" + Warning (332126): Node "z80_|alu_|db_low[2]~13|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~14|datad" + Warning (332126): Node "z80_|alu_|db_low[2]~14|combout" + Warning (332126): Node "z80_|alu_|db[2]~12|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~20|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~20|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~24|datad" + Warning (332126): Node "z80_|alu_|db_high[0]~24|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~25|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~25|combout" + Warning (332126): Node "z80_|alu_|db[4]~10|datad" + Warning (332126): Node "z80_|alu_|db[4]~10|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~31|datad" + Warning (332126): Node "z80_|alu_control_|db[4]~31|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~32|datac" + Warning (332126): Node "z80_|alu_control_|db[4]~32|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~33|datad" + Warning (332126): Node "z80_|alu_control_|db[4]~33|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~53|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~53|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~60|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~60|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~31|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|datac" + Warning (332126): Node "z80_|alu_|db[4]~8|datac" + Warning (332126): Node "z80_|alu_|db[4]~8|combout" + Warning (332126): Node "z80_|alu_|db[4]~10|datac" + Warning (332126): Node "z80_|bus_control_|db[4]~19|datac" + Warning (332126): Node "z80_|bus_control_|db[4]~19|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~33|datac" + Warning (332126): Node "z80_|alu_|db_high[1]~14|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~15|datab" + Warning (332126): Node "z80_|alu_|db_high[2]~11|datad" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|datad" + Warning (332126): Node "z80_|alu_|db_high[0]~20|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~23|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~23|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~25|datad" + Warning (332126): Node "z80_|alu_|db_low[0]~25|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~27|datac" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datad" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~7|datad" + Warning (332126): Node "z80_|alu_|db_high[3]~5|datad" + Warning (332126): Node "z80_|alu_|db_high[3]~5|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~6|datad" + Warning (332126): Node "z80_|alu_|db_high[1]~16|datad" + Warning (332126): Node "z80_|alu_|db_high[0]~23|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~23|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~24|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~53|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~53|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~55|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~55|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~56|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~56|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~57|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~57|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~13|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~13|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~14|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~14|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~15|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~15|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~57|datac" + Warning (332126): Node "z80_|alu_|db[4]~8|datad" + Warning (332126): Node "z80_|alu_|db_low[3]~4|datad" + Warning (332126): Node "z80_|alu_|db_low[3]~4|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~5|datad" + Warning (332126): Node "z80_|alu_|db_low[3]~5|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~8|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~23|dataa" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|dataa" + Warning (332126): Node "z80_|alu_|db_high[3]~5|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~22|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~22|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~23|datad" + Warning (332126): Node "z80_|alu_|db_low[3]~5|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~35|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~35|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~37|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~37|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~38|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~38|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~39|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~39|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~7|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~7|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~8|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~8|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~9|datac" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~9|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~39|datac" + Warning (332126): Node "z80_|alu_|db[3]~13|datac" + Warning (332126): Node "z80_|alu_|db_low[2]~9|datad" + Warning (332126): Node "z80_|alu_|db_low[2]~9|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~10|datad" + Warning (332126): Node "z80_|alu_|db_low[2]~10|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~14|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~13|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~20|datad" + Warning (332126): Node "z80_|alu_|db_low[0]~23|datad" + Warning (332126): Node "z80_|alu_|db_high[3]~5|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~65|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~65|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~69|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~69|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|combout" + Warning (332126): Node "z80_|alu_control_|db[5]~16|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|datab" + Warning (332126): Node "z80_|alu_|db[5]~23|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~22|datad" + Warning (332126): Node "z80_|alu_|db_high[2]~9|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~71|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~71|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~73|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~73|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~74|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~74|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~19|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~19|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~20|datac" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~20|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~21|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~21|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~75|datac" + Warning (332126): Node "z80_|alu_|db[6]~21|datac" + Warning (332126): Node "z80_|alu_|db[6]~21|combout" + Warning (332126): Node "z80_|alu_|db[6]~22|datad" + Warning (332126): Node "z80_|alu_control_|db[6]~22|datac" + Warning (332126): Node "z80_|alu_control_|db[6]~22|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~23|datab" + Warning (332126): Node "z80_|alu_control_|db[6]~23|combout" + Warning (332126): Node "z80_|bus_control_|db[6]~8|datad" + Warning (332126): Node "z80_|bus_control_|db[6]~8|combout" + Warning (332126): Node "z80_|bus_control_|db[6]~9|dataa" + Warning (332126): Node "z80_|bus_control_|db[6]~9|combout" + Warning (332126): Node "z80_|sw1_|db_down[6]~1|datac" + Warning (332126): Node "z80_|sw1_|db_down[6]~1|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~23|datad" + Warning (332126): Node "z80_|alu_|db[6]~21|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~77|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~77|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~78|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~78|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~0|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~0|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~23|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~62|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~62|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~64|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~64|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~65|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~65|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~66|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~66|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~16|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~16|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~17|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~17|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~18|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~18|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~66|datad" + Warning (332126): Node "z80_|alu_|db[7]~19|dataa" + Warning (332126): Node "z80_|alu_|db[7]~19|combout" + Warning (332126): Node "z80_|alu_|db[7]~20|datac" + Warning (332126): Node "z80_|alu_control_|db[7]~18|dataa" + Warning (332126): Node "z80_|alu_control_|db[7]~18|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~19|datad" + Warning (332126): Node "z80_|alu_control_|db[7]~19|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~20|datad" + Warning (332126): Node "z80_|alu_control_|db[7]~20|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~37|datad" + Warning (332126): Node "z80_|alu_control_|db[7]~37|combout" + Warning (332126): Node "z80_|bus_control_|db[7]~5|datab" + Warning (332126): Node "z80_|bus_control_|db[7]~5|combout" + Warning (332126): Node "z80_|bus_control_|db[7]~7|dataa" + Warning (332126): Node "z80_|bus_control_|db[7]~7|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~20|datab" + Warning (332126): Node "z80_|alu_|db[7]~19|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~87|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~87|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~88|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~88|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~19|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|datab" + Warning (332126): Node "z80_|sw2_|db_up[0]~0|dataa" + Warning (332126): Node "z80_|sw2_|db_up[0]~0|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~11|datad" + Warning (332126): Node "z80_|alu_control_|db[0]~11|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~14|dataa" + Warning (332126): Node "z80_|alu_control_|db[0]~14|combout" + Warning (332126): Node "z80_|bus_control_|db[0]~17|datab" + Warning (332126): Node "z80_|bus_control_|db[0]~17|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~10|datad" + Warning (332126): Node "z80_|alu_control_|db[0]~10|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~11|dataa" + Warning (332126): Node "z80_|alu_|db[0]~18|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|combout" + Warning (332126): Node "z80_|alu_control_|db[0]~11|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~18|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~22|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|dataa" - Warning (332126): Node "z80_|alu_|db[0]~18|datac" - Warning (332126): Node "z80_|sw2_|db_up[0]~0|datad" - Warning (332126): Node "z80_|sw2_|db_up[0]~0|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~9|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|dataa" -Critical Warning (332081): Design contains combinational loop of 511 nodes. Estimating the delays through the loop. + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|combout" + Warning (332126): Node "z80_|alu_|db[0]~17|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|datac" + Warning (332126): Node "z80_|alu_|db_low[2]~9|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|combout" + Warning (332126): Node "z80_|alu_|db[1]~15|datac" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datad" + Warning (332126): Node "z80_|alu_|db_low[2]~10|datac" + Warning (332126): Node "z80_|alu_control_|db[2]~28|dataa" + Warning (332126): Node "z80_|alu_control_|db[2]~28|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~30|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~44|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~44|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~46|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~46|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~47|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~47|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|combout" + Warning (332126): Node "z80_|alu_|db[2]~11|datac" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~10|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~10|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~11|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~11|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~12|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~48|datad" + Warning (332126): Node "z80_|alu_|db_low[3]~4|datac" +Critical Warning (332081): Design contains combinational loop of 513 nodes. Estimating the delays through the loop. Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment. Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment. Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. @@ -39730,34 +55893,37 @@ Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1200mV 85C Model Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -18.123 +Info (332146): Worst-case setup slack is -18.571 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -18.123 -549.338 CLOCK_50 - Info (332119): -7.533 -284.813 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] - Info (332119): -4.740 -42.810 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - Info (332119): -2.914 -2.914 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Info (332146): Worst-case hold slack is 0.210 + Info (332119): -18.571 -821.372 CLOCK_50 + Info (332119): -7.747 -287.138 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): -4.731 -41.432 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): -2.915 -2.915 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + Info (332119): 3.503 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case hold slack is 0.342 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.210 0.000 CLOCK_50 Info (332119): 0.342 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] - Info (332119): 0.344 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 0.342 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332119): 0.357 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Info (332146): Worst-case recovery slack is -6.223 + Info (332119): 0.359 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.373 0.000 CLOCK_50 +Info (332146): Worst-case recovery slack is -6.212 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -6.223 -459.348 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Info (332146): Worst-case removal slack is 3.698 + Info (332119): -6.212 -460.730 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case removal slack is 3.666 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 3.698 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Info (332146): Worst-case minimum pulse width slack is 9.488 + Info (332119): 3.666 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case minimum pulse width slack is 4.752 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== + Info (332119): 4.752 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Info (332119): 9.488 0.000 CLOCK_50 Info (332119): 19.602 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] - Info (332119): 20.595 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 20.597 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332119): 35.503 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Info: Analyzing Slow 1200mV 0C Model Info (334003): Started post-fitting delay annotation @@ -39767,33 +55933,36 @@ Warning (332060): Node: KEY[1] was determined to be a clock but was found withou Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -17.311 +Info (332146): Worst-case setup slack is -17.727 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -17.311 -526.609 CLOCK_50 - Info (332119): -6.686 -253.661 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] - Info (332119): -4.428 -40.009 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - Info (332119): -2.785 -2.785 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + Info (332119): -17.727 -781.205 CLOCK_50 + Info (332119): -6.896 -255.894 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): -4.422 -38.759 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): -2.786 -2.786 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] + Info (332119): 4.148 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Info (332146): Worst-case hold slack is 0.298 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.298 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] - Info (332119): 0.300 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - Info (332119): 0.304 0.000 CLOCK_50 + Info (332119): 0.298 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332119): 0.311 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Info (332146): Worst-case recovery slack is -5.744 + Info (332119): 0.312 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.339 0.000 CLOCK_50 +Info (332146): Worst-case recovery slack is -5.735 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -5.744 -423.582 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Info (332146): Worst-case removal slack is 3.374 + Info (332119): -5.735 -424.927 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case removal slack is 3.339 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 3.374 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Info (332146): Worst-case minimum pulse width slack is 9.489 + Info (332119): 3.339 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case minimum pulse width slack is 4.748 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== + Info (332119): 4.748 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Info (332119): 9.489 0.000 CLOCK_50 - Info (332119): 19.600 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 19.596 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Info (332119): 20.591 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332119): 35.491 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Info: Analyzing Fast 1200mV 0C Model @@ -39802,40 +55971,43 @@ Warning (332060): Node: KEY[1] was determined to be a clock but was found withou Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -14.971 +Info (332146): Worst-case setup slack is -15.243 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -14.971 -442.545 CLOCK_50 - Info (332119): -4.979 -171.124 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] - Info (332119): -3.775 -35.541 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): -15.243 -641.328 CLOCK_50 + Info (332119): -4.921 -171.346 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): -3.770 -34.841 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332119): -2.784 -2.784 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Info (332146): Worst-case hold slack is -0.053 + Info (332119): 6.261 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case hold slack is 0.098 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -0.053 -0.089 CLOCK_50 + Info (332119): 0.098 0.000 CLOCK_50 Info (332119): 0.177 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] - Info (332119): 0.178 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 0.177 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 0.186 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Info (332119): 0.186 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Info (332146): Worst-case recovery slack is -4.693 +Info (332146): Worst-case recovery slack is -4.684 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -4.693 -358.284 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Info (332146): Worst-case removal slack is 2.518 + Info (332119): -4.684 -358.844 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case removal slack is 2.507 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 2.518 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Info (332146): Worst-case minimum pulse width slack is 9.208 + Info (332119): 2.507 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case minimum pulse width slack is 4.783 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== + Info (332119): 4.783 0.000 sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0] Info (332119): 9.208 0.000 CLOCK_50 Info (332119): 19.609 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Info (332119): 20.600 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332119): 35.535 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements -Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 532 warnings - Info: Peak virtual memory: 437 megabytes - Info: Processing ended: Fri Apr 1 18:55:48 2022 +Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 534 warnings + Info: Peak virtual memory: 445 megabytes + Info: Processing ended: Sat Apr 2 14:51:17 2022 Info: Elapsed time: 00:00:04 Info: Total CPU time (on all processors): 00:00:04 diff --git a/output_files/spectrum.sta.summary b/output_files/spectrum.sta.summary index 337cec4..895d966 100644 --- a/output_files/spectrum.sta.summary +++ b/output_files/spectrum.sta.summary @@ -3,23 +3,23 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ Type : Slow 1200mV 85C Model Setup 'CLOCK_50' -Slack : -18.123 -TNS : -549.338 +Slack : -18.571 +TNS : -821.372 Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' -Slack : -7.533 -TNS : -284.813 +Slack : -7.747 +TNS : -287.138 Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : -4.740 -TNS : -42.810 +Slack : -4.731 +TNS : -41.432 Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' -Slack : -2.914 -TNS : -2.914 +Slack : -2.915 +TNS : -2.915 -Type : Slow 1200mV 85C Model Hold 'CLOCK_50' -Slack : 0.210 +Type : Slow 1200mV 85C Model Setup 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 3.503 TNS : 0.000 Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' @@ -27,19 +27,31 @@ Slack : 0.342 TNS : 0.000 Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 0.344 +Slack : 0.342 TNS : 0.000 Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' Slack : 0.357 TNS : 0.000 +Type : Slow 1200mV 85C Model Hold 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 0.359 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Hold 'CLOCK_50' +Slack : 0.373 +TNS : 0.000 + Type : Slow 1200mV 85C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : -6.223 -TNS : -459.348 +Slack : -6.212 +TNS : -460.730 Type : Slow 1200mV 85C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 3.698 +Slack : 3.666 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 4.752 TNS : 0.000 Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50' @@ -51,7 +63,7 @@ Slack : 19.602 TNS : 0.000 Type : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 20.595 +Slack : 20.597 TNS : 0.000 Type : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' @@ -59,43 +71,55 @@ Slack : 35.503 TNS : 0.000 Type : Slow 1200mV 0C Model Setup 'CLOCK_50' -Slack : -17.311 -TNS : -526.609 +Slack : -17.727 +TNS : -781.205 Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' -Slack : -6.686 -TNS : -253.661 +Slack : -6.896 +TNS : -255.894 Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : -4.428 -TNS : -40.009 +Slack : -4.422 +TNS : -38.759 Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' -Slack : -2.785 -TNS : -2.785 +Slack : -2.786 +TNS : -2.786 + +Type : Slow 1200mV 0C Model Setup 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 4.148 +TNS : 0.000 Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' Slack : 0.298 TNS : 0.000 Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 0.300 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Hold 'CLOCK_50' -Slack : 0.304 +Slack : 0.298 TNS : 0.000 Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' Slack : 0.311 TNS : 0.000 +Type : Slow 1200mV 0C Model Hold 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 0.312 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Hold 'CLOCK_50' +Slack : 0.339 +TNS : 0.000 + Type : Slow 1200mV 0C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : -5.744 -TNS : -423.582 +Slack : -5.735 +TNS : -424.927 Type : Slow 1200mV 0C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 3.374 +Slack : 3.339 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 4.748 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' @@ -103,7 +127,7 @@ Slack : 9.489 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' -Slack : 19.600 +Slack : 19.596 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' @@ -115,31 +139,39 @@ Slack : 35.491 TNS : 0.000 Type : Fast 1200mV 0C Model Setup 'CLOCK_50' -Slack : -14.971 -TNS : -442.545 +Slack : -15.243 +TNS : -641.328 Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' -Slack : -4.979 -TNS : -171.124 +Slack : -4.921 +TNS : -171.346 Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : -3.775 -TNS : -35.541 +Slack : -3.770 +TNS : -34.841 Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' Slack : -2.784 TNS : -2.784 +Type : Fast 1200mV 0C Model Setup 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 6.261 +TNS : 0.000 + Type : Fast 1200mV 0C Model Hold 'CLOCK_50' -Slack : -0.053 -TNS : -0.089 +Slack : 0.098 +TNS : 0.000 Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' Slack : 0.177 TNS : 0.000 Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 0.178 +Slack : 0.177 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Hold 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 0.186 TNS : 0.000 Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' @@ -147,11 +179,15 @@ Slack : 0.186 TNS : 0.000 Type : Fast 1200mV 0C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : -4.693 -TNS : -358.284 +Slack : -4.684 +TNS : -358.844 Type : Fast 1200mV 0C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 2.518 +Slack : 2.507 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 4.783 TNS : 0.000 Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' diff --git a/sdram.v.bak b/sdram.v.bak new file mode 100644 index 0000000..e69de29 diff --git a/sdram.vhdl b/sdram.vhdl new file mode 100644 index 0000000..df34a75 --- /dev/null +++ b/sdram.vhdl @@ -0,0 +1,510 @@ +------------------------------------------------------ +-- FSM for a SDRAM controller +-- +-- Version 0.1 - Ready to simulate +-- +-- Author: Mike Field (hamster@snap.net.nz) +-- +-- Feel free to use it however you would like, but +-- just drop me an email to say thanks. +------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity sdram_controller is + PORT ( + CLOCK_50 : IN STD_LOGIC; + + -- Signals to/from the SDRAM chip + DRAM_ADDR : OUT STD_LOGIC_VECTOR (12 downto 0); + DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0); + DRAM_CAS_N : OUT STD_LOGIC; + DRAM_CKE : OUT STD_LOGIC; + DRAM_CLK : OUT STD_LOGIC; + DRAM_CS_N : OUT STD_LOGIC; + DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0); + DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0); + DRAM_RAS_N : OUT STD_LOGIC; + DRAM_WE_N : OUT STD_LOGIC; + + --- Inputs from rest of the system + address : IN STD_LOGIC_VECTOR (23 downto 0); + req_read : IN STD_LOGIC; + req_write : IN STD_LOGIC; + data_out : OUT STD_LOGIC_VECTOR (31 downto 0); + data_out_valid : OUT STD_LOGIC; + data_in : IN STD_LOGIC_VECTOR (31 downto 0) + ); +end entity; + + +architecture rtl of sdram_controller is + + + type reg is record + state : std_logic_vector(8 downto 0); + + address : std_logic_vector(12 downto 0); + bank : std_logic_vector( 1 downto 0); + + init_counter: std_logic_vector(14 downto 0); + rf_counter : std_logic_vector( 9 downto 0); + rf_pending : std_logic; + + rd_pending : std_logic; + wr_pending : std_logic; + act_row : std_logic_vector(12 downto 0); + + data_out_low: std_logic_vector(15 downto 0); + data_out_valid : std_logic; + + dq_masks : std_logic_vector(1 downto 0); + end record; + component sdram_clk_gen + PORT + ( + inclk0: IN STD_LOGIC; + c0 : OUT STD_LOGIC; + c1 : OUT STD_LOGIC + ); + end component; + + -- note to self - this constant should be "(others => '0')" when not simulating!!! + signal r : reg := ((others => '0'), (others => '0'), + (others => '0'), "000000000001000", (others => '0'), + '0', '0', '0', (others => '0'), (others => '0'), '0', (others => '0')); + signal n : reg; + + -- Vectors for each SDRAM 'command' + --- CS_N, RAS_N, CAS_N, WE_N + constant cmd_nop : std_logic_vector(3 downto 0) := "0111"; + constant cmd_read : std_logic_vector(3 downto 0) := "0101"; -- Must be sure A10 is low. + constant cmd_write : std_logic_vector(3 downto 0) := "0100"; + constant cmd_act : std_logic_vector(3 downto 0) := "0011"; + constant cmd_pre : std_logic_vector(3 downto 0) := "0010"; -- Must set A10 to '1'. + constant cmd_ref : std_logic_vector(3 downto 0) := "0001"; + constant cmd_mrs : std_logic_vector(3 downto 0) := "0000"; -- Mode register set + -- State assignments + constant s_init_nop : std_logic_vector(8 downto 0) := "00000" & cmd_nop; + constant s_init_pre : std_logic_vector(8 downto 0) := "00000" & cmd_pre; + constant s_init_ref : std_logic_vector(8 downto 0) := "00000" & cmd_ref; + constant s_init_mrs : std_logic_vector(8 downto 0) := "00000" & cmd_mrs; + + constant s_idle : std_logic_vector(8 downto 0) := "00001" & cmd_nop; + + constant s_rf0 : std_logic_vector(8 downto 0) := "00010" & cmd_ref; + constant s_rf1 : std_logic_vector(8 downto 0) := "00011" & cmd_nop; + constant s_rf2 : std_logic_vector(8 downto 0) := "00100" & cmd_nop; + constant s_rf3 : std_logic_vector(8 downto 0) := "00101" & cmd_nop; + constant s_rf4 : std_logic_vector(8 downto 0) := "00110" & cmd_nop; + constant s_rf5 : std_logic_vector(8 downto 0) := "00111" & cmd_nop; + + constant s_ra0 : std_logic_vector(8 downto 0) := "01000" & cmd_act; + constant s_ra1 : std_logic_vector(8 downto 0) := "01001" & cmd_nop; + constant s_ra2 : std_logic_vector(8 downto 0) := "01010" & cmd_nop; + + constant s_dr0 : std_logic_vector(8 downto 0) := "01011" & cmd_pre; + constant s_dr1 : std_logic_vector(8 downto 0) := "01100" & cmd_nop; + + constant s_wr0 : std_logic_vector(8 downto 0) := "01101" & cmd_write; + constant s_wr1 : std_logic_vector(8 downto 0) := "01110" & cmd_nop; + constant s_wr2 : std_logic_vector(8 downto 0) := "01111" & cmd_nop; + constant s_wr3 : std_logic_vector(8 downto 0) := "10000" & cmd_nop; + + constant s_rd0 : std_logic_vector(8 downto 0) := "10001" & cmd_read; + constant s_rd1 : std_logic_vector(8 downto 0) := "10010" & cmd_nop; + constant s_rd2 : std_logic_vector(8 downto 0) := "10011" & cmd_nop; + constant s_rd3 : std_logic_vector(8 downto 0) := "10100" & cmd_nop; + constant s_rd4 : std_logic_vector(8 downto 0) := "10101" & cmd_read; + constant s_rd5 : std_logic_vector(8 downto 0) := "10110" & cmd_nop; + constant s_rd6 : std_logic_vector(8 downto 0) := "10111" & cmd_nop; + constant s_rd7 : std_logic_vector(8 downto 0) := "11000" & cmd_nop; + constant s_rd8 : std_logic_vector(8 downto 0) := "11001" & cmd_nop; + constant s_rd9 : std_logic_vector(8 downto 0) := "11011" & cmd_nop; + + constant s_drdr0 : std_logic_vector(8 downto 0) := "11101" & cmd_pre; + constant s_drdr1 : std_logic_vector(8 downto 0) := "11110" & cmd_nop; + constant s_drdr2 : std_logic_vector(8 downto 0) := "11111" & cmd_nop; + + signal addr_row : std_logic_vector(12 downto 0); + signal addr_bank: std_logic_vector(1 downto 0); + signal addr_col : std_logic_vector(9 downto 0); + + signal captured : std_logic_vector(15 downto 0); + + signal clock_100 : std_logic; + signal clock_100_delayed_3ns : std_logic; +begin + -- Addressing is in 32 bit words - twice that of the DRAM width, + -- so each burst of four access two system words. + addr_row <= address(23 downto 11); + addr_bank <= address(10 downto 9); + addr_col <= address(8 downto 1) & "00"; + +sdram_clk_pll: sdram_clk_gen + + -- Generate the 100MHz clock and the same phase shifted by 3ns + PORT MAP + ( + inclk0 => CLOCK_50, + c0 => clock_100, + c1 => clock_100_delayed_3ns + ); + + DRAM_CLK <= clock_100_delayed_3ns; + DRAM_CKE <= '1'; + DRAM_CS_N <= r.state(3); + DRAM_RAS_N <= r.state(2); + DRAM_CAS_N <= r.state(1); + DRAM_WE_N <= r.state(0); + DRAM_ADDR <= r.address; + DRAM_BA <= r.bank; + DATA_OUT <= captured & r.data_out_low; + DRAM_DQM <= r.dq_masks; + data_out_valid <= r.data_out_valid; + + process (r, address, req_read, req_write, addr_row, addr_bank, addr_col, data_in, captured) + begin + -- copy the existing values + n <= r; + if req_read = '1' then + n.rd_pending <= '1'; + end if; + + if req_write = '1' then + n.wr_pending <= '1'; + end if; + + n.dq_masks <= "11"; + + -- first off, do we need to perform a refresh cycle ASAP? + if r.rf_counter = 770 then -- 781 = 64,000,000ns / 8192 / 10ns + n.rf_counter <= (others => '0'); + n.rf_pending <= '1'; + else + -- only start looking for refreshes outside of the initialisation state. + if not(r.state(8 downto 4) = s_init_nop(8 downto 4)) then + n.rf_counter <= r.rf_counter + 1; + end if; + end if; + + -- Set the data bus into HIZ, high and low bytes masked + DRAM_DQ <= (others => 'Z'); + + n.init_counter <= r.init_counter-1; + + -- Process the FSM + case r.state(8 downto 4) is + when s_init_nop(8 downto 4) => + n.state <= s_init_nop; + n.address <= (others => '0'); + n.bank <= (others => '0'); + n.rf_counter <= (others => '0'); + n.data_out_valid <= '1'; + + -- T-130, precharge all banks. + if r.init_counter = "000000010000010" then + n.state <= s_init_pre; + n.address(10) <= '1'; + end if; + + -- T-127, T-111, T-95, T-79, T-63, T-47, T-31, T-15, the 8 refreshes + + if r.init_counter(14 downto 7) = 0 and r.init_counter(3 downto 0) = 15 then + n.state <= s_init_ref; + end if; + + -- T-3, the load mode register + if r.init_counter = 3 then + n.state <= s_init_mrs; + -- Mode register is as follows: + -- resvd wr_b OpMd CAS=3 Seq bust=4 + n.address <= "000" & "0" & "00" & "011" & "0" & "010"; + -- resvd + n.bank <= "00"; + end if; + + + -- T-1 The switch to the FSM (first command will be a NOP + if r.init_counter = 1 then + n.state <= s_idle; + end if; + + ------------------------------ + -- The Idle section + ------------------------------ + when s_idle(8 downto 4) => + n.state <= s_idle; + + -- do we have to activate a row? + if r.rd_pending = '1' or r.wr_pending = '1' then + n.state <= s_ra0; + n.address <= addr_row; + n.act_row <= addr_row; + end if; + + -- refreshes take priority over everything + if r.rf_pending = '1' then + n.state <= s_rf0; + n.rf_pending <= '0'; + end if; + ------------------------------ + -- Row activation + -- s_ra2 is also the "idle with active row" state and provides + -- a resting point between operations on the same row + ------------------------------ + when s_ra0(8 downto 4) => + n.state <= s_ra1; + when s_ra1(8 downto 4) => + n.state <= s_ra2; + when s_ra2(8 downto 4) => + -- we can stay in this state until we have something to do + n.state <= s_ra2; + + -- If there is a read pending, deactivate the row + if r.rd_pending = '1' or r.wr_pending = '1' then + n.state <= s_dr0; + n.address(10) <= '1'; + end if; + + -- unless we have a read to perform on the same row? do that instead + if r.rd_pending = '1' and r.act_row = addr_row then + n.state <= s_rd0; + n.address <= "000" & addr_col; + n.bank <= addr_bank; + n.dq_masks <= "00"; + n.rd_pending <= '0'; + end if; + + -- unless we have a write on the same row? writes take priroty over reads + if r.wr_pending = '1' and r.act_row = addr_row then + n.state <= s_wr0; + n.address <= "000" & addr_col; + n.bank <= addr_bank; + n.dq_masks<= "00"; + n.wr_pending <= '0'; + end if; + + -- But refreshes take piority over everything! + if r.rf_pending = '1' then + n.state <= s_dr0; + n.address(10) <= '1'; + end if; + + ------------------------------------------------------ + -- Deactivate the current row and return to idle state + ------------------------------------------------------ + when s_dr0(8 downto 4) => + n.state <= s_dr1; + when s_dr1(8 downto 4) => + n.state <= s_idle; + + ------------------------------ + -- The Refresh section + ------------------------------ + when s_rf0(8 downto 4) => + n.state <= s_rf1; + when s_rf1(8 downto 4) => + n.state <= s_rf2; + when s_rf2(8 downto 4) => + n.state <= s_rf3; + when s_rf3(8 downto 4) => + n.state <= s_rf4; + when s_rf4(8 downto 4) => + n.state <= s_rf5; + when s_rf5(8 downto 4) => + n.state <= s_idle; + ------------------------------ + -- The Write section + ------------------------------ + when s_wr0(8 downto 4) => + n.state <= s_wr1; + n.address <= "000" & addr_col; + n.bank <= addr_bank; + DRAM_DQ <= data_in(15 downto 0); + n.dq_masks<= "00"; + when s_wr1(8 downto 4) => + n.state <= s_wr2; + DRAM_DQ <= data_in(31 downto 16); + n.dq_masks<= "00"; + when s_wr2(8 downto 4) => + DRAM_DQ <= data_in(15 downto 0); + n.state <= s_wr3; + n.dq_masks<= "00"; + when s_wr3(8 downto 4) => + -- Default to the idle+row active state + n.state <= s_ra2; + DRAM_DQ <= data_in(31 downto 16); + n.dq_masks<= "11"; + + -- If there is a read or write then deactivate the row + if r.rd_pending = '1' or r.wr_pending = '1' then + n.state <= s_dr0; + n.address(10) <= '1'; + end if; + + -- But if there is a read pending in the same row, do that + if r.rd_pending = '1' and r.act_row = addr_row then + n.state <= s_rd0; + n.address <= "000" & addr_col; + n.bank <= addr_bank; + n.dq_masks <= "00"; + n.rd_pending <= '0'; + end if; + + -- unless there is a write pending in the same row, do that + if r.wr_pending = '1' and r.act_row = addr_row then + n.state <= s_wr0; + n.address <= "000" & addr_col; + n.bank <= addr_bank; + n.dq_masks<= "00"; + n.wr_pending <= '0'; + end if; + + -- But always try and refresh if one is pending! + if r.rf_pending = '1' then + n.state <= s_dr0; + n.address(10) <= '1'; + end if; + + ------------------------------ + -- The Read section + ------------------------------ + when s_rd0(8 downto 4) => + n.state <= s_rd1; + n.dq_masks <= "00"; + when s_rd1(8 downto 4) => + n.state <= s_rd2; + n.dq_masks <= "00"; + when s_rd2(8 downto 4) => + n.state <= s_rd3; + n.dq_masks <= "00"; + when s_rd3(8 downto 4) => + -- default is to end the read with the row open + n.state <= s_rd7; + + -- otherwise if there is a read or write prepare to deactivate the row. + -- (This is overridden if the read/write is to the same page) + if r.rd_pending = '1' or r.wr_pending = '1' then + n.state <= s_drdr0; + n.address(10) <= '1'; + end if; + + -- override if the write is from the same row + if r.wr_pending = '1' and r.act_row = addr_row then + n.state <= s_rd7; + end if; + + -- override if the read is from the same row + if r.rd_pending = '1' and r.act_row = addr_row then + n.state <= s_rd4; + n.address <= "000" & addr_col; + n.bank <= addr_bank; + n.dq_masks<= "00"; + end if; + + -- If a refresh is pending then always deactivate the row + if r.rf_pending = '1' then + n.state <= s_drdr0; + n.address(10) <= '1'; + end if; + n.data_out_low <= captured; + n.data_out_valid <= '1'; + when s_rd4(8 downto 4) => + n.state <= s_rd5; + n.dq_masks<= "00"; + when s_rd5(8 downto 4) => + n.state <= s_rd6; + n.data_out_low <= captured; + n.data_out_valid <= '1'; + n.dq_masks<= "00"; + when s_rd6(8 downto 4) => + n.state <= s_rd3; + n.dq_masks<= "00"; + when s_rd7(8 downto 4) => + n.state <= s_rd8; + n.data_out_low <= captured; + n.data_out_valid <= '1'; + when s_rd8(8 downto 4) => + n.state <= s_rd9; + when s_rd9(8 downto 4) => + -- by default go to the idle-with-row-active state + n.state <= s_ra2; + n.data_out_low <= captured; + n.data_out_valid <= '1'; + + -- otherwise if there is a read or write prepare to deactivate the row. + -- (This is overridden if the read/write is to the same row) + if r.rd_pending = '1' or r.wr_pending = '1' then + n.state <= s_dr0; + n.address(10) <= '1'; + end if; + + -- this is to catch if a read has turned up since the choices at state s_dr3 + if r.rd_pending = '1' and r.act_row = addr_row then + n.state <= s_rd0; + n.address <= "000" & addr_col; + n.bank <= addr_bank; + n.dq_masks <= "00"; + n.rd_pending <= '0'; + end if; + + -- this is to catch if a read has turned up since the choices at state s_dr3 + if r.wr_pending = '1' and r.act_row = addr_row then + n.state <= s_wr0; + n.address <= "000" & addr_col; + n.bank <= addr_bank; + n.dq_masks<= "00"; + n.wr_pending <= '0'; + end if; + + if r.rf_pending = '1' then + n.state <= s_dr0; + n.address(10) <= '1'; + end if; + + ------------------------------ + -- The Deactivate row during read section + ------------------------------ + when s_drdr0(8 downto 4) => + n.state <= s_drdr1; + when s_drdr1(8 downto 4) => + n.state <= s_drdr2; + n.data_out_low <= captured; + n.data_out_valid <= '1'; + when s_drdr2(8 downto 4) => + n.state <= s_idle; + + if r.rf_pending = '1' then + n.state <= s_rf0; + end if; + + if r.rd_pending = '1' or r.wr_pending = '1' then + n.state <= s_ra0; + n.address <= addr_row; + n.act_row <= addr_row; + n.bank <= addr_bank; + end if; + + when others => + n.state <= s_init_nop; + end case; + end process; + + --- The clock driven logic + process (clock_100, n) + begin + if clock_100'event and clock_100 = '1' then + r <= n; + end if; + end process; + + process (clock_100_delayed_3ns, dram_dq) + begin + if clock_100_delayed_3ns'event and clock_100_delayed_3ns = '1' then + captured <= dram_dq; + end if; + end process; + +end rtl; \ No newline at end of file diff --git a/sdram_clk_gen.ppf b/sdram_clk_gen.ppf new file mode 100644 index 0000000..751aa44 --- /dev/null +++ b/sdram_clk_gen.ppf @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/sdram_clk_gen.qip b/sdram_clk_gen.qip new file mode 100644 index 0000000..19c7fc5 --- /dev/null +++ b/sdram_clk_gen.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "sdram_clk_gen.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sdram_clk_gen_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sdram_clk_gen.ppf"] diff --git a/sdram_clk_gen.v b/sdram_clk_gen.v new file mode 100644 index 0000000..e90f670 --- /dev/null +++ b/sdram_clk_gen.v @@ -0,0 +1,329 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: sdram_clk_gen.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module sdram_clk_gen ( + inclk0, + c0, + c1); + + input inclk0; + output c0; + output c1; + + wire [4:0] sub_wire0; + wire [0:0] sub_wire5 = 1'h0; + wire [1:1] sub_wire2 = sub_wire0[1:1]; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire c1 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .inclk (sub_wire4), + .clk (sub_wire0), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .locked (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 1, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 2, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 1, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 2, + altpll_component.clk1_phase_shift = "3000", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 20000, + altpll_component.intended_device_family = "Cyclone IV E", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=sdram_clk_gen", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_UNUSED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "3.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "sdram_clk_gen.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "3000" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/sdram_clk_gen_bb.v b/sdram_clk_gen_bb.v new file mode 100644 index 0000000..cb1e21f --- /dev/null +++ b/sdram_clk_gen_bb.v @@ -0,0 +1,216 @@ +// megafunction wizard: %ALTPLL%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: sdram_clk_gen.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module sdram_clk_gen ( + inclk0, + c0, + c1); + + input inclk0; + output c0; + output c1; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "3.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "sdram_clk_gen.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "3000" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_clk_gen_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/simulation/modelsim/spectrum.vo b/simulation/modelsim/spectrum.vo index c5a510e..dcf16aa 100644 --- a/simulation/modelsim/spectrum.vo +++ b/simulation/modelsim/spectrum.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "04/01/2022 18:55:52" +// DATE "04/02/2022 14:51:21" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -50,14 +50,24 @@ module spectrum ( SW, GPIO_1, buzzer_out, - raw_loader_in); + raw_loader_in, + DRAM_BA, + DRAM_DQM, + DRAM_RAS_N, + DRAM_CAS_N, + DRAM_CKE, + DRAM_CLK, + DRAM_WE_N, + DRAM_CS_N, + DRAM_DQ, + DRAM_ADDR); output [7:0] LED; input CLOCK_50; input [1:0] KEY; input PS2_CLK; input PS2_DAT; -output I2C_SCLK; -output I2C_SDAT; +inout I2C_SCLK; +inout I2C_SDAT; output AUD_XCK; output AUD_ADCLRCK; output AUD_DACLRCK; @@ -73,6 +83,16 @@ input [3:0] SW; output [33:0] GPIO_1; output buzzer_out; input raw_loader_in; +output [1:0] DRAM_BA; +output [1:0] DRAM_DQM; +output DRAM_RAS_N; +output DRAM_CAS_N; +output DRAM_CKE; +output DRAM_CLK; +output DRAM_WE_N; +output DRAM_CS_N; +inout [15:0] DRAM_DQ; +output [12:0] DRAM_ADDR; // Design Ports Information // LED[0] => Location: PIN_A15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -139,8 +159,47 @@ input raw_loader_in; // GPIO_1[32] => Location: PIN_J13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // GPIO_1[33] => Location: PIN_J14, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // buzzer_out => Location: PIN_A6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_BA[0] => Location: PIN_M7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_BA[1] => Location: PIN_M6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQM[0] => Location: PIN_R6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQM[1] => Location: PIN_T5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_RAS_N => Location: PIN_L2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_CAS_N => Location: PIN_L1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_CKE => Location: PIN_L7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_CLK => Location: PIN_R4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_WE_N => Location: PIN_C2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_CS_N => Location: PIN_P6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[0] => Location: PIN_P2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[1] => Location: PIN_N5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[2] => Location: PIN_N6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[3] => Location: PIN_M8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[4] => Location: PIN_P8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[5] => Location: PIN_T7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[6] => Location: PIN_N8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[7] => Location: PIN_T6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[8] => Location: PIN_R1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[9] => Location: PIN_P1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[10] => Location: PIN_N2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[11] => Location: PIN_N1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[12] => Location: PIN_L4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // I2C_SCLK => Location: PIN_F2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // I2C_SDAT => Location: PIN_F1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[0] => Location: PIN_G2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[1] => Location: PIN_G1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[2] => Location: PIN_L8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[3] => Location: PIN_K5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[4] => Location: PIN_K2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[5] => Location: PIN_J2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[6] => Location: PIN_J1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[7] => Location: PIN_R7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[8] => Location: PIN_T4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[9] => Location: PIN_T2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[10] => Location: PIN_T3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[11] => Location: PIN_R3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[12] => Location: PIN_R5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[13] => Location: PIN_P3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[14] => Location: PIN_N3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[15] => Location: PIN_K1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // SW[1] => Location: PIN_T8, I/O Standard: 3.3-V LVTTL, Current Strength: Default // SW[2] => Location: PIN_B9, I/O Standard: 3.3-V LVTTL, Current Strength: Default // raw_loader_in => Location: PIN_B6, I/O Standard: 3.3-V LVTTL, Current Strength: Default @@ -170,6 +229,22 @@ initial $sdf_annotate("spectrum_v.sdo"); wire \SW[0]~input_o ; wire \SW[3]~input_o ; wire \I2C_SCLK~input_o ; +wire \DRAM_DQ[0]~input_o ; +wire \DRAM_DQ[1]~input_o ; +wire \DRAM_DQ[2]~input_o ; +wire \DRAM_DQ[3]~input_o ; +wire \DRAM_DQ[4]~input_o ; +wire \DRAM_DQ[5]~input_o ; +wire \DRAM_DQ[6]~input_o ; +wire \DRAM_DQ[7]~input_o ; +wire \DRAM_DQ[8]~input_o ; +wire \DRAM_DQ[9]~input_o ; +wire \DRAM_DQ[10]~input_o ; +wire \DRAM_DQ[11]~input_o ; +wire \DRAM_DQ[12]~input_o ; +wire \DRAM_DQ[13]~input_o ; +wire \DRAM_DQ[14]~input_o ; +wire \DRAM_DQ[15]~input_o ; wire \CLOCK_50~input_o ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_fbout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ; @@ -178,692 +253,8 @@ wire \SW[2]~input_o ; wire \ula_|clocks_|clk_cpu~0_combout ; wire \ula_|clocks_|clk_cpu~q ; wire \ula_|clocks_|clk_cpu~clkctrl_outclk ; -wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; -wire \z80_|sequencer_|ena_M~combout ; wire \KEY[1]~input_o ; wire \z80_|interrupts_|nmi_armed~feeder_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; -wire \z80_|interrupts_|nmi_armed~q ; -wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ; -wire \z80_|execute_|ctl_eval_cond~0_combout ; -wire \z80_|execute_|ixy_d~4_combout ; -wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M3_ff~q ; -wire \z80_|execute_|fIOWrite~1_combout ; -wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M4_ff~q ; -wire \z80_|pla_decode_|Equal32~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; -wire \z80_|decode_state_|table_xx~0_combout ; -wire \z80_|pla_decode_|Equal1~7_combout ; -wire \z80_|pla_decode_|Equal2~0_combout ; -wire \z80_|pla_decode_|Equal36~0_combout ; -wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; -wire \z80_|execute_|ctl_state_tbl_we~8_combout ; -wire \z80_|decode_state_|DFFE_instCB~q ; -wire \z80_|pla_decode_|Equal52~0_combout ; -wire \z80_|pla_decode_|Equal2~1_combout ; -wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; -wire \z80_|decode_state_|DFFE_instED~q ; -wire \z80_|pla_decode_|Equal13~0_combout ; -wire \z80_|pla_decode_|Equal33~0_combout ; -wire \z80_|execute_|ctl_im_we~combout ; -wire \z80_|pla_decode_|Equal49~0_combout ; -wire \z80_|pla_decode_|Equal33~1_combout ; -wire \z80_|pla_decode_|Equal6~0_combout ; -wire \z80_|execute_|ctl_mRead~14_combout ; -wire \z80_|pla_decode_|Equal12~0_combout ; -wire \z80_|execute_|ctl_sw_1d~8_combout ; -wire \z80_|nM1_int~2_combout ; -wire \z80_|execute_|ctl_sw_1d~5_combout ; -wire \z80_|pla_decode_|Equal3~0_combout ; -wire \z80_|execute_|ctl_mRead~4_combout ; -wire \z80_|execute_|ixy_d~7_combout ; -wire \z80_|execute_|ctl_state_alu~4_combout ; -wire \z80_|execute_|ctl_sw_1d~4_combout ; -wire \z80_|pla_decode_|Equal40~1_combout ; -wire \z80_|pla_decode_|Equal39~0_combout ; -wire \z80_|execute_|ctl_bus_db_oe~1_combout ; -wire \z80_|pla_decode_|Equal13~1_combout ; -wire \z80_|pla_decode_|Equal13~2_combout ; -wire \z80_|pla_decode_|Equal3~2_combout ; -wire \z80_|execute_|ctl_state_iy_set~2_combout ; -wire \z80_|execute_|ixy_d~8_combout ; -wire \z80_|execute_|ixy_d~6_combout ; -wire \z80_|execute_|ixy_d~9_combout ; -wire \z80_|execute_|ixy_d~12_combout ; -wire \z80_|execute_|ixy_d~10_combout ; -wire \z80_|pla_decode_|Equal44~0_combout ; -wire \z80_|execute_|ixy_d~16_combout ; -wire \z80_|execute_|ixy_d~13_combout ; -wire \z80_|pla_decode_|Equal50~0_combout ; -wire \z80_|pla_decode_|Equal33~2_combout ; -wire \z80_|execute_|ixy_d~17_combout ; -wire \z80_|execute_|ixy_d~5_combout ; -wire \z80_|execute_|ixy_d~14_combout ; -wire \z80_|execute_|ixy_d~11_combout ; -wire \z80_|execute_|ixy_d~15_combout ; -wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; -wire \z80_|decode_state_|DFFE_instIY1~q ; -wire \z80_|execute_|ctl_ir_we~5_combout ; -wire \z80_|execute_|ctl_ir_we~14_combout ; -wire \z80_|execute_|ctl_mWrite~2_combout ; -wire \z80_|execute_|ctl_mWrite~16_combout ; -wire \z80_|execute_|ctl_flags_alu~18_combout ; -wire \z80_|execute_|ctl_mRead~26_combout ; -wire \z80_|execute_|ctl_mRead~27_combout ; -wire \z80_|execute_|ctl_bus_db_oe~7_combout ; -wire \z80_|execute_|ctl_sw_2d~5_combout ; -wire \z80_|execute_|ctl_mRead~18_combout ; -wire \z80_|pla_decode_|Equal55~0_combout ; -wire \z80_|execute_|comb~1_combout ; -wire \z80_|execute_|ctl_mRead~15_combout ; -wire \z80_|execute_|ctl_mRead~17_combout ; -wire \z80_|execute_|ctl_reg_in_hi~5_combout ; -wire \z80_|execute_|ctl_mRead~9_combout ; -wire \z80_|pla_decode_|Equal9~0_combout ; -wire \z80_|execute_|ctl_mRead~10_combout ; -wire \z80_|execute_|ctl_mRead~8_combout ; -wire \z80_|execute_|ctl_mRead~20_combout ; -wire \z80_|pla_decode_|Equal12~1_combout ; -wire \z80_|pla_decode_|Equal9~1_combout ; -wire \z80_|pla_decode_|Equal25~0_combout ; -wire \z80_|execute_|ctl_mRead~21_combout ; -wire \z80_|execute_|ctl_state_alu~6_combout ; -wire \z80_|pla_decode_|Equal19~0_combout ; -wire \z80_|pla_decode_|Equal1~4_combout ; -wire \z80_|pla_decode_|Equal29~0_combout ; -wire \z80_|pla_decode_|Equal24~1_combout ; -wire \z80_|pla_decode_|Equal34~0_combout ; -wire \z80_|pla_decode_|Equal37~0_combout ; -wire \z80_|pla_decode_|Equal35~0_combout ; -wire \z80_|pla_decode_|Equal38~2_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; -wire \z80_|execute_|comb~0_combout ; -wire \z80_|pla_decode_|Equal47~0_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; -wire \z80_|execute_|ctl_mRead~22_combout ; -wire \z80_|execute_|ctl_mRead~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_in_hi~6_combout ; -wire \z80_|pla_decode_|Equal6~1_combout ; -wire \z80_|execute_|ctl_mRead~16_combout ; -wire \z80_|sequencer_|M5~0_combout ; -wire \z80_|sequencer_|M5~q ; -wire \z80_|execute_|ctl_reg_in_hi~2_combout ; -wire \z80_|execute_|setM1~29_combout ; -wire \z80_|execute_|ctl_mRead~25_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; -wire \z80_|execute_|ctl_ir_we~7_combout ; -wire \z80_|pla_decode_|Equal52~1_combout ; -wire \z80_|execute_|ctl_state_alu~14_combout ; -wire \z80_|execute_|ctl_state_alu~8_combout ; -wire \z80_|pla_decode_|Equal24~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~1_combout ; -wire \z80_|reg_control_|reg_sel_pc~2_combout ; -wire \z80_|execute_|fMRead~17_combout ; -wire \z80_|execute_|ctl_mRead~6_combout ; -wire \z80_|pla_decode_|Equal11~0_combout ; -wire \z80_|pla_decode_|Equal10~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; -wire \z80_|execute_|ctl_sw_2d~4_combout ; -wire \z80_|execute_|ctl_ir_we~15_combout ; -wire \z80_|execute_|fMRead~16_combout ; -wire \z80_|execute_|ctl_ir_we~9_combout ; -wire \z80_|pla_decode_|Equal46~0_combout ; -wire \z80_|execute_|ctl_ir_we~10_combout ; -wire \z80_|execute_|ctl_flags_alu~17_combout ; -wire \z80_|execute_|ctl_flags_alu~6_combout ; -wire \z80_|execute_|ctl_ir_we~6_combout ; -wire \z80_|execute_|ctl_ir_we~8_combout ; -wire \z80_|execute_|ctl_flags_alu~16_combout ; -wire \z80_|execute_|ctl_reg_in_hi~3_combout ; -wire \z80_|execute_|ctl_mWrite~8_combout ; -wire \z80_|execute_|fMRead~18_combout ; -wire \z80_|execute_|fMRead~19_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; -wire \z80_|execute_|ctl_mRead~36_combout ; -wire \z80_|execute_|ctl_alu_op_low~9_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; -wire \z80_|execute_|ctl_mRead~11_combout ; -wire \z80_|execute_|ctl_sw_2d~6_combout ; -wire \z80_|execute_|ctl_sw_2d~7_combout ; -wire \z80_|execute_|ctl_mWrite~7_combout ; -wire \z80_|execute_|ctl_ir_we~11_combout ; -wire \z80_|execute_|ctl_ir_we~12_combout ; -wire \z80_|execute_|ctl_flags_sz_we~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; -wire \z80_|execute_|ctl_sw_2d~8_combout ; -wire \z80_|execute_|ctl_sw_2d~9_combout ; -wire \z80_|execute_|ctl_sw_1d~6_combout ; -wire \z80_|execute_|ctl_sw_1d~7_combout ; -wire \z80_|execute_|ctl_alu_op_low~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; -wire \z80_|execute_|ctl_reg_out_hi~4_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; -wire \z80_|alu_|db_low[2]~4_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ; -wire \z80_|execute_|ctl_sw_4u~1_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; -wire \z80_|pla_decode_|Equal69~0_combout ; -wire \z80_|pla_decode_|Equal1~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~14_combout ; -wire \z80_|execute_|ctl_alu_op_low~12_combout ; -wire \z80_|pla_decode_|Equal56~0_combout ; -wire \z80_|execute_|ctl_alu_op_low~11_combout ; -wire \z80_|execute_|nextM~2_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~5_combout ; -wire \z80_|execute_|ctl_alu_oe~3_combout ; -wire \z80_|execute_|ctl_alu_op_low~15_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; -wire \z80_|execute_|ctl_alu_core_R~3_combout ; -wire \z80_|execute_|ctl_alu_core_R~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; -wire \z80_|pla_decode_|Equal48~0_combout ; -wire \z80_|execute_|ctl_flags_hf2_we~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; -wire \z80_|execute_|ctl_flags_xy_we~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; -wire \z80_|execute_|ctl_iorw~10_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~13_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; -wire \z80_|execute_|ctl_bus_db_oe~3_combout ; -wire \z80_|pla_decode_|Equal20~0_combout ; -wire \z80_|pla_decode_|Equal68~2_combout ; -wire \z80_|execute_|ctl_flags_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op_low~13_combout ; -wire \z80_|execute_|ctl_flags_bus~15_combout ; -wire \z80_|execute_|ctl_flags_bus~11_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ; -wire \z80_|execute_|ctl_flags_bus~10_combout ; -wire \z80_|execute_|ctl_flags_bus~8_combout ; -wire \z80_|execute_|ctl_flags_bus~9_combout ; -wire \z80_|execute_|ctl_flags_bus~12_combout ; -wire \z80_|execute_|ctl_flags_xy_we~11_combout ; -wire \z80_|execute_|ctl_flags_xy_we~12_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; -wire \z80_|execute_|ctl_ir_we~4_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; -wire \z80_|execute_|ctl_bus_db_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; -wire \z80_|execute_|ctl_66_oe~2_combout ; -wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; -wire \z80_|execute_|ctl_alu_op_low~10_combout ; -wire \z80_|execute_|fMWrite~11_combout ; -wire \z80_|execute_|ctl_alu_op_low~21_combout ; -wire \z80_|execute_|ctl_alu_op_low~22_combout ; -wire \z80_|execute_|ctl_alu_op_low~16_combout ; -wire \z80_|execute_|ctl_alu_op_low~17_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; -wire \z80_|execute_|ctl_reg_gp_sel~36_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~4_combout ; -wire \z80_|execute_|ctl_state_alu~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~18_combout ; -wire \z80_|execute_|ctl_alu_op_low~19_combout ; -wire \z80_|execute_|ctl_alu_op_low~33_combout ; -wire \z80_|execute_|ctl_alu_op_low~20_combout ; -wire \z80_|execute_|ctl_alu_op_low~23_combout ; -wire \z80_|execute_|ctl_alu_op_low~24_combout ; -wire \z80_|execute_|ctl_alu_op_low~25_combout ; -wire \z80_|execute_|ctl_alu_op_low~34_combout ; -wire \z80_|execute_|ctl_alu_op_low~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~14_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; -wire \z80_|execute_|ctl_reg_use_sp~0_combout ; -wire \z80_|execute_|ctl_reg_use_sp~1_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; -wire \z80_|execute_|ctl_reg_in_lo~9_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; -wire \z80_|execute_|ctl_flags_xy_we~8_combout ; -wire \z80_|execute_|ctl_flags_xy_we~9_combout ; -wire \z80_|pla_decode_|Equal8~0_combout ; -wire \z80_|execute_|ctl_flags_alu~9_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; -wire \z80_|execute_|ctl_flags_sz_we~3_combout ; -wire \z80_|pla_decode_|Equal11~1_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; -wire \z80_|execute_|ctl_flags_alu~10_combout ; -wire \z80_|execute_|ctl_flags_alu~11_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; -wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; -wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; -wire \z80_|execute_|ctl_flags_cf_we~7_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~2_combout ; -wire \z80_|execute_|ctl_alu_oe~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~25_combout ; -wire \z80_|execute_|ctl_flags_hf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; -wire \z80_|execute_|ctl_flags_pf_we~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~3_combout ; -wire \z80_|execute_|ctl_flags_xy_we~17_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; -wire \z80_|execute_|ctl_flags_xy_we~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; -wire \z80_|execute_|ctl_state_alu~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~1_combout ; -wire \z80_|execute_|ctl_flags_cf_we~2_combout ; -wire \z80_|execute_|ctl_alu_core_S~6_combout ; -wire \z80_|execute_|ctl_alu_core_S~7_combout ; -wire \z80_|execute_|ctl_alu_core_S~4_combout ; -wire \z80_|execute_|ctl_alu_core_S~5_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; -wire \z80_|execute_|ctl_alu_res_oe~0_combout ; -wire \z80_|execute_|ctl_alu_oe~15_combout ; -wire \z80_|execute_|ctl_alu_res_oe~1_combout ; -wire \z80_|execute_|ctl_alu_res_oe~2_combout ; -wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; -wire \z80_|alu_|db_high[3]~2_combout ; -wire \z80_|alu_|db_high[3]~3_combout ; -wire \z80_|alu_|db_low[2]~24_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~7_combout ; -wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_in_hi~8_combout ; -wire \z80_|execute_|ctl_alu_oe~8_combout ; -wire \z80_|execute_|ctl_alu_oe~4_combout ; -wire \z80_|execute_|ctl_mWrite~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~10_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; -wire \z80_|execute_|ctl_bus_db_we~5_combout ; -wire \z80_|execute_|ctl_alu_oe~9_combout ; -wire \z80_|execute_|ctl_alu_oe~11_combout ; -wire \z80_|execute_|ctl_alu_oe~5_combout ; -wire \z80_|execute_|ctl_alu_core_S~11_combout ; -wire \z80_|execute_|ctl_alu_oe~6_combout ; -wire \z80_|execute_|ctl_alu_oe~7_combout ; -wire \z80_|execute_|ctl_alu_oe~12_combout ; -wire \z80_|execute_|ctl_alu_oe~13_combout ; -wire \z80_|execute_|ctl_alu_oe~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ; -wire \z80_|execute_|ctl_reg_out_hi~8_combout ; -wire \z80_|execute_|setM1~54_combout ; -wire \z80_|execute_|ctl_sw_2u~1_combout ; -wire \z80_|execute_|ctl_sw_2u~4_combout ; -wire \z80_|execute_|ctl_sw_2u~5_combout ; -wire \z80_|execute_|ctl_sw_2u~6_combout ; -wire \z80_|execute_|ctl_inc_cy~35_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; -wire \z80_|execute_|ctl_mWrite~6_combout ; -wire \z80_|execute_|ctl_sw_2u~2_combout ; -wire \z80_|execute_|ctl_sw_2u~0_combout ; -wire \z80_|execute_|ctl_sw_2u~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; -wire \z80_|execute_|ctl_reg_out_lo~2_combout ; -wire \z80_|execute_|rsel3~combout ; -wire \z80_|execute_|ctl_reg_out_hi~5_combout ; -wire \z80_|execute_|ctl_reg_out_hi~6_combout ; -wire \z80_|execute_|ctl_reg_out_hi~7_combout ; -wire \z80_|execute_|rsel0~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ; -wire \z80_|execute_|ctl_reg_out_lo~6_combout ; -wire \z80_|execute_|ctl_reg_out_lo~7_combout ; -wire \z80_|execute_|ctl_iorw~11_combout ; -wire \z80_|execute_|ctl_sw_2d~10_combout ; -wire \z80_|execute_|ctl_sw_2d~14_combout ; -wire \z80_|execute_|ctl_sw_2d~11_combout ; -wire \z80_|execute_|ctl_sw_2d~12_combout ; -wire \z80_|execute_|ctl_sw_2d~13_combout ; -wire \z80_|execute_|ctl_66_oe~combout ; -wire \z80_|execute_|ctl_inc_cy~34_combout ; -wire \z80_|execute_|ctl_apin_mux~0_combout ; -wire \z80_|execute_|ctl_sw_4u~5_combout ; -wire \z80_|execute_|ctl_inc_cy~75_combout ; -wire \z80_|execute_|ctl_inc_cy~76_combout ; -wire \z80_|pla_decode_|Equal4~0_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; -wire \z80_|execute_|ctl_inc_cy~53_combout ; -wire \z80_|execute_|ctl_inc_cy~92_combout ; -wire \z80_|pla_decode_|Equal19~1_combout ; -wire \z80_|execute_|ctl_sw_4u~0_combout ; -wire \z80_|execute_|ctl_inc_cy~38_combout ; -wire \z80_|execute_|ctl_inc_cy~93_combout ; -wire \z80_|execute_|ctl_inc_cy~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~24_combout ; -wire \z80_|execute_|ctl_reg_gp_we~1_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; -wire \z80_|execute_|ctl_reg_gp_we~0_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; -wire \z80_|execute_|ctl_sw_4u~2_combout ; -wire \z80_|execute_|ctl_sw_4u~3_combout ; -wire \z80_|execute_|fMRead~3_combout ; -wire \z80_|execute_|ctl_sw_4u~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ; -wire \z80_|execute_|ctl_inc_cy~94_combout ; -wire \z80_|execute_|ctl_inc_cy~87_combout ; -wire \z80_|execute_|ctl_inc_cy~42_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; -wire \z80_|execute_|ctl_sw_4u~6_combout ; -wire \z80_|pla_decode_|Equal2~2_combout ; -wire \z80_|pla_decode_|Equal1~6_combout ; -wire \z80_|reg_control_|bank_exx~2_combout ; -wire \z80_|reg_control_|bank_exx~q ; -wire \z80_|reg_control_|bank_hl_de1~0_combout ; -wire \z80_|reg_control_|bank_hl_de1~q ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~12_combout ; -wire \z80_|execute_|ctl_mRead~7_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~13_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; -wire \z80_|execute_|fMWrite~3_combout ; -wire \z80_|execute_|ctl_flags_bus~5_combout ; -wire \z80_|execute_|fMRead~2_combout ; -wire \z80_|execute_|ctl_mRead~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~7_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; -wire \z80_|execute_|ctl_reg_use_sp~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; -wire \z80_|execute_|ctl_reg_use_sp~3_combout ; -wire \z80_|execute_|ctl_sw_1d~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~21_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~22_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~14_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; -wire \z80_|execute_|setM1~47_combout ; -wire \z80_|execute_|setM1~48_combout ; -wire \z80_|execute_|ctl_al_we~13_combout ; -wire \z80_|execute_|ctl_flags_oe~0_combout ; -wire \z80_|execute_|ctl_flags_oe~1_combout ; -wire \z80_|execute_|ctl_reg_in_hi~13_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; -wire \z80_|execute_|ctl_inc_cy~40_combout ; -wire \z80_|execute_|ctl_inc_dec~2_combout ; -wire \z80_|execute_|ctl_inc_dec~12_combout ; -wire \z80_|execute_|ctl_inc_cy~43_combout ; -wire \z80_|execute_|ctl_inc_dec~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; -wire \z80_|execute_|fMRead~6_combout ; -wire \z80_|execute_|fMRead~7_combout ; -wire \z80_|execute_|fMRead~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; -wire \z80_|execute_|ctl_state_alu~13_combout ; -wire \z80_|execute_|ctl_state_alu~10_combout ; -wire \z80_|execute_|ctl_state_alu~11_combout ; -wire \z80_|execute_|ctl_state_alu~9_combout ; -wire \z80_|pla_decode_|Equal62~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; -wire \z80_|pla_decode_|Equal64~0_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_state_alu~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; -wire \z80_|reg_control_|reg_sel_de2~5_combout ; -wire \z80_|reg_control_|reg_sel_de2~6_combout ; -wire \z80_|reg_control_|reg_sel_hl~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~q ; -wire \z80_|reg_control_|reg_sel_hl2~0_combout ; -wire \z80_|execute_|ctl_reg_in_hi~7_combout ; -wire \z80_|execute_|ctl_reg_gp_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_we~3_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_we~2_combout ; -wire \z80_|execute_|ctl_reg_gp_we~5_combout ; -wire \z80_|execute_|ctl_reg_gp_we~6_combout ; -wire \z80_|execute_|ctl_al_we~14_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; -wire \z80_|execute_|setM1~40_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~93_combout ; -wire \z80_|reg_control_|reg_sel_de~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; -wire \z80_|execute_|ctl_reg_in_hi~9_combout ; -wire \z80_|execute_|ctl_reg_in_hi~10_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; -wire \z80_|execute_|ctl_reg_in_lo~8_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; -wire \z80_|execute_|ctl_reg_use_sp~4_combout ; -wire \z80_|execute_|ctl_reg_use_sp~5_combout ; -wire \z80_|execute_|ctl_reg_use_sp~6_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; -wire \z80_|pla_decode_|Equal21~2_combout ; -wire \z80_|reg_control_|bank_af~0_combout ; -wire \z80_|reg_control_|bank_af~q ; -wire \z80_|reg_control_|reg_sel_af~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|reg_control_|reg_sel_af2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; -wire \z80_|execute_|ctl_flags_bus~4_combout ; -wire \z80_|execute_|ctl_flags_bus~6_combout ; -wire \z80_|execute_|ctl_flags_bus~7_combout ; -wire \z80_|execute_|fMRead~24_combout ; -wire \z80_|execute_|ctl_flags_bus~13_combout ; -wire \z80_|execute_|ctl_flags_bus~combout ; -wire \z80_|execute_|ctl_inc_dec~3_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; -wire \z80_|execute_|ctl_mRead~13_combout ; -wire \z80_|execute_|pc_inc_hold~49_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; -wire \z80_|execute_|pc_inc_hold~28_combout ; -wire \z80_|execute_|setM1~35_combout ; -wire \z80_|execute_|setM1~36_combout ; -wire \z80_|execute_|fMRead~5_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; -wire \z80_|execute_|pc_inc_hold~29_combout ; -wire \z80_|execute_|ctl_reg_sys_we~1_combout ; -wire \z80_|execute_|ctl_reg_sys_we~2_combout ; -wire \z80_|pla_decode_|Equal33~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~2_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~4_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~combout ; -wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; -wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; -wire \z80_|execute_|ctl_reg_out_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; -wire \z80_|execute_|ctl_reg_in_hi~4_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~5_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; -wire \z80_|execute_|ctl_al_we~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; -wire \z80_|execute_|fMRead~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; -wire \z80_|execute_|ctl_inc_dec~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; -wire \z80_|execute_|ctl_al_we~5_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; -wire \z80_|execute_|fMRead~1_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; -wire \z80_|execute_|ctl_inc_cy~77_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; -wire \z80_|execute_|ctl_sw_4d~3_combout ; -wire \z80_|execute_|ctl_sw_4d~4_combout ; -wire \z80_|execute_|ctl_sw_4d~2_combout ; -wire \z80_|execute_|ctl_sw_4d~5_combout ; -wire \z80_|execute_|setM1~45_combout ; -wire \z80_|execute_|setM1~46_combout ; -wire \z80_|execute_|ctl_sw_4d~1_combout ; -wire \z80_|execute_|ctl_sw_4d~0_combout ; -wire \z80_|execute_|ctl_sw_4d~6_combout ; -wire \z80_|execute_|fMRead~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~20_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; -wire \z80_|reg_control_|reg_sel_pc~3_combout ; -wire \z80_|reg_control_|reg_sel_pc~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; -wire \z80_|reg_file_|db_lo_as[0]~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; -wire \z80_|reg_file_|db_lo_as[7]~22_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; -wire \z80_|reg_file_|db_lo_as[7]~23_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; -wire \z80_|resets_|DFFE_intr_ff3~q ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ; wire \KEY[0]~input_o ; wire \reset~combout ; @@ -872,77 +263,13 @@ wire \z80_|fpga_reset~feeder_combout ; wire \z80_|fpga_reset~q ; wire \z80_|fpga_reset~clkctrl_outclk ; wire \z80_|resets_|x1~q ; -wire \z80_|resets_|clrpc_int~0_combout ; -wire \z80_|resets_|clrpc_int~q ; -wire \z80_|resets_|clrpc~0_combout ; -wire \z80_|execute_|ctl_apin_mux~1_combout ; -wire \z80_|execute_|ctl_al_we~6_combout ; -wire \z80_|execute_|ctl_al_we~7_combout ; -wire \z80_|execute_|ctl_al_we~8_combout ; -wire \z80_|execute_|ctl_alu_oe~10_combout ; -wire \z80_|execute_|ctl_al_we~9_combout ; -wire \z80_|execute_|ctl_al_we~10_combout ; -wire \z80_|execute_|ctl_al_we~11_combout ; -wire \z80_|execute_|ctl_al_we~12_combout ; -wire \z80_|execute_|ctl_inc_dec~6_combout ; -wire \z80_|execute_|fIOWrite~0_combout ; -wire \z80_|execute_|ctl_inc_dec~8_combout ; -wire \z80_|execute_|ctl_inc_dec~9_combout ; -wire \z80_|execute_|ctl_inc_dec~10_combout ; -wire \z80_|execute_|ctl_inc_dec~7_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; -wire \z80_|reg_control_|reg_sel_de2~4_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; -wire \z80_|reg_control_|reg_sel_iy~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; -wire \z80_|reg_file_|db_lo_as[2]~7_combout ; -wire \z80_|reg_file_|db_lo_as[2]~8_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; -wire \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; -wire \z80_|reg_file_|db_lo_as[0]~0_combout ; -wire \z80_|reg_file_|db_lo_as[0]~1_combout ; -wire \z80_|execute_|ctl_inc_cy~72_combout ; +wire \z80_|resets_|x3~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; +wire \z80_|interrupts_|nmi_armed~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; -wire \ula_|video_|Add0~15 ; -wire \ula_|video_|Add0~16_combout ; -wire \ula_|video_|vga_hc~2_combout ; -wire \ula_|video_|Add0~17 ; -wire \ula_|video_|Add0~18_combout ; -wire \ula_|video_|vga_hc~1_combout ; wire \ula_|video_|Add0~0_combout ; wire \ula_|video_|vga_hc~3_combout ; wire \ula_|video_|Add0~1 ; @@ -952,12 +279,8 @@ wire \ula_|video_|Add0~3 ; wire \ula_|video_|Add0~4_combout ; wire \ula_|video_|Add0~5 ; wire \ula_|video_|Add0~6_combout ; -wire \ula_|video_|vga_hc[3]~feeder_combout ; wire \ula_|video_|Add0~7 ; wire \ula_|video_|Add0~8_combout ; -wire \ula_|video_|Equal0~0_combout ; -wire \ula_|video_|Equal0~1_combout ; -wire \ula_|video_|Equal1~0_combout ; wire \ula_|video_|Add0~9 ; wire \ula_|video_|Add0~10_combout ; wire \ula_|video_|vga_hc~0_combout ; @@ -965,7 +288,18 @@ wire \ula_|video_|Add0~11 ; wire \ula_|video_|Add0~12_combout ; wire \ula_|video_|Add0~13 ; wire \ula_|video_|Add0~14_combout ; -wire \ula_|video_|Add1~0_combout ; +wire \ula_|video_|Equal0~0_combout ; +wire \ula_|video_|Equal0~1_combout ; +wire \ula_|video_|Add0~15 ; +wire \ula_|video_|Add0~16_combout ; +wire \ula_|video_|vga_hc~2_combout ; +wire \ula_|video_|Add0~17 ; +wire \ula_|video_|Add0~18_combout ; +wire \ula_|video_|vga_hc~1_combout ; +wire \ula_|video_|Equal1~0_combout ; +wire \ula_|video_|Add1~1 ; +wire \ula_|video_|Add1~2_combout ; +wire \ula_|video_|vga_vc[1]~1_combout ; wire \ula_|video_|Add1~3 ; wire \ula_|video_|Add1~4_combout ; wire \ula_|video_|vga_vc[2]~2_combout ; @@ -990,809 +324,1661 @@ wire \ula_|video_|vga_vc[8]~7_combout ; wire \ula_|video_|Add1~17 ; wire \ula_|video_|Add1~18_combout ; wire \ula_|video_|vga_vc[9]~9_combout ; -wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Equal3~0_combout ; +wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Equal3~1_combout ; +wire \ula_|video_|Add1~0_combout ; wire \ula_|video_|vga_vc[0]~0_combout ; -wire \ula_|video_|Add1~1 ; -wire \ula_|video_|Add1~2_combout ; -wire \ula_|video_|vga_vc[1]~1_combout ; -wire \SW[1]~input_o ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; -wire \z80_|pla_decode_|Equal79~0_combout ; -wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \z80_|interrupts_|DFFE_instIFF2~q ; -wire \z80_|interrupts_|iff1~0_combout ; -wire \z80_|interrupts_|iff1~1_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|interrupts_|iff1~q ; wire \ula_|video_|Equal2~1_combout ; wire \ula_|video_|Equal2~2_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ; -wire \z80_|interrupts_|int_armed~q ; -wire \z80_|interrupts_|DFFE_inst44~q ; -wire \z80_|execute_|pc_inc_hold~38_combout ; -wire \z80_|execute_|ctl_inc_cy~91_combout ; -wire \z80_|execute_|pc_inc_hold~45_combout ; -wire \z80_|execute_|pc_inc_hold~44_combout ; -wire \z80_|execute_|pc_inc_hold~46_combout ; -wire \z80_|execute_|pc_inc_hold~37_combout ; -wire \z80_|execute_|pc_inc_hold~50_combout ; -wire \z80_|execute_|pc_inc_hold~33_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; -wire \z80_|execute_|pc_inc_hold~31_combout ; -wire \z80_|execute_|pc_inc_hold~32_combout ; -wire \z80_|execute_|pc_inc_hold~34_combout ; -wire \z80_|execute_|pc_inc_hold~51_combout ; -wire \z80_|execute_|pc_inc_hold~30_combout ; -wire \z80_|execute_|pc_inc_hold~52_combout ; -wire \z80_|execute_|pc_inc_hold~35_combout ; -wire \z80_|execute_|pc_inc_hold~36_combout ; -wire \z80_|execute_|ctl_inc_cy~44_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; -wire \z80_|execute_|ctl_inc_cy~45_combout ; -wire \z80_|execute_|pc_inc_hold~43_combout ; -wire \z80_|execute_|ctl_inc_cy~71_combout ; -wire \z80_|execute_|ctl_inc_cy~73_combout ; +wire \SW[1]~input_o ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; +wire \z80_|execute_|ctl_mWrite~4_combout ; +wire \z80_|pla_decode_|Equal0~0_combout ; +wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M3_ff~q ; +wire \z80_|execute_|ixy_d~6_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ; +wire \z80_|pla_decode_|Equal33~0_combout ; +wire \z80_|execute_|ctl_mRead~5_combout ; +wire \z80_|pla_decode_|Equal77~0_combout ; +wire \z80_|pla_decode_|Equal50~0_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ; +wire \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ; +wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; +wire \z80_|clk_delay_|DFF_inst5~q ; +wire \z80_|clk_delay_|hold_clk_iorq~combout ; +wire \z80_|sequencer_|DFFE_T5_ff~q ; +wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; +wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; +wire \z80_|decode_state_|DFFE_inst4~q ; +wire \z80_|execute_|fMWrite~3_combout ; +wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M4_ff~q ; +wire \z80_|execute_|fMWrite~2_combout ; +wire \z80_|pla_decode_|Equal13~1_combout ; +wire \z80_|pla_decode_|Equal13~2_combout ; +wire \z80_|execute_|ixy_d~4_combout ; +wire \z80_|execute_|fIOWrite~1_combout ; +wire \z80_|execute_|ctl_mWrite~5_combout ; +wire \z80_|execute_|fMRead~2_combout ; +wire \z80_|execute_|ctl_state_alu~2_combout ; +wire \z80_|execute_|ctl_iorw~11_combout ; +wire \z80_|execute_|fIOWrite~2_combout ; +wire \z80_|pla_decode_|Equal2~0_combout ; +wire \z80_|decode_state_|table_xx~0_combout ; +wire \z80_|pla_decode_|Equal1~7_combout ; +wire \z80_|pla_decode_|Equal21~0_combout ; +wire \z80_|execute_|ctl_mRead~3_combout ; +wire \z80_|execute_|fIOWrite~3_combout ; +wire \z80_|execute_|ixy_d~5_combout ; +wire \z80_|execute_|fIOWrite~4_combout ; +wire \z80_|execute_|fIOWrite~5_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; +wire \z80_|execute_|ctl_state_alu~3_combout ; +wire \z80_|pla_decode_|Equal3~1_combout ; +wire \z80_|execute_|ctl_mWrite~6_combout ; +wire \z80_|execute_|ctl_ir_we~4_combout ; +wire \z80_|pla_decode_|Equal9~0_combout ; +wire \z80_|pla_decode_|Equal9~1_combout ; +wire \z80_|execute_|ctl_sw_2u~0_combout ; +wire \z80_|pla_decode_|Equal11~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~14_combout ; wire \z80_|execute_|ctl_inc_cy~46_combout ; -wire \z80_|execute_|pc_inc_hold~53_combout ; -wire \z80_|execute_|pc_inc_hold~39_combout ; -wire \z80_|execute_|pc_inc_hold~47_combout ; -wire \z80_|execute_|ctl_inc_cy~74_combout ; -wire \z80_|execute_|ctl_inc_cy~78_combout ; -wire \z80_|execute_|ctl_inc_cy~79_combout ; -wire \z80_|execute_|ctl_inc_cy~80_combout ; -wire \z80_|execute_|ctl_inc_cy~81_combout ; -wire \z80_|execute_|ctl_inc_cy~82_combout ; -wire \z80_|execute_|ctl_inc_cy~83_combout ; -wire \z80_|execute_|ctl_inc_cy~84_combout ; -wire \z80_|execute_|pc_inc_hold~42_combout ; -wire \z80_|execute_|ctl_inc_cy~90_combout ; -wire \z80_|execute_|pc_inc_hold~41_combout ; -wire \z80_|execute_|ctl_inc_cy~66_combout ; -wire \z80_|execute_|ctl_inc_cy~67_combout ; -wire \z80_|execute_|ctl_inc_cy~68_combout ; -wire \z80_|execute_|ctl_inc_cy~64_combout ; -wire \z80_|execute_|ctl_inc_cy~63_combout ; -wire \z80_|execute_|ctl_inc_cy~65_combout ; -wire \z80_|execute_|ctl_inc_cy~69_combout ; -wire \z80_|execute_|ctl_inc_cy~49_combout ; -wire \z80_|execute_|ctl_inc_cy~50_combout ; -wire \z80_|execute_|ctl_inc_cy~51_combout ; -wire \z80_|execute_|ctl_inc_cy~52_combout ; -wire \z80_|execute_|ctl_inc_cy~36_combout ; -wire \z80_|execute_|ctl_inc_cy~37_combout ; -wire \z80_|execute_|ctl_inc_cy~54_combout ; -wire \z80_|execute_|ctl_inc_cy~41_combout ; -wire \z80_|execute_|ctl_inc_cy~58_combout ; -wire \z80_|execute_|ctl_inc_cy~55_combout ; -wire \z80_|execute_|ctl_inc_cy~56_combout ; -wire \z80_|execute_|ctl_inc_cy~89_combout ; -wire \z80_|execute_|ctl_inc_cy~57_combout ; -wire \z80_|execute_|ctl_inc_cy~59_combout ; -wire \z80_|execute_|ctl_inc_cy~60_combout ; wire \z80_|execute_|ctl_inc_cy~47_combout ; -wire \z80_|execute_|ctl_inc_cy~88_combout ; +wire \z80_|pla_decode_|Equal19~0_combout ; +wire \z80_|pla_decode_|Equal34~0_combout ; +wire \z80_|execute_|comb~0_combout ; +wire \z80_|pla_decode_|Equal47~0_combout ; +wire \z80_|execute_|ctl_inc_cy~45_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; +wire \z80_|sequencer_|M5~0_combout ; +wire \z80_|sequencer_|M5~q ; +wire \z80_|execute_|ctl_alu_oe~2_combout ; +wire \z80_|execute_|ixy_d~7_combout ; +wire \z80_|execute_|ctl_inc_cy~44_combout ; +wire \z80_|execute_|ctl_apin_mux~0_combout ; +wire \z80_|execute_|ctl_mRead~4_combout ; +wire \z80_|execute_|ctl_ir_we~5_combout ; +wire \z80_|execute_|ctl_ir_we~15_combout ; +wire \z80_|execute_|ctl_ir_we~14_combout ; +wire \z80_|execute_|ctl_ir_we~7_combout ; +wire \z80_|execute_|fMWrite~0_combout ; +wire \z80_|execute_|ctl_inc_cy~97_combout ; +wire \z80_|execute_|ctl_inc_cy~96_combout ; +wire \z80_|execute_|ctl_inc_cy~98_combout ; wire \z80_|execute_|ctl_inc_cy~48_combout ; -wire \z80_|execute_|pc_inc_hold~40_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; +wire \z80_|execute_|fMWrite~1_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; +wire \z80_|execute_|ctl_mRead~6_combout ; +wire \z80_|execute_|ctl_reg_in_hi~2_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; +wire \z80_|execute_|ctl_mWrite~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; +wire \z80_|execute_|ctl_mWrite~17_combout ; +wire \z80_|execute_|fMWrite~4_combout ; +wire \z80_|execute_|ctl_state_alu~4_combout ; +wire \z80_|execute_|ctl_inc_cy~49_combout ; +wire \z80_|execute_|ctl_inc_dec~2_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; +wire \z80_|execute_|fMWrite~8_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~51_combout ; +wire \z80_|execute_|ctl_ir_we~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~10_combout ; +wire \z80_|pla_decode_|Equal46~0_combout ; +wire \z80_|execute_|ctl_ir_we~10_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; +wire \z80_|execute_|ctl_ir_we~6_combout ; +wire \z80_|execute_|ctl_ir_we~8_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; +wire \z80_|pla_decode_|Equal55~0_combout ; +wire \z80_|execute_|ctl_mRead~7_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; +wire \z80_|pin_control_|bus_db_pin_oe~17_combout ; +wire \z80_|execute_|fIOWrite~0_combout ; +wire \z80_|execute_|fMWrite~6_combout ; +wire \z80_|execute_|ctl_mWrite~8_combout ; +wire \z80_|execute_|fMWrite~5_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; +wire \z80_|execute_|fMRead~3_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; +wire \z80_|execute_|ctl_sw_4u~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ; +wire \z80_|execute_|fMWrite~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~15_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~16_combout ; +wire \z80_|execute_|ctl_mRead~9_combout ; +wire \z80_|pla_decode_|Equal24~0_combout ; +wire \z80_|execute_|nextM~4_combout ; +wire \z80_|pla_decode_|Equal3~0_combout ; +wire \z80_|execute_|ctl_eval_cond~0_combout ; +wire \z80_|execute_|ctl_iorw~12_combout ; +wire \z80_|execute_|ctl_iorw~8_combout ; +wire \z80_|execute_|ctl_iorw~9_combout ; +wire \z80_|memory_ifc_|DFFE_iorq_ff1~q ; +wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ; +wire \z80_|memory_ifc_|wait_iorq~feeder_combout ; +wire \z80_|memory_ifc_|wait_iorq~q ; +wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; +wire \z80_|memory_ifc_|iorq~0_combout ; +wire \z80_|pla_decode_|Equal33~2_combout ; +wire \z80_|execute_|ixy_d~17_combout ; +wire \z80_|execute_|ctl_mWrite~15_combout ; +wire \z80_|execute_|ctl_mWrite~18_combout ; +wire \z80_|execute_|ctl_mWrite~12_combout ; +wire \z80_|execute_|ctl_flags_alu~21_combout ; +wire \z80_|execute_|ctl_flags_alu~20_combout ; +wire \z80_|execute_|ctl_reg_in_hi~3_combout ; +wire \z80_|execute_|ctl_flags_alu~10_combout ; +wire \z80_|execute_|ctl_mWrite~10_combout ; +wire \z80_|execute_|ctl_mWrite~13_combout ; +wire \z80_|execute_|ixy_d~9_combout ; +wire \z80_|execute_|ctl_inc_cy~51_combout ; +wire \z80_|execute_|ctl_inc_dec~12_combout ; +wire \z80_|execute_|ctl_inc_dec~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; +wire \z80_|execute_|ctl_mWrite~11_combout ; +wire \z80_|execute_|ctl_mRead~25_combout ; +wire \z80_|execute_|ctl_flags_alu~22_combout ; +wire \z80_|execute_|ctl_mRead~24_combout ; +wire \z80_|execute_|ctl_bus_db_oe~7_combout ; +wire \z80_|execute_|ctl_mWrite~14_combout ; +wire \z80_|execute_|ixy_d~8_combout ; +wire \z80_|execute_|ctl_mWrite~16_combout ; +wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; +wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; +wire \z80_|memory_ifc_|wait_mwr~q ; +wire \z80_|memory_ifc_|mwr_wr~feeder_combout ; +wire \z80_|memory_ifc_|mwr_wr~q ; +wire \z80_|memory_ifc_|nWR_out~0_combout ; +wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; +wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; +wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; +wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; +wire \z80_|memory_ifc_|nRD_out~0_combout ; +wire \z80_|execute_|ctl_mRead~2_combout ; +wire \z80_|execute_|fIORead~0_combout ; +wire \z80_|execute_|ctl_iorw~10_combout ; +wire \z80_|pla_decode_|Equal1~4_combout ; +wire \z80_|execute_|ctl_alu_op_low~15_combout ; +wire \z80_|execute_|fIORead~1_combout ; +wire \z80_|execute_|fIORead~2_combout ; +wire \z80_|execute_|fIORead~3_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; +wire \z80_|execute_|ctl_im_we~combout ; +wire \z80_|interrupts_|im2~q ; +wire \z80_|execute_|ctl_mRead~10_combout ; +wire \z80_|pla_decode_|Equal33~3_combout ; +wire \z80_|pla_decode_|Equal6~1_combout ; +wire \z80_|execute_|ctl_mRead~30_combout ; +wire \z80_|execute_|ctl_mRead~31_combout ; +wire \z80_|execute_|ctl_ir_we~12_combout ; +wire \z80_|execute_|ctl_flags_bus~5_combout ; +wire \z80_|pla_decode_|Equal44~0_combout ; +wire \z80_|execute_|ctl_state_alu~6_combout ; +wire \z80_|execute_|fMRead~5_combout ; +wire \z80_|execute_|ctl_mRead~17_combout ; +wire \z80_|execute_|ctl_mRead~12_combout ; +wire \z80_|pla_decode_|Equal49~0_combout ; +wire \z80_|execute_|setM1~57_combout ; +wire \z80_|execute_|ctl_mRead~15_combout ; +wire \z80_|pla_decode_|Equal25~0_combout ; +wire \z80_|pla_decode_|Equal12~1_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; +wire \z80_|execute_|ixy_d~10_combout ; +wire \z80_|execute_|ixy_d~16_combout ; +wire \z80_|execute_|ctl_al_we~4_combout ; +wire \z80_|execute_|fMRead~4_combout ; +wire \z80_|pla_decode_|Equal29~0_combout ; +wire \z80_|execute_|setM1~38_combout ; +wire \z80_|pla_decode_|Equal35~0_combout ; +wire \z80_|execute_|pc_inc_hold~33_combout ; +wire \z80_|execute_|comb~1_combout ; +wire \z80_|execute_|ctl_mRead~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; +wire \z80_|pla_decode_|Equal40~2_combout ; +wire \z80_|execute_|setM1~36_combout ; +wire \z80_|execute_|pc_inc_hold~14_combout ; +wire \z80_|execute_|setM1~37_combout ; +wire \z80_|execute_|ctl_mRead~14_combout ; +wire \z80_|execute_|setM1~39_combout ; +wire \z80_|execute_|ctl_mRead~32_combout ; +wire \z80_|pla_decode_|Equal40~0_combout ; +wire \z80_|pla_decode_|Equal21~2_combout ; +wire \z80_|pla_decode_|Equal37~0_combout ; +wire \z80_|execute_|ctl_mRead~26_combout ; +wire \z80_|pla_decode_|Equal12~0_combout ; +wire \z80_|execute_|ctl_mRead~16_combout ; +wire \z80_|execute_|ctl_reg_in_hi~5_combout ; +wire \z80_|execute_|ctl_mRead~19_combout ; +wire \z80_|pla_decode_|Equal24~1_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~0_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~1_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; +wire \z80_|execute_|ctl_mRead~18_combout ; +wire \z80_|execute_|ctl_mRead~20_combout ; +wire \z80_|execute_|ctl_mRead~22_combout ; +wire \z80_|pla_decode_|Equal52~1_combout ; +wire \z80_|execute_|ctl_mRead~23_combout ; +wire \z80_|execute_|ctl_mRead~27_combout ; +wire \z80_|execute_|ctl_mRead~28_combout ; +wire \z80_|execute_|nextM~3_combout ; +wire \z80_|execute_|ctl_mRead~29_combout ; +wire \z80_|execute_|ctl_mRead~33_combout ; +wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; +wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; +wire \z80_|memory_ifc_|wait_mrd~q ; +wire \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ; +wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; +wire \z80_|memory_ifc_|nRD_out~1_combout ; +wire \z80_|memory_ifc_|nRD_out~2_combout ; +wire \Equal2~1_combout ; +wire \PS2_DAT~input_o ; +wire \reset~clkctrl_outclk ; +wire \ula_|ps2_keyboard_|bit_count~2_combout ; +wire \PS2_CLK~input_o ; +wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~0_combout ; +wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~1_combout ; +wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~q ; +wire \ula_|ps2_keyboard_|clk_edge~0_combout ; +wire \ula_|ps2_keyboard_|clk_edge~q ; +wire \ula_|ps2_keyboard_|bit_count~3_combout ; +wire \ula_|ps2_keyboard_|bit_count~1_combout ; +wire \ula_|ps2_keyboard_|bit_count~0_combout ; +wire \ula_|ps2_keyboard_|LessThan0~0_combout ; +wire \ula_|ps2_keyboard_|always1~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; +wire \ula_|zx_keyboard_|Equal0~0_combout ; +wire \ula_|zx_keyboard_|Equal0~1_combout ; +wire \ula_|ps2_keyboard_|WideXor0~1_combout ; +wire \ula_|ps2_keyboard_|WideXor0~0_combout ; +wire \ula_|ps2_keyboard_|WideXor0~2_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~q ; +wire \ula_|zx_keyboard_|released~0_combout ; +wire \ula_|zx_keyboard_|released~q ; +wire \ula_|zx_keyboard_|Equal0~2_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~50_combout ; +wire \ula_|zx_keyboard_|extended~0_combout ; +wire \ula_|zx_keyboard_|extended~q ; +wire \ula_|zx_keyboard_|keys[7][4]~15_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~52_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~53_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~q ; +wire \z80_|resets_|clrpc_int~0_combout ; +wire \z80_|resets_|clrpc_int~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; +wire \z80_|resets_|DFFE_intr_ff3~q ; +wire \z80_|resets_|clrpc~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; +wire \z80_|pla_decode_|Equal21~1_combout ; +wire \z80_|pla_decode_|Equal40~1_combout ; +wire \z80_|pla_decode_|Equal39~0_combout ; +wire \z80_|execute_|ctl_bus_db_oe~1_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; +wire \z80_|execute_|ctl_inc_dec~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; +wire \z80_|execute_|ctl_al_we~5_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; +wire \z80_|execute_|ctl_al_we~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; +wire \z80_|pla_decode_|Equal10~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~6_combout ; +wire \z80_|execute_|ctl_bus_db_oe~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ; +wire \z80_|reg_control_|reg_sel_pc~1_combout ; +wire \z80_|reg_control_|reg_sel_pc~0_combout ; +wire \z80_|reg_control_|reg_sel_pc~2_combout ; +wire \z80_|pla_decode_|Equal56~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~18_combout ; +wire \z80_|execute_|ctl_alu_op_low~17_combout ; +wire \z80_|execute_|ctl_alu_oe~4_combout ; +wire \z80_|execute_|ctl_reg_in_hi~4_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; +wire \z80_|execute_|ctl_inc_dec~3_combout ; +wire \z80_|execute_|fMRead~6_combout ; +wire \z80_|nM1_int~2_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_inc_cy~94_combout ; +wire \z80_|execute_|ctl_inc_cy~50_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; +wire \z80_|execute_|ctl_inc_cy~99_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; +wire \z80_|execute_|ctl_reg_out_hi~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_in_lo~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; +wire \z80_|pla_decode_|Equal1~5_combout ; +wire \z80_|execute_|ctl_alu_op_low~20_combout ; +wire \z80_|pla_decode_|Equal48~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; +wire \z80_|execute_|ctl_flags_bus~4_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; +wire \z80_|execute_|fMRead~7_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; +wire \z80_|execute_|ctl_reg_sys_we~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we~1_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; +wire \z80_|execute_|ctl_reg_sys_we~2_combout ; +wire \z80_|pla_decode_|Equal8~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~1_combout ; +wire \z80_|alu_control_|sel[1]~0_combout ; +wire \z80_|execute_|ctl_state_alu~7_combout ; +wire \z80_|execute_|ctl_state_alu~11_combout ; +wire \z80_|execute_|ctl_state_alu~9_combout ; +wire \z80_|execute_|ctl_state_alu~5_combout ; +wire \z80_|execute_|ctl_state_alu~10_combout ; +wire \z80_|execute_|ctl_state_alu~8_combout ; +wire \z80_|pla_decode_|Equal62~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~5_combout ; +wire \z80_|execute_|ctl_ir_we~11_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~7_combout ; +wire \z80_|execute_|ctl_bus_db_oe~3_combout ; +wire \z80_|execute_|ctl_flags_xy_we~19_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; +wire \z80_|execute_|ctl_alu_op_low~19_combout ; +wire \z80_|execute_|ctl_flags_bus~15_combout ; +wire \z80_|execute_|ctl_flags_bus~9_combout ; +wire \z80_|pla_decode_|Equal20~0_combout ; +wire \z80_|pla_decode_|Equal68~2_combout ; +wire \z80_|execute_|ctl_flags_bus~14_combout ; +wire \z80_|pla_decode_|Equal63~0_combout ; +wire \z80_|pla_decode_|Equal76~2_combout ; +wire \z80_|execute_|ctl_flags_bus~8_combout ; +wire \z80_|execute_|ctl_flags_bus~6_combout ; +wire \z80_|execute_|ctl_flags_bus~7_combout ; +wire \z80_|execute_|ctl_flags_bus~10_combout ; +wire \z80_|execute_|ctl_flags_xy_we~11_combout ; +wire \z80_|execute_|ctl_flags_hf2_we~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; +wire \z80_|execute_|ctl_reg_gp_sel~7_combout ; +wire \z80_|execute_|ctl_state_alu~12_combout ; +wire \z80_|pla_decode_|Equal62~3_combout ; +wire \z80_|execute_|ctl_flags_pf_we~6_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; +wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; +wire \z80_|execute_|ctl_flags_cf_we~7_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~10_combout ; +wire \z80_|execute_|ctl_flags_hf_we~5_combout ; +wire \z80_|execute_|ctl_flags_pf_we~11_combout ; +wire \z80_|execute_|ctl_flags_pf_we~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~3_combout ; +wire \z80_|pla_decode_|Equal10~1_combout ; +wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; +wire \z80_|pla_decode_|Equal69~0_combout ; +wire \z80_|execute_|ctl_flags_pf_we~7_combout ; +wire \z80_|execute_|ctl_flags_pf_we~8_combout ; +wire \z80_|execute_|ctl_flags_pf_we~9_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~13_combout ; +wire \z80_|execute_|ctl_flags_pf_we~10_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; +wire \z80_|execute_|ctl_flags_xy_we~18_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~21_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~20_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ; +wire \z80_|execute_|ctl_reg_out_lo~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; +wire \z80_|execute_|ctl_al_we~14_combout ; +wire \z80_|execute_|ctl_sw_4d~1_combout ; +wire \z80_|execute_|ctl_alu_oe~5_combout ; +wire \z80_|execute_|setM1~47_combout ; +wire \z80_|execute_|ctl_sw_4d~0_combout ; +wire \z80_|execute_|ctl_sw_4d~4_combout ; +wire \z80_|execute_|fMRead~8_combout ; +wire \z80_|execute_|fMRead~9_combout ; +wire \z80_|execute_|fMRead~10_combout ; +wire \z80_|execute_|ctl_sw_4d~2_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; +wire \z80_|pla_decode_|Equal4~0_combout ; +wire \z80_|execute_|setM1~41_combout ; +wire \z80_|pla_decode_|Equal2~1_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_sw_1d~4_combout ; +wire \z80_|execute_|ctl_sw_4d~3_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; +wire \z80_|execute_|ctl_sw_4d~5_combout ; +wire \z80_|execute_|ctl_sw_4d~6_combout ; +wire \z80_|reg_control_|reg_sel_pc~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; +wire \z80_|execute_|ctl_sw_4u~1_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; +wire \z80_|reg_control_|reg_sel_pc~3_combout ; +wire \z80_|reg_control_|reg_sel_pc~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; +wire \z80_|pla_decode_|Equal1~6_combout ; +wire \z80_|reg_control_|bank_exx~2_combout ; +wire \z80_|reg_control_|bank_exx~q ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_sw_2u~1_combout ; +wire \z80_|execute_|ctl_alu_oe~3_combout ; +wire \z80_|execute_|ctl_sw_2u~4_combout ; +wire \z80_|execute_|setM1~56_combout ; +wire \z80_|execute_|ctl_sw_2u~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; +wire \z80_|execute_|ctl_state_alu~13_combout ; +wire \z80_|execute_|ctl_flags_xy_we~12_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; wire \z80_|execute_|ctl_inc_cy~61_combout ; -wire \z80_|execute_|ctl_inc_cy~62_combout ; -wire \z80_|execute_|ctl_inc_cy~70_combout ; -wire \z80_|execute_|ctl_inc_cy~85_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[0]~3_combout ; -wire \z80_|address_latch_|Q[0]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; -wire \z80_|reg_file_|db_lo_as[1]~4_combout ; -wire \z80_|reg_file_|db_lo_as[1]~5_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; -wire \z80_|reg_file_|db_lo_as[1]~6_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[2]~9_combout ; -wire \z80_|address_latch_|Q[2]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; wire \z80_|execute_|ctl_inc_cy~86_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|execute_|ctl_inc_dec~11_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; -wire \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; -wire \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ; +wire \z80_|execute_|ctl_inc_cy~87_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~52_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~49_combout ; +wire \z80_|execute_|ctl_reg_gp_we~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; +wire \z80_|execute_|ctl_alu_oe~7_combout ; +wire \z80_|execute_|ctl_alu_oe~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_flags_oe~0_combout ; +wire \z80_|execute_|ctl_flags_oe~1_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~8_combout ; +wire \z80_|execute_|setM1~48_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; +wire \z80_|execute_|nextM~2_combout ; +wire \z80_|execute_|setM1~49_combout ; +wire \z80_|execute_|ctl_reg_in_hi~12_combout ; +wire \z80_|execute_|ctl_sw_1d~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; +wire \z80_|execute_|ctl_sw_2u~2_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; +wire \z80_|execute_|nextM~11_combout ; +wire \z80_|execute_|ctl_reg_use_sp~0_combout ; +wire \z80_|execute_|ctl_reg_use_sp~2_combout ; +wire \z80_|execute_|ctl_reg_use_sp~3_combout ; +wire \z80_|execute_|ctl_sw_1d~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~13_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; +wire \z80_|execute_|setM1~30_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~14_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~22_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; +wire \z80_|reg_control_|reg_sel_de2~2_combout ; +wire \z80_|reg_control_|reg_sel_de2~4_combout ; +wire \z80_|pla_decode_|Equal2~2_combout ; +wire \z80_|reg_control_|bank_hl_de1~0_combout ; +wire \z80_|reg_control_|bank_hl_de1~q ; +wire \z80_|reg_control_|reg_sel_hl~0_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~50_combout ; +wire \z80_|execute_|ctl_reg_gp_we~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ; +wire \z80_|execute_|rsel3~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; +wire \z80_|execute_|rsel0~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; +wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; +wire \z80_|execute_|ctl_reg_in_hi~7_combout ; +wire \z80_|execute_|ctl_reg_gp_we~6_combout ; +wire \z80_|execute_|ctl_reg_gp_we~9_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; +wire \z80_|execute_|ctl_reg_gp_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; +wire \z80_|execute_|ctl_reg_gp_we~5_combout ; +wire \z80_|execute_|ctl_reg_gp_we~7_combout ; +wire \z80_|execute_|ctl_sw_4u~2_combout ; +wire \z80_|execute_|ctl_sw_4u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_we~8_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; +wire \z80_|reg_control_|bank_hl_de2~0_combout ; +wire \z80_|reg_control_|bank_hl_de2~q ; +wire \z80_|reg_control_|reg_sel_hl2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; +wire \z80_|execute_|ctl_flags_sz_we~1_combout ; +wire \z80_|execute_|ctl_reg_in_hi~8_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ; +wire \z80_|execute_|ctl_reg_in_hi~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; +wire \z80_|execute_|ctl_reg_in_lo~8_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; +wire \z80_|execute_|ctl_sw_2d~6_combout ; +wire \z80_|execute_|ctl_sw_2d~7_combout ; +wire \z80_|execute_|ctl_sw_2d~8_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; +wire \z80_|execute_|ctl_sw_2d~4_combout ; +wire \z80_|execute_|fMRead~18_combout ; +wire \z80_|execute_|fMRead~19_combout ; +wire \z80_|execute_|fMRead~20_combout ; +wire \z80_|execute_|ctl_reg_in_hi~6_combout ; +wire \z80_|execute_|fMRead~21_combout ; +wire \z80_|execute_|ctl_sw_2d~5_combout ; +wire \z80_|execute_|ctl_sw_2d~9_combout ; +wire \z80_|execute_|ctl_sw_1d~5_combout ; +wire \z80_|execute_|ctl_sw_1d~6_combout ; +wire \z80_|execute_|ctl_sw_1d~7_combout ; +wire \z80_|execute_|ctl_alu_op_low~41_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op_low~26_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; +wire \z80_|execute_|ctl_alu_op_low~27_combout ; +wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; +wire \z80_|pla_decode_|Equal61~2_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; +wire \z80_|execute_|ctl_alu_core_hf~12_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; +wire \z80_|execute_|ctl_flags_sz_we~3_combout ; +wire \z80_|execute_|ctl_flags_alu~13_combout ; +wire \z80_|execute_|ctl_flags_alu~14_combout ; +wire \z80_|execute_|ctl_flags_alu~15_combout ; +wire \z80_|execute_|ctl_reg_use_sp~1_combout ; +wire \z80_|execute_|ctl_alu_op_low~16_combout ; +wire \z80_|execute_|ctl_flags_xy_we~17_combout ; +wire \z80_|execute_|ctl_flags_sz_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ; +wire \z80_|execute_|ctl_alu_op_low~39_combout ; +wire \z80_|execute_|ctl_flags_alu~16_combout ; +wire \z80_|execute_|ctl_flags_alu~17_combout ; +wire \z80_|execute_|ctl_alu_op_low~23_combout ; +wire \z80_|execute_|ctl_flags_alu~18_combout ; +wire \z80_|execute_|ctl_flags_alu~11_combout ; +wire \z80_|execute_|ctl_alu_core_R~0_combout ; +wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~1_combout ; +wire \z80_|execute_|ctl_flags_alu~23_combout ; +wire \z80_|execute_|ctl_flags_alu~12_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~11_combout ; +wire \z80_|execute_|ctl_alu_oe~6_combout ; +wire \z80_|execute_|setM1~17_combout ; +wire \z80_|execute_|ctl_alu_op_low~22_combout ; +wire \z80_|execute_|ctl_flags_xy_we~6_combout ; +wire \z80_|execute_|ctl_flags_xy_we~7_combout ; +wire \z80_|execute_|ctl_flags_sz_we~2_combout ; +wire \z80_|execute_|ctl_flags_alu~19_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; +wire \z80_|execute_|fMRead~26_combout ; +wire \z80_|execute_|ctl_flags_bus~11_combout ; +wire \z80_|execute_|ctl_flags_bus~12_combout ; +wire \z80_|execute_|ctl_flags_bus~13_combout ; +wire \z80_|execute_|ctl_flags_bus~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~12_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~18_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; +wire \z80_|execute_|ctl_alu_op_low~24_combout ; +wire \z80_|execute_|ctl_alu_op_low~25_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~17_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; +wire \z80_|execute_|ctl_flags_xy_we~10_combout ; +wire \z80_|execute_|ctl_flags_cf_we~2_combout ; +wire \z80_|execute_|ctl_alu_core_S~6_combout ; +wire \z80_|execute_|ctl_alu_core_S~7_combout ; +wire \z80_|execute_|ctl_alu_core_S~4_combout ; +wire \z80_|execute_|ctl_alu_core_S~5_combout ; +wire \z80_|execute_|ctl_alu_oe~15_combout ; +wire \z80_|execute_|ctl_alu_res_oe~0_combout ; +wire \z80_|execute_|ctl_alu_res_oe~1_combout ; +wire \z80_|execute_|ctl_alu_res_oe~2_combout ; +wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; +wire \z80_|alu_|db_high[3]~0_combout ; +wire \z80_|execute_|ctl_reg_out_hi~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ; +wire \z80_|execute_|ctl_sw_2u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; +wire \z80_|execute_|ctl_sw_2u~6_combout ; +wire \z80_|execute_|ctl_reg_out_lo~2_combout ; +wire \z80_|execute_|ctl_reg_out_hi~5_combout ; +wire \z80_|execute_|ctl_reg_out_hi~6_combout ; +wire \z80_|execute_|ctl_reg_out_hi~7_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~40_combout ; +wire \z80_|execute_|ctl_reg_use_sp~4_combout ; +wire \z80_|execute_|ctl_reg_use_sp~5_combout ; +wire \z80_|execute_|ctl_reg_use_sp~6_combout ; +wire \z80_|reg_control_|bank_af~0_combout ; +wire \z80_|reg_control_|bank_af~q ; +wire \z80_|reg_control_|reg_sel_af~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~41_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ; -wire \z80_|execute_|ctl_reg_in_hi~11_combout ; -wire \z80_|execute_|ctl_reg_in_hi~12_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~44_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~32_combout ; +wire \z80_|reg_control_|reg_sel_de2~3_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_control_|reg_sel_de~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~31_combout ; wire \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ; +wire \z80_|reg_control_|reg_sel_iy~2_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~43_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~34_combout ; +wire \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; +wire \z80_|execute_|ctl_sw_4u~4_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~45_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~36_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~42_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~46_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~47_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~33_combout ; +wire \z80_|reg_control_|reg_sel_af2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; +wire \z80_|execute_|ctl_reg_in_hi~10_combout ; +wire \z80_|execute_|ctl_reg_in_hi~11_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~35_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~37_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~38_combout ; +wire \z80_|execute_|ctl_sw_4u~5_combout ; +wire \z80_|execute_|ctl_sw_4u~6_combout ; wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; -wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; -wire \z80_|reg_file_|db_hi_as[1]~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; -wire \z80_|reg_file_|db_hi_as[1]~1_combout ; -wire \z80_|reg_file_|db_hi_as[0]~2_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; -wire \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; -wire \z80_|reg_file_|db_hi_as[0]~4_combout ; -wire \z80_|reg_file_|db_hi_as[0]~5_combout ; -wire \z80_|reg_file_|db_hi_as[0]~6_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[1]~3_combout ; -wire \z80_|address_latch_|Q[9]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~32_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~35_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~34_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~33_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~36_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~37_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~31_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~38_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~39_combout ; -wire \z80_|reg_file_|db_hi_as[2]~7_combout ; -wire \z80_|reg_file_|db_hi_as[2]~8_combout ; -wire \z80_|reg_file_|db_hi_as[2]~9_combout ; -wire \z80_|address_latch_|Q[10]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; -wire \z80_|reg_file_|db_hi_as[3]~10_combout ; -wire \z80_|reg_file_|db_hi_as[3]~11_combout ; -wire \z80_|reg_file_|db_hi_as[3]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~48_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; -wire \z80_|alu_|alu_op1[3]~3_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; -wire \z80_|execute_|ctl_alu_core_R~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~5_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~20_combout ; -wire \z80_|execute_|ctl_state_alu~12_combout ; -wire \z80_|execute_|ctl_alu_core_hf~18_combout ; -wire \z80_|pla_decode_|Equal61~2_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~21_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~20_combout ; -wire \z80_|execute_|ctl_flags_sz_we~4_combout ; -wire \z80_|pla_decode_|Equal71~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; -wire \z80_|execute_|ctl_alu_op_low~31_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ; -wire \z80_|pla_decode_|Equal72~2_combout ; -wire \z80_|pla_decode_|Equal73~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~0_combout ; -wire \z80_|execute_|ctl_flags_nf_we~1_combout ; -wire \z80_|execute_|ctl_flags_nf_we~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~3_combout ; -wire \z80_|execute_|ctl_flags_sz_we~5_combout ; -wire \z80_|execute_|ctl_flags_sz_we~6_combout ; -wire \z80_|execute_|ctl_flags_nf_we~4_combout ; -wire \z80_|execute_|setM1~15_combout ; -wire \z80_|execute_|setM1~16_combout ; -wire \z80_|execute_|ctl_flags_xy_we~6_combout ; -wire \z80_|execute_|ctl_flags_xy_we~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~2_combout ; -wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~1_combout ; -wire \z80_|execute_|ctl_flags_alu~7_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~8_combout ; -wire \z80_|execute_|ctl_flags_alu~8_combout ; -wire \z80_|execute_|ctl_flags_xy_we~16_combout ; -wire \z80_|execute_|ctl_flags_alu~12_combout ; -wire \z80_|execute_|ctl_flags_alu~13_combout ; -wire \z80_|execute_|ctl_flags_alu~14_combout ; -wire \z80_|execute_|ctl_flags_alu~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~19_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; -wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~18_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; -wire \z80_|alu_|alu_op2[1]~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|execute_|ctl_alu_core_S~9_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ; -wire \z80_|alu_|alu_op2[0]~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ; -wire \z80_|execute_|ctl_alu_core_S~8_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|execute_|ctl_alu_core_hf~21_combout ; -wire \z80_|execute_|ctl_alu_core_hf~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~19_combout ; -wire \z80_|execute_|ctl_alu_op_low~27_combout ; -wire \z80_|execute_|ctl_alu_op_low~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~23_combout ; -wire \z80_|execute_|ctl_alu_core_hf~37_combout ; -wire \z80_|execute_|ctl_alu_core_hf~38_combout ; -wire \z80_|execute_|ctl_alu_core_hf~24_combout ; -wire \z80_|execute_|ctl_alu_core_hf~25_combout ; -wire \z80_|execute_|ctl_alu_core_hf~26_combout ; -wire \z80_|execute_|ctl_alu_core_hf~27_combout ; -wire \z80_|execute_|ctl_alu_core_hf~28_combout ; -wire \z80_|execute_|ctl_alu_op_low~30_combout ; -wire \z80_|execute_|ctl_alu_core_hf~34_combout ; -wire \z80_|execute_|ctl_alu_core_hf~32_combout ; -wire \z80_|execute_|ctl_alu_core_hf~43_combout ; -wire \z80_|execute_|ctl_alu_core_hf~33_combout ; -wire \z80_|execute_|ctl_alu_core_hf~42_combout ; -wire \z80_|execute_|ctl_alu_core_hf~35_combout ; -wire \z80_|execute_|ctl_alu_core_hf~41_combout ; -wire \z80_|execute_|ctl_alu_core_hf~30_combout ; -wire \z80_|execute_|ctl_mWrite~10_combout ; -wire \z80_|execute_|ctl_alu_core_hf~31_combout ; -wire \z80_|execute_|ctl_alu_core_hf~44_combout ; -wire \z80_|execute_|ctl_alu_core_hf~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~36_combout ; -wire \z80_|execute_|ctl_alu_core_hf~39_combout ; -wire \z80_|execute_|ctl_alu_core_hf~40_combout ; -wire \z80_|execute_|ctl_flags_hf_we~2_combout ; -wire \z80_|execute_|ctl_alu_core_R~2_combout ; -wire \z80_|execute_|ctl_alu_core_R~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ; -wire \z80_|alu_|alu_op2[3]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; -wire \z80_|execute_|ctl_flags_hf_we~3_combout ; -wire \z80_|execute_|ctl_flags_hf_we~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; -wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~13_combout ; -wire \z80_|alu_flags_|flags_hf~combout ; -wire \z80_|alu_control_|alu_core_cf_in~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; -wire \z80_|alu_|db_high[0]~23_combout ; -wire \z80_|address_latch_|Q[12]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[4]~16_combout ; -wire \z80_|reg_file_|db_hi_as[4]~17_combout ; -wire \z80_|reg_file_|db_hi_as[4]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~62_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~63_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~61_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~64_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~58_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~65_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~66_combout ; -wire \z80_|alu_|db[4]~16_combout ; -wire \z80_|alu_|db[7]~26_combout ; -wire \z80_|alu_|db[4]~17_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; -wire \z80_|alu_|db_high[0]~24_combout ; -wire \z80_|alu_|db_high[0]~21_combout ; -wire \z80_|alu_|db_high[0]~22_combout ; -wire \z80_|alu_|db_high[0]~25_combout ; -wire \z80_|alu_|db_high[0]~26_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; -wire \z80_|alu_|alu_op1[0]~1_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; -wire \z80_|alu_|alu_op1[1]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; -wire \z80_|alu_|alu_op1[2]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~5_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~69_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~70_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~72_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~71_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~73_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~67_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~68_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~74_combout ; -wire \z80_|reg_file_|db_hi_as[7]~19_combout ; -wire \z80_|reg_file_|db_hi_as[7]~20_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~54_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~53_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~51_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~52_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~55_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~49_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~50_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~56_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~57_combout ; -wire \z80_|reg_file_|db_hi_as[5]~13_combout ; -wire \z80_|reg_file_|db_hi_as[5]~14_combout ; -wire \z80_|reg_file_|db_hi_as[5]~15_combout ; -wire \z80_|address_latch_|Q[13]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~76_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~80_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~79_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~78_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~81_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~82_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~77_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~83_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~84_combout ; -wire \z80_|reg_file_|db_hi_as[6]~22_combout ; -wire \z80_|reg_file_|db_hi_as[6]~23_combout ; -wire \z80_|reg_file_|db_hi_as[6]~24_combout ; -wire \z80_|address_latch_|Q[14]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|reg_file_|db_hi_as[7]~21_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~75_combout ; -wire \z80_|alu_|db[7]~20_combout ; -wire \z80_|alu_|db[7]~21_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; -wire \z80_|execute_|ctl_flags_cf_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf_we~5_combout ; -wire \z80_|execute_|ctl_flags_cf_we~3_combout ; -wire \z80_|execute_|ctl_flags_cf_we~6_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~2_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; -wire \z80_|alu_|db_high[3]~5_combout ; -wire \z80_|alu_|db_high[3]~6_combout ; -wire \z80_|alu_|db_high[3]~4_combout ; -wire \z80_|alu_|db_high[3]~27_combout ; -wire \z80_|alu_|db_high[3]~7_combout ; -wire \z80_|alu_|db_high[3]~8_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ; -wire \z80_|alu_|db_low[3]~9_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; -wire \z80_|alu_|db_low[3]~10_combout ; -wire \z80_|alu_|db_low[3]~7_combout ; -wire \z80_|alu_|db_low[3]~8_combout ; -wire \z80_|alu_|db_low[3]~11_combout ; -wire \z80_|alu_|db_low[3]~25_combout ; -wire \z80_|alu_|db[3]~10_combout ; -wire \z80_|alu_|db[3]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~39_combout ; +wire \z80_|alu_|db[3]~13_combout ; +wire \z80_|execute_|ctl_sw_2d~12_combout ; +wire \z80_|execute_|ctl_sw_2d~10_combout ; +wire \z80_|execute_|ctl_sw_2d~14_combout ; +wire \z80_|execute_|ctl_sw_2d~11_combout ; +wire \z80_|execute_|ctl_sw_2d~13_combout ; +wire \z80_|execute_|ctl_bus_db_we~5_combout ; +wire \z80_|execute_|ctl_alu_oe~9_combout ; +wire \z80_|execute_|ctl_alu_oe~10_combout ; wire \z80_|execute_|ctl_sw_2u~7_combout ; -wire \z80_|execute_|setM1~49_combout ; -wire \z80_|execute_|ctl_flags_oe~2_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|execute_|ctl_flags_sz_we~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ; wire \z80_|execute_|ctl_flags_xy_we~13_combout ; wire \z80_|execute_|ctl_flags_xy_we~14_combout ; wire \z80_|execute_|ctl_flags_xy_we~15_combout ; +wire \z80_|execute_|ctl_flags_sz_we~5_combout ; +wire \z80_|execute_|ctl_flags_sz_we~6_combout ; +wire \z80_|execute_|ctl_flags_sz_we~7_combout ; +wire \z80_|execute_|ctl_flags_xy_we~16_combout ; wire \z80_|alu_flags_|flags_xf~q ; -wire \z80_|alu_control_|db[3]~33_combout ; +wire \z80_|execute_|setM1~50_combout ; +wire \z80_|execute_|ctl_flags_oe~2_combout ; +wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; +wire \z80_|alu_control_|db[3]~34_combout ; +wire \z80_|sw1_|db_down[3]~3_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~42_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~91_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; +wire \z80_|reg_file_|db_lo_as[3]~10_combout ; +wire \z80_|reg_file_|db_lo_as[3]~11_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; +wire \z80_|execute_|ctl_inc_cy~88_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; +wire \z80_|execute_|ctl_inc_dec~6_combout ; +wire \z80_|reg_file_|db_lo_as[0]~2_combout ; +wire \z80_|execute_|pc_inc_hold~25_combout ; +wire \z80_|execute_|ctl_inc_cy~67_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~64_combout ; +wire \z80_|execute_|ctl_inc_cy~65_combout ; +wire \z80_|execute_|ctl_inc_cy~63_combout ; +wire \z80_|execute_|ctl_inc_cy~66_combout ; +wire \z80_|execute_|ctl_inc_cy~68_combout ; +wire \z80_|execute_|ctl_inc_cy~58_combout ; +wire \z80_|execute_|ctl_inc_cy~59_combout ; +wire \z80_|execute_|ctl_inc_cy~60_combout ; +wire \z80_|execute_|ctl_inc_cy~57_combout ; +wire \z80_|execute_|ctl_inc_cy~62_combout ; +wire \z80_|execute_|pc_inc_hold~18_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; +wire \z80_|execute_|pc_inc_hold~17_combout ; +wire \z80_|execute_|pc_inc_hold~19_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; +wire \z80_|execute_|pc_inc_hold~20_combout ; +wire \z80_|execute_|pc_inc_hold~36_combout ; +wire \z80_|execute_|pc_inc_hold~15_combout ; +wire \z80_|execute_|pc_inc_hold~16_combout ; +wire \z80_|execute_|pc_inc_hold~21_combout ; +wire \z80_|execute_|ctl_inc_cy~69_combout ; +wire \z80_|execute_|ctl_inc_cy~52_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; +wire \z80_|execute_|pc_inc_hold~34_combout ; +wire \z80_|execute_|pc_inc_hold~22_combout ; +wire \z80_|execute_|pc_inc_hold~23_combout ; +wire \z80_|execute_|pc_inc_hold~35_combout ; +wire \z80_|execute_|pc_inc_hold~24_combout ; +wire \z80_|execute_|ctl_inc_cy~53_combout ; +wire \z80_|execute_|ctl_inc_cy~54_combout ; +wire \z80_|execute_|ctl_inc_cy~74_combout ; +wire \z80_|execute_|ctl_inc_cy~75_combout ; +wire \z80_|execute_|ctl_inc_cy~73_combout ; +wire \z80_|execute_|ctl_inc_cy~76_combout ; +wire \z80_|execute_|ctl_inc_cy~95_combout ; +wire \z80_|execute_|ctl_inc_cy~72_combout ; +wire \z80_|execute_|pc_inc_hold~27_combout ; +wire \z80_|execute_|ctl_inc_cy~77_combout ; +wire \z80_|execute_|ctl_inc_cy~78_combout ; +wire \z80_|execute_|ctl_inc_cy~79_combout ; +wire \z80_|execute_|ctl_inc_cy~70_combout ; +wire \z80_|execute_|ctl_inc_cy~71_combout ; +wire \z80_|execute_|ctl_inc_cy~80_combout ; +wire \z80_|execute_|ctl_inc_cy~55_combout ; +wire \z80_|execute_|pc_inc_hold~26_combout ; +wire \z80_|execute_|ctl_inc_cy~56_combout ; +wire \z80_|execute_|ctl_inc_cy~81_combout ; +wire \z80_|execute_|ctl_inc_cy~85_combout ; +wire \z80_|execute_|ctl_inc_cy~89_combout ; +wire \z80_|execute_|ctl_inc_cy~90_combout ; +wire \z80_|execute_|ctl_inc_cy~91_combout ; +wire \z80_|execute_|ctl_inc_cy~83_combout ; +wire \z80_|execute_|ctl_inc_cy~84_combout ; +wire \z80_|execute_|ctl_inc_cy~100_combout ; +wire \z80_|execute_|ctl_inc_cy~92_combout ; +wire \z80_|execute_|pc_inc_hold~28_combout ; +wire \z80_|execute_|ctl_inc_cy~82_combout ; +wire \z80_|execute_|pc_inc_hold~29_combout ; +wire \z80_|execute_|pc_inc_hold~30_combout ; +wire \z80_|execute_|pc_inc_hold~31_combout ; +wire \z80_|execute_|pc_inc_hold~32_combout ; +wire \z80_|execute_|ctl_inc_cy~93_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; +wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; +wire \z80_|alu_control_|db[0]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; +wire \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ; +wire \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; +wire \z80_|execute_|ctl_inc_dec~8_combout ; +wire \z80_|execute_|ctl_inc_dec~9_combout ; +wire \z80_|execute_|ctl_inc_dec~10_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|execute_|ctl_inc_dec~7_combout ; +wire \z80_|execute_|ctl_inc_dec~11_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; +wire \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; +wire \z80_|alu_|db_low[2]~9_combout ; +wire \z80_|alu_|db_low[2]~10_combout ; +wire \z80_|alu_|db_high[3]~1_combout ; +wire \z80_|execute_|ctl_flags_pf_we~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ; +wire \z80_|execute_|ctl_alu_op_low~38_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ; +wire \z80_|execute_|ctl_alu_core_S~8_combout ; +wire \z80_|execute_|ctl_alu_core_R~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~3_combout ; +wire \z80_|execute_|ctl_alu_core_R~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; +wire \z80_|execute_|ctl_alu_core_S~11_combout ; +wire \z80_|execute_|ctl_alu_core_S~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~combout ; +wire \z80_|pla_decode_|Equal73~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~5_combout ; +wire \z80_|execute_|ctl_alu_core_R~combout ; +wire \z80_|execute_|ctl_alu_op_low~28_combout ; +wire \z80_|execute_|ctl_alu_op_low~29_combout ; +wire \z80_|execute_|ctl_alu_op_low~30_combout ; +wire \z80_|execute_|ctl_alu_op_low~31_combout ; +wire \z80_|execute_|ctl_alu_op_low~32_combout ; +wire \z80_|execute_|ctl_alu_op_low~40_combout ; +wire \z80_|execute_|ctl_alu_op_low~33_combout ; +wire \z80_|execute_|ctl_alu_op_low~combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~59_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~58_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~61_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~62_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~63_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~60_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~64_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~65_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; +wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; +wire \z80_|reg_file_|db_hi_as[7]~16_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; +wire \z80_|reg_file_|db_hi_as[7]~17_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; +wire \z80_|reg_file_|db_hi_as[1]~0_combout ; +wire \z80_|reg_file_|db_hi_as[1]~1_combout ; +wire \z80_|execute_|ctl_al_we~6_combout ; +wire \z80_|execute_|ctl_al_we~9_combout ; +wire \z80_|execute_|ctl_al_we~10_combout ; +wire \z80_|execute_|ctl_al_we~7_combout ; +wire \z80_|execute_|ctl_al_we~8_combout ; +wire \z80_|execute_|ctl_al_we~11_combout ; +wire \z80_|execute_|ctl_al_we~12_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~82_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~81_combout ; +wire \z80_|alu_control_|db[6]~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|execute_|ctl_flags_sz_we~8_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; +wire \z80_|alu_control_|db[7]~18_combout ; +wire \z80_|alu_control_|db[7]~19_combout ; +wire \z80_|alu_control_|db[7]~20_combout ; +wire \z80_|alu_control_|db[7]~37_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; +wire \z80_|reg_file_|db_lo_as[7]~22_combout ; +wire \z80_|reg_file_|db_lo_as[7]~23_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[7]~24_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[1]~3_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~44_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~45_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~42_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~43_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~46_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~40_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~41_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~47_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~48_combout ; +wire \z80_|reg_file_|db_hi_as[2]~10_combout ; +wire \z80_|reg_file_|db_hi_as[2]~11_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[2]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~50_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~49_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~51_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~52_combout ; +wire \z80_|alu_|db[4]~8_combout ; +wire \z80_|alu_|db[4]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~53_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~54_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~55_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~56_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~57_combout ; +wire \z80_|reg_file_|db_hi_as[4]~13_combout ; +wire \z80_|reg_file_|db_hi_as[4]~14_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[4]~15_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~76_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~77_combout ; +wire \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~79_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; +wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; +wire \z80_|alu_|db_low[1]~18_combout ; +wire \z80_|alu_|db_low[1]~19_combout ; +wire \z80_|alu_|db_low[1]~16_combout ; +wire \z80_|alu_|db_low[1]~15_combout ; +wire \z80_|alu_|db_low[1]~17_combout ; +wire \z80_|alu_|db_low[1]~20_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; +wire \z80_|alu_|alu_op2[1]~2_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; +wire \z80_|alu_|db_high[2]~10_combout ; +wire \z80_|alu_|db_high[2]~8_combout ; +wire \z80_|alu_|db_high[2]~9_combout ; +wire \z80_|alu_|db_high[2]~11_combout ; +wire \z80_|alu_|db_high[2]~12_combout ; +wire \z80_|alu_|db_high[2]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~68_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~67_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~72_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~70_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~69_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~71_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~73_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~74_combout ; +wire \z80_|reg_file_|db_hi_as[6]~19_combout ; +wire \z80_|reg_file_|db_hi_as[6]~20_combout ; +wire \z80_|reg_file_|db_hi_as[6]~21_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~75_combout ; +wire \z80_|alu_|db[6]~21_combout ; +wire \z80_|alu_|db[6]~22_combout ; +wire \z80_|alu_|db_high[1]~16_combout ; +wire \z80_|alu_|db_high[1]~17_combout ; +wire \z80_|alu_|db_high[1]~14_combout ; +wire \z80_|alu_|db_high[1]~15_combout ; +wire \z80_|alu_|db_high[1]~18_combout ; +wire \z80_|alu_|db_high[1]~19_combout ; +wire \z80_|alu_|db[5]~23_combout ; +wire \z80_|alu_|db[5]~24_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~80_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~81_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~78_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~82_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~83_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~84_combout ; +wire \z80_|reg_file_|db_hi_as[5]~22_combout ; +wire \z80_|reg_file_|db_hi_as[5]~23_combout ; +wire \z80_|reg_file_|db_hi_as[5]~24_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|reg_file_|db_hi_as[7]~18_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~66_combout ; +wire \z80_|alu_|db[7]~19_combout ; +wire \z80_|alu_|db[7]~20_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ; +wire \z80_|alu_|alu_op1[3]~0_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ; +wire \z80_|alu_|alu_op2[2]~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; +wire \z80_|execute_|ctl_flags_cf_we~3_combout ; +wire \z80_|execute_|ctl_flags_hf_we~2_combout ; +wire \z80_|execute_|ctl_flags_cf_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf_we~5_combout ; +wire \z80_|execute_|ctl_flags_cf_we~6_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~6_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~5_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; +wire \z80_|alu_|db_low[0]~21_combout ; +wire \z80_|alu_|db_low[0]~22_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ; +wire \z80_|alu_|db_low[0]~24_combout ; +wire \z80_|alu_|db_low[0]~23_combout ; +wire \z80_|alu_|db_low[0]~25_combout ; +wire \z80_|alu_|db_low[0]~27_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ; +wire \z80_|alu_|alu_op2[0]~3_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|execute_|ctl_alu_op_low~34_combout ; +wire \z80_|execute_|ctl_alu_op_low~36_combout ; +wire \z80_|execute_|ctl_alu_op_low~35_combout ; +wire \z80_|execute_|ctl_alu_core_hf~13_combout ; +wire \z80_|execute_|ctl_alu_core_hf~14_combout ; +wire \z80_|execute_|ctl_alu_core_hf~15_combout ; +wire \z80_|execute_|ctl_alu_core_hf~16_combout ; +wire \z80_|execute_|ctl_alu_core_hf~17_combout ; +wire \z80_|execute_|ctl_alu_core_hf~37_combout ; +wire \z80_|execute_|ctl_alu_core_hf~38_combout ; +wire \z80_|execute_|ctl_alu_core_hf~36_combout ; +wire \z80_|execute_|ctl_alu_core_hf~23_combout ; +wire \z80_|execute_|ctl_alu_core_hf~34_combout ; +wire \z80_|execute_|ctl_alu_core_hf~29_combout ; +wire \z80_|execute_|ctl_alu_core_hf~26_combout ; +wire \z80_|execute_|ctl_alu_core_hf~35_combout ; +wire \z80_|execute_|ctl_alu_core_hf~27_combout ; +wire \z80_|execute_|ctl_alu_core_hf~28_combout ; +wire \z80_|execute_|ctl_alu_core_hf~30_combout ; +wire \z80_|execute_|ctl_alu_op_low~37_combout ; +wire \z80_|execute_|ctl_alu_core_hf~24_combout ; +wire \z80_|execute_|ctl_alu_core_hf~25_combout ; +wire \z80_|execute_|ctl_alu_core_hf~31_combout ; +wire \z80_|execute_|ctl_alu_core_hf~20_combout ; +wire \z80_|execute_|ctl_alu_core_hf~21_combout ; +wire \z80_|execute_|ctl_alu_core_hf~18_combout ; +wire \z80_|execute_|ctl_alu_core_hf~19_combout ; +wire \z80_|execute_|ctl_alu_core_hf~22_combout ; +wire \z80_|execute_|ctl_alu_core_hf~32_combout ; +wire \z80_|execute_|ctl_alu_core_hf~33_combout ; +wire \z80_|alu_control_|alu_core_cf_in~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; +wire \z80_|alu_|db_high[0]~21_combout ; +wire \z80_|alu_|db_high[0]~22_combout ; +wire \z80_|alu_|db_high[0]~23_combout ; +wire \z80_|alu_|db_high[0]~20_combout ; +wire \z80_|alu_|db_high[0]~24_combout ; +wire \z80_|alu_|db_high[0]~25_combout ; +wire \z80_|alu_|alu_op1[0]~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; +wire \z80_|alu_|db_low[2]~11_combout ; +wire \z80_|alu_|db_low[2]~12_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; +wire \z80_|alu_|db_low[2]~13_combout ; +wire \z80_|alu_|db_low[2]~14_combout ; +wire \z80_|alu_|db[2]~11_combout ; +wire \z80_|alu_|db[2]~12_combout ; +wire \z80_|alu_control_|db[2]~28_combout ; +wire \z80_|alu_flags_|flags_hf2~0_combout ; +wire \z80_|alu_flags_|flags_hf2~q ; +wire \z80_|alu_control_|out[6]~0_combout ; +wire \z80_|execute_|ctl_66_oe~combout ; +wire \z80_|alu_control_|db[2]~24_combout ; wire \z80_|execute_|ctl_reg_out_lo~3_combout ; wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; wire \z80_|execute_|ctl_reg_out_lo~4_combout ; wire \z80_|execute_|ctl_reg_out_lo~5_combout ; -wire \z80_|execute_|ctl_reg_out_lo~8_combout ; -wire \z80_|sw1_|db_down[3]~1_combout ; -wire \z80_|alu_control_|db[3]~34_combout ; -wire \z80_|alu_control_|db[3]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~52_combout ; -wire \z80_|reg_file_|db_lo_as[3]~10_combout ; -wire \z80_|reg_file_|db_lo_as[3]~11_combout ; -wire \z80_|reg_file_|db_lo_as[3]~12_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ; +wire \z80_|reg_file_|db_lo_ds[2]~1_combout ; +wire \z80_|alu_control_|db[2]~29_combout ; +wire \z80_|alu_control_|db[2]~30_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; +wire \z80_|reg_file_|db_lo_as[2]~7_combout ; +wire \z80_|reg_file_|db_lo_as[2]~8_combout ; +wire \z80_|reg_file_|db_lo_as[2]~9_combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~62_combout ; -wire \z80_|reg_file_|db_lo_as[4]~13_combout ; -wire \z80_|reg_file_|db_lo_as[4]~14_combout ; -wire \z80_|reg_file_|db_lo_as[4]~15_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; -wire \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~62_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~72_combout ; wire \z80_|reg_file_|db_lo_as[5]~16_combout ; wire \z80_|reg_file_|db_lo_as[5]~17_combout ; wire \z80_|reg_file_|db_lo_as[5]~18_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ; wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~72_combout ; +wire \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ; wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; wire \z80_|reg_file_|db_lo_as[6]~19_combout ; wire \z80_|reg_file_|db_lo_as[6]~20_combout ; wire \z80_|reg_file_|db_lo_as[6]~21_combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[7]~24_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~92_combout ; -wire \z80_|reg_file_|db_lo_ds[7]~0_combout ; -wire \z80_|interrupts_|im2~q ; -wire \z80_|execute_|ctl_mRead~12_combout ; -wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; -wire \z80_|alu_control_|db[7]~17_combout ; -wire \z80_|alu_control_|db[7]~16_combout ; -wire \z80_|alu_control_|db[7]~18_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|execute_|ctl_flags_sz_we~8_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; -wire \z80_|pla_decode_|Equal62~3_combout ; -wire \z80_|execute_|ctl_flags_pf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~6_combout ; -wire \z80_|execute_|ctl_flags_pf_we~7_combout ; -wire \z80_|execute_|ctl_flags_pf_we~8_combout ; -wire \z80_|execute_|ctl_flags_pf_we~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[0]~4_combout ; +wire \z80_|reg_file_|db_hi_as[0]~5_combout ; +wire \z80_|reg_file_|db_hi_as[0]~6_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; +wire \z80_|alu_|db[0]~17_combout ; +wire \z80_|alu_|db[0]~18_combout ; +wire \z80_|sw2_|db_up[0]~0_combout ; +wire \z80_|alu_control_|db[0]~11_combout ; +wire \z80_|alu_control_|db[0]~14_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; +wire \z80_|reg_file_|db_lo_as[0]~0_combout ; +wire \z80_|reg_file_|db_lo_as[0]~1_combout ; +wire \z80_|reg_file_|db_lo_as[0]~3_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; +wire \z80_|reg_file_|db_lo_as[1]~4_combout ; +wire \z80_|reg_file_|db_lo_as[1]~5_combout ; +wire \z80_|reg_file_|db_lo_as[1]~6_combout ; +wire \z80_|address_latch_|Q[1]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; +wire \z80_|reg_file_|db_lo_as[3]~12_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; +wire \z80_|alu_control_|db[3]~35_combout ; +wire \z80_|alu_control_|db[3]~36_combout ; +wire \z80_|alu_|db[3]~14_combout ; +wire \z80_|alu_|db_low[3]~4_combout ; +wire \z80_|alu_|db_low[3]~5_combout ; +wire \z80_|alu_|db_low[3]~6_combout ; +wire \z80_|alu_|db_low[3]~7_combout ; +wire \z80_|alu_|db_low[3]~8_combout ; +wire \z80_|alu_|db_low[3]~26_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ; +wire \z80_|alu_|alu_op2[3]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ; +wire \z80_|alu_|db_high[3]~4_combout ; +wire \z80_|alu_|db_high[3]~2_combout ; +wire \z80_|alu_|db_high[3]~3_combout ; +wire \z80_|alu_|db_high[3]~5_combout ; +wire \z80_|alu_|db_high[3]~6_combout ; +wire \z80_|alu_|db_high[3]~7_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; +wire \z80_|execute_|ctl_flags_nf_we~0_combout ; +wire \z80_|execute_|ctl_flags_nf_we~1_combout ; +wire \z80_|execute_|ctl_flags_nf_we~2_combout ; +wire \z80_|execute_|ctl_flags_nf_we~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; +wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; +wire \z80_|execute_|ctl_flags_cf_set~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; +wire \z80_|alu_control_|out[6]~1_combout ; +wire \z80_|alu_control_|out[6]~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; +wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; +wire \z80_|execute_|ctl_alu_op_low~21_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; +wire \z80_|pla_decode_|Equal64~0_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; +wire \z80_|alu_flags_|flags_cf~combout ; +wire \z80_|execute_|ctl_flags_hf_we~3_combout ; +wire \z80_|execute_|ctl_flags_hf_we~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; +wire \z80_|execute_|ctl_flags_hf_cpl~9_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; +wire \z80_|alu_flags_|flags_hf~combout ; +wire \z80_|alu_control_|db[4]~31_combout ; +wire \z80_|alu_control_|db[4]~32_combout ; +wire \z80_|alu_control_|db[4]~33_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~52_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; +wire \z80_|reg_file_|db_lo_as[4]~13_combout ; +wire \z80_|reg_file_|db_lo_as[4]~14_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[4]~15_combout ; wire \z80_|decode_state_|DFFE_instNonRep~2_combout ; wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; wire \z80_|decode_state_|DFFE_instNonRep~4_combout ; wire \z80_|decode_state_|DFFE_instNonRep~5_combout ; wire \z80_|decode_state_|DFFE_instNonRep~q ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; +wire \z80_|pla_decode_|Equal79~0_combout ; +wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|interrupts_|DFFE_instIFF2~q ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; +wire \z80_|execute_|ctl_pf_sel[1]~12_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~11_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; wire \z80_|alu_|alu_parity_out~0_combout ; wire \z80_|alu_|alu_parity_out~combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~q ; -wire \z80_|alu_control_|sel[1]~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; wire \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ; wire \z80_|alu_control_|flags_cond_true~0_combout ; wire \z80_|alu_control_|flags_cond_true~q ; -wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; -wire \z80_|reg_file_|db_lo_ds[1]~1_combout ; -wire \z80_|alu_control_|db[1]~25_combout ; -wire \z80_|alu_control_|db[1]~24_combout ; -wire \z80_|alu_control_|db[1]~26_combout ; -wire \z80_|alu_|db[1]~12_combout ; -wire \z80_|alu_|db[1]~13_combout ; -wire \z80_|alu_|db_low[0]~21_combout ; -wire \z80_|alu_|db_low[0]~22_combout ; -wire \z80_|alu_|db_low[0]~18_combout ; -wire \z80_|alu_|db_low[0]~19_combout ; -wire \z80_|alu_|db_low[0]~20_combout ; -wire \z80_|alu_|db_low[0]~23_combout ; -wire \z80_|alu_|db[0]~18_combout ; -wire \z80_|alu_|db[0]~19_combout ; -wire \z80_|alu_|db_low[1]~15_combout ; -wire \z80_|alu_|db_low[1]~16_combout ; -wire \z80_|alu_|db_low[1]~12_combout ; -wire \z80_|alu_|db_low[1]~13_combout ; -wire \z80_|alu_|db_low[1]~14_combout ; -wire \z80_|alu_|db_low[1]~17_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ; -wire \z80_|alu_control_|out[6]~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; -wire \z80_|alu_flags_|flags_hf2~0_combout ; -wire \z80_|alu_flags_|flags_hf2~q ; -wire \z80_|alu_control_|db[2]~23_combout ; -wire \z80_|reg_file_|db_lo_ds[2]~2_combout ; -wire \z80_|alu_control_|db[2]~28_combout ; -wire \z80_|alu_control_|db[2]~27_combout ; -wire \z80_|alu_control_|db[2]~29_combout ; -wire \z80_|alu_|db[2]~14_combout ; -wire \z80_|alu_|db[2]~15_combout ; -wire \z80_|alu_|db_low[2]~2_combout ; -wire \z80_|alu_|db_low[2]~3_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ; -wire \z80_|alu_|db_low[2]~5_combout ; -wire \z80_|alu_|db_low[2]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ; -wire \z80_|alu_|alu_op2[2]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; -wire \z80_|alu_|db_high[2]~9_combout ; -wire \z80_|alu_|db_high[2]~11_combout ; -wire \z80_|alu_|db_high[2]~12_combout ; -wire \z80_|alu_|db_high[2]~10_combout ; -wire \z80_|alu_|db_high[2]~13_combout ; -wire \z80_|alu_|db_high[2]~14_combout ; -wire \z80_|alu_|db[6]~22_combout ; -wire \z80_|alu_|db[6]~23_combout ; -wire \z80_|alu_control_|out[6]~1_combout ; -wire \z80_|alu_control_|out[6]~2_combout ; -wire \z80_|alu_control_|db[6]~19_combout ; -wire \z80_|alu_control_|db[6]~20_combout ; -wire \z80_|alu_control_|db[6]~21_combout ; -wire \z80_|alu_control_|db[6]~22_combout ; -wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; -wire \z80_|interrupts_|im1~q ; -wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; -wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; -wire \z80_|bus_control_|db[0]~4_combout ; -wire \z80_|bus_control_|db[6]~8_combout ; -wire \z80_|execute_|ctl_mRead~37_combout ; -wire \z80_|execute_|ctl_mRead~28_combout ; -wire \z80_|execute_|ctl_mRead~29_combout ; -wire \z80_|execute_|ctl_mRead~30_combout ; -wire \z80_|execute_|setM1~37_combout ; -wire \z80_|execute_|setM1~55_combout ; -wire \z80_|execute_|setM1~38_combout ; -wire \z80_|execute_|ctl_mRead~34_combout ; -wire \z80_|execute_|nextM~3_combout ; -wire \z80_|execute_|ctl_mRead~31_combout ; -wire \z80_|execute_|ctl_mRead~32_combout ; -wire \z80_|execute_|ctl_mRead~33_combout ; -wire \z80_|execute_|ctl_mRead~35_combout ; -wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; -wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; -wire \z80_|memory_ifc_|wait_mrd~q ; -wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; -wire \z80_|memory_ifc_|nRD_out~1_combout ; -wire \z80_|execute_|nextM~4_combout ; -wire \z80_|execute_|ctl_iorw~12_combout ; -wire \z80_|execute_|ctl_iorw~8_combout ; -wire \z80_|execute_|ctl_iorw~9_combout ; -wire \z80_|memory_ifc_|DFFE_iorq_ff1~q ; -wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ; -wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ; -wire \z80_|memory_ifc_|wait_iorq~q ; -wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; -wire \z80_|memory_ifc_|iorq~0_combout ; -wire \z80_|execute_|fIORead~1_combout ; -wire \z80_|execute_|fIORead~2_combout ; -wire \z80_|execute_|fIORead~0_combout ; -wire \z80_|execute_|fIORead~3_combout ; -wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; -wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; -wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; -wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; -wire \z80_|memory_ifc_|nRD_out~0_combout ; -wire \z80_|memory_ifc_|nRD_out~2_combout ; -wire \Equal2~1_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~0_combout ; -wire \z80_|execute_|fMWrite~5_combout ; -wire \z80_|execute_|fMWrite~6_combout ; -wire \z80_|execute_|fMWrite~2_combout ; -wire \z80_|execute_|fMWrite~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~1_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; -wire \z80_|execute_|fMWrite~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; -wire \z80_|execute_|fMWrite~9_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; -wire \z80_|execute_|fMWrite~8_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; -wire \z80_|execute_|fMWrite~10_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; -wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; -wire \z80_|clk_delay_|DFF_inst5~q ; -wire \z80_|memory_ifc_|wait_iorqinta~feeder_combout ; -wire \z80_|memory_ifc_|wait_iorqinta~q ; -wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; -wire \z80_|memory_ifc_|nIORQ_out~0_combout ; -wire \Equal2~0_combout ; -wire \ExtRamWE~0_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; +wire \z80_|reg_file_|db_hi_as[0]~2_combout ; +wire \z80_|reg_file_|db_hi_as[3]~7_combout ; +wire \z80_|reg_file_|db_hi_as[3]~8_combout ; +wire \z80_|reg_file_|db_hi_as[3]~9_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; wire \z80_|execute_|ctl_apin_mux2~0_combout ; wire \z80_|pin_control_|bus_ab_pin_we~2_combout ; wire \z80_|pin_control_|bus_ab_pin_we~3_combout ; -wire \z80_|address_pins_|abus[13]~20_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; -wire \z80_|address_pins_|abus[14]~23_combout ; +wire \z80_|address_pins_|abus[11]~19_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; +wire \z80_|address_pins_|abus[10]~20_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~19_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~48_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~51_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~q ; +wire \D[2]~43_combout ; +wire \ula_|zx_keyboard_|WideOr17~0_combout ; +wire \ula_|zx_keyboard_|shifted~2_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~11_combout ; +wire \ula_|zx_keyboard_|shifted~0_combout ; +wire \ula_|zx_keyboard_|shifted~3_combout ; +wire \ula_|zx_keyboard_|shifted~q ; +wire \ula_|zx_keyboard_|keys[5][0]~62_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~32_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~63_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~64_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~65_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~q ; wire \z80_|address_pins_|DFFE_apin_latch[15]~15_combout ; -wire \z80_|address_pins_|abus[15]~22_combout ; -wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; +wire \z80_|address_pins_|abus[15]~21_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; +wire \z80_|address_pins_|abus[14]~22_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~57_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~58_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~59_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~28_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~60_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~56_combout ; +wire \ula_|zx_keyboard_|Selector13~0_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~q ; +wire \D[2]~44_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; +wire \z80_|address_pins_|abus[12]~24_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~29_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~54_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~55_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~q ; +wire \ula_|zx_keyboard_|key_row~1_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~127_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~66_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~128_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~67_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~q ; +wire \D[2]~45_combout ; wire \z80_|address_pins_|abus[0]~16_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~43_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~44_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~45_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~46_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~q ; +wire \ula_|zx_keyboard_|keys[0][2]~47_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~49_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~q ; +wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; +wire \z80_|address_pins_|abus[9]~17_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; +wire \z80_|address_pins_|abus[8]~18_combout ; +wire \D[2]~42_combout ; +wire \D[2]~46_combout ; +wire \z80_|memory_ifc_|wait_iorqinta~q ; +wire \z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ; +wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; +wire \z80_|control_pins_|pin_nIORQ~1_combout ; +wire \Equal2~0_combout ; +wire \z80_|address_pins_|abus[13]~23_combout ; +wire \ExtRamWE~0_combout ; +wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; wire \z80_|address_pins_|DFFE_apin_latch[1]~1_combout ; wire \z80_|address_pins_|abus[1]~25_combout ; wire \z80_|address_pins_|DFFE_apin_latch[2]~2_combout ; @@ -1807,30 +1993,20 @@ wire \z80_|address_pins_|DFFE_apin_latch[6]~6_combout ; wire \z80_|address_pins_|abus[6]~30_combout ; wire \z80_|address_pins_|DFFE_apin_latch[7]~7_combout ; wire \z80_|address_pins_|abus[7]~31_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; -wire \z80_|address_pins_|abus[8]~18_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; -wire \z80_|address_pins_|abus[9]~17_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; -wire \z80_|address_pins_|abus[10]~24_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; -wire \z80_|address_pins_|abus[11]~19_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; -wire \z80_|address_pins_|abus[12]~21_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; -wire \D[6]~90_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; -wire \D[6]~91_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; +wire \D[2]~50_combout ; +wire \D[2]~51_combout ; wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ; wire \CLOCK_50~inputclkctrl_outclk ; wire \~GND~combout ; -wire \ula_|video_|vram_address[0]~feeder_combout ; wire \ula_|video_|vram_address~0_combout ; +wire \ula_|video_|vram_address[1]~feeder_combout ; wire \ula_|video_|vram_address[2]~4_combout ; wire \ula_|video_|Add3~0_combout ; wire \ula_|video_|Add3~1_combout ; @@ -1842,638 +2018,521 @@ wire \ula_|video_|Add4~7 ; wire \ula_|video_|Add4~8_combout ; wire \ula_|video_|Add4~9 ; wire \ula_|video_|Add4~10_combout ; +wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Add4~11 ; wire \ula_|video_|Add4~12_combout ; -wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Selector6~0_combout ; -wire \ula_|video_|vram_address[9]~1_combout ; +wire \ula_|video_|vram_address[8]~1_combout ; wire \ula_|video_|Add4~13 ; wire \ula_|video_|Add4~14_combout ; wire \ula_|video_|Add4~2_combout ; wire \ula_|video_|Selector5~0_combout ; -wire \ula_|video_|Add4~4_combout ; wire \ula_|video_|vram_address[10]~2_combout ; +wire \ula_|video_|Add4~4_combout ; wire \ula_|video_|vram_address[10]~3_combout ; wire \ula_|video_|Selector3~0_combout ; wire \ula_|video_|Selector2~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \D[6]~87_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \D[6]~88_combout ; -wire \D[6]~89_combout ; -wire \D[6]~111_combout ; -wire \raw_loader_in~input_o ; -wire \D[6]~86_combout ; -wire \D[6]~100_combout ; -wire \D[6]~101_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \D[2]~47_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \D[2]~48_combout ; +wire \D[2]~49_combout ; +wire \D[2]~119_combout ; +wire \D[2]~52_combout ; +wire \D[2]~53_combout ; wire \z80_|pin_control_|bus_db_pin_re~2_combout ; wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; -wire \z80_|bus_control_|db[6]~9_combout ; -wire \z80_|ir_|opcode[6]~feeder_combout ; +wire \z80_|bus_control_|db[2]~12_combout ; +wire \z80_|bus_control_|db[0]~6_combout ; +wire \z80_|bus_control_|db[2]~13_combout ; +wire \z80_|ir_|opcode[2]~feeder_combout ; wire \z80_|execute_|ctl_ir_we~13_combout ; -wire \z80_|pla_decode_|Equal41~0_combout ; -wire \z80_|pla_decode_|Equal41~1_combout ; -wire \z80_|pla_decode_|Equal41~2_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~combout ; -wire \z80_|alu_|db_high[1]~15_combout ; -wire \z80_|alu_|db_high[1]~16_combout ; -wire \z80_|alu_|db_high[1]~17_combout ; -wire \z80_|alu_|db_high[1]~18_combout ; -wire \z80_|alu_|db_high[1]~19_combout ; -wire \z80_|alu_|db_high[1]~20_combout ; -wire \z80_|alu_|db[5]~24_combout ; -wire \z80_|alu_|db[5]~25_combout ; -wire \z80_|sw1_|db_down[5]~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; -wire \z80_|alu_flags_|flags_yf~q ; -wire \z80_|alu_control_|db[5]~13_combout ; -wire \z80_|alu_control_|db[5]~14_combout ; -wire \z80_|alu_control_|db[5]~15_combout ; -wire \D[0]~107_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \Mux2~0_combout ; -wire \Mux2~1_combout ; -wire \D[5]~110_combout ; -wire \D[5]~85_combout ; -wire \D[5]~99_combout ; -wire \z80_|bus_control_|db[5]~14_combout ; -wire \z80_|bus_control_|db[5]~15_combout ; -wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|decode_state_|DFFE_inst4~q ; -wire \z80_|decode_state_|use_ixiy~combout ; -wire \z80_|execute_|ctl_mRead~23_combout ; -wire \z80_|execute_|fMRead~34_combout ; -wire \z80_|execute_|fMRead~31_combout ; +wire \z80_|execute_|ctl_mRead~34_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ; +wire \z80_|execute_|ctl_reg_out_lo~6_combout ; +wire \z80_|execute_|ctl_reg_out_lo~7_combout ; +wire \z80_|execute_|ctl_reg_out_lo~8_combout ; +wire \z80_|alu_control_|db[6]~13_combout ; +wire \z80_|alu_control_|db[6]~21_combout ; +wire \z80_|alu_control_|db[6]~22_combout ; +wire \z80_|reg_file_|db_lo_ds[6]~0_combout ; +wire \z80_|sw1_|db_down[6]~1_combout ; +wire \z80_|alu_control_|db[6]~23_combout ; +wire \z80_|bus_control_|db[6]~8_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; +wire \D[6]~103_combout ; +wire \D[6]~104_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \D[6]~100_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \D[6]~101_combout ; +wire \D[6]~102_combout ; +wire \D[6]~127_combout ; +wire \raw_loader_in~input_o ; +wire \D[6]~99_combout ; +wire \D[6]~114_combout ; +wire \D[6]~115_combout ; +wire \z80_|bus_control_|db[6]~9_combout ; +wire \z80_|pla_decode_|Equal13~0_combout ; +wire \z80_|pla_decode_|Equal38~2_combout ; +wire \z80_|interrupts_|iff1~0_combout ; +wire \z80_|interrupts_|iff1~1_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|interrupts_|iff1~q ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ; +wire \z80_|interrupts_|int_armed~q ; +wire \z80_|interrupts_|DFFE_inst44~q ; +wire \z80_|decode_state_|in_halt~0_combout ; +wire \z80_|pla_decode_|Equal77~1_combout ; +wire \z80_|decode_state_|in_halt~1_combout ; +wire \z80_|decode_state_|in_halt~q ; +wire \z80_|execute_|ctl_mRead~21_combout ; +wire \z80_|execute_|fMRead~35_combout ; +wire \z80_|execute_|fMRead~23_combout ; +wire \z80_|execute_|fMRead~27_combout ; +wire \z80_|execute_|fMRead~28_combout ; wire \z80_|execute_|fMRead~29_combout ; wire \z80_|execute_|fMRead~30_combout ; -wire \z80_|execute_|fMRead~28_combout ; +wire \z80_|execute_|fMRead~31_combout ; wire \z80_|execute_|fMRead~32_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; -wire \z80_|execute_|fMRead~14_combout ; -wire \z80_|execute_|fMRead~10_combout ; -wire \z80_|execute_|fMRead~9_combout ; +wire \z80_|execute_|fMRead~37_combout ; +wire \z80_|execute_|fMRead~33_combout ; +wire \z80_|execute_|fMRead~24_combout ; +wire \z80_|execute_|fMRead~25_combout ; +wire \z80_|execute_|fMRead~16_combout ; wire \z80_|execute_|fMRead~11_combout ; wire \z80_|execute_|fMRead~12_combout ; wire \z80_|execute_|fMRead~13_combout ; +wire \z80_|execute_|fMRead~14_combout ; wire \z80_|execute_|fMRead~15_combout ; -wire \z80_|execute_|fMRead~20_combout ; -wire \z80_|execute_|pc_inc_hold~48_combout ; +wire \z80_|execute_|fMRead~17_combout ; wire \z80_|execute_|fMRead~22_combout ; -wire \z80_|execute_|fMRead~21_combout ; -wire \z80_|execute_|fMRead~23_combout ; -wire \z80_|execute_|fMRead~26_combout ; -wire \z80_|execute_|fMRead~25_combout ; -wire \z80_|execute_|fMRead~27_combout ; -wire \z80_|execute_|fMRead~33_combout ; -wire \z80_|execute_|fMRead~35_combout ; +wire \z80_|execute_|fMRead~34_combout ; +wire \z80_|execute_|fMRead~36_combout ; wire \z80_|pin_control_|bus_db_pin_re~combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \Selector1~0_combout ; -wire \Selector1~1_combout ; -wire \D[1]~103_combout ; -wire \PS2_DAT~input_o ; -wire \reset~clkctrl_outclk ; -wire \ula_|ps2_keyboard_|bit_count~0_combout ; -wire \PS2_CLK~input_o ; -wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~0_combout ; -wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~1_combout ; -wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~q ; -wire \ula_|ps2_keyboard_|clk_edge~0_combout ; -wire \ula_|ps2_keyboard_|clk_edge~q ; -wire \ula_|ps2_keyboard_|bit_count~1_combout ; -wire \ula_|ps2_keyboard_|bit_count~3_combout ; -wire \ula_|ps2_keyboard_|bit_count~2_combout ; -wire \ula_|ps2_keyboard_|always1~0_combout ; -wire \ula_|ps2_keyboard_|LessThan0~0_combout ; -wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; -wire \ula_|zx_keyboard_|Equal0~0_combout ; -wire \ula_|zx_keyboard_|Equal0~1_combout ; -wire \ula_|zx_keyboard_|extended~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~1_combout ; -wire \ula_|ps2_keyboard_|WideXor0~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~2_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~q ; -wire \ula_|zx_keyboard_|extended~q ; -wire \ula_|zx_keyboard_|keys[0][0]~15_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; -wire \ula_|zx_keyboard_|shifted~0_combout ; -wire \ula_|zx_keyboard_|released~0_combout ; -wire \ula_|zx_keyboard_|released~q ; -wire \ula_|zx_keyboard_|WideOr17~0_combout ; -wire \ula_|zx_keyboard_|shifted~2_combout ; -wire \ula_|zx_keyboard_|shifted~3_combout ; -wire \ula_|zx_keyboard_|shifted~q ; -wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~103_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~20_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~21_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~q ; +wire \ula_|zx_keyboard_|keys[3][0]~73_combout ; +wire \ula_|zx_keyboard_|Selector5~0_combout ; +wire \ula_|zx_keyboard_|Selector5~1_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~129_combout ; +wire \ula_|zx_keyboard_|WideOr16~1_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~105_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~130_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~q ; +wire \D[3]~74_combout ; wire \ula_|zx_keyboard_|keys[5][1]~39_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~q ; -wire \ula_|zx_keyboard_|keys[4][1]~31_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~23_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~32_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~33_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~34_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~q ; -wire \D[1]~30_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~24_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~29_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~30_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~25_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~26_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~27_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~q ; -wire \ula_|zx_keyboard_|key_row~0_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~17_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~18_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~q ; -wire \ula_|zx_keyboard_|keys[7][4]~19_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~20_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~21_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~22_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~q ; -wire \D[1]~28_combout ; -wire \D[1]~29_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~43_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~44_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~q ; -wire \ula_|zx_keyboard_|keys[7][1]~45_combout ; -wire \ula_|zx_keyboard_|WideOr16~5_combout ; -wire \ula_|zx_keyboard_|WideOr16~2_combout ; -wire \ula_|zx_keyboard_|WideOr16~4_combout ; -wire \ula_|zx_keyboard_|WideOr16~7_combout ; -wire \ula_|zx_keyboard_|WideOr16~6_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~46_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~q ; -wire \D[1]~31_combout ; -wire \D[1]~32_combout ; -wire \D[1]~33_combout ; -wire \D[1]~34_combout ; -wire \z80_|bus_control_|db[1]~10_combout ; -wire \z80_|bus_control_|db[1]~11_combout ; -wire \z80_|ir_|opcode[1]~feeder_combout ; -wire \z80_|pla_decode_|Equal40~0_combout ; -wire \z80_|pla_decode_|Equal21~1_combout ; -wire \z80_|execute_|ctl_alu_op_low~26_combout ; -wire \z80_|execute_|ctl_alu_op_low~28_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; -wire \z80_|execute_|ctl_alu_op_low~32_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; -wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~10_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; -wire \z80_|execute_|ctl_flags_cf_set~0_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~9_combout ; -wire \z80_|alu_flags_|flags_cf~combout ; -wire \z80_|alu_control_|db[0]~8_combout ; -wire \z80_|sw2_|db_up[0]~0_combout ; -wire \z80_|alu_control_|db[0]~9_combout ; -wire \z80_|alu_control_|db[0]~12_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~67_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~81_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~82_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~83_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~q ; -wire \ula_|zx_keyboard_|keys[4][0]~84_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~85_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~86_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~q ; -wire \D[0]~49_combout ; -wire \ula_|zx_keyboard_|WideOr4~0_combout ; -wire \ula_|zx_keyboard_|keys~76_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~73_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~47_combout ; -wire \ula_|zx_keyboard_|WideOr0~0_combout ; -wire \ula_|zx_keyboard_|keys~74_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~75_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~77_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~q ; -wire \ula_|zx_keyboard_|keys[1][0]~71_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~72_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~q ; -wire \D[0]~47_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~80_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~q ; -wire \ula_|zx_keyboard_|keys[3][0]~78_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~79_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~q ; -wire \ula_|zx_keyboard_|key_row~1_combout ; -wire \D[0]~48_combout ; -wire \ula_|zx_keyboard_|shifted~1_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~91_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~92_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~q ; -wire \ula_|zx_keyboard_|keys[5][4]~63_combout ; -wire \ula_|zx_keyboard_|WideOr16~3_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~132_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~88_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~89_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~q ; -wire \D[0]~50_combout ; -wire \D[0]~51_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~55_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \D[0]~56_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \D[0]~52_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~53_combout ; -wire \D[0]~54_combout ; -wire \D[0]~106_combout ; -wire \D[0]~57_combout ; -wire \D[0]~58_combout ; -wire \z80_|bus_control_|db[0]~16_combout ; -wire \z80_|bus_control_|db[0]~17_combout ; -wire \z80_|pla_decode_|Equal63~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; -wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; -wire \z80_|alu_control_|db[6]~10_combout ; -wire \z80_|alu_control_|db[6]~11_combout ; -wire \z80_|alu_control_|db[4]~30_combout ; -wire \z80_|alu_control_|db[4]~31_combout ; -wire \z80_|alu_control_|db[4]~32_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~119_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~120_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~95_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~121_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~q ; -wire \ula_|zx_keyboard_|keys[3][4]~117_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~136_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~130_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~118_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~q ; -wire \D[4]~78_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~126_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~128_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~129_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~q ; -wire \ula_|zx_keyboard_|keys[6][4]~127_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~q ; -wire \ula_|zx_keyboard_|Equal0~2_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~51_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~125_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~q ; -wire \D[4]~79_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~122_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~123_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~q ; -wire \ula_|zx_keyboard_|key_row~3_combout ; -wire \D[4]~80_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~111_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~97_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~116_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~115_combout ; -wire \ula_|zx_keyboard_|keys[1][4]~q ; -wire \D[4]~77_combout ; -wire \D[4]~81_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \Selector4~0_combout ; -wire \Selector4~1_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ; -wire \D[4]~109_combout ; -wire \D[4]~97_combout ; -wire \D[4]~98_combout ; -wire \z80_|bus_control_|db[4]~18_combout ; -wire \z80_|bus_control_|db[4]~19_combout ; -wire \z80_|pla_decode_|Equal21~0_combout ; -wire \z80_|execute_|ctl_mRead~5_combout ; -wire \z80_|execute_|fIOWrite~2_combout ; -wire \z80_|execute_|fIOWrite~3_combout ; -wire \z80_|execute_|fIOWrite~4_combout ; -wire \z80_|execute_|fIOWrite~5_combout ; -wire \z80_|execute_|ctl_mWrite~11_combout ; -wire \z80_|execute_|ctl_mWrite~12_combout ; -wire \z80_|execute_|ctl_mWrite~13_combout ; -wire \z80_|execute_|ctl_mWrite~14_combout ; -wire \z80_|execute_|ctl_mWrite~15_combout ; -wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; -wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; -wire \z80_|memory_ifc_|wait_mwr~q ; -wire \z80_|memory_ifc_|mwr_wr~q ; -wire \z80_|memory_ifc_|nWR_out~0_combout ; -wire \D[5]~84_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~100_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~99_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~q ; +wire \ula_|zx_keyboard_|keys[3][3]~97_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~98_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~q ; +wire \D[3]~73_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~108_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~109_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~110_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~q ; +wire \ula_|zx_keyboard_|keys[6][3]~111_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~112_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~132_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~133_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~q ; +wire \D[3]~75_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~94_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~93_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~95_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~96_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~q ; +wire \ula_|zx_keyboard_|keys[1][3]~91_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~92_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~q ; +wire \D[3]~72_combout ; +wire \D[3]~76_combout ; +wire \D[3]~122_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \D[3]~79_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \D[3]~77_combout ; +wire \D[3]~80_combout ; +wire \D[3]~81_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \D[3]~124_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \D[3]~123_combout ; +wire \D[3]~78_combout ; +wire \D[3]~82_combout ; +wire \D[3]~108_combout ; +wire \D[3]~109_combout ; +wire \z80_|bus_control_|db[3]~20_combout ; +wire \z80_|bus_control_|db[3]~21_combout ; +wire \z80_|pla_decode_|Equal33~1_combout ; +wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; +wire \z80_|bus_control_|db[0]~4_combout ; +wire \z80_|bus_control_|db[7]~5_combout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ; +wire \D[5]~97_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; wire \Mux0~0_combout ; wire \Mux0~1_combout ; -wire \D[7]~112_combout ; -wire \D[7]~94_combout ; -wire \D[7]~102_combout ; -wire \z80_|bus_control_|db[7]~5_combout ; +wire \D[7]~116_combout ; +wire \D[7]~117_combout ; wire \z80_|bus_control_|db[7]~7_combout ; -wire \z80_|pla_decode_|Equal77~0_combout ; -wire \z80_|execute_|ctl_mWrite~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; -wire \z80_|execute_|ctl_bus_db_we~3_combout ; -wire \z80_|execute_|ctl_bus_db_we~8_combout ; -wire \z80_|execute_|ctl_bus_db_we~2_combout ; -wire \z80_|execute_|ctl_bus_db_we~4_combout ; -wire \z80_|execute_|ctl_bus_db_we~6_combout ; -wire \z80_|execute_|ctl_bus_db_we~7_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~50_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~52_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~q ; -wire \ula_|zx_keyboard_|keys[3][3]~48_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~49_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~q ; -wire \D[2]~35_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~57_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~58_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~q ; -wire \ula_|zx_keyboard_|keys[4][2]~59_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~131_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~60_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~q ; -wire \D[2]~37_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~53_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~55_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~56_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~q ; -wire \ula_|zx_keyboard_|keys[3][2]~54_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~q ; -wire \D[2]~36_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~68_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~69_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~70_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~q ; -wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~62_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~64_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~65_combout ; -wire \ula_|zx_keyboard_|Selector13~0_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~66_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~q ; -wire \D[2]~38_combout ; -wire \D[2]~39_combout ; -wire \D[2]~104_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \D[2]~43_combout ; -wire \D[2]~44_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \D[2]~40_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \D[2]~41_combout ; -wire \D[2]~42_combout ; -wire \D[2]~105_combout ; -wire \D[2]~45_combout ; -wire \D[2]~46_combout ; -wire \z80_|bus_control_|db[2]~12_combout ; -wire \z80_|bus_control_|db[2]~13_combout ; -wire \z80_|pla_decode_|Equal3~1_combout ; -wire \z80_|pla_decode_|Equal43~0_combout ; -wire \z80_|interrupts_|test1~2_combout ; -wire \z80_|interrupts_|test1~3_combout ; -wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ; -wire \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ; -wire \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ; -wire \z80_|clk_delay_|hold_clk_iorq~combout ; -wire \z80_|sequencer_|DFFE_T1_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; -wire \z80_|sequencer_|DFFE_T2_ff~q ; -wire \z80_|resets_|x3~combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \z80_|sequencer_|DFFE_M1_ff~q ; -wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M2_ff~q ; -wire \z80_|execute_|ctl_mWrite~3_combout ; -wire \z80_|execute_|nextM~11_combout ; -wire \z80_|execute_|nextM~8_combout ; -wire \z80_|execute_|nextM~9_combout ; -wire \z80_|execute_|nextM~10_combout ; -wire \z80_|execute_|nextM~12_combout ; -wire \z80_|execute_|nextM~15_combout ; -wire \z80_|execute_|nextM~6_combout ; -wire \z80_|execute_|nextM~7_combout ; -wire \z80_|execute_|nextM~13_combout ; -wire \z80_|execute_|setM1~39_combout ; -wire \z80_|execute_|nextM~5_combout ; -wire \z80_|execute_|nextM~14_combout ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|sequencer_|DFFE_T4_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|sequencer_|DFFE_T5_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; -wire \z80_|sequencer_|T6~q ; -wire \z80_|execute_|setM1~13_combout ; -wire \z80_|pla_decode_|Equal77~1_combout ; -wire \z80_|execute_|setM1~12_combout ; -wire \z80_|execute_|setM1~14_combout ; -wire \z80_|execute_|setM1~41_combout ; -wire \z80_|execute_|setM1~42_combout ; -wire \z80_|execute_|setM1~43_combout ; -wire \z80_|execute_|setM1~44_combout ; -wire \z80_|execute_|setM1~50_combout ; -wire \z80_|execute_|setM1~51_combout ; -wire \z80_|execute_|setM1~6_combout ; -wire \z80_|execute_|setM1~7_combout ; -wire \z80_|execute_|setM1~8_combout ; -wire \z80_|execute_|setM1~9_combout ; -wire \z80_|execute_|setM1~10_combout ; -wire \z80_|execute_|setM1~11_combout ; -wire \z80_|execute_|setM1~17_combout ; -wire \z80_|execute_|setM1~31_combout ; -wire \z80_|execute_|setM1~28_combout ; -wire \z80_|execute_|setM1~30_combout ; -wire \z80_|execute_|setM1~32_combout ; -wire \z80_|execute_|setM1~33_combout ; -wire \z80_|execute_|setM1~25_combout ; -wire \z80_|execute_|setM1~26_combout ; -wire \z80_|execute_|setM1~24_combout ; -wire \z80_|execute_|setM1~27_combout ; -wire \z80_|execute_|setM1~22_combout ; -wire \z80_|execute_|setM1~21_combout ; -wire \z80_|execute_|setM1~53_combout ; -wire \z80_|execute_|setM1~23_combout ; -wire \z80_|execute_|setM1~18_combout ; -wire \z80_|execute_|setM1~19_combout ; -wire \z80_|execute_|setM1~20_combout ; -wire \z80_|execute_|setM1~34_combout ; -wire \z80_|execute_|setM1~52_combout ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; -wire \z80_|sequencer_|DFFE_T3_ff~q ; -wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; -wire \z80_|decode_state_|in_halt~0_combout ; -wire \z80_|decode_state_|in_halt~1_combout ; -wire \z80_|decode_state_|in_halt~q ; +wire \z80_|pla_decode_|Equal41~0_combout ; +wire \z80_|pla_decode_|Equal41~1_combout ; +wire \z80_|pla_decode_|Equal41~2_combout ; +wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; +wire \z80_|execute_|ctl_state_tbl_we~8_combout ; +wire \z80_|decode_state_|DFFE_instCB~q ; +wire \z80_|pla_decode_|Equal52~0_combout ; +wire \z80_|execute_|ctl_66_oe~2_combout ; +wire \z80_|interrupts_|im1~q ; +wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; +wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; wire \z80_|execute_|ctl_bus_db_oe~2_combout ; wire \z80_|execute_|ctl_bus_db_oe~5_combout ; wire \z80_|execute_|ctl_bus_db_oe~6_combout ; wire \z80_|execute_|ctl_bus_db_oe~4_combout ; wire \z80_|execute_|ctl_bus_db_oe~combout ; -wire \z80_|bus_control_|db[0]~6_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~93_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~94_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~q ; -wire \ula_|zx_keyboard_|keys[0][3]~96_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~98_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~q ; -wire \D[3]~65_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~99_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~100_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~q ; -wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~133_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~103_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~q ; -wire \D[3]~66_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~105_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~q ; -wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; -wire \ula_|zx_keyboard_|Selector5~1_combout ; -wire \ula_|zx_keyboard_|Selector5~0_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~134_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~135_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~108_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~q ; -wire \D[3]~67_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~112_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~113_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~114_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~q ; -wire \ula_|zx_keyboard_|keys[6][3]~109_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~110_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~137_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~138_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~q ; +wire \ula_|zx_keyboard_|keys[6][0]~88_combout ; +wire \ula_|zx_keyboard_|shifted~1_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~89_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~q ; +wire \ula_|zx_keyboard_|keys[7][0]~84_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~78_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~85_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~86_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~q ; +wire \D[0]~57_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~81_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~82_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~40_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~83_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~q ; +wire \ula_|zx_keyboard_|keys[5][0]~79_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~80_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~q ; +wire \D[0]~56_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~76_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~77_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~q ; +wire \ula_|zx_keyboard_|keys[4][3]~68_combout ; +wire \ula_|zx_keyboard_|WideOr0~0_combout ; +wire \ula_|zx_keyboard_|keys~69_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~70_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~27_combout ; +wire \ula_|zx_keyboard_|WideOr4~0_combout ; +wire \ula_|zx_keyboard_|keys~71_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~72_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~q ; wire \ula_|zx_keyboard_|key_row~2_combout ; -wire \D[3]~68_combout ; -wire \D[3]~69_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \D[3]~73_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; -wire \D[3]~74_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \D[3]~70_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~71_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~72_combout ; -wire \D[3]~108_combout ; -wire \D[3]~95_combout ; -wire \D[3]~96_combout ; -wire \z80_|bus_control_|db[3]~20_combout ; -wire \z80_|bus_control_|db[3]~21_combout ; -wire \z80_|execute_|ctl_mWrite~4_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~22_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~75_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~q ; +wire \ula_|zx_keyboard_|keys[3][1]~24_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~74_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~q ; +wire \D[0]~54_combout ; +wire \D[0]~55_combout ; +wire \D[0]~58_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; +wire \D[0]~62_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \D[0]~63_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \D[0]~59_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \D[0]~60_combout ; +wire \D[0]~61_combout ; +wire \D[0]~120_combout ; +wire \D[0]~64_combout ; +wire \D[0]~65_combout ; +wire \z80_|bus_control_|db[0]~16_combout ; +wire \z80_|bus_control_|db[0]~17_combout ; +wire \z80_|pla_decode_|Equal3~2_combout ; +wire \z80_|execute_|ctl_state_iy_set~2_combout ; +wire \z80_|decode_state_|DFFE_instIY1~q ; +wire \z80_|decode_state_|use_ixiy~combout ; +wire \z80_|execute_|ixy_d~12_combout ; +wire \z80_|execute_|ixy_d~13_combout ; +wire \z80_|execute_|ixy_d~14_combout ; +wire \z80_|execute_|ixy_d~11_combout ; +wire \z80_|execute_|ixy_d~15_combout ; +wire \z80_|execute_|ctl_flags_xy_we~8_combout ; +wire \z80_|execute_|ctl_flags_xy_we~9_combout ; +wire \z80_|execute_|ctl_alu_oe~11_combout ; +wire \z80_|execute_|ctl_alu_oe~12_combout ; +wire \z80_|execute_|ctl_alu_oe~13_combout ; +wire \z80_|execute_|ctl_alu_oe~14_combout ; +wire \z80_|alu_|db[7]~9_combout ; +wire \z80_|alu_|db[1]~15_combout ; +wire \z80_|alu_|db[1]~16_combout ; +wire \z80_|alu_control_|db[1]~25_combout ; +wire \z80_|alu_control_|db[1]~26_combout ; +wire \z80_|sw1_|db_down[1]~2_combout ; +wire \z80_|alu_control_|db[1]~27_combout ; +wire \z80_|bus_control_|db[1]~10_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~41_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~42_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~q ; +wire \ula_|zx_keyboard_|keys[4][1]~30_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~q ; +wire \ula_|zx_keyboard_|key_row~0_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~36_combout ; +wire \ula_|zx_keyboard_|WideOr16~3_combout ; +wire \ula_|zx_keyboard_|WideOr16~0_combout ; +wire \ula_|zx_keyboard_|WideOr16~2_combout ; +wire \ula_|zx_keyboard_|WideOr16~4_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~37_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~q ; +wire \ula_|zx_keyboard_|keys[6][1]~33_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~34_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~31_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~35_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~q ; +wire \D[1]~32_combout ; +wire \D[1]~33_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~16_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~17_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~18_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~q ; +wire \ula_|zx_keyboard_|keys[0][1]~12_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~13_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~10_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~q ; +wire \D[1]~30_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~25_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~26_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~q ; +wire \ula_|zx_keyboard_|keys[2][1]~23_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~q ; +wire \D[1]~31_combout ; +wire \D[1]~34_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \D[1]~38_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \D[1]~39_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \D[1]~35_combout ; +wire \D[1]~36_combout ; +wire \D[1]~37_combout ; +wire \D[1]~118_combout ; +wire \D[1]~40_combout ; +wire \D[1]~41_combout ; +wire \z80_|bus_control_|db[1]~11_combout ; +wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; +wire \z80_|decode_state_|DFFE_instED~q ; +wire \z80_|pla_decode_|Equal6~0_combout ; +wire \z80_|execute_|ctl_mRead~8_combout ; +wire \z80_|execute_|ctl_bus_db_we~2_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; +wire \z80_|execute_|ctl_bus_db_we~3_combout ; +wire \z80_|execute_|ctl_bus_db_we~8_combout ; +wire \z80_|execute_|ctl_bus_db_we~4_combout ; +wire \z80_|execute_|ctl_bus_db_we~6_combout ; +wire \z80_|execute_|ctl_bus_db_we~7_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~126_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~q ; +wire \ula_|zx_keyboard_|keys[7][4]~125_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~q ; +wire \D[4]~88_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~120_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~121_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~q ; +wire \ula_|zx_keyboard_|keys[4][4]~122_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~123_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~q ; +wire \D[4]~87_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~115_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~116_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~117_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~q ; +wire \ula_|zx_keyboard_|key_row~3_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~118_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~131_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~119_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~q ; +wire \ula_|zx_keyboard_|keys[0][4]~114_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~q ; +wire \ula_|zx_keyboard_|keys[1][4]~113_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~q ; +wire \D[4]~85_combout ; +wire \D[4]~86_combout ; +wire \D[4]~89_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; +wire \D[4]~93_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; +wire \D[4]~94_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \D[4]~90_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \D[4]~91_combout ; +wire \D[4]~92_combout ; +wire \D[4]~125_combout ; +wire \D[4]~110_combout ; +wire \D[4]~111_combout ; +wire \z80_|bus_control_|db[4]~18_combout ; +wire \z80_|bus_control_|db[4]~19_combout ; +wire \z80_|pla_decode_|Equal32~0_combout ; +wire \z80_|pla_decode_|Equal36~0_combout ; +wire \z80_|pla_decode_|Equal43~0_combout ; +wire \z80_|interrupts_|test1~2_combout ; +wire \z80_|interrupts_|test1~3_combout ; +wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ; +wire \z80_|sw1_|db_down[5]~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; +wire \z80_|alu_flags_|flags_yf~q ; +wire \z80_|alu_control_|db[5]~15_combout ; +wire \z80_|alu_control_|db[5]~16_combout ; +wire \z80_|alu_control_|db[5]~17_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \Mux2~0_combout ; +wire \Mux2~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ; +wire \D[5]~112_combout ; +wire \D[5]~113_combout ; +wire \z80_|bus_control_|db[5]~14_combout ; +wire \z80_|bus_control_|db[5]~15_combout ; +wire \z80_|execute_|ctl_mRead~11_combout ; +wire \z80_|execute_|setM1~46_combout ; +wire \z80_|execute_|setM1~40_combout ; +wire \z80_|execute_|nextM~5_combout ; +wire \z80_|execute_|nextM~6_combout ; +wire \z80_|execute_|nextM~7_combout ; +wire \z80_|execute_|nextM~9_combout ; +wire \z80_|execute_|nextM~10_combout ; +wire \z80_|execute_|nextM~8_combout ; +wire \z80_|execute_|nextM~12_combout ; +wire \z80_|execute_|nextM~15_combout ; +wire \z80_|execute_|nextM~13_combout ; +wire \z80_|execute_|nextM~14_combout ; +wire \z80_|sequencer_|ena_M~combout ; +wire \z80_|sequencer_|DFFE_T1_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; +wire \z80_|sequencer_|DFFE_T2_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; +wire \z80_|sequencer_|DFFE_T3_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|sequencer_|DFFE_T4_ff~q ; +wire \z80_|execute_|ctl_mWrite~9_combout ; +wire \z80_|execute_|ctl_flags_sz_we~0_combout ; +wire \z80_|execute_|setM1~54_combout ; +wire \z80_|execute_|setM1~25_combout ; +wire \z80_|execute_|setM1~26_combout ; +wire \z80_|execute_|setM1~27_combout ; +wire \z80_|execute_|setM1~22_combout ; +wire \z80_|execute_|setM1~55_combout ; +wire \z80_|execute_|setM1~23_combout ; +wire \z80_|execute_|setM1~24_combout ; +wire \z80_|execute_|setM1~28_combout ; +wire \z80_|execute_|setM1~11_combout ; +wire \z80_|execute_|setM1~33_combout ; +wire \z80_|execute_|setM1~29_combout ; +wire \z80_|execute_|setM1~31_combout ; +wire \z80_|execute_|setM1~32_combout ; +wire \z80_|execute_|setM1~34_combout ; +wire \z80_|execute_|setM1~20_combout ; +wire \z80_|execute_|setM1~21_combout ; +wire \z80_|execute_|setM1~35_combout ; +wire \z80_|execute_|setM1~15_combout ; +wire \z80_|execute_|setM1~14_combout ; +wire \z80_|execute_|setM1~16_combout ; +wire \z80_|execute_|setM1~10_combout ; +wire \z80_|execute_|setM1~12_combout ; +wire \z80_|execute_|setM1~8_combout ; +wire \z80_|execute_|setM1~9_combout ; +wire \z80_|execute_|setM1~13_combout ; +wire \z80_|execute_|setM1~18_combout ; +wire \z80_|execute_|setM1~19_combout ; +wire \z80_|execute_|setM1~43_combout ; +wire \z80_|execute_|setM1~42_combout ; +wire \z80_|execute_|setM1~44_combout ; +wire \z80_|execute_|setM1~45_combout ; +wire \z80_|execute_|setM1~51_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; +wire \z80_|sequencer_|T6~q ; +wire \z80_|execute_|setM1~52_combout ; +wire \z80_|execute_|setM1~53_combout ; +wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M1_ff~q ; +wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~q ; +wire \z80_|execute_|ctl_apin_mux~1_combout ; wire \z80_|execute_|ctl_apin_mux~2_combout ; wire \z80_|address_pins_|DFFE_apin_latch[0]~0_combout ; -wire \D[0]~59_combout ; -wire \D[0]~60_combout ; -wire \D[1]~61_combout ; -wire \D[1]~62_combout ; -wire \D[2]~63_combout ; -wire \D[2]~64_combout ; -wire \D[3]~75_combout ; -wire \D[3]~76_combout ; -wire \D[4]~82_combout ; -wire \D[4]~83_combout ; -wire \D[6]~92_combout ; -wire \D[6]~93_combout ; +wire \D[0]~66_combout ; +wire \D[0]~67_combout ; +wire \D[0]~121_combout ; +wire \D[1]~68_combout ; +wire \D[1]~69_combout ; +wire \D[2]~70_combout ; +wire \D[2]~71_combout ; +wire \D[3]~83_combout ; +wire \D[3]~84_combout ; +wire \D[4]~95_combout ; +wire \D[4]~96_combout ; +wire \D[5]~126_combout ; +wire \D[5]~98_combout ; +wire \D[6]~105_combout ; +wire \D[6]~106_combout ; +wire \D[7]~128_combout ; +wire \D[7]~107_combout ; +wire \z80_|memory_ifc_|nIORQ_out~0_combout ; wire \z80_|nM1_int~3_combout ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ; @@ -2482,26 +2541,43 @@ wire \z80_|memory_ifc_|DFFE_mreq_ff2~q ; wire \z80_|memory_ifc_|nMREQ_out~0_combout ; wire \z80_|memory_ifc_|nMREQ_out~1_combout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ; -wire \ula_|i2c_loader_|state.Idle~feeder_combout ; wire \ula_|i2c_loader_|divider[0]~15_combout ; wire \ula_|i2c_loader_|divider[1]~5_combout ; wire \ula_|i2c_loader_|divider[1]~6 ; wire \ula_|i2c_loader_|divider[2]~7_combout ; wire \ula_|i2c_loader_|divider[2]~8 ; wire \ula_|i2c_loader_|divider[3]~9_combout ; +wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|divider[3]~10 ; wire \ula_|i2c_loader_|divider[4]~11_combout ; wire \ula_|i2c_loader_|divider[4]~12 ; wire \ula_|i2c_loader_|divider[5]~13_combout ; -wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|WideAnd0~combout ; +wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; +wire \ula_|i2c_loader_|state.Idle~feeder_combout ; wire \ula_|i2c_loader_|state.Idle~q ; wire \ula_|i2c_loader_|phase~0_combout ; wire \ula_|i2c_loader_|phase~1_combout ; -wire \ula_|i2c_loader_|nbit~5_combout ; -wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; wire \ula_|i2c_loader_|Mux42~0_combout ; +wire \ula_|i2c_loader_|nbyte~0_combout ; +wire \ula_|i2c_loader_|nbit~4_combout ; wire \ula_|i2c_loader_|nbyte~4_combout ; +wire \ula_|i2c_loader_|nbit[0]~1_combout ; +wire \ula_|i2c_loader_|nbit[0]~2_combout ; +wire \ula_|i2c_loader_|nbit[0]~3_combout ; +wire \ula_|i2c_loader_|nbit~5_combout ; +wire \ula_|i2c_loader_|state.Pause~1_combout ; +wire \ula_|i2c_loader_|state~27_combout ; +wire \ula_|i2c_loader_|state~24_combout ; +wire \ula_|i2c_loader_|state~26_combout ; +wire \ula_|i2c_loader_|state.Data~0_combout ; +wire \ula_|i2c_loader_|state.Data~q ; +wire \ula_|i2c_loader_|nbit~0_combout ; +wire \ula_|i2c_loader_|state.Pause~0_combout ; +wire \ula_|i2c_loader_|state.Idle~0_combout ; +wire \ula_|i2c_loader_|state.Ack~0_combout ; +wire \ula_|i2c_loader_|state.Ack~1_combout ; +wire \ula_|i2c_loader_|state.Ack~q ; wire \ula_|i2c_loader_|thisbyte[0]~7_combout ; wire \I2C_SDAT~input_o ; wire \ula_|i2c_loader_|nbyte[0]~1_combout ; @@ -2510,12 +2586,8 @@ wire \ula_|i2c_loader_|nbyte[0]~3_combout ; wire \ula_|i2c_loader_|state.Stop~0_combout ; wire \ula_|i2c_loader_|state.Stop~1_combout ; wire \ula_|i2c_loader_|state.Stop~q ; -wire \ula_|i2c_loader_|state.Idle~0_combout ; -wire \ula_|i2c_loader_|nbit~0_combout ; -wire \ula_|i2c_loader_|state.Done~0_combout ; -wire \ula_|i2c_loader_|state.Ack~0_combout ; -wire \ula_|i2c_loader_|state.Ack~1_combout ; -wire \ula_|i2c_loader_|state.Ack~q ; +wire \ula_|i2c_loader_|state.Pause~2_combout ; +wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; wire \ula_|i2c_loader_|nbyte[1]~5_combout ; wire \ula_|i2c_loader_|thisbyte[0]~18_combout ; wire \ula_|i2c_loader_|thisbyte[0]~9 ; @@ -2525,56 +2597,43 @@ wire \ula_|i2c_loader_|thisbyte[2]~12_combout ; wire \ula_|i2c_loader_|thisbyte[2]~13 ; wire \ula_|i2c_loader_|thisbyte[3]~14_combout ; wire \ula_|i2c_loader_|Equal2~0_combout ; -wire \ula_|i2c_loader_|state.Pause~0_combout ; wire \ula_|i2c_loader_|thisbyte[3]~15 ; wire \ula_|i2c_loader_|thisbyte[4]~16_combout ; -wire \ula_|i2c_loader_|state.Pause~1_combout ; -wire \ula_|i2c_loader_|state.Done~2_combout ; -wire \ula_|i2c_loader_|state.Pause~2_combout ; wire \ula_|i2c_loader_|state.Pause~3_combout ; +wire \ula_|i2c_loader_|scl_out~0_combout ; +wire \ula_|i2c_loader_|state.Pause~4_combout ; +wire \ula_|i2c_loader_|state.Pause~5_combout ; +wire \ula_|i2c_loader_|state.Pause~6_combout ; wire \ula_|i2c_loader_|state.Pause~q ; wire \ula_|i2c_loader_|state~25_combout ; wire \ula_|i2c_loader_|state.Start~q ; -wire \ula_|i2c_loader_|nbyte~0_combout ; -wire \ula_|i2c_loader_|nbit[0]~1_combout ; -wire \ula_|i2c_loader_|nbit[0]~2_combout ; -wire \ula_|i2c_loader_|nbit[0]~3_combout ; -wire \ula_|i2c_loader_|nbit[0]~4_combout ; -wire \ula_|i2c_loader_|nbit~6_combout ; -wire \ula_|i2c_loader_|state.Done~1_combout ; -wire \ula_|i2c_loader_|state~27_combout ; -wire \ula_|i2c_loader_|state~24_combout ; -wire \ula_|i2c_loader_|state~26_combout ; -wire \ula_|i2c_loader_|state.Data~0_combout ; -wire \ula_|i2c_loader_|state.Data~q ; -wire \ula_|i2c_loader_|scl_out~0_combout ; -wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; wire \ula_|i2c_loader_|scl_out~1_combout ; wire \ula_|i2c_loader_|scl_out~2_combout ; wire \ula_|i2c_loader_|scl_out~q ; wire \ula_|i2c_loader_|sda_out~_Duplicate_1_q ; -wire \ula_|i2c_loader_|shiftreg~4_combout ; wire \ula_|i2c_loader_|Mux35~0_combout ; -wire \ula_|i2c_loader_|shiftreg~13_combout ; -wire \ula_|i2c_loader_|shiftreg~14_combout ; -wire \ula_|i2c_loader_|shiftreg~15_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~24_combout ; +wire \ula_|i2c_loader_|shiftreg~4_combout ; +wire \ula_|i2c_loader_|shiftreg~19_combout ; +wire \ula_|i2c_loader_|shiftreg~20_combout ; +wire \ula_|i2c_loader_|shiftreg~22_combout ; +wire \ula_|i2c_loader_|shiftreg~23_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~25_combout ; wire \ula_|i2c_loader_|shiftreg[0]~6_combout ; wire \ula_|i2c_loader_|shiftreg[0]~7_combout ; wire \ula_|i2c_loader_|shiftreg[0]~8_combout ; -wire \ula_|i2c_loader_|shiftreg~21_combout ; -wire \ula_|i2c_loader_|shiftreg~22_combout ; -wire \ula_|i2c_loader_|shiftreg~23_combout ; +wire \ula_|i2c_loader_|shiftreg~24_combout ; wire \ula_|i2c_loader_|shiftreg[6]~10_combout ; wire \ula_|i2c_loader_|shiftreg[6]~11_combout ; -wire \ula_|i2c_loader_|shiftreg~18_combout ; -wire \ula_|i2c_loader_|shiftreg~19_combout ; -wire \ula_|i2c_loader_|shiftreg~20_combout ; -wire \ula_|i2c_loader_|shiftreg~16_combout ; +wire \ula_|i2c_loader_|shiftreg[6]~12_combout ; +wire \ula_|i2c_loader_|shiftreg~21_combout ; wire \ula_|i2c_loader_|shiftreg~17_combout ; +wire \ula_|i2c_loader_|shiftreg~15_combout ; +wire \ula_|i2c_loader_|shiftreg~18_combout ; +wire \ula_|i2c_loader_|shiftreg~27_combout ; +wire \ula_|i2c_loader_|shiftreg~14_combout ; +wire \ula_|i2c_loader_|shiftreg~16_combout ; wire \ula_|i2c_loader_|shiftreg~26_combout ; -wire \ula_|i2c_loader_|shiftreg~25_combout ; -wire \ula_|i2c_loader_|shiftreg~12_combout ; +wire \ula_|i2c_loader_|shiftreg~13_combout ; wire \ula_|i2c_loader_|shiftreg~9_combout ; wire \ula_|i2c_loader_|shiftreg[7]~5_combout ; wire \ula_|i2c_loader_|sda_out~0_combout ; @@ -2583,6 +2642,142 @@ wire \ula_|i2c_loader_|sda_out~2_combout ; wire \ula_|i2c_loader_|sda_out~3_combout ; wire \ula_|i2c_loader_|sda_out~4_combout ; wire \ula_|i2c_loader_|sda_out~q ; +wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_fbout ; +wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \sdram_|Mux38~0_combout ; +wire \sdram_|r.rd_pending~q ; +wire \sdram_|r.rf_counter[0]~12_combout ; +wire \sdram_|r.rf_counter[3]~32_combout ; +wire \sdram_|r.rf_counter[0]~13 ; +wire \sdram_|r.rf_counter[1]~14_combout ; +wire \sdram_|r.rf_counter[1]~15 ; +wire \sdram_|r.rf_counter[2]~16_combout ; +wire \sdram_|r.rf_counter[2]~17 ; +wire \sdram_|r.rf_counter[3]~18_combout ; +wire \sdram_|r.rf_counter[3]~19 ; +wire \sdram_|r.rf_counter[4]~20_combout ; +wire \sdram_|r.rf_counter[4]~21 ; +wire \sdram_|r.rf_counter[5]~22_combout ; +wire \sdram_|r.rf_counter[5]~23 ; +wire \sdram_|r.rf_counter[6]~24_combout ; +wire \sdram_|r.rf_counter[6]~25 ; +wire \sdram_|r.rf_counter[7]~26_combout ; +wire \sdram_|Equal0~1_combout ; +wire \sdram_|r.rf_counter[7]~27 ; +wire \sdram_|r.rf_counter[8]~28_combout ; +wire \sdram_|Equal0~0_combout ; +wire \sdram_|r.rf_counter[8]~29 ; +wire \sdram_|r.rf_counter[9]~30_combout ; +wire \sdram_|Equal0~2_combout ; +wire \sdram_|Mux13~8_combout ; +wire \sdram_|Mux37~0_combout ; +wire \sdram_|r.rf_pending~q ; +wire \sdram_|Mux4~0_combout ; +wire \sdram_|Mux4~1_combout ; +wire \sdram_|Mux4~2_combout ; +wire \sdram_|Mux4~3_combout ; +wire \sdram_|r.act_row[1]~0_combout ; +wire \sdram_|process_0~2_combout ; +wire \sdram_|r.act_row[1]~1_combout ; +wire \sdram_|r.act_row[2]~feeder_combout ; +wire \sdram_|Equal7~1_combout ; +wire \sdram_|Equal7~0_combout ; +wire \sdram_|Equal7~2_combout ; +wire \sdram_|Mux39~0_combout ; +wire \sdram_|Mux39~1_combout ; +wire \sdram_|Mux39~2_combout ; +wire \sdram_|r.wr_pending~q ; +wire \sdram_|Mux9~8_combout ; +wire \sdram_|Mux9~9_combout ; +wire \sdram_|Mux6~3_combout ; +wire \sdram_|Mux6~4_combout ; +wire \sdram_|Mux6~2_combout ; +wire \sdram_|Mux6~5_combout ; +wire \sdram_|process_0~3_combout ; +wire \sdram_|Mux6~0_combout ; +wire \sdram_|Mux6~1_combout ; +wire \sdram_|Mux6~6_combout ; +wire \sdram_|r.address[3]~6_combout ; +wire \sdram_|Mux7~2_combout ; +wire \sdram_|n~3_combout ; +wire \sdram_|Mux7~3_combout ; +wire \sdram_|Mux7~4_combout ; +wire \sdram_|Mux7~5_combout ; +wire \sdram_|Mux23~0_combout ; +wire \sdram_|Mux13~7_combout ; +wire \sdram_|Mux10~10_combout ; +wire \sdram_|Mux7~1_combout ; +wire \sdram_|Mux7~6_combout ; +wire \sdram_|Mux5~2_combout ; +wire \sdram_|Mux5~10_combout ; +wire \sdram_|Mux5~3_combout ; +wire \sdram_|Mux5~4_combout ; +wire \sdram_|Mux5~7_combout ; +wire \sdram_|Mux5~8_combout ; +wire \sdram_|Mux5~5_combout ; +wire \sdram_|Mux5~6_combout ; +wire \sdram_|Mux5~9_combout ; +wire \sdram_|n~2_combout ; +wire \sdram_|Mux8~3_combout ; +wire \sdram_|Mux8~4_combout ; +wire \sdram_|Mux9~10_combout ; +wire \sdram_|r.init_counter[0]~0_combout ; +wire \sdram_|Add1~1_cout ; +wire \sdram_|Add1~2_combout ; +wire \sdram_|Add1~3 ; +wire \sdram_|Add1~4_combout ; +wire \sdram_|Add1~5 ; +wire \sdram_|Add1~6_combout ; +wire \sdram_|r.init_counter[3]~1_combout ; +wire \sdram_|Add1~7 ; +wire \sdram_|Add1~8_combout ; +wire \sdram_|Add1~9 ; +wire \sdram_|Add1~10_combout ; +wire \sdram_|Add1~11 ; +wire \sdram_|Add1~12_combout ; +wire \sdram_|Add1~13 ; +wire \sdram_|Add1~14_combout ; +wire \sdram_|Add1~15 ; +wire \sdram_|Add1~16_combout ; +wire \sdram_|Add1~17 ; +wire \sdram_|Add1~18_combout ; +wire \sdram_|Add1~19 ; +wire \sdram_|Add1~20_combout ; +wire \sdram_|Equal2~0_combout ; +wire \sdram_|Equal2~1_combout ; +wire \sdram_|Add1~21 ; +wire \sdram_|Add1~22_combout ; +wire \sdram_|Add1~23 ; +wire \sdram_|Add1~24_combout ; +wire \sdram_|Add1~25 ; +wire \sdram_|Add1~26_combout ; +wire \sdram_|Add1~27 ; +wire \sdram_|Add1~28_combout ; +wire \sdram_|process_0~5_combout ; +wire \sdram_|Equal2~2_combout ; +wire \sdram_|Mux9~11_combout ; +wire \sdram_|Mux9~12_combout ; +wire \sdram_|Mux9~13_combout ; +wire \sdram_|Mux8~0_combout ; +wire \sdram_|Mux8~1_combout ; +wire \sdram_|Mux8~2_combout ; +wire \sdram_|Mux72~0_combout ; +wire \sdram_|Mux72~1_combout ; +wire \sdram_|Mux84~0_combout ; +wire \sdram_|Mux84~1_combout ; +wire \sdram_|Mux3~0_combout ; +wire \sdram_|Mux3~1_combout ; +wire \sdram_|Mux2~0_combout ; +wire \sdram_|Mux2~1_combout ; +wire \sdram_|Mux1~0_combout ; +wire \sdram_|Mux1~1_combout ; +wire \sdram_|Mux0~0_combout ; +wire \sdram_|Mux0~1_combout ; +wire \sdram_|Mux73~0_combout ; +wire \sdram_|Mux73~1_combout ; +wire \sdram_|Mux74~0_combout ; +wire \sdram_|Mux74~1_combout ; +wire \sdram_|Mux75~0_combout ; wire \ula_|i2s_intf_|mclk_r~0_combout ; wire \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|mclk_r~q ; @@ -2616,12 +2811,13 @@ wire \ula_|i2s_intf_|Add0~18_combout ; wire \ula_|i2s_intf_|lrdivider[9]~3_combout ; wire \ula_|i2s_intf_|Equal0~0_combout ; wire \ula_|i2s_intf_|Equal0~2_combout ; -wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; wire \ula_|i2s_intf_|lrclk_r~0_combout ; wire \ula_|i2s_intf_|lrclk_r~q ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_1_q ; +wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|bitcount[0]~5_combout ; +wire \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ; wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|bitcount[4]~15_combout ; wire \ula_|i2s_intf_|bitcount[0]~6 ; @@ -2630,9 +2826,10 @@ wire \ula_|i2s_intf_|bitcount[1]~8 ; wire \ula_|i2s_intf_|bitcount[2]~9_combout ; wire \ula_|i2s_intf_|bitcount[2]~10 ; wire \ula_|i2s_intf_|bitcount[3]~11_combout ; -wire \ula_|i2s_intf_|LessThan0~0_combout ; wire \ula_|i2s_intf_|bitcount[3]~12 ; wire \ula_|i2s_intf_|bitcount[4]~13_combout ; +wire \ula_|i2s_intf_|LessThan0~0_combout ; +wire \ula_|i2s_intf_|shiftreg[1]~1_combout ; wire \ula_|i2s_intf_|Add2~7_cout ; wire \ula_|i2s_intf_|Add2~8_combout ; wire \ula_|i2s_intf_|Add2~20_combout ; @@ -2646,8 +2843,6 @@ wire \ula_|i2s_intf_|Add2~13 ; wire \ula_|i2s_intf_|Add2~14_combout ; wire \ula_|i2s_intf_|Add2~16_combout ; wire \ula_|i2s_intf_|Equal1~0_combout ; -wire \ula_|i2s_intf_|shiftreg[4]~1_combout ; -wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|Equal1~1_combout ; wire \ula_|i2s_intf_|bclk_r~0_combout ; wire \ula_|i2s_intf_|bclk_r~1_combout ; @@ -2659,7 +2854,7 @@ wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; wire \AUD_ADCDAT~input_o ; wire \ula_|i2s_intf_|shiftreg[0]~20_combout ; wire \ula_|i2s_intf_|shiftreg~18_combout ; -wire \ula_|i2s_intf_|shiftreg[4]~2_combout ; +wire \ula_|i2s_intf_|shiftreg[1]~2_combout ; wire \ula_|i2s_intf_|shiftreg~17_combout ; wire \ula_|i2s_intf_|shiftreg~16_combout ; wire \ula_|i2s_intf_|shiftreg~15_combout ; @@ -2676,28 +2871,20 @@ wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; wire \ula_|pcm_outr~0_combout ; wire \ula_|i2s_intf_|shiftreg~6_combout ; wire \ula_|i2s_intf_|shiftreg~5_combout ; +wire \ula_|pcm_outl[14]~feeder_combout ; wire \ula_|i2s_intf_|shiftreg~4_combout ; wire \ula_|i2s_intf_|shiftreg~3_combout ; wire \ula_|i2s_intf_|shiftreg~0_combout ; -wire \ula_|video_|LessThan2~0_combout ; +wire \ula_|border[1]~feeder_combout ; wire \ula_|video_|LessThan6~0_combout ; -wire \ula_|video_|LessThan2~1_combout ; -wire \ula_|video_|LessThan3~0_combout ; -wire \ula_|video_|LessThan0~0_combout ; -wire \ula_|video_|disp_enable~0_combout ; -wire \ula_|video_|disp_enable~1_combout ; wire \ula_|video_|LessThan6~1_combout ; wire \ula_|video_|LessThan4~0_combout ; wire \ula_|video_|screen_en~0_combout ; wire \ula_|video_|screen_en~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; -wire \ula_|video_|attr_prefetch[1]~feeder_combout ; -wire \ula_|video_|Decoder0~1_combout ; -wire \ula_|video_|Decoder0~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; -wire \ula_|video_|attr_prefetch[4]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; wire \ula_|video_|attr_prefetch[7]~feeder_combout ; +wire \ula_|video_|Decoder0~1_combout ; +wire \ula_|video_|Decoder0~0_combout ; wire \ula_|video_|frame[0]~12_combout ; wire \ula_|video_|frame[1]~4_combout ; wire \ula_|video_|frame[1]~5 ; @@ -2710,7 +2897,7 @@ wire \ula_|video_|inverted~combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[6]~feeder_combout ; wire \ula_|video_|Decoder0~2_combout ; -wire \ula_|video_|bits[6]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[4]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[5]~feeder_combout ; @@ -2723,25 +2910,35 @@ wire \ula_|video_|bits_prefetch[2]~feeder_combout ; wire \ula_|video_|bits[2]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[0]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[1]~feeder_combout ; wire \ula_|video_|bits[1]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[3]~feeder_combout ; wire \ula_|video_|Mux0~2_combout ; wire \ula_|video_|Mux0~3_combout ; -wire \ula_|video_|cindex[1]~0_combout ; +wire \ula_|video_|cindex[2]~0_combout ; +wire \ula_|video_|attr_prefetch[4]~feeder_combout ; +wire \ula_|video_|attr_prefetch[1]~feeder_combout ; wire \ula_|video_|cindex[1]~1_combout ; +wire \ula_|video_|LessThan2~0_combout ; +wire \ula_|video_|LessThan2~1_combout ; +wire \ula_|video_|LessThan3~0_combout ; +wire \ula_|video_|LessThan0~0_combout ; +wire \ula_|video_|disp_enable~0_combout ; +wire \ula_|video_|disp_enable~1_combout ; wire \ula_|video_|VGA_R[0]~0_combout ; wire \ula_|video_|attr_prefetch[6]~feeder_combout ; wire \ula_|video_|VGA_B[1]~0_combout ; wire \ula_|video_|VGA_R[1]~1_combout ; -wire \ula_|video_|attr_prefetch[2]~feeder_combout ; +wire \ula_|border[2]~feeder_combout ; wire \ula_|video_|attr_prefetch[5]~feeder_combout ; +wire \ula_|video_|attr_prefetch[2]~feeder_combout ; wire \ula_|video_|cindex[2]~2_combout ; wire \ula_|video_|VGA_G[0]~0_combout ; wire \ula_|video_|VGA_G[1]~1_combout ; +wire \ula_|border[0]~feeder_combout ; wire \ula_|video_|attr_prefetch[0]~feeder_combout ; -wire \ula_|video_|attr[0]~feeder_combout ; wire \ula_|video_|attr_prefetch[3]~feeder_combout ; wire \ula_|video_|cindex[0]~3_combout ; wire \ula_|video_|VGA_B[0]~1_combout ; @@ -2760,23 +2957,171 @@ wire \z80_|memory_ifc_|nRFSH_out~0_combout ; wire \z80_|memory_ifc_|nM1_out~combout ; wire \ula_|beep~0_combout ; wire \ula_|beep~q ; -wire [0:0] \ram0|altsyncram_component|auto_generated|address_reg_a ; +wire \sdram_|Mux26~4_combout ; +wire \sdram_|r.bank[0]~7_combout ; +wire \sdram_|r.bank[0]~11_combout ; +wire \sdram_|r.bank[0]~4_combout ; +wire \sdram_|r.bank[0]~5_combout ; +wire \sdram_|r.bank[0]~6_combout ; +wire \sdram_|r.bank[0]~8_combout ; +wire \sdram_|r.bank[0]~12_combout ; +wire \sdram_|r.bank[0]~9_combout ; +wire \sdram_|Mux25~4_combout ; +wire \sdram_|Mux24~5_combout ; +wire \sdram_|Mux71~0_combout ; +wire \sdram_|process_0~7_combout ; +wire \sdram_|process_0~4_combout ; +wire \sdram_|Mux71~1_combout ; +wire \sdram_|Mux71~2_combout ; +wire \sdram_|Mux71~3_combout ; +wire \sdram_|Mux71~4_combout ; +wire \sdram_|r.bank[0]~10_combout ; +wire \sdram_|Mux9~3_combout ; +wire \sdram_|n~5_combout ; +wire \sdram_|Mux9~4_combout ; +wire \sdram_|Mux9~2_combout ; +wire \sdram_|Equal2~3_combout ; +wire \sdram_|Mux10~2_combout ; +wire \sdram_|Mux10~3_combout ; +wire \sdram_|process_0~6_combout ; +wire \sdram_|Mux10~4_combout ; +wire \sdram_|Mux9~5_combout ; +wire \sdram_|Mux7~0_combout ; +wire \sdram_|Mux9~6_combout ; +wire \sdram_|Mux9~7_combout ; +wire \sdram_|Mux10~11_combout ; +wire \sdram_|Mux10~6_combout ; +wire \sdram_|Mux10~5_combout ; +wire \sdram_|Mux10~7_combout ; +wire \sdram_|Mux10~8_combout ; +wire \sdram_|Mux10~9_combout ; +wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK_outclk ; +wire \sdram_|Mux11~2_combout ; +wire \sdram_|Mux11~3_combout ; +wire \sdram_|Mux11~4_combout ; +wire \sdram_|Mux11~5_combout ; +wire \sdram_|Mux11~6_combout ; +wire \sdram_|Mux11~7_combout ; +wire \sdram_|Mux11~9_combout ; +wire \sdram_|Mux11~8_combout ; +wire \sdram_|Mux24~2_combout ; +wire \sdram_|r.address[0]~7_combout ; +wire \sdram_|r.address[0]~0_combout ; +wire \sdram_|Mux13~9_combout ; +wire \sdram_|Mux13~4_combout ; +wire \sdram_|Mux13~5_combout ; +wire \sdram_|r.address[0]~_Duplicate_1_q ; +wire \sdram_|Mux24~3_combout ; +wire \sdram_|Mux24~4_combout ; +wire \sdram_|r.address[0]~SLOAD_MUX_combout ; +wire \sdram_|r.address[1]~_Duplicate_1feeder_combout ; +wire \sdram_|Mux23~4_combout ; +wire \sdram_|Equal5~0_combout ; +wire \sdram_|Mux23~5_combout ; +wire \sdram_|Mux23~6_combout ; +wire \sdram_|Mux19~0_combout ; +wire \sdram_|r.address[1]~_Duplicate_1_q ; +wire \sdram_|Mux23~2_combout ; +wire \sdram_|Mux23~3_combout ; +wire \sdram_|Mux23~1_combout ; +wire \sdram_|r.address[1]~1_combout ; +wire \sdram_|r.address[1]~SLOAD_MUX_combout ; +wire \sdram_|r.address[3]~8_combout ; +wire \sdram_|r.address[3]~9_combout ; +wire \sdram_|Mux21~0_combout ; +wire \sdram_|Mux22~0_combout ; +wire \sdram_|r.address[3]~10_combout ; +wire \sdram_|r.address[3]~11_combout ; +wire \sdram_|r.address[3]~12_combout ; +wire \sdram_|r.address[3]~13_combout ; +wire \sdram_|r.address[3]~14_combout ; +wire \sdram_|r.address[3]~15_combout ; +wire \sdram_|r.address[3]~16_combout ; +wire \sdram_|r.address[3]~17_combout ; +wire \sdram_|Mux21~1_combout ; +wire \sdram_|Mux20~4_combout ; +wire \sdram_|Mux20~7_combout ; +wire \sdram_|Mux23~7_combout ; +wire \sdram_|Mux20~8_combout ; +wire \sdram_|Mux20~10_combout ; +wire \sdram_|Mux20~9_combout ; +wire \sdram_|Mux20~11_combout ; +wire \sdram_|r.address[4]~_Duplicate_1_q ; +wire \sdram_|Mux20~12_combout ; +wire \sdram_|Mux20~5_combout ; +wire \sdram_|Mux20~6_combout ; +wire \sdram_|r.address[4]~2_combout ; +wire \sdram_|r.address[4]~SLOAD_MUX_combout ; +wire \sdram_|Mux19~1_combout ; +wire \sdram_|Mux19~4_combout ; +wire \sdram_|Mux19~5_combout ; +wire \sdram_|Mux19~6_combout ; +wire \sdram_|Mux19~7_combout ; +wire \sdram_|r.address[5]~_Duplicate_1_q ; +wire \sdram_|Mux19~2_combout ; +wire \sdram_|Mux19~3_combout ; +wire \sdram_|r.address[5]~3_combout ; +wire \sdram_|r.address[5]~SLOAD_MUX_combout ; +wire \sdram_|Mux18~0_combout ; +wire \sdram_|Mux17~0_combout ; +wire \sdram_|Mux16~0_combout ; +wire \sdram_|Mux15~2_combout ; +wire \sdram_|Mux14~0_combout ; +wire \sdram_|Mux14~1_combout ; +wire \sdram_|r.address[10]~4_combout ; +wire \sdram_|r.address[10]~_Duplicate_1_q ; +wire \sdram_|n~4_combout ; +wire \sdram_|Mux14~2_combout ; +wire \sdram_|Mux14~3_combout ; +wire \sdram_|r.address[10]~SLOAD_MUX_combout ; +wire \sdram_|r.address[11]~18_combout ; +wire \sdram_|r.address[11]~5_combout ; +wire \sdram_|r.address[11]~_Duplicate_2feeder_combout ; +wire \sdram_|r.address[11]~_Duplicate_2_q ; +wire \sdram_|Mux13~10_combout ; +wire \sdram_|Mux13~6_combout ; +wire \sdram_|r.address[11]~SLOAD_MUX_combout ; +wire \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout ; +wire \sdram_|r.address[11]~_Duplicate_1_q ; +wire [9:0] \sdram_|r.rf_counter ; +wire [12:0] \sdram_|r.address ; +wire [15:0] \ula_|pcm_outl ; +wire [1:0] \ula_|i2c_loader_|nbyte ; +wire [4:0] \ula_|i2s_intf_|bitcount ; +wire [4:0] \ula_|video_|frame ; +wire [7:0] \ula_|video_|attr_prefetch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_ix_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_pc_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_wz_hi|latch ; wire [1:0] \ram1|altsyncram_component|auto_generated|address_reg_a ; -wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode244w ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode223w ; +wire [3:0] \z80_|alu_|op2_low ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; +wire [15:0] \z80_|address_latch_|abusz ; +wire [7:0] \z80_|data_pins_|dout ; +wire [8:0] \sdram_|r.state ; +wire [14:0] \sdram_|r.init_counter ; +wire [1:0] \sdram_|r.bank ; +wire [12:0] \sdram_|r.act_row ; wire [2:0] \ula_|border ; wire [0:0] \ula_|clocks_|counter ; -wire [7:0] \ula_|i2c_loader_|shiftreg ; -wire [1:0] \ula_|i2c_loader_|nbyte ; -wire [5:0] \ula_|i2c_loader_|divider ; -wire [17:0] \ula_|i2s_intf_|shiftreg ; -wire [4:0] \ula_|i2s_intf_|bitcount ; -wire [15:0] \ula_|i2s_intf_|PCM_INR ; -wire [9:0] \ula_|video_|vga_vc ; -wire [4:0] \ula_|video_|frame ; -wire [7:0] \ula_|video_|bits_prefetch ; -wire [7:0] \ula_|video_|attr_prefetch ; -wire [7:0] \ula_|ps2_keyboard_|clk_filter ; +wire [4:0] \ula_|i2c_loader_|thisbyte ; +wire [1:0] \ula_|i2c_loader_|phase ; +wire [2:0] \ula_|i2c_loader_|nbit ; +wire [9:0] \ula_|i2s_intf_|lrdivider ; +wire [4:0] \ula_|i2s_intf_|bdivider ; +wire [15:0] \ula_|i2s_intf_|PCM_INL ; +wire [12:0] \ula_|video_|vram_address ; +wire [9:0] \ula_|video_|vga_hc ; +wire [7:0] \ula_|video_|bits ; +wire [7:0] \ula_|video_|attr ; +wire [8:0] \ula_|ps2_keyboard_|shiftreg ; +wire [3:0] \ula_|ps2_keyboard_|bit_count ; wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; @@ -2790,126 +3135,119 @@ wire [7:0] \z80_|reg_file_|b2v_latch_iy_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_pc_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_sp_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; -wire [3:0] \z80_|alu_|op2_low ; -wire [3:0] \z80_|alu_|op1_low ; -wire [15:0] \z80_|address_latch_|Q ; -wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; -wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; -wire [7:0] \z80_|data_pins_|dout ; -wire [7:0] \z80_|ir_|opcode ; wire [0:0] \ram0|altsyncram_component|auto_generated|out_address_reg_a ; wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode252w ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode236w ; -wire [15:0] \ula_|pcm_outl ; -wire [4:0] \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk ; -wire [4:0] \ula_|i2c_loader_|thisbyte ; -wire [1:0] \ula_|i2c_loader_|phase ; -wire [2:0] \ula_|i2c_loader_|nbit ; -wire [9:0] \ula_|i2s_intf_|lrdivider ; -wire [4:0] \ula_|i2s_intf_|bdivider ; -wire [15:0] \ula_|i2s_intf_|PCM_INL ; -wire [12:0] \ula_|video_|vram_address ; -wire [9:0] \ula_|video_|vga_hc ; -wire [7:0] \ula_|video_|bits ; -wire [7:0] \ula_|video_|attr ; -wire [8:0] \ula_|ps2_keyboard_|shiftreg ; -wire [3:0] \ula_|ps2_keyboard_|bit_count ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_ix_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_iy_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_pc_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_sp_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_wz_hi|latch ; wire [3:0] \z80_|alu_|result_lo ; wire [3:0] \z80_|alu_|op2_high ; wire [3:0] \z80_|alu_|op1_high ; wire [3:0] \z80_|alu_|b2v_op1_latch_mux_high|Q ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; -wire [15:0] \z80_|address_latch_|abusz ; +wire [15:0] \z80_|address_latch_|Q ; +wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; +wire [7:0] \z80_|ir_|opcode ; +wire [1:0] \sdram_|r.dq_masks ; +wire [4:0] \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk ; +wire [4:0] \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk ; +wire [7:0] \ula_|i2c_loader_|shiftreg ; +wire [5:0] \ula_|i2c_loader_|divider ; +wire [17:0] \ula_|i2s_intf_|shiftreg ; +wire [15:0] \ula_|i2s_intf_|PCM_INR ; +wire [9:0] \ula_|video_|vga_vc ; +wire [7:0] \ula_|video_|bits_prefetch ; +wire [7:0] \ula_|ps2_keyboard_|clk_filter ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_iy_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_sp_hi|latch ; +wire [0:0] \ram0|altsyncram_component|auto_generated|address_reg_a ; +wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode244w ; +wire [3:0] \z80_|alu_|op1_low ; +wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; +wire [4:0] \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus ; wire [4:0] \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; + +assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [0] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [1] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [2] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [3] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [4] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [4]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [0] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [0]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [1] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [1]; @@ -2917,24 +3255,24 @@ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [2] = \ula_|pll_ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [3] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [3]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [4] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [4]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; - assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0]; @@ -2947,12 +3285,12 @@ assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; @@ -2965,55 +3303,47 @@ assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \r assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; @@ -3025,6 +3355,14 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0]; @@ -3037,19 +3375,11 @@ assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; @@ -3061,6 +3391,14 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; + // Location: IOOBUF_X53_Y21_N23 cycloneive_io_obuf \GPIO_1[0]~output ( .i(\z80_|address_pins_|DFFE_apin_latch [0]), @@ -3271,8 +3609,8 @@ defparam \GPIO_1[15]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N9 cycloneive_io_obuf \GPIO_1[16]~output ( - .i(\D[0]~60_combout ), - .oe(\D[0]~107_combout ), + .i(\D[0]~67_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[16]), @@ -3284,8 +3622,8 @@ defparam \GPIO_1[16]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y12_N2 cycloneive_io_obuf \GPIO_1[17]~output ( - .i(\D[1]~62_combout ), - .oe(\D[0]~107_combout ), + .i(\D[1]~69_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[17]), @@ -3297,8 +3635,8 @@ defparam \GPIO_1[17]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y8_N23 cycloneive_io_obuf \GPIO_1[18]~output ( - .i(\D[2]~64_combout ), - .oe(\D[0]~107_combout ), + .i(\D[2]~71_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[18]), @@ -3310,8 +3648,8 @@ defparam \GPIO_1[18]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N2 cycloneive_io_obuf \GPIO_1[19]~output ( - .i(\D[3]~76_combout ), - .oe(\D[0]~107_combout ), + .i(\D[3]~84_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[19]), @@ -3323,8 +3661,8 @@ defparam \GPIO_1[19]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y6_N16 cycloneive_io_obuf \GPIO_1[20]~output ( - .i(\D[4]~83_combout ), - .oe(\D[0]~107_combout ), + .i(\D[4]~96_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[20]), @@ -3336,8 +3674,8 @@ defparam \GPIO_1[20]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y7_N9 cycloneive_io_obuf \GPIO_1[21]~output ( - .i(\D[5]~85_combout ), - .oe(\D[0]~107_combout ), + .i(\D[5]~98_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[21]), @@ -3349,8 +3687,8 @@ defparam \GPIO_1[21]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y0_N2 cycloneive_io_obuf \GPIO_1[22]~output ( - .i(\D[6]~93_combout ), - .oe(\D[0]~107_combout ), + .i(\D[6]~106_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[22]), @@ -3362,8 +3700,8 @@ defparam \GPIO_1[22]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y9_N23 cycloneive_io_obuf \GPIO_1[23]~output ( - .i(\D[7]~94_combout ), - .oe(\D[0]~107_combout ), + .i(\D[7]~107_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[23]), @@ -3401,7 +3739,7 @@ defparam \GPIO_1[28]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y10_N16 cycloneive_io_obuf \GPIO_1[29]~output ( - .i(!\z80_|memory_ifc_|nIORQ_out~0_combout ), + .i(\z80_|memory_ifc_|nIORQ_out~0_combout ), .oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3867,6 +4205,305 @@ defparam \buzzer_out~output .bus_hold = "false"; defparam \buzzer_out~output .open_drain_output = "false"; // synopsys translate_on +// Location: IOOBUF_X11_Y0_N16 +cycloneive_io_obuf \DRAM_BA[0]~output ( + .i(\sdram_|r.bank [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_BA[0]), + .obar()); +// synopsys translate_off +defparam \DRAM_BA[0]~output .bus_hold = "false"; +defparam \DRAM_BA[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y0_N9 +cycloneive_io_obuf \DRAM_BA[1]~output ( + .i(\sdram_|r.bank [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_BA[1]), + .obar()); +// synopsys translate_off +defparam \DRAM_BA[1]~output .bus_hold = "false"; +defparam \DRAM_BA[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y0_N9 +cycloneive_io_obuf \DRAM_DQM[0]~output ( + .i(\sdram_|r.dq_masks [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQM[0]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQM[0]~output .bus_hold = "false"; +defparam \DRAM_DQM[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y0_N16 +cycloneive_io_obuf \DRAM_DQM[1]~output ( + .i(\sdram_|r.dq_masks [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQM[1]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQM[1]~output .bus_hold = "false"; +defparam \DRAM_DQM[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y11_N2 +cycloneive_io_obuf \DRAM_RAS_N~output ( + .i(\sdram_|r.state [2]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_RAS_N), + .obar()); +// synopsys translate_off +defparam \DRAM_RAS_N~output .bus_hold = "false"; +defparam \DRAM_RAS_N~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y11_N9 +cycloneive_io_obuf \DRAM_CAS_N~output ( + .i(\sdram_|r.state [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_CAS_N), + .obar()); +// synopsys translate_off +defparam \DRAM_CAS_N~output .bus_hold = "false"; +defparam \DRAM_CAS_N~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N23 +cycloneive_io_obuf \DRAM_CKE~output ( + .i(vcc), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_CKE), + .obar()); +// synopsys translate_off +defparam \DRAM_CKE~output .bus_hold = "false"; +defparam \DRAM_CKE~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y0_N23 +cycloneive_io_obuf \DRAM_CLK~output ( + .i(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK_outclk ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_CLK), + .obar()); +// synopsys translate_off +defparam \DRAM_CLK~output .bus_hold = "false"; +defparam \DRAM_CLK~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y27_N2 +cycloneive_io_obuf \DRAM_WE_N~output ( + .i(\sdram_|r.state [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_WE_N), + .obar()); +// synopsys translate_off +defparam \DRAM_WE_N~output .bus_hold = "false"; +defparam \DRAM_WE_N~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y0_N23 +cycloneive_io_obuf \DRAM_CS_N~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_CS_N), + .obar()); +// synopsys translate_off +defparam \DRAM_CS_N~output .bus_hold = "false"; +defparam \DRAM_CS_N~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y4_N16 +cycloneive_io_obuf \DRAM_ADDR[0]~output ( + .i(\sdram_|r.address [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[0]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[0]~output .bus_hold = "false"; +defparam \DRAM_ADDR[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y0_N9 +cycloneive_io_obuf \DRAM_ADDR[1]~output ( + .i(\sdram_|r.address [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[1]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[1]~output .bus_hold = "false"; +defparam \DRAM_ADDR[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y0_N2 +cycloneive_io_obuf \DRAM_ADDR[2]~output ( + .i(\sdram_|r.address [2]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[2]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[2]~output .bus_hold = "false"; +defparam \DRAM_ADDR[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X20_Y0_N9 +cycloneive_io_obuf \DRAM_ADDR[3]~output ( + .i(\sdram_|r.address [3]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[3]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[3]~output .bus_hold = "false"; +defparam \DRAM_ADDR[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X25_Y0_N16 +cycloneive_io_obuf \DRAM_ADDR[4]~output ( + .i(\sdram_|r.address [4]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[4]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[4]~output .bus_hold = "false"; +defparam \DRAM_ADDR[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y0_N23 +cycloneive_io_obuf \DRAM_ADDR[5]~output ( + .i(\sdram_|r.address [5]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[5]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[5]~output .bus_hold = "false"; +defparam \DRAM_ADDR[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X20_Y0_N2 +cycloneive_io_obuf \DRAM_ADDR[6]~output ( + .i(\sdram_|r.address [6]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[6]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[6]~output .bus_hold = "false"; +defparam \DRAM_ADDR[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y0_N2 +cycloneive_io_obuf \DRAM_ADDR[7]~output ( + .i(\sdram_|r.address [7]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[7]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[7]~output .bus_hold = "false"; +defparam \DRAM_ADDR[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y5_N23 +cycloneive_io_obuf \DRAM_ADDR[8]~output ( + .i(\sdram_|r.address [8]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[8]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[8]~output .bus_hold = "false"; +defparam \DRAM_ADDR[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y4_N23 +cycloneive_io_obuf \DRAM_ADDR[9]~output ( + .i(\sdram_|r.address [9]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[9]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[9]~output .bus_hold = "false"; +defparam \DRAM_ADDR[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y8_N23 +cycloneive_io_obuf \DRAM_ADDR[10]~output ( + .i(\sdram_|r.address [10]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[10]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[10]~output .bus_hold = "false"; +defparam \DRAM_ADDR[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y7_N2 +cycloneive_io_obuf \DRAM_ADDR[11]~output ( + .i(\sdram_|r.address [11]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[11]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[11]~output .bus_hold = "false"; +defparam \DRAM_ADDR[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y6_N16 +cycloneive_io_obuf \DRAM_ADDR[12]~output ( + .i(\sdram_|r.address[11]~_Duplicate_1_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[12]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[12]~output .bus_hold = "false"; +defparam \DRAM_ADDR[12]~output .open_drain_output = "false"; +// synopsys translate_on + // Location: IOOBUF_X0_Y24_N23 cycloneive_io_obuf \I2C_SCLK~output ( .i(\ula_|i2c_loader_|scl_out~q ), @@ -3893,6 +4530,214 @@ defparam \I2C_SDAT~output .bus_hold = "false"; defparam \I2C_SDAT~output .open_drain_output = "true"; // synopsys translate_on +// Location: IOOBUF_X0_Y23_N16 +cycloneive_io_obuf \DRAM_DQ[0]~output ( + .i(\sdram_|Mux72~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[0]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[0]~output .bus_hold = "false"; +defparam \DRAM_DQ[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y23_N23 +cycloneive_io_obuf \DRAM_DQ[1]~output ( + .i(\sdram_|Mux3~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[1]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[1]~output .bus_hold = "false"; +defparam \DRAM_DQ[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y0_N9 +cycloneive_io_obuf \DRAM_DQ[2]~output ( + .i(\sdram_|Mux2~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[2]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[2]~output .bus_hold = "false"; +defparam \DRAM_DQ[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y7_N9 +cycloneive_io_obuf \DRAM_DQ[3]~output ( + .i(\sdram_|Mux1~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[3]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[3]~output .bus_hold = "false"; +defparam \DRAM_DQ[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y12_N2 +cycloneive_io_obuf \DRAM_DQ[4]~output ( + .i(\sdram_|Mux0~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[4]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[4]~output .bus_hold = "false"; +defparam \DRAM_DQ[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y15_N2 +cycloneive_io_obuf \DRAM_DQ[5]~output ( + .i(\sdram_|Mux73~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[5]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[5]~output .bus_hold = "false"; +defparam \DRAM_DQ[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y15_N9 +cycloneive_io_obuf \DRAM_DQ[6]~output ( + .i(\sdram_|Mux74~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[6]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[6]~output .bus_hold = "false"; +defparam \DRAM_DQ[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N16 +cycloneive_io_obuf \DRAM_DQ[7]~output ( + .i(\sdram_|Mux75~0_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[7]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[7]~output .bus_hold = "false"; +defparam \DRAM_DQ[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y0_N16 +cycloneive_io_obuf \DRAM_DQ[8]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[8]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[8]~output .bus_hold = "false"; +defparam \DRAM_DQ[8]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y0_N2 +cycloneive_io_obuf \DRAM_DQ[9]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[9]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[9]~output .bus_hold = "false"; +defparam \DRAM_DQ[9]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y0_N2 +cycloneive_io_obuf \DRAM_DQ[10]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[10]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[10]~output .bus_hold = "false"; +defparam \DRAM_DQ[10]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y0_N9 +cycloneive_io_obuf \DRAM_DQ[11]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[11]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[11]~output .bus_hold = "false"; +defparam \DRAM_DQ[11]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y0_N23 +cycloneive_io_obuf \DRAM_DQ[12]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[12]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[12]~output .bus_hold = "false"; +defparam \DRAM_DQ[12]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y0_N16 +cycloneive_io_obuf \DRAM_DQ[13]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[13]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[13]~output .bus_hold = "false"; +defparam \DRAM_DQ[13]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y0_N23 +cycloneive_io_obuf \DRAM_DQ[14]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[14]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[14]~output .bus_hold = "false"; +defparam \DRAM_DQ[14]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y12_N9 +cycloneive_io_obuf \DRAM_DQ[15]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[15]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[15]~output .bus_hold = "false"; +defparam \DRAM_DQ[15]~output .open_drain_output = "true"; +// synopsys translate_on + // Location: IOIBUF_X27_Y0_N22 cycloneive_io_ibuf \CLOCK_50~input ( .i(CLOCK_50), @@ -4024,7 +4869,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N4 +// Location: LCCOMB_X25_Y33_N0 cycloneive_lcell_comb \ula_|clocks_|counter[0]~0 ( // Equation(s): // \ula_|clocks_|counter[0]~0_combout = !\ula_|clocks_|counter [0] @@ -4041,7 +4886,7 @@ defparam \ula_|clocks_|counter[0]~0 .lut_mask = 16'h0F0F; defparam \ula_|clocks_|counter[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N5 +// Location: FF_X25_Y33_N1 dffeas \ula_|clocks_|counter[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|counter[0]~0_combout ), @@ -4070,7 +4915,7 @@ defparam \SW[2]~input .bus_hold = "false"; defparam \SW[2]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N10 +// Location: LCCOMB_X25_Y33_N4 cycloneive_lcell_comb \ula_|clocks_|clk_cpu~0 ( // Equation(s): // \ula_|clocks_|clk_cpu~0_combout = \ula_|clocks_|clk_cpu~q $ (((\SW[2]~input_o ) # (!\ula_|clocks_|counter [0]))) @@ -4087,7 +4932,7 @@ defparam \ula_|clocks_|clk_cpu~0 .lut_mask = 16'h0FC3; defparam \ula_|clocks_|clk_cpu~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N11 +// Location: FF_X25_Y33_N5 dffeas \ula_|clocks_|clk_cpu ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|clk_cpu~0_combout ), @@ -4119,40 +4964,6 @@ defparam \ula_|clocks_|clk_cpu~clkctrl .clock_type = "global clock"; defparam \ula_|clocks_|clk_cpu~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N20 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hAAA0; -defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N12 -cycloneive_lcell_comb \z80_|sequencer_|ena_M ( -// Equation(s): -// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|ena_M~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; -defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: IOIBUF_X0_Y16_N8 cycloneive_io_ibuf \KEY[1]~input ( .i(KEY[1]), @@ -4163,7 +4974,7 @@ defparam \KEY[1]~input .bus_hold = "false"; defparam \KEY[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N6 +// Location: LCCOMB_X35_Y10_N0 cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( // Equation(s): // \z80_|interrupts_|nmi_armed~feeder_combout = VCC @@ -4180,11775 +4991,6 @@ defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N2 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hAAFF; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y15_N7 -dffeas \z80_|interrupts_|nmi_armed ( - .clk(!\KEY[1]~input_o ), - .d(\z80_|interrupts_|nmi_armed~feeder_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|nmi_armed~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; -defparam \z80_|interrupts_|nmi_armed .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N12 -cycloneive_lcell_comb \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder ( -// Equation(s): -// \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout = \z80_|interrupts_|nmi_armed~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|interrupts_|nmi_armed~q ), - .cin(gnd), - .combout(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .lut_mask = 16'hFF00; -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( -// Equation(s): -// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_eval_cond~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( -// Equation(s): -// \z80_|execute_|ixy_d~4_combout = (!\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h1100; -defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N30 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N31 -dffeas \z80_|sequencer_|DFFE_M3_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M3_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( -// Equation(s): -// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hD0D0; -defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N2 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N3 -dffeas \z80_|sequencer_|DFFE_M4_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M4_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal32~0_combout = (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(gnd), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal32~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h00CC; -defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N14 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF33; -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N10 -cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( -// Equation(s): -// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instED~q ) # (\z80_|decode_state_|DFFE_instCB~q ) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|decode_state_|table_xx~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; -defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~0_combout = (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal41~2_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal36~0_combout )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|pla_decode_|Equal36~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|pla_decode_|Equal36~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hB3A0; -defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N29 -dffeas \z80_|decode_state_|DFFE_instCB ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instCB~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h0020; -defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_ed_set~combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal2~1_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N17 -dffeas \z80_|decode_state_|DFFE_instED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instED~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & \z80_|decode_state_|DFFE_instED~q )) - - .dataa(\z80_|ir_|opcode [7]), - .datab(gnd), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( -// Equation(s): -// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_im_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal49~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout )) - - .dataa(gnd), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal49~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h3000; -defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~1_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [3])) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; -defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~14_combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~8_combout = (((!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h4FFF; -defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N12 -cycloneive_lcell_comb \z80_|nM1_int~2 ( -// Equation(s): -// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|nM1_int~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|nM1_int~2 .lut_mask = 16'h0055; -defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal49~0_combout ) # ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hEF00; -defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( -// Equation(s): -// \z80_|execute_|ixy_d~7_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & -// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & \z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; -defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal39~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; -defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~2_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal3~2_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal3~2_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( -// Equation(s): -// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( -// Equation(s): -// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( -// Equation(s): -// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( -// Equation(s): -// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~8_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( -// Equation(s): -// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal44~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal44~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0002; -defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( -// Equation(s): -// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hC800; -defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( -// Equation(s): -// \z80_|execute_|ixy_d~13_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|execute_|ixy_d~16_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(gnd), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal50~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h3000; -defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h8800; -defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( -// Equation(s): -// \z80_|execute_|ixy_d~17_combout = (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|pla_decode_|Equal50~0_combout & ((!\z80_|pla_decode_|Equal33~2_combout )))) # (!\z80_|decode_state_|DFFE_inst4~q & (((!\z80_|pla_decode_|Equal50~0_combout & -// !\z80_|pla_decode_|Equal33~2_combout )) # (!\z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal50~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h0537; -defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( -// Equation(s): -// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( -// Equation(s): -// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~12_combout & (((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ixy_d~12_combout & -// (!\z80_|execute_|ixy_d~13_combout & (\z80_|execute_|ixy_d~17_combout ))) - - .dataa(\z80_|execute_|ixy_d~12_combout ), - .datab(\z80_|execute_|ixy_d~13_combout ), - .datac(\z80_|execute_|ixy_d~17_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h30BA; -defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( -// Equation(s): -// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T5_ff~q ) # ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hCC8C; -defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( -// Equation(s): -// \z80_|execute_|ixy_d~15_combout = ((\z80_|pla_decode_|Equal49~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|execute_|ixy_d~11_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) - - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|ixy_d~14_combout ), - .datad(\z80_|execute_|ixy_d~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|execute_|ixy_d~15_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T5_ff~q & -// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N23 -dffeas \z80_|decode_state_|DFFE_instIY1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_iy_set~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instIY1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q )) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(gnd), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0500; -defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~14_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~2 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~18_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~26_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~27_combout = (\z80_|pla_decode_|Equal13~2_combout & \z80_|ir_|opcode [3]) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (((!\z80_|execute_|ctl_mRead~26_combout & !\z80_|execute_|ctl_mRead~27_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_mRead~27_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h02AA; -defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h5D00; -defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~18_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal12~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal55~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0500; -defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|comb~1 ( -// Equation(s): -// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|comb~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~1 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|comb~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~17_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~18_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~17_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~9_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~10_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~8_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~20_combout = (\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h2200; -defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal25~0_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal25~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~21_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~17_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~1_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'hFDFC; -defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal32~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal29~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal41~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal34~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal37~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal35~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal38~2_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal38~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal35~0_combout ) # (\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~3_combout = (\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|pla_decode_|Equal29~0_combout ) # ((\z80_|pla_decode_|Equal24~1_combout ) # (\z80_|reg_control_|reg_sys_we_lo~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|pla_decode_|Equal24~1_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|comb~0 ( -// Equation(s): -// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|comb~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~0 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal47~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|comb~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N8 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|reg_control_|reg_sys_we_lo~3_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # -// (!\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|reg_control_|reg_sys_we_lo~3_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h153F; -defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~22_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (((!\z80_|execute_|ctl_mRead~20_combout & !\z80_|execute_|ctl_mRead~21_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~20_combout ), - .datab(\z80_|execute_|ctl_mRead~21_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~24_combout = (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~18_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_mRead~22_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h0313; -defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~16_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N16 -cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( -// Equation(s): -// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|M5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N17 -dffeas \z80_|sequencer_|M5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|M5~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|M5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|M5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~29 ( -// Equation(s): -// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & -// (((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~29 .lut_mask = 16'h0777; -defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~25_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~16_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout -// & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~17_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~17_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|setM1~29_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|setM1~29_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~7_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~1_combout = (!\z80_|decode_state_|DFFE_instED~q & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & !\z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~14_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~14 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_state_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~14_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((!\z80_|execute_|ctl_state_alu~14_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'h115F; -defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h1F3F; -defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|pla_decode_|Equal29~0_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal29~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|pla_decode_|Equal29~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; -defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (\z80_|reg_control_|reg_sel_pc~1_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~0_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h40C0; -defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( -// Equation(s): -// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|ctl_state_alu~8_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~8_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~17 .lut_mask = 16'h7000; -defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~6_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0004; -defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( -// Equation(s): -// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|execute_|ctl_mRead~18_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & -// (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~16 .lut_mask = 16'h135F; -defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|pla_decode_|Equal41~0_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal46~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [2] & \z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal46~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~17_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~6_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_flags_alu~17_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~6 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_flags_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]) - - .dataa(\z80_|ir_|opcode [6]), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0505; -defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~6_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~16_combout = (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|execute_|ctl_flags_alu~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & \z80_|execute_|ctl_reg_in_hi~3_combout )) - - .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( -// Equation(s): -// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|fMRead~17_combout & (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|fMRead~16_combout & \z80_|execute_|ctl_mWrite~8_combout ))) - - .dataa(\z80_|execute_|fMRead~17_combout ), - .datab(\z80_|execute_|ctl_sw_2d~4_combout ), - .datac(\z80_|execute_|fMRead~16_combout ), - .datad(\z80_|execute_|ctl_mWrite~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( -// Equation(s): -// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_mRead~24_combout & (\z80_|execute_|ctl_reg_in_hi~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|fMRead~18_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~24_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datad(\z80_|execute_|fMRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~36 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~36_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~36 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~9_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~9 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_op_low~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h007F; -defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~11_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h00AA; -defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal9~1_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ixy_d~6_combout & -// (((!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_mRead~11_combout ))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~4_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~7_combout & (!\z80_|execute_|ctl_ir_we~11_combout & ((!\z80_|execute_|ctl_ir_we~12_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout & (((!\z80_|execute_|ctl_ir_we~12_combout ) # -// (!\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0577; -defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~8_combout = (\z80_|execute_|ctl_alu_shift_oe~44_combout & (\z80_|execute_|ctl_sw_2d~7_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datab(\z80_|execute_|ctl_sw_2d~7_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~5_combout & (\z80_|execute_|fMRead~19_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & \z80_|execute_|ctl_sw_2d~8_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~5_combout ), - .datab(\z80_|execute_|fMRead~19_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datad(\z80_|execute_|ctl_sw_2d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (!\z80_|execute_|ctl_sw_1d~5_combout & (\z80_|execute_|ctl_sw_1d~4_combout & \z80_|execute_|ctl_sw_2d~9_combout ))) - - .dataa(\z80_|execute_|ctl_im_we~combout ), - .datab(\z80_|execute_|ctl_sw_1d~5_combout ), - .datac(\z80_|execute_|ctl_sw_1d~4_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal47~0_combout ))) # (!\z80_|execute_|ctl_sw_1d~6_combout ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7333; -defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~8_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~8 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_alu_op_low~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal2~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'h0111; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0088; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0037; -defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_zero~combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~4 ( -// Equation(s): -// \z80_|alu_|db_low[2]~4_combout = ((\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~4 .lut_mask = 16'h555D; -defparam \z80_|alu_|db_low[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_sw_4u~1_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # -// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_shift_oe~30_combout & (\z80_|execute_|ctl_alu_shift_oe~29_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal69~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal69~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~5_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [5]) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h00AA; -defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~5_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~12_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~12 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_alu_op_low~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal56~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal56~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~11_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~11 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op_low~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|nextM~2 ( -// Equation(s): -// \z80_|execute_|nextM~2_combout = (!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0011; -defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~4_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal69~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .lut_mask = 16'h0103; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~5_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hC0D0; -defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~15_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h0F3F; -defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_ir_we~7_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # -// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # -// (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~15_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~3_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ctl_ir_we~11_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h3000; -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_alu_core_R~4_combout & !\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout -// ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal48~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~18_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'hBBBF; -defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~17_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0100; -defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~18_combout = ((!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|ctl_iorw~10_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (\z80_|execute_|ctl_alu_shift_oe~18_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~19_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~13_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~13 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_alu_bs_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_alu_bs_oe~13_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~13_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal20~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal20~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal68~2_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|pla_decode_|Equal68~2_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~13 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_op_low~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~15_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_alu_op_low~13_combout & !\z80_|execute_|ctl_alu_op_low~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hBBBF; -defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_flags_bus~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~11 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .lut_mask = 16'hAFBF; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h70F0; -defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~8_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|execute_|ixy_d~10_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~9_combout = ((!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_flags_bus~8_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_flags_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_flags_bus~14_combout & (\z80_|execute_|ctl_flags_bus~11_combout & (\z80_|execute_|ctl_flags_bus~10_combout & \z80_|execute_|ctl_flags_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~14_combout ), - .datab(\z80_|execute_|ctl_flags_bus~11_combout ), - .datac(\z80_|execute_|ctl_flags_bus~10_combout ), - .datad(\z80_|execute_|ctl_flags_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_flags_xy_we~18_combout & (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout ))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datad(\z80_|execute_|ctl_flags_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & ((!\z80_|execute_|ctl_state_alu~14_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|execute_|ctl_ir_we~14_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) # -// (!\z80_|execute_|ctl_mWrite~3_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h3030; -defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h3700; -defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|pla_decode_|Equal41~2_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|execute_|ctl_bus_db_oe~0_combout & \z80_|execute_|ctl_alu_op1_sel_bus~12_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~13_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal48~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (((\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h1100; -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[2]~14_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N17 -dffeas \z80_|alu_|op1_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'h88C8; -defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~10_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~10 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op_low~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|fMWrite~11 ( -// Equation(s): -// \z80_|execute_|fMWrite~11_combout = ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~11 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|fMWrite~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~21_combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (\z80_|execute_|ctl_alu_op_low~9_combout ))) # (!\z80_|execute_|fMWrite~11_combout ) - - .dataa(\z80_|execute_|fMWrite~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~22_combout = ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~10_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~10_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~16_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h7737; -defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~17_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~16_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h2200; -defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel~36_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel~36 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & (\z80_|execute_|ctl_state_alu~8_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datab(\z80_|execute_|ctl_state_alu~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~18_combout = (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_mWrite~3_combout & -// (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~11_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~19_combout = ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|execute_|ctl_alu_op_low~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~33_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~12_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'h77F7; -defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'hF0FF; -defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~23_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_mRead~36_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|execute_|ctl_alu_op_low~22_combout ) # (((\z80_|execute_|ctl_alu_op_low~20_combout ) # (\z80_|execute_|ctl_alu_op_low~23_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ixy_d~9_combout & (((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|execute_|ixy_d~5_combout & -// (\z80_|pla_decode_|Equal40~1_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'hEAE0; -defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~34_combout = (\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFF08; -defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~combout = ((\z80_|execute_|ctl_alu_op_low~24_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~26_combout ))) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~26_combout ) # (\z80_|execute_|ctl_mRead~27_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~18_combout ) - - .dataa(\z80_|execute_|ctl_mRead~26_combout ), - .datab(\z80_|execute_|ctl_mRead~27_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hEF0F; -defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~39_combout = (\z80_|execute_|ctl_alu_shift_oe~37_combout ) # (((\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~42_combout = (\z80_|execute_|ctl_alu_shift_oe~40_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'hF200; -defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~21_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~22_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h3F20; -defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~23_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~22_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~22_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h0CEC; -defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~23_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~23_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'h32F0; -defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~25_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~24_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|ctl_alu_shift_oe~24_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h22EA; -defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~14_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~14 .lut_mask = 16'hC0C8; -defparam \z80_|execute_|ctl_alu_bs_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~26_combout = (!\z80_|execute_|ctl_alu_bs_oe~14_combout & ((\z80_|execute_|ctl_alu_shift_oe~25_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_bus_db_oe~1_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & -// (\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_bus_db_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~28_combout = ((\z80_|execute_|ctl_alu_shift_oe~27_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~20_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~44_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'hFF5F; -defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~4_combout -// & (\z80_|execute_|ctl_ir_we~10_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hEAC8; -defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|execute_|ctl_alu_bs_oe~10_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~32_combout = (!\z80_|execute_|ctl_alu_bs_oe~11_combout & ((\z80_|execute_|ctl_alu_shift_oe~28_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h00CF; -defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~32_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_alu_shift_oe~16_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout )))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hFF51; -defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|execute_|ctl_alu_op_low~11_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_state_alu~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_ir_we~7_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # -// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h3F20; -defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_ir_we~10_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~36_combout = (((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~12_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~26_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~36_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~9_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q ))) # (!\z80_|pla_decode_|Equal47~0_combout ) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~0_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hFDDD; -defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (\z80_|pla_decode_|Equal48~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h0088; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~9_combout = (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & (\z80_|execute_|ctl_flags_xy_we~8_combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h1300; -defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal8~0_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h0C00; -defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~9_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~9 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal39~0_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & -// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~1_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~1 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal11~1_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal11~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~10_combout = (\z80_|execute_|ctl_flags_alu~9_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_flags_sz_we~3_combout & !\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~9_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_alu~10_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~7_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal13~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~2 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~2_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) - - .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~2 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_pf_sel[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~2_combout = (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~25_combout = (\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_ir_we~14_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout ) # -// (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~25 .lut_mask = 16'h0377; -defparam \z80_|execute_|ctl_bus_inc_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~25_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hCC8C; -defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~10_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hCCC4; -defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'h3331; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~17_combout = (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~5_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h5557; -defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~6_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|reg_control_|reg_sys_we_lo~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'h7000; -defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & -// (((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal2~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|table_xx~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h0002; -defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|ctl_state_alu~7_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~2_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|nM1_int~2_combout & -// (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_mWrite~3_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & -// (((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h02AA; -defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & (\z80_|execute_|ctl_alu_res_oe~0_combout & !\z80_|execute_|ctl_alu_oe~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~11_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_alu_res_oe~1_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'h8C88; -defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( -// Equation(s): -// \z80_|alu_|db_high[3]~2_combout = (\z80_|execute_|ctl_alu_bs_oe~combout ) # ((\z80_|execute_|ctl_alu_op1_oe~1_combout ) # ((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFFEF; -defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( -// Equation(s): -// \z80_|alu_|db_high[3]~3_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout ) # (\z80_|alu_|db_high[3]~2_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(gnd), - .datac(\z80_|alu_|db_high[3]~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hFAFA; -defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~24 ( -// Equation(s): -// \z80_|alu_|db_low[2]~24_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[2]~3_combout & (\z80_|alu_|db_low[2]~6_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[2]~3_combout & -// \z80_|alu_|db_low[2]~6_combout )) # (!\z80_|alu_|db_high[3]~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[2]~3_combout ), - .datac(\z80_|alu_|db_low[2]~6_combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~24 .lut_mask = 16'hC0D5; -defparam \z80_|alu_|db_low[2]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~7 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~7_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~7 .lut_mask = 16'h0AAA; -defparam \z80_|reg_control_|reg_sys_we_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = ((!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|reg_control_|reg_sys_we_lo~7_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~10_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hFF57; -defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~43_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'hFF57; -defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~26_combout = (\z80_|execute_|ctl_alu_core_S~10_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & \z80_|execute_|ctl_bus_inc_oe~25_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_mWrite~9_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~9_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|execute_|ctl_alu_oe~8_combout & (\z80_|execute_|ctl_alu_oe~4_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|ctl_bus_db_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~8_combout ), - .datab(\z80_|execute_|ctl_alu_oe~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mWrite~16_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~6_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~7_combout = (\z80_|execute_|ctl_alu_oe~6_combout & (((!\z80_|execute_|ctl_mRead~27_combout & !\z80_|execute_|ctl_mRead~26_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~27_combout ), - .datac(\z80_|execute_|ctl_mRead~26_combout ), - .datad(\z80_|execute_|ctl_alu_oe~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~12_combout = (\z80_|execute_|ctl_alu_oe~11_combout ) # (((!\z80_|execute_|ctl_alu_oe~7_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_oe~5_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), - .datab(\z80_|execute_|ctl_alu_oe~5_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), - .datad(\z80_|execute_|ctl_alu_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_alu_oe~12_combout ) # (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_flags_alu~10_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~12_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~14_combout = (\z80_|execute_|ctl_alu_oe~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_oe~13_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hF5F5; -defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & -// (((!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mRead~26_combout ))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|nextM~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~53 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'h8C00; -defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~54 ( -// Equation(s): -// \z80_|execute_|setM1~54_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~54 .lut_mask = 16'hABFF; -defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~7_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((!\z80_|execute_|ctl_alu_oe~3_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout )) # -// (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_alu_oe~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|setM1~54_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_sw_2u~4_combout )) - - .dataa(\z80_|execute_|setM1~54_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~1_combout ), - .datad(\z80_|execute_|ctl_sw_2u~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_reg_gp_sel~36_combout & (\z80_|execute_|comb~0_combout $ ((!\z80_|ir_|opcode [0])))) # (!\z80_|execute_|ctl_reg_gp_sel~36_combout & (!\z80_|execute_|ctl_sw_2u~5_combout & -// (\z80_|execute_|comb~0_combout $ (!\z80_|ir_|opcode [0])))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'h82C3; -defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~35_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (\z80_|execute_|ctl_inc_cy~35_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_inc_cy~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hBF00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~6_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & -// (((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~2_combout & (\z80_|execute_|ctl_sw_2u~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|execute_|ctl_mRead~8_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(\z80_|execute_|ctl_sw_2u~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~10_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_op_low~13_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|rsel3 ( -// Equation(s): -// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|rsel3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel3 .lut_mask = 16'h7878; -defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & -// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7707; -defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~6_combout = (!\z80_|execute_|ctl_sw_2u~6_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout & \z80_|execute_|ctl_reg_out_hi~5_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2u~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~7_combout = ((\z80_|execute_|ctl_reg_out_hi~8_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|rsel0 ( -// Equation(s): -// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|rsel0~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel0 .lut_mask = 16'h5AAA; -defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .lut_mask = 16'h0444; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h7030; -defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~11_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~11_combout )) # (!\z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~14_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal77~0_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h0D0F; -defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_1d~8_combout ) # (!\z80_|execute_|ctl_sw_2d~14_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2d~10_combout ), - .datab(\z80_|execute_|ctl_sw_2d~14_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hBFAA; -defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # (\z80_|execute_|ctl_alu_shift_oe~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFEAA; -defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~11_combout ) # ((\z80_|execute_|ctl_sw_2d~12_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~11_combout ), - .datac(\z80_|execute_|ctl_sw_2d~12_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~34_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_alu_oe~2_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_inc_cy~34_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~75_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|pla_decode_|Equal38~2_combout & ((!\z80_|pla_decode_|Equal37~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|pla_decode_|Equal38~2_combout -// & !\z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|pla_decode_|Equal38~2_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal37~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~75_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal29~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal4~0_combout = (\z80_|execute_|comb~1_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|execute_|comb~1_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~48_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~46_combout = (\z80_|execute_|ctl_bus_inc_oe~48_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|pla_decode_|Equal4~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & ((!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & -// !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~92 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~92_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~92 .lut_mask = 16'h5F7F; -defparam \z80_|execute_|ctl_inc_cy~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~1 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal19~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~38_combout = (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal3~1_combout )) # (!\z80_|pla_decode_|Equal19~1_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal19~1_combout ), - .datac(\z80_|execute_|ctl_sw_4u~0_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~93 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~93_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~93 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~39_combout = (\z80_|execute_|ctl_inc_cy~93_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_inc_cy~93_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~24_combout = (\z80_|execute_|ctl_inc_cy~92_combout & (\z80_|execute_|ctl_inc_cy~38_combout & \z80_|execute_|ctl_inc_cy~39_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~92_combout ), - .datac(\z80_|execute_|ctl_inc_cy~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~24 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_bus_inc_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~1_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (\z80_|execute_|ctl_bus_inc_oe~46_combout & (\z80_|execute_|ctl_inc_cy~53_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~53_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~1 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~44_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'h1333; -defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~0_combout = (\z80_|execute_|ctl_bus_inc_oe~44_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & ((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~0 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_reg_gp_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (\z80_|execute_|ctl_reg_gp_we~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout & -// (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h3F15; -defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_sw_4u~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datad(\z80_|execute_|ctl_sw_4u~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( -// Equation(s): -// \z80_|execute_|fMRead~3_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|execute_|ctl_state_alu~14_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) # -// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_mRead~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h135F; -defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~15_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~12_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_sw_4u~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & -// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~94 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~94_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~94_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~94 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~87_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) - - .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~94_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~16_combout = (\z80_|execute_|fMRead~3_combout & (\z80_|execute_|ctl_reg_sel_wz~15_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ))) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~6_combout = ((\z80_|execute_|ctl_sw_4u~5_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout ))) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|execute_|ctl_sw_4u~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~6_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal1~5_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N22 -cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( -// Equation(s): -// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal1~6_combout & \z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal1~6_combout ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_exx~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N23 -dffeas \z80_|reg_control_|bank_exx ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_exx~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_exx~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_exx .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N26 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de1~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hF0D2; -defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N27 -dffeas \z80_|reg_control_|bank_hl_de1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal2~1_combout & \z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal2~1_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hC888; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h00FE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~12_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~13_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal50~0_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hEEEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( -// Equation(s): -// \z80_|execute_|fMWrite~3_combout = (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h0001; -defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [2]) # ((\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFAF; -defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( -// Equation(s): -// \z80_|execute_|fMRead~2_combout = (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_flags_bus~5_combout )) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~14_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMRead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h1010; -defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~19_combout = (\z80_|execute_|fMWrite~3_combout & (\z80_|execute_|fMRead~2_combout & !\z80_|execute_|ctl_ir_we~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|fMWrite~3_combout ), - .datac(\z80_|execute_|fMRead~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'h00C0; -defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [2] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h50F0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~14_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hC5CD; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~15_combout )))) # (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout & ((\z80_|execute_|ctl_ir_we~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_ir_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hCAC0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'h0050; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~47_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q ))) # (!\z80_|execute_|ctl_mRead~8_combout ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'hFF37; -defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|ctl_reg_use_sp~2_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_bus_inc_oe~47_combout & \z80_|execute_|nextM~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal6~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0050; -defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~21_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~5_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_sw_1d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & -// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'hAB00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~20_combout = (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mRead~14_combout & !\z80_|pla_decode_|Equal49~0_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .lut_mask = 16'h0101; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~22_combout = (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~21_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & ((\z80_|sequencer_|M5~q ) # (\z80_|sequencer_|DFFE_M4_ff~q )))) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|decode_state_|DFFE_instED~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'h0032; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout & \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~36_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h20AA; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|pla_decode_|Equal20~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h0505; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~14_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~14 .lut_mask = 16'hF0FF; -defparam \z80_|execute_|ctl_flags_hf_cpl~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (!\z80_|pla_decode_|Equal68~2_combout & (!\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_flags_hf_cpl~14_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|pla_decode_|Equal68~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~47 ( -// Equation(s): -// \z80_|execute_|setM1~47_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0015; -defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~48 ( -// Equation(s): -// \z80_|execute_|setM1~48_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|execute_|ctl_flags_hf_cpl~10_combout & (\z80_|execute_|setM1~47_combout & \z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .datac(\z80_|execute_|setM1~47_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~48 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~13_combout = (\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_iorw~10_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_flags_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~48_combout )))) - - .dataa(\z80_|execute_|setM1~48_combout ), - .datab(\z80_|execute_|ctl_flags_oe~1_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h0070; -defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~28_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & !\z80_|execute_|ctl_reg_in_hi~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~40_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~40_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~40_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~12_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~43_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~12_combout & (\z80_|execute_|ctl_inc_cy~43_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_inc_cy~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( -// Equation(s): -// \z80_|execute_|fMRead~6_combout = (\z80_|pla_decode_|Equal29~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ixy_d~7_combout ))) # (!\z80_|pla_decode_|Equal29~0_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & -// !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal29~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h0357; -defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( -// Equation(s): -// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & -// !\z80_|execute_|ctl_mRead~16_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h111F; -defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( -// Equation(s): -// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|fMRead~7_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|fMRead~7_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h10F0; -defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .datac(\z80_|execute_|fMRead~6_combout ), - .datad(\z80_|execute_|fMRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~13_combout = (\z80_|execute_|ctl_state_alu~8_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal52~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~8_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~10_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'h3331; -defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) # -// (!\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~9_combout = (\z80_|execute_|ctl_state_alu~14_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|execute_|ctl_state_alu~14_combout & (\z80_|pla_decode_|Equal52~1_combout & -// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'hF3A2; -defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~13_combout ), - .datab(\z80_|execute_|ctl_state_alu~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~9_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hFD00; -defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~4_combout = (((\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal62~2_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = ((!\z80_|execute_|ctl_mRead~4_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h373F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~13_combout ), - .datab(\z80_|execute_|ctl_state_alu~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~9_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h00FD; -defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~3 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~3_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal64~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal64~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~3 .lut_mask = 16'hEEFF; -defparam \z80_|execute_|ctl_pf_sel[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_flags_pf_we~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & (\z80_|execute_|ctl_alu_oe~7_combout & \z80_|execute_|ctl_pf_sel[0]~3_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .datac(\z80_|execute_|ctl_alu_oe~7_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_state_alu~14_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~15 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_state_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [4] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (\z80_|execute_|ctl_state_alu~15_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )) - - .dataa(\z80_|execute_|ctl_state_alu~15_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h00A0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~29_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ) # (((\z80_|execute_|ctl_reg_gp_sel[1]~23_combout & \z80_|ir_|opcode [5])) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal11~0_combout & -// ((\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mRead~5_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((\z80_|ir_|opcode [1] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(\z80_|execute_|ctl_sw_2u~5_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hFF70; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~20_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hF7F7; -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ctl_reg_sys_hilo~20_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h22A2; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N18 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0010; -defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h0F0B; -defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h00E4; -defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; -defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N15 -dffeas \z80_|reg_control_|bank_hl_de2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de2~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))))) - - .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hAC00; -defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & (((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~4_combout = (!\z80_|execute_|ctl_reg_in_hi~7_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & \z80_|execute_|ctl_state_alu~15_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_state_alu~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'h1100; -defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout & ((!\z80_|execute_|ctl_iorw~10_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datac(\z80_|execute_|ctl_iorw~10_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h004C; -defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout -// )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|pla_decode_|Equal25~0_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .lut_mask = 16'hA200; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout & !\z80_|execute_|ctl_sw_1d~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), - .datad(\z80_|execute_|ctl_sw_1d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & \z80_|execute_|ctl_reg_gp_we~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~6_combout = (((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_reg_gp_we~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .datab(\z80_|execute_|ctl_sw_4u~3_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~7_combout & (((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h00F7; -defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_flags_oe~1_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h1033; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_al_we~14_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFBF0; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = (\z80_|execute_|rsel3~combout & (((!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'h40CC; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (((\z80_|execute_|ctl_ir_we~7_combout ) # (\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo~20_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_iorw~11_combout ) # ((\z80_|execute_|ctl_state_alu~14_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout )))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~25_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ) # -// (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hF5FF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|execute_|rsel0~combout & ((\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & -// (((\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )) # (!\z80_|execute_|setM1~48_combout ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'hCD05; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~6_combout & (!\z80_|execute_|ixy_d~9_combout ))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|pla_decode_|Equal10~0_combout )) # -// (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h1357; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal2~1_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~40 ( -// Equation(s): -// \z80_|execute_|setM1~40_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal8~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~40 .lut_mask = 16'h1155; -defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & ((\z80_|execute_|setM1~40_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h1101; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~93 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~93_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & ((\z80_|reg_control_|reg_sel_hl~0_combout ) # (\z80_|reg_control_|reg_sel_hl2~0_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .lut_mask = 16'h0E00; -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h00D8; -defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h0F00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout -// & (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~10_combout = (\z80_|execute_|ctl_reg_in_hi~9_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_gp_we~5_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~19_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_mRead~22_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~8_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # (\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h00B0; -defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFECC; -defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~3_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout )) - - .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & !\z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N20 -cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( -// Equation(s): -// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|pla_decode_|Equal21~2_combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y12_N21 -dffeas \z80_|reg_control_|bank_af ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_af~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_af~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_af .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (!\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h1000; -defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; -defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h2200; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal19~0_combout & ((!\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout ) # -// (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'h035F; -defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal33~0_combout )) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hF8F8; -defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~7_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~6_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_bus~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( -// Equation(s): -// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~24 .lut_mask = 16'h0777; -defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~13_combout = (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datad(\z80_|execute_|ctl_flags_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~combout = (\z80_|execute_|ctl_flags_bus~7_combout ) # (((\z80_|execute_|ctl_flags_hf2_we~combout ) # (!\z80_|execute_|ctl_flags_bus~13_combout )) # (!\z80_|execute_|fMRead~24_combout )) - - .dataa(\z80_|execute_|ctl_flags_bus~7_combout ), - .datab(\z80_|execute_|fMRead~24_combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mWrite~2_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h3777; -defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_dec~3_combout & (!\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|fMRead~3_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|fMRead~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h7757; -defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h04CC; -defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|execute_|ixy_d~16_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & -// (((!\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|execute_|ixy_d~16_combout ))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|execute_|ixy_d~16_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h557F; -defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~3_combout & (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & \z80_|execute_|ctl_reg_sel_pc~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & -// (((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'h88F8; -defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~8_combout ) # (\z80_|execute_|ctl_mRead~17_combout )))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_reg_sel_pc~10_combout & (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .datab(\z80_|execute_|ctl_inc_cy~94_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout & -// !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~29_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|ir_|opcode [5]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~14_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h5455; -defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~49 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~49_combout = (!\z80_|pla_decode_|Equal35~0_combout & (((\z80_|ir_|opcode [3]) # (\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal24~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~49 .lut_mask = 16'h00FD; -defparam \z80_|execute_|pc_inc_hold~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_mRead~15_combout & (!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout )) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0A00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~28_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal33~2_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal50~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'h0515; -defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~35 ( -// Equation(s): -// \z80_|execute_|setM1~35_combout = (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~35 .lut_mask = 16'h0003; -defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~36 ( -// Equation(s): -// \z80_|execute_|setM1~36_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|execute_|ctl_mRead~9_combout & (\z80_|execute_|pc_inc_hold~28_combout & \z80_|execute_|setM1~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~28_combout ), - .datad(\z80_|execute_|setM1~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~36 .lut_mask = 16'h2000; -defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( -// Equation(s): -// \z80_|execute_|fMRead~5_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|setM1~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|setM1~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0100; -defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & (((\z80_|execute_|ctl_bus_inc_oe~29_combout & \z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'hA222; -defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'hC8C8; -defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~1_combout = (\z80_|execute_|pc_inc_hold~29_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(gnd), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'hEE00; -defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~2_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'h1113; -defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|pc_inc_hold~49_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|pc_inc_hold~49_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hF0B0; -defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~3_combout = (((\z80_|execute_|ctl_reg_sys_we~0_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout )) # (!\z80_|execute_|ctl_reg_sys_we~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~3 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_sys_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~2_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~3_combout = (\z80_|execute_|ctl_reg_sys_we_lo~2_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_reg_sys_we_lo~3_combout & \z80_|sequencer_|DFFE_M2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|execute_|ctl_reg_sys_we~3_combout ) # ((\z80_|execute_|ctl_reg_sys_we_lo~4_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~7_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hEFFF; -defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h3330; -defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_flags_bus~4_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_flags_bus~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hFF5D; -defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~34_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_inc_cy~34_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal48~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal48~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hF2F0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = (((\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'hBF3F; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_alu_oe~4_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) - - .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_alu_oe~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~4_combout = ((!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|pla_decode_|Equal3~1_combout ) # (!\z80_|pla_decode_|Equal19~1_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal19~1_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~4 .lut_mask = 16'h5777; -defparam \z80_|execute_|ctl_reg_sel_wz~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~5_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~5 .lut_mask = 16'h001F; -defparam \z80_|execute_|ctl_reg_sel_wz~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~6_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & \z80_|execute_|ctl_reg_sel_wz~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_in_hi~4_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & \z80_|execute_|ctl_reg_sel_wz~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~16_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~14_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .lut_mask = 16'h80C0; -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~16_combout & (((!\z80_|execute_|ctl_mRead~36_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'hE0F0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_al_we~13_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'h80AA; -defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|ctl_reg_sel_pc~12_combout & (\z80_|execute_|setM1~52_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ctl_mRead~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ixy_d~16_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h2022; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~0 ( -// Equation(s): -// \z80_|execute_|fMRead~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMRead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~0 .lut_mask = 16'h5D5D; -defparam \z80_|execute_|fMRead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal52~1_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h0030; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|fMRead~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h050F; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~4_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h0FAF; -defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_reg_sys_hilo~20_combout & ((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) # -// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datac(\z80_|execute_|ctl_inc_dec~4_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hD0DD; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~9_combout = (!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_ir_we~14_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_M2_ff~q )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout -// )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00C4; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~49_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h08CC; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~17_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h4455; -defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h5554; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & ((\z80_|execute_|fMRead~0_combout ) # ((!\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|pc_inc_hold~28_combout )))) - - .dataa(\z80_|execute_|fMRead~0_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h00BA; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_al_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h4404; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~18_combout = (\z80_|alu_control_|flags_cond_true~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~38_combout = ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~38_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_state_alu~14_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal6~1_combout & ((!\z80_|pla_decode_|Equal33~2_combout ) # (!\z80_|decode_state_|use_ixiy~combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~45_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~1 ( -// Equation(s): -// \z80_|execute_|fMRead~1_combout = ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~1 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|fMRead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|fMRead~1_combout ))) - - .dataa(\z80_|execute_|fMRead~1_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hF0D0; -defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~27_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_bus_inc_oe~47_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_bus_inc_oe~27_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~28_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~46_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_bus_inc_oe~45_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~37_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~39_combout & \z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~35_combout = ((\z80_|execute_|ctl_alu_oe~2_combout & ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout ) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~77_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_sw_4u~0_combout ), - .datac(\z80_|execute_|ctl_inc_cy~76_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ixy_d~9_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|pla_decode_|Equal10~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # -// (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|ctl_mWrite~2_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~33_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (\z80_|execute_|ctl_bus_inc_oe~32_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~34_combout = (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~53_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), - .datab(\z80_|execute_|ctl_inc_cy~77_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_bus_inc_oe~40_combout ) # (((\z80_|execute_|ctl_bus_inc_oe~35_combout ) # (\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~10_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # ((!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & -// (((!\z80_|execute_|ctl_alu_oe~2_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'hA0F3; -defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & \z80_|execute_|ctl_reg_sel_wz~10_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout )) - - .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ixy_d~6_combout & -// ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h2A3F; -defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|fMRead~6_combout ), - .datad(\z80_|execute_|fMRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_reg_sel_wz~11_combout & (\z80_|execute_|ctl_sw_4d~3_combout & (\z80_|execute_|ctl_sw_4d~4_combout & \z80_|execute_|ctl_sw_4d~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .datab(\z80_|execute_|ctl_sw_4d~3_combout ), - .datac(\z80_|execute_|ctl_sw_4d~4_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~45 ( -// Equation(s): -// \z80_|execute_|setM1~45_combout = (!\z80_|execute_|ctl_iorw~11_combout & (\z80_|execute_|ctl_mRead~19_combout & (!\z80_|execute_|ctl_mRead~13_combout & !\z80_|execute_|ctl_iorw~10_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_mRead~19_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0004; -defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~46 ( -// Equation(s): -// \z80_|execute_|setM1~46_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|setM1~45_combout & !\z80_|execute_|ctl_mWrite~6_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_al_we~13_combout ), - .datac(\z80_|execute_|setM1~45_combout ), - .datad(\z80_|execute_|ctl_mWrite~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~46 .lut_mask = 16'h00C0; -defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~1_combout = ((!\z80_|decode_state_|use_ixiy~combout & ((\z80_|pla_decode_|Equal50~0_combout ) # (\z80_|pla_decode_|Equal49~0_combout )))) # (!\z80_|execute_|setM1~46_combout ) - - .dataa(\z80_|pla_decode_|Equal50~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|execute_|setM1~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'h32FF; -defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_al_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_al_we~14_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~6_combout = ((\z80_|execute_|ctl_sw_4d~0_combout ) # ((\z80_|execute_|ctl_sw_4d~1_combout & \z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_sw_4d~5_combout ) - - .dataa(\z80_|execute_|ctl_sw_4d~5_combout ), - .datab(\z80_|execute_|ctl_sw_4d~1_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_sw_4d~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( -// Equation(s): -// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~4_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0A00; -defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|fMRead~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h5DFF; -defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal21~1_combout & (((\z80_|decode_state_|table_xx~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h00DF; -defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~20_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~20 .lut_mask = 16'h5010; -defparam \z80_|execute_|ctl_reg_sel_pc~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|setM1~36_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .datab(\z80_|execute_|setM1~36_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .datad(\z80_|execute_|fMRead~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hF0F7; -defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~17_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~18_combout = (((!\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'h4FFF; -defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~19_combout = ((\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (\z80_|execute_|ctl_reg_sel_pc~18_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & \z80_|execute_|ctl_reg_sel_wz~4_combout ))) - - .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h0800; -defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N18 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~combout = (!\z80_|execute_|ctl_reg_sel_wz~18_combout & (\z80_|execute_|ctl_reg_sel_pc~19_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|reg_control_|reg_sel_pc~3_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0400; -defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # ((\z80_|execute_|ctl_sw_4d~6_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|execute_|ctl_sw_4d~6_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[7]~92_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N25 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N26 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0F0F; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N27 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N9 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N29 -dffeas \z80_|resets_|DFFE_intr_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - // Location: IOIBUF_X53_Y14_N1 cycloneive_io_ibuf \KEY[0]~input ( .i(KEY[0]), @@ -15959,7 +5001,7 @@ defparam \KEY[0]~input .bus_hold = "false"; defparam \KEY[0]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X52_Y14_N4 +// Location: LCCOMB_X52_Y14_N12 cycloneive_lcell_comb reset( // Equation(s): // \reset~combout = (!\KEY[0]~input_o ) # (!\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ) @@ -15976,7 +5018,7 @@ defparam reset.lut_mask = 16'h0FFF; defparam reset.sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y13_N26 +// Location: LCCOMB_X52_Y14_N18 cycloneive_lcell_comb \z80_|resets_|x1~0 ( // Equation(s): // \z80_|resets_|x1~0_combout = !\reset~combout @@ -15993,7 +5035,7 @@ defparam \z80_|resets_|x1~0 .lut_mask = 16'h00FF; defparam \z80_|resets_|x1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N0 +// Location: LCCOMB_X26_Y32_N8 cycloneive_lcell_comb \z80_|fpga_reset~feeder ( // Equation(s): // \z80_|fpga_reset~feeder_combout = VCC @@ -16010,7 +5052,7 @@ defparam \z80_|fpga_reset~feeder .lut_mask = 16'hFFFF; defparam \z80_|fpga_reset~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N1 +// Location: FF_X26_Y32_N9 dffeas \z80_|fpga_reset ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|fpga_reset~feeder_combout ), @@ -16029,7 +5071,7 @@ defparam \z80_|fpga_reset .is_wysiwyg = "true"; defparam \z80_|fpga_reset .power_up = "low"; // synopsys translate_on -// Location: CLKCTRL_G12 +// Location: CLKCTRL_G10 cycloneive_clkctrl \z80_|fpga_reset~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\z80_|fpga_reset~q }), @@ -16042,7 +5084,7 @@ defparam \z80_|fpga_reset~clkctrl .clock_type = "global clock"; defparam \z80_|fpga_reset~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X35_Y13_N27 +// Location: FF_X52_Y14_N19 dffeas \z80_|resets_|x1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|resets_|x1~0_combout ), @@ -16061,1677 +5103,106 @@ defparam \z80_|resets_|x1 .is_wysiwyg = "true"; defparam \z80_|resets_|x1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y17_N18 -cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( +// Location: LCCOMB_X31_Y14_N0 +cycloneive_lcell_comb \z80_|resets_|x3 ( // Equation(s): -// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # -// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) +// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|resets_|clrpc_int~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), .datad(\z80_|resets_|x1~q ), .cin(gnd), - .combout(\z80_|resets_|clrpc_int~0_combout ), + .combout(\z80_|resets_|x3~combout ), .cout()); // synopsys translate_off -defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; -defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; +defparam \z80_|resets_|x3 .lut_mask = 16'hFF50; +defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y17_N19 -dffeas \z80_|resets_|clrpc_int ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|clrpc_int~0_combout ), +// Location: FF_X31_Y14_N1 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|x3~combout ), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(\z80_|fpga_reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|resets_|clrpc_int~q ), + .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; -defparam \z80_|resets_|clrpc_int .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N28 -cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( -// Equation(s): -// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_10~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|clrpc_int~q ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .datac(\z80_|resets_|DFFE_intr_ff3~q ), - .datad(\z80_|resets_|clrpc_int~q ), - .cin(gnd), - .combout(\z80_|resets_|clrpc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; -defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( -// Equation(s): -// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [7]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h5550; -defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )) # (!\z80_|execute_|ctl_al_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|execute_|ctl_al_we~14_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & (\z80_|execute_|ctl_ir_we~4_combout & -// ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_al_we~13_combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'h0EEE; -defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~8_combout = ((\z80_|execute_|ctl_al_we~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_al_we~7_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~9_combout = (((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout )) # (!\z80_|execute_|ctl_al_we~4_combout )) # (!\z80_|execute_|ctl_alu_oe~10_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~10_combout ), - .datab(\z80_|execute_|ctl_al_we~4_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~8_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_al_we~9_combout ) # (!\z80_|execute_|setM1~45_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~8_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|setM1~45_combout ), - .datad(\z80_|execute_|ctl_al_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEEAE; -defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~10_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) - - .dataa(\z80_|execute_|ctl_al_we~6_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_4d~5_combout ), - .datad(\z80_|execute_|ctl_al_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFFAF; -defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~12_combout = (\z80_|execute_|ctl_al_we~11_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|setM1~52_combout )) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_al_we~11_combout ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N5 -dffeas \z80_|address_latch_|Q[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [7]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~6_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( -// Equation(s): -// \z80_|execute_|fIOWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h3373; -defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~4_combout & (((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|fIOWrite~0_combout )) # (!\z80_|execute_|ctl_inc_dec~4_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~4_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~9_combout = ((\z80_|execute_|ctl_inc_dec~8_combout ) # ((!\z80_|execute_|ctl_reg_gp_we~0_combout & \z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_inc_dec~3_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_inc_dec~3_combout ), - .datad(\z80_|execute_|ctl_inc_dec~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hFF4F; -defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|execute_|ctl_inc_dec~9_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hF3F3; -defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout ) - - .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h55FF; -defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N1 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N3 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hCA00; -defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h1000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|gdfx_temp0[2]~36_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hA2A2; -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|alu_control_|db[2]~29_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|alu_control_|db[2]~29_combout & -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) - - .dataa(\z80_|alu_control_|db[2]~29_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .datac(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'h8CAF; -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_iy~2_combout = (\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0020; -defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|reg_control_|reg_sel_iy~2_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N15 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~42_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N29 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~37_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & \z80_|reg_file_|gdfx_temp0[2]~35_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~40_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~42_combout = ((\z80_|reg_file_|gdfx_temp0[2]~41_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[2]~42_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .datad(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|gdfx_temp0[0]~10_combout & (\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .datab(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'h8088; -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder ( +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( // Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout +// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .sum_lutc_input = "datac"; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hFF0F; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), +// Location: FF_X35_Y10_N1 +dffeas \z80_|interrupts_|nmi_armed ( + .clk(!\KEY[1]~input_o ), + .d(\z80_|interrupts_|nmi_armed~feeder_combout ), .asdata(vcc), - .clrn(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .q(\z80_|interrupts_|nmi_armed~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; +defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; +defparam \z80_|interrupts_|nmi_armed .power_up = "low"; // synopsys translate_on -// Location: FF_X29_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), +// Location: CLKCTRL_G7 +cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), + .clkselect(2'b00), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .prn(vcc)); + .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X29_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( +// Location: LCCOMB_X32_Y12_N30 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~15_combout & (\z80_|reg_file_|gdfx_temp0[0]~14_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .datad(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hA200; -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[0]~12_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .datad(\z80_|alu_control_|db[0]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N7 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~11_combout & (\z80_|reg_file_|gdfx_temp0[0]~16_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & \z80_|reg_file_|gdfx_temp0[0]~13_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hC4FF; -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|reg_file_|gdfx_temp0[0]~22_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) +// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) .dataa(gnd), - .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hCF00; -defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~72_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF33; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; // synopsys translate_on // Location: CLKCTRL_G18 @@ -17747,158 +5218,33 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add0~14 ( -// Equation(s): -// \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) -// \ula_|video_|Add0~15 = CARRY((!\ula_|video_|Add0~13 ) # (!\ula_|video_|vga_hc [7])) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~13 ), - .combout(\ula_|video_|Add0~14_combout ), - .cout(\ula_|video_|Add0~15 )); -// synopsys translate_off -defparam \ula_|video_|Add0~14 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Add0~16 ( -// Equation(s): -// \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) -// \ula_|video_|Add0~17 = CARRY((\ula_|video_|vga_hc [8] & !\ula_|video_|Add0~15 )) - - .dataa(\ula_|video_|vga_hc [8]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~15 ), - .combout(\ula_|video_|Add0~16_combout ), - .cout(\ula_|video_|Add0~17 )); -// synopsys translate_off -defparam \ula_|video_|Add0~16 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N26 -cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( -// Equation(s): -// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Equal1~0_combout ), - .datad(\ula_|video_|Add0~16_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hF000; -defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y33_N27 -dffeas \ula_|video_|vga_hc[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N20 -cycloneive_lcell_comb \ula_|video_|Add0~18 ( -// Equation(s): -// \ula_|video_|Add0~18_combout = \ula_|video_|Add0~17 $ (\ula_|video_|vga_hc [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [9]), - .cin(\ula_|video_|Add0~17 ), - .combout(\ula_|video_|Add0~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add0~18 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( -// Equation(s): -// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~18_combout ) - - .dataa(gnd), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(gnd), - .datad(\ula_|video_|Add0~18_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hCC00; -defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y33_N21 -dffeas \ula_|video_|vga_hc[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N2 +// Location: LCCOMB_X29_Y30_N8 cycloneive_lcell_comb \ula_|video_|Add0~0 ( // Equation(s): // \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) // \ula_|video_|Add0~1 = CARRY(\ula_|video_|vga_hc [0]) - .dataa(gnd), - .datab(\ula_|video_|vga_hc [0]), + .dataa(\ula_|video_|vga_hc [0]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(gnd), .combout(\ula_|video_|Add0~0_combout ), .cout(\ula_|video_|Add0~1 )); // synopsys translate_off -defparam \ula_|video_|Add0~0 .lut_mask = 16'h33CC; +defparam \ula_|video_|Add0~0 .lut_mask = 16'h55AA; defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N0 +// Location: LCCOMB_X29_Y29_N14 cycloneive_lcell_comb \ula_|video_|vga_hc~3 ( // Equation(s): -// \ula_|video_|vga_hc~3_combout = (\ula_|video_|Add0~0_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~3_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~0_combout ) .dataa(gnd), .datab(gnd), - .datac(\ula_|video_|Add0~0_combout ), - .datad(\ula_|video_|Equal1~0_combout ), + .datac(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~0_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~3_combout ), .cout()); @@ -17907,7 +5253,7 @@ defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hF000; defparam \ula_|video_|vga_hc~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y31_N1 +// Location: FF_X29_Y29_N15 dffeas \ula_|video_|vga_hc[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_hc~3_combout ), @@ -17926,7 +5272,7 @@ defparam \ula_|video_|vga_hc[0] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N4 +// Location: LCCOMB_X29_Y30_N10 cycloneive_lcell_comb \ula_|video_|Add0~2 ( // Equation(s): // \ula_|video_|Add0~2_combout = (\ula_|video_|vga_hc [1] & (!\ula_|video_|Add0~1 )) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|Add0~1 ) # (GND))) @@ -17944,7 +5290,7 @@ defparam \ula_|video_|Add0~2 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N16 +// Location: LCCOMB_X30_Y30_N22 cycloneive_lcell_comb \ula_|video_|vga_hc[1]~feeder ( // Equation(s): // \ula_|video_|vga_hc[1]~feeder_combout = \ula_|video_|Add0~2_combout @@ -17961,7 +5307,7 @@ defparam \ula_|video_|vga_hc[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|vga_hc[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N17 +// Location: FF_X30_Y30_N23 dffeas \ula_|video_|vga_hc[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_hc[1]~feeder_combout ), @@ -17980,7 +5326,7 @@ defparam \ula_|video_|vga_hc[1] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N6 +// Location: LCCOMB_X29_Y30_N12 cycloneive_lcell_comb \ula_|video_|Add0~4 ( // Equation(s): // \ula_|video_|Add0~4_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add0~3 $ (GND))) # (!\ula_|video_|vga_hc [2] & (!\ula_|video_|Add0~3 & VCC)) @@ -17998,7 +5344,7 @@ defparam \ula_|video_|Add0~4 .lut_mask = 16'hC30C; defparam \ula_|video_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X39_Y33_N23 +// Location: FF_X29_Y30_N31 dffeas \ula_|video_|vga_hc[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -18017,50 +5363,33 @@ defparam \ula_|video_|vga_hc[2] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N8 +// Location: LCCOMB_X29_Y30_N14 cycloneive_lcell_comb \ula_|video_|Add0~6 ( // Equation(s): // \ula_|video_|Add0~6_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|Add0~5 )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Add0~5 ) # (GND))) // \ula_|video_|Add0~7 = CARRY((!\ula_|video_|Add0~5 ) # (!\ula_|video_|vga_hc [3])) - .dataa(gnd), - .datab(\ula_|video_|vga_hc [3]), + .dataa(\ula_|video_|vga_hc [3]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~5 ), .combout(\ula_|video_|Add0~6_combout ), .cout(\ula_|video_|Add0~7 )); // synopsys translate_off -defparam \ula_|video_|Add0~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add0~6 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N8 -cycloneive_lcell_comb \ula_|video_|vga_hc[3]~feeder ( -// Equation(s): -// \ula_|video_|vga_hc[3]~feeder_combout = \ula_|video_|Add0~6_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Add0~6_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vga_hc[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y33_N9 +// Location: FF_X30_Y30_N11 dffeas \ula_|video_|vga_hc[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc[3]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|Add0~6_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18071,7 +5400,7 @@ defparam \ula_|video_|vga_hc[3] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N10 +// Location: LCCOMB_X29_Y30_N16 cycloneive_lcell_comb \ula_|video_|Add0~8 ( // Equation(s): // \ula_|video_|Add0~8_combout = (\ula_|video_|vga_hc [4] & (\ula_|video_|Add0~7 $ (GND))) # (!\ula_|video_|vga_hc [4] & (!\ula_|video_|Add0~7 & VCC)) @@ -18089,7 +5418,7 @@ defparam \ula_|video_|Add0~8 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X39_Y33_N31 +// Location: FF_X29_Y30_N7 dffeas \ula_|video_|vga_hc[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -18108,101 +5437,50 @@ defparam \ula_|video_|vga_hc[4] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N18 -cycloneive_lcell_comb \ula_|video_|Equal0~0 ( -// Equation(s): -// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N30 -cycloneive_lcell_comb \ula_|video_|Equal0~1 ( -// Equation(s): -// \ula_|video_|Equal0~1_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [7] & (!\ula_|video_|vga_hc [4] & \ula_|video_|Equal0~0_combout ))) - - .dataa(\ula_|video_|vga_hc [5]), - .datab(\ula_|video_|vga_hc [7]), - .datac(\ula_|video_|vga_hc [4]), - .datad(\ula_|video_|Equal0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0200; -defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Equal1~0 ( -// Equation(s): -// \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|Equal0~1_combout )) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9]) - - .dataa(\ula_|video_|vga_hc [9]), - .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal1~0 .lut_mask = 16'hF7FF; -defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N12 +// Location: LCCOMB_X29_Y30_N18 cycloneive_lcell_comb \ula_|video_|Add0~10 ( // Equation(s): // \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) // \ula_|video_|Add0~11 = CARRY((!\ula_|video_|Add0~9 ) # (!\ula_|video_|vga_hc [5])) - .dataa(\ula_|video_|vga_hc [5]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [5]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~9 ), .combout(\ula_|video_|Add0~10_combout ), .cout(\ula_|video_|Add0~11 )); // synopsys translate_off -defparam \ula_|video_|Add0~10 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add0~10 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N0 +// Location: LCCOMB_X29_Y30_N30 cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( // Equation(s): -// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~10_combout ) +// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Add0~10_combout & \ula_|video_|Equal1~0_combout ) .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Equal1~0_combout ), - .datad(\ula_|video_|Add0~10_combout ), + .datab(\ula_|video_|Add0~10_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hF000; +defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hCC00; defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y33_N1 +// Location: FF_X29_Y30_N1 dffeas \ula_|video_|vga_hc[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~0_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|vga_hc~0_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18213,25 +5491,25 @@ defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N14 +// Location: LCCOMB_X29_Y30_N20 cycloneive_lcell_comb \ula_|video_|Add0~12 ( // Equation(s): // \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) // \ula_|video_|Add0~13 = CARRY((\ula_|video_|vga_hc [6] & !\ula_|video_|Add0~11 )) - .dataa(\ula_|video_|vga_hc [6]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [6]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~11 ), .combout(\ula_|video_|Add0~12_combout ), .cout(\ula_|video_|Add0~13 )); // synopsys translate_off -defparam \ula_|video_|Add0~12 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add0~12 .lut_mask = 16'hC30C; defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X39_Y33_N29 +// Location: FF_X29_Y30_N29 dffeas \ula_|video_|vga_hc[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -18250,7 +5528,25 @@ defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X39_Y33_N25 +// Location: LCCOMB_X29_Y30_N22 +cycloneive_lcell_comb \ula_|video_|Add0~14 ( +// Equation(s): +// \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) +// \ula_|video_|Add0~15 = CARRY((!\ula_|video_|Add0~13 ) # (!\ula_|video_|vga_hc [7])) + + .dataa(\ula_|video_|vga_hc [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~13 ), + .combout(\ula_|video_|Add0~14_combout ), + .cout(\ula_|video_|Add0~15 )); +// synopsys translate_off +defparam \ula_|video_|Add0~14 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y30_N3 dffeas \ula_|video_|vga_hc[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -18269,578 +5565,218 @@ defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N0 +// Location: LCCOMB_X30_Y29_N12 +cycloneive_lcell_comb \ula_|video_|Equal0~0 ( +// Equation(s): +// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [0] & (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [1]))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N26 +cycloneive_lcell_comb \ula_|video_|Equal0~1 ( +// Equation(s): +// \ula_|video_|Equal0~1_combout = (!\ula_|video_|vga_hc [7] & (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [4] & \ula_|video_|Equal0~0_combout ))) + + .dataa(\ula_|video_|vga_hc [7]), + .datab(\ula_|video_|vga_hc [5]), + .datac(\ula_|video_|vga_hc [4]), + .datad(\ula_|video_|Equal0~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0400; +defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N24 +cycloneive_lcell_comb \ula_|video_|Add0~16 ( +// Equation(s): +// \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) +// \ula_|video_|Add0~17 = CARRY((\ula_|video_|vga_hc [8] & !\ula_|video_|Add0~15 )) + + .dataa(\ula_|video_|vga_hc [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~15 ), + .combout(\ula_|video_|Add0~16_combout ), + .cout(\ula_|video_|Add0~17 )); +// synopsys translate_off +defparam \ula_|video_|Add0~16 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N28 +cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( +// Equation(s): +// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Add0~16_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Add0~16_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y30_N17 +dffeas \ula_|video_|vga_hc[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~2_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N26 +cycloneive_lcell_comb \ula_|video_|Add0~18 ( +// Equation(s): +// \ula_|video_|Add0~18_combout = \ula_|video_|vga_hc [9] $ (\ula_|video_|Add0~17 ) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [9]), + .datac(gnd), + .datad(gnd), + .cin(\ula_|video_|Add0~17 ), + .combout(\ula_|video_|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add0~18 .lut_mask = 16'h3C3C; +defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N2 +cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( +// Equation(s): +// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Add0~18_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Add0~18_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y30_N5 +dffeas \ula_|video_|vga_hc[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~1_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N0 +cycloneive_lcell_comb \ula_|video_|Equal1~0 ( +// Equation(s): +// \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9])) # (!\ula_|video_|Equal0~1_combout ) + + .dataa(\ula_|video_|Equal0~1_combout ), + .datab(\ula_|video_|vga_hc [9]), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [8]), + .cin(gnd), + .combout(\ula_|video_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal1~0 .lut_mask = 16'hF7FF; +defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N0 cycloneive_lcell_comb \ula_|video_|Add1~0 ( // Equation(s): // \ula_|video_|Add1~0_combout = \ula_|video_|vga_vc [0] $ (VCC) // \ula_|video_|Add1~1 = CARRY(\ula_|video_|vga_vc [0]) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [0]), + .dataa(\ula_|video_|vga_vc [0]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(gnd), .combout(\ula_|video_|Add1~0_combout ), .cout(\ula_|video_|Add1~1 )); // synopsys translate_off -defparam \ula_|video_|Add1~0 .lut_mask = 16'h33CC; +defparam \ula_|video_|Add1~0 .lut_mask = 16'h55AA; defparam \ula_|video_|Add1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N2 +// Location: LCCOMB_X32_Y29_N2 cycloneive_lcell_comb \ula_|video_|Add1~2 ( // Equation(s): // \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) // \ula_|video_|Add1~3 = CARRY((!\ula_|video_|Add1~1 ) # (!\ula_|video_|vga_vc [1])) - .dataa(\ula_|video_|vga_vc [1]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [1]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~1 ), .combout(\ula_|video_|Add1~2_combout ), .cout(\ula_|video_|Add1~3 )); // synopsys translate_off -defparam \ula_|video_|Add1~2 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add1~2 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Add1~4 ( -// Equation(s): -// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) -// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) - - .dataa(\ula_|video_|vga_vc [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~3 ), - .combout(\ula_|video_|Add1~4_combout ), - .cout(\ula_|video_|Add1~5 )); -// synopsys translate_off -defparam \ula_|video_|Add1~4 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N12 -cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( -// Equation(s): -// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [2]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~4_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~4_combout ), - .datac(\ula_|video_|vga_vc [2]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N13 -dffeas \ula_|video_|vga_vc[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[2]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N6 -cycloneive_lcell_comb \ula_|video_|Add1~6 ( -// Equation(s): -// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) -// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~5 ), - .combout(\ula_|video_|Add1~6_combout ), - .cout(\ula_|video_|Add1~7 )); -// synopsys translate_off -defparam \ula_|video_|Add1~6 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( -// Equation(s): -// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) - - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|Add1~6_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h5140; -defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N3 -dffeas \ula_|video_|vga_vc[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_vc[3]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N8 -cycloneive_lcell_comb \ula_|video_|Add1~8 ( -// Equation(s): -// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) -// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~7 ), - .combout(\ula_|video_|Add1~8_combout ), - .cout(\ula_|video_|Add1~9 )); -// synopsys translate_off -defparam \ula_|video_|Add1~8 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( -// Equation(s): -// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~8_combout ), - .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[4]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N21 -dffeas \ula_|video_|vga_vc[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[4]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N10 -cycloneive_lcell_comb \ula_|video_|Add1~10 ( -// Equation(s): -// \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) -// \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~9 ), - .combout(\ula_|video_|Add1~10_combout ), - .cout(\ula_|video_|Add1~11 )); -// synopsys translate_off -defparam \ula_|video_|Add1~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N22 -cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( -// Equation(s): -// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [5])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~10_combout ))))) - - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(\ula_|video_|vga_vc [5]), - .datad(\ula_|video_|Add1~10_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[5]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h5140; -defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N17 -dffeas \ula_|video_|vga_vc[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_vc[5]~8_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N12 -cycloneive_lcell_comb \ula_|video_|Add1~12 ( -// Equation(s): -// \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) -// \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [6]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~11 ), - .combout(\ula_|video_|Add1~12_combout ), - .cout(\ula_|video_|Add1~13 )); -// synopsys translate_off -defparam \ula_|video_|Add1~12 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N6 -cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( -// Equation(s): -// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [6]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~12_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~12_combout ), - .datac(\ula_|video_|vga_vc [6]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[6]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N7 -dffeas \ula_|video_|vga_vc[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[6]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Add1~14 ( -// Equation(s): -// \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) -// \ula_|video_|Add1~15 = CARRY((!\ula_|video_|Add1~13 ) # (!\ula_|video_|vga_vc [7])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~13 ), - .combout(\ula_|video_|Add1~14_combout ), - .cout(\ula_|video_|Add1~15 )); -// synopsys translate_off -defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N14 -cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( -// Equation(s): -// \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~14_combout ), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[7]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N15 -dffeas \ula_|video_|vga_vc[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[7]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add1~16 ( -// Equation(s): -// \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) -// \ula_|video_|Add1~17 = CARRY((\ula_|video_|vga_vc [8] & !\ula_|video_|Add1~15 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [8]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~15 ), - .combout(\ula_|video_|Add1~16_combout ), - .cout(\ula_|video_|Add1~17 )); -// synopsys translate_off -defparam \ula_|video_|Add1~16 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N24 -cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( -// Equation(s): -// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~16_combout ), - .datac(\ula_|video_|vga_vc [8]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[8]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N25 -dffeas \ula_|video_|vga_vc[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[8]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Add1~18 ( -// Equation(s): -// \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_vc [9]), - .cin(\ula_|video_|Add1~17 ), - .combout(\ula_|video_|Add1~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N10 -cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( -// Equation(s): -// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [9]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~18_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~18_combout ), - .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[9]~9_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N11 -dffeas \ula_|video_|vga_vc[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[9]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Equal2~0 ( -// Equation(s): -// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [4] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [4]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [8]), - .cin(gnd), - .combout(\ula_|video_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y33_N30 -cycloneive_lcell_comb \ula_|video_|Equal3~0 ( -// Equation(s): -// \ula_|video_|Equal3~0_combout = (\ula_|video_|vga_vc [3] & (\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [1] & \ula_|video_|vga_vc [0]))) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal3~0 .lut_mask = 16'h0800; -defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Equal3~1 ( -// Equation(s): -// \ula_|video_|Equal3~1_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal2~0_combout & \ula_|video_|Equal3~0_combout ))) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|Equal2~0_combout ), - .datad(\ula_|video_|Equal3~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal3~1 .lut_mask = 16'h4000; -defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N28 -cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( -// Equation(s): -// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [0]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~0_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~0_combout ), - .datac(\ula_|video_|vga_vc [0]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N29 -dffeas \ula_|video_|vga_vc[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[0]~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N22 +// Location: LCCOMB_X32_Y30_N30 cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( // Equation(s): -// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [1]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~2_combout )))) +// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [1])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~2_combout ))))) .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~2_combout ), + .datab(\ula_|video_|Equal3~1_combout ), .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|Equal3~1_combout ), + .datad(\ula_|video_|Add1~2_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h3120; defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y33_N23 +// Location: FF_X32_Y30_N31 dffeas \ula_|video_|vga_vc[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[1]~1_combout ), @@ -18859,6 +5795,558 @@ defparam \ula_|video_|vga_vc[1] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[1] .power_up = "low"; // synopsys translate_on +// Location: LCCOMB_X32_Y29_N4 +cycloneive_lcell_comb \ula_|video_|Add1~4 ( +// Equation(s): +// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) +// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~3 ), + .combout(\ula_|video_|Add1~4_combout ), + .cout(\ula_|video_|Add1~5 )); +// synopsys translate_off +defparam \ula_|video_|Add1~4 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N20 +cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( +// Equation(s): +// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [2]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~4_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~4_combout ), + .datac(\ula_|video_|vga_vc [2]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y30_N21 +dffeas \ula_|video_|vga_vc[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[2]~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N6 +cycloneive_lcell_comb \ula_|video_|Add1~6 ( +// Equation(s): +// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) +// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~5 ), + .combout(\ula_|video_|Add1~6_combout ), + .cout(\ula_|video_|Add1~7 )); +// synopsys translate_off +defparam \ula_|video_|Add1~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N26 +cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( +// Equation(s): +// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|Add1~6_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y30_N27 +dffeas \ula_|video_|vga_vc[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[3]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N8 +cycloneive_lcell_comb \ula_|video_|Add1~8 ( +// Equation(s): +// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) +// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~7 ), + .combout(\ula_|video_|Add1~8_combout ), + .cout(\ula_|video_|Add1~9 )); +// synopsys translate_off +defparam \ula_|video_|Add1~8 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N22 +cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( +// Equation(s): +// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~8_combout ), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y30_N23 +dffeas \ula_|video_|vga_vc[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[4]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N10 +cycloneive_lcell_comb \ula_|video_|Add1~10 ( +// Equation(s): +// \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) +// \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~9 ), + .combout(\ula_|video_|Add1~10_combout ), + .cout(\ula_|video_|Add1~11 )); +// synopsys translate_off +defparam \ula_|video_|Add1~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N8 +cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( +// Equation(s): +// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [5])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~10_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Add1~10_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[5]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y30_N9 +dffeas \ula_|video_|vga_vc[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[5]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N12 +cycloneive_lcell_comb \ula_|video_|Add1~12 ( +// Equation(s): +// \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) +// \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~11 ), + .combout(\ula_|video_|Add1~12_combout ), + .cout(\ula_|video_|Add1~13 )); +// synopsys translate_off +defparam \ula_|video_|Add1~12 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N16 +cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( +// Equation(s): +// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [6])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~12_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [6]), + .datad(\ula_|video_|Add1~12_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[6]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y30_N17 +dffeas \ula_|video_|vga_vc[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[6]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N14 +cycloneive_lcell_comb \ula_|video_|Add1~14 ( +// Equation(s): +// \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) +// \ula_|video_|Add1~15 = CARRY((!\ula_|video_|Add1~13 ) # (!\ula_|video_|vga_vc [7])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [7]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~13 ), + .combout(\ula_|video_|Add1~14_combout ), + .cout(\ula_|video_|Add1~15 )); +// synopsys translate_off +defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N22 +cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( +// Equation(s): +// \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~14_combout ), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[7]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y30_N23 +dffeas \ula_|video_|vga_vc[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[7]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N16 +cycloneive_lcell_comb \ula_|video_|Add1~16 ( +// Equation(s): +// \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) +// \ula_|video_|Add1~17 = CARRY((\ula_|video_|vga_vc [8] & !\ula_|video_|Add1~15 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [8]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~15 ), + .combout(\ula_|video_|Add1~16_combout ), + .cout(\ula_|video_|Add1~17 )); +// synopsys translate_off +defparam \ula_|video_|Add1~16 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N20 +cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( +// Equation(s): +// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~16_combout ), + .datac(\ula_|video_|vga_vc [8]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[8]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y30_N21 +dffeas \ula_|video_|vga_vc[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[8]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N18 +cycloneive_lcell_comb \ula_|video_|Add1~18 ( +// Equation(s): +// \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc [9]), + .cin(\ula_|video_|Add1~17 ), + .combout(\ula_|video_|Add1~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N8 +cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( +// Equation(s): +// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [9])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~18_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [9]), + .datad(\ula_|video_|Add1~18_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y30_N9 +dffeas \ula_|video_|vga_vc[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[9]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N10 +cycloneive_lcell_comb \ula_|video_|Equal3~0 ( +// Equation(s): +// \ula_|video_|Equal3~0_combout = (!\ula_|video_|vga_vc [1] & (\ula_|video_|vga_vc [2] & (\ula_|video_|vga_vc [3] & \ula_|video_|vga_vc [0]))) + + .dataa(\ula_|video_|vga_vc [1]), + .datab(\ula_|video_|vga_vc [2]), + .datac(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|vga_vc [0]), + .cin(gnd), + .combout(\ula_|video_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal3~0 .lut_mask = 16'h4000; +defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N30 +cycloneive_lcell_comb \ula_|video_|Equal2~0 ( +// Equation(s): +// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [4]))) + + .dataa(\ula_|video_|vga_vc [8]), + .datab(\ula_|video_|vga_vc [6]), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|vga_vc [4]), + .cin(gnd), + .combout(\ula_|video_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N16 +cycloneive_lcell_comb \ula_|video_|Equal3~1 ( +// Equation(s): +// \ula_|video_|Equal3~1_combout = (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal3~0_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) + + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|Equal3~0_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Equal2~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal3~1 .lut_mask = 16'h0800; +defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N24 +cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( +// Equation(s): +// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [0])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~0_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [0]), + .datad(\ula_|video_|Add1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y30_N25 +dffeas \ula_|video_|vga_vc[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N18 +cycloneive_lcell_comb \ula_|video_|Equal2~1 ( +// Equation(s): +// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [0] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & !\ula_|video_|vga_vc [9]))) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [2]), + .datac(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|vga_vc [9]), + .cin(gnd), + .combout(\ula_|video_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal2~1 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N12 +cycloneive_lcell_comb \ula_|video_|Equal2~2 ( +// Equation(s): +// \ula_|video_|Equal2~2_combout = (\ula_|video_|Equal2~1_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout )) + + .dataa(\ula_|video_|Equal2~1_combout ), + .datab(gnd), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Equal2~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal2~2 .lut_mask = 16'h0A00; +defparam \ula_|video_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: IOIBUF_X27_Y0_N15 cycloneive_io_ibuf \SW[1]~input ( .i(SW[1]), @@ -18869,15 +6357,15 @@ defparam \SW[1]~input .bus_hold = "false"; defparam \SW[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X34_Y33_N30 +// Location: LCCOMB_X31_Y27_N2 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_vc [1] & (!\SW[1]~input_o & !\ula_|video_|vga_hc [9]))) +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_vc [1] & (!\ula_|video_|vga_hc [9] & !\SW[1]~input_o ))) .dataa(\ula_|video_|vga_hc [8]), .datab(\ula_|video_|vga_vc [1]), - .datac(\SW[1]~input_o ), - .datad(\ula_|video_|vga_hc [9]), + .datac(\ula_|video_|vga_hc [9]), + .datad(\SW[1]~input_o ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), .cout()); @@ -18886,18144 +6374,249 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .lut_mask = 16'h0001; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( +// Location: LCCOMB_X30_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( // Equation(s): -// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal79~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N16 -cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( -// Equation(s): -// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|interrupts_|DFFE_instIFF2~q -// ))))) # (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal79~0_combout ), - .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hB8F0; -defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N28 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|interrupts_|DFFE_inst44~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h7733; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G16 -cycloneive_clkctrl \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: FF_X35_Y17_N17 -dffeas \z80_|interrupts_|DFFE_instIFF2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|DFFE_instIFF2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N2 -cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( -// Equation(s): -// \z80_|interrupts_|iff1~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|interrupts_|iff1~q ), - .datac(\z80_|pla_decode_|Equal79~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|interrupts_|iff1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hEC4C; -defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N18 -cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( -// Equation(s): -// \z80_|interrupts_|iff1~1_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|pla_decode_|Equal38~2_combout & ((\z80_|interrupts_|iff1~0_combout ))))) # -// (!\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|interrupts_|iff1~0_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|interrupts_|DFFE_instIFF2~q ), - .datac(\z80_|pla_decode_|Equal38~2_combout ), - .datad(\z80_|interrupts_|iff1~0_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|iff1~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hDF80; -defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N12 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|interrupts_|DFFE_inst44~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFF3; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N19 -dffeas \z80_|interrupts_|iff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|iff1~1_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|iff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|iff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Equal2~1 ( -// Equation(s): -// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [3] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [0]))) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal2~1 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Equal2~2 ( -// Equation(s): -// \ula_|video_|Equal2~2_combout = (\ula_|video_|Equal2~1_combout & (\ula_|video_|Equal2~0_combout & !\ula_|video_|vga_vc [5])) - - .dataa(gnd), - .datab(\ula_|video_|Equal2~1_combout ), - .datac(\ula_|video_|Equal2~0_combout ), - .datad(\ula_|video_|vga_vc [5]), - .cin(gnd), - .combout(\ula_|video_|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal2~2 .lut_mask = 16'h00C0; -defparam \ula_|video_|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y31_N28 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (!\ula_|video_|vga_hc [7] & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & (\z80_|interrupts_|iff1~q & \ula_|video_|Equal2~2_combout ))) - - .dataa(\ula_|video_|vga_hc [7]), - .datab(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), - .datac(\z80_|interrupts_|iff1~q ), - .datad(\ula_|video_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h4000; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y31_N29 -dffeas \z80_|interrupts_|int_armed ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|int_armed~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; -defparam \z80_|interrupts_|int_armed .power_up = "low"; -// synopsys translate_on - -// Location: FF_X32_Y15_N11 -dffeas \z80_|interrupts_|DFFE_inst44 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|interrupts_|int_armed~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|interrupts_|test1~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|DFFE_inst44~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~38 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~38_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|decode_state_|in_halt~q ) # (\z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .datab(gnd), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~38 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|pc_inc_hold~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~91 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~91_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~91 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~45 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~45_combout = (\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) # (!\z80_|pla_decode_|Equal19~0_combout & -// (((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~45 .lut_mask = 16'hF888; -defparam \z80_|execute_|pc_inc_hold~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~44 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~44_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((!\z80_|execute_|pc_inc_hold~49_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|pc_inc_hold~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~44 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|pc_inc_hold~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~46 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~46_combout = (\z80_|execute_|pc_inc_hold~45_combout ) # ((\z80_|execute_|pc_inc_hold~44_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~49_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~45_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|pc_inc_hold~44_combout ), - .datad(\z80_|execute_|pc_inc_hold~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~46 .lut_mask = 16'hFAFE; -defparam \z80_|execute_|pc_inc_hold~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~37 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~37_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|pc_inc_hold~29_combout ) # ((\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & -// (\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~37 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|pc_inc_hold~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~50 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~50_combout = (\z80_|execute_|pc_inc_hold~37_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|execute_|pc_inc_hold~37_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~50 .lut_mask = 16'hECCC; -defparam \z80_|execute_|pc_inc_hold~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~33_combout = (\z80_|execute_|ctl_mRead~10_combout & (((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|pla_decode_|Equal6~1_combout & -// ((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~2_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|pc_inc_hold~28_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|execute_|pc_inc_hold~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hECEE; -defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|execute_|ctl_mRead~15_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hEEA0; -defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|execute_|pc_inc_hold~33_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # ((\z80_|execute_|pc_inc_hold~31_combout ) # (\z80_|execute_|pc_inc_hold~32_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~33_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|pc_inc_hold~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~51 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~51_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ixy_d~15_combout ), .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~51_combout ), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~51 .lut_mask = 16'h57FF; -defparam \z80_|execute_|pc_inc_hold~51 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( +// Location: LCCOMB_X37_Y6_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) +// \z80_|execute_|ctl_mWrite~4_combout = (\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~30_combout ), + .combout(\z80_|execute_|ctl_mWrite~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~52 ( +// Location: LCCOMB_X36_Y6_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal0~0 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~52_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~52 .lut_mask = 16'hA800; -defparam \z80_|execute_|pc_inc_hold~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~35_combout = (!\z80_|execute_|pc_inc_hold~34_combout & (\z80_|execute_|pc_inc_hold~51_combout & (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~52_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~34_combout ), - .datab(\z80_|execute_|pc_inc_hold~51_combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|pc_inc_hold~52_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'h0040; -defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~36_combout = ((\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|execute_|pc_inc_hold~35_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hCF8F; -defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~44_combout = (((!\z80_|pla_decode_|Equal21~0_combout & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ixy_d~10_combout )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~45_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_inc_cy~44_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~50_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_inc_cy~44_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~43 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~43_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~43 .lut_mask = 16'hC080; -defparam \z80_|execute_|pc_inc_hold~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~71_combout = (\z80_|execute_|ctl_inc_cy~91_combout & (!\z80_|execute_|pc_inc_hold~46_combout & (\z80_|execute_|ctl_inc_cy~45_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~91_combout ), - .datab(\z80_|execute_|pc_inc_hold~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~45_combout ), - .datad(\z80_|execute_|pc_inc_hold~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~73_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~72_combout & \z80_|execute_|ctl_inc_cy~71_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_inc_cy~72_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~71_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_mWrite~16_combout & ((\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'h8C00; -defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~53 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~53_combout = (\z80_|pla_decode_|Equal11~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~53 .lut_mask = 16'hE000; -defparam \z80_|execute_|pc_inc_hold~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~39 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~39_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~53_combout & (\z80_|execute_|pc_inc_hold~35_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~50_combout ), - .datab(\z80_|execute_|pc_inc_hold~53_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~39 .lut_mask = 16'h0010; -defparam \z80_|execute_|pc_inc_hold~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~47 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~47_combout = (\z80_|execute_|pc_inc_hold~46_combout ) # ((\z80_|execute_|pc_inc_hold~43_combout ) # ((!\z80_|execute_|ctl_inc_cy~44_combout ) # (!\z80_|execute_|pc_inc_hold~39_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~46_combout ), - .datab(\z80_|execute_|pc_inc_hold~43_combout ), - .datac(\z80_|execute_|pc_inc_hold~39_combout ), - .datad(\z80_|execute_|ctl_inc_cy~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~47 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|pc_inc_hold~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~74_combout = (((!\z80_|execute_|ctl_inc_cy~40_combout ) # (!\z80_|execute_|ctl_inc_cy~34_combout )) # (!\z80_|execute_|ctl_inc_cy~35_combout )) # (!\z80_|execute_|ctl_inc_cy~43_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~43_combout ), - .datab(\z80_|execute_|ctl_inc_cy~35_combout ), - .datac(\z80_|execute_|ctl_inc_cy~34_combout ), - .datad(\z80_|execute_|ctl_inc_cy~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~78_combout = ((\z80_|execute_|ctl_inc_cy~74_combout ) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~39_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~39_combout ), - .datac(\z80_|execute_|ctl_inc_cy~77_combout ), - .datad(\z80_|execute_|ctl_inc_cy~74_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (((!\z80_|execute_|pc_inc_hold~47_combout & \z80_|execute_|ctl_inc_cy~91_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~47_combout ), - .datab(\z80_|execute_|ctl_inc_cy~78_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~91_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'h4C0C; -defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~45_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|pc_inc_hold~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal19~1_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hA800; -defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~82_combout = (\z80_|execute_|ctl_inc_cy~81_combout ) # ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~81_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|pc_inc_hold~47_combout & (!\z80_|execute_|pc_inc_hold~38_combout & ((\z80_|execute_|ctl_inc_cy~82_combout ) # (!\z80_|execute_|ctl_inc_cy~38_combout )))) # (!\z80_|execute_|pc_inc_hold~47_combout -// & ((\z80_|execute_|ctl_inc_cy~82_combout ) # ((!\z80_|execute_|ctl_inc_cy~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~47_combout ), - .datab(\z80_|execute_|ctl_inc_cy~82_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'h4C5F; -defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~84_combout = (\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~79_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|execute_|ctl_inc_cy~83_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~42 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~42_combout = ((\z80_|execute_|pc_inc_hold~34_combout ) # (\z80_|execute_|pc_inc_hold~52_combout )) # (!\z80_|execute_|pc_inc_hold~30_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|pc_inc_hold~52_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~42 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|pc_inc_hold~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~90 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~90_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~8_combout ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~90 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~41 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~41_combout = (\z80_|execute_|pc_inc_hold~31_combout ) # ((\z80_|execute_|pc_inc_hold~32_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~31_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|execute_|pc_inc_hold~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~41 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|pc_inc_hold~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~66_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'h0004; -defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~66_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~20_combout & !\z80_|execute_|pc_inc_hold~31_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|ctl_inc_cy~66_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hAA02; -defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~67_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|pc_inc_hold~41_combout & \z80_|execute_|ctl_mRead~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|pc_inc_hold~41_combout ), - .datac(\z80_|execute_|ctl_inc_cy~67_combout ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hF2F0; -defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~64_combout = (!\z80_|execute_|pc_inc_hold~31_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|pc_inc_hold~34_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_sw_4u~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h0C08; -defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~65_combout = (\z80_|execute_|ctl_inc_cy~63_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((\z80_|execute_|ctl_inc_cy~64_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|execute_|ctl_inc_cy~64_combout ), - .datad(\z80_|execute_|ctl_inc_cy~63_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hFFC4; -defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|ctl_inc_cy~68_combout ) # ((\z80_|execute_|ctl_inc_cy~65_combout ) # ((!\z80_|execute_|pc_inc_hold~42_combout & !\z80_|execute_|ctl_inc_cy~90_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~42_combout ), - .datab(\z80_|execute_|ctl_inc_cy~90_combout ), - .datac(\z80_|execute_|ctl_inc_cy~68_combout ), - .datad(\z80_|execute_|ctl_inc_cy~65_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~49_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_inc_cy~92_combout ) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_inc_cy~92_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~50_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) # (!\z80_|execute_|ixy_d~9_combout & -// (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_mRead~11_combout )) # (!\z80_|execute_|ctl_inc_cy~94_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|execute_|ctl_inc_cy~94_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_inc_cy~51_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~51_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~36_combout = ((!\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_mWrite~4_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~36_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_sw_2u~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~54_combout = ((\z80_|execute_|ctl_inc_cy~49_combout ) # ((\z80_|execute_|ctl_inc_cy~52_combout ) # (!\z80_|execute_|ctl_inc_cy~37_combout ))) # (!\z80_|execute_|ctl_inc_cy~53_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), - .datab(\z80_|execute_|ctl_inc_cy~49_combout ), - .datac(\z80_|execute_|ctl_inc_cy~52_combout ), - .datad(\z80_|execute_|ctl_inc_cy~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~41_combout = (!\z80_|execute_|ctl_mRead~17_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'h0045; -defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~58_combout = (\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_inc_cy~41_combout )) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~41_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'hEEFF; -defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout ) # ((\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & -// ((\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~56_combout = (((!\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|fMRead~3_combout ) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~89 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~89_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~89 .lut_mask = 16'hA020; -defparam \z80_|execute_|ctl_inc_cy~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_inc_cy~56_combout ) # (\z80_|execute_|ctl_inc_cy~89_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ctl_inc_cy~55_combout ), - .datac(\z80_|execute_|ctl_inc_cy~56_combout ), - .datad(\z80_|execute_|ctl_inc_cy~89_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_inc_cy~57_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~58_combout ) # (!\z80_|execute_|fMRead~5_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_inc_cy~58_combout ), - .datac(\z80_|execute_|fMRead~5_combout ), - .datad(\z80_|execute_|ctl_inc_cy~57_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'hFF8A; -defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~60_combout = (\z80_|execute_|pc_inc_hold~38_combout & (\z80_|execute_|pc_inc_hold~35_combout & (\z80_|execute_|ctl_inc_cy~54_combout ))) # (!\z80_|execute_|pc_inc_hold~38_combout & (((\z80_|execute_|ctl_inc_cy~54_combout ) # -// (\z80_|execute_|ctl_inc_cy~59_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|pc_inc_hold~35_combout ), - .datac(\z80_|execute_|ctl_inc_cy~54_combout ), - .datad(\z80_|execute_|ctl_inc_cy~59_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'hD5D0; -defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|pc_inc_hold~50_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|pc_inc_hold~50_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~88_combout = (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ) # ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~47_combout ) # ((\z80_|execute_|ctl_inc_cy~88_combout & ((\z80_|execute_|pc_inc_hold~39_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~39_combout ), - .datab(\z80_|execute_|ctl_inc_cy~47_combout ), - .datac(\z80_|execute_|ctl_inc_cy~88_combout ), - .datad(\z80_|execute_|pc_inc_hold~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'hECFC; -defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~40 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~40_combout = (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~34_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~40 .lut_mask = 16'h0C0C; -defparam \z80_|execute_|pc_inc_hold~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~61_combout = (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h3200; -defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~62_combout = (\z80_|execute_|ctl_inc_cy~61_combout ) # ((!\z80_|execute_|ctl_inc_cy~42_combout & ((\z80_|execute_|pc_inc_hold~40_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|pc_inc_hold~40_combout ), - .datac(\z80_|execute_|ctl_inc_cy~61_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hF0FD; -defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~69_combout ) # ((\z80_|execute_|ctl_inc_cy~60_combout ) # ((\z80_|execute_|ctl_inc_cy~48_combout ) # (\z80_|execute_|ctl_inc_cy~62_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), - .datab(\z80_|execute_|ctl_inc_cy~60_combout ), - .datac(\z80_|execute_|ctl_inc_cy~48_combout ), - .datad(\z80_|execute_|ctl_inc_cy~62_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~85_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~84_combout ) # (\z80_|execute_|ctl_inc_cy~70_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), - .datab(\z80_|execute_|ctl_inc_cy~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~84_combout ), - .datad(\z80_|execute_|ctl_inc_cy~70_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (\z80_|execute_|ctl_inc_cy~85_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_cy~85_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hAF2F; -defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( -// Equation(s): -// \z80_|address_latch_|abusz [0] = (\z80_|reg_file_|db_lo_as[0]~3_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [0]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|Q[0]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[0]~feeder_combout = \z80_|address_latch_|abusz [0] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [0]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N23 -dffeas \z80_|address_latch_|Q[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[0]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X31_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[1]~32_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .datad(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_cy~85_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h6A6A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hAF2F; -defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( -// Equation(s): -// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [1]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h3300; -defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N19 -dffeas \z80_|address_latch_|Q[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [1]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout = \z80_|address_latch_|Q [1] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|address_latch_|Q [1]), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .lut_mask = 16'h0F87; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & (\z80_|execute_|ctl_inc_cy~85_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hF575; -defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( -// Equation(s): -// \z80_|address_latch_|abusz [2] = (\z80_|reg_file_|db_lo_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [2]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h00AA; -defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N14 -cycloneive_lcell_comb \z80_|address_latch_|Q[2]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[2]~feeder_combout = \z80_|address_latch_|abusz [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [2]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N15 -dffeas \z80_|address_latch_|Q[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[2]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|address_latch_|Q [2] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|address_latch_|Q [2]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h40BF; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~86_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), - .datab(\z80_|execute_|ctl_inc_cy~79_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|execute_|ctl_inc_cy~83_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~86_combout ) # -// (\z80_|execute_|ctl_inc_cy~70_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datab(\z80_|execute_|ctl_inc_cy~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~86_combout ), - .datad(\z80_|execute_|ctl_inc_cy~70_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hAAA8; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~11_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout )) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout = (\z80_|execute_|ctl_inc_cy~85_combout & ((\z80_|address_latch_|Q [1] & (!\z80_|execute_|ctl_inc_dec~11_combout & \z80_|address_latch_|Q [0])) # (!\z80_|address_latch_|Q -// [1] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [0])))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_cy~85_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .lut_mask = 16'h2400; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout -// ))) - - .dataa(gnd), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h3FC0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N11 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N5 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'h3F3B; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~29_combout ) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|setM1~29_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_al_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'hB3F3; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & !\z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ) # ((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hF7F5; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = ((\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|execute_|setM1~46_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datad(\z80_|execute_|setM1~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'h5DDD; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ) # (!\z80_|execute_|ctl_reg_gp_we~2_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~40 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[3]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~41 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[3]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hB3FF; -defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~12_combout = (\z80_|execute_|ctl_reg_in_hi~11_combout ) # (((!\z80_|execute_|ctl_reg_in_hi~4_combout ) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~44_combout = (\z80_|alu_|db[3]~11_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[3]~11_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~44 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~48_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h4444; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h4000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|execute_|ctl_reg_gp_we~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~43_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h5450; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # (\z80_|execute_|ctl_reg_sys_we_lo~3_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hFB33; -defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~combout = ((\z80_|reg_control_|reg_sys_we_hi~0_combout ) # (\z80_|execute_|ctl_reg_sys_we~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF3; -defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~45 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[3]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0002; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h0400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0008; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~42_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~42 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[3]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~46_combout = (\z80_|reg_file_|gdfx_temp1[3]~44_combout & (\z80_|reg_file_|gdfx_temp1[3]~43_combout & (\z80_|reg_file_|gdfx_temp1[3]~45_combout & \z80_|reg_file_|gdfx_temp1[3]~42_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~46 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~47_combout = (\z80_|reg_file_|gdfx_temp1[3]~40_combout & (\z80_|reg_file_|gdfx_temp1[3]~41_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout & \z80_|reg_file_|gdfx_temp1[3]~46_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~47 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFF8; -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~16_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|reg_control_|reg_sel_pc~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N11 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|alu_|db[1]~13_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[1]~13_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[1]~13_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~21_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~12_combout & (\z80_|reg_file_|gdfx_temp1[1]~10_combout & \z80_|reg_file_|gdfx_temp1[1]~11_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~8_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout & (\z80_|reg_file_|gdfx_temp1[1]~14_combout & \z80_|reg_file_|gdfx_temp1[1]~9_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .datac(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (!\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_control_|reg_sys_we_lo~combout ) # ((!\z80_|execute_|ctl_reg_sel_ir~1_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'h8AAA; -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_file_|gdfx_temp1[1]~21_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[1]~21_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|reg_control_|reg_sel_pc~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # (\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|address_latch_|Q [7] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [8]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'h96CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|alu_|db[0]~19_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[0]~19_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[0]~19_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~24_combout & (\z80_|reg_file_|gdfx_temp1[0]~26_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & \z80_|reg_file_|gdfx_temp1[0]~27_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|gdfx_temp1[0]~28_combout & \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .datad(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( -// Equation(s): -// \z80_|address_latch_|abusz [8] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[0]~6_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [8]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N9 -dffeas \z80_|address_latch_|Q[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [8]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N18 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|address_latch_|Q [7] & (\z80_|address_latch_|Q [8] & !\z80_|execute_|ctl_inc_dec~11_combout -// )) # (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [8] & \z80_|execute_|ctl_inc_dec~11_combout )))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [8]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h1800; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N24 -cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( -// Equation(s): -// \z80_|address_latch_|abusz [9] = (\z80_|reg_file_|db_hi_as[1]~3_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [9]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|Q[9]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[9]~feeder_combout = \z80_|address_latch_|abusz [9] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [9]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[9]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[9]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[9]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N5 -dffeas \z80_|address_latch_|Q[9] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[9]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ -// (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [9]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~32 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~35_combout = (\z80_|alu_|db[2]~15_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[2]~15_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[2]~15_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~35 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~34 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~33_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~33 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N1 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~36 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~37_combout = (\z80_|reg_file_|gdfx_temp1[2]~35_combout & (\z80_|reg_file_|gdfx_temp1[2]~34_combout & (\z80_|reg_file_|gdfx_temp1[2]~33_combout & \z80_|reg_file_|gdfx_temp1[2]~36_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~37 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~31 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~38_combout = (\z80_|reg_file_|gdfx_temp1[2]~32_combout & (\z80_|reg_file_|gdfx_temp1[2]~37_combout & (\z80_|reg_file_|gdfx_temp1[2]~31_combout & \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~38 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~39_combout = ((\z80_|reg_file_|gdfx_temp1[2]~38_combout & ((\z80_|reg_file_|db_hi_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~39 .lut_mask = 16'h8FAF; -defparam \z80_|reg_file_|gdfx_temp1[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp1[2]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[2]~39_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~7 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~8_combout = (\z80_|reg_file_|db_hi_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~7_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~8 .lut_mask = 16'hCC44; -defparam \z80_|reg_file_|db_hi_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~9 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~9_combout = ((\z80_|reg_file_|db_hi_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[2]~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~9 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N0 -cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( -// Equation(s): -// \z80_|address_latch_|abusz [10] = (\z80_|reg_file_|db_hi_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [10]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|Q[10]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[10]~feeder_combout = \z80_|address_latch_|abusz [10] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [10]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[10]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[10]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N27 -dffeas \z80_|address_latch_|Q[10] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[10]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [10] & (\z80_|address_latch_|Q [9] & -// !\z80_|execute_|ctl_inc_dec~11_combout )) # (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [9] & \z80_|execute_|ctl_inc_dec~11_combout )))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [9]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h1800; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( -// Equation(s): -// \z80_|address_latch_|abusz [11] = (\z80_|reg_file_|db_hi_as[3]~12_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h00CC; -defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N15 -dffeas \z80_|address_latch_|Q[11] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [11]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout $ (\z80_|address_latch_|Q [11]) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(gnd), - .datac(\z80_|address_latch_|Q [11]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h5A5A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp1[3]~48_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[3]~48_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~11 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~11_combout = (\z80_|reg_file_|db_hi_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[3]~10_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~11 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|db_hi_as[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~12_combout = ((\z80_|reg_file_|db_hi_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[3]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~12 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~48_combout = ((\z80_|reg_file_|gdfx_temp1[3]~47_combout & ((\z80_|reg_file_|db_hi_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~48 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'h888A; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hC0E0; -defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[3]~8_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N7 -dffeas \z80_|alu_|op1_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~3 ( -// Equation(s): -// \z80_|alu_|alu_op1[3]~3_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])) - - .dataa(gnd), - .datab(\z80_|alu_|op1_high [3]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[3]~3 .lut_mask = 16'hF0CC; -defparam \z80_|alu_|alu_op1[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [2])))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|alu_|alu_op2[2]~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0305; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = ((\z80_|pla_decode_|Equal8~0_combout & (\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mWrite~2_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|pla_decode_|Equal8~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'hAAFB; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~0_combout = (\z80_|pla_decode_|Equal1~5_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~5_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) # (((\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = ((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) # -// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .lut_mask = 16'h5050; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_zero~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFFFA; -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N1 -dffeas \z80_|alu_|op2_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[1]~20_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N23 -dffeas \z80_|alu_|op1_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))))) - - .dataa(\z80_|alu_|op1_low [1]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'h8C80; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|alu_|db_low[1]~17_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .datac(\z80_|alu_|db_low[1]~17_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N21 -dffeas \z80_|alu_|op2_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~20_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal68~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal68~2_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .lut_mask = 16'h0D0F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|execute_|ctl_state_alu~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # ((\z80_|execute_|ctl_state_alu~11_combout ) # (!\z80_|execute_|ctl_state_alu~8_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~9_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datac(\z80_|execute_|ctl_state_alu~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~18_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~12_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h7577; -defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) +// \z80_|pla_decode_|Equal0~0_combout = (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~4_combout ) .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal61~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal61~2_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M4_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'hFC00; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~20_combout & (\z80_|execute_|ctl_alu_core_hf~18_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~21_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~17_combout & (((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~4_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout -// ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & (\z80_|execute_|ctl_alu_core_S~4_combout & \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_ir_we~11_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .lut_mask = 16'hC4CC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~20_combout = ((\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout ))) # (!\z80_|execute_|ctl_state_alu~12_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal71~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal71~2_combout = (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~12_combout & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal71~2 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_alu_core_hf~20_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & !\z80_|pla_decode_|Equal71~2_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|pla_decode_|Equal71~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'h0080; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~31_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~9_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'h1333; -defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (\z80_|pla_decode_|Equal21~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal3~0_combout & -// ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'hFCA8; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout = (\z80_|pla_decode_|Equal13~1_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal13~1_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N16 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & \z80_|pla_decode_|Equal63~0_combout -// ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'hFFEC; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (\z80_|execute_|ctl_alu_op_low~31_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & !\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'h0080; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal72~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal72~2_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal72~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal72~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal72~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal73~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|pla_decode_|Equal61~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal61~2_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (!\z80_|pla_decode_|Equal72~2_combout & (!\z80_|pla_decode_|Equal73~2_combout & \z80_|execute_|ctl_flags_nf_we~0_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datab(\z80_|pla_decode_|Equal72~2_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~3_combout = ((\z80_|execute_|ctl_flags_nf_we~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout )) # (!\z80_|execute_|ctl_flags_nf_we~1_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFAFF; -defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|pla_decode_|Equal48~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|execute_|ctl_flags_sz_we~5_combout & \z80_|execute_|ctl_alu_core_R~0_combout )))) # -// (!\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_flags_sz_we~5_combout & ((\z80_|execute_|ctl_alu_core_R~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hECA0; -defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~4_combout = (((\z80_|execute_|ctl_flags_nf_we~3_combout ) # (\z80_|execute_|ctl_flags_sz_we~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~12_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~15 ( -// Equation(s): -// \z80_|execute_|setM1~15_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_state_alu~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~15 .lut_mask = 16'h5000; -defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~16 ( -// Equation(s): -// \z80_|execute_|setM1~16_combout = (\z80_|execute_|setM1~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~31_combout ))) - - .dataa(\z80_|execute_|setM1~15_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0200; -defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|setM1~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|setM1~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & \z80_|execute_|ctl_alu_oe~5_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (\z80_|execute_|ctl_flags_xy_we~7_combout & \z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) - - .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~7_combout ), .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .combout(\z80_|pla_decode_|Equal0~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal0~0 .lut_mask = 16'h5500; +defparam \z80_|pla_decode_|Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 ( +// Location: LCCOMB_X40_Y13_N8 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( // Equation(s): -// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal11~1_combout & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) +// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal11~1_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), + .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88C0; +defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), - .cout()); +// Location: FF_X40_Y13_N9 +dffeas \z80_|sequencer_|DFFE_M3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M3_ff~q ), + .prn(vcc)); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFBAA; -defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~7_combout = (\z80_|execute_|ctl_alu_core_R~1_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_flags_alu~18_combout )) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~7 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_flags_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~8 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~8_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal56~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~8 .lut_mask = 16'h7F00; -defparam \z80_|reg_control_|reg_sys_we_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~8_combout = ((\z80_|execute_|ctl_flags_alu~7_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~8_combout ) # (!\z80_|execute_|ctl_flags_alu~16_combout ))) # (!\z80_|execute_|ctl_flags_alu~6_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), - .datab(\z80_|execute_|ctl_flags_alu~7_combout ), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~8 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_alu_op_low~10_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal20~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~10_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'h0070; -defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~13_combout = (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_flags_xy_we~16_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_alu~12_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datac(\z80_|execute_|ctl_sw_2d~4_combout ), - .datad(\z80_|execute_|ctl_flags_alu~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_alu_op_low~15_combout & (\z80_|execute_|ctl_sw_4u~1_combout & \z80_|execute_|ctl_flags_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|execute_|ctl_flags_alu~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~15_combout = ((\z80_|execute_|ctl_flags_alu~8_combout ) # ((!\z80_|execute_|ctl_flags_alu~11_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_alu~8_combout ), - .datac(\z80_|execute_|ctl_flags_alu~14_combout ), - .datad(\z80_|execute_|ctl_flags_alu~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N12 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFCEC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~19_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ) # ((\z80_|alu_control_|db[1]~26_combout & \z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), - .datac(\z80_|alu_control_|db[1]~26_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEEE; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X37_Y9_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( +cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( // Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|execute_|ctl_flags_alu~15_combout & \z80_|alu_|db_high[3]~8_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) +// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFFB3; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'h3070; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .lut_mask = 16'h0800; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) - - .dataa(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .lut_mask = 16'hD850; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y9_N27 -dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) # (!\z80_|sequencer_|DFFE_M2_ff~q & -// (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'h7707; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = ((\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'hB3BB; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~11_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~18_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~15_combout & \z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .lut_mask = 16'hFDF5; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal13~2_combout & \z80_|sequencer_|DFFE_M3_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~1 ( -// Equation(s): -// \z80_|alu_|alu_op2[1]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [1])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [1]))))) - - .dataa(\z80_|alu_|op2_high [1]), - .datab(\z80_|alu_|op2_low [1]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[1]~1 .lut_mask = 16'h5A3C; -defparam \z80_|alu_|alu_op2[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high -// [1]))))) - - .dataa(\z80_|alu_|alu_op2[1]~1_combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h1015; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~9_combout = (((\z80_|pla_decode_|Equal71~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_core_S~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), - .datad(\z80_|pla_decode_|Equal71~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout = (\z80_|alu_|db_high[0]~26_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|alu_|db_low[0]~23_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # -// (!\z80_|alu_|db_high[0]~26_combout & (\z80_|alu_|db_low[0]~23_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout ))) - - .dataa(\z80_|alu_|db_high[0]~26_combout ), - .datab(\z80_|alu_|db_low[0]~23_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .lut_mask = 16'hEAC0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) - - .dataa(gnd), + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N7 -dffeas \z80_|alu_|op2_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( -// Equation(s): -// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|alu_|op2_high [0]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h3C5A; -defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~12 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & ((\z80_|ir_|opcode [3]) # ((!\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal62~2_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .lut_mask = 16'hB0F0; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & \z80_|execute_|ctl_alu_core_S~7_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~9_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # -// (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h37FF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_alu_core_hf~20_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .datac(gnd), .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .combout(\z80_|execute_|ixy_d~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( +// Location: LCCOMB_X36_Y6_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 ( // Equation(s): -// \z80_|execute_|ctl_alu_core_hf~22_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~21_combout )) # (!\z80_|execute_|ctl_alu_core_hf~18_combout ) +// \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal0~0_combout & (\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [1]))) - .dataa(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal0~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'hD5FF; -defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( +// Location: LCCOMB_X36_Y6_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( // Equation(s): -// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hA0E0; -defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (((\z80_|execute_|ctl_alu_op_low~22_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~29_combout = (\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~23_combout = (\z80_|execute_|ctl_alu_core_hf~22_combout & (((\z80_|execute_|ctl_alu_core_hf~19_combout & !\z80_|execute_|ctl_alu_op_low~29_combout )) # (!\z80_|execute_|ctl_alu_op_low~28_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~22_combout & (\z80_|execute_|ctl_alu_core_hf~19_combout & (!\z80_|execute_|ctl_alu_op_low~29_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h0CAE; -defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|pla_decode_|Equal39~0_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal40~1_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hFF30; -defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~25_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'hEFEE; -defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'hA0A8; -defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~26_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hDFCC; -defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~28_combout = (\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_alu_op_low~20_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h22F2; -defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (((\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datab(\z80_|execute_|ctl_state_alu~13_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout & !\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~7_combout & -// ((!\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hC0CA; -defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~43_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|ctl_mRead~6_combout & (\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # -// ((\z80_|execute_|ctl_mRead~6_combout & \z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~43 .lut_mask = 16'hD5C0; -defparam \z80_|execute_|ctl_alu_core_hf~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~33_combout = (!\z80_|execute_|ctl_alu_core_hf~43_combout & ((\z80_|execute_|ctl_alu_core_hf~32_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~32_combout & (\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'h00E8; -defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~42 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~42_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~42 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_alu_core_hf~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~42_combout & ((\z80_|execute_|ctl_alu_core_hf~34_combout ) # (\z80_|execute_|ctl_alu_core_hf~33_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~41_combout = (!\z80_|execute_|ctl_state_alu~4_combout & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal10~0_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~41 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_alu_core_hf~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & -// (\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~10_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal11~1_combout & \z80_|execute_|ctl_mWrite~2_combout ))) +// \z80_|pla_decode_|Equal33~0_combout = (\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0])) .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal11~1_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~31_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_mWrite~10_combout & ((\z80_|execute_|ctl_alu_core_hf~41_combout ) # (\z80_|execute_|ctl_alu_core_hf~30_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~41_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'h0054; -defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~44_combout = (\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~44 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_core_hf~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~29_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & ((\z80_|execute_|ctl_alu_core_hf~44_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~44_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'h0E0A; -defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # ((!\z80_|execute_|ctl_alu_op_low~30_combout & \z80_|execute_|ctl_alu_core_hf~35_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'hFFF4; -defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~39_combout = (\z80_|execute_|ctl_alu_core_hf~28_combout ) # ((\z80_|execute_|ctl_alu_core_hf~36_combout ) # ((\z80_|execute_|ctl_alu_core_hf~38_combout & !\z80_|execute_|ctl_alu_op_low~24_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~39 .lut_mask = 16'hFCFE; -defparam \z80_|execute_|ctl_alu_core_hf~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~40_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((\z80_|execute_|ctl_alu_core_hf~39_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~40 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_alu_core_hf~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datad(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~combout = (\z80_|execute_|ctl_alu_core_R~2_combout ) # (((\z80_|pla_decode_|Equal73~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_R~2_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .lut_mask = 16'hC0D0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_high[3]~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), - .datad(\z80_|alu_|db_high[3]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .lut_mask = 16'h5450; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N9 -dffeas \z80_|alu_|op2_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [3]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ) # ((\z80_|alu_|db_low[3]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), - .datac(\z80_|alu_|db_low[3]~25_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N19 -dffeas \z80_|alu_|op2_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~2 ( -// Equation(s): -// \z80_|alu_|alu_op2[3]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [3])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [3]))))) - - .dataa(\z80_|alu_|op2_high [3]), - .datab(\z80_|alu_|op2_low [3]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[3]~2 .lut_mask = 16'h5A3C; -defparam \z80_|alu_|alu_op2[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[3]~3_combout & \z80_|alu_|alu_op2[3]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|alu_|alu_op1[3]~3_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datac(\z80_|alu_|alu_op2[3]~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [3])))) - - .dataa(\z80_|alu_|alu_op2[3]~2_combout ), - .datab(\z80_|alu_|op1_high [3]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0511; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_R~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hAFAE; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # -// (!\z80_|execute_|ctl_flags_bus~combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'h8F88; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((\z80_|pla_decode_|Equal10~0_combout & -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hFC88; -defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~14_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~14_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) - - .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datad(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hCCE4; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N7 -dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|pla_decode_|Equal52~1_combout ) # (\z80_|execute_|ctl_state_alu~14_combout )) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~12_combout = ((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_alu_op_low~12_combout ))) # (!\z80_|execute_|ctl_flags_hf_cpl~10_combout ) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .datab(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~13_combout = (\z80_|execute_|ctl_flags_hf_cpl~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|alu_flags_|DFFE_inst_latch_nf~q ))) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~13 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_hf_cpl~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N8 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( -// Equation(s): -// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~13_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h559A; -defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N30 -cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( -// Equation(s): -// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~40_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~40_combout & (\z80_|alu_flags_|flags_cf~combout )) - - .dataa(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .datab(\z80_|alu_flags_|flags_cf~combout ), + .datab(\z80_|ir_|opcode [1]), .datac(gnd), - .datad(\z80_|alu_flags_|flags_hf~combout ), + .datad(\z80_|ir_|opcode [0]), .cin(gnd), - .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .combout(\z80_|pla_decode_|Equal33~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hEE44; -defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_control_|alu_core_cf_in~0_combout & \z80_|alu_|alu_op1[0]~1_combout )))) -// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|alu_|alu_op1[0]~1_combout )))) - - .dataa(\z80_|alu_|alu_op2[0]~3_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op1[0]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( -// Equation(s): -// \z80_|alu_|db_high[0]~23_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~25_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[3]~11_combout ), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hE4E4; -defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( -// Equation(s): -// \z80_|address_latch_|abusz [12] = (\z80_|reg_file_|db_hi_as[4]~18_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [12]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|Q[12]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[12]~feeder_combout = \z80_|address_latch_|abusz [12] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [12]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[12]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[12]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[12]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N15 -dffeas \z80_|address_latch_|Q[12] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[12]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ -// (\z80_|address_latch_|Q [11]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hD278; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~16 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~16_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~16 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|db_hi_as[4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~17 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~17_combout = (\z80_|reg_file_|db_hi_as[4]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .datad(\z80_|reg_file_|db_hi_as[4]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~17 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|db_hi_as[4]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~18 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~18_combout = ((\z80_|reg_file_|db_hi_as[4]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[4]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~18 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[4]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N11 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~62_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [4] & ((\z80_|alu_|db[4]~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~12_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[4]~17_combout )) # (!\z80_|execute_|ctl_reg_in_hi~12_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .datad(\z80_|alu_|db[4]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~62 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y11_N29 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~63_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~63 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[4]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N23 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~61_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~61 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp1[4]~66_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~60_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~60 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~64_combout = (\z80_|reg_file_|gdfx_temp1[4]~62_combout & (\z80_|reg_file_|gdfx_temp1[4]~63_combout & (\z80_|reg_file_|gdfx_temp1[4]~61_combout & \z80_|reg_file_|gdfx_temp1[4]~60_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~64 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~59 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~58 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~65_combout = (\z80_|reg_file_|gdfx_temp1[4]~64_combout & (\z80_|reg_file_|gdfx_temp1[4]~59_combout & (\z80_|reg_file_|gdfx_temp1[4]~58_combout & \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~65 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~66_combout = ((\z80_|reg_file_|gdfx_temp1[4]~65_combout & ((\z80_|reg_file_|db_hi_as[4]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~66 .lut_mask = 16'hD5F5; -defparam \z80_|reg_file_|gdfx_temp1[4]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db[4]~16 ( -// Equation(s): -// \z80_|alu_|db[4]~16_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[4]~32_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[4]~32_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~16 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|db[7]~26 ( -// Equation(s): -// \z80_|alu_|db[7]~26_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout ) # ((\z80_|execute_|ctl_alu_oe~13_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_alu_oe~13_combout ), - .datac(\z80_|execute_|ctl_alu_oe~9_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~26 .lut_mask = 16'hFFEF; -defparam \z80_|alu_|db[7]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db[4]~17 ( -// Equation(s): -// \z80_|alu_|db[4]~17_combout = ((\z80_|alu_|db[4]~16_combout & ((\z80_|alu_|db_high[0]~26_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[4]~16_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db_high[0]~26_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~17 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[4]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & \z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h00C8; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~6_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( -// Equation(s): -// \z80_|alu_|db_high[0]~24_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[0]~23_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[4]~17_combout ))) - - .dataa(\z80_|alu_|db_high[0]~23_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[4]~17_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hAAF0; -defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( -// Equation(s): -// \z80_|alu_|db_high[0]~21_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'h5575; -defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|alu_|db_high[0]~26_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[0]~26_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N21 -dffeas \z80_|alu_|op1_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( -// Equation(s): -// \z80_|alu_|db_high[0]~22_combout = (\z80_|alu_|op1_high [0] & (((\z80_|alu_|op2_high [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [0] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [0]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [0]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( -// Equation(s): -// \z80_|alu_|db_high[0]~25_combout = (\z80_|alu_|db_high[0]~21_combout & (\z80_|alu_|db_high[0]~22_combout & ((\z80_|alu_|db_high[0]~24_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[0]~24_combout ), - .datab(\z80_|alu_|db_high[0]~21_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[0]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'h8C00; -defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~26 ( -// Equation(s): -// \z80_|alu_|db_high[0]~26_combout = ((\z80_|alu_|db_high[0]~25_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|db_high[0]~25_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~26 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|db_low[0]~23_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) # -// (!\z80_|alu_|db_low[0]~23_combout & (((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) - - .dataa(\z80_|alu_|db_low[0]~23_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datad(\z80_|alu_|db_high[0]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFEFE; -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N31 -dffeas \z80_|alu_|op1_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( -// Equation(s): -// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [0]))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_low [0]), - .datac(\z80_|alu_|op1_high [0]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|alu_|alu_op1[0]~1_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[0]~23_combout )))) # -// (!\z80_|alu_|alu_op1[0]~1_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & ((\z80_|alu_|db_low[0]~23_combout )))) - - .dataa(\z80_|alu_|alu_op1[0]~1_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_low[0]~23_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h5050; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N15 -dffeas \z80_|alu_|op2_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(gnd), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hF0AA; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op1[0]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hF660; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~9_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & -// \z80_|execute_|ctl_alu_core_S~8_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hF1F0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op1[1]~0 ( -// Equation(s): -// \z80_|alu_|alu_op1[1]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(gnd), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[1]~0 .lut_mask = 16'hDD88; -defparam \z80_|alu_|alu_op1[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[1]~0_combout & \z80_|alu_|alu_op2[1]~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datac(\z80_|alu_|alu_op1[1]~0_combout ), - .datad(\z80_|alu_|alu_op2[1]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hFBBB; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # -// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h0F01; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op1[2]~2 ( -// Equation(s): -// \z80_|alu_|alu_op1[2]~2_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(gnd), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[2]~2 .lut_mask = 16'hEE22; -defparam \z80_|alu_|alu_op1[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op2[2]~0_combout & \z80_|alu_|alu_op1[2]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|alu_|alu_op2[2]~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datac(\z80_|alu_|alu_op1[2]~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hFF0B; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & \z80_|execute_|ctl_alu_core_S~8_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .lut_mask = 16'h5F5D; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op1[3]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & -// \z80_|alu_|alu_op2[3]~2_combout )))) # (!\z80_|alu_|alu_op1[3]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[3]~2_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) - - .dataa(\z80_|alu_|alu_op1[3]~3_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|alu_op2[3]~2_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'hFB20; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp1[7]~75_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~69_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~69 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[7]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~70 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~72_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~72 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[7]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~71_combout = (\z80_|alu_|db[7]~21_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[7]~21_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~71 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[7]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~73_combout = (\z80_|reg_file_|gdfx_temp1[7]~69_combout & (\z80_|reg_file_|gdfx_temp1[7]~70_combout & (\z80_|reg_file_|gdfx_temp1[7]~72_combout & \z80_|reg_file_|gdfx_temp1[7]~71_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~73 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~67 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[7]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~68 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~74_combout = (\z80_|reg_file_|gdfx_temp1[7]~73_combout & (\z80_|reg_file_|gdfx_temp1[7]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout & \z80_|reg_file_|gdfx_temp1[7]~68_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~74 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~19 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~75_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~75_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~19 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[7]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~20 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~20_combout = (\z80_|reg_file_|db_hi_as[7]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[7]~19_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~20 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|db_hi_as[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [12] & -// !\z80_|address_latch_|Q [11])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [12] & \z80_|address_latch_|Q [11])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~54 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[5]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~53_combout = (\z80_|alu_|db[5]~25_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[5]~25_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[5]~25_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~53 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[5]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~57_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~51_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~51 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[5]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N11 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~52_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~52 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[5]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~55_combout = (\z80_|reg_file_|gdfx_temp1[5]~54_combout & (\z80_|reg_file_|gdfx_temp1[5]~53_combout & (\z80_|reg_file_|gdfx_temp1[5]~51_combout & \z80_|reg_file_|gdfx_temp1[5]~52_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~55 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~49 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~50 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[5]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~56_combout = (\z80_|reg_file_|gdfx_temp1[5]~55_combout & (\z80_|reg_file_|gdfx_temp1[5]~49_combout & (\z80_|reg_file_|gdfx_temp1[5]~50_combout & \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~56 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~57_combout = ((\z80_|reg_file_|gdfx_temp1[5]~56_combout & ((\z80_|reg_file_|db_hi_as[5]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), - .datac(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~57 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~13 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~13_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[5]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~14 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~14_combout = (\z80_|reg_file_|db_hi_as[5]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|db_hi_as[5]~13_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~14 .lut_mask = 16'hC4C4; -defparam \z80_|reg_file_|db_hi_as[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~15 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~15_combout = ((\z80_|reg_file_|db_hi_as[5]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[5]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~15 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[5]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( -// Equation(s): -// \z80_|address_latch_|abusz [13] = (\z80_|reg_file_|db_hi_as[5]~15_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [13]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|Q[13]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[13]~feeder_combout = \z80_|address_latch_|abusz [13] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [13]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[13]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[13]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N23 -dffeas \z80_|address_latch_|Q[13] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[13]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|execute_|ctl_inc_dec~11_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( -// Equation(s): -// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~21_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N27 -dffeas \z80_|address_latch_|Q[15] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [15]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [13]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [14]), - .datad(\z80_|execute_|ctl_inc_dec~11_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'hB478; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~76 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~80_combout = (\z80_|alu_|db[6]~23_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[6]~23_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[6]~23_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~80 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N17 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~79_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~79 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~78 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~81 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~82_combout = (\z80_|reg_file_|gdfx_temp1[6]~80_combout & (\z80_|reg_file_|gdfx_temp1[6]~79_combout & (\z80_|reg_file_|gdfx_temp1[6]~78_combout & \z80_|reg_file_|gdfx_temp1[6]~81_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~82 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~77 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~83_combout = (\z80_|reg_file_|gdfx_temp1[6]~76_combout & (\z80_|reg_file_|gdfx_temp1[6]~82_combout & (\z80_|reg_file_|gdfx_temp1[6]~77_combout & \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~83 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~84_combout = ((\z80_|reg_file_|gdfx_temp1[6]~83_combout & ((\z80_|reg_file_|db_hi_as[6]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), - .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~84 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~22 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~22_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~22 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~23 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~23_combout = (\z80_|reg_file_|db_hi_as[6]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .datab(\z80_|reg_file_|db_hi_as[6]~22_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~23 .lut_mask = 16'h88CC; -defparam \z80_|reg_file_|db_hi_as[6]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~24 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~24_combout = ((\z80_|reg_file_|db_hi_as[6]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_file_|db_hi_as[6]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~24 .lut_mask = 16'hBF33; -defparam \z80_|reg_file_|db_hi_as[6]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( -// Equation(s): -// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~24_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|Q[14]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[14]~feeder_combout = \z80_|address_latch_|abusz [14] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [14]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[14]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[14]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N5 -dffeas \z80_|address_latch_|Q[14] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[14]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|address_latch_|Q [14]), - .datac(\z80_|execute_|ctl_inc_dec~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h3363; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~21 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~21_combout = ((\z80_|reg_file_|db_hi_as[7]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[7]~20_combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~21 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_hi_as[7]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~75_combout = ((\z80_|reg_file_|gdfx_temp1[7]~74_combout & ((\z80_|reg_file_|db_hi_as[7]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), - .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~75 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[7]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( -// Equation(s): -// \z80_|alu_|db[7]~20_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[7]~75_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .datad(\z80_|alu_control_|db[7]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db[7]~21 ( -// Equation(s): -// \z80_|alu_|db[7]~21_combout = ((\z80_|alu_|db[7]~20_combout & ((\z80_|alu_|db_high[3]~8_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[7]~20_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~21 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[7]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N22 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (\z80_|alu_|db[7]~21_combout & ((\z80_|ir_|opcode [3])))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & -// (\z80_|alu_|db[7]~21_combout )))) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hB822; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (\z80_|alu_control_|db[0]~12_combout & (\z80_|execute_|ctl_flags_bus~combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & -// ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[0]~12_combout & \z80_|execute_|ctl_flags_bus~combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datab(\z80_|alu_control_|db[0]~12_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'hD5C0; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hF4FC; -defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~6_combout = ((\z80_|execute_|ctl_flags_cf_we~5_combout ) # ((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~2 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_flags_cf2_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~4_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal10~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'hE000; -defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~3_combout = (\z80_|execute_|ctl_flags_cf2_we~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|ixy_d~15_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_flags_cf2_we~2_combout ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_flags_cf2_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~3_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0B8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y9_N3 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N0 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h0A88; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N4 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout & !\z80_|ir_|opcode [4])) - - .dataa(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .datac(gnd), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hCCEE; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( -// Equation(s): -// \z80_|alu_|db_high[3]~5_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[6]~23_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .datac(\z80_|alu_|db[6]~23_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( -// Equation(s): -// \z80_|alu_|db_high[3]~6_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[3]~5_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[7]~21_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(\z80_|alu_|db_high[3]~5_combout ), - .datac(\z80_|alu_|db[7]~21_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( -// Equation(s): -// \z80_|alu_|db_high[3]~4_combout = (\z80_|alu_|op2_high [3] & (((\z80_|alu_|op1_high [3])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_high [3] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [3]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_high [3]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_high [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~27 ( -// Equation(s): -// \z80_|alu_|db_high[3]~27_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~27 .lut_mask = 16'hD555; -defparam \z80_|alu_|db_high[3]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( -// Equation(s): -// \z80_|alu_|db_high[3]~7_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~27_combout & ((\z80_|alu_|db_high[3]~6_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[3]~6_combout ), - .datab(\z80_|alu_|db_high[3]~4_combout ), - .datac(\z80_|alu_|db_high[3]~27_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'h80C0; -defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~8 ( -// Equation(s): -// \z80_|alu_|db_high[3]~8_combout = ((\z80_|alu_|db_high[3]~7_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|db_high[3]~7_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~8 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[3]~8_combout )))) - - .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N15 -dffeas \z80_|alu_|op1_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~9 ( -// Equation(s): -// \z80_|alu_|db_low[3]~9_combout = (\z80_|alu_|op1_low [3] & (((\z80_|alu_|op2_low [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_low [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [3]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_low [3]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_low [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~9 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_low[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[4]~19_combout & \z80_|bus_control_|db[3]~21_combout ) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hCC00; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~10 ( -// Equation(s): -// \z80_|alu_|db_low[3]~10_combout = (\z80_|alu_|db_low[3]~9_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|bus_control_|db[5]~15_combout ), - .datab(\z80_|alu_|db_low[3]~9_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~10 .lut_mask = 16'h4C0C; -defparam \z80_|alu_|db_low[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N15 -dffeas \z80_|alu_|result_lo[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~7 ( -// Equation(s): -// \z80_|alu_|db_low[3]~7_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~17_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) - - .dataa(\z80_|alu_|db[4]~17_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[2]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~7 .lut_mask = 16'hAFA0; -defparam \z80_|alu_|db_low[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~8 ( -// Equation(s): -// \z80_|alu_|db_low[3]~8_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~7_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~11_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_low[3]~7_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~8 .lut_mask = 16'hF3BB; -defparam \z80_|alu_|db_low[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~11 ( -// Equation(s): -// \z80_|alu_|db_low[3]~11_combout = (\z80_|alu_|db_low[3]~10_combout & (\z80_|alu_|db_low[3]~8_combout & ((\z80_|alu_|result_lo [3]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[3]~10_combout ), - .datab(\z80_|alu_|result_lo [3]), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_low[3]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~11 .lut_mask = 16'hA800; -defparam \z80_|alu_|db_low[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~25 ( -// Equation(s): -// \z80_|alu_|db_low[3]~25_combout = (\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|alu_|db_low[3]~11_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~25 .lut_mask = 16'hF1F1; -defparam \z80_|alu_|db_low[3]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N12 -cycloneive_lcell_comb \z80_|alu_|db[3]~10 ( -// Equation(s): -// \z80_|alu_|db[3]~10_combout = (\z80_|execute_|ctl_alu_oe~14_combout & (\z80_|alu_|db_low[3]~25_combout & ((\z80_|reg_file_|gdfx_temp1[3]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_alu_oe~14_combout & -// (((\z80_|reg_file_|gdfx_temp1[3]~48_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .datad(\z80_|alu_|db_low[3]~25_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~10 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|db[3]~11 ( -// Equation(s): -// \z80_|alu_|db[3]~11_combout = ((\z80_|alu_|db[3]~10_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[3]~10_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[3]~35_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~11 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_alu_oe~9_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~3_combout ), - .datac(\z80_|execute_|ctl_alu_oe~9_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~49 ( -// Equation(s): -// \z80_|execute_|setM1~49_combout = (\z80_|execute_|setM1~48_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~49 .lut_mask = 16'h0070; -defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~14_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~49_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|setM1~49_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h0B0F; -defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|alu_|db_low[3]~25_combout & ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[3]~35_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_low[3]~25_combout & -// (\z80_|alu_control_|db[3]~35_combout & (\z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|alu_|db_low[3]~25_combout ), - .datab(\z80_|alu_control_|db[3]~35_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hEAC0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout = (\z80_|pla_decode_|Equal56~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # ((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # -// (!\z80_|execute_|ctl_flags_xy_we~10_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~14_combout = (((\z80_|execute_|ctl_flags_xy_we~13_combout ) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) - - .dataa(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~15_combout = (((\z80_|execute_|ctl_flags_xy_we~14_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N31 -dffeas \z80_|alu_flags_|flags_xf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_xf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_xf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( -// Equation(s): -// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_flags_|flags_xf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hF030; -defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFEFA; -defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|execute_|ixy_d~7_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFAEA; -defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N16 -cycloneive_lcell_comb \z80_|sw1_|db_down[3]~1 ( -// Equation(s): -// \z80_|sw1_|db_down[3]~1_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[3]~1 .lut_mask = 16'hFF8C; -defparam \z80_|sw1_|db_down[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( -// Equation(s): -// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & (\z80_|sw1_|db_down[3]~1_combout & ((\z80_|reg_file_|gdfx_temp0[3]~52_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datab(\z80_|alu_control_|db[3]~33_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|sw1_|db_down[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'h8C00; -defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( -// Equation(s): -// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~11_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[3]~34_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hBF33; -defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [3] & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[3]~35_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .datad(\z80_|alu_control_|db[3]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|gdfx_temp0[3]~46_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .datab(gnd), - .datac(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~49_combout & \z80_|reg_file_|gdfx_temp0[3]~47_combout )) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N31 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N5 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~51_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & (\z80_|reg_file_|gdfx_temp0[3]~50_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~52_combout = ((\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp0[3]~52_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[3]~52_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hAA0A; -defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( -// Equation(s): -// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [3]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h3030; -defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N17 -dffeas \z80_|address_latch_|Q[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [3]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout = \z80_|address_latch_|Q [3] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .lut_mask = 16'h40BF; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout )))) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h6AAA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|gdfx_temp0[4]~53_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|alu_control_|db[4]~32_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hBB00; -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N27 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N1 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~58_combout & (\z80_|reg_file_|gdfx_temp0[4]~59_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'hA200; -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N21 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N11 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N1 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N7 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|gdfx_temp0[4]~55_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~61_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & (\z80_|reg_file_|gdfx_temp0[4]~60_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & \z80_|reg_file_|gdfx_temp0[4]~56_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~62_combout = ((\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|reg_file_|gdfx_temp0[4]~62_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[4]~62_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hCC0C; -defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N16 -cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( -// Equation(s): -// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~15_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [4]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h3300; -defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N23 -dffeas \z80_|address_latch_|Q[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [4]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|address_latch_|Q [4]), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout -// ))) - - .dataa(\z80_|address_latch_|Q [5]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h6A6A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N23 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N13 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N21 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N5 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [5] & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[5]~15_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .datad(\z80_|alu_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|gdfx_temp0[5]~66_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .datad(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N3 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~67_combout & (\z80_|reg_file_|gdfx_temp0[5]~65_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~68_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~71_combout = (\z80_|reg_file_|gdfx_temp0[5]~64_combout & (\z80_|reg_file_|gdfx_temp0[5]~63_combout & \z80_|reg_file_|gdfx_temp0[5]~70_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~72_combout = ((\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .lut_mask = 16'hD5F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|reg_file_|gdfx_temp0[5]~72_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[5]~72_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'hF050; -defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( -// Equation(s): -// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~18_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [5]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N27 -dffeas \z80_|address_latch_|Q[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [5]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N26 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout = \z80_|address_latch_|Q [5] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout ))) - - .dataa(\z80_|address_latch_|Q [5]), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .lut_mask = 16'h5595; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N17 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N7 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N19 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N5 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N3 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[6]~22_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|gdfx_temp0[6]~76_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~78_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & \z80_|reg_file_|gdfx_temp0[6]~77_combout )) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N5 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~74_combout & (\z80_|reg_file_|gdfx_temp0[6]~73_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & \z80_|reg_file_|gdfx_temp0[6]~75_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[6]~82_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .datad(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( -// Equation(s): -// \z80_|address_latch_|abusz [6] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[6]~21_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N23 -dffeas \z80_|address_latch_|Q[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [6]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # (\z80_|execute_|ctl_inc_dec~7_combout ))))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h001E; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h55AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'hF575; -defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N25 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N29 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N19 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N11 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~92_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|gdfx_temp0[7]~86_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .datad(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[7]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & \z80_|reg_file_|gdfx_temp0[7]~89_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~91_combout = (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~84_combout & \z80_|reg_file_|gdfx_temp0[7]~90_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~92 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~92_combout = ((\z80_|reg_file_|gdfx_temp0[7]~91_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[7]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[7]~0_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[7]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[7]~0 .lut_mask = 16'hF0F8; -defparam \z80_|reg_file_|db_lo_ds[7]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N11 -dffeas \z80_|interrupts_|im2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~12_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|interrupts_|im2~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h5000; -defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|execute_|ctl_mRead~12_combout & \z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~17 ( -// Equation(s): -// \z80_|alu_control_|db[7]~17_combout = (\z80_|reg_file_|db_lo_ds[7]~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|reg_file_|db_lo_ds[7]~0_combout ), - .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|bus_control_|db[7]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~17 .lut_mask = 16'h2A0A; -defparam \z80_|alu_control_|db[7]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~16 ( -// Equation(s): -// \z80_|alu_control_|db[7]~16_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[7]~21_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (\z80_|execute_|ctl_sw_2u~7_combout & (!\z80_|alu_|db[7]~21_combout ))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_|db[7]~21_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~16 .lut_mask = 16'h0CAE; -defparam \z80_|alu_control_|db[7]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( -// Equation(s): -// \z80_|alu_control_|db[7]~18_combout = ((\z80_|alu_control_|db[7]~17_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & !\z80_|alu_control_|db[7]~16_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[7]~17_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_control_|db[7]~16_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h33B3; -defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[7]~18_combout ) # ((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout -// & (((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[7]~18_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~7_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~3_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y9_N9 -dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'h008C; -defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h0088; +defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X37_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( // Equation(s): -// \z80_|execute_|ctl_flags_pf_we~8_combout = (((\z80_|execute_|ctl_flags_pf_we~5_combout ) # (\z80_|execute_|ctl_flags_pf_we~7_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ) - - .dataa(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # ((!\z80_|execute_|ctl_pf_sel[0]~3_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~11_combout ) - - .dataa(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|execute_|ctl_flags_bus~combout & (\z80_|alu_control_|db[2]~29_combout ))) # (!\z80_|execute_|ctl_flags_pf_we~9_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[2]~29_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'h88F0; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (((!\z80_|pla_decode_|Equal62~3_combout & !\z80_|execute_|ctl_alu_op_low~13_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h3070; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ))))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h152A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h3B00; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N24 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [14] & (!\z80_|address_latch_|Q [12] & (!\z80_|address_latch_|Q [15] & !\z80_|address_latch_|Q [13]))) - - .dataa(\z80_|address_latch_|Q [14]), - .datab(\z80_|address_latch_|Q [12]), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|Q [13]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N16 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~3_combout = (!\z80_|address_latch_|Q [1] & (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [3] & !\z80_|address_latch_|Q [2]))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|address_latch_|Q [0]), - .datac(\z80_|address_latch_|Q [3]), - .datad(\z80_|address_latch_|Q [2]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0004; -defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N14 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [6] & (!\z80_|address_latch_|Q [5] & !\z80_|address_latch_|Q [4]))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [6]), - .datac(\z80_|address_latch_|Q [5]), - .datad(\z80_|address_latch_|Q [4]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N8 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [11] & (!\z80_|address_latch_|Q [9] & !\z80_|address_latch_|Q [8]))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [11]), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|Q [8]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N18 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~0_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & (\z80_|decode_state_|DFFE_instNonRep~2_combout & \z80_|decode_state_|DFFE_instNonRep~1_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instNonRep~0_combout ), - .datab(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; -defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N16 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~9_combout & -// ((\z80_|decode_state_|DFFE_instNonRep~4_combout ))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|decode_state_|DFFE_instNonRep~q )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~q ), - .datad(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hF4B0; -defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y16_N17 -dffeas \z80_|decode_state_|DFFE_instNonRep ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instNonRep~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N12 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|pla_decode_|Equal62~3_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h0040; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & -// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - - .dataa(\z80_|interrupts_|DFFE_instIFF2~q ), - .datab(\z80_|decode_state_|DFFE_instNonRep~q ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'hA030; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout & -// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'h808C; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N23 -dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|alu_parity_out~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55FD; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & -// \z80_|alu_|alu_op1[1]~0_combout )))) # (!\z80_|alu_|alu_op2[1]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[1]~0_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[1]~1_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|alu_|alu_op1[1]~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'hFB20; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( -// Equation(s): -// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'hA55A; -defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( -// Equation(s): -// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout $ (\z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .datad(\z80_|alu_|alu_parity_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out .lut_mask = 16'hA956; -defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'hFFEF; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h20A0; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_|alu_parity_out~combout & \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .datac(\z80_|alu_|alu_parity_out~combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFEEE; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout & \z80_|execute_|ctl_flags_alu~15_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'hECCC; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N15 -dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( -// Equation(s): -// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal40~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ))) +// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal40~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|sel[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h70F0; -defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout = (!\z80_|alu_|db_high[1]~20_combout & (!\z80_|alu_|db_high[3]~8_combout & (!\z80_|alu_|db_high[2]~14_combout & !\z80_|alu_|db_high[0]~26_combout ))) - - .dataa(\z80_|alu_|db_high[1]~20_combout ), - .datab(\z80_|alu_|db_high[3]~8_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|alu_|db_high[0]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .lut_mask = 16'h0001; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout = (\z80_|alu_control_|db[6]~22_combout & \z80_|execute_|ctl_flags_bus~combout ) - - .dataa(\z80_|alu_control_|db[6]~22_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .lut_mask = 16'hAA00; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N14 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[3]~11_combout & (\z80_|alu_|db_high[3]~3_combout & ((!\z80_|alu_|db_low[2]~3_combout ) # (!\z80_|alu_|db_low[2]~6_combout )))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|alu_|db_low[2]~3_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h1300; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_low[1]~17_combout & (\z80_|execute_|ctl_flags_alu~15_combout & (!\z80_|alu_|db_low[0]~23_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_flags_alu~15_combout ), - .datac(\z80_|alu_|db_low[0]~23_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0400; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hF7FF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hEC00; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y13_N27 -dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|alu_control_|sel[1]~0_combout & (((\z80_|ir_|opcode [4])))) # (!\z80_|alu_control_|sel[1]~0_combout & ((\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ))) # (!\z80_|ir_|opcode [4] -// & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(\z80_|alu_control_|sel[1]~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hFC0A; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & (\z80_|alu_flags_|DFFE_inst_latch_sf~q )) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_pf~q ))))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datac(\z80_|alu_control_|sel[1]~0_combout ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hAFC0; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( -// Equation(s): -// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((\z80_|alu_control_|flags_cond_true~q )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|flags_cond_true~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hB874; -defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N21 -dffeas \z80_|alu_control_|flags_cond_true ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_control_|flags_cond_true~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|flags_cond_true~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; -defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~13_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sel_wz~14_combout ) # (((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~11_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|gdfx_temp0[0]~93_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~20_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N23 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X31_Y10_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .datad(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & (((\z80_|alu_control_|db[1]~26_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[1]~26_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N3 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N9 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~28_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & (\z80_|reg_file_|gdfx_temp0[1]~29_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N27 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N25 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~23_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'hF733; -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[1]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[1]~1_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[1]~1 .lut_mask = 16'hF0F8; -defparam \z80_|reg_file_|db_lo_ds[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N30 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( -// Equation(s): -// \z80_|alu_control_|db[1]~25_combout = (\z80_|reg_file_|db_lo_ds[1]~1_combout & (((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[1]~11_combout ), - .datab(\z80_|reg_file_|db_lo_ds[1]~1_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h0C8C; -defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~24 ( -// Equation(s): -// \z80_|alu_control_|db[1]~24_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[1]~13_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (\z80_|execute_|ctl_sw_2u~7_combout & ((!\z80_|alu_|db[1]~13_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_|db[1]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~24 .lut_mask = 16'h0ACE; -defparam \z80_|alu_control_|db[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( -// Equation(s): -// \z80_|alu_control_|db[1]~26_combout = ((\z80_|alu_control_|db[1]~25_combout & (\z80_|alu_control_|db[2]~23_combout & !\z80_|alu_control_|db[1]~24_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[1]~25_combout ), - .datab(\z80_|alu_control_|db[2]~23_combout ), - .datac(\z80_|alu_control_|db[6]~11_combout ), - .datad(\z80_|alu_control_|db[1]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h0F8F; -defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db[1]~12 ( -// Equation(s): -// \z80_|alu_|db[1]~12_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[1]~26_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~12 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db[1]~13 ( -// Equation(s): -// \z80_|alu_|db[1]~13_combout = ((\z80_|alu_|db[1]~12_combout & ((\z80_|alu_|db_low[1]~17_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[1]~12_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_low[1]~17_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~13 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( -// Equation(s): -// \z80_|alu_|db_low[0]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~13_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hF5A0; -defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( -// Equation(s): -// \z80_|alu_|db_low[0]~22_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[0]~21_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[0]~19_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db_low[0]~21_combout ), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~18 ( -// Equation(s): -// \z80_|alu_|db_low[0]~18_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~18 .lut_mask = 16'h5557; -defparam \z80_|alu_|db_low[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~19 ( -// Equation(s): -// \z80_|alu_|db_low[0]~19_combout = (\z80_|alu_|op2_low [0] & (((\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [0]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_low [0]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~19 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_low[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N25 -dffeas \z80_|alu_|result_lo[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~20 ( -// Equation(s): -// \z80_|alu_|db_low[0]~20_combout = (\z80_|alu_|db_low[0]~18_combout & (\z80_|alu_|db_low[0]~19_combout & ((\z80_|alu_|result_lo [0]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[0]~18_combout ), - .datab(\z80_|alu_|db_low[0]~19_combout ), - .datac(\z80_|alu_|result_lo [0]), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~20 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( -// Equation(s): -// \z80_|alu_|db_low[0]~23_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[0]~22_combout & ((\z80_|alu_|db_low[0]~20_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[0]~20_combout ) # -// (!\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|alu_|db_low[0]~22_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_low[0]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'hAF03; -defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( -// Equation(s): -// \z80_|alu_|db[0]~18_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|alu_|db_low[0]~23_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_|db_low[0]~23_combout ) # ((!\z80_|execute_|ctl_alu_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_|db_low[0]~23_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~18 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|db[0]~19 ( -// Equation(s): -// \z80_|alu_|db[0]~19_combout = ((\z80_|alu_|db[0]~18_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[0]~12_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~19 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( -// Equation(s): -// \z80_|alu_|db_low[1]~15_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~19_combout )) - - .dataa(\z80_|alu_|db[0]~19_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[2]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( -// Equation(s): -// \z80_|alu_|db_low[1]~16_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[1]~15_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[1]~13_combout ))) - - .dataa(\z80_|alu_|db_low[1]~15_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hAAF0; -defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( -// Equation(s): -// \z80_|alu_|db_low[1]~12_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'h5755; -defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~13 ( -// Equation(s): -// \z80_|alu_|db_low[1]~13_combout = (\z80_|alu_|op2_low [1] & (((\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [1] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [1]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [1]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~13 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_low[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N21 -dffeas \z80_|alu_|result_lo[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~14 ( -// Equation(s): -// \z80_|alu_|db_low[1]~14_combout = (\z80_|alu_|db_low[1]~12_combout & (\z80_|alu_|db_low[1]~13_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[1]~12_combout ), - .datab(\z80_|alu_|db_low[1]~13_combout ), - .datac(\z80_|alu_|result_lo [1]), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~14 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( -// Equation(s): -// \z80_|alu_|db_low[1]~17_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~16_combout & \z80_|alu_|db_low[1]~14_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~14_combout )) # -// (!\z80_|alu_|db_high[3]~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|alu_|db_low[1]~16_combout ), - .datad(\z80_|alu_|db_low[1]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'hF511; -defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # -// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N1 -dffeas \z80_|alu_|op1_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N28 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( -// Equation(s): -// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [1]) # (\z80_|alu_|op1_low [2]))) - - .dataa(gnd), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hF0C0; -defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0F00; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N8 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( -// Equation(s): -// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & -// (((\z80_|alu_flags_|flags_hf2~q )))) - - .dataa(\z80_|alu_control_|db[4]~32_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .datac(\z80_|alu_flags_|flags_hf2~q ), - .datad(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hEEF0; -defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N9 -dffeas \z80_|alu_flags_|flags_hf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|flags_hf2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_hf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~23 ( -// Equation(s): -// \z80_|alu_control_|db[2]~23_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|alu_flags_|flags_hf2~q ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~combout ), - .datab(\z80_|alu_control_|out[6]~0_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|alu_flags_|flags_hf2~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~23 .lut_mask = 16'hFFEF; -defparam \z80_|alu_control_|db[2]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[2]~2_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[2]~2 .lut_mask = 16'hFF40; -defparam \z80_|reg_file_|db_lo_ds[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( -// Equation(s): -// \z80_|alu_control_|db[2]~28_combout = (\z80_|reg_file_|db_lo_ds[2]~2_combout & (((\z80_|bus_control_|db[2]~13_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[2]~13_combout ), - .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h2F00; -defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~27 ( -// Equation(s): -// \z80_|alu_control_|db[2]~27_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((!\z80_|alu_|db[2]~15_combout & \z80_|execute_|ctl_sw_2u~7_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (!\z80_|alu_|db[2]~15_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|alu_|db[2]~15_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~27 .lut_mask = 16'h3B0A; -defparam \z80_|alu_control_|db[2]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( -// Equation(s): -// \z80_|alu_control_|db[2]~29_combout = ((\z80_|alu_control_|db[2]~23_combout & (\z80_|alu_control_|db[2]~28_combout & !\z80_|alu_control_|db[2]~27_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[2]~23_combout ), - .datac(\z80_|alu_control_|db[2]~28_combout ), - .datad(\z80_|alu_control_|db[2]~27_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h55D5; -defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db[2]~14 ( -// Equation(s): -// \z80_|alu_|db[2]~14_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[2]~39_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[2]~29_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[2]~29_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~14 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[2]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db[2]~15 ( -// Equation(s): -// \z80_|alu_|db[2]~15_combout = ((\z80_|alu_|db[2]~14_combout & ((\z80_|alu_|db_low[2]~24_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_low[2]~24_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[2]~14_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~15 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[2]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N4 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~2 ( -// Equation(s): -// \z80_|alu_|db_low[2]~2_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[1]~13_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[3]~11_combout ), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~2 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|db_low[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~3 ( -// Equation(s): -// \z80_|alu_|db_low[2]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~15_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[2]~15_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_low[2]~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~3 .lut_mask = 16'hF3BB; -defparam \z80_|alu_|db_low[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_high[3]~3_combout ), - .datac(\z80_|alu_|db_low[2]~3_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .lut_mask = 16'hB300; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'h3222; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N25 -dffeas \z80_|alu_|op1_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ) # ((\z80_|alu_|db_low[2]~24_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), - .datac(\z80_|alu_|db_low[2]~24_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N13 -dffeas \z80_|alu_|op2_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~5 ( -// Equation(s): -// \z80_|alu_|db_low[2]~5_combout = (\z80_|alu_|op2_low [2] & ((\z80_|alu_|op1_low [2]) # ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_low [2] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [2]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [2]), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~5 .lut_mask = 16'h8ACF; -defparam \z80_|alu_|db_low[2]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N13 -dffeas \z80_|alu_|result_lo[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~6 ( -// Equation(s): -// \z80_|alu_|db_low[2]~6_combout = (\z80_|alu_|db_low[2]~4_combout & (\z80_|alu_|db_low[2]~5_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [2])))) - - .dataa(\z80_|alu_|db_low[2]~4_combout ), - .datab(\z80_|alu_|db_low[2]~5_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|result_lo [2]), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~6 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[2]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_low[2]~3_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h80F0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N27 -dffeas \z80_|alu_|op2_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~0 ( -// Equation(s): -// \z80_|alu_|alu_op2[2]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) - - .dataa(\z80_|alu_|op2_high [2]), - .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|alu_|op2_low [2]), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[2]~0 .lut_mask = 16'h4B78; -defparam \z80_|alu_|alu_op2[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h0BFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[2]~2_combout & -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|alu_|alu_op2[2]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[2]~2_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[2]~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .datac(\z80_|alu_|alu_op1[2]~2_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hECC8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( -// Equation(s): -// \z80_|alu_|db_high[2]~9_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'h55D5; -defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( -// Equation(s): -// \z80_|alu_|db_high[2]~11_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~21_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~25_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(\z80_|alu_|db[7]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'hFA50; -defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( -// Equation(s): -// \z80_|alu_|db_high[2]~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[2]~11_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[6]~23_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[2]~11_combout ), - .datac(\z80_|alu_|db[6]~23_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( -// Equation(s): -// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [2]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( -// Equation(s): -// \z80_|alu_|db_high[2]~13_combout = (\z80_|alu_|db_high[2]~9_combout & (\z80_|alu_|db_high[2]~10_combout & ((\z80_|alu_|db_high[2]~12_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[2]~9_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[2]~12_combout ), - .datad(\z80_|alu_|db_high[2]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hA200; -defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~14 ( -// Equation(s): -// \z80_|alu_|db_high[2]~14_combout = ((\z80_|alu_|db_high[2]~13_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .datab(\z80_|alu_|db_high[3]~3_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_high[2]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~14 .lut_mask = 16'hFB33; -defparam \z80_|alu_|db_high[2]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( -// Equation(s): -// \z80_|alu_|db[6]~22_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .datad(\z80_|alu_control_|db[6]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db[6]~23 ( -// Equation(s): -// \z80_|alu_|db[6]~23_combout = ((\z80_|alu_|db[6]~22_combout & ((\z80_|alu_|db_high[2]~14_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_high[2]~14_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~23 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[6]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N10 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( -// Equation(s): -// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_|op1_high [0] & \z80_|alu_control_|out[6]~0_combout ))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|alu_|op1_high [0]), - .datac(\z80_|alu_|op1_high [1]), - .datad(\z80_|alu_control_|out[6]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEFA; -defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N26 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( -// Equation(s): -// \z80_|alu_control_|out[6]~2_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) - - .dataa(\z80_|execute_|ctl_66_oe~combout ), - .datab(\z80_|alu_control_|out[6]~1_combout ), - .datac(\z80_|alu_|op1_high [3]), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFFEA; -defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~19 ( -// Equation(s): -// \z80_|alu_control_|db[6]~19_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & -// (!\z80_|execute_|ctl_flags_oe~2_combout & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|out[6]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~19 .lut_mask = 16'hAF8C; -defparam \z80_|alu_control_|db[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~20 ( -// Equation(s): -// \z80_|alu_control_|db[6]~20_combout = (\z80_|alu_control_|db[6]~19_combout & ((\z80_|alu_|db[6]~23_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db[6]~23_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[6]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~20 .lut_mask = 16'hCF00; -defparam \z80_|alu_control_|db[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( -// Equation(s): -// \z80_|alu_control_|db[6]~21_combout = (\z80_|alu_control_|db[6]~20_combout & (((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[6]~9_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|alu_control_|db[6]~20_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'h30B0; -defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( -// Equation(s): -// \z80_|alu_control_|db[6]~22_combout = ((\z80_|alu_control_|db[6]~21_combout & ((\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[6]~21_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'hD5DD; -defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal33~1_combout & ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .combout(\z80_|execute_|ctl_mRead~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'hC800; -defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( +// Location: LCCOMB_X37_Y6_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( // Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[3]~21_combout ) +// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) - .dataa(gnd), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[3]~21_combout ), + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .combout(\z80_|pla_decode_|Equal77~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h00CC; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0100; +defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y10_N9 -dffeas \z80_|interrupts_|im1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( +// Location: LCCOMB_X37_Y12_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( // Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|interrupts_|im1~q ), - .datac(\z80_|interrupts_|im2~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hDC00; -defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & -// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h40EE; -defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N0 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( -// Equation(s): -// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) +// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout )) .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[0]~4_combout ), + .combout(\z80_|pla_decode_|Equal50~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hFF31; -defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N6 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( +// Location: LCCOMB_X40_Y13_N16 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( // Equation(s): -// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) +// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) - .dataa(gnd), - .datab(\z80_|alu_control_|db[6]~22_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[6]~8_combout ), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~37 ( +// Location: LCCOMB_X30_Y11_N20 +cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( // Equation(s): -// \z80_|execute_|ctl_mRead~37_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|sequencer_|DFFE_T5_ff~q ) +// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|interrupts_|DFFE_inst44~q & !\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~37 .lut_mask = 16'hDDDF; -defparam \z80_|execute_|ctl_mRead~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~37_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~37_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ctl_mRead~28_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~28_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_mRead~29_combout & (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & !\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ))) - - .dataa(\z80_|execute_|ctl_mRead~29_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_mRead~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~37 ( -// Equation(s): -// \z80_|execute_|setM1~37_combout = (!\z80_|pla_decode_|Equal9~1_combout & (!\z80_|pla_decode_|Equal29~0_combout & (\z80_|execute_|ctl_al_we~4_combout & \z80_|execute_|ctl_inc_cy~41_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|execute_|ctl_al_we~4_combout ), - .datad(\z80_|execute_|ctl_inc_cy~41_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~37 .lut_mask = 16'h1000; -defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~55 ( -// Equation(s): -// \z80_|execute_|setM1~55_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~55 .lut_mask = 16'h3233; -defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~38 ( -// Equation(s): -// \z80_|execute_|setM1~38_combout = (!\z80_|execute_|ctl_mRead~16_combout & (\z80_|execute_|setM1~37_combout & (\z80_|execute_|setM1~55_combout & \z80_|execute_|setM1~36_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|setM1~37_combout ), - .datac(\z80_|execute_|setM1~55_combout ), - .datad(\z80_|execute_|setM1~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~38 .lut_mask = 16'h4000; -defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~34_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|setM1~38_combout ))) - - .dataa(\z80_|execute_|setM1~38_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~3 ( -// Equation(s): -// \z80_|execute_|nextM~3_combout = (!\z80_|pla_decode_|Equal41~2_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ixy_d~16_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0003; -defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|nextM~3_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_mRead~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|execute_|ctl_mRead~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFC0; -defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~35 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~35_combout = ((\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|execute_|ctl_mRead~31_combout ) # (\z80_|execute_|ctl_mRead~33_combout ))) # (!\z80_|execute_|ctl_mRead~30_combout ) - - .dataa(\z80_|execute_|ctl_mRead~30_combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|ctl_mRead~31_combout ), - .datad(\z80_|execute_|ctl_mRead~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~35 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_mRead~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N23 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mRead~35_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N24 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X46_Y15_N25 -dffeas \z80_|memory_ifc_|wait_mrd ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mrd~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N3 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_mrd~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N8 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & !\z80_|memory_ifc_|DFFE_mrd_ff3~q ) - - .dataa(\z80_|memory_ifc_|wait_mrd~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0055; -defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|nextM~4 ( -// Equation(s): -// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout ) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~4 .lut_mask = 16'h373F; -defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~12_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_iorw~12_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~11_combout & \z80_|execute_|ctl_mWrite~16_combout ))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|nextM~4_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_iorw~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N7 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_iorw~9_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N26 -cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder ( -// Equation(s): -// \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout = \z80_|memory_ifc_|DFFE_iorq_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N27 -dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N9 -dffeas \z80_|memory_ifc_|wait_iorq ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorq~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N13 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorq~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( -// Equation(s): -// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|wait_iorq~q ), - .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|iorq~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; -defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( -// Equation(s): -// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hA800; -defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( -// Equation(s): -// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_alu_op_low~9_combout ) # ((\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|fIOWrite~0_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|fIORead~1_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFFF2; -defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( -// Equation(s): -// \z80_|execute_|fIORead~0_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hA080; -defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( -// Equation(s): -// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|fIOWrite~1_combout ), - .datab(\z80_|execute_|fIORead~2_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|fIORead~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N25 -dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|setM1~52_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_m1_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N14 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( -// Equation(s): -// \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_m1_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N15 -dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N21 -dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_m1_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N20 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|interrupts_|DFFE_inst44~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # (\z80_|memory_ifc_|DFFE_m1_ff3~q )))) # (!\z80_|interrupts_|DFFE_inst44~q & -// ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # ((\z80_|memory_ifc_|DFFE_m1_ff3~q )))) - - .dataa(\z80_|interrupts_|DFFE_inst44~q ), - .datab(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .datac(\z80_|memory_ifc_|DFFE_m1_ff3~q ), + .datac(\z80_|interrupts_|DFFE_inst44~q ), .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~0_combout ), + .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hFC54; -defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0010; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N18 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~2_combout = ((\z80_|memory_ifc_|nRD_out~0_combout ) # ((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIORead~3_combout ))) # (!\z80_|memory_ifc_|nRD_out~1_combout ) - - .dataa(\z80_|memory_ifc_|nRD_out~1_combout ), - .datab(\z80_|memory_ifc_|iorq~0_combout ), - .datac(\z80_|execute_|fIORead~3_combout ), - .datad(\z80_|memory_ifc_|nRD_out~0_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~2_combout ), - .cout()); +// Location: FF_X30_Y11_N21 +dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .prn(vcc)); // synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hFFD5; -defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N24 -cycloneive_lcell_comb \Equal2~1 ( -// Equation(s): -// \Equal2~1_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~1 .lut_mask = 16'h4040; -defparam \Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~0 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~0 .lut_mask = 16'hFFAA; -defparam \z80_|pin_control_|bus_db_pin_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( -// Equation(s): -// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h3F33; -defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( -// Equation(s): -// \z80_|execute_|fMWrite~6_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) - - .dataa(\z80_|execute_|fMWrite~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'h5554; -defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( -// Equation(s): -// \z80_|execute_|fMWrite~2_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h555F; -defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( -// Equation(s): -// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fMWrite~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|fMWrite~2_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h00EF; -defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~1 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~1_combout = (\z80_|execute_|ctl_bus_inc_oe~24_combout & (!\z80_|execute_|fIOWrite~5_combout & (!\z80_|execute_|fMWrite~6_combout & !\z80_|execute_|fMWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .datab(\z80_|execute_|fIOWrite~5_combout ), - .datac(\z80_|execute_|fMWrite~6_combout ), - .datad(\z80_|execute_|fMWrite~4_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~1 .lut_mask = 16'h0002; -defparam \z80_|pin_control_|bus_db_pin_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'h135F; -defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N24 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|pin_control_|bus_db_pin_oe~2_combout & (((\z80_|execute_|ixy_d~4_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'hA2AA; -defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( -// Equation(s): -// \z80_|execute_|fMWrite~7_combout = (!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_mRead~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'h0003; -defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~7_combout ) # ((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|fMWrite~7_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'hCD00; -defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~10_combout & ((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h0777; -defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N4 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|fMRead~1_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout )) # -// (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|fMRead~1_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h3715; -defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|fMWrite~9 ( -// Equation(s): -// \z80_|execute_|fMWrite~9_combout = (\z80_|pla_decode_|Equal46~0_combout ) # (((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout )) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~9 .lut_mask = 16'hCEFF; -defparam \z80_|execute_|fMWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|execute_|fIOWrite~0_combout & ((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) # (!\z80_|execute_|ctl_mWrite~6_combout & -// (((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|fMWrite~2_combout ), - .datad(\z80_|execute_|fMWrite~9_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'hDDD0; -defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N0 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (\z80_|execute_|fMWrite~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout )) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .datab(\z80_|execute_|fMWrite~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h0808; -defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( -// Equation(s): -// \z80_|execute_|fMWrite~8_combout = (\z80_|execute_|ctl_state_alu~6_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & (\z80_|execute_|ctl_reg_sel_wz~5_combout & (!\z80_|execute_|fMWrite~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .datac(\z80_|execute_|fMWrite~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h0800; -defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|pin_control_|bus_db_pin_oe~7_combout & (\z80_|pin_control_|bus_db_pin_oe~6_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~5_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|fMWrite~10 ( -// Equation(s): -// \z80_|execute_|fMWrite~10_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|execute_|ctl_alu_oe~2_combout & -// ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~10 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N0 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|pin_control_|bus_db_pin_oe~10_combout & (!\z80_|execute_|fMWrite~10_combout & \z80_|execute_|ctl_bus_inc_oe~28_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .datac(\z80_|execute_|fMWrite~10_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h0800; -defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~3_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h2A00; -defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (\z80_|pin_control_|bus_db_pin_oe~1_combout & (\z80_|pin_control_|bus_db_pin_oe~12_combout & \z80_|execute_|ctl_inc_cy~37_combout ))) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .datad(\z80_|execute_|ctl_inc_cy~37_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N28 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout ))) # -// (!\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|fIOWrite~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'hF222; -defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N0 +// Location: LCCOMB_X39_Y14_N26 cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( // Equation(s): // \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q @@ -37040,7 +6633,7 @@ defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y15_N1 +// Location: FF_X39_Y14_N27 dffeas \z80_|clk_delay_|DFF_inst5 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), @@ -37059,3754 +6652,96 @@ defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y15_N22 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorqinta~feeder ( +// Location: LCCOMB_X39_Y14_N4 +cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( // Equation(s): -// \z80_|memory_ifc_|wait_iorqinta~feeder_combout = \z80_|clk_delay_|DFF_inst5~q +// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|DFF_inst5~q & !\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ) - .dataa(gnd), + .dataa(\z80_|clk_delay_|DFF_inst5~q ), .datab(gnd), .datac(gnd), - .datad(\z80_|clk_delay_|DFF_inst5~q ), + .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), .cin(gnd), - .combout(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), + .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .sum_lutc_input = "datac"; +defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0055; +defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y15_N23 -dffeas \z80_|memory_ifc_|wait_iorqinta ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), +// Location: FF_X40_Y13_N17 +dffeas \z80_|sequencer_|DFFE_T5_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorqinta~q ), + .q(\z80_|sequencer_|DFFE_T5_ff~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; +defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; // synopsys translate_on -// Location: FF_X43_Y15_N13 -dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Location: LCCOMB_X32_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( // Equation(s): -// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|wait_iorqinta~q ) # ((\z80_|memory_ifc_|DFFE_intr_ff3~q ) # (\z80_|memory_ifc_|iorq~0_combout )) +// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) - .dataa(\z80_|memory_ifc_|wait_iorqinta~q ), - .datab(gnd), - .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .datad(\z80_|memory_ifc_|iorq~0_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFFFA; -defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N18 -cycloneive_lcell_comb \Equal2~0 ( -// Equation(s): -// \Equal2~0_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~0 .lut_mask = 16'h4000; -defparam \Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N22 -cycloneive_lcell_comb \ExtRamWE~0 ( -// Equation(s): -// \ExtRamWE~0_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\ExtRamWE~0_combout ), - .cout()); -// synopsys translate_off -defparam \ExtRamWE~0 .lut_mask = 16'h0020; -defparam \ExtRamWE~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [13]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [13]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|ixy_d~15_combout ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), + .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h0B0B; -defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N28 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~2_combout = (((\z80_|execute_|fMRead~35_combout ) # (\z80_|execute_|fIORead~3_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .datac(\z80_|execute_|fMRead~35_combout ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFFF7; -defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N2 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pin_control_|bus_ab_pin_we~2_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T3_ff~q & -// (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pin_control_|bus_ab_pin_we~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h3B0A; -defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .asdata(\z80_|address_latch_|Q [13]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[13]~20 ( -// Equation(s): -// \z80_|address_pins_|abus[13]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[13]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[13]~20 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[13]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [14])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [14]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [14]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .asdata(\z80_|address_latch_|Q [14]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N4 -cycloneive_lcell_comb \z80_|address_pins_|abus[14]~23 ( -// Equation(s): -// \z80_|address_pins_|abus[14]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[14]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[14]~23 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[14]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [15]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .asdata(\z80_|address_latch_|Q [15]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N12 -cycloneive_lcell_comb \z80_|address_pins_|abus[15]~22 ( -// Equation(s): -// \z80_|address_pins_|abus[15]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[15]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[15]~22 .lut_mask = 16'hF3F3; -defparam \z80_|address_pins_|abus[15]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h0800; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00C0; -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( -// Equation(s): -// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [1]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [1]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .asdata(\z80_|address_latch_|Q [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( -// Equation(s): -// \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [1]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [2]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .asdata(\z80_|address_latch_|Q [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N26 -cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( -// Equation(s): -// \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [2]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[2]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N0 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [3])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [3]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N1 -dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .asdata(\z80_|address_latch_|Q [3]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N12 -cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( -// Equation(s): -// \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [3]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[3]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N30 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [4])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [4]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N31 -dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .asdata(\z80_|address_latch_|Q [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N2 -cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( -// Equation(s): -// \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [4]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[4]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N12 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [5]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N13 -dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .asdata(\z80_|address_latch_|Q [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( -// Equation(s): -// \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[5]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hF3F3; -defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [6])) - - .dataa(\z80_|address_latch_|abusz [6]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .asdata(\z80_|address_latch_|Q [6]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N28 -cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( -// Equation(s): -// \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [6]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[6]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hCFCF; -defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N30 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [7]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N31 -dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .asdata(\z80_|address_latch_|Q [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N22 -cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( -// Equation(s): -// \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [7]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[7]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N20 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [8])) - - .dataa(\z80_|address_latch_|abusz [8]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N21 -dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .asdata(\z80_|address_latch_|Q [8]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N30 -cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( -// Equation(s): -// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [8]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[8]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N16 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [9]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [9]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N17 -dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .asdata(\z80_|address_latch_|Q [9]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N4 -cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( -// Equation(s): -// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [9]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[9]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N24 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [10]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .datab(\z80_|address_latch_|abusz [10]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N25 -dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .asdata(\z80_|address_latch_|Q [10]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N24 -cycloneive_lcell_comb \z80_|address_pins_|abus[10]~24 ( -// Equation(s): -// \z80_|address_pins_|abus[10]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [10]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[10]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[10]~24 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[10]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N6 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datab(\z80_|address_latch_|abusz [11]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N7 -dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .asdata(\z80_|address_latch_|Q [11]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( -// Equation(s): -// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [11]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[11]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N16 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [12])) - - .dataa(\z80_|address_latch_|abusz [12]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N17 -dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .asdata(\z80_|address_latch_|Q [12]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N30 -cycloneive_lcell_comb \z80_|address_pins_|abus[12]~21 ( -// Equation(s): -// \z80_|address_pins_|abus[12]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [12]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[12]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[12]~21 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[12]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y11_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X32_Y14_N31 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[13]~20_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X32_Y14_N1 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N12 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0200; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N18 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h000C; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: FF_X29_Y14_N5 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[14]~23_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N21 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N24 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h2000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N26 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h0C00; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N10 -cycloneive_lcell_comb \D[6]~90 ( -// Equation(s): -// \D[6]~90_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .cin(gnd), - .combout(\D[6]~90_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~90 .lut_mask = 16'hCCE2; -defparam \D[6]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N20 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hF333; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N16 -cycloneive_lcell_comb \D[6]~91 ( -// Equation(s): -// \D[6]~91_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~90_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ))) # (!\D[6]~90_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~90_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[6]~90_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), - .cin(gnd), - .combout(\D[6]~91_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~91 .lut_mask = 16'hF838; -defparam \D[6]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N2 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h0020; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G15 -cycloneive_clkctrl \CLOCK_50~inputclkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\CLOCK_50~inputclkctrl_outclk )); -// synopsys translate_off -defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; -defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y24_N16 -cycloneive_lcell_comb \~GND ( -// Equation(s): -// \~GND~combout = GND - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\~GND~combout ), - .cout()); -// synopsys translate_off -defparam \~GND .lut_mask = 16'h0000; -defparam \~GND .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vram_address[0]~feeder ( -// Equation(s): -// \ula_|video_|vram_address[0]~feeder_combout = \ula_|video_|vga_hc [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [4]), - .cin(gnd), - .combout(\ula_|video_|vram_address[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vram_address[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N4 -cycloneive_lcell_comb \ula_|video_|vram_address~0 ( -// Equation(s): -// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N21 -dffeas \ula_|video_|vram_address[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X34_Y33_N19 -dffeas \ula_|video_|vram_address[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N0 -cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( -// Equation(s): -// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|video_|vram_address[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; -defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N1 -dffeas \ula_|video_|vram_address[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N26 -cycloneive_lcell_comb \ula_|video_|Add3~0 ( -// Equation(s): -// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|Add3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N27 -dffeas \ula_|video_|vram_address[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N28 -cycloneive_lcell_comb \ula_|video_|Add3~1 ( -// Equation(s): -// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) - - .dataa(\ula_|video_|vga_hc [6]), - .datab(gnd), - .datac(\ula_|video_|vga_hc [8]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|Add3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~1 .lut_mask = 16'hA50F; -defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N29 -dffeas \ula_|video_|vram_address[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N2 -cycloneive_lcell_comb \ula_|video_|Add4~0 ( -// Equation(s): -// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) -// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) - - .dataa(\ula_|video_|vga_vc [0]), - .datab(\ula_|video_|vga_vc [1]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add4~0_combout ), - .cout(\ula_|video_|Add4~1 )); -// synopsys translate_off -defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; -defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Add4~2 ( -// Equation(s): -// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) -// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~1 ), - .combout(\ula_|video_|Add4~2_combout ), - .cout(\ula_|video_|Add4~3 )); -// synopsys translate_off -defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; -defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N6 -cycloneive_lcell_comb \ula_|video_|Add4~4 ( -// Equation(s): -// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) -// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~3 ), - .combout(\ula_|video_|Add4~4_combout ), - .cout(\ula_|video_|Add4~5 )); -// synopsys translate_off -defparam \ula_|video_|Add4~4 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N8 -cycloneive_lcell_comb \ula_|video_|Add4~6 ( -// Equation(s): -// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) -// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~5 ), - .combout(\ula_|video_|Add4~6_combout ), - .cout(\ula_|video_|Add4~7 )); -// synopsys translate_off -defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N9 -dffeas \ula_|video_|vram_address[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N10 -cycloneive_lcell_comb \ula_|video_|Add4~8 ( -// Equation(s): -// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) -// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~7 ), - .combout(\ula_|video_|Add4~8_combout ), - .cout(\ula_|video_|Add4~9 )); -// synopsys translate_off -defparam \ula_|video_|Add4~8 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N11 -dffeas \ula_|video_|vram_address[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N12 -cycloneive_lcell_comb \ula_|video_|Add4~10 ( -// Equation(s): -// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) -// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~9 ), - .combout(\ula_|video_|Add4~10_combout ), - .cout(\ula_|video_|Add4~11 )); -// synopsys translate_off -defparam \ula_|video_|Add4~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N13 -dffeas \ula_|video_|vram_address[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Add4~12 ( -// Equation(s): -// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) -// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~11 ), - .combout(\ula_|video_|Add4~12_combout ), - .cout(\ula_|video_|Add4~13 )); -// synopsys translate_off -defparam \ula_|video_|Add4~12 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N22 -cycloneive_lcell_comb \ula_|video_|Selector6~0 ( -// Equation(s): -// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~12_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~0_combout ))) - - .dataa(gnd), - .datab(\ula_|video_|Add4~12_combout ), - .datac(\ula_|video_|Add4~0_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector6~0 .lut_mask = 16'hCCF0; -defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N14 -cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( -// Equation(s): -// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address[9]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N23 -dffeas \ula_|video_|vram_address[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector6~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add4~14 ( -// Equation(s): -// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_vc [8]), - .cin(\ula_|video_|Add4~13 ), - .combout(\ula_|video_|Add4~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; -defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N20 -cycloneive_lcell_comb \ula_|video_|Selector5~0 ( -// Equation(s): -// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) - - .dataa(\ula_|video_|Add4~14_combout ), - .datab(gnd), - .datac(\ula_|video_|Add4~2_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector5~0 .lut_mask = 16'hAAF0; -defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N21 -dffeas \ula_|video_|vram_address[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector5~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N28 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( -// Equation(s): -// \ula_|video_|vram_address[10]~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N30 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( -// Equation(s): -// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & (\ula_|video_|vga_hc [1]))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) - - .dataa(\ula_|video_|Add4~4_combout ), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vram_address [10]), - .datad(\ula_|video_|vram_address[10]~2_combout ), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'h88F0; -defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N31 -dffeas \ula_|video_|vram_address[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[10]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N16 -cycloneive_lcell_comb \ula_|video_|Selector3~0 ( -// Equation(s): -// \ula_|video_|Selector3~0_combout = (\ula_|video_|Add4~12_combout ) # (\ula_|video_|vga_hc [2]) - - .dataa(gnd), - .datab(\ula_|video_|Add4~12_combout ), - .datac(gnd), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFCC; -defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N17 -dffeas \ula_|video_|vram_address[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N26 -cycloneive_lcell_comb \ula_|video_|Selector2~0 ( -// Equation(s): -// \ula_|video_|Selector2~0_combout = (\ula_|video_|Add4~14_combout ) # (\ula_|video_|vga_hc [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Add4~14_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFFF0; -defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N27 -dffeas \ula_|video_|vram_address[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[12] .power_up = "low"; -// synopsys translate_on - -// Location: M9K_X33_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N22 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|abus[13]~20_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N23 -dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y14_N1 -dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(gnd), - .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N10 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h0080; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y33_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N2 -cycloneive_lcell_comb \D[6]~87 ( -// Equation(s): -// \D[6]~87_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .cin(gnd), - .combout(\D[6]~87_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~87 .lut_mask = 16'hE6A2; -defparam \D[6]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y1_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N6 -cycloneive_lcell_comb \D[6]~88 ( -// Equation(s): -// \D[6]~88_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ (((\D[6]~87_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~87_combout )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datad(\D[6]~87_combout ), - .cin(gnd), - .combout(\D[6]~88_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~88 .lut_mask = 16'h22D8; -defparam \D[6]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N20 -cycloneive_lcell_comb \D[6]~89 ( -// Equation(s): -// \D[6]~89_combout = (\D[6]~87_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~88_combout )))) # (!\D[6]~87_combout & -// (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \D[6]~88_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datab(\D[6]~87_combout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\D[6]~88_combout ), - .cin(gnd), - .combout(\D[6]~89_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~89 .lut_mask = 16'hC3C8; -defparam \D[6]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N14 -cycloneive_lcell_comb \D[6]~111 ( -// Equation(s): -// \D[6]~111_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\D[6]~91_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\D[6]~89_combout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[6]~91_combout )) - - .dataa(\D[6]~91_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\D[6]~89_combout ), - .cin(gnd), - .combout(\D[6]~111_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~111 .lut_mask = 16'hAEA2; -defparam \D[6]~111 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X16_Y34_N8 -cycloneive_io_ibuf \raw_loader_in~input ( - .i(raw_loader_in), - .ibar(gnd), - .o(\raw_loader_in~input_o )); -// synopsys translate_off -defparam \raw_loader_in~input .bus_hold = "false"; -defparam \raw_loader_in~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N18 -cycloneive_lcell_comb \D[6]~86 ( -// Equation(s): -// \D[6]~86_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(gnd), - .datac(\raw_loader_in~input_o ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\D[6]~86_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~86 .lut_mask = 16'hFAFF; -defparam \D[6]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N28 -cycloneive_lcell_comb \D[6]~100 ( -// Equation(s): -// \D[6]~100_combout = ((\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout ))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~1_combout ), - .datab(\Equal2~0_combout ), - .datac(\D[6]~111_combout ), - .datad(\D[6]~86_combout ), - .cin(gnd), - .combout(\D[6]~100_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~100 .lut_mask = 16'hFD75; -defparam \D[6]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N4 -cycloneive_lcell_comb \D[6]~101 ( -// Equation(s): -// \D[6]~101_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [6] & \D[6]~100_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[6]~100_combout )) # (!\Equal2~1_combout ))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[6]~100_combout ), - .cin(gnd), - .combout(\D[6]~101_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~101 .lut_mask = 16'hCF05; -defparam \D[6]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N12 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[6]~101_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\D[6]~101_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[6]~9_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|fIORead~3_combout )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # -// ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|fIORead~3_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hDC50; -defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N16 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|execute_|fMRead~35_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEA; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N13 -dffeas \z80_|data_pins_|dout[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N16 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( -// Equation(s): -// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[6]~8_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|execute_|ctl_bus_db_oe~combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'h8AFF; -defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N8 -cycloneive_lcell_comb \z80_|ir_|opcode[6]~feeder ( -// Equation(s): -// \z80_|ir_|opcode[6]~feeder_combout = \z80_|bus_control_|db[6]~9_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[6]~9_combout ), - .cin(gnd), - .combout(\z80_|ir_|opcode[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|ir_|opcode[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|ir_|opcode[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_ir_we~5_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N9 -dffeas \z80_|ir_|opcode[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|ir_|opcode[6]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~1_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~2_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~1_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|pla_decode_|Equal41~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal41~2_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFF08; -defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( -// Equation(s): -// \z80_|alu_|db_high[1]~15_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'h7555; -defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( -// Equation(s): -// \z80_|alu_|db_high[1]~16_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [1]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [1]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( -// Equation(s): -// \z80_|alu_|db_high[1]~17_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~23_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~17_combout ))) - - .dataa(\z80_|alu_|db[6]~23_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[4]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hAFA0; -defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( -// Equation(s): -// \z80_|alu_|db_high[1]~18_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[1]~17_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[5]~25_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[1]~17_combout ), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( -// Equation(s): -// \z80_|alu_|db_high[1]~19_combout = (\z80_|alu_|db_high[1]~15_combout & (\z80_|alu_|db_high[1]~16_combout & ((\z80_|alu_|db_high[1]~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[1]~15_combout ), - .datab(\z80_|alu_|db_high[1]~16_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[1]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~20 ( -// Equation(s): -// \z80_|alu_|db_high[1]~20_combout = ((\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~20 .lut_mask = 16'hA8FF; -defparam \z80_|alu_|db_high[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( -// Equation(s): -// \z80_|alu_|db[5]~24_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[5]~15_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_control_|db[5]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db[5]~25 ( -// Equation(s): -// \z80_|alu_|db[5]~25_combout = ((\z80_|alu_|db[5]~24_combout & ((\z80_|alu_|db_high[1]~20_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_high[1]~20_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db[5]~24_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~25 .lut_mask = 16'hB3F3; -defparam \z80_|alu_|db[5]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N14 -cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( -// Equation(s): -// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_1d~6_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[5]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hEFCC; -defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_control_|db[5]~15_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|alu_control_|db[5]~15_combout -// & (\z80_|alu_|db_high[1]~20_combout & ((\z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|alu_control_|db[5]~15_combout ), - .datab(\z80_|alu_|db_high[1]~20_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hECA0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N23 -dffeas \z80_|alu_flags_|flags_yf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_yf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_yf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~13 ( -// Equation(s): -// \z80_|alu_control_|db[5]~13_combout = (\z80_|alu_flags_|flags_yf~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|flags_yf~q & (!\z80_|execute_|ctl_flags_oe~2_combout & -// ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) - - .dataa(\z80_|alu_flags_|flags_yf~q ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|out[6]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~13 .lut_mask = 16'hAF8C; -defparam \z80_|alu_control_|db[5]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~14 ( -// Equation(s): -// \z80_|alu_control_|db[5]~14_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~13_combout & ((\z80_|reg_file_|gdfx_temp0[5]~72_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|sw1_|db_down[5]~0_combout ), - .datab(\z80_|alu_control_|db[5]~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~14 .lut_mask = 16'h8088; -defparam \z80_|alu_control_|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( -// Equation(s): -// \z80_|alu_control_|db[5]~15_combout = ((\z80_|alu_control_|db[5]~14_combout & ((\z80_|alu_|db[5]~25_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_|db[5]~25_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[5]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hDF55; -defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N10 -cycloneive_lcell_comb \D[0]~107 ( -// Equation(s): -// \D[0]~107_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout ) # ((!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nRD_out~2_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|memory_ifc_|nRD_out~2_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[0]~107_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~107 .lut_mask = 16'hFF40; -defparam \D[0]~107 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y9_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: M9K_X22_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .lut_mask = 16'hDC98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y23_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hF838; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y29_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; -// synopsys translate_on - -// Location: M9K_X33_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'hE10F8B8C100323720BEBBDEBB81DF13FF97B252E2CB4F27BA091FBD0002D1A611E1EDBBC716D44D2912B80041C44558060CFCF15955C0D780DD5E71393920844F25E16C87C5D0308EEC52C011514BBC13AFA1028924D0C7CE738105BD47A10AA5B5C1D9D4193E4339F492B0E1A64E13AE35BE6B67AC8057BDACC155F14E906A017A1841358335450D4B26CD2A21B3D8F2211080B81EC040D7FA0B51CD48008112508062020A02490900092D2040259108806A328F4006D2AA514B42FB006ECCCCB9A360865678449975A8AE72B5C0F7BA800C1B5DC55D7D6FE2EF4EED85D00AB111821321BA426A4FE4956B43595832C271E83E060341AE5F2023FC808177383; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h1A2955372D510AC266A5445146E27000020C320FAE1557E37154040A13202DC6F40B840FB9A59B6DBB296562CB6220EFBE99D2776A202044D9101006FD221D305519198C859000004012AFF4FB060307C92BB732203BFDFEFFFFFFDFFF87FCFFFBFFEFF03FFE0FFFBFAFE0FF80787FFF7FFF83F7F87003FFBFFFFBFFFBFF0FFC0FF81FFF7FFBFFDFFFBFFFE1FF0086F3141AAB6005810A0621595A893F9D85983B9254954341968BAC8C141C90938C05B2C9CD267E11650407375FEDD6A2FEB346AAF6CFDC0791AA97B741995A3B3981E06D1A44D3711955197BB9910FCA20744915C84D6C24BAF53929814CA8A4697E8F4201145AE7415DC122A5F010436107; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h02E84F969E3C800AC610D276182020227809001A50DDDBA3487BB6AE802BA06509312DA0E620656EAF24D57C08FFB14D289613DC32083803B84DC6415FD5EDC000300A8D128FA20030ACCBAFA237B7024504D36A4BA26081137F059E78991154FE2AC2A884A8CC7FBBB21C851CC92B12E15593C0C020FFEE066558590E882D5B67459F1A8C3240FE4E6A8D028C0C088FCF471D400A19B38211004DD122212288B111114514CB11840E04828849C621392041163C00808C67223422F00110201DD18FCFFFF3FFE7F9FFFFFFF82C0B422D214711E08904524A069491774E663F48F665955B4E2C63DAC0078652D10120900298F7EE380092442AFD400BEC43C003; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; -// synopsys translate_on - -// Location: M9K_X33_Y29_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80000001C000000160F000FF70C0007F78C00000F05001007870010010000000000800000038000000F000000070000000300000006000000000000040000000F00000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000001D108000BEDA9FA9698A000000000000000000000000FFFFFFFF408102048004188297E014DA9FA9E9CA00000000000000000000000000000000FFFFFFFC800400CA972208DA9FA9CD8E00000000000000000000000000000000FFFFFFFC8004046A97A289FA9FA9CDC20000000000000000000000007FFFFFFC8000000280040E2A97A2997A9DA9CFC20000000000000000000000007FFFFFFE8000000280042EB28002BE369DA9274200000000000000000000000040810206BFFFFFFE9FE430A29D82AC3E8009E34A000000000000000000000000000000023FFFFFFC9FE4B1829FA2800E8009436A; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h9FE8334E88F827C697F88D1600A80A44809E8FC2B86999C2B85B3A82B1D32A869FE8336A88F807CA97F88F96A0A80EC2838E8D42B9E98FC2B86B3B82B0D7B2D2800832E288F827CA97F88B82A0080EC683869542B939B8C2B1AB0F8290B730C2800826EA8878078297F88AD2A0280EC283E694C2B83A3BC2A3AB3E8291A316AA800826EE881807C69DE8ABD6A0280BC282209CD2BA2A3D42A2737F82918314E2800806E6981805C69D48AED6A1E80BCA82709FC2BB223DC2A07B7F8295DF11C2800886E6980805869848AAC6A1E42DC281789DC2BBAA3DC6A02B7582955F00928008A6EE98082D9618088AC8A0F40FC289E89DC2BBCA3DC2A18B7782154F02F0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N0 -cycloneive_lcell_comb \Mux2~0 ( -// Equation(s): -// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .cin(gnd), - .combout(\Mux2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Mux2~0 .lut_mask = 16'hBA98; -defparam \Mux2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N2 -cycloneive_lcell_comb \Mux2~1 ( -// Equation(s): -// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datad(\Mux2~0_combout ), - .cin(gnd), - .combout(\Mux2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Mux2~1 .lut_mask = 16'hBBC0; -defparam \Mux2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N20 -cycloneive_lcell_comb \D[5]~110 ( -// Equation(s): -// \D[5]~110_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux2~1_combout ))))) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) - - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\Mux2~1_combout ), - .cin(gnd), - .combout(\D[5]~110_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~110 .lut_mask = 16'hAEA2; -defparam \D[5]~110 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N28 -cycloneive_lcell_comb \D[5]~85 ( -// Equation(s): -// \D[5]~85_combout = (\D[5]~84_combout & (\D[5]~110_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & (((\z80_|data_pins_|dout [5])) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout ))) - - .dataa(\D[5]~84_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\z80_|data_pins_|dout [5]), - .datad(\D[5]~110_combout ), - .cin(gnd), - .combout(\D[5]~85_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~85 .lut_mask = 16'hF351; -defparam \D[5]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N24 -cycloneive_lcell_comb \D[5]~99 ( -// Equation(s): -// \D[5]~99_combout = (\D[5]~85_combout ) # (!\D[0]~107_combout ) - - .dataa(\D[0]~107_combout ), - .datab(gnd), - .datac(gnd), - .datad(\D[5]~85_combout ), - .cin(gnd), - .combout(\D[5]~99_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~99 .lut_mask = 16'hFF55; -defparam \D[5]~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N14 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[5]~15_combout ) # ((\D[5]~99_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[5]~99_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[5]~99_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N15 -dffeas \z80_|data_pins_|dout[5] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( -// Equation(s): -// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|data_pins_|dout [5]), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hF300; -defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( -// Equation(s): -// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|alu_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[5]~14_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[5]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hF755; -defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N13 -dffeas \z80_|ir_|opcode[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[5]~15_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N20 +// Location: LCCOMB_X37_Y7_N24 cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( // Equation(s): -// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|ir_|opcode [5] & -// ((\z80_|pla_decode_|Equal3~2_combout )))) +// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|ir_|opcode [5] & +// \z80_|pla_decode_|Equal3~2_combout )))) - .dataa(\z80_|ir_|opcode [5]), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|pla_decode_|Equal3~2_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~2_combout ), .cin(gnd), .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h3350; +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2722; defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y15_N21 +// Location: LCCOMB_X37_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T2_ff~q & +// (((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hF222; +defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y7_N25 dffeas \z80_|decode_state_|DFFE_inst4 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), @@ -40825,7174 +6760,2555 @@ defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y18_N4 -cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( +// Location: LCCOMB_X37_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( // Equation(s): -// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q ) +// \z80_|execute_|fMWrite~3_combout = (!\z80_|execute_|ctl_mRead~5_combout & (((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )) # (!\z80_|pla_decode_|Equal50~0_combout ))) - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(gnd), + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|pla_decode_|Equal50~0_combout ), .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(gnd), + .datad(\z80_|decode_state_|DFFE_inst4~q ), .cin(gnd), - .combout(\z80_|decode_state_|use_ixiy~combout ), + .combout(\z80_|execute_|fMWrite~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFAFA; -defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h5551; +defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( +// Location: LCCOMB_X40_Y13_N0 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( // Equation(s): -// \z80_|execute_|ctl_mRead~23_combout = (!\z80_|decode_state_|use_ixiy~combout & (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) +// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~23_combout ), + .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88C0; +defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( -// Equation(s): -// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMWrite~3_combout )) - - .dataa(\z80_|execute_|ctl_mRead~23_combout ), - .datab(\z80_|execute_|fMWrite~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( -// Equation(s): -// \z80_|execute_|fMRead~31_combout = (\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|pla_decode_|Equal33~3_combout ) # (\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( -// Equation(s): -// \z80_|execute_|fMRead~29_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((\z80_|ir_|opcode [6]) # (\z80_|ir_|opcode [7])))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC800; -defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( -// Equation(s): -// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~9_combout ) # ((\z80_|execute_|fMRead~29_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|fMRead~29_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( -// Equation(s): -// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|nextM~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( -// Equation(s): -// \z80_|execute_|fMRead~32_combout = ((\z80_|execute_|fMRead~31_combout ) # ((\z80_|execute_|fMRead~30_combout ) # (\z80_|execute_|fMRead~28_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .datab(\z80_|execute_|fMRead~31_combout ), - .datac(\z80_|execute_|fMRead~30_combout ), - .datad(\z80_|execute_|fMRead~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (\z80_|execute_|ctl_inc_cy~77_combout & \z80_|execute_|ctl_inc_cy~53_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datab(\z80_|execute_|ctl_inc_cy~77_combout ), - .datac(\z80_|execute_|ctl_inc_cy~53_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( -// Equation(s): -// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_mRead~23_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_ir_we~12_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~23_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( -// Equation(s): -// \z80_|execute_|fMRead~10_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0100; -defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( -// Equation(s): -// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|pc_inc_hold~28_combout )) - - .dataa(\z80_|execute_|ctl_mRead~23_combout ), - .datab(\z80_|execute_|pc_inc_hold~28_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|nextM~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~9 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( -// Equation(s): -// \z80_|execute_|fMRead~11_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|fMRead~9_combout )) # (!\z80_|execute_|fMRead~10_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|fMRead~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|fMRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hAAA2; -defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( -// Equation(s): -// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~12 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( -// Equation(s): -// \z80_|execute_|fMRead~13_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|fMRead~12_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|ctl_mRead~6_combout )))) - - .dataa(\z80_|execute_|fMRead~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|fMWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~13 .lut_mask = 16'h00FE; -defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( -// Equation(s): -// \z80_|execute_|fMRead~15_combout = (\z80_|execute_|fMRead~11_combout ) # ((\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|fMRead~14_combout ), - .datab(\z80_|execute_|fMRead~11_combout ), - .datac(\z80_|execute_|fMRead~13_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~15 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( -// Equation(s): -// \z80_|execute_|fMRead~20_combout = (((\z80_|execute_|fMRead~15_combout ) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|fMRead~19_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .datab(\z80_|execute_|fMRead~19_combout ), - .datac(\z80_|execute_|fMRead~15_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~20 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~48 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~48_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~48 .lut_mask = 16'hE0C0; -defparam \z80_|execute_|pc_inc_hold~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( -// Equation(s): -// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_mRead~17_combout & (\z80_|execute_|ctl_mRead~18_combout & -// ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( -// Equation(s): -// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|fMRead~2_combout ))) - - .dataa(\z80_|execute_|fMRead~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|fMRead~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~21 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( -// Equation(s): -// \z80_|execute_|fMRead~23_combout = ((\z80_|execute_|pc_inc_hold~48_combout ) # ((\z80_|execute_|fMRead~22_combout ) # (\z80_|execute_|fMRead~21_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|pc_inc_hold~48_combout ), - .datac(\z80_|execute_|fMRead~22_combout ), - .datad(\z80_|execute_|fMRead~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( -// Equation(s): -// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~26 .lut_mask = 16'hCCEC; -defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( -// Equation(s): -// \z80_|execute_|fMRead~25_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ctl_mRead~14_combout ))) # (!\z80_|execute_|fMRead~24_combout ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|fMRead~24_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~25 .lut_mask = 16'h2F0F; -defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( -// Equation(s): -// \z80_|execute_|fMRead~27_combout = ((\z80_|execute_|fMRead~25_combout ) # ((\z80_|execute_|fMRead~26_combout & \z80_|execute_|ctl_ir_we~4_combout ))) # (!\z80_|execute_|fMRead~3_combout ) - - .dataa(\z80_|execute_|fMRead~26_combout ), - .datab(\z80_|execute_|fMRead~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|fMRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~27 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( -// Equation(s): -// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~32_combout ) # ((\z80_|execute_|fMRead~20_combout ) # ((\z80_|execute_|fMRead~23_combout ) # (\z80_|execute_|fMRead~27_combout ))) - - .dataa(\z80_|execute_|fMRead~32_combout ), - .datab(\z80_|execute_|fMRead~20_combout ), - .datac(\z80_|execute_|fMRead~23_combout ), - .datad(\z80_|execute_|fMRead~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( -// Equation(s): -// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((\z80_|execute_|fMRead~34_combout & !\z80_|execute_|fMRead~0_combout ))) - - .dataa(\z80_|execute_|fMRead~34_combout ), - .datab(\z80_|execute_|fMRead~33_combout ), - .datac(\z80_|execute_|fMRead~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFFCE; -defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(gnd), - .datab(\z80_|execute_|fMRead~35_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFC0; -defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: M9K_X33_Y18_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N28 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .lut_mask = 16'hDC98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y19_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y20_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N16 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout )) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hEC64; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y24_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y32_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; -// synopsys translate_on - -// Location: M9K_X33_Y21_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; -// synopsys translate_on - -// Location: M9K_X33_Y22_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X32_Y18_N0 -cycloneive_lcell_comb \Selector1~0 ( -// Equation(s): -// \Selector1~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .cin(gnd), - .combout(\Selector1~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector1~0 .lut_mask = 16'hBA98; -defparam \Selector1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y18_N2 -cycloneive_lcell_comb \Selector1~1 ( -// Equation(s): -// \Selector1~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector1~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector1~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector1~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datad(\Selector1~0_combout ), - .cin(gnd), - .combout(\Selector1~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector1~1 .lut_mask = 16'hBBC0; -defparam \Selector1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y18_N12 -cycloneive_lcell_comb \D[1]~103 ( -// Equation(s): -// \D[1]~103_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Selector1~1_combout -// ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), - .datad(\Selector1~1_combout ), - .cin(gnd), - .combout(\D[1]~103_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~103 .lut_mask = 16'hF2D0; -defparam \D[1]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X18_Y34_N1 -cycloneive_io_ibuf \PS2_DAT~input ( - .i(PS2_DAT), - .ibar(gnd), - .o(\PS2_DAT~input_o )); -// synopsys translate_off -defparam \PS2_DAT~input .bus_hold = "false"; -defparam \PS2_DAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: CLKCTRL_G5 -cycloneive_clkctrl \reset~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\reset~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\reset~clkctrl_outclk )); -// synopsys translate_off -defparam \reset~clkctrl .clock_type = "global clock"; -defparam \reset~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [2])) # (!\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [0]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; -defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X9_Y34_N8 -cycloneive_io_ibuf \PS2_CLK~input ( - .i(PS2_CLK), - .ibar(gnd), - .o(\PS2_CLK~input_o )); -// synopsys translate_off -defparam \PS2_CLK~input .bus_hold = "false"; -defparam \PS2_CLK~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\PS2_CLK~input_o ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N1 -dffeas \ula_|ps2_keyboard_|clk_filter[7] ( +// Location: FF_X40_Y13_N1 +dffeas \z80_|sequencer_|DFFE_M4_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [7]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N7 -dffeas \ula_|ps2_keyboard_|clk_filter[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N20 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N21 -dffeas \ula_|ps2_keyboard_|clk_filter[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N18 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N19 -dffeas \ula_|ps2_keyboard_|clk_filter[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [6] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [5] & !\ula_|ps2_keyboard_|clk_filter [4]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [6]), - .datab(\ula_|ps2_keyboard_|clk_filter [7]), - .datac(\ula_|ps2_keyboard_|clk_filter [5]), - .datad(\ula_|ps2_keyboard_|clk_filter [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N3 -dffeas \ula_|ps2_keyboard_|clk_filter[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N29 -dffeas \ula_|ps2_keyboard_|clk_filter[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N23 -dffeas \ula_|ps2_keyboard_|clk_filter[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N16 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|clk_filter [2] & (!\ula_|ps2_keyboard_|clk_filter [1] & !\ula_|ps2_keyboard_|clk_filter [3]))) - - .dataa(\ula_|ps2_keyboard_|Equal0~0_combout ), - .datab(\ula_|ps2_keyboard_|clk_filter [2]), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0002; -defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N10 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N11 -dffeas \ula_|ps2_keyboard_|clk_filter[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFC30; -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N27 -dffeas \ula_|ps2_keyboard_|ps2_clk_in ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N4 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0C00; -defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N5 -dffeas \ula_|ps2_keyboard_|clk_edge ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_edge~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y21_N3 -dffeas \ula_|ps2_keyboard_|bit_count[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [2]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; -defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N1 -dffeas \ula_|ps2_keyboard_|bit_count[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N16 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [1] & -// (!\ula_|ps2_keyboard_|bit_count [2] & (\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [3]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h1810; -defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N17 -dffeas \ula_|ps2_keyboard_|bit_count[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [3] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [3] & -// ((\ula_|ps2_keyboard_|bit_count [1] $ (\ula_|ps2_keyboard_|bit_count [0])))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h0750; -defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N27 -dffeas \ula_|ps2_keyboard_|bit_count[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [3] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [2]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\PS2_DAT~input_o ), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|always1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [1]) # (\ula_|ps2_keyboard_|bit_count [2]))) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCCC0; -defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (\ula_|ps2_keyboard_|clk_edge~q & (!\ula_|ps2_keyboard_|LessThan0~0_combout & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) - - .dataa(\ula_|ps2_keyboard_|always1~0_combout ), - .datab(\ula_|ps2_keyboard_|bit_count [0]), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h00D0; -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N9 -dffeas \ula_|ps2_keyboard_|shiftreg[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\PS2_DAT~input_o ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N15 -dffeas \ula_|ps2_keyboard_|shiftreg[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [8]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N5 -dffeas \ula_|ps2_keyboard_|shiftreg[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [7]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N11 -dffeas \ula_|ps2_keyboard_|shiftreg[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [6]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N11 -dffeas \ula_|ps2_keyboard_|shiftreg[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [5]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N25 -dffeas \ula_|ps2_keyboard_|shiftreg[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [4]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N29 -dffeas \ula_|ps2_keyboard_|shiftreg[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [3]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N1 -dffeas \ula_|ps2_keyboard_|shiftreg[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [2]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N17 -dffeas \ula_|ps2_keyboard_|shiftreg[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [1]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|Equal0~0_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( -// Equation(s): -// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|extended~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hF300; -defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|shiftreg [8]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|WideXor0~0_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .datad(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hC33C; -defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|LessThan0~0_combout & (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|WideXor0~2_combout ))) - - .dataa(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .datab(\PS2_DAT~input_o ), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N9 -dffeas \ula_|ps2_keyboard_|scan_code_ready ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|scan_code_ready~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y20_N1 -dffeas \ula_|zx_keyboard_|extended ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|extended~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|extended~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|extended .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~15 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~15_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & !\ula_|ps2_keyboard_|shiftreg [7])) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~15 .lut_mask = 16'h0202; -defparam \ula_|zx_keyboard_|keys[0][0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[0][0]~15_combout )) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0500; -defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][1]~36_combout & \ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( -// Equation(s): -// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & -// (((\ula_|zx_keyboard_|released~q )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|released~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hC8F0; -defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N19 -dffeas \ula_|zx_keyboard_|released ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|released~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|released~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|released .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|zx_keyboard_|WideOr17~0_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(\ula_|zx_keyboard_|WideOr17~0_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # -// (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|shifted~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|zx_keyboard_|shifted~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y21_N3 -dffeas \ula_|zx_keyboard_|shifted ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|shifted~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|shifted~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|shifted .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hFF88; -defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~38_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'h0003; -defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~39_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[5][1]~38_combout & (!\ula_|zx_keyboard_|keys[5][1]~35_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~38_combout & -// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~35_combout ), - .datac(\ula_|zx_keyboard_|keys[5][1]~q ), - .datad(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N19 -dffeas \ula_|zx_keyboard_|keys[5][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~31 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~31_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~31 .lut_mask = 16'h00CC; -defparam \ula_|zx_keyboard_|keys[4][1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~23 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~23_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q )) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~23 .lut_mask = 16'h1010; -defparam \ula_|zx_keyboard_|keys[7][1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~32 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~32_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~32 .lut_mask = 16'h000C; -defparam \ula_|zx_keyboard_|keys[7][2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~33 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~33_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[7][2]~32_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~33 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[5][2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~34 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~34_combout = (\ula_|zx_keyboard_|keys[4][1]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[4][1]~q -// )))) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~34 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N9 -dffeas \ula_|zx_keyboard_|keys[4][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N24 -cycloneive_lcell_comb \D[1]~30 ( -// Equation(s): -// \D[1]~30_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][1]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~30 .lut_mask = 16'hBB0B; -defparam \D[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~24 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~24_combout = (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~24 .lut_mask = 16'hA0A0; -defparam \ula_|zx_keyboard_|keys[5][4]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~28_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~24_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~29 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~29_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~29 .lut_mask = 16'h00C0; -defparam \ula_|zx_keyboard_|keys[3][1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~30 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~30_combout = (\ula_|zx_keyboard_|keys[3][1]~28_combout & ((\ula_|zx_keyboard_|keys[3][1]~29_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[3][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~30 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N17 -dffeas \ula_|zx_keyboard_|keys[3][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~25 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~25 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[1][4]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~26 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~26_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & \ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~26 .lut_mask = 16'h4040; -defparam \ula_|zx_keyboard_|keys[2][1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~27 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~27_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # -// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][1]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~27 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[2][1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N17 -dffeas \ula_|zx_keyboard_|keys[2][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][1]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [10]), - .datad(\ula_|zx_keyboard_|keys[2][1]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hF3FF; -defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'hCCCF; -defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h0060; -defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~17 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~17_combout = (\ula_|zx_keyboard_|keys[0][1]~16_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [4])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~17 .lut_mask = 16'h2040; -defparam \ula_|zx_keyboard_|keys[0][1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~18 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~18_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~17_combout & (!\ula_|zx_keyboard_|keys[0][1]~14_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~17_combout & -// ((\ula_|zx_keyboard_|keys[0][1]~q ))))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .datac(\ula_|zx_keyboard_|keys[0][1]~q ), - .datad(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~18 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y21_N7 -dffeas \ula_|zx_keyboard_|keys[0][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~19 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|scan_code_ready~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~19 .lut_mask = 16'h0100; -defparam \ula_|zx_keyboard_|keys[7][4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~20 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~20_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~20 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[6][4]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~21 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~21_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~21 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[1][1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~22 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~22_combout = (\ula_|zx_keyboard_|keys[1][1]~21_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][1]~21_combout & (\ula_|zx_keyboard_|keys[1][1]~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[1][1]~21_combout ), - .datac(\ula_|zx_keyboard_|keys[1][1]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~22 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[1][1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N13 -dffeas \ula_|zx_keyboard_|keys[1][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N2 -cycloneive_lcell_comb \D[1]~28 ( -// Equation(s): -// \D[1]~28_combout = (\ula_|zx_keyboard_|keys[0][1]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) # (!\ula_|zx_keyboard_|keys[0][1]~q & -// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][1]~q ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\ula_|zx_keyboard_|keys[1][1]~q ), - .cin(gnd), - .combout(\D[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~28 .lut_mask = 16'hD0DD; -defparam \D[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N26 -cycloneive_lcell_comb \D[1]~29 ( -// Equation(s): -// \D[1]~29_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~28_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][1]~q ), - .datab(\ula_|zx_keyboard_|key_row~0_combout ), - .datac(\z80_|address_pins_|abus[11]~19_combout ), - .datad(\D[1]~28_combout ), - .cin(gnd), - .combout(\D[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~29 .lut_mask = 16'hC400; -defparam \D[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~41_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[0][0]~15_combout ))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h0240; -defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~43 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~43_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[6][1]~42_combout )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~43 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[6][1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'hEAEA; -defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~44 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~44_combout = (\ula_|zx_keyboard_|keys[6][1]~43_combout & ((!\ula_|zx_keyboard_|keys[6][1]~40_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~43_combout & (\ula_|zx_keyboard_|keys[6][1]~q )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\ula_|zx_keyboard_|keys[6][1]~40_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~44 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[6][1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N25 -dffeas \ula_|zx_keyboard_|keys[6][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~45 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~45_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [7]))) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [7]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~45 .lut_mask = 16'h0002; -defparam \ula_|zx_keyboard_|keys[7][1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & -// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h0A38; -defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h0044; -defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h0140; -defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~4_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & (!\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|WideOr16~4_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'hF022; -defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~7_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~5_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|WideOr16~5_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|WideOr16~7_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hF808; -defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~46 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~46_combout = (\ula_|zx_keyboard_|keys[7][1]~45_combout & ((\ula_|zx_keyboard_|WideOr16~6_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~6_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # -// (!\ula_|zx_keyboard_|keys[7][1]~45_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][1]~q ), - .datad(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~46 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N31 -dffeas \ula_|zx_keyboard_|keys[7][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N20 -cycloneive_lcell_comb \D[1]~31 ( -// Equation(s): -// \D[1]~31_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][1]~q & -// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[6][1]~q ), - .datac(\z80_|address_pins_|abus[15]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[7][1]~q ), - .cin(gnd), - .combout(\D[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~31 .lut_mask = 16'hB0BB; -defparam \D[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N18 -cycloneive_lcell_comb \D[1]~32 ( -// Equation(s): -// \D[1]~32_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~30_combout & (\D[1]~29_combout & \D[1]~31_combout ))) - - .dataa(\D[1]~30_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[1]~29_combout ), - .datad(\D[1]~31_combout ), - .cin(gnd), - .combout(\D[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~32 .lut_mask = 16'hECCC; -defparam \D[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N4 -cycloneive_lcell_comb \D[1]~33 ( -// Equation(s): -// \D[1]~33_combout = ((\Equal2~0_combout & ((\D[1]~32_combout ))) # (!\Equal2~0_combout & (\D[1]~103_combout ))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[1]~103_combout ), - .datad(\D[1]~32_combout ), - .cin(gnd), - .combout(\D[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~33 .lut_mask = 16'hFB73; -defparam \D[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N8 -cycloneive_lcell_comb \D[1]~34 ( -// Equation(s): -// \D[1]~34_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout & \z80_|data_pins_|dout [1])))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[1]~33_combout ), - .datad(\z80_|data_pins_|dout [1]), - .cin(gnd), - .combout(\D[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~34 .lut_mask = 16'hF151; -defparam \D[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N18 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[1]~11_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[1]~11_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\D[1]~34_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N19 -dffeas \z80_|data_pins_|dout[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N30 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( -// Equation(s): -// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N24 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~11 ( -// Equation(s): -// \z80_|bus_control_|db[1]~11_combout = ((\z80_|bus_control_|db[1]~10_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(\z80_|data_pins_|dout [1]), - .datac(\z80_|bus_control_|db[1]~10_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'hD0FF; -defparam \z80_|bus_control_|db[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N14 -cycloneive_lcell_comb \z80_|ir_|opcode[1]~feeder ( -// Equation(s): -// \z80_|ir_|opcode[1]~feeder_combout = \z80_|bus_control_|db[1]~11_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[1]~11_combout ), - .cin(gnd), - .combout(\z80_|ir_|opcode[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|ir_|opcode[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|ir_|opcode[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N15 -dffeas \z80_|ir_|opcode[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|ir_|opcode[1]~feeder_combout ), + .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0005; -defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hC080; -defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~3_combout = (\z80_|execute_|ctl_alu_op_low~28_combout & (\z80_|pla_decode_|Equal64~0_combout & ((\z80_|pla_decode_|Equal9~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|pla_decode_|Equal64~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|pla_decode_|Equal61~2_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h001F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & -// (((!\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'h153F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'h8000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h0088; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h4000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_flags_cf_cpl~2_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'h040C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout = (((!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .lut_mask = 16'h777F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'h0F0C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hC0E0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hAAA8; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_flags_nf_we~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & !\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ))) - - .dataa(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'h0008; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal62~2_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'h20A0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal21~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'hCECC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|execute_|ctl_alu_op_low~32_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFFEF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N24 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~20_combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ) - - .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'hFFB3; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout = (\z80_|execute_|ctl_state_alu~12_combout & ((\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|ir_|opcode [3] & ((!\z80_|ir_|opcode [5]))))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .lut_mask = 16'h8500; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~21_combout )) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hF0AA; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_control_|out[6]~2_combout )) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|out[6]~2_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hFA50; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout & ((!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout -// & ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h11D8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~3_combout & (\z80_|execute_|ctl_flags_cf2_sel_daa~combout $ ((!\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'h99F8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y9_N31 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .q(\z80_|sequencer_|DFFE_M4_ff~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; +defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( +// Location: LCCOMB_X37_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( // Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~10_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h0B00; -defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~14_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~11_combout ) # (((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout )) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout )) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ))) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hF0E4; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout & \z80_|execute_|ctl_alu_op_low~28_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .lut_mask = 16'hFEFA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~10_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_alu_op_low~12_combout ))) +// \z80_|execute_|fMWrite~2_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .lut_mask = 16'hFF40; -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~10_combout ) # ((\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~19_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~5_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_alu_op_low~12_combout ) # (\z80_|execute_|ctl_state_alu~7_combout )))) # (!\z80_|execute_|ctl_state_alu~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_state_alu~15_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_state_alu~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h3F3B; -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal68~2_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|pla_decode_|Equal68~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hAA20; -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFF32; -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_set~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_set~0_combout = (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~12_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_set~0 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_flags_cf_set~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hC0CC; -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~9_combout = (\z80_|execute_|ctl_flags_cf_cpl~8_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|execute_|ctl_flags_cf_set~0_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .datac(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N4 -cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( -// Equation(s): -// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~9_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_cf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0C48; -defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~8 ( -// Equation(s): -// \z80_|alu_control_|db[0]~8_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((\z80_|bus_control_|db[0]~17_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|bus_control_|db[0]~17_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~8 .lut_mask = 16'h22A2; -defparam \z80_|alu_control_|db[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N20 -cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( -// Equation(s): -// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~19_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_|db[0]~19_combout ), - .cin(gnd), - .combout(\z80_|sw2_|db_up[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hFF0F; -defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N4 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~9 ( -// Equation(s): -// \z80_|alu_control_|db[0]~9_combout = (\z80_|alu_control_|db[0]~8_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[0]~8_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|sw2_|db_up[0]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~9 .lut_mask = 16'h8A00; -defparam \z80_|alu_control_|db[0]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~12 ( -// Equation(s): -// \z80_|alu_control_|db[0]~12_combout = ((\z80_|alu_control_|db[0]~9_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|db[0]~9_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~12 .lut_mask = 16'hB0FF; -defparam \z80_|alu_control_|db[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~67 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~67_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~67 .lut_mask = 16'hFF50; -defparam \ula_|zx_keyboard_|keys[5][0]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~81 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~81_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~81_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~81 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[5][0]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~82 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~82_combout = (\ula_|zx_keyboard_|keys[5][0]~81_combout & (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~81_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~82 .lut_mask = 16'h2800; -defparam \ula_|zx_keyboard_|keys[5][0]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~83 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~83_combout = (\ula_|zx_keyboard_|keys[5][0]~82_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~82_combout & ((\ula_|zx_keyboard_|keys[5][0]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .datab(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .datac(\ula_|zx_keyboard_|keys[5][0]~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), .datad(gnd), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~83_combout ), + .combout(\z80_|execute_|fMWrite~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~83 .lut_mask = 16'h7474; -defparam \ula_|zx_keyboard_|keys[5][0]~83 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h2F2F; +defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y20_N11 -dffeas \ula_|zx_keyboard_|keys[5][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][0]~83_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~84 ( +// Location: LCCOMB_X38_Y11_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~84_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [3])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~84_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~84 .lut_mask = 16'h0160; -defparam \ula_|zx_keyboard_|keys[4][0]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~85 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~85_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~85 .lut_mask = 16'hBABA; -defparam \ula_|zx_keyboard_|keys[4][0]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~86 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~86_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[4][0]~84_combout & ((!\ula_|zx_keyboard_|keys[4][0]~85_combout ))) # (!\ula_|zx_keyboard_|keys[4][0]~84_combout & -// (\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datab(\ula_|zx_keyboard_|keys[4][0]~84_combout ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~86 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][0]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N27 -dffeas \ula_|zx_keyboard_|keys[4][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N20 -cycloneive_lcell_comb \D[0]~49 ( -// Equation(s): -// \D[0]~49_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][0]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][0]~q ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[0]~49_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~49 .lut_mask = 16'hBB0B; -defparam \D[0]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [5] & ((\ula_|ps2_keyboard_|shiftreg [6])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & -// (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'h8810; -defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~76 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~76_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout )) # (!\ula_|zx_keyboard_|WideOr4~0_combout ))) - - .dataa(\ula_|zx_keyboard_|WideOr4~0_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~76_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~76 .lut_mask = 16'h3313; -defparam \ula_|zx_keyboard_|keys~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~73 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~73_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~73_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~73 .lut_mask = 16'hF000; -defparam \ula_|zx_keyboard_|keys[4][3]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~47 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~47_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~47 .lut_mask = 16'h0808; -defparam \ula_|zx_keyboard_|keys[6][4]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// ((\ula_|ps2_keyboard_|shiftreg [2]))))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0310; -defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~74 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~74_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~74_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~74 .lut_mask = 16'h353F; -defparam \ula_|zx_keyboard_|keys~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~75 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~75_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][3]~73_combout & !\ula_|zx_keyboard_|keys~74_combout )) # (!\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~73_combout ), - .datab(\ula_|zx_keyboard_|keys~74_combout ), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~75_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~75 .lut_mask = 16'h2F00; -defparam \ula_|zx_keyboard_|keys[0][0]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~77 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~77_combout = (\ula_|zx_keyboard_|keys~76_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) # (!\ula_|zx_keyboard_|keys~76_combout & ((\ula_|zx_keyboard_|keys[0][0]~75_combout & ((!\ula_|zx_keyboard_|released~q ))) # -// (!\ula_|zx_keyboard_|keys[0][0]~75_combout & (\ula_|zx_keyboard_|keys[0][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys~76_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~75_combout ), - .datac(\ula_|zx_keyboard_|keys[0][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~77_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~77 .lut_mask = 16'hB0F4; -defparam \ula_|zx_keyboard_|keys[0][0]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N15 -dffeas \ula_|zx_keyboard_|keys[0][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][0]~77_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~71 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~71_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~71_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~71 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[1][0]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~72 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~72_combout = (\ula_|zx_keyboard_|keys[1][0]~71_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][0]~71_combout & (\ula_|zx_keyboard_|keys[1][0]~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[1][0]~71_combout ), - .datac(\ula_|zx_keyboard_|keys[1][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~72 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[1][0]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N17 -dffeas \ula_|zx_keyboard_|keys[1][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N30 -cycloneive_lcell_comb \D[0]~47 ( -// Equation(s): -// \D[0]~47_combout = (\ula_|zx_keyboard_|keys[0][0]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~q & -// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~q ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\ula_|zx_keyboard_|keys[1][0]~q ), - .cin(gnd), - .combout(\D[0]~47_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~47 .lut_mask = 16'hD0DD; -defparam \D[0]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~80 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][0]~80_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # -// (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][0]~80_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0]~80 .lut_mask = 16'hB1F0; -defparam \ula_|zx_keyboard_|keys[2][0]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N23 -dffeas \ula_|zx_keyboard_|keys[2][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][0]~80_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~78 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~78 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|keys[3][0]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~79 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~79_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & ((\ula_|zx_keyboard_|keys[3][1]~28_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (\ula_|zx_keyboard_|keys[3][0]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][0]~78_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~79 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[3][0]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N5 -dffeas \ula_|zx_keyboard_|keys[3][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~1_combout = ((\z80_|address_pins_|DFFE_apin_latch [11]) # (!\ula_|zx_keyboard_|keys[3][0]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [11]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hFF3F; -defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N4 -cycloneive_lcell_comb \D[0]~48 ( -// Equation(s): -// \D[0]~48_combout = (\D[0]~47_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][0]~q )))) - - .dataa(\D[0]~47_combout ), - .datab(\z80_|address_pins_|abus[10]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|key_row~1_combout ), - .cin(gnd), - .combout(\D[0]~48_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~48 .lut_mask = 16'h8A00; -defparam \D[0]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~91 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~91_combout = (\ula_|zx_keyboard_|shifted~1_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[6][0]~90_combout & \ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|shifted~1_combout ), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[6][0]~90_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~91 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[6][0]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~92 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~92_combout = (\ula_|zx_keyboard_|keys[6][0]~91_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][0]~91_combout & ((\ula_|zx_keyboard_|keys[6][0]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][0]~q ), - .datad(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~92 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[6][0]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N21 -dffeas \ula_|zx_keyboard_|keys[6][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~63 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~63_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~63 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[5][4]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h0303; -defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[5][4]~63_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|WideOr16~3_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~132 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~132_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~132_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~132 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[7][0]~132 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~88 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~88_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & ((\ula_|zx_keyboard_|keys[7][0]~87_combout ) # (\ula_|zx_keyboard_|keys[7][0]~132_combout )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .datad(\ula_|zx_keyboard_|keys[7][0]~132_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~88 .lut_mask = 16'h8880; -defparam \ula_|zx_keyboard_|keys[7][0]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~89 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~89_combout = (\ula_|zx_keyboard_|keys[7][0]~88_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][0]~88_combout & (\ula_|zx_keyboard_|keys[7][0]~q )) - - .dataa(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~89 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[7][0]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N7 -dffeas \ula_|zx_keyboard_|keys[7][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N28 -cycloneive_lcell_comb \D[0]~50 ( -// Equation(s): -// \D[0]~50_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][0]~q & -// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[6][0]~q ), - .datac(\z80_|address_pins_|abus[15]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[7][0]~q ), - .cin(gnd), - .combout(\D[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~50 .lut_mask = 16'hB0BB; -defparam \D[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N10 -cycloneive_lcell_comb \D[0]~51 ( -// Equation(s): -// \D[0]~51_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~49_combout & (\D[0]~48_combout & \D[0]~50_combout ))) - - .dataa(\D[0]~49_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[0]~48_combout ), - .datad(\D[0]~50_combout ), - .cin(gnd), - .combout(\D[0]~51_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~51 .lut_mask = 16'hECCC; -defparam \D[0]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y16_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N14 -cycloneive_lcell_comb \D[0]~55 ( -// Equation(s): -// \D[0]~55_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\D[0]~55_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~55 .lut_mask = 16'hE3E0; -defparam \D[0]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N22 -cycloneive_lcell_comb \D[0]~56 ( -// Equation(s): -// \D[0]~56_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~55_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout )) # (!\D[0]~55_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~55_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[0]~55_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .cin(gnd), - .combout(\D[0]~56_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~56 .lut_mask = 16'hBCB0; -defparam \D[0]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y28_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X22_Y30_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; -// synopsys translate_on - -// Location: M9K_X22_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N4 -cycloneive_lcell_comb \D[0]~52 ( -// Equation(s): -// \D[0]~52_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\z80_|address_pins_|abus[14]~23_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .cin(gnd), - .combout(\D[0]~52_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~52 .lut_mask = 16'hF858; -defparam \D[0]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y20_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N28 -cycloneive_lcell_comb \D[0]~53 ( -// Equation(s): -// \D[0]~53_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout $ ((\D[0]~52_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & (((!\D[0]~52_combout & -// \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datab(\z80_|address_pins_|abus[15]~22_combout ), - .datac(\D[0]~52_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\D[0]~53_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~53 .lut_mask = 16'h4B48; -defparam \D[0]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N16 -cycloneive_lcell_comb \D[0]~54 ( -// Equation(s): -// \D[0]~54_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~52_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~52_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & !\D[0]~53_combout )) # (!\D[0]~52_combout & ((\D[0]~53_combout ))))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[0]~52_combout ), - .datad(\D[0]~53_combout ), - .cin(gnd), - .combout(\D[0]~54_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~54 .lut_mask = 16'hC3E0; -defparam \D[0]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N8 -cycloneive_lcell_comb \D[0]~106 ( -// Equation(s): -// \D[0]~106_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[0]~56_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[0]~54_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[0]~56_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[0]~56_combout ), - .datad(\D[0]~54_combout ), - .cin(gnd), - .combout(\D[0]~106_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~106 .lut_mask = 16'hF4B0; -defparam \D[0]~106 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N14 -cycloneive_lcell_comb \D[0]~57 ( -// Equation(s): -// \D[0]~57_combout = ((\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout )))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~1_combout ), - .datab(\D[0]~51_combout ), - .datac(\D[0]~106_combout ), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[0]~57_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~57 .lut_mask = 16'hDDF5; -defparam \D[0]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N0 -cycloneive_lcell_comb \D[0]~58 ( -// Equation(s): -// \D[0]~58_combout = (\D[0]~57_combout & (((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[0]~57_combout & (!\Equal2~1_combout & ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [0]), - .datac(\D[0]~57_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[0]~58_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~58 .lut_mask = 16'hC0F5; -defparam \D[0]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N0 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[0]~17_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[0]~17_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\D[0]~58_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N1 -dffeas \z80_|data_pins_|dout[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N4 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( -// Equation(s): -// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(\z80_|data_pins_|dout [0]), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'hC0CC; -defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( -// Equation(s): -// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|alu_control_|db[0]~12_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~16_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'hDF55; -defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y13_N27 -dffeas \z80_|ir_|opcode[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[0]~17_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) +// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2])) .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), .cin(gnd), - .combout(\z80_|pla_decode_|Equal63~0_combout ), + .combout(\z80_|pla_decode_|Equal13~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; +defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( +// Location: LCCOMB_X38_Y11_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( // Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) +// \z80_|pla_decode_|Equal13~2_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .combout(\z80_|pla_decode_|Equal13~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N20 -cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( +// Location: LCCOMB_X36_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( // Equation(s): -// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h070F; -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( -// Equation(s): -// \z80_|alu_control_|db[6]~10_combout = ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|execute_|ctl_flags_oe~2_combout )) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) - - .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|execute_|ctl_flags_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hFFF5; -defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( -// Equation(s): -// \z80_|alu_control_|db[6]~11_combout = (\z80_|alu_control_|db[6]~10_combout ) # ((\z80_|execute_|ctl_sw_1d~7_combout ) # (\z80_|execute_|ctl_reg_out_lo~8_combout )) - - .dataa(\z80_|alu_control_|db[6]~10_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFEFE; -defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( -// Equation(s): -// \z80_|alu_control_|db[4]~30_combout = (\z80_|alu_|db[4]~17_combout & (\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|reg_file_|gdfx_temp0[4]~62_combout ))) # (!\z80_|alu_|db[4]~17_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((\z80_|execute_|ctl_reg_out_lo~8_combout & !\z80_|reg_file_|gdfx_temp0[4]~62_combout )))) - - .dataa(\z80_|alu_|db[4]~17_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h5D0C; -defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( -// Equation(s): -// \z80_|alu_control_|db[4]~31_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[4]~30_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_flags_|flags_hf~combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_control_|db[4]~30_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h00B0; -defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( -// Equation(s): -// \z80_|alu_control_|db[4]~32_combout = ((\z80_|alu_control_|db[4]~31_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|alu_control_|db[4]~31_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'hBF33; -defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~119 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~119_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & -// (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~119_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~119 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[2][4]~119 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~120 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~120_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][4]~119_combout & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|zx_keyboard_|keys[2][4]~119_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~120_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~120 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[2][4]~120 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~95 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~95_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~95_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~95 .lut_mask = 16'hAFAA; -defparam \ula_|zx_keyboard_|keys[2][4]~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~121 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~121_combout = (\ula_|zx_keyboard_|keys[2][4]~120_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[2][4]~120_combout & (\ula_|zx_keyboard_|keys[2][4]~q )) - - .dataa(\ula_|zx_keyboard_|keys[2][4]~120_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~121_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~121 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[2][4]~121 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N23 -dffeas \ula_|zx_keyboard_|keys[2][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][4]~121_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~117 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~117_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~117_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~117 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|keys[3][4]~117 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~136 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~136_combout = (\ula_|zx_keyboard_|keys[3][4]~117_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[3][4]~117_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~136_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~136 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[3][4]~136 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~130 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~130_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~130_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~130 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[3][4]~130 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~118 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~118_combout = (\ula_|zx_keyboard_|keys[3][4]~136_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[3][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~136_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][4]~136_combout ), - .datac(\ula_|zx_keyboard_|keys[3][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~118 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][4]~118 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N9 -dffeas \ula_|zx_keyboard_|keys[3][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N18 -cycloneive_lcell_comb \D[4]~78 ( -// Equation(s): -// \D[4]~78_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # ((!\ula_|zx_keyboard_|keys[2][4]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][4]~q & -// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\z80_|address_pins_|abus[10]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~q ), - .cin(gnd), - .combout(\D[4]~78_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~78 .lut_mask = 16'h8ACF; -defparam \D[4]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~126 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~126_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~126 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[6][4]~126 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~128 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~128_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~128_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~128 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[5][4]~128 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~129 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~129_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[5][4]~128_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~128_combout & -// (\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~128_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~129_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~129 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][4]~129 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y19_N9 -dffeas \ula_|zx_keyboard_|keys[5][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][4]~129_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~127 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~127_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~20_combout & ((\ula_|zx_keyboard_|keys[6][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~127_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~127 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[6][4]~127 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N5 -dffeas \ula_|zx_keyboard_|keys[6][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][4]~127_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~51 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~51_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~51 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[7][4]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~125 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~125_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~51_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) -// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~1_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~125_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~125 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][4]~125 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N11 -dffeas \ula_|zx_keyboard_|keys[7][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][4]~125_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N30 -cycloneive_lcell_comb \D[4]~79 ( -// Equation(s): -// \D[4]~79_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\z80_|address_pins_|abus[14]~23_combout ) # ((!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][4]~q & -// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\z80_|address_pins_|abus[14]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~q ), - .cin(gnd), - .combout(\D[4]~79_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~79 .lut_mask = 16'h8ACF; -defparam \D[4]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~122 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q )) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & -// \ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~122 .lut_mask = 16'h4422; -defparam \ula_|zx_keyboard_|keys[4][4]~122 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~123 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~123_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][4]~122_combout ))) - - .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~123 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][4]~123 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & ((\ula_|zx_keyboard_|keys[4][4]~123_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~123_combout & ((\ula_|zx_keyboard_|keys[4][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[4][4]~q ), - .datad(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N25 -dffeas \ula_|zx_keyboard_|keys[4][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\ula_|zx_keyboard_|keys[4][4]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|execute_|ixy_d~4_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_T3_ff~q )) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [12]), - .datad(\ula_|zx_keyboard_|keys[4][4]~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~3_combout ), + .combout(\z80_|execute_|ixy_d~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hF3FF; -defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h000C; +defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y19_N8 -cycloneive_lcell_comb \D[4]~80 ( +// Location: LCCOMB_X38_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( // Equation(s): -// \D[4]~80_combout = (\D[4]~79_combout & (\ula_|zx_keyboard_|key_row~3_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) +// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) - .dataa(\ula_|zx_keyboard_|keys[5][4]~q ), - .datab(\D[4]~79_combout ), - .datac(\z80_|address_pins_|abus[13]~20_combout ), - .datad(\ula_|zx_keyboard_|key_row~3_combout ), - .cin(gnd), - .combout(\D[4]~80_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~80 .lut_mask = 16'hC400; -defparam \D[4]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~111 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~111_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|zx_keyboard_|released~q ), + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), .datab(gnd), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~111_combout ), + .combout(\z80_|execute_|fIOWrite~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~111 .lut_mask = 16'hFAAA; -defparam \ula_|zx_keyboard_|keys[0][4]~111 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hAA0A; +defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~97 ( +// Location: LCCOMB_X38_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~97_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~97 .lut_mask = 16'h0060; -defparam \ula_|zx_keyboard_|keys[0][4]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~116 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~116_combout = (\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & (!\ula_|zx_keyboard_|keys[0][4]~111_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & -// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~116_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~116 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][4]~116 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N11 -dffeas \ula_|zx_keyboard_|keys[0][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][4]~116_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~115 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~115_combout = (\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[1][4]~q )))) # -// (!\ula_|zx_keyboard_|Equal0~2_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) - - .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[1][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~115_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~115 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][4]~115 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N7 -dffeas \ula_|zx_keyboard_|keys[1][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][4]~115_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N28 -cycloneive_lcell_comb \D[4]~77 ( -// Equation(s): -// \D[4]~77_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][4]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][4]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[1][4]~q ), - .cin(gnd), - .combout(\D[4]~77_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~77 .lut_mask = 16'h8ACF; -defparam \D[4]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N26 -cycloneive_lcell_comb \D[4]~81 ( -// Equation(s): -// \D[4]~81_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~78_combout & (\D[4]~80_combout & \D[4]~77_combout ))) - - .dataa(\z80_|address_pins_|abus[0]~16_combout ), - .datab(\D[4]~78_combout ), - .datac(\D[4]~80_combout ), - .datad(\D[4]~77_combout ), - .cin(gnd), - .combout(\D[4]~81_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~81 .lut_mask = 16'hEAAA; -defparam \D[4]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y1_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; -// synopsys translate_on - -// Location: M9K_X22_Y22_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y3_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; -// synopsys translate_on - -// Location: M9K_X22_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N2 -cycloneive_lcell_comb \Selector4~0 ( -// Equation(s): -// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .cin(gnd), - .combout(\Selector4~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector4~0 .lut_mask = 16'hBA98; -defparam \Selector4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N26 -cycloneive_lcell_comb \Selector4~1 ( -// Equation(s): -// \Selector4~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector4~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # (!\Selector4~0_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector4~0_combout )))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datad(\Selector4~0_combout ), - .cin(gnd), - .combout(\Selector4~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector4~1 .lut_mask = 16'hF388; -defparam \Selector4~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y16_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y3_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N20 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .lut_mask = 16'hE5E0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N10 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .lut_mask = 16'hAFC0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N6 -cycloneive_lcell_comb \D[4]~109 ( -// Equation(s): -// \D[4]~109_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\Selector4~1_combout -// )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ))))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\Selector4~1_combout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), - .cin(gnd), - .combout(\D[4]~109_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~109 .lut_mask = 16'hFB40; -defparam \D[4]~109 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N18 -cycloneive_lcell_comb \D[4]~97 ( -// Equation(s): -// \D[4]~97_combout = ((\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout )))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\D[4]~81_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[4]~109_combout ), - .cin(gnd), - .combout(\D[4]~97_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~97 .lut_mask = 16'hDF8F; -defparam \D[4]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N30 -cycloneive_lcell_comb \D[4]~98 ( -// Equation(s): -// \D[4]~98_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [4] & ((\D[4]~97_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[4]~97_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[4]~97_combout ), - .cin(gnd), - .combout(\D[4]~98_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~98 .lut_mask = 16'hBB03; -defparam \D[4]~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N24 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[4]~19_combout ) # ((\D[4]~98_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[4]~98_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[4]~98_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N25 -dffeas \z80_|data_pins_|dout[4] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N20 -cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( -// Equation(s): -// \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[4]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'h88CC; -defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N18 -cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( -// Equation(s): -// \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[4]~18_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hDF55; -defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N19 -dffeas \z80_|ir_|opcode[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[4]~19_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~0_combout = (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) +// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) .dataa(gnd), .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~0_combout ), + .combout(\z80_|execute_|ctl_mWrite~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( +// Location: LCCOMB_X34_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( // Equation(s): -// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) +// \z80_|execute_|fMRead~2_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~5_combout ), + .combout(\z80_|execute_|fMRead~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h3F0F; +defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N22 +// Location: LCCOMB_X34_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~2_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~2 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_state_alu~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~11_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N2 cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( // Equation(s): -// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|fMRead~0_combout )))) +// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|fMRead~2_combout )))) - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), - .datad(\z80_|execute_|fMRead~0_combout ), + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|fMRead~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), .cin(gnd), .combout(\z80_|execute_|fIOWrite~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hFB00; defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( +// Location: LCCOMB_X39_Y7_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( // Equation(s): -// \z80_|execute_|fIOWrite~3_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) +// \z80_|pla_decode_|Equal2~0_combout = (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h00CC; +defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N2 +cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( +// Equation(s): +// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instCB~q ) # (\z80_|decode_state_|DFFE_instED~q ) + + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|decode_state_|table_xx~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; +defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|table_xx~0_combout & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~0_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~3 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~3_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~3 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( +// Equation(s): +// \z80_|execute_|fIOWrite~3_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), .cin(gnd), .combout(\z80_|execute_|fIOWrite~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3F0F; +defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3B3B; defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y18_N2 +// Location: LCCOMB_X39_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( +// Equation(s): +// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N16 cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( // Equation(s): -// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) +// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|fIOWrite~3_combout ), + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|fIOWrite~3_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), .cin(gnd), .combout(\z80_|execute_|fIOWrite~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hA8AA; +defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hCC8C; defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N4 +// Location: LCCOMB_X38_Y13_N4 cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( // Equation(s): -// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~5_combout ))) +// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~3_combout ))) .dataa(\z80_|execute_|fIOWrite~1_combout ), - .datab(\z80_|execute_|ctl_mRead~5_combout ), - .datac(\z80_|execute_|fIOWrite~2_combout ), + .datab(\z80_|execute_|fIOWrite~2_combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), .datad(\z80_|execute_|fIOWrite~4_combout ), .cin(gnd), .combout(\z80_|execute_|fIOWrite~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFFEC; defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( +// Location: LCCOMB_X37_Y8_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~11_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) +// \z80_|pin_control_|bus_db_pin_oe~4_combout = (!\z80_|execute_|fIOWrite~5_combout & ((\z80_|execute_|fMWrite~2_combout ) # ((\z80_|execute_|fMWrite~3_combout & !\z80_|pla_decode_|Equal13~2_combout )))) - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mWrite~10_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .dataa(\z80_|execute_|fMWrite~3_combout ), + .datab(\z80_|execute_|fMWrite~2_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|fIOWrite~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~11_combout ), + .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; +defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'h00CE; +defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( +// Location: LCCOMB_X40_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~3 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~12_combout = (\z80_|execute_|ctl_mWrite~8_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) +// \z80_|execute_|ctl_state_alu~3_combout = (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~3 .lut_mask = 16'h0C0C; +defparam \z80_|execute_|ctl_state_alu~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~1_combout = (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h3300; +defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~6_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~4_combout = (\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; +defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0100; +defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~46_combout = ((!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|execute_|ctl_mWrite~6_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~46_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2u~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal19~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal34~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h0400; +defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|comb~0 ( +// Equation(s): +// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|comb~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~0 .lut_mask = 16'hCC00; +defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal47~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|execute_|comb~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~45_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & +// (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (\z80_|execute_|ctl_inc_cy~45_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal19~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_inc_cy~45_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N10 +cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( +// Equation(s): +// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|M5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88C0; +defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N11 +dffeas \z80_|sequencer_|M5 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|M5~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|M5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|M5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( +// Equation(s): +// \z80_|execute_|ixy_d~7_combout = (\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h00AA; +defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~44_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ctl_alu_oe~2_combout & +// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_inc_cy~44_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|ctl_inc_cy~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q )) + + .dataa(gnd), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0300; +defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~14_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~7_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N24 +cycloneive_lcell_comb \z80_|execute_|fMWrite~0 ( +// Equation(s): +// \z80_|execute_|fMWrite~0_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~0 .lut_mask = 16'h0001; +defparam \z80_|execute_|fMWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~97 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~97_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~97_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~97 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~96 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~96_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal19~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~96_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~96 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~98 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~98_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~98_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~98 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~98_combout & (((!\z80_|execute_|ctl_alu_op_low~14_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_inc_cy~98_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_inc_cy~97_combout & (\z80_|execute_|ctl_inc_cy~96_combout & \z80_|execute_|ctl_inc_cy~48_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~97_combout ), + .datab(\z80_|execute_|ctl_inc_cy~96_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_cy~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|fMWrite~1 ( +// Equation(s): +// \z80_|execute_|fMWrite~1_combout = (\z80_|sequencer_|M5~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|sequencer_|M5~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # +// (\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~1 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMWrite~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N18 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|execute_|ctl_bus_inc_oe~28_combout & ((\z80_|execute_|fMWrite~0_combout ) # (!\z80_|execute_|fMWrite~1_combout ))) + + .dataa(\z80_|execute_|fMWrite~0_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .datac(gnd), + .datad(\z80_|execute_|fMWrite~1_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'h88CC; +defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N4 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|execute_|ctl_inc_cy~47_combout & (\z80_|execute_|ctl_apin_mux~0_combout & \z80_|pin_control_|bus_db_pin_oe~3_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .datab(\z80_|execute_|ctl_inc_cy~47_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~6_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|execute_|ctl_mRead~6_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h153F; +defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~7_combout = (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N22 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|pin_control_|bus_db_pin_oe~6_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((!\z80_|execute_|ctl_mWrite~7_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'hB0F0; +defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~17 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~17_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~17 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_mWrite~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( +// Equation(s): +// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|ctl_mWrite~17_combout & (!\z80_|execute_|ctl_mWrite~6_combout & !\z80_|execute_|ctl_mRead~5_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_mWrite~11_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~12_combout ), + .combout(\z80_|execute_|fMWrite~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h0003; +defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( +// Location: LCCOMB_X37_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~9_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) +// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - .dataa(\z80_|execute_|ctl_mWrite~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datac(\z80_|execute_|ctl_mWrite~9_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~13_combout ), + .combout(\z80_|execute_|ctl_state_alu~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( +// Location: LCCOMB_X39_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) +// \z80_|execute_|ctl_inc_cy~49_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout +// & (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~14_combout ), + .combout(\z80_|execute_|ctl_inc_cy~49_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N28 +// Location: LCCOMB_X36_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~49_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~49_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~4_combout ) # ((!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|fMWrite~4_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_inc_dec~2_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'hCD00; +defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( +// Equation(s): +// \z80_|execute_|fMWrite~8_combout = (\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ctl_alu_oe~2_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (\z80_|execute_|ctl_mRead~8_combout & +// ((\z80_|execute_|ctl_alu_oe~2_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~51 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~51_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~51 .lut_mask = 16'hABFF; +defparam \z80_|execute_|ctl_bus_inc_oe~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|M5~q )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~15_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hABFF; +defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal46~0_combout = (\z80_|ir_|opcode [2] & (\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [0] & \z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal46~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~10_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~45_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'hF3F7; +defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [7]), + .datac(gnd), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0033; +defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|decode_state_|DFFE_instCB~q )))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~29_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout ))) # (!\z80_|execute_|ctl_alu_oe~2_combout & (((!\z80_|execute_|ixy_d~7_combout )) # +// (!\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h1357; +defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|ctl_alu_core_S~10_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & \z80_|execute_|ctl_bus_inc_oe~29_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_S~10_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal55~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0044; +defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout )) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~7_combout & ((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & +// (((!\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ctl_bus_inc_oe~51_combout & (\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|execute_|ctl_bus_inc_oe~31_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~51_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N6 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~17 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~17_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~17 .lut_mask = 16'h1333; +defparam \z80_|pin_control_|bus_db_pin_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( +// Equation(s): +// \z80_|execute_|fIOWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h3733; +defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N0 +cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( +// Equation(s): +// \z80_|execute_|fMWrite~6_combout = ((\z80_|pla_decode_|Equal46~0_combout ) # ((!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) # (!\z80_|execute_|ctl_ir_we~5_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'hF7F5; +defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( +// Equation(s): +// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h3737; +defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N0 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|execute_|fIOWrite~0_combout & ((\z80_|execute_|fMWrite~6_combout ) # ((\z80_|execute_|fMWrite~5_combout )))) # (!\z80_|execute_|fIOWrite~0_combout & (!\z80_|execute_|ctl_mWrite~8_combout & +// ((\z80_|execute_|fMWrite~6_combout ) # (\z80_|execute_|fMWrite~5_combout )))) + + .dataa(\z80_|execute_|fIOWrite~0_combout ), + .datab(\z80_|execute_|fMWrite~6_combout ), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|execute_|fMWrite~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'hAF8C; +defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( +// Equation(s): +// \z80_|execute_|fMRead~3_combout = ((!\z80_|execute_|ctl_ir_we~5_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|ir_|opcode [7]) + + .dataa(\z80_|ir_|opcode [7]), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~4_combout & \z80_|execute_|fMRead~3_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~4_combout )) # +// (!\z80_|execute_|ctl_alu_oe~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|fMRead~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h1F15; +defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N24 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~8_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & +// (((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~5_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h0777; +defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N6 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~17_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~10_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~17_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|execute_|comb~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'h0313; +defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_reg_sel_wz~6_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|M5~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout = (\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~8_combout & +// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .lut_mask = 16'h0537; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( +// Equation(s): +// \z80_|execute_|fMWrite~7_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # (\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|pin_control_|bus_db_pin_oe~12_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & !\z80_|execute_|fMWrite~7_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .datad(\z80_|execute_|fMWrite~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h0080; +defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N2 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (!\z80_|execute_|fMWrite~8_combout & (\z80_|execute_|ctl_bus_inc_oe~32_combout & \z80_|pin_control_|bus_db_pin_oe~13_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .datab(\z80_|execute_|fMWrite~8_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'h2000; +defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~15 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~15_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout & (\z80_|pin_control_|bus_db_pin_oe~5_combout & (\z80_|pin_control_|bus_db_pin_oe~7_combout & \z80_|pin_control_|bus_db_pin_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~15 .lut_mask = 16'h4000; +defparam \z80_|pin_control_|bus_db_pin_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N8 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'hFCFC; +defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~16 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~16_combout = (\z80_|sequencer_|DFFE_T4_ff~q & ((\z80_|execute_|fIOWrite~5_combout ) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout & \z80_|pin_control_|bus_db_pin_oe~2_combout )))) # (!\z80_|sequencer_|DFFE_T4_ff~q & +// (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (\z80_|pin_control_|bus_db_pin_oe~2_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .datad(\z80_|execute_|fIOWrite~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~16 .lut_mask = 16'hBA30; +defparam \z80_|pin_control_|bus_db_pin_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|nextM~4 ( +// Equation(s): +// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout ) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~4 .lut_mask = 16'h373F; +defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( +// Equation(s): +// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_eval_cond~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h0A0A; +defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~12_combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_iorw~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|ctl_mWrite~17_combout ))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|nextM~4_combout ), + .datad(\z80_|execute_|ctl_iorw~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y11_N21 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_iorw~9_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y11_N17 +dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N14 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorq~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_iorq~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_iorq~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y11_N15 +dffeas \z80_|memory_ifc_|wait_iorq ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorq~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y11_N23 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorq~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N22 +cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( +// Equation(s): +// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) + + .dataa(gnd), + .datab(\z80_|memory_ifc_|wait_iorq~q ), + .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|iorq~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; +defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'hA000; +defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( +// Equation(s): +// \z80_|execute_|ixy_d~17_combout = (\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|decode_state_|DFFE_instIY1~q & !\z80_|decode_state_|DFFE_inst4~q )))) # (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|decode_state_|DFFE_instIY1~q & +// !\z80_|decode_state_|DFFE_inst4~q )) # (!\z80_|pla_decode_|Equal50~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~2_combout ), + .datab(\z80_|pla_decode_|Equal50~0_combout ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h111F; +defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N14 cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~15_combout = ((\z80_|execute_|ctl_mWrite~14_combout ) # ((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout ))) # (!\z80_|execute_|ctl_mWrite~13_combout ) +// \z80_|execute_|ctl_mWrite~15_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~7_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|execute_|ctl_mWrite~7_combout ))) - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|execute_|ctl_mWrite~13_combout ), - .datac(\z80_|execute_|ctl_mWrite~14_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_mWrite~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hF7F3; +defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hEAC0; defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N29 +// Location: LCCOMB_X34_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~18 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~18_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal11~0_combout & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~18 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_mWrite~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~12_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~21 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~21_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~21 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_flags_alu~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~20 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~20_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~20 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~10_combout = (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~10_combout = (\z80_|execute_|ctl_flags_alu~21_combout & (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & \z80_|execute_|ctl_flags_alu~10_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~21_combout ), + .datab(\z80_|execute_|ctl_flags_alu~20_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_mWrite~10_combout & ((!\z80_|execute_|ctl_mWrite~8_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~12_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|execute_|ctl_mWrite~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( +// Equation(s): +// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~9_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~12_combout = (\z80_|execute_|ctl_inc_cy~51_combout & (((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|execute_|ctl_inc_cy~51_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (\z80_|execute_|ctl_inc_dec~12_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_inc_dec~2_combout ), + .datac(\z80_|execute_|ctl_inc_dec~12_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~11_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~25_combout = (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~22 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~22_combout = (((!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~22 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_flags_alu~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~24_combout = (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~22_combout & (((!\z80_|execute_|ctl_mRead~25_combout & !\z80_|execute_|ctl_mRead~24_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~25_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ctl_flags_alu~22_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_mWrite~13_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~11_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~11_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( +// Equation(s): +// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|execute_|ctl_mWrite~15_combout ) # (((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout )) # (!\z80_|execute_|ctl_mWrite~14_combout )) + + .dataa(\z80_|execute_|ixy_d~17_combout ), + .datab(\z80_|execute_|ctl_mWrite~15_combout ), + .datac(\z80_|execute_|ctl_mWrite~14_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'hDFCF; +defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N1 dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mWrite~15_combout ), + .d(\z80_|execute_|ctl_mWrite~16_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -48008,7 +9324,7 @@ defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N4 +// Location: LCCOMB_X37_Y14_N12 cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( // Equation(s): // \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q @@ -48025,7 +9341,7 @@ defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N5 +// Location: FF_X37_Y14_N13 dffeas \z80_|memory_ifc_|wait_mwr ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), @@ -48044,15 +9360,32 @@ defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; // synopsys translate_on -// Location: FF_X43_Y17_N17 +// Location: LCCOMB_X40_Y11_N20 +cycloneive_lcell_comb \z80_|memory_ifc_|mwr_wr~feeder ( +// Equation(s): +// \z80_|memory_ifc_|mwr_wr~feeder_combout = \z80_|memory_ifc_|wait_mwr~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|wait_mwr~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|mwr_wr~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|mwr_wr~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|mwr_wr~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y11_N21 dffeas \z80_|memory_ifc_|mwr_wr ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_mwr~q ), + .d(\z80_|memory_ifc_|mwr_wr~feeder_combout ), + .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), @@ -48063,1063 +9396,1523 @@ defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N16 +// Location: LCCOMB_X40_Y11_N24 cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( // Equation(s): -// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|memory_ifc_|iorq~0_combout )) +// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIOWrite~5_combout )) - .dataa(\z80_|execute_|fIOWrite~5_combout ), - .datab(\z80_|memory_ifc_|iorq~0_combout ), - .datac(\z80_|memory_ifc_|mwr_wr~q ), + .dataa(\z80_|memory_ifc_|iorq~0_combout ), + .datab(\z80_|memory_ifc_|mwr_wr~q ), + .datac(\z80_|execute_|fIOWrite~5_combout ), .datad(gnd), .cin(gnd), .combout(\z80_|memory_ifc_|nWR_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hF8F8; +defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hECEC; defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N4 -cycloneive_lcell_comb \D[5]~84 ( -// Equation(s): -// \D[5]~84_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\D[5]~84_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~84 .lut_mask = 16'h0040; -defparam \D[5]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y5_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: M9K_X33_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N14 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # -// ((\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// (\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .lut_mask = 16'hBA98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N4 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hF858; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y24_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y30_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; -// synopsys translate_on - -// Location: M9K_X22_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; -// synopsys translate_on - -// Location: M9K_X33_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N18 -cycloneive_lcell_comb \Mux0~0 ( -// Equation(s): -// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .cin(gnd), - .combout(\Mux0~0_combout ), - .cout()); -// synopsys translate_off -defparam \Mux0~0 .lut_mask = 16'hBA98; -defparam \Mux0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N12 -cycloneive_lcell_comb \Mux0~1 ( -// Equation(s): -// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\Mux0~0_combout ), - .cin(gnd), - .combout(\Mux0~1_combout ), - .cout()); -// synopsys translate_off -defparam \Mux0~1 .lut_mask = 16'hBBC0; -defparam \Mux0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N22 -cycloneive_lcell_comb \D[7]~112 ( -// Equation(s): -// \D[7]~112_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Mux0~1_combout ))) -// # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), - .datad(\Mux0~1_combout ), - .cin(gnd), - .combout(\D[7]~112_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~112 .lut_mask = 16'hF4B0; -defparam \D[7]~112 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N30 -cycloneive_lcell_comb \D[7]~94 ( -// Equation(s): -// \D[7]~94_combout = (\D[5]~84_combout & (\D[7]~112_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & ((\z80_|data_pins_|dout [7]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\D[5]~84_combout ), - .datab(\z80_|data_pins_|dout [7]), - .datac(\D[7]~112_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[7]~94_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~94 .lut_mask = 16'hC4F5; -defparam \D[7]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N26 -cycloneive_lcell_comb \D[7]~102 ( -// Equation(s): -// \D[7]~102_combout = (\D[7]~94_combout ) # (!\D[0]~107_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\D[7]~94_combout ), - .datad(\D[0]~107_combout ), - .cin(gnd), - .combout(\D[7]~102_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~102 .lut_mask = 16'hF0FF; -defparam \D[7]~102 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N26 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\D[7]~102_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[7]~7_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[7]~102_combout & (\z80_|bus_control_|db[7]~7_combout -// & ((\z80_|execute_|ctl_bus_db_we~7_combout )))) - - .dataa(\D[7]~102_combout ), - .datab(\z80_|bus_control_|db[7]~7_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hECA0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N27 -dffeas \z80_|data_pins_|dout[7] ( +// Location: FF_X40_Y11_N17 +dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .d(\z80_|execute_|setM1~53_combout ), .asdata(vcc), - .clrn(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|data_pins_|dout [7]), + .q(\z80_|memory_ifc_|DFFE_m1_ff1~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[7] .power_up = "low"; +defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N2 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( +// Location: LCCOMB_X40_Y11_N8 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( // Equation(s): -// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) +// \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q .dataa(gnd), - .datab(\z80_|alu_control_|db[7]~18_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_m1_ff1~q ), .cin(gnd), - .combout(\z80_|bus_control_|db[7]~5_combout ), + .combout(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N8 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( -// Equation(s): -// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|data_pins_|dout [7]), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|bus_control_|db[7]~5_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[7]~7_combout ), - .cout()); +// Location: FF_X40_Y11_N9 +dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), + .prn(vcc)); // synopsys translate_off -defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hBF0F; -defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; // synopsys translate_on -// Location: FF_X32_Y13_N21 -dffeas \z80_|ir_|opcode[7] ( +// Location: FF_X40_Y11_N7 +dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|bus_control_|db[7]~7_combout ), + .asdata(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [7]), + .q(\z80_|memory_ifc_|DFFE_m1_ff3~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[7] .power_up = "low"; +defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y13_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( +// Location: LCCOMB_X40_Y11_N6 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( // Equation(s): -// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) +// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # ((\z80_|memory_ifc_|DFFE_m1_ff3~q )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & +// (!\z80_|interrupts_|DFFE_inst44~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # (\z80_|memory_ifc_|DFFE_m1_ff3~q )))) - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), + .datac(\z80_|memory_ifc_|DFFE_m1_ff3~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~0_combout ), + .combout(\z80_|memory_ifc_|nRD_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0010; -defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hA8FC; +defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( +// Location: LCCOMB_X29_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~2 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|pla_decode_|Equal77~0_combout & (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~1_combout ))) +// \z80_|execute_|ctl_mRead~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal2~0_combout ))) - .dataa(\z80_|pla_decode_|Equal77~0_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal2~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~5_combout ), + .combout(\z80_|execute_|ctl_mRead~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( +// Location: LCCOMB_X38_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( // Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_ir_we~4_combout & (\z80_|pla_decode_|Equal8~0_combout & !\z80_|ir_|opcode [3]))) +// \z80_|execute_|fIORead~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hC080; +defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h0033; +defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~15_combout = (\z80_|execute_|ctl_mWrite~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal1~4_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( +// Equation(s): +// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hC080; +defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( +// Equation(s): +// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|ctl_alu_op_low~15_combout ) # ((\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|fIOWrite~0_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~10_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datac(\z80_|execute_|fIOWrite~0_combout ), + .datad(\z80_|execute_|fIORead~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFFCE; +defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( +// Equation(s): +// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|ctl_mRead~2_combout & \z80_|execute_|fIOWrite~1_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|fIORead~0_combout ), + .datac(\z80_|execute_|fIOWrite~1_combout ), + .datad(\z80_|execute_|fIORead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hAA00; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( +// Equation(s): +// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_im_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N23 +dffeas \z80_|interrupts_|im2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_im_we~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|im2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~10_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|im2~q ), + .datac(gnd), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~1_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ctl_mRead~30_combout ) # ((\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mRead~10_combout ), + .datac(\z80_|execute_|ctl_mRead~30_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'hFCF0; +defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [1]) # ((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~4_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFCF; +defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal44~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal44~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0010; +defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~6_combout = (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|DFFE_inst4~q ))) + + .dataa(\z80_|pla_decode_|Equal44~0_combout ), + .datab(\z80_|decode_state_|DFFE_instIY1~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( +// Equation(s): +// \z80_|execute_|fMRead~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|pla_decode_|Equal13~2_combout )) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMRead~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0202; +defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~17_combout = (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|fMWrite~0_combout & \z80_|execute_|fMRead~5_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|fMWrite~0_combout ), + .datad(\z80_|execute_|fMRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~12_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h00A0; +defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal49~0_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal77~0_combout & !\z80_|decode_state_|in_halt~q )) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal77~0_combout ), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal49~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h0808; +defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~57 ( +// Equation(s): +// \z80_|execute_|setM1~57_combout = (!\z80_|execute_|ctl_mRead~12_combout & (((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )) # (!\z80_|pla_decode_|Equal49~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~57 .lut_mask = 16'h5551; +defparam \z80_|execute_|setM1~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~15_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal25~0_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal25~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_ir_we~6_combout & (\z80_|pla_decode_|Equal55~0_combout & !\z80_|decode_state_|table_xx~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_ir_we~6_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|decode_state_|table_xx~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h3303; +defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( +// Equation(s): +// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( +// Equation(s): +// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) + + .dataa(\z80_|pla_decode_|Equal44~0_combout ), + .datab(\z80_|decode_state_|DFFE_instIY1~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hA080; +defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ixy_d~10_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ctl_mRead~3_combout & !\z80_|execute_|ctl_mRead~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~10_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( +// Equation(s): +// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_al_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0A00; +defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal29~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal29~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~38 ( +// Equation(s): +// \z80_|execute_|setM1~38_combout = (\z80_|execute_|fMRead~4_combout & (!\z80_|pla_decode_|Equal29~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) + + .dataa(\z80_|execute_|fMRead~4_combout ), + .datab(\z80_|pla_decode_|Equal29~0_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|setM1~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~38 .lut_mask = 16'h0202; +defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal35~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~33_combout = (!\z80_|pla_decode_|Equal35~0_combout & ((\z80_|ir_|opcode [4]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|pla_decode_|Equal24~0_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), .datad(\z80_|ir_|opcode [3]), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .combout(\z80_|execute_|pc_inc_hold~33_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'h0F0B; +defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( +// Location: LCCOMB_X38_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|comb~1 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) +// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .dataa(gnd), + .datab(\z80_|ir_|opcode [5]), + .datac(gnd), + .datad(\z80_|ir_|opcode [4]), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), + .combout(\z80_|execute_|comb~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; +defparam \z80_|execute_|comb~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( +// Location: LCCOMB_X38_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~8_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|M5~q & ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) +// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|comb~1_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), + .combout(\z80_|execute_|ctl_mRead~13_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h3020; -defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( +// Location: LCCOMB_X38_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) +// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|pla_decode_|Equal41~2_combout ))) - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .dataa(\z80_|execute_|ctl_mRead~13_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( +// Location: LCCOMB_X39_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) +// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|pc_inc_hold~33_combout & (!\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout )) - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), + .dataa(gnd), + .datab(\z80_|execute_|pc_inc_hold~33_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC8C0; -defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0C00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( +// Location: LCCOMB_X36_Y6_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~2 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~6_combout = (((\z80_|execute_|ctl_bus_db_we~4_combout ) # (!\z80_|execute_|ctl_sw_2u~3_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) +// \z80_|pla_decode_|Equal40~2_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [2]))) - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~4_combout ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [2]), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), + .combout(\z80_|pla_decode_|Equal40~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal40~2 .lut_mask = 16'h0010; +defparam \z80_|pla_decode_|Equal40~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( +// Location: LCCOMB_X36_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~36 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~3_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|execute_|ctl_bus_db_we~2_combout ) # (\z80_|execute_|ctl_bus_db_we~6_combout ))) +// \z80_|execute_|setM1~36_combout = (!\z80_|pla_decode_|Equal6~1_combout & (((!\z80_|ir_|opcode [5] & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal40~2_combout ))) - .dataa(\z80_|execute_|ctl_bus_db_we~3_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~6_combout ), + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|pla_decode_|Equal40~2_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), + .combout(\z80_|execute_|setM1~36_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; +defparam \z80_|execute_|setM1~36 .lut_mask = 16'h1115; +defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~50 ( +// Location: LCCOMB_X37_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~14 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) +// \z80_|execute_|pc_inc_hold~14_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|pla_decode_|Equal33~2_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|pla_decode_|Equal50~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~14 .lut_mask = 16'h1115; +defparam \z80_|execute_|pc_inc_hold~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~37 ( +// Equation(s): +// \z80_|execute_|setM1~37_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (\z80_|execute_|setM1~36_combout & (\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datab(\z80_|execute_|setM1~36_combout ), + .datac(\z80_|execute_|pc_inc_hold~14_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~37 .lut_mask = 16'h0080; +defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~14_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~39 ( +// Equation(s): +// \z80_|execute_|setM1~39_combout = (\z80_|execute_|setM1~57_combout & (\z80_|execute_|setM1~38_combout & (\z80_|execute_|setM1~37_combout & !\z80_|execute_|ctl_mRead~14_combout ))) + + .dataa(\z80_|execute_|setM1~57_combout ), + .datab(\z80_|execute_|setM1~38_combout ), + .datac(\z80_|execute_|setM1~37_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0080; +defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((!\z80_|execute_|setM1~39_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|ctl_mRead~17_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|setM1~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0011; +defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal40~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h4040; +defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal37~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0400; +defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~26_combout = (\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~2_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~16_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal12~0_combout & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal12~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~13_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~19_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~1_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal38~2_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|pla_decode_|Equal35~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~0 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N8 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~1_combout = (\z80_|pla_decode_|Equal24~1_combout ) # ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|reg_control_|reg_sys_we_lo~0_combout ) # (\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~1_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~0_combout ), + .datad(\z80_|pla_decode_|Equal29~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~1 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|reg_control_|reg_sys_we_lo~1_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # +// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|reg_control_|reg_sys_we_lo~1_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~1_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'h153F; +defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~18_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~20_combout = (\z80_|reg_control_|reg_sys_we_lo~2_combout & (((!\z80_|execute_|ctl_mRead~19_combout & !\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~19_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~22_combout = (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~20_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~16_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datab(\z80_|execute_|ctl_mRead~16_combout ), + .datac(\z80_|execute_|ctl_mRead~20_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~1_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|DFFE_instED~q & !\z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0008; +defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~23_combout = (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_mRead~14_combout & +// (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~14_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~27_combout = (\z80_|execute_|ctl_mRead~23_combout & (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal38~2_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|ctl_mRead~27_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~26_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mRead~22_combout ), + .datad(\z80_|execute_|ctl_mRead~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~3 ( +// Equation(s): +// \z80_|execute_|nextM~3_combout = (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|pla_decode_|Equal41~2_combout )) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ixy_d~10_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0011; +defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|execute_|nextM~3_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h8F00; +defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~31_combout ) # ((\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_mRead~29_combout ) # (!\z80_|execute_|ctl_mRead~28_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~31_combout ), + .datab(\z80_|execute_|ctl_mRead~32_combout ), + .datac(\z80_|execute_|ctl_mRead~28_combout ), + .datad(\z80_|execute_|ctl_mRead~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y11_N19 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mRead~33_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N28 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q .dataa(gnd), .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~50 .lut_mask = 16'h000F; -defparam \ula_|zx_keyboard_|keys[0][2]~50 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~52 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~52_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[0][2]~50_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[0][2]~50_combout & ((\ula_|zx_keyboard_|keys[0][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[0][2]~q ), - .datad(\ula_|zx_keyboard_|keys[0][2]~50_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~52_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~52 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][2]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N17 -dffeas \ula_|zx_keyboard_|keys[0][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][2]~52_combout ), +// Location: FF_X40_Y11_N29 +dffeas \z80_|memory_ifc_|wait_mrd ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][2]~q ), + .q(\z80_|memory_ifc_|wait_mrd~q ), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; +defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~48 ( +// Location: LCCOMB_X40_Y11_N10 +cycloneive_lcell_comb \z80_|memory_ifc_|DFFE_mrd_ff3~feeder ( // Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~48_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~48 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|keys[3][3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~49 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~49_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[6][4]~47_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout & (\ula_|zx_keyboard_|keys[1][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[1][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .datab(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~49 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][2]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N23 -dffeas \ula_|zx_keyboard_|keys[1][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N22 -cycloneive_lcell_comb \D[2]~35 ( -// Equation(s): -// \D[2]~35_combout = (\z80_|address_pins_|abus[8]~18_combout & (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) # (!\z80_|address_pins_|abus[8]~18_combout & (!\ula_|zx_keyboard_|keys[0][2]~q & -// ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) - - .dataa(\z80_|address_pins_|abus[8]~18_combout ), - .datab(\ula_|zx_keyboard_|keys[0][2]~q ), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\z80_|address_pins_|abus[9]~17_combout ), - .cin(gnd), - .combout(\D[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~35 .lut_mask = 16'hBB0B; -defparam \D[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~57 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~57_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]) +// \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout = \z80_|memory_ifc_|wait_mrd~q .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(gnd), .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\z80_|memory_ifc_|wait_mrd~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~57_combout ), + .combout(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~57 .lut_mask = 16'h3300; -defparam \ula_|zx_keyboard_|keys[5][2]~57 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~58 ( +// Location: FF_X40_Y11_N11 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N0 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~58_combout = (\ula_|zx_keyboard_|keys[5][2]~57_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[5][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[5][2]~57_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) +// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|wait_mrd~q ) - .dataa(\ula_|zx_keyboard_|keys[5][2]~57_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[5][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), + .dataa(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|wait_mrd~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~58_combout ), + .combout(\z80_|memory_ifc_|nRD_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~58 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][2]~58 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0055; +defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y18_N15 -dffeas \ula_|zx_keyboard_|keys[5][2] ( +// Location: LCCOMB_X40_Y11_N12 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~2_combout = (\z80_|memory_ifc_|nRD_out~0_combout ) # (((\z80_|execute_|fIORead~3_combout & \z80_|memory_ifc_|iorq~0_combout )) # (!\z80_|memory_ifc_|nRD_out~1_combout )) + + .dataa(\z80_|memory_ifc_|nRD_out~0_combout ), + .datab(\z80_|execute_|fIORead~3_combout ), + .datac(\z80_|memory_ifc_|iorq~0_combout ), + .datad(\z80_|memory_ifc_|nRD_out~1_combout ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hEAFF; +defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N12 +cycloneive_lcell_comb \Equal2~1 ( +// Equation(s): +// \Equal2~1_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nRD_out~2_combout )) + + .dataa(gnd), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nRD_out~2_combout ), + .cin(gnd), + .combout(\Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~1 .lut_mask = 16'h3000; +defparam \Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y34_N1 +cycloneive_io_ibuf \PS2_DAT~input ( + .i(PS2_DAT), + .ibar(gnd), + .o(\PS2_DAT~input_o )); +// synopsys translate_off +defparam \PS2_DAT~input .bus_hold = "false"; +defparam \PS2_DAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G9 +cycloneive_clkctrl \reset~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\reset~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\reset~clkctrl_outclk )); +// synopsys translate_off +defparam \reset~clkctrl .clock_type = "global clock"; +defparam \reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N18 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [1] & ((!\ula_|ps2_keyboard_|bit_count [2]) # (!\ula_|ps2_keyboard_|bit_count [3])))) # (!\ula_|ps2_keyboard_|bit_count [0] & +// (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [1]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [1]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h121A; +defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y34_N8 +cycloneive_io_ibuf \PS2_CLK~input ( + .i(PS2_CLK), + .ibar(gnd), + .o(\PS2_CLK~input_o )); +// synopsys translate_off +defparam \PS2_CLK~input .bus_hold = "false"; +defparam \PS2_CLK~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N24 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\PS2_CLK~input_o ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N25 +dffeas \ula_|ps2_keyboard_|clk_filter[7] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][2]~58_combout ), + .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49128,70 +10921,827 @@ dffeas \ula_|zx_keyboard_|keys[5][2] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][2]~q ), + .q(\ula_|ps2_keyboard_|clk_filter [7]), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; +defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~59 ( +// Location: LCCOMB_X17_Y27_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~59_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|extended~q ))) +// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|extended~q ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [7]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~59_combout ), + .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~59 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[4][2]~59 .sum_lutc_input = "datac"; +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~131 ( +// Location: FF_X17_Y27_N3 +dffeas \ula_|ps2_keyboard_|clk_filter[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~131_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[4][2]~59_combout & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [0]))) +// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [6]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N13 +dffeas \ula_|ps2_keyboard_|clk_filter[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N18 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N19 +dffeas \ula_|ps2_keyboard_|clk_filter[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [4]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N11 +dffeas \ula_|ps2_keyboard_|clk_filter[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N20 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [5] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [4] & !\ula_|ps2_keyboard_|clk_filter [6]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [5]), + .datab(\ula_|ps2_keyboard_|clk_filter [7]), + .datac(\ula_|ps2_keyboard_|clk_filter [4]), + .datad(\ula_|ps2_keyboard_|clk_filter [6]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N1 +dffeas \ula_|ps2_keyboard_|clk_filter[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N23 +dffeas \ula_|ps2_keyboard_|clk_filter[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|clk_filter [3] & (\ula_|ps2_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|clk_filter [1] & !\ula_|ps2_keyboard_|clk_filter [2]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [3]), + .datab(\ula_|ps2_keyboard_|Equal0~0_combout ), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0004; +defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N27 +dffeas \ula_|ps2_keyboard_|clk_filter[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|clk_filter [0])) # (!\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|ps2_clk_in~q ))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hAAF0; +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N7 +dffeas \ula_|ps2_keyboard_|ps2_clk_in ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|clk_filter [0] & !\ula_|ps2_keyboard_|ps2_clk_in~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datac(\ula_|ps2_keyboard_|clk_filter [0]), + .datad(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h00C0; +defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N17 +dffeas \ula_|ps2_keyboard_|clk_edge ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_edge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; +// synopsys translate_on + +// Location: FF_X18_Y12_N19 +dffeas \ula_|ps2_keyboard_|bit_count[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [2]))) # (!\ula_|ps2_keyboard_|bit_count [1] & +// (((\ula_|ps2_keyboard_|bit_count [3] & !\ula_|ps2_keyboard_|bit_count [2])))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [1]), + .datac(\ula_|ps2_keyboard_|bit_count [3]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h0830; +defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y12_N29 +dffeas \ula_|ps2_keyboard_|bit_count[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [0] & \ula_|ps2_keyboard_|bit_count [1]))))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [2]), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; +defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y12_N13 +dffeas \ula_|ps2_keyboard_|bit_count[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [2] & !\ula_|ps2_keyboard_|bit_count [1])) # (!\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [2]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [0]), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; +defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y12_N23 +dffeas \ula_|ps2_keyboard_|bit_count[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [2]) # (\ula_|ps2_keyboard_|bit_count [1]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [2]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCC88; +defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [3] & !\PS2_DAT~input_o ))) + + .dataa(\ula_|ps2_keyboard_|bit_count [2]), + .datab(\ula_|ps2_keyboard_|bit_count [1]), + .datac(\ula_|ps2_keyboard_|bit_count [3]), + .datad(\PS2_DAT~input_o ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (!\ula_|ps2_keyboard_|LessThan0~0_combout & (\ula_|ps2_keyboard_|clk_edge~q & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|always1~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h2030; +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y10_N5 +dffeas \ula_|ps2_keyboard_|shiftreg[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\PS2_DAT~input_o ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y10_N27 +dffeas \ula_|ps2_keyboard_|shiftreg[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [8]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y10_N13 +dffeas \ula_|ps2_keyboard_|shiftreg[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [7]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y8_N21 +dffeas \ula_|ps2_keyboard_|shiftreg[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [6]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y10_N31 +dffeas \ula_|ps2_keyboard_|shiftreg[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [5]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X20_Y8_N17 +dffeas \ula_|ps2_keyboard_|shiftreg[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [4]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X20_Y8_N31 +dffeas \ula_|ps2_keyboard_|shiftreg[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [3]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X20_Y8_N23 +dffeas \ula_|ps2_keyboard_|shiftreg[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [2]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y10_N23 +dffeas \ula_|ps2_keyboard_|shiftreg[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [1]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [6]))) .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[4][2]~59_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|zx_keyboard_|Equal0~0_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~131_combout ), + .combout(\ula_|zx_keyboard_|Equal0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~131 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[4][2]~131 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~60 ( +// Location: LCCOMB_X19_Y10_N4 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~60_combout = (\ula_|zx_keyboard_|keys[4][2]~131_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[4][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[4][2]~131_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) +// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [6]))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[4][2]~131_combout ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [8]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~60_combout ), + .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~60 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[4][2]~60 .sum_lutc_input = "datac"; +defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y18_N15 -dffeas \ula_|zx_keyboard_|keys[4][2] ( +// Location: LCCOMB_X19_Y10_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N24 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~0_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hC33C; +defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N24 +cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|WideXor0~2_combout & (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|LessThan0~0_combout ))) + + .dataa(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .datab(\PS2_DAT~input_o ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y12_N25 +dffeas \ula_|ps2_keyboard_|scan_code_ready ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][2]~60_combout ), + .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49200,86 +11750,175 @@ dffeas \ula_|zx_keyboard_|keys[4][2] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][2]~q ), + .q(\ula_|ps2_keyboard_|scan_code_ready~q ), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; +defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N4 -cycloneive_lcell_comb \D[2]~37 ( +// Location: LCCOMB_X20_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( // Equation(s): -// \D[2]~37_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][2]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) +// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|released~q ) # (\ula_|ps2_keyboard_|shiftreg [4])))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & +// (((\ula_|zx_keyboard_|released~q )))) - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~q ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~37 .lut_mask = 16'hBB0B; -defparam \D[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~53 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~53_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .dataa(\ula_|zx_keyboard_|Equal0~1_combout ), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|zx_keyboard_|released~q ), .datad(\ula_|ps2_keyboard_|shiftreg [4]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~53_combout ), + .combout(\ula_|zx_keyboard_|released~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~53 .lut_mask = 16'h00F0; -defparam \ula_|zx_keyboard_|keys[3][2]~53 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hB8B0; +defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~55 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~55_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) +// Location: FF_X20_Y9_N27 +dffeas \ula_|zx_keyboard_|released ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|released~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|released~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|released .power_up = "low"; +// synopsys translate_on - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), +// Location: LCCOMB_X21_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(gnd), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~55_combout ), + .combout(\ula_|zx_keyboard_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~55 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[2][2]~55 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h1010; +defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~56 ( +// Location: LCCOMB_X20_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~50 ( // Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~56_combout = (\ula_|zx_keyboard_|keys[2][2]~55_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~55_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) +// \ula_|zx_keyboard_|keys[3][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~50 .lut_mask = 16'h5500; +defparam \ula_|zx_keyboard_|keys[3][2]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( +// Equation(s): +// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|zx_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|extended~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hA0AA; +defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N1 +dffeas \ula_|zx_keyboard_|extended ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|extended~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|extended~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|extended .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~15 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~15_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~15 .lut_mask = 16'h0010; +defparam \ula_|zx_keyboard_|keys[7][4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~52 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~52_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[3][2]~50_combout & \ula_|zx_keyboard_|keys[7][4]~15_combout ))) + + .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .datad(\ula_|zx_keyboard_|keys[7][4]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~52_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~52 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[2][2]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~53 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~53_combout = (\ula_|zx_keyboard_|keys[2][2]~52_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~52_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), .datac(\ula_|zx_keyboard_|keys[2][2]~q ), - .datad(\ula_|zx_keyboard_|keys[2][2]~55_combout ), + .datad(\ula_|zx_keyboard_|keys[2][2]~52_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~56_combout ), + .combout(\ula_|zx_keyboard_|keys[2][2]~53_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~56 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[2][2]~56 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][2]~53 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[2][2]~53 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y20_N27 +// Location: FF_X20_Y9_N25 dffeas \ula_|zx_keyboard_|keys[2][2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][2]~56_combout ), + .d(\ula_|zx_keyboard_|keys[2][2]~53_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49295,28 +11934,27482 @@ defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~54 ( +// Location: LCCOMB_X31_Y14_N4 +cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~54_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][2]~53_combout & ((\ula_|zx_keyboard_|keys[3][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) +// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # +// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[3][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][2]~53_combout ), + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|resets_|clrpc_int~q ), + .datad(\z80_|resets_|x1~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~54_combout ), + .combout(\z80_|resets_|clrpc_int~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~54 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[3][2]~54 .sum_lutc_input = "datac"; +defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; +defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y20_N29 +// Location: FF_X31_Y14_N5 +dffeas \z80_|resets_|clrpc_int ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|clrpc_int~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|clrpc_int~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; +defparam \z80_|resets_|clrpc_int .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N0 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0F0F; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N1 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N14 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_9~feeder ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout = \z80_|resets_|SYNTHESIZED_WIRE_10~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .lut_mask = 16'hFF00; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N15 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y12_N27 +dffeas \z80_|resets_|DFFE_intr_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N26 +cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( +// Equation(s): +// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|clrpc_int~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|SYNTHESIZED_WIRE_10~q ))) + + .dataa(\z80_|resets_|clrpc_int~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .datac(\z80_|resets_|DFFE_intr_ff3~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .cin(gnd), + .combout(\z80_|resets_|clrpc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; +defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_al_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h4044; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~1_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal40~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal40~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal40~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; +defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal39~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal40~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal40~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0003; +defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal6~1_combout )) + + .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h000A; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ))) + + .dataa(\z80_|execute_|fMRead~2_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h0555; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_alu_oe~2_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h5554; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & ((\z80_|execute_|fMRead~2_combout ) # ((\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~14_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .datad(\z80_|execute_|fMRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h0F02; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~10_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_mRead~13_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'h0003; +defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~20_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hDFDF; +defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~4_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h33BB; +defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_reg_sys_hilo~20_combout & (((\z80_|execute_|ctl_inc_dec~4_combout )) # (!\z80_|pla_decode_|Equal33~3_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo~20_combout & +// (!\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datab(\z80_|pla_decode_|Equal33~3_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_inc_dec~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hAF23; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & ((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout +// )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00D0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~33_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|pc_inc_hold~33_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h50D0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & \z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|execute_|ctl_mRead~7_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .datac(\z80_|execute_|ctl_al_we~5_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h4044; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~13_combout = ((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'hF0D0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~16_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~12_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~16 .lut_mask = 16'h8808; +defparam \z80_|execute_|ctl_reg_sys_hilo~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~16_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_mWrite~9_combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h010F; +defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_al_we~13_combout & \z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'hB300; +defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|setM1~53_combout & (\z80_|execute_|ctl_reg_sel_pc~12_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~6_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~6 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_alu_bs_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~6_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~2_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal29~0_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout & +// (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|pla_decode_|Equal29~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; +defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal9~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h3777; +defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N0 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~1_combout & (\z80_|reg_control_|reg_sel_pc~0_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal38~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h7000; +defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal56~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal56~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~18_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~17_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|execute_|ctl_alu_op_low~17_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_oe~4_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~9_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_in_hi~4_combout & \z80_|execute_|ctl_reg_in_hi~3_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|execute_|ctl_mWrite~9_combout ) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~9_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h337F; +defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( +// Equation(s): +// \z80_|execute_|fMRead~6_combout = (\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|execute_|ctl_alu_op_low~14_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_mRead~13_combout )))) # +// (!\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N28 +cycloneive_lcell_comb \z80_|nM1_int~2 ( +// Equation(s): +// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|nM1_int~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|nM1_int~2 .lut_mask = 16'h000F; +defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_dec~3_combout & (\z80_|execute_|fMRead~6_combout & (!\z80_|nM1_int~2_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), + .datab(\z80_|execute_|fMRead~6_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~94 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~94_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~94_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~94 .lut_mask = 16'h7F7F; +defparam \z80_|execute_|ctl_inc_cy~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~50_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hF5F7; +defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ixy_d~16_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & +// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ixy_d~16_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~15_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ixy_d~10_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h373F; +defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~13_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h3F37; +defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & (\z80_|execute_|ctl_reg_sel_pc~4_combout & \z80_|execute_|ctl_reg_sel_pc~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & +// (!\z80_|pla_decode_|Equal12~1_combout & ((\z80_|pla_decode_|Equal25~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(\z80_|pla_decode_|Equal24~0_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'hB3A0; +defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|execute_|ctl_reg_sel_pc~8_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h020A; +defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~99 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~99_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~99_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~99 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_inc_cy~99 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~50_combout & (\z80_|execute_|ctl_reg_sel_pc~10_combout & \z80_|execute_|ctl_inc_cy~99_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), + .datab(\z80_|execute_|ctl_inc_cy~50_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .datad(\z80_|execute_|ctl_inc_cy~99_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & +// !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~9_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal47~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF1FF; +defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'hEAFF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~5_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal48~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal48~0_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal48~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h5444; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ))) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~13_combout = (\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout & !\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout )) # +// (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h131F; +defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h00FC; +defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((!\z80_|execute_|ctl_flags_bus~4_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hFF73; +defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( +// Equation(s): +// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|setM1~37_combout & (!\z80_|execute_|ctl_mRead~11_combout & (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal21~1_combout ))) + + .dataa(\z80_|execute_|setM1~37_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h0002; +defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~33_combout = (!\z80_|execute_|ctl_mRead~12_combout & ((\z80_|ir_|opcode [3]) # ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal12~0_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal12~0_combout ), + .datad(\z80_|execute_|ctl_mRead~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h00EF; +defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~35_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & (((\z80_|execute_|fMRead~7_combout & \z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) + + .dataa(\z80_|execute_|fMRead~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'h8C0C; +defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~34_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|pc_inc_hold~33_combout & ((!\z80_|decode_state_|use_ixiy~combout ) # (!\z80_|pla_decode_|Equal33~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|pla_decode_|Equal33~2_combout ), + .datac(\z80_|execute_|pc_inc_hold~33_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h1050; +defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_mWrite~9_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_mRead~34_combout +// & ((\z80_|execute_|ctl_mWrite~9_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~9_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~1_combout = (!\z80_|execute_|ctl_reg_sys_we~0_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'h0155; +defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal48~0_combout & \z80_|sequencer_|DFFE_T4_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~2_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~34_combout & \z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'hFF4F; +defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal8~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0])) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h4400; +defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~1_combout = (\z80_|execute_|ctl_reg_sys_we_lo~0_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( +// Equation(s): +// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal40~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal40~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|sel[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h2AAA; +defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & +// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal52~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h053F; +defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~7_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|execute_|ctl_state_alu~7_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hAA2A; +defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'h00EF; +defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~5_combout = (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|table_xx~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0002; +defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~10_combout = (\z80_|pla_decode_|Equal52~1_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # ((\z80_|execute_|ctl_state_alu~9_combout & \z80_|execute_|ctl_state_alu~5_combout )))) # (!\z80_|pla_decode_|Equal52~1_combout +// & (\z80_|execute_|ctl_state_alu~9_combout & ((\z80_|execute_|ctl_state_alu~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~9_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_state_alu~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'hECA0; +defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|pla_decode_|Equal52~1_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_state_alu~6_combout & +// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'hFA32; +defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~11_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hAAA2; +defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~5_combout = (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal62~2_combout )) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal62~2_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hF777; +defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hABFF; +defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~7_combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~7 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_alu_bs_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~7_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~19_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~19 .lut_mask = 16'hDDDF; +defparam \z80_|execute_|ctl_flags_xy_we~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~2_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~25_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~26_combout = ((!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|execute_|ctl_mRead~34_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_iorw~10_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~28_combout = (\z80_|execute_|ctl_alu_shift_oe~25_combout & (\z80_|execute_|ctl_alu_shift_oe~26_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~27_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~19_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal6~0_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hFF37; +defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~9_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|execute_|ctl_flags_bus~15_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h5070; +defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal20~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|comb~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal20~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal68~2_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|pla_decode_|Equal68~2_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF57; +defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal63~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|execute_|comb~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal63~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal76~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal76~2_combout = (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal76~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal76~2 .lut_mask = 16'h0A00; +defparam \z80_|pla_decode_|Equal76~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~8_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal76~2_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal76~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal32~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|execute_|ixy_d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~7_combout = ((!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_flags_bus~6_combout & !\z80_|pla_decode_|Equal13~2_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~6_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|execute_|ctl_flags_bus~9_combout & (\z80_|execute_|ctl_flags_bus~14_combout & (\z80_|execute_|ctl_flags_bus~8_combout & \z80_|execute_|ctl_flags_bus~7_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~9_combout ), + .datab(\z80_|execute_|ctl_flags_bus~14_combout ), + .datac(\z80_|execute_|ctl_flags_bus~8_combout ), + .datad(\z80_|execute_|ctl_flags_bus~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_bus_db_oe~3_combout & (\z80_|execute_|ctl_flags_xy_we~19_combout & (\z80_|execute_|ctl_alu_shift_oe~28_combout & \z80_|execute_|ctl_flags_bus~10_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datad(\z80_|execute_|ctl_flags_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf2_we~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h0155; +defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel~7_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|decode_state_|table_xx~0_combout ), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel~7 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~12_combout = ((\z80_|execute_|ctl_reg_gp_sel~7_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout ))) # (!\z80_|execute_|ctl_state_alu~7_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|ctl_state_alu~12_combout & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal62~3_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_alu_op_low~19_combout & !\z80_|execute_|ctl_iorw~10_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datab(\z80_|execute_|ctl_iorw~10_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'hFFF1; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~7_combout = (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~10 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~10_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~10 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_pf_sel[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~29_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hAAA2; +defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~11_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~11 .lut_mask = 16'hCCC4; +defparam \z80_|execute_|ctl_flags_pf_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & (\z80_|execute_|ctl_pf_sel[0]~10_combout & \z80_|execute_|ctl_flags_pf_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~10_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal10~1_combout = (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal10~1 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal10~1_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal10~1_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal69~0_combout = (\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal69~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'h0A02; +defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~8_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_pf_we~7_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~13 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~13_combout = (\z80_|ir_|opcode [5]) # (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_state_alu~12_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~13 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_pf_sel[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~10_combout = (((\z80_|execute_|ctl_flags_pf_we~9_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout )) # (!\z80_|execute_|ctl_flags_xy_we~11_combout )) # (!\z80_|execute_|ctl_flags_pf_we~5_combout ) + + .dataa(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N20 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~3_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'h0F1F; +defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~18_combout = (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N0 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|reg_control_|reg_sys_we_lo~3_combout & (\z80_|execute_|ctl_flags_xy_we~18_combout & ((!\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h40C0; +defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~5_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h7700; +defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N10 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~6_combout = (((\z80_|execute_|ctl_reg_sys_we_lo~1_combout & \z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~5_combout ) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'hDF5F; +defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout ) # ((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hFBFB; +defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~21_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (\z80_|execute_|ctl_mRead~20_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datac(\z80_|execute_|ctl_mRead~20_combout ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~21 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_sel_wz~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~20_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal35~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~20 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout = (\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|sequencer_|M5~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~44_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|M5~q ))) + + .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'hAA2A; +defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hF2F0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = (((\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'hF777; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout = ((\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~21_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h4040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~5_combout & ((\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~4_combout )))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_mRead~5_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h2333; +defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~1_combout = (\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((!\z80_|execute_|ctl_al_we~14_combout & \z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~14_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) + + .dataa(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'hABFF; +defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~47 ( +// Equation(s): +// \z80_|execute_|setM1~47_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|setM1~46_combout & !\z80_|execute_|ctl_mWrite~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_al_we~13_combout ), + .datac(\z80_|execute_|setM1~46_combout ), + .datad(\z80_|execute_|ctl_mWrite~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~47 .lut_mask = 16'h00C0; +defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|execute_|ctl_alu_oe~5_combout & !\z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|setM1~47_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~5_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|setM1~47_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ixy_d~6_combout & +// ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h2A3F; +defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( +// Equation(s): +// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal9~1_combout & ((!\z80_|pla_decode_|Equal29~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal9~1_combout & +// !\z80_|pla_decode_|Equal29~0_combout )) # (!\z80_|execute_|ctl_state_alu~3_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|pla_decode_|Equal29~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h0537; +defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( +// Equation(s): +// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~14_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal37~0_combout & +// !\z80_|execute_|ctl_mRead~14_combout )) # (!\z80_|execute_|ctl_state_alu~3_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~9 .lut_mask = 16'h111F; +defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( +// Equation(s): +// \z80_|execute_|fMRead~10_combout = (\z80_|execute_|fMRead~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|fMRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h3700; +defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|fMRead~8_combout & \z80_|execute_|fMRead~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datac(\z80_|execute_|fMRead~8_combout ), + .datad(\z80_|execute_|fMRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|pla_decode_|Equal11~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal4~0_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|execute_|comb~1_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|execute_|comb~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~41 ( +// Equation(s): +// \z80_|execute_|setM1~41_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal4~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~41 .lut_mask = 16'h003F; +defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal2~1_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal2~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & ((\z80_|execute_|setM1~41_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|setM1~41_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h0051; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~3_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~3_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_sw_1d~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datad(\z80_|execute_|ctl_sw_1d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & +// (!\z80_|execute_|ctl_alu_oe~2_combout & ((!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hC0DD; +defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sel_wz~11_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_sw_4d~4_combout & (\z80_|execute_|ctl_sw_4d~2_combout & (\z80_|execute_|ctl_sw_4d~3_combout & \z80_|execute_|ctl_reg_sel_wz~12_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~4_combout ), + .datab(\z80_|execute_|ctl_sw_4d~2_combout ), + .datac(\z80_|execute_|ctl_sw_4d~3_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~6_combout = (\z80_|execute_|ctl_sw_4d~1_combout ) # ((\z80_|execute_|ctl_sw_4d~0_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_4d~1_combout ), + .datac(\z80_|execute_|ctl_sw_4d~0_combout ), + .datad(\z80_|execute_|ctl_sw_4d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N30 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~4_combout = ((!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|alu_control_|flags_cond_true~q ) # (!\z80_|pla_decode_|Equal35~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~4 .lut_mask = 16'h337F; +defparam \z80_|reg_control_|reg_sel_pc~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((!\z80_|execute_|fMRead~4_combout & \z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .datab(\z80_|execute_|fMRead~4_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h7F5F; +defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~17_combout = (\z80_|nM1_int~2_combout ) # (((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|ctl_inc_dec~3_combout )) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_inc_dec~3_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'hBBFB; +defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~19_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal33~3_combout ), + .datac(\z80_|execute_|ctl_al_we~5_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'h4500; +defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal21~1_combout & ((!\z80_|pla_decode_|Equal52~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h030F; +defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sel_pc~14_combout ) # (!\z80_|execute_|setM1~37_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .datab(\z80_|execute_|setM1~37_combout ), + .datac(\z80_|execute_|fMRead~2_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hABAF; +defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~18_combout = (\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~17_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (!\z80_|execute_|ctl_sw_4u~1_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~19_combout = (((!\z80_|pla_decode_|Equal34~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_wz~19_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h0080; +defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~combout = (\z80_|reg_control_|reg_sel_pc~4_combout & (\z80_|reg_control_|reg_sel_pc~3_combout & ((\z80_|execute_|ctl_reg_sel_pc~18_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_pc~4_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~3_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h80A0; +defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h4040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~6_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal1~5_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N24 +cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( +// Equation(s): +// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal1~6_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|reg_control_|bank_exx~q ), + .datad(\z80_|pla_decode_|Equal1~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_exx~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y14_N25 +dffeas \z80_|reg_control_|bank_exx ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_exx~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_exx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_exx .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|execute_|ctl_state_alu~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal77~0_combout ), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hC0C4; +defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mWrite~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout ) # +// (!\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h0737; +defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~56 ( +// Equation(s): +// \z80_|execute_|setM1~56_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~56 .lut_mask = 16'hFF1F; +defparam \z80_|execute_|setM1~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (\z80_|execute_|ctl_sw_2u~4_combout & \z80_|execute_|setM1~56_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_2u~1_combout ), + .datac(\z80_|execute_|ctl_sw_2u~4_combout ), + .datad(\z80_|execute_|setM1~56_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|ir_|opcode [1] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'h30F0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|pla_decode_|Equal11~0_combout & (((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (\z80_|execute_|ctl_mRead~3_combout & +// ((\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hEEC0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~13_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hFF37; +defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & (\z80_|execute_|ctl_state_alu~13_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datac(\z80_|execute_|ctl_state_alu~13_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~61_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|execute_|ixy_d~5_combout & +// !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|execute_|ctl_mRead~14_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h0357; +defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~86_combout = (\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ixy_d~5_combout & +// !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'h111F; +defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~87_combout = (\z80_|execute_|ctl_inc_cy~86_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~86_combout ), + .datab(\z80_|pla_decode_|Equal29~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h222A; +defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~52 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~52_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~52 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_bus_inc_oe~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~49 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~49_combout = (\z80_|execute_|ctl_bus_inc_oe~52_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal4~0_combout )) # (!\z80_|sequencer_|DFFE_T5_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(\z80_|execute_|ctl_bus_inc_oe~52_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal4~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~49 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_bus_inc_oe~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_inc_cy~61_combout & (\z80_|execute_|ctl_bus_inc_oe~28_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_bus_inc_oe~49_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .datac(\z80_|execute_|ctl_inc_cy~87_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|fMRead~10_combout & (\z80_|execute_|fMRead~8_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_reg_gp_we~3_combout ))) + + .dataa(\z80_|execute_|fMRead~10_combout ), + .datab(\z80_|execute_|fMRead~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = ((!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h15FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~7_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h0105; +defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|execute_|ctl_alu_oe~7_combout & (((!\z80_|execute_|ctl_mRead~25_combout & !\z80_|execute_|ctl_mRead~24_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~25_combout ), + .datac(\z80_|execute_|ctl_mRead~24_combout ), + .datad(\z80_|execute_|ctl_alu_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & (\z80_|execute_|ctl_flags_pf_we~5_combout & (\z80_|execute_|ctl_pf_sel[0]~13_combout & \z80_|execute_|ctl_alu_oe~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .datad(\z80_|execute_|ctl_alu_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_mRead~4_combout & !\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (!\z80_|pla_decode_|Equal13~2_combout & (\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|ctl_flags_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~12_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [4]), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hCCFF; +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~8_combout = (!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ctl_alu_op_low~19_combout & (\z80_|execute_|ctl_flags_hf_cpl~12_combout & !\z80_|pla_decode_|Equal68~2_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .datad(\z80_|pla_decode_|Equal68~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~8 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_flags_hf_cpl~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~48 ( +// Equation(s): +// \z80_|execute_|setM1~48_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~48 .lut_mask = 16'h0013; +defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|pla_decode_|Equal20~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h0033; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~2 ( +// Equation(s): +// \z80_|execute_|nextM~2_combout = (!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|execute_|ctl_alu_op_low~18_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0003; +defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~49 ( +// Equation(s): +// \z80_|execute_|setM1~49_combout = (\z80_|execute_|ctl_flags_hf_cpl~8_combout & (\z80_|execute_|setM1~48_combout & (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & \z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), + .datab(\z80_|execute_|setM1~48_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~49 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~12_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|setM1~49_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_flags_oe~1_combout ), + .datad(\z80_|execute_|setM1~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'h0444; +defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~8_combout = (((\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal12~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h77F7; +defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_sw_1d~8_combout ), + .datac(\z80_|execute_|ctl_sw_1d~4_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h40F0; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|execute_|ctl_mRead~24_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|execute_|ctl_mRead~24_combout & +// (((!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal20~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~24_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_mWrite~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ctl_mWrite~8_combout & +// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (!\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~25_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|nextM~11 ( +// Equation(s): +// \z80_|execute_|nextM~11_combout = ((!\z80_|execute_|ctl_alu_op_low~18_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_mWrite~5_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~11 .lut_mask = 16'h5557; +defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|execute_|ctl_alu_op_low~18_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|nextM~11_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_bus_inc_oe~51_combout & \z80_|execute_|ctl_reg_use_sp~2_combout ))) + + .dataa(\z80_|execute_|nextM~11_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~51_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal6~1_combout )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0500; +defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~13_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_sw_1d~9_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .lut_mask = 16'h0133; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~12_combout = (!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & !\z80_|pla_decode_|Equal49~0_combout )) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_oe~3_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .lut_mask = 16'h0005; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & +// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'hF010; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # (\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~30 ( +// Equation(s): +// \z80_|execute_|setM1~30_combout = (\z80_|execute_|ctl_mRead~15_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|execute_|ctl_mRead~15_combout & +// (((!\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~30 .lut_mask = 16'h0777; +defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|ctl_mRead~23_combout & (\z80_|execute_|setM1~30_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ctl_mRead~23_combout ), + .datac(\z80_|execute_|setM1~30_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~14_combout = (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((!\z80_|execute_|ctl_reg_sys_hilo~20_combout & \z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h4F00; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|execute_|ctl_mRead~5_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal2~1_combout & \z80_|pla_decode_|Equal1~4_combout )))) + + .dataa(\z80_|pla_decode_|Equal2~1_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal4~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'hF080; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~20_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .lut_mask = 16'h3332; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~21_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal11~0_combout ))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h7F00; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ) # ((\z80_|ir_|opcode [2] & ((!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .datab(\z80_|execute_|ctl_sw_2u~5_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'hBFAA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|decode_state_|DFFE_instIY1~q ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|pla_decode_|Equal50~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hEEEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_mRead~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hA2AA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ) # ((\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & ((\z80_|sequencer_|M5~q ) # (\z80_|sequencer_|DFFE_M4_ff~q )))) + + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h1110; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~36_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [6] & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [7]))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|ir_|opcode [3] & (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal12~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hA2AF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~8_combout )) # (!\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout & \z80_|execute_|ctl_ir_we~6_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_ir_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hACA0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'hB030; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N2 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~2_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~2 .lut_mask = 16'h00F0; +defparam \z80_|reg_control_|reg_sel_de2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~4_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|decode_state_|DFFE_inst4~q & !\z80_|decode_state_|DFFE_instIY1~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'h0004; +defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N12 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((!\z80_|reg_control_|bank_exx~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal2~2_combout )))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|reg_control_|bank_hl_de1~q ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hE1F0; +defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N13 +dffeas \z80_|reg_control_|bank_hl_de1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N28 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~2_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~4_combout ))))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|reg_control_|reg_sel_de2~2_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|reg_control_|bank_hl_de1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h4450; +defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal8~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~50 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~50_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~50 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_bus_inc_oe~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_bus_inc_oe~50_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~50_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & (\z80_|execute_|ctl_reg_gp_we~2_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h1500; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|execute_|ixy_d~9_combout ) # +// (!\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h0737; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h3230; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # ((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|ctl_mRead~23_combout ) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ctl_mRead~23_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'hFBF3; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (\z80_|execute_|ctl_ir_we~7_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~20_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ) # ((\z80_|execute_|ctl_iorw~11_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .datab(\z80_|execute_|ctl_iorw~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h00A0; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'h0133; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # +// (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|rsel3 ( +// Equation(s): +// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(gnd), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|rsel3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel3 .lut_mask = 16'h5AAA; +defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = (\z80_|execute_|rsel3~combout & (((\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'h08CC; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_flags_oe~1_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h040F; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~14_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFDF0; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel~7_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|rsel0 ( +// Equation(s): +// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|rsel0~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel0 .lut_mask = 16'h66AA; +defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout & ((\z80_|execute_|rsel0~combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|execute_|setM1~49_combout )))) # +// (!\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|execute_|setM1~49_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|setM1~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'h888F; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal3~1_combout & !\z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_sw_1d~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~6_combout = (!\z80_|execute_|ctl_reg_in_hi~7_combout & (\z80_|execute_|ctl_state_alu~13_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & !\z80_|execute_|ctl_reg_in_hi~12_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .datab(\z80_|execute_|ctl_state_alu~13_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'h0004; +defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~9_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~16_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_sw_1d~9_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~9 .lut_mask = 16'h070F; +defparam \z80_|execute_|ctl_reg_gp_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'h0015; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (\z80_|execute_|ctl_reg_gp_we~9_combout & \z80_|execute_|ctl_alu_sel_op2_neg~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~9_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h5155; +defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~7_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & (\z80_|execute_|ctl_reg_gp_we~5_combout & \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((!\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h31F5; +defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|ctl_sw_4u~2_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datac(\z80_|execute_|ctl_sw_4u~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~8_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (((!\z80_|execute_|ctl_sw_4u~3_combout ) # (!\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(\z80_|execute_|ctl_sw_4u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~8 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_gp_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|reg_control_|reg_sel_hl~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N16 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|reg_control_|bank_exx~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal2~2_combout )))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; +defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N17 +dffeas \z80_|reg_control_|bank_hl_de2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de2~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~2_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~4_combout )))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|reg_control_|bank_hl_de2~q ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hA820; +defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|reg_control_|reg_sel_hl2~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|reg_control_|reg_sel_hl2~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|pla_decode_|Equal52~1_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_state_alu~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout = (\z80_|sequencer_|DFFE_M3_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal3~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal24~0_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|execute_|ctl_reg_in_hi~8_combout & (!\z80_|execute_|ctl_66_oe~2_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout & \z80_|execute_|ctl_reg_gp_we~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~8_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~21_combout ) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h070F; +defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|pla_decode_|Equal6~1_combout & !\z80_|execute_|ctl_mRead~2_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_sw_2d~6_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~8_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_alu_shift_oe~44_combout & \z80_|execute_|ctl_sw_2d~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .datad(\z80_|execute_|ctl_sw_2d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h5500; +defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N4 +cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( +// Equation(s): +// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|execute_|ctl_mRead~16_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & +// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( +// Equation(s): +// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~7_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~7_combout ), + .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h0888; +defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( +// Equation(s): +// \z80_|execute_|fMRead~20_combout = (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|ctl_mWrite~10_combout & (\z80_|execute_|fMRead~18_combout & \z80_|execute_|fMRead~19_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~10_combout ), + .datac(\z80_|execute_|fMRead~18_combout ), + .datad(\z80_|execute_|fMRead~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~20 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h1115; +defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Equation(s): +// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|fMRead~20_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_in_hi~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~22_combout ), + .datab(\z80_|execute_|fMRead~20_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~21 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h20AA; +defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & (\z80_|execute_|fMRead~21_combout & \z80_|execute_|ctl_sw_2d~5_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~8_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .datac(\z80_|execute_|fMRead~21_combout ), + .datad(\z80_|execute_|ctl_sw_2d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|pla_decode_|Equal49~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hAA8A; +defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (\z80_|execute_|ctl_sw_2d~9_combout & (!\z80_|execute_|ctl_sw_1d~5_combout & \z80_|execute_|ctl_sw_1d~4_combout ))) + + .dataa(\z80_|execute_|ctl_im_we~combout ), + .datab(\z80_|execute_|ctl_sw_2d~9_combout ), + .datac(\z80_|execute_|ctl_sw_1d~5_combout ), + .datad(\z80_|execute_|ctl_sw_1d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|execute_|ctl_66_oe~2_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7733; +defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~41_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~18_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~41 .lut_mask = 16'h3BFF; +defparam \z80_|execute_|ctl_alu_op_low~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal44~0_combout & ((\z80_|ir_|opcode [0]) # (!\z80_|execute_|comb~0_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|comb~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal44~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & !\z80_|execute_|ctl_reg_gp_sel~7_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~7_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|execute_|ctl_alu_op_low~17_combout & (((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) # (!\z80_|execute_|ctl_alu_op_low~17_combout & +// (\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0155; +defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~27_combout = ((\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~20_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~26_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & ((\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~41_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hF300; +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal61~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal61~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h222A; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~12_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~12 .lut_mask = 16'h3B3F; +defparam \z80_|execute_|ctl_alu_core_hf~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_core_hf~12_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & +// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~13_combout = (((!\z80_|execute_|ixy_d~6_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_flags_sz_we~3_combout & (\z80_|execute_|ctl_flags_alu~13_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & !\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datab(\z80_|execute_|ctl_flags_alu~13_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~15_combout = (\z80_|execute_|ctl_flags_alu~14_combout & (\z80_|execute_|ctl_flags_xy_we~9_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|execute_|ctl_flags_alu~14_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|nextM~11_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~16_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~17_combout = (\z80_|execute_|ctl_alu_op_low~16_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal20~0_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'hF070; +defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .lut_mask = 16'h010F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~39_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~39 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~16_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (!\z80_|execute_|ctl_alu_op_low~39_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~39_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h020A; +defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~17_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_alu~16_combout ))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datac(\z80_|execute_|ctl_sw_2d~4_combout ), + .datad(\z80_|execute_|ctl_flags_alu~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~23_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'h0F5F; +defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~18_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_alu_op_low~23_combout & \z80_|execute_|ctl_sw_4u~1_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datab(\z80_|execute_|ctl_flags_alu~17_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~11_combout = (((!\z80_|execute_|ctl_flags_alu~10_combout ) # (!\z80_|execute_|ctl_flags_alu~22_combout )) # (!\z80_|execute_|ctl_flags_alu~20_combout )) # (!\z80_|execute_|ctl_flags_alu~21_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~21_combout ), + .datab(\z80_|execute_|ctl_flags_alu~20_combout ), + .datac(\z80_|execute_|ctl_flags_alu~22_combout ), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal1~5_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal1~5_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .lut_mask = 16'h0050; +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFFC4; +defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~23 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~23_combout = (\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~23 .lut_mask = 16'hF040; +defparam \z80_|execute_|ctl_flags_alu~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_flags_alu~11_combout ) # (((\z80_|execute_|ctl_alu_core_R~1_combout ) # (\z80_|execute_|ctl_flags_alu~23_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~3_combout )) + + .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datad(\z80_|execute_|ctl_flags_alu~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~11_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .lut_mask = 16'hF5F1; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~6_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mWrite~17_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (((!\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~17 ( +// Equation(s): +// \z80_|execute_|setM1~17_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (!\z80_|execute_|ctl_alu_shift_oe~15_combout & \z80_|execute_|ctl_state_alu~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_2u~1_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~17 .lut_mask = 16'h0C00; +defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~22_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'h0015; +defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|execute_|setM1~17_combout & (!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|setM1~17_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_alu_oe~6_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & \z80_|execute_|ctl_flags_xy_we~18_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~6_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~11_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_flags_xy_we~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~19_combout = (((\z80_|execute_|ctl_flags_alu~12_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_alu~18_combout )) # (!\z80_|execute_|ctl_flags_alu~15_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), + .datab(\z80_|execute_|ctl_flags_alu~18_combout ), + .datac(\z80_|execute_|ctl_flags_alu~12_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~19 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_alu~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFFE0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( +// Equation(s): +// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~12_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # +// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~26 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal52~0_combout )) + + .dataa(\z80_|pla_decode_|Equal44~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'hEEAA; +defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~11_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_bus~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'hF070; +defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~13_combout = ((\z80_|execute_|ctl_flags_hf2_we~combout ) # (\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|fMRead~26_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|fMRead~26_combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'hFFF3; +defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~combout = ((\z80_|execute_|ctl_flags_bus~13_combout ) # ((!\z80_|execute_|ctl_flags_bus~10_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~28_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~3_combout ) + + .dataa(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datab(\z80_|execute_|ctl_flags_bus~13_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datad(\z80_|execute_|ctl_flags_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|alu_control_|db[1]~27_combout & \z80_|execute_|ctl_flags_bus~combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .datab(\z80_|alu_control_|db[1]~27_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEFA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~12_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|nextM~11_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFEAA; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = (\z80_|execute_|ctl_alu_op_low~39_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~39_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~18_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datad(\z80_|pla_decode_|Equal48~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~18 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h0507; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_ir_we~14_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout +// & (((!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_flags_alu~20_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~18_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~18_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~25_combout ) # (\z80_|execute_|ctl_mRead~24_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~19_combout ) + + .dataa(\z80_|execute_|ctl_mRead~25_combout ), + .datab(\z80_|execute_|ctl_mRead~24_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hE0FF; +defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~24_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'h0BFF; +defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ctl_alu_op_low~24_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'h2200; +defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~17_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .lut_mask = 16'h3230; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (!\z80_|execute_|ctl_alu_op1_sel_bus~17_combout & (!\z80_|execute_|ctl_alu_op_low~20_combout & ((!\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0105; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & \z80_|execute_|ctl_alu_shift_oe~38_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|execute_|ctl_ir_we~11_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|execute_|ctl_alu_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAA20; +defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~39_combout = ((\z80_|execute_|ctl_alu_shift_oe~37_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~42_combout = ((\z80_|execute_|ctl_alu_shift_oe~40_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # (!\z80_|execute_|ctl_alu_op_low~25_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hC0C8; +defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~8_combout = (\z80_|execute_|ctl_alu_bs_oe~12_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~7_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|execute_|ctl_ir_we~7_combout & (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # +// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h7740; +defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_ir_we~10_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h5540; +defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~36_combout = ((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~1_combout ) # (!\z80_|execute_|ctl_flags_bus~10_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .datac(\z80_|execute_|ctl_flags_bus~10_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~7_combout )))) # (!\z80_|execute_|ctl_bus_db_oe~1_combout & ((\z80_|execute_|ixy_d~7_combout ) +// # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~7_combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'hF444; +defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~29_combout = ((\z80_|execute_|ctl_alu_shift_oe~24_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~28_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~44_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_ir_we~7_combout & (((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~10_combout +// & (\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'hECE0; +defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~8_combout ) # ((\z80_|pla_decode_|Equal41~2_combout & \z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~23_combout = (!\z80_|execute_|ctl_alu_bs_oe~combout & (((\z80_|execute_|ixy_d~15_combout & !\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~23_combout ))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h020F; +defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) # +// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (\z80_|execute_|ctl_sw_4u~1_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~32_combout = (\z80_|execute_|ctl_alu_shift_oe~30_combout & (\z80_|execute_|ctl_alu_shift_oe~31_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~7_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~23_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~10_combout & ((\z80_|execute_|ctl_alu_shift_oe~29_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hCCEF; +defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~17_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h88A8; +defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~18_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h7740; +defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~18_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~18_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'h5F40; +defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_alu_shift_oe~19_combout ) # (\z80_|execute_|ctl_mWrite~9_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~19_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h7470; +defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~20_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~20_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'h5C4C; +defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~22_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~21_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h0E0C; +defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~36_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~22_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & +// (((!\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~2_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & \z80_|reg_control_|reg_sys_we_lo~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_ir_we~9_combout & +// (((!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_ir_we~10_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|nM1_int~2_combout & +// (((!\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & (!\z80_|execute_|ctl_alu_oe~15_combout & \z80_|execute_|ctl_alu_res_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datac(\z80_|execute_|ctl_alu_oe~15_combout ), + .datad(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~15_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_alu_res_oe~1_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datad(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'hA0E0; +defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~0_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hEFCF; +defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~0 ( +// Equation(s): +// \z80_|alu_|db_high[3]~0_combout = (\z80_|execute_|ctl_alu_bs_oe~combout ) # (((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (\z80_|execute_|ctl_alu_op1_oe~1_combout )) # (!\z80_|execute_|ctl_alu_res_oe~2_combout )) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~0 .lut_mask = 16'hFFFB; +defparam \z80_|alu_|db_high[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'h0103; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout & (\z80_|execute_|nextM~11_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .datac(\z80_|execute_|nextM~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~53 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|pla_decode_|Equal21~1_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_sw_2u~2_combout & ((!\z80_|execute_|ctl_mRead~6_combout ) # (!\z80_|execute_|ctl_alu_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2u~0_combout ), + .datab(\z80_|execute_|ctl_sw_2u~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_sw_2u~5_combout & (\z80_|execute_|ctl_reg_gp_sel~7_combout & (\z80_|ir_|opcode [0] $ (!\z80_|execute_|comb~0_combout )))) # (!\z80_|execute_|ctl_sw_2u~5_combout & ((\z80_|ir_|opcode [0] $ +// (!\z80_|execute_|comb~0_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2u~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'hD00D; +defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFAEA; +defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~3_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|rsel3~combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7077; +defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout & (!\z80_|execute_|ctl_sw_2u~6_combout & \z80_|execute_|ctl_reg_out_hi~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .datac(\z80_|execute_|ctl_sw_2u~6_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~7_combout = ((\z80_|execute_|ctl_reg_out_hi~8_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ))) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = ((\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|execute_|setM1~47_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datab(\z80_|execute_|setM1~47_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'h7F0F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'h0EFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~30_combout ) + + .dataa(\z80_|execute_|ctl_al_we~14_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|setM1~30_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'hDF0F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & !\z80_|execute_|rsel3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFCFD; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ) # ((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hFF75; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # (!\z80_|execute_|ctl_reg_gp_we~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h2202; +defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~15_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~6_combout = ((\z80_|execute_|ctl_reg_use_sp~5_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout )) # (!\z80_|execute_|ctl_reg_use_sp~3_combout ) + + .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hFF5F; +defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N26 +cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( +// Equation(s): +// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal21~2_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N27 +dffeas \z80_|reg_control_|bank_af ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_af~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_af~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_af .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N30 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h4040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~32 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[3]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~3_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~4_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~2_combout ))))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|reg_control_|bank_hl_de2~q ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~3 .lut_mask = 16'hA280; +defparam \z80_|reg_control_|reg_sel_de2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~4_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~2_combout )))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|reg_control_|reg_sel_de2~2_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|reg_control_|bank_hl_de1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h5044; +defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_de~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_de~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~31 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[3]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_iy~2_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|decode_state_|DFFE_inst4~q & \z80_|decode_state_|DFFE_instIY1~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hCC00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h4000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h3030; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|decode_state_|DFFE_inst4~q & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h4000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~34_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~34 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~15_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # (((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout )) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~16_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ctl_sw_4u~4_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h0015; +defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~50_combout & \z80_|execute_|ctl_inc_cy~99_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_cy~50_combout ), + .datad(\z80_|execute_|ctl_inc_cy~99_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & (\z80_|execute_|fMRead~6_combout & (\z80_|execute_|ctl_reg_sel_wz~16_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .datab(\z80_|execute_|fMRead~6_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~18_combout = ((\z80_|execute_|ctl_reg_sel_wz~15_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~21_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~17_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~18_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~18_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~36_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~36 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[3]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h1000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~33 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[3]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; +defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~10_combout = (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|execute_|ctl_reg_in_hi~10_combout ) # (!\z80_|execute_|ctl_reg_in_hi~9_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout )) # (!\z80_|execute_|ctl_reg_in_hi~3_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [3] & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[3]~14_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .datad(\z80_|alu_|db[3]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~37_combout = (\z80_|reg_file_|gdfx_temp1[3]~34_combout & (\z80_|reg_file_|gdfx_temp1[3]~36_combout & (\z80_|reg_file_|gdfx_temp1[3]~33_combout & \z80_|reg_file_|gdfx_temp1[3]~35_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~37 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~38_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout & (\z80_|reg_file_|gdfx_temp1[3]~32_combout & (\z80_|reg_file_|gdfx_temp1[3]~31_combout & \z80_|reg_file_|gdfx_temp1[3]~37_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~38 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # (((\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hEAFF; +defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~6_combout = ((\z80_|execute_|ctl_sw_4u~5_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~17_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout ))) # (!\z80_|execute_|ctl_sw_4u~3_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~3_combout ), + .datab(\z80_|execute_|ctl_sw_4u~5_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFEC; +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~11_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~16_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~39_combout = ((\z80_|reg_file_|gdfx_temp1[3]~38_combout & ((\z80_|reg_file_|db_hi_as[3]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~39 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|gdfx_temp1[3]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N24 +cycloneive_lcell_comb \z80_|alu_|db[3]~13 ( +// Equation(s): +// \z80_|alu_|db[3]~13_combout = (\z80_|alu_|db_low[3]~26_combout & (((\z80_|reg_file_|gdfx_temp1[3]~39_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) # (!\z80_|alu_|db_low[3]~26_combout & (!\z80_|execute_|ctl_alu_oe~14_combout & +// ((\z80_|reg_file_|gdfx_temp1[3]~39_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) + + .dataa(\z80_|alu_|db_low[3]~26_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .datad(\z80_|execute_|ctl_alu_oe~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~13 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~20_combout ) # (\z80_|execute_|ctl_alu_shift_oe~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hEEEA; +defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~11_combout )) # (!\z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|nextM~2_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|rsel3~combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'hC444; +defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~12_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal77~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h3313; +defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_2d~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~8_combout ), + .datac(\z80_|execute_|ctl_sw_2d~10_combout ), + .datad(\z80_|execute_|ctl_sw_2d~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hF2FA; +defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~12_combout ) # ((\z80_|execute_|ctl_sw_2d~11_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~12_combout ), + .datac(\z80_|execute_|ctl_sw_2d~11_combout ), + .datad(\z80_|execute_|ctl_sw_2d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~30_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ctl_mRead~24_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datac(\z80_|execute_|ctl_mWrite~11_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|execute_|ctl_bus_db_we~5_combout & (\z80_|execute_|ctl_alu_oe~9_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|ctl_alu_oe~4_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~5_combout ), + .datab(\z80_|execute_|ctl_alu_oe~9_combout ), + .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datad(\z80_|execute_|ctl_alu_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_alu_oe~10_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .datac(\z80_|execute_|ctl_alu_oe~10_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|alu_control_|db[3]~36_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_flags_alu~19_combout )))) # (!\z80_|alu_control_|db[3]~36_combout & +// (((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_flags_alu~19_combout )))) + + .dataa(\z80_|alu_control_|db[3]~36_combout ), + .datab(\z80_|execute_|ctl_flags_bus~combout ), + .datac(\z80_|alu_|db_low[3]~26_combout ), + .datad(\z80_|execute_|ctl_flags_alu~19_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_ir_we~12_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & \z80_|pla_decode_|Equal56~0_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal56~0_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~14_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_flags_xy_we~13_combout ) # (!\z80_|execute_|ctl_flags_xy_we~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hFFCF; +defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~15_combout = (\z80_|execute_|ctl_flags_xy_we~14_combout ) # (((!\z80_|execute_|ctl_flags_xy_we~17_combout ) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) + + .dataa(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|execute_|ctl_flags_sz_we~5_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # +// (!\z80_|execute_|ctl_alu_core_R~0_combout & (\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_flags_xy_we~15_combout ) # (((!\z80_|execute_|ctl_flags_pf_we~5_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) + + .dataa(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N19 +dffeas \z80_|alu_flags_|flags_xf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_xf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_xf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~50 ( +// Equation(s): +// \z80_|execute_|setM1~50_combout = (!\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|setM1~49_combout & ((!\z80_|pla_decode_|Equal3~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|setM1~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~50 .lut_mask = 16'h0700; +defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )) # (!\z80_|execute_|setM1~50_combout ))) + + .dataa(\z80_|execute_|setM1~50_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_flags_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h3133; +defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( +// Equation(s): +// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h1333; +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( +// Equation(s): +// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) + + .dataa(\z80_|alu_flags_|flags_xf~q ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(gnd), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'hBB00; +defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N0 +cycloneive_lcell_comb \z80_|sw1_|db_down[3]~3 ( +// Equation(s): +// \z80_|sw1_|db_down[3]~3_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_sw_1d~6_combout ), + .datab(\z80_|bus_control_|db[3]~21_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[3]~3 .lut_mask = 16'hECEE; +defparam \z80_|sw1_|db_down[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h5500; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h0808; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h4400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N9 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~51_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N7 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h4040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h0008; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[3]~36_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .datad(\z80_|alu_control_|db[3]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hC4C4; +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|decode_state_|DFFE_inst4~q & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h4000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h2000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0100; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0004; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & (\z80_|reg_file_|gdfx_temp0[3]~46_combout & \z80_|reg_file_|gdfx_temp0[3]~47_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_de~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~51_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_de~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N13 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~42 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[3]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N15 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~49_combout & (\z80_|reg_file_|gdfx_temp0[3]~42_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~42_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~91 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~91_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & ((\z80_|reg_control_|reg_sel_hl2~0_combout ) # (\z80_|reg_control_|reg_sel_hl~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~91_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~91 .lut_mask = 16'h2220; +defparam \z80_|reg_file_|gdfx_temp0[0]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # (\z80_|execute_|ctl_sw_4u~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~19_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~91_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ) # (\z80_|reg_file_|gdfx_temp0[0]~20_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~91_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal11~0_combout )) # +// (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h113F; +defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~43_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & (\z80_|execute_|ctl_bus_inc_oe~42_combout & (\z80_|execute_|ctl_bus_inc_oe~28_combout & !\z80_|execute_|ctl_reg_sys_we~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~88_combout = (\z80_|execute_|ctl_inc_cy~87_combout & (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_inc_cy~87_combout ), + .datac(\z80_|execute_|ctl_sw_4u~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_inc_cy~61_combout & (\z80_|execute_|ctl_inc_cy~88_combout & \z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), + .datab(\z80_|execute_|ctl_inc_cy~88_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~38_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|fMRead~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), + .datad(\z80_|execute_|fMRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hA8AA; +defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_bus_inc_oe~38_combout ) # (((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~49_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~32_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_mRead~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|pla_decode_|Equal13~2_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~47_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((!\z80_|execute_|ctl_bus_inc_oe~34_combout ) # (!\z80_|execute_|nextM~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~48_combout = (\z80_|execute_|ctl_bus_inc_oe~47_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~37_combout & (\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'hCCEC; +defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~46_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~4_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'h00C8; +defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_bus_inc_oe~39_combout ) # (((\z80_|execute_|ctl_bus_inc_oe~48_combout ) # (\z80_|execute_|ctl_bus_inc_oe~46_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~50_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~39_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~50_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~44_combout = (((\z80_|execute_|ctl_bus_inc_oe~40_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~6_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (\z80_|execute_|ctl_apin_mux~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datad(\z80_|execute_|ctl_apin_mux~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h0700; +defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|execute_|ctl_sw_4d~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~44_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~25 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~25_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|decode_state_|in_halt~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(gnd), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~25 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|pc_inc_hold~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~67_combout = ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout ) # (\z80_|execute_|ctl_mRead~2_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~64_combout = ((!\z80_|execute_|ctl_alu_op_low~14_combout & ((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) # (!\z80_|pla_decode_|Equal10~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h1F3F; +defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~65_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ) # (!\z80_|execute_|ctl_inc_cy~64_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout )) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .datad(\z80_|execute_|ctl_inc_cy~64_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~34_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h80A0; +defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~66_combout = ((\z80_|execute_|ctl_inc_cy~65_combout ) # (\z80_|execute_|ctl_inc_cy~63_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datab(\z80_|execute_|ctl_inc_cy~65_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_cy~63_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'hFFDD; +defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~66_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~67_combout ) # (!\z80_|execute_|fMRead~7_combout )))) + + .dataa(\z80_|execute_|fMRead~7_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_inc_cy~67_combout ), + .datad(\z80_|execute_|ctl_inc_cy~66_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hFFC4; +defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~58_combout = (\z80_|execute_|ctl_mWrite~6_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ixy_d~9_combout )))) # (!\z80_|execute_|ctl_mWrite~6_combout & +// (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'hECA0; +defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_inc_cy~58_combout ) # (((\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|execute_|ctl_inc_cy~99_combout )) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|execute_|ctl_inc_cy~58_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_inc_cy~99_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'hECFF; +defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~60_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_inc_cy~59_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datad(\z80_|execute_|ctl_inc_cy~59_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|ctl_inc_cy~97_combout ) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_inc_cy~97_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hEF0F; +defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~62_combout = ((\z80_|execute_|ctl_inc_cy~60_combout ) # ((\z80_|execute_|ctl_inc_cy~57_combout ) # (!\z80_|execute_|ctl_inc_cy~47_combout ))) # (!\z80_|execute_|ctl_inc_cy~61_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), + .datab(\z80_|execute_|ctl_inc_cy~60_combout ), + .datac(\z80_|execute_|ctl_inc_cy~57_combout ), + .datad(\z80_|execute_|ctl_inc_cy~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~18 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~18_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ctl_mRead~13_combout +// & (\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~18 .lut_mask = 16'hEAC8; +defparam \z80_|execute_|pc_inc_hold~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal33~2_combout & \z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal33~2_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~17 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~17_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # (!\z80_|execute_|pc_inc_hold~14_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|pc_inc_hold~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~17 .lut_mask = 16'hECFC; +defparam \z80_|execute_|pc_inc_hold~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~19 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~19_combout = (\z80_|pla_decode_|Equal6~1_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_mRead~8_combout & +// ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~19 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|pc_inc_hold~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~20 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~20_combout = (\z80_|execute_|pc_inc_hold~18_combout ) # ((\z80_|execute_|pc_inc_hold~17_combout ) # ((\z80_|execute_|pc_inc_hold~19_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~18_combout ), + .datab(\z80_|execute_|pc_inc_hold~17_combout ), + .datac(\z80_|execute_|pc_inc_hold~19_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~20 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|pc_inc_hold~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~36_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hA080; +defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~15 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~15_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~15 .lut_mask = 16'hFF57; +defparam \z80_|execute_|pc_inc_hold~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~16 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~16_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~16 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|pc_inc_hold~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~21 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~21_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|pc_inc_hold~15_combout & \z80_|execute_|pc_inc_hold~16_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~20_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|pc_inc_hold~15_combout ), + .datad(\z80_|execute_|pc_inc_hold~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~21 .lut_mask = 16'h1000; +defparam \z80_|execute_|pc_inc_hold~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|pc_inc_hold~25_combout & (((\z80_|execute_|ctl_inc_cy~62_combout & \z80_|execute_|pc_inc_hold~21_combout )))) # (!\z80_|execute_|pc_inc_hold~25_combout & ((\z80_|execute_|ctl_inc_cy~68_combout ) # +// ((\z80_|execute_|ctl_inc_cy~62_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~25_combout ), + .datab(\z80_|execute_|ctl_inc_cy~68_combout ), + .datac(\z80_|execute_|ctl_inc_cy~62_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hF454; +defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~52_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|pla_decode_|Equal24~0_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ixy_d~10_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ixy_d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hC800; +defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~22 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~22_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~22 .lut_mask = 16'hCCC0; +defparam \z80_|execute_|pc_inc_hold~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~23 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~23_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|pc_inc_hold~22_combout )))) # +// (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|pc_inc_hold~22_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|pc_inc_hold~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~23 .lut_mask = 16'hECA0; +defparam \z80_|execute_|pc_inc_hold~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~35_combout = (\z80_|execute_|pc_inc_hold~23_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|pc_inc_hold~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'hFF80; +defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~24 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~24_combout = (!\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout & (!\z80_|execute_|pc_inc_hold~34_combout & (!\z80_|execute_|pc_inc_hold~35_combout & \z80_|execute_|pc_inc_hold~21_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .datab(\z80_|execute_|pc_inc_hold~34_combout ), + .datac(\z80_|execute_|pc_inc_hold~35_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~24 .lut_mask = 16'h0100; +defparam \z80_|execute_|pc_inc_hold~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_inc_cy~52_combout & \z80_|execute_|pc_inc_hold~24_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~52_combout ), + .datac(gnd), + .datad(\z80_|execute_|pc_inc_hold~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~54_combout = (\z80_|execute_|ctl_mWrite~17_combout & (\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_inc_cy~53_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_inc_cy~53_combout ), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'h8088; +defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~74_combout = (((!\z80_|pla_decode_|Equal33~1_combout ) # (!\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~75_combout = ((!\z80_|execute_|pc_inc_hold~17_combout & (\z80_|execute_|ctl_inc_cy~74_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ))) # (!\z80_|execute_|pc_inc_hold~25_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|ctl_inc_cy~74_combout ), + .datac(\z80_|execute_|pc_inc_hold~25_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h0F4F; +defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~73_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|execute_|ctl_sw_4u~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), + .datab(\z80_|execute_|pc_inc_hold~20_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h3020; +defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~75_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_inc_cy~73_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~95 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~95_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~95_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~95 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_inc_cy~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~72_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|pc_inc_hold~15_combout & !\z80_|execute_|ctl_inc_cy~95_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~20_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|pc_inc_hold~15_combout ), + .datad(\z80_|execute_|ctl_inc_cy~95_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~27 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~27_combout = (\z80_|execute_|pc_inc_hold~18_combout ) # ((\z80_|execute_|pc_inc_hold~17_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~18_combout ), + .datab(\z80_|execute_|pc_inc_hold~17_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~27 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|pc_inc_hold~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~77_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & (\z80_|execute_|ctl_mRead~12_combout & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~78_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~77_combout ) # ((!\z80_|execute_|pc_inc_hold~17_combout & !\z80_|execute_|ctl_reg_sys_hilo~20_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|pc_inc_hold~17_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datad(\z80_|execute_|ctl_inc_cy~77_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'hAA02; +defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout ) # ((!\z80_|execute_|pc_inc_hold~27_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~27_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|ctl_inc_cy~78_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'hFF40; +defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # ((\z80_|execute_|pc_inc_hold~25_combout & ((\z80_|execute_|pc_inc_hold~20_combout ) # (!\z80_|execute_|pc_inc_hold~15_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), + .datab(\z80_|execute_|pc_inc_hold~15_combout ), + .datac(\z80_|execute_|pc_inc_hold~25_combout ), + .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFABA; +defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~71_combout = ((!\z80_|execute_|ctl_inc_cy~64_combout & (!\z80_|execute_|pc_inc_hold~34_combout & \z80_|execute_|pc_inc_hold~21_combout ))) # (!\z80_|execute_|ctl_inc_cy~70_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~64_combout ), + .datab(\z80_|execute_|pc_inc_hold~34_combout ), + .datac(\z80_|execute_|ctl_inc_cy~70_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h1F0F; +defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~76_combout ) # ((\z80_|execute_|ctl_inc_cy~72_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout ) # (\z80_|execute_|ctl_inc_cy~71_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), + .datab(\z80_|execute_|ctl_inc_cy~72_combout ), + .datac(\z80_|execute_|ctl_inc_cy~79_combout ), + .datad(\z80_|execute_|ctl_inc_cy~71_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & ((\z80_|execute_|pc_inc_hold~24_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) # +// (!\z80_|execute_|ctl_inc_cy~94_combout & (((\z80_|execute_|pc_inc_hold~24_combout )) # (!\z80_|execute_|pc_inc_hold~25_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), + .datab(\z80_|execute_|pc_inc_hold~25_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datad(\z80_|execute_|pc_inc_hold~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hF531; +defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~26 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~26_combout = (\z80_|execute_|pc_inc_hold~34_combout ) # ((\z80_|execute_|pc_inc_hold~35_combout ) # (!\z80_|execute_|pc_inc_hold~21_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|pc_inc_hold~34_combout ), + .datac(\z80_|execute_|pc_inc_hold~35_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~26 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|pc_inc_hold~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~56_combout = (\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|pc_inc_hold~26_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~55_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'hAAEA; +defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|execute_|ctl_inc_cy~69_combout ) # ((\z80_|execute_|ctl_inc_cy~54_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~56_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), + .datab(\z80_|execute_|ctl_inc_cy~54_combout ), + .datac(\z80_|execute_|ctl_inc_cy~80_combout ), + .datad(\z80_|execute_|ctl_inc_cy~56_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~85_combout = (((!\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|ctl_inc_cy~49_combout )) # (!\z80_|execute_|ctl_inc_cy~51_combout )) # (!\z80_|execute_|ctl_inc_cy~44_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), + .datab(\z80_|execute_|ctl_inc_cy~51_combout ), + .datac(\z80_|execute_|ctl_inc_cy~49_combout ), + .datad(\z80_|execute_|ctl_inc_cy~45_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~89 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~89_combout = (\z80_|execute_|ctl_inc_cy~85_combout ) # ((!\z80_|execute_|ctl_inc_cy~48_combout ) # (!\z80_|execute_|ctl_inc_cy~88_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~85_combout ), + .datab(\z80_|execute_|ctl_inc_cy~88_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_cy~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~89_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~89 .lut_mask = 16'hBBFF; +defparam \z80_|execute_|ctl_inc_cy~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~90 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~90_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~90_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~90 .lut_mask = 16'h0515; +defparam \z80_|execute_|ctl_inc_cy~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~91 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~91_combout = (\z80_|execute_|ctl_inc_cy~89_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_inc_cy~90_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~89_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_inc_cy~90_combout ), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~91_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~91 .lut_mask = 16'hEAEE; +defparam \z80_|execute_|ctl_inc_cy~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~84_combout = ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_inc_cy~83_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_inc_cy~96_combout ) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_inc_cy~83_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_inc_cy~96_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~100 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~100_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~100_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~100 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~100 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~92 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~92_combout = (\z80_|execute_|ctl_inc_cy~84_combout ) # ((\z80_|execute_|ctl_inc_cy~91_combout & ((\z80_|execute_|ctl_inc_cy~100_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~91_combout ), + .datab(\z80_|execute_|ctl_inc_cy~84_combout ), + .datac(\z80_|execute_|ctl_inc_cy~100_combout ), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~92_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~92 .lut_mask = 16'hECEE; +defparam \z80_|execute_|ctl_inc_cy~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~28_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~9_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'hC080; +defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~82_combout = (\z80_|execute_|pc_inc_hold~24_combout & (!\z80_|execute_|pc_inc_hold~28_combout & (\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout & \z80_|execute_|ctl_inc_cy~52_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~24_combout ), + .datab(\z80_|execute_|pc_inc_hold~28_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .datad(\z80_|execute_|ctl_inc_cy~52_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((!\z80_|execute_|pc_inc_hold~33_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datad(\z80_|execute_|pc_inc_hold~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'h8AAA; +defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|pc_inc_hold~22_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|pc_inc_hold~22_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|pc_inc_hold~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hF888; +defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|pc_inc_hold~29_combout ) # ((\z80_|execute_|pc_inc_hold~30_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~33_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|pc_inc_hold~33_combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|pc_inc_hold~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hFFF2; +defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|pc_inc_hold~31_combout ) # (((\z80_|execute_|pc_inc_hold~28_combout ) # (!\z80_|execute_|pc_inc_hold~24_combout )) # (!\z80_|execute_|ctl_inc_cy~52_combout )) + + .dataa(\z80_|execute_|pc_inc_hold~31_combout ), + .datab(\z80_|execute_|ctl_inc_cy~52_combout ), + .datac(\z80_|execute_|pc_inc_hold~28_combout ), + .datad(\z80_|execute_|pc_inc_hold~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~93 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~93_combout = (\z80_|execute_|ctl_inc_cy~82_combout ) # ((\z80_|execute_|ctl_inc_cy~92_combout & ((!\z80_|execute_|pc_inc_hold~25_combout ) # (!\z80_|execute_|pc_inc_hold~32_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~92_combout ), + .datab(\z80_|execute_|ctl_inc_cy~82_combout ), + .datac(\z80_|execute_|pc_inc_hold~32_combout ), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~93_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~93 .lut_mask = 16'hCEEE; +defparam \z80_|execute_|ctl_inc_cy~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N14 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~81_combout ), + .datac(\z80_|execute_|ctl_inc_cy~93_combout ), + .datad(\z80_|address_latch_|Q [0]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h03FC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N19 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y17_N17 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal47~0_combout & !\z80_|execute_|ctl_mRead~10_combout ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~10 ( +// Equation(s): +// \z80_|alu_control_|db[0]~10_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[0]~17_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|bus_control_|db[0]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~10 .lut_mask = 16'h4C0C; +defparam \z80_|alu_control_|db[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N31 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|alu_|db[0]~18_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[0]~18_combout & (!\z80_|execute_|ctl_reg_in_hi~11_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~27_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & (\z80_|reg_file_|gdfx_temp1[0]~24_combout & \z80_|reg_file_|gdfx_temp1[0]~26_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout & \z80_|reg_file_|gdfx_temp1[0]~28_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_inc_dec~4_combout )) # (!\z80_|execute_|fIOWrite~0_combout ))) + + .dataa(\z80_|execute_|fIOWrite~0_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~9_combout = (\z80_|execute_|ctl_inc_dec~8_combout ) # (((\z80_|ir_|opcode [3] & !\z80_|execute_|ctl_reg_gp_we~2_combout )) # (!\z80_|execute_|ctl_inc_dec~3_combout )) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .datac(\z80_|execute_|ctl_inc_dec~8_combout ), + .datad(\z80_|execute_|ctl_inc_dec~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hF2FF; +defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_dec~9_combout ), + .datad(\z80_|execute_|ctl_inc_dec~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hF0FF; +defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) + + .dataa(\z80_|address_latch_|Q [4]), + .datab(\z80_|execute_|ctl_inc_dec~5_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h5595; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h5F5F; +defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~11_combout = (((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|execute_|ctl_inc_dec~5_combout ), + .datac(\z80_|execute_|ctl_inc_dec~9_combout ), + .datad(\z80_|execute_|ctl_inc_dec~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ) + + .dataa(\z80_|address_latch_|Q [2]), + .datab(gnd), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h5A5A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N5 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y17_N3 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N5 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|execute_|ctl_reg_sel_wz~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N11 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h2220; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|DFFE_instCB~q & \z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_ir_we~5_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~6_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hECCC; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~9 ( +// Equation(s): +// \z80_|alu_|db_low[2]~9_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[3]~14_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[1]~16_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[3]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~9 .lut_mask = 16'hFC0C; +defparam \z80_|alu_|db_low[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~10 ( +// Equation(s): +// \z80_|alu_|db_low[2]~10_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~9_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~12_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(\z80_|alu_|db[2]~12_combout ), + .datad(\z80_|alu_|db_low[2]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~10 .lut_mask = 16'hFD75; +defparam \z80_|alu_|db_low[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~1 ( +// Equation(s): +// \z80_|alu_|db_high[3]~1_combout = (\z80_|alu_|db_high[3]~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|db_high[3]~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~1 .lut_mask = 16'hFFF0; +defparam \z80_|alu_|db_high[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~4_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'hFFF5; +defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~10 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & (\z80_|execute_|ctl_flags_pf_we~4_combout & \z80_|execute_|ctl_flags_hf_we~5_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datac(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .lut_mask = 16'h8080; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~17 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~17_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_iorw~10_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~17 .lut_mask = 16'h0054; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~18 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~18_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|ir_|opcode [4] & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~18 .lut_mask = 16'h2030; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~38_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~38 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_alu_op_low~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~11 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout = (!\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout & (\z80_|execute_|ctl_alu_op_low~38_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .lut_mask = 16'h1050; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~12 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & ((!\z80_|pla_decode_|Equal62~2_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .lut_mask = 16'h4C00; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~15_combout & ((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # +// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_alu_core_R~2_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_S~8_combout & \z80_|execute_|ctl_alu_core_R~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|execute_|ctl_ir_we~11_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~10_combout )))) # +// (!\z80_|execute_|ctl_ir_we~7_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_ir_we~10_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~10_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h222A; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~11_combout & \z80_|execute_|ctl_alu_core_R~3_combout +// ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFCD; +defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~9_combout = ((!\z80_|execute_|ctl_alu_core_S~11_combout ) # (!\z80_|execute_|ctl_alu_core_S~5_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_core_S~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'h77FF; +defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~combout = ((\z80_|execute_|ctl_alu_core_S~9_combout ) # ((\z80_|pla_decode_|Equal62~2_combout & \z80_|pla_decode_|Equal9~0_combout ))) # (!\z80_|execute_|ctl_alu_core_S~8_combout ) + + .dataa(\z80_|pla_decode_|Equal62~2_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_alu_core_S .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal73~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hE000; +defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~combout = ((\z80_|pla_decode_|Equal73~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~5_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout ))) # (!\z80_|execute_|ctl_alu_core_R~3_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~3_combout ), + .datab(\z80_|pla_decode_|Equal73~2_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~41_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hF3F3; +defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~29_combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # (!\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_alu_op_low~16_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~34_combout & (((\z80_|pla_decode_|Equal39~0_combout & +// \z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFA88; +defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~31_combout = ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~29_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) # (!\z80_|execute_|ctl_alu_op_low~25_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((\z80_|pla_decode_|Equal40~1_combout & +// \z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'hF8C8; +defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~40_combout = (\z80_|execute_|ctl_alu_op_low~32_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~40 .lut_mask = 16'hCCEC; +defparam \z80_|execute_|ctl_alu_op_low~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~33_combout = (\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'hE000; +defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~combout = (\z80_|execute_|ctl_alu_op_low~31_combout ) # ((\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~33_combout ) # (!\z80_|execute_|ctl_alu_op_low~23_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~33_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~59 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~58 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N11 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~61_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~61 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[7]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y12_N19 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~62_combout = (\z80_|alu_|db[7]~20_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ))) # (!\z80_|alu_|db[7]~20_combout & (!\z80_|execute_|ctl_reg_in_hi~11_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .datad(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~62 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[7]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N21 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~63 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[7]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~60 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~64_combout = (\z80_|reg_file_|gdfx_temp1[7]~61_combout & (\z80_|reg_file_|gdfx_temp1[7]~62_combout & (\z80_|reg_file_|gdfx_temp1[7]~63_combout & \z80_|reg_file_|gdfx_temp1[7]~60_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~61_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~62_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~63_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~60_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~64 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~65_combout = (\z80_|reg_file_|gdfx_temp1[7]~59_combout & (\z80_|reg_file_|gdfx_temp1[7]~58_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout & \z80_|reg_file_|gdfx_temp1[7]~64_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~59_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~58_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~64_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~65 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[7]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_control_|reg_sys_we_lo~combout ) # (!\z80_|execute_|ctl_reg_sel_ir~1_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'hF700; +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~16 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~16_combout = (\z80_|reg_file_|gdfx_temp1[7]~66_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~66_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~16 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[7]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N17 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[7]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~17 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~17_combout = (\z80_|reg_file_|db_hi_as[7]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[7]~16_combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~17 .lut_mask = 16'h88AA; +defparam \z80_|reg_file_|db_hi_as[7]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N25 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N1 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [1] & ((\z80_|alu_|db[1]~16_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[1]~16_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .datad(\z80_|alu_|db[1]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~10_combout & (\z80_|reg_file_|gdfx_temp1[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~11_combout & \z80_|reg_file_|gdfx_temp1[1]~12_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~8_combout & (\z80_|reg_file_|gdfx_temp1[1]~9_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout & \z80_|reg_file_|gdfx_temp1[1]~14_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hBB00; +defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N6 +cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( +// Equation(s): +// \z80_|address_latch_|abusz [8] = (\z80_|reg_file_|db_hi_as[0]~6_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [8]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h0A0A; +defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )) # (!\z80_|execute_|ctl_al_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~14_combout ), + .datab(\z80_|execute_|ctl_al_we~5_combout ), + .datac(\z80_|execute_|ctl_apin_mux~1_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hF070; +defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~9_combout = (\z80_|execute_|ctl_al_we~13_combout & (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & +// (((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h7770; +defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~9_combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) + + .dataa(\z80_|execute_|ctl_al_we~9_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEAFF; +defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~7_combout = ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_alu_oe~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~5_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .datad(\z80_|execute_|ctl_mWrite~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~8_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_al_we~7_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )) # (!\z80_|execute_|setM1~46_combout ))) + + .dataa(\z80_|execute_|setM1~46_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_al_we~4_combout ), + .datad(\z80_|execute_|ctl_al_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~10_combout ) # ((\z80_|execute_|ctl_al_we~8_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~6_combout ), + .datab(\z80_|execute_|ctl_al_we~10_combout ), + .datac(\z80_|execute_|ctl_al_we~8_combout ), + .datad(\z80_|execute_|ctl_sw_4d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~12_combout = (\z80_|execute_|ctl_al_we~11_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|setM1~53_combout )) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_al_we~11_combout ), + .datad(\z80_|execute_|setM1~53_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hF8FF; +defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N7 +dffeas \z80_|address_latch_|Q[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [8]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y15_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~82_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~82 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[7]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N25 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~81 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[7]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~12 ( +// Equation(s): +// \z80_|alu_control_|db[6]~12_combout = ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|execute_|ctl_flags_oe~2_combout )) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) + + .dataa(gnd), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~12 .lut_mask = 16'hFFF3; +defparam \z80_|alu_control_|db[6]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|alu_|db_high[3]~7_combout & ((\z80_|execute_|ctl_flags_alu~19_combout ) # ((\z80_|alu_control_|db[7]~37_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_high[3]~7_combout & +// (((\z80_|alu_control_|db[7]~37_combout & \z80_|execute_|ctl_flags_bus~combout )))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_flags_alu~19_combout ), + .datac(\z80_|alu_control_|db[7]~37_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~3_combout ) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N11 +dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( +// Equation(s): +// \z80_|alu_control_|db[7]~18_combout = (\z80_|alu_|db[7]~20_combout & (((!\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_|db[7]~20_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((!\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h4F44; +defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~19 ( +// Equation(s): +// \z80_|alu_control_|db[7]~19_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[7]~18_combout & ((\z80_|reg_file_|gdfx_temp0[7]~90_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .datad(\z80_|alu_control_|db[7]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~19 .lut_mask = 16'h00C4; +defparam \z80_|alu_control_|db[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~20 ( +// Equation(s): +// \z80_|alu_control_|db[7]~20_combout = (\z80_|alu_control_|db[7]~19_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datab(\z80_|bus_control_|db[7]~7_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|alu_control_|db[7]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~20 .lut_mask = 16'h4F00; +defparam \z80_|alu_control_|db[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~37 ( +// Equation(s): +// \z80_|alu_control_|db[7]~37_combout = (\z80_|alu_control_|db[7]~20_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|alu_control_|db[6]~12_combout & !\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datab(\z80_|alu_control_|db[6]~12_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|alu_control_|db[7]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~37 .lut_mask = 16'hFF01; +defparam \z80_|alu_control_|db[7]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~37_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|alu_control_|db[7]~37_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~90_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|gdfx_temp0[7]~84_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .datad(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y17_N29 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|gdfx_temp0[7]~87_combout & (\z80_|reg_file_|gdfx_temp0[7]~86_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & \z80_|reg_file_|gdfx_temp0[7]~83_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|gdfx_temp0[7]~82_combout & (\z80_|reg_file_|gdfx_temp0[7]~81_combout & \z80_|reg_file_|gdfx_temp0[7]~88_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~82_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~81_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~90_combout = ((\z80_|reg_file_|gdfx_temp0[7]~89_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .datab(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8AFF; +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[7]~90_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .datab(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) + + .dataa(gnd), + .datab(\z80_|address_latch_|Q [7]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h33CC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'h8AFF; +defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( +// Equation(s): +// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [7]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N3 +dffeas \z80_|address_latch_|Q[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [7]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [8] & !\z80_|address_latch_|Q +// [7])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [8] & \z80_|address_latch_|Q [7])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [8]), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h2008; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N18 +cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( +// Equation(s): +// \z80_|address_latch_|abusz [9] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[1]~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [9]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N19 +dffeas \z80_|address_latch_|Q[9] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [9]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y16_N21 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [2] & ((\z80_|alu_|db[2]~12_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[2]~12_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~44 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[2]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N17 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~45_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~45 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[2]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~42 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~43_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~43 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[2]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~46_combout = (\z80_|reg_file_|gdfx_temp1[2]~44_combout & (\z80_|reg_file_|gdfx_temp1[2]~45_combout & (\z80_|reg_file_|gdfx_temp1[2]~42_combout & \z80_|reg_file_|gdfx_temp1[2]~43_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~46 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~48_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~40 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~41 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~47_combout = (\z80_|reg_file_|gdfx_temp1[2]~46_combout & (\z80_|reg_file_|gdfx_temp1[2]~40_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout & \z80_|reg_file_|gdfx_temp1[2]~41_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~47 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~48_combout = ((\z80_|reg_file_|gdfx_temp1[2]~47_combout & ((\z80_|reg_file_|db_hi_as[2]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~48 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp1[2]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~10 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [2] & ((\z80_|reg_file_|gdfx_temp1[2]~48_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[2]~48_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~10 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|db_hi_as[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~11 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~11_combout = (\z80_|reg_file_|db_hi_as[2]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[2]~10_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~11 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|db_hi_as[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N22 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ +// (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [10]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~12 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~12_combout = ((\z80_|reg_file_|db_hi_as[2]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|reg_file_|db_hi_as[2]~11_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~12 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|db_hi_as[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N0 +cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( +// Equation(s): +// \z80_|address_latch_|abusz [10] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[2]~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [10]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N1 +dffeas \z80_|address_latch_|Q[10] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [10]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [9] & (!\z80_|execute_|ctl_inc_dec~11_combout & +// \z80_|address_latch_|Q [10])) # (!\z80_|address_latch_|Q [9] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [10])))) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [10]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h2400; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~50 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~49 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~51_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~51 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~52_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~52 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[4]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N8 +cycloneive_lcell_comb \z80_|alu_|db[4]~8 ( +// Equation(s): +// \z80_|alu_|db[4]~8_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~57_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[4]~33_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[4]~33_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~8 .lut_mask = 16'hF351; +defparam \z80_|alu_|db[4]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N2 +cycloneive_lcell_comb \z80_|alu_|db[4]~10 ( +// Equation(s): +// \z80_|alu_|db[4]~10_combout = ((\z80_|alu_|db[4]~8_combout & ((\z80_|alu_|db_high[0]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[4]~8_combout ), + .datad(\z80_|alu_|db_high[0]~25_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~10 .lut_mask = 16'hF575; +defparam \z80_|alu_|db[4]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~53_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [4] & ((\z80_|alu_|db[4]~10_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[4]~10_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .datad(\z80_|alu_|db[4]~10_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~53 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N25 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~54_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~54 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[4]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~55_combout = (\z80_|reg_file_|gdfx_temp1[4]~51_combout & (\z80_|reg_file_|gdfx_temp1[4]~52_combout & (\z80_|reg_file_|gdfx_temp1[4]~53_combout & \z80_|reg_file_|gdfx_temp1[4]~54_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~51_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~52_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~53_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~54_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~55 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~56_combout = (\z80_|reg_file_|gdfx_temp1[4]~50_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout & (\z80_|reg_file_|gdfx_temp1[4]~49_combout & \z80_|reg_file_|gdfx_temp1[4]~55_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~50_combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~49_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~55_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~56 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~57_combout = ((\z80_|reg_file_|gdfx_temp1[4]~56_combout & ((\z80_|reg_file_|db_hi_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~56_combout ), + .datac(\z80_|reg_file_|db_hi_as[4]~15_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~57 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|gdfx_temp1[4]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[4]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~13 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~13_combout = (\z80_|reg_file_|gdfx_temp1[4]~57_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[4]~57_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~13 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[4]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[4]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~14 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~14_combout = (\z80_|reg_file_|db_hi_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[4]~13_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~14 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|db_hi_as[4]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N14 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ +// (\z80_|address_latch_|Q [11]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [12]), + .datad(\z80_|address_latch_|Q [11]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hD278; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~15 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~15_combout = ((\z80_|reg_file_|db_hi_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datab(\z80_|reg_file_|db_hi_as[4]~14_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~15 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|db_hi_as[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N12 +cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( +// Equation(s): +// \z80_|address_latch_|abusz [12] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[4]~15_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(\z80_|reg_file_|db_hi_as[4]~15_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [12]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h3030; +defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N13 +dffeas \z80_|address_latch_|Q[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [12]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [12] & +// !\z80_|address_latch_|Q [11])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [12] & \z80_|address_latch_|Q [11])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [12]), + .datad(\z80_|address_latch_|Q [11]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2008; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h55AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[5]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~76 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[5]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~77 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[5]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~84_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~79_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~79 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[5]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op_low~23_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_alu_oe~3_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (((\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_66_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h0088; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFCC; +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N25 +dffeas \z80_|alu_|op1_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h00A0; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_zero~combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~18 ( +// Equation(s): +// \z80_|alu_|db_low[1]~18_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~12_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~18 .lut_mask = 16'hFA0A; +defparam \z80_|alu_|db_low[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~19 ( +// Equation(s): +// \z80_|alu_|db_low[1]~19_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[1]~18_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[1]~16_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[1]~16_combout ), + .datac(\z80_|alu_|db_low[1]~18_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~19 .lut_mask = 16'hF0CC; +defparam \z80_|alu_|db_low[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( +// Equation(s): +// \z80_|alu_|db_low[1]~16_combout = (\z80_|alu_|op1_low [1] & (((\z80_|alu_|op2_low [1])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_low [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [1]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_low [1]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op2_low [1]), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hAF23; +defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( +// Equation(s): +// \z80_|alu_|db_low[1]~15_combout = ((\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'h0F2F; +defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N27 +dffeas \z80_|alu_|result_lo[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N26 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( +// Equation(s): +// \z80_|alu_|db_low[1]~17_combout = (\z80_|alu_|db_low[1]~16_combout & (\z80_|alu_|db_low[1]~15_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) + + .dataa(\z80_|alu_|db_low[1]~16_combout ), + .datab(\z80_|alu_|db_low[1]~15_combout ), + .datac(\z80_|alu_|result_lo [1]), + .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'h8880; +defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~20 ( +// Equation(s): +// \z80_|alu_|db_low[1]~20_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[1]~19_combout & ((\z80_|alu_|db_low[1]~17_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~17_combout ) # +// (!\z80_|alu_|db_high[3]~0_combout )))) + + .dataa(\z80_|alu_|db_low[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[3]~0_combout ), + .datad(\z80_|alu_|db_low[1]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~20 .lut_mask = 16'hBB03; +defparam \z80_|alu_|db_low[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & \z80_|alu_|db_low[1]~20_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|alu_|db_low[1]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'hF000; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hAE00; +defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[1]~19_combout )))) + + .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|alu_|db_high[1]~19_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .lut_mask = 16'h00EA; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFFFC; +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N21 +dffeas \z80_|alu_|op1_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'hCE00; +defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [1]), + .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'hE200; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[1]~20_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .datad(\z80_|alu_|db_low[1]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h3230; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # (\z80_|execute_|ctl_alu_op2_sel_zero~combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFEFE; +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N9 +dffeas \z80_|alu_|op2_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~14_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y6_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout )) # (!\z80_|execute_|ctl_alu_op_low~41_combout +// )) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~10_combout & (\z80_|execute_|ctl_flags_alu~21_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & \z80_|execute_|ctl_alu_core_S~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datab(\z80_|execute_|ctl_flags_alu~21_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ) # ((!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ) # (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~2_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout +// )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFBF3; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout = (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[1]~20_combout )))) # +// (!\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[1]~20_combout )))) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datad(\z80_|alu_|db_low[1]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N11 +dffeas \z80_|alu_|op2_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~25_combout ) # (\z80_|execute_|ctl_mRead~24_combout )))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) + + .dataa(\z80_|execute_|ctl_mRead~25_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'hCF8F; +defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N16 +cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~2 ( +// Equation(s): +// \z80_|alu_|alu_op2[1]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [1]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [1])))) + + .dataa(\z80_|alu_|op2_low [1]), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|alu_|op2_high [1]), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[1]~2 .lut_mask = 16'h3C66; +defparam \z80_|alu_|alu_op2[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[1]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|alu_|alu_op2[1]~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hC808; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[1]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high +// [1])))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|alu_|alu_op2[1]~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0131; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hF1F1; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & (!\z80_|execute_|ctl_alu_core_S~combout & +// !\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h3337; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ) # +// ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'h3F0A; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & (\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_bus~16_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h3000; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N29 +dffeas \z80_|alu_|op1_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout = (\z80_|alu_|db_high[2]~13_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[2]~14_combout )))) # +// (!\z80_|alu_|db_high[2]~13_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[2]~14_combout )))) + + .dataa(\z80_|alu_|db_high[2]~13_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datad(\z80_|alu_|db_low[2]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h0A0A; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N3 +dffeas \z80_|alu_|op2_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( +// Equation(s): +// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op2_high [2]), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hAF23; +defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~8 ( +// Equation(s): +// \z80_|alu_|db_high[2]~8_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db[7]~20_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~8 .lut_mask = 16'hCFC0; +defparam \z80_|alu_|db_high[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( +// Equation(s): +// \z80_|alu_|db_high[2]~9_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[2]~8_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[6]~22_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(\z80_|alu_|db[6]~22_combout ), + .datad(\z80_|alu_|db_high[2]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'hFD75; +defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( +// Equation(s): +// \z80_|alu_|db_high[2]~11_combout = (!\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[4]~19_combout )) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'h4400; +defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( +// Equation(s): +// \z80_|alu_|db_high[2]~12_combout = (\z80_|alu_|db_high[2]~10_combout & (\z80_|alu_|db_high[2]~9_combout & ((\z80_|alu_|db_high[2]~11_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|alu_|db_high[2]~10_combout ), + .datac(\z80_|alu_|db_high[2]~9_combout ), + .datad(\z80_|alu_|db_high[2]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hC040; +defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( +// Equation(s): +// \z80_|alu_|db_high[2]~13_combout = ((\z80_|alu_|db_high[2]~12_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_high[2]~12_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hBBB3; +defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~68 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~75_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~67 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N25 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N19 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~72 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~70 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~69 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~71_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [6] & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .datad(\z80_|alu_|db[6]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~71 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~73_combout = (\z80_|reg_file_|gdfx_temp1[6]~72_combout & (\z80_|reg_file_|gdfx_temp1[6]~70_combout & (\z80_|reg_file_|gdfx_temp1[6]~69_combout & \z80_|reg_file_|gdfx_temp1[6]~71_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~73 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~74_combout = (\z80_|reg_file_|gdfx_temp1[6]~68_combout & (\z80_|reg_file_|gdfx_temp1[6]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout & \z80_|reg_file_|gdfx_temp1[6]~73_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~74 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N26 +cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( +// Equation(s): +// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~21_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h3300; +defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N27 +dffeas \z80_|address_latch_|Q[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [14]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datac(\z80_|address_latch_|Q [14]), + .datad(\z80_|execute_|ctl_inc_dec~11_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'hB478; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~19 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp1[6]~75_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[6]~75_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~19 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~20_combout = (\z80_|reg_file_|db_hi_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~19_combout ), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~20 .lut_mask = 16'hF030; +defparam \z80_|reg_file_|db_hi_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~21_combout = ((\z80_|reg_file_|db_hi_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[6]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~21 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_hi_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~75_combout = ((\z80_|reg_file_|gdfx_temp1[6]~74_combout & ((\z80_|reg_file_|db_hi_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~75 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|gdfx_temp1[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N16 +cycloneive_lcell_comb \z80_|alu_|db[6]~21 ( +// Equation(s): +// \z80_|alu_|db[6]~21_combout = (\z80_|alu_control_|db[6]~23_combout & (((\z80_|reg_file_|gdfx_temp1[6]~75_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[6]~23_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[6]~75_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) + + .dataa(\z80_|alu_control_|db[6]~23_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~21 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N26 +cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( +// Equation(s): +// \z80_|alu_|db[6]~22_combout = ((\z80_|alu_|db[6]~21_combout & ((\z80_|alu_|db_high[2]~13_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|alu_|db[6]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF755; +defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( +// Equation(s): +// \z80_|alu_|db_high[1]~16_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_|db[6]~22_combout ), + .datad(\z80_|alu_|db[4]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hF3C0; +defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( +// Equation(s): +// \z80_|alu_|db_high[1]~17_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[1]~16_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[5]~24_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datad(\z80_|alu_|db_high[1]~16_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hFC0C; +defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~14 ( +// Equation(s): +// \z80_|alu_|db_high[1]~14_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[4]~19_combout ), + .datab(\z80_|bus_control_|db[3]~21_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~14 .lut_mask = 16'h4F0F; +defparam \z80_|alu_|db_high[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( +// Equation(s): +// \z80_|alu_|db_high[1]~15_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [1]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_high [1]), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( +// Equation(s): +// \z80_|alu_|db_high[1]~18_combout = (\z80_|alu_|db_high[1]~14_combout & (\z80_|alu_|db_high[1]~15_combout & ((\z80_|alu_|db_high[1]~17_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[1]~17_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[1]~14_combout ), + .datad(\z80_|alu_|db_high[1]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hB000; +defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( +// Equation(s): +// \z80_|alu_|db_high[1]~19_combout = ((\z80_|alu_|db_high[1]~18_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datac(\z80_|alu_|db_high[1]~18_combout ), + .datad(\z80_|alu_|db_high[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'hE0FF; +defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N4 +cycloneive_lcell_comb \z80_|alu_|db[5]~23 ( +// Equation(s): +// \z80_|alu_|db[5]~23_combout = (\z80_|reg_file_|gdfx_temp1[5]~84_combout & (((\z80_|alu_control_|db[5]~17_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) # (!\z80_|reg_file_|gdfx_temp1[5]~84_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[5]~17_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[5]~17_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~23 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db[5]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N10 +cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( +// Equation(s): +// \z80_|alu_|db[5]~24_combout = ((\z80_|alu_|db[5]~23_combout & ((\z80_|alu_|db_high[1]~19_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[5]~23_combout ), + .datad(\z80_|alu_|db[7]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hB0FF; +defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~80_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [5] & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[5]~24_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~80 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[5]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~81_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~81 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[5]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~78 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[5]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~82_combout = (\z80_|reg_file_|gdfx_temp1[5]~79_combout & (\z80_|reg_file_|gdfx_temp1[5]~80_combout & (\z80_|reg_file_|gdfx_temp1[5]~81_combout & \z80_|reg_file_|gdfx_temp1[5]~78_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~79_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~80_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~81_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~78_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~82 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~83_combout = (\z80_|reg_file_|gdfx_temp1[5]~76_combout & (\z80_|reg_file_|gdfx_temp1[5]~77_combout & (\z80_|reg_file_|gdfx_temp1[5]~82_combout & \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~76_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~77_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~82_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~83 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~84_combout = ((\z80_|reg_file_|gdfx_temp1[5]~83_combout & ((\z80_|reg_file_|db_hi_as[5]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[5]~24_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~83_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~84 .lut_mask = 16'h8CFF; +defparam \z80_|reg_file_|gdfx_temp1[5]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[5]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~22 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~22_combout = (\z80_|reg_file_|gdfx_temp1[5]~84_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[5]~84_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~22 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[5]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~23 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~23_combout = (\z80_|reg_file_|db_hi_as[5]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .datab(\z80_|reg_file_|db_hi_as[5]~22_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~23 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_hi_as[5]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~24 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~24_combout = ((\z80_|reg_file_|db_hi_as[5]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[5]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~24 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_hi_as[5]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N20 +cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( +// Equation(s): +// \z80_|address_latch_|abusz [13] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[5]~24_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(\z80_|reg_file_|db_hi_as[5]~24_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [13]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h3030; +defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N21 +dffeas \z80_|address_latch_|Q[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [13]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q [13]) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [13]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h3C3C; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N6 +cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( +// Equation(s): +// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~18_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[7]~18_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h00AA; +defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N7 +dffeas \z80_|address_latch_|Q[15] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [15]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|address_latch_|Q [14]), + .datac(\z80_|execute_|ctl_inc_dec~7_combout ), + .datad(\z80_|execute_|ctl_inc_dec~6_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h3633; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N8 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~18 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~18_combout = ((\z80_|reg_file_|db_hi_as[7]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|reg_file_|db_hi_as[7]~17_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~18 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|db_hi_as[7]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~66_combout = ((\z80_|reg_file_|gdfx_temp1[7]~65_combout & ((\z80_|reg_file_|db_hi_as[7]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~65_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_hi_as[7]~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~66 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp1[7]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N4 +cycloneive_lcell_comb \z80_|alu_|db[7]~19 ( +// Equation(s): +// \z80_|alu_|db[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~66_combout & (((\z80_|alu_control_|db[7]~37_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~66_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[7]~37_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~19 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N18 +cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( +// Equation(s): +// \z80_|alu_|db[7]~20_combout = ((\z80_|alu_|db[7]~19_combout & ((\z80_|alu_|db_high[3]~7_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[7]~19_combout ), + .datad(\z80_|alu_|db_high[3]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hF575; +defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N8 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (((\z80_|alu_|db[7]~20_combout & \z80_|ir_|opcode [3])))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) # (!\z80_|ir_|opcode [3] & +// ((\z80_|alu_|db[7]~20_combout ))))) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|alu_|db[7]~20_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hE230; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((\z80_|alu_|db_low[3]~8_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_low[3]~8_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|alu_|db_high[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'hC0D0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 .lut_mask = 16'h00F8; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N5 +dffeas \z80_|alu_|op1_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|alu_|db_high[3]~7_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h0088; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N11 +dffeas \z80_|alu_|op1_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N18 +cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~0 ( +// Equation(s): +// \z80_|alu_|alu_op1[3]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [3]))) + + .dataa(\z80_|alu_|op1_low [3]), + .datab(\z80_|alu_|op1_high [3]), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[3]~0 .lut_mask = 16'hAACC; +defparam \z80_|alu_|alu_op1[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (\z80_|alu_|db_low[2]~14_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # +// (!\z80_|alu_|db_low[2]~14_combout & (\z80_|alu_|db_high[2]~13_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|alu_|db_low[2]~14_combout ), + .datab(\z80_|alu_|db_high[2]~13_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N7 +dffeas \z80_|alu_|op1_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [2]))))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|alu_|op1_high [2]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .lut_mask = 16'h88A0; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[2]~14_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|alu_|db_low[2]~14_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .lut_mask = 16'h0F08; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N31 +dffeas \z80_|alu_|op2_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N0 +cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~1 ( +// Equation(s): +// \z80_|alu_|alu_op2[2]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) + + .dataa(\z80_|alu_|op2_high [2]), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datad(\z80_|alu_|op2_low [2]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[2]~1 .lut_mask = 16'h636C; +defparam \z80_|alu_|alu_op2[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [2]))))) + + .dataa(\z80_|alu_|op1_low [2]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_high [2]), + .datad(\z80_|alu_|alu_op2[2]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0047; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[2]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) + + .dataa(\z80_|alu_|alu_op2[2]~1_combout ), + .datab(\z80_|alu_|op1_high [2]), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hA088; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_S~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFF0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hAAFB; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op1[3]~0_combout & ((\z80_|alu_|alu_op2[3]~0_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ))) # +// (!\z80_|alu_|alu_op1[3]~0_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & \z80_|alu_|alu_op2[3]~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(\z80_|alu_|alu_op1[3]~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_|alu_op2[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hEFAE; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout & (\z80_|execute_|ctl_flags_alu~19_combout & !\z80_|execute_|ctl_alu_core_R~combout )) + + .dataa(gnd), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|execute_|ctl_flags_alu~19_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'h00C0; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[0]~14_combout )) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datac(gnd), + .datad(\z80_|alu_control_|db[0]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hEECC; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~4_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) + + .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_bus~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hBAFA; +defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~6_combout = (\z80_|execute_|ctl_flags_cf_we~3_combout ) # (((\z80_|execute_|ctl_flags_cf_we~5_combout ) # (!\z80_|execute_|ctl_flags_hf_we~2_combout )) # (!\z80_|execute_|ctl_flags_cf_we~2_combout )) + + .dataa(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datac(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~4_combout = ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal0~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal0~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~6 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_cf2_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~5_combout = (\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~6_combout ) # ((\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_we~6_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~5 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_flags_cf2_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~5_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~5_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'hF0B8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N21 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N2 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h20A8; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N30 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((!\z80_|ir_|opcode [4] & \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout )) + + .dataa(\z80_|ir_|opcode [4]), + .datab(gnd), + .datac(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hFF50; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( +// Equation(s): +// \z80_|alu_|db_low[0]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_|db[1]~16_combout ), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hF3C0; +defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( +// Equation(s): +// \z80_|alu_|db_low[0]~22_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[0]~21_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[0]~18_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datab(\z80_|alu_|db[0]~18_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[0]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hEF4F; +defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|db_high[0]~25_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & \z80_|alu_|db_low[0]~27_combout )))) # +// (!\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & (\z80_|alu_|db_low[0]~27_combout ))) + + .dataa(\z80_|alu_|db_high[0]~25_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(\z80_|alu_|db_low[0]~27_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N31 +dffeas \z80_|alu_|op1_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~24 ( +// Equation(s): +// \z80_|alu_|db_low[0]~24_combout = (\z80_|alu_|op2_low [0] & (((\z80_|alu_|op1_low [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_low [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [0]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op1_low [0]), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~24 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_low[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N23 +dffeas \z80_|alu_|result_lo[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( +// Equation(s): +// \z80_|alu_|db_low[0]~23_combout = ((!\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'h0F1F; +defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~25 ( +// Equation(s): +// \z80_|alu_|db_low[0]~25_combout = (\z80_|alu_|db_low[0]~24_combout & (\z80_|alu_|db_low[0]~23_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [0])))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(\z80_|alu_|db_low[0]~24_combout ), + .datac(\z80_|alu_|result_lo [0]), + .datad(\z80_|alu_|db_low[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~25 .lut_mask = 16'hC800; +defparam \z80_|alu_|db_low[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~27 ( +// Equation(s): +// \z80_|alu_|db_low[0]~27_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[0]~22_combout & (\z80_|alu_|db_low[0]~25_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[0]~22_combout & +// \z80_|alu_|db_low[0]~25_combout )) # (!\z80_|alu_|db_high[3]~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_low[0]~22_combout ), + .datac(\z80_|alu_|db_low[0]~25_combout ), + .datad(\z80_|alu_|db_high[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~27 .lut_mask = 16'hC0D5; +defparam \z80_|alu_|db_low[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])))) + + .dataa(\z80_|alu_|op1_high [0]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [0]), + .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hE200; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[0]~27_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|alu_|db_low[0]~27_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h0F08; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N15 +dffeas \z80_|alu_|op2_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_high[0]~25_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[0]~27_combout )))) # +// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[0]~27_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|db_high[0]~25_combout ), + .datad(\z80_|alu_|db_low[0]~27_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N17 +dffeas \z80_|alu_|op2_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N10 +cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( +// Equation(s): +// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|alu_|op2_high [0]), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h1DE2; +defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_R~3_combout )) # +// (!\z80_|execute_|ctl_alu_core_S~8_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h1FFF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~34_combout = (((\z80_|execute_|ctl_alu_op_low~29_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_alu_op_low~41_combout )) # (!\z80_|execute_|ctl_alu_op_low~25_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~36_combout = (\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~36 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|ctl_alu_op_low~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~35_combout = (\z80_|execute_|ctl_alu_op_low~33_combout ) # ((\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~33_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~35 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op_low~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~13_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~13 .lut_mask = 16'hD0C0; +defparam \z80_|execute_|ctl_alu_core_hf~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~14_combout = (\z80_|ir_|opcode [5]) # (((!\z80_|pla_decode_|Equal9~0_combout & !\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout )) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~14 .lut_mask = 16'hCFDF; +defparam \z80_|execute_|ctl_alu_core_hf~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~15_combout = (\z80_|execute_|ctl_alu_core_hf~14_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~15 .lut_mask = 16'h8CCC; +defparam \z80_|execute_|ctl_alu_core_hf~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~16_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~15_combout )) # (!\z80_|execute_|ctl_alu_core_hf~12_combout ) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~16 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|ctl_alu_core_hf~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~17_combout = (\z80_|execute_|ctl_alu_op_low~36_combout & (!\z80_|execute_|ctl_alu_op_low~35_combout & ((\z80_|execute_|ctl_alu_core_hf~16_combout )))) # (!\z80_|execute_|ctl_alu_op_low~36_combout & +// ((\z80_|execute_|ctl_alu_core_hf~13_combout ) # ((!\z80_|execute_|ctl_alu_op_low~35_combout & \z80_|execute_|ctl_alu_core_hf~16_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~36_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~13_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~17 .lut_mask = 16'h7350; +defparam \z80_|execute_|ctl_alu_core_hf~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|execute_|ixy_d~6_combout ) # ((!\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ixy_d~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hF3F0; +defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout & !\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'h88C8; +defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ctl_alu_op_low~18_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~23_combout = (!\z80_|execute_|ctl_alu_op_low~27_combout & ((\z80_|execute_|ctl_alu_core_hf~36_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|execute_|ctl_alu_op_low~17_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h0E0A; +defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~34_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'h1333; +defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~29_combout = (\z80_|execute_|ctl_mRead~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((!\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'hB0A0; +defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|execute_|ctl_mRead~4_combout +// & (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal56~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_alu_op_low~17_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((\z80_|execute_|ixy_d~7_combout ) # (\z80_|execute_|ctl_alu_core_hf~35_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & +// (((\z80_|execute_|ctl_alu_core_hf~35_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'h7740; +defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~28_combout = (\z80_|execute_|ctl_alu_core_hf~26_combout & ((\z80_|execute_|ctl_alu_core_hf~27_combout ) # ((\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'hAA80; +defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~34_combout & ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # (\z80_|execute_|ctl_alu_core_hf~28_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~37_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (((\z80_|execute_|ctl_alu_op_low~20_combout ) # (!\z80_|execute_|ctl_state_alu~11_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|execute_|ctl_state_alu~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~37 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_op_low~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_state_alu~2_combout & (((\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # +// (\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'hFC20; +defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~25_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (!\z80_|execute_|ctl_alu_op_low~20_combout & ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_alu_core_hf~24_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'h0032; +defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~31_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((\z80_|execute_|ctl_alu_core_hf~25_combout ) # ((\z80_|execute_|ctl_alu_core_hf~30_combout & !\z80_|execute_|ctl_alu_op_low~37_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~37_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'hFFAE; +defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~20_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hD0C0; +defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~20_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hCEEE; +defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~18_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~18_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~22_combout = (\z80_|execute_|ctl_alu_op_low~34_combout & (((!\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_alu_core_hf~19_combout )))) # (!\z80_|execute_|ctl_alu_op_low~34_combout & +// ((\z80_|execute_|ctl_alu_core_hf~21_combout ) # ((!\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_alu_core_hf~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'h4F44; +defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((\z80_|execute_|ctl_alu_core_hf~22_combout ) # ((\z80_|execute_|ctl_alu_core_hf~38_combout & !\z80_|execute_|ctl_alu_op_low~31_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hFCFE; +defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~33_combout = (\z80_|execute_|ctl_alu_core_hf~17_combout ) # ((\z80_|execute_|ctl_alu_core_hf~32_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N20 +cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( +// Equation(s): +// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~33_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~33_combout & (\z80_|alu_flags_|flags_cf~combout )) + + .dataa(\z80_|alu_flags_|flags_cf~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .datad(\z80_|alu_flags_|flags_hf~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hFA0A; +defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[0]~1_combout & \z80_|alu_control_|alu_core_cf_in~0_combout )))) +// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_control_|alu_core_cf_in~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[0]~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_|alu_op1[0]~1_combout ), + .datad(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( +// Equation(s): +// \z80_|alu_|db_high[0]~21_combout = (\z80_|alu_|op2_high [0] & (((\z80_|alu_|op1_high [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_high [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [0]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|alu_|op2_high [0]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|alu_|op1_high [0]), + .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N16 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( +// Equation(s): +// \z80_|alu_|db_high[0]~22_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~14_combout )) + + .dataa(\z80_|ir_|opcode [3]), + .datab(gnd), + .datac(\z80_|alu_|db[3]~14_combout ), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hFA50; +defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N2 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( +// Equation(s): +// \z80_|alu_|db_high[0]~23_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[0]~22_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[4]~10_combout )) + + .dataa(\z80_|alu_|db[4]~10_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(gnd), + .datad(\z80_|alu_|db_high[0]~22_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hEE22; +defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~20 ( +// Equation(s): +// \z80_|alu_|db_high[0]~20_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[4]~19_combout ), + .datab(\z80_|bus_control_|db[3]~21_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~20 .lut_mask = 16'h1F0F; +defparam \z80_|alu_|db_high[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( +// Equation(s): +// \z80_|alu_|db_high[0]~24_combout = (\z80_|alu_|db_high[0]~21_combout & (\z80_|alu_|db_high[0]~20_combout & ((\z80_|alu_|db_high[0]~23_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[0]~21_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[0]~23_combout ), + .datad(\z80_|alu_|db_high[0]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hA200; +defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( +// Equation(s): +// \z80_|alu_|db_high[0]~25_combout = ((\z80_|alu_|db_high[0]~24_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datac(\z80_|alu_|db_high[0]~24_combout ), + .datad(\z80_|alu_|db_high[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'hE0FF; +defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(\z80_|alu_|db_high[0]~25_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h0088; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N23 +dffeas \z80_|alu_|op1_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( +// Equation(s): +// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_high [0]), + .datad(\z80_|alu_|op1_low [0]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hFC30; +defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|alu_|op2_high [0]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hE2E2; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_|alu_op1[0]~1_combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|alu_|alu_op1[0]~1_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hBE28; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|execute_|ctl_alu_core_R~combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|execute_|ctl_alu_core_S~combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(\z80_|execute_|ctl_alu_core_R~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h0032; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h0F0E; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55F7; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hF2A2; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N19 +dffeas \z80_|alu_|result_lo[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~11 ( +// Equation(s): +// \z80_|alu_|db_low[2]~11_combout = (\z80_|alu_|result_lo [2]) # (\z80_|execute_|ctl_alu_res_oe~2_combout ) + + .dataa(gnd), + .datab(\z80_|alu_|result_lo [2]), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~11 .lut_mask = 16'hFFCC; +defparam \z80_|alu_|db_low[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N2 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~12 ( +// Equation(s): +// \z80_|alu_|db_low[2]~12_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [2] & ((\z80_|alu_|op2_low [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [2]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_low [2]), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~12 .lut_mask = 16'hDD0D; +defparam \z80_|alu_|db_low[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h5500; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~13 ( +// Equation(s): +// \z80_|alu_|db_low[2]~13_combout = (\z80_|alu_|db_low[2]~12_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|alu_|db_low[2]~12_combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~13 .lut_mask = 16'h7050; +defparam \z80_|alu_|db_low[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N28 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~14 ( +// Equation(s): +// \z80_|alu_|db_low[2]~14_combout = ((\z80_|alu_|db_low[2]~10_combout & (\z80_|alu_|db_low[2]~11_combout & \z80_|alu_|db_low[2]~13_combout ))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_low[2]~10_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|alu_|db_low[2]~11_combout ), + .datad(\z80_|alu_|db_low[2]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~14 .lut_mask = 16'hB333; +defparam \z80_|alu_|db_low[2]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N24 +cycloneive_lcell_comb \z80_|alu_|db[2]~11 ( +// Equation(s): +// \z80_|alu_|db[2]~11_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[2]~48_combout & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[2]~30_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .datad(\z80_|alu_control_|db[2]~30_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~11 .lut_mask = 16'hF531; +defparam \z80_|alu_|db[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N22 +cycloneive_lcell_comb \z80_|alu_|db[2]~12 ( +// Equation(s): +// \z80_|alu_|db[2]~12_combout = ((\z80_|alu_|db[2]~11_combout & ((\z80_|alu_|db_low[2]~14_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db_low[2]~14_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[2]~11_combout ), + .datad(\z80_|alu_|db[7]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~12 .lut_mask = 16'hB0FF; +defparam \z80_|alu_|db[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( +// Equation(s): +// \z80_|alu_control_|db[2]~28_combout = (\z80_|alu_|db[2]~12_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~q & ((\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_|db[2]~12_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((!\z80_|alu_flags_|DFFE_inst_latch_pf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_|db[2]~12_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h7350; +defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N12 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( +// Equation(s): +// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~33_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & +// (((\z80_|alu_flags_|flags_hf2~q )))) + + .dataa(\z80_|alu_control_|db[4]~33_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datac(\z80_|alu_flags_|flags_hf2~q ), + .datad(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hEEF0; +defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N13 +dffeas \z80_|alu_flags_|flags_hf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|flags_hf2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_hf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N12 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( +// Equation(s): +// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [2]) # (\z80_|alu_|op1_low [1]))) + + .dataa(gnd), + .datab(\z80_|alu_|op1_low [3]), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hCCC0; +defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~combout = (\z80_|pla_decode_|Equal47~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~24 ( +// Equation(s): +// \z80_|alu_control_|db[2]~24_combout = (\z80_|alu_flags_|flags_hf2~q ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|execute_|ctl_66_oe~combout ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|alu_flags_|flags_hf2~q ), + .datab(\z80_|alu_control_|out[6]~0_combout ), + .datac(\z80_|execute_|ctl_66_oe~combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~24 .lut_mask = 16'hFEFF; +defparam \z80_|alu_control_|db[2]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datac(\z80_|execute_|rsel3~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # (\z80_|pla_decode_|Equal40~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout )) + + .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[2]~1_combout = (\z80_|reg_file_|gdfx_temp0[2]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[2]~1 .lut_mask = 16'hCCEC; +defparam \z80_|reg_file_|db_lo_ds[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N18 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( +// Equation(s): +// \z80_|alu_control_|db[2]~29_combout = (\z80_|reg_file_|db_lo_ds[2]~1_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[2]~13_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), + .datab(\z80_|reg_file_|db_lo_ds[2]~1_combout ), + .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datad(\z80_|bus_control_|db[2]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h4C44; +defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~30 ( +// Equation(s): +// \z80_|alu_control_|db[2]~30_combout = ((!\z80_|alu_control_|db[2]~28_combout & (\z80_|alu_control_|db[2]~24_combout & \z80_|alu_control_|db[2]~29_combout ))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_control_|db[2]~28_combout ), + .datab(\z80_|alu_control_|db[2]~24_combout ), + .datac(\z80_|alu_control_|db[6]~13_combout ), + .datad(\z80_|alu_control_|db[2]~29_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~30 .lut_mask = 16'h4F0F; +defparam \z80_|alu_control_|db[2]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [2] & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|alu_control_|db[2]~30_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .datad(\z80_|alu_control_|db[2]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N31 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~41_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~41_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y17_N29 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & (\z80_|reg_file_|gdfx_temp0[2]~37_combout & \z80_|reg_file_|gdfx_temp0[2]~36_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~35_combout & (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~39_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~41_combout = ((\z80_|reg_file_|gdfx_temp0[2]~40_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .datac(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp0[2]~41_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[2]~41_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hCC0C; +defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hDF55; +defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N26 +cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( +// Equation(s): +// \z80_|address_latch_|abusz [2] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[2]~9_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [2]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N27 +dffeas \z80_|address_latch_|Q[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [2]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N18 +cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( +// Equation(s): +// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [3]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N21 +dffeas \z80_|address_latch_|Q[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_latch_|abusz [3]), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [2] & +// !\z80_|address_latch_|Q [3])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [2] & \z80_|address_latch_|Q [3])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [2]), + .datad(\z80_|address_latch_|Q [3]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h2008; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [4] $ +// (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [4]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [5]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N15 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[5]~17_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .datad(\z80_|alu_control_|db[5]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|gdfx_temp0[5]~65_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hC4C4; +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N15 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N31 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y17_N25 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|gdfx_temp0[5]~67_combout & (\z80_|reg_file_|gdfx_temp0[5]~66_combout & (\z80_|reg_file_|gdfx_temp0[5]~68_combout & \z80_|reg_file_|gdfx_temp0[5]~64_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N9 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~62_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~62 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[5]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~63_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~62_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~62_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~71_combout = ((\z80_|reg_file_|gdfx_temp0[5]~70_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'h8AFF; +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .datad(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .datab(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .datab(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'h8CFF; +defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N30 +cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( +// Equation(s): +// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~18_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [5]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N31 +dffeas \z80_|address_latch_|Q[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [5]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout = \z80_|address_latch_|Q [5] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|address_latch_|Q [5]), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0F4B; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N31 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N21 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~72 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[6]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|execute_|ctl_reg_sel_wz~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & ((\z80_|alu_control_|db[6]~23_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|alu_control_|db[6]~23_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .datad(\z80_|alu_control_|db[6]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y17_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout & (\z80_|reg_file_|gdfx_temp0[6]~77_combout & (\z80_|reg_file_|gdfx_temp0[6]~75_combout & \z80_|reg_file_|gdfx_temp0[6]~76_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N27 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~80_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N21 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|gdfx_temp0[6]~73_combout & (\z80_|reg_file_|gdfx_temp0[6]~72_combout & (\z80_|reg_file_|gdfx_temp0[6]~78_combout & \z80_|reg_file_|gdfx_temp0[6]~74_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~72_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~80_combout = ((\z80_|reg_file_|gdfx_temp0[6]~79_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hCC44; +defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datab(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'h8CFF; +defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( +// Equation(s): +// \z80_|address_latch_|abusz [6] = (\z80_|reg_file_|db_lo_as[6]~21_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h00CC; +defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N15 +dffeas \z80_|address_latch_|Q[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [6]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~7_combout ) # (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|execute_|ctl_inc_dec~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h0312; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q [7]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [8]), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'hD278; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [0] & ((\z80_|reg_file_|gdfx_temp1[0]~30_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[0]~30_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hAA22; +defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hB3BB; +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N20 +cycloneive_lcell_comb \z80_|alu_|db[0]~17 ( +// Equation(s): +// \z80_|alu_|db[0]~17_combout = (\z80_|reg_file_|gdfx_temp1[0]~30_combout & (((\z80_|alu_|db_low[0]~27_combout )) # (!\z80_|execute_|ctl_alu_oe~14_combout ))) # (!\z80_|reg_file_|gdfx_temp1[0]~30_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_|db_low[0]~27_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db_low[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~17 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N30 +cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( +// Equation(s): +// \z80_|alu_|db[0]~18_combout = ((\z80_|alu_|db[0]~17_combout & ((\z80_|alu_control_|db[0]~14_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_control_|db[0]~14_combout ), + .datab(\z80_|alu_|db[0]~17_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|alu_|db[7]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~18 .lut_mask = 16'h8CFF; +defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N20 +cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( +// Equation(s): +// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~18_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|sw2_|db_up[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hAAFF; +defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~11 ( +// Equation(s): +// \z80_|alu_control_|db[0]~11_combout = (\z80_|alu_control_|db[0]~10_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|alu_control_|db[0]~10_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datad(\z80_|sw2_|db_up[0]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~11 .lut_mask = 16'h8A00; +defparam \z80_|alu_control_|db[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~14 ( +// Equation(s): +// \z80_|alu_control_|db[0]~14_combout = ((\z80_|alu_control_|db[0]~11_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_control_|db[0]~11_combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|db[6]~13_combout ), + .datad(\z80_|alu_flags_|flags_cf~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~14 .lut_mask = 16'hAF2F; +defparam \z80_|alu_control_|db[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[0]~14_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .datad(\z80_|alu_control_|db[0]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y17_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) # (!\z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N1 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout & (\z80_|reg_file_|gdfx_temp0[0]~10_combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .datad(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'hC400; +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~14_combout & (\z80_|reg_file_|gdfx_temp0[0]~15_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .datab(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'h8C00; +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~13_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & (\z80_|reg_file_|gdfx_temp0[0]~11_combout & \z80_|reg_file_|gdfx_temp0[0]~16_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hB0FF; +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[0]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hAA0A; +defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hDF55; +defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N16 +cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( +// Equation(s): +// \z80_|address_latch_|abusz [0] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[0]~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [0]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N17 +dffeas \z80_|address_latch_|Q[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [0]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ ((((\z80_|execute_|ctl_inc_dec~7_combout ) # (\z80_|execute_|ctl_inc_dec~9_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~6_combout ), + .datab(\z80_|address_latch_|Q [0]), + .datac(\z80_|execute_|ctl_inc_dec~7_combout ), + .datad(\z80_|execute_|ctl_inc_dec~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h3339; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout +// ))))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|execute_|ctl_inc_cy~81_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datad(\z80_|execute_|ctl_inc_cy~93_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h5A6A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N17 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N15 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hC4C4; +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|alu_control_|db[1]~27_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|alu_control_|db[1]~27_combout & +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) + + .dataa(\z80_|alu_control_|db[1]~27_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hBB0B; +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~28_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & \z80_|reg_file_|gdfx_temp0[1]~29_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N3 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N15 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N13 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~23_combout & (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .datab(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'h8AFF; +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[1]~32_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .datad(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hF755; +defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( +// Equation(s): +// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [1]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N0 +cycloneive_lcell_comb \z80_|address_latch_|Q[1]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[1]~feeder_combout = \z80_|address_latch_|abusz [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [1]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N1 +dffeas \z80_|address_latch_|Q[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[1]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|execute_|ctl_inc_dec~9_combout ), + .datac(\z80_|execute_|ctl_inc_dec~7_combout ), + .datad(\z80_|execute_|ctl_inc_dec~6_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h5655; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout & +// ((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datab(\z80_|execute_|ctl_inc_cy~81_combout ), + .datac(\z80_|execute_|ctl_inc_cy~93_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .lut_mask = 16'hA800; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q +// [2]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [2]), + .datad(\z80_|address_latch_|Q [3]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'hD728; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~51_combout = ((\z80_|reg_file_|gdfx_temp0[3]~50_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( +// Equation(s): +// \z80_|alu_control_|db[3]~35_combout = (\z80_|alu_control_|db[3]~34_combout & (\z80_|sw1_|db_down[3]~3_combout & ((\z80_|reg_file_|gdfx_temp0[3]~51_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|alu_control_|db[3]~34_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|sw1_|db_down[3]~3_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hA020; +defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~36 ( +// Equation(s): +// \z80_|alu_control_|db[3]~36_combout = ((\z80_|alu_control_|db[3]~35_combout & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_|db[3]~14_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_control_|db[6]~13_combout ), + .datad(\z80_|alu_control_|db[3]~35_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~36 .lut_mask = 16'hBF0F; +defparam \z80_|alu_control_|db[3]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N26 +cycloneive_lcell_comb \z80_|alu_|db[3]~14 ( +// Equation(s): +// \z80_|alu_|db[3]~14_combout = ((\z80_|alu_|db[3]~13_combout & ((\z80_|alu_control_|db[3]~36_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~9_combout ), + .datab(\z80_|alu_|db[3]~13_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|alu_control_|db[3]~36_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~14 .lut_mask = 16'hDD5D; +defparam \z80_|alu_|db[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N0 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~4 ( +// Equation(s): +// \z80_|alu_|db_low[3]~4_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[2]~12_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_|db[2]~12_combout ), + .datad(\z80_|alu_|db[4]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~4 .lut_mask = 16'hFC30; +defparam \z80_|alu_|db_low[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N10 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~5 ( +// Equation(s): +// \z80_|alu_|db_low[3]~5_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~4_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~14_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db[3]~14_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datad(\z80_|alu_|db_low[3]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~5 .lut_mask = 16'hFD5D; +defparam \z80_|alu_|db_low[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N25 +dffeas \z80_|alu_|result_lo[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~6 ( +// Equation(s): +// \z80_|alu_|db_low[3]~6_combout = (\z80_|alu_|op1_low [3] & (((\z80_|alu_|op2_low [3])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_low [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [3]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_low [3]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op2_low [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~6 .lut_mask = 16'hAF23; +defparam \z80_|alu_|db_low[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~7 ( +// Equation(s): +// \z80_|alu_|db_low[3]~7_combout = (\z80_|alu_|db_low[3]~6_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|alu_|db_low[3]~6_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~7 .lut_mask = 16'h2A0A; +defparam \z80_|alu_|db_low[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~8 ( +// Equation(s): +// \z80_|alu_|db_low[3]~8_combout = (\z80_|alu_|db_low[3]~5_combout & (\z80_|alu_|db_low[3]~7_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [3])))) + + .dataa(\z80_|alu_|db_low[3]~5_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|result_lo [3]), + .datad(\z80_|alu_|db_low[3]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~8 .lut_mask = 16'hA800; +defparam \z80_|alu_|db_low[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~26 ( +// Equation(s): +// \z80_|alu_|db_low[3]~26_combout = (\z80_|alu_|db_low[3]~8_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[3]~0_combout ), + .datad(\z80_|alu_|db_low[3]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~26 .lut_mask = 16'hFF03; +defparam \z80_|alu_|db_low[3]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) + + .dataa(\z80_|alu_|op1_high [3]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [3]), + .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .lut_mask = 16'hE200; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[3]~26_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|alu_|db_low[3]~26_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .lut_mask = 16'h0F08; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N13 +dffeas \z80_|alu_|op2_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_high[3]~7_combout ) # ((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # +// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|alu_|db_high[3]~7_combout ), + .datac(\z80_|alu_|db_low[3]~26_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N21 +dffeas \z80_|alu_|op2_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N14 +cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~0 ( +// Equation(s): +// \z80_|alu_|alu_op2[3]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [3]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [3])))) + + .dataa(\z80_|alu_|op2_low [3]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|alu_|op2_high [3]), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[3]~0 .lut_mask = 16'h1DE2; +defparam \z80_|alu_|alu_op2[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op2[3]~0_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & \z80_|alu_|alu_op1[3]~0_combout )) # (!\z80_|alu_|alu_op2[3]~0_combout & +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & !\z80_|alu_|alu_op1[3]~0_combout )) + + .dataa(\z80_|alu_|alu_op2[3]~0_combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_|alu_op1[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'h0A50; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout & (\z80_|alu_|alu_op2[3]~0_combout )) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout & +// (((!\z80_|execute_|ctl_alu_core_R~4_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[3]~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .lut_mask = 16'hAA3F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( +// Equation(s): +// \z80_|alu_|db_high[3]~4_combout = (\z80_|alu_|op1_high [3] & (((\z80_|alu_|op2_high [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [3]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [3]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_high [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( +// Equation(s): +// \z80_|alu_|db_high[3]~2_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_|db[6]~22_combout ), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFC30; +defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( +// Equation(s): +// \z80_|alu_|db_high[3]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[3]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[7]~20_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datab(\z80_|alu_|db[7]~20_combout ), + .datac(\z80_|alu_|db_high[3]~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hE4FF; +defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( +// Equation(s): +// \z80_|alu_|db_high[3]~5_combout = (\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[4]~19_combout )) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'h8800; +defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( +// Equation(s): +// \z80_|alu_|db_high[3]~6_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~3_combout & ((\z80_|alu_|db_high[3]~5_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|alu_|db_high[3]~4_combout ), + .datab(\z80_|alu_|db_high[3]~3_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|db_high[3]~5_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'h8808; +defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( +// Equation(s): +// \z80_|alu_|db_high[3]~7_combout = ((\z80_|alu_|db_high[3]~6_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|db_high[3]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'hFB33; +defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|execute_|ctl_flags_alu~19_combout & \z80_|alu_|db_high[3]~7_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datab(\z80_|execute_|ctl_flags_alu~19_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .datad(\z80_|alu_|db_high[3]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFDF5; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_shift_oe~38_combout & \z80_|execute_|ctl_alu_core_S~11_combout +// ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~11_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout & (((!\z80_|execute_|ctl_state_alu~12_combout ) # (!\z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'h7F00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (!\z80_|pla_decode_|Equal73~2_combout & (!\z80_|execute_|ctl_alu_sel_op2_neg~16_combout & !\z80_|execute_|ctl_alu_op_low~39_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .datab(\z80_|pla_decode_|Equal73~2_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h0002; +defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout & (\z80_|execute_|ctl_alu_core_hf~14_combout & (\z80_|execute_|ctl_flags_nf_we~0_combout & \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal61~2_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~3_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_nf_we~2_combout ) # (!\z80_|execute_|ctl_flags_xy_we~12_combout ))) # (!\z80_|execute_|ctl_flags_nf_we~1_combout ) + + .dataa(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~14 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~14_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (((!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~14 .lut_mask = 16'h0155; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~13 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout & \z80_|execute_|ctl_alu_core_hf~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~13 .lut_mask = 16'hF000; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~15 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~15_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (!\z80_|pla_decode_|Equal73~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .datab(\z80_|pla_decode_|Equal73~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~15 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~16 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~16_combout = (\z80_|execute_|ctl_flags_nf_we~3_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~3_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .datab(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~16 .lut_mask = 16'hB830; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N25 +dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~3_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_op_low~18_combout )))) # (!\z80_|execute_|ctl_state_alu~13_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datad(\z80_|execute_|ctl_state_alu~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'h32FF; +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal68~2_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .datad(\z80_|pla_decode_|Equal68~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hA2A0; +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~5_combout = (\z80_|execute_|ctl_flags_cf_cpl~4_combout ) # ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'hF0FE; +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_set~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_set~0_combout = (\z80_|execute_|ctl_state_alu~12_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal9~0_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~12_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_set~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_set~0 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_cf_set~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_state_alu~3_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout & +// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), + .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~2_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((\z80_|execute_|ctl_flags_cf_set~0_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~6_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .datac(\z80_|execute_|ctl_flags_cf_set~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N18 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( +// Equation(s): +// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [1]) # ((\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [0] & \z80_|alu_control_|out[6]~0_combout ))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|alu_|op1_high [0]), + .datac(\z80_|alu_|op1_high [2]), + .datad(\z80_|alu_control_|out[6]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEFA; +defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( +// Equation(s): +// \z80_|alu_control_|out[6]~2_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_|op1_high [3] & \z80_|alu_control_|out[6]~1_combout ))) + + .dataa(\z80_|alu_|op1_high [3]), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|execute_|ctl_66_oe~combout ), + .datad(\z80_|alu_control_|out[6]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFEFC; +defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~18_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_|db[7]~20_combout ), + .datad(\z80_|alu_|db[0]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hFC30; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N12 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|execute_|ctl_alu_core_R~combout +// & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hCC50; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_we~5_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~5_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_flags_cf2_we~5_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h7430; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N30 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_control_|out[6]~2_combout & !\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|alu_control_|out[6]~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'hF0F8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N31 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~10_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h4050; +defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal10~0_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|pla_decode_|Equal20~0_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h00EC; +defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~11_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout ))) + + .dataa(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hAAAC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N14 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = (\z80_|execute_|ctl_state_alu~12_combout & ((\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'h8044; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal63~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'hAEAA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~21_combout = (\z80_|pla_decode_|Equal10~1_combout & (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|pla_decode_|Equal10~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ) # ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~21_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'hFEFF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ) # ((\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFF8F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) # ((\z80_|execute_|ctl_alu_op_low~35_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'hFFEA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_state_alu~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~1_combout = (\z80_|pla_decode_|Equal64~0_combout & (\z80_|execute_|ctl_alu_op_low~35_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal64~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~1 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_flags_cf_cpl~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'hA8A0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout & ((\z80_|execute_|ctl_alu_op_low~30_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~40_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~40_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'hCCC8; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|pla_decode_|Equal61~2_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .lut_mask = 16'h0313; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout = (\z80_|execute_|ctl_alu_core_R~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & \z80_|execute_|ctl_flags_alu~10_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_R~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .lut_mask = 16'h8800; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|nM1_int~2_combout & +// (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal56~0_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .lut_mask = 16'h135F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~0 .lut_mask = 16'hFCEC; +defparam \z80_|execute_|ctl_flags_cf_cpl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_flags_cf_cpl~0_combout ) # (!\z80_|execute_|ctl_alu_op_low~34_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h040C; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = ((!\z80_|pla_decode_|Equal39~0_combout & ((!\z80_|pla_decode_|Equal40~2_combout ) # (!\z80_|ir_|opcode [5])))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal40~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h5777; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'h3330; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & \z80_|execute_|ctl_flags_nf_we~0_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .datad(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N2 +cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( +// Equation(s): +// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~1_combout ))))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_cf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h3600; +defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & (((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (\z80_|nM1_int~2_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (\z80_|pla_decode_|Equal10~0_combout & +// (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hECE0; +defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~18_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ) # ((\z80_|alu_control_|db[4]~33_combout & \z80_|execute_|ctl_flags_bus~combout )) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[4]~33_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'hFCF0; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N30 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_hf~q )))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (((\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )))) + + .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hFD20; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N31 +dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~9_combout = ((!\z80_|pla_decode_|Equal52~0_combout & ((\z80_|decode_state_|use_ixiy~combout ) # (!\z80_|pla_decode_|Equal44~0_combout )))) # (!\z80_|pla_decode_|Equal33~0_combout ) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~9 .lut_mask = 16'h45FF; +defparam \z80_|execute_|ctl_flags_hf_cpl~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (\z80_|execute_|ctl_alu_op_low~18_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_hf_cpl~10_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~8_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), + .datad(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'h2202; +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N12 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( +// Equation(s): +// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) + + .dataa(\z80_|alu_flags_|flags_cf~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h393C; +defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( +// Equation(s): +// \z80_|alu_control_|db[4]~31_combout = (\z80_|execute_|ctl_reg_out_lo~8_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[4]~10_combout )) # (!\z80_|reg_file_|gdfx_temp0[4]~61_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~8_combout & +// (\z80_|execute_|ctl_sw_2u~7_combout & ((!\z80_|alu_|db[4]~10_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .datad(\z80_|alu_|db[4]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h0ACE; +defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( +// Equation(s): +// \z80_|alu_control_|db[4]~32_combout = (!\z80_|alu_control_|db[4]~31_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_flags_|flags_hf~combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|db[4]~31_combout ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'h0B00; +defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~33 ( +// Equation(s): +// \z80_|alu_control_|db[4]~33_combout = ((\z80_|alu_control_|db[4]~32_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_control_|db[6]~13_combout ), + .datab(\z80_|execute_|ctl_sw_1d~7_combout ), + .datac(\z80_|bus_control_|db[4]~19_combout ), + .datad(\z80_|alu_control_|db[4]~32_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~33 .lut_mask = 16'hF755; +defparam \z80_|alu_control_|db[4]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N15 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N29 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~52_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~52 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[4]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|gdfx_temp0[4]~52_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|alu_control_|db[4]~33_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~52_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hDD00; +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N23 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y15_N3 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y17_N9 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N1 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y17_N11 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N19 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|gdfx_temp0[4]~58_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datad(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'h8808; +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~56_combout & (\z80_|reg_file_|gdfx_temp0[4]~53_combout & (\z80_|reg_file_|gdfx_temp0[4]~55_combout & \z80_|reg_file_|gdfx_temp0[4]~59_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~61_combout = ((\z80_|reg_file_|gdfx_temp0[4]~60_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .datab(gnd), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hAF00; +defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N22 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ) + + .dataa(\z80_|address_latch_|Q [4]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h55AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .datab(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N4 +cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( +// Equation(s): +// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~15_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [4]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N5 +dffeas \z80_|address_latch_|Q[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [4]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N6 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [4] & (!\z80_|address_latch_|Q [5] & (!\z80_|address_latch_|Q [6] & !\z80_|address_latch_|Q [7]))) + + .dataa(\z80_|address_latch_|Q [4]), + .datab(\z80_|address_latch_|Q [5]), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N30 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [8] & (!\z80_|address_latch_|Q [9] & !\z80_|address_latch_|Q [11]))) + + .dataa(\z80_|address_latch_|Q [10]), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|Q [11]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N20 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~3_combout = (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [3] & (!\z80_|address_latch_|Q [2] & !\z80_|address_latch_|Q [1]))) + + .dataa(\z80_|address_latch_|Q [0]), + .datab(\z80_|address_latch_|Q [3]), + .datac(\z80_|address_latch_|Q [2]), + .datad(\z80_|address_latch_|Q [1]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0002; +defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N16 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [13] & (!\z80_|address_latch_|Q [12] & (!\z80_|address_latch_|Q [15] & !\z80_|address_latch_|Q [14]))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|address_latch_|Q [12]), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|Q [14]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N26 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~2_combout & (\z80_|decode_state_|DFFE_instNonRep~1_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & \z80_|decode_state_|DFFE_instNonRep~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; +defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N12 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~9_combout & +// ((\z80_|decode_state_|DFFE_instNonRep~4_combout ))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|decode_state_|DFFE_instNonRep~q )))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hF4B0; +defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N13 +dffeas \z80_|decode_state_|DFFE_instNonRep ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instNonRep~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N30 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & (!\z80_|pla_decode_|Equal62~3_combout & (\z80_|execute_|ctl_pf_sel[0]~13_combout & \z80_|execute_|ctl_pf_sel[0]~10_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datab(\z80_|pla_decode_|Equal62~3_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h1000; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N18 +cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( +// Equation(s): +// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & (\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal79~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|pla_decode_|Equal79~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hD8F0; +defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N4 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|interrupts_|DFFE_inst44~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h5F0F; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G16 +cycloneive_clkctrl \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X30_Y12_N19 +dffeas \z80_|interrupts_|DFFE_instIFF2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|DFFE_instIFF2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'h80C4; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & +// (!\z80_|decode_state_|DFFE_instNonRep~q )))) + + .dataa(\z80_|decode_state_|DFFE_instNonRep~q ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'hC500; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|pla_decode_|Equal62~3_combout ) # (\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout ) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|pla_decode_|Equal62~3_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'hFFFD; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|execute_|ctl_pf_sel[0]~13_combout & (\z80_|execute_|ctl_pf_sel[0]~10_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'h4C00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[1]~12 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[1]~12_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[1]~12 .lut_mask = 16'h0031; +defparam \z80_|execute_|ctl_pf_sel[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~11 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~11_combout = (\z80_|nM1_int~2_combout & (((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|pla_decode_|Equal62~3_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|pla_decode_|Equal62~3_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~11 .lut_mask = 16'hFD00; +defparam \z80_|execute_|ctl_pf_sel[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (!\z80_|execute_|ctl_pf_sel[1]~12_combout & (((\z80_|execute_|ctl_pf_sel[0]~11_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~10_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .datab(\z80_|execute_|ctl_pf_sel[1]~12_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~11_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h3133; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ (((\z80_|execute_|ctl_alu_core_R~combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ))))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h6500; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N17 +dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|alu_parity_out~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N2 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( +// Equation(s): +// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'h6996; +defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( +// Equation(s): +// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .datad(\z80_|alu_|alu_parity_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out .lut_mask = 16'h03FC; +defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout & \z80_|alu_|alu_parity_out~combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .datad(\z80_|alu_|alu_parity_out~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'hFEFA; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~10_combout & (((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[2]~30_combout )))) # (!\z80_|execute_|ctl_flags_pf_we~10_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_pf~q )) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datab(\z80_|execute_|ctl_flags_bus~combout ), + .datac(\z80_|alu_control_|db[2]~30_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'hC0AA; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout & \z80_|execute_|ctl_flags_alu~19_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .datac(\z80_|execute_|ctl_flags_alu~19_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFF80; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y11_N25 +dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal13~0_combout ) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hF7FF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[2]~14_combout & (!\z80_|alu_|db_low[0]~27_combout & (!\z80_|alu_|db_low[3]~26_combout & !\z80_|alu_|db_low[1]~20_combout ))) + + .dataa(\z80_|alu_|db_low[2]~14_combout ), + .datab(\z80_|alu_|db_low[0]~27_combout ), + .datac(\z80_|alu_|db_low[3]~26_combout ), + .datad(\z80_|alu_|db_low[1]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_high[1]~19_combout & (!\z80_|alu_|db_high[0]~25_combout & (!\z80_|alu_|db_high[2]~13_combout & !\z80_|alu_|db_high[3]~7_combout ))) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|alu_|db_high[0]~25_combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|alu_|db_high[3]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout = (\z80_|execute_|ctl_flags_alu~19_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_alu~19_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hC000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ) # ((\z80_|alu_control_|db[6]~23_combout & \z80_|execute_|ctl_flags_bus~combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .datab(\z80_|alu_control_|db[6]~23_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hA8A0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N25 +dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ) # ((\z80_|alu_control_|sel[1]~0_combout )))) # (!\z80_|ir_|opcode [4] & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & +// !\z80_|alu_control_|sel[1]~0_combout )))) + + .dataa(\z80_|alu_flags_|flags_cf~combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|alu_control_|sel[1]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hF0AC; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) + + .dataa(\z80_|alu_control_|sel[1]~0_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hF588; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N8 +cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( +// Equation(s): +// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((\z80_|alu_control_|flags_cond_true~q )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|flags_cond_true~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hD872; +defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N9 +dffeas \z80_|alu_control_|flags_cond_true ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_control_|flags_cond_true~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|flags_cond_true~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; +defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|execute_|ctl_reg_sys_we_lo~1_combout ) # (\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hA8FF; +defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~combout = (((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (\z80_|reg_control_|reg_sys_we_hi~0_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF7; +defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~44_combout ) # ((\z80_|reg_control_|reg_sw_4d_hi~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datac(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~7 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~7_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [3] & ((\z80_|reg_file_|gdfx_temp1[3]~39_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[3]~39_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~7 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|db_hi_as[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~8 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~8_combout = (\z80_|reg_file_|db_hi_as[3]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[3]~7_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~8 .lut_mask = 16'hAA22; +defparam \z80_|reg_file_|db_hi_as[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~9 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~9_combout = ((\z80_|reg_file_|db_hi_as[3]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datac(\z80_|reg_file_|db_hi_as[3]~8_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~9 .lut_mask = 16'hD5F5; +defparam \z80_|reg_file_|db_hi_as[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N12 +cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( +// Equation(s): +// \z80_|address_latch_|abusz [11] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[3]~9_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N13 +dffeas \z80_|address_latch_|Q[11] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [11]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|Q [11] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [11]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N14 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [11]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h5505; +defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N6 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~2_combout = (\z80_|execute_|fIORead~3_combout ) # (((\z80_|execute_|fMRead~36_combout ) # (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )) + + .dataa(\z80_|execute_|fIORead~3_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datac(\z80_|execute_|fMRead~36_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFBFF; +defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N12 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|pin_control_|bus_ab_pin_we~2_combout & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) # (!\z80_|pin_control_|bus_ab_pin_we~2_combout & +// (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h22F2; +defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N15 +dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .asdata(\z80_|address_latch_|Q [11]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y4_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( +// Equation(s): +// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [11]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[11]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N4 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [10])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [10]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N5 +dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .asdata(\z80_|address_latch_|Q [10]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[10]~20 ( +// Equation(s): +// \z80_|address_pins_|abus[10]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [10]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[10]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[10]~20 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[10]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~19 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|extended~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~19 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|keys[7][1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~48 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~48_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~48_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~48 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[7][4]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~51 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~51_combout = (\ula_|zx_keyboard_|keys[3][2]~50_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[3][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][2]~50_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .datac(\ula_|zx_keyboard_|keys[3][2]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~51 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][2]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N7 dffeas \ula_|zx_keyboard_|keys[3][2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][2]~54_combout ), + .d(\ula_|zx_keyboard_|keys[3][2]~51_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49332,80 +39425,221 @@ defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N8 -cycloneive_lcell_comb \D[2]~36 ( +// Location: LCCOMB_X23_Y9_N26 +cycloneive_lcell_comb \D[2]~43 ( // Equation(s): -// \D[2]~36_combout = (\ula_|zx_keyboard_|keys[2][2]~q & (\z80_|address_pins_|abus[10]~24_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) # (!\ula_|zx_keyboard_|keys[2][2]~q & -// (((\z80_|address_pins_|abus[11]~19_combout )) # (!\ula_|zx_keyboard_|keys[3][2]~q ))) +// \D[2]~43_combout = (\ula_|zx_keyboard_|keys[2][2]~q & (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) # (!\ula_|zx_keyboard_|keys[2][2]~q & +// ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][2]~q )))) .dataa(\ula_|zx_keyboard_|keys[2][2]~q ), - .datab(\ula_|zx_keyboard_|keys[3][2]~q ), - .datac(\z80_|address_pins_|abus[10]~24_combout ), - .datad(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\z80_|address_pins_|abus[11]~19_combout ), + .datac(\z80_|address_pins_|abus[10]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[3][2]~q ), .cin(gnd), - .combout(\D[2]~36_combout ), + .combout(\D[2]~43_combout ), .cout()); // synopsys translate_off -defparam \D[2]~36 .lut_mask = 16'hF531; -defparam \D[2]~36 .sum_lutc_input = "datac"; +defparam \D[2]~43 .lut_mask = 16'hC4F5; +defparam \D[2]~43 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y19_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~68 ( +// Location: LCCOMB_X20_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~68_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [1]))) +// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|WideOr17~0_combout )) .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|WideOr17~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .combout(\ula_|zx_keyboard_|shifted~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~68 .lut_mask = 16'h0180; -defparam \ula_|zx_keyboard_|keys[6][2]~68 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y20_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~69 ( +// Location: LCCOMB_X19_Y10_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~11 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~69_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~68_combout )) +// \ula_|zx_keyboard_|keys[0][0]~11_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|Equal0~1_combout )) - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~11 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|keys[0][0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h000A; +defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~0_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # +// (!\ula_|zx_keyboard_|shifted~2_combout & (((\ula_|zx_keyboard_|shifted~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|shifted~2_combout ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|shifted~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y8_N31 +dffeas \ula_|zx_keyboard_|shifted ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|shifted~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|shifted~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|shifted .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~62 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~62_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~62_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~62 .lut_mask = 16'hF0FC; +defparam \ula_|zx_keyboard_|keys[5][0]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~32 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~32_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|zx_keyboard_|extended~q & \ula_|zx_keyboard_|keys[0][0]~11_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~32 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~63 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~63_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~63_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~63 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[6][2]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~64 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~64_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~63_combout ) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .datad(\ula_|zx_keyboard_|keys[6][2]~63_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .combout(\ula_|zx_keyboard_|keys[6][2]~64_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~69 .lut_mask = 16'h2200; -defparam \ula_|zx_keyboard_|keys[6][2]~69 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][2]~64 .lut_mask = 16'h5500; +defparam \ula_|zx_keyboard_|keys[6][2]~64 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~70 ( +// Location: LCCOMB_X21_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~65 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~70_combout = (\ula_|zx_keyboard_|keys[6][2]~69_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~69_combout & ((\ula_|zx_keyboard_|keys[6][2]~q ))) +// \ula_|zx_keyboard_|keys[6][2]~65_combout = (\ula_|zx_keyboard_|keys[6][1]~32_combout & ((\ula_|zx_keyboard_|keys[6][2]~64_combout & (!\ula_|zx_keyboard_|keys[5][0]~62_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~64_combout & +// ((\ula_|zx_keyboard_|keys[6][2]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~32_combout & (((\ula_|zx_keyboard_|keys[6][2]~q )))) - .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .datab(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .dataa(\ula_|zx_keyboard_|keys[5][0]~62_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~32_combout ), .datac(\ula_|zx_keyboard_|keys[6][2]~q ), - .datad(gnd), + .datad(\ula_|zx_keyboard_|keys[6][2]~64_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~70_combout ), + .combout(\ula_|zx_keyboard_|keys[6][2]~65_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~70 .lut_mask = 16'h7474; -defparam \ula_|zx_keyboard_|keys[6][2]~70 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][2]~65 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[6][2]~65 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y20_N1 +// Location: FF_X21_Y9_N5 dffeas \ula_|zx_keyboard_|keys[6][2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][2]~70_combout ), + .d(\ula_|zx_keyboard_|keys[6][2]~65_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49421,112 +39655,253 @@ defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( +// Location: LCCOMB_X31_Y16_N18 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~61_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) +// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) + + .dataa(\z80_|address_latch_|abusz [15]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N19 +dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .asdata(\z80_|address_latch_|Q [15]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[15]~21 ( +// Equation(s): +// \z80_|address_pins_|abus[15]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .combout(\z80_|address_pins_|abus[15]~21_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[15]~21 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[15]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~62 ( +// Location: LCCOMB_X31_Y16_N22 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~62_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[7][2]~61_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0]))) +// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [14])) + + .dataa(\z80_|address_latch_|abusz [14]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N23 +dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .asdata(\z80_|address_latch_|Q [14]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N14 +cycloneive_lcell_comb \z80_|address_pins_|abus[14]~22 ( +// Equation(s): +// \z80_|address_pins_|abus[14]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[14]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[14]~22 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[14]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~57 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~57_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~57_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~57 .lut_mask = 16'h3030; +defparam \ula_|zx_keyboard_|keys[7][2]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~58 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~58_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~57_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[7][2]~57_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~58_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~58 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[7][2]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~59 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~59_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~59 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|keys[5][4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~28 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~28_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5])) .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(gnd), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~62_combout ), + .combout(\ula_|zx_keyboard_|keys[7][2]~28_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~62 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[7][2]~62 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[7][2]~28 .lut_mask = 16'h0404; +defparam \ula_|zx_keyboard_|keys[7][2]~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~64 ( +// Location: LCCOMB_X21_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~60 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~64_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~62_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~63_combout & \ula_|zx_keyboard_|keys[7][2]~32_combout )))) +// \ula_|zx_keyboard_|keys[7][2]~60_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~58_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~59_combout & \ula_|zx_keyboard_|keys[7][2]~28_combout )))) - .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .dataa(\ula_|zx_keyboard_|keys[7][2]~58_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~59_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .combout(\ula_|zx_keyboard_|keys[7][2]~60_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~64 .lut_mask = 16'hC8C0; -defparam \ula_|zx_keyboard_|keys[7][2]~64 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[7][2]~60 .lut_mask = 16'hE0A0; +defparam \ula_|zx_keyboard_|keys[7][2]~60 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~65 ( +// Location: LCCOMB_X20_Y8_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~56 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~65_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~15_combout & \ula_|zx_keyboard_|keys[7][2]~64_combout ))) +// \ula_|zx_keyboard_|keys[7][2]~56_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[0][0]~11_combout & !\ula_|zx_keyboard_|extended~q )) .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~65_combout ), + .combout(\ula_|zx_keyboard_|keys[7][2]~56_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~65 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|keys[7][2]~65 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[7][2]~56 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|keys[7][2]~56 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N22 +// Location: LCCOMB_X23_Y8_N28 cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( // Equation(s): -// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [5])) +// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q )) - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|released~q ), + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), .cin(gnd), .combout(\ula_|zx_keyboard_|Selector13~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hFF22; +defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hF5F0; defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~66 ( +// Location: LCCOMB_X23_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~66_combout = (\ula_|zx_keyboard_|keys[7][2]~65_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~65_combout & (\ula_|zx_keyboard_|keys[7][2]~q )) +// \ula_|zx_keyboard_|keys[7][2]~61_combout = (\ula_|zx_keyboard_|keys[7][2]~60_combout & ((\ula_|zx_keyboard_|keys[7][2]~56_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~56_combout & +// (\ula_|zx_keyboard_|keys[7][2]~q )))) # (!\ula_|zx_keyboard_|keys[7][2]~60_combout & (((\ula_|zx_keyboard_|keys[7][2]~q )))) - .dataa(\ula_|zx_keyboard_|keys[7][2]~65_combout ), - .datab(gnd), + .dataa(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .datab(\ula_|zx_keyboard_|keys[7][2]~56_combout ), .datac(\ula_|zx_keyboard_|keys[7][2]~q ), .datad(\ula_|zx_keyboard_|Selector13~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~66_combout ), + .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~66 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[7][2]~66 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y21_N13 +// Location: FF_X23_Y8_N1 dffeas \ula_|zx_keyboard_|keys[7][2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][2]~66_combout ), + .d(\ula_|zx_keyboard_|keys[7][2]~61_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49542,173 +39917,1135 @@ defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N0 -cycloneive_lcell_comb \D[2]~38 ( +// Location: LCCOMB_X23_Y9_N10 +cycloneive_lcell_comb \D[2]~44 ( // Equation(s): -// \D[2]~38_combout = (\z80_|address_pins_|abus[15]~22_combout & (((\z80_|address_pins_|abus[14]~23_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~q ))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][2]~q & -// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) +// \D[2]~44_combout = (\ula_|zx_keyboard_|keys[6][2]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][2]~q )))) # (!\ula_|zx_keyboard_|keys[6][2]~q & +// ((\z80_|address_pins_|abus[15]~21_combout ) # ((!\ula_|zx_keyboard_|keys[7][2]~q )))) - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ula_|zx_keyboard_|keys[6][2]~q ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), + .dataa(\ula_|zx_keyboard_|keys[6][2]~q ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), .datad(\ula_|zx_keyboard_|keys[7][2]~q ), .cin(gnd), - .combout(\D[2]~38_combout ), + .combout(\D[2]~44_combout ), .cout()); // synopsys translate_off -defparam \D[2]~38 .lut_mask = 16'hA2F3; -defparam \D[2]~38 .sum_lutc_input = "datac"; +defparam \D[2]~44 .lut_mask = 16'hC4F5; +defparam \D[2]~44 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N14 -cycloneive_lcell_comb \D[2]~39 ( +// Location: LCCOMB_X31_Y16_N24 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( // Equation(s): -// \D[2]~39_combout = (\D[2]~35_combout & (\D[2]~37_combout & (\D[2]~36_combout & \D[2]~38_combout ))) +// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [12])) - .dataa(\D[2]~35_combout ), - .datab(\D[2]~37_combout ), - .datac(\D[2]~36_combout ), - .datad(\D[2]~38_combout ), + .dataa(\z80_|address_latch_|abusz [12]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), .cin(gnd), - .combout(\D[2]~39_combout ), + .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), .cout()); // synopsys translate_off -defparam \D[2]~39 .lut_mask = 16'h8000; -defparam \D[2]~39 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N14 -cycloneive_lcell_comb \D[2]~104 ( +// Location: FF_X31_Y16_N25 +dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .asdata(\z80_|address_latch_|Q [12]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[12]~24 ( // Equation(s): -// \D[2]~104_combout = ((\z80_|address_pins_|DFFE_apin_latch [0]) # (\D[2]~39_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|address_pins_|abus[12]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [12]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[12]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[12]~24 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[12]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N0 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [13]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datab(\z80_|address_latch_|abusz [13]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N1 +dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .asdata(\z80_|address_latch_|Q [13]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~29 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~29_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[7][2]~28_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~29_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~29 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[5][2]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~54 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~54_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~54_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~54 .lut_mask = 16'h0C0C; +defparam \ula_|zx_keyboard_|keys[5][2]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~55 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~55_combout = (\ula_|zx_keyboard_|keys[5][2]~29_combout & ((\ula_|zx_keyboard_|keys[5][2]~54_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][2]~54_combout & ((\ula_|zx_keyboard_|keys[5][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~29_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~29_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[5][2]~q ), + .datad(\ula_|zx_keyboard_|keys[5][2]~54_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~55_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~55 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][2]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y10_N31 +dffeas \ula_|zx_keyboard_|keys[5][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][2]~55_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~1_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # ((!\ula_|zx_keyboard_|keys[5][2]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|zx_keyboard_|keys[5][2]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hCFFF; +defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~127 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~127_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|Equal0~1_combout ))) + + .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~127_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~127 .lut_mask = 16'h0008; +defparam \ula_|zx_keyboard_|keys[3][4]~127 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~66 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~66_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~66_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~66 .lut_mask = 16'h0240; +defparam \ula_|zx_keyboard_|keys[4][2]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~128 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~128_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[4][2]~66_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|keys[4][2]~66_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~128_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~128 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[4][2]~128 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~67 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~67_combout = (\ula_|zx_keyboard_|keys[3][4]~127_combout & ((\ula_|zx_keyboard_|keys[4][2]~128_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][2]~128_combout & ((\ula_|zx_keyboard_|keys[4][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~127_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][4]~127_combout ), + .datac(\ula_|zx_keyboard_|keys[4][2]~q ), + .datad(\ula_|zx_keyboard_|keys[4][2]~128_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~67_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~67 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][2]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N23 +dffeas \ula_|zx_keyboard_|keys[4][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][2]~67_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N18 +cycloneive_lcell_comb \D[2]~45 ( +// Equation(s): +// \D[2]~45_combout = (\D[2]~44_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\D[2]~44_combout ), + .datab(\z80_|address_pins_|abus[12]~24_combout ), + .datac(\ula_|zx_keyboard_|key_row~1_combout ), + .datad(\ula_|zx_keyboard_|keys[4][2]~q ), + .cin(gnd), + .combout(\D[2]~45_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~45 .lut_mask = 16'h80A0; +defparam \D[2]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N26 +cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( +// Equation(s): +// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [0]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~43 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~43_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~43_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~43 .lut_mask = 16'h0808; +defparam \ula_|zx_keyboard_|keys[6][4]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~44 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~44_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[7][1]~19_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~44_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~44 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][4]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~45 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~45_combout = (\ula_|zx_keyboard_|keys[6][4]~43_combout & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~44_combout )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[6][4]~43_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[6][4]~44_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~45_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~45 .lut_mask = 16'h0C00; +defparam \ula_|zx_keyboard_|keys[1][2]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~46 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~46_combout = (\ula_|zx_keyboard_|keys[1][2]~45_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][2]~45_combout & ((\ula_|zx_keyboard_|keys[1][2]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[1][2]~q ), + .datad(\ula_|zx_keyboard_|keys[1][2]~45_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~46_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~46 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[1][2]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y9_N15 +dffeas \ula_|zx_keyboard_|keys[1][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][2]~46_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~47 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~47_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~47 .lut_mask = 16'h0055; +defparam \ula_|zx_keyboard_|keys[0][2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~49 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~49_combout = (\ula_|zx_keyboard_|keys[0][2]~47_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[0][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[0][2]~47_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[0][2]~47_combout ), + .datac(\ula_|zx_keyboard_|keys[0][2]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~49_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~49 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[0][2]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N13 +dffeas \ula_|zx_keyboard_|keys[0][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][2]~49_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N8 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [9])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [9]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N9 +dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .asdata(\z80_|address_latch_|Q [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N28 +cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( +// Equation(s): +// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [9]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[9]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N24 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [8]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [8]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N25 +dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .asdata(\z80_|address_latch_|Q [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N24 +cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( +// Equation(s): +// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [8]), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[8]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hCCFF; +defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N20 +cycloneive_lcell_comb \D[2]~42 ( +// Equation(s): +// \D[2]~42_combout = (\ula_|zx_keyboard_|keys[1][2]~q & (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][2]~q )))) # (!\ula_|zx_keyboard_|keys[1][2]~q & +// (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[1][2]~q ), + .datab(\ula_|zx_keyboard_|keys[0][2]~q ), + .datac(\z80_|address_pins_|abus[9]~17_combout ), + .datad(\z80_|address_pins_|abus[8]~18_combout ), + .cin(gnd), + .combout(\D[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~42 .lut_mask = 16'hF531; +defparam \D[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N24 +cycloneive_lcell_comb \D[2]~46 ( +// Equation(s): +// \D[2]~46_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[2]~43_combout & (\D[2]~45_combout & \D[2]~42_combout ))) + + .dataa(\D[2]~43_combout ), + .datab(\D[2]~45_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[2]~42_combout ), + .cin(gnd), + .combout(\D[2]~46_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~46 .lut_mask = 16'hF8F0; +defparam \D[2]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y14_N3 +dffeas \z80_|memory_ifc_|wait_iorqinta ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|clk_delay_|DFF_inst5~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorqinta~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N0 +cycloneive_lcell_comb \z80_|memory_ifc_|DFFE_intr_ff3~feeder ( +// Equation(s): +// \z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout = \z80_|memory_ifc_|wait_iorqinta~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|wait_iorqinta~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_intr_ff3~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|DFFE_intr_ff3~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y14_N1 +dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N8 +cycloneive_lcell_comb \z80_|control_pins_|pin_nIORQ~1 ( +// Equation(s): +// \z80_|control_pins_|pin_nIORQ~1_combout = ((!\z80_|memory_ifc_|iorq~0_combout & (!\z80_|memory_ifc_|DFFE_intr_ff3~q & !\z80_|memory_ifc_|wait_iorqinta~q ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|memory_ifc_|iorq~0_combout ), + .datab(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|wait_iorqinta~q ), + .cin(gnd), + .combout(\z80_|control_pins_|pin_nIORQ~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|control_pins_|pin_nIORQ~1 .lut_mask = 16'h0F1F; +defparam \z80_|control_pins_|pin_nIORQ~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N8 +cycloneive_lcell_comb \Equal2~0 ( +// Equation(s): +// \Equal2~0_combout = (\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|control_pins_|pin_nIORQ~1_combout ))) + + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), + .cin(gnd), + .combout(\Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~0 .lut_mask = 16'h0020; +defparam \Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N30 +cycloneive_lcell_comb \z80_|address_pins_|abus[13]~23 ( +// Equation(s): +// \z80_|address_pins_|abus[13]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[13]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[13]~23 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[13]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N18 +cycloneive_lcell_comb \ExtRamWE~0 ( +// Equation(s): +// \ExtRamWE~0_combout = (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|control_pins_|pin_nIORQ~1_combout ))) + + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), + .cin(gnd), + .combout(\ExtRamWE~0_combout ), + .cout()); +// synopsys translate_off +defparam \ExtRamWE~0 .lut_mask = 16'h4000; +defparam \ExtRamWE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N6 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h2000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y8_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|address_pins_|DFFE_apin_latch [14])) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h5000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N28 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [1]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .datab(\z80_|address_latch_|abusz [1]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N29 +dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .asdata(\z80_|address_latch_|Q [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N16 +cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( +// Equation(s): +// \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hF5F5; +defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N10 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) + + .dataa(\z80_|address_latch_|abusz [2]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hEE22; +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N11 +dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .asdata(\z80_|address_latch_|Q [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N20 +cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( +// Equation(s): +// \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [2]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[2]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N28 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [3]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [3]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y12_N29 +dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .asdata(\z80_|address_latch_|Q [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( +// Equation(s): +// \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [3]), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[3]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hCCFF; +defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N12 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [4]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .datab(\z80_|address_latch_|abusz [4]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N13 +dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .asdata(\z80_|address_latch_|Q [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N10 +cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( +// Equation(s): +// \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(\D[2]~39_combout ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [4]), .cin(gnd), - .combout(\D[2]~104_combout ), + .combout(\z80_|address_pins_|abus[4]~28_combout ), .cout()); // synopsys translate_off -defparam \D[2]~104 .lut_mask = 16'hFFF3; -defparam \D[2]~104 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF33; +defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: LCCOMB_X30_Y14_N8 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) + + .dataa(\z80_|address_latch_|abusz [5]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE22; +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N9 +dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .asdata(\z80_|address_latch_|Q [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), - .portbdataout()); + .q(\z80_|address_pins_|DFFE_apin_latch [5]), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y12_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: LCCOMB_X25_Y12_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( +// Equation(s): +// \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [5]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[5]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N18 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [6])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [6]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [6]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N19 +dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .asdata(\z80_|address_latch_|Q [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); + .q(\z80_|address_pins_|DFFE_apin_latch [6]), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y9_N0 +// Location: LCCOMB_X25_Y12_N10 +cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( +// Equation(s): +// \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [6]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[6]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N26 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) + + .dataa(\z80_|address_latch_|abusz [7]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y12_N27 +dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .asdata(\z80_|address_latch_|Q [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N12 +cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( +// Equation(s): +// \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [7]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[7]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hF5F5; +defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y5_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), @@ -49724,8 +41061,8 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -49765,7 +41102,79 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y12_N0 +// Location: FF_X24_Y19_N11 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[13]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y19_N3 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[14]~22_combout & (\ExtRamWE~0_combout & !\z80_|address_pins_|abus[13]~23_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ExtRamWE~0_combout ), + .datad(\z80_|address_pins_|abus[13]~23_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0020; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y8_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h0050; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y8_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), @@ -49781,8 +41190,8 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -49822,60 +41231,58 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N8 -cycloneive_lcell_comb \D[2]~43 ( +// Location: LCCOMB_X21_Y13_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( // Equation(s): -// \D[2]~43_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) +// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & (!\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\ExtRamWE~0_combout ), .cin(gnd), - .combout(\D[2]~43_combout ), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .cout()); // synopsys translate_off -defparam \D[2]~43 .lut_mask = 16'hB9A8; -defparam \D[2]~43 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h0800; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N6 -cycloneive_lcell_comb \D[2]~44 ( +// Location: LCCOMB_X25_Y8_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( // Equation(s): -// \D[2]~44_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~43_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout )) # (!\D[2]~43_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~43_combout )))) +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])) - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\D[2]~43_combout ), + .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), .cin(gnd), - .combout(\D[2]~44_combout ), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), .cout()); // synopsys translate_off -defparam \D[2]~44 .lut_mask = 16'hBBC0; -defparam \D[2]~44 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00A0; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y17_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(vcc), +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -49884,39 +41291,1006 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y28_N0 +// Location: FF_X25_Y19_N15 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y19_N19 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y8_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hAF0F; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y3_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N10 +cycloneive_lcell_comb \D[2]~50 ( +// Equation(s): +// \D[2]~50_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), + .cin(gnd), + .combout(\D[2]~50_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~50 .lut_mask = 16'hF838; +defparam \D[2]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N26 +cycloneive_lcell_comb \D[2]~51 ( +// Equation(s): +// \D[2]~51_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~50_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~50_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )) # (!\D[2]~50_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\D[2]~50_combout ), + .cin(gnd), + .combout(\D[2]~51_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~51 .lut_mask = 16'hEE30; +defparam \D[2]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N24 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (!\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h1000; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G15 +cycloneive_clkctrl \CLOCK_50~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\CLOCK_50~inputclkctrl_outclk )); +// synopsys translate_off +defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; +defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N30 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N8 +cycloneive_lcell_comb \ula_|video_|vram_address~0 ( +// Equation(s): +// \ula_|video_|vram_address~0_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|vram_address~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address~0 .lut_mask = 16'h1040; +defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N25 +dffeas \ula_|video_|vram_address[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N30 +cycloneive_lcell_comb \ula_|video_|vram_address[1]~feeder ( +// Equation(s): +// \ula_|video_|vram_address[1]~feeder_combout = \ula_|video_|vga_hc [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [5]), + .cin(gnd), + .combout(\ula_|video_|vram_address[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vram_address[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N31 +dffeas \ula_|video_|vram_address[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N4 +cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( +// Equation(s): +// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|video_|vram_address[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; +defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N5 +dffeas \ula_|video_|vram_address[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[2]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N22 +cycloneive_lcell_comb \ula_|video_|Add3~0 ( +// Equation(s): +// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N23 +dffeas \ula_|video_|vram_address[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N16 +cycloneive_lcell_comb \ula_|video_|Add3~1 ( +// Equation(s): +// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) + + .dataa(\ula_|video_|vga_hc [6]), + .datab(\ula_|video_|vga_hc [7]), + .datac(gnd), + .datad(\ula_|video_|vga_hc [8]), + .cin(gnd), + .combout(\ula_|video_|Add3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~1 .lut_mask = 16'h8877; +defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N17 +dffeas \ula_|video_|vram_address[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N8 +cycloneive_lcell_comb \ula_|video_|Add4~0 ( +// Equation(s): +// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) +// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add4~0_combout ), + .cout(\ula_|video_|Add4~1 )); +// synopsys translate_off +defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; +defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N10 +cycloneive_lcell_comb \ula_|video_|Add4~2 ( +// Equation(s): +// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) +// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) + + .dataa(\ula_|video_|vga_vc [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~1 ), + .combout(\ula_|video_|Add4~2_combout ), + .cout(\ula_|video_|Add4~3 )); +// synopsys translate_off +defparam \ula_|video_|Add4~2 .lut_mask = 16'hA505; +defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N12 +cycloneive_lcell_comb \ula_|video_|Add4~4 ( +// Equation(s): +// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) +// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) + + .dataa(\ula_|video_|vga_vc [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~3 ), + .combout(\ula_|video_|Add4~4_combout ), + .cout(\ula_|video_|Add4~5 )); +// synopsys translate_off +defparam \ula_|video_|Add4~4 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N14 +cycloneive_lcell_comb \ula_|video_|Add4~6 ( +// Equation(s): +// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) +// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [4]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~5 ), + .combout(\ula_|video_|Add4~6_combout ), + .cout(\ula_|video_|Add4~7 )); +// synopsys translate_off +defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y29_N15 +dffeas \ula_|video_|vram_address[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N16 +cycloneive_lcell_comb \ula_|video_|Add4~8 ( +// Equation(s): +// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) +// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) + + .dataa(\ula_|video_|vga_vc [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~7 ), + .combout(\ula_|video_|Add4~8_combout ), + .cout(\ula_|video_|Add4~9 )); +// synopsys translate_off +defparam \ula_|video_|Add4~8 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y29_N17 +dffeas \ula_|video_|vram_address[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N18 +cycloneive_lcell_comb \ula_|video_|Add4~10 ( +// Equation(s): +// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) +// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [6]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~9 ), + .combout(\ula_|video_|Add4~10_combout ), + .cout(\ula_|video_|Add4~11 )); +// synopsys translate_off +defparam \ula_|video_|Add4~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y29_N19 +dffeas \ula_|video_|vram_address[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N20 +cycloneive_lcell_comb \ula_|video_|Add4~12 ( +// Equation(s): +// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) +// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~11 ), + .combout(\ula_|video_|Add4~12_combout ), + .cout(\ula_|video_|Add4~13 )); +// synopsys translate_off +defparam \ula_|video_|Add4~12 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N28 +cycloneive_lcell_comb \ula_|video_|Selector6~0 ( +// Equation(s): +// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~12_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~0_combout )) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(gnd), + .datac(\ula_|video_|Add4~0_combout ), + .datad(\ula_|video_|Add4~12_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector6~0 .lut_mask = 16'hFA50; +defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N2 +cycloneive_lcell_comb \ula_|video_|vram_address[8]~1 ( +// Equation(s): +// \ula_|video_|vram_address[8]~1_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|vram_address[8]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[8]~1 .lut_mask = 16'h1040; +defparam \ula_|video_|vram_address[8]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y29_N29 +dffeas \ula_|video_|vram_address[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[8]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N22 +cycloneive_lcell_comb \ula_|video_|Add4~14 ( +// Equation(s): +// \ula_|video_|Add4~14_combout = \ula_|video_|vga_vc [8] $ (!\ula_|video_|Add4~13 ) + + .dataa(\ula_|video_|vga_vc [8]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|video_|Add4~13 ), + .combout(\ula_|video_|Add4~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add4~14 .lut_mask = 16'hA5A5; +defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N6 +cycloneive_lcell_comb \ula_|video_|Selector5~0 ( +// Equation(s): +// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(gnd), + .datac(\ula_|video_|Add4~14_combout ), + .datad(\ula_|video_|Add4~2_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector5~0 .lut_mask = 16'hF5A0; +defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y29_N7 +dffeas \ula_|video_|vram_address[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[8]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N28 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( +// Equation(s): +// \ula_|video_|vram_address[10]~2_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h1040; +defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N18 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( +// Equation(s): +// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) + + .dataa(\ula_|video_|vram_address[10]~2_combout ), + .datab(\ula_|video_|Add4~4_combout ), + .datac(\ula_|video_|vram_address [10]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'hD850; +defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N19 +dffeas \ula_|video_|vram_address[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[10]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N24 +cycloneive_lcell_comb \ula_|video_|Selector3~0 ( +// Equation(s): +// \ula_|video_|Selector3~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|Add4~12_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFF0; +defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y29_N25 +dffeas \ula_|video_|vram_address[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[8]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N2 +cycloneive_lcell_comb \ula_|video_|Selector2~0 ( +// Equation(s): +// \ula_|video_|Selector2~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~14_combout ) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(gnd), + .datac(\ula_|video_|Add4~14_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|video_|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFAFA; +defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y29_N3 +dffeas \ula_|video_|vram_address[12] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[8]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[12] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X22_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N28 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~23_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~23_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y19_N29 +dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N20 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|address_reg_a [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y19_N21 +dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N0 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\z80_|address_pins_|abus[14]~22_combout & (!\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~23_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h2000; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y23_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), @@ -49926,14 +42300,14 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -49989,97 +42363,83 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N12 -cycloneive_lcell_comb \D[2]~40 ( -// Equation(s): -// \D[2]~40_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .cin(gnd), - .combout(\D[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~40 .lut_mask = 16'hEA62; -defparam \D[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y31_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), +// Location: M9K_X33_Y20_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); // synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; // synopsys translate_on -// Location: M9K_X33_Y17_N0 +// Location: LCCOMB_X25_Y19_N22 +cycloneive_lcell_comb \D[2]~47 ( +// Equation(s): +// \D[2]~47_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\D[2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~47 .lut_mask = 16'hE6A2; +defparam \D[2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y32_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( .portawe(vcc), .portare(vcc), @@ -50089,14 +42449,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -50137,113 +42497,148 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N16 -cycloneive_lcell_comb \D[2]~41 ( +// Location: LCCOMB_X25_Y19_N24 +cycloneive_lcell_comb \D[2]~48 ( // Equation(s): -// \D[2]~41_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout $ (\D[2]~40_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout & ((!\D[2]~40_combout )))) +// \D[2]~48_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout $ ((\D[2]~47_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[2]~47_combout & +// \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\D[2]~40_combout ), + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\D[2]~47_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), .cin(gnd), - .combout(\D[2]~41_combout ), + .combout(\D[2]~48_combout ), .cout()); // synopsys translate_off -defparam \D[2]~41 .lut_mask = 16'h0AE4; -defparam \D[2]~41 .sum_lutc_input = "datac"; +defparam \D[2]~48 .lut_mask = 16'h4B48; +defparam \D[2]~48 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N30 -cycloneive_lcell_comb \D[2]~42 ( +// Location: LCCOMB_X25_Y19_N16 +cycloneive_lcell_comb \D[2]~49 ( // Equation(s): -// \D[2]~42_combout = (\D[2]~40_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout & !\D[2]~41_combout )))) # (!\D[2]~40_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~41_combout )))) +// \D[2]~49_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~47_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~47_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout & !\D[2]~48_combout )) # (!\D[2]~47_combout & ((\D[2]~48_combout ))))) - .dataa(\D[2]~40_combout ), + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datad(\D[2]~41_combout ), + .datac(\D[2]~47_combout ), + .datad(\D[2]~48_combout ), .cin(gnd), - .combout(\D[2]~42_combout ), + .combout(\D[2]~49_combout ), .cout()); // synopsys translate_off -defparam \D[2]~42 .lut_mask = 16'h99A8; -defparam \D[2]~42 .sum_lutc_input = "datac"; +defparam \D[2]~49 .lut_mask = 16'hC3E0; +defparam \D[2]~49 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N0 -cycloneive_lcell_comb \D[2]~105 ( +// Location: LCCOMB_X25_Y19_N6 +cycloneive_lcell_comb \D[2]~119 ( // Equation(s): -// \D[2]~105_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[2]~44_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[2]~42_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[2]~44_combout )))) +// \D[2]~119_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[2]~51_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[2]~49_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[2]~51_combout )))) - .dataa(\D[2]~44_combout ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[2]~42_combout ), + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\D[2]~51_combout ), + .datad(\D[2]~49_combout ), .cin(gnd), - .combout(\D[2]~105_combout ), + .combout(\D[2]~119_combout ), .cout()); // synopsys translate_off -defparam \D[2]~105 .lut_mask = 16'hBA8A; -defparam \D[2]~105 .sum_lutc_input = "datac"; +defparam \D[2]~119 .lut_mask = 16'hF4B0; +defparam \D[2]~119 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N28 -cycloneive_lcell_comb \D[2]~45 ( +// Location: LCCOMB_X24_Y19_N20 +cycloneive_lcell_comb \D[2]~52 ( // Equation(s): -// \D[2]~45_combout = ((\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout )))) # (!\Equal2~1_combout ) +// \D[2]~52_combout = ((\Equal2~0_combout & (\D[2]~46_combout )) # (!\Equal2~0_combout & ((\D[2]~119_combout )))) # (!\Equal2~1_combout ) - .dataa(\Equal2~0_combout ), + .dataa(\D[2]~46_combout ), .datab(\Equal2~1_combout ), - .datac(\D[2]~104_combout ), - .datad(\D[2]~105_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[2]~119_combout ), .cin(gnd), - .combout(\D[2]~45_combout ), + .combout(\D[2]~52_combout ), .cout()); // synopsys translate_off -defparam \D[2]~45 .lut_mask = 16'hF7B3; -defparam \D[2]~45 .sum_lutc_input = "datac"; +defparam \D[2]~52 .lut_mask = 16'hBFB3; +defparam \D[2]~52 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N30 -cycloneive_lcell_comb \D[2]~46 ( +// Location: LCCOMB_X24_Y19_N26 +cycloneive_lcell_comb \D[2]~53 ( // Equation(s): -// \D[2]~46_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [2] & ((\D[2]~45_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[2]~45_combout ) # (!\Equal2~1_combout )))) +// \D[2]~53_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [2] & \D[2]~52_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[2]~52_combout )) # (!\Equal2~1_combout ))) - .dataa(\z80_|data_pins_|dout [2]), + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[2]~45_combout ), + .datac(\z80_|data_pins_|dout [2]), + .datad(\D[2]~52_combout ), .cin(gnd), - .combout(\D[2]~46_combout ), + .combout(\D[2]~53_combout ), .cout()); // synopsys translate_off -defparam \D[2]~46 .lut_mask = 16'hAF03; -defparam \D[2]~46 .sum_lutc_input = "datac"; +defparam \D[2]~53 .lut_mask = 16'hF511; +defparam \D[2]~53 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N2 +// Location: LCCOMB_X29_Y12_N16 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[2]~13_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[2]~46_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[2]~46_combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|bus_control_|db[2]~13_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\D[2]~53_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|bus_control_|db[2]~13_combout & (\D[2]~53_combout +// & ((\z80_|pin_control_|bus_db_pin_re~combout )))) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\D[2]~46_combout ), - .datad(\z80_|bus_control_|db[2]~13_combout ), + .dataa(\z80_|bus_control_|db[2]~13_combout ), + .datab(\D[2]~53_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hECA0; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y12_N3 +// Location: LCCOMB_X32_Y12_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|execute_|fIORead~3_combout & ((\z80_|sequencer_|DFFE_T3_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|execute_|fIORead~3_combout & +// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|execute_|fIORead~3_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hA0EC; +defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N16 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .datac(\z80_|execute_|fMRead~36_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEC; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N17 dffeas \z80_|data_pins_|dout[2] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), @@ -50262,44 +42657,95 @@ defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N18 +// Location: LCCOMB_X29_Y12_N0 cycloneive_lcell_comb \z80_|bus_control_|db[2]~12 ( // Equation(s): -// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) +// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - .dataa(gnd), - .datab(\z80_|alu_control_|db[2]~29_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(\z80_|alu_control_|db[2]~30_combout ), + .datad(gnd), .cin(gnd), .combout(\z80_|bus_control_|db[2]~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hCF00; +defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hC4C4; defparam \z80_|bus_control_|db[2]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N12 +// Location: LCCOMB_X29_Y12_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( +// Equation(s): +// \z80_|bus_control_|db[0]~6_combout = ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (\z80_|execute_|ctl_bus_db_oe~combout )) # (!\z80_|execute_|ctl_bus_db_oe~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFFF5; +defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N10 cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( // Equation(s): // \z80_|bus_control_|db[2]~13_combout = ((\z80_|bus_control_|db[2]~12_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) .dataa(\z80_|data_pins_|dout [2]), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~combout ), - .datad(\z80_|bus_control_|db[2]~12_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|bus_control_|db[2]~12_combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[2]~13_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hBF33; +defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hB0FF; defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y12_N13 +// Location: LCCOMB_X29_Y13_N8 +cycloneive_lcell_comb \z80_|ir_|opcode[2]~feeder ( +// Equation(s): +// \z80_|ir_|opcode[2]~feeder_combout = \z80_|bus_control_|db[2]~13_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[2]~13_combout ), + .cin(gnd), + .combout(\z80_|ir_|opcode[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|ir_|opcode[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_ir_we~5_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hDDD5; +defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N9 dffeas \z80_|ir_|opcode[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[2]~13_combout ), + .d(\z80_|ir_|opcode[2]~feeder_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -50315,662 +42761,1129 @@ defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y16_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( +// Location: LCCOMB_X39_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( // Equation(s): -// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) +// \z80_|execute_|ctl_mRead~34_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .lut_mask = 16'h1500; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h2A22; +defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hFF5F; +defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~13 ( +// Equation(s): +// \z80_|alu_control_|db[6]~13_combout = (\z80_|execute_|ctl_reg_out_lo~8_combout ) # ((\z80_|alu_control_|db[6]~12_combout ) # (\z80_|execute_|ctl_sw_1d~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datab(\z80_|alu_control_|db[6]~12_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~13 .lut_mask = 16'hFEFE; +defparam \z80_|alu_control_|db[6]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( +// Equation(s): +// \z80_|alu_control_|db[6]~21_combout = (\z80_|alu_control_|out[6]~2_combout & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_control_|out[6]~2_combout & +// (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_control_|out[6]~2_combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'hF3A2; +defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( +// Equation(s): +// \z80_|alu_control_|db[6]~22_combout = (\z80_|alu_control_|db[6]~21_combout & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) + + .dataa(\z80_|alu_control_|db[6]~21_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_|db[6]~22_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'hA2A2; +defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[6]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[6]~0_combout = (\z80_|reg_file_|gdfx_temp0[6]~80_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[6]~0 .lut_mask = 16'hCCEC; +defparam \z80_|reg_file_|db_lo_ds[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N2 +cycloneive_lcell_comb \z80_|sw1_|db_down[6]~1 ( +// Equation(s): +// \z80_|sw1_|db_down[6]~1_combout = ((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) + + .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), + .datab(gnd), + .datac(\z80_|bus_control_|db[6]~9_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[6]~1 .lut_mask = 16'h55F5; +defparam \z80_|sw1_|db_down[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N20 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~23 ( +// Equation(s): +// \z80_|alu_control_|db[6]~23_combout = ((\z80_|alu_control_|db[6]~22_combout & (\z80_|reg_file_|db_lo_ds[6]~0_combout & \z80_|sw1_|db_down[6]~1_combout ))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_control_|db[6]~13_combout ), + .datab(\z80_|alu_control_|db[6]~22_combout ), + .datac(\z80_|reg_file_|db_lo_ds[6]~0_combout ), + .datad(\z80_|sw1_|db_down[6]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~23 .lut_mask = 16'hD555; +defparam \z80_|alu_control_|db[6]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N22 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( +// Equation(s): +// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~23_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(gnd), + .datad(\z80_|alu_control_|db[6]~23_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hCC44; +defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y17_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: M9K_X22_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N2 +cycloneive_lcell_comb \D[6]~103 ( +// Equation(s): +// \D[6]~103_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .cin(gnd), + .combout(\D[6]~103_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~103 .lut_mask = 16'hEA4A; +defparam \D[6]~103 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N30 +cycloneive_lcell_comb \D[6]~104 ( +// Equation(s): +// \D[6]~104_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~103_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~103_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )) # (!\D[6]~103_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\D[6]~103_combout ), + .cin(gnd), + .combout(\D[6]~104_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~104 .lut_mask = 16'hEE30; +defparam \D[6]~104 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X22_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y30_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N14 +cycloneive_lcell_comb \D[6]~100 ( +// Equation(s): +// \D[6]~100_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\z80_|address_pins_|abus[14]~22_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\z80_|address_pins_|abus[14]~22_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .cin(gnd), + .combout(\D[6]~100_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~100 .lut_mask = 16'hBCB0; +defparam \D[6]~100 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y22_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N12 +cycloneive_lcell_comb \D[6]~101 ( +// Equation(s): +// \D[6]~101_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ ((\D[6]~100_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[6]~100_combout & +// \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datac(\D[6]~100_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .cin(gnd), + .combout(\D[6]~101_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~101 .lut_mask = 16'h2D28; +defparam \D[6]~101 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N0 +cycloneive_lcell_comb \D[6]~102 ( +// Equation(s): +// \D[6]~102_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~100_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~100_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~101_combout )) # (!\D[6]~100_combout & ((\D[6]~101_combout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[6]~100_combout ), + .datad(\D[6]~101_combout ), + .cin(gnd), + .combout(\D[6]~102_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~102 .lut_mask = 16'hC3E0; +defparam \D[6]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N8 +cycloneive_lcell_comb \D[6]~127 ( +// Equation(s): +// \D[6]~127_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[6]~104_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[6]~102_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[6]~104_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\D[6]~104_combout ), + .datad(\D[6]~102_combout ), + .cin(gnd), + .combout(\D[6]~127_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~127 .lut_mask = 16'hF4B0; +defparam \D[6]~127 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y34_N8 +cycloneive_io_ibuf \raw_loader_in~input ( + .i(raw_loader_in), + .ibar(gnd), + .o(\raw_loader_in~input_o )); +// synopsys translate_off +defparam \raw_loader_in~input .bus_hold = "false"; +defparam \raw_loader_in~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N28 +cycloneive_lcell_comb \D[6]~99 ( +// Equation(s): +// \D[6]~99_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\raw_loader_in~input_o ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~1_combout ), + .combout(\D[6]~99_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00F0; -defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; +defparam \D[6]~99 .lut_mask = 16'hFFCF; +defparam \D[6]~99 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( +// Location: LCCOMB_X23_Y19_N10 +cycloneive_lcell_comb \D[6]~114 ( // Equation(s): -// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) +// \D[6]~114_combout = ((\Equal2~0_combout & ((\D[6]~99_combout ))) # (!\Equal2~0_combout & (\D[6]~127_combout ))) # (!\Equal2~1_combout ) - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), + .dataa(\Equal2~0_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[6]~127_combout ), + .datad(\D[6]~99_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal43~0_combout ), + .combout(\D[6]~114_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; +defparam \D[6]~114 .lut_mask = 16'hFB73; +defparam \D[6]~114 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N24 -cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( +// Location: LCCOMB_X23_Y19_N12 +cycloneive_lcell_comb \D[6]~115 ( // Equation(s): -// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal43~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal36~0_combout ))) +// \D[6]~115_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [6] & \D[6]~114_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[6]~114_combout )) # (!\Equal2~1_combout ))) - .dataa(\z80_|pla_decode_|Equal43~0_combout ), - .datab(\z80_|pla_decode_|Equal3~2_combout ), - .datac(\z80_|pla_decode_|Equal79~0_combout ), - .datad(\z80_|pla_decode_|Equal36~0_combout ), + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\Equal2~1_combout ), + .datac(\z80_|data_pins_|dout [6]), + .datad(\D[6]~114_combout ), .cin(gnd), - .combout(\z80_|interrupts_|test1~2_combout ), + .combout(\D[6]~115_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; -defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; +defparam \D[6]~115 .lut_mask = 16'hF511; +defparam \D[6]~115 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y15_N26 -cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( +// Location: LCCOMB_X28_Y12_N14 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( // Equation(s): -// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|interrupts_|test1~2_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\D[6]~115_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[6]~9_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[6]~115_combout & +// (((\z80_|bus_control_|db[6]~9_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|interrupts_|test1~2_combout ), + .dataa(\D[6]~115_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|bus_control_|db[6]~9_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), .cin(gnd), - .combout(\z80_|interrupts_|test1~3_combout ), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h5545; -defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y15_N13 -dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), +// Location: FF_X28_Y12_N15 +dffeas \z80_|data_pins_|dout[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N14 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( +// Equation(s): +// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[6]~8_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|data_pins_|dout [6]), + .datad(\z80_|bus_control_|db[0]~6_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'hA2FF; +defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N3 +dffeas \z80_|ir_|opcode[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[6]~9_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~0_combout = (\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6])) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h0A00; +defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal38~2_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal38~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N0 +cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Equation(s): +// \z80_|interrupts_|iff1~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|interrupts_|iff1~q ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal79~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hE4CC; +defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N4 +cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( +// Equation(s): +// \z80_|interrupts_|iff1~1_combout = (\z80_|pla_decode_|Equal38~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|interrupts_|iff1~0_combout )))) # +// (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|iff1~0_combout )) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|interrupts_|iff1~0_combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hE4CC; +defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N24 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|interrupts_|DFFE_inst44~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFF3; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N5 +dffeas \z80_|interrupts_|iff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|iff1~1_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|iff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|iff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y27_N8 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (\ula_|video_|Equal2~2_combout & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & (!\ula_|video_|vga_hc [7] & \z80_|interrupts_|iff1~q ))) + + .dataa(\ula_|video_|Equal2~2_combout ), + .datab(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), + .datac(\ula_|video_|vga_hc [7]), + .datad(\z80_|interrupts_|iff1~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0800; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y27_N9 +dffeas \z80_|interrupts_|int_armed ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|int_armed~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; +defparam \z80_|interrupts_|int_armed .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N25 +dffeas \z80_|interrupts_|DFFE_inst44 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|interrupts_|int_armed~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), .ena(\z80_|interrupts_|test1~3_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .q(\z80_|interrupts_|DFFE_inst44~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; +defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y15_N2 -cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( +// Location: LCCOMB_X30_Y11_N22 +cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( // Equation(s): -// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|interrupts_|DFFE_inst44~q ))) +// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & \z80_|decode_state_|in_halt~q )) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0100; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y15_N3 -dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N20 -cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( -// Equation(s): -// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q & !\z80_|clk_delay_|DFF_inst5~q ) - - .dataa(gnd), - .datab(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), .datac(gnd), - .datad(\z80_|clk_delay_|DFF_inst5~q ), + .datad(\z80_|decode_state_|in_halt~q ), .cin(gnd), - .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), + .combout(\z80_|decode_state_|in_halt~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0033; -defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h1100; +defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N13 -dffeas \z80_|sequencer_|DFFE_T1_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|ena_M~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T1_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N4 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0050; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N5 -dffeas \z80_|sequencer_|DFFE_T2_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T2_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N10 -cycloneive_lcell_comb \z80_|resets_|x3 ( -// Equation(s): -// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(\z80_|resets_|x1~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|resets_|x3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|x3 .lut_mask = 16'hF0FA; -defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N11 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|x3~combout ), - .asdata(vcc), - .clrn(\z80_|fpga_reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; -// synopsys translate_on - -// Location: CLKCTRL_G7 -cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: FF_X32_Y17_N21 -dffeas \z80_|sequencer_|DFFE_M1_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M1_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N10 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h22A0; -defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N11 -dffeas \z80_|sequencer_|DFFE_M2_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M2_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~3 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~3_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~3 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~11 ( -// Equation(s): -// \z80_|execute_|nextM~11_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ctl_mWrite~3_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~11 .lut_mask = 16'h5557; -defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~8 ( -// Equation(s): -// \z80_|execute_|nextM~8_combout = (\z80_|alu_control_|flags_cond_true~q & (((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) # (!\z80_|alu_control_|flags_cond_true~q & ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout -// ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~8 .lut_mask = 16'h44F4; -defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~9 ( -// Equation(s): -// \z80_|execute_|nextM~9_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # (\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~9 .lut_mask = 16'h8880; -defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|nextM~10 ( -// Equation(s): -// \z80_|execute_|nextM~10_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datab(\z80_|execute_|nextM~9_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~12 ( -// Equation(s): -// \z80_|execute_|nextM~12_combout = ((\z80_|execute_|nextM~8_combout ) # ((\z80_|execute_|nextM~10_combout ) # (\z80_|execute_|ctl_alu_op_low~32_combout ))) # (!\z80_|execute_|nextM~11_combout ) - - .dataa(\z80_|execute_|nextM~11_combout ), - .datab(\z80_|execute_|nextM~8_combout ), - .datac(\z80_|execute_|nextM~10_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|nextM~15 ( -// Equation(s): -// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|fMRead~10_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|fMRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~15 .lut_mask = 16'h80A0; -defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|nextM~6 ( -// Equation(s): -// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|ixy_d~17_combout ) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|nextM~3_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~6 .lut_mask = 16'hDF5F; -defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~7 ( -// Equation(s): -// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ixy_d~8_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|execute_|nextM~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|nextM~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~7 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~13 ( -// Equation(s): -// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~12_combout ) # ((\z80_|execute_|nextM~15_combout ) # (\z80_|execute_|nextM~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|nextM~12_combout ), - .datac(\z80_|execute_|nextM~15_combout ), - .datad(\z80_|execute_|nextM~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~39 ( -// Equation(s): -// \z80_|execute_|setM1~39_combout = (!\z80_|execute_|ctl_mWrite~5_combout & \z80_|execute_|setM1~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|setM1~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0F00; -defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~5 ( -// Equation(s): -// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~45_combout ) # (!\z80_|execute_|nextM~2_combout )) # (!\z80_|execute_|setM1~39_combout ))) - - .dataa(\z80_|execute_|setM1~39_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|setM1~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~5 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|nextM~14 ( -// Equation(s): -// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~13_combout ) # (((\z80_|execute_|nextM~5_combout ) # (!\z80_|execute_|ctl_mRead~30_combout )) # (!\z80_|execute_|ctl_mWrite~13_combout )) - - .dataa(\z80_|execute_|nextM~13_combout ), - .datab(\z80_|execute_|ctl_mWrite~13_combout ), - .datac(\z80_|execute_|ctl_mRead~30_combout ), - .datad(\z80_|execute_|nextM~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~14 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N14 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00C0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N15 -dffeas \z80_|sequencer_|DFFE_T4_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T4_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N18 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N19 -dffeas \z80_|sequencer_|DFFE_T5_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T5_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N26 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00C0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N27 -dffeas \z80_|sequencer_|T6 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|T6~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|T6 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~13 ( -// Equation(s): -// \z80_|execute_|setM1~13_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|pla_decode_|Equal33~0_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal21~2_combout )))) # (!\z80_|pla_decode_|Equal13~0_combout & -// (((!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal21~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal21~2_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~13 .lut_mask = 16'h153F; -defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N4 +// Location: LCCOMB_X34_Y11_N16 cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( // Equation(s): -// \z80_|pla_decode_|Equal77~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) +// \z80_|pla_decode_|Equal77~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal21~0_combout ))) .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), .cin(gnd), .combout(\z80_|pla_decode_|Equal77~1_combout ), .cout()); @@ -50979,660 +43892,24 @@ defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~12 ( -// Equation(s): -// \z80_|execute_|setM1~12_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|pla_decode_|Equal2~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal77~1_combout ), - .datab(\z80_|execute_|ctl_alu_oe~3_combout ), - .datac(\z80_|pla_decode_|Equal1~6_combout ), - .datad(\z80_|pla_decode_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~14 ( -// Equation(s): -// \z80_|execute_|setM1~14_combout = (\z80_|execute_|setM1~13_combout & (\z80_|interrupts_|test1~2_combout & \z80_|execute_|setM1~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|setM1~13_combout ), - .datac(\z80_|interrupts_|test1~2_combout ), - .datad(\z80_|execute_|setM1~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~14 .lut_mask = 16'hC000; -defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~41 ( -// Equation(s): -// \z80_|execute_|setM1~41_combout = (!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_ir_we~10_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~41 .lut_mask = 16'h0005; -defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~42 ( -// Equation(s): -// \z80_|execute_|setM1~42_combout = (!\z80_|pla_decode_|Equal38~2_combout & (!\z80_|pla_decode_|Equal37~0_combout & (!\z80_|pla_decode_|Equal47~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0100; -defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~43 ( -// Equation(s): -// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~41_combout & (!\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|setM1~42_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|setM1~41_combout ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|execute_|setM1~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0400; -defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~44 ( -// Equation(s): -// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (\z80_|execute_|setM1~40_combout & ((!\z80_|pla_decode_|Equal2~1_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|execute_|setM1~43_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|pla_decode_|Equal2~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~44 .lut_mask = 16'h20A0; -defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~50 ( -// Equation(s): -// \z80_|execute_|setM1~50_combout = (\z80_|execute_|setM1~46_combout & (\z80_|execute_|setM1~14_combout & (\z80_|execute_|setM1~44_combout & \z80_|execute_|setM1~49_combout ))) - - .dataa(\z80_|execute_|setM1~46_combout ), - .datab(\z80_|execute_|setM1~14_combout ), - .datac(\z80_|execute_|setM1~44_combout ), - .datad(\z80_|execute_|setM1~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~50 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~51 ( -// Equation(s): -// \z80_|execute_|setM1~51_combout = (\z80_|sequencer_|T6~q & (((\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~39_combout )) # (!\z80_|execute_|setM1~40_combout ))) # (!\z80_|sequencer_|T6~q & (\z80_|execute_|setM1~50_combout & -// ((\z80_|execute_|setM1~39_combout )))) - - .dataa(\z80_|sequencer_|T6~q ), - .datab(\z80_|execute_|setM1~50_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|execute_|setM1~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~51 .lut_mask = 16'hCE0A; -defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~6 ( -// Equation(s): -// \z80_|execute_|setM1~6_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|sequencer_|M5~q & (\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & -// \z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~6 .lut_mask = 16'hD5C0; -defparam \z80_|execute_|setM1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~7 ( -// Equation(s): -// \z80_|execute_|setM1~7_combout = ((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|setM1~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~7 .lut_mask = 16'hF333; -defparam \z80_|execute_|setM1~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~8 ( -// Equation(s): -// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|fMWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~8 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~9 ( -// Equation(s): -// \z80_|execute_|setM1~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~9 .lut_mask = 16'hF1F0; -defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~10 ( -// Equation(s): -// \z80_|execute_|setM1~10_combout = ((\z80_|execute_|setM1~8_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout & \z80_|execute_|setM1~9_combout ))) # (!\z80_|execute_|nextM~2_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|setM1~8_combout ), - .datad(\z80_|execute_|setM1~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~11 ( -// Equation(s): -// \z80_|execute_|setM1~11_combout = (\z80_|execute_|setM1~7_combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|setM1~10_combout )) # (!\z80_|reg_control_|reg_sel_pc~3_combout )) - - .dataa(\z80_|execute_|setM1~7_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|setM1~10_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~11 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~17 ( -// Equation(s): -// \z80_|execute_|setM1~17_combout = ((\z80_|execute_|setM1~11_combout ) # ((!\z80_|execute_|setM1~14_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|setM1~16_combout ) - - .dataa(\z80_|execute_|setM1~16_combout ), - .datab(\z80_|execute_|setM1~14_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~17 .lut_mask = 16'hFF75; -defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~31 ( -// Equation(s): -// \z80_|execute_|setM1~31_combout = (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout & \z80_|execute_|ctl_mRead~18_combout )))) # (!\z80_|pla_decode_|Equal35~0_combout & -// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|execute_|ctl_mRead~18_combout )))) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~31 .lut_mask = 16'hECA0; -defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~28 ( -// Equation(s): -// \z80_|execute_|setM1~28_combout = ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~30 ( -// Equation(s): -// \z80_|execute_|setM1~30_combout = (((\z80_|execute_|ctl_state_alu~6_combout & \z80_|execute_|setM1~28_combout )) # (!\z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~54_combout ) - - .dataa(\z80_|execute_|setM1~54_combout ), - .datab(\z80_|execute_|setM1~29_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|setM1~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~30 .lut_mask = 16'hF777; -defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~32 ( -// Equation(s): -// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|setM1~9_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|setM1~9_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~32 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~33 ( -// Equation(s): -// \z80_|execute_|setM1~33_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~30_combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|setM1~32_combout ))) - - .dataa(\z80_|execute_|setM1~31_combout ), - .datab(\z80_|execute_|setM1~30_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|setM1~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~25 ( -// Equation(s): -// \z80_|execute_|setM1~25_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~25 .lut_mask = 16'hAF0F; -defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~26 ( -// Equation(s): -// \z80_|execute_|setM1~26_combout = ((\z80_|execute_|ctl_mRead~13_combout ) # ((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~26 .lut_mask = 16'hF7F5; -defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~24 ( -// Equation(s): -// \z80_|execute_|setM1~24_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_mRead~12_combout ))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & ((!\z80_|alu_control_|flags_cond_true~q )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|alu_control_|flags_cond_true~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~24 .lut_mask = 16'h0ACE; -defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~27 ( -// Equation(s): -// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|setM1~25_combout ) # (\z80_|execute_|setM1~26_combout )))) - - .dataa(\z80_|execute_|setM1~25_combout ), - .datab(\z80_|execute_|setM1~26_combout ), - .datac(\z80_|execute_|setM1~24_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~27 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~22 ( -// Equation(s): -// \z80_|execute_|setM1~22_combout = (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|execute_|fMWrite~9_combout & (!\z80_|execute_|ctl_mRead~8_combout & \z80_|execute_|fMWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|fMWrite~9_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~22 .lut_mask = 16'h0400; -defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~21 ( -// Equation(s): -// \z80_|execute_|setM1~21_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|decode_state_|DFFE_instNonRep~q ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~21 .lut_mask = 16'hF1F0; -defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~53 ( -// Equation(s): -// \z80_|execute_|setM1~53_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|execute_|setM1~21_combout & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~21_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~53 .lut_mask = 16'hC888; -defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~23 ( -// Equation(s): -// \z80_|execute_|setM1~23_combout = (\z80_|execute_|setM1~22_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) # (!\z80_|execute_|setM1~22_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # -// ((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) - - .dataa(\z80_|execute_|setM1~22_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|setM1~53_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~23 .lut_mask = 16'h4F44; -defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~18 ( -// Equation(s): -// \z80_|execute_|setM1~18_combout = (\z80_|execute_|ctl_mRead~11_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~18 .lut_mask = 16'h08CC; -defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~19 ( -// Equation(s): -// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~18_combout ) # ((\z80_|execute_|ixy_d~8_combout & (\z80_|pla_decode_|Equal10~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ))) - - .dataa(\z80_|execute_|setM1~18_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~19 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~20 ( -// Equation(s): -// \z80_|execute_|setM1~20_combout = ((\z80_|execute_|setM1~19_combout ) # ((\z80_|execute_|ctl_iorw~11_combout & \z80_|execute_|ctl_mWrite~3_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datad(\z80_|execute_|setM1~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~20 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~34 ( -// Equation(s): -// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~33_combout ) # ((\z80_|execute_|setM1~27_combout ) # ((\z80_|execute_|setM1~23_combout ) # (\z80_|execute_|setM1~20_combout ))) - - .dataa(\z80_|execute_|setM1~33_combout ), - .datab(\z80_|execute_|setM1~27_combout ), - .datac(\z80_|execute_|setM1~23_combout ), - .datad(\z80_|execute_|setM1~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~52 ( -// Equation(s): -// \z80_|execute_|setM1~52_combout = (!\z80_|execute_|setM1~17_combout & (!\z80_|execute_|setM1~34_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~51_combout )))) - - .dataa(\z80_|execute_|setM1~51_combout ), - .datab(\z80_|execute_|setM1~17_combout ), - .datac(\z80_|execute_|setM1~34_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~52 .lut_mask = 16'h0301; -defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N24 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N25 -dffeas \z80_|sequencer_|DFFE_T3_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T3_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N24 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( -// Equation(s): -// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|decode_state_|in_halt~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h0050; -defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N24 +// Location: LCCOMB_X30_Y11_N12 cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( // Equation(s): -// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|decode_state_|in_halt~q & \z80_|pla_decode_|Equal77~1_combout ))) +// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|pla_decode_|Equal77~1_combout & (!\z80_|decode_state_|in_halt~q & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|decode_state_|in_halt~0_combout ), + .dataa(\z80_|decode_state_|in_halt~0_combout ), + .datab(\z80_|pla_decode_|Equal77~1_combout ), .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|pla_decode_|Equal77~1_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), .cin(gnd), .combout(\z80_|decode_state_|in_halt~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hCECC; +defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hAEAA; defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y13_N25 +// Location: FF_X30_Y11_N13 dffeas \z80_|decode_state_|in_halt ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|decode_state_|in_halt~1_combout ), @@ -51651,434 +43928,489 @@ defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; defparam \z80_|decode_state_|in_halt .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Location: LCCOMB_X34_Y6_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_zero_oe~0_combout & (!\z80_|execute_|ctl_bus_ff_oe~1_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) +// \z80_|execute_|ctl_mRead~21_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal77~0_combout ))) .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .combout(\z80_|execute_|ctl_mRead~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0031; -defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( +// Location: LCCOMB_X34_Y6_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|pla_decode_|Equal41~2_combout ))) +// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|ctl_mRead~21_combout ) # (((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|fMWrite~0_combout )) # (!\z80_|execute_|fMRead~7_combout )) + + .dataa(\z80_|execute_|ctl_mRead~21_combout ), + .datab(\z80_|execute_|fMRead~7_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|fMWrite~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( +// Equation(s): +// \z80_|execute_|fMRead~23_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|fMRead~4_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|fMRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hA2AA; +defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( +// Equation(s): +// \z80_|execute_|fMRead~27_combout = ((\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ixy_d~4_combout & \z80_|sequencer_|DFFE_M2_ff~q ))) # (!\z80_|execute_|fMRead~26_combout ) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|fMRead~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~27 .lut_mask = 16'h20FF; +defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Equation(s): +// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|pla_decode_|Equal41~2_combout ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hFB33; +defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( +// Equation(s): +// \z80_|execute_|fMRead~29_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((\z80_|ir_|opcode [7]) # (\z80_|ir_|opcode [6])))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|fMRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC080; +defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( +// Equation(s): +// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~10_combout ) # ((\z80_|execute_|ctl_ir_we~9_combout ) # (\z80_|execute_|fMRead~29_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|fMRead~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( +// Equation(s): +// \z80_|execute_|fMRead~31_combout = (\z80_|pla_decode_|Equal33~3_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal33~3_combout & (\z80_|pla_decode_|Equal6~1_combout & +// ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Equation(s): +// \z80_|execute_|fMRead~32_combout = (\z80_|execute_|fMRead~28_combout ) # ((\z80_|execute_|fMRead~30_combout ) # ((\z80_|execute_|fMRead~31_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ))) + + .dataa(\z80_|execute_|fMRead~28_combout ), + .datab(\z80_|execute_|fMRead~30_combout ), + .datac(\z80_|execute_|fMRead~31_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~37 ( +// Equation(s): +// \z80_|execute_|fMRead~37_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_mRead~13_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~37 .lut_mask = 16'h0E00; +defparam \z80_|execute_|fMRead~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Equation(s): +// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~27_combout ) # (((\z80_|execute_|fMRead~32_combout ) # (\z80_|execute_|fMRead~37_combout )) # (!\z80_|execute_|fMRead~6_combout )) + + .dataa(\z80_|execute_|fMRead~27_combout ), + .datab(\z80_|execute_|fMRead~6_combout ), + .datac(\z80_|execute_|fMRead~32_combout ), + .datad(\z80_|execute_|fMRead~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( +// Equation(s): +// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & (\z80_|execute_|ctl_alu_oe~2_combout & +// ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~16_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ctl_mRead~16_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~24 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( +// Equation(s): +// \z80_|execute_|fMRead~25_combout = ((\z80_|execute_|fMRead~24_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~33_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|pc_inc_hold~33_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|fMRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~25 .lut_mask = 16'hFF2F; +defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( +// Equation(s): +// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_ir_we~12_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~21_combout ) # (\z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_mRead~21_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~16 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( +// Equation(s): +// \z80_|execute_|fMRead~11_combout = ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ctl_mRead~21_combout ) # (!\z80_|execute_|nextM~3_combout ))) # (!\z80_|execute_|pc_inc_hold~14_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~14_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_mRead~21_combout ), + .datad(\z80_|execute_|nextM~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Equation(s): +// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (!\z80_|execute_|ctl_mRead~2_combout & (!\z80_|pla_decode_|Equal6~1_combout & !\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datab(\z80_|execute_|ctl_mRead~2_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~12 .lut_mask = 16'h0002; +defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Equation(s): +// \z80_|execute_|fMRead~13_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|fMRead~11_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # (!\z80_|execute_|fMRead~12_combout )))) + + .dataa(\z80_|execute_|fMRead~11_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|fMRead~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~13 .lut_mask = 16'hC8CC; +defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Equation(s): +// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout ))) .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFBFA; +defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N10 +cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Equation(s): +// \z80_|execute_|fMRead~15_combout = (!\z80_|execute_|fMWrite~2_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|fMRead~14_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|fMWrite~2_combout ), .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|fMRead~14_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .combout(\z80_|execute_|fMRead~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~15 .lut_mask = 16'h3332; +defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( +// Location: LCCOMB_X34_Y6_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_bus_db_oe~5_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) +// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~15_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|fMRead~16_combout ))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|fMRead~16_combout ), + .datac(\z80_|execute_|fMRead~13_combout ), + .datad(\z80_|execute_|fMRead~15_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .combout(\z80_|execute_|fMRead~17_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFDF5; -defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~17 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( +// Location: LCCOMB_X34_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) +// \z80_|execute_|fMRead~22_combout = (((\z80_|execute_|fMRead~17_combout ) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|fMRead~21_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datab(\z80_|execute_|fMRead~21_combout ), + .datac(\z80_|execute_|fMRead~17_combout ), + .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( +// Equation(s): +// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|fMRead~23_combout ) # ((\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|fMRead~25_combout ) # (\z80_|execute_|fMRead~22_combout ))) + + .dataa(\z80_|execute_|fMRead~23_combout ), + .datab(\z80_|execute_|fMRead~33_combout ), + .datac(\z80_|execute_|fMRead~25_combout ), + .datad(\z80_|execute_|fMRead~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~36 ( +// Equation(s): +// \z80_|execute_|fMRead~36_combout = (\z80_|execute_|fMRead~34_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((\z80_|execute_|fMRead~35_combout & !\z80_|execute_|fMRead~2_combout ))) + + .dataa(\z80_|execute_|fMRead~35_combout ), + .datab(\z80_|execute_|fMRead~34_combout ), + .datac(\z80_|execute_|fMRead~2_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~36 .lut_mask = 16'hFFCE; +defparam \z80_|execute_|fMRead~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout )) .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|fMRead~36_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .combout(\z80_|pin_control_|bus_db_pin_re~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; -defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; +defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFC0; +defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Location: LCCOMB_X21_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~103 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (\z80_|execute_|ctl_bus_db_oe~4_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hAAA2; -defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( -// Equation(s): -// \z80_|bus_control_|db[0]~6_combout = (\z80_|execute_|ctl_bus_db_oe~combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) - - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFAFF; -defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~93 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~93_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~47_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~93_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~93 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[1][3]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~94 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~94_combout = (\ula_|zx_keyboard_|keys[1][3]~93_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # -// (!\ula_|zx_keyboard_|keys[1][3]~93_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[1][3]~93_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~94 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][3]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N31 -dffeas \ula_|zx_keyboard_|keys[1][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) +// \ula_|zx_keyboard_|keys[5][3]~103_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5])) .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .combout(\ula_|zx_keyboard_|keys[5][3]~103_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][3]~103 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|keys[5][3]~103 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~98 ( +// Location: LCCOMB_X20_Y10_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~20 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~98_combout = (\ula_|zx_keyboard_|keys[0][3]~96_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & -// (\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][3]~96_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) +// \ula_|zx_keyboard_|keys[5][4]~20_combout = (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) - .dataa(\ula_|zx_keyboard_|keys[0][3]~96_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .datac(\ula_|zx_keyboard_|keys[0][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~98_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~98 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[0][3]~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N1 -dffeas \ula_|zx_keyboard_|keys[0][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][3]~98_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N4 -cycloneive_lcell_comb \D[3]~65 ( -// Equation(s): -// \D[3]~65_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][3]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][3]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][3]~q ), - .cin(gnd), - .combout(\D[3]~65_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~65 .lut_mask = 16'h8CAF; -defparam \D[3]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~99 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~99_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), .datad(gnd), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~99_combout ), + .combout(\ula_|zx_keyboard_|keys[5][4]~20_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~99 .lut_mask = 16'h4040; -defparam \ula_|zx_keyboard_|keys[3][3]~99 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][4]~20 .lut_mask = 16'hC0C0; +defparam \ula_|zx_keyboard_|keys[5][4]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~100 ( +// Location: LCCOMB_X20_Y10_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~21 ( // Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~100_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[3][3]~99_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][3]~99_combout & (\ula_|zx_keyboard_|keys[3][3]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[3][3]~q )))) +// \ula_|zx_keyboard_|keys[1][4]~21_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) - .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .datab(\ula_|zx_keyboard_|keys[3][3]~99_combout ), - .datac(\ula_|zx_keyboard_|keys[3][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~100_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~100 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[3][3]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N9 -dffeas \ula_|zx_keyboard_|keys[3][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][3]~100_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'hCCDD; -defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .combout(\ula_|zx_keyboard_|keys[1][4]~21_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[1][4]~21 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[1][4]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~133 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~133_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][3]~102_combout & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|zx_keyboard_|keys[2][3]~102_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~133_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~133 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[2][3]~133 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~103 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~103_combout = (\ula_|zx_keyboard_|keys[2][3]~133_combout & (!\ula_|zx_keyboard_|keys[2][3]~101_combout )) # (!\ula_|zx_keyboard_|keys[2][3]~133_combout & ((\ula_|zx_keyboard_|keys[2][3]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[2][3]~101_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][3]~133_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~103 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[2][3]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N3 -dffeas \ula_|zx_keyboard_|keys[2][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N28 -cycloneive_lcell_comb \D[3]~66 ( -// Equation(s): -// \D[3]~66_combout = (\z80_|address_pins_|abus[11]~19_combout & (((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & -// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[3][3]~q ), - .datac(\z80_|address_pins_|abus[10]~24_combout ), - .datad(\ula_|zx_keyboard_|keys[2][3]~q ), - .cin(gnd), - .combout(\D[3]~66_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~66 .lut_mask = 16'hB0BB; -defparam \D[3]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N12 +// Location: LCCOMB_X21_Y8_N24 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) +// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|zx_keyboard_|keys[5][3]~103_combout & ((\ula_|zx_keyboard_|keys[1][4]~21_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][4]~21_combout & ((\ula_|zx_keyboard_|keys[5][3]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][3]~103_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(gnd), + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[5][3]~103_combout ), + .datac(\ula_|zx_keyboard_|keys[5][3]~q ), + .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h0808; +defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h74F0; defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y19_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~105 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~105_combout = (\ula_|zx_keyboard_|keys[5][3]~104_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[5][3]~q -// )))) # (!\ula_|zx_keyboard_|keys[5][3]~104_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][3]~104_combout ), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[5][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~105_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~105 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][3]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N23 +// Location: FF_X21_Y8_N25 dffeas \ula_|zx_keyboard_|keys[5][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][3]~105_combout ), + .d(\ula_|zx_keyboard_|keys[5][3]~104_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52094,32 +44426,49 @@ defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y19_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( +// Location: LCCOMB_X19_Y9_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~73 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|WideOr16~2_combout ))) +// \ula_|zx_keyboard_|keys[3][0]~73_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1])) - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .combout(\ula_|zx_keyboard_|keys[3][0]~73_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[3][0]~73 .lut_mask = 16'h0500; +defparam \ula_|zx_keyboard_|keys[3][0]~73 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( +// Location: LCCOMB_X19_Y10_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( // Equation(s): -// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) +// \ula_|zx_keyboard_|Selector5~0_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[3][0]~73_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]))) .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|zx_keyboard_|keys[3][0]~73_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), .cin(gnd), .combout(\ula_|zx_keyboard_|Selector5~1_combout ), .cout()); @@ -52128,96 +44477,113 @@ defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h0800; defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( +// Location: LCCOMB_X19_Y10_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~129 ( // Equation(s): -// \ula_|zx_keyboard_|Selector5~0_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5]))) +// \ula_|zx_keyboard_|keys[4][3]~129_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|Selector5~1_combout ))) - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~134 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~134_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|zx_keyboard_|Selector5~1_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|Selector5~1_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), .datab(\ula_|zx_keyboard_|Selector5~0_combout ), .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|Selector5~1_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~134_combout ), + .combout(\ula_|zx_keyboard_|keys[4][3]~129_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~134 .lut_mask = 16'hCECC; -defparam \ula_|zx_keyboard_|keys[4][3]~134 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[4][3]~129 .lut_mask = 16'hCECC; +defparam \ula_|zx_keyboard_|keys[4][3]~129 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N6 +// Location: LCCOMB_X21_Y10_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~1 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~1_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~1 .lut_mask = 16'h0030; +defparam \ula_|zx_keyboard_|WideOr16~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~105 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~105_combout = (\ula_|zx_keyboard_|WideOr16~1_combout & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) + + .dataa(\ula_|zx_keyboard_|WideOr16~1_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~105_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~105 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][3]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|zx_keyboard_|extended~q & (((\ula_|zx_keyboard_|keys[4][3]~105_combout )))) # (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~129_combout & (\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~129_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[4][3]~105_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'hEC20; +defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~130 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~130_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~130_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~130 .lut_mask = 16'hAAAE; +defparam \ula_|zx_keyboard_|keys[4][3]~130 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N2 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~107 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~106_combout )) # (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][3]~134_combout )))) +// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & ((\ula_|zx_keyboard_|keys[4][3]~106_combout & ((!\ula_|zx_keyboard_|keys[4][3]~130_combout ))) # (!\ula_|zx_keyboard_|keys[4][3]~106_combout & +// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) - .dataa(\ula_|zx_keyboard_|extended~q ), + .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), .datab(\ula_|zx_keyboard_|keys[4][3]~106_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][3]~134_combout ), + .datac(\ula_|zx_keyboard_|keys[4][3]~q ), + .datad(\ula_|zx_keyboard_|keys[4][3]~130_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[4][3]~107_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'hD888; +defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'h70F8; defparam \ula_|zx_keyboard_|keys[4][3]~107 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~135 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~135_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q ))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~135_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~135 .lut_mask = 16'hCDCC; -defparam \ula_|zx_keyboard_|keys[4][3]~135 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~108 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~108_combout = (\ula_|zx_keyboard_|keys[4][3]~107_combout & ((\ula_|zx_keyboard_|keys[0][0]~15_combout & ((!\ula_|zx_keyboard_|keys[4][3]~135_combout ))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & -// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[4][3]~107_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~107_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\ula_|zx_keyboard_|keys[4][3]~135_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~108_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~108 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][3]~108 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N23 +// Location: FF_X21_Y8_N3 dffeas \ula_|zx_keyboard_|keys[4][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][3]~108_combout ), + .d(\ula_|zx_keyboard_|keys[4][3]~107_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52233,79 +44599,257 @@ defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y19_N20 -cycloneive_lcell_comb \D[3]~67 ( +// Location: LCCOMB_X21_Y8_N12 +cycloneive_lcell_comb \D[3]~74 ( // Equation(s): -// \D[3]~67_combout = (\ula_|zx_keyboard_|keys[5][3]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][3]~q & -// (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) +// \D[3]~74_combout = (\z80_|address_pins_|abus[12]~24_combout & (((\z80_|address_pins_|abus[13]~23_combout )) # (!\ula_|zx_keyboard_|keys[5][3]~q ))) # (!\z80_|address_pins_|abus[12]~24_combout & (!\ula_|zx_keyboard_|keys[4][3]~q & +// ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) - .dataa(\ula_|zx_keyboard_|keys[5][3]~q ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), + .dataa(\z80_|address_pins_|abus[12]~24_combout ), + .datab(\ula_|zx_keyboard_|keys[5][3]~q ), + .datac(\z80_|address_pins_|abus[13]~23_combout ), + .datad(\ula_|zx_keyboard_|keys[4][3]~q ), .cin(gnd), - .combout(\D[3]~67_combout ), + .combout(\D[3]~74_combout ), .cout()); // synopsys translate_off -defparam \D[3]~67 .lut_mask = 16'hDD0D; -defparam \D[3]~67 .sum_lutc_input = "datac"; +defparam \D[3]~74 .lut_mask = 16'hA2F3; +defparam \D[3]~74 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~112 ( +// Location: LCCOMB_X20_Y8_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~112_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~32_combout ) # ((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~61_combout )))) +// \ula_|zx_keyboard_|keys[5][1]~39_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[0][0]~11_combout & !\ula_|zx_keyboard_|extended~q )) - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~112_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~112 .lut_mask = 16'hA888; -defparam \ula_|zx_keyboard_|keys[7][3]~112 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~113 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~113_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][3]~112_combout & (\ula_|zx_keyboard_|keys[0][0]~15_combout & !\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[7][3]~112_combout ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[0][0]~11_combout ), .datad(\ula_|zx_keyboard_|extended~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~113_combout ), + .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~113 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[7][3]~113 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~114 ( +// Location: LCCOMB_X21_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~100 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~114_combout = (\ula_|zx_keyboard_|keys[7][3]~113_combout & ((!\ula_|zx_keyboard_|keys[0][4]~111_combout ))) # (!\ula_|zx_keyboard_|keys[7][3]~113_combout & (\ula_|zx_keyboard_|keys[7][3]~q )) +// \ula_|zx_keyboard_|keys[2][3]~100_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & +// !\ula_|ps2_keyboard_|shiftreg [2])) .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[7][3]~113_combout ), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~111_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .combout(\ula_|zx_keyboard_|keys[2][3]~100_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~114 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[7][3]~114 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][3]~100 .lut_mask = 16'h0C30; +defparam \ula_|zx_keyboard_|keys[2][3]~100 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y20_N9 +// Location: LCCOMB_X21_Y10_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|keys[2][3]~100_combout & (\ula_|zx_keyboard_|keys[5][4]~59_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (!\ula_|ps2_keyboard_|shiftreg [3])))) + + .dataa(\ula_|zx_keyboard_|keys[2][3]~100_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[5][4]~59_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'h8200; +defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~99 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~99_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~99 .lut_mask = 16'hF0F5; +defparam \ula_|zx_keyboard_|keys[2][3]~99 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & ((\ula_|zx_keyboard_|keys[2][3]~101_combout & ((!\ula_|zx_keyboard_|keys[2][3]~99_combout ))) # (!\ula_|zx_keyboard_|keys[2][3]~101_combout & +// (\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~39_combout & (((\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .datab(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .datac(\ula_|zx_keyboard_|keys[2][3]~q ), + .datad(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y7_N23 +dffeas \ula_|zx_keyboard_|keys[2][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~97 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~97_combout = (\ula_|zx_keyboard_|keys[6][4]~44_combout & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[5][4]~59_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~44_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[5][4]~59_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~97_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~97 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[3][3]~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~98 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~98_combout = (\ula_|zx_keyboard_|keys[3][3]~97_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][3]~97_combout & ((\ula_|zx_keyboard_|keys[3][3]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][3]~97_combout ), + .datac(\ula_|zx_keyboard_|keys[3][3]~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~98_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~98 .lut_mask = 16'h7474; +defparam \ula_|zx_keyboard_|keys[3][3]~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y7_N25 +dffeas \ula_|zx_keyboard_|keys[3][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][3]~98_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N20 +cycloneive_lcell_comb \D[3]~73 ( +// Equation(s): +// \D[3]~73_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~20_combout ) # ((!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & +// ((\z80_|address_pins_|abus[10]~20_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\z80_|address_pins_|abus[10]~20_combout ), + .datac(\ula_|zx_keyboard_|keys[2][3]~q ), + .datad(\ula_|zx_keyboard_|keys[3][3]~q ), + .cin(gnd), + .combout(\D[3]~73_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~73 .lut_mask = 16'h8ACF; +defparam \D[3]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~108 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~108_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~108 .lut_mask = 16'hFAF0; +defparam \ula_|zx_keyboard_|keys[0][4]~108 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~109 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~109_combout = (\ula_|zx_keyboard_|WideOr16~1_combout & ((\ula_|zx_keyboard_|keys[7][2]~28_combout ) # ((\ula_|zx_keyboard_|keys[7][2]~57_combout & \ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~57_combout ), + .datab(\ula_|zx_keyboard_|keys[7][2]~28_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|WideOr16~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~109_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~109 .lut_mask = 16'hEC00; +defparam \ula_|zx_keyboard_|keys[7][3]~109 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~110 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~110_combout = (\ula_|zx_keyboard_|keys[7][3]~109_combout & ((\ula_|zx_keyboard_|keys[7][2]~56_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[7][2]~56_combout & +// ((\ula_|zx_keyboard_|keys[7][3]~q ))))) # (!\ula_|zx_keyboard_|keys[7][3]~109_combout & (((\ula_|zx_keyboard_|keys[7][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .datab(\ula_|zx_keyboard_|keys[7][3]~109_combout ), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\ula_|zx_keyboard_|keys[7][2]~56_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~110_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~110 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[7][3]~110 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y8_N23 dffeas \ula_|zx_keyboard_|keys[7][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .d(\ula_|zx_keyboard_|keys[7][3]~110_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52321,79 +44865,79 @@ defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~109 ( +// Location: LCCOMB_X20_Y8_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~111 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~109_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [5]))) +// \ula_|zx_keyboard_|keys[6][3]~111_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), .datad(\ula_|ps2_keyboard_|shiftreg [5]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~109_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~111_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~109 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|keys[6][3]~109 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~111 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][3]~111 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~110 ( +// Location: LCCOMB_X20_Y8_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~112 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~110_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~109_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][2]~32_combout ))) +// \ula_|zx_keyboard_|keys[6][3]~112_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~111_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & ((\ula_|zx_keyboard_|keys[7][2]~28_combout )))) .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|zx_keyboard_|keys[6][3]~109_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|zx_keyboard_|keys[6][3]~111_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~112_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~110 .lut_mask = 16'hF088; -defparam \ula_|zx_keyboard_|keys[6][3]~110 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~112 .lut_mask = 16'hCAC0; +defparam \ula_|zx_keyboard_|keys[6][3]~112 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~137 ( +// Location: LCCOMB_X20_Y8_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~132 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~137_combout = (\ula_|zx_keyboard_|extended~q ) # (((!\ula_|zx_keyboard_|keys[0][0]~15_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][3]~110_combout )) +// \ula_|zx_keyboard_|keys[6][3]~132_combout = (((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][3]~112_combout )) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout ) - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .datab(\ula_|zx_keyboard_|keys[6][3]~112_combout ), .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~132_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~137 .lut_mask = 16'hBFFF; -defparam \ula_|zx_keyboard_|keys[6][3]~137 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~132 .lut_mask = 16'hFF7F; +defparam \ula_|zx_keyboard_|keys[6][3]~132 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~138 ( +// Location: LCCOMB_X23_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~133 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~138_combout = (\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~137_combout & ((\ula_|zx_keyboard_|keys[6][3]~q ))) # (!\ula_|zx_keyboard_|keys[6][3]~137_combout & -// (!\ula_|zx_keyboard_|Selector13~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|zx_keyboard_|keys[6][3]~q )))) +// \ula_|zx_keyboard_|keys[6][3]~133_combout = (\ula_|zx_keyboard_|keys[6][3]~132_combout & (((\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[6][3]~132_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & +// ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[6][3]~q )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|Selector13~0_combout ), + .dataa(\ula_|zx_keyboard_|keys[6][3]~132_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), .datac(\ula_|zx_keyboard_|keys[6][3]~q ), - .datad(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .datad(\ula_|zx_keyboard_|Selector13~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~133_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~138 .lut_mask = 16'hF072; -defparam \ula_|zx_keyboard_|keys[6][3]~138 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~133 .lut_mask = 16'hB0F4; +defparam \ula_|zx_keyboard_|keys[6][3]~133 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y21_N29 +// Location: FF_X23_Y8_N5 dffeas \ula_|zx_keyboard_|keys[6][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .d(\ula_|zx_keyboard_|keys[6][3]~133_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52409,115 +44953,220 @@ defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( +// Location: LCCOMB_X23_Y8_N30 +cycloneive_lcell_comb \D[3]~75 ( // Equation(s): -// \ula_|zx_keyboard_|key_row~2_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # ((!\ula_|zx_keyboard_|keys[6][3]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) +// \D[3]~75_combout = (\ula_|zx_keyboard_|keys[7][3]~q & (\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[7][3]~q & +// ((\z80_|address_pins_|abus[14]~22_combout ) # ((!\ula_|zx_keyboard_|keys[6][3]~q )))) - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [14]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|zx_keyboard_|keys[6][3]~q ), + .dataa(\ula_|zx_keyboard_|keys[7][3]~q ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ula_|zx_keyboard_|keys[6][3]~q ), + .datad(\z80_|address_pins_|abus[15]~21_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~2_combout ), + .combout(\D[3]~75_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hCFFF; -defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; +defparam \D[3]~75 .lut_mask = 16'hCF45; +defparam \D[3]~75 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N8 -cycloneive_lcell_comb \D[3]~68 ( +// Location: LCCOMB_X23_Y8_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~94 ( // Equation(s): -// \D[3]~68_combout = (\D[3]~67_combout & (\ula_|zx_keyboard_|key_row~2_combout & ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) +// \ula_|zx_keyboard_|keys[0][3]~94_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\D[3]~67_combout ), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|key_row~2_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\D[3]~68_combout ), + .combout(\ula_|zx_keyboard_|keys[0][3]~94_combout ), .cout()); // synopsys translate_off -defparam \D[3]~68 .lut_mask = 16'h8C00; -defparam \D[3]~68 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[0][3]~94 .lut_mask = 16'h2004; +defparam \ula_|zx_keyboard_|keys[0][3]~94 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N30 -cycloneive_lcell_comb \D[3]~69 ( +// Location: LCCOMB_X23_Y8_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~93 ( // Equation(s): -// \D[3]~69_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[3]~65_combout & (\D[3]~66_combout & \D[3]~68_combout ))) +// \ula_|zx_keyboard_|keys[2][4]~93_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|shifted~q )) - .dataa(\D[3]~65_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[3]~66_combout ), - .datad(\D[3]~68_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), .cin(gnd), - .combout(\D[3]~69_combout ), + .combout(\ula_|zx_keyboard_|keys[2][4]~93_combout ), .cout()); // synopsys translate_off -defparam \D[3]~69 .lut_mask = 16'hECCC; -defparam \D[3]~69 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][4]~93 .lut_mask = 16'hF0FA; +defparam \ula_|zx_keyboard_|keys[2][4]~93 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y11_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: LCCOMB_X23_Y7_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~95 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~95_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~95 .lut_mask = 16'h0060; +defparam \ula_|zx_keyboard_|keys[0][4]~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|zx_keyboard_|keys[0][3]~94_combout & ((\ula_|zx_keyboard_|keys[0][4]~95_combout & (!\ula_|zx_keyboard_|keys[2][4]~93_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & +// ((\ula_|zx_keyboard_|keys[0][3]~q ))))) # (!\ula_|zx_keyboard_|keys[0][3]~94_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][3]~94_combout ), + .datab(\ula_|zx_keyboard_|keys[2][4]~93_combout ), + .datac(\ula_|zx_keyboard_|keys[0][3]~q ), + .datad(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y8_N3 +dffeas \ula_|zx_keyboard_|keys[0][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), - .portbdataout()); + .q(\ula_|zx_keyboard_|keys[0][3]~q ), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; // synopsys translate_on -// Location: M9K_X22_Y15_N0 +// Location: LCCOMB_X19_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~91 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~91_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][4]~15_combout & \ula_|zx_keyboard_|keys[6][4]~43_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[7][4]~15_combout ), + .datad(\ula_|zx_keyboard_|keys[6][4]~43_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~91_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~91 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[1][3]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~92 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~92_combout = (\ula_|zx_keyboard_|keys[1][3]~91_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # +// (!\ula_|zx_keyboard_|keys[1][3]~91_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][3]~91_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~92 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][3]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y9_N5 +dffeas \ula_|zx_keyboard_|keys[1][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N8 +cycloneive_lcell_comb \D[3]~72 ( +// Equation(s): +// \D[3]~72_combout = (\z80_|address_pins_|abus[9]~17_combout & (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][3]~q ))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][3]~q & +// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\z80_|address_pins_|abus[9]~17_combout ), + .datab(\ula_|zx_keyboard_|keys[0][3]~q ), + .datac(\z80_|address_pins_|abus[8]~18_combout ), + .datad(\ula_|zx_keyboard_|keys[1][3]~q ), + .cin(gnd), + .combout(\D[3]~72_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~72 .lut_mask = 16'hA2F3; +defparam \D[3]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N10 +cycloneive_lcell_comb \D[3]~76 ( +// Equation(s): +// \D[3]~76_combout = (\D[3]~74_combout & (\D[3]~73_combout & (\D[3]~75_combout & \D[3]~72_combout ))) + + .dataa(\D[3]~74_combout ), + .datab(\D[3]~73_combout ), + .datac(\D[3]~75_combout ), + .datad(\D[3]~72_combout ), + .cin(gnd), + .combout(\D[3]~76_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~76 .lut_mask = 16'h8000; +defparam \D[3]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N2 +cycloneive_lcell_comb \D[3]~122 ( +// Equation(s): +// \D[3]~122_combout = (\Equal2~0_combout & ((\D[3]~76_combout ) # ((\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) + + .dataa(\D[3]~76_combout ), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\Equal2~0_combout ), + .cin(gnd), + .combout(\D[3]~122_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~122 .lut_mask = 16'hEF00; +defparam \D[3]~122 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y14_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), @@ -52533,8 +45182,8 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52574,7 +45223,24 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; // synopsys translate_on -// Location: M9K_X22_Y18_N0 +// Location: LCCOMB_X25_Y15_N28 +cycloneive_lcell_comb \D[3]~79 ( +// Equation(s): +// \D[3]~79_combout = (!\Equal2~0_combout & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\Equal2~0_combout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\D[3]~79_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~79 .lut_mask = 16'h3332; +defparam \D[3]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), @@ -52590,8 +45256,8 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52631,25 +45297,7 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N14 -cycloneive_lcell_comb \D[3]~73 ( -// Equation(s): -// \D[3]~73_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .cin(gnd), - .combout(\D[3]~73_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~73 .lut_mask = 16'hCCE2; -defparam \D[3]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y5_N0 +// Location: M9K_X22_Y15_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), .portare(vcc), @@ -52665,8 +45313,8 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52706,42 +45354,24 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N16 -cycloneive_lcell_comb \D[3]~74 ( -// Equation(s): -// \D[3]~74_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\D[3]~73_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ))) # (!\D[3]~73_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[3]~73_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datac(\D[3]~73_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), - .cin(gnd), - .combout(\D[3]~74_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~74 .lut_mask = 16'hF858; -defparam \D[3]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y19_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(vcc), +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52750,39 +45380,238 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y23_N0 +// Location: M9K_X33_Y12_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N20 +cycloneive_lcell_comb \D[3]~77 ( +// Equation(s): +// \D[3]~77_combout = (\z80_|address_pins_|abus[15]~21_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) # (!\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # +// ((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\D[3]~77_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~77 .lut_mask = 16'hF5E4; +defparam \D[3]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N22 +cycloneive_lcell_comb \D[3]~80 ( +// Equation(s): +// \D[3]~80_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~77_combout ))) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\D[3]~77_combout ), + .cin(gnd), + .combout(\D[3]~80_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~80 .lut_mask = 16'hCFC0; +defparam \D[3]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N4 +cycloneive_lcell_comb \D[3]~81 ( +// Equation(s): +// \D[3]~81_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[3]~80_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout +// )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datac(\D[3]~80_combout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\D[3]~81_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~81 .lut_mask = 16'hF0DD; +defparam \D[3]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N30 +cycloneive_lcell_comb \D[3]~124 ( +// Equation(s): +// \D[3]~124_combout = (\D[3]~77_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ) # ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datad(\D[3]~77_combout ), + .cin(gnd), + .combout(\D[3]~124_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~124 .lut_mask = 16'hF200; +defparam \D[3]~124 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y23_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), @@ -52792,14 +45621,14 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52855,26 +45684,8 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N24 -cycloneive_lcell_comb \D[3]~70 ( -// Equation(s): -// \D[3]~70_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~23_combout )) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\z80_|address_pins_|abus[14]~23_combout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .cin(gnd), - .combout(\D[3]~70_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~70 .lut_mask = 16'hEC64; -defparam \D[3]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y21_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( +// Location: M9K_X22_Y32_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), @@ -52883,14 +45694,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52899,217 +45710,143 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N22 -cycloneive_lcell_comb \D[3]~71 ( +// Location: LCCOMB_X25_Y15_N0 +cycloneive_lcell_comb \D[3]~123 ( // Equation(s): -// \D[3]~71_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout $ (((\D[3]~70_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout & !\D[3]~70_combout )))) +// \D[3]~123_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & (\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # (!\z80_|address_pins_|DFFE_apin_latch [14] & +// ((\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datad(\D[3]~70_combout ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), .cin(gnd), - .combout(\D[3]~71_combout ), + .combout(\D[3]~123_combout ), .cout()); // synopsys translate_off -defparam \D[3]~71 .lut_mask = 16'h22D8; -defparam \D[3]~71 .sum_lutc_input = "datac"; +defparam \D[3]~123 .lut_mask = 16'hF2D0; +defparam \D[3]~123 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y31_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N20 -cycloneive_lcell_comb \D[3]~72 ( +// Location: LCCOMB_X25_Y15_N10 +cycloneive_lcell_comb \D[3]~78 ( // Equation(s): -// \D[3]~72_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\D[3]~70_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~70_combout & (!\D[3]~71_combout & -// \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout )) # (!\D[3]~70_combout & (\D[3]~71_combout )))) +// \D[3]~78_combout = (!\Equal2~0_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~123_combout ))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\D[3]~124_combout )))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\D[3]~70_combout ), - .datac(\D[3]~71_combout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .dataa(\Equal2~0_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[3]~124_combout ), + .datad(\D[3]~123_combout ), .cin(gnd), - .combout(\D[3]~72_combout ), + .combout(\D[3]~78_combout ), .cout()); // synopsys translate_off -defparam \D[3]~72 .lut_mask = 16'h9C98; -defparam \D[3]~72 .sum_lutc_input = "datac"; +defparam \D[3]~78 .lut_mask = 16'h5410; +defparam \D[3]~78 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N28 +// Location: LCCOMB_X25_Y15_N6 +cycloneive_lcell_comb \D[3]~82 ( +// Equation(s): +// \D[3]~82_combout = (\z80_|address_pins_|abus[15]~21_combout & (\D[3]~79_combout & (\D[3]~81_combout ))) # (!\z80_|address_pins_|abus[15]~21_combout & (((\D[3]~78_combout )))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\D[3]~79_combout ), + .datac(\D[3]~81_combout ), + .datad(\D[3]~78_combout ), + .cin(gnd), + .combout(\D[3]~82_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~82 .lut_mask = 16'hD580; +defparam \D[3]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N26 cycloneive_lcell_comb \D[3]~108 ( // Equation(s): -// \D[3]~108_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[3]~74_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[3]~72_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[3]~74_combout )))) +// \D[3]~108_combout = ((\D[3]~122_combout ) # (\D[3]~82_combout )) # (!\Equal2~1_combout ) - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\D[3]~74_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[3]~72_combout ), + .dataa(\Equal2~1_combout ), + .datab(\D[3]~122_combout ), + .datac(gnd), + .datad(\D[3]~82_combout ), .cin(gnd), .combout(\D[3]~108_combout ), .cout()); // synopsys translate_off -defparam \D[3]~108 .lut_mask = 16'hDC8C; +defparam \D[3]~108 .lut_mask = 16'hFFDD; defparam \D[3]~108 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N4 -cycloneive_lcell_comb \D[3]~95 ( +// Location: LCCOMB_X25_Y15_N8 +cycloneive_lcell_comb \D[3]~109 ( // Equation(s): -// \D[3]~95_combout = ((\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout )))) # (!\Equal2~1_combout ) +// \D[3]~109_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [3] & (\D[3]~108_combout ))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[3]~108_combout ) # (!\Equal2~1_combout )))) - .dataa(\D[3]~69_combout ), - .datab(\Equal2~1_combout ), - .datac(\Equal2~0_combout ), - .datad(\D[3]~108_combout ), + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|data_pins_|dout [3]), + .datac(\D[3]~108_combout ), + .datad(\Equal2~1_combout ), .cin(gnd), - .combout(\D[3]~95_combout ), + .combout(\D[3]~109_combout ), .cout()); // synopsys translate_off -defparam \D[3]~95 .lut_mask = 16'hBFB3; -defparam \D[3]~95 .sum_lutc_input = "datac"; +defparam \D[3]~109 .lut_mask = 16'hD0D5; +defparam \D[3]~109 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N26 -cycloneive_lcell_comb \D[3]~96 ( -// Equation(s): -// \D[3]~96_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [3] & \D[3]~95_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[3]~95_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [3]), - .datad(\D[3]~95_combout ), - .cin(gnd), - .combout(\D[3]~96_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~96 .lut_mask = 16'hF511; -defparam \D[3]~96 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N6 +// Location: LCCOMB_X28_Y12_N4 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[3]~21_combout ) # ((\D[3]~96_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[3]~96_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[3]~109_combout ) # ((\z80_|bus_control_|db[3]~21_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & +// (((\z80_|bus_control_|db[3]~21_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[3]~96_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), + .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), + .datab(\D[3]~109_combout ), + .datac(\z80_|bus_control_|db[3]~21_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hF888; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N7 +// Location: FF_X28_Y12_N5 dffeas \z80_|data_pins_|dout[3] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), @@ -53128,41 +45865,41 @@ defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N4 +// Location: LCCOMB_X28_Y12_N22 cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( // Equation(s): // \z80_|bus_control_|db[3]~20_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(\z80_|data_pins_|dout [3]), - .datac(gnd), + .dataa(gnd), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|data_pins_|dout [3]), .datad(\z80_|bus_control_|db[0]~4_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[3]~20_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hDD00; +defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hF300; defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N0 +// Location: LCCOMB_X27_Y12_N28 cycloneive_lcell_comb \z80_|bus_control_|db[3]~21 ( // Equation(s): -// \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~36_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|bus_control_|db[0]~6_combout ), + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), .datab(\z80_|bus_control_|db[3]~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|alu_control_|db[3]~36_combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[3]~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hDD5D; +defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hC4FF; defparam \z80_|bus_control_|db[3]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y10_N1 +// Location: FF_X27_Y12_N29 dffeas \z80_|ir_|opcode[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|bus_control_|db[3]~21_combout ), @@ -53181,41 +45918,7772 @@ defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( +// Location: LCCOMB_X39_Y8_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~4_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) +// \z80_|pla_decode_|Equal33~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4])) .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal52~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~4_combout ), + .combout(\z80_|pla_decode_|Equal33~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N20 +// Location: LCCOMB_X36_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N4 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( +// Equation(s): +// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hCECF; +defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N6 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( +// Equation(s): +// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|bus_control_|db[0]~4_combout ), + .datab(\z80_|alu_control_|db[7]~37_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'h88AA; +defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y1_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 .lut_mask = 16'hCFA0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N2 +cycloneive_lcell_comb \D[5]~97 ( +// Equation(s): +// \D[5]~97_combout = (\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|control_pins_|pin_nIORQ~1_combout ))) + + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), + .cin(gnd), + .combout(\D[5]~97_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~97 .lut_mask = 16'h2000; +defparam \D[5]~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y21_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y3_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: M9K_X33_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y27_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N6 +cycloneive_lcell_comb \Mux0~0 ( +// Equation(s): +// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) # (!\z80_|address_pins_|abus[14]~22_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~0 .lut_mask = 16'hB9A8; +defparam \Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N4 +cycloneive_lcell_comb \Mux0~1 ( +// Equation(s): +// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datad(\Mux0~0_combout ), + .cin(gnd), + .combout(\Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~1 .lut_mask = 16'hDDA0; +defparam \Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N20 +cycloneive_lcell_comb \D[7]~116 ( +// Equation(s): +// \D[7]~116_combout = ((\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )) # (!\z80_|address_pins_|abus[15]~21_combout & ((\Mux0~1_combout )))) # (!\D[5]~97_combout ) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .datab(\D[5]~97_combout ), + .datac(\z80_|address_pins_|abus[15]~21_combout ), + .datad(\Mux0~1_combout ), + .cin(gnd), + .combout(\D[7]~116_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~116 .lut_mask = 16'hBFB3; +defparam \D[7]~116 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N26 +cycloneive_lcell_comb \D[7]~117 ( +// Equation(s): +// \D[7]~117_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [7] & \D[7]~116_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[7]~116_combout )) # (!\Equal2~1_combout ))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [7]), + .datad(\D[7]~116_combout ), + .cin(gnd), + .combout(\D[7]~117_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~117 .lut_mask = 16'hF311; +defparam \D[7]~117 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N0 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\z80_|bus_control_|db[7]~7_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[7]~117_combout )))) # (!\z80_|bus_control_|db[7]~7_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[7]~117_combout ))) + + .dataa(\z80_|bus_control_|db[7]~7_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\D[7]~117_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N1 +dffeas \z80_|data_pins_|dout[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N20 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( +// Equation(s): +// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[7]~5_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|bus_control_|db[0]~6_combout ), + .datad(\z80_|data_pins_|dout [7]), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hAF2F; +defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N13 +dffeas \z80_|ir_|opcode[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[7]~7_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~2_combout = (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~0_combout & \z80_|pla_decode_|Equal41~1_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datad(\z80_|pla_decode_|Equal41~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|pla_decode_|Equal36~0_combout & (((\z80_|pla_decode_|Equal41~2_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # +// (!\z80_|pla_decode_|Equal36~0_combout & (\z80_|pla_decode_|Equal41~2_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal36~0_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hC0EA; +defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h3222; +defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y7_N9 +dffeas \z80_|decode_state_|DFFE_instCB ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instCB~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|execute_|comb~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N29 +dffeas \z80_|interrupts_|im1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_im_we~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|im1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|interrupts_|im1~q ), + .datad(\z80_|interrupts_|im2~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hC4C0; +defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & +// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h4F0A; +defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_ff_oe~1_combout & (!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0203; +defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_bus_db_oe~5_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; +defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (\z80_|execute_|ctl_bus_db_oe~4_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hAAA2; +defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~88 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~88_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~88_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~88 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[6][0]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~1_combout = (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~89 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~89_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|zx_keyboard_|keys[6][0]~88_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|shifted~1_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .datab(\ula_|zx_keyboard_|keys[6][0]~88_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|shifted~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~89 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[6][0]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|zx_keyboard_|keys[6][0]~89_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][0]~89_combout & ((\ula_|zx_keyboard_|keys[6][0]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[6][0]~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h7272; +defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y10_N23 +dffeas \ula_|zx_keyboard_|keys[6][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~84 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~84_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~84_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~84 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[7][0]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~78 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~78_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~78 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[5][0]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~85 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~85_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[5][0]~78_combout ) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[5][0]~78_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~85_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~85 .lut_mask = 16'h3300; +defparam \ula_|zx_keyboard_|keys[7][0]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~86 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~86_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[3][0]~73_combout & (\ula_|zx_keyboard_|keys[5][4]~20_combout ))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|keys[7][0]~85_combout +// )))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~73_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~20_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|keys[7][0]~85_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~86 .lut_mask = 16'h8F80; +defparam \ula_|zx_keyboard_|keys[7][0]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[7][0]~84_combout & ((\ula_|zx_keyboard_|keys[7][0]~86_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][0]~86_combout & ((\ula_|zx_keyboard_|keys[7][0]~q +// ))))) # (!\ula_|zx_keyboard_|keys[7][0]~84_combout & (((\ula_|zx_keyboard_|keys[7][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][0]~84_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[7][0]~q ), + .datad(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y10_N1 +dffeas \ula_|zx_keyboard_|keys[7][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N28 +cycloneive_lcell_comb \D[0]~57 ( +// Equation(s): +// \D[0]~57_combout = (\ula_|zx_keyboard_|keys[6][0]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\ula_|zx_keyboard_|keys[6][0]~q & +// (((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][0]~q ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[15]~21_combout ), + .datad(\ula_|zx_keyboard_|keys[7][0]~q ), + .cin(gnd), + .combout(\D[0]~57_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~57 .lut_mask = 16'hD0DD; +defparam \D[0]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~81 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~81_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [5]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & +// (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [5])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~81_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~81 .lut_mask = 16'h1024; +defparam \ula_|zx_keyboard_|keys[4][0]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~82 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~82_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~82_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~82 .lut_mask = 16'hF0FA; +defparam \ula_|zx_keyboard_|keys[4][0]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~40 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~40_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][1]~39_combout & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~40 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[5][1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~83 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~83_combout = (\ula_|zx_keyboard_|keys[4][0]~81_combout & ((\ula_|zx_keyboard_|keys[5][1]~40_combout & (!\ula_|zx_keyboard_|keys[4][0]~82_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~40_combout & +// ((\ula_|zx_keyboard_|keys[4][0]~q ))))) # (!\ula_|zx_keyboard_|keys[4][0]~81_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][0]~81_combout ), + .datab(\ula_|zx_keyboard_|keys[4][0]~82_combout ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~40_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~83_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~83 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][0]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y8_N23 +dffeas \ula_|zx_keyboard_|keys[4][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][0]~83_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~79 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~79_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (((!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[5][0]~78_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & +// ((\ula_|zx_keyboard_|keys[3][0]~73_combout ) # (\ula_|zx_keyboard_|keys[5][0]~78_combout )))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~73_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[5][0]~78_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~79_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~79 .lut_mask = 16'h3C20; +defparam \ula_|zx_keyboard_|keys[5][0]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~80 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~80_combout = (\ula_|zx_keyboard_|keys[6][1]~32_combout & ((\ula_|zx_keyboard_|keys[5][0]~79_combout & (!\ula_|zx_keyboard_|keys[5][0]~62_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~79_combout & +// ((\ula_|zx_keyboard_|keys[5][0]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~32_combout & (((\ula_|zx_keyboard_|keys[5][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~62_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~32_combout ), + .datac(\ula_|zx_keyboard_|keys[5][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][0]~79_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~80 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[5][0]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y9_N15 +dffeas \ula_|zx_keyboard_|keys[5][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N2 +cycloneive_lcell_comb \D[0]~56 ( +// Equation(s): +// \D[0]~56_combout = (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\z80_|address_pins_|abus[13]~23_combout & (!\ula_|zx_keyboard_|keys[5][0]~q & +// ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~23_combout ), + .datab(\z80_|address_pins_|abus[12]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][0]~q ), + .cin(gnd), + .combout(\D[0]~56_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~56 .lut_mask = 16'h8ACF; +defparam \D[0]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~76 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~76_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~21_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~76_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~76 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[1][0]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~77 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~77_combout = (\ula_|zx_keyboard_|keys[1][0]~76_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][0]~76_combout & ((\ula_|zx_keyboard_|keys[1][0]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[1][0]~q ), + .datad(\ula_|zx_keyboard_|keys[1][0]~76_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~77_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~77 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[1][0]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N23 +dffeas \ula_|zx_keyboard_|keys[1][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][0]~77_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~68 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~68_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~68_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~68 .lut_mask = 16'hC0C0; +defparam \ula_|zx_keyboard_|keys[4][3]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [2] & ((!\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & +// \ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0130; +defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~69 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~69_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|zx_keyboard_|WideOr0~0_combout )) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|keys[6][4]~43_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[6][4]~43_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~69_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~69 .lut_mask = 16'h2777; +defparam \ula_|zx_keyboard_|keys~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~70 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~70_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][3]~68_combout & !\ula_|zx_keyboard_|keys~69_combout )) # (!\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .datab(\ula_|zx_keyboard_|keys[4][3]~68_combout ), + .datac(\ula_|zx_keyboard_|keys~69_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~70_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~70 .lut_mask = 16'h08AA; +defparam \ula_|zx_keyboard_|keys[0][0]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~27 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~27_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~27 .lut_mask = 16'h3030; +defparam \ula_|zx_keyboard_|keys[4][1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & +// (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'hC002; +defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~71 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~71_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|WideOr4~0_combout )) # (!\ula_|zx_keyboard_|keys[4][1]~27_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[4][1]~27_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|WideOr4~0_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~71_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~71 .lut_mask = 16'h3313; +defparam \ula_|zx_keyboard_|keys~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~72 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~72_combout = (\ula_|zx_keyboard_|keys[0][0]~70_combout & ((\ula_|zx_keyboard_|keys~71_combout & ((\ula_|zx_keyboard_|keys[0][0]~q ))) # (!\ula_|zx_keyboard_|keys~71_combout & (!\ula_|zx_keyboard_|released~q )))) # +// (!\ula_|zx_keyboard_|keys[0][0]~70_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~70_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[0][0]~q ), + .datad(\ula_|zx_keyboard_|keys~71_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~72_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~72 .lut_mask = 16'hF072; +defparam \ula_|zx_keyboard_|keys[0][0]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y8_N11 +dffeas \ula_|zx_keyboard_|keys[0][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][0]~72_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~2_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # ((!\ula_|zx_keyboard_|keys[0][0]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [8]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hAFFF; +defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~22 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~22_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~21_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~22 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|keys[2][1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~75 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][0]~75_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~22_combout & (!\ula_|zx_keyboard_|released~q )) # +// (!\ula_|zx_keyboard_|keys[2][1]~22_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~22_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][0]~75_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0]~75 .lut_mask = 16'hD1F0; +defparam \ula_|zx_keyboard_|keys[2][0]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N15 +dffeas \ula_|zx_keyboard_|keys[2][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][0]~75_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~24 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~24_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~24 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[3][1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~74 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~74_combout = (\ula_|zx_keyboard_|keys[3][0]~73_combout & ((\ula_|zx_keyboard_|keys[3][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~24_combout & ((\ula_|zx_keyboard_|keys[3][0]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][0]~73_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][0]~73_combout ), + .datac(\ula_|zx_keyboard_|keys[3][0]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~24_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~74_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~74 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][0]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N17 +dffeas \ula_|zx_keyboard_|keys[3][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][0]~74_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N0 +cycloneive_lcell_comb \D[0]~54 ( +// Equation(s): +// \D[0]~54_combout = (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][0]~q )))) # (!\z80_|address_pins_|abus[10]~20_combout & (!\ula_|zx_keyboard_|keys[2][0]~q & +// ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][0]~q )))) + + .dataa(\z80_|address_pins_|abus[10]~20_combout ), + .datab(\z80_|address_pins_|abus[11]~19_combout ), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|keys[3][0]~q ), + .cin(gnd), + .combout(\D[0]~54_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~54 .lut_mask = 16'h8CAF; +defparam \D[0]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N12 +cycloneive_lcell_comb \D[0]~55 ( +// Equation(s): +// \D[0]~55_combout = (\ula_|zx_keyboard_|key_row~2_combout & (\D[0]~54_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][0]~q ), + .datab(\z80_|address_pins_|abus[9]~17_combout ), + .datac(\ula_|zx_keyboard_|key_row~2_combout ), + .datad(\D[0]~54_combout ), + .cin(gnd), + .combout(\D[0]~55_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~55 .lut_mask = 16'hD000; +defparam \D[0]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N0 +cycloneive_lcell_comb \D[0]~58 ( +// Equation(s): +// \D[0]~58_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~57_combout & (\D[0]~56_combout & \D[0]~55_combout ))) + + .dataa(\D[0]~57_combout ), + .datab(\D[0]~56_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[0]~55_combout ), + .cin(gnd), + .combout(\D[0]~58_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~58 .lut_mask = 16'hF8F0; +defparam \D[0]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N12 +cycloneive_lcell_comb \D[0]~62 ( +// Equation(s): +// \D[0]~62_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .cin(gnd), + .combout(\D[0]~62_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~62 .lut_mask = 16'hEC64; +defparam \D[0]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N8 +cycloneive_lcell_comb \D[0]~63 ( +// Equation(s): +// \D[0]~63_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~62_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~62_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # (!\D[0]~62_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[0]~62_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\D[0]~63_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~63 .lut_mask = 16'hE3E0; +defparam \D[0]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y29_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y4_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N6 +cycloneive_lcell_comb \D[0]~59 ( +// Equation(s): +// \D[0]~59_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout & +// (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .cin(gnd), + .combout(\D[0]~59_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~59 .lut_mask = 16'hE6A2; +defparam \D[0]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y29_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y11_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N28 +cycloneive_lcell_comb \D[0]~60 ( +// Equation(s): +// \D[0]~60_combout = (\z80_|address_pins_|abus[15]~21_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout $ (\D[0]~59_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout & ((!\D[0]~59_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datac(\z80_|address_pins_|abus[15]~21_combout ), + .datad(\D[0]~59_combout ), + .cin(gnd), + .combout(\D[0]~60_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~60 .lut_mask = 16'h30CA; +defparam \D[0]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N10 +cycloneive_lcell_comb \D[0]~61 ( +// Equation(s): +// \D[0]~61_combout = (\D[0]~59_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & !\D[0]~60_combout )))) # (!\D[0]~59_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~60_combout )))) + + .dataa(\D[0]~59_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datad(\D[0]~60_combout ), + .cin(gnd), + .combout(\D[0]~61_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~61 .lut_mask = 16'h99A8; +defparam \D[0]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N18 +cycloneive_lcell_comb \D[0]~120 ( +// Equation(s): +// \D[0]~120_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[0]~63_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[0]~61_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[0]~63_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\D[0]~63_combout ), + .datad(\D[0]~61_combout ), + .cin(gnd), + .combout(\D[0]~120_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~120 .lut_mask = 16'hF4B0; +defparam \D[0]~120 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N26 +cycloneive_lcell_comb \D[0]~64 ( +// Equation(s): +// \D[0]~64_combout = ((\Equal2~0_combout & (\D[0]~58_combout )) # (!\Equal2~0_combout & ((\D[0]~120_combout )))) # (!\Equal2~1_combout ) + + .dataa(\D[0]~58_combout ), + .datab(\Equal2~0_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[0]~120_combout ), + .cin(gnd), + .combout(\D[0]~64_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~64 .lut_mask = 16'hBF8F; +defparam \D[0]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N16 +cycloneive_lcell_comb \D[0]~65 ( +// Equation(s): +// \D[0]~65_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [0] & (\D[0]~64_combout ))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[0]~64_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [0]), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\D[0]~64_combout ), + .datad(\Equal2~1_combout ), + .cin(gnd), + .combout(\D[0]~65_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~65 .lut_mask = 16'hB0B3; +defparam \D[0]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N26 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\D[0]~65_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[0]~17_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[0]~65_combout & +// (((\z80_|bus_control_|db[0]~17_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) + + .dataa(\D[0]~65_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|bus_control_|db[0]~17_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N27 +dffeas \z80_|data_pins_|dout[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N30 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( +// Equation(s): +// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|bus_control_|db[0]~4_combout ), + .datad(\z80_|data_pins_|dout [0]), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'hF030; +defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N12 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( +// Equation(s): +// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~14_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~16_combout ), + .datab(\z80_|alu_control_|db[0]~14_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'h8AFF; +defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N19 +dffeas \z80_|ir_|opcode[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[0]~17_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal3~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal3~2_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pla_decode_|Equal3~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y7_N31 +dffeas \z80_|decode_state_|DFFE_instIY1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_iy_set~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instIY1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N16 +cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( +// Equation(s): +// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|decode_state_|use_ixiy~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFFF0; +defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( +// Equation(s): +// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~9_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~8_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; +defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( +// Equation(s): +// \z80_|execute_|ixy_d~13_combout = (\z80_|execute_|ixy_d~16_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|pla_decode_|Equal41~2_combout )) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ixy_d~10_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( +// Equation(s): +// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~5_combout & (((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )))) # (!\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ixy_d~12_combout ) # +// ((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ixy_d~12_combout ), + .datac(\z80_|execute_|ixy_d~13_combout ), + .datad(\z80_|execute_|ixy_d~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h4F44; +defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( +// Equation(s): +// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hAA8A; +defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( +// Equation(s): +// \z80_|execute_|ixy_d~15_combout = ((\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal49~0_combout & \z80_|execute_|ixy_d~11_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|ixy_d~14_combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|execute_|ixy_d~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'hB333; +defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~9_combout = (\z80_|execute_|ctl_flags_xy_we~8_combout & (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h0070; +defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~12_combout = ((\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_ir_we~12_combout ) # (\z80_|execute_|ctl_ir_we~11_combout )))) # (!\z80_|execute_|ctl_alu_oe~6_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hBBB3; +defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_alu_oe~11_combout ) # ((\z80_|execute_|ctl_alu_oe~12_combout ) # (!\z80_|execute_|ctl_alu_oe~8_combout ))) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~11_combout ), + .datac(\z80_|execute_|ctl_alu_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~14_combout = ((\z80_|execute_|ctl_alu_oe~13_combout ) # ((!\z80_|execute_|ctl_alu_oe~10_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~9_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~13_combout ), + .datac(\z80_|execute_|ctl_flags_alu~14_combout ), + .datad(\z80_|execute_|ctl_alu_oe~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N6 +cycloneive_lcell_comb \z80_|alu_|db[7]~9 ( +// Equation(s): +// \z80_|alu_|db[7]~9_combout = (\z80_|execute_|ctl_alu_oe~14_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (\z80_|execute_|ctl_reg_out_hi~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~9 .lut_mask = 16'hFFFC; +defparam \z80_|alu_|db[7]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N0 +cycloneive_lcell_comb \z80_|alu_|db[1]~15 ( +// Equation(s): +// \z80_|alu_|db[1]~15_combout = (\z80_|alu_control_|db[1]~27_combout & (((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[1]~27_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) + + .dataa(\z80_|alu_control_|db[1]~27_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~15 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N14 +cycloneive_lcell_comb \z80_|alu_|db[1]~16 ( +// Equation(s): +// \z80_|alu_|db[1]~16_combout = ((\z80_|alu_|db[1]~15_combout & ((\z80_|alu_|db_low[1]~20_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db_low[1]~20_combout ), + .datad(\z80_|alu_|db[1]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~16 .lut_mask = 16'hF755; +defparam \z80_|alu_|db[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( +// Equation(s): +// \z80_|alu_control_|db[1]~25_combout = (\z80_|alu_|db[1]~16_combout & (\z80_|execute_|ctl_flags_oe~2_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) # (!\z80_|alu_|db[1]~16_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((\z80_|execute_|ctl_flags_oe~2_combout & !\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) + + .dataa(\z80_|alu_|db[1]~16_combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h50DC; +defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( +// Equation(s): +// \z80_|alu_control_|db[1]~26_combout = (!\z80_|alu_control_|db[1]~25_combout & (\z80_|alu_control_|db[2]~24_combout & ((\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|alu_control_|db[1]~25_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .datad(\z80_|alu_control_|db[2]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h5100; +defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N6 +cycloneive_lcell_comb \z80_|sw1_|db_down[1]~2 ( +// Equation(s): +// \z80_|sw1_|db_down[1]~2_combout = ((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) + + .dataa(\z80_|bus_control_|db[1]~11_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datad(\z80_|execute_|ctl_sw_1d~7_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[1]~2 .lut_mask = 16'h0AFF; +defparam \z80_|sw1_|db_down[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~27 ( +// Equation(s): +// \z80_|alu_control_|db[1]~27_combout = ((\z80_|alu_control_|db[1]~26_combout & \z80_|sw1_|db_down[1]~2_combout )) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[1]~26_combout ), + .datac(\z80_|alu_control_|db[6]~13_combout ), + .datad(\z80_|sw1_|db_down[1]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~27 .lut_mask = 16'hCF0F; +defparam \z80_|alu_control_|db[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N12 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( +// Equation(s): +// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~27_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|alu_control_|db[1]~27_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[0]~4_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hBB00; +defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~38_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'hFAF0; +defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~41 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~41_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~41 .lut_mask = 16'h0005; +defparam \ula_|zx_keyboard_|keys[5][1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~42 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~42_combout = (\ula_|zx_keyboard_|keys[5][1]~41_combout & ((\ula_|zx_keyboard_|keys[5][1]~40_combout & (!\ula_|zx_keyboard_|keys[5][1]~38_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~40_combout & +// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~41_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~38_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~41_combout ), + .datac(\ula_|zx_keyboard_|keys[5][1]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~40_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~42 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[5][1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y8_N9 +dffeas \ula_|zx_keyboard_|keys[5][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][1]~42_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~30 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~30_combout = (\ula_|zx_keyboard_|keys[5][2]~29_combout & ((\ula_|zx_keyboard_|keys[4][1]~27_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][1]~27_combout & ((\ula_|zx_keyboard_|keys[4][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~29_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~29_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][1]~q ), + .datad(\ula_|zx_keyboard_|keys[4][1]~27_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~30 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y10_N9 +dffeas \ula_|zx_keyboard_|keys[4][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][1]~30_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~0_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # ((!\ula_|zx_keyboard_|keys[4][1]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [12]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|zx_keyboard_|keys[4][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hCFFF; +defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~36 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~36_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~36 .lut_mask = 16'h0010; +defparam \ula_|zx_keyboard_|keys[7][1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~3_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & +// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h444A; +defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [0] & +// (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~0 .lut_mask = 16'h0120; +defparam \ula_|zx_keyboard_|WideOr16~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~2_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~1_combout & (!\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|zx_keyboard_|WideOr16~1_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|WideOr16~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'hF202; +defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~4_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~2_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~3_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|WideOr16~3_combout ), + .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'hEA40; +defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~37 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~37_combout = (\ula_|zx_keyboard_|keys[7][1]~36_combout & ((\ula_|zx_keyboard_|WideOr16~4_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~4_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # +// (!\ula_|zx_keyboard_|keys[7][1]~36_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[7][1]~36_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~q ), + .datad(\ula_|zx_keyboard_|WideOr16~4_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~37 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[7][1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y10_N25 +dffeas \ula_|zx_keyboard_|keys[7][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][1]~37_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~33 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~33_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & +// (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~33 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[6][1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~34 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~34_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|zx_keyboard_|keys[6][1]~33_combout & \ula_|zx_keyboard_|keys[6][1]~32_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|zx_keyboard_|keys[6][1]~33_combout ), + .datad(\ula_|zx_keyboard_|keys[6][1]~32_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~34 .lut_mask = 16'hC000; +defparam \ula_|zx_keyboard_|keys[6][1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~31 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~31_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|shifted~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~31 .lut_mask = 16'hFCF0; +defparam \ula_|zx_keyboard_|keys[6][1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~35 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~35_combout = (\ula_|zx_keyboard_|keys[6][1]~34_combout & ((!\ula_|zx_keyboard_|keys[6][1]~31_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~34_combout & (\ula_|zx_keyboard_|keys[6][1]~q )) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~34_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[6][1]~q ), + .datad(\ula_|zx_keyboard_|keys[6][1]~31_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~35 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[6][1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y9_N31 +dffeas \ula_|zx_keyboard_|keys[6][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][1]~35_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N28 +cycloneive_lcell_comb \D[1]~32 ( +// Equation(s): +// \D[1]~32_combout = (\ula_|zx_keyboard_|keys[7][1]~q & (\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) # (!\ula_|zx_keyboard_|keys[7][1]~q & +// ((\z80_|address_pins_|abus[14]~22_combout ) # ((!\ula_|zx_keyboard_|keys[6][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~q ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ula_|zx_keyboard_|keys[6][1]~q ), + .datad(\z80_|address_pins_|abus[15]~21_combout ), + .cin(gnd), + .combout(\D[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~32 .lut_mask = 16'hCF45; +defparam \D[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N12 +cycloneive_lcell_comb \D[1]~33 ( +// Equation(s): +// \D[1]~33_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~32_combout & ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~q ), + .datac(\ula_|zx_keyboard_|key_row~0_combout ), + .datad(\D[1]~32_combout ), + .cin(gnd), + .combout(\D[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~33 .lut_mask = 16'hB000; +defparam \D[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~16 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~16_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~16 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[6][4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~17 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~17_combout = (\ula_|zx_keyboard_|keys[6][4]~16_combout & (\ula_|zx_keyboard_|keys[7][4]~15_combout & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~16_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~15_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~17 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[1][1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~18 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~18_combout = (\ula_|zx_keyboard_|keys[1][1]~17_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][1]~17_combout & ((\ula_|zx_keyboard_|keys[1][1]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[1][1]~17_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[1][1]~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~18 .lut_mask = 16'h7272; +defparam \ula_|zx_keyboard_|keys[1][1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y9_N9 +dffeas \ula_|zx_keyboard_|keys[1][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][1]~18_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~12 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~12_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~12 .lut_mask = 16'h0048; +defparam \ula_|zx_keyboard_|keys[0][1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~13 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~13_combout = (\ula_|zx_keyboard_|keys[0][1]~12_combout & ((\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [4] & +// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~13 .lut_mask = 16'h2400; +defparam \ula_|zx_keyboard_|keys[0][1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~10 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~10_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~10 .lut_mask = 16'hF0F3; +defparam \ula_|zx_keyboard_|keys[0][1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~13_combout & ((!\ula_|zx_keyboard_|keys[0][1]~10_combout ))) # (!\ula_|zx_keyboard_|keys[0][1]~13_combout & +// (\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~0_combout ), + .datab(\ula_|zx_keyboard_|keys[0][1]~13_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\ula_|zx_keyboard_|keys[0][1]~10_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y9_N21 +dffeas \ula_|zx_keyboard_|keys[0][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N16 +cycloneive_lcell_comb \D[1]~30 ( +// Equation(s): +// \D[1]~30_combout = (\ula_|zx_keyboard_|keys[1][1]~q & (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|keys[1][1]~q & +// (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[1][1]~q ), + .datab(\ula_|zx_keyboard_|keys[0][1]~q ), + .datac(\z80_|address_pins_|abus[9]~17_combout ), + .datad(\z80_|address_pins_|abus[8]~18_combout ), + .cin(gnd), + .combout(\D[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~30 .lut_mask = 16'hF531; +defparam \D[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~25 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~25 .lut_mask = 16'h3000; +defparam \ula_|zx_keyboard_|keys[3][1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~26 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~26_combout = (\ula_|zx_keyboard_|keys[3][1]~25_combout & ((\ula_|zx_keyboard_|keys[3][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~24_combout & ((\ula_|zx_keyboard_|keys[3][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~25_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][1]~25_combout ), + .datac(\ula_|zx_keyboard_|keys[3][1]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~24_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~26 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N31 +dffeas \ula_|zx_keyboard_|keys[3][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~23 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~23_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~22_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~22_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # +// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[2][1]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~22_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~23 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[2][1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N21 +dffeas \ula_|zx_keyboard_|keys[2][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][1]~23_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N8 +cycloneive_lcell_comb \D[1]~31 ( +// Equation(s): +// \D[1]~31_combout = (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][1]~q )))) # (!\z80_|address_pins_|abus[10]~20_combout & (!\ula_|zx_keyboard_|keys[2][1]~q & +// ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\z80_|address_pins_|abus[10]~20_combout ), + .datab(\z80_|address_pins_|abus[11]~19_combout ), + .datac(\ula_|zx_keyboard_|keys[3][1]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~q ), + .cin(gnd), + .combout(\D[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~31 .lut_mask = 16'h8ACF; +defparam \D[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N6 +cycloneive_lcell_comb \D[1]~34 ( +// Equation(s): +// \D[1]~34_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~33_combout & (\D[1]~30_combout & \D[1]~31_combout ))) + + .dataa(\D[1]~33_combout ), + .datab(\D[1]~30_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[1]~31_combout ), + .cin(gnd), + .combout(\D[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~34 .lut_mask = 16'hF8F0; +defparam \D[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N22 +cycloneive_lcell_comb \D[1]~38 ( +// Equation(s): +// \D[1]~38_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .cin(gnd), + .combout(\D[1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~38 .lut_mask = 16'hE6A2; +defparam \D[1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N4 +cycloneive_lcell_comb \D[1]~39 ( +// Equation(s): +// \D[1]~39_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[1]~38_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\D[1]~38_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\D[1]~38_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datac(\D[1]~38_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .cin(gnd), + .combout(\D[1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~39 .lut_mask = 16'hE5E0; +defparam \D[1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y2_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +// synopsys translate_on + +// Location: M9K_X22_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +// synopsys translate_on + +// Location: M9K_X22_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N24 +cycloneive_lcell_comb \D[1]~35 ( +// Equation(s): +// \D[1]~35_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout & +// (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .cin(gnd), + .combout(\D[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~35 .lut_mask = 16'hEA62; +defparam \D[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N14 +cycloneive_lcell_comb \D[1]~36 ( +// Equation(s): +// \D[1]~36_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout $ (((\D[1]~35_combout ))))) # (!\z80_|address_pins_|abus[15]~21_combout & +// (((\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout & !\D[1]~35_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\D[1]~35_combout ), + .cin(gnd), + .combout(\D[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~36 .lut_mask = 16'h44B8; +defparam \D[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N0 +cycloneive_lcell_comb \D[1]~37 ( +// Equation(s): +// \D[1]~37_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[1]~35_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[1]~36_combout & ((!\D[1]~35_combout ))) # (!\D[1]~36_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout & \D[1]~35_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datac(\D[1]~36_combout ), + .datad(\D[1]~35_combout ), + .cin(gnd), + .combout(\D[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~37 .lut_mask = 16'hAE50; +defparam \D[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N20 +cycloneive_lcell_comb \D[1]~118 ( +// Equation(s): +// \D[1]~118_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[1]~39_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[1]~37_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[1]~39_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\D[1]~39_combout ), + .datad(\D[1]~37_combout ), + .cin(gnd), + .combout(\D[1]~118_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~118 .lut_mask = 16'hF4B0; +defparam \D[1]~118 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N2 +cycloneive_lcell_comb \D[1]~40 ( +// Equation(s): +// \D[1]~40_combout = ((\Equal2~0_combout & (\D[1]~34_combout )) # (!\Equal2~0_combout & ((\D[1]~118_combout )))) # (!\Equal2~1_combout ) + + .dataa(\D[1]~34_combout ), + .datab(\Equal2~0_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[1]~118_combout ), + .cin(gnd), + .combout(\D[1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~40 .lut_mask = 16'hBF8F; +defparam \D[1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N12 +cycloneive_lcell_comb \D[1]~41 ( +// Equation(s): +// \D[1]~41_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~40_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[1]~40_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [1]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[1]~40_combout ), + .cin(gnd), + .combout(\D[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~41 .lut_mask = 16'hAF03; +defparam \D[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N28 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\D[1]~41_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[1]~11_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[1]~41_combout & +// (((\z80_|bus_control_|db[1]~11_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) + + .dataa(\D[1]~41_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|bus_control_|db[1]~11_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N29 +dffeas \z80_|data_pins_|dout[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N8 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~11 ( +// Equation(s): +// \z80_|bus_control_|db[1]~11_combout = ((\z80_|bus_control_|db[1]~10_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[1]~10_combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\z80_|bus_control_|db[0]~6_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'h8FAF; +defparam \z80_|bus_control_|db[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N9 +dffeas \z80_|ir_|opcode[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[1]~11_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_ed_set~combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|pla_decode_|Equal2~1_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y7_N29 +dffeas \z80_|decode_state_|DFFE_instED ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instED~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; +defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~8_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~8_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFAEA; +defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~8_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h00C8; +defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~6_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC888; +defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~6_combout = (\z80_|execute_|ctl_bus_db_we~4_combout ) # (((!\z80_|execute_|ctl_sw_2u~3_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) + + .dataa(\z80_|execute_|ctl_bus_db_we~4_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~2_combout ) # ((\z80_|execute_|ctl_bus_db_we~3_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # (\z80_|execute_|ctl_bus_db_we~6_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~2_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~3_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~126 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~126_combout = (\ula_|zx_keyboard_|keys[6][4]~16_combout & ((\ula_|zx_keyboard_|keys[6][4]~44_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~44_combout & ((\ula_|zx_keyboard_|keys[6][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~16_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~16_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~44_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~126_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~126 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[6][4]~126 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y9_N1 +dffeas \ula_|zx_keyboard_|keys[6][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][4]~126_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~125 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~125_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) +// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|shifted~1_combout ), + .datac(\ula_|zx_keyboard_|keys[7][4]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~125_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~125 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[7][4]~125 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N11 +dffeas \ula_|zx_keyboard_|keys[7][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][4]~125_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N16 +cycloneive_lcell_comb \D[4]~88 ( +// Equation(s): +// \D[4]~88_combout = (\ula_|zx_keyboard_|keys[6][4]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][4]~q )))) # (!\ula_|zx_keyboard_|keys[6][4]~q & +// (((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~q ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[15]~21_combout ), + .datad(\ula_|zx_keyboard_|keys[7][4]~q ), + .cin(gnd), + .combout(\D[4]~88_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~88 .lut_mask = 16'hD0DD; +defparam \D[4]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~120 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~120_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~120_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~120 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[5][4]~120 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~121 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~121_combout = (\ula_|zx_keyboard_|keys[6][4]~44_combout & ((\ula_|zx_keyboard_|keys[5][4]~120_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~120_combout & (\ula_|zx_keyboard_|keys[5][4]~q +// )))) # (!\ula_|zx_keyboard_|keys[6][4]~44_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~44_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~120_combout ), + .datac(\ula_|zx_keyboard_|keys[5][4]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~121_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~121 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][4]~121 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y9_N31 +dffeas \ula_|zx_keyboard_|keys[5][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][4]~121_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~122 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q )) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & +// \ula_|zx_keyboard_|extended~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~122_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~122 .lut_mask = 16'h300C; +defparam \ula_|zx_keyboard_|keys[4][4]~122 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~123 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~123_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[4][4]~122_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[4][4]~122_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~123_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~123 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][4]~123 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & ((\ula_|zx_keyboard_|keys[4][4]~123_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~123_combout & ((\ula_|zx_keyboard_|keys[4][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .datac(\ula_|zx_keyboard_|keys[4][4]~q ), + .datad(\ula_|zx_keyboard_|keys[4][4]~123_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y9_N9 +dffeas \ula_|zx_keyboard_|keys[4][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N28 +cycloneive_lcell_comb \D[4]~87 ( +// Equation(s): +// \D[4]~87_combout = (\z80_|address_pins_|abus[12]~24_combout & ((\z80_|address_pins_|abus[13]~23_combout ) # ((!\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\z80_|address_pins_|abus[12]~24_combout & (!\ula_|zx_keyboard_|keys[4][4]~q & +// ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\z80_|address_pins_|abus[12]~24_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[5][4]~q ), + .datad(\ula_|zx_keyboard_|keys[4][4]~q ), + .cin(gnd), + .combout(\D[4]~87_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~87 .lut_mask = 16'h8ACF; +defparam \D[4]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~115 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~115_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [5] & +// (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~115_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~115 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[2][4]~115 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~116 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~116_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[2][4]~115_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[2][4]~115_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~116_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~116 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[2][4]~116 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~117 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~117_combout = (\ula_|zx_keyboard_|keys[2][4]~116_combout & (!\ula_|zx_keyboard_|keys[2][4]~93_combout )) # (!\ula_|zx_keyboard_|keys[2][4]~116_combout & ((\ula_|zx_keyboard_|keys[2][4]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[2][4]~93_combout ), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~116_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~117_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~117 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[2][4]~117 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y8_N25 +dffeas \ula_|zx_keyboard_|keys[2][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][4]~117_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][4]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [10]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[2][4]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hDDFF; +defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~118 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~118_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~118_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~118 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|keys[3][4]~118 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~131 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~131_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[3][4]~118_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[3][4]~118_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~131_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~131 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[3][4]~131 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~119 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~119_combout = (\ula_|zx_keyboard_|keys[3][4]~127_combout & ((\ula_|zx_keyboard_|keys[3][4]~131_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~131_combout & ((\ula_|zx_keyboard_|keys[3][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~127_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][4]~127_combout ), + .datac(\ula_|zx_keyboard_|keys[3][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~131_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~119_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~119 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][4]~119 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N21 +dffeas \ula_|zx_keyboard_|keys[3][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][4]~119_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~114 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~114_combout = (\ula_|zx_keyboard_|keys[0][4]~95_combout & ((\ula_|zx_keyboard_|keys[3][1]~25_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[3][1]~25_combout & +// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .datac(\ula_|zx_keyboard_|keys[0][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~25_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~114_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~114 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[0][4]~114 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y8_N21 +dffeas \ula_|zx_keyboard_|keys[0][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][4]~114_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~113 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~113_combout = (\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~21_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][4]~21_combout & ((\ula_|zx_keyboard_|keys[1][4]~q ))))) # +// (!\ula_|zx_keyboard_|Equal0~2_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|Equal0~2_combout ), + .datac(\ula_|zx_keyboard_|keys[1][4]~q ), + .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~113_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~113 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[1][4]~113 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y8_N15 +dffeas \ula_|zx_keyboard_|keys[1][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][4]~113_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N6 +cycloneive_lcell_comb \D[4]~85 ( +// Equation(s): +// \D[4]~85_combout = (\z80_|address_pins_|abus[9]~17_combout & (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~q ))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][4]~q & +// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\z80_|address_pins_|abus[9]~17_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~q ), + .datac(\z80_|address_pins_|abus[8]~18_combout ), + .datad(\ula_|zx_keyboard_|keys[1][4]~q ), + .cin(gnd), + .combout(\D[4]~85_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~85 .lut_mask = 16'hA2F3; +defparam \D[4]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y11_N20 +cycloneive_lcell_comb \D[4]~86 ( +// Equation(s): +// \D[4]~86_combout = (\ula_|zx_keyboard_|key_row~3_combout & (\D[4]~85_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][4]~q )))) + + .dataa(\ula_|zx_keyboard_|key_row~3_combout ), + .datab(\z80_|address_pins_|abus[11]~19_combout ), + .datac(\ula_|zx_keyboard_|keys[3][4]~q ), + .datad(\D[4]~85_combout ), + .cin(gnd), + .combout(\D[4]~86_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~86 .lut_mask = 16'h8A00; +defparam \D[4]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N24 +cycloneive_lcell_comb \D[4]~89 ( +// Equation(s): +// \D[4]~89_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~88_combout & (\D[4]~87_combout & \D[4]~86_combout ))) + + .dataa(\D[4]~88_combout ), + .datab(\D[4]~87_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[4]~86_combout ), + .cin(gnd), + .combout(\D[4]~89_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~89 .lut_mask = 16'hF8F0; +defparam \D[4]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N18 +cycloneive_lcell_comb \D[4]~93 ( +// Equation(s): +// \D[4]~93_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), + .cin(gnd), + .combout(\D[4]~93_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~93 .lut_mask = 16'hF838; +defparam \D[4]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N4 +cycloneive_lcell_comb \D[4]~94 ( +// Equation(s): +// \D[4]~94_combout = (\D[4]~93_combout & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )))) # (!\D[4]~93_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datab(\D[4]~93_combout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), + .cin(gnd), + .combout(\D[4]~94_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~94 .lut_mask = 16'hCEC2; +defparam \D[4]~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y22_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X22_Y21_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y33_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N8 +cycloneive_lcell_comb \D[4]~90 ( +// Equation(s): +// \D[4]~90_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .cin(gnd), + .combout(\D[4]~90_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~90 .lut_mask = 16'hE6A2; +defparam \D[4]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y30_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N22 +cycloneive_lcell_comb \D[4]~91 ( +// Equation(s): +// \D[4]~91_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout $ ((\D[4]~90_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[4]~90_combout & +// \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\D[4]~90_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .cin(gnd), + .combout(\D[4]~91_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~91 .lut_mask = 16'h4B48; +defparam \D[4]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N28 +cycloneive_lcell_comb \D[4]~92 ( +// Equation(s): +// \D[4]~92_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[4]~90_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[4]~90_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout & !\D[4]~91_combout )) # (!\D[4]~90_combout & ((\D[4]~91_combout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[4]~90_combout ), + .datad(\D[4]~91_combout ), + .cin(gnd), + .combout(\D[4]~92_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~92 .lut_mask = 16'hC3E0; +defparam \D[4]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N8 +cycloneive_lcell_comb \D[4]~125 ( +// Equation(s): +// \D[4]~125_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\D[4]~94_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\D[4]~92_combout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (((\D[4]~94_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\D[4]~94_combout ), + .datad(\D[4]~92_combout ), + .cin(gnd), + .combout(\D[4]~125_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~125 .lut_mask = 16'hF2D0; +defparam \D[4]~125 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N30 +cycloneive_lcell_comb \D[4]~110 ( +// Equation(s): +// \D[4]~110_combout = ((\Equal2~0_combout & (\D[4]~89_combout )) # (!\Equal2~0_combout & ((\D[4]~125_combout )))) # (!\Equal2~1_combout ) + + .dataa(\D[4]~89_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[4]~125_combout ), + .datad(\Equal2~1_combout ), + .cin(gnd), + .combout(\D[4]~110_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~110 .lut_mask = 16'hB8FF; +defparam \D[4]~110 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N4 +cycloneive_lcell_comb \D[4]~111 ( +// Equation(s): +// \D[4]~111_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[4]~110_combout & \z80_|data_pins_|dout [4])))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[4]~110_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[4]~110_combout ), + .datad(\z80_|data_pins_|dout [4]), + .cin(gnd), + .combout(\D[4]~111_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~111 .lut_mask = 16'hF151; +defparam \D[4]~111 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N10 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\D[4]~111_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[4]~19_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[4]~111_combout & +// (((\z80_|bus_control_|db[4]~19_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) + + .dataa(\D[4]~111_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|bus_control_|db[4]~19_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N11 +dffeas \z80_|data_pins_|dout[4] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N18 +cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( +// Equation(s): +// \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|data_pins_|dout [4]), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[0]~4_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'hBB00; +defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N6 +cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( +// Equation(s): +// \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[4]~18_combout ), + .datac(\z80_|alu_control_|db[4]~33_combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[4]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hC4FF; +defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N23 +dffeas \z80_|ir_|opcode[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[4]~19_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal32~0_combout = (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal32~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N26 +cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( +// Equation(s): +// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal36~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal43~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal36~0_combout ), + .datab(\z80_|pla_decode_|Equal3~2_combout ), + .datac(\z80_|pla_decode_|Equal79~0_combout ), + .datad(\z80_|pla_decode_|Equal43~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|test1~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; +defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N30 +cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( +// Equation(s): +// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~53_combout & (((\z80_|interrupts_|test1~2_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|interrupts_|test1~2_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|setM1~53_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|test1~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h00FD; +defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N7 +dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|interrupts_|nmi_armed~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|interrupts_|test1~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N16 +cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( +// Equation(s): +// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hF8FC; +defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_flags_alu~19_combout ) # ((\z80_|alu_control_|db[5]~17_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_high[1]~19_combout & +// (((\z80_|alu_control_|db[5]~17_combout & \z80_|execute_|ctl_flags_bus~combout )))) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_flags_alu~19_combout ), + .datac(\z80_|alu_control_|db[5]~17_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N3 +dffeas \z80_|alu_flags_|flags_yf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_yf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_yf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N18 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( +// Equation(s): +// \z80_|alu_control_|db[5]~15_combout = (\z80_|alu_control_|out[6]~2_combout & (((\z80_|alu_flags_|flags_yf~q )) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_control_|out[6]~2_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & +// ((\z80_|alu_flags_|flags_yf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_control_|out[6]~2_combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_flags_|flags_yf~q ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hF3A2; +defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N12 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~16 ( +// Equation(s): +// \z80_|alu_control_|db[5]~16_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~15_combout & ((\z80_|reg_file_|gdfx_temp0[5]~71_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|sw1_|db_down[5]~0_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .datad(\z80_|alu_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~16 .lut_mask = 16'hA200; +defparam \z80_|alu_control_|db[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~17 ( +// Equation(s): +// \z80_|alu_control_|db[5]~17_combout = ((\z80_|alu_control_|db[5]~16_combout & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_control_|db[5]~16_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_control_|db[6]~13_combout ), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~17 .lut_mask = 16'hAF2F; +defparam \z80_|alu_control_|db[5]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y33_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; +// synopsys translate_on + +// Location: M9K_X33_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80000001C000000160F000FF70C0007F78C00000F05001007870010010000000000800000038000000F000000070000000300000006000000000000040000000F00000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000001D108000BEDA9FA9698A000000000000000000000000FFFFFFFF408102048004188297E014DA9FA9E9CA00000000000000000000000000000000FFFFFFFC800400CA972208DA9FA9CD8E00000000000000000000000000000000FFFFFFFC8004046A97A289FA9FA9CDC20000000000000000000000007FFFFFFC8000000280040E2A97A2997A9DA9CFC20000000000000000000000007FFFFFFE8000000280042EB28002BE369DA9274200000000000000000000000040810206BFFFFFFE9FE430A29D82AC3E8009E34A000000000000000000000000000000023FFFFFFC9FE4B1829FA2800E8009436A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h9FE8334E88F827C697F88D1600A80A44809E8FC2B86999C2B85B3A82B1D32A869FE8336A88F807CA97F88F96A0A80EC2838E8D42B9E98FC2B86B3B82B0D7B2D2800832E288F827CA97F88B82A0080EC683869542B939B8C2B1AB0F8290B730C2800826EA8878078297F88AD2A0280EC283E694C2B83A3BC2A3AB3E8291A316AA800826EE881807C69DE8ABD6A0280BC282209CD2BA2A3D42A2737F82918314E2800806E6981805C69D48AED6A1E80BCA82709FC2BB223DC2A07B7F8295DF11C2800886E6980805869848AAC6A1E42DC281789DC2BBAA3DC6A02B7582955F00928008A6EE98082D9618088AC8A0F40FC289E89DC2BBCA3DC2A18B7782154F02F0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y6_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'hE10F8B8C100323720BEBBDEBB81DF13FF97B252E2CB4F27BA091FBD0002D1A611E1EDBBC716D44D2912B80041C44558060CFCF15955C0D780DD5E71393920844F25E16C87C5D0308EEC52C011514BBC13AFA1028924D0C7CE738105BD47A10AA5B5C1D9D4193E4339F492B0E1A64E13AE35BE6B67AC8057BDACC155F14E906A017A1841358335450D4B26CD2A21B3D8F2211080B81EC040D7FA0B51CD48008112508062020A02490900092D2040259108806A328F4006D2AA514B42FB006ECCCCB9A360865678449975A8AE72B5C0F7BA800C1B5DC55D7D6FE2EF4EED85D00AB111821321BA426A4FE4956B43595832C271E83E060341AE5F2023FC808177383; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h1A2955372D510AC266A5445146E27000020C320FAE1557E37154040A13202DC6F40B840FB9A59B6DBB296562CB6220EFBE99D2776A202044D9101006FD221D305519198C859000004012AFF4FB060307C92BB732203BFDFEFFFFFFDFFF87FCFFFBFFEFF03FFE0FFFBFAFE0FF80787FFF7FFF83F7F87003FFBFFFFBFFFBFF0FFC0FF81FFF7FFBFFDFFFBFFFE1FF0086F3141AAB6005810A0621595A893F9D85983B9254954341968BAC8C141C90938C05B2C9CD267E11650407375FEDD6A2FEB346AAF6CFDC0791AA97B741995A3B3981E06D1A44D3711955197BB9910FCA20744915C84D6C24BAF53929814CA8A4697E8F4201145AE7415DC122A5F010436107; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h02E84F969E3C800AC610D276182020227809001A50DDDBA3487BB6AE802BA06509312DA0E620656EAF24D57C08FFB14D289613DC32083803B84DC6415FD5EDC000300A8D128FA20030ACCBAFA237B7024504D36A4BA26081137F059E78991154FE2AC2A884A8CC7FBBB21C851CC92B12E15593C0C020FFEE066558590E882D5B67459F1A8C3240FE4E6A8D028C0C088FCF471D400A19B38211004DD122212288B111114514CB11840E04828849C621392041163C00808C67223422F00110201DD18FCFFFF3FFE7F9FFFFFFF82C0B422D214711E08904524A069491774E663F48F665955B4E2C63DAC0078652D10120900298F7EE380092442AFD400BEC43C003; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N2 +cycloneive_lcell_comb \Mux2~0 ( +// Equation(s): +// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~22_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .cin(gnd), + .combout(\Mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux2~0 .lut_mask = 16'hB9A8; +defparam \Mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N24 +cycloneive_lcell_comb \Mux2~1 ( +// Equation(s): +// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datad(\Mux2~0_combout ), + .cin(gnd), + .combout(\Mux2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Mux2~1 .lut_mask = 16'hBBC0; +defparam \Mux2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y2_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # +// (\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout & +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 .lut_mask = 16'hCEC2; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 .lut_mask = 16'hBCB0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N30 +cycloneive_lcell_comb \D[5]~112 ( +// Equation(s): +// \D[5]~112_combout = ((\z80_|address_pins_|abus[15]~21_combout & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ))) # (!\z80_|address_pins_|abus[15]~21_combout & (\Mux2~1_combout ))) # (!\D[5]~97_combout ) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\D[5]~97_combout ), + .datac(\Mux2~1_combout ), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .cin(gnd), + .combout(\D[5]~112_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~112 .lut_mask = 16'hFB73; +defparam \D[5]~112 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N8 +cycloneive_lcell_comb \D[5]~113 ( +// Equation(s): +// \D[5]~113_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[5]~112_combout & \z80_|data_pins_|dout [5])))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[5]~112_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[5]~112_combout ), + .datad(\z80_|data_pins_|dout [5]), + .cin(gnd), + .combout(\D[5]~113_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~113 .lut_mask = 16'hF151; +defparam \D[5]~113 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N24 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|bus_control_|db[5]~15_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[5]~113_combout )))) # (!\z80_|bus_control_|db[5]~15_combout & +// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[5]~113_combout )))) + + .dataa(\z80_|bus_control_|db[5]~15_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\D[5]~113_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N25 +dffeas \z80_|data_pins_|dout[5] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N20 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( +// Equation(s): +// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(gnd), + .datab(\z80_|data_pins_|dout [5]), + .datac(\z80_|bus_control_|db[0]~4_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hC0F0; +defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( +// Equation(s): +// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~17_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|alu_control_|db[5]~17_combout ), + .datab(\z80_|bus_control_|db[0]~6_combout ), + .datac(\z80_|bus_control_|db[5]~14_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hB3F3; +defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N25 +dffeas \z80_|ir_|opcode[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[5]~15_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~11_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~46 ( +// Equation(s): +// \z80_|execute_|setM1~46_combout = (!\z80_|execute_|ctl_mRead~11_combout & (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_iorw~10_combout & \z80_|execute_|ctl_mRead~17_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|ctl_iorw~11_combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|execute_|ctl_mRead~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~46 .lut_mask = 16'h0100; +defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~40 ( +// Equation(s): +// \z80_|execute_|setM1~40_combout = (!\z80_|execute_|ctl_mWrite~7_combout & \z80_|execute_|setM1~39_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|setM1~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~40 .lut_mask = 16'h0F00; +defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|nextM~5 ( +// Equation(s): +// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|setM1~40_combout )) # (!\z80_|execute_|setM1~46_combout ))) + + .dataa(\z80_|execute_|setM1~46_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|setM1~40_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~5 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|nextM~6 ( +// Equation(s): +// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|nextM~3_combout ) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|nextM~3_combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|execute_|ixy_d~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~6 .lut_mask = 16'hB3FF; +defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|nextM~7 ( +// Equation(s): +// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~8_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|nextM~6_combout ), + .datac(\z80_|execute_|ixy_d~8_combout ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~7 .lut_mask = 16'hC8FF; +defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|nextM~9 ( +// Equation(s): +// \z80_|execute_|nextM~9_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~9 .lut_mask = 16'hE000; +defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|nextM~10 ( +// Equation(s): +// \z80_|execute_|nextM~10_combout = (\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ctl_mRead~34_combout ))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|nextM~9_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~8 ( +// Equation(s): +// \z80_|execute_|nextM~8_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ixy_d~8_combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ixy_d~8_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~8 .lut_mask = 16'h2F22; +defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|nextM~12 ( +// Equation(s): +// \z80_|execute_|nextM~12_combout = (\z80_|execute_|ctl_alu_op_low~21_combout ) # (((\z80_|execute_|nextM~10_combout ) # (\z80_|execute_|nextM~8_combout )) # (!\z80_|execute_|nextM~11_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~21_combout ), + .datab(\z80_|execute_|nextM~11_combout ), + .datac(\z80_|execute_|nextM~10_combout ), + .datad(\z80_|execute_|nextM~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|nextM~15 ( +// Equation(s): +// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|fMRead~12_combout )))) + + .dataa(\z80_|execute_|fMRead~12_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~15 .lut_mask = 16'hC040; +defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|nextM~13 ( +// Equation(s): +// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~7_combout ) # ((\z80_|execute_|nextM~12_combout ) # (\z80_|execute_|nextM~15_combout )) + + .dataa(\z80_|execute_|nextM~7_combout ), + .datab(\z80_|execute_|nextM~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~14 ( +// Equation(s): +// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~5_combout ) # ((\z80_|execute_|nextM~13_combout ) # ((!\z80_|execute_|ctl_mWrite~14_combout ) # (!\z80_|execute_|ctl_mRead~28_combout ))) + + .dataa(\z80_|execute_|nextM~5_combout ), + .datab(\z80_|execute_|nextM~13_combout ), + .datac(\z80_|execute_|ctl_mRead~28_combout ), + .datad(\z80_|execute_|ctl_mWrite~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~14 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N22 +cycloneive_lcell_comb \z80_|sequencer_|ena_M ( +// Equation(s): +// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|ena_M~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; +defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N23 +dffeas \z80_|sequencer_|DFFE_T1_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|ena_M~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T1_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N26 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0050; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N27 +dffeas \z80_|sequencer_|DFFE_T2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T2_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N30 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N31 +dffeas \z80_|sequencer_|DFFE_T3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T3_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N20 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N21 +dffeas \z80_|sequencer_|DFFE_T4_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T4_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~9_combout & (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|execute_|ctl_mWrite~9_combout & (((!\z80_|execute_|ctl_mWrite~5_combout ) # +// (!\z80_|execute_|ctl_ir_we~12_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0757; +defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~54 ( +// Equation(s): +// \z80_|execute_|setM1~54_combout = ((\z80_|execute_|ctl_iorw~11_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_iorw~11_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~54 .lut_mask = 16'hD555; +defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~25 ( +// Equation(s): +// \z80_|execute_|setM1~25_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_mRead~10_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~25 .lut_mask = 16'h2F22; +defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~26 ( +// Equation(s): +// \z80_|execute_|setM1~26_combout = (\z80_|execute_|ctl_mRead~11_combout ) # (((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~26 .lut_mask = 16'hDCFF; +defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~27 ( +// Equation(s): +// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~26_combout ) # (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|execute_|setM1~26_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~27 .lut_mask = 16'hECFF; +defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~22 ( +// Equation(s): +// \z80_|execute_|setM1~22_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~22 .lut_mask = 16'hFF04; +defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~55 ( +// Equation(s): +// \z80_|execute_|setM1~55_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|execute_|setM1~22_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|setM1~22_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~55 .lut_mask = 16'hF080; +defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~23 ( +// Equation(s): +// \z80_|execute_|setM1~23_combout = (\z80_|execute_|fMWrite~0_combout & (!\z80_|execute_|ctl_mRead~8_combout & (\z80_|execute_|fMWrite~6_combout & !\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|fMWrite~0_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|fMWrite~6_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~23 .lut_mask = 16'h0020; +defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~24 ( +// Equation(s): +// \z80_|execute_|setM1~24_combout = (\z80_|execute_|setM1~55_combout & (((\z80_|execute_|ctl_reg_in_hi~2_combout & !\z80_|execute_|setM1~23_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|setM1~55_combout & +// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|execute_|setM1~23_combout )))) + + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|setM1~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~24 .lut_mask = 16'h0ACE; +defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~28 ( +// Equation(s): +// \z80_|execute_|setM1~28_combout = (\z80_|execute_|setM1~25_combout ) # ((\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|setM1~27_combout & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|setM1~25_combout ), + .datab(\z80_|execute_|setM1~27_combout ), + .datac(\z80_|execute_|setM1~24_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~11 ( +// Equation(s): +// \z80_|execute_|setM1~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~11 .lut_mask = 16'hFF04; +defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~33 ( +// Equation(s): +// \z80_|execute_|setM1~33_combout = (\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mRead~2_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|setM1~11_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|setM1~11_combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~29 ( +// Equation(s): +// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~5_combout ) # (((\z80_|execute_|ctl_mRead~13_combout ) # (\z80_|execute_|ctl_mRead~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~29 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~31 ( +// Equation(s): +// \z80_|execute_|setM1~31_combout = (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~30_combout )) # (!\z80_|execute_|setM1~56_combout ) + + .dataa(\z80_|execute_|setM1~56_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|setM1~29_combout ), + .datad(\z80_|execute_|setM1~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~31 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~32 ( +// Equation(s): +// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~16_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & +// (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~32 .lut_mask = 16'hECA0; +defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~34 ( +// Equation(s): +// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~32_combout ) # ((\z80_|execute_|setM1~33_combout & \z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|setM1~33_combout ), + .datab(\z80_|execute_|setM1~31_combout ), + .datac(\z80_|execute_|setM1~32_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~20 ( +// Equation(s): +// \z80_|execute_|setM1~20_combout = (\z80_|execute_|ctl_mRead~9_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_flags_bus~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~20 .lut_mask = 16'h20F0; +defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~21 ( +// Equation(s): +// \z80_|execute_|setM1~21_combout = (\z80_|execute_|setM1~20_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & (\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|ixy_d~8_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|setM1~20_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~21 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~35 ( +// Equation(s): +// \z80_|execute_|setM1~35_combout = (\z80_|execute_|setM1~54_combout ) # ((\z80_|execute_|setM1~28_combout ) # ((\z80_|execute_|setM1~34_combout ) # (\z80_|execute_|setM1~21_combout ))) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(\z80_|execute_|setM1~28_combout ), + .datac(\z80_|execute_|setM1~34_combout ), + .datad(\z80_|execute_|setM1~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~35 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~15 ( +// Equation(s): +// \z80_|execute_|setM1~15_combout = (\z80_|pla_decode_|Equal21~2_combout & (!\z80_|pla_decode_|Equal32~0_combout & ((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )))) # (!\z80_|pla_decode_|Equal21~2_combout & +// (((!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~2_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~15 .lut_mask = 16'h153F; +defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~14 ( +// Equation(s): +// \z80_|execute_|setM1~14_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|execute_|ctl_alu_oe~3_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal77~1_combout ), + .datac(\z80_|pla_decode_|Equal1~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~14 .lut_mask = 16'h0003; +defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~16 ( +// Equation(s): +// \z80_|execute_|setM1~16_combout = (\z80_|interrupts_|test1~2_combout & (\z80_|execute_|setM1~15_combout & (\z80_|execute_|setM1~14_combout & !\z80_|pla_decode_|Equal2~2_combout ))) + + .dataa(\z80_|interrupts_|test1~2_combout ), + .datab(\z80_|execute_|setM1~15_combout ), + .datac(\z80_|execute_|setM1~14_combout ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0080; +defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~10 ( +// Equation(s): +// \z80_|execute_|setM1~10_combout = (\z80_|pla_decode_|Equal6~1_combout ) # (((\z80_|execute_|ctl_mWrite~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|fMWrite~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|fMWrite~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~12 ( +// Equation(s): +// \z80_|execute_|setM1~12_combout = ((\z80_|execute_|setM1~10_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout & \z80_|execute_|setM1~11_combout ))) # (!\z80_|execute_|nextM~2_combout ) + + .dataa(\z80_|execute_|nextM~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|setM1~11_combout ), + .datad(\z80_|execute_|setM1~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~12 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~8 ( +// Equation(s): +// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_al_we~13_combout & (((\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & +// \z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~8 .lut_mask = 16'hF444; +defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~9 ( +// Equation(s): +// \z80_|execute_|setM1~9_combout = ((\z80_|execute_|setM1~8_combout & \z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|execute_|ctl_flags_xy_we~17_combout ) + + .dataa(\z80_|execute_|setM1~8_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~9 .lut_mask = 16'hA0FF; +defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~13 ( +// Equation(s): +// \z80_|execute_|setM1~13_combout = ((\z80_|execute_|setM1~9_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|setM1~12_combout ))) # (!\z80_|reg_control_|reg_sel_pc~3_combout ) + + .dataa(\z80_|reg_control_|reg_sel_pc~3_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|setM1~12_combout ), + .datad(\z80_|execute_|setM1~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~13 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~18 ( +// Equation(s): +// \z80_|execute_|setM1~18_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|execute_|setM1~17_combout & (\z80_|execute_|ctl_alu_op_low~38_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|setM1~17_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~18 .lut_mask = 16'h0040; +defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~19 ( +// Equation(s): +// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~13_combout ) # (((!\z80_|execute_|setM1~16_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|setM1~18_combout )) + + .dataa(\z80_|execute_|setM1~16_combout ), + .datab(\z80_|execute_|setM1~13_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|setM1~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~19 .lut_mask = 16'hDCFF; +defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~43 ( +// Equation(s): +// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|pla_decode_|Equal37~0_combout & !\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0004; +defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~42 ( +// Equation(s): +// \z80_|execute_|setM1~42_combout = (!\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout )) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|setM1~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0101; +defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~44 ( +// Equation(s): +// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~42_combout & !\z80_|pla_decode_|Equal48~0_combout ))) + + .dataa(\z80_|execute_|setM1~43_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|setM1~42_combout ), + .datad(\z80_|pla_decode_|Equal48~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~44 .lut_mask = 16'h0020; +defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~45 ( +// Equation(s): +// \z80_|execute_|setM1~45_combout = (\z80_|execute_|setM1~41_combout & (\z80_|execute_|setM1~44_combout & ((!\z80_|pla_decode_|Equal1~4_combout ) # (!\z80_|pla_decode_|Equal2~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal2~1_combout ), + .datab(\z80_|execute_|setM1~41_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|execute_|setM1~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~45 .lut_mask = 16'h4C00; +defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~51 ( +// Equation(s): +// \z80_|execute_|setM1~51_combout = (\z80_|execute_|setM1~45_combout & (\z80_|execute_|setM1~47_combout & (\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~16_combout ))) + + .dataa(\z80_|execute_|setM1~45_combout ), + .datab(\z80_|execute_|setM1~47_combout ), + .datac(\z80_|execute_|setM1~50_combout ), + .datad(\z80_|execute_|setM1~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~51 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N18 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N19 +dffeas \z80_|sequencer_|T6 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|T6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|T6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~52 ( +// Equation(s): +// \z80_|execute_|setM1~52_combout = (\z80_|execute_|setM1~51_combout & ((\z80_|execute_|setM1~40_combout ) # ((\z80_|sequencer_|T6~q & !\z80_|execute_|setM1~41_combout )))) # (!\z80_|execute_|setM1~51_combout & (\z80_|sequencer_|T6~q & +// (!\z80_|execute_|setM1~41_combout ))) + + .dataa(\z80_|execute_|setM1~51_combout ), + .datab(\z80_|sequencer_|T6~q ), + .datac(\z80_|execute_|setM1~41_combout ), + .datad(\z80_|execute_|setM1~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~52 .lut_mask = 16'hAE0C; +defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~53 ( +// Equation(s): +// \z80_|execute_|setM1~53_combout = (!\z80_|execute_|setM1~35_combout & (!\z80_|execute_|setM1~19_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~52_combout )))) + + .dataa(\z80_|execute_|setM1~35_combout ), + .datab(\z80_|execute_|setM1~19_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|setM1~52_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~53 .lut_mask = 16'h1011; +defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N14 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hCCC0; +defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N15 +dffeas \z80_|sequencer_|DFFE_M1_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M1_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N28 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h44C0; +defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N29 +dffeas \z80_|sequencer_|DFFE_M2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M2_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h0F0C; +defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N28 cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( // Equation(s): -// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_apin_mux~1_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) +// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_apin_mux~1_combout ), - .datac(\z80_|execute_|ctl_inc_dec~6_combout ), - .datad(gnd), + .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_dec~6_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_apin_mux~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'h8F8F; +defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'h88FF; defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y16_N18 +// Location: LCCOMB_X28_Y16_N20 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[0]~0 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [0]))) @@ -53232,7 +53700,7 @@ defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hDD88; defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y16_N19 +// Location: FF_X28_Y16_N21 dffeas \z80_|address_pins_|DFFE_apin_latch[0] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), @@ -53251,228 +53719,332 @@ defparam \z80_|address_pins_|DFFE_apin_latch[0] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N12 -cycloneive_lcell_comb \D[0]~59 ( +// Location: LCCOMB_X24_Y15_N30 +cycloneive_lcell_comb \D[0]~66 ( // Equation(s): -// \D[0]~59_combout = (\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout ))) - - .dataa(\Equal2~0_combout ), - .datab(\D[0]~51_combout ), - .datac(\D[0]~106_combout ), - .datad(gnd), - .cin(gnd), - .combout(\D[0]~59_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~59 .lut_mask = 16'hD8D8; -defparam \D[0]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N8 -cycloneive_lcell_comb \D[0]~60 ( -// Equation(s): -// \D[0]~60_combout = (\Equal2~1_combout & (\D[0]~59_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [0]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [0]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[0]~59_combout ), - .cin(gnd), - .combout(\D[0]~60_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~60 .lut_mask = 16'hCF45; -defparam \D[0]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y18_N20 -cycloneive_lcell_comb \D[1]~61 ( -// Equation(s): -// \D[1]~61_combout = (\Equal2~0_combout & (\D[1]~32_combout )) # (!\Equal2~0_combout & ((\D[1]~103_combout ))) - - .dataa(\Equal2~0_combout ), - .datab(gnd), - .datac(\D[1]~32_combout ), - .datad(\D[1]~103_combout ), - .cin(gnd), - .combout(\D[1]~61_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~61 .lut_mask = 16'hF5A0; -defparam \D[1]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y18_N22 -cycloneive_lcell_comb \D[1]~62 ( -// Equation(s): -// \D[1]~62_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~61_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~61_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [1]), - .datad(\D[1]~61_combout ), - .cin(gnd), - .combout(\D[1]~62_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~62 .lut_mask = 16'hF531; -defparam \D[1]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N12 -cycloneive_lcell_comb \D[2]~63 ( -// Equation(s): -// \D[2]~63_combout = (\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout ))) - - .dataa(\Equal2~0_combout ), - .datab(gnd), - .datac(\D[2]~104_combout ), - .datad(\D[2]~105_combout ), - .cin(gnd), - .combout(\D[2]~63_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~63 .lut_mask = 16'hF5A0; -defparam \D[2]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N26 -cycloneive_lcell_comb \D[2]~64 ( -// Equation(s): -// \D[2]~64_combout = (\z80_|data_pins_|dout [2] & (((\D[2]~63_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [2] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[2]~63_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [2]), - .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[2]~63_combout ), - .cin(gnd), - .combout(\D[2]~64_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~64 .lut_mask = 16'hAF23; -defparam \D[2]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N2 -cycloneive_lcell_comb \D[3]~75 ( -// Equation(s): -// \D[3]~75_combout = (\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout ))) - - .dataa(\D[3]~69_combout ), - .datab(gnd), - .datac(\Equal2~0_combout ), - .datad(\D[3]~108_combout ), - .cin(gnd), - .combout(\D[3]~75_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~75 .lut_mask = 16'hAFA0; -defparam \D[3]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N20 -cycloneive_lcell_comb \D[3]~76 ( -// Equation(s): -// \D[3]~76_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~75_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[3]~75_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [3]), - .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[3]~75_combout ), - .cin(gnd), - .combout(\D[3]~76_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~76 .lut_mask = 16'hAF23; -defparam \D[3]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N24 -cycloneive_lcell_comb \D[4]~82 ( -// Equation(s): -// \D[4]~82_combout = (\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout ))) - - .dataa(\Equal2~0_combout ), - .datab(\D[4]~81_combout ), - .datac(gnd), - .datad(\D[4]~109_combout ), - .cin(gnd), - .combout(\D[4]~82_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~82 .lut_mask = 16'hDD88; -defparam \D[4]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N26 -cycloneive_lcell_comb \D[4]~83 ( -// Equation(s): -// \D[4]~83_combout = (\Equal2~1_combout & (\D[4]~82_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [4]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [4]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[4]~82_combout ), - .cin(gnd), - .combout(\D[4]~83_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~83 .lut_mask = 16'hCF45; -defparam \D[4]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N24 -cycloneive_lcell_comb \D[6]~92 ( -// Equation(s): -// \D[6]~92_combout = (\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout )) +// \D[0]~66_combout = (\Equal2~0_combout & (\D[0]~58_combout )) # (!\Equal2~0_combout & ((\D[0]~120_combout ))) .dataa(gnd), .datab(\Equal2~0_combout ), - .datac(\D[6]~111_combout ), - .datad(\D[6]~86_combout ), + .datac(\D[0]~58_combout ), + .datad(\D[0]~120_combout ), .cin(gnd), - .combout(\D[6]~92_combout ), + .combout(\D[0]~66_combout ), .cout()); // synopsys translate_off -defparam \D[6]~92 .lut_mask = 16'hFC30; -defparam \D[6]~92 .sum_lutc_input = "datac"; +defparam \D[0]~66 .lut_mask = 16'hF3C0; +defparam \D[0]~66 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N10 -cycloneive_lcell_comb \D[6]~93 ( +// Location: LCCOMB_X25_Y15_N18 +cycloneive_lcell_comb \D[0]~67 ( // Equation(s): -// \D[6]~93_combout = (\Equal2~1_combout & (\D[6]~92_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [6]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) +// \D[0]~67_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [0] & ((\D[0]~66_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[0]~66_combout ) # (!\Equal2~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[6]~92_combout ), + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|data_pins_|dout [0]), + .datac(\Equal2~1_combout ), + .datad(\D[0]~66_combout ), .cin(gnd), - .combout(\D[6]~93_combout ), + .combout(\D[0]~67_combout ), .cout()); // synopsys translate_off -defparam \D[6]~93 .lut_mask = 16'hCF45; -defparam \D[6]~93 .sum_lutc_input = "datac"; +defparam \D[0]~67 .lut_mask = 16'hDD0D; +defparam \D[0]~67 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N0 -cycloneive_lcell_comb \z80_|nM1_int~3 ( +// Location: LCCOMB_X25_Y17_N24 +cycloneive_lcell_comb \D[0]~121 ( // Equation(s): -// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) +// \D[0]~121_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout ) # ((\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .cin(gnd), + .combout(\D[0]~121_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~121 .lut_mask = 16'hFF20; +defparam \D[0]~121 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N16 +cycloneive_lcell_comb \D[1]~68 ( +// Equation(s): +// \D[1]~68_combout = (\Equal2~0_combout & (\D[1]~34_combout )) # (!\Equal2~0_combout & ((\D[1]~118_combout ))) .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|setM1~52_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[1]~34_combout ), + .datad(\D[1]~118_combout ), + .cin(gnd), + .combout(\D[1]~68_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~68 .lut_mask = 16'hF3C0; +defparam \D[1]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N14 +cycloneive_lcell_comb \D[1]~69 ( +// Equation(s): +// \D[1]~69_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~68_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[1]~68_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\Equal2~1_combout ), + .datad(\D[1]~68_combout ), + .cin(gnd), + .combout(\D[1]~69_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~69 .lut_mask = 16'hDD0D; +defparam \D[1]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N16 +cycloneive_lcell_comb \D[2]~70 ( +// Equation(s): +// \D[2]~70_combout = (\Equal2~0_combout & (\D[2]~46_combout )) # (!\Equal2~0_combout & ((\D[2]~119_combout ))) + + .dataa(gnd), + .datab(\D[2]~46_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[2]~119_combout ), + .cin(gnd), + .combout(\D[2]~70_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~70 .lut_mask = 16'hCFC0; +defparam \D[2]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N14 +cycloneive_lcell_comb \D[2]~71 ( +// Equation(s): +// \D[2]~71_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [2] & ((\D[2]~70_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[2]~70_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\Equal2~1_combout ), + .datac(\z80_|data_pins_|dout [2]), + .datad(\D[2]~70_combout ), + .cin(gnd), + .combout(\D[2]~71_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~71 .lut_mask = 16'hF531; +defparam \D[2]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N24 +cycloneive_lcell_comb \D[3]~83 ( +// Equation(s): +// \D[3]~83_combout = (\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(gnd), + .datac(\z80_|data_pins_|dout [3]), + .datad(gnd), + .cin(gnd), + .combout(\D[3]~83_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~83 .lut_mask = 16'hF5F5; +defparam \D[3]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N6 +cycloneive_lcell_comb \D[3]~84 ( +// Equation(s): +// \D[3]~84_combout = (\D[3]~83_combout & ((\D[3]~122_combout ) # ((\D[3]~82_combout ) # (!\Equal2~1_combout )))) + + .dataa(\D[3]~122_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[3]~82_combout ), + .datad(\D[3]~83_combout ), + .cin(gnd), + .combout(\D[3]~84_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~84 .lut_mask = 16'hFB00; +defparam \D[3]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N20 +cycloneive_lcell_comb \D[4]~95 ( +// Equation(s): +// \D[4]~95_combout = (\Equal2~0_combout & (\D[4]~89_combout )) # (!\Equal2~0_combout & ((\D[4]~125_combout ))) + + .dataa(\D[4]~89_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[4]~125_combout ), + .datad(gnd), + .cin(gnd), + .combout(\D[4]~95_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~95 .lut_mask = 16'hB8B8; +defparam \D[4]~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N6 +cycloneive_lcell_comb \D[4]~96 ( +// Equation(s): +// \D[4]~96_combout = (\z80_|data_pins_|dout [4] & (((\D[4]~95_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [4] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[4]~95_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [4]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[4]~95_combout ), + .cin(gnd), + .combout(\D[4]~96_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~96 .lut_mask = 16'hAF23; +defparam \D[4]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N18 +cycloneive_lcell_comb \D[5]~126 ( +// Equation(s): +// \D[5]~126_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\Mux2~1_combout )) # +// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ))))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\Mux2~1_combout ), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .cin(gnd), + .combout(\D[5]~126_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~126 .lut_mask = 16'hFB40; +defparam \D[5]~126 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N0 +cycloneive_lcell_comb \D[5]~98 ( +// Equation(s): +// \D[5]~98_combout = (\z80_|data_pins_|dout [5] & (((\D[5]~126_combout )) # (!\D[5]~97_combout ))) # (!\z80_|data_pins_|dout [5] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[5]~126_combout ) # (!\D[5]~97_combout )))) + + .dataa(\z80_|data_pins_|dout [5]), + .datab(\D[5]~97_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[5]~126_combout ), + .cin(gnd), + .combout(\D[5]~98_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~98 .lut_mask = 16'hAF23; +defparam \D[5]~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N18 +cycloneive_lcell_comb \D[6]~105 ( +// Equation(s): +// \D[6]~105_combout = (\Equal2~0_combout & ((\D[6]~99_combout ))) # (!\Equal2~0_combout & (\D[6]~127_combout )) + + .dataa(gnd), + .datab(\Equal2~0_combout ), + .datac(\D[6]~127_combout ), + .datad(\D[6]~99_combout ), + .cin(gnd), + .combout(\D[6]~105_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~105 .lut_mask = 16'hFC30; +defparam \D[6]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N0 +cycloneive_lcell_comb \D[6]~106 ( +// Equation(s): +// \D[6]~106_combout = (\z80_|data_pins_|dout [6] & (((\D[6]~105_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [6] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[6]~105_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [6]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[6]~105_combout ), + .cin(gnd), + .combout(\D[6]~106_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~106 .lut_mask = 16'hAF23; +defparam \D[6]~106 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N10 +cycloneive_lcell_comb \D[7]~128 ( +// Equation(s): +// \D[7]~128_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux0~1_combout ))))) # +// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .datad(\Mux0~1_combout ), + .cin(gnd), + .combout(\D[7]~128_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~128 .lut_mask = 16'hF2D0; +defparam \D[7]~128 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N16 +cycloneive_lcell_comb \D[7]~107 ( +// Equation(s): +// \D[7]~107_combout = (\z80_|data_pins_|dout [7] & (((\D[7]~128_combout ) # (!\D[5]~97_combout )))) # (!\z80_|data_pins_|dout [7] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[7]~128_combout ) # (!\D[5]~97_combout )))) + + .dataa(\z80_|data_pins_|dout [7]), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\D[5]~97_combout ), + .datad(\D[7]~128_combout ), + .cin(gnd), + .combout(\D[7]~107_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~107 .lut_mask = 16'hBB0B; +defparam \D[7]~107 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N6 +cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nIORQ_out~0_combout = (!\z80_|memory_ifc_|DFFE_intr_ff3~q & (!\z80_|memory_ifc_|iorq~0_combout & !\z80_|memory_ifc_|wait_iorqinta~q )) + + .dataa(gnd), + .datab(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .datac(\z80_|memory_ifc_|iorq~0_combout ), + .datad(\z80_|memory_ifc_|wait_iorqinta~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'h0003; +defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N12 +cycloneive_lcell_comb \z80_|nM1_int~3 ( +// Equation(s): +// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), .combout(\z80_|nM1_int~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|nM1_int~3 .lut_mask = 16'hFC00; +defparam \z80_|nM1_int~3 .lut_mask = 16'hCCC0; defparam \z80_|nM1_int~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N1 +// Location: FF_X40_Y13_N13 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|nM1_int~3_combout ), @@ -53491,7 +54063,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N30 +// Location: LCCOMB_X40_Y11_N4 cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder ( // Equation(s): // \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -53508,7 +54080,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N31 +// Location: FF_X40_Y11_N5 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ), @@ -53527,7 +54099,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .power_up = "low"; // synopsys translate_on -// Location: FF_X43_Y17_N25 +// Location: FF_X40_Y11_N27 dffeas \z80_|memory_ifc_|DFFE_mreq_ff2 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -53546,31 +54118,31 @@ defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N24 +// Location: LCCOMB_X40_Y11_N26 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~0 ( // Equation(s): // \z80_|memory_ifc_|nMREQ_out~0_combout = (\z80_|memory_ifc_|wait_mwr~q ) # ((\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q & !\z80_|memory_ifc_|DFFE_mreq_ff2~q ))) - .dataa(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), - .datab(\z80_|memory_ifc_|wait_mwr~q ), + .dataa(\z80_|memory_ifc_|wait_mwr~q ), + .datab(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), .datac(\z80_|memory_ifc_|DFFE_mreq_ff2~q ), .datad(\z80_|memory_ifc_|mwr_wr~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFCE; +defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFAE; defparam \z80_|memory_ifc_|nMREQ_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N2 +// Location: LCCOMB_X40_Y11_N2 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~1 ( // Equation(s): -// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nMREQ_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|nRD_out~0_combout ))) +// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nMREQ_out~0_combout & !\z80_|memory_ifc_|nRD_out~0_combout ))) - .dataa(\z80_|memory_ifc_|wait_mrd~q ), - .datab(\z80_|memory_ifc_|nMREQ_out~0_combout ), - .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .dataa(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .datab(\z80_|memory_ifc_|wait_mrd~q ), + .datac(\z80_|memory_ifc_|nMREQ_out~0_combout ), .datad(\z80_|memory_ifc_|nRD_out~0_combout ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~1_combout ), @@ -53593,24 +54165,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( -// Equation(s): -// \ula_|i2c_loader_|state.Idle~feeder_combout = VCC - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Idle~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; -defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y24_N0 +// Location: LCCOMB_X1_Y24_N18 cycloneive_lcell_comb \ula_|i2c_loader_|divider[0]~15 ( // Equation(s): // \ula_|i2c_loader_|divider[0]~15_combout = !\ula_|i2c_loader_|divider [0] @@ -53627,7 +54182,7 @@ defparam \ula_|i2c_loader_|divider[0]~15 .lut_mask = 16'h0F0F; defparam \ula_|i2c_loader_|divider[0]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X4_Y24_N1 +// Location: FF_X1_Y24_N19 dffeas \ula_|i2c_loader_|divider[0] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[0]~15_combout ), @@ -53646,14 +54201,14 @@ defparam \ula_|i2c_loader_|divider[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N10 +// Location: LCCOMB_X1_Y24_N8 cycloneive_lcell_comb \ula_|i2c_loader_|divider[1]~5 ( // Equation(s): -// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] $ (VCC))) # (!\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] & VCC)) -// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [1] & \ula_|i2c_loader_|divider [0])) +// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] $ (VCC))) # (!\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] & VCC)) +// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [0] & \ula_|i2c_loader_|divider [1])) - .dataa(\ula_|i2c_loader_|divider [1]), - .datab(\ula_|i2c_loader_|divider [0]), + .dataa(\ula_|i2c_loader_|divider [0]), + .datab(\ula_|i2c_loader_|divider [1]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -53664,7 +54219,7 @@ defparam \ula_|i2c_loader_|divider[1]~5 .lut_mask = 16'h6688; defparam \ula_|i2c_loader_|divider[1]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X4_Y24_N11 +// Location: FF_X1_Y24_N9 dffeas \ula_|i2c_loader_|divider[1] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[1]~5_combout ), @@ -53683,7 +54238,7 @@ defparam \ula_|i2c_loader_|divider[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N12 +// Location: LCCOMB_X1_Y24_N10 cycloneive_lcell_comb \ula_|i2c_loader_|divider[2]~7 ( // Equation(s): // \ula_|i2c_loader_|divider[2]~7_combout = (\ula_|i2c_loader_|divider [2] & (!\ula_|i2c_loader_|divider[1]~6 )) # (!\ula_|i2c_loader_|divider [2] & ((\ula_|i2c_loader_|divider[1]~6 ) # (GND))) @@ -53701,7 +54256,7 @@ defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|divider[2]~7 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N13 +// Location: FF_X1_Y24_N11 dffeas \ula_|i2c_loader_|divider[2] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[2]~7_combout ), @@ -53720,25 +54275,25 @@ defparam \ula_|i2c_loader_|divider[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N14 +// Location: LCCOMB_X1_Y24_N12 cycloneive_lcell_comb \ula_|i2c_loader_|divider[3]~9 ( // Equation(s): // \ula_|i2c_loader_|divider[3]~9_combout = (\ula_|i2c_loader_|divider [3] & (\ula_|i2c_loader_|divider[2]~8 $ (GND))) # (!\ula_|i2c_loader_|divider [3] & (!\ula_|i2c_loader_|divider[2]~8 & VCC)) // \ula_|i2c_loader_|divider[3]~10 = CARRY((\ula_|i2c_loader_|divider [3] & !\ula_|i2c_loader_|divider[2]~8 )) - .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [3]), + .dataa(\ula_|i2c_loader_|divider [3]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|divider[2]~8 ), .combout(\ula_|i2c_loader_|divider[3]~9_combout ), .cout(\ula_|i2c_loader_|divider[3]~10 )); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[3]~9 .lut_mask = 16'hC30C; +defparam \ula_|i2c_loader_|divider[3]~9 .lut_mask = 16'hA50A; defparam \ula_|i2c_loader_|divider[3]~9 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N15 +// Location: FF_X1_Y24_N13 dffeas \ula_|i2c_loader_|divider[3] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[3]~9_combout ), @@ -53757,7 +54312,24 @@ defparam \ula_|i2c_loader_|divider[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N16 +// Location: LCCOMB_X1_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( +// Equation(s): +// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [1])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [3]) + + .dataa(\ula_|i2c_loader_|divider [3]), + .datab(\ula_|i2c_loader_|divider [0]), + .datac(\ula_|i2c_loader_|divider [1]), + .datad(\ula_|i2c_loader_|divider [2]), + .cin(gnd), + .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; +defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N14 cycloneive_lcell_comb \ula_|i2c_loader_|divider[4]~11 ( // Equation(s): // \ula_|i2c_loader_|divider[4]~11_combout = (\ula_|i2c_loader_|divider [4] & (!\ula_|i2c_loader_|divider[3]~10 )) # (!\ula_|i2c_loader_|divider [4] & ((\ula_|i2c_loader_|divider[3]~10 ) # (GND))) @@ -53775,7 +54347,7 @@ defparam \ula_|i2c_loader_|divider[4]~11 .lut_mask = 16'h3C3F; defparam \ula_|i2c_loader_|divider[4]~11 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N17 +// Location: FF_X1_Y24_N15 dffeas \ula_|i2c_loader_|divider[4] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[4]~11_combout ), @@ -53794,7 +54366,7 @@ defparam \ula_|i2c_loader_|divider[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N18 +// Location: LCCOMB_X1_Y24_N16 cycloneive_lcell_comb \ula_|i2c_loader_|divider[5]~13 ( // Equation(s): // \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider[4]~12 $ (!\ula_|i2c_loader_|divider [5]) @@ -53811,7 +54383,7 @@ defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hF00F; defparam \ula_|i2c_loader_|divider[5]~13 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N19 +// Location: FF_X1_Y24_N17 dffeas \ula_|i2c_loader_|divider[5] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[5]~13_combout ), @@ -53830,1115 +54402,23 @@ defparam \ula_|i2c_loader_|divider[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( -// Equation(s): -// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [3])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [1]) - - .dataa(\ula_|i2c_loader_|divider [1]), - .datab(\ula_|i2c_loader_|divider [0]), - .datac(\ula_|i2c_loader_|divider [3]), - .datad(\ula_|i2c_loader_|divider [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; -defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y24_N8 +// Location: LCCOMB_X1_Y24_N30 cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0 ( // Equation(s): -// \ula_|i2c_loader_|WideAnd0~combout = ((\ula_|i2c_loader_|WideAnd0~0_combout ) # (!\ula_|i2c_loader_|divider [4])) # (!\ula_|i2c_loader_|divider [5]) +// \ula_|i2c_loader_|WideAnd0~combout = (\ula_|i2c_loader_|WideAnd0~0_combout ) # ((!\ula_|i2c_loader_|divider [5]) # (!\ula_|i2c_loader_|divider [4])) .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [5]), - .datac(\ula_|i2c_loader_|WideAnd0~0_combout ), - .datad(\ula_|i2c_loader_|divider [4]), + .datab(\ula_|i2c_loader_|WideAnd0~0_combout ), + .datac(\ula_|i2c_loader_|divider [4]), + .datad(\ula_|i2c_loader_|divider [5]), .cin(gnd), .combout(\ula_|i2c_loader_|WideAnd0~combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hF3FF; +defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hCFFF; defparam \ula_|i2c_loader_|WideAnd0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N1 -dffeas \ula_|i2c_loader_|state.Idle ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Idle~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Idle~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Idle .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Idle .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|phase~0 ( -// Equation(s): -// \ula_|i2c_loader_|phase~0_combout = (!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|phase~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|phase~0 .lut_mask = 16'h0F00; -defparam \ula_|i2c_loader_|phase~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N5 -dffeas \ula_|i2c_loader_|phase[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|phase~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|phase [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|phase[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|phase[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|phase~1 ( -// Equation(s): -// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [0] $ (\ula_|i2c_loader_|phase [1]))) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|phase~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h3C00; -defparam \ula_|i2c_loader_|phase~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N15 -dffeas \ula_|i2c_loader_|phase[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|phase~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|phase [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|phase[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|phase[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~5_combout = (!\ula_|i2c_loader_|nbit [0]) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbit [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h5F5F; -defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) -// \ula_|i2c_loader_|thisbyte[0]~9 = CARRY(\ula_|i2c_loader_|thisbyte [0]) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~8_combout ), - .cout(\ula_|i2c_loader_|thisbyte[0]~9 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; -defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( -// Equation(s): -// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Mux42~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hF000; -defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [0] $ (!\ula_|i2c_loader_|nbyte [1])))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Start~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hFF84; -defparam \ula_|i2c_loader_|nbyte~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state.Ack~q ) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hC0C0; -defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X0_Y23_N1 -cycloneive_io_ibuf \I2C_SDAT~input ( - .i(I2C_SDAT), - .ibar(gnd), - .o(\I2C_SDAT~input_o )); -// synopsys translate_off -defparam \I2C_SDAT~input .bus_hold = "false"; -defparam \I2C_SDAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hEFE0; -defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|thisbyte[0]~7_combout & \ula_|i2c_loader_|nbyte[0]~1_combout )))) - - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hD888; -defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~3_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|nbyte[0]~2_combout )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), - .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h3000; -defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N29 -dffeas \ula_|i2c_loader_|nbyte[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbyte~4_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbyte [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbyte[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Stop~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h1010; -defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Stop~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))) # -// (!\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Stop~q )))) - - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Stop~q ), - .datad(\ula_|i2c_loader_|state.Stop~0_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Stop~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF4B0; -defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N3 -dffeas \ula_|i2c_loader_|state.Stop ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Stop~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Stop~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Ack~q ))) - - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Ack~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Idle~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; -defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])))) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|nbit [0]), - .datac(\ula_|i2c_loader_|nbit [2]), - .datad(\ula_|i2c_loader_|nbit [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; -defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N1 -dffeas \ula_|i2c_loader_|nbit[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~0_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [0]))) - - .dataa(\ula_|i2c_loader_|nbit [1]), - .datab(\ula_|i2c_loader_|nbit [2]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|nbit [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~0 .lut_mask = 16'h0010; -defparam \ula_|i2c_loader_|state.Done~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Done~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|state.Idle~0_combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), - .datad(\ula_|i2c_loader_|state.Done~0_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hAF2F; -defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Data~q ))))) # -// (!\ula_|i2c_loader_|state.Ack~0_combout & (((\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|state.Ack~0_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF2D0; -defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N31 -dffeas \ula_|i2c_loader_|state.Ack ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Ack~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Ack~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hEFE0; -defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[1]~5_combout ))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h0800; -defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y23_N15 -dffeas \ula_|i2c_loader_|thisbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), - .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; -defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N17 -dffeas \ula_|i2c_loader_|thisbyte[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) -// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), - .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hC30C; -defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N19 -dffeas \ula_|i2c_loader_|thisbyte[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), - .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; -defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N21 -dffeas \ula_|i2c_loader_|thisbyte[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( -// Equation(s): -// \ula_|i2c_loader_|Equal2~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0002; -defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~0_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]))) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Stop~q )))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h5FCC; -defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) - - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), - .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; -defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N23 -dffeas \ula_|i2c_loader_|thisbyte[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~1_combout = (\ula_|i2c_loader_|state.Pause~0_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|Equal2~0_combout ), - .datac(\ula_|i2c_loader_|state.Pause~0_combout ), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h30F0; -defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~2_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Done~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & -// (\ula_|i2c_loader_|state.Data~q & ((!\ula_|i2c_loader_|state.Done~1_combout )))) - - .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Done~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~2 .lut_mask = 16'h0ACE; -defparam \ula_|i2c_loader_|state.Done~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~2_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Done~2_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Done~2_combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'hC4FF; -defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Pause~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~2_combout & (\ula_|i2c_loader_|state.Pause~1_combout )) # -// (!\ula_|i2c_loader_|state.Pause~2_combout & ((\ula_|i2c_loader_|state.Pause~q ))))) - - .dataa(\ula_|i2c_loader_|state.Pause~1_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Pause~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'hE2F0; -defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N23 -dffeas \ula_|i2c_loader_|state.Pause ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Pause~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Pause~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( -// Equation(s): -// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # -// (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Pause~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h38FF; -defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N31 -dffeas \ula_|i2c_loader_|state.Start ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state~25_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Start~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Start .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Start~q )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [0]), - .datad(\ula_|i2c_loader_|state.Start~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h000C; -defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N11 -dffeas \ula_|i2c_loader_|nbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbyte~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & !\ula_|i2c_loader_|state.Data~q )) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0005; -defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h47CF; -defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # ((\ula_|i2c_loader_|nbit[0]~2_combout ) # (\ula_|i2c_loader_|state.Done~0_combout )))) - - .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), - .datab(\ula_|i2c_loader_|nbit[0]~2_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Done~0_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h0F0E; -defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~4 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~4_combout = (!\ula_|i2c_loader_|nbit[0]~3_combout & (\ula_|i2c_loader_|Mux42~0_combout & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q ))) - - .dataa(\ula_|i2c_loader_|nbit[0]~3_combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~4 .lut_mask = 16'h0400; -defparam \ula_|i2c_loader_|nbit[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N3 -dffeas \ula_|i2c_loader_|nbit[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~5_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbit [1]), - .datad(\ula_|i2c_loader_|nbit [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hF55F; -defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N13 -dffeas \ula_|i2c_loader_|nbit[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~6_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~1_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & !\ula_|i2c_loader_|nbit [0])) - - .dataa(\ula_|i2c_loader_|nbit [1]), - .datab(\ula_|i2c_loader_|nbit [2]), - .datac(gnd), - .datad(\ula_|i2c_loader_|nbit [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~1 .lut_mask = 16'h0011; -defparam \ula_|i2c_loader_|state.Done~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( -// Equation(s): -// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Done~1_combout ) # (!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Done~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h5FFF; -defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( -// Equation(s): -// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hE0E0; -defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( -// Equation(s): -// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state~24_combout )) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state~24_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hA000; -defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~27_combout )) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~26_combout ))) - - .dataa(\ula_|i2c_loader_|state~27_combout ), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state~26_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Data~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hAFA0; -defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N29 -dffeas \ula_|i2c_loader_|state.Data ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Data~0_combout ), - .asdata(\ula_|i2c_loader_|Mux42~0_combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2c_loader_|state.Start~q ), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Data~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Data .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( -// Equation(s): -// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Stop~q )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Stop~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|scl_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0003; -defparam \ula_|i2c_loader_|scl_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: FF_X1_Y23_N13 dffeas \ula_|i2c_loader_|scl_out~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), @@ -54958,38 +54438,1113 @@ defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~1 ( +// Location: LCCOMB_X2_Y24_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( // Equation(s): -// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Start~q $ (((!\ula_|i2c_loader_|scl_out~_Duplicate_1_q ))))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # -// ((\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|scl_out~_Duplicate_1_q )))) +// \ula_|i2c_loader_|state.Idle~feeder_combout = VCC - .dataa(\ula_|i2c_loader_|state.Start~q ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Idle~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; +defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N23 +dffeas \ula_|i2c_loader_|state.Idle ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Idle~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Idle~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Idle .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Idle .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|phase~0 ( +// Equation(s): +// \ula_|i2c_loader_|phase~0_combout = (!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|phase~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|phase~0 .lut_mask = 16'h0F00; +defparam \ula_|i2c_loader_|phase~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N9 +dffeas \ula_|i2c_loader_|phase[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|phase~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|phase [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|phase[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|phase[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|phase~1 ( +// Equation(s): +// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [0] $ (\ula_|i2c_loader_|phase [1]))) + + .dataa(gnd), .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|phase~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h3C00; +defparam \ula_|i2c_loader_|phase~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y24_N29 +dffeas \ula_|i2c_loader_|phase[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|phase~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|phase [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|phase[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|phase[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( +// Equation(s): +// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|phase [0]) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|Mux42~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hC0C0; +defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|phase [0])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|phase [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y25_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~4_combout = (!\ula_|i2c_loader_|state.Data~q ) # (!\ula_|i2c_loader_|nbit [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|nbit [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~4 .lut_mask = 16'h0FFF; +defparam \ula_|i2c_loader_|nbit~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [0] $ (!\ula_|i2c_loader_|nbyte [1])))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|phase [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hEDCC; +defparam \ula_|i2c_loader_|nbyte~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y23_N31 +dffeas \ula_|i2c_loader_|nbyte[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbyte~4_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbyte [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbyte[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~1_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'hFC00; +defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Start~q ) # ((!\ula_|i2c_loader_|state.Pause~0_combout & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # (\ula_|i2c_loader_|state.Data~q )))) + + .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Pause~0_combout ), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'hCFCE; +defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~3_combout = (\ula_|i2c_loader_|Mux42~0_combout & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|nbit[0]~2_combout ))) + + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|nbit[0]~2_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h2000; +defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y25_N27 +dffeas \ula_|i2c_loader_|nbit[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~4_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y25_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~5_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(gnd), + .datac(\ula_|i2c_loader_|nbit [1]), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'hF55F; +defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y25_N1 +dffeas \ula_|i2c_loader_|nbit[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~5_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y25_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~1_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [1] & !\ula_|i2c_loader_|nbit [0])) + + .dataa(\ula_|i2c_loader_|nbit [2]), + .datab(\ula_|i2c_loader_|nbit [1]), + .datac(gnd), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h0011; +defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( +// Equation(s): +// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Pause~1_combout ) # (!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Pause~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h3FFF; +defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( +// Equation(s): +// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hFC00; +defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( +// Equation(s): +// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state~24_combout )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state~24_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hC000; +defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~27_combout )) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~26_combout ))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state~27_combout ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|state~26_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Data~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hCFC0; +defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N5 +dffeas \ula_|i2c_loader_|state.Data ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Data~0_combout ), + .asdata(\ula_|i2c_loader_|Mux42~0_combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2c_loader_|state.Start~q ), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Data~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Data .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y25_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [1] & !\ula_|i2c_loader_|nbit [0])))) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|nbit [1]), + .datac(\ula_|i2c_loader_|nbit [2]), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; +defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y25_N13 +dffeas \ula_|i2c_loader_|nbit[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y25_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~0_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [0] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [1]))) + + .dataa(\ula_|i2c_loader_|nbit [2]), + .datab(\ula_|i2c_loader_|nbit [0]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|nbit [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h0010; +defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Pause~q ))) + + .dataa(\ula_|i2c_loader_|state.Stop~q ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Pause~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Idle~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; +defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Pause~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|state.Pause~0_combout ), + .datad(\ula_|i2c_loader_|state.Idle~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hB3BB; +defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|state.Data~q ))) # +// (!\ula_|i2c_loader_|state.Ack~0_combout & (\ula_|i2c_loader_|state.Ack~q )))) + + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|state.Ack~0_combout ), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF4B0; +defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N25 +dffeas \ula_|i2c_loader_|state.Ack ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Ack~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Ack~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state.Ack~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hF000; +defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y23_N1 +cycloneive_io_ibuf \I2C_SDAT~input ( + .i(I2C_SDAT), + .ibar(gnd), + .o(\I2C_SDAT~input_o )); +// synopsys translate_off +defparam \I2C_SDAT~input .bus_hold = "false"; +defparam \I2C_SDAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hFBC8; +defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|Mux42~0_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|thisbyte[0]~7_combout & ((\ula_|i2c_loader_|nbyte[0]~1_combout )))) + + .dataa(\ula_|i2c_loader_|thisbyte[0]~7_combout ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hCAC0; +defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~3_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[0]~2_combout )) + + .dataa(\ula_|i2c_loader_|state.Idle~q ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(gnd), + .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h2200; +defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y23_N21 +dffeas \ula_|i2c_loader_|nbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|i2c_loader_|nbyte~0_combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Stop~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Stop~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))))) # +// (!\ula_|i2c_loader_|Mux42~0_combout & (((\ula_|i2c_loader_|state.Stop~q )))) + + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Stop~q ), + .datad(\ula_|i2c_loader_|state.Stop~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Stop~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF2D0; +defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N7 +dffeas \ula_|i2c_loader_|state.Stop ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Stop~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Stop~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0]) # (!\ula_|i2c_loader_|phase [1])))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state.Stop~q )) + + .dataa(\ula_|i2c_loader_|state.Stop~q ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|phase [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'h2EEE; +defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) +// \ula_|i2c_loader_|thisbyte[0]~9 = CARRY(\ula_|i2c_loader_|thisbyte [0]) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~8_combout ), + .cout(\ula_|i2c_loader_|thisbyte[0]~9 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; +defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hFBC8; +defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~18_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q & (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|nbyte[1]~5_combout ))) + + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h4000; +defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y23_N19 +dffeas \ula_|i2c_loader_|thisbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), + .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y23_N21 +dffeas \ula_|i2c_loader_|thisbyte[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) +// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) + + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), + .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hA50A; +defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y23_N23 +dffeas \ula_|i2c_loader_|thisbyte[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), + .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y23_N25 +dffeas \ula_|i2c_loader_|thisbyte[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( +// Equation(s): +// \ula_|i2c_loader_|Equal2~0_combout = (!\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte [3]))) + + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0010; +defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) + + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), + .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; +defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y23_N27 +dffeas \ula_|i2c_loader_|thisbyte[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|state.Pause~2_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Pause~2_combout ), + .datac(\ula_|i2c_loader_|Equal2~0_combout ), + .datad(\ula_|i2c_loader_|thisbyte [4]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'h0CCC; +defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( +// Equation(s): +// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Data~q )) + + .dataa(\ula_|i2c_loader_|state.Stop~q ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|scl_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0011; +defparam \ula_|i2c_loader_|scl_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~4 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~4_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Pause~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & +// (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Pause~1_combout )))) + + .dataa(\ula_|i2c_loader_|scl_out~0_combout ), + .datab(\ula_|i2c_loader_|state.Pause~q ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|state.Pause~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~4 .lut_mask = 16'h22F2; +defparam \ula_|i2c_loader_|state.Pause~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~5 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~5_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Pause~4_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Pause~4_combout ), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|Mux42~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~5 .lut_mask = 16'hF733; +defparam \ula_|i2c_loader_|state.Pause~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~6 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~6_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Pause~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~5_combout & (\ula_|i2c_loader_|state.Pause~3_combout )) # +// (!\ula_|i2c_loader_|state.Pause~5_combout & ((\ula_|i2c_loader_|state.Pause~q ))))) + + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|state.Pause~3_combout ), + .datac(\ula_|i2c_loader_|state.Pause~q ), + .datad(\ula_|i2c_loader_|state.Pause~5_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~6 .lut_mask = 16'hE4F0; +defparam \ula_|i2c_loader_|state.Pause~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N21 +dffeas \ula_|i2c_loader_|state.Pause ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Pause~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Pause~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( +// Equation(s): +// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # +// (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|state.Pause~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h58FF; +defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N31 +dffeas \ula_|i2c_loader_|state.Start ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state~25_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Start~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Start .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~1 ( +// Equation(s): +// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|scl_out~_Duplicate_1_q $ (((!\ula_|i2c_loader_|state.Start~q ))))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # +// ((\ula_|i2c_loader_|scl_out~_Duplicate_1_q & \ula_|i2c_loader_|state.Start~q )))) + + .dataa(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|phase [0]), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hBA74; +defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hA5EC; defparam \ula_|i2c_loader_|scl_out~1 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X1_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~2 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|scl_out~1_combout & ((\ula_|i2c_loader_|state.Start~q ))) # (!\ula_|i2c_loader_|scl_out~1_combout & (!\ula_|i2c_loader_|scl_out~0_combout & !\ula_|i2c_loader_|state.Start~q )) +// \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|scl_out~1_combout & (\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|scl_out~1_combout & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|scl_out~0_combout )) - .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(\ula_|i2c_loader_|scl_out~1_combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|state.Start~q ), + .dataa(\ula_|i2c_loader_|scl_out~1_combout ), + .datab(gnd), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|scl_out~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hCC11; +defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hA0A5; defparam \ula_|i2c_loader_|scl_out~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -55031,15 +55586,32 @@ defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N10 +// Location: LCCOMB_X3_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( +// Equation(s): +// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [3]) # (!\ula_|i2c_loader_|thisbyte [1])))) + + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Mux35~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h20A0; +defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~4 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Start~q ) +// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Data~q ) .dataa(gnd), .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~4_combout ), .cout()); @@ -55048,146 +55620,146 @@ defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h000F; defparam \ula_|i2c_loader_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( +// Location: LCCOMB_X3_Y23_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( // Equation(s): -// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [1]) # (!\ula_|i2c_loader_|thisbyte [3])))) +// \ula_|i2c_loader_|shiftreg~19_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1])) # (!\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [3]))))) .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [1]), - .datad(\ula_|i2c_loader_|thisbyte [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Mux35~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h2A00; -defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) - - .dataa(\ula_|i2c_loader_|thisbyte [4]), .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h001A; -defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~14_combout = (\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2]) - - .dataa(gnd), - .datab(gnd), .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [3]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~14_combout ), + .combout(\ula_|i2c_loader_|shiftreg~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h00F0; -defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h202A; +defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( +// Location: LCCOMB_X3_Y23_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|shiftreg~13_combout ) # ((!\ula_|i2c_loader_|thisbyte [3] & (\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|shiftreg~14_combout ))) +// \ula_|i2c_loader_|shiftreg~20_combout = ((\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|shiftreg~19_combout ))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) - .dataa(\ula_|i2c_loader_|shiftreg~13_combout ), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|shiftreg~14_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'hAABA; -defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~24 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~24_combout = (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|thisbyte [0])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|shiftreg~4_combout ), + .datac(\ula_|i2c_loader_|shiftreg~19_combout ), .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~24_combout ), + .combout(\ula_|i2c_loader_|shiftreg~20_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~24 .lut_mask = 16'h0300; -defparam \ula_|i2c_loader_|shiftreg[0]~24 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'h73FB; +defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N14 +// Location: LCCOMB_X3_Y23_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [3]))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [3])))) + + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [0]), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h8804; +defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~23 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~23_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~22_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) + + .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|shiftreg~22_combout ), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hA0A8; +defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~25 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[0]~25_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|thisbyte [3] & \ula_|i2c_loader_|thisbyte [0])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|thisbyte [3]), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg[0]~25 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|shiftreg[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N12 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~6 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~6_combout = (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|shiftreg[0]~6_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|phase [0] & !\ula_|i2c_loader_|phase [1])) - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|phase [1]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h5000; +defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h00C0; defparam \ula_|i2c_loader_|shiftreg[0]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N0 +// Location: LCCOMB_X2_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~7 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|state~24_combout )))) +// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state~24_combout ) # (\ula_|i2c_loader_|state.Start~q )))) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|shiftreg[0]~6_combout ), - .datad(\ula_|i2c_loader_|state~24_combout ), + .dataa(\ula_|i2c_loader_|shiftreg[0]~6_combout ), + .datab(\ula_|i2c_loader_|state~24_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|Mux42~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFCF8; +defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFEAA; defparam \ula_|i2c_loader_|shiftreg[0]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N10 +// Location: LCCOMB_X2_Y24_N0 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~8 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~8_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|shiftreg[0]~7_combout )) +// \ula_|i2c_loader_|shiftreg[0]~8_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|shiftreg[0]~7_combout & \ula_|i2c_loader_|state.Idle~q )) - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Idle~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|shiftreg[0]~7_combout ), + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|shiftreg[0]~7_combout ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Idle~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h0C00; +defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h4400; defparam \ula_|i2c_loader_|shiftreg[0]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N13 +// Location: FF_X3_Y24_N21 dffeas \ula_|i2c_loader_|shiftreg[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg[0]~24_combout ), + .d(\ula_|i2c_loader_|shiftreg[0]~25_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -55203,102 +55775,85 @@ defparam \ula_|i2c_loader_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( +// Location: LCCOMB_X3_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~24 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte [2]))) # (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2])))) +// \ula_|i2c_loader_|shiftreg~24_combout = (\ula_|i2c_loader_|shiftreg~23_combout ) # ((\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [0])) - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~21_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hC010; -defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~21_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) - - .dataa(\ula_|i2c_loader_|shiftreg~21_combout ), - .datab(\ula_|i2c_loader_|shiftreg~4_combout ), - .datac(\ula_|i2c_loader_|thisbyte [1]), - .datad(\ula_|i2c_loader_|thisbyte [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h88C8; -defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~23 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~23_combout = (\ula_|i2c_loader_|shiftreg~22_combout ) # ((\ula_|i2c_loader_|shiftreg [0] & \ula_|i2c_loader_|state.Data~q )) - - .dataa(\ula_|i2c_loader_|shiftreg [0]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|shiftreg~23_combout ), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~22_combout ), + .datad(\ula_|i2c_loader_|shiftreg [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~23_combout ), + .combout(\ula_|i2c_loader_|shiftreg~24_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hFFA0; -defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~24 .lut_mask = 16'hFCCC; +defparam \ula_|i2c_loader_|shiftreg~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N10 +// Location: LCCOMB_X2_Y24_N6 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~10 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state.Start~q ) # ((!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|state~24_combout )))) # (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Data~q -// & (!\ula_|i2c_loader_|state.Start~q ))) +// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|phase [1]) # (!\ula_|i2c_loader_|phase [0])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state~24_combout )) - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state~24_combout ), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|state~24_combout ), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|phase [1]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hA6A4; +defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hBB1B; defparam \ula_|i2c_loader_|shiftreg[6]~10 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X2_Y24_N24 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~11 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|shiftreg[6]~10_combout ))) +// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg[6]~10_combout ) # ((!\ula_|i2c_loader_|Mux42~0_combout & +// !\ula_|i2c_loader_|state.Data~q )))) - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), .datad(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~11 .lut_mask = 16'h2000; +defparam \ula_|i2c_loader_|shiftreg[6]~11 .lut_mask = 16'h5F51; defparam \ula_|i2c_loader_|shiftreg[6]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N23 +// Location: LCCOMB_X2_Y24_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~12 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[6]~12_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (!\ula_|i2c_loader_|shiftreg[6]~11_combout & \ula_|i2c_loader_|state.Idle~q )) + + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg[6]~12 .lut_mask = 16'h1100; +defparam \ula_|i2c_loader_|shiftreg[6]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N13 dffeas \ula_|i2c_loader_|shiftreg[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~23_combout ), + .d(\ula_|i2c_loader_|shiftreg~24_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [1]), @@ -55308,67 +55863,33 @@ defparam \ula_|i2c_loader_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( +// Location: LCCOMB_X3_Y24_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [1]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [3])))) +// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|shiftreg~20_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h10B0; -defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~19_combout = ((\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [0])) # (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|shiftreg~18_combout )))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(\ula_|i2c_loader_|shiftreg~18_combout ), - .datad(\ula_|i2c_loader_|shiftreg~4_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h74FF; -defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~20_combout = (\ula_|i2c_loader_|shiftreg~19_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) - - .dataa(\ula_|i2c_loader_|shiftreg [1]), + .dataa(\ula_|i2c_loader_|shiftreg~20_combout ), .datab(gnd), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~19_combout ), + .datad(\ula_|i2c_loader_|shiftreg [1]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~20_combout ), + .combout(\ula_|i2c_loader_|shiftreg~21_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'hAF00; -defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hAA0A; +defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N3 +// Location: FF_X3_Y24_N11 dffeas \ula_|i2c_loader_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~20_combout ), + .d(\ula_|i2c_loader_|shiftreg~21_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [2]), @@ -55378,67 +55899,84 @@ defparam \ula_|i2c_loader_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( +// Location: LCCOMB_X3_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) +// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) .dataa(\ula_|i2c_loader_|thisbyte [2]), .datab(\ula_|i2c_loader_|thisbyte [1]), .datac(\ula_|i2c_loader_|thisbyte [4]), .datad(\ula_|i2c_loader_|thisbyte [3]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'h10BA; -defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~16_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [3] & ((!\ula_|i2c_loader_|shiftreg~14_combout )))) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|shiftreg~16_combout ), - .datad(\ula_|i2c_loader_|shiftreg~14_combout ), - .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'hA0E4; +defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'h10BA; defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( +// Location: LCCOMB_X3_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [2])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg~17_combout )))) +// \ula_|i2c_loader_|shiftreg~15_combout = (!\ula_|i2c_loader_|thisbyte [2] & \ula_|i2c_loader_|thisbyte [4]) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|shiftreg [2]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~17_combout ), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(gnd), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(gnd), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~26_combout ), + .combout(\ula_|i2c_loader_|shiftreg~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hC5C0; -defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'h5050; +defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N7 +// Location: LCCOMB_X3_Y24_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|shiftreg~17_combout )) # (!\ula_|i2c_loader_|thisbyte [0] & (((!\ula_|i2c_loader_|shiftreg~15_combout & \ula_|i2c_loader_|thisbyte [3])))) + + .dataa(\ula_|i2c_loader_|shiftreg~17_combout ), + .datab(\ula_|i2c_loader_|shiftreg~15_combout ), + .datac(\ula_|i2c_loader_|thisbyte [3]), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'hAA30; +defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~27 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~27_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [2])) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|shiftreg~18_combout )))) + + .dataa(\ula_|i2c_loader_|shiftreg [2]), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg~18_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~27 .lut_mask = 16'hA3A0; +defparam \ula_|i2c_loader_|shiftreg~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N23 dffeas \ula_|i2c_loader_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~26_combout ), + .d(\ula_|i2c_loader_|shiftreg~27_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [3]), @@ -55448,33 +55986,67 @@ defparam \ula_|i2c_loader_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~25 ( +// Location: LCCOMB_X3_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg~15_combout ) # ((\ula_|i2c_loader_|state.Start~q )))) +// \ula_|i2c_loader_|shiftreg~14_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) - .dataa(\ula_|i2c_loader_|shiftreg~15_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|shiftreg [3]), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~25_combout ), + .combout(\ula_|i2c_loader_|shiftreg~14_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hFE32; -defparam \ula_|i2c_loader_|shiftreg~25 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h0150; +defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N1 +// Location: LCCOMB_X3_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|shiftreg~14_combout ) # ((\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [3] & !\ula_|i2c_loader_|shiftreg~15_combout ))) + + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|shiftreg~14_combout ), + .datac(\ula_|i2c_loader_|thisbyte [3]), + .datad(\ula_|i2c_loader_|shiftreg~15_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'hCCCE; +defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [3])) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|shiftreg~16_combout )))) + + .dataa(\ula_|i2c_loader_|shiftreg [3]), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg~16_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hAFAC; +defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N15 dffeas \ula_|i2c_loader_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~25_combout ), + .d(\ula_|i2c_loader_|shiftreg~26_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [4]), @@ -55484,33 +56056,33 @@ defparam \ula_|i2c_loader_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~12 ( +// Location: LCCOMB_X4_Y24_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~12_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) +// \ula_|i2c_loader_|shiftreg~13_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) .dataa(\ula_|i2c_loader_|Mux35~0_combout ), .datab(\ula_|i2c_loader_|state.Data~q ), .datac(gnd), .datad(\ula_|i2c_loader_|shiftreg [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~12_combout ), + .combout(\ula_|i2c_loader_|shiftreg~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~12 .lut_mask = 16'hEE22; -defparam \ula_|i2c_loader_|shiftreg~12 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'hEE22; +defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N5 +// Location: FF_X4_Y24_N5 dffeas \ula_|i2c_loader_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~12_combout ), + .d(\ula_|i2c_loader_|shiftreg~13_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(\ula_|i2c_loader_|state.Start~q ), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [5]), @@ -55520,24 +56092,24 @@ defparam \ula_|i2c_loader_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N18 +// Location: LCCOMB_X3_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~9 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~9_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [5])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) +// \ula_|i2c_loader_|shiftreg~9_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [5]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) .dataa(gnd), - .datab(\ula_|i2c_loader_|shiftreg [5]), + .datab(\ula_|i2c_loader_|Mux35~0_combout ), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|Mux35~0_combout ), + .datad(\ula_|i2c_loader_|shiftreg [5]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hCFC0; +defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hFC0C; defparam \ula_|i2c_loader_|shiftreg~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N19 +// Location: FF_X3_Y24_N3 dffeas \ula_|i2c_loader_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~9_combout ), @@ -55546,7 +56118,7 @@ dffeas \ula_|i2c_loader_|shiftreg[6] ( .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [6]), @@ -55556,7 +56128,7 @@ defparam \ula_|i2c_loader_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N4 +// Location: LCCOMB_X3_Y24_N28 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[7]~5 ( // Equation(s): // \ula_|i2c_loader_|shiftreg[7]~5_combout = (\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [6]) @@ -55573,7 +56145,7 @@ defparam \ula_|i2c_loader_|shiftreg[7]~5 .lut_mask = 16'hF000; defparam \ula_|i2c_loader_|shiftreg[7]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N5 +// Location: FF_X3_Y24_N29 dffeas \ula_|i2c_loader_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg[7]~5_combout ), @@ -55592,42 +56164,42 @@ defparam \ula_|i2c_loader_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N12 +// Location: LCCOMB_X2_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~0 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|shiftreg [7]))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|state.Data~q & +// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|shiftreg [7])) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|state.Ack~q ))))) # (!\ula_|i2c_loader_|state.Data~q & // (((\ula_|i2c_loader_|state.Ack~q )))) - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|phase [0]), + .dataa(\ula_|i2c_loader_|shiftreg [7]), + .datab(\ula_|i2c_loader_|state.Data~q ), .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|shiftreg [7]), + .datad(\ula_|i2c_loader_|phase [0]), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hF870; +defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hB8F0; defparam \ula_|i2c_loader_|sda_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N6 +// Location: LCCOMB_X1_Y23_N18 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~1 ( // Equation(s): // \ula_|i2c_loader_|sda_out~1_combout = (\ula_|i2c_loader_|sda_out~0_combout & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|shiftreg~4_combout & !\I2C_SDAT~input_o )))) - .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), + .dataa(\ula_|i2c_loader_|sda_out~0_combout ), .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|sda_out~0_combout ), + .datac(\ula_|i2c_loader_|shiftreg~4_combout ), .datad(\I2C_SDAT~input_o ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'hC0E0; +defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'h88A8; defparam \ula_|i2c_loader_|sda_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N8 +// Location: LCCOMB_X1_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~2 ( // Equation(s): // \ula_|i2c_loader_|sda_out~2_combout = (!\ula_|i2c_loader_|sda_out~_Duplicate_1_q & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|phase [1] & !\ula_|i2c_loader_|sda_out~1_combout )))) @@ -55644,7 +56216,7 @@ defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h4454; defparam \ula_|i2c_loader_|sda_out~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N2 +// Location: LCCOMB_X1_Y23_N6 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~3 ( // Equation(s): // \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )) # (!\ula_|i2c_loader_|phase [1] & ((!\ula_|i2c_loader_|sda_out~1_combout ))))) # (!\ula_|i2c_loader_|phase @@ -55698,7 +56270,2727 @@ defparam \ula_|i2c_loader_|sda_out .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out .power_up = "high"; // synopsys translate_on -// Location: LCCOMB_X27_Y23_N16 +// Location: PLL_1 +cycloneive_pll \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 ( + .areset(gnd), + .pfdena(vcc), + .fbin(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\CLOCK_50~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(), + .vcooverrange(), + .vcounderrange(), + .fbout(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c0_high = 3; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c0_initial = 2; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c0_low = 2; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c0_mode = "odd"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c0_ph = 4; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_high = 3; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_initial = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_low = 2; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_mode = "odd"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk0_counter = "c1"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk0_divide_by = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk0_multiply_by = 2; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk1_counter = "c0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk1_divide_by = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk1_multiply_by = 2; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk1_phase_shift = "3000"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .m = 10; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .n = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .pll_compensation_delay = 5611; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 250; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N14 +cycloneive_lcell_comb \sdram_|Mux38~0 ( +// Equation(s): +// \sdram_|Mux38~0_combout = (\sdram_|r.rd_pending~q & (((\sdram_|Mux39~1_combout )))) # (!\sdram_|r.rd_pending~q & (\z80_|control_pins_|pin_nIORQ~1_combout & (\Equal2~1_combout ))) + + .dataa(\z80_|control_pins_|pin_nIORQ~1_combout ), + .datab(\Equal2~1_combout ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Mux39~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux38~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux38~0 .lut_mask = 16'hF808; +defparam \sdram_|Mux38~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y12_N15 +dffeas \sdram_|r.rd_pending ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux38~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rd_pending~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rd_pending .is_wysiwyg = "true"; +defparam \sdram_|r.rd_pending .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N0 +cycloneive_lcell_comb \sdram_|r.rf_counter[0]~12 ( +// Equation(s): +// \sdram_|r.rf_counter[0]~12_combout = \sdram_|r.rf_counter [0] $ (VCC) +// \sdram_|r.rf_counter[0]~13 = CARRY(\sdram_|r.rf_counter [0]) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_|r.rf_counter[0]~12_combout ), + .cout(\sdram_|r.rf_counter[0]~13 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[0]~12 .lut_mask = 16'h33CC; +defparam \sdram_|r.rf_counter[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N26 +cycloneive_lcell_comb \sdram_|r.rf_counter[3]~32 ( +// Equation(s): +// \sdram_|r.rf_counter[3]~32_combout = ((!\sdram_|r.state [5] & (\sdram_|r.address[3]~6_combout & !\sdram_|r.state [4]))) # (!\sdram_|Equal0~2_combout ) + + .dataa(\sdram_|Equal0~2_combout ), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.address[3]~6_combout ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|r.rf_counter[3]~32_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.rf_counter[3]~32 .lut_mask = 16'h5575; +defparam \sdram_|r.rf_counter[3]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y13_N1 +dffeas \sdram_|r.rf_counter[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[0]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[0] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N2 +cycloneive_lcell_comb \sdram_|r.rf_counter[1]~14 ( +// Equation(s): +// \sdram_|r.rf_counter[1]~14_combout = (\sdram_|r.rf_counter [1] & (!\sdram_|r.rf_counter[0]~13 )) # (!\sdram_|r.rf_counter [1] & ((\sdram_|r.rf_counter[0]~13 ) # (GND))) +// \sdram_|r.rf_counter[1]~15 = CARRY((!\sdram_|r.rf_counter[0]~13 ) # (!\sdram_|r.rf_counter [1])) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[0]~13 ), + .combout(\sdram_|r.rf_counter[1]~14_combout ), + .cout(\sdram_|r.rf_counter[1]~15 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[1]~14 .lut_mask = 16'h3C3F; +defparam \sdram_|r.rf_counter[1]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N3 +dffeas \sdram_|r.rf_counter[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[1]~14_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[1] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N4 +cycloneive_lcell_comb \sdram_|r.rf_counter[2]~16 ( +// Equation(s): +// \sdram_|r.rf_counter[2]~16_combout = (\sdram_|r.rf_counter [2] & (\sdram_|r.rf_counter[1]~15 $ (GND))) # (!\sdram_|r.rf_counter [2] & (!\sdram_|r.rf_counter[1]~15 & VCC)) +// \sdram_|r.rf_counter[2]~17 = CARRY((\sdram_|r.rf_counter [2] & !\sdram_|r.rf_counter[1]~15 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[1]~15 ), + .combout(\sdram_|r.rf_counter[2]~16_combout ), + .cout(\sdram_|r.rf_counter[2]~17 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[2]~16 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[2]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N5 +dffeas \sdram_|r.rf_counter[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[2]~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[2] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N6 +cycloneive_lcell_comb \sdram_|r.rf_counter[3]~18 ( +// Equation(s): +// \sdram_|r.rf_counter[3]~18_combout = (\sdram_|r.rf_counter [3] & (!\sdram_|r.rf_counter[2]~17 )) # (!\sdram_|r.rf_counter [3] & ((\sdram_|r.rf_counter[2]~17 ) # (GND))) +// \sdram_|r.rf_counter[3]~19 = CARRY((!\sdram_|r.rf_counter[2]~17 ) # (!\sdram_|r.rf_counter [3])) + + .dataa(\sdram_|r.rf_counter [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[2]~17 ), + .combout(\sdram_|r.rf_counter[3]~18_combout ), + .cout(\sdram_|r.rf_counter[3]~19 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[3]~18 .lut_mask = 16'h5A5F; +defparam \sdram_|r.rf_counter[3]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N7 +dffeas \sdram_|r.rf_counter[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[3]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[3] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N8 +cycloneive_lcell_comb \sdram_|r.rf_counter[4]~20 ( +// Equation(s): +// \sdram_|r.rf_counter[4]~20_combout = (\sdram_|r.rf_counter [4] & (\sdram_|r.rf_counter[3]~19 $ (GND))) # (!\sdram_|r.rf_counter [4] & (!\sdram_|r.rf_counter[3]~19 & VCC)) +// \sdram_|r.rf_counter[4]~21 = CARRY((\sdram_|r.rf_counter [4] & !\sdram_|r.rf_counter[3]~19 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[3]~19 ), + .combout(\sdram_|r.rf_counter[4]~20_combout ), + .cout(\sdram_|r.rf_counter[4]~21 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[4]~20 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[4]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N9 +dffeas \sdram_|r.rf_counter[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[4]~20_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[4] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N10 +cycloneive_lcell_comb \sdram_|r.rf_counter[5]~22 ( +// Equation(s): +// \sdram_|r.rf_counter[5]~22_combout = (\sdram_|r.rf_counter [5] & (!\sdram_|r.rf_counter[4]~21 )) # (!\sdram_|r.rf_counter [5] & ((\sdram_|r.rf_counter[4]~21 ) # (GND))) +// \sdram_|r.rf_counter[5]~23 = CARRY((!\sdram_|r.rf_counter[4]~21 ) # (!\sdram_|r.rf_counter [5])) + + .dataa(\sdram_|r.rf_counter [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[4]~21 ), + .combout(\sdram_|r.rf_counter[5]~22_combout ), + .cout(\sdram_|r.rf_counter[5]~23 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[5]~22 .lut_mask = 16'h5A5F; +defparam \sdram_|r.rf_counter[5]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N11 +dffeas \sdram_|r.rf_counter[5] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[5]~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[5] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N12 +cycloneive_lcell_comb \sdram_|r.rf_counter[6]~24 ( +// Equation(s): +// \sdram_|r.rf_counter[6]~24_combout = (\sdram_|r.rf_counter [6] & (\sdram_|r.rf_counter[5]~23 $ (GND))) # (!\sdram_|r.rf_counter [6] & (!\sdram_|r.rf_counter[5]~23 & VCC)) +// \sdram_|r.rf_counter[6]~25 = CARRY((\sdram_|r.rf_counter [6] & !\sdram_|r.rf_counter[5]~23 )) + + .dataa(\sdram_|r.rf_counter [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[5]~23 ), + .combout(\sdram_|r.rf_counter[6]~24_combout ), + .cout(\sdram_|r.rf_counter[6]~25 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[6]~24 .lut_mask = 16'hA50A; +defparam \sdram_|r.rf_counter[6]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N13 +dffeas \sdram_|r.rf_counter[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[6]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[6] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N14 +cycloneive_lcell_comb \sdram_|r.rf_counter[7]~26 ( +// Equation(s): +// \sdram_|r.rf_counter[7]~26_combout = (\sdram_|r.rf_counter [7] & (!\sdram_|r.rf_counter[6]~25 )) # (!\sdram_|r.rf_counter [7] & ((\sdram_|r.rf_counter[6]~25 ) # (GND))) +// \sdram_|r.rf_counter[7]~27 = CARRY((!\sdram_|r.rf_counter[6]~25 ) # (!\sdram_|r.rf_counter [7])) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[6]~25 ), + .combout(\sdram_|r.rf_counter[7]~26_combout ), + .cout(\sdram_|r.rf_counter[7]~27 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[7]~26 .lut_mask = 16'h3C3F; +defparam \sdram_|r.rf_counter[7]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N15 +dffeas \sdram_|r.rf_counter[7] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[7]~26_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[7] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N24 +cycloneive_lcell_comb \sdram_|Equal0~1 ( +// Equation(s): +// \sdram_|Equal0~1_combout = (\sdram_|r.rf_counter [5]) # ((\sdram_|r.rf_counter [7]) # ((\sdram_|r.rf_counter [4]) # (\sdram_|r.rf_counter [6]))) + + .dataa(\sdram_|r.rf_counter [5]), + .datab(\sdram_|r.rf_counter [7]), + .datac(\sdram_|r.rf_counter [4]), + .datad(\sdram_|r.rf_counter [6]), + .cin(gnd), + .combout(\sdram_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~1 .lut_mask = 16'hFFFE; +defparam \sdram_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N16 +cycloneive_lcell_comb \sdram_|r.rf_counter[8]~28 ( +// Equation(s): +// \sdram_|r.rf_counter[8]~28_combout = (\sdram_|r.rf_counter [8] & (\sdram_|r.rf_counter[7]~27 $ (GND))) # (!\sdram_|r.rf_counter [8] & (!\sdram_|r.rf_counter[7]~27 & VCC)) +// \sdram_|r.rf_counter[8]~29 = CARRY((\sdram_|r.rf_counter [8] & !\sdram_|r.rf_counter[7]~27 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[7]~27 ), + .combout(\sdram_|r.rf_counter[8]~28_combout ), + .cout(\sdram_|r.rf_counter[8]~29 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[8]~28 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[8]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N17 +dffeas \sdram_|r.rf_counter[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[8]~28_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[8] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N30 +cycloneive_lcell_comb \sdram_|Equal0~0 ( +// Equation(s): +// \sdram_|Equal0~0_combout = (\sdram_|r.rf_counter [3]) # ((\sdram_|r.rf_counter [0]) # ((\sdram_|r.rf_counter [2]) # (!\sdram_|r.rf_counter [1]))) + + .dataa(\sdram_|r.rf_counter [3]), + .datab(\sdram_|r.rf_counter [0]), + .datac(\sdram_|r.rf_counter [2]), + .datad(\sdram_|r.rf_counter [1]), + .cin(gnd), + .combout(\sdram_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~0 .lut_mask = 16'hFEFF; +defparam \sdram_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N18 +cycloneive_lcell_comb \sdram_|r.rf_counter[9]~30 ( +// Equation(s): +// \sdram_|r.rf_counter[9]~30_combout = \sdram_|r.rf_counter[8]~29 $ (\sdram_|r.rf_counter [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_|r.rf_counter [9]), + .cin(\sdram_|r.rf_counter[8]~29 ), + .combout(\sdram_|r.rf_counter[9]~30_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.rf_counter[9]~30 .lut_mask = 16'h0FF0; +defparam \sdram_|r.rf_counter[9]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N19 +dffeas \sdram_|r.rf_counter[9] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[9]~30_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[9] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N22 +cycloneive_lcell_comb \sdram_|Equal0~2 ( +// Equation(s): +// \sdram_|Equal0~2_combout = (\sdram_|Equal0~1_combout ) # (((\sdram_|Equal0~0_combout ) # (!\sdram_|r.rf_counter [9])) # (!\sdram_|r.rf_counter [8])) + + .dataa(\sdram_|Equal0~1_combout ), + .datab(\sdram_|r.rf_counter [8]), + .datac(\sdram_|Equal0~0_combout ), + .datad(\sdram_|r.rf_counter [9]), + .cin(gnd), + .combout(\sdram_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~2 .lut_mask = 16'hFBFF; +defparam \sdram_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N28 +cycloneive_lcell_comb \sdram_|Mux13~8 ( +// Equation(s): +// \sdram_|Mux13~8_combout = (\sdram_|r.state [4] & !\sdram_|r.state [5]) + + .dataa(gnd), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [5]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|Mux13~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~8 .lut_mask = 16'h0C0C; +defparam \sdram_|Mux13~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N20 +cycloneive_lcell_comb \sdram_|Mux37~0 ( +// Equation(s): +// \sdram_|Mux37~0_combout = (\sdram_|r.rf_pending~q & (((!\sdram_|Mux13~8_combout ) # (!\sdram_|r.address[3]~6_combout )))) # (!\sdram_|r.rf_pending~q & (!\sdram_|Equal0~2_combout )) + + .dataa(\sdram_|Equal0~2_combout ), + .datab(\sdram_|r.address[3]~6_combout ), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Mux13~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux37~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux37~0 .lut_mask = 16'h35F5; +defparam \sdram_|Mux37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y13_N21 +dffeas \sdram_|r.rf_pending ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux37~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_pending~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_pending .is_wysiwyg = "true"; +defparam \sdram_|r.rf_pending .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N14 +cycloneive_lcell_comb \sdram_|Mux4~0 ( +// Equation(s): +// \sdram_|Mux4~0_combout = (!\sdram_|r.wr_pending~q & (\sdram_|r.rd_pending~q & (!\sdram_|r.rf_pending~q & \sdram_|Equal7~2_combout ))) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~0 .lut_mask = 16'h0400; +defparam \sdram_|Mux4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N0 +cycloneive_lcell_comb \sdram_|Mux4~1 ( +// Equation(s): +// \sdram_|Mux4~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [5] $ ((!\sdram_|r.state [4])))) # (!\sdram_|r.state [6] & (\sdram_|r.state [5] & ((!\sdram_|Mux4~0_combout ) # (!\sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|Mux4~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~1 .lut_mask = 16'h86C6; +defparam \sdram_|Mux4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N2 +cycloneive_lcell_comb \sdram_|Mux4~2 ( +// Equation(s): +// \sdram_|Mux4~2_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [5]) # ((\sdram_|r.state [4])))) # (!\sdram_|r.state [6] & ((\sdram_|Mux4~0_combout ) # ((!\sdram_|r.state [5] & \sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|Mux4~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~2 .lut_mask = 16'hFDB8; +defparam \sdram_|Mux4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N30 +cycloneive_lcell_comb \sdram_|Mux4~3 ( +// Equation(s): +// \sdram_|Mux4~3_combout = (\sdram_|Mux4~2_combout & (\sdram_|r.state [8] $ (((\sdram_|Mux4~1_combout & \sdram_|r.state [7]))))) # (!\sdram_|Mux4~2_combout & (\sdram_|r.state [8] & (\sdram_|Mux4~1_combout $ (\sdram_|r.state [7])))) + + .dataa(\sdram_|Mux4~1_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux4~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~3 .lut_mask = 16'h7860; +defparam \sdram_|Mux4~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y15_N31 +dffeas \sdram_|r.state[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux4~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[8] .is_wysiwyg = "true"; +defparam \sdram_|r.state[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N6 +cycloneive_lcell_comb \sdram_|r.act_row[1]~0 ( +// Equation(s): +// \sdram_|r.act_row[1]~0_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [6] & (\sdram_|r.state [5] & \sdram_|r.state [8])) # (!\sdram_|r.state [6] & (!\sdram_|r.state [5] & !\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.act_row[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.act_row[1]~0 .lut_mask = 16'h8004; +defparam \sdram_|r.act_row[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N18 +cycloneive_lcell_comb \sdram_|process_0~2 ( +// Equation(s): +// \sdram_|process_0~2_combout = (\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|process_0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~2 .lut_mask = 16'hFFF0; +defparam \sdram_|process_0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N0 +cycloneive_lcell_comb \sdram_|r.act_row[1]~1 ( +// Equation(s): +// \sdram_|r.act_row[1]~1_combout = (\sdram_|r.act_row[1]~0_combout & (\sdram_|process_0~2_combout & (\sdram_|r.state [7] $ (!\sdram_|r.state [8])))) + + .dataa(\sdram_|r.act_row[1]~0_combout ), + .datab(\sdram_|process_0~2_combout ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.act_row[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.act_row[1]~1 .lut_mask = 16'h8008; +defparam \sdram_|r.act_row[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y13_N9 +dffeas \sdram_|r.act_row[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\z80_|address_pins_|abus[15]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.act_row[1]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[4] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y13_N23 +dffeas \sdram_|r.act_row[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[1]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[3] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N20 +cycloneive_lcell_comb \sdram_|r.act_row[2]~feeder ( +// Equation(s): +// \sdram_|r.act_row[2]~feeder_combout = \z80_|address_pins_|abus[13]~23_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~23_combout ), + .cin(gnd), + .combout(\sdram_|r.act_row[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.act_row[2]~feeder .lut_mask = 16'hFF00; +defparam \sdram_|r.act_row[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y13_N21 +dffeas \sdram_|r.act_row[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.act_row[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.act_row[1]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[2] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N22 +cycloneive_lcell_comb \sdram_|Equal7~1 ( +// Equation(s): +// \sdram_|Equal7~1_combout = (\z80_|address_pins_|abus[14]~22_combout & (\sdram_|r.act_row [3] & (\z80_|address_pins_|abus[13]~23_combout $ (!\sdram_|r.act_row [2])))) # (!\z80_|address_pins_|abus[14]~22_combout & (!\sdram_|r.act_row [3] & +// (\z80_|address_pins_|abus[13]~23_combout $ (!\sdram_|r.act_row [2])))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\sdram_|r.act_row [3]), + .datad(\sdram_|r.act_row [2]), + .cin(gnd), + .combout(\sdram_|Equal7~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal7~1 .lut_mask = 16'h8421; +defparam \sdram_|Equal7~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y13_N3 +dffeas \sdram_|r.act_row[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[12]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[1]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[1] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y13_N13 +dffeas \sdram_|r.act_row[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[11]~19_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[1]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[0] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N2 +cycloneive_lcell_comb \sdram_|Equal7~0 ( +// Equation(s): +// \sdram_|Equal7~0_combout = (\z80_|address_pins_|abus[11]~19_combout & (\sdram_|r.act_row [0] & (\z80_|address_pins_|abus[12]~24_combout $ (!\sdram_|r.act_row [1])))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\sdram_|r.act_row [0] & +// (\z80_|address_pins_|abus[12]~24_combout $ (!\sdram_|r.act_row [1])))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\z80_|address_pins_|abus[12]~24_combout ), + .datac(\sdram_|r.act_row [1]), + .datad(\sdram_|r.act_row [0]), + .cin(gnd), + .combout(\sdram_|Equal7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal7~0 .lut_mask = 16'h8241; +defparam \sdram_|Equal7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N30 +cycloneive_lcell_comb \sdram_|Equal7~2 ( +// Equation(s): +// \sdram_|Equal7~2_combout = (\sdram_|Equal7~1_combout & (\sdram_|Equal7~0_combout & (\z80_|address_pins_|abus[15]~21_combout $ (!\sdram_|r.act_row [4])))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\sdram_|r.act_row [4]), + .datac(\sdram_|Equal7~1_combout ), + .datad(\sdram_|Equal7~0_combout ), + .cin(gnd), + .combout(\sdram_|Equal7~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal7~2 .lut_mask = 16'h9000; +defparam \sdram_|Equal7~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N4 +cycloneive_lcell_comb \sdram_|Mux39~0 ( +// Equation(s): +// \sdram_|Mux39~0_combout = (\sdram_|r.state [5] & (\sdram_|r.state [7] & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & (\sdram_|r.state [8] & (!\sdram_|r.state [7] & !\sdram_|r.state [4]))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux39~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux39~0 .lut_mask = 16'h8024; +defparam \sdram_|Mux39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N12 +cycloneive_lcell_comb \sdram_|Mux39~1 ( +// Equation(s): +// \sdram_|Mux39~1_combout = (\sdram_|r.state [6]) # ((!\sdram_|Mux39~0_combout ) # (!\sdram_|Equal7~2_combout )) + + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|Mux39~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux39~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux39~1 .lut_mask = 16'hAFFF; +defparam \sdram_|Mux39~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N24 +cycloneive_lcell_comb \sdram_|Mux39~2 ( +// Equation(s): +// \sdram_|Mux39~2_combout = (\sdram_|r.wr_pending~q & (\sdram_|Mux39~1_combout )) # (!\sdram_|r.wr_pending~q & (((\z80_|address_pins_|abus[15]~21_combout & \ExtRamWE~0_combout )))) + + .dataa(\sdram_|Mux39~1_combout ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\sdram_|r.wr_pending~q ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux39~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux39~2 .lut_mask = 16'hACA0; +defparam \sdram_|Mux39~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y12_N25 +dffeas \sdram_|r.wr_pending ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux39~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.wr_pending~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.wr_pending .is_wysiwyg = "true"; +defparam \sdram_|r.wr_pending .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N8 +cycloneive_lcell_comb \sdram_|Mux9~8 ( +// Equation(s): +// \sdram_|Mux9~8_combout = (\sdram_|r.state [8] & !\sdram_|r.state [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux9~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~8 .lut_mask = 16'h00F0; +defparam \sdram_|Mux9~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N20 +cycloneive_lcell_comb \sdram_|Mux9~9 ( +// Equation(s): +// \sdram_|Mux9~9_combout = (!\sdram_|r.rd_pending~q & (!\sdram_|r.rf_pending~q & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.wr_pending~q )))) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux9~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~9 .lut_mask = 16'h0405; +defparam \sdram_|Mux9~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N26 +cycloneive_lcell_comb \sdram_|Mux6~3 ( +// Equation(s): +// \sdram_|Mux6~3_combout = (\sdram_|r.state [6] & (((!\sdram_|Mux9~9_combout ) # (!\sdram_|Mux9~8_combout )))) # (!\sdram_|r.state [6] & (\sdram_|r.wr_pending~q & (\sdram_|Mux9~8_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|Mux9~8_combout ), + .datad(\sdram_|Mux9~9_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~3 .lut_mask = 16'h4AEA; +defparam \sdram_|Mux6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N0 +cycloneive_lcell_comb \sdram_|Mux6~4 ( +// Equation(s): +// \sdram_|Mux6~4_combout = (\sdram_|r.state [6]) # ((!\sdram_|r.rf_pending~q & \sdram_|Equal7~2_combout )) + + .dataa(gnd), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux6~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~4 .lut_mask = 16'hFF30; +defparam \sdram_|Mux6~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N6 +cycloneive_lcell_comb \sdram_|Mux6~2 ( +// Equation(s): +// \sdram_|Mux6~2_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [8]) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & ((\sdram_|r.state [4]))) + + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~2 .lut_mask = 16'hF5AA; +defparam \sdram_|Mux6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N10 +cycloneive_lcell_comb \sdram_|Mux6~5 ( +// Equation(s): +// \sdram_|Mux6~5_combout = (\sdram_|r.state [5] & (((\sdram_|Mux6~2_combout )))) # (!\sdram_|r.state [5] & (\sdram_|Mux6~3_combout & (\sdram_|Mux6~4_combout ))) + + .dataa(\sdram_|Mux6~3_combout ), + .datab(\sdram_|Mux6~4_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|Mux6~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~5 .lut_mask = 16'hF808; +defparam \sdram_|Mux6~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N8 +cycloneive_lcell_comb \sdram_|process_0~3 ( +// Equation(s): +// \sdram_|process_0~3_combout = (\sdram_|r.wr_pending~q & \sdram_|Equal7~2_combout ) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(gnd), + .datac(\sdram_|Equal7~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|process_0~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~3 .lut_mask = 16'hA0A0; +defparam \sdram_|process_0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N14 +cycloneive_lcell_comb \sdram_|Mux6~0 ( +// Equation(s): +// \sdram_|Mux6~0_combout = (\sdram_|r.state [8] & (\sdram_|r.state [4] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|process_0~3_combout )))) # (!\sdram_|r.state [8] & (!\sdram_|r.rf_pending~q & (\sdram_|process_0~3_combout & !\sdram_|r.state [4]))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|process_0~3_combout ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~0 .lut_mask = 16'h8A10; +defparam \sdram_|Mux6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N16 +cycloneive_lcell_comb \sdram_|Mux6~1 ( +// Equation(s): +// \sdram_|Mux6~1_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] $ (((\sdram_|r.state [6]) # (\sdram_|Mux6~0_combout ))))) # (!\sdram_|r.state [5] & (\sdram_|r.state [6] & ((\sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|Mux6~0_combout ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~1 .lut_mask = 16'h46A8; +defparam \sdram_|Mux6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N24 +cycloneive_lcell_comb \sdram_|Mux6~6 ( +// Equation(s): +// \sdram_|Mux6~6_combout = (\sdram_|r.state [7] & ((\sdram_|Mux6~1_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux6~5_combout )) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux6~5_combout ), + .datad(\sdram_|Mux6~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~6 .lut_mask = 16'hFC30; +defparam \sdram_|Mux6~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y15_N25 +dffeas \sdram_|r.state[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux6~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[6] .is_wysiwyg = "true"; +defparam \sdram_|r.state[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N12 +cycloneive_lcell_comb \sdram_|r.address[3]~6 ( +// Equation(s): +// \sdram_|r.address[3]~6_combout = (!\sdram_|r.state [6] & (!\sdram_|r.state [7] & !\sdram_|r.state [8])) + + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.address[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~6 .lut_mask = 16'h0005; +defparam \sdram_|r.address[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N22 +cycloneive_lcell_comb \sdram_|Mux7~2 ( +// Equation(s): +// \sdram_|Mux7~2_combout = (!\sdram_|r.state [5] & (\sdram_|r.state [4] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|r.address[3]~6_combout )))) + + .dataa(\sdram_|r.address[3]~6_combout ), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux7~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~2 .lut_mask = 16'h3100; +defparam \sdram_|Mux7~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N12 +cycloneive_lcell_comb \sdram_|n~3 ( +// Equation(s): +// \sdram_|n~3_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q ))) + + .dataa(gnd), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|n~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|n~3 .lut_mask = 16'hFC00; +defparam \sdram_|n~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N6 +cycloneive_lcell_comb \sdram_|Mux7~3 ( +// Equation(s): +// \sdram_|Mux7~3_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [6]) # (!\sdram_|r.rd_pending~q ))) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|r.state [6]), + .datac(gnd), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux7~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~3 .lut_mask = 16'h7700; +defparam \sdram_|Mux7~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N28 +cycloneive_lcell_comb \sdram_|Mux7~4 ( +// Equation(s): +// \sdram_|Mux7~4_combout = (\sdram_|r.state [6] & (\sdram_|Mux7~3_combout & (!\sdram_|r.wr_pending~q & \sdram_|r.state [7]))) # (!\sdram_|r.state [6] & (\sdram_|Mux7~3_combout $ (((\sdram_|r.state [7]))))) + + .dataa(\sdram_|Mux7~3_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux7~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~4 .lut_mask = 16'h1922; +defparam \sdram_|Mux7~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N10 +cycloneive_lcell_comb \sdram_|Mux7~5 ( +// Equation(s): +// \sdram_|Mux7~5_combout = (\sdram_|r.state [6] & (((\sdram_|r.rf_pending~q & \sdram_|Mux7~4_combout )))) # (!\sdram_|r.state [6] & (!\sdram_|Mux7~4_combout & ((\sdram_|r.rf_pending~q ) # (!\sdram_|n~3_combout )))) + + .dataa(\sdram_|n~3_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Mux7~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux7~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~5 .lut_mask = 16'hC031; +defparam \sdram_|Mux7~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N0 +cycloneive_lcell_comb \sdram_|Mux23~0 ( +// Equation(s): +// \sdram_|Mux23~0_combout = (\sdram_|r.state [8] & \sdram_|r.state [6]) + + .dataa(gnd), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [6]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|Mux23~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~0 .lut_mask = 16'hC0C0; +defparam \sdram_|Mux23~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N24 +cycloneive_lcell_comb \sdram_|Mux13~7 ( +// Equation(s): +// \sdram_|Mux13~7_combout = (!\sdram_|r.state [4] & \sdram_|r.state [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), + .cin(gnd), + .combout(\sdram_|Mux13~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~7 .lut_mask = 16'h0F00; +defparam \sdram_|Mux13~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N20 +cycloneive_lcell_comb \sdram_|Mux10~10 ( +// Equation(s): +// \sdram_|Mux10~10_combout = (!\sdram_|r.state [8] & (((\sdram_|r.state [6]) # (\sdram_|r.rf_pending~q )) # (!\sdram_|n~3_combout ))) + + .dataa(\sdram_|n~3_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.rf_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux10~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~10 .lut_mask = 16'h3331; +defparam \sdram_|Mux10~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N18 +cycloneive_lcell_comb \sdram_|Mux7~1 ( +// Equation(s): +// \sdram_|Mux7~1_combout = (\sdram_|Mux13~7_combout & ((\sdram_|Mux23~0_combout ) # ((\sdram_|Mux10~10_combout ) # (!\sdram_|r.state [7])))) + + .dataa(\sdram_|Mux23~0_combout ), + .datab(\sdram_|Mux13~7_combout ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|Mux10~10_combout ), + .cin(gnd), + .combout(\sdram_|Mux7~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~1 .lut_mask = 16'hCC8C; +defparam \sdram_|Mux7~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N22 +cycloneive_lcell_comb \sdram_|Mux7~6 ( +// Equation(s): +// \sdram_|Mux7~6_combout = (\sdram_|Mux7~2_combout ) # ((\sdram_|Mux7~1_combout ) # ((\sdram_|Mux7~5_combout & \sdram_|r.state [8]))) + + .dataa(\sdram_|Mux7~2_combout ), + .datab(\sdram_|Mux7~5_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux7~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux7~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~6 .lut_mask = 16'hFFEA; +defparam \sdram_|Mux7~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y15_N23 +dffeas \sdram_|r.state[5] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux7~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[5] .is_wysiwyg = "true"; +defparam \sdram_|r.state[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N6 +cycloneive_lcell_comb \sdram_|Mux5~2 ( +// Equation(s): +// \sdram_|Mux5~2_combout = (\sdram_|Mux13~7_combout & ((\sdram_|r.state [6]) # ((!\sdram_|Mux4~0_combout & !\sdram_|r.state [8])))) + + .dataa(\sdram_|Mux4~0_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux13~7_combout ), + .cin(gnd), + .combout(\sdram_|Mux5~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~2 .lut_mask = 16'hCD00; +defparam \sdram_|Mux5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N18 +cycloneive_lcell_comb \sdram_|Mux5~10 ( +// Equation(s): +// \sdram_|Mux5~10_combout = (\sdram_|r.state [6] & (\sdram_|r.state [8] & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q )))) # (!\sdram_|r.state [6] & (((!\sdram_|r.state [8])))) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux5~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~10 .lut_mask = 16'hE00F; +defparam \sdram_|Mux5~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N16 +cycloneive_lcell_comb \sdram_|Mux5~3 ( +// Equation(s): +// \sdram_|Mux5~3_combout = ((\sdram_|Mux5~10_combout ) # ((!\sdram_|r.state [6] & !\sdram_|Mux4~0_combout ))) # (!\sdram_|r.state [5]) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|Mux4~0_combout ), + .datad(\sdram_|Mux5~10_combout ), + .cin(gnd), + .combout(\sdram_|Mux5~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~3 .lut_mask = 16'hFF37; +defparam \sdram_|Mux5~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N30 +cycloneive_lcell_comb \sdram_|Mux5~4 ( +// Equation(s): +// \sdram_|Mux5~4_combout = (\sdram_|r.state [7] & ((\sdram_|Mux5~2_combout ) # ((\sdram_|Mux5~3_combout & \sdram_|r.state [4])))) + + .dataa(\sdram_|Mux5~2_combout ), + .datab(\sdram_|Mux5~3_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux5~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~4 .lut_mask = 16'hEA00; +defparam \sdram_|Mux5~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N18 +cycloneive_lcell_comb \sdram_|Mux5~7 ( +// Equation(s): +// \sdram_|Mux5~7_combout = (!\sdram_|r.state [8] & (\sdram_|r.state [4] & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.rd_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux5~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~7 .lut_mask = 16'h4440; +defparam \sdram_|Mux5~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N4 +cycloneive_lcell_comb \sdram_|Mux5~8 ( +// Equation(s): +// \sdram_|Mux5~8_combout = (!\sdram_|r.state [6] & ((\sdram_|r.state [7]) # ((\sdram_|Mux5~7_combout & !\sdram_|r.rf_pending~q )))) + + .dataa(\sdram_|Mux5~7_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux5~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~8 .lut_mask = 16'h3302; +defparam \sdram_|Mux5~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N26 +cycloneive_lcell_comb \sdram_|Mux5~5 ( +// Equation(s): +// \sdram_|Mux5~5_combout = (!\sdram_|r.state [7] & (((\sdram_|r.rf_pending~q ) # (!\sdram_|Equal7~2_combout )) # (!\sdram_|r.rd_pending~q ))) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux5~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~5 .lut_mask = 16'h00DF; +defparam \sdram_|Mux5~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N12 +cycloneive_lcell_comb \sdram_|Mux5~6 ( +// Equation(s): +// \sdram_|Mux5~6_combout = (\sdram_|Mux9~8_combout & ((\sdram_|Mux5~5_combout ) # ((!\sdram_|r.state [6] & \sdram_|process_0~3_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|process_0~3_combout ), + .datac(\sdram_|Mux9~8_combout ), + .datad(\sdram_|Mux5~5_combout ), + .cin(gnd), + .combout(\sdram_|Mux5~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~6 .lut_mask = 16'hF040; +defparam \sdram_|Mux5~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N20 +cycloneive_lcell_comb \sdram_|Mux5~9 ( +// Equation(s): +// \sdram_|Mux5~9_combout = (\sdram_|Mux5~4_combout ) # ((!\sdram_|r.state [5] & ((\sdram_|Mux5~8_combout ) # (\sdram_|Mux5~6_combout )))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|Mux5~4_combout ), + .datac(\sdram_|Mux5~8_combout ), + .datad(\sdram_|Mux5~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux5~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~9 .lut_mask = 16'hDDDC; +defparam \sdram_|Mux5~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y15_N21 +dffeas \sdram_|r.state[7] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux5~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[7] .is_wysiwyg = "true"; +defparam \sdram_|r.state[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N8 +cycloneive_lcell_comb \sdram_|n~2 ( +// Equation(s): +// \sdram_|n~2_combout = (\sdram_|r.rd_pending~q ) # ((\sdram_|r.rf_pending~q ) # (\sdram_|r.wr_pending~q )) + + .dataa(gnd), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|n~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|n~2 .lut_mask = 16'hFFFC; +defparam \sdram_|n~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N8 +cycloneive_lcell_comb \sdram_|Mux8~3 ( +// Equation(s): +// \sdram_|Mux8~3_combout = (\sdram_|r.state [5] & (\sdram_|n~2_combout & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & (((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) + + .dataa(\sdram_|n~2_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux8~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~3 .lut_mask = 16'h8C2F; +defparam \sdram_|Mux8~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N6 +cycloneive_lcell_comb \sdram_|Mux8~4 ( +// Equation(s): +// \sdram_|Mux8~4_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [6] $ (\sdram_|Mux8~3_combout )))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [4] & ((\sdram_|r.state [6]) # (\sdram_|Mux8~3_combout )))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|Mux8~3_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux8~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~4 .lut_mask = 16'h3C54; +defparam \sdram_|Mux8~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N4 +cycloneive_lcell_comb \sdram_|Mux9~10 ( +// Equation(s): +// \sdram_|Mux9~10_combout = (!\sdram_|r.state [4] & ((!\sdram_|r.state [8]) # (!\sdram_|Mux9~9_combout ))) + + .dataa(gnd), + .datab(\sdram_|Mux9~9_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux9~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~10 .lut_mask = 16'h003F; +defparam \sdram_|Mux9~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N28 +cycloneive_lcell_comb \sdram_|r.init_counter[0]~0 ( +// Equation(s): +// \sdram_|r.init_counter[0]~0_combout = !\sdram_|r.init_counter [0] + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.init_counter [0]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.init_counter[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.init_counter[0]~0 .lut_mask = 16'h0F0F; +defparam \sdram_|r.init_counter[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y7_N29 +dffeas \sdram_|r.init_counter[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.init_counter[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[0] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N2 +cycloneive_lcell_comb \sdram_|Add1~1 ( +// Equation(s): +// \sdram_|Add1~1_cout = CARRY(\sdram_|r.init_counter [0]) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\sdram_|Add1~1_cout )); +// synopsys translate_off +defparam \sdram_|Add1~1 .lut_mask = 16'h00CC; +defparam \sdram_|Add1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N4 +cycloneive_lcell_comb \sdram_|Add1~2 ( +// Equation(s): +// \sdram_|Add1~2_combout = (\sdram_|r.init_counter [1] & (\sdram_|Add1~1_cout & VCC)) # (!\sdram_|r.init_counter [1] & (!\sdram_|Add1~1_cout )) +// \sdram_|Add1~3 = CARRY((!\sdram_|r.init_counter [1] & !\sdram_|Add1~1_cout )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~1_cout ), + .combout(\sdram_|Add1~2_combout ), + .cout(\sdram_|Add1~3 )); +// synopsys translate_off +defparam \sdram_|Add1~2 .lut_mask = 16'hC303; +defparam \sdram_|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N5 +dffeas \sdram_|r.init_counter[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[1] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N6 +cycloneive_lcell_comb \sdram_|Add1~4 ( +// Equation(s): +// \sdram_|Add1~4_combout = (\sdram_|r.init_counter [2] & ((GND) # (!\sdram_|Add1~3 ))) # (!\sdram_|r.init_counter [2] & (\sdram_|Add1~3 $ (GND))) +// \sdram_|Add1~5 = CARRY((\sdram_|r.init_counter [2]) # (!\sdram_|Add1~3 )) + + .dataa(\sdram_|r.init_counter [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~3 ), + .combout(\sdram_|Add1~4_combout ), + .cout(\sdram_|Add1~5 )); +// synopsys translate_off +defparam \sdram_|Add1~4 .lut_mask = 16'h5AAF; +defparam \sdram_|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N7 +dffeas \sdram_|r.init_counter[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[2] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N8 +cycloneive_lcell_comb \sdram_|Add1~6 ( +// Equation(s): +// \sdram_|Add1~6_combout = (\sdram_|r.init_counter [3] & (!\sdram_|Add1~5 )) # (!\sdram_|r.init_counter [3] & (\sdram_|Add1~5 & VCC)) +// \sdram_|Add1~7 = CARRY((\sdram_|r.init_counter [3] & !\sdram_|Add1~5 )) + + .dataa(\sdram_|r.init_counter [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~5 ), + .combout(\sdram_|Add1~6_combout ), + .cout(\sdram_|Add1~7 )); +// synopsys translate_off +defparam \sdram_|Add1~6 .lut_mask = 16'h5A0A; +defparam \sdram_|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N2 +cycloneive_lcell_comb \sdram_|r.init_counter[3]~1 ( +// Equation(s): +// \sdram_|r.init_counter[3]~1_combout = !\sdram_|Add1~6_combout + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|Add1~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.init_counter[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.init_counter[3]~1 .lut_mask = 16'h0F0F; +defparam \sdram_|r.init_counter[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y3_N3 +dffeas \sdram_|r.init_counter[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.init_counter[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[3] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N10 +cycloneive_lcell_comb \sdram_|Add1~8 ( +// Equation(s): +// \sdram_|Add1~8_combout = (\sdram_|r.init_counter [4] & ((GND) # (!\sdram_|Add1~7 ))) # (!\sdram_|r.init_counter [4] & (\sdram_|Add1~7 $ (GND))) +// \sdram_|Add1~9 = CARRY((\sdram_|r.init_counter [4]) # (!\sdram_|Add1~7 )) + + .dataa(\sdram_|r.init_counter [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~7 ), + .combout(\sdram_|Add1~8_combout ), + .cout(\sdram_|Add1~9 )); +// synopsys translate_off +defparam \sdram_|Add1~8 .lut_mask = 16'h5AAF; +defparam \sdram_|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N11 +dffeas \sdram_|r.init_counter[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[4] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N12 +cycloneive_lcell_comb \sdram_|Add1~10 ( +// Equation(s): +// \sdram_|Add1~10_combout = (\sdram_|r.init_counter [5] & (\sdram_|Add1~9 & VCC)) # (!\sdram_|r.init_counter [5] & (!\sdram_|Add1~9 )) +// \sdram_|Add1~11 = CARRY((!\sdram_|r.init_counter [5] & !\sdram_|Add1~9 )) + + .dataa(\sdram_|r.init_counter [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~9 ), + .combout(\sdram_|Add1~10_combout ), + .cout(\sdram_|Add1~11 )); +// synopsys translate_off +defparam \sdram_|Add1~10 .lut_mask = 16'hA505; +defparam \sdram_|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N13 +dffeas \sdram_|r.init_counter[5] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[5] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N14 +cycloneive_lcell_comb \sdram_|Add1~12 ( +// Equation(s): +// \sdram_|Add1~12_combout = (\sdram_|r.init_counter [6] & ((GND) # (!\sdram_|Add1~11 ))) # (!\sdram_|r.init_counter [6] & (\sdram_|Add1~11 $ (GND))) +// \sdram_|Add1~13 = CARRY((\sdram_|r.init_counter [6]) # (!\sdram_|Add1~11 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~11 ), + .combout(\sdram_|Add1~12_combout ), + .cout(\sdram_|Add1~13 )); +// synopsys translate_off +defparam \sdram_|Add1~12 .lut_mask = 16'h3CCF; +defparam \sdram_|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N15 +dffeas \sdram_|r.init_counter[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[6] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N16 +cycloneive_lcell_comb \sdram_|Add1~14 ( +// Equation(s): +// \sdram_|Add1~14_combout = (\sdram_|r.init_counter [7] & (\sdram_|Add1~13 & VCC)) # (!\sdram_|r.init_counter [7] & (!\sdram_|Add1~13 )) +// \sdram_|Add1~15 = CARRY((!\sdram_|r.init_counter [7] & !\sdram_|Add1~13 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~13 ), + .combout(\sdram_|Add1~14_combout ), + .cout(\sdram_|Add1~15 )); +// synopsys translate_off +defparam \sdram_|Add1~14 .lut_mask = 16'hC303; +defparam \sdram_|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N17 +dffeas \sdram_|r.init_counter[7] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~14_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[7] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N18 +cycloneive_lcell_comb \sdram_|Add1~16 ( +// Equation(s): +// \sdram_|Add1~16_combout = (\sdram_|r.init_counter [8] & ((GND) # (!\sdram_|Add1~15 ))) # (!\sdram_|r.init_counter [8] & (\sdram_|Add1~15 $ (GND))) +// \sdram_|Add1~17 = CARRY((\sdram_|r.init_counter [8]) # (!\sdram_|Add1~15 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~15 ), + .combout(\sdram_|Add1~16_combout ), + .cout(\sdram_|Add1~17 )); +// synopsys translate_off +defparam \sdram_|Add1~16 .lut_mask = 16'h3CCF; +defparam \sdram_|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N19 +dffeas \sdram_|r.init_counter[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[8] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N20 +cycloneive_lcell_comb \sdram_|Add1~18 ( +// Equation(s): +// \sdram_|Add1~18_combout = (\sdram_|r.init_counter [9] & (\sdram_|Add1~17 & VCC)) # (!\sdram_|r.init_counter [9] & (!\sdram_|Add1~17 )) +// \sdram_|Add1~19 = CARRY((!\sdram_|r.init_counter [9] & !\sdram_|Add1~17 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [9]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~17 ), + .combout(\sdram_|Add1~18_combout ), + .cout(\sdram_|Add1~19 )); +// synopsys translate_off +defparam \sdram_|Add1~18 .lut_mask = 16'hC303; +defparam \sdram_|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N21 +dffeas \sdram_|r.init_counter[9] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[9] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N22 +cycloneive_lcell_comb \sdram_|Add1~20 ( +// Equation(s): +// \sdram_|Add1~20_combout = (\sdram_|r.init_counter [10] & ((GND) # (!\sdram_|Add1~19 ))) # (!\sdram_|r.init_counter [10] & (\sdram_|Add1~19 $ (GND))) +// \sdram_|Add1~21 = CARRY((\sdram_|r.init_counter [10]) # (!\sdram_|Add1~19 )) + + .dataa(\sdram_|r.init_counter [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~19 ), + .combout(\sdram_|Add1~20_combout ), + .cout(\sdram_|Add1~21 )); +// synopsys translate_off +defparam \sdram_|Add1~20 .lut_mask = 16'h5AAF; +defparam \sdram_|Add1~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N23 +dffeas \sdram_|r.init_counter[10] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~20_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[10] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N22 +cycloneive_lcell_comb \sdram_|Equal2~0 ( +// Equation(s): +// \sdram_|Equal2~0_combout = (!\sdram_|r.init_counter [9] & (!\sdram_|r.init_counter [8] & (!\sdram_|r.init_counter [4] & !\sdram_|r.init_counter [10]))) + + .dataa(\sdram_|r.init_counter [9]), + .datab(\sdram_|r.init_counter [8]), + .datac(\sdram_|r.init_counter [4]), + .datad(\sdram_|r.init_counter [10]), + .cin(gnd), + .combout(\sdram_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~0 .lut_mask = 16'h0001; +defparam \sdram_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N0 +cycloneive_lcell_comb \sdram_|Equal2~1 ( +// Equation(s): +// \sdram_|Equal2~1_combout = (!\sdram_|r.init_counter [6] & (!\sdram_|r.init_counter [5] & \sdram_|r.init_counter [3])) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [6]), + .datac(\sdram_|r.init_counter [5]), + .datad(\sdram_|r.init_counter [3]), + .cin(gnd), + .combout(\sdram_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~1 .lut_mask = 16'h0300; +defparam \sdram_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N24 +cycloneive_lcell_comb \sdram_|Add1~22 ( +// Equation(s): +// \sdram_|Add1~22_combout = (\sdram_|r.init_counter [11] & (\sdram_|Add1~21 & VCC)) # (!\sdram_|r.init_counter [11] & (!\sdram_|Add1~21 )) +// \sdram_|Add1~23 = CARRY((!\sdram_|r.init_counter [11] & !\sdram_|Add1~21 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [11]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~21 ), + .combout(\sdram_|Add1~22_combout ), + .cout(\sdram_|Add1~23 )); +// synopsys translate_off +defparam \sdram_|Add1~22 .lut_mask = 16'hC303; +defparam \sdram_|Add1~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N25 +dffeas \sdram_|r.init_counter[11] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[11] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N26 +cycloneive_lcell_comb \sdram_|Add1~24 ( +// Equation(s): +// \sdram_|Add1~24_combout = (\sdram_|r.init_counter [12] & ((GND) # (!\sdram_|Add1~23 ))) # (!\sdram_|r.init_counter [12] & (\sdram_|Add1~23 $ (GND))) +// \sdram_|Add1~25 = CARRY((\sdram_|r.init_counter [12]) # (!\sdram_|Add1~23 )) + + .dataa(\sdram_|r.init_counter [12]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~23 ), + .combout(\sdram_|Add1~24_combout ), + .cout(\sdram_|Add1~25 )); +// synopsys translate_off +defparam \sdram_|Add1~24 .lut_mask = 16'h5AAF; +defparam \sdram_|Add1~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N27 +dffeas \sdram_|r.init_counter[12] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[12] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N28 +cycloneive_lcell_comb \sdram_|Add1~26 ( +// Equation(s): +// \sdram_|Add1~26_combout = (\sdram_|r.init_counter [13] & (\sdram_|Add1~25 & VCC)) # (!\sdram_|r.init_counter [13] & (!\sdram_|Add1~25 )) +// \sdram_|Add1~27 = CARRY((!\sdram_|r.init_counter [13] & !\sdram_|Add1~25 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [13]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~25 ), + .combout(\sdram_|Add1~26_combout ), + .cout(\sdram_|Add1~27 )); +// synopsys translate_off +defparam \sdram_|Add1~26 .lut_mask = 16'hC303; +defparam \sdram_|Add1~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N29 +dffeas \sdram_|r.init_counter[13] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~26_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[13] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N30 +cycloneive_lcell_comb \sdram_|Add1~28 ( +// Equation(s): +// \sdram_|Add1~28_combout = \sdram_|r.init_counter [14] $ (\sdram_|Add1~27 ) + + .dataa(\sdram_|r.init_counter [14]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sdram_|Add1~27 ), + .combout(\sdram_|Add1~28_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Add1~28 .lut_mask = 16'h5A5A; +defparam \sdram_|Add1~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N31 +dffeas \sdram_|r.init_counter[14] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~28_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[14] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N0 +cycloneive_lcell_comb \sdram_|process_0~5 ( +// Equation(s): +// \sdram_|process_0~5_combout = (!\sdram_|r.init_counter [14] & (!\sdram_|r.init_counter [11] & (!\sdram_|r.init_counter [12] & !\sdram_|r.init_counter [13]))) + + .dataa(\sdram_|r.init_counter [14]), + .datab(\sdram_|r.init_counter [11]), + .datac(\sdram_|r.init_counter [12]), + .datad(\sdram_|r.init_counter [13]), + .cin(gnd), + .combout(\sdram_|process_0~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~5 .lut_mask = 16'h0001; +defparam \sdram_|process_0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N6 +cycloneive_lcell_comb \sdram_|Equal2~2 ( +// Equation(s): +// \sdram_|Equal2~2_combout = (\sdram_|Equal2~0_combout & (\sdram_|Equal2~1_combout & (\sdram_|process_0~5_combout & !\sdram_|r.init_counter [2]))) + + .dataa(\sdram_|Equal2~0_combout ), + .datab(\sdram_|Equal2~1_combout ), + .datac(\sdram_|process_0~5_combout ), + .datad(\sdram_|r.init_counter [2]), + .cin(gnd), + .combout(\sdram_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~2 .lut_mask = 16'h0080; +defparam \sdram_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N10 +cycloneive_lcell_comb \sdram_|Mux9~11 ( +// Equation(s): +// \sdram_|Mux9~11_combout = (!\sdram_|r.init_counter [1] & (\sdram_|r.init_counter [0] & !\sdram_|r.init_counter [7])) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [0]), + .datac(gnd), + .datad(\sdram_|r.init_counter [7]), + .cin(gnd), + .combout(\sdram_|Mux9~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~11 .lut_mask = 16'h0044; +defparam \sdram_|Mux9~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N24 +cycloneive_lcell_comb \sdram_|Mux9~12 ( +// Equation(s): +// \sdram_|Mux9~12_combout = (\sdram_|r.state [4] & (!\sdram_|n~2_combout )) # (!\sdram_|r.state [4] & (((\sdram_|Equal2~2_combout & \sdram_|Mux9~11_combout )))) + + .dataa(\sdram_|n~2_combout ), + .datab(\sdram_|Equal2~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|Mux9~11_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~12 .lut_mask = 16'h5C50; +defparam \sdram_|Mux9~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N0 +cycloneive_lcell_comb \sdram_|Mux9~13 ( +// Equation(s): +// \sdram_|Mux9~13_combout = (\sdram_|r.state [8] & (!\sdram_|r.state [4] & (\sdram_|n~2_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux9~12_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|n~2_combout ), + .datad(\sdram_|Mux9~12_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~13_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~13 .lut_mask = 16'h7520; +defparam \sdram_|Mux9~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N2 +cycloneive_lcell_comb \sdram_|Mux8~0 ( +// Equation(s): +// \sdram_|Mux8~0_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [5]) # ((\sdram_|Mux9~10_combout )))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [5] & ((\sdram_|Mux9~13_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|Mux9~10_combout ), + .datad(\sdram_|Mux9~13_combout ), + .cin(gnd), + .combout(\sdram_|Mux8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~0 .lut_mask = 16'hB9A8; +defparam \sdram_|Mux8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N16 +cycloneive_lcell_comb \sdram_|Mux8~1 ( +// Equation(s): +// \sdram_|Mux8~1_combout = (\sdram_|r.state [5] & (((!\sdram_|r.state [8] & \sdram_|Mux8~0_combout )) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [5] & (((\sdram_|Mux8~0_combout )))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|Mux8~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux8~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~1 .lut_mask = 16'h7F50; +defparam \sdram_|Mux8~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N20 +cycloneive_lcell_comb \sdram_|Mux8~2 ( +// Equation(s): +// \sdram_|Mux8~2_combout = (\sdram_|r.state [7] & (\sdram_|Mux8~4_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux8~1_combout ))) + + .dataa(\sdram_|r.state [7]), + .datab(gnd), + .datac(\sdram_|Mux8~4_combout ), + .datad(\sdram_|Mux8~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux8~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~2 .lut_mask = 16'hF5A0; +defparam \sdram_|Mux8~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y15_N21 +dffeas \sdram_|r.state[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux8~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[4] .is_wysiwyg = "true"; +defparam \sdram_|r.state[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N4 +cycloneive_lcell_comb \sdram_|Mux72~0 ( +// Equation(s): +// \sdram_|Mux72~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [0]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux72~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux72~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux72~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N2 +cycloneive_lcell_comb \sdram_|Mux72~1 ( +// Equation(s): +// \sdram_|Mux72~1_combout = (\sdram_|Mux72~0_combout & ((\D[0]~64_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\sdram_|Mux72~0_combout ), + .datad(\D[0]~64_combout ), + .cin(gnd), + .combout(\sdram_|Mux72~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux72~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux72~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N0 +cycloneive_lcell_comb \sdram_|Mux84~0 ( +// Equation(s): +// \sdram_|Mux84~0_combout = (\sdram_|r.state [5]) # (\sdram_|r.state [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux84~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux84~0 .lut_mask = 16'hFFF0; +defparam \sdram_|Mux84~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N2 +cycloneive_lcell_comb \sdram_|Mux84~1 ( +// Equation(s): +// \sdram_|Mux84~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [7] & (!\sdram_|r.state [8] & \sdram_|Mux84~0_combout ))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [7] & (\sdram_|r.state [8] & !\sdram_|Mux84~0_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux84~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux84~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux84~1 .lut_mask = 16'h0810; +defparam \sdram_|Mux84~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N16 +cycloneive_lcell_comb \sdram_|Mux3~0 ( +// Equation(s): +// \sdram_|Mux3~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [1]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux3~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N18 +cycloneive_lcell_comb \sdram_|Mux3~1 ( +// Equation(s): +// \sdram_|Mux3~1_combout = (\sdram_|Mux3~0_combout & ((\D[1]~40_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\sdram_|Mux3~0_combout ), + .datad(\D[1]~40_combout ), + .cin(gnd), + .combout(\sdram_|Mux3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux3~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N0 +cycloneive_lcell_comb \sdram_|Mux2~0 ( +// Equation(s): +// \sdram_|Mux2~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [2]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux2~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N30 +cycloneive_lcell_comb \sdram_|Mux2~1 ( +// Equation(s): +// \sdram_|Mux2~1_combout = (\sdram_|Mux2~0_combout & ((\D[2]~52_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\sdram_|Mux2~0_combout ), + .datad(\D[2]~52_combout ), + .cin(gnd), + .combout(\sdram_|Mux2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux2~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N28 +cycloneive_lcell_comb \sdram_|Mux1~0 ( +// Equation(s): +// \sdram_|Mux1~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [3]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux1~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N10 +cycloneive_lcell_comb \sdram_|Mux1~1 ( +// Equation(s): +// \sdram_|Mux1~1_combout = (\sdram_|Mux1~0_combout & ((\D[3]~108_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\D[3]~108_combout ), + .datad(\sdram_|Mux1~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux1~1 .lut_mask = 16'hF100; +defparam \sdram_|Mux1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N12 +cycloneive_lcell_comb \sdram_|Mux0~0 ( +// Equation(s): +// \sdram_|Mux0~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [4]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux0~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N26 +cycloneive_lcell_comb \sdram_|Mux0~1 ( +// Equation(s): +// \sdram_|Mux0~1_combout = (\sdram_|Mux0~0_combout & ((\D[4]~110_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\sdram_|Mux0~0_combout ), + .datad(\D[4]~110_combout ), + .cin(gnd), + .combout(\sdram_|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux0~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N8 +cycloneive_lcell_comb \sdram_|Mux73~0 ( +// Equation(s): +// \sdram_|Mux73~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [5]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux73~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux73~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux73~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N14 +cycloneive_lcell_comb \sdram_|Mux73~1 ( +// Equation(s): +// \sdram_|Mux73~1_combout = (\sdram_|Mux73~0_combout & ((\D[5]~112_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\sdram_|Mux73~0_combout ), + .datad(\D[5]~112_combout ), + .cin(gnd), + .combout(\sdram_|Mux73~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux73~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux73~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N24 +cycloneive_lcell_comb \sdram_|Mux74~0 ( +// Equation(s): +// \sdram_|Mux74~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [6]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux74~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux74~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux74~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N6 +cycloneive_lcell_comb \sdram_|Mux74~1 ( +// Equation(s): +// \sdram_|Mux74~1_combout = (\sdram_|Mux74~0_combout & ((\D[6]~114_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\sdram_|Mux74~0_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[6]~114_combout ), + .cin(gnd), + .combout(\sdram_|Mux74~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux74~1 .lut_mask = 16'hCC04; +defparam \sdram_|Mux74~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y4_N28 +cycloneive_lcell_comb \sdram_|Mux75~0 ( +// Equation(s): +// \sdram_|Mux75~0_combout = (\sdram_|r.state [4] & \D[7]~117_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\D[7]~117_combout ), + .cin(gnd), + .combout(\sdram_|Mux75~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux75~0 .lut_mask = 16'hF000; +defparam \sdram_|Mux75~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y32_N8 cycloneive_lcell_comb \ula_|i2s_intf_|mclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|mclk_r~0_combout = !\ula_|i2s_intf_|mclk_r~_Duplicate_1_q @@ -55715,7 +59007,7 @@ defparam \ula_|i2s_intf_|mclk_r~0 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|mclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y23_N17 +// Location: FF_X20_Y32_N9 dffeas \ula_|i2s_intf_|mclk_r~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|mclk_r~0_combout ), @@ -55753,24 +59045,24 @@ defparam \ula_|i2s_intf_|mclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|mclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N6 +// Location: LCCOMB_X20_Y31_N12 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~1 ( // Equation(s): // \ula_|i2s_intf_|Add0~1_cout = CARRY(!\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ) - .dataa(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), .datac(gnd), .datad(vcc), .cin(gnd), .combout(), .cout(\ula_|i2s_intf_|Add0~1_cout )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0033; defparam \ula_|i2s_intf_|Add0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N8 +// Location: LCCOMB_X20_Y31_N14 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~2 ( // Equation(s): // \ula_|i2s_intf_|Add0~2_combout = (\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Add0~1_cout & VCC)) # (!\ula_|i2s_intf_|lrdivider [1] & (!\ula_|i2s_intf_|Add0~1_cout )) @@ -55788,24 +59080,24 @@ defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hC303; defparam \ula_|i2s_intf_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N28 +// Location: LCCOMB_X20_Y31_N0 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~2 ( // Equation(s): -// \ula_|i2s_intf_|lrdivider~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~2_combout ) +// \ula_|i2s_intf_|lrdivider~2_combout = (\ula_|i2s_intf_|Add0~2_combout & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(gnd), .datab(gnd), .datac(\ula_|i2s_intf_|Add0~2_combout ), - .datad(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h5050; +defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h00F0; defparam \ula_|i2s_intf_|lrdivider~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N29 +// Location: FF_X20_Y31_N1 dffeas \ula_|i2s_intf_|lrdivider[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~2_combout ), @@ -55824,7 +59116,7 @@ defparam \ula_|i2s_intf_|lrdivider[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N10 +// Location: LCCOMB_X20_Y31_N16 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~4 ( // Equation(s): // \ula_|i2s_intf_|Add0~4_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|Add0~3 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add0~3 ))) @@ -55842,24 +59134,24 @@ defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hA55F; defparam \ula_|i2s_intf_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X30_Y23_N6 +// Location: LCCOMB_X21_Y31_N6 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[2]~8 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[2]~8_combout = !\ula_|i2s_intf_|Add0~4_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~4_combout ), + .datac(\ula_|i2s_intf_|Add0~4_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[2]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[2]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y23_N7 +// Location: FF_X21_Y31_N7 dffeas \ula_|i2s_intf_|lrdivider[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[2]~8_combout ), @@ -55878,42 +59170,42 @@ defparam \ula_|i2s_intf_|lrdivider[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N12 +// Location: LCCOMB_X20_Y31_N18 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~6 ( // Equation(s): // \ula_|i2s_intf_|Add0~6_combout = (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|Add0~5 )) # (!\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|Add0~5 & VCC)) // \ula_|i2s_intf_|Add0~7 = CARRY((\ula_|i2s_intf_|lrdivider [3] & !\ula_|i2s_intf_|Add0~5 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [3]), + .dataa(\ula_|i2s_intf_|lrdivider [3]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~5 ), .combout(\ula_|i2s_intf_|Add0~6_combout ), .cout(\ula_|i2s_intf_|Add0~7 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h3C0C; +defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h5A0A; defparam \ula_|i2s_intf_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N6 +// Location: LCCOMB_X20_Y32_N30 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[3]~7 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[3]~7_combout = !\ula_|i2s_intf_|Add0~6_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~6_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~6_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[3]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[3]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N7 +// Location: FF_X20_Y32_N31 dffeas \ula_|i2s_intf_|lrdivider[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[3]~7_combout ), @@ -55932,7 +59224,7 @@ defparam \ula_|i2s_intf_|lrdivider[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N14 +// Location: LCCOMB_X20_Y31_N20 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~8 ( // Equation(s): // \ula_|i2s_intf_|Add0~8_combout = (\ula_|i2s_intf_|lrdivider [4] & ((GND) # (!\ula_|i2s_intf_|Add0~7 ))) # (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|Add0~7 $ (GND))) @@ -55950,24 +59242,24 @@ defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N4 +// Location: LCCOMB_X20_Y31_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~1 ( // Equation(s): -// \ula_|i2s_intf_|lrdivider~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~8_combout ) +// \ula_|i2s_intf_|lrdivider~1_combout = (\ula_|i2s_intf_|Add0~8_combout & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~8_combout ), - .datad(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|Add0~8_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h5050; +defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h00CC; defparam \ula_|i2s_intf_|lrdivider~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N5 +// Location: FF_X20_Y31_N5 dffeas \ula_|i2s_intf_|lrdivider[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~1_combout ), @@ -55986,25 +59278,25 @@ defparam \ula_|i2s_intf_|lrdivider[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N16 +// Location: LCCOMB_X20_Y31_N22 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~10 ( // Equation(s): // \ula_|i2s_intf_|Add0~10_combout = (\ula_|i2s_intf_|lrdivider [5] & (!\ula_|i2s_intf_|Add0~9 )) # (!\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|Add0~9 & VCC)) // \ula_|i2s_intf_|Add0~11 = CARRY((\ula_|i2s_intf_|lrdivider [5] & !\ula_|i2s_intf_|Add0~9 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [5]), + .dataa(\ula_|i2s_intf_|lrdivider [5]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~9 ), .combout(\ula_|i2s_intf_|Add0~10_combout ), .cout(\ula_|i2s_intf_|Add0~11 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h3C0C; +defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h5A0A; defparam \ula_|i2s_intf_|Add0~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N2 +// Location: LCCOMB_X21_Y31_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[5]~6 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[5]~6_combout = !\ula_|i2s_intf_|Add0~10_combout @@ -56021,7 +59313,7 @@ defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[5]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N3 +// Location: FF_X21_Y31_N5 dffeas \ula_|i2s_intf_|lrdivider[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[5]~6_combout ), @@ -56040,7 +59332,7 @@ defparam \ula_|i2s_intf_|lrdivider[5] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N26 +// Location: LCCOMB_X20_Y31_N10 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~1 ( // Equation(s): // \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [2] & (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|lrdivider [3] & \ula_|i2s_intf_|lrdivider [5]))) @@ -56057,25 +59349,25 @@ defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h2000; defparam \ula_|i2s_intf_|Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N18 +// Location: LCCOMB_X20_Y31_N24 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~12 ( // Equation(s): // \ula_|i2s_intf_|Add0~12_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|Add0~11 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [6] & ((GND) # (!\ula_|i2s_intf_|Add0~11 ))) // \ula_|i2s_intf_|Add0~13 = CARRY((!\ula_|i2s_intf_|Add0~11 ) # (!\ula_|i2s_intf_|lrdivider [6])) - .dataa(\ula_|i2s_intf_|lrdivider [6]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [6]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~11 ), .combout(\ula_|i2s_intf_|Add0~12_combout ), .cout(\ula_|i2s_intf_|Add0~13 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hC33F; defparam \ula_|i2s_intf_|Add0~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N26 +// Location: LCCOMB_X21_Y31_N22 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[6]~5 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[6]~5_combout = !\ula_|i2s_intf_|Add0~12_combout @@ -56092,7 +59384,7 @@ defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[6]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N27 +// Location: FF_X21_Y31_N23 dffeas \ula_|i2s_intf_|lrdivider[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[6]~5_combout ), @@ -56111,7 +59403,7 @@ defparam \ula_|i2s_intf_|lrdivider[6] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N20 +// Location: LCCOMB_X20_Y31_N26 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~14 ( // Equation(s): // \ula_|i2s_intf_|Add0~14_combout = (\ula_|i2s_intf_|lrdivider [7] & (!\ula_|i2s_intf_|Add0~13 )) # (!\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|Add0~13 & VCC)) @@ -56129,24 +59421,24 @@ defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h5A0A; defparam \ula_|i2s_intf_|Add0~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X30_Y23_N4 +// Location: LCCOMB_X21_Y31_N20 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[7]~4 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[7]~4_combout = !\ula_|i2s_intf_|Add0~14_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~14_combout ), + .datac(\ula_|i2s_intf_|Add0~14_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[7]~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[7]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y23_N5 +// Location: FF_X21_Y31_N21 dffeas \ula_|i2s_intf_|lrdivider[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[7]~4_combout ), @@ -56165,42 +59457,42 @@ defparam \ula_|i2s_intf_|lrdivider[7] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N22 +// Location: LCCOMB_X20_Y31_N28 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~16 ( // Equation(s): // \ula_|i2s_intf_|Add0~16_combout = (\ula_|i2s_intf_|lrdivider [8] & ((GND) # (!\ula_|i2s_intf_|Add0~15 ))) # (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|Add0~15 $ (GND))) // \ula_|i2s_intf_|Add0~17 = CARRY((\ula_|i2s_intf_|lrdivider [8]) # (!\ula_|i2s_intf_|Add0~15 )) - .dataa(\ula_|i2s_intf_|lrdivider [8]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [8]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~15 ), .combout(\ula_|i2s_intf_|Add0~16_combout ), .cout(\ula_|i2s_intf_|Add0~17 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h5AAF; +defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|Add0~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N16 +// Location: LCCOMB_X20_Y31_N8 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~0 ( // Equation(s): // \ula_|i2s_intf_|lrdivider~0_combout = (\ula_|i2s_intf_|Add0~16_combout & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), .datab(\ula_|i2s_intf_|Add0~16_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h0C0C; +defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h00CC; defparam \ula_|i2s_intf_|lrdivider~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N17 +// Location: FF_X20_Y31_N9 dffeas \ula_|i2s_intf_|lrdivider[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~0_combout ), @@ -56219,7 +59511,7 @@ defparam \ula_|i2s_intf_|lrdivider[8] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N24 +// Location: LCCOMB_X20_Y31_N30 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~18 ( // Equation(s): // \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|Add0~17 $ (\ula_|i2s_intf_|lrdivider [9]) @@ -56236,24 +59528,24 @@ defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h0FF0; defparam \ula_|i2s_intf_|Add0~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N24 +// Location: LCCOMB_X19_Y31_N24 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[9]~3 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[9]~3_combout = !\ula_|i2s_intf_|Add0~18_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~18_combout ), + .datac(\ula_|i2s_intf_|Add0~18_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[9]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[9]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N25 +// Location: FF_X19_Y31_N25 dffeas \ula_|i2s_intf_|lrdivider[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[9]~3_combout ), @@ -56272,32 +59564,32 @@ defparam \ula_|i2s_intf_|lrdivider[9] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N0 +// Location: LCCOMB_X20_Y31_N6 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~0 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~0_combout = (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|lrdivider [9] & (\ula_|i2s_intf_|lrdivider [6] & \ula_|i2s_intf_|lrdivider [7]))) +// \ula_|i2s_intf_|Equal0~0_combout = (\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|lrdivider [9] & (!\ula_|i2s_intf_|lrdivider [8] & \ula_|i2s_intf_|lrdivider [6]))) - .dataa(\ula_|i2s_intf_|lrdivider [8]), + .dataa(\ula_|i2s_intf_|lrdivider [7]), .datab(\ula_|i2s_intf_|lrdivider [9]), - .datac(\ula_|i2s_intf_|lrdivider [6]), - .datad(\ula_|i2s_intf_|lrdivider [7]), + .datac(\ula_|i2s_intf_|lrdivider [8]), + .datad(\ula_|i2s_intf_|lrdivider [6]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h4000; +defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h0800; defparam \ula_|i2s_intf_|Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N30 +// Location: LCCOMB_X20_Y31_N2 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~2 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & \ula_|i2s_intf_|Equal0~0_combout ))) +// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Equal0~0_combout & \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ))) .dataa(\ula_|i2s_intf_|Equal0~1_combout ), .datab(\ula_|i2s_intf_|lrdivider [1]), - .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|Equal0~0_combout ), + .datac(\ula_|i2s_intf_|Equal0~0_combout ), + .datad(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~2_combout ), .cout()); @@ -56306,32 +59598,15 @@ defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h2000; defparam \ula_|i2s_intf_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder ( -// Equation(s): -// \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout = \ula_|i2s_intf_|lrclk_r~0_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .lut_mask = 16'hFF00; -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N25 +// Location: FF_X23_Y32_N29 dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|i2s_intf_|lrclk_r~0_combout ), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -56342,7 +59617,7 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N0 +// Location: LCCOMB_X23_Y32_N30 cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|Equal0~2_combout $ (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ) @@ -56397,516 +59672,13 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] -// \ula_|i2s_intf_|bitcount[0]~6 = CARRY(!\ula_|i2s_intf_|bitcount [0]) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [0]), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|bitcount[0]~5_combout ), - .cout(\ula_|i2s_intf_|bitcount[0]~6 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; -defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N11 -dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bclk_r~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & !\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hF0FC; -defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N1 -dffeas \ula_|i2s_intf_|bitcount[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) -// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[0]~6 ), - .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .cout(\ula_|i2s_intf_|bitcount[1]~8 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y22_N3 -dffeas \ula_|i2s_intf_|bitcount[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) -// \ula_|i2s_intf_|bitcount[2]~10 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[1]~8 ), - .combout(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .cout(\ula_|i2s_intf_|bitcount[2]~10 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; -defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y22_N5 -dffeas \ula_|i2s_intf_|bitcount[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N6 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) -// \ula_|i2s_intf_|bitcount[3]~12 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~10 )) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[2]~10 ), - .combout(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .cout(\ula_|i2s_intf_|bitcount[3]~12 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hA505; -defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y22_N7 -dffeas \ula_|i2s_intf_|bitcount[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( -// Equation(s): -// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # (((\ula_|i2s_intf_|bitcount [2]) # (\ula_|i2s_intf_|bitcount [1])) # (!\ula_|i2s_intf_|bitcount [0])) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(\ula_|i2s_intf_|bitcount [0]), - .datac(\ula_|i2s_intf_|bitcount [2]), - .datad(\ula_|i2s_intf_|bitcount [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFFB; -defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [4]), - .datac(gnd), - .datad(gnd), - .cin(\ula_|i2s_intf_|bitcount[3]~12 ), - .combout(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h3C3C; -defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y22_N9 -dffeas \ula_|i2s_intf_|bitcount[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(), - .cout(\ula_|i2s_intf_|Add2~7_cout )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; -defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) -// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) - - .dataa(\ula_|i2s_intf_|bdivider [1]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~7_cout ), - .combout(\ula_|i2s_intf_|Add2~8_combout ), - .cout(\ula_|i2s_intf_|Add2~9 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hA505; -defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Equal1~0_combout ), - .datad(\ula_|i2s_intf_|Add2~8_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h1300; -defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N13 -dffeas \ula_|i2s_intf_|bdivider[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~20_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) -// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) - - .dataa(\ula_|i2s_intf_|bdivider [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~9 ), - .combout(\ula_|i2s_intf_|Add2~10_combout ), - .cout(\ula_|i2s_intf_|Add2~11 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hA55F; -defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add2~10_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h0203; -defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N17 -dffeas \ula_|i2s_intf_|bdivider[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~17_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) -// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~11 ), - .combout(\ula_|i2s_intf_|Add2~12_combout ), - .cout(\ula_|i2s_intf_|Add2~13 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~19_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~12_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Equal1~0_combout ), - .datad(\ula_|i2s_intf_|Add2~12_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h1300; -defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N3 -dffeas \ula_|i2s_intf_|bdivider[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~19_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|bdivider [4]), - .cin(\ula_|i2s_intf_|Add2~13 ), - .combout(\ula_|i2s_intf_|Add2~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; -defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add2~14_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0203; -defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N19 -dffeas \ula_|i2s_intf_|bdivider[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( -// Equation(s): -// \ula_|i2s_intf_|Equal1~0_combout = (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|bdivider [2] & \ula_|i2s_intf_|bdivider [4]))) - - .dataa(\ula_|i2s_intf_|bdivider [1]), - .datab(\ula_|i2s_intf_|bdivider [3]), - .datac(\ula_|i2s_intf_|bdivider [2]), - .datad(\ula_|i2s_intf_|bdivider [4]), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h1000; -defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~1 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[4]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|LessThan0~0_combout ), - .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4]~1 .lut_mask = 16'h8A00; -defparam \ula_|i2s_intf_|shiftreg[4]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N12 +// Location: LCCOMB_X23_Y32_N8 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( // Equation(s): -// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[4]~1_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) +// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(\ula_|i2s_intf_|bdivider [0]), .datad(\ula_|i2s_intf_|Equal1~0_combout ), .cin(gnd), @@ -56917,7 +59689,7 @@ defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1101; defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y22_N13 +// Location: FF_X23_Y32_N9 dffeas \ula_|i2s_intf_|bdivider[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~18_combout ), @@ -56936,54 +59708,574 @@ defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( +// Location: LCCOMB_X24_Y32_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( // Equation(s): -// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|bdivider [0] & \ula_|i2s_intf_|Equal1~0_combout ) +// \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] +// \ula_|i2s_intf_|bitcount[0]~6 = CARRY(!\ula_|i2s_intf_|bitcount [0]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [0]), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|bitcount[0]~5_combout ), + .cout(\ula_|i2s_intf_|bitcount[0]~6 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; +defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder ( +// Equation(s): +// \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout = \ula_|i2s_intf_|bclk_r~1_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|bdivider [0]), + .datac(\ula_|i2s_intf_|bclk_r~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .lut_mask = 16'hF0F0; +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y32_N25 +dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[1]~1_combout )) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datac(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hBABA; +defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y32_N15 +dffeas \ula_|i2s_intf_|bitcount[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) +// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[0]~6 ), + .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .cout(\ula_|i2s_intf_|bitcount[1]~8 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y32_N17 +dffeas \ula_|i2s_intf_|bitcount[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) +// \ula_|i2s_intf_|bitcount[2]~10 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[1]~8 ), + .combout(\ula_|i2s_intf_|bitcount[2]~9_combout ), + .cout(\ula_|i2s_intf_|bitcount[2]~10 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; +defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y32_N19 +dffeas \ula_|i2s_intf_|bitcount[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) +// \ula_|i2s_intf_|bitcount[3]~12 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~10 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[2]~10 ), + .combout(\ula_|i2s_intf_|bitcount[3]~11_combout ), + .cout(\ula_|i2s_intf_|bitcount[3]~12 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y32_N21 +dffeas \ula_|i2s_intf_|bitcount[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) + + .dataa(\ula_|i2s_intf_|bitcount [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2s_intf_|bitcount[3]~12 ), + .combout(\ula_|i2s_intf_|bitcount[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h5A5A; +defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y32_N23 +dffeas \ula_|i2s_intf_|bitcount[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( +// Equation(s): +// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # ((\ula_|i2s_intf_|bitcount [2]) # ((\ula_|i2s_intf_|bitcount [1]) # (!\ula_|i2s_intf_|bitcount [0]))) + + .dataa(\ula_|i2s_intf_|bitcount [3]), + .datab(\ula_|i2s_intf_|bitcount [2]), + .datac(\ula_|i2s_intf_|bitcount [0]), + .datad(\ula_|i2s_intf_|bitcount [1]), + .cin(gnd), + .combout(\ula_|i2s_intf_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFEF; +defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[1]~1 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[1]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Equal1~0_combout ), + .datac(\ula_|i2s_intf_|bitcount [4]), + .datad(\ula_|i2s_intf_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[1]~1 .lut_mask = 16'h8808; +defparam \ula_|i2s_intf_|shiftreg[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\ula_|i2s_intf_|Add2~7_cout )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) +// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~7_cout ), + .combout(\ula_|i2s_intf_|Add2~8_combout ), + .cout(\ula_|i2s_intf_|Add2~9 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Add2~8_combout ), .datad(\ula_|i2s_intf_|Equal1~0_combout ), .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h1030; +defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y32_N5 +dffeas \ula_|i2s_intf_|bdivider[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) +// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~9 ), + .combout(\ula_|i2s_intf_|Add2~10_combout ), + .cout(\ula_|i2s_intf_|Add2~11 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hC33F; +defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) + + .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Add2~10_combout ), + .datad(\ula_|i2s_intf_|Equal1~1_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h1101; +defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y32_N17 +dffeas \ula_|i2s_intf_|bdivider[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~17_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) +// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~11 ), + .combout(\ula_|i2s_intf_|Add2~12_combout ), + .cout(\ula_|i2s_intf_|Add2~13 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~19_combout = (\ula_|i2s_intf_|Add2~12_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Add2~12_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h040C; +defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y32_N15 +dffeas \ula_|i2s_intf_|bdivider[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~19_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|bdivider [4]), + .cin(\ula_|i2s_intf_|Add2~13 ), + .combout(\ula_|i2s_intf_|Add2~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; +defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) + + .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Add2~14_combout ), + .datad(\ula_|i2s_intf_|Equal1~1_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h1101; +defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y32_N7 +dffeas \ula_|i2s_intf_|bdivider[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~0_combout = (\ula_|i2s_intf_|bdivider [4] & (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & \ula_|i2s_intf_|bdivider [2]))) + + .dataa(\ula_|i2s_intf_|bdivider [4]), + .datab(\ula_|i2s_intf_|bdivider [1]), + .datac(\ula_|i2s_intf_|bdivider [3]), + .datad(\ula_|i2s_intf_|bdivider [2]), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h0200; +defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|Equal1~0_combout & \ula_|i2s_intf_|bdivider [0]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal1~0_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|bdivider [0]), + .cin(gnd), .combout(\ula_|i2s_intf_|Equal1~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hF000; +defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hCC00; defparam \ula_|i2s_intf_|Equal1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N14 +// Location: LCCOMB_X24_Y32_N12 cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|bclk_r~0_combout = \ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]))) - .dataa(gnd), - .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .dataa(\ula_|i2s_intf_|LessThan0~0_combout ), + .datab(gnd), .datac(\ula_|i2s_intf_|bitcount [4]), .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), .cin(gnd), .combout(\ula_|i2s_intf_|bclk_r~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h30CF; +defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h50AF; defparam \ula_|i2s_intf_|bclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N10 +// Location: LCCOMB_X24_Y32_N26 cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~1 ( // Equation(s): -// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~0_combout )) # (!\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))))) +// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~0_combout ))) # (!\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )))) .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|bclk_r~0_combout ), - .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|bclk_r~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|bclk_r~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h00D8; +defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h0E04; defparam \ula_|i2s_intf_|bclk_r~1 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57006,15 +60298,15 @@ defparam \ula_|i2s_intf_|bclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N24 +// Location: LCCOMB_X23_Y19_N16 cycloneive_lcell_comb \ula_|pcm_outl[13]~feeder ( // Equation(s): -// \ula_|pcm_outl[13]~feeder_combout = \D[3]~96_combout +// \ula_|pcm_outl[13]~feeder_combout = \D[3]~109_combout .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(\D[3]~96_combout ), + .datad(\D[3]~109_combout ), .cin(gnd), .combout(\ula_|pcm_outl[13]~feeder_combout ), .cout()); @@ -57023,41 +60315,41 @@ defparam \ula_|pcm_outl[13]~feeder .lut_mask = 16'hFF00; defparam \ula_|pcm_outl[13]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N2 +// Location: LCCOMB_X24_Y19_N30 cycloneive_lcell_comb \ula_|always0~2 ( // Equation(s): -// \ula_|always0~2_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) +// \ula_|always0~2_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nRD_out~2_combout )) - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .dataa(gnd), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), + .datad(\z80_|memory_ifc_|nRD_out~2_combout ), .cin(gnd), .combout(\ula_|always0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~2 .lut_mask = 16'h2020; +defparam \ula_|always0~2 .lut_mask = 16'h00C0; defparam \ula_|always0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N20 +// Location: LCCOMB_X23_Y19_N2 cycloneive_lcell_comb \ula_|always0~3 ( // Equation(s): -// \ula_|always0~3_combout = (!\z80_|address_pins_|DFFE_apin_latch [0] & (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~2_combout ))) +// \ula_|always0~3_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [0] & (!\z80_|control_pins_|pin_nIORQ~1_combout & \ula_|always0~2_combout ))) - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|control_pins_|pin_nIORQ~1_combout ), .datad(\ula_|always0~2_combout ), .cin(gnd), .combout(\ula_|always0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~3 .lut_mask = 16'h4000; +defparam \ula_|always0~3 .lut_mask = 16'h0200; defparam \ula_|always0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y19_N25 +// Location: FF_X23_Y19_N17 dffeas \ula_|pcm_outl[13] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|pcm_outl[13]~feeder_combout ), @@ -57076,20 +60368,20 @@ defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N26 +// Location: LCCOMB_X24_Y32_N0 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( // Equation(s): // \ula_|i2s_intf_|shiftreg[0]~19_combout = (\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|LessThan0~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h008A; +defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h2202; defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57103,25 +60395,25 @@ defparam \AUD_ADCDAT~input .bus_hold = "false"; defparam \AUD_ADCDAT~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N20 +// Location: LCCOMB_X23_Y33_N6 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~20 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [0])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\AUD_ADCDAT~input_o ))))) # -// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (((\ula_|i2s_intf_|shiftreg [0])))) +// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|shiftreg [0])))) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\AUD_ADCDAT~input_o ))) # +// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (\ula_|i2s_intf_|shiftreg [0])))) - .dataa(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|shiftreg[0]~19_combout ), .datac(\ula_|i2s_intf_|shiftreg [0]), .datad(\AUD_ADCDAT~input_o ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[0]~20_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF2D0; +defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF4B0; defparam \ula_|i2s_intf_|shiftreg[0]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N21 +// Location: FF_X23_Y33_N7 dffeas \ula_|i2s_intf_|shiftreg[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg[0]~20_combout ), @@ -57140,41 +60432,41 @@ defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N26 +// Location: LCCOMB_X23_Y33_N28 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~18 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~18_combout = (\ula_|i2s_intf_|shiftreg [0] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [0]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [0]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [0]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~2 ( +// Location: LCCOMB_X24_Y32_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[1]~2 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg[4]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & \ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) +// \ula_|i2s_intf_|shiftreg[1]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[1]~1_combout )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datac(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .datad(gnd), .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .combout(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4]~2 .lut_mask = 16'hFCF0; -defparam \ula_|i2s_intf_|shiftreg[4]~2 .sum_lutc_input = "datac"; +defparam \ula_|i2s_intf_|shiftreg[1]~2 .lut_mask = 16'hEAEA; +defparam \ula_|i2s_intf_|shiftreg[1]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N27 +// Location: FF_X23_Y33_N29 dffeas \ula_|i2s_intf_|shiftreg[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~18_combout ), @@ -57183,7 +60475,7 @@ dffeas \ula_|i2s_intf_|shiftreg[1] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [1]), @@ -57193,24 +60485,24 @@ defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N24 +// Location: LCCOMB_X23_Y33_N14 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~17_combout = (\ula_|i2s_intf_|shiftreg [1] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [1]) .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|shiftreg [1]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [1]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N25 +// Location: FF_X23_Y33_N15 dffeas \ula_|i2s_intf_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~17_combout ), @@ -57219,7 +60511,7 @@ dffeas \ula_|i2s_intf_|shiftreg[2] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [2]), @@ -57229,24 +60521,24 @@ defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N18 +// Location: LCCOMB_X23_Y33_N16 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~16_combout = (\ula_|i2s_intf_|shiftreg [2] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), .datab(\ula_|i2s_intf_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N19 +// Location: FF_X23_Y33_N17 dffeas \ula_|i2s_intf_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~16_combout ), @@ -57255,7 +60547,7 @@ dffeas \ula_|i2s_intf_|shiftreg[3] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [3]), @@ -57265,24 +60557,24 @@ defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N0 +// Location: LCCOMB_X23_Y33_N22 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~15_combout = (\ula_|i2s_intf_|shiftreg [3] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~15_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [3]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [3]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [3]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N1 +// Location: FF_X23_Y33_N23 dffeas \ula_|i2s_intf_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~15_combout ), @@ -57291,7 +60583,7 @@ dffeas \ula_|i2s_intf_|shiftreg[4] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [4]), @@ -57301,24 +60593,24 @@ defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N10 +// Location: LCCOMB_X23_Y33_N12 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~14_combout = (\ula_|i2s_intf_|shiftreg [4] & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [4]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|shiftreg [4]), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~14_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h0A0A; defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N11 +// Location: FF_X23_Y33_N13 dffeas \ula_|i2s_intf_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~14_combout ), @@ -57327,7 +60619,7 @@ dffeas \ula_|i2s_intf_|shiftreg[5] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [5]), @@ -57337,24 +60629,24 @@ defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N16 +// Location: LCCOMB_X23_Y33_N18 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~13_combout = (\ula_|i2s_intf_|shiftreg [5] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~13_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [5]) - .dataa(\ula_|i2s_intf_|shiftreg [5]), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [5]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N17 +// Location: FF_X23_Y33_N19 dffeas \ula_|i2s_intf_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~13_combout ), @@ -57363,7 +60655,7 @@ dffeas \ula_|i2s_intf_|shiftreg[6] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [6]), @@ -57373,24 +60665,24 @@ defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N30 +// Location: LCCOMB_X23_Y33_N8 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~12_combout = (\ula_|i2s_intf_|shiftreg [6] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~12_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [6]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [6]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [6]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N31 +// Location: FF_X23_Y33_N9 dffeas \ula_|i2s_intf_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~12_combout ), @@ -57399,7 +60691,7 @@ dffeas \ula_|i2s_intf_|shiftreg[7] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [7]), @@ -57409,24 +60701,24 @@ defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N28 +// Location: LCCOMB_X23_Y33_N2 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~11_combout = (\ula_|i2s_intf_|shiftreg [7] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|shiftreg [7]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|shiftreg [7]), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~11_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N29 +// Location: FF_X23_Y33_N3 dffeas \ula_|i2s_intf_|shiftreg[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~11_combout ), @@ -57435,7 +60727,7 @@ dffeas \ula_|i2s_intf_|shiftreg[8] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [8]), @@ -57445,24 +60737,24 @@ defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N22 +// Location: LCCOMB_X23_Y33_N4 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~10_combout = (\ula_|i2s_intf_|shiftreg [8] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~10_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [8]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [8]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [8]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N23 +// Location: FF_X23_Y33_N5 dffeas \ula_|i2s_intf_|shiftreg[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~10_combout ), @@ -57471,7 +60763,7 @@ dffeas \ula_|i2s_intf_|shiftreg[9] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [9]), @@ -57481,24 +60773,24 @@ defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N12 +// Location: LCCOMB_X23_Y33_N10 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [9] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|shiftreg [9]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|shiftreg [9]), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N13 +// Location: FF_X23_Y33_N11 dffeas \ula_|i2s_intf_|shiftreg[10] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~9_combout ), @@ -57507,7 +60799,7 @@ dffeas \ula_|i2s_intf_|shiftreg[10] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [10]), @@ -57517,24 +60809,24 @@ defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N2 +// Location: LCCOMB_X23_Y33_N0 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~8_combout = (\ula_|i2s_intf_|shiftreg [10] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~8_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [10]) - .dataa(\ula_|i2s_intf_|shiftreg [10]), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [10]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N3 +// Location: FF_X23_Y33_N1 dffeas \ula_|i2s_intf_|shiftreg[11] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~8_combout ), @@ -57543,7 +60835,7 @@ dffeas \ula_|i2s_intf_|shiftreg[11] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [11]), @@ -57553,24 +60845,24 @@ defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N8 +// Location: LCCOMB_X23_Y33_N26 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~7_combout = (\ula_|i2s_intf_|shiftreg [11] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~7_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [11]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [11]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [11]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N9 +// Location: FF_X23_Y33_N27 dffeas \ula_|i2s_intf_|shiftreg[12] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~7_combout ), @@ -57579,7 +60871,7 @@ dffeas \ula_|i2s_intf_|shiftreg[12] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [12]), @@ -57589,7 +60881,7 @@ defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N30 +// Location: LCCOMB_X23_Y32_N10 cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( // Equation(s): // \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INR [14]))))) # @@ -57607,7 +60899,7 @@ defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hB8F0; defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N31 +// Location: FF_X23_Y32_N11 dffeas \ula_|i2s_intf_|PCM_INR[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), @@ -57626,7 +60918,7 @@ defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N28 +// Location: LCCOMB_X23_Y32_N12 cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INL[14]~0 ( // Equation(s): // \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INL [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])))) # @@ -57644,7 +60936,7 @@ defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF0B8; defparam \ula_|i2s_intf_|PCM_INL[14]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N29 +// Location: FF_X23_Y32_N13 dffeas \ula_|i2s_intf_|PCM_INL[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), @@ -57663,24 +60955,24 @@ defparam \ula_|i2s_intf_|PCM_INL[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|PCM_INL[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N6 +// Location: LCCOMB_X23_Y32_N0 cycloneive_lcell_comb \ula_|pcm_outr~0 ( // Equation(s): // \ula_|pcm_outr~0_combout = (\ula_|i2s_intf_|PCM_INR [14]) # (\ula_|i2s_intf_|PCM_INL [14]) - .dataa(gnd), + .dataa(\ula_|i2s_intf_|PCM_INR [14]), .datab(gnd), - .datac(\ula_|i2s_intf_|PCM_INR [14]), + .datac(gnd), .datad(\ula_|i2s_intf_|PCM_INL [14]), .cin(gnd), .combout(\ula_|pcm_outr~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFF0; +defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFAA; defparam \ula_|pcm_outr~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N7 +// Location: FF_X23_Y32_N1 dffeas \ula_|pcm_outl[12] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|pcm_outr~0_combout ), @@ -57699,24 +60991,24 @@ defparam \ula_|pcm_outl[12] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N14 +// Location: LCCOMB_X23_Y33_N20 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~6 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [12]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [12])) - .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg [12]), + .dataa(\ula_|i2s_intf_|shiftreg [12]), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), .datad(\ula_|pcm_outl [12]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFC30; +defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFA0A; defparam \ula_|i2s_intf_|shiftreg~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N15 +// Location: FF_X23_Y33_N21 dffeas \ula_|i2s_intf_|shiftreg[13] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~6_combout ), @@ -57725,7 +61017,7 @@ dffeas \ula_|i2s_intf_|shiftreg[13] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [13]), @@ -57735,24 +61027,24 @@ defparam \ula_|i2s_intf_|shiftreg[13] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N4 +// Location: LCCOMB_X23_Y33_N30 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) .dataa(gnd), .datab(\ula_|pcm_outl [13]), - .datac(\ula_|i2s_intf_|shiftreg [13]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [13]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hCCF0; +defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hCFC0; defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N5 +// Location: FF_X23_Y33_N31 dffeas \ula_|i2s_intf_|shiftreg[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~5_combout ), @@ -57761,7 +61053,7 @@ dffeas \ula_|i2s_intf_|shiftreg[14] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [14]), @@ -57771,10 +61063,27 @@ defparam \ula_|i2s_intf_|shiftreg[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[14] .power_up = "low"; // synopsys translate_on -// Location: FF_X29_Y14_N31 +// Location: LCCOMB_X23_Y19_N22 +cycloneive_lcell_comb \ula_|pcm_outl[14]~feeder ( +// Equation(s): +// \ula_|pcm_outl[14]~feeder_combout = \D[4]~111_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\D[4]~111_combout ), + .cin(gnd), + .combout(\ula_|pcm_outl[14]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|pcm_outl[14]~feeder .lut_mask = 16'hFF00; +defparam \ula_|pcm_outl[14]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N23 dffeas \ula_|pcm_outl[14] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\D[4]~98_combout ), + .d(\ula_|pcm_outl[14]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -57790,24 +61099,24 @@ defparam \ula_|pcm_outl[14] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y22_N4 +// Location: LCCOMB_X23_Y33_N24 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~4 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) .dataa(\ula_|i2s_intf_|shiftreg [14]), .datab(gnd), - .datac(\ula_|pcm_outl [14]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|pcm_outl [14]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hF0AA; +defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hFA0A; defparam \ula_|i2s_intf_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y22_N5 +// Location: FF_X23_Y33_N25 dffeas \ula_|i2s_intf_|shiftreg[15] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~4_combout ), @@ -57816,7 +61125,7 @@ dffeas \ula_|i2s_intf_|shiftreg[15] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [15]), @@ -57826,24 +61135,24 @@ defparam \ula_|i2s_intf_|shiftreg[15] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y22_N0 +// Location: LCCOMB_X20_Y33_N0 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~3 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~3_combout = (\ula_|i2s_intf_|shiftreg [15] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~3_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [15]) .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|shiftreg [15]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [15]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h3300; defparam \ula_|i2s_intf_|shiftreg~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y22_N1 +// Location: FF_X20_Y33_N1 dffeas \ula_|i2s_intf_|shiftreg[16] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~3_combout ), @@ -57852,7 +61161,7 @@ dffeas \ula_|i2s_intf_|shiftreg[16] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [16]), @@ -57862,20 +61171,20 @@ defparam \ula_|i2s_intf_|shiftreg[16] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y22_N10 +// Location: LCCOMB_X20_Y33_N14 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~0 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~0_combout = (\ula_|i2s_intf_|shiftreg [16] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [16]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [16]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [16]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h3300; defparam \ula_|i2s_intf_|shiftreg~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57888,7 +61197,7 @@ dffeas \ula_|i2s_intf_|shiftreg[17] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [17]), @@ -57898,135 +61207,32 @@ defparam \ula_|i2s_intf_|shiftreg[17] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N8 -cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Location: LCCOMB_X27_Y18_N12 +cycloneive_lcell_comb \ula_|border[1]~feeder ( // Equation(s): -// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [6]))) +// \ula_|border[1]~feeder_combout = \D[1]~41_combout - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|vga_vc [8]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [6]), - .cin(gnd), - .combout(\ula_|video_|LessThan2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N4 -cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( -// Equation(s): -// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) - - .dataa(\ula_|video_|vga_vc [2]), - .datab(\ula_|video_|vga_vc [3]), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|LessThan6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0111; -defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N30 -cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( -// Equation(s): -// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(\ula_|video_|vga_vc [4]), - .datac(\ula_|video_|LessThan2~0_combout ), - .datad(\ula_|video_|LessThan6~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan2~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7050; -defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N16 -cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( -// Equation(s): -// \ula_|video_|LessThan3~0_combout = ((\ula_|video_|LessThan6~0_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) # (!\ula_|video_|vga_vc [9]) - - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|LessThan6~0_combout ), - .datac(\ula_|video_|vga_vc [5]), - .datad(\ula_|video_|Equal2~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h5D55; -defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N22 -cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( -// Equation(s): -// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [6] & !\ula_|video_|vga_hc [5])) - - .dataa(\ula_|video_|vga_hc [4]), - .datab(\ula_|video_|vga_hc [6]), + .dataa(gnd), + .datab(gnd), .datac(gnd), - .datad(\ula_|video_|vga_hc [5]), + .datad(\D[1]~41_combout ), .cin(gnd), - .combout(\ula_|video_|LessThan0~0_combout ), + .combout(\ula_|border[1]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0011; -defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; +defparam \ula_|border[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|border[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N24 -cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( -// Equation(s): -// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((\ula_|video_|LessThan0~0_combout & !\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # -// ((!\ula_|video_|LessThan0~0_combout & \ula_|video_|vga_hc [7])))) - - .dataa(\ula_|video_|LessThan0~0_combout ), - .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|vga_hc [7]), - .datad(\ula_|video_|vga_hc [9]), - .cin(gnd), - .combout(\ula_|video_|disp_enable~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h3BDC; -defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N2 -cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( -// Equation(s): -// \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) - - .dataa(\ula_|video_|LessThan2~1_combout ), - .datab(\ula_|video_|LessThan3~0_combout ), - .datac(gnd), - .datad(\ula_|video_|disp_enable~0_combout ), - .cin(gnd), - .combout(\ula_|video_|disp_enable~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h4400; -defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N11 +// Location: FF_X27_Y18_N13 dffeas \ula_|border[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\D[1]~34_combout ), + .d(\ula_|border[1]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58037,58 +61243,75 @@ defparam \ula_|border[1] .is_wysiwyg = "true"; defparam \ula_|border[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N8 +// Location: LCCOMB_X32_Y30_N28 +cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( +// Equation(s): +// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) + + .dataa(\ula_|video_|vga_vc [1]), + .datab(\ula_|video_|vga_vc [2]), + .datac(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|vga_vc [0]), + .cin(gnd), + .combout(\ula_|video_|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0103; +defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N14 cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( // Equation(s): // \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) - .dataa(\ula_|video_|vga_vc [6]), + .dataa(\ula_|video_|vga_vc [4]), .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|vga_vc [4]), + .datac(\ula_|video_|vga_vc [6]), .datad(\ula_|video_|LessThan6~0_combout ), .cin(gnd), .combout(\ula_|video_|LessThan6~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h7757; +defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h3F1F; defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N28 +// Location: LCCOMB_X29_Y30_N6 cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( // Equation(s): -// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) +// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [5] & !\ula_|video_|vga_hc [4])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) - .dataa(\ula_|video_|vga_hc [4]), - .datab(\ula_|video_|vga_hc [5]), - .datac(\ula_|video_|vga_hc [6]), + .dataa(\ula_|video_|vga_hc [5]), + .datab(\ula_|video_|vga_hc [6]), + .datac(\ula_|video_|vga_hc [4]), .datad(\ula_|video_|vga_hc [7]), .cin(gnd), .combout(\ula_|video_|LessThan4~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h1FFF; +defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h37FF; defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N10 +// Location: LCCOMB_X31_Y30_N10 cycloneive_lcell_comb \ula_|video_|screen_en~0 ( // Equation(s): // \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) - .dataa(\ula_|video_|vga_hc [9]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|LessThan4~0_combout ), - .datad(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|vga_hc [9]), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|LessThan4~0_combout ), .cin(gnd), .combout(\ula_|video_|screen_en~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1121; +defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1411; defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N22 +// Location: LCCOMB_X31_Y30_N24 cycloneive_lcell_comb \ula_|video_|screen_en~1 ( // Equation(s): // \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # @@ -58106,151 +61329,7 @@ defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE700; defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N28 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N10 -cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( -// Equation(s): -// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h0080; -defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N29 -dffeas \ula_|video_|attr_prefetch[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N12 -cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( -// Equation(s): -// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & \ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; -defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y33_N27 -dffeas \ula_|video_|attr[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N10 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N11 -dffeas \ula_|video_|attr_prefetch[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y33_N13 -dffeas \ula_|video_|attr[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N24 +// Location: LCCOMB_X30_Y28_N0 cycloneive_lcell_comb \ula_|video_|attr_prefetch[7]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 @@ -58267,7 +61346,24 @@ defparam \ula_|video_|attr_prefetch[7]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N25 +// Location: LCCOMB_X30_Y29_N20 +cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( +// Equation(s): +// \ula_|video_|Decoder0~1_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & \ula_|video_|vga_hc [1]))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h4000; +defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N1 dffeas \ula_|video_|attr_prefetch[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[7]~feeder_combout ), @@ -58286,7 +61382,24 @@ defparam \ula_|video_|attr_prefetch[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[7] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N5 +// Location: LCCOMB_X30_Y29_N10 +cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( +// Equation(s): +// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & \ula_|video_|vga_hc [1]))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; +defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y30_N7 dffeas \ula_|video_|attr[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58305,32 +61418,32 @@ defparam \ula_|video_|attr[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y33_N22 +// Location: LCCOMB_X34_Y30_N4 cycloneive_lcell_comb \ula_|video_|frame[0]~12 ( // Equation(s): // \ula_|video_|frame[0]~12_combout = \ula_|video_|Equal3~1_combout $ (\ula_|video_|frame [0]) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(gnd), - .datac(\ula_|video_|frame [0]), - .datad(gnd), + .dataa(gnd), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(gnd), + .datad(\ula_|video_|frame [0]), .cin(gnd), .combout(\ula_|video_|frame[0]~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h5A5A; +defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h33CC; defparam \ula_|video_|frame[0]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y33_N23 +// Location: FF_X34_Y30_N21 dffeas \ula_|video_|frame[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[0]~12_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|frame[0]~12_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -58341,14 +61454,14 @@ defparam \ula_|video_|frame[0] .is_wysiwyg = "true"; defparam \ula_|video_|frame[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N24 +// Location: LCCOMB_X34_Y30_N14 cycloneive_lcell_comb \ula_|video_|frame[1]~4 ( // Equation(s): -// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [0] & (\ula_|video_|frame [1] $ (VCC))) # (!\ula_|video_|frame [0] & (\ula_|video_|frame [1] & VCC)) -// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [0] & \ula_|video_|frame [1])) +// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [1] & (\ula_|video_|frame [0] $ (VCC))) # (!\ula_|video_|frame [1] & (\ula_|video_|frame [0] & VCC)) +// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [1] & \ula_|video_|frame [0])) - .dataa(\ula_|video_|frame [0]), - .datab(\ula_|video_|frame [1]), + .dataa(\ula_|video_|frame [1]), + .datab(\ula_|video_|frame [0]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -58359,7 +61472,7 @@ defparam \ula_|video_|frame[1]~4 .lut_mask = 16'h6688; defparam \ula_|video_|frame[1]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y33_N25 +// Location: FF_X34_Y30_N15 dffeas \ula_|video_|frame[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[1]~4_combout ), @@ -58378,25 +61491,25 @@ defparam \ula_|video_|frame[1] .is_wysiwyg = "true"; defparam \ula_|video_|frame[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N26 +// Location: LCCOMB_X34_Y30_N16 cycloneive_lcell_comb \ula_|video_|frame[2]~6 ( // Equation(s): // \ula_|video_|frame[2]~6_combout = (\ula_|video_|frame [2] & (!\ula_|video_|frame[1]~5 )) # (!\ula_|video_|frame [2] & ((\ula_|video_|frame[1]~5 ) # (GND))) // \ula_|video_|frame[2]~7 = CARRY((!\ula_|video_|frame[1]~5 ) # (!\ula_|video_|frame [2])) - .dataa(\ula_|video_|frame [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|frame [2]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|frame[1]~5 ), .combout(\ula_|video_|frame[2]~6_combout ), .cout(\ula_|video_|frame[2]~7 )); // synopsys translate_off -defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h3C3F; defparam \ula_|video_|frame[2]~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N27 +// Location: FF_X34_Y30_N17 dffeas \ula_|video_|frame[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[2]~6_combout ), @@ -58415,7 +61528,7 @@ defparam \ula_|video_|frame[2] .is_wysiwyg = "true"; defparam \ula_|video_|frame[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N28 +// Location: LCCOMB_X34_Y30_N18 cycloneive_lcell_comb \ula_|video_|frame[3]~8 ( // Equation(s): // \ula_|video_|frame[3]~8_combout = (\ula_|video_|frame [3] & (\ula_|video_|frame[2]~7 $ (GND))) # (!\ula_|video_|frame [3] & (!\ula_|video_|frame[2]~7 & VCC)) @@ -58433,7 +61546,7 @@ defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hC30C; defparam \ula_|video_|frame[3]~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N29 +// Location: FF_X34_Y30_N19 dffeas \ula_|video_|frame[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[3]~8_combout ), @@ -58452,32 +61565,32 @@ defparam \ula_|video_|frame[3] .is_wysiwyg = "true"; defparam \ula_|video_|frame[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N30 +// Location: LCCOMB_X34_Y30_N20 cycloneive_lcell_comb \ula_|video_|frame[4]~10 ( // Equation(s): -// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame [4] $ (\ula_|video_|frame[3]~9 ) +// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame[3]~9 $ (\ula_|video_|frame [4]) - .dataa(\ula_|video_|frame [4]), + .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|video_|frame [4]), .cin(\ula_|video_|frame[3]~9 ), .combout(\ula_|video_|frame[4]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h5A5A; +defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h0FF0; defparam \ula_|video_|frame[4]~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N31 +// Location: FF_X34_Y30_N5 dffeas \ula_|video_|frame[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[4]~10_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|frame[4]~10_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|video_|Equal3~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58488,7 +61601,7 @@ defparam \ula_|video_|frame[4] .is_wysiwyg = "true"; defparam \ula_|video_|frame[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N4 +// Location: LCCOMB_X30_Y30_N6 cycloneive_lcell_comb \ula_|video_|inverted ( // Equation(s): // \ula_|video_|inverted~combout = (\ula_|video_|attr [7] & \ula_|video_|frame [4]) @@ -58505,7 +61618,7 @@ defparam \ula_|video_|inverted .lut_mask = 16'hF000; defparam \ula_|video_|inverted .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N12 +// Location: LCCOMB_X30_Y28_N28 cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 @@ -58522,24 +61635,24 @@ defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N8 +// Location: LCCOMB_X30_Y29_N14 cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( // Equation(s): -// \ula_|video_|Decoder0~2_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) +// \ula_|video_|Decoder0~2_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [1]))) - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), .cin(gnd), .combout(\ula_|video_|Decoder0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0008; +defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0040; defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N13 +// Location: FF_X30_Y28_N29 dffeas \ula_|video_|bits_prefetch[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), @@ -58558,32 +61671,15 @@ defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N6 -cycloneive_lcell_comb \ula_|video_|bits[6]~feeder ( -// Equation(s): -// \ula_|video_|bits[6]~feeder_combout = \ula_|video_|bits_prefetch [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|bits_prefetch [6]), - .cin(gnd), - .combout(\ula_|video_|bits[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y33_N7 +// Location: FF_X30_Y30_N5 dffeas \ula_|video_|bits[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits[6]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [6]), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58594,7 +61690,7 @@ defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; defparam \ula_|video_|bits[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N22 +// Location: LCCOMB_X30_Y28_N26 cycloneive_lcell_comb \ula_|video_|bits_prefetch[4]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 @@ -58611,7 +61707,7 @@ defparam \ula_|video_|bits_prefetch[4]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[4]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N23 +// Location: FF_X30_Y28_N27 dffeas \ula_|video_|bits_prefetch[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[4]~feeder_combout ), @@ -58630,7 +61726,7 @@ defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N23 +// Location: FF_X30_Y30_N29 dffeas \ula_|video_|bits[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58649,7 +61745,7 @@ defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; defparam \ula_|video_|bits[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N18 +// Location: LCCOMB_X30_Y28_N14 cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 @@ -58666,7 +61762,7 @@ defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N19 +// Location: FF_X30_Y28_N15 dffeas \ula_|video_|bits_prefetch[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), @@ -58685,7 +61781,7 @@ defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N18 +// Location: LCCOMB_X30_Y30_N24 cycloneive_lcell_comb \ula_|video_|bits[5]~feeder ( // Equation(s): // \ula_|video_|bits[5]~feeder_combout = \ula_|video_|bits_prefetch [5] @@ -58702,7 +61798,7 @@ defparam \ula_|video_|bits[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N19 +// Location: FF_X30_Y30_N25 dffeas \ula_|video_|bits[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[5]~feeder_combout ), @@ -58721,7 +61817,7 @@ defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; defparam \ula_|video_|bits[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N0 +// Location: LCCOMB_X30_Y28_N12 cycloneive_lcell_comb \ula_|video_|bits_prefetch[7]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 @@ -58738,7 +61834,7 @@ defparam \ula_|video_|bits_prefetch[7]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N1 +// Location: FF_X30_Y28_N13 dffeas \ula_|video_|bits_prefetch[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[7]~feeder_combout ), @@ -58757,7 +61853,7 @@ defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N1 +// Location: FF_X30_Y30_N19 dffeas \ula_|video_|bits[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58776,41 +61872,41 @@ defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; defparam \ula_|video_|bits[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N0 +// Location: LCCOMB_X30_Y30_N18 cycloneive_lcell_comb \ula_|video_|Mux0~0 ( // Equation(s): // \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [5])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [7]))))) - .dataa(\ula_|video_|bits [5]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [5]), .datac(\ula_|video_|bits [7]), .datad(\ula_|video_|vga_hc [2]), .cin(gnd), .combout(\ula_|video_|Mux0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE30; +defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE50; defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N22 +// Location: LCCOMB_X30_Y30_N28 cycloneive_lcell_comb \ula_|video_|Mux0~1 ( // Equation(s): // \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) - .dataa(\ula_|video_|bits [6]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [6]), .datac(\ula_|video_|bits [4]), .datad(\ula_|video_|Mux0~0_combout ), .cin(gnd), .combout(\ula_|video_|Mux0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF388; +defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF588; defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N16 +// Location: LCCOMB_X30_Y28_N20 cycloneive_lcell_comb \ula_|video_|bits_prefetch[2]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 @@ -58827,7 +61923,7 @@ defparam \ula_|video_|bits_prefetch[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N17 +// Location: FF_X30_Y28_N21 dffeas \ula_|video_|bits_prefetch[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[2]~feeder_combout ), @@ -58846,7 +61942,7 @@ defparam \ula_|video_|bits_prefetch[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N12 +// Location: LCCOMB_X30_Y30_N14 cycloneive_lcell_comb \ula_|video_|bits[2]~feeder ( // Equation(s): // \ula_|video_|bits[2]~feeder_combout = \ula_|video_|bits_prefetch [2] @@ -58863,7 +61959,7 @@ defparam \ula_|video_|bits[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N13 +// Location: FF_X30_Y30_N15 dffeas \ula_|video_|bits[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[2]~feeder_combout ), @@ -58882,7 +61978,7 @@ defparam \ula_|video_|bits[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N14 +// Location: LCCOMB_X30_Y28_N18 cycloneive_lcell_comb \ula_|video_|bits_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -58899,7 +61995,7 @@ defparam \ula_|video_|bits_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N15 +// Location: FF_X30_Y28_N19 dffeas \ula_|video_|bits_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[0]~feeder_combout ), @@ -58918,7 +62014,7 @@ defparam \ula_|video_|bits_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N3 +// Location: FF_X30_Y30_N1 dffeas \ula_|video_|bits[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58937,7 +62033,7 @@ defparam \ula_|video_|bits[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N6 +// Location: LCCOMB_X30_Y28_N6 cycloneive_lcell_comb \ula_|video_|bits_prefetch[1]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 @@ -58954,7 +62050,7 @@ defparam \ula_|video_|bits_prefetch[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N7 +// Location: FF_X30_Y28_N7 dffeas \ula_|video_|bits_prefetch[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[1]~feeder_combout ), @@ -58973,7 +62069,7 @@ defparam \ula_|video_|bits_prefetch[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N26 +// Location: LCCOMB_X30_Y30_N20 cycloneive_lcell_comb \ula_|video_|bits[1]~feeder ( // Equation(s): // \ula_|video_|bits[1]~feeder_combout = \ula_|video_|bits_prefetch [1] @@ -58990,7 +62086,7 @@ defparam \ula_|video_|bits[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N27 +// Location: FF_X30_Y30_N21 dffeas \ula_|video_|bits[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[1]~feeder_combout ), @@ -59009,7 +62105,7 @@ defparam \ula_|video_|bits[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N4 +// Location: LCCOMB_X30_Y28_N24 cycloneive_lcell_comb \ula_|video_|bits_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 @@ -59026,7 +62122,7 @@ defparam \ula_|video_|bits_prefetch[3]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N5 +// Location: FF_X30_Y28_N25 dffeas \ula_|video_|bits_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[3]~feeder_combout ), @@ -59045,7 +62141,7 @@ defparam \ula_|video_|bits_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N25 +// Location: FF_X30_Y30_N3 dffeas \ula_|video_|bits[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59064,92 +62160,305 @@ defparam \ula_|video_|bits[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N24 +// Location: LCCOMB_X30_Y30_N2 cycloneive_lcell_comb \ula_|video_|Mux0~2 ( // Equation(s): // \ula_|video_|Mux0~2_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [1])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [3]))))) - .dataa(\ula_|video_|bits [1]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [1]), .datac(\ula_|video_|bits [3]), .datad(\ula_|video_|vga_hc [2]), .cin(gnd), .combout(\ula_|video_|Mux0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE30; +defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE50; defparam \ula_|video_|Mux0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N2 +// Location: LCCOMB_X30_Y30_N0 cycloneive_lcell_comb \ula_|video_|Mux0~3 ( // Equation(s): // \ula_|video_|Mux0~3_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~2_combout & ((\ula_|video_|bits [0]))) # (!\ula_|video_|Mux0~2_combout & (\ula_|video_|bits [2])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~2_combout )))) - .dataa(\ula_|video_|bits [2]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [2]), .datac(\ula_|video_|bits [0]), .datad(\ula_|video_|Mux0~2_combout ), .cin(gnd), .combout(\ula_|video_|Mux0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF388; +defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF588; defparam \ula_|video_|Mux0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N10 -cycloneive_lcell_comb \ula_|video_|cindex[1]~0 ( +// Location: LCCOMB_X30_Y30_N10 +cycloneive_lcell_comb \ula_|video_|cindex[2]~0 ( // Equation(s): -// \ula_|video_|cindex[1]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~3_combout ))) # (!\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~1_combout )))) +// \ula_|video_|cindex[2]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~3_combout ))) # (!\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~1_combout )))) - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|inverted~combout ), - .datac(\ula_|video_|Mux0~1_combout ), + .dataa(\ula_|video_|inverted~combout ), + .datab(\ula_|video_|Mux0~1_combout ), + .datac(\ula_|video_|vga_hc [3]), .datad(\ula_|video_|Mux0~3_combout ), .cin(gnd), - .combout(\ula_|video_|cindex[1]~0_combout ), + .combout(\ula_|video_|cindex[2]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h369C; -defparam \ula_|video_|cindex[1]~0 .sum_lutc_input = "datac"; +defparam \ula_|video_|cindex[2]~0 .lut_mask = 16'h56A6; +defparam \ula_|video_|cindex[2]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N12 +// Location: LCCOMB_X30_Y28_N10 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N11 +dffeas \ula_|video_|attr_prefetch[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y30_N17 +dffeas \ula_|video_|attr[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y28_N4 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N5 +dffeas \ula_|video_|attr_prefetch[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y30_N19 +dffeas \ula_|video_|attr[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y30_N16 cycloneive_lcell_comb \ula_|video_|cindex[1]~1 ( // Equation(s): -// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [1])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [4]))) +// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [1]))) # (!\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [4])) - .dataa(\ula_|video_|attr [1]), + .dataa(\ula_|video_|cindex[2]~0_combout ), .datab(gnd), .datac(\ula_|video_|attr [4]), - .datad(\ula_|video_|cindex[1]~0_combout ), + .datad(\ula_|video_|attr [1]), .cin(gnd), .combout(\ula_|video_|cindex[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hAAF0; +defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hFA50; defparam \ula_|video_|cindex[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N24 +// Location: LCCOMB_X31_Y30_N4 +cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Equation(s): +// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) + + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|vga_vc [6]), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|vga_vc [8]), + .cin(gnd), + .combout(\ula_|video_|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N2 +cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( +// Equation(s): +// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|vga_vc [5]), + .datac(\ula_|video_|LessThan2~0_combout ), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7030; +defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N14 +cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( +// Equation(s): +// \ula_|video_|LessThan3~0_combout = ((!\ula_|video_|vga_vc [5] & (\ula_|video_|Equal2~0_combout & \ula_|video_|LessThan6~0_combout ))) # (!\ula_|video_|vga_vc [9]) + + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|vga_vc [5]), + .datac(\ula_|video_|Equal2~0_combout ), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h7555; +defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N0 +cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( +// Equation(s): +// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [5] & !\ula_|video_|vga_hc [6])) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(gnd), + .datac(\ula_|video_|vga_hc [5]), + .datad(\ula_|video_|vga_hc [6]), + .cin(gnd), + .combout(\ula_|video_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0005; +defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N4 +cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( +// Equation(s): +// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((!\ula_|video_|vga_hc [7] & \ula_|video_|LessThan0~0_combout )) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # ((\ula_|video_|vga_hc [7] & +// !\ula_|video_|LessThan0~0_combout )))) + + .dataa(\ula_|video_|vga_hc [7]), + .datab(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [9]), + .datad(\ula_|video_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|video_|disp_enable~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h7C3E; +defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N12 +cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( +// Equation(s): +// \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) + + .dataa(gnd), + .datab(\ula_|video_|LessThan2~1_combout ), + .datac(\ula_|video_|LessThan3~0_combout ), + .datad(\ula_|video_|disp_enable~0_combout ), + .cin(gnd), + .combout(\ula_|video_|disp_enable~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h3000; +defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N26 cycloneive_lcell_comb \ula_|video_|VGA_R[0]~0 ( // Equation(s): // \ula_|video_|VGA_R[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[1]~1_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [1])))) - .dataa(\ula_|video_|disp_enable~1_combout ), - .datab(\ula_|border [1]), - .datac(\ula_|video_|screen_en~1_combout ), - .datad(\ula_|video_|cindex[1]~1_combout ), + .dataa(\ula_|border [1]), + .datab(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|cindex[1]~1_combout ), + .datad(\ula_|video_|disp_enable~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hA808; +defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hE200; defparam \ula_|video_|VGA_R[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N26 +// Location: LCCOMB_X30_Y28_N22 cycloneive_lcell_comb \ula_|video_|attr_prefetch[6]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 @@ -59166,7 +62475,7 @@ defparam \ula_|video_|attr_prefetch[6]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N27 +// Location: FF_X30_Y28_N23 dffeas \ula_|video_|attr_prefetch[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[6]~feeder_combout ), @@ -59185,7 +62494,7 @@ defparam \ula_|video_|attr_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X38_Y33_N1 +// Location: FF_X31_Y30_N29 dffeas \ula_|video_|attr[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59204,49 +62513,66 @@ defparam \ula_|video_|attr[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N0 +// Location: LCCOMB_X31_Y30_N28 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~0 ( // Equation(s): -// \ula_|video_|VGA_B[1]~0_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & (\ula_|video_|attr [6] & \ula_|video_|disp_enable~0_combout ))) +// \ula_|video_|VGA_B[1]~0_combout = (\ula_|video_|LessThan3~0_combout & (\ula_|video_|disp_enable~0_combout & (\ula_|video_|attr [6] & !\ula_|video_|LessThan2~1_combout ))) - .dataa(\ula_|video_|LessThan2~1_combout ), - .datab(\ula_|video_|LessThan3~0_combout ), + .dataa(\ula_|video_|LessThan3~0_combout ), + .datab(\ula_|video_|disp_enable~0_combout ), .datac(\ula_|video_|attr [6]), - .datad(\ula_|video_|disp_enable~0_combout ), + .datad(\ula_|video_|LessThan2~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h4000; +defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h0080; defparam \ula_|video_|VGA_B[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N2 +// Location: LCCOMB_X31_Y30_N6 cycloneive_lcell_comb \ula_|video_|VGA_R[1]~1 ( // Equation(s): -// \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[1]~1_combout )) +// \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[1]~1_combout )) - .dataa(\ula_|video_|screen_en~1_combout ), - .datab(gnd), - .datac(\ula_|video_|VGA_B[1]~0_combout ), - .datad(\ula_|video_|cindex[1]~1_combout ), + .dataa(\ula_|video_|VGA_B[1]~0_combout ), + .datab(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|cindex[1]~1_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|VGA_R[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'hA000; +defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'h8080; defparam \ula_|video_|VGA_R[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y12_N17 +// Location: LCCOMB_X30_Y27_N20 +cycloneive_lcell_comb \ula_|border[2]~feeder ( +// Equation(s): +// \ula_|border[2]~feeder_combout = \D[2]~53_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\D[2]~53_combout ), + .cin(gnd), + .combout(\ula_|border[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|border[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|border[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y27_N21 dffeas \ula_|border[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\D[2]~46_combout ), + .d(\ula_|border[2]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -59257,62 +62583,7 @@ defparam \ula_|border[2] .is_wysiwyg = "true"; defparam \ula_|border[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N8 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N9 -dffeas \ula_|video_|attr_prefetch[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y33_N21 -dffeas \ula_|video_|attr[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N30 +// Location: LCCOMB_X30_Y28_N30 cycloneive_lcell_comb \ula_|video_|attr_prefetch[5]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 @@ -59329,7 +62600,7 @@ defparam \ula_|video_|attr_prefetch[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N31 +// Location: FF_X30_Y28_N31 dffeas \ula_|video_|attr_prefetch[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[5]~feeder_combout ), @@ -59348,7 +62619,7 @@ defparam \ula_|video_|attr_prefetch[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[5] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N15 +// Location: FF_X30_Y30_N31 dffeas \ula_|video_|attr[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59367,66 +62638,138 @@ defparam \ula_|video_|attr[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N14 -cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( +// Location: LCCOMB_X30_Y28_N16 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( // Equation(s): -// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [2])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [5]))) +// \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 .dataa(gnd), - .datab(\ula_|video_|attr [2]), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N17 +dffeas \ula_|video_|attr_prefetch[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y30_N13 +dffeas \ula_|video_|attr[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y30_N30 +cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( +// Equation(s): +// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [2]))) # (!\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [5])) + + .dataa(\ula_|video_|cindex[2]~0_combout ), + .datab(gnd), .datac(\ula_|video_|attr [5]), - .datad(\ula_|video_|cindex[1]~0_combout ), + .datad(\ula_|video_|attr [2]), .cin(gnd), .combout(\ula_|video_|cindex[2]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hCCF0; +defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hFA50; defparam \ula_|video_|cindex[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N26 +// Location: LCCOMB_X31_Y30_N0 cycloneive_lcell_comb \ula_|video_|VGA_G[0]~0 ( // Equation(s): // \ula_|video_|VGA_G[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[2]~2_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [2])))) - .dataa(\ula_|border [2]), + .dataa(\ula_|video_|disp_enable~1_combout ), .datab(\ula_|video_|screen_en~1_combout ), - .datac(\ula_|video_|disp_enable~1_combout ), + .datac(\ula_|border [2]), .datad(\ula_|video_|cindex[2]~2_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hE020; +defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hA820; defparam \ula_|video_|VGA_G[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N20 +// Location: LCCOMB_X31_Y30_N18 cycloneive_lcell_comb \ula_|video_|VGA_G[1]~1 ( // Equation(s): -// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|cindex[2]~2_combout & \ula_|video_|screen_en~1_combout )) +// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[2]~2_combout )) .dataa(\ula_|video_|VGA_B[1]~0_combout ), - .datab(\ula_|video_|cindex[2]~2_combout ), - .datac(gnd), - .datad(\ula_|video_|screen_en~1_combout ), + .datab(gnd), + .datac(\ula_|video_|screen_en~1_combout ), + .datad(\ula_|video_|cindex[2]~2_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_G[1]~1 .lut_mask = 16'h8800; +defparam \ula_|video_|VGA_G[1]~1 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_G[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N1 +// Location: LCCOMB_X26_Y15_N4 +cycloneive_lcell_comb \ula_|border[0]~feeder ( +// Equation(s): +// \ula_|border[0]~feeder_combout = \D[0]~65_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\D[0]~65_combout ), + .cin(gnd), + .combout(\ula_|border[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|border[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|border[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y15_N5 dffeas \ula_|border[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\D[0]~58_combout ), + .d(\ula_|border[0]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -59437,7 +62780,7 @@ defparam \ula_|border[0] .is_wysiwyg = "true"; defparam \ula_|border[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N20 +// Location: LCCOMB_X30_Y28_N8 cycloneive_lcell_comb \ula_|video_|attr_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -59454,7 +62797,7 @@ defparam \ula_|video_|attr_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N21 +// Location: FF_X30_Y28_N9 dffeas \ula_|video_|attr_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[0]~feeder_combout ), @@ -59473,32 +62816,15 @@ defparam \ula_|video_|attr_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N28 -cycloneive_lcell_comb \ula_|video_|attr[0]~feeder ( -// Equation(s): -// \ula_|video_|attr[0]~feeder_combout = \ula_|video_|attr_prefetch [0] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|attr_prefetch [0]), - .cin(gnd), - .combout(\ula_|video_|attr[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y33_N29 +// Location: FF_X29_Y30_N23 dffeas \ula_|video_|attr[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr[0]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [0]), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -59509,7 +62835,7 @@ defparam \ula_|video_|attr[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N2 +// Location: LCCOMB_X30_Y28_N2 cycloneive_lcell_comb \ula_|video_|attr_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 @@ -59526,7 +62852,7 @@ defparam \ula_|video_|attr_prefetch[3]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N3 +// Location: FF_X30_Y28_N3 dffeas \ula_|video_|attr_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[3]~feeder_combout ), @@ -59545,7 +62871,7 @@ defparam \ula_|video_|attr_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N29 +// Location: FF_X30_Y30_N9 dffeas \ula_|video_|attr[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59564,15 +62890,15 @@ defparam \ula_|video_|attr[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N28 +// Location: LCCOMB_X30_Y30_N8 cycloneive_lcell_comb \ula_|video_|cindex[0]~3 ( // Equation(s): -// \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [3]))) +// \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [3]))) .dataa(gnd), .datab(\ula_|video_|attr [0]), .datac(\ula_|video_|attr [3]), - .datad(\ula_|video_|cindex[1]~0_combout ), + .datad(\ula_|video_|cindex[2]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[0]~3_combout ), .cout()); @@ -59581,58 +62907,58 @@ defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hCCF0; defparam \ula_|video_|cindex[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N30 +// Location: LCCOMB_X30_Y30_N26 cycloneive_lcell_comb \ula_|video_|VGA_B[0]~1 ( // Equation(s): // \ula_|video_|VGA_B[0]~1_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[0]~3_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [0])))) - .dataa(\ula_|video_|disp_enable~1_combout ), - .datab(\ula_|border [0]), - .datac(\ula_|video_|screen_en~1_combout ), - .datad(\ula_|video_|cindex[0]~3_combout ), + .dataa(\ula_|border [0]), + .datab(\ula_|video_|cindex[0]~3_combout ), + .datac(\ula_|video_|disp_enable~1_combout ), + .datad(\ula_|video_|screen_en~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[0]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hA808; +defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hC0A0; defparam \ula_|video_|VGA_B[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N0 +// Location: LCCOMB_X30_Y30_N12 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~2 ( // Equation(s): -// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[0]~3_combout )) +// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|cindex[0]~3_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|screen_en~1_combout )) - .dataa(\ula_|video_|screen_en~1_combout ), - .datab(gnd), - .datac(\ula_|video_|VGA_B[1]~0_combout ), - .datad(\ula_|video_|cindex[0]~3_combout ), + .dataa(\ula_|video_|cindex[0]~3_combout ), + .datab(\ula_|video_|VGA_B[1]~0_combout ), + .datac(gnd), + .datad(\ula_|video_|screen_en~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[1]~2 .lut_mask = 16'hA000; +defparam \ula_|video_|VGA_B[1]~2 .lut_mask = 16'h8800; defparam \ula_|video_|VGA_B[1]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N26 +// Location: LCCOMB_X29_Y29_N12 cycloneive_lcell_comb \ula_|video_|Equal0~2 ( // Equation(s): -// \ula_|video_|Equal0~2_combout = (\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [9] & !\ula_|video_|vga_hc [8])) +// \ula_|video_|Equal0~2_combout = (!\ula_|video_|vga_hc [9] & (!\ula_|video_|vga_hc [8] & \ula_|video_|vga_hc [6])) - .dataa(\ula_|video_|vga_hc [6]), - .datab(\ula_|video_|vga_hc [9]), - .datac(gnd), - .datad(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_hc [9]), + .datab(gnd), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|vga_hc [6]), .cin(gnd), .combout(\ula_|video_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0022; +defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0500; defparam \ula_|video_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y33_N7 +// Location: FF_X29_Y29_N1 dffeas \ula_|video_|VGA_HS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector0~0_combout ), @@ -59651,7 +62977,7 @@ defparam \ula_|video_|VGA_HS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N6 +// Location: LCCOMB_X29_Y29_N0 cycloneive_lcell_comb \ula_|video_|Selector0~0 ( // Equation(s): // \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|Equal1~0_combout & \ula_|video_|VGA_HS~_Duplicate_1_q )))) # (!\ula_|video_|Equal0~2_combout & (\ula_|video_|Equal1~0_combout & @@ -59688,7 +63014,7 @@ defparam \ula_|video_|VGA_HS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS .power_up = "low"; // synopsys translate_on -// Location: FF_X34_Y33_N25 +// Location: FF_X32_Y30_N1 dffeas \ula_|video_|VGA_VS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector1~0_combout ), @@ -59707,21 +63033,21 @@ defparam \ula_|video_|VGA_VS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y33_N24 +// Location: LCCOMB_X32_Y30_N0 cycloneive_lcell_comb \ula_|video_|Selector1~0 ( // Equation(s): -// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal3~1_combout & (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1])))) # (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|VGA_VS~_Duplicate_1_q ) # ((\ula_|video_|Equal2~2_combout & -// \ula_|video_|vga_vc [1])))) +// \ula_|video_|Selector1~0_combout = (\ula_|video_|vga_vc [1] & ((\ula_|video_|Equal2~2_combout ) # ((\ula_|video_|VGA_VS~_Duplicate_1_q & !\ula_|video_|Equal3~1_combout )))) # (!\ula_|video_|vga_vc [1] & (((\ula_|video_|VGA_VS~_Duplicate_1_q & +// !\ula_|video_|Equal3~1_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), + .dataa(\ula_|video_|vga_vc [1]), .datab(\ula_|video_|Equal2~2_combout ), .datac(\ula_|video_|VGA_VS~_Duplicate_1_q ), - .datad(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector1~0 .lut_mask = 16'hDC50; +defparam \ula_|video_|Selector1~0 .lut_mask = 16'h88F8; defparam \ula_|video_|Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59744,7 +63070,7 @@ defparam \ula_|video_|VGA_VS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N4 +// Location: LCCOMB_X40_Y13_N4 cycloneive_lcell_comb \z80_|memory_ifc_|q1~feeder ( // Equation(s): // \z80_|memory_ifc_|q1~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -59761,7 +63087,7 @@ defparam \z80_|memory_ifc_|q1~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|q1~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X47_Y17_N5 +// Location: FF_X40_Y13_N5 dffeas \z80_|memory_ifc_|q1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|q1~feeder_combout ), @@ -59780,7 +63106,7 @@ defparam \z80_|memory_ifc_|q1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q1 .power_up = "low"; // synopsys translate_on -// Location: FF_X47_Y17_N25 +// Location: FF_X40_Y13_N3 dffeas \z80_|memory_ifc_|q2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -59799,7 +63125,7 @@ defparam \z80_|memory_ifc_|q2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N24 +// Location: LCCOMB_X40_Y13_N2 cycloneive_lcell_comb \z80_|memory_ifc_|nRFSH_out~0 ( // Equation(s): // \z80_|memory_ifc_|nRFSH_out~0_combout = (!\z80_|memory_ifc_|q2~q & \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) @@ -59816,7 +63142,7 @@ defparam \z80_|memory_ifc_|nRFSH_out~0 .lut_mask = 16'h0F00; defparam \z80_|memory_ifc_|nRFSH_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N26 +// Location: LCCOMB_X40_Y13_N24 cycloneive_lcell_comb \z80_|memory_ifc_|nM1_out ( // Equation(s): // \z80_|memory_ifc_|nM1_out~combout = (\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) @@ -59833,24 +63159,24 @@ defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF0F; defparam \z80_|memory_ifc_|nM1_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y26_N0 +// Location: LCCOMB_X23_Y19_N24 cycloneive_lcell_comb \ula_|beep~0 ( // Equation(s): -// \ula_|beep~0_combout = \D[4]~98_combout $ (\raw_loader_in~input_o $ (\D[3]~96_combout )) +// \ula_|beep~0_combout = \D[3]~109_combout $ (\raw_loader_in~input_o $ (\D[4]~111_combout )) - .dataa(gnd), - .datab(\D[4]~98_combout ), + .dataa(\D[3]~109_combout ), + .datab(gnd), .datac(\raw_loader_in~input_o ), - .datad(\D[3]~96_combout ), + .datad(\D[4]~111_combout ), .cin(gnd), .combout(\ula_|beep~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|beep~0 .lut_mask = 16'hC33C; +defparam \ula_|beep~0 .lut_mask = 16'hA55A; defparam \ula_|beep~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y26_N1 +// Location: FF_X23_Y19_N25 dffeas \ula_|beep ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|beep~0_combout ), @@ -59869,6 +63195,2526 @@ defparam \ula_|beep .is_wysiwyg = "true"; defparam \ula_|beep .power_up = "low"; // synopsys translate_on +// Location: LCCOMB_X23_Y10_N4 +cycloneive_lcell_comb \sdram_|Mux26~4 ( +// Equation(s): +// \sdram_|Mux26~4_combout = (!\sdram_|r.address[3]~6_combout & ((\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\sdram_|r.address[3]~6_combout ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [9]), + .cin(gnd), + .combout(\sdram_|Mux26~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux26~4 .lut_mask = 16'h3311; +defparam \sdram_|Mux26~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N10 +cycloneive_lcell_comb \sdram_|r.bank[0]~7 ( +// Equation(s): +// \sdram_|r.bank[0]~7_combout = (\sdram_|r.state [6] & \sdram_|r.state [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|r.bank[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~7 .lut_mask = 16'hF000; +defparam \sdram_|r.bank[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N8 +cycloneive_lcell_comb \sdram_|r.bank[0]~11 ( +// Equation(s): +// \sdram_|r.bank[0]~11_combout = (\sdram_|r.rd_pending~q & ((\sdram_|Equal7~2_combout ) # ((\sdram_|r.bank[0]~7_combout )))) # (!\sdram_|r.rd_pending~q & (((\sdram_|r.wr_pending~q & \sdram_|r.bank[0]~7_combout )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.bank[0]~7_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~11 .lut_mask = 16'hFCA0; +defparam \sdram_|r.bank[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N28 +cycloneive_lcell_comb \sdram_|r.bank[0]~4 ( +// Equation(s): +// \sdram_|r.bank[0]~4_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q ))) + + .dataa(gnd), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~4 .lut_mask = 16'hF0C0; +defparam \sdram_|r.bank[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N28 +cycloneive_lcell_comb \sdram_|r.bank[0]~5 ( +// Equation(s): +// \sdram_|r.bank[0]~5_combout = (\sdram_|r.state [5] & (!\sdram_|r.state [4] & ((!\sdram_|r.bank[0]~4_combout ) # (!\sdram_|r.state [7])))) # (!\sdram_|r.state [5] & (((\sdram_|r.state [7])))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.bank[0]~4_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~5 .lut_mask = 16'h3474; +defparam \sdram_|r.bank[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N4 +cycloneive_lcell_comb \sdram_|r.bank[0]~6 ( +// Equation(s): +// \sdram_|r.bank[0]~6_combout = (\sdram_|r.state [8] & (((\sdram_|r.state [6])))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & ((!\sdram_|r.bank[0]~5_combout ) # (!\sdram_|r.state [6]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [6]) # +// (\sdram_|r.bank[0]~5_combout ))))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.bank[0]~5_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~6 .lut_mask = 16'hB5F4; +defparam \sdram_|r.bank[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N28 +cycloneive_lcell_comb \sdram_|r.bank[0]~8 ( +// Equation(s): +// \sdram_|r.bank[0]~8_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] & \sdram_|r.state [7])) # (!\sdram_|r.state [5] & (!\sdram_|r.state [4] & !\sdram_|r.state [7])) + + .dataa(gnd), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.bank[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~8 .lut_mask = 16'hC003; +defparam \sdram_|r.bank[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N18 +cycloneive_lcell_comb \sdram_|r.bank[0]~12 ( +// Equation(s): +// \sdram_|r.bank[0]~12_combout = (\sdram_|r.bank[0]~8_combout & ((\sdram_|r.bank[0]~11_combout ) # ((\sdram_|Equal7~2_combout & \sdram_|r.wr_pending~q )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.bank[0]~11_combout ), + .datad(\sdram_|r.bank[0]~8_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~12 .lut_mask = 16'hF800; +defparam \sdram_|r.bank[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N2 +cycloneive_lcell_comb \sdram_|r.bank[0]~9 ( +// Equation(s): +// \sdram_|r.bank[0]~9_combout = (\sdram_|r.state [8] & (\sdram_|r.bank[0]~12_combout & ((\sdram_|r.bank[0]~11_combout ) # (!\sdram_|r.bank[0]~6_combout )))) # (!\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~6_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.bank[0]~11_combout ), + .datac(\sdram_|r.bank[0]~6_combout ), + .datad(\sdram_|r.bank[0]~12_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~9 .lut_mask = 16'h8F05; +defparam \sdram_|r.bank[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X11_Y0_N18 +dffeas \sdram_|r.bank[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux26~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.bank[0]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.bank [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.bank[0] .is_wysiwyg = "true"; +defparam \sdram_|r.bank[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N2 +cycloneive_lcell_comb \sdram_|Mux25~4 ( +// Equation(s): +// \sdram_|Mux25~4_combout = (!\sdram_|r.address[3]~6_combout & ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [10]), + .datac(gnd), + .datad(\sdram_|r.address[3]~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux25~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux25~4 .lut_mask = 16'h00DD; +defparam \sdram_|Mux25~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X7_Y0_N11 +dffeas \sdram_|r.bank[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux25~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.bank[0]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.bank [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.bank[1] .is_wysiwyg = "true"; +defparam \sdram_|r.bank[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N6 +cycloneive_lcell_comb \sdram_|Mux24~5 ( +// Equation(s): +// \sdram_|Mux24~5_combout = (!\sdram_|r.state [6] & (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|Equal7~2_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux24~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~5 .lut_mask = 16'h0515; +defparam \sdram_|Mux24~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N24 +cycloneive_lcell_comb \sdram_|Mux71~0 ( +// Equation(s): +// \sdram_|Mux71~0_combout = (!\sdram_|r.state [4] & !\sdram_|r.state [5]) + + .dataa(gnd), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [5]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|Mux71~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~0 .lut_mask = 16'h0303; +defparam \sdram_|Mux71~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N4 +cycloneive_lcell_comb \sdram_|process_0~7 ( +// Equation(s): +// \sdram_|process_0~7_combout = \sdram_|r.act_row [4] $ (((\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\sdram_|r.act_row [4]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\sdram_|process_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~7 .lut_mask = 16'h3C0F; +defparam \sdram_|process_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N28 +cycloneive_lcell_comb \sdram_|process_0~4 ( +// Equation(s): +// \sdram_|process_0~4_combout = ((\sdram_|process_0~7_combout ) # ((!\sdram_|Equal7~0_combout ) # (!\sdram_|Equal7~1_combout ))) # (!\sdram_|r.rd_pending~q ) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|process_0~7_combout ), + .datac(\sdram_|Equal7~1_combout ), + .datad(\sdram_|Equal7~0_combout ), + .cin(gnd), + .combout(\sdram_|process_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~4 .lut_mask = 16'hDFFF; +defparam \sdram_|process_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N30 +cycloneive_lcell_comb \sdram_|Mux71~1 ( +// Equation(s): +// \sdram_|Mux71~1_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [6]) # ((!\sdram_|r.state [4]) # (!\sdram_|r.state [5])))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [6] & ((\sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux71~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~1 .lut_mask = 16'h9BAA; +defparam \sdram_|Mux71~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N28 +cycloneive_lcell_comb \sdram_|Mux71~2 ( +// Equation(s): +// \sdram_|Mux71~2_combout = (\sdram_|r.state [7] & ((\sdram_|Mux71~1_combout ) # ((!\sdram_|r.state [8] & \sdram_|Mux71~0_combout )))) # (!\sdram_|r.state [7] & (!\sdram_|r.state [8])) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux71~1_combout ), + .datad(\sdram_|Mux71~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux71~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~2 .lut_mask = 16'hD5D1; +defparam \sdram_|Mux71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N14 +cycloneive_lcell_comb \sdram_|Mux71~3 ( +// Equation(s): +// \sdram_|Mux71~3_combout = (\sdram_|Mux71~2_combout ) # ((\sdram_|process_0~4_combout & (\sdram_|Mux71~0_combout & \sdram_|r.state [6]))) + + .dataa(\sdram_|process_0~4_combout ), + .datab(\sdram_|Mux71~0_combout ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux71~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux71~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~3 .lut_mask = 16'hFF80; +defparam \sdram_|Mux71~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N4 +cycloneive_lcell_comb \sdram_|Mux71~4 ( +// Equation(s): +// \sdram_|Mux71~4_combout = (\sdram_|Mux71~3_combout ) # ((\sdram_|Mux24~5_combout & ((\sdram_|Mux71~0_combout ) # (\sdram_|r.state [7])))) + + .dataa(\sdram_|Mux24~5_combout ), + .datab(\sdram_|Mux71~0_combout ), + .datac(\sdram_|Mux71~3_combout ), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux71~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~4 .lut_mask = 16'hFAF8; +defparam \sdram_|Mux71~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X14_Y0_N11 +dffeas \sdram_|r.dq_masks[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux71~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.dq_masks [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.dq_masks[0] .is_wysiwyg = "true"; +defparam \sdram_|r.dq_masks[0] .power_up = "low"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X14_Y0_N18 +dffeas \sdram_|r.dq_masks[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux71~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.dq_masks [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.dq_masks[1] .is_wysiwyg = "true"; +defparam \sdram_|r.dq_masks[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N2 +cycloneive_lcell_comb \sdram_|r.bank[0]~10 ( +// Equation(s): +// \sdram_|r.bank[0]~10_combout = \sdram_|r.state [5] $ (\sdram_|r.state [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.bank[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~10 .lut_mask = 16'h0FF0; +defparam \sdram_|r.bank[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N18 +cycloneive_lcell_comb \sdram_|Mux9~3 ( +// Equation(s): +// \sdram_|Mux9~3_combout = (\sdram_|r.bank[0]~10_combout ) # ((!\sdram_|n~2_combout & (\sdram_|r.state [6] & \sdram_|r.state [4]))) + + .dataa(\sdram_|n~2_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.bank[0]~10_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~3 .lut_mask = 16'hFF40; +defparam \sdram_|Mux9~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N30 +cycloneive_lcell_comb \sdram_|n~5 ( +// Equation(s): +// \sdram_|n~5_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|Equal7~2_combout ) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|n~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|n~5 .lut_mask = 16'h3031; +defparam \sdram_|n~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N12 +cycloneive_lcell_comb \sdram_|Mux9~4 ( +// Equation(s): +// \sdram_|Mux9~4_combout = (\sdram_|Mux9~3_combout ) # ((\sdram_|r.state [7] & (\sdram_|n~5_combout & !\sdram_|r.state [6]))) + + .dataa(\sdram_|Mux9~3_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|n~5_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux9~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~4 .lut_mask = 16'hAAEA; +defparam \sdram_|Mux9~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N4 +cycloneive_lcell_comb \sdram_|Mux9~2 ( +// Equation(s): +// \sdram_|Mux9~2_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [4] & (!\sdram_|r.state [7])) # (!\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (\sdram_|n~5_combout ))))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|n~5_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux9~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~2 .lut_mask = 16'h7600; +defparam \sdram_|Mux9~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N30 +cycloneive_lcell_comb \sdram_|Equal2~3 ( +// Equation(s): +// \sdram_|Equal2~3_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [0] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [7]))) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [0]), + .datac(\sdram_|Equal2~2_combout ), + .datad(\sdram_|r.init_counter [7]), + .cin(gnd), + .combout(\sdram_|Equal2~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~3 .lut_mask = 16'h2000; +defparam \sdram_|Equal2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N8 +cycloneive_lcell_comb \sdram_|Mux10~2 ( +// Equation(s): +// \sdram_|Mux10~2_combout = (\sdram_|r.init_counter [6]) # ((\sdram_|r.init_counter [5]) # (\sdram_|r.init_counter [4])) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [6]), + .datac(\sdram_|r.init_counter [5]), + .datad(\sdram_|r.init_counter [4]), + .cin(gnd), + .combout(\sdram_|Mux10~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~2 .lut_mask = 16'hFFFC; +defparam \sdram_|Mux10~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N26 +cycloneive_lcell_comb \sdram_|Mux10~3 ( +// Equation(s): +// \sdram_|Mux10~3_combout = (\sdram_|r.init_counter [1] & ((\sdram_|r.init_counter [2] & (!\sdram_|r.init_counter [3])) # (!\sdram_|r.init_counter [2] & (\sdram_|r.init_counter [3] & !\sdram_|Mux10~2_combout )))) + + .dataa(\sdram_|r.init_counter [2]), + .datab(\sdram_|r.init_counter [3]), + .datac(\sdram_|Mux10~2_combout ), + .datad(\sdram_|r.init_counter [1]), + .cin(gnd), + .combout(\sdram_|Mux10~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~3 .lut_mask = 16'h2600; +defparam \sdram_|Mux10~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N4 +cycloneive_lcell_comb \sdram_|process_0~6 ( +// Equation(s): +// \sdram_|process_0~6_combout = (!\sdram_|r.init_counter [9] & (!\sdram_|r.init_counter [8] & (\sdram_|process_0~5_combout & !\sdram_|r.init_counter [10]))) + + .dataa(\sdram_|r.init_counter [9]), + .datab(\sdram_|r.init_counter [8]), + .datac(\sdram_|process_0~5_combout ), + .datad(\sdram_|r.init_counter [10]), + .cin(gnd), + .combout(\sdram_|process_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~6 .lut_mask = 16'h0010; +defparam \sdram_|process_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N24 +cycloneive_lcell_comb \sdram_|Mux10~4 ( +// Equation(s): +// \sdram_|Mux10~4_combout = ((\sdram_|r.init_counter [7]) # ((!\sdram_|r.init_counter [0]) # (!\sdram_|process_0~6_combout ))) # (!\sdram_|Mux10~3_combout ) + + .dataa(\sdram_|Mux10~3_combout ), + .datab(\sdram_|r.init_counter [7]), + .datac(\sdram_|process_0~6_combout ), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Mux10~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~4 .lut_mask = 16'hDFFF; +defparam \sdram_|Mux10~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N22 +cycloneive_lcell_comb \sdram_|Mux9~5 ( +// Equation(s): +// \sdram_|Mux9~5_combout = (\sdram_|r.state [6]) # ((\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|n~2_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|n~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~5 .lut_mask = 16'hEAEE; +defparam \sdram_|Mux9~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N20 +cycloneive_lcell_comb \sdram_|Mux7~0 ( +// Equation(s): +// \sdram_|Mux7~0_combout = (!\sdram_|r.state [7] & !\sdram_|r.state [4]) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(gnd), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~0 .lut_mask = 16'h0033; +defparam \sdram_|Mux7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N10 +cycloneive_lcell_comb \sdram_|Mux9~6 ( +// Equation(s): +// \sdram_|Mux9~6_combout = (\sdram_|Mux9~5_combout ) # ((!\sdram_|Equal2~3_combout & (\sdram_|Mux10~4_combout & \sdram_|Mux7~0_combout ))) + + .dataa(\sdram_|Equal2~3_combout ), + .datab(\sdram_|Mux10~4_combout ), + .datac(\sdram_|Mux9~5_combout ), + .datad(\sdram_|Mux7~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~6 .lut_mask = 16'hF4F0; +defparam \sdram_|Mux9~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N24 +cycloneive_lcell_comb \sdram_|Mux9~7 ( +// Equation(s): +// \sdram_|Mux9~7_combout = (\sdram_|Mux9~4_combout ) # ((\sdram_|Mux9~2_combout ) # ((!\sdram_|r.state [8] & \sdram_|Mux9~6_combout ))) + + .dataa(\sdram_|Mux9~4_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux9~2_combout ), + .datad(\sdram_|Mux9~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~7 .lut_mask = 16'hFBFA; +defparam \sdram_|Mux9~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y11_N4 +dffeas \sdram_|r.state[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux9~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[2] .is_wysiwyg = "true"; +defparam \sdram_|r.state[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N16 +cycloneive_lcell_comb \sdram_|Mux10~11 ( +// Equation(s): +// \sdram_|Mux10~11_combout = (\sdram_|r.rf_pending~q & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q )))) # (!\sdram_|r.rf_pending~q & (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|Equal7~2_combout ))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux10~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~11 .lut_mask = 16'hAF9D; +defparam \sdram_|Mux10~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N12 +cycloneive_lcell_comb \sdram_|Mux10~6 ( +// Equation(s): +// \sdram_|Mux10~6_combout = (\sdram_|r.state [6] & (((\sdram_|process_0~4_combout ) # (!\sdram_|r.state [8])))) # (!\sdram_|r.state [6] & (\sdram_|Mux10~11_combout & ((\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Mux10~11_combout ), + .datac(\sdram_|process_0~4_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux10~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~6 .lut_mask = 16'hE4AA; +defparam \sdram_|Mux10~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N26 +cycloneive_lcell_comb \sdram_|Mux10~5 ( +// Equation(s): +// \sdram_|Mux10~5_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [4]) # ((\sdram_|r.rf_pending~q )))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & (!\sdram_|r.rf_pending~q )) # (!\sdram_|r.state [4] & ((\sdram_|Mux10~4_combout ))))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Mux10~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~5 .lut_mask = 16'hBDAC; +defparam \sdram_|Mux10~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N10 +cycloneive_lcell_comb \sdram_|Mux10~7 ( +// Equation(s): +// \sdram_|Mux10~7_combout = (\sdram_|r.state [6] & (((!\sdram_|r.state [8]) # (!\sdram_|r.rf_pending~q )) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & ((\sdram_|r.rf_pending~q ) # (\sdram_|r.state [4] $ (\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux10~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~7 .lut_mask = 16'h7BFE; +defparam \sdram_|Mux10~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N20 +cycloneive_lcell_comb \sdram_|Mux10~8 ( +// Equation(s): +// \sdram_|Mux10~8_combout = (\sdram_|r.state [7] & ((\sdram_|Mux10~7_combout ) # ((\sdram_|Mux10~11_combout )))) # (!\sdram_|r.state [7] & (((\sdram_|Mux10~5_combout )))) + + .dataa(\sdram_|Mux10~7_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux10~5_combout ), + .datad(\sdram_|Mux10~11_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~8 .lut_mask = 16'hFCB8; +defparam \sdram_|Mux10~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N22 +cycloneive_lcell_comb \sdram_|Mux10~9 ( +// Equation(s): +// \sdram_|Mux10~9_combout = (\sdram_|r.bank[0]~10_combout ) # ((\sdram_|Mux10~8_combout ) # ((\sdram_|Mux10~6_combout & !\sdram_|Mux10~5_combout ))) + + .dataa(\sdram_|Mux10~6_combout ), + .datab(\sdram_|r.bank[0]~10_combout ), + .datac(\sdram_|Mux10~5_combout ), + .datad(\sdram_|Mux10~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~9 .lut_mask = 16'hFFCE; +defparam \sdram_|Mux10~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y11_N11 +dffeas \sdram_|r.state[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux10~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[1] .is_wysiwyg = "true"; +defparam \sdram_|r.state[1] .power_up = "low"; +// synopsys translate_on + +// Location: CLKCTRL_PLL1E0 +cycloneive_clkctrl \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [1]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK_outclk )); +// synopsys translate_off +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK .clock_type = "external clock output"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK .ena_register_mode = "double register"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N8 +cycloneive_lcell_comb \sdram_|Mux11~2 ( +// Equation(s): +// \sdram_|Mux11~2_combout = (\sdram_|r.init_counter [7] $ (!\sdram_|r.init_counter [0])) # (!\sdram_|r.init_counter [1]) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [7]), + .datac(gnd), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Mux11~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~2 .lut_mask = 16'hDD77; +defparam \sdram_|Mux11~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N6 +cycloneive_lcell_comb \sdram_|Mux11~3 ( +// Equation(s): +// \sdram_|Mux11~3_combout = (!\sdram_|r.state [8] & (!\sdram_|r.state [6] & ((\sdram_|Mux11~2_combout ) # (!\sdram_|Equal2~2_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Equal2~2_combout ), + .datac(\sdram_|Mux11~2_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux11~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~3 .lut_mask = 16'h0051; +defparam \sdram_|Mux11~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N26 +cycloneive_lcell_comb \sdram_|Mux11~4 ( +// Equation(s): +// \sdram_|Mux11~4_combout = (!\sdram_|r.state [7] & ((\sdram_|Mux11~3_combout ) # ((\sdram_|r.state [4] & !\sdram_|Mux23~0_combout )))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux23~0_combout ), + .datad(\sdram_|Mux11~3_combout ), + .cin(gnd), + .combout(\sdram_|Mux11~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~4 .lut_mask = 16'h3302; +defparam \sdram_|Mux11~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N28 +cycloneive_lcell_comb \sdram_|Mux11~5 ( +// Equation(s): +// \sdram_|Mux11~5_combout = (\sdram_|r.state [7] & ((\sdram_|r.state [4] $ (\sdram_|r.state [8])) # (!\sdram_|r.state [5]))) # (!\sdram_|r.state [7] & (((\sdram_|r.state [5])))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux11~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~5 .lut_mask = 16'h7CBC; +defparam \sdram_|Mux11~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N0 +cycloneive_lcell_comb \sdram_|Mux11~6 ( +// Equation(s): +// \sdram_|Mux11~6_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|r.state [7]) # ((!\sdram_|r.state [6] & \sdram_|r.state [8])))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux11~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~6 .lut_mask = 16'h4544; +defparam \sdram_|Mux11~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N30 +cycloneive_lcell_comb \sdram_|Mux11~7 ( +// Equation(s): +// \sdram_|Mux11~7_combout = (!\sdram_|r.wr_pending~q & (\sdram_|Mux11~6_combout & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.rd_pending~q )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Mux11~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux11~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~7 .lut_mask = 16'h2300; +defparam \sdram_|Mux11~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N16 +cycloneive_lcell_comb \sdram_|Mux11~9 ( +// Equation(s): +// \sdram_|Mux11~9_combout = (\sdram_|r.state [6] & (((\sdram_|n~5_combout ) # (!\sdram_|Mux7~0_combout )) # (!\sdram_|r.state [8]))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|n~5_combout ), + .datad(\sdram_|Mux7~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux11~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~9 .lut_mask = 16'hA2AA; +defparam \sdram_|Mux11~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N14 +cycloneive_lcell_comb \sdram_|Mux11~8 ( +// Equation(s): +// \sdram_|Mux11~8_combout = (\sdram_|Mux11~4_combout ) # ((\sdram_|Mux11~5_combout ) # ((\sdram_|Mux11~7_combout ) # (\sdram_|Mux11~9_combout ))) + + .dataa(\sdram_|Mux11~4_combout ), + .datab(\sdram_|Mux11~5_combout ), + .datac(\sdram_|Mux11~7_combout ), + .datad(\sdram_|Mux11~9_combout ), + .cin(gnd), + .combout(\sdram_|Mux11~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~8 .lut_mask = 16'hFFFE; +defparam \sdram_|Mux11~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y27_N4 +dffeas \sdram_|r.state[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux11~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[0] .is_wysiwyg = "true"; +defparam \sdram_|r.state[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N20 +cycloneive_lcell_comb \sdram_|Mux24~2 ( +// Equation(s): +// \sdram_|Mux24~2_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q & !\sdram_|r.state [6])))) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux24~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~2 .lut_mask = 16'hCE00; +defparam \sdram_|Mux24~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N2 +cycloneive_lcell_comb \sdram_|r.address[0]~7 ( +// Equation(s): +// \sdram_|r.address[0]~7_combout = (\sdram_|r.state [4] & ((\sdram_|process_0~2_combout & (\z80_|address_pins_|abus[11]~19_combout )) # (!\sdram_|process_0~2_combout & ((\sdram_|r.address[0]~_Duplicate_1_q ))))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\sdram_|r.address[0]~_Duplicate_1_q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|r.address[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[0]~7 .lut_mask = 16'hA0C0; +defparam \sdram_|r.address[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N12 +cycloneive_lcell_comb \sdram_|r.address[0]~0 ( +// Equation(s): +// \sdram_|r.address[0]~0_combout = (\sdram_|r.state [8] & (!\sdram_|Mux24~2_combout & (\sdram_|r.address[0]~_Duplicate_1_q ))) # (!\sdram_|r.state [8] & (((\sdram_|r.address[0]~7_combout )))) + + .dataa(\sdram_|Mux24~2_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.address[0]~_Duplicate_1_q ), + .datad(\sdram_|r.address[0]~7_combout ), + .cin(gnd), + .combout(\sdram_|r.address[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[0]~0 .lut_mask = 16'h7340; +defparam \sdram_|r.address[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N30 +cycloneive_lcell_comb \sdram_|Mux13~9 ( +// Equation(s): +// \sdram_|Mux13~9_combout = (!\sdram_|r.state [5] & ((\sdram_|r.state [8] & (!\sdram_|r.state [4])) # (!\sdram_|r.state [8] & ((!\sdram_|r.state [6]))))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux13~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~9 .lut_mask = 16'h0407; +defparam \sdram_|Mux13~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N0 +cycloneive_lcell_comb \sdram_|Mux13~4 ( +// Equation(s): +// \sdram_|Mux13~4_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] & (\sdram_|r.state [8] $ (!\sdram_|r.state [5])))) # (!\sdram_|r.state [6] & (\sdram_|r.state [5] & (\sdram_|r.state [4] $ (!\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux13~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~4 .lut_mask = 16'h8290; +defparam \sdram_|Mux13~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N2 +cycloneive_lcell_comb \sdram_|Mux13~5 ( +// Equation(s): +// \sdram_|Mux13~5_combout = (\sdram_|r.state [7] & ((\sdram_|Mux13~4_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux13~9_combout )) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux13~9_combout ), + .datad(\sdram_|Mux13~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux13~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~5 .lut_mask = 16'hFC30; +defparam \sdram_|Mux13~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y11_N13 +dffeas \sdram_|r.address[0]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[0]~0_combout ), + .asdata(\sdram_|Mux24~4_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\sdram_|r.state [7]), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[0]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[0]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[0]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N4 +cycloneive_lcell_comb \sdram_|Mux24~3 ( +// Equation(s): +// \sdram_|Mux24~3_combout = (\sdram_|Mux23~0_combout & ((\sdram_|process_0~2_combout & (\z80_|address_pins_|abus[11]~19_combout )) # (!\sdram_|process_0~2_combout & ((\sdram_|r.address[0]~_Duplicate_1_q ))))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\sdram_|r.address[0]~_Duplicate_1_q ), + .datac(\sdram_|Mux23~0_combout ), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux24~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~3 .lut_mask = 16'hA0C0; +defparam \sdram_|Mux24~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N14 +cycloneive_lcell_comb \sdram_|Mux24~4 ( +// Equation(s): +// \sdram_|Mux24~4_combout = (\sdram_|Mux24~3_combout ) # ((!\sdram_|n~3_combout & (\sdram_|r.address[0]~_Duplicate_1_q & !\sdram_|r.state [6]))) + + .dataa(\sdram_|n~3_combout ), + .datab(\sdram_|r.address[0]~_Duplicate_1_q ), + .datac(\sdram_|Mux24~3_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux24~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~4 .lut_mask = 16'hF0F4; +defparam \sdram_|Mux24~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N24 +cycloneive_lcell_comb \sdram_|r.address[0]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[0]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux24~4_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[0]~0_combout ))) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux24~4_combout ), + .datad(\sdram_|r.address[0]~0_combout ), + .cin(gnd), + .combout(\sdram_|r.address[0]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[0]~SLOAD_MUX .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[0]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y4_N18 +dffeas \sdram_|r.address[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[0]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[0] .is_wysiwyg = "true"; +defparam \sdram_|r.address[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N16 +cycloneive_lcell_comb \sdram_|r.address[1]~_Duplicate_1feeder ( +// Equation(s): +// \sdram_|r.address[1]~_Duplicate_1feeder_combout = \sdram_|r.address[1]~1_combout + + .dataa(\sdram_|r.address[1]~1_combout ), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[1]~_Duplicate_1feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~_Duplicate_1feeder .lut_mask = 16'hAAAA; +defparam \sdram_|r.address[1]~_Duplicate_1feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N20 +cycloneive_lcell_comb \sdram_|Mux23~4 ( +// Equation(s): +// \sdram_|Mux23~4_combout = (\sdram_|r.state [8] & (\sdram_|r.address[1]~_Duplicate_1_q )) # (!\sdram_|r.state [8] & ((\sdram_|process_0~2_combout & ((\z80_|address_pins_|abus[12]~24_combout ))) # (!\sdram_|process_0~2_combout & +// (\sdram_|r.address[1]~_Duplicate_1_q )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.address[1]~_Duplicate_1_q ), + .datac(\z80_|address_pins_|abus[12]~24_combout ), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux23~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~4 .lut_mask = 16'hD8CC; +defparam \sdram_|Mux23~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N16 +cycloneive_lcell_comb \sdram_|Equal5~0 ( +// Equation(s): +// \sdram_|Equal5~0_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [0]))) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [7]), + .datac(\sdram_|Equal2~2_combout ), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Equal5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal5~0 .lut_mask = 16'h2000; +defparam \sdram_|Equal5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N14 +cycloneive_lcell_comb \sdram_|Mux23~5 ( +// Equation(s): +// \sdram_|Mux23~5_combout = (\sdram_|r.state [8] & (\sdram_|Mux23~4_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & (\sdram_|Mux23~4_combout )) # (!\sdram_|r.state [4] & ((\sdram_|Equal5~0_combout ))))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux23~4_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|Equal5~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux23~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~5 .lut_mask = 16'hCDC8; +defparam \sdram_|Mux23~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N8 +cycloneive_lcell_comb \sdram_|Mux23~6 ( +// Equation(s): +// \sdram_|Mux23~6_combout = (\sdram_|Mux23~5_combout & (((\sdram_|r.state [4]) # (!\sdram_|Mux24~2_combout )) # (!\sdram_|r.state [8]))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|Mux23~5_combout ), + .datad(\sdram_|Mux24~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux23~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~6 .lut_mask = 16'hD0F0; +defparam \sdram_|Mux23~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N2 +cycloneive_lcell_comb \sdram_|Mux19~0 ( +// Equation(s): +// \sdram_|Mux19~0_combout = (\sdram_|r.state [7] & (\sdram_|r.state [5] $ (((!\sdram_|r.state [8] & \sdram_|r.state [6]))))) # (!\sdram_|r.state [7] & (!\sdram_|r.state [5] & ((\sdram_|r.state [8]) # (!\sdram_|r.state [6])))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [5]), + .cin(gnd), + .combout(\sdram_|Mux19~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~0 .lut_mask = 16'h8C63; +defparam \sdram_|Mux19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y12_N17 +dffeas \sdram_|r.address[1]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[1]~_Duplicate_1feeder_combout ), + .asdata(\sdram_|Mux23~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(!\sdram_|r.state [7]), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[1]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[1]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[1]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N28 +cycloneive_lcell_comb \sdram_|Mux23~2 ( +// Equation(s): +// \sdram_|Mux23~2_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] & ((\sdram_|process_0~2_combout ) # (!\sdram_|r.state [8])))) # (!\sdram_|r.state [6] & (\sdram_|process_0~2_combout & (\sdram_|r.state [4] $ (!\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|process_0~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux23~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~2 .lut_mask = 16'hC0A4; +defparam \sdram_|Mux23~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N30 +cycloneive_lcell_comb \sdram_|Mux23~3 ( +// Equation(s): +// \sdram_|Mux23~3_combout = (\sdram_|Mux23~2_combout & ((\sdram_|r.state [6]) # (\sdram_|Equal7~2_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|Mux23~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux23~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~3 .lut_mask = 16'hFA00; +defparam \sdram_|Mux23~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N18 +cycloneive_lcell_comb \sdram_|Mux23~1 ( +// Equation(s): +// \sdram_|Mux23~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [8] & ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) + + .dataa(\sdram_|r.state [6]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [12]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux23~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~1 .lut_mask = 16'hA200; +defparam \sdram_|Mux23~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N22 +cycloneive_lcell_comb \sdram_|r.address[1]~1 ( +// Equation(s): +// \sdram_|r.address[1]~1_combout = (\sdram_|Mux23~3_combout & ((\sdram_|Mux23~1_combout ))) # (!\sdram_|Mux23~3_combout & (\sdram_|r.address[1]~_Duplicate_1_q )) + + .dataa(gnd), + .datab(\sdram_|r.address[1]~_Duplicate_1_q ), + .datac(\sdram_|Mux23~3_combout ), + .datad(\sdram_|Mux23~1_combout ), + .cin(gnd), + .combout(\sdram_|r.address[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~1 .lut_mask = 16'hFC0C; +defparam \sdram_|r.address[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N2 +cycloneive_lcell_comb \sdram_|r.address[1]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[1]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|r.address[1]~1_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux23~6_combout ))) + + .dataa(\sdram_|r.address[1]~1_combout ), + .datab(\sdram_|Mux23~6_combout ), + .datac(\sdram_|r.state [7]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[1]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~SLOAD_MUX .lut_mask = 16'hACAC; +defparam \sdram_|r.address[1]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X5_Y0_N11 +dffeas \sdram_|r.address[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[1]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[1] .is_wysiwyg = "true"; +defparam \sdram_|r.address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N10 +cycloneive_lcell_comb \sdram_|r.address[3]~8 ( +// Equation(s): +// \sdram_|r.address[3]~8_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [5])) # (!\sdram_|r.state [6] & (((\sdram_|r.state [7]) # (\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.address[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~8 .lut_mask = 16'h7772; +defparam \sdram_|r.address[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N24 +cycloneive_lcell_comb \sdram_|r.address[3]~9 ( +// Equation(s): +// \sdram_|r.address[3]~9_combout = (\sdram_|r.state [5] & \sdram_|r.state [6]) + + .dataa(gnd), + .datab(\sdram_|r.state [5]), + .datac(gnd), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|r.address[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~9 .lut_mask = 16'hCC00; +defparam \sdram_|r.address[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N26 +cycloneive_lcell_comb \sdram_|Mux21~0 ( +// Equation(s): +// \sdram_|Mux21~0_combout = (!\sdram_|r.address[3]~8_combout & ((\sdram_|r.address[3]~9_combout ) # ((\sdram_|r.address[3]~6_combout & \sdram_|r.state [4])))) + + .dataa(\sdram_|r.address[3]~6_combout ), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.address[3]~9_combout ), + .datad(\sdram_|r.address[3]~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux21~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux21~0 .lut_mask = 16'h00F8; +defparam \sdram_|Mux21~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N18 +cycloneive_lcell_comb \sdram_|Mux22~0 ( +// Equation(s): +// \sdram_|Mux22~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|abus[1]~25_combout ) # ((\z80_|address_pins_|abus[13]~23_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~8_combout & +// (((\z80_|address_pins_|abus[13]~23_combout & \sdram_|Mux21~0_combout )))) + + .dataa(\sdram_|r.address[3]~8_combout ), + .datab(\z80_|address_pins_|abus[1]~25_combout ), + .datac(\z80_|address_pins_|abus[13]~23_combout ), + .datad(\sdram_|Mux21~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux22~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux22~0 .lut_mask = 16'hF888; +defparam \sdram_|Mux22~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N20 +cycloneive_lcell_comb \sdram_|r.address[3]~10 ( +// Equation(s): +// \sdram_|r.address[3]~10_combout = (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|r.state [7])) # (!\sdram_|r.state [4]) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|r.address[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~10 .lut_mask = 16'h777F; +defparam \sdram_|r.address[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N14 +cycloneive_lcell_comb \sdram_|r.address[3]~11 ( +// Equation(s): +// \sdram_|r.address[3]~11_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [7]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|r.rd_pending~q ))) + + .dataa(gnd), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.address[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~11 .lut_mask = 16'h0FF3; +defparam \sdram_|r.address[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N0 +cycloneive_lcell_comb \sdram_|r.address[3]~12 ( +// Equation(s): +// \sdram_|r.address[3]~12_combout = (\sdram_|r.address[3]~11_combout ) # ((\sdram_|r.state [4] & ((\sdram_|r.state [8]))) # (!\sdram_|r.state [4] & ((!\sdram_|r.state [8]) # (!\sdram_|Equal7~2_combout )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.address[3]~11_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.address[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~12 .lut_mask = 16'hFDCF; +defparam \sdram_|r.address[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N6 +cycloneive_lcell_comb \sdram_|r.address[3]~13 ( +// Equation(s): +// \sdram_|r.address[3]~13_combout = (\sdram_|r.state [5] & (((\sdram_|r.address[3]~10_combout )) # (!\sdram_|r.state [8]))) # (!\sdram_|r.state [5] & (((\sdram_|r.address[3]~12_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.address[3]~10_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.address[3]~12_combout ), + .cin(gnd), + .combout(\sdram_|r.address[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~13 .lut_mask = 16'hDFD0; +defparam \sdram_|r.address[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N16 +cycloneive_lcell_comb \sdram_|r.address[3]~14 ( +// Equation(s): +// \sdram_|r.address[3]~14_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [7]) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) # (!\sdram_|r.state [4] & (\sdram_|r.state [7] & (!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q ))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|r.address[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~14 .lut_mask = 16'h888E; +defparam \sdram_|r.address[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N22 +cycloneive_lcell_comb \sdram_|r.address[3]~15 ( +// Equation(s): +// \sdram_|r.address[3]~15_combout = (\sdram_|r.address[3]~14_combout ) # ((\sdram_|r.state [5] & ((!\sdram_|r.state [7]) # (!\sdram_|Equal7~2_combout ))) # (!\sdram_|r.state [5] & ((\sdram_|r.state [7])))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.address[3]~14_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.address[3]~15_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~15 .lut_mask = 16'hDFFC; +defparam \sdram_|r.address[3]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N24 +cycloneive_lcell_comb \sdram_|r.address[3]~16 ( +// Equation(s): +// \sdram_|r.address[3]~16_combout = (\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~8_combout )) # (!\sdram_|n~3_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|r.address[3]~15_combout )))) + + .dataa(\sdram_|n~3_combout ), + .datab(\sdram_|r.bank[0]~8_combout ), + .datac(\sdram_|r.address[3]~15_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.address[3]~16_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~16 .lut_mask = 16'h77F0; +defparam \sdram_|r.address[3]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N26 +cycloneive_lcell_comb \sdram_|r.address[3]~17 ( +// Equation(s): +// \sdram_|r.address[3]~17_combout = (\sdram_|r.state [6] & (!\sdram_|r.address[3]~13_combout )) # (!\sdram_|r.state [6] & ((!\sdram_|r.address[3]~16_combout ))) + + .dataa(\sdram_|r.address[3]~13_combout ), + .datab(gnd), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.address[3]~16_combout ), + .cin(gnd), + .combout(\sdram_|r.address[3]~17_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~17 .lut_mask = 16'h505F; +defparam \sdram_|r.address[3]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X5_Y0_N4 +dffeas \sdram_|r.address[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux22~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[2] .is_wysiwyg = "true"; +defparam \sdram_|r.address[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N2 +cycloneive_lcell_comb \sdram_|Mux21~1 ( +// Equation(s): +// \sdram_|Mux21~1_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|abus[2]~26_combout ) # ((\z80_|address_pins_|abus[14]~22_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~8_combout & +// (((\z80_|address_pins_|abus[14]~22_combout & \sdram_|Mux21~0_combout )))) + + .dataa(\sdram_|r.address[3]~8_combout ), + .datab(\z80_|address_pins_|abus[2]~26_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\sdram_|Mux21~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux21~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux21~1 .lut_mask = 16'hF888; +defparam \sdram_|Mux21~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X20_Y0_N11 +dffeas \sdram_|r.address[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux21~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[3] .is_wysiwyg = "true"; +defparam \sdram_|r.address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N22 +cycloneive_lcell_comb \sdram_|Mux20~4 ( +// Equation(s): +// \sdram_|Mux20~4_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & \sdram_|r.init_counter [0])) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [7]), + .datac(gnd), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Mux20~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~4 .lut_mask = 16'h2200; +defparam \sdram_|Mux20~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N26 +cycloneive_lcell_comb \sdram_|Mux20~7 ( +// Equation(s): +// \sdram_|Mux20~7_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\sdram_|r.state [6] & (!\z80_|address_pins_|DFFE_apin_latch [15])) # (!\sdram_|r.state [6] & ((!\z80_|address_pins_|DFFE_apin_latch [3]))))) + + .dataa(\sdram_|r.state [6]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\z80_|address_pins_|DFFE_apin_latch [3]), + .cin(gnd), + .combout(\sdram_|Mux20~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~7 .lut_mask = 16'h084C; +defparam \sdram_|Mux20~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N10 +cycloneive_lcell_comb \sdram_|Mux23~7 ( +// Equation(s): +// \sdram_|Mux23~7_combout = (\sdram_|r.state [4] & (\sdram_|process_0~2_combout & ((\sdram_|r.state [6]) # (\sdram_|Equal7~2_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux23~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~7 .lut_mask = 16'hE000; +defparam \sdram_|Mux23~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N10 +cycloneive_lcell_comb \sdram_|Mux20~8 ( +// Equation(s): +// \sdram_|Mux20~8_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] $ (((\sdram_|r.state [8]))))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [4] & (\sdram_|n~3_combout & !\sdram_|r.state [8]))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|n~3_combout ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux20~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~8 .lut_mask = 16'h50A4; +defparam \sdram_|Mux20~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N18 +cycloneive_lcell_comb \sdram_|Mux20~10 ( +// Equation(s): +// \sdram_|Mux20~10_combout = (\sdram_|r.state [8] & (\sdram_|Mux20~7_combout & (\sdram_|Mux23~7_combout & !\sdram_|Mux20~8_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux20~8_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux20~7_combout ), + .datac(\sdram_|Mux23~7_combout ), + .datad(\sdram_|Mux20~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~10 .lut_mask = 16'h5580; +defparam \sdram_|Mux20~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N0 +cycloneive_lcell_comb \sdram_|Mux20~9 ( +// Equation(s): +// \sdram_|Mux20~9_combout = (\sdram_|r.state [8] & (!\sdram_|Mux20~7_combout & (\sdram_|Mux23~7_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux20~8_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux20~7_combout ), + .datac(\sdram_|Mux23~7_combout ), + .datad(\sdram_|Mux20~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~9 .lut_mask = 16'h7520; +defparam \sdram_|Mux20~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N24 +cycloneive_lcell_comb \sdram_|Mux20~11 ( +// Equation(s): +// \sdram_|Mux20~11_combout = (\sdram_|Mux20~10_combout & (((\z80_|address_pins_|abus[3]~27_combout & \sdram_|Mux20~9_combout )))) # (!\sdram_|Mux20~10_combout & ((\sdram_|r.address[4]~_Duplicate_1_q ) # ((\sdram_|Mux20~9_combout )))) + + .dataa(\sdram_|r.address[4]~_Duplicate_1_q ), + .datab(\z80_|address_pins_|abus[3]~27_combout ), + .datac(\sdram_|Mux20~10_combout ), + .datad(\sdram_|Mux20~9_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~11 .lut_mask = 16'hCF0A; +defparam \sdram_|Mux20~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y11_N5 +dffeas \sdram_|r.address[4]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[4]~2_combout ), + .asdata(\sdram_|Mux20~11_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\sdram_|r.state [7]), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[4]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[4]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[4]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N2 +cycloneive_lcell_comb \sdram_|Mux20~12 ( +// Equation(s): +// \sdram_|Mux20~12_combout = (\sdram_|process_0~2_combout & (((\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) # (!\sdram_|process_0~2_combout & (\sdram_|r.address[4]~_Duplicate_1_q )) + + .dataa(\sdram_|r.address[4]~_Duplicate_1_q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~12 .lut_mask = 16'hCFAA; +defparam \sdram_|Mux20~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N4 +cycloneive_lcell_comb \sdram_|Mux20~5 ( +// Equation(s): +// \sdram_|Mux20~5_combout = (\sdram_|r.state [4] & (((\sdram_|Mux20~12_combout )))) # (!\sdram_|r.state [4] & (\sdram_|Mux20~4_combout & (\sdram_|Equal2~2_combout ))) + + .dataa(\sdram_|Mux20~4_combout ), + .datab(\sdram_|Equal2~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|Mux20~12_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~5 .lut_mask = 16'hF808; +defparam \sdram_|Mux20~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N16 +cycloneive_lcell_comb \sdram_|Mux20~6 ( +// Equation(s): +// \sdram_|Mux20~6_combout = (\sdram_|Mux24~2_combout & ((\sdram_|r.state [4] & ((\sdram_|r.address[4]~_Duplicate_1_q ))) # (!\sdram_|r.state [4] & (\z80_|address_pins_|abus[3]~27_combout )))) # (!\sdram_|Mux24~2_combout & +// (((\sdram_|r.address[4]~_Duplicate_1_q )))) + + .dataa(\sdram_|Mux24~2_combout ), + .datab(\z80_|address_pins_|abus[3]~27_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.address[4]~_Duplicate_1_q ), + .cin(gnd), + .combout(\sdram_|Mux20~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~6 .lut_mask = 16'hFD08; +defparam \sdram_|Mux20~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N4 +cycloneive_lcell_comb \sdram_|r.address[4]~2 ( +// Equation(s): +// \sdram_|r.address[4]~2_combout = (\sdram_|r.state [8] & ((\sdram_|Mux20~6_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux20~5_combout )) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux20~5_combout ), + .datac(gnd), + .datad(\sdram_|Mux20~6_combout ), + .cin(gnd), + .combout(\sdram_|r.address[4]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[4]~2 .lut_mask = 16'hEE44; +defparam \sdram_|r.address[4]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N8 +cycloneive_lcell_comb \sdram_|r.address[4]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[4]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux20~11_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[4]~2_combout )) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.address[4]~2_combout ), + .datad(\sdram_|Mux20~11_combout ), + .cin(gnd), + .combout(\sdram_|r.address[4]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[4]~SLOAD_MUX .lut_mask = 16'hFC30; +defparam \sdram_|r.address[4]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X25_Y0_N18 +dffeas \sdram_|r.address[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[4]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[4] .is_wysiwyg = "true"; +defparam \sdram_|r.address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N26 +cycloneive_lcell_comb \sdram_|Mux19~1 ( +// Equation(s): +// \sdram_|Mux19~1_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [0]))) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [7]), + .datac(\sdram_|Equal2~2_combout ), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Mux19~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~1 .lut_mask = 16'h2000; +defparam \sdram_|Mux19~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N12 +cycloneive_lcell_comb \sdram_|Mux19~4 ( +// Equation(s): +// \sdram_|Mux19~4_combout = (\sdram_|r.state [8] & (\sdram_|Mux23~7_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.bank[0]~4_combout ))) + + .dataa(\sdram_|r.state [8]), + .datab(gnd), + .datac(\sdram_|Mux23~7_combout ), + .datad(\sdram_|r.bank[0]~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux19~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~4 .lut_mask = 16'hF5A0; +defparam \sdram_|Mux19~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N22 +cycloneive_lcell_comb \sdram_|Mux19~5 ( +// Equation(s): +// \sdram_|Mux19~5_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [8] & (\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & (\sdram_|Mux19~4_combout & ((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux19~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux19~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~5 .lut_mask = 16'h4B40; +defparam \sdram_|Mux19~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N20 +cycloneive_lcell_comb \sdram_|Mux19~6 ( +// Equation(s): +// \sdram_|Mux19~6_combout = (\sdram_|r.state [8] & (\sdram_|r.state [4] & (\sdram_|r.state [6] & \sdram_|Mux19~4_combout ))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux19~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux19~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~6 .lut_mask = 16'h8000; +defparam \sdram_|Mux19~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N14 +cycloneive_lcell_comb \sdram_|Mux19~7 ( +// Equation(s): +// \sdram_|Mux19~7_combout = (\sdram_|Mux19~5_combout & ((\sdram_|Mux19~6_combout & ((\sdram_|r.address[5]~_Duplicate_1_q ))) # (!\sdram_|Mux19~6_combout & (\z80_|address_pins_|abus[4]~28_combout )))) # (!\sdram_|Mux19~5_combout & +// (((\sdram_|r.address[5]~_Duplicate_1_q & !\sdram_|Mux19~6_combout )))) + + .dataa(\z80_|address_pins_|abus[4]~28_combout ), + .datab(\sdram_|r.address[5]~_Duplicate_1_q ), + .datac(\sdram_|Mux19~5_combout ), + .datad(\sdram_|Mux19~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux19~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~7 .lut_mask = 16'hC0AC; +defparam \sdram_|Mux19~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y11_N31 +dffeas \sdram_|r.address[5]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[5]~3_combout ), + .asdata(\sdram_|Mux19~7_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\sdram_|r.state [7]), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[5]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[5]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[5]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N20 +cycloneive_lcell_comb \sdram_|Mux19~2 ( +// Equation(s): +// \sdram_|Mux19~2_combout = (\sdram_|r.state [4] & (((!\sdram_|process_0~2_combout & \sdram_|r.address[5]~_Duplicate_1_q )))) # (!\sdram_|r.state [4] & (\sdram_|Mux19~1_combout )) + + .dataa(\sdram_|Mux19~1_combout ), + .datab(\sdram_|process_0~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.address[5]~_Duplicate_1_q ), + .cin(gnd), + .combout(\sdram_|Mux19~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~2 .lut_mask = 16'h3A0A; +defparam \sdram_|Mux19~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N6 +cycloneive_lcell_comb \sdram_|Mux19~3 ( +// Equation(s): +// \sdram_|Mux19~3_combout = (\sdram_|Mux24~2_combout & ((\sdram_|r.state [4] & ((\sdram_|r.address[5]~_Duplicate_1_q ))) # (!\sdram_|r.state [4] & (\z80_|address_pins_|abus[4]~28_combout )))) # (!\sdram_|Mux24~2_combout & +// (((\sdram_|r.address[5]~_Duplicate_1_q )))) + + .dataa(\sdram_|Mux24~2_combout ), + .datab(\sdram_|r.state [4]), + .datac(\z80_|address_pins_|abus[4]~28_combout ), + .datad(\sdram_|r.address[5]~_Duplicate_1_q ), + .cin(gnd), + .combout(\sdram_|Mux19~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~3 .lut_mask = 16'hFD20; +defparam \sdram_|Mux19~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N30 +cycloneive_lcell_comb \sdram_|r.address[5]~3 ( +// Equation(s): +// \sdram_|r.address[5]~3_combout = (\sdram_|r.state [8] & ((\sdram_|Mux19~3_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux19~2_combout )) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux19~2_combout ), + .datac(gnd), + .datad(\sdram_|Mux19~3_combout ), + .cin(gnd), + .combout(\sdram_|r.address[5]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[5]~3 .lut_mask = 16'hEE44; +defparam \sdram_|r.address[5]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N26 +cycloneive_lcell_comb \sdram_|r.address[5]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[5]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux19~7_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[5]~3_combout )) + + .dataa(\sdram_|r.address[5]~3_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux19~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[5]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[5]~SLOAD_MUX .lut_mask = 16'hE2E2; +defparam \sdram_|r.address[5]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X18_Y0_N25 +dffeas \sdram_|r.address[5] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[5]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[5] .is_wysiwyg = "true"; +defparam \sdram_|r.address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N6 +cycloneive_lcell_comb \sdram_|Mux18~0 ( +// Equation(s): +// \sdram_|Mux18~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [5]), + .datad(\sdram_|r.address[3]~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux18~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux18~0 .lut_mask = 16'hF500; +defparam \sdram_|Mux18~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X20_Y0_N4 +dffeas \sdram_|r.address[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux18~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[6] .is_wysiwyg = "true"; +defparam \sdram_|r.address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N4 +cycloneive_lcell_comb \sdram_|Mux17~0 ( +// Equation(s): +// \sdram_|Mux17~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [6]), + .datad(\sdram_|r.address[3]~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux17~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux17~0 .lut_mask = 16'hF500; +defparam \sdram_|Mux17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X14_Y0_N4 +dffeas \sdram_|r.address[7] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux17~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[7] .is_wysiwyg = "true"; +defparam \sdram_|r.address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N22 +cycloneive_lcell_comb \sdram_|Mux16~0 ( +// Equation(s): +// \sdram_|Mux16~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [7]), + .datad(\sdram_|r.address[3]~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux16~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux16~0 .lut_mask = 16'hF500; +defparam \sdram_|Mux16~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y5_N25 +dffeas \sdram_|r.address[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux16~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[8] .is_wysiwyg = "true"; +defparam \sdram_|r.address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N30 +cycloneive_lcell_comb \sdram_|Mux15~2 ( +// Equation(s): +// \sdram_|Mux15~2_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [8]), + .datac(gnd), + .datad(\sdram_|r.address[3]~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux15~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux15~2 .lut_mask = 16'hDD00; +defparam \sdram_|Mux15~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y4_N25 +dffeas \sdram_|r.address[9] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux15~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[9] .is_wysiwyg = "true"; +defparam \sdram_|r.address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N22 +cycloneive_lcell_comb \sdram_|Mux14~0 ( +// Equation(s): +// \sdram_|Mux14~0_combout = (\sdram_|r.rf_pending~q ) # ((\sdram_|n~4_combout & ((\sdram_|r.state [6]) # (!\sdram_|process_0~3_combout )))) + + .dataa(\sdram_|process_0~3_combout ), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|n~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux14~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~0 .lut_mask = 16'hFDCC; +defparam \sdram_|Mux14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N28 +cycloneive_lcell_comb \sdram_|Mux14~1 ( +// Equation(s): +// \sdram_|Mux14~1_combout = (\sdram_|r.state [4] & (((\sdram_|r.address[10]~_Duplicate_1_q & !\sdram_|process_0~2_combout )))) # (!\sdram_|r.state [4] & (\sdram_|Equal2~3_combout )) + + .dataa(\sdram_|Equal2~3_combout ), + .datab(\sdram_|r.address[10]~_Duplicate_1_q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux14~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~1 .lut_mask = 16'h0ACA; +defparam \sdram_|Mux14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N10 +cycloneive_lcell_comb \sdram_|r.address[10]~4 ( +// Equation(s): +// \sdram_|r.address[10]~4_combout = (\sdram_|r.state [8] & (\sdram_|Mux14~0_combout )) # (!\sdram_|r.state [8] & ((\sdram_|Mux14~1_combout ))) + + .dataa(\sdram_|Mux14~0_combout ), + .datab(\sdram_|r.state [8]), + .datac(gnd), + .datad(\sdram_|Mux14~1_combout ), + .cin(gnd), + .combout(\sdram_|r.address[10]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[10]~4 .lut_mask = 16'hBB88; +defparam \sdram_|r.address[10]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y11_N11 +dffeas \sdram_|r.address[10]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[10]~4_combout ), + .asdata(\sdram_|Mux14~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\sdram_|r.state [7]), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[10]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[10]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[10]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N16 +cycloneive_lcell_comb \sdram_|n~4 ( +// Equation(s): +// \sdram_|n~4_combout = (\sdram_|r.rd_pending~q & (!\sdram_|Equal7~2_combout )) # (!\sdram_|r.rd_pending~q & (((\sdram_|r.address[10]~_Duplicate_1_q ) # (\sdram_|r.wr_pending~q )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.address[10]~_Duplicate_1_q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|n~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|n~4 .lut_mask = 16'h5F5C; +defparam \sdram_|n~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N30 +cycloneive_lcell_comb \sdram_|Mux14~2 ( +// Equation(s): +// \sdram_|Mux14~2_combout = (!\sdram_|r.state [6] & ((\sdram_|r.rf_pending~q ) # ((!\sdram_|process_0~3_combout & \sdram_|n~4_combout )))) + + .dataa(\sdram_|process_0~3_combout ), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|n~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux14~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~2 .lut_mask = 16'h0D0C; +defparam \sdram_|Mux14~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N8 +cycloneive_lcell_comb \sdram_|Mux14~3 ( +// Equation(s): +// \sdram_|Mux14~3_combout = (\sdram_|Mux14~2_combout ) # ((\sdram_|r.address[10]~_Duplicate_1_q & (\sdram_|Mux23~0_combout & !\sdram_|process_0~2_combout ))) + + .dataa(\sdram_|Mux14~2_combout ), + .datab(\sdram_|r.address[10]~_Duplicate_1_q ), + .datac(\sdram_|Mux23~0_combout ), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux14~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~3 .lut_mask = 16'hAAEA; +defparam \sdram_|Mux14~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N26 +cycloneive_lcell_comb \sdram_|r.address[10]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[10]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux14~3_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[10]~4_combout ))) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux14~3_combout ), + .datad(\sdram_|r.address[10]~4_combout ), + .cin(gnd), + .combout(\sdram_|r.address[10]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[10]~SLOAD_MUX .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[10]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y8_N25 +dffeas \sdram_|r.address[10] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[10]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[10] .is_wysiwyg = "true"; +defparam \sdram_|r.address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N28 +cycloneive_lcell_comb \sdram_|r.address[11]~18 ( +// Equation(s): +// \sdram_|r.address[11]~18_combout = (!\sdram_|r.rd_pending~q & (\sdram_|r.state [4] & !\sdram_|r.wr_pending~q )) + + .dataa(gnd), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|r.address[11]~18_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~18 .lut_mask = 16'h0030; +defparam \sdram_|r.address[11]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N26 +cycloneive_lcell_comb \sdram_|r.address[11]~5 ( +// Equation(s): +// \sdram_|r.address[11]~5_combout = (\sdram_|r.address[11]~_Duplicate_2_q & ((\sdram_|r.state [8] & (!\sdram_|Mux24~2_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.address[11]~18_combout ))))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux24~2_combout ), + .datac(\sdram_|r.address[11]~_Duplicate_2_q ), + .datad(\sdram_|r.address[11]~18_combout ), + .cin(gnd), + .combout(\sdram_|r.address[11]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~5 .lut_mask = 16'h7020; +defparam \sdram_|r.address[11]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N4 +cycloneive_lcell_comb \sdram_|r.address[11]~_Duplicate_2feeder ( +// Equation(s): +// \sdram_|r.address[11]~_Duplicate_2feeder_combout = \sdram_|r.address[11]~5_combout + + .dataa(\sdram_|r.address[11]~5_combout ), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[11]~_Duplicate_2feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~_Duplicate_2feeder .lut_mask = 16'hAAAA; +defparam \sdram_|r.address[11]~_Duplicate_2feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y11_N5 +dffeas \sdram_|r.address[11]~_Duplicate_2 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[11]~_Duplicate_2feeder_combout ), + .asdata(\sdram_|Mux13~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\sdram_|r.state [7]), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[11]~_Duplicate_2_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[11]~_Duplicate_2 .is_wysiwyg = "true"; +defparam \sdram_|r.address[11]~_Duplicate_2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N8 +cycloneive_lcell_comb \sdram_|Mux13~10 ( +// Equation(s): +// \sdram_|Mux13~10_combout = (\sdram_|r.address[11]~_Duplicate_2_q & ((\sdram_|r.state [8]) # (!\sdram_|r.state [6]))) + + .dataa(gnd), + .datab(\sdram_|r.address[11]~_Duplicate_2_q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux13~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~10 .lut_mask = 16'hCC0C; +defparam \sdram_|Mux13~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N22 +cycloneive_lcell_comb \sdram_|Mux13~6 ( +// Equation(s): +// \sdram_|Mux13~6_combout = (\sdram_|Mux13~10_combout & (((!\sdram_|r.state [6] & !\sdram_|Equal7~2_combout )) # (!\sdram_|process_0~2_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|Mux13~10_combout ), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux13~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~6 .lut_mask = 16'h10F0; +defparam \sdram_|Mux13~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N12 +cycloneive_lcell_comb \sdram_|r.address[11]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[11]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux13~6_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[11]~5_combout ))) + + .dataa(\sdram_|Mux13~6_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.address[11]~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[11]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~SLOAD_MUX .lut_mask = 16'hB8B8; +defparam \sdram_|r.address[11]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y7_N4 +dffeas \sdram_|r.address[11] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[11]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[11] .is_wysiwyg = "true"; +defparam \sdram_|r.address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N6 +cycloneive_lcell_comb \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux13~6_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[11]~5_combout ))) + + .dataa(\sdram_|Mux13~6_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.address[11]~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX .lut_mask = 16'hB8B8; +defparam \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y6_N18 +dffeas \sdram_|r.address[11]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[11]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[11]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[11]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + // Location: IOIBUF_X0_Y16_N22 cycloneive_io_ibuf \SW[0]~input ( .i(SW[0]), @@ -59899,4 +65745,164 @@ defparam \I2C_SCLK~input .bus_hold = "false"; defparam \I2C_SCLK~input .simulate_z_as = "z"; // synopsys translate_on +// Location: IOIBUF_X0_Y23_N15 +cycloneive_io_ibuf \DRAM_DQ[0]~input ( + .i(DRAM_DQ[0]), + .ibar(gnd), + .o(\DRAM_DQ[0]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[0]~input .bus_hold = "false"; +defparam \DRAM_DQ[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y23_N22 +cycloneive_io_ibuf \DRAM_DQ[1]~input ( + .i(DRAM_DQ[1]), + .ibar(gnd), + .o(\DRAM_DQ[1]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[1]~input .bus_hold = "false"; +defparam \DRAM_DQ[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N8 +cycloneive_io_ibuf \DRAM_DQ[2]~input ( + .i(DRAM_DQ[2]), + .ibar(gnd), + .o(\DRAM_DQ[2]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[2]~input .bus_hold = "false"; +defparam \DRAM_DQ[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y7_N8 +cycloneive_io_ibuf \DRAM_DQ[3]~input ( + .i(DRAM_DQ[3]), + .ibar(gnd), + .o(\DRAM_DQ[3]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[3]~input .bus_hold = "false"; +defparam \DRAM_DQ[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y12_N1 +cycloneive_io_ibuf \DRAM_DQ[4]~input ( + .i(DRAM_DQ[4]), + .ibar(gnd), + .o(\DRAM_DQ[4]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[4]~input .bus_hold = "false"; +defparam \DRAM_DQ[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y15_N1 +cycloneive_io_ibuf \DRAM_DQ[5]~input ( + .i(DRAM_DQ[5]), + .ibar(gnd), + .o(\DRAM_DQ[5]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[5]~input .bus_hold = "false"; +defparam \DRAM_DQ[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y15_N8 +cycloneive_io_ibuf \DRAM_DQ[6]~input ( + .i(DRAM_DQ[6]), + .ibar(gnd), + .o(\DRAM_DQ[6]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[6]~input .bus_hold = "false"; +defparam \DRAM_DQ[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y0_N15 +cycloneive_io_ibuf \DRAM_DQ[7]~input ( + .i(DRAM_DQ[7]), + .ibar(gnd), + .o(\DRAM_DQ[7]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[7]~input .bus_hold = "false"; +defparam \DRAM_DQ[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y0_N15 +cycloneive_io_ibuf \DRAM_DQ[8]~input ( + .i(DRAM_DQ[8]), + .ibar(gnd), + .o(\DRAM_DQ[8]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[8]~input .bus_hold = "false"; +defparam \DRAM_DQ[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y0_N1 +cycloneive_io_ibuf \DRAM_DQ[9]~input ( + .i(DRAM_DQ[9]), + .ibar(gnd), + .o(\DRAM_DQ[9]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[9]~input .bus_hold = "false"; +defparam \DRAM_DQ[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X1_Y0_N1 +cycloneive_io_ibuf \DRAM_DQ[10]~input ( + .i(DRAM_DQ[10]), + .ibar(gnd), + .o(\DRAM_DQ[10]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[10]~input .bus_hold = "false"; +defparam \DRAM_DQ[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X1_Y0_N8 +cycloneive_io_ibuf \DRAM_DQ[11]~input ( + .i(DRAM_DQ[11]), + .ibar(gnd), + .o(\DRAM_DQ[11]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[11]~input .bus_hold = "false"; +defparam \DRAM_DQ[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y0_N22 +cycloneive_io_ibuf \DRAM_DQ[12]~input ( + .i(DRAM_DQ[12]), + .ibar(gnd), + .o(\DRAM_DQ[12]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[12]~input .bus_hold = "false"; +defparam \DRAM_DQ[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X1_Y0_N15 +cycloneive_io_ibuf \DRAM_DQ[13]~input ( + .i(DRAM_DQ[13]), + .ibar(gnd), + .o(\DRAM_DQ[13]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[13]~input .bus_hold = "false"; +defparam \DRAM_DQ[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X1_Y0_N22 +cycloneive_io_ibuf \DRAM_DQ[14]~input ( + .i(DRAM_DQ[14]), + .ibar(gnd), + .o(\DRAM_DQ[14]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[14]~input .bus_hold = "false"; +defparam \DRAM_DQ[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y12_N8 +cycloneive_io_ibuf \DRAM_DQ[15]~input ( + .i(DRAM_DQ[15]), + .ibar(gnd), + .o(\DRAM_DQ[15]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[15]~input .bus_hold = "false"; +defparam \DRAM_DQ[15]~input .simulate_z_as = "z"; +// synopsys translate_on + endmodule diff --git a/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo b/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo index 5f5d1b7..518d14d 100644 --- a/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo +++ b/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "04/01/2022 18:55:51" +// DATE "04/02/2022 14:51:20" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -50,14 +50,24 @@ module spectrum ( SW, GPIO_1, buzzer_out, - raw_loader_in); + raw_loader_in, + DRAM_BA, + DRAM_DQM, + DRAM_RAS_N, + DRAM_CAS_N, + DRAM_CKE, + DRAM_CLK, + DRAM_WE_N, + DRAM_CS_N, + DRAM_DQ, + DRAM_ADDR); output [7:0] LED; input CLOCK_50; input [1:0] KEY; input PS2_CLK; input PS2_DAT; -output I2C_SCLK; -output I2C_SDAT; +inout I2C_SCLK; +inout I2C_SDAT; output AUD_XCK; output AUD_ADCLRCK; output AUD_DACLRCK; @@ -73,6 +83,16 @@ input [3:0] SW; output [33:0] GPIO_1; output buzzer_out; input raw_loader_in; +output [1:0] DRAM_BA; +output [1:0] DRAM_DQM; +output DRAM_RAS_N; +output DRAM_CAS_N; +output DRAM_CKE; +output DRAM_CLK; +output DRAM_WE_N; +output DRAM_CS_N; +inout [15:0] DRAM_DQ; +output [12:0] DRAM_ADDR; // Design Ports Information // LED[0] => Location: PIN_A15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -139,8 +159,47 @@ input raw_loader_in; // GPIO_1[32] => Location: PIN_J13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // GPIO_1[33] => Location: PIN_J14, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // buzzer_out => Location: PIN_A6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_BA[0] => Location: PIN_M7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_BA[1] => Location: PIN_M6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQM[0] => Location: PIN_R6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQM[1] => Location: PIN_T5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_RAS_N => Location: PIN_L2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_CAS_N => Location: PIN_L1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_CKE => Location: PIN_L7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_CLK => Location: PIN_R4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_WE_N => Location: PIN_C2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_CS_N => Location: PIN_P6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[0] => Location: PIN_P2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[1] => Location: PIN_N5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[2] => Location: PIN_N6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[3] => Location: PIN_M8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[4] => Location: PIN_P8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[5] => Location: PIN_T7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[6] => Location: PIN_N8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[7] => Location: PIN_T6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[8] => Location: PIN_R1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[9] => Location: PIN_P1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[10] => Location: PIN_N2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[11] => Location: PIN_N1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[12] => Location: PIN_L4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // I2C_SCLK => Location: PIN_F2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // I2C_SDAT => Location: PIN_F1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[0] => Location: PIN_G2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[1] => Location: PIN_G1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[2] => Location: PIN_L8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[3] => Location: PIN_K5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[4] => Location: PIN_K2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[5] => Location: PIN_J2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[6] => Location: PIN_J1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[7] => Location: PIN_R7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[8] => Location: PIN_T4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[9] => Location: PIN_T2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[10] => Location: PIN_T3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[11] => Location: PIN_R3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[12] => Location: PIN_R5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[13] => Location: PIN_P3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[14] => Location: PIN_N3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[15] => Location: PIN_K1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // SW[1] => Location: PIN_T8, I/O Standard: 3.3-V LVTTL, Current Strength: Default // SW[2] => Location: PIN_B9, I/O Standard: 3.3-V LVTTL, Current Strength: Default // raw_loader_in => Location: PIN_B6, I/O Standard: 3.3-V LVTTL, Current Strength: Default @@ -170,6 +229,22 @@ initial $sdf_annotate("spectrum_6_1200mv_0c_v_slow.sdo"); wire \SW[0]~input_o ; wire \SW[3]~input_o ; wire \I2C_SCLK~input_o ; +wire \DRAM_DQ[0]~input_o ; +wire \DRAM_DQ[1]~input_o ; +wire \DRAM_DQ[2]~input_o ; +wire \DRAM_DQ[3]~input_o ; +wire \DRAM_DQ[4]~input_o ; +wire \DRAM_DQ[5]~input_o ; +wire \DRAM_DQ[6]~input_o ; +wire \DRAM_DQ[7]~input_o ; +wire \DRAM_DQ[8]~input_o ; +wire \DRAM_DQ[9]~input_o ; +wire \DRAM_DQ[10]~input_o ; +wire \DRAM_DQ[11]~input_o ; +wire \DRAM_DQ[12]~input_o ; +wire \DRAM_DQ[13]~input_o ; +wire \DRAM_DQ[14]~input_o ; +wire \DRAM_DQ[15]~input_o ; wire \CLOCK_50~input_o ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_fbout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ; @@ -178,692 +253,8 @@ wire \SW[2]~input_o ; wire \ula_|clocks_|clk_cpu~0_combout ; wire \ula_|clocks_|clk_cpu~q ; wire \ula_|clocks_|clk_cpu~clkctrl_outclk ; -wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; -wire \z80_|sequencer_|ena_M~combout ; wire \KEY[1]~input_o ; wire \z80_|interrupts_|nmi_armed~feeder_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; -wire \z80_|interrupts_|nmi_armed~q ; -wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ; -wire \z80_|execute_|ctl_eval_cond~0_combout ; -wire \z80_|execute_|ixy_d~4_combout ; -wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M3_ff~q ; -wire \z80_|execute_|fIOWrite~1_combout ; -wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M4_ff~q ; -wire \z80_|pla_decode_|Equal32~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; -wire \z80_|decode_state_|table_xx~0_combout ; -wire \z80_|pla_decode_|Equal1~7_combout ; -wire \z80_|pla_decode_|Equal2~0_combout ; -wire \z80_|pla_decode_|Equal36~0_combout ; -wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; -wire \z80_|execute_|ctl_state_tbl_we~8_combout ; -wire \z80_|decode_state_|DFFE_instCB~q ; -wire \z80_|pla_decode_|Equal52~0_combout ; -wire \z80_|pla_decode_|Equal2~1_combout ; -wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; -wire \z80_|decode_state_|DFFE_instED~q ; -wire \z80_|pla_decode_|Equal13~0_combout ; -wire \z80_|pla_decode_|Equal33~0_combout ; -wire \z80_|execute_|ctl_im_we~combout ; -wire \z80_|pla_decode_|Equal49~0_combout ; -wire \z80_|pla_decode_|Equal33~1_combout ; -wire \z80_|pla_decode_|Equal6~0_combout ; -wire \z80_|execute_|ctl_mRead~14_combout ; -wire \z80_|pla_decode_|Equal12~0_combout ; -wire \z80_|execute_|ctl_sw_1d~8_combout ; -wire \z80_|nM1_int~2_combout ; -wire \z80_|execute_|ctl_sw_1d~5_combout ; -wire \z80_|pla_decode_|Equal3~0_combout ; -wire \z80_|execute_|ctl_mRead~4_combout ; -wire \z80_|execute_|ixy_d~7_combout ; -wire \z80_|execute_|ctl_state_alu~4_combout ; -wire \z80_|execute_|ctl_sw_1d~4_combout ; -wire \z80_|pla_decode_|Equal40~1_combout ; -wire \z80_|pla_decode_|Equal39~0_combout ; -wire \z80_|execute_|ctl_bus_db_oe~1_combout ; -wire \z80_|pla_decode_|Equal13~1_combout ; -wire \z80_|pla_decode_|Equal13~2_combout ; -wire \z80_|pla_decode_|Equal3~2_combout ; -wire \z80_|execute_|ctl_state_iy_set~2_combout ; -wire \z80_|execute_|ixy_d~8_combout ; -wire \z80_|execute_|ixy_d~6_combout ; -wire \z80_|execute_|ixy_d~9_combout ; -wire \z80_|execute_|ixy_d~12_combout ; -wire \z80_|execute_|ixy_d~10_combout ; -wire \z80_|pla_decode_|Equal44~0_combout ; -wire \z80_|execute_|ixy_d~16_combout ; -wire \z80_|execute_|ixy_d~13_combout ; -wire \z80_|pla_decode_|Equal50~0_combout ; -wire \z80_|pla_decode_|Equal33~2_combout ; -wire \z80_|execute_|ixy_d~17_combout ; -wire \z80_|execute_|ixy_d~5_combout ; -wire \z80_|execute_|ixy_d~14_combout ; -wire \z80_|execute_|ixy_d~11_combout ; -wire \z80_|execute_|ixy_d~15_combout ; -wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; -wire \z80_|decode_state_|DFFE_instIY1~q ; -wire \z80_|execute_|ctl_ir_we~5_combout ; -wire \z80_|execute_|ctl_ir_we~14_combout ; -wire \z80_|execute_|ctl_mWrite~2_combout ; -wire \z80_|execute_|ctl_mWrite~16_combout ; -wire \z80_|execute_|ctl_flags_alu~18_combout ; -wire \z80_|execute_|ctl_mRead~26_combout ; -wire \z80_|execute_|ctl_mRead~27_combout ; -wire \z80_|execute_|ctl_bus_db_oe~7_combout ; -wire \z80_|execute_|ctl_sw_2d~5_combout ; -wire \z80_|execute_|ctl_mRead~18_combout ; -wire \z80_|pla_decode_|Equal55~0_combout ; -wire \z80_|execute_|comb~1_combout ; -wire \z80_|execute_|ctl_mRead~15_combout ; -wire \z80_|execute_|ctl_mRead~17_combout ; -wire \z80_|execute_|ctl_reg_in_hi~5_combout ; -wire \z80_|execute_|ctl_mRead~9_combout ; -wire \z80_|pla_decode_|Equal9~0_combout ; -wire \z80_|execute_|ctl_mRead~10_combout ; -wire \z80_|execute_|ctl_mRead~8_combout ; -wire \z80_|execute_|ctl_mRead~20_combout ; -wire \z80_|pla_decode_|Equal12~1_combout ; -wire \z80_|pla_decode_|Equal9~1_combout ; -wire \z80_|pla_decode_|Equal25~0_combout ; -wire \z80_|execute_|ctl_mRead~21_combout ; -wire \z80_|execute_|ctl_state_alu~6_combout ; -wire \z80_|pla_decode_|Equal19~0_combout ; -wire \z80_|pla_decode_|Equal1~4_combout ; -wire \z80_|pla_decode_|Equal29~0_combout ; -wire \z80_|pla_decode_|Equal24~1_combout ; -wire \z80_|pla_decode_|Equal34~0_combout ; -wire \z80_|pla_decode_|Equal37~0_combout ; -wire \z80_|pla_decode_|Equal35~0_combout ; -wire \z80_|pla_decode_|Equal38~2_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; -wire \z80_|execute_|comb~0_combout ; -wire \z80_|pla_decode_|Equal47~0_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; -wire \z80_|execute_|ctl_mRead~22_combout ; -wire \z80_|execute_|ctl_mRead~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_in_hi~6_combout ; -wire \z80_|pla_decode_|Equal6~1_combout ; -wire \z80_|execute_|ctl_mRead~16_combout ; -wire \z80_|sequencer_|M5~0_combout ; -wire \z80_|sequencer_|M5~q ; -wire \z80_|execute_|ctl_reg_in_hi~2_combout ; -wire \z80_|execute_|setM1~29_combout ; -wire \z80_|execute_|ctl_mRead~25_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; -wire \z80_|execute_|ctl_ir_we~7_combout ; -wire \z80_|pla_decode_|Equal52~1_combout ; -wire \z80_|execute_|ctl_state_alu~14_combout ; -wire \z80_|execute_|ctl_state_alu~8_combout ; -wire \z80_|pla_decode_|Equal24~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~1_combout ; -wire \z80_|reg_control_|reg_sel_pc~2_combout ; -wire \z80_|execute_|fMRead~17_combout ; -wire \z80_|execute_|ctl_mRead~6_combout ; -wire \z80_|pla_decode_|Equal11~0_combout ; -wire \z80_|pla_decode_|Equal10~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; -wire \z80_|execute_|ctl_sw_2d~4_combout ; -wire \z80_|execute_|ctl_ir_we~15_combout ; -wire \z80_|execute_|fMRead~16_combout ; -wire \z80_|execute_|ctl_ir_we~9_combout ; -wire \z80_|pla_decode_|Equal46~0_combout ; -wire \z80_|execute_|ctl_ir_we~10_combout ; -wire \z80_|execute_|ctl_flags_alu~17_combout ; -wire \z80_|execute_|ctl_flags_alu~6_combout ; -wire \z80_|execute_|ctl_ir_we~6_combout ; -wire \z80_|execute_|ctl_ir_we~8_combout ; -wire \z80_|execute_|ctl_flags_alu~16_combout ; -wire \z80_|execute_|ctl_reg_in_hi~3_combout ; -wire \z80_|execute_|ctl_mWrite~8_combout ; -wire \z80_|execute_|fMRead~18_combout ; -wire \z80_|execute_|fMRead~19_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; -wire \z80_|execute_|ctl_mRead~36_combout ; -wire \z80_|execute_|ctl_alu_op_low~9_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; -wire \z80_|execute_|ctl_mRead~11_combout ; -wire \z80_|execute_|ctl_sw_2d~6_combout ; -wire \z80_|execute_|ctl_sw_2d~7_combout ; -wire \z80_|execute_|ctl_mWrite~7_combout ; -wire \z80_|execute_|ctl_ir_we~11_combout ; -wire \z80_|execute_|ctl_ir_we~12_combout ; -wire \z80_|execute_|ctl_flags_sz_we~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; -wire \z80_|execute_|ctl_sw_2d~8_combout ; -wire \z80_|execute_|ctl_sw_2d~9_combout ; -wire \z80_|execute_|ctl_sw_1d~6_combout ; -wire \z80_|execute_|ctl_sw_1d~7_combout ; -wire \z80_|execute_|ctl_alu_op_low~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; -wire \z80_|execute_|ctl_reg_out_hi~4_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; -wire \z80_|alu_|db_low[2]~4_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ; -wire \z80_|execute_|ctl_sw_4u~1_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; -wire \z80_|pla_decode_|Equal69~0_combout ; -wire \z80_|pla_decode_|Equal1~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~14_combout ; -wire \z80_|execute_|ctl_alu_op_low~12_combout ; -wire \z80_|pla_decode_|Equal56~0_combout ; -wire \z80_|execute_|ctl_alu_op_low~11_combout ; -wire \z80_|execute_|nextM~2_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~5_combout ; -wire \z80_|execute_|ctl_alu_oe~3_combout ; -wire \z80_|execute_|ctl_alu_op_low~15_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; -wire \z80_|execute_|ctl_alu_core_R~3_combout ; -wire \z80_|execute_|ctl_alu_core_R~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; -wire \z80_|pla_decode_|Equal48~0_combout ; -wire \z80_|execute_|ctl_flags_hf2_we~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; -wire \z80_|execute_|ctl_flags_xy_we~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; -wire \z80_|execute_|ctl_iorw~10_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~13_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; -wire \z80_|execute_|ctl_bus_db_oe~3_combout ; -wire \z80_|pla_decode_|Equal20~0_combout ; -wire \z80_|pla_decode_|Equal68~2_combout ; -wire \z80_|execute_|ctl_flags_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op_low~13_combout ; -wire \z80_|execute_|ctl_flags_bus~15_combout ; -wire \z80_|execute_|ctl_flags_bus~11_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ; -wire \z80_|execute_|ctl_flags_bus~10_combout ; -wire \z80_|execute_|ctl_flags_bus~8_combout ; -wire \z80_|execute_|ctl_flags_bus~9_combout ; -wire \z80_|execute_|ctl_flags_bus~12_combout ; -wire \z80_|execute_|ctl_flags_xy_we~11_combout ; -wire \z80_|execute_|ctl_flags_xy_we~12_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; -wire \z80_|execute_|ctl_ir_we~4_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; -wire \z80_|execute_|ctl_bus_db_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; -wire \z80_|execute_|ctl_66_oe~2_combout ; -wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; -wire \z80_|execute_|ctl_alu_op_low~10_combout ; -wire \z80_|execute_|fMWrite~11_combout ; -wire \z80_|execute_|ctl_alu_op_low~21_combout ; -wire \z80_|execute_|ctl_alu_op_low~22_combout ; -wire \z80_|execute_|ctl_alu_op_low~16_combout ; -wire \z80_|execute_|ctl_alu_op_low~17_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; -wire \z80_|execute_|ctl_reg_gp_sel~36_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~4_combout ; -wire \z80_|execute_|ctl_state_alu~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~18_combout ; -wire \z80_|execute_|ctl_alu_op_low~19_combout ; -wire \z80_|execute_|ctl_alu_op_low~33_combout ; -wire \z80_|execute_|ctl_alu_op_low~20_combout ; -wire \z80_|execute_|ctl_alu_op_low~23_combout ; -wire \z80_|execute_|ctl_alu_op_low~24_combout ; -wire \z80_|execute_|ctl_alu_op_low~25_combout ; -wire \z80_|execute_|ctl_alu_op_low~34_combout ; -wire \z80_|execute_|ctl_alu_op_low~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~14_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; -wire \z80_|execute_|ctl_reg_use_sp~0_combout ; -wire \z80_|execute_|ctl_reg_use_sp~1_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; -wire \z80_|execute_|ctl_reg_in_lo~9_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; -wire \z80_|execute_|ctl_flags_xy_we~8_combout ; -wire \z80_|execute_|ctl_flags_xy_we~9_combout ; -wire \z80_|pla_decode_|Equal8~0_combout ; -wire \z80_|execute_|ctl_flags_alu~9_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; -wire \z80_|execute_|ctl_flags_sz_we~3_combout ; -wire \z80_|pla_decode_|Equal11~1_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; -wire \z80_|execute_|ctl_flags_alu~10_combout ; -wire \z80_|execute_|ctl_flags_alu~11_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; -wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; -wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; -wire \z80_|execute_|ctl_flags_cf_we~7_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~2_combout ; -wire \z80_|execute_|ctl_alu_oe~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~25_combout ; -wire \z80_|execute_|ctl_flags_hf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; -wire \z80_|execute_|ctl_flags_pf_we~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~3_combout ; -wire \z80_|execute_|ctl_flags_xy_we~17_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; -wire \z80_|execute_|ctl_flags_xy_we~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; -wire \z80_|execute_|ctl_state_alu~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~1_combout ; -wire \z80_|execute_|ctl_flags_cf_we~2_combout ; -wire \z80_|execute_|ctl_alu_core_S~6_combout ; -wire \z80_|execute_|ctl_alu_core_S~7_combout ; -wire \z80_|execute_|ctl_alu_core_S~4_combout ; -wire \z80_|execute_|ctl_alu_core_S~5_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; -wire \z80_|execute_|ctl_alu_res_oe~0_combout ; -wire \z80_|execute_|ctl_alu_oe~15_combout ; -wire \z80_|execute_|ctl_alu_res_oe~1_combout ; -wire \z80_|execute_|ctl_alu_res_oe~2_combout ; -wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; -wire \z80_|alu_|db_high[3]~2_combout ; -wire \z80_|alu_|db_high[3]~3_combout ; -wire \z80_|alu_|db_low[2]~24_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~7_combout ; -wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_in_hi~8_combout ; -wire \z80_|execute_|ctl_alu_oe~8_combout ; -wire \z80_|execute_|ctl_alu_oe~4_combout ; -wire \z80_|execute_|ctl_mWrite~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~10_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; -wire \z80_|execute_|ctl_bus_db_we~5_combout ; -wire \z80_|execute_|ctl_alu_oe~9_combout ; -wire \z80_|execute_|ctl_alu_oe~11_combout ; -wire \z80_|execute_|ctl_alu_oe~5_combout ; -wire \z80_|execute_|ctl_alu_core_S~11_combout ; -wire \z80_|execute_|ctl_alu_oe~6_combout ; -wire \z80_|execute_|ctl_alu_oe~7_combout ; -wire \z80_|execute_|ctl_alu_oe~12_combout ; -wire \z80_|execute_|ctl_alu_oe~13_combout ; -wire \z80_|execute_|ctl_alu_oe~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ; -wire \z80_|execute_|ctl_reg_out_hi~8_combout ; -wire \z80_|execute_|setM1~54_combout ; -wire \z80_|execute_|ctl_sw_2u~1_combout ; -wire \z80_|execute_|ctl_sw_2u~4_combout ; -wire \z80_|execute_|ctl_sw_2u~5_combout ; -wire \z80_|execute_|ctl_sw_2u~6_combout ; -wire \z80_|execute_|ctl_inc_cy~35_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; -wire \z80_|execute_|ctl_mWrite~6_combout ; -wire \z80_|execute_|ctl_sw_2u~2_combout ; -wire \z80_|execute_|ctl_sw_2u~0_combout ; -wire \z80_|execute_|ctl_sw_2u~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; -wire \z80_|execute_|ctl_reg_out_lo~2_combout ; -wire \z80_|execute_|rsel3~combout ; -wire \z80_|execute_|ctl_reg_out_hi~5_combout ; -wire \z80_|execute_|ctl_reg_out_hi~6_combout ; -wire \z80_|execute_|ctl_reg_out_hi~7_combout ; -wire \z80_|execute_|rsel0~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ; -wire \z80_|execute_|ctl_reg_out_lo~6_combout ; -wire \z80_|execute_|ctl_reg_out_lo~7_combout ; -wire \z80_|execute_|ctl_iorw~11_combout ; -wire \z80_|execute_|ctl_sw_2d~10_combout ; -wire \z80_|execute_|ctl_sw_2d~14_combout ; -wire \z80_|execute_|ctl_sw_2d~11_combout ; -wire \z80_|execute_|ctl_sw_2d~12_combout ; -wire \z80_|execute_|ctl_sw_2d~13_combout ; -wire \z80_|execute_|ctl_66_oe~combout ; -wire \z80_|execute_|ctl_inc_cy~34_combout ; -wire \z80_|execute_|ctl_apin_mux~0_combout ; -wire \z80_|execute_|ctl_sw_4u~5_combout ; -wire \z80_|execute_|ctl_inc_cy~75_combout ; -wire \z80_|execute_|ctl_inc_cy~76_combout ; -wire \z80_|pla_decode_|Equal4~0_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; -wire \z80_|execute_|ctl_inc_cy~53_combout ; -wire \z80_|execute_|ctl_inc_cy~92_combout ; -wire \z80_|pla_decode_|Equal19~1_combout ; -wire \z80_|execute_|ctl_sw_4u~0_combout ; -wire \z80_|execute_|ctl_inc_cy~38_combout ; -wire \z80_|execute_|ctl_inc_cy~93_combout ; -wire \z80_|execute_|ctl_inc_cy~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~24_combout ; -wire \z80_|execute_|ctl_reg_gp_we~1_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; -wire \z80_|execute_|ctl_reg_gp_we~0_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; -wire \z80_|execute_|ctl_sw_4u~2_combout ; -wire \z80_|execute_|ctl_sw_4u~3_combout ; -wire \z80_|execute_|fMRead~3_combout ; -wire \z80_|execute_|ctl_sw_4u~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ; -wire \z80_|execute_|ctl_inc_cy~94_combout ; -wire \z80_|execute_|ctl_inc_cy~87_combout ; -wire \z80_|execute_|ctl_inc_cy~42_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; -wire \z80_|execute_|ctl_sw_4u~6_combout ; -wire \z80_|pla_decode_|Equal2~2_combout ; -wire \z80_|pla_decode_|Equal1~6_combout ; -wire \z80_|reg_control_|bank_exx~2_combout ; -wire \z80_|reg_control_|bank_exx~q ; -wire \z80_|reg_control_|bank_hl_de1~0_combout ; -wire \z80_|reg_control_|bank_hl_de1~q ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~12_combout ; -wire \z80_|execute_|ctl_mRead~7_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~13_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; -wire \z80_|execute_|fMWrite~3_combout ; -wire \z80_|execute_|ctl_flags_bus~5_combout ; -wire \z80_|execute_|fMRead~2_combout ; -wire \z80_|execute_|ctl_mRead~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~7_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; -wire \z80_|execute_|ctl_reg_use_sp~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; -wire \z80_|execute_|ctl_reg_use_sp~3_combout ; -wire \z80_|execute_|ctl_sw_1d~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~21_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~22_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~14_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; -wire \z80_|execute_|setM1~47_combout ; -wire \z80_|execute_|setM1~48_combout ; -wire \z80_|execute_|ctl_al_we~13_combout ; -wire \z80_|execute_|ctl_flags_oe~0_combout ; -wire \z80_|execute_|ctl_flags_oe~1_combout ; -wire \z80_|execute_|ctl_reg_in_hi~13_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; -wire \z80_|execute_|ctl_inc_cy~40_combout ; -wire \z80_|execute_|ctl_inc_dec~2_combout ; -wire \z80_|execute_|ctl_inc_dec~12_combout ; -wire \z80_|execute_|ctl_inc_cy~43_combout ; -wire \z80_|execute_|ctl_inc_dec~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; -wire \z80_|execute_|fMRead~6_combout ; -wire \z80_|execute_|fMRead~7_combout ; -wire \z80_|execute_|fMRead~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; -wire \z80_|execute_|ctl_state_alu~13_combout ; -wire \z80_|execute_|ctl_state_alu~10_combout ; -wire \z80_|execute_|ctl_state_alu~11_combout ; -wire \z80_|execute_|ctl_state_alu~9_combout ; -wire \z80_|pla_decode_|Equal62~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; -wire \z80_|pla_decode_|Equal64~0_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_state_alu~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; -wire \z80_|reg_control_|reg_sel_de2~5_combout ; -wire \z80_|reg_control_|reg_sel_de2~6_combout ; -wire \z80_|reg_control_|reg_sel_hl~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~q ; -wire \z80_|reg_control_|reg_sel_hl2~0_combout ; -wire \z80_|execute_|ctl_reg_in_hi~7_combout ; -wire \z80_|execute_|ctl_reg_gp_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_we~3_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_we~2_combout ; -wire \z80_|execute_|ctl_reg_gp_we~5_combout ; -wire \z80_|execute_|ctl_reg_gp_we~6_combout ; -wire \z80_|execute_|ctl_al_we~14_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; -wire \z80_|execute_|setM1~40_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~93_combout ; -wire \z80_|reg_control_|reg_sel_de~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; -wire \z80_|execute_|ctl_reg_in_hi~9_combout ; -wire \z80_|execute_|ctl_reg_in_hi~10_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; -wire \z80_|execute_|ctl_reg_in_lo~8_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; -wire \z80_|execute_|ctl_reg_use_sp~4_combout ; -wire \z80_|execute_|ctl_reg_use_sp~5_combout ; -wire \z80_|execute_|ctl_reg_use_sp~6_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; -wire \z80_|pla_decode_|Equal21~2_combout ; -wire \z80_|reg_control_|bank_af~0_combout ; -wire \z80_|reg_control_|bank_af~q ; -wire \z80_|reg_control_|reg_sel_af~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|reg_control_|reg_sel_af2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; -wire \z80_|execute_|ctl_flags_bus~4_combout ; -wire \z80_|execute_|ctl_flags_bus~6_combout ; -wire \z80_|execute_|ctl_flags_bus~7_combout ; -wire \z80_|execute_|fMRead~24_combout ; -wire \z80_|execute_|ctl_flags_bus~13_combout ; -wire \z80_|execute_|ctl_flags_bus~combout ; -wire \z80_|execute_|ctl_inc_dec~3_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; -wire \z80_|execute_|ctl_mRead~13_combout ; -wire \z80_|execute_|pc_inc_hold~49_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; -wire \z80_|execute_|pc_inc_hold~28_combout ; -wire \z80_|execute_|setM1~35_combout ; -wire \z80_|execute_|setM1~36_combout ; -wire \z80_|execute_|fMRead~5_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; -wire \z80_|execute_|pc_inc_hold~29_combout ; -wire \z80_|execute_|ctl_reg_sys_we~1_combout ; -wire \z80_|execute_|ctl_reg_sys_we~2_combout ; -wire \z80_|pla_decode_|Equal33~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~2_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~4_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~combout ; -wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; -wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; -wire \z80_|execute_|ctl_reg_out_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; -wire \z80_|execute_|ctl_reg_in_hi~4_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~5_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; -wire \z80_|execute_|ctl_al_we~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; -wire \z80_|execute_|fMRead~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; -wire \z80_|execute_|ctl_inc_dec~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; -wire \z80_|execute_|ctl_al_we~5_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; -wire \z80_|execute_|fMRead~1_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; -wire \z80_|execute_|ctl_inc_cy~77_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; -wire \z80_|execute_|ctl_sw_4d~3_combout ; -wire \z80_|execute_|ctl_sw_4d~4_combout ; -wire \z80_|execute_|ctl_sw_4d~2_combout ; -wire \z80_|execute_|ctl_sw_4d~5_combout ; -wire \z80_|execute_|setM1~45_combout ; -wire \z80_|execute_|setM1~46_combout ; -wire \z80_|execute_|ctl_sw_4d~1_combout ; -wire \z80_|execute_|ctl_sw_4d~0_combout ; -wire \z80_|execute_|ctl_sw_4d~6_combout ; -wire \z80_|execute_|fMRead~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~20_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; -wire \z80_|reg_control_|reg_sel_pc~3_combout ; -wire \z80_|reg_control_|reg_sel_pc~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; -wire \z80_|reg_file_|db_lo_as[0]~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; -wire \z80_|reg_file_|db_lo_as[7]~22_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; -wire \z80_|reg_file_|db_lo_as[7]~23_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; -wire \z80_|resets_|DFFE_intr_ff3~q ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ; wire \KEY[0]~input_o ; wire \reset~combout ; @@ -872,77 +263,13 @@ wire \z80_|fpga_reset~feeder_combout ; wire \z80_|fpga_reset~q ; wire \z80_|fpga_reset~clkctrl_outclk ; wire \z80_|resets_|x1~q ; -wire \z80_|resets_|clrpc_int~0_combout ; -wire \z80_|resets_|clrpc_int~q ; -wire \z80_|resets_|clrpc~0_combout ; -wire \z80_|execute_|ctl_apin_mux~1_combout ; -wire \z80_|execute_|ctl_al_we~6_combout ; -wire \z80_|execute_|ctl_al_we~7_combout ; -wire \z80_|execute_|ctl_al_we~8_combout ; -wire \z80_|execute_|ctl_alu_oe~10_combout ; -wire \z80_|execute_|ctl_al_we~9_combout ; -wire \z80_|execute_|ctl_al_we~10_combout ; -wire \z80_|execute_|ctl_al_we~11_combout ; -wire \z80_|execute_|ctl_al_we~12_combout ; -wire \z80_|execute_|ctl_inc_dec~6_combout ; -wire \z80_|execute_|fIOWrite~0_combout ; -wire \z80_|execute_|ctl_inc_dec~8_combout ; -wire \z80_|execute_|ctl_inc_dec~9_combout ; -wire \z80_|execute_|ctl_inc_dec~10_combout ; -wire \z80_|execute_|ctl_inc_dec~7_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; -wire \z80_|reg_control_|reg_sel_de2~4_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; -wire \z80_|reg_control_|reg_sel_iy~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; -wire \z80_|reg_file_|db_lo_as[2]~7_combout ; -wire \z80_|reg_file_|db_lo_as[2]~8_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; -wire \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; -wire \z80_|reg_file_|db_lo_as[0]~0_combout ; -wire \z80_|reg_file_|db_lo_as[0]~1_combout ; -wire \z80_|execute_|ctl_inc_cy~72_combout ; +wire \z80_|resets_|x3~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; +wire \z80_|interrupts_|nmi_armed~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; -wire \ula_|video_|Add0~15 ; -wire \ula_|video_|Add0~16_combout ; -wire \ula_|video_|vga_hc~2_combout ; -wire \ula_|video_|Add0~17 ; -wire \ula_|video_|Add0~18_combout ; -wire \ula_|video_|vga_hc~1_combout ; wire \ula_|video_|Add0~0_combout ; wire \ula_|video_|vga_hc~3_combout ; wire \ula_|video_|Add0~1 ; @@ -952,12 +279,8 @@ wire \ula_|video_|Add0~3 ; wire \ula_|video_|Add0~4_combout ; wire \ula_|video_|Add0~5 ; wire \ula_|video_|Add0~6_combout ; -wire \ula_|video_|vga_hc[3]~feeder_combout ; wire \ula_|video_|Add0~7 ; wire \ula_|video_|Add0~8_combout ; -wire \ula_|video_|Equal0~0_combout ; -wire \ula_|video_|Equal0~1_combout ; -wire \ula_|video_|Equal1~0_combout ; wire \ula_|video_|Add0~9 ; wire \ula_|video_|Add0~10_combout ; wire \ula_|video_|vga_hc~0_combout ; @@ -965,7 +288,18 @@ wire \ula_|video_|Add0~11 ; wire \ula_|video_|Add0~12_combout ; wire \ula_|video_|Add0~13 ; wire \ula_|video_|Add0~14_combout ; -wire \ula_|video_|Add1~0_combout ; +wire \ula_|video_|Equal0~0_combout ; +wire \ula_|video_|Equal0~1_combout ; +wire \ula_|video_|Add0~15 ; +wire \ula_|video_|Add0~16_combout ; +wire \ula_|video_|vga_hc~2_combout ; +wire \ula_|video_|Add0~17 ; +wire \ula_|video_|Add0~18_combout ; +wire \ula_|video_|vga_hc~1_combout ; +wire \ula_|video_|Equal1~0_combout ; +wire \ula_|video_|Add1~1 ; +wire \ula_|video_|Add1~2_combout ; +wire \ula_|video_|vga_vc[1]~1_combout ; wire \ula_|video_|Add1~3 ; wire \ula_|video_|Add1~4_combout ; wire \ula_|video_|vga_vc[2]~2_combout ; @@ -990,809 +324,1661 @@ wire \ula_|video_|vga_vc[8]~7_combout ; wire \ula_|video_|Add1~17 ; wire \ula_|video_|Add1~18_combout ; wire \ula_|video_|vga_vc[9]~9_combout ; -wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Equal3~0_combout ; +wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Equal3~1_combout ; +wire \ula_|video_|Add1~0_combout ; wire \ula_|video_|vga_vc[0]~0_combout ; -wire \ula_|video_|Add1~1 ; -wire \ula_|video_|Add1~2_combout ; -wire \ula_|video_|vga_vc[1]~1_combout ; -wire \SW[1]~input_o ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; -wire \z80_|pla_decode_|Equal79~0_combout ; -wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \z80_|interrupts_|DFFE_instIFF2~q ; -wire \z80_|interrupts_|iff1~0_combout ; -wire \z80_|interrupts_|iff1~1_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|interrupts_|iff1~q ; wire \ula_|video_|Equal2~1_combout ; wire \ula_|video_|Equal2~2_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ; -wire \z80_|interrupts_|int_armed~q ; -wire \z80_|interrupts_|DFFE_inst44~q ; -wire \z80_|execute_|pc_inc_hold~38_combout ; -wire \z80_|execute_|ctl_inc_cy~91_combout ; -wire \z80_|execute_|pc_inc_hold~45_combout ; -wire \z80_|execute_|pc_inc_hold~44_combout ; -wire \z80_|execute_|pc_inc_hold~46_combout ; -wire \z80_|execute_|pc_inc_hold~37_combout ; -wire \z80_|execute_|pc_inc_hold~50_combout ; -wire \z80_|execute_|pc_inc_hold~33_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; -wire \z80_|execute_|pc_inc_hold~31_combout ; -wire \z80_|execute_|pc_inc_hold~32_combout ; -wire \z80_|execute_|pc_inc_hold~34_combout ; -wire \z80_|execute_|pc_inc_hold~51_combout ; -wire \z80_|execute_|pc_inc_hold~30_combout ; -wire \z80_|execute_|pc_inc_hold~52_combout ; -wire \z80_|execute_|pc_inc_hold~35_combout ; -wire \z80_|execute_|pc_inc_hold~36_combout ; -wire \z80_|execute_|ctl_inc_cy~44_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; -wire \z80_|execute_|ctl_inc_cy~45_combout ; -wire \z80_|execute_|pc_inc_hold~43_combout ; -wire \z80_|execute_|ctl_inc_cy~71_combout ; -wire \z80_|execute_|ctl_inc_cy~73_combout ; +wire \SW[1]~input_o ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; +wire \z80_|execute_|ctl_mWrite~4_combout ; +wire \z80_|pla_decode_|Equal0~0_combout ; +wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M3_ff~q ; +wire \z80_|execute_|ixy_d~6_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ; +wire \z80_|pla_decode_|Equal33~0_combout ; +wire \z80_|execute_|ctl_mRead~5_combout ; +wire \z80_|pla_decode_|Equal77~0_combout ; +wire \z80_|pla_decode_|Equal50~0_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ; +wire \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ; +wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; +wire \z80_|clk_delay_|DFF_inst5~q ; +wire \z80_|clk_delay_|hold_clk_iorq~combout ; +wire \z80_|sequencer_|DFFE_T5_ff~q ; +wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; +wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; +wire \z80_|decode_state_|DFFE_inst4~q ; +wire \z80_|execute_|fMWrite~3_combout ; +wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M4_ff~q ; +wire \z80_|execute_|fMWrite~2_combout ; +wire \z80_|pla_decode_|Equal13~1_combout ; +wire \z80_|pla_decode_|Equal13~2_combout ; +wire \z80_|execute_|ixy_d~4_combout ; +wire \z80_|execute_|fIOWrite~1_combout ; +wire \z80_|execute_|ctl_mWrite~5_combout ; +wire \z80_|execute_|fMRead~2_combout ; +wire \z80_|execute_|ctl_state_alu~2_combout ; +wire \z80_|execute_|ctl_iorw~11_combout ; +wire \z80_|execute_|fIOWrite~2_combout ; +wire \z80_|pla_decode_|Equal2~0_combout ; +wire \z80_|decode_state_|table_xx~0_combout ; +wire \z80_|pla_decode_|Equal1~7_combout ; +wire \z80_|pla_decode_|Equal21~0_combout ; +wire \z80_|execute_|ctl_mRead~3_combout ; +wire \z80_|execute_|fIOWrite~3_combout ; +wire \z80_|execute_|ixy_d~5_combout ; +wire \z80_|execute_|fIOWrite~4_combout ; +wire \z80_|execute_|fIOWrite~5_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; +wire \z80_|execute_|ctl_state_alu~3_combout ; +wire \z80_|pla_decode_|Equal3~1_combout ; +wire \z80_|execute_|ctl_mWrite~6_combout ; +wire \z80_|execute_|ctl_ir_we~4_combout ; +wire \z80_|pla_decode_|Equal9~0_combout ; +wire \z80_|pla_decode_|Equal9~1_combout ; +wire \z80_|execute_|ctl_sw_2u~0_combout ; +wire \z80_|pla_decode_|Equal11~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~14_combout ; wire \z80_|execute_|ctl_inc_cy~46_combout ; -wire \z80_|execute_|pc_inc_hold~53_combout ; -wire \z80_|execute_|pc_inc_hold~39_combout ; -wire \z80_|execute_|pc_inc_hold~47_combout ; -wire \z80_|execute_|ctl_inc_cy~74_combout ; -wire \z80_|execute_|ctl_inc_cy~78_combout ; -wire \z80_|execute_|ctl_inc_cy~79_combout ; -wire \z80_|execute_|ctl_inc_cy~80_combout ; -wire \z80_|execute_|ctl_inc_cy~81_combout ; -wire \z80_|execute_|ctl_inc_cy~82_combout ; -wire \z80_|execute_|ctl_inc_cy~83_combout ; -wire \z80_|execute_|ctl_inc_cy~84_combout ; -wire \z80_|execute_|pc_inc_hold~42_combout ; -wire \z80_|execute_|ctl_inc_cy~90_combout ; -wire \z80_|execute_|pc_inc_hold~41_combout ; -wire \z80_|execute_|ctl_inc_cy~66_combout ; -wire \z80_|execute_|ctl_inc_cy~67_combout ; -wire \z80_|execute_|ctl_inc_cy~68_combout ; -wire \z80_|execute_|ctl_inc_cy~64_combout ; -wire \z80_|execute_|ctl_inc_cy~63_combout ; -wire \z80_|execute_|ctl_inc_cy~65_combout ; -wire \z80_|execute_|ctl_inc_cy~69_combout ; -wire \z80_|execute_|ctl_inc_cy~49_combout ; -wire \z80_|execute_|ctl_inc_cy~50_combout ; -wire \z80_|execute_|ctl_inc_cy~51_combout ; -wire \z80_|execute_|ctl_inc_cy~52_combout ; -wire \z80_|execute_|ctl_inc_cy~36_combout ; -wire \z80_|execute_|ctl_inc_cy~37_combout ; -wire \z80_|execute_|ctl_inc_cy~54_combout ; -wire \z80_|execute_|ctl_inc_cy~41_combout ; -wire \z80_|execute_|ctl_inc_cy~58_combout ; -wire \z80_|execute_|ctl_inc_cy~55_combout ; -wire \z80_|execute_|ctl_inc_cy~56_combout ; -wire \z80_|execute_|ctl_inc_cy~89_combout ; -wire \z80_|execute_|ctl_inc_cy~57_combout ; -wire \z80_|execute_|ctl_inc_cy~59_combout ; -wire \z80_|execute_|ctl_inc_cy~60_combout ; wire \z80_|execute_|ctl_inc_cy~47_combout ; -wire \z80_|execute_|ctl_inc_cy~88_combout ; +wire \z80_|pla_decode_|Equal19~0_combout ; +wire \z80_|pla_decode_|Equal34~0_combout ; +wire \z80_|execute_|comb~0_combout ; +wire \z80_|pla_decode_|Equal47~0_combout ; +wire \z80_|execute_|ctl_inc_cy~45_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; +wire \z80_|sequencer_|M5~0_combout ; +wire \z80_|sequencer_|M5~q ; +wire \z80_|execute_|ctl_alu_oe~2_combout ; +wire \z80_|execute_|ixy_d~7_combout ; +wire \z80_|execute_|ctl_inc_cy~44_combout ; +wire \z80_|execute_|ctl_apin_mux~0_combout ; +wire \z80_|execute_|ctl_mRead~4_combout ; +wire \z80_|execute_|ctl_ir_we~5_combout ; +wire \z80_|execute_|ctl_ir_we~15_combout ; +wire \z80_|execute_|ctl_ir_we~14_combout ; +wire \z80_|execute_|ctl_ir_we~7_combout ; +wire \z80_|execute_|fMWrite~0_combout ; +wire \z80_|execute_|ctl_inc_cy~97_combout ; +wire \z80_|execute_|ctl_inc_cy~96_combout ; +wire \z80_|execute_|ctl_inc_cy~98_combout ; wire \z80_|execute_|ctl_inc_cy~48_combout ; -wire \z80_|execute_|pc_inc_hold~40_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; +wire \z80_|execute_|fMWrite~1_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; +wire \z80_|execute_|ctl_mRead~6_combout ; +wire \z80_|execute_|ctl_reg_in_hi~2_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; +wire \z80_|execute_|ctl_mWrite~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; +wire \z80_|execute_|ctl_mWrite~17_combout ; +wire \z80_|execute_|fMWrite~4_combout ; +wire \z80_|execute_|ctl_state_alu~4_combout ; +wire \z80_|execute_|ctl_inc_cy~49_combout ; +wire \z80_|execute_|ctl_inc_dec~2_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; +wire \z80_|execute_|fMWrite~8_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~51_combout ; +wire \z80_|execute_|ctl_ir_we~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~10_combout ; +wire \z80_|pla_decode_|Equal46~0_combout ; +wire \z80_|execute_|ctl_ir_we~10_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; +wire \z80_|execute_|ctl_ir_we~6_combout ; +wire \z80_|execute_|ctl_ir_we~8_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; +wire \z80_|pla_decode_|Equal55~0_combout ; +wire \z80_|execute_|ctl_mRead~7_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; +wire \z80_|pin_control_|bus_db_pin_oe~17_combout ; +wire \z80_|execute_|fIOWrite~0_combout ; +wire \z80_|execute_|fMWrite~6_combout ; +wire \z80_|execute_|ctl_mWrite~8_combout ; +wire \z80_|execute_|fMWrite~5_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; +wire \z80_|execute_|fMRead~3_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; +wire \z80_|execute_|ctl_sw_4u~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ; +wire \z80_|execute_|fMWrite~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~15_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~16_combout ; +wire \z80_|execute_|ctl_mRead~9_combout ; +wire \z80_|pla_decode_|Equal24~0_combout ; +wire \z80_|execute_|nextM~4_combout ; +wire \z80_|pla_decode_|Equal3~0_combout ; +wire \z80_|execute_|ctl_eval_cond~0_combout ; +wire \z80_|execute_|ctl_iorw~12_combout ; +wire \z80_|execute_|ctl_iorw~8_combout ; +wire \z80_|execute_|ctl_iorw~9_combout ; +wire \z80_|memory_ifc_|DFFE_iorq_ff1~q ; +wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ; +wire \z80_|memory_ifc_|wait_iorq~feeder_combout ; +wire \z80_|memory_ifc_|wait_iorq~q ; +wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; +wire \z80_|memory_ifc_|iorq~0_combout ; +wire \z80_|pla_decode_|Equal33~2_combout ; +wire \z80_|execute_|ixy_d~17_combout ; +wire \z80_|execute_|ctl_mWrite~15_combout ; +wire \z80_|execute_|ctl_mWrite~18_combout ; +wire \z80_|execute_|ctl_mWrite~12_combout ; +wire \z80_|execute_|ctl_flags_alu~21_combout ; +wire \z80_|execute_|ctl_flags_alu~20_combout ; +wire \z80_|execute_|ctl_reg_in_hi~3_combout ; +wire \z80_|execute_|ctl_flags_alu~10_combout ; +wire \z80_|execute_|ctl_mWrite~10_combout ; +wire \z80_|execute_|ctl_mWrite~13_combout ; +wire \z80_|execute_|ixy_d~9_combout ; +wire \z80_|execute_|ctl_inc_cy~51_combout ; +wire \z80_|execute_|ctl_inc_dec~12_combout ; +wire \z80_|execute_|ctl_inc_dec~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; +wire \z80_|execute_|ctl_mWrite~11_combout ; +wire \z80_|execute_|ctl_mRead~25_combout ; +wire \z80_|execute_|ctl_flags_alu~22_combout ; +wire \z80_|execute_|ctl_mRead~24_combout ; +wire \z80_|execute_|ctl_bus_db_oe~7_combout ; +wire \z80_|execute_|ctl_mWrite~14_combout ; +wire \z80_|execute_|ixy_d~8_combout ; +wire \z80_|execute_|ctl_mWrite~16_combout ; +wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; +wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; +wire \z80_|memory_ifc_|wait_mwr~q ; +wire \z80_|memory_ifc_|mwr_wr~feeder_combout ; +wire \z80_|memory_ifc_|mwr_wr~q ; +wire \z80_|memory_ifc_|nWR_out~0_combout ; +wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; +wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; +wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; +wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; +wire \z80_|memory_ifc_|nRD_out~0_combout ; +wire \z80_|execute_|ctl_mRead~2_combout ; +wire \z80_|execute_|fIORead~0_combout ; +wire \z80_|execute_|ctl_iorw~10_combout ; +wire \z80_|pla_decode_|Equal1~4_combout ; +wire \z80_|execute_|ctl_alu_op_low~15_combout ; +wire \z80_|execute_|fIORead~1_combout ; +wire \z80_|execute_|fIORead~2_combout ; +wire \z80_|execute_|fIORead~3_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; +wire \z80_|execute_|ctl_im_we~combout ; +wire \z80_|interrupts_|im2~q ; +wire \z80_|execute_|ctl_mRead~10_combout ; +wire \z80_|pla_decode_|Equal33~3_combout ; +wire \z80_|pla_decode_|Equal6~1_combout ; +wire \z80_|execute_|ctl_mRead~30_combout ; +wire \z80_|execute_|ctl_mRead~31_combout ; +wire \z80_|execute_|ctl_ir_we~12_combout ; +wire \z80_|execute_|ctl_flags_bus~5_combout ; +wire \z80_|pla_decode_|Equal44~0_combout ; +wire \z80_|execute_|ctl_state_alu~6_combout ; +wire \z80_|execute_|fMRead~5_combout ; +wire \z80_|execute_|ctl_mRead~17_combout ; +wire \z80_|execute_|ctl_mRead~12_combout ; +wire \z80_|pla_decode_|Equal49~0_combout ; +wire \z80_|execute_|setM1~57_combout ; +wire \z80_|execute_|ctl_mRead~15_combout ; +wire \z80_|pla_decode_|Equal25~0_combout ; +wire \z80_|pla_decode_|Equal12~1_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; +wire \z80_|execute_|ixy_d~10_combout ; +wire \z80_|execute_|ixy_d~16_combout ; +wire \z80_|execute_|ctl_al_we~4_combout ; +wire \z80_|execute_|fMRead~4_combout ; +wire \z80_|pla_decode_|Equal29~0_combout ; +wire \z80_|execute_|setM1~38_combout ; +wire \z80_|pla_decode_|Equal35~0_combout ; +wire \z80_|execute_|pc_inc_hold~33_combout ; +wire \z80_|execute_|comb~1_combout ; +wire \z80_|execute_|ctl_mRead~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; +wire \z80_|pla_decode_|Equal40~2_combout ; +wire \z80_|execute_|setM1~36_combout ; +wire \z80_|execute_|pc_inc_hold~14_combout ; +wire \z80_|execute_|setM1~37_combout ; +wire \z80_|execute_|ctl_mRead~14_combout ; +wire \z80_|execute_|setM1~39_combout ; +wire \z80_|execute_|ctl_mRead~32_combout ; +wire \z80_|pla_decode_|Equal40~0_combout ; +wire \z80_|pla_decode_|Equal21~2_combout ; +wire \z80_|pla_decode_|Equal37~0_combout ; +wire \z80_|execute_|ctl_mRead~26_combout ; +wire \z80_|pla_decode_|Equal12~0_combout ; +wire \z80_|execute_|ctl_mRead~16_combout ; +wire \z80_|execute_|ctl_reg_in_hi~5_combout ; +wire \z80_|execute_|ctl_mRead~19_combout ; +wire \z80_|pla_decode_|Equal24~1_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~0_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~1_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; +wire \z80_|execute_|ctl_mRead~18_combout ; +wire \z80_|execute_|ctl_mRead~20_combout ; +wire \z80_|execute_|ctl_mRead~22_combout ; +wire \z80_|pla_decode_|Equal52~1_combout ; +wire \z80_|execute_|ctl_mRead~23_combout ; +wire \z80_|execute_|ctl_mRead~27_combout ; +wire \z80_|execute_|ctl_mRead~28_combout ; +wire \z80_|execute_|nextM~3_combout ; +wire \z80_|execute_|ctl_mRead~29_combout ; +wire \z80_|execute_|ctl_mRead~33_combout ; +wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; +wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; +wire \z80_|memory_ifc_|wait_mrd~q ; +wire \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ; +wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; +wire \z80_|memory_ifc_|nRD_out~1_combout ; +wire \z80_|memory_ifc_|nRD_out~2_combout ; +wire \Equal2~1_combout ; +wire \PS2_DAT~input_o ; +wire \reset~clkctrl_outclk ; +wire \ula_|ps2_keyboard_|bit_count~2_combout ; +wire \PS2_CLK~input_o ; +wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~0_combout ; +wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~1_combout ; +wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~q ; +wire \ula_|ps2_keyboard_|clk_edge~0_combout ; +wire \ula_|ps2_keyboard_|clk_edge~q ; +wire \ula_|ps2_keyboard_|bit_count~3_combout ; +wire \ula_|ps2_keyboard_|bit_count~1_combout ; +wire \ula_|ps2_keyboard_|bit_count~0_combout ; +wire \ula_|ps2_keyboard_|LessThan0~0_combout ; +wire \ula_|ps2_keyboard_|always1~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; +wire \ula_|zx_keyboard_|Equal0~0_combout ; +wire \ula_|zx_keyboard_|Equal0~1_combout ; +wire \ula_|ps2_keyboard_|WideXor0~1_combout ; +wire \ula_|ps2_keyboard_|WideXor0~0_combout ; +wire \ula_|ps2_keyboard_|WideXor0~2_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~q ; +wire \ula_|zx_keyboard_|released~0_combout ; +wire \ula_|zx_keyboard_|released~q ; +wire \ula_|zx_keyboard_|Equal0~2_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~50_combout ; +wire \ula_|zx_keyboard_|extended~0_combout ; +wire \ula_|zx_keyboard_|extended~q ; +wire \ula_|zx_keyboard_|keys[7][4]~15_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~52_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~53_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~q ; +wire \z80_|resets_|clrpc_int~0_combout ; +wire \z80_|resets_|clrpc_int~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; +wire \z80_|resets_|DFFE_intr_ff3~q ; +wire \z80_|resets_|clrpc~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; +wire \z80_|pla_decode_|Equal21~1_combout ; +wire \z80_|pla_decode_|Equal40~1_combout ; +wire \z80_|pla_decode_|Equal39~0_combout ; +wire \z80_|execute_|ctl_bus_db_oe~1_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; +wire \z80_|execute_|ctl_inc_dec~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; +wire \z80_|execute_|ctl_al_we~5_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; +wire \z80_|execute_|ctl_al_we~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; +wire \z80_|pla_decode_|Equal10~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~6_combout ; +wire \z80_|execute_|ctl_bus_db_oe~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ; +wire \z80_|reg_control_|reg_sel_pc~1_combout ; +wire \z80_|reg_control_|reg_sel_pc~0_combout ; +wire \z80_|reg_control_|reg_sel_pc~2_combout ; +wire \z80_|pla_decode_|Equal56~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~18_combout ; +wire \z80_|execute_|ctl_alu_op_low~17_combout ; +wire \z80_|execute_|ctl_alu_oe~4_combout ; +wire \z80_|execute_|ctl_reg_in_hi~4_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; +wire \z80_|execute_|ctl_inc_dec~3_combout ; +wire \z80_|execute_|fMRead~6_combout ; +wire \z80_|nM1_int~2_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_inc_cy~94_combout ; +wire \z80_|execute_|ctl_inc_cy~50_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; +wire \z80_|execute_|ctl_inc_cy~99_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; +wire \z80_|execute_|ctl_reg_out_hi~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_in_lo~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; +wire \z80_|pla_decode_|Equal1~5_combout ; +wire \z80_|execute_|ctl_alu_op_low~20_combout ; +wire \z80_|pla_decode_|Equal48~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; +wire \z80_|execute_|ctl_flags_bus~4_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; +wire \z80_|execute_|fMRead~7_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; +wire \z80_|execute_|ctl_reg_sys_we~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we~1_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; +wire \z80_|execute_|ctl_reg_sys_we~2_combout ; +wire \z80_|pla_decode_|Equal8~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~1_combout ; +wire \z80_|alu_control_|sel[1]~0_combout ; +wire \z80_|execute_|ctl_state_alu~7_combout ; +wire \z80_|execute_|ctl_state_alu~11_combout ; +wire \z80_|execute_|ctl_state_alu~9_combout ; +wire \z80_|execute_|ctl_state_alu~5_combout ; +wire \z80_|execute_|ctl_state_alu~10_combout ; +wire \z80_|execute_|ctl_state_alu~8_combout ; +wire \z80_|pla_decode_|Equal62~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~5_combout ; +wire \z80_|execute_|ctl_ir_we~11_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~7_combout ; +wire \z80_|execute_|ctl_bus_db_oe~3_combout ; +wire \z80_|execute_|ctl_flags_xy_we~19_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; +wire \z80_|execute_|ctl_alu_op_low~19_combout ; +wire \z80_|execute_|ctl_flags_bus~15_combout ; +wire \z80_|execute_|ctl_flags_bus~9_combout ; +wire \z80_|pla_decode_|Equal20~0_combout ; +wire \z80_|pla_decode_|Equal68~2_combout ; +wire \z80_|execute_|ctl_flags_bus~14_combout ; +wire \z80_|pla_decode_|Equal63~0_combout ; +wire \z80_|pla_decode_|Equal76~2_combout ; +wire \z80_|execute_|ctl_flags_bus~8_combout ; +wire \z80_|execute_|ctl_flags_bus~6_combout ; +wire \z80_|execute_|ctl_flags_bus~7_combout ; +wire \z80_|execute_|ctl_flags_bus~10_combout ; +wire \z80_|execute_|ctl_flags_xy_we~11_combout ; +wire \z80_|execute_|ctl_flags_hf2_we~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; +wire \z80_|execute_|ctl_reg_gp_sel~7_combout ; +wire \z80_|execute_|ctl_state_alu~12_combout ; +wire \z80_|pla_decode_|Equal62~3_combout ; +wire \z80_|execute_|ctl_flags_pf_we~6_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; +wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; +wire \z80_|execute_|ctl_flags_cf_we~7_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~10_combout ; +wire \z80_|execute_|ctl_flags_hf_we~5_combout ; +wire \z80_|execute_|ctl_flags_pf_we~11_combout ; +wire \z80_|execute_|ctl_flags_pf_we~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~3_combout ; +wire \z80_|pla_decode_|Equal10~1_combout ; +wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; +wire \z80_|pla_decode_|Equal69~0_combout ; +wire \z80_|execute_|ctl_flags_pf_we~7_combout ; +wire \z80_|execute_|ctl_flags_pf_we~8_combout ; +wire \z80_|execute_|ctl_flags_pf_we~9_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~13_combout ; +wire \z80_|execute_|ctl_flags_pf_we~10_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; +wire \z80_|execute_|ctl_flags_xy_we~18_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~21_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~20_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ; +wire \z80_|execute_|ctl_reg_out_lo~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; +wire \z80_|execute_|ctl_al_we~14_combout ; +wire \z80_|execute_|ctl_sw_4d~1_combout ; +wire \z80_|execute_|ctl_alu_oe~5_combout ; +wire \z80_|execute_|setM1~47_combout ; +wire \z80_|execute_|ctl_sw_4d~0_combout ; +wire \z80_|execute_|ctl_sw_4d~4_combout ; +wire \z80_|execute_|fMRead~8_combout ; +wire \z80_|execute_|fMRead~9_combout ; +wire \z80_|execute_|fMRead~10_combout ; +wire \z80_|execute_|ctl_sw_4d~2_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; +wire \z80_|pla_decode_|Equal4~0_combout ; +wire \z80_|execute_|setM1~41_combout ; +wire \z80_|pla_decode_|Equal2~1_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_sw_1d~4_combout ; +wire \z80_|execute_|ctl_sw_4d~3_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; +wire \z80_|execute_|ctl_sw_4d~5_combout ; +wire \z80_|execute_|ctl_sw_4d~6_combout ; +wire \z80_|reg_control_|reg_sel_pc~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; +wire \z80_|execute_|ctl_sw_4u~1_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; +wire \z80_|reg_control_|reg_sel_pc~3_combout ; +wire \z80_|reg_control_|reg_sel_pc~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; +wire \z80_|pla_decode_|Equal1~6_combout ; +wire \z80_|reg_control_|bank_exx~2_combout ; +wire \z80_|reg_control_|bank_exx~q ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_sw_2u~1_combout ; +wire \z80_|execute_|ctl_alu_oe~3_combout ; +wire \z80_|execute_|ctl_sw_2u~4_combout ; +wire \z80_|execute_|setM1~56_combout ; +wire \z80_|execute_|ctl_sw_2u~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; +wire \z80_|execute_|ctl_state_alu~13_combout ; +wire \z80_|execute_|ctl_flags_xy_we~12_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; wire \z80_|execute_|ctl_inc_cy~61_combout ; -wire \z80_|execute_|ctl_inc_cy~62_combout ; -wire \z80_|execute_|ctl_inc_cy~70_combout ; -wire \z80_|execute_|ctl_inc_cy~85_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[0]~3_combout ; -wire \z80_|address_latch_|Q[0]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; -wire \z80_|reg_file_|db_lo_as[1]~4_combout ; -wire \z80_|reg_file_|db_lo_as[1]~5_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; -wire \z80_|reg_file_|db_lo_as[1]~6_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[2]~9_combout ; -wire \z80_|address_latch_|Q[2]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; wire \z80_|execute_|ctl_inc_cy~86_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|execute_|ctl_inc_dec~11_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; -wire \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; -wire \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ; +wire \z80_|execute_|ctl_inc_cy~87_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~52_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~49_combout ; +wire \z80_|execute_|ctl_reg_gp_we~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; +wire \z80_|execute_|ctl_alu_oe~7_combout ; +wire \z80_|execute_|ctl_alu_oe~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_flags_oe~0_combout ; +wire \z80_|execute_|ctl_flags_oe~1_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~8_combout ; +wire \z80_|execute_|setM1~48_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; +wire \z80_|execute_|nextM~2_combout ; +wire \z80_|execute_|setM1~49_combout ; +wire \z80_|execute_|ctl_reg_in_hi~12_combout ; +wire \z80_|execute_|ctl_sw_1d~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; +wire \z80_|execute_|ctl_sw_2u~2_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; +wire \z80_|execute_|nextM~11_combout ; +wire \z80_|execute_|ctl_reg_use_sp~0_combout ; +wire \z80_|execute_|ctl_reg_use_sp~2_combout ; +wire \z80_|execute_|ctl_reg_use_sp~3_combout ; +wire \z80_|execute_|ctl_sw_1d~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~13_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; +wire \z80_|execute_|setM1~30_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~14_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~22_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; +wire \z80_|reg_control_|reg_sel_de2~2_combout ; +wire \z80_|reg_control_|reg_sel_de2~4_combout ; +wire \z80_|pla_decode_|Equal2~2_combout ; +wire \z80_|reg_control_|bank_hl_de1~0_combout ; +wire \z80_|reg_control_|bank_hl_de1~q ; +wire \z80_|reg_control_|reg_sel_hl~0_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~50_combout ; +wire \z80_|execute_|ctl_reg_gp_we~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ; +wire \z80_|execute_|rsel3~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; +wire \z80_|execute_|rsel0~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; +wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; +wire \z80_|execute_|ctl_reg_in_hi~7_combout ; +wire \z80_|execute_|ctl_reg_gp_we~6_combout ; +wire \z80_|execute_|ctl_reg_gp_we~9_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; +wire \z80_|execute_|ctl_reg_gp_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; +wire \z80_|execute_|ctl_reg_gp_we~5_combout ; +wire \z80_|execute_|ctl_reg_gp_we~7_combout ; +wire \z80_|execute_|ctl_sw_4u~2_combout ; +wire \z80_|execute_|ctl_sw_4u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_we~8_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; +wire \z80_|reg_control_|bank_hl_de2~0_combout ; +wire \z80_|reg_control_|bank_hl_de2~q ; +wire \z80_|reg_control_|reg_sel_hl2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; +wire \z80_|execute_|ctl_flags_sz_we~1_combout ; +wire \z80_|execute_|ctl_reg_in_hi~8_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ; +wire \z80_|execute_|ctl_reg_in_hi~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; +wire \z80_|execute_|ctl_reg_in_lo~8_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; +wire \z80_|execute_|ctl_sw_2d~6_combout ; +wire \z80_|execute_|ctl_sw_2d~7_combout ; +wire \z80_|execute_|ctl_sw_2d~8_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; +wire \z80_|execute_|ctl_sw_2d~4_combout ; +wire \z80_|execute_|fMRead~18_combout ; +wire \z80_|execute_|fMRead~19_combout ; +wire \z80_|execute_|fMRead~20_combout ; +wire \z80_|execute_|ctl_reg_in_hi~6_combout ; +wire \z80_|execute_|fMRead~21_combout ; +wire \z80_|execute_|ctl_sw_2d~5_combout ; +wire \z80_|execute_|ctl_sw_2d~9_combout ; +wire \z80_|execute_|ctl_sw_1d~5_combout ; +wire \z80_|execute_|ctl_sw_1d~6_combout ; +wire \z80_|execute_|ctl_sw_1d~7_combout ; +wire \z80_|execute_|ctl_alu_op_low~41_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op_low~26_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; +wire \z80_|execute_|ctl_alu_op_low~27_combout ; +wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; +wire \z80_|pla_decode_|Equal61~2_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; +wire \z80_|execute_|ctl_alu_core_hf~12_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; +wire \z80_|execute_|ctl_flags_sz_we~3_combout ; +wire \z80_|execute_|ctl_flags_alu~13_combout ; +wire \z80_|execute_|ctl_flags_alu~14_combout ; +wire \z80_|execute_|ctl_flags_alu~15_combout ; +wire \z80_|execute_|ctl_reg_use_sp~1_combout ; +wire \z80_|execute_|ctl_alu_op_low~16_combout ; +wire \z80_|execute_|ctl_flags_xy_we~17_combout ; +wire \z80_|execute_|ctl_flags_sz_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ; +wire \z80_|execute_|ctl_alu_op_low~39_combout ; +wire \z80_|execute_|ctl_flags_alu~16_combout ; +wire \z80_|execute_|ctl_flags_alu~17_combout ; +wire \z80_|execute_|ctl_alu_op_low~23_combout ; +wire \z80_|execute_|ctl_flags_alu~18_combout ; +wire \z80_|execute_|ctl_flags_alu~11_combout ; +wire \z80_|execute_|ctl_alu_core_R~0_combout ; +wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~1_combout ; +wire \z80_|execute_|ctl_flags_alu~23_combout ; +wire \z80_|execute_|ctl_flags_alu~12_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~11_combout ; +wire \z80_|execute_|ctl_alu_oe~6_combout ; +wire \z80_|execute_|setM1~17_combout ; +wire \z80_|execute_|ctl_alu_op_low~22_combout ; +wire \z80_|execute_|ctl_flags_xy_we~6_combout ; +wire \z80_|execute_|ctl_flags_xy_we~7_combout ; +wire \z80_|execute_|ctl_flags_sz_we~2_combout ; +wire \z80_|execute_|ctl_flags_alu~19_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; +wire \z80_|execute_|fMRead~26_combout ; +wire \z80_|execute_|ctl_flags_bus~11_combout ; +wire \z80_|execute_|ctl_flags_bus~12_combout ; +wire \z80_|execute_|ctl_flags_bus~13_combout ; +wire \z80_|execute_|ctl_flags_bus~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~12_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~18_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; +wire \z80_|execute_|ctl_alu_op_low~24_combout ; +wire \z80_|execute_|ctl_alu_op_low~25_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~17_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; +wire \z80_|execute_|ctl_flags_xy_we~10_combout ; +wire \z80_|execute_|ctl_flags_cf_we~2_combout ; +wire \z80_|execute_|ctl_alu_core_S~6_combout ; +wire \z80_|execute_|ctl_alu_core_S~7_combout ; +wire \z80_|execute_|ctl_alu_core_S~4_combout ; +wire \z80_|execute_|ctl_alu_core_S~5_combout ; +wire \z80_|execute_|ctl_alu_oe~15_combout ; +wire \z80_|execute_|ctl_alu_res_oe~0_combout ; +wire \z80_|execute_|ctl_alu_res_oe~1_combout ; +wire \z80_|execute_|ctl_alu_res_oe~2_combout ; +wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; +wire \z80_|alu_|db_high[3]~0_combout ; +wire \z80_|execute_|ctl_reg_out_hi~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ; +wire \z80_|execute_|ctl_sw_2u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; +wire \z80_|execute_|ctl_sw_2u~6_combout ; +wire \z80_|execute_|ctl_reg_out_lo~2_combout ; +wire \z80_|execute_|ctl_reg_out_hi~5_combout ; +wire \z80_|execute_|ctl_reg_out_hi~6_combout ; +wire \z80_|execute_|ctl_reg_out_hi~7_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~40_combout ; +wire \z80_|execute_|ctl_reg_use_sp~4_combout ; +wire \z80_|execute_|ctl_reg_use_sp~5_combout ; +wire \z80_|execute_|ctl_reg_use_sp~6_combout ; +wire \z80_|reg_control_|bank_af~0_combout ; +wire \z80_|reg_control_|bank_af~q ; +wire \z80_|reg_control_|reg_sel_af~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~41_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ; -wire \z80_|execute_|ctl_reg_in_hi~11_combout ; -wire \z80_|execute_|ctl_reg_in_hi~12_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~44_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~32_combout ; +wire \z80_|reg_control_|reg_sel_de2~3_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_control_|reg_sel_de~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~31_combout ; wire \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ; +wire \z80_|reg_control_|reg_sel_iy~2_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~43_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~34_combout ; +wire \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; +wire \z80_|execute_|ctl_sw_4u~4_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~45_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~36_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~42_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~46_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~47_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~33_combout ; +wire \z80_|reg_control_|reg_sel_af2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; +wire \z80_|execute_|ctl_reg_in_hi~10_combout ; +wire \z80_|execute_|ctl_reg_in_hi~11_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~35_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~37_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~38_combout ; +wire \z80_|execute_|ctl_sw_4u~5_combout ; +wire \z80_|execute_|ctl_sw_4u~6_combout ; wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; -wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; -wire \z80_|reg_file_|db_hi_as[1]~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; -wire \z80_|reg_file_|db_hi_as[1]~1_combout ; -wire \z80_|reg_file_|db_hi_as[0]~2_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; -wire \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; -wire \z80_|reg_file_|db_hi_as[0]~4_combout ; -wire \z80_|reg_file_|db_hi_as[0]~5_combout ; -wire \z80_|reg_file_|db_hi_as[0]~6_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[1]~3_combout ; -wire \z80_|address_latch_|Q[9]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~32_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~35_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~34_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~33_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~36_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~37_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~31_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~38_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~39_combout ; -wire \z80_|reg_file_|db_hi_as[2]~7_combout ; -wire \z80_|reg_file_|db_hi_as[2]~8_combout ; -wire \z80_|reg_file_|db_hi_as[2]~9_combout ; -wire \z80_|address_latch_|Q[10]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; -wire \z80_|reg_file_|db_hi_as[3]~10_combout ; -wire \z80_|reg_file_|db_hi_as[3]~11_combout ; -wire \z80_|reg_file_|db_hi_as[3]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~48_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; -wire \z80_|alu_|alu_op1[3]~3_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; -wire \z80_|execute_|ctl_alu_core_R~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~5_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~20_combout ; -wire \z80_|execute_|ctl_state_alu~12_combout ; -wire \z80_|execute_|ctl_alu_core_hf~18_combout ; -wire \z80_|pla_decode_|Equal61~2_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~21_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~20_combout ; -wire \z80_|execute_|ctl_flags_sz_we~4_combout ; -wire \z80_|pla_decode_|Equal71~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; -wire \z80_|execute_|ctl_alu_op_low~31_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ; -wire \z80_|pla_decode_|Equal72~2_combout ; -wire \z80_|pla_decode_|Equal73~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~0_combout ; -wire \z80_|execute_|ctl_flags_nf_we~1_combout ; -wire \z80_|execute_|ctl_flags_nf_we~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~3_combout ; -wire \z80_|execute_|ctl_flags_sz_we~5_combout ; -wire \z80_|execute_|ctl_flags_sz_we~6_combout ; -wire \z80_|execute_|ctl_flags_nf_we~4_combout ; -wire \z80_|execute_|setM1~15_combout ; -wire \z80_|execute_|setM1~16_combout ; -wire \z80_|execute_|ctl_flags_xy_we~6_combout ; -wire \z80_|execute_|ctl_flags_xy_we~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~2_combout ; -wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~1_combout ; -wire \z80_|execute_|ctl_flags_alu~7_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~8_combout ; -wire \z80_|execute_|ctl_flags_alu~8_combout ; -wire \z80_|execute_|ctl_flags_xy_we~16_combout ; -wire \z80_|execute_|ctl_flags_alu~12_combout ; -wire \z80_|execute_|ctl_flags_alu~13_combout ; -wire \z80_|execute_|ctl_flags_alu~14_combout ; -wire \z80_|execute_|ctl_flags_alu~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~19_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; -wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~18_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; -wire \z80_|alu_|alu_op2[1]~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|execute_|ctl_alu_core_S~9_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ; -wire \z80_|alu_|alu_op2[0]~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ; -wire \z80_|execute_|ctl_alu_core_S~8_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|execute_|ctl_alu_core_hf~21_combout ; -wire \z80_|execute_|ctl_alu_core_hf~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~19_combout ; -wire \z80_|execute_|ctl_alu_op_low~27_combout ; -wire \z80_|execute_|ctl_alu_op_low~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~23_combout ; -wire \z80_|execute_|ctl_alu_core_hf~37_combout ; -wire \z80_|execute_|ctl_alu_core_hf~38_combout ; -wire \z80_|execute_|ctl_alu_core_hf~24_combout ; -wire \z80_|execute_|ctl_alu_core_hf~25_combout ; -wire \z80_|execute_|ctl_alu_core_hf~26_combout ; -wire \z80_|execute_|ctl_alu_core_hf~27_combout ; -wire \z80_|execute_|ctl_alu_core_hf~28_combout ; -wire \z80_|execute_|ctl_alu_op_low~30_combout ; -wire \z80_|execute_|ctl_alu_core_hf~34_combout ; -wire \z80_|execute_|ctl_alu_core_hf~32_combout ; -wire \z80_|execute_|ctl_alu_core_hf~43_combout ; -wire \z80_|execute_|ctl_alu_core_hf~33_combout ; -wire \z80_|execute_|ctl_alu_core_hf~42_combout ; -wire \z80_|execute_|ctl_alu_core_hf~35_combout ; -wire \z80_|execute_|ctl_alu_core_hf~41_combout ; -wire \z80_|execute_|ctl_alu_core_hf~30_combout ; -wire \z80_|execute_|ctl_mWrite~10_combout ; -wire \z80_|execute_|ctl_alu_core_hf~31_combout ; -wire \z80_|execute_|ctl_alu_core_hf~44_combout ; -wire \z80_|execute_|ctl_alu_core_hf~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~36_combout ; -wire \z80_|execute_|ctl_alu_core_hf~39_combout ; -wire \z80_|execute_|ctl_alu_core_hf~40_combout ; -wire \z80_|execute_|ctl_flags_hf_we~2_combout ; -wire \z80_|execute_|ctl_alu_core_R~2_combout ; -wire \z80_|execute_|ctl_alu_core_R~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ; -wire \z80_|alu_|alu_op2[3]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; -wire \z80_|execute_|ctl_flags_hf_we~3_combout ; -wire \z80_|execute_|ctl_flags_hf_we~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; -wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~13_combout ; -wire \z80_|alu_flags_|flags_hf~combout ; -wire \z80_|alu_control_|alu_core_cf_in~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; -wire \z80_|alu_|db_high[0]~23_combout ; -wire \z80_|address_latch_|Q[12]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[4]~16_combout ; -wire \z80_|reg_file_|db_hi_as[4]~17_combout ; -wire \z80_|reg_file_|db_hi_as[4]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~62_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~63_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~61_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~64_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~58_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~65_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~66_combout ; -wire \z80_|alu_|db[4]~16_combout ; -wire \z80_|alu_|db[7]~26_combout ; -wire \z80_|alu_|db[4]~17_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; -wire \z80_|alu_|db_high[0]~24_combout ; -wire \z80_|alu_|db_high[0]~21_combout ; -wire \z80_|alu_|db_high[0]~22_combout ; -wire \z80_|alu_|db_high[0]~25_combout ; -wire \z80_|alu_|db_high[0]~26_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; -wire \z80_|alu_|alu_op1[0]~1_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; -wire \z80_|alu_|alu_op1[1]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; -wire \z80_|alu_|alu_op1[2]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~5_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~69_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~70_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~72_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~71_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~73_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~67_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~68_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~74_combout ; -wire \z80_|reg_file_|db_hi_as[7]~19_combout ; -wire \z80_|reg_file_|db_hi_as[7]~20_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~54_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~53_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~51_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~52_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~55_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~49_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~50_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~56_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~57_combout ; -wire \z80_|reg_file_|db_hi_as[5]~13_combout ; -wire \z80_|reg_file_|db_hi_as[5]~14_combout ; -wire \z80_|reg_file_|db_hi_as[5]~15_combout ; -wire \z80_|address_latch_|Q[13]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~76_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~80_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~79_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~78_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~81_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~82_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~77_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~83_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~84_combout ; -wire \z80_|reg_file_|db_hi_as[6]~22_combout ; -wire \z80_|reg_file_|db_hi_as[6]~23_combout ; -wire \z80_|reg_file_|db_hi_as[6]~24_combout ; -wire \z80_|address_latch_|Q[14]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|reg_file_|db_hi_as[7]~21_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~75_combout ; -wire \z80_|alu_|db[7]~20_combout ; -wire \z80_|alu_|db[7]~21_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; -wire \z80_|execute_|ctl_flags_cf_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf_we~5_combout ; -wire \z80_|execute_|ctl_flags_cf_we~3_combout ; -wire \z80_|execute_|ctl_flags_cf_we~6_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~2_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; -wire \z80_|alu_|db_high[3]~5_combout ; -wire \z80_|alu_|db_high[3]~6_combout ; -wire \z80_|alu_|db_high[3]~4_combout ; -wire \z80_|alu_|db_high[3]~27_combout ; -wire \z80_|alu_|db_high[3]~7_combout ; -wire \z80_|alu_|db_high[3]~8_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ; -wire \z80_|alu_|db_low[3]~9_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; -wire \z80_|alu_|db_low[3]~10_combout ; -wire \z80_|alu_|db_low[3]~7_combout ; -wire \z80_|alu_|db_low[3]~8_combout ; -wire \z80_|alu_|db_low[3]~11_combout ; -wire \z80_|alu_|db_low[3]~25_combout ; -wire \z80_|alu_|db[3]~10_combout ; -wire \z80_|alu_|db[3]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~39_combout ; +wire \z80_|alu_|db[3]~13_combout ; +wire \z80_|execute_|ctl_sw_2d~12_combout ; +wire \z80_|execute_|ctl_sw_2d~10_combout ; +wire \z80_|execute_|ctl_sw_2d~14_combout ; +wire \z80_|execute_|ctl_sw_2d~11_combout ; +wire \z80_|execute_|ctl_sw_2d~13_combout ; +wire \z80_|execute_|ctl_bus_db_we~5_combout ; +wire \z80_|execute_|ctl_alu_oe~9_combout ; +wire \z80_|execute_|ctl_alu_oe~10_combout ; wire \z80_|execute_|ctl_sw_2u~7_combout ; -wire \z80_|execute_|setM1~49_combout ; -wire \z80_|execute_|ctl_flags_oe~2_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|execute_|ctl_flags_sz_we~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ; wire \z80_|execute_|ctl_flags_xy_we~13_combout ; wire \z80_|execute_|ctl_flags_xy_we~14_combout ; wire \z80_|execute_|ctl_flags_xy_we~15_combout ; +wire \z80_|execute_|ctl_flags_sz_we~5_combout ; +wire \z80_|execute_|ctl_flags_sz_we~6_combout ; +wire \z80_|execute_|ctl_flags_sz_we~7_combout ; +wire \z80_|execute_|ctl_flags_xy_we~16_combout ; wire \z80_|alu_flags_|flags_xf~q ; -wire \z80_|alu_control_|db[3]~33_combout ; +wire \z80_|execute_|setM1~50_combout ; +wire \z80_|execute_|ctl_flags_oe~2_combout ; +wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; +wire \z80_|alu_control_|db[3]~34_combout ; +wire \z80_|sw1_|db_down[3]~3_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~42_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~91_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; +wire \z80_|reg_file_|db_lo_as[3]~10_combout ; +wire \z80_|reg_file_|db_lo_as[3]~11_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; +wire \z80_|execute_|ctl_inc_cy~88_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; +wire \z80_|execute_|ctl_inc_dec~6_combout ; +wire \z80_|reg_file_|db_lo_as[0]~2_combout ; +wire \z80_|execute_|pc_inc_hold~25_combout ; +wire \z80_|execute_|ctl_inc_cy~67_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~64_combout ; +wire \z80_|execute_|ctl_inc_cy~65_combout ; +wire \z80_|execute_|ctl_inc_cy~63_combout ; +wire \z80_|execute_|ctl_inc_cy~66_combout ; +wire \z80_|execute_|ctl_inc_cy~68_combout ; +wire \z80_|execute_|ctl_inc_cy~58_combout ; +wire \z80_|execute_|ctl_inc_cy~59_combout ; +wire \z80_|execute_|ctl_inc_cy~60_combout ; +wire \z80_|execute_|ctl_inc_cy~57_combout ; +wire \z80_|execute_|ctl_inc_cy~62_combout ; +wire \z80_|execute_|pc_inc_hold~18_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; +wire \z80_|execute_|pc_inc_hold~17_combout ; +wire \z80_|execute_|pc_inc_hold~19_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; +wire \z80_|execute_|pc_inc_hold~20_combout ; +wire \z80_|execute_|pc_inc_hold~36_combout ; +wire \z80_|execute_|pc_inc_hold~15_combout ; +wire \z80_|execute_|pc_inc_hold~16_combout ; +wire \z80_|execute_|pc_inc_hold~21_combout ; +wire \z80_|execute_|ctl_inc_cy~69_combout ; +wire \z80_|execute_|ctl_inc_cy~52_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; +wire \z80_|execute_|pc_inc_hold~34_combout ; +wire \z80_|execute_|pc_inc_hold~22_combout ; +wire \z80_|execute_|pc_inc_hold~23_combout ; +wire \z80_|execute_|pc_inc_hold~35_combout ; +wire \z80_|execute_|pc_inc_hold~24_combout ; +wire \z80_|execute_|ctl_inc_cy~53_combout ; +wire \z80_|execute_|ctl_inc_cy~54_combout ; +wire \z80_|execute_|ctl_inc_cy~74_combout ; +wire \z80_|execute_|ctl_inc_cy~75_combout ; +wire \z80_|execute_|ctl_inc_cy~73_combout ; +wire \z80_|execute_|ctl_inc_cy~76_combout ; +wire \z80_|execute_|ctl_inc_cy~95_combout ; +wire \z80_|execute_|ctl_inc_cy~72_combout ; +wire \z80_|execute_|pc_inc_hold~27_combout ; +wire \z80_|execute_|ctl_inc_cy~77_combout ; +wire \z80_|execute_|ctl_inc_cy~78_combout ; +wire \z80_|execute_|ctl_inc_cy~79_combout ; +wire \z80_|execute_|ctl_inc_cy~70_combout ; +wire \z80_|execute_|ctl_inc_cy~71_combout ; +wire \z80_|execute_|ctl_inc_cy~80_combout ; +wire \z80_|execute_|ctl_inc_cy~55_combout ; +wire \z80_|execute_|pc_inc_hold~26_combout ; +wire \z80_|execute_|ctl_inc_cy~56_combout ; +wire \z80_|execute_|ctl_inc_cy~81_combout ; +wire \z80_|execute_|ctl_inc_cy~85_combout ; +wire \z80_|execute_|ctl_inc_cy~89_combout ; +wire \z80_|execute_|ctl_inc_cy~90_combout ; +wire \z80_|execute_|ctl_inc_cy~91_combout ; +wire \z80_|execute_|ctl_inc_cy~83_combout ; +wire \z80_|execute_|ctl_inc_cy~84_combout ; +wire \z80_|execute_|ctl_inc_cy~100_combout ; +wire \z80_|execute_|ctl_inc_cy~92_combout ; +wire \z80_|execute_|pc_inc_hold~28_combout ; +wire \z80_|execute_|ctl_inc_cy~82_combout ; +wire \z80_|execute_|pc_inc_hold~29_combout ; +wire \z80_|execute_|pc_inc_hold~30_combout ; +wire \z80_|execute_|pc_inc_hold~31_combout ; +wire \z80_|execute_|pc_inc_hold~32_combout ; +wire \z80_|execute_|ctl_inc_cy~93_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; +wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; +wire \z80_|alu_control_|db[0]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; +wire \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ; +wire \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; +wire \z80_|execute_|ctl_inc_dec~8_combout ; +wire \z80_|execute_|ctl_inc_dec~9_combout ; +wire \z80_|execute_|ctl_inc_dec~10_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|execute_|ctl_inc_dec~7_combout ; +wire \z80_|execute_|ctl_inc_dec~11_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; +wire \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; +wire \z80_|alu_|db_low[2]~9_combout ; +wire \z80_|alu_|db_low[2]~10_combout ; +wire \z80_|alu_|db_high[3]~1_combout ; +wire \z80_|execute_|ctl_flags_pf_we~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ; +wire \z80_|execute_|ctl_alu_op_low~38_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ; +wire \z80_|execute_|ctl_alu_core_S~8_combout ; +wire \z80_|execute_|ctl_alu_core_R~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~3_combout ; +wire \z80_|execute_|ctl_alu_core_R~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; +wire \z80_|execute_|ctl_alu_core_S~11_combout ; +wire \z80_|execute_|ctl_alu_core_S~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~combout ; +wire \z80_|pla_decode_|Equal73~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~5_combout ; +wire \z80_|execute_|ctl_alu_core_R~combout ; +wire \z80_|execute_|ctl_alu_op_low~28_combout ; +wire \z80_|execute_|ctl_alu_op_low~29_combout ; +wire \z80_|execute_|ctl_alu_op_low~30_combout ; +wire \z80_|execute_|ctl_alu_op_low~31_combout ; +wire \z80_|execute_|ctl_alu_op_low~32_combout ; +wire \z80_|execute_|ctl_alu_op_low~40_combout ; +wire \z80_|execute_|ctl_alu_op_low~33_combout ; +wire \z80_|execute_|ctl_alu_op_low~combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~59_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~58_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~61_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~62_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~63_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~60_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~64_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~65_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; +wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; +wire \z80_|reg_file_|db_hi_as[7]~16_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; +wire \z80_|reg_file_|db_hi_as[7]~17_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; +wire \z80_|reg_file_|db_hi_as[1]~0_combout ; +wire \z80_|reg_file_|db_hi_as[1]~1_combout ; +wire \z80_|execute_|ctl_al_we~6_combout ; +wire \z80_|execute_|ctl_al_we~9_combout ; +wire \z80_|execute_|ctl_al_we~10_combout ; +wire \z80_|execute_|ctl_al_we~7_combout ; +wire \z80_|execute_|ctl_al_we~8_combout ; +wire \z80_|execute_|ctl_al_we~11_combout ; +wire \z80_|execute_|ctl_al_we~12_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~82_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~81_combout ; +wire \z80_|alu_control_|db[6]~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|execute_|ctl_flags_sz_we~8_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; +wire \z80_|alu_control_|db[7]~18_combout ; +wire \z80_|alu_control_|db[7]~19_combout ; +wire \z80_|alu_control_|db[7]~20_combout ; +wire \z80_|alu_control_|db[7]~37_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; +wire \z80_|reg_file_|db_lo_as[7]~22_combout ; +wire \z80_|reg_file_|db_lo_as[7]~23_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[7]~24_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[1]~3_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~44_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~45_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~42_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~43_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~46_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~40_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~41_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~47_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~48_combout ; +wire \z80_|reg_file_|db_hi_as[2]~10_combout ; +wire \z80_|reg_file_|db_hi_as[2]~11_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[2]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~50_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~49_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~51_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~52_combout ; +wire \z80_|alu_|db[4]~8_combout ; +wire \z80_|alu_|db[4]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~53_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~54_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~55_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~56_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~57_combout ; +wire \z80_|reg_file_|db_hi_as[4]~13_combout ; +wire \z80_|reg_file_|db_hi_as[4]~14_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[4]~15_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~76_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~77_combout ; +wire \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~79_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; +wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; +wire \z80_|alu_|db_low[1]~18_combout ; +wire \z80_|alu_|db_low[1]~19_combout ; +wire \z80_|alu_|db_low[1]~16_combout ; +wire \z80_|alu_|db_low[1]~15_combout ; +wire \z80_|alu_|db_low[1]~17_combout ; +wire \z80_|alu_|db_low[1]~20_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; +wire \z80_|alu_|alu_op2[1]~2_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; +wire \z80_|alu_|db_high[2]~10_combout ; +wire \z80_|alu_|db_high[2]~8_combout ; +wire \z80_|alu_|db_high[2]~9_combout ; +wire \z80_|alu_|db_high[2]~11_combout ; +wire \z80_|alu_|db_high[2]~12_combout ; +wire \z80_|alu_|db_high[2]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~68_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~67_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~72_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~70_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~69_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~71_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~73_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~74_combout ; +wire \z80_|reg_file_|db_hi_as[6]~19_combout ; +wire \z80_|reg_file_|db_hi_as[6]~20_combout ; +wire \z80_|reg_file_|db_hi_as[6]~21_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~75_combout ; +wire \z80_|alu_|db[6]~21_combout ; +wire \z80_|alu_|db[6]~22_combout ; +wire \z80_|alu_|db_high[1]~16_combout ; +wire \z80_|alu_|db_high[1]~17_combout ; +wire \z80_|alu_|db_high[1]~14_combout ; +wire \z80_|alu_|db_high[1]~15_combout ; +wire \z80_|alu_|db_high[1]~18_combout ; +wire \z80_|alu_|db_high[1]~19_combout ; +wire \z80_|alu_|db[5]~23_combout ; +wire \z80_|alu_|db[5]~24_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~80_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~81_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~78_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~82_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~83_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~84_combout ; +wire \z80_|reg_file_|db_hi_as[5]~22_combout ; +wire \z80_|reg_file_|db_hi_as[5]~23_combout ; +wire \z80_|reg_file_|db_hi_as[5]~24_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|reg_file_|db_hi_as[7]~18_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~66_combout ; +wire \z80_|alu_|db[7]~19_combout ; +wire \z80_|alu_|db[7]~20_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ; +wire \z80_|alu_|alu_op1[3]~0_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ; +wire \z80_|alu_|alu_op2[2]~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; +wire \z80_|execute_|ctl_flags_cf_we~3_combout ; +wire \z80_|execute_|ctl_flags_hf_we~2_combout ; +wire \z80_|execute_|ctl_flags_cf_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf_we~5_combout ; +wire \z80_|execute_|ctl_flags_cf_we~6_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~6_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~5_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; +wire \z80_|alu_|db_low[0]~21_combout ; +wire \z80_|alu_|db_low[0]~22_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ; +wire \z80_|alu_|db_low[0]~24_combout ; +wire \z80_|alu_|db_low[0]~23_combout ; +wire \z80_|alu_|db_low[0]~25_combout ; +wire \z80_|alu_|db_low[0]~27_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ; +wire \z80_|alu_|alu_op2[0]~3_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|execute_|ctl_alu_op_low~34_combout ; +wire \z80_|execute_|ctl_alu_op_low~36_combout ; +wire \z80_|execute_|ctl_alu_op_low~35_combout ; +wire \z80_|execute_|ctl_alu_core_hf~13_combout ; +wire \z80_|execute_|ctl_alu_core_hf~14_combout ; +wire \z80_|execute_|ctl_alu_core_hf~15_combout ; +wire \z80_|execute_|ctl_alu_core_hf~16_combout ; +wire \z80_|execute_|ctl_alu_core_hf~17_combout ; +wire \z80_|execute_|ctl_alu_core_hf~37_combout ; +wire \z80_|execute_|ctl_alu_core_hf~38_combout ; +wire \z80_|execute_|ctl_alu_core_hf~36_combout ; +wire \z80_|execute_|ctl_alu_core_hf~23_combout ; +wire \z80_|execute_|ctl_alu_core_hf~34_combout ; +wire \z80_|execute_|ctl_alu_core_hf~29_combout ; +wire \z80_|execute_|ctl_alu_core_hf~26_combout ; +wire \z80_|execute_|ctl_alu_core_hf~35_combout ; +wire \z80_|execute_|ctl_alu_core_hf~27_combout ; +wire \z80_|execute_|ctl_alu_core_hf~28_combout ; +wire \z80_|execute_|ctl_alu_core_hf~30_combout ; +wire \z80_|execute_|ctl_alu_op_low~37_combout ; +wire \z80_|execute_|ctl_alu_core_hf~24_combout ; +wire \z80_|execute_|ctl_alu_core_hf~25_combout ; +wire \z80_|execute_|ctl_alu_core_hf~31_combout ; +wire \z80_|execute_|ctl_alu_core_hf~20_combout ; +wire \z80_|execute_|ctl_alu_core_hf~21_combout ; +wire \z80_|execute_|ctl_alu_core_hf~18_combout ; +wire \z80_|execute_|ctl_alu_core_hf~19_combout ; +wire \z80_|execute_|ctl_alu_core_hf~22_combout ; +wire \z80_|execute_|ctl_alu_core_hf~32_combout ; +wire \z80_|execute_|ctl_alu_core_hf~33_combout ; +wire \z80_|alu_control_|alu_core_cf_in~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; +wire \z80_|alu_|db_high[0]~21_combout ; +wire \z80_|alu_|db_high[0]~22_combout ; +wire \z80_|alu_|db_high[0]~23_combout ; +wire \z80_|alu_|db_high[0]~20_combout ; +wire \z80_|alu_|db_high[0]~24_combout ; +wire \z80_|alu_|db_high[0]~25_combout ; +wire \z80_|alu_|alu_op1[0]~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; +wire \z80_|alu_|db_low[2]~11_combout ; +wire \z80_|alu_|db_low[2]~12_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; +wire \z80_|alu_|db_low[2]~13_combout ; +wire \z80_|alu_|db_low[2]~14_combout ; +wire \z80_|alu_|db[2]~11_combout ; +wire \z80_|alu_|db[2]~12_combout ; +wire \z80_|alu_control_|db[2]~28_combout ; +wire \z80_|alu_flags_|flags_hf2~0_combout ; +wire \z80_|alu_flags_|flags_hf2~q ; +wire \z80_|alu_control_|out[6]~0_combout ; +wire \z80_|execute_|ctl_66_oe~combout ; +wire \z80_|alu_control_|db[2]~24_combout ; wire \z80_|execute_|ctl_reg_out_lo~3_combout ; wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; wire \z80_|execute_|ctl_reg_out_lo~4_combout ; wire \z80_|execute_|ctl_reg_out_lo~5_combout ; -wire \z80_|execute_|ctl_reg_out_lo~8_combout ; -wire \z80_|sw1_|db_down[3]~1_combout ; -wire \z80_|alu_control_|db[3]~34_combout ; -wire \z80_|alu_control_|db[3]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~52_combout ; -wire \z80_|reg_file_|db_lo_as[3]~10_combout ; -wire \z80_|reg_file_|db_lo_as[3]~11_combout ; -wire \z80_|reg_file_|db_lo_as[3]~12_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ; +wire \z80_|reg_file_|db_lo_ds[2]~1_combout ; +wire \z80_|alu_control_|db[2]~29_combout ; +wire \z80_|alu_control_|db[2]~30_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; +wire \z80_|reg_file_|db_lo_as[2]~7_combout ; +wire \z80_|reg_file_|db_lo_as[2]~8_combout ; +wire \z80_|reg_file_|db_lo_as[2]~9_combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~62_combout ; -wire \z80_|reg_file_|db_lo_as[4]~13_combout ; -wire \z80_|reg_file_|db_lo_as[4]~14_combout ; -wire \z80_|reg_file_|db_lo_as[4]~15_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; -wire \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~62_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~72_combout ; wire \z80_|reg_file_|db_lo_as[5]~16_combout ; wire \z80_|reg_file_|db_lo_as[5]~17_combout ; wire \z80_|reg_file_|db_lo_as[5]~18_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ; wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~72_combout ; +wire \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ; wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; wire \z80_|reg_file_|db_lo_as[6]~19_combout ; wire \z80_|reg_file_|db_lo_as[6]~20_combout ; wire \z80_|reg_file_|db_lo_as[6]~21_combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[7]~24_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~92_combout ; -wire \z80_|reg_file_|db_lo_ds[7]~0_combout ; -wire \z80_|interrupts_|im2~q ; -wire \z80_|execute_|ctl_mRead~12_combout ; -wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; -wire \z80_|alu_control_|db[7]~17_combout ; -wire \z80_|alu_control_|db[7]~16_combout ; -wire \z80_|alu_control_|db[7]~18_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|execute_|ctl_flags_sz_we~8_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; -wire \z80_|pla_decode_|Equal62~3_combout ; -wire \z80_|execute_|ctl_flags_pf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~6_combout ; -wire \z80_|execute_|ctl_flags_pf_we~7_combout ; -wire \z80_|execute_|ctl_flags_pf_we~8_combout ; -wire \z80_|execute_|ctl_flags_pf_we~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[0]~4_combout ; +wire \z80_|reg_file_|db_hi_as[0]~5_combout ; +wire \z80_|reg_file_|db_hi_as[0]~6_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; +wire \z80_|alu_|db[0]~17_combout ; +wire \z80_|alu_|db[0]~18_combout ; +wire \z80_|sw2_|db_up[0]~0_combout ; +wire \z80_|alu_control_|db[0]~11_combout ; +wire \z80_|alu_control_|db[0]~14_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; +wire \z80_|reg_file_|db_lo_as[0]~0_combout ; +wire \z80_|reg_file_|db_lo_as[0]~1_combout ; +wire \z80_|reg_file_|db_lo_as[0]~3_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; +wire \z80_|reg_file_|db_lo_as[1]~4_combout ; +wire \z80_|reg_file_|db_lo_as[1]~5_combout ; +wire \z80_|reg_file_|db_lo_as[1]~6_combout ; +wire \z80_|address_latch_|Q[1]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; +wire \z80_|reg_file_|db_lo_as[3]~12_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; +wire \z80_|alu_control_|db[3]~35_combout ; +wire \z80_|alu_control_|db[3]~36_combout ; +wire \z80_|alu_|db[3]~14_combout ; +wire \z80_|alu_|db_low[3]~4_combout ; +wire \z80_|alu_|db_low[3]~5_combout ; +wire \z80_|alu_|db_low[3]~6_combout ; +wire \z80_|alu_|db_low[3]~7_combout ; +wire \z80_|alu_|db_low[3]~8_combout ; +wire \z80_|alu_|db_low[3]~26_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ; +wire \z80_|alu_|alu_op2[3]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ; +wire \z80_|alu_|db_high[3]~4_combout ; +wire \z80_|alu_|db_high[3]~2_combout ; +wire \z80_|alu_|db_high[3]~3_combout ; +wire \z80_|alu_|db_high[3]~5_combout ; +wire \z80_|alu_|db_high[3]~6_combout ; +wire \z80_|alu_|db_high[3]~7_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; +wire \z80_|execute_|ctl_flags_nf_we~0_combout ; +wire \z80_|execute_|ctl_flags_nf_we~1_combout ; +wire \z80_|execute_|ctl_flags_nf_we~2_combout ; +wire \z80_|execute_|ctl_flags_nf_we~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; +wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; +wire \z80_|execute_|ctl_flags_cf_set~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; +wire \z80_|alu_control_|out[6]~1_combout ; +wire \z80_|alu_control_|out[6]~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; +wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; +wire \z80_|execute_|ctl_alu_op_low~21_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; +wire \z80_|pla_decode_|Equal64~0_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; +wire \z80_|alu_flags_|flags_cf~combout ; +wire \z80_|execute_|ctl_flags_hf_we~3_combout ; +wire \z80_|execute_|ctl_flags_hf_we~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; +wire \z80_|execute_|ctl_flags_hf_cpl~9_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; +wire \z80_|alu_flags_|flags_hf~combout ; +wire \z80_|alu_control_|db[4]~31_combout ; +wire \z80_|alu_control_|db[4]~32_combout ; +wire \z80_|alu_control_|db[4]~33_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~52_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; +wire \z80_|reg_file_|db_lo_as[4]~13_combout ; +wire \z80_|reg_file_|db_lo_as[4]~14_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[4]~15_combout ; wire \z80_|decode_state_|DFFE_instNonRep~2_combout ; wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; wire \z80_|decode_state_|DFFE_instNonRep~4_combout ; wire \z80_|decode_state_|DFFE_instNonRep~5_combout ; wire \z80_|decode_state_|DFFE_instNonRep~q ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; +wire \z80_|pla_decode_|Equal79~0_combout ; +wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|interrupts_|DFFE_instIFF2~q ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; +wire \z80_|execute_|ctl_pf_sel[1]~12_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~11_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; wire \z80_|alu_|alu_parity_out~0_combout ; wire \z80_|alu_|alu_parity_out~combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~q ; -wire \z80_|alu_control_|sel[1]~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; wire \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ; wire \z80_|alu_control_|flags_cond_true~0_combout ; wire \z80_|alu_control_|flags_cond_true~q ; -wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; -wire \z80_|reg_file_|db_lo_ds[1]~1_combout ; -wire \z80_|alu_control_|db[1]~25_combout ; -wire \z80_|alu_control_|db[1]~24_combout ; -wire \z80_|alu_control_|db[1]~26_combout ; -wire \z80_|alu_|db[1]~12_combout ; -wire \z80_|alu_|db[1]~13_combout ; -wire \z80_|alu_|db_low[0]~21_combout ; -wire \z80_|alu_|db_low[0]~22_combout ; -wire \z80_|alu_|db_low[0]~18_combout ; -wire \z80_|alu_|db_low[0]~19_combout ; -wire \z80_|alu_|db_low[0]~20_combout ; -wire \z80_|alu_|db_low[0]~23_combout ; -wire \z80_|alu_|db[0]~18_combout ; -wire \z80_|alu_|db[0]~19_combout ; -wire \z80_|alu_|db_low[1]~15_combout ; -wire \z80_|alu_|db_low[1]~16_combout ; -wire \z80_|alu_|db_low[1]~12_combout ; -wire \z80_|alu_|db_low[1]~13_combout ; -wire \z80_|alu_|db_low[1]~14_combout ; -wire \z80_|alu_|db_low[1]~17_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ; -wire \z80_|alu_control_|out[6]~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; -wire \z80_|alu_flags_|flags_hf2~0_combout ; -wire \z80_|alu_flags_|flags_hf2~q ; -wire \z80_|alu_control_|db[2]~23_combout ; -wire \z80_|reg_file_|db_lo_ds[2]~2_combout ; -wire \z80_|alu_control_|db[2]~28_combout ; -wire \z80_|alu_control_|db[2]~27_combout ; -wire \z80_|alu_control_|db[2]~29_combout ; -wire \z80_|alu_|db[2]~14_combout ; -wire \z80_|alu_|db[2]~15_combout ; -wire \z80_|alu_|db_low[2]~2_combout ; -wire \z80_|alu_|db_low[2]~3_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ; -wire \z80_|alu_|db_low[2]~5_combout ; -wire \z80_|alu_|db_low[2]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ; -wire \z80_|alu_|alu_op2[2]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; -wire \z80_|alu_|db_high[2]~9_combout ; -wire \z80_|alu_|db_high[2]~11_combout ; -wire \z80_|alu_|db_high[2]~12_combout ; -wire \z80_|alu_|db_high[2]~10_combout ; -wire \z80_|alu_|db_high[2]~13_combout ; -wire \z80_|alu_|db_high[2]~14_combout ; -wire \z80_|alu_|db[6]~22_combout ; -wire \z80_|alu_|db[6]~23_combout ; -wire \z80_|alu_control_|out[6]~1_combout ; -wire \z80_|alu_control_|out[6]~2_combout ; -wire \z80_|alu_control_|db[6]~19_combout ; -wire \z80_|alu_control_|db[6]~20_combout ; -wire \z80_|alu_control_|db[6]~21_combout ; -wire \z80_|alu_control_|db[6]~22_combout ; -wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; -wire \z80_|interrupts_|im1~q ; -wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; -wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; -wire \z80_|bus_control_|db[0]~4_combout ; -wire \z80_|bus_control_|db[6]~8_combout ; -wire \z80_|execute_|ctl_mRead~37_combout ; -wire \z80_|execute_|ctl_mRead~28_combout ; -wire \z80_|execute_|ctl_mRead~29_combout ; -wire \z80_|execute_|ctl_mRead~30_combout ; -wire \z80_|execute_|setM1~37_combout ; -wire \z80_|execute_|setM1~55_combout ; -wire \z80_|execute_|setM1~38_combout ; -wire \z80_|execute_|ctl_mRead~34_combout ; -wire \z80_|execute_|nextM~3_combout ; -wire \z80_|execute_|ctl_mRead~31_combout ; -wire \z80_|execute_|ctl_mRead~32_combout ; -wire \z80_|execute_|ctl_mRead~33_combout ; -wire \z80_|execute_|ctl_mRead~35_combout ; -wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; -wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; -wire \z80_|memory_ifc_|wait_mrd~q ; -wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; -wire \z80_|memory_ifc_|nRD_out~1_combout ; -wire \z80_|execute_|nextM~4_combout ; -wire \z80_|execute_|ctl_iorw~12_combout ; -wire \z80_|execute_|ctl_iorw~8_combout ; -wire \z80_|execute_|ctl_iorw~9_combout ; -wire \z80_|memory_ifc_|DFFE_iorq_ff1~q ; -wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ; -wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ; -wire \z80_|memory_ifc_|wait_iorq~q ; -wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; -wire \z80_|memory_ifc_|iorq~0_combout ; -wire \z80_|execute_|fIORead~1_combout ; -wire \z80_|execute_|fIORead~2_combout ; -wire \z80_|execute_|fIORead~0_combout ; -wire \z80_|execute_|fIORead~3_combout ; -wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; -wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; -wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; -wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; -wire \z80_|memory_ifc_|nRD_out~0_combout ; -wire \z80_|memory_ifc_|nRD_out~2_combout ; -wire \Equal2~1_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~0_combout ; -wire \z80_|execute_|fMWrite~5_combout ; -wire \z80_|execute_|fMWrite~6_combout ; -wire \z80_|execute_|fMWrite~2_combout ; -wire \z80_|execute_|fMWrite~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~1_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; -wire \z80_|execute_|fMWrite~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; -wire \z80_|execute_|fMWrite~9_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; -wire \z80_|execute_|fMWrite~8_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; -wire \z80_|execute_|fMWrite~10_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; -wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; -wire \z80_|clk_delay_|DFF_inst5~q ; -wire \z80_|memory_ifc_|wait_iorqinta~feeder_combout ; -wire \z80_|memory_ifc_|wait_iorqinta~q ; -wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; -wire \z80_|memory_ifc_|nIORQ_out~0_combout ; -wire \Equal2~0_combout ; -wire \ExtRamWE~0_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; +wire \z80_|reg_file_|db_hi_as[0]~2_combout ; +wire \z80_|reg_file_|db_hi_as[3]~7_combout ; +wire \z80_|reg_file_|db_hi_as[3]~8_combout ; +wire \z80_|reg_file_|db_hi_as[3]~9_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; wire \z80_|execute_|ctl_apin_mux2~0_combout ; wire \z80_|pin_control_|bus_ab_pin_we~2_combout ; wire \z80_|pin_control_|bus_ab_pin_we~3_combout ; -wire \z80_|address_pins_|abus[13]~20_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; -wire \z80_|address_pins_|abus[14]~23_combout ; +wire \z80_|address_pins_|abus[11]~19_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; +wire \z80_|address_pins_|abus[10]~20_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~19_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~48_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~51_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~q ; +wire \D[2]~43_combout ; +wire \ula_|zx_keyboard_|WideOr17~0_combout ; +wire \ula_|zx_keyboard_|shifted~2_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~11_combout ; +wire \ula_|zx_keyboard_|shifted~0_combout ; +wire \ula_|zx_keyboard_|shifted~3_combout ; +wire \ula_|zx_keyboard_|shifted~q ; +wire \ula_|zx_keyboard_|keys[5][0]~62_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~32_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~63_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~64_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~65_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~q ; wire \z80_|address_pins_|DFFE_apin_latch[15]~15_combout ; -wire \z80_|address_pins_|abus[15]~22_combout ; -wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; +wire \z80_|address_pins_|abus[15]~21_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; +wire \z80_|address_pins_|abus[14]~22_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~57_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~58_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~59_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~28_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~60_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~56_combout ; +wire \ula_|zx_keyboard_|Selector13~0_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~q ; +wire \D[2]~44_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; +wire \z80_|address_pins_|abus[12]~24_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~29_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~54_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~55_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~q ; +wire \ula_|zx_keyboard_|key_row~1_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~127_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~66_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~128_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~67_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~q ; +wire \D[2]~45_combout ; wire \z80_|address_pins_|abus[0]~16_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~43_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~44_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~45_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~46_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~q ; +wire \ula_|zx_keyboard_|keys[0][2]~47_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~49_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~q ; +wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; +wire \z80_|address_pins_|abus[9]~17_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; +wire \z80_|address_pins_|abus[8]~18_combout ; +wire \D[2]~42_combout ; +wire \D[2]~46_combout ; +wire \z80_|memory_ifc_|wait_iorqinta~q ; +wire \z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ; +wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; +wire \z80_|control_pins_|pin_nIORQ~1_combout ; +wire \Equal2~0_combout ; +wire \z80_|address_pins_|abus[13]~23_combout ; +wire \ExtRamWE~0_combout ; +wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; wire \z80_|address_pins_|DFFE_apin_latch[1]~1_combout ; wire \z80_|address_pins_|abus[1]~25_combout ; wire \z80_|address_pins_|DFFE_apin_latch[2]~2_combout ; @@ -1807,30 +1993,20 @@ wire \z80_|address_pins_|DFFE_apin_latch[6]~6_combout ; wire \z80_|address_pins_|abus[6]~30_combout ; wire \z80_|address_pins_|DFFE_apin_latch[7]~7_combout ; wire \z80_|address_pins_|abus[7]~31_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; -wire \z80_|address_pins_|abus[8]~18_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; -wire \z80_|address_pins_|abus[9]~17_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; -wire \z80_|address_pins_|abus[10]~24_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; -wire \z80_|address_pins_|abus[11]~19_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; -wire \z80_|address_pins_|abus[12]~21_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; -wire \D[6]~90_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; -wire \D[6]~91_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; +wire \D[2]~50_combout ; +wire \D[2]~51_combout ; wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ; wire \CLOCK_50~inputclkctrl_outclk ; wire \~GND~combout ; -wire \ula_|video_|vram_address[0]~feeder_combout ; wire \ula_|video_|vram_address~0_combout ; +wire \ula_|video_|vram_address[1]~feeder_combout ; wire \ula_|video_|vram_address[2]~4_combout ; wire \ula_|video_|Add3~0_combout ; wire \ula_|video_|Add3~1_combout ; @@ -1842,638 +2018,521 @@ wire \ula_|video_|Add4~7 ; wire \ula_|video_|Add4~8_combout ; wire \ula_|video_|Add4~9 ; wire \ula_|video_|Add4~10_combout ; +wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Add4~11 ; wire \ula_|video_|Add4~12_combout ; -wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Selector6~0_combout ; -wire \ula_|video_|vram_address[9]~1_combout ; +wire \ula_|video_|vram_address[8]~1_combout ; wire \ula_|video_|Add4~13 ; wire \ula_|video_|Add4~14_combout ; wire \ula_|video_|Add4~2_combout ; wire \ula_|video_|Selector5~0_combout ; -wire \ula_|video_|Add4~4_combout ; wire \ula_|video_|vram_address[10]~2_combout ; +wire \ula_|video_|Add4~4_combout ; wire \ula_|video_|vram_address[10]~3_combout ; wire \ula_|video_|Selector3~0_combout ; wire \ula_|video_|Selector2~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \D[6]~87_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \D[6]~88_combout ; -wire \D[6]~89_combout ; -wire \D[6]~111_combout ; -wire \raw_loader_in~input_o ; -wire \D[6]~86_combout ; -wire \D[6]~100_combout ; -wire \D[6]~101_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \D[2]~47_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \D[2]~48_combout ; +wire \D[2]~49_combout ; +wire \D[2]~119_combout ; +wire \D[2]~52_combout ; +wire \D[2]~53_combout ; wire \z80_|pin_control_|bus_db_pin_re~2_combout ; wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; -wire \z80_|bus_control_|db[6]~9_combout ; -wire \z80_|ir_|opcode[6]~feeder_combout ; +wire \z80_|bus_control_|db[2]~12_combout ; +wire \z80_|bus_control_|db[0]~6_combout ; +wire \z80_|bus_control_|db[2]~13_combout ; +wire \z80_|ir_|opcode[2]~feeder_combout ; wire \z80_|execute_|ctl_ir_we~13_combout ; -wire \z80_|pla_decode_|Equal41~0_combout ; -wire \z80_|pla_decode_|Equal41~1_combout ; -wire \z80_|pla_decode_|Equal41~2_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~combout ; -wire \z80_|alu_|db_high[1]~15_combout ; -wire \z80_|alu_|db_high[1]~16_combout ; -wire \z80_|alu_|db_high[1]~17_combout ; -wire \z80_|alu_|db_high[1]~18_combout ; -wire \z80_|alu_|db_high[1]~19_combout ; -wire \z80_|alu_|db_high[1]~20_combout ; -wire \z80_|alu_|db[5]~24_combout ; -wire \z80_|alu_|db[5]~25_combout ; -wire \z80_|sw1_|db_down[5]~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; -wire \z80_|alu_flags_|flags_yf~q ; -wire \z80_|alu_control_|db[5]~13_combout ; -wire \z80_|alu_control_|db[5]~14_combout ; -wire \z80_|alu_control_|db[5]~15_combout ; -wire \D[0]~107_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \Mux2~0_combout ; -wire \Mux2~1_combout ; -wire \D[5]~110_combout ; -wire \D[5]~85_combout ; -wire \D[5]~99_combout ; -wire \z80_|bus_control_|db[5]~14_combout ; -wire \z80_|bus_control_|db[5]~15_combout ; -wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|decode_state_|DFFE_inst4~q ; -wire \z80_|decode_state_|use_ixiy~combout ; -wire \z80_|execute_|ctl_mRead~23_combout ; -wire \z80_|execute_|fMRead~34_combout ; -wire \z80_|execute_|fMRead~31_combout ; +wire \z80_|execute_|ctl_mRead~34_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ; +wire \z80_|execute_|ctl_reg_out_lo~6_combout ; +wire \z80_|execute_|ctl_reg_out_lo~7_combout ; +wire \z80_|execute_|ctl_reg_out_lo~8_combout ; +wire \z80_|alu_control_|db[6]~13_combout ; +wire \z80_|alu_control_|db[6]~21_combout ; +wire \z80_|alu_control_|db[6]~22_combout ; +wire \z80_|reg_file_|db_lo_ds[6]~0_combout ; +wire \z80_|sw1_|db_down[6]~1_combout ; +wire \z80_|alu_control_|db[6]~23_combout ; +wire \z80_|bus_control_|db[6]~8_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; +wire \D[6]~103_combout ; +wire \D[6]~104_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \D[6]~100_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \D[6]~101_combout ; +wire \D[6]~102_combout ; +wire \D[6]~127_combout ; +wire \raw_loader_in~input_o ; +wire \D[6]~99_combout ; +wire \D[6]~114_combout ; +wire \D[6]~115_combout ; +wire \z80_|bus_control_|db[6]~9_combout ; +wire \z80_|pla_decode_|Equal13~0_combout ; +wire \z80_|pla_decode_|Equal38~2_combout ; +wire \z80_|interrupts_|iff1~0_combout ; +wire \z80_|interrupts_|iff1~1_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|interrupts_|iff1~q ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ; +wire \z80_|interrupts_|int_armed~q ; +wire \z80_|interrupts_|DFFE_inst44~q ; +wire \z80_|decode_state_|in_halt~0_combout ; +wire \z80_|pla_decode_|Equal77~1_combout ; +wire \z80_|decode_state_|in_halt~1_combout ; +wire \z80_|decode_state_|in_halt~q ; +wire \z80_|execute_|ctl_mRead~21_combout ; +wire \z80_|execute_|fMRead~35_combout ; +wire \z80_|execute_|fMRead~23_combout ; +wire \z80_|execute_|fMRead~27_combout ; +wire \z80_|execute_|fMRead~28_combout ; wire \z80_|execute_|fMRead~29_combout ; wire \z80_|execute_|fMRead~30_combout ; -wire \z80_|execute_|fMRead~28_combout ; +wire \z80_|execute_|fMRead~31_combout ; wire \z80_|execute_|fMRead~32_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; -wire \z80_|execute_|fMRead~14_combout ; -wire \z80_|execute_|fMRead~10_combout ; -wire \z80_|execute_|fMRead~9_combout ; +wire \z80_|execute_|fMRead~37_combout ; +wire \z80_|execute_|fMRead~33_combout ; +wire \z80_|execute_|fMRead~24_combout ; +wire \z80_|execute_|fMRead~25_combout ; +wire \z80_|execute_|fMRead~16_combout ; wire \z80_|execute_|fMRead~11_combout ; wire \z80_|execute_|fMRead~12_combout ; wire \z80_|execute_|fMRead~13_combout ; +wire \z80_|execute_|fMRead~14_combout ; wire \z80_|execute_|fMRead~15_combout ; -wire \z80_|execute_|fMRead~20_combout ; -wire \z80_|execute_|pc_inc_hold~48_combout ; +wire \z80_|execute_|fMRead~17_combout ; wire \z80_|execute_|fMRead~22_combout ; -wire \z80_|execute_|fMRead~21_combout ; -wire \z80_|execute_|fMRead~23_combout ; -wire \z80_|execute_|fMRead~26_combout ; -wire \z80_|execute_|fMRead~25_combout ; -wire \z80_|execute_|fMRead~27_combout ; -wire \z80_|execute_|fMRead~33_combout ; -wire \z80_|execute_|fMRead~35_combout ; +wire \z80_|execute_|fMRead~34_combout ; +wire \z80_|execute_|fMRead~36_combout ; wire \z80_|pin_control_|bus_db_pin_re~combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \Selector1~0_combout ; -wire \Selector1~1_combout ; -wire \D[1]~103_combout ; -wire \PS2_DAT~input_o ; -wire \reset~clkctrl_outclk ; -wire \ula_|ps2_keyboard_|bit_count~0_combout ; -wire \PS2_CLK~input_o ; -wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~0_combout ; -wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~1_combout ; -wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~q ; -wire \ula_|ps2_keyboard_|clk_edge~0_combout ; -wire \ula_|ps2_keyboard_|clk_edge~q ; -wire \ula_|ps2_keyboard_|bit_count~1_combout ; -wire \ula_|ps2_keyboard_|bit_count~3_combout ; -wire \ula_|ps2_keyboard_|bit_count~2_combout ; -wire \ula_|ps2_keyboard_|always1~0_combout ; -wire \ula_|ps2_keyboard_|LessThan0~0_combout ; -wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; -wire \ula_|zx_keyboard_|Equal0~0_combout ; -wire \ula_|zx_keyboard_|Equal0~1_combout ; -wire \ula_|zx_keyboard_|extended~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~1_combout ; -wire \ula_|ps2_keyboard_|WideXor0~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~2_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~q ; -wire \ula_|zx_keyboard_|extended~q ; -wire \ula_|zx_keyboard_|keys[0][0]~15_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; -wire \ula_|zx_keyboard_|shifted~0_combout ; -wire \ula_|zx_keyboard_|released~0_combout ; -wire \ula_|zx_keyboard_|released~q ; -wire \ula_|zx_keyboard_|WideOr17~0_combout ; -wire \ula_|zx_keyboard_|shifted~2_combout ; -wire \ula_|zx_keyboard_|shifted~3_combout ; -wire \ula_|zx_keyboard_|shifted~q ; -wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~103_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~20_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~21_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~q ; +wire \ula_|zx_keyboard_|keys[3][0]~73_combout ; +wire \ula_|zx_keyboard_|Selector5~0_combout ; +wire \ula_|zx_keyboard_|Selector5~1_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~129_combout ; +wire \ula_|zx_keyboard_|WideOr16~1_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~105_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~130_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~q ; +wire \D[3]~74_combout ; wire \ula_|zx_keyboard_|keys[5][1]~39_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~q ; -wire \ula_|zx_keyboard_|keys[4][1]~31_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~23_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~32_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~33_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~34_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~q ; -wire \D[1]~30_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~24_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~29_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~30_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~25_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~26_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~27_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~q ; -wire \ula_|zx_keyboard_|key_row~0_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~17_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~18_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~q ; -wire \ula_|zx_keyboard_|keys[7][4]~19_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~20_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~21_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~22_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~q ; -wire \D[1]~28_combout ; -wire \D[1]~29_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~43_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~44_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~q ; -wire \ula_|zx_keyboard_|keys[7][1]~45_combout ; -wire \ula_|zx_keyboard_|WideOr16~5_combout ; -wire \ula_|zx_keyboard_|WideOr16~2_combout ; -wire \ula_|zx_keyboard_|WideOr16~4_combout ; -wire \ula_|zx_keyboard_|WideOr16~7_combout ; -wire \ula_|zx_keyboard_|WideOr16~6_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~46_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~q ; -wire \D[1]~31_combout ; -wire \D[1]~32_combout ; -wire \D[1]~33_combout ; -wire \D[1]~34_combout ; -wire \z80_|bus_control_|db[1]~10_combout ; -wire \z80_|bus_control_|db[1]~11_combout ; -wire \z80_|ir_|opcode[1]~feeder_combout ; -wire \z80_|pla_decode_|Equal40~0_combout ; -wire \z80_|pla_decode_|Equal21~1_combout ; -wire \z80_|execute_|ctl_alu_op_low~26_combout ; -wire \z80_|execute_|ctl_alu_op_low~28_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; -wire \z80_|execute_|ctl_alu_op_low~32_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; -wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~10_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; -wire \z80_|execute_|ctl_flags_cf_set~0_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~9_combout ; -wire \z80_|alu_flags_|flags_cf~combout ; -wire \z80_|alu_control_|db[0]~8_combout ; -wire \z80_|sw2_|db_up[0]~0_combout ; -wire \z80_|alu_control_|db[0]~9_combout ; -wire \z80_|alu_control_|db[0]~12_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~67_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~81_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~82_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~83_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~q ; -wire \ula_|zx_keyboard_|keys[4][0]~84_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~85_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~86_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~q ; -wire \D[0]~49_combout ; -wire \ula_|zx_keyboard_|WideOr4~0_combout ; -wire \ula_|zx_keyboard_|keys~76_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~73_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~47_combout ; -wire \ula_|zx_keyboard_|WideOr0~0_combout ; -wire \ula_|zx_keyboard_|keys~74_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~75_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~77_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~q ; -wire \ula_|zx_keyboard_|keys[1][0]~71_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~72_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~q ; -wire \D[0]~47_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~80_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~q ; -wire \ula_|zx_keyboard_|keys[3][0]~78_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~79_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~q ; -wire \ula_|zx_keyboard_|key_row~1_combout ; -wire \D[0]~48_combout ; -wire \ula_|zx_keyboard_|shifted~1_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~91_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~92_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~q ; -wire \ula_|zx_keyboard_|keys[5][4]~63_combout ; -wire \ula_|zx_keyboard_|WideOr16~3_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~132_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~88_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~89_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~q ; -wire \D[0]~50_combout ; -wire \D[0]~51_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~55_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \D[0]~56_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \D[0]~52_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~53_combout ; -wire \D[0]~54_combout ; -wire \D[0]~106_combout ; -wire \D[0]~57_combout ; -wire \D[0]~58_combout ; -wire \z80_|bus_control_|db[0]~16_combout ; -wire \z80_|bus_control_|db[0]~17_combout ; -wire \z80_|pla_decode_|Equal63~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; -wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; -wire \z80_|alu_control_|db[6]~10_combout ; -wire \z80_|alu_control_|db[6]~11_combout ; -wire \z80_|alu_control_|db[4]~30_combout ; -wire \z80_|alu_control_|db[4]~31_combout ; -wire \z80_|alu_control_|db[4]~32_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~119_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~120_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~95_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~121_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~q ; -wire \ula_|zx_keyboard_|keys[3][4]~117_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~136_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~130_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~118_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~q ; -wire \D[4]~78_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~126_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~128_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~129_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~q ; -wire \ula_|zx_keyboard_|keys[6][4]~127_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~q ; -wire \ula_|zx_keyboard_|Equal0~2_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~51_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~125_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~q ; -wire \D[4]~79_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~122_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~123_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~q ; -wire \ula_|zx_keyboard_|key_row~3_combout ; -wire \D[4]~80_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~111_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~97_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~116_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~115_combout ; -wire \ula_|zx_keyboard_|keys[1][4]~q ; -wire \D[4]~77_combout ; -wire \D[4]~81_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \Selector4~0_combout ; -wire \Selector4~1_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ; -wire \D[4]~109_combout ; -wire \D[4]~97_combout ; -wire \D[4]~98_combout ; -wire \z80_|bus_control_|db[4]~18_combout ; -wire \z80_|bus_control_|db[4]~19_combout ; -wire \z80_|pla_decode_|Equal21~0_combout ; -wire \z80_|execute_|ctl_mRead~5_combout ; -wire \z80_|execute_|fIOWrite~2_combout ; -wire \z80_|execute_|fIOWrite~3_combout ; -wire \z80_|execute_|fIOWrite~4_combout ; -wire \z80_|execute_|fIOWrite~5_combout ; -wire \z80_|execute_|ctl_mWrite~11_combout ; -wire \z80_|execute_|ctl_mWrite~12_combout ; -wire \z80_|execute_|ctl_mWrite~13_combout ; -wire \z80_|execute_|ctl_mWrite~14_combout ; -wire \z80_|execute_|ctl_mWrite~15_combout ; -wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; -wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; -wire \z80_|memory_ifc_|wait_mwr~q ; -wire \z80_|memory_ifc_|mwr_wr~q ; -wire \z80_|memory_ifc_|nWR_out~0_combout ; -wire \D[5]~84_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~100_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~99_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~q ; +wire \ula_|zx_keyboard_|keys[3][3]~97_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~98_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~q ; +wire \D[3]~73_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~108_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~109_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~110_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~q ; +wire \ula_|zx_keyboard_|keys[6][3]~111_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~112_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~132_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~133_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~q ; +wire \D[3]~75_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~94_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~93_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~95_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~96_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~q ; +wire \ula_|zx_keyboard_|keys[1][3]~91_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~92_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~q ; +wire \D[3]~72_combout ; +wire \D[3]~76_combout ; +wire \D[3]~122_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \D[3]~79_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \D[3]~77_combout ; +wire \D[3]~80_combout ; +wire \D[3]~81_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \D[3]~124_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \D[3]~123_combout ; +wire \D[3]~78_combout ; +wire \D[3]~82_combout ; +wire \D[3]~108_combout ; +wire \D[3]~109_combout ; +wire \z80_|bus_control_|db[3]~20_combout ; +wire \z80_|bus_control_|db[3]~21_combout ; +wire \z80_|pla_decode_|Equal33~1_combout ; +wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; +wire \z80_|bus_control_|db[0]~4_combout ; +wire \z80_|bus_control_|db[7]~5_combout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ; +wire \D[5]~97_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; wire \Mux0~0_combout ; wire \Mux0~1_combout ; -wire \D[7]~112_combout ; -wire \D[7]~94_combout ; -wire \D[7]~102_combout ; -wire \z80_|bus_control_|db[7]~5_combout ; +wire \D[7]~116_combout ; +wire \D[7]~117_combout ; wire \z80_|bus_control_|db[7]~7_combout ; -wire \z80_|pla_decode_|Equal77~0_combout ; -wire \z80_|execute_|ctl_mWrite~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; -wire \z80_|execute_|ctl_bus_db_we~3_combout ; -wire \z80_|execute_|ctl_bus_db_we~8_combout ; -wire \z80_|execute_|ctl_bus_db_we~2_combout ; -wire \z80_|execute_|ctl_bus_db_we~4_combout ; -wire \z80_|execute_|ctl_bus_db_we~6_combout ; -wire \z80_|execute_|ctl_bus_db_we~7_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~50_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~52_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~q ; -wire \ula_|zx_keyboard_|keys[3][3]~48_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~49_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~q ; -wire \D[2]~35_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~57_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~58_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~q ; -wire \ula_|zx_keyboard_|keys[4][2]~59_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~131_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~60_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~q ; -wire \D[2]~37_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~53_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~55_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~56_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~q ; -wire \ula_|zx_keyboard_|keys[3][2]~54_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~q ; -wire \D[2]~36_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~68_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~69_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~70_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~q ; -wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~62_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~64_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~65_combout ; -wire \ula_|zx_keyboard_|Selector13~0_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~66_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~q ; -wire \D[2]~38_combout ; -wire \D[2]~39_combout ; -wire \D[2]~104_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \D[2]~43_combout ; -wire \D[2]~44_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \D[2]~40_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \D[2]~41_combout ; -wire \D[2]~42_combout ; -wire \D[2]~105_combout ; -wire \D[2]~45_combout ; -wire \D[2]~46_combout ; -wire \z80_|bus_control_|db[2]~12_combout ; -wire \z80_|bus_control_|db[2]~13_combout ; -wire \z80_|pla_decode_|Equal3~1_combout ; -wire \z80_|pla_decode_|Equal43~0_combout ; -wire \z80_|interrupts_|test1~2_combout ; -wire \z80_|interrupts_|test1~3_combout ; -wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ; -wire \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ; -wire \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ; -wire \z80_|clk_delay_|hold_clk_iorq~combout ; -wire \z80_|sequencer_|DFFE_T1_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; -wire \z80_|sequencer_|DFFE_T2_ff~q ; -wire \z80_|resets_|x3~combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \z80_|sequencer_|DFFE_M1_ff~q ; -wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M2_ff~q ; -wire \z80_|execute_|ctl_mWrite~3_combout ; -wire \z80_|execute_|nextM~11_combout ; -wire \z80_|execute_|nextM~8_combout ; -wire \z80_|execute_|nextM~9_combout ; -wire \z80_|execute_|nextM~10_combout ; -wire \z80_|execute_|nextM~12_combout ; -wire \z80_|execute_|nextM~15_combout ; -wire \z80_|execute_|nextM~6_combout ; -wire \z80_|execute_|nextM~7_combout ; -wire \z80_|execute_|nextM~13_combout ; -wire \z80_|execute_|setM1~39_combout ; -wire \z80_|execute_|nextM~5_combout ; -wire \z80_|execute_|nextM~14_combout ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|sequencer_|DFFE_T4_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|sequencer_|DFFE_T5_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; -wire \z80_|sequencer_|T6~q ; -wire \z80_|execute_|setM1~13_combout ; -wire \z80_|pla_decode_|Equal77~1_combout ; -wire \z80_|execute_|setM1~12_combout ; -wire \z80_|execute_|setM1~14_combout ; -wire \z80_|execute_|setM1~41_combout ; -wire \z80_|execute_|setM1~42_combout ; -wire \z80_|execute_|setM1~43_combout ; -wire \z80_|execute_|setM1~44_combout ; -wire \z80_|execute_|setM1~50_combout ; -wire \z80_|execute_|setM1~51_combout ; -wire \z80_|execute_|setM1~6_combout ; -wire \z80_|execute_|setM1~7_combout ; -wire \z80_|execute_|setM1~8_combout ; -wire \z80_|execute_|setM1~9_combout ; -wire \z80_|execute_|setM1~10_combout ; -wire \z80_|execute_|setM1~11_combout ; -wire \z80_|execute_|setM1~17_combout ; -wire \z80_|execute_|setM1~31_combout ; -wire \z80_|execute_|setM1~28_combout ; -wire \z80_|execute_|setM1~30_combout ; -wire \z80_|execute_|setM1~32_combout ; -wire \z80_|execute_|setM1~33_combout ; -wire \z80_|execute_|setM1~25_combout ; -wire \z80_|execute_|setM1~26_combout ; -wire \z80_|execute_|setM1~24_combout ; -wire \z80_|execute_|setM1~27_combout ; -wire \z80_|execute_|setM1~22_combout ; -wire \z80_|execute_|setM1~21_combout ; -wire \z80_|execute_|setM1~53_combout ; -wire \z80_|execute_|setM1~23_combout ; -wire \z80_|execute_|setM1~18_combout ; -wire \z80_|execute_|setM1~19_combout ; -wire \z80_|execute_|setM1~20_combout ; -wire \z80_|execute_|setM1~34_combout ; -wire \z80_|execute_|setM1~52_combout ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; -wire \z80_|sequencer_|DFFE_T3_ff~q ; -wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; -wire \z80_|decode_state_|in_halt~0_combout ; -wire \z80_|decode_state_|in_halt~1_combout ; -wire \z80_|decode_state_|in_halt~q ; +wire \z80_|pla_decode_|Equal41~0_combout ; +wire \z80_|pla_decode_|Equal41~1_combout ; +wire \z80_|pla_decode_|Equal41~2_combout ; +wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; +wire \z80_|execute_|ctl_state_tbl_we~8_combout ; +wire \z80_|decode_state_|DFFE_instCB~q ; +wire \z80_|pla_decode_|Equal52~0_combout ; +wire \z80_|execute_|ctl_66_oe~2_combout ; +wire \z80_|interrupts_|im1~q ; +wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; +wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; wire \z80_|execute_|ctl_bus_db_oe~2_combout ; wire \z80_|execute_|ctl_bus_db_oe~5_combout ; wire \z80_|execute_|ctl_bus_db_oe~6_combout ; wire \z80_|execute_|ctl_bus_db_oe~4_combout ; wire \z80_|execute_|ctl_bus_db_oe~combout ; -wire \z80_|bus_control_|db[0]~6_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~93_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~94_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~q ; -wire \ula_|zx_keyboard_|keys[0][3]~96_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~98_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~q ; -wire \D[3]~65_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~99_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~100_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~q ; -wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~133_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~103_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~q ; -wire \D[3]~66_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~105_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~q ; -wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; -wire \ula_|zx_keyboard_|Selector5~1_combout ; -wire \ula_|zx_keyboard_|Selector5~0_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~134_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~135_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~108_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~q ; -wire \D[3]~67_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~112_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~113_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~114_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~q ; -wire \ula_|zx_keyboard_|keys[6][3]~109_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~110_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~137_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~138_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~q ; +wire \ula_|zx_keyboard_|keys[6][0]~88_combout ; +wire \ula_|zx_keyboard_|shifted~1_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~89_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~q ; +wire \ula_|zx_keyboard_|keys[7][0]~84_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~78_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~85_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~86_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~q ; +wire \D[0]~57_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~81_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~82_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~40_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~83_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~q ; +wire \ula_|zx_keyboard_|keys[5][0]~79_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~80_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~q ; +wire \D[0]~56_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~76_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~77_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~q ; +wire \ula_|zx_keyboard_|keys[4][3]~68_combout ; +wire \ula_|zx_keyboard_|WideOr0~0_combout ; +wire \ula_|zx_keyboard_|keys~69_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~70_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~27_combout ; +wire \ula_|zx_keyboard_|WideOr4~0_combout ; +wire \ula_|zx_keyboard_|keys~71_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~72_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~q ; wire \ula_|zx_keyboard_|key_row~2_combout ; -wire \D[3]~68_combout ; -wire \D[3]~69_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \D[3]~73_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; -wire \D[3]~74_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \D[3]~70_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~71_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~72_combout ; -wire \D[3]~108_combout ; -wire \D[3]~95_combout ; -wire \D[3]~96_combout ; -wire \z80_|bus_control_|db[3]~20_combout ; -wire \z80_|bus_control_|db[3]~21_combout ; -wire \z80_|execute_|ctl_mWrite~4_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~22_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~75_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~q ; +wire \ula_|zx_keyboard_|keys[3][1]~24_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~74_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~q ; +wire \D[0]~54_combout ; +wire \D[0]~55_combout ; +wire \D[0]~58_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; +wire \D[0]~62_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \D[0]~63_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \D[0]~59_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \D[0]~60_combout ; +wire \D[0]~61_combout ; +wire \D[0]~120_combout ; +wire \D[0]~64_combout ; +wire \D[0]~65_combout ; +wire \z80_|bus_control_|db[0]~16_combout ; +wire \z80_|bus_control_|db[0]~17_combout ; +wire \z80_|pla_decode_|Equal3~2_combout ; +wire \z80_|execute_|ctl_state_iy_set~2_combout ; +wire \z80_|decode_state_|DFFE_instIY1~q ; +wire \z80_|decode_state_|use_ixiy~combout ; +wire \z80_|execute_|ixy_d~12_combout ; +wire \z80_|execute_|ixy_d~13_combout ; +wire \z80_|execute_|ixy_d~14_combout ; +wire \z80_|execute_|ixy_d~11_combout ; +wire \z80_|execute_|ixy_d~15_combout ; +wire \z80_|execute_|ctl_flags_xy_we~8_combout ; +wire \z80_|execute_|ctl_flags_xy_we~9_combout ; +wire \z80_|execute_|ctl_alu_oe~11_combout ; +wire \z80_|execute_|ctl_alu_oe~12_combout ; +wire \z80_|execute_|ctl_alu_oe~13_combout ; +wire \z80_|execute_|ctl_alu_oe~14_combout ; +wire \z80_|alu_|db[7]~9_combout ; +wire \z80_|alu_|db[1]~15_combout ; +wire \z80_|alu_|db[1]~16_combout ; +wire \z80_|alu_control_|db[1]~25_combout ; +wire \z80_|alu_control_|db[1]~26_combout ; +wire \z80_|sw1_|db_down[1]~2_combout ; +wire \z80_|alu_control_|db[1]~27_combout ; +wire \z80_|bus_control_|db[1]~10_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~41_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~42_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~q ; +wire \ula_|zx_keyboard_|keys[4][1]~30_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~q ; +wire \ula_|zx_keyboard_|key_row~0_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~36_combout ; +wire \ula_|zx_keyboard_|WideOr16~3_combout ; +wire \ula_|zx_keyboard_|WideOr16~0_combout ; +wire \ula_|zx_keyboard_|WideOr16~2_combout ; +wire \ula_|zx_keyboard_|WideOr16~4_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~37_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~q ; +wire \ula_|zx_keyboard_|keys[6][1]~33_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~34_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~31_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~35_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~q ; +wire \D[1]~32_combout ; +wire \D[1]~33_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~16_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~17_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~18_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~q ; +wire \ula_|zx_keyboard_|keys[0][1]~12_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~13_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~10_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~q ; +wire \D[1]~30_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~25_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~26_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~q ; +wire \ula_|zx_keyboard_|keys[2][1]~23_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~q ; +wire \D[1]~31_combout ; +wire \D[1]~34_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \D[1]~38_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \D[1]~39_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \D[1]~35_combout ; +wire \D[1]~36_combout ; +wire \D[1]~37_combout ; +wire \D[1]~118_combout ; +wire \D[1]~40_combout ; +wire \D[1]~41_combout ; +wire \z80_|bus_control_|db[1]~11_combout ; +wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; +wire \z80_|decode_state_|DFFE_instED~q ; +wire \z80_|pla_decode_|Equal6~0_combout ; +wire \z80_|execute_|ctl_mRead~8_combout ; +wire \z80_|execute_|ctl_bus_db_we~2_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; +wire \z80_|execute_|ctl_bus_db_we~3_combout ; +wire \z80_|execute_|ctl_bus_db_we~8_combout ; +wire \z80_|execute_|ctl_bus_db_we~4_combout ; +wire \z80_|execute_|ctl_bus_db_we~6_combout ; +wire \z80_|execute_|ctl_bus_db_we~7_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~126_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~q ; +wire \ula_|zx_keyboard_|keys[7][4]~125_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~q ; +wire \D[4]~88_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~120_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~121_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~q ; +wire \ula_|zx_keyboard_|keys[4][4]~122_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~123_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~q ; +wire \D[4]~87_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~115_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~116_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~117_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~q ; +wire \ula_|zx_keyboard_|key_row~3_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~118_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~131_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~119_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~q ; +wire \ula_|zx_keyboard_|keys[0][4]~114_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~q ; +wire \ula_|zx_keyboard_|keys[1][4]~113_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~q ; +wire \D[4]~85_combout ; +wire \D[4]~86_combout ; +wire \D[4]~89_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; +wire \D[4]~93_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; +wire \D[4]~94_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \D[4]~90_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \D[4]~91_combout ; +wire \D[4]~92_combout ; +wire \D[4]~125_combout ; +wire \D[4]~110_combout ; +wire \D[4]~111_combout ; +wire \z80_|bus_control_|db[4]~18_combout ; +wire \z80_|bus_control_|db[4]~19_combout ; +wire \z80_|pla_decode_|Equal32~0_combout ; +wire \z80_|pla_decode_|Equal36~0_combout ; +wire \z80_|pla_decode_|Equal43~0_combout ; +wire \z80_|interrupts_|test1~2_combout ; +wire \z80_|interrupts_|test1~3_combout ; +wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ; +wire \z80_|sw1_|db_down[5]~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; +wire \z80_|alu_flags_|flags_yf~q ; +wire \z80_|alu_control_|db[5]~15_combout ; +wire \z80_|alu_control_|db[5]~16_combout ; +wire \z80_|alu_control_|db[5]~17_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \Mux2~0_combout ; +wire \Mux2~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ; +wire \D[5]~112_combout ; +wire \D[5]~113_combout ; +wire \z80_|bus_control_|db[5]~14_combout ; +wire \z80_|bus_control_|db[5]~15_combout ; +wire \z80_|execute_|ctl_mRead~11_combout ; +wire \z80_|execute_|setM1~46_combout ; +wire \z80_|execute_|setM1~40_combout ; +wire \z80_|execute_|nextM~5_combout ; +wire \z80_|execute_|nextM~6_combout ; +wire \z80_|execute_|nextM~7_combout ; +wire \z80_|execute_|nextM~9_combout ; +wire \z80_|execute_|nextM~10_combout ; +wire \z80_|execute_|nextM~8_combout ; +wire \z80_|execute_|nextM~12_combout ; +wire \z80_|execute_|nextM~15_combout ; +wire \z80_|execute_|nextM~13_combout ; +wire \z80_|execute_|nextM~14_combout ; +wire \z80_|sequencer_|ena_M~combout ; +wire \z80_|sequencer_|DFFE_T1_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; +wire \z80_|sequencer_|DFFE_T2_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; +wire \z80_|sequencer_|DFFE_T3_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|sequencer_|DFFE_T4_ff~q ; +wire \z80_|execute_|ctl_mWrite~9_combout ; +wire \z80_|execute_|ctl_flags_sz_we~0_combout ; +wire \z80_|execute_|setM1~54_combout ; +wire \z80_|execute_|setM1~25_combout ; +wire \z80_|execute_|setM1~26_combout ; +wire \z80_|execute_|setM1~27_combout ; +wire \z80_|execute_|setM1~22_combout ; +wire \z80_|execute_|setM1~55_combout ; +wire \z80_|execute_|setM1~23_combout ; +wire \z80_|execute_|setM1~24_combout ; +wire \z80_|execute_|setM1~28_combout ; +wire \z80_|execute_|setM1~11_combout ; +wire \z80_|execute_|setM1~33_combout ; +wire \z80_|execute_|setM1~29_combout ; +wire \z80_|execute_|setM1~31_combout ; +wire \z80_|execute_|setM1~32_combout ; +wire \z80_|execute_|setM1~34_combout ; +wire \z80_|execute_|setM1~20_combout ; +wire \z80_|execute_|setM1~21_combout ; +wire \z80_|execute_|setM1~35_combout ; +wire \z80_|execute_|setM1~15_combout ; +wire \z80_|execute_|setM1~14_combout ; +wire \z80_|execute_|setM1~16_combout ; +wire \z80_|execute_|setM1~10_combout ; +wire \z80_|execute_|setM1~12_combout ; +wire \z80_|execute_|setM1~8_combout ; +wire \z80_|execute_|setM1~9_combout ; +wire \z80_|execute_|setM1~13_combout ; +wire \z80_|execute_|setM1~18_combout ; +wire \z80_|execute_|setM1~19_combout ; +wire \z80_|execute_|setM1~43_combout ; +wire \z80_|execute_|setM1~42_combout ; +wire \z80_|execute_|setM1~44_combout ; +wire \z80_|execute_|setM1~45_combout ; +wire \z80_|execute_|setM1~51_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; +wire \z80_|sequencer_|T6~q ; +wire \z80_|execute_|setM1~52_combout ; +wire \z80_|execute_|setM1~53_combout ; +wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M1_ff~q ; +wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~q ; +wire \z80_|execute_|ctl_apin_mux~1_combout ; wire \z80_|execute_|ctl_apin_mux~2_combout ; wire \z80_|address_pins_|DFFE_apin_latch[0]~0_combout ; -wire \D[0]~59_combout ; -wire \D[0]~60_combout ; -wire \D[1]~61_combout ; -wire \D[1]~62_combout ; -wire \D[2]~63_combout ; -wire \D[2]~64_combout ; -wire \D[3]~75_combout ; -wire \D[3]~76_combout ; -wire \D[4]~82_combout ; -wire \D[4]~83_combout ; -wire \D[6]~92_combout ; -wire \D[6]~93_combout ; +wire \D[0]~66_combout ; +wire \D[0]~67_combout ; +wire \D[0]~121_combout ; +wire \D[1]~68_combout ; +wire \D[1]~69_combout ; +wire \D[2]~70_combout ; +wire \D[2]~71_combout ; +wire \D[3]~83_combout ; +wire \D[3]~84_combout ; +wire \D[4]~95_combout ; +wire \D[4]~96_combout ; +wire \D[5]~126_combout ; +wire \D[5]~98_combout ; +wire \D[6]~105_combout ; +wire \D[6]~106_combout ; +wire \D[7]~128_combout ; +wire \D[7]~107_combout ; +wire \z80_|memory_ifc_|nIORQ_out~0_combout ; wire \z80_|nM1_int~3_combout ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ; @@ -2482,26 +2541,43 @@ wire \z80_|memory_ifc_|DFFE_mreq_ff2~q ; wire \z80_|memory_ifc_|nMREQ_out~0_combout ; wire \z80_|memory_ifc_|nMREQ_out~1_combout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ; -wire \ula_|i2c_loader_|state.Idle~feeder_combout ; wire \ula_|i2c_loader_|divider[0]~15_combout ; wire \ula_|i2c_loader_|divider[1]~5_combout ; wire \ula_|i2c_loader_|divider[1]~6 ; wire \ula_|i2c_loader_|divider[2]~7_combout ; wire \ula_|i2c_loader_|divider[2]~8 ; wire \ula_|i2c_loader_|divider[3]~9_combout ; +wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|divider[3]~10 ; wire \ula_|i2c_loader_|divider[4]~11_combout ; wire \ula_|i2c_loader_|divider[4]~12 ; wire \ula_|i2c_loader_|divider[5]~13_combout ; -wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|WideAnd0~combout ; +wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; +wire \ula_|i2c_loader_|state.Idle~feeder_combout ; wire \ula_|i2c_loader_|state.Idle~q ; wire \ula_|i2c_loader_|phase~0_combout ; wire \ula_|i2c_loader_|phase~1_combout ; -wire \ula_|i2c_loader_|nbit~5_combout ; -wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; wire \ula_|i2c_loader_|Mux42~0_combout ; +wire \ula_|i2c_loader_|nbyte~0_combout ; +wire \ula_|i2c_loader_|nbit~4_combout ; wire \ula_|i2c_loader_|nbyte~4_combout ; +wire \ula_|i2c_loader_|nbit[0]~1_combout ; +wire \ula_|i2c_loader_|nbit[0]~2_combout ; +wire \ula_|i2c_loader_|nbit[0]~3_combout ; +wire \ula_|i2c_loader_|nbit~5_combout ; +wire \ula_|i2c_loader_|state.Pause~1_combout ; +wire \ula_|i2c_loader_|state~27_combout ; +wire \ula_|i2c_loader_|state~24_combout ; +wire \ula_|i2c_loader_|state~26_combout ; +wire \ula_|i2c_loader_|state.Data~0_combout ; +wire \ula_|i2c_loader_|state.Data~q ; +wire \ula_|i2c_loader_|nbit~0_combout ; +wire \ula_|i2c_loader_|state.Pause~0_combout ; +wire \ula_|i2c_loader_|state.Idle~0_combout ; +wire \ula_|i2c_loader_|state.Ack~0_combout ; +wire \ula_|i2c_loader_|state.Ack~1_combout ; +wire \ula_|i2c_loader_|state.Ack~q ; wire \ula_|i2c_loader_|thisbyte[0]~7_combout ; wire \I2C_SDAT~input_o ; wire \ula_|i2c_loader_|nbyte[0]~1_combout ; @@ -2510,12 +2586,8 @@ wire \ula_|i2c_loader_|nbyte[0]~3_combout ; wire \ula_|i2c_loader_|state.Stop~0_combout ; wire \ula_|i2c_loader_|state.Stop~1_combout ; wire \ula_|i2c_loader_|state.Stop~q ; -wire \ula_|i2c_loader_|state.Idle~0_combout ; -wire \ula_|i2c_loader_|nbit~0_combout ; -wire \ula_|i2c_loader_|state.Done~0_combout ; -wire \ula_|i2c_loader_|state.Ack~0_combout ; -wire \ula_|i2c_loader_|state.Ack~1_combout ; -wire \ula_|i2c_loader_|state.Ack~q ; +wire \ula_|i2c_loader_|state.Pause~2_combout ; +wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; wire \ula_|i2c_loader_|nbyte[1]~5_combout ; wire \ula_|i2c_loader_|thisbyte[0]~18_combout ; wire \ula_|i2c_loader_|thisbyte[0]~9 ; @@ -2525,56 +2597,43 @@ wire \ula_|i2c_loader_|thisbyte[2]~12_combout ; wire \ula_|i2c_loader_|thisbyte[2]~13 ; wire \ula_|i2c_loader_|thisbyte[3]~14_combout ; wire \ula_|i2c_loader_|Equal2~0_combout ; -wire \ula_|i2c_loader_|state.Pause~0_combout ; wire \ula_|i2c_loader_|thisbyte[3]~15 ; wire \ula_|i2c_loader_|thisbyte[4]~16_combout ; -wire \ula_|i2c_loader_|state.Pause~1_combout ; -wire \ula_|i2c_loader_|state.Done~2_combout ; -wire \ula_|i2c_loader_|state.Pause~2_combout ; wire \ula_|i2c_loader_|state.Pause~3_combout ; +wire \ula_|i2c_loader_|scl_out~0_combout ; +wire \ula_|i2c_loader_|state.Pause~4_combout ; +wire \ula_|i2c_loader_|state.Pause~5_combout ; +wire \ula_|i2c_loader_|state.Pause~6_combout ; wire \ula_|i2c_loader_|state.Pause~q ; wire \ula_|i2c_loader_|state~25_combout ; wire \ula_|i2c_loader_|state.Start~q ; -wire \ula_|i2c_loader_|nbyte~0_combout ; -wire \ula_|i2c_loader_|nbit[0]~1_combout ; -wire \ula_|i2c_loader_|nbit[0]~2_combout ; -wire \ula_|i2c_loader_|nbit[0]~3_combout ; -wire \ula_|i2c_loader_|nbit[0]~4_combout ; -wire \ula_|i2c_loader_|nbit~6_combout ; -wire \ula_|i2c_loader_|state.Done~1_combout ; -wire \ula_|i2c_loader_|state~27_combout ; -wire \ula_|i2c_loader_|state~24_combout ; -wire \ula_|i2c_loader_|state~26_combout ; -wire \ula_|i2c_loader_|state.Data~0_combout ; -wire \ula_|i2c_loader_|state.Data~q ; -wire \ula_|i2c_loader_|scl_out~0_combout ; -wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; wire \ula_|i2c_loader_|scl_out~1_combout ; wire \ula_|i2c_loader_|scl_out~2_combout ; wire \ula_|i2c_loader_|scl_out~q ; wire \ula_|i2c_loader_|sda_out~_Duplicate_1_q ; -wire \ula_|i2c_loader_|shiftreg~4_combout ; wire \ula_|i2c_loader_|Mux35~0_combout ; -wire \ula_|i2c_loader_|shiftreg~13_combout ; -wire \ula_|i2c_loader_|shiftreg~14_combout ; -wire \ula_|i2c_loader_|shiftreg~15_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~24_combout ; +wire \ula_|i2c_loader_|shiftreg~4_combout ; +wire \ula_|i2c_loader_|shiftreg~19_combout ; +wire \ula_|i2c_loader_|shiftreg~20_combout ; +wire \ula_|i2c_loader_|shiftreg~22_combout ; +wire \ula_|i2c_loader_|shiftreg~23_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~25_combout ; wire \ula_|i2c_loader_|shiftreg[0]~6_combout ; wire \ula_|i2c_loader_|shiftreg[0]~7_combout ; wire \ula_|i2c_loader_|shiftreg[0]~8_combout ; -wire \ula_|i2c_loader_|shiftreg~21_combout ; -wire \ula_|i2c_loader_|shiftreg~22_combout ; -wire \ula_|i2c_loader_|shiftreg~23_combout ; +wire \ula_|i2c_loader_|shiftreg~24_combout ; wire \ula_|i2c_loader_|shiftreg[6]~10_combout ; wire \ula_|i2c_loader_|shiftreg[6]~11_combout ; -wire \ula_|i2c_loader_|shiftreg~18_combout ; -wire \ula_|i2c_loader_|shiftreg~19_combout ; -wire \ula_|i2c_loader_|shiftreg~20_combout ; -wire \ula_|i2c_loader_|shiftreg~16_combout ; +wire \ula_|i2c_loader_|shiftreg[6]~12_combout ; +wire \ula_|i2c_loader_|shiftreg~21_combout ; wire \ula_|i2c_loader_|shiftreg~17_combout ; +wire \ula_|i2c_loader_|shiftreg~15_combout ; +wire \ula_|i2c_loader_|shiftreg~18_combout ; +wire \ula_|i2c_loader_|shiftreg~27_combout ; +wire \ula_|i2c_loader_|shiftreg~14_combout ; +wire \ula_|i2c_loader_|shiftreg~16_combout ; wire \ula_|i2c_loader_|shiftreg~26_combout ; -wire \ula_|i2c_loader_|shiftreg~25_combout ; -wire \ula_|i2c_loader_|shiftreg~12_combout ; +wire \ula_|i2c_loader_|shiftreg~13_combout ; wire \ula_|i2c_loader_|shiftreg~9_combout ; wire \ula_|i2c_loader_|shiftreg[7]~5_combout ; wire \ula_|i2c_loader_|sda_out~0_combout ; @@ -2583,6 +2642,142 @@ wire \ula_|i2c_loader_|sda_out~2_combout ; wire \ula_|i2c_loader_|sda_out~3_combout ; wire \ula_|i2c_loader_|sda_out~4_combout ; wire \ula_|i2c_loader_|sda_out~q ; +wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_fbout ; +wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \sdram_|Mux38~0_combout ; +wire \sdram_|r.rd_pending~q ; +wire \sdram_|r.rf_counter[0]~12_combout ; +wire \sdram_|r.rf_counter[3]~32_combout ; +wire \sdram_|r.rf_counter[0]~13 ; +wire \sdram_|r.rf_counter[1]~14_combout ; +wire \sdram_|r.rf_counter[1]~15 ; +wire \sdram_|r.rf_counter[2]~16_combout ; +wire \sdram_|r.rf_counter[2]~17 ; +wire \sdram_|r.rf_counter[3]~18_combout ; +wire \sdram_|r.rf_counter[3]~19 ; +wire \sdram_|r.rf_counter[4]~20_combout ; +wire \sdram_|r.rf_counter[4]~21 ; +wire \sdram_|r.rf_counter[5]~22_combout ; +wire \sdram_|r.rf_counter[5]~23 ; +wire \sdram_|r.rf_counter[6]~24_combout ; +wire \sdram_|r.rf_counter[6]~25 ; +wire \sdram_|r.rf_counter[7]~26_combout ; +wire \sdram_|Equal0~1_combout ; +wire \sdram_|r.rf_counter[7]~27 ; +wire \sdram_|r.rf_counter[8]~28_combout ; +wire \sdram_|Equal0~0_combout ; +wire \sdram_|r.rf_counter[8]~29 ; +wire \sdram_|r.rf_counter[9]~30_combout ; +wire \sdram_|Equal0~2_combout ; +wire \sdram_|Mux13~8_combout ; +wire \sdram_|Mux37~0_combout ; +wire \sdram_|r.rf_pending~q ; +wire \sdram_|Mux4~0_combout ; +wire \sdram_|Mux4~1_combout ; +wire \sdram_|Mux4~2_combout ; +wire \sdram_|Mux4~3_combout ; +wire \sdram_|r.act_row[1]~0_combout ; +wire \sdram_|process_0~2_combout ; +wire \sdram_|r.act_row[1]~1_combout ; +wire \sdram_|r.act_row[2]~feeder_combout ; +wire \sdram_|Equal7~1_combout ; +wire \sdram_|Equal7~0_combout ; +wire \sdram_|Equal7~2_combout ; +wire \sdram_|Mux39~0_combout ; +wire \sdram_|Mux39~1_combout ; +wire \sdram_|Mux39~2_combout ; +wire \sdram_|r.wr_pending~q ; +wire \sdram_|Mux9~8_combout ; +wire \sdram_|Mux9~9_combout ; +wire \sdram_|Mux6~3_combout ; +wire \sdram_|Mux6~4_combout ; +wire \sdram_|Mux6~2_combout ; +wire \sdram_|Mux6~5_combout ; +wire \sdram_|process_0~3_combout ; +wire \sdram_|Mux6~0_combout ; +wire \sdram_|Mux6~1_combout ; +wire \sdram_|Mux6~6_combout ; +wire \sdram_|r.address[3]~6_combout ; +wire \sdram_|Mux7~2_combout ; +wire \sdram_|n~3_combout ; +wire \sdram_|Mux7~3_combout ; +wire \sdram_|Mux7~4_combout ; +wire \sdram_|Mux7~5_combout ; +wire \sdram_|Mux23~0_combout ; +wire \sdram_|Mux13~7_combout ; +wire \sdram_|Mux10~10_combout ; +wire \sdram_|Mux7~1_combout ; +wire \sdram_|Mux7~6_combout ; +wire \sdram_|Mux5~2_combout ; +wire \sdram_|Mux5~10_combout ; +wire \sdram_|Mux5~3_combout ; +wire \sdram_|Mux5~4_combout ; +wire \sdram_|Mux5~7_combout ; +wire \sdram_|Mux5~8_combout ; +wire \sdram_|Mux5~5_combout ; +wire \sdram_|Mux5~6_combout ; +wire \sdram_|Mux5~9_combout ; +wire \sdram_|n~2_combout ; +wire \sdram_|Mux8~3_combout ; +wire \sdram_|Mux8~4_combout ; +wire \sdram_|Mux9~10_combout ; +wire \sdram_|r.init_counter[0]~0_combout ; +wire \sdram_|Add1~1_cout ; +wire \sdram_|Add1~2_combout ; +wire \sdram_|Add1~3 ; +wire \sdram_|Add1~4_combout ; +wire \sdram_|Add1~5 ; +wire \sdram_|Add1~6_combout ; +wire \sdram_|r.init_counter[3]~1_combout ; +wire \sdram_|Add1~7 ; +wire \sdram_|Add1~8_combout ; +wire \sdram_|Add1~9 ; +wire \sdram_|Add1~10_combout ; +wire \sdram_|Add1~11 ; +wire \sdram_|Add1~12_combout ; +wire \sdram_|Add1~13 ; +wire \sdram_|Add1~14_combout ; +wire \sdram_|Add1~15 ; +wire \sdram_|Add1~16_combout ; +wire \sdram_|Add1~17 ; +wire \sdram_|Add1~18_combout ; +wire \sdram_|Add1~19 ; +wire \sdram_|Add1~20_combout ; +wire \sdram_|Equal2~0_combout ; +wire \sdram_|Equal2~1_combout ; +wire \sdram_|Add1~21 ; +wire \sdram_|Add1~22_combout ; +wire \sdram_|Add1~23 ; +wire \sdram_|Add1~24_combout ; +wire \sdram_|Add1~25 ; +wire \sdram_|Add1~26_combout ; +wire \sdram_|Add1~27 ; +wire \sdram_|Add1~28_combout ; +wire \sdram_|process_0~5_combout ; +wire \sdram_|Equal2~2_combout ; +wire \sdram_|Mux9~11_combout ; +wire \sdram_|Mux9~12_combout ; +wire \sdram_|Mux9~13_combout ; +wire \sdram_|Mux8~0_combout ; +wire \sdram_|Mux8~1_combout ; +wire \sdram_|Mux8~2_combout ; +wire \sdram_|Mux72~0_combout ; +wire \sdram_|Mux72~1_combout ; +wire \sdram_|Mux84~0_combout ; +wire \sdram_|Mux84~1_combout ; +wire \sdram_|Mux3~0_combout ; +wire \sdram_|Mux3~1_combout ; +wire \sdram_|Mux2~0_combout ; +wire \sdram_|Mux2~1_combout ; +wire \sdram_|Mux1~0_combout ; +wire \sdram_|Mux1~1_combout ; +wire \sdram_|Mux0~0_combout ; +wire \sdram_|Mux0~1_combout ; +wire \sdram_|Mux73~0_combout ; +wire \sdram_|Mux73~1_combout ; +wire \sdram_|Mux74~0_combout ; +wire \sdram_|Mux74~1_combout ; +wire \sdram_|Mux75~0_combout ; wire \ula_|i2s_intf_|mclk_r~0_combout ; wire \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|mclk_r~q ; @@ -2616,12 +2811,13 @@ wire \ula_|i2s_intf_|Add0~18_combout ; wire \ula_|i2s_intf_|lrdivider[9]~3_combout ; wire \ula_|i2s_intf_|Equal0~0_combout ; wire \ula_|i2s_intf_|Equal0~2_combout ; -wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; wire \ula_|i2s_intf_|lrclk_r~0_combout ; wire \ula_|i2s_intf_|lrclk_r~q ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_1_q ; +wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|bitcount[0]~5_combout ; +wire \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ; wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|bitcount[4]~15_combout ; wire \ula_|i2s_intf_|bitcount[0]~6 ; @@ -2630,9 +2826,10 @@ wire \ula_|i2s_intf_|bitcount[1]~8 ; wire \ula_|i2s_intf_|bitcount[2]~9_combout ; wire \ula_|i2s_intf_|bitcount[2]~10 ; wire \ula_|i2s_intf_|bitcount[3]~11_combout ; -wire \ula_|i2s_intf_|LessThan0~0_combout ; wire \ula_|i2s_intf_|bitcount[3]~12 ; wire \ula_|i2s_intf_|bitcount[4]~13_combout ; +wire \ula_|i2s_intf_|LessThan0~0_combout ; +wire \ula_|i2s_intf_|shiftreg[1]~1_combout ; wire \ula_|i2s_intf_|Add2~7_cout ; wire \ula_|i2s_intf_|Add2~8_combout ; wire \ula_|i2s_intf_|Add2~20_combout ; @@ -2646,8 +2843,6 @@ wire \ula_|i2s_intf_|Add2~13 ; wire \ula_|i2s_intf_|Add2~14_combout ; wire \ula_|i2s_intf_|Add2~16_combout ; wire \ula_|i2s_intf_|Equal1~0_combout ; -wire \ula_|i2s_intf_|shiftreg[4]~1_combout ; -wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|Equal1~1_combout ; wire \ula_|i2s_intf_|bclk_r~0_combout ; wire \ula_|i2s_intf_|bclk_r~1_combout ; @@ -2659,7 +2854,7 @@ wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; wire \AUD_ADCDAT~input_o ; wire \ula_|i2s_intf_|shiftreg[0]~20_combout ; wire \ula_|i2s_intf_|shiftreg~18_combout ; -wire \ula_|i2s_intf_|shiftreg[4]~2_combout ; +wire \ula_|i2s_intf_|shiftreg[1]~2_combout ; wire \ula_|i2s_intf_|shiftreg~17_combout ; wire \ula_|i2s_intf_|shiftreg~16_combout ; wire \ula_|i2s_intf_|shiftreg~15_combout ; @@ -2676,28 +2871,20 @@ wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; wire \ula_|pcm_outr~0_combout ; wire \ula_|i2s_intf_|shiftreg~6_combout ; wire \ula_|i2s_intf_|shiftreg~5_combout ; +wire \ula_|pcm_outl[14]~feeder_combout ; wire \ula_|i2s_intf_|shiftreg~4_combout ; wire \ula_|i2s_intf_|shiftreg~3_combout ; wire \ula_|i2s_intf_|shiftreg~0_combout ; -wire \ula_|video_|LessThan2~0_combout ; +wire \ula_|border[1]~feeder_combout ; wire \ula_|video_|LessThan6~0_combout ; -wire \ula_|video_|LessThan2~1_combout ; -wire \ula_|video_|LessThan3~0_combout ; -wire \ula_|video_|LessThan0~0_combout ; -wire \ula_|video_|disp_enable~0_combout ; -wire \ula_|video_|disp_enable~1_combout ; wire \ula_|video_|LessThan6~1_combout ; wire \ula_|video_|LessThan4~0_combout ; wire \ula_|video_|screen_en~0_combout ; wire \ula_|video_|screen_en~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; -wire \ula_|video_|attr_prefetch[1]~feeder_combout ; -wire \ula_|video_|Decoder0~1_combout ; -wire \ula_|video_|Decoder0~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; -wire \ula_|video_|attr_prefetch[4]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; wire \ula_|video_|attr_prefetch[7]~feeder_combout ; +wire \ula_|video_|Decoder0~1_combout ; +wire \ula_|video_|Decoder0~0_combout ; wire \ula_|video_|frame[0]~12_combout ; wire \ula_|video_|frame[1]~4_combout ; wire \ula_|video_|frame[1]~5 ; @@ -2710,7 +2897,7 @@ wire \ula_|video_|inverted~combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[6]~feeder_combout ; wire \ula_|video_|Decoder0~2_combout ; -wire \ula_|video_|bits[6]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[4]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[5]~feeder_combout ; @@ -2723,25 +2910,35 @@ wire \ula_|video_|bits_prefetch[2]~feeder_combout ; wire \ula_|video_|bits[2]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[0]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[1]~feeder_combout ; wire \ula_|video_|bits[1]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[3]~feeder_combout ; wire \ula_|video_|Mux0~2_combout ; wire \ula_|video_|Mux0~3_combout ; -wire \ula_|video_|cindex[1]~0_combout ; +wire \ula_|video_|cindex[2]~0_combout ; +wire \ula_|video_|attr_prefetch[4]~feeder_combout ; +wire \ula_|video_|attr_prefetch[1]~feeder_combout ; wire \ula_|video_|cindex[1]~1_combout ; +wire \ula_|video_|LessThan2~0_combout ; +wire \ula_|video_|LessThan2~1_combout ; +wire \ula_|video_|LessThan3~0_combout ; +wire \ula_|video_|LessThan0~0_combout ; +wire \ula_|video_|disp_enable~0_combout ; +wire \ula_|video_|disp_enable~1_combout ; wire \ula_|video_|VGA_R[0]~0_combout ; wire \ula_|video_|attr_prefetch[6]~feeder_combout ; wire \ula_|video_|VGA_B[1]~0_combout ; wire \ula_|video_|VGA_R[1]~1_combout ; -wire \ula_|video_|attr_prefetch[2]~feeder_combout ; +wire \ula_|border[2]~feeder_combout ; wire \ula_|video_|attr_prefetch[5]~feeder_combout ; +wire \ula_|video_|attr_prefetch[2]~feeder_combout ; wire \ula_|video_|cindex[2]~2_combout ; wire \ula_|video_|VGA_G[0]~0_combout ; wire \ula_|video_|VGA_G[1]~1_combout ; +wire \ula_|border[0]~feeder_combout ; wire \ula_|video_|attr_prefetch[0]~feeder_combout ; -wire \ula_|video_|attr[0]~feeder_combout ; wire \ula_|video_|attr_prefetch[3]~feeder_combout ; wire \ula_|video_|cindex[0]~3_combout ; wire \ula_|video_|VGA_B[0]~1_combout ; @@ -2760,23 +2957,171 @@ wire \z80_|memory_ifc_|nRFSH_out~0_combout ; wire \z80_|memory_ifc_|nM1_out~combout ; wire \ula_|beep~0_combout ; wire \ula_|beep~q ; -wire [0:0] \ram0|altsyncram_component|auto_generated|address_reg_a ; +wire \sdram_|Mux26~4_combout ; +wire \sdram_|r.bank[0]~7_combout ; +wire \sdram_|r.bank[0]~11_combout ; +wire \sdram_|r.bank[0]~4_combout ; +wire \sdram_|r.bank[0]~5_combout ; +wire \sdram_|r.bank[0]~6_combout ; +wire \sdram_|r.bank[0]~8_combout ; +wire \sdram_|r.bank[0]~12_combout ; +wire \sdram_|r.bank[0]~9_combout ; +wire \sdram_|Mux25~4_combout ; +wire \sdram_|Mux24~5_combout ; +wire \sdram_|Mux71~0_combout ; +wire \sdram_|process_0~7_combout ; +wire \sdram_|process_0~4_combout ; +wire \sdram_|Mux71~1_combout ; +wire \sdram_|Mux71~2_combout ; +wire \sdram_|Mux71~3_combout ; +wire \sdram_|Mux71~4_combout ; +wire \sdram_|r.bank[0]~10_combout ; +wire \sdram_|Mux9~3_combout ; +wire \sdram_|n~5_combout ; +wire \sdram_|Mux9~4_combout ; +wire \sdram_|Mux9~2_combout ; +wire \sdram_|Equal2~3_combout ; +wire \sdram_|Mux10~2_combout ; +wire \sdram_|Mux10~3_combout ; +wire \sdram_|process_0~6_combout ; +wire \sdram_|Mux10~4_combout ; +wire \sdram_|Mux9~5_combout ; +wire \sdram_|Mux7~0_combout ; +wire \sdram_|Mux9~6_combout ; +wire \sdram_|Mux9~7_combout ; +wire \sdram_|Mux10~11_combout ; +wire \sdram_|Mux10~6_combout ; +wire \sdram_|Mux10~5_combout ; +wire \sdram_|Mux10~7_combout ; +wire \sdram_|Mux10~8_combout ; +wire \sdram_|Mux10~9_combout ; +wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK_outclk ; +wire \sdram_|Mux11~2_combout ; +wire \sdram_|Mux11~3_combout ; +wire \sdram_|Mux11~4_combout ; +wire \sdram_|Mux11~5_combout ; +wire \sdram_|Mux11~6_combout ; +wire \sdram_|Mux11~7_combout ; +wire \sdram_|Mux11~9_combout ; +wire \sdram_|Mux11~8_combout ; +wire \sdram_|Mux24~2_combout ; +wire \sdram_|r.address[0]~7_combout ; +wire \sdram_|r.address[0]~0_combout ; +wire \sdram_|Mux13~9_combout ; +wire \sdram_|Mux13~4_combout ; +wire \sdram_|Mux13~5_combout ; +wire \sdram_|r.address[0]~_Duplicate_1_q ; +wire \sdram_|Mux24~3_combout ; +wire \sdram_|Mux24~4_combout ; +wire \sdram_|r.address[0]~SLOAD_MUX_combout ; +wire \sdram_|r.address[1]~_Duplicate_1feeder_combout ; +wire \sdram_|Mux23~4_combout ; +wire \sdram_|Equal5~0_combout ; +wire \sdram_|Mux23~5_combout ; +wire \sdram_|Mux23~6_combout ; +wire \sdram_|Mux19~0_combout ; +wire \sdram_|r.address[1]~_Duplicate_1_q ; +wire \sdram_|Mux23~2_combout ; +wire \sdram_|Mux23~3_combout ; +wire \sdram_|Mux23~1_combout ; +wire \sdram_|r.address[1]~1_combout ; +wire \sdram_|r.address[1]~SLOAD_MUX_combout ; +wire \sdram_|r.address[3]~8_combout ; +wire \sdram_|r.address[3]~9_combout ; +wire \sdram_|Mux21~0_combout ; +wire \sdram_|Mux22~0_combout ; +wire \sdram_|r.address[3]~10_combout ; +wire \sdram_|r.address[3]~11_combout ; +wire \sdram_|r.address[3]~12_combout ; +wire \sdram_|r.address[3]~13_combout ; +wire \sdram_|r.address[3]~14_combout ; +wire \sdram_|r.address[3]~15_combout ; +wire \sdram_|r.address[3]~16_combout ; +wire \sdram_|r.address[3]~17_combout ; +wire \sdram_|Mux21~1_combout ; +wire \sdram_|Mux20~4_combout ; +wire \sdram_|Mux20~7_combout ; +wire \sdram_|Mux23~7_combout ; +wire \sdram_|Mux20~8_combout ; +wire \sdram_|Mux20~10_combout ; +wire \sdram_|Mux20~9_combout ; +wire \sdram_|Mux20~11_combout ; +wire \sdram_|r.address[4]~_Duplicate_1_q ; +wire \sdram_|Mux20~12_combout ; +wire \sdram_|Mux20~5_combout ; +wire \sdram_|Mux20~6_combout ; +wire \sdram_|r.address[4]~2_combout ; +wire \sdram_|r.address[4]~SLOAD_MUX_combout ; +wire \sdram_|Mux19~1_combout ; +wire \sdram_|Mux19~4_combout ; +wire \sdram_|Mux19~5_combout ; +wire \sdram_|Mux19~6_combout ; +wire \sdram_|Mux19~7_combout ; +wire \sdram_|r.address[5]~_Duplicate_1_q ; +wire \sdram_|Mux19~2_combout ; +wire \sdram_|Mux19~3_combout ; +wire \sdram_|r.address[5]~3_combout ; +wire \sdram_|r.address[5]~SLOAD_MUX_combout ; +wire \sdram_|Mux18~0_combout ; +wire \sdram_|Mux17~0_combout ; +wire \sdram_|Mux16~0_combout ; +wire \sdram_|Mux15~2_combout ; +wire \sdram_|Mux14~0_combout ; +wire \sdram_|Mux14~1_combout ; +wire \sdram_|r.address[10]~4_combout ; +wire \sdram_|r.address[10]~_Duplicate_1_q ; +wire \sdram_|n~4_combout ; +wire \sdram_|Mux14~2_combout ; +wire \sdram_|Mux14~3_combout ; +wire \sdram_|r.address[10]~SLOAD_MUX_combout ; +wire \sdram_|r.address[11]~18_combout ; +wire \sdram_|r.address[11]~5_combout ; +wire \sdram_|r.address[11]~_Duplicate_2feeder_combout ; +wire \sdram_|r.address[11]~_Duplicate_2_q ; +wire \sdram_|Mux13~10_combout ; +wire \sdram_|Mux13~6_combout ; +wire \sdram_|r.address[11]~SLOAD_MUX_combout ; +wire \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout ; +wire \sdram_|r.address[11]~_Duplicate_1_q ; +wire [9:0] \sdram_|r.rf_counter ; +wire [12:0] \sdram_|r.address ; +wire [15:0] \ula_|pcm_outl ; +wire [1:0] \ula_|i2c_loader_|nbyte ; +wire [4:0] \ula_|i2s_intf_|bitcount ; +wire [4:0] \ula_|video_|frame ; +wire [7:0] \ula_|video_|attr_prefetch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_ix_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_pc_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_wz_hi|latch ; wire [1:0] \ram1|altsyncram_component|auto_generated|address_reg_a ; -wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode244w ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode223w ; +wire [3:0] \z80_|alu_|op2_low ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; +wire [15:0] \z80_|address_latch_|abusz ; +wire [7:0] \z80_|data_pins_|dout ; +wire [8:0] \sdram_|r.state ; +wire [14:0] \sdram_|r.init_counter ; +wire [1:0] \sdram_|r.bank ; +wire [12:0] \sdram_|r.act_row ; wire [2:0] \ula_|border ; wire [0:0] \ula_|clocks_|counter ; -wire [7:0] \ula_|i2c_loader_|shiftreg ; -wire [1:0] \ula_|i2c_loader_|nbyte ; -wire [5:0] \ula_|i2c_loader_|divider ; -wire [17:0] \ula_|i2s_intf_|shiftreg ; -wire [4:0] \ula_|i2s_intf_|bitcount ; -wire [15:0] \ula_|i2s_intf_|PCM_INR ; -wire [9:0] \ula_|video_|vga_vc ; -wire [4:0] \ula_|video_|frame ; -wire [7:0] \ula_|video_|bits_prefetch ; -wire [7:0] \ula_|video_|attr_prefetch ; -wire [7:0] \ula_|ps2_keyboard_|clk_filter ; +wire [4:0] \ula_|i2c_loader_|thisbyte ; +wire [1:0] \ula_|i2c_loader_|phase ; +wire [2:0] \ula_|i2c_loader_|nbit ; +wire [9:0] \ula_|i2s_intf_|lrdivider ; +wire [4:0] \ula_|i2s_intf_|bdivider ; +wire [15:0] \ula_|i2s_intf_|PCM_INL ; +wire [12:0] \ula_|video_|vram_address ; +wire [9:0] \ula_|video_|vga_hc ; +wire [7:0] \ula_|video_|bits ; +wire [7:0] \ula_|video_|attr ; +wire [8:0] \ula_|ps2_keyboard_|shiftreg ; +wire [3:0] \ula_|ps2_keyboard_|bit_count ; wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; @@ -2790,126 +3135,119 @@ wire [7:0] \z80_|reg_file_|b2v_latch_iy_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_pc_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_sp_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; -wire [3:0] \z80_|alu_|op2_low ; -wire [3:0] \z80_|alu_|op1_low ; -wire [15:0] \z80_|address_latch_|Q ; -wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; -wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; -wire [7:0] \z80_|data_pins_|dout ; -wire [7:0] \z80_|ir_|opcode ; wire [0:0] \ram0|altsyncram_component|auto_generated|out_address_reg_a ; wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode252w ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode236w ; -wire [15:0] \ula_|pcm_outl ; -wire [4:0] \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk ; -wire [4:0] \ula_|i2c_loader_|thisbyte ; -wire [1:0] \ula_|i2c_loader_|phase ; -wire [2:0] \ula_|i2c_loader_|nbit ; -wire [9:0] \ula_|i2s_intf_|lrdivider ; -wire [4:0] \ula_|i2s_intf_|bdivider ; -wire [15:0] \ula_|i2s_intf_|PCM_INL ; -wire [12:0] \ula_|video_|vram_address ; -wire [9:0] \ula_|video_|vga_hc ; -wire [7:0] \ula_|video_|bits ; -wire [7:0] \ula_|video_|attr ; -wire [8:0] \ula_|ps2_keyboard_|shiftreg ; -wire [3:0] \ula_|ps2_keyboard_|bit_count ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_ix_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_iy_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_pc_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_sp_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_wz_hi|latch ; wire [3:0] \z80_|alu_|result_lo ; wire [3:0] \z80_|alu_|op2_high ; wire [3:0] \z80_|alu_|op1_high ; wire [3:0] \z80_|alu_|b2v_op1_latch_mux_high|Q ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; -wire [15:0] \z80_|address_latch_|abusz ; +wire [15:0] \z80_|address_latch_|Q ; +wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; +wire [7:0] \z80_|ir_|opcode ; +wire [1:0] \sdram_|r.dq_masks ; +wire [4:0] \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk ; +wire [4:0] \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk ; +wire [7:0] \ula_|i2c_loader_|shiftreg ; +wire [5:0] \ula_|i2c_loader_|divider ; +wire [17:0] \ula_|i2s_intf_|shiftreg ; +wire [15:0] \ula_|i2s_intf_|PCM_INR ; +wire [9:0] \ula_|video_|vga_vc ; +wire [7:0] \ula_|video_|bits_prefetch ; +wire [7:0] \ula_|ps2_keyboard_|clk_filter ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_iy_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_sp_hi|latch ; +wire [0:0] \ram0|altsyncram_component|auto_generated|address_reg_a ; +wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode244w ; +wire [3:0] \z80_|alu_|op1_low ; +wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; +wire [4:0] \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus ; wire [4:0] \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; + +assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [0] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [1] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [2] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [3] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [4] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [4]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [0] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [0]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [1] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [1]; @@ -2917,24 +3255,24 @@ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [2] = \ula_|pll_ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [3] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [3]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [4] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [4]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; - assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0]; @@ -2947,12 +3285,12 @@ assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; @@ -2965,55 +3303,47 @@ assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \r assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; @@ -3025,6 +3355,14 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0]; @@ -3037,19 +3375,11 @@ assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; @@ -3061,6 +3391,14 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; + // Location: IOOBUF_X53_Y21_N23 cycloneive_io_obuf \GPIO_1[0]~output ( .i(\z80_|address_pins_|DFFE_apin_latch [0]), @@ -3271,8 +3609,8 @@ defparam \GPIO_1[15]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N9 cycloneive_io_obuf \GPIO_1[16]~output ( - .i(\D[0]~60_combout ), - .oe(\D[0]~107_combout ), + .i(\D[0]~67_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[16]), @@ -3284,8 +3622,8 @@ defparam \GPIO_1[16]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y12_N2 cycloneive_io_obuf \GPIO_1[17]~output ( - .i(\D[1]~62_combout ), - .oe(\D[0]~107_combout ), + .i(\D[1]~69_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[17]), @@ -3297,8 +3635,8 @@ defparam \GPIO_1[17]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y8_N23 cycloneive_io_obuf \GPIO_1[18]~output ( - .i(\D[2]~64_combout ), - .oe(\D[0]~107_combout ), + .i(\D[2]~71_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[18]), @@ -3310,8 +3648,8 @@ defparam \GPIO_1[18]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N2 cycloneive_io_obuf \GPIO_1[19]~output ( - .i(\D[3]~76_combout ), - .oe(\D[0]~107_combout ), + .i(\D[3]~84_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[19]), @@ -3323,8 +3661,8 @@ defparam \GPIO_1[19]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y6_N16 cycloneive_io_obuf \GPIO_1[20]~output ( - .i(\D[4]~83_combout ), - .oe(\D[0]~107_combout ), + .i(\D[4]~96_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[20]), @@ -3336,8 +3674,8 @@ defparam \GPIO_1[20]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y7_N9 cycloneive_io_obuf \GPIO_1[21]~output ( - .i(\D[5]~85_combout ), - .oe(\D[0]~107_combout ), + .i(\D[5]~98_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[21]), @@ -3349,8 +3687,8 @@ defparam \GPIO_1[21]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y0_N2 cycloneive_io_obuf \GPIO_1[22]~output ( - .i(\D[6]~93_combout ), - .oe(\D[0]~107_combout ), + .i(\D[6]~106_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[22]), @@ -3362,8 +3700,8 @@ defparam \GPIO_1[22]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y9_N23 cycloneive_io_obuf \GPIO_1[23]~output ( - .i(\D[7]~94_combout ), - .oe(\D[0]~107_combout ), + .i(\D[7]~107_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[23]), @@ -3401,7 +3739,7 @@ defparam \GPIO_1[28]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y10_N16 cycloneive_io_obuf \GPIO_1[29]~output ( - .i(!\z80_|memory_ifc_|nIORQ_out~0_combout ), + .i(\z80_|memory_ifc_|nIORQ_out~0_combout ), .oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3867,6 +4205,305 @@ defparam \buzzer_out~output .bus_hold = "false"; defparam \buzzer_out~output .open_drain_output = "false"; // synopsys translate_on +// Location: IOOBUF_X11_Y0_N16 +cycloneive_io_obuf \DRAM_BA[0]~output ( + .i(\sdram_|r.bank [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_BA[0]), + .obar()); +// synopsys translate_off +defparam \DRAM_BA[0]~output .bus_hold = "false"; +defparam \DRAM_BA[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y0_N9 +cycloneive_io_obuf \DRAM_BA[1]~output ( + .i(\sdram_|r.bank [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_BA[1]), + .obar()); +// synopsys translate_off +defparam \DRAM_BA[1]~output .bus_hold = "false"; +defparam \DRAM_BA[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y0_N9 +cycloneive_io_obuf \DRAM_DQM[0]~output ( + .i(\sdram_|r.dq_masks [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQM[0]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQM[0]~output .bus_hold = "false"; +defparam \DRAM_DQM[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y0_N16 +cycloneive_io_obuf \DRAM_DQM[1]~output ( + .i(\sdram_|r.dq_masks [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQM[1]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQM[1]~output .bus_hold = "false"; +defparam \DRAM_DQM[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y11_N2 +cycloneive_io_obuf \DRAM_RAS_N~output ( + .i(\sdram_|r.state [2]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_RAS_N), + .obar()); +// synopsys translate_off +defparam \DRAM_RAS_N~output .bus_hold = "false"; +defparam \DRAM_RAS_N~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y11_N9 +cycloneive_io_obuf \DRAM_CAS_N~output ( + .i(\sdram_|r.state [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_CAS_N), + .obar()); +// synopsys translate_off +defparam \DRAM_CAS_N~output .bus_hold = "false"; +defparam \DRAM_CAS_N~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N23 +cycloneive_io_obuf \DRAM_CKE~output ( + .i(vcc), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_CKE), + .obar()); +// synopsys translate_off +defparam \DRAM_CKE~output .bus_hold = "false"; +defparam \DRAM_CKE~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y0_N23 +cycloneive_io_obuf \DRAM_CLK~output ( + .i(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK_outclk ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_CLK), + .obar()); +// synopsys translate_off +defparam \DRAM_CLK~output .bus_hold = "false"; +defparam \DRAM_CLK~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y27_N2 +cycloneive_io_obuf \DRAM_WE_N~output ( + .i(\sdram_|r.state [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_WE_N), + .obar()); +// synopsys translate_off +defparam \DRAM_WE_N~output .bus_hold = "false"; +defparam \DRAM_WE_N~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y0_N23 +cycloneive_io_obuf \DRAM_CS_N~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_CS_N), + .obar()); +// synopsys translate_off +defparam \DRAM_CS_N~output .bus_hold = "false"; +defparam \DRAM_CS_N~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y4_N16 +cycloneive_io_obuf \DRAM_ADDR[0]~output ( + .i(\sdram_|r.address [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[0]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[0]~output .bus_hold = "false"; +defparam \DRAM_ADDR[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y0_N9 +cycloneive_io_obuf \DRAM_ADDR[1]~output ( + .i(\sdram_|r.address [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[1]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[1]~output .bus_hold = "false"; +defparam \DRAM_ADDR[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y0_N2 +cycloneive_io_obuf \DRAM_ADDR[2]~output ( + .i(\sdram_|r.address [2]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[2]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[2]~output .bus_hold = "false"; +defparam \DRAM_ADDR[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X20_Y0_N9 +cycloneive_io_obuf \DRAM_ADDR[3]~output ( + .i(\sdram_|r.address [3]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[3]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[3]~output .bus_hold = "false"; +defparam \DRAM_ADDR[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X25_Y0_N16 +cycloneive_io_obuf \DRAM_ADDR[4]~output ( + .i(\sdram_|r.address [4]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[4]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[4]~output .bus_hold = "false"; +defparam \DRAM_ADDR[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y0_N23 +cycloneive_io_obuf \DRAM_ADDR[5]~output ( + .i(\sdram_|r.address [5]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[5]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[5]~output .bus_hold = "false"; +defparam \DRAM_ADDR[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X20_Y0_N2 +cycloneive_io_obuf \DRAM_ADDR[6]~output ( + .i(\sdram_|r.address [6]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[6]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[6]~output .bus_hold = "false"; +defparam \DRAM_ADDR[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y0_N2 +cycloneive_io_obuf \DRAM_ADDR[7]~output ( + .i(\sdram_|r.address [7]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[7]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[7]~output .bus_hold = "false"; +defparam \DRAM_ADDR[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y5_N23 +cycloneive_io_obuf \DRAM_ADDR[8]~output ( + .i(\sdram_|r.address [8]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[8]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[8]~output .bus_hold = "false"; +defparam \DRAM_ADDR[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y4_N23 +cycloneive_io_obuf \DRAM_ADDR[9]~output ( + .i(\sdram_|r.address [9]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[9]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[9]~output .bus_hold = "false"; +defparam \DRAM_ADDR[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y8_N23 +cycloneive_io_obuf \DRAM_ADDR[10]~output ( + .i(\sdram_|r.address [10]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[10]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[10]~output .bus_hold = "false"; +defparam \DRAM_ADDR[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y7_N2 +cycloneive_io_obuf \DRAM_ADDR[11]~output ( + .i(\sdram_|r.address [11]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[11]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[11]~output .bus_hold = "false"; +defparam \DRAM_ADDR[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y6_N16 +cycloneive_io_obuf \DRAM_ADDR[12]~output ( + .i(\sdram_|r.address[11]~_Duplicate_1_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[12]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[12]~output .bus_hold = "false"; +defparam \DRAM_ADDR[12]~output .open_drain_output = "false"; +// synopsys translate_on + // Location: IOOBUF_X0_Y24_N23 cycloneive_io_obuf \I2C_SCLK~output ( .i(\ula_|i2c_loader_|scl_out~q ), @@ -3893,6 +4530,214 @@ defparam \I2C_SDAT~output .bus_hold = "false"; defparam \I2C_SDAT~output .open_drain_output = "true"; // synopsys translate_on +// Location: IOOBUF_X0_Y23_N16 +cycloneive_io_obuf \DRAM_DQ[0]~output ( + .i(\sdram_|Mux72~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[0]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[0]~output .bus_hold = "false"; +defparam \DRAM_DQ[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y23_N23 +cycloneive_io_obuf \DRAM_DQ[1]~output ( + .i(\sdram_|Mux3~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[1]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[1]~output .bus_hold = "false"; +defparam \DRAM_DQ[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y0_N9 +cycloneive_io_obuf \DRAM_DQ[2]~output ( + .i(\sdram_|Mux2~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[2]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[2]~output .bus_hold = "false"; +defparam \DRAM_DQ[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y7_N9 +cycloneive_io_obuf \DRAM_DQ[3]~output ( + .i(\sdram_|Mux1~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[3]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[3]~output .bus_hold = "false"; +defparam \DRAM_DQ[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y12_N2 +cycloneive_io_obuf \DRAM_DQ[4]~output ( + .i(\sdram_|Mux0~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[4]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[4]~output .bus_hold = "false"; +defparam \DRAM_DQ[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y15_N2 +cycloneive_io_obuf \DRAM_DQ[5]~output ( + .i(\sdram_|Mux73~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[5]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[5]~output .bus_hold = "false"; +defparam \DRAM_DQ[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y15_N9 +cycloneive_io_obuf \DRAM_DQ[6]~output ( + .i(\sdram_|Mux74~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[6]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[6]~output .bus_hold = "false"; +defparam \DRAM_DQ[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N16 +cycloneive_io_obuf \DRAM_DQ[7]~output ( + .i(\sdram_|Mux75~0_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[7]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[7]~output .bus_hold = "false"; +defparam \DRAM_DQ[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y0_N16 +cycloneive_io_obuf \DRAM_DQ[8]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[8]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[8]~output .bus_hold = "false"; +defparam \DRAM_DQ[8]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y0_N2 +cycloneive_io_obuf \DRAM_DQ[9]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[9]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[9]~output .bus_hold = "false"; +defparam \DRAM_DQ[9]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y0_N2 +cycloneive_io_obuf \DRAM_DQ[10]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[10]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[10]~output .bus_hold = "false"; +defparam \DRAM_DQ[10]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y0_N9 +cycloneive_io_obuf \DRAM_DQ[11]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[11]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[11]~output .bus_hold = "false"; +defparam \DRAM_DQ[11]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y0_N23 +cycloneive_io_obuf \DRAM_DQ[12]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[12]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[12]~output .bus_hold = "false"; +defparam \DRAM_DQ[12]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y0_N16 +cycloneive_io_obuf \DRAM_DQ[13]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[13]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[13]~output .bus_hold = "false"; +defparam \DRAM_DQ[13]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y0_N23 +cycloneive_io_obuf \DRAM_DQ[14]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[14]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[14]~output .bus_hold = "false"; +defparam \DRAM_DQ[14]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y12_N9 +cycloneive_io_obuf \DRAM_DQ[15]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[15]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[15]~output .bus_hold = "false"; +defparam \DRAM_DQ[15]~output .open_drain_output = "true"; +// synopsys translate_on + // Location: IOIBUF_X27_Y0_N22 cycloneive_io_ibuf \CLOCK_50~input ( .i(CLOCK_50), @@ -4024,7 +4869,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N4 +// Location: LCCOMB_X25_Y33_N0 cycloneive_lcell_comb \ula_|clocks_|counter[0]~0 ( // Equation(s): // \ula_|clocks_|counter[0]~0_combout = !\ula_|clocks_|counter [0] @@ -4041,7 +4886,7 @@ defparam \ula_|clocks_|counter[0]~0 .lut_mask = 16'h0F0F; defparam \ula_|clocks_|counter[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N5 +// Location: FF_X25_Y33_N1 dffeas \ula_|clocks_|counter[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|counter[0]~0_combout ), @@ -4070,7 +4915,7 @@ defparam \SW[2]~input .bus_hold = "false"; defparam \SW[2]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N10 +// Location: LCCOMB_X25_Y33_N4 cycloneive_lcell_comb \ula_|clocks_|clk_cpu~0 ( // Equation(s): // \ula_|clocks_|clk_cpu~0_combout = \ula_|clocks_|clk_cpu~q $ (((\SW[2]~input_o ) # (!\ula_|clocks_|counter [0]))) @@ -4087,7 +4932,7 @@ defparam \ula_|clocks_|clk_cpu~0 .lut_mask = 16'h0FC3; defparam \ula_|clocks_|clk_cpu~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N11 +// Location: FF_X25_Y33_N5 dffeas \ula_|clocks_|clk_cpu ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|clk_cpu~0_combout ), @@ -4119,40 +4964,6 @@ defparam \ula_|clocks_|clk_cpu~clkctrl .clock_type = "global clock"; defparam \ula_|clocks_|clk_cpu~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N20 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hAAA0; -defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N12 -cycloneive_lcell_comb \z80_|sequencer_|ena_M ( -// Equation(s): -// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|ena_M~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; -defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: IOIBUF_X0_Y16_N8 cycloneive_io_ibuf \KEY[1]~input ( .i(KEY[1]), @@ -4163,7 +4974,7 @@ defparam \KEY[1]~input .bus_hold = "false"; defparam \KEY[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N6 +// Location: LCCOMB_X35_Y10_N0 cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( // Equation(s): // \z80_|interrupts_|nmi_armed~feeder_combout = VCC @@ -4180,11775 +4991,6 @@ defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N2 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hAAFF; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y15_N7 -dffeas \z80_|interrupts_|nmi_armed ( - .clk(!\KEY[1]~input_o ), - .d(\z80_|interrupts_|nmi_armed~feeder_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|nmi_armed~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; -defparam \z80_|interrupts_|nmi_armed .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N12 -cycloneive_lcell_comb \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder ( -// Equation(s): -// \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout = \z80_|interrupts_|nmi_armed~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|interrupts_|nmi_armed~q ), - .cin(gnd), - .combout(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .lut_mask = 16'hFF00; -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( -// Equation(s): -// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_eval_cond~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( -// Equation(s): -// \z80_|execute_|ixy_d~4_combout = (!\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h1100; -defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N30 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N31 -dffeas \z80_|sequencer_|DFFE_M3_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M3_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( -// Equation(s): -// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hD0D0; -defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N2 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N3 -dffeas \z80_|sequencer_|DFFE_M4_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M4_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal32~0_combout = (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(gnd), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal32~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h00CC; -defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N14 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF33; -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N10 -cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( -// Equation(s): -// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instED~q ) # (\z80_|decode_state_|DFFE_instCB~q ) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|decode_state_|table_xx~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; -defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~0_combout = (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal41~2_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal36~0_combout )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|pla_decode_|Equal36~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|pla_decode_|Equal36~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hB3A0; -defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N29 -dffeas \z80_|decode_state_|DFFE_instCB ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instCB~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h0020; -defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_ed_set~combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal2~1_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N17 -dffeas \z80_|decode_state_|DFFE_instED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instED~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & \z80_|decode_state_|DFFE_instED~q )) - - .dataa(\z80_|ir_|opcode [7]), - .datab(gnd), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( -// Equation(s): -// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_im_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal49~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout )) - - .dataa(gnd), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal49~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h3000; -defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~1_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [3])) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; -defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~14_combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~8_combout = (((!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h4FFF; -defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N12 -cycloneive_lcell_comb \z80_|nM1_int~2 ( -// Equation(s): -// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|nM1_int~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|nM1_int~2 .lut_mask = 16'h0055; -defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal49~0_combout ) # ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hEF00; -defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( -// Equation(s): -// \z80_|execute_|ixy_d~7_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & -// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & \z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; -defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal39~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; -defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~2_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal3~2_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal3~2_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( -// Equation(s): -// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( -// Equation(s): -// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( -// Equation(s): -// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( -// Equation(s): -// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~8_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( -// Equation(s): -// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal44~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal44~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0002; -defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( -// Equation(s): -// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hC800; -defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( -// Equation(s): -// \z80_|execute_|ixy_d~13_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|execute_|ixy_d~16_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(gnd), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal50~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h3000; -defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h8800; -defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( -// Equation(s): -// \z80_|execute_|ixy_d~17_combout = (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|pla_decode_|Equal50~0_combout & ((!\z80_|pla_decode_|Equal33~2_combout )))) # (!\z80_|decode_state_|DFFE_inst4~q & (((!\z80_|pla_decode_|Equal50~0_combout & -// !\z80_|pla_decode_|Equal33~2_combout )) # (!\z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal50~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h0537; -defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( -// Equation(s): -// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( -// Equation(s): -// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~12_combout & (((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ixy_d~12_combout & -// (!\z80_|execute_|ixy_d~13_combout & (\z80_|execute_|ixy_d~17_combout ))) - - .dataa(\z80_|execute_|ixy_d~12_combout ), - .datab(\z80_|execute_|ixy_d~13_combout ), - .datac(\z80_|execute_|ixy_d~17_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h30BA; -defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( -// Equation(s): -// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T5_ff~q ) # ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hCC8C; -defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( -// Equation(s): -// \z80_|execute_|ixy_d~15_combout = ((\z80_|pla_decode_|Equal49~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|execute_|ixy_d~11_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) - - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|ixy_d~14_combout ), - .datad(\z80_|execute_|ixy_d~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|execute_|ixy_d~15_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T5_ff~q & -// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N23 -dffeas \z80_|decode_state_|DFFE_instIY1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_iy_set~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instIY1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q )) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(gnd), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0500; -defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~14_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~2 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~18_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~26_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~27_combout = (\z80_|pla_decode_|Equal13~2_combout & \z80_|ir_|opcode [3]) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (((!\z80_|execute_|ctl_mRead~26_combout & !\z80_|execute_|ctl_mRead~27_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_mRead~27_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h02AA; -defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h5D00; -defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~18_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal12~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal55~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0500; -defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|comb~1 ( -// Equation(s): -// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|comb~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~1 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|comb~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~17_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~18_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~17_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~9_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~10_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~8_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~20_combout = (\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h2200; -defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal25~0_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal25~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~21_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~17_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~1_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'hFDFC; -defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal32~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal29~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal41~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal34~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal37~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal35~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal38~2_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal38~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal35~0_combout ) # (\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~3_combout = (\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|pla_decode_|Equal29~0_combout ) # ((\z80_|pla_decode_|Equal24~1_combout ) # (\z80_|reg_control_|reg_sys_we_lo~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|pla_decode_|Equal24~1_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|comb~0 ( -// Equation(s): -// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|comb~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~0 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal47~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|comb~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N8 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|reg_control_|reg_sys_we_lo~3_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # -// (!\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|reg_control_|reg_sys_we_lo~3_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h153F; -defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~22_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (((!\z80_|execute_|ctl_mRead~20_combout & !\z80_|execute_|ctl_mRead~21_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~20_combout ), - .datab(\z80_|execute_|ctl_mRead~21_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~24_combout = (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~18_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_mRead~22_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h0313; -defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~16_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N16 -cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( -// Equation(s): -// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|M5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N17 -dffeas \z80_|sequencer_|M5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|M5~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|M5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|M5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~29 ( -// Equation(s): -// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & -// (((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~29 .lut_mask = 16'h0777; -defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~25_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~16_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout -// & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~17_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~17_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|setM1~29_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|setM1~29_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~7_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~1_combout = (!\z80_|decode_state_|DFFE_instED~q & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & !\z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~14_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~14 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_state_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~14_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((!\z80_|execute_|ctl_state_alu~14_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'h115F; -defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h1F3F; -defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|pla_decode_|Equal29~0_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal29~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|pla_decode_|Equal29~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; -defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (\z80_|reg_control_|reg_sel_pc~1_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~0_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h40C0; -defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( -// Equation(s): -// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|ctl_state_alu~8_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~8_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~17 .lut_mask = 16'h7000; -defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~6_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0004; -defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( -// Equation(s): -// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|execute_|ctl_mRead~18_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & -// (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~16 .lut_mask = 16'h135F; -defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|pla_decode_|Equal41~0_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal46~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [2] & \z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal46~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~17_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~6_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_flags_alu~17_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~6 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_flags_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]) - - .dataa(\z80_|ir_|opcode [6]), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0505; -defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~6_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~16_combout = (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|execute_|ctl_flags_alu~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & \z80_|execute_|ctl_reg_in_hi~3_combout )) - - .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( -// Equation(s): -// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|fMRead~17_combout & (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|fMRead~16_combout & \z80_|execute_|ctl_mWrite~8_combout ))) - - .dataa(\z80_|execute_|fMRead~17_combout ), - .datab(\z80_|execute_|ctl_sw_2d~4_combout ), - .datac(\z80_|execute_|fMRead~16_combout ), - .datad(\z80_|execute_|ctl_mWrite~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( -// Equation(s): -// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_mRead~24_combout & (\z80_|execute_|ctl_reg_in_hi~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|fMRead~18_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~24_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datad(\z80_|execute_|fMRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~36 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~36_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~36 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~9_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~9 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_op_low~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h007F; -defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~11_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h00AA; -defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal9~1_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ixy_d~6_combout & -// (((!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_mRead~11_combout ))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~4_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~7_combout & (!\z80_|execute_|ctl_ir_we~11_combout & ((!\z80_|execute_|ctl_ir_we~12_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout & (((!\z80_|execute_|ctl_ir_we~12_combout ) # -// (!\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0577; -defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~8_combout = (\z80_|execute_|ctl_alu_shift_oe~44_combout & (\z80_|execute_|ctl_sw_2d~7_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datab(\z80_|execute_|ctl_sw_2d~7_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~5_combout & (\z80_|execute_|fMRead~19_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & \z80_|execute_|ctl_sw_2d~8_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~5_combout ), - .datab(\z80_|execute_|fMRead~19_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datad(\z80_|execute_|ctl_sw_2d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (!\z80_|execute_|ctl_sw_1d~5_combout & (\z80_|execute_|ctl_sw_1d~4_combout & \z80_|execute_|ctl_sw_2d~9_combout ))) - - .dataa(\z80_|execute_|ctl_im_we~combout ), - .datab(\z80_|execute_|ctl_sw_1d~5_combout ), - .datac(\z80_|execute_|ctl_sw_1d~4_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal47~0_combout ))) # (!\z80_|execute_|ctl_sw_1d~6_combout ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7333; -defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~8_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~8 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_alu_op_low~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal2~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'h0111; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0088; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0037; -defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_zero~combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~4 ( -// Equation(s): -// \z80_|alu_|db_low[2]~4_combout = ((\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~4 .lut_mask = 16'h555D; -defparam \z80_|alu_|db_low[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_sw_4u~1_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # -// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_shift_oe~30_combout & (\z80_|execute_|ctl_alu_shift_oe~29_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal69~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal69~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~5_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [5]) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h00AA; -defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~5_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~12_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~12 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_alu_op_low~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal56~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal56~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~11_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~11 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op_low~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|nextM~2 ( -// Equation(s): -// \z80_|execute_|nextM~2_combout = (!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0011; -defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~4_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal69~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .lut_mask = 16'h0103; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~5_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hC0D0; -defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~15_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h0F3F; -defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_ir_we~7_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # -// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # -// (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~15_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~3_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ctl_ir_we~11_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h3000; -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_alu_core_R~4_combout & !\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout -// ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal48~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~18_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'hBBBF; -defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~17_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0100; -defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~18_combout = ((!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|ctl_iorw~10_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (\z80_|execute_|ctl_alu_shift_oe~18_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~19_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~13_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~13 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_alu_bs_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_alu_bs_oe~13_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~13_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal20~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal20~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal68~2_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|pla_decode_|Equal68~2_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~13 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_op_low~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~15_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_alu_op_low~13_combout & !\z80_|execute_|ctl_alu_op_low~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hBBBF; -defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_flags_bus~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~11 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .lut_mask = 16'hAFBF; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h70F0; -defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~8_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|execute_|ixy_d~10_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~9_combout = ((!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_flags_bus~8_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_flags_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_flags_bus~14_combout & (\z80_|execute_|ctl_flags_bus~11_combout & (\z80_|execute_|ctl_flags_bus~10_combout & \z80_|execute_|ctl_flags_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~14_combout ), - .datab(\z80_|execute_|ctl_flags_bus~11_combout ), - .datac(\z80_|execute_|ctl_flags_bus~10_combout ), - .datad(\z80_|execute_|ctl_flags_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_flags_xy_we~18_combout & (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout ))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datad(\z80_|execute_|ctl_flags_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & ((!\z80_|execute_|ctl_state_alu~14_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|execute_|ctl_ir_we~14_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) # -// (!\z80_|execute_|ctl_mWrite~3_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h3030; -defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h3700; -defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|pla_decode_|Equal41~2_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|execute_|ctl_bus_db_oe~0_combout & \z80_|execute_|ctl_alu_op1_sel_bus~12_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~13_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal48~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (((\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h1100; -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[2]~14_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N17 -dffeas \z80_|alu_|op1_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'h88C8; -defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~10_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~10 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op_low~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|fMWrite~11 ( -// Equation(s): -// \z80_|execute_|fMWrite~11_combout = ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~11 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|fMWrite~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~21_combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (\z80_|execute_|ctl_alu_op_low~9_combout ))) # (!\z80_|execute_|fMWrite~11_combout ) - - .dataa(\z80_|execute_|fMWrite~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~22_combout = ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~10_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~10_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~16_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h7737; -defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~17_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~16_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h2200; -defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel~36_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel~36 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & (\z80_|execute_|ctl_state_alu~8_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datab(\z80_|execute_|ctl_state_alu~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~18_combout = (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_mWrite~3_combout & -// (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~11_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~19_combout = ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|execute_|ctl_alu_op_low~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~33_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~12_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'h77F7; -defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'hF0FF; -defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~23_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_mRead~36_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|execute_|ctl_alu_op_low~22_combout ) # (((\z80_|execute_|ctl_alu_op_low~20_combout ) # (\z80_|execute_|ctl_alu_op_low~23_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ixy_d~9_combout & (((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|execute_|ixy_d~5_combout & -// (\z80_|pla_decode_|Equal40~1_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'hEAE0; -defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~34_combout = (\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFF08; -defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~combout = ((\z80_|execute_|ctl_alu_op_low~24_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~26_combout ))) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~26_combout ) # (\z80_|execute_|ctl_mRead~27_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~18_combout ) - - .dataa(\z80_|execute_|ctl_mRead~26_combout ), - .datab(\z80_|execute_|ctl_mRead~27_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hEF0F; -defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~39_combout = (\z80_|execute_|ctl_alu_shift_oe~37_combout ) # (((\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~42_combout = (\z80_|execute_|ctl_alu_shift_oe~40_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'hF200; -defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~21_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~22_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h3F20; -defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~23_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~22_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~22_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h0CEC; -defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~23_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~23_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'h32F0; -defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~25_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~24_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|ctl_alu_shift_oe~24_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h22EA; -defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~14_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~14 .lut_mask = 16'hC0C8; -defparam \z80_|execute_|ctl_alu_bs_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~26_combout = (!\z80_|execute_|ctl_alu_bs_oe~14_combout & ((\z80_|execute_|ctl_alu_shift_oe~25_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_bus_db_oe~1_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & -// (\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_bus_db_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~28_combout = ((\z80_|execute_|ctl_alu_shift_oe~27_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~20_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~44_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'hFF5F; -defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~4_combout -// & (\z80_|execute_|ctl_ir_we~10_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hEAC8; -defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|execute_|ctl_alu_bs_oe~10_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~32_combout = (!\z80_|execute_|ctl_alu_bs_oe~11_combout & ((\z80_|execute_|ctl_alu_shift_oe~28_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h00CF; -defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~32_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_alu_shift_oe~16_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout )))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hFF51; -defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|execute_|ctl_alu_op_low~11_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_state_alu~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_ir_we~7_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # -// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h3F20; -defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_ir_we~10_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~36_combout = (((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~12_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~26_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~36_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~9_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q ))) # (!\z80_|pla_decode_|Equal47~0_combout ) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~0_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hFDDD; -defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (\z80_|pla_decode_|Equal48~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h0088; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~9_combout = (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & (\z80_|execute_|ctl_flags_xy_we~8_combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h1300; -defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal8~0_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h0C00; -defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~9_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~9 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal39~0_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & -// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~1_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~1 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal11~1_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal11~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~10_combout = (\z80_|execute_|ctl_flags_alu~9_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_flags_sz_we~3_combout & !\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~9_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_alu~10_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~7_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal13~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~2 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~2_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) - - .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~2 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_pf_sel[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~2_combout = (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~25_combout = (\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_ir_we~14_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout ) # -// (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~25 .lut_mask = 16'h0377; -defparam \z80_|execute_|ctl_bus_inc_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~25_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hCC8C; -defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~10_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hCCC4; -defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'h3331; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~17_combout = (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~5_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h5557; -defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~6_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|reg_control_|reg_sys_we_lo~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'h7000; -defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & -// (((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal2~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|table_xx~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h0002; -defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|ctl_state_alu~7_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~2_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|nM1_int~2_combout & -// (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_mWrite~3_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & -// (((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h02AA; -defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & (\z80_|execute_|ctl_alu_res_oe~0_combout & !\z80_|execute_|ctl_alu_oe~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~11_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_alu_res_oe~1_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'h8C88; -defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( -// Equation(s): -// \z80_|alu_|db_high[3]~2_combout = (\z80_|execute_|ctl_alu_bs_oe~combout ) # ((\z80_|execute_|ctl_alu_op1_oe~1_combout ) # ((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFFEF; -defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( -// Equation(s): -// \z80_|alu_|db_high[3]~3_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout ) # (\z80_|alu_|db_high[3]~2_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(gnd), - .datac(\z80_|alu_|db_high[3]~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hFAFA; -defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~24 ( -// Equation(s): -// \z80_|alu_|db_low[2]~24_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[2]~3_combout & (\z80_|alu_|db_low[2]~6_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[2]~3_combout & -// \z80_|alu_|db_low[2]~6_combout )) # (!\z80_|alu_|db_high[3]~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[2]~3_combout ), - .datac(\z80_|alu_|db_low[2]~6_combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~24 .lut_mask = 16'hC0D5; -defparam \z80_|alu_|db_low[2]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~7 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~7_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~7 .lut_mask = 16'h0AAA; -defparam \z80_|reg_control_|reg_sys_we_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = ((!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|reg_control_|reg_sys_we_lo~7_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~10_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hFF57; -defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~43_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'hFF57; -defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~26_combout = (\z80_|execute_|ctl_alu_core_S~10_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & \z80_|execute_|ctl_bus_inc_oe~25_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_mWrite~9_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~9_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|execute_|ctl_alu_oe~8_combout & (\z80_|execute_|ctl_alu_oe~4_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|ctl_bus_db_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~8_combout ), - .datab(\z80_|execute_|ctl_alu_oe~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mWrite~16_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~6_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~7_combout = (\z80_|execute_|ctl_alu_oe~6_combout & (((!\z80_|execute_|ctl_mRead~27_combout & !\z80_|execute_|ctl_mRead~26_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~27_combout ), - .datac(\z80_|execute_|ctl_mRead~26_combout ), - .datad(\z80_|execute_|ctl_alu_oe~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~12_combout = (\z80_|execute_|ctl_alu_oe~11_combout ) # (((!\z80_|execute_|ctl_alu_oe~7_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_oe~5_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), - .datab(\z80_|execute_|ctl_alu_oe~5_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), - .datad(\z80_|execute_|ctl_alu_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_alu_oe~12_combout ) # (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_flags_alu~10_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~12_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~14_combout = (\z80_|execute_|ctl_alu_oe~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_oe~13_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hF5F5; -defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & -// (((!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mRead~26_combout ))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|nextM~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~53 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'h8C00; -defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~54 ( -// Equation(s): -// \z80_|execute_|setM1~54_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~54 .lut_mask = 16'hABFF; -defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~7_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((!\z80_|execute_|ctl_alu_oe~3_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout )) # -// (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_alu_oe~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|setM1~54_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_sw_2u~4_combout )) - - .dataa(\z80_|execute_|setM1~54_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~1_combout ), - .datad(\z80_|execute_|ctl_sw_2u~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_reg_gp_sel~36_combout & (\z80_|execute_|comb~0_combout $ ((!\z80_|ir_|opcode [0])))) # (!\z80_|execute_|ctl_reg_gp_sel~36_combout & (!\z80_|execute_|ctl_sw_2u~5_combout & -// (\z80_|execute_|comb~0_combout $ (!\z80_|ir_|opcode [0])))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'h82C3; -defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~35_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (\z80_|execute_|ctl_inc_cy~35_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_inc_cy~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hBF00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~6_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & -// (((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~2_combout & (\z80_|execute_|ctl_sw_2u~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|execute_|ctl_mRead~8_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(\z80_|execute_|ctl_sw_2u~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~10_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_op_low~13_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|rsel3 ( -// Equation(s): -// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|rsel3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel3 .lut_mask = 16'h7878; -defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & -// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7707; -defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~6_combout = (!\z80_|execute_|ctl_sw_2u~6_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout & \z80_|execute_|ctl_reg_out_hi~5_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2u~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~7_combout = ((\z80_|execute_|ctl_reg_out_hi~8_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|rsel0 ( -// Equation(s): -// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|rsel0~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel0 .lut_mask = 16'h5AAA; -defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .lut_mask = 16'h0444; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h7030; -defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~11_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~11_combout )) # (!\z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~14_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal77~0_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h0D0F; -defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_1d~8_combout ) # (!\z80_|execute_|ctl_sw_2d~14_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2d~10_combout ), - .datab(\z80_|execute_|ctl_sw_2d~14_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hBFAA; -defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # (\z80_|execute_|ctl_alu_shift_oe~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFEAA; -defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~11_combout ) # ((\z80_|execute_|ctl_sw_2d~12_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~11_combout ), - .datac(\z80_|execute_|ctl_sw_2d~12_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~34_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_alu_oe~2_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_inc_cy~34_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~75_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|pla_decode_|Equal38~2_combout & ((!\z80_|pla_decode_|Equal37~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|pla_decode_|Equal38~2_combout -// & !\z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|pla_decode_|Equal38~2_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal37~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~75_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal29~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal4~0_combout = (\z80_|execute_|comb~1_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|execute_|comb~1_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~48_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~46_combout = (\z80_|execute_|ctl_bus_inc_oe~48_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|pla_decode_|Equal4~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & ((!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & -// !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~92 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~92_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~92 .lut_mask = 16'h5F7F; -defparam \z80_|execute_|ctl_inc_cy~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~1 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal19~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~38_combout = (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal3~1_combout )) # (!\z80_|pla_decode_|Equal19~1_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal19~1_combout ), - .datac(\z80_|execute_|ctl_sw_4u~0_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~93 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~93_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~93 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~39_combout = (\z80_|execute_|ctl_inc_cy~93_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_inc_cy~93_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~24_combout = (\z80_|execute_|ctl_inc_cy~92_combout & (\z80_|execute_|ctl_inc_cy~38_combout & \z80_|execute_|ctl_inc_cy~39_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~92_combout ), - .datac(\z80_|execute_|ctl_inc_cy~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~24 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_bus_inc_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~1_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (\z80_|execute_|ctl_bus_inc_oe~46_combout & (\z80_|execute_|ctl_inc_cy~53_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~53_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~1 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~44_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'h1333; -defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~0_combout = (\z80_|execute_|ctl_bus_inc_oe~44_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & ((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~0 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_reg_gp_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (\z80_|execute_|ctl_reg_gp_we~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout & -// (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h3F15; -defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_sw_4u~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datad(\z80_|execute_|ctl_sw_4u~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( -// Equation(s): -// \z80_|execute_|fMRead~3_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|execute_|ctl_state_alu~14_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) # -// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_mRead~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h135F; -defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~15_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~12_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_sw_4u~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & -// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~94 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~94_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~94_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~94 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~87_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) - - .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~94_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~16_combout = (\z80_|execute_|fMRead~3_combout & (\z80_|execute_|ctl_reg_sel_wz~15_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ))) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~6_combout = ((\z80_|execute_|ctl_sw_4u~5_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout ))) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|execute_|ctl_sw_4u~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~6_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal1~5_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N22 -cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( -// Equation(s): -// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal1~6_combout & \z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal1~6_combout ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_exx~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N23 -dffeas \z80_|reg_control_|bank_exx ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_exx~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_exx~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_exx .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N26 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de1~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hF0D2; -defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N27 -dffeas \z80_|reg_control_|bank_hl_de1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal2~1_combout & \z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal2~1_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hC888; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h00FE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~12_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~13_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal50~0_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hEEEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( -// Equation(s): -// \z80_|execute_|fMWrite~3_combout = (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h0001; -defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [2]) # ((\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFAF; -defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( -// Equation(s): -// \z80_|execute_|fMRead~2_combout = (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_flags_bus~5_combout )) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~14_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMRead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h1010; -defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~19_combout = (\z80_|execute_|fMWrite~3_combout & (\z80_|execute_|fMRead~2_combout & !\z80_|execute_|ctl_ir_we~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|fMWrite~3_combout ), - .datac(\z80_|execute_|fMRead~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'h00C0; -defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [2] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h50F0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~14_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hC5CD; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~15_combout )))) # (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout & ((\z80_|execute_|ctl_ir_we~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_ir_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hCAC0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'h0050; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~47_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q ))) # (!\z80_|execute_|ctl_mRead~8_combout ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'hFF37; -defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|ctl_reg_use_sp~2_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_bus_inc_oe~47_combout & \z80_|execute_|nextM~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal6~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0050; -defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~21_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~5_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_sw_1d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & -// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'hAB00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~20_combout = (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mRead~14_combout & !\z80_|pla_decode_|Equal49~0_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .lut_mask = 16'h0101; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~22_combout = (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~21_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & ((\z80_|sequencer_|M5~q ) # (\z80_|sequencer_|DFFE_M4_ff~q )))) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|decode_state_|DFFE_instED~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'h0032; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout & \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~36_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h20AA; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|pla_decode_|Equal20~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h0505; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~14_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~14 .lut_mask = 16'hF0FF; -defparam \z80_|execute_|ctl_flags_hf_cpl~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (!\z80_|pla_decode_|Equal68~2_combout & (!\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_flags_hf_cpl~14_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|pla_decode_|Equal68~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~47 ( -// Equation(s): -// \z80_|execute_|setM1~47_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0015; -defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~48 ( -// Equation(s): -// \z80_|execute_|setM1~48_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|execute_|ctl_flags_hf_cpl~10_combout & (\z80_|execute_|setM1~47_combout & \z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .datac(\z80_|execute_|setM1~47_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~48 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~13_combout = (\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_iorw~10_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_flags_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~48_combout )))) - - .dataa(\z80_|execute_|setM1~48_combout ), - .datab(\z80_|execute_|ctl_flags_oe~1_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h0070; -defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~28_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & !\z80_|execute_|ctl_reg_in_hi~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~40_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~40_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~40_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~12_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~43_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~12_combout & (\z80_|execute_|ctl_inc_cy~43_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_inc_cy~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( -// Equation(s): -// \z80_|execute_|fMRead~6_combout = (\z80_|pla_decode_|Equal29~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ixy_d~7_combout ))) # (!\z80_|pla_decode_|Equal29~0_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & -// !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal29~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h0357; -defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( -// Equation(s): -// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & -// !\z80_|execute_|ctl_mRead~16_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h111F; -defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( -// Equation(s): -// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|fMRead~7_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|fMRead~7_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h10F0; -defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .datac(\z80_|execute_|fMRead~6_combout ), - .datad(\z80_|execute_|fMRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~13_combout = (\z80_|execute_|ctl_state_alu~8_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal52~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~8_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~10_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'h3331; -defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) # -// (!\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~9_combout = (\z80_|execute_|ctl_state_alu~14_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|execute_|ctl_state_alu~14_combout & (\z80_|pla_decode_|Equal52~1_combout & -// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'hF3A2; -defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~13_combout ), - .datab(\z80_|execute_|ctl_state_alu~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~9_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hFD00; -defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~4_combout = (((\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal62~2_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = ((!\z80_|execute_|ctl_mRead~4_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h373F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~13_combout ), - .datab(\z80_|execute_|ctl_state_alu~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~9_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h00FD; -defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~3 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~3_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal64~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal64~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~3 .lut_mask = 16'hEEFF; -defparam \z80_|execute_|ctl_pf_sel[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_flags_pf_we~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & (\z80_|execute_|ctl_alu_oe~7_combout & \z80_|execute_|ctl_pf_sel[0]~3_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .datac(\z80_|execute_|ctl_alu_oe~7_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_state_alu~14_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~15 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_state_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [4] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (\z80_|execute_|ctl_state_alu~15_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )) - - .dataa(\z80_|execute_|ctl_state_alu~15_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h00A0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~29_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ) # (((\z80_|execute_|ctl_reg_gp_sel[1]~23_combout & \z80_|ir_|opcode [5])) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal11~0_combout & -// ((\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mRead~5_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((\z80_|ir_|opcode [1] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(\z80_|execute_|ctl_sw_2u~5_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hFF70; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~20_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hF7F7; -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ctl_reg_sys_hilo~20_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h22A2; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N18 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0010; -defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h0F0B; -defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h00E4; -defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; -defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N15 -dffeas \z80_|reg_control_|bank_hl_de2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de2~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))))) - - .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hAC00; -defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & (((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~4_combout = (!\z80_|execute_|ctl_reg_in_hi~7_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & \z80_|execute_|ctl_state_alu~15_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_state_alu~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'h1100; -defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout & ((!\z80_|execute_|ctl_iorw~10_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datac(\z80_|execute_|ctl_iorw~10_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h004C; -defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout -// )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|pla_decode_|Equal25~0_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .lut_mask = 16'hA200; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout & !\z80_|execute_|ctl_sw_1d~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), - .datad(\z80_|execute_|ctl_sw_1d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & \z80_|execute_|ctl_reg_gp_we~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~6_combout = (((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_reg_gp_we~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .datab(\z80_|execute_|ctl_sw_4u~3_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~7_combout & (((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h00F7; -defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_flags_oe~1_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h1033; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_al_we~14_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFBF0; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = (\z80_|execute_|rsel3~combout & (((!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'h40CC; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (((\z80_|execute_|ctl_ir_we~7_combout ) # (\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo~20_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_iorw~11_combout ) # ((\z80_|execute_|ctl_state_alu~14_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout )))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~25_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ) # -// (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hF5FF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|execute_|rsel0~combout & ((\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & -// (((\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )) # (!\z80_|execute_|setM1~48_combout ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'hCD05; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~6_combout & (!\z80_|execute_|ixy_d~9_combout ))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|pla_decode_|Equal10~0_combout )) # -// (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h1357; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal2~1_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~40 ( -// Equation(s): -// \z80_|execute_|setM1~40_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal8~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~40 .lut_mask = 16'h1155; -defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & ((\z80_|execute_|setM1~40_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h1101; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~93 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~93_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & ((\z80_|reg_control_|reg_sel_hl~0_combout ) # (\z80_|reg_control_|reg_sel_hl2~0_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .lut_mask = 16'h0E00; -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h00D8; -defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h0F00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout -// & (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~10_combout = (\z80_|execute_|ctl_reg_in_hi~9_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_gp_we~5_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~19_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_mRead~22_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~8_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # (\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h00B0; -defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFECC; -defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~3_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout )) - - .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & !\z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N20 -cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( -// Equation(s): -// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|pla_decode_|Equal21~2_combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y12_N21 -dffeas \z80_|reg_control_|bank_af ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_af~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_af~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_af .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (!\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h1000; -defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; -defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h2200; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal19~0_combout & ((!\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout ) # -// (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'h035F; -defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal33~0_combout )) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hF8F8; -defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~7_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~6_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_bus~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( -// Equation(s): -// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~24 .lut_mask = 16'h0777; -defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~13_combout = (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datad(\z80_|execute_|ctl_flags_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~combout = (\z80_|execute_|ctl_flags_bus~7_combout ) # (((\z80_|execute_|ctl_flags_hf2_we~combout ) # (!\z80_|execute_|ctl_flags_bus~13_combout )) # (!\z80_|execute_|fMRead~24_combout )) - - .dataa(\z80_|execute_|ctl_flags_bus~7_combout ), - .datab(\z80_|execute_|fMRead~24_combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mWrite~2_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h3777; -defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_dec~3_combout & (!\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|fMRead~3_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|fMRead~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h7757; -defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h04CC; -defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|execute_|ixy_d~16_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & -// (((!\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|execute_|ixy_d~16_combout ))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|execute_|ixy_d~16_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h557F; -defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~3_combout & (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & \z80_|execute_|ctl_reg_sel_pc~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & -// (((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'h88F8; -defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~8_combout ) # (\z80_|execute_|ctl_mRead~17_combout )))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_reg_sel_pc~10_combout & (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .datab(\z80_|execute_|ctl_inc_cy~94_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout & -// !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~29_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|ir_|opcode [5]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~14_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h5455; -defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~49 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~49_combout = (!\z80_|pla_decode_|Equal35~0_combout & (((\z80_|ir_|opcode [3]) # (\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal24~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~49 .lut_mask = 16'h00FD; -defparam \z80_|execute_|pc_inc_hold~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_mRead~15_combout & (!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout )) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0A00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~28_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal33~2_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal50~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'h0515; -defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~35 ( -// Equation(s): -// \z80_|execute_|setM1~35_combout = (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~35 .lut_mask = 16'h0003; -defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~36 ( -// Equation(s): -// \z80_|execute_|setM1~36_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|execute_|ctl_mRead~9_combout & (\z80_|execute_|pc_inc_hold~28_combout & \z80_|execute_|setM1~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~28_combout ), - .datad(\z80_|execute_|setM1~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~36 .lut_mask = 16'h2000; -defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( -// Equation(s): -// \z80_|execute_|fMRead~5_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|setM1~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|setM1~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0100; -defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & (((\z80_|execute_|ctl_bus_inc_oe~29_combout & \z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'hA222; -defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'hC8C8; -defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~1_combout = (\z80_|execute_|pc_inc_hold~29_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(gnd), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'hEE00; -defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~2_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'h1113; -defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|pc_inc_hold~49_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|pc_inc_hold~49_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hF0B0; -defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~3_combout = (((\z80_|execute_|ctl_reg_sys_we~0_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout )) # (!\z80_|execute_|ctl_reg_sys_we~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~3 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_sys_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~2_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~3_combout = (\z80_|execute_|ctl_reg_sys_we_lo~2_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_reg_sys_we_lo~3_combout & \z80_|sequencer_|DFFE_M2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|execute_|ctl_reg_sys_we~3_combout ) # ((\z80_|execute_|ctl_reg_sys_we_lo~4_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~7_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hEFFF; -defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h3330; -defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_flags_bus~4_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_flags_bus~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hFF5D; -defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~34_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_inc_cy~34_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal48~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal48~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hF2F0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = (((\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'hBF3F; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_alu_oe~4_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) - - .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_alu_oe~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~4_combout = ((!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|pla_decode_|Equal3~1_combout ) # (!\z80_|pla_decode_|Equal19~1_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal19~1_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~4 .lut_mask = 16'h5777; -defparam \z80_|execute_|ctl_reg_sel_wz~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~5_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~5 .lut_mask = 16'h001F; -defparam \z80_|execute_|ctl_reg_sel_wz~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~6_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & \z80_|execute_|ctl_reg_sel_wz~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_in_hi~4_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & \z80_|execute_|ctl_reg_sel_wz~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~16_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~14_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .lut_mask = 16'h80C0; -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~16_combout & (((!\z80_|execute_|ctl_mRead~36_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'hE0F0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_al_we~13_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'h80AA; -defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|ctl_reg_sel_pc~12_combout & (\z80_|execute_|setM1~52_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ctl_mRead~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ixy_d~16_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h2022; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~0 ( -// Equation(s): -// \z80_|execute_|fMRead~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMRead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~0 .lut_mask = 16'h5D5D; -defparam \z80_|execute_|fMRead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal52~1_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h0030; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|fMRead~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h050F; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~4_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h0FAF; -defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_reg_sys_hilo~20_combout & ((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) # -// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datac(\z80_|execute_|ctl_inc_dec~4_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hD0DD; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~9_combout = (!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_ir_we~14_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_M2_ff~q )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout -// )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00C4; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~49_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h08CC; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~17_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h4455; -defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h5554; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & ((\z80_|execute_|fMRead~0_combout ) # ((!\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|pc_inc_hold~28_combout )))) - - .dataa(\z80_|execute_|fMRead~0_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h00BA; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_al_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h4404; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~18_combout = (\z80_|alu_control_|flags_cond_true~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~38_combout = ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~38_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_state_alu~14_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal6~1_combout & ((!\z80_|pla_decode_|Equal33~2_combout ) # (!\z80_|decode_state_|use_ixiy~combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~45_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~1 ( -// Equation(s): -// \z80_|execute_|fMRead~1_combout = ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~1 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|fMRead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|fMRead~1_combout ))) - - .dataa(\z80_|execute_|fMRead~1_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hF0D0; -defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~27_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_bus_inc_oe~47_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_bus_inc_oe~27_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~28_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~46_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_bus_inc_oe~45_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~37_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~39_combout & \z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~35_combout = ((\z80_|execute_|ctl_alu_oe~2_combout & ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout ) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~77_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_sw_4u~0_combout ), - .datac(\z80_|execute_|ctl_inc_cy~76_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ixy_d~9_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|pla_decode_|Equal10~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # -// (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|ctl_mWrite~2_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~33_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (\z80_|execute_|ctl_bus_inc_oe~32_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~34_combout = (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~53_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), - .datab(\z80_|execute_|ctl_inc_cy~77_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_bus_inc_oe~40_combout ) # (((\z80_|execute_|ctl_bus_inc_oe~35_combout ) # (\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~10_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # ((!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & -// (((!\z80_|execute_|ctl_alu_oe~2_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'hA0F3; -defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & \z80_|execute_|ctl_reg_sel_wz~10_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout )) - - .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ixy_d~6_combout & -// ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h2A3F; -defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|fMRead~6_combout ), - .datad(\z80_|execute_|fMRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_reg_sel_wz~11_combout & (\z80_|execute_|ctl_sw_4d~3_combout & (\z80_|execute_|ctl_sw_4d~4_combout & \z80_|execute_|ctl_sw_4d~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .datab(\z80_|execute_|ctl_sw_4d~3_combout ), - .datac(\z80_|execute_|ctl_sw_4d~4_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~45 ( -// Equation(s): -// \z80_|execute_|setM1~45_combout = (!\z80_|execute_|ctl_iorw~11_combout & (\z80_|execute_|ctl_mRead~19_combout & (!\z80_|execute_|ctl_mRead~13_combout & !\z80_|execute_|ctl_iorw~10_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_mRead~19_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0004; -defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~46 ( -// Equation(s): -// \z80_|execute_|setM1~46_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|setM1~45_combout & !\z80_|execute_|ctl_mWrite~6_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_al_we~13_combout ), - .datac(\z80_|execute_|setM1~45_combout ), - .datad(\z80_|execute_|ctl_mWrite~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~46 .lut_mask = 16'h00C0; -defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~1_combout = ((!\z80_|decode_state_|use_ixiy~combout & ((\z80_|pla_decode_|Equal50~0_combout ) # (\z80_|pla_decode_|Equal49~0_combout )))) # (!\z80_|execute_|setM1~46_combout ) - - .dataa(\z80_|pla_decode_|Equal50~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|execute_|setM1~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'h32FF; -defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_al_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_al_we~14_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~6_combout = ((\z80_|execute_|ctl_sw_4d~0_combout ) # ((\z80_|execute_|ctl_sw_4d~1_combout & \z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_sw_4d~5_combout ) - - .dataa(\z80_|execute_|ctl_sw_4d~5_combout ), - .datab(\z80_|execute_|ctl_sw_4d~1_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_sw_4d~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( -// Equation(s): -// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~4_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0A00; -defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|fMRead~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h5DFF; -defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal21~1_combout & (((\z80_|decode_state_|table_xx~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h00DF; -defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~20_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~20 .lut_mask = 16'h5010; -defparam \z80_|execute_|ctl_reg_sel_pc~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|setM1~36_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .datab(\z80_|execute_|setM1~36_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .datad(\z80_|execute_|fMRead~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hF0F7; -defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~17_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~18_combout = (((!\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'h4FFF; -defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~19_combout = ((\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (\z80_|execute_|ctl_reg_sel_pc~18_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & \z80_|execute_|ctl_reg_sel_wz~4_combout ))) - - .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h0800; -defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N18 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~combout = (!\z80_|execute_|ctl_reg_sel_wz~18_combout & (\z80_|execute_|ctl_reg_sel_pc~19_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|reg_control_|reg_sel_pc~3_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0400; -defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # ((\z80_|execute_|ctl_sw_4d~6_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|execute_|ctl_sw_4d~6_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[7]~92_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N25 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N26 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0F0F; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N27 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N9 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N29 -dffeas \z80_|resets_|DFFE_intr_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - // Location: IOIBUF_X53_Y14_N1 cycloneive_io_ibuf \KEY[0]~input ( .i(KEY[0]), @@ -15959,7 +5001,7 @@ defparam \KEY[0]~input .bus_hold = "false"; defparam \KEY[0]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X52_Y14_N4 +// Location: LCCOMB_X52_Y14_N12 cycloneive_lcell_comb reset( // Equation(s): // \reset~combout = (!\KEY[0]~input_o ) # (!\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ) @@ -15976,7 +5018,7 @@ defparam reset.lut_mask = 16'h0FFF; defparam reset.sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y13_N26 +// Location: LCCOMB_X52_Y14_N18 cycloneive_lcell_comb \z80_|resets_|x1~0 ( // Equation(s): // \z80_|resets_|x1~0_combout = !\reset~combout @@ -15993,7 +5035,7 @@ defparam \z80_|resets_|x1~0 .lut_mask = 16'h00FF; defparam \z80_|resets_|x1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N0 +// Location: LCCOMB_X26_Y32_N8 cycloneive_lcell_comb \z80_|fpga_reset~feeder ( // Equation(s): // \z80_|fpga_reset~feeder_combout = VCC @@ -16010,7 +5052,7 @@ defparam \z80_|fpga_reset~feeder .lut_mask = 16'hFFFF; defparam \z80_|fpga_reset~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N1 +// Location: FF_X26_Y32_N9 dffeas \z80_|fpga_reset ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|fpga_reset~feeder_combout ), @@ -16029,7 +5071,7 @@ defparam \z80_|fpga_reset .is_wysiwyg = "true"; defparam \z80_|fpga_reset .power_up = "low"; // synopsys translate_on -// Location: CLKCTRL_G12 +// Location: CLKCTRL_G10 cycloneive_clkctrl \z80_|fpga_reset~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\z80_|fpga_reset~q }), @@ -16042,7 +5084,7 @@ defparam \z80_|fpga_reset~clkctrl .clock_type = "global clock"; defparam \z80_|fpga_reset~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X35_Y13_N27 +// Location: FF_X52_Y14_N19 dffeas \z80_|resets_|x1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|resets_|x1~0_combout ), @@ -16061,1677 +5103,106 @@ defparam \z80_|resets_|x1 .is_wysiwyg = "true"; defparam \z80_|resets_|x1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y17_N18 -cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( +// Location: LCCOMB_X31_Y14_N0 +cycloneive_lcell_comb \z80_|resets_|x3 ( // Equation(s): -// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # -// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) +// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|resets_|clrpc_int~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), .datad(\z80_|resets_|x1~q ), .cin(gnd), - .combout(\z80_|resets_|clrpc_int~0_combout ), + .combout(\z80_|resets_|x3~combout ), .cout()); // synopsys translate_off -defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; -defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; +defparam \z80_|resets_|x3 .lut_mask = 16'hFF50; +defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y17_N19 -dffeas \z80_|resets_|clrpc_int ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|clrpc_int~0_combout ), +// Location: FF_X31_Y14_N1 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|x3~combout ), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(\z80_|fpga_reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|resets_|clrpc_int~q ), + .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; -defparam \z80_|resets_|clrpc_int .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N28 -cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( -// Equation(s): -// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_10~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|clrpc_int~q ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .datac(\z80_|resets_|DFFE_intr_ff3~q ), - .datad(\z80_|resets_|clrpc_int~q ), - .cin(gnd), - .combout(\z80_|resets_|clrpc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; -defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( -// Equation(s): -// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [7]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h5550; -defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )) # (!\z80_|execute_|ctl_al_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|execute_|ctl_al_we~14_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & (\z80_|execute_|ctl_ir_we~4_combout & -// ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_al_we~13_combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'h0EEE; -defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~8_combout = ((\z80_|execute_|ctl_al_we~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_al_we~7_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~9_combout = (((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout )) # (!\z80_|execute_|ctl_al_we~4_combout )) # (!\z80_|execute_|ctl_alu_oe~10_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~10_combout ), - .datab(\z80_|execute_|ctl_al_we~4_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~8_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_al_we~9_combout ) # (!\z80_|execute_|setM1~45_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~8_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|setM1~45_combout ), - .datad(\z80_|execute_|ctl_al_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEEAE; -defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~10_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) - - .dataa(\z80_|execute_|ctl_al_we~6_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_4d~5_combout ), - .datad(\z80_|execute_|ctl_al_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFFAF; -defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~12_combout = (\z80_|execute_|ctl_al_we~11_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|setM1~52_combout )) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_al_we~11_combout ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N5 -dffeas \z80_|address_latch_|Q[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [7]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~6_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( -// Equation(s): -// \z80_|execute_|fIOWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h3373; -defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~4_combout & (((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|fIOWrite~0_combout )) # (!\z80_|execute_|ctl_inc_dec~4_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~4_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~9_combout = ((\z80_|execute_|ctl_inc_dec~8_combout ) # ((!\z80_|execute_|ctl_reg_gp_we~0_combout & \z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_inc_dec~3_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_inc_dec~3_combout ), - .datad(\z80_|execute_|ctl_inc_dec~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hFF4F; -defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|execute_|ctl_inc_dec~9_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hF3F3; -defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout ) - - .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h55FF; -defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N1 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N3 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hCA00; -defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h1000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|gdfx_temp0[2]~36_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hA2A2; -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|alu_control_|db[2]~29_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|alu_control_|db[2]~29_combout & -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) - - .dataa(\z80_|alu_control_|db[2]~29_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .datac(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'h8CAF; -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_iy~2_combout = (\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0020; -defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|reg_control_|reg_sel_iy~2_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N15 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~42_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N29 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~37_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & \z80_|reg_file_|gdfx_temp0[2]~35_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~40_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~42_combout = ((\z80_|reg_file_|gdfx_temp0[2]~41_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[2]~42_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .datad(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|gdfx_temp0[0]~10_combout & (\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .datab(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'h8088; -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder ( +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( // Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout +// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .sum_lutc_input = "datac"; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hFF0F; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), +// Location: FF_X35_Y10_N1 +dffeas \z80_|interrupts_|nmi_armed ( + .clk(!\KEY[1]~input_o ), + .d(\z80_|interrupts_|nmi_armed~feeder_combout ), .asdata(vcc), - .clrn(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .q(\z80_|interrupts_|nmi_armed~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; +defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; +defparam \z80_|interrupts_|nmi_armed .power_up = "low"; // synopsys translate_on -// Location: FF_X29_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), +// Location: CLKCTRL_G7 +cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), + .clkselect(2'b00), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .prn(vcc)); + .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X29_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( +// Location: LCCOMB_X32_Y12_N30 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~15_combout & (\z80_|reg_file_|gdfx_temp0[0]~14_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .datad(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hA200; -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[0]~12_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .datad(\z80_|alu_control_|db[0]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N7 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~11_combout & (\z80_|reg_file_|gdfx_temp0[0]~16_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & \z80_|reg_file_|gdfx_temp0[0]~13_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hC4FF; -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|reg_file_|gdfx_temp0[0]~22_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) +// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) .dataa(gnd), - .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hCF00; -defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~72_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF33; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; // synopsys translate_on // Location: CLKCTRL_G18 @@ -17747,158 +5218,33 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add0~14 ( -// Equation(s): -// \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) -// \ula_|video_|Add0~15 = CARRY((!\ula_|video_|Add0~13 ) # (!\ula_|video_|vga_hc [7])) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~13 ), - .combout(\ula_|video_|Add0~14_combout ), - .cout(\ula_|video_|Add0~15 )); -// synopsys translate_off -defparam \ula_|video_|Add0~14 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Add0~16 ( -// Equation(s): -// \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) -// \ula_|video_|Add0~17 = CARRY((\ula_|video_|vga_hc [8] & !\ula_|video_|Add0~15 )) - - .dataa(\ula_|video_|vga_hc [8]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~15 ), - .combout(\ula_|video_|Add0~16_combout ), - .cout(\ula_|video_|Add0~17 )); -// synopsys translate_off -defparam \ula_|video_|Add0~16 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N26 -cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( -// Equation(s): -// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Equal1~0_combout ), - .datad(\ula_|video_|Add0~16_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hF000; -defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y33_N27 -dffeas \ula_|video_|vga_hc[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N20 -cycloneive_lcell_comb \ula_|video_|Add0~18 ( -// Equation(s): -// \ula_|video_|Add0~18_combout = \ula_|video_|Add0~17 $ (\ula_|video_|vga_hc [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [9]), - .cin(\ula_|video_|Add0~17 ), - .combout(\ula_|video_|Add0~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add0~18 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( -// Equation(s): -// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~18_combout ) - - .dataa(gnd), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(gnd), - .datad(\ula_|video_|Add0~18_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hCC00; -defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y33_N21 -dffeas \ula_|video_|vga_hc[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N2 +// Location: LCCOMB_X29_Y30_N8 cycloneive_lcell_comb \ula_|video_|Add0~0 ( // Equation(s): // \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) // \ula_|video_|Add0~1 = CARRY(\ula_|video_|vga_hc [0]) - .dataa(gnd), - .datab(\ula_|video_|vga_hc [0]), + .dataa(\ula_|video_|vga_hc [0]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(gnd), .combout(\ula_|video_|Add0~0_combout ), .cout(\ula_|video_|Add0~1 )); // synopsys translate_off -defparam \ula_|video_|Add0~0 .lut_mask = 16'h33CC; +defparam \ula_|video_|Add0~0 .lut_mask = 16'h55AA; defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N0 +// Location: LCCOMB_X29_Y29_N14 cycloneive_lcell_comb \ula_|video_|vga_hc~3 ( // Equation(s): -// \ula_|video_|vga_hc~3_combout = (\ula_|video_|Add0~0_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~3_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~0_combout ) .dataa(gnd), .datab(gnd), - .datac(\ula_|video_|Add0~0_combout ), - .datad(\ula_|video_|Equal1~0_combout ), + .datac(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~0_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~3_combout ), .cout()); @@ -17907,7 +5253,7 @@ defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hF000; defparam \ula_|video_|vga_hc~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y31_N1 +// Location: FF_X29_Y29_N15 dffeas \ula_|video_|vga_hc[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_hc~3_combout ), @@ -17926,7 +5272,7 @@ defparam \ula_|video_|vga_hc[0] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N4 +// Location: LCCOMB_X29_Y30_N10 cycloneive_lcell_comb \ula_|video_|Add0~2 ( // Equation(s): // \ula_|video_|Add0~2_combout = (\ula_|video_|vga_hc [1] & (!\ula_|video_|Add0~1 )) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|Add0~1 ) # (GND))) @@ -17944,7 +5290,7 @@ defparam \ula_|video_|Add0~2 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N16 +// Location: LCCOMB_X30_Y30_N22 cycloneive_lcell_comb \ula_|video_|vga_hc[1]~feeder ( // Equation(s): // \ula_|video_|vga_hc[1]~feeder_combout = \ula_|video_|Add0~2_combout @@ -17961,7 +5307,7 @@ defparam \ula_|video_|vga_hc[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|vga_hc[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N17 +// Location: FF_X30_Y30_N23 dffeas \ula_|video_|vga_hc[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_hc[1]~feeder_combout ), @@ -17980,7 +5326,7 @@ defparam \ula_|video_|vga_hc[1] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N6 +// Location: LCCOMB_X29_Y30_N12 cycloneive_lcell_comb \ula_|video_|Add0~4 ( // Equation(s): // \ula_|video_|Add0~4_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add0~3 $ (GND))) # (!\ula_|video_|vga_hc [2] & (!\ula_|video_|Add0~3 & VCC)) @@ -17998,7 +5344,7 @@ defparam \ula_|video_|Add0~4 .lut_mask = 16'hC30C; defparam \ula_|video_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X39_Y33_N23 +// Location: FF_X29_Y30_N31 dffeas \ula_|video_|vga_hc[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -18017,50 +5363,33 @@ defparam \ula_|video_|vga_hc[2] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N8 +// Location: LCCOMB_X29_Y30_N14 cycloneive_lcell_comb \ula_|video_|Add0~6 ( // Equation(s): // \ula_|video_|Add0~6_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|Add0~5 )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Add0~5 ) # (GND))) // \ula_|video_|Add0~7 = CARRY((!\ula_|video_|Add0~5 ) # (!\ula_|video_|vga_hc [3])) - .dataa(gnd), - .datab(\ula_|video_|vga_hc [3]), + .dataa(\ula_|video_|vga_hc [3]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~5 ), .combout(\ula_|video_|Add0~6_combout ), .cout(\ula_|video_|Add0~7 )); // synopsys translate_off -defparam \ula_|video_|Add0~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add0~6 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N8 -cycloneive_lcell_comb \ula_|video_|vga_hc[3]~feeder ( -// Equation(s): -// \ula_|video_|vga_hc[3]~feeder_combout = \ula_|video_|Add0~6_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Add0~6_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vga_hc[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y33_N9 +// Location: FF_X30_Y30_N11 dffeas \ula_|video_|vga_hc[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc[3]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|Add0~6_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18071,7 +5400,7 @@ defparam \ula_|video_|vga_hc[3] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N10 +// Location: LCCOMB_X29_Y30_N16 cycloneive_lcell_comb \ula_|video_|Add0~8 ( // Equation(s): // \ula_|video_|Add0~8_combout = (\ula_|video_|vga_hc [4] & (\ula_|video_|Add0~7 $ (GND))) # (!\ula_|video_|vga_hc [4] & (!\ula_|video_|Add0~7 & VCC)) @@ -18089,7 +5418,7 @@ defparam \ula_|video_|Add0~8 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X39_Y33_N31 +// Location: FF_X29_Y30_N7 dffeas \ula_|video_|vga_hc[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -18108,101 +5437,50 @@ defparam \ula_|video_|vga_hc[4] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N18 -cycloneive_lcell_comb \ula_|video_|Equal0~0 ( -// Equation(s): -// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N30 -cycloneive_lcell_comb \ula_|video_|Equal0~1 ( -// Equation(s): -// \ula_|video_|Equal0~1_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [7] & (!\ula_|video_|vga_hc [4] & \ula_|video_|Equal0~0_combout ))) - - .dataa(\ula_|video_|vga_hc [5]), - .datab(\ula_|video_|vga_hc [7]), - .datac(\ula_|video_|vga_hc [4]), - .datad(\ula_|video_|Equal0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0200; -defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Equal1~0 ( -// Equation(s): -// \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|Equal0~1_combout )) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9]) - - .dataa(\ula_|video_|vga_hc [9]), - .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal1~0 .lut_mask = 16'hF7FF; -defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N12 +// Location: LCCOMB_X29_Y30_N18 cycloneive_lcell_comb \ula_|video_|Add0~10 ( // Equation(s): // \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) // \ula_|video_|Add0~11 = CARRY((!\ula_|video_|Add0~9 ) # (!\ula_|video_|vga_hc [5])) - .dataa(\ula_|video_|vga_hc [5]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [5]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~9 ), .combout(\ula_|video_|Add0~10_combout ), .cout(\ula_|video_|Add0~11 )); // synopsys translate_off -defparam \ula_|video_|Add0~10 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add0~10 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N0 +// Location: LCCOMB_X29_Y30_N30 cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( // Equation(s): -// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~10_combout ) +// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Add0~10_combout & \ula_|video_|Equal1~0_combout ) .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Equal1~0_combout ), - .datad(\ula_|video_|Add0~10_combout ), + .datab(\ula_|video_|Add0~10_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hF000; +defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hCC00; defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y33_N1 +// Location: FF_X29_Y30_N1 dffeas \ula_|video_|vga_hc[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~0_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|vga_hc~0_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18213,25 +5491,25 @@ defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N14 +// Location: LCCOMB_X29_Y30_N20 cycloneive_lcell_comb \ula_|video_|Add0~12 ( // Equation(s): // \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) // \ula_|video_|Add0~13 = CARRY((\ula_|video_|vga_hc [6] & !\ula_|video_|Add0~11 )) - .dataa(\ula_|video_|vga_hc [6]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [6]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~11 ), .combout(\ula_|video_|Add0~12_combout ), .cout(\ula_|video_|Add0~13 )); // synopsys translate_off -defparam \ula_|video_|Add0~12 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add0~12 .lut_mask = 16'hC30C; defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X39_Y33_N29 +// Location: FF_X29_Y30_N29 dffeas \ula_|video_|vga_hc[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -18250,7 +5528,25 @@ defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X39_Y33_N25 +// Location: LCCOMB_X29_Y30_N22 +cycloneive_lcell_comb \ula_|video_|Add0~14 ( +// Equation(s): +// \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) +// \ula_|video_|Add0~15 = CARRY((!\ula_|video_|Add0~13 ) # (!\ula_|video_|vga_hc [7])) + + .dataa(\ula_|video_|vga_hc [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~13 ), + .combout(\ula_|video_|Add0~14_combout ), + .cout(\ula_|video_|Add0~15 )); +// synopsys translate_off +defparam \ula_|video_|Add0~14 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y30_N3 dffeas \ula_|video_|vga_hc[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -18269,578 +5565,218 @@ defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N0 +// Location: LCCOMB_X30_Y29_N12 +cycloneive_lcell_comb \ula_|video_|Equal0~0 ( +// Equation(s): +// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [0] & (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [1]))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N26 +cycloneive_lcell_comb \ula_|video_|Equal0~1 ( +// Equation(s): +// \ula_|video_|Equal0~1_combout = (!\ula_|video_|vga_hc [7] & (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [4] & \ula_|video_|Equal0~0_combout ))) + + .dataa(\ula_|video_|vga_hc [7]), + .datab(\ula_|video_|vga_hc [5]), + .datac(\ula_|video_|vga_hc [4]), + .datad(\ula_|video_|Equal0~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0400; +defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N24 +cycloneive_lcell_comb \ula_|video_|Add0~16 ( +// Equation(s): +// \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) +// \ula_|video_|Add0~17 = CARRY((\ula_|video_|vga_hc [8] & !\ula_|video_|Add0~15 )) + + .dataa(\ula_|video_|vga_hc [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~15 ), + .combout(\ula_|video_|Add0~16_combout ), + .cout(\ula_|video_|Add0~17 )); +// synopsys translate_off +defparam \ula_|video_|Add0~16 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N28 +cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( +// Equation(s): +// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Add0~16_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Add0~16_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y30_N17 +dffeas \ula_|video_|vga_hc[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~2_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N26 +cycloneive_lcell_comb \ula_|video_|Add0~18 ( +// Equation(s): +// \ula_|video_|Add0~18_combout = \ula_|video_|vga_hc [9] $ (\ula_|video_|Add0~17 ) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [9]), + .datac(gnd), + .datad(gnd), + .cin(\ula_|video_|Add0~17 ), + .combout(\ula_|video_|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add0~18 .lut_mask = 16'h3C3C; +defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N2 +cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( +// Equation(s): +// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Add0~18_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Add0~18_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y30_N5 +dffeas \ula_|video_|vga_hc[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~1_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N0 +cycloneive_lcell_comb \ula_|video_|Equal1~0 ( +// Equation(s): +// \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9])) # (!\ula_|video_|Equal0~1_combout ) + + .dataa(\ula_|video_|Equal0~1_combout ), + .datab(\ula_|video_|vga_hc [9]), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [8]), + .cin(gnd), + .combout(\ula_|video_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal1~0 .lut_mask = 16'hF7FF; +defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N0 cycloneive_lcell_comb \ula_|video_|Add1~0 ( // Equation(s): // \ula_|video_|Add1~0_combout = \ula_|video_|vga_vc [0] $ (VCC) // \ula_|video_|Add1~1 = CARRY(\ula_|video_|vga_vc [0]) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [0]), + .dataa(\ula_|video_|vga_vc [0]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(gnd), .combout(\ula_|video_|Add1~0_combout ), .cout(\ula_|video_|Add1~1 )); // synopsys translate_off -defparam \ula_|video_|Add1~0 .lut_mask = 16'h33CC; +defparam \ula_|video_|Add1~0 .lut_mask = 16'h55AA; defparam \ula_|video_|Add1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N2 +// Location: LCCOMB_X32_Y29_N2 cycloneive_lcell_comb \ula_|video_|Add1~2 ( // Equation(s): // \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) // \ula_|video_|Add1~3 = CARRY((!\ula_|video_|Add1~1 ) # (!\ula_|video_|vga_vc [1])) - .dataa(\ula_|video_|vga_vc [1]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [1]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~1 ), .combout(\ula_|video_|Add1~2_combout ), .cout(\ula_|video_|Add1~3 )); // synopsys translate_off -defparam \ula_|video_|Add1~2 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add1~2 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Add1~4 ( -// Equation(s): -// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) -// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) - - .dataa(\ula_|video_|vga_vc [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~3 ), - .combout(\ula_|video_|Add1~4_combout ), - .cout(\ula_|video_|Add1~5 )); -// synopsys translate_off -defparam \ula_|video_|Add1~4 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N12 -cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( -// Equation(s): -// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [2]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~4_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~4_combout ), - .datac(\ula_|video_|vga_vc [2]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N13 -dffeas \ula_|video_|vga_vc[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[2]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N6 -cycloneive_lcell_comb \ula_|video_|Add1~6 ( -// Equation(s): -// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) -// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~5 ), - .combout(\ula_|video_|Add1~6_combout ), - .cout(\ula_|video_|Add1~7 )); -// synopsys translate_off -defparam \ula_|video_|Add1~6 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( -// Equation(s): -// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) - - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|Add1~6_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h5140; -defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N3 -dffeas \ula_|video_|vga_vc[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_vc[3]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N8 -cycloneive_lcell_comb \ula_|video_|Add1~8 ( -// Equation(s): -// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) -// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~7 ), - .combout(\ula_|video_|Add1~8_combout ), - .cout(\ula_|video_|Add1~9 )); -// synopsys translate_off -defparam \ula_|video_|Add1~8 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( -// Equation(s): -// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~8_combout ), - .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[4]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N21 -dffeas \ula_|video_|vga_vc[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[4]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N10 -cycloneive_lcell_comb \ula_|video_|Add1~10 ( -// Equation(s): -// \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) -// \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~9 ), - .combout(\ula_|video_|Add1~10_combout ), - .cout(\ula_|video_|Add1~11 )); -// synopsys translate_off -defparam \ula_|video_|Add1~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N22 -cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( -// Equation(s): -// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [5])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~10_combout ))))) - - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(\ula_|video_|vga_vc [5]), - .datad(\ula_|video_|Add1~10_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[5]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h5140; -defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N17 -dffeas \ula_|video_|vga_vc[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_vc[5]~8_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N12 -cycloneive_lcell_comb \ula_|video_|Add1~12 ( -// Equation(s): -// \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) -// \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [6]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~11 ), - .combout(\ula_|video_|Add1~12_combout ), - .cout(\ula_|video_|Add1~13 )); -// synopsys translate_off -defparam \ula_|video_|Add1~12 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N6 -cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( -// Equation(s): -// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [6]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~12_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~12_combout ), - .datac(\ula_|video_|vga_vc [6]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[6]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N7 -dffeas \ula_|video_|vga_vc[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[6]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Add1~14 ( -// Equation(s): -// \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) -// \ula_|video_|Add1~15 = CARRY((!\ula_|video_|Add1~13 ) # (!\ula_|video_|vga_vc [7])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~13 ), - .combout(\ula_|video_|Add1~14_combout ), - .cout(\ula_|video_|Add1~15 )); -// synopsys translate_off -defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N14 -cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( -// Equation(s): -// \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~14_combout ), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[7]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N15 -dffeas \ula_|video_|vga_vc[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[7]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add1~16 ( -// Equation(s): -// \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) -// \ula_|video_|Add1~17 = CARRY((\ula_|video_|vga_vc [8] & !\ula_|video_|Add1~15 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [8]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~15 ), - .combout(\ula_|video_|Add1~16_combout ), - .cout(\ula_|video_|Add1~17 )); -// synopsys translate_off -defparam \ula_|video_|Add1~16 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N24 -cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( -// Equation(s): -// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~16_combout ), - .datac(\ula_|video_|vga_vc [8]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[8]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N25 -dffeas \ula_|video_|vga_vc[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[8]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Add1~18 ( -// Equation(s): -// \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_vc [9]), - .cin(\ula_|video_|Add1~17 ), - .combout(\ula_|video_|Add1~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N10 -cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( -// Equation(s): -// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [9]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~18_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~18_combout ), - .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[9]~9_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N11 -dffeas \ula_|video_|vga_vc[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[9]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Equal2~0 ( -// Equation(s): -// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [4] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [4]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [8]), - .cin(gnd), - .combout(\ula_|video_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y33_N30 -cycloneive_lcell_comb \ula_|video_|Equal3~0 ( -// Equation(s): -// \ula_|video_|Equal3~0_combout = (\ula_|video_|vga_vc [3] & (\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [1] & \ula_|video_|vga_vc [0]))) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal3~0 .lut_mask = 16'h0800; -defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Equal3~1 ( -// Equation(s): -// \ula_|video_|Equal3~1_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal2~0_combout & \ula_|video_|Equal3~0_combout ))) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|Equal2~0_combout ), - .datad(\ula_|video_|Equal3~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal3~1 .lut_mask = 16'h4000; -defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N28 -cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( -// Equation(s): -// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [0]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~0_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~0_combout ), - .datac(\ula_|video_|vga_vc [0]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N29 -dffeas \ula_|video_|vga_vc[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[0]~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N22 +// Location: LCCOMB_X32_Y30_N30 cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( // Equation(s): -// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [1]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~2_combout )))) +// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [1])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~2_combout ))))) .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~2_combout ), + .datab(\ula_|video_|Equal3~1_combout ), .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|Equal3~1_combout ), + .datad(\ula_|video_|Add1~2_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h3120; defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y33_N23 +// Location: FF_X32_Y30_N31 dffeas \ula_|video_|vga_vc[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[1]~1_combout ), @@ -18859,6 +5795,558 @@ defparam \ula_|video_|vga_vc[1] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[1] .power_up = "low"; // synopsys translate_on +// Location: LCCOMB_X32_Y29_N4 +cycloneive_lcell_comb \ula_|video_|Add1~4 ( +// Equation(s): +// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) +// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~3 ), + .combout(\ula_|video_|Add1~4_combout ), + .cout(\ula_|video_|Add1~5 )); +// synopsys translate_off +defparam \ula_|video_|Add1~4 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N20 +cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( +// Equation(s): +// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [2]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~4_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~4_combout ), + .datac(\ula_|video_|vga_vc [2]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y30_N21 +dffeas \ula_|video_|vga_vc[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[2]~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N6 +cycloneive_lcell_comb \ula_|video_|Add1~6 ( +// Equation(s): +// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) +// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~5 ), + .combout(\ula_|video_|Add1~6_combout ), + .cout(\ula_|video_|Add1~7 )); +// synopsys translate_off +defparam \ula_|video_|Add1~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N26 +cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( +// Equation(s): +// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|Add1~6_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y30_N27 +dffeas \ula_|video_|vga_vc[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[3]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N8 +cycloneive_lcell_comb \ula_|video_|Add1~8 ( +// Equation(s): +// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) +// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~7 ), + .combout(\ula_|video_|Add1~8_combout ), + .cout(\ula_|video_|Add1~9 )); +// synopsys translate_off +defparam \ula_|video_|Add1~8 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N22 +cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( +// Equation(s): +// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~8_combout ), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y30_N23 +dffeas \ula_|video_|vga_vc[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[4]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N10 +cycloneive_lcell_comb \ula_|video_|Add1~10 ( +// Equation(s): +// \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) +// \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~9 ), + .combout(\ula_|video_|Add1~10_combout ), + .cout(\ula_|video_|Add1~11 )); +// synopsys translate_off +defparam \ula_|video_|Add1~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N8 +cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( +// Equation(s): +// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [5])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~10_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Add1~10_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[5]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y30_N9 +dffeas \ula_|video_|vga_vc[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[5]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N12 +cycloneive_lcell_comb \ula_|video_|Add1~12 ( +// Equation(s): +// \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) +// \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~11 ), + .combout(\ula_|video_|Add1~12_combout ), + .cout(\ula_|video_|Add1~13 )); +// synopsys translate_off +defparam \ula_|video_|Add1~12 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N16 +cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( +// Equation(s): +// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [6])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~12_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [6]), + .datad(\ula_|video_|Add1~12_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[6]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y30_N17 +dffeas \ula_|video_|vga_vc[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[6]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N14 +cycloneive_lcell_comb \ula_|video_|Add1~14 ( +// Equation(s): +// \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) +// \ula_|video_|Add1~15 = CARRY((!\ula_|video_|Add1~13 ) # (!\ula_|video_|vga_vc [7])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [7]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~13 ), + .combout(\ula_|video_|Add1~14_combout ), + .cout(\ula_|video_|Add1~15 )); +// synopsys translate_off +defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N22 +cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( +// Equation(s): +// \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~14_combout ), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[7]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y30_N23 +dffeas \ula_|video_|vga_vc[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[7]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N16 +cycloneive_lcell_comb \ula_|video_|Add1~16 ( +// Equation(s): +// \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) +// \ula_|video_|Add1~17 = CARRY((\ula_|video_|vga_vc [8] & !\ula_|video_|Add1~15 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [8]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~15 ), + .combout(\ula_|video_|Add1~16_combout ), + .cout(\ula_|video_|Add1~17 )); +// synopsys translate_off +defparam \ula_|video_|Add1~16 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N20 +cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( +// Equation(s): +// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~16_combout ), + .datac(\ula_|video_|vga_vc [8]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[8]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y30_N21 +dffeas \ula_|video_|vga_vc[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[8]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N18 +cycloneive_lcell_comb \ula_|video_|Add1~18 ( +// Equation(s): +// \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc [9]), + .cin(\ula_|video_|Add1~17 ), + .combout(\ula_|video_|Add1~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N8 +cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( +// Equation(s): +// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [9])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~18_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [9]), + .datad(\ula_|video_|Add1~18_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y30_N9 +dffeas \ula_|video_|vga_vc[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[9]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N10 +cycloneive_lcell_comb \ula_|video_|Equal3~0 ( +// Equation(s): +// \ula_|video_|Equal3~0_combout = (!\ula_|video_|vga_vc [1] & (\ula_|video_|vga_vc [2] & (\ula_|video_|vga_vc [3] & \ula_|video_|vga_vc [0]))) + + .dataa(\ula_|video_|vga_vc [1]), + .datab(\ula_|video_|vga_vc [2]), + .datac(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|vga_vc [0]), + .cin(gnd), + .combout(\ula_|video_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal3~0 .lut_mask = 16'h4000; +defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N30 +cycloneive_lcell_comb \ula_|video_|Equal2~0 ( +// Equation(s): +// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [4]))) + + .dataa(\ula_|video_|vga_vc [8]), + .datab(\ula_|video_|vga_vc [6]), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|vga_vc [4]), + .cin(gnd), + .combout(\ula_|video_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N16 +cycloneive_lcell_comb \ula_|video_|Equal3~1 ( +// Equation(s): +// \ula_|video_|Equal3~1_combout = (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal3~0_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) + + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|Equal3~0_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Equal2~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal3~1 .lut_mask = 16'h0800; +defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N24 +cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( +// Equation(s): +// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [0])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~0_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [0]), + .datad(\ula_|video_|Add1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y30_N25 +dffeas \ula_|video_|vga_vc[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N18 +cycloneive_lcell_comb \ula_|video_|Equal2~1 ( +// Equation(s): +// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [0] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & !\ula_|video_|vga_vc [9]))) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [2]), + .datac(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|vga_vc [9]), + .cin(gnd), + .combout(\ula_|video_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal2~1 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N12 +cycloneive_lcell_comb \ula_|video_|Equal2~2 ( +// Equation(s): +// \ula_|video_|Equal2~2_combout = (\ula_|video_|Equal2~1_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout )) + + .dataa(\ula_|video_|Equal2~1_combout ), + .datab(gnd), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Equal2~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal2~2 .lut_mask = 16'h0A00; +defparam \ula_|video_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: IOIBUF_X27_Y0_N15 cycloneive_io_ibuf \SW[1]~input ( .i(SW[1]), @@ -18869,15 +6357,15 @@ defparam \SW[1]~input .bus_hold = "false"; defparam \SW[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X34_Y33_N30 +// Location: LCCOMB_X31_Y27_N2 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_vc [1] & (!\SW[1]~input_o & !\ula_|video_|vga_hc [9]))) +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_vc [1] & (!\ula_|video_|vga_hc [9] & !\SW[1]~input_o ))) .dataa(\ula_|video_|vga_hc [8]), .datab(\ula_|video_|vga_vc [1]), - .datac(\SW[1]~input_o ), - .datad(\ula_|video_|vga_hc [9]), + .datac(\ula_|video_|vga_hc [9]), + .datad(\SW[1]~input_o ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), .cout()); @@ -18886,18144 +6374,249 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .lut_mask = 16'h0001; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( +// Location: LCCOMB_X30_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( // Equation(s): -// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal79~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N16 -cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( -// Equation(s): -// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|interrupts_|DFFE_instIFF2~q -// ))))) # (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal79~0_combout ), - .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hB8F0; -defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N28 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|interrupts_|DFFE_inst44~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h7733; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G16 -cycloneive_clkctrl \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: FF_X35_Y17_N17 -dffeas \z80_|interrupts_|DFFE_instIFF2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|DFFE_instIFF2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N2 -cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( -// Equation(s): -// \z80_|interrupts_|iff1~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|interrupts_|iff1~q ), - .datac(\z80_|pla_decode_|Equal79~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|interrupts_|iff1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hEC4C; -defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N18 -cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( -// Equation(s): -// \z80_|interrupts_|iff1~1_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|pla_decode_|Equal38~2_combout & ((\z80_|interrupts_|iff1~0_combout ))))) # -// (!\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|interrupts_|iff1~0_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|interrupts_|DFFE_instIFF2~q ), - .datac(\z80_|pla_decode_|Equal38~2_combout ), - .datad(\z80_|interrupts_|iff1~0_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|iff1~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hDF80; -defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N12 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|interrupts_|DFFE_inst44~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFF3; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N19 -dffeas \z80_|interrupts_|iff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|iff1~1_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|iff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|iff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Equal2~1 ( -// Equation(s): -// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [3] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [0]))) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal2~1 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Equal2~2 ( -// Equation(s): -// \ula_|video_|Equal2~2_combout = (\ula_|video_|Equal2~1_combout & (\ula_|video_|Equal2~0_combout & !\ula_|video_|vga_vc [5])) - - .dataa(gnd), - .datab(\ula_|video_|Equal2~1_combout ), - .datac(\ula_|video_|Equal2~0_combout ), - .datad(\ula_|video_|vga_vc [5]), - .cin(gnd), - .combout(\ula_|video_|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal2~2 .lut_mask = 16'h00C0; -defparam \ula_|video_|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y31_N28 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (!\ula_|video_|vga_hc [7] & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & (\z80_|interrupts_|iff1~q & \ula_|video_|Equal2~2_combout ))) - - .dataa(\ula_|video_|vga_hc [7]), - .datab(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), - .datac(\z80_|interrupts_|iff1~q ), - .datad(\ula_|video_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h4000; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y31_N29 -dffeas \z80_|interrupts_|int_armed ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|int_armed~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; -defparam \z80_|interrupts_|int_armed .power_up = "low"; -// synopsys translate_on - -// Location: FF_X32_Y15_N11 -dffeas \z80_|interrupts_|DFFE_inst44 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|interrupts_|int_armed~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|interrupts_|test1~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|DFFE_inst44~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~38 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~38_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|decode_state_|in_halt~q ) # (\z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .datab(gnd), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~38 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|pc_inc_hold~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~91 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~91_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~91 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~45 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~45_combout = (\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) # (!\z80_|pla_decode_|Equal19~0_combout & -// (((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~45 .lut_mask = 16'hF888; -defparam \z80_|execute_|pc_inc_hold~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~44 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~44_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((!\z80_|execute_|pc_inc_hold~49_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|pc_inc_hold~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~44 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|pc_inc_hold~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~46 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~46_combout = (\z80_|execute_|pc_inc_hold~45_combout ) # ((\z80_|execute_|pc_inc_hold~44_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~49_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~45_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|pc_inc_hold~44_combout ), - .datad(\z80_|execute_|pc_inc_hold~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~46 .lut_mask = 16'hFAFE; -defparam \z80_|execute_|pc_inc_hold~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~37 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~37_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|pc_inc_hold~29_combout ) # ((\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & -// (\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~37 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|pc_inc_hold~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~50 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~50_combout = (\z80_|execute_|pc_inc_hold~37_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|execute_|pc_inc_hold~37_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~50 .lut_mask = 16'hECCC; -defparam \z80_|execute_|pc_inc_hold~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~33_combout = (\z80_|execute_|ctl_mRead~10_combout & (((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|pla_decode_|Equal6~1_combout & -// ((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~2_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|pc_inc_hold~28_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|execute_|pc_inc_hold~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hECEE; -defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|execute_|ctl_mRead~15_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hEEA0; -defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|execute_|pc_inc_hold~33_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # ((\z80_|execute_|pc_inc_hold~31_combout ) # (\z80_|execute_|pc_inc_hold~32_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~33_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|pc_inc_hold~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~51 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~51_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ixy_d~15_combout ), .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~51_combout ), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~51 .lut_mask = 16'h57FF; -defparam \z80_|execute_|pc_inc_hold~51 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( +// Location: LCCOMB_X37_Y6_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) +// \z80_|execute_|ctl_mWrite~4_combout = (\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~30_combout ), + .combout(\z80_|execute_|ctl_mWrite~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~52 ( +// Location: LCCOMB_X36_Y6_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal0~0 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~52_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~52 .lut_mask = 16'hA800; -defparam \z80_|execute_|pc_inc_hold~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~35_combout = (!\z80_|execute_|pc_inc_hold~34_combout & (\z80_|execute_|pc_inc_hold~51_combout & (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~52_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~34_combout ), - .datab(\z80_|execute_|pc_inc_hold~51_combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|pc_inc_hold~52_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'h0040; -defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~36_combout = ((\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|execute_|pc_inc_hold~35_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hCF8F; -defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~44_combout = (((!\z80_|pla_decode_|Equal21~0_combout & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ixy_d~10_combout )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~45_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_inc_cy~44_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~50_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_inc_cy~44_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~43 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~43_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~43 .lut_mask = 16'hC080; -defparam \z80_|execute_|pc_inc_hold~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~71_combout = (\z80_|execute_|ctl_inc_cy~91_combout & (!\z80_|execute_|pc_inc_hold~46_combout & (\z80_|execute_|ctl_inc_cy~45_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~91_combout ), - .datab(\z80_|execute_|pc_inc_hold~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~45_combout ), - .datad(\z80_|execute_|pc_inc_hold~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~73_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~72_combout & \z80_|execute_|ctl_inc_cy~71_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_inc_cy~72_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~71_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_mWrite~16_combout & ((\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'h8C00; -defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~53 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~53_combout = (\z80_|pla_decode_|Equal11~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~53 .lut_mask = 16'hE000; -defparam \z80_|execute_|pc_inc_hold~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~39 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~39_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~53_combout & (\z80_|execute_|pc_inc_hold~35_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~50_combout ), - .datab(\z80_|execute_|pc_inc_hold~53_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~39 .lut_mask = 16'h0010; -defparam \z80_|execute_|pc_inc_hold~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~47 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~47_combout = (\z80_|execute_|pc_inc_hold~46_combout ) # ((\z80_|execute_|pc_inc_hold~43_combout ) # ((!\z80_|execute_|ctl_inc_cy~44_combout ) # (!\z80_|execute_|pc_inc_hold~39_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~46_combout ), - .datab(\z80_|execute_|pc_inc_hold~43_combout ), - .datac(\z80_|execute_|pc_inc_hold~39_combout ), - .datad(\z80_|execute_|ctl_inc_cy~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~47 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|pc_inc_hold~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~74_combout = (((!\z80_|execute_|ctl_inc_cy~40_combout ) # (!\z80_|execute_|ctl_inc_cy~34_combout )) # (!\z80_|execute_|ctl_inc_cy~35_combout )) # (!\z80_|execute_|ctl_inc_cy~43_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~43_combout ), - .datab(\z80_|execute_|ctl_inc_cy~35_combout ), - .datac(\z80_|execute_|ctl_inc_cy~34_combout ), - .datad(\z80_|execute_|ctl_inc_cy~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~78_combout = ((\z80_|execute_|ctl_inc_cy~74_combout ) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~39_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~39_combout ), - .datac(\z80_|execute_|ctl_inc_cy~77_combout ), - .datad(\z80_|execute_|ctl_inc_cy~74_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (((!\z80_|execute_|pc_inc_hold~47_combout & \z80_|execute_|ctl_inc_cy~91_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~47_combout ), - .datab(\z80_|execute_|ctl_inc_cy~78_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~91_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'h4C0C; -defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~45_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|pc_inc_hold~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal19~1_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hA800; -defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~82_combout = (\z80_|execute_|ctl_inc_cy~81_combout ) # ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~81_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|pc_inc_hold~47_combout & (!\z80_|execute_|pc_inc_hold~38_combout & ((\z80_|execute_|ctl_inc_cy~82_combout ) # (!\z80_|execute_|ctl_inc_cy~38_combout )))) # (!\z80_|execute_|pc_inc_hold~47_combout -// & ((\z80_|execute_|ctl_inc_cy~82_combout ) # ((!\z80_|execute_|ctl_inc_cy~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~47_combout ), - .datab(\z80_|execute_|ctl_inc_cy~82_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'h4C5F; -defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~84_combout = (\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~79_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|execute_|ctl_inc_cy~83_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~42 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~42_combout = ((\z80_|execute_|pc_inc_hold~34_combout ) # (\z80_|execute_|pc_inc_hold~52_combout )) # (!\z80_|execute_|pc_inc_hold~30_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|pc_inc_hold~52_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~42 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|pc_inc_hold~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~90 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~90_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~8_combout ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~90 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~41 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~41_combout = (\z80_|execute_|pc_inc_hold~31_combout ) # ((\z80_|execute_|pc_inc_hold~32_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~31_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|execute_|pc_inc_hold~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~41 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|pc_inc_hold~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~66_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'h0004; -defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~66_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~20_combout & !\z80_|execute_|pc_inc_hold~31_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|ctl_inc_cy~66_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hAA02; -defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~67_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|pc_inc_hold~41_combout & \z80_|execute_|ctl_mRead~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|pc_inc_hold~41_combout ), - .datac(\z80_|execute_|ctl_inc_cy~67_combout ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hF2F0; -defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~64_combout = (!\z80_|execute_|pc_inc_hold~31_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|pc_inc_hold~34_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_sw_4u~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h0C08; -defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~65_combout = (\z80_|execute_|ctl_inc_cy~63_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((\z80_|execute_|ctl_inc_cy~64_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|execute_|ctl_inc_cy~64_combout ), - .datad(\z80_|execute_|ctl_inc_cy~63_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hFFC4; -defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|ctl_inc_cy~68_combout ) # ((\z80_|execute_|ctl_inc_cy~65_combout ) # ((!\z80_|execute_|pc_inc_hold~42_combout & !\z80_|execute_|ctl_inc_cy~90_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~42_combout ), - .datab(\z80_|execute_|ctl_inc_cy~90_combout ), - .datac(\z80_|execute_|ctl_inc_cy~68_combout ), - .datad(\z80_|execute_|ctl_inc_cy~65_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~49_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_inc_cy~92_combout ) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_inc_cy~92_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~50_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) # (!\z80_|execute_|ixy_d~9_combout & -// (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_mRead~11_combout )) # (!\z80_|execute_|ctl_inc_cy~94_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|execute_|ctl_inc_cy~94_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_inc_cy~51_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~51_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~36_combout = ((!\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_mWrite~4_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~36_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_sw_2u~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~54_combout = ((\z80_|execute_|ctl_inc_cy~49_combout ) # ((\z80_|execute_|ctl_inc_cy~52_combout ) # (!\z80_|execute_|ctl_inc_cy~37_combout ))) # (!\z80_|execute_|ctl_inc_cy~53_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), - .datab(\z80_|execute_|ctl_inc_cy~49_combout ), - .datac(\z80_|execute_|ctl_inc_cy~52_combout ), - .datad(\z80_|execute_|ctl_inc_cy~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~41_combout = (!\z80_|execute_|ctl_mRead~17_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'h0045; -defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~58_combout = (\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_inc_cy~41_combout )) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~41_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'hEEFF; -defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout ) # ((\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & -// ((\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~56_combout = (((!\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|fMRead~3_combout ) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~89 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~89_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~89 .lut_mask = 16'hA020; -defparam \z80_|execute_|ctl_inc_cy~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_inc_cy~56_combout ) # (\z80_|execute_|ctl_inc_cy~89_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ctl_inc_cy~55_combout ), - .datac(\z80_|execute_|ctl_inc_cy~56_combout ), - .datad(\z80_|execute_|ctl_inc_cy~89_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_inc_cy~57_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~58_combout ) # (!\z80_|execute_|fMRead~5_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_inc_cy~58_combout ), - .datac(\z80_|execute_|fMRead~5_combout ), - .datad(\z80_|execute_|ctl_inc_cy~57_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'hFF8A; -defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~60_combout = (\z80_|execute_|pc_inc_hold~38_combout & (\z80_|execute_|pc_inc_hold~35_combout & (\z80_|execute_|ctl_inc_cy~54_combout ))) # (!\z80_|execute_|pc_inc_hold~38_combout & (((\z80_|execute_|ctl_inc_cy~54_combout ) # -// (\z80_|execute_|ctl_inc_cy~59_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|pc_inc_hold~35_combout ), - .datac(\z80_|execute_|ctl_inc_cy~54_combout ), - .datad(\z80_|execute_|ctl_inc_cy~59_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'hD5D0; -defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|pc_inc_hold~50_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|pc_inc_hold~50_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~88_combout = (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ) # ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~47_combout ) # ((\z80_|execute_|ctl_inc_cy~88_combout & ((\z80_|execute_|pc_inc_hold~39_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~39_combout ), - .datab(\z80_|execute_|ctl_inc_cy~47_combout ), - .datac(\z80_|execute_|ctl_inc_cy~88_combout ), - .datad(\z80_|execute_|pc_inc_hold~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'hECFC; -defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~40 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~40_combout = (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~34_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~40 .lut_mask = 16'h0C0C; -defparam \z80_|execute_|pc_inc_hold~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~61_combout = (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h3200; -defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~62_combout = (\z80_|execute_|ctl_inc_cy~61_combout ) # ((!\z80_|execute_|ctl_inc_cy~42_combout & ((\z80_|execute_|pc_inc_hold~40_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|pc_inc_hold~40_combout ), - .datac(\z80_|execute_|ctl_inc_cy~61_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hF0FD; -defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~69_combout ) # ((\z80_|execute_|ctl_inc_cy~60_combout ) # ((\z80_|execute_|ctl_inc_cy~48_combout ) # (\z80_|execute_|ctl_inc_cy~62_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), - .datab(\z80_|execute_|ctl_inc_cy~60_combout ), - .datac(\z80_|execute_|ctl_inc_cy~48_combout ), - .datad(\z80_|execute_|ctl_inc_cy~62_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~85_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~84_combout ) # (\z80_|execute_|ctl_inc_cy~70_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), - .datab(\z80_|execute_|ctl_inc_cy~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~84_combout ), - .datad(\z80_|execute_|ctl_inc_cy~70_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (\z80_|execute_|ctl_inc_cy~85_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_cy~85_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hAF2F; -defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( -// Equation(s): -// \z80_|address_latch_|abusz [0] = (\z80_|reg_file_|db_lo_as[0]~3_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [0]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|Q[0]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[0]~feeder_combout = \z80_|address_latch_|abusz [0] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [0]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N23 -dffeas \z80_|address_latch_|Q[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[0]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X31_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[1]~32_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .datad(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_cy~85_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h6A6A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hAF2F; -defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( -// Equation(s): -// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [1]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h3300; -defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N19 -dffeas \z80_|address_latch_|Q[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [1]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout = \z80_|address_latch_|Q [1] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|address_latch_|Q [1]), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .lut_mask = 16'h0F87; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & (\z80_|execute_|ctl_inc_cy~85_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hF575; -defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( -// Equation(s): -// \z80_|address_latch_|abusz [2] = (\z80_|reg_file_|db_lo_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [2]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h00AA; -defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N14 -cycloneive_lcell_comb \z80_|address_latch_|Q[2]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[2]~feeder_combout = \z80_|address_latch_|abusz [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [2]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N15 -dffeas \z80_|address_latch_|Q[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[2]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|address_latch_|Q [2] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|address_latch_|Q [2]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h40BF; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~86_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), - .datab(\z80_|execute_|ctl_inc_cy~79_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|execute_|ctl_inc_cy~83_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~86_combout ) # -// (\z80_|execute_|ctl_inc_cy~70_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datab(\z80_|execute_|ctl_inc_cy~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~86_combout ), - .datad(\z80_|execute_|ctl_inc_cy~70_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hAAA8; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~11_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout )) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout = (\z80_|execute_|ctl_inc_cy~85_combout & ((\z80_|address_latch_|Q [1] & (!\z80_|execute_|ctl_inc_dec~11_combout & \z80_|address_latch_|Q [0])) # (!\z80_|address_latch_|Q -// [1] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [0])))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_cy~85_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .lut_mask = 16'h2400; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout -// ))) - - .dataa(gnd), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h3FC0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N11 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N5 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'h3F3B; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~29_combout ) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|setM1~29_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_al_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'hB3F3; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & !\z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ) # ((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hF7F5; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = ((\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|execute_|setM1~46_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datad(\z80_|execute_|setM1~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'h5DDD; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ) # (!\z80_|execute_|ctl_reg_gp_we~2_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~40 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[3]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~41 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[3]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hB3FF; -defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~12_combout = (\z80_|execute_|ctl_reg_in_hi~11_combout ) # (((!\z80_|execute_|ctl_reg_in_hi~4_combout ) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~44_combout = (\z80_|alu_|db[3]~11_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[3]~11_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~44 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~48_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h4444; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h4000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|execute_|ctl_reg_gp_we~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~43_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h5450; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # (\z80_|execute_|ctl_reg_sys_we_lo~3_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hFB33; -defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~combout = ((\z80_|reg_control_|reg_sys_we_hi~0_combout ) # (\z80_|execute_|ctl_reg_sys_we~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF3; -defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~45 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[3]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0002; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h0400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0008; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~42_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~42 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[3]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~46_combout = (\z80_|reg_file_|gdfx_temp1[3]~44_combout & (\z80_|reg_file_|gdfx_temp1[3]~43_combout & (\z80_|reg_file_|gdfx_temp1[3]~45_combout & \z80_|reg_file_|gdfx_temp1[3]~42_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~46 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~47_combout = (\z80_|reg_file_|gdfx_temp1[3]~40_combout & (\z80_|reg_file_|gdfx_temp1[3]~41_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout & \z80_|reg_file_|gdfx_temp1[3]~46_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~47 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFF8; -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~16_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|reg_control_|reg_sel_pc~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N11 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|alu_|db[1]~13_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[1]~13_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[1]~13_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~21_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~12_combout & (\z80_|reg_file_|gdfx_temp1[1]~10_combout & \z80_|reg_file_|gdfx_temp1[1]~11_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~8_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout & (\z80_|reg_file_|gdfx_temp1[1]~14_combout & \z80_|reg_file_|gdfx_temp1[1]~9_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .datac(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (!\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_control_|reg_sys_we_lo~combout ) # ((!\z80_|execute_|ctl_reg_sel_ir~1_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'h8AAA; -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_file_|gdfx_temp1[1]~21_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[1]~21_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|reg_control_|reg_sel_pc~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # (\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|address_latch_|Q [7] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [8]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'h96CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|alu_|db[0]~19_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[0]~19_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[0]~19_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~24_combout & (\z80_|reg_file_|gdfx_temp1[0]~26_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & \z80_|reg_file_|gdfx_temp1[0]~27_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|gdfx_temp1[0]~28_combout & \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .datad(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( -// Equation(s): -// \z80_|address_latch_|abusz [8] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[0]~6_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [8]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N9 -dffeas \z80_|address_latch_|Q[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [8]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N18 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|address_latch_|Q [7] & (\z80_|address_latch_|Q [8] & !\z80_|execute_|ctl_inc_dec~11_combout -// )) # (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [8] & \z80_|execute_|ctl_inc_dec~11_combout )))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [8]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h1800; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N24 -cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( -// Equation(s): -// \z80_|address_latch_|abusz [9] = (\z80_|reg_file_|db_hi_as[1]~3_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [9]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|Q[9]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[9]~feeder_combout = \z80_|address_latch_|abusz [9] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [9]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[9]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[9]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[9]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N5 -dffeas \z80_|address_latch_|Q[9] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[9]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ -// (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [9]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~32 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~35_combout = (\z80_|alu_|db[2]~15_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[2]~15_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[2]~15_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~35 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~34 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~33_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~33 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N1 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~36 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~37_combout = (\z80_|reg_file_|gdfx_temp1[2]~35_combout & (\z80_|reg_file_|gdfx_temp1[2]~34_combout & (\z80_|reg_file_|gdfx_temp1[2]~33_combout & \z80_|reg_file_|gdfx_temp1[2]~36_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~37 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~31 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~38_combout = (\z80_|reg_file_|gdfx_temp1[2]~32_combout & (\z80_|reg_file_|gdfx_temp1[2]~37_combout & (\z80_|reg_file_|gdfx_temp1[2]~31_combout & \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~38 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~39_combout = ((\z80_|reg_file_|gdfx_temp1[2]~38_combout & ((\z80_|reg_file_|db_hi_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~39 .lut_mask = 16'h8FAF; -defparam \z80_|reg_file_|gdfx_temp1[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp1[2]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[2]~39_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~7 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~8_combout = (\z80_|reg_file_|db_hi_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~7_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~8 .lut_mask = 16'hCC44; -defparam \z80_|reg_file_|db_hi_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~9 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~9_combout = ((\z80_|reg_file_|db_hi_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[2]~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~9 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N0 -cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( -// Equation(s): -// \z80_|address_latch_|abusz [10] = (\z80_|reg_file_|db_hi_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [10]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|Q[10]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[10]~feeder_combout = \z80_|address_latch_|abusz [10] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [10]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[10]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[10]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N27 -dffeas \z80_|address_latch_|Q[10] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[10]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [10] & (\z80_|address_latch_|Q [9] & -// !\z80_|execute_|ctl_inc_dec~11_combout )) # (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [9] & \z80_|execute_|ctl_inc_dec~11_combout )))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [9]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h1800; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( -// Equation(s): -// \z80_|address_latch_|abusz [11] = (\z80_|reg_file_|db_hi_as[3]~12_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h00CC; -defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N15 -dffeas \z80_|address_latch_|Q[11] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [11]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout $ (\z80_|address_latch_|Q [11]) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(gnd), - .datac(\z80_|address_latch_|Q [11]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h5A5A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp1[3]~48_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[3]~48_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~11 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~11_combout = (\z80_|reg_file_|db_hi_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[3]~10_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~11 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|db_hi_as[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~12_combout = ((\z80_|reg_file_|db_hi_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[3]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~12 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~48_combout = ((\z80_|reg_file_|gdfx_temp1[3]~47_combout & ((\z80_|reg_file_|db_hi_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~48 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'h888A; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hC0E0; -defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[3]~8_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N7 -dffeas \z80_|alu_|op1_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~3 ( -// Equation(s): -// \z80_|alu_|alu_op1[3]~3_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])) - - .dataa(gnd), - .datab(\z80_|alu_|op1_high [3]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[3]~3 .lut_mask = 16'hF0CC; -defparam \z80_|alu_|alu_op1[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [2])))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|alu_|alu_op2[2]~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0305; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = ((\z80_|pla_decode_|Equal8~0_combout & (\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mWrite~2_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|pla_decode_|Equal8~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'hAAFB; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~0_combout = (\z80_|pla_decode_|Equal1~5_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~5_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) # (((\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = ((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) # -// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .lut_mask = 16'h5050; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_zero~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFFFA; -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N1 -dffeas \z80_|alu_|op2_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[1]~20_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N23 -dffeas \z80_|alu_|op1_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))))) - - .dataa(\z80_|alu_|op1_low [1]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'h8C80; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|alu_|db_low[1]~17_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .datac(\z80_|alu_|db_low[1]~17_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N21 -dffeas \z80_|alu_|op2_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~20_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal68~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal68~2_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .lut_mask = 16'h0D0F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|execute_|ctl_state_alu~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # ((\z80_|execute_|ctl_state_alu~11_combout ) # (!\z80_|execute_|ctl_state_alu~8_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~9_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datac(\z80_|execute_|ctl_state_alu~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~18_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~12_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h7577; -defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) +// \z80_|pla_decode_|Equal0~0_combout = (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~4_combout ) .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal61~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal61~2_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M4_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'hFC00; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~20_combout & (\z80_|execute_|ctl_alu_core_hf~18_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~21_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~17_combout & (((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~4_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout -// ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & (\z80_|execute_|ctl_alu_core_S~4_combout & \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_ir_we~11_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .lut_mask = 16'hC4CC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~20_combout = ((\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout ))) # (!\z80_|execute_|ctl_state_alu~12_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal71~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal71~2_combout = (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~12_combout & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal71~2 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_alu_core_hf~20_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & !\z80_|pla_decode_|Equal71~2_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|pla_decode_|Equal71~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'h0080; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~31_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~9_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'h1333; -defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (\z80_|pla_decode_|Equal21~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal3~0_combout & -// ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'hFCA8; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout = (\z80_|pla_decode_|Equal13~1_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal13~1_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N16 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & \z80_|pla_decode_|Equal63~0_combout -// ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'hFFEC; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (\z80_|execute_|ctl_alu_op_low~31_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & !\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'h0080; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal72~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal72~2_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal72~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal72~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal72~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal73~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|pla_decode_|Equal61~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal61~2_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (!\z80_|pla_decode_|Equal72~2_combout & (!\z80_|pla_decode_|Equal73~2_combout & \z80_|execute_|ctl_flags_nf_we~0_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datab(\z80_|pla_decode_|Equal72~2_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~3_combout = ((\z80_|execute_|ctl_flags_nf_we~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout )) # (!\z80_|execute_|ctl_flags_nf_we~1_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFAFF; -defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|pla_decode_|Equal48~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|execute_|ctl_flags_sz_we~5_combout & \z80_|execute_|ctl_alu_core_R~0_combout )))) # -// (!\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_flags_sz_we~5_combout & ((\z80_|execute_|ctl_alu_core_R~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hECA0; -defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~4_combout = (((\z80_|execute_|ctl_flags_nf_we~3_combout ) # (\z80_|execute_|ctl_flags_sz_we~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~12_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~15 ( -// Equation(s): -// \z80_|execute_|setM1~15_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_state_alu~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~15 .lut_mask = 16'h5000; -defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~16 ( -// Equation(s): -// \z80_|execute_|setM1~16_combout = (\z80_|execute_|setM1~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~31_combout ))) - - .dataa(\z80_|execute_|setM1~15_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0200; -defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|setM1~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|setM1~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & \z80_|execute_|ctl_alu_oe~5_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (\z80_|execute_|ctl_flags_xy_we~7_combout & \z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) - - .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~7_combout ), .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .combout(\z80_|pla_decode_|Equal0~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal0~0 .lut_mask = 16'h5500; +defparam \z80_|pla_decode_|Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 ( +// Location: LCCOMB_X40_Y13_N8 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( // Equation(s): -// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal11~1_combout & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) +// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal11~1_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), + .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88C0; +defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), - .cout()); +// Location: FF_X40_Y13_N9 +dffeas \z80_|sequencer_|DFFE_M3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M3_ff~q ), + .prn(vcc)); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFBAA; -defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~7_combout = (\z80_|execute_|ctl_alu_core_R~1_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_flags_alu~18_combout )) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~7 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_flags_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~8 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~8_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal56~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~8 .lut_mask = 16'h7F00; -defparam \z80_|reg_control_|reg_sys_we_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~8_combout = ((\z80_|execute_|ctl_flags_alu~7_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~8_combout ) # (!\z80_|execute_|ctl_flags_alu~16_combout ))) # (!\z80_|execute_|ctl_flags_alu~6_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), - .datab(\z80_|execute_|ctl_flags_alu~7_combout ), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~8 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_alu_op_low~10_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal20~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~10_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'h0070; -defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~13_combout = (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_flags_xy_we~16_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_alu~12_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datac(\z80_|execute_|ctl_sw_2d~4_combout ), - .datad(\z80_|execute_|ctl_flags_alu~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_alu_op_low~15_combout & (\z80_|execute_|ctl_sw_4u~1_combout & \z80_|execute_|ctl_flags_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|execute_|ctl_flags_alu~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~15_combout = ((\z80_|execute_|ctl_flags_alu~8_combout ) # ((!\z80_|execute_|ctl_flags_alu~11_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_alu~8_combout ), - .datac(\z80_|execute_|ctl_flags_alu~14_combout ), - .datad(\z80_|execute_|ctl_flags_alu~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N12 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFCEC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~19_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ) # ((\z80_|alu_control_|db[1]~26_combout & \z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), - .datac(\z80_|alu_control_|db[1]~26_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEEE; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X37_Y9_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( +cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( // Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|execute_|ctl_flags_alu~15_combout & \z80_|alu_|db_high[3]~8_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) +// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFFB3; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'h3070; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .lut_mask = 16'h0800; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) - - .dataa(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .lut_mask = 16'hD850; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y9_N27 -dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) # (!\z80_|sequencer_|DFFE_M2_ff~q & -// (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'h7707; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = ((\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'hB3BB; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~11_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~18_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~15_combout & \z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .lut_mask = 16'hFDF5; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal13~2_combout & \z80_|sequencer_|DFFE_M3_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~1 ( -// Equation(s): -// \z80_|alu_|alu_op2[1]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [1])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [1]))))) - - .dataa(\z80_|alu_|op2_high [1]), - .datab(\z80_|alu_|op2_low [1]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[1]~1 .lut_mask = 16'h5A3C; -defparam \z80_|alu_|alu_op2[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high -// [1]))))) - - .dataa(\z80_|alu_|alu_op2[1]~1_combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h1015; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~9_combout = (((\z80_|pla_decode_|Equal71~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_core_S~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), - .datad(\z80_|pla_decode_|Equal71~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout = (\z80_|alu_|db_high[0]~26_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|alu_|db_low[0]~23_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # -// (!\z80_|alu_|db_high[0]~26_combout & (\z80_|alu_|db_low[0]~23_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout ))) - - .dataa(\z80_|alu_|db_high[0]~26_combout ), - .datab(\z80_|alu_|db_low[0]~23_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .lut_mask = 16'hEAC0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) - - .dataa(gnd), + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N7 -dffeas \z80_|alu_|op2_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( -// Equation(s): -// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|alu_|op2_high [0]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h3C5A; -defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~12 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & ((\z80_|ir_|opcode [3]) # ((!\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal62~2_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .lut_mask = 16'hB0F0; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & \z80_|execute_|ctl_alu_core_S~7_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~9_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # -// (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h37FF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_alu_core_hf~20_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .datac(gnd), .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .combout(\z80_|execute_|ixy_d~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( +// Location: LCCOMB_X36_Y6_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 ( // Equation(s): -// \z80_|execute_|ctl_alu_core_hf~22_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~21_combout )) # (!\z80_|execute_|ctl_alu_core_hf~18_combout ) +// \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal0~0_combout & (\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [1]))) - .dataa(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal0~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'hD5FF; -defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( +// Location: LCCOMB_X36_Y6_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( // Equation(s): -// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hA0E0; -defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (((\z80_|execute_|ctl_alu_op_low~22_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~29_combout = (\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~23_combout = (\z80_|execute_|ctl_alu_core_hf~22_combout & (((\z80_|execute_|ctl_alu_core_hf~19_combout & !\z80_|execute_|ctl_alu_op_low~29_combout )) # (!\z80_|execute_|ctl_alu_op_low~28_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~22_combout & (\z80_|execute_|ctl_alu_core_hf~19_combout & (!\z80_|execute_|ctl_alu_op_low~29_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h0CAE; -defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|pla_decode_|Equal39~0_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal40~1_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hFF30; -defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~25_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'hEFEE; -defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'hA0A8; -defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~26_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hDFCC; -defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~28_combout = (\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_alu_op_low~20_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h22F2; -defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (((\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datab(\z80_|execute_|ctl_state_alu~13_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout & !\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~7_combout & -// ((!\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hC0CA; -defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~43_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|ctl_mRead~6_combout & (\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # -// ((\z80_|execute_|ctl_mRead~6_combout & \z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~43 .lut_mask = 16'hD5C0; -defparam \z80_|execute_|ctl_alu_core_hf~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~33_combout = (!\z80_|execute_|ctl_alu_core_hf~43_combout & ((\z80_|execute_|ctl_alu_core_hf~32_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~32_combout & (\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'h00E8; -defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~42 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~42_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~42 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_alu_core_hf~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~42_combout & ((\z80_|execute_|ctl_alu_core_hf~34_combout ) # (\z80_|execute_|ctl_alu_core_hf~33_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~41_combout = (!\z80_|execute_|ctl_state_alu~4_combout & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal10~0_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~41 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_alu_core_hf~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & -// (\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~10_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal11~1_combout & \z80_|execute_|ctl_mWrite~2_combout ))) +// \z80_|pla_decode_|Equal33~0_combout = (\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0])) .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal11~1_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~31_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_mWrite~10_combout & ((\z80_|execute_|ctl_alu_core_hf~41_combout ) # (\z80_|execute_|ctl_alu_core_hf~30_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~41_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'h0054; -defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~44_combout = (\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~44 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_core_hf~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~29_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & ((\z80_|execute_|ctl_alu_core_hf~44_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~44_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'h0E0A; -defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # ((!\z80_|execute_|ctl_alu_op_low~30_combout & \z80_|execute_|ctl_alu_core_hf~35_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'hFFF4; -defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~39_combout = (\z80_|execute_|ctl_alu_core_hf~28_combout ) # ((\z80_|execute_|ctl_alu_core_hf~36_combout ) # ((\z80_|execute_|ctl_alu_core_hf~38_combout & !\z80_|execute_|ctl_alu_op_low~24_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~39 .lut_mask = 16'hFCFE; -defparam \z80_|execute_|ctl_alu_core_hf~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~40_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((\z80_|execute_|ctl_alu_core_hf~39_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~40 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_alu_core_hf~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datad(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~combout = (\z80_|execute_|ctl_alu_core_R~2_combout ) # (((\z80_|pla_decode_|Equal73~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_R~2_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .lut_mask = 16'hC0D0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_high[3]~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), - .datad(\z80_|alu_|db_high[3]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .lut_mask = 16'h5450; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N9 -dffeas \z80_|alu_|op2_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [3]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ) # ((\z80_|alu_|db_low[3]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), - .datac(\z80_|alu_|db_low[3]~25_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N19 -dffeas \z80_|alu_|op2_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~2 ( -// Equation(s): -// \z80_|alu_|alu_op2[3]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [3])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [3]))))) - - .dataa(\z80_|alu_|op2_high [3]), - .datab(\z80_|alu_|op2_low [3]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[3]~2 .lut_mask = 16'h5A3C; -defparam \z80_|alu_|alu_op2[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[3]~3_combout & \z80_|alu_|alu_op2[3]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|alu_|alu_op1[3]~3_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datac(\z80_|alu_|alu_op2[3]~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [3])))) - - .dataa(\z80_|alu_|alu_op2[3]~2_combout ), - .datab(\z80_|alu_|op1_high [3]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0511; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_R~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hAFAE; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # -// (!\z80_|execute_|ctl_flags_bus~combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'h8F88; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((\z80_|pla_decode_|Equal10~0_combout & -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hFC88; -defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~14_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~14_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) - - .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datad(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hCCE4; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N7 -dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|pla_decode_|Equal52~1_combout ) # (\z80_|execute_|ctl_state_alu~14_combout )) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~12_combout = ((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_alu_op_low~12_combout ))) # (!\z80_|execute_|ctl_flags_hf_cpl~10_combout ) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .datab(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~13_combout = (\z80_|execute_|ctl_flags_hf_cpl~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|alu_flags_|DFFE_inst_latch_nf~q ))) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~13 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_hf_cpl~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N8 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( -// Equation(s): -// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~13_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h559A; -defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N30 -cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( -// Equation(s): -// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~40_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~40_combout & (\z80_|alu_flags_|flags_cf~combout )) - - .dataa(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .datab(\z80_|alu_flags_|flags_cf~combout ), + .datab(\z80_|ir_|opcode [1]), .datac(gnd), - .datad(\z80_|alu_flags_|flags_hf~combout ), + .datad(\z80_|ir_|opcode [0]), .cin(gnd), - .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .combout(\z80_|pla_decode_|Equal33~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hEE44; -defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_control_|alu_core_cf_in~0_combout & \z80_|alu_|alu_op1[0]~1_combout )))) -// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|alu_|alu_op1[0]~1_combout )))) - - .dataa(\z80_|alu_|alu_op2[0]~3_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op1[0]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( -// Equation(s): -// \z80_|alu_|db_high[0]~23_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~25_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[3]~11_combout ), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hE4E4; -defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( -// Equation(s): -// \z80_|address_latch_|abusz [12] = (\z80_|reg_file_|db_hi_as[4]~18_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [12]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|Q[12]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[12]~feeder_combout = \z80_|address_latch_|abusz [12] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [12]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[12]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[12]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[12]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N15 -dffeas \z80_|address_latch_|Q[12] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[12]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ -// (\z80_|address_latch_|Q [11]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hD278; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~16 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~16_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~16 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|db_hi_as[4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~17 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~17_combout = (\z80_|reg_file_|db_hi_as[4]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .datad(\z80_|reg_file_|db_hi_as[4]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~17 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|db_hi_as[4]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~18 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~18_combout = ((\z80_|reg_file_|db_hi_as[4]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[4]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~18 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[4]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N11 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~62_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [4] & ((\z80_|alu_|db[4]~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~12_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[4]~17_combout )) # (!\z80_|execute_|ctl_reg_in_hi~12_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .datad(\z80_|alu_|db[4]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~62 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y11_N29 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~63_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~63 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[4]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N23 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~61_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~61 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp1[4]~66_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~60_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~60 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~64_combout = (\z80_|reg_file_|gdfx_temp1[4]~62_combout & (\z80_|reg_file_|gdfx_temp1[4]~63_combout & (\z80_|reg_file_|gdfx_temp1[4]~61_combout & \z80_|reg_file_|gdfx_temp1[4]~60_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~64 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~59 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~58 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~65_combout = (\z80_|reg_file_|gdfx_temp1[4]~64_combout & (\z80_|reg_file_|gdfx_temp1[4]~59_combout & (\z80_|reg_file_|gdfx_temp1[4]~58_combout & \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~65 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~66_combout = ((\z80_|reg_file_|gdfx_temp1[4]~65_combout & ((\z80_|reg_file_|db_hi_as[4]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~66 .lut_mask = 16'hD5F5; -defparam \z80_|reg_file_|gdfx_temp1[4]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db[4]~16 ( -// Equation(s): -// \z80_|alu_|db[4]~16_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[4]~32_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[4]~32_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~16 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|db[7]~26 ( -// Equation(s): -// \z80_|alu_|db[7]~26_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout ) # ((\z80_|execute_|ctl_alu_oe~13_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_alu_oe~13_combout ), - .datac(\z80_|execute_|ctl_alu_oe~9_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~26 .lut_mask = 16'hFFEF; -defparam \z80_|alu_|db[7]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db[4]~17 ( -// Equation(s): -// \z80_|alu_|db[4]~17_combout = ((\z80_|alu_|db[4]~16_combout & ((\z80_|alu_|db_high[0]~26_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[4]~16_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db_high[0]~26_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~17 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[4]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & \z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h00C8; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~6_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( -// Equation(s): -// \z80_|alu_|db_high[0]~24_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[0]~23_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[4]~17_combout ))) - - .dataa(\z80_|alu_|db_high[0]~23_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[4]~17_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hAAF0; -defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( -// Equation(s): -// \z80_|alu_|db_high[0]~21_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'h5575; -defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|alu_|db_high[0]~26_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[0]~26_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N21 -dffeas \z80_|alu_|op1_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( -// Equation(s): -// \z80_|alu_|db_high[0]~22_combout = (\z80_|alu_|op1_high [0] & (((\z80_|alu_|op2_high [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [0] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [0]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [0]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( -// Equation(s): -// \z80_|alu_|db_high[0]~25_combout = (\z80_|alu_|db_high[0]~21_combout & (\z80_|alu_|db_high[0]~22_combout & ((\z80_|alu_|db_high[0]~24_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[0]~24_combout ), - .datab(\z80_|alu_|db_high[0]~21_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[0]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'h8C00; -defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~26 ( -// Equation(s): -// \z80_|alu_|db_high[0]~26_combout = ((\z80_|alu_|db_high[0]~25_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|db_high[0]~25_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~26 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|db_low[0]~23_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) # -// (!\z80_|alu_|db_low[0]~23_combout & (((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) - - .dataa(\z80_|alu_|db_low[0]~23_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datad(\z80_|alu_|db_high[0]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFEFE; -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N31 -dffeas \z80_|alu_|op1_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( -// Equation(s): -// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [0]))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_low [0]), - .datac(\z80_|alu_|op1_high [0]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|alu_|alu_op1[0]~1_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[0]~23_combout )))) # -// (!\z80_|alu_|alu_op1[0]~1_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & ((\z80_|alu_|db_low[0]~23_combout )))) - - .dataa(\z80_|alu_|alu_op1[0]~1_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_low[0]~23_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h5050; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N15 -dffeas \z80_|alu_|op2_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(gnd), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hF0AA; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op1[0]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hF660; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~9_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & -// \z80_|execute_|ctl_alu_core_S~8_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hF1F0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op1[1]~0 ( -// Equation(s): -// \z80_|alu_|alu_op1[1]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(gnd), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[1]~0 .lut_mask = 16'hDD88; -defparam \z80_|alu_|alu_op1[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[1]~0_combout & \z80_|alu_|alu_op2[1]~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datac(\z80_|alu_|alu_op1[1]~0_combout ), - .datad(\z80_|alu_|alu_op2[1]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hFBBB; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # -// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h0F01; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op1[2]~2 ( -// Equation(s): -// \z80_|alu_|alu_op1[2]~2_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(gnd), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[2]~2 .lut_mask = 16'hEE22; -defparam \z80_|alu_|alu_op1[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op2[2]~0_combout & \z80_|alu_|alu_op1[2]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|alu_|alu_op2[2]~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datac(\z80_|alu_|alu_op1[2]~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hFF0B; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & \z80_|execute_|ctl_alu_core_S~8_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .lut_mask = 16'h5F5D; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op1[3]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & -// \z80_|alu_|alu_op2[3]~2_combout )))) # (!\z80_|alu_|alu_op1[3]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[3]~2_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) - - .dataa(\z80_|alu_|alu_op1[3]~3_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|alu_op2[3]~2_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'hFB20; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp1[7]~75_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~69_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~69 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[7]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~70 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~72_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~72 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[7]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~71_combout = (\z80_|alu_|db[7]~21_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[7]~21_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~71 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[7]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~73_combout = (\z80_|reg_file_|gdfx_temp1[7]~69_combout & (\z80_|reg_file_|gdfx_temp1[7]~70_combout & (\z80_|reg_file_|gdfx_temp1[7]~72_combout & \z80_|reg_file_|gdfx_temp1[7]~71_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~73 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~67 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[7]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~68 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~74_combout = (\z80_|reg_file_|gdfx_temp1[7]~73_combout & (\z80_|reg_file_|gdfx_temp1[7]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout & \z80_|reg_file_|gdfx_temp1[7]~68_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~74 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~19 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~75_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~75_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~19 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[7]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~20 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~20_combout = (\z80_|reg_file_|db_hi_as[7]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[7]~19_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~20 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|db_hi_as[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [12] & -// !\z80_|address_latch_|Q [11])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [12] & \z80_|address_latch_|Q [11])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~54 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[5]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~53_combout = (\z80_|alu_|db[5]~25_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[5]~25_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[5]~25_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~53 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[5]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~57_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~51_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~51 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[5]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N11 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~52_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~52 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[5]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~55_combout = (\z80_|reg_file_|gdfx_temp1[5]~54_combout & (\z80_|reg_file_|gdfx_temp1[5]~53_combout & (\z80_|reg_file_|gdfx_temp1[5]~51_combout & \z80_|reg_file_|gdfx_temp1[5]~52_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~55 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~49 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~50 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[5]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~56_combout = (\z80_|reg_file_|gdfx_temp1[5]~55_combout & (\z80_|reg_file_|gdfx_temp1[5]~49_combout & (\z80_|reg_file_|gdfx_temp1[5]~50_combout & \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~56 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~57_combout = ((\z80_|reg_file_|gdfx_temp1[5]~56_combout & ((\z80_|reg_file_|db_hi_as[5]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), - .datac(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~57 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~13 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~13_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[5]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~14 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~14_combout = (\z80_|reg_file_|db_hi_as[5]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|db_hi_as[5]~13_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~14 .lut_mask = 16'hC4C4; -defparam \z80_|reg_file_|db_hi_as[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~15 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~15_combout = ((\z80_|reg_file_|db_hi_as[5]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[5]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~15 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[5]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( -// Equation(s): -// \z80_|address_latch_|abusz [13] = (\z80_|reg_file_|db_hi_as[5]~15_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [13]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|Q[13]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[13]~feeder_combout = \z80_|address_latch_|abusz [13] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [13]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[13]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[13]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N23 -dffeas \z80_|address_latch_|Q[13] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[13]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|execute_|ctl_inc_dec~11_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( -// Equation(s): -// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~21_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N27 -dffeas \z80_|address_latch_|Q[15] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [15]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [13]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [14]), - .datad(\z80_|execute_|ctl_inc_dec~11_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'hB478; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~76 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~80_combout = (\z80_|alu_|db[6]~23_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[6]~23_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[6]~23_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~80 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N17 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~79_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~79 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~78 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~81 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~82_combout = (\z80_|reg_file_|gdfx_temp1[6]~80_combout & (\z80_|reg_file_|gdfx_temp1[6]~79_combout & (\z80_|reg_file_|gdfx_temp1[6]~78_combout & \z80_|reg_file_|gdfx_temp1[6]~81_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~82 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~77 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~83_combout = (\z80_|reg_file_|gdfx_temp1[6]~76_combout & (\z80_|reg_file_|gdfx_temp1[6]~82_combout & (\z80_|reg_file_|gdfx_temp1[6]~77_combout & \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~83 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~84_combout = ((\z80_|reg_file_|gdfx_temp1[6]~83_combout & ((\z80_|reg_file_|db_hi_as[6]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), - .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~84 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~22 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~22_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~22 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~23 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~23_combout = (\z80_|reg_file_|db_hi_as[6]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .datab(\z80_|reg_file_|db_hi_as[6]~22_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~23 .lut_mask = 16'h88CC; -defparam \z80_|reg_file_|db_hi_as[6]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~24 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~24_combout = ((\z80_|reg_file_|db_hi_as[6]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_file_|db_hi_as[6]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~24 .lut_mask = 16'hBF33; -defparam \z80_|reg_file_|db_hi_as[6]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( -// Equation(s): -// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~24_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|Q[14]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[14]~feeder_combout = \z80_|address_latch_|abusz [14] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [14]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[14]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[14]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N5 -dffeas \z80_|address_latch_|Q[14] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[14]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|address_latch_|Q [14]), - .datac(\z80_|execute_|ctl_inc_dec~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h3363; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~21 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~21_combout = ((\z80_|reg_file_|db_hi_as[7]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[7]~20_combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~21 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_hi_as[7]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~75_combout = ((\z80_|reg_file_|gdfx_temp1[7]~74_combout & ((\z80_|reg_file_|db_hi_as[7]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), - .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~75 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[7]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( -// Equation(s): -// \z80_|alu_|db[7]~20_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[7]~75_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .datad(\z80_|alu_control_|db[7]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db[7]~21 ( -// Equation(s): -// \z80_|alu_|db[7]~21_combout = ((\z80_|alu_|db[7]~20_combout & ((\z80_|alu_|db_high[3]~8_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[7]~20_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~21 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[7]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N22 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (\z80_|alu_|db[7]~21_combout & ((\z80_|ir_|opcode [3])))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & -// (\z80_|alu_|db[7]~21_combout )))) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hB822; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (\z80_|alu_control_|db[0]~12_combout & (\z80_|execute_|ctl_flags_bus~combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & -// ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[0]~12_combout & \z80_|execute_|ctl_flags_bus~combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datab(\z80_|alu_control_|db[0]~12_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'hD5C0; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hF4FC; -defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~6_combout = ((\z80_|execute_|ctl_flags_cf_we~5_combout ) # ((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~2 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_flags_cf2_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~4_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal10~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'hE000; -defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~3_combout = (\z80_|execute_|ctl_flags_cf2_we~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|ixy_d~15_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_flags_cf2_we~2_combout ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_flags_cf2_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~3_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0B8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y9_N3 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N0 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h0A88; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N4 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout & !\z80_|ir_|opcode [4])) - - .dataa(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .datac(gnd), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hCCEE; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( -// Equation(s): -// \z80_|alu_|db_high[3]~5_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[6]~23_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .datac(\z80_|alu_|db[6]~23_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( -// Equation(s): -// \z80_|alu_|db_high[3]~6_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[3]~5_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[7]~21_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(\z80_|alu_|db_high[3]~5_combout ), - .datac(\z80_|alu_|db[7]~21_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( -// Equation(s): -// \z80_|alu_|db_high[3]~4_combout = (\z80_|alu_|op2_high [3] & (((\z80_|alu_|op1_high [3])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_high [3] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [3]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_high [3]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_high [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~27 ( -// Equation(s): -// \z80_|alu_|db_high[3]~27_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~27 .lut_mask = 16'hD555; -defparam \z80_|alu_|db_high[3]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( -// Equation(s): -// \z80_|alu_|db_high[3]~7_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~27_combout & ((\z80_|alu_|db_high[3]~6_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[3]~6_combout ), - .datab(\z80_|alu_|db_high[3]~4_combout ), - .datac(\z80_|alu_|db_high[3]~27_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'h80C0; -defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~8 ( -// Equation(s): -// \z80_|alu_|db_high[3]~8_combout = ((\z80_|alu_|db_high[3]~7_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|db_high[3]~7_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~8 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[3]~8_combout )))) - - .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N15 -dffeas \z80_|alu_|op1_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~9 ( -// Equation(s): -// \z80_|alu_|db_low[3]~9_combout = (\z80_|alu_|op1_low [3] & (((\z80_|alu_|op2_low [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_low [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [3]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_low [3]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_low [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~9 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_low[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[4]~19_combout & \z80_|bus_control_|db[3]~21_combout ) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hCC00; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~10 ( -// Equation(s): -// \z80_|alu_|db_low[3]~10_combout = (\z80_|alu_|db_low[3]~9_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|bus_control_|db[5]~15_combout ), - .datab(\z80_|alu_|db_low[3]~9_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~10 .lut_mask = 16'h4C0C; -defparam \z80_|alu_|db_low[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N15 -dffeas \z80_|alu_|result_lo[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~7 ( -// Equation(s): -// \z80_|alu_|db_low[3]~7_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~17_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) - - .dataa(\z80_|alu_|db[4]~17_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[2]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~7 .lut_mask = 16'hAFA0; -defparam \z80_|alu_|db_low[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~8 ( -// Equation(s): -// \z80_|alu_|db_low[3]~8_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~7_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~11_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_low[3]~7_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~8 .lut_mask = 16'hF3BB; -defparam \z80_|alu_|db_low[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~11 ( -// Equation(s): -// \z80_|alu_|db_low[3]~11_combout = (\z80_|alu_|db_low[3]~10_combout & (\z80_|alu_|db_low[3]~8_combout & ((\z80_|alu_|result_lo [3]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[3]~10_combout ), - .datab(\z80_|alu_|result_lo [3]), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_low[3]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~11 .lut_mask = 16'hA800; -defparam \z80_|alu_|db_low[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~25 ( -// Equation(s): -// \z80_|alu_|db_low[3]~25_combout = (\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|alu_|db_low[3]~11_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~25 .lut_mask = 16'hF1F1; -defparam \z80_|alu_|db_low[3]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N12 -cycloneive_lcell_comb \z80_|alu_|db[3]~10 ( -// Equation(s): -// \z80_|alu_|db[3]~10_combout = (\z80_|execute_|ctl_alu_oe~14_combout & (\z80_|alu_|db_low[3]~25_combout & ((\z80_|reg_file_|gdfx_temp1[3]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_alu_oe~14_combout & -// (((\z80_|reg_file_|gdfx_temp1[3]~48_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .datad(\z80_|alu_|db_low[3]~25_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~10 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|db[3]~11 ( -// Equation(s): -// \z80_|alu_|db[3]~11_combout = ((\z80_|alu_|db[3]~10_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[3]~10_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[3]~35_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~11 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_alu_oe~9_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~3_combout ), - .datac(\z80_|execute_|ctl_alu_oe~9_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~49 ( -// Equation(s): -// \z80_|execute_|setM1~49_combout = (\z80_|execute_|setM1~48_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~49 .lut_mask = 16'h0070; -defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~14_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~49_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|setM1~49_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h0B0F; -defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|alu_|db_low[3]~25_combout & ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[3]~35_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_low[3]~25_combout & -// (\z80_|alu_control_|db[3]~35_combout & (\z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|alu_|db_low[3]~25_combout ), - .datab(\z80_|alu_control_|db[3]~35_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hEAC0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout = (\z80_|pla_decode_|Equal56~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # ((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # -// (!\z80_|execute_|ctl_flags_xy_we~10_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~14_combout = (((\z80_|execute_|ctl_flags_xy_we~13_combout ) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) - - .dataa(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~15_combout = (((\z80_|execute_|ctl_flags_xy_we~14_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N31 -dffeas \z80_|alu_flags_|flags_xf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_xf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_xf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( -// Equation(s): -// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_flags_|flags_xf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hF030; -defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFEFA; -defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|execute_|ixy_d~7_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFAEA; -defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N16 -cycloneive_lcell_comb \z80_|sw1_|db_down[3]~1 ( -// Equation(s): -// \z80_|sw1_|db_down[3]~1_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[3]~1 .lut_mask = 16'hFF8C; -defparam \z80_|sw1_|db_down[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( -// Equation(s): -// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & (\z80_|sw1_|db_down[3]~1_combout & ((\z80_|reg_file_|gdfx_temp0[3]~52_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datab(\z80_|alu_control_|db[3]~33_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|sw1_|db_down[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'h8C00; -defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( -// Equation(s): -// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~11_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[3]~34_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hBF33; -defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [3] & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[3]~35_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .datad(\z80_|alu_control_|db[3]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|gdfx_temp0[3]~46_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .datab(gnd), - .datac(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~49_combout & \z80_|reg_file_|gdfx_temp0[3]~47_combout )) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N31 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N5 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~51_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & (\z80_|reg_file_|gdfx_temp0[3]~50_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~52_combout = ((\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp0[3]~52_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[3]~52_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hAA0A; -defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( -// Equation(s): -// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [3]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h3030; -defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N17 -dffeas \z80_|address_latch_|Q[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [3]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout = \z80_|address_latch_|Q [3] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .lut_mask = 16'h40BF; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout )))) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h6AAA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|gdfx_temp0[4]~53_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|alu_control_|db[4]~32_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hBB00; -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N27 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N1 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~58_combout & (\z80_|reg_file_|gdfx_temp0[4]~59_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'hA200; -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N21 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N11 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N1 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N7 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|gdfx_temp0[4]~55_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~61_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & (\z80_|reg_file_|gdfx_temp0[4]~60_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & \z80_|reg_file_|gdfx_temp0[4]~56_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~62_combout = ((\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|reg_file_|gdfx_temp0[4]~62_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[4]~62_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hCC0C; -defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N16 -cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( -// Equation(s): -// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~15_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [4]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h3300; -defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N23 -dffeas \z80_|address_latch_|Q[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [4]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|address_latch_|Q [4]), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout -// ))) - - .dataa(\z80_|address_latch_|Q [5]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h6A6A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N23 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N13 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N21 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N5 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [5] & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[5]~15_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .datad(\z80_|alu_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|gdfx_temp0[5]~66_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .datad(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N3 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~67_combout & (\z80_|reg_file_|gdfx_temp0[5]~65_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~68_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~71_combout = (\z80_|reg_file_|gdfx_temp0[5]~64_combout & (\z80_|reg_file_|gdfx_temp0[5]~63_combout & \z80_|reg_file_|gdfx_temp0[5]~70_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~72_combout = ((\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .lut_mask = 16'hD5F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|reg_file_|gdfx_temp0[5]~72_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[5]~72_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'hF050; -defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( -// Equation(s): -// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~18_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [5]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N27 -dffeas \z80_|address_latch_|Q[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [5]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N26 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout = \z80_|address_latch_|Q [5] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout ))) - - .dataa(\z80_|address_latch_|Q [5]), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .lut_mask = 16'h5595; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N17 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N7 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N19 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N5 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N3 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[6]~22_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|gdfx_temp0[6]~76_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~78_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & \z80_|reg_file_|gdfx_temp0[6]~77_combout )) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N5 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~74_combout & (\z80_|reg_file_|gdfx_temp0[6]~73_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & \z80_|reg_file_|gdfx_temp0[6]~75_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[6]~82_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .datad(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( -// Equation(s): -// \z80_|address_latch_|abusz [6] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[6]~21_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N23 -dffeas \z80_|address_latch_|Q[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [6]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # (\z80_|execute_|ctl_inc_dec~7_combout ))))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h001E; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h55AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'hF575; -defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N25 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N29 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N19 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N11 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~92_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|gdfx_temp0[7]~86_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .datad(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[7]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & \z80_|reg_file_|gdfx_temp0[7]~89_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~91_combout = (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~84_combout & \z80_|reg_file_|gdfx_temp0[7]~90_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~92 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~92_combout = ((\z80_|reg_file_|gdfx_temp0[7]~91_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[7]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[7]~0_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[7]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[7]~0 .lut_mask = 16'hF0F8; -defparam \z80_|reg_file_|db_lo_ds[7]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N11 -dffeas \z80_|interrupts_|im2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~12_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|interrupts_|im2~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h5000; -defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|execute_|ctl_mRead~12_combout & \z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~17 ( -// Equation(s): -// \z80_|alu_control_|db[7]~17_combout = (\z80_|reg_file_|db_lo_ds[7]~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|reg_file_|db_lo_ds[7]~0_combout ), - .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|bus_control_|db[7]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~17 .lut_mask = 16'h2A0A; -defparam \z80_|alu_control_|db[7]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~16 ( -// Equation(s): -// \z80_|alu_control_|db[7]~16_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[7]~21_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (\z80_|execute_|ctl_sw_2u~7_combout & (!\z80_|alu_|db[7]~21_combout ))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_|db[7]~21_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~16 .lut_mask = 16'h0CAE; -defparam \z80_|alu_control_|db[7]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( -// Equation(s): -// \z80_|alu_control_|db[7]~18_combout = ((\z80_|alu_control_|db[7]~17_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & !\z80_|alu_control_|db[7]~16_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[7]~17_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_control_|db[7]~16_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h33B3; -defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[7]~18_combout ) # ((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout -// & (((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[7]~18_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~7_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~3_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y9_N9 -dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'h008C; -defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h0088; +defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X37_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( // Equation(s): -// \z80_|execute_|ctl_flags_pf_we~8_combout = (((\z80_|execute_|ctl_flags_pf_we~5_combout ) # (\z80_|execute_|ctl_flags_pf_we~7_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ) - - .dataa(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # ((!\z80_|execute_|ctl_pf_sel[0]~3_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~11_combout ) - - .dataa(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|execute_|ctl_flags_bus~combout & (\z80_|alu_control_|db[2]~29_combout ))) # (!\z80_|execute_|ctl_flags_pf_we~9_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[2]~29_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'h88F0; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (((!\z80_|pla_decode_|Equal62~3_combout & !\z80_|execute_|ctl_alu_op_low~13_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h3070; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ))))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h152A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h3B00; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N24 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [14] & (!\z80_|address_latch_|Q [12] & (!\z80_|address_latch_|Q [15] & !\z80_|address_latch_|Q [13]))) - - .dataa(\z80_|address_latch_|Q [14]), - .datab(\z80_|address_latch_|Q [12]), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|Q [13]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N16 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~3_combout = (!\z80_|address_latch_|Q [1] & (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [3] & !\z80_|address_latch_|Q [2]))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|address_latch_|Q [0]), - .datac(\z80_|address_latch_|Q [3]), - .datad(\z80_|address_latch_|Q [2]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0004; -defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N14 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [6] & (!\z80_|address_latch_|Q [5] & !\z80_|address_latch_|Q [4]))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [6]), - .datac(\z80_|address_latch_|Q [5]), - .datad(\z80_|address_latch_|Q [4]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N8 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [11] & (!\z80_|address_latch_|Q [9] & !\z80_|address_latch_|Q [8]))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [11]), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|Q [8]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N18 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~0_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & (\z80_|decode_state_|DFFE_instNonRep~2_combout & \z80_|decode_state_|DFFE_instNonRep~1_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instNonRep~0_combout ), - .datab(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; -defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N16 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~9_combout & -// ((\z80_|decode_state_|DFFE_instNonRep~4_combout ))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|decode_state_|DFFE_instNonRep~q )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~q ), - .datad(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hF4B0; -defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y16_N17 -dffeas \z80_|decode_state_|DFFE_instNonRep ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instNonRep~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N12 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|pla_decode_|Equal62~3_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h0040; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & -// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - - .dataa(\z80_|interrupts_|DFFE_instIFF2~q ), - .datab(\z80_|decode_state_|DFFE_instNonRep~q ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'hA030; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout & -// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'h808C; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N23 -dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|alu_parity_out~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55FD; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & -// \z80_|alu_|alu_op1[1]~0_combout )))) # (!\z80_|alu_|alu_op2[1]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[1]~0_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[1]~1_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|alu_|alu_op1[1]~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'hFB20; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( -// Equation(s): -// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'hA55A; -defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( -// Equation(s): -// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout $ (\z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .datad(\z80_|alu_|alu_parity_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out .lut_mask = 16'hA956; -defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'hFFEF; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h20A0; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_|alu_parity_out~combout & \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .datac(\z80_|alu_|alu_parity_out~combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFEEE; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout & \z80_|execute_|ctl_flags_alu~15_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'hECCC; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N15 -dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( -// Equation(s): -// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal40~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ))) +// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal40~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|sel[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h70F0; -defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout = (!\z80_|alu_|db_high[1]~20_combout & (!\z80_|alu_|db_high[3]~8_combout & (!\z80_|alu_|db_high[2]~14_combout & !\z80_|alu_|db_high[0]~26_combout ))) - - .dataa(\z80_|alu_|db_high[1]~20_combout ), - .datab(\z80_|alu_|db_high[3]~8_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|alu_|db_high[0]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .lut_mask = 16'h0001; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout = (\z80_|alu_control_|db[6]~22_combout & \z80_|execute_|ctl_flags_bus~combout ) - - .dataa(\z80_|alu_control_|db[6]~22_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .lut_mask = 16'hAA00; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N14 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[3]~11_combout & (\z80_|alu_|db_high[3]~3_combout & ((!\z80_|alu_|db_low[2]~3_combout ) # (!\z80_|alu_|db_low[2]~6_combout )))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|alu_|db_low[2]~3_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h1300; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_low[1]~17_combout & (\z80_|execute_|ctl_flags_alu~15_combout & (!\z80_|alu_|db_low[0]~23_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_flags_alu~15_combout ), - .datac(\z80_|alu_|db_low[0]~23_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0400; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hF7FF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hEC00; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y13_N27 -dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|alu_control_|sel[1]~0_combout & (((\z80_|ir_|opcode [4])))) # (!\z80_|alu_control_|sel[1]~0_combout & ((\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ))) # (!\z80_|ir_|opcode [4] -// & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(\z80_|alu_control_|sel[1]~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hFC0A; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & (\z80_|alu_flags_|DFFE_inst_latch_sf~q )) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_pf~q ))))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datac(\z80_|alu_control_|sel[1]~0_combout ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hAFC0; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( -// Equation(s): -// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((\z80_|alu_control_|flags_cond_true~q )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|flags_cond_true~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hB874; -defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N21 -dffeas \z80_|alu_control_|flags_cond_true ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_control_|flags_cond_true~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|flags_cond_true~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; -defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~13_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sel_wz~14_combout ) # (((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~11_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|gdfx_temp0[0]~93_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~20_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N23 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X31_Y10_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .datad(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & (((\z80_|alu_control_|db[1]~26_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[1]~26_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N3 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N9 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~28_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & (\z80_|reg_file_|gdfx_temp0[1]~29_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N27 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N25 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~23_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'hF733; -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[1]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[1]~1_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[1]~1 .lut_mask = 16'hF0F8; -defparam \z80_|reg_file_|db_lo_ds[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N30 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( -// Equation(s): -// \z80_|alu_control_|db[1]~25_combout = (\z80_|reg_file_|db_lo_ds[1]~1_combout & (((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[1]~11_combout ), - .datab(\z80_|reg_file_|db_lo_ds[1]~1_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h0C8C; -defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~24 ( -// Equation(s): -// \z80_|alu_control_|db[1]~24_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[1]~13_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (\z80_|execute_|ctl_sw_2u~7_combout & ((!\z80_|alu_|db[1]~13_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_|db[1]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~24 .lut_mask = 16'h0ACE; -defparam \z80_|alu_control_|db[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( -// Equation(s): -// \z80_|alu_control_|db[1]~26_combout = ((\z80_|alu_control_|db[1]~25_combout & (\z80_|alu_control_|db[2]~23_combout & !\z80_|alu_control_|db[1]~24_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[1]~25_combout ), - .datab(\z80_|alu_control_|db[2]~23_combout ), - .datac(\z80_|alu_control_|db[6]~11_combout ), - .datad(\z80_|alu_control_|db[1]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h0F8F; -defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db[1]~12 ( -// Equation(s): -// \z80_|alu_|db[1]~12_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[1]~26_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~12 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db[1]~13 ( -// Equation(s): -// \z80_|alu_|db[1]~13_combout = ((\z80_|alu_|db[1]~12_combout & ((\z80_|alu_|db_low[1]~17_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[1]~12_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_low[1]~17_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~13 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( -// Equation(s): -// \z80_|alu_|db_low[0]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~13_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hF5A0; -defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( -// Equation(s): -// \z80_|alu_|db_low[0]~22_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[0]~21_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[0]~19_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db_low[0]~21_combout ), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~18 ( -// Equation(s): -// \z80_|alu_|db_low[0]~18_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~18 .lut_mask = 16'h5557; -defparam \z80_|alu_|db_low[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~19 ( -// Equation(s): -// \z80_|alu_|db_low[0]~19_combout = (\z80_|alu_|op2_low [0] & (((\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [0]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_low [0]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~19 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_low[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N25 -dffeas \z80_|alu_|result_lo[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~20 ( -// Equation(s): -// \z80_|alu_|db_low[0]~20_combout = (\z80_|alu_|db_low[0]~18_combout & (\z80_|alu_|db_low[0]~19_combout & ((\z80_|alu_|result_lo [0]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[0]~18_combout ), - .datab(\z80_|alu_|db_low[0]~19_combout ), - .datac(\z80_|alu_|result_lo [0]), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~20 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( -// Equation(s): -// \z80_|alu_|db_low[0]~23_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[0]~22_combout & ((\z80_|alu_|db_low[0]~20_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[0]~20_combout ) # -// (!\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|alu_|db_low[0]~22_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_low[0]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'hAF03; -defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( -// Equation(s): -// \z80_|alu_|db[0]~18_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|alu_|db_low[0]~23_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_|db_low[0]~23_combout ) # ((!\z80_|execute_|ctl_alu_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_|db_low[0]~23_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~18 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|db[0]~19 ( -// Equation(s): -// \z80_|alu_|db[0]~19_combout = ((\z80_|alu_|db[0]~18_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[0]~12_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~19 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( -// Equation(s): -// \z80_|alu_|db_low[1]~15_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~19_combout )) - - .dataa(\z80_|alu_|db[0]~19_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[2]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( -// Equation(s): -// \z80_|alu_|db_low[1]~16_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[1]~15_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[1]~13_combout ))) - - .dataa(\z80_|alu_|db_low[1]~15_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hAAF0; -defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( -// Equation(s): -// \z80_|alu_|db_low[1]~12_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'h5755; -defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~13 ( -// Equation(s): -// \z80_|alu_|db_low[1]~13_combout = (\z80_|alu_|op2_low [1] & (((\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [1] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [1]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [1]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~13 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_low[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N21 -dffeas \z80_|alu_|result_lo[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~14 ( -// Equation(s): -// \z80_|alu_|db_low[1]~14_combout = (\z80_|alu_|db_low[1]~12_combout & (\z80_|alu_|db_low[1]~13_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[1]~12_combout ), - .datab(\z80_|alu_|db_low[1]~13_combout ), - .datac(\z80_|alu_|result_lo [1]), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~14 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( -// Equation(s): -// \z80_|alu_|db_low[1]~17_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~16_combout & \z80_|alu_|db_low[1]~14_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~14_combout )) # -// (!\z80_|alu_|db_high[3]~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|alu_|db_low[1]~16_combout ), - .datad(\z80_|alu_|db_low[1]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'hF511; -defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # -// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N1 -dffeas \z80_|alu_|op1_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N28 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( -// Equation(s): -// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [1]) # (\z80_|alu_|op1_low [2]))) - - .dataa(gnd), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hF0C0; -defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0F00; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N8 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( -// Equation(s): -// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & -// (((\z80_|alu_flags_|flags_hf2~q )))) - - .dataa(\z80_|alu_control_|db[4]~32_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .datac(\z80_|alu_flags_|flags_hf2~q ), - .datad(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hEEF0; -defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N9 -dffeas \z80_|alu_flags_|flags_hf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|flags_hf2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_hf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~23 ( -// Equation(s): -// \z80_|alu_control_|db[2]~23_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|alu_flags_|flags_hf2~q ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~combout ), - .datab(\z80_|alu_control_|out[6]~0_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|alu_flags_|flags_hf2~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~23 .lut_mask = 16'hFFEF; -defparam \z80_|alu_control_|db[2]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[2]~2_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[2]~2 .lut_mask = 16'hFF40; -defparam \z80_|reg_file_|db_lo_ds[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( -// Equation(s): -// \z80_|alu_control_|db[2]~28_combout = (\z80_|reg_file_|db_lo_ds[2]~2_combout & (((\z80_|bus_control_|db[2]~13_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[2]~13_combout ), - .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h2F00; -defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~27 ( -// Equation(s): -// \z80_|alu_control_|db[2]~27_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((!\z80_|alu_|db[2]~15_combout & \z80_|execute_|ctl_sw_2u~7_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (!\z80_|alu_|db[2]~15_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|alu_|db[2]~15_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~27 .lut_mask = 16'h3B0A; -defparam \z80_|alu_control_|db[2]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( -// Equation(s): -// \z80_|alu_control_|db[2]~29_combout = ((\z80_|alu_control_|db[2]~23_combout & (\z80_|alu_control_|db[2]~28_combout & !\z80_|alu_control_|db[2]~27_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[2]~23_combout ), - .datac(\z80_|alu_control_|db[2]~28_combout ), - .datad(\z80_|alu_control_|db[2]~27_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h55D5; -defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db[2]~14 ( -// Equation(s): -// \z80_|alu_|db[2]~14_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[2]~39_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[2]~29_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[2]~29_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~14 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[2]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db[2]~15 ( -// Equation(s): -// \z80_|alu_|db[2]~15_combout = ((\z80_|alu_|db[2]~14_combout & ((\z80_|alu_|db_low[2]~24_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_low[2]~24_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[2]~14_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~15 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[2]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N4 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~2 ( -// Equation(s): -// \z80_|alu_|db_low[2]~2_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[1]~13_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[3]~11_combout ), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~2 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|db_low[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~3 ( -// Equation(s): -// \z80_|alu_|db_low[2]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~15_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[2]~15_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_low[2]~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~3 .lut_mask = 16'hF3BB; -defparam \z80_|alu_|db_low[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_high[3]~3_combout ), - .datac(\z80_|alu_|db_low[2]~3_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .lut_mask = 16'hB300; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'h3222; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N25 -dffeas \z80_|alu_|op1_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ) # ((\z80_|alu_|db_low[2]~24_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), - .datac(\z80_|alu_|db_low[2]~24_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N13 -dffeas \z80_|alu_|op2_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~5 ( -// Equation(s): -// \z80_|alu_|db_low[2]~5_combout = (\z80_|alu_|op2_low [2] & ((\z80_|alu_|op1_low [2]) # ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_low [2] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [2]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [2]), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~5 .lut_mask = 16'h8ACF; -defparam \z80_|alu_|db_low[2]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N13 -dffeas \z80_|alu_|result_lo[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~6 ( -// Equation(s): -// \z80_|alu_|db_low[2]~6_combout = (\z80_|alu_|db_low[2]~4_combout & (\z80_|alu_|db_low[2]~5_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [2])))) - - .dataa(\z80_|alu_|db_low[2]~4_combout ), - .datab(\z80_|alu_|db_low[2]~5_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|result_lo [2]), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~6 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[2]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_low[2]~3_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h80F0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N27 -dffeas \z80_|alu_|op2_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~0 ( -// Equation(s): -// \z80_|alu_|alu_op2[2]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) - - .dataa(\z80_|alu_|op2_high [2]), - .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|alu_|op2_low [2]), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[2]~0 .lut_mask = 16'h4B78; -defparam \z80_|alu_|alu_op2[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h0BFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[2]~2_combout & -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|alu_|alu_op2[2]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[2]~2_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[2]~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .datac(\z80_|alu_|alu_op1[2]~2_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hECC8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( -// Equation(s): -// \z80_|alu_|db_high[2]~9_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'h55D5; -defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( -// Equation(s): -// \z80_|alu_|db_high[2]~11_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~21_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~25_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(\z80_|alu_|db[7]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'hFA50; -defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( -// Equation(s): -// \z80_|alu_|db_high[2]~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[2]~11_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[6]~23_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[2]~11_combout ), - .datac(\z80_|alu_|db[6]~23_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( -// Equation(s): -// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [2]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( -// Equation(s): -// \z80_|alu_|db_high[2]~13_combout = (\z80_|alu_|db_high[2]~9_combout & (\z80_|alu_|db_high[2]~10_combout & ((\z80_|alu_|db_high[2]~12_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[2]~9_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[2]~12_combout ), - .datad(\z80_|alu_|db_high[2]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hA200; -defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~14 ( -// Equation(s): -// \z80_|alu_|db_high[2]~14_combout = ((\z80_|alu_|db_high[2]~13_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .datab(\z80_|alu_|db_high[3]~3_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_high[2]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~14 .lut_mask = 16'hFB33; -defparam \z80_|alu_|db_high[2]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( -// Equation(s): -// \z80_|alu_|db[6]~22_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .datad(\z80_|alu_control_|db[6]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db[6]~23 ( -// Equation(s): -// \z80_|alu_|db[6]~23_combout = ((\z80_|alu_|db[6]~22_combout & ((\z80_|alu_|db_high[2]~14_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_high[2]~14_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~23 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[6]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N10 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( -// Equation(s): -// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_|op1_high [0] & \z80_|alu_control_|out[6]~0_combout ))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|alu_|op1_high [0]), - .datac(\z80_|alu_|op1_high [1]), - .datad(\z80_|alu_control_|out[6]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEFA; -defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N26 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( -// Equation(s): -// \z80_|alu_control_|out[6]~2_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) - - .dataa(\z80_|execute_|ctl_66_oe~combout ), - .datab(\z80_|alu_control_|out[6]~1_combout ), - .datac(\z80_|alu_|op1_high [3]), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFFEA; -defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~19 ( -// Equation(s): -// \z80_|alu_control_|db[6]~19_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & -// (!\z80_|execute_|ctl_flags_oe~2_combout & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|out[6]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~19 .lut_mask = 16'hAF8C; -defparam \z80_|alu_control_|db[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~20 ( -// Equation(s): -// \z80_|alu_control_|db[6]~20_combout = (\z80_|alu_control_|db[6]~19_combout & ((\z80_|alu_|db[6]~23_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db[6]~23_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[6]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~20 .lut_mask = 16'hCF00; -defparam \z80_|alu_control_|db[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( -// Equation(s): -// \z80_|alu_control_|db[6]~21_combout = (\z80_|alu_control_|db[6]~20_combout & (((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[6]~9_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|alu_control_|db[6]~20_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'h30B0; -defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( -// Equation(s): -// \z80_|alu_control_|db[6]~22_combout = ((\z80_|alu_control_|db[6]~21_combout & ((\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[6]~21_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'hD5DD; -defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal33~1_combout & ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .combout(\z80_|execute_|ctl_mRead~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'hC800; -defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( +// Location: LCCOMB_X37_Y6_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( // Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[3]~21_combout ) +// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) - .dataa(gnd), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[3]~21_combout ), + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .combout(\z80_|pla_decode_|Equal77~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h00CC; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0100; +defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y10_N9 -dffeas \z80_|interrupts_|im1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( +// Location: LCCOMB_X37_Y12_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( // Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|interrupts_|im1~q ), - .datac(\z80_|interrupts_|im2~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hDC00; -defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & -// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h40EE; -defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N0 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( -// Equation(s): -// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) +// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout )) .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[0]~4_combout ), + .combout(\z80_|pla_decode_|Equal50~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hFF31; -defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N6 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( +// Location: LCCOMB_X40_Y13_N16 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( // Equation(s): -// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) +// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) - .dataa(gnd), - .datab(\z80_|alu_control_|db[6]~22_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[6]~8_combout ), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~37 ( +// Location: LCCOMB_X30_Y11_N20 +cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( // Equation(s): -// \z80_|execute_|ctl_mRead~37_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|sequencer_|DFFE_T5_ff~q ) +// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|interrupts_|DFFE_inst44~q & !\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~37 .lut_mask = 16'hDDDF; -defparam \z80_|execute_|ctl_mRead~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~37_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~37_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ctl_mRead~28_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~28_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_mRead~29_combout & (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & !\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ))) - - .dataa(\z80_|execute_|ctl_mRead~29_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_mRead~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~37 ( -// Equation(s): -// \z80_|execute_|setM1~37_combout = (!\z80_|pla_decode_|Equal9~1_combout & (!\z80_|pla_decode_|Equal29~0_combout & (\z80_|execute_|ctl_al_we~4_combout & \z80_|execute_|ctl_inc_cy~41_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|execute_|ctl_al_we~4_combout ), - .datad(\z80_|execute_|ctl_inc_cy~41_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~37 .lut_mask = 16'h1000; -defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~55 ( -// Equation(s): -// \z80_|execute_|setM1~55_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~55 .lut_mask = 16'h3233; -defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~38 ( -// Equation(s): -// \z80_|execute_|setM1~38_combout = (!\z80_|execute_|ctl_mRead~16_combout & (\z80_|execute_|setM1~37_combout & (\z80_|execute_|setM1~55_combout & \z80_|execute_|setM1~36_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|setM1~37_combout ), - .datac(\z80_|execute_|setM1~55_combout ), - .datad(\z80_|execute_|setM1~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~38 .lut_mask = 16'h4000; -defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~34_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|setM1~38_combout ))) - - .dataa(\z80_|execute_|setM1~38_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~3 ( -// Equation(s): -// \z80_|execute_|nextM~3_combout = (!\z80_|pla_decode_|Equal41~2_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ixy_d~16_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0003; -defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|nextM~3_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_mRead~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|execute_|ctl_mRead~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFC0; -defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~35 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~35_combout = ((\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|execute_|ctl_mRead~31_combout ) # (\z80_|execute_|ctl_mRead~33_combout ))) # (!\z80_|execute_|ctl_mRead~30_combout ) - - .dataa(\z80_|execute_|ctl_mRead~30_combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|ctl_mRead~31_combout ), - .datad(\z80_|execute_|ctl_mRead~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~35 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_mRead~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N23 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mRead~35_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N24 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X46_Y15_N25 -dffeas \z80_|memory_ifc_|wait_mrd ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mrd~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N3 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_mrd~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N8 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & !\z80_|memory_ifc_|DFFE_mrd_ff3~q ) - - .dataa(\z80_|memory_ifc_|wait_mrd~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0055; -defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|nextM~4 ( -// Equation(s): -// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout ) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~4 .lut_mask = 16'h373F; -defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~12_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_iorw~12_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~11_combout & \z80_|execute_|ctl_mWrite~16_combout ))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|nextM~4_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_iorw~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N7 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_iorw~9_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N26 -cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder ( -// Equation(s): -// \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout = \z80_|memory_ifc_|DFFE_iorq_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N27 -dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N9 -dffeas \z80_|memory_ifc_|wait_iorq ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorq~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N13 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorq~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( -// Equation(s): -// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|wait_iorq~q ), - .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|iorq~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; -defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( -// Equation(s): -// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hA800; -defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( -// Equation(s): -// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_alu_op_low~9_combout ) # ((\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|fIOWrite~0_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|fIORead~1_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFFF2; -defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( -// Equation(s): -// \z80_|execute_|fIORead~0_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hA080; -defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( -// Equation(s): -// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|fIOWrite~1_combout ), - .datab(\z80_|execute_|fIORead~2_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|fIORead~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N25 -dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|setM1~52_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_m1_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N14 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( -// Equation(s): -// \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_m1_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N15 -dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N21 -dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_m1_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N20 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|interrupts_|DFFE_inst44~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # (\z80_|memory_ifc_|DFFE_m1_ff3~q )))) # (!\z80_|interrupts_|DFFE_inst44~q & -// ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # ((\z80_|memory_ifc_|DFFE_m1_ff3~q )))) - - .dataa(\z80_|interrupts_|DFFE_inst44~q ), - .datab(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .datac(\z80_|memory_ifc_|DFFE_m1_ff3~q ), + .datac(\z80_|interrupts_|DFFE_inst44~q ), .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~0_combout ), + .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hFC54; -defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0010; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N18 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~2_combout = ((\z80_|memory_ifc_|nRD_out~0_combout ) # ((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIORead~3_combout ))) # (!\z80_|memory_ifc_|nRD_out~1_combout ) - - .dataa(\z80_|memory_ifc_|nRD_out~1_combout ), - .datab(\z80_|memory_ifc_|iorq~0_combout ), - .datac(\z80_|execute_|fIORead~3_combout ), - .datad(\z80_|memory_ifc_|nRD_out~0_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~2_combout ), - .cout()); +// Location: FF_X30_Y11_N21 +dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .prn(vcc)); // synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hFFD5; -defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N24 -cycloneive_lcell_comb \Equal2~1 ( -// Equation(s): -// \Equal2~1_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~1 .lut_mask = 16'h4040; -defparam \Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~0 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~0 .lut_mask = 16'hFFAA; -defparam \z80_|pin_control_|bus_db_pin_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( -// Equation(s): -// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h3F33; -defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( -// Equation(s): -// \z80_|execute_|fMWrite~6_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) - - .dataa(\z80_|execute_|fMWrite~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'h5554; -defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( -// Equation(s): -// \z80_|execute_|fMWrite~2_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h555F; -defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( -// Equation(s): -// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fMWrite~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|fMWrite~2_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h00EF; -defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~1 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~1_combout = (\z80_|execute_|ctl_bus_inc_oe~24_combout & (!\z80_|execute_|fIOWrite~5_combout & (!\z80_|execute_|fMWrite~6_combout & !\z80_|execute_|fMWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .datab(\z80_|execute_|fIOWrite~5_combout ), - .datac(\z80_|execute_|fMWrite~6_combout ), - .datad(\z80_|execute_|fMWrite~4_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~1 .lut_mask = 16'h0002; -defparam \z80_|pin_control_|bus_db_pin_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'h135F; -defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N24 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|pin_control_|bus_db_pin_oe~2_combout & (((\z80_|execute_|ixy_d~4_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'hA2AA; -defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( -// Equation(s): -// \z80_|execute_|fMWrite~7_combout = (!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_mRead~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'h0003; -defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~7_combout ) # ((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|fMWrite~7_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'hCD00; -defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~10_combout & ((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h0777; -defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N4 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|fMRead~1_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout )) # -// (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|fMRead~1_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h3715; -defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|fMWrite~9 ( -// Equation(s): -// \z80_|execute_|fMWrite~9_combout = (\z80_|pla_decode_|Equal46~0_combout ) # (((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout )) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~9 .lut_mask = 16'hCEFF; -defparam \z80_|execute_|fMWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|execute_|fIOWrite~0_combout & ((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) # (!\z80_|execute_|ctl_mWrite~6_combout & -// (((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|fMWrite~2_combout ), - .datad(\z80_|execute_|fMWrite~9_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'hDDD0; -defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N0 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (\z80_|execute_|fMWrite~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout )) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .datab(\z80_|execute_|fMWrite~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h0808; -defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( -// Equation(s): -// \z80_|execute_|fMWrite~8_combout = (\z80_|execute_|ctl_state_alu~6_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & (\z80_|execute_|ctl_reg_sel_wz~5_combout & (!\z80_|execute_|fMWrite~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .datac(\z80_|execute_|fMWrite~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h0800; -defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|pin_control_|bus_db_pin_oe~7_combout & (\z80_|pin_control_|bus_db_pin_oe~6_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~5_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|fMWrite~10 ( -// Equation(s): -// \z80_|execute_|fMWrite~10_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|execute_|ctl_alu_oe~2_combout & -// ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~10 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N0 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|pin_control_|bus_db_pin_oe~10_combout & (!\z80_|execute_|fMWrite~10_combout & \z80_|execute_|ctl_bus_inc_oe~28_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .datac(\z80_|execute_|fMWrite~10_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h0800; -defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~3_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h2A00; -defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (\z80_|pin_control_|bus_db_pin_oe~1_combout & (\z80_|pin_control_|bus_db_pin_oe~12_combout & \z80_|execute_|ctl_inc_cy~37_combout ))) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .datad(\z80_|execute_|ctl_inc_cy~37_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N28 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout ))) # -// (!\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|fIOWrite~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'hF222; -defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N0 +// Location: LCCOMB_X39_Y14_N26 cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( // Equation(s): // \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q @@ -37040,7 +6633,7 @@ defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y15_N1 +// Location: FF_X39_Y14_N27 dffeas \z80_|clk_delay_|DFF_inst5 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), @@ -37059,3754 +6652,96 @@ defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y15_N22 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorqinta~feeder ( +// Location: LCCOMB_X39_Y14_N4 +cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( // Equation(s): -// \z80_|memory_ifc_|wait_iorqinta~feeder_combout = \z80_|clk_delay_|DFF_inst5~q +// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|DFF_inst5~q & !\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ) - .dataa(gnd), + .dataa(\z80_|clk_delay_|DFF_inst5~q ), .datab(gnd), .datac(gnd), - .datad(\z80_|clk_delay_|DFF_inst5~q ), + .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), .cin(gnd), - .combout(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), + .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .sum_lutc_input = "datac"; +defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0055; +defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y15_N23 -dffeas \z80_|memory_ifc_|wait_iorqinta ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), +// Location: FF_X40_Y13_N17 +dffeas \z80_|sequencer_|DFFE_T5_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorqinta~q ), + .q(\z80_|sequencer_|DFFE_T5_ff~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; +defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; // synopsys translate_on -// Location: FF_X43_Y15_N13 -dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Location: LCCOMB_X32_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( // Equation(s): -// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|wait_iorqinta~q ) # ((\z80_|memory_ifc_|DFFE_intr_ff3~q ) # (\z80_|memory_ifc_|iorq~0_combout )) +// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) - .dataa(\z80_|memory_ifc_|wait_iorqinta~q ), - .datab(gnd), - .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .datad(\z80_|memory_ifc_|iorq~0_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFFFA; -defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N18 -cycloneive_lcell_comb \Equal2~0 ( -// Equation(s): -// \Equal2~0_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~0 .lut_mask = 16'h4000; -defparam \Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N22 -cycloneive_lcell_comb \ExtRamWE~0 ( -// Equation(s): -// \ExtRamWE~0_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\ExtRamWE~0_combout ), - .cout()); -// synopsys translate_off -defparam \ExtRamWE~0 .lut_mask = 16'h0020; -defparam \ExtRamWE~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [13]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [13]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|ixy_d~15_combout ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), + .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h0B0B; -defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N28 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~2_combout = (((\z80_|execute_|fMRead~35_combout ) # (\z80_|execute_|fIORead~3_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .datac(\z80_|execute_|fMRead~35_combout ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFFF7; -defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N2 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pin_control_|bus_ab_pin_we~2_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T3_ff~q & -// (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pin_control_|bus_ab_pin_we~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h3B0A; -defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .asdata(\z80_|address_latch_|Q [13]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[13]~20 ( -// Equation(s): -// \z80_|address_pins_|abus[13]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[13]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[13]~20 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[13]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [14])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [14]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [14]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .asdata(\z80_|address_latch_|Q [14]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N4 -cycloneive_lcell_comb \z80_|address_pins_|abus[14]~23 ( -// Equation(s): -// \z80_|address_pins_|abus[14]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[14]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[14]~23 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[14]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [15]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .asdata(\z80_|address_latch_|Q [15]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N12 -cycloneive_lcell_comb \z80_|address_pins_|abus[15]~22 ( -// Equation(s): -// \z80_|address_pins_|abus[15]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[15]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[15]~22 .lut_mask = 16'hF3F3; -defparam \z80_|address_pins_|abus[15]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h0800; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00C0; -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( -// Equation(s): -// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [1]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [1]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .asdata(\z80_|address_latch_|Q [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( -// Equation(s): -// \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [1]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [2]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .asdata(\z80_|address_latch_|Q [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N26 -cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( -// Equation(s): -// \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [2]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[2]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N0 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [3])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [3]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N1 -dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .asdata(\z80_|address_latch_|Q [3]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N12 -cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( -// Equation(s): -// \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [3]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[3]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N30 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [4])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [4]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N31 -dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .asdata(\z80_|address_latch_|Q [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N2 -cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( -// Equation(s): -// \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [4]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[4]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N12 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [5]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N13 -dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .asdata(\z80_|address_latch_|Q [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( -// Equation(s): -// \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[5]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hF3F3; -defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [6])) - - .dataa(\z80_|address_latch_|abusz [6]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .asdata(\z80_|address_latch_|Q [6]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N28 -cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( -// Equation(s): -// \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [6]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[6]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hCFCF; -defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N30 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [7]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N31 -dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .asdata(\z80_|address_latch_|Q [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N22 -cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( -// Equation(s): -// \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [7]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[7]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N20 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [8])) - - .dataa(\z80_|address_latch_|abusz [8]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N21 -dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .asdata(\z80_|address_latch_|Q [8]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N30 -cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( -// Equation(s): -// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [8]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[8]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N16 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [9]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [9]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N17 -dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .asdata(\z80_|address_latch_|Q [9]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N4 -cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( -// Equation(s): -// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [9]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[9]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N24 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [10]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .datab(\z80_|address_latch_|abusz [10]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N25 -dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .asdata(\z80_|address_latch_|Q [10]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N24 -cycloneive_lcell_comb \z80_|address_pins_|abus[10]~24 ( -// Equation(s): -// \z80_|address_pins_|abus[10]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [10]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[10]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[10]~24 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[10]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N6 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datab(\z80_|address_latch_|abusz [11]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N7 -dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .asdata(\z80_|address_latch_|Q [11]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( -// Equation(s): -// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [11]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[11]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N16 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [12])) - - .dataa(\z80_|address_latch_|abusz [12]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N17 -dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .asdata(\z80_|address_latch_|Q [12]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N30 -cycloneive_lcell_comb \z80_|address_pins_|abus[12]~21 ( -// Equation(s): -// \z80_|address_pins_|abus[12]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [12]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[12]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[12]~21 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[12]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y11_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X32_Y14_N31 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[13]~20_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X32_Y14_N1 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N12 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0200; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N18 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h000C; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: FF_X29_Y14_N5 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[14]~23_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N21 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N24 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h2000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N26 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h0C00; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N10 -cycloneive_lcell_comb \D[6]~90 ( -// Equation(s): -// \D[6]~90_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .cin(gnd), - .combout(\D[6]~90_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~90 .lut_mask = 16'hCCE2; -defparam \D[6]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N20 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hF333; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N16 -cycloneive_lcell_comb \D[6]~91 ( -// Equation(s): -// \D[6]~91_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~90_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ))) # (!\D[6]~90_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~90_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[6]~90_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), - .cin(gnd), - .combout(\D[6]~91_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~91 .lut_mask = 16'hF838; -defparam \D[6]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N2 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h0020; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G15 -cycloneive_clkctrl \CLOCK_50~inputclkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\CLOCK_50~inputclkctrl_outclk )); -// synopsys translate_off -defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; -defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y24_N16 -cycloneive_lcell_comb \~GND ( -// Equation(s): -// \~GND~combout = GND - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\~GND~combout ), - .cout()); -// synopsys translate_off -defparam \~GND .lut_mask = 16'h0000; -defparam \~GND .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vram_address[0]~feeder ( -// Equation(s): -// \ula_|video_|vram_address[0]~feeder_combout = \ula_|video_|vga_hc [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [4]), - .cin(gnd), - .combout(\ula_|video_|vram_address[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vram_address[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N4 -cycloneive_lcell_comb \ula_|video_|vram_address~0 ( -// Equation(s): -// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N21 -dffeas \ula_|video_|vram_address[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X34_Y33_N19 -dffeas \ula_|video_|vram_address[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N0 -cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( -// Equation(s): -// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|video_|vram_address[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; -defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N1 -dffeas \ula_|video_|vram_address[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N26 -cycloneive_lcell_comb \ula_|video_|Add3~0 ( -// Equation(s): -// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|Add3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N27 -dffeas \ula_|video_|vram_address[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N28 -cycloneive_lcell_comb \ula_|video_|Add3~1 ( -// Equation(s): -// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) - - .dataa(\ula_|video_|vga_hc [6]), - .datab(gnd), - .datac(\ula_|video_|vga_hc [8]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|Add3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~1 .lut_mask = 16'hA50F; -defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N29 -dffeas \ula_|video_|vram_address[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N2 -cycloneive_lcell_comb \ula_|video_|Add4~0 ( -// Equation(s): -// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) -// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) - - .dataa(\ula_|video_|vga_vc [0]), - .datab(\ula_|video_|vga_vc [1]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add4~0_combout ), - .cout(\ula_|video_|Add4~1 )); -// synopsys translate_off -defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; -defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Add4~2 ( -// Equation(s): -// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) -// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~1 ), - .combout(\ula_|video_|Add4~2_combout ), - .cout(\ula_|video_|Add4~3 )); -// synopsys translate_off -defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; -defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N6 -cycloneive_lcell_comb \ula_|video_|Add4~4 ( -// Equation(s): -// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) -// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~3 ), - .combout(\ula_|video_|Add4~4_combout ), - .cout(\ula_|video_|Add4~5 )); -// synopsys translate_off -defparam \ula_|video_|Add4~4 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N8 -cycloneive_lcell_comb \ula_|video_|Add4~6 ( -// Equation(s): -// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) -// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~5 ), - .combout(\ula_|video_|Add4~6_combout ), - .cout(\ula_|video_|Add4~7 )); -// synopsys translate_off -defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N9 -dffeas \ula_|video_|vram_address[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N10 -cycloneive_lcell_comb \ula_|video_|Add4~8 ( -// Equation(s): -// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) -// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~7 ), - .combout(\ula_|video_|Add4~8_combout ), - .cout(\ula_|video_|Add4~9 )); -// synopsys translate_off -defparam \ula_|video_|Add4~8 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N11 -dffeas \ula_|video_|vram_address[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N12 -cycloneive_lcell_comb \ula_|video_|Add4~10 ( -// Equation(s): -// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) -// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~9 ), - .combout(\ula_|video_|Add4~10_combout ), - .cout(\ula_|video_|Add4~11 )); -// synopsys translate_off -defparam \ula_|video_|Add4~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N13 -dffeas \ula_|video_|vram_address[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Add4~12 ( -// Equation(s): -// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) -// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~11 ), - .combout(\ula_|video_|Add4~12_combout ), - .cout(\ula_|video_|Add4~13 )); -// synopsys translate_off -defparam \ula_|video_|Add4~12 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N22 -cycloneive_lcell_comb \ula_|video_|Selector6~0 ( -// Equation(s): -// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~12_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~0_combout ))) - - .dataa(gnd), - .datab(\ula_|video_|Add4~12_combout ), - .datac(\ula_|video_|Add4~0_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector6~0 .lut_mask = 16'hCCF0; -defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N14 -cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( -// Equation(s): -// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address[9]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N23 -dffeas \ula_|video_|vram_address[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector6~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add4~14 ( -// Equation(s): -// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_vc [8]), - .cin(\ula_|video_|Add4~13 ), - .combout(\ula_|video_|Add4~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; -defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N20 -cycloneive_lcell_comb \ula_|video_|Selector5~0 ( -// Equation(s): -// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) - - .dataa(\ula_|video_|Add4~14_combout ), - .datab(gnd), - .datac(\ula_|video_|Add4~2_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector5~0 .lut_mask = 16'hAAF0; -defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N21 -dffeas \ula_|video_|vram_address[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector5~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N28 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( -// Equation(s): -// \ula_|video_|vram_address[10]~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N30 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( -// Equation(s): -// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & (\ula_|video_|vga_hc [1]))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) - - .dataa(\ula_|video_|Add4~4_combout ), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vram_address [10]), - .datad(\ula_|video_|vram_address[10]~2_combout ), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'h88F0; -defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N31 -dffeas \ula_|video_|vram_address[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[10]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N16 -cycloneive_lcell_comb \ula_|video_|Selector3~0 ( -// Equation(s): -// \ula_|video_|Selector3~0_combout = (\ula_|video_|Add4~12_combout ) # (\ula_|video_|vga_hc [2]) - - .dataa(gnd), - .datab(\ula_|video_|Add4~12_combout ), - .datac(gnd), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFCC; -defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N17 -dffeas \ula_|video_|vram_address[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N26 -cycloneive_lcell_comb \ula_|video_|Selector2~0 ( -// Equation(s): -// \ula_|video_|Selector2~0_combout = (\ula_|video_|Add4~14_combout ) # (\ula_|video_|vga_hc [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Add4~14_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFFF0; -defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N27 -dffeas \ula_|video_|vram_address[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[12] .power_up = "low"; -// synopsys translate_on - -// Location: M9K_X33_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N22 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|abus[13]~20_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N23 -dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y14_N1 -dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(gnd), - .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N10 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h0080; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y33_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N2 -cycloneive_lcell_comb \D[6]~87 ( -// Equation(s): -// \D[6]~87_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .cin(gnd), - .combout(\D[6]~87_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~87 .lut_mask = 16'hE6A2; -defparam \D[6]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y1_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N6 -cycloneive_lcell_comb \D[6]~88 ( -// Equation(s): -// \D[6]~88_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ (((\D[6]~87_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~87_combout )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datad(\D[6]~87_combout ), - .cin(gnd), - .combout(\D[6]~88_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~88 .lut_mask = 16'h22D8; -defparam \D[6]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N20 -cycloneive_lcell_comb \D[6]~89 ( -// Equation(s): -// \D[6]~89_combout = (\D[6]~87_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~88_combout )))) # (!\D[6]~87_combout & -// (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \D[6]~88_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datab(\D[6]~87_combout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\D[6]~88_combout ), - .cin(gnd), - .combout(\D[6]~89_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~89 .lut_mask = 16'hC3C8; -defparam \D[6]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N14 -cycloneive_lcell_comb \D[6]~111 ( -// Equation(s): -// \D[6]~111_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\D[6]~91_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\D[6]~89_combout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[6]~91_combout )) - - .dataa(\D[6]~91_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\D[6]~89_combout ), - .cin(gnd), - .combout(\D[6]~111_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~111 .lut_mask = 16'hAEA2; -defparam \D[6]~111 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X16_Y34_N8 -cycloneive_io_ibuf \raw_loader_in~input ( - .i(raw_loader_in), - .ibar(gnd), - .o(\raw_loader_in~input_o )); -// synopsys translate_off -defparam \raw_loader_in~input .bus_hold = "false"; -defparam \raw_loader_in~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N18 -cycloneive_lcell_comb \D[6]~86 ( -// Equation(s): -// \D[6]~86_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(gnd), - .datac(\raw_loader_in~input_o ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\D[6]~86_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~86 .lut_mask = 16'hFAFF; -defparam \D[6]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N28 -cycloneive_lcell_comb \D[6]~100 ( -// Equation(s): -// \D[6]~100_combout = ((\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout ))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~1_combout ), - .datab(\Equal2~0_combout ), - .datac(\D[6]~111_combout ), - .datad(\D[6]~86_combout ), - .cin(gnd), - .combout(\D[6]~100_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~100 .lut_mask = 16'hFD75; -defparam \D[6]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N4 -cycloneive_lcell_comb \D[6]~101 ( -// Equation(s): -// \D[6]~101_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [6] & \D[6]~100_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[6]~100_combout )) # (!\Equal2~1_combout ))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[6]~100_combout ), - .cin(gnd), - .combout(\D[6]~101_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~101 .lut_mask = 16'hCF05; -defparam \D[6]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N12 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[6]~101_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\D[6]~101_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[6]~9_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|fIORead~3_combout )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # -// ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|fIORead~3_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hDC50; -defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N16 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|execute_|fMRead~35_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEA; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N13 -dffeas \z80_|data_pins_|dout[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N16 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( -// Equation(s): -// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[6]~8_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|execute_|ctl_bus_db_oe~combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'h8AFF; -defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N8 -cycloneive_lcell_comb \z80_|ir_|opcode[6]~feeder ( -// Equation(s): -// \z80_|ir_|opcode[6]~feeder_combout = \z80_|bus_control_|db[6]~9_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[6]~9_combout ), - .cin(gnd), - .combout(\z80_|ir_|opcode[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|ir_|opcode[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|ir_|opcode[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_ir_we~5_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N9 -dffeas \z80_|ir_|opcode[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|ir_|opcode[6]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~1_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~2_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~1_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|pla_decode_|Equal41~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal41~2_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFF08; -defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( -// Equation(s): -// \z80_|alu_|db_high[1]~15_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'h7555; -defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( -// Equation(s): -// \z80_|alu_|db_high[1]~16_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [1]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [1]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( -// Equation(s): -// \z80_|alu_|db_high[1]~17_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~23_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~17_combout ))) - - .dataa(\z80_|alu_|db[6]~23_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[4]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hAFA0; -defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( -// Equation(s): -// \z80_|alu_|db_high[1]~18_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[1]~17_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[5]~25_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[1]~17_combout ), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( -// Equation(s): -// \z80_|alu_|db_high[1]~19_combout = (\z80_|alu_|db_high[1]~15_combout & (\z80_|alu_|db_high[1]~16_combout & ((\z80_|alu_|db_high[1]~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[1]~15_combout ), - .datab(\z80_|alu_|db_high[1]~16_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[1]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~20 ( -// Equation(s): -// \z80_|alu_|db_high[1]~20_combout = ((\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~20 .lut_mask = 16'hA8FF; -defparam \z80_|alu_|db_high[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( -// Equation(s): -// \z80_|alu_|db[5]~24_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[5]~15_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_control_|db[5]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db[5]~25 ( -// Equation(s): -// \z80_|alu_|db[5]~25_combout = ((\z80_|alu_|db[5]~24_combout & ((\z80_|alu_|db_high[1]~20_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_high[1]~20_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db[5]~24_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~25 .lut_mask = 16'hB3F3; -defparam \z80_|alu_|db[5]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N14 -cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( -// Equation(s): -// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_1d~6_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[5]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hEFCC; -defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_control_|db[5]~15_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|alu_control_|db[5]~15_combout -// & (\z80_|alu_|db_high[1]~20_combout & ((\z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|alu_control_|db[5]~15_combout ), - .datab(\z80_|alu_|db_high[1]~20_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hECA0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N23 -dffeas \z80_|alu_flags_|flags_yf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_yf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_yf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~13 ( -// Equation(s): -// \z80_|alu_control_|db[5]~13_combout = (\z80_|alu_flags_|flags_yf~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|flags_yf~q & (!\z80_|execute_|ctl_flags_oe~2_combout & -// ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) - - .dataa(\z80_|alu_flags_|flags_yf~q ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|out[6]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~13 .lut_mask = 16'hAF8C; -defparam \z80_|alu_control_|db[5]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~14 ( -// Equation(s): -// \z80_|alu_control_|db[5]~14_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~13_combout & ((\z80_|reg_file_|gdfx_temp0[5]~72_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|sw1_|db_down[5]~0_combout ), - .datab(\z80_|alu_control_|db[5]~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~14 .lut_mask = 16'h8088; -defparam \z80_|alu_control_|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( -// Equation(s): -// \z80_|alu_control_|db[5]~15_combout = ((\z80_|alu_control_|db[5]~14_combout & ((\z80_|alu_|db[5]~25_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_|db[5]~25_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[5]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hDF55; -defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N10 -cycloneive_lcell_comb \D[0]~107 ( -// Equation(s): -// \D[0]~107_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout ) # ((!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nRD_out~2_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|memory_ifc_|nRD_out~2_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[0]~107_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~107 .lut_mask = 16'hFF40; -defparam \D[0]~107 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y9_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: M9K_X22_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .lut_mask = 16'hDC98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y23_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hF838; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y29_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; -// synopsys translate_on - -// Location: M9K_X33_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'hE10F8B8C100323720BEBBDEBB81DF13FF97B252E2CB4F27BA091FBD0002D1A611E1EDBBC716D44D2912B80041C44558060CFCF15955C0D780DD5E71393920844F25E16C87C5D0308EEC52C011514BBC13AFA1028924D0C7CE738105BD47A10AA5B5C1D9D4193E4339F492B0E1A64E13AE35BE6B67AC8057BDACC155F14E906A017A1841358335450D4B26CD2A21B3D8F2211080B81EC040D7FA0B51CD48008112508062020A02490900092D2040259108806A328F4006D2AA514B42FB006ECCCCB9A360865678449975A8AE72B5C0F7BA800C1B5DC55D7D6FE2EF4EED85D00AB111821321BA426A4FE4956B43595832C271E83E060341AE5F2023FC808177383; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h1A2955372D510AC266A5445146E27000020C320FAE1557E37154040A13202DC6F40B840FB9A59B6DBB296562CB6220EFBE99D2776A202044D9101006FD221D305519198C859000004012AFF4FB060307C92BB732203BFDFEFFFFFFDFFF87FCFFFBFFEFF03FFE0FFFBFAFE0FF80787FFF7FFF83F7F87003FFBFFFFBFFFBFF0FFC0FF81FFF7FFBFFDFFFBFFFE1FF0086F3141AAB6005810A0621595A893F9D85983B9254954341968BAC8C141C90938C05B2C9CD267E11650407375FEDD6A2FEB346AAF6CFDC0791AA97B741995A3B3981E06D1A44D3711955197BB9910FCA20744915C84D6C24BAF53929814CA8A4697E8F4201145AE7415DC122A5F010436107; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h02E84F969E3C800AC610D276182020227809001A50DDDBA3487BB6AE802BA06509312DA0E620656EAF24D57C08FFB14D289613DC32083803B84DC6415FD5EDC000300A8D128FA20030ACCBAFA237B7024504D36A4BA26081137F059E78991154FE2AC2A884A8CC7FBBB21C851CC92B12E15593C0C020FFEE066558590E882D5B67459F1A8C3240FE4E6A8D028C0C088FCF471D400A19B38211004DD122212288B111114514CB11840E04828849C621392041163C00808C67223422F00110201DD18FCFFFF3FFE7F9FFFFFFF82C0B422D214711E08904524A069491774E663F48F665955B4E2C63DAC0078652D10120900298F7EE380092442AFD400BEC43C003; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; -// synopsys translate_on - -// Location: M9K_X33_Y29_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80000001C000000160F000FF70C0007F78C00000F05001007870010010000000000800000038000000F000000070000000300000006000000000000040000000F00000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000001D108000BEDA9FA9698A000000000000000000000000FFFFFFFF408102048004188297E014DA9FA9E9CA00000000000000000000000000000000FFFFFFFC800400CA972208DA9FA9CD8E00000000000000000000000000000000FFFFFFFC8004046A97A289FA9FA9CDC20000000000000000000000007FFFFFFC8000000280040E2A97A2997A9DA9CFC20000000000000000000000007FFFFFFE8000000280042EB28002BE369DA9274200000000000000000000000040810206BFFFFFFE9FE430A29D82AC3E8009E34A000000000000000000000000000000023FFFFFFC9FE4B1829FA2800E8009436A; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h9FE8334E88F827C697F88D1600A80A44809E8FC2B86999C2B85B3A82B1D32A869FE8336A88F807CA97F88F96A0A80EC2838E8D42B9E98FC2B86B3B82B0D7B2D2800832E288F827CA97F88B82A0080EC683869542B939B8C2B1AB0F8290B730C2800826EA8878078297F88AD2A0280EC283E694C2B83A3BC2A3AB3E8291A316AA800826EE881807C69DE8ABD6A0280BC282209CD2BA2A3D42A2737F82918314E2800806E6981805C69D48AED6A1E80BCA82709FC2BB223DC2A07B7F8295DF11C2800886E6980805869848AAC6A1E42DC281789DC2BBAA3DC6A02B7582955F00928008A6EE98082D9618088AC8A0F40FC289E89DC2BBCA3DC2A18B7782154F02F0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N0 -cycloneive_lcell_comb \Mux2~0 ( -// Equation(s): -// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .cin(gnd), - .combout(\Mux2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Mux2~0 .lut_mask = 16'hBA98; -defparam \Mux2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N2 -cycloneive_lcell_comb \Mux2~1 ( -// Equation(s): -// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datad(\Mux2~0_combout ), - .cin(gnd), - .combout(\Mux2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Mux2~1 .lut_mask = 16'hBBC0; -defparam \Mux2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N20 -cycloneive_lcell_comb \D[5]~110 ( -// Equation(s): -// \D[5]~110_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux2~1_combout ))))) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) - - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\Mux2~1_combout ), - .cin(gnd), - .combout(\D[5]~110_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~110 .lut_mask = 16'hAEA2; -defparam \D[5]~110 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N28 -cycloneive_lcell_comb \D[5]~85 ( -// Equation(s): -// \D[5]~85_combout = (\D[5]~84_combout & (\D[5]~110_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & (((\z80_|data_pins_|dout [5])) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout ))) - - .dataa(\D[5]~84_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\z80_|data_pins_|dout [5]), - .datad(\D[5]~110_combout ), - .cin(gnd), - .combout(\D[5]~85_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~85 .lut_mask = 16'hF351; -defparam \D[5]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N24 -cycloneive_lcell_comb \D[5]~99 ( -// Equation(s): -// \D[5]~99_combout = (\D[5]~85_combout ) # (!\D[0]~107_combout ) - - .dataa(\D[0]~107_combout ), - .datab(gnd), - .datac(gnd), - .datad(\D[5]~85_combout ), - .cin(gnd), - .combout(\D[5]~99_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~99 .lut_mask = 16'hFF55; -defparam \D[5]~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N14 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[5]~15_combout ) # ((\D[5]~99_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[5]~99_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[5]~99_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N15 -dffeas \z80_|data_pins_|dout[5] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( -// Equation(s): -// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|data_pins_|dout [5]), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hF300; -defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( -// Equation(s): -// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|alu_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[5]~14_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[5]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hF755; -defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N13 -dffeas \z80_|ir_|opcode[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[5]~15_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N20 +// Location: LCCOMB_X37_Y7_N24 cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( // Equation(s): -// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|ir_|opcode [5] & -// ((\z80_|pla_decode_|Equal3~2_combout )))) +// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|ir_|opcode [5] & +// \z80_|pla_decode_|Equal3~2_combout )))) - .dataa(\z80_|ir_|opcode [5]), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|pla_decode_|Equal3~2_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~2_combout ), .cin(gnd), .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h3350; +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2722; defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y15_N21 +// Location: LCCOMB_X37_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T2_ff~q & +// (((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hF222; +defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y7_N25 dffeas \z80_|decode_state_|DFFE_inst4 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), @@ -40825,7174 +6760,2555 @@ defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y18_N4 -cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( +// Location: LCCOMB_X37_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( // Equation(s): -// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q ) +// \z80_|execute_|fMWrite~3_combout = (!\z80_|execute_|ctl_mRead~5_combout & (((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )) # (!\z80_|pla_decode_|Equal50~0_combout ))) - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(gnd), + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|pla_decode_|Equal50~0_combout ), .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(gnd), + .datad(\z80_|decode_state_|DFFE_inst4~q ), .cin(gnd), - .combout(\z80_|decode_state_|use_ixiy~combout ), + .combout(\z80_|execute_|fMWrite~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFAFA; -defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h5551; +defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( +// Location: LCCOMB_X40_Y13_N0 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( // Equation(s): -// \z80_|execute_|ctl_mRead~23_combout = (!\z80_|decode_state_|use_ixiy~combout & (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) +// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~23_combout ), + .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88C0; +defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( -// Equation(s): -// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMWrite~3_combout )) - - .dataa(\z80_|execute_|ctl_mRead~23_combout ), - .datab(\z80_|execute_|fMWrite~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( -// Equation(s): -// \z80_|execute_|fMRead~31_combout = (\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|pla_decode_|Equal33~3_combout ) # (\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( -// Equation(s): -// \z80_|execute_|fMRead~29_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((\z80_|ir_|opcode [6]) # (\z80_|ir_|opcode [7])))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC800; -defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( -// Equation(s): -// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~9_combout ) # ((\z80_|execute_|fMRead~29_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|fMRead~29_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( -// Equation(s): -// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|nextM~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( -// Equation(s): -// \z80_|execute_|fMRead~32_combout = ((\z80_|execute_|fMRead~31_combout ) # ((\z80_|execute_|fMRead~30_combout ) # (\z80_|execute_|fMRead~28_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .datab(\z80_|execute_|fMRead~31_combout ), - .datac(\z80_|execute_|fMRead~30_combout ), - .datad(\z80_|execute_|fMRead~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (\z80_|execute_|ctl_inc_cy~77_combout & \z80_|execute_|ctl_inc_cy~53_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datab(\z80_|execute_|ctl_inc_cy~77_combout ), - .datac(\z80_|execute_|ctl_inc_cy~53_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( -// Equation(s): -// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_mRead~23_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_ir_we~12_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~23_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( -// Equation(s): -// \z80_|execute_|fMRead~10_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0100; -defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( -// Equation(s): -// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|pc_inc_hold~28_combout )) - - .dataa(\z80_|execute_|ctl_mRead~23_combout ), - .datab(\z80_|execute_|pc_inc_hold~28_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|nextM~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~9 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( -// Equation(s): -// \z80_|execute_|fMRead~11_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|fMRead~9_combout )) # (!\z80_|execute_|fMRead~10_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|fMRead~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|fMRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hAAA2; -defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( -// Equation(s): -// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~12 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( -// Equation(s): -// \z80_|execute_|fMRead~13_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|fMRead~12_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|ctl_mRead~6_combout )))) - - .dataa(\z80_|execute_|fMRead~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|fMWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~13 .lut_mask = 16'h00FE; -defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( -// Equation(s): -// \z80_|execute_|fMRead~15_combout = (\z80_|execute_|fMRead~11_combout ) # ((\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|fMRead~14_combout ), - .datab(\z80_|execute_|fMRead~11_combout ), - .datac(\z80_|execute_|fMRead~13_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~15 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( -// Equation(s): -// \z80_|execute_|fMRead~20_combout = (((\z80_|execute_|fMRead~15_combout ) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|fMRead~19_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .datab(\z80_|execute_|fMRead~19_combout ), - .datac(\z80_|execute_|fMRead~15_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~20 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~48 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~48_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~48 .lut_mask = 16'hE0C0; -defparam \z80_|execute_|pc_inc_hold~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( -// Equation(s): -// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_mRead~17_combout & (\z80_|execute_|ctl_mRead~18_combout & -// ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( -// Equation(s): -// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|fMRead~2_combout ))) - - .dataa(\z80_|execute_|fMRead~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|fMRead~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~21 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( -// Equation(s): -// \z80_|execute_|fMRead~23_combout = ((\z80_|execute_|pc_inc_hold~48_combout ) # ((\z80_|execute_|fMRead~22_combout ) # (\z80_|execute_|fMRead~21_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|pc_inc_hold~48_combout ), - .datac(\z80_|execute_|fMRead~22_combout ), - .datad(\z80_|execute_|fMRead~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( -// Equation(s): -// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~26 .lut_mask = 16'hCCEC; -defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( -// Equation(s): -// \z80_|execute_|fMRead~25_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ctl_mRead~14_combout ))) # (!\z80_|execute_|fMRead~24_combout ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|fMRead~24_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~25 .lut_mask = 16'h2F0F; -defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( -// Equation(s): -// \z80_|execute_|fMRead~27_combout = ((\z80_|execute_|fMRead~25_combout ) # ((\z80_|execute_|fMRead~26_combout & \z80_|execute_|ctl_ir_we~4_combout ))) # (!\z80_|execute_|fMRead~3_combout ) - - .dataa(\z80_|execute_|fMRead~26_combout ), - .datab(\z80_|execute_|fMRead~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|fMRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~27 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( -// Equation(s): -// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~32_combout ) # ((\z80_|execute_|fMRead~20_combout ) # ((\z80_|execute_|fMRead~23_combout ) # (\z80_|execute_|fMRead~27_combout ))) - - .dataa(\z80_|execute_|fMRead~32_combout ), - .datab(\z80_|execute_|fMRead~20_combout ), - .datac(\z80_|execute_|fMRead~23_combout ), - .datad(\z80_|execute_|fMRead~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( -// Equation(s): -// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((\z80_|execute_|fMRead~34_combout & !\z80_|execute_|fMRead~0_combout ))) - - .dataa(\z80_|execute_|fMRead~34_combout ), - .datab(\z80_|execute_|fMRead~33_combout ), - .datac(\z80_|execute_|fMRead~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFFCE; -defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(gnd), - .datab(\z80_|execute_|fMRead~35_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFC0; -defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: M9K_X33_Y18_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N28 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .lut_mask = 16'hDC98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y19_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y20_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N16 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout )) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hEC64; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y24_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y32_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; -// synopsys translate_on - -// Location: M9K_X33_Y21_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; -// synopsys translate_on - -// Location: M9K_X33_Y22_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X32_Y18_N0 -cycloneive_lcell_comb \Selector1~0 ( -// Equation(s): -// \Selector1~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .cin(gnd), - .combout(\Selector1~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector1~0 .lut_mask = 16'hBA98; -defparam \Selector1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y18_N2 -cycloneive_lcell_comb \Selector1~1 ( -// Equation(s): -// \Selector1~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector1~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector1~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector1~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datad(\Selector1~0_combout ), - .cin(gnd), - .combout(\Selector1~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector1~1 .lut_mask = 16'hBBC0; -defparam \Selector1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y18_N12 -cycloneive_lcell_comb \D[1]~103 ( -// Equation(s): -// \D[1]~103_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Selector1~1_combout -// ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), - .datad(\Selector1~1_combout ), - .cin(gnd), - .combout(\D[1]~103_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~103 .lut_mask = 16'hF2D0; -defparam \D[1]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X18_Y34_N1 -cycloneive_io_ibuf \PS2_DAT~input ( - .i(PS2_DAT), - .ibar(gnd), - .o(\PS2_DAT~input_o )); -// synopsys translate_off -defparam \PS2_DAT~input .bus_hold = "false"; -defparam \PS2_DAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: CLKCTRL_G5 -cycloneive_clkctrl \reset~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\reset~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\reset~clkctrl_outclk )); -// synopsys translate_off -defparam \reset~clkctrl .clock_type = "global clock"; -defparam \reset~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [2])) # (!\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [0]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; -defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X9_Y34_N8 -cycloneive_io_ibuf \PS2_CLK~input ( - .i(PS2_CLK), - .ibar(gnd), - .o(\PS2_CLK~input_o )); -// synopsys translate_off -defparam \PS2_CLK~input .bus_hold = "false"; -defparam \PS2_CLK~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\PS2_CLK~input_o ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N1 -dffeas \ula_|ps2_keyboard_|clk_filter[7] ( +// Location: FF_X40_Y13_N1 +dffeas \z80_|sequencer_|DFFE_M4_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [7]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N7 -dffeas \ula_|ps2_keyboard_|clk_filter[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N20 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N21 -dffeas \ula_|ps2_keyboard_|clk_filter[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N18 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N19 -dffeas \ula_|ps2_keyboard_|clk_filter[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [6] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [5] & !\ula_|ps2_keyboard_|clk_filter [4]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [6]), - .datab(\ula_|ps2_keyboard_|clk_filter [7]), - .datac(\ula_|ps2_keyboard_|clk_filter [5]), - .datad(\ula_|ps2_keyboard_|clk_filter [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N3 -dffeas \ula_|ps2_keyboard_|clk_filter[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N29 -dffeas \ula_|ps2_keyboard_|clk_filter[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N23 -dffeas \ula_|ps2_keyboard_|clk_filter[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N16 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|clk_filter [2] & (!\ula_|ps2_keyboard_|clk_filter [1] & !\ula_|ps2_keyboard_|clk_filter [3]))) - - .dataa(\ula_|ps2_keyboard_|Equal0~0_combout ), - .datab(\ula_|ps2_keyboard_|clk_filter [2]), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0002; -defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N10 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N11 -dffeas \ula_|ps2_keyboard_|clk_filter[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFC30; -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N27 -dffeas \ula_|ps2_keyboard_|ps2_clk_in ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N4 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0C00; -defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N5 -dffeas \ula_|ps2_keyboard_|clk_edge ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_edge~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y21_N3 -dffeas \ula_|ps2_keyboard_|bit_count[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [2]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; -defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N1 -dffeas \ula_|ps2_keyboard_|bit_count[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N16 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [1] & -// (!\ula_|ps2_keyboard_|bit_count [2] & (\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [3]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h1810; -defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N17 -dffeas \ula_|ps2_keyboard_|bit_count[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [3] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [3] & -// ((\ula_|ps2_keyboard_|bit_count [1] $ (\ula_|ps2_keyboard_|bit_count [0])))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h0750; -defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N27 -dffeas \ula_|ps2_keyboard_|bit_count[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [3] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [2]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\PS2_DAT~input_o ), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|always1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [1]) # (\ula_|ps2_keyboard_|bit_count [2]))) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCCC0; -defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (\ula_|ps2_keyboard_|clk_edge~q & (!\ula_|ps2_keyboard_|LessThan0~0_combout & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) - - .dataa(\ula_|ps2_keyboard_|always1~0_combout ), - .datab(\ula_|ps2_keyboard_|bit_count [0]), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h00D0; -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N9 -dffeas \ula_|ps2_keyboard_|shiftreg[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\PS2_DAT~input_o ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N15 -dffeas \ula_|ps2_keyboard_|shiftreg[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [8]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N5 -dffeas \ula_|ps2_keyboard_|shiftreg[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [7]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N11 -dffeas \ula_|ps2_keyboard_|shiftreg[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [6]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N11 -dffeas \ula_|ps2_keyboard_|shiftreg[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [5]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N25 -dffeas \ula_|ps2_keyboard_|shiftreg[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [4]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N29 -dffeas \ula_|ps2_keyboard_|shiftreg[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [3]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N1 -dffeas \ula_|ps2_keyboard_|shiftreg[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [2]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N17 -dffeas \ula_|ps2_keyboard_|shiftreg[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [1]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|Equal0~0_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( -// Equation(s): -// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|extended~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hF300; -defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|shiftreg [8]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|WideXor0~0_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .datad(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hC33C; -defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|LessThan0~0_combout & (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|WideXor0~2_combout ))) - - .dataa(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .datab(\PS2_DAT~input_o ), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N9 -dffeas \ula_|ps2_keyboard_|scan_code_ready ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|scan_code_ready~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y20_N1 -dffeas \ula_|zx_keyboard_|extended ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|extended~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|extended~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|extended .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~15 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~15_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & !\ula_|ps2_keyboard_|shiftreg [7])) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~15 .lut_mask = 16'h0202; -defparam \ula_|zx_keyboard_|keys[0][0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[0][0]~15_combout )) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0500; -defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][1]~36_combout & \ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( -// Equation(s): -// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & -// (((\ula_|zx_keyboard_|released~q )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|released~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hC8F0; -defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N19 -dffeas \ula_|zx_keyboard_|released ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|released~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|released~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|released .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|zx_keyboard_|WideOr17~0_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(\ula_|zx_keyboard_|WideOr17~0_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # -// (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|shifted~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|zx_keyboard_|shifted~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y21_N3 -dffeas \ula_|zx_keyboard_|shifted ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|shifted~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|shifted~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|shifted .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hFF88; -defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~38_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'h0003; -defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~39_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[5][1]~38_combout & (!\ula_|zx_keyboard_|keys[5][1]~35_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~38_combout & -// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~35_combout ), - .datac(\ula_|zx_keyboard_|keys[5][1]~q ), - .datad(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N19 -dffeas \ula_|zx_keyboard_|keys[5][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~31 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~31_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~31 .lut_mask = 16'h00CC; -defparam \ula_|zx_keyboard_|keys[4][1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~23 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~23_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q )) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~23 .lut_mask = 16'h1010; -defparam \ula_|zx_keyboard_|keys[7][1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~32 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~32_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~32 .lut_mask = 16'h000C; -defparam \ula_|zx_keyboard_|keys[7][2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~33 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~33_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[7][2]~32_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~33 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[5][2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~34 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~34_combout = (\ula_|zx_keyboard_|keys[4][1]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[4][1]~q -// )))) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~34 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N9 -dffeas \ula_|zx_keyboard_|keys[4][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N24 -cycloneive_lcell_comb \D[1]~30 ( -// Equation(s): -// \D[1]~30_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][1]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~30 .lut_mask = 16'hBB0B; -defparam \D[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~24 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~24_combout = (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~24 .lut_mask = 16'hA0A0; -defparam \ula_|zx_keyboard_|keys[5][4]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~28_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~24_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~29 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~29_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~29 .lut_mask = 16'h00C0; -defparam \ula_|zx_keyboard_|keys[3][1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~30 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~30_combout = (\ula_|zx_keyboard_|keys[3][1]~28_combout & ((\ula_|zx_keyboard_|keys[3][1]~29_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[3][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~30 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N17 -dffeas \ula_|zx_keyboard_|keys[3][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~25 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~25 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[1][4]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~26 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~26_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & \ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~26 .lut_mask = 16'h4040; -defparam \ula_|zx_keyboard_|keys[2][1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~27 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~27_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # -// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][1]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~27 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[2][1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N17 -dffeas \ula_|zx_keyboard_|keys[2][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][1]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [10]), - .datad(\ula_|zx_keyboard_|keys[2][1]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hF3FF; -defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'hCCCF; -defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h0060; -defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~17 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~17_combout = (\ula_|zx_keyboard_|keys[0][1]~16_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [4])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~17 .lut_mask = 16'h2040; -defparam \ula_|zx_keyboard_|keys[0][1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~18 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~18_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~17_combout & (!\ula_|zx_keyboard_|keys[0][1]~14_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~17_combout & -// ((\ula_|zx_keyboard_|keys[0][1]~q ))))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .datac(\ula_|zx_keyboard_|keys[0][1]~q ), - .datad(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~18 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y21_N7 -dffeas \ula_|zx_keyboard_|keys[0][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~19 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|scan_code_ready~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~19 .lut_mask = 16'h0100; -defparam \ula_|zx_keyboard_|keys[7][4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~20 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~20_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~20 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[6][4]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~21 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~21_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~21 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[1][1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~22 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~22_combout = (\ula_|zx_keyboard_|keys[1][1]~21_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][1]~21_combout & (\ula_|zx_keyboard_|keys[1][1]~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[1][1]~21_combout ), - .datac(\ula_|zx_keyboard_|keys[1][1]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~22 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[1][1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N13 -dffeas \ula_|zx_keyboard_|keys[1][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N2 -cycloneive_lcell_comb \D[1]~28 ( -// Equation(s): -// \D[1]~28_combout = (\ula_|zx_keyboard_|keys[0][1]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) # (!\ula_|zx_keyboard_|keys[0][1]~q & -// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][1]~q ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\ula_|zx_keyboard_|keys[1][1]~q ), - .cin(gnd), - .combout(\D[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~28 .lut_mask = 16'hD0DD; -defparam \D[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N26 -cycloneive_lcell_comb \D[1]~29 ( -// Equation(s): -// \D[1]~29_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~28_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][1]~q ), - .datab(\ula_|zx_keyboard_|key_row~0_combout ), - .datac(\z80_|address_pins_|abus[11]~19_combout ), - .datad(\D[1]~28_combout ), - .cin(gnd), - .combout(\D[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~29 .lut_mask = 16'hC400; -defparam \D[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~41_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[0][0]~15_combout ))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h0240; -defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~43 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~43_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[6][1]~42_combout )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~43 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[6][1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'hEAEA; -defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~44 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~44_combout = (\ula_|zx_keyboard_|keys[6][1]~43_combout & ((!\ula_|zx_keyboard_|keys[6][1]~40_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~43_combout & (\ula_|zx_keyboard_|keys[6][1]~q )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\ula_|zx_keyboard_|keys[6][1]~40_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~44 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[6][1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N25 -dffeas \ula_|zx_keyboard_|keys[6][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~45 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~45_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [7]))) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [7]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~45 .lut_mask = 16'h0002; -defparam \ula_|zx_keyboard_|keys[7][1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & -// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h0A38; -defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h0044; -defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h0140; -defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~4_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & (!\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|WideOr16~4_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'hF022; -defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~7_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~5_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|WideOr16~5_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|WideOr16~7_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hF808; -defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~46 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~46_combout = (\ula_|zx_keyboard_|keys[7][1]~45_combout & ((\ula_|zx_keyboard_|WideOr16~6_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~6_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # -// (!\ula_|zx_keyboard_|keys[7][1]~45_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][1]~q ), - .datad(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~46 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N31 -dffeas \ula_|zx_keyboard_|keys[7][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N20 -cycloneive_lcell_comb \D[1]~31 ( -// Equation(s): -// \D[1]~31_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][1]~q & -// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[6][1]~q ), - .datac(\z80_|address_pins_|abus[15]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[7][1]~q ), - .cin(gnd), - .combout(\D[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~31 .lut_mask = 16'hB0BB; -defparam \D[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N18 -cycloneive_lcell_comb \D[1]~32 ( -// Equation(s): -// \D[1]~32_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~30_combout & (\D[1]~29_combout & \D[1]~31_combout ))) - - .dataa(\D[1]~30_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[1]~29_combout ), - .datad(\D[1]~31_combout ), - .cin(gnd), - .combout(\D[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~32 .lut_mask = 16'hECCC; -defparam \D[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N4 -cycloneive_lcell_comb \D[1]~33 ( -// Equation(s): -// \D[1]~33_combout = ((\Equal2~0_combout & ((\D[1]~32_combout ))) # (!\Equal2~0_combout & (\D[1]~103_combout ))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[1]~103_combout ), - .datad(\D[1]~32_combout ), - .cin(gnd), - .combout(\D[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~33 .lut_mask = 16'hFB73; -defparam \D[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N8 -cycloneive_lcell_comb \D[1]~34 ( -// Equation(s): -// \D[1]~34_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout & \z80_|data_pins_|dout [1])))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[1]~33_combout ), - .datad(\z80_|data_pins_|dout [1]), - .cin(gnd), - .combout(\D[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~34 .lut_mask = 16'hF151; -defparam \D[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N18 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[1]~11_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[1]~11_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\D[1]~34_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N19 -dffeas \z80_|data_pins_|dout[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N30 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( -// Equation(s): -// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N24 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~11 ( -// Equation(s): -// \z80_|bus_control_|db[1]~11_combout = ((\z80_|bus_control_|db[1]~10_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(\z80_|data_pins_|dout [1]), - .datac(\z80_|bus_control_|db[1]~10_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'hD0FF; -defparam \z80_|bus_control_|db[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N14 -cycloneive_lcell_comb \z80_|ir_|opcode[1]~feeder ( -// Equation(s): -// \z80_|ir_|opcode[1]~feeder_combout = \z80_|bus_control_|db[1]~11_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[1]~11_combout ), - .cin(gnd), - .combout(\z80_|ir_|opcode[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|ir_|opcode[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|ir_|opcode[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N15 -dffeas \z80_|ir_|opcode[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|ir_|opcode[1]~feeder_combout ), + .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0005; -defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hC080; -defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~3_combout = (\z80_|execute_|ctl_alu_op_low~28_combout & (\z80_|pla_decode_|Equal64~0_combout & ((\z80_|pla_decode_|Equal9~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|pla_decode_|Equal64~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|pla_decode_|Equal61~2_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h001F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & -// (((!\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'h153F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'h8000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h0088; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h4000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_flags_cf_cpl~2_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'h040C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout = (((!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .lut_mask = 16'h777F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'h0F0C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hC0E0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hAAA8; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_flags_nf_we~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & !\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ))) - - .dataa(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'h0008; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal62~2_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'h20A0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal21~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'hCECC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|execute_|ctl_alu_op_low~32_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFFEF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N24 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~20_combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ) - - .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'hFFB3; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout = (\z80_|execute_|ctl_state_alu~12_combout & ((\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|ir_|opcode [3] & ((!\z80_|ir_|opcode [5]))))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .lut_mask = 16'h8500; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~21_combout )) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hF0AA; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_control_|out[6]~2_combout )) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|out[6]~2_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hFA50; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout & ((!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout -// & ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h11D8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~3_combout & (\z80_|execute_|ctl_flags_cf2_sel_daa~combout $ ((!\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'h99F8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y9_N31 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .q(\z80_|sequencer_|DFFE_M4_ff~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; +defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( +// Location: LCCOMB_X37_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( // Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~10_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h0B00; -defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~14_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~11_combout ) # (((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout )) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout )) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ))) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hF0E4; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout & \z80_|execute_|ctl_alu_op_low~28_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .lut_mask = 16'hFEFA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~10_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_alu_op_low~12_combout ))) +// \z80_|execute_|fMWrite~2_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .lut_mask = 16'hFF40; -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~10_combout ) # ((\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~19_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~5_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_alu_op_low~12_combout ) # (\z80_|execute_|ctl_state_alu~7_combout )))) # (!\z80_|execute_|ctl_state_alu~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_state_alu~15_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_state_alu~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h3F3B; -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal68~2_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|pla_decode_|Equal68~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hAA20; -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFF32; -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_set~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_set~0_combout = (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~12_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_set~0 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_flags_cf_set~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hC0CC; -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~9_combout = (\z80_|execute_|ctl_flags_cf_cpl~8_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|execute_|ctl_flags_cf_set~0_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .datac(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N4 -cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( -// Equation(s): -// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~9_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_cf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0C48; -defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~8 ( -// Equation(s): -// \z80_|alu_control_|db[0]~8_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((\z80_|bus_control_|db[0]~17_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|bus_control_|db[0]~17_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~8 .lut_mask = 16'h22A2; -defparam \z80_|alu_control_|db[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N20 -cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( -// Equation(s): -// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~19_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_|db[0]~19_combout ), - .cin(gnd), - .combout(\z80_|sw2_|db_up[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hFF0F; -defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N4 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~9 ( -// Equation(s): -// \z80_|alu_control_|db[0]~9_combout = (\z80_|alu_control_|db[0]~8_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[0]~8_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|sw2_|db_up[0]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~9 .lut_mask = 16'h8A00; -defparam \z80_|alu_control_|db[0]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~12 ( -// Equation(s): -// \z80_|alu_control_|db[0]~12_combout = ((\z80_|alu_control_|db[0]~9_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|db[0]~9_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~12 .lut_mask = 16'hB0FF; -defparam \z80_|alu_control_|db[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~67 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~67_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~67 .lut_mask = 16'hFF50; -defparam \ula_|zx_keyboard_|keys[5][0]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~81 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~81_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~81_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~81 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[5][0]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~82 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~82_combout = (\ula_|zx_keyboard_|keys[5][0]~81_combout & (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~81_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~82 .lut_mask = 16'h2800; -defparam \ula_|zx_keyboard_|keys[5][0]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~83 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~83_combout = (\ula_|zx_keyboard_|keys[5][0]~82_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~82_combout & ((\ula_|zx_keyboard_|keys[5][0]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .datab(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .datac(\ula_|zx_keyboard_|keys[5][0]~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), .datad(gnd), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~83_combout ), + .combout(\z80_|execute_|fMWrite~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~83 .lut_mask = 16'h7474; -defparam \ula_|zx_keyboard_|keys[5][0]~83 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h2F2F; +defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y20_N11 -dffeas \ula_|zx_keyboard_|keys[5][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][0]~83_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~84 ( +// Location: LCCOMB_X38_Y11_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~84_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [3])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~84_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~84 .lut_mask = 16'h0160; -defparam \ula_|zx_keyboard_|keys[4][0]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~85 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~85_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~85 .lut_mask = 16'hBABA; -defparam \ula_|zx_keyboard_|keys[4][0]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~86 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~86_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[4][0]~84_combout & ((!\ula_|zx_keyboard_|keys[4][0]~85_combout ))) # (!\ula_|zx_keyboard_|keys[4][0]~84_combout & -// (\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datab(\ula_|zx_keyboard_|keys[4][0]~84_combout ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~86 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][0]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N27 -dffeas \ula_|zx_keyboard_|keys[4][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N20 -cycloneive_lcell_comb \D[0]~49 ( -// Equation(s): -// \D[0]~49_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][0]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][0]~q ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[0]~49_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~49 .lut_mask = 16'hBB0B; -defparam \D[0]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [5] & ((\ula_|ps2_keyboard_|shiftreg [6])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & -// (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'h8810; -defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~76 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~76_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout )) # (!\ula_|zx_keyboard_|WideOr4~0_combout ))) - - .dataa(\ula_|zx_keyboard_|WideOr4~0_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~76_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~76 .lut_mask = 16'h3313; -defparam \ula_|zx_keyboard_|keys~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~73 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~73_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~73_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~73 .lut_mask = 16'hF000; -defparam \ula_|zx_keyboard_|keys[4][3]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~47 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~47_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~47 .lut_mask = 16'h0808; -defparam \ula_|zx_keyboard_|keys[6][4]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// ((\ula_|ps2_keyboard_|shiftreg [2]))))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0310; -defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~74 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~74_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~74_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~74 .lut_mask = 16'h353F; -defparam \ula_|zx_keyboard_|keys~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~75 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~75_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][3]~73_combout & !\ula_|zx_keyboard_|keys~74_combout )) # (!\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~73_combout ), - .datab(\ula_|zx_keyboard_|keys~74_combout ), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~75_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~75 .lut_mask = 16'h2F00; -defparam \ula_|zx_keyboard_|keys[0][0]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~77 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~77_combout = (\ula_|zx_keyboard_|keys~76_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) # (!\ula_|zx_keyboard_|keys~76_combout & ((\ula_|zx_keyboard_|keys[0][0]~75_combout & ((!\ula_|zx_keyboard_|released~q ))) # -// (!\ula_|zx_keyboard_|keys[0][0]~75_combout & (\ula_|zx_keyboard_|keys[0][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys~76_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~75_combout ), - .datac(\ula_|zx_keyboard_|keys[0][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~77_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~77 .lut_mask = 16'hB0F4; -defparam \ula_|zx_keyboard_|keys[0][0]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N15 -dffeas \ula_|zx_keyboard_|keys[0][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][0]~77_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~71 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~71_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~71_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~71 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[1][0]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~72 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~72_combout = (\ula_|zx_keyboard_|keys[1][0]~71_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][0]~71_combout & (\ula_|zx_keyboard_|keys[1][0]~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[1][0]~71_combout ), - .datac(\ula_|zx_keyboard_|keys[1][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~72 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[1][0]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N17 -dffeas \ula_|zx_keyboard_|keys[1][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N30 -cycloneive_lcell_comb \D[0]~47 ( -// Equation(s): -// \D[0]~47_combout = (\ula_|zx_keyboard_|keys[0][0]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~q & -// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~q ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\ula_|zx_keyboard_|keys[1][0]~q ), - .cin(gnd), - .combout(\D[0]~47_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~47 .lut_mask = 16'hD0DD; -defparam \D[0]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~80 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][0]~80_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # -// (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][0]~80_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0]~80 .lut_mask = 16'hB1F0; -defparam \ula_|zx_keyboard_|keys[2][0]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N23 -dffeas \ula_|zx_keyboard_|keys[2][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][0]~80_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~78 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~78 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|keys[3][0]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~79 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~79_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & ((\ula_|zx_keyboard_|keys[3][1]~28_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (\ula_|zx_keyboard_|keys[3][0]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][0]~78_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~79 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[3][0]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N5 -dffeas \ula_|zx_keyboard_|keys[3][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~1_combout = ((\z80_|address_pins_|DFFE_apin_latch [11]) # (!\ula_|zx_keyboard_|keys[3][0]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [11]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hFF3F; -defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N4 -cycloneive_lcell_comb \D[0]~48 ( -// Equation(s): -// \D[0]~48_combout = (\D[0]~47_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][0]~q )))) - - .dataa(\D[0]~47_combout ), - .datab(\z80_|address_pins_|abus[10]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|key_row~1_combout ), - .cin(gnd), - .combout(\D[0]~48_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~48 .lut_mask = 16'h8A00; -defparam \D[0]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~91 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~91_combout = (\ula_|zx_keyboard_|shifted~1_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[6][0]~90_combout & \ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|shifted~1_combout ), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[6][0]~90_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~91 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[6][0]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~92 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~92_combout = (\ula_|zx_keyboard_|keys[6][0]~91_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][0]~91_combout & ((\ula_|zx_keyboard_|keys[6][0]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][0]~q ), - .datad(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~92 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[6][0]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N21 -dffeas \ula_|zx_keyboard_|keys[6][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~63 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~63_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~63 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[5][4]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h0303; -defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[5][4]~63_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|WideOr16~3_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~132 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~132_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~132_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~132 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[7][0]~132 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~88 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~88_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & ((\ula_|zx_keyboard_|keys[7][0]~87_combout ) # (\ula_|zx_keyboard_|keys[7][0]~132_combout )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .datad(\ula_|zx_keyboard_|keys[7][0]~132_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~88 .lut_mask = 16'h8880; -defparam \ula_|zx_keyboard_|keys[7][0]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~89 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~89_combout = (\ula_|zx_keyboard_|keys[7][0]~88_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][0]~88_combout & (\ula_|zx_keyboard_|keys[7][0]~q )) - - .dataa(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~89 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[7][0]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N7 -dffeas \ula_|zx_keyboard_|keys[7][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N28 -cycloneive_lcell_comb \D[0]~50 ( -// Equation(s): -// \D[0]~50_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][0]~q & -// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[6][0]~q ), - .datac(\z80_|address_pins_|abus[15]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[7][0]~q ), - .cin(gnd), - .combout(\D[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~50 .lut_mask = 16'hB0BB; -defparam \D[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N10 -cycloneive_lcell_comb \D[0]~51 ( -// Equation(s): -// \D[0]~51_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~49_combout & (\D[0]~48_combout & \D[0]~50_combout ))) - - .dataa(\D[0]~49_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[0]~48_combout ), - .datad(\D[0]~50_combout ), - .cin(gnd), - .combout(\D[0]~51_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~51 .lut_mask = 16'hECCC; -defparam \D[0]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y16_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N14 -cycloneive_lcell_comb \D[0]~55 ( -// Equation(s): -// \D[0]~55_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\D[0]~55_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~55 .lut_mask = 16'hE3E0; -defparam \D[0]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N22 -cycloneive_lcell_comb \D[0]~56 ( -// Equation(s): -// \D[0]~56_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~55_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout )) # (!\D[0]~55_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~55_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[0]~55_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .cin(gnd), - .combout(\D[0]~56_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~56 .lut_mask = 16'hBCB0; -defparam \D[0]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y28_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X22_Y30_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; -// synopsys translate_on - -// Location: M9K_X22_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N4 -cycloneive_lcell_comb \D[0]~52 ( -// Equation(s): -// \D[0]~52_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\z80_|address_pins_|abus[14]~23_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .cin(gnd), - .combout(\D[0]~52_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~52 .lut_mask = 16'hF858; -defparam \D[0]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y20_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N28 -cycloneive_lcell_comb \D[0]~53 ( -// Equation(s): -// \D[0]~53_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout $ ((\D[0]~52_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & (((!\D[0]~52_combout & -// \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datab(\z80_|address_pins_|abus[15]~22_combout ), - .datac(\D[0]~52_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\D[0]~53_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~53 .lut_mask = 16'h4B48; -defparam \D[0]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N16 -cycloneive_lcell_comb \D[0]~54 ( -// Equation(s): -// \D[0]~54_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~52_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~52_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & !\D[0]~53_combout )) # (!\D[0]~52_combout & ((\D[0]~53_combout ))))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[0]~52_combout ), - .datad(\D[0]~53_combout ), - .cin(gnd), - .combout(\D[0]~54_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~54 .lut_mask = 16'hC3E0; -defparam \D[0]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N8 -cycloneive_lcell_comb \D[0]~106 ( -// Equation(s): -// \D[0]~106_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[0]~56_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[0]~54_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[0]~56_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[0]~56_combout ), - .datad(\D[0]~54_combout ), - .cin(gnd), - .combout(\D[0]~106_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~106 .lut_mask = 16'hF4B0; -defparam \D[0]~106 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N14 -cycloneive_lcell_comb \D[0]~57 ( -// Equation(s): -// \D[0]~57_combout = ((\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout )))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~1_combout ), - .datab(\D[0]~51_combout ), - .datac(\D[0]~106_combout ), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[0]~57_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~57 .lut_mask = 16'hDDF5; -defparam \D[0]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N0 -cycloneive_lcell_comb \D[0]~58 ( -// Equation(s): -// \D[0]~58_combout = (\D[0]~57_combout & (((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[0]~57_combout & (!\Equal2~1_combout & ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [0]), - .datac(\D[0]~57_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[0]~58_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~58 .lut_mask = 16'hC0F5; -defparam \D[0]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N0 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[0]~17_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[0]~17_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\D[0]~58_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N1 -dffeas \z80_|data_pins_|dout[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N4 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( -// Equation(s): -// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(\z80_|data_pins_|dout [0]), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'hC0CC; -defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( -// Equation(s): -// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|alu_control_|db[0]~12_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~16_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'hDF55; -defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y13_N27 -dffeas \z80_|ir_|opcode[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[0]~17_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) +// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2])) .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), .cin(gnd), - .combout(\z80_|pla_decode_|Equal63~0_combout ), + .combout(\z80_|pla_decode_|Equal13~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; +defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( +// Location: LCCOMB_X38_Y11_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( // Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) +// \z80_|pla_decode_|Equal13~2_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .combout(\z80_|pla_decode_|Equal13~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N20 -cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( +// Location: LCCOMB_X36_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( // Equation(s): -// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h070F; -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( -// Equation(s): -// \z80_|alu_control_|db[6]~10_combout = ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|execute_|ctl_flags_oe~2_combout )) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) - - .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|execute_|ctl_flags_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hFFF5; -defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( -// Equation(s): -// \z80_|alu_control_|db[6]~11_combout = (\z80_|alu_control_|db[6]~10_combout ) # ((\z80_|execute_|ctl_sw_1d~7_combout ) # (\z80_|execute_|ctl_reg_out_lo~8_combout )) - - .dataa(\z80_|alu_control_|db[6]~10_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFEFE; -defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( -// Equation(s): -// \z80_|alu_control_|db[4]~30_combout = (\z80_|alu_|db[4]~17_combout & (\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|reg_file_|gdfx_temp0[4]~62_combout ))) # (!\z80_|alu_|db[4]~17_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((\z80_|execute_|ctl_reg_out_lo~8_combout & !\z80_|reg_file_|gdfx_temp0[4]~62_combout )))) - - .dataa(\z80_|alu_|db[4]~17_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h5D0C; -defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( -// Equation(s): -// \z80_|alu_control_|db[4]~31_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[4]~30_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_flags_|flags_hf~combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_control_|db[4]~30_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h00B0; -defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( -// Equation(s): -// \z80_|alu_control_|db[4]~32_combout = ((\z80_|alu_control_|db[4]~31_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|alu_control_|db[4]~31_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'hBF33; -defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~119 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~119_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & -// (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~119_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~119 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[2][4]~119 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~120 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~120_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][4]~119_combout & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|zx_keyboard_|keys[2][4]~119_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~120_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~120 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[2][4]~120 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~95 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~95_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~95_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~95 .lut_mask = 16'hAFAA; -defparam \ula_|zx_keyboard_|keys[2][4]~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~121 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~121_combout = (\ula_|zx_keyboard_|keys[2][4]~120_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[2][4]~120_combout & (\ula_|zx_keyboard_|keys[2][4]~q )) - - .dataa(\ula_|zx_keyboard_|keys[2][4]~120_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~121_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~121 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[2][4]~121 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N23 -dffeas \ula_|zx_keyboard_|keys[2][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][4]~121_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~117 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~117_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~117_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~117 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|keys[3][4]~117 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~136 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~136_combout = (\ula_|zx_keyboard_|keys[3][4]~117_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[3][4]~117_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~136_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~136 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[3][4]~136 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~130 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~130_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~130_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~130 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[3][4]~130 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~118 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~118_combout = (\ula_|zx_keyboard_|keys[3][4]~136_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[3][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~136_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][4]~136_combout ), - .datac(\ula_|zx_keyboard_|keys[3][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~118 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][4]~118 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N9 -dffeas \ula_|zx_keyboard_|keys[3][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N18 -cycloneive_lcell_comb \D[4]~78 ( -// Equation(s): -// \D[4]~78_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # ((!\ula_|zx_keyboard_|keys[2][4]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][4]~q & -// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\z80_|address_pins_|abus[10]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~q ), - .cin(gnd), - .combout(\D[4]~78_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~78 .lut_mask = 16'h8ACF; -defparam \D[4]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~126 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~126_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~126 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[6][4]~126 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~128 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~128_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~128_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~128 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[5][4]~128 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~129 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~129_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[5][4]~128_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~128_combout & -// (\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~128_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~129_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~129 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][4]~129 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y19_N9 -dffeas \ula_|zx_keyboard_|keys[5][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][4]~129_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~127 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~127_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~20_combout & ((\ula_|zx_keyboard_|keys[6][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~127_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~127 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[6][4]~127 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N5 -dffeas \ula_|zx_keyboard_|keys[6][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][4]~127_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~51 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~51_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~51 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[7][4]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~125 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~125_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~51_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) -// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~1_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~125_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~125 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][4]~125 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N11 -dffeas \ula_|zx_keyboard_|keys[7][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][4]~125_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N30 -cycloneive_lcell_comb \D[4]~79 ( -// Equation(s): -// \D[4]~79_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\z80_|address_pins_|abus[14]~23_combout ) # ((!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][4]~q & -// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\z80_|address_pins_|abus[14]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~q ), - .cin(gnd), - .combout(\D[4]~79_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~79 .lut_mask = 16'h8ACF; -defparam \D[4]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~122 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q )) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & -// \ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~122 .lut_mask = 16'h4422; -defparam \ula_|zx_keyboard_|keys[4][4]~122 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~123 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~123_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][4]~122_combout ))) - - .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~123 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][4]~123 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & ((\ula_|zx_keyboard_|keys[4][4]~123_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~123_combout & ((\ula_|zx_keyboard_|keys[4][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[4][4]~q ), - .datad(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N25 -dffeas \ula_|zx_keyboard_|keys[4][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\ula_|zx_keyboard_|keys[4][4]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|execute_|ixy_d~4_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_T3_ff~q )) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [12]), - .datad(\ula_|zx_keyboard_|keys[4][4]~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~3_combout ), + .combout(\z80_|execute_|ixy_d~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hF3FF; -defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h000C; +defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y19_N8 -cycloneive_lcell_comb \D[4]~80 ( +// Location: LCCOMB_X38_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( // Equation(s): -// \D[4]~80_combout = (\D[4]~79_combout & (\ula_|zx_keyboard_|key_row~3_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) +// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) - .dataa(\ula_|zx_keyboard_|keys[5][4]~q ), - .datab(\D[4]~79_combout ), - .datac(\z80_|address_pins_|abus[13]~20_combout ), - .datad(\ula_|zx_keyboard_|key_row~3_combout ), - .cin(gnd), - .combout(\D[4]~80_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~80 .lut_mask = 16'hC400; -defparam \D[4]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~111 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~111_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|zx_keyboard_|released~q ), + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), .datab(gnd), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~111_combout ), + .combout(\z80_|execute_|fIOWrite~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~111 .lut_mask = 16'hFAAA; -defparam \ula_|zx_keyboard_|keys[0][4]~111 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hAA0A; +defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~97 ( +// Location: LCCOMB_X38_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~97_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~97 .lut_mask = 16'h0060; -defparam \ula_|zx_keyboard_|keys[0][4]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~116 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~116_combout = (\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & (!\ula_|zx_keyboard_|keys[0][4]~111_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & -// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~116_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~116 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][4]~116 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N11 -dffeas \ula_|zx_keyboard_|keys[0][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][4]~116_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~115 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~115_combout = (\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[1][4]~q )))) # -// (!\ula_|zx_keyboard_|Equal0~2_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) - - .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[1][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~115_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~115 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][4]~115 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N7 -dffeas \ula_|zx_keyboard_|keys[1][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][4]~115_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N28 -cycloneive_lcell_comb \D[4]~77 ( -// Equation(s): -// \D[4]~77_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][4]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][4]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[1][4]~q ), - .cin(gnd), - .combout(\D[4]~77_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~77 .lut_mask = 16'h8ACF; -defparam \D[4]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N26 -cycloneive_lcell_comb \D[4]~81 ( -// Equation(s): -// \D[4]~81_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~78_combout & (\D[4]~80_combout & \D[4]~77_combout ))) - - .dataa(\z80_|address_pins_|abus[0]~16_combout ), - .datab(\D[4]~78_combout ), - .datac(\D[4]~80_combout ), - .datad(\D[4]~77_combout ), - .cin(gnd), - .combout(\D[4]~81_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~81 .lut_mask = 16'hEAAA; -defparam \D[4]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y1_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; -// synopsys translate_on - -// Location: M9K_X22_Y22_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y3_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; -// synopsys translate_on - -// Location: M9K_X22_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N2 -cycloneive_lcell_comb \Selector4~0 ( -// Equation(s): -// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .cin(gnd), - .combout(\Selector4~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector4~0 .lut_mask = 16'hBA98; -defparam \Selector4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N26 -cycloneive_lcell_comb \Selector4~1 ( -// Equation(s): -// \Selector4~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector4~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # (!\Selector4~0_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector4~0_combout )))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datad(\Selector4~0_combout ), - .cin(gnd), - .combout(\Selector4~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector4~1 .lut_mask = 16'hF388; -defparam \Selector4~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y16_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y3_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N20 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .lut_mask = 16'hE5E0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N10 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .lut_mask = 16'hAFC0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N6 -cycloneive_lcell_comb \D[4]~109 ( -// Equation(s): -// \D[4]~109_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\Selector4~1_combout -// )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ))))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\Selector4~1_combout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), - .cin(gnd), - .combout(\D[4]~109_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~109 .lut_mask = 16'hFB40; -defparam \D[4]~109 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N18 -cycloneive_lcell_comb \D[4]~97 ( -// Equation(s): -// \D[4]~97_combout = ((\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout )))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\D[4]~81_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[4]~109_combout ), - .cin(gnd), - .combout(\D[4]~97_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~97 .lut_mask = 16'hDF8F; -defparam \D[4]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N30 -cycloneive_lcell_comb \D[4]~98 ( -// Equation(s): -// \D[4]~98_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [4] & ((\D[4]~97_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[4]~97_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[4]~97_combout ), - .cin(gnd), - .combout(\D[4]~98_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~98 .lut_mask = 16'hBB03; -defparam \D[4]~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N24 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[4]~19_combout ) # ((\D[4]~98_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[4]~98_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[4]~98_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N25 -dffeas \z80_|data_pins_|dout[4] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N20 -cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( -// Equation(s): -// \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[4]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'h88CC; -defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N18 -cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( -// Equation(s): -// \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[4]~18_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hDF55; -defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N19 -dffeas \z80_|ir_|opcode[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[4]~19_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~0_combout = (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) +// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) .dataa(gnd), .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~0_combout ), + .combout(\z80_|execute_|ctl_mWrite~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( +// Location: LCCOMB_X34_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( // Equation(s): -// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) +// \z80_|execute_|fMRead~2_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~5_combout ), + .combout(\z80_|execute_|fMRead~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h3F0F; +defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N22 +// Location: LCCOMB_X34_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~2_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~2 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_state_alu~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~11_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N2 cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( // Equation(s): -// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|fMRead~0_combout )))) +// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|fMRead~2_combout )))) - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), - .datad(\z80_|execute_|fMRead~0_combout ), + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|fMRead~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), .cin(gnd), .combout(\z80_|execute_|fIOWrite~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hFB00; defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( +// Location: LCCOMB_X39_Y7_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( // Equation(s): -// \z80_|execute_|fIOWrite~3_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) +// \z80_|pla_decode_|Equal2~0_combout = (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h00CC; +defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N2 +cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( +// Equation(s): +// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instCB~q ) # (\z80_|decode_state_|DFFE_instED~q ) + + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|decode_state_|table_xx~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; +defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|table_xx~0_combout & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~0_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~3 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~3_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~3 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( +// Equation(s): +// \z80_|execute_|fIOWrite~3_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), .cin(gnd), .combout(\z80_|execute_|fIOWrite~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3F0F; +defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3B3B; defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y18_N2 +// Location: LCCOMB_X39_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( +// Equation(s): +// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N16 cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( // Equation(s): -// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) +// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|fIOWrite~3_combout ), + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|fIOWrite~3_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), .cin(gnd), .combout(\z80_|execute_|fIOWrite~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hA8AA; +defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hCC8C; defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N4 +// Location: LCCOMB_X38_Y13_N4 cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( // Equation(s): -// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~5_combout ))) +// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~3_combout ))) .dataa(\z80_|execute_|fIOWrite~1_combout ), - .datab(\z80_|execute_|ctl_mRead~5_combout ), - .datac(\z80_|execute_|fIOWrite~2_combout ), + .datab(\z80_|execute_|fIOWrite~2_combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), .datad(\z80_|execute_|fIOWrite~4_combout ), .cin(gnd), .combout(\z80_|execute_|fIOWrite~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFFEC; defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( +// Location: LCCOMB_X37_Y8_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~11_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) +// \z80_|pin_control_|bus_db_pin_oe~4_combout = (!\z80_|execute_|fIOWrite~5_combout & ((\z80_|execute_|fMWrite~2_combout ) # ((\z80_|execute_|fMWrite~3_combout & !\z80_|pla_decode_|Equal13~2_combout )))) - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mWrite~10_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .dataa(\z80_|execute_|fMWrite~3_combout ), + .datab(\z80_|execute_|fMWrite~2_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|fIOWrite~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~11_combout ), + .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; +defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'h00CE; +defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( +// Location: LCCOMB_X40_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~3 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~12_combout = (\z80_|execute_|ctl_mWrite~8_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) +// \z80_|execute_|ctl_state_alu~3_combout = (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~3 .lut_mask = 16'h0C0C; +defparam \z80_|execute_|ctl_state_alu~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~1_combout = (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h3300; +defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~6_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~4_combout = (\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; +defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0100; +defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~46_combout = ((!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|execute_|ctl_mWrite~6_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~46_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2u~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal19~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal34~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h0400; +defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|comb~0 ( +// Equation(s): +// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|comb~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~0 .lut_mask = 16'hCC00; +defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal47~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|execute_|comb~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~45_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & +// (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (\z80_|execute_|ctl_inc_cy~45_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal19~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_inc_cy~45_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N10 +cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( +// Equation(s): +// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|M5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88C0; +defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N11 +dffeas \z80_|sequencer_|M5 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|M5~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|M5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|M5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( +// Equation(s): +// \z80_|execute_|ixy_d~7_combout = (\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h00AA; +defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~44_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ctl_alu_oe~2_combout & +// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_inc_cy~44_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|ctl_inc_cy~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q )) + + .dataa(gnd), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0300; +defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~14_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~7_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N24 +cycloneive_lcell_comb \z80_|execute_|fMWrite~0 ( +// Equation(s): +// \z80_|execute_|fMWrite~0_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~0 .lut_mask = 16'h0001; +defparam \z80_|execute_|fMWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~97 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~97_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~97_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~97 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~96 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~96_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal19~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~96_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~96 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~98 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~98_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~98_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~98 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~98_combout & (((!\z80_|execute_|ctl_alu_op_low~14_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_inc_cy~98_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_inc_cy~97_combout & (\z80_|execute_|ctl_inc_cy~96_combout & \z80_|execute_|ctl_inc_cy~48_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~97_combout ), + .datab(\z80_|execute_|ctl_inc_cy~96_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_cy~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|fMWrite~1 ( +// Equation(s): +// \z80_|execute_|fMWrite~1_combout = (\z80_|sequencer_|M5~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|sequencer_|M5~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # +// (\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~1 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMWrite~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N18 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|execute_|ctl_bus_inc_oe~28_combout & ((\z80_|execute_|fMWrite~0_combout ) # (!\z80_|execute_|fMWrite~1_combout ))) + + .dataa(\z80_|execute_|fMWrite~0_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .datac(gnd), + .datad(\z80_|execute_|fMWrite~1_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'h88CC; +defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N4 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|execute_|ctl_inc_cy~47_combout & (\z80_|execute_|ctl_apin_mux~0_combout & \z80_|pin_control_|bus_db_pin_oe~3_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .datab(\z80_|execute_|ctl_inc_cy~47_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~6_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|execute_|ctl_mRead~6_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h153F; +defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~7_combout = (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N22 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|pin_control_|bus_db_pin_oe~6_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((!\z80_|execute_|ctl_mWrite~7_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'hB0F0; +defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~17 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~17_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~17 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_mWrite~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( +// Equation(s): +// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|ctl_mWrite~17_combout & (!\z80_|execute_|ctl_mWrite~6_combout & !\z80_|execute_|ctl_mRead~5_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_mWrite~11_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~12_combout ), + .combout(\z80_|execute_|fMWrite~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h0003; +defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( +// Location: LCCOMB_X37_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~9_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) +// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - .dataa(\z80_|execute_|ctl_mWrite~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datac(\z80_|execute_|ctl_mWrite~9_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~13_combout ), + .combout(\z80_|execute_|ctl_state_alu~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( +// Location: LCCOMB_X39_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) +// \z80_|execute_|ctl_inc_cy~49_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout +// & (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~14_combout ), + .combout(\z80_|execute_|ctl_inc_cy~49_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N28 +// Location: LCCOMB_X36_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~49_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~49_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~4_combout ) # ((!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|fMWrite~4_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_inc_dec~2_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'hCD00; +defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( +// Equation(s): +// \z80_|execute_|fMWrite~8_combout = (\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ctl_alu_oe~2_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (\z80_|execute_|ctl_mRead~8_combout & +// ((\z80_|execute_|ctl_alu_oe~2_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~51 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~51_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~51 .lut_mask = 16'hABFF; +defparam \z80_|execute_|ctl_bus_inc_oe~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|M5~q )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~15_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hABFF; +defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal46~0_combout = (\z80_|ir_|opcode [2] & (\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [0] & \z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal46~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~10_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~45_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'hF3F7; +defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [7]), + .datac(gnd), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0033; +defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|decode_state_|DFFE_instCB~q )))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~29_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout ))) # (!\z80_|execute_|ctl_alu_oe~2_combout & (((!\z80_|execute_|ixy_d~7_combout )) # +// (!\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h1357; +defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|ctl_alu_core_S~10_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & \z80_|execute_|ctl_bus_inc_oe~29_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_S~10_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal55~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0044; +defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout )) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~7_combout & ((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & +// (((!\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ctl_bus_inc_oe~51_combout & (\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|execute_|ctl_bus_inc_oe~31_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~51_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N6 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~17 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~17_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~17 .lut_mask = 16'h1333; +defparam \z80_|pin_control_|bus_db_pin_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( +// Equation(s): +// \z80_|execute_|fIOWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h3733; +defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N0 +cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( +// Equation(s): +// \z80_|execute_|fMWrite~6_combout = ((\z80_|pla_decode_|Equal46~0_combout ) # ((!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) # (!\z80_|execute_|ctl_ir_we~5_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'hF7F5; +defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( +// Equation(s): +// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h3737; +defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N0 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|execute_|fIOWrite~0_combout & ((\z80_|execute_|fMWrite~6_combout ) # ((\z80_|execute_|fMWrite~5_combout )))) # (!\z80_|execute_|fIOWrite~0_combout & (!\z80_|execute_|ctl_mWrite~8_combout & +// ((\z80_|execute_|fMWrite~6_combout ) # (\z80_|execute_|fMWrite~5_combout )))) + + .dataa(\z80_|execute_|fIOWrite~0_combout ), + .datab(\z80_|execute_|fMWrite~6_combout ), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|execute_|fMWrite~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'hAF8C; +defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( +// Equation(s): +// \z80_|execute_|fMRead~3_combout = ((!\z80_|execute_|ctl_ir_we~5_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|ir_|opcode [7]) + + .dataa(\z80_|ir_|opcode [7]), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~4_combout & \z80_|execute_|fMRead~3_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~4_combout )) # +// (!\z80_|execute_|ctl_alu_oe~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|fMRead~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h1F15; +defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N24 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~8_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & +// (((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~5_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h0777; +defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N6 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~17_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~10_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~17_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|execute_|comb~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'h0313; +defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_reg_sel_wz~6_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|M5~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout = (\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~8_combout & +// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .lut_mask = 16'h0537; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( +// Equation(s): +// \z80_|execute_|fMWrite~7_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # (\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|pin_control_|bus_db_pin_oe~12_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & !\z80_|execute_|fMWrite~7_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .datad(\z80_|execute_|fMWrite~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h0080; +defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N2 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (!\z80_|execute_|fMWrite~8_combout & (\z80_|execute_|ctl_bus_inc_oe~32_combout & \z80_|pin_control_|bus_db_pin_oe~13_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .datab(\z80_|execute_|fMWrite~8_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'h2000; +defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~15 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~15_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout & (\z80_|pin_control_|bus_db_pin_oe~5_combout & (\z80_|pin_control_|bus_db_pin_oe~7_combout & \z80_|pin_control_|bus_db_pin_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~15 .lut_mask = 16'h4000; +defparam \z80_|pin_control_|bus_db_pin_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N8 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'hFCFC; +defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~16 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~16_combout = (\z80_|sequencer_|DFFE_T4_ff~q & ((\z80_|execute_|fIOWrite~5_combout ) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout & \z80_|pin_control_|bus_db_pin_oe~2_combout )))) # (!\z80_|sequencer_|DFFE_T4_ff~q & +// (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (\z80_|pin_control_|bus_db_pin_oe~2_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .datad(\z80_|execute_|fIOWrite~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~16 .lut_mask = 16'hBA30; +defparam \z80_|pin_control_|bus_db_pin_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|nextM~4 ( +// Equation(s): +// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout ) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~4 .lut_mask = 16'h373F; +defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( +// Equation(s): +// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_eval_cond~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h0A0A; +defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~12_combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_iorw~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|ctl_mWrite~17_combout ))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|nextM~4_combout ), + .datad(\z80_|execute_|ctl_iorw~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y11_N21 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_iorw~9_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y11_N17 +dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N14 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorq~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_iorq~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_iorq~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y11_N15 +dffeas \z80_|memory_ifc_|wait_iorq ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorq~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y11_N23 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorq~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N22 +cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( +// Equation(s): +// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) + + .dataa(gnd), + .datab(\z80_|memory_ifc_|wait_iorq~q ), + .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|iorq~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; +defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'hA000; +defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( +// Equation(s): +// \z80_|execute_|ixy_d~17_combout = (\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|decode_state_|DFFE_instIY1~q & !\z80_|decode_state_|DFFE_inst4~q )))) # (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|decode_state_|DFFE_instIY1~q & +// !\z80_|decode_state_|DFFE_inst4~q )) # (!\z80_|pla_decode_|Equal50~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~2_combout ), + .datab(\z80_|pla_decode_|Equal50~0_combout ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h111F; +defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N14 cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~15_combout = ((\z80_|execute_|ctl_mWrite~14_combout ) # ((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout ))) # (!\z80_|execute_|ctl_mWrite~13_combout ) +// \z80_|execute_|ctl_mWrite~15_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~7_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|execute_|ctl_mWrite~7_combout ))) - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|execute_|ctl_mWrite~13_combout ), - .datac(\z80_|execute_|ctl_mWrite~14_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_mWrite~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hF7F3; +defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hEAC0; defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N29 +// Location: LCCOMB_X34_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~18 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~18_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal11~0_combout & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~18 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_mWrite~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~12_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~21 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~21_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~21 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_flags_alu~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~20 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~20_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~20 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~10_combout = (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~10_combout = (\z80_|execute_|ctl_flags_alu~21_combout & (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & \z80_|execute_|ctl_flags_alu~10_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~21_combout ), + .datab(\z80_|execute_|ctl_flags_alu~20_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_mWrite~10_combout & ((!\z80_|execute_|ctl_mWrite~8_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~12_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|execute_|ctl_mWrite~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( +// Equation(s): +// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~9_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~12_combout = (\z80_|execute_|ctl_inc_cy~51_combout & (((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|execute_|ctl_inc_cy~51_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (\z80_|execute_|ctl_inc_dec~12_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_inc_dec~2_combout ), + .datac(\z80_|execute_|ctl_inc_dec~12_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~11_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~25_combout = (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~22 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~22_combout = (((!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~22 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_flags_alu~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~24_combout = (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~22_combout & (((!\z80_|execute_|ctl_mRead~25_combout & !\z80_|execute_|ctl_mRead~24_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~25_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ctl_flags_alu~22_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_mWrite~13_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~11_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~11_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( +// Equation(s): +// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|execute_|ctl_mWrite~15_combout ) # (((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout )) # (!\z80_|execute_|ctl_mWrite~14_combout )) + + .dataa(\z80_|execute_|ixy_d~17_combout ), + .datab(\z80_|execute_|ctl_mWrite~15_combout ), + .datac(\z80_|execute_|ctl_mWrite~14_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'hDFCF; +defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N1 dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mWrite~15_combout ), + .d(\z80_|execute_|ctl_mWrite~16_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -48008,7 +9324,7 @@ defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N4 +// Location: LCCOMB_X37_Y14_N12 cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( // Equation(s): // \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q @@ -48025,7 +9341,7 @@ defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N5 +// Location: FF_X37_Y14_N13 dffeas \z80_|memory_ifc_|wait_mwr ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), @@ -48044,15 +9360,32 @@ defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; // synopsys translate_on -// Location: FF_X43_Y17_N17 +// Location: LCCOMB_X40_Y11_N20 +cycloneive_lcell_comb \z80_|memory_ifc_|mwr_wr~feeder ( +// Equation(s): +// \z80_|memory_ifc_|mwr_wr~feeder_combout = \z80_|memory_ifc_|wait_mwr~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|wait_mwr~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|mwr_wr~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|mwr_wr~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|mwr_wr~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y11_N21 dffeas \z80_|memory_ifc_|mwr_wr ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_mwr~q ), + .d(\z80_|memory_ifc_|mwr_wr~feeder_combout ), + .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), @@ -48063,1063 +9396,1523 @@ defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N16 +// Location: LCCOMB_X40_Y11_N24 cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( // Equation(s): -// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|memory_ifc_|iorq~0_combout )) +// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIOWrite~5_combout )) - .dataa(\z80_|execute_|fIOWrite~5_combout ), - .datab(\z80_|memory_ifc_|iorq~0_combout ), - .datac(\z80_|memory_ifc_|mwr_wr~q ), + .dataa(\z80_|memory_ifc_|iorq~0_combout ), + .datab(\z80_|memory_ifc_|mwr_wr~q ), + .datac(\z80_|execute_|fIOWrite~5_combout ), .datad(gnd), .cin(gnd), .combout(\z80_|memory_ifc_|nWR_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hF8F8; +defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hECEC; defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N4 -cycloneive_lcell_comb \D[5]~84 ( -// Equation(s): -// \D[5]~84_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\D[5]~84_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~84 .lut_mask = 16'h0040; -defparam \D[5]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y5_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: M9K_X33_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N14 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # -// ((\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// (\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .lut_mask = 16'hBA98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N4 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hF858; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y24_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y30_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; -// synopsys translate_on - -// Location: M9K_X22_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; -// synopsys translate_on - -// Location: M9K_X33_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N18 -cycloneive_lcell_comb \Mux0~0 ( -// Equation(s): -// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .cin(gnd), - .combout(\Mux0~0_combout ), - .cout()); -// synopsys translate_off -defparam \Mux0~0 .lut_mask = 16'hBA98; -defparam \Mux0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N12 -cycloneive_lcell_comb \Mux0~1 ( -// Equation(s): -// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\Mux0~0_combout ), - .cin(gnd), - .combout(\Mux0~1_combout ), - .cout()); -// synopsys translate_off -defparam \Mux0~1 .lut_mask = 16'hBBC0; -defparam \Mux0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N22 -cycloneive_lcell_comb \D[7]~112 ( -// Equation(s): -// \D[7]~112_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Mux0~1_combout ))) -// # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), - .datad(\Mux0~1_combout ), - .cin(gnd), - .combout(\D[7]~112_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~112 .lut_mask = 16'hF4B0; -defparam \D[7]~112 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N30 -cycloneive_lcell_comb \D[7]~94 ( -// Equation(s): -// \D[7]~94_combout = (\D[5]~84_combout & (\D[7]~112_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & ((\z80_|data_pins_|dout [7]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\D[5]~84_combout ), - .datab(\z80_|data_pins_|dout [7]), - .datac(\D[7]~112_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[7]~94_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~94 .lut_mask = 16'hC4F5; -defparam \D[7]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N26 -cycloneive_lcell_comb \D[7]~102 ( -// Equation(s): -// \D[7]~102_combout = (\D[7]~94_combout ) # (!\D[0]~107_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\D[7]~94_combout ), - .datad(\D[0]~107_combout ), - .cin(gnd), - .combout(\D[7]~102_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~102 .lut_mask = 16'hF0FF; -defparam \D[7]~102 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N26 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\D[7]~102_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[7]~7_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[7]~102_combout & (\z80_|bus_control_|db[7]~7_combout -// & ((\z80_|execute_|ctl_bus_db_we~7_combout )))) - - .dataa(\D[7]~102_combout ), - .datab(\z80_|bus_control_|db[7]~7_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hECA0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N27 -dffeas \z80_|data_pins_|dout[7] ( +// Location: FF_X40_Y11_N17 +dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .d(\z80_|execute_|setM1~53_combout ), .asdata(vcc), - .clrn(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|data_pins_|dout [7]), + .q(\z80_|memory_ifc_|DFFE_m1_ff1~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[7] .power_up = "low"; +defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N2 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( +// Location: LCCOMB_X40_Y11_N8 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( // Equation(s): -// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) +// \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q .dataa(gnd), - .datab(\z80_|alu_control_|db[7]~18_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_m1_ff1~q ), .cin(gnd), - .combout(\z80_|bus_control_|db[7]~5_combout ), + .combout(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N8 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( -// Equation(s): -// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|data_pins_|dout [7]), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|bus_control_|db[7]~5_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[7]~7_combout ), - .cout()); +// Location: FF_X40_Y11_N9 +dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), + .prn(vcc)); // synopsys translate_off -defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hBF0F; -defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; // synopsys translate_on -// Location: FF_X32_Y13_N21 -dffeas \z80_|ir_|opcode[7] ( +// Location: FF_X40_Y11_N7 +dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|bus_control_|db[7]~7_combout ), + .asdata(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [7]), + .q(\z80_|memory_ifc_|DFFE_m1_ff3~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[7] .power_up = "low"; +defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y13_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( +// Location: LCCOMB_X40_Y11_N6 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( // Equation(s): -// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) +// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # ((\z80_|memory_ifc_|DFFE_m1_ff3~q )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & +// (!\z80_|interrupts_|DFFE_inst44~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # (\z80_|memory_ifc_|DFFE_m1_ff3~q )))) - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), + .datac(\z80_|memory_ifc_|DFFE_m1_ff3~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~0_combout ), + .combout(\z80_|memory_ifc_|nRD_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0010; -defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hA8FC; +defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( +// Location: LCCOMB_X29_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~2 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|pla_decode_|Equal77~0_combout & (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~1_combout ))) +// \z80_|execute_|ctl_mRead~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal2~0_combout ))) - .dataa(\z80_|pla_decode_|Equal77~0_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal2~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~5_combout ), + .combout(\z80_|execute_|ctl_mRead~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( +// Location: LCCOMB_X38_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( // Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_ir_we~4_combout & (\z80_|pla_decode_|Equal8~0_combout & !\z80_|ir_|opcode [3]))) +// \z80_|execute_|fIORead~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hC080; +defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h0033; +defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~15_combout = (\z80_|execute_|ctl_mWrite~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal1~4_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( +// Equation(s): +// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hC080; +defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( +// Equation(s): +// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|ctl_alu_op_low~15_combout ) # ((\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|fIOWrite~0_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~10_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datac(\z80_|execute_|fIOWrite~0_combout ), + .datad(\z80_|execute_|fIORead~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFFCE; +defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( +// Equation(s): +// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|ctl_mRead~2_combout & \z80_|execute_|fIOWrite~1_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|fIORead~0_combout ), + .datac(\z80_|execute_|fIOWrite~1_combout ), + .datad(\z80_|execute_|fIORead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hAA00; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( +// Equation(s): +// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_im_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N23 +dffeas \z80_|interrupts_|im2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_im_we~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|im2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~10_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|im2~q ), + .datac(gnd), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~1_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ctl_mRead~30_combout ) # ((\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mRead~10_combout ), + .datac(\z80_|execute_|ctl_mRead~30_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'hFCF0; +defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [1]) # ((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~4_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFCF; +defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal44~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal44~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0010; +defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~6_combout = (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|DFFE_inst4~q ))) + + .dataa(\z80_|pla_decode_|Equal44~0_combout ), + .datab(\z80_|decode_state_|DFFE_instIY1~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( +// Equation(s): +// \z80_|execute_|fMRead~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|pla_decode_|Equal13~2_combout )) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMRead~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0202; +defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~17_combout = (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|fMWrite~0_combout & \z80_|execute_|fMRead~5_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|fMWrite~0_combout ), + .datad(\z80_|execute_|fMRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~12_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h00A0; +defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal49~0_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal77~0_combout & !\z80_|decode_state_|in_halt~q )) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal77~0_combout ), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal49~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h0808; +defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~57 ( +// Equation(s): +// \z80_|execute_|setM1~57_combout = (!\z80_|execute_|ctl_mRead~12_combout & (((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )) # (!\z80_|pla_decode_|Equal49~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~57 .lut_mask = 16'h5551; +defparam \z80_|execute_|setM1~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~15_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal25~0_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal25~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_ir_we~6_combout & (\z80_|pla_decode_|Equal55~0_combout & !\z80_|decode_state_|table_xx~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_ir_we~6_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|decode_state_|table_xx~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h3303; +defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( +// Equation(s): +// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( +// Equation(s): +// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) + + .dataa(\z80_|pla_decode_|Equal44~0_combout ), + .datab(\z80_|decode_state_|DFFE_instIY1~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hA080; +defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ixy_d~10_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ctl_mRead~3_combout & !\z80_|execute_|ctl_mRead~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~10_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( +// Equation(s): +// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_al_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0A00; +defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal29~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal29~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~38 ( +// Equation(s): +// \z80_|execute_|setM1~38_combout = (\z80_|execute_|fMRead~4_combout & (!\z80_|pla_decode_|Equal29~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) + + .dataa(\z80_|execute_|fMRead~4_combout ), + .datab(\z80_|pla_decode_|Equal29~0_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|setM1~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~38 .lut_mask = 16'h0202; +defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal35~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~33_combout = (!\z80_|pla_decode_|Equal35~0_combout & ((\z80_|ir_|opcode [4]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|pla_decode_|Equal24~0_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), .datad(\z80_|ir_|opcode [3]), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .combout(\z80_|execute_|pc_inc_hold~33_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'h0F0B; +defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( +// Location: LCCOMB_X38_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|comb~1 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) +// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .dataa(gnd), + .datab(\z80_|ir_|opcode [5]), + .datac(gnd), + .datad(\z80_|ir_|opcode [4]), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), + .combout(\z80_|execute_|comb~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; +defparam \z80_|execute_|comb~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( +// Location: LCCOMB_X38_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~8_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|M5~q & ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) +// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|comb~1_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), + .combout(\z80_|execute_|ctl_mRead~13_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h3020; -defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( +// Location: LCCOMB_X38_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) +// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|pla_decode_|Equal41~2_combout ))) - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .dataa(\z80_|execute_|ctl_mRead~13_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( +// Location: LCCOMB_X39_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) +// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|pc_inc_hold~33_combout & (!\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout )) - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), + .dataa(gnd), + .datab(\z80_|execute_|pc_inc_hold~33_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC8C0; -defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0C00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( +// Location: LCCOMB_X36_Y6_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~2 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~6_combout = (((\z80_|execute_|ctl_bus_db_we~4_combout ) # (!\z80_|execute_|ctl_sw_2u~3_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) +// \z80_|pla_decode_|Equal40~2_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [2]))) - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~4_combout ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [2]), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), + .combout(\z80_|pla_decode_|Equal40~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal40~2 .lut_mask = 16'h0010; +defparam \z80_|pla_decode_|Equal40~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( +// Location: LCCOMB_X36_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~36 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~3_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|execute_|ctl_bus_db_we~2_combout ) # (\z80_|execute_|ctl_bus_db_we~6_combout ))) +// \z80_|execute_|setM1~36_combout = (!\z80_|pla_decode_|Equal6~1_combout & (((!\z80_|ir_|opcode [5] & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal40~2_combout ))) - .dataa(\z80_|execute_|ctl_bus_db_we~3_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~6_combout ), + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|pla_decode_|Equal40~2_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), + .combout(\z80_|execute_|setM1~36_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; +defparam \z80_|execute_|setM1~36 .lut_mask = 16'h1115; +defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~50 ( +// Location: LCCOMB_X37_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~14 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) +// \z80_|execute_|pc_inc_hold~14_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|pla_decode_|Equal33~2_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|pla_decode_|Equal50~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~14 .lut_mask = 16'h1115; +defparam \z80_|execute_|pc_inc_hold~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~37 ( +// Equation(s): +// \z80_|execute_|setM1~37_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (\z80_|execute_|setM1~36_combout & (\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datab(\z80_|execute_|setM1~36_combout ), + .datac(\z80_|execute_|pc_inc_hold~14_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~37 .lut_mask = 16'h0080; +defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~14_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~39 ( +// Equation(s): +// \z80_|execute_|setM1~39_combout = (\z80_|execute_|setM1~57_combout & (\z80_|execute_|setM1~38_combout & (\z80_|execute_|setM1~37_combout & !\z80_|execute_|ctl_mRead~14_combout ))) + + .dataa(\z80_|execute_|setM1~57_combout ), + .datab(\z80_|execute_|setM1~38_combout ), + .datac(\z80_|execute_|setM1~37_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0080; +defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((!\z80_|execute_|setM1~39_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|ctl_mRead~17_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|setM1~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0011; +defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal40~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h4040; +defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal37~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0400; +defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~26_combout = (\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~2_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~16_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal12~0_combout & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal12~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~13_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~19_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~1_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal38~2_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|pla_decode_|Equal35~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~0 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N8 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~1_combout = (\z80_|pla_decode_|Equal24~1_combout ) # ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|reg_control_|reg_sys_we_lo~0_combout ) # (\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~1_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~0_combout ), + .datad(\z80_|pla_decode_|Equal29~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~1 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|reg_control_|reg_sys_we_lo~1_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # +// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|reg_control_|reg_sys_we_lo~1_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~1_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'h153F; +defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~18_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~20_combout = (\z80_|reg_control_|reg_sys_we_lo~2_combout & (((!\z80_|execute_|ctl_mRead~19_combout & !\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~19_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~22_combout = (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~20_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~16_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datab(\z80_|execute_|ctl_mRead~16_combout ), + .datac(\z80_|execute_|ctl_mRead~20_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~1_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|DFFE_instED~q & !\z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0008; +defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~23_combout = (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_mRead~14_combout & +// (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~14_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~27_combout = (\z80_|execute_|ctl_mRead~23_combout & (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal38~2_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|ctl_mRead~27_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~26_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mRead~22_combout ), + .datad(\z80_|execute_|ctl_mRead~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~3 ( +// Equation(s): +// \z80_|execute_|nextM~3_combout = (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|pla_decode_|Equal41~2_combout )) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ixy_d~10_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0011; +defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|execute_|nextM~3_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h8F00; +defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~31_combout ) # ((\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_mRead~29_combout ) # (!\z80_|execute_|ctl_mRead~28_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~31_combout ), + .datab(\z80_|execute_|ctl_mRead~32_combout ), + .datac(\z80_|execute_|ctl_mRead~28_combout ), + .datad(\z80_|execute_|ctl_mRead~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y11_N19 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mRead~33_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N28 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q .dataa(gnd), .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~50 .lut_mask = 16'h000F; -defparam \ula_|zx_keyboard_|keys[0][2]~50 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~52 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~52_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[0][2]~50_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[0][2]~50_combout & ((\ula_|zx_keyboard_|keys[0][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[0][2]~q ), - .datad(\ula_|zx_keyboard_|keys[0][2]~50_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~52_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~52 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][2]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N17 -dffeas \ula_|zx_keyboard_|keys[0][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][2]~52_combout ), +// Location: FF_X40_Y11_N29 +dffeas \z80_|memory_ifc_|wait_mrd ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][2]~q ), + .q(\z80_|memory_ifc_|wait_mrd~q ), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; +defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~48 ( +// Location: LCCOMB_X40_Y11_N10 +cycloneive_lcell_comb \z80_|memory_ifc_|DFFE_mrd_ff3~feeder ( // Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~48_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~48 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|keys[3][3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~49 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~49_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[6][4]~47_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout & (\ula_|zx_keyboard_|keys[1][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[1][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .datab(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~49 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][2]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N23 -dffeas \ula_|zx_keyboard_|keys[1][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N22 -cycloneive_lcell_comb \D[2]~35 ( -// Equation(s): -// \D[2]~35_combout = (\z80_|address_pins_|abus[8]~18_combout & (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) # (!\z80_|address_pins_|abus[8]~18_combout & (!\ula_|zx_keyboard_|keys[0][2]~q & -// ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) - - .dataa(\z80_|address_pins_|abus[8]~18_combout ), - .datab(\ula_|zx_keyboard_|keys[0][2]~q ), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\z80_|address_pins_|abus[9]~17_combout ), - .cin(gnd), - .combout(\D[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~35 .lut_mask = 16'hBB0B; -defparam \D[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~57 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~57_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]) +// \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout = \z80_|memory_ifc_|wait_mrd~q .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(gnd), .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\z80_|memory_ifc_|wait_mrd~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~57_combout ), + .combout(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~57 .lut_mask = 16'h3300; -defparam \ula_|zx_keyboard_|keys[5][2]~57 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~58 ( +// Location: FF_X40_Y11_N11 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N0 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~58_combout = (\ula_|zx_keyboard_|keys[5][2]~57_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[5][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[5][2]~57_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) +// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|wait_mrd~q ) - .dataa(\ula_|zx_keyboard_|keys[5][2]~57_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[5][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), + .dataa(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|wait_mrd~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~58_combout ), + .combout(\z80_|memory_ifc_|nRD_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~58 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][2]~58 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0055; +defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y18_N15 -dffeas \ula_|zx_keyboard_|keys[5][2] ( +// Location: LCCOMB_X40_Y11_N12 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~2_combout = (\z80_|memory_ifc_|nRD_out~0_combout ) # (((\z80_|execute_|fIORead~3_combout & \z80_|memory_ifc_|iorq~0_combout )) # (!\z80_|memory_ifc_|nRD_out~1_combout )) + + .dataa(\z80_|memory_ifc_|nRD_out~0_combout ), + .datab(\z80_|execute_|fIORead~3_combout ), + .datac(\z80_|memory_ifc_|iorq~0_combout ), + .datad(\z80_|memory_ifc_|nRD_out~1_combout ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hEAFF; +defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N12 +cycloneive_lcell_comb \Equal2~1 ( +// Equation(s): +// \Equal2~1_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nRD_out~2_combout )) + + .dataa(gnd), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nRD_out~2_combout ), + .cin(gnd), + .combout(\Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~1 .lut_mask = 16'h3000; +defparam \Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y34_N1 +cycloneive_io_ibuf \PS2_DAT~input ( + .i(PS2_DAT), + .ibar(gnd), + .o(\PS2_DAT~input_o )); +// synopsys translate_off +defparam \PS2_DAT~input .bus_hold = "false"; +defparam \PS2_DAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G9 +cycloneive_clkctrl \reset~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\reset~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\reset~clkctrl_outclk )); +// synopsys translate_off +defparam \reset~clkctrl .clock_type = "global clock"; +defparam \reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N18 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [1] & ((!\ula_|ps2_keyboard_|bit_count [2]) # (!\ula_|ps2_keyboard_|bit_count [3])))) # (!\ula_|ps2_keyboard_|bit_count [0] & +// (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [1]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [1]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h121A; +defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y34_N8 +cycloneive_io_ibuf \PS2_CLK~input ( + .i(PS2_CLK), + .ibar(gnd), + .o(\PS2_CLK~input_o )); +// synopsys translate_off +defparam \PS2_CLK~input .bus_hold = "false"; +defparam \PS2_CLK~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N24 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\PS2_CLK~input_o ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N25 +dffeas \ula_|ps2_keyboard_|clk_filter[7] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][2]~58_combout ), + .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49128,70 +10921,827 @@ dffeas \ula_|zx_keyboard_|keys[5][2] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][2]~q ), + .q(\ula_|ps2_keyboard_|clk_filter [7]), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; +defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~59 ( +// Location: LCCOMB_X17_Y27_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~59_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|extended~q ))) +// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|extended~q ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [7]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~59_combout ), + .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~59 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[4][2]~59 .sum_lutc_input = "datac"; +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~131 ( +// Location: FF_X17_Y27_N3 +dffeas \ula_|ps2_keyboard_|clk_filter[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~131_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[4][2]~59_combout & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [0]))) +// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [6]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N13 +dffeas \ula_|ps2_keyboard_|clk_filter[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N18 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N19 +dffeas \ula_|ps2_keyboard_|clk_filter[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [4]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N11 +dffeas \ula_|ps2_keyboard_|clk_filter[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N20 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [5] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [4] & !\ula_|ps2_keyboard_|clk_filter [6]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [5]), + .datab(\ula_|ps2_keyboard_|clk_filter [7]), + .datac(\ula_|ps2_keyboard_|clk_filter [4]), + .datad(\ula_|ps2_keyboard_|clk_filter [6]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N1 +dffeas \ula_|ps2_keyboard_|clk_filter[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N23 +dffeas \ula_|ps2_keyboard_|clk_filter[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|clk_filter [3] & (\ula_|ps2_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|clk_filter [1] & !\ula_|ps2_keyboard_|clk_filter [2]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [3]), + .datab(\ula_|ps2_keyboard_|Equal0~0_combout ), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0004; +defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N27 +dffeas \ula_|ps2_keyboard_|clk_filter[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|clk_filter [0])) # (!\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|ps2_clk_in~q ))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hAAF0; +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N7 +dffeas \ula_|ps2_keyboard_|ps2_clk_in ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|clk_filter [0] & !\ula_|ps2_keyboard_|ps2_clk_in~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datac(\ula_|ps2_keyboard_|clk_filter [0]), + .datad(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h00C0; +defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N17 +dffeas \ula_|ps2_keyboard_|clk_edge ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_edge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; +// synopsys translate_on + +// Location: FF_X18_Y12_N19 +dffeas \ula_|ps2_keyboard_|bit_count[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [2]))) # (!\ula_|ps2_keyboard_|bit_count [1] & +// (((\ula_|ps2_keyboard_|bit_count [3] & !\ula_|ps2_keyboard_|bit_count [2])))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [1]), + .datac(\ula_|ps2_keyboard_|bit_count [3]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h0830; +defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y12_N29 +dffeas \ula_|ps2_keyboard_|bit_count[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [0] & \ula_|ps2_keyboard_|bit_count [1]))))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [2]), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; +defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y12_N13 +dffeas \ula_|ps2_keyboard_|bit_count[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [2] & !\ula_|ps2_keyboard_|bit_count [1])) # (!\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [2]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [0]), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; +defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y12_N23 +dffeas \ula_|ps2_keyboard_|bit_count[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [2]) # (\ula_|ps2_keyboard_|bit_count [1]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [2]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCC88; +defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [3] & !\PS2_DAT~input_o ))) + + .dataa(\ula_|ps2_keyboard_|bit_count [2]), + .datab(\ula_|ps2_keyboard_|bit_count [1]), + .datac(\ula_|ps2_keyboard_|bit_count [3]), + .datad(\PS2_DAT~input_o ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (!\ula_|ps2_keyboard_|LessThan0~0_combout & (\ula_|ps2_keyboard_|clk_edge~q & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|always1~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h2030; +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y10_N5 +dffeas \ula_|ps2_keyboard_|shiftreg[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\PS2_DAT~input_o ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y10_N27 +dffeas \ula_|ps2_keyboard_|shiftreg[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [8]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y10_N13 +dffeas \ula_|ps2_keyboard_|shiftreg[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [7]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y8_N21 +dffeas \ula_|ps2_keyboard_|shiftreg[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [6]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y10_N31 +dffeas \ula_|ps2_keyboard_|shiftreg[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [5]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X20_Y8_N17 +dffeas \ula_|ps2_keyboard_|shiftreg[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [4]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X20_Y8_N31 +dffeas \ula_|ps2_keyboard_|shiftreg[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [3]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X20_Y8_N23 +dffeas \ula_|ps2_keyboard_|shiftreg[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [2]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y10_N23 +dffeas \ula_|ps2_keyboard_|shiftreg[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [1]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [6]))) .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[4][2]~59_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|zx_keyboard_|Equal0~0_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~131_combout ), + .combout(\ula_|zx_keyboard_|Equal0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~131 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[4][2]~131 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~60 ( +// Location: LCCOMB_X19_Y10_N4 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~60_combout = (\ula_|zx_keyboard_|keys[4][2]~131_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[4][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[4][2]~131_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) +// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [6]))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[4][2]~131_combout ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [8]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~60_combout ), + .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~60 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[4][2]~60 .sum_lutc_input = "datac"; +defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y18_N15 -dffeas \ula_|zx_keyboard_|keys[4][2] ( +// Location: LCCOMB_X19_Y10_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N24 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~0_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hC33C; +defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N24 +cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|WideXor0~2_combout & (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|LessThan0~0_combout ))) + + .dataa(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .datab(\PS2_DAT~input_o ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y12_N25 +dffeas \ula_|ps2_keyboard_|scan_code_ready ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][2]~60_combout ), + .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49200,86 +11750,175 @@ dffeas \ula_|zx_keyboard_|keys[4][2] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][2]~q ), + .q(\ula_|ps2_keyboard_|scan_code_ready~q ), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; +defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N4 -cycloneive_lcell_comb \D[2]~37 ( +// Location: LCCOMB_X20_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( // Equation(s): -// \D[2]~37_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][2]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) +// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|released~q ) # (\ula_|ps2_keyboard_|shiftreg [4])))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & +// (((\ula_|zx_keyboard_|released~q )))) - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~q ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~37 .lut_mask = 16'hBB0B; -defparam \D[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~53 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~53_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .dataa(\ula_|zx_keyboard_|Equal0~1_combout ), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|zx_keyboard_|released~q ), .datad(\ula_|ps2_keyboard_|shiftreg [4]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~53_combout ), + .combout(\ula_|zx_keyboard_|released~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~53 .lut_mask = 16'h00F0; -defparam \ula_|zx_keyboard_|keys[3][2]~53 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hB8B0; +defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~55 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~55_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) +// Location: FF_X20_Y9_N27 +dffeas \ula_|zx_keyboard_|released ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|released~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|released~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|released .power_up = "low"; +// synopsys translate_on - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), +// Location: LCCOMB_X21_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(gnd), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~55_combout ), + .combout(\ula_|zx_keyboard_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~55 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[2][2]~55 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h1010; +defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~56 ( +// Location: LCCOMB_X20_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~50 ( // Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~56_combout = (\ula_|zx_keyboard_|keys[2][2]~55_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~55_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) +// \ula_|zx_keyboard_|keys[3][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~50 .lut_mask = 16'h5500; +defparam \ula_|zx_keyboard_|keys[3][2]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( +// Equation(s): +// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|zx_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|extended~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hA0AA; +defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N1 +dffeas \ula_|zx_keyboard_|extended ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|extended~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|extended~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|extended .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~15 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~15_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~15 .lut_mask = 16'h0010; +defparam \ula_|zx_keyboard_|keys[7][4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~52 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~52_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[3][2]~50_combout & \ula_|zx_keyboard_|keys[7][4]~15_combout ))) + + .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .datad(\ula_|zx_keyboard_|keys[7][4]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~52_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~52 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[2][2]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~53 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~53_combout = (\ula_|zx_keyboard_|keys[2][2]~52_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~52_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), .datac(\ula_|zx_keyboard_|keys[2][2]~q ), - .datad(\ula_|zx_keyboard_|keys[2][2]~55_combout ), + .datad(\ula_|zx_keyboard_|keys[2][2]~52_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~56_combout ), + .combout(\ula_|zx_keyboard_|keys[2][2]~53_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~56 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[2][2]~56 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][2]~53 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[2][2]~53 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y20_N27 +// Location: FF_X20_Y9_N25 dffeas \ula_|zx_keyboard_|keys[2][2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][2]~56_combout ), + .d(\ula_|zx_keyboard_|keys[2][2]~53_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49295,28 +11934,27482 @@ defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~54 ( +// Location: LCCOMB_X31_Y14_N4 +cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~54_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][2]~53_combout & ((\ula_|zx_keyboard_|keys[3][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) +// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # +// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[3][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][2]~53_combout ), + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|resets_|clrpc_int~q ), + .datad(\z80_|resets_|x1~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~54_combout ), + .combout(\z80_|resets_|clrpc_int~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~54 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[3][2]~54 .sum_lutc_input = "datac"; +defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; +defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y20_N29 +// Location: FF_X31_Y14_N5 +dffeas \z80_|resets_|clrpc_int ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|clrpc_int~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|clrpc_int~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; +defparam \z80_|resets_|clrpc_int .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N0 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0F0F; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N1 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N14 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_9~feeder ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout = \z80_|resets_|SYNTHESIZED_WIRE_10~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .lut_mask = 16'hFF00; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N15 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y12_N27 +dffeas \z80_|resets_|DFFE_intr_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N26 +cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( +// Equation(s): +// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|clrpc_int~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|SYNTHESIZED_WIRE_10~q ))) + + .dataa(\z80_|resets_|clrpc_int~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .datac(\z80_|resets_|DFFE_intr_ff3~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .cin(gnd), + .combout(\z80_|resets_|clrpc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; +defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_al_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h4044; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~1_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal40~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal40~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal40~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; +defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal39~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal40~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal40~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0003; +defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal6~1_combout )) + + .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h000A; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ))) + + .dataa(\z80_|execute_|fMRead~2_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h0555; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_alu_oe~2_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h5554; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & ((\z80_|execute_|fMRead~2_combout ) # ((\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~14_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .datad(\z80_|execute_|fMRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h0F02; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~10_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_mRead~13_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'h0003; +defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~20_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hDFDF; +defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~4_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h33BB; +defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_reg_sys_hilo~20_combout & (((\z80_|execute_|ctl_inc_dec~4_combout )) # (!\z80_|pla_decode_|Equal33~3_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo~20_combout & +// (!\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datab(\z80_|pla_decode_|Equal33~3_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_inc_dec~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hAF23; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & ((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout +// )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00D0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~33_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|pc_inc_hold~33_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h50D0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & \z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|execute_|ctl_mRead~7_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .datac(\z80_|execute_|ctl_al_we~5_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h4044; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~13_combout = ((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'hF0D0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~16_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~12_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~16 .lut_mask = 16'h8808; +defparam \z80_|execute_|ctl_reg_sys_hilo~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~16_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_mWrite~9_combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h010F; +defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_al_we~13_combout & \z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'hB300; +defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|setM1~53_combout & (\z80_|execute_|ctl_reg_sel_pc~12_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~6_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~6 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_alu_bs_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~6_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~2_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal29~0_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout & +// (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|pla_decode_|Equal29~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; +defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal9~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h3777; +defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N0 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~1_combout & (\z80_|reg_control_|reg_sel_pc~0_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal38~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h7000; +defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal56~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal56~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~18_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~17_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|execute_|ctl_alu_op_low~17_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_oe~4_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~9_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_in_hi~4_combout & \z80_|execute_|ctl_reg_in_hi~3_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|execute_|ctl_mWrite~9_combout ) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~9_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h337F; +defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( +// Equation(s): +// \z80_|execute_|fMRead~6_combout = (\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|execute_|ctl_alu_op_low~14_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_mRead~13_combout )))) # +// (!\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N28 +cycloneive_lcell_comb \z80_|nM1_int~2 ( +// Equation(s): +// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|nM1_int~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|nM1_int~2 .lut_mask = 16'h000F; +defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_dec~3_combout & (\z80_|execute_|fMRead~6_combout & (!\z80_|nM1_int~2_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), + .datab(\z80_|execute_|fMRead~6_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~94 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~94_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~94_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~94 .lut_mask = 16'h7F7F; +defparam \z80_|execute_|ctl_inc_cy~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~50_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hF5F7; +defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ixy_d~16_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & +// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ixy_d~16_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~15_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ixy_d~10_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h373F; +defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~13_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h3F37; +defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & (\z80_|execute_|ctl_reg_sel_pc~4_combout & \z80_|execute_|ctl_reg_sel_pc~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & +// (!\z80_|pla_decode_|Equal12~1_combout & ((\z80_|pla_decode_|Equal25~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(\z80_|pla_decode_|Equal24~0_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'hB3A0; +defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|execute_|ctl_reg_sel_pc~8_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h020A; +defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~99 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~99_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~99_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~99 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_inc_cy~99 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~50_combout & (\z80_|execute_|ctl_reg_sel_pc~10_combout & \z80_|execute_|ctl_inc_cy~99_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), + .datab(\z80_|execute_|ctl_inc_cy~50_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .datad(\z80_|execute_|ctl_inc_cy~99_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & +// !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~9_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal47~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF1FF; +defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'hEAFF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~5_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal48~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal48~0_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal48~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h5444; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ))) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~13_combout = (\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout & !\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout )) # +// (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h131F; +defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h00FC; +defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((!\z80_|execute_|ctl_flags_bus~4_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hFF73; +defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( +// Equation(s): +// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|setM1~37_combout & (!\z80_|execute_|ctl_mRead~11_combout & (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal21~1_combout ))) + + .dataa(\z80_|execute_|setM1~37_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h0002; +defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~33_combout = (!\z80_|execute_|ctl_mRead~12_combout & ((\z80_|ir_|opcode [3]) # ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal12~0_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal12~0_combout ), + .datad(\z80_|execute_|ctl_mRead~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h00EF; +defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~35_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & (((\z80_|execute_|fMRead~7_combout & \z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) + + .dataa(\z80_|execute_|fMRead~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'h8C0C; +defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~34_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|pc_inc_hold~33_combout & ((!\z80_|decode_state_|use_ixiy~combout ) # (!\z80_|pla_decode_|Equal33~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|pla_decode_|Equal33~2_combout ), + .datac(\z80_|execute_|pc_inc_hold~33_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h1050; +defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_mWrite~9_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_mRead~34_combout +// & ((\z80_|execute_|ctl_mWrite~9_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~9_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~1_combout = (!\z80_|execute_|ctl_reg_sys_we~0_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'h0155; +defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal48~0_combout & \z80_|sequencer_|DFFE_T4_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~2_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~34_combout & \z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'hFF4F; +defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal8~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0])) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h4400; +defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~1_combout = (\z80_|execute_|ctl_reg_sys_we_lo~0_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( +// Equation(s): +// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal40~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal40~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|sel[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h2AAA; +defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & +// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal52~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h053F; +defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~7_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|execute_|ctl_state_alu~7_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hAA2A; +defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'h00EF; +defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~5_combout = (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|table_xx~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0002; +defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~10_combout = (\z80_|pla_decode_|Equal52~1_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # ((\z80_|execute_|ctl_state_alu~9_combout & \z80_|execute_|ctl_state_alu~5_combout )))) # (!\z80_|pla_decode_|Equal52~1_combout +// & (\z80_|execute_|ctl_state_alu~9_combout & ((\z80_|execute_|ctl_state_alu~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~9_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_state_alu~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'hECA0; +defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|pla_decode_|Equal52~1_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_state_alu~6_combout & +// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'hFA32; +defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~11_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hAAA2; +defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~5_combout = (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal62~2_combout )) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal62~2_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hF777; +defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hABFF; +defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~7_combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~7 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_alu_bs_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~7_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~19_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~19 .lut_mask = 16'hDDDF; +defparam \z80_|execute_|ctl_flags_xy_we~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~2_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~25_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~26_combout = ((!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|execute_|ctl_mRead~34_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_iorw~10_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~28_combout = (\z80_|execute_|ctl_alu_shift_oe~25_combout & (\z80_|execute_|ctl_alu_shift_oe~26_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~27_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~19_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal6~0_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hFF37; +defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~9_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|execute_|ctl_flags_bus~15_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h5070; +defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal20~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|comb~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal20~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal68~2_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|pla_decode_|Equal68~2_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF57; +defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal63~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|execute_|comb~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal63~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal76~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal76~2_combout = (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal76~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal76~2 .lut_mask = 16'h0A00; +defparam \z80_|pla_decode_|Equal76~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~8_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal76~2_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal76~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal32~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|execute_|ixy_d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~7_combout = ((!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_flags_bus~6_combout & !\z80_|pla_decode_|Equal13~2_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~6_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|execute_|ctl_flags_bus~9_combout & (\z80_|execute_|ctl_flags_bus~14_combout & (\z80_|execute_|ctl_flags_bus~8_combout & \z80_|execute_|ctl_flags_bus~7_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~9_combout ), + .datab(\z80_|execute_|ctl_flags_bus~14_combout ), + .datac(\z80_|execute_|ctl_flags_bus~8_combout ), + .datad(\z80_|execute_|ctl_flags_bus~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_bus_db_oe~3_combout & (\z80_|execute_|ctl_flags_xy_we~19_combout & (\z80_|execute_|ctl_alu_shift_oe~28_combout & \z80_|execute_|ctl_flags_bus~10_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datad(\z80_|execute_|ctl_flags_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf2_we~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h0155; +defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel~7_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|decode_state_|table_xx~0_combout ), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel~7 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~12_combout = ((\z80_|execute_|ctl_reg_gp_sel~7_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout ))) # (!\z80_|execute_|ctl_state_alu~7_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|ctl_state_alu~12_combout & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal62~3_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_alu_op_low~19_combout & !\z80_|execute_|ctl_iorw~10_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datab(\z80_|execute_|ctl_iorw~10_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'hFFF1; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~7_combout = (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~10 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~10_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~10 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_pf_sel[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~29_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hAAA2; +defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~11_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~11 .lut_mask = 16'hCCC4; +defparam \z80_|execute_|ctl_flags_pf_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & (\z80_|execute_|ctl_pf_sel[0]~10_combout & \z80_|execute_|ctl_flags_pf_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~10_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal10~1_combout = (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal10~1 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal10~1_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal10~1_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal69~0_combout = (\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal69~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'h0A02; +defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~8_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_pf_we~7_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~13 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~13_combout = (\z80_|ir_|opcode [5]) # (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_state_alu~12_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~13 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_pf_sel[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~10_combout = (((\z80_|execute_|ctl_flags_pf_we~9_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout )) # (!\z80_|execute_|ctl_flags_xy_we~11_combout )) # (!\z80_|execute_|ctl_flags_pf_we~5_combout ) + + .dataa(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N20 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~3_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'h0F1F; +defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~18_combout = (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N0 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|reg_control_|reg_sys_we_lo~3_combout & (\z80_|execute_|ctl_flags_xy_we~18_combout & ((!\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h40C0; +defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~5_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h7700; +defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N10 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~6_combout = (((\z80_|execute_|ctl_reg_sys_we_lo~1_combout & \z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~5_combout ) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'hDF5F; +defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout ) # ((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hFBFB; +defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~21_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (\z80_|execute_|ctl_mRead~20_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datac(\z80_|execute_|ctl_mRead~20_combout ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~21 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_sel_wz~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~20_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal35~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~20 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout = (\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|sequencer_|M5~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~44_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|M5~q ))) + + .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'hAA2A; +defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hF2F0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = (((\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'hF777; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout = ((\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~21_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h4040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~5_combout & ((\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~4_combout )))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_mRead~5_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h2333; +defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~1_combout = (\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((!\z80_|execute_|ctl_al_we~14_combout & \z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~14_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) + + .dataa(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'hABFF; +defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~47 ( +// Equation(s): +// \z80_|execute_|setM1~47_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|setM1~46_combout & !\z80_|execute_|ctl_mWrite~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_al_we~13_combout ), + .datac(\z80_|execute_|setM1~46_combout ), + .datad(\z80_|execute_|ctl_mWrite~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~47 .lut_mask = 16'h00C0; +defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|execute_|ctl_alu_oe~5_combout & !\z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|setM1~47_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~5_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|setM1~47_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ixy_d~6_combout & +// ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h2A3F; +defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( +// Equation(s): +// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal9~1_combout & ((!\z80_|pla_decode_|Equal29~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal9~1_combout & +// !\z80_|pla_decode_|Equal29~0_combout )) # (!\z80_|execute_|ctl_state_alu~3_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|pla_decode_|Equal29~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h0537; +defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( +// Equation(s): +// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~14_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal37~0_combout & +// !\z80_|execute_|ctl_mRead~14_combout )) # (!\z80_|execute_|ctl_state_alu~3_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~9 .lut_mask = 16'h111F; +defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( +// Equation(s): +// \z80_|execute_|fMRead~10_combout = (\z80_|execute_|fMRead~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|fMRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h3700; +defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|fMRead~8_combout & \z80_|execute_|fMRead~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datac(\z80_|execute_|fMRead~8_combout ), + .datad(\z80_|execute_|fMRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|pla_decode_|Equal11~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal4~0_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|execute_|comb~1_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|execute_|comb~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~41 ( +// Equation(s): +// \z80_|execute_|setM1~41_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal4~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~41 .lut_mask = 16'h003F; +defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal2~1_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal2~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & ((\z80_|execute_|setM1~41_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|setM1~41_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h0051; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~3_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~3_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_sw_1d~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datad(\z80_|execute_|ctl_sw_1d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & +// (!\z80_|execute_|ctl_alu_oe~2_combout & ((!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hC0DD; +defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sel_wz~11_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_sw_4d~4_combout & (\z80_|execute_|ctl_sw_4d~2_combout & (\z80_|execute_|ctl_sw_4d~3_combout & \z80_|execute_|ctl_reg_sel_wz~12_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~4_combout ), + .datab(\z80_|execute_|ctl_sw_4d~2_combout ), + .datac(\z80_|execute_|ctl_sw_4d~3_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~6_combout = (\z80_|execute_|ctl_sw_4d~1_combout ) # ((\z80_|execute_|ctl_sw_4d~0_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_4d~1_combout ), + .datac(\z80_|execute_|ctl_sw_4d~0_combout ), + .datad(\z80_|execute_|ctl_sw_4d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N30 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~4_combout = ((!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|alu_control_|flags_cond_true~q ) # (!\z80_|pla_decode_|Equal35~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~4 .lut_mask = 16'h337F; +defparam \z80_|reg_control_|reg_sel_pc~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((!\z80_|execute_|fMRead~4_combout & \z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .datab(\z80_|execute_|fMRead~4_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h7F5F; +defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~17_combout = (\z80_|nM1_int~2_combout ) # (((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|ctl_inc_dec~3_combout )) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_inc_dec~3_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'hBBFB; +defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~19_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal33~3_combout ), + .datac(\z80_|execute_|ctl_al_we~5_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'h4500; +defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal21~1_combout & ((!\z80_|pla_decode_|Equal52~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h030F; +defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sel_pc~14_combout ) # (!\z80_|execute_|setM1~37_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .datab(\z80_|execute_|setM1~37_combout ), + .datac(\z80_|execute_|fMRead~2_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hABAF; +defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~18_combout = (\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~17_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (!\z80_|execute_|ctl_sw_4u~1_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~19_combout = (((!\z80_|pla_decode_|Equal34~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_wz~19_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h0080; +defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~combout = (\z80_|reg_control_|reg_sel_pc~4_combout & (\z80_|reg_control_|reg_sel_pc~3_combout & ((\z80_|execute_|ctl_reg_sel_pc~18_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_pc~4_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~3_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h80A0; +defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h4040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~6_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal1~5_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N24 +cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( +// Equation(s): +// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal1~6_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|reg_control_|bank_exx~q ), + .datad(\z80_|pla_decode_|Equal1~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_exx~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y14_N25 +dffeas \z80_|reg_control_|bank_exx ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_exx~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_exx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_exx .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|execute_|ctl_state_alu~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal77~0_combout ), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hC0C4; +defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mWrite~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout ) # +// (!\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h0737; +defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~56 ( +// Equation(s): +// \z80_|execute_|setM1~56_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~56 .lut_mask = 16'hFF1F; +defparam \z80_|execute_|setM1~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (\z80_|execute_|ctl_sw_2u~4_combout & \z80_|execute_|setM1~56_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_2u~1_combout ), + .datac(\z80_|execute_|ctl_sw_2u~4_combout ), + .datad(\z80_|execute_|setM1~56_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|ir_|opcode [1] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'h30F0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|pla_decode_|Equal11~0_combout & (((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (\z80_|execute_|ctl_mRead~3_combout & +// ((\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hEEC0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~13_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hFF37; +defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & (\z80_|execute_|ctl_state_alu~13_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datac(\z80_|execute_|ctl_state_alu~13_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~61_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|execute_|ixy_d~5_combout & +// !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|execute_|ctl_mRead~14_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h0357; +defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~86_combout = (\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ixy_d~5_combout & +// !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'h111F; +defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~87_combout = (\z80_|execute_|ctl_inc_cy~86_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~86_combout ), + .datab(\z80_|pla_decode_|Equal29~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h222A; +defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~52 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~52_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~52 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_bus_inc_oe~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~49 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~49_combout = (\z80_|execute_|ctl_bus_inc_oe~52_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal4~0_combout )) # (!\z80_|sequencer_|DFFE_T5_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(\z80_|execute_|ctl_bus_inc_oe~52_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal4~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~49 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_bus_inc_oe~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_inc_cy~61_combout & (\z80_|execute_|ctl_bus_inc_oe~28_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_bus_inc_oe~49_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .datac(\z80_|execute_|ctl_inc_cy~87_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|fMRead~10_combout & (\z80_|execute_|fMRead~8_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_reg_gp_we~3_combout ))) + + .dataa(\z80_|execute_|fMRead~10_combout ), + .datab(\z80_|execute_|fMRead~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = ((!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h15FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~7_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h0105; +defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|execute_|ctl_alu_oe~7_combout & (((!\z80_|execute_|ctl_mRead~25_combout & !\z80_|execute_|ctl_mRead~24_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~25_combout ), + .datac(\z80_|execute_|ctl_mRead~24_combout ), + .datad(\z80_|execute_|ctl_alu_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & (\z80_|execute_|ctl_flags_pf_we~5_combout & (\z80_|execute_|ctl_pf_sel[0]~13_combout & \z80_|execute_|ctl_alu_oe~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .datad(\z80_|execute_|ctl_alu_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_mRead~4_combout & !\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (!\z80_|pla_decode_|Equal13~2_combout & (\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|ctl_flags_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~12_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [4]), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hCCFF; +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~8_combout = (!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ctl_alu_op_low~19_combout & (\z80_|execute_|ctl_flags_hf_cpl~12_combout & !\z80_|pla_decode_|Equal68~2_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .datad(\z80_|pla_decode_|Equal68~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~8 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_flags_hf_cpl~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~48 ( +// Equation(s): +// \z80_|execute_|setM1~48_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~48 .lut_mask = 16'h0013; +defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|pla_decode_|Equal20~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h0033; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~2 ( +// Equation(s): +// \z80_|execute_|nextM~2_combout = (!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|execute_|ctl_alu_op_low~18_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0003; +defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~49 ( +// Equation(s): +// \z80_|execute_|setM1~49_combout = (\z80_|execute_|ctl_flags_hf_cpl~8_combout & (\z80_|execute_|setM1~48_combout & (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & \z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), + .datab(\z80_|execute_|setM1~48_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~49 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~12_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|setM1~49_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_flags_oe~1_combout ), + .datad(\z80_|execute_|setM1~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'h0444; +defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~8_combout = (((\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal12~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h77F7; +defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_sw_1d~8_combout ), + .datac(\z80_|execute_|ctl_sw_1d~4_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h40F0; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|execute_|ctl_mRead~24_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|execute_|ctl_mRead~24_combout & +// (((!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal20~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~24_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_mWrite~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ctl_mWrite~8_combout & +// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (!\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~25_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|nextM~11 ( +// Equation(s): +// \z80_|execute_|nextM~11_combout = ((!\z80_|execute_|ctl_alu_op_low~18_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_mWrite~5_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~11 .lut_mask = 16'h5557; +defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|execute_|ctl_alu_op_low~18_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|nextM~11_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_bus_inc_oe~51_combout & \z80_|execute_|ctl_reg_use_sp~2_combout ))) + + .dataa(\z80_|execute_|nextM~11_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~51_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal6~1_combout )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0500; +defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~13_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_sw_1d~9_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .lut_mask = 16'h0133; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~12_combout = (!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & !\z80_|pla_decode_|Equal49~0_combout )) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_oe~3_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .lut_mask = 16'h0005; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & +// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'hF010; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # (\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~30 ( +// Equation(s): +// \z80_|execute_|setM1~30_combout = (\z80_|execute_|ctl_mRead~15_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|execute_|ctl_mRead~15_combout & +// (((!\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~30 .lut_mask = 16'h0777; +defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|ctl_mRead~23_combout & (\z80_|execute_|setM1~30_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ctl_mRead~23_combout ), + .datac(\z80_|execute_|setM1~30_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~14_combout = (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((!\z80_|execute_|ctl_reg_sys_hilo~20_combout & \z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h4F00; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|execute_|ctl_mRead~5_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal2~1_combout & \z80_|pla_decode_|Equal1~4_combout )))) + + .dataa(\z80_|pla_decode_|Equal2~1_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal4~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'hF080; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~20_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .lut_mask = 16'h3332; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~21_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal11~0_combout ))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h7F00; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ) # ((\z80_|ir_|opcode [2] & ((!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .datab(\z80_|execute_|ctl_sw_2u~5_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'hBFAA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|decode_state_|DFFE_instIY1~q ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|pla_decode_|Equal50~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hEEEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_mRead~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hA2AA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ) # ((\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & ((\z80_|sequencer_|M5~q ) # (\z80_|sequencer_|DFFE_M4_ff~q )))) + + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h1110; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~36_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [6] & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [7]))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|ir_|opcode [3] & (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal12~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hA2AF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~8_combout )) # (!\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout & \z80_|execute_|ctl_ir_we~6_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_ir_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hACA0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'hB030; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N2 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~2_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~2 .lut_mask = 16'h00F0; +defparam \z80_|reg_control_|reg_sel_de2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~4_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|decode_state_|DFFE_inst4~q & !\z80_|decode_state_|DFFE_instIY1~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'h0004; +defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N12 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((!\z80_|reg_control_|bank_exx~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal2~2_combout )))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|reg_control_|bank_hl_de1~q ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hE1F0; +defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N13 +dffeas \z80_|reg_control_|bank_hl_de1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N28 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~2_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~4_combout ))))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|reg_control_|reg_sel_de2~2_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|reg_control_|bank_hl_de1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h4450; +defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal8~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~50 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~50_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~50 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_bus_inc_oe~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_bus_inc_oe~50_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~50_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & (\z80_|execute_|ctl_reg_gp_we~2_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h1500; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|execute_|ixy_d~9_combout ) # +// (!\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h0737; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h3230; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # ((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|ctl_mRead~23_combout ) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ctl_mRead~23_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'hFBF3; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (\z80_|execute_|ctl_ir_we~7_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~20_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ) # ((\z80_|execute_|ctl_iorw~11_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .datab(\z80_|execute_|ctl_iorw~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h00A0; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'h0133; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # +// (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|rsel3 ( +// Equation(s): +// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(gnd), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|rsel3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel3 .lut_mask = 16'h5AAA; +defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = (\z80_|execute_|rsel3~combout & (((\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'h08CC; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_flags_oe~1_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h040F; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~14_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFDF0; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel~7_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|rsel0 ( +// Equation(s): +// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|rsel0~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel0 .lut_mask = 16'h66AA; +defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout & ((\z80_|execute_|rsel0~combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|execute_|setM1~49_combout )))) # +// (!\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|execute_|setM1~49_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|setM1~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'h888F; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal3~1_combout & !\z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_sw_1d~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~6_combout = (!\z80_|execute_|ctl_reg_in_hi~7_combout & (\z80_|execute_|ctl_state_alu~13_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & !\z80_|execute_|ctl_reg_in_hi~12_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .datab(\z80_|execute_|ctl_state_alu~13_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'h0004; +defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~9_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~16_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_sw_1d~9_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~9 .lut_mask = 16'h070F; +defparam \z80_|execute_|ctl_reg_gp_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'h0015; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (\z80_|execute_|ctl_reg_gp_we~9_combout & \z80_|execute_|ctl_alu_sel_op2_neg~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~9_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h5155; +defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~7_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & (\z80_|execute_|ctl_reg_gp_we~5_combout & \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((!\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h31F5; +defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|ctl_sw_4u~2_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datac(\z80_|execute_|ctl_sw_4u~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~8_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (((!\z80_|execute_|ctl_sw_4u~3_combout ) # (!\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(\z80_|execute_|ctl_sw_4u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~8 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_gp_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|reg_control_|reg_sel_hl~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N16 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|reg_control_|bank_exx~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal2~2_combout )))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; +defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N17 +dffeas \z80_|reg_control_|bank_hl_de2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de2~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~2_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~4_combout )))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|reg_control_|bank_hl_de2~q ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hA820; +defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|reg_control_|reg_sel_hl2~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|reg_control_|reg_sel_hl2~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|pla_decode_|Equal52~1_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_state_alu~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout = (\z80_|sequencer_|DFFE_M3_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal3~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal24~0_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|execute_|ctl_reg_in_hi~8_combout & (!\z80_|execute_|ctl_66_oe~2_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout & \z80_|execute_|ctl_reg_gp_we~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~8_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~21_combout ) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h070F; +defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|pla_decode_|Equal6~1_combout & !\z80_|execute_|ctl_mRead~2_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_sw_2d~6_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~8_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_alu_shift_oe~44_combout & \z80_|execute_|ctl_sw_2d~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .datad(\z80_|execute_|ctl_sw_2d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h5500; +defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N4 +cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( +// Equation(s): +// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|execute_|ctl_mRead~16_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & +// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( +// Equation(s): +// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~7_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~7_combout ), + .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h0888; +defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( +// Equation(s): +// \z80_|execute_|fMRead~20_combout = (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|ctl_mWrite~10_combout & (\z80_|execute_|fMRead~18_combout & \z80_|execute_|fMRead~19_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~10_combout ), + .datac(\z80_|execute_|fMRead~18_combout ), + .datad(\z80_|execute_|fMRead~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~20 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h1115; +defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Equation(s): +// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|fMRead~20_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_in_hi~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~22_combout ), + .datab(\z80_|execute_|fMRead~20_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~21 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h20AA; +defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & (\z80_|execute_|fMRead~21_combout & \z80_|execute_|ctl_sw_2d~5_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~8_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .datac(\z80_|execute_|fMRead~21_combout ), + .datad(\z80_|execute_|ctl_sw_2d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|pla_decode_|Equal49~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hAA8A; +defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (\z80_|execute_|ctl_sw_2d~9_combout & (!\z80_|execute_|ctl_sw_1d~5_combout & \z80_|execute_|ctl_sw_1d~4_combout ))) + + .dataa(\z80_|execute_|ctl_im_we~combout ), + .datab(\z80_|execute_|ctl_sw_2d~9_combout ), + .datac(\z80_|execute_|ctl_sw_1d~5_combout ), + .datad(\z80_|execute_|ctl_sw_1d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|execute_|ctl_66_oe~2_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7733; +defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~41_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~18_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~41 .lut_mask = 16'h3BFF; +defparam \z80_|execute_|ctl_alu_op_low~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal44~0_combout & ((\z80_|ir_|opcode [0]) # (!\z80_|execute_|comb~0_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|comb~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal44~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & !\z80_|execute_|ctl_reg_gp_sel~7_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~7_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|execute_|ctl_alu_op_low~17_combout & (((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) # (!\z80_|execute_|ctl_alu_op_low~17_combout & +// (\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0155; +defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~27_combout = ((\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~20_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~26_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & ((\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~41_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hF300; +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal61~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal61~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h222A; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~12_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~12 .lut_mask = 16'h3B3F; +defparam \z80_|execute_|ctl_alu_core_hf~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_core_hf~12_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & +// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~13_combout = (((!\z80_|execute_|ixy_d~6_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_flags_sz_we~3_combout & (\z80_|execute_|ctl_flags_alu~13_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & !\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datab(\z80_|execute_|ctl_flags_alu~13_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~15_combout = (\z80_|execute_|ctl_flags_alu~14_combout & (\z80_|execute_|ctl_flags_xy_we~9_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|execute_|ctl_flags_alu~14_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|nextM~11_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~16_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~17_combout = (\z80_|execute_|ctl_alu_op_low~16_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal20~0_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'hF070; +defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .lut_mask = 16'h010F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~39_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~39 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~16_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (!\z80_|execute_|ctl_alu_op_low~39_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~39_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h020A; +defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~17_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_alu~16_combout ))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datac(\z80_|execute_|ctl_sw_2d~4_combout ), + .datad(\z80_|execute_|ctl_flags_alu~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~23_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'h0F5F; +defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~18_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_alu_op_low~23_combout & \z80_|execute_|ctl_sw_4u~1_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datab(\z80_|execute_|ctl_flags_alu~17_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~11_combout = (((!\z80_|execute_|ctl_flags_alu~10_combout ) # (!\z80_|execute_|ctl_flags_alu~22_combout )) # (!\z80_|execute_|ctl_flags_alu~20_combout )) # (!\z80_|execute_|ctl_flags_alu~21_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~21_combout ), + .datab(\z80_|execute_|ctl_flags_alu~20_combout ), + .datac(\z80_|execute_|ctl_flags_alu~22_combout ), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal1~5_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal1~5_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .lut_mask = 16'h0050; +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFFC4; +defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~23 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~23_combout = (\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~23 .lut_mask = 16'hF040; +defparam \z80_|execute_|ctl_flags_alu~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_flags_alu~11_combout ) # (((\z80_|execute_|ctl_alu_core_R~1_combout ) # (\z80_|execute_|ctl_flags_alu~23_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~3_combout )) + + .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datad(\z80_|execute_|ctl_flags_alu~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~11_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .lut_mask = 16'hF5F1; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~6_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mWrite~17_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (((!\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~17 ( +// Equation(s): +// \z80_|execute_|setM1~17_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (!\z80_|execute_|ctl_alu_shift_oe~15_combout & \z80_|execute_|ctl_state_alu~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_2u~1_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~17 .lut_mask = 16'h0C00; +defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~22_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'h0015; +defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|execute_|setM1~17_combout & (!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|setM1~17_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_alu_oe~6_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & \z80_|execute_|ctl_flags_xy_we~18_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~6_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~11_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_flags_xy_we~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~19_combout = (((\z80_|execute_|ctl_flags_alu~12_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_alu~18_combout )) # (!\z80_|execute_|ctl_flags_alu~15_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), + .datab(\z80_|execute_|ctl_flags_alu~18_combout ), + .datac(\z80_|execute_|ctl_flags_alu~12_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~19 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_alu~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFFE0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( +// Equation(s): +// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~12_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # +// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~26 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal52~0_combout )) + + .dataa(\z80_|pla_decode_|Equal44~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'hEEAA; +defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~11_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_bus~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'hF070; +defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~13_combout = ((\z80_|execute_|ctl_flags_hf2_we~combout ) # (\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|fMRead~26_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|fMRead~26_combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'hFFF3; +defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~combout = ((\z80_|execute_|ctl_flags_bus~13_combout ) # ((!\z80_|execute_|ctl_flags_bus~10_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~28_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~3_combout ) + + .dataa(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datab(\z80_|execute_|ctl_flags_bus~13_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datad(\z80_|execute_|ctl_flags_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|alu_control_|db[1]~27_combout & \z80_|execute_|ctl_flags_bus~combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .datab(\z80_|alu_control_|db[1]~27_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEFA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~12_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|nextM~11_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFEAA; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = (\z80_|execute_|ctl_alu_op_low~39_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~39_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~18_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datad(\z80_|pla_decode_|Equal48~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~18 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h0507; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_ir_we~14_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout +// & (((!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_flags_alu~20_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~18_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~18_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~25_combout ) # (\z80_|execute_|ctl_mRead~24_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~19_combout ) + + .dataa(\z80_|execute_|ctl_mRead~25_combout ), + .datab(\z80_|execute_|ctl_mRead~24_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hE0FF; +defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~24_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'h0BFF; +defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ctl_alu_op_low~24_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'h2200; +defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~17_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .lut_mask = 16'h3230; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (!\z80_|execute_|ctl_alu_op1_sel_bus~17_combout & (!\z80_|execute_|ctl_alu_op_low~20_combout & ((!\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0105; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & \z80_|execute_|ctl_alu_shift_oe~38_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|execute_|ctl_ir_we~11_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|execute_|ctl_alu_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAA20; +defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~39_combout = ((\z80_|execute_|ctl_alu_shift_oe~37_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~42_combout = ((\z80_|execute_|ctl_alu_shift_oe~40_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # (!\z80_|execute_|ctl_alu_op_low~25_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hC0C8; +defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~8_combout = (\z80_|execute_|ctl_alu_bs_oe~12_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~7_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|execute_|ctl_ir_we~7_combout & (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # +// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h7740; +defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_ir_we~10_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h5540; +defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~36_combout = ((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~1_combout ) # (!\z80_|execute_|ctl_flags_bus~10_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .datac(\z80_|execute_|ctl_flags_bus~10_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~7_combout )))) # (!\z80_|execute_|ctl_bus_db_oe~1_combout & ((\z80_|execute_|ixy_d~7_combout ) +// # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~7_combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'hF444; +defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~29_combout = ((\z80_|execute_|ctl_alu_shift_oe~24_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~28_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~44_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_ir_we~7_combout & (((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~10_combout +// & (\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'hECE0; +defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~8_combout ) # ((\z80_|pla_decode_|Equal41~2_combout & \z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~23_combout = (!\z80_|execute_|ctl_alu_bs_oe~combout & (((\z80_|execute_|ixy_d~15_combout & !\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~23_combout ))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h020F; +defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) # +// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (\z80_|execute_|ctl_sw_4u~1_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~32_combout = (\z80_|execute_|ctl_alu_shift_oe~30_combout & (\z80_|execute_|ctl_alu_shift_oe~31_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~7_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~23_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~10_combout & ((\z80_|execute_|ctl_alu_shift_oe~29_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hCCEF; +defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~17_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h88A8; +defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~18_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h7740; +defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~18_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~18_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'h5F40; +defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_alu_shift_oe~19_combout ) # (\z80_|execute_|ctl_mWrite~9_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~19_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h7470; +defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~20_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~20_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'h5C4C; +defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~22_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~21_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h0E0C; +defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~36_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~22_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & +// (((!\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~2_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & \z80_|reg_control_|reg_sys_we_lo~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_ir_we~9_combout & +// (((!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_ir_we~10_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|nM1_int~2_combout & +// (((!\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & (!\z80_|execute_|ctl_alu_oe~15_combout & \z80_|execute_|ctl_alu_res_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datac(\z80_|execute_|ctl_alu_oe~15_combout ), + .datad(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~15_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_alu_res_oe~1_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datad(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'hA0E0; +defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~0_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hEFCF; +defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~0 ( +// Equation(s): +// \z80_|alu_|db_high[3]~0_combout = (\z80_|execute_|ctl_alu_bs_oe~combout ) # (((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (\z80_|execute_|ctl_alu_op1_oe~1_combout )) # (!\z80_|execute_|ctl_alu_res_oe~2_combout )) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~0 .lut_mask = 16'hFFFB; +defparam \z80_|alu_|db_high[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'h0103; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout & (\z80_|execute_|nextM~11_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .datac(\z80_|execute_|nextM~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~53 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|pla_decode_|Equal21~1_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_sw_2u~2_combout & ((!\z80_|execute_|ctl_mRead~6_combout ) # (!\z80_|execute_|ctl_alu_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2u~0_combout ), + .datab(\z80_|execute_|ctl_sw_2u~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_sw_2u~5_combout & (\z80_|execute_|ctl_reg_gp_sel~7_combout & (\z80_|ir_|opcode [0] $ (!\z80_|execute_|comb~0_combout )))) # (!\z80_|execute_|ctl_sw_2u~5_combout & ((\z80_|ir_|opcode [0] $ +// (!\z80_|execute_|comb~0_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2u~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'hD00D; +defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFAEA; +defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~3_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|rsel3~combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7077; +defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout & (!\z80_|execute_|ctl_sw_2u~6_combout & \z80_|execute_|ctl_reg_out_hi~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .datac(\z80_|execute_|ctl_sw_2u~6_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~7_combout = ((\z80_|execute_|ctl_reg_out_hi~8_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ))) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = ((\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|execute_|setM1~47_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datab(\z80_|execute_|setM1~47_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'h7F0F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'h0EFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~30_combout ) + + .dataa(\z80_|execute_|ctl_al_we~14_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|setM1~30_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'hDF0F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & !\z80_|execute_|rsel3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFCFD; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ) # ((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hFF75; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # (!\z80_|execute_|ctl_reg_gp_we~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h2202; +defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~15_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~6_combout = ((\z80_|execute_|ctl_reg_use_sp~5_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout )) # (!\z80_|execute_|ctl_reg_use_sp~3_combout ) + + .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hFF5F; +defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N26 +cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( +// Equation(s): +// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal21~2_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N27 +dffeas \z80_|reg_control_|bank_af ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_af~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_af~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_af .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N30 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h4040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~32 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[3]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~3_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~4_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~2_combout ))))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|reg_control_|bank_hl_de2~q ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~3 .lut_mask = 16'hA280; +defparam \z80_|reg_control_|reg_sel_de2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~4_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~2_combout )))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|reg_control_|reg_sel_de2~2_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|reg_control_|bank_hl_de1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h5044; +defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_de~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_de~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~31 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[3]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_iy~2_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|decode_state_|DFFE_inst4~q & \z80_|decode_state_|DFFE_instIY1~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hCC00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h4000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h3030; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|decode_state_|DFFE_inst4~q & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h4000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~34_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~34 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~15_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # (((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout )) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~16_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ctl_sw_4u~4_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h0015; +defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~50_combout & \z80_|execute_|ctl_inc_cy~99_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_cy~50_combout ), + .datad(\z80_|execute_|ctl_inc_cy~99_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & (\z80_|execute_|fMRead~6_combout & (\z80_|execute_|ctl_reg_sel_wz~16_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .datab(\z80_|execute_|fMRead~6_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~18_combout = ((\z80_|execute_|ctl_reg_sel_wz~15_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~21_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~17_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~18_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~18_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~36_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~36 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[3]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h1000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~33 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[3]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; +defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~10_combout = (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|execute_|ctl_reg_in_hi~10_combout ) # (!\z80_|execute_|ctl_reg_in_hi~9_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout )) # (!\z80_|execute_|ctl_reg_in_hi~3_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [3] & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[3]~14_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .datad(\z80_|alu_|db[3]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~37_combout = (\z80_|reg_file_|gdfx_temp1[3]~34_combout & (\z80_|reg_file_|gdfx_temp1[3]~36_combout & (\z80_|reg_file_|gdfx_temp1[3]~33_combout & \z80_|reg_file_|gdfx_temp1[3]~35_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~37 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~38_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout & (\z80_|reg_file_|gdfx_temp1[3]~32_combout & (\z80_|reg_file_|gdfx_temp1[3]~31_combout & \z80_|reg_file_|gdfx_temp1[3]~37_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~38 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # (((\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hEAFF; +defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~6_combout = ((\z80_|execute_|ctl_sw_4u~5_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~17_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout ))) # (!\z80_|execute_|ctl_sw_4u~3_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~3_combout ), + .datab(\z80_|execute_|ctl_sw_4u~5_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFEC; +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~11_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~16_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~39_combout = ((\z80_|reg_file_|gdfx_temp1[3]~38_combout & ((\z80_|reg_file_|db_hi_as[3]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~39 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|gdfx_temp1[3]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N24 +cycloneive_lcell_comb \z80_|alu_|db[3]~13 ( +// Equation(s): +// \z80_|alu_|db[3]~13_combout = (\z80_|alu_|db_low[3]~26_combout & (((\z80_|reg_file_|gdfx_temp1[3]~39_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) # (!\z80_|alu_|db_low[3]~26_combout & (!\z80_|execute_|ctl_alu_oe~14_combout & +// ((\z80_|reg_file_|gdfx_temp1[3]~39_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) + + .dataa(\z80_|alu_|db_low[3]~26_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .datad(\z80_|execute_|ctl_alu_oe~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~13 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~20_combout ) # (\z80_|execute_|ctl_alu_shift_oe~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hEEEA; +defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~11_combout )) # (!\z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|nextM~2_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|rsel3~combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'hC444; +defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~12_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal77~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h3313; +defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_2d~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~8_combout ), + .datac(\z80_|execute_|ctl_sw_2d~10_combout ), + .datad(\z80_|execute_|ctl_sw_2d~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hF2FA; +defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~12_combout ) # ((\z80_|execute_|ctl_sw_2d~11_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~12_combout ), + .datac(\z80_|execute_|ctl_sw_2d~11_combout ), + .datad(\z80_|execute_|ctl_sw_2d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~30_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ctl_mRead~24_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datac(\z80_|execute_|ctl_mWrite~11_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|execute_|ctl_bus_db_we~5_combout & (\z80_|execute_|ctl_alu_oe~9_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|ctl_alu_oe~4_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~5_combout ), + .datab(\z80_|execute_|ctl_alu_oe~9_combout ), + .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datad(\z80_|execute_|ctl_alu_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_alu_oe~10_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .datac(\z80_|execute_|ctl_alu_oe~10_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|alu_control_|db[3]~36_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_flags_alu~19_combout )))) # (!\z80_|alu_control_|db[3]~36_combout & +// (((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_flags_alu~19_combout )))) + + .dataa(\z80_|alu_control_|db[3]~36_combout ), + .datab(\z80_|execute_|ctl_flags_bus~combout ), + .datac(\z80_|alu_|db_low[3]~26_combout ), + .datad(\z80_|execute_|ctl_flags_alu~19_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_ir_we~12_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & \z80_|pla_decode_|Equal56~0_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal56~0_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~14_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_flags_xy_we~13_combout ) # (!\z80_|execute_|ctl_flags_xy_we~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hFFCF; +defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~15_combout = (\z80_|execute_|ctl_flags_xy_we~14_combout ) # (((!\z80_|execute_|ctl_flags_xy_we~17_combout ) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) + + .dataa(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|execute_|ctl_flags_sz_we~5_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # +// (!\z80_|execute_|ctl_alu_core_R~0_combout & (\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_flags_xy_we~15_combout ) # (((!\z80_|execute_|ctl_flags_pf_we~5_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) + + .dataa(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N19 +dffeas \z80_|alu_flags_|flags_xf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_xf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_xf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~50 ( +// Equation(s): +// \z80_|execute_|setM1~50_combout = (!\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|setM1~49_combout & ((!\z80_|pla_decode_|Equal3~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|setM1~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~50 .lut_mask = 16'h0700; +defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )) # (!\z80_|execute_|setM1~50_combout ))) + + .dataa(\z80_|execute_|setM1~50_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_flags_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h3133; +defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( +// Equation(s): +// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h1333; +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( +// Equation(s): +// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) + + .dataa(\z80_|alu_flags_|flags_xf~q ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(gnd), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'hBB00; +defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N0 +cycloneive_lcell_comb \z80_|sw1_|db_down[3]~3 ( +// Equation(s): +// \z80_|sw1_|db_down[3]~3_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_sw_1d~6_combout ), + .datab(\z80_|bus_control_|db[3]~21_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[3]~3 .lut_mask = 16'hECEE; +defparam \z80_|sw1_|db_down[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h5500; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h0808; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h4400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N9 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~51_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N7 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h4040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h0008; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[3]~36_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .datad(\z80_|alu_control_|db[3]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hC4C4; +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|decode_state_|DFFE_inst4~q & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h4000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h2000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0100; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0004; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & (\z80_|reg_file_|gdfx_temp0[3]~46_combout & \z80_|reg_file_|gdfx_temp0[3]~47_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_de~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~51_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_de~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N13 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~42 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[3]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N15 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~49_combout & (\z80_|reg_file_|gdfx_temp0[3]~42_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~42_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~91 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~91_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & ((\z80_|reg_control_|reg_sel_hl2~0_combout ) # (\z80_|reg_control_|reg_sel_hl~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~91_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~91 .lut_mask = 16'h2220; +defparam \z80_|reg_file_|gdfx_temp0[0]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # (\z80_|execute_|ctl_sw_4u~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~19_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~91_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ) # (\z80_|reg_file_|gdfx_temp0[0]~20_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~91_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal11~0_combout )) # +// (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h113F; +defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~43_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & (\z80_|execute_|ctl_bus_inc_oe~42_combout & (\z80_|execute_|ctl_bus_inc_oe~28_combout & !\z80_|execute_|ctl_reg_sys_we~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~88_combout = (\z80_|execute_|ctl_inc_cy~87_combout & (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_inc_cy~87_combout ), + .datac(\z80_|execute_|ctl_sw_4u~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_inc_cy~61_combout & (\z80_|execute_|ctl_inc_cy~88_combout & \z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), + .datab(\z80_|execute_|ctl_inc_cy~88_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~38_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|fMRead~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), + .datad(\z80_|execute_|fMRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hA8AA; +defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_bus_inc_oe~38_combout ) # (((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~49_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~32_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_mRead~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|pla_decode_|Equal13~2_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~47_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((!\z80_|execute_|ctl_bus_inc_oe~34_combout ) # (!\z80_|execute_|nextM~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~48_combout = (\z80_|execute_|ctl_bus_inc_oe~47_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~37_combout & (\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'hCCEC; +defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~46_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~4_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'h00C8; +defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_bus_inc_oe~39_combout ) # (((\z80_|execute_|ctl_bus_inc_oe~48_combout ) # (\z80_|execute_|ctl_bus_inc_oe~46_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~50_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~39_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~50_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~44_combout = (((\z80_|execute_|ctl_bus_inc_oe~40_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~6_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (\z80_|execute_|ctl_apin_mux~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datad(\z80_|execute_|ctl_apin_mux~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h0700; +defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|execute_|ctl_sw_4d~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~44_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~25 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~25_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|decode_state_|in_halt~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(gnd), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~25 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|pc_inc_hold~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~67_combout = ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout ) # (\z80_|execute_|ctl_mRead~2_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~64_combout = ((!\z80_|execute_|ctl_alu_op_low~14_combout & ((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) # (!\z80_|pla_decode_|Equal10~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h1F3F; +defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~65_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ) # (!\z80_|execute_|ctl_inc_cy~64_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout )) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .datad(\z80_|execute_|ctl_inc_cy~64_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~34_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h80A0; +defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~66_combout = ((\z80_|execute_|ctl_inc_cy~65_combout ) # (\z80_|execute_|ctl_inc_cy~63_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datab(\z80_|execute_|ctl_inc_cy~65_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_cy~63_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'hFFDD; +defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~66_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~67_combout ) # (!\z80_|execute_|fMRead~7_combout )))) + + .dataa(\z80_|execute_|fMRead~7_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_inc_cy~67_combout ), + .datad(\z80_|execute_|ctl_inc_cy~66_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hFFC4; +defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~58_combout = (\z80_|execute_|ctl_mWrite~6_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ixy_d~9_combout )))) # (!\z80_|execute_|ctl_mWrite~6_combout & +// (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'hECA0; +defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_inc_cy~58_combout ) # (((\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|execute_|ctl_inc_cy~99_combout )) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|execute_|ctl_inc_cy~58_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_inc_cy~99_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'hECFF; +defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~60_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_inc_cy~59_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datad(\z80_|execute_|ctl_inc_cy~59_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|ctl_inc_cy~97_combout ) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_inc_cy~97_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hEF0F; +defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~62_combout = ((\z80_|execute_|ctl_inc_cy~60_combout ) # ((\z80_|execute_|ctl_inc_cy~57_combout ) # (!\z80_|execute_|ctl_inc_cy~47_combout ))) # (!\z80_|execute_|ctl_inc_cy~61_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), + .datab(\z80_|execute_|ctl_inc_cy~60_combout ), + .datac(\z80_|execute_|ctl_inc_cy~57_combout ), + .datad(\z80_|execute_|ctl_inc_cy~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~18 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~18_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ctl_mRead~13_combout +// & (\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~18 .lut_mask = 16'hEAC8; +defparam \z80_|execute_|pc_inc_hold~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal33~2_combout & \z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal33~2_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~17 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~17_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # (!\z80_|execute_|pc_inc_hold~14_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|pc_inc_hold~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~17 .lut_mask = 16'hECFC; +defparam \z80_|execute_|pc_inc_hold~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~19 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~19_combout = (\z80_|pla_decode_|Equal6~1_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_mRead~8_combout & +// ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~19 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|pc_inc_hold~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~20 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~20_combout = (\z80_|execute_|pc_inc_hold~18_combout ) # ((\z80_|execute_|pc_inc_hold~17_combout ) # ((\z80_|execute_|pc_inc_hold~19_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~18_combout ), + .datab(\z80_|execute_|pc_inc_hold~17_combout ), + .datac(\z80_|execute_|pc_inc_hold~19_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~20 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|pc_inc_hold~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~36_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hA080; +defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~15 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~15_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~15 .lut_mask = 16'hFF57; +defparam \z80_|execute_|pc_inc_hold~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~16 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~16_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~16 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|pc_inc_hold~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~21 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~21_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|pc_inc_hold~15_combout & \z80_|execute_|pc_inc_hold~16_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~20_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|pc_inc_hold~15_combout ), + .datad(\z80_|execute_|pc_inc_hold~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~21 .lut_mask = 16'h1000; +defparam \z80_|execute_|pc_inc_hold~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|pc_inc_hold~25_combout & (((\z80_|execute_|ctl_inc_cy~62_combout & \z80_|execute_|pc_inc_hold~21_combout )))) # (!\z80_|execute_|pc_inc_hold~25_combout & ((\z80_|execute_|ctl_inc_cy~68_combout ) # +// ((\z80_|execute_|ctl_inc_cy~62_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~25_combout ), + .datab(\z80_|execute_|ctl_inc_cy~68_combout ), + .datac(\z80_|execute_|ctl_inc_cy~62_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hF454; +defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~52_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|pla_decode_|Equal24~0_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ixy_d~10_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ixy_d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hC800; +defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~22 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~22_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~22 .lut_mask = 16'hCCC0; +defparam \z80_|execute_|pc_inc_hold~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~23 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~23_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|pc_inc_hold~22_combout )))) # +// (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|pc_inc_hold~22_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|pc_inc_hold~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~23 .lut_mask = 16'hECA0; +defparam \z80_|execute_|pc_inc_hold~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~35_combout = (\z80_|execute_|pc_inc_hold~23_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|pc_inc_hold~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'hFF80; +defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~24 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~24_combout = (!\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout & (!\z80_|execute_|pc_inc_hold~34_combout & (!\z80_|execute_|pc_inc_hold~35_combout & \z80_|execute_|pc_inc_hold~21_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .datab(\z80_|execute_|pc_inc_hold~34_combout ), + .datac(\z80_|execute_|pc_inc_hold~35_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~24 .lut_mask = 16'h0100; +defparam \z80_|execute_|pc_inc_hold~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_inc_cy~52_combout & \z80_|execute_|pc_inc_hold~24_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~52_combout ), + .datac(gnd), + .datad(\z80_|execute_|pc_inc_hold~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~54_combout = (\z80_|execute_|ctl_mWrite~17_combout & (\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_inc_cy~53_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_inc_cy~53_combout ), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'h8088; +defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~74_combout = (((!\z80_|pla_decode_|Equal33~1_combout ) # (!\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~75_combout = ((!\z80_|execute_|pc_inc_hold~17_combout & (\z80_|execute_|ctl_inc_cy~74_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ))) # (!\z80_|execute_|pc_inc_hold~25_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|ctl_inc_cy~74_combout ), + .datac(\z80_|execute_|pc_inc_hold~25_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h0F4F; +defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~73_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|execute_|ctl_sw_4u~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), + .datab(\z80_|execute_|pc_inc_hold~20_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h3020; +defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~75_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_inc_cy~73_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~95 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~95_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~95_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~95 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_inc_cy~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~72_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|pc_inc_hold~15_combout & !\z80_|execute_|ctl_inc_cy~95_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~20_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|pc_inc_hold~15_combout ), + .datad(\z80_|execute_|ctl_inc_cy~95_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~27 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~27_combout = (\z80_|execute_|pc_inc_hold~18_combout ) # ((\z80_|execute_|pc_inc_hold~17_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~18_combout ), + .datab(\z80_|execute_|pc_inc_hold~17_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~27 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|pc_inc_hold~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~77_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & (\z80_|execute_|ctl_mRead~12_combout & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~78_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~77_combout ) # ((!\z80_|execute_|pc_inc_hold~17_combout & !\z80_|execute_|ctl_reg_sys_hilo~20_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|pc_inc_hold~17_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datad(\z80_|execute_|ctl_inc_cy~77_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'hAA02; +defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout ) # ((!\z80_|execute_|pc_inc_hold~27_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~27_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|ctl_inc_cy~78_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'hFF40; +defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # ((\z80_|execute_|pc_inc_hold~25_combout & ((\z80_|execute_|pc_inc_hold~20_combout ) # (!\z80_|execute_|pc_inc_hold~15_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), + .datab(\z80_|execute_|pc_inc_hold~15_combout ), + .datac(\z80_|execute_|pc_inc_hold~25_combout ), + .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFABA; +defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~71_combout = ((!\z80_|execute_|ctl_inc_cy~64_combout & (!\z80_|execute_|pc_inc_hold~34_combout & \z80_|execute_|pc_inc_hold~21_combout ))) # (!\z80_|execute_|ctl_inc_cy~70_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~64_combout ), + .datab(\z80_|execute_|pc_inc_hold~34_combout ), + .datac(\z80_|execute_|ctl_inc_cy~70_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h1F0F; +defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~76_combout ) # ((\z80_|execute_|ctl_inc_cy~72_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout ) # (\z80_|execute_|ctl_inc_cy~71_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), + .datab(\z80_|execute_|ctl_inc_cy~72_combout ), + .datac(\z80_|execute_|ctl_inc_cy~79_combout ), + .datad(\z80_|execute_|ctl_inc_cy~71_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & ((\z80_|execute_|pc_inc_hold~24_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) # +// (!\z80_|execute_|ctl_inc_cy~94_combout & (((\z80_|execute_|pc_inc_hold~24_combout )) # (!\z80_|execute_|pc_inc_hold~25_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), + .datab(\z80_|execute_|pc_inc_hold~25_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datad(\z80_|execute_|pc_inc_hold~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hF531; +defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~26 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~26_combout = (\z80_|execute_|pc_inc_hold~34_combout ) # ((\z80_|execute_|pc_inc_hold~35_combout ) # (!\z80_|execute_|pc_inc_hold~21_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|pc_inc_hold~34_combout ), + .datac(\z80_|execute_|pc_inc_hold~35_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~26 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|pc_inc_hold~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~56_combout = (\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|pc_inc_hold~26_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~55_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'hAAEA; +defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|execute_|ctl_inc_cy~69_combout ) # ((\z80_|execute_|ctl_inc_cy~54_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~56_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), + .datab(\z80_|execute_|ctl_inc_cy~54_combout ), + .datac(\z80_|execute_|ctl_inc_cy~80_combout ), + .datad(\z80_|execute_|ctl_inc_cy~56_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~85_combout = (((!\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|ctl_inc_cy~49_combout )) # (!\z80_|execute_|ctl_inc_cy~51_combout )) # (!\z80_|execute_|ctl_inc_cy~44_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), + .datab(\z80_|execute_|ctl_inc_cy~51_combout ), + .datac(\z80_|execute_|ctl_inc_cy~49_combout ), + .datad(\z80_|execute_|ctl_inc_cy~45_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~89 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~89_combout = (\z80_|execute_|ctl_inc_cy~85_combout ) # ((!\z80_|execute_|ctl_inc_cy~48_combout ) # (!\z80_|execute_|ctl_inc_cy~88_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~85_combout ), + .datab(\z80_|execute_|ctl_inc_cy~88_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_cy~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~89_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~89 .lut_mask = 16'hBBFF; +defparam \z80_|execute_|ctl_inc_cy~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~90 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~90_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~90_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~90 .lut_mask = 16'h0515; +defparam \z80_|execute_|ctl_inc_cy~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~91 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~91_combout = (\z80_|execute_|ctl_inc_cy~89_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_inc_cy~90_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~89_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_inc_cy~90_combout ), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~91_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~91 .lut_mask = 16'hEAEE; +defparam \z80_|execute_|ctl_inc_cy~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~84_combout = ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_inc_cy~83_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_inc_cy~96_combout ) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_inc_cy~83_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_inc_cy~96_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~100 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~100_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~100_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~100 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~100 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~92 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~92_combout = (\z80_|execute_|ctl_inc_cy~84_combout ) # ((\z80_|execute_|ctl_inc_cy~91_combout & ((\z80_|execute_|ctl_inc_cy~100_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~91_combout ), + .datab(\z80_|execute_|ctl_inc_cy~84_combout ), + .datac(\z80_|execute_|ctl_inc_cy~100_combout ), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~92_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~92 .lut_mask = 16'hECEE; +defparam \z80_|execute_|ctl_inc_cy~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~28_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~9_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'hC080; +defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~82_combout = (\z80_|execute_|pc_inc_hold~24_combout & (!\z80_|execute_|pc_inc_hold~28_combout & (\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout & \z80_|execute_|ctl_inc_cy~52_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~24_combout ), + .datab(\z80_|execute_|pc_inc_hold~28_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .datad(\z80_|execute_|ctl_inc_cy~52_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((!\z80_|execute_|pc_inc_hold~33_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datad(\z80_|execute_|pc_inc_hold~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'h8AAA; +defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|pc_inc_hold~22_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|pc_inc_hold~22_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|pc_inc_hold~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hF888; +defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|pc_inc_hold~29_combout ) # ((\z80_|execute_|pc_inc_hold~30_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~33_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|pc_inc_hold~33_combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|pc_inc_hold~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hFFF2; +defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|pc_inc_hold~31_combout ) # (((\z80_|execute_|pc_inc_hold~28_combout ) # (!\z80_|execute_|pc_inc_hold~24_combout )) # (!\z80_|execute_|ctl_inc_cy~52_combout )) + + .dataa(\z80_|execute_|pc_inc_hold~31_combout ), + .datab(\z80_|execute_|ctl_inc_cy~52_combout ), + .datac(\z80_|execute_|pc_inc_hold~28_combout ), + .datad(\z80_|execute_|pc_inc_hold~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~93 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~93_combout = (\z80_|execute_|ctl_inc_cy~82_combout ) # ((\z80_|execute_|ctl_inc_cy~92_combout & ((!\z80_|execute_|pc_inc_hold~25_combout ) # (!\z80_|execute_|pc_inc_hold~32_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~92_combout ), + .datab(\z80_|execute_|ctl_inc_cy~82_combout ), + .datac(\z80_|execute_|pc_inc_hold~32_combout ), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~93_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~93 .lut_mask = 16'hCEEE; +defparam \z80_|execute_|ctl_inc_cy~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N14 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~81_combout ), + .datac(\z80_|execute_|ctl_inc_cy~93_combout ), + .datad(\z80_|address_latch_|Q [0]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h03FC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N19 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y17_N17 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal47~0_combout & !\z80_|execute_|ctl_mRead~10_combout ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~10 ( +// Equation(s): +// \z80_|alu_control_|db[0]~10_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[0]~17_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|bus_control_|db[0]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~10 .lut_mask = 16'h4C0C; +defparam \z80_|alu_control_|db[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N31 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|alu_|db[0]~18_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[0]~18_combout & (!\z80_|execute_|ctl_reg_in_hi~11_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~27_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & (\z80_|reg_file_|gdfx_temp1[0]~24_combout & \z80_|reg_file_|gdfx_temp1[0]~26_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout & \z80_|reg_file_|gdfx_temp1[0]~28_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_inc_dec~4_combout )) # (!\z80_|execute_|fIOWrite~0_combout ))) + + .dataa(\z80_|execute_|fIOWrite~0_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~9_combout = (\z80_|execute_|ctl_inc_dec~8_combout ) # (((\z80_|ir_|opcode [3] & !\z80_|execute_|ctl_reg_gp_we~2_combout )) # (!\z80_|execute_|ctl_inc_dec~3_combout )) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .datac(\z80_|execute_|ctl_inc_dec~8_combout ), + .datad(\z80_|execute_|ctl_inc_dec~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hF2FF; +defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_dec~9_combout ), + .datad(\z80_|execute_|ctl_inc_dec~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hF0FF; +defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) + + .dataa(\z80_|address_latch_|Q [4]), + .datab(\z80_|execute_|ctl_inc_dec~5_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h5595; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h5F5F; +defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~11_combout = (((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|execute_|ctl_inc_dec~5_combout ), + .datac(\z80_|execute_|ctl_inc_dec~9_combout ), + .datad(\z80_|execute_|ctl_inc_dec~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ) + + .dataa(\z80_|address_latch_|Q [2]), + .datab(gnd), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h5A5A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N5 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y17_N3 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N5 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|execute_|ctl_reg_sel_wz~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N11 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h2220; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|DFFE_instCB~q & \z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_ir_we~5_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~6_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hECCC; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~9 ( +// Equation(s): +// \z80_|alu_|db_low[2]~9_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[3]~14_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[1]~16_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[3]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~9 .lut_mask = 16'hFC0C; +defparam \z80_|alu_|db_low[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~10 ( +// Equation(s): +// \z80_|alu_|db_low[2]~10_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~9_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~12_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(\z80_|alu_|db[2]~12_combout ), + .datad(\z80_|alu_|db_low[2]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~10 .lut_mask = 16'hFD75; +defparam \z80_|alu_|db_low[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~1 ( +// Equation(s): +// \z80_|alu_|db_high[3]~1_combout = (\z80_|alu_|db_high[3]~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|db_high[3]~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~1 .lut_mask = 16'hFFF0; +defparam \z80_|alu_|db_high[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~4_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'hFFF5; +defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~10 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & (\z80_|execute_|ctl_flags_pf_we~4_combout & \z80_|execute_|ctl_flags_hf_we~5_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datac(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .lut_mask = 16'h8080; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~17 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~17_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_iorw~10_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~17 .lut_mask = 16'h0054; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~18 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~18_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|ir_|opcode [4] & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~18 .lut_mask = 16'h2030; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~38_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~38 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_alu_op_low~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~11 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout = (!\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout & (\z80_|execute_|ctl_alu_op_low~38_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .lut_mask = 16'h1050; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~12 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & ((!\z80_|pla_decode_|Equal62~2_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .lut_mask = 16'h4C00; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~15_combout & ((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # +// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_alu_core_R~2_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_S~8_combout & \z80_|execute_|ctl_alu_core_R~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|execute_|ctl_ir_we~11_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~10_combout )))) # +// (!\z80_|execute_|ctl_ir_we~7_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_ir_we~10_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~10_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h222A; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~11_combout & \z80_|execute_|ctl_alu_core_R~3_combout +// ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFCD; +defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~9_combout = ((!\z80_|execute_|ctl_alu_core_S~11_combout ) # (!\z80_|execute_|ctl_alu_core_S~5_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_core_S~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'h77FF; +defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~combout = ((\z80_|execute_|ctl_alu_core_S~9_combout ) # ((\z80_|pla_decode_|Equal62~2_combout & \z80_|pla_decode_|Equal9~0_combout ))) # (!\z80_|execute_|ctl_alu_core_S~8_combout ) + + .dataa(\z80_|pla_decode_|Equal62~2_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_alu_core_S .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal73~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hE000; +defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~combout = ((\z80_|pla_decode_|Equal73~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~5_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout ))) # (!\z80_|execute_|ctl_alu_core_R~3_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~3_combout ), + .datab(\z80_|pla_decode_|Equal73~2_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~41_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hF3F3; +defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~29_combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # (!\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_alu_op_low~16_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~34_combout & (((\z80_|pla_decode_|Equal39~0_combout & +// \z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFA88; +defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~31_combout = ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~29_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) # (!\z80_|execute_|ctl_alu_op_low~25_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((\z80_|pla_decode_|Equal40~1_combout & +// \z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'hF8C8; +defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~40_combout = (\z80_|execute_|ctl_alu_op_low~32_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~40 .lut_mask = 16'hCCEC; +defparam \z80_|execute_|ctl_alu_op_low~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~33_combout = (\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'hE000; +defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~combout = (\z80_|execute_|ctl_alu_op_low~31_combout ) # ((\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~33_combout ) # (!\z80_|execute_|ctl_alu_op_low~23_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~33_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~59 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~58 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N11 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~61_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~61 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[7]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y12_N19 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~62_combout = (\z80_|alu_|db[7]~20_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ))) # (!\z80_|alu_|db[7]~20_combout & (!\z80_|execute_|ctl_reg_in_hi~11_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .datad(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~62 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[7]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N21 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~63 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[7]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~60 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~64_combout = (\z80_|reg_file_|gdfx_temp1[7]~61_combout & (\z80_|reg_file_|gdfx_temp1[7]~62_combout & (\z80_|reg_file_|gdfx_temp1[7]~63_combout & \z80_|reg_file_|gdfx_temp1[7]~60_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~61_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~62_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~63_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~60_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~64 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~65_combout = (\z80_|reg_file_|gdfx_temp1[7]~59_combout & (\z80_|reg_file_|gdfx_temp1[7]~58_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout & \z80_|reg_file_|gdfx_temp1[7]~64_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~59_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~58_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~64_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~65 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[7]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_control_|reg_sys_we_lo~combout ) # (!\z80_|execute_|ctl_reg_sel_ir~1_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'hF700; +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~16 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~16_combout = (\z80_|reg_file_|gdfx_temp1[7]~66_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~66_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~16 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[7]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N17 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[7]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~17 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~17_combout = (\z80_|reg_file_|db_hi_as[7]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[7]~16_combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~17 .lut_mask = 16'h88AA; +defparam \z80_|reg_file_|db_hi_as[7]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N25 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N1 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [1] & ((\z80_|alu_|db[1]~16_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[1]~16_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .datad(\z80_|alu_|db[1]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~10_combout & (\z80_|reg_file_|gdfx_temp1[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~11_combout & \z80_|reg_file_|gdfx_temp1[1]~12_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~8_combout & (\z80_|reg_file_|gdfx_temp1[1]~9_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout & \z80_|reg_file_|gdfx_temp1[1]~14_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hBB00; +defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N6 +cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( +// Equation(s): +// \z80_|address_latch_|abusz [8] = (\z80_|reg_file_|db_hi_as[0]~6_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [8]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h0A0A; +defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )) # (!\z80_|execute_|ctl_al_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~14_combout ), + .datab(\z80_|execute_|ctl_al_we~5_combout ), + .datac(\z80_|execute_|ctl_apin_mux~1_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hF070; +defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~9_combout = (\z80_|execute_|ctl_al_we~13_combout & (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & +// (((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h7770; +defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~9_combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) + + .dataa(\z80_|execute_|ctl_al_we~9_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEAFF; +defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~7_combout = ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_alu_oe~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~5_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .datad(\z80_|execute_|ctl_mWrite~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~8_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_al_we~7_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )) # (!\z80_|execute_|setM1~46_combout ))) + + .dataa(\z80_|execute_|setM1~46_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_al_we~4_combout ), + .datad(\z80_|execute_|ctl_al_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~10_combout ) # ((\z80_|execute_|ctl_al_we~8_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~6_combout ), + .datab(\z80_|execute_|ctl_al_we~10_combout ), + .datac(\z80_|execute_|ctl_al_we~8_combout ), + .datad(\z80_|execute_|ctl_sw_4d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~12_combout = (\z80_|execute_|ctl_al_we~11_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|setM1~53_combout )) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_al_we~11_combout ), + .datad(\z80_|execute_|setM1~53_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hF8FF; +defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N7 +dffeas \z80_|address_latch_|Q[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [8]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y15_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~82_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~82 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[7]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N25 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~81 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[7]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~12 ( +// Equation(s): +// \z80_|alu_control_|db[6]~12_combout = ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|execute_|ctl_flags_oe~2_combout )) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) + + .dataa(gnd), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~12 .lut_mask = 16'hFFF3; +defparam \z80_|alu_control_|db[6]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|alu_|db_high[3]~7_combout & ((\z80_|execute_|ctl_flags_alu~19_combout ) # ((\z80_|alu_control_|db[7]~37_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_high[3]~7_combout & +// (((\z80_|alu_control_|db[7]~37_combout & \z80_|execute_|ctl_flags_bus~combout )))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_flags_alu~19_combout ), + .datac(\z80_|alu_control_|db[7]~37_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~3_combout ) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N11 +dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( +// Equation(s): +// \z80_|alu_control_|db[7]~18_combout = (\z80_|alu_|db[7]~20_combout & (((!\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_|db[7]~20_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((!\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h4F44; +defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~19 ( +// Equation(s): +// \z80_|alu_control_|db[7]~19_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[7]~18_combout & ((\z80_|reg_file_|gdfx_temp0[7]~90_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .datad(\z80_|alu_control_|db[7]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~19 .lut_mask = 16'h00C4; +defparam \z80_|alu_control_|db[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~20 ( +// Equation(s): +// \z80_|alu_control_|db[7]~20_combout = (\z80_|alu_control_|db[7]~19_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datab(\z80_|bus_control_|db[7]~7_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|alu_control_|db[7]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~20 .lut_mask = 16'h4F00; +defparam \z80_|alu_control_|db[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~37 ( +// Equation(s): +// \z80_|alu_control_|db[7]~37_combout = (\z80_|alu_control_|db[7]~20_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|alu_control_|db[6]~12_combout & !\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datab(\z80_|alu_control_|db[6]~12_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|alu_control_|db[7]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~37 .lut_mask = 16'hFF01; +defparam \z80_|alu_control_|db[7]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~37_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|alu_control_|db[7]~37_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~90_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|gdfx_temp0[7]~84_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .datad(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y17_N29 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|gdfx_temp0[7]~87_combout & (\z80_|reg_file_|gdfx_temp0[7]~86_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & \z80_|reg_file_|gdfx_temp0[7]~83_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|gdfx_temp0[7]~82_combout & (\z80_|reg_file_|gdfx_temp0[7]~81_combout & \z80_|reg_file_|gdfx_temp0[7]~88_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~82_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~81_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~90_combout = ((\z80_|reg_file_|gdfx_temp0[7]~89_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .datab(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8AFF; +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[7]~90_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .datab(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) + + .dataa(gnd), + .datab(\z80_|address_latch_|Q [7]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h33CC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'h8AFF; +defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( +// Equation(s): +// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [7]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N3 +dffeas \z80_|address_latch_|Q[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [7]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [8] & !\z80_|address_latch_|Q +// [7])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [8] & \z80_|address_latch_|Q [7])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [8]), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h2008; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N18 +cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( +// Equation(s): +// \z80_|address_latch_|abusz [9] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[1]~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [9]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N19 +dffeas \z80_|address_latch_|Q[9] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [9]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y16_N21 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [2] & ((\z80_|alu_|db[2]~12_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[2]~12_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~44 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[2]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N17 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~45_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~45 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[2]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~42 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~43_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~43 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[2]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~46_combout = (\z80_|reg_file_|gdfx_temp1[2]~44_combout & (\z80_|reg_file_|gdfx_temp1[2]~45_combout & (\z80_|reg_file_|gdfx_temp1[2]~42_combout & \z80_|reg_file_|gdfx_temp1[2]~43_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~46 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~48_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~40 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~41 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~47_combout = (\z80_|reg_file_|gdfx_temp1[2]~46_combout & (\z80_|reg_file_|gdfx_temp1[2]~40_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout & \z80_|reg_file_|gdfx_temp1[2]~41_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~47 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~48_combout = ((\z80_|reg_file_|gdfx_temp1[2]~47_combout & ((\z80_|reg_file_|db_hi_as[2]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~48 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp1[2]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~10 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [2] & ((\z80_|reg_file_|gdfx_temp1[2]~48_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[2]~48_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~10 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|db_hi_as[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~11 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~11_combout = (\z80_|reg_file_|db_hi_as[2]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[2]~10_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~11 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|db_hi_as[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N22 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ +// (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [10]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~12 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~12_combout = ((\z80_|reg_file_|db_hi_as[2]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|reg_file_|db_hi_as[2]~11_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~12 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|db_hi_as[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N0 +cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( +// Equation(s): +// \z80_|address_latch_|abusz [10] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[2]~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [10]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N1 +dffeas \z80_|address_latch_|Q[10] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [10]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [9] & (!\z80_|execute_|ctl_inc_dec~11_combout & +// \z80_|address_latch_|Q [10])) # (!\z80_|address_latch_|Q [9] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [10])))) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [10]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h2400; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~50 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~49 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~51_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~51 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~52_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~52 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[4]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N8 +cycloneive_lcell_comb \z80_|alu_|db[4]~8 ( +// Equation(s): +// \z80_|alu_|db[4]~8_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~57_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[4]~33_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[4]~33_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~8 .lut_mask = 16'hF351; +defparam \z80_|alu_|db[4]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N2 +cycloneive_lcell_comb \z80_|alu_|db[4]~10 ( +// Equation(s): +// \z80_|alu_|db[4]~10_combout = ((\z80_|alu_|db[4]~8_combout & ((\z80_|alu_|db_high[0]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[4]~8_combout ), + .datad(\z80_|alu_|db_high[0]~25_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~10 .lut_mask = 16'hF575; +defparam \z80_|alu_|db[4]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~53_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [4] & ((\z80_|alu_|db[4]~10_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[4]~10_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .datad(\z80_|alu_|db[4]~10_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~53 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N25 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~54_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~54 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[4]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~55_combout = (\z80_|reg_file_|gdfx_temp1[4]~51_combout & (\z80_|reg_file_|gdfx_temp1[4]~52_combout & (\z80_|reg_file_|gdfx_temp1[4]~53_combout & \z80_|reg_file_|gdfx_temp1[4]~54_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~51_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~52_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~53_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~54_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~55 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~56_combout = (\z80_|reg_file_|gdfx_temp1[4]~50_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout & (\z80_|reg_file_|gdfx_temp1[4]~49_combout & \z80_|reg_file_|gdfx_temp1[4]~55_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~50_combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~49_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~55_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~56 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~57_combout = ((\z80_|reg_file_|gdfx_temp1[4]~56_combout & ((\z80_|reg_file_|db_hi_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~56_combout ), + .datac(\z80_|reg_file_|db_hi_as[4]~15_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~57 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|gdfx_temp1[4]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[4]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~13 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~13_combout = (\z80_|reg_file_|gdfx_temp1[4]~57_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[4]~57_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~13 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[4]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[4]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~14 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~14_combout = (\z80_|reg_file_|db_hi_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[4]~13_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~14 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|db_hi_as[4]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N14 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ +// (\z80_|address_latch_|Q [11]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [12]), + .datad(\z80_|address_latch_|Q [11]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hD278; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~15 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~15_combout = ((\z80_|reg_file_|db_hi_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datab(\z80_|reg_file_|db_hi_as[4]~14_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~15 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|db_hi_as[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N12 +cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( +// Equation(s): +// \z80_|address_latch_|abusz [12] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[4]~15_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(\z80_|reg_file_|db_hi_as[4]~15_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [12]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h3030; +defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N13 +dffeas \z80_|address_latch_|Q[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [12]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [12] & +// !\z80_|address_latch_|Q [11])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [12] & \z80_|address_latch_|Q [11])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [12]), + .datad(\z80_|address_latch_|Q [11]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2008; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h55AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[5]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~76 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[5]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~77 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[5]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~84_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~79_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~79 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[5]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op_low~23_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_alu_oe~3_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (((\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_66_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h0088; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFCC; +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N25 +dffeas \z80_|alu_|op1_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h00A0; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_zero~combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~18 ( +// Equation(s): +// \z80_|alu_|db_low[1]~18_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~12_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~18 .lut_mask = 16'hFA0A; +defparam \z80_|alu_|db_low[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~19 ( +// Equation(s): +// \z80_|alu_|db_low[1]~19_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[1]~18_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[1]~16_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[1]~16_combout ), + .datac(\z80_|alu_|db_low[1]~18_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~19 .lut_mask = 16'hF0CC; +defparam \z80_|alu_|db_low[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( +// Equation(s): +// \z80_|alu_|db_low[1]~16_combout = (\z80_|alu_|op1_low [1] & (((\z80_|alu_|op2_low [1])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_low [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [1]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_low [1]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op2_low [1]), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hAF23; +defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( +// Equation(s): +// \z80_|alu_|db_low[1]~15_combout = ((\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'h0F2F; +defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N27 +dffeas \z80_|alu_|result_lo[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N26 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( +// Equation(s): +// \z80_|alu_|db_low[1]~17_combout = (\z80_|alu_|db_low[1]~16_combout & (\z80_|alu_|db_low[1]~15_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) + + .dataa(\z80_|alu_|db_low[1]~16_combout ), + .datab(\z80_|alu_|db_low[1]~15_combout ), + .datac(\z80_|alu_|result_lo [1]), + .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'h8880; +defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~20 ( +// Equation(s): +// \z80_|alu_|db_low[1]~20_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[1]~19_combout & ((\z80_|alu_|db_low[1]~17_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~17_combout ) # +// (!\z80_|alu_|db_high[3]~0_combout )))) + + .dataa(\z80_|alu_|db_low[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[3]~0_combout ), + .datad(\z80_|alu_|db_low[1]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~20 .lut_mask = 16'hBB03; +defparam \z80_|alu_|db_low[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & \z80_|alu_|db_low[1]~20_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|alu_|db_low[1]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'hF000; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hAE00; +defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[1]~19_combout )))) + + .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|alu_|db_high[1]~19_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .lut_mask = 16'h00EA; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFFFC; +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N21 +dffeas \z80_|alu_|op1_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'hCE00; +defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [1]), + .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'hE200; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[1]~20_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .datad(\z80_|alu_|db_low[1]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h3230; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # (\z80_|execute_|ctl_alu_op2_sel_zero~combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFEFE; +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N9 +dffeas \z80_|alu_|op2_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~14_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y6_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout )) # (!\z80_|execute_|ctl_alu_op_low~41_combout +// )) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~10_combout & (\z80_|execute_|ctl_flags_alu~21_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & \z80_|execute_|ctl_alu_core_S~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datab(\z80_|execute_|ctl_flags_alu~21_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ) # ((!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ) # (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~2_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout +// )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFBF3; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout = (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[1]~20_combout )))) # +// (!\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[1]~20_combout )))) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datad(\z80_|alu_|db_low[1]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N11 +dffeas \z80_|alu_|op2_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~25_combout ) # (\z80_|execute_|ctl_mRead~24_combout )))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) + + .dataa(\z80_|execute_|ctl_mRead~25_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'hCF8F; +defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N16 +cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~2 ( +// Equation(s): +// \z80_|alu_|alu_op2[1]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [1]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [1])))) + + .dataa(\z80_|alu_|op2_low [1]), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|alu_|op2_high [1]), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[1]~2 .lut_mask = 16'h3C66; +defparam \z80_|alu_|alu_op2[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[1]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|alu_|alu_op2[1]~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hC808; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[1]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high +// [1])))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|alu_|alu_op2[1]~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0131; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hF1F1; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & (!\z80_|execute_|ctl_alu_core_S~combout & +// !\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h3337; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ) # +// ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'h3F0A; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & (\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_bus~16_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h3000; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N29 +dffeas \z80_|alu_|op1_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout = (\z80_|alu_|db_high[2]~13_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[2]~14_combout )))) # +// (!\z80_|alu_|db_high[2]~13_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[2]~14_combout )))) + + .dataa(\z80_|alu_|db_high[2]~13_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datad(\z80_|alu_|db_low[2]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h0A0A; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N3 +dffeas \z80_|alu_|op2_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( +// Equation(s): +// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op2_high [2]), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hAF23; +defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~8 ( +// Equation(s): +// \z80_|alu_|db_high[2]~8_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db[7]~20_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~8 .lut_mask = 16'hCFC0; +defparam \z80_|alu_|db_high[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( +// Equation(s): +// \z80_|alu_|db_high[2]~9_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[2]~8_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[6]~22_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(\z80_|alu_|db[6]~22_combout ), + .datad(\z80_|alu_|db_high[2]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'hFD75; +defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( +// Equation(s): +// \z80_|alu_|db_high[2]~11_combout = (!\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[4]~19_combout )) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'h4400; +defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( +// Equation(s): +// \z80_|alu_|db_high[2]~12_combout = (\z80_|alu_|db_high[2]~10_combout & (\z80_|alu_|db_high[2]~9_combout & ((\z80_|alu_|db_high[2]~11_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|alu_|db_high[2]~10_combout ), + .datac(\z80_|alu_|db_high[2]~9_combout ), + .datad(\z80_|alu_|db_high[2]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hC040; +defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( +// Equation(s): +// \z80_|alu_|db_high[2]~13_combout = ((\z80_|alu_|db_high[2]~12_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_high[2]~12_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hBBB3; +defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~68 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~75_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~67 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N25 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N19 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~72 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~70 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~69 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~71_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [6] & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .datad(\z80_|alu_|db[6]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~71 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~73_combout = (\z80_|reg_file_|gdfx_temp1[6]~72_combout & (\z80_|reg_file_|gdfx_temp1[6]~70_combout & (\z80_|reg_file_|gdfx_temp1[6]~69_combout & \z80_|reg_file_|gdfx_temp1[6]~71_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~73 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~74_combout = (\z80_|reg_file_|gdfx_temp1[6]~68_combout & (\z80_|reg_file_|gdfx_temp1[6]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout & \z80_|reg_file_|gdfx_temp1[6]~73_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~74 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N26 +cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( +// Equation(s): +// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~21_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h3300; +defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N27 +dffeas \z80_|address_latch_|Q[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [14]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datac(\z80_|address_latch_|Q [14]), + .datad(\z80_|execute_|ctl_inc_dec~11_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'hB478; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~19 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp1[6]~75_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[6]~75_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~19 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~20_combout = (\z80_|reg_file_|db_hi_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~19_combout ), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~20 .lut_mask = 16'hF030; +defparam \z80_|reg_file_|db_hi_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~21_combout = ((\z80_|reg_file_|db_hi_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[6]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~21 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_hi_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~75_combout = ((\z80_|reg_file_|gdfx_temp1[6]~74_combout & ((\z80_|reg_file_|db_hi_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~75 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|gdfx_temp1[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N16 +cycloneive_lcell_comb \z80_|alu_|db[6]~21 ( +// Equation(s): +// \z80_|alu_|db[6]~21_combout = (\z80_|alu_control_|db[6]~23_combout & (((\z80_|reg_file_|gdfx_temp1[6]~75_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[6]~23_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[6]~75_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) + + .dataa(\z80_|alu_control_|db[6]~23_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~21 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N26 +cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( +// Equation(s): +// \z80_|alu_|db[6]~22_combout = ((\z80_|alu_|db[6]~21_combout & ((\z80_|alu_|db_high[2]~13_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|alu_|db[6]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF755; +defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( +// Equation(s): +// \z80_|alu_|db_high[1]~16_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_|db[6]~22_combout ), + .datad(\z80_|alu_|db[4]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hF3C0; +defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( +// Equation(s): +// \z80_|alu_|db_high[1]~17_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[1]~16_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[5]~24_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datad(\z80_|alu_|db_high[1]~16_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hFC0C; +defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~14 ( +// Equation(s): +// \z80_|alu_|db_high[1]~14_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[4]~19_combout ), + .datab(\z80_|bus_control_|db[3]~21_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~14 .lut_mask = 16'h4F0F; +defparam \z80_|alu_|db_high[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( +// Equation(s): +// \z80_|alu_|db_high[1]~15_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [1]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_high [1]), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( +// Equation(s): +// \z80_|alu_|db_high[1]~18_combout = (\z80_|alu_|db_high[1]~14_combout & (\z80_|alu_|db_high[1]~15_combout & ((\z80_|alu_|db_high[1]~17_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[1]~17_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[1]~14_combout ), + .datad(\z80_|alu_|db_high[1]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hB000; +defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( +// Equation(s): +// \z80_|alu_|db_high[1]~19_combout = ((\z80_|alu_|db_high[1]~18_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datac(\z80_|alu_|db_high[1]~18_combout ), + .datad(\z80_|alu_|db_high[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'hE0FF; +defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N4 +cycloneive_lcell_comb \z80_|alu_|db[5]~23 ( +// Equation(s): +// \z80_|alu_|db[5]~23_combout = (\z80_|reg_file_|gdfx_temp1[5]~84_combout & (((\z80_|alu_control_|db[5]~17_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) # (!\z80_|reg_file_|gdfx_temp1[5]~84_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[5]~17_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[5]~17_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~23 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db[5]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N10 +cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( +// Equation(s): +// \z80_|alu_|db[5]~24_combout = ((\z80_|alu_|db[5]~23_combout & ((\z80_|alu_|db_high[1]~19_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[5]~23_combout ), + .datad(\z80_|alu_|db[7]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hB0FF; +defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~80_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [5] & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[5]~24_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~80 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[5]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~81_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~81 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[5]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~78 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[5]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~82_combout = (\z80_|reg_file_|gdfx_temp1[5]~79_combout & (\z80_|reg_file_|gdfx_temp1[5]~80_combout & (\z80_|reg_file_|gdfx_temp1[5]~81_combout & \z80_|reg_file_|gdfx_temp1[5]~78_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~79_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~80_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~81_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~78_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~82 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~83_combout = (\z80_|reg_file_|gdfx_temp1[5]~76_combout & (\z80_|reg_file_|gdfx_temp1[5]~77_combout & (\z80_|reg_file_|gdfx_temp1[5]~82_combout & \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~76_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~77_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~82_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~83 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~84_combout = ((\z80_|reg_file_|gdfx_temp1[5]~83_combout & ((\z80_|reg_file_|db_hi_as[5]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[5]~24_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~83_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~84 .lut_mask = 16'h8CFF; +defparam \z80_|reg_file_|gdfx_temp1[5]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[5]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~22 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~22_combout = (\z80_|reg_file_|gdfx_temp1[5]~84_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[5]~84_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~22 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[5]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~23 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~23_combout = (\z80_|reg_file_|db_hi_as[5]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .datab(\z80_|reg_file_|db_hi_as[5]~22_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~23 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_hi_as[5]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~24 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~24_combout = ((\z80_|reg_file_|db_hi_as[5]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[5]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~24 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_hi_as[5]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N20 +cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( +// Equation(s): +// \z80_|address_latch_|abusz [13] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[5]~24_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(\z80_|reg_file_|db_hi_as[5]~24_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [13]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h3030; +defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N21 +dffeas \z80_|address_latch_|Q[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [13]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q [13]) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [13]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h3C3C; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N6 +cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( +// Equation(s): +// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~18_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[7]~18_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h00AA; +defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N7 +dffeas \z80_|address_latch_|Q[15] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [15]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|address_latch_|Q [14]), + .datac(\z80_|execute_|ctl_inc_dec~7_combout ), + .datad(\z80_|execute_|ctl_inc_dec~6_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h3633; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N8 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~18 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~18_combout = ((\z80_|reg_file_|db_hi_as[7]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|reg_file_|db_hi_as[7]~17_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~18 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|db_hi_as[7]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~66_combout = ((\z80_|reg_file_|gdfx_temp1[7]~65_combout & ((\z80_|reg_file_|db_hi_as[7]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~65_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_hi_as[7]~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~66 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp1[7]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N4 +cycloneive_lcell_comb \z80_|alu_|db[7]~19 ( +// Equation(s): +// \z80_|alu_|db[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~66_combout & (((\z80_|alu_control_|db[7]~37_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~66_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[7]~37_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~19 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N18 +cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( +// Equation(s): +// \z80_|alu_|db[7]~20_combout = ((\z80_|alu_|db[7]~19_combout & ((\z80_|alu_|db_high[3]~7_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[7]~19_combout ), + .datad(\z80_|alu_|db_high[3]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hF575; +defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N8 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (((\z80_|alu_|db[7]~20_combout & \z80_|ir_|opcode [3])))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) # (!\z80_|ir_|opcode [3] & +// ((\z80_|alu_|db[7]~20_combout ))))) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|alu_|db[7]~20_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hE230; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((\z80_|alu_|db_low[3]~8_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_low[3]~8_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|alu_|db_high[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'hC0D0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 .lut_mask = 16'h00F8; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N5 +dffeas \z80_|alu_|op1_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|alu_|db_high[3]~7_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h0088; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N11 +dffeas \z80_|alu_|op1_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N18 +cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~0 ( +// Equation(s): +// \z80_|alu_|alu_op1[3]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [3]))) + + .dataa(\z80_|alu_|op1_low [3]), + .datab(\z80_|alu_|op1_high [3]), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[3]~0 .lut_mask = 16'hAACC; +defparam \z80_|alu_|alu_op1[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (\z80_|alu_|db_low[2]~14_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # +// (!\z80_|alu_|db_low[2]~14_combout & (\z80_|alu_|db_high[2]~13_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|alu_|db_low[2]~14_combout ), + .datab(\z80_|alu_|db_high[2]~13_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N7 +dffeas \z80_|alu_|op1_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [2]))))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|alu_|op1_high [2]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .lut_mask = 16'h88A0; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[2]~14_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|alu_|db_low[2]~14_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .lut_mask = 16'h0F08; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N31 +dffeas \z80_|alu_|op2_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N0 +cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~1 ( +// Equation(s): +// \z80_|alu_|alu_op2[2]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) + + .dataa(\z80_|alu_|op2_high [2]), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datad(\z80_|alu_|op2_low [2]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[2]~1 .lut_mask = 16'h636C; +defparam \z80_|alu_|alu_op2[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [2]))))) + + .dataa(\z80_|alu_|op1_low [2]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_high [2]), + .datad(\z80_|alu_|alu_op2[2]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0047; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[2]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) + + .dataa(\z80_|alu_|alu_op2[2]~1_combout ), + .datab(\z80_|alu_|op1_high [2]), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hA088; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_S~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFF0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hAAFB; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op1[3]~0_combout & ((\z80_|alu_|alu_op2[3]~0_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ))) # +// (!\z80_|alu_|alu_op1[3]~0_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & \z80_|alu_|alu_op2[3]~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(\z80_|alu_|alu_op1[3]~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_|alu_op2[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hEFAE; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout & (\z80_|execute_|ctl_flags_alu~19_combout & !\z80_|execute_|ctl_alu_core_R~combout )) + + .dataa(gnd), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|execute_|ctl_flags_alu~19_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'h00C0; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[0]~14_combout )) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datac(gnd), + .datad(\z80_|alu_control_|db[0]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hEECC; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~4_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) + + .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_bus~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hBAFA; +defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~6_combout = (\z80_|execute_|ctl_flags_cf_we~3_combout ) # (((\z80_|execute_|ctl_flags_cf_we~5_combout ) # (!\z80_|execute_|ctl_flags_hf_we~2_combout )) # (!\z80_|execute_|ctl_flags_cf_we~2_combout )) + + .dataa(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datac(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~4_combout = ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal0~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal0~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~6 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_cf2_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~5_combout = (\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~6_combout ) # ((\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_we~6_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~5 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_flags_cf2_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~5_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~5_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'hF0B8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N21 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N2 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h20A8; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N30 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((!\z80_|ir_|opcode [4] & \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout )) + + .dataa(\z80_|ir_|opcode [4]), + .datab(gnd), + .datac(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hFF50; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( +// Equation(s): +// \z80_|alu_|db_low[0]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_|db[1]~16_combout ), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hF3C0; +defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( +// Equation(s): +// \z80_|alu_|db_low[0]~22_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[0]~21_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[0]~18_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datab(\z80_|alu_|db[0]~18_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[0]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hEF4F; +defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|db_high[0]~25_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & \z80_|alu_|db_low[0]~27_combout )))) # +// (!\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & (\z80_|alu_|db_low[0]~27_combout ))) + + .dataa(\z80_|alu_|db_high[0]~25_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(\z80_|alu_|db_low[0]~27_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N31 +dffeas \z80_|alu_|op1_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~24 ( +// Equation(s): +// \z80_|alu_|db_low[0]~24_combout = (\z80_|alu_|op2_low [0] & (((\z80_|alu_|op1_low [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_low [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [0]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op1_low [0]), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~24 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_low[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N23 +dffeas \z80_|alu_|result_lo[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( +// Equation(s): +// \z80_|alu_|db_low[0]~23_combout = ((!\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'h0F1F; +defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~25 ( +// Equation(s): +// \z80_|alu_|db_low[0]~25_combout = (\z80_|alu_|db_low[0]~24_combout & (\z80_|alu_|db_low[0]~23_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [0])))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(\z80_|alu_|db_low[0]~24_combout ), + .datac(\z80_|alu_|result_lo [0]), + .datad(\z80_|alu_|db_low[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~25 .lut_mask = 16'hC800; +defparam \z80_|alu_|db_low[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~27 ( +// Equation(s): +// \z80_|alu_|db_low[0]~27_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[0]~22_combout & (\z80_|alu_|db_low[0]~25_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[0]~22_combout & +// \z80_|alu_|db_low[0]~25_combout )) # (!\z80_|alu_|db_high[3]~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_low[0]~22_combout ), + .datac(\z80_|alu_|db_low[0]~25_combout ), + .datad(\z80_|alu_|db_high[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~27 .lut_mask = 16'hC0D5; +defparam \z80_|alu_|db_low[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])))) + + .dataa(\z80_|alu_|op1_high [0]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [0]), + .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hE200; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[0]~27_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|alu_|db_low[0]~27_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h0F08; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N15 +dffeas \z80_|alu_|op2_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_high[0]~25_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[0]~27_combout )))) # +// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[0]~27_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|db_high[0]~25_combout ), + .datad(\z80_|alu_|db_low[0]~27_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N17 +dffeas \z80_|alu_|op2_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N10 +cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( +// Equation(s): +// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|alu_|op2_high [0]), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h1DE2; +defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_R~3_combout )) # +// (!\z80_|execute_|ctl_alu_core_S~8_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h1FFF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~34_combout = (((\z80_|execute_|ctl_alu_op_low~29_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_alu_op_low~41_combout )) # (!\z80_|execute_|ctl_alu_op_low~25_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~36_combout = (\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~36 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|ctl_alu_op_low~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~35_combout = (\z80_|execute_|ctl_alu_op_low~33_combout ) # ((\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~33_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~35 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op_low~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~13_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~13 .lut_mask = 16'hD0C0; +defparam \z80_|execute_|ctl_alu_core_hf~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~14_combout = (\z80_|ir_|opcode [5]) # (((!\z80_|pla_decode_|Equal9~0_combout & !\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout )) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~14 .lut_mask = 16'hCFDF; +defparam \z80_|execute_|ctl_alu_core_hf~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~15_combout = (\z80_|execute_|ctl_alu_core_hf~14_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~15 .lut_mask = 16'h8CCC; +defparam \z80_|execute_|ctl_alu_core_hf~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~16_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~15_combout )) # (!\z80_|execute_|ctl_alu_core_hf~12_combout ) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~16 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|ctl_alu_core_hf~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~17_combout = (\z80_|execute_|ctl_alu_op_low~36_combout & (!\z80_|execute_|ctl_alu_op_low~35_combout & ((\z80_|execute_|ctl_alu_core_hf~16_combout )))) # (!\z80_|execute_|ctl_alu_op_low~36_combout & +// ((\z80_|execute_|ctl_alu_core_hf~13_combout ) # ((!\z80_|execute_|ctl_alu_op_low~35_combout & \z80_|execute_|ctl_alu_core_hf~16_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~36_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~13_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~17 .lut_mask = 16'h7350; +defparam \z80_|execute_|ctl_alu_core_hf~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|execute_|ixy_d~6_combout ) # ((!\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ixy_d~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hF3F0; +defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout & !\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'h88C8; +defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ctl_alu_op_low~18_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~23_combout = (!\z80_|execute_|ctl_alu_op_low~27_combout & ((\z80_|execute_|ctl_alu_core_hf~36_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|execute_|ctl_alu_op_low~17_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h0E0A; +defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~34_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'h1333; +defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~29_combout = (\z80_|execute_|ctl_mRead~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((!\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'hB0A0; +defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|execute_|ctl_mRead~4_combout +// & (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal56~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_alu_op_low~17_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((\z80_|execute_|ixy_d~7_combout ) # (\z80_|execute_|ctl_alu_core_hf~35_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & +// (((\z80_|execute_|ctl_alu_core_hf~35_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'h7740; +defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~28_combout = (\z80_|execute_|ctl_alu_core_hf~26_combout & ((\z80_|execute_|ctl_alu_core_hf~27_combout ) # ((\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'hAA80; +defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~34_combout & ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # (\z80_|execute_|ctl_alu_core_hf~28_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~37_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (((\z80_|execute_|ctl_alu_op_low~20_combout ) # (!\z80_|execute_|ctl_state_alu~11_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|execute_|ctl_state_alu~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~37 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_op_low~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_state_alu~2_combout & (((\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # +// (\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'hFC20; +defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~25_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (!\z80_|execute_|ctl_alu_op_low~20_combout & ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_alu_core_hf~24_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'h0032; +defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~31_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((\z80_|execute_|ctl_alu_core_hf~25_combout ) # ((\z80_|execute_|ctl_alu_core_hf~30_combout & !\z80_|execute_|ctl_alu_op_low~37_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~37_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'hFFAE; +defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~20_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hD0C0; +defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~20_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hCEEE; +defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~18_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~18_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~22_combout = (\z80_|execute_|ctl_alu_op_low~34_combout & (((!\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_alu_core_hf~19_combout )))) # (!\z80_|execute_|ctl_alu_op_low~34_combout & +// ((\z80_|execute_|ctl_alu_core_hf~21_combout ) # ((!\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_alu_core_hf~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'h4F44; +defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((\z80_|execute_|ctl_alu_core_hf~22_combout ) # ((\z80_|execute_|ctl_alu_core_hf~38_combout & !\z80_|execute_|ctl_alu_op_low~31_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hFCFE; +defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~33_combout = (\z80_|execute_|ctl_alu_core_hf~17_combout ) # ((\z80_|execute_|ctl_alu_core_hf~32_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N20 +cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( +// Equation(s): +// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~33_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~33_combout & (\z80_|alu_flags_|flags_cf~combout )) + + .dataa(\z80_|alu_flags_|flags_cf~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .datad(\z80_|alu_flags_|flags_hf~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hFA0A; +defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[0]~1_combout & \z80_|alu_control_|alu_core_cf_in~0_combout )))) +// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_control_|alu_core_cf_in~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[0]~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_|alu_op1[0]~1_combout ), + .datad(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( +// Equation(s): +// \z80_|alu_|db_high[0]~21_combout = (\z80_|alu_|op2_high [0] & (((\z80_|alu_|op1_high [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_high [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [0]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|alu_|op2_high [0]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|alu_|op1_high [0]), + .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N16 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( +// Equation(s): +// \z80_|alu_|db_high[0]~22_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~14_combout )) + + .dataa(\z80_|ir_|opcode [3]), + .datab(gnd), + .datac(\z80_|alu_|db[3]~14_combout ), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hFA50; +defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N2 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( +// Equation(s): +// \z80_|alu_|db_high[0]~23_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[0]~22_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[4]~10_combout )) + + .dataa(\z80_|alu_|db[4]~10_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(gnd), + .datad(\z80_|alu_|db_high[0]~22_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hEE22; +defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~20 ( +// Equation(s): +// \z80_|alu_|db_high[0]~20_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[4]~19_combout ), + .datab(\z80_|bus_control_|db[3]~21_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~20 .lut_mask = 16'h1F0F; +defparam \z80_|alu_|db_high[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( +// Equation(s): +// \z80_|alu_|db_high[0]~24_combout = (\z80_|alu_|db_high[0]~21_combout & (\z80_|alu_|db_high[0]~20_combout & ((\z80_|alu_|db_high[0]~23_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[0]~21_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[0]~23_combout ), + .datad(\z80_|alu_|db_high[0]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hA200; +defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( +// Equation(s): +// \z80_|alu_|db_high[0]~25_combout = ((\z80_|alu_|db_high[0]~24_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datac(\z80_|alu_|db_high[0]~24_combout ), + .datad(\z80_|alu_|db_high[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'hE0FF; +defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(\z80_|alu_|db_high[0]~25_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h0088; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N23 +dffeas \z80_|alu_|op1_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( +// Equation(s): +// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_high [0]), + .datad(\z80_|alu_|op1_low [0]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hFC30; +defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|alu_|op2_high [0]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hE2E2; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_|alu_op1[0]~1_combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|alu_|alu_op1[0]~1_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hBE28; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|execute_|ctl_alu_core_R~combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|execute_|ctl_alu_core_S~combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(\z80_|execute_|ctl_alu_core_R~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h0032; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h0F0E; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55F7; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hF2A2; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N19 +dffeas \z80_|alu_|result_lo[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~11 ( +// Equation(s): +// \z80_|alu_|db_low[2]~11_combout = (\z80_|alu_|result_lo [2]) # (\z80_|execute_|ctl_alu_res_oe~2_combout ) + + .dataa(gnd), + .datab(\z80_|alu_|result_lo [2]), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~11 .lut_mask = 16'hFFCC; +defparam \z80_|alu_|db_low[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N2 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~12 ( +// Equation(s): +// \z80_|alu_|db_low[2]~12_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [2] & ((\z80_|alu_|op2_low [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [2]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_low [2]), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~12 .lut_mask = 16'hDD0D; +defparam \z80_|alu_|db_low[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h5500; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~13 ( +// Equation(s): +// \z80_|alu_|db_low[2]~13_combout = (\z80_|alu_|db_low[2]~12_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|alu_|db_low[2]~12_combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~13 .lut_mask = 16'h7050; +defparam \z80_|alu_|db_low[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N28 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~14 ( +// Equation(s): +// \z80_|alu_|db_low[2]~14_combout = ((\z80_|alu_|db_low[2]~10_combout & (\z80_|alu_|db_low[2]~11_combout & \z80_|alu_|db_low[2]~13_combout ))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_low[2]~10_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|alu_|db_low[2]~11_combout ), + .datad(\z80_|alu_|db_low[2]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~14 .lut_mask = 16'hB333; +defparam \z80_|alu_|db_low[2]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N24 +cycloneive_lcell_comb \z80_|alu_|db[2]~11 ( +// Equation(s): +// \z80_|alu_|db[2]~11_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[2]~48_combout & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[2]~30_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .datad(\z80_|alu_control_|db[2]~30_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~11 .lut_mask = 16'hF531; +defparam \z80_|alu_|db[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N22 +cycloneive_lcell_comb \z80_|alu_|db[2]~12 ( +// Equation(s): +// \z80_|alu_|db[2]~12_combout = ((\z80_|alu_|db[2]~11_combout & ((\z80_|alu_|db_low[2]~14_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db_low[2]~14_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[2]~11_combout ), + .datad(\z80_|alu_|db[7]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~12 .lut_mask = 16'hB0FF; +defparam \z80_|alu_|db[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( +// Equation(s): +// \z80_|alu_control_|db[2]~28_combout = (\z80_|alu_|db[2]~12_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~q & ((\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_|db[2]~12_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((!\z80_|alu_flags_|DFFE_inst_latch_pf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_|db[2]~12_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h7350; +defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N12 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( +// Equation(s): +// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~33_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & +// (((\z80_|alu_flags_|flags_hf2~q )))) + + .dataa(\z80_|alu_control_|db[4]~33_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datac(\z80_|alu_flags_|flags_hf2~q ), + .datad(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hEEF0; +defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N13 +dffeas \z80_|alu_flags_|flags_hf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|flags_hf2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_hf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N12 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( +// Equation(s): +// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [2]) # (\z80_|alu_|op1_low [1]))) + + .dataa(gnd), + .datab(\z80_|alu_|op1_low [3]), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hCCC0; +defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~combout = (\z80_|pla_decode_|Equal47~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~24 ( +// Equation(s): +// \z80_|alu_control_|db[2]~24_combout = (\z80_|alu_flags_|flags_hf2~q ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|execute_|ctl_66_oe~combout ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|alu_flags_|flags_hf2~q ), + .datab(\z80_|alu_control_|out[6]~0_combout ), + .datac(\z80_|execute_|ctl_66_oe~combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~24 .lut_mask = 16'hFEFF; +defparam \z80_|alu_control_|db[2]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datac(\z80_|execute_|rsel3~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # (\z80_|pla_decode_|Equal40~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout )) + + .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[2]~1_combout = (\z80_|reg_file_|gdfx_temp0[2]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[2]~1 .lut_mask = 16'hCCEC; +defparam \z80_|reg_file_|db_lo_ds[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N18 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( +// Equation(s): +// \z80_|alu_control_|db[2]~29_combout = (\z80_|reg_file_|db_lo_ds[2]~1_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[2]~13_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), + .datab(\z80_|reg_file_|db_lo_ds[2]~1_combout ), + .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datad(\z80_|bus_control_|db[2]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h4C44; +defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~30 ( +// Equation(s): +// \z80_|alu_control_|db[2]~30_combout = ((!\z80_|alu_control_|db[2]~28_combout & (\z80_|alu_control_|db[2]~24_combout & \z80_|alu_control_|db[2]~29_combout ))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_control_|db[2]~28_combout ), + .datab(\z80_|alu_control_|db[2]~24_combout ), + .datac(\z80_|alu_control_|db[6]~13_combout ), + .datad(\z80_|alu_control_|db[2]~29_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~30 .lut_mask = 16'h4F0F; +defparam \z80_|alu_control_|db[2]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [2] & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|alu_control_|db[2]~30_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .datad(\z80_|alu_control_|db[2]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N31 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~41_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~41_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y17_N29 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & (\z80_|reg_file_|gdfx_temp0[2]~37_combout & \z80_|reg_file_|gdfx_temp0[2]~36_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~35_combout & (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~39_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~41_combout = ((\z80_|reg_file_|gdfx_temp0[2]~40_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .datac(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp0[2]~41_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[2]~41_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hCC0C; +defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hDF55; +defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N26 +cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( +// Equation(s): +// \z80_|address_latch_|abusz [2] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[2]~9_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [2]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N27 +dffeas \z80_|address_latch_|Q[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [2]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N18 +cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( +// Equation(s): +// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [3]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N21 +dffeas \z80_|address_latch_|Q[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_latch_|abusz [3]), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [2] & +// !\z80_|address_latch_|Q [3])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [2] & \z80_|address_latch_|Q [3])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [2]), + .datad(\z80_|address_latch_|Q [3]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h2008; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [4] $ +// (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [4]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [5]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N15 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[5]~17_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .datad(\z80_|alu_control_|db[5]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|gdfx_temp0[5]~65_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hC4C4; +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N15 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N31 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y17_N25 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|gdfx_temp0[5]~67_combout & (\z80_|reg_file_|gdfx_temp0[5]~66_combout & (\z80_|reg_file_|gdfx_temp0[5]~68_combout & \z80_|reg_file_|gdfx_temp0[5]~64_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N9 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~62_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~62 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[5]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~63_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~62_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~62_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~71_combout = ((\z80_|reg_file_|gdfx_temp0[5]~70_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'h8AFF; +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .datad(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .datab(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .datab(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'h8CFF; +defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N30 +cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( +// Equation(s): +// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~18_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [5]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N31 +dffeas \z80_|address_latch_|Q[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [5]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout = \z80_|address_latch_|Q [5] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|address_latch_|Q [5]), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0F4B; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N31 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N21 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~72 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[6]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|execute_|ctl_reg_sel_wz~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & ((\z80_|alu_control_|db[6]~23_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|alu_control_|db[6]~23_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .datad(\z80_|alu_control_|db[6]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y17_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout & (\z80_|reg_file_|gdfx_temp0[6]~77_combout & (\z80_|reg_file_|gdfx_temp0[6]~75_combout & \z80_|reg_file_|gdfx_temp0[6]~76_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N27 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~80_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N21 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|gdfx_temp0[6]~73_combout & (\z80_|reg_file_|gdfx_temp0[6]~72_combout & (\z80_|reg_file_|gdfx_temp0[6]~78_combout & \z80_|reg_file_|gdfx_temp0[6]~74_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~72_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~80_combout = ((\z80_|reg_file_|gdfx_temp0[6]~79_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hCC44; +defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datab(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'h8CFF; +defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( +// Equation(s): +// \z80_|address_latch_|abusz [6] = (\z80_|reg_file_|db_lo_as[6]~21_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h00CC; +defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N15 +dffeas \z80_|address_latch_|Q[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [6]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~7_combout ) # (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|execute_|ctl_inc_dec~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h0312; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q [7]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [8]), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'hD278; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [0] & ((\z80_|reg_file_|gdfx_temp1[0]~30_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[0]~30_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hAA22; +defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hB3BB; +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N20 +cycloneive_lcell_comb \z80_|alu_|db[0]~17 ( +// Equation(s): +// \z80_|alu_|db[0]~17_combout = (\z80_|reg_file_|gdfx_temp1[0]~30_combout & (((\z80_|alu_|db_low[0]~27_combout )) # (!\z80_|execute_|ctl_alu_oe~14_combout ))) # (!\z80_|reg_file_|gdfx_temp1[0]~30_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_|db_low[0]~27_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db_low[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~17 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N30 +cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( +// Equation(s): +// \z80_|alu_|db[0]~18_combout = ((\z80_|alu_|db[0]~17_combout & ((\z80_|alu_control_|db[0]~14_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_control_|db[0]~14_combout ), + .datab(\z80_|alu_|db[0]~17_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|alu_|db[7]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~18 .lut_mask = 16'h8CFF; +defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N20 +cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( +// Equation(s): +// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~18_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|sw2_|db_up[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hAAFF; +defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~11 ( +// Equation(s): +// \z80_|alu_control_|db[0]~11_combout = (\z80_|alu_control_|db[0]~10_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|alu_control_|db[0]~10_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datad(\z80_|sw2_|db_up[0]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~11 .lut_mask = 16'h8A00; +defparam \z80_|alu_control_|db[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~14 ( +// Equation(s): +// \z80_|alu_control_|db[0]~14_combout = ((\z80_|alu_control_|db[0]~11_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_control_|db[0]~11_combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|db[6]~13_combout ), + .datad(\z80_|alu_flags_|flags_cf~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~14 .lut_mask = 16'hAF2F; +defparam \z80_|alu_control_|db[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[0]~14_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .datad(\z80_|alu_control_|db[0]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y17_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) # (!\z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N1 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout & (\z80_|reg_file_|gdfx_temp0[0]~10_combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .datad(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'hC400; +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~14_combout & (\z80_|reg_file_|gdfx_temp0[0]~15_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .datab(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'h8C00; +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~13_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & (\z80_|reg_file_|gdfx_temp0[0]~11_combout & \z80_|reg_file_|gdfx_temp0[0]~16_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hB0FF; +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[0]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hAA0A; +defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hDF55; +defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N16 +cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( +// Equation(s): +// \z80_|address_latch_|abusz [0] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[0]~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [0]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N17 +dffeas \z80_|address_latch_|Q[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [0]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ ((((\z80_|execute_|ctl_inc_dec~7_combout ) # (\z80_|execute_|ctl_inc_dec~9_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~6_combout ), + .datab(\z80_|address_latch_|Q [0]), + .datac(\z80_|execute_|ctl_inc_dec~7_combout ), + .datad(\z80_|execute_|ctl_inc_dec~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h3339; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout +// ))))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|execute_|ctl_inc_cy~81_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datad(\z80_|execute_|ctl_inc_cy~93_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h5A6A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N17 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N15 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hC4C4; +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|alu_control_|db[1]~27_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|alu_control_|db[1]~27_combout & +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) + + .dataa(\z80_|alu_control_|db[1]~27_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hBB0B; +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~28_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & \z80_|reg_file_|gdfx_temp0[1]~29_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N3 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N15 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N13 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~23_combout & (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .datab(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'h8AFF; +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[1]~32_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .datad(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hF755; +defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( +// Equation(s): +// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [1]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N0 +cycloneive_lcell_comb \z80_|address_latch_|Q[1]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[1]~feeder_combout = \z80_|address_latch_|abusz [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [1]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N1 +dffeas \z80_|address_latch_|Q[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[1]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|execute_|ctl_inc_dec~9_combout ), + .datac(\z80_|execute_|ctl_inc_dec~7_combout ), + .datad(\z80_|execute_|ctl_inc_dec~6_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h5655; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout & +// ((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datab(\z80_|execute_|ctl_inc_cy~81_combout ), + .datac(\z80_|execute_|ctl_inc_cy~93_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .lut_mask = 16'hA800; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q +// [2]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [2]), + .datad(\z80_|address_latch_|Q [3]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'hD728; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~51_combout = ((\z80_|reg_file_|gdfx_temp0[3]~50_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( +// Equation(s): +// \z80_|alu_control_|db[3]~35_combout = (\z80_|alu_control_|db[3]~34_combout & (\z80_|sw1_|db_down[3]~3_combout & ((\z80_|reg_file_|gdfx_temp0[3]~51_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|alu_control_|db[3]~34_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|sw1_|db_down[3]~3_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hA020; +defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~36 ( +// Equation(s): +// \z80_|alu_control_|db[3]~36_combout = ((\z80_|alu_control_|db[3]~35_combout & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_|db[3]~14_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_control_|db[6]~13_combout ), + .datad(\z80_|alu_control_|db[3]~35_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~36 .lut_mask = 16'hBF0F; +defparam \z80_|alu_control_|db[3]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N26 +cycloneive_lcell_comb \z80_|alu_|db[3]~14 ( +// Equation(s): +// \z80_|alu_|db[3]~14_combout = ((\z80_|alu_|db[3]~13_combout & ((\z80_|alu_control_|db[3]~36_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~9_combout ), + .datab(\z80_|alu_|db[3]~13_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|alu_control_|db[3]~36_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~14 .lut_mask = 16'hDD5D; +defparam \z80_|alu_|db[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N0 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~4 ( +// Equation(s): +// \z80_|alu_|db_low[3]~4_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[2]~12_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_|db[2]~12_combout ), + .datad(\z80_|alu_|db[4]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~4 .lut_mask = 16'hFC30; +defparam \z80_|alu_|db_low[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N10 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~5 ( +// Equation(s): +// \z80_|alu_|db_low[3]~5_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~4_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~14_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db[3]~14_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datad(\z80_|alu_|db_low[3]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~5 .lut_mask = 16'hFD5D; +defparam \z80_|alu_|db_low[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N25 +dffeas \z80_|alu_|result_lo[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~6 ( +// Equation(s): +// \z80_|alu_|db_low[3]~6_combout = (\z80_|alu_|op1_low [3] & (((\z80_|alu_|op2_low [3])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_low [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [3]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_low [3]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op2_low [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~6 .lut_mask = 16'hAF23; +defparam \z80_|alu_|db_low[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~7 ( +// Equation(s): +// \z80_|alu_|db_low[3]~7_combout = (\z80_|alu_|db_low[3]~6_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|alu_|db_low[3]~6_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~7 .lut_mask = 16'h2A0A; +defparam \z80_|alu_|db_low[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~8 ( +// Equation(s): +// \z80_|alu_|db_low[3]~8_combout = (\z80_|alu_|db_low[3]~5_combout & (\z80_|alu_|db_low[3]~7_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [3])))) + + .dataa(\z80_|alu_|db_low[3]~5_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|result_lo [3]), + .datad(\z80_|alu_|db_low[3]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~8 .lut_mask = 16'hA800; +defparam \z80_|alu_|db_low[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~26 ( +// Equation(s): +// \z80_|alu_|db_low[3]~26_combout = (\z80_|alu_|db_low[3]~8_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[3]~0_combout ), + .datad(\z80_|alu_|db_low[3]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~26 .lut_mask = 16'hFF03; +defparam \z80_|alu_|db_low[3]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) + + .dataa(\z80_|alu_|op1_high [3]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [3]), + .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .lut_mask = 16'hE200; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[3]~26_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|alu_|db_low[3]~26_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .lut_mask = 16'h0F08; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N13 +dffeas \z80_|alu_|op2_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_high[3]~7_combout ) # ((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # +// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|alu_|db_high[3]~7_combout ), + .datac(\z80_|alu_|db_low[3]~26_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N21 +dffeas \z80_|alu_|op2_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N14 +cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~0 ( +// Equation(s): +// \z80_|alu_|alu_op2[3]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [3]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [3])))) + + .dataa(\z80_|alu_|op2_low [3]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|alu_|op2_high [3]), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[3]~0 .lut_mask = 16'h1DE2; +defparam \z80_|alu_|alu_op2[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op2[3]~0_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & \z80_|alu_|alu_op1[3]~0_combout )) # (!\z80_|alu_|alu_op2[3]~0_combout & +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & !\z80_|alu_|alu_op1[3]~0_combout )) + + .dataa(\z80_|alu_|alu_op2[3]~0_combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_|alu_op1[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'h0A50; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout & (\z80_|alu_|alu_op2[3]~0_combout )) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout & +// (((!\z80_|execute_|ctl_alu_core_R~4_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[3]~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .lut_mask = 16'hAA3F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( +// Equation(s): +// \z80_|alu_|db_high[3]~4_combout = (\z80_|alu_|op1_high [3] & (((\z80_|alu_|op2_high [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [3]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [3]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_high [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( +// Equation(s): +// \z80_|alu_|db_high[3]~2_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_|db[6]~22_combout ), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFC30; +defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( +// Equation(s): +// \z80_|alu_|db_high[3]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[3]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[7]~20_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datab(\z80_|alu_|db[7]~20_combout ), + .datac(\z80_|alu_|db_high[3]~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hE4FF; +defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( +// Equation(s): +// \z80_|alu_|db_high[3]~5_combout = (\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[4]~19_combout )) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'h8800; +defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( +// Equation(s): +// \z80_|alu_|db_high[3]~6_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~3_combout & ((\z80_|alu_|db_high[3]~5_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|alu_|db_high[3]~4_combout ), + .datab(\z80_|alu_|db_high[3]~3_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|db_high[3]~5_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'h8808; +defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( +// Equation(s): +// \z80_|alu_|db_high[3]~7_combout = ((\z80_|alu_|db_high[3]~6_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|db_high[3]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'hFB33; +defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|execute_|ctl_flags_alu~19_combout & \z80_|alu_|db_high[3]~7_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datab(\z80_|execute_|ctl_flags_alu~19_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .datad(\z80_|alu_|db_high[3]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFDF5; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_shift_oe~38_combout & \z80_|execute_|ctl_alu_core_S~11_combout +// ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~11_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout & (((!\z80_|execute_|ctl_state_alu~12_combout ) # (!\z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'h7F00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (!\z80_|pla_decode_|Equal73~2_combout & (!\z80_|execute_|ctl_alu_sel_op2_neg~16_combout & !\z80_|execute_|ctl_alu_op_low~39_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .datab(\z80_|pla_decode_|Equal73~2_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h0002; +defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout & (\z80_|execute_|ctl_alu_core_hf~14_combout & (\z80_|execute_|ctl_flags_nf_we~0_combout & \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal61~2_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~3_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_nf_we~2_combout ) # (!\z80_|execute_|ctl_flags_xy_we~12_combout ))) # (!\z80_|execute_|ctl_flags_nf_we~1_combout ) + + .dataa(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~14 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~14_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (((!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~14 .lut_mask = 16'h0155; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~13 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout & \z80_|execute_|ctl_alu_core_hf~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~13 .lut_mask = 16'hF000; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~15 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~15_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (!\z80_|pla_decode_|Equal73~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .datab(\z80_|pla_decode_|Equal73~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~15 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~16 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~16_combout = (\z80_|execute_|ctl_flags_nf_we~3_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~3_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .datab(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~16 .lut_mask = 16'hB830; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N25 +dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~3_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_op_low~18_combout )))) # (!\z80_|execute_|ctl_state_alu~13_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datad(\z80_|execute_|ctl_state_alu~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'h32FF; +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal68~2_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .datad(\z80_|pla_decode_|Equal68~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hA2A0; +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~5_combout = (\z80_|execute_|ctl_flags_cf_cpl~4_combout ) # ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'hF0FE; +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_set~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_set~0_combout = (\z80_|execute_|ctl_state_alu~12_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal9~0_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~12_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_set~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_set~0 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_cf_set~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_state_alu~3_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout & +// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), + .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~2_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((\z80_|execute_|ctl_flags_cf_set~0_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~6_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .datac(\z80_|execute_|ctl_flags_cf_set~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N18 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( +// Equation(s): +// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [1]) # ((\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [0] & \z80_|alu_control_|out[6]~0_combout ))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|alu_|op1_high [0]), + .datac(\z80_|alu_|op1_high [2]), + .datad(\z80_|alu_control_|out[6]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEFA; +defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( +// Equation(s): +// \z80_|alu_control_|out[6]~2_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_|op1_high [3] & \z80_|alu_control_|out[6]~1_combout ))) + + .dataa(\z80_|alu_|op1_high [3]), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|execute_|ctl_66_oe~combout ), + .datad(\z80_|alu_control_|out[6]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFEFC; +defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~18_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_|db[7]~20_combout ), + .datad(\z80_|alu_|db[0]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hFC30; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N12 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|execute_|ctl_alu_core_R~combout +// & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hCC50; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_we~5_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~5_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_flags_cf2_we~5_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h7430; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N30 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_control_|out[6]~2_combout & !\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|alu_control_|out[6]~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'hF0F8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N31 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~10_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h4050; +defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal10~0_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|pla_decode_|Equal20~0_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h00EC; +defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~11_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout ))) + + .dataa(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hAAAC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N14 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = (\z80_|execute_|ctl_state_alu~12_combout & ((\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'h8044; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal63~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'hAEAA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~21_combout = (\z80_|pla_decode_|Equal10~1_combout & (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|pla_decode_|Equal10~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ) # ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~21_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'hFEFF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ) # ((\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFF8F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) # ((\z80_|execute_|ctl_alu_op_low~35_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'hFFEA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_state_alu~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~1_combout = (\z80_|pla_decode_|Equal64~0_combout & (\z80_|execute_|ctl_alu_op_low~35_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal64~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~1 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_flags_cf_cpl~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'hA8A0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout & ((\z80_|execute_|ctl_alu_op_low~30_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~40_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~40_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'hCCC8; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|pla_decode_|Equal61~2_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .lut_mask = 16'h0313; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout = (\z80_|execute_|ctl_alu_core_R~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & \z80_|execute_|ctl_flags_alu~10_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_R~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .lut_mask = 16'h8800; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|nM1_int~2_combout & +// (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal56~0_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .lut_mask = 16'h135F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~0 .lut_mask = 16'hFCEC; +defparam \z80_|execute_|ctl_flags_cf_cpl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_flags_cf_cpl~0_combout ) # (!\z80_|execute_|ctl_alu_op_low~34_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h040C; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = ((!\z80_|pla_decode_|Equal39~0_combout & ((!\z80_|pla_decode_|Equal40~2_combout ) # (!\z80_|ir_|opcode [5])))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal40~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h5777; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'h3330; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & \z80_|execute_|ctl_flags_nf_we~0_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .datad(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N2 +cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( +// Equation(s): +// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~1_combout ))))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_cf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h3600; +defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & (((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (\z80_|nM1_int~2_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (\z80_|pla_decode_|Equal10~0_combout & +// (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hECE0; +defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~18_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ) # ((\z80_|alu_control_|db[4]~33_combout & \z80_|execute_|ctl_flags_bus~combout )) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[4]~33_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'hFCF0; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N30 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_hf~q )))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (((\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )))) + + .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hFD20; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N31 +dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~9_combout = ((!\z80_|pla_decode_|Equal52~0_combout & ((\z80_|decode_state_|use_ixiy~combout ) # (!\z80_|pla_decode_|Equal44~0_combout )))) # (!\z80_|pla_decode_|Equal33~0_combout ) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~9 .lut_mask = 16'h45FF; +defparam \z80_|execute_|ctl_flags_hf_cpl~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (\z80_|execute_|ctl_alu_op_low~18_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_hf_cpl~10_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~8_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), + .datad(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'h2202; +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N12 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( +// Equation(s): +// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) + + .dataa(\z80_|alu_flags_|flags_cf~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h393C; +defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( +// Equation(s): +// \z80_|alu_control_|db[4]~31_combout = (\z80_|execute_|ctl_reg_out_lo~8_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[4]~10_combout )) # (!\z80_|reg_file_|gdfx_temp0[4]~61_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~8_combout & +// (\z80_|execute_|ctl_sw_2u~7_combout & ((!\z80_|alu_|db[4]~10_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .datad(\z80_|alu_|db[4]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h0ACE; +defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( +// Equation(s): +// \z80_|alu_control_|db[4]~32_combout = (!\z80_|alu_control_|db[4]~31_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_flags_|flags_hf~combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|db[4]~31_combout ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'h0B00; +defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~33 ( +// Equation(s): +// \z80_|alu_control_|db[4]~33_combout = ((\z80_|alu_control_|db[4]~32_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_control_|db[6]~13_combout ), + .datab(\z80_|execute_|ctl_sw_1d~7_combout ), + .datac(\z80_|bus_control_|db[4]~19_combout ), + .datad(\z80_|alu_control_|db[4]~32_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~33 .lut_mask = 16'hF755; +defparam \z80_|alu_control_|db[4]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N15 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N29 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~52_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~52 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[4]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|gdfx_temp0[4]~52_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|alu_control_|db[4]~33_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~52_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hDD00; +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N23 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y15_N3 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y17_N9 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N1 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y17_N11 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N19 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|gdfx_temp0[4]~58_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datad(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'h8808; +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~56_combout & (\z80_|reg_file_|gdfx_temp0[4]~53_combout & (\z80_|reg_file_|gdfx_temp0[4]~55_combout & \z80_|reg_file_|gdfx_temp0[4]~59_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~61_combout = ((\z80_|reg_file_|gdfx_temp0[4]~60_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .datab(gnd), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hAF00; +defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N22 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ) + + .dataa(\z80_|address_latch_|Q [4]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h55AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .datab(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N4 +cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( +// Equation(s): +// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~15_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [4]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N5 +dffeas \z80_|address_latch_|Q[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [4]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N6 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [4] & (!\z80_|address_latch_|Q [5] & (!\z80_|address_latch_|Q [6] & !\z80_|address_latch_|Q [7]))) + + .dataa(\z80_|address_latch_|Q [4]), + .datab(\z80_|address_latch_|Q [5]), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N30 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [8] & (!\z80_|address_latch_|Q [9] & !\z80_|address_latch_|Q [11]))) + + .dataa(\z80_|address_latch_|Q [10]), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|Q [11]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N20 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~3_combout = (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [3] & (!\z80_|address_latch_|Q [2] & !\z80_|address_latch_|Q [1]))) + + .dataa(\z80_|address_latch_|Q [0]), + .datab(\z80_|address_latch_|Q [3]), + .datac(\z80_|address_latch_|Q [2]), + .datad(\z80_|address_latch_|Q [1]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0002; +defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N16 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [13] & (!\z80_|address_latch_|Q [12] & (!\z80_|address_latch_|Q [15] & !\z80_|address_latch_|Q [14]))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|address_latch_|Q [12]), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|Q [14]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N26 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~2_combout & (\z80_|decode_state_|DFFE_instNonRep~1_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & \z80_|decode_state_|DFFE_instNonRep~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; +defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N12 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~9_combout & +// ((\z80_|decode_state_|DFFE_instNonRep~4_combout ))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|decode_state_|DFFE_instNonRep~q )))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hF4B0; +defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N13 +dffeas \z80_|decode_state_|DFFE_instNonRep ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instNonRep~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N30 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & (!\z80_|pla_decode_|Equal62~3_combout & (\z80_|execute_|ctl_pf_sel[0]~13_combout & \z80_|execute_|ctl_pf_sel[0]~10_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datab(\z80_|pla_decode_|Equal62~3_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h1000; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N18 +cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( +// Equation(s): +// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & (\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal79~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|pla_decode_|Equal79~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hD8F0; +defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N4 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|interrupts_|DFFE_inst44~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h5F0F; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G16 +cycloneive_clkctrl \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X30_Y12_N19 +dffeas \z80_|interrupts_|DFFE_instIFF2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|DFFE_instIFF2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'h80C4; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & +// (!\z80_|decode_state_|DFFE_instNonRep~q )))) + + .dataa(\z80_|decode_state_|DFFE_instNonRep~q ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'hC500; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|pla_decode_|Equal62~3_combout ) # (\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout ) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|pla_decode_|Equal62~3_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'hFFFD; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|execute_|ctl_pf_sel[0]~13_combout & (\z80_|execute_|ctl_pf_sel[0]~10_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'h4C00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[1]~12 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[1]~12_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[1]~12 .lut_mask = 16'h0031; +defparam \z80_|execute_|ctl_pf_sel[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~11 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~11_combout = (\z80_|nM1_int~2_combout & (((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|pla_decode_|Equal62~3_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|pla_decode_|Equal62~3_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~11 .lut_mask = 16'hFD00; +defparam \z80_|execute_|ctl_pf_sel[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (!\z80_|execute_|ctl_pf_sel[1]~12_combout & (((\z80_|execute_|ctl_pf_sel[0]~11_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~10_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .datab(\z80_|execute_|ctl_pf_sel[1]~12_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~11_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h3133; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ (((\z80_|execute_|ctl_alu_core_R~combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ))))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h6500; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N17 +dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|alu_parity_out~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N2 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( +// Equation(s): +// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'h6996; +defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( +// Equation(s): +// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .datad(\z80_|alu_|alu_parity_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out .lut_mask = 16'h03FC; +defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout & \z80_|alu_|alu_parity_out~combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .datad(\z80_|alu_|alu_parity_out~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'hFEFA; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~10_combout & (((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[2]~30_combout )))) # (!\z80_|execute_|ctl_flags_pf_we~10_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_pf~q )) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datab(\z80_|execute_|ctl_flags_bus~combout ), + .datac(\z80_|alu_control_|db[2]~30_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'hC0AA; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout & \z80_|execute_|ctl_flags_alu~19_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .datac(\z80_|execute_|ctl_flags_alu~19_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFF80; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y11_N25 +dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal13~0_combout ) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hF7FF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[2]~14_combout & (!\z80_|alu_|db_low[0]~27_combout & (!\z80_|alu_|db_low[3]~26_combout & !\z80_|alu_|db_low[1]~20_combout ))) + + .dataa(\z80_|alu_|db_low[2]~14_combout ), + .datab(\z80_|alu_|db_low[0]~27_combout ), + .datac(\z80_|alu_|db_low[3]~26_combout ), + .datad(\z80_|alu_|db_low[1]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_high[1]~19_combout & (!\z80_|alu_|db_high[0]~25_combout & (!\z80_|alu_|db_high[2]~13_combout & !\z80_|alu_|db_high[3]~7_combout ))) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|alu_|db_high[0]~25_combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|alu_|db_high[3]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout = (\z80_|execute_|ctl_flags_alu~19_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_alu~19_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hC000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ) # ((\z80_|alu_control_|db[6]~23_combout & \z80_|execute_|ctl_flags_bus~combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .datab(\z80_|alu_control_|db[6]~23_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hA8A0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N25 +dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ) # ((\z80_|alu_control_|sel[1]~0_combout )))) # (!\z80_|ir_|opcode [4] & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & +// !\z80_|alu_control_|sel[1]~0_combout )))) + + .dataa(\z80_|alu_flags_|flags_cf~combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|alu_control_|sel[1]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hF0AC; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) + + .dataa(\z80_|alu_control_|sel[1]~0_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hF588; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N8 +cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( +// Equation(s): +// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((\z80_|alu_control_|flags_cond_true~q )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|flags_cond_true~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hD872; +defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N9 +dffeas \z80_|alu_control_|flags_cond_true ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_control_|flags_cond_true~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|flags_cond_true~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; +defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|execute_|ctl_reg_sys_we_lo~1_combout ) # (\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hA8FF; +defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~combout = (((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (\z80_|reg_control_|reg_sys_we_hi~0_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF7; +defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~44_combout ) # ((\z80_|reg_control_|reg_sw_4d_hi~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datac(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~7 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~7_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [3] & ((\z80_|reg_file_|gdfx_temp1[3]~39_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[3]~39_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~7 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|db_hi_as[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~8 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~8_combout = (\z80_|reg_file_|db_hi_as[3]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[3]~7_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~8 .lut_mask = 16'hAA22; +defparam \z80_|reg_file_|db_hi_as[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~9 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~9_combout = ((\z80_|reg_file_|db_hi_as[3]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datac(\z80_|reg_file_|db_hi_as[3]~8_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~9 .lut_mask = 16'hD5F5; +defparam \z80_|reg_file_|db_hi_as[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N12 +cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( +// Equation(s): +// \z80_|address_latch_|abusz [11] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[3]~9_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N13 +dffeas \z80_|address_latch_|Q[11] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [11]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|Q [11] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [11]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N14 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [11]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h5505; +defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N6 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~2_combout = (\z80_|execute_|fIORead~3_combout ) # (((\z80_|execute_|fMRead~36_combout ) # (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )) + + .dataa(\z80_|execute_|fIORead~3_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datac(\z80_|execute_|fMRead~36_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFBFF; +defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N12 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|pin_control_|bus_ab_pin_we~2_combout & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) # (!\z80_|pin_control_|bus_ab_pin_we~2_combout & +// (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h22F2; +defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N15 +dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .asdata(\z80_|address_latch_|Q [11]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y4_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( +// Equation(s): +// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [11]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[11]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N4 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [10])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [10]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N5 +dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .asdata(\z80_|address_latch_|Q [10]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[10]~20 ( +// Equation(s): +// \z80_|address_pins_|abus[10]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [10]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[10]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[10]~20 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[10]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~19 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|extended~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~19 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|keys[7][1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~48 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~48_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~48_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~48 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[7][4]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~51 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~51_combout = (\ula_|zx_keyboard_|keys[3][2]~50_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[3][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][2]~50_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .datac(\ula_|zx_keyboard_|keys[3][2]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~51 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][2]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N7 dffeas \ula_|zx_keyboard_|keys[3][2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][2]~54_combout ), + .d(\ula_|zx_keyboard_|keys[3][2]~51_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49332,80 +39425,221 @@ defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N8 -cycloneive_lcell_comb \D[2]~36 ( +// Location: LCCOMB_X23_Y9_N26 +cycloneive_lcell_comb \D[2]~43 ( // Equation(s): -// \D[2]~36_combout = (\ula_|zx_keyboard_|keys[2][2]~q & (\z80_|address_pins_|abus[10]~24_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) # (!\ula_|zx_keyboard_|keys[2][2]~q & -// (((\z80_|address_pins_|abus[11]~19_combout )) # (!\ula_|zx_keyboard_|keys[3][2]~q ))) +// \D[2]~43_combout = (\ula_|zx_keyboard_|keys[2][2]~q & (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) # (!\ula_|zx_keyboard_|keys[2][2]~q & +// ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][2]~q )))) .dataa(\ula_|zx_keyboard_|keys[2][2]~q ), - .datab(\ula_|zx_keyboard_|keys[3][2]~q ), - .datac(\z80_|address_pins_|abus[10]~24_combout ), - .datad(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\z80_|address_pins_|abus[11]~19_combout ), + .datac(\z80_|address_pins_|abus[10]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[3][2]~q ), .cin(gnd), - .combout(\D[2]~36_combout ), + .combout(\D[2]~43_combout ), .cout()); // synopsys translate_off -defparam \D[2]~36 .lut_mask = 16'hF531; -defparam \D[2]~36 .sum_lutc_input = "datac"; +defparam \D[2]~43 .lut_mask = 16'hC4F5; +defparam \D[2]~43 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y19_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~68 ( +// Location: LCCOMB_X20_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~68_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [1]))) +// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|WideOr17~0_combout )) .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|WideOr17~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .combout(\ula_|zx_keyboard_|shifted~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~68 .lut_mask = 16'h0180; -defparam \ula_|zx_keyboard_|keys[6][2]~68 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y20_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~69 ( +// Location: LCCOMB_X19_Y10_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~11 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~69_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~68_combout )) +// \ula_|zx_keyboard_|keys[0][0]~11_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|Equal0~1_combout )) - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~11 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|keys[0][0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h000A; +defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~0_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # +// (!\ula_|zx_keyboard_|shifted~2_combout & (((\ula_|zx_keyboard_|shifted~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|shifted~2_combout ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|shifted~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y8_N31 +dffeas \ula_|zx_keyboard_|shifted ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|shifted~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|shifted~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|shifted .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~62 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~62_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~62_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~62 .lut_mask = 16'hF0FC; +defparam \ula_|zx_keyboard_|keys[5][0]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~32 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~32_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|zx_keyboard_|extended~q & \ula_|zx_keyboard_|keys[0][0]~11_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~32 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~63 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~63_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~63_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~63 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[6][2]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~64 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~64_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~63_combout ) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .datad(\ula_|zx_keyboard_|keys[6][2]~63_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .combout(\ula_|zx_keyboard_|keys[6][2]~64_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~69 .lut_mask = 16'h2200; -defparam \ula_|zx_keyboard_|keys[6][2]~69 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][2]~64 .lut_mask = 16'h5500; +defparam \ula_|zx_keyboard_|keys[6][2]~64 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~70 ( +// Location: LCCOMB_X21_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~65 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~70_combout = (\ula_|zx_keyboard_|keys[6][2]~69_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~69_combout & ((\ula_|zx_keyboard_|keys[6][2]~q ))) +// \ula_|zx_keyboard_|keys[6][2]~65_combout = (\ula_|zx_keyboard_|keys[6][1]~32_combout & ((\ula_|zx_keyboard_|keys[6][2]~64_combout & (!\ula_|zx_keyboard_|keys[5][0]~62_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~64_combout & +// ((\ula_|zx_keyboard_|keys[6][2]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~32_combout & (((\ula_|zx_keyboard_|keys[6][2]~q )))) - .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .datab(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .dataa(\ula_|zx_keyboard_|keys[5][0]~62_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~32_combout ), .datac(\ula_|zx_keyboard_|keys[6][2]~q ), - .datad(gnd), + .datad(\ula_|zx_keyboard_|keys[6][2]~64_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~70_combout ), + .combout(\ula_|zx_keyboard_|keys[6][2]~65_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~70 .lut_mask = 16'h7474; -defparam \ula_|zx_keyboard_|keys[6][2]~70 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][2]~65 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[6][2]~65 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y20_N1 +// Location: FF_X21_Y9_N5 dffeas \ula_|zx_keyboard_|keys[6][2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][2]~70_combout ), + .d(\ula_|zx_keyboard_|keys[6][2]~65_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49421,112 +39655,253 @@ defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( +// Location: LCCOMB_X31_Y16_N18 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~61_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) +// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) + + .dataa(\z80_|address_latch_|abusz [15]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N19 +dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .asdata(\z80_|address_latch_|Q [15]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[15]~21 ( +// Equation(s): +// \z80_|address_pins_|abus[15]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .combout(\z80_|address_pins_|abus[15]~21_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[15]~21 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[15]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~62 ( +// Location: LCCOMB_X31_Y16_N22 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~62_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[7][2]~61_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0]))) +// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [14])) + + .dataa(\z80_|address_latch_|abusz [14]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N23 +dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .asdata(\z80_|address_latch_|Q [14]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N14 +cycloneive_lcell_comb \z80_|address_pins_|abus[14]~22 ( +// Equation(s): +// \z80_|address_pins_|abus[14]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[14]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[14]~22 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[14]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~57 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~57_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~57_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~57 .lut_mask = 16'h3030; +defparam \ula_|zx_keyboard_|keys[7][2]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~58 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~58_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~57_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[7][2]~57_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~58_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~58 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[7][2]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~59 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~59_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~59 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|keys[5][4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~28 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~28_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5])) .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(gnd), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~62_combout ), + .combout(\ula_|zx_keyboard_|keys[7][2]~28_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~62 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[7][2]~62 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[7][2]~28 .lut_mask = 16'h0404; +defparam \ula_|zx_keyboard_|keys[7][2]~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~64 ( +// Location: LCCOMB_X21_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~60 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~64_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~62_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~63_combout & \ula_|zx_keyboard_|keys[7][2]~32_combout )))) +// \ula_|zx_keyboard_|keys[7][2]~60_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~58_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~59_combout & \ula_|zx_keyboard_|keys[7][2]~28_combout )))) - .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .dataa(\ula_|zx_keyboard_|keys[7][2]~58_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~59_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .combout(\ula_|zx_keyboard_|keys[7][2]~60_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~64 .lut_mask = 16'hC8C0; -defparam \ula_|zx_keyboard_|keys[7][2]~64 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[7][2]~60 .lut_mask = 16'hE0A0; +defparam \ula_|zx_keyboard_|keys[7][2]~60 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~65 ( +// Location: LCCOMB_X20_Y8_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~56 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~65_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~15_combout & \ula_|zx_keyboard_|keys[7][2]~64_combout ))) +// \ula_|zx_keyboard_|keys[7][2]~56_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[0][0]~11_combout & !\ula_|zx_keyboard_|extended~q )) .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~65_combout ), + .combout(\ula_|zx_keyboard_|keys[7][2]~56_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~65 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|keys[7][2]~65 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[7][2]~56 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|keys[7][2]~56 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N22 +// Location: LCCOMB_X23_Y8_N28 cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( // Equation(s): -// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [5])) +// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q )) - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|released~q ), + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), .cin(gnd), .combout(\ula_|zx_keyboard_|Selector13~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hFF22; +defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hF5F0; defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~66 ( +// Location: LCCOMB_X23_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~66_combout = (\ula_|zx_keyboard_|keys[7][2]~65_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~65_combout & (\ula_|zx_keyboard_|keys[7][2]~q )) +// \ula_|zx_keyboard_|keys[7][2]~61_combout = (\ula_|zx_keyboard_|keys[7][2]~60_combout & ((\ula_|zx_keyboard_|keys[7][2]~56_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~56_combout & +// (\ula_|zx_keyboard_|keys[7][2]~q )))) # (!\ula_|zx_keyboard_|keys[7][2]~60_combout & (((\ula_|zx_keyboard_|keys[7][2]~q )))) - .dataa(\ula_|zx_keyboard_|keys[7][2]~65_combout ), - .datab(gnd), + .dataa(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .datab(\ula_|zx_keyboard_|keys[7][2]~56_combout ), .datac(\ula_|zx_keyboard_|keys[7][2]~q ), .datad(\ula_|zx_keyboard_|Selector13~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~66_combout ), + .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~66 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[7][2]~66 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y21_N13 +// Location: FF_X23_Y8_N1 dffeas \ula_|zx_keyboard_|keys[7][2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][2]~66_combout ), + .d(\ula_|zx_keyboard_|keys[7][2]~61_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49542,173 +39917,1135 @@ defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N0 -cycloneive_lcell_comb \D[2]~38 ( +// Location: LCCOMB_X23_Y9_N10 +cycloneive_lcell_comb \D[2]~44 ( // Equation(s): -// \D[2]~38_combout = (\z80_|address_pins_|abus[15]~22_combout & (((\z80_|address_pins_|abus[14]~23_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~q ))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][2]~q & -// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) +// \D[2]~44_combout = (\ula_|zx_keyboard_|keys[6][2]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][2]~q )))) # (!\ula_|zx_keyboard_|keys[6][2]~q & +// ((\z80_|address_pins_|abus[15]~21_combout ) # ((!\ula_|zx_keyboard_|keys[7][2]~q )))) - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ula_|zx_keyboard_|keys[6][2]~q ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), + .dataa(\ula_|zx_keyboard_|keys[6][2]~q ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), .datad(\ula_|zx_keyboard_|keys[7][2]~q ), .cin(gnd), - .combout(\D[2]~38_combout ), + .combout(\D[2]~44_combout ), .cout()); // synopsys translate_off -defparam \D[2]~38 .lut_mask = 16'hA2F3; -defparam \D[2]~38 .sum_lutc_input = "datac"; +defparam \D[2]~44 .lut_mask = 16'hC4F5; +defparam \D[2]~44 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N14 -cycloneive_lcell_comb \D[2]~39 ( +// Location: LCCOMB_X31_Y16_N24 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( // Equation(s): -// \D[2]~39_combout = (\D[2]~35_combout & (\D[2]~37_combout & (\D[2]~36_combout & \D[2]~38_combout ))) +// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [12])) - .dataa(\D[2]~35_combout ), - .datab(\D[2]~37_combout ), - .datac(\D[2]~36_combout ), - .datad(\D[2]~38_combout ), + .dataa(\z80_|address_latch_|abusz [12]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), .cin(gnd), - .combout(\D[2]~39_combout ), + .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), .cout()); // synopsys translate_off -defparam \D[2]~39 .lut_mask = 16'h8000; -defparam \D[2]~39 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N14 -cycloneive_lcell_comb \D[2]~104 ( +// Location: FF_X31_Y16_N25 +dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .asdata(\z80_|address_latch_|Q [12]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[12]~24 ( // Equation(s): -// \D[2]~104_combout = ((\z80_|address_pins_|DFFE_apin_latch [0]) # (\D[2]~39_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|address_pins_|abus[12]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [12]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[12]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[12]~24 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[12]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N0 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [13]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datab(\z80_|address_latch_|abusz [13]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N1 +dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .asdata(\z80_|address_latch_|Q [13]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~29 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~29_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[7][2]~28_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~29_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~29 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[5][2]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~54 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~54_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~54_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~54 .lut_mask = 16'h0C0C; +defparam \ula_|zx_keyboard_|keys[5][2]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~55 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~55_combout = (\ula_|zx_keyboard_|keys[5][2]~29_combout & ((\ula_|zx_keyboard_|keys[5][2]~54_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][2]~54_combout & ((\ula_|zx_keyboard_|keys[5][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~29_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~29_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[5][2]~q ), + .datad(\ula_|zx_keyboard_|keys[5][2]~54_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~55_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~55 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][2]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y10_N31 +dffeas \ula_|zx_keyboard_|keys[5][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][2]~55_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~1_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # ((!\ula_|zx_keyboard_|keys[5][2]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|zx_keyboard_|keys[5][2]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hCFFF; +defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~127 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~127_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|Equal0~1_combout ))) + + .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~127_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~127 .lut_mask = 16'h0008; +defparam \ula_|zx_keyboard_|keys[3][4]~127 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~66 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~66_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~66_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~66 .lut_mask = 16'h0240; +defparam \ula_|zx_keyboard_|keys[4][2]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~128 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~128_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[4][2]~66_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|keys[4][2]~66_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~128_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~128 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[4][2]~128 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~67 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~67_combout = (\ula_|zx_keyboard_|keys[3][4]~127_combout & ((\ula_|zx_keyboard_|keys[4][2]~128_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][2]~128_combout & ((\ula_|zx_keyboard_|keys[4][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~127_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][4]~127_combout ), + .datac(\ula_|zx_keyboard_|keys[4][2]~q ), + .datad(\ula_|zx_keyboard_|keys[4][2]~128_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~67_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~67 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][2]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N23 +dffeas \ula_|zx_keyboard_|keys[4][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][2]~67_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N18 +cycloneive_lcell_comb \D[2]~45 ( +// Equation(s): +// \D[2]~45_combout = (\D[2]~44_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\D[2]~44_combout ), + .datab(\z80_|address_pins_|abus[12]~24_combout ), + .datac(\ula_|zx_keyboard_|key_row~1_combout ), + .datad(\ula_|zx_keyboard_|keys[4][2]~q ), + .cin(gnd), + .combout(\D[2]~45_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~45 .lut_mask = 16'h80A0; +defparam \D[2]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N26 +cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( +// Equation(s): +// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [0]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~43 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~43_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~43_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~43 .lut_mask = 16'h0808; +defparam \ula_|zx_keyboard_|keys[6][4]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~44 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~44_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[7][1]~19_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~44_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~44 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][4]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~45 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~45_combout = (\ula_|zx_keyboard_|keys[6][4]~43_combout & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~44_combout )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[6][4]~43_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[6][4]~44_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~45_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~45 .lut_mask = 16'h0C00; +defparam \ula_|zx_keyboard_|keys[1][2]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~46 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~46_combout = (\ula_|zx_keyboard_|keys[1][2]~45_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][2]~45_combout & ((\ula_|zx_keyboard_|keys[1][2]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[1][2]~q ), + .datad(\ula_|zx_keyboard_|keys[1][2]~45_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~46_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~46 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[1][2]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y9_N15 +dffeas \ula_|zx_keyboard_|keys[1][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][2]~46_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~47 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~47_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~47 .lut_mask = 16'h0055; +defparam \ula_|zx_keyboard_|keys[0][2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~49 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~49_combout = (\ula_|zx_keyboard_|keys[0][2]~47_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[0][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[0][2]~47_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[0][2]~47_combout ), + .datac(\ula_|zx_keyboard_|keys[0][2]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~49_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~49 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[0][2]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N13 +dffeas \ula_|zx_keyboard_|keys[0][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][2]~49_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N8 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [9])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [9]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N9 +dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .asdata(\z80_|address_latch_|Q [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N28 +cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( +// Equation(s): +// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [9]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[9]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N24 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [8]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [8]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N25 +dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .asdata(\z80_|address_latch_|Q [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N24 +cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( +// Equation(s): +// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [8]), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[8]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hCCFF; +defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N20 +cycloneive_lcell_comb \D[2]~42 ( +// Equation(s): +// \D[2]~42_combout = (\ula_|zx_keyboard_|keys[1][2]~q & (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][2]~q )))) # (!\ula_|zx_keyboard_|keys[1][2]~q & +// (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[1][2]~q ), + .datab(\ula_|zx_keyboard_|keys[0][2]~q ), + .datac(\z80_|address_pins_|abus[9]~17_combout ), + .datad(\z80_|address_pins_|abus[8]~18_combout ), + .cin(gnd), + .combout(\D[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~42 .lut_mask = 16'hF531; +defparam \D[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N24 +cycloneive_lcell_comb \D[2]~46 ( +// Equation(s): +// \D[2]~46_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[2]~43_combout & (\D[2]~45_combout & \D[2]~42_combout ))) + + .dataa(\D[2]~43_combout ), + .datab(\D[2]~45_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[2]~42_combout ), + .cin(gnd), + .combout(\D[2]~46_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~46 .lut_mask = 16'hF8F0; +defparam \D[2]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y14_N3 +dffeas \z80_|memory_ifc_|wait_iorqinta ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|clk_delay_|DFF_inst5~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorqinta~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N0 +cycloneive_lcell_comb \z80_|memory_ifc_|DFFE_intr_ff3~feeder ( +// Equation(s): +// \z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout = \z80_|memory_ifc_|wait_iorqinta~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|wait_iorqinta~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_intr_ff3~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|DFFE_intr_ff3~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y14_N1 +dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N8 +cycloneive_lcell_comb \z80_|control_pins_|pin_nIORQ~1 ( +// Equation(s): +// \z80_|control_pins_|pin_nIORQ~1_combout = ((!\z80_|memory_ifc_|iorq~0_combout & (!\z80_|memory_ifc_|DFFE_intr_ff3~q & !\z80_|memory_ifc_|wait_iorqinta~q ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|memory_ifc_|iorq~0_combout ), + .datab(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|wait_iorqinta~q ), + .cin(gnd), + .combout(\z80_|control_pins_|pin_nIORQ~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|control_pins_|pin_nIORQ~1 .lut_mask = 16'h0F1F; +defparam \z80_|control_pins_|pin_nIORQ~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N8 +cycloneive_lcell_comb \Equal2~0 ( +// Equation(s): +// \Equal2~0_combout = (\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|control_pins_|pin_nIORQ~1_combout ))) + + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), + .cin(gnd), + .combout(\Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~0 .lut_mask = 16'h0020; +defparam \Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N30 +cycloneive_lcell_comb \z80_|address_pins_|abus[13]~23 ( +// Equation(s): +// \z80_|address_pins_|abus[13]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[13]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[13]~23 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[13]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N18 +cycloneive_lcell_comb \ExtRamWE~0 ( +// Equation(s): +// \ExtRamWE~0_combout = (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|control_pins_|pin_nIORQ~1_combout ))) + + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), + .cin(gnd), + .combout(\ExtRamWE~0_combout ), + .cout()); +// synopsys translate_off +defparam \ExtRamWE~0 .lut_mask = 16'h4000; +defparam \ExtRamWE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N6 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h2000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y8_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|address_pins_|DFFE_apin_latch [14])) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h5000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N28 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [1]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .datab(\z80_|address_latch_|abusz [1]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N29 +dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .asdata(\z80_|address_latch_|Q [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N16 +cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( +// Equation(s): +// \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hF5F5; +defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N10 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) + + .dataa(\z80_|address_latch_|abusz [2]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hEE22; +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N11 +dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .asdata(\z80_|address_latch_|Q [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N20 +cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( +// Equation(s): +// \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [2]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[2]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N28 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [3]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [3]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y12_N29 +dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .asdata(\z80_|address_latch_|Q [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( +// Equation(s): +// \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [3]), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[3]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hCCFF; +defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N12 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [4]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .datab(\z80_|address_latch_|abusz [4]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N13 +dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .asdata(\z80_|address_latch_|Q [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N10 +cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( +// Equation(s): +// \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(\D[2]~39_combout ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [4]), .cin(gnd), - .combout(\D[2]~104_combout ), + .combout(\z80_|address_pins_|abus[4]~28_combout ), .cout()); // synopsys translate_off -defparam \D[2]~104 .lut_mask = 16'hFFF3; -defparam \D[2]~104 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF33; +defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: LCCOMB_X30_Y14_N8 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) + + .dataa(\z80_|address_latch_|abusz [5]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE22; +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N9 +dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .asdata(\z80_|address_latch_|Q [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), - .portbdataout()); + .q(\z80_|address_pins_|DFFE_apin_latch [5]), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y12_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: LCCOMB_X25_Y12_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( +// Equation(s): +// \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [5]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[5]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N18 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [6])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [6]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [6]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N19 +dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .asdata(\z80_|address_latch_|Q [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); + .q(\z80_|address_pins_|DFFE_apin_latch [6]), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y9_N0 +// Location: LCCOMB_X25_Y12_N10 +cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( +// Equation(s): +// \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [6]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[6]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N26 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) + + .dataa(\z80_|address_latch_|abusz [7]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y12_N27 +dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .asdata(\z80_|address_latch_|Q [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N12 +cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( +// Equation(s): +// \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [7]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[7]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hF5F5; +defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y5_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), @@ -49724,8 +41061,8 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -49765,7 +41102,79 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y12_N0 +// Location: FF_X24_Y19_N11 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[13]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y19_N3 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[14]~22_combout & (\ExtRamWE~0_combout & !\z80_|address_pins_|abus[13]~23_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ExtRamWE~0_combout ), + .datad(\z80_|address_pins_|abus[13]~23_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0020; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y8_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h0050; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y8_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), @@ -49781,8 +41190,8 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -49822,60 +41231,58 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N8 -cycloneive_lcell_comb \D[2]~43 ( +// Location: LCCOMB_X21_Y13_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( // Equation(s): -// \D[2]~43_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) +// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & (!\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\ExtRamWE~0_combout ), .cin(gnd), - .combout(\D[2]~43_combout ), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .cout()); // synopsys translate_off -defparam \D[2]~43 .lut_mask = 16'hB9A8; -defparam \D[2]~43 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h0800; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N6 -cycloneive_lcell_comb \D[2]~44 ( +// Location: LCCOMB_X25_Y8_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( // Equation(s): -// \D[2]~44_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~43_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout )) # (!\D[2]~43_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~43_combout )))) +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])) - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\D[2]~43_combout ), + .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), .cin(gnd), - .combout(\D[2]~44_combout ), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), .cout()); // synopsys translate_off -defparam \D[2]~44 .lut_mask = 16'hBBC0; -defparam \D[2]~44 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00A0; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y17_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(vcc), +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -49884,39 +41291,1006 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y28_N0 +// Location: FF_X25_Y19_N15 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y19_N19 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y8_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hAF0F; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y3_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N10 +cycloneive_lcell_comb \D[2]~50 ( +// Equation(s): +// \D[2]~50_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), + .cin(gnd), + .combout(\D[2]~50_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~50 .lut_mask = 16'hF838; +defparam \D[2]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N26 +cycloneive_lcell_comb \D[2]~51 ( +// Equation(s): +// \D[2]~51_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~50_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~50_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )) # (!\D[2]~50_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\D[2]~50_combout ), + .cin(gnd), + .combout(\D[2]~51_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~51 .lut_mask = 16'hEE30; +defparam \D[2]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N24 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (!\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h1000; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G15 +cycloneive_clkctrl \CLOCK_50~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\CLOCK_50~inputclkctrl_outclk )); +// synopsys translate_off +defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; +defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N30 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N8 +cycloneive_lcell_comb \ula_|video_|vram_address~0 ( +// Equation(s): +// \ula_|video_|vram_address~0_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|vram_address~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address~0 .lut_mask = 16'h1040; +defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N25 +dffeas \ula_|video_|vram_address[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N30 +cycloneive_lcell_comb \ula_|video_|vram_address[1]~feeder ( +// Equation(s): +// \ula_|video_|vram_address[1]~feeder_combout = \ula_|video_|vga_hc [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [5]), + .cin(gnd), + .combout(\ula_|video_|vram_address[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vram_address[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N31 +dffeas \ula_|video_|vram_address[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N4 +cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( +// Equation(s): +// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|video_|vram_address[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; +defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N5 +dffeas \ula_|video_|vram_address[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[2]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N22 +cycloneive_lcell_comb \ula_|video_|Add3~0 ( +// Equation(s): +// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N23 +dffeas \ula_|video_|vram_address[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N16 +cycloneive_lcell_comb \ula_|video_|Add3~1 ( +// Equation(s): +// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) + + .dataa(\ula_|video_|vga_hc [6]), + .datab(\ula_|video_|vga_hc [7]), + .datac(gnd), + .datad(\ula_|video_|vga_hc [8]), + .cin(gnd), + .combout(\ula_|video_|Add3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~1 .lut_mask = 16'h8877; +defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N17 +dffeas \ula_|video_|vram_address[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N8 +cycloneive_lcell_comb \ula_|video_|Add4~0 ( +// Equation(s): +// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) +// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add4~0_combout ), + .cout(\ula_|video_|Add4~1 )); +// synopsys translate_off +defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; +defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N10 +cycloneive_lcell_comb \ula_|video_|Add4~2 ( +// Equation(s): +// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) +// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) + + .dataa(\ula_|video_|vga_vc [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~1 ), + .combout(\ula_|video_|Add4~2_combout ), + .cout(\ula_|video_|Add4~3 )); +// synopsys translate_off +defparam \ula_|video_|Add4~2 .lut_mask = 16'hA505; +defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N12 +cycloneive_lcell_comb \ula_|video_|Add4~4 ( +// Equation(s): +// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) +// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) + + .dataa(\ula_|video_|vga_vc [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~3 ), + .combout(\ula_|video_|Add4~4_combout ), + .cout(\ula_|video_|Add4~5 )); +// synopsys translate_off +defparam \ula_|video_|Add4~4 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N14 +cycloneive_lcell_comb \ula_|video_|Add4~6 ( +// Equation(s): +// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) +// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [4]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~5 ), + .combout(\ula_|video_|Add4~6_combout ), + .cout(\ula_|video_|Add4~7 )); +// synopsys translate_off +defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y29_N15 +dffeas \ula_|video_|vram_address[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N16 +cycloneive_lcell_comb \ula_|video_|Add4~8 ( +// Equation(s): +// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) +// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) + + .dataa(\ula_|video_|vga_vc [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~7 ), + .combout(\ula_|video_|Add4~8_combout ), + .cout(\ula_|video_|Add4~9 )); +// synopsys translate_off +defparam \ula_|video_|Add4~8 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y29_N17 +dffeas \ula_|video_|vram_address[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N18 +cycloneive_lcell_comb \ula_|video_|Add4~10 ( +// Equation(s): +// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) +// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [6]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~9 ), + .combout(\ula_|video_|Add4~10_combout ), + .cout(\ula_|video_|Add4~11 )); +// synopsys translate_off +defparam \ula_|video_|Add4~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y29_N19 +dffeas \ula_|video_|vram_address[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N20 +cycloneive_lcell_comb \ula_|video_|Add4~12 ( +// Equation(s): +// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) +// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~11 ), + .combout(\ula_|video_|Add4~12_combout ), + .cout(\ula_|video_|Add4~13 )); +// synopsys translate_off +defparam \ula_|video_|Add4~12 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N28 +cycloneive_lcell_comb \ula_|video_|Selector6~0 ( +// Equation(s): +// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~12_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~0_combout )) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(gnd), + .datac(\ula_|video_|Add4~0_combout ), + .datad(\ula_|video_|Add4~12_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector6~0 .lut_mask = 16'hFA50; +defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N2 +cycloneive_lcell_comb \ula_|video_|vram_address[8]~1 ( +// Equation(s): +// \ula_|video_|vram_address[8]~1_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|vram_address[8]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[8]~1 .lut_mask = 16'h1040; +defparam \ula_|video_|vram_address[8]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y29_N29 +dffeas \ula_|video_|vram_address[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[8]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N22 +cycloneive_lcell_comb \ula_|video_|Add4~14 ( +// Equation(s): +// \ula_|video_|Add4~14_combout = \ula_|video_|vga_vc [8] $ (!\ula_|video_|Add4~13 ) + + .dataa(\ula_|video_|vga_vc [8]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|video_|Add4~13 ), + .combout(\ula_|video_|Add4~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add4~14 .lut_mask = 16'hA5A5; +defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N6 +cycloneive_lcell_comb \ula_|video_|Selector5~0 ( +// Equation(s): +// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(gnd), + .datac(\ula_|video_|Add4~14_combout ), + .datad(\ula_|video_|Add4~2_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector5~0 .lut_mask = 16'hF5A0; +defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y29_N7 +dffeas \ula_|video_|vram_address[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[8]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N28 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( +// Equation(s): +// \ula_|video_|vram_address[10]~2_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h1040; +defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N18 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( +// Equation(s): +// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) + + .dataa(\ula_|video_|vram_address[10]~2_combout ), + .datab(\ula_|video_|Add4~4_combout ), + .datac(\ula_|video_|vram_address [10]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'hD850; +defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N19 +dffeas \ula_|video_|vram_address[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[10]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N24 +cycloneive_lcell_comb \ula_|video_|Selector3~0 ( +// Equation(s): +// \ula_|video_|Selector3~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|Add4~12_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFF0; +defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y29_N25 +dffeas \ula_|video_|vram_address[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[8]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N2 +cycloneive_lcell_comb \ula_|video_|Selector2~0 ( +// Equation(s): +// \ula_|video_|Selector2~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~14_combout ) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(gnd), + .datac(\ula_|video_|Add4~14_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|video_|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFAFA; +defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y29_N3 +dffeas \ula_|video_|vram_address[12] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[8]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[12] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X22_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N28 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~23_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~23_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y19_N29 +dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N20 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|address_reg_a [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y19_N21 +dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N0 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\z80_|address_pins_|abus[14]~22_combout & (!\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~23_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h2000; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y23_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), @@ -49926,14 +42300,14 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -49989,97 +42363,83 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N12 -cycloneive_lcell_comb \D[2]~40 ( -// Equation(s): -// \D[2]~40_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .cin(gnd), - .combout(\D[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~40 .lut_mask = 16'hEA62; -defparam \D[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y31_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), +// Location: M9K_X33_Y20_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); // synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; // synopsys translate_on -// Location: M9K_X33_Y17_N0 +// Location: LCCOMB_X25_Y19_N22 +cycloneive_lcell_comb \D[2]~47 ( +// Equation(s): +// \D[2]~47_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\D[2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~47 .lut_mask = 16'hE6A2; +defparam \D[2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y32_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( .portawe(vcc), .portare(vcc), @@ -50089,14 +42449,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -50137,113 +42497,148 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N16 -cycloneive_lcell_comb \D[2]~41 ( +// Location: LCCOMB_X25_Y19_N24 +cycloneive_lcell_comb \D[2]~48 ( // Equation(s): -// \D[2]~41_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout $ (\D[2]~40_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout & ((!\D[2]~40_combout )))) +// \D[2]~48_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout $ ((\D[2]~47_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[2]~47_combout & +// \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\D[2]~40_combout ), + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\D[2]~47_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), .cin(gnd), - .combout(\D[2]~41_combout ), + .combout(\D[2]~48_combout ), .cout()); // synopsys translate_off -defparam \D[2]~41 .lut_mask = 16'h0AE4; -defparam \D[2]~41 .sum_lutc_input = "datac"; +defparam \D[2]~48 .lut_mask = 16'h4B48; +defparam \D[2]~48 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N30 -cycloneive_lcell_comb \D[2]~42 ( +// Location: LCCOMB_X25_Y19_N16 +cycloneive_lcell_comb \D[2]~49 ( // Equation(s): -// \D[2]~42_combout = (\D[2]~40_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout & !\D[2]~41_combout )))) # (!\D[2]~40_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~41_combout )))) +// \D[2]~49_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~47_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~47_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout & !\D[2]~48_combout )) # (!\D[2]~47_combout & ((\D[2]~48_combout ))))) - .dataa(\D[2]~40_combout ), + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datad(\D[2]~41_combout ), + .datac(\D[2]~47_combout ), + .datad(\D[2]~48_combout ), .cin(gnd), - .combout(\D[2]~42_combout ), + .combout(\D[2]~49_combout ), .cout()); // synopsys translate_off -defparam \D[2]~42 .lut_mask = 16'h99A8; -defparam \D[2]~42 .sum_lutc_input = "datac"; +defparam \D[2]~49 .lut_mask = 16'hC3E0; +defparam \D[2]~49 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N0 -cycloneive_lcell_comb \D[2]~105 ( +// Location: LCCOMB_X25_Y19_N6 +cycloneive_lcell_comb \D[2]~119 ( // Equation(s): -// \D[2]~105_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[2]~44_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[2]~42_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[2]~44_combout )))) +// \D[2]~119_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[2]~51_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[2]~49_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[2]~51_combout )))) - .dataa(\D[2]~44_combout ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[2]~42_combout ), + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\D[2]~51_combout ), + .datad(\D[2]~49_combout ), .cin(gnd), - .combout(\D[2]~105_combout ), + .combout(\D[2]~119_combout ), .cout()); // synopsys translate_off -defparam \D[2]~105 .lut_mask = 16'hBA8A; -defparam \D[2]~105 .sum_lutc_input = "datac"; +defparam \D[2]~119 .lut_mask = 16'hF4B0; +defparam \D[2]~119 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N28 -cycloneive_lcell_comb \D[2]~45 ( +// Location: LCCOMB_X24_Y19_N20 +cycloneive_lcell_comb \D[2]~52 ( // Equation(s): -// \D[2]~45_combout = ((\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout )))) # (!\Equal2~1_combout ) +// \D[2]~52_combout = ((\Equal2~0_combout & (\D[2]~46_combout )) # (!\Equal2~0_combout & ((\D[2]~119_combout )))) # (!\Equal2~1_combout ) - .dataa(\Equal2~0_combout ), + .dataa(\D[2]~46_combout ), .datab(\Equal2~1_combout ), - .datac(\D[2]~104_combout ), - .datad(\D[2]~105_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[2]~119_combout ), .cin(gnd), - .combout(\D[2]~45_combout ), + .combout(\D[2]~52_combout ), .cout()); // synopsys translate_off -defparam \D[2]~45 .lut_mask = 16'hF7B3; -defparam \D[2]~45 .sum_lutc_input = "datac"; +defparam \D[2]~52 .lut_mask = 16'hBFB3; +defparam \D[2]~52 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N30 -cycloneive_lcell_comb \D[2]~46 ( +// Location: LCCOMB_X24_Y19_N26 +cycloneive_lcell_comb \D[2]~53 ( // Equation(s): -// \D[2]~46_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [2] & ((\D[2]~45_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[2]~45_combout ) # (!\Equal2~1_combout )))) +// \D[2]~53_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [2] & \D[2]~52_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[2]~52_combout )) # (!\Equal2~1_combout ))) - .dataa(\z80_|data_pins_|dout [2]), + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[2]~45_combout ), + .datac(\z80_|data_pins_|dout [2]), + .datad(\D[2]~52_combout ), .cin(gnd), - .combout(\D[2]~46_combout ), + .combout(\D[2]~53_combout ), .cout()); // synopsys translate_off -defparam \D[2]~46 .lut_mask = 16'hAF03; -defparam \D[2]~46 .sum_lutc_input = "datac"; +defparam \D[2]~53 .lut_mask = 16'hF511; +defparam \D[2]~53 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N2 +// Location: LCCOMB_X29_Y12_N16 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[2]~13_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[2]~46_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[2]~46_combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|bus_control_|db[2]~13_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\D[2]~53_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|bus_control_|db[2]~13_combout & (\D[2]~53_combout +// & ((\z80_|pin_control_|bus_db_pin_re~combout )))) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\D[2]~46_combout ), - .datad(\z80_|bus_control_|db[2]~13_combout ), + .dataa(\z80_|bus_control_|db[2]~13_combout ), + .datab(\D[2]~53_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hECA0; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y12_N3 +// Location: LCCOMB_X32_Y12_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|execute_|fIORead~3_combout & ((\z80_|sequencer_|DFFE_T3_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|execute_|fIORead~3_combout & +// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|execute_|fIORead~3_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hA0EC; +defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N16 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .datac(\z80_|execute_|fMRead~36_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEC; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N17 dffeas \z80_|data_pins_|dout[2] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), @@ -50262,44 +42657,95 @@ defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N18 +// Location: LCCOMB_X29_Y12_N0 cycloneive_lcell_comb \z80_|bus_control_|db[2]~12 ( // Equation(s): -// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) +// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - .dataa(gnd), - .datab(\z80_|alu_control_|db[2]~29_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(\z80_|alu_control_|db[2]~30_combout ), + .datad(gnd), .cin(gnd), .combout(\z80_|bus_control_|db[2]~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hCF00; +defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hC4C4; defparam \z80_|bus_control_|db[2]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N12 +// Location: LCCOMB_X29_Y12_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( +// Equation(s): +// \z80_|bus_control_|db[0]~6_combout = ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (\z80_|execute_|ctl_bus_db_oe~combout )) # (!\z80_|execute_|ctl_bus_db_oe~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFFF5; +defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N10 cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( // Equation(s): // \z80_|bus_control_|db[2]~13_combout = ((\z80_|bus_control_|db[2]~12_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) .dataa(\z80_|data_pins_|dout [2]), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~combout ), - .datad(\z80_|bus_control_|db[2]~12_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|bus_control_|db[2]~12_combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[2]~13_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hBF33; +defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hB0FF; defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y12_N13 +// Location: LCCOMB_X29_Y13_N8 +cycloneive_lcell_comb \z80_|ir_|opcode[2]~feeder ( +// Equation(s): +// \z80_|ir_|opcode[2]~feeder_combout = \z80_|bus_control_|db[2]~13_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[2]~13_combout ), + .cin(gnd), + .combout(\z80_|ir_|opcode[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|ir_|opcode[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_ir_we~5_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hDDD5; +defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N9 dffeas \z80_|ir_|opcode[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[2]~13_combout ), + .d(\z80_|ir_|opcode[2]~feeder_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -50315,662 +42761,1129 @@ defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y16_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( +// Location: LCCOMB_X39_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( // Equation(s): -// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) +// \z80_|execute_|ctl_mRead~34_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .lut_mask = 16'h1500; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h2A22; +defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hFF5F; +defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~13 ( +// Equation(s): +// \z80_|alu_control_|db[6]~13_combout = (\z80_|execute_|ctl_reg_out_lo~8_combout ) # ((\z80_|alu_control_|db[6]~12_combout ) # (\z80_|execute_|ctl_sw_1d~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datab(\z80_|alu_control_|db[6]~12_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~13 .lut_mask = 16'hFEFE; +defparam \z80_|alu_control_|db[6]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( +// Equation(s): +// \z80_|alu_control_|db[6]~21_combout = (\z80_|alu_control_|out[6]~2_combout & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_control_|out[6]~2_combout & +// (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_control_|out[6]~2_combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'hF3A2; +defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( +// Equation(s): +// \z80_|alu_control_|db[6]~22_combout = (\z80_|alu_control_|db[6]~21_combout & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) + + .dataa(\z80_|alu_control_|db[6]~21_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_|db[6]~22_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'hA2A2; +defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[6]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[6]~0_combout = (\z80_|reg_file_|gdfx_temp0[6]~80_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[6]~0 .lut_mask = 16'hCCEC; +defparam \z80_|reg_file_|db_lo_ds[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N2 +cycloneive_lcell_comb \z80_|sw1_|db_down[6]~1 ( +// Equation(s): +// \z80_|sw1_|db_down[6]~1_combout = ((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) + + .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), + .datab(gnd), + .datac(\z80_|bus_control_|db[6]~9_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[6]~1 .lut_mask = 16'h55F5; +defparam \z80_|sw1_|db_down[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N20 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~23 ( +// Equation(s): +// \z80_|alu_control_|db[6]~23_combout = ((\z80_|alu_control_|db[6]~22_combout & (\z80_|reg_file_|db_lo_ds[6]~0_combout & \z80_|sw1_|db_down[6]~1_combout ))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_control_|db[6]~13_combout ), + .datab(\z80_|alu_control_|db[6]~22_combout ), + .datac(\z80_|reg_file_|db_lo_ds[6]~0_combout ), + .datad(\z80_|sw1_|db_down[6]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~23 .lut_mask = 16'hD555; +defparam \z80_|alu_control_|db[6]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N22 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( +// Equation(s): +// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~23_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(gnd), + .datad(\z80_|alu_control_|db[6]~23_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hCC44; +defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y17_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: M9K_X22_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N2 +cycloneive_lcell_comb \D[6]~103 ( +// Equation(s): +// \D[6]~103_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .cin(gnd), + .combout(\D[6]~103_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~103 .lut_mask = 16'hEA4A; +defparam \D[6]~103 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N30 +cycloneive_lcell_comb \D[6]~104 ( +// Equation(s): +// \D[6]~104_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~103_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~103_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )) # (!\D[6]~103_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\D[6]~103_combout ), + .cin(gnd), + .combout(\D[6]~104_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~104 .lut_mask = 16'hEE30; +defparam \D[6]~104 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X22_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y30_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N14 +cycloneive_lcell_comb \D[6]~100 ( +// Equation(s): +// \D[6]~100_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\z80_|address_pins_|abus[14]~22_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\z80_|address_pins_|abus[14]~22_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .cin(gnd), + .combout(\D[6]~100_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~100 .lut_mask = 16'hBCB0; +defparam \D[6]~100 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y22_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N12 +cycloneive_lcell_comb \D[6]~101 ( +// Equation(s): +// \D[6]~101_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ ((\D[6]~100_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[6]~100_combout & +// \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datac(\D[6]~100_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .cin(gnd), + .combout(\D[6]~101_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~101 .lut_mask = 16'h2D28; +defparam \D[6]~101 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N0 +cycloneive_lcell_comb \D[6]~102 ( +// Equation(s): +// \D[6]~102_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~100_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~100_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~101_combout )) # (!\D[6]~100_combout & ((\D[6]~101_combout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[6]~100_combout ), + .datad(\D[6]~101_combout ), + .cin(gnd), + .combout(\D[6]~102_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~102 .lut_mask = 16'hC3E0; +defparam \D[6]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N8 +cycloneive_lcell_comb \D[6]~127 ( +// Equation(s): +// \D[6]~127_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[6]~104_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[6]~102_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[6]~104_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\D[6]~104_combout ), + .datad(\D[6]~102_combout ), + .cin(gnd), + .combout(\D[6]~127_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~127 .lut_mask = 16'hF4B0; +defparam \D[6]~127 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y34_N8 +cycloneive_io_ibuf \raw_loader_in~input ( + .i(raw_loader_in), + .ibar(gnd), + .o(\raw_loader_in~input_o )); +// synopsys translate_off +defparam \raw_loader_in~input .bus_hold = "false"; +defparam \raw_loader_in~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N28 +cycloneive_lcell_comb \D[6]~99 ( +// Equation(s): +// \D[6]~99_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\raw_loader_in~input_o ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~1_combout ), + .combout(\D[6]~99_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00F0; -defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; +defparam \D[6]~99 .lut_mask = 16'hFFCF; +defparam \D[6]~99 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( +// Location: LCCOMB_X23_Y19_N10 +cycloneive_lcell_comb \D[6]~114 ( // Equation(s): -// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) +// \D[6]~114_combout = ((\Equal2~0_combout & ((\D[6]~99_combout ))) # (!\Equal2~0_combout & (\D[6]~127_combout ))) # (!\Equal2~1_combout ) - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), + .dataa(\Equal2~0_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[6]~127_combout ), + .datad(\D[6]~99_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal43~0_combout ), + .combout(\D[6]~114_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; +defparam \D[6]~114 .lut_mask = 16'hFB73; +defparam \D[6]~114 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N24 -cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( +// Location: LCCOMB_X23_Y19_N12 +cycloneive_lcell_comb \D[6]~115 ( // Equation(s): -// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal43~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal36~0_combout ))) +// \D[6]~115_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [6] & \D[6]~114_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[6]~114_combout )) # (!\Equal2~1_combout ))) - .dataa(\z80_|pla_decode_|Equal43~0_combout ), - .datab(\z80_|pla_decode_|Equal3~2_combout ), - .datac(\z80_|pla_decode_|Equal79~0_combout ), - .datad(\z80_|pla_decode_|Equal36~0_combout ), + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\Equal2~1_combout ), + .datac(\z80_|data_pins_|dout [6]), + .datad(\D[6]~114_combout ), .cin(gnd), - .combout(\z80_|interrupts_|test1~2_combout ), + .combout(\D[6]~115_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; -defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; +defparam \D[6]~115 .lut_mask = 16'hF511; +defparam \D[6]~115 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y15_N26 -cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( +// Location: LCCOMB_X28_Y12_N14 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( // Equation(s): -// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|interrupts_|test1~2_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\D[6]~115_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[6]~9_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[6]~115_combout & +// (((\z80_|bus_control_|db[6]~9_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|interrupts_|test1~2_combout ), + .dataa(\D[6]~115_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|bus_control_|db[6]~9_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), .cin(gnd), - .combout(\z80_|interrupts_|test1~3_combout ), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h5545; -defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y15_N13 -dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), +// Location: FF_X28_Y12_N15 +dffeas \z80_|data_pins_|dout[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N14 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( +// Equation(s): +// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[6]~8_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|data_pins_|dout [6]), + .datad(\z80_|bus_control_|db[0]~6_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'hA2FF; +defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N3 +dffeas \z80_|ir_|opcode[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[6]~9_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~0_combout = (\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6])) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h0A00; +defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal38~2_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal38~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N0 +cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Equation(s): +// \z80_|interrupts_|iff1~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|interrupts_|iff1~q ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal79~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hE4CC; +defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N4 +cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( +// Equation(s): +// \z80_|interrupts_|iff1~1_combout = (\z80_|pla_decode_|Equal38~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|interrupts_|iff1~0_combout )))) # +// (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|iff1~0_combout )) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|interrupts_|iff1~0_combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hE4CC; +defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N24 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|interrupts_|DFFE_inst44~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFF3; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N5 +dffeas \z80_|interrupts_|iff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|iff1~1_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|iff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|iff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y27_N8 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (\ula_|video_|Equal2~2_combout & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & (!\ula_|video_|vga_hc [7] & \z80_|interrupts_|iff1~q ))) + + .dataa(\ula_|video_|Equal2~2_combout ), + .datab(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), + .datac(\ula_|video_|vga_hc [7]), + .datad(\z80_|interrupts_|iff1~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0800; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y27_N9 +dffeas \z80_|interrupts_|int_armed ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|int_armed~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; +defparam \z80_|interrupts_|int_armed .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N25 +dffeas \z80_|interrupts_|DFFE_inst44 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|interrupts_|int_armed~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), .ena(\z80_|interrupts_|test1~3_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .q(\z80_|interrupts_|DFFE_inst44~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; +defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y15_N2 -cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( +// Location: LCCOMB_X30_Y11_N22 +cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( // Equation(s): -// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|interrupts_|DFFE_inst44~q ))) +// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & \z80_|decode_state_|in_halt~q )) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0100; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y15_N3 -dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N20 -cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( -// Equation(s): -// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q & !\z80_|clk_delay_|DFF_inst5~q ) - - .dataa(gnd), - .datab(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), .datac(gnd), - .datad(\z80_|clk_delay_|DFF_inst5~q ), + .datad(\z80_|decode_state_|in_halt~q ), .cin(gnd), - .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), + .combout(\z80_|decode_state_|in_halt~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0033; -defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h1100; +defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N13 -dffeas \z80_|sequencer_|DFFE_T1_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|ena_M~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T1_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N4 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0050; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N5 -dffeas \z80_|sequencer_|DFFE_T2_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T2_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N10 -cycloneive_lcell_comb \z80_|resets_|x3 ( -// Equation(s): -// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(\z80_|resets_|x1~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|resets_|x3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|x3 .lut_mask = 16'hF0FA; -defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N11 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|x3~combout ), - .asdata(vcc), - .clrn(\z80_|fpga_reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; -// synopsys translate_on - -// Location: CLKCTRL_G7 -cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: FF_X32_Y17_N21 -dffeas \z80_|sequencer_|DFFE_M1_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M1_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N10 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h22A0; -defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N11 -dffeas \z80_|sequencer_|DFFE_M2_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M2_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~3 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~3_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~3 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~11 ( -// Equation(s): -// \z80_|execute_|nextM~11_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ctl_mWrite~3_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~11 .lut_mask = 16'h5557; -defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~8 ( -// Equation(s): -// \z80_|execute_|nextM~8_combout = (\z80_|alu_control_|flags_cond_true~q & (((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) # (!\z80_|alu_control_|flags_cond_true~q & ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout -// ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~8 .lut_mask = 16'h44F4; -defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~9 ( -// Equation(s): -// \z80_|execute_|nextM~9_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # (\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~9 .lut_mask = 16'h8880; -defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|nextM~10 ( -// Equation(s): -// \z80_|execute_|nextM~10_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datab(\z80_|execute_|nextM~9_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~12 ( -// Equation(s): -// \z80_|execute_|nextM~12_combout = ((\z80_|execute_|nextM~8_combout ) # ((\z80_|execute_|nextM~10_combout ) # (\z80_|execute_|ctl_alu_op_low~32_combout ))) # (!\z80_|execute_|nextM~11_combout ) - - .dataa(\z80_|execute_|nextM~11_combout ), - .datab(\z80_|execute_|nextM~8_combout ), - .datac(\z80_|execute_|nextM~10_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|nextM~15 ( -// Equation(s): -// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|fMRead~10_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|fMRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~15 .lut_mask = 16'h80A0; -defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|nextM~6 ( -// Equation(s): -// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|ixy_d~17_combout ) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|nextM~3_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~6 .lut_mask = 16'hDF5F; -defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~7 ( -// Equation(s): -// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ixy_d~8_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|execute_|nextM~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|nextM~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~7 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~13 ( -// Equation(s): -// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~12_combout ) # ((\z80_|execute_|nextM~15_combout ) # (\z80_|execute_|nextM~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|nextM~12_combout ), - .datac(\z80_|execute_|nextM~15_combout ), - .datad(\z80_|execute_|nextM~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~39 ( -// Equation(s): -// \z80_|execute_|setM1~39_combout = (!\z80_|execute_|ctl_mWrite~5_combout & \z80_|execute_|setM1~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|setM1~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0F00; -defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~5 ( -// Equation(s): -// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~45_combout ) # (!\z80_|execute_|nextM~2_combout )) # (!\z80_|execute_|setM1~39_combout ))) - - .dataa(\z80_|execute_|setM1~39_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|setM1~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~5 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|nextM~14 ( -// Equation(s): -// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~13_combout ) # (((\z80_|execute_|nextM~5_combout ) # (!\z80_|execute_|ctl_mRead~30_combout )) # (!\z80_|execute_|ctl_mWrite~13_combout )) - - .dataa(\z80_|execute_|nextM~13_combout ), - .datab(\z80_|execute_|ctl_mWrite~13_combout ), - .datac(\z80_|execute_|ctl_mRead~30_combout ), - .datad(\z80_|execute_|nextM~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~14 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N14 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00C0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N15 -dffeas \z80_|sequencer_|DFFE_T4_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T4_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N18 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N19 -dffeas \z80_|sequencer_|DFFE_T5_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T5_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N26 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00C0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N27 -dffeas \z80_|sequencer_|T6 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|T6~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|T6 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~13 ( -// Equation(s): -// \z80_|execute_|setM1~13_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|pla_decode_|Equal33~0_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal21~2_combout )))) # (!\z80_|pla_decode_|Equal13~0_combout & -// (((!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal21~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal21~2_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~13 .lut_mask = 16'h153F; -defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N4 +// Location: LCCOMB_X34_Y11_N16 cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( // Equation(s): -// \z80_|pla_decode_|Equal77~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) +// \z80_|pla_decode_|Equal77~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal21~0_combout ))) .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), .cin(gnd), .combout(\z80_|pla_decode_|Equal77~1_combout ), .cout()); @@ -50979,660 +43892,24 @@ defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~12 ( -// Equation(s): -// \z80_|execute_|setM1~12_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|pla_decode_|Equal2~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal77~1_combout ), - .datab(\z80_|execute_|ctl_alu_oe~3_combout ), - .datac(\z80_|pla_decode_|Equal1~6_combout ), - .datad(\z80_|pla_decode_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~14 ( -// Equation(s): -// \z80_|execute_|setM1~14_combout = (\z80_|execute_|setM1~13_combout & (\z80_|interrupts_|test1~2_combout & \z80_|execute_|setM1~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|setM1~13_combout ), - .datac(\z80_|interrupts_|test1~2_combout ), - .datad(\z80_|execute_|setM1~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~14 .lut_mask = 16'hC000; -defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~41 ( -// Equation(s): -// \z80_|execute_|setM1~41_combout = (!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_ir_we~10_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~41 .lut_mask = 16'h0005; -defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~42 ( -// Equation(s): -// \z80_|execute_|setM1~42_combout = (!\z80_|pla_decode_|Equal38~2_combout & (!\z80_|pla_decode_|Equal37~0_combout & (!\z80_|pla_decode_|Equal47~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0100; -defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~43 ( -// Equation(s): -// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~41_combout & (!\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|setM1~42_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|setM1~41_combout ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|execute_|setM1~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0400; -defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~44 ( -// Equation(s): -// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (\z80_|execute_|setM1~40_combout & ((!\z80_|pla_decode_|Equal2~1_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|execute_|setM1~43_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|pla_decode_|Equal2~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~44 .lut_mask = 16'h20A0; -defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~50 ( -// Equation(s): -// \z80_|execute_|setM1~50_combout = (\z80_|execute_|setM1~46_combout & (\z80_|execute_|setM1~14_combout & (\z80_|execute_|setM1~44_combout & \z80_|execute_|setM1~49_combout ))) - - .dataa(\z80_|execute_|setM1~46_combout ), - .datab(\z80_|execute_|setM1~14_combout ), - .datac(\z80_|execute_|setM1~44_combout ), - .datad(\z80_|execute_|setM1~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~50 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~51 ( -// Equation(s): -// \z80_|execute_|setM1~51_combout = (\z80_|sequencer_|T6~q & (((\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~39_combout )) # (!\z80_|execute_|setM1~40_combout ))) # (!\z80_|sequencer_|T6~q & (\z80_|execute_|setM1~50_combout & -// ((\z80_|execute_|setM1~39_combout )))) - - .dataa(\z80_|sequencer_|T6~q ), - .datab(\z80_|execute_|setM1~50_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|execute_|setM1~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~51 .lut_mask = 16'hCE0A; -defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~6 ( -// Equation(s): -// \z80_|execute_|setM1~6_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|sequencer_|M5~q & (\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & -// \z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~6 .lut_mask = 16'hD5C0; -defparam \z80_|execute_|setM1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~7 ( -// Equation(s): -// \z80_|execute_|setM1~7_combout = ((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|setM1~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~7 .lut_mask = 16'hF333; -defparam \z80_|execute_|setM1~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~8 ( -// Equation(s): -// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|fMWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~8 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~9 ( -// Equation(s): -// \z80_|execute_|setM1~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~9 .lut_mask = 16'hF1F0; -defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~10 ( -// Equation(s): -// \z80_|execute_|setM1~10_combout = ((\z80_|execute_|setM1~8_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout & \z80_|execute_|setM1~9_combout ))) # (!\z80_|execute_|nextM~2_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|setM1~8_combout ), - .datad(\z80_|execute_|setM1~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~11 ( -// Equation(s): -// \z80_|execute_|setM1~11_combout = (\z80_|execute_|setM1~7_combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|setM1~10_combout )) # (!\z80_|reg_control_|reg_sel_pc~3_combout )) - - .dataa(\z80_|execute_|setM1~7_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|setM1~10_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~11 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~17 ( -// Equation(s): -// \z80_|execute_|setM1~17_combout = ((\z80_|execute_|setM1~11_combout ) # ((!\z80_|execute_|setM1~14_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|setM1~16_combout ) - - .dataa(\z80_|execute_|setM1~16_combout ), - .datab(\z80_|execute_|setM1~14_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~17 .lut_mask = 16'hFF75; -defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~31 ( -// Equation(s): -// \z80_|execute_|setM1~31_combout = (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout & \z80_|execute_|ctl_mRead~18_combout )))) # (!\z80_|pla_decode_|Equal35~0_combout & -// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|execute_|ctl_mRead~18_combout )))) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~31 .lut_mask = 16'hECA0; -defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~28 ( -// Equation(s): -// \z80_|execute_|setM1~28_combout = ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~30 ( -// Equation(s): -// \z80_|execute_|setM1~30_combout = (((\z80_|execute_|ctl_state_alu~6_combout & \z80_|execute_|setM1~28_combout )) # (!\z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~54_combout ) - - .dataa(\z80_|execute_|setM1~54_combout ), - .datab(\z80_|execute_|setM1~29_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|setM1~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~30 .lut_mask = 16'hF777; -defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~32 ( -// Equation(s): -// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|setM1~9_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|setM1~9_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~32 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~33 ( -// Equation(s): -// \z80_|execute_|setM1~33_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~30_combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|setM1~32_combout ))) - - .dataa(\z80_|execute_|setM1~31_combout ), - .datab(\z80_|execute_|setM1~30_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|setM1~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~25 ( -// Equation(s): -// \z80_|execute_|setM1~25_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~25 .lut_mask = 16'hAF0F; -defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~26 ( -// Equation(s): -// \z80_|execute_|setM1~26_combout = ((\z80_|execute_|ctl_mRead~13_combout ) # ((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~26 .lut_mask = 16'hF7F5; -defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~24 ( -// Equation(s): -// \z80_|execute_|setM1~24_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_mRead~12_combout ))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & ((!\z80_|alu_control_|flags_cond_true~q )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|alu_control_|flags_cond_true~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~24 .lut_mask = 16'h0ACE; -defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~27 ( -// Equation(s): -// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|setM1~25_combout ) # (\z80_|execute_|setM1~26_combout )))) - - .dataa(\z80_|execute_|setM1~25_combout ), - .datab(\z80_|execute_|setM1~26_combout ), - .datac(\z80_|execute_|setM1~24_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~27 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~22 ( -// Equation(s): -// \z80_|execute_|setM1~22_combout = (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|execute_|fMWrite~9_combout & (!\z80_|execute_|ctl_mRead~8_combout & \z80_|execute_|fMWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|fMWrite~9_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~22 .lut_mask = 16'h0400; -defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~21 ( -// Equation(s): -// \z80_|execute_|setM1~21_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|decode_state_|DFFE_instNonRep~q ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~21 .lut_mask = 16'hF1F0; -defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~53 ( -// Equation(s): -// \z80_|execute_|setM1~53_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|execute_|setM1~21_combout & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~21_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~53 .lut_mask = 16'hC888; -defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~23 ( -// Equation(s): -// \z80_|execute_|setM1~23_combout = (\z80_|execute_|setM1~22_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) # (!\z80_|execute_|setM1~22_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # -// ((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) - - .dataa(\z80_|execute_|setM1~22_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|setM1~53_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~23 .lut_mask = 16'h4F44; -defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~18 ( -// Equation(s): -// \z80_|execute_|setM1~18_combout = (\z80_|execute_|ctl_mRead~11_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~18 .lut_mask = 16'h08CC; -defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~19 ( -// Equation(s): -// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~18_combout ) # ((\z80_|execute_|ixy_d~8_combout & (\z80_|pla_decode_|Equal10~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ))) - - .dataa(\z80_|execute_|setM1~18_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~19 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~20 ( -// Equation(s): -// \z80_|execute_|setM1~20_combout = ((\z80_|execute_|setM1~19_combout ) # ((\z80_|execute_|ctl_iorw~11_combout & \z80_|execute_|ctl_mWrite~3_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datad(\z80_|execute_|setM1~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~20 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~34 ( -// Equation(s): -// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~33_combout ) # ((\z80_|execute_|setM1~27_combout ) # ((\z80_|execute_|setM1~23_combout ) # (\z80_|execute_|setM1~20_combout ))) - - .dataa(\z80_|execute_|setM1~33_combout ), - .datab(\z80_|execute_|setM1~27_combout ), - .datac(\z80_|execute_|setM1~23_combout ), - .datad(\z80_|execute_|setM1~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~52 ( -// Equation(s): -// \z80_|execute_|setM1~52_combout = (!\z80_|execute_|setM1~17_combout & (!\z80_|execute_|setM1~34_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~51_combout )))) - - .dataa(\z80_|execute_|setM1~51_combout ), - .datab(\z80_|execute_|setM1~17_combout ), - .datac(\z80_|execute_|setM1~34_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~52 .lut_mask = 16'h0301; -defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N24 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N25 -dffeas \z80_|sequencer_|DFFE_T3_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T3_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N24 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( -// Equation(s): -// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|decode_state_|in_halt~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h0050; -defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N24 +// Location: LCCOMB_X30_Y11_N12 cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( // Equation(s): -// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|decode_state_|in_halt~q & \z80_|pla_decode_|Equal77~1_combout ))) +// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|pla_decode_|Equal77~1_combout & (!\z80_|decode_state_|in_halt~q & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|decode_state_|in_halt~0_combout ), + .dataa(\z80_|decode_state_|in_halt~0_combout ), + .datab(\z80_|pla_decode_|Equal77~1_combout ), .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|pla_decode_|Equal77~1_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), .cin(gnd), .combout(\z80_|decode_state_|in_halt~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hCECC; +defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hAEAA; defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y13_N25 +// Location: FF_X30_Y11_N13 dffeas \z80_|decode_state_|in_halt ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|decode_state_|in_halt~1_combout ), @@ -51651,434 +43928,489 @@ defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; defparam \z80_|decode_state_|in_halt .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Location: LCCOMB_X34_Y6_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_zero_oe~0_combout & (!\z80_|execute_|ctl_bus_ff_oe~1_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) +// \z80_|execute_|ctl_mRead~21_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal77~0_combout ))) .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .combout(\z80_|execute_|ctl_mRead~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0031; -defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( +// Location: LCCOMB_X34_Y6_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|pla_decode_|Equal41~2_combout ))) +// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|ctl_mRead~21_combout ) # (((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|fMWrite~0_combout )) # (!\z80_|execute_|fMRead~7_combout )) + + .dataa(\z80_|execute_|ctl_mRead~21_combout ), + .datab(\z80_|execute_|fMRead~7_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|fMWrite~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( +// Equation(s): +// \z80_|execute_|fMRead~23_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|fMRead~4_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|fMRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hA2AA; +defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( +// Equation(s): +// \z80_|execute_|fMRead~27_combout = ((\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ixy_d~4_combout & \z80_|sequencer_|DFFE_M2_ff~q ))) # (!\z80_|execute_|fMRead~26_combout ) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|fMRead~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~27 .lut_mask = 16'h20FF; +defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Equation(s): +// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|pla_decode_|Equal41~2_combout ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hFB33; +defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( +// Equation(s): +// \z80_|execute_|fMRead~29_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((\z80_|ir_|opcode [7]) # (\z80_|ir_|opcode [6])))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|fMRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC080; +defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( +// Equation(s): +// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~10_combout ) # ((\z80_|execute_|ctl_ir_we~9_combout ) # (\z80_|execute_|fMRead~29_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|fMRead~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( +// Equation(s): +// \z80_|execute_|fMRead~31_combout = (\z80_|pla_decode_|Equal33~3_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal33~3_combout & (\z80_|pla_decode_|Equal6~1_combout & +// ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Equation(s): +// \z80_|execute_|fMRead~32_combout = (\z80_|execute_|fMRead~28_combout ) # ((\z80_|execute_|fMRead~30_combout ) # ((\z80_|execute_|fMRead~31_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ))) + + .dataa(\z80_|execute_|fMRead~28_combout ), + .datab(\z80_|execute_|fMRead~30_combout ), + .datac(\z80_|execute_|fMRead~31_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~37 ( +// Equation(s): +// \z80_|execute_|fMRead~37_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_mRead~13_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~37 .lut_mask = 16'h0E00; +defparam \z80_|execute_|fMRead~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Equation(s): +// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~27_combout ) # (((\z80_|execute_|fMRead~32_combout ) # (\z80_|execute_|fMRead~37_combout )) # (!\z80_|execute_|fMRead~6_combout )) + + .dataa(\z80_|execute_|fMRead~27_combout ), + .datab(\z80_|execute_|fMRead~6_combout ), + .datac(\z80_|execute_|fMRead~32_combout ), + .datad(\z80_|execute_|fMRead~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( +// Equation(s): +// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & (\z80_|execute_|ctl_alu_oe~2_combout & +// ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~16_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ctl_mRead~16_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~24 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( +// Equation(s): +// \z80_|execute_|fMRead~25_combout = ((\z80_|execute_|fMRead~24_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~33_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|pc_inc_hold~33_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|fMRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~25 .lut_mask = 16'hFF2F; +defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( +// Equation(s): +// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_ir_we~12_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~21_combout ) # (\z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_mRead~21_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~16 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( +// Equation(s): +// \z80_|execute_|fMRead~11_combout = ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ctl_mRead~21_combout ) # (!\z80_|execute_|nextM~3_combout ))) # (!\z80_|execute_|pc_inc_hold~14_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~14_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_mRead~21_combout ), + .datad(\z80_|execute_|nextM~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Equation(s): +// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (!\z80_|execute_|ctl_mRead~2_combout & (!\z80_|pla_decode_|Equal6~1_combout & !\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datab(\z80_|execute_|ctl_mRead~2_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~12 .lut_mask = 16'h0002; +defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Equation(s): +// \z80_|execute_|fMRead~13_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|fMRead~11_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # (!\z80_|execute_|fMRead~12_combout )))) + + .dataa(\z80_|execute_|fMRead~11_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|fMRead~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~13 .lut_mask = 16'hC8CC; +defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Equation(s): +// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout ))) .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFBFA; +defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N10 +cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Equation(s): +// \z80_|execute_|fMRead~15_combout = (!\z80_|execute_|fMWrite~2_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|fMRead~14_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|fMWrite~2_combout ), .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|fMRead~14_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .combout(\z80_|execute_|fMRead~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~15 .lut_mask = 16'h3332; +defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( +// Location: LCCOMB_X34_Y6_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_bus_db_oe~5_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) +// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~15_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|fMRead~16_combout ))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|fMRead~16_combout ), + .datac(\z80_|execute_|fMRead~13_combout ), + .datad(\z80_|execute_|fMRead~15_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .combout(\z80_|execute_|fMRead~17_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFDF5; -defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~17 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( +// Location: LCCOMB_X34_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) +// \z80_|execute_|fMRead~22_combout = (((\z80_|execute_|fMRead~17_combout ) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|fMRead~21_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datab(\z80_|execute_|fMRead~21_combout ), + .datac(\z80_|execute_|fMRead~17_combout ), + .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( +// Equation(s): +// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|fMRead~23_combout ) # ((\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|fMRead~25_combout ) # (\z80_|execute_|fMRead~22_combout ))) + + .dataa(\z80_|execute_|fMRead~23_combout ), + .datab(\z80_|execute_|fMRead~33_combout ), + .datac(\z80_|execute_|fMRead~25_combout ), + .datad(\z80_|execute_|fMRead~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~36 ( +// Equation(s): +// \z80_|execute_|fMRead~36_combout = (\z80_|execute_|fMRead~34_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((\z80_|execute_|fMRead~35_combout & !\z80_|execute_|fMRead~2_combout ))) + + .dataa(\z80_|execute_|fMRead~35_combout ), + .datab(\z80_|execute_|fMRead~34_combout ), + .datac(\z80_|execute_|fMRead~2_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~36 .lut_mask = 16'hFFCE; +defparam \z80_|execute_|fMRead~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout )) .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|fMRead~36_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .combout(\z80_|pin_control_|bus_db_pin_re~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; -defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; +defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFC0; +defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Location: LCCOMB_X21_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~103 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (\z80_|execute_|ctl_bus_db_oe~4_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hAAA2; -defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( -// Equation(s): -// \z80_|bus_control_|db[0]~6_combout = (\z80_|execute_|ctl_bus_db_oe~combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) - - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFAFF; -defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~93 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~93_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~47_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~93_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~93 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[1][3]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~94 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~94_combout = (\ula_|zx_keyboard_|keys[1][3]~93_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # -// (!\ula_|zx_keyboard_|keys[1][3]~93_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[1][3]~93_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~94 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][3]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N31 -dffeas \ula_|zx_keyboard_|keys[1][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) +// \ula_|zx_keyboard_|keys[5][3]~103_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5])) .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .combout(\ula_|zx_keyboard_|keys[5][3]~103_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][3]~103 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|keys[5][3]~103 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~98 ( +// Location: LCCOMB_X20_Y10_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~20 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~98_combout = (\ula_|zx_keyboard_|keys[0][3]~96_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & -// (\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][3]~96_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) +// \ula_|zx_keyboard_|keys[5][4]~20_combout = (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) - .dataa(\ula_|zx_keyboard_|keys[0][3]~96_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .datac(\ula_|zx_keyboard_|keys[0][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~98_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~98 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[0][3]~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N1 -dffeas \ula_|zx_keyboard_|keys[0][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][3]~98_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N4 -cycloneive_lcell_comb \D[3]~65 ( -// Equation(s): -// \D[3]~65_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][3]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][3]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][3]~q ), - .cin(gnd), - .combout(\D[3]~65_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~65 .lut_mask = 16'h8CAF; -defparam \D[3]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~99 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~99_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), .datad(gnd), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~99_combout ), + .combout(\ula_|zx_keyboard_|keys[5][4]~20_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~99 .lut_mask = 16'h4040; -defparam \ula_|zx_keyboard_|keys[3][3]~99 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][4]~20 .lut_mask = 16'hC0C0; +defparam \ula_|zx_keyboard_|keys[5][4]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~100 ( +// Location: LCCOMB_X20_Y10_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~21 ( // Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~100_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[3][3]~99_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][3]~99_combout & (\ula_|zx_keyboard_|keys[3][3]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[3][3]~q )))) +// \ula_|zx_keyboard_|keys[1][4]~21_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) - .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .datab(\ula_|zx_keyboard_|keys[3][3]~99_combout ), - .datac(\ula_|zx_keyboard_|keys[3][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~100_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~100 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[3][3]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N9 -dffeas \ula_|zx_keyboard_|keys[3][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][3]~100_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'hCCDD; -defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .combout(\ula_|zx_keyboard_|keys[1][4]~21_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[1][4]~21 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[1][4]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~133 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~133_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][3]~102_combout & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|zx_keyboard_|keys[2][3]~102_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~133_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~133 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[2][3]~133 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~103 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~103_combout = (\ula_|zx_keyboard_|keys[2][3]~133_combout & (!\ula_|zx_keyboard_|keys[2][3]~101_combout )) # (!\ula_|zx_keyboard_|keys[2][3]~133_combout & ((\ula_|zx_keyboard_|keys[2][3]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[2][3]~101_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][3]~133_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~103 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[2][3]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N3 -dffeas \ula_|zx_keyboard_|keys[2][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N28 -cycloneive_lcell_comb \D[3]~66 ( -// Equation(s): -// \D[3]~66_combout = (\z80_|address_pins_|abus[11]~19_combout & (((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & -// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[3][3]~q ), - .datac(\z80_|address_pins_|abus[10]~24_combout ), - .datad(\ula_|zx_keyboard_|keys[2][3]~q ), - .cin(gnd), - .combout(\D[3]~66_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~66 .lut_mask = 16'hB0BB; -defparam \D[3]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N12 +// Location: LCCOMB_X21_Y8_N24 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) +// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|zx_keyboard_|keys[5][3]~103_combout & ((\ula_|zx_keyboard_|keys[1][4]~21_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][4]~21_combout & ((\ula_|zx_keyboard_|keys[5][3]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][3]~103_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(gnd), + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[5][3]~103_combout ), + .datac(\ula_|zx_keyboard_|keys[5][3]~q ), + .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h0808; +defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h74F0; defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y19_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~105 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~105_combout = (\ula_|zx_keyboard_|keys[5][3]~104_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[5][3]~q -// )))) # (!\ula_|zx_keyboard_|keys[5][3]~104_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][3]~104_combout ), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[5][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~105_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~105 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][3]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N23 +// Location: FF_X21_Y8_N25 dffeas \ula_|zx_keyboard_|keys[5][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][3]~105_combout ), + .d(\ula_|zx_keyboard_|keys[5][3]~104_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52094,32 +44426,49 @@ defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y19_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( +// Location: LCCOMB_X19_Y9_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~73 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|WideOr16~2_combout ))) +// \ula_|zx_keyboard_|keys[3][0]~73_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1])) - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .combout(\ula_|zx_keyboard_|keys[3][0]~73_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[3][0]~73 .lut_mask = 16'h0500; +defparam \ula_|zx_keyboard_|keys[3][0]~73 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( +// Location: LCCOMB_X19_Y10_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( // Equation(s): -// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) +// \ula_|zx_keyboard_|Selector5~0_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[3][0]~73_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]))) .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|zx_keyboard_|keys[3][0]~73_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), .cin(gnd), .combout(\ula_|zx_keyboard_|Selector5~1_combout ), .cout()); @@ -52128,96 +44477,113 @@ defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h0800; defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( +// Location: LCCOMB_X19_Y10_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~129 ( // Equation(s): -// \ula_|zx_keyboard_|Selector5~0_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5]))) +// \ula_|zx_keyboard_|keys[4][3]~129_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|Selector5~1_combout ))) - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~134 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~134_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|zx_keyboard_|Selector5~1_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|Selector5~1_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), .datab(\ula_|zx_keyboard_|Selector5~0_combout ), .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|Selector5~1_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~134_combout ), + .combout(\ula_|zx_keyboard_|keys[4][3]~129_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~134 .lut_mask = 16'hCECC; -defparam \ula_|zx_keyboard_|keys[4][3]~134 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[4][3]~129 .lut_mask = 16'hCECC; +defparam \ula_|zx_keyboard_|keys[4][3]~129 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N6 +// Location: LCCOMB_X21_Y10_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~1 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~1_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~1 .lut_mask = 16'h0030; +defparam \ula_|zx_keyboard_|WideOr16~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~105 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~105_combout = (\ula_|zx_keyboard_|WideOr16~1_combout & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) + + .dataa(\ula_|zx_keyboard_|WideOr16~1_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~105_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~105 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][3]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|zx_keyboard_|extended~q & (((\ula_|zx_keyboard_|keys[4][3]~105_combout )))) # (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~129_combout & (\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~129_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[4][3]~105_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'hEC20; +defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~130 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~130_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~130_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~130 .lut_mask = 16'hAAAE; +defparam \ula_|zx_keyboard_|keys[4][3]~130 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N2 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~107 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~106_combout )) # (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][3]~134_combout )))) +// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & ((\ula_|zx_keyboard_|keys[4][3]~106_combout & ((!\ula_|zx_keyboard_|keys[4][3]~130_combout ))) # (!\ula_|zx_keyboard_|keys[4][3]~106_combout & +// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) - .dataa(\ula_|zx_keyboard_|extended~q ), + .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), .datab(\ula_|zx_keyboard_|keys[4][3]~106_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][3]~134_combout ), + .datac(\ula_|zx_keyboard_|keys[4][3]~q ), + .datad(\ula_|zx_keyboard_|keys[4][3]~130_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[4][3]~107_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'hD888; +defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'h70F8; defparam \ula_|zx_keyboard_|keys[4][3]~107 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~135 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~135_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q ))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~135_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~135 .lut_mask = 16'hCDCC; -defparam \ula_|zx_keyboard_|keys[4][3]~135 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~108 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~108_combout = (\ula_|zx_keyboard_|keys[4][3]~107_combout & ((\ula_|zx_keyboard_|keys[0][0]~15_combout & ((!\ula_|zx_keyboard_|keys[4][3]~135_combout ))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & -// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[4][3]~107_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~107_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\ula_|zx_keyboard_|keys[4][3]~135_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~108_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~108 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][3]~108 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N23 +// Location: FF_X21_Y8_N3 dffeas \ula_|zx_keyboard_|keys[4][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][3]~108_combout ), + .d(\ula_|zx_keyboard_|keys[4][3]~107_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52233,79 +44599,257 @@ defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y19_N20 -cycloneive_lcell_comb \D[3]~67 ( +// Location: LCCOMB_X21_Y8_N12 +cycloneive_lcell_comb \D[3]~74 ( // Equation(s): -// \D[3]~67_combout = (\ula_|zx_keyboard_|keys[5][3]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][3]~q & -// (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) +// \D[3]~74_combout = (\z80_|address_pins_|abus[12]~24_combout & (((\z80_|address_pins_|abus[13]~23_combout )) # (!\ula_|zx_keyboard_|keys[5][3]~q ))) # (!\z80_|address_pins_|abus[12]~24_combout & (!\ula_|zx_keyboard_|keys[4][3]~q & +// ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) - .dataa(\ula_|zx_keyboard_|keys[5][3]~q ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), + .dataa(\z80_|address_pins_|abus[12]~24_combout ), + .datab(\ula_|zx_keyboard_|keys[5][3]~q ), + .datac(\z80_|address_pins_|abus[13]~23_combout ), + .datad(\ula_|zx_keyboard_|keys[4][3]~q ), .cin(gnd), - .combout(\D[3]~67_combout ), + .combout(\D[3]~74_combout ), .cout()); // synopsys translate_off -defparam \D[3]~67 .lut_mask = 16'hDD0D; -defparam \D[3]~67 .sum_lutc_input = "datac"; +defparam \D[3]~74 .lut_mask = 16'hA2F3; +defparam \D[3]~74 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~112 ( +// Location: LCCOMB_X20_Y8_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~112_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~32_combout ) # ((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~61_combout )))) +// \ula_|zx_keyboard_|keys[5][1]~39_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[0][0]~11_combout & !\ula_|zx_keyboard_|extended~q )) - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~112_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~112 .lut_mask = 16'hA888; -defparam \ula_|zx_keyboard_|keys[7][3]~112 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~113 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~113_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][3]~112_combout & (\ula_|zx_keyboard_|keys[0][0]~15_combout & !\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[7][3]~112_combout ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[0][0]~11_combout ), .datad(\ula_|zx_keyboard_|extended~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~113_combout ), + .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~113 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[7][3]~113 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~114 ( +// Location: LCCOMB_X21_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~100 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~114_combout = (\ula_|zx_keyboard_|keys[7][3]~113_combout & ((!\ula_|zx_keyboard_|keys[0][4]~111_combout ))) # (!\ula_|zx_keyboard_|keys[7][3]~113_combout & (\ula_|zx_keyboard_|keys[7][3]~q )) +// \ula_|zx_keyboard_|keys[2][3]~100_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & +// !\ula_|ps2_keyboard_|shiftreg [2])) .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[7][3]~113_combout ), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~111_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .combout(\ula_|zx_keyboard_|keys[2][3]~100_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~114 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[7][3]~114 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][3]~100 .lut_mask = 16'h0C30; +defparam \ula_|zx_keyboard_|keys[2][3]~100 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y20_N9 +// Location: LCCOMB_X21_Y10_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|keys[2][3]~100_combout & (\ula_|zx_keyboard_|keys[5][4]~59_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (!\ula_|ps2_keyboard_|shiftreg [3])))) + + .dataa(\ula_|zx_keyboard_|keys[2][3]~100_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[5][4]~59_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'h8200; +defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~99 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~99_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~99 .lut_mask = 16'hF0F5; +defparam \ula_|zx_keyboard_|keys[2][3]~99 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & ((\ula_|zx_keyboard_|keys[2][3]~101_combout & ((!\ula_|zx_keyboard_|keys[2][3]~99_combout ))) # (!\ula_|zx_keyboard_|keys[2][3]~101_combout & +// (\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~39_combout & (((\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .datab(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .datac(\ula_|zx_keyboard_|keys[2][3]~q ), + .datad(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y7_N23 +dffeas \ula_|zx_keyboard_|keys[2][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~97 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~97_combout = (\ula_|zx_keyboard_|keys[6][4]~44_combout & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[5][4]~59_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~44_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[5][4]~59_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~97_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~97 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[3][3]~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~98 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~98_combout = (\ula_|zx_keyboard_|keys[3][3]~97_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][3]~97_combout & ((\ula_|zx_keyboard_|keys[3][3]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][3]~97_combout ), + .datac(\ula_|zx_keyboard_|keys[3][3]~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~98_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~98 .lut_mask = 16'h7474; +defparam \ula_|zx_keyboard_|keys[3][3]~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y7_N25 +dffeas \ula_|zx_keyboard_|keys[3][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][3]~98_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N20 +cycloneive_lcell_comb \D[3]~73 ( +// Equation(s): +// \D[3]~73_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~20_combout ) # ((!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & +// ((\z80_|address_pins_|abus[10]~20_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\z80_|address_pins_|abus[10]~20_combout ), + .datac(\ula_|zx_keyboard_|keys[2][3]~q ), + .datad(\ula_|zx_keyboard_|keys[3][3]~q ), + .cin(gnd), + .combout(\D[3]~73_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~73 .lut_mask = 16'h8ACF; +defparam \D[3]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~108 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~108_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~108 .lut_mask = 16'hFAF0; +defparam \ula_|zx_keyboard_|keys[0][4]~108 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~109 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~109_combout = (\ula_|zx_keyboard_|WideOr16~1_combout & ((\ula_|zx_keyboard_|keys[7][2]~28_combout ) # ((\ula_|zx_keyboard_|keys[7][2]~57_combout & \ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~57_combout ), + .datab(\ula_|zx_keyboard_|keys[7][2]~28_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|WideOr16~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~109_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~109 .lut_mask = 16'hEC00; +defparam \ula_|zx_keyboard_|keys[7][3]~109 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~110 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~110_combout = (\ula_|zx_keyboard_|keys[7][3]~109_combout & ((\ula_|zx_keyboard_|keys[7][2]~56_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[7][2]~56_combout & +// ((\ula_|zx_keyboard_|keys[7][3]~q ))))) # (!\ula_|zx_keyboard_|keys[7][3]~109_combout & (((\ula_|zx_keyboard_|keys[7][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .datab(\ula_|zx_keyboard_|keys[7][3]~109_combout ), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\ula_|zx_keyboard_|keys[7][2]~56_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~110_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~110 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[7][3]~110 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y8_N23 dffeas \ula_|zx_keyboard_|keys[7][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .d(\ula_|zx_keyboard_|keys[7][3]~110_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52321,79 +44865,79 @@ defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~109 ( +// Location: LCCOMB_X20_Y8_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~111 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~109_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [5]))) +// \ula_|zx_keyboard_|keys[6][3]~111_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), .datad(\ula_|ps2_keyboard_|shiftreg [5]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~109_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~111_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~109 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|keys[6][3]~109 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~111 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][3]~111 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~110 ( +// Location: LCCOMB_X20_Y8_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~112 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~110_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~109_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][2]~32_combout ))) +// \ula_|zx_keyboard_|keys[6][3]~112_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~111_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & ((\ula_|zx_keyboard_|keys[7][2]~28_combout )))) .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|zx_keyboard_|keys[6][3]~109_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|zx_keyboard_|keys[6][3]~111_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~112_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~110 .lut_mask = 16'hF088; -defparam \ula_|zx_keyboard_|keys[6][3]~110 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~112 .lut_mask = 16'hCAC0; +defparam \ula_|zx_keyboard_|keys[6][3]~112 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~137 ( +// Location: LCCOMB_X20_Y8_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~132 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~137_combout = (\ula_|zx_keyboard_|extended~q ) # (((!\ula_|zx_keyboard_|keys[0][0]~15_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][3]~110_combout )) +// \ula_|zx_keyboard_|keys[6][3]~132_combout = (((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][3]~112_combout )) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout ) - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .datab(\ula_|zx_keyboard_|keys[6][3]~112_combout ), .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~132_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~137 .lut_mask = 16'hBFFF; -defparam \ula_|zx_keyboard_|keys[6][3]~137 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~132 .lut_mask = 16'hFF7F; +defparam \ula_|zx_keyboard_|keys[6][3]~132 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~138 ( +// Location: LCCOMB_X23_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~133 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~138_combout = (\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~137_combout & ((\ula_|zx_keyboard_|keys[6][3]~q ))) # (!\ula_|zx_keyboard_|keys[6][3]~137_combout & -// (!\ula_|zx_keyboard_|Selector13~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|zx_keyboard_|keys[6][3]~q )))) +// \ula_|zx_keyboard_|keys[6][3]~133_combout = (\ula_|zx_keyboard_|keys[6][3]~132_combout & (((\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[6][3]~132_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & +// ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[6][3]~q )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|Selector13~0_combout ), + .dataa(\ula_|zx_keyboard_|keys[6][3]~132_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), .datac(\ula_|zx_keyboard_|keys[6][3]~q ), - .datad(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .datad(\ula_|zx_keyboard_|Selector13~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~133_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~138 .lut_mask = 16'hF072; -defparam \ula_|zx_keyboard_|keys[6][3]~138 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~133 .lut_mask = 16'hB0F4; +defparam \ula_|zx_keyboard_|keys[6][3]~133 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y21_N29 +// Location: FF_X23_Y8_N5 dffeas \ula_|zx_keyboard_|keys[6][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .d(\ula_|zx_keyboard_|keys[6][3]~133_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52409,115 +44953,220 @@ defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( +// Location: LCCOMB_X23_Y8_N30 +cycloneive_lcell_comb \D[3]~75 ( // Equation(s): -// \ula_|zx_keyboard_|key_row~2_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # ((!\ula_|zx_keyboard_|keys[6][3]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) +// \D[3]~75_combout = (\ula_|zx_keyboard_|keys[7][3]~q & (\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[7][3]~q & +// ((\z80_|address_pins_|abus[14]~22_combout ) # ((!\ula_|zx_keyboard_|keys[6][3]~q )))) - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [14]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|zx_keyboard_|keys[6][3]~q ), + .dataa(\ula_|zx_keyboard_|keys[7][3]~q ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ula_|zx_keyboard_|keys[6][3]~q ), + .datad(\z80_|address_pins_|abus[15]~21_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~2_combout ), + .combout(\D[3]~75_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hCFFF; -defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; +defparam \D[3]~75 .lut_mask = 16'hCF45; +defparam \D[3]~75 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N8 -cycloneive_lcell_comb \D[3]~68 ( +// Location: LCCOMB_X23_Y8_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~94 ( // Equation(s): -// \D[3]~68_combout = (\D[3]~67_combout & (\ula_|zx_keyboard_|key_row~2_combout & ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) +// \ula_|zx_keyboard_|keys[0][3]~94_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\D[3]~67_combout ), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|key_row~2_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\D[3]~68_combout ), + .combout(\ula_|zx_keyboard_|keys[0][3]~94_combout ), .cout()); // synopsys translate_off -defparam \D[3]~68 .lut_mask = 16'h8C00; -defparam \D[3]~68 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[0][3]~94 .lut_mask = 16'h2004; +defparam \ula_|zx_keyboard_|keys[0][3]~94 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N30 -cycloneive_lcell_comb \D[3]~69 ( +// Location: LCCOMB_X23_Y8_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~93 ( // Equation(s): -// \D[3]~69_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[3]~65_combout & (\D[3]~66_combout & \D[3]~68_combout ))) +// \ula_|zx_keyboard_|keys[2][4]~93_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|shifted~q )) - .dataa(\D[3]~65_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[3]~66_combout ), - .datad(\D[3]~68_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), .cin(gnd), - .combout(\D[3]~69_combout ), + .combout(\ula_|zx_keyboard_|keys[2][4]~93_combout ), .cout()); // synopsys translate_off -defparam \D[3]~69 .lut_mask = 16'hECCC; -defparam \D[3]~69 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][4]~93 .lut_mask = 16'hF0FA; +defparam \ula_|zx_keyboard_|keys[2][4]~93 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y11_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: LCCOMB_X23_Y7_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~95 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~95_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~95 .lut_mask = 16'h0060; +defparam \ula_|zx_keyboard_|keys[0][4]~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|zx_keyboard_|keys[0][3]~94_combout & ((\ula_|zx_keyboard_|keys[0][4]~95_combout & (!\ula_|zx_keyboard_|keys[2][4]~93_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & +// ((\ula_|zx_keyboard_|keys[0][3]~q ))))) # (!\ula_|zx_keyboard_|keys[0][3]~94_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][3]~94_combout ), + .datab(\ula_|zx_keyboard_|keys[2][4]~93_combout ), + .datac(\ula_|zx_keyboard_|keys[0][3]~q ), + .datad(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y8_N3 +dffeas \ula_|zx_keyboard_|keys[0][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), - .portbdataout()); + .q(\ula_|zx_keyboard_|keys[0][3]~q ), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; // synopsys translate_on -// Location: M9K_X22_Y15_N0 +// Location: LCCOMB_X19_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~91 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~91_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][4]~15_combout & \ula_|zx_keyboard_|keys[6][4]~43_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[7][4]~15_combout ), + .datad(\ula_|zx_keyboard_|keys[6][4]~43_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~91_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~91 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[1][3]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~92 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~92_combout = (\ula_|zx_keyboard_|keys[1][3]~91_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # +// (!\ula_|zx_keyboard_|keys[1][3]~91_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][3]~91_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~92 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][3]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y9_N5 +dffeas \ula_|zx_keyboard_|keys[1][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N8 +cycloneive_lcell_comb \D[3]~72 ( +// Equation(s): +// \D[3]~72_combout = (\z80_|address_pins_|abus[9]~17_combout & (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][3]~q ))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][3]~q & +// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\z80_|address_pins_|abus[9]~17_combout ), + .datab(\ula_|zx_keyboard_|keys[0][3]~q ), + .datac(\z80_|address_pins_|abus[8]~18_combout ), + .datad(\ula_|zx_keyboard_|keys[1][3]~q ), + .cin(gnd), + .combout(\D[3]~72_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~72 .lut_mask = 16'hA2F3; +defparam \D[3]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N10 +cycloneive_lcell_comb \D[3]~76 ( +// Equation(s): +// \D[3]~76_combout = (\D[3]~74_combout & (\D[3]~73_combout & (\D[3]~75_combout & \D[3]~72_combout ))) + + .dataa(\D[3]~74_combout ), + .datab(\D[3]~73_combout ), + .datac(\D[3]~75_combout ), + .datad(\D[3]~72_combout ), + .cin(gnd), + .combout(\D[3]~76_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~76 .lut_mask = 16'h8000; +defparam \D[3]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N2 +cycloneive_lcell_comb \D[3]~122 ( +// Equation(s): +// \D[3]~122_combout = (\Equal2~0_combout & ((\D[3]~76_combout ) # ((\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) + + .dataa(\D[3]~76_combout ), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\Equal2~0_combout ), + .cin(gnd), + .combout(\D[3]~122_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~122 .lut_mask = 16'hEF00; +defparam \D[3]~122 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y14_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), @@ -52533,8 +45182,8 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52574,7 +45223,24 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; // synopsys translate_on -// Location: M9K_X22_Y18_N0 +// Location: LCCOMB_X25_Y15_N28 +cycloneive_lcell_comb \D[3]~79 ( +// Equation(s): +// \D[3]~79_combout = (!\Equal2~0_combout & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\Equal2~0_combout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\D[3]~79_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~79 .lut_mask = 16'h3332; +defparam \D[3]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), @@ -52590,8 +45256,8 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52631,25 +45297,7 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N14 -cycloneive_lcell_comb \D[3]~73 ( -// Equation(s): -// \D[3]~73_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .cin(gnd), - .combout(\D[3]~73_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~73 .lut_mask = 16'hCCE2; -defparam \D[3]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y5_N0 +// Location: M9K_X22_Y15_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), .portare(vcc), @@ -52665,8 +45313,8 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52706,42 +45354,24 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N16 -cycloneive_lcell_comb \D[3]~74 ( -// Equation(s): -// \D[3]~74_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\D[3]~73_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ))) # (!\D[3]~73_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[3]~73_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datac(\D[3]~73_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), - .cin(gnd), - .combout(\D[3]~74_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~74 .lut_mask = 16'hF858; -defparam \D[3]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y19_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(vcc), +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52750,39 +45380,238 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y23_N0 +// Location: M9K_X33_Y12_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N20 +cycloneive_lcell_comb \D[3]~77 ( +// Equation(s): +// \D[3]~77_combout = (\z80_|address_pins_|abus[15]~21_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) # (!\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # +// ((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\D[3]~77_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~77 .lut_mask = 16'hF5E4; +defparam \D[3]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N22 +cycloneive_lcell_comb \D[3]~80 ( +// Equation(s): +// \D[3]~80_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~77_combout ))) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\D[3]~77_combout ), + .cin(gnd), + .combout(\D[3]~80_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~80 .lut_mask = 16'hCFC0; +defparam \D[3]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N4 +cycloneive_lcell_comb \D[3]~81 ( +// Equation(s): +// \D[3]~81_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[3]~80_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout +// )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datac(\D[3]~80_combout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\D[3]~81_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~81 .lut_mask = 16'hF0DD; +defparam \D[3]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N30 +cycloneive_lcell_comb \D[3]~124 ( +// Equation(s): +// \D[3]~124_combout = (\D[3]~77_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ) # ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datad(\D[3]~77_combout ), + .cin(gnd), + .combout(\D[3]~124_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~124 .lut_mask = 16'hF200; +defparam \D[3]~124 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y23_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), @@ -52792,14 +45621,14 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52855,26 +45684,8 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N24 -cycloneive_lcell_comb \D[3]~70 ( -// Equation(s): -// \D[3]~70_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~23_combout )) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\z80_|address_pins_|abus[14]~23_combout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .cin(gnd), - .combout(\D[3]~70_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~70 .lut_mask = 16'hEC64; -defparam \D[3]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y21_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( +// Location: M9K_X22_Y32_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), @@ -52883,14 +45694,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52899,217 +45710,143 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N22 -cycloneive_lcell_comb \D[3]~71 ( +// Location: LCCOMB_X25_Y15_N0 +cycloneive_lcell_comb \D[3]~123 ( // Equation(s): -// \D[3]~71_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout $ (((\D[3]~70_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout & !\D[3]~70_combout )))) +// \D[3]~123_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & (\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # (!\z80_|address_pins_|DFFE_apin_latch [14] & +// ((\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datad(\D[3]~70_combout ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), .cin(gnd), - .combout(\D[3]~71_combout ), + .combout(\D[3]~123_combout ), .cout()); // synopsys translate_off -defparam \D[3]~71 .lut_mask = 16'h22D8; -defparam \D[3]~71 .sum_lutc_input = "datac"; +defparam \D[3]~123 .lut_mask = 16'hF2D0; +defparam \D[3]~123 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y31_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N20 -cycloneive_lcell_comb \D[3]~72 ( +// Location: LCCOMB_X25_Y15_N10 +cycloneive_lcell_comb \D[3]~78 ( // Equation(s): -// \D[3]~72_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\D[3]~70_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~70_combout & (!\D[3]~71_combout & -// \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout )) # (!\D[3]~70_combout & (\D[3]~71_combout )))) +// \D[3]~78_combout = (!\Equal2~0_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~123_combout ))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\D[3]~124_combout )))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\D[3]~70_combout ), - .datac(\D[3]~71_combout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .dataa(\Equal2~0_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[3]~124_combout ), + .datad(\D[3]~123_combout ), .cin(gnd), - .combout(\D[3]~72_combout ), + .combout(\D[3]~78_combout ), .cout()); // synopsys translate_off -defparam \D[3]~72 .lut_mask = 16'h9C98; -defparam \D[3]~72 .sum_lutc_input = "datac"; +defparam \D[3]~78 .lut_mask = 16'h5410; +defparam \D[3]~78 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N28 +// Location: LCCOMB_X25_Y15_N6 +cycloneive_lcell_comb \D[3]~82 ( +// Equation(s): +// \D[3]~82_combout = (\z80_|address_pins_|abus[15]~21_combout & (\D[3]~79_combout & (\D[3]~81_combout ))) # (!\z80_|address_pins_|abus[15]~21_combout & (((\D[3]~78_combout )))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\D[3]~79_combout ), + .datac(\D[3]~81_combout ), + .datad(\D[3]~78_combout ), + .cin(gnd), + .combout(\D[3]~82_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~82 .lut_mask = 16'hD580; +defparam \D[3]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N26 cycloneive_lcell_comb \D[3]~108 ( // Equation(s): -// \D[3]~108_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[3]~74_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[3]~72_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[3]~74_combout )))) +// \D[3]~108_combout = ((\D[3]~122_combout ) # (\D[3]~82_combout )) # (!\Equal2~1_combout ) - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\D[3]~74_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[3]~72_combout ), + .dataa(\Equal2~1_combout ), + .datab(\D[3]~122_combout ), + .datac(gnd), + .datad(\D[3]~82_combout ), .cin(gnd), .combout(\D[3]~108_combout ), .cout()); // synopsys translate_off -defparam \D[3]~108 .lut_mask = 16'hDC8C; +defparam \D[3]~108 .lut_mask = 16'hFFDD; defparam \D[3]~108 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N4 -cycloneive_lcell_comb \D[3]~95 ( +// Location: LCCOMB_X25_Y15_N8 +cycloneive_lcell_comb \D[3]~109 ( // Equation(s): -// \D[3]~95_combout = ((\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout )))) # (!\Equal2~1_combout ) +// \D[3]~109_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [3] & (\D[3]~108_combout ))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[3]~108_combout ) # (!\Equal2~1_combout )))) - .dataa(\D[3]~69_combout ), - .datab(\Equal2~1_combout ), - .datac(\Equal2~0_combout ), - .datad(\D[3]~108_combout ), + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|data_pins_|dout [3]), + .datac(\D[3]~108_combout ), + .datad(\Equal2~1_combout ), .cin(gnd), - .combout(\D[3]~95_combout ), + .combout(\D[3]~109_combout ), .cout()); // synopsys translate_off -defparam \D[3]~95 .lut_mask = 16'hBFB3; -defparam \D[3]~95 .sum_lutc_input = "datac"; +defparam \D[3]~109 .lut_mask = 16'hD0D5; +defparam \D[3]~109 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N26 -cycloneive_lcell_comb \D[3]~96 ( -// Equation(s): -// \D[3]~96_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [3] & \D[3]~95_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[3]~95_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [3]), - .datad(\D[3]~95_combout ), - .cin(gnd), - .combout(\D[3]~96_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~96 .lut_mask = 16'hF511; -defparam \D[3]~96 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N6 +// Location: LCCOMB_X28_Y12_N4 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[3]~21_combout ) # ((\D[3]~96_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[3]~96_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[3]~109_combout ) # ((\z80_|bus_control_|db[3]~21_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & +// (((\z80_|bus_control_|db[3]~21_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[3]~96_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), + .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), + .datab(\D[3]~109_combout ), + .datac(\z80_|bus_control_|db[3]~21_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hF888; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N7 +// Location: FF_X28_Y12_N5 dffeas \z80_|data_pins_|dout[3] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), @@ -53128,41 +45865,41 @@ defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N4 +// Location: LCCOMB_X28_Y12_N22 cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( // Equation(s): // \z80_|bus_control_|db[3]~20_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(\z80_|data_pins_|dout [3]), - .datac(gnd), + .dataa(gnd), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|data_pins_|dout [3]), .datad(\z80_|bus_control_|db[0]~4_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[3]~20_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hDD00; +defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hF300; defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N0 +// Location: LCCOMB_X27_Y12_N28 cycloneive_lcell_comb \z80_|bus_control_|db[3]~21 ( // Equation(s): -// \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~36_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|bus_control_|db[0]~6_combout ), + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), .datab(\z80_|bus_control_|db[3]~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|alu_control_|db[3]~36_combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[3]~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hDD5D; +defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hC4FF; defparam \z80_|bus_control_|db[3]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y10_N1 +// Location: FF_X27_Y12_N29 dffeas \z80_|ir_|opcode[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|bus_control_|db[3]~21_combout ), @@ -53181,41 +45918,7772 @@ defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( +// Location: LCCOMB_X39_Y8_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~4_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) +// \z80_|pla_decode_|Equal33~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4])) .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal52~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~4_combout ), + .combout(\z80_|pla_decode_|Equal33~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N20 +// Location: LCCOMB_X36_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N4 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( +// Equation(s): +// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hCECF; +defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N6 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( +// Equation(s): +// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|bus_control_|db[0]~4_combout ), + .datab(\z80_|alu_control_|db[7]~37_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'h88AA; +defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y1_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 .lut_mask = 16'hCFA0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N2 +cycloneive_lcell_comb \D[5]~97 ( +// Equation(s): +// \D[5]~97_combout = (\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|control_pins_|pin_nIORQ~1_combout ))) + + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), + .cin(gnd), + .combout(\D[5]~97_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~97 .lut_mask = 16'h2000; +defparam \D[5]~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y21_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y3_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: M9K_X33_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y27_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N6 +cycloneive_lcell_comb \Mux0~0 ( +// Equation(s): +// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) # (!\z80_|address_pins_|abus[14]~22_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~0 .lut_mask = 16'hB9A8; +defparam \Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N4 +cycloneive_lcell_comb \Mux0~1 ( +// Equation(s): +// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datad(\Mux0~0_combout ), + .cin(gnd), + .combout(\Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~1 .lut_mask = 16'hDDA0; +defparam \Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N20 +cycloneive_lcell_comb \D[7]~116 ( +// Equation(s): +// \D[7]~116_combout = ((\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )) # (!\z80_|address_pins_|abus[15]~21_combout & ((\Mux0~1_combout )))) # (!\D[5]~97_combout ) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .datab(\D[5]~97_combout ), + .datac(\z80_|address_pins_|abus[15]~21_combout ), + .datad(\Mux0~1_combout ), + .cin(gnd), + .combout(\D[7]~116_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~116 .lut_mask = 16'hBFB3; +defparam \D[7]~116 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N26 +cycloneive_lcell_comb \D[7]~117 ( +// Equation(s): +// \D[7]~117_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [7] & \D[7]~116_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[7]~116_combout )) # (!\Equal2~1_combout ))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [7]), + .datad(\D[7]~116_combout ), + .cin(gnd), + .combout(\D[7]~117_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~117 .lut_mask = 16'hF311; +defparam \D[7]~117 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N0 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\z80_|bus_control_|db[7]~7_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[7]~117_combout )))) # (!\z80_|bus_control_|db[7]~7_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[7]~117_combout ))) + + .dataa(\z80_|bus_control_|db[7]~7_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\D[7]~117_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N1 +dffeas \z80_|data_pins_|dout[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N20 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( +// Equation(s): +// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[7]~5_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|bus_control_|db[0]~6_combout ), + .datad(\z80_|data_pins_|dout [7]), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hAF2F; +defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N13 +dffeas \z80_|ir_|opcode[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[7]~7_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~2_combout = (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~0_combout & \z80_|pla_decode_|Equal41~1_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datad(\z80_|pla_decode_|Equal41~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|pla_decode_|Equal36~0_combout & (((\z80_|pla_decode_|Equal41~2_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # +// (!\z80_|pla_decode_|Equal36~0_combout & (\z80_|pla_decode_|Equal41~2_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal36~0_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hC0EA; +defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h3222; +defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y7_N9 +dffeas \z80_|decode_state_|DFFE_instCB ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instCB~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|execute_|comb~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N29 +dffeas \z80_|interrupts_|im1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_im_we~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|im1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|interrupts_|im1~q ), + .datad(\z80_|interrupts_|im2~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hC4C0; +defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & +// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h4F0A; +defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_ff_oe~1_combout & (!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0203; +defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_bus_db_oe~5_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; +defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (\z80_|execute_|ctl_bus_db_oe~4_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hAAA2; +defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~88 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~88_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~88_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~88 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[6][0]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~1_combout = (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~89 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~89_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|zx_keyboard_|keys[6][0]~88_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|shifted~1_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .datab(\ula_|zx_keyboard_|keys[6][0]~88_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|shifted~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~89 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[6][0]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|zx_keyboard_|keys[6][0]~89_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][0]~89_combout & ((\ula_|zx_keyboard_|keys[6][0]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[6][0]~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h7272; +defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y10_N23 +dffeas \ula_|zx_keyboard_|keys[6][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~84 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~84_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~84_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~84 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[7][0]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~78 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~78_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~78 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[5][0]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~85 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~85_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[5][0]~78_combout ) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[5][0]~78_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~85_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~85 .lut_mask = 16'h3300; +defparam \ula_|zx_keyboard_|keys[7][0]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~86 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~86_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[3][0]~73_combout & (\ula_|zx_keyboard_|keys[5][4]~20_combout ))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|keys[7][0]~85_combout +// )))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~73_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~20_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|keys[7][0]~85_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~86 .lut_mask = 16'h8F80; +defparam \ula_|zx_keyboard_|keys[7][0]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[7][0]~84_combout & ((\ula_|zx_keyboard_|keys[7][0]~86_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][0]~86_combout & ((\ula_|zx_keyboard_|keys[7][0]~q +// ))))) # (!\ula_|zx_keyboard_|keys[7][0]~84_combout & (((\ula_|zx_keyboard_|keys[7][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][0]~84_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[7][0]~q ), + .datad(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y10_N1 +dffeas \ula_|zx_keyboard_|keys[7][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N28 +cycloneive_lcell_comb \D[0]~57 ( +// Equation(s): +// \D[0]~57_combout = (\ula_|zx_keyboard_|keys[6][0]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\ula_|zx_keyboard_|keys[6][0]~q & +// (((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][0]~q ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[15]~21_combout ), + .datad(\ula_|zx_keyboard_|keys[7][0]~q ), + .cin(gnd), + .combout(\D[0]~57_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~57 .lut_mask = 16'hD0DD; +defparam \D[0]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~81 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~81_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [5]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & +// (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [5])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~81_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~81 .lut_mask = 16'h1024; +defparam \ula_|zx_keyboard_|keys[4][0]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~82 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~82_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~82_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~82 .lut_mask = 16'hF0FA; +defparam \ula_|zx_keyboard_|keys[4][0]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~40 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~40_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][1]~39_combout & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~40 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[5][1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~83 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~83_combout = (\ula_|zx_keyboard_|keys[4][0]~81_combout & ((\ula_|zx_keyboard_|keys[5][1]~40_combout & (!\ula_|zx_keyboard_|keys[4][0]~82_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~40_combout & +// ((\ula_|zx_keyboard_|keys[4][0]~q ))))) # (!\ula_|zx_keyboard_|keys[4][0]~81_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][0]~81_combout ), + .datab(\ula_|zx_keyboard_|keys[4][0]~82_combout ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~40_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~83_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~83 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][0]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y8_N23 +dffeas \ula_|zx_keyboard_|keys[4][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][0]~83_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~79 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~79_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (((!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[5][0]~78_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & +// ((\ula_|zx_keyboard_|keys[3][0]~73_combout ) # (\ula_|zx_keyboard_|keys[5][0]~78_combout )))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~73_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[5][0]~78_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~79_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~79 .lut_mask = 16'h3C20; +defparam \ula_|zx_keyboard_|keys[5][0]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~80 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~80_combout = (\ula_|zx_keyboard_|keys[6][1]~32_combout & ((\ula_|zx_keyboard_|keys[5][0]~79_combout & (!\ula_|zx_keyboard_|keys[5][0]~62_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~79_combout & +// ((\ula_|zx_keyboard_|keys[5][0]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~32_combout & (((\ula_|zx_keyboard_|keys[5][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~62_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~32_combout ), + .datac(\ula_|zx_keyboard_|keys[5][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][0]~79_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~80 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[5][0]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y9_N15 +dffeas \ula_|zx_keyboard_|keys[5][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N2 +cycloneive_lcell_comb \D[0]~56 ( +// Equation(s): +// \D[0]~56_combout = (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\z80_|address_pins_|abus[13]~23_combout & (!\ula_|zx_keyboard_|keys[5][0]~q & +// ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~23_combout ), + .datab(\z80_|address_pins_|abus[12]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][0]~q ), + .cin(gnd), + .combout(\D[0]~56_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~56 .lut_mask = 16'h8ACF; +defparam \D[0]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~76 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~76_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~21_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~76_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~76 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[1][0]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~77 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~77_combout = (\ula_|zx_keyboard_|keys[1][0]~76_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][0]~76_combout & ((\ula_|zx_keyboard_|keys[1][0]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[1][0]~q ), + .datad(\ula_|zx_keyboard_|keys[1][0]~76_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~77_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~77 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[1][0]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N23 +dffeas \ula_|zx_keyboard_|keys[1][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][0]~77_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~68 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~68_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~68_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~68 .lut_mask = 16'hC0C0; +defparam \ula_|zx_keyboard_|keys[4][3]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [2] & ((!\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & +// \ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0130; +defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~69 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~69_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|zx_keyboard_|WideOr0~0_combout )) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|keys[6][4]~43_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[6][4]~43_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~69_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~69 .lut_mask = 16'h2777; +defparam \ula_|zx_keyboard_|keys~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~70 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~70_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][3]~68_combout & !\ula_|zx_keyboard_|keys~69_combout )) # (!\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .datab(\ula_|zx_keyboard_|keys[4][3]~68_combout ), + .datac(\ula_|zx_keyboard_|keys~69_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~70_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~70 .lut_mask = 16'h08AA; +defparam \ula_|zx_keyboard_|keys[0][0]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~27 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~27_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~27 .lut_mask = 16'h3030; +defparam \ula_|zx_keyboard_|keys[4][1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & +// (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'hC002; +defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~71 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~71_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|WideOr4~0_combout )) # (!\ula_|zx_keyboard_|keys[4][1]~27_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[4][1]~27_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|WideOr4~0_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~71_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~71 .lut_mask = 16'h3313; +defparam \ula_|zx_keyboard_|keys~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~72 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~72_combout = (\ula_|zx_keyboard_|keys[0][0]~70_combout & ((\ula_|zx_keyboard_|keys~71_combout & ((\ula_|zx_keyboard_|keys[0][0]~q ))) # (!\ula_|zx_keyboard_|keys~71_combout & (!\ula_|zx_keyboard_|released~q )))) # +// (!\ula_|zx_keyboard_|keys[0][0]~70_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~70_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[0][0]~q ), + .datad(\ula_|zx_keyboard_|keys~71_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~72_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~72 .lut_mask = 16'hF072; +defparam \ula_|zx_keyboard_|keys[0][0]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y8_N11 +dffeas \ula_|zx_keyboard_|keys[0][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][0]~72_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~2_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # ((!\ula_|zx_keyboard_|keys[0][0]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [8]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hAFFF; +defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~22 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~22_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~21_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~22 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|keys[2][1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~75 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][0]~75_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~22_combout & (!\ula_|zx_keyboard_|released~q )) # +// (!\ula_|zx_keyboard_|keys[2][1]~22_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~22_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][0]~75_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0]~75 .lut_mask = 16'hD1F0; +defparam \ula_|zx_keyboard_|keys[2][0]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N15 +dffeas \ula_|zx_keyboard_|keys[2][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][0]~75_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~24 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~24_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~24 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[3][1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~74 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~74_combout = (\ula_|zx_keyboard_|keys[3][0]~73_combout & ((\ula_|zx_keyboard_|keys[3][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~24_combout & ((\ula_|zx_keyboard_|keys[3][0]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][0]~73_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][0]~73_combout ), + .datac(\ula_|zx_keyboard_|keys[3][0]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~24_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~74_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~74 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][0]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N17 +dffeas \ula_|zx_keyboard_|keys[3][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][0]~74_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N0 +cycloneive_lcell_comb \D[0]~54 ( +// Equation(s): +// \D[0]~54_combout = (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][0]~q )))) # (!\z80_|address_pins_|abus[10]~20_combout & (!\ula_|zx_keyboard_|keys[2][0]~q & +// ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][0]~q )))) + + .dataa(\z80_|address_pins_|abus[10]~20_combout ), + .datab(\z80_|address_pins_|abus[11]~19_combout ), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|keys[3][0]~q ), + .cin(gnd), + .combout(\D[0]~54_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~54 .lut_mask = 16'h8CAF; +defparam \D[0]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N12 +cycloneive_lcell_comb \D[0]~55 ( +// Equation(s): +// \D[0]~55_combout = (\ula_|zx_keyboard_|key_row~2_combout & (\D[0]~54_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][0]~q ), + .datab(\z80_|address_pins_|abus[9]~17_combout ), + .datac(\ula_|zx_keyboard_|key_row~2_combout ), + .datad(\D[0]~54_combout ), + .cin(gnd), + .combout(\D[0]~55_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~55 .lut_mask = 16'hD000; +defparam \D[0]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N0 +cycloneive_lcell_comb \D[0]~58 ( +// Equation(s): +// \D[0]~58_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~57_combout & (\D[0]~56_combout & \D[0]~55_combout ))) + + .dataa(\D[0]~57_combout ), + .datab(\D[0]~56_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[0]~55_combout ), + .cin(gnd), + .combout(\D[0]~58_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~58 .lut_mask = 16'hF8F0; +defparam \D[0]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N12 +cycloneive_lcell_comb \D[0]~62 ( +// Equation(s): +// \D[0]~62_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .cin(gnd), + .combout(\D[0]~62_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~62 .lut_mask = 16'hEC64; +defparam \D[0]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N8 +cycloneive_lcell_comb \D[0]~63 ( +// Equation(s): +// \D[0]~63_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~62_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~62_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # (!\D[0]~62_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[0]~62_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\D[0]~63_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~63 .lut_mask = 16'hE3E0; +defparam \D[0]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y29_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y4_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N6 +cycloneive_lcell_comb \D[0]~59 ( +// Equation(s): +// \D[0]~59_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout & +// (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .cin(gnd), + .combout(\D[0]~59_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~59 .lut_mask = 16'hE6A2; +defparam \D[0]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y29_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y11_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N28 +cycloneive_lcell_comb \D[0]~60 ( +// Equation(s): +// \D[0]~60_combout = (\z80_|address_pins_|abus[15]~21_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout $ (\D[0]~59_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout & ((!\D[0]~59_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datac(\z80_|address_pins_|abus[15]~21_combout ), + .datad(\D[0]~59_combout ), + .cin(gnd), + .combout(\D[0]~60_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~60 .lut_mask = 16'h30CA; +defparam \D[0]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N10 +cycloneive_lcell_comb \D[0]~61 ( +// Equation(s): +// \D[0]~61_combout = (\D[0]~59_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & !\D[0]~60_combout )))) # (!\D[0]~59_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~60_combout )))) + + .dataa(\D[0]~59_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datad(\D[0]~60_combout ), + .cin(gnd), + .combout(\D[0]~61_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~61 .lut_mask = 16'h99A8; +defparam \D[0]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N18 +cycloneive_lcell_comb \D[0]~120 ( +// Equation(s): +// \D[0]~120_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[0]~63_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[0]~61_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[0]~63_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\D[0]~63_combout ), + .datad(\D[0]~61_combout ), + .cin(gnd), + .combout(\D[0]~120_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~120 .lut_mask = 16'hF4B0; +defparam \D[0]~120 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N26 +cycloneive_lcell_comb \D[0]~64 ( +// Equation(s): +// \D[0]~64_combout = ((\Equal2~0_combout & (\D[0]~58_combout )) # (!\Equal2~0_combout & ((\D[0]~120_combout )))) # (!\Equal2~1_combout ) + + .dataa(\D[0]~58_combout ), + .datab(\Equal2~0_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[0]~120_combout ), + .cin(gnd), + .combout(\D[0]~64_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~64 .lut_mask = 16'hBF8F; +defparam \D[0]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N16 +cycloneive_lcell_comb \D[0]~65 ( +// Equation(s): +// \D[0]~65_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [0] & (\D[0]~64_combout ))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[0]~64_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [0]), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\D[0]~64_combout ), + .datad(\Equal2~1_combout ), + .cin(gnd), + .combout(\D[0]~65_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~65 .lut_mask = 16'hB0B3; +defparam \D[0]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N26 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\D[0]~65_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[0]~17_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[0]~65_combout & +// (((\z80_|bus_control_|db[0]~17_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) + + .dataa(\D[0]~65_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|bus_control_|db[0]~17_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N27 +dffeas \z80_|data_pins_|dout[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N30 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( +// Equation(s): +// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|bus_control_|db[0]~4_combout ), + .datad(\z80_|data_pins_|dout [0]), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'hF030; +defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N12 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( +// Equation(s): +// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~14_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~16_combout ), + .datab(\z80_|alu_control_|db[0]~14_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'h8AFF; +defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N19 +dffeas \z80_|ir_|opcode[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[0]~17_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal3~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal3~2_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pla_decode_|Equal3~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y7_N31 +dffeas \z80_|decode_state_|DFFE_instIY1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_iy_set~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instIY1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N16 +cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( +// Equation(s): +// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|decode_state_|use_ixiy~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFFF0; +defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( +// Equation(s): +// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~9_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~8_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; +defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( +// Equation(s): +// \z80_|execute_|ixy_d~13_combout = (\z80_|execute_|ixy_d~16_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|pla_decode_|Equal41~2_combout )) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ixy_d~10_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( +// Equation(s): +// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~5_combout & (((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )))) # (!\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ixy_d~12_combout ) # +// ((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ixy_d~12_combout ), + .datac(\z80_|execute_|ixy_d~13_combout ), + .datad(\z80_|execute_|ixy_d~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h4F44; +defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( +// Equation(s): +// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hAA8A; +defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( +// Equation(s): +// \z80_|execute_|ixy_d~15_combout = ((\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal49~0_combout & \z80_|execute_|ixy_d~11_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|ixy_d~14_combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|execute_|ixy_d~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'hB333; +defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~9_combout = (\z80_|execute_|ctl_flags_xy_we~8_combout & (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h0070; +defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~12_combout = ((\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_ir_we~12_combout ) # (\z80_|execute_|ctl_ir_we~11_combout )))) # (!\z80_|execute_|ctl_alu_oe~6_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hBBB3; +defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_alu_oe~11_combout ) # ((\z80_|execute_|ctl_alu_oe~12_combout ) # (!\z80_|execute_|ctl_alu_oe~8_combout ))) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~11_combout ), + .datac(\z80_|execute_|ctl_alu_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~14_combout = ((\z80_|execute_|ctl_alu_oe~13_combout ) # ((!\z80_|execute_|ctl_alu_oe~10_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~9_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~13_combout ), + .datac(\z80_|execute_|ctl_flags_alu~14_combout ), + .datad(\z80_|execute_|ctl_alu_oe~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N6 +cycloneive_lcell_comb \z80_|alu_|db[7]~9 ( +// Equation(s): +// \z80_|alu_|db[7]~9_combout = (\z80_|execute_|ctl_alu_oe~14_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (\z80_|execute_|ctl_reg_out_hi~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~9 .lut_mask = 16'hFFFC; +defparam \z80_|alu_|db[7]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N0 +cycloneive_lcell_comb \z80_|alu_|db[1]~15 ( +// Equation(s): +// \z80_|alu_|db[1]~15_combout = (\z80_|alu_control_|db[1]~27_combout & (((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[1]~27_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) + + .dataa(\z80_|alu_control_|db[1]~27_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~15 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N14 +cycloneive_lcell_comb \z80_|alu_|db[1]~16 ( +// Equation(s): +// \z80_|alu_|db[1]~16_combout = ((\z80_|alu_|db[1]~15_combout & ((\z80_|alu_|db_low[1]~20_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db_low[1]~20_combout ), + .datad(\z80_|alu_|db[1]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~16 .lut_mask = 16'hF755; +defparam \z80_|alu_|db[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( +// Equation(s): +// \z80_|alu_control_|db[1]~25_combout = (\z80_|alu_|db[1]~16_combout & (\z80_|execute_|ctl_flags_oe~2_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) # (!\z80_|alu_|db[1]~16_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((\z80_|execute_|ctl_flags_oe~2_combout & !\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) + + .dataa(\z80_|alu_|db[1]~16_combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h50DC; +defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( +// Equation(s): +// \z80_|alu_control_|db[1]~26_combout = (!\z80_|alu_control_|db[1]~25_combout & (\z80_|alu_control_|db[2]~24_combout & ((\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|alu_control_|db[1]~25_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .datad(\z80_|alu_control_|db[2]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h5100; +defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N6 +cycloneive_lcell_comb \z80_|sw1_|db_down[1]~2 ( +// Equation(s): +// \z80_|sw1_|db_down[1]~2_combout = ((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) + + .dataa(\z80_|bus_control_|db[1]~11_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datad(\z80_|execute_|ctl_sw_1d~7_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[1]~2 .lut_mask = 16'h0AFF; +defparam \z80_|sw1_|db_down[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~27 ( +// Equation(s): +// \z80_|alu_control_|db[1]~27_combout = ((\z80_|alu_control_|db[1]~26_combout & \z80_|sw1_|db_down[1]~2_combout )) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[1]~26_combout ), + .datac(\z80_|alu_control_|db[6]~13_combout ), + .datad(\z80_|sw1_|db_down[1]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~27 .lut_mask = 16'hCF0F; +defparam \z80_|alu_control_|db[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N12 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( +// Equation(s): +// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~27_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|alu_control_|db[1]~27_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[0]~4_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hBB00; +defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~38_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'hFAF0; +defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~41 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~41_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~41 .lut_mask = 16'h0005; +defparam \ula_|zx_keyboard_|keys[5][1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~42 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~42_combout = (\ula_|zx_keyboard_|keys[5][1]~41_combout & ((\ula_|zx_keyboard_|keys[5][1]~40_combout & (!\ula_|zx_keyboard_|keys[5][1]~38_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~40_combout & +// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~41_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~38_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~41_combout ), + .datac(\ula_|zx_keyboard_|keys[5][1]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~40_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~42 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[5][1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y8_N9 +dffeas \ula_|zx_keyboard_|keys[5][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][1]~42_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~30 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~30_combout = (\ula_|zx_keyboard_|keys[5][2]~29_combout & ((\ula_|zx_keyboard_|keys[4][1]~27_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][1]~27_combout & ((\ula_|zx_keyboard_|keys[4][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~29_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~29_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][1]~q ), + .datad(\ula_|zx_keyboard_|keys[4][1]~27_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~30 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y10_N9 +dffeas \ula_|zx_keyboard_|keys[4][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][1]~30_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~0_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # ((!\ula_|zx_keyboard_|keys[4][1]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [12]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|zx_keyboard_|keys[4][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hCFFF; +defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~36 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~36_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~36 .lut_mask = 16'h0010; +defparam \ula_|zx_keyboard_|keys[7][1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~3_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & +// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h444A; +defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [0] & +// (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~0 .lut_mask = 16'h0120; +defparam \ula_|zx_keyboard_|WideOr16~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~2_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~1_combout & (!\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|zx_keyboard_|WideOr16~1_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|WideOr16~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'hF202; +defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~4_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~2_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~3_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|WideOr16~3_combout ), + .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'hEA40; +defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~37 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~37_combout = (\ula_|zx_keyboard_|keys[7][1]~36_combout & ((\ula_|zx_keyboard_|WideOr16~4_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~4_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # +// (!\ula_|zx_keyboard_|keys[7][1]~36_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[7][1]~36_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~q ), + .datad(\ula_|zx_keyboard_|WideOr16~4_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~37 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[7][1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y10_N25 +dffeas \ula_|zx_keyboard_|keys[7][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][1]~37_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~33 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~33_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & +// (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~33 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[6][1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~34 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~34_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|zx_keyboard_|keys[6][1]~33_combout & \ula_|zx_keyboard_|keys[6][1]~32_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|zx_keyboard_|keys[6][1]~33_combout ), + .datad(\ula_|zx_keyboard_|keys[6][1]~32_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~34 .lut_mask = 16'hC000; +defparam \ula_|zx_keyboard_|keys[6][1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~31 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~31_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|shifted~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~31 .lut_mask = 16'hFCF0; +defparam \ula_|zx_keyboard_|keys[6][1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~35 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~35_combout = (\ula_|zx_keyboard_|keys[6][1]~34_combout & ((!\ula_|zx_keyboard_|keys[6][1]~31_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~34_combout & (\ula_|zx_keyboard_|keys[6][1]~q )) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~34_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[6][1]~q ), + .datad(\ula_|zx_keyboard_|keys[6][1]~31_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~35 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[6][1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y9_N31 +dffeas \ula_|zx_keyboard_|keys[6][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][1]~35_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N28 +cycloneive_lcell_comb \D[1]~32 ( +// Equation(s): +// \D[1]~32_combout = (\ula_|zx_keyboard_|keys[7][1]~q & (\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) # (!\ula_|zx_keyboard_|keys[7][1]~q & +// ((\z80_|address_pins_|abus[14]~22_combout ) # ((!\ula_|zx_keyboard_|keys[6][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~q ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ula_|zx_keyboard_|keys[6][1]~q ), + .datad(\z80_|address_pins_|abus[15]~21_combout ), + .cin(gnd), + .combout(\D[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~32 .lut_mask = 16'hCF45; +defparam \D[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N12 +cycloneive_lcell_comb \D[1]~33 ( +// Equation(s): +// \D[1]~33_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~32_combout & ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~q ), + .datac(\ula_|zx_keyboard_|key_row~0_combout ), + .datad(\D[1]~32_combout ), + .cin(gnd), + .combout(\D[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~33 .lut_mask = 16'hB000; +defparam \D[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~16 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~16_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~16 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[6][4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~17 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~17_combout = (\ula_|zx_keyboard_|keys[6][4]~16_combout & (\ula_|zx_keyboard_|keys[7][4]~15_combout & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~16_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~15_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~17 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[1][1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~18 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~18_combout = (\ula_|zx_keyboard_|keys[1][1]~17_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][1]~17_combout & ((\ula_|zx_keyboard_|keys[1][1]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[1][1]~17_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[1][1]~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~18 .lut_mask = 16'h7272; +defparam \ula_|zx_keyboard_|keys[1][1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y9_N9 +dffeas \ula_|zx_keyboard_|keys[1][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][1]~18_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~12 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~12_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~12 .lut_mask = 16'h0048; +defparam \ula_|zx_keyboard_|keys[0][1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~13 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~13_combout = (\ula_|zx_keyboard_|keys[0][1]~12_combout & ((\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [4] & +// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~13 .lut_mask = 16'h2400; +defparam \ula_|zx_keyboard_|keys[0][1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~10 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~10_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~10 .lut_mask = 16'hF0F3; +defparam \ula_|zx_keyboard_|keys[0][1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~13_combout & ((!\ula_|zx_keyboard_|keys[0][1]~10_combout ))) # (!\ula_|zx_keyboard_|keys[0][1]~13_combout & +// (\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~0_combout ), + .datab(\ula_|zx_keyboard_|keys[0][1]~13_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\ula_|zx_keyboard_|keys[0][1]~10_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y9_N21 +dffeas \ula_|zx_keyboard_|keys[0][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N16 +cycloneive_lcell_comb \D[1]~30 ( +// Equation(s): +// \D[1]~30_combout = (\ula_|zx_keyboard_|keys[1][1]~q & (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|keys[1][1]~q & +// (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[1][1]~q ), + .datab(\ula_|zx_keyboard_|keys[0][1]~q ), + .datac(\z80_|address_pins_|abus[9]~17_combout ), + .datad(\z80_|address_pins_|abus[8]~18_combout ), + .cin(gnd), + .combout(\D[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~30 .lut_mask = 16'hF531; +defparam \D[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~25 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~25 .lut_mask = 16'h3000; +defparam \ula_|zx_keyboard_|keys[3][1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~26 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~26_combout = (\ula_|zx_keyboard_|keys[3][1]~25_combout & ((\ula_|zx_keyboard_|keys[3][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~24_combout & ((\ula_|zx_keyboard_|keys[3][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~25_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][1]~25_combout ), + .datac(\ula_|zx_keyboard_|keys[3][1]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~24_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~26 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N31 +dffeas \ula_|zx_keyboard_|keys[3][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~23 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~23_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~22_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~22_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # +// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[2][1]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~22_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~23 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[2][1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N21 +dffeas \ula_|zx_keyboard_|keys[2][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][1]~23_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N8 +cycloneive_lcell_comb \D[1]~31 ( +// Equation(s): +// \D[1]~31_combout = (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][1]~q )))) # (!\z80_|address_pins_|abus[10]~20_combout & (!\ula_|zx_keyboard_|keys[2][1]~q & +// ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\z80_|address_pins_|abus[10]~20_combout ), + .datab(\z80_|address_pins_|abus[11]~19_combout ), + .datac(\ula_|zx_keyboard_|keys[3][1]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~q ), + .cin(gnd), + .combout(\D[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~31 .lut_mask = 16'h8ACF; +defparam \D[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N6 +cycloneive_lcell_comb \D[1]~34 ( +// Equation(s): +// \D[1]~34_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~33_combout & (\D[1]~30_combout & \D[1]~31_combout ))) + + .dataa(\D[1]~33_combout ), + .datab(\D[1]~30_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[1]~31_combout ), + .cin(gnd), + .combout(\D[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~34 .lut_mask = 16'hF8F0; +defparam \D[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N22 +cycloneive_lcell_comb \D[1]~38 ( +// Equation(s): +// \D[1]~38_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .cin(gnd), + .combout(\D[1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~38 .lut_mask = 16'hE6A2; +defparam \D[1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N4 +cycloneive_lcell_comb \D[1]~39 ( +// Equation(s): +// \D[1]~39_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[1]~38_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\D[1]~38_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\D[1]~38_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datac(\D[1]~38_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .cin(gnd), + .combout(\D[1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~39 .lut_mask = 16'hE5E0; +defparam \D[1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y2_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +// synopsys translate_on + +// Location: M9K_X22_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +// synopsys translate_on + +// Location: M9K_X22_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N24 +cycloneive_lcell_comb \D[1]~35 ( +// Equation(s): +// \D[1]~35_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout & +// (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .cin(gnd), + .combout(\D[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~35 .lut_mask = 16'hEA62; +defparam \D[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N14 +cycloneive_lcell_comb \D[1]~36 ( +// Equation(s): +// \D[1]~36_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout $ (((\D[1]~35_combout ))))) # (!\z80_|address_pins_|abus[15]~21_combout & +// (((\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout & !\D[1]~35_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\D[1]~35_combout ), + .cin(gnd), + .combout(\D[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~36 .lut_mask = 16'h44B8; +defparam \D[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N0 +cycloneive_lcell_comb \D[1]~37 ( +// Equation(s): +// \D[1]~37_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[1]~35_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[1]~36_combout & ((!\D[1]~35_combout ))) # (!\D[1]~36_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout & \D[1]~35_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datac(\D[1]~36_combout ), + .datad(\D[1]~35_combout ), + .cin(gnd), + .combout(\D[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~37 .lut_mask = 16'hAE50; +defparam \D[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N20 +cycloneive_lcell_comb \D[1]~118 ( +// Equation(s): +// \D[1]~118_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[1]~39_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[1]~37_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[1]~39_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\D[1]~39_combout ), + .datad(\D[1]~37_combout ), + .cin(gnd), + .combout(\D[1]~118_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~118 .lut_mask = 16'hF4B0; +defparam \D[1]~118 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N2 +cycloneive_lcell_comb \D[1]~40 ( +// Equation(s): +// \D[1]~40_combout = ((\Equal2~0_combout & (\D[1]~34_combout )) # (!\Equal2~0_combout & ((\D[1]~118_combout )))) # (!\Equal2~1_combout ) + + .dataa(\D[1]~34_combout ), + .datab(\Equal2~0_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[1]~118_combout ), + .cin(gnd), + .combout(\D[1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~40 .lut_mask = 16'hBF8F; +defparam \D[1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N12 +cycloneive_lcell_comb \D[1]~41 ( +// Equation(s): +// \D[1]~41_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~40_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[1]~40_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [1]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[1]~40_combout ), + .cin(gnd), + .combout(\D[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~41 .lut_mask = 16'hAF03; +defparam \D[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N28 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\D[1]~41_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[1]~11_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[1]~41_combout & +// (((\z80_|bus_control_|db[1]~11_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) + + .dataa(\D[1]~41_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|bus_control_|db[1]~11_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N29 +dffeas \z80_|data_pins_|dout[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N8 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~11 ( +// Equation(s): +// \z80_|bus_control_|db[1]~11_combout = ((\z80_|bus_control_|db[1]~10_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[1]~10_combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\z80_|bus_control_|db[0]~6_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'h8FAF; +defparam \z80_|bus_control_|db[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N9 +dffeas \z80_|ir_|opcode[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[1]~11_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_ed_set~combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|pla_decode_|Equal2~1_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y7_N29 +dffeas \z80_|decode_state_|DFFE_instED ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instED~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; +defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~8_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~8_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFAEA; +defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~8_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h00C8; +defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~6_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC888; +defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~6_combout = (\z80_|execute_|ctl_bus_db_we~4_combout ) # (((!\z80_|execute_|ctl_sw_2u~3_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) + + .dataa(\z80_|execute_|ctl_bus_db_we~4_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~2_combout ) # ((\z80_|execute_|ctl_bus_db_we~3_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # (\z80_|execute_|ctl_bus_db_we~6_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~2_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~3_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~126 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~126_combout = (\ula_|zx_keyboard_|keys[6][4]~16_combout & ((\ula_|zx_keyboard_|keys[6][4]~44_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~44_combout & ((\ula_|zx_keyboard_|keys[6][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~16_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~16_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~44_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~126_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~126 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[6][4]~126 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y9_N1 +dffeas \ula_|zx_keyboard_|keys[6][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][4]~126_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~125 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~125_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) +// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|shifted~1_combout ), + .datac(\ula_|zx_keyboard_|keys[7][4]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~125_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~125 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[7][4]~125 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N11 +dffeas \ula_|zx_keyboard_|keys[7][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][4]~125_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N16 +cycloneive_lcell_comb \D[4]~88 ( +// Equation(s): +// \D[4]~88_combout = (\ula_|zx_keyboard_|keys[6][4]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][4]~q )))) # (!\ula_|zx_keyboard_|keys[6][4]~q & +// (((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~q ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[15]~21_combout ), + .datad(\ula_|zx_keyboard_|keys[7][4]~q ), + .cin(gnd), + .combout(\D[4]~88_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~88 .lut_mask = 16'hD0DD; +defparam \D[4]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~120 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~120_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~120_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~120 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[5][4]~120 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~121 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~121_combout = (\ula_|zx_keyboard_|keys[6][4]~44_combout & ((\ula_|zx_keyboard_|keys[5][4]~120_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~120_combout & (\ula_|zx_keyboard_|keys[5][4]~q +// )))) # (!\ula_|zx_keyboard_|keys[6][4]~44_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~44_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~120_combout ), + .datac(\ula_|zx_keyboard_|keys[5][4]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~121_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~121 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][4]~121 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y9_N31 +dffeas \ula_|zx_keyboard_|keys[5][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][4]~121_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~122 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q )) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & +// \ula_|zx_keyboard_|extended~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~122_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~122 .lut_mask = 16'h300C; +defparam \ula_|zx_keyboard_|keys[4][4]~122 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~123 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~123_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[4][4]~122_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[4][4]~122_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~123_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~123 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][4]~123 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & ((\ula_|zx_keyboard_|keys[4][4]~123_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~123_combout & ((\ula_|zx_keyboard_|keys[4][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .datac(\ula_|zx_keyboard_|keys[4][4]~q ), + .datad(\ula_|zx_keyboard_|keys[4][4]~123_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y9_N9 +dffeas \ula_|zx_keyboard_|keys[4][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N28 +cycloneive_lcell_comb \D[4]~87 ( +// Equation(s): +// \D[4]~87_combout = (\z80_|address_pins_|abus[12]~24_combout & ((\z80_|address_pins_|abus[13]~23_combout ) # ((!\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\z80_|address_pins_|abus[12]~24_combout & (!\ula_|zx_keyboard_|keys[4][4]~q & +// ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\z80_|address_pins_|abus[12]~24_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[5][4]~q ), + .datad(\ula_|zx_keyboard_|keys[4][4]~q ), + .cin(gnd), + .combout(\D[4]~87_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~87 .lut_mask = 16'h8ACF; +defparam \D[4]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~115 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~115_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [5] & +// (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~115_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~115 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[2][4]~115 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~116 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~116_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[2][4]~115_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[2][4]~115_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~116_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~116 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[2][4]~116 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~117 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~117_combout = (\ula_|zx_keyboard_|keys[2][4]~116_combout & (!\ula_|zx_keyboard_|keys[2][4]~93_combout )) # (!\ula_|zx_keyboard_|keys[2][4]~116_combout & ((\ula_|zx_keyboard_|keys[2][4]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[2][4]~93_combout ), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~116_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~117_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~117 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[2][4]~117 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y8_N25 +dffeas \ula_|zx_keyboard_|keys[2][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][4]~117_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][4]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [10]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[2][4]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hDDFF; +defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~118 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~118_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~118_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~118 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|keys[3][4]~118 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~131 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~131_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[3][4]~118_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[3][4]~118_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~131_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~131 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[3][4]~131 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~119 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~119_combout = (\ula_|zx_keyboard_|keys[3][4]~127_combout & ((\ula_|zx_keyboard_|keys[3][4]~131_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~131_combout & ((\ula_|zx_keyboard_|keys[3][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~127_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][4]~127_combout ), + .datac(\ula_|zx_keyboard_|keys[3][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~131_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~119_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~119 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][4]~119 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N21 +dffeas \ula_|zx_keyboard_|keys[3][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][4]~119_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~114 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~114_combout = (\ula_|zx_keyboard_|keys[0][4]~95_combout & ((\ula_|zx_keyboard_|keys[3][1]~25_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[3][1]~25_combout & +// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .datac(\ula_|zx_keyboard_|keys[0][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~25_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~114_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~114 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[0][4]~114 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y8_N21 +dffeas \ula_|zx_keyboard_|keys[0][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][4]~114_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~113 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~113_combout = (\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~21_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][4]~21_combout & ((\ula_|zx_keyboard_|keys[1][4]~q ))))) # +// (!\ula_|zx_keyboard_|Equal0~2_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|Equal0~2_combout ), + .datac(\ula_|zx_keyboard_|keys[1][4]~q ), + .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~113_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~113 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[1][4]~113 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y8_N15 +dffeas \ula_|zx_keyboard_|keys[1][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][4]~113_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N6 +cycloneive_lcell_comb \D[4]~85 ( +// Equation(s): +// \D[4]~85_combout = (\z80_|address_pins_|abus[9]~17_combout & (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~q ))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][4]~q & +// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\z80_|address_pins_|abus[9]~17_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~q ), + .datac(\z80_|address_pins_|abus[8]~18_combout ), + .datad(\ula_|zx_keyboard_|keys[1][4]~q ), + .cin(gnd), + .combout(\D[4]~85_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~85 .lut_mask = 16'hA2F3; +defparam \D[4]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y11_N20 +cycloneive_lcell_comb \D[4]~86 ( +// Equation(s): +// \D[4]~86_combout = (\ula_|zx_keyboard_|key_row~3_combout & (\D[4]~85_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][4]~q )))) + + .dataa(\ula_|zx_keyboard_|key_row~3_combout ), + .datab(\z80_|address_pins_|abus[11]~19_combout ), + .datac(\ula_|zx_keyboard_|keys[3][4]~q ), + .datad(\D[4]~85_combout ), + .cin(gnd), + .combout(\D[4]~86_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~86 .lut_mask = 16'h8A00; +defparam \D[4]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N24 +cycloneive_lcell_comb \D[4]~89 ( +// Equation(s): +// \D[4]~89_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~88_combout & (\D[4]~87_combout & \D[4]~86_combout ))) + + .dataa(\D[4]~88_combout ), + .datab(\D[4]~87_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[4]~86_combout ), + .cin(gnd), + .combout(\D[4]~89_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~89 .lut_mask = 16'hF8F0; +defparam \D[4]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N18 +cycloneive_lcell_comb \D[4]~93 ( +// Equation(s): +// \D[4]~93_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), + .cin(gnd), + .combout(\D[4]~93_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~93 .lut_mask = 16'hF838; +defparam \D[4]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N4 +cycloneive_lcell_comb \D[4]~94 ( +// Equation(s): +// \D[4]~94_combout = (\D[4]~93_combout & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )))) # (!\D[4]~93_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datab(\D[4]~93_combout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), + .cin(gnd), + .combout(\D[4]~94_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~94 .lut_mask = 16'hCEC2; +defparam \D[4]~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y22_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X22_Y21_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y33_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N8 +cycloneive_lcell_comb \D[4]~90 ( +// Equation(s): +// \D[4]~90_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .cin(gnd), + .combout(\D[4]~90_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~90 .lut_mask = 16'hE6A2; +defparam \D[4]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y30_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N22 +cycloneive_lcell_comb \D[4]~91 ( +// Equation(s): +// \D[4]~91_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout $ ((\D[4]~90_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[4]~90_combout & +// \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\D[4]~90_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .cin(gnd), + .combout(\D[4]~91_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~91 .lut_mask = 16'h4B48; +defparam \D[4]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N28 +cycloneive_lcell_comb \D[4]~92 ( +// Equation(s): +// \D[4]~92_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[4]~90_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[4]~90_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout & !\D[4]~91_combout )) # (!\D[4]~90_combout & ((\D[4]~91_combout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[4]~90_combout ), + .datad(\D[4]~91_combout ), + .cin(gnd), + .combout(\D[4]~92_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~92 .lut_mask = 16'hC3E0; +defparam \D[4]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N8 +cycloneive_lcell_comb \D[4]~125 ( +// Equation(s): +// \D[4]~125_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\D[4]~94_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\D[4]~92_combout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (((\D[4]~94_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\D[4]~94_combout ), + .datad(\D[4]~92_combout ), + .cin(gnd), + .combout(\D[4]~125_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~125 .lut_mask = 16'hF2D0; +defparam \D[4]~125 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N30 +cycloneive_lcell_comb \D[4]~110 ( +// Equation(s): +// \D[4]~110_combout = ((\Equal2~0_combout & (\D[4]~89_combout )) # (!\Equal2~0_combout & ((\D[4]~125_combout )))) # (!\Equal2~1_combout ) + + .dataa(\D[4]~89_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[4]~125_combout ), + .datad(\Equal2~1_combout ), + .cin(gnd), + .combout(\D[4]~110_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~110 .lut_mask = 16'hB8FF; +defparam \D[4]~110 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N4 +cycloneive_lcell_comb \D[4]~111 ( +// Equation(s): +// \D[4]~111_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[4]~110_combout & \z80_|data_pins_|dout [4])))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[4]~110_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[4]~110_combout ), + .datad(\z80_|data_pins_|dout [4]), + .cin(gnd), + .combout(\D[4]~111_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~111 .lut_mask = 16'hF151; +defparam \D[4]~111 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N10 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\D[4]~111_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[4]~19_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[4]~111_combout & +// (((\z80_|bus_control_|db[4]~19_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) + + .dataa(\D[4]~111_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|bus_control_|db[4]~19_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N11 +dffeas \z80_|data_pins_|dout[4] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N18 +cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( +// Equation(s): +// \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|data_pins_|dout [4]), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[0]~4_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'hBB00; +defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N6 +cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( +// Equation(s): +// \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[4]~18_combout ), + .datac(\z80_|alu_control_|db[4]~33_combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[4]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hC4FF; +defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N23 +dffeas \z80_|ir_|opcode[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[4]~19_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal32~0_combout = (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal32~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N26 +cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( +// Equation(s): +// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal36~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal43~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal36~0_combout ), + .datab(\z80_|pla_decode_|Equal3~2_combout ), + .datac(\z80_|pla_decode_|Equal79~0_combout ), + .datad(\z80_|pla_decode_|Equal43~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|test1~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; +defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N30 +cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( +// Equation(s): +// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~53_combout & (((\z80_|interrupts_|test1~2_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|interrupts_|test1~2_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|setM1~53_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|test1~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h00FD; +defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N7 +dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|interrupts_|nmi_armed~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|interrupts_|test1~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N16 +cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( +// Equation(s): +// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hF8FC; +defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_flags_alu~19_combout ) # ((\z80_|alu_control_|db[5]~17_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_high[1]~19_combout & +// (((\z80_|alu_control_|db[5]~17_combout & \z80_|execute_|ctl_flags_bus~combout )))) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_flags_alu~19_combout ), + .datac(\z80_|alu_control_|db[5]~17_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N3 +dffeas \z80_|alu_flags_|flags_yf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_yf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_yf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N18 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( +// Equation(s): +// \z80_|alu_control_|db[5]~15_combout = (\z80_|alu_control_|out[6]~2_combout & (((\z80_|alu_flags_|flags_yf~q )) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_control_|out[6]~2_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & +// ((\z80_|alu_flags_|flags_yf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_control_|out[6]~2_combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_flags_|flags_yf~q ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hF3A2; +defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N12 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~16 ( +// Equation(s): +// \z80_|alu_control_|db[5]~16_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~15_combout & ((\z80_|reg_file_|gdfx_temp0[5]~71_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|sw1_|db_down[5]~0_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .datad(\z80_|alu_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~16 .lut_mask = 16'hA200; +defparam \z80_|alu_control_|db[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~17 ( +// Equation(s): +// \z80_|alu_control_|db[5]~17_combout = ((\z80_|alu_control_|db[5]~16_combout & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_control_|db[5]~16_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_control_|db[6]~13_combout ), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~17 .lut_mask = 16'hAF2F; +defparam \z80_|alu_control_|db[5]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y33_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; +// synopsys translate_on + +// Location: M9K_X33_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80000001C000000160F000FF70C0007F78C00000F05001007870010010000000000800000038000000F000000070000000300000006000000000000040000000F00000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000001D108000BEDA9FA9698A000000000000000000000000FFFFFFFF408102048004188297E014DA9FA9E9CA00000000000000000000000000000000FFFFFFFC800400CA972208DA9FA9CD8E00000000000000000000000000000000FFFFFFFC8004046A97A289FA9FA9CDC20000000000000000000000007FFFFFFC8000000280040E2A97A2997A9DA9CFC20000000000000000000000007FFFFFFE8000000280042EB28002BE369DA9274200000000000000000000000040810206BFFFFFFE9FE430A29D82AC3E8009E34A000000000000000000000000000000023FFFFFFC9FE4B1829FA2800E8009436A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h9FE8334E88F827C697F88D1600A80A44809E8FC2B86999C2B85B3A82B1D32A869FE8336A88F807CA97F88F96A0A80EC2838E8D42B9E98FC2B86B3B82B0D7B2D2800832E288F827CA97F88B82A0080EC683869542B939B8C2B1AB0F8290B730C2800826EA8878078297F88AD2A0280EC283E694C2B83A3BC2A3AB3E8291A316AA800826EE881807C69DE8ABD6A0280BC282209CD2BA2A3D42A2737F82918314E2800806E6981805C69D48AED6A1E80BCA82709FC2BB223DC2A07B7F8295DF11C2800886E6980805869848AAC6A1E42DC281789DC2BBAA3DC6A02B7582955F00928008A6EE98082D9618088AC8A0F40FC289E89DC2BBCA3DC2A18B7782154F02F0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y6_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'hE10F8B8C100323720BEBBDEBB81DF13FF97B252E2CB4F27BA091FBD0002D1A611E1EDBBC716D44D2912B80041C44558060CFCF15955C0D780DD5E71393920844F25E16C87C5D0308EEC52C011514BBC13AFA1028924D0C7CE738105BD47A10AA5B5C1D9D4193E4339F492B0E1A64E13AE35BE6B67AC8057BDACC155F14E906A017A1841358335450D4B26CD2A21B3D8F2211080B81EC040D7FA0B51CD48008112508062020A02490900092D2040259108806A328F4006D2AA514B42FB006ECCCCB9A360865678449975A8AE72B5C0F7BA800C1B5DC55D7D6FE2EF4EED85D00AB111821321BA426A4FE4956B43595832C271E83E060341AE5F2023FC808177383; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h1A2955372D510AC266A5445146E27000020C320FAE1557E37154040A13202DC6F40B840FB9A59B6DBB296562CB6220EFBE99D2776A202044D9101006FD221D305519198C859000004012AFF4FB060307C92BB732203BFDFEFFFFFFDFFF87FCFFFBFFEFF03FFE0FFFBFAFE0FF80787FFF7FFF83F7F87003FFBFFFFBFFFBFF0FFC0FF81FFF7FFBFFDFFFBFFFE1FF0086F3141AAB6005810A0621595A893F9D85983B9254954341968BAC8C141C90938C05B2C9CD267E11650407375FEDD6A2FEB346AAF6CFDC0791AA97B741995A3B3981E06D1A44D3711955197BB9910FCA20744915C84D6C24BAF53929814CA8A4697E8F4201145AE7415DC122A5F010436107; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h02E84F969E3C800AC610D276182020227809001A50DDDBA3487BB6AE802BA06509312DA0E620656EAF24D57C08FFB14D289613DC32083803B84DC6415FD5EDC000300A8D128FA20030ACCBAFA237B7024504D36A4BA26081137F059E78991154FE2AC2A884A8CC7FBBB21C851CC92B12E15593C0C020FFEE066558590E882D5B67459F1A8C3240FE4E6A8D028C0C088FCF471D400A19B38211004DD122212288B111114514CB11840E04828849C621392041163C00808C67223422F00110201DD18FCFFFF3FFE7F9FFFFFFF82C0B422D214711E08904524A069491774E663F48F665955B4E2C63DAC0078652D10120900298F7EE380092442AFD400BEC43C003; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N2 +cycloneive_lcell_comb \Mux2~0 ( +// Equation(s): +// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~22_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .cin(gnd), + .combout(\Mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux2~0 .lut_mask = 16'hB9A8; +defparam \Mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N24 +cycloneive_lcell_comb \Mux2~1 ( +// Equation(s): +// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datad(\Mux2~0_combout ), + .cin(gnd), + .combout(\Mux2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Mux2~1 .lut_mask = 16'hBBC0; +defparam \Mux2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y2_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # +// (\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout & +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 .lut_mask = 16'hCEC2; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 .lut_mask = 16'hBCB0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N30 +cycloneive_lcell_comb \D[5]~112 ( +// Equation(s): +// \D[5]~112_combout = ((\z80_|address_pins_|abus[15]~21_combout & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ))) # (!\z80_|address_pins_|abus[15]~21_combout & (\Mux2~1_combout ))) # (!\D[5]~97_combout ) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\D[5]~97_combout ), + .datac(\Mux2~1_combout ), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .cin(gnd), + .combout(\D[5]~112_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~112 .lut_mask = 16'hFB73; +defparam \D[5]~112 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N8 +cycloneive_lcell_comb \D[5]~113 ( +// Equation(s): +// \D[5]~113_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[5]~112_combout & \z80_|data_pins_|dout [5])))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[5]~112_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[5]~112_combout ), + .datad(\z80_|data_pins_|dout [5]), + .cin(gnd), + .combout(\D[5]~113_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~113 .lut_mask = 16'hF151; +defparam \D[5]~113 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N24 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|bus_control_|db[5]~15_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[5]~113_combout )))) # (!\z80_|bus_control_|db[5]~15_combout & +// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[5]~113_combout )))) + + .dataa(\z80_|bus_control_|db[5]~15_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\D[5]~113_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N25 +dffeas \z80_|data_pins_|dout[5] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N20 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( +// Equation(s): +// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(gnd), + .datab(\z80_|data_pins_|dout [5]), + .datac(\z80_|bus_control_|db[0]~4_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hC0F0; +defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( +// Equation(s): +// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~17_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|alu_control_|db[5]~17_combout ), + .datab(\z80_|bus_control_|db[0]~6_combout ), + .datac(\z80_|bus_control_|db[5]~14_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hB3F3; +defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N25 +dffeas \z80_|ir_|opcode[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[5]~15_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~11_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~46 ( +// Equation(s): +// \z80_|execute_|setM1~46_combout = (!\z80_|execute_|ctl_mRead~11_combout & (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_iorw~10_combout & \z80_|execute_|ctl_mRead~17_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|ctl_iorw~11_combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|execute_|ctl_mRead~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~46 .lut_mask = 16'h0100; +defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~40 ( +// Equation(s): +// \z80_|execute_|setM1~40_combout = (!\z80_|execute_|ctl_mWrite~7_combout & \z80_|execute_|setM1~39_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|setM1~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~40 .lut_mask = 16'h0F00; +defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|nextM~5 ( +// Equation(s): +// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|setM1~40_combout )) # (!\z80_|execute_|setM1~46_combout ))) + + .dataa(\z80_|execute_|setM1~46_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|setM1~40_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~5 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|nextM~6 ( +// Equation(s): +// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|nextM~3_combout ) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|nextM~3_combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|execute_|ixy_d~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~6 .lut_mask = 16'hB3FF; +defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|nextM~7 ( +// Equation(s): +// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~8_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|nextM~6_combout ), + .datac(\z80_|execute_|ixy_d~8_combout ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~7 .lut_mask = 16'hC8FF; +defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|nextM~9 ( +// Equation(s): +// \z80_|execute_|nextM~9_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~9 .lut_mask = 16'hE000; +defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|nextM~10 ( +// Equation(s): +// \z80_|execute_|nextM~10_combout = (\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ctl_mRead~34_combout ))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|nextM~9_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~8 ( +// Equation(s): +// \z80_|execute_|nextM~8_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ixy_d~8_combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ixy_d~8_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~8 .lut_mask = 16'h2F22; +defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|nextM~12 ( +// Equation(s): +// \z80_|execute_|nextM~12_combout = (\z80_|execute_|ctl_alu_op_low~21_combout ) # (((\z80_|execute_|nextM~10_combout ) # (\z80_|execute_|nextM~8_combout )) # (!\z80_|execute_|nextM~11_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~21_combout ), + .datab(\z80_|execute_|nextM~11_combout ), + .datac(\z80_|execute_|nextM~10_combout ), + .datad(\z80_|execute_|nextM~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|nextM~15 ( +// Equation(s): +// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|fMRead~12_combout )))) + + .dataa(\z80_|execute_|fMRead~12_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~15 .lut_mask = 16'hC040; +defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|nextM~13 ( +// Equation(s): +// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~7_combout ) # ((\z80_|execute_|nextM~12_combout ) # (\z80_|execute_|nextM~15_combout )) + + .dataa(\z80_|execute_|nextM~7_combout ), + .datab(\z80_|execute_|nextM~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~14 ( +// Equation(s): +// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~5_combout ) # ((\z80_|execute_|nextM~13_combout ) # ((!\z80_|execute_|ctl_mWrite~14_combout ) # (!\z80_|execute_|ctl_mRead~28_combout ))) + + .dataa(\z80_|execute_|nextM~5_combout ), + .datab(\z80_|execute_|nextM~13_combout ), + .datac(\z80_|execute_|ctl_mRead~28_combout ), + .datad(\z80_|execute_|ctl_mWrite~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~14 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N22 +cycloneive_lcell_comb \z80_|sequencer_|ena_M ( +// Equation(s): +// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|ena_M~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; +defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N23 +dffeas \z80_|sequencer_|DFFE_T1_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|ena_M~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T1_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N26 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0050; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N27 +dffeas \z80_|sequencer_|DFFE_T2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T2_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N30 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N31 +dffeas \z80_|sequencer_|DFFE_T3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T3_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N20 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N21 +dffeas \z80_|sequencer_|DFFE_T4_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T4_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~9_combout & (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|execute_|ctl_mWrite~9_combout & (((!\z80_|execute_|ctl_mWrite~5_combout ) # +// (!\z80_|execute_|ctl_ir_we~12_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0757; +defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~54 ( +// Equation(s): +// \z80_|execute_|setM1~54_combout = ((\z80_|execute_|ctl_iorw~11_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_iorw~11_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~54 .lut_mask = 16'hD555; +defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~25 ( +// Equation(s): +// \z80_|execute_|setM1~25_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_mRead~10_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~25 .lut_mask = 16'h2F22; +defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~26 ( +// Equation(s): +// \z80_|execute_|setM1~26_combout = (\z80_|execute_|ctl_mRead~11_combout ) # (((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~26 .lut_mask = 16'hDCFF; +defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~27 ( +// Equation(s): +// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~26_combout ) # (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|execute_|setM1~26_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~27 .lut_mask = 16'hECFF; +defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~22 ( +// Equation(s): +// \z80_|execute_|setM1~22_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~22 .lut_mask = 16'hFF04; +defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~55 ( +// Equation(s): +// \z80_|execute_|setM1~55_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|execute_|setM1~22_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|setM1~22_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~55 .lut_mask = 16'hF080; +defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~23 ( +// Equation(s): +// \z80_|execute_|setM1~23_combout = (\z80_|execute_|fMWrite~0_combout & (!\z80_|execute_|ctl_mRead~8_combout & (\z80_|execute_|fMWrite~6_combout & !\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|fMWrite~0_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|fMWrite~6_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~23 .lut_mask = 16'h0020; +defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~24 ( +// Equation(s): +// \z80_|execute_|setM1~24_combout = (\z80_|execute_|setM1~55_combout & (((\z80_|execute_|ctl_reg_in_hi~2_combout & !\z80_|execute_|setM1~23_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|setM1~55_combout & +// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|execute_|setM1~23_combout )))) + + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|setM1~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~24 .lut_mask = 16'h0ACE; +defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~28 ( +// Equation(s): +// \z80_|execute_|setM1~28_combout = (\z80_|execute_|setM1~25_combout ) # ((\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|setM1~27_combout & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|setM1~25_combout ), + .datab(\z80_|execute_|setM1~27_combout ), + .datac(\z80_|execute_|setM1~24_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~11 ( +// Equation(s): +// \z80_|execute_|setM1~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~11 .lut_mask = 16'hFF04; +defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~33 ( +// Equation(s): +// \z80_|execute_|setM1~33_combout = (\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mRead~2_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|setM1~11_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|setM1~11_combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~29 ( +// Equation(s): +// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~5_combout ) # (((\z80_|execute_|ctl_mRead~13_combout ) # (\z80_|execute_|ctl_mRead~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~29 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~31 ( +// Equation(s): +// \z80_|execute_|setM1~31_combout = (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~30_combout )) # (!\z80_|execute_|setM1~56_combout ) + + .dataa(\z80_|execute_|setM1~56_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|setM1~29_combout ), + .datad(\z80_|execute_|setM1~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~31 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~32 ( +// Equation(s): +// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~16_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & +// (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~32 .lut_mask = 16'hECA0; +defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~34 ( +// Equation(s): +// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~32_combout ) # ((\z80_|execute_|setM1~33_combout & \z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|setM1~33_combout ), + .datab(\z80_|execute_|setM1~31_combout ), + .datac(\z80_|execute_|setM1~32_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~20 ( +// Equation(s): +// \z80_|execute_|setM1~20_combout = (\z80_|execute_|ctl_mRead~9_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_flags_bus~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~20 .lut_mask = 16'h20F0; +defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~21 ( +// Equation(s): +// \z80_|execute_|setM1~21_combout = (\z80_|execute_|setM1~20_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & (\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|ixy_d~8_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|setM1~20_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~21 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~35 ( +// Equation(s): +// \z80_|execute_|setM1~35_combout = (\z80_|execute_|setM1~54_combout ) # ((\z80_|execute_|setM1~28_combout ) # ((\z80_|execute_|setM1~34_combout ) # (\z80_|execute_|setM1~21_combout ))) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(\z80_|execute_|setM1~28_combout ), + .datac(\z80_|execute_|setM1~34_combout ), + .datad(\z80_|execute_|setM1~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~35 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~15 ( +// Equation(s): +// \z80_|execute_|setM1~15_combout = (\z80_|pla_decode_|Equal21~2_combout & (!\z80_|pla_decode_|Equal32~0_combout & ((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )))) # (!\z80_|pla_decode_|Equal21~2_combout & +// (((!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~2_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~15 .lut_mask = 16'h153F; +defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~14 ( +// Equation(s): +// \z80_|execute_|setM1~14_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|execute_|ctl_alu_oe~3_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal77~1_combout ), + .datac(\z80_|pla_decode_|Equal1~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~14 .lut_mask = 16'h0003; +defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~16 ( +// Equation(s): +// \z80_|execute_|setM1~16_combout = (\z80_|interrupts_|test1~2_combout & (\z80_|execute_|setM1~15_combout & (\z80_|execute_|setM1~14_combout & !\z80_|pla_decode_|Equal2~2_combout ))) + + .dataa(\z80_|interrupts_|test1~2_combout ), + .datab(\z80_|execute_|setM1~15_combout ), + .datac(\z80_|execute_|setM1~14_combout ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0080; +defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~10 ( +// Equation(s): +// \z80_|execute_|setM1~10_combout = (\z80_|pla_decode_|Equal6~1_combout ) # (((\z80_|execute_|ctl_mWrite~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|fMWrite~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|fMWrite~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~12 ( +// Equation(s): +// \z80_|execute_|setM1~12_combout = ((\z80_|execute_|setM1~10_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout & \z80_|execute_|setM1~11_combout ))) # (!\z80_|execute_|nextM~2_combout ) + + .dataa(\z80_|execute_|nextM~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|setM1~11_combout ), + .datad(\z80_|execute_|setM1~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~12 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~8 ( +// Equation(s): +// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_al_we~13_combout & (((\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & +// \z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~8 .lut_mask = 16'hF444; +defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~9 ( +// Equation(s): +// \z80_|execute_|setM1~9_combout = ((\z80_|execute_|setM1~8_combout & \z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|execute_|ctl_flags_xy_we~17_combout ) + + .dataa(\z80_|execute_|setM1~8_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~9 .lut_mask = 16'hA0FF; +defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~13 ( +// Equation(s): +// \z80_|execute_|setM1~13_combout = ((\z80_|execute_|setM1~9_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|setM1~12_combout ))) # (!\z80_|reg_control_|reg_sel_pc~3_combout ) + + .dataa(\z80_|reg_control_|reg_sel_pc~3_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|setM1~12_combout ), + .datad(\z80_|execute_|setM1~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~13 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~18 ( +// Equation(s): +// \z80_|execute_|setM1~18_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|execute_|setM1~17_combout & (\z80_|execute_|ctl_alu_op_low~38_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|setM1~17_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~18 .lut_mask = 16'h0040; +defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~19 ( +// Equation(s): +// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~13_combout ) # (((!\z80_|execute_|setM1~16_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|setM1~18_combout )) + + .dataa(\z80_|execute_|setM1~16_combout ), + .datab(\z80_|execute_|setM1~13_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|setM1~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~19 .lut_mask = 16'hDCFF; +defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~43 ( +// Equation(s): +// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|pla_decode_|Equal37~0_combout & !\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0004; +defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~42 ( +// Equation(s): +// \z80_|execute_|setM1~42_combout = (!\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout )) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|setM1~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0101; +defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~44 ( +// Equation(s): +// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~42_combout & !\z80_|pla_decode_|Equal48~0_combout ))) + + .dataa(\z80_|execute_|setM1~43_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|setM1~42_combout ), + .datad(\z80_|pla_decode_|Equal48~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~44 .lut_mask = 16'h0020; +defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~45 ( +// Equation(s): +// \z80_|execute_|setM1~45_combout = (\z80_|execute_|setM1~41_combout & (\z80_|execute_|setM1~44_combout & ((!\z80_|pla_decode_|Equal1~4_combout ) # (!\z80_|pla_decode_|Equal2~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal2~1_combout ), + .datab(\z80_|execute_|setM1~41_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|execute_|setM1~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~45 .lut_mask = 16'h4C00; +defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~51 ( +// Equation(s): +// \z80_|execute_|setM1~51_combout = (\z80_|execute_|setM1~45_combout & (\z80_|execute_|setM1~47_combout & (\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~16_combout ))) + + .dataa(\z80_|execute_|setM1~45_combout ), + .datab(\z80_|execute_|setM1~47_combout ), + .datac(\z80_|execute_|setM1~50_combout ), + .datad(\z80_|execute_|setM1~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~51 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N18 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N19 +dffeas \z80_|sequencer_|T6 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|T6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|T6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~52 ( +// Equation(s): +// \z80_|execute_|setM1~52_combout = (\z80_|execute_|setM1~51_combout & ((\z80_|execute_|setM1~40_combout ) # ((\z80_|sequencer_|T6~q & !\z80_|execute_|setM1~41_combout )))) # (!\z80_|execute_|setM1~51_combout & (\z80_|sequencer_|T6~q & +// (!\z80_|execute_|setM1~41_combout ))) + + .dataa(\z80_|execute_|setM1~51_combout ), + .datab(\z80_|sequencer_|T6~q ), + .datac(\z80_|execute_|setM1~41_combout ), + .datad(\z80_|execute_|setM1~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~52 .lut_mask = 16'hAE0C; +defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~53 ( +// Equation(s): +// \z80_|execute_|setM1~53_combout = (!\z80_|execute_|setM1~35_combout & (!\z80_|execute_|setM1~19_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~52_combout )))) + + .dataa(\z80_|execute_|setM1~35_combout ), + .datab(\z80_|execute_|setM1~19_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|setM1~52_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~53 .lut_mask = 16'h1011; +defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N14 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hCCC0; +defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N15 +dffeas \z80_|sequencer_|DFFE_M1_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M1_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N28 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h44C0; +defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N29 +dffeas \z80_|sequencer_|DFFE_M2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M2_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h0F0C; +defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N28 cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( // Equation(s): -// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_apin_mux~1_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) +// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_apin_mux~1_combout ), - .datac(\z80_|execute_|ctl_inc_dec~6_combout ), - .datad(gnd), + .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_dec~6_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_apin_mux~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'h8F8F; +defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'h88FF; defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y16_N18 +// Location: LCCOMB_X28_Y16_N20 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[0]~0 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [0]))) @@ -53232,7 +53700,7 @@ defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hDD88; defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y16_N19 +// Location: FF_X28_Y16_N21 dffeas \z80_|address_pins_|DFFE_apin_latch[0] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), @@ -53251,228 +53719,332 @@ defparam \z80_|address_pins_|DFFE_apin_latch[0] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N12 -cycloneive_lcell_comb \D[0]~59 ( +// Location: LCCOMB_X24_Y15_N30 +cycloneive_lcell_comb \D[0]~66 ( // Equation(s): -// \D[0]~59_combout = (\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout ))) - - .dataa(\Equal2~0_combout ), - .datab(\D[0]~51_combout ), - .datac(\D[0]~106_combout ), - .datad(gnd), - .cin(gnd), - .combout(\D[0]~59_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~59 .lut_mask = 16'hD8D8; -defparam \D[0]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N8 -cycloneive_lcell_comb \D[0]~60 ( -// Equation(s): -// \D[0]~60_combout = (\Equal2~1_combout & (\D[0]~59_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [0]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [0]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[0]~59_combout ), - .cin(gnd), - .combout(\D[0]~60_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~60 .lut_mask = 16'hCF45; -defparam \D[0]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y18_N20 -cycloneive_lcell_comb \D[1]~61 ( -// Equation(s): -// \D[1]~61_combout = (\Equal2~0_combout & (\D[1]~32_combout )) # (!\Equal2~0_combout & ((\D[1]~103_combout ))) - - .dataa(\Equal2~0_combout ), - .datab(gnd), - .datac(\D[1]~32_combout ), - .datad(\D[1]~103_combout ), - .cin(gnd), - .combout(\D[1]~61_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~61 .lut_mask = 16'hF5A0; -defparam \D[1]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y18_N22 -cycloneive_lcell_comb \D[1]~62 ( -// Equation(s): -// \D[1]~62_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~61_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~61_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [1]), - .datad(\D[1]~61_combout ), - .cin(gnd), - .combout(\D[1]~62_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~62 .lut_mask = 16'hF531; -defparam \D[1]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N12 -cycloneive_lcell_comb \D[2]~63 ( -// Equation(s): -// \D[2]~63_combout = (\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout ))) - - .dataa(\Equal2~0_combout ), - .datab(gnd), - .datac(\D[2]~104_combout ), - .datad(\D[2]~105_combout ), - .cin(gnd), - .combout(\D[2]~63_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~63 .lut_mask = 16'hF5A0; -defparam \D[2]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N26 -cycloneive_lcell_comb \D[2]~64 ( -// Equation(s): -// \D[2]~64_combout = (\z80_|data_pins_|dout [2] & (((\D[2]~63_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [2] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[2]~63_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [2]), - .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[2]~63_combout ), - .cin(gnd), - .combout(\D[2]~64_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~64 .lut_mask = 16'hAF23; -defparam \D[2]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N2 -cycloneive_lcell_comb \D[3]~75 ( -// Equation(s): -// \D[3]~75_combout = (\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout ))) - - .dataa(\D[3]~69_combout ), - .datab(gnd), - .datac(\Equal2~0_combout ), - .datad(\D[3]~108_combout ), - .cin(gnd), - .combout(\D[3]~75_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~75 .lut_mask = 16'hAFA0; -defparam \D[3]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N20 -cycloneive_lcell_comb \D[3]~76 ( -// Equation(s): -// \D[3]~76_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~75_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[3]~75_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [3]), - .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[3]~75_combout ), - .cin(gnd), - .combout(\D[3]~76_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~76 .lut_mask = 16'hAF23; -defparam \D[3]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N24 -cycloneive_lcell_comb \D[4]~82 ( -// Equation(s): -// \D[4]~82_combout = (\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout ))) - - .dataa(\Equal2~0_combout ), - .datab(\D[4]~81_combout ), - .datac(gnd), - .datad(\D[4]~109_combout ), - .cin(gnd), - .combout(\D[4]~82_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~82 .lut_mask = 16'hDD88; -defparam \D[4]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N26 -cycloneive_lcell_comb \D[4]~83 ( -// Equation(s): -// \D[4]~83_combout = (\Equal2~1_combout & (\D[4]~82_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [4]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [4]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[4]~82_combout ), - .cin(gnd), - .combout(\D[4]~83_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~83 .lut_mask = 16'hCF45; -defparam \D[4]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N24 -cycloneive_lcell_comb \D[6]~92 ( -// Equation(s): -// \D[6]~92_combout = (\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout )) +// \D[0]~66_combout = (\Equal2~0_combout & (\D[0]~58_combout )) # (!\Equal2~0_combout & ((\D[0]~120_combout ))) .dataa(gnd), .datab(\Equal2~0_combout ), - .datac(\D[6]~111_combout ), - .datad(\D[6]~86_combout ), + .datac(\D[0]~58_combout ), + .datad(\D[0]~120_combout ), .cin(gnd), - .combout(\D[6]~92_combout ), + .combout(\D[0]~66_combout ), .cout()); // synopsys translate_off -defparam \D[6]~92 .lut_mask = 16'hFC30; -defparam \D[6]~92 .sum_lutc_input = "datac"; +defparam \D[0]~66 .lut_mask = 16'hF3C0; +defparam \D[0]~66 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N10 -cycloneive_lcell_comb \D[6]~93 ( +// Location: LCCOMB_X25_Y15_N18 +cycloneive_lcell_comb \D[0]~67 ( // Equation(s): -// \D[6]~93_combout = (\Equal2~1_combout & (\D[6]~92_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [6]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) +// \D[0]~67_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [0] & ((\D[0]~66_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[0]~66_combout ) # (!\Equal2~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[6]~92_combout ), + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|data_pins_|dout [0]), + .datac(\Equal2~1_combout ), + .datad(\D[0]~66_combout ), .cin(gnd), - .combout(\D[6]~93_combout ), + .combout(\D[0]~67_combout ), .cout()); // synopsys translate_off -defparam \D[6]~93 .lut_mask = 16'hCF45; -defparam \D[6]~93 .sum_lutc_input = "datac"; +defparam \D[0]~67 .lut_mask = 16'hDD0D; +defparam \D[0]~67 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N0 -cycloneive_lcell_comb \z80_|nM1_int~3 ( +// Location: LCCOMB_X25_Y17_N24 +cycloneive_lcell_comb \D[0]~121 ( // Equation(s): -// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) +// \D[0]~121_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout ) # ((\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .cin(gnd), + .combout(\D[0]~121_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~121 .lut_mask = 16'hFF20; +defparam \D[0]~121 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N16 +cycloneive_lcell_comb \D[1]~68 ( +// Equation(s): +// \D[1]~68_combout = (\Equal2~0_combout & (\D[1]~34_combout )) # (!\Equal2~0_combout & ((\D[1]~118_combout ))) .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|setM1~52_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[1]~34_combout ), + .datad(\D[1]~118_combout ), + .cin(gnd), + .combout(\D[1]~68_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~68 .lut_mask = 16'hF3C0; +defparam \D[1]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N14 +cycloneive_lcell_comb \D[1]~69 ( +// Equation(s): +// \D[1]~69_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~68_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[1]~68_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\Equal2~1_combout ), + .datad(\D[1]~68_combout ), + .cin(gnd), + .combout(\D[1]~69_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~69 .lut_mask = 16'hDD0D; +defparam \D[1]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N16 +cycloneive_lcell_comb \D[2]~70 ( +// Equation(s): +// \D[2]~70_combout = (\Equal2~0_combout & (\D[2]~46_combout )) # (!\Equal2~0_combout & ((\D[2]~119_combout ))) + + .dataa(gnd), + .datab(\D[2]~46_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[2]~119_combout ), + .cin(gnd), + .combout(\D[2]~70_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~70 .lut_mask = 16'hCFC0; +defparam \D[2]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N14 +cycloneive_lcell_comb \D[2]~71 ( +// Equation(s): +// \D[2]~71_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [2] & ((\D[2]~70_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[2]~70_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\Equal2~1_combout ), + .datac(\z80_|data_pins_|dout [2]), + .datad(\D[2]~70_combout ), + .cin(gnd), + .combout(\D[2]~71_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~71 .lut_mask = 16'hF531; +defparam \D[2]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N24 +cycloneive_lcell_comb \D[3]~83 ( +// Equation(s): +// \D[3]~83_combout = (\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(gnd), + .datac(\z80_|data_pins_|dout [3]), + .datad(gnd), + .cin(gnd), + .combout(\D[3]~83_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~83 .lut_mask = 16'hF5F5; +defparam \D[3]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N6 +cycloneive_lcell_comb \D[3]~84 ( +// Equation(s): +// \D[3]~84_combout = (\D[3]~83_combout & ((\D[3]~122_combout ) # ((\D[3]~82_combout ) # (!\Equal2~1_combout )))) + + .dataa(\D[3]~122_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[3]~82_combout ), + .datad(\D[3]~83_combout ), + .cin(gnd), + .combout(\D[3]~84_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~84 .lut_mask = 16'hFB00; +defparam \D[3]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N20 +cycloneive_lcell_comb \D[4]~95 ( +// Equation(s): +// \D[4]~95_combout = (\Equal2~0_combout & (\D[4]~89_combout )) # (!\Equal2~0_combout & ((\D[4]~125_combout ))) + + .dataa(\D[4]~89_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[4]~125_combout ), + .datad(gnd), + .cin(gnd), + .combout(\D[4]~95_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~95 .lut_mask = 16'hB8B8; +defparam \D[4]~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N6 +cycloneive_lcell_comb \D[4]~96 ( +// Equation(s): +// \D[4]~96_combout = (\z80_|data_pins_|dout [4] & (((\D[4]~95_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [4] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[4]~95_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [4]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[4]~95_combout ), + .cin(gnd), + .combout(\D[4]~96_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~96 .lut_mask = 16'hAF23; +defparam \D[4]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N18 +cycloneive_lcell_comb \D[5]~126 ( +// Equation(s): +// \D[5]~126_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\Mux2~1_combout )) # +// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ))))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\Mux2~1_combout ), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .cin(gnd), + .combout(\D[5]~126_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~126 .lut_mask = 16'hFB40; +defparam \D[5]~126 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N0 +cycloneive_lcell_comb \D[5]~98 ( +// Equation(s): +// \D[5]~98_combout = (\z80_|data_pins_|dout [5] & (((\D[5]~126_combout )) # (!\D[5]~97_combout ))) # (!\z80_|data_pins_|dout [5] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[5]~126_combout ) # (!\D[5]~97_combout )))) + + .dataa(\z80_|data_pins_|dout [5]), + .datab(\D[5]~97_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[5]~126_combout ), + .cin(gnd), + .combout(\D[5]~98_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~98 .lut_mask = 16'hAF23; +defparam \D[5]~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N18 +cycloneive_lcell_comb \D[6]~105 ( +// Equation(s): +// \D[6]~105_combout = (\Equal2~0_combout & ((\D[6]~99_combout ))) # (!\Equal2~0_combout & (\D[6]~127_combout )) + + .dataa(gnd), + .datab(\Equal2~0_combout ), + .datac(\D[6]~127_combout ), + .datad(\D[6]~99_combout ), + .cin(gnd), + .combout(\D[6]~105_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~105 .lut_mask = 16'hFC30; +defparam \D[6]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N0 +cycloneive_lcell_comb \D[6]~106 ( +// Equation(s): +// \D[6]~106_combout = (\z80_|data_pins_|dout [6] & (((\D[6]~105_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [6] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[6]~105_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [6]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[6]~105_combout ), + .cin(gnd), + .combout(\D[6]~106_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~106 .lut_mask = 16'hAF23; +defparam \D[6]~106 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N10 +cycloneive_lcell_comb \D[7]~128 ( +// Equation(s): +// \D[7]~128_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux0~1_combout ))))) # +// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .datad(\Mux0~1_combout ), + .cin(gnd), + .combout(\D[7]~128_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~128 .lut_mask = 16'hF2D0; +defparam \D[7]~128 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N16 +cycloneive_lcell_comb \D[7]~107 ( +// Equation(s): +// \D[7]~107_combout = (\z80_|data_pins_|dout [7] & (((\D[7]~128_combout ) # (!\D[5]~97_combout )))) # (!\z80_|data_pins_|dout [7] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[7]~128_combout ) # (!\D[5]~97_combout )))) + + .dataa(\z80_|data_pins_|dout [7]), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\D[5]~97_combout ), + .datad(\D[7]~128_combout ), + .cin(gnd), + .combout(\D[7]~107_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~107 .lut_mask = 16'hBB0B; +defparam \D[7]~107 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N6 +cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nIORQ_out~0_combout = (!\z80_|memory_ifc_|DFFE_intr_ff3~q & (!\z80_|memory_ifc_|iorq~0_combout & !\z80_|memory_ifc_|wait_iorqinta~q )) + + .dataa(gnd), + .datab(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .datac(\z80_|memory_ifc_|iorq~0_combout ), + .datad(\z80_|memory_ifc_|wait_iorqinta~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'h0003; +defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N12 +cycloneive_lcell_comb \z80_|nM1_int~3 ( +// Equation(s): +// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), .combout(\z80_|nM1_int~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|nM1_int~3 .lut_mask = 16'hFC00; +defparam \z80_|nM1_int~3 .lut_mask = 16'hCCC0; defparam \z80_|nM1_int~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N1 +// Location: FF_X40_Y13_N13 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|nM1_int~3_combout ), @@ -53491,7 +54063,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N30 +// Location: LCCOMB_X40_Y11_N4 cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder ( // Equation(s): // \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -53508,7 +54080,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N31 +// Location: FF_X40_Y11_N5 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ), @@ -53527,7 +54099,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .power_up = "low"; // synopsys translate_on -// Location: FF_X43_Y17_N25 +// Location: FF_X40_Y11_N27 dffeas \z80_|memory_ifc_|DFFE_mreq_ff2 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -53546,31 +54118,31 @@ defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N24 +// Location: LCCOMB_X40_Y11_N26 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~0 ( // Equation(s): // \z80_|memory_ifc_|nMREQ_out~0_combout = (\z80_|memory_ifc_|wait_mwr~q ) # ((\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q & !\z80_|memory_ifc_|DFFE_mreq_ff2~q ))) - .dataa(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), - .datab(\z80_|memory_ifc_|wait_mwr~q ), + .dataa(\z80_|memory_ifc_|wait_mwr~q ), + .datab(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), .datac(\z80_|memory_ifc_|DFFE_mreq_ff2~q ), .datad(\z80_|memory_ifc_|mwr_wr~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFCE; +defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFAE; defparam \z80_|memory_ifc_|nMREQ_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N2 +// Location: LCCOMB_X40_Y11_N2 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~1 ( // Equation(s): -// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nMREQ_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|nRD_out~0_combout ))) +// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nMREQ_out~0_combout & !\z80_|memory_ifc_|nRD_out~0_combout ))) - .dataa(\z80_|memory_ifc_|wait_mrd~q ), - .datab(\z80_|memory_ifc_|nMREQ_out~0_combout ), - .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .dataa(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .datab(\z80_|memory_ifc_|wait_mrd~q ), + .datac(\z80_|memory_ifc_|nMREQ_out~0_combout ), .datad(\z80_|memory_ifc_|nRD_out~0_combout ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~1_combout ), @@ -53593,24 +54165,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( -// Equation(s): -// \ula_|i2c_loader_|state.Idle~feeder_combout = VCC - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Idle~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; -defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y24_N0 +// Location: LCCOMB_X1_Y24_N18 cycloneive_lcell_comb \ula_|i2c_loader_|divider[0]~15 ( // Equation(s): // \ula_|i2c_loader_|divider[0]~15_combout = !\ula_|i2c_loader_|divider [0] @@ -53627,7 +54182,7 @@ defparam \ula_|i2c_loader_|divider[0]~15 .lut_mask = 16'h0F0F; defparam \ula_|i2c_loader_|divider[0]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X4_Y24_N1 +// Location: FF_X1_Y24_N19 dffeas \ula_|i2c_loader_|divider[0] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[0]~15_combout ), @@ -53646,14 +54201,14 @@ defparam \ula_|i2c_loader_|divider[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N10 +// Location: LCCOMB_X1_Y24_N8 cycloneive_lcell_comb \ula_|i2c_loader_|divider[1]~5 ( // Equation(s): -// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] $ (VCC))) # (!\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] & VCC)) -// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [1] & \ula_|i2c_loader_|divider [0])) +// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] $ (VCC))) # (!\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] & VCC)) +// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [0] & \ula_|i2c_loader_|divider [1])) - .dataa(\ula_|i2c_loader_|divider [1]), - .datab(\ula_|i2c_loader_|divider [0]), + .dataa(\ula_|i2c_loader_|divider [0]), + .datab(\ula_|i2c_loader_|divider [1]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -53664,7 +54219,7 @@ defparam \ula_|i2c_loader_|divider[1]~5 .lut_mask = 16'h6688; defparam \ula_|i2c_loader_|divider[1]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X4_Y24_N11 +// Location: FF_X1_Y24_N9 dffeas \ula_|i2c_loader_|divider[1] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[1]~5_combout ), @@ -53683,7 +54238,7 @@ defparam \ula_|i2c_loader_|divider[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N12 +// Location: LCCOMB_X1_Y24_N10 cycloneive_lcell_comb \ula_|i2c_loader_|divider[2]~7 ( // Equation(s): // \ula_|i2c_loader_|divider[2]~7_combout = (\ula_|i2c_loader_|divider [2] & (!\ula_|i2c_loader_|divider[1]~6 )) # (!\ula_|i2c_loader_|divider [2] & ((\ula_|i2c_loader_|divider[1]~6 ) # (GND))) @@ -53701,7 +54256,7 @@ defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|divider[2]~7 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N13 +// Location: FF_X1_Y24_N11 dffeas \ula_|i2c_loader_|divider[2] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[2]~7_combout ), @@ -53720,25 +54275,25 @@ defparam \ula_|i2c_loader_|divider[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N14 +// Location: LCCOMB_X1_Y24_N12 cycloneive_lcell_comb \ula_|i2c_loader_|divider[3]~9 ( // Equation(s): // \ula_|i2c_loader_|divider[3]~9_combout = (\ula_|i2c_loader_|divider [3] & (\ula_|i2c_loader_|divider[2]~8 $ (GND))) # (!\ula_|i2c_loader_|divider [3] & (!\ula_|i2c_loader_|divider[2]~8 & VCC)) // \ula_|i2c_loader_|divider[3]~10 = CARRY((\ula_|i2c_loader_|divider [3] & !\ula_|i2c_loader_|divider[2]~8 )) - .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [3]), + .dataa(\ula_|i2c_loader_|divider [3]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|divider[2]~8 ), .combout(\ula_|i2c_loader_|divider[3]~9_combout ), .cout(\ula_|i2c_loader_|divider[3]~10 )); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[3]~9 .lut_mask = 16'hC30C; +defparam \ula_|i2c_loader_|divider[3]~9 .lut_mask = 16'hA50A; defparam \ula_|i2c_loader_|divider[3]~9 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N15 +// Location: FF_X1_Y24_N13 dffeas \ula_|i2c_loader_|divider[3] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[3]~9_combout ), @@ -53757,7 +54312,24 @@ defparam \ula_|i2c_loader_|divider[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N16 +// Location: LCCOMB_X1_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( +// Equation(s): +// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [1])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [3]) + + .dataa(\ula_|i2c_loader_|divider [3]), + .datab(\ula_|i2c_loader_|divider [0]), + .datac(\ula_|i2c_loader_|divider [1]), + .datad(\ula_|i2c_loader_|divider [2]), + .cin(gnd), + .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; +defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N14 cycloneive_lcell_comb \ula_|i2c_loader_|divider[4]~11 ( // Equation(s): // \ula_|i2c_loader_|divider[4]~11_combout = (\ula_|i2c_loader_|divider [4] & (!\ula_|i2c_loader_|divider[3]~10 )) # (!\ula_|i2c_loader_|divider [4] & ((\ula_|i2c_loader_|divider[3]~10 ) # (GND))) @@ -53775,7 +54347,7 @@ defparam \ula_|i2c_loader_|divider[4]~11 .lut_mask = 16'h3C3F; defparam \ula_|i2c_loader_|divider[4]~11 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N17 +// Location: FF_X1_Y24_N15 dffeas \ula_|i2c_loader_|divider[4] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[4]~11_combout ), @@ -53794,7 +54366,7 @@ defparam \ula_|i2c_loader_|divider[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N18 +// Location: LCCOMB_X1_Y24_N16 cycloneive_lcell_comb \ula_|i2c_loader_|divider[5]~13 ( // Equation(s): // \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider[4]~12 $ (!\ula_|i2c_loader_|divider [5]) @@ -53811,7 +54383,7 @@ defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hF00F; defparam \ula_|i2c_loader_|divider[5]~13 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N19 +// Location: FF_X1_Y24_N17 dffeas \ula_|i2c_loader_|divider[5] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[5]~13_combout ), @@ -53830,1115 +54402,23 @@ defparam \ula_|i2c_loader_|divider[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( -// Equation(s): -// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [3])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [1]) - - .dataa(\ula_|i2c_loader_|divider [1]), - .datab(\ula_|i2c_loader_|divider [0]), - .datac(\ula_|i2c_loader_|divider [3]), - .datad(\ula_|i2c_loader_|divider [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; -defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y24_N8 +// Location: LCCOMB_X1_Y24_N30 cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0 ( // Equation(s): -// \ula_|i2c_loader_|WideAnd0~combout = ((\ula_|i2c_loader_|WideAnd0~0_combout ) # (!\ula_|i2c_loader_|divider [4])) # (!\ula_|i2c_loader_|divider [5]) +// \ula_|i2c_loader_|WideAnd0~combout = (\ula_|i2c_loader_|WideAnd0~0_combout ) # ((!\ula_|i2c_loader_|divider [5]) # (!\ula_|i2c_loader_|divider [4])) .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [5]), - .datac(\ula_|i2c_loader_|WideAnd0~0_combout ), - .datad(\ula_|i2c_loader_|divider [4]), + .datab(\ula_|i2c_loader_|WideAnd0~0_combout ), + .datac(\ula_|i2c_loader_|divider [4]), + .datad(\ula_|i2c_loader_|divider [5]), .cin(gnd), .combout(\ula_|i2c_loader_|WideAnd0~combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hF3FF; +defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hCFFF; defparam \ula_|i2c_loader_|WideAnd0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N1 -dffeas \ula_|i2c_loader_|state.Idle ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Idle~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Idle~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Idle .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Idle .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|phase~0 ( -// Equation(s): -// \ula_|i2c_loader_|phase~0_combout = (!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|phase~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|phase~0 .lut_mask = 16'h0F00; -defparam \ula_|i2c_loader_|phase~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N5 -dffeas \ula_|i2c_loader_|phase[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|phase~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|phase [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|phase[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|phase[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|phase~1 ( -// Equation(s): -// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [0] $ (\ula_|i2c_loader_|phase [1]))) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|phase~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h3C00; -defparam \ula_|i2c_loader_|phase~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N15 -dffeas \ula_|i2c_loader_|phase[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|phase~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|phase [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|phase[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|phase[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~5_combout = (!\ula_|i2c_loader_|nbit [0]) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbit [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h5F5F; -defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) -// \ula_|i2c_loader_|thisbyte[0]~9 = CARRY(\ula_|i2c_loader_|thisbyte [0]) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~8_combout ), - .cout(\ula_|i2c_loader_|thisbyte[0]~9 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; -defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( -// Equation(s): -// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Mux42~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hF000; -defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [0] $ (!\ula_|i2c_loader_|nbyte [1])))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Start~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hFF84; -defparam \ula_|i2c_loader_|nbyte~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state.Ack~q ) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hC0C0; -defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X0_Y23_N1 -cycloneive_io_ibuf \I2C_SDAT~input ( - .i(I2C_SDAT), - .ibar(gnd), - .o(\I2C_SDAT~input_o )); -// synopsys translate_off -defparam \I2C_SDAT~input .bus_hold = "false"; -defparam \I2C_SDAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hEFE0; -defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|thisbyte[0]~7_combout & \ula_|i2c_loader_|nbyte[0]~1_combout )))) - - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hD888; -defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~3_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|nbyte[0]~2_combout )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), - .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h3000; -defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N29 -dffeas \ula_|i2c_loader_|nbyte[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbyte~4_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbyte [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbyte[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Stop~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h1010; -defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Stop~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))) # -// (!\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Stop~q )))) - - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Stop~q ), - .datad(\ula_|i2c_loader_|state.Stop~0_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Stop~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF4B0; -defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N3 -dffeas \ula_|i2c_loader_|state.Stop ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Stop~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Stop~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Ack~q ))) - - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Ack~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Idle~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; -defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])))) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|nbit [0]), - .datac(\ula_|i2c_loader_|nbit [2]), - .datad(\ula_|i2c_loader_|nbit [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; -defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N1 -dffeas \ula_|i2c_loader_|nbit[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~0_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [0]))) - - .dataa(\ula_|i2c_loader_|nbit [1]), - .datab(\ula_|i2c_loader_|nbit [2]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|nbit [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~0 .lut_mask = 16'h0010; -defparam \ula_|i2c_loader_|state.Done~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Done~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|state.Idle~0_combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), - .datad(\ula_|i2c_loader_|state.Done~0_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hAF2F; -defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Data~q ))))) # -// (!\ula_|i2c_loader_|state.Ack~0_combout & (((\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|state.Ack~0_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF2D0; -defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N31 -dffeas \ula_|i2c_loader_|state.Ack ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Ack~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Ack~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hEFE0; -defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[1]~5_combout ))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h0800; -defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y23_N15 -dffeas \ula_|i2c_loader_|thisbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), - .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; -defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N17 -dffeas \ula_|i2c_loader_|thisbyte[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) -// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), - .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hC30C; -defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N19 -dffeas \ula_|i2c_loader_|thisbyte[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), - .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; -defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N21 -dffeas \ula_|i2c_loader_|thisbyte[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( -// Equation(s): -// \ula_|i2c_loader_|Equal2~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0002; -defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~0_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]))) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Stop~q )))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h5FCC; -defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) - - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), - .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; -defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N23 -dffeas \ula_|i2c_loader_|thisbyte[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~1_combout = (\ula_|i2c_loader_|state.Pause~0_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|Equal2~0_combout ), - .datac(\ula_|i2c_loader_|state.Pause~0_combout ), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h30F0; -defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~2_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Done~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & -// (\ula_|i2c_loader_|state.Data~q & ((!\ula_|i2c_loader_|state.Done~1_combout )))) - - .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Done~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~2 .lut_mask = 16'h0ACE; -defparam \ula_|i2c_loader_|state.Done~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~2_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Done~2_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Done~2_combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'hC4FF; -defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Pause~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~2_combout & (\ula_|i2c_loader_|state.Pause~1_combout )) # -// (!\ula_|i2c_loader_|state.Pause~2_combout & ((\ula_|i2c_loader_|state.Pause~q ))))) - - .dataa(\ula_|i2c_loader_|state.Pause~1_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Pause~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'hE2F0; -defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N23 -dffeas \ula_|i2c_loader_|state.Pause ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Pause~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Pause~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( -// Equation(s): -// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # -// (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Pause~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h38FF; -defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N31 -dffeas \ula_|i2c_loader_|state.Start ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state~25_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Start~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Start .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Start~q )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [0]), - .datad(\ula_|i2c_loader_|state.Start~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h000C; -defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N11 -dffeas \ula_|i2c_loader_|nbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbyte~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & !\ula_|i2c_loader_|state.Data~q )) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0005; -defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h47CF; -defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # ((\ula_|i2c_loader_|nbit[0]~2_combout ) # (\ula_|i2c_loader_|state.Done~0_combout )))) - - .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), - .datab(\ula_|i2c_loader_|nbit[0]~2_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Done~0_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h0F0E; -defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~4 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~4_combout = (!\ula_|i2c_loader_|nbit[0]~3_combout & (\ula_|i2c_loader_|Mux42~0_combout & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q ))) - - .dataa(\ula_|i2c_loader_|nbit[0]~3_combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~4 .lut_mask = 16'h0400; -defparam \ula_|i2c_loader_|nbit[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N3 -dffeas \ula_|i2c_loader_|nbit[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~5_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbit [1]), - .datad(\ula_|i2c_loader_|nbit [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hF55F; -defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N13 -dffeas \ula_|i2c_loader_|nbit[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~6_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~1_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & !\ula_|i2c_loader_|nbit [0])) - - .dataa(\ula_|i2c_loader_|nbit [1]), - .datab(\ula_|i2c_loader_|nbit [2]), - .datac(gnd), - .datad(\ula_|i2c_loader_|nbit [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~1 .lut_mask = 16'h0011; -defparam \ula_|i2c_loader_|state.Done~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( -// Equation(s): -// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Done~1_combout ) # (!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Done~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h5FFF; -defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( -// Equation(s): -// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hE0E0; -defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( -// Equation(s): -// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state~24_combout )) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state~24_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hA000; -defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~27_combout )) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~26_combout ))) - - .dataa(\ula_|i2c_loader_|state~27_combout ), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state~26_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Data~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hAFA0; -defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N29 -dffeas \ula_|i2c_loader_|state.Data ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Data~0_combout ), - .asdata(\ula_|i2c_loader_|Mux42~0_combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2c_loader_|state.Start~q ), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Data~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Data .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( -// Equation(s): -// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Stop~q )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Stop~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|scl_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0003; -defparam \ula_|i2c_loader_|scl_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: FF_X1_Y23_N13 dffeas \ula_|i2c_loader_|scl_out~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), @@ -54958,38 +54438,1113 @@ defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~1 ( +// Location: LCCOMB_X2_Y24_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( // Equation(s): -// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Start~q $ (((!\ula_|i2c_loader_|scl_out~_Duplicate_1_q ))))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # -// ((\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|scl_out~_Duplicate_1_q )))) +// \ula_|i2c_loader_|state.Idle~feeder_combout = VCC - .dataa(\ula_|i2c_loader_|state.Start~q ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Idle~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; +defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N23 +dffeas \ula_|i2c_loader_|state.Idle ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Idle~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Idle~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Idle .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Idle .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|phase~0 ( +// Equation(s): +// \ula_|i2c_loader_|phase~0_combout = (!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|phase~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|phase~0 .lut_mask = 16'h0F00; +defparam \ula_|i2c_loader_|phase~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N9 +dffeas \ula_|i2c_loader_|phase[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|phase~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|phase [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|phase[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|phase[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|phase~1 ( +// Equation(s): +// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [0] $ (\ula_|i2c_loader_|phase [1]))) + + .dataa(gnd), .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|phase~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h3C00; +defparam \ula_|i2c_loader_|phase~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y24_N29 +dffeas \ula_|i2c_loader_|phase[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|phase~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|phase [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|phase[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|phase[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( +// Equation(s): +// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|phase [0]) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|Mux42~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hC0C0; +defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|phase [0])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|phase [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y25_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~4_combout = (!\ula_|i2c_loader_|state.Data~q ) # (!\ula_|i2c_loader_|nbit [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|nbit [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~4 .lut_mask = 16'h0FFF; +defparam \ula_|i2c_loader_|nbit~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [0] $ (!\ula_|i2c_loader_|nbyte [1])))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|phase [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hEDCC; +defparam \ula_|i2c_loader_|nbyte~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y23_N31 +dffeas \ula_|i2c_loader_|nbyte[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbyte~4_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbyte [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbyte[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~1_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'hFC00; +defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Start~q ) # ((!\ula_|i2c_loader_|state.Pause~0_combout & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # (\ula_|i2c_loader_|state.Data~q )))) + + .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Pause~0_combout ), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'hCFCE; +defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~3_combout = (\ula_|i2c_loader_|Mux42~0_combout & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|nbit[0]~2_combout ))) + + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|nbit[0]~2_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h2000; +defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y25_N27 +dffeas \ula_|i2c_loader_|nbit[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~4_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y25_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~5_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(gnd), + .datac(\ula_|i2c_loader_|nbit [1]), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'hF55F; +defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y25_N1 +dffeas \ula_|i2c_loader_|nbit[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~5_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y25_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~1_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [1] & !\ula_|i2c_loader_|nbit [0])) + + .dataa(\ula_|i2c_loader_|nbit [2]), + .datab(\ula_|i2c_loader_|nbit [1]), + .datac(gnd), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h0011; +defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( +// Equation(s): +// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Pause~1_combout ) # (!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Pause~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h3FFF; +defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( +// Equation(s): +// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hFC00; +defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( +// Equation(s): +// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state~24_combout )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state~24_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hC000; +defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~27_combout )) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~26_combout ))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state~27_combout ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|state~26_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Data~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hCFC0; +defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N5 +dffeas \ula_|i2c_loader_|state.Data ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Data~0_combout ), + .asdata(\ula_|i2c_loader_|Mux42~0_combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2c_loader_|state.Start~q ), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Data~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Data .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y25_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [1] & !\ula_|i2c_loader_|nbit [0])))) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|nbit [1]), + .datac(\ula_|i2c_loader_|nbit [2]), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; +defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y25_N13 +dffeas \ula_|i2c_loader_|nbit[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y25_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~0_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [0] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [1]))) + + .dataa(\ula_|i2c_loader_|nbit [2]), + .datab(\ula_|i2c_loader_|nbit [0]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|nbit [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h0010; +defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Pause~q ))) + + .dataa(\ula_|i2c_loader_|state.Stop~q ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Pause~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Idle~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; +defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Pause~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|state.Pause~0_combout ), + .datad(\ula_|i2c_loader_|state.Idle~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hB3BB; +defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|state.Data~q ))) # +// (!\ula_|i2c_loader_|state.Ack~0_combout & (\ula_|i2c_loader_|state.Ack~q )))) + + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|state.Ack~0_combout ), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF4B0; +defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N25 +dffeas \ula_|i2c_loader_|state.Ack ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Ack~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Ack~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state.Ack~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hF000; +defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y23_N1 +cycloneive_io_ibuf \I2C_SDAT~input ( + .i(I2C_SDAT), + .ibar(gnd), + .o(\I2C_SDAT~input_o )); +// synopsys translate_off +defparam \I2C_SDAT~input .bus_hold = "false"; +defparam \I2C_SDAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hFBC8; +defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|Mux42~0_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|thisbyte[0]~7_combout & ((\ula_|i2c_loader_|nbyte[0]~1_combout )))) + + .dataa(\ula_|i2c_loader_|thisbyte[0]~7_combout ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hCAC0; +defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~3_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[0]~2_combout )) + + .dataa(\ula_|i2c_loader_|state.Idle~q ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(gnd), + .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h2200; +defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y23_N21 +dffeas \ula_|i2c_loader_|nbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|i2c_loader_|nbyte~0_combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Stop~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Stop~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))))) # +// (!\ula_|i2c_loader_|Mux42~0_combout & (((\ula_|i2c_loader_|state.Stop~q )))) + + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Stop~q ), + .datad(\ula_|i2c_loader_|state.Stop~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Stop~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF2D0; +defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N7 +dffeas \ula_|i2c_loader_|state.Stop ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Stop~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Stop~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0]) # (!\ula_|i2c_loader_|phase [1])))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state.Stop~q )) + + .dataa(\ula_|i2c_loader_|state.Stop~q ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|phase [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'h2EEE; +defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) +// \ula_|i2c_loader_|thisbyte[0]~9 = CARRY(\ula_|i2c_loader_|thisbyte [0]) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~8_combout ), + .cout(\ula_|i2c_loader_|thisbyte[0]~9 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; +defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hFBC8; +defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~18_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q & (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|nbyte[1]~5_combout ))) + + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h4000; +defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y23_N19 +dffeas \ula_|i2c_loader_|thisbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), + .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y23_N21 +dffeas \ula_|i2c_loader_|thisbyte[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) +// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) + + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), + .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hA50A; +defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y23_N23 +dffeas \ula_|i2c_loader_|thisbyte[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), + .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y23_N25 +dffeas \ula_|i2c_loader_|thisbyte[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( +// Equation(s): +// \ula_|i2c_loader_|Equal2~0_combout = (!\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte [3]))) + + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0010; +defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) + + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), + .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; +defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y23_N27 +dffeas \ula_|i2c_loader_|thisbyte[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|state.Pause~2_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Pause~2_combout ), + .datac(\ula_|i2c_loader_|Equal2~0_combout ), + .datad(\ula_|i2c_loader_|thisbyte [4]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'h0CCC; +defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( +// Equation(s): +// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Data~q )) + + .dataa(\ula_|i2c_loader_|state.Stop~q ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|scl_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0011; +defparam \ula_|i2c_loader_|scl_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~4 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~4_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Pause~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & +// (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Pause~1_combout )))) + + .dataa(\ula_|i2c_loader_|scl_out~0_combout ), + .datab(\ula_|i2c_loader_|state.Pause~q ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|state.Pause~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~4 .lut_mask = 16'h22F2; +defparam \ula_|i2c_loader_|state.Pause~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~5 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~5_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Pause~4_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Pause~4_combout ), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|Mux42~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~5 .lut_mask = 16'hF733; +defparam \ula_|i2c_loader_|state.Pause~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~6 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~6_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Pause~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~5_combout & (\ula_|i2c_loader_|state.Pause~3_combout )) # +// (!\ula_|i2c_loader_|state.Pause~5_combout & ((\ula_|i2c_loader_|state.Pause~q ))))) + + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|state.Pause~3_combout ), + .datac(\ula_|i2c_loader_|state.Pause~q ), + .datad(\ula_|i2c_loader_|state.Pause~5_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~6 .lut_mask = 16'hE4F0; +defparam \ula_|i2c_loader_|state.Pause~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N21 +dffeas \ula_|i2c_loader_|state.Pause ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Pause~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Pause~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( +// Equation(s): +// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # +// (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|state.Pause~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h58FF; +defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N31 +dffeas \ula_|i2c_loader_|state.Start ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state~25_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Start~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Start .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~1 ( +// Equation(s): +// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|scl_out~_Duplicate_1_q $ (((!\ula_|i2c_loader_|state.Start~q ))))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # +// ((\ula_|i2c_loader_|scl_out~_Duplicate_1_q & \ula_|i2c_loader_|state.Start~q )))) + + .dataa(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|phase [0]), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hBA74; +defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hA5EC; defparam \ula_|i2c_loader_|scl_out~1 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X1_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~2 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|scl_out~1_combout & ((\ula_|i2c_loader_|state.Start~q ))) # (!\ula_|i2c_loader_|scl_out~1_combout & (!\ula_|i2c_loader_|scl_out~0_combout & !\ula_|i2c_loader_|state.Start~q )) +// \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|scl_out~1_combout & (\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|scl_out~1_combout & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|scl_out~0_combout )) - .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(\ula_|i2c_loader_|scl_out~1_combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|state.Start~q ), + .dataa(\ula_|i2c_loader_|scl_out~1_combout ), + .datab(gnd), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|scl_out~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hCC11; +defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hA0A5; defparam \ula_|i2c_loader_|scl_out~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -55031,15 +55586,32 @@ defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N10 +// Location: LCCOMB_X3_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( +// Equation(s): +// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [3]) # (!\ula_|i2c_loader_|thisbyte [1])))) + + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Mux35~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h20A0; +defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~4 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Start~q ) +// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Data~q ) .dataa(gnd), .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~4_combout ), .cout()); @@ -55048,146 +55620,146 @@ defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h000F; defparam \ula_|i2c_loader_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( +// Location: LCCOMB_X3_Y23_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( // Equation(s): -// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [1]) # (!\ula_|i2c_loader_|thisbyte [3])))) +// \ula_|i2c_loader_|shiftreg~19_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1])) # (!\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [3]))))) .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [1]), - .datad(\ula_|i2c_loader_|thisbyte [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Mux35~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h2A00; -defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) - - .dataa(\ula_|i2c_loader_|thisbyte [4]), .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h001A; -defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~14_combout = (\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2]) - - .dataa(gnd), - .datab(gnd), .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [3]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~14_combout ), + .combout(\ula_|i2c_loader_|shiftreg~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h00F0; -defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h202A; +defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( +// Location: LCCOMB_X3_Y23_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|shiftreg~13_combout ) # ((!\ula_|i2c_loader_|thisbyte [3] & (\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|shiftreg~14_combout ))) +// \ula_|i2c_loader_|shiftreg~20_combout = ((\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|shiftreg~19_combout ))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) - .dataa(\ula_|i2c_loader_|shiftreg~13_combout ), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|shiftreg~14_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'hAABA; -defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~24 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~24_combout = (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|thisbyte [0])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|shiftreg~4_combout ), + .datac(\ula_|i2c_loader_|shiftreg~19_combout ), .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~24_combout ), + .combout(\ula_|i2c_loader_|shiftreg~20_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~24 .lut_mask = 16'h0300; -defparam \ula_|i2c_loader_|shiftreg[0]~24 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'h73FB; +defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N14 +// Location: LCCOMB_X3_Y23_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [3]))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [3])))) + + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [0]), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h8804; +defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~23 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~23_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~22_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) + + .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|shiftreg~22_combout ), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hA0A8; +defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~25 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[0]~25_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|thisbyte [3] & \ula_|i2c_loader_|thisbyte [0])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|thisbyte [3]), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg[0]~25 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|shiftreg[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N12 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~6 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~6_combout = (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|shiftreg[0]~6_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|phase [0] & !\ula_|i2c_loader_|phase [1])) - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|phase [1]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h5000; +defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h00C0; defparam \ula_|i2c_loader_|shiftreg[0]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N0 +// Location: LCCOMB_X2_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~7 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|state~24_combout )))) +// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state~24_combout ) # (\ula_|i2c_loader_|state.Start~q )))) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|shiftreg[0]~6_combout ), - .datad(\ula_|i2c_loader_|state~24_combout ), + .dataa(\ula_|i2c_loader_|shiftreg[0]~6_combout ), + .datab(\ula_|i2c_loader_|state~24_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|Mux42~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFCF8; +defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFEAA; defparam \ula_|i2c_loader_|shiftreg[0]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N10 +// Location: LCCOMB_X2_Y24_N0 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~8 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~8_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|shiftreg[0]~7_combout )) +// \ula_|i2c_loader_|shiftreg[0]~8_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|shiftreg[0]~7_combout & \ula_|i2c_loader_|state.Idle~q )) - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Idle~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|shiftreg[0]~7_combout ), + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|shiftreg[0]~7_combout ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Idle~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h0C00; +defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h4400; defparam \ula_|i2c_loader_|shiftreg[0]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N13 +// Location: FF_X3_Y24_N21 dffeas \ula_|i2c_loader_|shiftreg[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg[0]~24_combout ), + .d(\ula_|i2c_loader_|shiftreg[0]~25_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -55203,102 +55775,85 @@ defparam \ula_|i2c_loader_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( +// Location: LCCOMB_X3_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~24 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte [2]))) # (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2])))) +// \ula_|i2c_loader_|shiftreg~24_combout = (\ula_|i2c_loader_|shiftreg~23_combout ) # ((\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [0])) - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~21_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hC010; -defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~21_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) - - .dataa(\ula_|i2c_loader_|shiftreg~21_combout ), - .datab(\ula_|i2c_loader_|shiftreg~4_combout ), - .datac(\ula_|i2c_loader_|thisbyte [1]), - .datad(\ula_|i2c_loader_|thisbyte [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h88C8; -defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~23 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~23_combout = (\ula_|i2c_loader_|shiftreg~22_combout ) # ((\ula_|i2c_loader_|shiftreg [0] & \ula_|i2c_loader_|state.Data~q )) - - .dataa(\ula_|i2c_loader_|shiftreg [0]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|shiftreg~23_combout ), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~22_combout ), + .datad(\ula_|i2c_loader_|shiftreg [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~23_combout ), + .combout(\ula_|i2c_loader_|shiftreg~24_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hFFA0; -defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~24 .lut_mask = 16'hFCCC; +defparam \ula_|i2c_loader_|shiftreg~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N10 +// Location: LCCOMB_X2_Y24_N6 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~10 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state.Start~q ) # ((!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|state~24_combout )))) # (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Data~q -// & (!\ula_|i2c_loader_|state.Start~q ))) +// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|phase [1]) # (!\ula_|i2c_loader_|phase [0])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state~24_combout )) - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state~24_combout ), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|state~24_combout ), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|phase [1]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hA6A4; +defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hBB1B; defparam \ula_|i2c_loader_|shiftreg[6]~10 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X2_Y24_N24 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~11 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|shiftreg[6]~10_combout ))) +// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg[6]~10_combout ) # ((!\ula_|i2c_loader_|Mux42~0_combout & +// !\ula_|i2c_loader_|state.Data~q )))) - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), .datad(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~11 .lut_mask = 16'h2000; +defparam \ula_|i2c_loader_|shiftreg[6]~11 .lut_mask = 16'h5F51; defparam \ula_|i2c_loader_|shiftreg[6]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N23 +// Location: LCCOMB_X2_Y24_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~12 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[6]~12_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (!\ula_|i2c_loader_|shiftreg[6]~11_combout & \ula_|i2c_loader_|state.Idle~q )) + + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg[6]~12 .lut_mask = 16'h1100; +defparam \ula_|i2c_loader_|shiftreg[6]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N13 dffeas \ula_|i2c_loader_|shiftreg[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~23_combout ), + .d(\ula_|i2c_loader_|shiftreg~24_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [1]), @@ -55308,67 +55863,33 @@ defparam \ula_|i2c_loader_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( +// Location: LCCOMB_X3_Y24_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [1]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [3])))) +// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|shiftreg~20_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h10B0; -defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~19_combout = ((\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [0])) # (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|shiftreg~18_combout )))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(\ula_|i2c_loader_|shiftreg~18_combout ), - .datad(\ula_|i2c_loader_|shiftreg~4_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h74FF; -defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~20_combout = (\ula_|i2c_loader_|shiftreg~19_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) - - .dataa(\ula_|i2c_loader_|shiftreg [1]), + .dataa(\ula_|i2c_loader_|shiftreg~20_combout ), .datab(gnd), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~19_combout ), + .datad(\ula_|i2c_loader_|shiftreg [1]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~20_combout ), + .combout(\ula_|i2c_loader_|shiftreg~21_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'hAF00; -defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hAA0A; +defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N3 +// Location: FF_X3_Y24_N11 dffeas \ula_|i2c_loader_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~20_combout ), + .d(\ula_|i2c_loader_|shiftreg~21_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [2]), @@ -55378,67 +55899,84 @@ defparam \ula_|i2c_loader_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( +// Location: LCCOMB_X3_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) +// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) .dataa(\ula_|i2c_loader_|thisbyte [2]), .datab(\ula_|i2c_loader_|thisbyte [1]), .datac(\ula_|i2c_loader_|thisbyte [4]), .datad(\ula_|i2c_loader_|thisbyte [3]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'h10BA; -defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~16_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [3] & ((!\ula_|i2c_loader_|shiftreg~14_combout )))) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|shiftreg~16_combout ), - .datad(\ula_|i2c_loader_|shiftreg~14_combout ), - .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'hA0E4; +defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'h10BA; defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( +// Location: LCCOMB_X3_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [2])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg~17_combout )))) +// \ula_|i2c_loader_|shiftreg~15_combout = (!\ula_|i2c_loader_|thisbyte [2] & \ula_|i2c_loader_|thisbyte [4]) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|shiftreg [2]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~17_combout ), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(gnd), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(gnd), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~26_combout ), + .combout(\ula_|i2c_loader_|shiftreg~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hC5C0; -defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'h5050; +defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N7 +// Location: LCCOMB_X3_Y24_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|shiftreg~17_combout )) # (!\ula_|i2c_loader_|thisbyte [0] & (((!\ula_|i2c_loader_|shiftreg~15_combout & \ula_|i2c_loader_|thisbyte [3])))) + + .dataa(\ula_|i2c_loader_|shiftreg~17_combout ), + .datab(\ula_|i2c_loader_|shiftreg~15_combout ), + .datac(\ula_|i2c_loader_|thisbyte [3]), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'hAA30; +defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~27 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~27_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [2])) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|shiftreg~18_combout )))) + + .dataa(\ula_|i2c_loader_|shiftreg [2]), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg~18_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~27 .lut_mask = 16'hA3A0; +defparam \ula_|i2c_loader_|shiftreg~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N23 dffeas \ula_|i2c_loader_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~26_combout ), + .d(\ula_|i2c_loader_|shiftreg~27_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [3]), @@ -55448,33 +55986,67 @@ defparam \ula_|i2c_loader_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~25 ( +// Location: LCCOMB_X3_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg~15_combout ) # ((\ula_|i2c_loader_|state.Start~q )))) +// \ula_|i2c_loader_|shiftreg~14_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) - .dataa(\ula_|i2c_loader_|shiftreg~15_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|shiftreg [3]), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~25_combout ), + .combout(\ula_|i2c_loader_|shiftreg~14_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hFE32; -defparam \ula_|i2c_loader_|shiftreg~25 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h0150; +defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N1 +// Location: LCCOMB_X3_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|shiftreg~14_combout ) # ((\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [3] & !\ula_|i2c_loader_|shiftreg~15_combout ))) + + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|shiftreg~14_combout ), + .datac(\ula_|i2c_loader_|thisbyte [3]), + .datad(\ula_|i2c_loader_|shiftreg~15_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'hCCCE; +defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [3])) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|shiftreg~16_combout )))) + + .dataa(\ula_|i2c_loader_|shiftreg [3]), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg~16_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hAFAC; +defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N15 dffeas \ula_|i2c_loader_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~25_combout ), + .d(\ula_|i2c_loader_|shiftreg~26_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [4]), @@ -55484,33 +56056,33 @@ defparam \ula_|i2c_loader_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~12 ( +// Location: LCCOMB_X4_Y24_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~12_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) +// \ula_|i2c_loader_|shiftreg~13_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) .dataa(\ula_|i2c_loader_|Mux35~0_combout ), .datab(\ula_|i2c_loader_|state.Data~q ), .datac(gnd), .datad(\ula_|i2c_loader_|shiftreg [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~12_combout ), + .combout(\ula_|i2c_loader_|shiftreg~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~12 .lut_mask = 16'hEE22; -defparam \ula_|i2c_loader_|shiftreg~12 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'hEE22; +defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N5 +// Location: FF_X4_Y24_N5 dffeas \ula_|i2c_loader_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~12_combout ), + .d(\ula_|i2c_loader_|shiftreg~13_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(\ula_|i2c_loader_|state.Start~q ), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [5]), @@ -55520,24 +56092,24 @@ defparam \ula_|i2c_loader_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N18 +// Location: LCCOMB_X3_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~9 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~9_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [5])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) +// \ula_|i2c_loader_|shiftreg~9_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [5]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) .dataa(gnd), - .datab(\ula_|i2c_loader_|shiftreg [5]), + .datab(\ula_|i2c_loader_|Mux35~0_combout ), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|Mux35~0_combout ), + .datad(\ula_|i2c_loader_|shiftreg [5]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hCFC0; +defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hFC0C; defparam \ula_|i2c_loader_|shiftreg~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N19 +// Location: FF_X3_Y24_N3 dffeas \ula_|i2c_loader_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~9_combout ), @@ -55546,7 +56118,7 @@ dffeas \ula_|i2c_loader_|shiftreg[6] ( .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [6]), @@ -55556,7 +56128,7 @@ defparam \ula_|i2c_loader_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N4 +// Location: LCCOMB_X3_Y24_N28 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[7]~5 ( // Equation(s): // \ula_|i2c_loader_|shiftreg[7]~5_combout = (\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [6]) @@ -55573,7 +56145,7 @@ defparam \ula_|i2c_loader_|shiftreg[7]~5 .lut_mask = 16'hF000; defparam \ula_|i2c_loader_|shiftreg[7]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N5 +// Location: FF_X3_Y24_N29 dffeas \ula_|i2c_loader_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg[7]~5_combout ), @@ -55592,42 +56164,42 @@ defparam \ula_|i2c_loader_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N12 +// Location: LCCOMB_X2_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~0 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|shiftreg [7]))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|state.Data~q & +// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|shiftreg [7])) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|state.Ack~q ))))) # (!\ula_|i2c_loader_|state.Data~q & // (((\ula_|i2c_loader_|state.Ack~q )))) - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|phase [0]), + .dataa(\ula_|i2c_loader_|shiftreg [7]), + .datab(\ula_|i2c_loader_|state.Data~q ), .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|shiftreg [7]), + .datad(\ula_|i2c_loader_|phase [0]), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hF870; +defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hB8F0; defparam \ula_|i2c_loader_|sda_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N6 +// Location: LCCOMB_X1_Y23_N18 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~1 ( // Equation(s): // \ula_|i2c_loader_|sda_out~1_combout = (\ula_|i2c_loader_|sda_out~0_combout & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|shiftreg~4_combout & !\I2C_SDAT~input_o )))) - .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), + .dataa(\ula_|i2c_loader_|sda_out~0_combout ), .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|sda_out~0_combout ), + .datac(\ula_|i2c_loader_|shiftreg~4_combout ), .datad(\I2C_SDAT~input_o ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'hC0E0; +defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'h88A8; defparam \ula_|i2c_loader_|sda_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N8 +// Location: LCCOMB_X1_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~2 ( // Equation(s): // \ula_|i2c_loader_|sda_out~2_combout = (!\ula_|i2c_loader_|sda_out~_Duplicate_1_q & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|phase [1] & !\ula_|i2c_loader_|sda_out~1_combout )))) @@ -55644,7 +56216,7 @@ defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h4454; defparam \ula_|i2c_loader_|sda_out~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N2 +// Location: LCCOMB_X1_Y23_N6 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~3 ( // Equation(s): // \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )) # (!\ula_|i2c_loader_|phase [1] & ((!\ula_|i2c_loader_|sda_out~1_combout ))))) # (!\ula_|i2c_loader_|phase @@ -55698,7 +56270,2727 @@ defparam \ula_|i2c_loader_|sda_out .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out .power_up = "high"; // synopsys translate_on -// Location: LCCOMB_X27_Y23_N16 +// Location: PLL_1 +cycloneive_pll \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 ( + .areset(gnd), + .pfdena(vcc), + .fbin(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\CLOCK_50~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(), + .vcooverrange(), + .vcounderrange(), + .fbout(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c0_high = 3; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c0_initial = 2; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c0_low = 2; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c0_mode = "odd"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c0_ph = 4; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_high = 3; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_initial = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_low = 2; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_mode = "odd"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk0_counter = "c1"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk0_divide_by = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk0_multiply_by = 2; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk1_counter = "c0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk1_divide_by = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk1_multiply_by = 2; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk1_phase_shift = "3000"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .m = 10; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .n = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .pll_compensation_delay = 4936; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 250; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N14 +cycloneive_lcell_comb \sdram_|Mux38~0 ( +// Equation(s): +// \sdram_|Mux38~0_combout = (\sdram_|r.rd_pending~q & (((\sdram_|Mux39~1_combout )))) # (!\sdram_|r.rd_pending~q & (\z80_|control_pins_|pin_nIORQ~1_combout & (\Equal2~1_combout ))) + + .dataa(\z80_|control_pins_|pin_nIORQ~1_combout ), + .datab(\Equal2~1_combout ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Mux39~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux38~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux38~0 .lut_mask = 16'hF808; +defparam \sdram_|Mux38~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y12_N15 +dffeas \sdram_|r.rd_pending ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux38~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rd_pending~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rd_pending .is_wysiwyg = "true"; +defparam \sdram_|r.rd_pending .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N0 +cycloneive_lcell_comb \sdram_|r.rf_counter[0]~12 ( +// Equation(s): +// \sdram_|r.rf_counter[0]~12_combout = \sdram_|r.rf_counter [0] $ (VCC) +// \sdram_|r.rf_counter[0]~13 = CARRY(\sdram_|r.rf_counter [0]) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_|r.rf_counter[0]~12_combout ), + .cout(\sdram_|r.rf_counter[0]~13 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[0]~12 .lut_mask = 16'h33CC; +defparam \sdram_|r.rf_counter[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N26 +cycloneive_lcell_comb \sdram_|r.rf_counter[3]~32 ( +// Equation(s): +// \sdram_|r.rf_counter[3]~32_combout = ((!\sdram_|r.state [5] & (\sdram_|r.address[3]~6_combout & !\sdram_|r.state [4]))) # (!\sdram_|Equal0~2_combout ) + + .dataa(\sdram_|Equal0~2_combout ), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.address[3]~6_combout ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|r.rf_counter[3]~32_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.rf_counter[3]~32 .lut_mask = 16'h5575; +defparam \sdram_|r.rf_counter[3]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y13_N1 +dffeas \sdram_|r.rf_counter[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[0]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[0] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N2 +cycloneive_lcell_comb \sdram_|r.rf_counter[1]~14 ( +// Equation(s): +// \sdram_|r.rf_counter[1]~14_combout = (\sdram_|r.rf_counter [1] & (!\sdram_|r.rf_counter[0]~13 )) # (!\sdram_|r.rf_counter [1] & ((\sdram_|r.rf_counter[0]~13 ) # (GND))) +// \sdram_|r.rf_counter[1]~15 = CARRY((!\sdram_|r.rf_counter[0]~13 ) # (!\sdram_|r.rf_counter [1])) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[0]~13 ), + .combout(\sdram_|r.rf_counter[1]~14_combout ), + .cout(\sdram_|r.rf_counter[1]~15 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[1]~14 .lut_mask = 16'h3C3F; +defparam \sdram_|r.rf_counter[1]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N3 +dffeas \sdram_|r.rf_counter[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[1]~14_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[1] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N4 +cycloneive_lcell_comb \sdram_|r.rf_counter[2]~16 ( +// Equation(s): +// \sdram_|r.rf_counter[2]~16_combout = (\sdram_|r.rf_counter [2] & (\sdram_|r.rf_counter[1]~15 $ (GND))) # (!\sdram_|r.rf_counter [2] & (!\sdram_|r.rf_counter[1]~15 & VCC)) +// \sdram_|r.rf_counter[2]~17 = CARRY((\sdram_|r.rf_counter [2] & !\sdram_|r.rf_counter[1]~15 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[1]~15 ), + .combout(\sdram_|r.rf_counter[2]~16_combout ), + .cout(\sdram_|r.rf_counter[2]~17 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[2]~16 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[2]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N5 +dffeas \sdram_|r.rf_counter[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[2]~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[2] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N6 +cycloneive_lcell_comb \sdram_|r.rf_counter[3]~18 ( +// Equation(s): +// \sdram_|r.rf_counter[3]~18_combout = (\sdram_|r.rf_counter [3] & (!\sdram_|r.rf_counter[2]~17 )) # (!\sdram_|r.rf_counter [3] & ((\sdram_|r.rf_counter[2]~17 ) # (GND))) +// \sdram_|r.rf_counter[3]~19 = CARRY((!\sdram_|r.rf_counter[2]~17 ) # (!\sdram_|r.rf_counter [3])) + + .dataa(\sdram_|r.rf_counter [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[2]~17 ), + .combout(\sdram_|r.rf_counter[3]~18_combout ), + .cout(\sdram_|r.rf_counter[3]~19 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[3]~18 .lut_mask = 16'h5A5F; +defparam \sdram_|r.rf_counter[3]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N7 +dffeas \sdram_|r.rf_counter[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[3]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[3] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N8 +cycloneive_lcell_comb \sdram_|r.rf_counter[4]~20 ( +// Equation(s): +// \sdram_|r.rf_counter[4]~20_combout = (\sdram_|r.rf_counter [4] & (\sdram_|r.rf_counter[3]~19 $ (GND))) # (!\sdram_|r.rf_counter [4] & (!\sdram_|r.rf_counter[3]~19 & VCC)) +// \sdram_|r.rf_counter[4]~21 = CARRY((\sdram_|r.rf_counter [4] & !\sdram_|r.rf_counter[3]~19 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[3]~19 ), + .combout(\sdram_|r.rf_counter[4]~20_combout ), + .cout(\sdram_|r.rf_counter[4]~21 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[4]~20 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[4]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N9 +dffeas \sdram_|r.rf_counter[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[4]~20_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[4] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N10 +cycloneive_lcell_comb \sdram_|r.rf_counter[5]~22 ( +// Equation(s): +// \sdram_|r.rf_counter[5]~22_combout = (\sdram_|r.rf_counter [5] & (!\sdram_|r.rf_counter[4]~21 )) # (!\sdram_|r.rf_counter [5] & ((\sdram_|r.rf_counter[4]~21 ) # (GND))) +// \sdram_|r.rf_counter[5]~23 = CARRY((!\sdram_|r.rf_counter[4]~21 ) # (!\sdram_|r.rf_counter [5])) + + .dataa(\sdram_|r.rf_counter [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[4]~21 ), + .combout(\sdram_|r.rf_counter[5]~22_combout ), + .cout(\sdram_|r.rf_counter[5]~23 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[5]~22 .lut_mask = 16'h5A5F; +defparam \sdram_|r.rf_counter[5]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N11 +dffeas \sdram_|r.rf_counter[5] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[5]~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[5] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N12 +cycloneive_lcell_comb \sdram_|r.rf_counter[6]~24 ( +// Equation(s): +// \sdram_|r.rf_counter[6]~24_combout = (\sdram_|r.rf_counter [6] & (\sdram_|r.rf_counter[5]~23 $ (GND))) # (!\sdram_|r.rf_counter [6] & (!\sdram_|r.rf_counter[5]~23 & VCC)) +// \sdram_|r.rf_counter[6]~25 = CARRY((\sdram_|r.rf_counter [6] & !\sdram_|r.rf_counter[5]~23 )) + + .dataa(\sdram_|r.rf_counter [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[5]~23 ), + .combout(\sdram_|r.rf_counter[6]~24_combout ), + .cout(\sdram_|r.rf_counter[6]~25 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[6]~24 .lut_mask = 16'hA50A; +defparam \sdram_|r.rf_counter[6]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N13 +dffeas \sdram_|r.rf_counter[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[6]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[6] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N14 +cycloneive_lcell_comb \sdram_|r.rf_counter[7]~26 ( +// Equation(s): +// \sdram_|r.rf_counter[7]~26_combout = (\sdram_|r.rf_counter [7] & (!\sdram_|r.rf_counter[6]~25 )) # (!\sdram_|r.rf_counter [7] & ((\sdram_|r.rf_counter[6]~25 ) # (GND))) +// \sdram_|r.rf_counter[7]~27 = CARRY((!\sdram_|r.rf_counter[6]~25 ) # (!\sdram_|r.rf_counter [7])) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[6]~25 ), + .combout(\sdram_|r.rf_counter[7]~26_combout ), + .cout(\sdram_|r.rf_counter[7]~27 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[7]~26 .lut_mask = 16'h3C3F; +defparam \sdram_|r.rf_counter[7]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N15 +dffeas \sdram_|r.rf_counter[7] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[7]~26_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[7] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N24 +cycloneive_lcell_comb \sdram_|Equal0~1 ( +// Equation(s): +// \sdram_|Equal0~1_combout = (\sdram_|r.rf_counter [5]) # ((\sdram_|r.rf_counter [7]) # ((\sdram_|r.rf_counter [4]) # (\sdram_|r.rf_counter [6]))) + + .dataa(\sdram_|r.rf_counter [5]), + .datab(\sdram_|r.rf_counter [7]), + .datac(\sdram_|r.rf_counter [4]), + .datad(\sdram_|r.rf_counter [6]), + .cin(gnd), + .combout(\sdram_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~1 .lut_mask = 16'hFFFE; +defparam \sdram_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N16 +cycloneive_lcell_comb \sdram_|r.rf_counter[8]~28 ( +// Equation(s): +// \sdram_|r.rf_counter[8]~28_combout = (\sdram_|r.rf_counter [8] & (\sdram_|r.rf_counter[7]~27 $ (GND))) # (!\sdram_|r.rf_counter [8] & (!\sdram_|r.rf_counter[7]~27 & VCC)) +// \sdram_|r.rf_counter[8]~29 = CARRY((\sdram_|r.rf_counter [8] & !\sdram_|r.rf_counter[7]~27 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[7]~27 ), + .combout(\sdram_|r.rf_counter[8]~28_combout ), + .cout(\sdram_|r.rf_counter[8]~29 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[8]~28 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[8]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N17 +dffeas \sdram_|r.rf_counter[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[8]~28_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[8] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N30 +cycloneive_lcell_comb \sdram_|Equal0~0 ( +// Equation(s): +// \sdram_|Equal0~0_combout = (\sdram_|r.rf_counter [3]) # ((\sdram_|r.rf_counter [0]) # ((\sdram_|r.rf_counter [2]) # (!\sdram_|r.rf_counter [1]))) + + .dataa(\sdram_|r.rf_counter [3]), + .datab(\sdram_|r.rf_counter [0]), + .datac(\sdram_|r.rf_counter [2]), + .datad(\sdram_|r.rf_counter [1]), + .cin(gnd), + .combout(\sdram_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~0 .lut_mask = 16'hFEFF; +defparam \sdram_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N18 +cycloneive_lcell_comb \sdram_|r.rf_counter[9]~30 ( +// Equation(s): +// \sdram_|r.rf_counter[9]~30_combout = \sdram_|r.rf_counter[8]~29 $ (\sdram_|r.rf_counter [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_|r.rf_counter [9]), + .cin(\sdram_|r.rf_counter[8]~29 ), + .combout(\sdram_|r.rf_counter[9]~30_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.rf_counter[9]~30 .lut_mask = 16'h0FF0; +defparam \sdram_|r.rf_counter[9]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N19 +dffeas \sdram_|r.rf_counter[9] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[9]~30_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[9] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N22 +cycloneive_lcell_comb \sdram_|Equal0~2 ( +// Equation(s): +// \sdram_|Equal0~2_combout = (\sdram_|Equal0~1_combout ) # (((\sdram_|Equal0~0_combout ) # (!\sdram_|r.rf_counter [9])) # (!\sdram_|r.rf_counter [8])) + + .dataa(\sdram_|Equal0~1_combout ), + .datab(\sdram_|r.rf_counter [8]), + .datac(\sdram_|Equal0~0_combout ), + .datad(\sdram_|r.rf_counter [9]), + .cin(gnd), + .combout(\sdram_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~2 .lut_mask = 16'hFBFF; +defparam \sdram_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N28 +cycloneive_lcell_comb \sdram_|Mux13~8 ( +// Equation(s): +// \sdram_|Mux13~8_combout = (\sdram_|r.state [4] & !\sdram_|r.state [5]) + + .dataa(gnd), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [5]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|Mux13~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~8 .lut_mask = 16'h0C0C; +defparam \sdram_|Mux13~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N20 +cycloneive_lcell_comb \sdram_|Mux37~0 ( +// Equation(s): +// \sdram_|Mux37~0_combout = (\sdram_|r.rf_pending~q & (((!\sdram_|Mux13~8_combout ) # (!\sdram_|r.address[3]~6_combout )))) # (!\sdram_|r.rf_pending~q & (!\sdram_|Equal0~2_combout )) + + .dataa(\sdram_|Equal0~2_combout ), + .datab(\sdram_|r.address[3]~6_combout ), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Mux13~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux37~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux37~0 .lut_mask = 16'h35F5; +defparam \sdram_|Mux37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y13_N21 +dffeas \sdram_|r.rf_pending ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux37~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_pending~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_pending .is_wysiwyg = "true"; +defparam \sdram_|r.rf_pending .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N14 +cycloneive_lcell_comb \sdram_|Mux4~0 ( +// Equation(s): +// \sdram_|Mux4~0_combout = (!\sdram_|r.wr_pending~q & (\sdram_|r.rd_pending~q & (!\sdram_|r.rf_pending~q & \sdram_|Equal7~2_combout ))) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~0 .lut_mask = 16'h0400; +defparam \sdram_|Mux4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N0 +cycloneive_lcell_comb \sdram_|Mux4~1 ( +// Equation(s): +// \sdram_|Mux4~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [5] $ ((!\sdram_|r.state [4])))) # (!\sdram_|r.state [6] & (\sdram_|r.state [5] & ((!\sdram_|Mux4~0_combout ) # (!\sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|Mux4~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~1 .lut_mask = 16'h86C6; +defparam \sdram_|Mux4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N2 +cycloneive_lcell_comb \sdram_|Mux4~2 ( +// Equation(s): +// \sdram_|Mux4~2_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [5]) # ((\sdram_|r.state [4])))) # (!\sdram_|r.state [6] & ((\sdram_|Mux4~0_combout ) # ((!\sdram_|r.state [5] & \sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|Mux4~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~2 .lut_mask = 16'hFDB8; +defparam \sdram_|Mux4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N30 +cycloneive_lcell_comb \sdram_|Mux4~3 ( +// Equation(s): +// \sdram_|Mux4~3_combout = (\sdram_|Mux4~2_combout & (\sdram_|r.state [8] $ (((\sdram_|Mux4~1_combout & \sdram_|r.state [7]))))) # (!\sdram_|Mux4~2_combout & (\sdram_|r.state [8] & (\sdram_|Mux4~1_combout $ (\sdram_|r.state [7])))) + + .dataa(\sdram_|Mux4~1_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux4~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~3 .lut_mask = 16'h7860; +defparam \sdram_|Mux4~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y15_N31 +dffeas \sdram_|r.state[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux4~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[8] .is_wysiwyg = "true"; +defparam \sdram_|r.state[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N6 +cycloneive_lcell_comb \sdram_|r.act_row[1]~0 ( +// Equation(s): +// \sdram_|r.act_row[1]~0_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [6] & (\sdram_|r.state [5] & \sdram_|r.state [8])) # (!\sdram_|r.state [6] & (!\sdram_|r.state [5] & !\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.act_row[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.act_row[1]~0 .lut_mask = 16'h8004; +defparam \sdram_|r.act_row[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N18 +cycloneive_lcell_comb \sdram_|process_0~2 ( +// Equation(s): +// \sdram_|process_0~2_combout = (\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|process_0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~2 .lut_mask = 16'hFFF0; +defparam \sdram_|process_0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N0 +cycloneive_lcell_comb \sdram_|r.act_row[1]~1 ( +// Equation(s): +// \sdram_|r.act_row[1]~1_combout = (\sdram_|r.act_row[1]~0_combout & (\sdram_|process_0~2_combout & (\sdram_|r.state [7] $ (!\sdram_|r.state [8])))) + + .dataa(\sdram_|r.act_row[1]~0_combout ), + .datab(\sdram_|process_0~2_combout ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.act_row[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.act_row[1]~1 .lut_mask = 16'h8008; +defparam \sdram_|r.act_row[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y13_N9 +dffeas \sdram_|r.act_row[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\z80_|address_pins_|abus[15]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.act_row[1]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[4] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y13_N23 +dffeas \sdram_|r.act_row[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[1]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[3] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N20 +cycloneive_lcell_comb \sdram_|r.act_row[2]~feeder ( +// Equation(s): +// \sdram_|r.act_row[2]~feeder_combout = \z80_|address_pins_|abus[13]~23_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~23_combout ), + .cin(gnd), + .combout(\sdram_|r.act_row[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.act_row[2]~feeder .lut_mask = 16'hFF00; +defparam \sdram_|r.act_row[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y13_N21 +dffeas \sdram_|r.act_row[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.act_row[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.act_row[1]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[2] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N22 +cycloneive_lcell_comb \sdram_|Equal7~1 ( +// Equation(s): +// \sdram_|Equal7~1_combout = (\z80_|address_pins_|abus[14]~22_combout & (\sdram_|r.act_row [3] & (\z80_|address_pins_|abus[13]~23_combout $ (!\sdram_|r.act_row [2])))) # (!\z80_|address_pins_|abus[14]~22_combout & (!\sdram_|r.act_row [3] & +// (\z80_|address_pins_|abus[13]~23_combout $ (!\sdram_|r.act_row [2])))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\sdram_|r.act_row [3]), + .datad(\sdram_|r.act_row [2]), + .cin(gnd), + .combout(\sdram_|Equal7~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal7~1 .lut_mask = 16'h8421; +defparam \sdram_|Equal7~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y13_N3 +dffeas \sdram_|r.act_row[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[12]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[1]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[1] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y13_N13 +dffeas \sdram_|r.act_row[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[11]~19_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[1]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[0] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N2 +cycloneive_lcell_comb \sdram_|Equal7~0 ( +// Equation(s): +// \sdram_|Equal7~0_combout = (\z80_|address_pins_|abus[11]~19_combout & (\sdram_|r.act_row [0] & (\z80_|address_pins_|abus[12]~24_combout $ (!\sdram_|r.act_row [1])))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\sdram_|r.act_row [0] & +// (\z80_|address_pins_|abus[12]~24_combout $ (!\sdram_|r.act_row [1])))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\z80_|address_pins_|abus[12]~24_combout ), + .datac(\sdram_|r.act_row [1]), + .datad(\sdram_|r.act_row [0]), + .cin(gnd), + .combout(\sdram_|Equal7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal7~0 .lut_mask = 16'h8241; +defparam \sdram_|Equal7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N30 +cycloneive_lcell_comb \sdram_|Equal7~2 ( +// Equation(s): +// \sdram_|Equal7~2_combout = (\sdram_|Equal7~1_combout & (\sdram_|Equal7~0_combout & (\z80_|address_pins_|abus[15]~21_combout $ (!\sdram_|r.act_row [4])))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\sdram_|r.act_row [4]), + .datac(\sdram_|Equal7~1_combout ), + .datad(\sdram_|Equal7~0_combout ), + .cin(gnd), + .combout(\sdram_|Equal7~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal7~2 .lut_mask = 16'h9000; +defparam \sdram_|Equal7~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N4 +cycloneive_lcell_comb \sdram_|Mux39~0 ( +// Equation(s): +// \sdram_|Mux39~0_combout = (\sdram_|r.state [5] & (\sdram_|r.state [7] & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & (\sdram_|r.state [8] & (!\sdram_|r.state [7] & !\sdram_|r.state [4]))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux39~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux39~0 .lut_mask = 16'h8024; +defparam \sdram_|Mux39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N12 +cycloneive_lcell_comb \sdram_|Mux39~1 ( +// Equation(s): +// \sdram_|Mux39~1_combout = (\sdram_|r.state [6]) # ((!\sdram_|Mux39~0_combout ) # (!\sdram_|Equal7~2_combout )) + + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|Mux39~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux39~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux39~1 .lut_mask = 16'hAFFF; +defparam \sdram_|Mux39~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N24 +cycloneive_lcell_comb \sdram_|Mux39~2 ( +// Equation(s): +// \sdram_|Mux39~2_combout = (\sdram_|r.wr_pending~q & (\sdram_|Mux39~1_combout )) # (!\sdram_|r.wr_pending~q & (((\z80_|address_pins_|abus[15]~21_combout & \ExtRamWE~0_combout )))) + + .dataa(\sdram_|Mux39~1_combout ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\sdram_|r.wr_pending~q ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux39~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux39~2 .lut_mask = 16'hACA0; +defparam \sdram_|Mux39~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y12_N25 +dffeas \sdram_|r.wr_pending ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux39~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.wr_pending~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.wr_pending .is_wysiwyg = "true"; +defparam \sdram_|r.wr_pending .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N8 +cycloneive_lcell_comb \sdram_|Mux9~8 ( +// Equation(s): +// \sdram_|Mux9~8_combout = (\sdram_|r.state [8] & !\sdram_|r.state [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux9~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~8 .lut_mask = 16'h00F0; +defparam \sdram_|Mux9~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N20 +cycloneive_lcell_comb \sdram_|Mux9~9 ( +// Equation(s): +// \sdram_|Mux9~9_combout = (!\sdram_|r.rd_pending~q & (!\sdram_|r.rf_pending~q & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.wr_pending~q )))) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux9~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~9 .lut_mask = 16'h0405; +defparam \sdram_|Mux9~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N26 +cycloneive_lcell_comb \sdram_|Mux6~3 ( +// Equation(s): +// \sdram_|Mux6~3_combout = (\sdram_|r.state [6] & (((!\sdram_|Mux9~9_combout ) # (!\sdram_|Mux9~8_combout )))) # (!\sdram_|r.state [6] & (\sdram_|r.wr_pending~q & (\sdram_|Mux9~8_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|Mux9~8_combout ), + .datad(\sdram_|Mux9~9_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~3 .lut_mask = 16'h4AEA; +defparam \sdram_|Mux6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N0 +cycloneive_lcell_comb \sdram_|Mux6~4 ( +// Equation(s): +// \sdram_|Mux6~4_combout = (\sdram_|r.state [6]) # ((!\sdram_|r.rf_pending~q & \sdram_|Equal7~2_combout )) + + .dataa(gnd), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux6~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~4 .lut_mask = 16'hFF30; +defparam \sdram_|Mux6~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N6 +cycloneive_lcell_comb \sdram_|Mux6~2 ( +// Equation(s): +// \sdram_|Mux6~2_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [8]) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & ((\sdram_|r.state [4]))) + + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~2 .lut_mask = 16'hF5AA; +defparam \sdram_|Mux6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N10 +cycloneive_lcell_comb \sdram_|Mux6~5 ( +// Equation(s): +// \sdram_|Mux6~5_combout = (\sdram_|r.state [5] & (((\sdram_|Mux6~2_combout )))) # (!\sdram_|r.state [5] & (\sdram_|Mux6~3_combout & (\sdram_|Mux6~4_combout ))) + + .dataa(\sdram_|Mux6~3_combout ), + .datab(\sdram_|Mux6~4_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|Mux6~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~5 .lut_mask = 16'hF808; +defparam \sdram_|Mux6~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N8 +cycloneive_lcell_comb \sdram_|process_0~3 ( +// Equation(s): +// \sdram_|process_0~3_combout = (\sdram_|r.wr_pending~q & \sdram_|Equal7~2_combout ) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(gnd), + .datac(\sdram_|Equal7~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|process_0~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~3 .lut_mask = 16'hA0A0; +defparam \sdram_|process_0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N14 +cycloneive_lcell_comb \sdram_|Mux6~0 ( +// Equation(s): +// \sdram_|Mux6~0_combout = (\sdram_|r.state [8] & (\sdram_|r.state [4] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|process_0~3_combout )))) # (!\sdram_|r.state [8] & (!\sdram_|r.rf_pending~q & (\sdram_|process_0~3_combout & !\sdram_|r.state [4]))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|process_0~3_combout ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~0 .lut_mask = 16'h8A10; +defparam \sdram_|Mux6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N16 +cycloneive_lcell_comb \sdram_|Mux6~1 ( +// Equation(s): +// \sdram_|Mux6~1_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] $ (((\sdram_|r.state [6]) # (\sdram_|Mux6~0_combout ))))) # (!\sdram_|r.state [5] & (\sdram_|r.state [6] & ((\sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|Mux6~0_combout ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~1 .lut_mask = 16'h46A8; +defparam \sdram_|Mux6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N24 +cycloneive_lcell_comb \sdram_|Mux6~6 ( +// Equation(s): +// \sdram_|Mux6~6_combout = (\sdram_|r.state [7] & ((\sdram_|Mux6~1_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux6~5_combout )) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux6~5_combout ), + .datad(\sdram_|Mux6~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~6 .lut_mask = 16'hFC30; +defparam \sdram_|Mux6~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y15_N25 +dffeas \sdram_|r.state[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux6~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[6] .is_wysiwyg = "true"; +defparam \sdram_|r.state[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N12 +cycloneive_lcell_comb \sdram_|r.address[3]~6 ( +// Equation(s): +// \sdram_|r.address[3]~6_combout = (!\sdram_|r.state [6] & (!\sdram_|r.state [7] & !\sdram_|r.state [8])) + + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.address[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~6 .lut_mask = 16'h0005; +defparam \sdram_|r.address[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N22 +cycloneive_lcell_comb \sdram_|Mux7~2 ( +// Equation(s): +// \sdram_|Mux7~2_combout = (!\sdram_|r.state [5] & (\sdram_|r.state [4] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|r.address[3]~6_combout )))) + + .dataa(\sdram_|r.address[3]~6_combout ), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux7~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~2 .lut_mask = 16'h3100; +defparam \sdram_|Mux7~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N12 +cycloneive_lcell_comb \sdram_|n~3 ( +// Equation(s): +// \sdram_|n~3_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q ))) + + .dataa(gnd), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|n~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|n~3 .lut_mask = 16'hFC00; +defparam \sdram_|n~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N6 +cycloneive_lcell_comb \sdram_|Mux7~3 ( +// Equation(s): +// \sdram_|Mux7~3_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [6]) # (!\sdram_|r.rd_pending~q ))) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|r.state [6]), + .datac(gnd), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux7~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~3 .lut_mask = 16'h7700; +defparam \sdram_|Mux7~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N28 +cycloneive_lcell_comb \sdram_|Mux7~4 ( +// Equation(s): +// \sdram_|Mux7~4_combout = (\sdram_|r.state [6] & (\sdram_|Mux7~3_combout & (!\sdram_|r.wr_pending~q & \sdram_|r.state [7]))) # (!\sdram_|r.state [6] & (\sdram_|Mux7~3_combout $ (((\sdram_|r.state [7]))))) + + .dataa(\sdram_|Mux7~3_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux7~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~4 .lut_mask = 16'h1922; +defparam \sdram_|Mux7~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N10 +cycloneive_lcell_comb \sdram_|Mux7~5 ( +// Equation(s): +// \sdram_|Mux7~5_combout = (\sdram_|r.state [6] & (((\sdram_|r.rf_pending~q & \sdram_|Mux7~4_combout )))) # (!\sdram_|r.state [6] & (!\sdram_|Mux7~4_combout & ((\sdram_|r.rf_pending~q ) # (!\sdram_|n~3_combout )))) + + .dataa(\sdram_|n~3_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Mux7~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux7~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~5 .lut_mask = 16'hC031; +defparam \sdram_|Mux7~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N0 +cycloneive_lcell_comb \sdram_|Mux23~0 ( +// Equation(s): +// \sdram_|Mux23~0_combout = (\sdram_|r.state [8] & \sdram_|r.state [6]) + + .dataa(gnd), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [6]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|Mux23~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~0 .lut_mask = 16'hC0C0; +defparam \sdram_|Mux23~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N24 +cycloneive_lcell_comb \sdram_|Mux13~7 ( +// Equation(s): +// \sdram_|Mux13~7_combout = (!\sdram_|r.state [4] & \sdram_|r.state [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), + .cin(gnd), + .combout(\sdram_|Mux13~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~7 .lut_mask = 16'h0F00; +defparam \sdram_|Mux13~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N20 +cycloneive_lcell_comb \sdram_|Mux10~10 ( +// Equation(s): +// \sdram_|Mux10~10_combout = (!\sdram_|r.state [8] & (((\sdram_|r.state [6]) # (\sdram_|r.rf_pending~q )) # (!\sdram_|n~3_combout ))) + + .dataa(\sdram_|n~3_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.rf_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux10~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~10 .lut_mask = 16'h3331; +defparam \sdram_|Mux10~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N18 +cycloneive_lcell_comb \sdram_|Mux7~1 ( +// Equation(s): +// \sdram_|Mux7~1_combout = (\sdram_|Mux13~7_combout & ((\sdram_|Mux23~0_combout ) # ((\sdram_|Mux10~10_combout ) # (!\sdram_|r.state [7])))) + + .dataa(\sdram_|Mux23~0_combout ), + .datab(\sdram_|Mux13~7_combout ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|Mux10~10_combout ), + .cin(gnd), + .combout(\sdram_|Mux7~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~1 .lut_mask = 16'hCC8C; +defparam \sdram_|Mux7~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N22 +cycloneive_lcell_comb \sdram_|Mux7~6 ( +// Equation(s): +// \sdram_|Mux7~6_combout = (\sdram_|Mux7~2_combout ) # ((\sdram_|Mux7~1_combout ) # ((\sdram_|Mux7~5_combout & \sdram_|r.state [8]))) + + .dataa(\sdram_|Mux7~2_combout ), + .datab(\sdram_|Mux7~5_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux7~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux7~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~6 .lut_mask = 16'hFFEA; +defparam \sdram_|Mux7~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y15_N23 +dffeas \sdram_|r.state[5] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux7~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[5] .is_wysiwyg = "true"; +defparam \sdram_|r.state[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N6 +cycloneive_lcell_comb \sdram_|Mux5~2 ( +// Equation(s): +// \sdram_|Mux5~2_combout = (\sdram_|Mux13~7_combout & ((\sdram_|r.state [6]) # ((!\sdram_|Mux4~0_combout & !\sdram_|r.state [8])))) + + .dataa(\sdram_|Mux4~0_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux13~7_combout ), + .cin(gnd), + .combout(\sdram_|Mux5~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~2 .lut_mask = 16'hCD00; +defparam \sdram_|Mux5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N18 +cycloneive_lcell_comb \sdram_|Mux5~10 ( +// Equation(s): +// \sdram_|Mux5~10_combout = (\sdram_|r.state [6] & (\sdram_|r.state [8] & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q )))) # (!\sdram_|r.state [6] & (((!\sdram_|r.state [8])))) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux5~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~10 .lut_mask = 16'hE00F; +defparam \sdram_|Mux5~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N16 +cycloneive_lcell_comb \sdram_|Mux5~3 ( +// Equation(s): +// \sdram_|Mux5~3_combout = ((\sdram_|Mux5~10_combout ) # ((!\sdram_|r.state [6] & !\sdram_|Mux4~0_combout ))) # (!\sdram_|r.state [5]) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|Mux4~0_combout ), + .datad(\sdram_|Mux5~10_combout ), + .cin(gnd), + .combout(\sdram_|Mux5~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~3 .lut_mask = 16'hFF37; +defparam \sdram_|Mux5~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N30 +cycloneive_lcell_comb \sdram_|Mux5~4 ( +// Equation(s): +// \sdram_|Mux5~4_combout = (\sdram_|r.state [7] & ((\sdram_|Mux5~2_combout ) # ((\sdram_|Mux5~3_combout & \sdram_|r.state [4])))) + + .dataa(\sdram_|Mux5~2_combout ), + .datab(\sdram_|Mux5~3_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux5~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~4 .lut_mask = 16'hEA00; +defparam \sdram_|Mux5~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N18 +cycloneive_lcell_comb \sdram_|Mux5~7 ( +// Equation(s): +// \sdram_|Mux5~7_combout = (!\sdram_|r.state [8] & (\sdram_|r.state [4] & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.rd_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux5~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~7 .lut_mask = 16'h4440; +defparam \sdram_|Mux5~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N4 +cycloneive_lcell_comb \sdram_|Mux5~8 ( +// Equation(s): +// \sdram_|Mux5~8_combout = (!\sdram_|r.state [6] & ((\sdram_|r.state [7]) # ((\sdram_|Mux5~7_combout & !\sdram_|r.rf_pending~q )))) + + .dataa(\sdram_|Mux5~7_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux5~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~8 .lut_mask = 16'h3302; +defparam \sdram_|Mux5~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N26 +cycloneive_lcell_comb \sdram_|Mux5~5 ( +// Equation(s): +// \sdram_|Mux5~5_combout = (!\sdram_|r.state [7] & (((\sdram_|r.rf_pending~q ) # (!\sdram_|Equal7~2_combout )) # (!\sdram_|r.rd_pending~q ))) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux5~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~5 .lut_mask = 16'h00DF; +defparam \sdram_|Mux5~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N12 +cycloneive_lcell_comb \sdram_|Mux5~6 ( +// Equation(s): +// \sdram_|Mux5~6_combout = (\sdram_|Mux9~8_combout & ((\sdram_|Mux5~5_combout ) # ((!\sdram_|r.state [6] & \sdram_|process_0~3_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|process_0~3_combout ), + .datac(\sdram_|Mux9~8_combout ), + .datad(\sdram_|Mux5~5_combout ), + .cin(gnd), + .combout(\sdram_|Mux5~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~6 .lut_mask = 16'hF040; +defparam \sdram_|Mux5~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N20 +cycloneive_lcell_comb \sdram_|Mux5~9 ( +// Equation(s): +// \sdram_|Mux5~9_combout = (\sdram_|Mux5~4_combout ) # ((!\sdram_|r.state [5] & ((\sdram_|Mux5~8_combout ) # (\sdram_|Mux5~6_combout )))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|Mux5~4_combout ), + .datac(\sdram_|Mux5~8_combout ), + .datad(\sdram_|Mux5~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux5~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~9 .lut_mask = 16'hDDDC; +defparam \sdram_|Mux5~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y15_N21 +dffeas \sdram_|r.state[7] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux5~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[7] .is_wysiwyg = "true"; +defparam \sdram_|r.state[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N8 +cycloneive_lcell_comb \sdram_|n~2 ( +// Equation(s): +// \sdram_|n~2_combout = (\sdram_|r.rd_pending~q ) # ((\sdram_|r.rf_pending~q ) # (\sdram_|r.wr_pending~q )) + + .dataa(gnd), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|n~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|n~2 .lut_mask = 16'hFFFC; +defparam \sdram_|n~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N8 +cycloneive_lcell_comb \sdram_|Mux8~3 ( +// Equation(s): +// \sdram_|Mux8~3_combout = (\sdram_|r.state [5] & (\sdram_|n~2_combout & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & (((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) + + .dataa(\sdram_|n~2_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux8~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~3 .lut_mask = 16'h8C2F; +defparam \sdram_|Mux8~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N6 +cycloneive_lcell_comb \sdram_|Mux8~4 ( +// Equation(s): +// \sdram_|Mux8~4_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [6] $ (\sdram_|Mux8~3_combout )))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [4] & ((\sdram_|r.state [6]) # (\sdram_|Mux8~3_combout )))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|Mux8~3_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux8~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~4 .lut_mask = 16'h3C54; +defparam \sdram_|Mux8~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N4 +cycloneive_lcell_comb \sdram_|Mux9~10 ( +// Equation(s): +// \sdram_|Mux9~10_combout = (!\sdram_|r.state [4] & ((!\sdram_|r.state [8]) # (!\sdram_|Mux9~9_combout ))) + + .dataa(gnd), + .datab(\sdram_|Mux9~9_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux9~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~10 .lut_mask = 16'h003F; +defparam \sdram_|Mux9~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N28 +cycloneive_lcell_comb \sdram_|r.init_counter[0]~0 ( +// Equation(s): +// \sdram_|r.init_counter[0]~0_combout = !\sdram_|r.init_counter [0] + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.init_counter [0]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.init_counter[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.init_counter[0]~0 .lut_mask = 16'h0F0F; +defparam \sdram_|r.init_counter[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y7_N29 +dffeas \sdram_|r.init_counter[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.init_counter[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[0] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N2 +cycloneive_lcell_comb \sdram_|Add1~1 ( +// Equation(s): +// \sdram_|Add1~1_cout = CARRY(\sdram_|r.init_counter [0]) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\sdram_|Add1~1_cout )); +// synopsys translate_off +defparam \sdram_|Add1~1 .lut_mask = 16'h00CC; +defparam \sdram_|Add1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N4 +cycloneive_lcell_comb \sdram_|Add1~2 ( +// Equation(s): +// \sdram_|Add1~2_combout = (\sdram_|r.init_counter [1] & (\sdram_|Add1~1_cout & VCC)) # (!\sdram_|r.init_counter [1] & (!\sdram_|Add1~1_cout )) +// \sdram_|Add1~3 = CARRY((!\sdram_|r.init_counter [1] & !\sdram_|Add1~1_cout )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~1_cout ), + .combout(\sdram_|Add1~2_combout ), + .cout(\sdram_|Add1~3 )); +// synopsys translate_off +defparam \sdram_|Add1~2 .lut_mask = 16'hC303; +defparam \sdram_|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N5 +dffeas \sdram_|r.init_counter[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[1] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N6 +cycloneive_lcell_comb \sdram_|Add1~4 ( +// Equation(s): +// \sdram_|Add1~4_combout = (\sdram_|r.init_counter [2] & ((GND) # (!\sdram_|Add1~3 ))) # (!\sdram_|r.init_counter [2] & (\sdram_|Add1~3 $ (GND))) +// \sdram_|Add1~5 = CARRY((\sdram_|r.init_counter [2]) # (!\sdram_|Add1~3 )) + + .dataa(\sdram_|r.init_counter [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~3 ), + .combout(\sdram_|Add1~4_combout ), + .cout(\sdram_|Add1~5 )); +// synopsys translate_off +defparam \sdram_|Add1~4 .lut_mask = 16'h5AAF; +defparam \sdram_|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N7 +dffeas \sdram_|r.init_counter[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[2] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N8 +cycloneive_lcell_comb \sdram_|Add1~6 ( +// Equation(s): +// \sdram_|Add1~6_combout = (\sdram_|r.init_counter [3] & (!\sdram_|Add1~5 )) # (!\sdram_|r.init_counter [3] & (\sdram_|Add1~5 & VCC)) +// \sdram_|Add1~7 = CARRY((\sdram_|r.init_counter [3] & !\sdram_|Add1~5 )) + + .dataa(\sdram_|r.init_counter [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~5 ), + .combout(\sdram_|Add1~6_combout ), + .cout(\sdram_|Add1~7 )); +// synopsys translate_off +defparam \sdram_|Add1~6 .lut_mask = 16'h5A0A; +defparam \sdram_|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N2 +cycloneive_lcell_comb \sdram_|r.init_counter[3]~1 ( +// Equation(s): +// \sdram_|r.init_counter[3]~1_combout = !\sdram_|Add1~6_combout + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|Add1~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.init_counter[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.init_counter[3]~1 .lut_mask = 16'h0F0F; +defparam \sdram_|r.init_counter[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y3_N3 +dffeas \sdram_|r.init_counter[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.init_counter[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[3] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N10 +cycloneive_lcell_comb \sdram_|Add1~8 ( +// Equation(s): +// \sdram_|Add1~8_combout = (\sdram_|r.init_counter [4] & ((GND) # (!\sdram_|Add1~7 ))) # (!\sdram_|r.init_counter [4] & (\sdram_|Add1~7 $ (GND))) +// \sdram_|Add1~9 = CARRY((\sdram_|r.init_counter [4]) # (!\sdram_|Add1~7 )) + + .dataa(\sdram_|r.init_counter [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~7 ), + .combout(\sdram_|Add1~8_combout ), + .cout(\sdram_|Add1~9 )); +// synopsys translate_off +defparam \sdram_|Add1~8 .lut_mask = 16'h5AAF; +defparam \sdram_|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N11 +dffeas \sdram_|r.init_counter[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[4] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N12 +cycloneive_lcell_comb \sdram_|Add1~10 ( +// Equation(s): +// \sdram_|Add1~10_combout = (\sdram_|r.init_counter [5] & (\sdram_|Add1~9 & VCC)) # (!\sdram_|r.init_counter [5] & (!\sdram_|Add1~9 )) +// \sdram_|Add1~11 = CARRY((!\sdram_|r.init_counter [5] & !\sdram_|Add1~9 )) + + .dataa(\sdram_|r.init_counter [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~9 ), + .combout(\sdram_|Add1~10_combout ), + .cout(\sdram_|Add1~11 )); +// synopsys translate_off +defparam \sdram_|Add1~10 .lut_mask = 16'hA505; +defparam \sdram_|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N13 +dffeas \sdram_|r.init_counter[5] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[5] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N14 +cycloneive_lcell_comb \sdram_|Add1~12 ( +// Equation(s): +// \sdram_|Add1~12_combout = (\sdram_|r.init_counter [6] & ((GND) # (!\sdram_|Add1~11 ))) # (!\sdram_|r.init_counter [6] & (\sdram_|Add1~11 $ (GND))) +// \sdram_|Add1~13 = CARRY((\sdram_|r.init_counter [6]) # (!\sdram_|Add1~11 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~11 ), + .combout(\sdram_|Add1~12_combout ), + .cout(\sdram_|Add1~13 )); +// synopsys translate_off +defparam \sdram_|Add1~12 .lut_mask = 16'h3CCF; +defparam \sdram_|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N15 +dffeas \sdram_|r.init_counter[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[6] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N16 +cycloneive_lcell_comb \sdram_|Add1~14 ( +// Equation(s): +// \sdram_|Add1~14_combout = (\sdram_|r.init_counter [7] & (\sdram_|Add1~13 & VCC)) # (!\sdram_|r.init_counter [7] & (!\sdram_|Add1~13 )) +// \sdram_|Add1~15 = CARRY((!\sdram_|r.init_counter [7] & !\sdram_|Add1~13 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~13 ), + .combout(\sdram_|Add1~14_combout ), + .cout(\sdram_|Add1~15 )); +// synopsys translate_off +defparam \sdram_|Add1~14 .lut_mask = 16'hC303; +defparam \sdram_|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N17 +dffeas \sdram_|r.init_counter[7] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~14_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[7] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N18 +cycloneive_lcell_comb \sdram_|Add1~16 ( +// Equation(s): +// \sdram_|Add1~16_combout = (\sdram_|r.init_counter [8] & ((GND) # (!\sdram_|Add1~15 ))) # (!\sdram_|r.init_counter [8] & (\sdram_|Add1~15 $ (GND))) +// \sdram_|Add1~17 = CARRY((\sdram_|r.init_counter [8]) # (!\sdram_|Add1~15 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~15 ), + .combout(\sdram_|Add1~16_combout ), + .cout(\sdram_|Add1~17 )); +// synopsys translate_off +defparam \sdram_|Add1~16 .lut_mask = 16'h3CCF; +defparam \sdram_|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N19 +dffeas \sdram_|r.init_counter[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[8] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N20 +cycloneive_lcell_comb \sdram_|Add1~18 ( +// Equation(s): +// \sdram_|Add1~18_combout = (\sdram_|r.init_counter [9] & (\sdram_|Add1~17 & VCC)) # (!\sdram_|r.init_counter [9] & (!\sdram_|Add1~17 )) +// \sdram_|Add1~19 = CARRY((!\sdram_|r.init_counter [9] & !\sdram_|Add1~17 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [9]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~17 ), + .combout(\sdram_|Add1~18_combout ), + .cout(\sdram_|Add1~19 )); +// synopsys translate_off +defparam \sdram_|Add1~18 .lut_mask = 16'hC303; +defparam \sdram_|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N21 +dffeas \sdram_|r.init_counter[9] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[9] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N22 +cycloneive_lcell_comb \sdram_|Add1~20 ( +// Equation(s): +// \sdram_|Add1~20_combout = (\sdram_|r.init_counter [10] & ((GND) # (!\sdram_|Add1~19 ))) # (!\sdram_|r.init_counter [10] & (\sdram_|Add1~19 $ (GND))) +// \sdram_|Add1~21 = CARRY((\sdram_|r.init_counter [10]) # (!\sdram_|Add1~19 )) + + .dataa(\sdram_|r.init_counter [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~19 ), + .combout(\sdram_|Add1~20_combout ), + .cout(\sdram_|Add1~21 )); +// synopsys translate_off +defparam \sdram_|Add1~20 .lut_mask = 16'h5AAF; +defparam \sdram_|Add1~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N23 +dffeas \sdram_|r.init_counter[10] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~20_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[10] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N22 +cycloneive_lcell_comb \sdram_|Equal2~0 ( +// Equation(s): +// \sdram_|Equal2~0_combout = (!\sdram_|r.init_counter [9] & (!\sdram_|r.init_counter [8] & (!\sdram_|r.init_counter [4] & !\sdram_|r.init_counter [10]))) + + .dataa(\sdram_|r.init_counter [9]), + .datab(\sdram_|r.init_counter [8]), + .datac(\sdram_|r.init_counter [4]), + .datad(\sdram_|r.init_counter [10]), + .cin(gnd), + .combout(\sdram_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~0 .lut_mask = 16'h0001; +defparam \sdram_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N0 +cycloneive_lcell_comb \sdram_|Equal2~1 ( +// Equation(s): +// \sdram_|Equal2~1_combout = (!\sdram_|r.init_counter [6] & (!\sdram_|r.init_counter [5] & \sdram_|r.init_counter [3])) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [6]), + .datac(\sdram_|r.init_counter [5]), + .datad(\sdram_|r.init_counter [3]), + .cin(gnd), + .combout(\sdram_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~1 .lut_mask = 16'h0300; +defparam \sdram_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N24 +cycloneive_lcell_comb \sdram_|Add1~22 ( +// Equation(s): +// \sdram_|Add1~22_combout = (\sdram_|r.init_counter [11] & (\sdram_|Add1~21 & VCC)) # (!\sdram_|r.init_counter [11] & (!\sdram_|Add1~21 )) +// \sdram_|Add1~23 = CARRY((!\sdram_|r.init_counter [11] & !\sdram_|Add1~21 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [11]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~21 ), + .combout(\sdram_|Add1~22_combout ), + .cout(\sdram_|Add1~23 )); +// synopsys translate_off +defparam \sdram_|Add1~22 .lut_mask = 16'hC303; +defparam \sdram_|Add1~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N25 +dffeas \sdram_|r.init_counter[11] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[11] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N26 +cycloneive_lcell_comb \sdram_|Add1~24 ( +// Equation(s): +// \sdram_|Add1~24_combout = (\sdram_|r.init_counter [12] & ((GND) # (!\sdram_|Add1~23 ))) # (!\sdram_|r.init_counter [12] & (\sdram_|Add1~23 $ (GND))) +// \sdram_|Add1~25 = CARRY((\sdram_|r.init_counter [12]) # (!\sdram_|Add1~23 )) + + .dataa(\sdram_|r.init_counter [12]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~23 ), + .combout(\sdram_|Add1~24_combout ), + .cout(\sdram_|Add1~25 )); +// synopsys translate_off +defparam \sdram_|Add1~24 .lut_mask = 16'h5AAF; +defparam \sdram_|Add1~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N27 +dffeas \sdram_|r.init_counter[12] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[12] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N28 +cycloneive_lcell_comb \sdram_|Add1~26 ( +// Equation(s): +// \sdram_|Add1~26_combout = (\sdram_|r.init_counter [13] & (\sdram_|Add1~25 & VCC)) # (!\sdram_|r.init_counter [13] & (!\sdram_|Add1~25 )) +// \sdram_|Add1~27 = CARRY((!\sdram_|r.init_counter [13] & !\sdram_|Add1~25 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [13]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~25 ), + .combout(\sdram_|Add1~26_combout ), + .cout(\sdram_|Add1~27 )); +// synopsys translate_off +defparam \sdram_|Add1~26 .lut_mask = 16'hC303; +defparam \sdram_|Add1~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N29 +dffeas \sdram_|r.init_counter[13] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~26_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[13] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N30 +cycloneive_lcell_comb \sdram_|Add1~28 ( +// Equation(s): +// \sdram_|Add1~28_combout = \sdram_|r.init_counter [14] $ (\sdram_|Add1~27 ) + + .dataa(\sdram_|r.init_counter [14]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sdram_|Add1~27 ), + .combout(\sdram_|Add1~28_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Add1~28 .lut_mask = 16'h5A5A; +defparam \sdram_|Add1~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N31 +dffeas \sdram_|r.init_counter[14] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~28_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[14] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N0 +cycloneive_lcell_comb \sdram_|process_0~5 ( +// Equation(s): +// \sdram_|process_0~5_combout = (!\sdram_|r.init_counter [14] & (!\sdram_|r.init_counter [11] & (!\sdram_|r.init_counter [12] & !\sdram_|r.init_counter [13]))) + + .dataa(\sdram_|r.init_counter [14]), + .datab(\sdram_|r.init_counter [11]), + .datac(\sdram_|r.init_counter [12]), + .datad(\sdram_|r.init_counter [13]), + .cin(gnd), + .combout(\sdram_|process_0~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~5 .lut_mask = 16'h0001; +defparam \sdram_|process_0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N6 +cycloneive_lcell_comb \sdram_|Equal2~2 ( +// Equation(s): +// \sdram_|Equal2~2_combout = (\sdram_|Equal2~0_combout & (\sdram_|Equal2~1_combout & (\sdram_|process_0~5_combout & !\sdram_|r.init_counter [2]))) + + .dataa(\sdram_|Equal2~0_combout ), + .datab(\sdram_|Equal2~1_combout ), + .datac(\sdram_|process_0~5_combout ), + .datad(\sdram_|r.init_counter [2]), + .cin(gnd), + .combout(\sdram_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~2 .lut_mask = 16'h0080; +defparam \sdram_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N10 +cycloneive_lcell_comb \sdram_|Mux9~11 ( +// Equation(s): +// \sdram_|Mux9~11_combout = (!\sdram_|r.init_counter [1] & (\sdram_|r.init_counter [0] & !\sdram_|r.init_counter [7])) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [0]), + .datac(gnd), + .datad(\sdram_|r.init_counter [7]), + .cin(gnd), + .combout(\sdram_|Mux9~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~11 .lut_mask = 16'h0044; +defparam \sdram_|Mux9~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N24 +cycloneive_lcell_comb \sdram_|Mux9~12 ( +// Equation(s): +// \sdram_|Mux9~12_combout = (\sdram_|r.state [4] & (!\sdram_|n~2_combout )) # (!\sdram_|r.state [4] & (((\sdram_|Equal2~2_combout & \sdram_|Mux9~11_combout )))) + + .dataa(\sdram_|n~2_combout ), + .datab(\sdram_|Equal2~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|Mux9~11_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~12 .lut_mask = 16'h5C50; +defparam \sdram_|Mux9~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N0 +cycloneive_lcell_comb \sdram_|Mux9~13 ( +// Equation(s): +// \sdram_|Mux9~13_combout = (\sdram_|r.state [8] & (!\sdram_|r.state [4] & (\sdram_|n~2_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux9~12_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|n~2_combout ), + .datad(\sdram_|Mux9~12_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~13_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~13 .lut_mask = 16'h7520; +defparam \sdram_|Mux9~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N2 +cycloneive_lcell_comb \sdram_|Mux8~0 ( +// Equation(s): +// \sdram_|Mux8~0_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [5]) # ((\sdram_|Mux9~10_combout )))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [5] & ((\sdram_|Mux9~13_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|Mux9~10_combout ), + .datad(\sdram_|Mux9~13_combout ), + .cin(gnd), + .combout(\sdram_|Mux8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~0 .lut_mask = 16'hB9A8; +defparam \sdram_|Mux8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N16 +cycloneive_lcell_comb \sdram_|Mux8~1 ( +// Equation(s): +// \sdram_|Mux8~1_combout = (\sdram_|r.state [5] & (((!\sdram_|r.state [8] & \sdram_|Mux8~0_combout )) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [5] & (((\sdram_|Mux8~0_combout )))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|Mux8~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux8~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~1 .lut_mask = 16'h7F50; +defparam \sdram_|Mux8~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N20 +cycloneive_lcell_comb \sdram_|Mux8~2 ( +// Equation(s): +// \sdram_|Mux8~2_combout = (\sdram_|r.state [7] & (\sdram_|Mux8~4_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux8~1_combout ))) + + .dataa(\sdram_|r.state [7]), + .datab(gnd), + .datac(\sdram_|Mux8~4_combout ), + .datad(\sdram_|Mux8~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux8~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~2 .lut_mask = 16'hF5A0; +defparam \sdram_|Mux8~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y15_N21 +dffeas \sdram_|r.state[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux8~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[4] .is_wysiwyg = "true"; +defparam \sdram_|r.state[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N4 +cycloneive_lcell_comb \sdram_|Mux72~0 ( +// Equation(s): +// \sdram_|Mux72~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [0]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux72~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux72~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux72~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N2 +cycloneive_lcell_comb \sdram_|Mux72~1 ( +// Equation(s): +// \sdram_|Mux72~1_combout = (\sdram_|Mux72~0_combout & ((\D[0]~64_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\sdram_|Mux72~0_combout ), + .datad(\D[0]~64_combout ), + .cin(gnd), + .combout(\sdram_|Mux72~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux72~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux72~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N0 +cycloneive_lcell_comb \sdram_|Mux84~0 ( +// Equation(s): +// \sdram_|Mux84~0_combout = (\sdram_|r.state [5]) # (\sdram_|r.state [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux84~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux84~0 .lut_mask = 16'hFFF0; +defparam \sdram_|Mux84~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N2 +cycloneive_lcell_comb \sdram_|Mux84~1 ( +// Equation(s): +// \sdram_|Mux84~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [7] & (!\sdram_|r.state [8] & \sdram_|Mux84~0_combout ))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [7] & (\sdram_|r.state [8] & !\sdram_|Mux84~0_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux84~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux84~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux84~1 .lut_mask = 16'h0810; +defparam \sdram_|Mux84~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N16 +cycloneive_lcell_comb \sdram_|Mux3~0 ( +// Equation(s): +// \sdram_|Mux3~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [1]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux3~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N18 +cycloneive_lcell_comb \sdram_|Mux3~1 ( +// Equation(s): +// \sdram_|Mux3~1_combout = (\sdram_|Mux3~0_combout & ((\D[1]~40_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\sdram_|Mux3~0_combout ), + .datad(\D[1]~40_combout ), + .cin(gnd), + .combout(\sdram_|Mux3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux3~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N0 +cycloneive_lcell_comb \sdram_|Mux2~0 ( +// Equation(s): +// \sdram_|Mux2~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [2]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux2~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N30 +cycloneive_lcell_comb \sdram_|Mux2~1 ( +// Equation(s): +// \sdram_|Mux2~1_combout = (\sdram_|Mux2~0_combout & ((\D[2]~52_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\sdram_|Mux2~0_combout ), + .datad(\D[2]~52_combout ), + .cin(gnd), + .combout(\sdram_|Mux2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux2~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N28 +cycloneive_lcell_comb \sdram_|Mux1~0 ( +// Equation(s): +// \sdram_|Mux1~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [3]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux1~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N10 +cycloneive_lcell_comb \sdram_|Mux1~1 ( +// Equation(s): +// \sdram_|Mux1~1_combout = (\sdram_|Mux1~0_combout & ((\D[3]~108_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\D[3]~108_combout ), + .datad(\sdram_|Mux1~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux1~1 .lut_mask = 16'hF100; +defparam \sdram_|Mux1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N12 +cycloneive_lcell_comb \sdram_|Mux0~0 ( +// Equation(s): +// \sdram_|Mux0~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [4]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux0~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N26 +cycloneive_lcell_comb \sdram_|Mux0~1 ( +// Equation(s): +// \sdram_|Mux0~1_combout = (\sdram_|Mux0~0_combout & ((\D[4]~110_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\sdram_|Mux0~0_combout ), + .datad(\D[4]~110_combout ), + .cin(gnd), + .combout(\sdram_|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux0~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N8 +cycloneive_lcell_comb \sdram_|Mux73~0 ( +// Equation(s): +// \sdram_|Mux73~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [5]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux73~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux73~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux73~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N14 +cycloneive_lcell_comb \sdram_|Mux73~1 ( +// Equation(s): +// \sdram_|Mux73~1_combout = (\sdram_|Mux73~0_combout & ((\D[5]~112_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\sdram_|Mux73~0_combout ), + .datad(\D[5]~112_combout ), + .cin(gnd), + .combout(\sdram_|Mux73~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux73~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux73~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N24 +cycloneive_lcell_comb \sdram_|Mux74~0 ( +// Equation(s): +// \sdram_|Mux74~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [6]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux74~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux74~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux74~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N6 +cycloneive_lcell_comb \sdram_|Mux74~1 ( +// Equation(s): +// \sdram_|Mux74~1_combout = (\sdram_|Mux74~0_combout & ((\D[6]~114_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\sdram_|Mux74~0_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[6]~114_combout ), + .cin(gnd), + .combout(\sdram_|Mux74~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux74~1 .lut_mask = 16'hCC04; +defparam \sdram_|Mux74~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y4_N28 +cycloneive_lcell_comb \sdram_|Mux75~0 ( +// Equation(s): +// \sdram_|Mux75~0_combout = (\sdram_|r.state [4] & \D[7]~117_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\D[7]~117_combout ), + .cin(gnd), + .combout(\sdram_|Mux75~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux75~0 .lut_mask = 16'hF000; +defparam \sdram_|Mux75~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y32_N8 cycloneive_lcell_comb \ula_|i2s_intf_|mclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|mclk_r~0_combout = !\ula_|i2s_intf_|mclk_r~_Duplicate_1_q @@ -55715,7 +59007,7 @@ defparam \ula_|i2s_intf_|mclk_r~0 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|mclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y23_N17 +// Location: FF_X20_Y32_N9 dffeas \ula_|i2s_intf_|mclk_r~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|mclk_r~0_combout ), @@ -55753,24 +59045,24 @@ defparam \ula_|i2s_intf_|mclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|mclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N6 +// Location: LCCOMB_X20_Y31_N12 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~1 ( // Equation(s): // \ula_|i2s_intf_|Add0~1_cout = CARRY(!\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ) - .dataa(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), .datac(gnd), .datad(vcc), .cin(gnd), .combout(), .cout(\ula_|i2s_intf_|Add0~1_cout )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0033; defparam \ula_|i2s_intf_|Add0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N8 +// Location: LCCOMB_X20_Y31_N14 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~2 ( // Equation(s): // \ula_|i2s_intf_|Add0~2_combout = (\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Add0~1_cout & VCC)) # (!\ula_|i2s_intf_|lrdivider [1] & (!\ula_|i2s_intf_|Add0~1_cout )) @@ -55788,24 +59080,24 @@ defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hC303; defparam \ula_|i2s_intf_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N28 +// Location: LCCOMB_X20_Y31_N0 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~2 ( // Equation(s): -// \ula_|i2s_intf_|lrdivider~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~2_combout ) +// \ula_|i2s_intf_|lrdivider~2_combout = (\ula_|i2s_intf_|Add0~2_combout & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(gnd), .datab(gnd), .datac(\ula_|i2s_intf_|Add0~2_combout ), - .datad(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h5050; +defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h00F0; defparam \ula_|i2s_intf_|lrdivider~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N29 +// Location: FF_X20_Y31_N1 dffeas \ula_|i2s_intf_|lrdivider[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~2_combout ), @@ -55824,7 +59116,7 @@ defparam \ula_|i2s_intf_|lrdivider[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N10 +// Location: LCCOMB_X20_Y31_N16 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~4 ( // Equation(s): // \ula_|i2s_intf_|Add0~4_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|Add0~3 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add0~3 ))) @@ -55842,24 +59134,24 @@ defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hA55F; defparam \ula_|i2s_intf_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X30_Y23_N6 +// Location: LCCOMB_X21_Y31_N6 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[2]~8 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[2]~8_combout = !\ula_|i2s_intf_|Add0~4_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~4_combout ), + .datac(\ula_|i2s_intf_|Add0~4_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[2]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[2]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y23_N7 +// Location: FF_X21_Y31_N7 dffeas \ula_|i2s_intf_|lrdivider[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[2]~8_combout ), @@ -55878,42 +59170,42 @@ defparam \ula_|i2s_intf_|lrdivider[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N12 +// Location: LCCOMB_X20_Y31_N18 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~6 ( // Equation(s): // \ula_|i2s_intf_|Add0~6_combout = (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|Add0~5 )) # (!\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|Add0~5 & VCC)) // \ula_|i2s_intf_|Add0~7 = CARRY((\ula_|i2s_intf_|lrdivider [3] & !\ula_|i2s_intf_|Add0~5 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [3]), + .dataa(\ula_|i2s_intf_|lrdivider [3]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~5 ), .combout(\ula_|i2s_intf_|Add0~6_combout ), .cout(\ula_|i2s_intf_|Add0~7 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h3C0C; +defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h5A0A; defparam \ula_|i2s_intf_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N6 +// Location: LCCOMB_X20_Y32_N30 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[3]~7 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[3]~7_combout = !\ula_|i2s_intf_|Add0~6_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~6_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~6_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[3]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[3]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N7 +// Location: FF_X20_Y32_N31 dffeas \ula_|i2s_intf_|lrdivider[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[3]~7_combout ), @@ -55932,7 +59224,7 @@ defparam \ula_|i2s_intf_|lrdivider[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N14 +// Location: LCCOMB_X20_Y31_N20 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~8 ( // Equation(s): // \ula_|i2s_intf_|Add0~8_combout = (\ula_|i2s_intf_|lrdivider [4] & ((GND) # (!\ula_|i2s_intf_|Add0~7 ))) # (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|Add0~7 $ (GND))) @@ -55950,24 +59242,24 @@ defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N4 +// Location: LCCOMB_X20_Y31_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~1 ( // Equation(s): -// \ula_|i2s_intf_|lrdivider~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~8_combout ) +// \ula_|i2s_intf_|lrdivider~1_combout = (\ula_|i2s_intf_|Add0~8_combout & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~8_combout ), - .datad(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|Add0~8_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h5050; +defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h00CC; defparam \ula_|i2s_intf_|lrdivider~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N5 +// Location: FF_X20_Y31_N5 dffeas \ula_|i2s_intf_|lrdivider[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~1_combout ), @@ -55986,25 +59278,25 @@ defparam \ula_|i2s_intf_|lrdivider[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N16 +// Location: LCCOMB_X20_Y31_N22 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~10 ( // Equation(s): // \ula_|i2s_intf_|Add0~10_combout = (\ula_|i2s_intf_|lrdivider [5] & (!\ula_|i2s_intf_|Add0~9 )) # (!\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|Add0~9 & VCC)) // \ula_|i2s_intf_|Add0~11 = CARRY((\ula_|i2s_intf_|lrdivider [5] & !\ula_|i2s_intf_|Add0~9 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [5]), + .dataa(\ula_|i2s_intf_|lrdivider [5]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~9 ), .combout(\ula_|i2s_intf_|Add0~10_combout ), .cout(\ula_|i2s_intf_|Add0~11 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h3C0C; +defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h5A0A; defparam \ula_|i2s_intf_|Add0~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N2 +// Location: LCCOMB_X21_Y31_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[5]~6 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[5]~6_combout = !\ula_|i2s_intf_|Add0~10_combout @@ -56021,7 +59313,7 @@ defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[5]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N3 +// Location: FF_X21_Y31_N5 dffeas \ula_|i2s_intf_|lrdivider[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[5]~6_combout ), @@ -56040,7 +59332,7 @@ defparam \ula_|i2s_intf_|lrdivider[5] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N26 +// Location: LCCOMB_X20_Y31_N10 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~1 ( // Equation(s): // \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [2] & (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|lrdivider [3] & \ula_|i2s_intf_|lrdivider [5]))) @@ -56057,25 +59349,25 @@ defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h2000; defparam \ula_|i2s_intf_|Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N18 +// Location: LCCOMB_X20_Y31_N24 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~12 ( // Equation(s): // \ula_|i2s_intf_|Add0~12_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|Add0~11 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [6] & ((GND) # (!\ula_|i2s_intf_|Add0~11 ))) // \ula_|i2s_intf_|Add0~13 = CARRY((!\ula_|i2s_intf_|Add0~11 ) # (!\ula_|i2s_intf_|lrdivider [6])) - .dataa(\ula_|i2s_intf_|lrdivider [6]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [6]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~11 ), .combout(\ula_|i2s_intf_|Add0~12_combout ), .cout(\ula_|i2s_intf_|Add0~13 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hC33F; defparam \ula_|i2s_intf_|Add0~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N26 +// Location: LCCOMB_X21_Y31_N22 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[6]~5 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[6]~5_combout = !\ula_|i2s_intf_|Add0~12_combout @@ -56092,7 +59384,7 @@ defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[6]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N27 +// Location: FF_X21_Y31_N23 dffeas \ula_|i2s_intf_|lrdivider[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[6]~5_combout ), @@ -56111,7 +59403,7 @@ defparam \ula_|i2s_intf_|lrdivider[6] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N20 +// Location: LCCOMB_X20_Y31_N26 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~14 ( // Equation(s): // \ula_|i2s_intf_|Add0~14_combout = (\ula_|i2s_intf_|lrdivider [7] & (!\ula_|i2s_intf_|Add0~13 )) # (!\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|Add0~13 & VCC)) @@ -56129,24 +59421,24 @@ defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h5A0A; defparam \ula_|i2s_intf_|Add0~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X30_Y23_N4 +// Location: LCCOMB_X21_Y31_N20 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[7]~4 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[7]~4_combout = !\ula_|i2s_intf_|Add0~14_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~14_combout ), + .datac(\ula_|i2s_intf_|Add0~14_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[7]~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[7]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y23_N5 +// Location: FF_X21_Y31_N21 dffeas \ula_|i2s_intf_|lrdivider[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[7]~4_combout ), @@ -56165,42 +59457,42 @@ defparam \ula_|i2s_intf_|lrdivider[7] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N22 +// Location: LCCOMB_X20_Y31_N28 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~16 ( // Equation(s): // \ula_|i2s_intf_|Add0~16_combout = (\ula_|i2s_intf_|lrdivider [8] & ((GND) # (!\ula_|i2s_intf_|Add0~15 ))) # (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|Add0~15 $ (GND))) // \ula_|i2s_intf_|Add0~17 = CARRY((\ula_|i2s_intf_|lrdivider [8]) # (!\ula_|i2s_intf_|Add0~15 )) - .dataa(\ula_|i2s_intf_|lrdivider [8]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [8]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~15 ), .combout(\ula_|i2s_intf_|Add0~16_combout ), .cout(\ula_|i2s_intf_|Add0~17 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h5AAF; +defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|Add0~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N16 +// Location: LCCOMB_X20_Y31_N8 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~0 ( // Equation(s): // \ula_|i2s_intf_|lrdivider~0_combout = (\ula_|i2s_intf_|Add0~16_combout & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), .datab(\ula_|i2s_intf_|Add0~16_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h0C0C; +defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h00CC; defparam \ula_|i2s_intf_|lrdivider~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N17 +// Location: FF_X20_Y31_N9 dffeas \ula_|i2s_intf_|lrdivider[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~0_combout ), @@ -56219,7 +59511,7 @@ defparam \ula_|i2s_intf_|lrdivider[8] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N24 +// Location: LCCOMB_X20_Y31_N30 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~18 ( // Equation(s): // \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|Add0~17 $ (\ula_|i2s_intf_|lrdivider [9]) @@ -56236,24 +59528,24 @@ defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h0FF0; defparam \ula_|i2s_intf_|Add0~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N24 +// Location: LCCOMB_X19_Y31_N24 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[9]~3 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[9]~3_combout = !\ula_|i2s_intf_|Add0~18_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~18_combout ), + .datac(\ula_|i2s_intf_|Add0~18_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[9]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[9]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N25 +// Location: FF_X19_Y31_N25 dffeas \ula_|i2s_intf_|lrdivider[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[9]~3_combout ), @@ -56272,32 +59564,32 @@ defparam \ula_|i2s_intf_|lrdivider[9] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N0 +// Location: LCCOMB_X20_Y31_N6 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~0 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~0_combout = (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|lrdivider [9] & (\ula_|i2s_intf_|lrdivider [6] & \ula_|i2s_intf_|lrdivider [7]))) +// \ula_|i2s_intf_|Equal0~0_combout = (\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|lrdivider [9] & (!\ula_|i2s_intf_|lrdivider [8] & \ula_|i2s_intf_|lrdivider [6]))) - .dataa(\ula_|i2s_intf_|lrdivider [8]), + .dataa(\ula_|i2s_intf_|lrdivider [7]), .datab(\ula_|i2s_intf_|lrdivider [9]), - .datac(\ula_|i2s_intf_|lrdivider [6]), - .datad(\ula_|i2s_intf_|lrdivider [7]), + .datac(\ula_|i2s_intf_|lrdivider [8]), + .datad(\ula_|i2s_intf_|lrdivider [6]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h4000; +defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h0800; defparam \ula_|i2s_intf_|Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N30 +// Location: LCCOMB_X20_Y31_N2 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~2 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & \ula_|i2s_intf_|Equal0~0_combout ))) +// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Equal0~0_combout & \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ))) .dataa(\ula_|i2s_intf_|Equal0~1_combout ), .datab(\ula_|i2s_intf_|lrdivider [1]), - .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|Equal0~0_combout ), + .datac(\ula_|i2s_intf_|Equal0~0_combout ), + .datad(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~2_combout ), .cout()); @@ -56306,32 +59598,15 @@ defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h2000; defparam \ula_|i2s_intf_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder ( -// Equation(s): -// \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout = \ula_|i2s_intf_|lrclk_r~0_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .lut_mask = 16'hFF00; -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N25 +// Location: FF_X23_Y32_N29 dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|i2s_intf_|lrclk_r~0_combout ), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -56342,7 +59617,7 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N0 +// Location: LCCOMB_X23_Y32_N30 cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|Equal0~2_combout $ (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ) @@ -56397,516 +59672,13 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] -// \ula_|i2s_intf_|bitcount[0]~6 = CARRY(!\ula_|i2s_intf_|bitcount [0]) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [0]), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|bitcount[0]~5_combout ), - .cout(\ula_|i2s_intf_|bitcount[0]~6 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; -defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N11 -dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bclk_r~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & !\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hF0FC; -defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N1 -dffeas \ula_|i2s_intf_|bitcount[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) -// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[0]~6 ), - .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .cout(\ula_|i2s_intf_|bitcount[1]~8 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y22_N3 -dffeas \ula_|i2s_intf_|bitcount[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) -// \ula_|i2s_intf_|bitcount[2]~10 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[1]~8 ), - .combout(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .cout(\ula_|i2s_intf_|bitcount[2]~10 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; -defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y22_N5 -dffeas \ula_|i2s_intf_|bitcount[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N6 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) -// \ula_|i2s_intf_|bitcount[3]~12 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~10 )) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[2]~10 ), - .combout(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .cout(\ula_|i2s_intf_|bitcount[3]~12 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hA505; -defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y22_N7 -dffeas \ula_|i2s_intf_|bitcount[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( -// Equation(s): -// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # (((\ula_|i2s_intf_|bitcount [2]) # (\ula_|i2s_intf_|bitcount [1])) # (!\ula_|i2s_intf_|bitcount [0])) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(\ula_|i2s_intf_|bitcount [0]), - .datac(\ula_|i2s_intf_|bitcount [2]), - .datad(\ula_|i2s_intf_|bitcount [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFFB; -defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [4]), - .datac(gnd), - .datad(gnd), - .cin(\ula_|i2s_intf_|bitcount[3]~12 ), - .combout(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h3C3C; -defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y22_N9 -dffeas \ula_|i2s_intf_|bitcount[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(), - .cout(\ula_|i2s_intf_|Add2~7_cout )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; -defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) -// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) - - .dataa(\ula_|i2s_intf_|bdivider [1]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~7_cout ), - .combout(\ula_|i2s_intf_|Add2~8_combout ), - .cout(\ula_|i2s_intf_|Add2~9 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hA505; -defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Equal1~0_combout ), - .datad(\ula_|i2s_intf_|Add2~8_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h1300; -defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N13 -dffeas \ula_|i2s_intf_|bdivider[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~20_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) -// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) - - .dataa(\ula_|i2s_intf_|bdivider [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~9 ), - .combout(\ula_|i2s_intf_|Add2~10_combout ), - .cout(\ula_|i2s_intf_|Add2~11 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hA55F; -defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add2~10_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h0203; -defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N17 -dffeas \ula_|i2s_intf_|bdivider[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~17_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) -// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~11 ), - .combout(\ula_|i2s_intf_|Add2~12_combout ), - .cout(\ula_|i2s_intf_|Add2~13 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~19_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~12_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Equal1~0_combout ), - .datad(\ula_|i2s_intf_|Add2~12_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h1300; -defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N3 -dffeas \ula_|i2s_intf_|bdivider[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~19_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|bdivider [4]), - .cin(\ula_|i2s_intf_|Add2~13 ), - .combout(\ula_|i2s_intf_|Add2~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; -defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add2~14_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0203; -defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N19 -dffeas \ula_|i2s_intf_|bdivider[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( -// Equation(s): -// \ula_|i2s_intf_|Equal1~0_combout = (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|bdivider [2] & \ula_|i2s_intf_|bdivider [4]))) - - .dataa(\ula_|i2s_intf_|bdivider [1]), - .datab(\ula_|i2s_intf_|bdivider [3]), - .datac(\ula_|i2s_intf_|bdivider [2]), - .datad(\ula_|i2s_intf_|bdivider [4]), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h1000; -defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~1 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[4]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|LessThan0~0_combout ), - .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4]~1 .lut_mask = 16'h8A00; -defparam \ula_|i2s_intf_|shiftreg[4]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N12 +// Location: LCCOMB_X23_Y32_N8 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( // Equation(s): -// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[4]~1_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) +// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(\ula_|i2s_intf_|bdivider [0]), .datad(\ula_|i2s_intf_|Equal1~0_combout ), .cin(gnd), @@ -56917,7 +59689,7 @@ defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1101; defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y22_N13 +// Location: FF_X23_Y32_N9 dffeas \ula_|i2s_intf_|bdivider[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~18_combout ), @@ -56936,54 +59708,574 @@ defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( +// Location: LCCOMB_X24_Y32_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( // Equation(s): -// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|bdivider [0] & \ula_|i2s_intf_|Equal1~0_combout ) +// \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] +// \ula_|i2s_intf_|bitcount[0]~6 = CARRY(!\ula_|i2s_intf_|bitcount [0]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [0]), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|bitcount[0]~5_combout ), + .cout(\ula_|i2s_intf_|bitcount[0]~6 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; +defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder ( +// Equation(s): +// \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout = \ula_|i2s_intf_|bclk_r~1_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|bdivider [0]), + .datac(\ula_|i2s_intf_|bclk_r~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .lut_mask = 16'hF0F0; +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y32_N25 +dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[1]~1_combout )) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datac(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hBABA; +defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y32_N15 +dffeas \ula_|i2s_intf_|bitcount[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) +// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[0]~6 ), + .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .cout(\ula_|i2s_intf_|bitcount[1]~8 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y32_N17 +dffeas \ula_|i2s_intf_|bitcount[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) +// \ula_|i2s_intf_|bitcount[2]~10 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[1]~8 ), + .combout(\ula_|i2s_intf_|bitcount[2]~9_combout ), + .cout(\ula_|i2s_intf_|bitcount[2]~10 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; +defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y32_N19 +dffeas \ula_|i2s_intf_|bitcount[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) +// \ula_|i2s_intf_|bitcount[3]~12 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~10 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[2]~10 ), + .combout(\ula_|i2s_intf_|bitcount[3]~11_combout ), + .cout(\ula_|i2s_intf_|bitcount[3]~12 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y32_N21 +dffeas \ula_|i2s_intf_|bitcount[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) + + .dataa(\ula_|i2s_intf_|bitcount [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2s_intf_|bitcount[3]~12 ), + .combout(\ula_|i2s_intf_|bitcount[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h5A5A; +defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y32_N23 +dffeas \ula_|i2s_intf_|bitcount[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( +// Equation(s): +// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # ((\ula_|i2s_intf_|bitcount [2]) # ((\ula_|i2s_intf_|bitcount [1]) # (!\ula_|i2s_intf_|bitcount [0]))) + + .dataa(\ula_|i2s_intf_|bitcount [3]), + .datab(\ula_|i2s_intf_|bitcount [2]), + .datac(\ula_|i2s_intf_|bitcount [0]), + .datad(\ula_|i2s_intf_|bitcount [1]), + .cin(gnd), + .combout(\ula_|i2s_intf_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFEF; +defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[1]~1 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[1]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Equal1~0_combout ), + .datac(\ula_|i2s_intf_|bitcount [4]), + .datad(\ula_|i2s_intf_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[1]~1 .lut_mask = 16'h8808; +defparam \ula_|i2s_intf_|shiftreg[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\ula_|i2s_intf_|Add2~7_cout )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) +// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~7_cout ), + .combout(\ula_|i2s_intf_|Add2~8_combout ), + .cout(\ula_|i2s_intf_|Add2~9 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Add2~8_combout ), .datad(\ula_|i2s_intf_|Equal1~0_combout ), .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h1030; +defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y32_N5 +dffeas \ula_|i2s_intf_|bdivider[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) +// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~9 ), + .combout(\ula_|i2s_intf_|Add2~10_combout ), + .cout(\ula_|i2s_intf_|Add2~11 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hC33F; +defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) + + .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Add2~10_combout ), + .datad(\ula_|i2s_intf_|Equal1~1_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h1101; +defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y32_N17 +dffeas \ula_|i2s_intf_|bdivider[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~17_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) +// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~11 ), + .combout(\ula_|i2s_intf_|Add2~12_combout ), + .cout(\ula_|i2s_intf_|Add2~13 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~19_combout = (\ula_|i2s_intf_|Add2~12_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Add2~12_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h040C; +defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y32_N15 +dffeas \ula_|i2s_intf_|bdivider[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~19_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|bdivider [4]), + .cin(\ula_|i2s_intf_|Add2~13 ), + .combout(\ula_|i2s_intf_|Add2~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; +defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) + + .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Add2~14_combout ), + .datad(\ula_|i2s_intf_|Equal1~1_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h1101; +defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y32_N7 +dffeas \ula_|i2s_intf_|bdivider[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~0_combout = (\ula_|i2s_intf_|bdivider [4] & (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & \ula_|i2s_intf_|bdivider [2]))) + + .dataa(\ula_|i2s_intf_|bdivider [4]), + .datab(\ula_|i2s_intf_|bdivider [1]), + .datac(\ula_|i2s_intf_|bdivider [3]), + .datad(\ula_|i2s_intf_|bdivider [2]), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h0200; +defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|Equal1~0_combout & \ula_|i2s_intf_|bdivider [0]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal1~0_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|bdivider [0]), + .cin(gnd), .combout(\ula_|i2s_intf_|Equal1~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hF000; +defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hCC00; defparam \ula_|i2s_intf_|Equal1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N14 +// Location: LCCOMB_X24_Y32_N12 cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|bclk_r~0_combout = \ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]))) - .dataa(gnd), - .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .dataa(\ula_|i2s_intf_|LessThan0~0_combout ), + .datab(gnd), .datac(\ula_|i2s_intf_|bitcount [4]), .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), .cin(gnd), .combout(\ula_|i2s_intf_|bclk_r~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h30CF; +defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h50AF; defparam \ula_|i2s_intf_|bclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N10 +// Location: LCCOMB_X24_Y32_N26 cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~1 ( // Equation(s): -// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~0_combout )) # (!\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))))) +// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~0_combout ))) # (!\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )))) .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|bclk_r~0_combout ), - .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|bclk_r~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|bclk_r~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h00D8; +defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h0E04; defparam \ula_|i2s_intf_|bclk_r~1 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57006,15 +60298,15 @@ defparam \ula_|i2s_intf_|bclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N24 +// Location: LCCOMB_X23_Y19_N16 cycloneive_lcell_comb \ula_|pcm_outl[13]~feeder ( // Equation(s): -// \ula_|pcm_outl[13]~feeder_combout = \D[3]~96_combout +// \ula_|pcm_outl[13]~feeder_combout = \D[3]~109_combout .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(\D[3]~96_combout ), + .datad(\D[3]~109_combout ), .cin(gnd), .combout(\ula_|pcm_outl[13]~feeder_combout ), .cout()); @@ -57023,41 +60315,41 @@ defparam \ula_|pcm_outl[13]~feeder .lut_mask = 16'hFF00; defparam \ula_|pcm_outl[13]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N2 +// Location: LCCOMB_X24_Y19_N30 cycloneive_lcell_comb \ula_|always0~2 ( // Equation(s): -// \ula_|always0~2_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) +// \ula_|always0~2_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nRD_out~2_combout )) - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .dataa(gnd), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), + .datad(\z80_|memory_ifc_|nRD_out~2_combout ), .cin(gnd), .combout(\ula_|always0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~2 .lut_mask = 16'h2020; +defparam \ula_|always0~2 .lut_mask = 16'h00C0; defparam \ula_|always0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N20 +// Location: LCCOMB_X23_Y19_N2 cycloneive_lcell_comb \ula_|always0~3 ( // Equation(s): -// \ula_|always0~3_combout = (!\z80_|address_pins_|DFFE_apin_latch [0] & (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~2_combout ))) +// \ula_|always0~3_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [0] & (!\z80_|control_pins_|pin_nIORQ~1_combout & \ula_|always0~2_combout ))) - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|control_pins_|pin_nIORQ~1_combout ), .datad(\ula_|always0~2_combout ), .cin(gnd), .combout(\ula_|always0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~3 .lut_mask = 16'h4000; +defparam \ula_|always0~3 .lut_mask = 16'h0200; defparam \ula_|always0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y19_N25 +// Location: FF_X23_Y19_N17 dffeas \ula_|pcm_outl[13] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|pcm_outl[13]~feeder_combout ), @@ -57076,20 +60368,20 @@ defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N26 +// Location: LCCOMB_X24_Y32_N0 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( // Equation(s): // \ula_|i2s_intf_|shiftreg[0]~19_combout = (\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|LessThan0~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h008A; +defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h2202; defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57103,25 +60395,25 @@ defparam \AUD_ADCDAT~input .bus_hold = "false"; defparam \AUD_ADCDAT~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N20 +// Location: LCCOMB_X23_Y33_N6 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~20 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [0])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\AUD_ADCDAT~input_o ))))) # -// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (((\ula_|i2s_intf_|shiftreg [0])))) +// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|shiftreg [0])))) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\AUD_ADCDAT~input_o ))) # +// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (\ula_|i2s_intf_|shiftreg [0])))) - .dataa(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|shiftreg[0]~19_combout ), .datac(\ula_|i2s_intf_|shiftreg [0]), .datad(\AUD_ADCDAT~input_o ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[0]~20_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF2D0; +defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF4B0; defparam \ula_|i2s_intf_|shiftreg[0]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N21 +// Location: FF_X23_Y33_N7 dffeas \ula_|i2s_intf_|shiftreg[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg[0]~20_combout ), @@ -57140,41 +60432,41 @@ defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N26 +// Location: LCCOMB_X23_Y33_N28 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~18 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~18_combout = (\ula_|i2s_intf_|shiftreg [0] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [0]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [0]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [0]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~2 ( +// Location: LCCOMB_X24_Y32_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[1]~2 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg[4]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & \ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) +// \ula_|i2s_intf_|shiftreg[1]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[1]~1_combout )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datac(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .datad(gnd), .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .combout(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4]~2 .lut_mask = 16'hFCF0; -defparam \ula_|i2s_intf_|shiftreg[4]~2 .sum_lutc_input = "datac"; +defparam \ula_|i2s_intf_|shiftreg[1]~2 .lut_mask = 16'hEAEA; +defparam \ula_|i2s_intf_|shiftreg[1]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N27 +// Location: FF_X23_Y33_N29 dffeas \ula_|i2s_intf_|shiftreg[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~18_combout ), @@ -57183,7 +60475,7 @@ dffeas \ula_|i2s_intf_|shiftreg[1] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [1]), @@ -57193,24 +60485,24 @@ defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N24 +// Location: LCCOMB_X23_Y33_N14 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~17_combout = (\ula_|i2s_intf_|shiftreg [1] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [1]) .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|shiftreg [1]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [1]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N25 +// Location: FF_X23_Y33_N15 dffeas \ula_|i2s_intf_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~17_combout ), @@ -57219,7 +60511,7 @@ dffeas \ula_|i2s_intf_|shiftreg[2] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [2]), @@ -57229,24 +60521,24 @@ defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N18 +// Location: LCCOMB_X23_Y33_N16 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~16_combout = (\ula_|i2s_intf_|shiftreg [2] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), .datab(\ula_|i2s_intf_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N19 +// Location: FF_X23_Y33_N17 dffeas \ula_|i2s_intf_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~16_combout ), @@ -57255,7 +60547,7 @@ dffeas \ula_|i2s_intf_|shiftreg[3] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [3]), @@ -57265,24 +60557,24 @@ defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N0 +// Location: LCCOMB_X23_Y33_N22 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~15_combout = (\ula_|i2s_intf_|shiftreg [3] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~15_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [3]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [3]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [3]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N1 +// Location: FF_X23_Y33_N23 dffeas \ula_|i2s_intf_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~15_combout ), @@ -57291,7 +60583,7 @@ dffeas \ula_|i2s_intf_|shiftreg[4] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [4]), @@ -57301,24 +60593,24 @@ defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N10 +// Location: LCCOMB_X23_Y33_N12 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~14_combout = (\ula_|i2s_intf_|shiftreg [4] & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [4]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|shiftreg [4]), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~14_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h0A0A; defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N11 +// Location: FF_X23_Y33_N13 dffeas \ula_|i2s_intf_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~14_combout ), @@ -57327,7 +60619,7 @@ dffeas \ula_|i2s_intf_|shiftreg[5] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [5]), @@ -57337,24 +60629,24 @@ defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N16 +// Location: LCCOMB_X23_Y33_N18 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~13_combout = (\ula_|i2s_intf_|shiftreg [5] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~13_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [5]) - .dataa(\ula_|i2s_intf_|shiftreg [5]), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [5]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N17 +// Location: FF_X23_Y33_N19 dffeas \ula_|i2s_intf_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~13_combout ), @@ -57363,7 +60655,7 @@ dffeas \ula_|i2s_intf_|shiftreg[6] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [6]), @@ -57373,24 +60665,24 @@ defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N30 +// Location: LCCOMB_X23_Y33_N8 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~12_combout = (\ula_|i2s_intf_|shiftreg [6] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~12_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [6]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [6]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [6]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N31 +// Location: FF_X23_Y33_N9 dffeas \ula_|i2s_intf_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~12_combout ), @@ -57399,7 +60691,7 @@ dffeas \ula_|i2s_intf_|shiftreg[7] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [7]), @@ -57409,24 +60701,24 @@ defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N28 +// Location: LCCOMB_X23_Y33_N2 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~11_combout = (\ula_|i2s_intf_|shiftreg [7] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|shiftreg [7]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|shiftreg [7]), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~11_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N29 +// Location: FF_X23_Y33_N3 dffeas \ula_|i2s_intf_|shiftreg[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~11_combout ), @@ -57435,7 +60727,7 @@ dffeas \ula_|i2s_intf_|shiftreg[8] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [8]), @@ -57445,24 +60737,24 @@ defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N22 +// Location: LCCOMB_X23_Y33_N4 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~10_combout = (\ula_|i2s_intf_|shiftreg [8] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~10_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [8]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [8]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [8]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N23 +// Location: FF_X23_Y33_N5 dffeas \ula_|i2s_intf_|shiftreg[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~10_combout ), @@ -57471,7 +60763,7 @@ dffeas \ula_|i2s_intf_|shiftreg[9] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [9]), @@ -57481,24 +60773,24 @@ defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N12 +// Location: LCCOMB_X23_Y33_N10 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [9] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|shiftreg [9]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|shiftreg [9]), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N13 +// Location: FF_X23_Y33_N11 dffeas \ula_|i2s_intf_|shiftreg[10] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~9_combout ), @@ -57507,7 +60799,7 @@ dffeas \ula_|i2s_intf_|shiftreg[10] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [10]), @@ -57517,24 +60809,24 @@ defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N2 +// Location: LCCOMB_X23_Y33_N0 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~8_combout = (\ula_|i2s_intf_|shiftreg [10] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~8_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [10]) - .dataa(\ula_|i2s_intf_|shiftreg [10]), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [10]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N3 +// Location: FF_X23_Y33_N1 dffeas \ula_|i2s_intf_|shiftreg[11] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~8_combout ), @@ -57543,7 +60835,7 @@ dffeas \ula_|i2s_intf_|shiftreg[11] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [11]), @@ -57553,24 +60845,24 @@ defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N8 +// Location: LCCOMB_X23_Y33_N26 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~7_combout = (\ula_|i2s_intf_|shiftreg [11] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~7_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [11]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [11]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [11]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N9 +// Location: FF_X23_Y33_N27 dffeas \ula_|i2s_intf_|shiftreg[12] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~7_combout ), @@ -57579,7 +60871,7 @@ dffeas \ula_|i2s_intf_|shiftreg[12] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [12]), @@ -57589,7 +60881,7 @@ defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N30 +// Location: LCCOMB_X23_Y32_N10 cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( // Equation(s): // \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INR [14]))))) # @@ -57607,7 +60899,7 @@ defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hB8F0; defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N31 +// Location: FF_X23_Y32_N11 dffeas \ula_|i2s_intf_|PCM_INR[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), @@ -57626,7 +60918,7 @@ defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N28 +// Location: LCCOMB_X23_Y32_N12 cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INL[14]~0 ( // Equation(s): // \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INL [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])))) # @@ -57644,7 +60936,7 @@ defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF0B8; defparam \ula_|i2s_intf_|PCM_INL[14]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N29 +// Location: FF_X23_Y32_N13 dffeas \ula_|i2s_intf_|PCM_INL[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), @@ -57663,24 +60955,24 @@ defparam \ula_|i2s_intf_|PCM_INL[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|PCM_INL[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N6 +// Location: LCCOMB_X23_Y32_N0 cycloneive_lcell_comb \ula_|pcm_outr~0 ( // Equation(s): // \ula_|pcm_outr~0_combout = (\ula_|i2s_intf_|PCM_INR [14]) # (\ula_|i2s_intf_|PCM_INL [14]) - .dataa(gnd), + .dataa(\ula_|i2s_intf_|PCM_INR [14]), .datab(gnd), - .datac(\ula_|i2s_intf_|PCM_INR [14]), + .datac(gnd), .datad(\ula_|i2s_intf_|PCM_INL [14]), .cin(gnd), .combout(\ula_|pcm_outr~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFF0; +defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFAA; defparam \ula_|pcm_outr~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N7 +// Location: FF_X23_Y32_N1 dffeas \ula_|pcm_outl[12] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|pcm_outr~0_combout ), @@ -57699,24 +60991,24 @@ defparam \ula_|pcm_outl[12] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N14 +// Location: LCCOMB_X23_Y33_N20 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~6 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [12]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [12])) - .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg [12]), + .dataa(\ula_|i2s_intf_|shiftreg [12]), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), .datad(\ula_|pcm_outl [12]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFC30; +defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFA0A; defparam \ula_|i2s_intf_|shiftreg~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N15 +// Location: FF_X23_Y33_N21 dffeas \ula_|i2s_intf_|shiftreg[13] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~6_combout ), @@ -57725,7 +61017,7 @@ dffeas \ula_|i2s_intf_|shiftreg[13] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [13]), @@ -57735,24 +61027,24 @@ defparam \ula_|i2s_intf_|shiftreg[13] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N4 +// Location: LCCOMB_X23_Y33_N30 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) .dataa(gnd), .datab(\ula_|pcm_outl [13]), - .datac(\ula_|i2s_intf_|shiftreg [13]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [13]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hCCF0; +defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hCFC0; defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N5 +// Location: FF_X23_Y33_N31 dffeas \ula_|i2s_intf_|shiftreg[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~5_combout ), @@ -57761,7 +61053,7 @@ dffeas \ula_|i2s_intf_|shiftreg[14] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [14]), @@ -57771,10 +61063,27 @@ defparam \ula_|i2s_intf_|shiftreg[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[14] .power_up = "low"; // synopsys translate_on -// Location: FF_X29_Y14_N31 +// Location: LCCOMB_X23_Y19_N22 +cycloneive_lcell_comb \ula_|pcm_outl[14]~feeder ( +// Equation(s): +// \ula_|pcm_outl[14]~feeder_combout = \D[4]~111_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\D[4]~111_combout ), + .cin(gnd), + .combout(\ula_|pcm_outl[14]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|pcm_outl[14]~feeder .lut_mask = 16'hFF00; +defparam \ula_|pcm_outl[14]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N23 dffeas \ula_|pcm_outl[14] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\D[4]~98_combout ), + .d(\ula_|pcm_outl[14]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -57790,24 +61099,24 @@ defparam \ula_|pcm_outl[14] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y22_N4 +// Location: LCCOMB_X23_Y33_N24 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~4 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) .dataa(\ula_|i2s_intf_|shiftreg [14]), .datab(gnd), - .datac(\ula_|pcm_outl [14]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|pcm_outl [14]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hF0AA; +defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hFA0A; defparam \ula_|i2s_intf_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y22_N5 +// Location: FF_X23_Y33_N25 dffeas \ula_|i2s_intf_|shiftreg[15] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~4_combout ), @@ -57816,7 +61125,7 @@ dffeas \ula_|i2s_intf_|shiftreg[15] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [15]), @@ -57826,24 +61135,24 @@ defparam \ula_|i2s_intf_|shiftreg[15] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y22_N0 +// Location: LCCOMB_X20_Y33_N0 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~3 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~3_combout = (\ula_|i2s_intf_|shiftreg [15] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~3_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [15]) .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|shiftreg [15]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [15]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h3300; defparam \ula_|i2s_intf_|shiftreg~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y22_N1 +// Location: FF_X20_Y33_N1 dffeas \ula_|i2s_intf_|shiftreg[16] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~3_combout ), @@ -57852,7 +61161,7 @@ dffeas \ula_|i2s_intf_|shiftreg[16] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [16]), @@ -57862,20 +61171,20 @@ defparam \ula_|i2s_intf_|shiftreg[16] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y22_N10 +// Location: LCCOMB_X20_Y33_N14 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~0 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~0_combout = (\ula_|i2s_intf_|shiftreg [16] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [16]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [16]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [16]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h3300; defparam \ula_|i2s_intf_|shiftreg~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57888,7 +61197,7 @@ dffeas \ula_|i2s_intf_|shiftreg[17] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [17]), @@ -57898,135 +61207,32 @@ defparam \ula_|i2s_intf_|shiftreg[17] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N8 -cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Location: LCCOMB_X27_Y18_N12 +cycloneive_lcell_comb \ula_|border[1]~feeder ( // Equation(s): -// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [6]))) +// \ula_|border[1]~feeder_combout = \D[1]~41_combout - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|vga_vc [8]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [6]), - .cin(gnd), - .combout(\ula_|video_|LessThan2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N4 -cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( -// Equation(s): -// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) - - .dataa(\ula_|video_|vga_vc [2]), - .datab(\ula_|video_|vga_vc [3]), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|LessThan6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0111; -defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N30 -cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( -// Equation(s): -// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(\ula_|video_|vga_vc [4]), - .datac(\ula_|video_|LessThan2~0_combout ), - .datad(\ula_|video_|LessThan6~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan2~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7050; -defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N16 -cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( -// Equation(s): -// \ula_|video_|LessThan3~0_combout = ((\ula_|video_|LessThan6~0_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) # (!\ula_|video_|vga_vc [9]) - - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|LessThan6~0_combout ), - .datac(\ula_|video_|vga_vc [5]), - .datad(\ula_|video_|Equal2~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h5D55; -defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N22 -cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( -// Equation(s): -// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [6] & !\ula_|video_|vga_hc [5])) - - .dataa(\ula_|video_|vga_hc [4]), - .datab(\ula_|video_|vga_hc [6]), + .dataa(gnd), + .datab(gnd), .datac(gnd), - .datad(\ula_|video_|vga_hc [5]), + .datad(\D[1]~41_combout ), .cin(gnd), - .combout(\ula_|video_|LessThan0~0_combout ), + .combout(\ula_|border[1]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0011; -defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; +defparam \ula_|border[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|border[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N24 -cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( -// Equation(s): -// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((\ula_|video_|LessThan0~0_combout & !\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # -// ((!\ula_|video_|LessThan0~0_combout & \ula_|video_|vga_hc [7])))) - - .dataa(\ula_|video_|LessThan0~0_combout ), - .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|vga_hc [7]), - .datad(\ula_|video_|vga_hc [9]), - .cin(gnd), - .combout(\ula_|video_|disp_enable~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h3BDC; -defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N2 -cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( -// Equation(s): -// \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) - - .dataa(\ula_|video_|LessThan2~1_combout ), - .datab(\ula_|video_|LessThan3~0_combout ), - .datac(gnd), - .datad(\ula_|video_|disp_enable~0_combout ), - .cin(gnd), - .combout(\ula_|video_|disp_enable~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h4400; -defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N11 +// Location: FF_X27_Y18_N13 dffeas \ula_|border[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\D[1]~34_combout ), + .d(\ula_|border[1]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58037,58 +61243,75 @@ defparam \ula_|border[1] .is_wysiwyg = "true"; defparam \ula_|border[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N8 +// Location: LCCOMB_X32_Y30_N28 +cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( +// Equation(s): +// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) + + .dataa(\ula_|video_|vga_vc [1]), + .datab(\ula_|video_|vga_vc [2]), + .datac(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|vga_vc [0]), + .cin(gnd), + .combout(\ula_|video_|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0103; +defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N14 cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( // Equation(s): // \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) - .dataa(\ula_|video_|vga_vc [6]), + .dataa(\ula_|video_|vga_vc [4]), .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|vga_vc [4]), + .datac(\ula_|video_|vga_vc [6]), .datad(\ula_|video_|LessThan6~0_combout ), .cin(gnd), .combout(\ula_|video_|LessThan6~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h7757; +defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h3F1F; defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N28 +// Location: LCCOMB_X29_Y30_N6 cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( // Equation(s): -// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) +// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [5] & !\ula_|video_|vga_hc [4])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) - .dataa(\ula_|video_|vga_hc [4]), - .datab(\ula_|video_|vga_hc [5]), - .datac(\ula_|video_|vga_hc [6]), + .dataa(\ula_|video_|vga_hc [5]), + .datab(\ula_|video_|vga_hc [6]), + .datac(\ula_|video_|vga_hc [4]), .datad(\ula_|video_|vga_hc [7]), .cin(gnd), .combout(\ula_|video_|LessThan4~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h1FFF; +defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h37FF; defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N10 +// Location: LCCOMB_X31_Y30_N10 cycloneive_lcell_comb \ula_|video_|screen_en~0 ( // Equation(s): // \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) - .dataa(\ula_|video_|vga_hc [9]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|LessThan4~0_combout ), - .datad(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|vga_hc [9]), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|LessThan4~0_combout ), .cin(gnd), .combout(\ula_|video_|screen_en~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1121; +defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1411; defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N22 +// Location: LCCOMB_X31_Y30_N24 cycloneive_lcell_comb \ula_|video_|screen_en~1 ( // Equation(s): // \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # @@ -58106,151 +61329,7 @@ defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE700; defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N28 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N10 -cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( -// Equation(s): -// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h0080; -defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N29 -dffeas \ula_|video_|attr_prefetch[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N12 -cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( -// Equation(s): -// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & \ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; -defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y33_N27 -dffeas \ula_|video_|attr[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N10 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N11 -dffeas \ula_|video_|attr_prefetch[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y33_N13 -dffeas \ula_|video_|attr[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N24 +// Location: LCCOMB_X30_Y28_N0 cycloneive_lcell_comb \ula_|video_|attr_prefetch[7]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 @@ -58267,7 +61346,24 @@ defparam \ula_|video_|attr_prefetch[7]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N25 +// Location: LCCOMB_X30_Y29_N20 +cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( +// Equation(s): +// \ula_|video_|Decoder0~1_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & \ula_|video_|vga_hc [1]))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h4000; +defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N1 dffeas \ula_|video_|attr_prefetch[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[7]~feeder_combout ), @@ -58286,7 +61382,24 @@ defparam \ula_|video_|attr_prefetch[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[7] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N5 +// Location: LCCOMB_X30_Y29_N10 +cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( +// Equation(s): +// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & \ula_|video_|vga_hc [1]))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; +defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y30_N7 dffeas \ula_|video_|attr[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58305,32 +61418,32 @@ defparam \ula_|video_|attr[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y33_N22 +// Location: LCCOMB_X34_Y30_N4 cycloneive_lcell_comb \ula_|video_|frame[0]~12 ( // Equation(s): // \ula_|video_|frame[0]~12_combout = \ula_|video_|Equal3~1_combout $ (\ula_|video_|frame [0]) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(gnd), - .datac(\ula_|video_|frame [0]), - .datad(gnd), + .dataa(gnd), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(gnd), + .datad(\ula_|video_|frame [0]), .cin(gnd), .combout(\ula_|video_|frame[0]~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h5A5A; +defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h33CC; defparam \ula_|video_|frame[0]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y33_N23 +// Location: FF_X34_Y30_N21 dffeas \ula_|video_|frame[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[0]~12_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|frame[0]~12_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -58341,14 +61454,14 @@ defparam \ula_|video_|frame[0] .is_wysiwyg = "true"; defparam \ula_|video_|frame[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N24 +// Location: LCCOMB_X34_Y30_N14 cycloneive_lcell_comb \ula_|video_|frame[1]~4 ( // Equation(s): -// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [0] & (\ula_|video_|frame [1] $ (VCC))) # (!\ula_|video_|frame [0] & (\ula_|video_|frame [1] & VCC)) -// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [0] & \ula_|video_|frame [1])) +// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [1] & (\ula_|video_|frame [0] $ (VCC))) # (!\ula_|video_|frame [1] & (\ula_|video_|frame [0] & VCC)) +// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [1] & \ula_|video_|frame [0])) - .dataa(\ula_|video_|frame [0]), - .datab(\ula_|video_|frame [1]), + .dataa(\ula_|video_|frame [1]), + .datab(\ula_|video_|frame [0]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -58359,7 +61472,7 @@ defparam \ula_|video_|frame[1]~4 .lut_mask = 16'h6688; defparam \ula_|video_|frame[1]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y33_N25 +// Location: FF_X34_Y30_N15 dffeas \ula_|video_|frame[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[1]~4_combout ), @@ -58378,25 +61491,25 @@ defparam \ula_|video_|frame[1] .is_wysiwyg = "true"; defparam \ula_|video_|frame[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N26 +// Location: LCCOMB_X34_Y30_N16 cycloneive_lcell_comb \ula_|video_|frame[2]~6 ( // Equation(s): // \ula_|video_|frame[2]~6_combout = (\ula_|video_|frame [2] & (!\ula_|video_|frame[1]~5 )) # (!\ula_|video_|frame [2] & ((\ula_|video_|frame[1]~5 ) # (GND))) // \ula_|video_|frame[2]~7 = CARRY((!\ula_|video_|frame[1]~5 ) # (!\ula_|video_|frame [2])) - .dataa(\ula_|video_|frame [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|frame [2]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|frame[1]~5 ), .combout(\ula_|video_|frame[2]~6_combout ), .cout(\ula_|video_|frame[2]~7 )); // synopsys translate_off -defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h3C3F; defparam \ula_|video_|frame[2]~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N27 +// Location: FF_X34_Y30_N17 dffeas \ula_|video_|frame[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[2]~6_combout ), @@ -58415,7 +61528,7 @@ defparam \ula_|video_|frame[2] .is_wysiwyg = "true"; defparam \ula_|video_|frame[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N28 +// Location: LCCOMB_X34_Y30_N18 cycloneive_lcell_comb \ula_|video_|frame[3]~8 ( // Equation(s): // \ula_|video_|frame[3]~8_combout = (\ula_|video_|frame [3] & (\ula_|video_|frame[2]~7 $ (GND))) # (!\ula_|video_|frame [3] & (!\ula_|video_|frame[2]~7 & VCC)) @@ -58433,7 +61546,7 @@ defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hC30C; defparam \ula_|video_|frame[3]~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N29 +// Location: FF_X34_Y30_N19 dffeas \ula_|video_|frame[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[3]~8_combout ), @@ -58452,32 +61565,32 @@ defparam \ula_|video_|frame[3] .is_wysiwyg = "true"; defparam \ula_|video_|frame[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N30 +// Location: LCCOMB_X34_Y30_N20 cycloneive_lcell_comb \ula_|video_|frame[4]~10 ( // Equation(s): -// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame [4] $ (\ula_|video_|frame[3]~9 ) +// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame[3]~9 $ (\ula_|video_|frame [4]) - .dataa(\ula_|video_|frame [4]), + .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|video_|frame [4]), .cin(\ula_|video_|frame[3]~9 ), .combout(\ula_|video_|frame[4]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h5A5A; +defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h0FF0; defparam \ula_|video_|frame[4]~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N31 +// Location: FF_X34_Y30_N5 dffeas \ula_|video_|frame[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[4]~10_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|frame[4]~10_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|video_|Equal3~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58488,7 +61601,7 @@ defparam \ula_|video_|frame[4] .is_wysiwyg = "true"; defparam \ula_|video_|frame[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N4 +// Location: LCCOMB_X30_Y30_N6 cycloneive_lcell_comb \ula_|video_|inverted ( // Equation(s): // \ula_|video_|inverted~combout = (\ula_|video_|attr [7] & \ula_|video_|frame [4]) @@ -58505,7 +61618,7 @@ defparam \ula_|video_|inverted .lut_mask = 16'hF000; defparam \ula_|video_|inverted .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N12 +// Location: LCCOMB_X30_Y28_N28 cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 @@ -58522,24 +61635,24 @@ defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N8 +// Location: LCCOMB_X30_Y29_N14 cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( // Equation(s): -// \ula_|video_|Decoder0~2_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) +// \ula_|video_|Decoder0~2_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [1]))) - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), .cin(gnd), .combout(\ula_|video_|Decoder0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0008; +defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0040; defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N13 +// Location: FF_X30_Y28_N29 dffeas \ula_|video_|bits_prefetch[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), @@ -58558,32 +61671,15 @@ defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N6 -cycloneive_lcell_comb \ula_|video_|bits[6]~feeder ( -// Equation(s): -// \ula_|video_|bits[6]~feeder_combout = \ula_|video_|bits_prefetch [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|bits_prefetch [6]), - .cin(gnd), - .combout(\ula_|video_|bits[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y33_N7 +// Location: FF_X30_Y30_N5 dffeas \ula_|video_|bits[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits[6]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [6]), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58594,7 +61690,7 @@ defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; defparam \ula_|video_|bits[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N22 +// Location: LCCOMB_X30_Y28_N26 cycloneive_lcell_comb \ula_|video_|bits_prefetch[4]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 @@ -58611,7 +61707,7 @@ defparam \ula_|video_|bits_prefetch[4]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[4]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N23 +// Location: FF_X30_Y28_N27 dffeas \ula_|video_|bits_prefetch[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[4]~feeder_combout ), @@ -58630,7 +61726,7 @@ defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N23 +// Location: FF_X30_Y30_N29 dffeas \ula_|video_|bits[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58649,7 +61745,7 @@ defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; defparam \ula_|video_|bits[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N18 +// Location: LCCOMB_X30_Y28_N14 cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 @@ -58666,7 +61762,7 @@ defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N19 +// Location: FF_X30_Y28_N15 dffeas \ula_|video_|bits_prefetch[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), @@ -58685,7 +61781,7 @@ defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N18 +// Location: LCCOMB_X30_Y30_N24 cycloneive_lcell_comb \ula_|video_|bits[5]~feeder ( // Equation(s): // \ula_|video_|bits[5]~feeder_combout = \ula_|video_|bits_prefetch [5] @@ -58702,7 +61798,7 @@ defparam \ula_|video_|bits[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N19 +// Location: FF_X30_Y30_N25 dffeas \ula_|video_|bits[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[5]~feeder_combout ), @@ -58721,7 +61817,7 @@ defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; defparam \ula_|video_|bits[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N0 +// Location: LCCOMB_X30_Y28_N12 cycloneive_lcell_comb \ula_|video_|bits_prefetch[7]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 @@ -58738,7 +61834,7 @@ defparam \ula_|video_|bits_prefetch[7]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N1 +// Location: FF_X30_Y28_N13 dffeas \ula_|video_|bits_prefetch[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[7]~feeder_combout ), @@ -58757,7 +61853,7 @@ defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N1 +// Location: FF_X30_Y30_N19 dffeas \ula_|video_|bits[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58776,41 +61872,41 @@ defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; defparam \ula_|video_|bits[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N0 +// Location: LCCOMB_X30_Y30_N18 cycloneive_lcell_comb \ula_|video_|Mux0~0 ( // Equation(s): // \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [5])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [7]))))) - .dataa(\ula_|video_|bits [5]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [5]), .datac(\ula_|video_|bits [7]), .datad(\ula_|video_|vga_hc [2]), .cin(gnd), .combout(\ula_|video_|Mux0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE30; +defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE50; defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N22 +// Location: LCCOMB_X30_Y30_N28 cycloneive_lcell_comb \ula_|video_|Mux0~1 ( // Equation(s): // \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) - .dataa(\ula_|video_|bits [6]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [6]), .datac(\ula_|video_|bits [4]), .datad(\ula_|video_|Mux0~0_combout ), .cin(gnd), .combout(\ula_|video_|Mux0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF388; +defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF588; defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N16 +// Location: LCCOMB_X30_Y28_N20 cycloneive_lcell_comb \ula_|video_|bits_prefetch[2]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 @@ -58827,7 +61923,7 @@ defparam \ula_|video_|bits_prefetch[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N17 +// Location: FF_X30_Y28_N21 dffeas \ula_|video_|bits_prefetch[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[2]~feeder_combout ), @@ -58846,7 +61942,7 @@ defparam \ula_|video_|bits_prefetch[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N12 +// Location: LCCOMB_X30_Y30_N14 cycloneive_lcell_comb \ula_|video_|bits[2]~feeder ( // Equation(s): // \ula_|video_|bits[2]~feeder_combout = \ula_|video_|bits_prefetch [2] @@ -58863,7 +61959,7 @@ defparam \ula_|video_|bits[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N13 +// Location: FF_X30_Y30_N15 dffeas \ula_|video_|bits[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[2]~feeder_combout ), @@ -58882,7 +61978,7 @@ defparam \ula_|video_|bits[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N14 +// Location: LCCOMB_X30_Y28_N18 cycloneive_lcell_comb \ula_|video_|bits_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -58899,7 +61995,7 @@ defparam \ula_|video_|bits_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N15 +// Location: FF_X30_Y28_N19 dffeas \ula_|video_|bits_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[0]~feeder_combout ), @@ -58918,7 +62014,7 @@ defparam \ula_|video_|bits_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N3 +// Location: FF_X30_Y30_N1 dffeas \ula_|video_|bits[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58937,7 +62033,7 @@ defparam \ula_|video_|bits[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N6 +// Location: LCCOMB_X30_Y28_N6 cycloneive_lcell_comb \ula_|video_|bits_prefetch[1]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 @@ -58954,7 +62050,7 @@ defparam \ula_|video_|bits_prefetch[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N7 +// Location: FF_X30_Y28_N7 dffeas \ula_|video_|bits_prefetch[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[1]~feeder_combout ), @@ -58973,7 +62069,7 @@ defparam \ula_|video_|bits_prefetch[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N26 +// Location: LCCOMB_X30_Y30_N20 cycloneive_lcell_comb \ula_|video_|bits[1]~feeder ( // Equation(s): // \ula_|video_|bits[1]~feeder_combout = \ula_|video_|bits_prefetch [1] @@ -58990,7 +62086,7 @@ defparam \ula_|video_|bits[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N27 +// Location: FF_X30_Y30_N21 dffeas \ula_|video_|bits[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[1]~feeder_combout ), @@ -59009,7 +62105,7 @@ defparam \ula_|video_|bits[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N4 +// Location: LCCOMB_X30_Y28_N24 cycloneive_lcell_comb \ula_|video_|bits_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 @@ -59026,7 +62122,7 @@ defparam \ula_|video_|bits_prefetch[3]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N5 +// Location: FF_X30_Y28_N25 dffeas \ula_|video_|bits_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[3]~feeder_combout ), @@ -59045,7 +62141,7 @@ defparam \ula_|video_|bits_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N25 +// Location: FF_X30_Y30_N3 dffeas \ula_|video_|bits[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59064,92 +62160,305 @@ defparam \ula_|video_|bits[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N24 +// Location: LCCOMB_X30_Y30_N2 cycloneive_lcell_comb \ula_|video_|Mux0~2 ( // Equation(s): // \ula_|video_|Mux0~2_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [1])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [3]))))) - .dataa(\ula_|video_|bits [1]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [1]), .datac(\ula_|video_|bits [3]), .datad(\ula_|video_|vga_hc [2]), .cin(gnd), .combout(\ula_|video_|Mux0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE30; +defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE50; defparam \ula_|video_|Mux0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N2 +// Location: LCCOMB_X30_Y30_N0 cycloneive_lcell_comb \ula_|video_|Mux0~3 ( // Equation(s): // \ula_|video_|Mux0~3_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~2_combout & ((\ula_|video_|bits [0]))) # (!\ula_|video_|Mux0~2_combout & (\ula_|video_|bits [2])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~2_combout )))) - .dataa(\ula_|video_|bits [2]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [2]), .datac(\ula_|video_|bits [0]), .datad(\ula_|video_|Mux0~2_combout ), .cin(gnd), .combout(\ula_|video_|Mux0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF388; +defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF588; defparam \ula_|video_|Mux0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N10 -cycloneive_lcell_comb \ula_|video_|cindex[1]~0 ( +// Location: LCCOMB_X30_Y30_N10 +cycloneive_lcell_comb \ula_|video_|cindex[2]~0 ( // Equation(s): -// \ula_|video_|cindex[1]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~3_combout ))) # (!\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~1_combout )))) +// \ula_|video_|cindex[2]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~3_combout ))) # (!\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~1_combout )))) - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|inverted~combout ), - .datac(\ula_|video_|Mux0~1_combout ), + .dataa(\ula_|video_|inverted~combout ), + .datab(\ula_|video_|Mux0~1_combout ), + .datac(\ula_|video_|vga_hc [3]), .datad(\ula_|video_|Mux0~3_combout ), .cin(gnd), - .combout(\ula_|video_|cindex[1]~0_combout ), + .combout(\ula_|video_|cindex[2]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h369C; -defparam \ula_|video_|cindex[1]~0 .sum_lutc_input = "datac"; +defparam \ula_|video_|cindex[2]~0 .lut_mask = 16'h56A6; +defparam \ula_|video_|cindex[2]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N12 +// Location: LCCOMB_X30_Y28_N10 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N11 +dffeas \ula_|video_|attr_prefetch[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y30_N17 +dffeas \ula_|video_|attr[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y28_N4 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N5 +dffeas \ula_|video_|attr_prefetch[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y30_N19 +dffeas \ula_|video_|attr[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y30_N16 cycloneive_lcell_comb \ula_|video_|cindex[1]~1 ( // Equation(s): -// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [1])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [4]))) +// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [1]))) # (!\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [4])) - .dataa(\ula_|video_|attr [1]), + .dataa(\ula_|video_|cindex[2]~0_combout ), .datab(gnd), .datac(\ula_|video_|attr [4]), - .datad(\ula_|video_|cindex[1]~0_combout ), + .datad(\ula_|video_|attr [1]), .cin(gnd), .combout(\ula_|video_|cindex[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hAAF0; +defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hFA50; defparam \ula_|video_|cindex[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N24 +// Location: LCCOMB_X31_Y30_N4 +cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Equation(s): +// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) + + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|vga_vc [6]), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|vga_vc [8]), + .cin(gnd), + .combout(\ula_|video_|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N2 +cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( +// Equation(s): +// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|vga_vc [5]), + .datac(\ula_|video_|LessThan2~0_combout ), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7030; +defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N14 +cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( +// Equation(s): +// \ula_|video_|LessThan3~0_combout = ((!\ula_|video_|vga_vc [5] & (\ula_|video_|Equal2~0_combout & \ula_|video_|LessThan6~0_combout ))) # (!\ula_|video_|vga_vc [9]) + + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|vga_vc [5]), + .datac(\ula_|video_|Equal2~0_combout ), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h7555; +defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N0 +cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( +// Equation(s): +// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [5] & !\ula_|video_|vga_hc [6])) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(gnd), + .datac(\ula_|video_|vga_hc [5]), + .datad(\ula_|video_|vga_hc [6]), + .cin(gnd), + .combout(\ula_|video_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0005; +defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N4 +cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( +// Equation(s): +// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((!\ula_|video_|vga_hc [7] & \ula_|video_|LessThan0~0_combout )) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # ((\ula_|video_|vga_hc [7] & +// !\ula_|video_|LessThan0~0_combout )))) + + .dataa(\ula_|video_|vga_hc [7]), + .datab(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [9]), + .datad(\ula_|video_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|video_|disp_enable~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h7C3E; +defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N12 +cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( +// Equation(s): +// \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) + + .dataa(gnd), + .datab(\ula_|video_|LessThan2~1_combout ), + .datac(\ula_|video_|LessThan3~0_combout ), + .datad(\ula_|video_|disp_enable~0_combout ), + .cin(gnd), + .combout(\ula_|video_|disp_enable~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h3000; +defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N26 cycloneive_lcell_comb \ula_|video_|VGA_R[0]~0 ( // Equation(s): // \ula_|video_|VGA_R[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[1]~1_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [1])))) - .dataa(\ula_|video_|disp_enable~1_combout ), - .datab(\ula_|border [1]), - .datac(\ula_|video_|screen_en~1_combout ), - .datad(\ula_|video_|cindex[1]~1_combout ), + .dataa(\ula_|border [1]), + .datab(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|cindex[1]~1_combout ), + .datad(\ula_|video_|disp_enable~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hA808; +defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hE200; defparam \ula_|video_|VGA_R[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N26 +// Location: LCCOMB_X30_Y28_N22 cycloneive_lcell_comb \ula_|video_|attr_prefetch[6]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 @@ -59166,7 +62475,7 @@ defparam \ula_|video_|attr_prefetch[6]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N27 +// Location: FF_X30_Y28_N23 dffeas \ula_|video_|attr_prefetch[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[6]~feeder_combout ), @@ -59185,7 +62494,7 @@ defparam \ula_|video_|attr_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X38_Y33_N1 +// Location: FF_X31_Y30_N29 dffeas \ula_|video_|attr[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59204,49 +62513,66 @@ defparam \ula_|video_|attr[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N0 +// Location: LCCOMB_X31_Y30_N28 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~0 ( // Equation(s): -// \ula_|video_|VGA_B[1]~0_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & (\ula_|video_|attr [6] & \ula_|video_|disp_enable~0_combout ))) +// \ula_|video_|VGA_B[1]~0_combout = (\ula_|video_|LessThan3~0_combout & (\ula_|video_|disp_enable~0_combout & (\ula_|video_|attr [6] & !\ula_|video_|LessThan2~1_combout ))) - .dataa(\ula_|video_|LessThan2~1_combout ), - .datab(\ula_|video_|LessThan3~0_combout ), + .dataa(\ula_|video_|LessThan3~0_combout ), + .datab(\ula_|video_|disp_enable~0_combout ), .datac(\ula_|video_|attr [6]), - .datad(\ula_|video_|disp_enable~0_combout ), + .datad(\ula_|video_|LessThan2~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h4000; +defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h0080; defparam \ula_|video_|VGA_B[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N2 +// Location: LCCOMB_X31_Y30_N6 cycloneive_lcell_comb \ula_|video_|VGA_R[1]~1 ( // Equation(s): -// \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[1]~1_combout )) +// \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[1]~1_combout )) - .dataa(\ula_|video_|screen_en~1_combout ), - .datab(gnd), - .datac(\ula_|video_|VGA_B[1]~0_combout ), - .datad(\ula_|video_|cindex[1]~1_combout ), + .dataa(\ula_|video_|VGA_B[1]~0_combout ), + .datab(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|cindex[1]~1_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|VGA_R[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'hA000; +defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'h8080; defparam \ula_|video_|VGA_R[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y12_N17 +// Location: LCCOMB_X30_Y27_N20 +cycloneive_lcell_comb \ula_|border[2]~feeder ( +// Equation(s): +// \ula_|border[2]~feeder_combout = \D[2]~53_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\D[2]~53_combout ), + .cin(gnd), + .combout(\ula_|border[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|border[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|border[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y27_N21 dffeas \ula_|border[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\D[2]~46_combout ), + .d(\ula_|border[2]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -59257,62 +62583,7 @@ defparam \ula_|border[2] .is_wysiwyg = "true"; defparam \ula_|border[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N8 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N9 -dffeas \ula_|video_|attr_prefetch[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y33_N21 -dffeas \ula_|video_|attr[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N30 +// Location: LCCOMB_X30_Y28_N30 cycloneive_lcell_comb \ula_|video_|attr_prefetch[5]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 @@ -59329,7 +62600,7 @@ defparam \ula_|video_|attr_prefetch[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N31 +// Location: FF_X30_Y28_N31 dffeas \ula_|video_|attr_prefetch[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[5]~feeder_combout ), @@ -59348,7 +62619,7 @@ defparam \ula_|video_|attr_prefetch[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[5] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N15 +// Location: FF_X30_Y30_N31 dffeas \ula_|video_|attr[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59367,66 +62638,138 @@ defparam \ula_|video_|attr[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N14 -cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( +// Location: LCCOMB_X30_Y28_N16 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( // Equation(s): -// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [2])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [5]))) +// \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 .dataa(gnd), - .datab(\ula_|video_|attr [2]), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N17 +dffeas \ula_|video_|attr_prefetch[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y30_N13 +dffeas \ula_|video_|attr[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y30_N30 +cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( +// Equation(s): +// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [2]))) # (!\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [5])) + + .dataa(\ula_|video_|cindex[2]~0_combout ), + .datab(gnd), .datac(\ula_|video_|attr [5]), - .datad(\ula_|video_|cindex[1]~0_combout ), + .datad(\ula_|video_|attr [2]), .cin(gnd), .combout(\ula_|video_|cindex[2]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hCCF0; +defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hFA50; defparam \ula_|video_|cindex[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N26 +// Location: LCCOMB_X31_Y30_N0 cycloneive_lcell_comb \ula_|video_|VGA_G[0]~0 ( // Equation(s): // \ula_|video_|VGA_G[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[2]~2_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [2])))) - .dataa(\ula_|border [2]), + .dataa(\ula_|video_|disp_enable~1_combout ), .datab(\ula_|video_|screen_en~1_combout ), - .datac(\ula_|video_|disp_enable~1_combout ), + .datac(\ula_|border [2]), .datad(\ula_|video_|cindex[2]~2_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hE020; +defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hA820; defparam \ula_|video_|VGA_G[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N20 +// Location: LCCOMB_X31_Y30_N18 cycloneive_lcell_comb \ula_|video_|VGA_G[1]~1 ( // Equation(s): -// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|cindex[2]~2_combout & \ula_|video_|screen_en~1_combout )) +// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[2]~2_combout )) .dataa(\ula_|video_|VGA_B[1]~0_combout ), - .datab(\ula_|video_|cindex[2]~2_combout ), - .datac(gnd), - .datad(\ula_|video_|screen_en~1_combout ), + .datab(gnd), + .datac(\ula_|video_|screen_en~1_combout ), + .datad(\ula_|video_|cindex[2]~2_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_G[1]~1 .lut_mask = 16'h8800; +defparam \ula_|video_|VGA_G[1]~1 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_G[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N1 +// Location: LCCOMB_X26_Y15_N4 +cycloneive_lcell_comb \ula_|border[0]~feeder ( +// Equation(s): +// \ula_|border[0]~feeder_combout = \D[0]~65_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\D[0]~65_combout ), + .cin(gnd), + .combout(\ula_|border[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|border[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|border[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y15_N5 dffeas \ula_|border[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\D[0]~58_combout ), + .d(\ula_|border[0]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -59437,7 +62780,7 @@ defparam \ula_|border[0] .is_wysiwyg = "true"; defparam \ula_|border[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N20 +// Location: LCCOMB_X30_Y28_N8 cycloneive_lcell_comb \ula_|video_|attr_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -59454,7 +62797,7 @@ defparam \ula_|video_|attr_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N21 +// Location: FF_X30_Y28_N9 dffeas \ula_|video_|attr_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[0]~feeder_combout ), @@ -59473,32 +62816,15 @@ defparam \ula_|video_|attr_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N28 -cycloneive_lcell_comb \ula_|video_|attr[0]~feeder ( -// Equation(s): -// \ula_|video_|attr[0]~feeder_combout = \ula_|video_|attr_prefetch [0] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|attr_prefetch [0]), - .cin(gnd), - .combout(\ula_|video_|attr[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y33_N29 +// Location: FF_X29_Y30_N23 dffeas \ula_|video_|attr[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr[0]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [0]), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -59509,7 +62835,7 @@ defparam \ula_|video_|attr[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N2 +// Location: LCCOMB_X30_Y28_N2 cycloneive_lcell_comb \ula_|video_|attr_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 @@ -59526,7 +62852,7 @@ defparam \ula_|video_|attr_prefetch[3]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N3 +// Location: FF_X30_Y28_N3 dffeas \ula_|video_|attr_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[3]~feeder_combout ), @@ -59545,7 +62871,7 @@ defparam \ula_|video_|attr_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N29 +// Location: FF_X30_Y30_N9 dffeas \ula_|video_|attr[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59564,15 +62890,15 @@ defparam \ula_|video_|attr[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N28 +// Location: LCCOMB_X30_Y30_N8 cycloneive_lcell_comb \ula_|video_|cindex[0]~3 ( // Equation(s): -// \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [3]))) +// \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [3]))) .dataa(gnd), .datab(\ula_|video_|attr [0]), .datac(\ula_|video_|attr [3]), - .datad(\ula_|video_|cindex[1]~0_combout ), + .datad(\ula_|video_|cindex[2]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[0]~3_combout ), .cout()); @@ -59581,58 +62907,58 @@ defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hCCF0; defparam \ula_|video_|cindex[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N30 +// Location: LCCOMB_X30_Y30_N26 cycloneive_lcell_comb \ula_|video_|VGA_B[0]~1 ( // Equation(s): // \ula_|video_|VGA_B[0]~1_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[0]~3_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [0])))) - .dataa(\ula_|video_|disp_enable~1_combout ), - .datab(\ula_|border [0]), - .datac(\ula_|video_|screen_en~1_combout ), - .datad(\ula_|video_|cindex[0]~3_combout ), + .dataa(\ula_|border [0]), + .datab(\ula_|video_|cindex[0]~3_combout ), + .datac(\ula_|video_|disp_enable~1_combout ), + .datad(\ula_|video_|screen_en~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[0]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hA808; +defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hC0A0; defparam \ula_|video_|VGA_B[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N0 +// Location: LCCOMB_X30_Y30_N12 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~2 ( // Equation(s): -// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[0]~3_combout )) +// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|cindex[0]~3_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|screen_en~1_combout )) - .dataa(\ula_|video_|screen_en~1_combout ), - .datab(gnd), - .datac(\ula_|video_|VGA_B[1]~0_combout ), - .datad(\ula_|video_|cindex[0]~3_combout ), + .dataa(\ula_|video_|cindex[0]~3_combout ), + .datab(\ula_|video_|VGA_B[1]~0_combout ), + .datac(gnd), + .datad(\ula_|video_|screen_en~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[1]~2 .lut_mask = 16'hA000; +defparam \ula_|video_|VGA_B[1]~2 .lut_mask = 16'h8800; defparam \ula_|video_|VGA_B[1]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N26 +// Location: LCCOMB_X29_Y29_N12 cycloneive_lcell_comb \ula_|video_|Equal0~2 ( // Equation(s): -// \ula_|video_|Equal0~2_combout = (\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [9] & !\ula_|video_|vga_hc [8])) +// \ula_|video_|Equal0~2_combout = (!\ula_|video_|vga_hc [9] & (!\ula_|video_|vga_hc [8] & \ula_|video_|vga_hc [6])) - .dataa(\ula_|video_|vga_hc [6]), - .datab(\ula_|video_|vga_hc [9]), - .datac(gnd), - .datad(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_hc [9]), + .datab(gnd), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|vga_hc [6]), .cin(gnd), .combout(\ula_|video_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0022; +defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0500; defparam \ula_|video_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y33_N7 +// Location: FF_X29_Y29_N1 dffeas \ula_|video_|VGA_HS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector0~0_combout ), @@ -59651,7 +62977,7 @@ defparam \ula_|video_|VGA_HS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N6 +// Location: LCCOMB_X29_Y29_N0 cycloneive_lcell_comb \ula_|video_|Selector0~0 ( // Equation(s): // \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|Equal1~0_combout & \ula_|video_|VGA_HS~_Duplicate_1_q )))) # (!\ula_|video_|Equal0~2_combout & (\ula_|video_|Equal1~0_combout & @@ -59688,7 +63014,7 @@ defparam \ula_|video_|VGA_HS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS .power_up = "low"; // synopsys translate_on -// Location: FF_X34_Y33_N25 +// Location: FF_X32_Y30_N1 dffeas \ula_|video_|VGA_VS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector1~0_combout ), @@ -59707,21 +63033,21 @@ defparam \ula_|video_|VGA_VS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y33_N24 +// Location: LCCOMB_X32_Y30_N0 cycloneive_lcell_comb \ula_|video_|Selector1~0 ( // Equation(s): -// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal3~1_combout & (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1])))) # (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|VGA_VS~_Duplicate_1_q ) # ((\ula_|video_|Equal2~2_combout & -// \ula_|video_|vga_vc [1])))) +// \ula_|video_|Selector1~0_combout = (\ula_|video_|vga_vc [1] & ((\ula_|video_|Equal2~2_combout ) # ((\ula_|video_|VGA_VS~_Duplicate_1_q & !\ula_|video_|Equal3~1_combout )))) # (!\ula_|video_|vga_vc [1] & (((\ula_|video_|VGA_VS~_Duplicate_1_q & +// !\ula_|video_|Equal3~1_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), + .dataa(\ula_|video_|vga_vc [1]), .datab(\ula_|video_|Equal2~2_combout ), .datac(\ula_|video_|VGA_VS~_Duplicate_1_q ), - .datad(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector1~0 .lut_mask = 16'hDC50; +defparam \ula_|video_|Selector1~0 .lut_mask = 16'h88F8; defparam \ula_|video_|Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59744,7 +63070,7 @@ defparam \ula_|video_|VGA_VS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N4 +// Location: LCCOMB_X40_Y13_N4 cycloneive_lcell_comb \z80_|memory_ifc_|q1~feeder ( // Equation(s): // \z80_|memory_ifc_|q1~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -59761,7 +63087,7 @@ defparam \z80_|memory_ifc_|q1~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|q1~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X47_Y17_N5 +// Location: FF_X40_Y13_N5 dffeas \z80_|memory_ifc_|q1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|q1~feeder_combout ), @@ -59780,7 +63106,7 @@ defparam \z80_|memory_ifc_|q1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q1 .power_up = "low"; // synopsys translate_on -// Location: FF_X47_Y17_N25 +// Location: FF_X40_Y13_N3 dffeas \z80_|memory_ifc_|q2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -59799,7 +63125,7 @@ defparam \z80_|memory_ifc_|q2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N24 +// Location: LCCOMB_X40_Y13_N2 cycloneive_lcell_comb \z80_|memory_ifc_|nRFSH_out~0 ( // Equation(s): // \z80_|memory_ifc_|nRFSH_out~0_combout = (!\z80_|memory_ifc_|q2~q & \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) @@ -59816,7 +63142,7 @@ defparam \z80_|memory_ifc_|nRFSH_out~0 .lut_mask = 16'h0F00; defparam \z80_|memory_ifc_|nRFSH_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N26 +// Location: LCCOMB_X40_Y13_N24 cycloneive_lcell_comb \z80_|memory_ifc_|nM1_out ( // Equation(s): // \z80_|memory_ifc_|nM1_out~combout = (\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) @@ -59833,24 +63159,24 @@ defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF0F; defparam \z80_|memory_ifc_|nM1_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y26_N0 +// Location: LCCOMB_X23_Y19_N24 cycloneive_lcell_comb \ula_|beep~0 ( // Equation(s): -// \ula_|beep~0_combout = \D[4]~98_combout $ (\raw_loader_in~input_o $ (\D[3]~96_combout )) +// \ula_|beep~0_combout = \D[3]~109_combout $ (\raw_loader_in~input_o $ (\D[4]~111_combout )) - .dataa(gnd), - .datab(\D[4]~98_combout ), + .dataa(\D[3]~109_combout ), + .datab(gnd), .datac(\raw_loader_in~input_o ), - .datad(\D[3]~96_combout ), + .datad(\D[4]~111_combout ), .cin(gnd), .combout(\ula_|beep~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|beep~0 .lut_mask = 16'hC33C; +defparam \ula_|beep~0 .lut_mask = 16'hA55A; defparam \ula_|beep~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y26_N1 +// Location: FF_X23_Y19_N25 dffeas \ula_|beep ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|beep~0_combout ), @@ -59869,6 +63195,2526 @@ defparam \ula_|beep .is_wysiwyg = "true"; defparam \ula_|beep .power_up = "low"; // synopsys translate_on +// Location: LCCOMB_X23_Y10_N4 +cycloneive_lcell_comb \sdram_|Mux26~4 ( +// Equation(s): +// \sdram_|Mux26~4_combout = (!\sdram_|r.address[3]~6_combout & ((\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\sdram_|r.address[3]~6_combout ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [9]), + .cin(gnd), + .combout(\sdram_|Mux26~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux26~4 .lut_mask = 16'h3311; +defparam \sdram_|Mux26~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N10 +cycloneive_lcell_comb \sdram_|r.bank[0]~7 ( +// Equation(s): +// \sdram_|r.bank[0]~7_combout = (\sdram_|r.state [6] & \sdram_|r.state [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|r.bank[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~7 .lut_mask = 16'hF000; +defparam \sdram_|r.bank[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N8 +cycloneive_lcell_comb \sdram_|r.bank[0]~11 ( +// Equation(s): +// \sdram_|r.bank[0]~11_combout = (\sdram_|r.rd_pending~q & ((\sdram_|Equal7~2_combout ) # ((\sdram_|r.bank[0]~7_combout )))) # (!\sdram_|r.rd_pending~q & (((\sdram_|r.wr_pending~q & \sdram_|r.bank[0]~7_combout )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.bank[0]~7_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~11 .lut_mask = 16'hFCA0; +defparam \sdram_|r.bank[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N28 +cycloneive_lcell_comb \sdram_|r.bank[0]~4 ( +// Equation(s): +// \sdram_|r.bank[0]~4_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q ))) + + .dataa(gnd), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~4 .lut_mask = 16'hF0C0; +defparam \sdram_|r.bank[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N28 +cycloneive_lcell_comb \sdram_|r.bank[0]~5 ( +// Equation(s): +// \sdram_|r.bank[0]~5_combout = (\sdram_|r.state [5] & (!\sdram_|r.state [4] & ((!\sdram_|r.bank[0]~4_combout ) # (!\sdram_|r.state [7])))) # (!\sdram_|r.state [5] & (((\sdram_|r.state [7])))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.bank[0]~4_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~5 .lut_mask = 16'h3474; +defparam \sdram_|r.bank[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N4 +cycloneive_lcell_comb \sdram_|r.bank[0]~6 ( +// Equation(s): +// \sdram_|r.bank[0]~6_combout = (\sdram_|r.state [8] & (((\sdram_|r.state [6])))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & ((!\sdram_|r.bank[0]~5_combout ) # (!\sdram_|r.state [6]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [6]) # +// (\sdram_|r.bank[0]~5_combout ))))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.bank[0]~5_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~6 .lut_mask = 16'hB5F4; +defparam \sdram_|r.bank[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N28 +cycloneive_lcell_comb \sdram_|r.bank[0]~8 ( +// Equation(s): +// \sdram_|r.bank[0]~8_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] & \sdram_|r.state [7])) # (!\sdram_|r.state [5] & (!\sdram_|r.state [4] & !\sdram_|r.state [7])) + + .dataa(gnd), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.bank[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~8 .lut_mask = 16'hC003; +defparam \sdram_|r.bank[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N18 +cycloneive_lcell_comb \sdram_|r.bank[0]~12 ( +// Equation(s): +// \sdram_|r.bank[0]~12_combout = (\sdram_|r.bank[0]~8_combout & ((\sdram_|r.bank[0]~11_combout ) # ((\sdram_|Equal7~2_combout & \sdram_|r.wr_pending~q )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.bank[0]~11_combout ), + .datad(\sdram_|r.bank[0]~8_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~12 .lut_mask = 16'hF800; +defparam \sdram_|r.bank[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N2 +cycloneive_lcell_comb \sdram_|r.bank[0]~9 ( +// Equation(s): +// \sdram_|r.bank[0]~9_combout = (\sdram_|r.state [8] & (\sdram_|r.bank[0]~12_combout & ((\sdram_|r.bank[0]~11_combout ) # (!\sdram_|r.bank[0]~6_combout )))) # (!\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~6_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.bank[0]~11_combout ), + .datac(\sdram_|r.bank[0]~6_combout ), + .datad(\sdram_|r.bank[0]~12_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~9 .lut_mask = 16'h8F05; +defparam \sdram_|r.bank[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X11_Y0_N18 +dffeas \sdram_|r.bank[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux26~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.bank[0]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.bank [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.bank[0] .is_wysiwyg = "true"; +defparam \sdram_|r.bank[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N2 +cycloneive_lcell_comb \sdram_|Mux25~4 ( +// Equation(s): +// \sdram_|Mux25~4_combout = (!\sdram_|r.address[3]~6_combout & ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [10]), + .datac(gnd), + .datad(\sdram_|r.address[3]~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux25~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux25~4 .lut_mask = 16'h00DD; +defparam \sdram_|Mux25~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X7_Y0_N11 +dffeas \sdram_|r.bank[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux25~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.bank[0]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.bank [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.bank[1] .is_wysiwyg = "true"; +defparam \sdram_|r.bank[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N6 +cycloneive_lcell_comb \sdram_|Mux24~5 ( +// Equation(s): +// \sdram_|Mux24~5_combout = (!\sdram_|r.state [6] & (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|Equal7~2_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux24~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~5 .lut_mask = 16'h0515; +defparam \sdram_|Mux24~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N24 +cycloneive_lcell_comb \sdram_|Mux71~0 ( +// Equation(s): +// \sdram_|Mux71~0_combout = (!\sdram_|r.state [4] & !\sdram_|r.state [5]) + + .dataa(gnd), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [5]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|Mux71~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~0 .lut_mask = 16'h0303; +defparam \sdram_|Mux71~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N4 +cycloneive_lcell_comb \sdram_|process_0~7 ( +// Equation(s): +// \sdram_|process_0~7_combout = \sdram_|r.act_row [4] $ (((\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\sdram_|r.act_row [4]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\sdram_|process_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~7 .lut_mask = 16'h3C0F; +defparam \sdram_|process_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N28 +cycloneive_lcell_comb \sdram_|process_0~4 ( +// Equation(s): +// \sdram_|process_0~4_combout = ((\sdram_|process_0~7_combout ) # ((!\sdram_|Equal7~0_combout ) # (!\sdram_|Equal7~1_combout ))) # (!\sdram_|r.rd_pending~q ) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|process_0~7_combout ), + .datac(\sdram_|Equal7~1_combout ), + .datad(\sdram_|Equal7~0_combout ), + .cin(gnd), + .combout(\sdram_|process_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~4 .lut_mask = 16'hDFFF; +defparam \sdram_|process_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N30 +cycloneive_lcell_comb \sdram_|Mux71~1 ( +// Equation(s): +// \sdram_|Mux71~1_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [6]) # ((!\sdram_|r.state [4]) # (!\sdram_|r.state [5])))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [6] & ((\sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux71~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~1 .lut_mask = 16'h9BAA; +defparam \sdram_|Mux71~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N28 +cycloneive_lcell_comb \sdram_|Mux71~2 ( +// Equation(s): +// \sdram_|Mux71~2_combout = (\sdram_|r.state [7] & ((\sdram_|Mux71~1_combout ) # ((!\sdram_|r.state [8] & \sdram_|Mux71~0_combout )))) # (!\sdram_|r.state [7] & (!\sdram_|r.state [8])) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux71~1_combout ), + .datad(\sdram_|Mux71~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux71~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~2 .lut_mask = 16'hD5D1; +defparam \sdram_|Mux71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N14 +cycloneive_lcell_comb \sdram_|Mux71~3 ( +// Equation(s): +// \sdram_|Mux71~3_combout = (\sdram_|Mux71~2_combout ) # ((\sdram_|process_0~4_combout & (\sdram_|Mux71~0_combout & \sdram_|r.state [6]))) + + .dataa(\sdram_|process_0~4_combout ), + .datab(\sdram_|Mux71~0_combout ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux71~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux71~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~3 .lut_mask = 16'hFF80; +defparam \sdram_|Mux71~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N4 +cycloneive_lcell_comb \sdram_|Mux71~4 ( +// Equation(s): +// \sdram_|Mux71~4_combout = (\sdram_|Mux71~3_combout ) # ((\sdram_|Mux24~5_combout & ((\sdram_|Mux71~0_combout ) # (\sdram_|r.state [7])))) + + .dataa(\sdram_|Mux24~5_combout ), + .datab(\sdram_|Mux71~0_combout ), + .datac(\sdram_|Mux71~3_combout ), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux71~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~4 .lut_mask = 16'hFAF8; +defparam \sdram_|Mux71~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X14_Y0_N11 +dffeas \sdram_|r.dq_masks[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux71~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.dq_masks [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.dq_masks[0] .is_wysiwyg = "true"; +defparam \sdram_|r.dq_masks[0] .power_up = "low"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X14_Y0_N18 +dffeas \sdram_|r.dq_masks[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux71~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.dq_masks [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.dq_masks[1] .is_wysiwyg = "true"; +defparam \sdram_|r.dq_masks[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N2 +cycloneive_lcell_comb \sdram_|r.bank[0]~10 ( +// Equation(s): +// \sdram_|r.bank[0]~10_combout = \sdram_|r.state [5] $ (\sdram_|r.state [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.bank[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~10 .lut_mask = 16'h0FF0; +defparam \sdram_|r.bank[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N18 +cycloneive_lcell_comb \sdram_|Mux9~3 ( +// Equation(s): +// \sdram_|Mux9~3_combout = (\sdram_|r.bank[0]~10_combout ) # ((!\sdram_|n~2_combout & (\sdram_|r.state [6] & \sdram_|r.state [4]))) + + .dataa(\sdram_|n~2_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.bank[0]~10_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~3 .lut_mask = 16'hFF40; +defparam \sdram_|Mux9~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N30 +cycloneive_lcell_comb \sdram_|n~5 ( +// Equation(s): +// \sdram_|n~5_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|Equal7~2_combout ) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|n~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|n~5 .lut_mask = 16'h3031; +defparam \sdram_|n~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N12 +cycloneive_lcell_comb \sdram_|Mux9~4 ( +// Equation(s): +// \sdram_|Mux9~4_combout = (\sdram_|Mux9~3_combout ) # ((\sdram_|r.state [7] & (\sdram_|n~5_combout & !\sdram_|r.state [6]))) + + .dataa(\sdram_|Mux9~3_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|n~5_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux9~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~4 .lut_mask = 16'hAAEA; +defparam \sdram_|Mux9~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N4 +cycloneive_lcell_comb \sdram_|Mux9~2 ( +// Equation(s): +// \sdram_|Mux9~2_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [4] & (!\sdram_|r.state [7])) # (!\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (\sdram_|n~5_combout ))))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|n~5_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux9~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~2 .lut_mask = 16'h7600; +defparam \sdram_|Mux9~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N30 +cycloneive_lcell_comb \sdram_|Equal2~3 ( +// Equation(s): +// \sdram_|Equal2~3_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [0] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [7]))) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [0]), + .datac(\sdram_|Equal2~2_combout ), + .datad(\sdram_|r.init_counter [7]), + .cin(gnd), + .combout(\sdram_|Equal2~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~3 .lut_mask = 16'h2000; +defparam \sdram_|Equal2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N8 +cycloneive_lcell_comb \sdram_|Mux10~2 ( +// Equation(s): +// \sdram_|Mux10~2_combout = (\sdram_|r.init_counter [6]) # ((\sdram_|r.init_counter [5]) # (\sdram_|r.init_counter [4])) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [6]), + .datac(\sdram_|r.init_counter [5]), + .datad(\sdram_|r.init_counter [4]), + .cin(gnd), + .combout(\sdram_|Mux10~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~2 .lut_mask = 16'hFFFC; +defparam \sdram_|Mux10~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N26 +cycloneive_lcell_comb \sdram_|Mux10~3 ( +// Equation(s): +// \sdram_|Mux10~3_combout = (\sdram_|r.init_counter [1] & ((\sdram_|r.init_counter [2] & (!\sdram_|r.init_counter [3])) # (!\sdram_|r.init_counter [2] & (\sdram_|r.init_counter [3] & !\sdram_|Mux10~2_combout )))) + + .dataa(\sdram_|r.init_counter [2]), + .datab(\sdram_|r.init_counter [3]), + .datac(\sdram_|Mux10~2_combout ), + .datad(\sdram_|r.init_counter [1]), + .cin(gnd), + .combout(\sdram_|Mux10~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~3 .lut_mask = 16'h2600; +defparam \sdram_|Mux10~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N4 +cycloneive_lcell_comb \sdram_|process_0~6 ( +// Equation(s): +// \sdram_|process_0~6_combout = (!\sdram_|r.init_counter [9] & (!\sdram_|r.init_counter [8] & (\sdram_|process_0~5_combout & !\sdram_|r.init_counter [10]))) + + .dataa(\sdram_|r.init_counter [9]), + .datab(\sdram_|r.init_counter [8]), + .datac(\sdram_|process_0~5_combout ), + .datad(\sdram_|r.init_counter [10]), + .cin(gnd), + .combout(\sdram_|process_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~6 .lut_mask = 16'h0010; +defparam \sdram_|process_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N24 +cycloneive_lcell_comb \sdram_|Mux10~4 ( +// Equation(s): +// \sdram_|Mux10~4_combout = ((\sdram_|r.init_counter [7]) # ((!\sdram_|r.init_counter [0]) # (!\sdram_|process_0~6_combout ))) # (!\sdram_|Mux10~3_combout ) + + .dataa(\sdram_|Mux10~3_combout ), + .datab(\sdram_|r.init_counter [7]), + .datac(\sdram_|process_0~6_combout ), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Mux10~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~4 .lut_mask = 16'hDFFF; +defparam \sdram_|Mux10~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N22 +cycloneive_lcell_comb \sdram_|Mux9~5 ( +// Equation(s): +// \sdram_|Mux9~5_combout = (\sdram_|r.state [6]) # ((\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|n~2_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|n~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~5 .lut_mask = 16'hEAEE; +defparam \sdram_|Mux9~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N20 +cycloneive_lcell_comb \sdram_|Mux7~0 ( +// Equation(s): +// \sdram_|Mux7~0_combout = (!\sdram_|r.state [7] & !\sdram_|r.state [4]) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(gnd), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~0 .lut_mask = 16'h0033; +defparam \sdram_|Mux7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N10 +cycloneive_lcell_comb \sdram_|Mux9~6 ( +// Equation(s): +// \sdram_|Mux9~6_combout = (\sdram_|Mux9~5_combout ) # ((!\sdram_|Equal2~3_combout & (\sdram_|Mux10~4_combout & \sdram_|Mux7~0_combout ))) + + .dataa(\sdram_|Equal2~3_combout ), + .datab(\sdram_|Mux10~4_combout ), + .datac(\sdram_|Mux9~5_combout ), + .datad(\sdram_|Mux7~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~6 .lut_mask = 16'hF4F0; +defparam \sdram_|Mux9~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N24 +cycloneive_lcell_comb \sdram_|Mux9~7 ( +// Equation(s): +// \sdram_|Mux9~7_combout = (\sdram_|Mux9~4_combout ) # ((\sdram_|Mux9~2_combout ) # ((!\sdram_|r.state [8] & \sdram_|Mux9~6_combout ))) + + .dataa(\sdram_|Mux9~4_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux9~2_combout ), + .datad(\sdram_|Mux9~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~7 .lut_mask = 16'hFBFA; +defparam \sdram_|Mux9~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y11_N4 +dffeas \sdram_|r.state[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux9~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[2] .is_wysiwyg = "true"; +defparam \sdram_|r.state[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N16 +cycloneive_lcell_comb \sdram_|Mux10~11 ( +// Equation(s): +// \sdram_|Mux10~11_combout = (\sdram_|r.rf_pending~q & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q )))) # (!\sdram_|r.rf_pending~q & (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|Equal7~2_combout ))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux10~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~11 .lut_mask = 16'hAF9D; +defparam \sdram_|Mux10~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N12 +cycloneive_lcell_comb \sdram_|Mux10~6 ( +// Equation(s): +// \sdram_|Mux10~6_combout = (\sdram_|r.state [6] & (((\sdram_|process_0~4_combout ) # (!\sdram_|r.state [8])))) # (!\sdram_|r.state [6] & (\sdram_|Mux10~11_combout & ((\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Mux10~11_combout ), + .datac(\sdram_|process_0~4_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux10~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~6 .lut_mask = 16'hE4AA; +defparam \sdram_|Mux10~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N26 +cycloneive_lcell_comb \sdram_|Mux10~5 ( +// Equation(s): +// \sdram_|Mux10~5_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [4]) # ((\sdram_|r.rf_pending~q )))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & (!\sdram_|r.rf_pending~q )) # (!\sdram_|r.state [4] & ((\sdram_|Mux10~4_combout ))))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Mux10~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~5 .lut_mask = 16'hBDAC; +defparam \sdram_|Mux10~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N10 +cycloneive_lcell_comb \sdram_|Mux10~7 ( +// Equation(s): +// \sdram_|Mux10~7_combout = (\sdram_|r.state [6] & (((!\sdram_|r.state [8]) # (!\sdram_|r.rf_pending~q )) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & ((\sdram_|r.rf_pending~q ) # (\sdram_|r.state [4] $ (\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux10~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~7 .lut_mask = 16'h7BFE; +defparam \sdram_|Mux10~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N20 +cycloneive_lcell_comb \sdram_|Mux10~8 ( +// Equation(s): +// \sdram_|Mux10~8_combout = (\sdram_|r.state [7] & ((\sdram_|Mux10~7_combout ) # ((\sdram_|Mux10~11_combout )))) # (!\sdram_|r.state [7] & (((\sdram_|Mux10~5_combout )))) + + .dataa(\sdram_|Mux10~7_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux10~5_combout ), + .datad(\sdram_|Mux10~11_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~8 .lut_mask = 16'hFCB8; +defparam \sdram_|Mux10~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N22 +cycloneive_lcell_comb \sdram_|Mux10~9 ( +// Equation(s): +// \sdram_|Mux10~9_combout = (\sdram_|r.bank[0]~10_combout ) # ((\sdram_|Mux10~8_combout ) # ((\sdram_|Mux10~6_combout & !\sdram_|Mux10~5_combout ))) + + .dataa(\sdram_|Mux10~6_combout ), + .datab(\sdram_|r.bank[0]~10_combout ), + .datac(\sdram_|Mux10~5_combout ), + .datad(\sdram_|Mux10~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~9 .lut_mask = 16'hFFCE; +defparam \sdram_|Mux10~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y11_N11 +dffeas \sdram_|r.state[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux10~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[1] .is_wysiwyg = "true"; +defparam \sdram_|r.state[1] .power_up = "low"; +// synopsys translate_on + +// Location: CLKCTRL_PLL1E0 +cycloneive_clkctrl \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [1]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK_outclk )); +// synopsys translate_off +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK .clock_type = "external clock output"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK .ena_register_mode = "double register"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N8 +cycloneive_lcell_comb \sdram_|Mux11~2 ( +// Equation(s): +// \sdram_|Mux11~2_combout = (\sdram_|r.init_counter [7] $ (!\sdram_|r.init_counter [0])) # (!\sdram_|r.init_counter [1]) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [7]), + .datac(gnd), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Mux11~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~2 .lut_mask = 16'hDD77; +defparam \sdram_|Mux11~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N6 +cycloneive_lcell_comb \sdram_|Mux11~3 ( +// Equation(s): +// \sdram_|Mux11~3_combout = (!\sdram_|r.state [8] & (!\sdram_|r.state [6] & ((\sdram_|Mux11~2_combout ) # (!\sdram_|Equal2~2_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Equal2~2_combout ), + .datac(\sdram_|Mux11~2_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux11~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~3 .lut_mask = 16'h0051; +defparam \sdram_|Mux11~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N26 +cycloneive_lcell_comb \sdram_|Mux11~4 ( +// Equation(s): +// \sdram_|Mux11~4_combout = (!\sdram_|r.state [7] & ((\sdram_|Mux11~3_combout ) # ((\sdram_|r.state [4] & !\sdram_|Mux23~0_combout )))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux23~0_combout ), + .datad(\sdram_|Mux11~3_combout ), + .cin(gnd), + .combout(\sdram_|Mux11~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~4 .lut_mask = 16'h3302; +defparam \sdram_|Mux11~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N28 +cycloneive_lcell_comb \sdram_|Mux11~5 ( +// Equation(s): +// \sdram_|Mux11~5_combout = (\sdram_|r.state [7] & ((\sdram_|r.state [4] $ (\sdram_|r.state [8])) # (!\sdram_|r.state [5]))) # (!\sdram_|r.state [7] & (((\sdram_|r.state [5])))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux11~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~5 .lut_mask = 16'h7CBC; +defparam \sdram_|Mux11~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N0 +cycloneive_lcell_comb \sdram_|Mux11~6 ( +// Equation(s): +// \sdram_|Mux11~6_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|r.state [7]) # ((!\sdram_|r.state [6] & \sdram_|r.state [8])))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux11~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~6 .lut_mask = 16'h4544; +defparam \sdram_|Mux11~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N30 +cycloneive_lcell_comb \sdram_|Mux11~7 ( +// Equation(s): +// \sdram_|Mux11~7_combout = (!\sdram_|r.wr_pending~q & (\sdram_|Mux11~6_combout & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.rd_pending~q )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Mux11~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux11~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~7 .lut_mask = 16'h2300; +defparam \sdram_|Mux11~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N16 +cycloneive_lcell_comb \sdram_|Mux11~9 ( +// Equation(s): +// \sdram_|Mux11~9_combout = (\sdram_|r.state [6] & (((\sdram_|n~5_combout ) # (!\sdram_|Mux7~0_combout )) # (!\sdram_|r.state [8]))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|n~5_combout ), + .datad(\sdram_|Mux7~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux11~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~9 .lut_mask = 16'hA2AA; +defparam \sdram_|Mux11~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N14 +cycloneive_lcell_comb \sdram_|Mux11~8 ( +// Equation(s): +// \sdram_|Mux11~8_combout = (\sdram_|Mux11~4_combout ) # ((\sdram_|Mux11~5_combout ) # ((\sdram_|Mux11~7_combout ) # (\sdram_|Mux11~9_combout ))) + + .dataa(\sdram_|Mux11~4_combout ), + .datab(\sdram_|Mux11~5_combout ), + .datac(\sdram_|Mux11~7_combout ), + .datad(\sdram_|Mux11~9_combout ), + .cin(gnd), + .combout(\sdram_|Mux11~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~8 .lut_mask = 16'hFFFE; +defparam \sdram_|Mux11~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y27_N4 +dffeas \sdram_|r.state[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux11~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[0] .is_wysiwyg = "true"; +defparam \sdram_|r.state[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N20 +cycloneive_lcell_comb \sdram_|Mux24~2 ( +// Equation(s): +// \sdram_|Mux24~2_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q & !\sdram_|r.state [6])))) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux24~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~2 .lut_mask = 16'hCE00; +defparam \sdram_|Mux24~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N2 +cycloneive_lcell_comb \sdram_|r.address[0]~7 ( +// Equation(s): +// \sdram_|r.address[0]~7_combout = (\sdram_|r.state [4] & ((\sdram_|process_0~2_combout & (\z80_|address_pins_|abus[11]~19_combout )) # (!\sdram_|process_0~2_combout & ((\sdram_|r.address[0]~_Duplicate_1_q ))))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\sdram_|r.address[0]~_Duplicate_1_q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|r.address[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[0]~7 .lut_mask = 16'hA0C0; +defparam \sdram_|r.address[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N12 +cycloneive_lcell_comb \sdram_|r.address[0]~0 ( +// Equation(s): +// \sdram_|r.address[0]~0_combout = (\sdram_|r.state [8] & (!\sdram_|Mux24~2_combout & (\sdram_|r.address[0]~_Duplicate_1_q ))) # (!\sdram_|r.state [8] & (((\sdram_|r.address[0]~7_combout )))) + + .dataa(\sdram_|Mux24~2_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.address[0]~_Duplicate_1_q ), + .datad(\sdram_|r.address[0]~7_combout ), + .cin(gnd), + .combout(\sdram_|r.address[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[0]~0 .lut_mask = 16'h7340; +defparam \sdram_|r.address[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N30 +cycloneive_lcell_comb \sdram_|Mux13~9 ( +// Equation(s): +// \sdram_|Mux13~9_combout = (!\sdram_|r.state [5] & ((\sdram_|r.state [8] & (!\sdram_|r.state [4])) # (!\sdram_|r.state [8] & ((!\sdram_|r.state [6]))))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux13~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~9 .lut_mask = 16'h0407; +defparam \sdram_|Mux13~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N0 +cycloneive_lcell_comb \sdram_|Mux13~4 ( +// Equation(s): +// \sdram_|Mux13~4_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] & (\sdram_|r.state [8] $ (!\sdram_|r.state [5])))) # (!\sdram_|r.state [6] & (\sdram_|r.state [5] & (\sdram_|r.state [4] $ (!\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux13~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~4 .lut_mask = 16'h8290; +defparam \sdram_|Mux13~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N2 +cycloneive_lcell_comb \sdram_|Mux13~5 ( +// Equation(s): +// \sdram_|Mux13~5_combout = (\sdram_|r.state [7] & ((\sdram_|Mux13~4_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux13~9_combout )) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux13~9_combout ), + .datad(\sdram_|Mux13~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux13~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~5 .lut_mask = 16'hFC30; +defparam \sdram_|Mux13~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y11_N13 +dffeas \sdram_|r.address[0]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[0]~0_combout ), + .asdata(\sdram_|Mux24~4_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\sdram_|r.state [7]), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[0]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[0]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[0]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N4 +cycloneive_lcell_comb \sdram_|Mux24~3 ( +// Equation(s): +// \sdram_|Mux24~3_combout = (\sdram_|Mux23~0_combout & ((\sdram_|process_0~2_combout & (\z80_|address_pins_|abus[11]~19_combout )) # (!\sdram_|process_0~2_combout & ((\sdram_|r.address[0]~_Duplicate_1_q ))))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\sdram_|r.address[0]~_Duplicate_1_q ), + .datac(\sdram_|Mux23~0_combout ), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux24~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~3 .lut_mask = 16'hA0C0; +defparam \sdram_|Mux24~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N14 +cycloneive_lcell_comb \sdram_|Mux24~4 ( +// Equation(s): +// \sdram_|Mux24~4_combout = (\sdram_|Mux24~3_combout ) # ((!\sdram_|n~3_combout & (\sdram_|r.address[0]~_Duplicate_1_q & !\sdram_|r.state [6]))) + + .dataa(\sdram_|n~3_combout ), + .datab(\sdram_|r.address[0]~_Duplicate_1_q ), + .datac(\sdram_|Mux24~3_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux24~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~4 .lut_mask = 16'hF0F4; +defparam \sdram_|Mux24~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N24 +cycloneive_lcell_comb \sdram_|r.address[0]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[0]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux24~4_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[0]~0_combout ))) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux24~4_combout ), + .datad(\sdram_|r.address[0]~0_combout ), + .cin(gnd), + .combout(\sdram_|r.address[0]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[0]~SLOAD_MUX .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[0]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y4_N18 +dffeas \sdram_|r.address[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[0]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[0] .is_wysiwyg = "true"; +defparam \sdram_|r.address[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N16 +cycloneive_lcell_comb \sdram_|r.address[1]~_Duplicate_1feeder ( +// Equation(s): +// \sdram_|r.address[1]~_Duplicate_1feeder_combout = \sdram_|r.address[1]~1_combout + + .dataa(\sdram_|r.address[1]~1_combout ), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[1]~_Duplicate_1feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~_Duplicate_1feeder .lut_mask = 16'hAAAA; +defparam \sdram_|r.address[1]~_Duplicate_1feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N20 +cycloneive_lcell_comb \sdram_|Mux23~4 ( +// Equation(s): +// \sdram_|Mux23~4_combout = (\sdram_|r.state [8] & (\sdram_|r.address[1]~_Duplicate_1_q )) # (!\sdram_|r.state [8] & ((\sdram_|process_0~2_combout & ((\z80_|address_pins_|abus[12]~24_combout ))) # (!\sdram_|process_0~2_combout & +// (\sdram_|r.address[1]~_Duplicate_1_q )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.address[1]~_Duplicate_1_q ), + .datac(\z80_|address_pins_|abus[12]~24_combout ), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux23~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~4 .lut_mask = 16'hD8CC; +defparam \sdram_|Mux23~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N16 +cycloneive_lcell_comb \sdram_|Equal5~0 ( +// Equation(s): +// \sdram_|Equal5~0_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [0]))) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [7]), + .datac(\sdram_|Equal2~2_combout ), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Equal5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal5~0 .lut_mask = 16'h2000; +defparam \sdram_|Equal5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N14 +cycloneive_lcell_comb \sdram_|Mux23~5 ( +// Equation(s): +// \sdram_|Mux23~5_combout = (\sdram_|r.state [8] & (\sdram_|Mux23~4_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & (\sdram_|Mux23~4_combout )) # (!\sdram_|r.state [4] & ((\sdram_|Equal5~0_combout ))))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux23~4_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|Equal5~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux23~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~5 .lut_mask = 16'hCDC8; +defparam \sdram_|Mux23~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N8 +cycloneive_lcell_comb \sdram_|Mux23~6 ( +// Equation(s): +// \sdram_|Mux23~6_combout = (\sdram_|Mux23~5_combout & (((\sdram_|r.state [4]) # (!\sdram_|Mux24~2_combout )) # (!\sdram_|r.state [8]))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|Mux23~5_combout ), + .datad(\sdram_|Mux24~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux23~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~6 .lut_mask = 16'hD0F0; +defparam \sdram_|Mux23~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N2 +cycloneive_lcell_comb \sdram_|Mux19~0 ( +// Equation(s): +// \sdram_|Mux19~0_combout = (\sdram_|r.state [7] & (\sdram_|r.state [5] $ (((!\sdram_|r.state [8] & \sdram_|r.state [6]))))) # (!\sdram_|r.state [7] & (!\sdram_|r.state [5] & ((\sdram_|r.state [8]) # (!\sdram_|r.state [6])))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [5]), + .cin(gnd), + .combout(\sdram_|Mux19~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~0 .lut_mask = 16'h8C63; +defparam \sdram_|Mux19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y12_N17 +dffeas \sdram_|r.address[1]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[1]~_Duplicate_1feeder_combout ), + .asdata(\sdram_|Mux23~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(!\sdram_|r.state [7]), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[1]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[1]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[1]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N28 +cycloneive_lcell_comb \sdram_|Mux23~2 ( +// Equation(s): +// \sdram_|Mux23~2_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] & ((\sdram_|process_0~2_combout ) # (!\sdram_|r.state [8])))) # (!\sdram_|r.state [6] & (\sdram_|process_0~2_combout & (\sdram_|r.state [4] $ (!\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|process_0~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux23~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~2 .lut_mask = 16'hC0A4; +defparam \sdram_|Mux23~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N30 +cycloneive_lcell_comb \sdram_|Mux23~3 ( +// Equation(s): +// \sdram_|Mux23~3_combout = (\sdram_|Mux23~2_combout & ((\sdram_|r.state [6]) # (\sdram_|Equal7~2_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|Mux23~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux23~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~3 .lut_mask = 16'hFA00; +defparam \sdram_|Mux23~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N18 +cycloneive_lcell_comb \sdram_|Mux23~1 ( +// Equation(s): +// \sdram_|Mux23~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [8] & ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) + + .dataa(\sdram_|r.state [6]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [12]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux23~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~1 .lut_mask = 16'hA200; +defparam \sdram_|Mux23~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N22 +cycloneive_lcell_comb \sdram_|r.address[1]~1 ( +// Equation(s): +// \sdram_|r.address[1]~1_combout = (\sdram_|Mux23~3_combout & ((\sdram_|Mux23~1_combout ))) # (!\sdram_|Mux23~3_combout & (\sdram_|r.address[1]~_Duplicate_1_q )) + + .dataa(gnd), + .datab(\sdram_|r.address[1]~_Duplicate_1_q ), + .datac(\sdram_|Mux23~3_combout ), + .datad(\sdram_|Mux23~1_combout ), + .cin(gnd), + .combout(\sdram_|r.address[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~1 .lut_mask = 16'hFC0C; +defparam \sdram_|r.address[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N2 +cycloneive_lcell_comb \sdram_|r.address[1]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[1]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|r.address[1]~1_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux23~6_combout ))) + + .dataa(\sdram_|r.address[1]~1_combout ), + .datab(\sdram_|Mux23~6_combout ), + .datac(\sdram_|r.state [7]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[1]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~SLOAD_MUX .lut_mask = 16'hACAC; +defparam \sdram_|r.address[1]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X5_Y0_N11 +dffeas \sdram_|r.address[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[1]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[1] .is_wysiwyg = "true"; +defparam \sdram_|r.address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N10 +cycloneive_lcell_comb \sdram_|r.address[3]~8 ( +// Equation(s): +// \sdram_|r.address[3]~8_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [5])) # (!\sdram_|r.state [6] & (((\sdram_|r.state [7]) # (\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.address[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~8 .lut_mask = 16'h7772; +defparam \sdram_|r.address[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N24 +cycloneive_lcell_comb \sdram_|r.address[3]~9 ( +// Equation(s): +// \sdram_|r.address[3]~9_combout = (\sdram_|r.state [5] & \sdram_|r.state [6]) + + .dataa(gnd), + .datab(\sdram_|r.state [5]), + .datac(gnd), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|r.address[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~9 .lut_mask = 16'hCC00; +defparam \sdram_|r.address[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N26 +cycloneive_lcell_comb \sdram_|Mux21~0 ( +// Equation(s): +// \sdram_|Mux21~0_combout = (!\sdram_|r.address[3]~8_combout & ((\sdram_|r.address[3]~9_combout ) # ((\sdram_|r.address[3]~6_combout & \sdram_|r.state [4])))) + + .dataa(\sdram_|r.address[3]~6_combout ), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.address[3]~9_combout ), + .datad(\sdram_|r.address[3]~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux21~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux21~0 .lut_mask = 16'h00F8; +defparam \sdram_|Mux21~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N18 +cycloneive_lcell_comb \sdram_|Mux22~0 ( +// Equation(s): +// \sdram_|Mux22~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|abus[1]~25_combout ) # ((\z80_|address_pins_|abus[13]~23_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~8_combout & +// (((\z80_|address_pins_|abus[13]~23_combout & \sdram_|Mux21~0_combout )))) + + .dataa(\sdram_|r.address[3]~8_combout ), + .datab(\z80_|address_pins_|abus[1]~25_combout ), + .datac(\z80_|address_pins_|abus[13]~23_combout ), + .datad(\sdram_|Mux21~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux22~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux22~0 .lut_mask = 16'hF888; +defparam \sdram_|Mux22~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N20 +cycloneive_lcell_comb \sdram_|r.address[3]~10 ( +// Equation(s): +// \sdram_|r.address[3]~10_combout = (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|r.state [7])) # (!\sdram_|r.state [4]) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|r.address[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~10 .lut_mask = 16'h777F; +defparam \sdram_|r.address[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N14 +cycloneive_lcell_comb \sdram_|r.address[3]~11 ( +// Equation(s): +// \sdram_|r.address[3]~11_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [7]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|r.rd_pending~q ))) + + .dataa(gnd), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.address[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~11 .lut_mask = 16'h0FF3; +defparam \sdram_|r.address[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N0 +cycloneive_lcell_comb \sdram_|r.address[3]~12 ( +// Equation(s): +// \sdram_|r.address[3]~12_combout = (\sdram_|r.address[3]~11_combout ) # ((\sdram_|r.state [4] & ((\sdram_|r.state [8]))) # (!\sdram_|r.state [4] & ((!\sdram_|r.state [8]) # (!\sdram_|Equal7~2_combout )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.address[3]~11_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.address[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~12 .lut_mask = 16'hFDCF; +defparam \sdram_|r.address[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N6 +cycloneive_lcell_comb \sdram_|r.address[3]~13 ( +// Equation(s): +// \sdram_|r.address[3]~13_combout = (\sdram_|r.state [5] & (((\sdram_|r.address[3]~10_combout )) # (!\sdram_|r.state [8]))) # (!\sdram_|r.state [5] & (((\sdram_|r.address[3]~12_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.address[3]~10_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.address[3]~12_combout ), + .cin(gnd), + .combout(\sdram_|r.address[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~13 .lut_mask = 16'hDFD0; +defparam \sdram_|r.address[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N16 +cycloneive_lcell_comb \sdram_|r.address[3]~14 ( +// Equation(s): +// \sdram_|r.address[3]~14_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [7]) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) # (!\sdram_|r.state [4] & (\sdram_|r.state [7] & (!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q ))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|r.address[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~14 .lut_mask = 16'h888E; +defparam \sdram_|r.address[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N22 +cycloneive_lcell_comb \sdram_|r.address[3]~15 ( +// Equation(s): +// \sdram_|r.address[3]~15_combout = (\sdram_|r.address[3]~14_combout ) # ((\sdram_|r.state [5] & ((!\sdram_|r.state [7]) # (!\sdram_|Equal7~2_combout ))) # (!\sdram_|r.state [5] & ((\sdram_|r.state [7])))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.address[3]~14_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.address[3]~15_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~15 .lut_mask = 16'hDFFC; +defparam \sdram_|r.address[3]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N24 +cycloneive_lcell_comb \sdram_|r.address[3]~16 ( +// Equation(s): +// \sdram_|r.address[3]~16_combout = (\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~8_combout )) # (!\sdram_|n~3_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|r.address[3]~15_combout )))) + + .dataa(\sdram_|n~3_combout ), + .datab(\sdram_|r.bank[0]~8_combout ), + .datac(\sdram_|r.address[3]~15_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.address[3]~16_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~16 .lut_mask = 16'h77F0; +defparam \sdram_|r.address[3]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N26 +cycloneive_lcell_comb \sdram_|r.address[3]~17 ( +// Equation(s): +// \sdram_|r.address[3]~17_combout = (\sdram_|r.state [6] & (!\sdram_|r.address[3]~13_combout )) # (!\sdram_|r.state [6] & ((!\sdram_|r.address[3]~16_combout ))) + + .dataa(\sdram_|r.address[3]~13_combout ), + .datab(gnd), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.address[3]~16_combout ), + .cin(gnd), + .combout(\sdram_|r.address[3]~17_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~17 .lut_mask = 16'h505F; +defparam \sdram_|r.address[3]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X5_Y0_N4 +dffeas \sdram_|r.address[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux22~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[2] .is_wysiwyg = "true"; +defparam \sdram_|r.address[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N2 +cycloneive_lcell_comb \sdram_|Mux21~1 ( +// Equation(s): +// \sdram_|Mux21~1_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|abus[2]~26_combout ) # ((\z80_|address_pins_|abus[14]~22_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~8_combout & +// (((\z80_|address_pins_|abus[14]~22_combout & \sdram_|Mux21~0_combout )))) + + .dataa(\sdram_|r.address[3]~8_combout ), + .datab(\z80_|address_pins_|abus[2]~26_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\sdram_|Mux21~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux21~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux21~1 .lut_mask = 16'hF888; +defparam \sdram_|Mux21~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X20_Y0_N11 +dffeas \sdram_|r.address[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux21~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[3] .is_wysiwyg = "true"; +defparam \sdram_|r.address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N22 +cycloneive_lcell_comb \sdram_|Mux20~4 ( +// Equation(s): +// \sdram_|Mux20~4_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & \sdram_|r.init_counter [0])) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [7]), + .datac(gnd), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Mux20~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~4 .lut_mask = 16'h2200; +defparam \sdram_|Mux20~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N26 +cycloneive_lcell_comb \sdram_|Mux20~7 ( +// Equation(s): +// \sdram_|Mux20~7_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\sdram_|r.state [6] & (!\z80_|address_pins_|DFFE_apin_latch [15])) # (!\sdram_|r.state [6] & ((!\z80_|address_pins_|DFFE_apin_latch [3]))))) + + .dataa(\sdram_|r.state [6]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\z80_|address_pins_|DFFE_apin_latch [3]), + .cin(gnd), + .combout(\sdram_|Mux20~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~7 .lut_mask = 16'h084C; +defparam \sdram_|Mux20~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N10 +cycloneive_lcell_comb \sdram_|Mux23~7 ( +// Equation(s): +// \sdram_|Mux23~7_combout = (\sdram_|r.state [4] & (\sdram_|process_0~2_combout & ((\sdram_|r.state [6]) # (\sdram_|Equal7~2_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux23~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~7 .lut_mask = 16'hE000; +defparam \sdram_|Mux23~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N10 +cycloneive_lcell_comb \sdram_|Mux20~8 ( +// Equation(s): +// \sdram_|Mux20~8_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] $ (((\sdram_|r.state [8]))))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [4] & (\sdram_|n~3_combout & !\sdram_|r.state [8]))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|n~3_combout ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux20~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~8 .lut_mask = 16'h50A4; +defparam \sdram_|Mux20~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N18 +cycloneive_lcell_comb \sdram_|Mux20~10 ( +// Equation(s): +// \sdram_|Mux20~10_combout = (\sdram_|r.state [8] & (\sdram_|Mux20~7_combout & (\sdram_|Mux23~7_combout & !\sdram_|Mux20~8_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux20~8_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux20~7_combout ), + .datac(\sdram_|Mux23~7_combout ), + .datad(\sdram_|Mux20~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~10 .lut_mask = 16'h5580; +defparam \sdram_|Mux20~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N0 +cycloneive_lcell_comb \sdram_|Mux20~9 ( +// Equation(s): +// \sdram_|Mux20~9_combout = (\sdram_|r.state [8] & (!\sdram_|Mux20~7_combout & (\sdram_|Mux23~7_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux20~8_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux20~7_combout ), + .datac(\sdram_|Mux23~7_combout ), + .datad(\sdram_|Mux20~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~9 .lut_mask = 16'h7520; +defparam \sdram_|Mux20~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N24 +cycloneive_lcell_comb \sdram_|Mux20~11 ( +// Equation(s): +// \sdram_|Mux20~11_combout = (\sdram_|Mux20~10_combout & (((\z80_|address_pins_|abus[3]~27_combout & \sdram_|Mux20~9_combout )))) # (!\sdram_|Mux20~10_combout & ((\sdram_|r.address[4]~_Duplicate_1_q ) # ((\sdram_|Mux20~9_combout )))) + + .dataa(\sdram_|r.address[4]~_Duplicate_1_q ), + .datab(\z80_|address_pins_|abus[3]~27_combout ), + .datac(\sdram_|Mux20~10_combout ), + .datad(\sdram_|Mux20~9_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~11 .lut_mask = 16'hCF0A; +defparam \sdram_|Mux20~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y11_N5 +dffeas \sdram_|r.address[4]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[4]~2_combout ), + .asdata(\sdram_|Mux20~11_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\sdram_|r.state [7]), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[4]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[4]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[4]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N2 +cycloneive_lcell_comb \sdram_|Mux20~12 ( +// Equation(s): +// \sdram_|Mux20~12_combout = (\sdram_|process_0~2_combout & (((\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) # (!\sdram_|process_0~2_combout & (\sdram_|r.address[4]~_Duplicate_1_q )) + + .dataa(\sdram_|r.address[4]~_Duplicate_1_q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~12 .lut_mask = 16'hCFAA; +defparam \sdram_|Mux20~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N4 +cycloneive_lcell_comb \sdram_|Mux20~5 ( +// Equation(s): +// \sdram_|Mux20~5_combout = (\sdram_|r.state [4] & (((\sdram_|Mux20~12_combout )))) # (!\sdram_|r.state [4] & (\sdram_|Mux20~4_combout & (\sdram_|Equal2~2_combout ))) + + .dataa(\sdram_|Mux20~4_combout ), + .datab(\sdram_|Equal2~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|Mux20~12_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~5 .lut_mask = 16'hF808; +defparam \sdram_|Mux20~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N16 +cycloneive_lcell_comb \sdram_|Mux20~6 ( +// Equation(s): +// \sdram_|Mux20~6_combout = (\sdram_|Mux24~2_combout & ((\sdram_|r.state [4] & ((\sdram_|r.address[4]~_Duplicate_1_q ))) # (!\sdram_|r.state [4] & (\z80_|address_pins_|abus[3]~27_combout )))) # (!\sdram_|Mux24~2_combout & +// (((\sdram_|r.address[4]~_Duplicate_1_q )))) + + .dataa(\sdram_|Mux24~2_combout ), + .datab(\z80_|address_pins_|abus[3]~27_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.address[4]~_Duplicate_1_q ), + .cin(gnd), + .combout(\sdram_|Mux20~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~6 .lut_mask = 16'hFD08; +defparam \sdram_|Mux20~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N4 +cycloneive_lcell_comb \sdram_|r.address[4]~2 ( +// Equation(s): +// \sdram_|r.address[4]~2_combout = (\sdram_|r.state [8] & ((\sdram_|Mux20~6_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux20~5_combout )) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux20~5_combout ), + .datac(gnd), + .datad(\sdram_|Mux20~6_combout ), + .cin(gnd), + .combout(\sdram_|r.address[4]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[4]~2 .lut_mask = 16'hEE44; +defparam \sdram_|r.address[4]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N8 +cycloneive_lcell_comb \sdram_|r.address[4]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[4]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux20~11_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[4]~2_combout )) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.address[4]~2_combout ), + .datad(\sdram_|Mux20~11_combout ), + .cin(gnd), + .combout(\sdram_|r.address[4]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[4]~SLOAD_MUX .lut_mask = 16'hFC30; +defparam \sdram_|r.address[4]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X25_Y0_N18 +dffeas \sdram_|r.address[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[4]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[4] .is_wysiwyg = "true"; +defparam \sdram_|r.address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N26 +cycloneive_lcell_comb \sdram_|Mux19~1 ( +// Equation(s): +// \sdram_|Mux19~1_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [0]))) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [7]), + .datac(\sdram_|Equal2~2_combout ), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Mux19~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~1 .lut_mask = 16'h2000; +defparam \sdram_|Mux19~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N12 +cycloneive_lcell_comb \sdram_|Mux19~4 ( +// Equation(s): +// \sdram_|Mux19~4_combout = (\sdram_|r.state [8] & (\sdram_|Mux23~7_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.bank[0]~4_combout ))) + + .dataa(\sdram_|r.state [8]), + .datab(gnd), + .datac(\sdram_|Mux23~7_combout ), + .datad(\sdram_|r.bank[0]~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux19~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~4 .lut_mask = 16'hF5A0; +defparam \sdram_|Mux19~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N22 +cycloneive_lcell_comb \sdram_|Mux19~5 ( +// Equation(s): +// \sdram_|Mux19~5_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [8] & (\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & (\sdram_|Mux19~4_combout & ((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux19~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux19~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~5 .lut_mask = 16'h4B40; +defparam \sdram_|Mux19~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N20 +cycloneive_lcell_comb \sdram_|Mux19~6 ( +// Equation(s): +// \sdram_|Mux19~6_combout = (\sdram_|r.state [8] & (\sdram_|r.state [4] & (\sdram_|r.state [6] & \sdram_|Mux19~4_combout ))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux19~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux19~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~6 .lut_mask = 16'h8000; +defparam \sdram_|Mux19~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N14 +cycloneive_lcell_comb \sdram_|Mux19~7 ( +// Equation(s): +// \sdram_|Mux19~7_combout = (\sdram_|Mux19~5_combout & ((\sdram_|Mux19~6_combout & ((\sdram_|r.address[5]~_Duplicate_1_q ))) # (!\sdram_|Mux19~6_combout & (\z80_|address_pins_|abus[4]~28_combout )))) # (!\sdram_|Mux19~5_combout & +// (((\sdram_|r.address[5]~_Duplicate_1_q & !\sdram_|Mux19~6_combout )))) + + .dataa(\z80_|address_pins_|abus[4]~28_combout ), + .datab(\sdram_|r.address[5]~_Duplicate_1_q ), + .datac(\sdram_|Mux19~5_combout ), + .datad(\sdram_|Mux19~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux19~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~7 .lut_mask = 16'hC0AC; +defparam \sdram_|Mux19~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y11_N31 +dffeas \sdram_|r.address[5]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[5]~3_combout ), + .asdata(\sdram_|Mux19~7_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\sdram_|r.state [7]), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[5]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[5]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[5]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N20 +cycloneive_lcell_comb \sdram_|Mux19~2 ( +// Equation(s): +// \sdram_|Mux19~2_combout = (\sdram_|r.state [4] & (((!\sdram_|process_0~2_combout & \sdram_|r.address[5]~_Duplicate_1_q )))) # (!\sdram_|r.state [4] & (\sdram_|Mux19~1_combout )) + + .dataa(\sdram_|Mux19~1_combout ), + .datab(\sdram_|process_0~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.address[5]~_Duplicate_1_q ), + .cin(gnd), + .combout(\sdram_|Mux19~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~2 .lut_mask = 16'h3A0A; +defparam \sdram_|Mux19~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N6 +cycloneive_lcell_comb \sdram_|Mux19~3 ( +// Equation(s): +// \sdram_|Mux19~3_combout = (\sdram_|Mux24~2_combout & ((\sdram_|r.state [4] & ((\sdram_|r.address[5]~_Duplicate_1_q ))) # (!\sdram_|r.state [4] & (\z80_|address_pins_|abus[4]~28_combout )))) # (!\sdram_|Mux24~2_combout & +// (((\sdram_|r.address[5]~_Duplicate_1_q )))) + + .dataa(\sdram_|Mux24~2_combout ), + .datab(\sdram_|r.state [4]), + .datac(\z80_|address_pins_|abus[4]~28_combout ), + .datad(\sdram_|r.address[5]~_Duplicate_1_q ), + .cin(gnd), + .combout(\sdram_|Mux19~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~3 .lut_mask = 16'hFD20; +defparam \sdram_|Mux19~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N30 +cycloneive_lcell_comb \sdram_|r.address[5]~3 ( +// Equation(s): +// \sdram_|r.address[5]~3_combout = (\sdram_|r.state [8] & ((\sdram_|Mux19~3_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux19~2_combout )) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux19~2_combout ), + .datac(gnd), + .datad(\sdram_|Mux19~3_combout ), + .cin(gnd), + .combout(\sdram_|r.address[5]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[5]~3 .lut_mask = 16'hEE44; +defparam \sdram_|r.address[5]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N26 +cycloneive_lcell_comb \sdram_|r.address[5]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[5]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux19~7_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[5]~3_combout )) + + .dataa(\sdram_|r.address[5]~3_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux19~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[5]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[5]~SLOAD_MUX .lut_mask = 16'hE2E2; +defparam \sdram_|r.address[5]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X18_Y0_N25 +dffeas \sdram_|r.address[5] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[5]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[5] .is_wysiwyg = "true"; +defparam \sdram_|r.address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N6 +cycloneive_lcell_comb \sdram_|Mux18~0 ( +// Equation(s): +// \sdram_|Mux18~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [5]), + .datad(\sdram_|r.address[3]~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux18~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux18~0 .lut_mask = 16'hF500; +defparam \sdram_|Mux18~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X20_Y0_N4 +dffeas \sdram_|r.address[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux18~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[6] .is_wysiwyg = "true"; +defparam \sdram_|r.address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N4 +cycloneive_lcell_comb \sdram_|Mux17~0 ( +// Equation(s): +// \sdram_|Mux17~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [6]), + .datad(\sdram_|r.address[3]~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux17~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux17~0 .lut_mask = 16'hF500; +defparam \sdram_|Mux17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X14_Y0_N4 +dffeas \sdram_|r.address[7] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux17~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[7] .is_wysiwyg = "true"; +defparam \sdram_|r.address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N22 +cycloneive_lcell_comb \sdram_|Mux16~0 ( +// Equation(s): +// \sdram_|Mux16~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [7]), + .datad(\sdram_|r.address[3]~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux16~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux16~0 .lut_mask = 16'hF500; +defparam \sdram_|Mux16~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y5_N25 +dffeas \sdram_|r.address[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux16~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[8] .is_wysiwyg = "true"; +defparam \sdram_|r.address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N30 +cycloneive_lcell_comb \sdram_|Mux15~2 ( +// Equation(s): +// \sdram_|Mux15~2_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [8]), + .datac(gnd), + .datad(\sdram_|r.address[3]~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux15~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux15~2 .lut_mask = 16'hDD00; +defparam \sdram_|Mux15~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y4_N25 +dffeas \sdram_|r.address[9] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux15~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[9] .is_wysiwyg = "true"; +defparam \sdram_|r.address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N22 +cycloneive_lcell_comb \sdram_|Mux14~0 ( +// Equation(s): +// \sdram_|Mux14~0_combout = (\sdram_|r.rf_pending~q ) # ((\sdram_|n~4_combout & ((\sdram_|r.state [6]) # (!\sdram_|process_0~3_combout )))) + + .dataa(\sdram_|process_0~3_combout ), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|n~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux14~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~0 .lut_mask = 16'hFDCC; +defparam \sdram_|Mux14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N28 +cycloneive_lcell_comb \sdram_|Mux14~1 ( +// Equation(s): +// \sdram_|Mux14~1_combout = (\sdram_|r.state [4] & (((\sdram_|r.address[10]~_Duplicate_1_q & !\sdram_|process_0~2_combout )))) # (!\sdram_|r.state [4] & (\sdram_|Equal2~3_combout )) + + .dataa(\sdram_|Equal2~3_combout ), + .datab(\sdram_|r.address[10]~_Duplicate_1_q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux14~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~1 .lut_mask = 16'h0ACA; +defparam \sdram_|Mux14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N10 +cycloneive_lcell_comb \sdram_|r.address[10]~4 ( +// Equation(s): +// \sdram_|r.address[10]~4_combout = (\sdram_|r.state [8] & (\sdram_|Mux14~0_combout )) # (!\sdram_|r.state [8] & ((\sdram_|Mux14~1_combout ))) + + .dataa(\sdram_|Mux14~0_combout ), + .datab(\sdram_|r.state [8]), + .datac(gnd), + .datad(\sdram_|Mux14~1_combout ), + .cin(gnd), + .combout(\sdram_|r.address[10]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[10]~4 .lut_mask = 16'hBB88; +defparam \sdram_|r.address[10]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y11_N11 +dffeas \sdram_|r.address[10]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[10]~4_combout ), + .asdata(\sdram_|Mux14~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\sdram_|r.state [7]), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[10]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[10]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[10]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N16 +cycloneive_lcell_comb \sdram_|n~4 ( +// Equation(s): +// \sdram_|n~4_combout = (\sdram_|r.rd_pending~q & (!\sdram_|Equal7~2_combout )) # (!\sdram_|r.rd_pending~q & (((\sdram_|r.address[10]~_Duplicate_1_q ) # (\sdram_|r.wr_pending~q )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.address[10]~_Duplicate_1_q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|n~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|n~4 .lut_mask = 16'h5F5C; +defparam \sdram_|n~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N30 +cycloneive_lcell_comb \sdram_|Mux14~2 ( +// Equation(s): +// \sdram_|Mux14~2_combout = (!\sdram_|r.state [6] & ((\sdram_|r.rf_pending~q ) # ((!\sdram_|process_0~3_combout & \sdram_|n~4_combout )))) + + .dataa(\sdram_|process_0~3_combout ), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|n~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux14~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~2 .lut_mask = 16'h0D0C; +defparam \sdram_|Mux14~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N8 +cycloneive_lcell_comb \sdram_|Mux14~3 ( +// Equation(s): +// \sdram_|Mux14~3_combout = (\sdram_|Mux14~2_combout ) # ((\sdram_|r.address[10]~_Duplicate_1_q & (\sdram_|Mux23~0_combout & !\sdram_|process_0~2_combout ))) + + .dataa(\sdram_|Mux14~2_combout ), + .datab(\sdram_|r.address[10]~_Duplicate_1_q ), + .datac(\sdram_|Mux23~0_combout ), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux14~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~3 .lut_mask = 16'hAAEA; +defparam \sdram_|Mux14~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N26 +cycloneive_lcell_comb \sdram_|r.address[10]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[10]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux14~3_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[10]~4_combout ))) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux14~3_combout ), + .datad(\sdram_|r.address[10]~4_combout ), + .cin(gnd), + .combout(\sdram_|r.address[10]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[10]~SLOAD_MUX .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[10]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y8_N25 +dffeas \sdram_|r.address[10] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[10]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[10] .is_wysiwyg = "true"; +defparam \sdram_|r.address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N28 +cycloneive_lcell_comb \sdram_|r.address[11]~18 ( +// Equation(s): +// \sdram_|r.address[11]~18_combout = (!\sdram_|r.rd_pending~q & (\sdram_|r.state [4] & !\sdram_|r.wr_pending~q )) + + .dataa(gnd), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|r.address[11]~18_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~18 .lut_mask = 16'h0030; +defparam \sdram_|r.address[11]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N26 +cycloneive_lcell_comb \sdram_|r.address[11]~5 ( +// Equation(s): +// \sdram_|r.address[11]~5_combout = (\sdram_|r.address[11]~_Duplicate_2_q & ((\sdram_|r.state [8] & (!\sdram_|Mux24~2_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.address[11]~18_combout ))))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux24~2_combout ), + .datac(\sdram_|r.address[11]~_Duplicate_2_q ), + .datad(\sdram_|r.address[11]~18_combout ), + .cin(gnd), + .combout(\sdram_|r.address[11]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~5 .lut_mask = 16'h7020; +defparam \sdram_|r.address[11]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N4 +cycloneive_lcell_comb \sdram_|r.address[11]~_Duplicate_2feeder ( +// Equation(s): +// \sdram_|r.address[11]~_Duplicate_2feeder_combout = \sdram_|r.address[11]~5_combout + + .dataa(\sdram_|r.address[11]~5_combout ), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[11]~_Duplicate_2feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~_Duplicate_2feeder .lut_mask = 16'hAAAA; +defparam \sdram_|r.address[11]~_Duplicate_2feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y11_N5 +dffeas \sdram_|r.address[11]~_Duplicate_2 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[11]~_Duplicate_2feeder_combout ), + .asdata(\sdram_|Mux13~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\sdram_|r.state [7]), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[11]~_Duplicate_2_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[11]~_Duplicate_2 .is_wysiwyg = "true"; +defparam \sdram_|r.address[11]~_Duplicate_2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N8 +cycloneive_lcell_comb \sdram_|Mux13~10 ( +// Equation(s): +// \sdram_|Mux13~10_combout = (\sdram_|r.address[11]~_Duplicate_2_q & ((\sdram_|r.state [8]) # (!\sdram_|r.state [6]))) + + .dataa(gnd), + .datab(\sdram_|r.address[11]~_Duplicate_2_q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux13~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~10 .lut_mask = 16'hCC0C; +defparam \sdram_|Mux13~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N22 +cycloneive_lcell_comb \sdram_|Mux13~6 ( +// Equation(s): +// \sdram_|Mux13~6_combout = (\sdram_|Mux13~10_combout & (((!\sdram_|r.state [6] & !\sdram_|Equal7~2_combout )) # (!\sdram_|process_0~2_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|Mux13~10_combout ), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux13~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~6 .lut_mask = 16'h10F0; +defparam \sdram_|Mux13~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N12 +cycloneive_lcell_comb \sdram_|r.address[11]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[11]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux13~6_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[11]~5_combout ))) + + .dataa(\sdram_|Mux13~6_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.address[11]~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[11]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~SLOAD_MUX .lut_mask = 16'hB8B8; +defparam \sdram_|r.address[11]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y7_N4 +dffeas \sdram_|r.address[11] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[11]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[11] .is_wysiwyg = "true"; +defparam \sdram_|r.address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N6 +cycloneive_lcell_comb \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux13~6_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[11]~5_combout ))) + + .dataa(\sdram_|Mux13~6_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.address[11]~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX .lut_mask = 16'hB8B8; +defparam \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y6_N18 +dffeas \sdram_|r.address[11]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[11]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[11]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[11]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + // Location: IOIBUF_X0_Y16_N22 cycloneive_io_ibuf \SW[0]~input ( .i(SW[0]), @@ -59899,4 +65745,164 @@ defparam \I2C_SCLK~input .bus_hold = "false"; defparam \I2C_SCLK~input .simulate_z_as = "z"; // synopsys translate_on +// Location: IOIBUF_X0_Y23_N15 +cycloneive_io_ibuf \DRAM_DQ[0]~input ( + .i(DRAM_DQ[0]), + .ibar(gnd), + .o(\DRAM_DQ[0]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[0]~input .bus_hold = "false"; +defparam \DRAM_DQ[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y23_N22 +cycloneive_io_ibuf \DRAM_DQ[1]~input ( + .i(DRAM_DQ[1]), + .ibar(gnd), + .o(\DRAM_DQ[1]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[1]~input .bus_hold = "false"; +defparam \DRAM_DQ[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N8 +cycloneive_io_ibuf \DRAM_DQ[2]~input ( + .i(DRAM_DQ[2]), + .ibar(gnd), + .o(\DRAM_DQ[2]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[2]~input .bus_hold = "false"; +defparam \DRAM_DQ[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y7_N8 +cycloneive_io_ibuf \DRAM_DQ[3]~input ( + .i(DRAM_DQ[3]), + .ibar(gnd), + .o(\DRAM_DQ[3]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[3]~input .bus_hold = "false"; +defparam \DRAM_DQ[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y12_N1 +cycloneive_io_ibuf \DRAM_DQ[4]~input ( + .i(DRAM_DQ[4]), + .ibar(gnd), + .o(\DRAM_DQ[4]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[4]~input .bus_hold = "false"; +defparam \DRAM_DQ[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y15_N1 +cycloneive_io_ibuf \DRAM_DQ[5]~input ( + .i(DRAM_DQ[5]), + .ibar(gnd), + .o(\DRAM_DQ[5]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[5]~input .bus_hold = "false"; +defparam \DRAM_DQ[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y15_N8 +cycloneive_io_ibuf \DRAM_DQ[6]~input ( + .i(DRAM_DQ[6]), + .ibar(gnd), + .o(\DRAM_DQ[6]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[6]~input .bus_hold = "false"; +defparam \DRAM_DQ[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y0_N15 +cycloneive_io_ibuf \DRAM_DQ[7]~input ( + .i(DRAM_DQ[7]), + .ibar(gnd), + .o(\DRAM_DQ[7]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[7]~input .bus_hold = "false"; +defparam \DRAM_DQ[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y0_N15 +cycloneive_io_ibuf \DRAM_DQ[8]~input ( + .i(DRAM_DQ[8]), + .ibar(gnd), + .o(\DRAM_DQ[8]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[8]~input .bus_hold = "false"; +defparam \DRAM_DQ[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y0_N1 +cycloneive_io_ibuf \DRAM_DQ[9]~input ( + .i(DRAM_DQ[9]), + .ibar(gnd), + .o(\DRAM_DQ[9]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[9]~input .bus_hold = "false"; +defparam \DRAM_DQ[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X1_Y0_N1 +cycloneive_io_ibuf \DRAM_DQ[10]~input ( + .i(DRAM_DQ[10]), + .ibar(gnd), + .o(\DRAM_DQ[10]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[10]~input .bus_hold = "false"; +defparam \DRAM_DQ[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X1_Y0_N8 +cycloneive_io_ibuf \DRAM_DQ[11]~input ( + .i(DRAM_DQ[11]), + .ibar(gnd), + .o(\DRAM_DQ[11]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[11]~input .bus_hold = "false"; +defparam \DRAM_DQ[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y0_N22 +cycloneive_io_ibuf \DRAM_DQ[12]~input ( + .i(DRAM_DQ[12]), + .ibar(gnd), + .o(\DRAM_DQ[12]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[12]~input .bus_hold = "false"; +defparam \DRAM_DQ[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X1_Y0_N15 +cycloneive_io_ibuf \DRAM_DQ[13]~input ( + .i(DRAM_DQ[13]), + .ibar(gnd), + .o(\DRAM_DQ[13]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[13]~input .bus_hold = "false"; +defparam \DRAM_DQ[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X1_Y0_N22 +cycloneive_io_ibuf \DRAM_DQ[14]~input ( + .i(DRAM_DQ[14]), + .ibar(gnd), + .o(\DRAM_DQ[14]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[14]~input .bus_hold = "false"; +defparam \DRAM_DQ[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y12_N8 +cycloneive_io_ibuf \DRAM_DQ[15]~input ( + .i(DRAM_DQ[15]), + .ibar(gnd), + .o(\DRAM_DQ[15]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[15]~input .bus_hold = "false"; +defparam \DRAM_DQ[15]~input .simulate_z_as = "z"; +// synopsys translate_on + endmodule diff --git a/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo b/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo index 33e447c..52dc786 100644 --- a/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo +++ b/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "04/01/2022 18:55:52") + (DATE "04/02/2022 14:51:21") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,8 +41,8 @@ (INSTANCE GPIO_1\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1954:1954:1954) (1953:1953:1953)) - (PORT oe (1513:1513:1513) (1540:1540:1540)) + (PORT i (1389:1389:1389) (1434:1434:1434)) + (PORT oe (1581:1581:1581) (1600:1600:1600)) (IOPATH i o (2194:2194:2194) (2119:2119:2119)) (IOPATH oe o (2175:2175:2175) (2064:2064:2064)) ) @@ -53,8 +53,8 @@ (INSTANCE GPIO_1\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1975:1975:1975) (1942:1942:1942)) - (PORT oe (1769:1769:1769) (1737:1737:1737)) + (PORT i (1902:1902:1902) (1871:1871:1871)) + (PORT oe (1566:1566:1566) (1592:1592:1592)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -65,8 +65,8 @@ (INSTANCE GPIO_1\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1830:1830:1830) (1856:1856:1856)) - (PORT oe (1769:1769:1769) (1737:1737:1737)) + (PORT i (2060:2060:2060) (2022:2022:2022)) + (PORT oe (1566:1566:1566) (1592:1592:1592)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -77,8 +77,8 @@ (INSTANCE GPIO_1\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (2041:2041:2041) (2075:2075:2075)) - (PORT oe (1983:1983:1983) (2026:2026:2026)) + (PORT i (1683:1683:1683) (1652:1652:1652)) + (PORT oe (1959:1959:1959) (1951:1951:1951)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -89,8 +89,8 @@ (INSTANCE GPIO_1\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (2091:2091:2091) (2141:2141:2141)) - (PORT oe (1983:1983:1983) (2026:2026:2026)) + (PORT i (1753:1753:1753) (1733:1733:1733)) + (PORT oe (1959:1959:1959) (1951:1951:1951)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -101,8 +101,8 @@ (INSTANCE GPIO_1\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1824:1824:1824) (1811:1811:1811)) - (PORT oe (1772:1772:1772) (1805:1805:1805)) + (PORT i (1415:1415:1415) (1479:1479:1479)) + (PORT oe (2181:2181:2181) (2185:2185:2185)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -113,8 +113,8 @@ (INSTANCE GPIO_1\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1513:1513:1513) (1526:1526:1526)) - (PORT oe (1772:1772:1772) (1805:1805:1805)) + (PORT i (1527:1527:1527) (1518:1518:1518)) + (PORT oe (2181:2181:2181) (2185:2185:2185)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -125,8 +125,8 @@ (INSTANCE GPIO_1\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (1827:1827:1827) (1912:1912:1912)) - (PORT oe (1772:1772:1772) (1805:1805:1805)) + (PORT i (1534:1534:1534) (1562:1562:1562)) + (PORT oe (2181:2181:2181) (2185:2185:2185)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -137,8 +137,8 @@ (INSTANCE GPIO_1\[8\]\~output) (DELAY (ABSOLUTE - (PORT i (909:909:909) (940:940:940)) - (PORT oe (1999:1999:1999) (2033:2033:2033)) + (PORT i (1354:1354:1354) (1354:1354:1354)) + (PORT oe (2447:2447:2447) (2429:2429:2429)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -149,8 +149,8 @@ (INSTANCE GPIO_1\[9\]\~output) (DELAY (ABSOLUTE - (PORT i (1589:1589:1589) (1611:1611:1611)) - (PORT oe (1999:1999:1999) (2033:2033:2033)) + (PORT i (1499:1499:1499) (1481:1481:1481)) + (PORT oe (2447:2447:2447) (2429:2429:2429)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -161,8 +161,8 @@ (INSTANCE GPIO_1\[10\]\~output) (DELAY (ABSOLUTE - (PORT i (1797:1797:1797) (1798:1798:1798)) - (PORT oe (2219:2219:2219) (2301:2301:2301)) + (PORT i (1577:1577:1577) (1622:1622:1622)) + (PORT oe (2194:2194:2194) (2185:2185:2185)) (IOPATH i o (4033:4033:4033) (3610:3610:3610)) (IOPATH oe o (4029:4029:4029) (3565:3565:3565)) ) @@ -173,8 +173,8 @@ (INSTANCE GPIO_1\[11\]\~output) (DELAY (ABSOLUTE - (PORT i (1305:1305:1305) (1313:1313:1313)) - (PORT oe (1999:1999:1999) (2033:2033:2033)) + (PORT i (1445:1445:1445) (1430:1430:1430)) + (PORT oe (2447:2447:2447) (2429:2429:2429)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -185,8 +185,8 @@ (INSTANCE GPIO_1\[12\]\~output) (DELAY (ABSOLUTE - (PORT i (2024:2024:2024) (1964:1964:1964)) - (PORT oe (1581:1581:1581) (1553:1553:1553)) + (PORT i (1521:1521:1521) (1518:1518:1518)) + (PORT oe (1588:1588:1588) (1607:1607:1607)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -197,8 +197,8 @@ (INSTANCE GPIO_1\[13\]\~output) (DELAY (ABSOLUTE - (PORT i (2054:2054:2054) (2078:2078:2078)) - (PORT oe (2220:2220:2220) (2301:2301:2301)) + (PORT i (1526:1526:1526) (1561:1561:1561)) + (PORT oe (2194:2194:2194) (2185:2185:2185)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -209,8 +209,8 @@ (INSTANCE GPIO_1\[14\]\~output) (DELAY (ABSOLUTE - (PORT i (1495:1495:1495) (1526:1526:1526)) - (PORT oe (1979:1979:1979) (2021:2021:2021)) + (PORT i (1317:1317:1317) (1363:1363:1363)) + (PORT oe (1953:1953:1953) (2028:2028:2028)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -221,8 +221,8 @@ (INSTANCE GPIO_1\[15\]\~output) (DELAY (ABSOLUTE - (PORT i (1599:1599:1599) (1663:1663:1663)) - (PORT oe (1787:1787:1787) (1749:1749:1749)) + (PORT i (1675:1675:1675) (1640:1640:1640)) + (PORT oe (1763:1763:1763) (1772:1772:1772)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -233,8 +233,8 @@ (INSTANCE GPIO_1\[16\]\~output) (DELAY (ABSOLUTE - (PORT i (1110:1110:1110) (1123:1123:1123)) - (PORT oe (2254:2254:2254) (2230:2230:2230)) + (PORT i (1077:1077:1077) (1106:1106:1106)) + (PORT oe (1299:1299:1299) (1308:1308:1308)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -245,8 +245,8 @@ (INSTANCE GPIO_1\[17\]\~output) (DELAY (ABSOLUTE - (PORT i (1121:1121:1121) (1144:1144:1144)) - (PORT oe (2255:2255:2255) (2231:2231:2231)) + (PORT i (1121:1121:1121) (1157:1157:1157)) + (PORT oe (1550:1550:1550) (1564:1564:1564)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -257,8 +257,8 @@ (INSTANCE GPIO_1\[18\]\~output) (DELAY (ABSOLUTE - (PORT i (1039:1039:1039) (1034:1034:1034)) - (PORT oe (1972:1972:1972) (1940:1940:1940)) + (PORT i (1347:1347:1347) (1358:1358:1358)) + (PORT oe (1521:1521:1521) (1518:1518:1518)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -269,8 +269,8 @@ (INSTANCE GPIO_1\[19\]\~output) (DELAY (ABSOLUTE - (PORT i (1077:1077:1077) (1107:1107:1107)) - (PORT oe (2254:2254:2254) (2230:2230:2230)) + (PORT i (1290:1290:1290) (1266:1266:1266)) + (PORT oe (1299:1299:1299) (1308:1308:1308)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -281,8 +281,8 @@ (INSTANCE GPIO_1\[20\]\~output) (DELAY (ABSOLUTE - (PORT i (1347:1347:1347) (1360:1360:1360)) - (PORT oe (1937:1937:1937) (1909:1909:1909)) + (PORT i (1508:1508:1508) (1504:1504:1504)) + (PORT oe (1315:1315:1315) (1323:1323:1323)) (IOPATH i o (2194:2194:2194) (2119:2119:2119)) (IOPATH oe o (2175:2175:2175) (2064:2064:2064)) ) @@ -293,8 +293,8 @@ (INSTANCE GPIO_1\[21\]\~output) (DELAY (ABSOLUTE - (PORT i (1247:1247:1247) (1225:1225:1225)) - (PORT oe (1971:1971:1971) (1939:1939:1939)) + (PORT i (1351:1351:1351) (1368:1368:1368)) + (PORT oe (1576:1576:1576) (1576:1576:1576)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -305,8 +305,8 @@ (INSTANCE GPIO_1\[22\]\~output) (DELAY (ABSOLUTE - (PORT i (1127:1127:1127) (1128:1128:1128)) - (PORT oe (1883:1883:1883) (1842:1842:1842)) + (PORT i (1498:1498:1498) (1552:1552:1552)) + (PORT oe (1516:1516:1516) (1502:1502:1502)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -317,8 +317,8 @@ (INSTANCE GPIO_1\[23\]\~output) (DELAY (ABSOLUTE - (PORT i (1045:1045:1045) (1025:1025:1025)) - (PORT oe (2220:2220:2220) (2182:2182:2182)) + (PORT i (1281:1281:1281) (1310:1310:1310)) + (PORT oe (1289:1289:1289) (1299:1299:1299)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -329,8 +329,8 @@ (INSTANCE GPIO_1\[27\]\~output) (DELAY (ABSOLUTE - (PORT i (1255:1255:1255) (1313:1313:1313)) - (PORT oe (1518:1518:1518) (1539:1539:1539)) + (PORT i (1292:1292:1292) (1340:1340:1340)) + (PORT oe (1411:1411:1411) (1448:1448:1448)) (IOPATH i o (2119:2119:2119) (2194:2194:2194)) (IOPATH oe o (2175:2175:2175) (2064:2064:2064)) ) @@ -341,8 +341,8 @@ (INSTANCE GPIO_1\[28\]\~output) (DELAY (ABSOLUTE - (PORT i (1602:1602:1602) (1577:1577:1577)) - (PORT oe (1787:1787:1787) (1749:1749:1749)) + (PORT i (1126:1126:1126) (1146:1146:1146)) + (PORT oe (1763:1763:1763) (1772:1772:1772)) (IOPATH i o (2180:2180:2180) (2265:2265:2265)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -353,9 +353,9 @@ (INSTANCE GPIO_1\[29\]\~output) (DELAY (ABSOLUTE - (PORT i (1357:1357:1357) (1419:1419:1419)) - (PORT oe (1250:1250:1250) (1266:1266:1266)) - (IOPATH i o (2180:2180:2180) (2277:2277:2277)) + (PORT i (1099:1099:1099) (1045:1045:1045)) + (PORT oe (1707:1707:1707) (1746:1746:1746)) + (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) ) @@ -365,8 +365,8 @@ (INSTANCE GPIO_1\[30\]\~output) (DELAY (ABSOLUTE - (PORT i (967:967:967) (940:940:940)) - (PORT oe (1226:1226:1226) (1242:1242:1242)) + (PORT i (1083:1083:1083) (1032:1032:1032)) + (PORT oe (920:920:920) (954:954:954)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -377,7 +377,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1447:1447:1447) (1410:1410:1410)) + (PORT i (1448:1448:1448) (1410:1410:1410)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -387,7 +387,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (916:916:916) (942:942:942)) + (PORT i (917:917:917) (942:942:942)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -397,7 +397,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1202:1202:1202) (1194:1194:1194)) + (PORT i (1356:1356:1356) (1406:1406:1406)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -452,7 +452,7 @@ (INSTANCE VGA_R\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1082:1082:1082) (1068:1068:1068)) + (PORT i (1034:1034:1034) (1046:1046:1046)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -462,7 +462,7 @@ (INSTANCE VGA_R\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (995:995:995) (1003:1003:1003)) + (PORT i (1049:1049:1049) (1057:1057:1057)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -472,7 +472,7 @@ (INSTANCE VGA_R\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (719:719:719) (672:672:672)) + (PORT i (805:805:805) (799:799:799)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -482,7 +482,7 @@ (INSTANCE VGA_R\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (917:917:917) (865:865:865)) + (PORT i (765:765:765) (747:747:747)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -492,7 +492,7 @@ (INSTANCE VGA_G\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (908:908:908) (871:871:871)) + (PORT i (536:536:536) (534:534:534)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -502,7 +502,7 @@ (INSTANCE VGA_G\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (670:670:670) (626:626:626)) + (PORT i (516:516:516) (516:516:516)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -512,7 +512,7 @@ (INSTANCE VGA_G\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (784:784:784) (728:728:728)) + (PORT i (1192:1192:1192) (1149:1149:1149)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -522,7 +522,7 @@ (INSTANCE VGA_G\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (784:784:784) (728:728:728)) + (PORT i (1192:1192:1192) (1149:1149:1149)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -532,7 +532,7 @@ (INSTANCE VGA_B\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (664:664:664) (633:633:633)) + (PORT i (1029:1029:1029) (1033:1033:1033)) (IOPATH i o (4033:4033:4033) (3610:3610:3610)) ) ) @@ -542,7 +542,7 @@ (INSTANCE VGA_B\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (645:645:645) (617:617:617)) + (PORT i (1156:1156:1156) (1115:1115:1115)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -552,7 +552,7 @@ (INSTANCE VGA_B\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (883:883:883) (830:830:830)) + (PORT i (1054:1054:1054) (1070:1070:1070)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -562,7 +562,7 @@ (INSTANCE VGA_B\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1278:1278:1278) (1196:1196:1196)) + (PORT i (1054:1054:1054) (1064:1064:1064)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -590,7 +590,7 @@ (INSTANCE GPIO_1\[25\]\~output) (DELAY (ABSOLUTE - (PORT i (1842:1842:1842) (1809:1809:1809)) + (PORT i (1548:1548:1548) (1532:1532:1532)) (IOPATH i o (2180:2180:2180) (2265:2265:2265)) ) ) @@ -600,7 +600,7 @@ (INSTANCE GPIO_1\[26\]\~output) (DELAY (ABSOLUTE - (PORT i (1161:1161:1161) (1186:1186:1186)) + (PORT i (1028:1028:1028) (1076:1076:1076)) (IOPATH i o (3539:3539:3539) (3961:3961:3961)) ) ) @@ -610,7 +610,7 @@ (INSTANCE GPIO_1\[31\]\~output) (DELAY (ABSOLUTE - (PORT i (862:862:862) (826:826:826)) + (PORT i (826:826:826) (776:776:776)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) ) ) @@ -620,11 +620,201 @@ (INSTANCE buzzer_out\~output) (DELAY (ABSOLUTE - (PORT i (1253:1253:1253) (1261:1261:1261)) + (PORT i (1528:1528:1528) (1518:1518:1518)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_BA\[0\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1818:1818:1818) (1733:1733:1733)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_BA\[1\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1818:1818:1818) (1733:1733:1733)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQM\[0\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1818:1818:1818) (1733:1733:1733)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQM\[1\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1818:1818:1818) (1733:1733:1733)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_RAS_N\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1872:1872:1872) (1775:1775:1775)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_CAS_N\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1872:1872:1872) (1775:1775:1775)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_CLK\~output) + (DELAY + (ABSOLUTE + (PORT i (1578:1578:1578) (1595:1595:1595)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_WE_N\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1872:1872:1872) (1775:1775:1775)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[0\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1872:1872:1872) (1775:1775:1775)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[1\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1818:1818:1818) (1733:1733:1733)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[2\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1818:1818:1818) (1733:1733:1733)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[3\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1818:1818:1818) (1733:1733:1733)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[4\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1818:1818:1818) (1733:1733:1733)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[5\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1818:1818:1818) (1733:1733:1733)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[6\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1818:1818:1818) (1733:1733:1733)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[7\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1818:1818:1818) (1733:1733:1733)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[8\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1789:1789:1789) (1714:1714:1714)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[9\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1872:1872:1872) (1775:1775:1775)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[10\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1872:1872:1872) (1775:1775:1775)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[11\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1872:1872:1872) (1775:1775:1775)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[12\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1789:1789:1789) (1714:1714:1714)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_obuf") (INSTANCE I2C_SCLK\~output) @@ -643,6 +833,182 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1156:1156:1156) (1184:1184:1184)) + (PORT oe (1586:1586:1586) (1588:1588:1588)) + (IOPATH i o (2277:2277:2277) (2180:2180:2180)) + (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1295:1295:1295) (1296:1296:1296)) + (PORT oe (1586:1586:1586) (1588:1588:1588)) + (IOPATH i o (2277:2277:2277) (2180:2180:2180)) + (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1044:1044:1044) (1027:1027:1027)) + (PORT oe (1266:1266:1266) (1273:1273:1273)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1106:1106:1106) (1135:1135:1135)) + (PORT oe (1368:1368:1368) (1397:1397:1397)) + (IOPATH i o (2194:2194:2194) (2119:2119:2119)) + (IOPATH oe o (2175:2175:2175) (2064:2064:2064)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1099:1099:1099) (1111:1111:1111)) + (PORT oe (1104:1104:1104) (1100:1100:1100)) + (IOPATH i o (2277:2277:2277) (2180:2180:2180)) + (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1316:1316:1316) (1350:1350:1350)) + (PORT oe (1293:1293:1293) (1201:1201:1201)) + (IOPATH i o (2277:2277:2277) (2180:2180:2180)) + (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1066:1066:1066) (1083:1083:1083)) + (PORT oe (1293:1293:1293) (1201:1201:1201)) + (IOPATH i o (2277:2277:2277) (2180:2180:2180)) + (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (512:512:512) (512:512:512)) + (PORT oe (1273:1273:1273) (1259:1259:1259)) + (IOPATH i o (2265:2265:2265) (2180:2180:2180)) + (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1496:1496:1496) (1514:1514:1514)) + (IOPATH i o (2180:2180:2180) (2265:2265:2265)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1317:1317:1317) (1306:1306:1306)) + (IOPATH i o (2180:2180:2180) (2265:2265:2265)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1299:1299:1299) (1285:1285:1285)) + (IOPATH i o (2180:2180:2180) (2265:2265:2265)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1299:1299:1299) (1285:1285:1285)) + (IOPATH i o (2180:2180:2180) (2265:2265:2265)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1468:1468:1468) (1513:1513:1513)) + (IOPATH i o (2180:2180:2180) (2265:2265:2265)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1490:1490:1490) (1505:1505:1505)) + (IOPATH i o (2180:2180:2180) (2265:2265:2265)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[14\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1490:1490:1490) (1505:1505:1505)) + (IOPATH i o (2180:2180:2180) (2265:2265:2265)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[15\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1100:1100:1100) (1104:1104:1104)) + (IOPATH i o (2180:2180:2180) (2277:2277:2277)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE CLOCK_50\~input) @@ -707,8 +1073,8 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~0) (DELAY (ABSOLUTE - (PORT datab (223:223:223) (293:293:293)) - (PORT datad (493:493:493) (526:526:526)) + (PORT datab (222:222:222) (291:291:291)) + (PORT datad (492:492:492) (527:527:527)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -734,32 +1100,7 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (655:655:655) (669:669:669)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1052:1052:1052) (1052:1052:1052)) - (PORT datad (1052:1052:1052) (1044:1044:1044)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|ena_M) - (DELAY - (ABSOLUTE - (PORT datac (1029:1029:1029) (1028:1028:1028)) - (PORT datad (1049:1049:1049) (1040:1040:1040)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT inclk[0] (658:658:658) (673:673:673)) ) ) ) @@ -772,10573 +1113,6 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT dataa (321:321:321) (448:448:448)) - (PORT datad (1849:1849:1849) (1871:1871:1871)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|nmi_armed) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1338:1338:1338)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1229:1229:1229) (1175:1175:1175)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (736:736:736) (745:745:745)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) - (DELAY - (ABSOLUTE - (PORT datac (219:219:219) (288:288:288)) - (PORT datad (226:226:226) (290:290:290)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (2229:2229:2229) (2292:2292:2292)) - (PORT datab (2226:2226:2226) (2286:2286:2286)) - (PORT datad (1468:1468:1468) (1557:1557:1557)) - (IOPATH dataa combout (267:267:267) (273:273:273)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M3_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1045:1045:1045) (1047:1047:1047)) - (PORT datab (378:378:378) (425:425:425)) - (PORT datad (1056:1056:1056) (1045:1045:1045)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M3_ff) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1383:1383:1383)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1262:1262:1262) (1213:1213:1213)) - (PORT datab (1423:1423:1423) (1478:1478:1478)) - (PORT datac (1249:1249:1249) (1279:1279:1279)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M4_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1060:1060:1060) (1066:1066:1066)) - (PORT datab (379:379:379) (433:433:433)) - (PORT datad (1043:1043:1043) (1031:1031:1031)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M4_ff) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1383:1383:1383)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal32\~0) - (DELAY - (ABSOLUTE - (PORT datab (360:360:360) (412:412:412)) - (PORT datad (612:612:612) (661:661:661)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) - (DELAY - (ABSOLUTE - (PORT datab (2400:2400:2400) (2429:2429:2429)) - (PORT datad (1482:1482:1482) (1552:1552:1552)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|table_xx\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1268:1268:1268) (1344:1344:1344)) - (PORT datad (1113:1113:1113) (1173:1173:1173)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1551:1551:1551) (1547:1547:1547)) - (PORT datab (863:863:863) (876:876:876)) - (PORT datac (1969:1969:1969) (2066:2066:2066)) - (PORT datad (1075:1075:1075) (1083:1083:1083)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT datac (1336:1336:1336) (1371:1371:1371)) - (PORT datad (2093:2093:2093) (2156:2156:2156)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal36\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1200:1200:1200)) - (PORT datab (1518:1518:1518) (1601:1601:1601)) - (PORT datac (834:834:834) (865:865:865)) - (PORT datad (878:878:878) (895:895:895)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) - (DELAY - (ABSOLUTE - (PORT dataa (1601:1601:1601) (1614:1614:1614)) - (PORT datab (1315:1315:1315) (1312:1312:1312)) - (PORT datac (783:783:783) (794:794:794)) - (PORT datad (731:731:731) (698:698:698)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1132:1132:1132) (1169:1169:1169)) - (PORT datab (2443:2443:2443) (2464:2464:2464)) - (PORT datac (781:781:781) (791:791:791)) - (PORT datad (898:898:898) (951:951:951)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instCB) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1371:1371:1371)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~0) - (DELAY - (ABSOLUTE - (PORT dataa (662:662:662) (725:725:725)) - (PORT datab (1149:1149:1149) (1197:1197:1197)) - (PORT datac (897:897:897) (935:935:935)) - (PORT datad (1227:1227:1227) (1306:1306:1306)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2170:2170:2170) (2236:2236:2236)) - (PORT datab (1514:1514:1514) (1603:1603:1603)) - (PORT datac (834:834:834) (863:863:863)) - (PORT datad (622:622:622) (647:647:647)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) - (DELAY - (ABSOLUTE - (PORT dataa (1618:1618:1618) (1654:1654:1654)) - (PORT datab (780:780:780) (764:764:764)) - (PORT datac (1286:1286:1286) (1282:1282:1282)) - (PORT datad (1889:1889:1889) (1943:1943:1943)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instED) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1371:1371:1371)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (728:728:728)) - (PORT datac (890:890:890) (927:927:927)) - (PORT datad (1223:1223:1223) (1301:1301:1301)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2001:2001:2001) (2098:2098:2098)) - (PORT datac (1337:1337:1337) (1368:1368:1368)) - (PORT datad (2095:2095:2095) (2153:2153:2153)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_im_we) - (DELAY - (ABSOLUTE - (PORT dataa (564:564:564) (569:569:569)) - (PORT datab (972:972:972) (1033:1033:1033)) - (PORT datac (1235:1235:1235) (1324:1324:1324)) - (PORT datad (850:850:850) (879:879:879)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal49\~0) - (DELAY - (ABSOLUTE - (PORT datab (917:917:917) (979:979:979)) - (PORT datac (601:601:601) (640:640:640)) - (PORT datad (1151:1151:1151) (1208:1208:1208)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1302:1302:1302) (1348:1348:1348)) - (PORT datab (1375:1375:1375) (1421:1421:1421)) - (PORT datac (1321:1321:1321) (1379:1379:1379)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (662:662:662) (725:725:725)) - (PORT datab (1149:1149:1149) (1197:1197:1197)) - (PORT datac (897:897:897) (936:936:936)) - (PORT datad (1227:1227:1227) (1307:1307:1307)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1167:1167:1167)) - (PORT datab (1177:1177:1177) (1243:1243:1243)) - (PORT datad (653:653:653) (694:694:694)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2447:2447:2447) (2537:2537:2537)) - (PORT datab (821:821:821) (835:835:835)) - (PORT datac (1028:1028:1028) (1065:1065:1065)) - (PORT datad (1063:1063:1063) (1082:1082:1082)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (923:923:923)) - (PORT datab (1440:1440:1440) (1502:1502:1502)) - (PORT datac (1299:1299:1299) (1315:1315:1315)) - (PORT datad (182:182:182) (214:214:214)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|nM1_int\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1028:1028:1028) (1119:1119:1119)) - (PORT datad (1947:1947:1947) (2004:2004:2004)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1001:1001:1001) (1052:1052:1052)) - (PORT datab (1029:1029:1029) (1024:1024:1024)) - (PORT datac (310:310:310) (319:319:319)) - (PORT datad (638:638:638) (672:672:672)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT datac (1314:1314:1314) (1383:1383:1383)) - (PORT datad (1350:1350:1350) (1411:1411:1411)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1153:1153:1153) (1191:1191:1191)) - (PORT datab (1516:1516:1516) (1601:1601:1601)) - (PORT datac (1576:1576:1576) (1593:1593:1593)) - (PORT datad (879:879:879) (897:897:897)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~7) - (DELAY - (ABSOLUTE - (PORT datac (1830:1830:1830) (1949:1949:1949)) - (PORT datad (1139:1139:1139) (1170:1170:1170)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1785:1785:1785) (1823:1823:1823)) - (PORT datac (2376:2376:2376) (2399:2399:2399)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (835:835:835)) - (PORT datab (947:947:947) (992:992:992)) - (PORT datac (779:779:779) (830:830:830)) - (PORT datad (859:859:859) (876:876:876)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~1) - (DELAY - (ABSOLUTE - (PORT dataa (836:836:836) (842:842:842)) - (PORT datab (821:821:821) (826:826:826)) - (PORT datac (838:838:838) (890:890:890)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (841:841:841)) - (PORT datab (824:824:824) (822:822:822)) - (PORT datac (839:839:839) (888:888:888)) - (PORT datad (1082:1082:1082) (1087:1087:1087)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (807:807:807)) - (PORT datac (904:904:904) (936:936:936)) - (PORT datad (1074:1074:1074) (1054:1054:1054)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2000:2000:2000) (2094:2094:2094)) - (PORT datac (1337:1337:1337) (1365:1365:1365)) - (PORT datad (2091:2091:2091) (2150:2150:2150)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~2) - (DELAY - (ABSOLUTE - (PORT dataa (807:807:807) (861:861:861)) - (PORT datab (1587:1587:1587) (1615:1615:1615)) - (PORT datac (1051:1051:1051) (1035:1035:1035)) - (PORT datad (602:602:602) (618:618:618)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (871:871:871)) - (PORT datab (2149:2149:2149) (2219:2219:2219)) - (PORT datac (1578:1578:1578) (1596:1596:1596)) - (PORT datad (618:618:618) (643:643:643)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1186:1186:1186)) - (PORT datab (1912:1912:1912) (2034:2034:2034)) - (PORT datac (798:798:798) (784:784:784)) - (PORT datad (1339:1339:1339) (1371:1371:1371)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~8) - (DELAY - (ABSOLUTE - (PORT datab (1310:1310:1310) (1338:1338:1338)) - (PORT datac (1438:1438:1438) (1451:1451:1451)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~6) - (DELAY - (ABSOLUTE - (PORT datac (1484:1484:1484) (1509:1509:1509)) - (PORT datad (1740:1740:1740) (1785:1785:1785)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~9) - (DELAY - (ABSOLUTE - (PORT datac (951:951:951) (1008:1008:1008)) - (PORT datad (910:910:910) (938:938:938)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (924:924:924) (955:955:955)) - (PORT datab (917:917:917) (933:933:933)) - (PORT datac (837:837:837) (836:836:836)) - (PORT datad (1899:1899:1899) (1915:1915:1915)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (411:411:411)) - (PORT datab (1065:1065:1065) (1080:1080:1080)) - (PORT datac (573:573:573) (605:605:605)) - (PORT datad (1017:1017:1017) (1034:1034:1034)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal44\~0) - (DELAY - (ABSOLUTE - (PORT dataa (662:662:662) (727:727:727)) - (PORT datab (1154:1154:1154) (1202:1202:1202)) - (PORT datac (891:891:891) (928:928:928)) - (PORT datad (1223:1223:1223) (1302:1302:1302)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~16) - (DELAY - (ABSOLUTE - (PORT dataa (896:896:896) (972:972:972)) - (PORT datab (1230:1230:1230) (1207:1207:1207)) - (PORT datac (856:856:856) (914:914:914)) - (PORT datad (1025:1025:1025) (1004:1004:1004)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~13) - (DELAY - (ABSOLUTE - (PORT datab (773:773:773) (797:797:797)) - (PORT datac (572:572:572) (595:595:595)) - (PORT datad (192:192:192) (222:222:222)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal50\~0) - (DELAY - (ABSOLUTE - (PORT datab (918:918:918) (983:983:983)) - (PORT datac (602:602:602) (637:637:637)) - (PORT datad (1080:1080:1080) (1127:1127:1127)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1166:1166:1166)) - (PORT datab (1178:1178:1178) (1243:1243:1243)) - (PORT datad (653:653:653) (694:694:694)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~17) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (961:961:961)) - (PORT datab (1021:1021:1021) (990:990:990)) - (PORT datac (854:854:854) (908:908:908)) - (PORT datad (1001:1001:1001) (970:970:970)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~5) - (DELAY - (ABSOLUTE - (PORT datac (1464:1464:1464) (1537:1537:1537)) - (PORT datad (909:909:909) (938:938:938)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (568:568:568) (600:600:600)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (1021:1021:1021) (995:995:995)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1465:1465:1465) (1484:1484:1484)) - (PORT datab (1312:1312:1312) (1341:1341:1341)) - (PORT datac (350:350:350) (354:354:354)) - (PORT datad (1660:1660:1660) (1718:1718:1718)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1006:1006:1006) (1006:1006:1006)) - (PORT datab (212:212:212) (254:254:254)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1185:1185:1185) (1234:1234:1234)) - (PORT datab (1381:1381:1381) (1410:1410:1410)) - (PORT datac (1348:1348:1348) (1401:1401:1401)) - (PORT datad (1893:1893:1893) (2005:2005:2005)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instIY1) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1407:1407:1407) (1373:1373:1373)) - (PORT ena (745:745:745) (752:752:752)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (812:812:812) (851:851:851)) - (PORT datac (591:591:591) (628:628:628)) - (PORT datad (1268:1268:1268) (1330:1330:1330)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1163:1163:1163) (1209:1209:1209)) - (PORT datab (418:418:418) (465:465:465)) - (PORT datac (1561:1561:1561) (1571:1571:1571)) - (PORT datad (244:244:244) (293:293:293)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (710:710:710)) - (PORT datab (925:925:925) (963:963:963)) - (PORT datac (632:632:632) (694:694:694)) - (PORT datad (1226:1226:1226) (1304:1304:1304)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1491:1491:1491) (1603:1603:1603)) - (PORT datab (1405:1405:1405) (1444:1444:1444)) - (PORT datac (1574:1574:1574) (1628:1628:1628)) - (PORT datad (1380:1380:1380) (1457:1457:1457)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1201:1201:1201) (1253:1253:1253)) - (PORT datab (1150:1150:1150) (1183:1183:1183)) - (PORT datac (957:957:957) (983:983:983)) - (PORT datad (1554:1554:1554) (1554:1554:1554)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~26) - (DELAY - (ABSOLUTE - (PORT datac (625:625:625) (655:655:655)) - (PORT datad (1595:1595:1595) (1666:1666:1666)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (593:593:593)) - (PORT datac (1016:1016:1016) (1041:1041:1041)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (227:227:227)) - (PORT datab (218:218:218) (262:262:262)) - (PORT datac (616:616:616) (628:628:628)) - (PORT datad (1898:1898:1898) (1914:1914:1914)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (927:927:927) (960:960:960)) - (PORT datab (1142:1142:1142) (1138:1138:1138)) - (PORT datac (627:627:627) (661:661:661)) - (PORT datad (164:164:164) (186:186:186)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (921:921:921)) - (PORT datab (1436:1436:1436) (1502:1502:1502)) - (PORT datac (1297:1297:1297) (1313:1313:1313)) - (PORT datad (184:184:184) (214:214:214)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal55\~0) - (DELAY - (ABSOLUTE - (PORT dataa (261:261:261) (346:346:346)) - (PORT datac (833:833:833) (861:861:861)) - (PORT datad (852:852:852) (878:878:878)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1621:1621:1621) (1670:1670:1670)) - (PORT datac (1054:1054:1054) (1097:1097:1097)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (597:597:597)) - (PORT datab (1083:1083:1083) (1081:1081:1081)) - (PORT datac (858:858:858) (922:922:922)) - (PORT datad (166:166:166) (192:192:192)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (638:638:638)) - (PORT datab (601:601:601) (604:604:604)) - (PORT datac (859:859:859) (924:924:924)) - (PORT datad (829:829:829) (826:826:826)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (864:864:864) (868:868:868)) - (PORT datab (1107:1107:1107) (1080:1080:1080)) - (PORT datac (1672:1672:1672) (1725:1725:1725)) - (PORT datad (807:807:807) (820:820:820)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1556:1556:1556) (1580:1580:1580)) - (PORT datac (1522:1522:1522) (1548:1548:1548)) - (PORT datad (1081:1081:1081) (1109:1109:1109)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~0) - (DELAY - (ABSOLUTE - (PORT datac (767:767:767) (786:786:786)) - (PORT datad (825:825:825) (873:873:873)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1554:1554:1554) (1584:1584:1584)) - (PORT datab (1552:1552:1552) (1580:1580:1580)) - (PORT datac (1363:1363:1363) (1419:1419:1419)) - (PORT datad (1142:1142:1142) (1162:1162:1162)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1359:1359:1359) (1387:1387:1387)) - (PORT datab (1132:1132:1132) (1189:1189:1189)) - (PORT datac (1315:1315:1315) (1370:1370:1370)) - (PORT datad (770:770:770) (747:747:747)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (827:827:827) (808:808:808)) - (PORT datab (1149:1149:1149) (1166:1166:1166)) - (PORT datac (1267:1267:1267) (1245:1245:1245)) - (PORT datad (1175:1175:1175) (1183:1183:1183)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~1) - (DELAY - (ABSOLUTE - (PORT dataa (570:570:570) (590:590:590)) - (PORT datab (881:881:881) (942:942:942)) - (PORT datad (1060:1060:1060) (1048:1048:1048)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1442:1442:1442) (1476:1476:1476)) - (PORT datab (917:917:917) (932:932:932)) - (PORT datac (1484:1484:1484) (1570:1570:1570)) - (PORT datad (1129:1129:1129) (1157:1157:1157)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal25\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1344:1344:1344) (1415:1415:1415)) - (PORT datab (1421:1421:1421) (1497:1497:1497)) - (PORT datac (1271:1271:1271) (1288:1288:1288)) - (PORT datad (1447:1447:1447) (1437:1437:1437)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (819:819:819)) - (PORT datab (1683:1683:1683) (1701:1701:1701)) - (PORT datac (805:805:805) (790:790:790)) - (PORT datad (1375:1375:1375) (1390:1390:1390)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1167:1167:1167)) - (PORT datac (876:876:876) (907:907:907)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~0) - (DELAY - (ABSOLUTE - (PORT dataa (869:869:869) (865:865:865)) - (PORT datab (863:863:863) (893:893:893)) - (PORT datac (1483:1483:1483) (1575:1575:1575)) - (PORT datad (1128:1128:1128) (1157:1157:1157)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~4) - (DELAY - (ABSOLUTE - (PORT datac (1578:1578:1578) (1613:1613:1613)) - (PORT datad (1886:1886:1886) (1938:1938:1938)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal29\~0) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (237:237:237)) - (PORT datab (1078:1078:1078) (1072:1072:1072)) - (PORT datac (1486:1486:1486) (1452:1452:1452)) - (PORT datad (1339:1339:1339) (1387:1387:1387)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1441:1441:1441) (1474:1474:1474)) - (PORT datab (913:913:913) (929:929:929)) - (PORT datac (1483:1483:1483) (1581:1581:1581)) - (PORT datad (1134:1134:1134) (1164:1164:1164)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal34\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2001:2001:2001) (2097:2097:2097)) - (PORT datab (865:865:865) (881:881:881)) - (PORT datac (175:175:175) (206:206:206)) - (PORT datad (385:385:385) (421:421:421)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (453:453:453)) - (PORT datab (863:863:863) (875:875:875)) - (PORT datac (1973:1973:1973) (2062:2062:2062)) - (PORT datad (1053:1053:1053) (1052:1052:1052)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal35\~0) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (452:452:452)) - (PORT datab (863:863:863) (876:876:876)) - (PORT datac (1969:1969:1969) (2064:2064:2064)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal38\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1493:1493:1493) (1602:1602:1602)) - (PORT datab (1418:1418:1418) (1497:1497:1497)) - (PORT datac (1573:1573:1573) (1625:1625:1625)) - (PORT datad (1334:1334:1334) (1354:1354:1354)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1033:1033:1033) (1015:1015:1015)) - (PORT datab (1013:1013:1013) (1053:1053:1053)) - (PORT datac (546:546:546) (546:546:546)) - (PORT datad (822:822:822) (842:842:842)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (800:800:800) (821:821:821)) - (PORT datab (1265:1265:1265) (1297:1297:1297)) - (PORT datac (543:543:543) (561:561:561)) - (PORT datad (547:547:547) (536:536:536)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~0) - (DELAY - (ABSOLUTE - (PORT datab (1792:1792:1792) (1827:1827:1827)) - (PORT datac (1077:1077:1077) (1135:1135:1135)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (461:461:461)) - (PORT datab (865:865:865) (881:881:881)) - (PORT datac (1972:1972:1972) (2061:2061:2061)) - (PORT datad (340:340:340) (342:342:342)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1189:1189:1189) (1227:1227:1227)) - (PORT datab (1119:1119:1119) (1117:1117:1117)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (1173:1173:1173) (1221:1221:1221)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (636:636:636)) - (PORT datab (594:594:594) (585:585:585)) - (PORT datac (163:163:163) (197:197:197)) - (PORT datad (1082:1082:1082) (1083:1083:1083)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (869:869:869)) - (PORT datab (208:208:208) (254:254:254)) - (PORT datac (576:576:576) (584:584:584)) - (PORT datad (603:603:603) (621:621:621)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (1339:1339:1339) (1327:1327:1327)) - (PORT datab (1126:1126:1126) (1187:1187:1187)) - (PORT datac (631:631:631) (657:657:657)) - (PORT datad (1056:1056:1056) (1051:1051:1051)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (680:680:680)) - (PORT datab (1062:1062:1062) (1049:1049:1049)) - (PORT datac (1678:1678:1678) (1728:1728:1728)) - (PORT datad (540:540:540) (545:545:545)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1345:1345:1345) (1407:1407:1407)) - (PORT datab (1044:1044:1044) (1070:1070:1070)) - (PORT datac (1099:1099:1099) (1163:1163:1163)) - (PORT datad (600:600:600) (626:626:626)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1351:1351:1351) (1413:1413:1413)) - (PORT datab (628:628:628) (661:661:661)) - (PORT datac (1097:1097:1097) (1155:1155:1155)) - (PORT datad (1294:1294:1294) (1285:1285:1285)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|M5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1055:1055:1055) (1060:1060:1060)) - (PORT datab (243:243:243) (313:313:313)) - (PORT datad (1055:1055:1055) (1041:1041:1041)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|M5) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1383:1383:1383)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) - (DELAY - (ABSOLUTE - (PORT datab (1460:1460:1460) (1548:1548:1548)) - (PORT datac (2403:2403:2403) (2409:2409:2409)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~29) - (DELAY - (ABSOLUTE - (PORT dataa (599:599:599) (596:596:596)) - (PORT datab (866:866:866) (895:895:895)) - (PORT datac (934:934:934) (949:949:949)) - (PORT datad (608:608:608) (635:635:635)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1795:1795:1795) (1857:1857:1857)) - (PORT datab (633:633:633) (669:669:669)) - (PORT datac (612:612:612) (643:643:643)) - (PORT datad (551:551:551) (551:551:551)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1769:1769:1769) (1771:1771:1771)) - (PORT datab (824:824:824) (869:869:869)) - (PORT datac (174:174:174) (206:206:206)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1212:1212:1212)) - (PORT datab (419:419:419) (463:463:463)) - (PORT datac (1560:1560:1560) (1572:1572:1572)) - (PORT datad (242:242:242) (294:294:294)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1269:1269:1269) (1344:1344:1344)) - (PORT datab (863:863:863) (909:909:909)) - (PORT datac (889:889:889) (907:907:907)) - (PORT datad (1117:1117:1117) (1173:1173:1173)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~14) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (968:968:968)) - (PORT datab (1229:1229:1229) (1209:1209:1209)) - (PORT datac (851:851:851) (913:913:913)) - (PORT datad (1024:1024:1024) (1000:1000:1000)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (588:588:588) (598:598:598)) - (PORT datab (1162:1162:1162) (1169:1169:1169)) - (PORT datac (524:524:524) (520:520:520)) - (PORT datad (1507:1507:1507) (1516:1516:1516)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~0) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (713:713:713)) - (PORT datab (199:199:199) (233:233:233)) - (PORT datac (231:231:231) (314:314:314)) - (PORT datad (826:826:826) (839:839:839)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (845:845:845)) - (PORT datab (1015:1015:1015) (1057:1057:1057)) - (PORT datac (1018:1018:1018) (1024:1024:1024)) - (PORT datad (622:622:622) (638:638:638)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (438:438:438)) - (PORT datab (1792:1792:1792) (1867:1867:1867)) - (PORT datac (958:958:958) (971:971:971)) - (PORT datad (1445:1445:1445) (1464:1464:1464)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (886:886:886)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (822:822:822) (840:840:840)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (602:602:602)) - (PORT datab (1112:1112:1112) (1118:1118:1118)) - (PORT datac (185:185:185) (225:225:225)) - (PORT datad (578:578:578) (592:592:592)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (408:408:408)) - (PORT datab (1081:1081:1081) (1087:1087:1087)) - (PORT datac (571:571:571) (603:603:603)) - (PORT datad (1022:1022:1022) (1035:1035:1035)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1492:1492:1492) (1602:1602:1602)) - (PORT datab (1404:1404:1404) (1447:1447:1447)) - (PORT datac (1574:1574:1574) (1625:1625:1625)) - (PORT datad (1378:1378:1378) (1458:1458:1458)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1491:1491:1491) (1604:1604:1604)) - (PORT datab (1406:1406:1406) (1443:1443:1443)) - (PORT datac (1575:1575:1575) (1624:1624:1624)) - (PORT datad (1381:1381:1381) (1455:1455:1455)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1563:1563:1563) (1599:1599:1599)) - (PORT datab (1362:1362:1362) (1404:1404:1404)) - (PORT datac (2378:2378:2378) (2398:2398:2398)) - (PORT datad (1743:1743:1743) (1779:1779:1779)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (602:602:602)) - (PORT datab (1161:1161:1161) (1170:1170:1170)) - (PORT datac (1041:1041:1041) (1032:1032:1032)) - (PORT datad (523:523:523) (506:506:506)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1212:1212:1212)) - (PORT datab (419:419:419) (462:462:462)) - (PORT datac (1561:1561:1561) (1572:1572:1572)) - (PORT datad (241:241:241) (293:293:293)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1028:1028:1028) (1044:1044:1044)) - (PORT datab (1056:1056:1056) (1076:1076:1076)) - (PORT datac (507:507:507) (487:487:487)) - (PORT datad (565:565:565) (562:562:562)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (265:265:265) (325:325:325)) - (PORT datab (421:421:421) (461:461:461)) - (PORT datac (173:173:173) (203:203:203)) - (PORT datad (1271:1271:1271) (1327:1327:1327)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal46\~0) - (DELAY - (ABSOLUTE - (PORT dataa (259:259:259) (342:342:342)) - (PORT datab (875:875:875) (908:908:908)) - (PORT datac (836:836:836) (860:860:860)) - (PORT datad (1108:1108:1108) (1167:1167:1167)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1156:1156:1156) (1205:1205:1205)) - (PORT datab (794:794:794) (808:808:808)) - (PORT datac (1564:1564:1564) (1573:1573:1573)) - (PORT datad (242:242:242) (287:287:287)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1957:1957:1957) (1991:1991:1991)) - (PORT datab (1894:1894:1894) (1936:1936:1936)) - (PORT datac (896:896:896) (945:945:945)) - (PORT datad (1119:1119:1119) (1134:1134:1134)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1279:1279:1279) (1291:1291:1291)) - (PORT datab (978:978:978) (1022:1022:1022)) - (PORT datac (711:711:711) (680:680:680)) - (PORT datad (1137:1137:1137) (1143:1143:1143)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (907:907:907) (947:947:947)) - (PORT datac (1064:1064:1064) (1085:1085:1085)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (269:269:269) (332:332:332)) - (PORT datab (420:420:420) (460:460:460)) - (PORT datac (1115:1115:1115) (1139:1139:1139)) - (PORT datad (1266:1266:1266) (1324:1324:1324)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1041:1041:1041) (1136:1136:1136)) - (PORT datab (2035:2035:2035) (2054:2054:2054)) - (PORT datac (1230:1230:1230) (1285:1285:1285)) - (PORT datad (884:884:884) (922:922:922)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1669:1669:1669) (1692:1692:1692)) - (PORT datab (1199:1199:1199) (1213:1213:1213)) - (PORT datac (1267:1267:1267) (1246:1246:1246)) - (PORT datad (814:814:814) (797:797:797)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (564:564:564) (562:562:562)) - (PORT datac (510:510:510) (508:508:508)) - (PORT datad (1141:1141:1141) (1159:1159:1159)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (218:218:218)) - (PORT datab (200:200:200) (232:232:232)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (188:188:188) (225:225:225)) - (PORT datac (793:793:793) (783:783:783)) - (PORT datad (788:788:788) (795:795:795)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) - (DELAY - (ABSOLUTE - (PORT datac (1912:1912:1912) (1952:1952:1952)) - (PORT datad (880:880:880) (918:918:918)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1483:1483:1483) (1600:1600:1600)) - (PORT datab (1404:1404:1404) (1443:1443:1443)) - (PORT datac (1566:1566:1566) (1623:1623:1623)) - (PORT datad (1374:1374:1374) (1455:1455:1455)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~9) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (655:655:655)) - (PORT datab (1379:1379:1379) (1404:1404:1404)) - (PORT datac (1050:1050:1050) (1096:1096:1096)) - (PORT datad (1279:1279:1279) (1264:1264:1264)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1976:1976:1976) (2058:2058:2058)) - (PORT datab (622:622:622) (670:670:670)) - (PORT datac (1582:1582:1582) (1588:1588:1588)) - (PORT datad (185:185:185) (212:212:212)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1183:1183:1183) (1233:1233:1233)) - (PORT datad (1885:1885:1885) (1995:1995:1995)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (885:885:885)) - (PORT datab (419:419:419) (435:435:435)) - (PORT datac (369:369:369) (398:398:398)) - (PORT datad (1436:1436:1436) (1448:1448:1448)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (593:593:593)) - (PORT datab (1062:1062:1062) (1073:1073:1073)) - (PORT datac (1335:1335:1335) (1345:1345:1345)) - (PORT datad (312:312:312) (324:324:324)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~7) - (DELAY - (ABSOLUTE - (PORT datac (1401:1401:1401) (1456:1456:1456)) - (PORT datad (1072:1072:1072) (1084:1084:1084)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1166:1166:1166) (1212:1212:1212)) - (PORT datab (794:794:794) (806:806:806)) - (PORT datac (1559:1559:1559) (1567:1567:1567)) - (PORT datad (244:244:244) (294:294:294)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1165:1165:1165) (1211:1211:1211)) - (PORT datab (419:419:419) (460:460:460)) - (PORT datac (1559:1559:1559) (1568:1568:1568)) - (PORT datad (248:248:248) (293:293:293)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1311:1311:1311) (1310:1310:1310)) - (PORT datab (1018:1018:1018) (1005:1005:1005)) - (PORT datac (995:995:995) (972:972:972)) - (PORT datad (868:868:868) (909:909:909)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (658:658:658)) - (PORT datab (1076:1076:1076) (1125:1125:1125)) - (PORT datac (1339:1339:1339) (1351:1351:1351)) - (PORT datad (1353:1353:1353) (1375:1375:1375)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (375:375:375)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (571:571:571) (590:590:590)) - (PORT datad (170:170:170) (198:198:198)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (529:529:529) (528:528:528)) - (PORT datab (799:799:799) (782:782:782)) - (PORT datac (788:788:788) (812:812:812)) - (PORT datad (747:747:747) (739:739:739)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1069:1069:1069) (1062:1062:1062)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (169:169:169) (209:209:209)) - (PORT datad (164:164:164) (186:186:186)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (320:320:320) (440:440:440)) - (PORT datab (1127:1127:1127) (1143:1143:1143)) - (PORT datac (630:630:630) (641:641:641)) - (PORT datad (1195:1195:1195) (1262:1262:1262)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~8) - (DELAY - (ABSOLUTE - (PORT datab (2689:2689:2689) (2747:2747:2747)) - (PORT datac (1865:1865:1865) (1891:1891:1891)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1749:1749:1749) (1741:1741:1741)) - (PORT datab (1929:1929:1929) (1999:1999:1999)) - (PORT datac (1035:1035:1035) (1006:1006:1006)) - (PORT datad (188:188:188) (215:215:215)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) - (DELAY - (ABSOLUTE - (PORT datac (1142:1142:1142) (1188:1188:1188)) - (PORT datad (578:578:578) (592:592:592)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1097:1097:1097) (1115:1115:1115)) - (PORT datab (845:845:845) (865:865:865)) - (PORT datac (1866:1866:1866) (1858:1858:1858)) - (PORT datad (1360:1360:1360) (1373:1373:1373)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) - (DELAY - (ABSOLUTE - (PORT dataa (975:975:975) (1040:1040:1040)) - (PORT datab (2198:2198:2198) (2252:2252:2252)) - (PORT datad (1951:1951:1951) (2009:2009:2009)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1369:1369:1369) (1399:1399:1399)) - (PORT datab (934:934:934) (962:962:962)) - (PORT datac (824:824:824) (840:840:840)) - (PORT datad (1077:1077:1077) (1057:1057:1057)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1337:1337:1337) (1317:1317:1317)) - (PORT datab (1045:1045:1045) (1069:1069:1069)) - (PORT datac (313:313:313) (327:327:327)) - (PORT datad (1050:1050:1050) (1046:1046:1046)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (371:371:371)) - (PORT datab (1005:1005:1005) (1005:1005:1005)) - (PORT datac (1453:1453:1453) (1473:1473:1473)) - (PORT datad (754:754:754) (748:748:748)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (1057:1057:1057) (1058:1058:1058)) - (PORT datab (1080:1080:1080) (1081:1081:1081)) - (PORT datac (784:784:784) (792:792:792)) - (PORT datad (748:748:748) (744:744:744)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1095:1095:1095)) - (PORT datab (247:247:247) (316:316:316)) - (PORT datac (224:224:224) (279:279:279)) - (PORT datad (230:230:230) (267:267:267)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) - (DELAY - (ABSOLUTE - (PORT datac (876:876:876) (907:907:907)) - (PORT datad (1861:1861:1861) (1900:1900:1900)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (799:799:799) (807:807:807)) - (PORT datab (935:935:935) (964:964:964)) - (PORT datac (1128:1128:1128) (1143:1143:1143)) - (PORT datad (1076:1076:1076) (1053:1053:1053)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) - (DELAY - (ABSOLUTE - (PORT datab (200:200:200) (232:232:232)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1114:1114:1114)) - (PORT datab (936:936:936) (965:965:965)) - (PORT datac (1864:1864:1864) (1858:1858:1858)) - (PORT datad (1360:1360:1360) (1376:1376:1376)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1201:1201:1201) (1242:1242:1242)) - (PORT datab (1088:1088:1088) (1118:1118:1118)) - (PORT datac (782:782:782) (781:781:781)) - (PORT datad (1227:1227:1227) (1301:1301:1301)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (896:896:896)) - (PORT datab (883:883:883) (907:907:907)) - (PORT datac (1114:1114:1114) (1158:1158:1158)) - (PORT datad (607:607:607) (628:628:628)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1254:1254:1254) (1342:1342:1342)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (356:356:356) (362:362:362)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal69\~0) - (DELAY - (ABSOLUTE - (PORT dataa (803:803:803) (857:857:857)) - (PORT datab (1584:1584:1584) (1611:1611:1611)) - (PORT datac (1047:1047:1047) (1030:1030:1030)) - (PORT datad (605:605:605) (621:621:621)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1105:1105:1105) (1153:1153:1153)) - (PORT datad (1097:1097:1097) (1114:1114:1114)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) - (DELAY - (ABSOLUTE - (PORT dataa (935:935:935) (946:946:946)) - (PORT datab (1862:1862:1862) (1865:1865:1865)) - (PORT datac (1051:1051:1051) (1035:1035:1035)) - (PORT datad (602:602:602) (618:618:618)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1626:1626:1626) (1696:1696:1696)) - (PORT datab (862:862:862) (871:871:871)) - (PORT datad (197:197:197) (219:219:219)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal56\~0) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (640:640:640)) - (PORT datab (1083:1083:1083) (1081:1081:1081)) - (PORT datac (857:857:857) (921:921:921)) - (PORT datad (843:843:843) (863:863:863)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1361:1361:1361) (1388:1388:1388)) - (PORT datab (1126:1126:1126) (1184:1184:1184)) - (PORT datac (1320:1320:1320) (1376:1376:1376)) - (PORT datad (766:766:766) (743:743:743)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~2) - (DELAY - (ABSOLUTE - (PORT dataa (763:763:763) (765:765:765)) - (PORT datab (785:785:785) (803:803:803)) - (PORT datad (612:612:612) (635:635:635)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1851:1851:1851) (1879:1879:1879)) - (PORT datab (1944:1944:1944) (1958:1958:1958)) - (PORT datac (513:513:513) (506:506:506)) - (PORT datad (1594:1594:1594) (1608:1608:1608)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (798:798:798)) - (PORT datab (877:877:877) (901:901:901)) - (PORT datac (160:160:160) (193:193:193)) - (PORT datad (1351:1351:1351) (1370:1370:1370)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~5) - (DELAY - (ABSOLUTE - (PORT datac (1076:1076:1076) (1085:1085:1085)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1170:1170:1170)) - (PORT datab (912:912:912) (976:976:976)) - (PORT datac (603:603:603) (636:636:636)) - (PORT datad (1148:1148:1148) (1203:1203:1203)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) - (DELAY - (ABSOLUTE - (PORT datab (996:996:996) (1071:1071:1071)) - (PORT datac (1357:1357:1357) (1402:1402:1402)) - (PORT datad (2154:2154:2154) (2212:2212:2212)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (656:656:656)) - (PORT datab (1652:1652:1652) (1651:1651:1651)) - (PORT datac (898:898:898) (950:950:950)) - (PORT datad (1119:1119:1119) (1138:1138:1138)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (934:934:934) (980:980:980)) - (PORT datab (1157:1157:1157) (1169:1169:1169)) - (PORT datac (1014:1014:1014) (1031:1031:1031)) - (PORT datad (168:168:168) (192:192:192)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (880:880:880)) - (PORT datab (1011:1011:1011) (1050:1050:1050)) - (PORT datac (912:912:912) (952:952:952)) - (PORT datad (1082:1082:1082) (1086:1086:1086)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) - (DELAY - (ABSOLUTE - (PORT dataa (938:938:938) (980:980:980)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (1152:1152:1152) (1191:1191:1191)) - (PORT datad (973:973:973) (1014:1014:1014)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) - (DELAY - (ABSOLUTE - (PORT datab (1410:1410:1410) (1479:1479:1479)) - (PORT datac (1389:1389:1389) (1444:1444:1444)) - (PORT datad (1204:1204:1204) (1168:1168:1168)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (741:741:741) (740:740:740)) - (PORT datab (799:799:799) (766:766:766)) - (PORT datac (1149:1149:1149) (1124:1124:1124)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1298:1298:1298) (1298:1298:1298)) - (PORT datab (1920:1920:1920) (1910:1910:1910)) - (PORT datac (776:776:776) (769:769:769)) - (PORT datad (734:734:734) (710:710:710)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal48\~0) - (DELAY - (ABSOLUTE - (PORT dataa (803:803:803) (857:857:857)) - (PORT datab (1584:1584:1584) (1610:1610:1610)) - (PORT datac (1047:1047:1047) (1029:1029:1029)) - (PORT datad (606:606:606) (621:621:621)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) - (DELAY - (ABSOLUTE - (PORT dataa (857:857:857) (892:892:892)) - (PORT datab (833:833:833) (876:876:876)) - (PORT datac (874:874:874) (902:902:902)) - (PORT datad (1198:1198:1198) (1213:1213:1213)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (1149:1149:1149) (1212:1212:1212)) - (PORT datab (910:910:910) (938:938:938)) - (PORT datac (187:187:187) (223:223:223)) - (PORT datad (1100:1100:1100) (1133:1133:1133)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1710:1710:1710) (1758:1758:1758)) - (PORT datab (1197:1197:1197) (1242:1242:1242)) - (PORT datac (1863:1863:1863) (1898:1898:1898)) - (PORT datad (776:776:776) (751:751:751)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1130:1130:1130)) - (PORT datab (935:935:935) (959:959:959)) - (PORT datac (573:573:573) (592:592:592)) - (PORT datad (1081:1081:1081) (1058:1058:1058)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) - (DELAY - (ABSOLUTE - (PORT dataa (815:815:815) (829:829:829)) - (PORT datab (980:980:980) (1012:1012:1012)) - (PORT datac (534:534:534) (541:541:541)) - (PORT datad (1010:1010:1010) (990:990:990)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1486:1486:1486) (1597:1597:1597)) - (PORT datab (1406:1406:1406) (1486:1486:1486)) - (PORT datac (1570:1570:1570) (1623:1623:1623)) - (PORT datad (1338:1338:1338) (1358:1358:1358)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1559:1559:1559) (1557:1557:1557)) - (PORT datab (1417:1417:1417) (1466:1466:1466)) - (PORT datac (875:875:875) (902:902:902)) - (PORT datad (1069:1069:1069) (1109:1109:1109)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) - (DELAY - (ABSOLUTE - (PORT dataa (547:547:547) (564:564:564)) - (PORT datab (861:861:861) (862:862:862)) - (PORT datac (878:878:878) (906:906:906)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1509:1509:1509) (1553:1553:1553)) - (PORT datab (986:986:986) (1053:1053:1053)) - (PORT datac (1675:1675:1675) (1745:1745:1745)) - (PORT datad (871:871:871) (912:912:912)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1145:1145:1145) (1159:1159:1159)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (889:889:889) (916:916:916)) - (PORT datad (840:840:840) (871:871:871)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1245:1245:1245) (1268:1268:1268)) - (PORT datab (907:907:907) (938:938:938)) - (PORT datac (544:544:544) (545:545:545)) - (PORT datad (586:586:586) (604:604:604)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal20\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1846:1846:1846) (1909:1909:1909)) - (PORT datab (1409:1409:1409) (1459:1459:1459)) - (PORT datac (201:201:201) (245:245:245)) - (PORT datad (1019:1019:1019) (1030:1030:1030)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal68\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1485:1485:1485) (1596:1596:1596)) - (PORT datab (1407:1407:1407) (1486:1486:1486)) - (PORT datac (1569:1569:1569) (1622:1622:1622)) - (PORT datad (1338:1338:1338) (1358:1358:1358)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (890:890:890)) - (PORT datab (1324:1324:1324) (1342:1342:1342)) - (PORT datac (1230:1230:1230) (1288:1288:1288)) - (PORT datad (1439:1439:1439) (1489:1489:1489)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~13) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (643:643:643)) - (PORT datab (1512:1512:1512) (1464:1464:1464)) - (PORT datac (1211:1211:1211) (1179:1179:1179)) - (PORT datad (1329:1329:1329) (1380:1380:1380)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1465:1465:1465) (1527:1527:1527)) - (PORT datab (1258:1258:1258) (1314:1314:1314)) - (PORT datac (1072:1072:1072) (1074:1074:1074)) - (PORT datad (764:764:764) (745:745:745)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (652:652:652)) - (PORT datab (917:917:917) (953:953:953)) - (PORT datac (993:993:993) (1090:1090:1090)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~11) - (DELAY - (ABSOLUTE - (PORT dataa (2092:2092:2092) (2170:2170:2170)) - (PORT datab (780:780:780) (796:796:796)) - (PORT datac (1947:1947:1947) (1965:1965:1965)) - (PORT datad (609:609:609) (634:634:634)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (891:891:891)) - (PORT datab (910:910:910) (942:942:942)) - (PORT datac (1321:1321:1321) (1340:1340:1340)) - (PORT datad (1414:1414:1414) (1436:1436:1436)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (611:611:611)) - (PORT datab (412:412:412) (427:427:427)) - (PORT datac (181:181:181) (215:215:215)) - (PORT datad (1303:1303:1303) (1297:1297:1297)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (598:598:598) (580:580:580)) - (PORT datab (907:907:907) (935:935:935)) - (PORT datac (817:817:817) (816:816:816)) - (PORT datad (754:754:754) (757:757:757)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (352:352:352)) - (PORT datab (307:307:307) (325:325:325)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (240:240:240)) - (PORT datab (206:206:206) (245:245:245)) - (PORT datac (181:181:181) (216:216:216)) - (PORT datad (184:184:184) (209:209:209)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (584:584:584)) - (PORT datab (1311:1311:1311) (1349:1349:1349)) - (PORT datac (579:579:579) (584:584:584)) - (PORT datad (1507:1507:1507) (1522:1522:1522)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (631:631:631)) - (PORT datab (917:917:917) (951:951:951)) - (PORT datac (993:993:993) (1088:1088:1088)) - (PORT datad (2123:2123:2123) (2118:2118:2118)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (890:890:890)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (320:320:320) (331:331:331)) - (PORT datad (2124:2124:2124) (2121:2121:2121)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~4) - (DELAY - (ABSOLUTE - (PORT datab (976:976:976) (1054:1054:1054)) - (PORT datac (1345:1345:1345) (1372:1372:1372)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1290:1290:1290) (1309:1309:1309)) - (PORT datab (882:882:882) (907:907:907)) - (PORT datac (958:958:958) (1025:1025:1025)) - (PORT datad (1298:1298:1298) (1305:1305:1305)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (934:934:934)) - (PORT datab (1321:1321:1321) (1331:1331:1331)) - (PORT datac (889:889:889) (919:919:919)) - (PORT datad (178:178:178) (201:201:201)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1038:1038:1038) (1018:1018:1018)) - (PORT datab (1093:1093:1093) (1100:1100:1100)) - (PORT datac (609:609:609) (638:638:638)) - (PORT datad (810:810:810) (832:832:832)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) - (DELAY - (ABSOLUTE - (PORT dataa (554:554:554) (555:555:555)) - (PORT datac (539:539:539) (529:529:529)) - (PORT datad (491:491:491) (485:485:485)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (226:226:226) (275:275:275)) - (PORT datab (1147:1147:1147) (1139:1139:1139)) - (PORT datac (1072:1072:1072) (1085:1085:1085)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (816:816:816) (838:838:838)) - (PORT datab (791:791:791) (782:782:782)) - (PORT datac (320:320:320) (326:326:326)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1843:1843:1843) (1913:1913:1913)) - (PORT datab (830:830:830) (855:855:855)) - (PORT datac (198:198:198) (243:243:243)) - (PORT datad (1301:1301:1301) (1303:1303:1303)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) - (DELAY - (ABSOLUTE - (PORT dataa (1673:1673:1673) (1743:1743:1743)) - (PORT datab (1490:1490:1490) (1552:1552:1552)) - (PORT datad (1304:1304:1304) (1336:1336:1336)) - (IOPATH dataa combout (267:267:267) (273:273:273)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1897:1897:1897) (1897:1897:1897)) - (PORT datab (869:869:869) (915:915:915)) - (PORT datac (1005:1005:1005) (1022:1022:1022)) - (PORT datad (848:848:848) (890:890:890)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1248:1248:1248) (1215:1215:1215)) - (PORT datab (1074:1074:1074) (1125:1125:1125)) - (PORT datac (1366:1366:1366) (1365:1365:1365)) - (PORT datad (1353:1353:1353) (1375:1375:1375)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (1068:1068:1068) (1064:1064:1064)) - (PORT datab (202:202:202) (242:242:242)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (780:780:780) (768:768:768)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT datab (888:888:888) (913:913:913)) - (PORT datac (547:547:547) (540:540:540)) - (PORT datad (628:628:628) (648:648:648)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) - (DELAY - (ABSOLUTE - (PORT datac (858:858:858) (882:882:882)) - (PORT datad (633:633:633) (656:656:656)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) - (DELAY - (ABSOLUTE - (PORT dataa (927:927:927) (959:959:959)) - (PORT datab (655:655:655) (689:689:689)) - (PORT datac (837:837:837) (839:839:839)) - (PORT datad (1600:1600:1600) (1674:1674:1674)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1376:1376:1376) (1454:1454:1454)) - (PORT datab (1348:1348:1348) (1415:1415:1415)) - (PORT datac (1702:1702:1702) (1704:1704:1704)) - (PORT datad (376:376:376) (398:398:398)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1166:1166:1166)) - (PORT datac (873:873:873) (903:903:903)) - (PORT datad (1115:1115:1115) (1158:1158:1158)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1128:1128:1128) (1145:1145:1145)) - (PORT datab (1319:1319:1319) (1327:1327:1327)) - (PORT datac (1020:1020:1020) (994:994:994)) - (PORT datad (1237:1237:1237) (1210:1210:1210)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) - (DELAY - (ABSOLUTE - (PORT datab (864:864:864) (860:860:860)) - (PORT datac (496:496:496) (486:486:486)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (958:958:958)) - (PORT datab (655:655:655) (689:689:689)) - (PORT datac (835:835:835) (838:838:838)) - (PORT datad (1599:1599:1599) (1672:1672:1672)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1256:1256:1256) (1253:1253:1253)) - (PORT datab (843:843:843) (852:852:852)) - (PORT datad (569:569:569) (580:580:580)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (804:804:804) (816:816:816)) - (PORT datab (1350:1350:1350) (1391:1391:1391)) - (PORT datac (1212:1212:1212) (1289:1289:1289)) - (PORT datad (2057:2057:2057) (2079:2079:2079)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~36) - (DELAY - (ABSOLUTE - (PORT dataa (2171:2171:2171) (2222:2222:2222)) - (PORT datab (828:828:828) (853:853:853)) - (PORT datac (345:345:345) (360:360:360)) - (PORT datad (1356:1356:1356) (1393:1393:1393)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (234:234:234)) - (PORT datab (215:215:215) (256:256:256)) - (PORT datac (780:780:780) (771:771:771)) - (PORT datad (525:525:525) (507:507:507)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~5) - (DELAY - (ABSOLUTE - (PORT datac (2248:2248:2248) (2394:2394:2394)) - (PORT datad (1842:1842:1842) (1860:1860:1860)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1349:1349:1349) (1371:1371:1371)) - (PORT datab (775:775:775) (797:797:797)) - (PORT datac (849:849:849) (884:884:884)) - (PORT datad (606:606:606) (629:629:629)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1321:1321:1321) (1320:1320:1320)) - (PORT datab (1246:1246:1246) (1217:1217:1217)) - (PORT datac (792:792:792) (789:789:789)) - (PORT datad (754:754:754) (719:719:719)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1015:1015:1015) (999:999:999)) - (PORT datab (2388:2388:2388) (2382:2382:2382)) - (PORT datac (1421:1421:1421) (1511:1511:1511)) - (PORT datad (1582:1582:1582) (1635:1635:1635)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) - (DELAY - (ABSOLUTE - (PORT datac (187:187:187) (225:225:225)) - (PORT datad (190:190:190) (216:216:216)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1147:1147:1147)) - (PORT datab (1182:1182:1182) (1237:1237:1237)) - (PORT datac (1617:1617:1617) (1628:1628:1628)) - (PORT datad (783:783:783) (768:768:768)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (378:378:378)) - (PORT datab (376:376:376) (377:377:377)) - (PORT datac (346:346:346) (350:350:350)) - (PORT datad (183:183:183) (220:220:220)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1369:1369:1369) (1400:1400:1400)) - (PORT datab (1173:1173:1173) (1231:1231:1231)) - (PORT datac (824:824:824) (841:841:841)) - (PORT datad (1076:1076:1076) (1060:1060:1060)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (676:676:676)) - (PORT datab (2586:2586:2586) (2576:2576:2576)) - (PORT datac (1203:1203:1203) (1279:1279:1279)) - (PORT datad (528:528:528) (521:521:521)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low) - (DELAY - (ABSOLUTE - (PORT dataa (816:816:816) (813:813:813)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datac (175:175:175) (215:215:215)) - (PORT datad (167:167:167) (193:193:193)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (619:619:619)) - (PORT datab (199:199:199) (233:233:233)) - (PORT datac (539:539:539) (532:532:532)) - (PORT datad (1313:1313:1313) (1331:1331:1331)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1275:1275:1275) (1269:1269:1269)) - (PORT datab (1702:1702:1702) (1643:1643:1643)) - (PORT datac (1043:1043:1043) (1045:1045:1045)) - (PORT datad (1615:1615:1615) (1615:1615:1615)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1738:1738:1738) (1736:1736:1736)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (1052:1052:1052) (1081:1081:1081)) - (PORT datad (560:560:560) (567:567:567)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (586:586:586) (586:586:586)) - (PORT datab (958:958:958) (1002:1002:1002)) - (PORT datac (817:817:817) (816:816:816)) - (PORT datad (1479:1479:1479) (1546:1546:1546)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (336:336:336) (355:355:355)) - (PORT datac (155:155:155) (184:184:184)) - (PORT datad (966:966:966) (920:920:920)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1322:1322:1322) (1335:1335:1335)) - (PORT datab (1318:1318:1318) (1333:1333:1333)) - (PORT datac (568:568:568) (566:566:566)) - (PORT datad (838:838:838) (870:870:870)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1510:1510:1510) (1554:1554:1554)) - (PORT datab (182:182:182) (216:216:216)) - (PORT datac (1675:1675:1675) (1745:1745:1745)) - (PORT datad (845:845:845) (877:877:877)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1322:1322:1322) (1335:1335:1335)) - (PORT datab (1317:1317:1317) (1334:1334:1334)) - (PORT datac (961:961:961) (1026:1026:1026)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1666:1666:1666) (1679:1679:1679)) - (PORT datab (310:310:310) (325:325:325)) - (PORT datac (958:958:958) (1026:1026:1026)) - (PORT datad (1099:1099:1099) (1115:1115:1115)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1310:1310:1310) (1309:1309:1309)) - (PORT datab (1319:1319:1319) (1327:1327:1327)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (867:867:867) (906:906:906)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (908:908:908) (942:942:942)) - (PORT datac (997:997:997) (973:973:973)) - (PORT datad (1098:1098:1098) (1114:1114:1114)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (294:294:294)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1816:1816:1816) (1865:1865:1865)) - (PORT datab (1699:1699:1699) (1638:1638:1638)) - (PORT datac (1040:1040:1040) (1043:1043:1043)) - (PORT datad (1843:1843:1843) (1917:1917:1917)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (361:361:361)) - (PORT datab (1699:1699:1699) (1639:1639:1639)) - (PORT datac (1465:1465:1465) (1441:1441:1441)) - (PORT datad (169:169:169) (199:199:199)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (612:612:612)) - (PORT datab (919:919:919) (961:961:961)) - (PORT datac (1200:1200:1200) (1207:1207:1207)) - (PORT datad (743:743:743) (733:733:733)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (599:599:599)) - (PORT datac (980:980:980) (963:963:963)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (900:900:900) (934:934:934)) - (PORT datab (1320:1320:1320) (1328:1328:1328)) - (PORT datac (892:892:892) (915:915:915)) - (PORT datad (1102:1102:1102) (1119:1119:1119)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (366:366:366)) - (PORT datab (194:194:194) (232:232:232)) - (PORT datac (331:331:331) (342:342:342)) - (PORT datad (324:324:324) (326:326:326)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) - (DELAY - (ABSOLUTE - (PORT datab (598:598:598) (600:600:600)) - (PORT datac (802:802:802) (819:819:819)) - (PORT datad (166:166:166) (189:189:189)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (565:565:565) (547:547:547)) - (PORT datab (825:825:825) (812:812:812)) - (PORT datac (174:174:174) (206:206:206)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) - (DELAY - (ABSOLUTE - (PORT dataa (762:762:762) (760:760:760)) - (PORT datab (634:634:634) (663:663:663)) - (PORT datac (850:850:850) (886:886:886)) - (PORT datad (751:751:751) (757:757:757)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) - (DELAY - (ABSOLUTE - (PORT datab (805:805:805) (798:798:798)) - (PORT datad (757:757:757) (738:738:738)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) - (DELAY - (ABSOLUTE - (PORT datab (195:195:195) (234:234:234)) - (PORT datac (332:332:332) (342:342:342)) - (PORT datad (324:324:324) (326:326:326)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1509:1509:1509) (1555:1555:1555)) - (PORT datab (1686:1686:1686) (1724:1724:1724)) - (PORT datac (1674:1674:1674) (1748:1748:1748)) - (PORT datad (873:873:873) (896:896:896)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1322:1322:1322) (1336:1336:1336)) - (PORT datab (1319:1319:1319) (1328:1328:1328)) - (PORT datac (892:892:892) (920:920:920)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1667:1667:1667) (1681:1681:1681)) - (PORT datab (918:918:918) (948:948:948)) - (PORT datac (297:297:297) (304:304:304)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (616:616:616)) - (PORT datab (559:559:559) (561:561:561)) - (PORT datac (762:762:762) (744:744:744)) - (PORT datad (314:314:314) (313:313:313)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (218:218:218)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1188:1188:1188) (1198:1198:1198)) - (PORT datab (909:909:909) (990:990:990)) - (PORT datac (993:993:993) (1063:1063:1063)) - (PORT datad (891:891:891) (962:962:962)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1358:1358:1358) (1324:1324:1324)) - (PORT datab (1281:1281:1281) (1252:1252:1252)) - (PORT datac (1502:1502:1502) (1479:1479:1479)) - (PORT datad (1157:1157:1157) (1199:1199:1199)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1120:1120:1120) (1110:1110:1110)) - (PORT datab (966:966:966) (1033:1033:1033)) - (PORT datad (1249:1249:1249) (1347:1347:1347)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (656:656:656)) - (PORT datab (922:922:922) (918:918:918)) - (PORT datac (517:517:517) (502:502:502)) - (PORT datad (202:202:202) (225:225:225)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (715:715:715)) - (PORT datab (871:871:871) (917:917:917)) - (PORT datac (1005:1005:1005) (1023:1023:1023)) - (PORT datad (843:843:843) (885:885:885)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1132:1132:1132) (1172:1172:1172)) - (PORT datab (203:203:203) (245:245:245)) - (PORT datac (2166:2166:2166) (2200:2200:2200)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal8\~0) - (DELAY - (ABSOLUTE - (PORT datab (1924:1924:1924) (1977:1977:1977)) - (PORT datac (1577:1577:1577) (1617:1617:1617)) - (PORT datad (1064:1064:1064) (1115:1115:1115)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1336:1336:1336) (1342:1342:1342)) - (PORT datab (1328:1328:1328) (1302:1302:1302)) - (PORT datac (772:772:772) (771:771:771)) - (PORT datad (364:364:364) (378:378:378)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) - (DELAY - (ABSOLUTE - (PORT dataa (800:800:800) (804:804:804)) - (PORT datab (1094:1094:1094) (1088:1088:1088)) - (PORT datac (908:908:908) (931:931:931)) - (PORT datad (900:900:900) (934:934:934)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1847:1847:1847) (1918:1918:1918)) - (PORT datab (415:415:415) (432:432:432)) - (PORT datac (920:920:920) (954:954:954)) - (PORT datad (834:834:834) (846:846:846)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~1) - (DELAY - (ABSOLUTE - (PORT datac (1462:1462:1462) (1567:1567:1567)) - (PORT datad (1383:1383:1383) (1455:1455:1455)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) - (DELAY - (ABSOLUTE - (PORT dataa (882:882:882) (927:927:927)) - (PORT datab (1103:1103:1103) (1088:1088:1088)) - (PORT datac (1796:1796:1796) (1829:1829:1829)) - (PORT datad (596:596:596) (615:615:615)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (573:573:573) (590:590:590)) - (PORT datac (1558:1558:1558) (1610:1610:1610)) - (PORT datad (578:578:578) (592:592:592)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1386:1386:1386) (1425:1425:1425)) - (PORT datab (329:329:329) (353:353:353)) - (PORT datac (1936:1936:1936) (1950:1950:1950)) - (PORT datad (552:552:552) (533:533:533)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (715:715:715)) - (PORT datab (870:870:870) (912:912:912)) - (PORT datac (1004:1004:1004) (1021:1021:1021)) - (PORT datad (845:845:845) (889:889:889)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) - (DELAY - (ABSOLUTE - (PORT dataa (1359:1359:1359) (1390:1390:1390)) - (PORT datab (1129:1129:1129) (1189:1189:1189)) - (PORT datac (1349:1349:1349) (1357:1357:1357)) - (PORT datad (1052:1052:1052) (1047:1047:1047)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1699:1699:1699) (1727:1727:1727)) - (PORT datab (1918:1918:1918) (1966:1966:1966)) - (PORT datac (1236:1236:1236) (1200:1200:1200)) - (PORT datad (1859:1859:1859) (1904:1904:1904)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1032:1032:1032) (1089:1089:1089)) - (PORT datab (602:602:602) (604:604:604)) - (PORT datac (1124:1124:1124) (1159:1159:1159)) - (PORT datad (553:553:553) (559:559:559)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1048:1048:1048) (1038:1038:1038)) - (PORT datab (786:786:786) (772:772:772)) - (PORT datad (534:534:534) (525:525:525)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) - (DELAY - (ABSOLUTE - (PORT datac (1624:1624:1624) (1672:1672:1672)) - (PORT datad (1455:1455:1455) (1524:1524:1524)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~25) - (DELAY - (ABSOLUTE - (PORT dataa (940:940:940) (967:967:967)) - (PORT datab (959:959:959) (994:994:994)) - (PORT datac (978:978:978) (1009:1009:1009)) - (PORT datad (585:585:585) (593:593:593)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1467:1467:1467) (1544:1544:1544)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datac (978:978:978) (1009:1009:1009)) - (PORT datad (1658:1658:1658) (1738:1738:1738)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1132:1132:1132)) - (PORT datab (639:639:639) (634:634:634)) - (PORT datac (1175:1175:1175) (1251:1251:1251)) - (PORT datad (1462:1462:1462) (1539:1539:1539)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datab (194:194:194) (234:234:234)) - (PORT datac (1174:1174:1174) (1251:1251:1251)) - (PORT datad (1465:1465:1465) (1543:1543:1543)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1133:1133:1133) (1133:1133:1133)) - (PORT datab (1529:1529:1529) (1476:1476:1476)) - (PORT datac (729:729:729) (713:713:713)) - (PORT datad (541:541:541) (543:543:543)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (597:597:597)) - (PORT datab (610:610:610) (626:626:626)) - (PORT datac (627:627:627) (658:658:658)) - (PORT datad (740:740:740) (792:792:792)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) - (DELAY - (ABSOLUTE - (PORT dataa (917:917:917) (963:963:963)) - (PORT datab (1558:1558:1558) (1560:1560:1560)) - (PORT datac (1455:1455:1455) (1513:1513:1513)) - (PORT datad (889:889:889) (912:912:912)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1194:1194:1194) (1204:1204:1204)) - (PORT datab (854:854:854) (864:864:864)) - (PORT datac (905:905:905) (931:931:931)) - (PORT datad (1082:1082:1082) (1058:1058:1058)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (351:351:351)) - (PORT datab (1367:1367:1367) (1350:1350:1350)) - (PORT datac (995:995:995) (995:995:995)) - (PORT datad (1254:1254:1254) (1233:1233:1233)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (353:353:353)) - (PORT datab (216:216:216) (250:250:250)) - (PORT datac (969:969:969) (989:989:989)) - (PORT datad (1280:1280:1280) (1284:1284:1284)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (803:803:803) (806:806:806)) - (PORT datab (342:342:342) (353:353:353)) - (PORT datac (605:605:605) (626:626:626)) - (PORT datad (771:771:771) (793:793:793)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (727:727:727)) - (PORT datab (863:863:863) (905:905:905)) - (PORT datac (889:889:889) (926:926:926)) - (PORT datad (176:176:176) (197:197:197)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1343:1343:1343) (1389:1389:1389)) - (PORT datab (571:571:571) (573:573:573)) - (PORT datac (1107:1107:1107) (1146:1146:1146)) - (PORT datad (778:778:778) (761:761:761)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (249:249:249)) - (PORT datab (190:190:190) (226:226:226)) - (PORT datac (548:548:548) (534:534:534)) - (PORT datad (797:797:797) (784:784:784)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1118:1118:1118)) - (PORT datab (888:888:888) (925:925:925)) - (PORT datac (963:963:963) (1020:1020:1020)) - (PORT datad (1328:1328:1328) (1332:1332:1332)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) - (DELAY - (ABSOLUTE - (PORT dataa (993:993:993) (1052:1052:1052)) - (PORT datab (893:893:893) (931:931:931)) - (PORT datac (292:292:292) (301:301:301)) - (PORT datad (588:588:588) (597:597:597)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) - (DELAY - (ABSOLUTE - (PORT dataa (933:933:933) (981:981:981)) - (PORT datab (1278:1278:1278) (1267:1267:1267)) - (PORT datac (1084:1084:1084) (1086:1086:1086)) - (PORT datad (1118:1118:1118) (1133:1133:1133)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (229:229:229)) - (PORT datab (1155:1155:1155) (1173:1173:1173)) - (PORT datac (894:894:894) (943:943:943)) - (PORT datad (585:585:585) (594:594:594)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) - (DELAY - (ABSOLUTE - (PORT dataa (805:805:805) (809:809:809)) - (PORT datab (1331:1331:1331) (1306:1306:1306)) - (PORT datac (1553:1553:1553) (1554:1554:1554)) - (PORT datad (1898:1898:1898) (1969:1969:1969)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (572:572:572) (574:574:574)) - (PORT datab (189:189:189) (226:226:226)) - (PORT datac (1291:1291:1291) (1332:1332:1332)) - (PORT datad (1314:1314:1314) (1311:1311:1311)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1677:1677:1677) (1730:1730:1730)) - (PORT datab (780:780:780) (772:772:772)) - (PORT datac (774:774:774) (776:776:776)) - (PORT datad (1897:1897:1897) (1970:1970:1970)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (775:775:775) (754:754:754)) - (PORT datab (731:731:731) (724:724:724)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (326:326:326) (339:339:339)) - (PORT datab (200:200:200) (233:233:233)) - (PORT datac (175:175:175) (207:207:207)) - (PORT datad (506:506:506) (496:496:496)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (880:880:880) (899:899:899)) - (PORT datab (807:807:807) (798:798:798)) - (PORT datac (1556:1556:1556) (1622:1622:1622)) - (PORT datad (1087:1087:1087) (1096:1096:1096)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1253:1253:1253) (1205:1205:1205)) - (PORT datab (1072:1072:1072) (1087:1087:1087)) - (PORT datac (1037:1037:1037) (1010:1010:1010)) - (PORT datad (620:620:620) (635:635:635)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1101:1101:1101) (1124:1124:1124)) - (PORT datac (549:549:549) (548:548:548)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1096:1096:1096) (1119:1119:1119)) - (PORT datab (603:603:603) (603:603:603)) - (PORT datac (174:174:174) (223:223:223)) - (PORT datad (571:571:571) (570:570:570)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (248:248:248)) - (PORT datac (1939:1939:1939) (1948:1948:1948)) - (PORT datad (1345:1345:1345) (1382:1382:1382)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (411:411:411)) - (PORT datab (1066:1066:1066) (1075:1075:1075)) - (PORT datac (1350:1350:1350) (1358:1358:1358)) - (PORT datad (1016:1016:1016) (1032:1032:1032)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (991:991:991) (1047:1047:1047)) - (PORT datab (960:960:960) (1002:1002:1002)) - (PORT datac (1084:1084:1084) (1085:1085:1085)) - (PORT datad (1118:1118:1118) (1133:1133:1133)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (828:828:828) (817:817:817)) - (PORT datab (606:606:606) (624:624:624)) - (PORT datac (1030:1030:1030) (994:994:994)) - (PORT datad (723:723:723) (705:705:705)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1040:1040:1040) (1029:1029:1029)) - (PORT datab (1420:1420:1420) (1483:1483:1483)) - (PORT datac (568:568:568) (595:595:595)) - (PORT datad (165:165:165) (190:190:190)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (703:703:703)) - (PORT datab (781:781:781) (795:795:795)) - (PORT datac (733:733:733) (731:731:731)) - (PORT datad (610:610:610) (634:634:634)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~9) - (DELAY - (ABSOLUTE - (PORT dataa (933:933:933) (981:981:981)) - (PORT datab (892:892:892) (930:930:930)) - (PORT datac (173:173:173) (203:203:203)) - (PORT datad (1328:1328:1328) (1329:1329:1329)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1192:1192:1192) (1254:1254:1254)) - (PORT datab (891:891:891) (929:929:929)) - (PORT datac (965:965:965) (1018:1018:1018)) - (PORT datad (1442:1442:1442) (1506:1506:1506)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1191:1191:1191) (1254:1254:1254)) - (PORT datab (1156:1156:1156) (1167:1167:1167)) - (PORT datac (894:894:894) (945:945:945)) - (PORT datad (1443:1443:1443) (1507:1507:1507)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datac (161:161:161) (196:196:196)) - (PORT datad (165:165:165) (191:191:191)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (530:530:530) (517:517:517)) - (PORT datab (217:217:217) (259:259:259)) - (PORT datac (503:503:503) (491:491:491)) - (PORT datad (1341:1341:1341) (1348:1348:1348)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (1285:1285:1285) (1264:1264:1264)) - (PORT datac (533:533:533) (527:527:527)) - (PORT datad (559:559:559) (564:564:564)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (656:656:656)) - (PORT datab (1042:1042:1042) (1050:1050:1050)) - (PORT datac (894:894:894) (891:891:891)) - (PORT datad (1079:1079:1079) (1090:1090:1090)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (853:853:853) (896:896:896)) - (PORT datab (883:883:883) (906:906:906)) - (PORT datac (1114:1114:1114) (1159:1159:1159)) - (PORT datad (355:355:355) (359:359:359)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1638:1638:1638) (1596:1596:1596)) - (PORT datab (1504:1504:1504) (1511:1511:1511)) - (PORT datac (1208:1208:1208) (1288:1288:1288)) - (PORT datad (1428:1428:1428) (1521:1521:1521)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1032:1032:1032) (1036:1036:1036)) - (PORT datab (970:970:970) (989:989:989)) - (PORT datac (876:876:876) (885:885:885)) - (PORT datad (764:764:764) (753:753:753)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (902:902:902) (917:917:917)) - (PORT datab (644:644:644) (656:656:656)) - (PORT datac (191:191:191) (236:236:236)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (791:791:791) (790:790:790)) - (PORT datab (602:602:602) (612:612:612)) - (PORT datac (814:814:814) (813:813:813)) - (PORT datad (759:759:759) (751:751:751)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (329:329:329) (355:355:355)) - (PORT datac (899:899:899) (931:931:931)) - (PORT datad (552:552:552) (532:532:532)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datac (1584:1584:1584) (1557:1557:1557)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (268:268:268)) - (PORT datab (1098:1098:1098) (1106:1106:1106)) - (PORT datac (1117:1117:1117) (1107:1107:1107)) - (PORT datad (521:521:521) (507:507:507)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1031:1031:1031) (1039:1039:1039)) - (PORT datab (220:220:220) (265:265:265)) - (PORT datac (835:835:835) (838:838:838)) - (PORT datad (1812:1812:1812) (1811:1811:1811)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (768:768:768) (752:752:752)) - (PORT datab (804:804:804) (790:790:790)) - (PORT datac (554:554:554) (548:548:548)) - (PORT datad (758:758:758) (736:736:736)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1996:1996:1996) (2051:2051:2051)) - (PORT datab (1617:1617:1617) (1676:1676:1676)) - (PORT datac (813:813:813) (805:805:805)) - (PORT datad (2159:2159:2159) (2213:2213:2213)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (894:894:894) (933:933:933)) - (PORT datab (1942:1942:1942) (1959:1959:1959)) - (PORT datac (513:513:513) (510:510:510)) - (PORT datad (1825:1825:1825) (1841:1841:1841)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~54) - (DELAY - (ABSOLUTE - (PORT dataa (1648:1648:1648) (1706:1706:1706)) - (PORT datab (988:988:988) (1054:1054:1054)) - (PORT datac (889:889:889) (915:915:915)) - (PORT datad (1891:1891:1891) (1927:1927:1927)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1041:1041:1041) (1131:1131:1131)) - (PORT datab (1090:1090:1090) (1095:1095:1095)) - (PORT datac (564:564:564) (560:560:560)) - (PORT datad (2123:2123:2123) (2121:2121:2121)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (928:928:928)) - (PORT datab (1059:1059:1059) (1039:1039:1039)) - (PORT datac (321:321:321) (343:343:343)) - (PORT datad (576:576:576) (601:601:601)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (806:806:806) (815:815:815)) - (PORT datac (775:775:775) (771:771:771)) - (PORT datad (485:485:485) (478:478:478)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (260:260:260)) - (PORT datab (223:223:223) (267:267:267)) - (PORT datac (1819:1819:1819) (1877:1877:1877)) - (PORT datad (184:184:184) (214:214:214)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1253:1253:1253) (1338:1338:1338)) - (PORT datab (1252:1252:1252) (1227:1227:1227)) - (PORT datac (806:806:806) (800:800:800)) - (PORT datad (1348:1348:1348) (1350:1350:1350)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1021:1021:1021) (1092:1092:1092)) - (PORT datab (627:627:627) (671:671:671)) - (PORT datac (883:883:883) (964:964:964)) - (PORT datad (568:568:568) (558:558:558)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (578:578:578) (597:597:597)) - (PORT datab (890:890:890) (953:953:953)) - (PORT datac (1596:1596:1596) (1638:1638:1638)) - (PORT datad (1056:1056:1056) (1043:1043:1043)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1834:1834:1834) (1832:1832:1832)) - (PORT datab (811:811:811) (805:805:805)) - (PORT datac (1249:1249:1249) (1292:1292:1292)) - (PORT datad (1251:1251:1251) (1268:1268:1268)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (569:569:569) (584:584:584)) - (PORT datab (977:977:977) (1008:1008:1008)) - (PORT datac (186:186:186) (223:223:223)) - (PORT datad (810:810:810) (824:824:824)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) - (DELAY - (ABSOLUTE - (PORT dataa (572:572:572) (571:571:571)) - (PORT datab (184:184:184) (221:221:221)) - (PORT datac (804:804:804) (814:814:814)) - (PORT datad (797:797:797) (788:788:788)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1600:1600:1600) (1606:1606:1606)) - (PORT datab (979:979:979) (1057:1057:1057)) - (PORT datac (1109:1109:1109) (1153:1153:1153)) - (PORT datad (803:803:803) (799:799:799)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (657:657:657)) - (PORT datab (1074:1074:1074) (1122:1122:1122)) - (PORT datac (1365:1365:1365) (1362:1362:1362)) - (PORT datad (1355:1355:1355) (1371:1371:1371)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (797:797:797) (797:797:797)) - (PORT datab (1287:1287:1287) (1268:1268:1268)) - (PORT datac (730:730:730) (706:706:706)) - (PORT datad (1594:1594:1594) (1604:1604:1604)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel3) - (DELAY - (ABSOLUTE - (PORT dataa (1293:1293:1293) (1323:1323:1323)) - (PORT datab (2166:2166:2166) (2220:2220:2220)) - (PORT datac (1040:1040:1040) (1047:1047:1047)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (886:886:886) (905:905:905)) - (PORT datab (946:946:946) (963:963:963)) - (PORT datac (163:163:163) (199:199:199)) - (PORT datad (592:592:592) (606:606:606)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (550:550:550) (567:567:567)) - (PORT datab (622:622:622) (640:640:640)) - (PORT datac (474:474:474) (464:464:464)) - (PORT datad (780:780:780) (784:784:784)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (231:231:231)) - (PORT datab (820:820:820) (834:834:834)) - (PORT datac (817:817:817) (831:831:831)) - (PORT datad (165:165:165) (189:189:189)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel0) - (DELAY - (ABSOLUTE - (PORT dataa (2000:2000:2000) (2094:2094:2094)) - (PORT datac (1337:1337:1337) (1366:1366:1366)) - (PORT datad (2090:2090:2090) (2151:2151:2151)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) - (DELAY - (ABSOLUTE - (PORT datab (855:855:855) (898:898:898)) - (PORT datac (1428:1428:1428) (1488:1488:1488)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (663:663:663)) - (PORT datab (804:804:804) (798:798:798)) - (PORT datac (1185:1185:1185) (1244:1244:1244)) - (PORT datad (830:830:830) (837:837:837)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1371:1371:1371) (1382:1382:1382)) - (PORT datab (186:186:186) (221:221:221)) - (PORT datac (915:915:915) (939:939:939)) - (PORT datad (943:943:943) (974:974:974)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (213:213:213) (257:257:257)) - (PORT datab (348:348:348) (358:358:358)) - (PORT datac (557:557:557) (574:574:574)) - (PORT datad (182:182:182) (214:214:214)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1490:1490:1490) (1599:1599:1599)) - (PORT datab (1414:1414:1414) (1492:1492:1492)) - (PORT datac (1571:1571:1571) (1623:1623:1623)) - (PORT datad (1336:1336:1336) (1357:1357:1357)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1639:1639:1639) (1647:1647:1647)) - (PORT datab (618:618:618) (642:642:642)) - (PORT datac (515:515:515) (508:508:508)) - (PORT datad (1048:1048:1048) (1051:1051:1051)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (671:671:671)) - (PORT datab (921:921:921) (982:982:982)) - (PORT datac (174:174:174) (205:205:205)) - (PORT datad (1151:1151:1151) (1208:1208:1208)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (568:568:568) (562:562:562)) - (PORT datab (813:813:813) (811:811:811)) - (PORT datac (314:314:314) (324:324:324)) - (PORT datad (635:635:635) (668:668:668)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (630:630:630)) - (PORT datab (875:875:875) (898:898:898)) - (PORT datac (542:542:542) (538:538:538)) - (PORT datad (593:593:593) (607:607:607)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1065:1065:1065) (1038:1038:1038)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (537:537:537) (532:532:532)) - (PORT datad (165:165:165) (187:187:187)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (453:453:453)) - (PORT datab (1209:1209:1209) (1252:1252:1252)) - (PORT datac (633:633:633) (694:694:694)) - (PORT datad (1201:1201:1201) (1265:1265:1265)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1460:1460:1460) (1479:1479:1479)) - (PORT datab (843:843:843) (847:847:847)) - (PORT datac (1162:1162:1162) (1169:1169:1169)) - (PORT datad (1542:1542:1542) (1536:1536:1536)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (355:355:355)) - (PORT datab (201:201:201) (236:236:236)) - (PORT datac (595:595:595) (637:637:637)) - (PORT datad (1543:1543:1543) (1538:1538:1538)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1202:1202:1202) (1240:1240:1240)) - (PORT datab (1096:1096:1096) (1120:1120:1120)) - (PORT datac (1060:1060:1060) (1088:1088:1088)) - (PORT datad (1228:1228:1228) (1299:1299:1299)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (838:838:838)) - (PORT datab (357:357:357) (362:362:362)) - (PORT datac (595:595:595) (625:625:625)) - (PORT datad (1112:1112:1112) (1131:1131:1131)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) - (DELAY - (ABSOLUTE - (PORT dataa (1036:1036:1036) (1010:1010:1010)) - (PORT datab (840:840:840) (845:845:845)) - (PORT datac (938:938:938) (942:942:942)) - (PORT datad (844:844:844) (850:850:850)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (226:226:226)) - (PORT datab (882:882:882) (943:943:943)) - (PORT datac (788:788:788) (775:775:775)) - (PORT datad (845:845:845) (863:863:863)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (960:960:960)) - (PORT datab (1111:1111:1111) (1133:1133:1133)) - (PORT datac (1453:1453:1453) (1510:1510:1510)) - (PORT datad (1061:1061:1061) (1067:1067:1067)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (568:568:568) (599:599:599)) - (PORT datab (1910:1910:1910) (2031:2031:2031)) - (PORT datac (794:794:794) (793:793:793)) - (PORT datad (1137:1137:1137) (1187:1187:1187)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) - (DELAY - (ABSOLUTE - (PORT dataa (830:830:830) (853:853:853)) - (PORT datab (838:838:838) (837:837:837)) - (PORT datac (1039:1039:1039) (1029:1029:1029)) - (PORT datad (845:845:845) (851:851:851)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~92) - (DELAY - (ABSOLUTE - (PORT dataa (946:946:946) (1006:1006:1006)) - (PORT datab (1459:1459:1459) (1555:1555:1555)) - (PORT datac (578:578:578) (579:579:579)) - (PORT datad (1554:1554:1554) (1605:1605:1605)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2170:2170:2170) (2236:2236:2236)) - (PORT datab (1515:1515:1515) (1602:1602:1602)) - (PORT datac (833:833:833) (863:863:863)) - (PORT datad (622:622:622) (647:647:647)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (994:994:994)) - (PORT datad (1419:1419:1419) (1497:1497:1497)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1204:1204:1204) (1241:1241:1241)) - (PORT datab (604:604:604) (626:626:626)) - (PORT datac (1256:1256:1256) (1261:1261:1261)) - (PORT datad (824:824:824) (814:814:814)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~93) - (DELAY - (ABSOLUTE - (PORT dataa (1046:1046:1046) (1058:1058:1058)) - (PORT datab (1581:1581:1581) (1635:1635:1635)) - (PORT datac (1431:1431:1431) (1520:1520:1520)) - (PORT datad (922:922:922) (971:971:971)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1258:1258:1258) (1338:1338:1338)) - (PORT datab (769:769:769) (764:764:764)) - (PORT datac (1036:1036:1036) (1044:1044:1044)) - (PORT datad (587:587:587) (616:616:616)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~24) - (DELAY - (ABSOLUTE - (PORT datab (1090:1090:1090) (1101:1101:1101)) - (PORT datac (175:175:175) (207:207:207)) - (PORT datad (166:166:166) (192:192:192)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (240:240:240)) - (PORT datab (792:792:792) (802:802:802)) - (PORT datac (176:176:176) (220:220:220)) - (PORT datad (620:620:620) (653:653:653)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (937:937:937)) - (PORT datab (857:857:857) (883:883:883)) - (PORT datac (1297:1297:1297) (1301:1301:1301)) - (PORT datad (505:505:505) (493:493:493)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (553:553:553) (573:573:573)) - (PORT datab (813:813:813) (797:797:797)) - (PORT datac (1265:1265:1265) (1299:1299:1299)) - (PORT datad (1371:1371:1371) (1415:1415:1415)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (902:902:902)) - (PORT datab (838:838:838) (839:839:839)) - (PORT datac (844:844:844) (867:867:867)) - (PORT datad (1421:1421:1421) (1476:1476:1476)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1087:1087:1087) (1086:1086:1086)) - (PORT datab (598:598:598) (626:626:626)) - (PORT datac (842:842:842) (851:851:851)) - (PORT datad (313:313:313) (321:321:321)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) - (DELAY - (ABSOLUTE - (PORT datab (1398:1398:1398) (1449:1449:1449)) - (PORT datac (1595:1595:1595) (1640:1640:1640)) - (PORT datad (992:992:992) (983:983:983)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (651:651:651)) - (PORT datab (1077:1077:1077) (1092:1092:1092)) - (PORT datac (791:791:791) (802:802:802)) - (PORT datad (1085:1085:1085) (1121:1121:1121)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (893:893:893)) - (PORT datab (871:871:871) (898:898:898)) - (PORT datac (588:588:588) (608:608:608)) - (PORT datad (1068:1068:1068) (1085:1085:1085)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) - (DELAY - (ABSOLUTE - (PORT datab (795:795:795) (812:812:812)) - (PORT datac (162:162:162) (193:193:193)) - (PORT datad (785:785:785) (796:796:796)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (982:982:982) (955:955:955)) - (PORT datab (1347:1347:1347) (1362:1362:1362)) - (PORT datac (1202:1202:1202) (1202:1202:1202)) - (PORT datad (796:796:796) (783:783:783)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1554:1554:1554) (1584:1584:1584)) - (PORT datab (1555:1555:1555) (1584:1584:1584)) - (PORT datac (1364:1364:1364) (1421:1421:1421)) - (PORT datad (800:800:800) (784:784:784)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (1339:1339:1339) (1364:1364:1364)) - (PORT datab (1555:1555:1555) (1579:1579:1579)) - (PORT datac (1526:1526:1526) (1546:1546:1546)) - (PORT datad (1081:1081:1081) (1109:1109:1109)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) - (DELAY - (ABSOLUTE - (PORT dataa (766:766:766) (823:823:823)) - (PORT datab (566:566:566) (558:558:558)) - (PORT datac (1372:1372:1372) (1392:1392:1392)) - (PORT datad (529:529:529) (531:531:531)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (889:889:889)) - (PORT datab (852:852:852) (861:861:861)) - (PORT datac (819:819:819) (835:835:835)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~94) - (DELAY - (ABSOLUTE - (PORT dataa (1666:1666:1666) (1693:1693:1693)) - (PORT datab (1579:1579:1579) (1635:1635:1635)) - (PORT datac (1433:1433:1433) (1520:1520:1520)) - (PORT datad (924:924:924) (971:971:971)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) - (DELAY - (ABSOLUTE - (PORT dataa (1490:1490:1490) (1562:1562:1562)) - (PORT datac (2316:2316:2316) (2354:2354:2354)) - (PORT datad (1370:1370:1370) (1419:1419:1419)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1093:1093:1093) (1079:1079:1079)) - (PORT datab (1076:1076:1076) (1084:1084:1084)) - (PORT datac (175:175:175) (206:206:206)) - (PORT datad (801:801:801) (790:790:790)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT datab (633:633:633) (649:649:649)) - (PORT datac (350:350:350) (372:372:372)) - (PORT datad (185:185:185) (210:210:210)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (441:441:441)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (755:755:755) (733:733:733)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (366:366:366)) - (PORT datab (840:840:840) (809:809:809)) - (PORT datac (583:583:583) (587:587:587)) - (PORT datad (1100:1100:1100) (1110:1110:1110)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1160:1160:1160) (1201:1201:1201)) - (PORT datab (1520:1520:1520) (1606:1606:1606)) - (PORT datac (837:837:837) (864:864:864)) - (PORT datad (875:875:875) (891:891:891)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1344:1344:1344) (1403:1403:1403)) - (PORT datab (1544:1544:1544) (1566:1566:1566)) - (PORT datac (780:780:780) (766:766:766)) - (PORT datad (599:599:599) (622:622:622)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_exx\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1303:1303:1303) (1397:1397:1397)) - (PORT datab (841:841:841) (835:835:835)) - (PORT datad (2159:2159:2159) (2215:2215:2215)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_exx) - (DELAY - (ABSOLUTE - (PORT clk (1340:1340:1340) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1394:1394:1394) (1365:1365:1365)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1082:1082:1082) (1075:1075:1075)) - (PORT datab (1111:1111:1111) (1127:1127:1127)) - (PORT datad (1118:1118:1118) (1164:1164:1164)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de1) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1414:1414:1414) (1380:1380:1380)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (855:855:855) (872:872:872)) - (PORT datab (1882:1882:1882) (1862:1862:1862)) - (PORT datac (749:749:749) (731:731:731)) - (PORT datad (308:308:308) (321:321:321)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (889:889:889)) - (PORT datab (1596:1596:1596) (1576:1576:1576)) - (PORT datac (1137:1137:1137) (1193:1193:1193)) - (PORT datad (1069:1069:1069) (1084:1084:1084)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (721:721:721) (704:704:704)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1138:1138:1138) (1195:1195:1195)) - (PORT datad (1423:1423:1423) (1478:1478:1478)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1167:1167:1167)) - (PORT datab (1180:1180:1180) (1243:1243:1243)) - (PORT datac (1064:1064:1064) (1081:1081:1081)) - (PORT datad (653:653:653) (698:698:698)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (572:572:572) (587:587:587)) - (PORT datab (558:558:558) (547:547:547)) - (PORT datac (842:842:842) (851:851:851)) - (PORT datad (1614:1614:1614) (1636:1636:1636)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (882:882:882)) - (PORT datab (334:334:334) (351:351:351)) - (PORT datac (1095:1095:1095) (1094:1094:1094)) - (PORT datad (1866:1866:1866) (1908:1908:1908)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (321:321:321) (333:333:333)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (814:814:814) (838:838:838)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (890:890:890) (966:966:966)) - (PORT datab (841:841:841) (903:903:903)) - (PORT datac (994:994:994) (962:962:962)) - (PORT datad (981:981:981) (973:973:973)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1243:1243:1243) (1274:1274:1274)) - (PORT datab (836:836:836) (860:860:860)) - (PORT datac (614:614:614) (619:619:619)) - (PORT datad (1077:1077:1077) (1096:1096:1096)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1883:1883:1883) (1905:1905:1905)) - (PORT datac (1526:1526:1526) (1519:1519:1519)) - (PORT datad (1594:1594:1594) (1640:1640:1640)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~2) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (952:952:952)) - (PORT datab (1230:1230:1230) (1233:1233:1233)) - (PORT datac (1216:1216:1216) (1250:1250:1250)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~19) - (DELAY - (ABSOLUTE - (PORT datab (614:614:614) (609:609:609)) - (PORT datac (605:605:605) (605:605:605)) - (PORT datad (830:830:830) (864:864:864)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (614:614:614)) - (PORT datab (656:656:656) (655:655:655)) - (PORT datac (625:625:625) (659:659:659)) - (PORT datad (773:773:773) (751:751:751)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (788:788:788)) - (PORT datac (1768:1768:1768) (1803:1803:1803)) - (PORT datad (182:182:182) (216:216:216)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (568:568:568) (599:599:599)) - (PORT datab (802:802:802) (832:832:832)) - (PORT datac (1015:1015:1015) (1007:1007:1007)) - (PORT datad (767:767:767) (769:769:769)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (985:985:985) (1061:1061:1061)) - (PORT datab (925:925:925) (982:982:982)) - (PORT datac (1298:1298:1298) (1315:1315:1315)) - (PORT datad (185:185:185) (216:216:216)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (988:988:988) (1063:1063:1063)) - (PORT datab (1826:1826:1826) (1865:1865:1865)) - (PORT datac (1066:1066:1066) (1087:1087:1087)) - (PORT datad (862:862:862) (902:902:902)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (2410:2410:2410) (2500:2500:2500)) - (PORT datad (176:176:176) (198:198:198)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (922:922:922)) - (PORT datac (1027:1027:1027) (1063:1063:1063)) - (PORT datad (1062:1062:1062) (1079:1079:1079)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (923:923:923)) - (PORT datab (784:784:784) (755:755:755)) - (PORT datac (1854:1854:1854) (1845:1845:1845)) - (PORT datad (1290:1290:1290) (1271:1271:1271)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1463:1463:1463) (1537:1537:1537)) - (PORT datab (846:846:846) (865:865:865)) - (PORT datac (857:857:857) (889:889:889)) - (PORT datad (1410:1410:1410) (1477:1477:1477)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (602:602:602)) - (PORT datab (806:806:806) (796:796:796)) - (PORT datac (556:556:556) (588:588:588)) - (PORT datad (756:756:756) (737:737:737)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1028:1028:1028) (1120:1120:1120)) - (PORT datac (1287:1287:1287) (1310:1310:1310)) - (PORT datad (1946:1946:1946) (2000:2000:2000)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (838:838:838) (866:866:866)) - (PORT datab (1437:1437:1437) (1489:1489:1489)) - (PORT datac (189:189:189) (227:227:227)) - (PORT datad (571:571:571) (571:571:571)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1273:1273:1273) (1297:1297:1297)) - (PORT datab (570:570:570) (567:567:567)) - (PORT datac (730:730:730) (709:709:709)) - (PORT datad (553:553:553) (545:545:545)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1541:1541:1541) (1540:1540:1540)) - (PORT datab (1032:1032:1032) (1027:1027:1027)) - (PORT datac (973:973:973) (1020:1020:1020)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1222:1222:1222) (1283:1283:1283)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datac (553:553:553) (560:560:560)) - (PORT datad (1361:1361:1361) (1405:1405:1405)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (542:542:542) (529:529:529)) - (PORT datab (572:572:572) (598:598:598)) - (PORT datac (568:568:568) (565:565:565)) - (PORT datad (543:543:543) (521:521:521)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (2077:2077:2077) (2125:2125:2125)) - (PORT datab (237:237:237) (304:304:304)) - (PORT datac (1069:1069:1069) (1106:1106:1106)) - (PORT datad (214:214:214) (271:271:271)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (161:161:161) (196:196:196)) - (PORT datad (809:809:809) (823:823:823)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT datab (189:189:189) (226:226:226)) - (PORT datad (614:614:614) (630:630:630)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (195:195:195) (239:239:239)) - (PORT datab (959:959:959) (957:957:957)) - (PORT datac (310:310:310) (319:319:319)) - (PORT datad (637:637:637) (668:668:668)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1041:1041:1041) (1135:1135:1135)) - (PORT datac (825:825:825) (856:856:856)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~14) - (DELAY - (ABSOLUTE - (PORT datac (611:611:611) (666:666:666)) - (PORT datad (830:830:830) (826:826:826)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1328:1328:1328) (1337:1337:1337)) - (PORT datab (575:575:575) (576:576:576)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (1052:1052:1052) (1050:1050:1050)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~47) - (DELAY - (ABSOLUTE - (PORT dataa (572:572:572) (570:570:570)) - (PORT datab (602:602:602) (594:594:594)) - (PORT datac (827:827:827) (826:826:826)) - (PORT datad (819:819:819) (832:832:832)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~48) - (DELAY - (ABSOLUTE - (PORT dataa (324:324:324) (341:341:341)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (566:566:566) (585:585:585)) - (PORT datad (985:985:985) (968:968:968)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1884:1884:1884) (1906:1906:1906)) - (PORT datac (1526:1526:1526) (1518:1518:1518)) - (PORT datad (1595:1595:1595) (1640:1640:1640)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1225:1225:1225) (1290:1290:1290)) - (PORT datab (1026:1026:1026) (1009:1009:1009)) - (PORT datac (849:849:849) (867:867:867)) - (PORT datad (521:521:521) (513:513:513)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (250:250:250)) - (PORT datab (207:207:207) (246:246:246)) - (PORT datac (1092:1092:1092) (1118:1118:1118)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) - (DELAY - (ABSOLUTE - (PORT dataa (757:757:757) (754:754:754)) - (PORT datab (1168:1168:1168) (1189:1189:1189)) - (PORT datac (1657:1657:1657) (1708:1708:1708)) - (PORT datad (1950:1950:1950) (2008:2008:2008)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (585:585:585) (583:583:583)) - (PORT datac (554:554:554) (549:549:549)) - (PORT datad (782:782:782) (777:777:777)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1258:1258:1258) (1344:1344:1344)) - (PORT datab (688:688:688) (729:729:729)) - (PORT datac (809:809:809) (805:805:805)) - (PORT datad (829:829:829) (860:860:860)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) - (DELAY - (ABSOLUTE - (PORT dataa (835:835:835) (809:809:809)) - (PORT datab (623:623:623) (666:666:666)) - (PORT datac (899:899:899) (929:929:929)) - (PORT datad (1646:1646:1646) (1664:1664:1664)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1201:1201:1201) (1254:1254:1254)) - (PORT datab (820:820:820) (825:825:825)) - (PORT datac (579:579:579) (580:580:580)) - (PORT datad (1600:1600:1600) (1599:1599:1599)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1258:1258:1258) (1346:1346:1346)) - (PORT datab (597:597:597) (633:633:633)) - (PORT datac (810:810:810) (806:806:806)) - (PORT datad (355:355:355) (359:359:359)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (851:851:851)) - (PORT datab (627:627:627) (668:668:668)) - (PORT datac (894:894:894) (935:935:935)) - (PORT datad (579:579:579) (570:570:570)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1347:1347:1347) (1368:1368:1368)) - (PORT datab (867:867:867) (863:863:863)) - (PORT datac (173:173:173) (204:204:204)) - (PORT datad (1302:1302:1302) (1304:1304:1304)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1469:1469:1469) (1500:1500:1500)) - (PORT datab (1474:1474:1474) (1453:1453:1453)) - (PORT datac (920:920:920) (954:954:954)) - (PORT datad (1434:1434:1434) (1445:1445:1445)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1352:1352:1352) (1366:1366:1366)) - (PORT datab (824:824:824) (865:865:865)) - (PORT datac (758:758:758) (792:792:792)) - (PORT datad (550:550:550) (549:549:549)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1349:1349:1349) (1363:1363:1363)) - (PORT datab (825:825:825) (869:869:869)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (842:842:842) (874:874:874)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (554:554:554) (549:549:549)) - (PORT datab (794:794:794) (812:812:812)) - (PORT datac (731:731:731) (762:762:762)) - (PORT datad (725:725:725) (755:755:755)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (604:604:604)) - (PORT datab (214:214:214) (255:255:255)) - (PORT datac (1213:1213:1213) (1288:1288:1288)) - (PORT datad (2060:2060:2060) (2081:2081:2081)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1666:1666:1666) (1749:1749:1749)) - (PORT datab (1520:1520:1520) (1585:1585:1585)) - (PORT datac (1196:1196:1196) (1253:1253:1253)) - (PORT datad (2365:2365:2365) (2392:2392:2392)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1167:1167:1167) (1182:1182:1182)) - (PORT datab (803:803:803) (793:793:793)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (546:546:546) (541:541:541)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1342:1342:1342) (1384:1384:1384)) - (PORT datab (236:236:236) (278:278:278)) - (PORT datac (1106:1106:1106) (1143:1143:1143)) - (PORT datad (776:776:776) (760:760:760)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~2) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (815:815:815)) - (PORT datab (827:827:827) (812:812:812)) - (PORT datac (798:798:798) (782:782:782)) - (PORT datad (830:830:830) (868:868:868)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (795:795:795) (821:821:821)) - (PORT datab (865:865:865) (910:910:910)) - (PORT datac (173:173:173) (217:217:217)) - (PORT datad (1070:1070:1070) (1075:1075:1075)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1350:1350:1350) (1336:1336:1336)) - (PORT datab (1385:1385:1385) (1402:1402:1402)) - (PORT datac (1018:1018:1018) (1017:1017:1017)) - (PORT datad (369:369:369) (395:395:395)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (782:782:782) (812:812:812)) - (PORT datab (829:829:829) (812:812:812)) - (PORT datac (800:800:800) (784:784:784)) - (PORT datad (831:831:831) (871:871:871)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (727:727:727)) - (PORT datab (721:721:721) (791:791:791)) - (PORT datad (1092:1092:1092) (1075:1075:1075)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (555:555:555) (538:538:538)) - (PORT datab (1080:1080:1080) (1067:1067:1067)) - (PORT datac (796:796:796) (816:816:816)) - (PORT datad (838:838:838) (844:844:844)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1342:1342:1342) (1386:1386:1386)) - (PORT datab (799:799:799) (795:795:795)) - (PORT datac (1177:1177:1177) (1213:1213:1213)) - (PORT datad (1481:1481:1481) (1552:1552:1552)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1376:1376:1376) (1455:1455:1455)) - (PORT datab (1328:1328:1328) (1314:1314:1314)) - (PORT datac (1318:1318:1318) (1387:1387:1387)) - (PORT datad (376:376:376) (397:397:397)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (936:936:936) (940:940:940)) - (PORT datac (742:742:742) (722:722:722)) - (PORT datad (941:941:941) (930:930:930)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (368:368:368) (398:398:398)) - (PORT datac (907:907:907) (902:902:902)) - (PORT datad (167:167:167) (191:191:191)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (319:319:319) (330:330:330)) - (PORT datab (181:181:181) (212:212:212)) - (PORT datac (547:547:547) (551:551:551)) - (PORT datad (1399:1399:1399) (1467:1467:1467)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1148:1148:1148)) - (PORT datab (1126:1126:1126) (1152:1152:1152)) - (PORT datac (820:820:820) (852:852:852)) - (PORT datad (1400:1400:1400) (1447:1447:1447)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (784:784:784)) - (PORT datab (208:208:208) (247:247:247)) - (PORT datac (1074:1074:1074) (1134:1134:1134)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1554:1554:1554) (1578:1578:1578)) - (PORT datab (1555:1555:1555) (1584:1584:1584)) - (PORT datac (1366:1366:1366) (1422:1422:1422)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (923:923:923)) - (PORT datab (187:187:187) (221:221:221)) - (PORT datac (1105:1105:1105) (1128:1128:1128)) - (PORT datad (820:820:820) (821:821:821)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) - (DELAY - (ABSOLUTE - (PORT datab (1117:1117:1117) (1098:1098:1098)) - (PORT datac (1157:1157:1157) (1166:1166:1166)) - (PORT datad (735:735:735) (714:714:714)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (864:864:864)) - (PORT datab (873:873:873) (894:894:894)) - (PORT datac (1056:1056:1056) (1047:1047:1047)) - (PORT datad (356:356:356) (376:376:376)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1190:1190:1190) (1198:1198:1198)) - (PORT datab (1113:1113:1113) (1096:1096:1096)) - (PORT datac (1053:1053:1053) (1046:1046:1046)) - (PORT datad (735:735:735) (713:713:713)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (307:307:307)) - (PORT datab (200:200:200) (245:245:245)) - (PORT datac (316:316:316) (331:331:331)) - (PORT datad (1131:1131:1131) (1174:1174:1174)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1084:1084:1084) (1078:1078:1078)) - (PORT datab (1108:1108:1108) (1126:1126:1126)) - (PORT datad (1131:1131:1131) (1181:1181:1181)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de2) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1414:1414:1414) (1380:1380:1380)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (357:357:357)) - (PORT datab (199:199:199) (242:242:242)) - (PORT datac (200:200:200) (270:270:270)) - (PORT datad (1114:1114:1114) (1162:1162:1162)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (526:526:526) (519:519:519)) - (PORT datab (960:960:960) (961:961:961)) - (PORT datac (314:314:314) (324:324:324)) - (PORT datad (635:635:635) (668:668:668)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (629:629:629)) - (PORT datab (1595:1595:1595) (1613:1613:1613)) - (PORT datad (813:813:813) (804:804:804)) - (IOPATH dataa combout (267:267:267) (273:273:273)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (2436:2436:2436) (2440:2440:2440)) - (PORT datab (1579:1579:1579) (1634:1634:1634)) - (PORT datac (945:945:945) (943:943:943)) - (PORT datad (1419:1419:1419) (1423:1423:1423)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (251:251:251)) - (PORT datab (819:819:819) (824:824:824)) - (PORT datac (1371:1371:1371) (1418:1418:1418)) - (PORT datad (1122:1122:1122) (1134:1134:1134)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) - (DELAY - (ABSOLUTE - (PORT dataa (897:897:897) (921:921:921)) - (PORT datab (185:185:185) (222:222:222)) - (PORT datac (878:878:878) (906:906:906)) - (PORT datad (190:190:190) (217:217:217)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla30npla13M5T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (878:878:878) (908:908:908)) - (PORT datab (210:210:210) (251:251:251)) - (PORT datac (1296:1296:1296) (1317:1317:1317)) - (PORT datad (1395:1395:1395) (1410:1410:1410)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1065:1065:1065) (1073:1073:1073)) - (PORT datab (1434:1434:1434) (1430:1430:1430)) - (PORT datac (553:553:553) (573:573:573)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (332:332:332) (347:347:347)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (155:155:155) (184:184:184)) - (PORT datad (163:163:163) (187:187:187)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (847:847:847)) - (PORT datab (615:615:615) (615:615:615)) - (PORT datac (1030:1030:1030) (994:994:994)) - (PORT datad (723:723:723) (705:705:705)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1491:1491:1491) (1597:1597:1597)) - (PORT datab (1403:1403:1403) (1444:1444:1444)) - (PORT datac (1573:1573:1573) (1621:1621:1621)) - (PORT datad (986:986:986) (963:963:963)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1855:1855:1855) (1982:1982:1982)) - (PORT datab (1351:1351:1351) (1392:1392:1392)) - (PORT datac (1387:1387:1387) (1427:1427:1427)) - (PORT datad (1772:1772:1772) (1781:1781:1781)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (835:835:835) (863:863:863)) - (PORT datab (808:808:808) (808:808:808)) - (PORT datac (747:747:747) (789:789:789)) - (PORT datad (1402:1402:1402) (1458:1458:1458)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (579:579:579) (590:590:590)) - (PORT datab (616:616:616) (645:645:645)) - (PORT datac (850:850:850) (872:872:872)) - (PORT datad (164:164:164) (190:190:190)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (669:669:669)) - (PORT datab (1098:1098:1098) (1128:1128:1128)) - (PORT datac (615:615:615) (620:620:620)) - (PORT datad (1199:1199:1199) (1235:1235:1235)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1268:1268:1268) (1283:1283:1283)) - (PORT datab (599:599:599) (612:612:612)) - (PORT datac (1228:1228:1228) (1222:1222:1222)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1022:1022:1022) (1093:1093:1093)) - (PORT datab (1683:1683:1683) (1698:1698:1698)) - (PORT datad (892:892:892) (959:959:959)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (841:841:841) (839:839:839)) - (PORT datab (631:631:631) (663:663:663)) - (PORT datac (182:182:182) (216:216:216)) - (PORT datad (2040:2040:2040) (2019:2019:2019)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1154:1154:1154) (1188:1188:1188)) - (PORT datab (1375:1375:1375) (1404:1404:1404)) - (PORT datac (1140:1140:1140) (1139:1139:1139)) - (PORT datad (1133:1133:1133) (1131:1131:1131)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1770:1770:1770) (1773:1773:1773)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (797:797:797) (838:838:838)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (568:568:568)) - (PORT datab (199:199:199) (233:233:233)) - (PORT datac (824:824:824) (827:827:827)) - (PORT datad (752:752:752) (779:779:779)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (751:751:751) (800:800:800)) - (PORT datab (186:186:186) (222:222:222)) - (PORT datac (521:521:521) (520:520:520)) - (PORT datad (572:572:572) (593:593:593)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (787:787:787)) - (PORT datac (188:188:188) (230:230:230)) - (PORT datad (184:184:184) (217:217:217)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1214:1214:1214) (1240:1240:1240)) - (PORT datab (574:574:574) (563:563:563)) - (PORT datac (779:779:779) (772:772:772)) - (PORT datad (568:568:568) (574:574:574)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1303:1303:1303) (1325:1325:1325)) - (PORT datab (851:851:851) (858:858:858)) - (PORT datac (1050:1050:1050) (1064:1064:1064)) - (PORT datad (1086:1086:1086) (1124:1124:1124)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1615:1615:1615) (1648:1648:1648)) - (PORT datab (777:777:777) (759:759:759)) - (PORT datac (1852:1852:1852) (1834:1834:1834)) - (PORT datad (1888:1888:1888) (1939:1939:1939)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~40) - (DELAY - (ABSOLUTE - (PORT dataa (855:855:855) (870:870:870)) - (PORT datab (1014:1014:1014) (1032:1032:1032)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (508:508:508) (501:501:501)) - (PORT datab (615:615:615) (629:629:629)) - (PORT datac (1842:1842:1842) (1822:1822:1822)) - (PORT datad (511:511:511) (487:487:487)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (791:791:791) (833:833:833)) - (PORT datac (162:162:162) (194:194:194)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (220:220:220)) - (PORT datab (790:790:790) (781:781:781)) - (PORT datac (530:530:530) (525:525:525)) - (PORT datad (166:166:166) (189:189:189)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~93) - (DELAY - (ABSOLUTE - (PORT dataa (1105:1105:1105) (1110:1110:1110)) - (PORT datab (984:984:984) (938:938:938)) - (PORT datac (1084:1084:1084) (1078:1078:1078)) - (PORT datad (1262:1262:1262) (1238:1238:1238)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) - (DELAY - (ABSOLUTE - (PORT dataa (226:226:226) (301:301:301)) - (PORT datab (199:199:199) (242:242:242)) - (PORT datac (314:314:314) (326:326:326)) - (PORT datad (1115:1115:1115) (1162:1162:1162)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) - (DELAY - (ABSOLUTE - (PORT datab (1303:1303:1303) (1278:1278:1278)) - (PORT datac (1080:1080:1080) (1073:1073:1073)) - (PORT datad (551:551:551) (560:560:560)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) - (DELAY - (ABSOLUTE - (PORT datac (836:836:836) (844:844:844)) - (PORT datad (1247:1247:1247) (1232:1232:1232)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1085:1085:1085) (1104:1104:1104)) - (PORT datab (202:202:202) (244:244:244)) - (PORT datac (1054:1054:1054) (1051:1051:1051)) - (PORT datad (624:624:624) (643:643:643)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (685:685:685)) - (PORT datab (1364:1364:1364) (1393:1393:1393)) - (PORT datac (1057:1057:1057) (1051:1051:1051)) - (PORT datad (179:179:179) (212:212:212)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) - (DELAY - (ABSOLUTE - (PORT dataa (643:643:643) (678:678:678)) - (PORT datab (1366:1366:1366) (1398:1398:1398)) - (PORT datac (1051:1051:1051) (1047:1047:1047)) - (PORT datad (176:176:176) (209:209:209)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1241:1241:1241) (1264:1264:1264)) - (PORT datab (802:802:802) (818:818:818)) - (PORT datac (1675:1675:1675) (1702:1702:1702)) - (PORT datad (1446:1446:1446) (1466:1466:1466)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datad (798:798:798) (802:802:802)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) - (DELAY - (ABSOLUTE - (PORT dataa (907:907:907) (968:968:968)) - (PORT datab (603:603:603) (608:608:608)) - (PORT datac (851:851:851) (875:875:875)) - (PORT datad (1334:1334:1334) (1387:1387:1387)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (1018:1018:1018) (1057:1057:1057)) - (PORT datab (651:651:651) (704:704:704)) - (PORT datac (1319:1319:1319) (1387:1387:1387)) - (PORT datad (1351:1351:1351) (1415:1415:1415)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (559:559:559) (558:558:558)) - (PORT datab (187:187:187) (223:223:223)) - (PORT datac (576:576:576) (588:588:588)) - (PORT datad (1016:1016:1016) (977:977:977)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (370:370:370)) - (PORT datab (1097:1097:1097) (1091:1091:1091)) - (PORT datac (330:330:330) (337:337:337)) - (PORT datad (1019:1019:1019) (993:993:993)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1153:1153:1153) (1192:1192:1192)) - (PORT datab (1464:1464:1464) (1534:1534:1534)) - (PORT datac (2034:2034:2034) (2016:2016:2016)) - (PORT datad (985:985:985) (1044:1044:1044)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) - (DELAY - (ABSOLUTE - (PORT dataa (880:880:880) (909:909:909)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1151:1151:1151) (1162:1162:1162)) - (PORT datad (178:178:178) (199:199:199)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) - (DELAY - (ABSOLUTE - (PORT dataa (576:576:576) (587:587:587)) - (PORT datac (614:614:614) (623:623:623)) - (PORT datad (519:519:519) (489:489:489)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1065:1065:1065) (1076:1076:1076)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (1048:1048:1048) (1041:1041:1041)) - (PORT datad (615:615:615) (635:635:635)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~2) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (840:840:840)) - (PORT datab (823:823:823) (821:821:821)) - (PORT datac (839:839:839) (888:888:888)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (674:674:674)) - (PORT datab (1094:1094:1094) (1073:1073:1073)) - (PORT datad (877:877:877) (872:872:872)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_af) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1361:1361:1361)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1368:1368:1368)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1063:1063:1063) (1081:1081:1081)) - (PORT datab (225:225:225) (296:296:296)) - (PORT datac (1056:1056:1056) (1051:1051:1051)) - (PORT datad (624:624:624) (643:643:643)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (644:644:644)) - (PORT datab (1269:1269:1269) (1248:1248:1248)) - (PORT datad (843:843:843) (858:858:858)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1063:1063:1063) (1075:1075:1075)) - (PORT datab (226:226:226) (299:299:299)) - (PORT datac (1050:1050:1050) (1045:1045:1045)) - (PORT datad (614:614:614) (638:638:638)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) - (DELAY - (ABSOLUTE - (PORT dataa (1612:1612:1612) (1604:1604:1604)) - (PORT datab (1085:1085:1085) (1084:1084:1084)) - (PORT datad (744:744:744) (705:705:705)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (681:681:681)) - (PORT datab (857:857:857) (878:878:878)) - (PORT datac (1675:1675:1675) (1732:1732:1732)) - (PORT datad (1057:1057:1057) (1054:1054:1054)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1364:1364:1364) (1424:1424:1424)) - (PORT datac (942:942:942) (961:961:961)) - (PORT datad (304:304:304) (309:309:309)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1321:1321:1321) (1321:1321:1321)) - (PORT datab (1079:1079:1079) (1103:1103:1103)) - (PORT datac (1868:1868:1868) (1905:1905:1905)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1079:1079:1079) (1075:1075:1075)) - (PORT datab (1895:1895:1895) (1904:1904:1904)) - (PORT datac (878:878:878) (907:907:907)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (764:764:764) (823:823:823)) - (PORT datab (1401:1401:1401) (1421:1421:1421)) - (PORT datac (1205:1205:1205) (1204:1204:1204)) - (PORT datad (802:802:802) (787:787:787)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) - (DELAY - (ABSOLUTE - (PORT datab (207:207:207) (246:246:246)) - (PORT datac (182:182:182) (217:217:217)) - (PORT datad (184:184:184) (209:209:209)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (1424:1424:1424) (1497:1497:1497)) - (PORT datac (186:186:186) (222:222:222)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) - (DELAY - (ABSOLUTE - (PORT dataa (549:549:549) (551:551:551)) - (PORT datab (811:811:811) (812:812:812)) - (PORT datac (1275:1275:1275) (1293:1293:1293)) - (PORT datad (1806:1806:1806) (1800:1800:1800)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (240:240:240)) - (PORT datab (1860:1860:1860) (1858:1858:1858)) - (PORT datac (752:752:752) (731:731:731)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (633:633:633) (662:662:662)) - (PORT datab (1339:1339:1339) (1359:1359:1359)) - (PORT datac (330:330:330) (348:348:348)) - (PORT datad (1037:1037:1037) (1058:1058:1058)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (251:251:251)) - (PORT datab (527:527:527) (514:514:514)) - (PORT datac (745:745:745) (740:740:740)) - (PORT datad (550:550:550) (564:564:564)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1084:1084:1084) (1118:1118:1118)) - (PORT datab (554:554:554) (551:551:551)) - (PORT datac (594:594:594) (624:624:624)) - (PORT datad (792:792:792) (796:796:796)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (659:659:659)) - (PORT datab (1109:1109:1109) (1110:1110:1110)) - (PORT datac (1070:1070:1070) (1080:1080:1080)) - (PORT datad (549:549:549) (536:536:536)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) - (DELAY - (ABSOLUTE - (PORT dataa (831:831:831) (830:830:830)) - (PORT datab (1103:1103:1103) (1126:1126:1126)) - (PORT datac (830:830:830) (843:843:843)) - (PORT datad (586:586:586) (608:608:608)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) - (DELAY - (ABSOLUTE - (PORT dataa (543:543:543) (543:543:543)) - (PORT datab (182:182:182) (216:216:216)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (862:862:862)) - (PORT datab (1104:1104:1104) (1125:1125:1125)) - (PORT datac (332:332:332) (352:352:352)) - (PORT datad (1035:1035:1035) (1058:1058:1058)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1083:1083:1083) (1119:1119:1119)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1071:1071:1071) (1083:1083:1083)) - (PORT datad (789:789:789) (795:795:795)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) - (DELAY - (ABSOLUTE - (PORT dataa (188:188:188) (228:228:228)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (593:593:593) (623:623:623)) - (PORT datad (785:785:785) (799:799:799)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (577:577:577) (565:565:565)) - (PORT datab (634:634:634) (646:646:646)) - (PORT datac (350:350:350) (370:370:370)) - (PORT datad (184:184:184) (208:208:208)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (565:565:565) (563:563:563)) - (PORT datac (499:499:499) (482:482:482)) - (PORT datad (781:781:781) (787:787:787)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (880:880:880)) - (PORT datab (1437:1437:1437) (1501:1501:1501)) - (PORT datac (1296:1296:1296) (1312:1312:1312)) - (PORT datad (182:182:182) (213:213:213)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (569:569:569) (594:594:594)) - (PORT datab (884:884:884) (945:945:945)) - (PORT datac (1595:1595:1595) (1641:1641:1641)) - (PORT datad (1057:1057:1057) (1049:1049:1049)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1019:1019:1019) (1055:1055:1055)) - (PORT datab (1346:1346:1346) (1415:1415:1415)) - (PORT datac (1487:1487:1487) (1528:1528:1528)) - (PORT datad (1084:1084:1084) (1099:1099:1099)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1292:1292:1292) (1272:1272:1272)) - (PORT datab (1148:1148:1148) (1164:1164:1164)) - (PORT datac (1167:1167:1167) (1153:1153:1153)) - (PORT datad (1172:1172:1172) (1180:1180:1180)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1049:1049:1049) (1030:1030:1030)) - (PORT datac (570:570:570) (565:565:565)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~28) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (256:256:256)) - (PORT datab (199:199:199) (231:231:231)) - (PORT datac (1059:1059:1059) (1076:1076:1076)) - (PORT datad (177:177:177) (197:197:197)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~35) - (DELAY - (ABSOLUTE - (PORT datab (1858:1858:1858) (1864:1864:1864)) - (PORT datac (1247:1247:1247) (1235:1235:1235)) - (PORT datad (790:790:790) (789:789:789)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~36) - (DELAY - (ABSOLUTE - (PORT dataa (196:196:196) (240:240:240)) - (PORT datab (840:840:840) (833:833:833)) - (PORT datac (578:578:578) (576:576:576)) - (PORT datad (849:849:849) (870:870:870)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1397:1397:1397) (1416:1416:1416)) - (PORT datab (1081:1081:1081) (1069:1069:1069)) - (PORT datac (1016:1016:1016) (1034:1034:1034)) - (PORT datad (505:505:505) (499:499:499)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (573:573:573) (580:580:580)) - (PORT datab (213:213:213) (251:251:251)) - (PORT datac (1050:1050:1050) (1062:1062:1062)) - (PORT datad (179:179:179) (201:201:201)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1502:1502:1502) (1572:1572:1572)) - (PORT datab (938:938:938) (988:988:988)) - (PORT datac (951:951:951) (1012:1012:1012)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1081:1081:1081) (1102:1102:1102)) - (PORT datab (1421:1421:1421) (1474:1474:1474)) - (PORT datad (184:184:184) (207:207:207)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (825:825:825)) - (PORT datab (529:529:529) (526:526:526)) - (PORT datac (561:561:561) (561:561:561)) - (PORT datad (557:557:557) (551:551:551)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1167:1167:1167)) - (PORT datab (1177:1177:1177) (1248:1248:1248)) - (PORT datac (1063:1063:1063) (1080:1080:1080)) - (PORT datad (650:650:650) (693:693:693)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (658:658:658)) - (PORT datab (1248:1248:1248) (1207:1207:1207)) - (PORT datac (1129:1129:1129) (1140:1140:1140)) - (PORT datad (1536:1536:1536) (1551:1551:1551)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (933:933:933) (979:979:979)) - (PORT datab (833:833:833) (842:842:842)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (202:202:202) (225:225:225)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (947:947:947) (1023:1023:1023)) - (PORT datac (2019:2019:2019) (2030:2030:2030)) - (PORT datad (599:599:599) (636:636:636)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (667:667:667) (697:697:697)) - (PORT datab (1056:1056:1056) (1042:1042:1042)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (1057:1057:1057) (1062:1062:1062)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (939:939:939) (993:993:993)) - (PORT datab (618:618:618) (616:616:616)) - (PORT datac (929:929:929) (990:990:990)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (230:230:230)) - (PORT datab (182:182:182) (216:216:216)) - (PORT datac (163:163:163) (197:197:197)) - (PORT datad (863:863:863) (870:870:870)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) - (DELAY - (ABSOLUTE - (PORT datab (251:251:251) (327:327:327)) - (PORT datac (217:217:217) (285:285:285)) - (PORT datad (223:223:223) (285:285:285)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (887:887:887)) - (PORT datab (199:199:199) (232:232:232)) - (PORT datac (1024:1024:1024) (1002:1002:1002)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1021:1021:1021) (1095:1095:1095)) - (PORT datab (200:200:200) (233:233:233)) - (PORT datac (592:592:592) (638:638:638)) - (PORT datad (891:891:891) (959:959:959)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (2372:2372:2372) (2400:2400:2400)) - (PORT datab (1481:1481:1481) (1548:1548:1548)) - (PORT datac (175:175:175) (207:207:207)) - (PORT datad (199:199:199) (236:236:236)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (987:987:987) (1008:1008:1008)) - (PORT datab (186:186:186) (221:221:221)) - (PORT datac (822:822:822) (802:802:802)) - (PORT datad (770:770:770) (760:760:760)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) - (DELAY - (ABSOLUTE - (PORT datab (852:852:852) (879:879:879)) - (PORT datad (579:579:579) (590:590:590)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (581:581:581) (607:607:607)) - (PORT datab (843:843:843) (873:873:873)) - (PORT datac (998:998:998) (992:992:992)) - (PORT datad (183:183:183) (207:207:207)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~4) - (DELAY - (ABSOLUTE - (PORT dataa (827:827:827) (855:855:855)) - (PORT datab (836:836:836) (832:832:832)) - (PORT datac (577:577:577) (600:600:600)) - (PORT datad (826:826:826) (816:816:816)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (1848:1848:1848) (1914:1914:1914)) - (PORT datab (833:833:833) (859:859:859)) - (PORT datac (197:197:197) (239:239:239)) - (PORT datad (1066:1066:1066) (1061:1061:1061)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~5) - (DELAY - (ABSOLUTE - (PORT dataa (853:853:853) (886:886:886)) - (PORT datab (847:847:847) (864:864:864)) - (PORT datac (815:815:815) (817:817:817)) - (PORT datad (555:555:555) (563:563:563)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) - (DELAY - (ABSOLUTE - (PORT dataa (833:833:833) (845:845:845)) - (PORT datad (164:164:164) (189:189:189)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1003:1003:1003) (988:988:988)) - (PORT datab (828:828:828) (845:845:845)) - (PORT datac (561:561:561) (591:591:591)) - (PORT datad (799:799:799) (810:810:810)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~16) - (DELAY - (ABSOLUTE - (PORT dataa (2231:2231:2231) (2295:2295:2295)) - (PORT datab (1676:1676:1676) (1732:1732:1732)) - (PORT datac (994:994:994) (967:967:967)) - (PORT datad (1468:1468:1468) (1554:1554:1554)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) - (DELAY - (ABSOLUTE - (PORT dataa (769:769:769) (746:746:746)) - (PORT datab (846:846:846) (845:845:845)) - (PORT datac (771:771:771) (772:772:772)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (2232:2232:2232) (2296:2296:2296)) - (PORT datab (2223:2223:2223) (2283:2283:2283)) - (PORT datac (1302:1302:1302) (1339:1339:1339)) - (PORT datad (1465:1465:1465) (1553:1553:1553)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (207:207:207) (245:245:245)) - (PORT datac (183:183:183) (220:220:220)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1150:1150:1150) (1196:1196:1196)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (769:769:769) (746:746:746)) - (PORT datad (807:807:807) (817:817:817)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (817:817:817) (796:796:796)) - (PORT datab (216:216:216) (254:254:254)) - (PORT datac (572:572:572) (594:594:594)) - (PORT datad (1245:1245:1245) (1260:1260:1260)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1195:1195:1195)) - (PORT datab (1281:1281:1281) (1366:1366:1366)) - (PORT datac (800:800:800) (838:838:838)) - (PORT datad (779:779:779) (766:766:766)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1902:1902:1902) (1924:1924:1924)) - (PORT datab (2319:2319:2319) (2469:2469:2469)) - (PORT datac (2661:2661:2661) (2717:2717:2717)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (786:786:786) (805:805:805)) - (PORT datac (919:919:919) (926:926:926)) - (PORT datad (1273:1273:1273) (1259:1259:1259)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (197:197:197) (241:241:241)) - (PORT datac (609:609:609) (621:621:621)) - (PORT datad (955:955:955) (992:992:992)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1226:1226:1226) (1317:1317:1317)) - (PORT datac (1093:1093:1093) (1091:1091:1091)) - (PORT datad (1863:1863:1863) (1900:1900:1900)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1036:1036:1036) (1029:1029:1029)) - (PORT datab (204:204:204) (240:240:240)) - (PORT datac (557:557:557) (554:554:554)) - (PORT datad (1064:1064:1064) (1079:1079:1079)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1023:1023:1023) (1113:1113:1113)) - (PORT datac (1050:1050:1050) (1044:1044:1044)) - (PORT datad (880:880:880) (917:917:917)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) - (DELAY - (ABSOLUTE - (PORT datab (1942:1942:1942) (1961:1961:1961)) - (PORT datac (856:856:856) (896:896:896)) - (PORT datad (1825:1825:1825) (1843:1843:1843)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1094:1094:1094) (1117:1117:1117)) - (PORT datab (565:565:565) (549:549:549)) - (PORT datac (806:806:806) (820:820:820)) - (PORT datad (1059:1059:1059) (1068:1068:1068)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1048:1048:1048) (1033:1033:1033)) - (PORT datab (553:553:553) (543:543:543)) - (PORT datac (1042:1042:1042) (1045:1045:1045)) - (PORT datad (810:810:810) (811:811:811)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1663:1663:1663) (1690:1690:1690)) - (PORT datab (1460:1460:1460) (1462:1462:1462)) - (PORT datad (920:920:920) (921:921:921)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (852:852:852) (853:853:853)) - (PORT datab (1074:1074:1074) (1100:1100:1100)) - (PORT datac (1370:1370:1370) (1409:1409:1409)) - (PORT datad (1025:1025:1025) (1017:1017:1017)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (656:656:656)) - (PORT datab (843:843:843) (834:834:834)) - (PORT datac (575:575:575) (572:572:572)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (217:217:217)) - (PORT datab (182:182:182) (213:213:213)) - (PORT datac (1401:1401:1401) (1413:1413:1413)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (853:853:853) (855:855:855)) - (PORT datab (829:829:829) (870:870:870)) - (PORT datac (169:169:169) (207:207:207)) - (PORT datad (816:816:816) (798:798:798)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (1591:1591:1591) (1613:1613:1613)) - (PORT datad (303:303:303) (314:314:314)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1101:1101:1101) (1097:1097:1097)) - (PORT datab (780:780:780) (766:766:766)) - (PORT datac (784:784:784) (778:778:778)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1431:1431:1431) (1492:1492:1492)) - (PORT datab (1625:1625:1625) (1632:1632:1632)) - (PORT datac (2403:2403:2403) (2409:2409:2409)) - (PORT datad (1067:1067:1067) (1081:1081:1081)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (2438:2438:2438) (2445:2445:2445)) - (PORT datab (1459:1459:1459) (1552:1552:1552)) - (PORT datac (581:581:581) (581:581:581)) - (PORT datad (185:185:185) (212:212:212)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (572:572:572) (563:563:563)) - (PORT datab (604:604:604) (616:616:616)) - (PORT datac (583:583:583) (607:607:607)) - (PORT datad (790:790:790) (806:806:806)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) - (DELAY - (ABSOLUTE - (PORT datab (659:659:659) (665:665:665)) - (PORT datac (981:981:981) (963:963:963)) - (PORT datad (842:842:842) (856:856:856)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (333:333:333) (357:357:357)) - (PORT datab (1036:1036:1036) (1034:1034:1034)) - (PORT datac (965:965:965) (955:955:955)) - (PORT datad (773:773:773) (761:761:761)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1599:1599:1599) (1605:1605:1605)) - (PORT datab (824:824:824) (816:816:816)) - (PORT datac (1393:1393:1393) (1460:1460:1460)) - (PORT datad (1048:1048:1048) (1075:1075:1075)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1064:1064:1064) (1034:1034:1034)) - (PORT datab (1534:1534:1534) (1529:1529:1529)) - (PORT datac (1059:1059:1059) (1072:1072:1072)) - (PORT datad (194:194:194) (224:224:224)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (626:626:626)) - (PORT datab (1072:1072:1072) (1065:1065:1065)) - (PORT datac (1092:1092:1092) (1109:1109:1109)) - (PORT datad (891:891:891) (936:936:936)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~1) - (DELAY - (ABSOLUTE - (PORT dataa (266:266:266) (330:330:330)) - (PORT datac (1563:1563:1563) (1574:1574:1574)) - (PORT datad (394:394:394) (428:428:428)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (623:623:623)) - (PORT datab (1068:1068:1068) (1096:1096:1096)) - (PORT datac (1370:1370:1370) (1407:1407:1407)) - (PORT datad (1176:1176:1176) (1194:1194:1194)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1333:1333:1333) (1335:1335:1335)) - (PORT datab (846:846:846) (864:864:864)) - (PORT datac (830:830:830) (829:829:829)) - (PORT datad (893:893:893) (897:897:897)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) - (DELAY - (ABSOLUTE - (PORT dataa (814:814:814) (806:806:806)) - (PORT datac (924:924:924) (944:944:944)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (984:984:984) (1014:1014:1014)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1006:1006:1006) (987:987:987)) - (PORT datad (165:165:165) (188:188:188)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (331:331:331)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (320:320:320) (344:344:344)) - (PORT datad (793:793:793) (779:779:779)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1310:1310:1310) (1282:1282:1282)) - (PORT datab (770:770:770) (753:753:753)) - (PORT datac (1562:1562:1562) (1571:1571:1571)) - (PORT datad (851:851:851) (864:864:864)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) - (DELAY - (ABSOLUTE - (PORT dataa (1022:1022:1022) (1026:1026:1026)) - (PORT datab (620:620:620) (624:624:624)) - (PORT datac (805:805:805) (782:782:782)) - (PORT datad (811:811:811) (819:819:819)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (249:249:249)) - (PORT datab (594:594:594) (608:608:608)) - (PORT datac (1273:1273:1273) (1300:1300:1300)) - (PORT datad (1052:1052:1052) (1059:1059:1059)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1503:1503:1503) (1574:1574:1574)) - (PORT datab (939:939:939) (984:984:984)) - (PORT datac (1792:1792:1792) (1771:1771:1771)) - (PORT datad (1535:1535:1535) (1547:1547:1547)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (237:237:237)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (598:598:598) (624:624:624)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (246:246:246)) - (PORT datab (598:598:598) (591:591:591)) - (PORT datac (181:181:181) (215:215:215)) - (PORT datad (1100:1100:1100) (1080:1080:1080)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (949:949:949) (970:970:970)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (552:552:552) (562:562:562)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) - (DELAY - (ABSOLUTE - (PORT dataa (831:831:831) (859:859:859)) - (PORT datab (1049:1049:1049) (1051:1051:1051)) - (PORT datac (814:814:814) (819:819:819)) - (PORT datad (1055:1055:1055) (1070:1070:1070)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) - (DELAY - (ABSOLUTE - (PORT datab (199:199:199) (231:231:231)) - (PORT datac (547:547:547) (579:579:579)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) - (DELAY - (ABSOLUTE - (PORT dataa (194:194:194) (238:238:238)) - (PORT datac (514:514:514) (511:511:511)) - (PORT datad (750:750:750) (794:794:794)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1201:1201:1201) (1239:1239:1239)) - (PORT datab (610:610:610) (611:611:611)) - (PORT datac (176:176:176) (208:208:208)) - (PORT datad (1090:1090:1090) (1098:1098:1098)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) - (DELAY - (ABSOLUTE - (PORT dataa (527:527:527) (521:521:521)) - (PORT datac (731:731:731) (762:762:762)) - (PORT datad (724:724:724) (755:755:755)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (850:850:850)) - (PORT datab (615:615:615) (631:631:631)) - (PORT datac (349:349:349) (360:360:360)) - (PORT datad (549:549:549) (569:569:569)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~45) - (DELAY - (ABSOLUTE - (PORT dataa (586:586:586) (619:619:619)) - (PORT datab (810:810:810) (784:784:784)) - (PORT datac (794:794:794) (808:808:808)) - (PORT datad (591:591:591) (614:614:614)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~46) - (DELAY - (ABSOLUTE - (PORT datab (767:767:767) (753:753:753)) - (PORT datac (180:180:180) (215:215:215)) - (PORT datad (1316:1316:1316) (1348:1348:1348)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) - (DELAY - (ABSOLUTE - (PORT dataa (551:551:551) (542:542:542)) - (PORT datab (860:860:860) (874:874:874)) - (PORT datac (541:541:541) (537:537:537)) - (PORT datad (552:552:552) (548:548:548)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) - (DELAY - (ABSOLUTE - (PORT dataa (895:895:895) (904:904:904)) - (PORT datab (1439:1439:1439) (1492:1492:1492)) - (PORT datac (778:778:778) (780:780:780)) - (PORT datad (347:347:347) (357:357:357)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (188:188:188) (225:225:225)) - (PORT datab (317:317:317) (334:334:334)) - (PORT datac (189:189:189) (227:227:227)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~4) - (DELAY - (ABSOLUTE - (PORT dataa (853:853:853) (859:859:859)) - (PORT datac (801:801:801) (843:843:843)) - (PORT datad (777:777:777) (765:765:765)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (609:609:609)) - (PORT datab (1386:1386:1386) (1385:1385:1385)) - (PORT datac (759:759:759) (755:755:755)) - (PORT datad (767:767:767) (781:781:781)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (456:456:456)) - (PORT datab (863:863:863) (880:880:880)) - (PORT datac (347:347:347) (362:362:362)) - (PORT datad (1765:1765:1765) (1823:1823:1823)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~20) - (DELAY - (ABSOLUTE - (PORT dataa (2276:2276:2276) (2425:2425:2425)) - (PORT datab (513:513:513) (511:511:511)) - (PORT datac (825:825:825) (840:840:840)) - (PORT datad (1041:1041:1041) (1050:1050:1050)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (620:620:620)) - (PORT datab (539:539:539) (531:531:531)) - (PORT datac (725:725:725) (754:754:754)) - (PORT datad (184:184:184) (208:208:208)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) - (DELAY - (ABSOLUTE - (PORT dataa (548:548:548) (551:551:551)) - (PORT datab (811:811:811) (812:812:812)) - (PORT datac (1834:1834:1834) (1833:1833:1833)) - (PORT datad (558:558:558) (552:552:552)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1067:1067:1067) (1036:1036:1036)) - (PORT datab (1449:1449:1449) (1509:1509:1509)) - (PORT datac (592:592:592) (615:615:615)) - (PORT datad (560:560:560) (573:573:573)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) - (DELAY - (ABSOLUTE - (PORT dataa (824:824:824) (822:822:822)) - (PORT datab (522:522:522) (518:518:518)) - (PORT datac (567:567:567) (580:580:580)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (582:582:582) (608:608:608)) - (PORT datab (843:843:843) (873:873:873)) - (PORT datac (499:499:499) (485:485:485)) - (PORT datad (808:808:808) (804:804:804)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (249:249:249)) - (PORT datab (604:604:604) (610:610:610)) - (PORT datac (777:777:777) (770:770:770)) - (PORT datad (321:321:321) (324:324:324)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) - (DELAY - (ABSOLUTE - (PORT datab (1339:1339:1339) (1361:1361:1361)) - (PORT datac (845:845:845) (849:849:849)) - (PORT datad (758:758:758) (746:746:746)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (249:249:249)) - (PORT datab (1244:1244:1244) (1192:1192:1192)) - (PORT datac (1279:1279:1279) (1261:1261:1261)) - (PORT datad (291:291:291) (298:298:298)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) - (DELAY - (ABSOLUTE - (PORT datab (868:868:868) (895:895:895)) - (PORT datac (1335:1335:1335) (1361:1361:1361)) - (PORT datad (622:622:622) (633:633:633)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) - (PORT asdata (890:890:890) (916:916:916)) - (PORT ena (1105:1105:1105) (1078:1078:1078)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1743:1743:1743) (1706:1706:1706)) - (PORT datab (649:649:649) (667:667:667)) - (PORT datad (1111:1111:1111) (1126:1126:1126)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) - (DELAY - (ABSOLUTE - (PORT datab (661:661:661) (663:663:663)) - (PORT datac (983:983:983) (964:964:964)) - (PORT datad (844:844:844) (855:855:855)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1384:1384:1384)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1175:1175:1175) (1170:1170:1170)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (677:677:677) (704:704:704)) - (PORT datac (571:571:571) (586:586:586)) - (PORT datad (198:198:198) (256:256:256)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT datac (1855:1855:1855) (1856:1856:1856)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) - (DELAY - (ABSOLUTE - (PORT clk (1370:1370:1370) (1377:1377:1377)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT clk (1370:1370:1370) (1377:1377:1377)) - (PORT asdata (513:513:513) (580:580:580)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1370:1370:1370) (1377:1377:1377)) - (PORT asdata (513:513:513) (581:581:581)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE KEY\[0\]\~input) @@ -11353,8 +1127,8 @@ (INSTANCE reset) (DELAY (ABSOLUTE - (PORT datac (1395:1395:1395) (1420:1420:1420)) - (PORT datad (490:490:490) (462:462:462)) + (PORT datac (1395:1395:1395) (1419:1419:1419)) + (PORT datad (489:489:489) (462:462:462)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -11365,7 +1139,7 @@ (INSTANCE z80_\|resets_\|x1\~0) (DELAY (ABSOLUTE - (PORT datad (1368:1368:1368) (1388:1388:1388)) + (PORT datad (180:180:180) (203:203:203)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -11375,7 +1149,7 @@ (INSTANCE z80_\|fpga_reset) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1368:1368:1368)) + (PORT clk (1349:1349:1349) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -11389,7 +1163,7 @@ (INSTANCE z80_\|fpga_reset\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (666:666:666) (673:673:673)) + (PORT inclk[0] (683:683:683) (701:701:701)) ) ) ) @@ -11398,9 +1172,9 @@ (INSTANCE z80_\|resets_\|x1) (DELAY (ABSOLUTE - (PORT clk (1343:1343:1343) (1354:1354:1354)) + (PORT clk (1359:1359:1359) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1667:1667:1667) (1646:1646:1646)) + (PORT clrn (1395:1395:1395) (1365:1365:1365)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -11411,27 +1185,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc_int\~0) + (INSTANCE z80_\|resets_\|x3) (DELAY (ABSOLUTE - (PORT dataa (604:604:604) (644:644:644)) - (PORT datab (568:568:568) (588:588:588)) - (PORT datad (1091:1091:1091) (1101:1101:1101)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (312:312:312)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (1758:1758:1758) (1865:1865:1865)) + (PORT datac (1361:1361:1361) (1383:1383:1383)) + (PORT datad (1075:1075:1075) (1125:1125:1125)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|clrpc_int) + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) (DELAY (ABSOLUTE - (PORT clk (1370:1370:1370) (1377:1377:1377)) + (PORT clk (1355:1355:1355) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1409:1409:1409) (1380:1380:1380)) + (PORT clrn (1397:1397:1397) (1367:1367:1367)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -11442,166 +1215,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc\~0) + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) (DELAY (ABSOLUTE - (PORT dataa (228:228:228) (302:302:302)) - (PORT datab (230:230:230) (302:302:302)) - (PORT datad (198:198:198) (254:254:254)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[7\]) - (DELAY - (ABSOLUTE - (PORT datac (609:609:609) (625:625:625)) - (PORT datad (564:564:564) (566:566:566)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2273:2273:2273) (2429:2429:2429)) - (PORT datac (825:825:825) (843:843:843)) - (PORT datad (1842:1842:1842) (1863:1863:1863)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (351:351:351)) - (PORT datab (517:517:517) (516:516:516)) - (PORT datac (782:782:782) (783:783:783)) - (PORT datad (1040:1040:1040) (1050:1050:1050)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1033:1033:1033) (1044:1044:1044)) - (PORT datab (1069:1069:1069) (1075:1075:1075)) - (PORT datac (742:742:742) (726:726:726)) - (PORT datad (591:591:591) (584:584:584)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (912:912:912) (948:948:948)) - (PORT datab (1520:1520:1520) (1487:1487:1487)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (1059:1059:1059) (1072:1072:1072)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1168:1168:1168)) - (PORT datab (921:921:921) (984:984:984)) - (PORT datac (599:599:599) (642:642:642)) - (PORT datad (1151:1151:1151) (1210:1210:1210)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (727:727:727) (703:703:703)) - (PORT datab (610:610:610) (603:603:603)) - (PORT datac (777:777:777) (798:798:798)) - (PORT datad (957:957:957) (972:972:972)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (659:659:659) (658:658:658)) - (PORT datac (181:181:181) (214:214:214)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (222:222:222)) - (PORT datac (164:164:164) (200:200:200)) - (PORT datad (506:506:506) (506:506:506)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1152:1152:1152) (1192:1192:1192)) - (PORT datab (776:776:776) (746:746:746)) - (PORT datac (772:772:772) (748:748:748)) - (PORT datad (809:809:809) (817:817:817)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (PORT datac (672:672:672) (729:729:729)) + (PORT datad (281:281:281) (373:373:373)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -11609,1226 +1227,37 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[7\]) + (INSTANCE z80_\|interrupts_\|nmi_armed) (DELAY (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT clk (1978:1978:1978) (2017:2017:2017)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1370:1370:1370)) - (PORT ena (1981:1981:1981) (2010:2010:2010)) + (PORT clrn (1356:1356:1356) (1330:1330:1330)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) (DELAY (ABSOLUTE - (PORT dataa (378:378:378) (387:387:387)) - (PORT datab (1678:1678:1678) (1697:1697:1697)) - (PORT datac (181:181:181) (214:214:214)) - (PORT datad (594:594:594) (626:626:626)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT inclk[0] (2051:2051:2051) (2092:2092:2092)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~0) + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) (DELAY (ABSOLUTE - (PORT dataa (1125:1125:1125) (1167:1167:1167)) - (PORT datab (1853:1853:1853) (1913:1913:1913)) - (PORT datac (1198:1198:1198) (1284:1284:1284)) - (PORT datad (1866:1866:1866) (1903:1903:1903)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT datab (1370:1370:1370) (1411:1411:1411)) + (PORT datad (1524:1524:1524) (1631:1631:1631)) (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (367:367:367)) - (PORT datab (192:192:192) (233:233:233)) - (PORT datac (1025:1025:1025) (1018:1018:1018)) - (PORT datad (1111:1111:1111) (1100:1100:1100)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datab (1573:1573:1573) (1616:1616:1616)) - (PORT datac (518:518:518) (494:494:494)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) - (DELAY - (ABSOLUTE - (PORT datab (919:919:919) (924:924:924)) - (PORT datac (1042:1042:1042) (1028:1028:1028)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) - (DELAY - (ABSOLUTE - (PORT dataa (927:927:927) (951:951:951)) - (PORT datad (1038:1038:1038) (1031:1031:1031)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1384:1384:1384)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1175:1175:1175) (1170:1170:1170)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) - (DELAY - (ABSOLUTE - (PORT datab (1448:1448:1448) (1428:1428:1428)) - (PORT datac (1112:1112:1112) (1131:1131:1131)) - (PORT datad (1000:1000:1000) (984:984:984)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) - (DELAY - (ABSOLUTE - (PORT datab (1445:1445:1445) (1427:1427:1427)) - (PORT datac (1120:1120:1120) (1140:1140:1140)) - (PORT datad (914:914:914) (922:922:922)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) - (DELAY - (ABSOLUTE - (PORT datab (1444:1444:1444) (1428:1428:1428)) - (PORT datac (1121:1121:1121) (1141:1141:1141)) - (PORT datad (1001:1001:1001) (984:984:984)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (1304:1304:1304) (1285:1285:1285)) - (PORT ena (1588:1588:1588) (1555:1555:1555)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) - (DELAY - (ABSOLUTE - (PORT datab (1449:1449:1449) (1432:1432:1432)) - (PORT datac (1106:1106:1106) (1125:1125:1125)) - (PORT datad (919:919:919) (927:927:927)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (1304:1304:1304) (1285:1285:1285)) - (PORT ena (1297:1297:1297) (1275:1275:1275)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (808:808:808) (840:840:840)) - (PORT datab (886:886:886) (937:937:937)) - (PORT datad (196:196:196) (252:252:252)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) - (DELAY - (ABSOLUTE - (PORT datab (1300:1300:1300) (1274:1274:1274)) - (PORT datac (1084:1084:1084) (1079:1079:1079)) - (PORT datad (546:546:546) (554:554:554)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (668:668:668) (669:669:669)) - (PORT ena (735:735:735) (733:733:733)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (359:359:359)) - (PORT datab (200:200:200) (245:245:245)) - (PORT datac (200:200:200) (269:269:269)) - (PORT datad (1129:1129:1129) (1170:1170:1170)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) - (DELAY - (ABSOLUTE - (PORT datab (1107:1107:1107) (1100:1100:1100)) - (PORT datac (587:587:587) (609:609:609)) - (PORT datad (1264:1264:1264) (1244:1244:1244)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT datab (1109:1109:1109) (1104:1104:1104)) - (PORT datac (588:588:588) (608:608:608)) - (PORT datad (1264:1264:1264) (1238:1238:1238)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (667:667:667) (668:668:668)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (295:295:295)) - (PORT datab (231:231:231) (284:284:284)) - (PORT datad (211:211:211) (246:246:246)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) - (DELAY - (ABSOLUTE - (PORT datac (836:836:836) (843:843:843)) - (PORT datad (1245:1245:1245) (1229:1229:1229)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (680:680:680)) - (PORT datab (1084:1084:1084) (1078:1078:1078)) - (PORT datac (174:174:174) (214:214:214)) - (PORT datad (1330:1330:1330) (1362:1362:1362)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1094:1094:1094) (1096:1096:1096)) - (PORT ena (1155:1155:1155) (1140:1140:1140)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (681:681:681)) - (PORT datab (1081:1081:1081) (1078:1078:1078)) - (PORT datac (175:175:175) (213:213:213)) - (PORT datad (1333:1333:1333) (1363:1363:1363)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1095:1095:1095) (1094:1094:1094)) - (PORT ena (1109:1109:1109) (1074:1074:1074)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (444:444:444)) - (PORT datab (220:220:220) (288:288:288)) - (PORT datad (587:587:587) (590:590:590)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (593:593:593)) - (PORT datab (869:869:869) (890:890:890)) - (PORT datad (623:623:623) (628:628:628)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1550:1550:1550) (1525:1525:1525)) - (PORT ena (1380:1380:1380) (1365:1365:1365)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (603:603:603)) - (PORT datab (1301:1301:1301) (1284:1284:1284)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1065:1065:1065) (1076:1076:1076)) - (PORT datab (1080:1080:1080) (1077:1077:1077)) - (PORT datac (174:174:174) (213:213:213)) - (PORT datad (614:614:614) (636:636:636)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1121:1121:1121) (1124:1124:1124)) - (PORT ena (1123:1123:1123) (1106:1106:1106)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (850:850:850) (845:845:845)) - (PORT datab (385:385:385) (422:422:422)) - (PORT datac (853:853:853) (854:854:854)) - (PORT datad (566:566:566) (575:575:575)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (861:861:861)) - (PORT datab (871:871:871) (892:892:892)) - (PORT datac (1053:1053:1053) (1048:1048:1048)) - (PORT datad (356:356:356) (371:371:371)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) - (DELAY - (ABSOLUTE - (PORT datab (863:863:863) (889:889:889)) - (PORT datac (1245:1245:1245) (1225:1225:1225)) - (PORT datad (819:819:819) (837:837:837)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1088:1088:1088) (1108:1108:1108)) - (PORT datab (1086:1086:1086) (1078:1078:1078)) - (PORT datac (174:174:174) (214:214:214)) - (PORT datad (624:624:624) (642:642:642)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1551:1551:1551) (1526:1526:1526)) - (PORT ena (1132:1132:1132) (1112:1112:1112)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) - (DELAY - (ABSOLUTE - (PORT dataa (1680:1680:1680) (1620:1620:1620)) - (PORT datab (844:844:844) (872:872:872)) - (PORT datad (840:840:840) (857:857:857)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1122:1122:1122) (1126:1126:1126)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (394:394:394) (415:415:415)) - (PORT datab (583:583:583) (608:608:608)) - (PORT datad (337:337:337) (366:366:366)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) - (DELAY - (ABSOLUTE - (PORT dataa (1612:1612:1612) (1601:1601:1601)) - (PORT datab (1087:1087:1087) (1086:1086:1086)) - (PORT datad (743:743:743) (706:706:706)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1298:1298:1298) (1281:1281:1281)) - (PORT ena (746:746:746) (759:759:759)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (784:784:784) (790:790:790)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT datab (977:977:977) (950:950:950)) - (PORT datac (843:843:843) (859:859:859)) - (PORT datad (821:821:821) (834:834:834)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1154:1154:1154) (1142:1142:1142)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (381:381:381) (423:423:423)) - (PORT datab (543:543:543) (552:552:552)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (497:497:497) (482:482:482)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (617:617:617)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datad (727:727:727) (719:719:719)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (356:356:356)) - (PORT datab (579:579:579) (582:582:582)) - (PORT datac (1289:1289:1289) (1259:1259:1259)) - (PORT datad (578:578:578) (598:598:598)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) - (PORT asdata (1299:1299:1299) (1282:1282:1282)) - (PORT ena (1105:1105:1105) (1078:1078:1078)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (238:238:238)) - (PORT datab (1144:1144:1144) (1154:1154:1154)) - (PORT datad (603:603:603) (628:628:628)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (632:632:632) (639:639:639)) - (PORT datac (1056:1056:1056) (1072:1072:1072)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1384:1384:1384)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1175:1175:1175) (1170:1170:1170)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1344:1344:1344) (1323:1323:1323)) - (PORT ena (735:735:735) (733:733:733)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1344:1344:1344) (1323:1323:1323)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (295:295:295)) - (PORT datab (232:232:232) (284:284:284)) - (PORT datad (211:211:211) (246:246:246)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (1095:1095:1095) (1097:1097:1097)) - (PORT ena (739:739:739) (742:742:742)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|db\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1103:1103:1103) (1101:1101:1101)) - (PORT datab (1444:1444:1444) (1427:1427:1427)) - (PORT datad (1001:1001:1001) (984:984:984)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (1365:1365:1365) (1374:1374:1374)) - (PORT ena (1297:1297:1297) (1275:1275:1275)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (610:610:610)) - (PORT datab (1005:1005:1005) (1016:1016:1016)) - (PORT datad (860:860:860) (895:895:895)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1126:1126:1126) (1114:1114:1114)) - (PORT ena (1123:1123:1123) (1106:1106:1106)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1126:1126:1126) (1114:1114:1114)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (599:599:599) (636:636:636)) - (PORT datab (220:220:220) (289:289:289)) - (PORT datad (344:344:344) (355:355:355)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1347:1347:1347) (1368:1368:1368)) - (PORT ena (1381:1381:1381) (1365:1365:1365)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (320:320:320) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1155:1155:1155) (1140:1140:1140)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1345:1345:1345) (1365:1365:1365)) - (PORT ena (1295:1295:1295) (1246:1246:1246)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (403:403:403) (439:439:439)) - (PORT datab (607:607:607) (599:599:599)) - (PORT datad (765:765:765) (749:749:749)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1123:1123:1123) (1128:1128:1128)) - (PORT datab (855:855:855) (860:860:860)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (869:869:869) (860:860:860)) - (PORT ena (1109:1109:1109) (1074:1074:1074)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (400:400:400) (435:435:435)) - (PORT datab (1063:1063:1063) (1045:1045:1045)) - (PORT datad (504:504:504) (492:492:492)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1580:1580:1580) (1593:1593:1593)) - (PORT ena (746:746:746) (759:759:759)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1580:1580:1580) (1596:1596:1596)) - (PORT ena (1154:1154:1154) (1142:1142:1142)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (386:386:386) (426:426:426)) - (PORT datab (538:538:538) (545:545:545)) - (PORT datad (197:197:197) (252:252:252)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (558:558:558) (578:578:578)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (322:322:322) (325:325:325)) - (PORT datad (550:550:550) (542:542:542)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1119:1119:1119) (1114:1114:1114)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1018:1018:1018) (1023:1023:1023)) - (PORT datad (763:763:763) (762:762:762)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) - (PORT asdata (1466:1466:1466) (1434:1434:1434)) - (PORT ena (1105:1105:1105) (1078:1078:1078)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1083:1083:1083) (1062:1062:1062)) - (PORT datab (642:642:642) (660:660:660)) - (PORT datad (1099:1099:1099) (1118:1118:1118)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT datab (222:222:222) (290:290:290)) - (PORT datac (648:648:648) (673:673:673)) - (PORT datad (775:775:775) (771:771:771)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (877:877:877)) - (PORT datab (849:849:849) (884:884:884)) - (PORT datac (1400:1400:1400) (1394:1394:1394)) - (PORT datad (613:613:613) (652:652:652)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -12842,105 +1271,14 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~14) - (DELAY - (ABSOLUTE - (PORT datab (1297:1297:1297) (1300:1300:1300)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (241:241:241) (314:314:314)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~2) - (DELAY - (ABSOLUTE - (PORT datac (777:777:777) (776:776:776)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~18) - (DELAY - (ABSOLUTE - (PORT datad (609:609:609) (646:646:646)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~1) - (DELAY - (ABSOLUTE - (PORT datab (208:208:208) (246:246:246)) - (PORT datad (529:529:529) (517:517:517)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1372:1372:1372)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~0) (DELAY (ABSOLUTE - (PORT datab (997:997:997) (981:981:981)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (619:619:619) (662:662:662)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -12950,8 +1288,8 @@ (INSTANCE ula_\|video_\|vga_hc\~3) (DELAY (ABSOLUTE - (PORT datac (772:772:772) (785:785:785)) - (PORT datad (844:844:844) (838:838:838)) + (PORT datac (347:347:347) (361:361:361)) + (PORT datad (582:582:582) (577:577:577)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -12962,7 +1300,7 @@ (INSTANCE ula_\|video_\|vga_hc\[0\]) (DELAY (ABSOLUTE - (PORT clk (1359:1359:1359) (1375:1375:1375)) + (PORT clk (1360:1360:1360) (1377:1377:1377)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -12976,7 +1314,7 @@ (INSTANCE ula_\|video_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (629:629:629) (645:645:645)) + (PORT datab (430:430:430) (462:462:462)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -12990,7 +1328,7 @@ (INSTANCE ula_\|video_\|vga_hc\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (552:552:552) (552:552:552)) + (PORT datad (306:306:306) (310:310:310)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -13000,7 +1338,7 @@ (INSTANCE ula_\|video_\|vga_hc\[1\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT clk (1361:1361:1361) (1378:1378:1378)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -13014,7 +1352,7 @@ (INSTANCE ula_\|video_\|Add0\~4) (DELAY (ABSOLUTE - (PORT datab (377:377:377) (431:431:431)) + (PORT datab (377:377:377) (433:433:433)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -13028,8 +1366,8 @@ (INSTANCE ula_\|video_\|vga_hc\[2\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) - (PORT asdata (607:607:607) (607:607:607)) + (PORT clk (1362:1362:1362) (1378:1378:1378)) + (PORT asdata (804:804:804) (779:779:779)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -13042,37 +1380,27 @@ (INSTANCE ula_\|video_\|Add0\~6) (DELAY (ABSOLUTE - (PORT datab (640:640:640) (667:667:667)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (598:598:598) (617:617:617)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (523:523:523) (522:522:522)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|vga_hc\[3\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) - (PORT d (67:67:67) (78:78:78)) + (PORT clk (1361:1361:1361) (1378:1378:1378)) + (PORT asdata (803:803:803) (785:785:785)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) ) ) (CELL @@ -13080,7 +1408,7 @@ (INSTANCE ula_\|video_\|Add0\~8) (DELAY (ABSOLUTE - (PORT dataa (1015:1015:1015) (1000:1000:1000)) + (PORT dataa (595:595:595) (630:630:630)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -13094,8 +1422,104 @@ (INSTANCE ula_\|video_\|vga_hc\[4\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) - (PORT asdata (607:607:607) (607:607:607)) + (PORT clk (1362:1362:1362) (1378:1378:1378)) + (PORT asdata (812:812:812) (784:784:784)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT datab (763:763:763) (784:784:784)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\~0) + (DELAY + (ABSOLUTE + (PORT datab (183:183:183) (215:215:215)) + (PORT datad (582:582:582) (580:580:580)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1362:1362:1362) (1378:1378:1378)) + (PORT asdata (469:469:469) (496:496:496)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (1271:1271:1271) (1273:1273:1273)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1362:1362:1362) (1378:1378:1378)) + (PORT asdata (603:603:603) (601:601:601)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (645:645:645)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1362:1362:1362) (1378:1378:1378)) + (PORT asdata (1334:1334:1334) (1318:1318:1318)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -13108,10 +1532,10 @@ (INSTANCE ula_\|video_\|Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (1151:1151:1151) (1185:1185:1185)) - (PORT datab (892:892:892) (947:947:947)) - (PORT datac (891:891:891) (943:943:943)) - (PORT datad (258:258:258) (326:326:326)) + (PORT dataa (411:411:411) (488:488:488)) + (PORT datab (895:895:895) (920:920:920)) + (PORT datac (639:639:639) (679:679:679)) + (PORT datad (684:684:684) (712:712:712)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -13124,39 +1548,24 @@ (INSTANCE ula_\|video_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (635:635:635) (653:653:653)) - (PORT datab (1298:1298:1298) (1302:1302:1302)) - (PORT datad (874:874:874) (842:842:842)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (414:414:414) (463:463:463)) - (PORT datab (641:641:641) (668:668:668)) - (PORT datac (600:600:600) (630:630:630)) - (PORT datad (528:528:528) (511:511:511)) + (PORT dataa (1141:1141:1141) (1173:1173:1173)) + (PORT datab (849:849:849) (860:860:860)) + (PORT datac (602:602:602) (629:629:629)) + (PORT datad (160:160:160) (181:181:181)) (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~10) + (INSTANCE ula_\|video_\|Add0\~16) (DELAY (ABSOLUTE - (PORT dataa (633:633:633) (650:650:650)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT dataa (998:998:998) (1009:1009:1009)) + (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) @@ -13166,22 +1575,130 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~0) + (INSTANCE ula_\|video_\|vga_hc\~2) (DELAY (ABSOLUTE - (PORT datac (780:780:780) (780:780:780)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datad (581:581:581) (580:580:580)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[5\]) + (INSTANCE ula_\|video_\|vga_hc\[8\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) + (PORT clk (1362:1362:1362) (1378:1378:1378)) + (PORT asdata (805:805:805) (783:783:783)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datab (241:241:241) (311:311:311)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH cin combout (408:408:408) (387:387:387)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\~1) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (338:338:338)) + (PORT datad (583:583:583) (582:582:582)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1362:1362:1362) (1378:1378:1378)) + (PORT asdata (1321:1321:1321) (1291:1291:1291)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (243:243:243)) + (PORT datab (1155:1155:1155) (1174:1174:1174)) + (PORT datac (827:827:827) (849:849:849)) + (PORT datad (810:810:810) (819:819:819)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1153:1153:1153) (1187:1187:1187)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (662:662:662) (682:682:682)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (630:630:630)) + (PORT datab (1389:1389:1389) (1361:1361:1361)) + (PORT datad (545:545:545) (541:541:541)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1361:1361:1361) (1377:1377:1377)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -13190,82 +1707,14 @@ (HOLD d (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~12) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (608:608:608)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) - (PORT asdata (467:467:467) (493:493:493)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) - (PORT asdata (806:806:806) (780:780:780)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~0) - (DELAY - (ABSOLUTE - (PORT datab (669:669:669) (695:695:695)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~2) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (681:681:681)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~4) (DELAY (ABSOLUTE - (PORT dataa (637:637:637) (664:664:664)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (625:625:625) (654:654:654)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -13277,9 +1726,9 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (452:452:452) (501:501:501)) - (PORT datab (556:556:556) (546:546:546)) - (PORT datad (829:829:829) (818:818:818)) + (PORT dataa (608:608:608) (634:634:634)) + (PORT datab (589:589:589) (597:597:597)) + (PORT datad (1352:1352:1352) (1330:1330:1330)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -13292,7 +1741,7 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1361:1361:1361) (1377:1377:1377)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -13306,9 +1755,9 @@ (INSTANCE ula_\|video_\|Add1\~6) (DELAY (ABSOLUTE - (PORT dataa (660:660:660) (695:695:695)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (646:646:646) (677:677:677)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -13320,13 +1769,12 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (574:574:574) (576:576:576)) - (PORT datab (598:598:598) (610:610:610)) - (PORT datac (626:626:626) (665:665:665)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (606:606:606) (629:629:629)) + (PORT datab (1390:1390:1390) (1360:1360:1360)) + (PORT datad (557:557:557) (544:544:544)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -13336,13 +1784,13 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) - (PORT asdata (1257:1257:1257) (1200:1200:1200)) + (PORT clk (1361:1361:1361) (1377:1377:1377)) + (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) + (HOLD d (posedge clk) (144:144:144)) ) ) (CELL @@ -13350,9 +1798,9 @@ (INSTANCE ula_\|video_\|Add1\~8) (DELAY (ABSOLUTE - (PORT datab (630:630:630) (668:668:668)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (895:895:895) (895:895:895)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -13364,9 +1812,9 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]\~5) (DELAY (ABSOLUTE - (PORT dataa (454:454:454) (503:503:503)) - (PORT datab (581:581:581) (564:564:564)) - (PORT datad (827:827:827) (817:817:817)) + (PORT dataa (604:604:604) (632:632:632)) + (PORT datab (620:620:620) (612:612:612)) + (PORT datad (1349:1349:1349) (1328:1328:1328)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -13379,7 +1827,7 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1361:1361:1361) (1377:1377:1377)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -13393,9 +1841,9 @@ (INSTANCE ula_\|video_\|Add1\~10) (DELAY (ABSOLUTE - (PORT dataa (641:641:641) (684:684:684)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (676:676:676) (721:721:721)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -13407,13 +1855,12 @@ (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) (DELAY (ABSOLUTE - (PORT dataa (574:574:574) (573:573:573)) - (PORT datab (598:598:598) (607:607:607)) - (PORT datac (654:654:654) (677:677:677)) - (PORT datad (160:160:160) (180:180:180)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (610:610:610) (634:634:634)) + (PORT datab (1394:1394:1394) (1364:1364:1364)) + (PORT datad (547:547:547) (534:534:534)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -13423,13 +1870,13 @@ (INSTANCE ula_\|video_\|vga_vc\[5\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) - (PORT asdata (812:812:812) (796:796:796)) + (PORT clk (1361:1361:1361) (1377:1377:1377)) + (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) + (HOLD d (posedge clk) (144:144:144)) ) ) (CELL @@ -13437,9 +1884,9 @@ (INSTANCE ula_\|video_\|Add1\~12) (DELAY (ABSOLUTE - (PORT datab (665:665:665) (689:689:689)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (885:885:885) (901:901:901)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -13451,11 +1898,11 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]\~4) (DELAY (ABSOLUTE - (PORT dataa (453:453:453) (501:501:501)) - (PORT datab (546:546:546) (539:539:539)) - (PORT datad (831:831:831) (812:812:812)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT dataa (632:632:632) (643:643:643)) + (PORT datab (539:539:539) (545:545:545)) + (PORT datad (724:724:724) (689:689:689)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13466,7 +1913,7 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1361:1361:1361) (1377:1377:1377)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -13480,7 +1927,7 @@ (INSTANCE ula_\|video_\|Add1\~14) (DELAY (ABSOLUTE - (PORT datab (641:641:641) (663:663:663)) + (PORT datab (887:887:887) (927:927:927)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -13494,9 +1941,9 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]\~6) (DELAY (ABSOLUTE - (PORT dataa (452:452:452) (500:500:500)) - (PORT datab (1086:1086:1086) (1066:1066:1066)) - (PORT datad (830:830:830) (816:816:816)) + (PORT dataa (630:630:630) (640:640:640)) + (PORT datab (997:997:997) (949:949:949)) + (PORT datad (514:514:514) (509:509:509)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -13509,7 +1956,7 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1361:1361:1361) (1377:1377:1377)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -13523,7 +1970,7 @@ (INSTANCE ula_\|video_\|Add1\~16) (DELAY (ABSOLUTE - (PORT datab (685:685:685) (711:711:711)) + (PORT datab (876:876:876) (903:903:903)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -13537,9 +1984,9 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]\~7) (DELAY (ABSOLUTE - (PORT dataa (454:454:454) (497:497:497)) - (PORT datab (929:929:929) (887:887:887)) - (PORT datad (822:822:822) (812:812:812)) + (PORT dataa (631:631:631) (643:643:643)) + (PORT datab (1042:1042:1042) (1017:1017:1017)) + (PORT datad (514:514:514) (513:513:513)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -13552,7 +1999,7 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1361:1361:1361) (1377:1377:1377)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -13566,7 +2013,7 @@ (INSTANCE ula_\|video_\|Add1\~18) (DELAY (ABSOLUTE - (PORT datad (607:607:607) (634:634:634)) + (PORT datad (594:594:594) (627:627:627)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) ) @@ -13577,11 +2024,11 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]\~9) (DELAY (ABSOLUTE - (PORT dataa (452:452:452) (496:496:496)) - (PORT datab (942:942:942) (906:906:906)) - (PORT datad (827:827:827) (818:818:818)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT dataa (633:633:633) (641:641:641)) + (PORT datab (540:540:540) (542:542:542)) + (PORT datad (727:727:727) (699:699:699)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13592,7 +2039,7 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1361:1361:1361) (1377:1377:1377)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -13603,31 +2050,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal2\~0) + (INSTANCE ula_\|video_\|Equal3\~0) (DELAY (ABSOLUTE - (PORT dataa (247:247:247) (322:322:322)) - (PORT datab (244:244:244) (318:318:318)) - (PORT datac (237:237:237) (307:307:307)) - (PORT datad (221:221:221) (283:283:283)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (257:257:257) (340:340:340)) + (PORT datab (654:654:654) (686:686:686)) + (PORT datac (599:599:599) (628:628:628)) + (PORT datad (1093:1093:1093) (1098:1098:1098)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal3\~0) + (INSTANCE ula_\|video_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (1082:1082:1082) (1131:1131:1131)) - (PORT datab (788:788:788) (823:823:823)) - (PORT datac (589:589:589) (595:595:595)) - (PORT datad (623:623:623) (667:667:667)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (395:395:395) (437:437:437)) + (PORT datab (262:262:262) (334:334:334)) + (PORT datac (226:226:226) (298:298:298)) + (PORT datad (390:390:390) (426:426:426)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13638,13 +2085,13 @@ (INSTANCE ula_\|video_\|Equal3\~1) (DELAY (ABSOLUTE - (PORT dataa (597:597:597) (627:627:627)) - (PORT datab (621:621:621) (651:651:651)) - (PORT datac (530:530:530) (525:525:525)) - (PORT datad (286:286:286) (291:291:291)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (370:370:370) (432:432:432)) + (PORT datab (813:813:813) (810:810:810)) + (PORT datac (576:576:576) (601:601:601)) + (PORT datad (549:549:549) (532:532:532)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -13654,11 +2101,11 @@ (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (454:454:454) (500:500:500)) - (PORT datab (518:518:518) (503:503:503)) - (PORT datad (823:823:823) (811:811:811)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT dataa (605:605:605) (632:632:632)) + (PORT datab (1389:1389:1389) (1363:1363:1363)) + (PORT datad (289:289:289) (297:297:297)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13669,7 +2116,7 @@ (INSTANCE ula_\|video_\|vga_vc\[0\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1361:1361:1361) (1377:1377:1377)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -13680,32 +2127,33 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (INSTANCE ula_\|video_\|Equal2\~1) (DELAY (ABSOLUTE - (PORT dataa (454:454:454) (499:499:499)) - (PORT datab (526:526:526) (522:522:522)) - (PORT datad (821:821:821) (812:812:812)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (385:385:385) (430:430:430)) + (PORT datab (654:654:654) (686:686:686)) + (PORT datac (598:598:598) (626:626:626)) + (PORT datad (345:345:345) (396:396:396)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[1\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal2\~2) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (PORT dataa (326:326:326) (344:344:344)) + (PORT datac (576:576:576) (600:600:600)) + (PORT datad (549:549:549) (533:533:533)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) ) (CELL (CELLTYPE "cycloneive_io_ibuf") @@ -13721,10 +2169,10 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13\~0) (DELAY (ABSOLUTE - (PORT dataa (1332:1332:1332) (1337:1337:1337)) - (PORT datab (659:659:659) (713:713:713)) - (PORT datac (1648:1648:1648) (1616:1616:1616)) - (PORT datad (627:627:627) (644:644:644)) + (PORT dataa (852:852:852) (879:879:879)) + (PORT datab (877:877:877) (888:888:888)) + (PORT datac (834:834:834) (858:858:858)) + (PORT datad (1162:1162:1162) (1116:1116:1116)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -13734,15 +2182,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal79\~0) + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) (DELAY (ABSOLUTE - (PORT dataa (1161:1161:1161) (1205:1205:1205)) - (PORT datab (912:912:912) (925:925:925)) - (PORT datac (1486:1486:1486) (1580:1580:1580)) - (PORT datad (1098:1098:1098) (1166:1166:1166)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT datac (1292:1292:1292) (1293:1293:1293)) + (PORT datad (1770:1770:1770) (1803:1803:1803)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13750,50 +2194,55 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) + (INSTANCE z80_\|execute_\|ctl_mWrite\~4) (DELAY (ABSOLUTE - (PORT dataa (1390:1390:1390) (1431:1431:1431)) - (PORT datab (333:333:333) (349:349:349)) - (PORT datad (607:607:607) (643:643:643)) + (PORT dataa (699:699:699) (750:750:750)) + (PORT datab (1378:1378:1378) (1431:1431:1431)) + (PORT datac (1694:1694:1694) (1775:1775:1775)) + (PORT datad (1560:1560:1560) (1564:1564:1564)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1633:1633:1633) (1686:1686:1686)) + (PORT datad (309:309:309) (317:317:317)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M3_ff\~0) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (428:428:428)) + (PORT datab (641:641:641) (683:683:683)) + (PORT datad (832:832:832) (839:839:839)) (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT dataa (327:327:327) (454:454:454)) - (PORT datab (1869:1869:1869) (1898:1898:1898)) - (PORT datad (251:251:251) (319:319:319)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (1460:1460:1460) (1433:1433:1433)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) + (INSTANCE z80_\|sequencer_\|DFFE_M3_ff) (DELAY (ABSOLUTE - (PORT clk (1358:1358:1358) (1380:1380:1380)) + (PORT clk (1346:1346:1346) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1376:1376:1376) (1354:1354:1354)) + (PORT clrn (1403:1403:1403) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -13804,31 +2253,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~0) + (INSTANCE z80_\|execute_\|ixy_d\~6) (DELAY (ABSOLUTE - (PORT dataa (653:653:653) (684:684:684)) - (PORT datab (242:242:242) (312:312:312)) - (PORT datac (184:184:184) (218:218:218)) - (PORT datad (1342:1342:1342) (1384:1384:1384)) + (PORT dataa (1307:1307:1307) (1397:1397:1397)) + (PORT datad (865:865:865) (926:926:926)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla12M3T3_3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1765:1765:1765) (1763:1763:1763)) + (PORT datab (188:188:188) (225:225:225)) + (PORT datac (582:582:582) (603:603:603)) + (PORT datad (1483:1483:1483) (1572:1572:1572)) (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1188:1188:1188) (1199:1199:1199)) - (PORT datab (242:242:242) (312:312:312)) - (PORT datac (825:825:825) (840:840:840)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13836,411 +2281,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) + (INSTANCE z80_\|pla_decode_\|Equal33\~0) (DELAY (ABSOLUTE - (PORT datab (1328:1328:1328) (1332:1332:1332)) - (PORT datac (1398:1398:1398) (1422:1422:1422)) - (PORT datad (1171:1171:1171) (1211:1211:1211)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|iff1) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1380:1380:1380)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1290:1290:1290) (1255:1255:1255)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1477:1477:1477) (1499:1499:1499)) - (PORT datab (784:784:784) (804:804:804)) - (PORT datac (591:591:591) (619:619:619)) - (PORT datad (398:398:398) (440:440:440)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (531:531:531) (526:526:526)) - (PORT datad (405:405:405) (457:457:457)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) - (DELAY - (ABSOLUTE - (PORT dataa (1091:1091:1091) (1093:1093:1093)) - (PORT datab (582:582:582) (590:590:590)) - (PORT datac (1420:1420:1420) (1485:1485:1485)) - (PORT datad (780:780:780) (777:777:777)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|int_armed) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1364:1364:1364)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|DFFE_inst44) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1375:1375:1375)) - (PORT asdata (1978:1978:1978) (2024:2024:2024)) - (PORT clrn (1413:1413:1413) (1379:1379:1379)) - (PORT ena (1556:1556:1556) (1512:1512:1512)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~38) - (DELAY - (ABSOLUTE - (PORT dataa (324:324:324) (445:445:445)) - (PORT datac (1096:1096:1096) (1138:1138:1138)) - (PORT datad (245:245:245) (311:311:311)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~91) - (DELAY - (ABSOLUTE - (PORT dataa (1544:1544:1544) (1565:1565:1565)) - (PORT datab (1160:1160:1160) (1190:1190:1190)) - (PORT datac (895:895:895) (947:947:947)) - (PORT datad (810:810:810) (791:791:791)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1008:1008:1008) (1008:1008:1008)) - (PORT datab (651:651:651) (683:683:683)) - (PORT datac (1101:1101:1101) (1142:1142:1142)) - (PORT datad (580:580:580) (593:593:593)) + (PORT dataa (1630:1630:1630) (1683:1683:1683)) + (PORT datab (1520:1520:1520) (1605:1605:1605)) + (PORT datad (1740:1740:1740) (1725:1725:1725)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~44) + (INSTANCE z80_\|execute_\|ctl_mRead\~5) (DELAY (ABSOLUTE - (PORT dataa (1011:1011:1011) (1009:1009:1009)) - (PORT datab (847:847:847) (880:880:880)) - (PORT datac (793:793:793) (800:800:800)) - (PORT datad (1020:1020:1020) (981:981:981)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~46) - (DELAY - (ABSOLUTE - (PORT dataa (310:310:310) (332:332:332)) - (PORT datab (654:654:654) (687:687:687)) - (PORT datac (158:158:158) (189:189:189)) - (PORT datad (1024:1024:1024) (986:986:986)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1077:1077:1077) (1102:1102:1102)) - (PORT datab (822:822:822) (841:841:841)) - (PORT datac (987:987:987) (979:979:979)) - (PORT datad (184:184:184) (209:209:209)) + (PORT dataa (1439:1439:1439) (1482:1482:1482)) + (PORT datab (235:235:235) (280:280:280)) + (PORT datac (1345:1345:1345) (1347:1347:1347)) + (PORT datad (1091:1091:1091) (1102:1102:1102)) (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~50) - (DELAY - (ABSOLUTE - (PORT dataa (776:776:776) (772:772:772)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1461:1461:1461) (1534:1534:1534)) - (PORT datad (2107:2107:2107) (2149:2149:2149)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~33) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (249:249:249)) - (PORT datab (1071:1071:1071) (1094:1094:1094)) - (PORT datac (1006:1006:1006) (997:997:997)) - (PORT datad (551:551:551) (559:559:559)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (1554:1554:1554) (1584:1584:1584)) - (PORT datab (576:576:576) (597:597:597)) - (PORT datac (1526:1526:1526) (1554:1554:1554)) - (PORT datad (1081:1081:1081) (1112:1112:1112)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (672:672:672) (721:721:721)) - (PORT datab (626:626:626) (663:663:663)) - (PORT datac (1059:1059:1059) (1071:1071:1071)) - (PORT datad (193:193:193) (224:224:224)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1035:1035:1035) (1028:1028:1028)) - (PORT datab (794:794:794) (779:779:779)) - (PORT datac (1125:1125:1125) (1118:1118:1118)) - (PORT datad (765:765:765) (755:755:755)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1034:1034:1034) (1031:1031:1031)) - (PORT datab (575:575:575) (597:597:597)) - (PORT datac (186:186:186) (226:226:226)) - (PORT datad (1521:1521:1521) (1537:1537:1537)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~34) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (174:174:174) (216:216:216)) - (PORT datad (165:165:165) (189:189:189)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1062:1062:1062) (1079:1079:1079)) - (PORT datab (1294:1294:1294) (1329:1329:1329)) - (PORT datac (2314:2314:2314) (2350:2350:2350)) - (PORT datad (1371:1371:1371) (1420:1420:1420)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~30) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (660:660:660)) - (PORT datab (1059:1059:1059) (1088:1088:1088)) - (PORT datac (334:334:334) (351:351:351)) - (PORT datad (791:791:791) (793:793:793)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1391:1391:1391) (1451:1451:1451)) - (PORT datab (1290:1290:1290) (1325:1325:1325)) - (PORT datac (2318:2318:2318) (2353:2353:2353)) - (PORT datad (980:980:980) (990:990:990)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~35) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (361:361:361)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (574:574:574) (576:576:576)) - (PORT datad (164:164:164) (187:187:187)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1029:1029:1029) (1017:1017:1017)) - (PORT datab (595:595:595) (607:607:607)) - (PORT datac (578:578:578) (566:566:566)) - (PORT datad (1278:1278:1278) (1289:1289:1289)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1920:1920:1920) (1948:1948:1948)) - (PORT datab (847:847:847) (880:880:880)) - (PORT datac (1304:1304:1304) (1325:1325:1325)) - (PORT datad (594:594:594) (621:621:621)) - (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal77\~0) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (753:753:753)) + (PORT datab (696:696:696) (740:740:740)) + (PORT datac (1687:1687:1687) (1770:1770:1770)) + (PORT datad (1552:1552:1552) (1558:1558:1558)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -14248,27 +2327,41 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) + (INSTANCE z80_\|pla_decode_\|Equal50\~0) (DELAY (ABSOLUTE - (PORT dataa (1231:1231:1231) (1280:1280:1280)) - (PORT datab (1626:1626:1626) (1684:1684:1684)) - (PORT datad (587:587:587) (607:607:607)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (1132:1132:1132) (1143:1143:1143)) + (PORT datac (849:849:849) (883:883:883)) + (PORT datad (1092:1092:1092) (1102:1102:1102)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) (DELAY (ABSOLUTE - (PORT dataa (196:196:196) (240:240:240)) - (PORT datab (195:195:195) (236:236:236)) - (PORT datac (621:621:621) (640:640:640)) - (PORT datad (531:531:531) (525:525:525)) + (PORT dataa (597:597:597) (632:632:632)) + (PORT datac (616:616:616) (657:657:657)) + (PORT datad (829:829:829) (838:838:838)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) + (DELAY + (ABSOLUTE + (PORT dataa (1249:1249:1249) (1340:1340:1340)) + (PORT datab (2045:2045:2045) (2160:2160:2160)) + (PORT datac (359:359:359) (399:399:399)) + (PORT datad (282:282:282) (374:374:374)) (IOPATH dataa combout (299:299:299) (304:304:304)) (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -14277,30 +2370,305 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~43) + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) (DELAY (ABSOLUTE - (PORT dataa (1317:1317:1317) (1312:1312:1312)) - (PORT datab (618:618:618) (637:637:637)) - (PORT datac (1836:1836:1836) (1869:1869:1869)) - (PORT datad (1153:1153:1153) (1156:1156:1156)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1408:1408:1408) (1376:1376:1376)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|DFF_inst5\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1092:1092:1092) (1111:1111:1111)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|DFF_inst5) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1366:1366:1366)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1403:1403:1403) (1369:1369:1369)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (306:306:306)) + (PORT datad (1090:1090:1090) (1107:1107:1107)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1366:1366:1366)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1403:1403:1403) (1369:1369:1369)) + (PORT ena (1133:1133:1133) (1118:1118:1118)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) + (DELAY + (ABSOLUTE + (PORT datab (1427:1427:1427) (1447:1447:1447)) + (PORT datac (1090:1090:1090) (1115:1115:1115)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1118:1118:1118) (1116:1116:1116)) + (PORT datab (1128:1128:1128) (1118:1118:1118)) + (PORT datac (2095:2095:2095) (2153:2153:2153)) + (PORT datad (339:339:339) (350:350:350)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) + (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) (DELAY (ABSOLUTE - (PORT dataa (189:189:189) (228:228:228)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (578:578:578) (601:601:601)) - (PORT datad (173:173:173) (201:201:201)) + (PORT dataa (2119:2119:2119) (2152:2152:2152)) + (PORT datab (2016:2016:2016) (2098:2098:2098)) + (PORT datac (1128:1128:1128) (1172:1172:1172)) + (PORT datad (806:806:806) (824:824:824)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_inst4) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1384:1384:1384) (1355:1355:1355)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~3) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (390:390:390)) + (PORT datab (203:203:203) (245:245:245)) + (PORT datac (908:908:908) (952:952:952)) + (PORT datad (1384:1384:1384) (1431:1431:1431)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M4_ff\~0) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (445:445:445)) + (PORT datab (642:642:642) (681:681:681)) + (PORT datad (833:833:833) (842:842:842)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M4_ff) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1366:1366:1366)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1403:1403:1403) (1369:1369:1369)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2292:2292:2292) (2375:2375:2375)) + (PORT datab (1433:1433:1433) (1504:1504:1504)) + (PORT datac (1099:1099:1099) (1134:1134:1134)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2356:2356:2356) (2373:2373:2373)) + (PORT datac (2247:2247:2247) (2354:2354:2354)) + (PORT datad (1693:1693:1693) (1721:1721:1721)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1824:1824:1824) (1826:1826:1826)) + (PORT datab (1946:1946:1946) (1990:1990:1990)) + (PORT datac (1339:1339:1339) (1399:1399:1399)) + (PORT datad (191:191:191) (222:222:222)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~4) + (DELAY + (ABSOLUTE + (PORT datab (2297:2297:2297) (2383:2383:2383)) + (PORT datac (2003:2003:2003) (2031:2031:2031)) + (PORT datad (1353:1353:1353) (1395:1395:1395)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (646:646:646)) + (PORT datac (1308:1308:1308) (1355:1355:1355)) + (PORT datad (610:610:610) (649:649:649)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~5) + (DELAY + (ABSOLUTE + (PORT datac (547:547:547) (578:578:578)) + (PORT datad (613:613:613) (652:652:652)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~2) + (DELAY + (ABSOLUTE + (PORT datab (1097:1097:1097) (1132:1132:1132)) + (PORT datac (1375:1375:1375) (1441:1441:1441)) + (PORT datad (1114:1114:1114) (1136:1136:1136)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~2) + (DELAY + (ABSOLUTE + (PORT datab (1499:1499:1499) (1588:1588:1588)) + (PORT datad (1559:1559:1559) (1583:1583:1583)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~11) + (DELAY + (ABSOLUTE + (PORT dataa (2355:2355:2355) (2370:2370:2370)) + (PORT datab (2281:2281:2281) (2390:2390:2390)) + (PORT datac (1342:1342:1342) (1403:1403:1403)) + (PORT datad (1695:1695:1695) (1725:1725:1725)) (IOPATH dataa combout (307:307:307) (280:280:280)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -14310,311 +2678,295 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) + (INSTANCE z80_\|execute_\|fIOWrite\~2) (DELAY (ABSOLUTE - (PORT dataa (363:363:363) (378:378:378)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (582:582:582) (587:587:587)) - (PORT datad (159:159:159) (181:181:181)) + (PORT dataa (235:235:235) (279:279:279)) + (PORT datab (829:829:829) (810:810:810)) + (PORT datac (1178:1178:1178) (1209:1209:1209)) + (PORT datad (728:728:728) (755:755:755)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT datab (1510:1510:1510) (1637:1637:1637)) + (PORT datad (1662:1662:1662) (1724:1724:1724)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|table_xx\~0) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (444:444:444)) + (PORT datad (223:223:223) (286:286:286)) (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1570:1570:1570) (1603:1603:1603)) + (PORT datab (1046:1046:1046) (1070:1070:1070)) + (PORT datac (828:828:828) (851:851:851)) + (PORT datad (1814:1814:1814) (1833:1833:1833)) + (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~0) + (DELAY + (ABSOLUTE + (PORT datac (949:949:949) (1024:1024:1024)) + (PORT datad (1170:1170:1170) (1214:1214:1214)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (972:972:972)) + (PORT datab (1396:1396:1396) (1397:1397:1397)) + (PORT datac (1003:1003:1003) (979:979:979)) + (PORT datad (183:183:183) (207:207:207)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~3) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (952:952:952)) + (PORT datab (689:689:689) (743:743:743)) + (PORT datac (836:836:836) (869:869:869)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~5) + (DELAY + (ABSOLUTE + (PORT datac (656:656:656) (712:712:712)) + (PORT datad (646:646:646) (699:699:699)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (608:608:608)) + (PORT datab (600:600:600) (602:602:602)) + (PORT datac (314:314:314) (322:322:322)) + (PORT datad (569:569:569) (556:556:556)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (228:228:228)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (1500:1500:1500) (1470:1470:1470)) + (PORT datad (566:566:566) (575:575:575)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (782:782:782) (841:841:841)) + (PORT datab (202:202:202) (236:236:236)) + (PORT datac (977:977:977) (979:979:979)) + (PORT datad (1115:1115:1115) (1189:1189:1189)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~3) + (DELAY + (ABSOLUTE + (PORT datab (682:682:682) (746:746:746)) + (PORT datac (892:892:892) (930:930:930)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT datab (1487:1487:1487) (1576:1576:1576)) + (PORT datad (1712:1712:1712) (1762:1762:1762)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (257:257:257)) + (PORT datab (1262:1262:1262) (1251:1251:1251)) + (PORT datac (1524:1524:1524) (1539:1539:1539)) + (PORT datad (1565:1565:1565) (1587:1587:1587)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~4) + (DELAY + (ABSOLUTE + (PORT datac (608:608:608) (638:638:638)) + (PORT datad (622:622:622) (672:672:672)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~0) + (DELAY + (ABSOLUTE + (PORT datac (949:949:949) (1019:1019:1019)) + (PORT datad (1170:1170:1170) (1216:1216:1216)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1953:1953:1953) (2030:2030:2030)) + (PORT datab (1369:1369:1369) (1339:1339:1339)) + (PORT datac (1030:1030:1030) (1032:1032:1032)) + (PORT datad (590:590:590) (601:601:601)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1052:1052:1052) (1077:1077:1077)) + (PORT datab (836:836:836) (855:855:855)) + (PORT datac (1307:1307:1307) (1293:1293:1293)) + (PORT datad (583:583:583) (606:606:606)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1707:1707:1707) (1766:1766:1766)) + (PORT datab (1506:1506:1506) (1630:1630:1630)) + (PORT datac (1568:1568:1568) (1606:1606:1606)) + (PORT datad (804:804:804) (798:798:798)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) + (DELAY + (ABSOLUTE + (PORT datab (1459:1459:1459) (1528:1528:1528)) + (PORT datac (1628:1628:1628) (1684:1684:1684)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) (DELAY (ABSOLUTE - (PORT dataa (615:615:615) (637:637:637)) - (PORT datab (651:651:651) (684:684:684)) - (PORT datac (584:584:584) (587:587:587)) - (PORT datad (1073:1073:1073) (1095:1095:1095)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1502:1502:1502) (1574:1574:1574)) - (PORT datab (981:981:981) (1037:1037:1037)) - (PORT datac (567:567:567) (581:581:581)) - (PORT datad (902:902:902) (949:949:949)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~39) - (DELAY - (ABSOLUTE - (PORT dataa (195:195:195) (238:238:238)) - (PORT datab (182:182:182) (216:216:216)) - (PORT datac (579:579:579) (567:567:567)) - (PORT datad (526:526:526) (520:520:520)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~47) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (377:377:377)) - (PORT datab (194:194:194) (231:231:231)) - (PORT datac (581:581:581) (601:601:601)) - (PORT datad (179:179:179) (201:201:201)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (240:240:240)) - (PORT datab (199:199:199) (233:233:233)) - (PORT datac (817:817:817) (795:795:795)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) - (DELAY - (ABSOLUTE - (PORT datab (189:189:189) (224:224:224)) - (PORT datac (582:582:582) (603:603:603)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (233:233:233)) - (PORT datab (319:319:319) (333:333:333)) - (PORT datac (584:584:584) (590:590:590)) - (PORT datad (167:167:167) (194:194:194)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (636:636:636)) - (PORT datab (848:848:848) (883:883:883)) - (PORT datac (1100:1100:1100) (1143:1143:1143)) - (PORT datad (171:171:171) (199:199:199)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) - (DELAY - (ABSOLUTE - (PORT dataa (815:815:815) (833:833:833)) - (PORT datab (632:632:632) (662:662:662)) - (PORT datac (893:893:893) (935:935:935)) - (PORT datad (575:575:575) (598:598:598)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (624:624:624) (666:666:666)) - (PORT datac (899:899:899) (931:931:931)) - (PORT datad (1543:1543:1543) (1538:1538:1538)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (231:231:231)) - (PORT datab (312:312:312) (331:331:331)) - (PORT datac (583:583:583) (588:588:588)) - (PORT datad (334:334:334) (333:333:333)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) - (DELAY - (ABSOLUTE - (PORT datab (186:186:186) (221:221:221)) - (PORT datac (162:162:162) (195:195:195)) - (PORT datad (165:165:165) (187:187:187)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~42) - (DELAY - (ABSOLUTE - (PORT datab (603:603:603) (606:606:606)) - (PORT datac (315:315:315) (333:333:333)) - (PORT datad (165:165:165) (189:189:189)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~90) - (DELAY - (ABSOLUTE - (PORT dataa (940:940:940) (985:985:985)) - (PORT datab (1013:1013:1013) (1022:1022:1022)) - (PORT datac (1086:1086:1086) (1108:1108:1108)) - (PORT datad (1371:1371:1371) (1420:1420:1420)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~41) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datab (580:580:580) (599:599:599)) - (PORT datac (186:186:186) (223:223:223)) - (PORT datad (165:165:165) (187:187:187)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) - (DELAY - (ABSOLUTE - (PORT dataa (325:325:325) (453:453:453)) - (PORT datab (841:841:841) (855:855:855)) - (PORT datac (1095:1095:1095) (1138:1138:1138)) - (PORT datad (249:249:249) (317:317:317)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) - (DELAY - (ABSOLUTE - (PORT dataa (1034:1034:1034) (1029:1029:1029)) - (PORT datab (205:205:205) (243:243:243)) - (PORT datac (175:175:175) (220:220:220)) - (PORT datad (804:804:804) (807:807:807)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) - (DELAY - (ABSOLUTE - (PORT dataa (1338:1338:1338) (1364:1364:1364)) - (PORT datab (179:179:179) (212:212:212)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (1522:1522:1522) (1538:1538:1538)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) - (DELAY - (ABSOLUTE - (PORT dataa (1034:1034:1034) (1029:1029:1029)) - (PORT datab (212:212:212) (249:249:249)) - (PORT datac (175:175:175) (219:219:219)) - (PORT datad (550:550:550) (559:559:559)) + (PORT dataa (1315:1315:1315) (1332:1332:1332)) + (PORT datab (1393:1393:1393) (1407:1407:1407)) + (PORT datac (1141:1141:1141) (1158:1158:1158)) + (PORT datad (1120:1120:1120) (1128:1128:1128)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -14622,335 +2974,354 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) - (DELAY - (ABSOLUTE - (PORT dataa (812:812:812) (790:790:790)) - (PORT datab (1045:1045:1045) (1051:1051:1051)) - (PORT datac (319:319:319) (335:335:335)) - (PORT datad (796:796:796) (792:792:792)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) - (DELAY - (ABSOLUTE - (PORT dataa (1065:1065:1065) (1069:1069:1069)) - (PORT datab (349:349:349) (358:358:358)) - (PORT datac (290:290:290) (293:293:293)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (308:308:308) (313:313:313)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (636:636:636)) - (PORT datab (384:384:384) (391:391:391)) - (PORT datac (1039:1039:1039) (1029:1029:1029)) - (PORT datad (795:795:795) (794:794:794)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (641:641:641)) - (PORT datab (870:870:870) (898:898:898)) - (PORT datac (1048:1048:1048) (1038:1038:1038)) - (PORT datad (1587:1587:1587) (1611:1611:1611)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (355:355:355)) - (PORT datab (1054:1054:1054) (1048:1048:1048)) - (PORT datac (972:972:972) (945:945:945)) - (PORT datad (1110:1110:1110) (1100:1100:1100)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (639:639:639)) - (PORT datab (843:843:843) (842:842:842)) - (PORT datac (842:842:842) (866:866:866)) - (PORT datad (294:294:294) (292:292:292)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) - (DELAY - (ABSOLUTE - (PORT dataa (842:842:842) (884:884:884)) - (PORT datab (831:831:831) (839:839:839)) - (PORT datac (1318:1318:1318) (1302:1302:1302)) - (PORT datad (794:794:794) (793:793:793)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1346:1346:1346) (1338:1338:1338)) - (PORT datab (841:841:841) (888:888:888)) - (PORT datac (300:300:300) (317:317:317)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) - (DELAY - (ABSOLUTE - (PORT dataa (205:205:205) (251:251:251)) - (PORT datab (183:183:183) (217:217:217)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (548:548:548) (534:534:534)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) - (DELAY - (ABSOLUTE - (PORT dataa (1097:1097:1097) (1113:1113:1113)) - (PORT datab (1059:1059:1059) (1091:1091:1091)) - (PORT datac (334:334:334) (354:354:354)) - (PORT datad (1059:1059:1059) (1083:1083:1083)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) - (DELAY - (ABSOLUTE - (PORT dataa (1029:1029:1029) (1030:1030:1030)) - (PORT datab (1064:1064:1064) (1084:1084:1084)) - (PORT datad (178:178:178) (199:199:199)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) - (DELAY - (ABSOLUTE - (PORT dataa (882:882:882) (905:905:905)) - (PORT datab (843:843:843) (841:841:841)) - (PORT datac (591:591:591) (607:607:607)) - (PORT datad (1424:1424:1424) (1478:1478:1478)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) - (DELAY - (ABSOLUTE - (PORT dataa (418:418:418) (445:445:445)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datac (753:753:753) (732:732:732)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~89) - (DELAY - (ABSOLUTE - (PORT dataa (1230:1230:1230) (1279:1279:1279)) - (PORT datab (1072:1072:1072) (1037:1037:1037)) - (PORT datac (1318:1318:1318) (1311:1311:1311)) - (PORT datad (785:785:785) (799:799:799)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (228:228:228)) - (PORT datab (775:775:775) (761:761:761)) - (PORT datac (295:295:295) (301:301:301)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) - (DELAY - (ABSOLUTE - (PORT dataa (836:836:836) (835:835:835)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (549:549:549) (539:539:539)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) - (DELAY - (ABSOLUTE - (PORT dataa (1064:1064:1064) (1070:1070:1070)) - (PORT datab (199:199:199) (231:231:231)) - (PORT datac (517:517:517) (505:505:505)) - (PORT datad (522:522:522) (514:514:514)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) (DELAY (ABSOLUTE - (PORT dataa (1017:1017:1017) (1017:1017:1017)) - (PORT datab (191:191:191) (231:231:231)) - (PORT datac (989:989:989) (981:981:981)) - (PORT datad (171:171:171) (202:202:202)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (190:190:190) (231:231:231)) + (PORT datab (1043:1043:1043) (1047:1047:1047)) + (PORT datac (1572:1572:1572) (1553:1553:1553)) + (PORT datad (917:917:917) (925:925:925)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) + (INSTANCE z80_\|pla_decode_\|Equal19\~0) (DELAY (ABSOLUTE - (PORT dataa (1491:1491:1491) (1562:1562:1562)) - (PORT datab (813:813:813) (800:800:800)) - (PORT datac (2318:2318:2318) (2351:2351:2351)) - (PORT datad (1368:1368:1368) (1417:1417:1417)) - (IOPATH dataa combout (273:273:273) (269:269:269)) + (PORT dataa (829:829:829) (830:830:830)) + (PORT datab (627:627:627) (634:634:634)) + (PORT datac (1906:1906:1906) (1985:1985:1985)) + (PORT datad (841:841:841) (848:848:848)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal34\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1569:1569:1569) (1598:1598:1598)) + (PORT datab (226:226:226) (271:271:271)) + (PORT datac (830:830:830) (850:850:850)) + (PORT datad (857:857:857) (879:879:879)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~0) + (DELAY + (ABSOLUTE + (PORT datab (1512:1512:1512) (1637:1637:1637)) + (PORT datad (1661:1661:1661) (1720:1720:1720)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1571:1571:1571) (1603:1603:1603)) + (PORT datab (227:227:227) (268:268:268)) + (PORT datac (829:829:829) (848:848:848)) + (PORT datad (1065:1065:1065) (1076:1076:1076)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1547:1547:1547) (1563:1563:1563)) + (PORT datab (1278:1278:1278) (1257:1257:1257)) + (PORT datac (2333:2333:2333) (2289:2289:2289)) + (PORT datad (1039:1039:1039) (1045:1045:1045)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (838:838:838)) + (PORT datab (188:188:188) (223:223:223)) + (PORT datac (1032:1032:1032) (1056:1056:1056)) + (PORT datad (887:887:887) (933:933:933)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|M5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (451:451:451)) + (PORT datab (640:640:640) (686:686:686)) + (PORT datad (826:826:826) (841:841:841)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|M5) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1366:1366:1366)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1403:1403:1403) (1369:1369:1369)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (950:950:950)) + (PORT datac (615:615:615) (680:680:680)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (2105:2105:2105) (2203:2203:2203)) + (PORT datad (1155:1155:1155) (1194:1194:1194)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (605:605:605)) + (PORT datab (1279:1279:1279) (1256:1256:1256)) + (PORT datac (1522:1522:1522) (1535:1535:1535)) + (PORT datad (826:826:826) (855:855:855)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (835:835:835)) + (PORT datab (324:324:324) (336:336:336)) + (PORT datac (572:572:572) (573:573:573)) + (PORT datad (184:184:184) (210:210:210)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1221:1221:1221) (1269:1269:1269)) + (PORT datab (899:899:899) (885:885:885)) + (PORT datac (1284:1284:1284) (1392:1392:1392)) + (PORT datad (1099:1099:1099) (1093:1093:1093)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~5) + (DELAY + (ABSOLUTE + (PORT datab (237:237:237) (306:306:306)) + (PORT datac (211:211:211) (278:278:278)) + (PORT datad (357:357:357) (411:411:411)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (422:422:422) (448:448:448)) + (PORT datab (1552:1552:1552) (1570:1570:1570)) + (PORT datac (1688:1688:1688) (1768:1768:1768)) + (PORT datad (720:720:720) (761:761:761)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (422:422:422) (448:448:448)) + (PORT datab (1553:1553:1553) (1570:1570:1570)) + (PORT datac (1689:1689:1689) (1768:1768:1768)) + (PORT datad (721:721:721) (759:759:759)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (425:425:425) (449:449:449)) + (PORT datab (1556:1556:1556) (1572:1572:1572)) + (PORT datac (1697:1697:1697) (1777:1777:1777)) + (PORT datad (728:728:728) (764:764:764)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1341:1341:1341) (1325:1325:1325)) + (PORT datab (593:593:593) (609:609:609)) + (PORT datac (605:605:605) (616:616:616)) + (PORT datad (604:604:604) (612:612:612)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~97) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (670:670:670)) + (PORT datab (1300:1300:1300) (1357:1357:1357)) + (PORT datac (1266:1266:1266) (1321:1321:1321)) + (PORT datad (620:620:620) (667:667:667)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~96) + (DELAY + (ABSOLUTE + (PORT dataa (1092:1092:1092) (1114:1114:1114)) + (PORT datab (890:890:890) (899:899:899)) + (PORT datac (616:616:616) (683:683:683)) + (PORT datad (642:642:642) (697:697:697)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~98) + (DELAY + (ABSOLUTE + (PORT dataa (1290:1290:1290) (1273:1273:1273)) + (PORT datab (1068:1068:1068) (1100:1100:1100)) + (PORT datac (615:615:615) (683:683:683)) + (PORT datad (642:642:642) (697:697:697)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) (DELAY (ABSOLUTE - (PORT dataa (557:557:557) (543:543:543)) - (PORT datab (546:546:546) (527:527:527)) + (PORT dataa (2307:2307:2307) (2328:2328:2328)) + (PORT datab (218:218:218) (250:250:250)) (PORT datac (156:156:156) (186:186:186)) - (PORT datad (1045:1045:1045) (1037:1037:1037)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT datad (1589:1589:1589) (1515:1515:1515)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -14958,687 +3329,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~40) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) (DELAY (ABSOLUTE - (PORT datab (603:603:603) (606:606:606)) - (PORT datac (317:317:317) (331:331:331)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (251:251:251)) - (PORT datab (193:193:193) (234:234:234)) - (PORT datac (986:986:986) (981:981:981)) - (PORT datad (1053:1053:1053) (1063:1063:1063)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (794:794:794) (846:846:846)) + (PORT datab (325:325:325) (336:336:336)) + (PORT datad (316:316:316) (321:321:321)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) + (INSTANCE z80_\|execute_\|fMWrite\~1) (DELAY (ABSOLUTE - (PORT dataa (1067:1067:1067) (1075:1075:1075)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (511:511:511) (508:508:508)) - (PORT datad (370:370:370) (382:382:382)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (153:153:153) (183:183:183)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) - (DELAY - (ABSOLUTE - (PORT dataa (1047:1047:1047) (1031:1031:1031)) - (PORT datab (1034:1034:1034) (999:999:999)) - (PORT datac (993:993:993) (991:991:991)) - (PORT datad (1086:1086:1086) (1100:1100:1100)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) - (DELAY - (ABSOLUTE - (PORT datac (646:646:646) (694:694:694)) - (PORT datad (338:338:338) (349:349:349)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (882:882:882) (898:898:898)) - (PORT datac (626:626:626) (663:663:663)) - (PORT datad (314:314:314) (326:326:326)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[0\]) - (DELAY - (ABSOLUTE - (PORT datac (934:934:934) (903:903:903)) - (PORT datad (852:852:852) (845:845:845)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (164:164:164) (187:187:187)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1370:1370:1370)) - (PORT ena (1924:1924:1924) (1928:1928:1928)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) - (DELAY - (ABSOLUTE - (PORT dataa (1071:1071:1071) (1059:1059:1059)) - (PORT datab (920:920:920) (926:926:926)) - (PORT datac (642:642:642) (688:688:688)) - (PORT datad (183:183:183) (207:207:207)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1384:1384:1384)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1175:1175:1175) (1170:1170:1170)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) - (PORT asdata (899:899:899) (920:920:920)) - (PORT ena (1105:1105:1105) (1078:1078:1078)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (354:354:354)) - (PORT datab (642:642:642) (662:662:662)) - (PORT datad (1099:1099:1099) (1119:1119:1119)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (679:679:679) (706:706:706)) - (PORT datac (197:197:197) (264:264:264)) - (PORT datad (568:568:568) (585:585:585)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (805:805:805)) - (PORT datab (376:376:376) (384:384:384)) - (PORT datac (175:175:175) (207:207:207)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (883:883:883) (896:896:896)) - (PORT datac (627:627:627) (664:664:664)) - (PORT datad (315:315:315) (324:324:324)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[1\]) - (DELAY - (ABSOLUTE - (PORT datab (370:370:370) (379:379:379)) - (PORT datad (322:322:322) (329:329:329)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1384:1384:1384)) - (PORT asdata (485:485:485) (512:512:512)) - (PORT clrn (1409:1409:1409) (1380:1380:1380)) - (PORT ena (1969:1969:1969) (1997:1997:1997)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~4) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (948:948:948)) - (PORT datab (1064:1064:1064) (1061:1061:1061)) - (PORT datac (753:753:753) (774:774:774)) - (PORT datad (331:331:331) (342:342:342)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (392:392:392)) - (PORT datab (200:200:200) (233:233:233)) - (PORT datac (214:214:214) (279:279:279)) - (PORT datad (307:307:307) (308:308:308)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (692:692:692)) - (PORT datab (885:885:885) (898:898:898)) - (PORT datac (579:579:579) (599:599:599)) - (PORT datad (491:491:491) (483:483:483)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (516:516:516) (518:518:518)) - (PORT datad (192:192:192) (224:224:224)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (178:178:178) (199:199:199)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1384:1384:1384)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1409:1409:1409) (1380:1380:1380)) - (PORT ena (1976:1976:1976) (1995:1995:1995)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (379:379:379)) - (PORT datab (1064:1064:1064) (1065:1065:1065)) - (PORT datac (891:891:891) (917:917:917)) - (PORT datad (368:368:368) (400:400:400)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (236:236:236)) - (PORT datab (186:186:186) (223:223:223)) - (PORT datac (160:160:160) (192:192:192)) - (PORT datad (164:164:164) (187:187:187)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (389:389:389)) - (PORT datab (1032:1032:1032) (997:997:997)) - (PORT datac (998:998:998) (976:976:976)) - (PORT datad (1091:1091:1091) (1105:1105:1105)) + (PORT dataa (1508:1508:1508) (1562:1562:1562)) + (PORT datab (1430:1430:1430) (1500:1500:1500)) + (PORT datac (1542:1542:1542) (1567:1567:1567)) + (PORT datad (1606:1606:1606) (1669:1669:1669)) (IOPATH dataa combout (307:307:307) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1068:1068:1068) (1057:1057:1057)) - (PORT datab (915:915:915) (924:924:924)) - (PORT datac (886:886:886) (910:910:910)) - (PORT datad (1039:1039:1039) (1026:1026:1026)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (807:807:807)) - (PORT datab (1284:1284:1284) (1227:1227:1227)) - (PORT datac (641:641:641) (688:688:688)) - (PORT datad (342:342:342) (353:353:353)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) - (DELAY - (ABSOLUTE - (PORT datab (186:186:186) (223:223:223)) - (PORT datac (307:307:307) (317:317:317)) - (PORT datad (222:222:222) (282:282:282)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1283:1283:1283) (1264:1264:1264)) - (PORT ena (746:746:746) (759:759:759)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1285:1285:1285) (1265:1265:1265)) - (PORT ena (1154:1154:1154) (1142:1142:1142)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (389:389:389) (434:434:434)) - (PORT datab (546:546:546) (555:555:555)) - (PORT datad (200:200:200) (257:257:257)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (755:755:755) (755:755:755)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1295:1295:1295) (1246:1246:1246)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1067:1067:1067) (1060:1060:1060)) - (PORT ena (1155:1155:1155) (1140:1140:1140)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (578:578:578) (596:596:596)) - (PORT datab (774:774:774) (774:774:774)) - (PORT datad (589:589:589) (599:599:599)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1104:1104:1104) (1099:1099:1099)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1103:1103:1103) (1102:1102:1102)) - (PORT ena (1123:1123:1123) (1106:1106:1106)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (646:646:646)) - (PORT datab (223:223:223) (293:293:293)) - (PORT datad (347:347:347) (360:360:360)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (753:753:753) (752:752:752)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1381:1381:1381) (1365:1365:1365)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1070:1070:1070) (1064:1064:1064)) - (PORT ena (1109:1109:1109) (1074:1074:1074)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (869:869:869) (865:865:865)) - (PORT datab (565:565:565) (561:561:561)) - (PORT datac (513:513:513) (507:507:507)) - (PORT datad (1405:1405:1405) (1456:1456:1456)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (908:908:908)) - (PORT datab (536:536:536) (546:546:546)) - (PORT datac (918:918:918) (935:935:935)) - (PORT datad (794:794:794) (808:808:808)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -15646,1335 +3359,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~43) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (238:238:238)) - (PORT datab (619:619:619) (648:648:648)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (156:156:156) (177:177:177)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (503:503:503) (496:496:496)) - (PORT datab (572:572:572) (561:561:561)) - (PORT datac (790:790:790) (807:807:807)) - (PORT datad (567:567:567) (574:574:574)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (580:580:580) (606:606:606)) - (PORT datab (600:600:600) (612:612:612)) - (PORT datac (1070:1070:1070) (1099:1099:1099)) - (PORT datad (550:550:550) (550:550:550)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (231:231:231)) - (PORT datab (181:181:181) (215:215:215)) - (PORT datac (566:566:566) (567:567:567)) - (PORT datad (167:167:167) (190:190:190)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) - (DELAY - (ABSOLUTE - (PORT datab (1320:1320:1320) (1344:1344:1344)) - (PORT datac (1116:1116:1116) (1136:1136:1136)) - (PORT datad (788:788:788) (810:810:810)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT datab (1320:1320:1320) (1346:1346:1346)) - (PORT datac (1120:1120:1120) (1139:1139:1139)) - (PORT datad (785:785:785) (795:795:795)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) - (DELAY - (ABSOLUTE - (PORT datab (1321:1321:1321) (1338:1338:1338)) - (PORT datac (1109:1109:1109) (1129:1129:1129)) - (PORT datad (785:785:785) (793:793:793)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (933:933:933) (955:955:955)) - (PORT ena (906:906:906) (905:905:905)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) - (DELAY - (ABSOLUTE - (PORT datab (1321:1321:1321) (1339:1339:1339)) - (PORT datac (1111:1111:1111) (1130:1130:1130)) - (PORT datad (790:790:790) (811:811:811)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (936:936:936) (957:957:957)) - (PORT ena (893:893:893) (877:877:877)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (425:425:425) (472:472:472)) - (PORT datab (450:450:450) (480:480:480)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) - (DELAY - (ABSOLUTE - (PORT datab (1320:1320:1320) (1340:1340:1340)) - (PORT datac (1115:1115:1115) (1134:1134:1134)) - (PORT datad (999:999:999) (984:984:984)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) - (DELAY - (ABSOLUTE - (PORT datab (1320:1320:1320) (1346:1346:1346)) - (PORT datac (1120:1120:1120) (1139:1139:1139)) - (PORT datad (916:916:916) (925:925:925)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1093:1093:1093) (1077:1077:1077)) - (PORT ena (1281:1281:1281) (1292:1292:1292)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) - (DELAY - (ABSOLUTE - (PORT datab (1321:1321:1321) (1342:1342:1342)) - (PORT datac (1119:1119:1119) (1139:1139:1139)) - (PORT datad (1001:1001:1001) (985:985:985)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1095:1095:1095) (1080:1080:1080)) - (PORT ena (1271:1271:1271) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) - (DELAY - (ABSOLUTE - (PORT datab (1323:1323:1323) (1343:1343:1343)) - (PORT datac (1122:1122:1122) (1141:1141:1141)) - (PORT datad (914:914:914) (922:922:922)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (831:831:831) (892:892:892)) - (PORT datab (221:221:221) (290:290:290)) - (PORT datad (799:799:799) (856:856:856)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) - (DELAY - (ABSOLUTE - (PORT datab (1114:1114:1114) (1152:1152:1152)) - (PORT datac (829:829:829) (849:849:849)) - (PORT datad (833:833:833) (842:842:842)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1119:1119:1119) (1113:1113:1113)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (869:869:869) (898:898:898)) - (PORT datab (1114:1114:1114) (1148:1148:1148)) - (PORT datad (821:821:821) (832:832:832)) + (PORT dataa (1068:1068:1068) (1062:1062:1062)) + (PORT datab (1383:1383:1383) (1397:1397:1397)) + (PORT datad (159:159:159) (181:181:181)) (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1080:1080:1080) (1087:1087:1087)) - (PORT datab (186:186:186) (222:222:222)) - (PORT datac (1680:1680:1680) (1729:1729:1729)) - (PORT datad (181:181:181) (218:218:218)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) - (DELAY - (ABSOLUTE - (PORT dataa (816:816:816) (809:809:809)) - (PORT datab (187:187:187) (223:223:223)) - (PORT datac (561:561:561) (588:588:588)) - (PORT datad (806:806:806) (810:810:810)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) - (DELAY - (ABSOLUTE - (PORT dataa (1359:1359:1359) (1373:1373:1373)) - (PORT datac (773:773:773) (748:748:748)) - (PORT datad (1042:1042:1042) (1034:1034:1034)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (906:906:906) (925:925:925)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) - (DELAY - (ABSOLUTE - (PORT dataa (1361:1361:1361) (1373:1373:1373)) - (PORT datac (774:774:774) (748:748:748)) - (PORT datad (1045:1045:1045) (1035:1035:1035)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1007:1007:1007) (991:991:991)) - (PORT datab (1073:1073:1073) (1081:1081:1081)) - (PORT datad (219:219:219) (252:252:252)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (614:614:614) (637:637:637)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) - (DELAY - (ABSOLUTE - (PORT datab (1043:1043:1043) (1038:1038:1038)) - (PORT datac (1294:1294:1294) (1292:1292:1292)) - (PORT datad (762:762:762) (769:769:769)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (888:888:888)) - (PORT datab (1113:1113:1113) (1147:1147:1147)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (406:406:406)) - (PORT datab (876:876:876) (897:897:897)) - (PORT datac (1060:1060:1060) (1056:1056:1056)) - (PORT datad (615:615:615) (618:618:618)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) - (DELAY - (ABSOLUTE - (PORT datac (1323:1323:1323) (1335:1335:1335)) - (PORT datad (1042:1042:1042) (1031:1031:1031)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1091:1091:1091) (1108:1108:1108)) - (PORT datab (755:755:755) (739:739:739)) - (PORT datac (1047:1047:1047) (1044:1044:1044)) - (PORT datad (615:615:615) (635:635:635)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1390:1390:1390) (1376:1376:1376)) - (PORT ena (1039:1039:1039) (993:993:993)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) - (DELAY - (ABSOLUTE - (PORT datab (1043:1043:1043) (1039:1039:1039)) - (PORT datac (1294:1294:1294) (1292:1292:1292)) - (PORT datad (762:762:762) (766:766:766)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (405:405:405)) - (PORT datab (813:813:813) (838:838:838)) - (PORT datad (339:339:339) (352:352:352)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) - (DELAY - (ABSOLUTE - (PORT dataa (381:381:381) (416:416:416)) - (PORT datab (1312:1312:1312) (1291:1291:1291)) - (PORT datac (1056:1056:1056) (1048:1048:1048)) - (PORT datad (612:612:612) (615:615:615)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1067:1067:1067) (1076:1076:1076)) - (PORT datab (757:757:757) (741:741:741)) - (PORT datac (1055:1055:1055) (1050:1050:1050)) - (PORT datad (622:622:622) (644:644:644)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1347:1347:1347) (1329:1329:1329)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1646:1646:1646) (1716:1716:1716)) - (PORT datab (893:893:893) (908:908:908)) - (PORT datac (1355:1355:1355) (1341:1341:1341)) - (PORT datad (1815:1815:1815) (1812:1812:1812)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (586:586:586) (588:588:588)) - (PORT datab (1157:1157:1157) (1140:1140:1140)) - (PORT datac (1681:1681:1681) (1734:1734:1734)) - (PORT datad (1026:1026:1026) (1018:1018:1018)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (625:625:625)) - (PORT datab (846:846:846) (872:872:872)) - (PORT datac (804:804:804) (801:801:801)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (232:232:232)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (1071:1071:1071) (1070:1070:1070)) - (PORT datad (183:183:183) (218:218:218)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (686:686:686)) - (PORT datab (188:188:188) (221:221:221)) - (PORT datac (322:322:322) (336:336:336)) - (PORT datad (1066:1066:1066) (1059:1059:1059)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) - (DELAY - (ABSOLUTE - (PORT datab (856:856:856) (854:854:854)) - (PORT datac (552:552:552) (546:546:546)) - (PORT datad (166:166:166) (192:192:192)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (813:813:813)) - (PORT datac (1053:1053:1053) (1034:1034:1034)) - (PORT datad (775:775:775) (763:763:763)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1392:1392:1392) (1376:1376:1376)) - (PORT ena (1164:1164:1164) (1167:1167:1167)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) - (DELAY - (ABSOLUTE - (PORT dataa (819:819:819) (811:811:811)) - (PORT datac (1047:1047:1047) (1033:1033:1033)) - (PORT datad (777:777:777) (763:763:763)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1019:1019:1019) (1011:1011:1011)) - (PORT datab (1187:1187:1187) (1245:1245:1245)) - (PORT datad (776:776:776) (789:789:789)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) - (DELAY - (ABSOLUTE - (PORT dataa (588:588:588) (614:614:614)) - (PORT datab (1170:1170:1170) (1220:1220:1220)) - (PORT datac (1060:1060:1060) (1052:1052:1052)) - (PORT datad (350:350:350) (371:371:371)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (912:912:912) (931:931:931)) - (PORT ena (1093:1093:1093) (1070:1070:1070)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) - (DELAY - (ABSOLUTE - (PORT dataa (377:377:377) (411:411:411)) - (PORT datab (1170:1170:1170) (1212:1212:1212)) - (PORT datac (1055:1055:1055) (1054:1054:1054)) - (PORT datad (612:612:612) (618:618:618)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (616:616:616)) - (PORT datab (1166:1166:1166) (1211:1211:1211)) - (PORT datac (1057:1057:1057) (1053:1053:1053)) - (PORT datad (356:356:356) (372:372:372)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (912:912:912) (931:931:931)) - (PORT ena (1173:1173:1173) (1169:1169:1169)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (409:409:409)) - (PORT datab (1169:1169:1169) (1219:1219:1219)) - (PORT datac (1060:1060:1060) (1052:1052:1052)) - (PORT datad (615:615:615) (614:614:614)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (429:429:429)) - (PORT datab (1479:1479:1479) (1478:1478:1478)) - (PORT datad (1098:1098:1098) (1089:1089:1089)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (563:563:563) (566:566:566)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (730:730:730) (696:696:696)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (573:573:573) (583:583:583)) - (PORT datab (312:312:312) (332:332:332)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (578:578:578) (588:588:588)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (882:882:882)) - (PORT datab (199:199:199) (232:232:232)) - (PORT datac (572:572:572) (586:586:586)) - (PORT datad (728:728:728) (697:697:697)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (987:987:987) (1001:1001:1001)) - (PORT datab (778:778:778) (771:771:771)) - (PORT datac (192:192:192) (237:237:237)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (606:606:606)) - (PORT datab (777:777:777) (776:776:776)) - (PORT datac (158:158:158) (189:189:189)) - (PORT datad (811:811:811) (817:817:817)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datac (176:176:176) (208:208:208)) - (PORT datad (178:178:178) (201:201:201)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1448:1448:1448) (1385:1385:1385)) - (PORT datab (782:782:782) (820:820:820)) - (PORT datac (1049:1049:1049) (1030:1030:1030)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) - (DELAY - (ABSOLUTE - (PORT dataa (1211:1211:1211) (1259:1259:1259)) - (PORT datac (1051:1051:1051) (1039:1039:1039)) - (PORT datad (774:774:774) (762:762:762)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1196:1196:1196) (1178:1178:1178)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1080:1080:1080) (1105:1105:1105)) - (PORT ena (906:906:906) (905:905:905)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1079:1079:1079) (1103:1103:1103)) - (PORT ena (893:893:893) (877:877:877)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (425:425:425) (478:478:478)) - (PORT datab (451:451:451) (487:487:487)) - (PORT datad (197:197:197) (254:254:254)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1792:1792:1792) (1799:1799:1799)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (892:892:892)) - (PORT datab (1114:1114:1114) (1155:1155:1155)) - (PORT datad (821:821:821) (832:832:832)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT asdata (493:493:493) (524:524:524)) - (PORT ena (1347:1347:1347) (1329:1329:1329)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1574:1574:1574) (1581:1581:1581)) - (PORT ena (1164:1164:1164) (1167:1167:1167)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1018:1018:1018) (1013:1013:1013)) - (PORT datab (603:603:603) (645:645:645)) - (PORT datad (779:779:779) (797:797:797)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (2031:2031:2031) (2021:2021:2021)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (787:787:787) (778:778:778)) - (PORT datab (1073:1073:1073) (1082:1082:1082)) - (PORT datad (219:219:219) (253:253:253)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1819:1819:1819) (1793:1793:1793)) - (PORT ena (1093:1093:1093) (1070:1070:1070)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1820:1820:1820) (1797:1797:1797)) - (PORT ena (1173:1173:1173) (1169:1169:1169)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (414:414:414)) - (PORT datab (1473:1473:1473) (1469:1469:1469)) - (PORT datad (1097:1097:1097) (1083:1083:1083)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1573:1573:1573) (1580:1580:1580)) - (PORT ena (1039:1039:1039) (993:993:993)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1482:1482:1482) (1473:1473:1473)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (391:391:391)) - (PORT datab (812:812:812) (837:837:837)) - (PORT datad (800:800:800) (823:823:823)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) (DELAY (ABSOLUTE (PORT dataa (182:182:182) (217:217:217)) - (PORT datab (591:591:591) (579:579:579)) - (PORT datac (311:311:311) (318:318:318)) - (PORT datad (158:158:158) (180:180:180)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (2181:2181:2181) (2175:2175:2175)) - (PORT ena (1271:1271:1271) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (2180:2180:2180) (2174:2174:2174)) - (PORT ena (1281:1281:1281) (1292:1292:1292)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (829:829:829) (889:889:889)) - (PORT datab (826:826:826) (890:890:890)) - (PORT datad (198:198:198) (254:254:254)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (602:602:602)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (559:559:559) (557:557:557)) - (PORT datad (296:296:296) (289:289:289)) + (PORT datab (723:723:723) (755:755:755)) + (PORT datac (908:908:908) (930:930:930)) + (PORT datad (158:158:158) (179:179:179)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -16984,29 +3389,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) + (INSTANCE z80_\|execute_\|ctl_mRead\~6) (DELAY (ABSOLUTE - (PORT dataa (814:814:814) (859:859:859)) - (PORT datab (507:507:507) (508:508:508)) - (PORT datac (969:969:969) (991:991:991)) - (PORT datad (1211:1211:1211) (1199:1199:1199)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) - (DELAY - (ABSOLUTE - (PORT dataa (799:799:799) (807:807:807)) - (PORT datac (1048:1048:1048) (1033:1033:1033)) - (PORT datad (786:786:786) (789:789:789)) + (PORT dataa (1660:1660:1660) (1705:1705:1705)) + (PORT datab (984:984:984) (1027:1027:1027)) + (PORT datac (1577:1577:1577) (1613:1613:1613)) + (PORT datad (198:198:198) (233:233:233)) (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -17014,1487 +3405,75 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) (DELAY (ABSOLUTE - (PORT dataa (798:798:798) (805:805:805)) - (PORT datac (1051:1051:1051) (1036:1036:1036)) - (PORT datad (787:787:787) (792:792:792)) + (PORT dataa (1254:1254:1254) (1318:1318:1318)) + (PORT datad (1839:1839:1839) (1872:1872:1872)) (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT asdata (1278:1278:1278) (1296:1296:1296)) - (PORT ena (857:857:857) (835:835:835)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1093:1093:1093) (1067:1067:1067)) - (PORT datab (777:777:777) (766:766:766)) - (PORT datac (1052:1052:1052) (1034:1034:1034)) - (PORT datad (787:787:787) (789:789:789)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (248:248:248)) - (PORT datab (376:376:376) (397:397:397)) - (PORT datad (358:358:358) (374:374:374)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) - (DELAY - (ABSOLUTE - (PORT dataa (1211:1211:1211) (1258:1258:1258)) - (PORT datac (1051:1051:1051) (1036:1036:1036)) - (PORT datad (774:774:774) (762:762:762)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (295:295:295)) - (PORT datac (702:702:702) (733:733:733)) - (PORT datad (596:596:596) (596:596:596)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (265:265:265)) - (PORT datab (212:212:212) (250:250:250)) - (PORT datac (1025:1025:1025) (991:991:991)) - (PORT datad (194:194:194) (224:224:224)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (392:392:392) (452:452:452)) - (PORT datab (251:251:251) (325:325:325)) - (PORT datac (1235:1235:1235) (1184:1184:1184)) - (PORT datad (169:169:169) (195:195:195)) + (PORT dataa (1331:1331:1331) (1313:1313:1313)) + (PORT datab (798:798:798) (793:793:793)) + (PORT datac (847:847:847) (872:872:872)) + (PORT datad (579:579:579) (571:571:571)) (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (765:765:765) (779:779:779)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (877:877:877) (870:870:870)) - (PORT ena (1271:1271:1271) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (876:876:876) (869:869:869)) - (PORT ena (1281:1281:1281) (1292:1292:1292)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (826:826:826) (882:882:882)) - (PORT datab (829:829:829) (893:893:893)) - (PORT datad (195:195:195) (252:252:252)) - (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1273:1273:1273) (1283:1283:1283)) - (PORT ena (906:906:906) (905:905:905)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1270:1270:1270) (1280:1280:1280)) - (PORT ena (893:893:893) (877:877:877)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (471:471:471)) - (PORT datab (454:454:454) (482:482:482)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1169:1169:1169) (1176:1176:1176)) - (PORT ena (1173:1173:1173) (1169:1169:1169)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1169:1169:1169) (1174:1174:1174)) - (PORT ena (1093:1093:1093) (1070:1070:1070)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (403:403:403)) - (PORT datab (1479:1479:1479) (1472:1472:1472)) - (PORT datad (1098:1098:1098) (1082:1082:1082)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (1130:1130:1130) (1150:1150:1150)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (980:980:980) (950:950:950)) - (PORT datab (1074:1074:1074) (1080:1080:1080)) - (PORT datad (217:217:217) (250:250:250)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (747:747:747) (778:778:778)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1118:1118:1118) (1094:1094:1094)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1154:1154:1154) (1178:1178:1178)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (295:295:295)) - (PORT datab (217:217:217) (259:259:259)) - (PORT datad (812:812:812) (819:819:819)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1355:1355:1355)) - (PORT asdata (631:631:631) (635:635:635)) - (PORT ena (1298:1298:1298) (1265:1265:1265)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1355:1355:1355)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1357:1357:1357) (1333:1333:1333)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (981:981:981) (954:954:954)) - (PORT datab (1176:1176:1176) (1200:1200:1200)) - (PORT datad (197:197:197) (254:254:254)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (782:782:782) (766:766:766)) - (PORT datab (952:952:952) (970:970:970)) - (PORT datac (745:745:745) (771:771:771)) - (PORT datad (159:159:159) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (887:887:887) (875:875:875)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (887:887:887)) - (PORT datab (1114:1114:1114) (1151:1151:1151)) - (PORT datad (833:833:833) (842:842:842)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (381:381:381)) - (PORT datab (768:768:768) (789:789:789)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (522:522:522) (514:514:514)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (781:781:781) (779:779:779)) - (PORT datab (813:813:813) (808:808:808)) - (PORT datac (750:750:750) (780:780:780)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT asdata (815:815:815) (794:794:794)) - (PORT ena (862:862:862) (838:838:838)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) + (INSTANCE z80_\|execute_\|ctl_mWrite\~7) (DELAY (ABSOLUTE - (PORT dataa (217:217:217) (259:259:259)) - (PORT datab (839:839:839) (848:848:848)) - (PORT datad (189:189:189) (221:221:221)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (1131:1131:1131) (1144:1144:1144)) + (PORT datab (237:237:237) (284:284:284)) + (PORT datac (853:853:853) (889:889:889)) + (PORT datad (1096:1096:1096) (1108:1108:1108)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) (DELAY (ABSOLUTE - (PORT dataa (216:216:216) (261:261:261)) - (PORT datac (194:194:194) (260:260:260)) - (PORT datad (158:158:158) (178:178:178)) + (PORT dataa (532:532:532) (526:526:526)) + (PORT datab (1228:1228:1228) (1309:1309:1309)) + (PORT datac (750:750:750) (728:728:728)) + (PORT datad (768:768:768) (830:830:830)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1709:1709:1709) (1770:1770:1770)) + (PORT datab (1512:1512:1512) (1639:1639:1639)) + (PORT datac (1577:1577:1577) (1614:1614:1614)) + (PORT datad (805:805:805) (801:801:801)) (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1062:1062:1062) (1027:1027:1027)) - (PORT datab (767:767:767) (747:747:747)) - (PORT datac (179:179:179) (212:212:212)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[8\]) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (656:656:656)) - (PORT datac (742:742:742) (728:728:728)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1370:1370:1370)) - (PORT ena (1981:1981:1981) (2010:2010:2010)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (458:458:458)) - (PORT datab (252:252:252) (329:329:329)) - (PORT datac (1232:1232:1232) (1182:1182:1182)) - (PORT datad (173:173:173) (200:200:200)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) - (DELAY - (ABSOLUTE - (PORT datac (220:220:220) (301:301:301)) - (PORT datad (302:302:302) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (659:659:659) (668:668:668)) - (PORT datac (759:759:759) (753:753:753)) - (PORT datad (542:542:542) (535:535:535)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[9\]) - (DELAY - (ABSOLUTE - (PORT datab (337:337:337) (345:345:345)) - (PORT datac (817:817:817) (816:816:816)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[9\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (512:512:512) (503:503:503)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1370:1370:1370)) - (PORT ena (1924:1924:1924) (1928:1928:1928)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (325:325:325)) - (PORT datab (250:250:250) (331:331:331)) - (PORT datac (1244:1244:1244) (1192:1192:1192)) - (PORT datad (303:303:303) (309:309:309)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1010:1010:1010) (1030:1030:1030)) - (PORT ena (1271:1271:1271) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1011:1011:1011) (1031:1031:1031)) - (PORT ena (1281:1281:1281) (1292:1292:1292)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (827:827:827) (884:884:884)) - (PORT datab (828:828:828) (886:886:886)) - (PORT datad (197:197:197) (252:252:252)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (1776:1776:1776) (1820:1820:1820)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (757:757:757) (743:743:743)) - (PORT datab (1075:1075:1075) (1081:1081:1081)) - (PORT datad (220:220:220) (254:254:254)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1312:1312:1312) (1376:1376:1376)) - (PORT ena (1039:1039:1039) (993:993:993)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (714:714:714) (768:768:768)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (390:390:390)) - (PORT datab (812:812:812) (837:837:837)) - (PORT datad (325:325:325) (363:363:363)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (927:927:927) (951:951:951)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1093:1093:1093) (1070:1070:1070)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1824:1824:1824) (1865:1865:1865)) - (PORT ena (1173:1173:1173) (1169:1169:1169)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (529:529:529) (565:565:565)) - (PORT datab (1478:1478:1478) (1476:1476:1476)) - (PORT datad (1096:1096:1096) (1087:1087:1087)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1347:1347:1347) (1329:1329:1329)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1312:1312:1312) (1374:1374:1374)) - (PORT ena (1164:1164:1164) (1167:1167:1167)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1020:1020:1020) (1009:1009:1009)) - (PORT datab (628:628:628) (666:666:666)) - (PORT datad (783:783:783) (799:799:799)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (582:582:582)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (552:552:552) (555:555:555)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1994:1994:1994) (2056:2056:2056)) - (PORT ena (893:893:893) (877:877:877)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1995:1995:1995) (2060:2060:2060)) - (PORT ena (906:906:906) (905:905:905)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (428:428:428) (478:478:478)) - (PORT datab (222:222:222) (291:291:291)) - (PORT datad (413:413:413) (447:447:447)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (2016:2016:2016) (2070:2070:2070)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (891:891:891)) - (PORT datab (1113:1113:1113) (1148:1148:1148)) - (PORT datad (831:831:831) (837:837:837)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (716:716:716) (753:753:753)) - (PORT datab (524:524:524) (527:527:527)) - (PORT datac (521:521:521) (502:502:502)) - (PORT datad (787:787:787) (800:800:800)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (769:769:769) (825:825:825)) - (PORT datab (372:372:372) (373:373:373)) - (PORT datac (786:786:786) (830:830:830)) - (PORT datad (1209:1209:1209) (1198:1198:1198)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT asdata (492:492:492) (521:521:521)) - (PORT ena (862:862:862) (838:838:838)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1743:1743:1743) (1803:1803:1803)) - (PORT datab (213:213:213) (254:254:254)) - (PORT datad (193:193:193) (223:223:223)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (765:765:765) (779:779:779)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (260:260:260)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datad (334:334:334) (367:367:367)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1066:1066:1066) (1029:1029:1029)) - (PORT datab (517:517:517) (500:500:500)) - (PORT datac (181:181:181) (216:216:216)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[10\]) - (DELAY - (ABSOLUTE - (PORT datac (180:180:180) (213:213:213)) - (PORT datad (805:805:805) (809:809:809)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[10\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (495:495:495) (485:485:485)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1370:1370:1370)) - (PORT ena (1924:1924:1924) (1928:1928:1928)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (330:330:330)) - (PORT datab (246:246:246) (327:327:327)) - (PORT datac (1247:1247:1247) (1195:1195:1195)) - (PORT datad (302:302:302) (311:311:311)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[11\]) - (DELAY - (ABSOLUTE - (PORT datab (554:554:554) (576:576:576)) - (PORT datad (852:852:852) (845:845:845)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1370:1370:1370)) - (PORT ena (1924:1924:1924) (1928:1928:1928)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datac (530:530:530) (559:559:559)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1196:1196:1196) (1178:1178:1178)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT asdata (671:671:671) (690:690:690)) - (PORT ena (857:857:857) (835:835:835)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (237:237:237)) - (PORT datab (373:373:373) (393:393:393)) - (PORT datad (364:364:364) (377:377:377)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (299:299:299)) - (PORT datac (750:750:750) (785:785:785)) - (PORT datad (594:594:594) (591:591:591)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (532:532:532) (520:520:520)) - (PORT datab (792:792:792) (788:788:788)) - (PORT datac (630:630:630) (643:643:643)) - (PORT datad (161:161:161) (183:183:183)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (567:567:567) (572:572:572)) - (PORT datab (758:758:758) (804:804:804)) - (PORT datac (360:360:360) (384:384:384)) - (PORT datad (1211:1211:1211) (1194:1194:1194)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (834:834:834)) - (PORT datab (200:200:200) (244:244:244)) - (PORT datac (1069:1069:1069) (1087:1087:1087)) - (PORT datad (571:571:571) (569:569:569)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (963:963:963)) - (PORT datab (1937:1937:1937) (1953:1953:1953)) - (PORT datac (626:626:626) (660:660:660)) - (PORT datad (1598:1598:1598) (1668:1668:1668)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT datab (889:889:889) (910:910:910)) - (PORT datac (1062:1062:1062) (1036:1036:1036)) - (PORT datad (632:632:632) (648:648:648)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT datab (601:601:601) (629:629:629)) - (PORT datac (593:593:593) (618:618:618)) - (PORT datad (590:590:590) (591:591:591)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (626:626:626)) - (PORT datab (598:598:598) (633:633:633)) - (PORT datac (175:175:175) (206:206:206)) - (PORT datad (543:543:543) (529:529:529)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1051:1051:1051) (1043:1043:1043)) - (PORT datab (1175:1175:1175) (1231:1231:1231)) - (PORT datac (561:561:561) (568:568:568)) - (PORT datad (1041:1041:1041) (1014:1014:1014)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1856:1856:1856) (1979:1979:1979)) - (PORT datab (1176:1176:1176) (1205:1205:1205)) - (PORT datac (914:914:914) (922:922:922)) - (PORT datad (1343:1343:1343) (1387:1387:1387)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) - (DELAY - (ABSOLUTE - (PORT dataa (938:938:938) (951:951:951)) - (PORT datab (1484:1484:1484) (1550:1550:1550)) - (PORT datac (1048:1048:1048) (1029:1029:1029)) - (PORT datad (606:606:606) (624:624:624)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~5) - (DELAY - (ABSOLUTE - (PORT dataa (2373:2373:2373) (2398:2398:2398)) - (PORT datab (1443:1443:1443) (1492:1492:1492)) - (PORT datac (800:800:800) (809:809:809)) - (PORT datad (175:175:175) (202:202:202)) - (IOPATH dataa combout (272:272:272) (269:269:269)) (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (364:364:364)) - (PORT datab (744:744:744) (771:771:771)) - (PORT datac (778:778:778) (763:763:763)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -18502,15 +3481,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) + (INSTANCE z80_\|execute_\|fMWrite\~4) (DELAY (ABSOLUTE - (PORT dataa (596:596:596) (594:594:594)) - (PORT datab (1079:1079:1079) (1111:1111:1111)) - (PORT datac (520:520:520) (505:505:505)) - (PORT datad (553:553:553) (546:546:546)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT datab (1495:1495:1495) (1566:1566:1566)) + (PORT datac (1289:1289:1289) (1304:1304:1304)) + (PORT datad (1218:1218:1218) (1232:1232:1232)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -18518,150 +3495,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~5) + (INSTANCE z80_\|execute_\|ctl_state_alu\~4) (DELAY (ABSOLUTE - (PORT dataa (549:549:549) (548:548:548)) - (PORT datab (1031:1031:1031) (1053:1053:1053)) - (PORT datac (521:521:521) (520:520:520)) - (PORT datad (843:843:843) (869:869:869)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datab (1921:1921:1921) (2005:2005:2005)) + (PORT datad (864:864:864) (923:923:923)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~6) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) (DELAY (ABSOLUTE - (PORT dataa (234:234:234) (306:306:306)) - (PORT datac (154:154:154) (184:184:184)) + (PORT dataa (859:859:859) (875:875:875)) + (PORT datab (1280:1280:1280) (1258:1258:1258)) + (PORT datac (1522:1522:1522) (1535:1535:1535)) + (PORT datad (1077:1077:1077) (1089:1089:1089)) (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) - (DELAY - (ABSOLUTE - (PORT dataa (241:241:241) (312:312:312)) - (PORT datac (1002:1002:1002) (1029:1029:1029)) - (PORT datad (840:840:840) (869:869:869)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT datab (893:893:893) (911:911:911)) - (PORT datac (339:339:339) (364:364:364)) - (PORT datad (624:624:624) (645:645:645)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (654:654:654)) - (PORT datab (1034:1034:1034) (1063:1063:1063)) - (PORT datac (551:551:551) (544:544:544)) - (PORT datad (353:353:353) (393:393:393)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (241:241:241) (312:312:312)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (520:520:520) (517:517:517)) - (PORT datad (838:838:838) (866:866:866)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1348:1348:1348) (1339:1339:1339)) - (PORT datab (1386:1386:1386) (1404:1404:1404)) - (PORT datac (1701:1701:1701) (1703:1703:1703)) - (PORT datad (373:373:373) (394:394:394)) - (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -18670,471 +3523,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~20) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) (DELAY (ABSOLUTE - (PORT dataa (1326:1326:1326) (1339:1339:1339)) - (PORT datab (1518:1518:1518) (1587:1587:1587)) - (PORT datac (986:986:986) (975:975:975)) - (PORT datad (1189:1189:1189) (1255:1255:1255)) + (PORT dataa (839:839:839) (850:850:850)) + (PORT datab (644:644:644) (683:683:683)) + (PORT datac (848:848:848) (848:848:848)) + (PORT datad (612:612:612) (648:648:648)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1092:1092:1092) (1083:1083:1083)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (807:807:807) (819:819:819)) + (PORT datad (167:167:167) (193:193:193)) (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (807:807:807)) - (PORT datab (875:875:875) (878:878:878)) - (PORT datac (797:797:797) (781:781:781)) - (PORT datad (603:603:603) (611:611:611)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) - (DELAY - (ABSOLUTE - (PORT dataa (443:443:443) (460:460:460)) - (PORT datab (1102:1102:1102) (1116:1116:1116)) - (PORT datac (843:843:843) (891:891:891)) - (PORT datad (1284:1284:1284) (1328:1328:1328)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal61\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1605:1605:1605) (1652:1652:1652)) - (PORT datab (1274:1274:1274) (1292:1292:1292)) - (PORT datac (1463:1463:1463) (1566:1566:1566)) - (PORT datad (1384:1384:1384) (1457:1457:1457)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) - (DELAY - (ABSOLUTE - (PORT datab (1689:1689:1689) (1725:1725:1725)) - (PORT datac (1573:1573:1573) (1613:1613:1613)) - (PORT datad (847:847:847) (878:878:878)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1726:1726:1726) (1696:1696:1696)) - (PORT datab (181:181:181) (215:215:215)) - (PORT datac (809:809:809) (787:787:787)) - (PORT datad (750:750:750) (734:734:734)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1234:1234:1234) (1289:1289:1289)) - (PORT datab (1624:1624:1624) (1652:1652:1652)) - (PORT datac (1346:1346:1346) (1370:1370:1370)) - (PORT datad (177:177:177) (200:200:200)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1414:1414:1414) (1447:1447:1447)) - (PORT datab (843:843:843) (875:875:875)) - (PORT datac (174:174:174) (206:206:206)) - (PORT datad (185:185:185) (209:209:209)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (236:236:236)) - (PORT datab (189:189:189) (224:224:224)) - (PORT datac (161:161:161) (195:195:195)) - (PORT datad (167:167:167) (192:192:192)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1638:1638:1638) (1596:1596:1596)) - (PORT datab (779:779:779) (785:785:785)) - (PORT datac (1208:1208:1208) (1288:1288:1288)) - (PORT datad (2364:2364:2364) (2375:2375:2375)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) - (DELAY - (ABSOLUTE - (PORT dataa (545:545:545) (551:551:551)) - (PORT datab (225:225:225) (259:259:259)) - (PORT datac (199:199:199) (233:233:233)) - (PORT datad (831:831:831) (867:867:867)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (980:980:980) (953:953:953)) - (PORT datab (1500:1500:1500) (1507:1507:1507)) - (PORT datac (1094:1094:1094) (1102:1102:1102)) - (PORT datad (1617:1617:1617) (1563:1563:1563)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal71\~2) - (DELAY - (ABSOLUTE - (PORT dataa (797:797:797) (821:821:821)) - (PORT datab (866:866:866) (911:911:911)) - (PORT datac (197:197:197) (231:231:231)) - (PORT datad (830:830:830) (866:866:866)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (234:234:234)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datac (181:181:181) (216:216:216)) - (PORT datad (167:167:167) (191:191:191)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1123:1123:1123) (1133:1133:1133)) - (PORT datab (207:207:207) (242:242:242)) - (PORT datac (1906:1906:1906) (1932:1932:1932)) - (PORT datad (1305:1305:1305) (1352:1352:1352)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (640:640:640)) - (PORT datab (1366:1366:1366) (1379:1379:1379)) - (PORT datac (1366:1366:1366) (1362:1362:1362)) - (PORT datad (588:588:588) (584:584:584)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla25M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (779:779:779) (767:767:767)) - (PORT datab (1367:1367:1367) (1380:1380:1380)) - (PORT datac (1486:1486:1486) (1439:1439:1439)) - (PORT datad (1331:1331:1331) (1383:1383:1383)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (194:194:194) (232:232:232)) - (PORT datac (778:778:778) (779:779:779)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (240:240:240)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (984:984:984) (969:969:969)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal72\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1292:1292:1292) (1320:1320:1320)) - (PORT datab (2167:2167:2167) (2220:2220:2220)) - (PORT datac (1039:1039:1039) (1045:1045:1045)) - (PORT datad (787:787:787) (766:766:766)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal73\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1843:1843:1843) (1911:1911:1911)) - (PORT datab (1033:1033:1033) (1056:1056:1056)) - (PORT datac (1247:1247:1247) (1267:1267:1267)) - (PORT datad (795:795:795) (774:774:774)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (929:929:929)) - (PORT datab (886:886:886) (934:934:934)) - (PORT datac (1635:1635:1635) (1643:1643:1643)) - (PORT datad (1348:1348:1348) (1364:1364:1364)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (974:974:974) (963:963:963)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (566:566:566) (569:569:569)) - (PORT datad (553:553:553) (547:547:547)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1393:1393:1393) (1432:1432:1432)) - (PORT datab (1814:1814:1814) (1843:1843:1843)) - (PORT datac (1150:1150:1150) (1194:1194:1194)) - (PORT datad (852:852:852) (886:886:886)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) - (DELAY - (ABSOLUTE - (PORT datab (806:806:806) (799:799:799)) - (PORT datac (757:757:757) (768:768:768)) - (PORT datad (753:753:753) (745:745:745)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (2375:2375:2375) (2401:2401:2401)) - (PORT datac (1415:1415:1415) (1465:1465:1465)) - (PORT datad (1429:1429:1429) (1504:1504:1504)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (226:226:226) (276:276:276)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (1075:1075:1075) (1083:1083:1083)) - (PORT datad (175:175:175) (203:203:203)) - (IOPATH dataa combout (307:307:307) (306:306:306)) (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (749:749:749) (771:771:771)) - (PORT datab (570:570:570) (593:593:593)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (735:735:735) (796:796:796)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~15) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (856:856:856)) - (PORT datac (771:771:771) (772:772:772)) - (PORT datad (594:594:594) (607:607:607)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~16) - (DELAY - (ABSOLUTE - (PORT dataa (847:847:847) (863:863:863)) - (PORT datab (339:339:339) (350:350:350)) - (PORT datac (545:545:545) (554:554:554)) - (PORT datad (318:318:318) (317:317:317)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -19142,942 +3555,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) + (INSTANCE z80_\|execute_\|fMWrite\~8) (DELAY (ABSOLUTE - (PORT datac (819:819:819) (825:825:825)) - (PORT datad (768:768:768) (767:767:767)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (595:595:595)) - (PORT datab (1019:1019:1019) (1019:1019:1019)) - (PORT datac (712:712:712) (684:684:684)) - (PORT datad (566:566:566) (579:579:579)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (842:842:842) (826:826:826)) - (PORT datab (190:190:190) (225:225:225)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1849:1849:1849) (1839:1839:1839)) - (PORT datab (207:207:207) (243:243:243)) - (PORT datac (1567:1567:1567) (1621:1621:1621)) - (PORT datad (1378:1378:1378) (1406:1406:1406)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1052:1052:1052) (1063:1063:1063)) - (PORT datab (1465:1465:1465) (1537:1537:1537)) - (PORT datac (2344:2344:2344) (2367:2367:2367)) - (PORT datad (173:173:173) (200:200:200)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (926:926:926) (957:957:957)) - (PORT datab (1202:1202:1202) (1227:1227:1227)) - (PORT datac (828:828:828) (821:821:821)) - (PORT datad (165:165:165) (190:190:190)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (596:596:596)) - (PORT datab (2125:2125:2125) (2116:2116:2116)) - (PORT datac (1899:1899:1899) (1945:1945:1945)) - (PORT datad (1071:1071:1071) (1063:1063:1063)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (569:569:569) (567:567:567)) - (PORT datab (564:564:564) (566:566:566)) - (PORT datac (508:508:508) (506:506:506)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) - (DELAY - (ABSOLUTE - (PORT dataa (953:953:953) (964:964:964)) - (PORT datab (1889:1889:1889) (1959:1959:1959)) - (PORT datac (761:761:761) (747:747:747)) - (PORT datad (2321:2321:2321) (2343:2343:2343)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1430:1430:1430) (1444:1444:1444)) - (PORT datab (865:865:865) (915:915:915)) - (PORT datac (559:559:559) (587:587:587)) - (PORT datad (534:534:534) (521:521:521)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (772:772:772) (828:828:828)) - (PORT datab (201:201:201) (233:233:233)) - (PORT datac (617:617:617) (630:630:630)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (610:610:610)) - (PORT datab (1080:1080:1080) (1089:1089:1089)) - (PORT datac (594:594:594) (617:617:617)) - (PORT datad (287:287:287) (294:294:294)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (608:608:608)) - (PORT datab (742:742:742) (790:790:790)) - (PORT datac (1019:1019:1019) (1018:1018:1018)) - (PORT datad (548:548:548) (553:553:553)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) - (DELAY - (ABSOLUTE - (PORT dataa (578:578:578) (600:600:600)) - (PORT datab (600:600:600) (610:610:610)) - (PORT datac (859:859:859) (925:925:925)) - (PORT datad (772:772:772) (765:765:765)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1393:1393:1393) (1433:1433:1433)) - (PORT datab (979:979:979) (967:967:967)) - (PORT datac (1150:1150:1150) (1195:1195:1195)) - (PORT datad (850:850:850) (884:884:884)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1339:1339:1339) (1319:1319:1319)) - (PORT datab (1049:1049:1049) (1071:1071:1071)) - (PORT datac (1100:1100:1100) (1162:1162:1162)) - (PORT datad (1057:1057:1057) (1051:1051:1051)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (591:591:591)) - (PORT datab (949:949:949) (972:972:972)) - (PORT datac (738:738:738) (720:720:720)) - (PORT datad (572:572:572) (566:566:566)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (249:249:249)) - (PORT datab (958:958:958) (972:972:972)) - (PORT datac (793:793:793) (769:769:769)) - (PORT datad (551:551:551) (557:557:557)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (547:547:547) (556:556:556)) - (PORT datab (201:201:201) (245:245:245)) - (PORT datac (765:765:765) (777:777:777)) - (PORT datad (1268:1268:1268) (1337:1337:1337)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~9) - (DELAY - (ABSOLUTE - (PORT dataa (718:718:718) (754:754:754)) - (PORT datab (780:780:780) (772:772:772)) - (PORT datac (697:697:697) (758:758:758)) - (PORT datad (703:703:703) (726:726:726)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~10) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) - (DELAY - (ABSOLUTE - (PORT clk (1331:1331:1331) (1350:1350:1350)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1133:1133:1133) (1133:1133:1133)) - (PORT datab (640:640:640) (667:667:667)) - (PORT datac (841:841:841) (887:887:887)) - (PORT datad (988:988:988) (976:976:976)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (599:599:599)) - (PORT datab (601:601:601) (604:604:604)) - (PORT datac (858:858:858) (924:924:924)) - (PORT datad (362:362:362) (363:363:363)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) - (DELAY - (ABSOLUTE - (PORT dataa (894:894:894) (921:921:921)) - (PORT datab (1659:1659:1659) (1669:1669:1669)) - (PORT datac (1148:1148:1148) (1193:1193:1193)) - (PORT datad (984:984:984) (962:962:962)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1863:1863:1863) (1886:1886:1886)) - (PORT datab (2223:2223:2223) (2282:2282:2282)) - (PORT datac (1279:1279:1279) (1294:1294:1294)) - (PORT datad (1468:1468:1468) (1553:1553:1553)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1391:1391:1391) (1425:1425:1425)) - (PORT datab (359:359:359) (365:365:365)) - (PORT datac (1149:1149:1149) (1187:1187:1187)) - (PORT datad (807:807:807) (816:816:816)) + (PORT dataa (945:945:945) (952:952:952)) + (PORT datab (1859:1859:1859) (1833:1833:1833)) + (PORT datac (921:921:921) (925:925:925)) + (PORT datad (1019:1019:1019) (1028:1028:1028)) (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1150:1150:1150)) - (PORT datab (318:318:318) (332:332:332)) - (PORT datac (988:988:988) (973:973:973)) - (PORT datad (314:314:314) (316:316:316)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) - (DELAY - (ABSOLUTE - (PORT dataa (329:329:329) (347:347:347)) - (PORT datab (596:596:596) (587:587:587)) - (PORT datac (153:153:153) (183:183:183)) - (PORT datad (566:566:566) (571:571:571)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~18) - (DELAY - (ABSOLUTE - (PORT dataa (776:776:776) (781:781:781)) - (PORT datab (1040:1040:1040) (1059:1059:1059)) - (PORT datac (784:784:784) (802:802:802)) - (PORT datad (334:334:334) (376:376:376)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) - (DELAY - (ABSOLUTE - (PORT dataa (2372:2372:2372) (2401:2401:2401)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (1289:1289:1289) (1277:1277:1277)) - (PORT datad (1742:1742:1742) (1773:1773:1773)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (420:420:420) (472:472:472)) - (PORT datab (418:418:418) (467:467:467)) - (PORT datac (802:802:802) (802:802:802)) - (PORT datad (611:611:611) (624:624:624)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (508:508:508) (513:513:513)) - (PORT datab (582:582:582) (628:628:628)) - (PORT datac (577:577:577) (576:576:576)) - (PORT datad (583:583:583) (615:615:615)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) - (DELAY - (ABSOLUTE - (PORT dataa (760:760:760) (755:755:755)) - (PORT datab (579:579:579) (568:568:568)) - (PORT datac (176:176:176) (207:207:207)) - (PORT datad (167:167:167) (192:192:192)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (758:758:758) (732:732:732)) - (PORT datab (573:573:573) (570:570:570)) - (PORT datac (1004:1004:1004) (1027:1027:1027)) - (PORT datad (831:831:831) (865:865:865)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (213:213:213) (265:265:265)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (399:399:399) (468:468:468)) - (PORT datab (625:625:625) (653:653:653)) - (PORT datac (802:802:802) (803:803:803)) - (PORT datad (611:611:611) (629:629:629)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~12) - (DELAY - (ABSOLUTE - (PORT dataa (797:797:797) (822:822:822)) - (PORT datab (200:200:200) (241:241:241)) - (PORT datac (767:767:767) (779:779:779)) - (PORT datad (829:829:829) (876:876:876)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) - (DELAY - (ABSOLUTE - (PORT dataa (719:719:719) (754:754:754)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1684:1684:1684) (1638:1638:1638)) - (PORT datad (741:741:741) (728:728:728)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (624:624:624)) - (PORT datab (1646:1646:1646) (1589:1589:1589)) - (PORT datac (161:161:161) (194:194:194)) - (PORT datad (763:763:763) (749:749:749)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) - (DELAY - (ABSOLUTE - (PORT dataa (2200:2200:2200) (2255:2255:2255)) - (PORT datab (1385:1385:1385) (1430:1430:1430)) - (PORT datac (812:812:812) (800:800:800)) - (PORT datad (936:936:936) (996:996:996)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) - (DELAY - (ABSOLUTE - (PORT dataa (536:536:536) (525:525:525)) - (PORT datab (910:910:910) (930:930:930)) - (PORT datac (615:615:615) (641:641:641)) - (PORT datad (759:759:759) (743:743:743)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (922:922:922)) - (PORT datab (407:407:407) (416:416:416)) - (PORT datac (878:878:878) (907:907:907)) - (PORT datad (1087:1087:1087) (1100:1100:1100)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) - (DELAY - (ABSOLUTE - (PORT dataa (214:214:214) (255:255:255)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datac (176:176:176) (208:208:208)) - (PORT datad (190:190:190) (214:214:214)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) - (DELAY - (ABSOLUTE - (PORT datab (205:205:205) (251:251:251)) - (PORT datac (172:172:172) (211:211:211)) - (PORT datad (351:351:351) (351:351:351)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (590:590:590) (599:599:599)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (178:178:178) (199:199:199)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) - (DELAY - (ABSOLUTE - (PORT datab (1176:1176:1176) (1233:1233:1233)) - (PORT datac (824:824:824) (837:837:837)) - (PORT datad (1082:1082:1082) (1061:1061:1061)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1191:1191:1191) (1202:1202:1202)) - (PORT datab (936:936:936) (969:969:969)) - (PORT datac (1342:1342:1342) (1366:1366:1366)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1896:1896:1896) (1896:1896:1896)) - (PORT datab (866:866:866) (914:914:914)) - (PORT datac (1118:1118:1118) (1108:1108:1108)) - (PORT datad (1005:1005:1005) (1001:1001:1001)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) - (DELAY - (ABSOLUTE - (PORT dataa (854:854:854) (850:850:850)) - (PORT datab (981:981:981) (964:964:964)) - (PORT datac (819:819:819) (829:829:829)) - (PORT datad (524:524:524) (522:522:522)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1375:1375:1375) (1411:1411:1411)) - (PORT datab (408:408:408) (415:415:415)) - (PORT datac (859:859:859) (884:884:884)) - (PORT datad (1089:1089:1089) (1098:1098:1098)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1379:1379:1379) (1416:1416:1416)) - (PORT datab (214:214:214) (251:251:251)) - (PORT datac (1854:1854:1854) (1845:1845:1845)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datac (571:571:571) (585:585:585)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (234:234:234)) - (PORT datab (198:198:198) (231:231:231)) - (PORT datac (745:745:745) (775:775:775)) - (PORT datad (525:525:525) (507:507:507)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1348:1348:1348) (1376:1376:1376)) - (PORT datab (1303:1303:1303) (1272:1272:1272)) - (PORT datac (1453:1453:1453) (1474:1474:1474)) - (PORT datad (983:983:983) (973:973:973)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (700:700:700)) - (PORT datab (637:637:637) (664:664:664)) - (PORT datac (1479:1479:1479) (1443:1443:1443)) - (PORT datad (1325:1325:1325) (1335:1335:1335)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1242:1242:1242) (1288:1288:1288)) - (PORT datab (1003:1003:1003) (1001:1001:1001)) - (PORT datac (1453:1453:1453) (1470:1470:1470)) - (PORT datad (1656:1656:1656) (1697:1697:1697)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (776:776:776) (796:796:796)) - (PORT datac (1482:1482:1482) (1447:1447:1447)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (307:307:307) (323:323:323)) (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~42) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~51) (DELAY (ABSOLUTE - (PORT dataa (776:776:776) (781:781:781)) - (PORT datab (1008:1008:1008) (1007:1007:1007)) - (PORT datac (1948:1948:1948) (1963:1963:1963)) - (PORT datad (1650:1650:1650) (1690:1690:1690)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (267:267:267) (275:275:275)) + (PORT dataa (2247:2247:2247) (2326:2326:2326)) + (PORT datab (1119:1119:1119) (1163:1163:1163)) + (PORT datac (1293:1293:1293) (1352:1352:1352)) + (PORT datad (523:523:523) (502:502:502)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -20085,1940 +3587,137 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) + (INSTANCE z80_\|execute_\|ctl_ir_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (421:421:421) (454:454:454)) + (PORT datab (694:694:694) (743:743:743)) + (PORT datac (992:992:992) (977:977:977)) + (PORT datad (726:726:726) (769:769:769)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) + (DELAY + (ABSOLUTE + (PORT dataa (2033:2033:2033) (2119:2119:2119)) + (PORT datab (639:639:639) (633:633:633)) + (PORT datac (782:782:782) (792:792:792)) + (PORT datad (1734:1734:1734) (1802:1802:1802)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal46\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1631:1631:1631) (1680:1680:1680)) + (PORT datab (676:676:676) (710:710:710)) + (PORT datac (1712:1712:1712) (1688:1688:1688)) + (PORT datad (1483:1483:1483) (1569:1569:1569)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (755:755:755) (807:807:807)) + (PORT datab (1727:1727:1727) (1808:1808:1808)) + (PORT datac (306:306:306) (314:314:314)) + (PORT datad (1560:1560:1560) (1564:1564:1564)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (911:911:911)) + (PORT datab (1754:1754:1754) (1831:1831:1831)) + (PORT datac (2007:2007:2007) (2086:2086:2086)) + (PORT datad (885:885:885) (892:892:892)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~6) + (DELAY + (ABSOLUTE + (PORT datab (1556:1556:1556) (1562:1562:1562)) + (PORT datad (2013:2013:2013) (2000:2000:2000)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1195:1195:1195) (1217:1217:1217)) + (PORT datab (612:612:612) (634:634:634)) + (PORT datac (788:788:788) (784:784:784)) + (PORT datad (788:788:788) (785:785:785)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1344:1344:1344) (1345:1345:1345)) + (PORT datab (1382:1382:1382) (1399:1399:1399)) + (PORT datac (1139:1139:1139) (1152:1152:1152)) + (PORT datad (858:858:858) (880:880:880)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) (DELAY (ABSOLUTE (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (947:947:947) (926:926:926)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~41) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (642:642:642)) - (PORT datab (1892:1892:1892) (1909:1909:1909)) - (PORT datac (1365:1365:1365) (1394:1394:1394)) - (PORT datad (1233:1233:1233) (1319:1319:1319)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1393:1393:1393) (1426:1426:1426)) - (PORT datab (1812:1812:1812) (1838:1838:1838)) - (PORT datac (1150:1150:1150) (1187:1187:1187)) - (PORT datad (805:805:805) (815:815:815)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1607:1607:1607) (1662:1662:1662)) - (PORT datab (951:951:951) (989:989:989)) - (PORT datac (178:178:178) (214:214:214)) - (PORT datad (1379:1379:1379) (1408:1408:1408)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1071:1071:1071) (1049:1049:1049)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (1252:1252:1252) (1248:1248:1248)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~44) - (DELAY - (ABSOLUTE - (PORT dataa (762:762:762) (761:761:761)) - (PORT datab (1679:1679:1679) (1738:1738:1738)) - (PORT datac (1205:1205:1205) (1254:1254:1254)) - (PORT datad (1656:1656:1656) (1697:1697:1697)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (638:638:638) (671:671:671)) - (PORT datac (801:801:801) (797:797:797)) - (PORT datad (628:628:628) (658:658:658)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) - (DELAY - (ABSOLUTE - (PORT dataa (499:499:499) (493:493:493)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (594:594:594) (607:607:607)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~39) - (DELAY - (ABSOLUTE - (PORT dataa (549:549:549) (556:556:556)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (561:561:561) (564:564:564)) - (PORT datad (320:320:320) (324:324:324)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~40) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (848:848:848) (862:862:862)) - (PORT datac (174:174:174) (206:206:206)) - (PORT datad (297:297:297) (298:298:298)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1554:1554:1554) (1565:1565:1565)) - (PORT datab (1312:1312:1312) (1351:1351:1351)) - (PORT datac (580:580:580) (585:585:585)) - (PORT datad (792:792:792) (769:769:769)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1337:1337:1337) (1346:1346:1346)) - (PORT datab (783:783:783) (774:774:774)) - (PORT datac (772:772:772) (771:771:771)) - (PORT datad (1291:1291:1291) (1267:1267:1267)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R) - (DELAY - (ABSOLUTE - (PORT dataa (779:779:779) (768:768:768)) - (PORT datab (1647:1647:1647) (1590:1590:1590)) - (PORT datac (567:567:567) (568:568:568)) - (PORT datad (762:762:762) (748:748:748)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1101:1101:1101) (1125:1125:1125)) - (PORT datab (199:199:199) (241:241:241)) - (PORT datac (845:845:845) (862:862:862)) - (PORT datad (571:571:571) (566:566:566)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (240:240:240) (306:306:306)) - (PORT datab (883:883:883) (904:904:904)) - (PORT datac (493:493:493) (487:487:487)) - (PORT datad (1039:1039:1039) (999:999:999)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (555:555:555) (599:599:599)) - (PORT datab (1031:1031:1031) (1053:1053:1053)) - (PORT datac (547:547:547) (538:538:538)) - (PORT datad (364:364:364) (394:394:394)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (240:240:240) (311:311:311)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (517:517:517) (522:522:522)) - (PORT datad (839:839:839) (865:865:865)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (459:459:459)) - (PORT datab (386:386:386) (447:447:447)) - (PORT datac (803:803:803) (806:806:806)) - (PORT datad (608:608:608) (621:621:621)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (229:229:229)) - (PORT datab (584:584:584) (588:588:588)) - (PORT datac (325:325:325) (340:340:340)) - (PORT datad (769:769:769) (749:749:749)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (376:376:376)) - (PORT datab (601:601:601) (629:629:629)) - (PORT datac (594:594:594) (618:618:618)) - (PORT datad (590:590:590) (589:589:589)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (393:393:393)) - (PORT datab (214:214:214) (257:257:257)) - (PORT datac (164:164:164) (197:197:197)) - (PORT datad (165:165:165) (187:187:187)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (652:652:652) (659:659:659)) - (PORT datab (1092:1092:1092) (1142:1142:1142)) - (PORT datac (795:795:795) (806:806:806)) - (PORT datad (620:620:620) (631:631:631)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1189:1189:1189) (1229:1229:1229)) - (PORT datab (1813:1813:1813) (1842:1842:1842)) - (PORT datac (1365:1365:1365) (1399:1399:1399)) - (PORT datad (1379:1379:1379) (1403:1403:1403)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1051:1051:1051) (1044:1044:1044)) - (PORT datab (560:560:560) (584:584:584)) - (PORT datac (766:766:766) (737:737:737)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (232:232:232)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datad (743:743:743) (721:721:721)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1353:1353:1353)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1078:1078:1078) (1068:1068:1068)) - (PORT datac (525:525:525) (522:522:522)) - (PORT datad (1507:1507:1507) (1518:1518:1518)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) - (DELAY - (ABSOLUTE - (PORT dataa (849:849:849) (829:829:829)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1689:1689:1689) (1734:1734:1734)) - (PORT datad (520:520:520) (523:523:523)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~13) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (370:370:370)) - (PORT datab (1925:1925:1925) (1970:1970:1970)) - (PORT datac (1213:1213:1213) (1286:1286:1286)) - (PORT datad (835:835:835) (875:875:875)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (406:406:406)) - (PORT datab (566:566:566) (560:560:560)) - (PORT datac (1084:1084:1084) (1116:1116:1116)) - (PORT datad (762:762:762) (766:766:766)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) - (DELAY - (ABSOLUTE - (PORT dataa (536:536:536) (529:529:529)) - (PORT datab (569:569:569) (564:564:564)) - (PORT datad (528:528:528) (509:509:509)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (609:609:609)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (742:742:742) (717:717:717)) - (PORT datad (185:185:185) (209:209:209)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1567:1567:1567) (1575:1575:1575)) - (PORT datab (848:848:848) (842:842:842)) - (PORT datac (817:817:817) (812:812:812)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[12\]) - (DELAY - (ABSOLUTE - (PORT datab (369:369:369) (402:402:402)) - (PORT datac (821:821:821) (818:818:818)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[12\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (293:293:293) (300:300:300)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1371:1371:1371)) - (PORT ena (1896:1896:1896) (1904:1904:1904)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (577:577:577) (566:566:566)) - (PORT datab (839:839:839) (828:828:828)) - (PORT datac (214:214:214) (291:291:291)) - (PORT datad (540:540:540) (567:567:567)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1196:1196:1196) (1178:1178:1178)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT asdata (1164:1164:1164) (1172:1172:1172)) - (PORT ena (857:857:857) (835:835:835)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (408:408:408)) - (PORT datab (379:379:379) (396:396:396)) - (PORT datad (177:177:177) (197:197:197)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (638:638:638)) - (PORT datac (196:196:196) (263:263:263)) - (PORT datad (716:716:716) (727:727:727)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (369:369:369)) - (PORT datab (786:786:786) (780:780:780)) - (PORT datac (630:630:630) (636:636:636)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (1869:1869:1869) (1838:1838:1838)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (391:391:391)) - (PORT datab (1072:1072:1072) (1080:1080:1080)) - (PORT datad (694:694:694) (665:665:665)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1347:1347:1347) (1329:1329:1329)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (1869:1869:1869) (1835:1835:1835)) - (PORT ena (1140:1140:1140) (1144:1144:1144)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (643:643:643) (688:688:688)) - (PORT datab (813:813:813) (820:820:820)) - (PORT datad (802:802:802) (793:793:793)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1261:1261:1261) (1287:1287:1287)) - (PORT ena (1118:1118:1118) (1094:1094:1094)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1260:1260:1260) (1289:1289:1289)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (839:839:839) (857:857:857)) - (PORT datab (218:218:218) (260:260:260)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1284:1284:1284) (1247:1247:1247)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1093:1093:1093) (1070:1070:1070)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1583:1583:1583) (1534:1534:1534)) - (PORT ena (1173:1173:1173) (1169:1169:1169)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (363:363:363) (411:411:411)) - (PORT datab (1472:1472:1472) (1470:1470:1470)) - (PORT datad (1096:1096:1096) (1083:1083:1083)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (749:749:749) (726:726:726)) - (PORT datad (565:565:565) (572:572:572)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1722:1722:1722) (1763:1763:1763)) - (PORT ena (1271:1271:1271) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1722:1722:1722) (1763:1763:1763)) - (PORT ena (1281:1281:1281) (1292:1292:1292)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (894:894:894)) - (PORT datab (827:827:827) (886:886:886)) - (PORT datad (196:196:196) (252:252:252)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1788:1788:1788) (1721:1721:1721)) - (PORT ena (906:906:906) (905:905:905)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1785:1785:1785) (1721:1721:1721)) - (PORT ena (893:893:893) (877:877:877)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (428:428:428) (473:473:473)) - (PORT datab (449:449:449) (482:482:482)) - (PORT datad (198:198:198) (254:254:254)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1719:1719:1719) (1758:1758:1758)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (868:868:868) (888:888:888)) - (PORT datab (1114:1114:1114) (1157:1157:1157)) - (PORT datad (832:832:832) (841:841:841)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (616:616:616)) - (PORT datab (308:308:308) (325:325:325)) - (PORT datac (541:541:541) (534:534:534)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (816:816:816) (863:863:863)) - (PORT datab (772:772:772) (825:825:825)) - (PORT datac (786:786:786) (755:755:755)) - (PORT datad (1208:1208:1208) (1196:1196:1196)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1180:1180:1180) (1212:1212:1212)) - (PORT datab (897:897:897) (908:908:908)) - (PORT datac (817:817:817) (809:809:809)) - (PORT datad (1327:1327:1327) (1311:1311:1311)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1168:1168:1168) (1194:1194:1194)) - (PORT datab (1141:1141:1141) (1122:1122:1122)) - (PORT datac (845:845:845) (859:859:859)) - (PORT datad (861:861:861) (871:871:871)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (188:188:188) (226:226:226)) - (PORT datab (227:227:227) (274:274:274)) - (PORT datac (995:995:995) (950:950:950)) - (PORT datad (877:877:877) (892:892:892)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1187:1187:1187) (1217:1217:1217)) - (PORT datab (863:863:863) (907:907:907)) - (PORT datac (348:348:348) (357:357:357)) - (PORT datad (1116:1116:1116) (1172:1172:1172)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1023:1023:1023) (1113:1113:1113)) - (PORT datab (1690:1690:1690) (1727:1727:1727)) - (PORT datac (819:819:819) (847:847:847)) - (PORT datad (1442:1442:1442) (1492:1492:1492)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (881:881:881)) - (PORT datab (588:588:588) (597:597:597)) - (PORT datac (1286:1286:1286) (1346:1346:1346)) - (PORT datad (544:544:544) (546:546:546)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (224:224:224)) - (PORT datac (860:860:860) (864:864:864)) - (PORT datad (220:220:220) (254:254:254)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1096:1096:1096)) - (PORT datab (251:251:251) (320:320:320)) - (PORT datac (223:223:223) (275:275:275)) - (PORT datad (225:225:225) (262:262:262)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT datab (334:334:334) (356:356:356)) - (PORT datac (857:857:857) (887:887:887)) - (PORT datad (625:625:625) (655:655:655)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (623:623:623)) - (PORT datab (1072:1072:1072) (1085:1085:1085)) - (PORT datac (595:595:595) (626:626:626)) - (PORT datad (619:619:619) (635:635:635)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (559:559:559) (560:560:560)) - (PORT datab (306:306:306) (321:321:321)) - (PORT datac (1071:1071:1071) (1088:1088:1088)) - (PORT datad (504:504:504) (485:485:485)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (606:606:606)) - (PORT datab (919:919:919) (929:929:929)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (199:199:199) (238:238:238)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (556:556:556) (543:543:543)) - (PORT datab (889:889:889) (910:910:910)) - (PORT datac (799:799:799) (810:810:810)) - (PORT datad (312:312:312) (322:322:322)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (619:619:619) (648:648:648)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) - (DELAY - (ABSOLUTE - (PORT dataa (842:842:842) (853:853:853)) - (PORT datab (670:670:670) (693:693:693)) - (PORT datac (859:859:859) (885:885:885)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (607:607:607)) - (PORT datab (590:590:590) (623:623:623)) - (PORT datac (566:566:566) (594:594:594)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (583:583:583)) - (PORT datab (874:874:874) (897:897:897)) - (PORT datac (1004:1004:1004) (1034:1034:1034)) - (PORT datad (536:536:536) (536:536:536)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (240:240:240) (311:311:311)) - (PORT datac (156:156:156) (186:186:186)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (397:397:397) (467:467:467)) - (PORT datac (596:596:596) (629:629:629)) - (PORT datad (609:609:609) (628:628:628)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (549:549:549) (534:534:534)) - (PORT datab (765:765:765) (758:758:758)) - (PORT datac (740:740:740) (715:715:715)) - (PORT datad (184:184:184) (209:209:209)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (629:629:629)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datac (182:182:182) (217:217:217)) - (PORT datad (758:758:758) (742:742:742)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (606:606:606)) - (PORT datab (582:582:582) (628:628:628)) - (PORT datad (583:583:583) (615:615:615)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (621:621:621)) - (PORT datab (801:801:801) (784:784:784)) - (PORT datac (163:163:163) (197:197:197)) - (PORT datad (480:480:480) (472:472:472)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (187:187:187) (226:226:226)) - (PORT datab (192:192:192) (232:232:232)) - (PORT datac (181:181:181) (215:215:215)) - (PORT datad (167:167:167) (191:191:191)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (585:585:585) (633:633:633)) - (PORT datab (616:616:616) (621:621:621)) - (PORT datad (567:567:567) (579:579:579)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (365:365:365)) - (PORT datab (585:585:585) (589:589:589)) - (PORT datac (163:163:163) (195:195:195)) - (PORT datad (768:768:768) (749:749:749)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (368:368:368)) - (PORT datab (368:368:368) (374:374:374)) - (PORT datac (161:161:161) (194:194:194)) - (PORT datad (340:340:340) (345:345:345)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) - (DELAY - (ABSOLUTE - (PORT datac (1618:1618:1618) (1563:1563:1563)) - (PORT datad (762:762:762) (748:748:748)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (363:363:363)) - (PORT datab (210:210:210) (251:251:251)) (PORT datac (160:160:160) (193:193:193)) - (PORT datad (164:164:164) (187:187:187)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (231:231:231)) - (PORT datab (212:212:212) (254:254:254)) - (PORT datac (325:325:325) (338:338:338)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (987:987:987) (994:994:994)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1093:1093:1093) (1070:1070:1070)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1322:1322:1322) (1333:1333:1333)) - (PORT ena (1173:1173:1173) (1169:1169:1169)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (295:295:295)) - (PORT datab (1475:1475:1475) (1473:1473:1473)) - (PORT datad (1095:1095:1095) (1089:1089:1089)) + (PORT datad (824:824:824) (846:846:846)) (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1514:1514:1514) (1542:1542:1542)) - (PORT ena (1118:1118:1118) (1094:1094:1094)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1512:1512:1512) (1538:1538:1538)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (836:836:836) (854:854:854)) - (PORT datab (219:219:219) (261:261:261)) - (PORT datad (199:199:199) (256:256:256)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1347:1347:1347) (1329:1329:1329)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (1287:1287:1287) (1329:1329:1329)) - (PORT ena (1140:1140:1140) (1144:1144:1144)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (702:702:702)) - (PORT datab (813:813:813) (820:820:820)) - (PORT datad (802:802:802) (793:793:793)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (1287:1287:1287) (1330:1330:1330)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (1299:1299:1299) (1263:1263:1263)) - (PORT datab (1074:1074:1074) (1082:1082:1082)) - (PORT datad (218:218:218) (251:251:251)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (764:764:764) (758:758:758)) - (PORT datab (991:991:991) (1012:1012:1012)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1326:1326:1326) (1339:1339:1339)) - (PORT ena (906:906:906) (905:905:905)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1324:1324:1324) (1338:1338:1338)) - (PORT ena (893:893:893) (877:877:877)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (429:429:429) (477:477:477)) - (PORT datab (450:450:450) (481:481:481)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1262:1262:1262) (1284:1284:1284)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (871:871:871) (895:895:895)) - (PORT datab (1115:1115:1115) (1156:1156:1156)) - (PORT datad (827:827:827) (840:840:840)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1086:1086:1086) (1125:1125:1125)) - (PORT ena (1271:1271:1271) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1086:1086:1086) (1124:1124:1124)) - (PORT ena (1281:1281:1281) (1292:1292:1292)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (828:828:828) (885:885:885)) - (PORT datab (825:825:825) (893:893:893)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (363:363:363)) - (PORT datab (586:586:586) (607:607:607)) - (PORT datac (586:586:586) (597:597:597)) - (PORT datad (726:726:726) (777:777:777)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT asdata (1039:1039:1039) (1059:1059:1059)) - (PORT ena (857:857:857) (835:835:835)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (240:240:240)) - (PORT datab (374:374:374) (393:393:393)) - (PORT datad (364:364:364) (377:377:377)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1196:1196:1196) (1178:1178:1178)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (730:730:730) (777:777:777)) - (PORT datac (193:193:193) (259:259:259)) - (PORT datad (600:600:600) (600:600:600)) - (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -22026,902 +3725,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) + (INSTANCE z80_\|pla_decode_\|Equal55\~0) (DELAY (ABSOLUTE - (PORT dataa (576:576:576) (563:563:563)) - (PORT datab (843:843:843) (835:835:835)) - (PORT datac (213:213:213) (287:287:287)) - (PORT datad (539:539:539) (564:564:564)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) - (DELAY - (ABSOLUTE - (PORT datac (232:232:232) (309:309:309)) - (PORT datad (169:169:169) (199:199:199)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1287:1287:1287) (1338:1338:1338)) - (PORT ena (1164:1164:1164) (1167:1167:1167)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1347:1347:1347) (1329:1329:1329)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (1018:1018:1018) (1013:1013:1013)) - (PORT datab (817:817:817) (832:832:832)) - (PORT datad (611:611:611) (654:654:654)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (1879:1879:1879) (1893:1893:1893)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1533:1533:1533) (1489:1489:1489)) - (PORT datab (1071:1071:1071) (1076:1076:1076)) - (PORT datad (210:210:210) (243:243:243)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1017:1017:1017) (1055:1055:1055)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1093:1093:1093) (1070:1070:1070)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1300:1300:1300) (1335:1335:1335)) - (PORT ena (1173:1173:1173) (1169:1169:1169)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (408:408:408)) - (PORT datab (1474:1474:1474) (1477:1477:1477)) - (PORT datad (1095:1095:1095) (1089:1089:1089)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1647:1647:1647) (1670:1670:1670)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1288:1288:1288) (1337:1337:1337)) - (PORT ena (1039:1039:1039) (993:993:993)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (427:427:427)) - (PORT datab (808:808:808) (830:830:830)) - (PORT datad (339:339:339) (347:347:347)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (310:310:310) (329:329:329)) - (PORT datac (736:736:736) (718:718:718)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1322:1322:1322) (1359:1359:1359)) - (PORT ena (893:893:893) (877:877:877)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1323:1323:1323) (1361:1361:1361)) - (PORT ena (906:906:906) (905:905:905)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (473:473:473)) - (PORT datab (219:219:219) (287:287:287)) - (PORT datad (416:416:416) (454:454:454)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1580:1580:1580) (1596:1596:1596)) - (PORT ena (1281:1281:1281) (1292:1292:1292)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1581:1581:1581) (1599:1599:1599)) - (PORT ena (1271:1271:1271) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (892:892:892)) - (PORT datab (222:222:222) (291:291:291)) - (PORT datad (800:800:800) (850:850:850)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1621:1621:1621) (1650:1650:1650)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (866:866:866) (890:890:890)) - (PORT datab (1113:1113:1113) (1157:1157:1157)) - (PORT datad (830:830:830) (842:842:842)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (615:615:615)) - (PORT datab (761:761:761) (785:785:785)) - (PORT datac (572:572:572) (565:565:565)) - (PORT datad (773:773:773) (752:752:752)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (817:817:817) (861:861:861)) - (PORT datab (180:180:180) (211:211:211)) - (PORT datac (744:744:744) (776:776:776)) - (PORT datad (1208:1208:1208) (1193:1193:1193)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT asdata (1055:1055:1055) (1083:1083:1083)) - (PORT ena (857:857:857) (835:835:835)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (408:408:408)) - (PORT datab (198:198:198) (232:232:232)) - (PORT datad (354:354:354) (365:365:365)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1196:1196:1196) (1178:1178:1178)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (637:637:637)) - (PORT datab (348:348:348) (378:378:378)) - (PORT datac (195:195:195) (262:262:262)) + (PORT dataa (1606:1606:1606) (1653:1653:1653)) + (PORT datab (1510:1510:1510) (1635:1635:1635)) + (PORT datad (1659:1659:1659) (1723:1723:1723)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (530:530:530) (514:514:514)) - (PORT datab (791:791:791) (787:787:787)) - (PORT datac (633:633:633) (637:637:637)) - (PORT datad (159:159:159) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[13\]) + (INSTANCE z80_\|execute_\|ctl_mRead\~7) (DELAY (ABSOLUTE - (PORT datab (351:351:351) (381:381:381)) - (PORT datac (821:821:821) (822:822:822)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[13\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (312:312:312) (317:317:317)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1371:1371:1371)) - (PORT ena (1896:1896:1896) (1904:1904:1904)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) - (DELAY - (ABSOLUTE - (PORT datac (232:232:232) (309:309:309)) - (PORT datad (805:805:805) (797:797:797)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[15\]) - (DELAY - (ABSOLUTE - (PORT datac (333:333:333) (341:341:341)) - (PORT datad (803:803:803) (800:800:800)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1371:1371:1371)) - (PORT ena (1896:1896:1896) (1904:1904:1904)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) - (DELAY - (ABSOLUTE - (PORT dataa (260:260:260) (341:341:341)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (221:221:221) (291:291:291)) - (PORT datad (802:802:802) (798:798:798)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1196:1196:1196) (1178:1178:1178)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (2087:2087:2087) (2176:2176:2176)) - (PORT ena (906:906:906) (905:905:905)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (2087:2087:2087) (2177:2177:2177)) - (PORT ena (893:893:893) (877:877:877)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (472:472:472)) - (PORT datab (451:451:451) (487:487:487)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (1723:1723:1723) (1782:1782:1782)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (763:763:763) (739:739:739)) - (PORT datab (1074:1074:1074) (1081:1081:1081)) - (PORT datad (219:219:219) (254:254:254)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1085:1085:1085) (1135:1135:1135)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1949:1949:1949) (1996:1996:1996)) - (PORT ena (1039:1039:1039) (993:993:993)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (408:408:408)) - (PORT datab (809:809:809) (832:832:832)) - (PORT datad (339:339:339) (348:348:348)) + (PORT dataa (907:907:907) (950:950:950)) + (PORT datac (1218:1218:1218) (1276:1276:1276)) + (PORT datad (839:839:839) (848:848:848)) (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1324:1324:1324) (1348:1348:1348)) - (PORT ena (1173:1173:1173) (1169:1169:1169)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1324:1324:1324) (1348:1348:1348)) - (PORT ena (1093:1093:1093) (1070:1070:1070)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (1207:1207:1207) (1200:1200:1200)) - (PORT datab (1135:1135:1135) (1117:1117:1117)) - (PORT datad (195:195:195) (252:252:252)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1347:1347:1347) (1329:1329:1329)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1951:1951:1951) (1996:1996:1996)) - (PORT ena (1164:1164:1164) (1167:1167:1167)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (1019:1019:1019) (1008:1008:1008)) - (PORT datab (631:631:631) (669:669:669)) - (PORT datad (783:783:783) (794:794:794)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (559:559:559) (554:554:554)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (548:548:548) (544:544:544)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1096:1096:1096) (1141:1141:1141)) - (PORT ena (1271:1271:1271) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1097:1097:1097) (1141:1141:1141)) - (PORT ena (1281:1281:1281) (1292:1292:1292)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (890:890:890)) - (PORT datab (826:826:826) (887:887:887)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1992:1992:1992) (1966:1966:1966)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (872:872:872) (899:899:899)) - (PORT datab (1113:1113:1113) (1158:1158:1158)) - (PORT datad (825:825:825) (837:837:837)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (582:582:582)) - (PORT datab (585:585:585) (603:603:603)) - (PORT datac (460:460:460) (454:454:454)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -22929,919 +3753,55 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~84) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) (DELAY (ABSOLUTE - (PORT dataa (814:814:814) (859:859:859)) - (PORT datab (618:618:618) (614:614:614)) - (PORT datac (722:722:722) (755:755:755)) - (PORT datad (1211:1211:1211) (1194:1194:1194)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT asdata (1035:1035:1035) (1063:1063:1063)) - (PORT ena (857:857:857) (835:835:835)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (415:415:415)) - (PORT datab (199:199:199) (233:233:233)) - (PORT datad (351:351:351) (363:363:363)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (297:297:297)) - (PORT datab (620:620:620) (618:618:618)) - (PORT datad (600:600:600) (599:599:599)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (354:354:354)) - (PORT datab (659:659:659) (664:664:664)) - (PORT datac (758:758:758) (750:750:750)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[14\]) - (DELAY - (ABSOLUTE - (PORT dataa (848:848:848) (851:851:851)) - (PORT datac (334:334:334) (355:355:355)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[14\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (302:302:302) (296:296:296)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1371:1371:1371)) - (PORT ena (1896:1896:1896) (1904:1904:1904)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (1056:1056:1056) (1060:1060:1060)) - (PORT datab (374:374:374) (427:427:427)) - (PORT datac (1030:1030:1030) (991:991:991)) - (PORT datad (586:586:586) (589:589:589)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (194:194:194) (233:233:233)) - (PORT datac (209:209:209) (281:281:281)) - (PORT datad (316:316:316) (319:319:319)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (370:370:370)) - (PORT datab (660:660:660) (671:671:671)) - (PORT datac (762:762:762) (758:758:758)) - (PORT datad (514:514:514) (503:503:503)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (813:813:813) (866:866:866)) - (PORT datab (615:615:615) (626:626:626)) - (PORT datac (726:726:726) (751:751:751)) - (PORT datad (1207:1207:1207) (1198:1198:1198)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1175:1175:1175) (1203:1203:1203)) - (PORT datab (905:905:905) (909:909:909)) - (PORT datac (1722:1722:1722) (1740:1740:1740)) - (PORT datad (765:765:765) (752:752:752)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (187:187:187) (224:224:224)) - (PORT datab (231:231:231) (282:282:282)) - (PORT datac (1100:1100:1100) (1078:1078:1078)) - (PORT datad (870:870:870) (885:885:885)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (862:862:862)) - (PORT datab (1122:1122:1122) (1147:1147:1147)) - (PORT datac (839:839:839) (832:832:832)) - (PORT datad (1284:1284:1284) (1294:1294:1294)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (838:838:838)) - (PORT datab (614:614:614) (613:613:613)) - (PORT datac (614:614:614) (619:619:619)) - (PORT datad (621:621:621) (632:632:632)) + (PORT dataa (2475:2475:2475) (2459:2459:2459)) + (PORT datab (691:691:691) (713:713:713)) + (PORT datac (931:931:931) (942:942:942)) + (PORT datad (824:824:824) (829:829:829)) (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (947:947:947)) + (PORT datac (1000:1000:1000) (977:977:977)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) + (DELAY + (ABSOLUTE + (PORT datab (1427:1427:1427) (1496:1496:1496)) + (PORT datac (1102:1102:1102) (1138:1138:1138)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) (DELAY (ABSOLUTE - (PORT dataa (1407:1407:1407) (1450:1450:1450)) - (PORT datab (1289:1289:1289) (1361:1361:1361)) - (PORT datac (1297:1297:1297) (1317:1317:1317)) - (PORT datad (780:780:780) (770:770:770)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (564:564:564)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (176:176:176) (207:207:207)) - (PORT datad (1005:1005:1005) (1002:1002:1002)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1081:1081:1081) (1074:1074:1074)) - (PORT datab (912:912:912) (944:944:944)) - (PORT datac (190:190:190) (227:227:227)) - (PORT datad (1859:1859:1859) (1867:1867:1867)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (236:236:236)) - (PORT datab (589:589:589) (575:575:575)) - (PORT datac (561:561:561) (550:550:550)) - (PORT datad (568:568:568) (566:566:566)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~2) - (DELAY - (ABSOLUTE - (PORT datab (642:642:642) (672:672:672)) - (PORT datac (1228:1228:1228) (1212:1212:1212)) - (PORT datad (1061:1061:1061) (1068:1068:1068)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1568:1568:1568) (1604:1604:1604)) - (PORT datab (1366:1366:1366) (1410:1410:1410)) - (PORT datac (2377:2377:2377) (2403:2403:2403)) - (PORT datad (1740:1740:1740) (1778:1778:1778)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1788:1788:1788) (1824:1824:1824)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (842:842:842) (859:859:859)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (586:586:586) (608:608:608)) - (PORT datab (590:590:590) (598:598:598)) - (PORT datad (809:809:809) (830:830:830)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) - (DELAY - (ABSOLUTE - (PORT clk (1332:1332:1332) (1350:1350:1350)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1103:1103:1103) (1149:1149:1149)) - (PORT datab (231:231:231) (304:304:304)) - (PORT datac (1255:1255:1255) (1261:1261:1261)) - (PORT datad (1099:1099:1099) (1117:1117:1117)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (179:179:179) (212:212:212)) - (PORT datad (1079:1079:1079) (1113:1113:1113)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (200:200:200) (234:234:234)) - (PORT datac (822:822:822) (821:821:821)) - (PORT datad (1281:1281:1281) (1295:1295:1295)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (397:397:397)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (823:823:823) (829:829:829)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (459:459:459)) - (PORT datab (1065:1065:1065) (1077:1077:1077)) - (PORT datac (550:550:550) (577:577:577)) - (PORT datad (618:618:618) (634:634:634)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1093:1093:1093) (1092:1092:1092)) - (PORT datab (243:243:243) (309:309:309)) - (PORT datac (219:219:219) (274:274:274)) - (PORT datad (234:234:234) (271:271:271)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (320:320:320) (333:333:333)) - (PORT datab (749:749:749) (742:742:742)) - (PORT datac (463:463:463) (447:447:447)) - (PORT datad (1014:1014:1014) (1005:1005:1005)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (557:557:557) (567:567:567)) - (PORT datab (920:920:920) (930:930:930)) - (PORT datac (542:542:542) (538:538:538)) - (PORT datad (200:200:200) (239:239:239)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (361:361:361)) - (PORT datab (826:826:826) (839:839:839)) - (PORT datac (1063:1063:1063) (1038:1038:1038)) - (PORT datad (630:630:630) (650:650:650)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (676:676:676)) - (PORT datab (1072:1072:1072) (1089:1089:1089)) - (PORT datac (571:571:571) (605:605:605)) - (PORT datad (621:621:621) (641:641:641)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) - (DELAY - (ABSOLUTE - (PORT datab (249:249:249) (315:315:315)) - (PORT datad (229:229:229) (266:266:266)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (250:250:250) (308:308:308)) - (PORT datab (583:583:583) (570:570:570)) - (PORT datac (1062:1062:1062) (1058:1058:1058)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1361:1361:1361)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1177:1177:1177) (1162:1162:1162)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (893:893:893) (892:892:892)) - (PORT datac (1533:1533:1533) (1538:1538:1538)) - (PORT datad (1304:1304:1304) (1277:1277:1277)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1045:1045:1045) (1033:1033:1033)) - (PORT datab (1038:1038:1038) (1036:1036:1036)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (220:220:220) (254:254:254)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (487:487:487) (476:476:476)) - (PORT datab (820:820:820) (835:835:835)) - (PORT datac (884:884:884) (892:892:892)) - (PORT datad (554:554:554) (543:543:543)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1099:1099:1099) (1121:1121:1121)) - (PORT datab (575:575:575) (574:574:574)) - (PORT datac (171:171:171) (213:213:213)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (626:626:626)) - (PORT datab (858:858:858) (851:851:851)) - (PORT datac (795:795:795) (793:793:793)) - (PORT datad (1069:1069:1069) (1065:1065:1065)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (599:599:599)) - (PORT datab (897:897:897) (906:906:906)) - (PORT datac (1066:1066:1066) (1069:1069:1069)) - (PORT datad (202:202:202) (243:243:243)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (252:252:252)) - (PORT datab (1335:1335:1335) (1345:1345:1345)) - (PORT datac (1038:1038:1038) (1033:1033:1033)) - (PORT datad (163:163:163) (186:186:186)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1109:1109:1109) (1129:1129:1129)) - (PORT datab (871:871:871) (866:866:866)) - (PORT datac (499:499:499) (489:489:489)) - (PORT datad (778:778:778) (762:762:762)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1340:1340:1340) (1384:1384:1384)) - (PORT datab (199:199:199) (232:232:232)) - (PORT datac (209:209:209) (250:250:250)) - (PORT datad (1300:1300:1300) (1310:1310:1310)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT dataa (599:599:599) (593:593:593)) - (PORT datab (568:568:568) (581:581:581)) - (PORT datac (609:609:609) (615:615:615)) - (PORT datad (626:626:626) (639:639:639)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) - (DELAY - (ABSOLUTE - (PORT datab (567:567:567) (590:590:590)) - (PORT datad (734:734:734) (793:793:793)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla69M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (597:597:597)) - (PORT datab (2129:2129:2129) (2118:2118:2118)) - (PORT datac (1897:1897:1897) (1944:1944:1944)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (378:378:378)) - (PORT datab (1506:1506:1506) (1510:1510:1510)) - (PORT datac (771:771:771) (762:762:762)) - (PORT datad (163:163:163) (189:189:189)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (749:749:749) (788:788:788)) - (PORT datab (327:327:327) (353:353:353)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (166:166:166) (191:191:191)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (884:884:884)) - (PORT datab (639:639:639) (644:644:644)) - (PORT datac (528:528:528) (512:512:512)) - (PORT datad (567:567:567) (575:575:575)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_xf) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1353:1353:1353)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~33) - (DELAY - (ABSOLUTE - (PORT datab (881:881:881) (876:876:876)) - (PORT datac (584:584:584) (610:610:610)) - (PORT datad (607:607:607) (634:634:634)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (324:324:324) (334:334:334)) - (PORT datab (190:190:190) (226:226:226)) - (PORT datac (160:160:160) (192:192:192)) - (PORT datad (592:592:592) (607:607:607)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (820:820:820) (804:804:804)) - (PORT datab (920:920:920) (947:947:947)) - (PORT datac (1321:1321:1321) (1376:1376:1376)) - (PORT datad (1057:1057:1057) (1052:1052:1052)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (617:617:617)) - (PORT datab (855:855:855) (865:865:865)) - (PORT datac (1341:1341:1341) (1367:1367:1367)) - (PORT datad (1066:1066:1066) (1053:1053:1053)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (578:578:578)) - (PORT datab (187:187:187) (224:224:224)) - (PORT datac (820:820:820) (831:831:831)) - (PORT datad (176:176:176) (198:198:198)) + (PORT dataa (908:908:908) (950:950:950)) + (PORT datab (1342:1342:1342) (1352:1352:1352)) + (PORT datac (1221:1221:1221) (1276:1276:1276)) + (PORT datad (842:842:842) (847:847:847)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -23851,2510 +3811,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~17) (DELAY (ABSOLUTE - (PORT datab (1528:1528:1528) (1520:1520:1520)) - (PORT datac (1336:1336:1336) (1338:1338:1338)) - (PORT datad (1075:1075:1075) (1068:1068:1068)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (458:458:458)) - (PORT datab (1131:1131:1131) (1152:1152:1152)) - (PORT datac (1069:1069:1069) (1065:1065:1065)) - (PORT datad (845:845:845) (849:849:849)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (800:800:800) (812:812:812)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (806:806:806) (817:817:817)) - (PORT datad (580:580:580) (589:589:589)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (575:575:575)) - (PORT datab (221:221:221) (266:266:266)) - (PORT datac (1066:1066:1066) (1070:1070:1070)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (411:411:411) (450:450:450)) - (PORT datab (1071:1071:1071) (1055:1055:1055)) - (PORT datad (1350:1350:1350) (1340:1340:1340)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (392:392:392) (434:434:434)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (1501:1501:1501) (1461:1461:1461)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) - (DELAY - (ABSOLUTE - (PORT datab (331:331:331) (345:345:345)) - (PORT datac (731:731:731) (710:710:710)) - (PORT datad (301:301:301) (301:301:301)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (887:887:887) (908:908:908)) - (PORT ena (1297:1297:1297) (1275:1275:1275)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (887:887:887) (908:908:908)) - (PORT ena (1588:1588:1588) (1555:1555:1555)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (300:300:300)) - (PORT datab (891:891:891) (937:937:937)) - (PORT datad (786:786:786) (805:805:805)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (797:797:797) (781:781:781)) - (PORT ena (735:735:735) (733:733:733)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (797:797:797) (781:781:781)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (296:296:296)) - (PORT datab (231:231:231) (282:282:282)) - (PORT datad (207:207:207) (242:242:242)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (791:791:791) (771:771:771)) - (PORT datab (185:185:185) (219:219:219)) - (PORT datac (560:560:560) (567:567:567)) - (PORT datad (575:575:575) (587:587:587)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (794:794:794)) - (PORT datab (564:564:564) (570:570:570)) - (PORT datac (311:311:311) (318:318:318)) - (PORT datad (1035:1035:1035) (1014:1014:1014)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) - (PORT asdata (886:886:886) (890:890:890)) - (PORT ena (1105:1105:1105) (1078:1078:1078)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1236:1236:1236) (1213:1213:1213)) - (PORT datab (647:647:647) (665:665:665)) - (PORT datad (1107:1107:1107) (1126:1126:1126)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1384:1384:1384)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1175:1175:1175) (1170:1170:1170)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (561:561:561) (590:590:590)) - (PORT datac (647:647:647) (678:678:678)) - (PORT datad (201:201:201) (259:259:259)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (361:361:361)) - (PORT datab (884:884:884) (895:895:895)) - (PORT datac (628:628:628) (660:660:660)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[3\]) - (DELAY - (ABSOLUTE - (PORT datab (217:217:217) (259:259:259)) - (PORT datac (511:511:511) (501:501:501)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1384:1384:1384)) - (PORT asdata (794:794:794) (788:788:788)) - (PORT clrn (1409:1409:1409) (1380:1380:1380)) - (PORT ena (1969:1969:1969) (1997:1997:1997)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~4) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (384:384:384)) - (PORT datab (1063:1063:1063) (1066:1066:1066)) - (PORT datac (889:889:889) (916:916:916)) - (PORT datad (222:222:222) (282:282:282)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (346:346:346)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (318:318:318) (325:325:325)) - (PORT datad (304:304:304) (306:306:306)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (241:241:241) (315:315:315)) - (PORT datab (187:187:187) (224:224:224)) - (PORT datac (308:308:308) (318:318:318)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1136:1136:1136) (1120:1120:1120)) - (PORT ena (735:735:735) (733:733:733)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1133:1133:1133) (1116:1116:1116)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (295:295:295)) - (PORT datab (229:229:229) (280:280:280)) - (PORT datad (207:207:207) (240:240:240)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (591:591:591)) - (PORT datab (1063:1063:1063) (1050:1050:1050)) - (PORT datad (582:582:582) (589:589:589)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1104:1104:1104) (1087:1087:1087)) - (PORT ena (746:746:746) (759:759:759)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1108:1108:1108) (1092:1092:1092)) - (PORT ena (1154:1154:1154) (1142:1142:1142)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (421:421:421)) - (PORT datab (544:544:544) (554:554:554)) - (PORT datad (199:199:199) (257:257:257)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1381:1381:1381) (1365:1365:1365)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (873:873:873) (865:865:865)) - (PORT ena (1109:1109:1109) (1074:1074:1074)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (874:874:874) (867:867:867)) - (PORT ena (1155:1155:1155) (1140:1140:1140)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (444:444:444)) - (PORT datab (612:612:612) (626:626:626)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (595:595:595)) - (PORT datab (856:856:856) (860:860:860)) - (PORT datac (193:193:193) (258:258:258)) - (PORT datad (312:312:312) (313:313:313)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (917:917:917) (924:924:924)) - (PORT ena (1588:1588:1588) (1555:1555:1555)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (918:918:918) (926:926:926)) - (PORT ena (1297:1297:1297) (1275:1275:1275)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (813:813:813) (846:846:846)) - (PORT datab (881:881:881) (934:934:934)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (903:903:903) (902:902:902)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (901:901:901) (899:899:899)) - (PORT ena (1123:1123:1123) (1106:1106:1106)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (640:640:640)) - (PORT datab (372:372:372) (391:391:391)) - (PORT datad (196:196:196) (253:253:253)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (804:804:804) (785:785:785)) - (PORT ena (1295:1295:1295) (1246:1246:1246)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (500:500:500) (490:490:490)) - (PORT datad (763:763:763) (747:747:747)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (318:318:318) (332:332:332)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (945:945:945) (917:917:917)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (800:800:800) (794:794:794)) - (PORT datac (1018:1018:1018) (1017:1017:1017)) - (PORT datad (1076:1076:1076) (1075:1075:1075)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) - (PORT asdata (1258:1258:1258) (1240:1240:1240)) - (PORT ena (1105:1105:1105) (1078:1078:1078)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (823:823:823) (805:805:805)) - (PORT datab (1148:1148:1148) (1158:1158:1158)) - (PORT datad (609:609:609) (629:629:629)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1384:1384:1384)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1175:1175:1175) (1170:1170:1170)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (579:579:579) (601:601:601)) - (PORT datac (647:647:647) (676:676:676)) - (PORT datad (197:197:197) (255:255:255)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (361:361:361)) - (PORT datab (883:883:883) (898:898:898)) - (PORT datac (627:627:627) (663:663:663)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[4\]) - (DELAY - (ABSOLUTE - (PORT datab (215:215:215) (256:256:256)) - (PORT datad (489:489:489) (481:481:481)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1384:1384:1384)) - (PORT asdata (784:784:784) (765:765:765)) - (PORT clrn (1409:1409:1409) (1380:1380:1380)) - (PORT ena (1969:1969:1969) (1997:1997:1997)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT dataa (1068:1068:1068) (1057:1057:1057)) - (PORT datab (917:917:917) (925:925:925)) - (PORT datad (183:183:183) (207:207:207)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (680:680:680)) - (PORT datab (1067:1067:1067) (1069:1069:1069)) - (PORT datac (576:576:576) (586:586:586)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (816:816:816) (799:799:799)) - (PORT ena (1297:1297:1297) (1275:1275:1275)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (815:815:815) (801:801:801)) - (PORT ena (1588:1588:1588) (1555:1555:1555)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (295:295:295)) - (PORT datab (882:882:882) (936:936:936)) - (PORT datad (785:785:785) (805:805:805)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (634:634:634) (638:638:638)) - (PORT ena (1353:1353:1353) (1319:1319:1319)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (634:634:634) (635:635:635)) - (PORT ena (1145:1145:1145) (1131:1131:1131)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (1020:1020:1020) (1039:1039:1039)) - (PORT datab (220:220:220) (288:288:288)) - (PORT datad (604:604:604) (622:622:622)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1330:1330:1330) (1311:1311:1311)) - (PORT ena (1381:1381:1381) (1365:1365:1365)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1341:1341:1341) (1321:1321:1321)) - (PORT ena (1109:1109:1109) (1074:1074:1074)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (401:401:401) (436:436:436)) - (PORT datab (1062:1062:1062) (1044:1044:1044)) - (PORT datad (581:581:581) (571:571:571)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) - (DELAY - (ABSOLUTE - (PORT datab (854:854:854) (856:856:856)) - (PORT datad (315:315:315) (318:318:318)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1121:1121:1121) (1091:1091:1091)) - (PORT ena (746:746:746) (759:759:759)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1120:1120:1120) (1090:1090:1090)) - (PORT ena (1154:1154:1154) (1142:1142:1142)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (422:422:422)) - (PORT datab (545:545:545) (555:555:555)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1343:1343:1343) (1328:1328:1328)) - (PORT ena (1123:1123:1123) (1106:1106:1106)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (560:560:560) (554:554:554)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (599:599:599) (633:633:633)) - (PORT datab (366:366:366) (384:384:384)) - (PORT datad (196:196:196) (252:252:252)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (790:790:790) (780:780:780)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1295:1295:1295) (1246:1246:1246)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1342:1342:1342) (1323:1323:1323)) - (PORT ena (1155:1155:1155) (1140:1140:1140)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (529:529:529) (564:564:564)) - (PORT datab (769:769:769) (765:765:765)) - (PORT datad (591:591:591) (597:597:597)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (597:597:597)) - (PORT datab (1039:1039:1039) (1014:1014:1014)) - (PORT datac (313:313:313) (320:320:320)) - (PORT datad (542:542:542) (549:549:549)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (354:354:354)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (161:161:161) (183:183:183)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (621:621:621)) - (PORT datab (861:861:861) (871:871:871)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (1497:1497:1497) (1445:1445:1445)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) - (PORT asdata (1126:1126:1126) (1121:1121:1121)) - (PORT ena (1105:1105:1105) (1078:1078:1078)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1092:1092:1092) (1090:1090:1090)) - (PORT datab (1149:1149:1149) (1158:1158:1158)) - (PORT datad (610:610:610) (629:629:629)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (735:735:735) (733:733:733)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (249:249:249)) - (PORT datac (562:562:562) (576:576:576)) - (PORT datad (199:199:199) (257:257:257)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (601:601:601)) - (PORT datab (1245:1245:1245) (1193:1193:1193)) - (PORT datac (174:174:174) (204:204:204)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[5\]) - (DELAY - (ABSOLUTE - (PORT datac (606:606:606) (623:623:623)) - (PORT datad (770:770:770) (749:749:749)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1370:1370:1370)) - (PORT ena (1981:1981:1981) (2010:2010:2010)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~4) - (DELAY - (ABSOLUTE - (PORT dataa (843:843:843) (881:881:881)) - (PORT datab (1064:1064:1064) (1061:1061:1061)) - (PORT datac (886:886:886) (910:910:910)) - (PORT datad (335:335:335) (347:347:347)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (619:619:619)) - (PORT datab (1066:1066:1066) (1068:1068:1068)) - (PORT datac (751:751:751) (759:759:759)) - (PORT datad (564:564:564) (573:573:573)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1384:1384:1384)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1175:1175:1175) (1170:1170:1170)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (1549:1549:1549) (1512:1512:1512)) - (PORT ena (1588:1588:1588) (1555:1555:1555)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1237:1237:1237) (1208:1208:1208)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1297:1297:1297) (1275:1275:1275)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (808:808:808) (843:843:843)) - (PORT datab (882:882:882) (933:933:933)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (1744:1744:1744) (1690:1690:1690)) - (PORT ena (1353:1353:1353) (1319:1319:1319)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (1742:1742:1742) (1687:1687:1687)) - (PORT ena (1145:1145:1145) (1131:1131:1131)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (1017:1017:1017) (1038:1038:1038)) - (PORT datab (220:220:220) (289:289:289)) - (PORT datad (601:601:601) (620:620:620)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1991:1991:1991) (1931:1931:1931)) - (PORT ena (1132:1132:1132) (1112:1112:1112)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (971:971:971) (951:951:951)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (420:420:420)) - (PORT datab (585:585:585) (612:612:612)) - (PORT datad (346:346:346) (387:387:387)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1342:1342:1342) (1311:1311:1311)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (679:679:679)) - (PORT datab (881:881:881) (880:880:880)) - (PORT datac (813:813:813) (804:804:804)) - (PORT datad (564:564:564) (571:571:571)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1992:1992:1992) (1930:1930:1930)) - (PORT ena (1380:1380:1380) (1365:1365:1365)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1208:1208:1208) (1166:1166:1166)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1155:1155:1155) (1140:1140:1140)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1485:1485:1485) (1445:1445:1445)) - (PORT ena (1109:1109:1109) (1074:1074:1074)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (444:444:444)) - (PORT datab (220:220:220) (289:289:289)) - (PORT datad (586:586:586) (594:594:594)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) - (DELAY - (ABSOLUTE - (PORT datab (1303:1303:1303) (1285:1285:1285)) - (PORT datad (522:522:522) (515:515:515)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) - (DELAY - (ABSOLUTE - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1242:1242:1242) (1213:1213:1213)) - (PORT ena (746:746:746) (759:759:759)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1317:1317:1317) (1303:1303:1303)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (386:386:386) (426:426:426)) - (PORT datab (537:537:537) (544:544:544)) - (PORT datad (773:773:773) (790:790:790)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (357:357:357)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (736:736:736) (706:706:706)) - (PORT datad (717:717:717) (689:689:689)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (550:550:550) (577:577:577)) - (PORT datab (620:620:620) (634:634:634)) - (PORT datac (1289:1289:1289) (1259:1259:1259)) - (PORT datad (554:554:554) (550:550:550)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) - (PORT asdata (900:900:900) (912:912:912)) - (PORT ena (1105:1105:1105) (1078:1078:1078)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1228:1228:1228) (1220:1220:1220)) - (PORT datab (1145:1145:1145) (1153:1153:1153)) - (PORT datad (604:604:604) (628:628:628)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (634:634:634) (641:641:641)) - (PORT datac (611:611:611) (663:663:663)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (695:695:695)) - (PORT datab (598:598:598) (620:620:620)) - (PORT datac (853:853:853) (867:867:867)) - (PORT datad (555:555:555) (576:576:576)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[6\]) - (DELAY - (ABSOLUTE - (PORT datac (606:606:606) (624:624:624)) - (PORT datad (759:759:759) (749:749:749)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1370:1370:1370)) - (PORT ena (1981:1981:1981) (2010:2010:2010)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (600:600:600)) - (PORT datab (583:583:583) (601:601:601)) - (PORT datac (749:749:749) (757:757:757)) - (PORT datad (1076:1076:1076) (1064:1064:1064)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (1063:1063:1063) (1063:1063:1063)) - (PORT datac (578:578:578) (590:590:590)) - (PORT datad (565:565:565) (573:573:573)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (397:397:397) (459:459:459)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (686:686:686)) - (PORT datab (886:886:886) (899:899:899)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (573:573:573) (580:580:580)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (1115:1115:1115) (1112:1112:1112)) - (PORT ena (1353:1353:1353) (1319:1319:1319)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (1114:1114:1114) (1114:1114:1114)) - (PORT ena (1145:1145:1145) (1131:1131:1131)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (1018:1018:1018) (1038:1038:1038)) - (PORT datab (221:221:221) (291:291:291)) - (PORT datad (602:602:602) (623:623:623)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (1299:1299:1299) (1274:1274:1274)) - (PORT ena (1588:1588:1588) (1555:1555:1555)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (1299:1299:1299) (1276:1276:1276)) - (PORT ena (1297:1297:1297) (1275:1275:1275)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (814:814:814) (848:848:848)) - (PORT datab (881:881:881) (927:927:927)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1782:1782:1782) (1748:1748:1748)) - (PORT ena (1132:1132:1132) (1112:1112:1112)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1496:1496:1496) (1460:1460:1460)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (419:419:419)) - (PORT datab (585:585:585) (612:612:612)) - (PORT datad (342:342:342) (382:382:382)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1781:1781:1781) (1748:1748:1748)) - (PORT ena (1380:1380:1380) (1365:1365:1365)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1795:1795:1795) (1766:1766:1766)) - (PORT ena (1155:1155:1155) (1140:1140:1140)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1795:1795:1795) (1766:1766:1766)) - (PORT ena (1109:1109:1109) (1074:1074:1074)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (401:401:401) (436:436:436)) - (PORT datab (220:220:220) (287:287:287)) - (PORT datad (587:587:587) (591:591:591)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) - (DELAY - (ABSOLUTE - (PORT datab (1303:1303:1303) (1287:1287:1287)) - (PORT datad (543:543:543) (535:535:535)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1602:1602:1602) (1574:1574:1574)) - (PORT ena (746:746:746) (759:759:759)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1600:1600:1600) (1576:1576:1576)) - (PORT ena (1154:1154:1154) (1142:1142:1142)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (381:381:381) (422:422:422)) - (PORT datab (544:544:544) (553:553:553)) - (PORT datad (197:197:197) (252:252:252)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1342:1342:1342) (1311:1311:1311)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (648:648:648)) - (PORT datab (881:881:881) (883:883:883)) - (PORT datac (778:778:778) (757:757:757)) - (PORT datad (562:562:562) (569:569:569)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (462:462:462) (448:448:448)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (340:340:340) (346:346:346)) - (PORT datad (532:532:532) (520:520:520)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~92) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (641:641:641)) - (PORT datab (615:615:615) (627:627:627)) - (PORT datac (1288:1288:1288) (1258:1258:1258)) - (PORT datad (553:553:553) (552:552:552)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[7\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1379:1379:1379) (1380:1380:1380)) - (PORT datab (1534:1534:1534) (1526:1526:1526)) - (PORT datac (807:807:807) (810:810:810)) - (PORT datad (1078:1078:1078) (1071:1071:1071)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im2) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1361:1361:1361)) - (PORT ena (1156:1156:1156) (1147:1147:1147)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (325:325:325) (451:451:451)) - (PORT datac (1130:1130:1130) (1175:1175:1175)) - (PORT datad (250:250:250) (317:317:317)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (326:326:326) (453:453:453)) - (PORT datab (663:663:663) (674:674:674)) - (PORT datac (173:173:173) (204:204:204)) - (PORT datad (1201:1201:1201) (1270:1270:1270)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (813:813:813) (813:813:813)) - (PORT datab (862:862:862) (865:865:865)) - (PORT datac (573:573:573) (605:605:605)) - (PORT datad (589:589:589) (590:590:590)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (778:778:778) (765:765:765)) - (PORT datab (785:785:785) (798:798:798)) - (PORT datac (832:832:832) (840:840:840)) - (PORT datad (587:587:587) (633:633:633)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (224:224:224)) - (PORT datab (219:219:219) (262:262:262)) - (PORT datac (584:584:584) (609:609:609)) - (PORT datad (574:574:574) (563:563:563)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (662:662:662)) - (PORT datab (825:825:825) (837:837:837)) - (PORT datac (791:791:791) (766:766:766)) - (PORT datad (184:184:184) (210:210:210)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1159:1159:1159) (1215:1215:1215)) - (PORT datab (793:793:793) (816:816:816)) - (PORT datac (563:563:563) (574:574:574)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) - (DELAY - (ABSOLUTE - (PORT clk (1331:1331:1331) (1350:1350:1350)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (765:765:765) (779:779:779)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1352:1352:1352) (1422:1422:1422)) - (PORT datab (1360:1360:1360) (1401:1401:1401)) - (PORT datac (1021:1021:1021) (1041:1041:1041)) - (PORT datad (597:597:597) (607:607:607)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1042:1042:1042) (1037:1037:1037)) - (PORT datab (694:694:694) (696:696:696)) - (PORT datac (1298:1298:1298) (1313:1313:1313)) - (PORT datad (1097:1097:1097) (1118:1118:1118)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (899:899:899)) - (PORT datab (1077:1077:1077) (1086:1086:1086)) - (PORT datac (682:682:682) (744:744:744)) - (PORT datad (1745:1745:1745) (1842:1842:1842)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (717:717:717)) - (PORT datab (1288:1288:1288) (1362:1362:1362)) - (PORT datac (1032:1032:1032) (1024:1024:1024)) - (PORT datad (179:179:179) (212:212:212)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (593:593:593)) - (PORT datab (762:762:762) (741:741:741)) - (PORT datac (1037:1037:1037) (1041:1041:1041)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (617:617:617)) - (PORT datab (956:956:956) (977:977:977)) - (PORT datac (527:527:527) (511:511:511)) - (PORT datad (836:836:836) (845:845:845)) + (PORT dataa (1118:1118:1118) (1154:1154:1154)) + (PORT datab (586:586:586) (599:599:599)) + (PORT datac (1084:1084:1084) (1105:1105:1105)) + (PORT datad (1804:1804:1804) (1823:1823:1823)) (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -26362,47 +3827,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (INSTANCE z80_\|execute_\|fIOWrite\~0) (DELAY (ABSOLUTE - (PORT dataa (649:649:649) (659:659:659)) - (PORT datab (571:571:571) (563:563:563)) - (PORT datac (215:215:215) (282:282:282)) - (PORT datad (166:166:166) (193:193:193)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1043:1043:1043) (1037:1037:1037)) - (PORT datab (690:690:690) (692:692:692)) - (PORT datac (837:837:837) (854:854:854)) - (PORT datad (1098:1098:1098) (1095:1095:1095)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1337:1337:1337) (1338:1338:1338)) - (PORT datab (620:620:620) (638:638:638)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (1307:1307:1307) (1301:1301:1301)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (1120:1120:1120) (1175:1175:1175)) + (PORT datab (1273:1273:1273) (1347:1347:1347)) + (PORT datac (2079:2079:2079) (2115:2115:2115)) + (PORT datad (2221:2221:2221) (2289:2289:2289)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -26410,157 +3843,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) + (INSTANCE z80_\|execute_\|fMWrite\~6) (DELAY (ABSOLUTE - (PORT dataa (1325:1325:1325) (1320:1320:1320)) - (PORT datab (691:691:691) (692:692:692)) - (PORT datac (1053:1053:1053) (1064:1064:1064)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) - (DELAY - (ABSOLUTE - (PORT dataa (389:389:389) (441:441:441)) - (PORT datab (241:241:241) (316:316:316)) - (PORT datac (206:206:206) (278:278:278)) - (PORT datad (566:566:566) (580:580:580)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (808:808:808)) - (PORT datab (673:673:673) (721:721:721)) - (PORT datad (370:370:370) (403:403:403)) + (PORT dataa (746:746:746) (797:797:797)) + (PORT datab (1722:1722:1722) (1802:1802:1802)) + (PORT datac (303:303:303) (310:310:310)) + (PORT datad (1551:1551:1551) (1557:1557:1557)) (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (458:458:458)) - (PORT datab (357:357:357) (410:410:410)) - (PORT datac (611:611:611) (650:650:650)) - (PORT datad (624:624:624) (668:668:668)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (329:329:329)) - (PORT datab (559:559:559) (586:586:586)) - (PORT datac (217:217:217) (297:297:297)) - (PORT datad (344:344:344) (382:382:382)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) - (DELAY - (ABSOLUTE - (PORT dataa (546:546:546) (536:536:536)) - (PORT datab (840:840:840) (821:821:821)) - (PORT datac (523:523:523) (518:518:518)) - (PORT datad (287:287:287) (291:291:291)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1326:1326:1326) (1322:1322:1322)) - (PORT datab (1427:1427:1427) (1456:1456:1456)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1369:1369:1369)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1041:1041:1041) (1036:1036:1036)) - (PORT datab (619:619:619) (638:638:638)) - (PORT datac (838:838:838) (856:856:856)) - (PORT datad (1096:1096:1096) (1095:1095:1095)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) - (DELAY - (ABSOLUTE - (PORT dataa (907:907:907) (928:928:928)) - (PORT datab (247:247:247) (318:318:318)) - (PORT datac (1050:1050:1050) (1062:1062:1062)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -26568,202 +3859,59 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) + (INSTANCE z80_\|execute_\|ctl_mWrite\~8) (DELAY (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (691:691:691) (692:692:692)) - (PORT datac (1297:1297:1297) (1289:1289:1289)) - (PORT datad (221:221:221) (282:282:282)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (1244:1244:1244) (1260:1260:1260)) + (PORT datab (599:599:599) (621:621:621)) + (PORT datac (2053:2053:2053) (2071:2071:2071)) + (PORT datad (1859:1859:1859) (1881:1881:1881)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~5) (DELAY (ABSOLUTE - (PORT clk (1339:1339:1339) (1361:1361:1361)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1177:1177:1177) (1162:1162:1162)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (PORT dataa (1121:1121:1121) (1174:1174:1174)) + (PORT datab (1320:1320:1320) (1383:1383:1383)) + (PORT datac (2080:2080:2080) (2112:2112:2112)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) (DELAY (ABSOLUTE (PORT dataa (201:201:201) (238:238:238)) - (PORT datab (193:193:193) (234:234:234)) - (PORT datac (163:163:163) (198:198:198)) - (PORT datad (166:166:166) (190:190:190)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (507:507:507) (509:509:509)) - (PORT datab (192:192:192) (232:232:232)) - (PORT datac (160:160:160) (193:193:193)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (754:754:754) (727:727:727)) - (PORT datac (305:305:305) (316:316:316)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out) - (DELAY - (ABSOLUTE - (PORT dataa (326:326:326) (338:338:338)) - (PORT datab (616:616:616) (622:622:622)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1041:1041:1041) (1041:1041:1041)) - (PORT datab (1081:1081:1081) (1091:1091:1091)) - (PORT datac (1297:1297:1297) (1292:1292:1292)) - (PORT datad (1098:1098:1098) (1098:1098:1098)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) - (DELAY - (ABSOLUTE - (PORT dataa (868:868:868) (888:888:888)) - (PORT datab (694:694:694) (697:697:697)) - (PORT datac (592:592:592) (608:608:608)) + (PORT datab (335:335:335) (353:353:353)) + (PORT datac (756:756:756) (738:738:738)) (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (181:181:181) (215:215:215)) - (PORT datac (1280:1280:1280) (1286:1286:1286)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~10) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (229:229:229)) - (PORT datab (317:317:317) (327:327:327)) - (PORT datac (1118:1118:1118) (1119:1119:1119)) - (PORT datad (622:622:622) (636:636:636)) - (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1353:1353:1353)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) + (INSTANCE z80_\|execute_\|fMRead\~3) (DELAY (ABSOLUTE - (PORT dataa (839:839:839) (847:847:847)) - (PORT datab (1855:1855:1855) (1877:1877:1877)) - (PORT datac (839:839:839) (893:893:893)) - (PORT datad (786:786:786) (790:790:790)) + (PORT dataa (1537:1537:1537) (1557:1557:1557)) + (PORT datac (830:830:830) (840:840:840)) + (PORT datad (1280:1280:1280) (1312:1312:1312)) (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~2) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (402:402:402)) - (PORT datab (1089:1089:1089) (1066:1066:1066)) - (PORT datac (547:547:547) (540:540:540)) - (PORT datad (310:310:310) (323:323:323)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -26771,1901 +3919,95 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_12) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) (DELAY (ABSOLUTE - (PORT dataa (765:765:765) (773:773:773)) - (PORT datad (312:312:312) (317:317:317)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (253:253:253)) - (PORT datab (200:200:200) (243:243:243)) - (PORT datac (573:573:573) (573:573:573)) - (PORT datad (195:195:195) (234:234:234)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) - (DELAY - (ABSOLUTE - (PORT dataa (553:553:553) (539:539:539)) - (PORT datab (631:631:631) (626:626:626)) - (PORT datac (528:528:528) (512:512:512)) - (PORT datad (295:295:295) (288:288:288)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (573:573:573) (593:593:593)) - (PORT datab (599:599:599) (604:604:604)) - (PORT datac (217:217:217) (285:285:285)) - (PORT datad (360:360:360) (362:362:362)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (614:614:614)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (571:571:571) (575:575:575)) - (PORT datad (161:161:161) (183:183:183)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1141:1141:1141) (1119:1119:1119)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1504:1504:1504) (1518:1518:1518)) - (PORT datab (202:202:202) (237:237:237)) - (PORT datac (163:163:163) (197:197:197)) - (PORT datad (812:812:812) (852:852:852)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (674:674:674)) - (PORT datab (615:615:615) (632:632:632)) - (PORT datac (163:163:163) (198:198:198)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1678:1678:1678) (1708:1708:1708)) - (PORT datab (1857:1857:1857) (1879:1879:1879)) - (PORT datad (159:159:159) (180:180:180)) + (PORT dataa (1446:1446:1446) (1478:1478:1478)) + (PORT datab (1862:1862:1862) (1832:1832:1832)) + (PORT datac (1042:1042:1042) (1038:1038:1038)) + (PORT datad (180:180:180) (202:202:202)) (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|flags_cond_true) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1352:1352:1352)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) - (DELAY - (ABSOLUTE - (PORT dataa (585:585:585) (590:590:590)) - (PORT datab (1645:1645:1645) (1688:1688:1688)) - (PORT datac (1674:1674:1674) (1728:1728:1728)) - (PORT datad (517:517:517) (529:529:529)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (232:232:232)) - (PORT datab (207:207:207) (252:252:252)) - (PORT datac (530:530:530) (526:526:526)) - (PORT datad (164:164:164) (191:191:191)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) - (DELAY - (ABSOLUTE - (PORT dataa (827:827:827) (822:822:822)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datac (577:577:577) (585:585:585)) - (PORT datad (1103:1103:1103) (1114:1114:1114)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (593:593:593)) - (PORT datab (868:868:868) (890:890:890)) - (PORT datad (622:622:622) (629:629:629)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (598:598:598) (634:634:634)) - (PORT datab (490:490:490) (477:477:477)) - (PORT datac (692:692:692) (663:663:663)) - (PORT datad (1026:1026:1026) (1006:1006:1006)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (512:512:512) (511:511:511)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (538:538:538) (550:550:550)) - (PORT datad (582:582:582) (583:583:583)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (218:218:218)) - (PORT datab (236:236:236) (281:281:281)) - (PORT datac (558:558:558) (555:555:555)) - (PORT datad (208:208:208) (250:250:250)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1730:1730:1730) (1680:1680:1680)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1694:1694:1694) (1639:1639:1639)) - (PORT ena (1132:1132:1132) (1112:1112:1112)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (415:415:415)) - (PORT datab (350:350:350) (401:401:401)) - (PORT datad (558:558:558) (575:575:575)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1694:1694:1694) (1639:1639:1639)) - (PORT ena (1380:1380:1380) (1365:1365:1365)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1963:1963:1963) (1914:1914:1914)) - (PORT ena (1109:1109:1109) (1074:1074:1074)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1361:1361:1361)) - (PORT asdata (1965:1965:1965) (1916:1916:1916)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (402:402:402) (440:440:440)) - (PORT datab (612:612:612) (630:630:630)) - (PORT datad (588:588:588) (609:609:609)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (1303:1303:1303) (1283:1283:1283)) - (PORT datad (541:541:541) (532:532:532)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1730:1730:1730) (1679:1679:1679)) - (PORT ena (1123:1123:1123) (1106:1106:1106)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (628:628:628)) - (PORT datab (882:882:882) (879:879:879)) - (PORT datac (831:831:831) (826:826:826)) - (PORT datad (564:564:564) (571:571:571)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1498:1498:1498) (1466:1466:1466)) - (PORT ena (746:746:746) (759:759:759)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (764:764:764) (753:753:753)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1154:1154:1154) (1142:1142:1142)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (429:429:429)) - (PORT datab (537:537:537) (543:543:543)) - (PORT datad (544:544:544) (560:560:560)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (222:222:222)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (508:508:508) (497:497:497)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1422:1422:1422) (1371:1371:1371)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1297:1297:1297) (1275:1275:1275)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (1714:1714:1714) (1658:1658:1658)) - (PORT ena (1588:1588:1588) (1555:1555:1555)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (293:293:293)) - (PORT datab (881:881:881) (929:929:929)) - (PORT datad (789:789:789) (804:804:804)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (654:654:654) (660:660:660)) - (PORT ena (735:735:735) (733:733:733)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (654:654:654) (660:660:660)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (293:293:293)) - (PORT datab (233:233:233) (286:286:286)) - (PORT datad (213:213:213) (247:247:247)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (643:643:643)) - (PORT datab (590:590:590) (599:599:599)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1254:1254:1254) (1219:1219:1219)) - (PORT datab (577:577:577) (581:581:581)) - (PORT datac (590:590:590) (615:615:615)) - (PORT datad (288:288:288) (293:293:293)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1376:1376:1376) (1382:1382:1382)) - (PORT datab (1533:1533:1533) (1529:1529:1529)) - (PORT datac (1413:1413:1413) (1363:1363:1363)) - (PORT datad (1079:1079:1079) (1074:1074:1074)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (908:908:908) (909:909:909)) - (PORT datab (819:819:819) (814:814:814)) - (PORT datac (849:849:849) (861:861:861)) - (PORT datad (819:819:819) (821:821:821)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (640:640:640)) - (PORT datab (1060:1060:1060) (1067:1067:1067)) - (PORT datac (821:821:821) (860:860:860)) - (PORT datad (1088:1088:1088) (1085:1085:1085)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (223:223:223)) - (PORT datab (870:870:870) (873:873:873)) - (PORT datac (599:599:599) (602:602:602)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1209:1209:1209)) - (PORT datab (871:871:871) (867:867:867)) - (PORT datac (1329:1329:1329) (1335:1335:1335)) - (PORT datad (855:855:855) (872:872:872)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (187:187:187) (224:224:224)) - (PORT datab (913:913:913) (921:921:921)) - (PORT datac (838:838:838) (837:837:837)) - (PORT datad (199:199:199) (240:240:240)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1565:1565:1565) (1571:1571:1571)) - (PORT datac (827:827:827) (824:824:824)) - (PORT datad (341:341:341) (342:342:342)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (856:856:856) (855:855:855)) - (PORT datad (216:216:216) (246:246:246)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1096:1096:1096)) - (PORT datab (247:247:247) (312:312:312)) - (PORT datac (223:223:223) (279:279:279)) - (PORT datad (233:233:233) (269:269:269)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (398:398:398) (471:471:471)) - (PORT datab (1068:1068:1068) (1086:1086:1086)) - (PORT datac (1069:1069:1069) (1080:1080:1080)) - (PORT datad (615:615:615) (638:638:638)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1361:1361:1361)) - (PORT asdata (616:616:616) (621:621:621)) - (PORT ena (1177:1177:1177) (1162:1162:1162)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (585:585:585) (594:594:594)) - (PORT datab (343:343:343) (350:350:350)) - (PORT datad (1055:1055:1055) (1049:1049:1049)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (539:539:539) (539:539:539)) - (PORT datab (201:201:201) (234:234:234)) - (PORT datac (1038:1038:1038) (1019:1019:1019)) - (PORT datad (312:312:312) (313:313:313)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1170:1170:1170) (1202:1202:1202)) - (PORT datab (855:855:855) (828:828:828)) - (PORT datac (1037:1037:1037) (1036:1036:1036)) - (PORT datad (873:873:873) (892:892:892)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (896:896:896) (905:905:905)) - (PORT datac (754:754:754) (730:730:730)) - (PORT datad (204:204:204) (245:245:245)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (899:899:899) (897:897:897)) - (PORT datac (1538:1538:1538) (1534:1534:1534)) - (PORT datad (1302:1302:1302) (1274:1274:1274)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datac (831:831:831) (829:829:829)) - (PORT datad (219:219:219) (253:253:253)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1095:1095:1095)) - (PORT datab (248:248:248) (314:314:314)) - (PORT datac (225:225:225) (275:275:275)) - (PORT datad (226:226:226) (263:263:263)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (652:652:652)) - (PORT datab (1068:1068:1068) (1086:1086:1086)) - (PORT datac (566:566:566) (605:605:605)) - (PORT datad (615:615:615) (637:637:637)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1361:1361:1361)) - (PORT asdata (1037:1037:1037) (1004:1004:1004)) - (PORT ena (1177:1177:1177) (1162:1162:1162)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (511:511:511) (520:520:520)) - (PORT datab (308:308:308) (328:328:328)) - (PORT datad (1055:1055:1055) (1049:1049:1049)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (640:640:640)) - (PORT datab (335:335:335) (351:351:351)) - (PORT datac (741:741:741) (727:727:727)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (551:551:551) (536:536:536)) - (PORT datab (893:893:893) (917:917:917)) - (PORT datac (339:339:339) (363:363:363)) - (PORT datad (797:797:797) (815:815:815)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (633:633:633) (656:656:656)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (240:240:240) (310:310:310)) - (PORT datac (213:213:213) (279:279:279)) - (PORT datad (214:214:214) (271:271:271)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) - (DELAY - (ABSOLUTE - (PORT datac (792:792:792) (801:801:801)) - (PORT datad (625:625:625) (638:638:638)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (643:643:643)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datad (569:569:569) (563:563:563)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_hf2) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1353:1353:1353)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1092:1092:1092) (1097:1097:1097)) - (PORT datab (632:632:632) (626:626:626)) - (PORT datac (1043:1043:1043) (1070:1070:1070)) - (PORT datad (608:608:608) (650:650:650)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1107:1107:1107) (1114:1114:1114)) - (PORT datab (1529:1529:1529) (1523:1523:1523)) - (PORT datac (1336:1336:1336) (1338:1338:1338)) - (PORT datad (781:781:781) (791:791:791)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (610:610:610)) - (PORT datab (862:862:862) (866:866:866)) - (PORT datac (572:572:572) (606:606:606)) - (PORT datad (779:779:779) (767:767:767)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (774:774:774) (759:759:759)) - (PORT datab (838:838:838) (834:834:834)) - (PORT datac (386:386:386) (421:421:421)) - (PORT datad (771:771:771) (777:777:777)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (633:633:633) (636:636:636)) - (PORT datab (870:870:870) (873:873:873)) - (PORT datac (540:540:540) (538:538:538)) - (PORT datad (297:297:297) (297:297:297)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1180:1180:1180) (1213:1213:1213)) - (PORT datab (895:895:895) (908:908:908)) - (PORT datac (855:855:855) (841:841:841)) - (PORT datad (1429:1429:1429) (1463:1463:1463)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (578:578:578)) - (PORT datab (914:914:914) (921:921:921)) - (PORT datac (159:159:159) (191:191:191)) - (PORT datad (198:198:198) (239:239:239)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1562:1562:1562) (1566:1566:1566)) - (PORT datab (845:845:845) (834:834:834)) - (PORT datac (833:833:833) (828:828:828)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1329:1329:1329) (1313:1313:1313)) - (PORT datab (1038:1038:1038) (1037:1037:1037)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (214:214:214) (247:247:247)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (254:254:254)) - (PORT datab (223:223:223) (273:273:273)) - (PORT datac (574:574:574) (576:576:576)) - (PORT datad (785:785:785) (799:799:799)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (511:511:511) (516:516:516)) - (PORT datab (662:662:662) (684:684:684)) - (PORT datac (547:547:547) (541:541:541)) - (PORT datad (799:799:799) (812:812:812)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (637:637:637)) - (PORT datab (1034:1034:1034) (1055:1055:1055)) - (PORT datac (551:551:551) (541:541:541)) - (PORT datad (370:370:370) (411:411:411)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (310:310:310)) - (PORT datab (182:182:182) (216:216:216)) - (PORT datac (525:525:525) (514:514:514)) - (PORT datad (842:842:842) (871:871:871)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (428:428:428) (482:482:482)) - (PORT datab (595:595:595) (630:630:630)) - (PORT datac (1025:1025:1025) (1003:1003:1003)) - (PORT datad (618:618:618) (634:634:634)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1361:1361:1361)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1177:1177:1177) (1162:1162:1162)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (321:321:321) (330:330:330)) - (PORT datab (554:554:554) (558:558:558)) - (PORT datac (889:889:889) (901:901:901)) - (PORT datad (549:549:549) (571:571:571)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (250:250:250)) - (PORT datab (606:606:606) (599:599:599)) - (PORT datac (847:847:847) (864:864:864)) - (PORT datad (199:199:199) (239:239:239)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (239:239:239) (308:308:308)) - (PORT datab (559:559:559) (546:546:546)) - (PORT datac (535:535:535) (527:527:527)) - (PORT datad (833:833:833) (861:861:861)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (475:475:475)) - (PORT datab (647:647:647) (660:660:660)) - (PORT datac (802:802:802) (805:805:805)) - (PORT datad (380:380:380) (436:436:436)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (369:369:369)) - (PORT datab (369:369:369) (374:374:374)) - (PORT datac (161:161:161) (194:194:194)) - (PORT datad (325:325:325) (327:327:327)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (364:364:364)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (163:163:163) (197:197:197)) - (PORT datad (330:330:330) (335:335:335)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1092:1092:1092) (1091:1091:1091)) - (PORT datab (243:243:243) (308:308:308)) - (PORT datac (218:218:218) (274:274:274)) - (PORT datad (234:234:234) (271:271:271)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1567:1567:1567) (1566:1566:1566)) - (PORT datac (816:816:816) (808:808:808)) - (PORT datad (814:814:814) (823:823:823)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (848:848:848) (853:853:853)) - (PORT datad (216:216:216) (249:249:249)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (624:624:624)) - (PORT datab (1065:1065:1065) (1080:1080:1080)) - (PORT datac (386:386:386) (440:440:440)) - (PORT datad (617:617:617) (636:636:636)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (1030:1030:1030) (1049:1049:1049)) - (PORT datac (560:560:560) (551:551:551)) - (PORT datad (584:584:584) (585:585:585)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1166:1166:1166) (1201:1201:1201)) - (PORT datab (217:217:217) (269:269:269)) - (PORT datac (885:885:885) (895:895:895)) - (PORT datad (305:305:305) (313:313:313)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1174:1174:1174) (1204:1204:1204)) - (PORT datab (895:895:895) (906:906:906)) - (PORT datac (1476:1476:1476) (1517:1517:1517)) - (PORT datad (802:802:802) (796:796:796)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (599:599:599)) - (PORT datab (911:911:911) (924:924:924)) - (PORT datac (295:295:295) (308:308:308)) - (PORT datad (204:204:204) (246:246:246)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (410:410:410)) - (PORT datab (239:239:239) (308:308:308)) - (PORT datac (213:213:213) (280:280:280)) - (PORT datad (179:179:179) (201:201:201)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1091:1091:1091) (1094:1094:1094)) - (PORT datab (609:609:609) (601:601:601)) - (PORT datac (589:589:589) (613:613:613)) - (PORT datad (211:211:211) (277:277:277)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1065:1065:1065) (1068:1068:1068)) - (PORT datab (822:822:822) (846:846:846)) - (PORT datac (599:599:599) (610:610:610)) - (PORT datad (817:817:817) (808:808:808)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (856:856:856) (838:838:838)) - (PORT datac (1032:1032:1032) (1039:1039:1039)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (897:897:897) (902:902:902)) - (PORT datab (874:874:874) (880:880:880)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (817:817:817) (818:818:818)) - (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~22) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) (DELAY (ABSOLUTE - (PORT dataa (639:639:639) (638:638:638)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1481:1481:1481) (1435:1435:1435)) - (PORT datad (802:802:802) (786:786:786)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (2478:2478:2478) (2461:2461:2461)) + (PORT datab (948:948:948) (952:952:952)) + (PORT datac (734:734:734) (800:800:800)) + (PORT datad (654:654:654) (677:677:677)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) (DELAY (ABSOLUTE - (PORT dataa (594:594:594) (584:584:584)) - (PORT datab (1154:1154:1154) (1156:1156:1156)) - (PORT datac (1065:1065:1065) (1071:1071:1071)) - (PORT datad (315:315:315) (325:325:325)) + (PORT dataa (573:573:573) (559:559:559)) + (PORT datab (730:730:730) (752:752:752)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (159:159:159) (180:180:180)) (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) - (DELAY - (ABSOLUTE - (PORT datab (249:249:249) (313:313:313)) - (PORT datad (228:228:228) (264:264:264)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im1) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1361:1361:1361)) - (PORT ena (1156:1156:1156) (1147:1147:1147)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1132:1132:1132) (1144:1144:1144)) - (PORT datab (1113:1113:1113) (1145:1145:1145)) - (PORT datac (1126:1126:1126) (1169:1169:1169)) - (PORT datad (248:248:248) (311:311:311)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (443:443:443)) - (PORT datab (179:179:179) (212:212:212)) - (PORT datac (1067:1067:1067) (1059:1059:1059)) - (PORT datad (1086:1086:1086) (1100:1100:1100)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (940:940:940)) - (PORT datab (1082:1082:1082) (1085:1085:1085)) - (PORT datac (627:627:627) (642:642:642)) - (PORT datad (580:580:580) (596:596:596)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (806:806:806) (794:794:794)) - (PORT datac (873:873:873) (899:899:899)) - (PORT datad (195:195:195) (224:224:224)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1236:1236:1236)) - (PORT datab (1913:1913:1913) (2038:2038:2038)) - (PORT datac (758:758:758) (794:794:794)) - (PORT datad (845:845:845) (866:866:866)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (1172:1172:1172) (1168:1168:1168)) - (PORT datac (1298:1298:1298) (1286:1286:1286)) - (PORT datad (841:841:841) (874:874:874)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (218:218:218)) - (PORT datab (220:220:220) (254:254:254)) - (PORT datac (1794:1794:1794) (1850:1850:1850)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (818:818:818) (824:824:824)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (578:578:578) (585:585:585)) - (PORT datad (883:883:883) (899:899:899)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~37) - (DELAY - (ABSOLUTE - (PORT dataa (969:969:969) (985:985:985)) - (PORT datab (983:983:983) (994:994:994)) - (PORT datac (972:972:972) (942:942:942)) - (PORT datad (583:583:583) (575:575:575)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~55) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (946:946:946)) - (PORT datab (1050:1050:1050) (1021:1021:1021)) - (PORT datac (862:862:862) (936:936:936)) - (PORT datad (981:981:981) (970:970:970)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~38) - (DELAY - (ABSOLUTE - (PORT dataa (830:830:830) (822:822:822)) - (PORT datab (183:183:183) (217:217:217)) - (PORT datac (502:502:502) (489:489:489)) - (PORT datad (502:502:502) (495:495:495)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (627:627:627)) - (PORT datab (825:825:825) (839:839:839)) - (PORT datac (1827:1827:1827) (1808:1808:1808)) - (PORT datad (771:771:771) (749:749:749)) - (IOPATH dataa combout (267:267:267) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (905:905:905)) + (PORT datab (1094:1094:1094) (1112:1112:1112)) + (PORT datac (1746:1746:1746) (1751:1751:1751)) + (PORT datad (595:595:595) (593:593:593)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1555:1555:1555) (1577:1577:1577)) + (PORT datab (529:529:529) (518:518:518)) + (PORT datac (174:174:174) (206:206:206)) + (PORT datad (326:326:326) (338:338:338)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (376:376:376)) + (PORT datab (853:853:853) (886:886:886)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (1016:1016:1016) (989:989:989)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -28673,12 +4015,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~3) + (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) (DELAY (ABSOLUTE - (PORT datab (770:770:770) (793:793:793)) - (PORT datac (574:574:574) (598:598:598)) - (PORT datad (187:187:187) (216:216:216)) + (PORT datab (1267:1267:1267) (1333:1333:1333)) + (PORT datad (898:898:898) (935:935:935)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (588:588:588)) + (PORT datab (748:748:748) (794:794:794)) + (PORT datac (1608:1608:1608) (1628:1628:1628)) + (PORT datad (183:183:183) (210:210:210)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -28687,29 +4043,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~31) + (INSTANCE z80_\|execute_\|fMWrite\~7) (DELAY (ABSOLUTE - (PORT dataa (210:210:210) (253:253:253)) - (PORT datab (214:214:214) (257:257:257)) - (PORT datac (328:328:328) (343:343:343)) - (PORT datad (982:982:982) (974:974:974)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (711:711:711)) - (PORT datab (1492:1492:1492) (1462:1462:1462)) - (PORT datac (571:571:571) (584:584:584)) - (PORT datad (509:509:509) (507:507:507)) + (PORT dataa (1111:1111:1111) (1133:1133:1133)) + (PORT datab (743:743:743) (811:811:811)) + (PORT datac (735:735:735) (804:804:804)) + (PORT datad (824:824:824) (826:826:826)) (IOPATH dataa combout (307:307:307) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -28719,13 +4059,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~33) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) (DELAY (ABSOLUTE - (PORT datab (517:517:517) (515:515:515)) - (PORT datac (1224:1224:1224) (1208:1208:1208)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (1160:1160:1160) (1141:1141:1141)) + (PORT datac (965:965:965) (934:934:934)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -28733,92 +4075,88 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~35) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) (DELAY (ABSOLUTE - (PORT dataa (974:974:974) (964:964:964)) - (PORT datab (543:543:543) (527:527:527)) - (PORT datac (728:728:728) (703:703:703)) - (PORT datad (717:717:717) (688:688:688)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (804:804:804) (831:831:831)) + (PORT datab (182:182:182) (216:216:216)) + (PORT datac (177:177:177) (209:209:209)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1189:1189:1189) (1191:1191:1191)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~15) (DELAY (ABSOLUTE - (PORT datad (758:758:758) (781:781:781)) + (PORT dataa (594:594:594) (598:598:598)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (332:332:332) (342:342:342)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mrd) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1364:1364:1364)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1409:1409:1409) (1375:1375:1375)) - (PORT ena (1071:1071:1071) (1043:1043:1043)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + (PORT datab (1429:1429:1429) (1498:1498:1498)) + (PORT datac (1542:1542:1542) (1565:1565:1565)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) - (PORT asdata (1135:1135:1135) (1150:1150:1150)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1217:1217:1217) (1223:1223:1223)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~16) (DELAY (ABSOLUTE - (PORT dataa (848:848:848) (871:871:871)) - (PORT datad (196:196:196) (253:253:253)) - (IOPATH dataa combout (329:329:329) (332:332:332)) + (PORT dataa (1260:1260:1260) (1309:1309:1309)) + (PORT datab (199:199:199) (232:232:232)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (1112:1112:1112) (1185:1185:1185)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1785:1785:1785) (1881:1881:1881)) + (PORT datac (1081:1081:1081) (1098:1098:1098)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~0) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (267:267:267)) + (PORT datab (1434:1434:1434) (1483:1483:1483)) + (PORT datac (1567:1567:1567) (1609:1609:1609)) + (PORT datad (1224:1224:1224) (1189:1189:1189)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -28828,10 +4166,10 @@ (INSTANCE z80_\|execute_\|nextM\~4) (DELAY (ABSOLUTE - (PORT dataa (211:211:211) (254:254:254)) - (PORT datab (653:653:653) (703:703:703)) - (PORT datac (796:796:796) (805:805:805)) - (PORT datad (998:998:998) (1024:1024:1024)) + (PORT dataa (1408:1408:1408) (1385:1385:1385)) + (PORT datab (1098:1098:1098) (1122:1122:1122)) + (PORT datac (588:588:588) (603:603:603)) + (PORT datad (590:590:590) (613:613:613)) (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -28839,18 +4177,42 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT datac (949:949:949) (1021:1021:1021)) + (PORT datad (1172:1172:1172) (1211:1211:1211)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2139:2139:2139) (2190:2190:2190)) + (PORT datac (1244:1244:1244) (1363:1363:1363)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_iorw\~12) (DELAY (ABSOLUTE - (PORT dataa (1744:1744:1744) (1744:1744:1744)) - (PORT datab (1365:1365:1365) (1377:1377:1377)) - (PORT datac (1368:1368:1368) (1420:1420:1420)) - (PORT datad (1779:1779:1779) (1810:1810:1810)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (1736:1736:1736) (1797:1797:1797)) + (PORT datab (1491:1491:1491) (1581:1581:1581)) + (PORT datac (1356:1356:1356) (1359:1359:1359)) + (PORT datad (972:972:972) (995:995:995)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -28860,13 +4222,13 @@ (INSTANCE z80_\|execute_\|ctl_iorw\~8) (DELAY (ABSOLUTE - (PORT dataa (1021:1021:1021) (1058:1058:1058)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (180:180:180) (214:214:214)) - (PORT datad (631:631:631) (673:673:673)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (599:599:599) (595:595:595)) + (PORT datab (1265:1265:1265) (1228:1228:1228)) + (PORT datac (580:580:580) (584:584:584)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -28876,13 +4238,13 @@ (INSTANCE z80_\|execute_\|ctl_iorw\~9) (DELAY (ABSOLUTE - (PORT dataa (812:812:812) (798:798:798)) - (PORT datab (1077:1077:1077) (1094:1094:1094)) - (PORT datac (766:766:766) (763:763:763)) - (PORT datad (743:743:743) (727:727:727)) - (IOPATH dataa combout (329:329:329) (332:332:332)) + (PORT dataa (1095:1095:1095) (1097:1097:1097)) + (PORT datab (616:616:616) (630:630:630)) + (PORT datac (175:175:175) (207:207:207)) + (PORT datad (551:551:551) (557:557:557)) + (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -28892,10 +4254,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1378:1378:1378)) + (PORT clk (1341:1341:1341) (1362:1362:1362)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1189:1189:1189) (1191:1191:1191)) + (PORT clrn (1398:1398:1398) (1366:1366:1366)) + (PORT ena (1137:1137:1137) (1130:1130:1130)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -28905,43 +4267,15 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (201:201:201) (258:258:258)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1189:1189:1189) (1191:1191:1191)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorq) - (DELAY - (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) - (PORT asdata (525:525:525) (588:588:588)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1217:1217:1217) (1223:1223:1223)) + (PORT clk (1341:1341:1341) (1362:1362:1362)) + (PORT asdata (644:644:644) (684:684:684)) + (PORT clrn (1398:1398:1398) (1366:1366:1366)) + (PORT ena (1319:1319:1319) (1295:1295:1295)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -28951,15 +4285,43 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_iorq\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (601:601:601) (634:634:634)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorq) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1399:1399:1399) (1367:1367:1367)) + (PORT ena (1146:1146:1146) (1137:1137:1137)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) (DELAY (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) - (PORT asdata (511:511:511) (578:578:578)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1217:1217:1217) (1223:1223:1223)) + (PORT clk (1349:1349:1349) (1356:1356:1356)) + (PORT asdata (512:512:512) (577:577:577)) + (PORT clrn (1399:1399:1399) (1367:1367:1367)) + (PORT ena (1146:1146:1146) (1137:1137:1137)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -28974,8 +4336,8 @@ (INSTANCE z80_\|memory_ifc_\|iorq\~0) (DELAY (ABSOLUTE - (PORT datab (226:226:226) (298:298:298)) - (PORT datad (568:568:568) (588:588:588)) + (PORT datab (227:227:227) (296:296:296)) + (PORT datad (601:601:601) (632:632:632)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -28984,14 +4346,154 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~1) + (INSTANCE z80_\|pla_decode_\|Equal33\~2) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (239:239:239)) - (PORT datab (877:877:877) (922:922:922)) - (PORT datac (350:350:350) (355:355:355)) - (PORT datad (198:198:198) (220:220:220)) + (PORT dataa (1439:1439:1439) (1482:1482:1482)) + (PORT datac (1345:1345:1345) (1347:1347:1347)) + (PORT datad (1091:1091:1091) (1102:1102:1102)) (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~17) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (251:251:251)) + (PORT datab (201:201:201) (242:242:242)) + (PORT datac (904:904:904) (954:954:954)) + (PORT datad (1379:1379:1379) (1423:1423:1423)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1131:1131:1131) (1135:1135:1135)) + (PORT datab (1720:1720:1720) (1750:1750:1750)) + (PORT datac (949:949:949) (988:988:988)) + (PORT datad (945:945:945) (974:974:974)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1630:1630:1630) (1658:1658:1658)) + (PORT datab (618:618:618) (608:608:608)) + (PORT datad (1474:1474:1474) (1554:1554:1554)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~12) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (849:849:849)) + (PORT datab (1155:1155:1155) (1145:1145:1145)) + (PORT datac (772:772:772) (767:767:767)) + (PORT datad (170:170:170) (198:198:198)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~21) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (915:915:915)) + (PORT datab (923:923:923) (932:932:932)) + (PORT datac (1866:1866:1866) (1882:1882:1882)) + (PORT datad (1378:1378:1378) (1423:1423:1423)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~20) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (624:624:624)) + (PORT datab (1389:1389:1389) (1428:1428:1428)) + (PORT datac (1587:1587:1587) (1630:1630:1630)) + (PORT datad (584:584:584) (589:589:589)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (588:588:588)) + (PORT datab (1638:1638:1638) (1656:1656:1656)) + (PORT datac (837:837:837) (842:842:842)) + (PORT datad (536:536:536) (520:520:520)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (566:566:566)) + (PORT datab (601:601:601) (607:607:607)) + (PORT datac (1296:1296:1296) (1331:1331:1331)) + (PORT datad (1633:1633:1633) (1669:1669:1669)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~10) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (596:596:596)) + (PORT datab (1100:1100:1100) (1091:1091:1091)) + (PORT datac (845:845:845) (862:862:862)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -29000,31 +4502,75 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~2) + (INSTANCE z80_\|execute_\|ctl_mWrite\~13) (DELAY (ABSOLUTE - (PORT dataa (823:823:823) (813:813:813)) - (PORT datab (193:193:193) (235:235:235)) - (PORT datac (1101:1101:1101) (1087:1087:1087)) - (PORT datad (1018:1018:1018) (1021:1021:1021)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (585:585:585) (577:577:577)) + (PORT datab (1648:1648:1648) (1662:1662:1662)) + (PORT datac (793:793:793) (797:797:797)) + (PORT datad (165:165:165) (191:191:191)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~0) + (INSTANCE z80_\|execute_\|ixy_d\~9) (DELAY (ABSOLUTE - (PORT dataa (1748:1748:1748) (1738:1738:1738)) - (PORT datab (1405:1405:1405) (1431:1431:1431)) - (PORT datac (2026:2026:2026) (2020:2020:2020)) - (PORT datad (190:190:190) (219:219:219)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT datab (2396:2396:2396) (2501:2501:2501)) + (PORT datac (1871:1871:1871) (1915:1915:1915)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1550:1550:1550) (1564:1564:1564)) + (PORT datab (1539:1539:1539) (1529:1529:1529)) + (PORT datac (1247:1247:1247) (1224:1224:1224)) + (PORT datad (1044:1044:1044) (1047:1047:1047)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (880:880:880)) + (PORT datab (1138:1138:1138) (1170:1170:1170)) + (PORT datac (626:626:626) (666:666:666)) + (PORT datad (619:619:619) (648:648:648)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (687:687:687)) + (PORT datab (187:187:187) (222:222:222)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (1084:1084:1084) (1079:1079:1079)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -29032,17 +4578,237 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~3) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (237:237:237)) - (PORT datab (312:312:312) (331:331:331)) - (PORT datac (535:535:535) (526:526:526)) - (PORT datad (330:330:330) (340:340:340)) + (PORT dataa (1167:1167:1167) (1193:1193:1193)) + (PORT datab (1013:1013:1013) (1018:1018:1018)) + (PORT datac (1287:1287:1287) (1305:1305:1305)) + (PORT datad (177:177:177) (200:200:200)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1350:1350:1350) (1393:1393:1393)) + (PORT datab (1387:1387:1387) (1462:1462:1462)) + (PORT datac (1310:1310:1310) (1344:1344:1344)) + (PORT datad (1293:1293:1293) (1282:1282:1282)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~11) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (239:239:239)) + (PORT datab (592:592:592) (611:611:611)) + (PORT datac (1631:1631:1631) (1624:1624:1624)) + (PORT datad (606:606:606) (614:614:614)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~25) + (DELAY + (ABSOLUTE + (PORT datac (1102:1102:1102) (1136:1136:1136)) + (PORT datad (1113:1113:1113) (1099:1099:1099)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1354:1354:1354) (1398:1398:1398)) + (PORT datab (1077:1077:1077) (1044:1044:1044)) + (PORT datac (605:605:605) (616:616:616)) + (PORT datad (1359:1359:1359) (1428:1428:1428)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~24) + (DELAY + (ABSOLUTE + (PORT datac (1106:1106:1106) (1139:1139:1139)) + (PORT datad (1116:1116:1116) (1102:1102:1102)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (625:625:625) (617:617:617)) + (PORT datab (224:224:224) (262:262:262)) + (PORT datac (853:853:853) (861:861:861)) + (PORT datad (778:778:778) (766:766:766)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~14) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (859:859:859)) + (PORT datab (838:838:838) (840:840:840)) + (PORT datac (823:823:823) (821:821:821)) + (PORT datad (548:548:548) (544:544:544)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1304:1304:1304) (1392:1392:1392)) + (PORT datad (1125:1125:1125) (1163:1163:1163)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~16) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (595:595:595)) + (PORT datab (763:763:763) (763:763:763)) + (PORT datac (1019:1019:1019) (998:998:998)) + (PORT datad (2206:2206:2206) (2183:2183:2183)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1406:1406:1406) (1372:1372:1372)) + (PORT ena (1106:1106:1106) (1073:1073:1073)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (199:199:199) (257:257:257)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mwr) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1406:1406:1406) (1372:1372:1372)) + (PORT ena (1081:1081:1081) (1044:1044:1044)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|mwr_wr\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (812:812:812) (848:848:848)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|mwr_wr) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1399:1399:1399) (1367:1367:1367)) + (PORT ena (1146:1146:1146) (1137:1137:1137)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (246:246:246)) + (PORT datab (226:226:226) (295:295:295)) + (PORT datac (948:948:948) (966:966:966)) (IOPATH dataa combout (307:307:307) (280:280:280)) (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -29051,10 +4817,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff1) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1368:1368:1368)) + (PORT clk (1349:1349:1349) (1356:1356:1356)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1371:1371:1371)) - (PORT ena (1671:1671:1671) (1677:1677:1677)) + (PORT clrn (1399:1399:1399) (1367:1367:1367)) + (PORT ena (1146:1146:1146) (1137:1137:1137)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -29069,7 +4835,7 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1\~0) (DELAY (ABSOLUTE - (PORT datad (545:545:545) (566:566:566)) + (PORT datad (200:200:200) (256:256:256)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -29079,10 +4845,10 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1) (DELAY (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) + (PORT clk (1349:1349:1349) (1356:1356:1356)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1217:1217:1217) (1223:1223:1223)) + (PORT clrn (1399:1399:1399) (1367:1367:1367)) + (PORT ena (1146:1146:1146) (1137:1137:1137)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -29097,10 +4863,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff3) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1378:1378:1378)) - (PORT asdata (512:512:512) (579:579:579)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1189:1189:1189) (1191:1191:1191)) + (PORT clk (1342:1342:1342) (1363:1363:1363)) + (PORT asdata (510:510:510) (576:576:576)) + (PORT clrn (1399:1399:1399) (1367:1367:1367)) + (PORT ena (1171:1171:1171) (1166:1166:1166)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -29115,478 +4881,11 @@ (INSTANCE z80_\|memory_ifc_\|nRD_out\~0) (DELAY (ABSOLUTE - (PORT dataa (1338:1338:1338) (1362:1362:1362)) - (PORT datab (227:227:227) (299:299:299)) - (PORT datad (1375:1375:1375) (1395:1395:1395)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (312:312:312) (336:336:336)) - (PORT datab (331:331:331) (350:350:350)) - (PORT datac (957:957:957) (925:925:925)) - (PORT datad (165:165:165) (189:189:189)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1619:1619:1619) (1653:1653:1653)) - (PORT datab (1479:1479:1479) (1531:1531:1531)) - (PORT datac (1107:1107:1107) (1125:1125:1125)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2204:2204:2204) (2261:2261:2261)) - (PORT datad (935:935:935) (996:996:996)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~5) - (DELAY - (ABSOLUTE - (PORT datab (1235:1235:1235) (1290:1290:1290)) - (PORT datac (2660:2660:2660) (2719:2719:2719)) - (PORT datad (2283:2283:2283) (2440:2440:2440)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (361:361:361)) - (PORT datab (801:801:801) (795:795:795)) - (PORT datac (880:880:880) (918:918:918)) - (PORT datad (988:988:988) (949:949:949)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (914:914:914)) - (PORT datac (1100:1100:1100) (1137:1137:1137)) - (PORT datad (1867:1867:1867) (1908:1908:1908)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1350:1350:1350) (1340:1340:1340)) - (PORT datab (842:842:842) (882:882:882)) - (PORT datac (334:334:334) (340:340:340)) - (PORT datad (176:176:176) (197:197:197)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (658:658:658)) - (PORT datab (776:776:776) (772:772:772)) - (PORT datac (808:808:808) (793:793:793)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1151:1151:1151) (1196:1196:1196)) - (PORT datab (804:804:804) (788:788:788)) - (PORT datac (1202:1202:1202) (1187:1187:1187)) - (PORT datad (579:579:579) (611:611:611)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (218:218:218)) - (PORT datab (1011:1011:1011) (984:984:984)) - (PORT datac (342:342:342) (353:353:353)) - (PORT datad (1653:1653:1653) (1697:1697:1697)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~7) - (DELAY - (ABSOLUTE - (PORT datab (851:851:851) (867:867:867)) - (PORT datac (798:798:798) (800:800:800)) - (PORT datad (722:722:722) (701:701:701)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1398:1398:1398) (1438:1438:1438)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (1584:1584:1584) (1587:1587:1587)) - (PORT datad (811:811:811) (816:816:816)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1336:1336:1336) (1339:1339:1339)) - (PORT datab (1075:1075:1075) (1065:1065:1065)) - (PORT datac (828:828:828) (827:827:827)) - (PORT datad (722:722:722) (703:703:703)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1395:1395:1395) (1436:1436:1436)) - (PORT datab (1065:1065:1065) (1092:1092:1092)) - (PORT datac (1018:1018:1018) (1007:1007:1007)) - (PORT datad (562:562:562) (576:576:576)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1156:1156:1156) (1202:1202:1202)) - (PORT datab (797:797:797) (811:811:811)) - (PORT datac (1565:1565:1565) (1576:1576:1576)) - (PORT datad (238:238:238) (287:287:287)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1062:1062:1062) (1058:1058:1058)) - (PORT datab (192:192:192) (233:233:233)) - (PORT datac (174:174:174) (205:205:205)) - (PORT datad (576:576:576) (591:591:591)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (202:202:202) (237:237:237)) - (PORT datac (977:977:977) (948:948:948)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1014:1014:1014) (988:988:988)) - (PORT datab (798:798:798) (790:790:790)) - (PORT datac (562:562:562) (584:584:584)) - (PORT datad (1108:1108:1108) (1102:1102:1102)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (833:833:833) (846:846:846)) - (PORT datab (189:189:189) (222:222:222)) - (PORT datac (543:543:543) (535:535:535)) - (PORT datad (180:180:180) (202:202:202)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (310:310:310) (316:316:316)) - (PORT datad (755:755:755) (755:755:755)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~10) - (DELAY - (ABSOLUTE - (PORT dataa (823:823:823) (811:811:811)) - (PORT datab (959:959:959) (991:991:991)) - (PORT datac (1017:1017:1017) (1007:1007:1007)) - (PORT datad (1035:1035:1035) (1028:1028:1028)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (223:223:223)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (166:166:166) (190:190:190)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (536:536:536) (538:538:538)) - (PORT datab (1030:1030:1030) (1034:1034:1034)) - (PORT datac (1583:1583:1583) (1587:1587:1587)) - (PORT datad (161:161:161) (182:182:182)) + (PORT dataa (1039:1039:1039) (1034:1034:1034)) + (PORT datab (226:226:226) (295:295:295)) + (PORT datad (1281:1281:1281) (1269:1269:1269)) (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (650:650:650)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (574:574:574) (566:566:566)) - (PORT datad (178:178:178) (199:199:199)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (861:861:861) (857:857:857)) - (PORT datac (971:971:971) (1049:1049:1049)) - (PORT datad (1053:1053:1053) (1051:1051:1051)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|DFF_inst5\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (203:203:203) (264:264:264)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|DFF_inst5) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1374:1374:1374)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_iorqinta\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (208:208:208) (268:268:268)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) - (DELAY - (ABSOLUTE - (PORT clk (1356:1356:1356) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1374:1374:1374)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (514:514:514) (581:581:581)) - (PORT clrn (1408:1408:1408) (1374:1374:1374)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (305:305:305)) - (PORT datad (572:572:572) (576:576:576)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -29594,13 +4893,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal2\~0) + (INSTANCE z80_\|execute_\|ctl_mRead\~2) (DELAY (ABSOLUTE - (PORT dataa (1620:1620:1620) (1655:1655:1655)) - (PORT datab (1476:1476:1476) (1535:1535:1535)) - (PORT datac (1106:1106:1106) (1124:1124:1124)) - (PORT datad (1131:1131:1131) (1160:1160:1160)) + (PORT dataa (913:913:913) (979:979:979)) + (PORT datab (213:213:213) (252:252:252)) + (PORT datac (1004:1004:1004) (980:980:980)) + (PORT datad (1362:1362:1362) (1362:1362:1362)) (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -29610,13 +4909,289 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ExtRamWE\~0) + (INSTANCE z80_\|execute_\|fIORead\~0) (DELAY (ABSOLUTE - (PORT dataa (1619:1619:1619) (1653:1653:1653)) - (PORT datab (1479:1479:1479) (1531:1531:1531)) - (PORT datac (1107:1107:1107) (1125:1125:1125)) - (PORT datad (1130:1130:1130) (1159:1159:1159)) + (PORT dataa (1203:1203:1203) (1239:1239:1239)) + (PORT datab (859:859:859) (906:906:906)) + (PORT datac (1070:1070:1070) (1079:1079:1079)) + (PORT datad (1323:1323:1323) (1313:1313:1313)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1597:1597:1597) (1647:1647:1647)) + (PORT datab (1506:1506:1506) (1630:1630:1630)) + (PORT datac (957:957:957) (996:996:996)) + (PORT datad (1662:1662:1662) (1723:1723:1723)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~4) + (DELAY + (ABSOLUTE + (PORT datab (1487:1487:1487) (1576:1576:1576)) + (PORT datad (1709:1709:1709) (1762:1762:1762)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) + (DELAY + (ABSOLUTE + (PORT dataa (236:236:236) (283:283:283)) + (PORT datab (1540:1540:1540) (1662:1662:1662)) + (PORT datac (1184:1184:1184) (1265:1265:1265)) + (PORT datad (2637:2637:2637) (2640:2640:2640)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~1) + (DELAY + (ABSOLUTE + (PORT dataa (236:236:236) (283:283:283)) + (PORT datab (859:859:859) (906:906:906)) + (PORT datac (1069:1069:1069) (1079:1079:1079)) + (PORT datad (1624:1624:1624) (1620:1620:1620)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1050:1050:1050) (1048:1048:1048)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (1299:1299:1299) (1293:1293:1293)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1500:1500:1500) (1461:1461:1461)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (163:163:163) (198:198:198)) + (PORT datad (159:159:159) (178:178:178)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) + (DELAY + (ABSOLUTE + (PORT dataa (415:415:415) (459:459:459)) + (PORT datad (554:554:554) (560:560:560)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_im_we) + (DELAY + (ABSOLUTE + (PORT dataa (1358:1358:1358) (1365:1365:1365)) + (PORT datab (1332:1332:1332) (1322:1322:1322)) + (PORT datac (1245:1245:1245) (1363:1363:1363)) + (PORT datad (2346:2346:2346) (2359:2359:2359)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im2) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (893:893:893) (884:884:884)) + (PORT clrn (1396:1396:1396) (1368:1368:1368)) + (PORT ena (889:889:889) (877:877:877)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (298:298:298) (402:402:402)) + (PORT datab (795:795:795) (809:809:809)) + (PORT datad (240:240:240) (313:313:313)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1437:1437:1437) (1480:1480:1480)) + (PORT datab (236:236:236) (280:280:280)) + (PORT datac (1341:1341:1341) (1345:1345:1345)) + (PORT datad (1097:1097:1097) (1108:1108:1108)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1554:1554:1554) (1573:1573:1573)) + (PORT datab (217:217:217) (259:259:259)) + (PORT datac (1619:1619:1619) (1657:1657:1657)) + (PORT datad (742:742:742) (792:792:792)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (415:415:415) (440:440:440)) + (PORT datab (1176:1176:1176) (1203:1203:1203)) + (PORT datac (1234:1234:1234) (1231:1231:1231)) + (PORT datad (603:603:603) (609:609:609)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~31) + (DELAY + (ABSOLUTE + (PORT datab (604:604:604) (597:597:597)) + (PORT datac (795:795:795) (782:782:782)) + (PORT datad (799:799:799) (783:783:783)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (422:422:422) (455:455:455)) + (PORT datab (1557:1557:1557) (1576:1576:1576)) + (PORT datac (1699:1699:1699) (1776:1776:1776)) + (PORT datad (730:730:730) (769:769:769)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) + (DELAY + (ABSOLUTE + (PORT datab (1349:1349:1349) (1345:1345:1345)) + (PORT datac (1089:1089:1089) (1093:1093:1093)) + (PORT datad (1319:1319:1319) (1350:1350:1350)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal44\~0) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (753:753:753)) + (PORT datab (696:696:696) (742:742:742)) + (PORT datac (1684:1684:1684) (1774:1774:1774)) + (PORT datad (1557:1557:1557) (1563:1563:1563)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~6) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (834:834:834)) + (PORT datab (935:935:935) (980:980:980)) + (PORT datac (1341:1341:1341) (1347:1347:1347)) + (PORT datad (1383:1383:1383) (1430:1430:1430)) (IOPATH dataa combout (307:307:307) (280:280:280)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -29626,12 +5201,25858 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) + (INSTANCE z80_\|execute_\|fMRead\~5) (DELAY (ABSOLUTE - (PORT dataa (1673:1673:1673) (1606:1606:1606)) - (PORT datab (793:793:793) (773:773:773)) - (PORT datad (312:312:312) (319:319:319)) + (PORT dataa (846:846:846) (852:852:852)) + (PORT datab (813:813:813) (885:885:885)) + (PORT datac (979:979:979) (978:978:978)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~17) + (DELAY + (ABSOLUTE + (PORT datab (587:587:587) (614:614:614)) + (PORT datac (745:745:745) (737:737:737)) + (PORT datad (786:786:786) (792:792:792)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1437:1437:1437) (1483:1483:1483)) + (PORT datac (1341:1341:1341) (1348:1348:1348)) + (PORT datad (1095:1095:1095) (1108:1108:1108)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal49\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1371:1371:1371) (1378:1378:1378)) + (PORT datab (881:881:881) (916:916:916)) + (PORT datac (1105:1105:1105) (1111:1111:1111)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1130:1130:1130) (1100:1100:1100)) + (PORT datab (614:614:614) (623:623:623)) + (PORT datac (1539:1539:1539) (1535:1535:1535)) + (PORT datad (835:835:835) (864:864:864)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1660:1660:1660) (1708:1708:1708)) + (PORT datab (986:986:986) (1030:1030:1030)) + (PORT datac (1575:1575:1575) (1607:1607:1607)) + (PORT datad (199:199:199) (234:234:234)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal25\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1952:1952:1952) (2030:2030:2030)) + (PORT datab (2427:2427:2427) (2430:2430:2430)) + (PORT datac (1261:1261:1261) (1331:1331:1331)) + (PORT datad (812:812:812) (821:821:821)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2086:2086:2086) (2103:2103:2103)) + (PORT datab (208:208:208) (244:244:244)) + (PORT datac (572:572:572) (594:594:594)) + (PORT datad (932:932:932) (948:948:948)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) + (DELAY + (ABSOLUTE + (PORT datab (1476:1476:1476) (1476:1476:1476)) + (PORT datac (1114:1114:1114) (1140:1140:1140)) + (PORT datad (1029:1029:1029) (1014:1014:1014)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1215:1215:1215) (1262:1262:1262)) + (PORT datab (902:902:902) (889:889:889)) + (PORT datac (1271:1271:1271) (1381:1381:1381)) + (PORT datad (1104:1104:1104) (1099:1099:1099)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~16) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (834:834:834)) + (PORT datab (934:934:934) (979:979:979)) + (PORT datac (1346:1346:1346) (1352:1352:1352)) + (PORT datad (1377:1377:1377) (1422:1422:1422)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (769:769:769) (745:745:745)) + (PORT datab (559:559:559) (562:562:562)) + (PORT datac (1499:1499:1499) (1474:1474:1474)) + (PORT datad (1478:1478:1478) (1428:1428:1428)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (627:627:627)) + (PORT datac (1034:1034:1034) (1025:1025:1025)) + (PORT datad (730:730:730) (781:781:781)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal29\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1953:1953:1953) (2030:2030:2030)) + (PORT datab (629:629:629) (636:636:636)) + (PORT datac (980:980:980) (1006:1006:1006)) + (PORT datad (803:803:803) (792:792:792)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~38) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (359:359:359)) + (PORT datab (357:357:357) (376:376:376)) + (PORT datac (602:602:602) (637:637:637)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal35\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1322:1322:1322) (1290:1290:1290)) + (PORT datab (1773:1773:1773) (1782:1782:1782)) + (PORT datac (828:828:828) (852:852:852)) + (PORT datad (202:202:202) (238:238:238)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~33) + (DELAY + (ABSOLUTE + (PORT dataa (2849:2849:2849) (2861:2861:2861)) + (PORT datab (788:788:788) (790:790:790)) + (PORT datac (1333:1333:1333) (1397:1397:1397)) + (PORT datad (1833:1833:1833) (1840:1840:1840)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~1) + (DELAY + (ABSOLUTE + (PORT datab (1671:1671:1671) (1701:1701:1701)) + (PORT datad (2143:2143:2143) (2150:2150:2150)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (785:785:785) (831:831:831)) + (PORT datab (367:367:367) (377:377:377)) + (PORT datac (1620:1620:1620) (1657:1657:1657)) + (PORT datad (165:165:165) (188:188:188)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1100:1100:1100) (1121:1121:1121)) + (PORT datab (1637:1637:1637) (1660:1660:1660)) + (PORT datac (551:551:551) (557:557:557)) + (PORT datad (574:574:574) (580:580:580)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (814:814:814) (824:824:824)) + (PORT datac (860:860:860) (867:867:867)) + (PORT datad (541:541:541) (534:534:534)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1764:1764:1764) (1758:1758:1758)) + (PORT datab (1523:1523:1523) (1607:1607:1607)) + (PORT datac (569:569:569) (589:589:589)) + (PORT datad (1607:1607:1607) (1641:1641:1641)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~36) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (812:812:812)) + (PORT datab (320:320:320) (342:342:342)) + (PORT datac (1860:1860:1860) (1884:1884:1884)) + (PORT datad (1016:1016:1016) (987:987:987)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~14) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (249:249:249)) + (PORT datab (235:235:235) (280:280:280)) + (PORT datac (313:313:313) (326:326:326)) + (PORT datad (175:175:175) (207:207:207)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1083:1083:1083) (1086:1086:1086)) + (PORT datab (608:608:608) (606:606:606)) + (PORT datac (856:856:856) (883:883:883)) + (PORT datad (1058:1058:1058) (1075:1075:1075)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1554:1554:1554) (1578:1578:1578)) + (PORT datab (1260:1260:1260) (1253:1253:1253)) + (PORT datac (1618:1618:1618) (1659:1659:1659)) + (PORT datad (195:195:195) (230:230:230)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~39) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (571:571:571) (582:582:582)) + (PORT datad (774:774:774) (751:751:751)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1122:1122:1122) (1122:1122:1122)) + (PORT datab (337:337:337) (355:355:355)) + (PORT datac (1690:1690:1690) (1716:1716:1716)) + (PORT datad (552:552:552) (547:547:547)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2354:2354:2354) (2371:2371:2371)) + (PORT datab (2281:2281:2281) (2388:2388:2388)) + (PORT datad (1694:1694:1694) (1723:1723:1723)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1769:1769:1769) (1792:1792:1792)) + (PORT datab (840:840:840) (833:833:833)) + (PORT datac (1477:1477:1477) (1567:1567:1567)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1571:1571:1571) (1599:1599:1599)) + (PORT datab (1022:1022:1022) (1035:1035:1035)) + (PORT datac (829:829:829) (849:849:849)) + (PORT datad (200:200:200) (234:234:234)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (887:887:887)) + (PORT datab (1315:1315:1315) (1279:1279:1279)) + (PORT datac (571:571:571) (589:589:589)) + (PORT datad (757:757:757) (740:740:740)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1763:1763:1763) (1758:1758:1758)) + (PORT datab (1523:1523:1523) (1606:1606:1606)) + (PORT datac (569:569:569) (589:589:589)) + (PORT datad (1606:1606:1606) (1641:1641:1641)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (2078:2078:2078) (2098:2098:2098)) + (PORT datab (817:817:817) (813:813:813)) + (PORT datac (1449:1449:1449) (1527:1527:1527)) + (PORT datad (1563:1563:1563) (1582:1582:1582)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (820:820:820) (850:850:850)) + (PORT datab (1486:1486:1486) (1494:1494:1494)) + (PORT datac (1101:1101:1101) (1111:1111:1111)) + (PORT datad (1541:1541:1541) (1528:1528:1528)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (715:715:715)) + (PORT datab (1476:1476:1476) (1477:1477:1477)) + (PORT datac (1114:1114:1114) (1140:1140:1140)) + (PORT datad (1029:1029:1029) (1014:1014:1014)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1948:1948:1948) (2028:2028:2028)) + (PORT datab (1367:1367:1367) (1339:1339:1339)) + (PORT datac (1029:1029:1029) (1032:1032:1032)) + (PORT datad (588:588:588) (601:601:601)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~0) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (880:880:880)) + (PORT datab (516:516:516) (522:522:522)) + (PORT datac (524:524:524) (516:516:516)) + (PORT datad (531:531:531) (528:528:528)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~1) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (217:217:217)) + (PORT datab (200:200:200) (232:232:232)) + (PORT datac (155:155:155) (184:184:184)) + (PORT datad (200:200:200) (227:227:227)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (845:845:845)) + (PORT datab (647:647:647) (671:671:671)) + (PORT datac (1229:1229:1229) (1207:1207:1207)) + (PORT datad (1102:1102:1102) (1090:1090:1090)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (859:859:859)) + (PORT datab (1348:1348:1348) (1390:1390:1390)) + (PORT datac (813:813:813) (820:820:820)) + (PORT datad (196:196:196) (223:223:223)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (815:815:815) (816:816:816)) + (PORT datab (637:637:637) (677:677:677)) + (PORT datac (300:300:300) (310:310:310)) + (PORT datad (782:782:782) (796:796:796)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (629:629:629)) + (PORT datab (829:829:829) (844:844:844)) + (PORT datac (161:161:161) (193:193:193)) + (PORT datad (808:808:808) (810:810:810)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~1) + (DELAY + (ABSOLUTE + (PORT dataa (421:421:421) (447:447:447)) + (PORT datab (1020:1020:1020) (1003:1003:1003)) + (PORT datac (661:661:661) (717:717:717)) + (PORT datad (657:657:657) (710:710:710)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (575:575:575)) + (PORT datab (609:609:609) (624:624:624)) + (PORT datac (537:537:537) (527:527:527)) + (PORT datad (608:608:608) (626:626:626)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (806:806:806)) + (PORT datab (579:579:579) (559:559:559)) + (PORT datac (1390:1390:1390) (1397:1397:1397)) + (PORT datad (173:173:173) (204:204:204)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (838:838:838) (844:844:844)) + (PORT datac (529:529:529) (549:549:549)) + (PORT datad (158:158:158) (180:180:180)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~3) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (601:601:601)) + (PORT datab (1146:1146:1146) (1144:1144:1144)) + (PORT datad (816:816:816) (825:825:825)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1115:1115:1115) (1101:1101:1101)) + (PORT datab (583:583:583) (608:608:608)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (2206:2206:2206) (2183:2183:2183)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (762:762:762) (734:734:734)) + (PORT datab (555:555:555) (548:548:548)) + (PORT datac (776:776:776) (786:786:786)) + (PORT datad (915:915:915) (946:946:946)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1399:1399:1399) (1367:1367:1367)) + (PORT ena (1171:1171:1171) (1166:1166:1166)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (199:199:199) (256:256:256)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mrd) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1399:1399:1399) (1367:1367:1367)) + (PORT ena (1146:1146:1146) (1137:1137:1137)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (213:213:213) (279:279:279)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1399:1399:1399) (1367:1367:1367)) + (PORT ena (1146:1146:1146) (1137:1137:1137)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (303:303:303)) + (PORT datad (212:212:212) (278:278:278)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (229:229:229)) + (PORT datab (762:762:762) (763:763:763)) + (PORT datac (183:183:183) (219:219:219)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~1) + (DELAY + (ABSOLUTE + (PORT datab (1725:1725:1725) (1809:1809:1809)) + (PORT datac (2847:2847:2847) (2968:2968:2968)) + (PORT datad (2391:2391:2391) (2370:2370:2370)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_DAT\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (459:459:459) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (769:769:769) (767:767:767)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (335:335:335)) + (PORT datab (259:259:259) (342:342:342)) + (PORT datad (228:228:228) (301:301:301)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_CLK\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (459:459:459) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (2878:2878:2878) (3118:3118:3118)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1377:1377:1377) (1357:1357:1357)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (207:207:207) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1377:1377:1377) (1357:1357:1357)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (206:206:206) (266:266:266)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1377:1377:1377) (1357:1357:1357)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (207:207:207) (270:270:270)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1377:1377:1377) (1357:1357:1357)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (219:219:219) (277:277:277)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1377:1377:1377) (1357:1357:1357)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (307:307:307)) + (PORT datab (229:229:229) (300:300:300)) + (PORT datac (353:353:353) (394:394:394)) + (PORT datad (207:207:207) (267:267:267)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (206:206:206) (267:267:267)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1377:1377:1377) (1357:1357:1357)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (208:208:208) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1377:1377:1377) (1357:1357:1357)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (307:307:307)) + (PORT datab (183:183:183) (215:215:215)) + (PORT datac (202:202:202) (271:271:271)) + (PORT datad (208:208:208) (269:269:269)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (203:203:203) (272:272:272)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1377:1377:1377) (1357:1357:1357)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (308:308:308)) + (PORT datad (166:166:166) (192:192:192)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1377:1377:1377) (1357:1357:1357)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) + (DELAY + (ABSOLUTE + (PORT datab (190:190:190) (226:226:226)) + (PORT datac (204:204:204) (277:277:277)) + (PORT datad (200:200:200) (257:257:257)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1377:1377:1377) (1357:1357:1357)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1372:1372:1372) (1351:1351:1351)) + (PORT ena (1966:1966:1966) (2011:2011:2011)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (331:331:331)) + (PORT datab (250:250:250) (327:327:327)) + (PORT datad (228:228:228) (300:300:300)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1372:1372:1372) (1351:1351:1351)) + (PORT ena (1966:1966:1966) (2011:2011:2011)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) + (DELAY + (ABSOLUTE + (PORT dataa (248:248:248) (336:336:336)) + (PORT datab (261:261:261) (345:345:345)) + (PORT datad (225:225:225) (295:295:295)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1372:1372:1372) (1351:1351:1351)) + (PORT ena (1966:1966:1966) (2011:2011:2011)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (337:337:337)) + (PORT datab (258:258:258) (340:340:340)) + (PORT datad (222:222:222) (293:293:293)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1372:1372:1372) (1351:1351:1351)) + (PORT ena (1966:1966:1966) (2011:2011:2011)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (251:251:251) (334:334:334)) + (PORT datab (260:260:260) (343:343:343)) + (PORT datad (225:225:225) (294:294:294)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (251:251:251) (334:334:334)) + (PORT datab (250:250:250) (330:330:330)) + (PORT datac (356:356:356) (394:394:394)) + (PORT datad (2885:2885:2885) (3130:3130:3130)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (331:331:331)) + (PORT datab (188:188:188) (223:223:223)) + (PORT datac (1378:1378:1378) (1434:1434:1434)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1326:1326:1326) (1345:1345:1345)) + (PORT asdata (3179:3179:3179) (3438:3438:3438)) + (PORT clrn (1369:1369:1369) (1349:1349:1349)) + (PORT ena (1512:1512:1512) (1469:1469:1469)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1326:1326:1326) (1345:1345:1345)) + (PORT asdata (639:639:639) (682:682:682)) + (PORT clrn (1369:1369:1369) (1349:1349:1349)) + (PORT ena (1512:1512:1512) (1469:1469:1469)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1326:1326:1326) (1345:1345:1345)) + (PORT asdata (556:556:556) (650:650:650)) + (PORT clrn (1369:1369:1369) (1349:1349:1349)) + (PORT ena (1512:1512:1512) (1469:1469:1469)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1348:1348:1348)) + (PORT asdata (1195:1195:1195) (1234:1234:1234)) + (PORT clrn (1365:1365:1365) (1346:1346:1346)) + (PORT ena (1544:1544:1544) (1514:1514:1514)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1326:1326:1326) (1345:1345:1345)) + (PORT asdata (1143:1143:1143) (1183:1183:1183)) + (PORT clrn (1369:1369:1369) (1349:1349:1349)) + (PORT ena (1512:1512:1512) (1469:1469:1469)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1348:1348:1348)) + (PORT asdata (1231:1231:1231) (1282:1282:1282)) + (PORT clrn (1364:1364:1364) (1345:1345:1345)) + (PORT ena (1310:1310:1310) (1303:1303:1303)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1348:1348:1348)) + (PORT asdata (1089:1089:1089) (1101:1101:1101)) + (PORT clrn (1364:1364:1364) (1345:1345:1345)) + (PORT ena (1310:1310:1310) (1303:1303:1303)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1348:1348:1348)) + (PORT asdata (549:549:549) (628:628:628)) + (PORT clrn (1364:1364:1364) (1345:1345:1345)) + (PORT ena (1310:1310:1310) (1303:1303:1303)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1326:1326:1326) (1345:1345:1345)) + (PORT asdata (1169:1169:1169) (1199:1199:1199)) + (PORT clrn (1369:1369:1369) (1349:1349:1349)) + (PORT ena (1512:1512:1512) (1469:1469:1469)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (374:374:374)) + (PORT datab (861:861:861) (916:916:916)) + (PORT datac (227:227:227) (302:302:302)) + (PORT datad (873:873:873) (914:914:914)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (795:795:795)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (854:854:854) (890:890:890)) + (PORT datad (241:241:241) (306:306:306)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (382:382:382)) + (PORT datab (914:914:914) (947:947:947)) + (PORT datad (241:241:241) (306:306:306)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (893:893:893)) + (PORT datab (886:886:886) (920:920:920)) + (PORT datad (690:690:690) (760:760:760)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) + (DELAY + (ABSOLUTE + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (213:213:213) (280:280:280)) + (PORT datad (286:286:286) (291:291:291)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (627:627:627)) + (PORT datab (2920:2920:2920) (3163:3163:3163)) + (PORT datac (1379:1379:1379) (1434:1434:1434)) + (PORT datad (168:168:168) (194:194:194)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1372:1372:1372) (1351:1351:1351)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|released\~0) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (637:637:637)) + (PORT datab (808:808:808) (833:833:833)) + (PORT datad (647:647:647) (688:688:688)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|released) + (DELAY + (ABSOLUTE + (PORT clk (1326:1326:1326) (1345:1345:1345)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1368:1368:1368) (1348:1348:1348)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (706:706:706)) + (PORT datab (719:719:719) (793:793:793)) + (PORT datac (655:655:655) (717:717:717)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (721:721:721)) + (PORT datad (681:681:681) (732:732:732)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|extended\~0) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (640:640:640)) + (PORT datad (640:640:640) (679:679:679)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|extended) + (DELAY + (ABSOLUTE + (PORT clk (1326:1326:1326) (1345:1345:1345)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1368:1368:1368) (1348:1348:1348)) + (PORT ena (1363:1363:1363) (1376:1376:1376)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (265:265:265) (367:367:367)) + (PORT datab (635:635:635) (657:657:657)) + (PORT datac (831:831:831) (852:852:852)) + (PORT datad (243:243:243) (311:311:311)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (612:612:612)) + (PORT datab (704:704:704) (753:753:753)) + (PORT datac (164:164:164) (199:199:199)) + (PORT datad (1045:1045:1045) (1020:1020:1020)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (393:393:393)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1326:1326:1326) (1345:1345:1345)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1368:1368:1368) (1348:1348:1348)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|clrpc_int\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1757:1757:1757) (1867:1867:1867)) + (PORT datab (1390:1390:1390) (1410:1410:1410)) + (PORT datad (1075:1075:1075) (1122:1122:1122)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (312:312:312)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|clrpc_int) + (DELAY + (ABSOLUTE + (PORT clk (1361:1361:1361) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1712:1712:1712) (1681:1681:1681)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT datac (878:878:878) (897:897:897)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (206:206:206) (266:266:266)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1357:1357:1357)) + (PORT asdata (512:512:512) (579:579:579)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|clrpc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (663:663:663)) + (PORT datab (228:228:228) (300:300:300)) + (PORT datad (207:207:207) (267:267:267)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1175:1175:1175) (1231:1231:1231)) + (PORT datab (904:904:904) (957:957:957)) + (PORT datac (577:577:577) (604:604:604)) + (PORT datad (822:822:822) (821:821:821)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1769:1769:1769) (1790:1790:1790)) + (PORT datab (1100:1100:1100) (1090:1090:1090)) + (PORT datac (1480:1480:1480) (1567:1567:1567)) + (PORT datad (802:802:802) (795:795:795)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1769:1769:1769) (1790:1790:1790)) + (PORT datab (839:839:839) (830:830:830)) + (PORT datac (1480:1480:1480) (1567:1567:1567)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1766:1766:1766) (1793:1793:1793)) + (PORT datab (1619:1619:1619) (1580:1580:1580)) + (PORT datac (1477:1477:1477) (1564:1564:1564)) + (PORT datad (802:802:802) (798:798:798)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) + (DELAY + (ABSOLUTE + (PORT datab (223:223:223) (270:270:270)) + (PORT datac (224:224:224) (275:275:275)) + (PORT datad (224:224:224) (272:272:272)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (593:593:593)) + (PORT datac (1545:1545:1545) (1548:1548:1548)) + (PORT datad (1056:1056:1056) (1053:1053:1053)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (625:625:625)) + (PORT datac (582:582:582) (572:572:572)) + (PORT datad (1137:1137:1137) (1128:1128:1128)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (623:623:623)) + (PORT datab (1339:1339:1339) (1318:1318:1318)) + (PORT datac (546:546:546) (541:541:541)) + (PORT datad (1030:1030:1030) (1043:1043:1043)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (611:611:611)) + (PORT datab (872:872:872) (860:860:860)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (814:814:814) (809:809:809)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) + (DELAY + (ABSOLUTE + (PORT datab (1381:1381:1381) (1395:1395:1395)) + (PORT datac (1136:1136:1136) (1148:1148:1148)) + (PORT datad (1310:1310:1310) (1319:1319:1319)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1245:1245:1245) (1262:1262:1262)) + (PORT datab (1477:1477:1477) (1550:1550:1550)) + (PORT datac (572:572:572) (595:595:595)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1828:1828:1828) (1912:1912:1912)) + (PORT datab (2391:2391:2391) (2483:2483:2483)) + (PORT datad (1582:1582:1582) (1631:1631:1631)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1355:1355:1355) (1353:1353:1353)) + (PORT datab (905:905:905) (879:879:879)) + (PORT datac (806:806:806) (821:821:821)) + (PORT datad (847:847:847) (864:864:864)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) + (DELAY + (ABSOLUTE + (PORT dataa (2180:2180:2180) (2223:2223:2223)) + (PORT datac (1740:1740:1740) (1694:1694:1694)) + (PORT datad (1637:1637:1637) (1696:1696:1696)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (896:896:896) (904:904:904)) + (PORT datab (189:189:189) (225:225:225)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (163:163:163) (188:188:188)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1100:1100:1100) (1133:1133:1133)) + (PORT datab (590:590:590) (569:569:569)) + (PORT datac (831:831:831) (859:859:859)) + (PORT datad (802:802:802) (806:806:806)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (831:831:831) (824:824:824)) + (PORT datac (571:571:571) (589:589:589)) + (PORT datad (583:583:583) (587:587:587)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (803:803:803)) + (PORT datab (1408:1408:1408) (1461:1461:1461)) + (PORT datac (576:576:576) (603:603:603)) + (PORT datad (1136:1136:1136) (1126:1126:1126)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (216:216:216)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (165:165:165) (203:203:203)) + (PORT datad (1151:1151:1151) (1165:1165:1165)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~13) + (DELAY + (ABSOLUTE + (PORT datab (2531:2531:2531) (2628:2628:2628)) + (PORT datac (1599:1599:1599) (1628:1628:1628)) + (PORT datad (774:774:774) (770:770:770)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1454:1454:1454) (1517:1517:1517)) + (PORT datab (1859:1859:1859) (1914:1914:1914)) + (PORT datac (2041:2041:2041) (2037:2037:2037)) + (PORT datad (1626:1626:1626) (1655:1655:1655)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1634:1634:1634) (1685:1685:1685)) + (PORT datab (332:332:332) (347:347:347)) + (PORT datac (1716:1716:1716) (1692:1692:1692)) + (PORT datad (1470:1470:1470) (1561:1561:1561)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~16) + (DELAY + (ABSOLUTE + (PORT dataa (2173:2173:2173) (2248:2248:2248)) + (PORT datab (1040:1040:1040) (1047:1047:1047)) + (PORT datac (1429:1429:1429) (1486:1486:1486)) + (PORT datad (1837:1837:1837) (1881:1881:1881)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) + (DELAY + (ABSOLUTE + (PORT dataa (818:818:818) (829:829:829)) + (PORT datab (776:776:776) (773:773:773)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (1512:1512:1512) (1536:1536:1536)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (260:260:260)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (597:597:597) (630:630:630)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1067:1067:1067) (1096:1096:1096)) + (PORT datab (798:798:798) (783:783:783)) + (PORT datac (1086:1086:1086) (1106:1106:1106)) + (PORT datad (824:824:824) (829:829:829)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1421:1421:1421) (1415:1415:1415)) + (PORT datab (1026:1026:1026) (1006:1006:1006)) + (PORT datac (1592:1592:1592) (1604:1604:1604)) + (PORT datad (1088:1088:1088) (1092:1092:1092)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1419:1419:1419) (1413:1413:1413)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (1164:1164:1164) (1198:1198:1198)) + (PORT datad (1086:1086:1086) (1102:1102:1102)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~2) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (318:318:318)) + (PORT datab (225:225:225) (270:270:270)) + (PORT datac (220:220:220) (272:272:272)) + (PORT datad (1331:1331:1331) (1314:1314:1314)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (559:559:559)) + (PORT datab (795:795:795) (770:770:770)) + (PORT datac (346:346:346) (351:351:351)) + (PORT datad (828:828:828) (850:850:850)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (551:551:551)) + (PORT datab (204:204:204) (241:241:241)) + (PORT datac (1034:1034:1034) (1034:1034:1034)) + (PORT datad (821:821:821) (839:839:839)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1027:1027:1027) (1035:1035:1035)) + (PORT datab (207:207:207) (245:245:245)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal56\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1022:1022:1022) (1047:1047:1047)) + (PORT datab (1855:1855:1855) (1879:1879:1879)) + (PORT datac (1265:1265:1265) (1338:1338:1338)) + (PORT datad (1740:1740:1740) (1736:1736:1736)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1552:1552:1552) (1573:1573:1573)) + (PORT datab (609:609:609) (596:596:596)) + (PORT datac (1619:1619:1619) (1656:1656:1656)) + (PORT datad (973:973:973) (996:996:996)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1554:1554:1554) (1577:1577:1577)) + (PORT datab (609:609:609) (598:598:598)) + (PORT datac (1618:1618:1618) (1661:1661:1661)) + (PORT datad (971:971:971) (997:997:997)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1129:1129:1129) (1106:1106:1106)) + (PORT datab (828:828:828) (835:835:835)) + (PORT datac (875:875:875) (900:900:900)) + (PORT datad (871:871:871) (878:878:878)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (387:387:387)) + (PORT datab (882:882:882) (865:865:865)) + (PORT datac (546:546:546) (559:559:559)) + (PORT datad (203:203:203) (230:230:230)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (861:861:861)) + (PORT datab (881:881:881) (872:872:872)) + (PORT datac (598:598:598) (609:609:609)) + (PORT datad (1089:1089:1089) (1111:1111:1111)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (930:930:930)) + (PORT datab (906:906:906) (915:915:915)) + (PORT datac (1074:1074:1074) (1075:1075:1075)) + (PORT datad (909:909:909) (944:944:944)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (609:609:609)) + (PORT datab (1357:1357:1357) (1357:1357:1357)) + (PORT datac (760:760:760) (823:823:823)) + (PORT datad (1761:1761:1761) (1803:1803:1803)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|nM1_int\~2) + (DELAY + (ABSOLUTE + (PORT datac (1220:1220:1220) (1304:1304:1304)) + (PORT datad (2019:2019:2019) (2122:2122:2122)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (781:781:781)) + (PORT datab (195:195:195) (237:237:237)) + (PORT datac (1068:1068:1068) (1048:1048:1048)) + (PORT datad (587:587:587) (602:602:602)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~94) + (DELAY + (ABSOLUTE + (PORT dataa (841:841:841) (883:883:883)) + (PORT datab (1370:1370:1370) (1391:1391:1391)) + (PORT datac (1296:1296:1296) (1351:1351:1351)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) + (DELAY + (ABSOLUTE + (PORT dataa (561:561:561) (577:577:577)) + (PORT datab (208:208:208) (244:244:244)) + (PORT datac (763:763:763) (750:750:750)) + (PORT datad (723:723:723) (765:765:765)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1852:1852:1852) (1889:1889:1889)) + (PORT datab (559:559:559) (570:570:570)) + (PORT datac (767:767:767) (773:773:773)) + (PORT datad (646:646:646) (661:661:661)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1531:1531:1531) (1548:1548:1548)) + (PORT datab (1639:1639:1639) (1660:1660:1660)) + (PORT datac (833:833:833) (838:838:838)) + (PORT datad (645:645:645) (656:656:656)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (853:853:853)) + (PORT datab (1832:1832:1832) (1865:1865:1865)) + (PORT datac (1661:1661:1661) (1617:1617:1617)) + (PORT datad (1326:1326:1326) (1285:1285:1285)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (578:578:578)) + (PORT datab (683:683:683) (691:691:691)) + (PORT datac (1062:1062:1062) (1084:1084:1084)) + (PORT datad (745:745:745) (734:734:734)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (589:589:589)) + (PORT datab (684:684:684) (694:694:694)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (568:568:568) (569:569:569)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (337:337:337)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1532:1532:1532) (1507:1507:1507)) + (PORT datab (772:772:772) (767:767:767)) + (PORT datac (811:811:811) (824:824:824)) + (PORT datad (538:538:538) (542:542:542)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1527:1527:1527) (1544:1544:1544)) + (PORT datab (558:558:558) (567:567:567)) + (PORT datac (155:155:155) (184:184:184)) + (PORT datad (1806:1806:1806) (1845:1845:1845)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) + (DELAY + (ABSOLUTE + (PORT dataa (722:722:722) (789:789:789)) + (PORT datab (1028:1028:1028) (1044:1044:1044)) + (PORT datac (702:702:702) (740:740:740)) + (PORT datad (600:600:600) (603:603:603)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~99) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (715:715:715)) + (PORT datab (2176:2176:2176) (2234:2234:2234)) + (PORT datac (683:683:683) (756:756:756)) + (PORT datad (1698:1698:1698) (1692:1692:1692)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (249:249:249)) + (PORT datab (574:574:574) (589:589:589)) + (PORT datac (329:329:329) (344:344:344)) + (PORT datad (761:761:761) (756:756:756)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) + (DELAY + (ABSOLUTE + (PORT datac (1948:1948:1948) (2007:2007:2007)) + (PORT datad (1523:1523:1523) (1632:1632:1632)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (239:239:239)) + (PORT datab (189:189:189) (224:224:224)) + (PORT datac (824:824:824) (808:808:808)) + (PORT datad (341:341:341) (342:342:342)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (344:344:344)) + (PORT datab (574:574:574) (558:558:558)) + (PORT datac (545:545:545) (536:536:536)) + (PORT datad (761:761:761) (721:721:721)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (317:317:317)) + (PORT datab (1626:1626:1626) (1629:1629:1629)) + (PORT datac (222:222:222) (275:275:275)) + (PORT datad (200:200:200) (240:240:240)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (905:905:905)) + (PORT datab (894:894:894) (914:914:914)) + (PORT datac (1746:1746:1746) (1751:1751:1751)) + (PORT datad (596:596:596) (596:596:596)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (939:939:939)) + (PORT datab (1304:1304:1304) (1379:1379:1379)) + (PORT datac (872:872:872) (925:925:925)) + (PORT datad (759:759:759) (739:739:739)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (632:632:632)) + (PORT datab (1488:1488:1488) (1495:1495:1495)) + (PORT datac (1185:1185:1185) (1218:1218:1218)) + (PORT datad (1062:1062:1062) (1042:1042:1042)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~5) + (DELAY + (ABSOLUTE + (PORT datac (1785:1785:1785) (1786:1786:1786)) + (PORT datad (1904:1904:1904) (1949:1949:1949)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (238:238:238)) + (PORT datab (1368:1368:1368) (1427:1427:1427)) + (PORT datac (1809:1809:1809) (1809:1809:1809)) + (PORT datad (189:189:189) (219:219:219)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal48\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1822:1822:1822) (1823:1823:1823)) + (PORT datab (1941:1941:1941) (1986:1986:1986)) + (PORT datac (1342:1342:1342) (1397:1397:1397)) + (PORT datad (194:194:194) (224:224:224)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1836:1836:1836) (1840:1840:1840)) + (PORT datab (1121:1121:1121) (1123:1123:1123)) + (PORT datac (1593:1593:1593) (1593:1593:1593)) + (PORT datad (868:868:868) (891:891:891)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1371:1371:1371) (1373:1373:1373)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (1279:1279:1279) (1272:1272:1272)) + (PORT datad (569:569:569) (579:579:579)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1087:1087:1087) (1074:1074:1074)) + (PORT datab (1488:1488:1488) (1495:1495:1495)) + (PORT datac (823:823:823) (828:828:828)) + (PORT datad (832:832:832) (840:840:840)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (230:230:230)) + (PORT datab (180:180:180) (214:214:214)) + (PORT datac (161:161:161) (195:195:195)) + (PORT datad (192:192:192) (219:219:219)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) + (DELAY + (ABSOLUTE + (PORT datab (1945:1945:1945) (1990:1990:1990)) + (PORT datac (1338:1338:1338) (1396:1396:1396)) + (PORT datad (191:191:191) (221:221:221)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) + (DELAY + (ABSOLUTE + (PORT datab (1374:1374:1374) (1413:1413:1413)) + (PORT datac (1950:1950:1950) (2007:2007:2007)) + (PORT datad (1528:1528:1528) (1633:1633:1633)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (885:885:885)) + (PORT datab (1006:1006:1006) (1006:1006:1006)) + (PORT datac (594:594:594) (616:616:616)) + (PORT datad (577:577:577) (576:576:576)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~7) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (555:555:555)) + (PORT datab (852:852:852) (849:849:849)) + (PORT datac (543:543:543) (526:526:526)) + (PORT datad (1499:1499:1499) (1446:1446:1446)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (2070:2070:2070) (2090:2090:2090)) + (PORT datab (1483:1483:1483) (1557:1557:1557)) + (PORT datac (788:788:788) (785:785:785)) + (PORT datad (808:808:808) (809:809:809)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (630:630:630)) + (PORT datab (812:812:812) (822:822:822)) + (PORT datac (1571:1571:1571) (1570:1570:1570)) + (PORT datad (1391:1391:1391) (1374:1374:1374)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1067:1067:1067) (1096:1096:1096)) + (PORT datab (584:584:584) (589:589:589)) + (PORT datac (605:605:605) (624:624:624)) + (PORT datad (1089:1089:1089) (1073:1073:1073)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1135:1135:1135) (1172:1172:1172)) + (PORT datab (905:905:905) (913:913:913)) + (PORT datac (1553:1553:1553) (1540:1540:1540)) + (PORT datad (1274:1274:1274) (1284:1284:1284)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (230:230:230)) + (PORT datab (929:929:929) (974:974:974)) + (PORT datac (1648:1648:1648) (1671:1671:1671)) + (PORT datad (1274:1274:1274) (1284:1284:1284)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (900:900:900)) + (PORT datab (879:879:879) (878:878:878)) + (PORT datad (831:831:831) (859:859:859)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (243:243:243)) + (PORT datab (914:914:914) (938:938:938)) + (PORT datac (748:748:748) (722:722:722)) + (PORT datad (1295:1295:1295) (1274:1274:1274)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1634:1634:1634) (1680:1680:1680)) + (PORT datab (1512:1512:1512) (1598:1598:1598)) + (PORT datad (1743:1743:1743) (1723:1723:1723)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~0) + (DELAY + (ABSOLUTE + (PORT dataa (982:982:982) (1041:1041:1041)) + (PORT datac (1611:1611:1611) (1672:1672:1672)) + (PORT datad (587:587:587) (619:619:619)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1000:1000:1000) (1047:1047:1047)) + (PORT datab (850:850:850) (891:891:891)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (529:529:529) (516:516:516)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1768:1768:1768) (1796:1796:1796)) + (PORT datab (1399:1399:1399) (1420:1420:1420)) + (PORT datac (1479:1479:1479) (1568:1568:1568)) + (PORT datad (803:803:803) (795:795:795)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1342:1342:1342) (1352:1352:1352)) + (PORT datab (1149:1149:1149) (1160:1160:1160)) + (PORT datac (861:861:861) (897:897:897)) + (PORT datad (777:777:777) (766:766:766)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (268:268:268)) + (PORT datab (1826:1826:1826) (1856:1856:1856)) + (PORT datac (1304:1304:1304) (1316:1316:1316)) + (PORT datad (1395:1395:1395) (1471:1471:1471)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1258:1258:1258) (1307:1307:1307)) + (PORT datab (1432:1432:1432) (1503:1503:1503)) + (PORT datac (2254:2254:2254) (2339:2339:2339)) + (PORT datad (1129:1129:1129) (1214:1214:1214)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1534:1534:1534) (1555:1555:1555)) + (PORT datab (857:857:857) (869:869:869)) + (PORT datac (2383:2383:2383) (2320:2320:2320)) + (PORT datad (709:709:709) (740:740:740)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1347:1347:1347) (1360:1360:1360)) + (PORT datab (560:560:560) (550:550:550)) + (PORT datac (1047:1047:1047) (1032:1032:1032)) + (PORT datad (545:545:545) (534:534:534)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1343:1343:1343) (1355:1355:1355)) + (PORT datab (1314:1314:1314) (1319:1319:1319)) + (PORT datac (858:858:858) (899:899:899)) + (PORT datad (1306:1306:1306) (1286:1286:1286)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1647:1647:1647) (1710:1710:1710)) + (PORT datab (198:198:198) (231:231:231)) + (PORT datac (163:163:163) (198:198:198)) + (PORT datad (165:165:165) (187:187:187)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (729:729:729)) + (PORT datab (1107:1107:1107) (1092:1092:1092)) + (PORT datac (1111:1111:1111) (1129:1129:1129)) + (PORT datad (821:821:821) (844:844:844)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (754:754:754) (808:808:808)) + (PORT datab (1731:1731:1731) (1808:1808:1808)) + (PORT datac (307:307:307) (314:314:314)) + (PORT datad (1562:1562:1562) (1567:1567:1567)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (2017:2017:2017) (2129:2129:2129)) + (PORT datab (1296:1296:1296) (1292:1292:1292)) + (PORT datac (1321:1321:1321) (1303:1303:1303)) + (PORT datad (2101:2101:2101) (2138:2138:2138)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1202:1202:1202) (1233:1233:1233)) + (PORT datab (1123:1123:1123) (1125:1125:1125)) + (PORT datac (601:601:601) (639:639:639)) + (PORT datad (1057:1057:1057) (1055:1055:1055)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1351:1351:1351) (1349:1349:1349)) + (PORT datab (1102:1102:1102) (1134:1134:1134)) + (PORT datac (604:604:604) (640:640:640)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1977:1977:1977) (2042:2042:2042)) + (PORT datab (1561:1561:1561) (1668:1668:1668)) + (PORT datac (1066:1066:1066) (1088:1088:1088)) + (PORT datad (1804:1804:1804) (1792:1792:1792)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (779:779:779) (803:803:803)) + (PORT datab (852:852:852) (870:870:870)) + (PORT datac (518:518:518) (524:524:524)) + (PORT datad (1017:1017:1017) (988:988:988)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (821:821:821)) + (PORT datab (958:958:958) (983:983:983)) + (PORT datac (1085:1085:1085) (1070:1070:1070)) + (PORT datad (590:590:590) (592:592:592)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (609:609:609)) + (PORT datab (617:617:617) (625:625:625)) + (PORT datac (588:588:588) (602:602:602)) + (PORT datad (1054:1054:1054) (1044:1044:1044)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (609:609:609)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1084:1084:1084) (1072:1072:1072)) + (PORT datad (523:523:523) (518:518:518)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1221:1221:1221) (1271:1271:1271)) + (PORT datab (1422:1422:1422) (1405:1405:1405)) + (PORT datac (1285:1285:1285) (1393:1393:1393)) + (PORT datad (2356:2356:2356) (2373:2373:2373)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1382:1382:1382) (1372:1372:1372)) + (PORT datab (1390:1390:1390) (1428:1428:1428)) + (PORT datac (1530:1530:1530) (1519:1519:1519)) + (PORT datad (1377:1377:1377) (1442:1442:1442)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1154:1154:1154) (1165:1165:1165)) + (PORT datab (609:609:609) (627:627:627)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (622:622:622) (642:642:642)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2147:2147:2147) (2204:2204:2204)) + (PORT datab (2061:2061:2061) (2084:2084:2084)) + (PORT datac (1284:1284:1284) (1392:1392:1392)) + (PORT datad (1081:1081:1081) (1077:1077:1077)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal68\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1609:1609:1609) (1650:1650:1650)) + (PORT datab (1513:1513:1513) (1636:1636:1636)) + (PORT datac (952:952:952) (992:992:992)) + (PORT datad (1661:1661:1661) (1721:1721:1721)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1335:1335:1335) (1374:1374:1374)) + (PORT datab (1056:1056:1056) (1054:1054:1054)) + (PORT datac (753:753:753) (736:736:736)) + (PORT datad (1382:1382:1382) (1447:1447:1447)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal63\~0) + (DELAY + (ABSOLUTE + (PORT dataa (979:979:979) (1025:1025:1025)) + (PORT datab (202:202:202) (236:236:236)) + (PORT datac (1569:1569:1569) (1607:1607:1607)) + (PORT datad (1411:1411:1411) (1450:1450:1450)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal76\~2) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (614:614:614)) + (PORT datac (2053:2053:2053) (2069:2069:2069)) + (PORT datad (1559:1559:1559) (1577:1577:1577)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (596:596:596)) + (PORT datab (1380:1380:1380) (1363:1363:1363)) + (PORT datac (1119:1119:1119) (1127:1127:1127)) + (PORT datad (523:523:523) (523:523:523)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1705:1705:1705) (1745:1745:1745)) + (PORT datab (832:832:832) (818:818:818)) + (PORT datac (797:797:797) (784:784:784)) + (PORT datad (1408:1408:1408) (1377:1377:1377)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1023:1023:1023) (1015:1015:1015)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1119:1119:1119) (1127:1127:1127)) + (PORT datad (850:850:850) (871:871:871)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (622:622:622)) + (PORT datab (360:360:360) (364:364:364)) + (PORT datac (1068:1068:1068) (1052:1052:1052)) + (PORT datad (870:870:870) (877:877:877)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) + (DELAY + (ABSOLUTE + (PORT dataa (1141:1141:1141) (1175:1175:1175)) + (PORT datab (895:895:895) (947:947:947)) + (PORT datac (775:775:775) (783:783:783)) + (PORT datad (1245:1245:1245) (1317:1317:1317)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) + (DELAY + (ABSOLUTE + (PORT dataa (833:833:833) (825:825:825)) + (PORT datab (1131:1131:1131) (1132:1132:1132)) + (PORT datac (1125:1125:1125) (1133:1133:1133)) + (PORT datad (628:628:628) (658:658:658)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1921:1921:1921) (1991:1991:1991)) + (PORT datab (1406:1406:1406) (1435:1435:1435)) + (PORT datac (546:546:546) (561:561:561)) + (PORT datad (1939:1939:1939) (1989:1989:1989)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~7) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (885:885:885)) + (PORT datab (227:227:227) (269:269:269)) + (PORT datac (1111:1111:1111) (1129:1129:1129)) + (PORT datad (1614:1614:1614) (1620:1620:1620)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (269:269:269)) + (PORT datab (594:594:594) (596:596:596)) + (PORT datac (162:162:162) (195:195:195)) + (PORT datad (165:165:165) (187:187:187)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~3) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (974:974:974)) + (PORT datab (821:821:821) (806:806:806)) + (PORT datac (951:951:951) (1023:1023:1023)) + (PORT datad (1170:1170:1170) (1212:1212:1212)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (799:799:799) (819:819:819)) + (PORT datab (587:587:587) (601:601:601)) + (PORT datac (1526:1526:1526) (1585:1585:1585)) + (PORT datad (1056:1056:1056) (1035:1035:1035)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (723:723:723)) + (PORT datab (1137:1137:1137) (1153:1153:1153)) + (PORT datac (1197:1197:1197) (1255:1255:1255)) + (PORT datad (822:822:822) (844:844:844)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (381:381:381)) + (PORT datab (1121:1121:1121) (1136:1136:1136)) + (PORT datac (887:887:887) (922:922:922)) + (PORT datad (1775:1775:1775) (1857:1857:1857)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) + (DELAY + (ABSOLUTE + (PORT dataa (1215:1215:1215) (1262:1262:1262)) + (PORT datab (1420:1420:1420) (1502:1502:1502)) + (PORT datac (2033:2033:2033) (2061:2061:2061)) + (PORT datad (848:848:848) (872:872:872)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (2372:2372:2372) (2473:2473:2473)) + (PORT datab (1161:1161:1161) (1175:1175:1175)) + (PORT datac (817:817:817) (826:826:826)) + (PORT datad (1995:1995:1995) (2065:2065:2065)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1169:1169:1169) (1185:1185:1185)) + (PORT datac (1311:1311:1311) (1283:1283:1283)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (597:597:597)) + (PORT datab (1160:1160:1160) (1157:1157:1157)) + (PORT datac (1735:1735:1735) (1819:1819:1819)) + (PORT datad (1528:1528:1528) (1635:1635:1635)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1126:1126:1126) (1130:1130:1130)) + (PORT datab (531:531:531) (520:520:520)) + (PORT datac (1894:1894:1894) (1961:1961:1961)) + (PORT datad (1212:1212:1212) (1280:1280:1280)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (252:252:252)) + (PORT datab (639:639:639) (632:632:632)) + (PORT datac (809:809:809) (821:821:821)) + (PORT datad (287:287:287) (294:294:294)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1509:1509:1509) (1501:1501:1501)) + (PORT datab (1390:1390:1390) (1428:1428:1428)) + (PORT datac (162:162:162) (197:197:197)) + (PORT datad (644:644:644) (687:687:687)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal10\~1) + (DELAY + (ABSOLUTE + (PORT datac (1974:1974:1974) (1977:1977:1977)) + (PORT datad (1309:1309:1309) (1309:1309:1309)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) + (DELAY + (ABSOLUTE + (PORT dataa (1114:1114:1114) (1124:1124:1124)) + (PORT datab (1321:1321:1321) (1318:1318:1318)) + (PORT datac (162:162:162) (198:198:198)) + (PORT datad (1318:1318:1318) (1354:1354:1354)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal69\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1822:1822:1822) (1823:1823:1823)) + (PORT datab (1941:1941:1941) (1986:1986:1986)) + (PORT datac (1342:1342:1342) (1397:1397:1397)) + (PORT datad (194:194:194) (224:224:224)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1753:1753:1753) (1714:1714:1714)) + (PORT datab (1251:1251:1251) (1313:1313:1313)) + (PORT datac (1895:1895:1895) (1963:1963:1963)) + (PORT datad (1940:1940:1940) (1990:1990:1990)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1624:1624:1624) (1649:1649:1649)) + (PORT datab (858:858:858) (861:861:861)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (578:578:578) (587:587:587)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (230:230:230)) + (PORT datab (592:592:592) (605:605:605)) + (PORT datac (564:564:564) (557:557:557)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (971:971:971)) + (PORT datab (820:820:820) (804:804:804)) + (PORT datac (1520:1520:1520) (1616:1616:1616)) + (PORT datad (1978:1978:1978) (2057:2057:2057)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1029:1029:1029) (1021:1021:1021)) + (PORT datab (194:194:194) (234:234:234)) + (PORT datac (157:157:157) (186:186:186)) + (PORT datad (796:796:796) (803:803:803)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (309:309:309)) + (PORT datab (225:225:225) (275:275:275)) + (PORT datac (1084:1084:1084) (1088:1088:1088)) + (PORT datad (228:228:228) (279:279:279)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1432:1432:1432) (1502:1502:1502)) + (PORT datab (1850:1850:1850) (1838:1838:1838)) + (PORT datac (816:816:816) (825:825:825)) + (PORT datad (1582:1582:1582) (1631:1631:1631)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1142:1142:1142) (1160:1160:1160)) + (PORT datab (569:569:569) (581:581:581)) + (PORT datac (571:571:571) (593:593:593)) + (PORT datad (823:823:823) (829:829:829)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1700:1700:1700) (1753:1753:1753)) + (PORT datab (850:850:850) (875:875:875)) + (PORT datad (588:588:588) (589:589:589)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (239:239:239)) + (PORT datab (1073:1073:1073) (1036:1036:1036)) + (PORT datac (300:300:300) (310:310:310)) + (PORT datad (612:612:612) (646:646:646)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (205:205:205) (241:241:241)) + (PORT datac (569:569:569) (575:575:575)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1699:1699:1699) (1750:1750:1750)) + (PORT datab (625:625:625) (622:622:622)) + (PORT datac (161:161:161) (193:193:193)) + (PORT datad (826:826:826) (840:840:840)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~20) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (975:975:975)) + (PORT datab (1698:1698:1698) (1746:1746:1746)) + (PORT datac (914:914:914) (948:948:948)) + (PORT datad (1137:1137:1137) (1170:1170:1170)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (2107:2107:2107) (2188:2188:2188)) + (PORT datab (1699:1699:1699) (1745:1745:1745)) + (PORT datac (806:806:806) (817:817:817)) + (PORT datad (164:164:164) (189:189:189)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (796:796:796) (787:787:787)) + (PORT datab (1296:1296:1296) (1351:1351:1351)) + (PORT datac (603:603:603) (634:634:634)) + (PORT datad (625:625:625) (674:674:674)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (317:317:317)) + (PORT datab (225:225:225) (270:270:270)) + (PORT datac (220:220:220) (272:272:272)) + (PORT datad (1121:1121:1121) (1127:1127:1127)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (733:733:733) (769:769:769)) + (PORT datab (591:591:591) (632:632:632)) + (PORT datac (770:770:770) (796:796:796)) + (PORT datad (614:614:614) (647:647:647)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (228:228:228)) + (PORT datab (1445:1445:1445) (1445:1445:1445)) + (PORT datac (2559:2559:2559) (2571:2571:2571)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (641:641:641)) + (PORT datab (354:354:354) (356:356:356)) + (PORT datac (164:164:164) (200:200:200)) + (PORT datad (831:831:831) (829:829:829)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) + (DELAY + (ABSOLUTE + (PORT dataa (1169:1169:1169) (1215:1215:1215)) + (PORT datab (926:926:926) (952:952:952)) + (PORT datac (877:877:877) (900:900:900)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1123:1123:1123) (1104:1104:1104)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) + (DELAY + (ABSOLUTE + (PORT dataa (1169:1169:1169) (1214:1214:1214)) + (PORT datab (927:927:927) (955:955:955)) + (PORT datac (877:877:877) (897:897:897)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1343:1343:1343) (1386:1386:1386)) + (PORT datab (995:995:995) (1021:1021:1021)) + (PORT datac (1089:1089:1089) (1092:1092:1092)) + (PORT datad (1309:1309:1309) (1311:1311:1311)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (588:588:588)) + (PORT datab (187:187:187) (220:220:220)) + (PORT datac (1283:1283:1283) (1258:1258:1258)) + (PORT datad (1155:1155:1155) (1167:1167:1167)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1421:1421:1421) (1458:1458:1458)) + (PORT datab (1629:1629:1629) (1626:1626:1626)) + (PORT datac (562:562:562) (557:557:557)) + (PORT datad (582:582:582) (580:580:580)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~47) + (DELAY + (ABSOLUTE + (PORT datab (638:638:638) (651:651:651)) + (PORT datac (354:354:354) (362:362:362)) + (PORT datad (795:795:795) (787:787:787)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) + (DELAY + (ABSOLUTE + (PORT dataa (819:819:819) (847:847:847)) + (PORT datab (1145:1145:1145) (1122:1122:1122)) + (PORT datac (167:167:167) (206:206:206)) + (PORT datad (1329:1329:1329) (1341:1341:1341)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (827:827:827)) + (PORT datab (628:628:628) (663:663:663)) + (PORT datac (821:821:821) (822:822:822)) + (PORT datad (1360:1360:1360) (1356:1356:1356)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (580:580:580) (598:598:598)) + (PORT datab (628:628:628) (663:663:663)) + (PORT datac (1534:1534:1534) (1540:1540:1540)) + (PORT datad (336:336:336) (346:346:346)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (581:581:581) (600:600:600)) + (PORT datab (1562:1562:1562) (1568:1568:1568)) + (PORT datac (767:767:767) (749:749:749)) + (PORT datad (774:774:774) (753:753:753)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (596:596:596)) + (PORT datab (838:838:838) (844:844:844)) + (PORT datac (1532:1532:1532) (1537:1537:1537)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) + (DELAY + (ABSOLUTE + (PORT datab (592:592:592) (582:582:582)) + (PORT datac (161:161:161) (194:194:194)) + (PORT datad (165:165:165) (190:190:190)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (1242:1242:1242) (1313:1313:1313)) + (PORT datac (1814:1814:1814) (1910:1910:1910)) + (PORT datad (1080:1080:1080) (1071:1071:1071)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1649:1649:1649) (1694:1694:1694)) + (PORT datab (221:221:221) (266:266:266)) + (PORT datac (819:819:819) (833:833:833)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~41) + (DELAY + (ABSOLUTE + (PORT datab (853:853:853) (886:886:886)) + (PORT datac (957:957:957) (1011:1011:1011)) + (PORT datad (570:570:570) (571:571:571)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1552:1552:1552) (1576:1576:1576)) + (PORT datab (1670:1670:1670) (1701:1701:1701)) + (PORT datac (1233:1233:1233) (1228:1228:1228)) + (PORT datad (596:596:596) (614:614:614)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (862:862:862)) + (PORT datab (987:987:987) (990:990:990)) + (PORT datac (1380:1380:1380) (1410:1410:1410)) + (PORT datad (1109:1109:1109) (1113:1113:1113)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (225:225:225)) + (PORT datab (1408:1408:1408) (1432:1432:1432)) + (PORT datac (1014:1014:1014) (990:990:990)) + (PORT datad (164:164:164) (188:188:188)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (849:849:849)) + (PORT datab (1529:1529:1529) (1498:1498:1498)) + (PORT datac (1177:1177:1177) (1208:1208:1208)) + (PORT datad (1475:1475:1475) (1423:1423:1423)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (594:594:594)) + (PORT datac (1122:1122:1122) (1118:1118:1118)) + (PORT datad (821:821:821) (838:838:838)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1341:1341:1341) (1342:1342:1342)) + (PORT datab (608:608:608) (594:594:594)) + (PORT datac (160:160:160) (193:193:193)) + (PORT datad (872:872:872) (866:866:866)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) + (DELAY + (ABSOLUTE + (PORT datac (547:547:547) (537:537:537)) + (PORT datad (800:800:800) (779:779:779)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (765:765:765) (743:743:743)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (349:349:349)) + (PORT datac (549:549:549) (545:545:545)) + (PORT datad (565:565:565) (574:574:574)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1214:1214:1214) (1249:1249:1249)) + (PORT datab (1486:1486:1486) (1494:1494:1494)) + (PORT datac (895:895:895) (929:929:929)) + (PORT datad (2050:2050:2050) (1954:1954:1954)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (770:770:770)) + (PORT datab (201:201:201) (234:234:234)) + (PORT datac (900:900:900) (904:904:904)) + (PORT datad (1028:1028:1028) (1042:1042:1042)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1070:1070:1070) (1064:1064:1064)) + (PORT datab (840:840:840) (837:837:837)) + (PORT datac (884:884:884) (913:913:913)) + (PORT datad (180:180:180) (211:211:211)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1176:1176:1176) (1232:1232:1232)) + (PORT datab (591:591:591) (580:580:580)) + (PORT datac (167:167:167) (205:205:205)) + (PORT datad (884:884:884) (936:936:936)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) + (DELAY + (ABSOLUTE + (PORT datab (1137:1137:1137) (1154:1154:1154)) + (PORT datac (862:862:862) (884:884:884)) + (PORT datad (839:839:839) (867:867:867)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1091:1091:1091) (1087:1087:1087)) + (PORT datab (849:849:849) (840:840:840)) + (PORT datac (1046:1046:1046) (1033:1033:1033)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) + (DELAY + (ABSOLUTE + (PORT datab (1245:1245:1245) (1206:1206:1206)) + (PORT datad (1059:1059:1059) (1042:1042:1042)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (610:610:610)) + (PORT datab (181:181:181) (212:212:212)) + (PORT datac (755:755:755) (745:745:745)) + (PORT datad (761:761:761) (754:754:754)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (603:603:603)) + (PORT datab (909:909:909) (962:962:962)) + (PORT datac (1010:1010:1010) (983:983:983)) + (PORT datad (1654:1654:1654) (1710:1710:1710)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (605:605:605)) + (PORT datab (882:882:882) (865:865:865)) + (PORT datac (334:334:334) (354:354:354)) + (PORT datad (164:164:164) (186:186:186)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (217:217:217)) + (PORT datab (579:579:579) (558:558:558)) + (PORT datac (809:809:809) (802:802:802)) + (PORT datad (537:537:537) (523:523:523)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) + (DELAY + (ABSOLUTE + (PORT dataa (1172:1172:1172) (1216:1216:1216)) + (PORT datab (914:914:914) (919:919:919)) + (PORT datac (895:895:895) (920:920:920)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) + (DELAY + (ABSOLUTE + (PORT dataa (1167:1167:1167) (1202:1202:1202)) + (PORT datab (910:910:910) (918:918:918)) + (PORT datac (902:902:902) (927:927:927)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (484:484:484) (510:510:510)) + (PORT ena (1129:1129:1129) (1100:1100:1100)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (873:873:873)) + (PORT datab (2423:2423:2423) (2439:2439:2439)) + (PORT datac (169:169:169) (208:208:208)) + (PORT datad (1277:1277:1277) (1281:1281:1281)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_exx\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1761:1761:1761) (1869:1869:1869)) + (PORT datab (1393:1393:1393) (1412:1412:1412)) + (PORT datad (1072:1072:1072) (1043:1043:1043)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_exx) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1375:1375:1375)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1712:1712:1712) (1681:1681:1681)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1522:1522:1522) (1510:1510:1510)) + (PORT datab (1608:1608:1608) (1577:1577:1577)) + (PORT datac (1098:1098:1098) (1115:1115:1115)) + (PORT datad (1127:1127:1127) (1147:1147:1147)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1133:1133:1133) (1124:1124:1124)) + (PORT datab (1117:1117:1117) (1129:1129:1129)) + (PORT datac (1547:1547:1547) (1532:1532:1532)) + (PORT datad (545:545:545) (534:534:534)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1369:1369:1369) (1380:1380:1380)) + (PORT datab (880:880:880) (913:913:913)) + (PORT datac (1104:1104:1104) (1110:1110:1110)) + (PORT datad (1095:1095:1095) (1103:1103:1103)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (579:579:579)) + (PORT datab (1718:1718:1718) (1747:1747:1747)) + (PORT datac (948:948:948) (985:985:985)) + (PORT datad (2417:2417:2417) (2388:2388:2388)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~56) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1143:1143:1143)) + (PORT datab (1165:1165:1165) (1181:1181:1181)) + (PORT datac (804:804:804) (835:835:835)) + (PORT datad (823:823:823) (858:858:858)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) + (DELAY + (ABSOLUTE + (PORT datab (847:847:847) (836:836:836)) + (PORT datac (586:586:586) (597:597:597)) + (PORT datad (178:178:178) (201:201:201)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (207:207:207) (253:253:253)) + (PORT datac (2500:2500:2500) (2608:2608:2608)) + (PORT datad (197:197:197) (229:229:229)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1467:1467:1467) (1453:1453:1453)) + (PORT datab (1388:1388:1388) (1407:1407:1407)) + (PORT datac (1366:1366:1366) (1382:1382:1382)) + (PORT datad (1029:1029:1029) (1031:1031:1031)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1137:1137:1137) (1179:1179:1179)) + (PORT datab (893:893:893) (949:949:949)) + (PORT datac (1810:1810:1810) (1805:1805:1805)) + (PORT datad (1249:1249:1249) (1320:1320:1320)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1346:1346:1346) (1358:1358:1358)) + (PORT datab (1209:1209:1209) (1281:1281:1281)) + (PORT datac (858:858:858) (900:900:900)) + (PORT datad (1392:1392:1392) (1470:1470:1470)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (902:902:902)) + (PORT datab (194:194:194) (233:233:233)) + (PORT datac (548:548:548) (564:564:564)) + (PORT datad (1143:1143:1143) (1150:1150:1150)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1409:1409:1409) (1435:1435:1435)) + (PORT datab (824:824:824) (825:825:825)) + (PORT datac (1350:1350:1350) (1325:1325:1325)) + (PORT datad (628:628:628) (654:654:654)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (882:882:882) (891:891:891)) + (PORT datac (583:583:583) (578:578:578)) + (PORT datad (534:534:534) (530:530:530)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (652:652:652)) + (PORT datab (1043:1043:1043) (1047:1047:1047)) + (PORT datac (1777:1777:1777) (1816:1816:1816)) + (PORT datad (755:755:755) (757:757:757)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (881:881:881)) + (PORT datab (516:516:516) (520:520:520)) + (PORT datac (888:888:888) (903:903:903)) + (PORT datad (858:858:858) (869:869:869)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (336:336:336)) + (PORT datab (227:227:227) (263:263:263)) + (PORT datac (888:888:888) (900:900:900)) + (PORT datad (858:858:858) (866:866:866)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~52) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (969:969:969)) + (PORT datab (715:715:715) (786:786:786)) + (PORT datac (673:673:673) (738:738:738)) + (PORT datad (579:579:579) (606:606:606)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1109:1109:1109) (1130:1130:1130)) + (PORT datab (315:315:315) (332:332:332)) + (PORT datac (1751:1751:1751) (1851:1851:1851)) + (PORT datad (570:570:570) (574:574:574)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (251:251:251)) + (PORT datab (370:370:370) (388:388:388)) + (PORT datac (905:905:905) (911:911:911)) + (PORT datad (755:755:755) (735:735:735)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (228:228:228)) + (PORT datab (188:188:188) (223:223:223)) + (PORT datac (1122:1122:1122) (1120:1120:1120)) + (PORT datad (301:301:301) (306:306:306)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1509:1509:1509) (1478:1478:1478)) + (PORT datab (1119:1119:1119) (1115:1115:1115)) + (PORT datac (1197:1197:1197) (1256:1256:1256)) + (PORT datad (636:636:636) (687:687:687)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (247:247:247)) + (PORT datab (575:575:575) (573:573:573)) + (PORT datac (1051:1051:1051) (1038:1038:1038)) + (PORT datad (643:643:643) (684:684:684)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (724:724:724)) + (PORT datab (619:619:619) (644:644:644)) + (PORT datac (589:589:589) (606:606:606)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (201:201:201) (233:233:233)) + (PORT datac (1060:1060:1060) (1049:1049:1049)) + (PORT datad (164:164:164) (187:187:187)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (567:567:567)) + (PORT datab (1090:1090:1090) (1068:1068:1068)) + (PORT datac (1306:1306:1306) (1296:1296:1296)) + (PORT datad (798:798:798) (785:785:785)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (264:264:264)) + (PORT datab (918:918:918) (938:938:938)) + (PORT datac (593:593:593) (624:624:624)) + (PORT datad (298:298:298) (294:294:294)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) + (DELAY + (ABSOLUTE + (PORT datab (3331:3331:3331) (3323:3323:3323)) + (PORT datad (1395:1395:1395) (1422:1422:1422)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~8) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (572:572:572)) + (PORT datab (1084:1084:1084) (1088:1088:1088)) + (PORT datac (580:580:580) (580:580:580)) + (PORT datad (770:770:770) (756:756:756)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~48) + (DELAY + (ABSOLUTE + (PORT dataa (1705:1705:1705) (1744:1744:1744)) + (PORT datab (832:832:832) (871:871:871)) + (PORT datac (822:822:822) (822:822:822)) + (PORT datad (797:797:797) (801:801:801)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) + (DELAY + (ABSOLUTE + (PORT datab (609:609:609) (622:622:622)) + (PORT datad (1028:1028:1028) (1015:1015:1015)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~2) + (DELAY + (ABSOLUTE + (PORT datab (809:809:809) (814:814:814)) + (PORT datac (977:977:977) (1012:1012:1012)) + (PORT datad (1394:1394:1394) (1376:1376:1376)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~49) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (349:349:349)) + (PORT datab (179:179:179) (212:212:212)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (516:516:516) (500:500:500)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1524:1524:1524) (1638:1638:1638)) + (PORT datab (1165:1165:1165) (1220:1220:1220)) + (PORT datac (1273:1273:1273) (1247:1247:1247)) + (PORT datad (545:545:545) (541:541:541)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2069:2069:2069) (2089:2089:2089)) + (PORT datab (817:817:817) (812:812:812)) + (PORT datac (1451:1451:1451) (1528:1528:1528)) + (PORT datad (1564:1564:1564) (1582:1582:1582)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (866:866:866)) + (PORT datab (1250:1250:1250) (1227:1227:1227)) + (PORT datac (817:817:817) (828:828:828)) + (PORT datad (1315:1315:1315) (1289:1289:1289)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (646:646:646)) + (PORT datab (1366:1366:1366) (1352:1352:1352)) + (PORT datac (792:792:792) (785:785:785)) + (PORT datad (621:621:621) (645:645:645)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1147:1147:1147) (1178:1178:1178)) + (PORT datab (869:869:869) (857:857:857)) + (PORT datac (1309:1309:1309) (1294:1294:1294)) + (PORT datad (1630:1630:1630) (1640:1640:1640)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT datac (801:801:801) (790:790:790)) + (PORT datad (305:305:305) (319:319:319)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (228:228:228)) + (PORT datab (188:188:188) (223:223:223)) + (PORT datac (609:609:609) (613:613:613)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (877:877:877)) + (PORT datab (920:920:920) (934:934:934)) + (PORT datac (807:807:807) (827:827:827)) + (PORT datad (821:821:821) (815:815:815)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1652:1652:1652) (1679:1679:1679)) + (PORT datab (1426:1426:1426) (1406:1406:1406)) + (PORT datac (976:976:976) (1009:1009:1009)) + (PORT datad (782:782:782) (779:779:779)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1085:1085:1085) (1087:1087:1087)) + (PORT datab (807:807:807) (811:811:811)) + (PORT datac (977:977:977) (1009:1009:1009)) + (PORT datad (1389:1389:1389) (1371:1371:1371)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1631:1631:1631) (1629:1629:1629)) + (PORT datab (1787:1787:1787) (1769:1769:1769)) + (PORT datac (1451:1451:1451) (1404:1404:1404)) + (PORT datad (971:971:971) (997:997:997)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (256:256:256)) + (PORT datab (213:213:213) (254:254:254)) + (PORT datac (938:938:938) (958:958:958)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1527:1527:1527) (1639:1639:1639)) + (PORT datac (1141:1141:1141) (1199:1199:1199)) + (PORT datad (1036:1036:1036) (1023:1023:1023)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1292:1292:1292) (1288:1288:1288)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (758:758:758) (748:748:748)) + (PORT datad (786:786:786) (789:789:789)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1103:1103:1103) (1107:1107:1107)) + (PORT datac (846:846:846) (845:845:845)) + (PORT datad (795:795:795) (793:793:793)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1217:1217:1217) (1269:1269:1269)) + (PORT datab (859:859:859) (860:860:860)) + (PORT datac (1279:1279:1279) (1390:1390:1390)) + (PORT datad (1100:1100:1100) (1096:1096:1096)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (865:865:865)) + (PORT datab (1420:1420:1420) (1505:1505:1505)) + (PORT datac (2031:2031:2031) (2059:2059:2059)) + (PORT datad (1408:1408:1408) (1475:1475:1475)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (249:249:249)) + (PORT datab (200:200:200) (233:233:233)) + (PORT datac (175:175:175) (206:206:206)) + (PORT datad (1103:1103:1103) (1098:1098:1098)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1525:1525:1525) (1634:1634:1634)) + (PORT datab (327:327:327) (345:345:345)) + (PORT datac (1137:1137:1137) (1194:1194:1194)) + (PORT datad (559:559:559) (569:569:569)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~30) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (556:556:556)) + (PORT datab (896:896:896) (914:914:914)) + (PORT datac (609:609:609) (637:637:637)) + (PORT datad (548:548:548) (535:535:535)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (813:813:813)) + (PORT datab (191:191:191) (230:230:230)) + (PORT datac (173:173:173) (203:203:203)) + (PORT datad (1439:1439:1439) (1492:1492:1492)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (564:564:564)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (163:163:163) (198:198:198)) + (PORT datad (583:583:583) (599:599:599)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (238:238:238)) + (PORT datab (590:590:590) (611:611:611)) + (PORT datac (765:765:765) (748:748:748)) + (PORT datad (1563:1563:1563) (1577:1577:1577)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (353:353:353)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (1117:1117:1117) (1138:1138:1138)) + (PORT datad (976:976:976) (971:971:971)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) + (DELAY + (ABSOLUTE + (PORT dataa (1254:1254:1254) (1302:1302:1302)) + (PORT datab (1081:1081:1081) (1064:1064:1064)) + (PORT datad (1485:1485:1485) (1526:1526:1526)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1469:1469:1469) (1453:1453:1453)) + (PORT datab (1496:1496:1496) (1567:1567:1567)) + (PORT datac (806:806:806) (818:818:818)) + (PORT datad (1218:1218:1218) (1233:1233:1233)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (391:391:391)) + (PORT datab (220:220:220) (265:265:265)) + (PORT datac (1354:1354:1354) (1358:1358:1358)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1326:1326:1326) (1334:1334:1334)) + (PORT datab (1024:1024:1024) (989:989:989)) + (PORT datac (1387:1387:1387) (1391:1391:1391)) + (PORT datad (585:585:585) (592:592:592)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (565:565:565)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (570:570:570) (588:588:588)) + (PORT datad (581:581:581) (585:585:585)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1133:1133:1133) (1172:1172:1172)) + (PORT datab (2234:2234:2234) (2241:2241:2241)) + (PORT datac (1550:1550:1550) (1541:1541:1541)) + (PORT datad (908:908:908) (944:944:944)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (972:972:972)) + (PORT datab (702:702:702) (761:761:761)) + (PORT datac (563:563:563) (580:580:580)) + (PORT datad (813:813:813) (809:809:809)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1063:1063:1063) (1065:1065:1065)) + (PORT datab (349:349:349) (348:348:348)) + (PORT datac (853:853:853) (879:879:879)) + (PORT datad (763:763:763) (766:766:766)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (178:178:178) (223:223:223)) + (PORT datad (807:807:807) (821:821:821)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1425:1425:1425) (1469:1469:1469)) + (PORT datab (934:934:934) (982:982:982)) + (PORT datac (311:311:311) (327:327:327)) + (PORT datad (177:177:177) (209:209:209)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1294:1294:1294) (1317:1317:1317)) + (PORT datab (1034:1034:1034) (1013:1013:1013)) + (PORT datac (1286:1286:1286) (1278:1278:1278)) + (PORT datad (309:309:309) (323:323:323)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (846:846:846)) + (PORT datab (653:653:653) (705:705:705)) + (PORT datac (624:624:624) (666:666:666)) + (PORT datad (539:539:539) (538:538:538)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (443:443:443)) + (PORT datab (245:245:245) (316:316:316)) + (PORT datac (1290:1290:1290) (1350:1350:1350)) + (PORT datad (1085:1085:1085) (1129:1129:1129)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1471:1471:1471) (1558:1558:1558)) + (PORT datab (1783:1783:1783) (1836:1836:1836)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (2390:2390:2390) (2402:2402:2402)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2057:2057:2057) (2042:2042:2042)) + (PORT datab (2299:2299:2299) (2386:2386:2386)) + (PORT datac (2055:2055:2055) (2071:2071:2071)) + (PORT datad (1520:1520:1520) (1530:1530:1530)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1117:1117:1117) (1153:1153:1153)) + (PORT datab (817:817:817) (806:806:806)) + (PORT datac (2053:2053:2053) (2071:2071:2071)) + (PORT datad (2264:2264:2264) (2348:2348:2348)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (1909:1909:1909) (1895:1895:1895)) + (PORT datad (183:183:183) (209:209:209)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (775:775:775) (771:771:771)) + (PORT datab (772:772:772) (760:760:760)) + (PORT datac (1442:1442:1442) (1516:1516:1516)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (360:360:360)) + (PORT datab (180:180:180) (211:211:211)) + (PORT datac (1113:1113:1113) (1133:1133:1133)) + (PORT datad (803:803:803) (817:817:817)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~2) + (DELAY + (ABSOLUTE + (PORT datac (794:794:794) (776:776:776)) + (PORT datad (1264:1264:1264) (1241:1241:1241)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1356:1356:1356) (1343:1343:1343)) + (PORT datab (1113:1113:1113) (1110:1110:1110)) + (PORT datac (1616:1616:1616) (1660:1660:1660)) + (PORT datad (1349:1349:1349) (1370:1370:1370)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (830:830:830) (829:829:829)) + (PORT datab (624:624:624) (630:630:630)) + (PORT datac (1900:1900:1900) (1981:1981:1981)) + (PORT datad (1329:1329:1329) (1300:1300:1300)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (686:686:686) (755:755:755)) + (PORT datab (829:829:829) (825:825:825)) + (PORT datad (1115:1115:1115) (1107:1107:1107)) + (IOPATH dataa combout (273:273:273) (273:273:273)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de1) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1375:1375:1375)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1412:1412:1412) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (685:685:685) (754:754:754)) + (PORT datab (204:204:204) (247:247:247)) + (PORT datac (727:727:727) (707:707:707)) + (PORT datad (204:204:204) (264:264:264)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) + (DELAY + (ABSOLUTE + (PORT dataa (983:983:983) (1044:1044:1044)) + (PORT datab (850:850:850) (890:890:890)) + (PORT datac (1748:1748:1748) (1851:1851:1851)) + (PORT datad (1110:1110:1110) (1136:1136:1136)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~50) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (834:834:834)) + (PORT datab (426:426:426) (467:467:467)) + (PORT datac (392:392:392) (431:431:431)) + (PORT datad (903:903:903) (942:942:942)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1709:1709:1709) (1732:1732:1732)) + (PORT datab (189:189:189) (227:227:227)) + (PORT datac (622:622:622) (652:652:652)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1024:1024:1024) (1018:1018:1018)) + (PORT datab (1140:1140:1140) (1138:1138:1138)) + (PORT datac (1106:1106:1106) (1142:1142:1142)) + (PORT datad (164:164:164) (190:190:190)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (681:681:681)) + (PORT datab (1397:1397:1397) (1391:1391:1391)) + (PORT datac (1845:1845:1845) (1825:1825:1825)) + (PORT datad (1328:1328:1328) (1336:1336:1336)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (831:831:831)) + (PORT datab (200:200:200) (232:232:232)) + (PORT datac (294:294:294) (299:299:299)) + (PORT datad (551:551:551) (555:555:555)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (2614:2614:2614) (2718:2718:2718)) + (PORT datab (1021:1021:1021) (986:986:986)) + (PORT datac (1388:1388:1388) (1392:1392:1392)) + (PORT datad (1173:1173:1173) (1248:1248:1248)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (811:811:811)) + (PORT datab (195:195:195) (235:235:235)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (1436:1436:1436) (1492:1492:1492)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1156:1156:1156)) + (PORT datab (1300:1300:1300) (1293:1293:1293)) + (PORT datac (1113:1113:1113) (1107:1107:1107)) + (PORT datad (1327:1327:1327) (1322:1322:1322)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1152:1152:1152) (1166:1166:1166)) + (PORT datab (796:796:796) (828:828:828)) + (PORT datac (1606:1606:1606) (1607:1607:1607)) + (PORT datad (759:759:759) (806:806:806)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (708:708:708)) + (PORT datac (1267:1267:1267) (1320:1320:1320)) + (PORT datad (625:625:625) (672:672:672)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1010:1010:1010) (1017:1017:1017)) + (PORT datab (206:206:206) (243:243:243)) + (PORT datac (1274:1274:1274) (1289:1289:1289)) + (PORT datad (183:183:183) (210:210:210)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (668:668:668)) + (PORT datab (623:623:623) (657:657:657)) + (PORT datac (1110:1110:1110) (1135:1135:1135)) + (PORT datad (1026:1026:1026) (1009:1009:1009)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1039:1039:1039) (1044:1044:1044)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (162:162:162) (197:197:197)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel3) + (DELAY + (ABSOLUTE + (PORT dataa (2081:2081:2081) (2101:2101:2101)) + (PORT datac (1448:1448:1448) (1525:1525:1525)) + (PORT datad (1561:1561:1561) (1577:1577:1577)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1356:1356:1356) (1326:1326:1326)) + (PORT datab (1039:1039:1039) (1025:1025:1025)) + (PORT datac (294:294:294) (312:312:312)) + (PORT datad (562:562:562) (570:570:570)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1230:1230:1230)) + (PORT datab (908:908:908) (956:956:956)) + (PORT datac (822:822:822) (834:834:834)) + (PORT datad (578:578:578) (584:584:584)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (594:594:594)) + (PORT datab (1371:1371:1371) (1394:1394:1394)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (1156:1156:1156) (1172:1172:1172)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (950:950:950)) + (PORT datab (839:839:839) (839:839:839)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (817:817:817) (819:819:819)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (207:207:207) (254:254:254)) + (PORT datac (795:795:795) (811:811:811)) + (PORT datad (196:196:196) (225:225:225)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel0) + (DELAY + (ABSOLUTE + (PORT dataa (2182:2182:2182) (2183:2183:2183)) + (PORT datab (2529:2529:2529) (2637:2637:2637)) + (PORT datad (808:808:808) (822:822:822)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (603:603:603)) + (PORT datab (589:589:589) (603:603:603)) + (PORT datac (580:580:580) (574:574:574)) + (PORT datad (1058:1058:1058) (1058:1058:1058)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (592:592:592)) + (PORT datab (590:590:590) (585:585:585)) + (PORT datac (601:601:601) (615:615:615)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) + (DELAY + (ABSOLUTE + (PORT dataa (1308:1308:1308) (1424:1424:1424)) + (PORT datab (884:884:884) (898:898:898)) + (PORT datac (1188:1188:1188) (1237:1237:1237)) + (PORT datad (1100:1100:1100) (1097:1097:1097)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (867:867:867)) + (PORT datab (1251:1251:1251) (1224:1224:1224)) + (PORT datac (299:299:299) (318:318:318)) + (PORT datad (1316:1316:1316) (1289:1289:1289)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (611:611:611) (605:605:605)) + (PORT datac (854:854:854) (863:863:863)) + (PORT datad (166:166:166) (192:192:192)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (808:808:808) (819:819:819)) + (PORT datab (1304:1304:1304) (1378:1378:1378)) + (PORT datac (520:520:520) (515:515:515)) + (PORT datad (867:867:867) (924:924:924)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) + (DELAY + (ABSOLUTE + (PORT dataa (1248:1248:1248) (1235:1235:1235)) + (PORT datab (1719:1719:1719) (1804:1804:1804)) + (PORT datac (1747:1747:1747) (1842:1842:1842)) + (PORT datad (980:980:980) (970:970:970)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (265:265:265)) + (PORT datab (832:832:832) (833:833:833)) + (PORT datac (1576:1576:1576) (1618:1618:1618)) + (PORT datad (590:590:590) (596:596:596)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) + (DELAY + (ABSOLUTE + (PORT dataa (964:964:964) (914:914:914)) + (PORT datab (1353:1353:1353) (1337:1337:1337)) + (PORT datac (1715:1715:1715) (1659:1659:1659)) + (PORT datad (836:836:836) (828:828:828)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) + (DELAY + (ABSOLUTE + (PORT datab (833:833:833) (852:852:852)) + (PORT datac (1197:1197:1197) (1223:1223:1223)) + (PORT datad (758:758:758) (730:730:730)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (911:911:911)) + (PORT datab (1419:1419:1419) (1503:1503:1503)) + (PORT datac (2033:2033:2033) (2056:2056:2056)) + (PORT datad (1405:1405:1405) (1473:1473:1473)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (910:910:910)) + (PORT datab (1123:1123:1123) (1127:1127:1127)) + (PORT datac (763:763:763) (747:747:747)) + (PORT datad (541:541:541) (545:545:545)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (218:218:218)) + (PORT datab (1106:1106:1106) (1101:1101:1101)) + (PORT datac (518:518:518) (512:512:512)) + (PORT datad (579:579:579) (597:597:597)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1075:1075:1075) (1065:1065:1065)) + (PORT datab (1362:1362:1362) (1367:1367:1367)) + (PORT datac (990:990:990) (968:968:968)) + (PORT datad (1337:1337:1337) (1331:1331:1331)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (337:337:337)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (780:780:780) (787:787:787)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (387:387:387)) + (PORT datab (204:204:204) (249:249:249)) + (PORT datac (1103:1103:1103) (1089:1089:1089)) + (PORT datad (589:589:589) (605:605:605)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (792:792:792)) + (PORT datab (1590:1590:1590) (1584:1584:1584)) + (PORT datad (1678:1678:1678) (1714:1714:1714)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (687:687:687) (757:757:757)) + (PORT datab (829:829:829) (824:824:824)) + (PORT datad (1114:1114:1114) (1107:1107:1107)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de2) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1375:1375:1375)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1412:1412:1412) (1378:1378:1378)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (684:684:684) (752:752:752)) + (PORT datab (225:225:225) (296:296:296)) + (PORT datac (726:726:726) (707:707:707)) + (PORT datad (177:177:177) (209:209:209)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (259:259:259)) + (PORT datac (1300:1300:1300) (1260:1260:1260)) + (PORT datad (1721:1721:1721) (1698:1698:1698)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (258:258:258)) + (PORT datac (1297:1297:1297) (1258:1258:1258)) + (PORT datad (1724:1724:1724) (1699:1699:1699)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (911:911:911) (911:911:911)) + (PORT ena (1307:1307:1307) (1269:1269:1269)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) + (DELAY + (ABSOLUTE + (PORT datab (1590:1590:1590) (1588:1588:1588)) + (PORT datac (768:768:768) (766:766:766)) + (PORT datad (1676:1676:1676) (1712:1712:1712)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (914:914:914) (914:914:914)) + (PORT ena (764:764:764) (779:779:779)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (293:293:293)) + (PORT datab (1005:1005:1005) (991:991:991)) + (PORT datad (330:330:330) (372:372:372)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1347:1347:1347) (1359:1359:1359)) + (PORT datab (1041:1041:1041) (1033:1033:1033)) + (PORT datac (856:856:856) (895:895:895)) + (PORT datad (547:547:547) (535:535:535)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (391:391:391)) + (PORT datab (202:202:202) (237:237:237)) + (PORT datac (180:180:180) (227:227:227)) + (PORT datad (1210:1210:1210) (1178:1178:1178)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37npla28M3T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (1891:1891:1891) (1972:1972:1972)) + (PORT datab (1267:1267:1267) (1341:1341:1341)) + (PORT datac (1029:1029:1029) (1038:1038:1038)) + (PORT datad (825:825:825) (807:807:807)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (894:894:894)) + (PORT datab (1024:1024:1024) (1010:1010:1010)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (812:812:812) (791:791:791)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (1058:1058:1058) (1070:1070:1070)) + (PORT datab (892:892:892) (923:923:923)) + (PORT datac (1106:1106:1106) (1137:1137:1137)) + (PORT datad (2646:2646:2646) (2656:2656:2656)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (226:226:226)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (1257:1257:1257) (1240:1240:1240)) + (PORT datad (604:604:604) (595:595:595)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (2118:2118:2118) (2206:2206:2206)) + (PORT datab (1616:1616:1616) (1649:1649:1649)) + (PORT datac (1336:1336:1336) (1319:1319:1319)) + (PORT datad (1030:1030:1030) (1011:1011:1011)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1030:1030:1030) (1024:1024:1024)) + (PORT datab (1138:1138:1138) (1124:1124:1124)) + (PORT datac (1106:1106:1106) (1101:1101:1101)) + (PORT datad (2057:2057:2057) (2027:2027:2027)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1077:1077:1077) (1072:1072:1072)) + (PORT datab (181:181:181) (215:215:215)) + (PORT datac (789:789:789) (788:788:788)) + (PORT datad (1876:1876:1876) (1812:1812:1812)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1128:1128:1128) (1150:1150:1150)) + (PORT datab (1259:1259:1259) (1230:1230:1230)) + (PORT datac (832:832:832) (834:834:834)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1174:1174:1174) (1198:1198:1198)) + (PORT datad (801:801:801) (821:821:821)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (878:878:878)) + (PORT datab (617:617:617) (610:610:610)) + (PORT datac (1799:1799:1799) (1813:1813:1813)) + (PORT datad (1474:1474:1474) (1557:1557:1557)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (869:869:869)) + (PORT datab (903:903:903) (908:908:908)) + (PORT datac (1258:1258:1258) (1237:1237:1237)) + (PORT datad (551:551:551) (548:548:548)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1073:1073:1073) (1096:1096:1096)) + (PORT datab (599:599:599) (606:606:606)) + (PORT datac (839:839:839) (836:836:836)) + (PORT datad (796:796:796) (796:796:796)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (273:273:273)) + (PORT datab (866:866:866) (873:873:873)) + (PORT datac (1351:1351:1351) (1373:1373:1373)) + (PORT datad (777:777:777) (769:769:769)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (229:229:229)) + (PORT datab (188:188:188) (223:223:223)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (529:529:529) (531:531:531)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (636:636:636)) + (PORT datab (1486:1486:1486) (1494:1494:1494)) + (PORT datac (1186:1186:1186) (1219:1219:1219)) + (PORT datad (830:830:830) (839:839:839)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (562:562:562) (582:582:582)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (571:571:571) (566:566:566)) + (PORT datad (849:849:849) (861:861:861)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (345:345:345)) + (PORT datab (1124:1124:1124) (1130:1130:1130)) + (PORT datac (1481:1481:1481) (1444:1444:1444)) + (PORT datad (900:900:900) (905:905:905)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (179:179:179) (212:212:212)) + (PORT datac (578:578:578) (587:587:587)) + (PORT datad (798:798:798) (782:782:782)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1139:1139:1139) (1168:1168:1168)) + (PORT datab (1362:1362:1362) (1365:1365:1365)) + (PORT datac (1057:1057:1057) (1048:1048:1048)) + (PORT datad (1098:1098:1098) (1111:1111:1111)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (338:338:338)) + (PORT datab (1274:1274:1274) (1252:1252:1252)) + (PORT datac (993:993:993) (986:986:986)) + (PORT datad (1255:1255:1255) (1228:1228:1228)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (667:667:667)) + (PORT datab (850:850:850) (851:851:851)) + (PORT datad (1090:1090:1090) (1122:1122:1122)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~41) + (DELAY + (ABSOLUTE + (PORT dataa (2042:2042:2042) (2131:2131:2131)) + (PORT datab (1463:1463:1463) (1529:1529:1529)) + (PORT datac (1387:1387:1387) (1436:1436:1436)) + (PORT datad (804:804:804) (801:801:801)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1657:1657:1657) (1659:1659:1659)) + (PORT datab (1094:1094:1094) (1112:1112:1112)) + (PORT datac (1746:1746:1746) (1751:1751:1751)) + (PORT datad (1020:1020:1020) (1006:1006:1006)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (356:356:356)) + (PORT datab (591:591:591) (602:602:602)) + (PORT datac (579:579:579) (583:583:583)) + (PORT datad (552:552:552) (547:547:547)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1014:1014:1014) (1048:1048:1048)) + (PORT datab (806:806:806) (815:815:815)) + (PORT datac (1626:1626:1626) (1652:1652:1652)) + (PORT datad (1039:1039:1039) (1046:1046:1046)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (908:908:908)) + (PORT datab (820:820:820) (815:815:815)) + (PORT datac (856:856:856) (859:859:859)) + (PORT datad (1293:1293:1293) (1282:1282:1282)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (245:245:245)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (1096:1096:1096) (1097:1097:1097)) + (PORT datad (566:566:566) (586:586:586)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) + (DELAY + (ABSOLUTE + (PORT dataa (1087:1087:1087) (1135:1135:1135)) + (PORT datab (903:903:903) (925:925:925)) + (PORT datac (815:815:815) (823:823:823)) + (PORT datad (1126:1126:1126) (1142:1142:1142)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) + (DELAY + (ABSOLUTE + (PORT datab (207:207:207) (245:245:245)) + (PORT datac (561:561:561) (569:569:569)) + (PORT datad (197:197:197) (220:220:220)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) + (DELAY + (ABSOLUTE + (PORT dataa (1137:1137:1137) (1174:1174:1174)) + (PORT datab (892:892:892) (949:949:949)) + (PORT datac (594:594:594) (616:616:616)) + (PORT datad (1248:1248:1248) (1323:1323:1323)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (855:855:855)) + (PORT datab (1289:1289:1289) (1357:1357:1357)) + (PORT datac (596:596:596) (617:617:617)) + (PORT datad (331:331:331) (350:350:350)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal61\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1765:1765:1765) (1762:1762:1762)) + (PORT datab (1517:1517:1517) (1602:1602:1602)) + (PORT datac (566:566:566) (587:587:587)) + (PORT datad (1608:1608:1608) (1642:1642:1642)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1029:1029:1029) (1023:1023:1023)) + (PORT datab (852:852:852) (854:854:854)) + (PORT datac (2057:2057:2057) (2054:2054:2054)) + (PORT datad (1477:1477:1477) (1555:1555:1555)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1218:1218:1218) (1269:1269:1269)) + (PORT datab (860:860:860) (859:859:859)) + (PORT datac (2031:2031:2031) (2059:2059:2059)) + (PORT datad (1382:1382:1382) (1472:1472:1472)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~12) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (972:972:972)) + (PORT datab (821:821:821) (803:803:803)) + (PORT datac (188:188:188) (227:227:227)) + (PORT datad (184:184:184) (206:206:206)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (626:626:626)) + (PORT datab (1125:1125:1125) (1150:1150:1150)) + (PORT datac (1153:1153:1153) (1176:1176:1176)) + (PORT datad (526:526:526) (518:518:518)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (948:948:948)) + (PORT datab (1083:1083:1083) (1077:1077:1077)) + (PORT datac (1289:1289:1289) (1272:1272:1272)) + (PORT datad (834:834:834) (838:838:838)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (604:604:604)) + (PORT datab (849:849:849) (884:884:884)) + (PORT datac (1354:1354:1354) (1372:1372:1372)) + (PORT datad (1059:1059:1059) (1062:1062:1062)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (835:835:835)) + (PORT datab (1055:1055:1055) (1052:1052:1052)) + (PORT datac (331:331:331) (349:349:349)) + (PORT datad (165:165:165) (190:190:190)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1118:1118:1118) (1144:1144:1144)) + (PORT datab (189:189:189) (225:225:225)) + (PORT datac (168:168:168) (204:204:204)) + (PORT datad (1881:1881:1881) (1925:1925:1925)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) + (DELAY + (ABSOLUTE + (PORT datab (212:212:212) (254:254:254)) + (PORT datac (188:188:188) (226:226:226)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) + (DELAY + (ABSOLUTE + (PORT dataa (3401:3401:3401) (3385:3385:3385)) + (PORT datab (885:885:885) (944:944:944)) + (PORT datac (1137:1137:1137) (1176:1176:1176)) + (PORT datad (622:622:622) (645:645:645)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1856:1856:1856) (1921:1921:1921)) + (PORT datab (1365:1365:1365) (1354:1354:1354)) + (PORT datac (161:161:161) (196:196:196)) + (PORT datad (1227:1227:1227) (1339:1339:1339)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (728:728:728)) + (PORT datab (201:201:201) (234:234:234)) + (PORT datac (1480:1480:1480) (1470:1470:1470)) + (PORT datad (1365:1365:1365) (1396:1396:1396)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (975:975:975)) + (PORT datab (718:718:718) (788:788:788)) + (PORT datac (1351:1351:1351) (1371:1371:1371)) + (PORT datad (585:585:585) (616:616:616)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1889:1889:1889) (1925:1925:1925)) + (PORT datab (1042:1042:1042) (1016:1016:1016)) + (PORT datac (801:801:801) (797:797:797)) + (PORT datad (618:618:618) (644:644:644)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~39) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (972:972:972)) + (PORT datab (702:702:702) (761:761:761)) + (PORT datac (1354:1354:1354) (1371:1371:1371)) + (PORT datad (824:824:824) (850:850:850)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (239:239:239)) + (PORT datab (1367:1367:1367) (1357:1357:1357)) + (PORT datac (959:959:959) (937:937:937)) + (PORT datad (563:563:563) (594:594:594)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (900:900:900)) + (PORT datab (1159:1159:1159) (1171:1171:1171)) + (PORT datac (161:161:161) (196:196:196)) + (PORT datad (800:800:800) (801:801:801)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1609:1609:1609) (1650:1650:1650)) + (PORT datac (1264:1264:1264) (1262:1262:1262)) + (PORT datad (1570:1570:1570) (1629:1629:1629)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (591:591:591)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (988:988:988) (960:960:960)) + (PORT datad (776:776:776) (799:799:799)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (594:594:594)) + (PORT datab (1101:1101:1101) (1089:1089:1089)) + (PORT datac (471:471:471) (460:460:460)) + (PORT datad (174:174:174) (201:201:201)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (947:947:947)) + (PORT datab (1367:1367:1367) (1425:1425:1425)) + (PORT datac (172:172:172) (211:211:211)) + (PORT datad (188:188:188) (218:218:218)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1288:1288:1288) (1384:1384:1384)) + (PORT datac (1127:1127:1127) (1135:1135:1135)) + (PORT datad (1220:1220:1220) (1329:1329:1329)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1288:1288:1288) (1379:1379:1379)) + (PORT datab (1533:1533:1533) (1540:1540:1540)) + (PORT datac (1615:1615:1615) (1652:1652:1652)) + (PORT datad (164:164:164) (188:188:188)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1287:1287:1287) (1382:1382:1382)) + (PORT datab (2376:2376:2376) (2487:2487:2487)) + (PORT datac (1112:1112:1112) (1127:1127:1127)) + (PORT datad (822:822:822) (830:830:830)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1147:1147:1147) (1145:1145:1145)) + (PORT datab (571:571:571) (582:582:582)) + (PORT datac (189:189:189) (230:230:230)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1570:1570:1570) (1563:1563:1563)) + (PORT datab (2395:2395:2395) (2500:2500:2500)) + (PORT datac (1523:1523:1523) (1614:1614:1614)) + (PORT datad (1465:1465:1465) (1420:1420:1420)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1166:1166:1166) (1192:1192:1192)) + (PORT datab (1013:1013:1013) (1018:1018:1018)) + (PORT datac (1466:1466:1466) (1538:1538:1538)) + (PORT datad (1362:1362:1362) (1362:1362:1362)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~17) + (DELAY + (ABSOLUTE + (PORT datab (200:200:200) (234:234:234)) + (PORT datac (1007:1007:1007) (1002:1002:1002)) + (PORT datad (199:199:199) (234:234:234)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1365:1365:1365) (1351:1351:1351)) + (PORT datab (1439:1439:1439) (1439:1439:1439)) + (PORT datac (1389:1389:1389) (1385:1385:1385)) + (PORT datad (1822:1822:1822) (1821:1821:1821)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (893:893:893)) + (PORT datab (639:639:639) (637:637:637)) + (PORT datac (583:583:583) (587:587:587)) + (PORT datad (178:178:178) (199:199:199)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (230:230:230)) + (PORT datab (609:609:609) (599:599:599)) + (PORT datac (828:828:828) (837:837:837)) + (PORT datad (854:854:854) (881:881:881)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) + (DELAY + (ABSOLUTE + (PORT datab (188:188:188) (224:224:224)) + (PORT datac (1249:1249:1249) (1220:1220:1220)) + (PORT datad (764:764:764) (757:757:757)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~19) + (DELAY + (ABSOLUTE + (PORT dataa (819:819:819) (804:804:804)) + (PORT datab (1003:1003:1003) (1003:1003:1003)) + (PORT datac (485:485:485) (472:472:472)) + (PORT datad (489:489:489) (477:477:477)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1217:1217:1217) (1267:1267:1267)) + (PORT datab (2060:2060:2060) (2091:2091:2091)) + (PORT datac (1278:1278:1278) (1385:1385:1385)) + (PORT datad (834:834:834) (826:826:826)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) + (DELAY + (ABSOLUTE + (PORT dataa (1090:1090:1090) (1099:1099:1099)) + (PORT datab (1104:1104:1104) (1147:1147:1147)) + (PORT datac (820:820:820) (830:830:830)) + (PORT datad (1124:1124:1124) (1140:1140:1140)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (877:877:877)) + (PORT datab (854:854:854) (860:860:860)) + (PORT datac (1110:1110:1110) (1126:1126:1126)) + (PORT datad (541:541:541) (538:538:538)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1204:1204:1204) (1235:1235:1235)) + (PORT datab (1631:1631:1631) (1634:1634:1634)) + (PORT datac (722:722:722) (759:759:759)) + (PORT datad (1973:1973:1973) (1910:1910:1910)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1044:1044:1044) (1042:1042:1042)) + (PORT datab (1139:1139:1139) (1156:1156:1156)) + (PORT datad (841:841:841) (870:870:870)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (888:888:888)) + (PORT datab (624:624:624) (621:621:621)) + (PORT datac (777:777:777) (786:786:786)) + (PORT datad (800:800:800) (796:796:796)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) + (DELAY + (ABSOLUTE + (PORT datab (1071:1071:1071) (1065:1065:1065)) + (PORT datac (183:183:183) (220:220:220)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (622:622:622)) + (PORT datab (316:316:316) (336:336:336)) + (PORT datac (1070:1070:1070) (1054:1054:1054)) + (PORT datad (871:871:871) (879:879:879)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1043:1043:1043) (1041:1041:1041)) + (PORT datab (610:610:610) (640:640:640)) + (PORT datac (840:840:840) (845:845:845)) + (PORT datad (764:764:764) (754:754:754)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (241:241:241)) + (PORT datab (215:215:215) (259:259:259)) + (PORT datac (190:190:190) (231:231:231)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1207:1207:1207) (1213:1213:1213)) + (PORT datab (1872:1872:1872) (1914:1914:1914)) + (PORT datac (1809:1809:1809) (1847:1847:1847)) + (PORT datad (1204:1204:1204) (1236:1236:1236)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1130:1130:1130) (1119:1119:1119)) + (PORT datab (1122:1122:1122) (1132:1132:1132)) + (PORT datac (966:966:966) (942:942:942)) + (PORT datad (290:290:290) (297:297:297)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1978:1978:1978) (2041:2041:2041)) + (PORT datab (1564:1564:1564) (1667:1667:1667)) + (PORT datac (553:553:553) (549:549:549)) + (PORT datad (1865:1865:1865) (1883:1883:1883)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1923:1923:1923) (1915:1915:1915)) + (PORT datab (1098:1098:1098) (1116:1116:1116)) + (PORT datac (1337:1337:1337) (1316:1316:1316)) + (PORT datad (1270:1270:1270) (1276:1276:1276)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (829:829:829) (825:825:825)) + (PORT datab (631:631:631) (639:639:639)) + (PORT datac (1631:1631:1631) (1624:1624:1624)) + (PORT datad (1627:1627:1627) (1620:1620:1620)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1331:1331:1331) (1325:1325:1325)) + (PORT datab (846:846:846) (842:842:842)) + (PORT datac (1336:1336:1336) (1363:1363:1363)) + (PORT datad (782:782:782) (779:779:779)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (860:860:860)) + (PORT datab (183:183:183) (217:217:217)) + (PORT datac (581:581:581) (596:596:596)) + (PORT datad (553:553:553) (573:573:573)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (814:814:814)) + (PORT datab (182:182:182) (213:213:213)) + (PORT datac (162:162:162) (196:196:196)) + (PORT datad (751:751:751) (750:750:750)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (616:616:616)) + (PORT datab (606:606:606) (632:632:632)) + (PORT datac (590:590:590) (609:609:609)) + (PORT datad (323:323:323) (326:326:326)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1132:1132:1132) (1167:1167:1167)) + (PORT datab (1149:1149:1149) (1141:1141:1141)) + (PORT datac (584:584:584) (599:599:599)) + (PORT datad (1112:1112:1112) (1101:1101:1101)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (883:883:883) (872:872:872)) + (PORT datad (574:574:574) (584:584:584)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~17) + (DELAY + (ABSOLUTE + (PORT dataa (2178:2178:2178) (2226:2226:2226)) + (PORT datab (905:905:905) (916:916:916)) + (PORT datac (1006:1006:1006) (983:983:983)) + (PORT datad (1637:1637:1637) (1699:1699:1699)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (229:229:229)) + (PORT datab (830:830:830) (817:817:817)) + (PORT datac (1105:1105:1105) (1098:1098:1098)) + (PORT datad (1334:1334:1334) (1324:1324:1324)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datac (1564:1564:1564) (1560:1560:1560)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (599:599:599)) + (PORT datab (540:540:540) (539:539:539)) + (PORT datac (1371:1371:1371) (1397:1397:1397)) + (PORT datad (1516:1516:1516) (1493:1493:1493)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1181:1181:1181) (1185:1185:1185)) + (PORT datab (1078:1078:1078) (1064:1064:1064)) + (PORT datac (848:848:848) (873:873:873)) + (PORT datad (295:295:295) (293:293:293)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (232:232:232)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (973:973:973) (934:934:934)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1626:1626:1626) (1667:1667:1667)) + (PORT datab (835:835:835) (875:875:875)) + (PORT datac (1116:1116:1116) (1125:1125:1125)) + (PORT datad (2260:2260:2260) (2349:2349:2349)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) + (DELAY + (ABSOLUTE + (PORT datab (621:621:621) (610:610:610)) + (PORT datac (166:166:166) (202:202:202)) + (PORT datad (174:174:174) (201:201:201)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1117:1117:1117) (1155:1155:1155)) + (PORT datab (1474:1474:1474) (1568:1568:1568)) + (PORT datac (1396:1396:1396) (1463:1463:1463)) + (PORT datad (1638:1638:1638) (1670:1670:1670)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1922:1922:1922) (1914:1914:1914)) + (PORT datab (1176:1176:1176) (1201:1201:1201)) + (PORT datac (1386:1386:1386) (1381:1381:1381)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (294:294:294)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (378:378:378)) + (PORT datab (1176:1176:1176) (1202:1202:1202)) + (PORT datac (1067:1067:1067) (1061:1061:1061)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (244:244:244)) + (PORT datab (561:561:561) (562:562:562)) + (PORT datac (1264:1264:1264) (1263:1263:1263)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (645:645:645)) + (PORT datab (888:888:888) (899:899:899)) + (PORT datac (1386:1386:1386) (1384:1384:1384)) + (PORT datad (1093:1093:1093) (1120:1120:1120)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) + (DELAY + (ABSOLUTE + (PORT datab (200:200:200) (232:232:232)) + (PORT datac (1353:1353:1353) (1330:1330:1330)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1203:1203:1203) (1237:1237:1237)) + (PORT datab (1103:1103:1103) (1133:1133:1133)) + (PORT datac (1392:1392:1392) (1384:1384:1384)) + (PORT datad (596:596:596) (611:611:611)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (231:231:231)) + (PORT datab (1139:1139:1139) (1164:1164:1164)) + (PORT datac (1389:1389:1389) (1387:1387:1387)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1291:1291:1291) (1293:1293:1293)) + (PORT datab (1563:1563:1563) (1654:1654:1654)) + (PORT datac (908:908:908) (871:871:871)) + (PORT datad (184:184:184) (208:208:208)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1058:1058:1058) (1058:1058:1058)) + (PORT datab (617:617:617) (629:629:629)) + (PORT datac (586:586:586) (601:601:601)) + (PORT datad (591:591:591) (602:602:602)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1542:1542:1542) (1544:1544:1544)) + (PORT datab (1279:1279:1279) (1252:1252:1252)) + (PORT datac (1037:1037:1037) (1044:1044:1044)) + (PORT datad (571:571:571) (573:573:573)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1094:1094:1094) (1095:1095:1095)) + (PORT datab (1284:1284:1284) (1260:1260:1260)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (232:232:232)) + (PORT datab (620:620:620) (612:612:612)) + (PORT datac (169:169:169) (207:207:207)) + (PORT datad (171:171:171) (197:197:197)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (340:340:340)) + (PORT datab (748:748:748) (727:727:727)) + (PORT datac (1315:1315:1315) (1318:1318:1318)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1525:1525:1525) (1508:1508:1508)) + (PORT datab (1154:1154:1154) (1204:1204:1204)) + (PORT datac (1386:1386:1386) (1381:1381:1381)) + (PORT datad (1899:1899:1899) (1879:1879:1879)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1663:1663:1663) (1705:1705:1705)) + (PORT datab (1470:1470:1470) (1565:1565:1565)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (1503:1503:1503) (1469:1469:1469)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1419:1419:1419) (1416:1416:1416)) + (PORT datab (1622:1622:1622) (1635:1635:1635)) + (PORT datac (1407:1407:1407) (1403:1403:1403)) + (PORT datad (314:314:314) (314:314:314)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (294:294:294)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (673:673:673)) + (PORT datab (851:851:851) (861:861:861)) + (PORT datac (1593:1593:1593) (1608:1608:1608)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1418:1418:1418) (1413:1413:1413)) + (PORT datab (1028:1028:1028) (1008:1008:1008)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (1752:1752:1752) (1755:1755:1755)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (671:671:671)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (1000:1000:1000) (984:984:984)) + (PORT datad (1559:1559:1559) (1528:1528:1528)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1352:1352:1352) (1350:1350:1350)) + (PORT datab (181:181:181) (215:215:215)) + (PORT datac (592:592:592) (583:583:583)) + (PORT datad (1757:1757:1757) (1760:1760:1760)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (608:608:608)) + (PORT datab (571:571:571) (573:573:573)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1332:1332:1332) (1325:1325:1325)) + (PORT datab (907:907:907) (903:903:903)) + (PORT datac (1107:1107:1107) (1119:1119:1119)) + (PORT datad (1095:1095:1095) (1094:1094:1094)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1081:1081:1081) (1070:1070:1070)) + (PORT datab (1068:1068:1068) (1054:1054:1054)) + (PORT datac (162:162:162) (195:195:195)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1618:1618:1618) (1635:1635:1635)) + (PORT datab (1300:1300:1300) (1292:1292:1292)) + (PORT datac (1111:1111:1111) (1137:1137:1137)) + (PORT datad (1390:1390:1390) (1393:1393:1393)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1616:1616:1616) (1631:1631:1631)) + (PORT datab (1302:1302:1302) (1296:1296:1296)) + (PORT datac (1369:1369:1369) (1351:1351:1351)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1157:1157:1157) (1193:1193:1193)) + (PORT datab (1431:1431:1431) (1434:1434:1434)) + (PORT datac (854:854:854) (888:888:888)) + (PORT datad (888:888:888) (900:900:900)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1102:1102:1102) (1106:1106:1106)) + (PORT datab (923:923:923) (932:932:932)) + (PORT datac (850:850:850) (883:883:883)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (865:865:865)) + (PORT datab (1768:1768:1768) (1854:1854:1854)) + (PORT datac (1747:1747:1747) (1840:1840:1840)) + (PORT datad (982:982:982) (971:971:971)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1138:1138:1138) (1168:1168:1168)) + (PORT datab (1134:1134:1134) (1122:1122:1122)) + (PORT datac (786:786:786) (771:771:771)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (240:240:240)) + (PORT datab (570:570:570) (576:576:576)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (842:842:842) (838:838:838)) + (PORT datab (810:810:810) (829:829:829)) + (PORT datac (596:596:596) (607:607:607)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2681:2681:2681) (2642:2642:2642)) + (PORT datab (970:970:970) (1002:1002:1002)) + (PORT datac (174:174:174) (206:206:206)) + (PORT datad (2383:2383:2383) (2407:2407:2407)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1123:1123:1123) (1123:1123:1123)) + (PORT datab (1023:1023:1023) (1010:1010:1010)) + (PORT datac (1256:1256:1256) (1242:1242:1242)) + (PORT datad (1112:1112:1112) (1101:1101:1101)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1282:1282:1282) (1288:1288:1288)) + (PORT datab (575:575:575) (594:594:594)) + (PORT datac (569:569:569) (573:573:573)) + (PORT datad (643:643:643) (684:684:684)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (791:791:791) (804:804:804)) + (PORT datab (822:822:822) (822:822:822)) + (PORT datac (1885:1885:1885) (1859:1859:1859)) + (PORT datad (759:759:759) (758:758:758)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2177:2177:2177) (2222:2222:2222)) + (PORT datab (907:907:907) (916:916:916)) + (PORT datac (1739:1739:1739) (1694:1694:1694)) + (PORT datad (1640:1640:1640) (1700:1700:1700)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) + (DELAY + (ABSOLUTE + (PORT datac (1090:1090:1090) (1113:1113:1113)) + (PORT datad (1576:1576:1576) (1610:1610:1610)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1887:1887:1887) (1922:1922:1922)) + (PORT datab (615:615:615) (601:601:601)) + (PORT datac (802:802:802) (798:798:798)) + (PORT datad (618:618:618) (645:645:645)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (239:239:239)) + (PORT datab (188:188:188) (224:224:224)) + (PORT datac (803:803:803) (786:786:786)) + (PORT datad (317:317:317) (320:320:320)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1738:1738:1738) (1841:1841:1841)) + (PORT datab (1394:1394:1394) (1426:1426:1426)) + (PORT datac (1120:1120:1120) (1137:1137:1137)) + (PORT datad (567:567:567) (579:579:579)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (229:229:229)) + (PORT datab (201:201:201) (236:236:236)) + (PORT datac (550:550:550) (544:544:544)) + (PORT datad (773:773:773) (777:777:777)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1493:1493:1493) (1497:1497:1497)) + (PORT datab (936:936:936) (1002:1002:1002)) + (PORT datac (2072:2072:2072) (2153:2153:2153)) + (PORT datad (588:588:588) (588:588:588)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (353:353:353)) + (PORT datab (818:818:818) (847:847:847)) + (PORT datac (2032:2032:2032) (2055:2055:2055)) + (PORT datad (1080:1080:1080) (1077:1077:1077)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (585:585:585)) + (PORT datab (568:568:568) (580:580:580)) + (PORT datac (1007:1007:1007) (982:982:982)) + (PORT datad (1331:1331:1331) (1320:1320:1320)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (918:918:918)) + (PORT datab (1225:1225:1225) (1199:1199:1199)) + (PORT datac (1307:1307:1307) (1298:1298:1298)) + (PORT datad (165:165:165) (191:191:191)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1078:1078:1078) (1080:1080:1080)) + (PORT datab (844:844:844) (841:841:841)) + (PORT datac (580:580:580) (577:577:577)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1373:1373:1373) (1352:1352:1352)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (175:175:175) (206:206:206)) + (PORT datad (292:292:292) (299:299:299)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (844:844:844)) + (PORT datab (193:193:193) (231:231:231)) + (PORT datac (556:556:556) (560:560:560)) + (PORT datad (1328:1328:1328) (1338:1338:1338)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (870:870:870)) + (PORT datab (891:891:891) (910:910:910)) + (PORT datac (714:714:714) (694:694:694)) + (PORT datad (164:164:164) (189:189:189)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (593:593:593)) + (PORT datab (1736:1736:1736) (1689:1689:1689)) + (PORT datac (875:875:875) (877:877:877)) + (PORT datad (1155:1155:1155) (1170:1170:1170)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (228:228:228)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (537:537:537) (548:548:548)) + (PORT datad (1001:1001:1001) (990:990:990)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (352:352:352)) + (PORT datab (589:589:589) (606:606:606)) + (PORT datac (560:560:560) (568:568:568)) + (PORT datad (570:570:570) (580:580:580)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (855:855:855)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (154:154:154) (185:185:185)) + (PORT datad (1041:1041:1041) (1035:1035:1035)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (816:816:816)) + (PORT datab (2049:2049:2049) (2133:2133:2133)) + (PORT datac (1145:1145:1145) (1231:1231:1231)) + (PORT datad (2588:2588:2588) (2680:2680:2680)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) + (DELAY + (ABSOLUTE + (PORT dataa (561:561:561) (554:554:554)) + (PORT datab (631:631:631) (656:656:656)) + (PORT datac (867:867:867) (886:886:886)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (564:564:564)) + (PORT datac (826:826:826) (804:804:804)) + (PORT datad (775:775:775) (762:762:762)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1850:1850:1850) (1840:1840:1840)) + (PORT datab (340:340:340) (348:348:348)) + (PORT datad (818:818:818) (819:819:819)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_af) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1408:1408:1408) (1376:1376:1376)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1325:1325:1325) (1313:1313:1313)) + (PORT datab (1115:1115:1115) (1111:1111:1111)) + (PORT datac (792:792:792) (817:817:817)) + (PORT datad (1282:1282:1282) (1230:1230:1230)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) + (DELAY + (ABSOLUTE + (PORT dataa (1572:1572:1572) (1630:1630:1630)) + (PORT datac (577:577:577) (601:601:601)) + (PORT datad (1307:1307:1307) (1339:1339:1339)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1084:1084:1084) (1145:1145:1145)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1345:1345:1345) (1376:1376:1376)) + (PORT datab (600:600:600) (622:622:622)) + (PORT datad (1511:1511:1511) (1576:1576:1576)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) + (DELAY + (ABSOLUTE + (PORT dataa (1172:1172:1172) (1218:1218:1218)) + (PORT datab (836:836:836) (834:834:834)) + (PORT datac (1331:1331:1331) (1344:1344:1344)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) + (DELAY + (ABSOLUTE + (PORT datab (1358:1358:1358) (1380:1380:1380)) + (PORT datac (817:817:817) (829:829:829)) + (PORT datad (1133:1133:1133) (1178:1178:1178)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (934:934:934) (941:941:941)) + (PORT ena (1371:1371:1371) (1356:1356:1356)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) + (DELAY + (ABSOLUTE + (PORT dataa (1185:1185:1185) (1237:1237:1237)) + (PORT datab (833:833:833) (830:830:830)) + (PORT datac (1333:1333:1333) (1346:1346:1346)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (936:936:936) (944:944:944)) + (PORT ena (1360:1360:1360) (1335:1335:1335)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) + (DELAY + (ABSOLUTE + (PORT datab (1362:1362:1362) (1373:1373:1373)) + (PORT datac (819:819:819) (829:829:829)) + (PORT datad (1126:1126:1126) (1172:1172:1172)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (880:880:880)) + (PORT datab (222:222:222) (291:291:291)) + (PORT datad (838:838:838) (838:838:838)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (685:685:685) (754:754:754)) + (PORT datab (225:225:225) (296:296:296)) + (PORT datac (727:727:727) (707:707:707)) + (PORT datad (179:179:179) (214:214:214)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT datab (1357:1357:1357) (1374:1374:1374)) + (PORT datac (792:792:792) (804:804:804)) + (PORT datad (1131:1131:1131) (1179:1179:1179)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (753:753:753)) + (PORT datab (202:202:202) (245:245:245)) + (PORT datac (726:726:726) (705:705:705)) + (PORT datad (204:204:204) (264:264:264)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) + (DELAY + (ABSOLUTE + (PORT datab (1360:1360:1360) (1371:1371:1371)) + (PORT datac (782:782:782) (792:792:792)) + (PORT datad (1127:1127:1127) (1175:1175:1175)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) + (DELAY + (ABSOLUTE + (PORT datab (1363:1363:1363) (1375:1375:1375)) + (PORT datac (792:792:792) (802:802:802)) + (PORT datad (1137:1137:1137) (1188:1188:1188)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1308:1308:1308) (1329:1329:1329)) + (PORT ena (1425:1425:1425) (1417:1417:1417)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) + (DELAY + (ABSOLUTE + (PORT datab (1360:1360:1360) (1375:1375:1375)) + (PORT datac (780:780:780) (793:793:793)) + (PORT datad (1131:1131:1131) (1180:1180:1180)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1306:1306:1306) (1327:1327:1327)) + (PORT ena (1335:1335:1335) (1310:1310:1310)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (940:940:940)) + (PORT datab (891:891:891) (922:922:922)) + (PORT datad (327:327:327) (366:366:366)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (785:785:785) (828:828:828)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1367:1367:1367) (1357:1357:1357)) + (PORT datab (1119:1119:1119) (1117:1117:1117)) + (PORT datac (1612:1612:1612) (1654:1654:1654)) + (PORT datad (1352:1352:1352) (1371:1371:1371)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) + (DELAY + (ABSOLUTE + (PORT datab (1488:1488:1488) (1556:1556:1556)) + (PORT datac (1015:1015:1015) (1009:1009:1009)) + (PORT datad (324:324:324) (334:334:334)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) + (DELAY + (ABSOLUTE + (PORT datab (1485:1485:1485) (1552:1552:1552)) + (PORT datac (1013:1013:1013) (1008:1008:1008)) + (PORT datad (321:321:321) (332:332:332)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) + (DELAY + (ABSOLUTE + (PORT datab (1484:1484:1484) (1552:1552:1552)) + (PORT datad (1603:1603:1603) (1601:1601:1601)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1370:1370:1370) (1357:1357:1357)) + (PORT datab (1643:1643:1643) (1684:1684:1684)) + (PORT datac (312:312:312) (322:322:322)) + (PORT datad (1082:1082:1082) (1081:1081:1081)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1298:1298:1298) (1328:1328:1328)) + (PORT ena (1096:1096:1096) (1054:1054:1054)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) + (DELAY + (ABSOLUTE + (PORT datab (1483:1483:1483) (1550:1550:1550)) + (PORT datac (1014:1014:1014) (1004:1004:1004)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1355:1355:1355) (1342:1342:1342)) + (PORT datab (342:342:342) (364:364:364)) + (PORT datac (1616:1616:1616) (1661:1661:1661)) + (PORT datad (1075:1075:1075) (1073:1073:1073)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (440:440:440) (487:487:487)) + (PORT datab (460:460:460) (489:489:489)) + (PORT datad (590:590:590) (590:590:590)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (559:559:559) (578:578:578)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1326:1326:1326) (1314:1314:1314)) + (PORT datab (1115:1115:1115) (1111:1111:1111)) + (PORT datac (316:316:316) (327:327:327)) + (PORT datad (1283:1283:1283) (1231:1231:1231)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1356:1356:1356) (1345:1345:1345)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1369:1369:1369) (1355:1355:1355)) + (PORT datab (337:337:337) (358:358:358)) + (PORT datac (1299:1299:1299) (1287:1287:1287)) + (PORT datad (1080:1080:1080) (1080:1080:1080)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (626:626:626)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datac (162:162:162) (196:196:196)) + (PORT datad (190:190:190) (217:217:217)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1897:1897:1897) (1886:1886:1886)) + (PORT datab (1292:1292:1292) (1361:1361:1361)) + (PORT datac (1908:1908:1908) (1990:1990:1990)) + (PORT datad (812:812:812) (824:824:824)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) + (DELAY + (ABSOLUTE + (PORT dataa (971:971:971) (974:974:974)) + (PORT datab (1174:1174:1174) (1201:1201:1201)) + (PORT datac (1779:1779:1779) (1760:1760:1760)) + (PORT datad (339:339:339) (340:340:340)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (249:249:249)) + (PORT datac (548:548:548) (563:563:563)) + (PORT datad (763:763:763) (756:756:756)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (641:641:641)) + (PORT datab (196:196:196) (239:239:239)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (237:237:237)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (804:804:804) (787:787:787)) + (PORT datad (592:592:592) (603:603:603)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (926:926:926)) + (PORT datac (848:848:848) (859:859:859)) + (PORT datad (1123:1123:1123) (1140:1140:1140)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (877:877:877) (889:889:889)) + (PORT ena (1094:1094:1094) (1068:1068:1068)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (919:919:919)) + (PORT datac (847:847:847) (856:856:856)) + (PORT datad (1117:1117:1117) (1135:1135:1135)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (292:292:292)) + (PORT datab (887:887:887) (915:915:915)) + (PORT datad (806:806:806) (819:819:819)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1366:1366:1366) (1352:1352:1352)) + (PORT datab (1118:1118:1118) (1119:1119:1119)) + (PORT datac (310:310:310) (330:330:330)) + (PORT datad (536:536:536) (568:568:568)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1366:1366:1366) (1352:1352:1352)) + (PORT datab (564:564:564) (605:605:605)) + (PORT datac (313:313:313) (324:324:324)) + (PORT datad (1078:1078:1078) (1083:1083:1083)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT asdata (1320:1320:1320) (1353:1353:1353)) + (PORT ena (1076:1076:1076) (1044:1044:1044)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1362:1362:1362) (1351:1351:1351)) + (PORT datab (561:561:561) (603:603:603)) + (PORT datac (315:315:315) (326:326:326)) + (PORT datad (1073:1073:1073) (1078:1078:1078)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT asdata (1325:1325:1325) (1359:1359:1359)) + (PORT ena (1114:1114:1114) (1081:1081:1081)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1367:1367:1367) (1356:1356:1356)) + (PORT datab (1119:1119:1119) (1116:1116:1116)) + (PORT datac (309:309:309) (330:330:330)) + (PORT datad (536:536:536) (565:565:565)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (619:619:619)) + (PORT datab (222:222:222) (292:292:292)) + (PORT datad (598:598:598) (595:595:595)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1326:1326:1326) (1313:1313:1313)) + (PORT datab (1119:1119:1119) (1117:1117:1117)) + (PORT datac (794:794:794) (819:819:819)) + (PORT datad (1286:1286:1286) (1232:1232:1232)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) + (DELAY + (ABSOLUTE + (PORT dataa (1348:1348:1348) (1382:1382:1382)) + (PORT datab (832:832:832) (820:820:820)) + (PORT datad (1521:1521:1521) (1583:1583:1583)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (239:239:239)) + (PORT datab (1486:1486:1486) (1500:1500:1500)) + (PORT datac (825:825:825) (830:830:830)) + (PORT datad (191:191:191) (217:217:217)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1556:1556:1556) (1553:1553:1553)) + (PORT datab (368:368:368) (370:370:370)) + (PORT datac (163:163:163) (199:199:199)) + (PORT datad (824:824:824) (803:803:803)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) + (DELAY + (ABSOLUTE + (PORT dataa (1346:1346:1346) (1379:1379:1379)) + (PORT datab (837:837:837) (825:825:825)) + (PORT datad (1514:1514:1514) (1575:1575:1575)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1301:1301:1301) (1332:1332:1332)) + (PORT ena (1148:1148:1148) (1134:1134:1134)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (919:919:919)) + (PORT datab (1202:1202:1202) (1198:1198:1198)) + (PORT datad (808:808:808) (813:813:813)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (220:220:220)) + (PORT datab (1226:1226:1226) (1191:1191:1191)) + (PORT datac (312:312:312) (323:323:323)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (608:608:608)) + (PORT datab (512:512:512) (511:511:511)) + (PORT datac (768:768:768) (749:749:749)) + (PORT datad (952:952:952) (997:997:997)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (348:348:348)) + (PORT datab (1284:1284:1284) (1260:1260:1260)) + (PORT datac (1042:1042:1042) (1050:1050:1050)) + (PORT datad (570:570:570) (571:571:571)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (650:650:650)) + (PORT datab (833:833:833) (845:845:845)) + (PORT datac (1123:1123:1123) (1138:1138:1138)) + (PORT datad (523:523:523) (516:516:516)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (238:238:238)) + (PORT datab (808:808:808) (809:809:809)) + (PORT datac (312:312:312) (334:334:334)) + (PORT datad (1026:1026:1026) (1008:1008:1008)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (238:238:238)) + (PORT datab (200:200:200) (233:233:233)) + (PORT datac (572:572:572) (577:577:577)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (531:531:531)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (240:240:240)) + (PORT datab (202:202:202) (236:236:236)) + (PORT datac (176:176:176) (208:208:208)) + (PORT datad (179:179:179) (202:202:202)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (851:851:851)) + (PORT datab (1278:1278:1278) (1261:1261:1261)) + (PORT datac (1279:1279:1279) (1273:1273:1273)) + (PORT datad (732:732:732) (759:759:759)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (586:586:586)) + (PORT datab (1282:1282:1282) (1263:1263:1263)) + (PORT datac (383:383:383) (398:398:398)) + (PORT datad (189:189:189) (219:219:219)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1391:1391:1391) (1415:1415:1415)) + (PORT datab (786:786:786) (768:768:768)) + (PORT datac (745:745:745) (817:817:817)) + (PORT datad (777:777:777) (787:787:787)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (909:909:909)) + (PORT datab (1304:1304:1304) (1295:1295:1295)) + (PORT datac (1001:1001:1001) (1022:1022:1022)) + (PORT datad (185:185:185) (210:210:210)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1044:1044:1044) (1038:1038:1038)) + (PORT datab (1718:1718:1718) (1746:1746:1746)) + (PORT datac (789:789:789) (812:812:812)) + (PORT datad (579:579:579) (594:594:594)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1110:1110:1110) (1079:1079:1079)) + (PORT datab (1362:1362:1362) (1367:1367:1367)) + (PORT datac (1018:1018:1018) (978:978:978)) + (PORT datad (1114:1114:1114) (1144:1144:1144)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1138:1138:1138) (1170:1170:1170)) + (PORT datab (1085:1085:1085) (1074:1074:1074)) + (PORT datac (850:850:850) (861:861:861)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) + (DELAY + (ABSOLUTE + (PORT dataa (799:799:799) (802:802:802)) + (PORT datab (768:768:768) (746:746:746)) + (PORT datac (1484:1484:1484) (1457:1457:1457)) + (PORT datad (1024:1024:1024) (1012:1012:1012)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (956:956:956)) + (PORT datab (598:598:598) (602:602:602)) + (PORT datac (820:820:820) (818:818:818)) + (PORT datad (179:179:179) (202:202:202)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1397:1397:1397) (1397:1397:1397)) + (PORT datab (600:600:600) (607:607:607)) + (PORT datac (854:854:854) (860:860:860)) + (PORT datad (1112:1112:1112) (1101:1101:1101)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (237:237:237)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (1257:1257:1257) (1243:1243:1243)) + (PORT datad (549:549:549) (559:559:559)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1279:1279:1279) (1292:1292:1292)) + (PORT datab (353:353:353) (355:355:355)) + (PORT datac (583:583:583) (592:592:592)) + (PORT datad (644:644:644) (688:688:688)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (916:916:916)) + (PORT datab (789:789:789) (789:789:789)) + (PORT datac (513:513:513) (501:501:501)) + (PORT datad (1022:1022:1022) (1008:1008:1008)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1056:1056:1056) (1058:1058:1058)) + (PORT datab (861:861:861) (865:865:865)) + (PORT datac (1114:1114:1114) (1128:1128:1128)) + (PORT datad (1128:1128:1128) (1147:1147:1147)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) + (DELAY + (ABSOLUTE + (PORT datab (188:188:188) (222:222:222)) + (PORT datac (160:160:160) (193:193:193)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1037:1037:1037) (1020:1020:1020)) + (PORT datab (571:571:571) (577:577:577)) + (PORT datac (168:168:168) (206:206:206)) + (PORT datad (775:775:775) (747:747:747)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) + (DELAY + (ABSOLUTE + (PORT datab (1872:1872:1872) (1917:1917:1917)) + (PORT datac (1809:1809:1809) (1849:1849:1849)) + (PORT datad (1500:1500:1500) (1588:1588:1588)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1251:1251:1251) (1282:1282:1282)) + (PORT datab (1112:1112:1112) (1133:1133:1133)) + (PORT datac (1084:1084:1084) (1086:1086:1086)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) + (DELAY + (ABSOLUTE + (PORT datac (776:776:776) (784:784:784)) + (PORT datad (580:580:580) (583:583:583)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (530:530:530)) + (PORT datab (361:361:361) (365:365:365)) + (PORT datac (1011:1011:1011) (1003:1003:1003)) + (PORT datad (757:757:757) (738:738:738)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_xf) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~50) + (DELAY + (ABSOLUTE + (PORT dataa (1443:1443:1443) (1491:1491:1491)) + (PORT datab (1522:1522:1522) (1494:1494:1494)) + (PORT datac (1545:1545:1545) (1548:1548:1548)) + (PORT datad (1058:1058:1058) (1056:1056:1056)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (640:640:640)) + (PORT datab (1318:1318:1318) (1322:1322:1322)) + (PORT datac (857:857:857) (895:895:895)) + (PORT datad (295:295:295) (305:305:305)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (304:304:304) (408:408:408)) + (PORT datab (356:356:356) (368:368:368)) + (PORT datac (882:882:882) (893:893:893)) + (PORT datad (831:831:831) (832:832:832)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (796:796:796) (814:814:814)) + (PORT datab (1080:1080:1080) (1078:1078:1078)) + (PORT datad (544:544:544) (544:544:544)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (594:594:594)) + (PORT datab (373:373:373) (403:403:403)) + (PORT datac (840:840:840) (855:855:855)) + (PORT datad (1073:1073:1073) (1099:1099:1099)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1056:1056:1056) (1041:1041:1041)) + (PORT datad (1725:1725:1725) (1693:1693:1693)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1072:1072:1072) (1078:1078:1078)) + (PORT datab (1082:1082:1082) (1070:1070:1070)) + (PORT datac (1264:1264:1264) (1261:1261:1261)) + (PORT datad (1025:1025:1025) (1001:1001:1001)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (368:368:368)) + (PORT datab (1589:1589:1589) (1581:1581:1581)) + (PORT datac (1456:1456:1456) (1520:1520:1520)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) + (DELAY + (ABSOLUTE + (PORT datac (1301:1301:1301) (1264:1264:1264)) + (PORT datad (1722:1722:1722) (1699:1699:1699)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1072:1072:1072) (1078:1078:1078)) + (PORT datab (1083:1083:1083) (1071:1071:1071)) + (PORT datac (1265:1265:1265) (1261:1261:1261)) + (PORT datad (774:774:774) (759:759:759)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (623:623:623) (635:635:635)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (366:366:366)) + (PORT datab (1590:1590:1590) (1581:1581:1581)) + (PORT datac (1454:1454:1454) (1520:1520:1520)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1564:1564:1564) (1566:1566:1566)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (298:298:298)) + (PORT datab (1292:1292:1292) (1363:1363:1363)) + (PORT datad (197:197:197) (254:254:254)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) + (DELAY + (ABSOLUTE + (PORT dataa (1182:1182:1182) (1230:1230:1230)) + (PORT datac (945:945:945) (943:943:943)) + (PORT datad (1272:1272:1272) (1260:1260:1260)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (1057:1057:1057) (1044:1044:1044)) + (PORT datab (343:343:343) (364:364:364)) + (PORT datad (1725:1725:1725) (1696:1696:1696)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) + (DELAY + (ABSOLUTE + (PORT dataa (1176:1176:1176) (1225:1225:1225)) + (PORT datac (943:943:943) (941:941:941)) + (PORT datad (1268:1268:1268) (1254:1254:1254)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT asdata (1559:1559:1559) (1542:1542:1542)) + (PORT ena (1053:1053:1053) (1033:1033:1033)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (832:832:832) (853:853:853)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (1058:1058:1058) (1042:1042:1042)) + (PORT datab (340:340:340) (363:363:363)) + (PORT datad (1728:1728:1728) (1695:1695:1695)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1141:1141:1141) (1140:1140:1140)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (580:580:580) (600:600:600)) + (PORT datab (866:866:866) (878:878:878)) + (PORT datad (196:196:196) (253:253:253)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) + (DELAY + (ABSOLUTE + (PORT dataa (1168:1168:1168) (1208:1208:1208)) + (PORT datab (928:928:928) (954:954:954)) + (PORT datac (847:847:847) (859:859:859)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1274:1274:1274) (1242:1242:1242)) + (PORT datab (206:206:206) (244:244:244)) + (PORT datac (1029:1029:1029) (1015:1015:1015)) + (PORT datad (548:548:548) (578:578:578)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (749:749:749)) + (PORT datab (199:199:199) (232:232:232)) + (PORT datac (795:795:795) (774:774:774)) + (PORT datad (1264:1264:1264) (1239:1239:1239)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (885:885:885) (893:893:893)) + (PORT ena (1142:1142:1142) (1145:1145:1145)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1109:1109:1109) (1125:1125:1125)) + (PORT datab (626:626:626) (647:647:647)) + (PORT datad (880:880:880) (901:901:901)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) + (DELAY + (ABSOLUTE + (PORT dataa (1165:1165:1165) (1201:1201:1201)) + (PORT datab (931:931:931) (955:955:955)) + (PORT datac (848:848:848) (860:860:860)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (885:885:885) (895:895:895)) + (PORT ena (1081:1081:1081) (1050:1050:1050)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (409:409:409)) + (PORT datab (181:181:181) (214:214:214)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (312:312:312) (325:325:325)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1365:1365:1365) (1355:1355:1355)) + (PORT datab (1117:1117:1117) (1120:1120:1120)) + (PORT datac (1615:1615:1615) (1660:1660:1660)) + (PORT datad (509:509:509) (493:493:493)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT asdata (1043:1043:1043) (1033:1033:1033)) + (PORT ena (879:879:879) (881:881:881)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1617:1617:1617) (1645:1645:1645)) + (PORT datab (1285:1285:1285) (1240:1240:1240)) + (PORT datac (1030:1030:1030) (1013:1013:1013)) + (PORT datad (1038:1038:1038) (1007:1007:1007)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1068:1068:1068) (1049:1049:1049)) + (PORT datab (576:576:576) (613:613:613)) + (PORT datac (1247:1247:1247) (1207:1207:1207)) + (PORT datad (769:769:769) (735:735:735)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT asdata (1041:1041:1041) (1031:1031:1031)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1277:1277:1277) (1243:1243:1243)) + (PORT datab (205:205:205) (242:242:242)) + (PORT datac (1030:1030:1030) (1017:1017:1017)) + (PORT datad (550:550:550) (580:580:580)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (294:294:294)) + (PORT datab (220:220:220) (266:266:266)) + (PORT datad (193:193:193) (220:220:220)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (616:616:616)) + (PORT datab (608:608:608) (601:601:601)) + (PORT datac (707:707:707) (698:698:698)) + (PORT datad (559:559:559) (576:576:576)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) + (DELAY + (ABSOLUTE + (PORT dataa (1182:1182:1182) (1232:1232:1232)) + (PORT datac (779:779:779) (795:795:795)) + (PORT datad (1271:1271:1271) (1255:1255:1255)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) + (DELAY + (ABSOLUTE + (PORT dataa (1185:1185:1185) (1236:1236:1236)) + (PORT datac (792:792:792) (801:801:801)) + (PORT datad (1275:1275:1275) (1260:1260:1260)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT dataa (1185:1185:1185) (1236:1236:1236)) + (PORT datac (792:792:792) (801:801:801)) + (PORT datad (1275:1275:1275) (1260:1260:1260)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (1104:1104:1104) (1106:1106:1106)) + (PORT ena (901:901:901) (894:894:894)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (621:621:621) (652:652:652)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) + (DELAY + (ABSOLUTE + (PORT dataa (1184:1184:1184) (1236:1236:1236)) + (PORT datac (780:780:780) (792:792:792)) + (PORT datad (1273:1273:1273) (1260:1260:1260)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (843:843:843) (827:827:827)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (416:416:416)) + (PORT datab (410:410:410) (432:432:432)) + (PORT datad (198:198:198) (253:253:253)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1021:1021:1021) (1001:1001:1001)) + (PORT ena (1307:1307:1307) (1269:1269:1269)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1020:1020:1020) (999:999:999)) + (PORT ena (764:764:764) (779:779:779)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (287:287:287)) + (PORT datab (1005:1005:1005) (993:993:993)) + (PORT datad (337:337:337) (365:365:365)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (616:616:616)) + (PORT datab (598:598:598) (623:623:623)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~91) + (DELAY + (ABSOLUTE + (PORT dataa (1745:1745:1745) (1734:1734:1734)) + (PORT datab (1691:1691:1691) (1727:1727:1727)) + (PORT datac (190:190:190) (232:232:232)) + (PORT datad (179:179:179) (201:201:201)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (799:799:799) (807:807:807)) + (PORT datab (815:815:815) (812:812:812)) + (PORT datac (497:497:497) (492:492:492)) + (PORT datad (577:577:577) (581:581:581)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1086:1086:1086) (1094:1094:1094)) + (PORT datab (979:979:979) (971:971:971)) + (PORT datac (641:641:641) (669:669:669)) + (PORT datad (1049:1049:1049) (1030:1030:1030)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1069:1069:1069) (1128:1128:1128)) + (PORT datab (616:616:616) (657:657:657)) + (PORT datac (510:510:510) (498:498:498)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (496:496:496) (488:488:488)) + (PORT datab (593:593:593) (621:621:621)) + (PORT datac (588:588:588) (585:585:585)) + (PORT datad (158:158:158) (180:180:180)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1123:1123:1123) (1104:1104:1104)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (486:486:486) (512:512:512)) + (PORT ena (1129:1129:1129) (1100:1100:1100)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1355:1355:1355) (1350:1350:1350)) + (PORT datab (534:534:534) (534:534:534)) + (PORT datad (595:595:595) (596:596:596)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (408:408:408)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (564:564:564) (560:560:560)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (927:927:927)) + (PORT datab (409:409:409) (449:449:449)) + (PORT datac (1073:1073:1073) (1075:1075:1075)) + (PORT datad (391:391:391) (436:436:436)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (1662:1662:1662) (1674:1674:1674)) + (PORT datab (1139:1139:1139) (1137:1137:1137)) + (PORT datac (1106:1106:1106) (1142:1142:1142)) + (PORT datad (907:907:907) (944:944:944)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (836:836:836) (856:856:856)) + (PORT datad (168:168:168) (195:195:195)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) + (DELAY + (ABSOLUTE + (PORT dataa (1640:1640:1640) (1564:1564:1564)) + (PORT datab (1122:1122:1122) (1119:1119:1119)) + (PORT datac (593:593:593) (588:588:588)) + (PORT datad (759:759:759) (794:794:794)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (614:614:614)) + (PORT datab (607:607:607) (596:596:596)) + (PORT datad (816:816:816) (824:824:824)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (852:852:852)) + (PORT datab (1060:1060:1060) (1035:1035:1035)) + (PORT datac (1500:1500:1500) (1474:1474:1474)) + (PORT datad (816:816:816) (806:806:806)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (332:332:332)) + (PORT datab (847:847:847) (843:843:843)) + (PORT datac (1001:1001:1001) (980:980:980)) + (PORT datad (1002:1002:1002) (982:982:982)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1068:1068:1068) (1071:1071:1071)) + (PORT datab (761:761:761) (829:829:829)) + (PORT datac (1051:1051:1051) (1054:1054:1054)) + (PORT datad (729:729:729) (759:759:759)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1022:1022:1022) (1028:1028:1028)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (917:917:917) (919:919:919)) + (PORT datad (825:825:825) (840:840:840)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (978:978:978)) + (PORT datab (882:882:882) (935:935:935)) + (PORT datac (1012:1012:1012) (998:998:998)) + (PORT datad (179:179:179) (210:210:210)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (839:839:839)) + (PORT datab (778:778:778) (752:752:752)) + (PORT datac (383:383:383) (426:426:426)) + (PORT datad (591:591:591) (628:628:628)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1059:1059:1059) (1044:1044:1044)) + (PORT datab (364:364:364) (414:414:414)) + (PORT datac (1023:1023:1023) (1011:1011:1011)) + (PORT datad (594:594:594) (630:630:630)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (189:189:189) (227:227:227)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (564:564:564)) + (PORT datab (1498:1498:1498) (1501:1501:1501)) + (PORT datac (164:164:164) (200:200:200)) + (PORT datad (799:799:799) (796:796:796)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (714:714:714)) + (PORT datab (207:207:207) (242:242:242)) + (PORT datac (181:181:181) (217:217:217)) + (PORT datad (912:912:912) (919:919:919)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1358:1358:1358) (1353:1353:1353)) + (PORT datab (592:592:592) (597:597:597)) + (PORT datac (1104:1104:1104) (1121:1121:1121)) + (PORT datad (606:606:606) (602:602:602)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~25) + (DELAY + (ABSOLUTE + (PORT dataa (301:301:301) (408:408:408)) + (PORT datab (263:263:263) (344:344:344)) + (PORT datad (228:228:228) (290:290:290)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (623:623:623)) + (PORT datab (961:961:961) (937:937:937)) + (PORT datac (1121:1121:1121) (1148:1148:1148)) + (PORT datad (1887:1887:1887) (1822:1822:1822)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla20M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (973:973:973)) + (PORT datab (715:715:715) (790:790:790)) + (PORT datac (1353:1353:1353) (1374:1374:1374)) + (PORT datad (824:824:824) (855:855:855)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (737:737:737)) + (PORT datab (2279:2279:2279) (2310:2310:2310)) + (PORT datac (1242:1242:1242) (1219:1219:1219)) + (PORT datad (650:650:650) (715:715:715)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) + (DELAY + (ABSOLUTE + (PORT dataa (779:779:779) (758:758:758)) + (PORT datab (606:606:606) (624:624:624)) + (PORT datac (786:786:786) (780:780:780)) + (PORT datad (780:780:780) (781:781:781)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (983:983:983)) + (PORT datab (844:844:844) (833:833:833)) + (PORT datac (854:854:854) (905:905:905)) + (PORT datad (178:178:178) (207:207:207)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (1012:1012:1012)) + (PORT datab (179:179:179) (212:212:212)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) + (DELAY + (ABSOLUTE + (PORT dataa (1142:1142:1142) (1135:1135:1135)) + (PORT datab (1804:1804:1804) (1838:1838:1838)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (537:537:537) (526:526:526)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) + (DELAY + (ABSOLUTE + (PORT dataa (1319:1319:1319) (1338:1338:1338)) + (PORT datab (1389:1389:1389) (1406:1406:1406)) + (PORT datac (801:801:801) (811:811:811)) + (PORT datad (1086:1086:1086) (1080:1080:1080)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) + (DELAY + (ABSOLUTE + (PORT dataa (1090:1090:1090) (1090:1090:1090)) + (PORT datab (806:806:806) (787:787:787)) + (PORT datac (615:615:615) (651:651:651)) + (PORT datad (1016:1016:1016) (983:983:983)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) + (DELAY + (ABSOLUTE + (PORT dataa (1598:1598:1598) (1581:1581:1581)) + (PORT datab (1804:1804:1804) (1840:1840:1840)) + (PORT datac (567:567:567) (588:588:588)) + (PORT datad (770:770:770) (761:761:761)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1103:1103:1103) (1104:1104:1104)) + (PORT datab (648:648:648) (674:674:674)) + (PORT datac (174:174:174) (205:205:205)) + (PORT datad (621:621:621) (669:669:669)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (251:251:251)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (562:562:562) (571:571:571)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~18) + (DELAY + (ABSOLUTE + (PORT dataa (2023:2023:2023) (2066:2066:2066)) + (PORT datab (1348:1348:1348) (1390:1390:1390)) + (PORT datac (662:662:662) (696:696:696)) + (PORT datad (197:197:197) (224:224:224)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (980:980:980)) + (PORT datab (885:885:885) (937:937:937)) + (PORT datac (560:560:560) (565:565:565)) + (PORT datad (1091:1091:1091) (1076:1076:1076)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~17) + (DELAY + (ABSOLUTE + (PORT dataa (552:552:552) (551:551:551)) + (PORT datab (535:535:535) (535:535:535)) + (PORT datac (1994:1994:1994) (2036:2036:2036)) + (PORT datad (493:493:493) (486:486:486)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1276:1276:1276) (1286:1286:1286)) + (PORT datab (687:687:687) (722:722:722)) + (PORT datac (1995:1995:1995) (2033:2033:2033)) + (PORT datad (1179:1179:1179) (1191:1191:1191)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (943:943:943)) + (PORT datab (1247:1247:1247) (1298:1298:1298)) + (PORT datac (660:660:660) (695:695:695)) + (PORT datad (840:840:840) (843:843:843)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~20) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (231:231:231)) + (PORT datab (212:212:212) (254:254:254)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (165:165:165) (189:189:189)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~36) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (787:787:787)) + (PORT datab (707:707:707) (780:780:780)) + (PORT datac (578:578:578) (603:603:603)) + (PORT datad (650:650:650) (715:715:715)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~15) + (DELAY + (ABSOLUTE + (PORT dataa (561:561:561) (577:577:577)) + (PORT datab (686:686:686) (695:695:695)) + (PORT datac (1803:1803:1803) (1838:1838:1838)) + (PORT datad (748:748:748) (738:738:738)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~16) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (753:753:753)) + (PORT datab (709:709:709) (780:780:780)) + (PORT datac (687:687:687) (757:757:757)) + (PORT datad (1697:1697:1697) (1689:1689:1689)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~21) + (DELAY + (ABSOLUTE + (PORT dataa (623:623:623) (640:640:640)) + (PORT datab (187:187:187) (222:222:222)) + (PORT datac (489:489:489) (479:479:479)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) + (DELAY + (ABSOLUTE + (PORT dataa (1070:1070:1070) (1040:1040:1040)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (756:756:756) (746:746:746)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1531:1531:1531) (1505:1505:1505)) + (PORT datab (1830:1830:1830) (1865:1865:1865)) + (PORT datac (814:814:814) (825:825:825)) + (PORT datad (1331:1331:1331) (1291:1291:1291)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) + (DELAY + (ABSOLUTE + (PORT datab (707:707:707) (776:776:776)) + (PORT datac (684:684:684) (750:750:750)) + (PORT datad (937:937:937) (919:919:919)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~34) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (734:734:734)) + (PORT datab (2174:2174:2174) (2228:2228:2228)) + (PORT datac (684:684:684) (750:750:750)) + (PORT datad (599:599:599) (620:620:620)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~22) + (DELAY + (ABSOLUTE + (PORT datab (1067:1067:1067) (1099:1099:1099)) + (PORT datac (834:834:834) (870:870:870)) + (PORT datad (644:644:644) (701:701:701)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~23) + (DELAY + (ABSOLUTE + (PORT dataa (2305:2305:2305) (2330:2330:2330)) + (PORT datab (861:861:861) (868:868:868)) + (PORT datac (1046:1046:1046) (1044:1044:1044)) + (PORT datad (166:166:166) (189:189:189)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~35) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (842:842:842)) + (PORT datab (706:706:706) (777:777:777)) + (PORT datac (684:684:684) (750:750:750)) + (PORT datad (523:523:523) (513:513:513)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~24) + (DELAY + (ABSOLUTE + (PORT dataa (180:180:180) (216:216:216)) + (PORT datab (192:192:192) (231:231:231)) + (PORT datac (160:160:160) (192:192:192)) + (PORT datad (189:189:189) (213:213:213)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) + (DELAY + (ABSOLUTE + (PORT datab (357:357:357) (385:385:385)) + (PORT datad (818:818:818) (802:802:802)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) + (DELAY + (ABSOLUTE + (PORT dataa (986:986:986) (996:996:996)) + (PORT datab (418:418:418) (433:433:433)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (1857:1857:1857) (1786:1786:1786)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (949:949:949)) + (PORT datab (1248:1248:1248) (1304:1304:1304)) + (PORT datac (1994:1994:1994) (2038:2038:2038)) + (PORT datad (839:839:839) (848:848:848)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (345:345:345)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1477:1477:1477) (1439:1439:1439)) + (PORT datad (165:165:165) (188:188:188)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (642:642:642)) + (PORT datab (199:199:199) (232:232:232)) + (PORT datac (818:818:818) (825:825:825)) + (PORT datad (1308:1308:1308) (1323:1323:1323)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (218:218:218)) + (PORT datab (1342:1342:1342) (1353:1353:1353)) + (PORT datac (318:318:318) (328:328:328)) + (PORT datad (196:196:196) (224:224:224)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~95) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (788:788:788)) + (PORT datab (2175:2175:2175) (2233:2233:2233)) + (PORT datac (579:579:579) (602:602:602)) + (PORT datad (615:615:615) (672:672:672)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (638:638:638)) + (PORT datab (187:187:187) (223:223:223)) + (PORT datac (488:488:488) (477:477:477)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~27) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (233:233:233)) + (PORT datab (212:212:212) (254:254:254)) + (PORT datac (660:660:660) (698:698:698)) + (PORT datad (198:198:198) (227:227:227)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) + (DELAY + (ABSOLUTE + (PORT dataa (291:291:291) (399:399:399)) + (PORT datab (266:266:266) (348:348:348)) + (PORT datac (1052:1052:1052) (1044:1044:1044)) + (PORT datad (228:228:228) (288:288:288)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) + (DELAY + (ABSOLUTE + (PORT dataa (2023:2023:2023) (2066:2066:2066)) + (PORT datab (211:211:211) (251:251:251)) + (PORT datac (564:564:564) (584:584:584)) + (PORT datad (965:965:965) (912:912:912)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (216:216:216)) + (PORT datab (1345:1345:1345) (1353:1353:1353)) + (PORT datac (1343:1343:1343) (1335:1335:1335)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (531:531:531)) + (PORT datab (512:512:512) (500:500:500)) + (PORT datac (1262:1262:1262) (1225:1225:1225)) + (PORT datad (598:598:598) (600:600:600)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) + (DELAY + (ABSOLUTE + (PORT dataa (527:527:527) (519:519:519)) + (PORT datab (193:193:193) (234:234:234)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (191:191:191) (217:217:217)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (582:582:582) (600:600:600)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (563:563:563) (568:568:568)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (813:813:813)) + (PORT datab (1880:1880:1880) (1816:1816:1816)) + (PORT datac (752:752:752) (732:732:732)) + (PORT datad (818:818:818) (802:802:802)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~26) + (DELAY + (ABSOLUTE + (PORT datab (195:195:195) (237:237:237)) + (PORT datac (163:163:163) (196:196:196)) + (PORT datad (193:193:193) (220:220:220)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (1815:1815:1815) (1845:1845:1845)) + (PORT datac (766:766:766) (811:811:811)) + (PORT datad (506:506:506) (495:495:495)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (373:373:373)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (565:565:565) (571:571:571)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (248:248:248)) + (PORT datab (200:200:200) (233:233:233)) + (PORT datac (174:174:174) (206:206:206)) + (PORT datad (164:164:164) (190:190:190)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~89) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (583:583:583)) + (PORT datab (200:200:200) (232:232:232)) + (PORT datad (315:315:315) (319:319:319)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~90) + (DELAY + (ABSOLUTE + (PORT dataa (1114:1114:1114) (1101:1101:1101)) + (PORT datab (417:417:417) (432:432:432)) + (PORT datac (684:684:684) (722:722:722)) + (PORT datad (1779:1779:1779) (1810:1810:1810)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~91) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (1127:1127:1127) (1134:1134:1134)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (1854:1854:1854) (1784:1784:1784)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) + (DELAY + (ABSOLUTE + (PORT dataa (855:855:855) (853:853:853)) + (PORT datab (876:876:876) (893:893:893)) + (PORT datac (882:882:882) (933:933:933)) + (PORT datad (1152:1152:1152) (1192:1192:1192)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) + (DELAY + (ABSOLUTE + (PORT dataa (815:815:815) (827:827:827)) + (PORT datab (515:515:515) (515:515:515)) + (PORT datac (2452:2452:2452) (2414:2414:2414)) + (PORT datad (303:303:303) (306:306:306)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~100) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (979:979:979)) + (PORT datab (719:719:719) (792:792:792)) + (PORT datac (669:669:669) (731:731:731)) + (PORT datad (1501:1501:1501) (1487:1487:1487)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~92) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (506:506:506) (493:493:493)) + (PORT datad (1854:1854:1854) (1784:1784:1784)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1191:1191:1191) (1228:1228:1228)) + (PORT datab (1375:1375:1375) (1383:1383:1383)) + (PORT datac (568:568:568) (602:602:602)) + (PORT datad (761:761:761) (794:794:794)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (813:813:813)) + (PORT datab (188:188:188) (223:223:223)) + (PORT datac (1015:1015:1015) (973:973:973)) + (PORT datad (330:330:330) (355:355:355)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~29) + (DELAY + (ABSOLUTE + (PORT dataa (2305:2305:2305) (2327:2327:2327)) + (PORT datab (889:889:889) (898:898:898)) + (PORT datac (1224:1224:1224) (1213:1213:1213)) + (PORT datad (791:791:791) (794:794:794)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~30) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (428:428:428)) + (PORT datab (889:889:889) (897:897:897)) + (PORT datac (1245:1245:1245) (1230:1230:1230)) + (PORT datad (165:165:165) (189:189:189)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~31) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (427:427:427)) + (PORT datab (817:817:817) (829:829:829)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~32) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (344:344:344)) + (PORT datab (355:355:355) (384:384:384)) + (PORT datac (163:163:163) (199:199:199)) + (PORT datad (817:817:817) (802:802:802)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~93) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (217:217:217)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (1857:1857:1857) (1785:1785:1785)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) + (DELAY + (ABSOLUTE + (PORT datab (1301:1301:1301) (1280:1280:1280)) + (PORT datac (1278:1278:1278) (1259:1259:1259)) + (PORT datad (988:988:988) (992:992:992)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT asdata (909:909:909) (921:921:921)) + (PORT ena (1053:1053:1053) (1033:1033:1033)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT asdata (909:909:909) (921:921:921)) + (PORT ena (1141:1141:1141) (1140:1140:1140)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (580:580:580) (600:600:600)) + (PORT datab (865:865:865) (882:882:882)) + (PORT datad (197:197:197) (255:255:255)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (623:623:623) (622:622:622)) + (PORT ena (1142:1142:1142) (1145:1145:1145)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (300:300:300) (403:403:403)) + (PORT datab (872:872:872) (869:869:869)) + (PORT datac (886:886:886) (898:898:898)) + (PORT datad (177:177:177) (198:198:198)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (812:812:812) (822:822:822)) + (PORT datab (818:818:818) (824:824:824)) + (PORT datac (740:740:740) (732:732:732)) + (PORT datad (525:525:525) (521:521:521)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1160:1160:1160) (1177:1177:1177)) + (PORT ena (1425:1425:1425) (1417:1417:1417)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1163:1163:1163) (1181:1181:1181)) + (PORT ena (1335:1335:1335) (1310:1310:1310)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (933:933:933)) + (PORT datab (889:889:889) (916:916:916)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (905:905:905) (911:911:911)) + (PORT ena (1360:1360:1360) (1335:1335:1335)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (594:594:594) (602:602:602)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1371:1371:1371) (1356:1356:1356)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (883:883:883)) + (PORT datab (878:878:878) (877:877:877)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1040:1040:1040) (1095:1095:1095)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1352:1352:1352) (1383:1383:1383)) + (PORT datab (608:608:608) (630:630:630)) + (PORT datad (1525:1525:1525) (1587:1587:1587)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (588:588:588) (609:609:609)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1094:1094:1094) (1068:1068:1068)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (925:925:925) (954:954:954)) + (PORT ena (1356:1356:1356) (1345:1345:1345)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (292:292:292)) + (PORT datab (884:884:884) (907:907:907)) + (PORT datad (807:807:807) (826:826:826)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1364:1364:1364)) + (PORT asdata (1055:1055:1055) (1091:1091:1091)) + (PORT ena (1103:1103:1103) (1073:1073:1073)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT asdata (1383:1383:1383) (1382:1382:1382)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (661:661:661)) + (PORT datab (200:200:200) (232:232:232)) + (PORT datad (544:544:544) (535:535:535)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT asdata (1159:1159:1159) (1174:1174:1174)) + (PORT ena (1114:1114:1114) (1081:1081:1081)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT asdata (1159:1159:1159) (1176:1176:1176)) + (PORT ena (1076:1076:1076) (1044:1044:1044)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (622:622:622)) + (PORT datab (221:221:221) (289:289:289)) + (PORT datad (597:597:597) (593:593:593)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1353:1353:1353)) + (PORT asdata (1428:1428:1428) (1491:1491:1491)) + (PORT ena (1148:1148:1148) (1139:1139:1139)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (771:771:771) (818:818:818)) + (PORT datab (1185:1185:1185) (1170:1170:1170)) + (PORT datad (578:578:578) (579:579:579)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (611:611:611)) + (PORT datab (744:744:744) (776:776:776)) + (PORT datac (555:555:555) (560:560:560)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (780:780:780) (765:765:765)) + (PORT datab (953:953:953) (974:974:974)) + (PORT datac (313:313:313) (320:320:320)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1072:1072:1072) (1088:1088:1088)) + (PORT datab (1292:1292:1292) (1268:1268:1268)) + (PORT datac (860:860:860) (893:893:893)) + (PORT datad (1252:1252:1252) (1235:1235:1235)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) + (DELAY + (ABSOLUTE + (PORT dataa (2397:2397:2397) (2425:2425:2425)) + (PORT datab (186:186:186) (220:220:220)) + (PORT datac (154:154:154) (183:183:183)) + (PORT datad (177:177:177) (198:198:198)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) + (DELAY + (ABSOLUTE + (PORT datac (1037:1037:1037) (1023:1023:1023)) + (PORT datad (1326:1326:1326) (1313:1313:1313)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (629:629:629)) + (PORT datab (870:870:870) (864:864:864)) + (PORT datac (1054:1054:1054) (1058:1058:1058)) + (PORT datad (164:164:164) (188:188:188)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1082:1082:1082) (1086:1086:1086)) + (PORT datac (843:843:843) (837:837:837)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1080:1080:1080) (1083:1083:1083)) + (PORT datab (872:872:872) (868:868:868)) + (PORT datac (1032:1032:1032) (1015:1015:1015)) + (PORT datad (1319:1319:1319) (1306:1306:1306)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (400:400:400) (439:439:439)) + (PORT datac (522:522:522) (523:523:523)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT asdata (630:630:630) (644:644:644)) + (PORT ena (1053:1053:1053) (1033:1033:1033)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT asdata (631:631:631) (645:645:645)) + (PORT ena (1141:1141:1141) (1140:1140:1140)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (581:581:581) (602:602:602)) + (PORT datab (869:869:869) (878:878:878)) + (PORT datad (196:196:196) (252:252:252)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1158:1158:1158) (1167:1167:1167)) + (PORT ena (1307:1307:1307) (1269:1269:1269)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1158:1158:1158) (1169:1169:1169)) + (PORT ena (764:764:764) (779:779:779)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (286:286:286)) + (PORT datab (1010:1010:1010) (988:988:988)) + (PORT datad (337:337:337) (370:370:370)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (846:846:846) (834:834:834)) + (PORT ena (843:843:843) (827:827:827)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (846:846:846) (834:834:834)) + (PORT ena (901:901:901) (894:894:894)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (414:414:414)) + (PORT datab (219:219:219) (287:287:287)) + (PORT datad (381:381:381) (400:400:400)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1305:1305:1305) (1278:1278:1278)) + (PORT ena (763:763:763) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1173:1173:1173) (1216:1216:1216)) + (PORT datab (925:925:925) (947:947:947)) + (PORT datad (832:832:832) (834:834:834)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1349:1349:1349) (1339:1339:1339)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1377:1377:1377) (1429:1429:1429)) + (PORT datab (1414:1414:1414) (1477:1477:1477)) + (PORT datac (1972:1972:1972) (1922:1922:1922)) + (PORT datad (585:585:585) (590:590:590)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (257:257:257)) + (PORT datab (673:673:673) (709:709:709)) + (PORT datac (824:824:824) (833:833:833)) + (PORT datad (1080:1080:1080) (1072:1072:1072)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (869:869:869)) + (PORT datab (599:599:599) (600:600:600)) + (PORT datac (1199:1199:1199) (1198:1198:1198)) + (PORT datad (312:312:312) (313:313:313)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT datab (763:763:763) (805:805:805)) + (PORT datac (656:656:656) (717:717:717)) + (PORT datad (595:595:595) (612:612:612)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (825:825:825)) + (PORT datab (1302:1302:1302) (1274:1274:1274)) + (PORT datac (184:184:184) (219:219:219)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (185:185:185) (221:221:221)) + (PORT datad (1182:1182:1182) (1162:1162:1162)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1125:1125:1125) (1134:1134:1134)) + (PORT datac (1889:1889:1889) (1953:1953:1953)) + (PORT datad (1208:1208:1208) (1276:1276:1276)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~10) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (612:612:612)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (507:507:507) (498:498:498)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1796:1796:1796) (1890:1890:1890)) + (PORT datab (1390:1390:1390) (1377:1377:1377)) + (PORT datac (1014:1014:1014) (1003:1003:1003)) + (PORT datad (1448:1448:1448) (1537:1537:1537)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1678:1678:1678) (1701:1701:1701)) + (PORT datab (1472:1472:1472) (1565:1565:1565)) + (PORT datac (2902:2902:2902) (2899:2899:2899)) + (PORT datad (1751:1751:1751) (1849:1849:1849)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1365:1365:1365) (1347:1347:1347)) + (PORT datab (1833:1833:1833) (1840:1840:1840)) + (PORT datac (1410:1410:1410) (1412:1412:1412)) + (PORT datad (1638:1638:1638) (1668:1668:1668)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~11) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (216:216:216)) + (PORT datab (180:180:180) (211:211:211)) + (PORT datac (160:160:160) (192:192:192)) + (PORT datad (1433:1433:1433) (1464:1464:1464)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~12) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (573:573:573)) + (PORT datab (563:563:563) (579:579:579)) + (PORT datac (585:585:585) (578:578:578)) + (PORT datad (320:320:320) (321:321:321)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (259:259:259)) + (PORT datab (628:628:628) (629:629:629)) + (PORT datac (955:955:955) (919:919:919)) + (PORT datad (548:548:548) (556:556:556)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (869:869:869)) + (PORT datab (602:602:602) (608:608:608)) + (PORT datac (1623:1623:1623) (1632:1632:1632)) + (PORT datad (520:520:520) (513:513:513)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (564:564:564)) + (PORT datab (601:601:601) (611:611:611)) + (PORT datac (162:162:162) (198:198:198)) + (PORT datad (867:867:867) (876:876:876)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) + (DELAY + (ABSOLUTE + (PORT datac (523:523:523) (522:522:522)) + (PORT datad (1012:1012:1012) (991:991:991)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1857:1857:1857) (1920:1920:1920)) + (PORT datab (1326:1326:1326) (1322:1322:1322)) + (PORT datad (1229:1229:1229) (1341:1341:1341)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (919:919:919)) + (PORT datab (922:922:922) (934:934:934)) + (PORT datac (1352:1352:1352) (1367:1367:1367)) + (PORT datad (1139:1139:1139) (1183:1183:1183)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (229:229:229)) + (PORT datab (904:904:904) (909:909:909)) + (PORT datac (853:853:853) (883:883:883)) + (PORT datad (887:887:887) (895:895:895)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1721:1721:1721) (1670:1670:1670)) + (PORT datab (187:187:187) (224:224:224)) + (PORT datac (547:547:547) (564:564:564)) + (PORT datad (1461:1461:1461) (1413:1413:1413)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1294:1294:1294) (1311:1311:1311)) + (PORT datab (1247:1247:1247) (1363:1363:1363)) + (PORT datac (1028:1028:1028) (1023:1023:1023)) + (PORT datad (1239:1239:1239) (1335:1335:1335)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (242:242:242)) + (PORT datab (589:589:589) (611:611:611)) + (PORT datad (313:313:313) (317:317:317)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S) + (DELAY + (ABSOLUTE + (PORT dataa (1018:1018:1018) (995:995:995)) + (PORT datab (762:762:762) (755:755:755)) + (PORT datac (526:526:526) (522:522:522)) + (PORT datad (511:511:511) (495:495:495)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal73\~2) + (DELAY + (ABSOLUTE + (PORT dataa (916:916:916) (980:980:980)) + (PORT datab (824:824:824) (808:808:808)) + (PORT datac (953:953:953) (1027:1027:1027)) + (PORT datad (1172:1172:1172) (1217:1217:1217)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (652:652:652)) + (PORT datab (853:853:853) (887:887:887)) + (PORT datac (1351:1351:1351) (1371:1371:1371)) + (PORT datad (1063:1063:1063) (1064:1064:1064)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R) + (DELAY + (ABSOLUTE + (PORT dataa (1035:1035:1035) (1026:1026:1026)) + (PORT datab (326:326:326) (350:350:350)) + (PORT datac (523:523:523) (521:521:521)) + (PORT datad (992:992:992) (968:968:968)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) + (DELAY + (ABSOLUTE + (PORT datab (204:204:204) (241:241:241)) + (PORT datac (557:557:557) (564:564:564)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (240:240:240)) + (PORT datab (188:188:188) (223:223:223)) + (PORT datac (801:801:801) (800:800:800)) + (PORT datad (552:552:552) (539:539:539)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (621:621:621)) + (PORT datab (1417:1417:1417) (1421:1421:1421)) + (PORT datac (887:887:887) (900:900:900)) + (PORT datad (1282:1282:1282) (1295:1295:1295)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) + (DELAY + (ABSOLUTE + (PORT dataa (802:802:802) (803:803:803)) + (PORT datab (528:528:528) (516:516:516)) + (PORT datac (745:745:745) (731:731:731)) + (PORT datad (780:780:780) (770:770:770)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) + (DELAY + (ABSOLUTE + (PORT dataa (248:248:248) (309:309:309)) + (PORT datab (1629:1629:1629) (1629:1629:1629)) + (PORT datac (223:223:223) (275:275:275)) + (PORT datad (1118:1118:1118) (1123:1123:1123)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1609:1609:1609) (1646:1646:1646)) + (PORT datab (824:824:824) (809:809:809)) + (PORT datac (794:794:794) (801:801:801)) + (PORT datad (1702:1702:1702) (1792:1792:1792)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1610:1610:1610) (1647:1647:1647)) + (PORT datab (1592:1592:1592) (1659:1659:1659)) + (PORT datac (794:794:794) (803:803:803)) + (PORT datad (1938:1938:1938) (2052:2052:2052)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (225:225:225)) + (PORT datab (199:199:199) (243:243:243)) + (PORT datac (163:163:163) (198:198:198)) + (PORT datad (183:183:183) (207:207:207)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (662:662:662) (663:663:663)) + (PORT ena (1360:1360:1360) (1335:1335:1335)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (661:661:661) (665:665:665)) + (PORT ena (1371:1371:1371) (1356:1356:1356)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (885:885:885)) + (PORT datab (881:881:881) (880:880:880)) + (PORT datad (197:197:197) (254:254:254)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1160:1160:1160) (1163:1163:1163)) + (PORT ena (1425:1425:1425) (1417:1417:1417)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1162:1162:1162) (1165:1165:1165)) + (PORT ena (1335:1335:1335) (1310:1310:1310)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (939:939:939)) + (PORT datab (893:893:893) (924:924:924)) + (PORT datad (196:196:196) (252:252:252)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (914:914:914) (931:931:931)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1348:1348:1348) (1383:1383:1383)) + (PORT datab (601:601:601) (621:621:621)) + (PORT datad (1515:1515:1515) (1580:1580:1580)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT asdata (1632:1632:1632) (1652:1652:1652)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1763:1763:1763) (1774:1774:1774)) + (PORT ena (1096:1096:1096) (1054:1054:1054)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (626:626:626)) + (PORT datab (459:459:459) (488:488:488)) + (PORT datad (590:590:590) (590:590:590)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1353:1353:1353)) + (PORT asdata (1355:1355:1355) (1361:1361:1361)) + (PORT ena (1148:1148:1148) (1139:1139:1139)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (774:774:774) (828:828:828)) + (PORT datab (616:616:616) (615:615:615)) + (PORT datad (1148:1148:1148) (1138:1138:1138)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1356:1356:1356) (1345:1345:1345)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (833:833:833) (827:827:827)) + (PORT ena (1094:1094:1094) (1068:1068:1068)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (867:867:867)) + (PORT datab (220:220:220) (289:289:289)) + (PORT datad (845:845:845) (878:878:878)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT asdata (918:918:918) (944:944:944)) + (PORT ena (1076:1076:1076) (1044:1044:1044)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT asdata (916:916:916) (944:944:944)) + (PORT ena (1114:1114:1114) (1081:1081:1081)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (619:619:619)) + (PORT datab (220:220:220) (287:287:287)) + (PORT datad (597:597:597) (588:588:588)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (593:593:593)) + (PORT datab (772:772:772) (813:813:813)) + (PORT datac (537:537:537) (528:528:528)) + (PORT datad (547:547:547) (542:542:542)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (760:760:760) (750:750:750)) + (PORT datab (956:956:956) (948:948:948)) + (PORT datac (757:757:757) (777:777:777)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (925:925:925)) + (PORT datac (877:877:877) (896:896:896)) + (PORT datad (1124:1124:1124) (1141:1141:1141)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1364:1364:1364)) + (PORT asdata (1079:1079:1079) (1062:1062:1062)) + (PORT ena (1070:1070:1070) (1040:1040:1040)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (921:921:921)) + (PORT datab (906:906:906) (921:921:921)) + (PORT datac (1134:1134:1134) (1176:1176:1176)) + (PORT datad (1039:1039:1039) (1007:1007:1007)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1375:1375:1375) (1413:1413:1413)) + (PORT datab (543:543:543) (547:547:547)) + (PORT datad (530:530:530) (529:529:529)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (DELAY + (ABSOLUTE + (PORT datab (915:915:915) (923:923:923)) + (PORT datac (864:864:864) (891:891:891)) + (PORT datad (1123:1123:1123) (1141:1141:1141)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1364:1364:1364)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1088:1088:1088) (1053:1053:1053)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) + (DELAY + (ABSOLUTE + (PORT datab (910:910:910) (917:917:917)) + (PORT datac (861:861:861) (886:886:886)) + (PORT datad (1118:1118:1118) (1135:1135:1135)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (221:221:221) (291:291:291)) + (PORT datad (522:522:522) (519:519:519)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1364:1364:1364)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1088:1088:1088) (1053:1053:1053)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (930:930:930) (957:957:957)) + (PORT ena (1425:1425:1425) (1417:1417:1417)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (930:930:930) (957:957:957)) + (PORT ena (1335:1335:1335) (1310:1310:1310)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (934:934:934)) + (PORT datab (889:889:889) (917:917:917)) + (PORT datad (196:196:196) (253:253:253)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (840:840:840) (827:827:827)) + (PORT ena (1360:1360:1360) (1335:1335:1335)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (840:840:840) (827:827:827)) + (PORT ena (1371:1371:1371) (1356:1356:1356)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (881:881:881)) + (PORT datab (876:876:876) (874:874:874)) + (PORT datad (198:198:198) (254:254:254)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1115:1115:1115) (1120:1120:1120)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1346:1346:1346) (1379:1379:1379)) + (PORT datab (600:600:600) (619:619:619)) + (PORT datad (1514:1514:1514) (1575:1575:1575)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT asdata (1108:1108:1108) (1113:1113:1113)) + (PORT ena (1076:1076:1076) (1044:1044:1044)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT asdata (1106:1106:1106) (1111:1111:1111)) + (PORT ena (1114:1114:1114) (1081:1081:1081)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (626:626:626)) + (PORT datab (221:221:221) (290:290:290)) + (PORT datad (594:594:594) (592:592:592)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (636:636:636) (646:646:646)) + (PORT ena (1094:1094:1094) (1068:1068:1068)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1356:1356:1356) (1345:1345:1345)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (850:850:850) (862:862:862)) + (PORT datab (885:885:885) (907:907:907)) + (PORT datad (197:197:197) (254:254:254)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT asdata (1120:1120:1120) (1111:1111:1111)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1123:1123:1123) (1119:1119:1119)) + (PORT ena (1096:1096:1096) (1054:1054:1054)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (399:399:399) (459:459:459)) + (PORT datab (460:460:460) (490:490:490)) + (PORT datad (589:589:589) (589:589:589)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1125:1125:1125) (1122:1122:1122)) + (PORT ena (1148:1148:1148) (1134:1134:1134)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (923:923:923)) + (PORT datab (1202:1202:1202) (1196:1196:1196)) + (PORT datad (1372:1372:1372) (1401:1401:1401)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (330:330:330)) + (PORT datab (604:604:604) (611:611:611)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (338:338:338)) + (PORT datab (571:571:571) (582:582:582)) + (PORT datac (591:591:591) (592:592:592)) + (PORT datad (574:574:574) (575:575:575)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (759:759:759) (768:768:768)) + (PORT datab (374:374:374) (393:393:393)) + (PORT datac (1262:1262:1262) (1243:1243:1243)) + (PORT datad (554:554:554) (536:536:536)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1364:1364:1364)) + (PORT asdata (827:827:827) (812:812:812)) + (PORT ena (1070:1070:1070) (1040:1040:1040)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (570:570:570)) + (PORT datab (1151:1151:1151) (1182:1182:1182)) + (PORT datad (519:519:519) (514:514:514)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (291:291:291)) + (PORT datab (544:544:544) (548:548:548)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[8\]) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (365:365:365)) + (PORT datac (813:813:813) (826:826:826)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (581:581:581) (591:591:591)) + (PORT datab (195:195:195) (233:233:233)) + (PORT datac (163:163:163) (200:200:200)) + (PORT datad (556:556:556) (545:545:545)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (261:261:261)) + (PORT datab (626:626:626) (655:655:655)) + (PORT datac (1105:1105:1105) (1104:1104:1104)) + (PORT datad (1640:1640:1640) (1626:1626:1626)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (763:763:763) (761:761:761)) + (PORT datab (1017:1017:1017) (1034:1034:1034)) + (PORT datac (929:929:929) (960:960:960)) + (PORT datad (785:785:785) (770:770:770)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (819:819:819) (850:850:850)) + (PORT datab (849:849:849) (843:843:843)) + (PORT datac (315:315:315) (320:320:320)) + (PORT datad (795:795:795) (789:789:789)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (399:399:399)) + (PORT datab (1369:1369:1369) (1378:1378:1378)) + (PORT datac (938:938:938) (970:970:970)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (335:335:335)) + (PORT datab (610:610:610) (603:603:603)) + (PORT datac (514:514:514) (501:501:501)) + (PORT datad (566:566:566) (576:576:576)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1069:1069:1069) (1097:1097:1097)) + (PORT datab (1114:1114:1114) (1133:1133:1133)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (776:776:776) (750:750:750)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1400:1400:1400) (1370:1370:1370)) + (PORT ena (1646:1646:1646) (1626:1626:1626)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1123:1123:1123) (1104:1104:1104)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (831:831:831) (811:811:811)) + (PORT ena (1307:1307:1307) (1269:1269:1269)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (832:832:832) (813:813:813)) + (PORT ena (764:764:764) (779:779:779)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (292:292:292)) + (PORT datab (1006:1006:1006) (987:987:987)) + (PORT datad (197:197:197) (254:254:254)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (1125:1125:1125) (1108:1108:1108)) + (PORT ena (901:901:901) (894:894:894)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (1127:1127:1127) (1106:1106:1106)) + (PORT ena (843:843:843) (827:827:827)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (419:419:419)) + (PORT datab (416:416:416) (432:432:432)) + (PORT datad (197:197:197) (254:254:254)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (580:580:580) (573:573:573)) + (PORT datac (1216:1216:1216) (1187:1187:1187)) + (PORT datad (1046:1046:1046) (1035:1035:1035)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (527:527:527) (531:531:531)) + (PORT datab (1047:1047:1047) (1047:1047:1047)) + (PORT datac (994:994:994) (975:975:975)) + (PORT datad (764:764:764) (757:757:757)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (773:773:773) (744:744:744)) + (PORT datab (364:364:364) (367:367:367)) + (PORT datac (995:995:995) (970:970:970)) + (PORT datad (1003:1003:1003) (985:985:985)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (611:611:611)) + (PORT datab (1241:1241:1241) (1210:1210:1210)) + (PORT datac (603:603:603) (633:633:633)) + (PORT datad (1053:1053:1053) (1039:1039:1039)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (834:834:834)) + (PORT datab (812:812:812) (813:813:813)) + (PORT datac (1005:1005:1005) (1022:1022:1022)) + (PORT datad (770:770:770) (758:758:758)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (807:807:807) (813:813:813)) + (PORT datab (555:555:555) (550:550:550)) + (PORT datac (736:736:736) (725:725:725)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (835:835:835)) + (PORT datab (838:838:838) (823:823:823)) + (PORT datac (740:740:740) (731:731:731)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (850:850:850) (845:845:845)) + (PORT datab (824:824:824) (803:803:803)) + (PORT datac (801:801:801) (836:836:836)) + (PORT datad (991:991:991) (983:983:983)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT asdata (1569:1569:1569) (1544:1544:1544)) + (PORT ena (879:879:879) (881:881:881)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (930:930:930) (945:945:945)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (764:764:764) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (620:620:620)) + (PORT datab (217:217:217) (261:261:261)) + (PORT datad (515:515:515) (529:529:529)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1564:1564:1564) (1524:1524:1524)) + (PORT ena (1081:1081:1081) (1050:1050:1050)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT asdata (1568:1568:1568) (1544:1544:1544)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1561:1561:1561) (1521:1521:1521)) + (PORT ena (1142:1142:1142) (1145:1145:1145)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (685:685:685)) + (PORT datab (625:625:625) (650:650:650)) + (PORT datad (587:587:587) (602:602:602)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (405:405:405)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT asdata (1334:1334:1334) (1295:1295:1295)) + (PORT ena (1053:1053:1053) (1033:1033:1033)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT asdata (1335:1335:1335) (1297:1297:1297)) + (PORT ena (1141:1141:1141) (1140:1140:1140)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (598:598:598)) + (PORT datab (865:865:865) (879:879:879)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (541:541:541)) + (PORT datab (753:753:753) (728:728:728)) + (PORT datac (596:596:596) (608:608:608)) + (PORT datad (768:768:768) (766:766:766)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (639:639:639)) + (PORT datab (181:181:181) (212:212:212)) + (PORT datad (576:576:576) (592:592:592)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (811:811:811) (789:789:789)) + (PORT datab (331:331:331) (348:348:348)) + (PORT datac (1058:1058:1058) (1052:1052:1052)) + (PORT datad (617:617:617) (641:641:641)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (616:616:616) (622:622:622)) + (PORT ena (1129:1129:1129) (1100:1100:1100)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1359:1359:1359) (1353:1353:1353)) + (PORT datab (769:769:769) (738:738:738)) + (PORT datad (606:606:606) (602:602:602)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (295:295:295)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datad (564:564:564) (562:562:562)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) + (DELAY + (ABSOLUTE + (PORT datab (649:649:649) (694:694:694)) + (PORT datad (741:741:741) (714:714:714)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (1104:1104:1104) (1124:1124:1124)) + (PORT datad (196:196:196) (228:228:228)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (1012:1012:1012) (1020:1020:1020)) + (PORT datad (580:580:580) (582:582:582)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1375:1375:1375)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1413:1413:1413) (1379:1379:1379)) + (PORT ena (1868:1868:1868) (1840:1840:1840)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1154:1154:1154) (1119:1119:1119)) + (PORT datab (834:834:834) (845:845:845)) + (PORT datac (351:351:351) (397:397:397)) + (PORT datad (844:844:844) (876:876:876)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) + (DELAY + (ABSOLUTE + (PORT datac (363:363:363) (414:414:414)) + (PORT datad (173:173:173) (200:200:200)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1418:1418:1418) (1444:1444:1444)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (387:387:387) (430:430:430)) + (PORT datad (299:299:299) (301:301:301)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[9\]) + (DELAY + (ABSOLUTE + (PORT datac (810:810:810) (826:826:826)) + (PORT datad (292:292:292) (301:301:301)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1400:1400:1400) (1370:1370:1370)) + (PORT ena (1646:1646:1646) (1626:1626:1626)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT asdata (828:828:828) (817:817:817)) + (PORT ena (1110:1110:1110) (1083:1083:1083)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1267:1267:1267) (1244:1244:1244)) + (PORT ena (1148:1148:1148) (1134:1134:1134)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (923:923:923)) + (PORT datab (1199:1199:1199) (1193:1193:1193)) + (PORT datad (765:765:765) (810:810:810)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1356:1356:1356) (1345:1345:1345)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (1103:1103:1103) (1080:1080:1080)) + (PORT ena (1094:1094:1094) (1068:1068:1068)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (294:294:294)) + (PORT datab (885:885:885) (912:912:912)) + (PORT datad (806:806:806) (822:822:822)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT asdata (1136:1136:1136) (1124:1124:1124)) + (PORT ena (1076:1076:1076) (1044:1044:1044)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT asdata (1136:1136:1136) (1124:1124:1124)) + (PORT ena (1114:1114:1114) (1081:1081:1081)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (620:620:620)) + (PORT datab (219:219:219) (287:287:287)) + (PORT datad (592:592:592) (587:587:587)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT asdata (1109:1109:1109) (1106:1106:1106)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1267:1267:1267) (1242:1242:1242)) + (PORT ena (1096:1096:1096) (1054:1054:1054)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (453:453:453)) + (PORT datab (459:459:459) (493:493:493)) + (PORT datad (587:587:587) (589:589:589)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (606:606:606)) + (PORT datab (790:790:790) (780:780:780)) + (PORT datac (538:538:538) (529:529:529)) + (PORT datad (534:534:534) (513:513:513)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1307:1307:1307) (1277:1277:1277)) + (PORT ena (1425:1425:1425) (1417:1417:1417)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (989:989:989) (965:965:965)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1335:1335:1335) (1310:1310:1310)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (939:939:939)) + (PORT datab (888:888:888) (922:922:922)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1104:1104:1104) (1102:1102:1102)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1345:1345:1345) (1374:1374:1374)) + (PORT datab (600:600:600) (623:623:623)) + (PORT datad (1513:1513:1513) (1577:1577:1577)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (651:651:651) (655:655:655)) + (PORT ena (1371:1371:1371) (1356:1356:1356)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (651:651:651) (655:655:655)) + (PORT ena (1360:1360:1360) (1335:1335:1335)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (880:880:880)) + (PORT datab (220:220:220) (288:288:288)) + (PORT datad (843:843:843) (840:840:840)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (611:611:611)) + (PORT datab (621:621:621) (632:632:632)) + (PORT datac (801:801:801) (815:815:815)) + (PORT datad (300:300:300) (300:300:300)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (523:523:523) (514:514:514)) + (PORT datab (369:369:369) (387:387:387)) + (PORT datac (1261:1261:1261) (1240:1240:1240)) + (PORT datad (532:532:532) (517:517:517)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (625:625:625)) + (PORT datab (574:574:574) (594:594:594)) + (PORT datad (532:532:532) (524:524:524)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1364:1364:1364)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1088:1088:1088) (1053:1053:1053)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (372:372:372) (427:427:427)) + (PORT datad (541:541:541) (544:544:544)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (448:448:448)) + (PORT datab (835:835:835) (842:842:842)) + (PORT datac (375:375:375) (430:430:430)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1415:1415:1415) (1442:1442:1442)) + (PORT datab (356:356:356) (373:373:373)) + (PORT datac (386:386:386) (436:436:436)) + (PORT datad (335:335:335) (334:334:334)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[10\]) + (DELAY + (ABSOLUTE + (PORT datac (813:813:813) (831:831:831)) + (PORT datad (309:309:309) (315:315:315)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1400:1400:1400) (1370:1370:1370)) + (PORT ena (1646:1646:1646) (1626:1626:1626)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (444:444:444)) + (PORT datab (835:835:835) (840:840:840)) + (PORT datac (373:373:373) (427:427:427)) + (PORT datad (173:173:173) (200:200:200)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (1986:1986:1986) (1972:1972:1972)) + (PORT ena (1360:1360:1360) (1335:1335:1335)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (1988:1988:1988) (1974:1974:1974)) + (PORT ena (1371:1371:1371) (1356:1356:1356)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (886:886:886)) + (PORT datab (876:876:876) (880:880:880)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1804:1804:1804) (1785:1785:1785)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1348:1348:1348) (1384:1384:1384)) + (PORT datab (605:605:605) (628:628:628)) + (PORT datad (1521:1521:1521) (1585:1585:1585)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (881:881:881) (886:886:886)) + (PORT ena (1425:1425:1425) (1417:1417:1417)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (883:883:883) (885:885:885)) + (PORT ena (1335:1335:1335) (1310:1310:1310)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (941:941:941)) + (PORT datab (888:888:888) (922:922:922)) + (PORT datad (334:334:334) (367:367:367)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT asdata (1620:1620:1620) (1626:1626:1626)) + (PORT ena (1076:1076:1076) (1044:1044:1044)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT asdata (1621:1621:1621) (1627:1627:1627)) + (PORT ena (1114:1114:1114) (1081:1081:1081)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (626:626:626)) + (PORT datab (220:220:220) (289:289:289)) + (PORT datad (593:593:593) (591:591:591)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT asdata (1747:1747:1747) (1736:1736:1736)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1826:1826:1826) (1808:1808:1808)) + (PORT ena (1096:1096:1096) (1054:1054:1054)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (396:396:396) (454:454:454)) + (PORT datab (458:458:458) (494:494:494)) + (PORT datad (582:582:582) (581:581:581)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1826:1826:1826) (1810:1810:1810)) + (PORT ena (1148:1148:1148) (1134:1134:1134)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1024:1024:1024) (1005:1005:1005)) + (PORT datab (823:823:823) (810:810:810)) + (PORT datac (766:766:766) (742:742:742)) + (PORT datad (1043:1043:1043) (1027:1027:1027)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (656:656:656)) + (PORT datab (1012:1012:1012) (982:982:982)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (884:884:884) (881:881:881)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (916:916:916)) + (PORT datab (1199:1199:1199) (1194:1194:1194)) + (PORT datad (775:775:775) (820:820:820)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1356:1356:1356) (1345:1345:1345)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (1967:1967:1967) (1956:1956:1956)) + (PORT ena (1094:1094:1094) (1068:1068:1068)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (291:291:291)) + (PORT datab (884:884:884) (907:907:907)) + (PORT datad (806:806:806) (819:819:819)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (627:627:627)) + (PORT datab (598:598:598) (627:627:627)) + (PORT datac (571:571:571) (584:584:584)) + (PORT datad (583:583:583) (589:589:589)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (571:571:571)) + (PORT datab (609:609:609) (625:625:625)) + (PORT datac (777:777:777) (793:793:793)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1288:1288:1288) (1271:1271:1271)) + (PORT datab (595:595:595) (625:625:625)) + (PORT datac (511:511:511) (498:498:498)) + (PORT datad (344:344:344) (353:353:353)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1364:1364:1364)) + (PORT asdata (1050:1050:1050) (1034:1034:1034)) + (PORT ena (1070:1070:1070) (1040:1040:1040)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1498:1498:1498) (1500:1500:1500)) + (PORT datab (542:542:542) (547:547:547)) + (PORT datad (531:531:531) (529:529:529)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1364:1364:1364)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1088:1088:1088) (1053:1053:1053)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (195:195:195) (261:261:261)) + (PORT datad (521:521:521) (519:519:519)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (528:528:528) (525:525:525)) + (PORT datab (659:659:659) (681:681:681)) + (PORT datac (353:353:353) (407:407:407)) + (PORT datad (581:581:581) (603:603:603)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (427:427:427) (467:467:467)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (490:490:490) (486:486:486)) + (PORT datad (1373:1373:1373) (1406:1406:1406)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[12\]) + (DELAY + (ABSOLUTE + (PORT datab (837:837:837) (843:843:843)) + (PORT datac (743:743:743) (739:739:739)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1399:1399:1399) (1369:1369:1369)) + (PORT ena (1625:1625:1625) (1596:1596:1596)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (529:529:529) (528:528:528)) + (PORT datab (660:660:660) (682:682:682)) + (PORT datac (352:352:352) (402:402:402)) + (PORT datad (582:582:582) (602:602:602)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (394:394:394) (448:448:448)) + (PORT datad (168:168:168) (198:198:198)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1364:1364:1364)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1088:1088:1088) (1053:1053:1053)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (884:884:884) (911:911:911)) + (PORT ena (1425:1425:1425) (1417:1417:1417)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (884:884:884) (910:910:910)) + (PORT ena (1335:1335:1335) (1310:1310:1310)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (940:940:940)) + (PORT datab (894:894:894) (918:918:918)) + (PORT datad (196:196:196) (252:252:252)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (621:621:621) (638:638:638)) + (PORT ena (1360:1360:1360) (1335:1335:1335)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (621:621:621) (637:637:637)) + (PORT ena (1371:1371:1371) (1356:1356:1356)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (886:886:886)) + (PORT datab (881:881:881) (879:879:879)) + (PORT datad (197:197:197) (254:254:254)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (826:826:826) (824:824:824)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1579:1579:1579) (1571:1571:1571)) + (PORT ena (1096:1096:1096) (1054:1054:1054)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (627:627:627)) + (PORT datab (462:462:462) (494:494:494)) + (PORT datad (581:581:581) (580:580:580)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1579:1579:1579) (1569:1569:1569)) + (PORT ena (1148:1148:1148) (1134:1134:1134)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1056:1056:1056) (1034:1034:1034)) + (PORT datab (657:657:657) (680:680:680)) + (PORT datac (1001:1001:1001) (992:992:992)) + (PORT datad (173:173:173) (203:203:203)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1121:1121:1121) (1150:1150:1150)) + (PORT datab (753:753:753) (754:754:754)) + (PORT datac (768:768:768) (764:764:764)) + (PORT datad (749:749:749) (718:718:718)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1139:1139:1139) (1178:1178:1178)) + (PORT datab (894:894:894) (948:948:948)) + (PORT datac (596:596:596) (619:619:619)) + (PORT datad (1252:1252:1252) (1323:1323:1323)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (343:343:343)) + (PORT datab (834:834:834) (846:846:846)) + (PORT datac (573:573:573) (592:592:592)) + (PORT datad (863:863:863) (894:894:894)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (878:878:878)) + (PORT datab (250:250:250) (308:308:308)) + (PORT datad (790:790:790) (763:763:763)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (311:311:311)) + (PORT datad (791:791:791) (763:763:763)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) + (DELAY + (ABSOLUTE + (PORT dataa (1858:1858:1858) (1922:1922:1922)) + (PORT datac (1011:1011:1011) (988:988:988)) + (PORT datad (1230:1230:1230) (1341:1341:1341)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (854:854:854)) + (PORT datab (188:188:188) (226:226:226)) + (PORT datac (816:816:816) (834:834:834)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (240:240:240)) + (PORT datac (641:641:641) (687:687:687)) + (PORT datad (784:784:784) (817:817:817)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (204:204:204) (239:239:239)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (1240:1240:1240) (1231:1231:1231)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1436:1436:1436) (1474:1474:1474)) + (PORT datab (1474:1474:1474) (1502:1502:1502)) + (PORT datac (794:794:794) (811:811:811)) + (PORT datad (369:369:369) (420:420:420)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (412:412:412) (457:457:457)) + (PORT datab (547:547:547) (541:541:541)) + (PORT datac (785:785:785) (803:803:803)) + (PORT datad (214:214:214) (255:255:255)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (608:608:608) (607:607:607)) + (PORT ena (1353:1353:1353) (1321:1321:1321)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (579:579:579)) + (PORT datab (1040:1040:1040) (1042:1042:1042)) + (PORT datad (785:785:785) (768:768:768)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (585:585:585)) + (PORT datab (1221:1221:1221) (1198:1198:1198)) + (PORT datac (187:187:187) (223:223:223)) + (PORT datad (777:777:777) (764:764:764)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datac (222:222:222) (282:282:282)) + (PORT datad (322:322:322) (334:334:334)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (372:372:372)) + (PORT datab (940:940:940) (946:946:946)) + (PORT datac (1556:1556:1556) (1555:1555:1555)) + (PORT datad (1101:1101:1101) (1102:1102:1102)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (551:551:551) (543:543:543)) + (PORT datac (838:838:838) (846:846:846)) + (PORT datad (789:789:789) (767:767:767)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) + (DELAY + (ABSOLUTE + (PORT datab (556:556:556) (548:548:548)) + (PORT datac (222:222:222) (276:276:276)) + (PORT datad (795:795:795) (768:768:768)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) + (DELAY + (ABSOLUTE + (PORT dataa (818:818:818) (815:815:815)) + (PORT datab (935:935:935) (938:938:938)) + (PORT datac (1560:1560:1560) (1559:1559:1559)) + (PORT datad (1095:1095:1095) (1094:1094:1094)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (917:917:917)) + (PORT datab (995:995:995) (1030:1030:1030)) + (PORT datac (808:808:808) (831:831:831)) + (PORT datad (591:591:591) (601:601:601)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (654:654:654)) + (PORT datab (600:600:600) (618:618:618)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (855:855:855) (853:853:853)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (649:649:649)) + (PORT datab (606:606:606) (634:634:634)) + (PORT datac (573:573:573) (590:590:590)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1344:1344:1344)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (746:746:746) (759:759:759)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1356:1356:1356) (1415:1415:1415)) + (PORT datab (880:880:880) (872:872:872)) + (PORT datac (546:546:546) (534:534:534)) + (PORT datad (1425:1425:1425) (1498:1498:1498)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) + (DELAY + (ABSOLUTE + (PORT dataa (814:814:814) (835:835:835)) + (PORT datab (911:911:911) (930:930:930)) + (PORT datac (1315:1315:1315) (1296:1296:1296)) + (PORT datad (600:600:600) (610:610:610)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1157:1157:1157) (1193:1193:1193)) + (PORT datab (579:579:579) (582:582:582)) + (PORT datac (1353:1353:1353) (1363:1363:1363)) + (PORT datad (579:579:579) (570:570:570)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nop3pla68M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1090:1090:1090) (1139:1139:1139)) + (PORT datab (1160:1160:1160) (1170:1170:1170)) + (PORT datac (820:820:820) (830:830:830)) + (PORT datad (176:176:176) (197:197:197)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1156:1156:1156) (1193:1193:1193)) + (PORT datab (1176:1176:1176) (1216:1216:1216)) + (PORT datac (1960:1960:1960) (2010:2010:2010)) + (PORT datad (1339:1339:1339) (1343:1343:1343)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (360:360:360)) + (PORT datab (611:611:611) (596:596:596)) + (PORT datac (330:330:330) (335:335:335)) + (PORT datad (296:296:296) (297:297:297)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (232:232:232)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datac (161:161:161) (195:195:195)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (352:352:352)) + (PORT datab (309:309:309) (330:330:330)) + (PORT datac (804:804:804) (778:778:778)) + (PORT datad (559:559:559) (570:570:570)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (264:264:264)) + (PORT datab (818:818:818) (798:798:798)) + (PORT datac (330:330:330) (348:348:348)) + (PORT datad (179:179:179) (201:201:201)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (881:881:881)) + (PORT datab (199:199:199) (230:230:230)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (562:562:562) (571:571:571)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1264:1264:1264) (1219:1219:1219)) + (PORT datab (618:618:618) (637:637:637)) + (PORT datac (593:593:593) (620:620:620)) + (PORT datad (855:855:855) (853:853:853)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~7) + (DELAY + (ABSOLUTE + (PORT datac (572:572:572) (592:592:592)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1344:1344:1344)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (746:746:746) (759:759:759)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (618:618:618)) + (PORT datab (223:223:223) (260:260:260)) + (PORT datac (774:774:774) (753:753:753)) + (PORT datad (777:777:777) (764:764:764)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (455:455:455)) + (PORT datab (809:809:809) (800:800:800)) + (PORT datac (560:560:560) (580:580:580)) + (PORT datad (523:523:523) (522:522:522)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1098:1098:1098) (1120:1120:1120)) + (PORT datab (533:533:533) (524:524:524)) + (PORT datac (799:799:799) (782:782:782)) + (PORT datad (1667:1667:1667) (1701:1701:1701)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1100:1100:1100) (1123:1123:1123)) + (PORT datab (531:531:531) (525:525:525)) + (PORT datac (797:797:797) (783:783:783)) + (PORT datad (1668:1668:1668) (1704:1704:1704)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (269:269:269)) + (PORT datab (517:517:517) (508:508:508)) + (PORT datac (203:203:203) (242:242:242)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (239:239:239)) + (PORT datab (199:199:199) (232:232:232)) + (PORT datac (194:194:194) (237:237:237)) + (PORT datad (186:186:186) (214:214:214)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (247:247:247)) + (PORT datab (188:188:188) (223:223:223)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT datab (774:774:774) (742:742:742)) + (PORT datac (515:515:515) (511:511:511)) + (PORT datad (309:309:309) (313:313:313)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1353:1353:1353)) + (PORT asdata (635:635:635) (632:632:632)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (968:968:968) (967:967:967)) + (PORT datab (608:608:608) (629:629:629)) + (PORT datac (586:586:586) (612:612:612)) + (PORT datad (545:545:545) (540:540:540)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datac (572:572:572) (588:588:588)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1344:1344:1344)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (746:746:746) (759:759:759)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (966:966:966)) + (PORT datab (1469:1469:1469) (1503:1503:1503)) + (PORT datac (793:793:793) (813:813:813)) + (PORT datad (384:384:384) (439:439:439)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (200:200:200) (234:234:234)) + (PORT datac (656:656:656) (718:718:718)) + (PORT datad (777:777:777) (814:814:814)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (827:827:827)) + (PORT datab (1303:1303:1303) (1276:1276:1276)) + (PORT datac (183:183:183) (219:219:219)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (419:419:419) (464:464:464)) + (PORT datab (244:244:244) (295:295:295)) + (PORT datad (557:557:557) (566:566:566)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (793:793:793) (807:807:807)) + (PORT datab (743:743:743) (786:786:786)) + (PORT datac (568:568:568) (558:558:558)) + (PORT datad (572:572:572) (578:578:578)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (206:206:206) (244:244:244)) + (PORT datac (792:792:792) (794:794:794)) + (PORT datad (607:607:607) (602:602:602)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (1577:1577:1577) (1638:1638:1638)) + (PORT ena (1360:1360:1360) (1335:1335:1335)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (1577:1577:1577) (1638:1638:1638)) + (PORT ena (1371:1371:1371) (1356:1356:1356)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (879:879:879)) + (PORT datab (876:876:876) (872:872:872)) + (PORT datad (195:195:195) (251:251:251)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1545:1545:1545) (1584:1584:1584)) + (PORT ena (1425:1425:1425) (1417:1417:1417)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (991:991:991) (1028:1028:1028)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1335:1335:1335) (1310:1310:1310)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (935:935:935)) + (PORT datab (893:893:893) (917:917:917)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1304:1304:1304) (1350:1350:1350)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1349:1349:1349) (1382:1382:1382)) + (PORT datab (606:606:606) (628:628:628)) + (PORT datad (1522:1522:1522) (1583:1583:1583)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (883:883:883) (891:891:891)) + (PORT ena (1094:1094:1094) (1068:1068:1068)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (883:883:883) (890:890:890)) + (PORT ena (1356:1356:1356) (1345:1345:1345)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (860:860:860)) + (PORT datab (885:885:885) (914:914:914)) + (PORT datad (197:197:197) (254:254:254)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT asdata (1085:1085:1085) (1138:1138:1138)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1310:1310:1310) (1357:1357:1357)) + (PORT ena (1096:1096:1096) (1054:1054:1054)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (617:617:617)) + (PORT datab (424:424:424) (468:468:468)) + (PORT datad (590:590:590) (591:591:591)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT asdata (1311:1311:1311) (1358:1358:1358)) + (PORT ena (1076:1076:1076) (1044:1044:1044)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT asdata (1311:1311:1311) (1359:1359:1359)) + (PORT ena (1114:1114:1114) (1081:1081:1081)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (619:619:619)) + (PORT datab (218:218:218) (286:286:286)) + (PORT datad (598:598:598) (595:595:595)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT asdata (1308:1308:1308) (1355:1355:1355)) + (PORT ena (1148:1148:1148) (1134:1134:1134)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (921:921:921)) + (PORT datab (1201:1201:1201) (1195:1195:1195)) + (PORT datad (746:746:746) (790:790:790)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (362:362:362)) + (PORT datab (797:797:797) (829:829:829)) + (PORT datac (534:534:534) (558:558:558)) + (PORT datad (747:747:747) (746:746:746)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (562:562:562) (546:546:546)) + (PORT datab (778:778:778) (773:773:773)) + (PORT datac (570:570:570) (589:589:589)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[14\]) + (DELAY + (ABSOLUTE + (PORT datab (836:836:836) (837:837:837)) + (PORT datad (809:809:809) (778:778:778)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1399:1399:1399) (1369:1369:1369)) + (PORT ena (1625:1625:1625) (1596:1596:1596)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (450:450:450)) + (PORT datab (194:194:194) (233:233:233)) + (PORT datac (542:542:542) (564:564:564)) + (PORT datad (620:620:620) (647:647:647)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT asdata (698:698:698) (715:715:715)) + (PORT ena (1110:1110:1110) (1083:1083:1083)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (238:238:238)) + (PORT datab (572:572:572) (590:590:590)) + (PORT datad (521:521:521) (524:524:524)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1364:1364:1364)) + (PORT asdata (486:486:486) (513:513:513)) + (PORT ena (1088:1088:1088) (1053:1053:1053)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (561:561:561) (577:577:577)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (366:366:366) (412:412:412)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1414:1414:1414) (1441:1441:1441)) + (PORT datab (503:503:503) (498:498:498)) + (PORT datac (386:386:386) (430:430:430)) + (PORT datad (321:321:321) (335:335:335)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (218:218:218)) + (PORT datab (1278:1278:1278) (1262:1262:1262)) + (PORT datac (390:390:390) (409:409:409)) + (PORT datad (188:188:188) (217:217:217)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (952:952:952) (961:961:961)) + (PORT datab (820:820:820) (812:812:812)) + (PORT datac (1172:1172:1172) (1225:1225:1225)) + (PORT datad (978:978:978) (966:966:966)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (663:663:663)) + (PORT datab (1010:1010:1010) (977:977:977)) + (PORT datac (923:923:923) (929:929:929)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (686:686:686) (745:745:745)) + (PORT datac (179:179:179) (212:212:212)) + (PORT datad (207:207:207) (232:232:232)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (814:814:814) (847:847:847)) + (PORT datac (1276:1276:1276) (1252:1252:1252)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (608:608:608)) + (PORT datab (378:378:378) (415:415:415)) + (PORT datac (790:790:790) (805:805:805)) + (PORT datad (216:216:216) (256:256:256)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (639:639:639)) + (PORT datab (799:799:799) (794:794:794)) + (PORT datac (1883:1883:1883) (1857:1857:1857)) + (PORT datad (770:770:770) (835:835:835)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (396:396:396)) + (PORT datab (1221:1221:1221) (1198:1198:1198)) + (PORT datac (571:571:571) (572:572:572)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (821:821:821)) + (PORT datab (329:329:329) (344:344:344)) + (PORT datac (563:563:563) (557:557:557)) + (PORT datad (587:587:587) (585:585:585)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (845:845:845)) + (PORT datab (554:554:554) (552:552:552)) + (PORT datac (177:177:177) (210:210:210)) + (PORT datad (756:756:756) (736:736:736)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (664:664:664)) + (PORT datab (815:815:815) (827:827:827)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (198:198:198) (232:232:232)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (924:924:924)) + (PORT datab (1197:1197:1197) (1189:1189:1189)) + (PORT datad (1253:1253:1253) (1295:1295:1295)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1356:1356:1356) (1345:1345:1345)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT asdata (834:834:834) (832:832:832)) + (PORT ena (1094:1094:1094) (1068:1068:1068)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (290:290:290)) + (PORT datab (886:886:886) (907:907:907)) + (PORT datad (805:805:805) (818:818:818)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT asdata (886:886:886) (906:906:906)) + (PORT ena (1076:1076:1076) (1044:1044:1044)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT asdata (889:889:889) (908:908:908)) + (PORT ena (1114:1114:1114) (1081:1081:1081)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (625:625:625)) + (PORT datab (356:356:356) (400:400:400)) + (PORT datad (591:591:591) (585:585:585)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (217:217:217)) + (PORT datab (183:183:183) (217:217:217)) + (PORT datac (977:977:977) (982:982:982)) + (PORT datad (305:305:305) (310:310:310)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (1117:1117:1117) (1124:1124:1124)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1350:1350:1350) (1383:1383:1383)) + (PORT datab (605:605:605) (629:629:629)) + (PORT datad (1520:1520:1520) (1585:1585:1585)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (772:772:772) (752:752:752)) + (PORT datab (847:847:847) (839:839:839)) + (PORT datac (312:312:312) (319:319:319)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (561:561:561)) + (PORT datab (593:593:593) (622:622:622)) + (PORT datac (1258:1258:1258) (1243:1243:1243)) + (PORT datad (346:346:346) (358:358:358)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1364:1364:1364)) + (PORT asdata (800:800:800) (787:787:787)) + (PORT ena (1070:1070:1070) (1040:1040:1040)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (539:539:539)) + (PORT datab (573:573:573) (590:590:590)) + (PORT datac (396:396:396) (439:439:439)) + (PORT datad (524:524:524) (527:527:527)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (400:400:400) (459:459:459)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datad (541:541:541) (542:542:542)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1416:1416:1416) (1438:1438:1438)) + (PORT datab (554:554:554) (533:533:533)) + (PORT datac (391:391:391) (437:437:437)) + (PORT datad (323:323:323) (337:337:337)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[13\]) + (DELAY + (ABSOLUTE + (PORT datab (837:837:837) (841:841:841)) + (PORT datac (723:723:723) (696:696:696)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1399:1399:1399) (1369:1369:1369)) + (PORT ena (1625:1625:1625) (1596:1596:1596)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) + (DELAY + (ABSOLUTE + (PORT datab (658:658:658) (677:677:677)) + (PORT datac (364:364:364) (414:414:414)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[15\]) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (790:790:790)) + (PORT datad (801:801:801) (805:805:805)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1399:1399:1399) (1369:1369:1369)) + (PORT ena (1625:1625:1625) (1596:1596:1596)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_16) + (DELAY + (ABSOLUTE + (PORT dataa (1074:1074:1074) (1073:1073:1073)) + (PORT datab (374:374:374) (420:420:420)) + (PORT datac (616:616:616) (631:631:631)) + (PORT datad (1064:1064:1064) (1060:1060:1060)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (193:193:193) (232:232:232)) + (PORT datac (514:514:514) (536:536:536)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1416:1416:1416) (1443:1443:1443)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (387:387:387) (433:433:433)) + (PORT datad (499:499:499) (478:478:478)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (561:561:561) (565:565:565)) + (PORT datab (370:370:370) (392:392:392)) + (PORT datac (1258:1258:1258) (1242:1242:1242)) + (PORT datad (519:519:519) (498:498:498)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1111:1111:1111) (1110:1110:1110)) + (PORT datab (823:823:823) (810:810:810)) + (PORT datac (524:524:524) (520:520:520)) + (PORT datad (979:979:979) (962:962:962)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (662:662:662)) + (PORT datab (1010:1010:1010) (981:981:981)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (745:745:745) (785:785:785)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (437:437:437)) + (PORT datab (1716:1716:1716) (1738:1738:1738)) + (PORT datac (965:965:965) (989:989:989)) + (PORT datad (223:223:223) (282:282:282)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (752:752:752) (754:754:754)) + (PORT datab (359:359:359) (365:365:365)) + (PORT datac (222:222:222) (280:280:280)) + (PORT datad (326:326:326) (320:320:320)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (387:387:387)) + (PORT datab (555:555:555) (547:547:547)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (794:794:794) (766:766:766)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (387:387:387)) + (PORT datab (252:252:252) (313:313:313)) + (PORT datad (792:792:792) (765:765:765)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (810:810:810) (820:820:820)) + (PORT datab (660:660:660) (694:694:694)) + (PORT datad (823:823:823) (807:807:807)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (626:626:626)) + (PORT datab (564:564:564) (558:558:558)) + (PORT datac (221:221:221) (276:276:276)) + (PORT datad (518:518:518) (512:512:512)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (820:820:820) (801:801:801)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (542:542:542) (535:535:535)) + (PORT datab (658:658:658) (700:700:700)) + (PORT datac (885:885:885) (940:940:940)) + (PORT datad (921:921:921) (950:950:950)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (647:647:647)) + (PORT datab (581:581:581) (574:574:574)) + (PORT datac (574:574:574) (593:593:593)) + (PORT datad (334:334:334) (345:345:345)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1344:1344:1344)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (746:746:746) (759:759:759)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (425:425:425) (476:476:476)) + (PORT datab (813:813:813) (805:805:805)) + (PORT datac (490:490:490) (477:477:477)) + (PORT datad (369:369:369) (417:417:417)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (437:437:437)) + (PORT datab (950:950:950) (972:972:972)) + (PORT datac (756:756:756) (767:767:767)) + (PORT datad (577:577:577) (571:571:571)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (359:359:359)) + (PORT datab (1132:1132:1132) (1157:1157:1157)) + (PORT datac (638:638:638) (670:670:670)) + (PORT datad (823:823:823) (809:809:809)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT datac (353:353:353) (364:364:364)) + (PORT datad (165:165:165) (188:188:188)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (587:587:587)) + (PORT datab (193:193:193) (233:233:233)) + (PORT datac (541:541:541) (538:538:538)) + (PORT datad (165:165:165) (189:189:189)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (394:394:394) (401:401:401)) + (PORT datab (188:188:188) (223:223:223)) + (PORT datac (180:180:180) (215:215:215)) + (PORT datad (312:312:312) (315:315:315)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) + (DELAY + (ABSOLUTE + (PORT datab (601:601:601) (618:618:618)) + (PORT datac (753:753:753) (743:743:743)) + (PORT datad (606:606:606) (613:613:613)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (777:777:777) (759:759:759)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datad (324:324:324) (332:332:332)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (246:246:246)) + (PORT datab (625:625:625) (622:622:622)) + (PORT datac (777:777:777) (784:784:784)) + (PORT datad (863:863:863) (853:853:853)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (904:904:904)) + (PORT datab (195:195:195) (235:235:235)) + (PORT datac (508:508:508) (499:499:499)) + (PORT datad (1145:1145:1145) (1151:1151:1151)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1238:1238:1238) (1223:1223:1223)) + (PORT datab (2112:2112:2112) (2126:2126:2126)) + (PORT datac (1100:1100:1100) (1126:1126:1126)) + (PORT datad (1243:1243:1243) (1209:1209:1209)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (554:554:554)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (1156:1156:1156) (1179:1179:1179)) + (PORT datad (873:873:873) (892:892:892)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (499:499:499) (491:491:491)) + (PORT datab (794:794:794) (782:782:782)) + (PORT datac (512:512:512) (501:501:501)) + (PORT datad (565:565:565) (570:570:570)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~4) + (DELAY + (ABSOLUTE + (PORT datab (780:780:780) (769:769:769)) + (PORT datac (768:768:768) (753:753:753)) + (PORT datad (1090:1090:1090) (1112:1112:1112)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1655:1655:1655) (1695:1695:1695)) + (PORT datab (187:187:187) (223:223:223)) + (PORT datac (1695:1695:1695) (1758:1758:1758)) + (PORT datad (1473:1473:1473) (1563:1563:1563)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (1536:1536:1536) (1543:1543:1543)) + (PORT datac (1305:1305:1305) (1273:1273:1273)) + (PORT datad (2107:2107:2107) (2143:2143:2143)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datad (164:164:164) (191:191:191)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (324:324:324)) + (PORT datab (1718:1718:1718) (1741:1741:1741)) + (PORT datac (1012:1012:1012) (1011:1011:1011)) + (PORT datad (224:224:224) (284:284:284)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (321:321:321)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT datab (870:870:870) (910:910:910)) + (PORT datac (988:988:988) (999:999:999)) + (PORT datad (578:578:578) (576:576:576)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1504:1504:1504) (1460:1460:1460)) + (PORT datab (884:884:884) (896:896:896)) + (PORT datac (955:955:955) (932:932:932)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (616:616:616)) + (PORT datab (252:252:252) (311:311:311)) + (PORT datac (181:181:181) (217:217:217)) + (PORT datad (513:513:513) (507:507:507)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (819:819:819) (799:799:799)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (402:402:402) (477:477:477)) + (PORT datab (1469:1469:1469) (1504:1504:1504)) + (PORT datac (793:793:793) (815:815:815)) + (PORT datad (564:564:564) (581:581:581)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (609:609:609) (621:621:621)) + (PORT ena (1415:1415:1415) (1385:1385:1385)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (460:460:460)) + (PORT datab (545:545:545) (541:541:541)) + (PORT datac (786:786:786) (803:803:803)) + (PORT datad (215:215:215) (257:257:257)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (817:817:817)) + (PORT datab (342:342:342) (349:349:349)) + (PORT datad (553:553:553) (558:558:558)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (750:750:750) (752:752:752)) + (PORT datab (616:616:616) (611:611:611)) + (PORT datac (530:530:530) (519:519:519)) + (PORT datad (324:324:324) (318:318:318)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (889:889:889)) + (PORT datab (992:992:992) (1029:1029:1029)) + (PORT datac (543:543:543) (573:573:573)) + (PORT datad (587:587:587) (599:599:599)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (653:653:653)) + (PORT datab (930:930:930) (943:943:943)) + (PORT datac (574:574:574) (594:594:594)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1344:1344:1344)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (746:746:746) (759:759:759)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (646:646:646)) + (PORT datab (609:609:609) (630:630:630)) + (PORT datac (538:538:538) (533:533:533)) + (PORT datad (904:904:904) (907:907:907)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT datac (574:574:574) (592:592:592)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1344:1344:1344)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (746:746:746) (759:759:759)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (400:400:400) (471:471:471)) + (PORT datab (547:547:547) (556:556:556)) + (PORT datac (397:397:397) (457:457:457)) + (PORT datad (771:771:771) (770:770:770)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (275:275:275)) + (PORT datab (515:515:515) (508:508:508)) + (PORT datac (522:522:522) (517:517:517)) + (PORT datad (1009:1009:1009) (986:986:986)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) + (DELAY + (ABSOLUTE + (PORT dataa (802:802:802) (802:802:802)) + (PORT datab (1008:1008:1008) (967:967:967)) + (PORT datac (745:745:745) (731:731:731)) + (PORT datad (735:735:735) (712:712:712)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~36) + (DELAY + (ABSOLUTE + (PORT datab (201:201:201) (245:245:245)) + (PORT datac (193:193:193) (234:234:234)) + (PORT datad (780:780:780) (771:771:771)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~35) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (231:231:231)) + (PORT datab (202:202:202) (246:246:246)) + (PORT datac (193:193:193) (231:231:231)) + (PORT datad (781:781:781) (771:771:771)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1399:1399:1399) (1416:1416:1416)) + (PORT datab (1354:1354:1354) (1338:1338:1338)) + (PORT datac (1714:1714:1714) (1656:1656:1656)) + (PORT datad (1239:1239:1239) (1207:1207:1207)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1027:1027:1027) (1009:1009:1009)) + (PORT datab (1279:1279:1279) (1304:1304:1304)) + (PORT datac (750:750:750) (729:729:729)) + (PORT datad (1220:1220:1220) (1202:1202:1202)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1800:1800:1800) (1837:1837:1837)) + (PORT datab (192:192:192) (231:231:231)) + (PORT datac (1807:1807:1807) (1845:1845:1845)) + (PORT datad (1499:1499:1499) (1475:1475:1475)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1048:1048:1048) (1024:1024:1024)) + (PORT datab (344:344:344) (356:356:356)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (769:769:769) (762:762:762)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~17) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (494:494:494) (478:478:478)) + (PORT datad (539:539:539) (526:526:526)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) + (DELAY + (ABSOLUTE + (PORT datab (1629:1629:1629) (1629:1629:1629)) + (PORT datac (1086:1086:1086) (1089:1089:1089)) + (PORT datad (1335:1335:1335) (1317:1317:1317)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) + (DELAY + (ABSOLUTE + (PORT dataa (248:248:248) (309:309:309)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (225:225:225) (280:280:280)) + (PORT datad (1118:1118:1118) (1123:1123:1123)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) + (DELAY + (ABSOLUTE + (PORT dataa (2040:2040:2040) (2130:2130:2130)) + (PORT datab (1459:1459:1459) (1528:1528:1528)) + (PORT datac (1628:1628:1628) (1684:1684:1684)) + (PORT datad (800:800:800) (799:799:799)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (216:216:216)) + (PORT datab (1718:1718:1718) (1764:1764:1764)) + (PORT datac (562:562:562) (570:570:570)) + (PORT datad (871:871:871) (875:875:875)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1673:1673:1673) (1700:1700:1700)) + (PORT datab (1321:1321:1321) (1291:1291:1291)) + (PORT datac (1307:1307:1307) (1298:1298:1298)) + (PORT datad (2153:2153:2153) (2218:2218:2218)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1426:1426:1426) (1451:1451:1451)) + (PORT datab (1131:1131:1131) (1128:1128:1128)) + (PORT datac (1306:1306:1306) (1296:1296:1296)) + (PORT datad (1510:1510:1510) (1535:1535:1535)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1342:1342:1342) (1328:1328:1328)) + (PORT datab (627:627:627) (661:661:661)) + (PORT datac (1101:1101:1101) (1098:1098:1098)) + (PORT datad (1545:1545:1545) (1549:1549:1549)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (587:587:587)) + (PORT datab (1859:1859:1859) (1914:1914:1914)) + (PORT datac (1427:1427:1427) (1486:1486:1486)) + (PORT datad (2153:2153:2153) (2218:2218:2218)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1427:1427:1427) (1452:1452:1452)) + (PORT datab (623:623:623) (657:657:657)) + (PORT datac (1412:1412:1412) (1466:1466:1466)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (294:294:294)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (624:624:624) (664:664:664)) + (PORT datac (1852:1852:1852) (1859:1859:1859)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) + (DELAY + (ABSOLUTE + (PORT dataa (317:317:317) (333:333:333)) + (PORT datab (351:351:351) (354:354:354)) + (PORT datac (297:297:297) (309:309:309)) + (PORT datad (814:814:814) (820:820:820)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~37) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (620:620:620)) + (PORT datab (592:592:592) (602:602:602)) + (PORT datac (1096:1096:1096) (1096:1096:1096)) + (PORT datad (342:342:342) (343:343:343)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (877:877:877)) + (PORT datab (200:200:200) (232:232:232)) + (PORT datac (1289:1289:1289) (1272:1272:1272)) + (PORT datad (582:582:582) (573:573:573)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (621:621:621)) + (PORT datab (194:194:194) (234:234:234)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (1092:1092:1092) (1094:1094:1094)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (598:598:598)) + (PORT datab (181:181:181) (212:212:212)) + (PORT datac (541:541:541) (532:532:532)) + (PORT datad (160:160:160) (180:180:180)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1399:1399:1399) (1416:1416:1416)) + (PORT datab (1354:1354:1354) (1338:1338:1338)) + (PORT datac (984:984:984) (963:963:963)) + (PORT datad (1238:1238:1238) (1207:1207:1207)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (873:873:873) (864:864:864)) + (PORT datac (837:837:837) (872:872:872)) + (PORT datad (2087:2087:2087) (2094:2094:2094)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1204:1204:1204) (1262:1262:1262)) + (PORT datab (1182:1182:1182) (1204:1204:1204)) + (PORT datac (839:839:839) (873:873:873)) + (PORT datad (1075:1075:1075) (1079:1079:1079)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1355:1355:1355) (1332:1332:1332)) + (PORT datab (913:913:913) (931:931:931)) + (PORT datac (358:358:358) (360:360:360)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (359:359:359)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (493:493:493) (473:473:473)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) + (DELAY + (ABSOLUTE + (PORT dataa (812:812:812) (808:808:808)) + (PORT datab (611:611:611) (601:601:601)) + (PORT datac (321:321:321) (323:323:323)) + (PORT datad (165:165:165) (190:190:190)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) + (DELAY + (ABSOLUTE + (PORT dataa (793:793:793) (777:777:777)) + (PORT datab (595:595:595) (598:598:598)) + (PORT datac (755:755:755) (731:731:731)) + (PORT datad (1146:1146:1146) (1162:1162:1162)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (619:619:619)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (166:166:166) (192:192:192)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (216:216:216)) + (PORT datab (519:519:519) (507:507:507)) + (PORT datac (162:162:162) (198:198:198)) + (PORT datad (543:543:543) (542:542:542)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (435:435:435) (489:489:489)) + (PORT datab (1469:1469:1469) (1503:1503:1503)) + (PORT datac (925:925:925) (967:967:967)) + (PORT datad (785:785:785) (793:793:793)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (717:717:717)) + (PORT datac (184:184:184) (221:221:221)) + (PORT datad (184:184:184) (208:208:208)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (653:653:653)) + (PORT datab (1266:1266:1266) (1266:1266:1266)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (608:608:608)) + (PORT datab (378:378:378) (415:415:415)) + (PORT datac (790:790:790) (805:805:805)) + (PORT datad (217:217:217) (255:255:255)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (754:754:754) (790:790:790)) + (PORT datab (1218:1218:1218) (1197:1197:1197)) + (PORT datac (706:706:706) (767:767:767)) + (PORT datad (697:697:697) (710:710:710)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (800:800:800) (820:820:820)) + (PORT datab (326:326:326) (344:344:344)) + (PORT datac (531:531:531) (520:520:520)) + (PORT datad (589:589:589) (588:588:588)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (614:614:614)) + (PORT datab (251:251:251) (308:308:308)) + (PORT datad (790:790:790) (764:764:764)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (954:954:954) (980:980:980)) + (PORT datac (925:925:925) (967:967:967)) + (PORT datad (563:563:563) (580:580:580)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (471:471:471)) + (PORT datab (549:549:549) (552:552:552)) + (PORT datac (397:397:397) (454:454:454)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (227:227:227)) + (PORT datab (809:809:809) (799:799:799)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (546:546:546) (546:546:546)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (274:274:274)) + (PORT datab (231:231:231) (272:272:272)) + (PORT datac (487:487:487) (482:482:482)) + (PORT datad (165:165:165) (191:191:191)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (401:401:401)) + (PORT datab (370:370:370) (370:370:370)) + (PORT datac (357:357:357) (358:358:358)) + (PORT datad (316:316:316) (315:315:315)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (358:358:358)) + (PORT datab (194:194:194) (234:234:234)) + (PORT datac (543:543:543) (540:540:540)) + (PORT datad (164:164:164) (186:186:186)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (566:566:566) (562:562:562)) + (PORT datac (165:165:165) (203:203:203)) + (PORT datad (163:163:163) (186:186:186)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT asdata (505:505:505) (532:532:532)) + (PORT ena (1415:1415:1415) (1385:1385:1385)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (352:352:352) (401:401:401)) + (PORT datad (783:783:783) (765:765:765)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (847:847:847)) + (PORT datab (655:655:655) (699:699:699)) + (PORT datac (1440:1440:1440) (1468:1468:1468)) + (PORT datad (369:369:369) (418:418:418)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (450:450:450)) + (PORT datad (555:555:555) (565:565:565)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (755:755:755) (741:741:741)) + (PORT datab (1012:1012:1012) (1032:1032:1032)) + (PORT datac (350:350:350) (370:370:370)) + (PORT datad (829:829:829) (834:834:834)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (733:733:733) (728:728:728)) + (PORT datab (624:624:624) (619:619:619)) + (PORT datac (324:324:324) (327:327:327)) + (PORT datad (303:303:303) (311:311:311)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1032:1032:1032) (1011:1011:1011)) + (PORT datab (824:824:824) (815:815:815)) + (PORT datac (946:946:946) (983:983:983)) + (PORT datad (913:913:913) (917:917:917)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (620:620:620)) + (PORT datab (1010:1010:1010) (979:979:979)) + (PORT datac (499:499:499) (483:483:483)) + (PORT datad (609:609:609) (624:624:624)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (591:591:591)) + (PORT datab (623:623:623) (646:646:646)) + (PORT datac (1212:1212:1212) (1181:1181:1181)) + (PORT datad (1054:1054:1054) (1041:1041:1041)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (919:919:919)) + (PORT datab (1035:1035:1035) (1029:1029:1029)) + (PORT datad (997:997:997) (970:970:970)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_hf2) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1375:1375:1375)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (354:354:354) (408:408:408)) + (PORT datac (354:354:354) (393:393:393)) + (PORT datad (355:355:355) (398:398:398)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (933:933:933)) + (PORT datab (2115:2115:2115) (2149:2149:2149)) + (PORT datad (2019:2019:2019) (2122:2122:2122)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (293:293:293)) + (PORT datab (567:567:567) (579:579:579)) + (PORT datac (747:747:747) (734:734:734)) + (PORT datad (1318:1318:1318) (1297:1297:1297)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (229:229:229)) + (PORT datab (188:188:188) (223:223:223)) + (PORT datac (1306:1306:1306) (1297:1297:1297)) + (PORT datad (167:167:167) (194:194:194)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1146:1146:1146)) + (PORT datab (875:875:875) (875:875:875)) + (PORT datac (1120:1120:1120) (1121:1121:1121)) + (PORT datad (1102:1102:1102) (1091:1091:1091)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (316:316:316)) + (PORT datab (1624:1624:1624) (1625:1625:1625)) + (PORT datac (220:220:220) (271:271:271)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (595:595:595)) + (PORT datab (188:188:188) (222:222:222)) + (PORT datac (1010:1010:1010) (989:989:989)) + (PORT datad (166:166:166) (191:191:191)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (777:777:777) (785:785:785)) + (PORT datab (847:847:847) (855:855:855)) + (PORT datac (775:775:775) (775:775:775)) + (PORT datad (765:765:765) (746:746:746)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (817:817:817)) + (PORT datab (185:185:185) (219:219:219)) + (PORT datac (585:585:585) (604:604:604)) + (PORT datad (574:574:574) (571:571:571)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (788:788:788) (774:774:774)) + (PORT datab (187:187:187) (221:221:221)) + (PORT datac (811:811:811) (818:818:818)) + (PORT datad (162:162:162) (183:183:183)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (240:240:240) (301:301:301)) + (PORT datab (1049:1049:1049) (1067:1067:1067)) + (PORT datad (1139:1139:1139) (1125:1125:1125)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (493:493:493) (524:524:524)) + (PORT ena (1141:1141:1141) (1133:1133:1133)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (854:854:854) (864:864:864)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (764:764:764) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1071:1071:1071) (1128:1128:1128)) + (PORT datab (620:620:620) (664:664:664)) + (PORT datad (809:809:809) (837:837:837)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (586:586:586) (604:604:604)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (493:493:493) (524:524:524)) + (PORT ena (1173:1173:1173) (1181:1181:1181)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (695:695:695)) + (PORT datab (672:672:672) (698:698:698)) + (PORT datad (955:955:955) (935:935:935)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (610:610:610)) + (PORT datab (566:566:566) (581:581:581)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (363:363:363)) + (PORT datab (571:571:571) (585:585:585)) + (PORT datac (290:290:290) (293:293:293)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (236:236:236)) + (PORT datab (179:179:179) (211:211:211)) + (PORT datac (757:757:757) (755:755:755)) + (PORT datad (1052:1052:1052) (1029:1029:1029)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1133:1133:1133) (1116:1116:1116)) + (PORT ena (739:739:739) (742:742:742)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1019:1019:1019) (1005:1005:1005)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datad (1038:1038:1038) (1010:1010:1010)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1145:1145:1145) (1120:1120:1120)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (579:579:579) (570:570:570)) + (PORT datac (604:604:604) (619:619:619)) + (PORT datad (199:199:199) (257:257:257)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (405:405:405)) + (PORT datab (581:581:581) (583:583:583)) + (PORT datac (1094:1094:1094) (1111:1111:1111)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (1018:1018:1018) (1028:1028:1028)) + (PORT datad (813:813:813) (807:807:807)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1375:1375:1375)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1413:1413:1413) (1379:1379:1379)) + (PORT ena (1868:1868:1868) (1840:1840:1840)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (1238:1238:1238) (1229:1229:1229)) + (PORT datad (346:346:346) (350:350:350)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1375:1375:1375)) + (PORT asdata (857:857:857) (867:867:867)) + (PORT clrn (1412:1412:1412) (1378:1378:1378)) + (PORT ena (1861:1861:1861) (1840:1840:1840)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (595:595:595)) + (PORT datab (571:571:571) (566:566:566)) + (PORT datac (547:547:547) (581:581:581)) + (PORT datad (608:608:608) (646:646:646)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (394:394:394) (458:458:458)) + (PORT datab (573:573:573) (569:569:569)) + (PORT datac (560:560:560) (587:587:587)) + (PORT datad (184:184:184) (209:209:209)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1123:1123:1123) (1104:1104:1104)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (485:485:485) (513:513:513)) + (PORT ena (1129:1129:1129) (1100:1100:1100)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (873:873:873) (867:867:867)) + (PORT ena (1307:1307:1307) (1269:1269:1269)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (872:872:872) (866:866:866)) + (PORT ena (764:764:764) (779:779:779)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (290:290:290)) + (PORT datab (1005:1005:1005) (990:990:990)) + (PORT datad (326:326:326) (367:367:367)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT asdata (1634:1634:1634) (1674:1674:1674)) + (PORT ena (879:879:879) (881:881:881)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT asdata (1634:1634:1634) (1674:1674:1674)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (294:294:294)) + (PORT datab (217:217:217) (263:263:263)) + (PORT datad (193:193:193) (220:220:220)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1637:1637:1637) (1669:1669:1669)) + (PORT ena (1142:1142:1142) (1145:1145:1145)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (1106:1106:1106) (1122:1122:1122)) + (PORT datab (628:628:628) (651:651:651)) + (PORT datad (778:778:778) (768:768:768)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1638:1638:1638) (1669:1669:1669)) + (PORT ena (1081:1081:1081) (1050:1050:1050)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (403:403:403)) + (PORT datab (179:179:179) (211:211:211)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (312:312:312) (325:325:325)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1564:1564:1564) (1566:1566:1566)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1035:1035:1035) (1005:1005:1005)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (299:299:299)) + (PORT datab (221:221:221) (290:290:290)) + (PORT datad (1267:1267:1267) (1329:1329:1329)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT asdata (879:879:879) (890:890:890)) + (PORT ena (1053:1053:1053) (1033:1033:1033)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT asdata (879:879:879) (890:890:890)) + (PORT ena (1141:1141:1141) (1140:1140:1140)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (597:597:597)) + (PORT datab (865:865:865) (879:879:879)) + (PORT datad (196:196:196) (253:253:253)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (747:747:747)) + (PORT datab (594:594:594) (608:608:608)) + (PORT datac (553:553:553) (571:571:571)) + (PORT datad (573:573:573) (567:567:567)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (1123:1123:1123) (1124:1124:1124)) + (PORT ena (843:843:843) (827:827:827)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (1124:1124:1124) (1124:1124:1124)) + (PORT ena (901:901:901) (894:894:894)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (416:416:416)) + (PORT datab (219:219:219) (288:288:288)) + (PORT datad (381:381:381) (405:405:405)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (634:634:634)) + (PORT datab (804:804:804) (777:777:777)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (811:811:811) (789:789:789)) + (PORT datab (375:375:375) (381:381:381)) + (PORT datac (1059:1059:1059) (1056:1056:1056)) + (PORT datad (613:613:613) (639:639:639)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1357:1357:1357) (1354:1354:1354)) + (PORT datab (626:626:626) (631:631:631)) + (PORT datad (308:308:308) (308:308:308)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (527:527:527) (564:564:564)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datad (563:563:563) (562:562:562)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (819:819:819) (795:795:795)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1104:1104:1104) (1124:1124:1124)) + (PORT datad (197:197:197) (228:228:228)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[5\]) + (DELAY + (ABSOLUTE + (PORT dataa (1018:1018:1018) (1028:1028:1028)) + (PORT datad (575:575:575) (571:571:571)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1375:1375:1375)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1413:1413:1413) (1379:1379:1379)) + (PORT ena (1868:1868:1868) (1840:1840:1840)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1074:1074:1074) (1057:1057:1057)) + (PORT datab (1362:1362:1362) (1347:1347:1347)) + (PORT datac (1094:1094:1094) (1100:1100:1100)) + (PORT datad (184:184:184) (209:209:209)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (557:557:557)) + (PORT datab (189:189:189) (224:224:224)) + (PORT datac (577:577:577) (597:597:597)) + (PORT datad (166:166:166) (193:193:193)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1339:1339:1339) (1328:1328:1328)) + (PORT ena (1307:1307:1307) (1269:1269:1269)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1336:1336:1336) (1324:1324:1324)) + (PORT ena (764:764:764) (779:779:779)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (282:282:282)) + (PORT datab (1006:1006:1006) (994:994:994)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (1120:1120:1120) (1137:1137:1137)) + (PORT ena (901:901:901) (894:894:894)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (1119:1119:1119) (1136:1136:1136)) + (PORT ena (843:843:843) (827:827:827)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (421:421:421)) + (PORT datab (413:413:413) (428:428:428)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1097:1097:1097) (1085:1085:1085)) + (PORT ena (763:763:763) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1164:1164:1164) (1200:1200:1200)) + (PORT datab (931:931:931) (954:954:954)) + (PORT datad (836:836:836) (838:838:838)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1727:1727:1727) (1737:1737:1737)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (236:236:236) (295:295:295)) + (PORT datab (1051:1051:1051) (1069:1069:1069)) + (PORT datad (793:793:793) (778:778:778)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT asdata (896:896:896) (894:894:894)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (882:882:882) (906:906:906)) + (PORT ena (1173:1173:1173) (1181:1181:1181)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (1057:1057:1057) (1103:1103:1103)) + (PORT datab (668:668:668) (692:692:692)) + (PORT datad (955:955:955) (935:935:935)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (882:882:882) (909:909:909)) + (PORT ena (1141:1141:1141) (1133:1133:1133)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1564:1564:1564) (1566:1566:1566)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (1070:1070:1070) (1124:1124:1124)) + (PORT datab (615:615:615) (657:657:657)) + (PORT datad (602:602:602) (645:645:645)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (633:633:633)) + (PORT datab (599:599:599) (611:611:611)) + (PORT datac (529:529:529) (520:520:520)) + (PORT datad (287:287:287) (294:294:294)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT asdata (1147:1147:1147) (1159:1159:1159)) + (PORT ena (1053:1053:1053) (1033:1033:1033)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (591:591:591) (623:623:623)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1141:1141:1141) (1140:1140:1140)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (596:596:596)) + (PORT datab (865:865:865) (879:879:879)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (594:594:594)) + (PORT datab (304:304:304) (321:321:321)) + (PORT datac (315:315:315) (322:322:322)) + (PORT datad (313:313:313) (312:312:312)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (623:623:623)) + (PORT datab (649:649:649) (674:674:674)) + (PORT datac (1062:1062:1062) (1054:1054:1054)) + (PORT datad (489:489:489) (479:479:479)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (789:789:789) (772:772:772)) + (PORT ena (1129:1129:1129) (1100:1100:1100)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1358:1358:1358) (1351:1351:1351)) + (PORT datab (357:357:357) (377:377:377)) + (PORT datad (596:596:596) (592:592:592)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1145:1145:1145) (1120:1120:1120)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (653:653:653)) + (PORT datab (309:309:309) (326:326:326)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (807:807:807) (781:781:781)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (1094:1094:1094) (1114:1114:1114)) + (PORT datad (343:343:343) (362:362:362)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[6\]) + (DELAY + (ABSOLUTE + (PORT datab (748:748:748) (733:733:733)) + (PORT datad (969:969:969) (981:981:981)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1375:1375:1375)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1413:1413:1413) (1379:1379:1379)) + (PORT ena (1868:1868:1868) (1840:1840:1840)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (248:248:248)) + (PORT datab (810:810:810) (820:820:820)) + (PORT datac (576:576:576) (595:595:595)) + (PORT datad (167:167:167) (191:191:191)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (226:226:226)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (538:538:538) (526:526:526)) + (PORT datad (163:163:163) (188:188:188)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (1155:1155:1155) (1116:1116:1116)) + (PORT datab (838:838:838) (846:846:846)) + (PORT datac (352:352:352) (396:396:396)) + (PORT datad (847:847:847) (878:878:878)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT asdata (828:828:828) (822:822:822)) + (PORT ena (1110:1110:1110) (1083:1083:1083)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (624:624:624)) + (PORT datab (572:572:572) (595:595:595)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1364:1364:1364)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1088:1088:1088) (1053:1053:1053)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (563:563:563) (577:577:577)) + (PORT datad (386:386:386) (433:433:433)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (361:361:361)) + (PORT datab (375:375:375) (391:391:391)) + (PORT datac (388:388:388) (431:431:431)) + (PORT datad (1373:1373:1373) (1406:1406:1406)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (578:578:578)) + (PORT datab (213:213:213) (251:251:251)) + (PORT datac (516:516:516) (514:514:514)) + (PORT datad (1241:1241:1241) (1231:1231:1231)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (770:770:770) (827:827:827)) + (PORT datab (814:814:814) (825:825:825)) + (PORT datac (582:582:582) (601:601:601)) + (PORT datad (752:752:752) (736:736:736)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1670:1670:1670) (1654:1654:1654)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (530:530:530) (527:527:527)) + (PORT datad (201:201:201) (236:236:236)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (771:771:771) (818:818:818)) + (PORT datad (755:755:755) (744:744:744)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (222:222:222)) + (PORT datab (1137:1137:1137) (1146:1146:1146)) + (PORT datac (815:815:815) (808:808:808)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (802:802:802)) + (PORT datab (1073:1073:1073) (1071:1071:1071)) + (PORT datac (1059:1059:1059) (1049:1049:1049)) + (PORT datad (570:570:570) (583:583:583)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1109:1109:1109) (1126:1126:1126)) + (PORT datab (627:627:627) (647:647:647)) + (PORT datad (1007:1007:1007) (988:988:988)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (1250:1250:1250) (1267:1267:1267)) + (PORT ena (1154:1154:1154) (1145:1145:1145)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|db\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1184:1184:1184) (1237:1237:1237)) + (PORT datab (860:860:860) (853:853:853)) + (PORT datad (1273:1273:1273) (1261:1261:1261)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1108:1108:1108) (1081:1081:1081)) + (PORT ena (1307:1307:1307) (1269:1269:1269)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (1092:1092:1092) (1083:1083:1083)) + (PORT ena (901:901:901) (894:894:894)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (1094:1094:1094) (1083:1083:1083)) + (PORT ena (843:843:843) (827:827:827)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (422:422:422)) + (PORT datab (416:416:416) (438:438:438)) + (PORT datad (197:197:197) (254:254:254)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (748:748:748) (744:744:744)) + (PORT datab (582:582:582) (611:611:611)) + (PORT datad (565:565:565) (583:583:583)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1081:1081:1081) (1050:1050:1050)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT asdata (916:916:916) (931:931:931)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT asdata (915:915:915) (931:931:931)) + (PORT ena (879:879:879) (881:881:881)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (405:405:405)) + (PORT datab (218:218:218) (264:264:264)) + (PORT datad (190:190:190) (217:217:217)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1091:1091:1091) (1066:1066:1066)) + (PORT ena (1564:1564:1564) (1566:1566:1566)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1089:1089:1089) (1063:1063:1063)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (303:303:303)) + (PORT datab (1296:1296:1296) (1366:1366:1366)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (295:295:295)) + (PORT datab (566:566:566) (585:585:585)) + (PORT datac (351:351:351) (373:373:373)) + (PORT datad (287:287:287) (295:295:295)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (599:599:599)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (484:484:484) (477:477:477)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (995:995:995) (958:958:958)) + (PORT datab (1108:1108:1108) (1090:1090:1090)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (606:606:606) (617:617:617)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1057:1057:1057) (1033:1033:1033)) + (PORT ena (1129:1129:1129) (1100:1100:1100)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1357:1357:1357) (1350:1350:1350)) + (PORT datab (1089:1089:1089) (1108:1108:1108)) + (PORT datad (604:604:604) (597:597:597)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1145:1145:1145) (1120:1120:1120)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (311:311:311) (333:333:333)) + (PORT datac (604:604:604) (618:618:618)) + (PORT datad (199:199:199) (257:257:257)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (398:398:398)) + (PORT datab (200:200:200) (232:232:232)) + (PORT datac (1090:1090:1090) (1109:1109:1109)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[0\]) + (DELAY + (ABSOLUTE + (PORT datac (810:810:810) (827:827:827)) + (PORT datad (733:733:733) (711:711:711)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1400:1400:1400) (1370:1370:1370)) + (PORT ena (1646:1646:1646) (1626:1626:1626)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) + (DELAY + (ABSOLUTE + (PORT dataa (1344:1344:1344) (1326:1326:1326)) + (PORT datab (1011:1011:1011) (1021:1021:1021)) + (PORT datac (614:614:614) (618:618:618)) + (PORT datad (1032:1032:1032) (1028:1028:1028)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (665:665:665)) + (PORT datab (1303:1303:1303) (1283:1283:1283)) + (PORT datac (161:161:161) (195:195:195)) + (PORT datad (1267:1267:1267) (1243:1243:1243)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1145:1145:1145) (1120:1120:1120)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (1349:1349:1349) (1350:1350:1350)) + (PORT ena (901:901:901) (894:894:894)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (1352:1352:1352) (1353:1353:1353)) + (PORT ena (843:843:843) (827:827:827)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (420:420:420)) + (PORT datab (411:411:411) (427:427:427)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (913:913:913) (936:936:936)) + (PORT ena (1141:1141:1141) (1133:1133:1133)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT asdata (1270:1270:1270) (1295:1295:1295)) + (PORT ena (764:764:764) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1070:1070:1070) (1127:1127:1127)) + (PORT datab (617:617:617) (660:660:660)) + (PORT datad (809:809:809) (835:835:835)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT asdata (1362:1362:1362) (1354:1354:1354)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1312:1312:1312) (1318:1318:1318)) + (PORT ena (1142:1142:1142) (1145:1145:1145)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (699:699:699)) + (PORT datab (628:628:628) (648:648:648)) + (PORT datad (590:590:590) (603:603:603)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (1312:1312:1312) (1318:1318:1318)) + (PORT ena (1081:1081:1081) (1050:1050:1050)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (409:409:409)) + (PORT datab (179:179:179) (211:211:211)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (312:312:312) (325:325:325)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (833:833:833) (828:828:828)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (854:854:854) (859:859:859)) + (PORT datab (1248:1248:1248) (1234:1234:1234)) + (PORT datac (774:774:774) (776:776:776)) + (PORT datad (772:772:772) (803:803:803)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (335:335:335)) + (PORT datab (571:571:571) (587:587:587)) + (PORT datad (299:299:299) (299:299:299)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (860:860:860) (859:859:859)) + (PORT ena (1307:1307:1307) (1269:1269:1269)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (552:552:552) (550:550:550)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (764:764:764) (779:779:779)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (292:292:292)) + (PORT datab (1006:1006:1006) (988:988:988)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT asdata (1124:1124:1124) (1127:1127:1127)) + (PORT ena (1053:1053:1053) (1033:1033:1033)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (592:592:592) (620:620:620)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1141:1141:1141) (1140:1140:1140)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (581:581:581) (602:602:602)) + (PORT datab (865:865:865) (884:884:884)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (493:493:493) (486:486:486)) + (PORT datab (346:346:346) (352:352:352)) + (PORT datac (767:767:767) (747:747:747)) + (PORT datad (296:296:296) (288:288:288)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (751:751:751) (763:763:763)) + (PORT datab (540:540:540) (527:527:527)) + (PORT datac (1062:1062:1062) (1058:1058:1058)) + (PORT datad (612:612:612) (638:638:638)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (789:789:789) (771:771:771)) + (PORT ena (1129:1129:1129) (1100:1100:1100)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1357:1357:1357) (1351:1351:1351)) + (PORT datab (357:357:357) (373:373:373)) + (PORT datad (597:597:597) (591:591:591)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (654:654:654)) + (PORT datac (197:197:197) (264:264:264)) + (PORT datad (310:310:310) (319:319:319)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (400:400:400)) + (PORT datab (1122:1122:1122) (1138:1138:1138)) + (PORT datac (162:162:162) (197:197:197)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (1238:1238:1238) (1226:1226:1226)) + (PORT datad (498:498:498) (488:488:488)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (524:524:524) (516:516:516)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1375:1375:1375)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1413:1413:1413) (1379:1379:1379)) + (PORT ena (1868:1868:1868) (1840:1840:1840)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (665:665:665)) + (PORT datab (1069:1069:1069) (1065:1065:1065)) + (PORT datac (613:613:613) (616:616:616)) + (PORT datad (1297:1297:1297) (1280:1280:1280)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (228:228:228)) + (PORT datab (1302:1302:1302) (1282:1282:1282)) + (PORT datac (1277:1277:1277) (1257:1257:1257)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (599:599:599)) + (PORT datab (572:572:572) (566:566:566)) + (PORT datac (548:548:548) (583:583:583)) + (PORT datad (610:610:610) (648:648:648)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (217:217:217)) + (PORT datab (1131:1131:1131) (1148:1148:1148)) + (PORT datac (812:812:812) (821:821:821)) + (PORT datad (194:194:194) (225:225:225)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (329:329:329)) + (PORT datab (654:654:654) (676:676:676)) + (PORT datac (1058:1058:1058) (1052:1052:1052)) + (PORT datad (343:343:343) (347:347:347)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (554:554:554) (572:572:572)) + (PORT datab (386:386:386) (389:389:389)) + (PORT datac (503:503:503) (490:490:490)) + (PORT datad (567:567:567) (578:578:578)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (245:245:245)) + (PORT datab (1038:1038:1038) (1006:1006:1006)) + (PORT datac (783:783:783) (775:775:775)) + (PORT datad (318:318:318) (321:321:321)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (271:271:271)) + (PORT datab (179:179:179) (211:211:211)) + (PORT datac (530:530:530) (528:528:528)) + (PORT datad (175:175:175) (197:197:197)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (686:686:686) (741:741:741)) + (PORT datac (185:185:185) (221:221:221)) + (PORT datad (201:201:201) (224:224:224)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (828:828:828)) + (PORT datab (623:623:623) (651:651:651)) + (PORT datac (1273:1273:1273) (1248:1248:1248)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (824:824:824) (808:808:808)) + (PORT ena (1486:1486:1486) (1479:1479:1479)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (850:850:850) (862:862:862)) + (PORT datab (1468:1468:1468) (1502:1502:1502)) + (PORT datac (792:792:792) (814:814:814)) + (PORT datad (382:382:382) (437:437:437)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (722:722:722) (789:789:789)) + (PORT datab (238:238:238) (290:290:290)) + (PORT datac (785:785:785) (804:804:804)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (752:752:752) (787:787:787)) + (PORT datab (825:825:825) (821:821:821)) + (PORT datad (683:683:683) (704:704:704)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (1214:1214:1214) (1194:1194:1194)) + (PORT datac (187:187:187) (224:224:224)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (897:897:897)) + (PORT datab (995:995:995) (1034:1034:1034)) + (PORT datac (829:829:829) (842:842:842)) + (PORT datad (592:592:592) (606:606:606)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (653:653:653)) + (PORT datab (788:788:788) (778:778:778)) + (PORT datac (573:573:573) (592:592:592)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1344:1344:1344)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (746:746:746) (759:759:759)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (648:648:648)) + (PORT datab (784:784:784) (815:815:815)) + (PORT datac (763:763:763) (754:754:754)) + (PORT datad (580:580:580) (598:598:598)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (572:572:572) (595:595:595)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1344:1344:1344)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (746:746:746) (759:759:759)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (426:426:426) (478:478:478)) + (PORT datab (548:548:548) (553:553:553)) + (PORT datac (598:598:598) (640:640:640)) + (PORT datad (774:774:774) (769:769:769)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (347:347:347)) + (PORT datac (180:180:180) (212:212:212)) + (PORT datad (164:164:164) (189:189:189)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~1) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (349:349:349)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datac (321:321:321) (331:331:331)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (636:636:636)) + (PORT datab (796:796:796) (793:793:793)) + (PORT datac (1887:1887:1887) (1861:1861:1861)) + (PORT datad (760:760:760) (829:829:829)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (871:871:871) (911:911:911)) + (PORT datac (608:608:608) (612:612:612)) + (PORT datad (576:576:576) (574:574:574)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1504:1504:1504) (1460:1460:1460)) + (PORT datab (664:664:664) (666:666:666)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (900:900:900) (877:877:877)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (462:462:462)) + (PORT datab (242:242:242) (295:295:295)) + (PORT datad (558:558:558) (568:568:568)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (592:592:592)) + (PORT datab (547:547:547) (536:536:536)) + (PORT datac (786:786:786) (801:801:801)) + (PORT datad (162:162:162) (183:183:183)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (542:542:542) (535:535:535)) + (PORT datab (205:205:205) (243:243:243)) + (PORT datac (792:792:792) (794:794:794)) + (PORT datad (717:717:717) (746:746:746)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (646:646:646)) + (PORT datab (1050:1050:1050) (1044:1044:1044)) + (PORT datac (155:155:155) (184:184:184)) + (PORT datad (503:503:503) (495:495:495)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1722:1722:1722) (1670:1670:1670)) + (PORT datab (185:185:185) (222:222:222)) + (PORT datac (813:813:813) (829:829:829)) + (PORT datad (310:310:310) (313:313:313)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1025:1025:1025) (1007:1007:1007)) + (PORT datab (1283:1283:1283) (1310:1310:1310)) + (PORT datac (749:749:749) (727:727:727)) + (PORT datad (523:523:523) (511:511:511)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (750:750:750) (736:736:736)) + (PORT datab (329:329:329) (352:352:352)) + (PORT datac (983:983:983) (977:977:977)) + (PORT datad (986:986:986) (957:957:957)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (239:239:239)) + (PORT datab (195:195:195) (234:234:234)) + (PORT datac (556:556:556) (550:550:550)) + (PORT datad (548:548:548) (535:535:535)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (881:881:881)) + (PORT datab (851:851:851) (855:855:855)) + (PORT datac (1109:1109:1109) (1124:1124:1124)) + (PORT datad (583:583:583) (577:577:577)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (218:218:218)) + (PORT datab (207:207:207) (242:242:242)) + (PORT datac (795:795:795) (786:786:786)) + (PORT datad (574:574:574) (581:581:581)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~14) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (260:260:260)) + (PORT datab (1413:1413:1413) (1394:1394:1394)) + (PORT datac (1114:1114:1114) (1128:1128:1128)) + (PORT datad (631:631:631) (658:658:658)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~13) + (DELAY + (ABSOLUTE + (PORT datac (168:168:168) (205:205:205)) + (PORT datad (172:172:172) (203:203:203)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~15) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (740:740:740)) + (PORT datab (328:328:328) (356:356:356)) + (PORT datac (486:486:486) (478:478:478)) + (PORT datad (752:752:752) (726:726:726)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~16) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (594:594:594)) + (PORT datab (613:613:613) (607:607:607)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (571:571:571)) + (PORT datab (1318:1318:1318) (1318:1318:1318)) + (PORT datac (1353:1353:1353) (1333:1333:1333)) + (PORT datad (177:177:177) (198:198:198)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1103:1103:1103) (1127:1127:1127)) + (PORT datab (1315:1315:1315) (1318:1318:1318)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (773:773:773) (760:760:760)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (931:931:931)) + (PORT datab (1088:1088:1088) (1105:1105:1105)) + (PORT datac (581:581:581) (579:579:579)) + (PORT datad (1254:1254:1254) (1262:1262:1262)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_set\~0) + (DELAY + (ABSOLUTE + (PORT dataa (775:775:775) (756:756:756)) + (PORT datab (1282:1282:1282) (1306:1306:1306)) + (PORT datac (997:997:997) (976:976:976)) + (PORT datad (1570:1570:1570) (1561:1561:1561)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M2T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (1661:1661:1661) (1703:1703:1703)) + (PORT datab (622:622:622) (635:635:635)) + (PORT datac (958:958:958) (1001:1001:1001)) + (PORT datad (307:307:307) (321:321:321)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) + (DELAY + (ABSOLUTE + (PORT dataa (795:795:795) (779:779:779)) + (PORT datab (586:586:586) (592:592:592)) + (PORT datac (175:175:175) (207:207:207)) + (PORT datad (576:576:576) (592:592:592)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) + (DELAY + (ABSOLUTE + (PORT dataa (519:519:519) (509:509:509)) + (PORT datab (598:598:598) (591:591:591)) + (PORT datac (523:523:523) (524:524:524)) + (PORT datad (301:301:301) (304:304:304)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (841:841:841)) + (PORT datab (1022:1022:1022) (1015:1015:1015)) + (PORT datac (751:751:751) (771:771:771)) + (PORT datad (545:545:545) (538:538:538)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (839:839:839)) + (PORT datab (408:408:408) (448:448:448)) + (PORT datac (300:300:300) (309:309:309)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) + (DELAY + (ABSOLUTE + (PORT datab (873:873:873) (913:913:913)) + (PORT datac (630:630:630) (633:633:633)) + (PORT datad (856:856:856) (860:860:860)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (649:649:649)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (572:572:572) (588:588:588)) + (PORT datad (1460:1460:1460) (1421:1421:1421)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (796:796:796) (783:783:783)) + (PORT datab (187:187:187) (221:221:221)) + (PORT datac (201:201:201) (272:272:272)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (784:784:784)) + (PORT datab (328:328:328) (339:339:339)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (1464:1464:1464) (1423:1423:1423)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1288:1288:1288) (1383:1383:1383)) + (PORT datab (2378:2378:2378) (2489:2489:2489)) + (PORT datac (1127:1127:1127) (1135:1135:1135)) + (PORT datad (1220:1220:1220) (1332:1332:1332)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (386:386:386)) + (PORT datab (594:594:594) (621:621:621)) + (PORT datac (1586:1586:1586) (1604:1604:1604)) + (PORT datad (784:784:784) (791:791:791)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (625:625:625)) + (PORT datab (610:610:610) (627:627:627)) + (PORT datad (1030:1030:1030) (1019:1019:1019)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1704:1704:1704) (1749:1749:1749)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (754:754:754) (736:736:736)) + (PORT datad (1097:1097:1097) (1087:1087:1087)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1062:1062:1062) (1023:1023:1023)) + (PORT datab (792:792:792) (810:810:810)) + (PORT datac (1075:1075:1075) (1067:1067:1067)) + (PORT datad (1030:1030:1030) (1003:1003:1003)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (302:302:302)) + (PORT datab (237:237:237) (306:306:306)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (787:787:787) (766:766:766)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (977:977:977)) + (PORT datab (821:821:821) (803:803:803)) + (PORT datac (948:948:948) (1019:1019:1019)) + (PORT datad (1170:1170:1170) (1213:1213:1213)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (255:255:255)) + (PORT datab (1290:1290:1290) (1358:1358:1358)) + (PORT datac (1813:1813:1813) (1806:1806:1806)) + (PORT datad (842:842:842) (852:852:852)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (229:229:229)) + (PORT datab (916:916:916) (956:956:956)) + (PORT datac (1087:1087:1087) (1096:1096:1096)) + (PORT datad (1318:1318:1318) (1350:1350:1350)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1078:1078:1078) (1041:1041:1041)) + (PORT datab (182:182:182) (216:216:216)) + (PORT datac (593:593:593) (607:607:607)) + (PORT datad (812:812:812) (811:811:811)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (616:616:616)) + (PORT datab (1150:1150:1150) (1159:1159:1159)) + (PORT datac (167:167:167) (204:204:204)) + (PORT datad (581:581:581) (590:590:590)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (590:590:590)) + (PORT datab (584:584:584) (567:567:567)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (301:301:301) (301:301:301)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal64\~0) + (DELAY + (ABSOLUTE + (PORT datac (885:885:885) (939:939:939)) + (PORT datad (784:784:784) (769:769:769)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~1) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (585:585:585) (567:567:567)) + (PORT datac (185:185:185) (223:223:223)) + (PORT datad (177:177:177) (198:198:198)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (833:833:833)) + (PORT datab (1840:1840:1840) (1853:1853:1853)) + (PORT datac (1259:1259:1259) (1237:1237:1237)) + (PORT datad (1938:1938:1938) (2052:2052:2052)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (817:817:817)) + (PORT datab (179:179:179) (211:211:211)) + (PORT datac (193:193:193) (233:233:233)) + (PORT datad (175:175:175) (206:206:206)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (810:810:810)) + (PORT datab (194:194:194) (234:234:234)) + (PORT datac (1107:1107:1107) (1125:1125:1125)) + (PORT datad (824:824:824) (823:823:823)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (230:230:230)) + (PORT datab (1087:1087:1087) (1104:1104:1104)) + (PORT datad (168:168:168) (194:194:194)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1149:1149:1149) (1163:1163:1163)) + (PORT datab (627:627:627) (661:661:661)) + (PORT datac (749:749:749) (747:747:747)) + (PORT datad (1545:1545:1545) (1549:1549:1549)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (543:543:543)) + (PORT datab (760:760:760) (753:753:753)) + (PORT datac (552:552:552) (548:548:548)) + (PORT datad (600:600:600) (608:608:608)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (619:619:619) (615:615:615)) + (PORT datac (325:325:325) (328:328:328)) + (PORT datad (568:568:568) (561:561:561)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1263:1263:1263) (1247:1247:1247)) + (PORT datab (872:872:872) (866:866:866)) + (PORT datac (987:987:987) (967:967:967)) + (PORT datad (1315:1315:1315) (1307:1307:1307)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (360:360:360)) + (PORT datab (582:582:582) (586:586:586)) + (PORT datac (173:173:173) (203:203:203)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (666:666:666)) + (PORT datab (912:912:912) (924:924:924)) + (PORT datac (1861:1861:1861) (1883:1883:1883)) + (PORT datad (298:298:298) (308:308:308)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) + (DELAY + (ABSOLUTE + (PORT datab (756:756:756) (737:737:737)) + (PORT datac (192:192:192) (230:230:230)) + (PORT datad (780:780:780) (771:771:771)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (323:323:323) (333:333:333)) + (PORT datac (155:155:155) (184:184:184)) + (PORT datad (567:567:567) (575:575:575)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_cf) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (579:579:579)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (532:532:532) (514:514:514)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1046:1046:1046) (1034:1034:1034)) + (PORT datab (1121:1121:1121) (1089:1089:1089)) + (PORT datac (1082:1082:1082) (1084:1084:1084)) + (PORT datad (1263:1263:1263) (1252:1252:1252)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1055:1055:1055) (1024:1024:1024)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (181:181:181) (217:217:217)) + (PORT datad (492:492:492) (488:488:488)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) + (DELAY + (ABSOLUTE + (PORT datab (783:783:783) (761:761:761)) + (PORT datac (1010:1010:1010) (1006:1006:1006)) + (PORT datad (766:766:766) (740:740:740)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (769:769:769) (752:752:752)) + (PORT datab (832:832:832) (820:820:820)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1375:1375:1375)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~9) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (866:866:866)) + (PORT datab (843:843:843) (826:826:826)) + (PORT datac (1308:1308:1308) (1302:1302:1302)) + (PORT datad (815:815:815) (797:797:797)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1124:1124:1124)) + (PORT datab (819:819:819) (825:825:825)) + (PORT datac (1042:1042:1042) (1037:1037:1037)) + (PORT datad (883:883:883) (887:887:887)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1103:1103:1103) (1129:1129:1129)) + (PORT datab (1314:1314:1314) (1321:1321:1321)) + (PORT datac (174:174:174) (206:206:206)) + (PORT datad (501:501:501) (491:491:491)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (617:617:617)) + (PORT datab (609:609:609) (661:661:661)) + (PORT datac (994:994:994) (974:974:974)) + (PORT datad (508:508:508) (499:499:499)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (680:680:680)) + (PORT datab (1242:1242:1242) (1213:1213:1213)) + (PORT datac (886:886:886) (899:899:899)) + (PORT datad (345:345:345) (354:354:354)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (227:227:227)) + (PORT datab (1083:1083:1083) (1080:1080:1080)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (548:548:548) (545:545:545)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (536:536:536) (542:542:542)) + (PORT datab (767:767:767) (749:749:749)) + (PORT datac (525:525:525) (518:518:518)) + (PORT datad (521:521:521) (509:509:509)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (935:935:935) (943:943:943)) + (PORT ena (901:901:901) (894:894:894)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (935:935:935) (943:943:943)) + (PORT ena (843:843:843) (827:827:827)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (422:422:422)) + (PORT datab (415:415:415) (432:432:432)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1107:1107:1107) (1127:1127:1127)) + (PORT datab (795:795:795) (803:803:803)) + (PORT datad (555:555:555) (556:556:556)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (1097:1097:1097) (1081:1081:1081)) + (PORT ena (1141:1141:1141) (1133:1133:1133)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (922:922:922) (926:926:926)) + (PORT ena (1564:1564:1564) (1566:1566:1566)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (923:923:923) (929:929:929)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (302:302:302)) + (PORT datab (1296:1296:1296) (1366:1366:1366)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (619:619:619) (659:659:659)) + (PORT datad (565:565:565) (576:576:576)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT asdata (890:890:890) (901:901:901)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (1095:1095:1095) (1081:1081:1081)) + (PORT ena (1173:1173:1173) (1181:1181:1181)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (697:697:697)) + (PORT datab (668:668:668) (693:693:693)) + (PORT datad (955:955:955) (935:935:935)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT asdata (1102:1102:1102) (1084:1084:1084)) + (PORT ena (1053:1053:1053) (1033:1033:1033)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT asdata (1101:1101:1101) (1086:1086:1086)) + (PORT ena (1141:1141:1141) (1140:1140:1140)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (604:604:604)) + (PORT datab (870:870:870) (885:885:885)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1081:1081:1081) (1050:1050:1050)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (622:622:622)) + (PORT datab (597:597:597) (595:595:595)) + (PORT datac (350:350:350) (375:375:375)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (752:752:752) (738:738:738)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (596:596:596) (605:605:605)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (1107:1107:1107) (1090:1090:1090)) + (PORT datac (1007:1007:1007) (970:970:970)) + (PORT datad (605:605:605) (618:618:618)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1356:1356:1356) (1350:1350:1350)) + (PORT datab (621:621:621) (631:631:631)) + (PORT datad (773:773:773) (746:746:746)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (429:429:429)) + (PORT datac (605:605:605) (616:616:616)) + (PORT datad (307:307:307) (313:313:313)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (455:455:455)) + (PORT datad (184:184:184) (207:207:207)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (545:545:545) (527:527:527)) + (PORT datab (223:223:223) (262:262:262)) + (PORT datac (1106:1106:1106) (1126:1126:1126)) + (PORT datad (573:573:573) (567:567:567)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[4\]) + (DELAY + (ABSOLUTE + (PORT dataa (1013:1013:1013) (1021:1021:1021)) + (PORT datad (791:791:791) (761:761:761)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1375:1375:1375)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1413:1413:1413) (1379:1379:1379)) + (PORT ena (1868:1868:1868) (1840:1840:1840)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (453:453:453)) + (PORT datab (358:358:358) (413:413:413)) + (PORT datac (219:219:219) (288:288:288)) + (PORT datad (215:215:215) (272:272:272)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (465:465:465)) + (PORT datab (384:384:384) (430:430:430)) + (PORT datac (366:366:366) (417:417:417)) + (PORT datad (217:217:217) (275:275:275)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1218:1218:1218) (1226:1226:1226)) + (PORT datab (650:650:650) (687:687:687)) + (PORT datac (550:550:550) (587:587:587)) + (PORT datad (218:218:218) (276:276:276)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (449:449:449)) + (PORT datab (382:382:382) (435:435:435)) + (PORT datac (517:517:517) (540:540:540)) + (PORT datad (353:353:353) (389:389:389)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) + (DELAY + (ABSOLUTE + (PORT dataa (801:801:801) (787:787:787)) + (PORT datab (760:760:760) (767:767:767)) + (PORT datac (571:571:571) (575:575:575)) + (PORT datad (578:578:578) (584:584:584)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (954:954:954)) + (PORT datab (639:639:639) (647:647:647)) + (PORT datad (570:570:570) (579:579:579)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1393:1393:1393) (1364:1364:1364)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (909:909:909)) + (PORT datab (590:590:590) (602:602:602)) + (PORT datac (779:779:779) (786:786:786)) + (PORT datad (585:585:585) (601:601:601)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal79\~0) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (566:566:566)) + (PORT datab (2427:2427:2427) (2430:2430:2430)) + (PORT datac (1911:1911:1911) (1993:1993:1993)) + (PORT datad (1331:1331:1331) (1300:1300:1300)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (542:542:542)) + (PORT datab (565:565:565) (605:605:605)) + (PORT datad (1058:1058:1058) (1048:1048:1048)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT dataa (298:298:298) (401:401:401)) + (PORT datac (667:667:667) (721:721:721)) + (PORT datad (239:239:239) (310:310:310)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1148:1148:1148) (1126:1126:1126)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1379:1379:1379) (1357:1357:1357)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (217:217:217)) + (PORT datab (1280:1280:1280) (1254:1254:1254)) + (PORT datac (793:793:793) (810:810:810)) + (PORT datad (212:212:212) (277:277:277)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (314:314:314)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (900:900:900) (918:918:918)) + (PORT datad (775:775:775) (783:783:783)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (952:952:952)) + (PORT datab (1277:1277:1277) (1250:1250:1250)) + (PORT datac (559:559:559) (577:577:577)) + (PORT datad (852:852:852) (864:864:864)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) + (DELAY + (ABSOLUTE + (PORT dataa (802:802:802) (820:820:820)) + (PORT datab (591:591:591) (628:628:628)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (585:585:585) (599:599:599)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (949:949:949)) + (PORT datab (2006:2006:2006) (2121:2121:2121)) + (PORT datac (1252:1252:1252) (1225:1225:1225)) + (PORT datad (1231:1231:1231) (1319:1319:1319)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (956:956:956)) + (PORT datab (861:861:861) (884:884:884)) + (PORT datac (560:560:560) (573:573:573)) + (PORT datad (774:774:774) (782:782:782)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (818:818:818)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (585:585:585) (603:603:603)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (347:347:347)) + (PORT datab (232:232:232) (271:271:271)) + (PORT datac (340:340:340) (352:352:352)) + (PORT datad (534:534:534) (521:521:521)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1721:1721:1721) (1724:1724:1724)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (370:370:370)) + (PORT datab (331:331:331) (346:346:346)) + (PORT datac (295:295:295) (312:312:312)) + (PORT datad (175:175:175) (197:197:197)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out) + (DELAY + (ABSOLUTE + (PORT datab (1160:1160:1160) (1187:1187:1187)) + (PORT datad (729:729:729) (700:700:700)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (473:473:473) (461:461:461)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (417:417:417)) + (PORT datab (901:901:901) (920:920:920)) + (PORT datac (893:893:893) (901:901:901)) + (PORT datad (866:866:866) (872:872:872)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (913:913:913)) + (PORT datab (738:738:738) (729:729:729)) + (PORT datac (770:770:770) (768:768:768)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1130:1130:1130) (1140:1140:1140)) + (PORT datab (939:939:939) (945:945:945)) + (PORT datac (1059:1059:1059) (1064:1064:1064)) + (PORT datad (1065:1065:1065) (1058:1058:1058)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (623:623:623)) + (PORT datab (206:206:206) (242:242:242)) + (PORT datac (506:506:506) (499:499:499)) + (PORT datad (324:324:324) (336:336:336)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) + (DELAY + (ABSOLUTE + (PORT dataa (778:778:778) (767:767:767)) + (PORT datab (583:583:583) (577:577:577)) + (PORT datac (515:515:515) (511:511:511)) + (PORT datad (506:506:506) (499:499:499)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11) + (DELAY + (ABSOLUTE + (PORT datab (1046:1046:1046) (1039:1039:1039)) + (PORT datac (294:294:294) (299:299:299)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) + (DELAY + (ABSOLUTE + (PORT dataa (581:581:581) (592:592:592)) + (PORT datab (1202:1202:1202) (1219:1219:1219)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (764:764:764) (752:752:752)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (589:589:589) (614:614:614)) + (PORT datab (867:867:867) (890:890:890)) + (PORT datac (1083:1083:1083) (1096:1096:1096)) + (PORT datad (730:730:730) (695:695:695)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (775:775:775) (740:740:740)) + (PORT datab (624:624:624) (649:649:649)) + (PORT datac (606:606:606) (638:638:638)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) + (DELAY + (ABSOLUTE + (PORT dataa (625:625:625) (651:651:651)) + (PORT datab (896:896:896) (950:950:950)) + (PORT datad (473:473:473) (451:451:451)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|flags_cond_true) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1212:1212:1212) (1253:1253:1253)) + (PORT datab (921:921:921) (956:956:956)) + (PORT datac (1029:1029:1029) (1009:1009:1009)) + (PORT datad (1447:1447:1447) (1466:1466:1466)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1368:1368:1368) (1363:1363:1363)) + (PORT datab (1074:1074:1074) (1036:1036:1036)) + (PORT datac (1010:1010:1010) (983:983:983)) + (PORT datad (558:558:558) (564:564:564)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (592:592:592)) + (PORT datab (205:205:205) (241:241:241)) + (PORT datac (569:569:569) (575:575:575)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (922:922:922)) + (PORT datac (875:875:875) (897:897:897)) + (PORT datad (1123:1123:1123) (1138:1138:1138)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (622:622:622)) + (PORT datab (1335:1335:1335) (1352:1352:1352)) + (PORT datac (545:545:545) (562:562:562)) + (PORT datad (539:539:539) (545:545:545)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT asdata (691:691:691) (703:703:703)) + (PORT ena (1110:1110:1110) (1083:1083:1083)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (620:620:620)) + (PORT datab (576:576:576) (595:595:595)) + (PORT datad (558:558:558) (575:575:575)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1364:1364:1364)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1088:1088:1088) (1053:1053:1053)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (520:520:520) (515:515:515)) + (PORT datab (548:548:548) (548:548:548)) + (PORT datad (198:198:198) (256:256:256)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (425:425:425) (464:464:464)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (1370:1370:1370) (1399:1399:1399)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[11\]) + (DELAY + (ABSOLUTE + (PORT datac (810:810:810) (830:830:830)) + (PORT datad (323:323:323) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1400:1400:1400) (1370:1370:1370)) + (PORT ena (1646:1646:1646) (1626:1626:1626)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) + (DELAY + (ABSOLUTE + (PORT datac (389:389:389) (423:423:423)) + (PORT datad (318:318:318) (320:320:320)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1090:1090:1090) (1124:1124:1124)) + (PORT datab (364:364:364) (369:369:369)) + (PORT datad (515:515:515) (492:492:492)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -29643,12 +31064,12 @@ (INSTANCE z80_\|execute_\|ctl_apin_mux2\~0) (DELAY (ABSOLUTE - (PORT dataa (879:879:879) (920:920:920)) - (PORT datab (921:921:921) (968:968:968)) - (PORT datac (1740:1740:1740) (1842:1842:1842)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (PORT dataa (1276:1276:1276) (1394:1394:1394)) + (PORT datac (1230:1230:1230) (1303:1303:1303)) + (PORT datad (2345:2345:2345) (2358:2358:2358)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -29657,13 +31078,13 @@ (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~2) (DELAY (ABSOLUTE - (PORT dataa (1557:1557:1557) (1646:1646:1646)) - (PORT datab (908:908:908) (918:918:918)) - (PORT datac (878:878:878) (894:894:894)) - (PORT datad (1117:1117:1117) (1116:1116:1116)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1058:1058:1058) (1025:1025:1025)) + (PORT datab (864:864:864) (872:872:872)) + (PORT datac (761:761:761) (760:760:760)) + (PORT datad (1529:1529:1529) (1635:1635:1635)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -29673,653 +31094,13 @@ (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~3) (DELAY (ABSOLUTE - (PORT dataa (878:878:878) (919:919:919)) - (PORT datab (922:922:922) (968:968:968)) - (PORT datac (1740:1740:1740) (1842:1842:1842)) - (PORT datad (573:573:573) (588:588:588)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (544:544:544) (617:617:617)) - (PORT sload (1041:1041:1041) (1053:1053:1053)) - (PORT ena (1068:1068:1068) (1021:1021:1021)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[13\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1091:1091:1091) (1116:1116:1116)) - (PORT datad (1866:1866:1866) (1899:1899:1899)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1672:1672:1672) (1604:1604:1604)) - (PORT datab (199:199:199) (232:232:232)) - (PORT datad (304:304:304) (299:299:299)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (532:532:532) (598:598:598)) - (PORT sload (1041:1041:1041) (1053:1053:1053)) - (PORT ena (1068:1068:1068) (1021:1021:1021)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[14\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (1891:1891:1891) (1933:1933:1933)) - (PORT datad (1054:1054:1054) (1082:1082:1082)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1672:1672:1672) (1607:1607:1607)) - (PORT datab (319:319:319) (332:332:332)) - (PORT datad (517:517:517) (497:497:497)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (520:520:520) (588:588:588)) - (PORT sload (1041:1041:1041) (1053:1053:1053)) - (PORT ena (1068:1068:1068) (1021:1021:1021)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[15\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (1530:1530:1530) (1544:1544:1544)) - (PORT datac (1457:1457:1457) (1454:1454:1454)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (659:659:659)) - (PORT datab (230:230:230) (284:284:284)) - (PORT datac (331:331:331) (358:358:358)) - (PORT datad (1200:1200:1200) (1152:1152:1152)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (1881:1881:1881) (1928:1928:1928)) - (PORT datac (1050:1050:1050) (1076:1076:1076)) - (PORT datad (1051:1051:1051) (1083:1083:1083)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (880:880:880)) - (PORT datad (1844:1844:1844) (1865:1865:1865)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (799:799:799) (793:793:793)) - (PORT datab (348:348:348) (356:356:356)) - (PORT datad (316:316:316) (308:308:308)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1370:1370:1370) (1377:1377:1377)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (1041:1041:1041) (1043:1043:1043)) - (PORT sload (1115:1115:1115) (1155:1155:1155)) - (PORT ena (1333:1333:1333) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1659:1659:1659) (1683:1683:1683)) - (PORT datad (623:623:623) (656:656:656)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (802:802:802) (794:794:794)) - (PORT datab (560:560:560) (552:552:552)) - (PORT datad (491:491:491) (483:483:483)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1370:1370:1370) (1377:1377:1377)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (915:915:915) (930:930:930)) - (PORT sload (1115:1115:1115) (1155:1155:1155)) - (PORT ena (1333:1333:1333) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) - (DELAY - (ABSOLUTE - (PORT datac (1617:1617:1617) (1642:1642:1642)) - (PORT datad (587:587:587) (619:619:619)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (805:805:805) (801:801:801)) - (PORT datab (498:498:498) (489:489:489)) - (PORT datad (310:310:310) (319:319:319)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1370:1370:1370) (1377:1377:1377)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (688:688:688) (723:723:723)) - (PORT sload (1115:1115:1115) (1155:1155:1155)) - (PORT ena (1333:1333:1333) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) - (DELAY - (ABSOLUTE - (PORT datac (1622:1622:1622) (1649:1649:1649)) - (PORT datad (336:336:336) (379:379:379)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (799:799:799) (793:793:793)) - (PORT datab (499:499:499) (494:494:494)) - (PORT datad (310:310:310) (321:321:321)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1370:1370:1370) (1377:1377:1377)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (896:896:896) (916:916:916)) - (PORT sload (1115:1115:1115) (1155:1155:1155)) - (PORT ena (1333:1333:1333) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) - (DELAY - (ABSOLUTE - (PORT datac (1624:1624:1624) (1654:1654:1654)) - (PORT datad (595:595:595) (629:629:629)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1261:1261:1261) (1230:1230:1230)) - (PORT datab (320:320:320) (332:332:332)) - (PORT datad (179:179:179) (201:201:201)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (922:922:922) (957:957:957)) - (PORT sload (1062:1062:1062) (1091:1091:1091)) - (PORT ena (1086:1086:1086) (1050:1050:1050)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) - (DELAY - (ABSOLUTE - (PORT datab (1883:1883:1883) (1881:1881:1881)) - (PORT datac (621:621:621) (665:665:665)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datad (1236:1236:1236) (1194:1194:1194)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (1061:1061:1061) (1067:1067:1067)) - (PORT sload (1062:1062:1062) (1091:1091:1091)) - (PORT ena (1086:1086:1086) (1050:1050:1050)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) - (DELAY - (ABSOLUTE - (PORT datab (641:641:641) (694:694:694)) - (PORT datac (1617:1617:1617) (1643:1643:1643)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1264:1264:1264) (1232:1232:1232)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (1519:1519:1519) (1486:1486:1486)) - (PORT sload (1062:1062:1062) (1091:1091:1091)) - (PORT ena (1086:1086:1086) (1050:1050:1050)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) - (DELAY - (ABSOLUTE - (PORT datac (1615:1615:1615) (1647:1647:1647)) - (PORT datad (854:854:854) (894:894:894)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (314:314:314) (339:339:339)) - (PORT datab (1265:1265:1265) (1219:1219:1219)) - (PORT datad (179:179:179) (201:201:201)) + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (1766:1766:1766) (1849:1849:1849)) + (PORT datac (1952:1952:1952) (2012:2012:2012)) + (PORT datad (1530:1530:1530) (1637:1637:1637)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (536:536:536) (608:608:608)) - (PORT sload (1062:1062:1062) (1091:1091:1091)) - (PORT ena (1086:1086:1086) (1050:1050:1050)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) - (DELAY - (ABSOLUTE - (PORT datab (871:871:871) (913:913:913)) - (PORT datad (1856:1856:1856) (1888:1888:1888)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1294:1294:1294) (1266:1266:1266)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datad (511:511:511) (504:504:504)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (529:529:529) (605:605:605)) - (PORT sload (1033:1033:1033) (1049:1049:1049)) - (PORT ena (735:735:735) (733:733:733)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) - (DELAY - (ABSOLUTE - (PORT datac (1624:1624:1624) (1649:1649:1649)) - (PORT datad (626:626:626) (674:674:674)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (238:238:238)) - (PORT datab (532:532:532) (519:519:519)) - (PORT datad (1271:1271:1271) (1229:1229:1229)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (525:525:525) (601:601:601)) - (PORT sload (1033:1033:1033) (1049:1049:1049)) - (PORT ena (735:735:735) (733:733:733)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[10\]\~24) - (DELAY - (ABSOLUTE - (PORT datac (844:844:844) (879:879:879)) - (PORT datad (1349:1349:1349) (1383:1383:1383)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (237:237:237)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datad (1268:1268:1268) (1227:1227:1227)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -30329,11 +31110,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1358:1358:1358)) + (PORT clk (1349:1349:1349) (1359:1359:1359)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (842:842:842) (864:864:864)) - (PORT sload (1033:1033:1033) (1049:1049:1049)) - (PORT ena (735:735:735) (733:733:733)) + (PORT asdata (1088:1088:1088) (1091:1091:1091)) + (PORT sload (1315:1315:1315) (1359:1359:1359)) + (PORT ena (1338:1338:1338) (1327:1327:1327)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -30349,37 +31130,37 @@ (INSTANCE z80_\|address_pins_\|abus\[11\]\~19) (DELAY (ABSOLUTE - (PORT dataa (890:890:890) (913:913:913)) - (PORT datad (1349:1349:1349) (1385:1385:1385)) - (IOPATH dataa combout (273:273:273) (269:269:269)) + (PORT datac (1294:1294:1294) (1315:1315:1315)) + (PORT datad (1815:1815:1815) (1915:1915:1915)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) (DELAY (ABSOLUTE - (PORT dataa (316:316:316) (337:337:337)) - (PORT datab (756:756:756) (741:741:741)) - (PORT datad (1458:1458:1458) (1392:1392:1392)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (1094:1094:1094) (1120:1120:1120)) + (PORT datab (179:179:179) (211:211:211)) + (PORT datad (530:530:530) (516:516:516)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) (DELAY (ABSOLUTE (PORT clk (1349:1349:1349) (1359:1359:1359)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (524:524:524) (596:596:596)) - (PORT sload (1041:1041:1041) (1053:1053:1053)) - (PORT ena (1068:1068:1068) (1021:1021:1021)) + (PORT asdata (682:682:682) (728:728:728)) + (PORT sload (1315:1315:1315) (1359:1359:1359)) + (PORT ena (1338:1338:1338) (1327:1327:1327)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -30392,206 +31173,205 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[12\]\~21) + (INSTANCE z80_\|address_pins_\|abus\[10\]\~20) (DELAY (ABSOLUTE - (PORT dataa (1657:1657:1657) (1678:1678:1678)) - (PORT datad (796:796:796) (826:826:826)) + (PORT dataa (2140:2140:2140) (2276:2276:2276)) + (PORT datad (1301:1301:1301) (1350:1350:1350)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~19) (DELAY (ABSOLUTE - (PORT d[0] (942:942:942) (945:945:945)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT dataa (275:275:275) (380:380:380)) + (PORT datac (834:834:834) (854:854:854)) + (PORT datad (600:600:600) (625:625:625)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (930:930:930) (940:940:940)) - (PORT d[1] (1926:1926:1926) (2072:2072:2072)) - (PORT d[2] (1357:1357:1357) (1362:1362:1362)) - (PORT d[3] (2658:2658:2658) (2763:2763:2763)) - (PORT d[4] (2440:2440:2440) (2546:2546:2546)) - (PORT d[5] (2926:2926:2926) (3031:3031:3031)) - (PORT d[6] (1266:1266:1266) (1301:1301:1301)) - (PORT d[7] (2683:2683:2683) (2727:2727:2727)) - (PORT d[8] (924:924:924) (930:930:930)) - (PORT d[9] (1474:1474:1474) (1500:1500:1500)) - (PORT d[10] (1486:1486:1486) (1519:1519:1519)) - (PORT d[11] (2077:2077:2077) (2152:2152:2152)) - (PORT d[12] (1485:1485:1485) (1526:1526:1526)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (876:876:876) (848:848:848)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (PORT d[0] (1323:1323:1323) (1298:1298:1298)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1634:1634:1634)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (878:878:878) (881:881:881)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1680:1680:1680) (1699:1699:1699)) - (PORT asdata (1873:1873:1873) (1892:1892:1892)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) - (PORT asdata (1325:1325:1325) (1320:1320:1320)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~48) (DELAY (ABSOLUTE - (PORT dataa (630:630:630) (658:658:658)) - (PORT datab (231:231:231) (286:286:286)) - (PORT datac (332:332:332) (357:357:357)) - (PORT datad (1201:1201:1201) (1156:1156:1156)) + (PORT dataa (574:574:574) (573:573:573)) + (PORT datab (1197:1197:1197) (1215:1215:1215)) + (PORT datac (674:674:674) (720:720:720)) + (PORT datad (570:570:570) (564:564:564)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (297:297:297) (394:394:394)) + (PORT datab (189:189:189) (224:224:224)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1326:1326:1326) (1345:1345:1345)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1368:1368:1368) (1348:1348:1348)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (628:628:628)) + (PORT datab (2569:2569:2569) (2664:2664:2664)) + (PORT datac (595:595:595) (614:614:614)) + (PORT datad (589:589:589) (620:620:620)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (327:327:327)) + (PORT datab (877:877:877) (917:917:917)) + (PORT datac (913:913:913) (955:955:955)) + (PORT datad (237:237:237) (304:304:304)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~2) + (DELAY + (ABSOLUTE + (PORT dataa (959:959:959) (1008:1008:1008)) + (PORT datac (240:240:240) (325:325:325)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (375:375:375)) + (PORT datac (831:831:831) (855:855:855)) + (PORT datad (185:185:185) (209:209:209)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1123:1123:1123) (1114:1114:1114)) + (PORT datac (642:642:642) (681:681:681)) + (PORT datad (573:573:573) (614:614:614)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~3) + (DELAY + (ABSOLUTE + (PORT dataa (720:720:720) (775:775:775)) + (PORT datab (313:313:313) (329:329:329)) + (PORT datad (179:179:179) (202:202:202)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|shifted) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1365:1365:1365) (1346:1346:1346)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~62) + (DELAY + (ABSOLUTE + (PORT datab (697:697:697) (758:758:758)) + (PORT datac (419:419:419) (476:476:476)) + (PORT datad (852:852:852) (871:871:871)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (963:963:963)) + (PORT datab (616:616:616) (651:651:651)) + (PORT datac (644:644:644) (682:682:682)) + (PORT datad (1077:1077:1077) (1068:1068:1068)) (IOPATH dataa combout (272:272:272) (269:269:269)) (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -30601,208 +31381,909 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~63) (DELAY (ABSOLUTE - (PORT datab (1888:1888:1888) (1933:1933:1933)) - (PORT datac (1051:1051:1051) (1079:1079:1079)) - (PORT datad (1052:1052:1052) (1086:1086:1086)) + (PORT dataa (915:915:915) (942:942:942)) + (PORT datab (695:695:695) (756:756:756)) + (PORT datac (645:645:645) (687:687:687)) + (PORT datad (895:895:895) (921:921:921)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (687:687:687) (749:749:749)) + (PORT datad (160:160:160) (180:180:180)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (234:234:234)) + (PORT datab (529:529:529) (516:516:516)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1326:1326:1326) (1345:1345:1345)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1369:1369:1369) (1349:1349:1349)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datad (1036:1036:1036) (1054:1054:1054)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (828:828:828) (846:846:846)) + (PORT sload (1103:1103:1103) (1144:1144:1144)) + (PORT ena (1325:1325:1325) (1316:1316:1316)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[15\]\~21) + (DELAY + (ABSOLUTE + (PORT datac (1553:1553:1553) (1654:1654:1654)) + (PORT datad (2417:2417:2417) (2527:2527:2527)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (217:217:217)) + (PORT datab (327:327:327) (335:335:335)) + (PORT datad (1036:1036:1036) (1050:1050:1050)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (854:854:854) (870:870:870)) + (PORT sload (1103:1103:1103) (1144:1144:1144)) + (PORT ena (1325:1325:1325) (1316:1316:1316)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[14\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (2233:2233:2233) (2387:2387:2387)) + (PORT datad (1538:1538:1538) (1577:1577:1577)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (1178:1178:1178) (1218:1218:1218)) + (PORT datac (654:654:654) (716:716:716)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (730:730:730) (791:791:791)) + (PORT datab (647:647:647) (679:679:679)) + (PORT datac (641:641:641) (683:683:683)) + (PORT datad (168:168:168) (194:194:194)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT datac (629:629:629) (670:670:670)) + (PORT datad (683:683:683) (747:747:747)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (672:672:672) (723:723:723)) + (PORT datab (1177:1177:1177) (1217:1217:1217)) + (PORT datac (654:654:654) (714:714:714)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (195:195:195) (230:230:230)) + (PORT datac (691:691:691) (764:764:764)) + (PORT datad (186:186:186) (213:213:213)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (268:268:268) (353:353:353)) + (PORT datac (781:781:781) (782:782:782)) + (PORT datad (657:657:657) (698:698:698)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (678:678:678)) + (PORT datac (908:908:908) (937:937:937)) + (PORT datad (606:606:606) (638:638:638)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (843:843:843) (832:832:832)) + (PORT datab (563:563:563) (571:571:571)) + (PORT datad (169:169:169) (194:194:194)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1351:1351:1351)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1367:1367:1367) (1349:1349:1349)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (636:636:636)) + (PORT datab (1362:1362:1362) (1339:1339:1339)) + (PORT datac (841:841:841) (844:844:844)) + (PORT datad (333:333:333) (373:373:373)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (200:200:200) (233:233:233)) + (PORT datad (1035:1035:1035) (1050:1050:1050)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (666:666:666) (711:711:711)) + (PORT sload (1103:1103:1103) (1144:1144:1144)) + (PORT ena (1325:1325:1325) (1316:1316:1316)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[12\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (1679:1679:1679) (1711:1711:1711)) + (PORT datac (2090:2090:2090) (2212:2212:2212)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (355:355:355)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datad (1039:1039:1039) (1054:1054:1054)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (678:678:678) (727:727:727)) + (PORT sload (1103:1103:1103) (1144:1144:1144)) + (PORT ena (1325:1325:1325) (1316:1316:1316)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (389:389:389)) + (PORT datab (709:709:709) (769:769:769)) + (PORT datac (642:642:642) (710:710:710)) + (PORT datad (325:325:325) (329:329:329)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~54) (DELAY (ABSOLUTE - (PORT d[0] (923:923:923) (927:927:927)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (930:930:930) (941:941:941)) - (PORT d[1] (1940:1940:1940) (2085:2085:2085)) - (PORT d[2] (3079:3079:3079) (3130:3130:3130)) - (PORT d[3] (2650:2650:2650) (2742:2742:2742)) - (PORT d[4] (2385:2385:2385) (2480:2480:2480)) - (PORT d[5] (2942:2942:2942) (3050:3050:3050)) - (PORT d[6] (1495:1495:1495) (1516:1516:1516)) - (PORT d[7] (2675:2675:2675) (2709:2709:2709)) - (PORT d[8] (950:950:950) (959:959:959)) - (PORT d[9] (2990:2990:2990) (3064:3064:3064)) - (PORT d[10] (1520:1520:1520) (1559:1559:1559)) - (PORT d[11] (1785:1785:1785) (1857:1857:1857)) - (PORT d[12] (1722:1722:1722) (1759:1759:1759)) - (PORT clk (1637:1637:1637) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (869:869:869) (834:834:834)) - (PORT clk (1637:1637:1637) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (PORT d[0] (1538:1538:1538) (1499:1499:1499)) + (PORT datab (392:392:392) (448:448:448)) + (PORT datac (675:675:675) (741:741:741)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~55) (DELAY (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1604:1604:1604) (1632:1632:1632)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (875:875:875) (879:879:879)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + (PORT dataa (193:193:193) (235:235:235)) + (PORT datab (716:716:716) (754:754:754)) + (PORT datad (162:162:162) (184:184:184)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) - (PORT asdata (1357:1357:1357) (1368:1368:1368)) + (PORT clk (1327:1327:1327) (1346:1346:1346)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1370:1370:1370) (1350:1350:1350)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~1) + (DELAY + (ABSOLUTE + (PORT datab (1823:1823:1823) (1920:1920:1920)) + (PORT datac (2093:2093:2093) (2212:2212:2212)) + (PORT datad (614:614:614) (639:639:639)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~127) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (885:885:885)) + (PORT datab (913:913:913) (946:946:946)) + (PORT datad (186:186:186) (211:211:211)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (986:986:986)) + (PORT datab (262:262:262) (338:338:338)) + (PORT datac (222:222:222) (295:295:295)) + (PORT datad (662:662:662) (702:702:702)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (285:285:285)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~128) + (DELAY + (ABSOLUTE + (PORT dataa (959:959:959) (1009:1009:1009)) + (PORT datab (878:878:878) (921:921:921)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (393:393:393)) + (PORT datab (579:579:579) (587:587:587)) + (PORT datad (735:735:735) (731:731:731)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1326:1326:1326) (1345:1345:1345)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1368:1368:1368) (1348:1348:1348)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (221:221:221)) + (PORT datab (208:208:208) (245:245:245)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (590:590:590) (613:613:613)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT datac (2343:2343:2343) (2477:2477:2477)) + (PORT datad (1094:1094:1094) (1146:1146:1146)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (733:733:733)) + (PORT datab (867:867:867) (899:899:899)) + (PORT datac (681:681:681) (744:744:744)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (853:853:853) (893:893:893)) + (PORT datab (670:670:670) (712:712:712)) + (PORT datac (642:642:642) (709:709:709)) + (PORT datad (330:330:330) (354:354:354)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (199:199:199) (237:237:237)) + (PORT datac (416:416:416) (485:485:485)) + (PORT datad (584:584:584) (579:579:579)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~46) + (DELAY + (ABSOLUTE + (PORT datab (463:463:463) (508:508:508)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1325:1325:1325) (1344:1344:1344)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1367:1367:1367) (1347:1347:1347)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (720:720:720)) + (PORT datad (681:681:681) (733:733:733)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (301:301:301) (399:399:399)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1326:1326:1326) (1345:1345:1345)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1368:1368:1368) (1348:1348:1348)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1091:1091:1091) (1120:1120:1120)) + (PORT datab (182:182:182) (213:213:213)) + (PORT datad (295:295:295) (301:301:301)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (676:676:676) (723:723:723)) + (PORT sload (1315:1315:1315) (1359:1359:1359)) + (PORT ena (1338:1338:1338) (1327:1327:1327)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (2136:2136:2136) (2272:2272:2272)) + (PORT datad (1320:1320:1320) (1368:1368:1368)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1092:1092:1092) (1119:1119:1119)) + (PORT datab (202:202:202) (236:236:236)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) - (PORT asdata (641:641:641) (686:686:686)) + (PORT clk (1349:1349:1349) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (667:667:667) (705:705:705)) + (PORT sload (1315:1315:1315) (1359:1359:1359)) + (PORT ena (1338:1338:1338) (1327:1327:1327)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (862:862:862) (919:919:919)) + (PORT datad (2208:2208:2208) (2347:2347:2347)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (685:685:685)) + (PORT datab (621:621:621) (661:661:661)) + (PORT datac (616:616:616) (640:640:640)) + (PORT datad (1379:1379:1379) (1422:1422:1422)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (2189:2189:2189) (2317:2317:2317)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1360:1360:1360)) + (PORT asdata (515:515:515) (584:584:584)) + (PORT clrn (1403:1403:1403) (1369:1369:1369)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) (TIMINGCHECK (HOLD asdata (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (211:211:211) (272:272:272)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1366:1366:1366)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1403:1403:1403) (1369:1369:1369)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|control_pins_\|pin_nIORQ\~1) + (DELAY + (ABSOLUTE + (PORT dataa (819:819:819) (806:806:806)) + (PORT datab (225:225:225) (297:297:297)) + (PORT datac (917:917:917) (930:930:930)) + (PORT datad (210:210:210) (270:270:270)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2429:2429:2429) (2458:2458:2458)) + (PORT datab (1787:1787:1787) (1868:1868:1868)) + (PORT datac (2566:2566:2566) (2669:2669:2669)) + (PORT datad (2051:2051:2051) (2020:2020:2020)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[13\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (1825:1825:1825) (1924:1924:1924)) + (PORT datac (2092:2092:2092) (2210:2210:2210)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ExtRamWE\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2429:2429:2429) (2462:2462:2462)) + (PORT datab (1785:1785:1785) (1869:1869:1869)) + (PORT datac (2568:2568:2568) (2669:2669:2669)) + (PORT datad (2053:2053:2053) (2023:2023:2023)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (631:631:631) (658:658:658)) - (PORT datab (234:234:234) (289:289:289)) - (PORT datac (334:334:334) (358:358:358)) - (PORT datad (1201:1201:1201) (1153:1153:1153)) + (PORT dataa (385:385:385) (415:415:415)) + (PORT datab (1157:1157:1157) (1168:1168:1168)) + (PORT datac (1135:1135:1135) (1143:1143:1143)) + (PORT datad (1288:1288:1288) (1263:1263:1263)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -30815,21 +32296,2740 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) (DELAY (ABSOLUTE - (PORT datab (1882:1882:1882) (1925:1925:1925)) - (PORT datac (1050:1050:1050) (1074:1074:1074)) - (PORT datad (1050:1050:1050) (1082:1082:1082)) - (IOPATH datab combout (273:273:273) (275:275:275)) + (PORT dataa (1783:1783:1783) (1908:1908:1908)) + (PORT datac (1831:1831:1831) (1936:1936:1936)) + (PORT datad (1320:1320:1320) (1359:1359:1359)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (227:227:227)) + (PORT datab (576:576:576) (559:559:559)) + (PORT datad (839:839:839) (839:839:839)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (915:915:915) (941:941:941)) + (PORT sload (1102:1102:1102) (1143:1143:1143)) + (PORT ena (1118:1118:1118) (1108:1108:1108)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (2234:2234:2234) (2386:2386:2386)) + (PORT datac (1001:1001:1001) (1001:1001:1001)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (1573:1573:1573) (1572:1572:1572)) + (PORT datad (305:305:305) (311:311:311)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1361:1361:1361) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (862:862:862) (893:893:893)) + (PORT sload (1505:1505:1505) (1525:1525:1525)) + (PORT ena (1340:1340:1340) (1296:1296:1296)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1092:1092:1092) (1078:1078:1078)) + (PORT datad (2208:2208:2208) (2347:2347:2347)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (793:793:793) (807:807:807)) + (PORT datab (1587:1587:1587) (1606:1606:1606)) + (PORT datad (814:814:814) (809:809:809)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (1166:1166:1166) (1198:1198:1198)) + (PORT sload (1258:1258:1258) (1265:1265:1265)) + (PORT ena (1296:1296:1296) (1261:1261:1261)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (240:240:240) (309:309:309)) + (PORT datad (2202:2202:2202) (2341:2341:2341)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (240:240:240)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datad (1536:1536:1536) (1535:1535:1535)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1361:1361:1361) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (833:833:833) (855:855:855)) + (PORT sload (1505:1505:1505) (1525:1525:1525)) + (PORT ena (1340:1340:1340) (1296:1296:1296)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (256:256:256) (326:326:326)) + (PORT datad (347:347:347) (390:390:390)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (1573:1573:1573) (1568:1568:1568)) + (PORT datad (178:178:178) (199:199:199)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1361:1361:1361) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (873:873:873) (894:894:894)) + (PORT sload (1505:1505:1505) (1525:1525:1525)) + (PORT ena (1340:1340:1340) (1296:1296:1296)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) + (DELAY + (ABSOLUTE + (PORT datac (1143:1143:1143) (1205:1205:1205)) + (PORT datad (2199:2199:2199) (2335:2335:2335)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (508:508:508) (500:500:500)) + (PORT datab (1571:1571:1571) (1568:1568:1568)) + (PORT datad (296:296:296) (292:292:292)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1361:1361:1361) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (531:531:531) (596:596:596)) + (PORT sload (1505:1505:1505) (1525:1525:1525)) + (PORT ena (1340:1340:1340) (1296:1296:1296)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) + (DELAY + (ABSOLUTE + (PORT datac (1398:1398:1398) (1414:1414:1414)) + (PORT datad (2204:2204:2204) (2340:2340:2340)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1001:1001:1001) (977:977:977)) + (PORT datab (842:842:842) (840:840:840)) + (PORT datad (1563:1563:1563) (1573:1573:1573)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (1170:1170:1170) (1213:1213:1213)) + (PORT sload (1258:1258:1258) (1265:1265:1265)) + (PORT ena (1296:1296:1296) (1261:1261:1261)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (2232:2232:2232) (2381:2381:2381)) + (PORT datac (220:220:220) (290:290:290)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1232:1232:1232) (1255:1255:1255)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2192:2192:2192) (2312:2312:2312)) + (PORT d[1] (2398:2398:2398) (2408:2408:2408)) + (PORT d[2] (1747:1747:1747) (1768:1768:1768)) + (PORT d[3] (1173:1173:1173) (1196:1196:1196)) + (PORT d[4] (2105:2105:2105) (2108:2108:2108)) + (PORT d[5] (1192:1192:1192) (1219:1219:1219)) + (PORT d[6] (1349:1349:1349) (1338:1338:1338)) + (PORT d[7] (2178:2178:2178) (2237:2237:2237)) + (PORT d[8] (2072:2072:2072) (2150:2150:2150)) + (PORT d[9] (969:969:969) (998:998:998)) + (PORT d[10] (947:947:947) (967:967:967)) + (PORT d[11] (1341:1341:1341) (1349:1349:1349)) + (PORT d[12] (699:699:699) (736:736:736)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1633:1633:1633) (1597:1597:1597)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1662:1662:1662)) + (PORT d[0] (1654:1654:1654) (1616:1616:1616)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1626:1626:1626)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1669:1669:1669) (1690:1690:1690)) + (PORT asdata (1855:1855:1855) (1863:1863:1863)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (1630:1630:1630) (1612:1612:1612)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (914:914:914)) + (PORT datab (830:830:830) (834:834:834)) + (PORT datac (1053:1053:1053) (1064:1064:1064)) + (PORT datad (883:883:883) (917:917:917)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1781:1781:1781) (1907:1907:1907)) + (PORT datac (1830:1830:1830) (1939:1939:1939)) + (PORT datad (1316:1316:1316) (1358:1358:1358)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1403:1403:1403) (1398:1398:1398)) + (PORT clk (1634:1634:1634) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1803:1803:1803) (1874:1874:1874)) + (PORT d[1] (2314:2314:2314) (2291:2291:2291)) + (PORT d[2] (2392:2392:2392) (2484:2484:2484)) + (PORT d[3] (1058:1058:1058) (1063:1063:1063)) + (PORT d[4] (2244:2244:2244) (2302:2302:2302)) + (PORT d[5] (2929:2929:2929) (2934:2934:2934)) + (PORT d[6] (2024:2024:2024) (2037:2037:2037)) + (PORT d[7] (1714:1714:1714) (1678:1678:1678)) + (PORT d[8] (2325:2325:2325) (2386:2386:2386)) + (PORT d[9] (1569:1569:1569) (1548:1548:1548)) + (PORT d[10] (2321:2321:2321) (2324:2324:2324)) + (PORT d[11] (3718:3718:3718) (3857:3857:3857)) + (PORT d[12] (2324:2324:2324) (2328:2328:2328)) + (PORT clk (1631:1631:1631) (1661:1661:1661)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1836:1836:1836) (1776:1776:1776)) + (PORT clk (1631:1631:1631) (1661:1661:1661)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1663:1663:1663)) + (PORT d[0] (1991:1991:1991) (1922:1922:1922)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1627:1627:1627)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (415:415:415)) + (PORT datab (1157:1157:1157) (1174:1174:1174)) + (PORT datac (1135:1135:1135) (1147:1147:1147)) + (PORT datad (1288:1288:1288) (1267:1267:1267)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1782:1782:1782) (1907:1907:1907)) + (PORT datac (1830:1830:1830) (1934:1934:1934)) + (PORT datad (1320:1320:1320) (1355:1355:1355)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (798:798:798) (778:778:778)) + (PORT clk (1646:1646:1646) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2702:2702:2702) (2810:2810:2810)) + (PORT d[1] (3071:3071:3071) (3143:3143:3143)) + (PORT d[2] (1388:1388:1388) (1408:1408:1408)) + (PORT d[3] (3663:3663:3663) (3710:3710:3710)) + (PORT d[4] (2688:2688:2688) (2785:2785:2785)) + (PORT d[5] (4080:4080:4080) (4141:4141:4141)) + (PORT d[6] (2045:2045:2045) (2040:2040:2040)) + (PORT d[7] (3688:3688:3688) (3683:3683:3683)) + (PORT d[8] (1409:1409:1409) (1424:1424:1424)) + (PORT d[9] (1966:1966:1966) (2004:2004:2004)) + (PORT d[10] (2120:2120:2120) (2114:2114:2114)) + (PORT d[11] (2915:2915:2915) (3018:3018:3018)) + (PORT d[12] (3812:3812:3812) (3918:3918:3918)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1774:1774:1774) (1701:1701:1701)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1672:1672:1672)) + (PORT d[0] (2479:2479:2479) (2455:2455:2455)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (1366:1366:1366) (1386:1386:1386)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (867:867:867) (886:886:886)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (420:420:420)) + (PORT datab (1152:1152:1152) (1167:1167:1167)) + (PORT datac (1134:1134:1134) (1146:1146:1146)) + (PORT datad (1287:1287:1287) (1261:1261:1261)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1778:1778:1778) (1903:1903:1903)) + (PORT datac (1832:1832:1832) (1935:1935:1935)) + (PORT datad (1314:1314:1314) (1353:1353:1353)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1219:1219:1219) (1239:1239:1239)) + (PORT clk (1637:1637:1637) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1968:1968:1968) (2075:2075:2075)) + (PORT d[1] (2097:2097:2097) (2114:2114:2114)) + (PORT d[2] (1482:1482:1482) (1499:1499:1499)) + (PORT d[3] (2317:2317:2317) (2327:2327:2327)) + (PORT d[4] (2131:2131:2131) (2125:2125:2125)) + (PORT d[5] (1457:1457:1457) (1474:1474:1474)) + (PORT d[6] (1593:1593:1593) (1587:1587:1587)) + (PORT d[7] (2052:2052:2052) (2057:2057:2057)) + (PORT d[8] (2295:2295:2295) (2395:2395:2395)) + (PORT d[9] (985:985:985) (1023:1023:1023)) + (PORT d[10] (1599:1599:1599) (1617:1617:1617)) + (PORT d[11] (1329:1329:1329) (1327:1327:1327)) + (PORT d[12] (941:941:941) (980:980:980)) + (PORT clk (1634:1634:1634) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1388:1388:1388) (1367:1367:1367)) + (PORT clk (1634:1634:1634) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1665:1665:1665)) + (PORT d[0] (1831:1831:1831) (1775:1775:1775)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1601:1601:1601) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (1019:1019:1019) (982:982:982)) + (PORT datab (1419:1419:1419) (1416:1416:1416)) + (PORT datac (1306:1306:1306) (1318:1318:1318)) + (PORT datad (1373:1373:1373) (1371:1371:1371)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1200:1200:1200) (1220:1220:1220)) + (PORT datab (1691:1691:1691) (1773:1773:1773)) + (PORT datac (1544:1544:1544) (1537:1537:1537)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (416:416:416)) + (PORT datab (1150:1150:1150) (1167:1167:1167)) + (PORT datac (1134:1134:1134) (1142:1142:1142)) + (PORT datad (1282:1282:1282) (1261:1261:1261)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE CLOCK_50\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (133:133:133) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\~0) + (DELAY + (ABSOLUTE + (PORT dataa (415:415:415) (486:486:486)) + (PORT datab (895:895:895) (920:920:920)) + (PORT datac (642:642:642) (681:681:681)) + (PORT datad (684:684:684) (714:714:714)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1359:1359:1359) (1376:1376:1376)) + (PORT asdata (913:913:913) (935:935:935)) + (PORT ena (740:740:740) (743:743:743)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (812:812:812) (826:826:826)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1359:1359:1359) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (740:740:740) (743:743:743)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT datac (829:829:829) (853:853:853)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1359:1359:1359) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (740:740:740) (743:743:743)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~0) + (DELAY + (ABSOLUTE + (PORT datac (833:833:833) (858:858:858)) + (PORT datad (816:816:816) (835:835:835)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1359:1359:1359) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (740:740:740) (743:743:743)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (893:893:893)) + (PORT datab (844:844:844) (870:870:870)) + (PORT datad (813:813:813) (824:824:824)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1359:1359:1359) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (740:740:740) (743:743:743)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1174:1174:1174) (1213:1213:1213)) + (PORT datab (586:586:586) (609:609:609)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (687:687:687) (719:719:719)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~4) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (668:668:668)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~6) + (DELAY + (ABSOLUTE + (PORT datab (878:878:878) (871:871:871)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1359:1359:1359) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (864:864:864) (845:845:845)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~8) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (901:901:901)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1359:1359:1359) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (864:864:864) (845:845:845)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~10) + (DELAY + (ABSOLUTE + (PORT datab (875:875:875) (902:902:902)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1359:1359:1359) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (864:864:864) (845:845:845)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~12) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (700:700:700)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (905:905:905)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (166:166:166) (188:188:188)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[8\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (416:416:416) (486:486:486)) + (PORT datab (893:893:893) (916:916:916)) + (PORT datac (643:643:643) (682:682:682)) + (PORT datad (682:682:682) (711:711:711)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1359:1359:1359) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (899:899:899) (893:893:893)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1037:1037:1037) (1046:1046:1046)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH cin combout (408:408:408) (387:387:387)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (899:899:899)) + (PORT datac (163:163:163) (197:197:197)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1359:1359:1359) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (899:899:899) (893:893:893)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (416:416:416) (487:487:487)) + (PORT datab (901:901:901) (926:926:926)) + (PORT datac (637:637:637) (676:676:676)) + (PORT datad (687:687:687) (718:718:718)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (332:332:332)) + (PORT datab (354:354:354) (357:357:357)) + (PORT datad (686:686:686) (719:719:719)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1359:1359:1359) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT datac (838:838:838) (869:869:869)) + (PORT datad (166:166:166) (188:188:188)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1359:1359:1359) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (899:899:899) (893:893:893)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (872:872:872) (898:898:898)) + (PORT datac (165:165:165) (199:199:199)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1359:1359:1359) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (899:899:899) (893:893:893)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1189:1189:1189) (1207:1207:1207)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2600:2600:2600) (2662:2662:2662)) + (PORT d[1] (2747:2747:2747) (2782:2782:2782)) + (PORT d[2] (1792:1792:1792) (1855:1855:1855)) + (PORT d[3] (2004:2004:2004) (2045:2045:2045)) + (PORT d[4] (1916:1916:1916) (1963:1963:1963)) + (PORT d[5] (1727:1727:1727) (1774:1774:1774)) + (PORT d[6] (2147:2147:2147) (2209:2209:2209)) + (PORT d[7] (1761:1761:1761) (1785:1785:1785)) + (PORT d[8] (2953:2953:2953) (2996:2996:2996)) + (PORT d[9] (1855:1855:1855) (1943:1943:1943)) + (PORT d[10] (3321:3321:3321) (3370:3370:3370)) + (PORT d[11] (2216:2216:2216) (2269:2269:2269)) + (PORT d[12] (1822:1822:1822) (1911:1911:1911)) + (PORT clk (1638:1638:1638) (1667:1667:1667)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1643:1643:1643) (1624:1624:1624)) + (PORT clk (1638:1638:1638) (1667:1667:1667)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (PORT d[0] (2934:2934:2934) (2920:2920:2920)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1600:1600:1600) (1599:1599:1599)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1725:1725:1725) (1737:1737:1737)) + (PORT clk (1608:1608:1608) (1606:1606:1606)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4163:4163:4163) (4138:4138:4138)) + (PORT d[1] (4073:4073:4073) (4107:4107:4107)) + (PORT d[2] (4223:4223:4223) (4111:4111:4111)) + (PORT d[3] (3967:3967:3967) (3949:3949:3949)) + (PORT d[4] (4067:4067:4067) (4010:4010:4010)) + (PORT d[5] (4104:4104:4104) (4095:4095:4095)) + (PORT d[6] (4094:4094:4094) (4038:4038:4038)) + (PORT d[7] (4079:4079:4079) (4065:4065:4065)) + (PORT d[8] (4307:4307:4307) (4239:4239:4239)) + (PORT d[9] (4112:4112:4112) (4038:4038:4038)) + (PORT d[10] (4146:4146:4146) (4023:4023:4023)) + (PORT d[11] (4101:4101:4101) (4053:4053:4053)) + (PORT d[12] (4079:4079:4079) (3997:3997:3997)) + (PORT clk (1605:1605:1605) (1603:1603:1603)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1606:1606:1606)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1607:1607:1607)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1607:1607:1607)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1607:1607:1607)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1607:1607:1607)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1601:1601:1601) (1600:1600:1600)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1334:1334:1334) (1342:1342:1342)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (199:199:199) (257:257:257)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1078:1078:1078) (1104:1104:1104)) + (PORT datab (1171:1171:1171) (1178:1178:1178)) + (PORT datac (1323:1323:1323) (1348:1348:1348)) + (PORT datad (1044:1044:1044) (1067:1067:1067)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1133:1133:1133) (1102:1102:1102)) + (PORT clk (1631:1631:1631) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2873:2873:2873) (2947:2947:2947)) + (PORT d[1] (1964:1964:1964) (1976:1976:1976)) + (PORT d[2] (1509:1509:1509) (1557:1557:1557)) + (PORT d[3] (1427:1427:1427) (1466:1466:1466)) + (PORT d[4] (2472:2472:2472) (2528:2528:2528)) + (PORT d[5] (1455:1455:1455) (1490:1490:1490)) + (PORT d[6] (1877:1877:1877) (1920:1920:1920)) + (PORT d[7] (1746:1746:1746) (1757:1757:1757)) + (PORT d[8] (3214:3214:3214) (3263:3263:3263)) + (PORT d[9] (1565:1565:1565) (1638:1638:1638)) + (PORT d[10] (1519:1519:1519) (1575:1575:1575)) + (PORT d[11] (1502:1502:1502) (1531:1531:1531)) + (PORT d[12] (1545:1545:1545) (1620:1620:1620)) + (PORT clk (1628:1628:1628) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1317:1317:1317) (1261:1261:1261)) + (PORT clk (1628:1628:1628) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1660:1660:1660)) + (PORT d[0] (2636:2636:2636) (2629:2629:2629)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1590:1590:1590) (1590:1590:1590)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1413:1413:1413) (1413:1413:1413)) + (PORT clk (1598:1598:1598) (1597:1597:1597)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4124:4124:4124) (4083:4083:4083)) + (PORT d[1] (4040:4040:4040) (3991:3991:3991)) + (PORT d[2] (4097:4097:4097) (4011:4011:4011)) + (PORT d[3] (3978:3978:3978) (3952:3952:3952)) + (PORT d[4] (4021:4021:4021) (3977:3977:3977)) + (PORT d[5] (4067:4067:4067) (4036:4036:4036)) + (PORT d[6] (4095:4095:4095) (3949:3949:3949)) + (PORT d[7] (4043:4043:4043) (4028:4028:4028)) + (PORT d[8] (4124:4124:4124) (4102:4102:4102)) + (PORT d[9] (4148:4148:4148) (4090:4090:4090)) + (PORT d[10] (4151:4151:4151) (4113:4113:4113)) + (PORT d[11] (4142:4142:4142) (4089:4089:4089)) + (PORT d[12] (4083:4083:4083) (3991:3991:3991)) + (PORT clk (1595:1595:1595) (1594:1594:1594)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1597:1597:1597)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1598:1598:1598)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1598:1598:1598)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1598:1598:1598)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1598:1598:1598)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2949:2949:2949) (3064:3064:3064)) + (PORT d[1] (3077:3077:3077) (3150:3150:3150)) + (PORT d[2] (1328:1328:1328) (1346:1346:1346)) + (PORT d[3] (3633:3633:3633) (3669:3669:3669)) + (PORT d[4] (2708:2708:2708) (2805:2805:2805)) + (PORT d[5] (4075:4075:4075) (4133:4133:4133)) + (PORT d[6] (2581:2581:2581) (2586:2586:2586)) + (PORT d[7] (1601:1601:1601) (1613:1613:1613)) + (PORT d[8] (1832:1832:1832) (1833:1833:1833)) + (PORT d[9] (1977:1977:1977) (2013:2013:2013)) + (PORT d[10] (2129:2129:2129) (2133:2133:2133)) + (PORT d[11] (2878:2878:2878) (2980:2980:2980)) + (PORT d[12] (3945:3945:3945) (4038:4038:4038)) + (PORT clk (1642:1642:1642) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1670:1670:1670)) + (PORT d[0] (1781:1781:1781) (1761:1761:1761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (855:855:855) (900:900:900)) + (PORT datab (273:273:273) (354:354:354)) + (PORT datac (825:825:825) (829:829:829)) + (PORT datad (982:982:982) (946:946:946)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1813:1813:1813) (1837:1837:1837)) + (PORT d[1] (2372:2372:2372) (2409:2409:2409)) + (PORT d[2] (2184:2184:2184) (2246:2246:2246)) + (PORT d[3] (2777:2777:2777) (2778:2778:2778)) + (PORT d[4] (2118:2118:2118) (2144:2144:2144)) + (PORT d[5] (2861:2861:2861) (2865:2865:2865)) + (PORT d[6] (2623:2623:2623) (2631:2631:2631)) + (PORT d[7] (2917:2917:2917) (2919:2919:2919)) + (PORT d[8] (2209:2209:2209) (2233:2233:2233)) + (PORT d[9] (2806:2806:2806) (2873:2873:2873)) + (PORT d[10] (2112:2112:2112) (2110:2110:2110)) + (PORT d[11] (2306:2306:2306) (2369:2369:2369)) + (PORT d[12] (2976:2976:2976) (3046:3046:3046)) + (PORT clk (1654:1654:1654) (1681:1681:1681)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1681:1681:1681)) + (PORT d[0] (2654:2654:2654) (2639:2639:2639)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1682:1682:1682)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1621:1621:1621) (1647:1647:1647)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (892:892:892) (894:894:894)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (893:893:893) (895:895:895)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (893:893:893) (895:895:895)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (893:893:893) (895:895:895)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (1019:1019:1019) (980:980:980)) + (PORT datab (1353:1353:1353) (1375:1375:1375)) + (PORT datac (161:161:161) (194:194:194)) + (PORT datad (1573:1573:1573) (1550:1550:1550)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1078:1078:1078) (1087:1087:1087)) + (PORT datab (275:275:275) (357:357:357)) + (PORT datac (162:162:162) (196:196:196)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~119) + (DELAY + (ABSOLUTE + (PORT dataa (1310:1310:1310) (1329:1329:1329)) + (PORT datab (2124:2124:2124) (2266:2266:2266)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1140:1140:1140) (1182:1182:1182)) + (PORT datab (577:577:577) (594:594:594)) + (PORT datac (783:783:783) (787:787:787)) + (PORT datad (307:307:307) (310:310:310)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (2029:2029:2029) (2017:2017:2017)) + (PORT datab (579:579:579) (595:595:595)) + (PORT datac (1572:1572:1572) (1603:1603:1603)) + (PORT datad (177:177:177) (198:198:198)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (238:238:238)) + (PORT datab (1326:1326:1326) (1317:1317:1317)) + (PORT datac (1018:1018:1018) (1002:1002:1002)) + (PORT datad (321:321:321) (326:326:326)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1056:1056:1056) (1025:1025:1025)) + (PORT datab (1374:1374:1374) (1418:1418:1418)) + (PORT datac (1950:1950:1950) (2012:2012:2012)) + (PORT datad (1524:1524:1524) (1636:1636:1636)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) + (DELAY + (ABSOLUTE + (PORT dataa (1569:1569:1569) (1598:1598:1598)) + (PORT datab (501:501:501) (498:498:498)) + (PORT datac (939:939:939) (914:914:914)) + (PORT datad (1042:1042:1042) (1029:1029:1029)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1064:1064:1064) (1031:1031:1031)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1049:1049:1049) (1039:1039:1039)) + (PORT datab (218:218:218) (259:259:259)) + (PORT datac (785:785:785) (760:760:760)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (229:229:229)) + (PORT datac (1018:1018:1018) (999:999:999)) + (PORT datad (200:200:200) (236:236:236)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (414:414:414)) + (PORT datab (227:227:227) (273:273:273)) + (PORT datac (313:313:313) (323:323:323)) + (PORT datad (199:199:199) (229:229:229)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|ir_\|opcode\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (570:570:570) (564:564:564)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1070:1070:1070) (1068:1068:1068)) + (PORT datab (2698:2698:2698) (2666:2666:2666)) + (PORT datac (1267:1267:1267) (1301:1301:1301)) + (PORT datad (734:734:734) (763:763:763)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1375:1375:1375)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1412:1412:1412) (1378:1378:1378)) + (PORT ena (2056:2056:2056) (1990:1990:1990)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1709:1709:1709) (1764:1764:1764)) + (PORT datab (1513:1513:1513) (1636:1636:1636)) + (PORT datac (1578:1578:1578) (1615:1615:1615)) + (PORT datad (807:807:807) (804:804:804)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (627:627:627)) + (PORT datab (780:780:780) (778:778:778)) + (PORT datac (325:325:325) (335:335:335)) + (PORT datad (565:565:565) (559:559:559)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (861:861:861)) + (PORT datab (1089:1089:1089) (1091:1091:1091)) + (PORT datac (1056:1056:1056) (1057:1057:1057)) + (PORT datad (1077:1077:1077) (1083:1083:1083)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (336:336:336)) + (PORT datab (199:199:199) (232:232:232)) + (PORT datac (796:796:796) (813:813:813)) + (PORT datad (197:197:197) (228:228:228)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (798:798:798)) + (PORT datac (744:744:744) (747:747:747)) + (PORT datad (765:765:765) (742:742:742)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (836:836:836)) + (PORT datab (838:838:838) (820:820:820)) + (PORT datac (739:739:739) (727:727:727)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (554:554:554) (561:561:561)) + (PORT datab (1075:1075:1075) (1072:1072:1072)) + (PORT datac (835:835:835) (845:845:845)) + (PORT datad (542:542:542) (540:540:540)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (217:217:217)) + (PORT datab (1244:1244:1244) (1216:1216:1216)) + (PORT datac (584:584:584) (589:589:589)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[6\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (776:776:776) (784:784:784)) + (PORT datab (625:625:625) (644:644:644)) + (PORT datac (773:773:773) (773:773:773)) + (PORT datad (768:768:768) (745:745:745)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (764:764:764) (760:760:760)) + (PORT datac (330:330:330) (336:336:336)) + (PORT datad (786:786:786) (771:771:771)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (847:847:847)) + (PORT datab (590:590:590) (601:601:601)) + (PORT datac (158:158:158) (190:190:190)) + (PORT datad (548:548:548) (542:542:542)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1046:1046:1046) (1032:1032:1032)) + (PORT datab (220:220:220) (262:262:262)) + (PORT datad (1100:1100:1100) (1096:1096:1096)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1107:1107:1107) (1120:1120:1120)) + (PORT d[0] (1219:1219:1219) (1236:1236:1236)) (PORT clk (1632:1632:1632) (1660:1660:1660)) ) ) @@ -30842,19 +35042,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3685:3685:3685) (3782:3782:3782)) - (PORT d[1] (1575:1575:1575) (1658:1658:1658)) - (PORT d[2] (3077:3077:3077) (3135:3135:3135)) - (PORT d[3] (1984:1984:1984) (2041:2041:2041)) - (PORT d[4] (1991:1991:1991) (2039:2039:2039)) - (PORT d[5] (1534:1534:1534) (1598:1598:1598)) - (PORT d[6] (1634:1634:1634) (1654:1654:1654)) - (PORT d[7] (2839:2839:2839) (2868:2868:2868)) - (PORT d[8] (3080:3080:3080) (3193:3193:3193)) - (PORT d[9] (1627:1627:1627) (1656:1656:1656)) - (PORT d[10] (2978:2978:2978) (3070:3070:3070)) - (PORT d[11] (1943:1943:1943) (1980:1980:1980)) - (PORT d[12] (1645:1645:1645) (1683:1683:1683)) + (PORT d[0] (2225:2225:2225) (2347:2347:2347)) + (PORT d[1] (2419:2419:2419) (2429:2429:2429)) + (PORT d[2] (1155:1155:1155) (1173:1173:1173)) + (PORT d[3] (1173:1173:1173) (1184:1184:1184)) + (PORT d[4] (1878:1878:1878) (1878:1878:1878)) + (PORT d[5] (1162:1162:1162) (1183:1183:1183)) + (PORT d[6] (1374:1374:1374) (1357:1357:1357)) + (PORT d[7] (2179:2179:2179) (2238:2238:2238)) + (PORT d[8] (2314:2314:2314) (2411:2411:2411)) + (PORT d[9] (716:716:716) (757:757:757)) + (PORT d[10] (1619:1619:1619) (1643:1643:1643)) + (PORT d[11] (1101:1101:1101) (1107:1107:1107)) + (PORT d[12] (673:673:673) (706:706:706)) (PORT clk (1629:1629:1629) (1658:1658:1658)) ) ) @@ -30867,7 +35067,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2067:2067:2067) (2031:2031:2031)) + (PORT d[0] (1648:1648:1648) (1601:1601:1601)) (PORT clk (1629:1629:1629) (1658:1658:1658)) ) ) @@ -30881,7 +35081,7 @@ (DELAY (ABSOLUTE (PORT clk (1632:1632:1632) (1660:1660:1660)) - (PORT d[0] (2694:2694:2694) (2699:2699:2699)) + (PORT d[0] (1654:1654:1654) (1615:1615:1615)) ) ) ) @@ -30978,48 +35178,308 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~90) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (565:565:565) (548:548:548)) - (PORT datab (896:896:896) (943:943:943)) - (PORT datac (772:772:772) (757:757:757)) - (PORT datad (1051:1051:1051) (1082:1082:1082)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT d[0] (898:898:898) (896:896:896)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2259:2259:2259) (2374:2374:2374)) + (PORT d[1] (1158:1158:1158) (1167:1167:1167)) + (PORT d[2] (1537:1537:1537) (1570:1570:1570)) + (PORT d[3] (1478:1478:1478) (1518:1518:1518)) + (PORT d[4] (2760:2760:2760) (2842:2842:2842)) + (PORT d[5] (1170:1170:1170) (1191:1191:1191)) + (PORT d[6] (1442:1442:1442) (1483:1483:1483)) + (PORT d[7] (1199:1199:1199) (1208:1208:1208)) + (PORT d[8] (1163:1163:1163) (1180:1180:1180)) + (PORT d[9] (995:995:995) (1054:1054:1054)) + (PORT d[10] (989:989:989) (1043:1043:1043)) + (PORT d[11] (2058:2058:2058) (2128:2128:2128)) + (PORT d[12] (1004:1004:1004) (1063:1063:1063)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1121:1121:1121) (1058:1058:1058)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (PORT d[0] (2116:2116:2116) (2080:2080:2080)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) (DELAY (ABSOLUTE - (PORT dataa (630:630:630) (663:663:663)) - (PORT datab (233:233:233) (288:288:288)) - (PORT datac (334:334:334) (361:361:361)) - (PORT datad (1200:1200:1200) (1155:1155:1155)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) (DELAY (ABSOLUTE - (PORT datab (1891:1891:1891) (1933:1933:1933)) - (PORT datac (1053:1053:1053) (1077:1077:1077)) - (PORT datad (1055:1055:1055) (1083:1083:1083)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1218:1218:1218) (1229:1229:1229)) + (PORT clk (1626:1626:1626) (1655:1655:1655)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2502:2502:2502) (2623:2623:2623)) + (PORT d[1] (2673:2673:2673) (2693:2693:2693)) + (PORT d[2] (1145:1145:1145) (1155:1155:1155)) + (PORT d[3] (910:910:910) (929:929:929)) + (PORT d[4] (1906:1906:1906) (1916:1916:1916)) + (PORT d[5] (882:882:882) (894:894:894)) + (PORT d[6] (1337:1337:1337) (1316:1316:1316)) + (PORT d[7] (2449:2449:2449) (2517:2517:2517)) + (PORT d[8] (2328:2328:2328) (2435:2435:2435)) + (PORT d[9] (685:685:685) (720:720:720)) + (PORT d[10] (698:698:698) (734:734:734)) + (PORT d[11] (2617:2617:2617) (2715:2715:2715)) + (PORT d[12] (659:659:659) (681:681:681)) + (PORT clk (1623:1623:1623) (1653:1653:1653)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1137:1137:1137) (1091:1091:1091)) + (PORT clk (1623:1623:1623) (1653:1653:1653)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1626:1626:1626) (1655:1655:1655)) + (PORT d[0] (1310:1310:1310) (1264:1264:1264)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1627:1627:1627) (1656:1656:1656)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1627:1627:1627) (1656:1656:1656)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1627:1627:1627) (1656:1656:1656)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1627:1627:1627) (1656:1656:1656)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1590:1590:1590) (1619:1619:1619)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (861:861:861) (866:866:866)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (862:862:862) (867:867:867)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (862:862:862) (867:867:867)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (862:862:862) (867:867:867)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) @@ -31028,8 +35488,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1113:1113:1113) (1106:1106:1106)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) + (PORT d[0] (635:635:635) (633:633:633)) + (PORT clk (1638:1638:1638) (1664:1664:1664)) ) ) (TIMINGCHECK @@ -31041,20 +35501,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3904:3904:3904) (3985:3985:3985)) - (PORT d[1] (2171:2171:2171) (2294:2294:2294)) - (PORT d[2] (2971:2971:2971) (2995:2995:2995)) - (PORT d[3] (2388:2388:2388) (2476:2476:2476)) - (PORT d[4] (2373:2373:2373) (2471:2471:2471)) - (PORT d[5] (2627:2627:2627) (2712:2712:2712)) - (PORT d[6] (1769:1769:1769) (1832:1832:1832)) - (PORT d[7] (2401:2401:2401) (2428:2428:2428)) - (PORT d[8] (3102:3102:3102) (3241:3241:3241)) - (PORT d[9] (2698:2698:2698) (2767:2767:2767)) - (PORT d[10] (4706:4706:4706) (4798:4798:4798)) - (PORT d[11] (1774:1774:1774) (1826:1826:1826)) - (PORT d[12] (1997:1997:1997) (2046:2046:2046)) - (PORT clk (1637:1637:1637) (1666:1666:1666)) + (PORT d[0] (2482:2482:2482) (2610:2610:2610)) + (PORT d[1] (1202:1202:1202) (1220:1220:1220)) + (PORT d[2] (1538:1538:1538) (1560:1560:1560)) + (PORT d[3] (1448:1448:1448) (1471:1471:1471)) + (PORT d[4] (2753:2753:2753) (2824:2824:2824)) + (PORT d[5] (1176:1176:1176) (1199:1199:1199)) + (PORT d[6] (1395:1395:1395) (1434:1434:1434)) + (PORT d[7] (1496:1496:1496) (1508:1508:1508)) + (PORT d[8] (1437:1437:1437) (1483:1483:1483)) + (PORT d[9] (1272:1272:1272) (1330:1330:1330)) + (PORT d[10] (1231:1231:1231) (1281:1281:1281)) + (PORT d[11] (1749:1749:1749) (1808:1808:1808)) + (PORT d[12] (1273:1273:1273) (1338:1338:1338)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) ) ) (TIMINGCHECK @@ -31066,8 +35526,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1851:1851:1851) (1777:1777:1777)) - (PORT clk (1637:1637:1637) (1666:1666:1666)) + (PORT d[0] (1132:1132:1132) (1110:1110:1110)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) ) ) (TIMINGCHECK @@ -31079,8 +35539,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (PORT d[0] (2025:2025:2025) (1959:1959:1959)) + (PORT clk (1638:1638:1638) (1664:1664:1664)) + (PORT d[0] (2443:2443:2443) (2415:2415:2415)) ) ) ) @@ -31089,7 +35549,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) + (PORT clk (1639:1639:1639) (1665:1665:1665)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) @@ -31099,7 +35559,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) + (PORT clk (1639:1639:1639) (1665:1665:1665)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -31109,7 +35569,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) + (PORT clk (1639:1639:1639) (1665:1665:1665)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -31119,7 +35579,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) + (PORT clk (1639:1639:1639) (1665:1665:1665)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -31129,7 +35589,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1604:1604:1604) (1632:1632:1632)) + (PORT clk (1602:1602:1602) (1628:1628:1628)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -31143,7 +35603,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (875:875:875) (879:879:879)) + (PORT clk (873:873:873) (875:875:875)) ) ) ) @@ -31152,7 +35612,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) + (PORT clk (874:874:874) (876:876:876)) ) ) ) @@ -31161,7 +35621,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) + (PORT clk (874:874:874) (876:876:876)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -31171,536 +35631,49 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) + (PORT clk (874:874:874) (876:876:876)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~91) + (INSTANCE D\[6\]\~103) (DELAY (ABSOLUTE - (PORT dataa (782:782:782) (763:763:763)) - (PORT datab (1311:1311:1311) (1347:1347:1347)) - (PORT datac (296:296:296) (303:303:303)) - (PORT datad (1025:1025:1025) (1001:1001:1001)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (658:658:658)) - (PORT datab (228:228:228) (282:282:282)) - (PORT datac (330:330:330) (356:356:356)) - (PORT datad (1201:1201:1201) (1152:1152:1152)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE CLOCK_50\~inputclkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (133:133:133) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (977:977:977) (979:979:979)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1154:1154:1154) (1185:1185:1185)) - (PORT datab (896:896:896) (950:950:950)) - (PORT datac (885:885:885) (936:936:936)) - (PORT datad (252:252:252) (321:321:321)) + (PORT dataa (1345:1345:1345) (1354:1354:1354)) + (PORT datab (1149:1149:1149) (1145:1145:1145)) + (PORT datad (1329:1329:1329) (1284:1284:1284)) (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1360:1360:1360) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1111:1111:1111) (1090:1090:1090)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1360:1360:1360) (1375:1375:1375)) - (PORT asdata (1110:1110:1110) (1132:1132:1132)) - (PORT ena (1111:1111:1111) (1090:1090:1090)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT datac (833:833:833) (864:864:864)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1360:1360:1360) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1111:1111:1111) (1090:1090:1090)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~0) - (DELAY - (ABSOLUTE - (PORT datac (829:829:829) (860:860:860)) - (PORT datad (1338:1338:1338) (1335:1335:1335)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1360:1360:1360) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1111:1111:1111) (1090:1090:1090)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (866:866:866) (895:895:895)) - (PORT datac (1295:1295:1295) (1303:1303:1303)) - (PORT datad (1339:1339:1339) (1335:1335:1335)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1360:1360:1360) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1111:1111:1111) (1090:1090:1090)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (694:694:694)) - (PORT datab (663:663:663) (715:715:715)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~2) - (DELAY - (ABSOLUTE - (PORT datab (607:607:607) (640:640:640)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~4) - (DELAY - (ABSOLUTE - (PORT datab (659:659:659) (688:688:688)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~6) - (DELAY - (ABSOLUTE - (PORT datab (634:634:634) (682:682:682)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1360:1360:1360) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1111:1111:1111) (1090:1090:1090)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~8) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (702:702:702)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1360:1360:1360) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1111:1111:1111) (1090:1090:1090)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~10) - (DELAY - (ABSOLUTE - (PORT dataa (907:907:907) (921:921:921)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1360:1360:1360) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1111:1111:1111) (1090:1090:1090)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~12) - (DELAY - (ABSOLUTE - (PORT datab (645:645:645) (681:681:681)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector6\~0) - (DELAY - (ABSOLUTE - (PORT datab (559:559:559) (581:581:581)) - (PORT datac (526:526:526) (531:531:531)) - (PORT datad (889:889:889) (923:923:923)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[9\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1154:1154:1154) (1188:1188:1188)) - (PORT datab (895:895:895) (951:951:951)) - (PORT datac (889:889:889) (941:941:941)) - (PORT datad (257:257:257) (326:326:326)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (752:752:752)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~14) - (DELAY - (ABSOLUTE - (PORT datad (652:652:652) (694:694:694)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (612:612:612)) - (PORT datac (736:736:736) (733:733:733)) - (PORT datad (889:889:889) (927:927:927)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (752:752:752)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1152:1152:1152) (1182:1182:1182)) - (PORT datab (891:891:891) (944:944:944)) - (PORT datac (893:893:893) (945:945:945)) - (PORT datad (261:261:261) (330:330:330)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (574:574:574) (583:583:583)) - (PORT datab (925:925:925) (976:976:976)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector3\~0) + (INSTANCE D\[6\]\~104) (DELAY (ABSOLUTE - (PORT datab (562:562:562) (582:582:582)) - (PORT datad (890:890:890) (925:925:925)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (752:752:752)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector2\~0) - (DELAY - (ABSOLUTE - (PORT datac (566:566:566) (578:578:578)) - (PORT datad (889:889:889) (923:923:923)) + (PORT dataa (1408:1408:1408) (1434:1434:1434)) + (PORT datab (1690:1690:1690) (1773:1773:1773)) + (PORT datac (1326:1326:1326) (1309:1309:1309)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (752:752:752)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1438:1438:1438) (1457:1457:1457)) - (PORT clk (1649:1649:1649) (1677:1677:1677)) + (PORT d[0] (1174:1174:1174) (1180:1180:1180)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) ) ) (TIMINGCHECK @@ -31712,20 +35685,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2413:2413:2413) (2427:2427:2427)) - (PORT d[1] (2186:2186:2186) (2314:2314:2314)) - (PORT d[2] (2143:2143:2143) (2219:2219:2219)) - (PORT d[3] (1833:1833:1833) (1876:1876:1876)) - (PORT d[4] (2724:2724:2724) (2866:2866:2866)) - (PORT d[5] (1945:1945:1945) (2062:2062:2062)) - (PORT d[6] (1446:1446:1446) (1485:1485:1485)) - (PORT d[7] (1502:1502:1502) (1535:1535:1535)) - (PORT d[8] (2576:2576:2576) (2689:2689:2689)) - (PORT d[9] (1919:1919:1919) (1944:1944:1944)) - (PORT d[10] (1964:1964:1964) (1995:1995:1995)) - (PORT d[11] (2954:2954:2954) (3003:3003:3003)) - (PORT d[12] (2038:2038:2038) (2059:2059:2059)) - (PORT clk (1646:1646:1646) (1675:1675:1675)) + (PORT d[0] (2605:2605:2605) (2669:2669:2669)) + (PORT d[1] (1701:1701:1701) (1733:1733:1733)) + (PORT d[2] (1765:1765:1765) (1825:1825:1825)) + (PORT d[3] (1991:1991:1991) (2045:2045:2045)) + (PORT d[4] (2201:2201:2201) (2250:2250:2250)) + (PORT d[5] (1726:1726:1726) (1773:1773:1773)) + (PORT d[6] (2165:2165:2165) (2208:2208:2208)) + (PORT d[7] (2045:2045:2045) (2081:2081:2081)) + (PORT d[8] (2933:2933:2933) (2976:2976:2976)) + (PORT d[9] (1602:1602:1602) (1690:1690:1690)) + (PORT d[10] (1508:1508:1508) (1579:1579:1579)) + (PORT d[11] (2225:2225:2225) (2285:2285:2285)) + (PORT d[12] (2265:2265:2265) (2328:2328:2328)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) ) ) (TIMINGCHECK @@ -31737,8 +35710,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2558:2558:2558) (2482:2482:2482)) - (PORT clk (1646:1646:1646) (1675:1675:1675)) + (PORT d[0] (1635:1635:1635) (1603:1603:1603)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) ) ) (TIMINGCHECK @@ -31750,8 +35723,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1649:1649:1649) (1677:1677:1677)) - (PORT d[0] (2573:2573:2573) (2575:2575:2575)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (PORT d[0] (2933:2933:2933) (2921:2921:2921)) ) ) ) @@ -31760,7 +35733,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1650:1650:1650) (1678:1678:1678)) + (PORT clk (1639:1639:1639) (1666:1666:1666)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) @@ -31770,7 +35743,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1650:1650:1650) (1678:1678:1678)) + (PORT clk (1639:1639:1639) (1666:1666:1666)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -31780,7 +35753,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1650:1650:1650) (1678:1678:1678)) + (PORT clk (1639:1639:1639) (1666:1666:1666)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -31790,7 +35763,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1650:1650:1650) (1678:1678:1678)) + (PORT clk (1639:1639:1639) (1666:1666:1666)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -31800,7 +35773,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1608:1608:1608) (1607:1607:1607)) + (PORT clk (1597:1597:1597) (1595:1595:1595)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -31814,8 +35787,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1996:1996:1996) (1985:1985:1985)) - (PORT clk (1616:1616:1616) (1614:1614:1614)) + (PORT d[0] (1744:1744:1744) (1758:1758:1758)) + (PORT clk (1605:1605:1605) (1602:1602:1602)) ) ) (TIMINGCHECK @@ -31827,20 +35800,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4310:4310:4310) (4203:4203:4203)) - (PORT d[1] (4109:4109:4109) (3957:3957:3957)) - (PORT d[2] (4248:4248:4248) (4146:4146:4146)) - (PORT d[3] (4389:4389:4389) (4241:4241:4241)) - (PORT d[4] (3981:3981:3981) (3826:3826:3826)) - (PORT d[5] (4115:4115:4115) (3954:3954:3954)) - (PORT d[6] (4311:4311:4311) (4251:4251:4251)) - (PORT d[7] (4106:4106:4106) (3931:3931:3931)) - (PORT d[8] (4394:4394:4394) (4226:4226:4226)) - (PORT d[9] (4253:4253:4253) (4312:4312:4312)) - (PORT d[10] (4136:4136:4136) (4024:4024:4024)) - (PORT d[11] (4334:4334:4334) (4189:4189:4189)) - (PORT d[12] (4138:4138:4138) (4057:4057:4057)) - (PORT clk (1613:1613:1613) (1611:1611:1611)) + (PORT d[0] (4118:4118:4118) (4095:4095:4095)) + (PORT d[1] (4082:4082:4082) (4121:4121:4121)) + (PORT d[2] (4232:4232:4232) (4129:4129:4129)) + (PORT d[3] (3938:3938:3938) (3910:3910:3910)) + (PORT d[4] (4046:4046:4046) (3977:3977:3977)) + (PORT d[5] (4080:4080:4080) (4058:4058:4058)) + (PORT d[6] (4035:4035:4035) (3994:3994:3994)) + (PORT d[7] (4079:4079:4079) (4064:4064:4064)) + (PORT d[8] (4294:4294:4294) (4238:4238:4238)) + (PORT d[9] (4104:4104:4104) (4047:4047:4047)) + (PORT d[10] (4093:4093:4093) (4034:4034:4034)) + (PORT d[11] (4127:4127:4127) (4082:4082:4082)) + (PORT d[12] (4100:4100:4100) (4018:4018:4018)) + (PORT clk (1602:1602:1602) (1599:1599:1599)) ) ) (TIMINGCHECK @@ -31852,7 +35825,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1616:1616:1616) (1614:1614:1614)) + (PORT clk (1605:1605:1605) (1602:1602:1602)) ) ) ) @@ -31861,7 +35834,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1617:1617:1617) (1615:1615:1615)) + (PORT clk (1606:1606:1606) (1603:1603:1603)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) @@ -31871,7 +35844,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1617:1617:1617) (1615:1615:1615)) + (PORT clk (1606:1606:1606) (1603:1603:1603)) (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) ) ) @@ -31881,7 +35854,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1617:1617:1617) (1615:1615:1615)) + (PORT clk (1606:1606:1606) (1603:1603:1603)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -31891,7 +35864,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1617:1617:1617) (1615:1615:1615)) + (PORT clk (1606:1606:1606) (1603:1603:1603)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -31901,7 +35874,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) (DELAY (ABSOLUTE - (PORT clk (1609:1609:1609) (1608:1608:1608)) + (PORT clk (1598:1598:1598) (1596:1596:1596)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -31910,67 +35883,13 @@ (HOLD d (posedge clk) (142:142:142)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1113:1113:1113) (1158:1158:1158)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1706:1706:1706) (1725:1725:1725)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) - (PORT asdata (1584:1584:1584) (1576:1576:1576)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (658:658:658)) - (PORT datab (231:231:231) (285:285:285)) - (PORT datac (331:331:331) (357:357:357)) - (PORT datad (1200:1200:1200) (1156:1156:1156)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1404:1404:1404) (1421:1421:1421)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT d[0] (1141:1141:1141) (1143:1143:1143)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) ) ) (TIMINGCHECK @@ -31982,20 +35901,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2693:2693:2693) (2714:2714:2714)) - (PORT d[1] (2208:2208:2208) (2339:2339:2339)) - (PORT d[2] (1126:1126:1126) (1144:1144:1144)) - (PORT d[3] (1855:1855:1855) (1908:1908:1908)) - (PORT d[4] (2708:2708:2708) (2836:2836:2836)) - (PORT d[5] (2235:2235:2235) (2355:2355:2355)) - (PORT d[6] (1416:1416:1416) (1429:1429:1429)) - (PORT d[7] (1186:1186:1186) (1211:1211:1211)) - (PORT d[8] (1580:1580:1580) (1586:1586:1586)) - (PORT d[9] (1446:1446:1446) (1451:1451:1451)) - (PORT d[10] (2003:2003:2003) (2052:2052:2052)) - (PORT d[11] (2973:2973:2973) (3030:3030:3030)) - (PORT d[12] (1779:1779:1779) (1812:1812:1812)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) + (PORT d[0] (2606:2606:2606) (2670:2670:2670)) + (PORT d[1] (1699:1699:1699) (1730:1730:1730)) + (PORT d[2] (2088:2088:2088) (2156:2156:2156)) + (PORT d[3] (1995:1995:1995) (2050:2050:2050)) + (PORT d[4] (2189:2189:2189) (2247:2247:2247)) + (PORT d[5] (1722:1722:1722) (1766:1766:1766)) + (PORT d[6] (1705:1705:1705) (1772:1772:1772)) + (PORT d[7] (1734:1734:1734) (1752:1752:1752)) + (PORT d[8] (2910:2910:2910) (2945:2945:2945)) + (PORT d[9] (1580:1580:1580) (1668:1668:1668)) + (PORT d[10] (3626:3626:3626) (3667:3667:3667)) + (PORT d[11] (2227:2227:2227) (2291:2291:2291)) + (PORT d[12] (1554:1554:1554) (1633:1633:1633)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) ) ) (TIMINGCHECK @@ -32007,8 +35926,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2500:2500:2500) (2409:2409:2409)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) + (PORT d[0] (1567:1567:1567) (1502:1502:1502)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) ) ) (TIMINGCHECK @@ -32020,8 +35939,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (PORT d[0] (2817:2817:2817) (2815:2815:2815)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) + (PORT d[0] (2670:2670:2670) (2673:2673:2673)) ) ) ) @@ -32030,7 +35949,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) + (PORT clk (1636:1636:1636) (1663:1663:1663)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) @@ -32040,7 +35959,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) + (PORT clk (1636:1636:1636) (1663:1663:1663)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -32050,7 +35969,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) + (PORT clk (1636:1636:1636) (1663:1663:1663)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -32060,7 +35979,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) + (PORT clk (1636:1636:1636) (1663:1663:1663)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -32070,7 +35989,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1602:1602:1602) (1600:1600:1600)) + (PORT clk (1594:1594:1594) (1592:1592:1592)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -32084,8 +36003,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2015:2015:2015) (2003:2003:2003)) - (PORT clk (1610:1610:1610) (1607:1607:1607)) + (PORT d[0] (1712:1712:1712) (1724:1724:1724)) + (PORT clk (1602:1602:1602) (1599:1599:1599)) ) ) (TIMINGCHECK @@ -32097,20 +36016,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4298:4298:4298) (4182:4182:4182)) - (PORT d[1] (3895:3895:3895) (3763:3763:3763)) - (PORT d[2] (3977:3977:3977) (3887:3887:3887)) - (PORT d[3] (4174:4174:4174) (4075:4075:4075)) - (PORT d[4] (4037:4037:4037) (3903:3903:3903)) - (PORT d[5] (4054:4054:4054) (3954:3954:3954)) - (PORT d[6] (4151:4151:4151) (4124:4124:4124)) - (PORT d[7] (3882:3882:3882) (3713:3713:3713)) - (PORT d[8] (4101:4101:4101) (3936:3936:3936)) - (PORT d[9] (4231:4231:4231) (4282:4282:4282)) - (PORT d[10] (4119:4119:4119) (4022:4022:4022)) - (PORT d[11] (4215:4215:4215) (4129:4129:4129)) - (PORT d[12] (4134:4134:4134) (4050:4050:4050)) - (PORT clk (1607:1607:1607) (1604:1604:1604)) + (PORT d[0] (4129:4129:4129) (4092:4092:4092)) + (PORT d[1] (4031:4031:4031) (4056:4056:4056)) + (PORT d[2] (4108:4108:4108) (4046:4046:4046)) + (PORT d[3] (3952:3952:3952) (3915:3915:3915)) + (PORT d[4] (4042:4042:4042) (3967:3967:3967)) + (PORT d[5] (4100:4100:4100) (4079:4079:4079)) + (PORT d[6] (4103:4103:4103) (4033:4033:4033)) + (PORT d[7] (4050:4050:4050) (4030:4030:4030)) + (PORT d[8] (4318:4318:4318) (4266:4266:4266)) + (PORT d[9] (4159:4159:4159) (4085:4085:4085)) + (PORT d[10] (4133:4133:4133) (4084:4084:4084)) + (PORT d[11] (4147:4147:4147) (4096:4096:4096)) + (PORT d[12] (4099:4099:4099) (4018:4018:4018)) + (PORT clk (1599:1599:1599) (1596:1596:1596)) ) ) (TIMINGCHECK @@ -32122,7 +36041,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1610:1610:1610) (1607:1607:1607)) + (PORT clk (1602:1602:1602) (1599:1599:1599)) ) ) ) @@ -32131,7 +36050,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1611:1611:1611) (1608:1608:1608)) + (PORT clk (1603:1603:1603) (1600:1600:1600)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) @@ -32141,7 +36060,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1611:1611:1611) (1608:1608:1608)) + (PORT clk (1603:1603:1603) (1600:1600:1600)) ) ) ) @@ -32150,7 +36069,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1611:1611:1611) (1608:1608:1608)) + (PORT clk (1603:1603:1603) (1600:1600:1600)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -32160,7 +36079,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1611:1611:1611) (1608:1608:1608)) + (PORT clk (1603:1603:1603) (1600:1600:1600)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -32170,20 +36089,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2355:2355:2355) (2346:2346:2346)) - (PORT d[1] (2066:2066:2066) (2149:2149:2149)) - (PORT d[2] (2142:2142:2142) (2225:2225:2225)) - (PORT d[3] (2023:2023:2023) (2092:2092:2092)) - (PORT d[4] (2698:2698:2698) (2836:2836:2836)) - (PORT d[5] (2125:2125:2125) (2238:2238:2238)) - (PORT d[6] (1723:1723:1723) (1771:1771:1771)) - (PORT d[7] (2056:2056:2056) (2040:2040:2040)) - (PORT d[8] (2548:2548:2548) (2649:2649:2649)) - (PORT d[9] (1614:1614:1614) (1648:1648:1648)) - (PORT d[10] (1630:1630:1630) (1624:1624:1624)) - (PORT d[11] (2891:2891:2891) (2914:2914:2914)) - (PORT d[12] (1192:1192:1192) (1217:1217:1217)) - (PORT clk (1654:1654:1654) (1681:1681:1681)) + (PORT d[0] (2326:2326:2326) (2379:2379:2379)) + (PORT d[1] (2454:2454:2454) (2491:2491:2491)) + (PORT d[2] (2065:2065:2065) (2140:2140:2140)) + (PORT d[3] (1941:1941:1941) (1996:1996:1996)) + (PORT d[4] (1635:1635:1635) (1673:1673:1673)) + (PORT d[5] (1981:1981:1981) (2035:2035:2035)) + (PORT d[6] (2222:2222:2222) (2291:2291:2291)) + (PORT d[7] (3167:3167:3167) (3201:3201:3201)) + (PORT d[8] (2665:2665:2665) (2694:2694:2694)) + (PORT d[9] (1892:1892:1892) (1995:1995:1995)) + (PORT d[10] (1768:1768:1768) (1842:1842:1842)) + (PORT d[11] (1974:1974:1974) (2023:2023:2023)) + (PORT d[12] (2086:2086:2086) (2174:2174:2174)) + (PORT clk (1644:1644:1644) (1672:1672:1672)) ) ) (TIMINGCHECK @@ -32195,8 +36114,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1654:1654:1654) (1681:1681:1681)) - (PORT d[0] (2020:2020:2020) (2024:2024:2024)) + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (PORT d[0] (2385:2385:2385) (2403:2403:2403)) ) ) ) @@ -32205,7 +36124,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1655:1655:1655) (1682:1682:1682)) + (PORT clk (1645:1645:1645) (1673:1673:1673)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -32215,7 +36134,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1621:1621:1621) (1647:1647:1647)) + (PORT clk (1611:1611:1611) (1638:1638:1638)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -32229,7 +36148,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (892:892:892) (894:894:894)) + (PORT clk (882:882:882) (885:885:885)) ) ) ) @@ -32238,7 +36157,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (893:893:893) (895:895:895)) + (PORT clk (883:883:883) (886:886:886)) ) ) ) @@ -32247,7 +36166,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (893:893:893) (895:895:895)) + (PORT clk (883:883:883) (886:886:886)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -32257,22 +36176,22 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (893:893:893) (895:895:895)) + (PORT clk (883:883:883) (886:886:886)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~87) + (INSTANCE D\[6\]\~100) (DELAY (ABSOLUTE - (PORT dataa (1255:1255:1255) (1240:1240:1240)) - (PORT datab (248:248:248) (325:325:325)) - (PORT datac (1284:1284:1284) (1276:1276:1276)) - (PORT datad (1538:1538:1538) (1507:1507:1507)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (1088:1088:1088) (1090:1090:1090)) + (PORT datab (275:275:275) (357:357:357)) + (PORT datac (1055:1055:1055) (1079:1079:1079)) + (PORT datad (1337:1337:1337) (1335:1335:1335)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -32283,20 +36202,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3394:3394:3394) (3476:3476:3476)) - (PORT d[1] (2412:2412:2412) (2539:2539:2539)) - (PORT d[2] (2265:2265:2265) (2288:2288:2288)) - (PORT d[3] (1992:1992:1992) (2060:2060:2060)) - (PORT d[4] (2069:2069:2069) (2140:2140:2140)) - (PORT d[5] (1928:1928:1928) (2016:2016:2016)) - (PORT d[6] (1784:1784:1784) (1847:1847:1847)) - (PORT d[7] (1844:1844:1844) (1862:1862:1862)) - (PORT d[8] (2787:2787:2787) (2891:2891:2891)) - (PORT d[9] (2420:2420:2420) (2486:2486:2486)) - (PORT d[10] (4385:4385:4385) (4449:4449:4449)) - (PORT d[11] (1943:1943:1943) (1988:1988:1988)) - (PORT d[12] (2255:2255:2255) (2302:2302:2302)) - (PORT clk (1643:1643:1643) (1672:1672:1672)) + (PORT d[0] (1821:1821:1821) (1875:1875:1875)) + (PORT d[1] (2776:2776:2776) (2838:2838:2838)) + (PORT d[2] (2092:2092:2092) (2106:2106:2106)) + (PORT d[3] (3365:3365:3365) (3401:3401:3401)) + (PORT d[4] (2411:2411:2411) (2492:2492:2492)) + (PORT d[5] (3823:3823:3823) (3873:3873:3873)) + (PORT d[6] (2552:2552:2552) (2551:2551:2551)) + (PORT d[7] (3438:3438:3438) (3438:3438:3438)) + (PORT d[8] (1871:1871:1871) (1885:1885:1885)) + (PORT d[9] (1981:1981:1981) (2019:2019:2019)) + (PORT d[10] (2182:2182:2182) (2193:2193:2193)) + (PORT d[11] (2612:2612:2612) (2700:2700:2700)) + (PORT d[12] (3545:3545:3545) (3643:3643:3643)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) ) ) (TIMINGCHECK @@ -32308,8 +36227,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1643:1643:1643) (1672:1672:1672)) - (PORT d[0] (2836:2836:2836) (2867:2867:2867)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (PORT d[0] (2037:2037:2037) (2057:2057:2057)) ) ) ) @@ -32318,7 +36237,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1644:1644:1644) (1673:1673:1673)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -32328,7 +36247,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1610:1610:1610) (1638:1638:1638)) + (PORT clk (1606:1606:1606) (1633:1633:1633)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -32342,7 +36261,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (881:881:881) (885:885:885)) + (PORT clk (877:877:877) (880:880:880)) ) ) ) @@ -32351,7 +36270,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) + (PORT clk (878:878:878) (881:881:881)) ) ) ) @@ -32360,7 +36279,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) + (PORT clk (878:878:878) (881:881:881)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -32370,38 +36289,22 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) + (PORT clk (878:878:878) (881:881:881)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~88) + (INSTANCE D\[6\]\~101) (DELAY (ABSOLUTE - (PORT dataa (1191:1191:1191) (1152:1152:1152)) - (PORT datab (1080:1080:1080) (1050:1050:1050)) - (PORT datac (1488:1488:1488) (1466:1466:1466)) - (PORT datad (163:163:163) (188:188:188)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (1324:1324:1324) (1337:1337:1337)) - (PORT datab (190:190:190) (225:225:225)) - (PORT datac (580:580:580) (608:608:608)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) + (PORT dataa (1209:1209:1209) (1247:1247:1247)) + (PORT datab (1151:1151:1151) (1147:1147:1147)) + (PORT datac (162:162:162) (197:197:197)) + (PORT datad (984:984:984) (957:957:957)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -32409,16 +36312,32 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~111) + (INSTANCE D\[6\]\~102) (DELAY (ABSOLUTE - (PORT dataa (598:598:598) (604:604:604)) - (PORT datab (1866:1866:1866) (1894:1894:1894)) - (PORT datac (848:848:848) (891:891:891)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1082:1082:1082) (1088:1088:1088)) + (PORT datab (276:276:276) (359:359:359)) + (PORT datac (162:162:162) (195:195:195)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~127) + (DELAY + (ABSOLUTE + (PORT dataa (1309:1309:1309) (1328:1328:1328)) + (PORT datab (2123:2123:2123) (2266:2266:2266)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -32434,29 +36353,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~86) + (INSTANCE D\[6\]\~99) (DELAY (ABSOLUTE - (PORT dataa (843:843:843) (876:876:876)) - (PORT datac (1426:1426:1426) (1503:1503:1503)) - (PORT datad (1841:1841:1841) (1862:1862:1862)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datab (1132:1132:1132) (1181:1181:1181)) + (PORT datac (2344:2344:2344) (2478:2478:2478)) + (PORT datad (1350:1350:1350) (1398:1398:1398)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~100) + (INSTANCE D\[6\]\~114) (DELAY (ABSOLUTE - (PORT dataa (879:879:879) (895:895:895)) - (PORT datab (1277:1277:1277) (1232:1232:1232)) - (PORT datac (163:163:163) (197:197:197)) - (PORT datad (166:166:166) (188:188:188)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (1441:1441:1441) (1455:1455:1455)) + (PORT datab (404:404:404) (424:424:424)) + (PORT datac (556:556:556) (530:530:530)) + (PORT datad (179:179:179) (202:202:202)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -32464,16 +36383,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~101) + (INSTANCE D\[6\]\~115) (DELAY (ABSOLUTE - (PORT dataa (875:875:875) (888:888:888)) - (PORT datab (824:824:824) (860:860:860)) - (PORT datac (1535:1535:1535) (1519:1519:1519)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (2075:2075:2075) (2058:2058:2058)) + (PORT datab (405:405:405) (421:421:421)) + (PORT datac (1118:1118:1118) (1162:1162:1162)) + (PORT datad (177:177:177) (200:200:200)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -32483,10 +36402,10 @@ (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (297:297:297)) - (PORT datab (1288:1288:1288) (1272:1272:1272)) - (PORT datac (874:874:874) (915:915:915)) - (PORT datad (772:772:772) (740:740:740)) + (PORT dataa (1738:1738:1738) (1713:1713:1713)) + (PORT datab (382:382:382) (409:409:409)) + (PORT datac (325:325:325) (335:335:335)) + (PORT datad (1048:1048:1048) (1025:1025:1025)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -32494,38 +36413,6 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1556:1556:1556) (1645:1645:1645)) - (PORT datab (703:703:703) (765:765:765)) - (PORT datac (881:881:881) (918:918:918)) - (PORT datad (1120:1120:1120) (1121:1121:1121)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) - (DELAY - (ABSOLUTE - (PORT dataa (900:900:900) (944:944:944)) - (PORT datab (906:906:906) (920:920:920)) - (PORT datac (883:883:883) (919:919:919)) - (PORT datad (166:166:166) (189:189:189)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|data_pins_\|dout\[6\]) @@ -32548,37 +36435,11 @@ (DELAY (ABSOLUTE (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (1089:1089:1089) (1102:1102:1102)) - (PORT datac (202:202:202) (249:249:249)) - (PORT datad (190:190:190) (219:219:219)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|ir_\|opcode\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (178:178:178) (198:198:198)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1024:1024:1024) (1078:1078:1078)) - (PORT datab (838:838:838) (869:869:869)) - (PORT datac (607:607:607) (638:638:638)) - (PORT datad (352:352:352) (353:353:353)) + (PORT datab (226:226:226) (273:273:273)) + (PORT datac (531:531:531) (555:555:555)) + (PORT datad (197:197:197) (227:227:227)) (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -32589,1717 +36450,10 @@ (INSTANCE z80_\|ir_\|opcode\[6\]) (DELAY (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1395:1395:1395) (1367:1367:1367)) - (PORT ena (1130:1130:1130) (1103:1103:1103)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~0) - (DELAY - (ABSOLUTE - (PORT datac (1564:1564:1564) (1572:1572:1572)) - (PORT datad (1132:1132:1132) (1167:1167:1167)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1375:1375:1375) (1400:1400:1400)) - (PORT datab (2129:2129:2129) (2186:2186:2186)) - (PORT datac (1970:1970:1970) (2062:2062:2062)) - (PORT datad (1338:1338:1338) (1386:1386:1386)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~2) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (454:454:454)) - (PORT datab (1517:1517:1517) (1484:1484:1484)) - (PORT datac (155:155:155) (184:184:184)) - (PORT datad (1017:1017:1017) (1026:1026:1026)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) - (DELAY - (ABSOLUTE - (PORT dataa (1815:1815:1815) (1864:1864:1864)) - (PORT datab (1040:1040:1040) (1024:1024:1024)) - (PORT datac (1910:1910:1910) (1950:1950:1950)) - (PORT datad (164:164:164) (186:186:186)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1096:1096:1096) (1097:1097:1097)) - (PORT datab (252:252:252) (318:318:318)) - (PORT datac (228:228:228) (287:287:287)) - (PORT datad (224:224:224) (260:260:260)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1046:1046:1046) (1077:1077:1077)) - (PORT datab (1066:1066:1066) (1087:1087:1087)) - (PORT datac (384:384:384) (438:438:438)) - (PORT datad (619:619:619) (637:637:637)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (890:890:890)) - (PORT datac (1540:1540:1540) (1543:1543:1543)) - (PORT datad (836:836:836) (826:826:826)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT datab (184:184:184) (217:217:217)) - (PORT datac (820:820:820) (816:816:816)) - (PORT datad (223:223:223) (257:257:257)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (350:350:350)) - (PORT datab (585:585:585) (576:576:576)) - (PORT datac (1068:1068:1068) (1089:1089:1089)) - (PORT datad (565:565:565) (556:556:556)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (919:919:919) (929:929:929)) - (PORT datac (549:549:549) (545:545:545)) - (PORT datad (200:200:200) (239:239:239)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1176:1176:1176) (1208:1208:1208)) - (PORT datab (868:868:868) (867:867:867)) - (PORT datac (1676:1676:1676) (1689:1689:1689)) - (PORT datad (864:864:864) (874:874:874)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (606:606:606)) - (PORT datab (230:230:230) (282:282:282)) - (PORT datac (159:159:159) (190:190:190)) - (PORT datad (871:871:871) (883:883:883)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (459:459:459)) - (PORT datab (1249:1249:1249) (1259:1259:1259)) - (PORT datac (1070:1070:1070) (1065:1065:1065)) - (PORT datad (1106:1106:1106) (1118:1118:1118)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) - (DELAY - (ABSOLUTE - (PORT dataa (517:517:517) (511:511:511)) - (PORT datab (584:584:584) (585:585:585)) - (PORT datac (608:608:608) (617:617:617)) - (PORT datad (625:625:625) (634:634:634)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_yf) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1353:1353:1353)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (618:618:618)) - (PORT datab (827:827:827) (852:852:852)) - (PORT datac (605:605:605) (615:615:615)) - (PORT datad (821:821:821) (812:812:812)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (899:899:899) (902:902:902)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (874:874:874) (874:874:874)) - (PORT datad (805:805:805) (791:791:791)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (641:641:641)) - (PORT datab (1109:1109:1109) (1091:1091:1091)) - (PORT datac (1028:1028:1028) (1036:1036:1036)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~107) - (DELAY - (ABSOLUTE - (PORT dataa (1618:1618:1618) (1660:1660:1660)) - (PORT datab (1133:1133:1133) (1150:1150:1150)) - (PORT datac (1446:1446:1446) (1508:1508:1508)) - (PORT datad (1045:1045:1045) (1034:1034:1034)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1107:1107:1107) (1081:1081:1081)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3423:3423:3423) (3511:3511:3511)) - (PORT d[1] (1610:1610:1610) (1712:1712:1712)) - (PORT d[2] (2815:2815:2815) (2865:2865:2865)) - (PORT d[3] (1754:1754:1754) (1799:1799:1799)) - (PORT d[4] (2040:2040:2040) (2098:2098:2098)) - (PORT d[5] (2484:2484:2484) (2590:2590:2590)) - (PORT d[6] (1915:1915:1915) (1948:1948:1948)) - (PORT d[7] (2568:2568:2568) (2586:2586:2586)) - (PORT d[8] (2819:2819:2819) (2925:2925:2925)) - (PORT d[9] (2617:2617:2617) (2662:2662:2662)) - (PORT d[10] (3254:3254:3254) (3360:3360:3360)) - (PORT d[11] (1682:1682:1682) (1715:1715:1715)) - (PORT d[12] (1930:1930:1930) (1983:1983:1983)) - (PORT clk (1629:1629:1629) (1658:1658:1658)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1794:1794:1794) (1753:1753:1753)) - (PORT clk (1629:1629:1629) (1658:1658:1658)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1660:1660:1660)) - (PORT d[0] (2430:2430:2430) (2431:2431:2431)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1596:1596:1596) (1624:1624:1624)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (867:867:867) (871:871:871)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (872:872:872)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (872:872:872)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (872:872:872)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1096:1096:1096) (1074:1074:1074)) - (PORT clk (1630:1630:1630) (1658:1658:1658)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3694:3694:3694) (3794:3794:3794)) - (PORT d[1] (1581:1581:1581) (1666:1666:1666)) - (PORT d[2] (3056:3056:3056) (3113:3113:3113)) - (PORT d[3] (1749:1749:1749) (1779:1779:1779)) - (PORT d[4] (1736:1736:1736) (1765:1765:1765)) - (PORT d[5] (1519:1519:1519) (1586:1586:1586)) - (PORT d[6] (1635:1635:1635) (1666:1666:1666)) - (PORT d[7] (2830:2830:2830) (2851:2851:2851)) - (PORT d[8] (3086:3086:3086) (3198:3198:3198)) - (PORT d[9] (2654:2654:2654) (2713:2713:2713)) - (PORT d[10] (3197:3197:3197) (3270:3270:3270)) - (PORT d[11] (1430:1430:1430) (1454:1454:1454)) - (PORT d[12] (1604:1604:1604) (1641:1641:1641)) - (PORT clk (1627:1627:1627) (1656:1656:1656)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1789:1789:1789) (1719:1719:1719)) - (PORT clk (1627:1627:1627) (1656:1656:1656)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1630:1630:1630) (1658:1658:1658)) - (PORT d[0] (2199:2199:2199) (2121:2121:2121)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1594:1594:1594) (1622:1622:1622)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (865:865:865) (869:869:869)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (866:866:866) (870:870:870)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (866:866:866) (870:870:870)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (866:866:866) (870:870:870)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1132:1132:1132) (1118:1118:1118)) - (PORT clk (1630:1630:1630) (1658:1658:1658)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3424:3424:3424) (3512:3512:3512)) - (PORT d[1] (1571:1571:1571) (1675:1675:1675)) - (PORT d[2] (2754:2754:2754) (2823:2823:2823)) - (PORT d[3] (1969:1969:1969) (1988:1988:1988)) - (PORT d[4] (2069:2069:2069) (2124:2124:2124)) - (PORT d[5] (2492:2492:2492) (2612:2612:2612)) - (PORT d[6] (1673:1673:1673) (1720:1720:1720)) - (PORT d[7] (2571:2571:2571) (2592:2592:2592)) - (PORT d[8] (3107:3107:3107) (3211:3211:3211)) - (PORT d[9] (2672:2672:2672) (2732:2732:2732)) - (PORT d[10] (3224:3224:3224) (3324:3324:3324)) - (PORT d[11] (1692:1692:1692) (1728:1728:1728)) - (PORT d[12] (1875:1875:1875) (1914:1914:1914)) - (PORT clk (1627:1627:1627) (1656:1656:1656)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1755:1755:1755) (1697:1697:1697)) - (PORT clk (1627:1627:1627) (1656:1656:1656)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1630:1630:1630) (1658:1658:1658)) - (PORT d[0] (2267:2267:2267) (2233:2233:2233)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1594:1594:1594) (1622:1622:1622)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (865:865:865) (869:869:869)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (866:866:866) (870:870:870)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (866:866:866) (870:870:870)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (866:866:866) (870:870:870)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1338:1338:1338) (1342:1342:1342)) - (PORT datab (1310:1310:1310) (1345:1345:1345)) - (PORT datac (1055:1055:1055) (1028:1028:1028)) - (PORT datad (1035:1035:1035) (1017:1017:1017)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1177:1177:1177) (1189:1189:1189)) - (PORT clk (1639:1639:1639) (1667:1667:1667)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2678:2678:2678) (2705:2705:2705)) - (PORT d[1] (2465:2465:2465) (2605:2605:2605)) - (PORT d[2] (1123:1123:1123) (1138:1138:1138)) - (PORT d[3] (1565:1565:1565) (1603:1603:1603)) - (PORT d[4] (2689:2689:2689) (2795:2795:2795)) - (PORT d[5] (2214:2214:2214) (2342:2342:2342)) - (PORT d[6] (1167:1167:1167) (1193:1193:1193)) - (PORT d[7] (1224:1224:1224) (1251:1251:1251)) - (PORT d[8] (1619:1619:1619) (1631:1631:1631)) - (PORT d[9] (1169:1169:1169) (1184:1184:1184)) - (PORT d[10] (2227:2227:2227) (2272:2272:2272)) - (PORT d[11] (2936:2936:2936) (3022:3022:3022)) - (PORT d[12] (2039:2039:2039) (2078:2078:2078)) - (PORT clk (1636:1636:1636) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1377:1377:1377) (1357:1357:1357)) - (PORT clk (1636:1636:1636) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (PORT d[0] (1925:1925:1925) (1914:1914:1914)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1603:1603:1603) (1631:1631:1631)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (875:875:875) (879:879:879)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (875:875:875) (879:879:879)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (875:875:875) (879:879:879)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1045:1045:1045) (1054:1054:1054)) - (PORT datab (1569:1569:1569) (1585:1585:1585)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (1315:1315:1315) (1322:1322:1322)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1492:1492:1492) (1530:1530:1530)) - (PORT clk (1638:1638:1638) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2957:2957:2957) (2968:2968:2968)) - (PORT d[1] (1859:1859:1859) (1960:1960:1960)) - (PORT d[2] (2024:2024:2024) (2042:2042:2042)) - (PORT d[3] (1726:1726:1726) (1784:1784:1784)) - (PORT d[4] (2308:2308:2308) (2357:2357:2357)) - (PORT d[5] (2072:2072:2072) (2153:2153:2153)) - (PORT d[6] (1595:1595:1595) (1605:1605:1605)) - (PORT d[7] (1567:1567:1567) (1598:1598:1598)) - (PORT d[8] (2423:2423:2423) (2497:2497:2497)) - (PORT d[9] (1817:1817:1817) (1859:1859:1859)) - (PORT d[10] (1866:1866:1866) (1904:1904:1904)) - (PORT d[11] (2253:2253:2253) (2298:2298:2298)) - (PORT d[12] (2364:2364:2364) (2372:2372:2372)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2369:2369:2369) (2331:2331:2331)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1665:1665:1665)) - (PORT d[0] (3638:3638:3638) (3625:3625:3625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1597:1597:1597) (1595:1595:1595)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1613:1613:1613) (1560:1560:1560)) - (PORT clk (1605:1605:1605) (1602:1602:1602)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4091:4091:4091) (4004:4004:4004)) - (PORT d[1] (3942:3942:3942) (3858:3858:3858)) - (PORT d[2] (4035:4035:4035) (3940:3940:3940)) - (PORT d[3] (4359:4359:4359) (4253:4253:4253)) - (PORT d[4] (4055:4055:4055) (3927:3927:3927)) - (PORT d[5] (4299:4299:4299) (4223:4223:4223)) - (PORT d[6] (4408:4408:4408) (4355:4355:4355)) - (PORT d[7] (4042:4042:4042) (3983:3983:3983)) - (PORT d[8] (4110:4110:4110) (3989:3989:3989)) - (PORT d[9] (4148:4148:4148) (4218:4218:4218)) - (PORT d[10] (4304:4304:4304) (4166:4166:4166)) - (PORT d[11] (4107:4107:4107) (3994:3994:3994)) - (PORT d[12] (4188:4188:4188) (4201:4201:4201)) - (PORT clk (1602:1602:1602) (1599:1599:1599)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1605:1605:1605) (1602:1602:1602)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1603:1603:1603)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1603:1603:1603)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1603:1603:1603)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1603:1603:1603)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2654:2654:2654) (2677:2677:2677)) - (PORT d[1] (1605:1605:1605) (1701:1701:1701)) - (PORT d[2] (1805:1805:1805) (1844:1844:1844)) - (PORT d[3] (1758:1758:1758) (1811:1811:1811)) - (PORT d[4] (2545:2545:2545) (2597:2597:2597)) - (PORT d[5] (2062:2062:2062) (2158:2158:2158)) - (PORT d[6] (1833:1833:1833) (1844:1844:1844)) - (PORT d[7] (1979:1979:1979) (2050:2050:2050)) - (PORT d[8] (2211:2211:2211) (2278:2278:2278)) - (PORT d[9] (1831:1831:1831) (1863:1863:1863)) - (PORT d[10] (1561:1561:1561) (1568:1568:1568)) - (PORT d[11] (1894:1894:1894) (1910:1910:1910)) - (PORT d[12] (2323:2323:2323) (2341:2341:2341)) - (PORT clk (1642:1642:1642) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1671:1671:1671)) - (PORT d[0] (2518:2518:2518) (2506:2506:2506)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1637:1637:1637)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (885:885:885)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (885:885:885)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3650:3650:3650) (3721:3721:3721)) - (PORT d[1] (2659:2659:2659) (2780:2780:2780)) - (PORT d[2] (2501:2501:2501) (2532:2532:2532)) - (PORT d[3] (2111:2111:2111) (2186:2186:2186)) - (PORT d[4] (2332:2332:2332) (2410:2410:2410)) - (PORT d[5] (2343:2343:2343) (2420:2420:2420)) - (PORT d[6] (1758:1758:1758) (1814:1814:1814)) - (PORT d[7] (2110:2110:2110) (2124:2124:2124)) - (PORT d[8] (2878:2878:2878) (3013:3013:3013)) - (PORT d[9] (2488:2488:2488) (2560:2560:2560)) - (PORT d[10] (4188:4188:4188) (4256:4256:4256)) - (PORT d[11] (1794:1794:1794) (1865:1865:1865)) - (PORT d[12] (2232:2232:2232) (2284:2284:2284)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) - (PORT d[0] (3251:3251:3251) (3306:3306:3306)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1637:1637:1637)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1388:1388:1388) (1400:1400:1400)) - (PORT clk (1653:1653:1653) (1680:1680:1680)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2615:2615:2615) (2615:2615:2615)) - (PORT d[1] (1928:1928:1928) (2048:2048:2048)) - (PORT d[2] (2048:2048:2048) (2108:2108:2108)) - (PORT d[3] (2094:2094:2094) (2149:2149:2149)) - (PORT d[4] (2727:2727:2727) (2871:2871:2871)) - (PORT d[5] (2213:2213:2213) (2304:2304:2304)) - (PORT d[6] (1452:1452:1452) (1493:1493:1493)) - (PORT d[7] (1446:1446:1446) (1477:1477:1477)) - (PORT d[8] (2564:2564:2564) (2665:2665:2665)) - (PORT d[9] (1933:1933:1933) (1963:1963:1963)) - (PORT d[10] (1735:1735:1735) (1770:1770:1770)) - (PORT d[11] (2684:2684:2684) (2729:2729:2729)) - (PORT d[12] (1488:1488:1488) (1509:1509:1509)) - (PORT clk (1650:1650:1650) (1678:1678:1678)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2318:2318:2318) (2256:2256:2256)) - (PORT clk (1650:1650:1650) (1678:1678:1678)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1653:1653:1653) (1680:1680:1680)) - (PORT d[0] (2607:2607:2607) (2597:2597:2597)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1654:1654:1654) (1681:1681:1681)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1654:1654:1654) (1681:1681:1681)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1654:1654:1654) (1681:1681:1681)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1654:1654:1654) (1681:1681:1681)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1612:1612:1612) (1610:1610:1610)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2309:2309:2309) (2319:2319:2319)) - (PORT clk (1620:1620:1620) (1617:1617:1617)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4211:4211:4211) (4070:4070:4070)) - (PORT d[1] (3836:3836:3836) (3699:3699:3699)) - (PORT d[2] (4108:4108:4108) (3975:3975:3975)) - (PORT d[3] (4152:4152:4152) (4053:4053:4053)) - (PORT d[4] (4243:4243:4243) (4094:4094:4094)) - (PORT d[5] (4089:4089:4089) (4013:4013:4013)) - (PORT d[6] (4274:4274:4274) (4211:4211:4211)) - (PORT d[7] (3881:3881:3881) (3728:3728:3728)) - (PORT d[8] (4330:4330:4330) (4206:4206:4206)) - (PORT d[9] (4176:4176:4176) (4207:4207:4207)) - (PORT d[10] (4313:4313:4313) (4213:4213:4213)) - (PORT d[11] (4097:4097:4097) (3970:3970:3970)) - (PORT d[12] (4147:4147:4147) (4084:4084:4084)) - (PORT clk (1617:1617:1617) (1614:1614:1614)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1620:1620:1620) (1617:1617:1617)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1621:1621:1621) (1618:1618:1618)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1621:1621:1621) (1618:1618:1618)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1621:1621:1621) (1618:1618:1618)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1621:1621:1621) (1618:1618:1618)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1613:1613:1613) (1611:1611:1611)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1327:1327:1327) (1341:1341:1341)) - (PORT datab (908:908:908) (940:940:940)) - (PORT datac (1088:1088:1088) (1077:1077:1077)) - (PORT datad (1560:1560:1560) (1534:1534:1534)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1400:1400:1400) (1441:1441:1441)) - (PORT datab (909:909:909) (941:941:941)) - (PORT datac (1580:1580:1580) (1576:1576:1576)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (1130:1130:1130) (1141:1141:1141)) - (PORT datac (1529:1529:1529) (1526:1526:1526)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (1282:1282:1282) (1254:1254:1254)) - (PORT datab (1295:1295:1295) (1272:1272:1272)) - (PORT datac (787:787:787) (812:812:812)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~99) - (DELAY - (ABSOLUTE - (PORT dataa (758:758:758) (752:752:752)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (945:945:945)) - (PORT datab (961:961:961) (952:952:952)) - (PORT datac (212:212:212) (261:261:261)) - (PORT datad (883:883:883) (890:890:890)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (656:656:656) (656:656:656)) - (PORT datac (212:212:212) (277:277:277)) - (PORT datad (327:327:327) (343:343:343)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (903:903:903)) - (PORT datab (849:849:849) (863:863:863)) - (PORT datac (755:755:755) (734:734:734)) - (PORT datad (817:817:817) (825:825:825)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1366:1366:1366)) - (PORT asdata (535:535:535) (588:588:588)) - (PORT clrn (1390:1390:1390) (1361:1361:1361)) - (PORT ena (1363:1363:1363) (1319:1319:1319)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (637:637:637) (638:638:638)) + (PORT clrn (1396:1396:1396) (1368:1368:1368)) + (PORT ena (1787:1787:1787) (1726:1726:1726)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -34311,61 +36465,537 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) + (INSTANCE z80_\|pla_decode_\|Equal13\~0) (DELAY (ABSOLUTE - (PORT dataa (1109:1109:1109) (1188:1188:1188)) - (PORT datab (795:795:795) (797:797:797)) - (PORT datac (798:798:798) (786:786:786)) - (PORT datad (1753:1753:1753) (1750:1750:1750)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT dataa (699:699:699) (745:745:745)) + (PORT datac (1700:1700:1700) (1776:1776:1776)) + (PORT datad (1563:1563:1563) (1567:1567:1567)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal38\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1606:1606:1606) (1650:1650:1650)) + (PORT datab (1511:1511:1511) (1636:1636:1636)) + (PORT datac (954:954:954) (996:996:996)) + (PORT datad (1663:1663:1663) (1723:1723:1723)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|iff1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (546:546:546)) + (PORT datab (239:239:239) (309:309:309)) + (PORT datac (576:576:576) (603:603:603)) + (PORT datad (1059:1059:1059) (1050:1050:1050)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|iff1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1549:1549:1549) (1530:1530:1530)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (344:344:344) (385:385:385)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) + (DELAY + (ABSOLUTE + (PORT datab (702:702:702) (756:756:756)) + (PORT datad (283:283:283) (377:377:377)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_inst4) + (INSTANCE z80_\|interrupts_\|iff1) (DELAY (ABSOLUTE - (PORT clk (1348:1348:1348) (1369:1369:1369)) + (PORT clk (1343:1343:1343) (1361:1361:1361)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1407:1407:1407) (1373:1373:1373)) - (PORT ena (745:745:745) (752:752:752)) + (PORT clrn (1121:1121:1121) (1096:1096:1096)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) + (DELAY + (ABSOLUTE + (PORT dataa (789:789:789) (784:784:784)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (1061:1061:1061) (1074:1074:1074)) + (PORT datad (1425:1425:1425) (1491:1491:1491)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|int_armed) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1366:1366:1366)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1384:1384:1384) (1363:1363:1363)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|DFFE_inst44) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT asdata (1708:1708:1708) (1760:1760:1760)) + (PORT clrn (1408:1408:1408) (1376:1376:1376)) + (PORT ena (906:906:906) (903:903:903)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|use_ixiy) + (INSTANCE z80_\|decode_state_\|in_halt\~0) (DELAY (ABSOLUTE - (PORT dataa (895:895:895) (970:970:970)) - (PORT datac (852:852:852) (909:909:909)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (311:311:311) (419:419:419)) + (PORT datab (264:264:264) (346:346:346)) + (PORT datad (230:230:230) (291:291:291)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~23) + (INSTANCE z80_\|pla_decode_\|Equal77\~1) (DELAY (ABSOLUTE - (PORT dataa (1100:1100:1100) (1111:1111:1111)) - (PORT datab (918:918:918) (981:981:981)) - (PORT datac (602:602:602) (641:641:641)) - (PORT datad (1150:1150:1150) (1209:1209:1209)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) + (PORT dataa (2142:2142:2142) (2198:2198:2198)) + (PORT datab (1137:1137:1137) (1160:1160:1160)) + (PORT datac (1062:1062:1062) (1070:1070:1070)) + (PORT datad (1130:1130:1130) (1115:1115:1115)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|in_halt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (224:224:224)) + (PORT datab (659:659:659) (652:652:652)) + (PORT datad (834:834:834) (839:839:839)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|in_halt) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1408:1408:1408) (1376:1376:1376)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1422:1422:1422) (1460:1460:1460)) + (PORT datab (590:590:590) (585:585:585)) + (PORT datac (1153:1153:1153) (1148:1148:1148)) + (PORT datad (584:584:584) (580:580:580)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~35) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (242:242:242)) + (PORT datab (199:199:199) (232:232:232)) + (PORT datac (550:550:550) (540:540:540)) + (PORT datad (179:179:179) (202:202:202)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (842:842:842)) + (PORT datab (591:591:591) (595:595:595)) + (PORT datac (776:776:776) (756:756:756)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (831:831:831) (838:838:838)) + (PORT datab (1336:1336:1336) (1385:1385:1385)) + (PORT datac (546:546:546) (575:575:575)) + (PORT datad (177:177:177) (198:198:198)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (645:645:645)) + (PORT datab (797:797:797) (791:791:791)) + (PORT datac (794:794:794) (806:806:806)) + (PORT datad (925:925:925) (960:960:960)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1040:1040:1040) (1071:1071:1071)) + (PORT datab (1139:1139:1139) (1153:1153:1153)) + (PORT datac (1205:1205:1205) (1221:1221:1221)) + (PORT datad (1815:1815:1815) (1832:1832:1832)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (794:794:794) (855:855:855)) + (PORT datab (1759:1759:1759) (1742:1742:1742)) + (PORT datac (1075:1075:1075) (1087:1087:1087)) + (PORT datad (771:771:771) (761:761:761)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~31) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (441:441:441)) + (PORT datab (948:948:948) (992:992:992)) + (PORT datac (1233:1233:1233) (1233:1233:1233)) + (PORT datad (992:992:992) (1011:1011:1011)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (221:221:221)) + (PORT datab (181:181:181) (212:212:212)) + (PORT datac (155:155:155) (184:184:184)) + (PORT datad (162:162:162) (188:188:188)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~37) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (612:612:612)) + (PORT datab (1357:1357:1357) (1359:1359:1359)) + (PORT datac (1372:1372:1372) (1413:1413:1413)) + (PORT datad (1500:1500:1500) (1528:1528:1528)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (580:580:580) (589:589:589)) + (PORT datab (194:194:194) (235:235:235)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~24) + (DELAY + (ABSOLUTE + (PORT dataa (2745:2745:2745) (2716:2716:2716)) + (PORT datab (588:588:588) (621:621:621)) + (PORT datac (561:561:561) (570:570:570)) + (PORT datad (196:196:196) (219:219:219)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~25) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (429:429:429)) + (PORT datab (816:816:816) (830:830:830)) + (PORT datac (1032:1032:1032) (1026:1026:1026)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (567:567:567)) + (PORT datab (597:597:597) (618:618:618)) + (PORT datac (170:170:170) (207:207:207)) + (PORT datad (1059:1059:1059) (1032:1032:1032)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1074:1074:1074) (1076:1076:1076)) + (PORT datab (851:851:851) (849:849:849)) + (PORT datac (170:170:170) (210:210:210)) + (PORT datad (1056:1056:1056) (1066:1066:1066)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (819:819:819)) + (PORT datab (1494:1494:1494) (1454:1454:1454)) + (PORT datac (1040:1040:1040) (1067:1067:1067)) + (PORT datad (1307:1307:1307) (1317:1317:1317)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (817:817:817) (812:812:812)) + (PORT datac (606:606:606) (617:617:617)) + (PORT datad (1083:1083:1083) (1091:1091:1091)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (831:831:831) (827:827:827)) + (PORT datab (1182:1182:1182) (1179:1179:1179)) + (PORT datac (606:606:606) (616:616:616)) + (PORT datad (1297:1297:1297) (1294:1294:1294)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1340:1340:1340) (1329:1329:1329)) + (PORT datab (1006:1006:1006) (1020:1020:1020)) + (PORT datac (607:607:607) (622:622:622)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (893:893:893)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (231:231:231)) + (PORT datab (607:607:607) (617:617:617)) + (PORT datac (572:572:572) (580:580:580)) + (PORT datad (579:579:579) (561:561:561)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -34376,120 +37006,10 @@ (INSTANCE z80_\|execute_\|fMRead\~34) (DELAY (ABSOLUTE - (PORT dataa (817:817:817) (821:821:821)) - (PORT datab (613:613:613) (611:611:611)) - (PORT datac (833:833:833) (862:862:862)) - (PORT datad (334:334:334) (344:344:344)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1087:1087:1087) (1094:1094:1094)) - (PORT datab (1490:1490:1490) (1461:1461:1461)) - (PORT datac (568:568:568) (582:582:582)) - (PORT datad (1010:1010:1010) (1002:1002:1002)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1158:1158:1158) (1204:1204:1204)) - (PORT datab (424:424:424) (464:464:464)) - (PORT datac (1567:1567:1567) (1577:1577:1577)) - (PORT datad (239:239:239) (288:288:288)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (397:397:397)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (998:998:998) (998:998:998)) - (PORT datad (184:184:184) (209:209:209)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1090:1090:1090) (1095:1095:1095)) - (PORT datab (533:533:533) (540:540:540)) - (PORT datac (1016:1016:1016) (1014:1014:1014)) - (PORT datad (295:295:295) (304:304:304)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (786:786:786) (800:800:800)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (542:542:542) (547:547:547)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (247:247:247)) - (PORT datab (598:598:598) (592:592:592)) - (PORT datac (175:175:175) (217:217:217)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (816:816:816) (820:820:820)) - (PORT datab (1037:1037:1037) (1034:1034:1034)) - (PORT datac (1298:1298:1298) (1314:1314:1314)) - (PORT datad (830:830:830) (865:865:865)) + (PORT dataa (1090:1090:1090) (1060:1060:1060)) + (PORT datab (883:883:883) (881:881:881)) + (PORT datac (561:561:561) (558:558:558)) + (PORT datad (160:160:160) (181:181:181)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -34499,253 +37019,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~10) + (INSTANCE z80_\|execute_\|fMRead\~36) (DELAY (ABSOLUTE - (PORT dataa (819:819:819) (816:816:816)) - (PORT datab (871:871:871) (884:884:884)) - (PORT datac (882:882:882) (920:920:920)) - (PORT datad (1026:1026:1026) (1026:1026:1026)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (818:818:818) (822:822:822)) - (PORT datab (806:806:806) (804:804:804)) - (PORT datac (1022:1022:1022) (1012:1012:1012)) - (PORT datad (307:307:307) (310:310:310)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1451:1451:1451) (1494:1494:1494)) - (PORT datab (188:188:188) (221:221:221)) - (PORT datac (1752:1752:1752) (1765:1765:1765)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1040:1040:1040) (1132:1132:1132)) - (PORT datab (922:922:922) (956:956:956)) - (PORT datac (1511:1511:1511) (1516:1516:1516)) - (PORT datad (1079:1079:1079) (1103:1103:1103)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1315:1315:1315) (1302:1302:1302)) - (PORT datab (1038:1038:1038) (1036:1036:1036)) - (PORT datac (967:967:967) (957:957:957)) - (PORT datad (309:309:309) (319:319:319)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (550:550:550) (538:538:538)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (580:580:580) (569:569:569)) - (PORT datab (965:965:965) (976:976:976)) - (PORT datac (533:533:533) (512:512:512)) - (PORT datad (553:553:553) (572:572:572)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~48) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (847:847:847)) - (PORT datab (1109:1109:1109) (1102:1102:1102)) - (PORT datac (1394:1394:1394) (1410:1410:1410)) - (PORT datad (622:622:622) (636:636:636)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1263:1263:1263) (1241:1241:1241)) - (PORT datab (792:792:792) (785:785:785)) - (PORT datac (992:992:992) (970:970:970)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (802:802:802) (854:854:854)) - (PORT datab (867:867:867) (916:916:916)) - (PORT datac (1446:1446:1446) (1424:1424:1424)) - (PORT datad (1118:1118:1118) (1102:1102:1102)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (808:808:808) (802:802:802)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (746:746:746) (736:736:736)) - (PORT datad (158:158:158) (180:180:180)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1902:1902:1902) (1935:1935:1935)) - (PORT datab (1116:1116:1116) (1117:1117:1117)) - (PORT datac (1048:1048:1048) (1072:1072:1072)) - (PORT datad (1067:1067:1067) (1091:1091:1091)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (2313:2313:2313) (2349:2349:2349)) - (PORT datab (542:542:542) (526:526:526)) - (PORT datac (175:175:175) (206:206:206)) - (PORT datad (911:911:911) (916:916:916)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1541:1541:1541) (1491:1491:1491)) - (PORT datab (770:770:770) (809:809:809)) - (PORT datac (953:953:953) (981:981:981)) - (PORT datad (712:712:712) (733:733:733)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~33) - (DELAY - (ABSOLUTE - (PORT dataa (961:961:961) (932:932:932)) - (PORT datab (182:182:182) (216:216:216)) - (PORT datac (761:761:761) (783:783:783)) - (PORT datad (158:158:158) (180:180:180)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~35) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (801:801:801)) - (PORT datab (182:182:182) (213:213:213)) - (PORT datac (758:758:758) (780:780:780)) - (PORT datad (177:177:177) (198:198:198)) + (PORT dataa (847:847:847) (865:865:865)) + (PORT datab (631:631:631) (624:624:624)) + (PORT datac (888:888:888) (889:889:889)) + (PORT datad (1014:1014:1014) (977:977:977)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -34758,1296 +37038,9 @@ (INSTANCE z80_\|pin_control_\|bus_db_pin_re) (DELAY (ABSOLUTE - (PORT datab (907:907:907) (921:921:921)) - (PORT datac (885:885:885) (921:921:921)) - (PORT datad (167:167:167) (191:191:191)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (935:935:935) (965:965:965)) - (PORT clk (1646:1646:1646) (1674:1674:1674)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1102:1102:1102) (1088:1088:1088)) - (PORT d[1] (2237:2237:2237) (2392:2392:2392)) - (PORT d[2] (1622:1622:1622) (1627:1627:1627)) - (PORT d[3] (936:936:936) (958:958:958)) - (PORT d[4] (2428:2428:2428) (2538:2538:2538)) - (PORT d[5] (3242:3242:3242) (3357:3357:3357)) - (PORT d[6] (950:950:950) (981:981:981)) - (PORT d[7] (2952:2952:2952) (3001:3001:3001)) - (PORT d[8] (1157:1157:1157) (1143:1143:1143)) - (PORT d[9] (950:950:950) (974:974:974)) - (PORT d[10] (1217:1217:1217) (1248:1248:1248)) - (PORT d[11] (2323:2323:2323) (2395:2395:2395)) - (PORT d[12] (1207:1207:1207) (1237:1237:1237)) - (PORT clk (1643:1643:1643) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (863:863:863) (813:813:813)) - (PORT clk (1643:1643:1643) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1674:1674:1674)) - (PORT d[0] (1543:1543:1543) (1494:1494:1494)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1638:1638:1638)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (659:659:659) (684:684:684)) - (PORT clk (1646:1646:1646) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (892:892:892) (908:908:908)) - (PORT d[1] (2746:2746:2746) (2901:2901:2901)) - (PORT d[2] (1143:1143:1143) (1158:1158:1158)) - (PORT d[3] (1198:1198:1198) (1236:1236:1236)) - (PORT d[4] (2401:2401:2401) (2505:2505:2505)) - (PORT d[5] (2764:2764:2764) (2904:2904:2904)) - (PORT d[6] (643:643:643) (644:644:644)) - (PORT d[7] (654:654:654) (659:659:659)) - (PORT d[8] (938:938:938) (949:949:949)) - (PORT d[9] (667:667:667) (672:672:672)) - (PORT d[10] (962:962:962) (987:987:987)) - (PORT d[11] (2364:2364:2364) (2465:2465:2465)) - (PORT d[12] (1168:1168:1168) (1176:1176:1176)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (885:885:885) (852:852:852)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1672:1672:1672)) - (PORT d[0] (1900:1900:1900) (1848:1848:1848)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1636:1636:1636)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (883:883:883)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (670:670:670)) - (PORT datab (626:626:626) (667:667:667)) - (PORT datac (735:735:735) (706:706:706)) - (PORT datad (796:796:796) (797:797:797)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (651:651:651) (672:672:672)) - (PORT clk (1646:1646:1646) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2935:2935:2935) (2963:2963:2963)) - (PORT d[1] (2718:2718:2718) (2863:2863:2863)) - (PORT d[2] (893:893:893) (888:888:888)) - (PORT d[3] (1235:1235:1235) (1270:1270:1270)) - (PORT d[4] (2431:2431:2431) (2549:2549:2549)) - (PORT d[5] (2464:2464:2464) (2593:2593:2593)) - (PORT d[6] (888:888:888) (891:891:891)) - (PORT d[7] (1176:1176:1176) (1191:1191:1191)) - (PORT d[8] (1345:1345:1345) (1346:1346:1346)) - (PORT d[9] (900:900:900) (906:906:906)) - (PORT d[10] (956:956:956) (956:956:956)) - (PORT d[11] (2665:2665:2665) (2768:2768:2768)) - (PORT d[12] (895:895:895) (910:910:910)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1141:1141:1141) (1101:1101:1101)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1672:1672:1672)) - (PORT d[0] (1845:1845:1845) (1794:1794:1794)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1636:1636:1636)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (883:883:883)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (692:692:692) (704:704:704)) - (PORT clk (1645:1645:1645) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2955:2955:2955) (2983:2983:2983)) - (PORT d[1] (2482:2482:2482) (2633:2633:2633)) - (PORT d[2] (1195:1195:1195) (1176:1176:1176)) - (PORT d[3] (1239:1239:1239) (1274:1274:1274)) - (PORT d[4] (2434:2434:2434) (2550:2550:2550)) - (PORT d[5] (2483:2483:2483) (2619:2619:2619)) - (PORT d[6] (1142:1142:1142) (1146:1146:1146)) - (PORT d[7] (1054:1054:1054) (1040:1040:1040)) - (PORT d[8] (1372:1372:1372) (1377:1377:1377)) - (PORT d[9] (1432:1432:1432) (1452:1452:1452)) - (PORT d[10] (675:675:675) (689:689:689)) - (PORT d[11] (2649:2649:2649) (2760:2760:2760)) - (PORT d[12] (899:899:899) (923:923:923)) - (PORT clk (1642:1642:1642) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1127:1127:1127) (1106:1106:1106)) - (PORT clk (1642:1642:1642) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1672:1672:1672)) - (PORT d[0] (1644:1644:1644) (1629:1629:1629)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1636:1636:1636)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (883:883:883)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1145:1145:1145) (1184:1184:1184)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (893:893:893) (908:908:908)) - (PORT datad (1017:1017:1017) (1005:1005:1005)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (695:695:695) (707:707:707)) - (PORT clk (1639:1639:1639) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2694:2694:2694) (2715:2715:2715)) - (PORT d[1] (2202:2202:2202) (2342:2342:2342)) - (PORT d[2] (1461:1461:1461) (1446:1446:1446)) - (PORT d[3] (1823:1823:1823) (1876:1876:1876)) - (PORT d[4] (2718:2718:2718) (2847:2847:2847)) - (PORT d[5] (2496:2496:2496) (2625:2625:2625)) - (PORT d[6] (1171:1171:1171) (1200:1200:1200)) - (PORT d[7] (1210:1210:1210) (1238:1238:1238)) - (PORT d[8] (1623:1623:1623) (1628:1628:1628)) - (PORT d[9] (1439:1439:1439) (1440:1440:1440)) - (PORT d[10] (2000:2000:2000) (2046:2046:2046)) - (PORT d[11] (3000:3000:3000) (3059:3059:3059)) - (PORT d[12] (1185:1185:1185) (1206:1206:1206)) - (PORT clk (1636:1636:1636) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2714:2714:2714) (2633:2633:2633)) - (PORT clk (1636:1636:1636) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1665:1665:1665)) - (PORT d[0] (2818:2818:2818) (2820:2820:2820)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1598:1598:1598) (1595:1595:1595)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1970:1970:1970) (1951:1951:1951)) - (PORT clk (1606:1606:1606) (1602:1602:1602)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4076:4076:4076) (3965:3965:3965)) - (PORT d[1] (3875:3875:3875) (3743:3743:3743)) - (PORT d[2] (3989:3989:3989) (3887:3887:3887)) - (PORT d[3] (4083:4083:4083) (3937:3937:3937)) - (PORT d[4] (4070:4070:4070) (3924:3924:3924)) - (PORT d[5] (4108:4108:4108) (3942:3942:3942)) - (PORT d[6] (4311:4311:4311) (4264:4264:4264)) - (PORT d[7] (4148:4148:4148) (3989:3989:3989)) - (PORT d[8] (4132:4132:4132) (3981:3981:3981)) - (PORT d[9] (4173:4173:4173) (4216:4216:4216)) - (PORT d[10] (4116:4116:4116) (4015:4015:4015)) - (PORT d[11] (4192:4192:4192) (4103:4103:4103)) - (PORT d[12] (4115:4115:4115) (4104:4104:4104)) - (PORT clk (1603:1603:1603) (1599:1599:1599)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1602:1602:1602)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1603:1603:1603)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1603:1603:1603)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1603:1603:1603)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1603:1603:1603)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2389:2389:2389) (2383:2383:2383)) - (PORT d[1] (1886:1886:1886) (1981:1981:1981)) - (PORT d[2] (2142:2142:2142) (2224:2224:2224)) - (PORT d[3] (2338:2338:2338) (2394:2394:2394)) - (PORT d[4] (2742:2742:2742) (2871:2871:2871)) - (PORT d[5] (2111:2111:2111) (2197:2197:2197)) - (PORT d[6] (1722:1722:1722) (1770:1770:1770)) - (PORT d[7] (2347:2347:2347) (2335:2335:2335)) - (PORT d[8] (2572:2572:2572) (2670:2670:2670)) - (PORT d[9] (1628:1628:1628) (1651:1651:1651)) - (PORT d[10] (1407:1407:1407) (1425:1425:1425)) - (PORT d[11] (3201:3201:3201) (3238:3238:3238)) - (PORT d[12] (1429:1429:1429) (1464:1464:1464)) - (PORT clk (1654:1654:1654) (1681:1681:1681)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1654:1654:1654) (1681:1681:1681)) - (PORT d[0] (2025:2025:2025) (2024:2024:2024)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1655:1655:1655) (1682:1682:1682)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1621:1621:1621) (1647:1647:1647)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (892:892:892) (894:894:894)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (893:893:893) (895:895:895)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (893:893:893) (895:895:895)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (893:893:893) (895:895:895)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1399:1399:1399) (1397:1397:1397)) - (PORT d[1] (2487:2487:2487) (2630:2630:2630)) - (PORT d[2] (915:915:915) (928:928:928)) - (PORT d[3] (1548:1548:1548) (1584:1584:1584)) - (PORT d[4] (2415:2415:2415) (2530:2530:2530)) - (PORT d[5] (2516:2516:2516) (2652:2652:2652)) - (PORT d[6] (901:901:901) (917:917:917)) - (PORT d[7] (894:894:894) (904:904:904)) - (PORT d[8] (1329:1329:1329) (1335:1335:1335)) - (PORT d[9] (1448:1448:1448) (1474:1474:1474)) - (PORT d[10] (2291:2291:2291) (2346:2346:2346)) - (PORT d[11] (2678:2678:2678) (2795:2795:2795)) - (PORT d[12] (1175:1175:1175) (1180:1180:1180)) - (PORT clk (1641:1641:1641) (1669:1669:1669)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (PORT d[0] (779:779:779) (793:793:793)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1608:1608:1608) (1635:1635:1635)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (883:883:883)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (883:883:883)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (883:883:883)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (865:865:865) (830:830:830)) - (PORT clk (1642:1642:1642) (1669:1669:1669)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2940:2940:2940) (2959:2959:2959)) - (PORT d[1] (2474:2474:2474) (2624:2624:2624)) - (PORT d[2] (1461:1461:1461) (1436:1436:1436)) - (PORT d[3] (1564:1564:1564) (1602:1602:1602)) - (PORT d[4] (2707:2707:2707) (2850:2850:2850)) - (PORT d[5] (2515:2515:2515) (2652:2652:2652)) - (PORT d[6] (902:902:902) (918:918:918)) - (PORT d[7] (1429:1429:1429) (1432:1432:1432)) - (PORT d[8] (2832:2832:2832) (2949:2949:2949)) - (PORT d[9] (924:924:924) (939:939:939)) - (PORT d[10] (2294:2294:2294) (2352:2352:2352)) - (PORT d[11] (2654:2654:2654) (2768:2768:2768)) - (PORT d[12] (2065:2065:2065) (2107:2107:2107)) - (PORT clk (1639:1639:1639) (1667:1667:1667)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2843:2843:2843) (2788:2788:2788)) - (PORT clk (1639:1639:1639) (1667:1667:1667)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1669:1669:1669)) - (PORT d[0] (1605:1605:1605) (1615:1615:1615)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1601:1601:1601) (1599:1599:1599)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2235:2235:2235) (2216:2216:2216)) - (PORT clk (1609:1609:1609) (1606:1606:1606)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4297:4297:4297) (4178:4178:4178)) - (PORT d[1] (3968:3968:3968) (3900:3900:3900)) - (PORT d[2] (3965:3965:3965) (3856:3856:3856)) - (PORT d[3] (4092:4092:4092) (3987:3987:3987)) - (PORT d[4] (4044:4044:4044) (3897:3897:3897)) - (PORT d[5] (4223:4223:4223) (4114:4114:4114)) - (PORT d[6] (4401:4401:4401) (4356:4356:4356)) - (PORT d[7] (4190:4190:4190) (4089:4089:4089)) - (PORT d[8] (4127:4127:4127) (3976:3976:3976)) - (PORT d[9] (4184:4184:4184) (4235:4235:4235)) - (PORT d[10] (4172:4172:4172) (4085:4085:4085)) - (PORT d[11] (4109:4109:4109) (3983:3983:3983)) - (PORT d[12] (4090:4090:4090) (3988:3988:3988)) - (PORT clk (1606:1606:1606) (1603:1603:1603)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1606:1606:1606)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1607:1607:1607)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1607:1607:1607)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1607:1607:1607)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1607:1607:1607)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1600:1600:1600)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (651:651:651)) - (PORT datab (1099:1099:1099) (1121:1121:1121)) - (PORT datac (777:777:777) (756:756:756)) - (PORT datad (820:820:820) (810:810:810)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1108:1108:1108) (1094:1094:1094)) - (PORT datab (1099:1099:1099) (1121:1121:1121)) - (PORT datac (1392:1392:1392) (1407:1407:1407)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) + (PORT datab (1364:1364:1364) (1398:1398:1398)) + (PORT datac (939:939:939) (914:914:914)) + (PORT datad (475:475:475) (463:463:463)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -36056,937 +37049,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~103) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~103) (DELAY (ABSOLUTE - (PORT dataa (1626:1626:1626) (1633:1633:1633)) - (PORT datab (1300:1300:1300) (1339:1339:1339)) - (PORT datac (595:595:595) (621:621:621)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_DAT\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (459:459:459) (708:708:708)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE reset\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (768:768:768) (767:767:767)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) - (DELAY - (ABSOLUTE - (PORT dataa (256:256:256) (347:347:347)) - (PORT datab (261:261:261) (345:345:345)) - (PORT datad (220:220:220) (289:289:289)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_CLK\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (459:459:459) (708:708:708)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (2920:2920:2920) (3165:3165:3165)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1334:1334:1334) (1352:1352:1352)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1368:1368:1368)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (204:204:204) (265:265:265)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1334:1334:1334) (1352:1352:1352)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1368:1368:1368)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (208:208:208) (270:270:270)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1334:1334:1334) (1352:1352:1352)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1368:1368:1368)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (218:218:218) (276:276:276)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1334:1334:1334) (1352:1352:1352)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1368:1368:1368)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (305:305:305)) - (PORT datab (229:229:229) (299:299:299)) - (PORT datac (352:352:352) (390:390:390)) - (PORT datad (206:206:206) (266:266:266)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (207:207:207) (267:267:267)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1334:1334:1334) (1352:1352:1352)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1368:1368:1368)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (208:208:208) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1334:1334:1334) (1352:1352:1352)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1368:1368:1368)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (204:204:204) (266:266:266)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1334:1334:1334) (1352:1352:1352)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1368:1368:1368)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (222:222:222)) - (PORT datab (230:230:230) (301:301:301)) - (PORT datac (203:203:203) (273:273:273)) - (PORT datad (207:207:207) (267:267:267)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (204:204:204) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1334:1334:1334) (1352:1352:1352)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1368:1368:1368)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) - (DELAY - (ABSOLUTE - (PORT datab (189:189:189) (225:225:225)) - (PORT datad (207:207:207) (267:267:267)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) - (DELAY - (ABSOLUTE - (PORT clk (1334:1334:1334) (1352:1352:1352)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1368:1368:1368)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) - (DELAY - (ABSOLUTE - (PORT datab (189:189:189) (226:226:226)) - (PORT datac (197:197:197) (265:265:265)) - (PORT datad (204:204:204) (263:263:263)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge) - (DELAY - (ABSOLUTE - (PORT clk (1334:1334:1334) (1352:1352:1352)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1368:1368:1368)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1361:1361:1361)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1388:1388:1388) (1369:1369:1369)) - (PORT ena (1851:1851:1851) (1843:1843:1843)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) - (DELAY - (ABSOLUTE - (PORT dataa (257:257:257) (347:347:347)) - (PORT datab (261:261:261) (345:345:345)) - (PORT datad (217:217:217) (282:282:282)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1361:1361:1361)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1388:1388:1388) (1369:1369:1369)) - (PORT ena (1851:1851:1851) (1843:1843:1843)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (343:343:343)) - (PORT datab (252:252:252) (332:332:332)) - (PORT datad (220:220:220) (286:286:286)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1361:1361:1361)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1388:1388:1388) (1369:1369:1369)) - (PORT ena (1851:1851:1851) (1843:1843:1843)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (424:424:424)) - (PORT datab (253:253:253) (334:334:334)) - (PORT datad (220:220:220) (287:287:287)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1361:1361:1361)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1388:1388:1388) (1369:1369:1369)) - (PORT ena (1851:1851:1851) (1843:1843:1843)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|always1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (250:250:250) (338:338:338)) - (PORT datab (257:257:257) (338:338:338)) - (PORT datac (2974:2974:2974) (3250:3250:3250)) - (PORT datad (226:226:226) (296:296:296)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT datab (259:259:259) (343:343:343)) - (PORT datac (225:225:225) (310:310:310)) - (PORT datad (223:223:223) (292:292:292)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (222:222:222)) - (PORT datab (241:241:241) (316:316:316)) - (PORT datac (1265:1265:1265) (1274:1274:1274)) - (PORT datad (167:167:167) (191:191:191)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT asdata (3472:3472:3472) (3720:3720:3720)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (PORT ena (1120:1120:1120) (1082:1082:1082)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT asdata (506:506:506) (568:568:568)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (PORT ena (1120:1120:1120) (1082:1082:1082)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT asdata (540:540:540) (613:613:613)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (PORT ena (1120:1120:1120) (1082:1082:1082)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT asdata (530:530:530) (596:596:596)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (PORT ena (1120:1120:1120) (1082:1082:1082)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT asdata (875:875:875) (902:902:902)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (PORT ena (1102:1102:1102) (1092:1092:1092)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT asdata (887:887:887) (901:901:901)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (PORT ena (1120:1120:1120) (1082:1082:1082)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT asdata (872:872:872) (902:902:902)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (PORT ena (1102:1102:1102) (1092:1092:1092)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT asdata (694:694:694) (750:750:750)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (PORT ena (1102:1102:1102) (1092:1092:1092)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT asdata (705:705:705) (769:769:769)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (PORT ena (1102:1102:1102) (1092:1092:1092)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (909:909:909) (948:948:948)) - (PORT datab (620:620:620) (670:670:670)) - (PORT datac (696:696:696) (773:773:773)) - (PORT datad (707:707:707) (791:791:791)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1301:1301:1301) (1379:1379:1379)) - (PORT datab (856:856:856) (908:908:908)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (703:703:703) (782:782:782)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|extended\~0) - (DELAY - (ABSOLUTE - (PORT datab (980:980:980) (1034:1034:1034)) - (PORT datad (732:732:732) (716:716:716)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (644:644:644)) - (PORT datab (259:259:259) (336:336:336)) - (PORT datad (770:770:770) (786:786:786)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (670:670:670) (726:726:726)) - (PORT datab (617:617:617) (658:658:658)) - (PORT datac (597:597:597) (631:631:631)) - (PORT datad (407:407:407) (451:451:451)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) - (DELAY - (ABSOLUTE - (PORT datab (621:621:621) (646:646:646)) - (PORT datac (323:323:323) (326:326:326)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (230:230:230)) - (PORT datab (2992:2992:2992) (3284:3284:3284)) - (PORT datac (1265:1265:1265) (1274:1274:1274)) - (PORT datad (335:335:335) (348:348:348)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1361:1361:1361)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1388:1388:1388) (1369:1369:1369)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|extended) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) - (PORT ena (1618:1618:1618) (1613:1613:1613)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (660:660:660)) - (PORT datab (620:620:620) (628:628:628)) - (PORT datac (231:231:231) (309:309:309)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (445:445:445) (495:495:495)) - (PORT datac (1250:1250:1250) (1305:1305:1305)) - (PORT datad (782:782:782) (772:772:772)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1087:1087:1087) (1146:1146:1146)) - (PORT datac (586:586:586) (609:609:609)) - (PORT datad (837:837:837) (881:881:881)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~0) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (385:385:385)) - (PORT datac (565:565:565) (594:594:594)) - (PORT datad (673:673:673) (704:704:704)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|released\~0) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (648:648:648)) - (PORT datab (618:618:618) (630:630:630)) - (PORT datad (1230:1230:1230) (1225:1225:1225)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|released) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) - (DELAY - (ABSOLUTE - (PORT dataa (435:435:435) (500:500:500)) - (PORT datab (607:607:607) (656:656:656)) - (PORT datac (560:560:560) (597:597:597)) - (PORT datad (236:236:236) (299:299:299)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~2) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (223:223:223)) - (PORT datac (382:382:382) (444:444:444)) - (PORT datad (605:605:605) (640:640:640)) + (PORT dataa (449:449:449) (513:513:513)) + (PORT datac (901:901:901) (943:943:943)) + (PORT datad (573:573:573) (610:610:610)) (IOPATH dataa combout (272:272:272) (269:269:269)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -36995,12 +37063,40 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~3) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~20) (DELAY (ABSOLUTE - (PORT dataa (553:553:553) (547:547:547)) - (PORT datab (394:394:394) (454:454:454)) - (PORT datad (159:159:159) (180:180:180)) + (PORT datab (702:702:702) (768:768:768)) + (PORT datac (617:617:617) (646:646:646)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (389:389:389)) + (PORT datab (709:709:709) (764:764:764)) + (PORT datac (639:639:639) (677:677:677)) + (PORT datad (175:175:175) (206:206:206)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) + (DELAY + (ABSOLUTE + (PORT dataa (718:718:718) (777:777:777)) + (PORT datab (183:183:183) (215:215:215)) + (PORT datad (557:557:557) (552:552:552)) (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -37010,12 +37106,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|shifted) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1331:1331:1331) (1348:1348:1348)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) + (PORT clrn (1365:1365:1365) (1346:1346:1346)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -37026,250 +37122,182 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~73) (DELAY (ABSOLUTE - (PORT dataa (683:683:683) (747:747:747)) - (PORT datab (911:911:911) (954:954:954)) - (PORT datad (887:887:887) (928:928:928)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (679:679:679) (731:731:731)) + (PORT datac (866:866:866) (909:909:909)) + (PORT datad (840:840:840) (866:866:866)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) + (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) (DELAY (ABSOLUTE - (PORT datab (690:690:690) (758:758:758)) - (PORT datac (684:684:684) (751:751:751)) - (PORT datad (679:679:679) (744:744:744)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (713:713:713) (796:796:796)) + (PORT datab (602:602:602) (618:618:618)) + (PORT datac (835:835:835) (881:881:881)) + (PORT datad (242:242:242) (307:307:307)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (255:255:255) (334:334:334)) + (PORT datab (862:862:862) (916:916:916)) + (PORT datac (855:855:855) (893:893:893)) + (PORT datad (688:688:688) (762:762:762)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~129) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (910:910:910)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~1) + (DELAY + (ABSOLUTE + (PORT datab (717:717:717) (789:789:789)) + (PORT datac (631:631:631) (671:671:671)) + (PORT datad (678:678:678) (742:742:742)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~105) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (365:365:365)) + (PORT datab (671:671:671) (714:714:714)) + (PORT datac (825:825:825) (860:860:860)) + (PORT datad (181:181:181) (212:212:212)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (357:357:357)) + (PORT datab (584:584:584) (608:608:608)) + (PORT datac (615:615:615) (643:643:643)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~130) + (DELAY + (ABSOLUTE + (PORT dataa (720:720:720) (777:777:777)) + (PORT datab (380:380:380) (440:440:440)) + (PORT datad (864:864:864) (897:897:897)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) + (DELAY + (ABSOLUTE + (PORT dataa (1122:1122:1122) (1110:1110:1110)) + (PORT datab (587:587:587) (589:589:589)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1365:1365:1365) (1346:1346:1346)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (1167:1167:1167) (1206:1206:1206)) + (PORT datab (221:221:221) (290:290:290)) + (PORT datac (818:818:818) (814:814:814)) + (PORT datad (197:197:197) (254:254:254)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~39) (DELAY (ABSOLUTE - (PORT dataa (328:328:328) (348:348:348)) - (PORT datab (185:185:185) (218:218:218)) - (PORT datad (161:161:161) (183:183:183)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT datab (884:884:884) (934:934:934)) - (PORT datad (679:679:679) (743:743:743)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (741:741:741)) - (PORT datab (259:259:259) (336:336:336)) - (PORT datac (596:596:596) (634:634:634)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~32) - (DELAY - (ABSOLUTE - (PORT datab (608:608:608) (641:641:641)) - (PORT datac (367:367:367) (415:415:415)) - (PORT datad (604:604:604) (638:638:638)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (371:371:371)) - (PORT datab (201:201:201) (243:243:243)) - (PORT datac (599:599:599) (634:634:634)) - (PORT datad (402:402:402) (446:446:446)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (205:205:205) (243:243:243)) - (PORT datab (574:574:574) (597:597:597)) - (PORT datad (887:887:887) (926:926:926)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1075:1075:1075) (1096:1096:1096)) - (PORT datab (220:220:220) (287:287:287)) - (PORT datac (195:195:195) (261:261:261)) - (PORT datad (511:511:511) (509:509:509)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (924:924:924)) - (PORT datac (825:825:825) (873:873:873)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1298:1298:1298) (1375:1375:1375)) - (PORT datab (636:636:636) (660:660:660)) - (PORT datac (882:882:882) (922:922:922)) - (PORT datad (171:171:171) (202:202:202)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT datab (909:909:909) (952:952:952)) - (PORT datac (663:663:663) (734:734:734)) - (PORT datad (679:679:679) (745:745:745)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (815:815:815)) - (PORT datab (615:615:615) (612:612:612)) - (PORT datad (468:468:468) (456:456:456)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1293:1293:1293) (1369:1369:1369)) - (PORT datab (194:194:194) (232:232:232)) - (PORT datac (608:608:608) (629:629:629)) - (PORT datad (706:706:706) (778:778:778)) + (PORT dataa (958:958:958) (1007:1007:1007)) + (PORT datac (781:781:781) (782:782:782)) + (PORT datad (655:655:655) (697:697:697)) (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -37277,57 +37305,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~26) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~100) (DELAY (ABSOLUTE - (PORT dataa (664:664:664) (731:731:731)) - (PORT datab (331:331:331) (353:353:353)) - (PORT datac (658:658:658) (726:726:726)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1436:1436:1436) (1485:1485:1485)) - (PORT datab (909:909:909) (926:926:926)) - (PORT datad (485:485:485) (469:469:469)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT datab (684:684:684) (746:746:746)) + (PORT datac (1149:1149:1149) (1189:1189:1189)) + (PORT datad (888:888:888) (929:929:929)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~0) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) (DELAY (ABSOLUTE - (PORT datab (1374:1374:1374) (1416:1416:1416)) - (PORT datac (846:846:846) (881:881:881)) - (PORT datad (198:198:198) (255:255:255)) + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (961:961:961) (1016:1016:1016)) + (PORT datac (689:689:689) (759:759:759)) + (PORT datad (172:172:172) (201:201:201)) + (IOPATH dataa combout (272:272:272) (269:269:269)) (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -37336,12 +37335,104 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~99) (DELAY (ABSOLUTE - (PORT datab (391:391:391) (450:450:450)) - (PORT datac (1029:1029:1029) (1039:1039:1039)) - (PORT datad (605:605:605) (641:641:641)) + (PORT dataa (713:713:713) (752:752:752)) + (PORT datac (900:900:900) (943:943:943)) + (PORT datad (600:600:600) (629:629:629)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (851:851:851)) + (PORT datab (826:826:826) (821:821:821)) + (PORT datad (161:161:161) (181:181:181)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1372:1372:1372) (1351:1351:1351)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~97) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (355:355:355)) + (PORT datab (961:961:961) (1016:1016:1016)) + (PORT datac (644:644:644) (687:687:687)) + (PORT datad (173:173:173) (200:200:200)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~98) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (972:972:972)) + (PORT datab (859:859:859) (854:854:854)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1372:1372:1372) (1351:1351:1351)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (1098:1098:1098) (1088:1088:1088)) + (PORT datab (654:654:654) (692:692:692)) + (PORT datac (194:194:194) (261:261:261)) + (PORT datad (197:197:197) (254:254:254)) + (IOPATH dataa combout (272:272:272) (269:269:269)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -37350,927 +37441,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~16) + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~108) (DELAY (ABSOLUTE - (PORT dataa (651:651:651) (689:689:689)) - (PORT datab (375:375:375) (438:438:438)) - (PORT datac (562:562:562) (598:598:598)) - (PORT datad (238:238:238) (303:303:303)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (436:436:436) (502:502:502)) - (PORT datab (608:608:608) (658:658:658)) - (PORT datac (463:463:463) (456:456:456)) - (PORT datad (609:609:609) (642:642:642)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (553:553:553) (546:546:546)) - (PORT datab (183:183:183) (215:215:215)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (680:680:680)) - (PORT datab (1141:1141:1141) (1156:1156:1156)) - (PORT datac (403:403:403) (453:453:453)) - (PORT datad (985:985:985) (970:970:970)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (749:749:749)) - (PORT datab (1279:1279:1279) (1336:1336:1336)) - (PORT datac (842:842:842) (874:874:874)) - (PORT datad (796:796:796) (814:814:814)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (254:254:254)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datac (678:678:678) (745:745:745)) - (PORT datad (1423:1423:1423) (1456:1456:1456)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (491:491:491) (476:476:476)) - (PORT datad (870:870:870) (892:892:892)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (649:649:649)) - (PORT datab (1042:1042:1042) (1062:1062:1062)) - (PORT datac (587:587:587) (615:615:615)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (676:676:676)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (176:176:176) (208:208:208)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (443:443:443) (492:492:492)) - (PORT datab (1139:1139:1139) (1158:1158:1158)) - (PORT datac (680:680:680) (750:750:750)) - (PORT datad (782:782:782) (771:771:771)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (704:704:704) (774:774:774)) - (PORT datab (835:835:835) (872:872:872)) - (PORT datac (1026:1026:1026) (1029:1029:1029)) - (PORT datad (652:652:652) (707:707:707)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (285:285:285)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (354:354:354)) - (PORT datac (641:641:641) (699:699:699)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (722:722:722) (779:779:779)) - (PORT datab (834:834:834) (870:870:870)) - (PORT datac (606:606:606) (657:657:657)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datad (162:162:162) (183:183:183)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (586:586:586) (628:628:628)) - (PORT datab (450:450:450) (517:517:517)) - (PORT datac (368:368:368) (413:413:413)) - (PORT datad (563:563:563) (566:566:566)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) - (DELAY - (ABSOLUTE - (PORT dataa (755:755:755) (835:835:835)) - (PORT datab (859:859:859) (909:909:909)) - (PORT datac (697:697:697) (774:774:774)) - (PORT datad (704:704:704) (777:777:777)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) - (DELAY - (ABSOLUTE - (PORT dataa (751:751:751) (830:830:830)) - (PORT datab (724:724:724) (796:796:796)) - (PORT datad (703:703:703) (783:783:783)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) - (DELAY - (ABSOLUTE - (PORT dataa (753:753:753) (833:833:833)) - (PORT datab (856:856:856) (908:908:908)) - (PORT datac (696:696:696) (771:771:771)) - (PORT datad (703:703:703) (782:782:782)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~7) - (DELAY - (ABSOLUTE - (PORT dataa (211:211:211) (251:251:251)) - (PORT datab (860:860:860) (910:910:910)) - (PORT datac (294:294:294) (304:304:304)) - (PORT datad (1278:1278:1278) (1340:1340:1340)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1302:1302:1302) (1381:1381:1381)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (858:858:858) (889:889:889)) - (PORT datad (486:486:486) (471:471:471)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (358:358:358)) - (PORT datab (248:248:248) (320:320:320)) - (PORT datad (555:555:555) (562:562:562)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1286:1286:1286) (1286:1286:1286)) - (PORT datab (382:382:382) (420:420:420)) - (PORT datac (1267:1267:1267) (1269:1269:1269)) - (PORT datad (539:539:539) (559:559:559)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (723:723:723)) - (PORT datab (3109:3109:3109) (3117:3117:3117)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1571:1571:1571) (1565:1565:1565)) - (PORT datab (1140:1140:1140) (1173:1173:1173)) - (PORT datac (587:587:587) (604:604:604)) - (PORT datad (1059:1059:1059) (1058:1058:1058)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1399:1399:1399) (1419:1419:1419)) - (PORT datab (1141:1141:1141) (1174:1174:1174)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (1149:1149:1149) (1213:1213:1213)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (945:945:945)) - (PORT datab (598:598:598) (605:605:605)) - (PORT datac (212:212:212) (262:262:262)) - (PORT datad (1541:1541:1541) (1544:1544:1544)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT datab (846:846:846) (848:848:848)) - (PORT datac (872:872:872) (898:898:898)) - (PORT datad (200:200:200) (230:230:230)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (279:279:279)) - (PORT datab (656:656:656) (683:683:683)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (188:188:188) (217:217:217)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|ir_\|opcode\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (178:178:178) (199:199:199)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1395:1395:1395) (1367:1367:1367)) - (PORT ena (1130:1130:1130) (1103:1103:1103)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (257:257:257) (345:345:345)) - (PORT datac (836:836:836) (862:862:862)) - (PORT datad (853:853:853) (877:877:877)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1308:1308:1308) (1362:1362:1362)) - (PORT datab (817:817:817) (820:820:820)) - (PORT datac (843:843:843) (887:887:887)) - (PORT datad (792:792:792) (800:800:800)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1453:1453:1453) (1518:1518:1518)) - (PORT datab (2173:2173:2173) (2172:2172:2172)) - (PORT datac (613:613:613) (644:644:644)) - (PORT datad (2549:2549:2549) (2541:2541:2541)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (228:228:228)) - (PORT datab (207:207:207) (255:255:255)) - (PORT datac (174:174:174) (213:213:213)) - (PORT datad (348:348:348) (354:354:354)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (576:576:576)) - (PORT datab (395:395:395) (417:417:417)) - (PORT datac (511:511:511) (505:505:505)) - (PORT datad (1080:1080:1080) (1089:1089:1089)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1376:1376:1376) (1411:1411:1411)) - (PORT datab (409:409:409) (421:421:421)) - (PORT datac (858:858:858) (881:881:881)) - (PORT datad (191:191:191) (220:220:220)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) - (DELAY - (ABSOLUTE - (PORT dataa (897:897:897) (927:927:927)) - (PORT datab (1034:1034:1034) (1042:1042:1042)) - (PORT datac (1148:1148:1148) (1192:1192:1192)) - (PORT datad (1252:1252:1252) (1251:1251:1251)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1017:1017:1017) (1011:1011:1011)) - (PORT datab (888:888:888) (937:937:937)) - (PORT datac (1150:1150:1150) (1193:1193:1193)) - (PORT datad (1112:1112:1112) (1148:1148:1148)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1399:1399:1399) (1353:1353:1353)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (796:796:796) (768:768:768)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1484:1484:1484) (1470:1470:1470)) - (PORT datab (771:771:771) (770:770:770)) - (PORT datad (963:963:963) (922:922:922)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1446:1446:1446) (1433:1433:1433)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (596:596:596) (611:611:611)) - (PORT datad (514:514:514) (514:514:514)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) - (DELAY - (ABSOLUTE - (PORT dataa (576:576:576) (594:594:594)) - (PORT datab (519:519:519) (506:506:506)) - (PORT datac (175:175:175) (207:207:207)) - (PORT datad (349:349:349) (349:349:349)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~21) - (DELAY - (ABSOLUTE - (PORT dataa (2085:2085:2085) (2088:2088:2088)) - (PORT datab (1436:1436:1436) (1471:1471:1471)) - (PORT datac (826:826:826) (842:842:842)) - (PORT datad (1068:1068:1068) (1049:1049:1049)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) - (DELAY - (ABSOLUTE - (PORT datab (205:205:205) (250:250:250)) - (PORT datac (317:317:317) (325:325:325)) - (PORT datad (346:346:346) (349:349:349)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1228:1228:1228)) - (PORT datab (862:862:862) (890:890:890)) - (PORT datac (1793:1793:1793) (1848:1848:1848)) - (PORT datad (1891:1891:1891) (1998:1998:1998)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) - (DELAY - (ABSOLUTE - (PORT dataa (793:793:793) (807:807:807)) - (PORT datab (206:206:206) (250:250:250)) - (PORT datac (175:175:175) (215:215:215)) - (PORT datad (347:347:347) (349:349:349)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1074:1074:1074) (1056:1056:1056)) - (PORT datab (181:181:181) (215:215:215)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (231:231:231)) - (PORT datab (199:199:199) (241:241:241)) - (PORT datac (180:180:180) (213:213:213)) - (PORT datad (202:202:202) (226:226:226)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1784:1784:1784) (1819:1819:1819)) - (PORT datab (2405:2405:2405) (2428:2428:2428)) - (PORT datad (1328:1328:1328) (1372:1372:1372)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (643:643:643)) - (PORT datab (640:640:640) (670:670:670)) - (PORT datac (1015:1015:1015) (996:996:996)) - (PORT datad (595:595:595) (619:619:619)) + (PORT dataa (1138:1138:1138) (1164:1164:1164)) + (PORT datac (908:908:908) (937:937:937)) + (PORT datad (605:605:605) (637:637:637)) (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (229:229:229)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (567:567:567) (559:559:559)) - (PORT datad (727:727:727) (716:716:716)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) - (DELAY - (ABSOLUTE - (PORT dataa (788:788:788) (790:790:790)) - (PORT datab (309:309:309) (327:327:327)) - (PORT datac (348:348:348) (352:352:352)) - (PORT datad (565:565:565) (566:566:566)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1673:1673:1673) (1700:1700:1700)) - (PORT datab (850:850:850) (888:888:888)) - (PORT datac (842:842:842) (887:887:887)) - (PORT datad (395:395:395) (415:415:415)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (857:857:857) (859:859:859)) - (PORT datac (837:837:837) (829:829:829)) - (PORT datad (1282:1282:1282) (1295:1295:1295)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (399:399:399)) - (PORT datac (173:173:173) (204:204:204)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -38278,30 +37455,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~109) (DELAY (ABSOLUTE - (PORT dataa (1072:1072:1072) (1102:1102:1102)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (554:554:554) (559:559:559)) - (PORT datad (340:340:340) (356:356:356)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (191:191:191) (230:230:230)) + (PORT datab (209:209:209) (245:245:245)) + (PORT datac (642:642:642) (687:687:687)) + (PORT datad (186:186:186) (213:213:213)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~110) (DELAY (ABSOLUTE - (PORT dataa (1073:1073:1073) (1100:1100:1100)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datad (807:807:807) (826:826:826)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (191:191:191) (232:232:232)) + (PORT datab (855:855:855) (853:853:853)) + (PORT datad (532:532:532) (533:533:533)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -38309,12 +37486,14 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) (DELAY (ABSOLUTE - (PORT clk (1332:1332:1332) (1350:1350:1350)) + (PORT clk (1334:1334:1334) (1351:1351:1351)) (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1367:1367:1367) (1349:1349:1349)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK @@ -38323,295 +37502,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~111) (DELAY (ABSOLUTE - (PORT dataa (2259:2259:2259) (2263:2263:2263)) - (PORT datab (1492:1492:1492) (1553:1553:1553)) - (PORT datac (1648:1648:1648) (1714:1714:1714)) - (PORT datad (1531:1531:1531) (1547:1547:1547)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1324:1324:1324) (1370:1370:1370)) - (PORT datab (181:181:181) (212:212:212)) - (PORT datac (970:970:970) (992:992:992)) - (PORT datad (1241:1241:1241) (1202:1202:1202)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1036:1036:1036) (1128:1128:1128)) - (PORT datac (822:822:822) (852:852:852)) - (PORT datad (882:882:882) (922:922:922)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) - (DELAY - (ABSOLUTE - (PORT dataa (841:841:841) (841:841:841)) - (PORT datab (867:867:867) (913:913:913)) - (PORT datac (549:549:549) (540:540:540)) - (PORT datad (502:502:502) (480:480:480)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (783:783:783) (768:768:768)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (175:175:175) (205:205:205)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1073:1073:1073) (1121:1121:1121)) - (PORT datab (233:233:233) (308:308:308)) - (PORT datac (194:194:194) (260:260:260)) - (PORT datad (540:540:540) (539:539:539)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~20) - (DELAY - (ABSOLUTE - (PORT dataa (538:538:538) (531:531:531)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (550:550:550) (563:563:563)) - (PORT datad (561:561:561) (538:538:538)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1449:1449:1449) (1544:1544:1544)) - (PORT datab (2385:2385:2385) (2384:2384:2384)) - (PORT datac (987:987:987) (972:972:972)) - (PORT datad (794:794:794) (809:809:809)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1016:1016:1016) (1000:1000:1000)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1096:1096:1096) (1117:1117:1117)) - (PORT datad (524:524:524) (510:510:510)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) - (DELAY - (ABSOLUTE - (PORT dataa (840:840:840) (823:823:823)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datac (210:210:210) (251:251:251)) - (PORT datad (551:551:551) (547:547:547)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (913:913:913)) - (PORT datab (236:236:236) (278:278:278)) - (PORT datac (1287:1287:1287) (1301:1301:1301)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) - (DELAY - (ABSOLUTE - (PORT dataa (854:854:854) (851:851:851)) - (PORT datab (1045:1045:1045) (1074:1074:1074)) - (PORT datac (818:818:818) (827:827:827)) - (PORT datad (937:937:937) (906:906:906)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_set\~0) - (DELAY - (ABSOLUTE - (PORT dataa (441:441:441) (457:457:457)) - (PORT datab (831:831:831) (816:816:816)) - (PORT datac (841:841:841) (886:886:886)) - (PORT datad (374:374:374) (385:385:385)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) - (DELAY - (ABSOLUTE - (PORT datab (983:983:983) (967:967:967)) - (PORT datac (187:187:187) (227:227:227)) - (PORT datad (190:190:190) (217:217:217)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~9) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (483:483:483) (492:492:492)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_cf) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (216:216:216)) - (PORT datab (550:550:550) (547:547:547)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (531:531:531) (513:513:513)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (657:657:657)) - (PORT datab (601:601:601) (632:632:632)) - (PORT datac (822:822:822) (816:816:816)) - (PORT datad (826:826:826) (831:831:831)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (1067:1067:1067) (1074:1074:1074)) - (PORT datad (577:577:577) (571:571:571)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (363:363:363)) - (PORT datab (603:603:603) (604:604:604)) - (PORT datac (807:807:807) (813:813:813)) - (PORT datad (158:158:158) (179:179:179)) + (PORT dataa (957:957:957) (1008:1008:1008)) + (PORT datab (384:384:384) (445:445:445)) + (PORT datac (907:907:907) (946:946:946)) + (PORT datad (558:558:558) (593:593:593)) (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -38619,286 +37518,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~12) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~112) (DELAY (ABSOLUTE - (PORT dataa (655:655:655) (647:647:647)) - (PORT datab (880:880:880) (876:876:876)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (193:193:193) (226:226:226)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (686:686:686)) - (PORT datac (1028:1028:1028) (1027:1027:1027)) - (PORT datad (680:680:680) (743:743:743)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (706:706:706) (771:771:771)) - (PORT datab (665:665:665) (720:720:720)) - (PORT datac (1028:1028:1028) (1028:1028:1028)) - (PORT datad (653:653:653) (704:704:704)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (222:222:222)) - (PORT datab (837:837:837) (875:875:875)) - (PORT datac (1028:1028:1028) (1028:1028:1028)) - (PORT datad (313:313:313) (315:315:315)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (194:194:194) (237:237:237)) - (PORT datab (183:183:183) (216:216:216)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (717:717:717)) - (PORT datab (908:908:908) (950:950:950)) - (PORT datac (664:664:664) (735:735:735)) - (PORT datad (679:679:679) (744:744:744)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (811:811:811)) - (PORT datab (672:672:672) (736:736:736)) - (PORT datac (658:658:658) (726:726:726)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (345:345:345)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datad (315:315:315) (314:314:314)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1075:1075:1075) (1095:1095:1095)) - (PORT datab (670:670:670) (717:717:717)) - (PORT datac (194:194:194) (261:261:261)) - (PORT datad (513:513:513) (512:512:512)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (905:905:905)) - (PORT datab (714:714:714) (780:780:780)) - (PORT datac (1248:1248:1248) (1310:1310:1310)) - (PORT datad (1100:1100:1100) (1121:1121:1121)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~76) - (DELAY - (ABSOLUTE - (PORT dataa (323:323:323) (337:337:337)) - (PORT datab (256:256:256) (326:326:326)) - (PORT datac (861:861:861) (853:853:853)) - (PORT datad (1380:1380:1380) (1419:1419:1419)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~73) - (DELAY - (ABSOLUTE - (PORT datac (680:680:680) (749:749:749)) - (PORT datad (1100:1100:1100) (1125:1125:1125)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (703:703:703) (772:772:772)) - (PORT datab (668:668:668) (725:725:725)) - (PORT datac (808:808:808) (845:845:845)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (696:696:696) (748:748:748)) - (PORT datab (1393:1393:1393) (1427:1427:1427)) - (PORT datac (841:841:841) (877:877:877)) - (PORT datad (794:794:794) (812:812:812)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~74) - (DELAY - (ABSOLUTE - (PORT dataa (547:547:547) (552:552:552)) - (PORT datab (320:320:320) (328:328:328)) - (PORT datac (1249:1249:1249) (1304:1304:1304)) - (PORT datad (1423:1423:1423) (1456:1456:1456)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (221:221:221)) + (PORT dataa (272:272:272) (361:361:361)) (PORT datab (184:184:184) (218:218:218)) - (PORT datac (407:407:407) (460:460:460)) - (PORT datad (782:782:782) (772:772:772)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datac (618:618:618) (665:665:665)) + (PORT datad (587:587:587) (595:595:595)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~77) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~132) (DELAY (ABSOLUTE - (PORT dataa (527:527:527) (507:507:507)) - (PORT datab (311:311:311) (328:328:328)) - (PORT datad (678:678:678) (741:741:741)) + (PORT dataa (808:808:808) (814:814:814)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datad (661:661:661) (700:700:700)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~133) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (579:579:579)) + (PORT datab (708:708:708) (740:740:740)) + (PORT datad (167:167:167) (191:191:191)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -38908,12 +37564,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT clk (1334:1334:1334) (1351:1351:1351)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) + (PORT clrn (1367:1367:1367) (1349:1349:1349)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -38924,15 +37580,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~71) + (INSTANCE D\[3\]\~75) (DELAY (ABSOLUTE - (PORT dataa (698:698:698) (765:765:765)) - (PORT datab (673:673:673) (738:738:738)) - (PORT datac (304:304:304) (328:328:328)) - (PORT datad (1044:1044:1044) (1061:1061:1061)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT dataa (221:221:221) (292:292:292)) + (PORT datab (844:844:844) (835:835:835)) + (PORT datac (196:196:196) (263:263:263)) + (PORT datad (1302:1302:1302) (1275:1275:1275)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~94) + (DELAY + (ABSOLUTE + (PORT dataa (1137:1137:1137) (1163:1163:1163)) + (PORT datab (1198:1198:1198) (1229:1229:1229)) + (PORT datac (636:636:636) (689:689:689)) + (PORT datad (665:665:665) (706:706:706)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (1137:1137:1137) (1163:1163:1163)) + (PORT datac (908:908:908) (939:939:939)) + (PORT datad (607:607:607) (640:640:640)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~95) + (DELAY + (ABSOLUTE + (PORT dataa (957:957:957) (995:995:995)) + (PORT datab (881:881:881) (922:922:922)) + (PORT datac (829:829:829) (823:823:823)) + (PORT datad (664:664:664) (705:705:705)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -38940,206 +37642,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~72) + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) (DELAY (ABSOLUTE - (PORT datab (183:183:183) (216:216:216)) - (PORT datad (662:662:662) (728:728:728)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (406:406:406)) - (PORT datab (1045:1045:1045) (1066:1066:1066)) - (PORT datac (590:590:590) (619:619:619)) - (PORT datad (581:581:581) (606:606:606)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (1438:1438:1438) (1484:1484:1484)) - (PORT datab (907:907:907) (923:923:923)) - (PORT datad (482:482:482) (467:467:467)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (435:435:435) (501:501:501)) - (PORT datac (561:561:561) (596:596:596)) - (PORT datad (237:237:237) (299:299:299)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (375:375:375) (380:380:380)) - (PORT datab (785:785:785) (759:759:759)) - (PORT datad (676:676:676) (737:737:737)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~1) - (DELAY - (ABSOLUTE - (PORT datab (1378:1378:1378) (1422:1422:1422)) - (PORT datac (321:321:321) (369:369:369)) - (PORT datad (844:844:844) (870:870:870)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (194:194:194) (261:261:261)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~1) - (DELAY - (ABSOLUTE - (PORT datac (985:985:985) (1045:1045:1045)) - (PORT datad (950:950:950) (998:998:998)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (1296:1296:1296) (1372:1372:1372)) - (PORT datab (724:724:724) (795:795:795)) - (PORT datac (883:883:883) (919:919:919)) - (PORT datad (704:704:704) (784:784:784)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (231:231:231)) - (PORT datab (620:620:620) (630:630:630)) - (PORT datac (562:562:562) (552:552:552)) - (PORT datad (828:828:828) (861:861:861)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~92) - (DELAY - (ABSOLUTE - (PORT datab (889:889:889) (937:937:937)) - (PORT datad (161:161:161) (182:182:182)) + (PORT dataa (184:184:184) (220:220:220)) + (PORT datab (189:189:189) (225:225:225)) + (PORT datad (571:571:571) (566:566:566)) + (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -39148,12 +37657,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT clk (1334:1334:1334) (1351:1351:1351)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) + (PORT clrn (1367:1367:1367) (1349:1349:1349)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -39164,83 +37673,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~63) + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~91) (DELAY (ABSOLUTE - (PORT datac (595:595:595) (633:633:633)) - (PORT datad (586:586:586) (621:621:621)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (453:453:453) (518:518:518)) + (PORT datab (823:823:823) (843:843:843)) + (PORT datac (575:575:575) (569:569:569)) + (PORT datad (173:173:173) (201:201:201)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~92) (DELAY (ABSOLUTE - (PORT datab (606:606:606) (639:639:639)) - (PORT datac (625:625:625) (684:684:684)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (233:233:233)) - (PORT datab (443:443:443) (484:484:484)) - (PORT datac (592:592:592) (619:619:619)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~132) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (250:250:250)) - (PORT datab (607:607:607) (657:657:657)) - (PORT datad (604:604:604) (646:646:646)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (795:795:795) (829:829:829)) - (PORT datab (203:203:203) (237:237:237)) - (PORT datac (314:314:314) (325:325:325)) - (PORT datad (504:504:504) (497:497:497)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (752:752:752) (731:731:731)) - (PORT datad (871:871:871) (888:888:888)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (899:899:899) (935:935:935)) + (PORT datad (426:426:426) (468:468:468)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -39248,12 +37704,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT clk (1325:1325:1325) (1344:1344:1344)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) + (PORT clrn (1367:1367:1367) (1347:1347:1347)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -39264,15 +37720,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~50) + (INSTANCE D\[3\]\~72) (DELAY (ABSOLUTE - (PORT dataa (1287:1287:1287) (1283:1283:1283)) - (PORT datab (555:555:555) (582:582:582)) - (PORT datac (1267:1267:1267) (1266:1266:1266)) - (PORT datad (199:199:199) (256:256:256)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (PORT dataa (657:657:657) (683:683:683)) + (PORT datab (219:219:219) (287:287:287)) + (PORT datac (2240:2240:2240) (2343:2343:2343)) + (PORT datad (816:816:816) (829:829:829)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (811:811:811)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (317:317:317) (325:325:325)) + (PORT datad (568:568:568) (562:562:562)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -39280,179 +37752,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~51) + (INSTANCE D\[3\]\~122) (DELAY (ABSOLUTE - (PORT dataa (723:723:723) (722:722:722)) - (PORT datab (3110:3110:3110) (3118:3118:3118)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (160:160:160) (182:182:182)) + (PORT dataa (1022:1022:1022) (1017:1017:1017)) + (PORT datab (1174:1174:1174) (1238:1238:1238)) + (PORT datac (2381:2381:2381) (2522:2522:2522)) + (PORT datad (591:591:591) (610:610:610)) (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (827:827:827) (822:822:822)) - (PORT clk (1646:1646:1646) (1674:1674:1674)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1142:1142:1142) (1152:1152:1152)) - (PORT d[1] (912:912:912) (937:937:937)) - (PORT d[2] (890:890:890) (884:884:884)) - (PORT d[3] (943:943:943) (966:966:966)) - (PORT d[4] (2421:2421:2421) (2524:2524:2524)) - (PORT d[5] (955:955:955) (960:960:960)) - (PORT d[6] (919:919:919) (944:944:944)) - (PORT d[7] (883:883:883) (901:901:901)) - (PORT d[8] (969:969:969) (983:983:983)) - (PORT d[9] (923:923:923) (948:948:948)) - (PORT d[10] (973:973:973) (1007:1007:1007)) - (PORT d[11] (2392:2392:2392) (2487:2487:2487)) - (PORT d[12] (1206:1206:1206) (1236:1236:1236)) - (PORT clk (1643:1643:1643) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (871:871:871) (835:835:835)) - (PORT clk (1643:1643:1643) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1674:1674:1674)) - (PORT d[0] (1334:1334:1334) (1304:1304:1304)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1638:1638:1638)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (905:905:905) (887:887:887)) + (PORT d[0] (1042:1042:1042) (1019:1019:1019)) (PORT clk (1646:1646:1646) (1673:1673:1673)) ) ) @@ -39462,22 +37781,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (655:655:655) (654:654:654)) - (PORT d[1] (2216:2216:2216) (2370:2370:2370)) - (PORT d[2] (1386:1386:1386) (1401:1401:1401)) - (PORT d[3] (909:909:909) (925:925:925)) - (PORT d[4] (2407:2407:2407) (2520:2520:2520)) - (PORT d[5] (3216:3216:3216) (3328:3328:3328)) - (PORT d[6] (1174:1174:1174) (1189:1189:1189)) - (PORT d[7] (2944:2944:2944) (2982:2982:2982)) - (PORT d[8] (644:644:644) (645:645:645)) - (PORT d[9] (1480:1480:1480) (1519:1519:1519)) - (PORT d[10] (1247:1247:1247) (1289:1289:1289)) - (PORT d[11] (2074:2074:2074) (2159:2159:2159)) - (PORT d[12] (1446:1446:1446) (1472:1472:1472)) + (PORT d[0] (2357:2357:2357) (2442:2442:2442)) + (PORT d[1] (3336:3336:3336) (3420:3420:3420)) + (PORT d[2] (2202:2202:2202) (2231:2231:2231)) + (PORT d[3] (3965:3965:3965) (4034:4034:4034)) + (PORT d[4] (2962:2962:2962) (3073:3073:3073)) + (PORT d[5] (4383:4383:4383) (4458:4458:4458)) + (PORT d[6] (2351:2351:2351) (2366:2366:2366)) + (PORT d[7] (1306:1306:1306) (1302:1302:1302)) + (PORT d[8] (2623:2623:2623) (2703:2703:2703)) + (PORT d[9] (1670:1670:1670) (1670:1670:1670)) + (PORT d[10] (1589:1589:1589) (1569:1569:1569)) + (PORT d[11] (3167:3167:3167) (3292:3292:3292)) + (PORT d[12] (4243:4243:4243) (4350:4350:4350)) (PORT clk (1643:1643:1643) (1671:1671:1671)) ) ) @@ -39487,10 +37806,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (612:612:612) (573:573:573)) + (PORT d[0] (1537:1537:1537) (1457:1457:1457)) (PORT clk (1643:1643:1643) (1671:1671:1671)) ) ) @@ -39500,17 +37819,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1646:1646:1646) (1673:1673:1673)) - (PORT d[0] (1332:1332:1332) (1279:1279:1279)) + (PORT d[0] (2039:2039:2039) (1990:1990:1990)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1647:1647:1647) (1674:1674:1674)) @@ -39520,7 +37839,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1647:1647:1647) (1674:1674:1674)) @@ -39530,7 +37849,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1647:1647:1647) (1674:1674:1674)) @@ -39540,7 +37859,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1647:1647:1647) (1674:1674:1674)) @@ -39550,7 +37869,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1610:1610:1610) (1637:1637:1637)) @@ -39564,7 +37883,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (881:881:881) (884:884:884)) @@ -39573,7 +37892,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) (DELAY (ABSOLUTE (PORT clk (882:882:882) (885:885:885)) @@ -39582,7 +37901,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (882:882:882) (885:885:885)) @@ -39592,7 +37911,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (882:882:882) (885:885:885)) @@ -39601,11 +37920,27 @@ ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~79) (DELAY (ABSOLUTE - (PORT d[0] (1018:1018:1018) (1000:1000:1000)) + (PORT dataa (1081:1081:1081) (1127:1127:1127)) + (PORT datab (624:624:624) (639:639:639)) + (PORT datac (1279:1279:1279) (1297:1297:1297)) + (PORT datad (1023:1023:1023) (1003:1003:1003)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1067:1067:1067) (1036:1036:1036)) (PORT clk (1645:1645:1645) (1672:1672:1672)) ) ) @@ -39615,22 +37950,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (908:908:908) (912:912:912)) - (PORT d[1] (3190:3190:3190) (3345:3345:3345)) - (PORT d[2] (1153:1153:1153) (1157:1157:1157)) - (PORT d[3] (1182:1182:1182) (1204:1204:1204)) - (PORT d[4] (2395:2395:2395) (2506:2506:2506)) - (PORT d[5] (3231:3231:3231) (3348:3348:3348)) - (PORT d[6] (1217:1217:1217) (1267:1267:1267)) - (PORT d[7] (1126:1126:1126) (1137:1137:1137)) - (PORT d[8] (929:929:929) (929:929:929)) - (PORT d[9] (1442:1442:1442) (1473:1473:1473)) - (PORT d[10] (1257:1257:1257) (1304:1304:1304)) - (PORT d[11] (2094:2094:2094) (2179:2179:2179)) - (PORT d[12] (1480:1480:1480) (1518:1518:1518)) + (PORT d[0] (1576:1576:1576) (1645:1645:1645)) + (PORT d[1] (2620:2620:2620) (2622:2622:2622)) + (PORT d[2] (2223:2223:2223) (2247:2247:2247)) + (PORT d[3] (3945:3945:3945) (4013:4013:4013)) + (PORT d[4] (915:915:915) (923:923:923)) + (PORT d[5] (2071:2071:2071) (2042:2042:2042)) + (PORT d[6] (2352:2352:2352) (2367:2367:2367)) + (PORT d[7] (1272:1272:1272) (1253:1253:1253)) + (PORT d[8] (2598:2598:2598) (2673:2673:2673)) + (PORT d[9] (1375:1375:1375) (1381:1381:1381)) + (PORT d[10] (1831:1831:1831) (1806:1806:1806)) + (PORT d[11] (3168:3168:3168) (3293:3293:3293)) + (PORT d[12] (4317:4317:4317) (4436:4436:4436)) (PORT clk (1642:1642:1642) (1670:1670:1670)) ) ) @@ -39640,10 +37975,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (881:881:881) (829:829:829)) + (PORT d[0] (2336:2336:2336) (2311:2311:2311)) (PORT clk (1642:1642:1642) (1670:1670:1670)) ) ) @@ -39653,17 +37988,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1645:1645:1645) (1672:1672:1672)) - (PORT d[0] (1526:1526:1526) (1472:1472:1472)) + (PORT d[0] (2017:2017:2017) (1966:1966:1966)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1646:1646:1646) (1673:1673:1673)) @@ -39673,7 +38008,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1646:1646:1646) (1673:1673:1673)) @@ -39683,7 +38018,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1646:1646:1646) (1673:1673:1673)) @@ -39693,7 +38028,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1646:1646:1646) (1673:1673:1673)) @@ -39703,7 +38038,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1609:1609:1609) (1636:1636:1636)) @@ -39717,7 +38052,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (880:880:880) (883:883:883)) @@ -39726,7 +38061,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) (DELAY (ABSOLUTE (PORT clk (881:881:881) (884:884:884)) @@ -39735,7 +38070,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (881:881:881) (884:884:884)) @@ -39745,7 +38080,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (881:881:881) (884:884:884)) @@ -39753,29 +38088,13 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (362:362:362)) - (PORT datab (624:624:624) (664:664:664)) - (PORT datac (603:603:603) (641:641:641)) - (PORT datad (598:598:598) (583:583:583)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1105:1105:1105) (1088:1088:1088)) - (PORT clk (1637:1637:1637) (1665:1665:1665)) + (PORT d[0] (698:698:698) (696:696:696)) + (PORT clk (1638:1638:1638) (1666:1666:1666)) ) ) (TIMINGCHECK @@ -39784,23 +38103,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3379:3379:3379) (3446:3446:3446)) - (PORT d[1] (1268:1268:1268) (1347:1347:1347)) - (PORT d[2] (1861:1861:1861) (1882:1882:1882)) - (PORT d[3] (2267:2267:2267) (2330:2330:2330)) - (PORT d[4] (2046:2046:2046) (2106:2106:2106)) - (PORT d[5] (1246:1246:1246) (1306:1306:1306)) - (PORT d[6] (1355:1355:1355) (1373:1373:1373)) - (PORT d[7] (3098:3098:3098) (3120:3120:3120)) - (PORT d[8] (3347:3347:3347) (3464:3464:3464)) - (PORT d[9] (2928:2928:2928) (2995:2995:2995)) - (PORT d[10] (2921:2921:2921) (2980:2980:2980)) - (PORT d[11] (1660:1660:1660) (1694:1694:1694)) - (PORT d[12] (1319:1319:1319) (1343:1343:1343)) - (PORT clk (1634:1634:1634) (1663:1663:1663)) + (PORT d[0] (2838:2838:2838) (2996:2996:2996)) + (PORT d[1] (1508:1508:1508) (1531:1531:1531)) + (PORT d[2] (934:934:934) (950:950:950)) + (PORT d[3] (888:888:888) (904:904:904)) + (PORT d[4] (3026:3026:3026) (3104:3104:3104)) + (PORT d[5] (898:898:898) (906:906:906)) + (PORT d[6] (1459:1459:1459) (1521:1521:1521)) + (PORT d[7] (922:922:922) (916:916:916)) + (PORT d[8] (1178:1178:1178) (1202:1202:1202)) + (PORT d[9] (979:979:979) (1018:1018:1018)) + (PORT d[10] (949:949:949) (981:981:981)) + (PORT d[11] (2036:2036:2036) (2114:2114:2114)) + (PORT d[12] (993:993:993) (1043:1043:1043)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) ) ) (TIMINGCHECK @@ -39809,11 +38128,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1505:1505:1505) (1437:1437:1437)) - (PORT clk (1634:1634:1634) (1663:1663:1663)) + (PORT d[0] (874:874:874) (840:840:840)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) ) ) (TIMINGCHECK @@ -39822,17 +38141,170 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1637:1637:1637) (1665:1665:1665)) - (PORT d[0] (2529:2529:2529) (2495:2495:2495)) + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (PORT d[0] (2712:2712:2712) (2702:2702:2702)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1630:1630:1630)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (932:932:932) (934:934:934)) + (PORT clk (1637:1637:1637) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2790:2790:2790) (2941:2941:2941)) + (PORT d[1] (1498:1498:1498) (1524:1524:1524)) + (PORT d[2] (913:913:913) (916:916:916)) + (PORT d[3] (892:892:892) (900:900:900)) + (PORT d[4] (1340:1340:1340) (1312:1312:1312)) + (PORT d[5] (876:876:876) (874:874:874)) + (PORT d[6] (1721:1721:1721) (1778:1778:1778)) + (PORT d[7] (876:876:876) (859:859:859)) + (PORT d[8] (1180:1180:1180) (1212:1212:1212)) + (PORT d[9] (694:694:694) (731:731:731)) + (PORT d[10] (699:699:699) (735:735:735)) + (PORT d[11] (2339:2339:2339) (2427:2427:2427)) + (PORT d[12] (715:715:715) (755:755:755)) + (PORT clk (1634:1634:1634) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (625:625:625) (568:568:568)) + (PORT clk (1634:1634:1634) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1665:1665:1665)) + (PORT d[0] (1616:1616:1616) (1566:1566:1566)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1638:1638:1638) (1666:1666:1666)) @@ -39842,7 +38314,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1638:1638:1638) (1666:1666:1666)) @@ -39852,7 +38324,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1638:1638:1638) (1666:1666:1666)) @@ -39862,7 +38334,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1638:1638:1638) (1666:1666:1666)) @@ -39872,7 +38344,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1601:1601:1601) (1629:1629:1629)) @@ -39886,7 +38358,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (872:872:872) (876:876:876)) @@ -39895,7 +38367,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) (DELAY (ABSOLUTE (PORT clk (873:873:873) (877:877:877)) @@ -39904,7 +38376,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (873:873:873) (877:877:877)) @@ -39912,27 +38384,3681 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2102:2102:2102) (2181:2181:2181)) + (PORT d[1] (2597:2597:2597) (2596:2596:2596)) + (PORT d[2] (2218:2218:2218) (2248:2248:2248)) + (PORT d[3] (4206:4206:4206) (4271:4271:4271)) + (PORT d[4] (927:927:927) (942:942:942)) + (PORT d[5] (2031:2031:2031) (2008:2008:2008)) + (PORT d[6] (862:862:862) (853:853:853)) + (PORT d[7] (1244:1244:1244) (1208:1208:1208)) + (PORT d[8] (2616:2616:2616) (2693:2693:2693)) + (PORT d[9] (1362:1362:1362) (1368:1368:1368)) + (PORT d[10] (1840:1840:1840) (1825:1825:1825)) + (PORT d[11] (3447:3447:3447) (3579:3579:3579)) + (PORT d[12] (4343:4343:4343) (4457:4457:4457)) + (PORT clk (1641:1641:1641) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1668:1668:1668)) + (PORT d[0] (1180:1180:1180) (1227:1227:1227)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1634:1634:1634)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (881:881:881)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (1816:1816:1816) (1835:1835:1835)) + (PORT datab (1402:1402:1402) (1431:1431:1431)) + (PORT datac (822:822:822) (820:820:820)) + (PORT datad (995:995:995) (971:971:971)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~80) + (DELAY + (ABSOLUTE + (PORT datab (846:846:846) (825:825:825)) + (PORT datac (1278:1278:1278) (1297:1297:1297)) + (PORT datad (165:165:165) (187:187:187)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (1376:1376:1376) (1447:1447:1447)) + (PORT datab (1056:1056:1056) (1037:1037:1037)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (1660:1660:1660) (1695:1695:1695)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1344:1344:1344) (1333:1333:1333)) + (PORT clk (1646:1646:1646) (1673:1673:1673)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2306:2306:2306) (2353:2353:2353)) + (PORT d[1] (2494:2494:2494) (2544:2544:2544)) + (PORT d[2] (2375:2375:2375) (2404:2404:2404)) + (PORT d[3] (3103:3103:3103) (3127:3127:3127)) + (PORT d[4] (2137:2137:2137) (2207:2207:2207)) + (PORT d[5] (3500:3500:3500) (3534:3534:3534)) + (PORT d[6] (2369:2369:2369) (2379:2379:2379)) + (PORT d[7] (3144:3144:3144) (3137:3137:3137)) + (PORT d[8] (2711:2711:2711) (2759:2759:2759)) + (PORT d[9] (2523:2523:2523) (2571:2571:2571)) + (PORT d[10] (2399:2399:2399) (2411:2411:2411)) + (PORT d[11] (2339:2339:2339) (2422:2422:2422)) + (PORT d[12] (3251:3251:3251) (3338:3338:3338)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2615:2615:2615) (2588:2588:2588)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (PORT d[0] (3167:3167:3167) (3168:3168:3168)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1605:1605:1605) (1603:1603:1603)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2266:2266:2266) (2211:2211:2211)) + (PORT clk (1613:1613:1613) (1610:1610:1610)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4159:4159:4159) (4029:4029:4029)) + (PORT d[1] (4126:4126:4126) (4092:4092:4092)) + (PORT d[2] (4226:4226:4226) (4086:4086:4086)) + (PORT d[3] (4078:4078:4078) (3991:3991:3991)) + (PORT d[4] (3967:3967:3967) (3947:3947:3947)) + (PORT d[5] (4071:4071:4071) (4018:4018:4018)) + (PORT d[6] (4131:4131:4131) (4004:4004:4004)) + (PORT d[7] (4068:4068:4068) (3937:3937:3937)) + (PORT d[8] (4094:4094:4094) (3992:3992:3992)) + (PORT d[9] (4102:4102:4102) (4037:4037:4037)) + (PORT d[10] (3964:3964:3964) (3840:3840:3840)) + (PORT d[11] (4072:4072:4072) (4007:4007:4007)) + (PORT d[12] (3962:3962:3962) (3828:3828:3828)) + (PORT clk (1610:1610:1610) (1607:1607:1607)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1610:1610:1610)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1611:1611:1611)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1611:1611:1611)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1611:1611:1611)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1611:1611:1611)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1604:1604:1604)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~124) + (DELAY + (ABSOLUTE + (PORT dataa (2423:2423:2423) (2563:2563:2563)) + (PORT datab (2280:2280:2280) (2312:2312:2312)) + (PORT datac (1473:1473:1473) (1523:1523:1523)) + (PORT datad (165:165:165) (188:188:188)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1293:1293:1293) (1290:1290:1290)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1812:1812:1812) (1859:1859:1859)) + (PORT d[1] (2792:2792:2792) (2855:2855:2855)) + (PORT d[2] (1672:1672:1672) (1704:1704:1704)) + (PORT d[3] (3380:3380:3380) (3415:3415:3415)) + (PORT d[4] (2432:2432:2432) (2519:2519:2519)) + (PORT d[5] (3796:3796:3796) (3844:3844:3844)) + (PORT d[6] (2523:2523:2523) (2513:2513:2513)) + (PORT d[7] (1839:1839:1839) (1853:1853:1853)) + (PORT d[8] (1846:1846:1846) (1858:1858:1858)) + (PORT d[9] (2247:2247:2247) (2298:2298:2298)) + (PORT d[10] (2436:2436:2436) (2454:2454:2454)) + (PORT d[11] (2592:2592:2592) (2685:2685:2685)) + (PORT d[12] (4223:4223:4223) (4300:4300:4300)) + (PORT clk (1636:1636:1636) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1433:1433:1433) (1350:1350:1350)) + (PORT clk (1636:1636:1636) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (PORT d[0] (2912:2912:2912) (2902:2902:2902)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1597:1597:1597)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2021:2021:2021) (1977:1977:1977)) + (PORT clk (1606:1606:1606) (1604:1604:1604)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4221:4221:4221) (4140:4140:4140)) + (PORT d[1] (4122:4122:4122) (4082:4082:4082)) + (PORT d[2] (4157:4157:4157) (4016:4016:4016)) + (PORT d[3] (4095:4095:4095) (4027:4027:4027)) + (PORT d[4] (4038:4038:4038) (4034:4034:4034)) + (PORT d[5] (4048:4048:4048) (3978:3978:3978)) + (PORT d[6] (4136:4136:4136) (3984:3984:3984)) + (PORT d[7] (4049:4049:4049) (4017:4017:4017)) + (PORT d[8] (4171:4171:4171) (4059:4059:4059)) + (PORT d[9] (4241:4241:4241) (4151:4151:4151)) + (PORT d[10] (4000:4000:4000) (3918:3918:3918)) + (PORT d[11] (4113:4113:4113) (4055:4055:4055)) + (PORT d[12] (3967:3967:3967) (3843:3843:3843)) + (PORT clk (1603:1603:1603) (1601:1601:1601)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1604:1604:1604)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1605:1605:1605)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1605:1605:1605)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1605:1605:1605)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1605:1605:1605)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2303:2303:2303) (2346:2346:2346)) + (PORT d[1] (2206:2206:2206) (2246:2246:2246)) + (PORT d[2] (2103:2103:2103) (2172:2172:2172)) + (PORT d[3] (2018:2018:2018) (2076:2076:2076)) + (PORT d[4] (1940:1940:1940) (1972:1972:1972)) + (PORT d[5] (2231:2231:2231) (2282:2282:2282)) + (PORT d[6] (2255:2255:2255) (2335:2335:2335)) + (PORT d[7] (2921:2921:2921) (2945:2945:2945)) + (PORT d[8] (2652:2652:2652) (2670:2670:2670)) + (PORT d[9] (2175:2175:2175) (2285:2285:2285)) + (PORT d[10] (3045:3045:3045) (3068:3068:3068)) + (PORT d[11] (1960:1960:1960) (1984:1984:1984)) + (PORT d[12] (2103:2103:2103) (2205:2205:2205)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (PORT d[0] (2373:2373:2373) (2397:2397:2397)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1640:1640:1640)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (887:887:887)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (888:888:888)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (888:888:888)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (888:888:888)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~123) + (DELAY + (ABSOLUTE + (PORT dataa (2418:2418:2418) (2557:2557:2557)) + (PORT datab (2282:2282:2282) (2314:2314:2314)) + (PORT datac (1223:1223:1223) (1219:1219:1219)) + (PORT datad (1550:1550:1550) (1542:1542:1542)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (1164:1164:1164) (1175:1175:1175)) + (PORT datab (679:679:679) (754:754:754)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (1814:1814:1814) (1832:1832:1832)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~108) + (DELAY + (ABSOLUTE + (PORT dataa (1439:1439:1439) (1421:1421:1421)) + (PORT datab (202:202:202) (236:236:236)) + (PORT datad (179:179:179) (201:201:201)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~109) + (DELAY + (ABSOLUTE + (PORT dataa (2562:2562:2562) (2558:2558:2558)) + (PORT datab (867:867:867) (908:908:908)) + (PORT datac (176:176:176) (207:207:207)) + (PORT datad (1390:1390:1390) (1375:1375:1375)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (268:268:268)) + (PORT datab (797:797:797) (802:802:802)) + (PORT datac (581:581:581) (587:587:587)) + (PORT datad (1049:1049:1049) (1028:1028:1028)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (763:763:763) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (392:392:392) (396:396:396)) + (PORT datac (331:331:331) (382:382:382)) + (PORT datad (359:359:359) (366:366:366)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1213:1213:1213) (1165:1165:1165)) + (PORT datab (349:349:349) (349:349:349)) + (PORT datac (757:757:757) (793:793:793)) + (PORT datad (526:526:526) (523:523:523)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1396:1396:1396) (1368:1368:1368)) + (PORT ena (1804:1804:1804) (1767:1767:1767)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2069:2069:2069) (2089:2089:2089)) + (PORT datac (1451:1451:1451) (1528:1528:1528)) + (PORT datad (1564:1564:1564) (1582:1582:1582)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (785:785:785) (777:777:777)) + (PORT datab (1721:1721:1721) (1751:1751:1751)) + (PORT datac (1054:1054:1054) (1054:1054:1054)) + (PORT datad (577:577:577) (593:593:593)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (609:609:609)) + (PORT datab (185:185:185) (222:222:222)) + (PORT datac (1084:1084:1084) (1074:1074:1074)) + (PORT datad (795:795:795) (794:794:794)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (407:407:407)) + (PORT datab (558:558:558) (548:548:548)) + (PORT datad (1051:1051:1051) (1028:1028:1028)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1404:1404:1404) (1378:1378:1378)) + (PORT clk (1636:1636:1636) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2201:2201:2201) (2312:2312:2312)) + (PORT d[1] (2367:2367:2367) (2384:2384:2384)) + (PORT d[2] (1436:1436:1436) (1464:1464:1464)) + (PORT d[3] (1174:1174:1174) (1200:1200:1200)) + (PORT d[4] (1867:1867:1867) (1874:1874:1874)) + (PORT d[5] (1168:1168:1168) (1192:1192:1192)) + (PORT d[6] (1584:1584:1584) (1571:1571:1571)) + (PORT d[7] (2173:2173:2173) (2230:2230:2230)) + (PORT d[8] (2286:2286:2286) (2379:2379:2379)) + (PORT d[9] (957:957:957) (997:997:997)) + (PORT d[10] (1609:1609:1609) (1637:1637:1637)) + (PORT d[11] (1363:1363:1363) (1363:1363:1363)) + (PORT d[12] (932:932:932) (963:963:963)) + (PORT clk (1633:1633:1633) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1628:1628:1628) (1593:1593:1593)) + (PORT clk (1633:1633:1633) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1662:1662:1662)) + (PORT d[0] (1911:1911:1911) (1866:1866:1866)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1600:1600:1600) (1626:1626:1626)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1382:1382:1382) (1346:1346:1346)) + (PORT clk (1638:1638:1638) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2176:2176:2176) (2275:2275:2275)) + (PORT d[1] (1846:1846:1846) (1859:1859:1859)) + (PORT d[2] (1717:1717:1717) (1728:1728:1728)) + (PORT d[3] (2057:2057:2057) (2080:2080:2080)) + (PORT d[4] (1887:1887:1887) (1883:1883:1883)) + (PORT d[5] (1467:1467:1467) (1502:1502:1502)) + (PORT d[6] (1597:1597:1597) (1593:1593:1593)) + (PORT d[7] (2104:2104:2104) (2135:2135:2135)) + (PORT d[8] (2298:2298:2298) (2401:2401:2401)) + (PORT d[9] (1095:1095:1095) (1110:1110:1110)) + (PORT d[10] (1527:1527:1527) (1530:1530:1530)) + (PORT d[11] (1117:1117:1117) (1121:1121:1121)) + (PORT d[12] (970:970:970) (1014:1014:1014)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1413:1413:1413) (1390:1390:1390)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (PORT d[0] (1800:1800:1800) (1759:1759:1759)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1630:1630:1630)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (853:853:853) (849:849:849)) + (PORT clk (1646:1646:1646) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2688:2688:2688) (2797:2797:2797)) + (PORT d[1] (3299:3299:3299) (3366:3366:3366)) + (PORT d[2] (1809:1809:1809) (1807:1807:1807)) + (PORT d[3] (3669:3669:3669) (3718:3718:3718)) + (PORT d[4] (2946:2946:2946) (3040:3040:3040)) + (PORT d[5] (4355:4355:4355) (4410:4410:4410)) + (PORT d[6] (2058:2058:2058) (2055:2055:2055)) + (PORT d[7] (1565:1565:1565) (1567:1567:1567)) + (PORT d[8] (2881:2881:2881) (2970:2970:2970)) + (PORT d[9] (1680:1680:1680) (1708:1708:1708)) + (PORT d[10] (1874:1874:1874) (1868:1868:1868)) + (PORT d[11] (2860:2860:2860) (2960:2960:2960)) + (PORT d[12] (4231:4231:4231) (4317:4317:4317)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2096:2096:2096) (2055:2055:2055)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1672:1672:1672)) + (PORT d[0] (2290:2290:2290) (2277:2277:2277)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1099:1099:1099) (1095:1095:1095)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2383:2383:2383) (2472:2472:2472)) + (PORT d[1] (3359:3359:3359) (3442:3442:3442)) + (PORT d[2] (1949:1949:1949) (1966:1966:1966)) + (PORT d[3] (3931:3931:3931) (3992:3992:3992)) + (PORT d[4] (2976:2976:2976) (3087:3087:3087)) + (PORT d[5] (4330:4330:4330) (4401:4401:4401)) + (PORT d[6] (2382:2382:2382) (2392:2392:2392)) + (PORT d[7] (1319:1319:1319) (1315:1315:1315)) + (PORT d[8] (2899:2899:2899) (2987:2987:2987)) + (PORT d[9] (1691:1691:1691) (1714:1714:1714)) + (PORT d[10] (1845:1845:1845) (1833:1833:1833)) + (PORT d[11] (3152:3152:3152) (3266:3266:3266)) + (PORT d[12] (4216:4216:4216) (4313:4313:4313)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1457:1457:1457) (1373:1373:1373)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (PORT d[0] (2270:2270:2270) (2199:2199:2199)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1638:1638:1638)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (779:779:779) (760:760:760)) + (PORT datab (1091:1091:1091) (1126:1126:1126)) + (PORT datac (1099:1099:1099) (1136:1136:1136)) + (PORT datad (1020:1020:1020) (1007:1007:1007)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1141:1141:1141) (1152:1152:1152)) + (PORT datab (1175:1175:1175) (1207:1207:1207)) + (PORT datac (1604:1604:1604) (1633:1633:1633)) + (PORT datad (288:288:288) (295:295:295)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~97) + (DELAY + (ABSOLUTE + (PORT dataa (2429:2429:2429) (2458:2458:2458)) + (PORT datab (1787:1787:1787) (1873:1873:1873)) + (PORT datac (2570:2570:2570) (2672:2672:2672)) + (PORT datad (2050:2050:2050) (2018:2018:2018)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1469:1469:1469) (1503:1503:1503)) + (PORT clk (1644:1644:1644) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2950:2950:2950) (3064:3064:3064)) + (PORT d[1] (3083:3083:3083) (3147:3147:3147)) + (PORT d[2] (2082:2082:2082) (2097:2097:2097)) + (PORT d[3] (3366:3366:3366) (3402:3402:3402)) + (PORT d[4] (2716:2716:2716) (2817:2817:2817)) + (PORT d[5] (4045:4045:4045) (4092:4092:4092)) + (PORT d[6] (1651:1651:1651) (1654:1654:1654)) + (PORT d[7] (1827:1827:1827) (1834:1834:1834)) + (PORT d[8] (1862:1862:1862) (1872:1872:1872)) + (PORT d[9] (1954:1954:1954) (1990:1990:1990)) + (PORT d[10] (2156:2156:2156) (2163:2163:2163)) + (PORT d[11] (2599:2599:2599) (2694:2694:2694)) + (PORT d[12] (3961:3961:3961) (4050:4050:4050)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1517:1517:1517) (1455:1455:1455)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (PORT d[0] (2606:2606:2606) (2582:2582:2582)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1601:1601:1601)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2010:2010:2010) (1977:1977:1977)) + (PORT clk (1611:1611:1611) (1608:1608:1608)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4199:4199:4199) (4120:4120:4120)) + (PORT d[1] (4132:4132:4132) (4100:4100:4100)) + (PORT d[2] (4206:4206:4206) (4076:4076:4076)) + (PORT d[3] (4107:4107:4107) (4035:4035:4035)) + (PORT d[4] (4069:4069:4069) (4073:4073:4073)) + (PORT d[5] (4037:4037:4037) (3953:3953:3953)) + (PORT d[6] (4106:4106:4106) (3960:3960:3960)) + (PORT d[7] (4098:4098:4098) (4008:4008:4008)) + (PORT d[8] (4229:4229:4229) (4129:4129:4129)) + (PORT d[9] (4232:4232:4232) (4134:4134:4134)) + (PORT d[10] (4251:4251:4251) (4159:4159:4159)) + (PORT d[11] (4122:4122:4122) (4057:4057:4057)) + (PORT d[12] (4002:4002:4002) (3877:3877:3877)) + (PORT clk (1608:1608:1608) (1605:1605:1605)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1608:1608:1608)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1612:1612:1612) (1609:1609:1609)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1612:1612:1612) (1609:1609:1609)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1612:1612:1612) (1609:1609:1609)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1612:1612:1612) (1609:1609:1609)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1570:1570:1570) (1644:1644:1644)) + (PORT d[1] (1531:1531:1531) (1530:1530:1530)) + (PORT d[2] (2098:2098:2098) (2171:2171:2171)) + (PORT d[3] (1724:1724:1724) (1724:1724:1724)) + (PORT d[4] (2211:2211:2211) (2247:2247:2247)) + (PORT d[5] (2356:2356:2356) (2342:2342:2342)) + (PORT d[6] (1841:1841:1841) (1845:1845:1845)) + (PORT d[7] (1877:1877:1877) (1902:1902:1902)) + (PORT d[8] (1969:1969:1969) (2001:2001:2001)) + (PORT d[9] (1849:1849:1849) (1839:1839:1839)) + (PORT d[10] (1533:1533:1533) (1529:1529:1529)) + (PORT d[11] (4032:4032:4032) (4182:4182:4182)) + (PORT d[12] (1993:1993:1993) (1977:1977:1977)) + (PORT clk (1642:1642:1642) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1670:1670:1670)) + (PORT d[0] (1931:1931:1931) (1867:1867:1867)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1451:1451:1451) (1474:1474:1474)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1512:1512:1512) (1569:1569:1569)) + (PORT d[1] (2761:2761:2761) (2811:2811:2811)) + (PORT d[2] (2365:2365:2365) (2395:2395:2395)) + (PORT d[3] (3083:3083:3083) (3107:3107:3107)) + (PORT d[4] (2419:2419:2419) (2507:2507:2507)) + (PORT d[5] (3525:3525:3525) (3563:3563:3563)) + (PORT d[6] (2075:2075:2075) (2077:2077:2077)) + (PORT d[7] (3157:3157:3157) (3133:3133:3133)) + (PORT d[8] (2711:2711:2711) (2760:2760:2760)) + (PORT d[9] (2286:2286:2286) (2337:2337:2337)) + (PORT d[10] (2419:2419:2419) (2432:2432:2432)) + (PORT d[11] (2319:2319:2319) (2402:2402:2402)) + (PORT d[12] (4285:4285:4285) (4364:4364:4364)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2616:2616:2616) (2589:2589:2589)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT d[0] (2893:2893:2893) (2895:2895:2895)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1600:1600:1600)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1797:1797:1797) (1757:1757:1757)) + (PORT clk (1610:1610:1610) (1607:1607:1607)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4160:4160:4160) (4037:4037:4037)) + (PORT d[1] (4104:4104:4104) (4045:4045:4045)) + (PORT d[2] (4197:4197:4197) (4054:4054:4054)) + (PORT d[3] (3899:3899:3899) (3838:3838:3838)) + (PORT d[4] (3999:3999:3999) (3981:3981:3981)) + (PORT d[5] (4055:4055:4055) (3981:3981:3981)) + (PORT d[6] (4096:4096:4096) (3971:3971:3971)) + (PORT d[7] (3874:3874:3874) (3779:3779:3779)) + (PORT d[8] (4080:4080:4080) (3975:3975:3975)) + (PORT d[9] (4070:4070:4070) (3994:3994:3994)) + (PORT d[10] (3980:3980:3980) (3891:3891:3891)) + (PORT d[11] (4145:4145:4145) (4087:4087:4087)) + (PORT d[12] (4127:4127:4127) (3949:3949:3949)) + (PORT clk (1607:1607:1607) (1604:1604:1604)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1607:1607:1607)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1608:1608:1608)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1608:1608:1608)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1608:1608:1608)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1608:1608:1608)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1601:1601:1601)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1544:1544:1544) (1606:1606:1606)) + (PORT d[1] (2499:2499:2499) (2543:2543:2543)) + (PORT d[2] (1955:1955:1955) (2002:2002:2002)) + (PORT d[3] (3077:3077:3077) (3098:3098:3098)) + (PORT d[4] (2136:2136:2136) (2206:2206:2206)) + (PORT d[5] (3465:3465:3465) (3498:3498:3498)) + (PORT d[6] (2348:2348:2348) (2357:2357:2357)) + (PORT d[7] (3181:3181:3181) (3148:3148:3148)) + (PORT d[8] (2706:2706:2706) (2753:2753:2753)) + (PORT d[9] (2552:2552:2552) (2610:2610:2610)) + (PORT d[10] (2154:2154:2154) (2163:2163:2163)) + (PORT d[11] (2306:2306:2306) (2384:2384:2384)) + (PORT d[12] (3248:3248:3248) (3331:3331:3331)) + (PORT clk (1646:1646:1646) (1675:1675:1675)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1675:1675:1675)) + (PORT d[0] (2384:2384:2384) (2376:2376:2376)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1676:1676:1676)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1641:1641:1641)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (888:888:888)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (889:889:889)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (889:889:889)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (889:889:889)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1118:1118:1118) (1132:1132:1132)) + (PORT datab (670:670:670) (696:696:696)) + (PORT datac (1246:1246:1246) (1244:1244:1244)) + (PORT datad (1308:1308:1308) (1313:1313:1313)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (675:675:675)) + (PORT datab (1027:1027:1027) (982:982:982)) + (PORT datac (1436:1436:1436) (1461:1461:1461)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~116) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (229:229:229)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (898:898:898) (930:930:930)) + (PORT datad (568:568:568) (584:584:584)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~117) + (DELAY + (ABSOLUTE + (PORT dataa (1130:1130:1130) (1127:1127:1127)) + (PORT datab (2298:2298:2298) (2286:2286:2286)) + (PORT datac (1102:1102:1102) (1110:1110:1110)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (352:352:352)) + (PORT datab (386:386:386) (416:416:416)) + (PORT datac (1073:1073:1073) (1102:1102:1102)) + (PORT datad (1050:1050:1050) (1030:1030:1030)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (763:763:763) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (392:392:392) (401:401:401)) + (PORT datac (549:549:549) (542:542:542)) + (PORT datad (219:219:219) (277:277:277)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (618:618:618) (625:625:625)) + (PORT clrn (1396:1396:1396) (1368:1368:1368)) + (PORT ena (1787:1787:1787) (1726:1726:1726)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~0) + (DELAY + (ABSOLUTE + (PORT datac (1019:1019:1019) (1041:1041:1041)) + (PORT datad (1812:1812:1812) (1831:1831:1831)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2355:2355:2355) (2370:2370:2370)) + (PORT datab (1942:1942:1942) (1983:1983:1983)) + (PORT datac (2252:2252:2252) (2362:2362:2362)) + (PORT datad (1696:1696:1696) (1725:1725:1725)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1493:1493:1493) (1502:1502:1502)) + (PORT datab (533:533:533) (520:520:520)) + (PORT datac (782:782:782) (774:774:774)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (635:635:635)) + (PORT datab (792:792:792) (841:841:841)) + (PORT datac (1339:1339:1339) (1320:1320:1320)) + (PORT datad (1071:1071:1071) (1072:1072:1072)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2120:2120:2120) (2150:2150:2150)) + (PORT datab (2017:2017:2017) (2098:2098:2098)) + (PORT datac (1096:1096:1096) (1146:1146:1146)) + (PORT datad (754:754:754) (807:807:807)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instCB) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1384:1384:1384) (1355:1355:1355)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~0) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (753:753:753)) + (PORT datab (696:696:696) (740:740:740)) + (PORT datac (1686:1686:1686) (1771:1771:1771)) + (PORT datad (1553:1553:1553) (1559:1559:1559)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (910:910:910)) + (PORT datab (1090:1090:1090) (1109:1109:1109)) + (PORT datac (1747:1747:1747) (1755:1755:1755)) + (PORT datad (1325:1325:1325) (1301:1301:1301)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im1) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (853:853:853) (842:842:842)) + (PORT clrn (1396:1396:1396) (1368:1368:1368)) + (PORT ena (889:889:889) (877:877:877)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (605:605:605)) + (PORT datab (893:893:893) (909:909:909)) + (PORT datad (329:329:329) (374:374:374)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (861:861:861)) + (PORT datab (923:923:923) (949:949:949)) + (PORT datac (571:571:571) (578:578:578)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (605:605:605)) + (PORT datab (189:189:189) (226:226:226)) + (PORT datac (1085:1085:1085) (1078:1078:1078)) + (PORT datad (791:791:791) (790:790:790)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1400:1400:1400) (1428:1428:1428)) + (PORT datab (1163:1163:1163) (1155:1155:1155)) + (PORT datac (1073:1073:1073) (1075:1075:1075)) + (PORT datad (1374:1374:1374) (1360:1360:1360)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (608:608:608)) + (PORT datab (1349:1349:1349) (1324:1324:1324)) + (PORT datac (476:476:476) (460:460:460)) + (PORT datad (885:885:885) (911:911:911)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) + (DELAY + (ABSOLUTE + (PORT datac (837:837:837) (840:840:840)) + (PORT datad (569:569:569) (580:580:580)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (232:232:232)) + (PORT datab (358:358:358) (362:362:362)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (492:492:492) (477:477:477)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (911:911:911)) + (PORT datab (862:862:862) (917:917:917)) + (PORT datac (227:227:227) (303:303:303)) + (PORT datad (243:243:243) (311:311:311)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~1) + (DELAY + (ABSOLUTE + (PORT datac (665:665:665) (725:725:725)) + (PORT datad (929:929:929) (969:969:969)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (396:396:396)) + (PORT datab (313:313:313) (331:331:331)) + (PORT datac (682:682:682) (741:741:741)) + (PORT datad (541:541:541) (529:529:529)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (220:220:220)) + (PORT datab (718:718:718) (754:754:754)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1327:1327:1327) (1346:1346:1346)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1370:1370:1370) (1350:1350:1350)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (377:377:377)) + (PORT datab (637:637:637) (662:662:662)) + (PORT datac (832:832:832) (856:856:856)) + (PORT datad (875:875:875) (915:915:915)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (687:687:687) (749:749:749)) + (PORT datab (696:696:696) (757:757:757)) + (PORT datac (645:645:645) (686:686:686)) + (PORT datad (892:892:892) (918:918:918)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~85) + (DELAY + (ABSOLUTE + (PORT datab (970:970:970) (1006:1006:1006)) + (PORT datad (168:168:168) (193:193:193)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (614:614:614)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (643:643:643) (685:685:685)) + (PORT datad (488:488:488) (477:477:477)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (338:338:338)) + (PORT datab (722:722:722) (759:759:759)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1327:1327:1327) (1346:1346:1346)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1370:1370:1370) (1350:1350:1350)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (292:292:292)) + (PORT datab (879:879:879) (894:894:894)) + (PORT datac (735:735:735) (725:725:725)) + (PORT datad (200:200:200) (257:257:257)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (449:449:449) (510:510:510)) + (PORT datab (928:928:928) (966:966:966)) + (PORT datac (612:612:612) (646:646:646)) + (PORT datad (577:577:577) (610:610:610)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (449:449:449) (510:510:510)) + (PORT datac (693:693:693) (744:744:744)) + (PORT datad (357:357:357) (405:405:405)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (996:996:996)) + (PORT datac (829:829:829) (824:824:824)) + (PORT datad (664:664:664) (705:705:705)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (222:222:222)) + (PORT datab (185:185:185) (218:218:218)) + (PORT datad (539:539:539) (529:529:529)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1365:1365:1365) (1346:1346:1346)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (556:556:556)) + (PORT datab (970:970:970) (1006:1006:1006)) + (PORT datac (659:659:659) (718:718:718)) + (PORT datad (168:168:168) (193:193:193)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (193:193:193) (234:234:234)) + (PORT datab (526:526:526) (514:514:514)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1326:1326:1326) (1345:1345:1345)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1369:1369:1369) (1349:1349:1349)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (256:256:256)) + (PORT datab (206:206:206) (242:242:242)) + (PORT datac (858:858:858) (870:870:870)) + (PORT datad (576:576:576) (591:591:591)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (719:719:719)) + (PORT datab (932:932:932) (990:990:990)) + (PORT datac (889:889:889) (928:928:928)) + (PORT datad (537:537:537) (535:535:535)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (1203:1203:1203) (1267:1267:1267)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1373:1373:1373) (1354:1354:1354)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~68) + (DELAY + (ABSOLUTE + (PORT datab (599:599:599) (630:630:630)) + (PORT datac (909:909:909) (950:950:950)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (680:680:680) (733:733:733)) + (PORT datab (897:897:897) (940:940:940)) + (PORT datac (681:681:681) (747:747:747)) + (PORT datad (841:841:841) (869:869:869)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~69) + (DELAY + (ABSOLUTE + (PORT dataa (452:452:452) (516:516:516)) + (PORT datab (183:183:183) (217:217:217)) + (PORT datac (868:868:868) (906:906:906)) + (PORT datad (175:175:175) (204:204:204)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (812:812:812)) + (PORT datab (183:183:183) (214:214:214)) + (PORT datac (560:560:560) (552:552:552)) + (PORT datad (664:664:664) (700:700:700)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (390:390:390) (448:448:448)) + (PORT datac (675:675:675) (743:743:743)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (1007:1007:1007)) + (PORT datab (555:555:555) (590:590:590)) + (PORT datac (912:912:912) (950:950:950)) + (PORT datad (564:564:564) (596:596:596)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~71) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (626:626:626)) + (PORT datab (699:699:699) (738:738:738)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (237:237:237) (305:305:305)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (221:221:221)) + (PORT datab (697:697:697) (726:726:726)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1348:1348:1348)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1364:1364:1364) (1345:1345:1345)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1374:1374:1374) (1400:1400:1400)) + (PORT datac (2108:2108:2108) (2239:2239:2239)) + (PORT datad (815:815:815) (836:836:836)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (716:716:716)) + (PORT datac (890:890:890) (927:927:927)) + (PORT datad (538:538:538) (533:533:533)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (1204:1204:1204) (1270:1270:1270)) + (PORT datab (933:933:933) (989:989:989)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1373:1373:1373) (1354:1354:1354)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (396:396:396)) + (PORT datab (671:671:671) (713:713:713)) + (PORT datac (826:826:826) (864:864:864)) + (PORT datad (180:180:180) (212:212:212)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (1203:1203:1203) (1270:1270:1270)) + (PORT datab (887:887:887) (883:883:883)) + (PORT datad (556:556:556) (540:540:540)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1373:1373:1373) (1354:1354:1354)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (250:250:250)) + (PORT datab (2590:2590:2590) (2690:2690:2690)) + (PORT datac (194:194:194) (260:260:260)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (295:295:295)) + (PORT datab (202:202:202) (236:236:236)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (836:836:836)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (2187:2187:2187) (2316:2316:2316)) + (PORT datad (574:574:574) (567:567:567)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1125:1125:1125) (1122:1122:1122)) + (PORT clk (1630:1630:1630) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2491:2491:2491) (2624:2624:2624)) + (PORT d[1] (2663:2663:2663) (2681:2681:2681)) + (PORT d[2] (947:947:947) (954:954:954)) + (PORT d[3] (906:906:906) (926:926:926)) + (PORT d[4] (1903:1903:1903) (1925:1925:1925)) + (PORT d[5] (902:902:902) (914:914:914)) + (PORT d[6] (1575:1575:1575) (1568:1568:1568)) + (PORT d[7] (2453:2453:2453) (2523:2523:2523)) + (PORT d[8] (2303:2303:2303) (2408:2408:2408)) + (PORT d[9] (697:697:697) (722:722:722)) + (PORT d[10] (689:689:689) (715:715:715)) + (PORT d[11] (2616:2616:2616) (2714:2714:2714)) + (PORT d[12] (400:400:400) (421:421:421)) + (PORT clk (1627:1627:1627) (1656:1656:1656)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1401:1401:1401) (1351:1351:1351)) + (PORT clk (1627:1627:1627) (1656:1656:1656)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1630:1630:1630) (1658:1658:1658)) + (PORT d[0] (1328:1328:1328) (1280:1280:1280)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1594:1594:1594) (1622:1622:1622)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (865:865:865) (869:869:869)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (882:882:882) (878:878:878)) + (PORT clk (1638:1638:1638) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2819:2819:2819) (2973:2973:2973)) + (PORT d[1] (1497:1497:1497) (1523:1523:1523)) + (PORT d[2] (925:925:925) (939:939:939)) + (PORT d[3] (880:880:880) (895:895:895)) + (PORT d[4] (1090:1090:1090) (1067:1067:1067)) + (PORT d[5] (886:886:886) (894:894:894)) + (PORT d[6] (1439:1439:1439) (1501:1501:1501)) + (PORT d[7] (911:911:911) (907:907:907)) + (PORT d[8] (1193:1193:1193) (1230:1230:1230)) + (PORT d[9] (715:715:715) (754:754:754)) + (PORT d[10] (674:674:674) (707:707:707)) + (PORT d[11] (2301:2301:2301) (2386:2386:2386)) + (PORT d[12] (985:985:985) (1022:1022:1022)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (860:860:860) (811:811:811)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (PORT d[0] (1853:1853:1853) (1826:1826:1826)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1630:1630:1630)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (933:933:933) (939:939:939)) + (PORT clk (1636:1636:1636) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2800:2800:2800) (2938:2938:2938)) + (PORT d[1] (1764:1764:1764) (1795:1795:1795)) + (PORT d[2] (1186:1186:1186) (1197:1197:1197)) + (PORT d[3] (1175:1175:1175) (1179:1179:1179)) + (PORT d[4] (1374:1374:1374) (1372:1372:1372)) + (PORT d[5] (623:623:623) (623:623:623)) + (PORT d[6] (1696:1696:1696) (1760:1760:1760)) + (PORT d[7] (2706:2706:2706) (2777:2777:2777)) + (PORT d[8] (1181:1181:1181) (1213:1213:1213)) + (PORT d[9] (933:933:933) (957:957:957)) + (PORT d[10] (669:669:669) (699:699:699)) + (PORT d[11] (2339:2339:2339) (2427:2427:2427)) + (PORT d[12] (714:714:714) (754:754:754)) + (PORT clk (1633:1633:1633) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (860:860:860) (812:812:812)) + (PORT clk (1633:1633:1633) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1662:1662:1662)) + (PORT d[0] (1631:1631:1631) (1604:1604:1604)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1600:1600:1600) (1626:1626:1626)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~56) + (INSTANCE D\[0\]\~62) (DELAY (ABSOLUTE - (PORT dataa (981:981:981) (936:936:936)) - (PORT datab (1299:1299:1299) (1349:1349:1349)) - (PORT datac (502:502:502) (483:483:483)) - (PORT datad (1089:1089:1089) (1062:1062:1062)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) + (PORT dataa (972:972:972) (1021:1021:1021)) + (PORT datab (887:887:887) (930:930:930)) + (PORT datac (824:824:824) (801:801:801)) + (PORT datad (860:860:860) (863:863:863)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -39940,11 +42066,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1522:1522:1522) (1552:1552:1552)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) + (PORT d[0] (1306:1306:1306) (1298:1298:1298)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) ) ) (TIMINGCHECK @@ -39953,23 +42079,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2671:2671:2671) (2689:2689:2689)) - (PORT d[1] (1867:1867:1867) (1957:1957:1957)) - (PORT d[2] (1810:1810:1810) (1839:1839:1839)) - (PORT d[3] (1758:1758:1758) (1816:1816:1816)) - (PORT d[4] (2803:2803:2803) (2841:2841:2841)) - (PORT d[5] (2060:2060:2060) (2153:2153:2153)) - (PORT d[6] (1591:1591:1591) (1614:1614:1614)) - (PORT d[7] (1980:1980:1980) (2023:2023:2023)) - (PORT d[8] (2256:2256:2256) (2327:2327:2327)) - (PORT d[9] (1564:1564:1564) (1597:1597:1597)) - (PORT d[10] (1345:1345:1345) (1361:1361:1361)) - (PORT d[11] (1607:1607:1607) (1625:1625:1625)) - (PORT d[12] (2124:2124:2124) (2140:2140:2140)) - (PORT clk (1640:1640:1640) (1669:1669:1669)) + (PORT d[0] (2300:2300:2300) (2365:2365:2365)) + (PORT d[1] (2336:2336:2336) (2336:2336:2336)) + (PORT d[2] (2373:2373:2373) (2464:2464:2464)) + (PORT d[3] (4241:4241:4241) (4317:4317:4317)) + (PORT d[4] (2716:2716:2716) (2753:2753:2753)) + (PORT d[5] (2909:2909:2909) (2914:2914:2914)) + (PORT d[6] (1369:1369:1369) (1354:1354:1354)) + (PORT d[7] (1294:1294:1294) (1288:1288:1288)) + (PORT d[8] (2307:2307:2307) (2367:2367:2367)) + (PORT d[9] (1560:1560:1560) (1529:1529:1529)) + (PORT d[10] (2347:2347:2347) (2353:2353:2353)) + (PORT d[11] (3434:3434:3434) (3555:3555:3555)) + (PORT d[12] (2305:2305:2305) (2306:2306:2306)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) ) ) (TIMINGCHECK @@ -39978,11 +42104,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2368:2368:2368) (2344:2344:2344)) - (PORT clk (1640:1640:1640) (1669:1669:1669)) + (PORT d[0] (1831:1831:1831) (1769:1769:1769)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) ) ) (TIMINGCHECK @@ -39991,60 +42117,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) - (PORT d[0] (3338:3338:3338) (3343:3343:3343)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (PORT d[0] (1765:1765:1765) (1703:1703:1703)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1644:1644:1644) (1672:1672:1672)) + (PORT clk (1639:1639:1639) (1666:1666:1666)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1644:1644:1644) (1672:1672:1672)) + (PORT clk (1639:1639:1639) (1666:1666:1666)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1644:1644:1644) (1672:1672:1672)) + (PORT clk (1639:1639:1639) (1666:1666:1666)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1644:1644:1644) (1672:1672:1672)) + (PORT clk (1639:1639:1639) (1666:1666:1666)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1602:1602:1602) (1601:1601:1601)) + (PORT clk (1602:1602:1602) (1629:1629:1629)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -40055,199 +42181,55 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (1885:1885:1885) (1823:1823:1823)) - (PORT clk (1610:1610:1610) (1608:1608:1608)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4094:4094:4094) (4004:4004:4004)) - (PORT d[1] (3872:3872:3872) (3773:3773:3773)) - (PORT d[2] (3969:3969:3969) (3885:3885:3885)) - (PORT d[3] (4229:4229:4229) (4158:4158:4158)) - (PORT d[4] (4027:4027:4027) (3879:3879:3879)) - (PORT d[5] (4301:4301:4301) (4209:4209:4209)) - (PORT d[6] (4101:4101:4101) (4071:4071:4071)) - (PORT d[7] (4030:4030:4030) (3869:3869:3869)) - (PORT d[8] (4251:4251:4251) (4163:4163:4163)) - (PORT d[9] (4115:4115:4115) (4191:4191:4191)) - (PORT d[10] (4389:4389:4389) (4323:4323:4323)) - (PORT d[11] (4066:4066:4066) (3954:3954:3954)) - (PORT d[12] (4192:4192:4192) (4207:4207:4207)) - (PORT clk (1607:1607:1607) (1605:1605:1605)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1608:1608:1608)) + (PORT clk (873:873:873) (876:876:876)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1611:1611:1611) (1609:1609:1609)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + (PORT clk (874:874:874) (877:877:877)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1611:1611:1611) (1609:1609:1609)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1609:1609:1609)) + (PORT clk (874:874:874) (877:877:877)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1611:1611:1611) (1609:1609:1609)) + (PORT clk (874:874:874) (877:877:877)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~63) (DELAY (ABSOLUTE - (PORT clk (1603:1603:1603) (1602:1602:1602)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2638:2638:2638) (2644:2644:2644)) - (PORT d[1] (1609:1609:1609) (1700:1700:1700)) - (PORT d[2] (1788:1788:1788) (1834:1834:1834)) - (PORT d[3] (1753:1753:1753) (1800:1800:1800)) - (PORT d[4] (2573:2573:2573) (2629:2629:2629)) - (PORT d[5] (2062:2062:2062) (2159:2159:2159)) - (PORT d[6] (1861:1861:1861) (1879:1879:1879)) - (PORT d[7] (1974:1974:1974) (2042:2042:2042)) - (PORT d[8] (2218:2218:2218) (2298:2298:2298)) - (PORT d[9] (1820:1820:1820) (1861:1861:1861)) - (PORT d[10] (1844:1844:1844) (1851:1851:1851)) - (PORT d[11] (1877:1877:1877) (1899:1899:1899)) - (PORT d[12] (2378:2378:2378) (2399:2399:2399)) - (PORT clk (1644:1644:1644) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1672:1672:1672)) - (PORT d[0] (2530:2530:2530) (2508:2508:2508)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1638:1638:1638)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (883:883:883) (886:886:886)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (883:883:883) (886:886:886)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (883:883:883) (886:886:886)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + (PORT dataa (1113:1113:1113) (1126:1126:1126)) + (PORT datab (1431:1431:1431) (1502:1502:1502)) + (PORT datac (327:327:327) (332:332:332)) + (PORT datad (1234:1234:1234) (1215:1215:1215)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -40256,8 +42238,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1503:1503:1503) (1531:1531:1531)) - (PORT clk (1641:1641:1641) (1669:1669:1669)) + (PORT d[0] (1466:1466:1466) (1476:1476:1476)) + (PORT clk (1645:1645:1645) (1673:1673:1673)) ) ) (TIMINGCHECK @@ -40269,20 +42251,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2666:2666:2666) (2687:2687:2687)) - (PORT d[1] (1897:1897:1897) (1996:1996:1996)) - (PORT d[2] (1753:1753:1753) (1779:1779:1779)) - (PORT d[3] (1747:1747:1747) (1800:1800:1800)) - (PORT d[4] (2818:2818:2818) (2858:2858:2858)) - (PORT d[5] (1809:1809:1809) (1901:1901:1901)) - (PORT d[6] (1611:1611:1611) (1617:1617:1617)) - (PORT d[7] (1692:1692:1692) (1718:1718:1718)) - (PORT d[8] (2251:2251:2251) (2328:2328:2328)) - (PORT d[9] (1828:1828:1828) (1861:1861:1861)) - (PORT d[10] (1856:1856:1856) (1882:1882:1882)) - (PORT d[11] (2347:2347:2347) (2365:2365:2365)) - (PORT d[12] (2075:2075:2075) (2105:2105:2105)) - (PORT clk (1638:1638:1638) (1667:1667:1667)) + (PORT d[0] (2327:2327:2327) (2380:2380:2380)) + (PORT d[1] (1965:1965:1965) (2005:2005:2005)) + (PORT d[2] (2233:2233:2233) (2277:2277:2277)) + (PORT d[3] (1943:1943:1943) (1987:1987:1987)) + (PORT d[4] (1923:1923:1923) (1958:1958:1958)) + (PORT d[5] (2143:2143:2143) (2185:2185:2185)) + (PORT d[6] (2157:2157:2157) (2215:2215:2215)) + (PORT d[7] (3196:3196:3196) (3235:3235:3235)) + (PORT d[8] (2645:2645:2645) (2674:2674:2674)) + (PORT d[9] (1870:1870:1870) (1972:1972:1972)) + (PORT d[10] (3334:3334:3334) (3376:3376:3376)) + (PORT d[11] (2005:2005:2005) (2053:2053:2053)) + (PORT d[12] (1826:1826:1826) (1919:1919:1919)) + (PORT clk (1642:1642:1642) (1671:1671:1671)) ) ) (TIMINGCHECK @@ -40294,8 +42276,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2330:2330:2330) (2279:2279:2279)) - (PORT clk (1638:1638:1638) (1667:1667:1667)) + (PORT d[0] (1816:1816:1816) (1751:1751:1751)) + (PORT clk (1642:1642:1642) (1671:1671:1671)) ) ) (TIMINGCHECK @@ -40307,8 +42289,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (PORT d[0] (3368:3368:3368) (3356:3356:3356)) + (PORT clk (1645:1645:1645) (1673:1673:1673)) + (PORT d[0] (2935:2935:2935) (2952:2952:2952)) ) ) ) @@ -40317,7 +42299,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) @@ -40327,7 +42309,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -40337,7 +42319,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -40347,7 +42329,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -40357,7 +42339,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1600:1600:1600) (1599:1599:1599)) + (PORT clk (1604:1604:1604) (1603:1603:1603)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -40371,8 +42353,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1887:1887:1887) (1819:1819:1819)) - (PORT clk (1608:1608:1608) (1606:1606:1606)) + (PORT d[0] (1987:1987:1987) (2006:2006:2006)) + (PORT clk (1612:1612:1612) (1610:1610:1610)) ) ) (TIMINGCHECK @@ -40384,20 +42366,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4135:4135:4135) (4045:4045:4045)) - (PORT d[1] (3941:3941:3941) (3838:3838:3838)) - (PORT d[2] (3995:3995:3995) (3898:3898:3898)) - (PORT d[3] (4226:4226:4226) (4152:4152:4152)) - (PORT d[4] (4046:4046:4046) (3907:3907:3907)) - (PORT d[5] (4290:4290:4290) (4190:4190:4190)) - (PORT d[6] (4375:4375:4375) (4339:4339:4339)) - (PORT d[7] (4037:4037:4037) (3866:3866:3866)) - (PORT d[8] (4167:4167:4167) (4039:4039:4039)) - (PORT d[9] (4129:4129:4129) (4216:4216:4216)) - (PORT d[10] (4314:4314:4314) (4238:4238:4238)) - (PORT d[11] (4075:4075:4075) (3952:3952:3952)) - (PORT d[12] (4191:4191:4191) (4206:4206:4206)) - (PORT clk (1605:1605:1605) (1603:1603:1603)) + (PORT d[0] (4032:4032:4032) (3948:3948:3948)) + (PORT d[1] (4163:4163:4163) (4141:4141:4141)) + (PORT d[2] (4233:4233:4233) (4120:4120:4120)) + (PORT d[3] (3992:3992:3992) (3977:3977:3977)) + (PORT d[4] (4079:4079:4079) (4027:4027:4027)) + (PORT d[5] (4116:4116:4116) (4106:4106:4106)) + (PORT d[6] (4231:4231:4231) (4154:4154:4154)) + (PORT d[7] (4020:4020:4020) (3901:3901:3901)) + (PORT d[8] (4079:4079:4079) (4042:4042:4042)) + (PORT d[9] (4173:4173:4173) (4057:4057:4057)) + (PORT d[10] (4101:4101:4101) (4044:4044:4044)) + (PORT d[11] (4113:4113:4113) (4060:4060:4060)) + (PORT d[12] (4066:4066:4066) (3898:3898:3898)) + (PORT clk (1609:1609:1609) (1607:1607:1607)) ) ) (TIMINGCHECK @@ -40409,7 +42391,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1608:1608:1608) (1606:1606:1606)) + (PORT clk (1612:1612:1612) (1610:1610:1610)) ) ) ) @@ -40418,7 +42400,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1609:1609:1609) (1607:1607:1607)) + (PORT clk (1613:1613:1613) (1611:1611:1611)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) @@ -40428,7 +42410,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1609:1609:1609) (1607:1607:1607)) + (PORT clk (1613:1613:1613) (1611:1611:1611)) ) ) ) @@ -40437,7 +42419,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1609:1609:1609) (1607:1607:1607)) + (PORT clk (1613:1613:1613) (1611:1611:1611)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -40447,46 +42429,359 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1609:1609:1609) (1607:1607:1607)) + (PORT clk (1613:1613:1613) (1611:1611:1611)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1841:1841:1841) (1901:1901:1901)) + (PORT d[1] (2032:2032:2032) (1999:1999:1999)) + (PORT d[2] (2067:2067:2067) (2148:2148:2148)) + (PORT d[3] (1598:1598:1598) (1596:1596:1596)) + (PORT d[4] (2140:2140:2140) (2176:2176:2176)) + (PORT d[5] (2594:2594:2594) (2578:2578:2578)) + (PORT d[6] (1613:1613:1613) (1625:1625:1625)) + (PORT d[7] (1823:1823:1823) (1818:1818:1818)) + (PORT d[8] (2024:2024:2024) (2071:2071:2071)) + (PORT d[9] (1846:1846:1846) (1833:1833:1833)) + (PORT d[10] (2316:2316:2316) (2294:2294:2294)) + (PORT d[11] (4003:4003:4003) (4148:4148:4148)) + (PORT d[12] (2003:2003:2003) (1997:1997:1997)) + (PORT clk (1641:1641:1641) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1668:1668:1668)) + (PORT d[0] (1962:1962:1962) (1910:1910:1910)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1634:1634:1634)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (881:881:881)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~52) + (INSTANCE D\[0\]\~59) (DELAY (ABSOLUTE - (PORT dataa (1129:1129:1129) (1172:1172:1172)) - (PORT datab (1335:1335:1335) (1318:1318:1318)) - (PORT datac (1047:1047:1047) (1062:1062:1062)) - (PORT datad (1324:1324:1324) (1319:1319:1319)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (857:857:857) (859:859:859)) + (PORT datab (713:713:713) (775:775:775)) + (PORT datac (1110:1110:1110) (1110:1110:1110)) + (PORT datad (1546:1546:1546) (1546:1546:1546)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1371:1371:1371) (1374:1374:1374)) + (PORT clk (1653:1653:1653) (1680:1680:1680)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2044:2044:2044) (2084:2084:2084)) + (PORT d[1] (2434:2434:2434) (2484:2484:2484)) + (PORT d[2] (2184:2184:2184) (2234:2234:2234)) + (PORT d[3] (2821:2821:2821) (2834:2834:2834)) + (PORT d[4] (2112:2112:2112) (2174:2174:2174)) + (PORT d[5] (3186:3186:3186) (3199:3199:3199)) + (PORT d[6] (2347:2347:2347) (2361:2361:2361)) + (PORT d[7] (2735:2735:2735) (2737:2737:2737)) + (PORT d[8] (2446:2446:2446) (2488:2488:2488)) + (PORT d[9] (2740:2740:2740) (2791:2791:2791)) + (PORT d[10] (2137:2137:2137) (2134:2134:2134)) + (PORT d[11] (2069:2069:2069) (2137:2137:2137)) + (PORT d[12] (3266:3266:3266) (3331:3331:3331)) + (PORT clk (1650:1650:1650) (1678:1678:1678)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2370:2370:2370) (2321:2321:2321)) + (PORT clk (1650:1650:1650) (1678:1678:1678)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (PORT d[0] (3196:3196:3196) (3184:3184:3184)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1681:1681:1681)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1681:1681:1681)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1681:1681:1681)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1681:1681:1681)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1612:1612:1612) (1610:1610:1610)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2021:2021:2021) (1988:1988:1988)) + (PORT clk (1620:1620:1620) (1617:1617:1617)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4178:4178:4178) (4052:4052:4052)) + (PORT d[1] (4135:4135:4135) (4061:4061:4061)) + (PORT d[2] (4153:4153:4153) (4015:4015:4015)) + (PORT d[3] (4095:4095:4095) (4025:4025:4025)) + (PORT d[4] (3950:3950:3950) (3909:3909:3909)) + (PORT d[5] (4139:4139:4139) (4063:4063:4063)) + (PORT d[6] (3944:3944:3944) (3864:3864:3864)) + (PORT d[7] (4095:4095:4095) (4013:4013:4013)) + (PORT d[8] (4078:4078:4078) (4028:4028:4028)) + (PORT d[9] (4043:4043:4043) (3945:3945:3945)) + (PORT d[10] (3975:3975:3975) (3864:3864:3864)) + (PORT d[11] (4166:4166:4166) (4042:4042:4042)) + (PORT d[12] (4008:4008:4008) (3886:3886:3886)) + (PORT clk (1617:1617:1617) (1614:1614:1614)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1620:1620:1620) (1617:1617:1617)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1621:1621:1621) (1618:1618:1618)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1621:1621:1621) (1618:1618:1618)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1621:1621:1621) (1618:1618:1618)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1621:1621:1621) (1618:1618:1618)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1611:1611:1611)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3372:3372:3372) (3445:3445:3445)) - (PORT d[1] (2443:2443:2443) (2564:2564:2564)) - (PORT d[2] (1520:1520:1520) (1542:1542:1542)) - (PORT d[3] (1998:1998:1998) (2040:2040:2040)) - (PORT d[4] (2014:2014:2014) (2036:2036:2036)) - (PORT d[5] (1537:1537:1537) (1604:1604:1604)) - (PORT d[6] (1058:1058:1058) (1070:1070:1070)) - (PORT d[7] (1084:1084:1084) (1098:1098:1098)) - (PORT d[8] (2012:2012:2012) (2097:2097:2097)) - (PORT d[9] (2103:2103:2103) (2157:2157:2157)) - (PORT d[10] (2374:2374:2374) (2416:2416:2416)) - (PORT d[11] (865:865:865) (853:853:853)) - (PORT d[12] (1628:1628:1628) (1646:1646:1646)) - (PORT clk (1634:1634:1634) (1662:1662:1662)) + (PORT d[0] (2081:2081:2081) (2158:2158:2158)) + (PORT d[1] (1020:1020:1020) (1010:1010:1010)) + (PORT d[2] (2446:2446:2446) (2469:2469:2469)) + (PORT d[3] (4243:4243:4243) (4308:4308:4308)) + (PORT d[4] (930:930:930) (946:946:946)) + (PORT d[5] (2034:2034:2034) (1999:1999:1999)) + (PORT d[6] (2635:2635:2635) (2656:2656:2656)) + (PORT d[7] (1307:1307:1307) (1283:1283:1283)) + (PORT d[8] (2560:2560:2560) (2621:2621:2621)) + (PORT d[9] (1372:1372:1372) (1367:1367:1367)) + (PORT d[10] (1867:1867:1867) (1854:1854:1854)) + (PORT d[11] (3462:3462:3462) (3595:3595:3595)) + (PORT d[12] (1576:1576:1576) (1578:1578:1578)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) ) ) (TIMINGCHECK @@ -40498,8 +42793,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1634:1634:1634) (1662:1662:1662)) - (PORT d[0] (3098:3098:3098) (3083:3083:3083)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (PORT d[0] (1190:1190:1190) (1233:1233:1233)) ) ) ) @@ -40508,7 +42803,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -40518,7 +42813,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1601:1601:1601) (1628:1628:1628)) + (PORT clk (1607:1607:1607) (1634:1634:1634)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -40532,7 +42827,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (872:872:872) (875:875:875)) + (PORT clk (878:878:878) (881:881:881)) ) ) ) @@ -40541,7 +42836,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (873:873:873) (876:876:876)) + (PORT clk (879:879:879) (882:882:882)) ) ) ) @@ -40550,7 +42845,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (873:873:873) (876:876:876)) + (PORT clk (879:879:879) (882:882:882)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -40560,22 +42855,22 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (873:873:873) (876:876:876)) + (PORT clk (879:879:879) (882:882:882)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~53) + (INSTANCE D\[0\]\~60) (DELAY (ABSOLUTE - (PORT dataa (1118:1118:1118) (1097:1097:1097)) - (PORT datab (995:995:995) (975:975:975)) - (PORT datac (164:164:164) (198:198:198)) - (PORT datad (1280:1280:1280) (1263:1263:1263)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (324:324:324)) + (PORT dataa (1079:1079:1079) (1065:1065:1065)) + (PORT datab (882:882:882) (853:853:853)) + (PORT datac (923:923:923) (961:961:961)) + (PORT datad (168:168:168) (194:194:194)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -40583,29 +42878,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~54) + (INSTANCE D\[0\]\~61) (DELAY (ABSOLUTE - (PORT dataa (1401:1401:1401) (1430:1430:1430)) - (PORT datab (885:885:885) (897:897:897)) - (PORT datac (162:162:162) (196:196:196)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (189:189:189) (228:228:228)) + (PORT datab (713:713:713) (779:779:779)) + (PORT datac (1754:1754:1754) (1751:1751:1751)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~106) + (INSTANCE D\[0\]\~120) (DELAY (ABSOLUTE - (PORT dataa (629:629:629) (693:693:693)) - (PORT datab (1093:1093:1093) (1105:1105:1105)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (159:159:159) (179:179:179)) + (PORT dataa (1596:1596:1596) (1607:1607:1607)) + (PORT datab (2775:2775:2775) (2913:2913:2913)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (160:160:160) (181:181:181)) (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -40615,31 +42910,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~57) + (INSTANCE D\[0\]\~64) (DELAY (ABSOLUTE - (PORT dataa (1837:1837:1837) (1832:1832:1832)) - (PORT datab (1053:1053:1053) (1081:1081:1081)) - (PORT datac (162:162:162) (196:196:196)) - (PORT datad (772:772:772) (778:778:778)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (842:842:842) (852:852:852)) + (PORT datab (834:834:834) (837:837:837)) + (PORT datac (1528:1528:1528) (1508:1508:1508)) + (PORT datad (166:166:166) (188:188:188)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~58) + (INSTANCE D\[0\]\~65) (DELAY (ABSOLUTE - (PORT dataa (1840:1840:1840) (1833:1833:1833)) - (PORT datab (606:606:606) (628:628:628)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (1526:1526:1526) (1471:1471:1471)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (1100:1100:1100) (1144:1144:1144)) + (PORT datab (2747:2747:2747) (2740:2740:2740)) + (PORT datac (175:175:175) (206:206:206)) + (PORT datad (1336:1336:1336) (1346:1346:1346)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -40650,10 +42945,10 @@ (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) (DELAY (ABSOLUTE - (PORT dataa (906:906:906) (945:945:945)) - (PORT datab (855:855:855) (862:862:862)) - (PORT datac (216:216:216) (266:266:266)) - (PORT datad (1460:1460:1460) (1444:1444:1444)) + (PORT dataa (1096:1096:1096) (1081:1081:1081)) + (PORT datab (380:380:380) (408:408:408)) + (PORT datac (347:347:347) (354:354:354)) + (PORT datad (1045:1045:1045) (1025:1025:1025)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -40682,11 +42977,11 @@ (INSTANCE z80_\|bus_control_\|db\[0\]\~16) (DELAY (ABSOLUTE - (PORT datab (359:359:359) (378:378:378)) - (PORT datac (376:376:376) (415:415:415)) - (PORT datad (621:621:621) (623:623:623)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datab (227:227:227) (270:270:270)) + (PORT datac (195:195:195) (239:239:239)) + (PORT datad (1970:1970:1970) (1970:1970:1970)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -40696,11 +42991,11 @@ (INSTANCE z80_\|bus_control_\|db\[0\]\~17) (DELAY (ABSOLUTE - (PORT dataa (904:904:904) (903:903:903)) - (PORT datab (1282:1282:1282) (1230:1230:1230)) - (PORT datac (822:822:822) (840:840:840)) - (PORT datad (825:825:825) (819:819:819)) - (IOPATH dataa combout (329:329:329) (332:332:332)) + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (1330:1330:1330) (1317:1317:1317)) + (PORT datac (1016:1016:1016) (1003:1003:1003)) + (PORT datad (198:198:198) (229:229:229)) + (IOPATH dataa combout (272:272:272) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -40712,10 +43007,10 @@ (INSTANCE z80_\|ir_\|opcode\[0\]) (DELAY (ABSOLUTE - (PORT clk (1341:1341:1341) (1358:1358:1358)) - (PORT asdata (1401:1401:1401) (1394:1394:1394)) - (PORT clrn (1395:1395:1395) (1365:1365:1365)) - (PORT ena (1378:1378:1378) (1338:1338:1338)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (657:657:657) (660:660:660)) + (PORT clrn (1396:1396:1396) (1368:1368:1368)) + (PORT ena (1787:1787:1787) (1726:1726:1726)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -40727,13 +43022,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal63\~0) + (INSTANCE z80_\|pla_decode_\|Equal3\~2) (DELAY (ABSOLUTE - (PORT dataa (1846:1846:1846) (1909:1909:1909)) - (PORT datab (1410:1410:1410) (1459:1459:1459)) - (PORT datac (201:201:201) (246:246:246)) - (PORT datad (1020:1020:1020) (1031:1031:1031)) + (PORT dataa (1554:1554:1554) (1577:1577:1577)) + (PORT datab (1260:1260:1260) (1252:1252:1252)) + (PORT datac (188:188:188) (230:230:230)) + (PORT datad (1237:1237:1237) (1193:1193:1193)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -40743,15 +43038,123 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) + (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) (DELAY (ABSOLUTE - (PORT dataa (1375:1375:1375) (1453:1453:1453)) - (PORT datab (1351:1351:1351) (1420:1420:1420)) - (PORT datac (1699:1699:1699) (1699:1699:1699)) - (PORT datad (370:370:370) (391:391:391)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) + (PORT dataa (2123:2123:2123) (2184:2184:2184)) + (PORT datab (2019:2019:2019) (2100:2100:2100)) + (PORT datac (2080:2080:2080) (2111:2111:2111)) + (PORT datad (341:341:341) (352:352:352)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instIY1) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1384:1384:1384) (1355:1355:1355)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|use_ixiy) + (DELAY + (ABSOLUTE + (PORT datac (905:905:905) (953:953:953)) + (PORT datad (1382:1382:1382) (1428:1428:1428)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~12) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (850:850:850)) + (PORT datab (1575:1575:1575) (1550:1550:1550)) + (PORT datac (984:984:984) (1002:1002:1002)) + (PORT datad (754:754:754) (779:779:779)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~13) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (603:603:603)) + (PORT datab (1143:1143:1143) (1141:1141:1141)) + (PORT datad (813:813:813) (823:823:823)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1008:1008:1008) (1035:1035:1035)) + (PORT datab (569:569:569) (578:578:578)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (550:550:550) (558:558:558)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (645:645:645)) + (PORT datab (653:653:653) (684:684:684)) + (PORT datac (1305:1305:1305) (1351:1351:1351)) + (PORT datad (561:561:561) (585:585:585)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1115:1115:1115) (1100:1100:1100)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (558:558:558) (580:580:580)) + (PORT datad (713:713:713) (739:739:739)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -40759,15 +43162,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) (DELAY (ABSOLUTE - (PORT dataa (327:327:327) (455:455:455)) - (PORT datab (660:660:660) (673:673:673)) - (PORT datac (1335:1335:1335) (1367:1367:1367)) - (PORT datad (1200:1200:1200) (1268:1268:1268)) + (PORT dataa (1138:1138:1138) (1181:1181:1181)) + (PORT datab (364:364:364) (382:382:382)) + (PORT datac (867:867:867) (922:922:922)) + (PORT datad (1246:1246:1246) (1315:1315:1315)) (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -40775,90 +43178,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~10) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) (DELAY (ABSOLUTE - (PORT dataa (622:622:622) (645:645:645)) - (PORT datac (1068:1068:1068) (1072:1072:1072)) - (PORT datad (842:842:842) (842:842:842)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (601:601:601) (632:632:632)) - (PORT datac (807:807:807) (818:818:818)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (502:502:502) (496:496:496)) - (PORT datab (836:836:836) (845:845:845)) - (PORT datac (545:545:545) (540:540:540)) - (PORT datad (1067:1067:1067) (1073:1073:1073)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (605:605:605)) - (PORT datab (879:879:879) (876:876:876)) - (PORT datac (585:585:585) (610:610:610)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (839:839:839) (838:838:838)) - (PORT datab (218:218:218) (262:262:262)) - (PORT datac (568:568:568) (598:598:598)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~119) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (761:761:761)) - (PORT datab (666:666:666) (734:734:734)) - (PORT datac (1056:1056:1056) (1114:1114:1114)) - (PORT datad (840:840:840) (880:880:880)) - (IOPATH dataa combout (307:307:307) (280:280:280)) + (PORT dataa (1117:1117:1117) (1144:1144:1144)) + (PORT datab (1429:1429:1429) (1449:1449:1449)) + (PORT datac (536:536:536) (528:528:528)) + (PORT datad (799:799:799) (789:789:789)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -40867,15 +43194,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~120) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) (DELAY (ABSOLUTE - (PORT dataa (622:622:622) (643:643:643)) - (PORT datab (321:321:321) (330:330:330)) - (PORT datac (658:658:658) (727:727:727)) - (PORT datad (670:670:670) (741:741:741)) + (PORT dataa (1279:1279:1279) (1287:1287:1287)) + (PORT datab (1962:1962:1962) (2055:2055:2055)) + (PORT datac (1514:1514:1514) (1482:1482:1482)) + (PORT datad (643:643:643) (681:681:681)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (722:722:722)) + (PORT datab (610:610:610) (596:596:596)) + (PORT datac (1481:1481:1481) (1467:1467:1467)) + (PORT datad (1363:1363:1363) (1392:1392:1392)) (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -40883,13 +43226,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~95) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) (DELAY (ABSOLUTE - (PORT dataa (729:729:729) (811:811:811)) - (PORT datac (645:645:645) (709:709:709)) - (PORT datad (1063:1063:1063) (1109:1109:1109)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT dataa (1078:1078:1078) (1085:1085:1085)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (195:195:195) (237:237:237)) + (PORT datab (578:578:578) (600:600:600)) + (PORT datac (161:161:161) (196:196:196)) + (PORT datad (323:323:323) (330:330:330)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -40897,86 +43258,160 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~121) + (INSTANCE z80_\|alu_\|db\[7\]\~9) (DELAY (ABSOLUTE - (PORT dataa (184:184:184) (219:219:219)) - (PORT datad (165:165:165) (189:189:189)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~117) - (DELAY - (ABSOLUTE - (PORT dataa (406:406:406) (472:472:472)) - (PORT datab (606:606:606) (652:652:652)) - (PORT datad (670:670:670) (705:705:705)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT datab (814:814:814) (822:822:822)) + (PORT datac (526:526:526) (524:524:524)) + (PORT datad (756:756:756) (735:735:735)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~136) + (INSTANCE z80_\|alu_\|db\[1\]\~15) (DELAY (ABSOLUTE - (PORT dataa (531:531:531) (520:520:520)) - (PORT datab (419:419:419) (464:464:464)) - (PORT datad (605:605:605) (640:640:640)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (554:554:554) (558:558:558)) + (PORT datab (555:555:555) (552:552:552)) + (PORT datac (827:827:827) (837:837:837)) + (PORT datad (757:757:757) (741:741:741)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~130) + (INSTANCE z80_\|alu_\|db\[1\]\~16) (DELAY (ABSOLUTE - (PORT dataa (624:624:624) (665:665:665)) - (PORT datab (618:618:618) (627:627:627)) - (PORT datad (770:770:770) (787:787:787)) - (IOPATH dataa combout (272:272:272) (269:269:269)) + (PORT dataa (222:222:222) (268:268:268)) + (PORT datab (814:814:814) (827:827:827)) + (PORT datac (603:603:603) (617:617:617)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~118) + (INSTANCE z80_\|alu_control_\|db\[1\]\~25) (DELAY (ABSOLUTE - (PORT dataa (731:731:731) (812:812:812)) - (PORT datab (589:589:589) (595:595:595)) - (PORT datad (570:570:570) (566:566:566)) + (PORT dataa (995:995:995) (1021:1021:1021)) + (PORT datab (1081:1081:1081) (1076:1076:1076)) + (PORT datac (1212:1212:1212) (1181:1181:1181)) + (PORT datad (1251:1251:1251) (1263:1263:1263)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (603:603:603)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datac (788:788:788) (794:794:794)) + (PORT datad (163:163:163) (188:188:188)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (580:580:580)) + (PORT datac (585:585:585) (600:600:600)) + (PORT datad (778:778:778) (775:775:775)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (809:809:809) (814:814:814)) + (PORT datad (162:162:162) (184:184:184)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (830:830:830) (813:813:813)) + (PORT datab (1076:1076:1076) (1063:1063:1063)) + (PORT datad (357:357:357) (367:367:367)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (450:450:450) (510:510:510)) + (PORT datac (689:689:689) (740:740:740)) + (PORT datad (352:352:352) (401:401:401)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (678:678:678)) + (PORT datac (901:901:901) (942:942:942)) + (PORT datad (574:574:574) (611:611:611)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (223:223:223)) + (PORT datab (184:184:184) (216:216:216)) + (PORT datad (542:542:542) (530:530:530)) (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -40986,12 +43421,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1371:1371:1371)) + (PORT clk (1331:1331:1331) (1348:1348:1348)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) + (PORT clrn (1365:1365:1365) (1346:1346:1346)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -41002,15 +43437,44 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~78) + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~30) (DELAY (ABSOLUTE - (PORT dataa (836:836:836) (811:811:811)) - (PORT datab (817:817:817) (808:808:808)) - (PORT datac (568:568:568) (598:598:598)) - (PORT datad (599:599:599) (627:627:627)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (PORT dataa (191:191:191) (231:231:231)) + (PORT datab (721:721:721) (755:755:755)) + (PORT datad (179:179:179) (200:200:200)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1327:1327:1327) (1346:1346:1346)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1370:1370:1370) (1350:1350:1350)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~0) + (DELAY + (ABSOLUTE + (PORT datab (1681:1681:1681) (1713:1713:1713)) + (PORT datac (2090:2090:2090) (2214:2214:2214)) + (PORT datad (840:840:840) (849:849:849)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -41018,13 +43482,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~126) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~36) (DELAY (ABSOLUTE - (PORT dataa (752:752:752) (832:832:832)) - (PORT datab (636:636:636) (659:659:659)) - (PORT datac (882:882:882) (920:920:920)) - (PORT datad (1276:1276:1276) (1339:1339:1339)) + (PORT dataa (278:278:278) (382:382:382)) + (PORT datab (640:640:640) (665:665:665)) + (PORT datac (835:835:835) (860:860:860)) + (PORT datad (876:876:876) (916:916:916)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (703:703:703)) + (PORT datab (720:720:720) (791:791:791)) + (PORT datac (935:935:935) (990:990:990)) + (PORT datad (682:682:682) (747:747:747)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -41034,15 +43514,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~128) + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~0) (DELAY (ABSOLUTE - (PORT dataa (893:893:893) (925:925:925)) - (PORT datab (723:723:723) (794:794:794)) - (PORT datac (826:826:826) (874:874:874)) - (PORT datad (707:707:707) (785:785:785)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT dataa (660:660:660) (708:708:708)) + (PORT datab (719:719:719) (788:788:788)) + (PORT datac (933:933:933) (989:989:989)) + (PORT datad (679:679:679) (744:744:744)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -41050,14 +43530,46 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~129) + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) (DELAY (ABSOLUTE - (PORT dataa (328:328:328) (342:342:342)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datad (839:839:839) (871:871:871)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (210:210:210) (250:250:250)) + (PORT datab (962:962:962) (1020:1020:1020)) + (PORT datac (1150:1150:1150) (1194:1194:1194)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (721:721:721)) + (PORT datab (1182:1182:1182) (1224:1224:1224)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (725:725:725)) + (PORT datab (559:559:559) (546:546:546)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -41065,12 +43577,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1371:1371:1371)) + (PORT clk (1328:1328:1328) (1347:1347:1347)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) + (PORT clrn (1371:1371:1371) (1351:1351:1351)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -41081,12 +43593,1974 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~127) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~33) (DELAY (ABSOLUTE - (PORT dataa (560:560:560) (564:564:564)) - (PORT datab (885:885:885) (931:931:931)) - (PORT datad (530:530:530) (517:517:517)) + (PORT dataa (686:686:686) (748:748:748)) + (PORT datab (673:673:673) (713:713:713)) + (PORT datac (666:666:666) (727:727:727)) + (PORT datad (928:928:928) (965:965:965)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (920:920:920) (956:956:956)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (488:488:488) (482:482:482)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (968:968:968) (1001:1001:1001)) + (PORT datac (419:419:419) (477:477:477)) + (PORT datad (852:852:852) (871:871:871)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (222:222:222)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1326:1326:1326) (1345:1345:1345)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1369:1369:1369) (1349:1349:1349)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (898:898:898)) + (PORT datab (872:872:872) (872:872:872)) + (PORT datac (600:600:600) (621:621:621)) + (PORT datad (1324:1324:1324) (1300:1300:1300)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (254:254:254)) + (PORT datab (849:849:849) (876:876:876)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (454:454:454) (521:521:521)) + (PORT datab (865:865:865) (902:902:902)) + (PORT datac (681:681:681) (747:747:747)) + (PORT datad (651:651:651) (691:691:691)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (234:234:234)) + (PORT datab (607:607:607) (601:601:601)) + (PORT datac (868:868:868) (912:912:912)) + (PORT datad (821:821:821) (829:829:829)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (222:222:222)) + (PORT datab (464:464:464) (504:504:504)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1325:1325:1325) (1344:1344:1344)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1367:1367:1367) (1347:1347:1347)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (456:456:456) (522:522:522)) + (PORT datab (897:897:897) (940:940:940)) + (PORT datac (681:681:681) (747:747:747)) + (PORT datad (654:654:654) (693:693:693)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (672:672:672) (727:727:727)) + (PORT datab (1197:1197:1197) (1219:1219:1219)) + (PORT datac (677:677:677) (725:725:725)) + (PORT datad (291:291:291) (297:297:297)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (692:692:692) (753:753:753)) + (PORT datac (421:421:421) (482:482:482)) + (PORT datad (848:848:848) (865:865:865)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (601:601:601)) + (PORT datab (312:312:312) (331:331:331)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1326:1326:1326) (1345:1345:1345)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1369:1369:1369) (1349:1349:1349)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (637:637:637)) + (PORT datab (619:619:619) (647:647:647)) + (PORT datac (616:616:616) (639:639:639)) + (PORT datad (1380:1380:1380) (1421:1421:1421)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (1197:1197:1197) (1228:1228:1228)) + (PORT datac (636:636:636) (689:689:689)) + (PORT datad (665:665:665) (708:708:708)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1204:1204:1204) (1267:1267:1267)) + (PORT datab (610:610:610) (627:627:627)) + (PORT datad (557:557:557) (542:542:542)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1373:1373:1373) (1354:1354:1354)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1203:1203:1203) (1272:1272:1272)) + (PORT datab (932:932:932) (990:990:990)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1330:1330:1330) (1349:1349:1349)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1373:1373:1373) (1354:1354:1354)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (250:250:250)) + (PORT datab (2589:2589:2589) (2687:2687:2687)) + (PORT datac (196:196:196) (262:262:262)) + (PORT datad (198:198:198) (254:254:254)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (218:218:218)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (2186:2186:2186) (2315:2315:2315)) + (PORT datad (533:533:533) (519:519:519)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1190:1190:1190) (1201:1201:1201)) + (PORT clk (1630:1630:1630) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2246:2246:2246) (2370:2370:2370)) + (PORT d[1] (2362:2362:2362) (2392:2392:2392)) + (PORT d[2] (1175:1175:1175) (1191:1191:1191)) + (PORT d[3] (1164:1164:1164) (1169:1169:1169)) + (PORT d[4] (1890:1890:1890) (1900:1900:1900)) + (PORT d[5] (1173:1173:1173) (1185:1185:1185)) + (PORT d[6] (1345:1345:1345) (1332:1332:1332)) + (PORT d[7] (2466:2466:2466) (2527:2527:2527)) + (PORT d[8] (2297:2297:2297) (2400:2400:2400)) + (PORT d[9] (715:715:715) (756:756:756)) + (PORT d[10] (676:676:676) (712:712:712)) + (PORT d[11] (1124:1124:1124) (1127:1127:1127)) + (PORT d[12] (668:668:668) (699:699:699)) + (PORT clk (1627:1627:1627) (1656:1656:1656)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1146:1146:1146) (1108:1108:1108)) + (PORT clk (1627:1627:1627) (1656:1656:1656)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1630:1630:1630) (1658:1658:1658)) + (PORT d[0] (1549:1549:1549) (1495:1495:1495)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1594:1594:1594) (1622:1622:1622)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (865:865:865) (869:869:869)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (934:934:934) (939:939:939)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2538:2538:2538) (2677:2677:2677)) + (PORT d[1] (1796:1796:1796) (1824:1824:1824)) + (PORT d[2] (926:926:926) (928:928:928)) + (PORT d[3] (899:899:899) (899:899:899)) + (PORT d[4] (1332:1332:1332) (1321:1321:1321)) + (PORT d[5] (887:887:887) (885:885:885)) + (PORT d[6] (1074:1074:1074) (1052:1052:1052)) + (PORT d[7] (2727:2727:2727) (2782:2782:2782)) + (PORT d[8] (1469:1469:1469) (1502:1502:1502)) + (PORT d[9] (678:678:678) (702:702:702)) + (PORT d[10] (660:660:660) (681:681:681)) + (PORT d[11] (2311:2311:2311) (2398:2398:2398)) + (PORT d[12] (702:702:702) (737:737:737)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (867:867:867) (836:836:836)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1662:1662:1662)) + (PORT d[0] (2978:2978:2978) (2980:2980:2980)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1626:1626:1626)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1100:1100:1100) (1053:1053:1053)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2363:2363:2363) (2450:2450:2450)) + (PORT d[1] (3342:3342:3342) (3418:3418:3418)) + (PORT d[2] (2193:2193:2193) (2211:2211:2211)) + (PORT d[3] (3959:3959:3959) (4026:4026:4026)) + (PORT d[4] (2941:2941:2941) (3050:3050:3050)) + (PORT d[5] (4357:4357:4357) (4429:4429:4429)) + (PORT d[6] (2344:2344:2344) (2357:2357:2357)) + (PORT d[7] (1294:1294:1294) (1285:1285:1285)) + (PORT d[8] (2887:2887:2887) (2959:2959:2959)) + (PORT d[9] (1662:1662:1662) (1669:1669:1669)) + (PORT d[10] (1838:1838:1838) (1814:1814:1814)) + (PORT d[11] (3155:3155:3155) (3274:3274:3274)) + (PORT d[12] (4329:4329:4329) (4444:4444:4444)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1736:1736:1736) (1726:1726:1726)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (PORT d[0] (2227:2227:2227) (2165:2165:2165)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1638:1638:1638)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (960:960:960)) + (PORT datab (1142:1142:1142) (1171:1171:1171)) + (PORT datac (843:843:843) (845:845:845)) + (PORT datad (1010:1010:1010) (978:978:978)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1275:1275:1275) (1267:1267:1267)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2290:2290:2290) (2354:2354:2354)) + (PORT d[1] (2298:2298:2298) (2277:2277:2277)) + (PORT d[2] (2382:2382:2382) (2475:2475:2475)) + (PORT d[3] (1574:1574:1574) (1563:1563:1563)) + (PORT d[4] (2243:2243:2243) (2301:2301:2301)) + (PORT d[5] (2941:2941:2941) (2949:2949:2949)) + (PORT d[6] (2049:2049:2049) (2065:2065:2065)) + (PORT d[7] (1590:1590:1590) (1591:1591:1591)) + (PORT d[8] (2270:2270:2270) (2315:2315:2315)) + (PORT d[9] (1574:1574:1574) (1556:1556:1556)) + (PORT d[10] (2338:2338:2338) (2339:2339:2339)) + (PORT d[11] (3735:3735:3735) (3877:3877:3877)) + (PORT d[12] (2289:2289:2289) (2292:2292:2292)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1836:1836:1836) (1777:1777:1777)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (PORT d[0] (1998:1998:1998) (1941:1941:1941)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1396:1396:1396) (1460:1460:1460)) + (PORT datab (1111:1111:1111) (1122:1122:1122)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (1296:1296:1296) (1273:1273:1273)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1383:1383:1383) (1372:1372:1372)) + (PORT clk (1652:1652:1652) (1679:1679:1679)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2317:2317:2317) (2350:2350:2350)) + (PORT d[1] (2108:2108:2108) (2115:2115:2115)) + (PORT d[2] (1911:1911:1911) (1960:1960:1960)) + (PORT d[3] (3067:3067:3067) (3079:3079:3079)) + (PORT d[4] (2142:2142:2142) (2219:2219:2219)) + (PORT d[5] (3480:3480:3480) (3506:3506:3506)) + (PORT d[6] (2330:2330:2330) (2339:2339:2339)) + (PORT d[7] (2310:2310:2310) (2319:2319:2319)) + (PORT d[8] (2724:2724:2724) (2759:2759:2759)) + (PORT d[9] (2535:2535:2535) (2595:2595:2595)) + (PORT d[10] (2698:2698:2698) (2717:2717:2717)) + (PORT d[11] (2555:2555:2555) (2620:2620:2620)) + (PORT d[12] (3239:3239:3239) (3318:3318:3318)) + (PORT clk (1649:1649:1649) (1677:1677:1677)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2602:2602:2602) (2565:2565:2565)) + (PORT clk (1649:1649:1649) (1677:1677:1677)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1679:1679:1679)) + (PORT d[0] (3196:3196:3196) (3184:3184:3184)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1609:1609:1609)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2020:2020:2020) (1987:1987:1987)) + (PORT clk (1619:1619:1619) (1616:1616:1616)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4191:4191:4191) (4059:4059:4059)) + (PORT d[1] (4108:4108:4108) (4082:4082:4082)) + (PORT d[2] (4214:4214:4214) (4086:4086:4086)) + (PORT d[3] (4077:4077:4077) (4001:4001:4001)) + (PORT d[4] (3956:3956:3956) (3928:3928:3928)) + (PORT d[5] (4097:4097:4097) (4012:4012:4012)) + (PORT d[6] (3962:3962:3962) (3881:3881:3881)) + (PORT d[7] (4119:4119:4119) (4038:4038:4038)) + (PORT d[8] (4217:4217:4217) (4160:4160:4160)) + (PORT d[9] (4068:4068:4068) (3996:3996:3996)) + (PORT d[10] (3941:3941:3941) (3829:3829:3829)) + (PORT d[11] (4112:4112:4112) (4036:4036:4036)) + (PORT d[12] (3982:3982:3982) (3857:3857:3857)) + (PORT clk (1616:1616:1616) (1613:1613:1613)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1619:1619:1619) (1616:1616:1616)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1620:1620:1620) (1617:1617:1617)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1620:1620:1620) (1617:1617:1617)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1620:1620:1620) (1617:1617:1617)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1620:1620:1620) (1617:1617:1617)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1612:1612:1612) (1610:1610:1610)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1776:1776:1776) (1834:1834:1834)) + (PORT d[1] (1547:1547:1547) (1554:1554:1554)) + (PORT d[2] (1830:1830:1830) (1909:1909:1909)) + (PORT d[3] (1769:1769:1769) (1768:1768:1768)) + (PORT d[4] (2482:2482:2482) (2511:2511:2511)) + (PORT d[5] (2126:2126:2126) (2129:2129:2129)) + (PORT d[6] (1597:1597:1597) (1613:1613:1613)) + (PORT d[7] (1861:1861:1861) (1868:1868:1868)) + (PORT d[8] (1714:1714:1714) (1753:1753:1753)) + (PORT d[9] (1875:1875:1875) (1867:1867:1867)) + (PORT d[10] (1560:1560:1560) (1557:1557:1557)) + (PORT d[11] (4007:4007:4007) (4155:4155:4155)) + (PORT d[12] (1529:1529:1529) (1530:1530:1530)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1671:1671:1671)) + (PORT d[0] (1629:1629:1629) (1698:1698:1698)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1637:1637:1637)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (885:885:885)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (885:885:885)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2314:2314:2314) (2367:2367:2367)) + (PORT d[1] (2467:2467:2467) (2495:2495:2495)) + (PORT d[2] (2053:2053:2053) (2130:2130:2130)) + (PORT d[3] (1957:1957:1957) (2014:2014:2014)) + (PORT d[4] (1933:1933:1933) (1952:1952:1952)) + (PORT d[5] (2251:2251:2251) (2287:2287:2287)) + (PORT d[6] (2256:2256:2256) (2336:2336:2336)) + (PORT d[7] (3179:3179:3179) (3205:3205:3205)) + (PORT d[8] (2636:2636:2636) (2663:2663:2663)) + (PORT d[9] (2141:2141:2141) (2240:2240:2240)) + (PORT d[10] (3053:3053:3053) (3089:3089:3089)) + (PORT d[11] (1988:1988:1988) (2023:2023:2023)) + (PORT d[12] (2094:2094:2094) (2192:2192:2192)) + (PORT clk (1645:1645:1645) (1673:1673:1673)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1673:1673:1673)) + (PORT d[0] (2383:2383:2383) (2403:2403:2403)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1612:1612:1612) (1639:1639:1639)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (887:887:887)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (887:887:887)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (887:887:887)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1496:1496:1496) (1548:1548:1548)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2591:2591:2591) (2643:2643:2643)) + (PORT d[1] (2732:2732:2732) (2767:2767:2767)) + (PORT d[2] (1830:1830:1830) (1887:1887:1887)) + (PORT d[3] (1729:1729:1729) (1779:1779:1779)) + (PORT d[4] (1952:1952:1952) (1999:1999:1999)) + (PORT d[5] (2434:2434:2434) (2448:2448:2448)) + (PORT d[6] (1983:1983:1983) (2059:2059:2059)) + (PORT d[7] (3172:3172:3172) (3208:3208:3208)) + (PORT d[8] (2926:2926:2926) (2945:2945:2945)) + (PORT d[9] (2106:2106:2106) (2193:2193:2193)) + (PORT d[10] (1766:1766:1766) (1836:1836:1836)) + (PORT d[11] (1962:1962:1962) (2017:2017:2017)) + (PORT d[12] (2226:2226:2226) (2293:2293:2293)) + (PORT clk (1640:1640:1640) (1669:1669:1669)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1867:1867:1867) (1818:1818:1818)) + (PORT clk (1640:1640:1640) (1669:1669:1669)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1671:1671:1671)) + (PORT d[0] (2918:2918:2918) (2929:2929:2929)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1601:1601:1601)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1958:1958:1958) (1963:1963:1963)) + (PORT clk (1610:1610:1610) (1608:1608:1608)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4144:4144:4144) (4118:4118:4118)) + (PORT d[1] (4074:4074:4074) (4107:4107:4107)) + (PORT d[2] (4099:4099:4099) (4045:4045:4045)) + (PORT d[3] (3971:3971:3971) (3955:3955:3955)) + (PORT d[4] (4076:4076:4076) (4027:4027:4027)) + (PORT d[5] (4136:4136:4136) (4126:4126:4126)) + (PORT d[6] (4038:4038:4038) (4000:4000:4000)) + (PORT d[7] (4060:4060:4060) (3930:3930:3930)) + (PORT d[8] (4294:4294:4294) (4231:4231:4231)) + (PORT d[9] (4162:4162:4162) (4042:4042:4042)) + (PORT d[10] (4066:4066:4066) (4007:4007:4007)) + (PORT d[11] (4075:4075:4075) (3998:3998:3998)) + (PORT d[12] (4087:4087:4087) (3903:3903:3903)) + (PORT clk (1607:1607:1607) (1605:1605:1605)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1608:1608:1608)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1609:1609:1609)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1609:1609:1609)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1609:1609:1609)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1609:1609:1609)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (859:859:859)) + (PORT datab (712:712:712) (774:774:774)) + (PORT datac (1347:1347:1347) (1362:1362:1362)) + (PORT datad (1070:1070:1070) (1069:1069:1069)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1002:1002:1002) (969:969:969)) + (PORT datab (949:949:949) (986:986:986)) + (PORT datac (1512:1512:1512) (1509:1509:1509)) + (PORT datad (166:166:166) (189:189:189)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (689:689:689) (759:759:759)) + (PORT datab (1619:1619:1619) (1655:1655:1655)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (167:167:167) (191:191:191)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~118) + (DELAY + (ABSOLUTE + (PORT dataa (1595:1595:1595) (1607:1607:1607)) + (PORT datab (2775:2775:2775) (2913:2913:2913)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (881:881:881)) + (PORT datab (837:837:837) (839:839:839)) + (PORT datac (1524:1524:1524) (1504:1504:1504)) + (PORT datad (179:179:179) (201:201:201)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1085:1085:1085) (1104:1104:1104)) + (PORT datab (1360:1360:1360) (1379:1379:1379)) + (PORT datac (2969:2969:2969) (2920:2920:2920)) + (PORT datad (178:178:178) (199:199:199)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (889:889:889)) + (PORT datab (380:380:380) (408:408:408)) + (PORT datac (176:176:176) (207:207:207)) + (PORT datad (1045:1045:1045) (1025:1025:1025)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (763:763:763) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (242:242:242) (312:312:312)) + (PORT datac (551:551:551) (542:542:542)) + (PORT datad (355:355:355) (361:361:361)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1396:1396:1396) (1368:1368:1368)) + (PORT ena (1787:1787:1787) (1726:1726:1726)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) + (DELAY + (ABSOLUTE + (PORT dataa (1475:1475:1475) (1562:1562:1562)) + (PORT datab (1787:1787:1787) (1841:1841:1841)) + (PORT datac (340:340:340) (363:363:363)) + (PORT datad (1072:1072:1072) (1077:1077:1077)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instED) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1384:1384:1384) (1355:1355:1355)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (698:698:698) (747:747:747)) + (PORT datab (692:692:692) (739:739:739)) + (PORT datac (1693:1693:1693) (1776:1776:1776)) + (PORT datad (1561:1561:1561) (1560:1560:1560)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1943:1943:1943) (2009:2009:2009)) + (PORT datab (1295:1295:1295) (1366:1366:1366)) + (PORT datac (1029:1029:1029) (1029:1029:1029)) + (PORT datad (816:816:816) (826:826:826)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1494:1494:1494) (1498:1498:1498)) + (PORT datab (605:605:605) (586:586:586)) + (PORT datac (951:951:951) (986:986:986)) + (PORT datad (2416:2416:2416) (2386:2386:2386)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (1660:1660:1660) (1708:1708:1708)) + (PORT datab (987:987:987) (1031:1031:1031)) + (PORT datac (779:779:779) (768:768:768)) + (PORT datad (2401:2401:2401) (2358:2358:2358)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (811:811:811) (835:835:835)) + (PORT datab (978:978:978) (1016:1016:1016)) + (PORT datac (1688:1688:1688) (1722:1722:1722)) + (PORT datad (578:578:578) (597:597:597)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1492:1492:1492) (1497:1497:1497)) + (PORT datab (2099:2099:2099) (2180:2180:2180)) + (PORT datac (574:574:574) (606:606:606)) + (PORT datad (912:912:912) (967:967:967)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (689:689:689)) + (PORT datab (866:866:866) (891:891:891)) + (PORT datac (1373:1373:1373) (1352:1352:1352)) + (PORT datad (595:595:595) (617:617:617)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (576:576:576)) + (PORT datab (1080:1080:1080) (1036:1036:1036)) + (PORT datac (516:516:516) (506:506:506)) + (PORT datad (587:587:587) (587:587:587)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (217:217:217)) + (PORT datab (181:181:181) (212:212:212)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~126) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (232:232:232)) + (PORT datab (466:466:466) (510:510:510)) + (PORT datad (584:584:584) (576:576:576)) (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -41099,9 +45573,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT clk (1325:1325:1325) (1344:1344:1344)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) + (PORT clrn (1367:1367:1367) (1347:1347:1347)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -41110,44 +45584,14 @@ (HOLD d (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1470:1470:1470) (1502:1502:1502)) - (PORT datac (684:684:684) (754:754:754)) - (PORT datad (654:654:654) (709:709:709)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (649:649:649)) - (PORT datab (1142:1142:1142) (1157:1157:1157)) - (PORT datac (845:845:845) (875:875:875)) - (PORT datad (305:305:305) (312:312:312)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~125) (DELAY (ABSOLUTE - (PORT dataa (193:193:193) (235:235:235)) - (PORT datab (886:886:886) (933:933:933)) - (PORT datad (329:329:329) (342:342:342)) + (PORT dataa (301:301:301) (399:399:399)) + (PORT datab (360:360:360) (364:364:364)) + (PORT datad (173:173:173) (200:200:200)) (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -41160,9 +45604,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT clk (1326:1326:1326) (1345:1345:1345)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) + (PORT clrn (1368:1368:1368) (1348:1348:1348)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -41173,30 +45617,77 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~79) + (INSTANCE D\[4\]\~88) (DELAY (ABSOLUTE - (PORT dataa (1249:1249:1249) (1240:1240:1240)) - (PORT datab (1134:1134:1134) (1154:1154:1154)) - (PORT datac (196:196:196) (263:263:263)) - (PORT datad (198:198:198) (256:256:256)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (387:387:387) (426:426:426)) + (PORT datab (886:886:886) (893:893:893)) + (PORT datac (791:791:791) (783:783:783)) + (PORT datad (197:197:197) (254:254:254)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~120) + (DELAY + (ABSOLUTE + (PORT dataa (457:457:457) (524:524:524)) + (PORT datab (867:867:867) (899:899:899)) + (PORT datac (682:682:682) (745:745:745)) + (PORT datad (656:656:656) (695:695:695)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~121) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (624:624:624)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datad (417:417:417) (465:465:465)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1325:1325:1325) (1344:1344:1344)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1367:1367:1367) (1347:1347:1347)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~122) (DELAY (ABSOLUTE - (PORT dataa (409:409:409) (474:474:474)) - (PORT datab (603:603:603) (651:651:651)) - (PORT datad (672:672:672) (706:706:706)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT datab (717:717:717) (766:766:766)) + (PORT datac (1168:1168:1168) (1191:1191:1191)) + (PORT datad (219:219:219) (277:277:277)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -41206,10 +45697,10 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~123) (DELAY (ABSOLUTE - (PORT dataa (546:546:546) (536:536:536)) - (PORT datab (668:668:668) (733:733:733)) - (PORT datac (1424:1424:1424) (1480:1480:1480)) - (PORT datad (544:544:544) (543:543:543)) + (PORT dataa (669:669:669) (721:721:721)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (675:675:675) (724:724:724)) + (PORT datad (572:572:572) (568:568:568)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -41222,9 +45713,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~124) (DELAY (ABSOLUTE - (PORT dataa (606:606:606) (631:631:631)) - (PORT datab (688:688:688) (759:759:759)) - (PORT datad (160:160:160) (180:180:180)) + (PORT dataa (462:462:462) (516:516:516)) + (PORT datab (1265:1265:1265) (1234:1234:1234)) + (PORT datad (299:299:299) (292:292:292)) (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -41237,9 +45728,86 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT clk (1326:1326:1326) (1345:1345:1345)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) + (PORT clrn (1369:1369:1369) (1349:1349:1349)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (1168:1168:1168) (1210:1210:1210)) + (PORT datab (849:849:849) (843:843:843)) + (PORT datac (559:559:559) (583:583:583)) + (PORT datad (600:600:600) (622:622:622)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~115) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (675:675:675)) + (PORT datab (672:672:672) (703:703:703)) + (PORT datac (1141:1141:1141) (1155:1155:1155)) + (PORT datad (1112:1112:1112) (1124:1124:1124)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~116) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (570:570:570)) + (PORT datab (703:703:703) (741:741:741)) + (PORT datac (636:636:636) (687:687:687)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~117) + (DELAY + (ABSOLUTE + (PORT datab (189:189:189) (225:225:225)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1334:1334:1334) (1351:1351:1351)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1367:1367:1367) (1349:1349:1349)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -41253,10 +45821,26 @@ (INSTANCE ula_\|zx_keyboard_\|key_row\~3) (DELAY (ABSOLUTE - (PORT datab (1409:1409:1409) (1437:1437:1437)) - (PORT datac (813:813:813) (846:846:846)) - (PORT datad (199:199:199) (256:256:256)) - (IOPATH datab combout (295:295:295) (285:285:285)) + (PORT dataa (2138:2138:2138) (2278:2278:2278)) + (PORT datab (1326:1326:1326) (1386:1386:1386)) + (PORT datad (614:614:614) (654:654:654)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~118) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (357:357:357)) + (PORT datab (877:877:877) (920:920:920)) + (PORT datac (909:909:909) (950:950:950)) + (PORT datad (660:660:660) (701:701:701)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -41264,58 +45848,58 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~80) + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~131) (DELAY (ABSOLUTE - (PORT dataa (350:350:350) (405:405:405)) - (PORT datab (580:580:580) (576:576:576)) - (PORT datac (1257:1257:1257) (1255:1255:1255)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (287:287:287) (280:280:280)) + (PORT dataa (957:957:957) (1009:1009:1009)) + (PORT datab (183:183:183) (215:215:215)) + (PORT datad (235:235:235) (301:301:301)) + (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~111) + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~119) (DELAY (ABSOLUTE - (PORT dataa (730:730:730) (811:811:811)) - (PORT datac (639:639:639) (702:702:702)) - (PORT datad (1057:1057:1057) (1101:1101:1101)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (299:299:299) (398:398:398)) + (PORT datab (579:579:579) (589:589:589)) + (PORT datad (762:762:762) (742:742:742)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~97) + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) (DELAY (ABSOLUTE - (PORT dataa (1087:1087:1087) (1147:1147:1147)) - (PORT datab (670:670:670) (736:736:736)) - (PORT datac (586:586:586) (610:610:610)) - (PORT datad (836:836:836) (879:879:879)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT clk (1326:1326:1326) (1345:1345:1345)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1368:1368:1368) (1348:1348:1348)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~116) + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~114) (DELAY (ABSOLUTE - (PORT dataa (358:358:358) (369:369:369)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datad (166:166:166) (193:193:193)) + (PORT dataa (192:192:192) (235:235:235)) + (PORT datab (606:606:606) (599:599:599)) + (PORT datad (180:180:180) (202:202:202)) (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -41328,9 +45912,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1371:1371:1371)) + (PORT clk (1334:1334:1334) (1351:1351:1351)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) + (PORT clrn (1367:1367:1367) (1349:1349:1349)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -41341,14 +45925,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~115) + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~113) (DELAY (ABSOLUTE - (PORT dataa (545:545:545) (533:533:533)) - (PORT datab (332:332:332) (353:353:353)) - (PORT datad (661:661:661) (725:725:725)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (721:721:721) (778:778:778)) + (PORT datab (568:568:568) (578:578:578)) + (PORT datad (554:554:554) (553:553:553)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -41359,9 +45943,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT clk (1331:1331:1331) (1348:1348:1348)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) + (PORT clrn (1365:1365:1365) (1346:1346:1346)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -41372,658 +45956,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~77) + (INSTANCE D\[4\]\~85) (DELAY (ABSOLUTE - (PORT dataa (1042:1042:1042) (1038:1038:1038)) - (PORT datab (1066:1066:1066) (1079:1079:1079)) - (PORT datac (590:590:590) (626:626:626)) - (PORT datad (199:199:199) (256:256:256)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (1497:1497:1497) (1479:1479:1479)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3117:3117:3117) (3202:3202:3202)) - (PORT d[1] (1492:1492:1492) (1570:1570:1570)) - (PORT d[2] (2221:2221:2221) (2276:2276:2276)) - (PORT d[3] (1745:1745:1745) (1779:1779:1779)) - (PORT d[4] (1772:1772:1772) (1805:1805:1805)) - (PORT d[5] (1930:1930:1930) (2022:2022:2022)) - (PORT d[6] (2105:2105:2105) (2140:2140:2140)) - (PORT d[7] (2005:2005:2005) (2010:2010:2010)) - (PORT d[8] (2724:2724:2724) (2779:2779:2779)) - (PORT d[9] (2094:2094:2094) (2123:2123:2123)) - (PORT d[10] (3714:3714:3714) (3823:3823:3823)) - (PORT d[11] (1664:1664:1664) (1694:1694:1694)) - (PORT d[12] (2152:2152:2152) (2211:2211:2211)) - (PORT clk (1635:1635:1635) (1664:1664:1664)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1664:1664:1664)) - (PORT d[0] (2258:2258:2258) (2250:2250:2250)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1665:1665:1665)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1630:1630:1630)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1398:1398:1398) (1418:1418:1418)) - (PORT clk (1634:1634:1634) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3220:3220:3220) (3238:3238:3238)) - (PORT d[1] (1562:1562:1562) (1647:1647:1647)) - (PORT d[2] (1668:1668:1668) (1669:1669:1669)) - (PORT d[3] (1976:1976:1976) (2007:2007:2007)) - (PORT d[4] (2050:2050:2050) (2095:2095:2095)) - (PORT d[5] (1525:1525:1525) (1602:1602:1602)) - (PORT d[6] (1345:1345:1345) (1352:1352:1352)) - (PORT d[7] (1353:1353:1353) (1377:1377:1377)) - (PORT d[8] (2698:2698:2698) (2781:2781:2781)) - (PORT d[9] (2098:2098:2098) (2149:2149:2149)) - (PORT d[10] (2137:2137:2137) (2175:2175:2175)) - (PORT d[11] (1988:1988:1988) (2028:2028:2028)) - (PORT d[12] (1876:1876:1876) (1897:1897:1897)) - (PORT clk (1631:1631:1631) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2643:2643:2643) (2613:2613:2613)) - (PORT clk (1631:1631:1631) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1634:1634:1634) (1662:1662:1662)) - (PORT d[0] (3917:3917:3917) (3913:3913:3913)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1593:1593:1593) (1592:1592:1592)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1614:1614:1614) (1543:1543:1543)) - (PORT clk (1601:1601:1601) (1599:1599:1599)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4103:4103:4103) (3997:3997:3997)) - (PORT d[1] (3955:3955:3955) (3883:3883:3883)) - (PORT d[2] (4006:4006:4006) (3895:3895:3895)) - (PORT d[3] (4212:4212:4212) (4117:4117:4117)) - (PORT d[4] (4315:4315:4315) (4187:4187:4187)) - (PORT d[5] (4021:4021:4021) (3945:3945:3945)) - (PORT d[6] (4378:4378:4378) (4355:4355:4355)) - (PORT d[7] (3996:3996:3996) (3938:3938:3938)) - (PORT d[8] (4192:4192:4192) (4072:4072:4072)) - (PORT d[9] (4141:4141:4141) (4229:4229:4229)) - (PORT d[10] (4080:4080:4080) (4007:4007:4007)) - (PORT d[11] (4096:4096:4096) (3973:3973:3973)) - (PORT d[12] (4047:4047:4047) (3950:3950:3950)) - (PORT clk (1598:1598:1598) (1596:1596:1596)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1601:1601:1601) (1599:1599:1599)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1600:1600:1600)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1600:1600:1600)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1600:1600:1600)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1600:1600:1600)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3890:3890:3890) (3959:3959:3959)) - (PORT d[1] (2668:2668:2668) (2802:2802:2802)) - (PORT d[2] (2492:2492:2492) (2533:2533:2533)) - (PORT d[3] (2120:2120:2120) (2205:2205:2205)) - (PORT d[4] (2339:2339:2339) (2426:2426:2426)) - (PORT d[5] (2353:2353:2353) (2440:2440:2440)) - (PORT d[6] (1749:1749:1749) (1794:1794:1794)) - (PORT d[7] (2139:2139:2139) (2164:2164:2164)) - (PORT d[8] (2895:2895:2895) (3020:3020:3020)) - (PORT d[9] (2427:2427:2427) (2496:2496:2496)) - (PORT d[10] (4456:4456:4456) (4549:4549:4549)) - (PORT d[11] (1768:1768:1768) (1835:1835:1835)) - (PORT d[12] (2036:2036:2036) (2099:2099:2099)) - (PORT clk (1642:1642:1642) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (PORT d[0] (3246:3246:3246) (3296:3296:3296)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1636:1636:1636)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (883:883:883)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1457:1457:1457) (1477:1477:1477)) - (PORT clk (1635:1635:1635) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2802:2802:2802) (2864:2864:2864)) - (PORT d[1] (2141:2141:2141) (2242:2242:2242)) - (PORT d[2] (2014:2014:2014) (2042:2042:2042)) - (PORT d[3] (1762:1762:1762) (1815:1815:1815)) - (PORT d[4] (2261:2261:2261) (2299:2299:2299)) - (PORT d[5] (1802:1802:1802) (1892:1892:1892)) - (PORT d[6] (1621:1621:1621) (1629:1629:1629)) - (PORT d[7] (2205:2205:2205) (2254:2254:2254)) - (PORT d[8] (2686:2686:2686) (2758:2758:2758)) - (PORT d[9] (1843:1843:1843) (1889:1889:1889)) - (PORT d[10] (1872:1872:1872) (1913:1913:1913)) - (PORT d[11] (2261:2261:2261) (2308:2308:2308)) - (PORT d[12] (2373:2373:2373) (2396:2396:2396)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2375:2375:2375) (2364:2364:2364)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1662:1662:1662)) - (PORT d[0] (3627:3627:3627) (3623:3623:3623)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1594:1594:1594) (1592:1592:1592)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1898:1898:1898) (1812:1812:1812)) - (PORT clk (1602:1602:1602) (1599:1599:1599)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4101:4101:4101) (4000:4000:4000)) - (PORT d[1] (3952:3952:3952) (3866:3866:3866)) - (PORT d[2] (4011:4011:4011) (3918:3918:3918)) - (PORT d[3] (4159:4159:4159) (4067:4067:4067)) - (PORT d[4] (4060:4060:4060) (3935:3935:3935)) - (PORT d[5] (4328:4328:4328) (4228:4228:4228)) - (PORT d[6] (4144:4144:4144) (4120:4120:4120)) - (PORT d[7] (4041:4041:4041) (3982:3982:3982)) - (PORT d[8] (4200:4200:4200) (4067:4067:4067)) - (PORT d[9] (4128:4128:4128) (4213:4213:4213)) - (PORT d[10] (4041:4041:4041) (3946:3946:3946)) - (PORT d[11] (4367:4367:4367) (4242:4242:4242)) - (PORT d[12] (4125:4125:4125) (4113:4113:4113)) - (PORT clk (1599:1599:1599) (1596:1596:1596)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1599:1599:1599)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1603:1603:1603) (1600:1600:1600)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1603:1603:1603) (1600:1600:1600)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1603:1603:1603) (1600:1600:1600)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1603:1603:1603) (1600:1600:1600)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1595:1595:1595) (1593:1593:1593)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1084:1084:1084) (1099:1099:1099)) - (PORT datab (881:881:881) (891:891:891)) - (PORT datac (1292:1292:1292) (1266:1266:1266)) - (PORT datad (1335:1335:1335) (1322:1322:1322)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (656:656:656) (683:683:683)) + (PORT datab (220:220:220) (288:288:288)) + (PORT datac (2240:2240:2240) (2343:2343:2343)) + (PORT datad (585:585:585) (613:613:613)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -42031,476 +45972,33 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~1) + (INSTANCE D\[4\]\~86) (DELAY (ABSOLUTE - (PORT dataa (1213:1213:1213) (1224:1224:1224)) - (PORT datab (886:886:886) (898:898:898)) - (PORT datac (1327:1327:1327) (1349:1349:1349)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (554:554:554) (554:554:554)) + (PORT datab (2286:2286:2286) (2371:2371:2371)) + (PORT datac (855:855:855) (885:885:885)) + (PORT datad (558:558:558) (559:559:559)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~89) (DELAY (ABSOLUTE - (PORT d[0] (851:851:851) (853:853:853)) - (PORT clk (1638:1638:1638) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3109:3109:3109) (3183:3183:3183)) - (PORT d[1] (1610:1610:1610) (1709:1709:1709)) - (PORT d[2] (1852:1852:1852) (1867:1867:1867)) - (PORT d[3] (2001:2001:2001) (2036:2036:2036)) - (PORT d[4] (1710:1710:1710) (1718:1718:1718)) - (PORT d[5] (1262:1262:1262) (1314:1314:1314)) - (PORT d[6] (1355:1355:1355) (1362:1362:1362)) - (PORT d[7] (3106:3106:3106) (3141:3141:3141)) - (PORT d[8] (2266:2266:2266) (2361:2361:2361)) - (PORT d[9] (3248:3248:3248) (3329:3329:3329)) - (PORT d[10] (2702:2702:2702) (2780:2780:2780)) - (PORT d[11] (1389:1389:1389) (1395:1395:1395)) - (PORT d[12] (1360:1360:1360) (1386:1386:1386)) - (PORT clk (1635:1635:1635) (1664:1664:1664)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3094:3094:3094) (3034:3034:3034)) - (PORT clk (1635:1635:1635) (1664:1664:1664)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (PORT d[0] (1771:1771:1771) (1681:1681:1681)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1630:1630:1630)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1374:1374:1374) (1380:1380:1380)) - (PORT clk (1626:1626:1626) (1655:1655:1655)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3408:3408:3408) (3498:3498:3498)) - (PORT d[1] (1569:1569:1569) (1663:1663:1663)) - (PORT d[2] (3026:3026:3026) (3089:3089:3089)) - (PORT d[3] (2000:2000:2000) (2020:2020:2020)) - (PORT d[4] (2357:2357:2357) (2411:2411:2411)) - (PORT d[5] (1547:1547:1547) (1619:1619:1619)) - (PORT d[6] (1669:1669:1669) (1713:1713:1713)) - (PORT d[7] (1572:1572:1572) (1598:1598:1598)) - (PORT d[8] (3085:3085:3085) (3197:3197:3197)) - (PORT d[9] (2632:2632:2632) (2690:2690:2690)) - (PORT d[10] (3216:3216:3216) (3306:3306:3306)) - (PORT d[11] (1667:1667:1667) (1701:1701:1701)) - (PORT d[12] (1605:1605:1605) (1642:1642:1642)) - (PORT clk (1623:1623:1623) (1653:1653:1653)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1801:1801:1801) (1740:1740:1740)) - (PORT clk (1623:1623:1623) (1653:1653:1653)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1626:1626:1626) (1655:1655:1655)) - (PORT d[0] (2539:2539:2539) (2489:2489:2489)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1627:1627:1627) (1656:1656:1656)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1627:1627:1627) (1656:1656:1656)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1627:1627:1627) (1656:1656:1656)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1627:1627:1627) (1656:1656:1656)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1590:1590:1590) (1619:1619:1619)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (861:861:861) (866:866:866)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (862:862:862) (867:867:867)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (862:862:862) (867:867:867)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (862:862:862) (867:867:867)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1169:1169:1169) (1177:1177:1177)) - (PORT clk (1638:1638:1638) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3109:3109:3109) (3181:3181:3181)) - (PORT d[1] (1236:1236:1236) (1300:1300:1300)) - (PORT d[2] (1799:1799:1799) (1833:1833:1833)) - (PORT d[3] (1433:1433:1433) (1450:1450:1450)) - (PORT d[4] (1740:1740:1740) (1757:1757:1757)) - (PORT d[5] (1521:1521:1521) (1560:1560:1560)) - (PORT d[6] (1100:1100:1100) (1121:1121:1121)) - (PORT d[7] (1350:1350:1350) (1384:1384:1384)) - (PORT d[8] (2320:2320:2320) (2418:2418:2418)) - (PORT d[9] (3238:3238:3238) (3316:3316:3316)) - (PORT d[10] (2664:2664:2664) (2731:2731:2731)) - (PORT d[11] (1162:1162:1162) (1161:1161:1161)) - (PORT d[12] (1034:1034:1034) (1044:1044:1044)) - (PORT clk (1635:1635:1635) (1664:1664:1664)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2652:2652:2652) (2627:2627:2627)) - (PORT clk (1635:1635:1635) (1664:1664:1664)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (PORT d[0] (2959:2959:2959) (2958:2958:2958)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1630:1630:1630)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + (PORT dataa (1074:1074:1074) (1082:1082:1082)) + (PORT datab (1113:1113:1113) (1122:1122:1122)) + (PORT datac (3021:3021:3021) (3172:3172:3172)) + (PORT datad (557:557:557) (560:560:560)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -42509,8 +46007,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1637:1637:1637) (1639:1639:1639)) - (PORT clk (1637:1637:1637) (1665:1665:1665)) + (PORT d[0] (954:954:954) (966:966:966)) + (PORT clk (1638:1638:1638) (1666:1666:1666)) ) ) (TIMINGCHECK @@ -42522,20 +46020,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3128:3128:3128) (3214:3214:3214)) - (PORT d[1] (1579:1579:1579) (1666:1666:1666)) - (PORT d[2] (2493:2493:2493) (2551:2551:2551)) - (PORT d[3] (1985:1985:1985) (2021:2021:2021)) - (PORT d[4] (2035:2035:2035) (2070:2070:2070)) - (PORT d[5] (2222:2222:2222) (2345:2345:2345)) - (PORT d[6] (1954:1954:1954) (2014:2014:2014)) - (PORT d[7] (2290:2290:2290) (2303:2303:2303)) - (PORT d[8] (2819:2819:2819) (2916:2916:2916)) - (PORT d[9] (2386:2386:2386) (2432:2432:2432)) - (PORT d[10] (3501:3501:3501) (3612:3612:3612)) - (PORT d[11] (1655:1655:1655) (1668:1668:1668)) - (PORT d[12] (2144:2144:2144) (2185:2185:2185)) - (PORT clk (1634:1634:1634) (1663:1663:1663)) + (PORT d[0] (3080:3080:3080) (3232:3232:3232)) + (PORT d[1] (1460:1460:1460) (1495:1495:1495)) + (PORT d[2] (963:963:963) (971:971:971)) + (PORT d[3] (1481:1481:1481) (1522:1522:1522)) + (PORT d[4] (2743:2743:2743) (2830:2830:2830)) + (PORT d[5] (899:899:899) (907:907:907)) + (PORT d[6] (1457:1457:1457) (1519:1519:1519)) + (PORT d[7] (1188:1188:1188) (1181:1181:1181)) + (PORT d[8] (1133:1133:1133) (1148:1148:1148)) + (PORT d[9] (1011:1011:1011) (1067:1067:1067)) + (PORT d[10] (956:956:956) (1001:1001:1001)) + (PORT d[11] (2062:2062:2062) (2133:2133:2133)) + (PORT d[12] (1000:1000:1000) (1058:1058:1058)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) ) ) (TIMINGCHECK @@ -42547,8 +46045,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2095:2095:2095) (2041:2041:2041)) - (PORT clk (1634:1634:1634) (1663:1663:1663)) + (PORT d[0] (1097:1097:1097) (1035:1035:1035)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) ) ) (TIMINGCHECK @@ -42560,8 +46058,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1637:1637:1637) (1665:1665:1665)) - (PORT d[0] (2457:2457:2457) (2386:2386:2386)) + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (PORT d[0] (2146:2146:2146) (2099:2099:2099)) ) ) ) @@ -42570,7 +46068,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) @@ -42580,7 +46078,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -42590,7 +46088,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -42600,7 +46098,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -42610,7 +46108,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1601:1601:1601) (1629:1629:1629)) + (PORT clk (1602:1602:1602) (1630:1630:1630)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -42624,7 +46122,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (872:872:872) (876:876:876)) + (PORT clk (873:873:873) (877:877:877)) ) ) ) @@ -42633,7 +46131,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) + (PORT clk (874:874:874) (878:878:878)) ) ) ) @@ -42642,7 +46140,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) + (PORT clk (874:874:874) (878:878:878)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -42652,53 +46150,1139 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (933:933:933) (932:932:932)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3090:3090:3090) (3254:3254:3254)) + (PORT d[1] (1215:1215:1215) (1249:1249:1249)) + (PORT d[2] (1570:1570:1570) (1595:1595:1595)) + (PORT d[3] (1476:1476:1476) (1511:1511:1511)) + (PORT d[4] (2752:2752:2752) (2817:2817:2817)) + (PORT d[5] (1175:1175:1175) (1198:1198:1198)) + (PORT d[6] (1212:1212:1212) (1258:1258:1258)) + (PORT d[7] (1237:1237:1237) (1250:1250:1250)) + (PORT d[8] (1433:1433:1433) (1471:1471:1471)) + (PORT d[9] (1016:1016:1016) (1076:1076:1076)) + (PORT d[10] (965:965:965) (1015:1015:1015)) + (PORT d[11] (2023:2023:2023) (2094:2094:2094)) + (PORT d[12] (1265:1265:1265) (1320:1320:1320)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1120:1120:1120) (1080:1080:1080)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (PORT d[0] (2136:2136:2136) (2108:2108:2108)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (869:869:869) (862:862:862)) + (PORT clk (1637:1637:1637) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2485:2485:2485) (2615:2615:2615)) + (PORT d[1] (1427:1427:1427) (1438:1438:1438)) + (PORT d[2] (1257:1257:1257) (1285:1285:1285)) + (PORT d[3] (1226:1226:1226) (1262:1262:1262)) + (PORT d[4] (2463:2463:2463) (2538:2538:2538)) + (PORT d[5] (1467:1467:1467) (1492:1492:1492)) + (PORT d[6] (1404:1404:1404) (1453:1453:1453)) + (PORT d[7] (1465:1465:1465) (1474:1474:1474)) + (PORT d[8] (1420:1420:1420) (1468:1468:1468)) + (PORT d[9] (1523:1523:1523) (1581:1581:1581)) + (PORT d[10] (1240:1240:1240) (1300:1300:1300)) + (PORT d[11] (1752:1752:1752) (1814:1814:1814)) + (PORT d[12] (1282:1282:1282) (1352:1352:1352)) + (PORT clk (1634:1634:1634) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1155:1155:1155) (1130:1130:1130)) + (PORT clk (1634:1634:1634) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1664:1664:1664)) + (PORT d[0] (2155:2155:2155) (2142:2142:2142)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1601:1601:1601) (1628:1628:1628)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (875:875:875)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~2) + (INSTANCE D\[4\]\~93) (DELAY (ABSOLUTE - (PORT dataa (1690:1690:1690) (1647:1647:1647)) - (PORT datab (1084:1084:1084) (1080:1080:1080)) - (PORT datad (1566:1566:1566) (1563:1563:1563)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (PORT dataa (840:840:840) (817:817:817)) + (PORT datab (1139:1139:1139) (1179:1179:1179)) + (PORT datad (842:842:842) (831:831:831)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~3) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (1359:1359:1359) (1382:1382:1382)) - (PORT datab (1365:1365:1365) (1350:1350:1350)) - (PORT datac (1957:1957:1957) (1959:1959:1959)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (PORT d[0] (1283:1283:1283) (1319:1319:1319)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2759:2759:2759) (2871:2871:2871)) + (PORT d[1] (2684:2684:2684) (2703:2703:2703)) + (PORT d[2] (931:931:931) (943:943:943)) + (PORT d[3] (1205:1205:1205) (1215:1215:1215)) + (PORT d[4] (1924:1924:1924) (1947:1947:1947)) + (PORT d[5] (876:876:876) (884:884:884)) + (PORT d[6] (1101:1101:1101) (1092:1092:1092)) + (PORT d[7] (2454:2454:2454) (2524:2524:2524)) + (PORT d[8] (1447:1447:1447) (1488:1488:1488)) + (PORT d[9] (406:406:406) (428:428:428)) + (PORT d[10] (398:398:398) (419:419:419)) + (PORT d[11] (2578:2578:2578) (2674:2674:2674)) + (PORT d[12] (693:693:693) (716:716:716)) + (PORT clk (1629:1629:1629) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1143:1143:1143) (1102:1102:1102)) + (PORT clk (1629:1629:1629) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1660:1660:1660)) + (PORT d[0] (1583:1583:1583) (1522:1522:1522)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1596:1596:1596) (1624:1624:1624)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (871:871:871)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~94) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (878:878:878)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1109:1109:1109) (1149:1149:1149)) + (PORT datad (1348:1348:1348) (1334:1334:1334)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~109) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (631:631:631) (693:693:693)) - (PORT datab (1093:1093:1093) (1105:1105:1105)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (158:158:158) (178:178:178)) + (PORT d[0] (1115:1115:1115) (1080:1080:1080)) + (PORT clk (1634:1634:1634) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2877:2877:2877) (2953:2953:2953)) + (PORT d[1] (1951:1951:1951) (1976:1976:1976)) + (PORT d[2] (1498:1498:1498) (1544:1544:1544)) + (PORT d[3] (1410:1410:1410) (1446:1446:1446)) + (PORT d[4] (2502:2502:2502) (2567:2567:2567)) + (PORT d[5] (1454:1454:1454) (1489:1489:1489)) + (PORT d[6] (1403:1403:1403) (1422:1422:1422)) + (PORT d[7] (1786:1786:1786) (1801:1801:1801)) + (PORT d[8] (3238:3238:3238) (3291:3291:3291)) + (PORT d[9] (1314:1314:1314) (1390:1390:1390)) + (PORT d[10] (1538:1538:1538) (1589:1589:1589)) + (PORT d[11] (1732:1732:1732) (1777:1777:1777)) + (PORT d[12] (1537:1537:1537) (1603:1603:1603)) + (PORT clk (1631:1631:1631) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1370:1370:1370) (1334:1334:1334)) + (PORT clk (1631:1631:1631) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1662:1662:1662)) + (PORT d[0] (2632:2632:2632) (2634:2634:2634)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1593:1593:1593) (1592:1592:1592)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1688:1688:1688) (1685:1685:1685)) + (PORT clk (1601:1601:1601) (1599:1599:1599)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4140:4140:4140) (4100:4100:4100)) + (PORT d[1] (4066:4066:4066) (4031:4031:4031)) + (PORT d[2] (4099:4099:4099) (4037:4037:4037)) + (PORT d[3] (3955:3955:3955) (3939:3939:3939)) + (PORT d[4] (4028:4028:4028) (3932:3932:3932)) + (PORT d[5] (4099:4099:4099) (4068:4068:4068)) + (PORT d[6] (4141:4141:4141) (4005:4005:4005)) + (PORT d[7] (4061:4061:4061) (4022:4022:4022)) + (PORT d[8] (4124:4124:4124) (4102:4102:4102)) + (PORT d[9] (4209:4209:4209) (4171:4171:4171)) + (PORT d[10] (4161:4161:4161) (4134:4134:4134)) + (PORT d[11] (4134:4134:4134) (4073:4073:4073)) + (PORT d[12] (4078:4078:4078) (3972:3972:3972)) + (PORT clk (1598:1598:1598) (1596:1596:1596)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1601:1601:1601) (1599:1599:1599)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1600:1600:1600)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1600:1600:1600)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1600:1600:1600)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1600:1600:1600)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1594:1594:1594) (1593:1593:1593)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1140:1140:1140) (1109:1109:1109)) + (PORT clk (1636:1636:1636) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2878:2878:2878) (2954:2954:2954)) + (PORT d[1] (1433:1433:1433) (1454:1454:1454)) + (PORT d[2] (1508:1508:1508) (1541:1541:1541)) + (PORT d[3] (1411:1411:1411) (1440:1440:1440)) + (PORT d[4] (2462:2462:2462) (2535:2535:2535)) + (PORT d[5] (1450:1450:1450) (1482:1482:1482)) + (PORT d[6] (1429:1429:1429) (1481:1481:1481)) + (PORT d[7] (1543:1543:1543) (1569:1569:1569)) + (PORT d[8] (1420:1420:1420) (1469:1469:1469)) + (PORT d[9] (1288:1288:1288) (1360:1360:1360)) + (PORT d[10] (1270:1270:1270) (1335:1335:1335)) + (PORT d[11] (1720:1720:1720) (1776:1776:1776)) + (PORT d[12] (1283:1283:1283) (1353:1353:1353)) + (PORT clk (1633:1633:1633) (1661:1661:1661)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1309:1309:1309) (1250:1250:1250)) + (PORT clk (1633:1633:1633) (1661:1661:1661)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (PORT d[0] (2363:2363:2363) (2353:2353:2353)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1595:1595:1595) (1593:1593:1593)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1698:1698:1698) (1695:1695:1695)) + (PORT clk (1603:1603:1603) (1600:1600:1600)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4136:4136:4136) (4113:4113:4113)) + (PORT d[1] (4031:4031:4031) (3982:3982:3982)) + (PORT d[2] (4143:4143:4143) (4073:4073:4073)) + (PORT d[3] (3977:3977:3977) (3962:3962:3962)) + (PORT d[4] (3998:3998:3998) (3956:3956:3956)) + (PORT d[5] (4063:4063:4063) (4024:4024:4024)) + (PORT d[6] (4108:4108:4108) (3971:3971:3971)) + (PORT d[7] (4041:4041:4041) (4018:4018:4018)) + (PORT d[8] (4094:4094:4094) (4068:4068:4068)) + (PORT d[9] (4136:4136:4136) (4082:4082:4082)) + (PORT d[10] (4197:4197:4197) (4167:4167:4167)) + (PORT d[11] (4160:4160:4160) (4096:4096:4096)) + (PORT d[12] (4059:4059:4059) (3968:3968:3968)) + (PORT clk (1600:1600:1600) (1597:1597:1597)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1600:1600:1600)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1604:1604:1604) (1601:1601:1601)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1604:1604:1604) (1601:1601:1601)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1604:1604:1604) (1601:1601:1601)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1604:1604:1604) (1601:1601:1601)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1999:1999:1999) (2048:2048:2048)) + (PORT d[1] (2191:2191:2191) (2224:2224:2224)) + (PORT d[2] (2259:2259:2259) (2315:2315:2315)) + (PORT d[3] (2146:2146:2146) (2181:2181:2181)) + (PORT d[4] (1897:1897:1897) (1929:1929:1929)) + (PORT d[5] (2232:2232:2232) (2287:2287:2287)) + (PORT d[6] (2281:2281:2281) (2364:2364:2364)) + (PORT d[7] (2348:2348:2348) (2388:2388:2388)) + (PORT d[8] (2351:2351:2351) (2363:2363:2363)) + (PORT d[9] (2152:2152:2152) (2263:2263:2263)) + (PORT d[10] (2791:2791:2791) (2826:2826:2826)) + (PORT d[11] (1943:1943:1943) (1974:1974:1974)) + (PORT d[12] (2104:2104:2104) (2206:2206:2206)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (PORT d[0] (2415:2415:2415) (2444:2444:2444)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1640:1640:1640)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (887:887:887)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (888:888:888)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (888:888:888)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (888:888:888)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (1118:1118:1118) (1132:1132:1132)) + (PORT datab (666:666:666) (696:696:696)) + (PORT datac (860:860:860) (852:852:852)) + (PORT datad (1118:1118:1118) (1101:1101:1101)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2033:2033:2033) (2075:2075:2075)) + (PORT d[1] (2213:2213:2213) (2255:2255:2255)) + (PORT d[2] (2382:2382:2382) (2422:2422:2422)) + (PORT d[3] (2799:2799:2799) (2812:2812:2812)) + (PORT d[4] (1811:1811:1811) (1878:1878:1878)) + (PORT d[5] (3194:3194:3194) (3207:3207:3207)) + (PORT d[6] (2583:2583:2583) (2584:2584:2584)) + (PORT d[7] (3114:3114:3114) (3084:3084:3084)) + (PORT d[8] (1945:1945:1945) (1976:1976:1976)) + (PORT d[9] (2814:2814:2814) (2873:2873:2873)) + (PORT d[10] (2147:2147:2147) (2145:2145:2145)) + (PORT d[11] (2295:2295:2295) (2359:2359:2359)) + (PORT d[12] (2989:2989:2989) (3069:3069:3069)) + (PORT clk (1652:1652:1652) (1680:1680:1680)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1680:1680:1680)) + (PORT d[0] (2632:2632:2632) (2627:2627:2627)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1681:1681:1681)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1619:1619:1619) (1646:1646:1646)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (890:890:890) (893:893:893)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (891:891:891) (894:894:894)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (891:891:891) (894:894:894)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (891:891:891) (894:894:894)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~91) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (824:824:824)) + (PORT datab (1217:1217:1217) (1249:1249:1249)) + (PORT datac (163:163:163) (195:195:195)) + (PORT datad (1469:1469:1469) (1460:1460:1460)) (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datab combout (308:308:308) (324:324:324)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -42706,32 +47290,64 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~97) + (INSTANCE D\[4\]\~92) (DELAY (ABSOLUTE - (PORT dataa (820:820:820) (822:822:822)) - (PORT datab (1441:1441:1441) (1442:1442:1442)) - (PORT datac (1357:1357:1357) (1385:1385:1385)) - (PORT datad (167:167:167) (191:191:191)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (910:910:910) (909:909:909)) + (PORT datab (666:666:666) (695:695:695)) + (PORT datac (164:164:164) (198:198:198)) + (PORT datad (287:287:287) (294:294:294)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~98) + (INSTANCE D\[4\]\~125) (DELAY (ABSOLUTE - (PORT dataa (1076:1076:1076) (1121:1121:1121)) - (PORT datab (1558:1558:1558) (1503:1503:1503)) - (PORT datac (1358:1358:1358) (1385:1385:1385)) - (PORT datad (158:158:158) (179:179:179)) + (PORT dataa (2374:2374:2374) (2511:2511:2511)) + (PORT datab (1289:1289:1289) (1316:1316:1316)) + (PORT datac (530:530:530) (517:517:517)) + (PORT datad (299:299:299) (297:297:297)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~110) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (862:862:862)) + (PORT datab (851:851:851) (852:852:852)) + (PORT datac (164:164:164) (198:198:198)) + (PORT datad (583:583:583) (579:579:579)) (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~111) + (DELAY + (ABSOLUTE + (PORT dataa (2077:2077:2077) (2056:2056:2056)) + (PORT datab (405:405:405) (418:418:418)) + (PORT datac (175:175:175) (208:208:208)) + (PORT datad (1169:1169:1169) (1220:1220:1220)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -42741,13 +47357,13 @@ (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) (DELAY (ABSOLUTE - (PORT dataa (899:899:899) (937:937:937)) - (PORT datab (1408:1408:1408) (1363:1363:1363)) - (PORT datac (209:209:209) (258:258:258)) - (PORT datad (1071:1071:1071) (1059:1059:1059)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (1559:1559:1559) (1617:1617:1617)) + (PORT datab (382:382:382) (415:415:415)) + (PORT datac (501:501:501) (489:489:489)) + (PORT datad (1049:1049:1049) (1028:1028:1028)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -42773,11 +47389,11 @@ (INSTANCE z80_\|bus_control_\|db\[4\]\~18) (DELAY (ABSOLUTE - (PORT dataa (365:365:365) (415:415:415)) - (PORT datab (355:355:355) (377:377:377)) - (PORT datad (619:619:619) (624:624:624)) + (PORT dataa (240:240:240) (313:313:313)) + (PORT datab (392:392:392) (400:400:400)) + (PORT datad (358:358:358) (368:368:368)) (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -42787,13 +47403,13 @@ (INSTANCE z80_\|bus_control_\|db\[4\]\~19) (DELAY (ABSOLUTE - (PORT dataa (904:904:904) (906:906:906)) - (PORT datab (856:856:856) (848:848:848)) - (PORT datac (821:821:821) (838:838:838)) - (PORT datad (826:826:826) (841:841:841)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (1048:1048:1048) (1033:1033:1033)) + (PORT datab (311:311:311) (329:329:329)) + (PORT datac (490:490:490) (480:480:480)) + (PORT datad (198:198:198) (226:226:226)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -42803,244 +47419,10 @@ (INSTANCE z80_\|ir_\|opcode\[4\]) (DELAY (ABSOLUTE - (PORT clk (1345:1345:1345) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1361:1361:1361)) - (PORT ena (1363:1363:1363) (1319:1319:1319)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~0) - (DELAY - (ABSOLUTE - (PORT datac (1315:1315:1315) (1385:1385:1385)) - (PORT datad (1349:1349:1349) (1412:1412:1412)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1284:1284:1284) (1279:1279:1279)) - (PORT datab (917:917:917) (931:931:931)) - (PORT datac (1485:1485:1485) (1580:1580:1580)) - (PORT datad (1131:1131:1131) (1161:1161:1161)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1184:1184:1184) (1229:1229:1229)) - (PORT datab (1408:1408:1408) (1433:1433:1433)) - (PORT datac (762:762:762) (748:748:748)) - (PORT datad (183:183:183) (207:207:207)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~3) - (DELAY - (ABSOLUTE - (PORT datab (1421:1421:1421) (1477:1477:1477)) - (PORT datac (1249:1249:1249) (1279:1279:1279)) - (PORT datad (2264:2264:2264) (2402:2402:2402)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (801:801:801) (822:822:822)) - (PORT datab (856:856:856) (852:852:852)) - (PORT datac (1586:1586:1586) (1591:1591:1591)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (397:397:397) (409:409:409)) - (PORT datab (1095:1095:1095) (1125:1125:1125)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (333:333:333) (345:345:345)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~11) - (DELAY - (ABSOLUTE - (PORT dataa (854:854:854) (888:888:888)) - (PORT datab (574:574:574) (600:600:600)) - (PORT datac (820:820:820) (837:837:837)) - (PORT datad (822:822:822) (813:813:813)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1837:1837:1837) (1846:1846:1846)) - (PORT datab (1056:1056:1056) (1022:1022:1022)) - (PORT datac (788:788:788) (768:768:768)) - (PORT datad (591:591:591) (611:611:611)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~13) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (219:219:219)) - (PORT datab (559:559:559) (548:548:548)) - (PORT datac (497:497:497) (488:488:488)) - (PORT datad (165:165:165) (188:188:188)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1451:1451:1451) (1497:1497:1497)) - (PORT datab (800:800:800) (797:797:797)) - (PORT datac (1353:1353:1353) (1351:1351:1351)) - (PORT datad (989:989:989) (953:953:953)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~15) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (581:581:581)) - (PORT datab (809:809:809) (826:826:826)) - (PORT datac (793:793:793) (777:777:777)) - (PORT datad (1104:1104:1104) (1100:1100:1100)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1189:1189:1189) (1191:1191:1191)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (200:200:200) (258:258:258)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mwr) - (DELAY - (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1217:1217:1217) (1223:1223:1223)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|mwr_wr) - (DELAY - (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) - (PORT asdata (511:511:511) (578:578:578)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1217:1217:1217) (1223:1223:1223)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (832:832:832) (819:819:819)) + (PORT clrn (1396:1396:1396) (1368:1368:1368)) + (PORT ena (1804:1804:1804) (1767:1767:1767)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -43052,683 +47434,200 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) + (INSTANCE z80_\|pla_decode_\|Equal32\~0) (DELAY (ABSOLUTE - (PORT dataa (804:804:804) (796:796:796)) - (PORT datab (331:331:331) (348:348:348)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT datac (1788:1788:1788) (1789:1789:1789)) + (PORT datad (2385:2385:2385) (2404:2404:2404)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~84) + (INSTANCE z80_\|pla_decode_\|Equal36\~0) (DELAY (ABSOLUTE - (PORT dataa (1623:1623:1623) (1655:1655:1655)) - (PORT datab (1476:1476:1476) (1530:1530:1530)) - (PORT datac (1099:1099:1099) (1117:1117:1117)) - (PORT datad (1134:1134:1134) (1160:1160:1160)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (PORT dataa (830:830:830) (833:833:833)) + (PORT datab (625:625:625) (630:630:630)) + (PORT datac (1901:1901:1901) (1972:1972:1972)) + (PORT datad (1330:1330:1330) (1299:1299:1299)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (259:259:259)) + (PORT datab (847:847:847) (859:859:859)) + (PORT datac (1615:1615:1615) (1640:1640:1640)) + (PORT datad (593:593:593) (610:610:610)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (635:635:635)) + (PORT datab (363:363:363) (383:383:383)) + (PORT datac (1300:1300:1300) (1335:1335:1335)) + (PORT datad (330:330:330) (339:339:339)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2142:2142:2142) (2194:2194:2194)) + (PORT datab (1506:1506:1506) (1483:1483:1483)) + (PORT datac (1247:1247:1247) (1363:1363:1363)) + (PORT datad (1194:1194:1194) (1145:1145:1145)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) (DELAY (ABSOLUTE - (PORT d[0] (1084:1084:1084) (1083:1083:1083)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT asdata (1116:1116:1116) (1117:1117:1117)) + (PORT clrn (1408:1408:1408) (1376:1376:1376)) + (PORT ena (906:906:906) (903:903:903)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) (DELAY (ABSOLUTE - (PORT d[0] (3903:3903:3903) (3984:3984:3984)) - (PORT d[1] (2655:2655:2655) (2790:2790:2790)) - (PORT d[2] (2992:2992:2992) (3016:3016:3016)) - (PORT d[3] (2356:2356:2356) (2437:2437:2437)) - (PORT d[4] (2074:2074:2074) (2161:2161:2161)) - (PORT d[5] (2391:2391:2391) (2481:2481:2481)) - (PORT d[6] (1728:1728:1728) (1769:1769:1769)) - (PORT d[7] (2149:2149:2149) (2178:2178:2178)) - (PORT d[8] (2888:2888:2888) (3027:3027:3027)) - (PORT d[9] (2688:2688:2688) (2747:2747:2747)) - (PORT d[10] (4446:4446:4446) (4545:4545:4545)) - (PORT d[11] (2033:2033:2033) (2092:2092:2092)) - (PORT d[12] (2027:2027:2027) (2085:2085:2085)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1812:1812:1812) (1737:1737:1737)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (PORT d[0] (2104:2104:2104) (2069:2069:2069)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1634:1634:1634)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (878:878:878) (881:881:881)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1106:1106:1106) (1100:1100:1100)) - (PORT clk (1644:1644:1644) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3898:3898:3898) (3977:3977:3977)) - (PORT d[1] (2675:2675:2675) (2810:2810:2810)) - (PORT d[2] (2544:2544:2544) (2585:2585:2585)) - (PORT d[3] (2356:2356:2356) (2433:2433:2433)) - (PORT d[4] (2094:2094:2094) (2182:2182:2182)) - (PORT d[5] (2365:2365:2365) (2452:2452:2452)) - (PORT d[6] (1754:1754:1754) (1791:1791:1791)) - (PORT d[7] (2123:2123:2123) (2149:2149:2149)) - (PORT d[8] (2905:2905:2905) (3041:3041:3041)) - (PORT d[9] (2410:2410:2410) (2473:2473:2473)) - (PORT d[10] (4441:4441:4441) (4538:4538:4538)) - (PORT d[11] (1762:1762:1762) (1827:1827:1827)) - (PORT d[12] (2035:2035:2035) (2098:2098:2098)) - (PORT clk (1641:1641:1641) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2200:2200:2200) (2122:2122:2122)) - (PORT clk (1641:1641:1641) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1670:1670:1670)) - (PORT d[0] (2614:2614:2614) (2527:2527:2527)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1608:1608:1608) (1634:1634:1634)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (881:881:881)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (817:817:817) (820:820:820)) - (PORT clk (1638:1638:1638) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1228:1228:1228) (1255:1255:1255)) - (PORT d[1] (1897:1897:1897) (2022:2022:2022)) - (PORT d[2] (2775:2775:2775) (2823:2823:2823)) - (PORT d[3] (2397:2397:2397) (2495:2495:2495)) - (PORT d[4] (2384:2384:2384) (2480:2480:2480)) - (PORT d[5] (2636:2636:2636) (2730:2730:2730)) - (PORT d[6] (1805:1805:1805) (1869:1869:1869)) - (PORT d[7] (2410:2410:2410) (2444:2444:2444)) - (PORT d[8] (3147:3147:3147) (3288:3288:3288)) - (PORT d[9] (2709:2709:2709) (2776:2776:2776)) - (PORT d[10] (4723:4723:4723) (4808:4808:4808)) - (PORT d[11] (1794:1794:1794) (1853:1853:1853)) - (PORT d[12] (1761:1761:1761) (1812:1812:1812)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1125:1125:1125) (1096:1096:1096)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1665:1665:1665)) - (PORT d[0] (2299:2299:2299) (2237:2237:2237)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1629:1629:1629)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + (PORT dataa (637:637:637) (671:671:671)) + (PORT datab (856:856:856) (857:857:857)) + (PORT datac (972:972:972) (983:983:983)) + (PORT datad (1094:1094:1094) (1125:1125:1125)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~6) + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) (DELAY (ABSOLUTE - (PORT dataa (1313:1313:1313) (1351:1351:1351)) - (PORT datab (897:897:897) (941:941:941)) - (PORT datac (1013:1013:1013) (988:988:988)) - (PORT datad (779:779:779) (758:758:758)) + (PORT dataa (780:780:780) (770:770:770)) + (PORT datab (1050:1050:1050) (1048:1048:1048)) + (PORT datac (962:962:962) (937:937:937)) + (PORT datad (768:768:768) (757:757:757)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_yf) (DELAY (ABSOLUTE - (PORT d[0] (1106:1106:1106) (1110:1110:1110)) - (PORT clk (1636:1636:1636) (1662:1662:1662)) + (PORT clk (1339:1339:1339) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~15) (DELAY (ABSOLUTE - (PORT d[0] (3118:3118:3118) (3206:3206:3206)) - (PORT d[1] (1574:1574:1574) (1682:1682:1682)) - (PORT d[2] (2764:2764:2764) (2820:2820:2820)) - (PORT d[3] (2036:2036:2036) (2067:2067:2067)) - (PORT d[4] (2319:2319:2319) (2363:2363:2363)) - (PORT d[5] (2234:2234:2234) (2357:2357:2357)) - (PORT d[6] (1950:1950:1950) (2007:2007:2007)) - (PORT d[7] (2300:2300:2300) (2311:2311:2311)) - (PORT d[8] (2804:2804:2804) (2907:2907:2907)) - (PORT d[9] (2345:2345:2345) (2391:2391:2391)) - (PORT d[10] (3492:3492:3492) (3594:3594:3594)) - (PORT d[11] (1620:1620:1620) (1617:1617:1617)) - (PORT d[12] (2158:2158:2158) (2197:2197:2197)) - (PORT clk (1633:1633:1633) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2044:2044:2044) (1984:1984:1984)) - (PORT clk (1633:1633:1633) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1662:1662:1662)) - (PORT d[0] (2515:2515:2515) (2442:2442:2442)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1600:1600:1600) (1626:1626:1626)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (873:873:873)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + (PORT dataa (558:558:558) (570:570:570)) + (PORT datab (1082:1082:1082) (1083:1083:1083)) + (PORT datac (608:608:608) (632:632:632)) + (PORT datad (547:547:547) (546:546:546)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) + (INSTANCE z80_\|alu_control_\|db\[5\]\~16) (DELAY (ABSOLUTE - (PORT dataa (1341:1341:1341) (1343:1343:1343)) - (PORT datab (1065:1065:1065) (1048:1048:1048)) - (PORT datac (155:155:155) (184:184:184)) - (PORT datad (1316:1316:1316) (1315:1315:1315)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (779:779:779) (808:808:808)) + (PORT datab (572:572:572) (578:578:578)) + (PORT datac (1301:1301:1301) (1331:1331:1331)) + (PORT datad (567:567:567) (574:574:574)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (187:187:187) (223:223:223)) + (PORT datab (1039:1039:1039) (1003:1003:1003)) + (PORT datac (783:783:783) (773:773:773)) + (PORT datad (184:184:184) (207:207:207)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1655:1655:1655) (1653:1653:1653)) + (PORT d[0] (1369:1369:1369) (1343:1343:1343)) (PORT clk (1631:1631:1631) (1657:1657:1657)) ) ) @@ -43738,22 +47637,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3090:3090:3090) (3149:3149:3149)) - (PORT d[1] (2170:2170:2170) (2280:2280:2280)) - (PORT d[2] (2054:2054:2054) (2074:2074:2074)) - (PORT d[3] (1760:1760:1760) (1812:1812:1812)) - (PORT d[4] (2275:2275:2275) (2299:2299:2299)) - (PORT d[5] (1818:1818:1818) (1900:1900:1900)) - (PORT d[6] (1325:1325:1325) (1345:1345:1345)) - (PORT d[7] (1367:1367:1367) (1391:1391:1391)) - (PORT d[8] (2695:2695:2695) (2775:2775:2775)) - (PORT d[9] (1844:1844:1844) (1890:1890:1890)) - (PORT d[10] (1848:1848:1848) (1885:1885:1885)) - (PORT d[11] (1347:1347:1347) (1357:1357:1357)) - (PORT d[12] (1878:1878:1878) (1897:1897:1897)) + (PORT d[0] (2864:2864:2864) (2925:2925:2925)) + (PORT d[1] (1709:1709:1709) (1735:1735:1735)) + (PORT d[2] (1538:1538:1538) (1578:1578:1578)) + (PORT d[3] (1996:1996:1996) (2051:2051:2051)) + (PORT d[4] (2211:2211:2211) (2258:2258:2258)) + (PORT d[5] (1915:1915:1915) (1940:1940:1940)) + (PORT d[6] (1725:1725:1725) (1793:1793:1793)) + (PORT d[7] (1829:1829:1829) (1859:1859:1859)) + (PORT d[8] (3188:3188:3188) (3236:3236:3236)) + (PORT d[9] (1599:1599:1599) (1687:1687:1687)) + (PORT d[10] (3579:3579:3579) (3632:3632:3632)) + (PORT d[11] (2472:2472:2472) (2519:2519:2519)) + (PORT d[12] (2278:2278:2278) (2358:2358:2358)) (PORT clk (1628:1628:1628) (1655:1655:1655)) ) ) @@ -43763,10 +47662,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2618:2618:2618) (2589:2589:2589)) + (PORT d[0] (2149:2149:2149) (2099:2099:2099)) (PORT clk (1628:1628:1628) (1655:1655:1655)) ) ) @@ -43776,17 +47675,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1631:1631:1631) (1657:1657:1657)) - (PORT d[0] (3631:3631:3631) (3630:3630:3630)) + (PORT d[0] (2628:2628:2628) (2625:2625:2625)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1632:1632:1632) (1658:1658:1658)) @@ -43796,7 +47695,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1632:1632:1632) (1658:1658:1658)) @@ -43806,7 +47705,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1632:1632:1632) (1658:1658:1658)) @@ -43816,7 +47715,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1632:1632:1632) (1658:1658:1658)) @@ -43826,7 +47725,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1590:1590:1590) (1587:1587:1587)) @@ -43840,10 +47739,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1120:1120:1120) (1076:1076:1076)) + (PORT d[0] (1680:1680:1680) (1682:1682:1682)) (PORT clk (1598:1598:1598) (1594:1594:1594)) ) ) @@ -43853,22 +47752,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4121:4121:4121) (4013:4013:4013)) - (PORT d[1] (3945:3945:3945) (3855:3855:3855)) - (PORT d[2] (4002:4002:4002) (3896:3896:3896)) - (PORT d[3] (4214:4214:4214) (4129:4129:4129)) - (PORT d[4] (4041:4041:4041) (3914:3914:3914)) - (PORT d[5] (4057:4057:4057) (3974:3974:3974)) - (PORT d[6] (4333:4333:4333) (4305:4305:4305)) - (PORT d[7] (4082:4082:4082) (4025:4025:4025)) - (PORT d[8] (4208:4208:4208) (4078:4078:4078)) - (PORT d[9] (4362:4362:4362) (4432:4432:4432)) - (PORT d[10] (4090:4090:4090) (4015:4015:4015)) - (PORT d[11] (4073:4073:4073) (3949:3949:3949)) - (PORT d[12] (4364:4364:4364) (4258:4258:4258)) + (PORT d[0] (4049:4049:4049) (3977:3977:3977)) + (PORT d[1] (3968:3968:3968) (3990:3990:3990)) + (PORT d[2] (4092:4092:4092) (4022:4022:4022)) + (PORT d[3] (3942:3942:3942) (3914:3914:3914)) + (PORT d[4] (4113:4113:4113) (4038:4038:4038)) + (PORT d[5] (4075:4075:4075) (4052:4052:4052)) + (PORT d[6] (4048:4048:4048) (3929:3929:3929)) + (PORT d[7] (4042:4042:4042) (4014:4014:4014)) + (PORT d[8] (4128:4128:4128) (4009:4009:4009)) + (PORT d[9] (4147:4147:4147) (4084:4084:4084)) + (PORT d[10] (4100:4100:4100) (4051:4051:4051)) + (PORT d[11] (4146:4146:4146) (4095:4095:4095)) + (PORT d[12] (4020:4020:4020) (3883:3883:3883)) (PORT clk (1595:1595:1595) (1591:1591:1591)) ) ) @@ -43878,7 +47777,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1598:1598:1598) (1594:1594:1594)) @@ -43887,7 +47786,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) (DELAY (ABSOLUTE (PORT clk (1599:1599:1599) (1595:1595:1595)) @@ -43897,7 +47796,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1599:1599:1599) (1595:1595:1595)) @@ -43906,7 +47805,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1599:1599:1599) (1595:1595:1595)) @@ -43916,7 +47815,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1599:1599:1599) (1595:1595:1595)) @@ -43926,23 +47825,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2416:2416:2416) (2419:2419:2419)) - (PORT d[1] (1915:1915:1915) (2042:2042:2042)) - (PORT d[2] (2107:2107:2107) (2177:2177:2177)) - (PORT d[3] (2104:2104:2104) (2154:2154:2154)) - (PORT d[4] (2750:2750:2750) (2873:2873:2873)) - (PORT d[5] (1930:1930:1930) (2036:2036:2036)) - (PORT d[6] (1710:1710:1710) (1749:1749:1749)) - (PORT d[7] (2359:2359:2359) (2360:2360:2360)) - (PORT d[8] (2561:2561:2561) (2682:2682:2682)) - (PORT d[9] (1438:1438:1438) (1472:1472:1472)) - (PORT d[10] (1709:1709:1709) (1741:1741:1741)) - (PORT d[11] (2675:2675:2675) (2708:2708:2708)) - (PORT d[12] (1424:1424:1424) (1457:1457:1457)) - (PORT clk (1652:1652:1652) (1680:1680:1680)) + (PORT d[0] (1550:1550:1550) (1606:1606:1606)) + (PORT d[1] (2532:2532:2532) (2555:2555:2555)) + (PORT d[2] (2382:2382:2382) (2423:2423:2423)) + (PORT d[3] (2288:2288:2288) (2312:2312:2312)) + (PORT d[4] (2270:2270:2270) (2269:2269:2269)) + (PORT d[5] (2680:2680:2680) (2702:2702:2702)) + (PORT d[6] (2582:2582:2582) (2591:2591:2591)) + (PORT d[7] (2965:2965:2965) (2961:2961:2961)) + (PORT d[8] (2156:2156:2156) (2169:2169:2169)) + (PORT d[9] (2831:2831:2831) (2893:2893:2893)) + (PORT d[10] (2156:2156:2156) (2158:2158:2158)) + (PORT d[11] (2330:2330:2330) (2394:2394:2394)) + (PORT d[12] (2720:2720:2720) (2792:2792:2792)) + (PORT clk (1654:1654:1654) (1681:1681:1681)) ) ) (TIMINGCHECK @@ -43951,30 +47850,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1652:1652:1652) (1680:1680:1680)) - (PORT d[0] (2018:2018:2018) (2009:2009:2009)) + (PORT clk (1654:1654:1654) (1681:1681:1681)) + (PORT d[0] (2640:2640:2640) (2655:2655:2655)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1653:1653:1653) (1681:1681:1681)) + (PORT clk (1655:1655:1655) (1682:1682:1682)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1619:1619:1619) (1646:1646:1646)) + (PORT clk (1621:1621:1621) (1647:1647:1647)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -43985,60 +47884,418 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (890:890:890) (893:893:893)) + (PORT clk (892:892:892) (894:894:894)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (891:891:891) (894:894:894)) + (PORT clk (893:893:893) (895:895:895)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (891:891:891) (894:894:894)) + (PORT clk (893:893:893) (895:895:895)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (891:891:891) (894:894:894)) + (PORT clk (893:893:893) (895:895:895)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3298:3298:3298) (3351:3351:3351)) - (PORT d[1] (1592:1592:1592) (1680:1680:1680)) - (PORT d[2] (2484:2484:2484) (2533:2533:2533)) - (PORT d[3] (1975:1975:1975) (2004:2004:2004)) - (PORT d[4] (1767:1767:1767) (1818:1818:1818)) - (PORT d[5] (2208:2208:2208) (2318:2318:2318)) - (PORT d[6] (2159:2159:2159) (2202:2202:2202)) - (PORT d[7] (2280:2280:2280) (2283:2283:2283)) - (PORT d[8] (2504:2504:2504) (2584:2584:2584)) - (PORT d[9] (2330:2330:2330) (2362:2362:2362)) - (PORT d[10] (3529:3529:3529) (3646:3646:3646)) - (PORT d[11] (1688:1688:1688) (1708:1708:1708)) - (PORT d[12] (2198:2198:2198) (2247:2247:2247)) + (PORT d[0] (1300:1300:1300) (1280:1280:1280)) + (PORT clk (1639:1639:1639) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1802:1802:1802) (1849:1849:1849)) + (PORT d[1] (2798:2798:2798) (2853:2853:2853)) + (PORT d[2] (1619:1619:1619) (1651:1651:1651)) + (PORT d[3] (3350:3350:3350) (3374:3374:3374)) + (PORT d[4] (2431:2431:2431) (2518:2518:2518)) + (PORT d[5] (3783:3783:3783) (3829:3829:3829)) + (PORT d[6] (2127:2127:2127) (2130:2130:2130)) + (PORT d[7] (3433:3433:3433) (3423:3423:3423)) + (PORT d[8] (1763:1763:1763) (1812:1812:1812)) + (PORT d[9] (2281:2281:2281) (2318:2318:2318)) + (PORT d[10] (2441:2441:2441) (2454:2454:2454)) + (PORT d[11] (2602:2602:2602) (2694:2694:2694)) + (PORT d[12] (3964:3964:3964) (4053:4053:4053)) + (PORT clk (1636:1636:1636) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2866:2866:2866) (2844:2844:2844)) + (PORT clk (1636:1636:1636) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1665:1665:1665)) + (PORT d[0] (2893:2893:2893) (2895:2895:2895)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1595:1595:1595)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2011:2011:2011) (1967:1967:1967)) + (PORT clk (1606:1606:1606) (1602:1602:1602)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4071:4071:4071) (4020:4020:4020)) + (PORT d[1] (4139:4139:4139) (4080:4080:4080)) + (PORT d[2] (4082:4082:4082) (3994:3994:3994)) + (PORT d[3] (4065:4065:4065) (3979:3979:3979)) + (PORT d[4] (3935:3935:3935) (3906:3906:3906)) + (PORT d[5] (4049:4049:4049) (3964:3964:3964)) + (PORT d[6] (4086:4086:4086) (3950:3950:3950)) + (PORT d[7] (3900:3900:3900) (3808:3808:3808)) + (PORT d[8] (4163:4163:4163) (4045:4045:4045)) + (PORT d[9] (4267:4267:4267) (4165:4165:4165)) + (PORT d[10] (3964:3964:3964) (3868:3868:3868)) + (PORT d[11] (4075:4075:4075) (4005:4005:4005)) + (PORT d[12] (3957:3957:3957) (3823:3823:3823)) + (PORT clk (1603:1603:1603) (1599:1599:1599)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1602:1602:1602)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1603:1603:1603)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1603:1603:1603)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1603:1603:1603)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1603:1603:1603)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1596:1596:1596)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1588:1588:1588) (1664:1664:1664)) + (PORT d[1] (1291:1291:1291) (1296:1296:1296)) + (PORT d[2] (2073:2073:2073) (2156:2156:2156)) + (PORT d[3] (1584:1584:1584) (1584:1584:1584)) + (PORT d[4] (2259:2259:2259) (2314:2314:2314)) + (PORT d[5] (2603:2603:2603) (2597:2597:2597)) + (PORT d[6] (1831:1831:1831) (1849:1849:1849)) + (PORT d[7] (1574:1574:1574) (1575:1575:1575)) + (PORT d[8] (2039:2039:2039) (2088:2088:2088)) + (PORT d[9] (1600:1600:1600) (1585:1585:1585)) + (PORT d[10] (2330:2330:2330) (2321:2321:2321)) + (PORT d[11] (3731:3731:3731) (3871:3871:3871)) + (PORT d[12] (1275:1275:1275) (1270:1270:1270)) + (PORT clk (1637:1637:1637) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1666:1666:1666)) + (PORT d[0] (1897:1897:1897) (1955:1955:1955)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1604:1604:1604) (1632:1632:1632)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1118:1118:1118) (1133:1133:1133)) + (PORT datab (670:670:670) (701:701:701)) + (PORT datac (1269:1269:1269) (1260:1260:1260)) + (PORT datad (1534:1534:1534) (1520:1520:1520)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1118:1118:1118) (1115:1115:1115)) + (PORT datab (666:666:666) (695:695:695)) + (PORT datac (1743:1743:1743) (1727:1727:1727)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1209:1209:1209) (1215:1215:1215)) + (PORT clk (1638:1638:1638) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2126:2126:2126) (2221:2221:2221)) + (PORT d[1] (2088:2088:2088) (2097:2097:2097)) + (PORT d[2] (1711:1711:1711) (1725:1725:1725)) + (PORT d[3] (2328:2328:2328) (2339:2339:2339)) + (PORT d[4] (1906:1906:1906) (1917:1917:1917)) + (PORT d[5] (1445:1445:1445) (1474:1474:1474)) + (PORT d[6] (1622:1622:1622) (1612:1612:1612)) + (PORT d[7] (2191:2191:2191) (2238:2238:2238)) + (PORT d[8] (2297:2297:2297) (2401:2401:2401)) + (PORT d[9] (1150:1150:1150) (1173:1173:1173)) + (PORT d[10] (1528:1528:1528) (1520:1520:1520)) + (PORT d[11] (1089:1089:1089) (1091:1091:1091)) + (PORT d[12] (944:944:944) (985:985:985)) (PORT clk (1635:1635:1635) (1664:1664:1664)) ) ) @@ -44048,27 +48305,70 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) (DELAY (ABSOLUTE + (PORT d[0] (1412:1412:1412) (1389:1389:1389)) (PORT clk (1635:1635:1635) (1664:1664:1664)) - (PORT d[0] (2249:2249:2249) (2258:2258:2258)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (PORT d[0] (1847:1847:1847) (1802:1802:1802)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1636:1636:1636) (1665:1665:1665)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1602:1602:1602) (1630:1630:1630)) @@ -44082,7 +48382,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (873:873:873) (877:877:877)) @@ -44091,7 +48391,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) (DELAY (ABSOLUTE (PORT clk (874:874:874) (878:878:878)) @@ -44100,7 +48400,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (874:874:874) (878:878:878)) @@ -44110,7 +48410,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (874:874:874) (878:878:878)) @@ -44120,11 +48420,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1532:1532:1532) (1559:1559:1559)) - (PORT clk (1646:1646:1646) (1673:1673:1673)) + (PORT d[0] (1090:1090:1090) (1057:1057:1057)) + (PORT clk (1646:1646:1646) (1672:1672:1672)) ) ) (TIMINGCHECK @@ -44133,23 +48433,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2702:2702:2702) (2726:2726:2726)) - (PORT d[1] (2194:2194:2194) (2333:2333:2333)) - (PORT d[2] (2394:2394:2394) (2459:2459:2459)) - (PORT d[3] (1855:1855:1855) (1909:1909:1909)) - (PORT d[4] (2716:2716:2716) (2843:2843:2843)) - (PORT d[5] (2202:2202:2202) (2319:2319:2319)) - (PORT d[6] (1727:1727:1727) (1746:1746:1746)) - (PORT d[7] (1517:1517:1517) (1555:1555:1555)) - (PORT d[8] (2811:2811:2811) (2896:2896:2896)) - (PORT d[9] (1130:1130:1130) (1151:1151:1151)) - (PORT d[10] (1994:1994:1994) (2037:2037:2037)) - (PORT d[11] (3422:3422:3422) (3471:3471:3471)) - (PORT d[12] (1753:1753:1753) (1782:1782:1782)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) + (PORT d[0] (2677:2677:2677) (2786:2786:2786)) + (PORT d[1] (3046:3046:3046) (3122:3122:3122)) + (PORT d[2] (1816:1816:1816) (1814:1814:1814)) + (PORT d[3] (3668:3668:3668) (3717:3717:3717)) + (PORT d[4] (2679:2679:2679) (2768:2768:2768)) + (PORT d[5] (4106:4106:4106) (4171:4171:4171)) + (PORT d[6] (2058:2058:2058) (2054:2054:2054)) + (PORT d[7] (1597:1597:1597) (1606:1606:1606)) + (PORT d[8] (2907:2907:2907) (3000:3000:3000)) + (PORT d[9] (1706:1706:1706) (1738:1738:1738)) + (PORT d[10] (1900:1900:1900) (1898:1898:1898)) + (PORT d[11] (2895:2895:2895) (2998:2998:2998)) + (PORT d[12] (3973:3973:3973) (4063:4063:4063)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) ) ) (TIMINGCHECK @@ -44158,11 +48458,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2584:2584:2584) (2522:2522:2522)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) + (PORT d[0] (1499:1499:1499) (1433:1433:1433)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) ) ) (TIMINGCHECK @@ -44171,60 +48471,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (PORT d[0] (2819:2819:2819) (2825:2825:2825)) + (PORT clk (1646:1646:1646) (1672:1672:1672)) + (PORT d[0] (2295:2295:2295) (2246:2246:2246)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) + (PORT clk (1647:1647:1647) (1673:1673:1673)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) + (PORT clk (1647:1647:1647) (1673:1673:1673)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) + (PORT clk (1647:1647:1647) (1673:1673:1673)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) + (PORT clk (1647:1647:1647) (1673:1673:1673)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1605:1605:1605) (1603:1603:1603)) + (PORT clk (1610:1610:1610) (1636:1636:1636)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -44235,97 +48535,149 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (2024:2024:2024) (2022:2022:2022)) - (PORT clk (1613:1613:1613) (1610:1610:1610)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4286:4286:4286) (4176:4176:4176)) - (PORT d[1] (3889:3889:3889) (3754:3754:3754)) - (PORT d[2] (3922:3922:3922) (3831:3831:3831)) - (PORT d[3] (4387:4387:4387) (4236:4236:4236)) - (PORT d[4] (4059:4059:4059) (3930:3930:3930)) - (PORT d[5] (4137:4137:4137) (3982:3982:3982)) - (PORT d[6] (4314:4314:4314) (4255:4255:4255)) - (PORT d[7] (3900:3900:3900) (3727:3727:3727)) - (PORT d[8] (4378:4378:4378) (4223:4223:4223)) - (PORT d[9] (4245:4245:4245) (4309:4309:4309)) - (PORT d[10] (4110:4110:4110) (4007:4007:4007)) - (PORT d[11] (4188:4188:4188) (4097:4097:4097)) - (PORT d[12] (4162:4162:4162) (4084:4084:4084)) - (PORT clk (1610:1610:1610) (1607:1607:1607)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1613:1613:1613) (1610:1610:1610)) + (PORT clk (881:881:881) (883:883:883)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1614:1614:1614) (1611:1611:1611)) + (PORT clk (882:882:882) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1303:1303:1303) (1293:1293:1293)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2076:2076:2076) (2151:2151:2151)) + (PORT d[1] (1045:1045:1045) (1047:1047:1047)) + (PORT d[2] (2474:2474:2474) (2506:2506:2506)) + (PORT d[3] (4240:4240:4240) (4316:4316:4316)) + (PORT d[4] (895:895:895) (905:905:905)) + (PORT d[5] (1531:1531:1531) (1511:1511:1511)) + (PORT d[6] (1336:1336:1336) (1341:1341:1341)) + (PORT d[7] (1313:1313:1313) (1299:1299:1299)) + (PORT d[8] (2333:2333:2333) (2396:2396:2396)) + (PORT d[9] (1059:1059:1059) (1054:1054:1054)) + (PORT d[10] (1893:1893:1893) (1883:1883:1883)) + (PORT d[11] (3463:3463:3463) (3596:3596:3596)) + (PORT d[12] (2280:2280:2280) (2280:2280:2280)) + (PORT clk (1637:1637:1637) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2590:2590:2590) (2563:2563:2563)) + (PORT clk (1637:1637:1637) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (PORT d[0] (1726:1726:1726) (1666:1666:1666)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1614:1614:1614) (1611:1611:1611)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1614:1614:1614) (1611:1611:1611)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1614:1614:1614) (1611:1611:1611)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1606:1606:1606) (1604:1604:1604)) + (PORT clk (1604:1604:1604) (1632:1632:1632)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -44335,46 +48687,221 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~0) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) (DELAY (ABSOLUTE - (PORT dataa (1324:1324:1324) (1337:1337:1337)) - (PORT datab (912:912:912) (946:946:946)) - (PORT datac (1320:1320:1320) (1311:1311:1311)) - (PORT datad (1291:1291:1291) (1297:1297:1297)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT clk (875:875:875) (879:879:879)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~1) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1403:1403:1403) (1437:1437:1437)) - (PORT datab (910:910:910) (944:944:944)) - (PORT datac (1361:1361:1361) (1365:1365:1365)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (PORT dataa (807:807:807) (788:788:788)) + (PORT datab (1158:1158:1158) (1192:1192:1192)) + (PORT datac (1341:1341:1341) (1368:1368:1368)) + (PORT datad (1314:1314:1314) (1327:1327:1327)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~112) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (1368:1368:1368) (1422:1422:1422)) - (PORT datab (1129:1129:1129) (1138:1138:1138)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (159:159:159) (179:179:179)) + (PORT d[0] (1351:1351:1351) (1333:1333:1333)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1561:1561:1561) (1629:1629:1629)) + (PORT d[1] (2056:2056:2056) (2043:2043:2043)) + (PORT d[2] (2092:2092:2092) (2176:2176:2176)) + (PORT d[3] (1603:1603:1603) (1594:1594:1594)) + (PORT d[4] (2248:2248:2248) (2292:2292:2292)) + (PORT d[5] (2623:2623:2623) (2618:2618:2618)) + (PORT d[6] (1878:1878:1878) (1895:1895:1895)) + (PORT d[7] (1603:1603:1603) (1608:1608:1608)) + (PORT d[8] (2013:2013:2013) (2059:2059:2059)) + (PORT d[9] (1837:1837:1837) (1816:1816:1816)) + (PORT d[10] (2045:2045:2045) (2041:2041:2041)) + (PORT d[11] (3995:3995:3995) (4131:4131:4131)) + (PORT d[12] (2040:2040:2040) (2037:2037:2037)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1758:1758:1758) (1762:1762:1762)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT d[0] (1720:1720:1720) (1667:1667:1667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1634:1634:1634)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (881:881:881)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1115:1115:1115) (1139:1139:1139)) + (PORT datab (1575:1575:1575) (1612:1612:1612)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (1573:1573:1573) (1589:1589:1589)) (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -44384,15 +48911,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~94) + (INSTANCE D\[5\]\~112) (DELAY (ABSOLUTE - (PORT dataa (1282:1282:1282) (1254:1254:1254)) - (PORT datab (819:819:819) (858:858:858)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (1259:1259:1259) (1238:1238:1238)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (1609:1609:1609) (1608:1608:1608)) + (PORT datab (620:620:620) (613:613:613)) + (PORT datac (572:572:572) (570:570:570)) + (PORT datad (303:303:303) (304:304:304)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -44400,35 +48927,39 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~102) + (INSTANCE D\[5\]\~113) (DELAY (ABSOLUTE - (PORT datac (173:173:173) (203:203:203)) - (PORT datad (735:735:735) (718:718:718)) + (PORT dataa (2306:2306:2306) (2269:2269:2269)) + (PORT datab (643:643:643) (643:643:643)) + (PORT datac (176:176:176) (207:207:207)) + (PORT datad (1091:1091:1091) (1115:1115:1115)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (613:613:613)) + (PORT datab (1071:1071:1071) (1059:1059:1059)) + (PORT datac (198:198:198) (235:235:235)) + (PORT datad (1433:1433:1433) (1401:1401:1401)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (904:904:904)) - (PORT datab (208:208:208) (245:245:245)) - (PORT datac (211:211:211) (256:256:256)) - (PORT datad (796:796:796) (802:802:802)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[7\]) + (INSTANCE z80_\|data_pins_\|dout\[5\]) (DELAY (ABSOLUTE (PORT clk (1347:1347:1347) (1358:1358:1358)) @@ -44444,2113 +48975,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~5) + (INSTANCE z80_\|bus_control_\|db\[5\]\~14) (DELAY (ABSOLUTE - (PORT datab (1079:1079:1079) (1089:1089:1089)) - (PORT datac (877:877:877) (911:911:911)) - (PORT datad (335:335:335) (347:347:347)) + (PORT datab (400:400:400) (437:437:437)) + (PORT datac (194:194:194) (238:238:238)) + (PORT datad (202:202:202) (239:239:239)) (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~7) + (INSTANCE z80_\|bus_control_\|db\[5\]\~15) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (317:317:317)) - (PORT datab (659:659:659) (657:657:657)) - (PORT datac (811:811:811) (793:793:793)) - (PORT datad (158:158:158) (178:178:178)) + (PORT dataa (813:813:813) (785:785:785)) + (PORT datab (550:550:550) (555:555:555)) + (PORT datac (496:496:496) (480:480:480)) + (PORT datad (1029:1029:1029) (998:998:998)) (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[7\]) + (INSTANCE z80_\|ir_\|opcode\[5\]) (DELAY (ABSOLUTE (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (492:492:492) (524:524:524)) - (PORT clrn (1398:1398:1398) (1368:1368:1368)) - (PORT ena (1378:1378:1378) (1346:1346:1346)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1396:1396:1396) (1368:1368:1368)) + (PORT ena (1804:1804:1804) (1767:1767:1767)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~0) - (DELAY - (ABSOLUTE - (PORT dataa (662:662:662) (730:730:730)) - (PORT datab (1151:1151:1151) (1204:1204:1204)) - (PORT datac (893:893:893) (932:932:932)) - (PORT datad (1224:1224:1224) (1307:1307:1307)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (668:668:668)) - (PORT datab (914:914:914) (979:979:979)) - (PORT datac (1059:1059:1059) (1078:1078:1078)) - (PORT datad (1084:1084:1084) (1127:1127:1127)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (694:694:694)) - (PORT datab (350:350:350) (370:370:370)) - (PORT datac (1024:1024:1024) (1011:1011:1011)) - (PORT datad (1602:1602:1602) (1608:1608:1608)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (931:931:931)) - (PORT datab (1056:1056:1056) (1041:1041:1041)) - (PORT datac (1025:1025:1025) (1039:1039:1039)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1599:1599:1599) (1605:1605:1605)) - (PORT datab (978:978:978) (1056:1056:1056)) - (PORT datac (1110:1110:1110) (1156:1156:1156)) - (PORT datad (1056:1056:1056) (1063:1063:1063)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1596:1596:1596) (1601:1601:1601)) - (PORT datab (346:346:346) (372:372:372)) - (PORT datac (1391:1391:1391) (1462:1462:1462)) - (PORT datad (1019:1019:1019) (1003:1003:1003)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (253:253:253)) - (PORT datab (953:953:953) (995:995:995)) - (PORT datac (1024:1024:1024) (1012:1012:1012)) - (PORT datad (997:997:997) (1023:1023:1023)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (819:819:819) (820:820:820)) - (PORT datab (1391:1391:1391) (1379:1379:1379)) - (PORT datac (770:770:770) (763:763:763)) - (PORT datad (803:803:803) (799:799:799)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~50) - (DELAY - (ABSOLUTE - (PORT datac (987:987:987) (1048:1048:1048)) - (PORT datad (950:950:950) (998:998:998)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (386:386:386)) - (PORT datab (889:889:889) (937:937:937)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (205:205:205) (254:254:254)) - (PORT datab (711:711:711) (776:776:776)) - (PORT datac (1249:1249:1249) (1305:1305:1305)) - (PORT datad (1421:1421:1421) (1458:1458:1458)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (321:321:321) (341:341:341)) - (PORT datab (202:202:202) (235:235:235)) - (PORT datad (681:681:681) (739:739:739)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (2135:2135:2135) (2209:2209:2209)) - (PORT datab (220:220:220) (287:287:287)) - (PORT datac (536:536:536) (557:557:557)) - (PORT datad (1219:1219:1219) (1194:1194:1194)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~57) - (DELAY - (ABSOLUTE - (PORT datab (887:887:887) (941:941:941)) - (PORT datad (678:678:678) (747:747:747)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (222:222:222)) - (PORT datab (574:574:574) (596:596:596)) - (PORT datad (886:886:886) (928:928:928)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (435:435:435) (501:501:501)) - (PORT datab (607:607:607) (656:656:656)) - (PORT datac (560:560:560) (595:595:595)) - (PORT datad (668:668:668) (700:700:700)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~131) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (475:475:475)) - (PORT datab (324:324:324) (338:338:338)) - (PORT datad (237:237:237) (302:302:302)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (815:815:815)) - (PORT datab (1010:1010:1010) (988:988:988)) - (PORT datad (570:570:570) (568:568:568)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1071:1071:1071) (1090:1090:1090)) - (PORT datab (219:219:219) (286:286:286)) - (PORT datac (529:529:529) (551:551:551)) - (PORT datad (515:515:515) (511:511:511)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~53) - (DELAY - (ABSOLUTE - (PORT datac (987:987:987) (1045:1045:1045)) - (PORT datad (950:950:950) (994:994:994)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (259:259:259)) - (PORT datab (363:363:363) (370:370:370)) - (PORT datac (843:843:843) (874:874:874)) - (PORT datad (303:303:303) (310:310:310)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~56) - (DELAY - (ABSOLUTE - (PORT datab (890:890:890) (939:939:939)) - (PORT datad (315:315:315) (314:314:314)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (388:388:388)) - (PORT datab (890:890:890) (939:939:939)) - (PORT datad (178:178:178) (199:199:199)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (294:294:294)) - (PORT datab (221:221:221) (290:290:290)) - (PORT datac (527:527:527) (527:527:527)) - (PORT datad (522:522:522) (510:510:510)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (918:918:918)) - (PORT datab (728:728:728) (803:803:803)) - (PORT datac (828:828:828) (877:877:877)) - (PORT datad (704:704:704) (778:778:778)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (354:354:354)) - (PORT datab (677:677:677) (738:738:738)) - (PORT datad (543:543:543) (537:537:537)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (195:195:195) (238:238:238)) - (PORT datab (184:184:184) (218:218:218)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) - (DELAY - (ABSOLUTE - (PORT datac (220:220:220) (290:290:290)) - (PORT datad (769:769:769) (789:789:789)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (681:681:681)) - (PORT datab (326:326:326) (337:337:337)) - (PORT datac (599:599:599) (636:636:636)) - (PORT datad (588:588:588) (618:618:618)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (233:233:233)) - (PORT datab (441:441:441) (481:481:481)) - (PORT datac (327:327:327) (340:340:340)) - (PORT datad (176:176:176) (209:209:209)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (724:724:724)) - (PORT datab (447:447:447) (513:513:513)) - (PORT datac (534:534:534) (537:537:537)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (685:685:685) (748:748:748)) - (PORT datab (714:714:714) (779:779:779)) - (PORT datad (884:884:884) (922:922:922)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (320:320:320) (331:331:331)) - (PORT datad (579:579:579) (592:592:592)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1543:1543:1543) (1518:1518:1518)) - (PORT datab (574:574:574) (597:597:597)) - (PORT datac (982:982:982) (1004:1004:1004)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (590:590:590) (591:591:591)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (546:546:546) (535:535:535)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~104) - (DELAY - (ABSOLUTE - (PORT datab (1135:1135:1135) (1151:1151:1151)) - (PORT datac (605:605:605) (649:649:649)) - (PORT datad (1287:1287:1287) (1270:1270:1270)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (878:878:878) (882:882:882)) - (PORT clk (1634:1634:1634) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1228:1228:1228) (1255:1255:1255)) - (PORT d[1] (1824:1824:1824) (1948:1948:1948)) - (PORT d[2] (2820:2820:2820) (2872:2872:2872)) - (PORT d[3] (2632:2632:2632) (2723:2723:2723)) - (PORT d[4] (2364:2364:2364) (2459:2459:2459)) - (PORT d[5] (2640:2640:2640) (2736:2736:2736)) - (PORT d[6] (1780:1780:1780) (1841:1841:1841)) - (PORT d[7] (2392:2392:2392) (2429:2429:2429)) - (PORT d[8] (3173:3173:3173) (3316:3316:3316)) - (PORT d[9] (1484:1484:1484) (1527:1527:1527)) - (PORT d[10] (4703:4703:4703) (4804:4804:4804)) - (PORT d[11] (1778:1778:1778) (1847:1847:1847)) - (PORT d[12] (1760:1760:1760) (1812:1812:1812)) - (PORT clk (1631:1631:1631) (1661:1661:1661)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1120:1120:1120) (1091:1091:1091)) - (PORT clk (1631:1631:1631) (1661:1661:1661)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1634:1634:1634) (1663:1663:1663)) - (PORT d[0] (2292:2292:2292) (2214:2214:2214)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1664:1664:1664)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1664:1664:1664)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1664:1664:1664)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1664:1664:1664)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1598:1598:1598) (1627:1627:1627)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (869:869:869) (874:874:874)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (875:875:875)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (875:875:875)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (875:875:875)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (656:656:656) (645:645:645)) - (PORT clk (1644:1644:1644) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1171:1171:1171) (1169:1169:1169)) - (PORT d[1] (1948:1948:1948) (2094:2094:2094)) - (PORT d[2] (1153:1153:1153) (1155:1155:1155)) - (PORT d[3] (1204:1204:1204) (1226:1226:1226)) - (PORT d[4] (2425:2425:2425) (2533:2533:2533)) - (PORT d[5] (3217:3217:3217) (3322:3322:3322)) - (PORT d[6] (1222:1222:1222) (1272:1272:1272)) - (PORT d[7] (2666:2666:2666) (2711:2711:2711)) - (PORT d[8] (913:913:913) (921:921:921)) - (PORT d[9] (1196:1196:1196) (1239:1239:1239)) - (PORT d[10] (1257:1257:1257) (1305:1305:1305)) - (PORT d[11] (2298:2298:2298) (2368:2368:2368)) - (PORT d[12] (1485:1485:1485) (1525:1525:1525)) - (PORT clk (1641:1641:1641) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (895:895:895) (859:859:859)) - (PORT clk (1641:1641:1641) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1670:1670:1670)) - (PORT d[0] (1342:1342:1342) (1309:1309:1309)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1608:1608:1608) (1634:1634:1634)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (881:881:881)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (877:877:877) (875:875:875)) - (PORT clk (1638:1638:1638) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1236:1236:1236) (1266:1266:1266)) - (PORT d[1] (2925:2925:2925) (3075:3075:3075)) - (PORT d[2] (3248:3248:3248) (3283:3283:3283)) - (PORT d[3] (2633:2633:2633) (2727:2727:2727)) - (PORT d[4] (2375:2375:2375) (2474:2474:2474)) - (PORT d[5] (2666:2666:2666) (2765:2765:2765)) - (PORT d[6] (1549:1549:1549) (1579:1579:1579)) - (PORT d[7] (1389:1389:1389) (1407:1407:1407)) - (PORT d[8] (3197:3197:3197) (3346:3346:3346)) - (PORT d[9] (2980:2980:2980) (3056:3056:3056)) - (PORT d[10] (4704:4704:4704) (4809:4809:4809)) - (PORT d[11] (1809:1809:1809) (1884:1884:1884)) - (PORT d[12] (1752:1752:1752) (1799:1799:1799)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1579:1579:1579) (1512:1512:1512)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1665:1665:1665)) - (PORT d[0] (1851:1851:1851) (1816:1816:1816)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1629:1629:1629)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1083:1083:1083) (1033:1033:1033)) - (PORT clk (1636:1636:1636) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3407:3407:3407) (3481:3481:3481)) - (PORT d[1] (1566:1566:1566) (1666:1666:1666)) - (PORT d[2] (1830:1830:1830) (1838:1838:1838)) - (PORT d[3] (1999:1999:1999) (2026:2026:2026)) - (PORT d[4] (2024:2024:2024) (2084:2084:2084)) - (PORT d[5] (1272:1272:1272) (1335:1335:1335)) - (PORT d[6] (1389:1389:1389) (1420:1420:1420)) - (PORT d[7] (1608:1608:1608) (1645:1645:1645)) - (PORT d[8] (3346:3346:3346) (3464:3464:3464)) - (PORT d[9] (2907:2907:2907) (2973:2973:2973)) - (PORT d[10] (2940:2940:2940) (3016:3016:3016)) - (PORT d[11] (1927:1927:1927) (1965:1965:1965)) - (PORT d[12] (1320:1320:1320) (1344:1344:1344)) - (PORT clk (1633:1633:1633) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1539:1539:1539) (1481:1481:1481)) - (PORT clk (1633:1633:1633) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1662:1662:1662)) - (PORT d[0] (2458:2458:2458) (2384:2384:2384)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1600:1600:1600) (1626:1626:1626)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (873:873:873)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (936:936:936)) - (PORT datab (1093:1093:1093) (1105:1105:1105)) - (PORT datac (774:774:774) (756:756:756)) - (PORT datad (976:976:976) (927:927:927)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1086:1086:1086) (1054:1054:1054)) - (PORT datab (1477:1477:1477) (1526:1526:1526)) - (PORT datac (1073:1073:1073) (1031:1031:1031)) - (PORT datad (287:287:287) (294:294:294)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2822:2822:2822) (2879:2879:2879)) - (PORT d[1] (2681:2681:2681) (2799:2799:2799)) - (PORT d[2] (1535:1535:1535) (1571:1571:1571)) - (PORT d[3] (1402:1402:1402) (1421:1421:1421)) - (PORT d[4] (1732:1732:1732) (1763:1763:1763)) - (PORT d[5] (1242:1242:1242) (1306:1306:1306)) - (PORT d[6] (1064:1064:1064) (1065:1065:1065)) - (PORT d[7] (1371:1371:1371) (1406:1406:1406)) - (PORT d[8] (2287:2287:2287) (2382:2382:2382)) - (PORT d[9] (3533:3533:3533) (3626:3626:3626)) - (PORT d[10] (2388:2388:2388) (2442:2442:2442)) - (PORT d[11] (1677:1677:1677) (1703:1703:1703)) - (PORT d[12] (1891:1891:1891) (1909:1909:1909)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) - (PORT d[0] (1181:1181:1181) (1144:1144:1144)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1664:1664:1664)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1629:1629:1629)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1503:1503:1503) (1520:1520:1520)) - (PORT clk (1652:1652:1652) (1679:1679:1679)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2412:2412:2412) (2426:2426:2426)) - (PORT d[1] (1923:1923:1923) (2051:2051:2051)) - (PORT d[2] (2374:2374:2374) (2419:2419:2419)) - (PORT d[3] (2086:2086:2086) (2133:2133:2133)) - (PORT d[4] (2745:2745:2745) (2877:2877:2877)) - (PORT d[5] (1944:1944:1944) (2061:2061:2061)) - (PORT d[6] (1451:1451:1451) (1492:1492:1492)) - (PORT d[7] (2608:2608:2608) (2591:2591:2591)) - (PORT d[8] (2597:2597:2597) (2711:2711:2711)) - (PORT d[9] (1918:1918:1918) (1943:1943:1943)) - (PORT d[10] (1715:1715:1715) (1750:1750:1750)) - (PORT d[11] (3415:3415:3415) (3446:3446:3446)) - (PORT d[12] (1742:1742:1742) (1761:1761:1761)) - (PORT clk (1649:1649:1649) (1677:1677:1677)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2934:2934:2934) (2838:2838:2838)) - (PORT clk (1649:1649:1649) (1677:1677:1677)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1652:1652:1652) (1679:1679:1679)) - (PORT d[0] (2618:2618:2618) (2605:2605:2605)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1653:1653:1653) (1680:1680:1680)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1653:1653:1653) (1680:1680:1680)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1653:1653:1653) (1680:1680:1680)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1653:1653:1653) (1680:1680:1680)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1609:1609:1609)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2009:2009:2009) (2009:2009:2009)) - (PORT clk (1619:1619:1619) (1616:1616:1616)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4228:4228:4228) (4049:4049:4049)) - (PORT d[1] (4048:4048:4048) (3926:3926:3926)) - (PORT d[2] (4235:4235:4235) (4146:4146:4146)) - (PORT d[3] (4160:4160:4160) (4050:4050:4050)) - (PORT d[4] (4027:4027:4027) (3872:3872:3872)) - (PORT d[5] (4063:4063:4063) (3983:3983:3983)) - (PORT d[6] (4304:4304:4304) (4248:4248:4248)) - (PORT d[7] (3871:3871:3871) (3708:3708:3708)) - (PORT d[8] (4136:4136:4136) (4016:4016:4016)) - (PORT d[9] (4278:4278:4278) (4341:4341:4341)) - (PORT d[10] (4175:4175:4175) (4089:4089:4089)) - (PORT d[11] (4347:4347:4347) (4198:4198:4198)) - (PORT d[12] (4172:4172:4172) (4111:4111:4111)) - (PORT clk (1616:1616:1616) (1613:1613:1613)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1619:1619:1619) (1616:1616:1616)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1620:1620:1620) (1617:1617:1617)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1620:1620:1620) (1617:1617:1617)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1620:1620:1620) (1617:1617:1617)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1620:1620:1620) (1617:1617:1617)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1253:1253:1253) (1237:1237:1237)) - (PORT datab (250:250:250) (328:328:328)) - (PORT datac (1247:1247:1247) (1214:1214:1214)) - (PORT datad (1361:1361:1361) (1371:1371:1371)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1461:1461:1461) (1472:1472:1472)) - (PORT clk (1656:1656:1656) (1683:1683:1683)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2158:2158:2158) (2147:2147:2147)) - (PORT d[1] (1907:1907:1907) (2023:2023:2023)) - (PORT d[2] (2137:2137:2137) (2217:2217:2217)) - (PORT d[3] (2113:2113:2113) (2196:2196:2196)) - (PORT d[4] (2735:2735:2735) (2857:2857:2857)) - (PORT d[5] (2220:2220:2220) (2324:2324:2324)) - (PORT d[6] (1719:1719:1719) (1765:1765:1765)) - (PORT d[7] (2330:2330:2330) (2325:2325:2325)) - (PORT d[8] (2908:2908:2908) (3035:3035:3035)) - (PORT d[9] (1649:1649:1649) (1670:1670:1670)) - (PORT d[10] (1675:1675:1675) (1693:1693:1693)) - (PORT d[11] (2723:2723:2723) (2755:2755:2755)) - (PORT d[12] (1741:1741:1741) (1769:1769:1769)) - (PORT clk (1653:1653:1653) (1681:1681:1681)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2037:2037:2037) (1970:1970:1970)) - (PORT clk (1653:1653:1653) (1681:1681:1681)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1656:1656:1656) (1683:1683:1683)) - (PORT d[0] (2843:2843:2843) (2837:2837:2837)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1657:1657:1657) (1684:1684:1684)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1657:1657:1657) (1684:1684:1684)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1657:1657:1657) (1684:1684:1684)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1657:1657:1657) (1684:1684:1684)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1615:1615:1615) (1613:1613:1613)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2299:2299:2299) (2304:2304:2304)) - (PORT clk (1623:1623:1623) (1620:1620:1620)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4203:4203:4203) (4062:4062:4062)) - (PORT d[1] (3847:3847:3847) (3718:3718:3718)) - (PORT d[2] (4210:4210:4210) (4080:4080:4080)) - (PORT d[3] (4242:4242:4242) (4139:4139:4139)) - (PORT d[4] (4247:4247:4247) (4105:4105:4105)) - (PORT d[5] (4340:4340:4340) (4259:4259:4259)) - (PORT d[6] (4317:4317:4317) (4290:4290:4290)) - (PORT d[7] (3916:3916:3916) (3762:3762:3762)) - (PORT d[8] (4362:4362:4362) (4253:4253:4253)) - (PORT d[9] (4208:4208:4208) (4238:4238:4238)) - (PORT d[10] (4238:4238:4238) (4121:4121:4121)) - (PORT d[11] (4183:4183:4183) (4093:4093:4093)) - (PORT d[12] (4275:4275:4275) (4202:4202:4202)) - (PORT clk (1620:1620:1620) (1617:1617:1617)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1623:1623:1623) (1620:1620:1620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1624:1624:1624) (1621:1621:1621)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1624:1624:1624) (1621:1621:1621)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1624:1624:1624) (1621:1621:1621)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1624:1624:1624) (1621:1621:1621)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1616:1616:1616) (1614:1614:1614)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (911:911:911) (929:929:929)) - (PORT d[1] (916:916:916) (933:933:933)) - (PORT d[2] (1136:1136:1136) (1138:1138:1138)) - (PORT d[3] (1217:1217:1217) (1244:1244:1244)) - (PORT d[4] (2415:2415:2415) (2527:2527:2527)) - (PORT d[5] (2765:2765:2765) (2905:2905:2905)) - (PORT d[6] (908:908:908) (915:915:915)) - (PORT d[7] (1185:1185:1185) (1202:1202:1202)) - (PORT d[8] (958:958:958) (970:970:970)) - (PORT d[9] (901:901:901) (908:908:908)) - (PORT d[10] (1223:1223:1223) (1237:1237:1237)) - (PORT d[11] (2375:2375:2375) (2471:2471:2471)) - (PORT d[12] (1196:1196:1196) (1217:1217:1217)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (PORT d[0] (515:515:515) (535:535:535)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1636:1636:1636)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (883:883:883)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (1192:1192:1192) (1154:1154:1154)) - (PORT datab (816:816:816) (796:796:796)) - (PORT datac (802:802:802) (785:785:785)) - (PORT datad (166:166:166) (192:192:192)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (230:230:230)) - (PORT datab (253:253:253) (331:331:331)) - (PORT datac (1507:1507:1507) (1487:1487:1487)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~105) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (855:855:855) (894:894:894)) - (PORT datac (1100:1100:1100) (1115:1115:1115)) - (PORT datad (531:531:531) (535:535:535)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (368:368:368)) - (PORT datab (210:210:210) (250:250:250)) - (PORT datac (163:163:163) (196:196:196)) - (PORT datad (168:168:168) (192:192:192)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (443:443:443)) - (PORT datab (210:210:210) (251:251:251)) - (PORT datac (1059:1059:1059) (1047:1047:1047)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (902:902:902) (934:934:934)) - (PORT datab (593:593:593) (598:598:598)) - (PORT datac (552:552:552) (544:544:544)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1141:1141:1141) (1105:1105:1105)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) @@ -46558,75 +49023,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~12) + (INSTANCE z80_\|execute_\|ctl_mRead\~11) (DELAY (ABSOLUTE - (PORT datab (852:852:852) (848:848:848)) - (PORT datac (871:871:871) (900:900:900)) - (PORT datad (199:199:199) (229:229:229)) + (PORT dataa (1946:1946:1946) (2019:2019:2019)) + (PORT datab (1854:1854:1854) (1879:1879:1879)) + (PORT datac (1265:1265:1265) (1337:1337:1337)) + (PORT datad (815:815:815) (826:826:826)) + (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (449:449:449)) - (PORT datab (215:215:215) (253:253:253)) - (PORT datac (203:203:203) (251:251:251)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1395:1395:1395) (1367:1367:1367)) - (PORT ena (1130:1130:1130) (1103:1103:1103)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~1) - (DELAY - (ABSOLUTE - (PORT datac (1336:1336:1336) (1363:1363:1363)) - (PORT datad (2097:2097:2097) (2151:2151:2151)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (871:871:871)) - (PORT datab (866:866:866) (898:898:898)) - (PORT datac (1486:1486:1486) (1580:1580:1580)) - (PORT datad (1135:1135:1135) (1165:1165:1165)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -46634,63 +49039,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~2) + (INSTANCE z80_\|execute_\|setM1\~46) (DELAY (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (198:198:198) (231:231:231)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~3) - (DELAY - (ABSOLUTE - (PORT dataa (781:781:781) (779:779:779)) - (PORT datab (1913:1913:1913) (1971:1971:1971)) - (PORT datac (1168:1168:1168) (1229:1229:1229)) - (PORT datad (1001:1001:1001) (989:989:989)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1413:1413:1413) (1379:1379:1379)) - (PORT ena (1556:1556:1556) (1512:1512:1512)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) - (DELAY - (ABSOLUTE - (PORT dataa (1132:1132:1132) (1162:1162:1162)) - (PORT datab (1910:1910:1910) (1969:1969:1969)) - (PORT datac (1180:1180:1180) (1261:1261:1261)) - (PORT datad (1734:1734:1734) (1725:1725:1725)) + (PORT dataa (1123:1123:1123) (1123:1123:1123)) + (PORT datab (614:614:614) (627:627:627)) + (PORT datac (1304:1304:1304) (1322:1322:1322)) + (PORT datad (306:306:306) (317:317:317)) (IOPATH dataa combout (265:265:265) (273:273:273)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -46699,29 +49054,183 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~40) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1374:1374:1374)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + (PORT datac (948:948:948) (983:983:983)) + (PORT datad (551:551:551) (546:546:546)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) + (INSTANCE z80_\|execute_\|nextM\~5) (DELAY (ABSOLUTE - (PORT datab (230:230:230) (301:301:301)) - (PORT datad (207:207:207) (267:267:267)) + (PORT dataa (200:200:200) (237:237:237)) + (PORT datab (1722:1722:1722) (1752:1752:1752)) + (PORT datac (176:176:176) (208:208:208)) + (PORT datad (1001:1001:1001) (998:998:998)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1116:1116:1116) (1105:1105:1105)) + (PORT datab (208:208:208) (245:245:245)) + (PORT datac (558:558:558) (584:584:584)) + (PORT datad (549:549:549) (561:561:561)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1181:1181:1181) (1206:1206:1206)) + (PORT datab (701:701:701) (734:734:734)) + (PORT datac (1796:1796:1796) (1749:1749:1749)) + (PORT datad (770:770:770) (751:751:751)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~9) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (610:610:610)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (1352:1352:1352) (1377:1377:1377)) + (PORT datad (585:585:585) (617:617:617)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1561:1561:1561) (1545:1545:1545)) + (PORT datab (858:858:858) (838:838:838)) + (PORT datac (1305:1305:1305) (1294:1294:1294)) + (PORT datad (803:803:803) (785:785:785)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~8) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (629:629:629)) + (PORT datab (1224:1224:1224) (1230:1230:1230)) + (PORT datac (192:192:192) (223:223:223)) + (PORT datad (1575:1575:1575) (1548:1548:1548)) + (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~12) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (241:241:241)) + (PORT datab (622:622:622) (627:627:627)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~15) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (791:791:791)) + (PORT datab (2167:2167:2167) (2207:2207:2207)) + (PORT datac (1357:1357:1357) (1416:1416:1416)) + (PORT datad (957:957:957) (987:987:987)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~13) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (835:835:835)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~14) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (223:223:223)) + (PORT datab (552:552:552) (536:536:536)) + (PORT datac (549:549:549) (572:572:572)) + (PORT datad (1294:1294:1294) (1274:1274:1274)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|ena_M) + (DELAY + (ABSOLUTE + (PORT datac (615:615:615) (658:658:658)) + (PORT datad (816:816:816) (835:835:835)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -46731,10 +49240,10 @@ (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1383:1383:1383)) + (PORT clk (1346:1346:1346) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1379:1379:1379)) - (PORT ena (1790:1790:1790) (1839:1839:1839)) + (PORT clrn (1403:1403:1403) (1369:1369:1369)) + (PORT ena (1133:1133:1133) (1118:1118:1118)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -46749,9 +49258,9 @@ (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) (DELAY (ABSOLUTE - (PORT dataa (242:242:242) (314:314:314)) - (PORT datac (1030:1030:1030) (1031:1031:1031)) - (PORT datad (1041:1041:1041) (1032:1032:1032)) + (PORT dataa (644:644:644) (683:683:683)) + (PORT datac (620:620:620) (655:655:655)) + (PORT datad (818:818:818) (832:832:832)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -46763,10 +49272,10 @@ (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1383:1383:1383)) + (PORT clk (1346:1346:1346) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1379:1379:1379)) - (PORT ena (1790:1790:1790) (1839:1839:1839)) + (PORT clrn (1403:1403:1403) (1369:1369:1369)) + (PORT ena (1133:1133:1133) (1118:1118:1118)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -46778,40 +49287,692 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|x3) + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) (DELAY (ABSOLUTE - (PORT dataa (2203:2203:2203) (2261:2261:2261)) - (PORT datac (217:217:217) (284:284:284)) - (PORT datad (1256:1256:1256) (1355:1355:1355)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (242:242:242) (315:315:315)) + (PORT datac (622:622:622) (656:656:656)) + (PORT datad (819:819:819) (832:832:832)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) + (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) (DELAY (ABSOLUTE - (PORT clk (1340:1340:1340) (1357:1357:1357)) + (PORT clk (1346:1346:1346) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1667:1667:1667) (1646:1646:1646)) + (PORT clrn (1403:1403:1403) (1369:1369:1369)) + (PORT ena (1133:1133:1133) (1118:1118:1118)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT inclk[0] (1453:1453:1453) (1482:1482:1482)) + (PORT dataa (243:243:243) (317:317:317)) + (PORT datac (617:617:617) (658:658:658)) + (PORT datad (826:826:826) (837:837:837)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1366:1366:1366)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1403:1403:1403) (1369:1369:1369)) + (PORT ena (1133:1133:1133) (1118:1118:1118)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~9) + (DELAY + (ABSOLUTE + (PORT datac (640:640:640) (704:704:704)) + (PORT datad (2140:2140:2140) (2196:2196:2196)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1109:1109:1109) (1149:1149:1149)) + (PORT datab (1388:1388:1388) (1423:1423:1423)) + (PORT datac (1482:1482:1482) (1468:1468:1468)) + (PORT datad (880:880:880) (867:867:867)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~54) + (DELAY + (ABSOLUTE + (PORT dataa (1046:1046:1046) (1035:1035:1035)) + (PORT datab (607:607:607) (615:615:615)) + (PORT datac (1073:1073:1073) (1109:1109:1109)) + (PORT datad (829:829:829) (871:871:871)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~25) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (627:627:627)) + (PORT datab (1219:1219:1219) (1224:1224:1224)) + (PORT datac (575:575:575) (567:567:567)) + (PORT datad (799:799:799) (783:783:783)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1117:1117:1117) (1120:1120:1120)) + (PORT datab (902:902:902) (908:908:908)) + (PORT datac (225:225:225) (280:280:280)) + (PORT datad (1058:1058:1058) (1058:1058:1058)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1107:1107:1107) (1106:1106:1106)) + (PORT datab (564:564:564) (571:571:571)) + (PORT datac (804:804:804) (787:787:787)) + (PORT datad (743:743:743) (783:783:783)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~22) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (885:885:885)) + (PORT datab (1358:1358:1358) (1351:1351:1351)) + (PORT datac (2642:2642:2642) (2660:2660:2660)) + (PORT datad (209:209:209) (272:272:272)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~55) + (DELAY + (ABSOLUTE + (PORT dataa (1308:1308:1308) (1398:1398:1398)) + (PORT datab (1002:1002:1002) (981:981:981)) + (PORT datac (1145:1145:1145) (1184:1184:1184)) + (PORT datad (1897:1897:1897) (1971:1971:1971)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1038:1038:1038) (1015:1015:1015)) + (PORT datab (358:358:358) (369:369:369)) + (PORT datac (757:757:757) (813:813:813)) + (PORT datad (1534:1534:1534) (1544:1544:1544)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~24) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (222:222:222)) + (PORT datab (855:855:855) (887:887:887)) + (PORT datac (794:794:794) (792:792:792)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~28) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (506:506:506)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (563:563:563) (573:573:573)) + (PORT datad (815:815:815) (809:809:809)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~11) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1056:1056:1056)) + (PORT datab (1807:1807:1807) (1785:1785:1785)) + (PORT datac (861:861:861) (897:897:897)) + (PORT datad (1109:1109:1109) (1129:1129:1129)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1592:1592:1592) (1592:1592:1592)) + (PORT datab (1898:1898:1898) (1829:1829:1829)) + (PORT datac (1502:1502:1502) (1474:1474:1474)) + (PORT datad (1478:1478:1478) (1429:1429:1429)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~29) + (DELAY + (ABSOLUTE + (PORT dataa (774:774:774) (799:799:799)) + (PORT datab (766:766:766) (814:814:814)) + (PORT datac (807:807:807) (845:845:845)) + (PORT datad (1181:1181:1181) (1216:1216:1216)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1091:1091:1091) (1052:1052:1052)) + (PORT datab (813:813:813) (822:822:822)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (1192:1192:1192) (1207:1207:1207)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~32) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (852:852:852)) + (PORT datab (1419:1419:1419) (1456:1456:1456)) + (PORT datac (1053:1053:1053) (1042:1042:1042)) + (PORT datad (1447:1447:1447) (1463:1463:1463)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~34) + (DELAY + (ABSOLUTE + (PORT dataa (773:773:773) (793:793:793)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (778:778:778) (755:755:755)) + (PORT datad (1535:1535:1535) (1512:1512:1512)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~20) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (897:897:897)) + (PORT datab (238:238:238) (306:306:306)) + (PORT datac (1541:1541:1541) (1531:1531:1531)) + (PORT datad (860:860:860) (848:848:848)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1106:1106:1106) (1107:1107:1107)) + (PORT datab (1190:1190:1190) (1223:1223:1223)) + (PORT datac (831:831:831) (807:807:807)) + (PORT datad (754:754:754) (778:778:778)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~35) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~15) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (595:595:595)) + (PORT datab (1138:1138:1138) (1159:1159:1159)) + (PORT datac (1315:1315:1315) (1372:1372:1372)) + (PORT datad (571:571:571) (567:567:567)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~14) + (DELAY + (ABSOLUTE + (PORT datab (200:200:200) (233:233:233)) + (PORT datac (570:570:570) (566:566:566)) + (PORT datad (1769:1769:1769) (1734:1734:1734)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1075:1075:1075) (1081:1081:1081)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (1251:1251:1251) (1218:1218:1218)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1080:1080:1080) (1095:1095:1095)) + (PORT datab (1056:1056:1056) (1051:1051:1051)) + (PORT datac (1288:1288:1288) (1303:1303:1303)) + (PORT datad (1217:1217:1217) (1233:1233:1233)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1040:1040:1040) (1031:1031:1031)) + (PORT datab (1493:1493:1493) (1562:1562:1562)) + (PORT datac (1243:1243:1243) (1219:1219:1219)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (836:836:836)) + (PORT datab (1063:1063:1063) (1094:1094:1094)) + (PORT datac (615:615:615) (678:678:678)) + (PORT datad (809:809:809) (802:802:802)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~9) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (834:834:834)) + (PORT datac (1396:1396:1396) (1416:1416:1416)) + (PORT datad (777:777:777) (749:749:749)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~13) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (236:236:236)) + (PORT datab (1102:1102:1102) (1107:1107:1107)) + (PORT datac (1119:1119:1119) (1115:1115:1115)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~18) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (892:892:892)) + (PORT datab (639:639:639) (636:636:636)) + (PORT datac (161:161:161) (194:194:194)) + (PORT datad (1822:1822:1822) (1821:1821:1821)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~19) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (868:868:868)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (1380:1380:1380) (1410:1410:1410)) + (PORT datad (584:584:584) (592:592:592)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1026:1026:1026) (1035:1035:1035)) + (PORT datab (1030:1030:1030) (1102:1102:1102)) + (PORT datac (519:519:519) (523:523:523)) + (PORT datad (760:760:760) (739:739:739)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~42) + (DELAY + (ABSOLUTE + (PORT dataa (1598:1598:1598) (1641:1641:1641)) + (PORT datab (1850:1850:1850) (1845:1845:1845)) + (PORT datac (872:872:872) (896:896:896)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~44) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (940:940:940)) + (PORT datab (923:923:923) (945:945:945)) + (PORT datac (154:154:154) (183:183:183)) + (PORT datad (870:870:870) (890:890:890)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1367:1367:1367) (1369:1369:1369)) + (PORT datab (1287:1287:1287) (1271:1271:1271)) + (PORT datac (1350:1350:1350) (1421:1421:1421)) + (PORT datad (548:548:548) (552:552:552)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~51) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (220:220:220)) + (PORT datab (194:194:194) (234:234:234)) + (PORT datac (174:174:174) (205:205:205)) + (PORT datad (321:321:321) (325:325:325)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) + (DELAY + (ABSOLUTE + (PORT datab (242:242:242) (312:312:312)) + (PORT datac (617:617:617) (656:656:656)) + (PORT datad (828:828:828) (836:836:836)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|T6) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1366:1366:1366)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1403:1403:1403) (1369:1369:1369)) + (PORT ena (1133:1133:1133) (1118:1118:1118)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~52) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (849:849:849) (901:901:901)) + (PORT datac (1262:1262:1262) (1245:1245:1245)) + (PORT datad (337:337:337) (338:338:338)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~53) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (573:573:573)) + (PORT datab (1030:1030:1030) (1023:1023:1023)) + (PORT datac (836:836:836) (888:888:888)) + (PORT datad (506:506:506) (503:503:503)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) + (DELAY + (ABSOLUTE + (PORT datab (640:640:640) (689:689:689)) + (PORT datad (830:830:830) (838:838:838)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -46820,9 +49981,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M1_ff) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1383:1383:1383)) + (PORT clk (1346:1346:1346) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1379:1379:1379)) + (PORT clrn (1403:1403:1403) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -46836,11 +49997,11 @@ (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (1060:1060:1060) (1064:1064:1064)) - (PORT datab (255:255:255) (332:332:332)) - (PORT datad (1047:1047:1047) (1037:1037:1037)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT dataa (618:618:618) (647:647:647)) + (PORT datab (653:653:653) (687:687:687)) + (PORT datad (819:819:819) (832:832:832)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -46851,9 +50012,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1383:1383:1383)) + (PORT clk (1346:1346:1346) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1379:1379:1379)) + (PORT clrn (1403:1403:1403) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -46864,3104 +50025,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~3) + (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) (DELAY (ABSOLUTE - (PORT datac (968:968:968) (1046:1046:1046)) - (PORT datad (1866:1866:1866) (1882:1882:1882)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1349:1349:1349) (1370:1370:1370)) - (PORT datab (785:785:785) (802:802:802)) - (PORT datac (735:735:735) (729:729:729)) - (PORT datad (611:611:611) (629:629:629)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~8) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (957:957:957)) - (PORT datab (617:617:617) (624:624:624)) - (PORT datac (880:880:880) (892:892:892)) - (PORT datad (2085:2085:2085) (2090:2090:2090)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~9) - (DELAY - (ABSOLUTE - (PORT dataa (805:805:805) (809:809:809)) - (PORT datab (780:780:780) (771:771:771)) - (PORT datac (859:859:859) (884:884:884)) - (PORT datad (372:372:372) (382:382:382)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~10) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (644:644:644)) - (PORT datab (310:310:310) (327:327:327)) - (PORT datac (1356:1356:1356) (1374:1374:1374)) - (PORT datad (1918:1918:1918) (1931:1931:1931)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~12) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (380:380:380)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (165:165:165) (190:190:190)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1847:1847:1847) (1878:1878:1878)) - (PORT datab (798:798:798) (792:792:792)) - (PORT datac (1341:1341:1341) (1341:1341:1341)) - (PORT datad (165:165:165) (189:189:189)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~6) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (249:249:249)) - (PORT datab (212:212:212) (254:254:254)) - (PORT datac (326:326:326) (340:340:340)) - (PORT datad (982:982:982) (970:970:970)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~7) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (252:252:252)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (915:915:915) (941:941:941)) - (PORT datad (730:730:730) (727:727:727)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~13) - (DELAY - (ABSOLUTE - (PORT datab (1021:1021:1021) (1030:1030:1030)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (296:296:296) (297:297:297)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~39) - (DELAY - (ABSOLUTE - (PORT datac (715:715:715) (700:700:700)) - (PORT datad (563:563:563) (569:569:569)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~5) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (226:226:226)) - (PORT datab (1883:1883:1883) (1863:1863:1863)) - (PORT datac (580:580:580) (600:600:600)) - (PORT datad (316:316:316) (307:307:307)) - (IOPATH dataa combout (287:287:287) (289:289:289)) + (PORT datab (909:909:909) (960:960:960)) + (PORT datac (1140:1140:1140) (1196:1196:1196)) + (PORT datad (887:887:887) (940:940:940)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~14) - (DELAY - (ABSOLUTE - (PORT dataa (776:776:776) (748:748:748)) - (PORT datab (808:808:808) (829:829:829)) - (PORT datac (950:950:950) (937:937:937)) - (PORT datad (496:496:496) (489:489:489)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT datab (248:248:248) (320:320:320)) - (PORT datac (1029:1029:1029) (1026:1026:1026)) - (PORT datad (1051:1051:1051) (1039:1039:1039)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1383:1383:1383)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1379:1379:1379)) - (PORT ena (1790:1790:1790) (1839:1839:1839)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (1053:1053:1053) (1051:1051:1051)) - (PORT datac (222:222:222) (293:293:293)) - (PORT datad (1051:1051:1051) (1043:1043:1043)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1383:1383:1383)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1379:1379:1379)) - (PORT ena (1790:1790:1790) (1839:1839:1839)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) - (DELAY - (ABSOLUTE - (PORT datab (241:241:241) (310:310:310)) - (PORT datac (1013:1013:1013) (1010:1010:1010)) - (PORT datad (1055:1055:1055) (1045:1045:1045)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|T6) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1383:1383:1383)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1379:1379:1379)) - (PORT ena (1790:1790:1790) (1839:1839:1839)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~13) - (DELAY - (ABSOLUTE - (PORT dataa (564:564:564) (569:569:569)) - (PORT datab (816:816:816) (818:818:818)) - (PORT datac (549:549:549) (564:564:564)) - (PORT datad (849:849:849) (880:880:880)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~1) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (1007:1007:1007)) - (PORT datab (1100:1100:1100) (1122:1122:1122)) - (PORT datac (599:599:599) (635:635:635)) - (PORT datad (1151:1151:1151) (1207:1207:1207)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~12) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (639:639:639)) - (PORT datab (1532:1532:1532) (1512:1512:1512)) - (PORT datac (807:807:807) (801:801:801)) - (PORT datad (793:793:793) (792:792:792)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~14) - (DELAY - (ABSOLUTE - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (589:589:589) (602:602:602)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~41) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (398:398:398)) - (PORT datac (998:998:998) (981:981:981)) - (PORT datad (184:184:184) (208:208:208)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~42) - (DELAY - (ABSOLUTE - (PORT dataa (869:869:869) (887:887:887)) - (PORT datab (1013:1013:1013) (1053:1053:1053)) - (PORT datac (372:372:372) (402:402:402)) - (PORT datad (2321:2321:2321) (2343:2343:2343)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1847:1847:1847) (1918:1918:1918)) - (PORT datab (712:712:712) (752:752:752)) - (PORT datac (885:885:885) (901:901:901)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~44) - (DELAY - (ABSOLUTE - (PORT dataa (831:831:831) (838:838:838)) - (PORT datab (326:326:326) (348:348:348)) - (PORT datac (182:182:182) (216:216:216)) - (PORT datad (704:704:704) (684:684:684)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~50) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (361:361:361)) - (PORT datab (969:969:969) (965:965:965)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (1210:1210:1210) (1195:1195:1195)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1039:1039:1039) (1043:1043:1043)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (180:180:180) (214:214:214)) - (PORT datad (166:166:166) (193:193:193)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~6) - (DELAY - (ABSOLUTE - (PORT dataa (796:796:796) (780:780:780)) - (PORT datab (1460:1460:1460) (1549:1549:1549)) - (PORT datac (577:577:577) (576:576:576)) - (PORT datad (1557:1557:1557) (1605:1605:1605)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~7) - (DELAY - (ABSOLUTE - (PORT datab (794:794:794) (821:821:821)) - (PORT datac (823:823:823) (838:838:838)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1334:1334:1334) (1334:1334:1334)) - (PORT datab (803:803:803) (797:797:797)) - (PORT datac (811:811:811) (824:824:824)) - (PORT datad (577:577:577) (578:578:578)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1375:1375:1375) (1454:1454:1454)) - (PORT datab (1812:1812:1812) (1844:1844:1844)) - (PORT datac (1240:1240:1240) (1288:1288:1288)) - (PORT datad (1027:1027:1027) (1026:1026:1026)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~10) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datab (1045:1045:1045) (1040:1040:1040)) - (PORT datac (478:478:478) (466:466:466)) - (PORT datad (591:591:591) (606:606:606)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~11) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (1127:1127:1127) (1133:1133:1133)) - (PORT datac (938:938:938) (948:948:948)) - (PORT datad (320:320:320) (321:321:321)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~17) - (DELAY - (ABSOLUTE - (PORT dataa (579:579:579) (601:601:601)) - (PORT datab (967:967:967) (963:963:963)) - (PORT datac (1852:1852:1852) (1836:1836:1836)) - (PORT datad (572:572:572) (581:581:581)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~31) - (DELAY - (ABSOLUTE - (PORT dataa (585:585:585) (588:588:588)) - (PORT datab (857:857:857) (877:877:877)) - (PORT datac (1676:1676:1676) (1729:1729:1729)) - (PORT datad (818:818:818) (827:827:827)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~28) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (357:357:357)) - (PORT datab (1132:1132:1132) (1137:1137:1137)) - (PORT datac (1298:1298:1298) (1315:1315:1315)) - (PORT datad (776:776:776) (761:761:761)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~30) - (DELAY - (ABSOLUTE - (PORT dataa (804:804:804) (811:811:811)) - (PORT datab (847:847:847) (854:854:854)) - (PORT datac (836:836:836) (830:830:830)) - (PORT datad (782:782:782) (783:783:783)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~32) - (DELAY - (ABSOLUTE - (PORT dataa (846:846:846) (882:882:882)) - (PORT datab (337:337:337) (351:351:351)) - (PORT datac (796:796:796) (810:810:810)) - (PORT datad (1018:1018:1018) (1013:1013:1013)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~33) - (DELAY - (ABSOLUTE - (PORT dataa (548:548:548) (548:548:548)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (832:832:832) (844:844:844)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1041:1041:1041) (1098:1098:1098)) - (PORT datac (574:574:574) (578:578:578)) - (PORT datad (1463:1463:1463) (1509:1509:1509)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~26) - (DELAY - (ABSOLUTE - (PORT dataa (802:802:802) (826:826:826)) - (PORT datab (1442:1442:1442) (1485:1485:1485)) - (PORT datac (796:796:796) (808:808:808)) - (PORT datad (1033:1033:1033) (1055:1055:1055)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~24) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (642:642:642)) - (PORT datab (616:616:616) (622:622:622)) - (PORT datac (1876:1876:1876) (1825:1825:1825)) - (PORT datad (875:875:875) (914:914:914)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~27) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (591:591:591) (617:617:617)) - (PORT datad (618:618:618) (657:657:657)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~22) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (885:885:885)) - (PORT datab (835:835:835) (821:821:821)) - (PORT datac (818:818:818) (833:833:833)) - (PORT datad (573:573:573) (585:585:585)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1599:1599:1599) (1658:1658:1658)) - (PORT datab (1429:1429:1429) (1495:1495:1495)) - (PORT datac (1123:1123:1123) (1162:1162:1162)) - (PORT datad (1378:1378:1378) (1406:1406:1406)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~53) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (922:922:922)) - (PORT datab (857:857:857) (886:886:886)) - (PORT datac (597:597:597) (611:611:611)) - (PORT datad (1199:1199:1199) (1205:1205:1205)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~23) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (216:216:216)) - (PORT datab (337:337:337) (357:357:357)) - (PORT datac (1413:1413:1413) (1418:1418:1418)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~18) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (367:367:367)) - (PORT datab (915:915:915) (914:914:914)) - (PORT datac (1406:1406:1406) (1456:1456:1456)) - (PORT datad (176:176:176) (198:198:198)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~19) - (DELAY - (ABSOLUTE - (PORT dataa (577:577:577) (576:576:576)) - (PORT datab (645:645:645) (668:668:668)) - (PORT datac (601:601:601) (626:626:626)) - (PORT datad (1213:1213:1213) (1266:1266:1266)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~20) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (615:615:615)) - (PORT datab (1087:1087:1087) (1081:1081:1081)) - (PORT datac (803:803:803) (828:828:828)) - (PORT datad (559:559:559) (573:573:573)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~34) - (DELAY - (ABSOLUTE - (PORT dataa (571:571:571) (580:580:580)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (287:287:287) (302:302:302)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~52) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (181:181:181) (212:212:212)) - (PORT datac (294:294:294) (298:298:298)) - (PORT datad (896:896:896) (948:948:948)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) - (DELAY - (ABSOLUTE - (PORT dataa (1043:1043:1043) (1054:1054:1054)) - (PORT datac (221:221:221) (291:291:291)) - (PORT datad (1054:1054:1054) (1045:1045:1045)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1383:1383:1383)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1379:1379:1379)) - (PORT ena (1790:1790:1790) (1839:1839:1839)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) - (DELAY - (ABSOLUTE - (PORT datac (910:910:910) (962:962:962)) - (PORT datad (1249:1249:1249) (1347:1347:1347)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~0) - (DELAY - (ABSOLUTE - (PORT dataa (329:329:329) (455:455:455)) - (PORT datac (1095:1095:1095) (1138:1138:1138)) - (PORT datad (248:248:248) (314:314:314)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~1) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (624:624:624)) - (PORT datab (1469:1469:1469) (1435:1435:1435)) - (PORT datad (583:583:583) (604:604:604)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|in_halt) - (DELAY - (ABSOLUTE - (PORT clk (1340:1340:1340) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1394:1394:1394) (1365:1365:1365)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (937:937:937)) - (PORT datab (1083:1083:1083) (1086:1086:1086)) - (PORT datac (627:627:627) (644:644:644)) - (PORT datad (584:584:584) (600:600:600)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1034:1034:1034) (1114:1114:1114)) - (PORT datab (920:920:920) (954:954:954)) - (PORT datac (1064:1064:1064) (1070:1070:1070)) - (PORT datad (810:810:810) (834:834:834)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (387:387:387)) - (PORT datab (634:634:634) (662:662:662)) - (PORT datac (824:824:824) (850:850:850)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) - (DELAY - (ABSOLUTE - (PORT datac (1009:1009:1009) (991:991:991)) - (PORT datad (598:598:598) (594:594:594)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (237:237:237)) - (PORT datab (879:879:879) (890:890:890)) - (PORT datac (592:592:592) (588:588:588)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (278:278:278)) - (PORT datac (871:871:871) (897:897:897)) - (PORT datad (319:319:319) (319:319:319)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~93) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (259:259:259)) - (PORT datab (715:715:715) (783:783:783)) - (PORT datac (1250:1250:1250) (1311:1311:1311)) - (PORT datad (524:524:524) (516:516:516)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~94) - (DELAY - (ABSOLUTE - (PORT dataa (578:578:578) (590:590:590)) - (PORT datab (676:676:676) (742:742:742)) - (PORT datad (662:662:662) (727:727:727)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) - (DELAY - (ABSOLUTE - (PORT dataa (686:686:686) (757:757:757)) - (PORT datab (1089:1089:1089) (1147:1147:1147)) - (PORT datac (667:667:667) (731:731:731)) - (PORT datad (673:673:673) (744:744:744)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~98) - (DELAY - (ABSOLUTE - (PORT dataa (187:187:187) (225:225:225)) - (PORT datab (191:191:191) (227:227:227)) - (PORT datad (169:169:169) (193:193:193)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (1042:1042:1042) (1038:1038:1038)) - (PORT datab (1068:1068:1068) (1080:1080:1080)) - (PORT datac (195:195:195) (262:262:262)) - (PORT datad (332:332:332) (369:369:369)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~99) - (DELAY - (ABSOLUTE - (PORT dataa (705:705:705) (773:773:773)) - (PORT datab (669:669:669) (726:726:726)) - (PORT datac (809:809:809) (846:846:846)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~100) - (DELAY - (ABSOLUTE - (PORT dataa (318:318:318) (341:341:341)) - (PORT datab (184:184:184) (216:216:216)) - (PORT datad (677:677:677) (738:738:738)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (751:751:751)) - (PORT datab (911:911:911) (964:964:964)) - (PORT datad (861:861:861) (908:908:908)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) - (DELAY - (ABSOLUTE - (PORT dataa (686:686:686) (759:759:759)) - (PORT datab (668:668:668) (738:738:738)) - (PORT datac (1059:1059:1059) (1118:1118:1118)) - (PORT datad (838:838:838) (881:881:881)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~133) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (639:639:639)) - (PORT datab (184:184:184) (217:217:217)) - (PORT datac (668:668:668) (734:734:734)) - (PORT datad (668:668:668) (738:738:738)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~103) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (220:220:220)) - (PORT datad (303:303:303) (304:304:304)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (566:566:566) (558:558:558)) - (PORT datab (394:394:394) (426:426:426)) - (PORT datac (525:525:525) (528:528:528)) - (PORT datad (576:576:576) (609:609:609)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) - (DELAY - (ABSOLUTE - (PORT dataa (662:662:662) (728:728:728)) - (PORT datab (672:672:672) (738:738:738)) - (PORT datac (660:660:660) (729:729:729)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~105) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (221:221:221)) - (PORT datab (335:335:335) (355:355:355)) - (PORT datad (661:661:661) (726:726:726)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) - (DELAY - (ABSOLUTE - (PORT dataa (1301:1301:1301) (1378:1378:1378)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (882:882:882) (920:920:920)) - (PORT datad (186:186:186) (212:212:212)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (662:662:662) (715:715:715)) - (PORT datab (613:613:613) (653:653:653)) - (PORT datac (599:599:599) (635:635:635)) - (PORT datad (402:402:402) (445:445:445)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (253:253:253)) - (PORT datab (374:374:374) (437:437:437)) - (PORT datac (577:577:577) (623:623:623)) - (PORT datad (374:374:374) (422:422:422)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~134) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (360:360:360)) - (PORT datab (357:357:357) (355:355:355)) - (PORT datad (771:771:771) (785:785:785)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (738:738:738)) - (PORT datab (563:563:563) (574:574:574)) - (PORT datac (574:574:574) (594:594:594)) - (PORT datad (490:490:490) (478:478:478)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~135) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (742:742:742)) - (PORT datab (248:248:248) (322:322:322)) - (PORT datad (1012:1012:1012) (1017:1017:1017)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~108) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (221:221:221)) - (PORT datab (344:344:344) (366:366:366)) - (PORT datad (161:161:161) (181:181:181)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (294:294:294)) - (PORT datab (1116:1116:1116) (1127:1127:1127)) - (PORT datac (580:580:580) (615:615:615)) - (PORT datad (725:725:725) (703:703:703)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~112) - (DELAY - (ABSOLUTE - (PORT dataa (791:791:791) (792:792:792)) - (PORT datab (200:200:200) (243:243:243)) - (PORT datac (592:592:592) (617:617:617)) - (PORT datad (302:302:302) (303:303:303)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~113) - (DELAY - (ABSOLUTE - (PORT dataa (664:664:664) (716:716:716)) - (PORT datab (184:184:184) (218:218:218)) - (PORT datac (531:531:531) (535:535:535)) - (PORT datad (420:420:420) (476:476:476)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~114) - (DELAY - (ABSOLUTE - (PORT datab (530:530:530) (510:510:510)) - (PORT datad (810:810:810) (810:810:810)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1389:1389:1389) (1370:1370:1370)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~109) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (719:719:719)) - (PORT datab (606:606:606) (639:639:639)) - (PORT datac (592:592:592) (618:618:618)) - (PORT datad (743:743:743) (755:755:755)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (719:719:719)) - (PORT datab (202:202:202) (246:246:246)) - (PORT datac (158:158:158) (189:189:189)) - (PORT datad (587:587:587) (622:622:622)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~137) - (DELAY - (ABSOLUTE - (PORT dataa (679:679:679) (735:735:735)) - (PORT datab (311:311:311) (328:328:328)) - (PORT datad (320:320:320) (332:332:332)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~138) - (DELAY - (ABSOLUTE - (PORT dataa (955:955:955) (1042:1042:1042)) - (PORT datab (617:617:617) (625:625:625)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~2) - (DELAY - (ABSOLUTE - (PORT datab (1289:1289:1289) (1294:1294:1294)) - (PORT datac (1505:1505:1505) (1522:1522:1522)) - (PORT datad (1100:1100:1100) (1138:1138:1138)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (250:250:250)) - (PORT datab (1109:1109:1109) (1116:1116:1116)) - (PORT datac (1094:1094:1094) (1124:1124:1124)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (1044:1044:1044) (1051:1051:1051)) - (PORT datab (3054:3054:3054) (3103:3103:3103)) - (PORT datac (1064:1064:1064) (1065:1065:1065)) - (PORT datad (522:522:522) (508:508:508)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (980:980:980) (986:986:986)) - (PORT clk (1635:1635:1635) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3707:3707:3707) (3804:3804:3804)) - (PORT d[1] (1578:1578:1578) (1672:1672:1672)) - (PORT d[2] (1570:1570:1570) (1580:1580:1580)) - (PORT d[3] (1744:1744:1744) (1781:1781:1781)) - (PORT d[4] (2000:2000:2000) (2056:2056:2056)) - (PORT d[5] (1252:1252:1252) (1314:1314:1314)) - (PORT d[6] (1393:1393:1393) (1427:1427:1427)) - (PORT d[7] (3116:3116:3116) (3137:3137:3137)) - (PORT d[8] (3368:3368:3368) (3477:3477:3477)) - (PORT d[9] (1365:1365:1365) (1402:1402:1402)) - (PORT d[10] (2948:2948:2948) (3034:3034:3034)) - (PORT d[11] (1950:1950:1950) (1990:1990:1990)) - (PORT d[12] (1611:1611:1611) (1636:1636:1636)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2373:2373:2373) (2344:2344:2344)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1662:1662:1662)) - (PORT d[0] (2716:2716:2716) (2716:2716:2716)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1626:1626:1626)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (873:873:873)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (630:630:630) (628:628:628)) - (PORT clk (1638:1638:1638) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2822:2822:2822) (2886:2886:2886)) - (PORT d[1] (1278:1278:1278) (1342:1342:1342)) - (PORT d[2] (1874:1874:1874) (1890:1890:1890)) - (PORT d[3] (2022:2022:2022) (2058:2058:2058)) - (PORT d[4] (1456:1456:1456) (1471:1471:1471)) - (PORT d[5] (1295:1295:1295) (1333:1333:1333)) - (PORT d[6] (1113:1113:1113) (1134:1134:1134)) - (PORT d[7] (3108:3108:3108) (3147:3147:3147)) - (PORT d[8] (2300:2300:2300) (2397:2397:2397)) - (PORT d[9] (3216:3216:3216) (3294:3294:3294)) - (PORT d[10] (2671:2671:2671) (2745:2745:2745)) - (PORT d[11] (1652:1652:1652) (1662:1662:1662)) - (PORT d[12] (1326:1326:1326) (1338:1338:1338)) - (PORT clk (1635:1635:1635) (1664:1664:1664)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1816:1816:1816) (1750:1750:1750)) - (PORT clk (1635:1635:1635) (1664:1664:1664)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (PORT d[0] (2737:2737:2737) (2658:2658:2658)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1630:1630:1630)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (922:922:922) (927:927:927)) - (PORT clk (1638:1638:1638) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2795:2795:2795) (2848:2848:2848)) - (PORT d[1] (1266:1266:1266) (1343:1343:1343)) - (PORT d[2] (1514:1514:1514) (1548:1548:1548)) - (PORT d[3] (1400:1400:1400) (1414:1414:1414)) - (PORT d[4] (1779:1779:1779) (1814:1814:1814)) - (PORT d[5] (1512:1512:1512) (1565:1565:1565)) - (PORT d[6] (1276:1276:1276) (1252:1252:1252)) - (PORT d[7] (1343:1343:1343) (1370:1370:1370)) - (PORT d[8] (1995:1995:1995) (2080:2080:2080)) - (PORT d[9] (3525:3525:3525) (3617:3617:3617)) - (PORT d[10] (2413:2413:2413) (2469:2469:2469)) - (PORT d[11] (1699:1699:1699) (1726:1726:1726)) - (PORT d[12] (1884:1884:1884) (1885:1885:1885)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1540:1540:1540) (1489:1489:1489)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1665:1665:1665)) - (PORT d[0] (2009:2009:2009) (1976:1976:1976)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1629:1629:1629)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (583:583:583)) - (PORT datab (1241:1241:1241) (1253:1253:1253)) - (PORT datac (822:822:822) (826:826:826)) - (PORT datad (1069:1069:1069) (1093:1093:1093)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1194:1194:1194) (1213:1213:1213)) - (PORT clk (1635:1635:1635) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3401:3401:3401) (3484:3484:3484)) - (PORT d[1] (1574:1574:1574) (1681:1681:1681)) - (PORT d[2] (2794:2794:2794) (2844:2844:2844)) - (PORT d[3] (2020:2020:2020) (2045:2045:2045)) - (PORT d[4] (2098:2098:2098) (2151:2151:2151)) - (PORT d[5] (2235:2235:2235) (2358:2358:2358)) - (PORT d[6] (1916:1916:1916) (1960:1960:1960)) - (PORT d[7] (2559:2559:2559) (2570:2570:2570)) - (PORT d[8] (2818:2818:2818) (2924:2924:2924)) - (PORT d[9] (2371:2371:2371) (2420:2420:2420)) - (PORT d[10] (3473:3473:3473) (3560:3560:3560)) - (PORT d[11] (1678:1678:1678) (1707:1707:1707)) - (PORT d[12] (1889:1889:1889) (1941:1941:1941)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2582:2582:2582) (2504:2504:2504)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1662:1662:1662)) - (PORT d[0] (2502:2502:2502) (2419:2419:2419)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1626:1626:1626)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (873:873:873)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (1118:1118:1118) (1126:1126:1126)) - (PORT datab (871:871:871) (890:890:890)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (1322:1322:1322) (1324:1324:1324)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3379:3379:3379) (3440:3440:3440)) - (PORT d[1] (2405:2405:2405) (2528:2528:2528)) - (PORT d[2] (1530:1530:1530) (1562:1562:1562)) - (PORT d[3] (1999:1999:1999) (2040:2040:2040)) - (PORT d[4] (1736:1736:1736) (1773:1773:1773)) - (PORT d[5] (1249:1249:1249) (1314:1314:1314)) - (PORT d[6] (1072:1072:1072) (1078:1078:1078)) - (PORT d[7] (1356:1356:1356) (1369:1369:1369)) - (PORT d[8] (2015:2015:2015) (2100:2100:2100)) - (PORT d[9] (3546:3546:3546) (3640:3640:3640)) - (PORT d[10] (2382:2382:2382) (2434:2434:2434)) - (PORT d[11] (1950:1950:1950) (1977:1977:1977)) - (PORT d[12] (1872:1872:1872) (1878:1878:1878)) - (PORT clk (1635:1635:1635) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1662:1662:1662)) - (PORT d[0] (3104:3104:3104) (3115:3115:3115)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1628:1628:1628)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (875:875:875)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (876:876:876)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (876:876:876)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1369:1369:1369) (1374:1374:1374)) - (PORT clk (1631:1631:1631) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3108:3108:3108) (3171:3171:3171)) - (PORT d[1] (2132:2132:2132) (2244:2244:2244)) - (PORT d[2] (2028:2028:2028) (2054:2054:2054)) - (PORT d[3] (1703:1703:1703) (1741:1741:1741)) - (PORT d[4] (2005:2005:2005) (2050:2050:2050)) - (PORT d[5] (1526:1526:1526) (1603:1603:1603)) - (PORT d[6] (1381:1381:1381) (1387:1387:1387)) - (PORT d[7] (1387:1387:1387) (1412:1412:1412)) - (PORT d[8] (2698:2698:2698) (2780:2780:2780)) - (PORT d[9] (2115:2115:2115) (2160:2160:2160)) - (PORT d[10] (2120:2120:2120) (2141:2141:2141)) - (PORT d[11] (2296:2296:2296) (2349:2349:2349)) - (PORT d[12] (1833:1833:1833) (1854:1854:1854)) - (PORT clk (1628:1628:1628) (1658:1658:1658)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2623:2623:2623) (2592:2592:2592)) - (PORT clk (1628:1628:1628) (1658:1658:1658)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1660:1660:1660)) - (PORT d[0] (3652:3652:3652) (3652:3652:3652)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1590:1590:1590) (1590:1590:1590)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2131:2131:2131) (2069:2069:2069)) - (PORT clk (1598:1598:1598) (1597:1597:1597)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4055:4055:4055) (3966:3966:3966)) - (PORT d[1] (3960:3960:3960) (3871:3871:3871)) - (PORT d[2] (3972:3972:3972) (3879:3879:3879)) - (PORT d[3] (4222:4222:4222) (4150:4150:4150)) - (PORT d[4] (3999:3999:3999) (3860:3860:3860)) - (PORT d[5] (4046:4046:4046) (3954:3954:3954)) - (PORT d[6] (4173:4173:4173) (4155:4155:4155)) - (PORT d[7] (4052:4052:4052) (3984:3984:3984)) - (PORT d[8] (4288:4288:4288) (4117:4117:4117)) - (PORT d[9] (4142:4142:4142) (4230:4230:4230)) - (PORT d[10] (4065:4065:4065) (3987:3987:3987)) - (PORT d[11] (4060:4060:4060) (3947:3947:3947)) - (PORT d[12] (4312:4312:4312) (4202:4202:4202)) - (PORT clk (1595:1595:1595) (1594:1594:1594)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1598:1598:1598) (1597:1597:1597)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1598:1598:1598)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1598:1598:1598)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1598:1598:1598)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1598:1598:1598)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (827:827:827) (847:847:847)) - (PORT datab (1559:1559:1559) (1578:1578:1578)) - (PORT datac (849:849:849) (860:860:860)) - (PORT datad (1100:1100:1100) (1108:1108:1108)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3343:3343:3343) (3403:3403:3403)) - (PORT d[1] (2414:2414:2414) (2527:2527:2527)) - (PORT d[2] (1429:1429:1429) (1441:1441:1441)) - (PORT d[3] (1966:1966:1966) (2008:2008:2008)) - (PORT d[4] (2008:2008:2008) (2048:2048:2048)) - (PORT d[5] (1520:1520:1520) (1595:1595:1595)) - (PORT d[6] (1309:1309:1309) (1307:1307:1307)) - (PORT d[7] (1368:1368:1368) (1386:1386:1386)) - (PORT d[8] (1998:1998:1998) (2066:2066:2066)) - (PORT d[9] (2127:2127:2127) (2184:2184:2184)) - (PORT d[10] (2112:2112:2112) (2157:2157:2157)) - (PORT d[11] (1966:1966:1966) (2005:2005:2005)) - (PORT d[12] (2122:2122:2122) (2139:2139:2139)) - (PORT clk (1633:1633:1633) (1661:1661:1661)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) - (PORT d[0] (3092:3092:3092) (3079:3079:3079)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1634:1634:1634) (1662:1662:1662)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1600:1600:1600) (1627:1627:1627)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (875:875:875)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (875:875:875)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (875:875:875)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (250:250:250)) - (PORT datab (847:847:847) (835:835:835)) - (PORT datac (1051:1051:1051) (1049:1049:1049)) - (PORT datad (164:164:164) (189:189:189)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1450:1450:1450) (1449:1449:1449)) - (PORT clk (1648:1648:1648) (1675:1675:1675)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2348:2348:2348) (2361:2361:2361)) - (PORT d[1] (1826:1826:1826) (1904:1904:1904)) - (PORT d[2] (1810:1810:1810) (1851:1851:1851)) - (PORT d[3] (1736:1736:1736) (1783:1783:1783)) - (PORT d[4] (2527:2527:2527) (2584:2584:2584)) - (PORT d[5] (2063:2063:2063) (2160:2160:2160)) - (PORT d[6] (1896:1896:1896) (1915:1915:1915)) - (PORT d[7] (2227:2227:2227) (2299:2299:2299)) - (PORT d[8] (2227:2227:2227) (2294:2294:2294)) - (PORT d[9] (1856:1856:1856) (1895:1895:1895)) - (PORT d[10] (1573:1573:1573) (1593:1593:1593)) - (PORT d[11] (1905:1905:1905) (1933:1933:1933)) - (PORT d[12] (2334:2334:2334) (2363:2363:2363)) - (PORT clk (1645:1645:1645) (1673:1673:1673)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2467:2467:2467) (2383:2383:2383)) - (PORT clk (1645:1645:1645) (1673:1673:1673)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1648:1648:1648) (1675:1675:1675)) - (PORT d[0] (3048:3048:3048) (3059:3059:3059)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1649:1649:1649) (1676:1676:1676)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1649:1649:1649) (1676:1676:1676)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1649:1649:1649) (1676:1676:1676)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1649:1649:1649) (1676:1676:1676)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1605:1605:1605)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1916:1916:1916) (1862:1862:1862)) - (PORT clk (1615:1615:1615) (1612:1612:1612)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4316:4316:4316) (4210:4210:4210)) - (PORT d[1] (3963:3963:3963) (3872:3872:3872)) - (PORT d[2] (4234:4234:4234) (4138:4138:4138)) - (PORT d[3] (4142:4142:4142) (4039:4039:4039)) - (PORT d[4] (4033:4033:4033) (3901:3901:3901)) - (PORT d[5] (4276:4276:4276) (4177:4177:4177)) - (PORT d[6] (4393:4393:4393) (4366:4366:4366)) - (PORT d[7] (4261:4261:4261) (4171:4171:4171)) - (PORT d[8] (4248:4248:4248) (4146:4146:4146)) - (PORT d[9] (4156:4156:4156) (4242:4242:4242)) - (PORT d[10] (4088:4088:4088) (4006:4006:4006)) - (PORT d[11] (4322:4322:4322) (4216:4216:4216)) - (PORT d[12] (4272:4272:4272) (4307:4307:4307)) - (PORT clk (1612:1612:1612) (1609:1609:1609)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1615:1615:1615) (1612:1612:1612)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1616:1616:1616) (1613:1613:1613)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1616:1616:1616) (1613:1613:1613)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1616:1616:1616) (1613:1613:1613)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1616:1616:1616) (1613:1613:1613)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1608:1608:1608) (1606:1606:1606)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (828:828:828) (850:850:850)) - (PORT datab (189:189:189) (224:224:224)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (1365:1365:1365) (1368:1368:1368)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~108) - (DELAY - (ABSOLUTE - (PORT dataa (1483:1483:1483) (1482:1482:1482)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1506:1506:1506) (1523:1523:1523)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~95) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (233:233:233)) - (PORT datab (1305:1305:1305) (1292:1292:1292)) - (PORT datac (1230:1230:1230) (1217:1217:1217)) - (PORT datad (316:316:316) (319:319:319)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~96) - (DELAY - (ABSOLUTE - (PORT dataa (1518:1518:1518) (1480:1480:1480)) - (PORT datab (1303:1303:1303) (1289:1289:1289)) - (PORT datac (1032:1032:1032) (1052:1052:1052)) - (PORT datad (298:298:298) (295:295:295)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (946:946:946)) - (PORT datab (1541:1541:1541) (1532:1532:1532)) - (PORT datac (211:211:211) (260:260:260)) - (PORT datad (820:820:820) (816:816:816)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (227:227:227) (279:279:279)) - (PORT datab (604:604:604) (646:646:646)) - (PORT datad (194:194:194) (223:223:223)) - (IOPATH dataa combout (267:267:267) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (907:907:907) (908:908:908)) - (PORT datab (837:837:837) (858:858:858)) - (PORT datac (817:817:817) (833:833:833)) - (PORT datad (850:850:850) (853:853:853)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1361:1361:1361)) - (PORT ena (1363:1363:1363) (1319:1319:1319)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1349:1349:1349) (1408:1408:1408)) - (PORT datab (1083:1083:1083) (1086:1086:1086)) - (PORT datac (1096:1096:1096) (1157:1157:1157)) - (PORT datad (1293:1293:1293) (1285:1285:1285)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) (DELAY (ABSOLUTE - (PORT dataa (836:836:836) (868:868:868)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datac (821:821:821) (822:822:822)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (189:189:189) (227:227:227)) + (PORT datab (1372:1372:1372) (1395:1395:1395)) + (PORT datad (1092:1092:1092) (1089:1089:1089)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -49970,9 +50056,9 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1294:1294:1294) (1268:1268:1268)) - (PORT datab (581:581:581) (603:603:603)) - (PORT datad (165:165:165) (189:189:189)) + (PORT dataa (1092:1092:1092) (1122:1122:1122)) + (PORT datab (781:781:781) (765:765:765)) + (PORT datad (159:159:159) (180:180:180)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -49984,11 +50070,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1358:1358:1358)) + (PORT clk (1349:1349:1349) (1359:1359:1359)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (524:524:524) (587:587:587)) - (PORT sload (1033:1033:1033) (1049:1049:1049)) - (PORT ena (735:735:735) (733:733:733)) + (PORT asdata (647:647:647) (684:684:684)) + (PORT sload (1315:1315:1315) (1359:1359:1359)) + (PORT ena (1338:1338:1338) (1327:1327:1327)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -50001,29 +50087,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~59) + (INSTANCE D\[0\]\~66) (DELAY (ABSOLUTE - (PORT dataa (818:818:818) (820:820:820)) - (PORT datab (1053:1053:1053) (1083:1083:1083)) - (PORT datac (162:162:162) (196:196:196)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT datab (835:835:835) (837:837:837)) + (PORT datac (805:805:805) (817:817:817)) + (PORT datad (166:166:166) (188:188:188)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~60) + (INSTANCE D\[0\]\~67) (DELAY (ABSOLUTE - (PORT dataa (875:875:875) (889:889:889)) - (PORT datab (601:601:601) (626:626:626)) - (PORT datac (1532:1532:1532) (1518:1518:1518)) - (PORT datad (305:305:305) (310:310:310)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (PORT dataa (2560:2560:2560) (2559:2559:2559)) + (PORT datab (1368:1368:1368) (1383:1383:1383)) + (PORT datac (1370:1370:1370) (1379:1379:1379)) + (PORT datad (287:287:287) (293:293:293)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -50031,13 +50117,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~61) + (INSTANCE D\[0\]\~121) (DELAY (ABSOLUTE - (PORT dataa (1333:1333:1333) (1327:1327:1327)) - (PORT datac (767:767:767) (762:762:762)) - (PORT datad (179:179:179) (201:201:201)) - (IOPATH dataa combout (307:307:307) (306:306:306)) + (PORT dataa (2429:2429:2429) (2459:2459:2459)) + (PORT datab (1783:1783:1783) (1866:1866:1866)) + (PORT datac (2569:2569:2569) (2667:2667:2667)) + (PORT datad (2260:2260:2260) (2252:2252:2252)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~68) + (DELAY + (ABSOLUTE + (PORT datab (626:626:626) (643:643:643)) + (PORT datac (1001:1001:1001) (1003:1003:1003)) + (PORT datad (324:324:324) (332:332:332)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -50045,13 +50147,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~62) + (INSTANCE D\[1\]\~69) (DELAY (ABSOLUTE - (PORT dataa (1305:1305:1305) (1307:1307:1307)) - (PORT datab (871:871:871) (918:918:918)) - (PORT datac (894:894:894) (961:961:961)) - (PORT datad (159:159:159) (179:179:179)) + (PORT dataa (2560:2560:2560) (2559:2559:2559)) + (PORT datab (883:883:883) (922:922:922)) + (PORT datac (1369:1369:1369) (1378:1378:1378)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~70) + (DELAY + (ABSOLUTE + (PORT datab (1076:1076:1076) (1097:1097:1097)) + (PORT datac (782:782:782) (785:785:785)) + (PORT datad (305:305:305) (308:308:308)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (2031:2031:2031) (2020:2020:2020)) + (PORT datab (578:578:578) (593:593:593)) + (PORT datac (1571:1571:1571) (1601:1601:1601)) + (PORT datad (159:159:159) (180:180:180)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -50061,13 +50193,73 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~63) + (INSTANCE D\[3\]\~83) (DELAY (ABSOLUTE - (PORT dataa (344:344:344) (370:370:370)) - (PORT datac (162:162:162) (196:196:196)) - (PORT datad (165:165:165) (189:189:189)) - (IOPATH dataa combout (307:307:307) (306:306:306)) + (PORT dataa (2559:2559:2559) (2556:2556:2556)) + (PORT datac (841:841:841) (883:883:883)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (368:368:368)) + (PORT datab (876:876:876) (873:873:873)) + (PORT datac (312:312:312) (314:314:314)) + (PORT datad (309:309:309) (317:317:317)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~95) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (863:863:863)) + (PORT datab (848:848:848) (853:853:853)) + (PORT datac (163:163:163) (198:198:198)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~96) + (DELAY + (ABSOLUTE + (PORT dataa (1193:1193:1193) (1257:1257:1257)) + (PORT datab (405:405:405) (418:418:418)) + (PORT datac (2040:2040:2040) (2021:2021:2021)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~126) + (DELAY + (ABSOLUTE + (PORT dataa (1730:1730:1730) (1712:1712:1712)) + (PORT datab (2864:2864:2864) (2965:2965:2965)) + (PORT datac (571:571:571) (569:569:569)) + (PORT datad (305:305:305) (307:307:307)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -50075,13 +50267,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~64) + (INSTANCE D\[5\]\~98) (DELAY (ABSOLUTE - (PORT dataa (384:384:384) (441:441:441)) - (PORT datab (209:209:209) (250:250:250)) - (PORT datac (1058:1058:1058) (1046:1046:1046)) - (PORT datad (159:159:159) (181:181:181)) + (PORT dataa (1115:1115:1115) (1152:1152:1152)) + (PORT datab (625:625:625) (617:617:617)) + (PORT datac (2270:2270:2270) (2238:2238:2238)) + (PORT datad (160:160:160) (181:181:181)) (IOPATH dataa combout (307:307:307) (280:280:280)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -50091,72 +50283,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~75) + (INSTANCE D\[6\]\~105) (DELAY (ABSOLUTE - (PORT dataa (193:193:193) (236:236:236)) - (PORT datac (1230:1230:1230) (1219:1219:1219)) - (PORT datad (180:180:180) (202:202:202)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (1040:1040:1040) (1082:1082:1082)) - (PORT datab (1068:1068:1068) (1064:1064:1064)) - (PORT datac (1432:1432:1432) (1391:1391:1391)) - (PORT datad (304:304:304) (309:309:309)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (820:820:820) (823:823:823)) - (PORT datab (1439:1439:1439) (1439:1439:1439)) - (PORT datad (166:166:166) (189:189:189)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (895:895:895)) - (PORT datab (1330:1330:1330) (1350:1350:1350)) - (PORT datac (1533:1533:1533) (1516:1516:1516)) - (PORT datad (306:306:306) (314:314:314)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~92) - (DELAY - (ABSOLUTE - (PORT datab (1278:1278:1278) (1232:1232:1232)) - (PORT datac (162:162:162) (195:195:195)) - (PORT datad (165:165:165) (187:187:187)) + (PORT datab (810:810:810) (813:813:813)) + (PORT datac (342:342:342) (345:345:345)) + (PORT datad (324:324:324) (330:330:330)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -50165,15 +50297,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~93) + (INSTANCE D\[6\]\~106) (DELAY (ABSOLUTE - (PORT dataa (876:876:876) (893:893:893)) - (PORT datab (824:824:824) (860:860:860)) - (PORT datac (1532:1532:1532) (1521:1521:1521)) + (PORT dataa (1123:1123:1123) (1165:1165:1165)) + (PORT datab (577:577:577) (590:590:590)) + (PORT datac (2006:2006:2006) (1993:1993:1993)) (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~128) + (DELAY + (ABSOLUTE + (PORT dataa (2594:2594:2594) (2704:2704:2704)) + (PORT datab (1879:1879:1879) (1883:1883:1883)) + (PORT datac (164:164:164) (200:200:200)) + (PORT datad (568:568:568) (585:585:585)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~107) + (DELAY + (ABSOLUTE + (PORT dataa (1113:1113:1113) (1139:1139:1139)) + (PORT datab (2300:2300:2300) (2288:2288:2288)) + (PORT datac (322:322:322) (330:330:330)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) + (DELAY + (ABSOLUTE + (PORT datab (225:225:225) (298:298:298)) + (PORT datac (793:793:793) (776:776:776)) + (PORT datad (210:210:210) (270:270:270)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -50184,11 +50362,11 @@ (INSTANCE z80_\|nM1_int\~3) (DELAY (ABSOLUTE - (PORT datab (1270:1270:1270) (1359:1359:1359)) - (PORT datac (2167:2167:2167) (2222:2222:2222)) - (PORT datad (516:516:516) (508:508:508)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datab (640:640:640) (689:689:689)) + (PORT datac (618:618:618) (656:656:656)) + (PORT datad (570:570:570) (600:600:600)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -50198,10 +50376,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_16) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1378:1378:1378)) + (PORT clk (1346:1346:1346) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1189:1189:1189) (1191:1191:1191)) + (PORT clrn (1403:1403:1403) (1369:1369:1369)) + (PORT ena (1133:1133:1133) (1118:1118:1118)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50216,7 +50394,7 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17\~feeder) (DELAY (ABSOLUTE - (PORT datad (220:220:220) (279:279:279)) + (PORT datad (626:626:626) (660:660:660)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -50226,10 +50404,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17) (DELAY (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) + (PORT clk (1349:1349:1349) (1356:1356:1356)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1217:1217:1217) (1223:1223:1223)) + (PORT clrn (1399:1399:1399) (1367:1367:1367)) + (PORT ena (1146:1146:1146) (1137:1137:1137)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50244,10 +50422,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_mreq_ff2) (DELAY (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) - (PORT asdata (511:511:511) (578:578:578)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1217:1217:1217) (1223:1223:1223)) + (PORT clk (1349:1349:1349) (1356:1356:1356)) + (PORT asdata (513:513:513) (581:581:581)) + (PORT clrn (1399:1399:1399) (1367:1367:1367)) + (PORT ena (1146:1146:1146) (1137:1137:1137)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50262,9 +50440,9 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~0) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (302:302:302)) - (PORT datab (228:228:228) (299:299:299)) - (PORT datad (197:197:197) (253:253:253)) + (PORT dataa (844:844:844) (882:882:882)) + (PORT datab (229:229:229) (301:301:301)) + (PORT datad (203:203:203) (263:263:263)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -50277,12 +50455,13 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~1) (DELAY (ABSOLUTE - (PORT dataa (850:850:850) (873:873:873)) - (PORT datab (184:184:184) (217:217:217)) - (PORT datad (167:167:167) (191:191:191)) + (PORT dataa (227:227:227) (304:304:304)) + (PORT datab (237:237:237) (311:311:311)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (165:165:165) (190:190:190)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -50310,9 +50489,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[0\]) (DELAY (ABSOLUTE - (PORT clk (1683:1683:1683) (1697:1697:1697)) + (PORT clk (1684:1684:1684) (1698:1698:1698)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1376:1376:1376)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50326,8 +50505,8 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (231:231:231) (309:309:309)) - (PORT datab (228:228:228) (301:301:301)) + (PORT dataa (382:382:382) (427:427:427)) + (PORT datab (228:228:228) (299:299:299)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datab combout (306:306:306) (324:324:324)) @@ -50341,9 +50520,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1683:1683:1683) (1697:1697:1697)) + (PORT clk (1684:1684:1684) (1698:1698:1698)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1376:1376:1376)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50357,7 +50536,7 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]\~7) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (306:306:306)) + (PORT dataa (231:231:231) (307:307:307)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -50371,9 +50550,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1683:1683:1683) (1697:1697:1697)) + (PORT clk (1684:1684:1684) (1698:1698:1698)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1376:1376:1376)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50387,9 +50566,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[3\]\~9) (DELAY (ABSOLUTE - (PORT datab (229:229:229) (301:301:301)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (231:231:231) (310:310:310)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -50401,9 +50580,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1683:1683:1683) (1697:1697:1697)) + (PORT clk (1684:1684:1684) (1698:1698:1698)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1376:1376:1376)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50412,6 +50591,22 @@ (HOLD d (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|WideAnd0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (306:306:306)) + (PORT datab (240:240:240) (310:310:310)) + (PORT datac (200:200:200) (271:271:271)) + (PORT datad (205:205:205) (266:266:266)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) @@ -50431,9 +50626,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1683:1683:1683) (1697:1697:1697)) + (PORT clk (1684:1684:1684) (1698:1698:1698)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1376:1376:1376)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50447,7 +50642,7 @@ (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) (DELAY (ABSOLUTE - (PORT datad (205:205:205) (267:267:267)) + (PORT datad (206:206:206) (265:265:265)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) ) @@ -50458,9 +50653,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[5\]) (DELAY (ABSOLUTE - (PORT clk (1683:1683:1683) (1697:1697:1697)) + (PORT clk (1684:1684:1684) (1698:1698:1698)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1376:1376:1376)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50471,43 +50666,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|WideAnd0\~0) + (INSTANCE ula_\|i2c_loader_\|WideAnd0) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (306:306:306)) - (PORT datab (229:229:229) (303:303:303)) - (PORT datac (201:201:201) (271:271:271)) - (PORT datad (205:205:205) (266:266:266)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT datab (185:185:185) (219:219:219)) + (PORT datac (202:202:202) (273:273:273)) + (PORT datad (205:205:205) (263:263:263)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|WideAnd0) + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|scl_out\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT datab (228:228:228) (298:298:298)) - (PORT datac (158:158:158) (188:188:188)) - (PORT datad (204:204:204) (264:264:264)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1388:1388:1388) (1367:1367:1367)) + (PORT ena (923:923:923) (893:893:893)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2c_loader_\|state\.Idle) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1351:1351:1351) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (PORT ena (1273:1273:1273) (1300:1300:1300)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT ena (1351:1351:1351) (1346:1346:1346)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50522,7 +50719,7 @@ (INSTANCE ula_\|i2c_loader_\|phase\~0) (DELAY (ABSOLUTE - (PORT datad (223:223:223) (282:282:282)) + (PORT datad (374:374:374) (422:422:422)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -50533,10 +50730,10 @@ (INSTANCE ula_\|i2c_loader_\|phase\[0\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1351:1351:1351) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (PORT ena (1273:1273:1273) (1300:1300:1300)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT ena (1351:1351:1351) (1346:1346:1346)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50551,8 +50748,8 @@ (INSTANCE ula_\|i2c_loader_\|phase\~1) (DELAY (ABSOLUTE - (PORT datab (291:291:291) (392:392:392)) - (PORT datad (225:225:225) (285:285:285)) + (PORT datab (424:424:424) (459:459:459)) + (PORT datad (365:365:365) (409:409:409)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -50562,12 +50759,146 @@ (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2c_loader_\|phase\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT ena (798:798:798) (748:748:748)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|Mux42\~0) + (DELAY + (ABSOLUTE + (PORT datab (421:421:421) (474:474:474)) + (PORT datac (239:239:239) (317:317:317)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbyte\~0) + (DELAY + (ABSOLUTE + (PORT datab (433:433:433) (483:483:483)) + (PORT datac (536:536:536) (561:561:561)) + (PORT datad (812:812:812) (835:835:835)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~4) + (DELAY + (ABSOLUTE + (PORT datad (638:638:638) (682:682:682)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbyte\~4) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (436:436:436)) + (PORT datab (603:603:603) (633:633:633)) + (PORT datad (659:659:659) (703:703:703)) + (IOPATH dataa combout (273:273:273) (273:273:273)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) (DELAY (ABSOLUTE (PORT clk (1352:1352:1352) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (PORT ena (1273:1273:1273) (1300:1300:1300)) + (PORT clrn (1388:1388:1388) (1367:1367:1367)) + (PORT ena (745:745:745) (752:752:752)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (432:432:432) (481:481:481)) + (PORT datac (547:547:547) (576:576:576)) + (PORT datad (255:255:255) (324:324:324)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (223:223:223)) + (PORT datab (565:565:565) (590:590:590)) + (PORT datac (581:581:581) (609:609:609)) + (PORT datad (791:791:791) (820:820:820)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (624:624:624)) + (PORT datab (586:586:586) (589:589:589)) + (PORT datac (578:578:578) (633:633:633)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1688:1688:1688) (1702:1702:1702)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1391:1391:1391) (1369:1369:1369)) + (PORT ena (1102:1102:1102) (1090:1090:1090)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50582,31 +50913,69 @@ (INSTANCE ula_\|i2c_loader_\|nbit\~5) (DELAY (ABSOLUTE - (PORT dataa (592:592:592) (633:633:633)) + (PORT dataa (680:680:680) (720:720:720)) + (PORT datad (364:364:364) (401:401:401)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) (DELAY (ABSOLUTE - (PORT datab (274:274:274) (356:356:356)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT clk (1355:1355:1355) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1391:1391:1391) (1369:1369:1369)) + (PORT ena (1131:1131:1131) (1133:1133:1133)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (307:307:307)) + (PORT datab (237:237:237) (314:314:314)) + (PORT datad (357:357:357) (394:394:394)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|Mux42\~0) + (INSTANCE ula_\|i2c_loader_\|state\~27) (DELAY (ABSOLUTE - (PORT datac (645:645:645) (686:686:686)) - (PORT datad (631:631:631) (667:667:667)) + (PORT datab (422:422:422) (472:472:472)) + (PORT datac (241:241:241) (320:320:320)) + (PORT datad (612:612:612) (633:633:633)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~24) + (DELAY + (ABSOLUTE + (PORT datab (435:435:435) (482:482:482)) + (PORT datac (550:550:550) (576:576:576)) + (PORT datad (256:256:256) (325:325:325)) + (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -50614,28 +50983,174 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\~4) + (INSTANCE ula_\|i2c_loader_\|state\~26) (DELAY (ABSOLUTE - (PORT dataa (259:259:259) (342:342:342)) - (PORT datab (294:294:294) (395:395:395)) - (PORT datad (591:591:591) (624:624:624)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT datab (423:423:423) (474:474:474)) + (PORT datac (240:240:240) (318:318:318)) + (PORT datad (306:306:306) (320:320:320)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) + (DELAY + (ABSOLUTE + (PORT datab (183:183:183) (216:216:216)) + (PORT datad (160:160:160) (180:180:180)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Data) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (631:631:631) (633:633:633)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT sload (787:787:787) (899:899:899)) + (PORT ena (1351:1351:1351) (1346:1346:1346)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~0) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (722:722:722)) + (PORT datab (236:236:236) (312:312:312)) + (PORT datad (360:360:360) (399:399:399)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1391:1391:1391) (1369:1369:1369)) + (PORT ena (1131:1131:1131) (1133:1133:1133)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (308:308:308)) + (PORT datab (382:382:382) (428:428:428)) + (PORT datac (816:816:816) (837:837:837)) + (PORT datad (213:213:213) (280:280:280)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) + (DELAY + (ABSOLUTE + (PORT dataa (248:248:248) (326:326:326)) + (PORT datab (281:281:281) (359:359:359)) + (PORT datac (534:534:534) (558:558:558)) + (PORT datad (570:570:570) (602:602:602)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (626:626:626)) + (PORT datab (604:604:604) (658:658:658)) + (PORT datac (580:580:580) (608:608:608)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (596:596:596)) + (PORT datab (183:183:183) (214:214:214)) + (PORT datad (792:792:792) (823:823:823)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Ack) + (DELAY + (ABSOLUTE + (PORT clk (1708:1708:1708) (1724:1724:1724)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1387:1387:1387) (1367:1367:1367)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~7) (DELAY (ABSOLUTE - (PORT datab (261:261:261) (338:338:338)) - (PORT datac (541:541:541) (554:554:554)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datac (616:616:616) (662:662:662)) + (PORT datad (404:404:404) (442:442:442)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -50653,13 +51168,13 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (258:258:258) (341:341:341)) - (PORT datab (246:246:246) (321:321:321)) - (PORT datac (262:262:262) (362:362:362)) - (PORT datad (473:473:473) (454:454:454)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (388:388:388) (437:437:437)) + (PORT datab (695:695:695) (743:743:743)) + (PORT datac (216:216:216) (284:284:284)) + (PORT datad (465:465:465) (444:444:444)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -50669,13 +51184,13 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~2) (DELAY (ABSOLUTE - (PORT dataa (615:615:615) (661:661:661)) - (PORT datab (608:608:608) (607:607:607)) - (PORT datac (157:157:157) (188:188:188)) + (PORT dataa (323:323:323) (332:332:332)) + (PORT datab (602:602:602) (601:601:601)) + (PORT datac (571:571:571) (600:600:600)) (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -50685,30 +51200,30 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~3) (DELAY (ABSOLUTE - (PORT datab (783:783:783) (753:753:753)) - (PORT datac (390:390:390) (436:436:436)) - (PORT datad (159:159:159) (179:179:179)) + (PORT dataa (588:588:588) (638:638:638)) + (PORT datab (573:573:573) (573:573:573)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) + (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]) (DELAY (ABSOLUTE (PORT clk (1352:1352:1352) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) + (PORT asdata (635:635:635) (635:635:635)) + (PORT clrn (1388:1388:1388) (1367:1367:1367)) (PORT ena (745:745:745) (752:752:752)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) @@ -50717,12 +51232,12 @@ (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) (DELAY (ABSOLUTE - (PORT dataa (624:624:624) (676:676:676)) - (PORT datab (653:653:653) (687:687:687)) - (PORT datac (227:227:227) (300:300:300)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datab (433:433:433) (481:481:481)) + (PORT datac (548:548:548) (573:573:573)) + (PORT datad (252:252:252) (321:321:321)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -50731,11 +51246,11 @@ (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) (DELAY (ABSOLUTE - (PORT dataa (567:567:567) (548:548:548)) - (PORT datab (232:232:232) (282:282:282)) - (PORT datad (318:318:318) (318:318:318)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) + (PORT dataa (611:611:611) (625:625:625)) + (PORT datab (584:584:584) (585:585:585)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -50746,9 +51261,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Stop) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT clk (1708:1708:1708) (1724:1724:1724)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) + (PORT clrn (1387:1387:1387) (1367:1367:1367)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50759,15 +51274,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) (DELAY (ABSOLUTE - (PORT dataa (263:263:263) (348:348:348)) - (PORT datab (236:236:236) (312:312:312)) - (PORT datac (209:209:209) (285:285:285)) - (PORT datad (530:530:530) (549:549:549)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (PORT dataa (247:247:247) (324:324:324)) + (PORT datab (820:820:820) (857:857:857)) + (PORT datac (744:744:744) (764:764:764)) + (PORT datad (814:814:814) (832:832:832)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -50775,112 +51290,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~0) + (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) (DELAY (ABSOLUTE - (PORT dataa (593:593:593) (633:633:633)) - (PORT datab (243:243:243) (317:317:317)) - (PORT datad (214:214:214) (280:280:280)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT datab (268:268:268) (348:348:348)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1376:1376:1376)) - (PORT ena (1089:1089:1089) (1068:1068:1068)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~0) - (DELAY - (ABSOLUTE - (PORT dataa (236:236:236) (314:314:314)) - (PORT datab (226:226:226) (299:299:299)) - (PORT datac (561:561:561) (597:597:597)) - (PORT datad (216:216:216) (281:281:281)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) - (DELAY - (ABSOLUTE - (PORT dataa (336:336:336) (357:357:357)) - (PORT datab (345:345:345) (352:352:352)) - (PORT datac (846:846:846) (866:866:866)) - (PORT datad (307:307:307) (310:310:310)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (223:223:223)) - (PORT datab (526:526:526) (534:534:534)) - (PORT datad (406:406:406) (459:459:459)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Ack) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (259:259:259) (342:342:342)) - (PORT datab (245:245:245) (318:318:318)) - (PORT datac (263:263:263) (363:363:363)) - (PORT datad (474:474:474) (451:451:451)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (558:558:558) (582:582:582)) + (PORT datab (864:864:864) (877:877:877)) + (PORT datac (574:574:574) (597:597:597)) + (PORT datad (651:651:651) (612:612:612)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -50890,13 +51321,13 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~18) (DELAY (ABSOLUTE - (PORT dataa (388:388:388) (436:436:436)) - (PORT datab (551:551:551) (569:569:569)) - (PORT datac (792:792:792) (757:757:757)) - (PORT datad (289:289:289) (294:294:294)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (558:558:558) (568:568:568)) + (PORT datab (425:425:425) (461:461:461)) + (PORT datac (731:731:731) (749:749:749)) + (PORT datad (162:162:162) (184:184:184)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -50906,12 +51337,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1680:1680:1680) (1693:1693:1693)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (1044:1044:1044) (1030:1030:1030)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT sload (959:959:959) (944:944:944)) - (PORT ena (721:721:721) (723:723:723)) + (PORT asdata (2461:2461:2461) (2410:2410:2410)) + (PORT clrn (1387:1387:1387) (1367:1367:1367)) + (PORT sload (1381:1381:1381) (1389:1389:1389)) + (PORT ena (745:745:745) (752:752:752)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50928,7 +51359,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]\~10) (DELAY (ABSOLUTE - (PORT datab (265:265:265) (350:350:350)) + (PORT datab (259:259:259) (353:353:353)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -50942,12 +51373,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1680:1680:1680) (1693:1693:1693)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (1045:1045:1045) (1032:1032:1032)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT sload (959:959:959) (944:944:944)) - (PORT ena (721:721:721) (723:723:723)) + (PORT asdata (2461:2461:2461) (2410:2410:2410)) + (PORT clrn (1387:1387:1387) (1367:1367:1367)) + (PORT sload (1381:1381:1381) (1389:1389:1389)) + (PORT ena (745:745:745) (752:752:752)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50964,9 +51395,9 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]\~12) (DELAY (ABSOLUTE - (PORT datab (261:261:261) (339:339:339)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (272:272:272) (370:370:370)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -50978,11 +51409,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1680:1680:1680) (1693:1693:1693)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT sload (959:959:959) (944:944:944)) - (PORT ena (721:721:721) (723:723:723)) + (PORT clrn (1387:1387:1387) (1367:1367:1367)) + (PORT sload (1381:1381:1381) (1389:1389:1389)) + (PORT ena (745:745:745) (752:752:752)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50999,7 +51430,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]\~14) (DELAY (ABSOLUTE - (PORT datab (273:273:273) (360:360:360)) + (PORT datab (272:272:272) (352:352:352)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -51013,12 +51444,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1680:1680:1680) (1693:1693:1693)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (1045:1045:1045) (1032:1032:1032)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT sload (959:959:959) (944:944:944)) - (PORT ena (721:721:721) (723:723:723)) + (PORT asdata (2463:2463:2463) (2407:2407:2407)) + (PORT clrn (1387:1387:1387) (1367:1367:1367)) + (PORT sload (1381:1381:1381) (1389:1389:1389)) + (PORT ena (745:745:745) (752:752:752)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51035,29 +51466,13 @@ (INSTANCE ula_\|i2c_loader_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (400:400:400) (453:453:453)) - (PORT datab (266:266:266) (350:350:350)) - (PORT datac (245:245:245) (323:323:323)) - (PORT datad (248:248:248) (324:324:324)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (713:713:713)) - (PORT datab (237:237:237) (313:313:313)) - (PORT datac (649:649:649) (690:690:690)) - (PORT datad (234:234:234) (300:300:300)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (403:403:403) (463:463:463)) + (PORT datab (259:259:259) (352:352:352)) + (PORT datac (244:244:244) (341:341:341)) + (PORT datad (251:251:251) (320:320:320)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -51067,7 +51482,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]\~16) (DELAY (ABSOLUTE - (PORT dataa (278:278:278) (369:369:369)) + (PORT dataa (271:271:271) (357:357:357)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH cin combout (408:408:408) (387:387:387)) ) @@ -51078,11 +51493,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1680:1680:1680) (1693:1693:1693)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT sload (959:959:959) (944:944:944)) - (PORT ena (721:721:721) (723:723:723)) + (PORT clrn (1387:1387:1387) (1367:1367:1367)) + (PORT sload (1381:1381:1381) (1389:1389:1389)) + (PORT ena (745:745:745) (752:752:752)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51096,29 +51511,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~3) (DELAY (ABSOLUTE - (PORT datab (583:583:583) (569:569:569)) - (PORT datac (313:313:313) (323:323:323)) - (PORT datad (612:612:612) (632:632:632)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~2) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (240:240:240)) - (PORT datab (258:258:258) (335:335:335)) - (PORT datac (208:208:208) (282:282:282)) - (PORT datad (461:461:461) (431:431:431)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT datab (184:184:184) (216:216:216)) + (PORT datac (328:328:328) (331:331:331)) + (PORT datad (373:373:373) (408:408:408)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51126,15 +51525,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) + (INSTANCE ula_\|i2c_loader_\|scl_out\~0) (DELAY (ABSOLUTE - (PORT dataa (321:321:321) (330:330:330)) - (PORT datab (234:234:234) (288:288:288)) - (PORT datac (236:236:236) (319:319:319)) - (PORT datad (385:385:385) (435:435:435)) + (PORT dataa (382:382:382) (427:427:427)) + (PORT datab (446:446:446) (482:482:482)) + (PORT datad (808:808:808) (819:819:819)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~4) + (DELAY + (ABSOLUTE + (PORT dataa (516:516:516) (507:507:507)) + (PORT datab (246:246:246) (319:319:319)) + (PORT datac (228:228:228) (305:305:305)) + (PORT datad (612:612:612) (630:630:630)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~5) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (395:395:395) (456:456:456)) + (PORT datac (234:234:234) (309:309:309)) + (PORT datad (201:201:201) (236:236:236)) (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51142,14 +51571,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~3) + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~6) (DELAY (ABSOLUTE - (PORT dataa (321:321:321) (335:335:335)) - (PORT datab (554:554:554) (543:543:543)) - (PORT datad (160:160:160) (180:180:180)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) + (PORT dataa (833:833:833) (838:838:838)) + (PORT datab (590:590:590) (578:578:578)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51162,7 +51591,7 @@ (ABSOLUTE (PORT clk (1351:1351:1351) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51176,11 +51605,11 @@ (INSTANCE ula_\|i2c_loader_\|state\~25) (DELAY (ABSOLUTE - (PORT dataa (238:238:238) (315:315:315)) - (PORT datab (235:235:235) (289:289:289)) - (PORT datad (383:383:383) (431:431:431)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT dataa (227:227:227) (273:273:273)) + (PORT datab (248:248:248) (321:321:321)) + (PORT datad (369:369:369) (421:421:421)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51193,273 +51622,8 @@ (ABSOLUTE (PORT clk (1351:1351:1351) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) - (PORT ena (1069:1069:1069) (1069:1069:1069)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\~0) - (DELAY - (ABSOLUTE - (PORT datab (290:290:290) (389:389:389)) - (PORT datad (587:587:587) (620:620:620)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (PORT ena (745:745:745) (752:752:752)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (670:670:670)) - (PORT datac (625:625:625) (655:655:655)) - (PORT datad (404:404:404) (459:459:459)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (966:966:966) (966:966:966)) - (PORT datab (449:449:449) (502:502:502)) - (PORT datac (229:229:229) (302:302:302)) - (PORT datad (614:614:614) (648:648:648)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (547:547:547) (572:572:572)) - (PORT datad (305:305:305) (307:307:307)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (325:325:325) (342:342:342)) - (PORT datab (231:231:231) (283:283:283)) - (PORT datac (522:522:522) (513:513:513)) - (PORT datad (388:388:388) (434:434:434)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1683:1683:1683) (1697:1697:1697)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1376:1376:1376)) - (PORT ena (1060:1060:1060) (1026:1026:1026)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~6) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (630:630:630)) - (PORT datad (218:218:218) (284:284:284)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1376:1376:1376)) - (PORT ena (1089:1089:1089) (1068:1068:1068)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~1) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (317:317:317)) - (PORT datab (228:228:228) (302:302:302)) - (PORT datad (218:218:218) (284:284:284)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~27) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (707:707:707)) - (PORT datac (646:646:646) (687:687:687)) - (PORT datad (460:460:460) (431:431:431)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~24) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (675:675:675)) - (PORT datab (654:654:654) (686:686:686)) - (PORT datac (224:224:224) (296:296:296)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~26) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (712:712:712)) - (PORT datac (647:647:647) (689:689:689)) - (PORT datad (326:326:326) (325:325:325)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (224:224:224)) - (PORT datad (160:160:160) (180:180:180)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Data) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (516:516:516) (563:563:563)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) - (PORT sload (789:789:789) (905:905:905)) - (PORT ena (1069:1069:1069) (1069:1069:1069)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|scl_out\~0) - (DELAY - (ABSOLUTE - (PORT datab (261:261:261) (339:339:339)) - (PORT datac (570:570:570) (586:586:586)) - (PORT datad (209:209:209) (276:276:276)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|scl_out\~_Duplicate_1) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (PORT ena (1273:1273:1273) (1300:1300:1300)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT ena (1351:1351:1351) (1346:1346:1346)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51474,12 +51638,12 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~1) (DELAY (ABSOLUTE - (PORT dataa (614:614:614) (660:660:660)) - (PORT datab (290:290:290) (387:387:387)) - (PORT datac (232:232:232) (310:310:310)) - (PORT datad (199:199:199) (256:256:256)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (224:224:224) (297:297:297)) + (PORT datab (645:645:645) (690:690:690)) + (PORT datac (573:573:573) (601:601:601)) + (PORT datad (657:657:657) (701:701:701)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51490,11 +51654,11 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~2) (DELAY (ABSOLUTE - (PORT dataa (597:597:597) (609:609:609)) - (PORT datab (183:183:183) (217:217:217)) - (PORT datad (586:586:586) (618:618:618)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (PORT dataa (185:185:185) (223:223:223)) + (PORT datac (570:570:570) (600:600:600)) + (PORT datad (184:184:184) (211:211:211)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -51505,9 +51669,9 @@ (DELAY (ABSOLUTE (PORT clk (1306:1306:1306) (1319:1319:1319)) - (PORT d (850:850:850) (915:915:915)) - (PORT aload (1507:1507:1507) (1553:1553:1553)) - (PORT ena (798:798:798) (813:813:813)) + (PORT d (851:851:851) (915:915:915)) + (PORT aload (1497:1497:1497) (1541:1541:1541)) + (PORT ena (650:650:650) (643:643:643)) (IOPATH (posedge clk) q (549:549:549) (552:552:552)) (IOPATH (posedge aload) q (455:455:455) (458:458:458)) ) @@ -51526,8 +51690,8 @@ (ABSOLUTE (PORT clk (1352:1352:1352) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (PORT ena (1273:1273:1273) (1300:1300:1300)) + (PORT clrn (1388:1388:1388) (1367:1367:1367)) + (PORT ena (923:923:923) (893:893:893)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51537,29 +51701,29 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) - (DELAY - (ABSOLUTE - (PORT datac (811:811:811) (844:844:844)) - (PORT datad (569:569:569) (594:594:594)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|Mux35\~0) (DELAY (ABSOLUTE - (PORT dataa (412:412:412) (464:464:464)) - (PORT datab (422:422:422) (464:464:464)) - (PORT datac (364:364:364) (401:401:401)) - (PORT datad (365:365:365) (408:408:408)) - (IOPATH dataa combout (273:273:273) (269:269:269)) + (PORT dataa (404:404:404) (460:460:460)) + (PORT datab (258:258:258) (347:347:347)) + (PORT datac (237:237:237) (333:333:333)) + (PORT datad (249:249:249) (314:314:314)) + (IOPATH dataa combout (307:307:307) (306:306:306)) (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) + (DELAY + (ABSOLUTE + (PORT datac (569:569:569) (596:596:596)) + (PORT datad (807:807:807) (816:816:816)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51567,56 +51731,76 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) (DELAY (ABSOLUTE - (PORT dataa (277:277:277) (366:366:366)) - (PORT datab (266:266:266) (347:347:347)) - (PORT datac (246:246:246) (327:327:327)) - (PORT datad (235:235:235) (302:302:302)) + (PORT dataa (406:406:406) (461:461:461)) + (PORT datab (256:256:256) (351:351:351)) + (PORT datac (246:246:246) (331:331:331)) + (PORT datad (248:248:248) (317:317:317)) (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) (DELAY (ABSOLUTE - (PORT datac (248:248:248) (333:333:333)) - (PORT datad (236:236:236) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (273:273:273) (377:377:377)) + (PORT datab (540:540:540) (529:529:529)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (242:242:242) (311:311:311)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) (DELAY (ABSOLUTE - (PORT dataa (186:186:186) (224:224:224)) - (PORT datab (274:274:274) (361:361:361)) - (PORT datac (246:246:246) (329:329:329)) - (PORT datad (180:180:180) (203:203:203)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (275:275:275) (376:376:376)) + (PORT datab (266:266:266) (344:344:344)) + (PORT datac (247:247:247) (329:329:329)) + (PORT datad (248:248:248) (317:317:317)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~24) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) (DELAY (ABSOLUTE - (PORT datab (421:421:421) (464:464:464)) - (PORT datac (814:814:814) (846:846:846)) - (PORT datad (387:387:387) (428:428:428)) + (PORT dataa (520:520:520) (520:520:520)) + (PORT datab (258:258:258) (351:351:351)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (242:242:242) (312:312:312)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (445:445:445) (515:515:515)) + (PORT datac (630:630:630) (661:661:661)) + (PORT datad (618:618:618) (645:645:645)) (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -51628,11 +51812,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~6) (DELAY (ABSOLUTE - (PORT dataa (658:658:658) (710:710:710)) - (PORT datac (646:646:646) (690:690:690)) - (PORT datad (235:235:235) (304:304:304)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datab (252:252:252) (328:328:328)) + (PORT datac (239:239:239) (317:317:317)) + (PORT datad (382:382:382) (438:438:438)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -51642,13 +51826,13 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~7) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (352:352:352)) - (PORT datab (231:231:231) (281:281:281)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (329:329:329) (327:327:327)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (184:184:184) (220:220:220)) + (PORT datab (333:333:333) (357:357:357)) + (PORT datac (237:237:237) (315:315:315)) + (PORT datad (196:196:196) (230:230:230)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -51658,11 +51842,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~8) (DELAY (ABSOLUTE - (PORT datab (410:410:410) (470:470:470)) - (PORT datac (523:523:523) (517:517:517)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (833:833:833) (833:833:833)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datad (375:375:375) (426:426:426)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -51672,11 +51856,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1350:1350:1350) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT sclr (1021:1021:1021) (1080:1080:1080)) - (PORT ena (1279:1279:1279) (1235:1235:1235)) + (PORT clrn (1386:1386:1386) (1364:1364:1364)) + (PORT sclr (1196:1196:1196) (1234:1234:1234)) + (PORT ena (869:869:869) (854:854:854)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51689,46 +51873,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~24) (DELAY (ABSOLUTE - (PORT dataa (276:276:276) (365:365:365)) - (PORT datab (272:272:272) (355:355:355)) - (PORT datac (246:246:246) (327:327:327)) - (PORT datad (234:234:234) (302:302:302)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (358:358:358)) - (PORT datab (349:349:349) (357:357:357)) - (PORT datac (364:364:364) (400:400:400)) - (PORT datad (391:391:391) (431:431:431)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (298:298:298)) - (PORT datac (817:817:817) (848:848:848)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT datab (582:582:582) (591:591:591)) + (PORT datac (412:412:412) (477:477:477)) + (PORT datad (200:200:200) (258:258:258)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -51738,13 +51890,13 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~10) (DELAY (ABSOLUTE - (PORT dataa (662:662:662) (692:692:692)) - (PORT datab (445:445:445) (501:501:501)) - (PORT datac (545:545:545) (575:575:575)) - (PORT datad (180:180:180) (202:202:202)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (401:401:401) (459:459:459)) + (PORT datab (333:333:333) (353:353:353)) + (PORT datac (237:237:237) (315:315:315)) + (PORT datad (386:386:386) (434:434:434)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -51754,13 +51906,27 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~11) (DELAY (ABSOLUTE - (PORT dataa (966:966:966) (963:963:963)) - (PORT datab (525:525:525) (530:530:530)) - (PORT datac (847:847:847) (866:866:866)) + (PORT dataa (225:225:225) (271:271:271)) + (PORT datab (253:253:253) (329:329:329)) + (PORT datac (232:232:232) (309:309:309)) (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (833:833:833) (837:837:837)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datad (373:373:373) (420:420:420)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -51770,10 +51936,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1350:1350:1350) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT ena (1112:1112:1112) (1084:1084:1084)) + (PORT clrn (1386:1386:1386) (1364:1364:1364)) + (PORT ena (879:879:879) (879:879:879)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51785,45 +51951,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) (DELAY (ABSOLUTE - (PORT dataa (275:275:275) (366:366:366)) - (PORT datab (270:270:270) (356:356:356)) - (PORT datac (242:242:242) (322:322:322)) - (PORT datad (238:238:238) (311:311:311)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (466:466:466)) - (PORT datab (388:388:388) (440:440:440)) - (PORT datac (286:286:286) (299:299:299)) - (PORT datad (179:179:179) (201:201:201)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) - (DELAY - (ABSOLUTE - (PORT dataa (226:226:226) (300:300:300)) - (PORT datac (811:811:811) (842:842:842)) - (PORT datad (161:161:161) (183:183:183)) - (IOPATH dataa combout (273:273:273) (269:269:269)) + (PORT dataa (584:584:584) (577:577:577)) + (PORT datac (411:411:411) (477:477:477)) + (PORT datad (199:199:199) (257:257:257)) + (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51834,10 +51968,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[2\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1350:1350:1350) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT ena (1112:1112:1112) (1084:1084:1084)) + (PORT clrn (1386:1386:1386) (1364:1364:1364)) + (PORT ena (879:879:879) (879:879:879)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51849,13 +51983,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) (DELAY (ABSOLUTE - (PORT dataa (397:397:397) (450:450:450)) - (PORT datab (266:266:266) (347:347:347)) - (PORT datac (248:248:248) (332:332:332)) - (PORT datad (247:247:247) (319:319:319)) + (PORT dataa (274:274:274) (377:377:377)) + (PORT datab (257:257:257) (351:351:351)) + (PORT datac (246:246:246) (330:330:330)) + (PORT datad (248:248:248) (317:317:317)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -51865,31 +51999,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) (DELAY (ABSOLUTE - (PORT dataa (413:413:413) (470:470:470)) - (PORT datab (419:419:419) (462:462:462)) - (PORT datac (467:467:467) (451:451:451)) - (PORT datad (326:326:326) (334:334:334)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT dataa (275:275:275) (377:377:377)) + (PORT datac (249:249:249) (332:332:332)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (556:556:556)) + (PORT datab (320:320:320) (341:341:341)) + (PORT datac (632:632:632) (658:658:658)) + (PORT datad (618:618:618) (642:642:642)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~27) (DELAY (ABSOLUTE - (PORT dataa (595:595:595) (630:630:630)) - (PORT datab (222:222:222) (291:291:291)) - (PORT datac (812:812:812) (843:843:843)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (PORT dataa (225:225:225) (298:298:298)) + (PORT datab (769:769:769) (781:781:781)) + (PORT datac (415:415:415) (479:479:479)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51900,10 +52046,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1350:1350:1350) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT ena (1112:1112:1112) (1084:1084:1084)) + (PORT clrn (1386:1386:1386) (1364:1364:1364)) + (PORT ena (879:879:879) (879:879:879)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51915,16 +52061,48 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~25) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) (DELAY (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (626:626:626) (663:663:663)) - (PORT datac (571:571:571) (592:592:592)) - (PORT datad (340:340:340) (371:371:371)) + (PORT dataa (275:275:275) (376:376:376)) + (PORT datab (260:260:260) (353:353:353)) + (PORT datac (248:248:248) (330:330:330)) + (PORT datad (243:243:243) (313:313:313)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (676:676:676)) + (PORT datab (609:609:609) (600:600:600)) + (PORT datac (631:631:631) (658:658:658)) + (PORT datad (302:302:302) (312:312:312)) (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (298:298:298)) + (PORT datab (771:771:771) (783:783:783)) + (PORT datac (412:412:412) (481:481:481)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -51934,10 +52112,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[4\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1350:1350:1350) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT ena (1301:1301:1301) (1268:1268:1268)) + (PORT clrn (1386:1386:1386) (1364:1364:1364)) + (PORT ena (879:879:879) (879:879:879)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51949,12 +52127,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~12) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) (DELAY (ABSOLUTE - (PORT dataa (516:516:516) (499:499:499)) - (PORT datab (451:451:451) (499:499:499)) - (PORT datad (334:334:334) (372:372:372)) + (PORT dataa (595:595:595) (588:588:588)) + (PORT datab (580:580:580) (610:610:610)) + (PORT datad (339:339:339) (366:366:366)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -51966,11 +52144,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT clk (1350:1350:1350) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) - (PORT sload (1099:1099:1099) (1160:1160:1160)) - (PORT ena (735:735:735) (734:734:734)) + (PORT clrn (1386:1386:1386) (1364:1364:1364)) + (PORT sload (1121:1121:1121) (1182:1182:1182)) + (PORT ena (1090:1090:1090) (1059:1059:1059)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51987,11 +52165,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~9) (DELAY (ABSOLUTE - (PORT datab (592:592:592) (640:640:640)) - (PORT datac (816:816:816) (848:848:848)) - (PORT datad (181:181:181) (203:203:203)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT datab (596:596:596) (584:584:584)) + (PORT datac (410:410:410) (476:476:476)) + (PORT datad (358:358:358) (391:391:391)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -52001,11 +52179,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1350:1350:1350) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT sclr (1021:1021:1021) (1080:1080:1080)) - (PORT ena (1112:1112:1112) (1084:1084:1084)) + (PORT clrn (1386:1386:1386) (1364:1364:1364)) + (PORT sclr (1196:1196:1196) (1234:1234:1234)) + (PORT ena (879:879:879) (879:879:879)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52021,8 +52199,8 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]\~5) (DELAY (ABSOLUTE - (PORT datac (811:811:811) (843:843:843)) - (PORT datad (199:199:199) (256:256:256)) + (PORT datac (415:415:415) (485:485:485)) + (PORT datad (201:201:201) (259:259:259)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -52033,11 +52211,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1350:1350:1350) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT sclr (1021:1021:1021) (1080:1080:1080)) - (PORT ena (1279:1279:1279) (1235:1235:1235)) + (PORT clrn (1386:1386:1386) (1364:1364:1364)) + (PORT sclr (1196:1196:1196) (1234:1234:1234)) + (PORT ena (869:869:869) (854:854:854)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52053,12 +52231,12 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~0) (DELAY (ABSOLUTE - (PORT dataa (633:633:633) (669:669:669)) - (PORT datab (384:384:384) (437:437:437)) - (PORT datac (523:523:523) (541:541:541)) - (PORT datad (357:357:357) (391:391:391)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (624:624:624) (657:657:657)) + (PORT datab (817:817:817) (858:858:858)) + (PORT datac (377:377:377) (416:416:416)) + (PORT datad (810:810:810) (834:834:834)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -52069,13 +52247,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~1) (DELAY (ABSOLUTE - (PORT dataa (508:508:508) (497:497:497)) - (PORT datab (286:286:286) (385:385:385)) - (PORT datac (324:324:324) (326:326:326)) - (PORT datad (473:473:473) (451:451:451)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (320:320:320) (336:336:336)) + (PORT datab (696:696:696) (742:742:742)) + (PORT datac (177:177:177) (209:209:209)) + (PORT datad (464:464:464) (444:444:444)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -52085,10 +52263,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~2) (DELAY (ABSOLUTE - (PORT dataa (232:232:232) (308:308:308)) - (PORT datab (288:288:288) (386:386:386)) - (PORT datac (232:232:232) (308:308:308)) - (PORT datad (166:166:166) (188:188:188)) + (PORT dataa (231:231:231) (309:309:309)) + (PORT datab (698:698:698) (739:739:739)) + (PORT datac (615:615:615) (657:657:657)) + (PORT datad (166:166:166) (189:189:189)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -52101,10 +52279,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~3) (DELAY (ABSOLUTE - (PORT dataa (233:233:233) (312:312:312)) - (PORT datab (286:286:286) (382:382:382)) - (PORT datac (233:233:233) (308:308:308)) - (PORT datad (165:165:165) (188:188:188)) + (PORT dataa (231:231:231) (309:309:309)) + (PORT datab (698:698:698) (739:739:739)) + (PORT datac (615:615:615) (658:658:658)) + (PORT datad (166:166:166) (189:189:189)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -52117,10 +52295,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~4) (DELAY (ABSOLUTE - (PORT dataa (616:616:616) (657:657:657)) - (PORT datab (746:746:746) (747:747:747)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (161:161:161) (182:182:182)) + (PORT dataa (770:770:770) (806:806:806)) + (PORT datab (211:211:211) (248:248:248)) + (PORT datac (158:158:158) (188:188:188)) + (PORT datad (160:160:160) (181:181:181)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -52135,8 +52313,8 @@ (ABSOLUTE (PORT clk (1307:1307:1307) (1321:1321:1321)) (PORT d (612:612:612) (666:666:666)) - (PORT aload (1521:1521:1521) (1568:1568:1568)) - (PORT ena (1129:1129:1129) (1199:1199:1199)) + (PORT aload (1498:1498:1498) (1543:1543:1543)) + (PORT ena (849:849:849) (851:851:851)) (IOPATH (posedge clk) q (549:549:549) (552:552:552)) (IOPATH (posedge aload) q (455:455:455) (458:458:458)) ) @@ -52148,6 +52326,2173 @@ (HOLD ena (posedge clk) (89:89:89)) ) ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2078:2078:2078) (2078:2078:2078)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1685:1685:1685) (1668:1668:1668)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux38\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1453:1453:1453) (1466:1466:1466)) + (PORT datab (1207:1207:1207) (1218:1218:1218)) + (PORT datad (166:166:166) (193:193:193)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rd_pending) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (225:225:225) (298:298:298)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[3\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (232:232:232)) + (PORT datab (893:893:893) (931:931:931)) + (PORT datac (604:604:604) (614:614:614)) + (PORT datad (1240:1240:1240) (1289:1289:1289)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (616:616:616) (675:675:675)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (226:226:226) (297:297:297)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (616:616:616) (675:675:675)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[2\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (226:226:226) (298:298:298)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (616:616:616) (675:675:675)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[3\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (306:306:306)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (616:616:616) (675:675:675)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[4\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (228:228:228) (299:299:299)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (616:616:616) (675:675:675)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[5\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (309:309:309)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (616:616:616) (675:675:675)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[6\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (306:306:306)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (616:616:616) (675:675:675)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[7\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (228:228:228) (302:302:302)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (616:616:616) (675:675:675)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (307:307:307)) + (PORT datab (227:227:227) (299:299:299)) + (PORT datac (201:201:201) (272:272:272)) + (PORT datad (205:205:205) (267:267:267)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[8\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (229:229:229) (302:302:302)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (616:616:616) (675:675:675)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (310:310:310)) + (PORT datab (230:230:230) (304:304:304)) + (PORT datac (203:203:203) (275:275:275)) + (PORT datad (206:206:206) (268:268:268)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[9\]\~30) + (DELAY + (ABSOLUTE + (PORT datad (206:206:206) (266:266:266)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT sclr (616:616:616) (675:675:675)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sclr (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (330:330:330)) + (PORT datab (228:228:228) (300:300:300)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (205:205:205) (264:264:264)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~8) + (DELAY + (ABSOLUTE + (PORT datab (1278:1278:1278) (1325:1325:1325)) + (PORT datac (866:866:866) (903:903:903)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (235:235:235)) + (PORT datab (630:630:630) (641:641:641)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_pending) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (715:715:715) (769:769:769)) + (PORT datab (695:695:695) (764:764:764)) + (PORT datac (594:594:594) (658:658:658)) + (PORT datad (803:803:803) (787:787:787)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (734:734:734) (822:822:822)) + (PORT datab (951:951:951) (995:995:995)) + (PORT datac (1167:1167:1167) (1240:1240:1240)) + (PORT datad (532:532:532) (521:521:521)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (734:734:734) (822:822:822)) + (PORT datab (951:951:951) (995:995:995)) + (PORT datac (1167:1167:1167) (1240:1240:1240)) + (PORT datad (532:532:532) (521:521:521)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux4\~3) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (606:606:606)) + (PORT datab (274:274:274) (355:355:355)) + (PORT datad (560:560:560) (565:565:565)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.act_row\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1205:1205:1205) (1279:1279:1279)) + (PORT datab (990:990:990) (1064:1064:1064)) + (PORT datac (1299:1299:1299) (1308:1308:1308)) + (PORT datad (916:916:916) (970:970:970)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~2) + (DELAY + (ABSOLUTE + (PORT datac (237:237:237) (310:310:310)) + (PORT datad (259:259:259) (327:327:327)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.act_row\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (335:335:335) (361:361:361)) + (PORT datac (937:937:937) (999:999:999)) + (PORT datad (918:918:918) (973:973:973)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (880:880:880) (873:873:873)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1369:1369:1369)) + (PORT asdata (1444:1444:1444) (1449:1449:1449)) + (PORT ena (880:880:880) (873:873:873)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.act_row\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1115:1115:1115) (1135:1135:1135)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (880:880:880) (873:873:873)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal7\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1162:1162:1162) (1175:1175:1175)) + (PORT datab (1149:1149:1149) (1166:1166:1166)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1369:1369:1369)) + (PORT asdata (1214:1214:1214) (1246:1246:1246)) + (PORT ena (880:880:880) (873:873:873)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1349:1349:1349) (1369:1369:1369)) + (PORT asdata (2821:2821:2821) (2904:2904:2904)) + (PORT ena (880:880:880) (873:873:873)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2539:2539:2539) (2632:2632:2632)) + (PORT datab (930:930:930) (966:966:966)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal7\~2) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (421:421:421)) + (PORT datab (229:229:229) (300:300:300)) + (PORT datac (162:162:162) (194:194:194)) + (PORT datad (168:168:168) (193:193:193)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1326:1326:1326) (1338:1338:1338)) + (PORT datab (956:956:956) (1006:1006:1006)) + (PORT datac (935:935:935) (997:997:997)) + (PORT datad (952:952:952) (1028:1028:1028)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1180:1180:1180) (1236:1236:1236)) + (PORT datac (536:536:536) (538:538:538)) + (PORT datad (317:317:317) (320:320:320)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~2) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (228:228:228)) + (PORT datab (615:615:615) (604:604:604)) + (PORT datad (1257:1257:1257) (1239:1239:1239)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.wr_pending) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~8) + (DELAY + (ABSOLUTE + (PORT datac (1076:1076:1076) (1119:1119:1119)) + (PORT datad (979:979:979) (1051:1051:1051)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~9) + (DELAY + (ABSOLUTE + (PORT dataa (412:412:412) (463:463:463)) + (PORT datab (567:567:567) (568:568:568)) + (PORT datac (610:610:610) (660:660:660)) + (PORT datad (260:260:260) (328:328:328)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1182:1182:1182) (1238:1238:1238)) + (PORT datab (283:283:283) (358:358:358)) + (PORT datac (177:177:177) (208:208:208)) + (PORT datad (164:164:164) (188:188:188)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~4) + (DELAY + (ABSOLUTE + (PORT datab (633:633:633) (681:681:681)) + (PORT datac (536:536:536) (535:535:535)) + (PORT datad (1152:1152:1152) (1192:1192:1192)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1178:1178:1178) (1233:1233:1233)) + (PORT datac (1077:1077:1077) (1120:1120:1120)) + (PORT datad (979:979:979) (1051:1051:1051)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~5) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (893:893:893) (940:940:940)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (871:871:871)) + (PORT datac (740:740:740) (736:736:736)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (262:262:262) (346:346:346)) + (PORT datab (667:667:667) (726:726:726)) + (PORT datac (181:181:181) (217:217:217)) + (PORT datad (688:688:688) (726:726:726)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (256:256:256) (338:338:338)) + (PORT datab (265:265:265) (353:353:353)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (688:688:688) (727:727:727)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~6) + (DELAY + (ABSOLUTE + (PORT datab (273:273:273) (356:356:356)) + (PORT datac (563:563:563) (566:566:566)) + (PORT datad (159:159:159) (178:178:178)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1206:1206:1206) (1283:1283:1283)) + (PORT datac (935:935:935) (999:999:999)) + (PORT datad (913:913:913) (969:969:969)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~2) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (558:558:558)) + (PORT datab (1346:1346:1346) (1353:1353:1353)) + (PORT datac (611:611:611) (661:661:661)) + (PORT datad (976:976:976) (1050:1050:1050)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~3) + (DELAY + (ABSOLUTE + (PORT datab (759:759:759) (830:830:830)) + (PORT datac (716:716:716) (791:791:791)) + (PORT datad (816:816:816) (826:826:826)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~3) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (897:897:897)) + (PORT datab (264:264:264) (349:349:349)) + (PORT datad (689:689:689) (723:723:723)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~4) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (223:223:223)) + (PORT datab (263:263:263) (346:346:346)) + (PORT datac (808:808:808) (841:841:841)) + (PORT datad (246:246:246) (317:317:317)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~5) + (DELAY + (ABSOLUTE + (PORT dataa (820:820:820) (844:844:844)) + (PORT datab (266:266:266) (354:354:354)) + (PORT datac (637:637:637) (697:697:697)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~0) + (DELAY + (ABSOLUTE + (PORT datab (900:900:900) (968:968:968)) + (PORT datac (1152:1152:1152) (1213:1213:1213)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~7) + (DELAY + (ABSOLUTE + (PORT datac (1161:1161:1161) (1233:1233:1233)) + (PORT datad (908:908:908) (954:954:954)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~10) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (848:848:848)) + (PORT datab (903:903:903) (973:973:973)) + (PORT datac (1152:1152:1152) (1217:1217:1217)) + (PORT datad (624:624:624) (692:692:692)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~1) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (401:401:401)) + (PORT datab (356:356:356) (367:367:367)) + (PORT datac (943:943:943) (999:999:999)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~6) + (DELAY + (ABSOLUTE + (PORT dataa (746:746:746) (734:734:734)) + (PORT datab (320:320:320) (328:328:328)) + (PORT datac (233:233:233) (314:314:314)) + (PORT datad (786:786:786) (770:770:770)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (360:360:360)) + (PORT datab (1181:1181:1181) (1240:1240:1240)) + (PORT datac (872:872:872) (940:940:940)) + (PORT datad (321:321:321) (331:331:331)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~10) + (DELAY + (ABSOLUTE + (PORT dataa (718:718:718) (773:773:773)) + (PORT datab (695:695:695) (765:765:765)) + (PORT datac (699:699:699) (778:778:778)) + (PORT datad (623:623:623) (686:686:686)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~3) + (DELAY + (ABSOLUTE + (PORT dataa (730:730:730) (817:817:817)) + (PORT datab (946:946:946) (993:993:993)) + (PORT datac (175:175:175) (207:207:207)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~4) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (344:344:344)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (1161:1161:1161) (1231:1231:1231)) + (PORT datad (648:648:648) (710:710:710)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~7) + (DELAY + (ABSOLUTE + (PORT dataa (262:262:262) (345:345:345)) + (PORT datab (726:726:726) (761:761:761)) + (PORT datac (808:808:808) (843:843:843)) + (PORT datad (819:819:819) (858:858:858)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~8) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (339:339:339)) + (PORT datab (264:264:264) (351:351:351)) + (PORT datac (636:636:636) (695:695:695)) + (PORT datad (246:246:246) (319:319:319)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~5) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (901:901:901)) + (PORT datab (669:669:669) (728:728:728)) + (PORT datac (743:743:743) (740:740:740)) + (PORT datad (246:246:246) (316:316:316)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~6) + (DELAY + (ABSOLUTE + (PORT dataa (400:400:400) (452:452:452)) + (PORT datab (207:207:207) (244:244:244)) + (PORT datac (580:580:580) (598:598:598)) + (PORT datad (837:837:837) (851:851:851)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~9) + (DELAY + (ABSOLUTE + (PORT dataa (257:257:257) (338:338:338)) + (PORT datab (614:614:614) (625:625:625)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~2) + (DELAY + (ABSOLUTE + (PORT datab (935:935:935) (987:987:987)) + (PORT datac (874:874:874) (944:944:944)) + (PORT datad (918:918:918) (956:956:956)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~3) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (356:356:356)) + (PORT datab (1150:1150:1150) (1215:1215:1215)) + (PORT datac (1454:1454:1454) (1502:1502:1502)) + (PORT datad (1459:1459:1459) (1515:1515:1515)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1263:1263:1263) (1351:1351:1351)) + (PORT datab (1374:1374:1374) (1411:1411:1411)) + (PORT datac (156:156:156) (185:185:185)) + (PORT datad (1158:1158:1158) (1203:1203:1203)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~10) + (DELAY + (ABSOLUTE + (PORT datab (188:188:188) (222:222:222)) + (PORT datac (1077:1077:1077) (1120:1120:1120)) + (PORT datad (979:979:979) (1051:1051:1051)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.init_counter\[0\]\~0) + (DELAY + (ABSOLUTE + (IOPATH datac combout (312:312:312) (325:325:325)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1359:1359:1359) (1382:1382:1382)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~1) + (DELAY + (ABSOLUTE + (PORT datab (679:679:679) (727:727:727)) + (IOPATH datab cout (385:385:385) (280:280:280)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (256:256:256) (326:326:326)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (240:240:240) (313:313:313)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (445:445:445)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.init_counter\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (324:324:324) (326:326:326)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (315:315:315)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (315:315:315)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~12) + (DELAY + (ABSOLUTE + (PORT datab (240:240:240) (310:310:310)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~14) + (DELAY + (ABSOLUTE + (PORT datab (258:258:258) (329:329:329)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~16) + (DELAY + (ABSOLUTE + (PORT datab (240:240:240) (310:310:310)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~18) + (DELAY + (ABSOLUTE + (PORT datab (241:241:241) (310:310:310)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~20) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (314:314:314)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (437:437:437)) + (PORT datab (417:417:417) (452:452:452)) + (PORT datac (361:361:361) (402:402:402)) + (PORT datad (380:380:380) (416:416:416)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT datab (419:419:419) (451:451:451)) + (PORT datac (388:388:388) (423:423:423)) + (PORT datad (220:220:220) (281:281:281)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~22) + (DELAY + (ABSOLUTE + (PORT datab (227:227:227) (299:299:299)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~24) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (303:303:303)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~26) + (DELAY + (ABSOLUTE + (PORT datab (227:227:227) (298:298:298)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~28) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (307:307:307)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH cin combout (408:408:408) (387:387:387)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (309:309:309)) + (PORT datab (228:228:228) (301:301:301)) + (PORT datac (204:204:204) (275:275:275)) + (PORT datad (205:205:205) (267:267:267)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (220:220:220)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (330:330:330) (336:336:336)) + (PORT datad (364:364:364) (397:397:397)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~11) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (771:771:771)) + (PORT datab (275:275:275) (356:356:356)) + (PORT datad (686:686:686) (746:746:746)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~12) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (541:541:541)) + (PORT datab (604:604:604) (631:631:631)) + (PORT datac (1456:1456:1456) (1516:1516:1516)) + (PORT datad (160:160:160) (180:180:180)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1388:1388:1388) (1442:1442:1442)) + (PORT datab (1272:1272:1272) (1341:1341:1341)) + (PORT datac (525:525:525) (514:514:514)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (307:307:307) (289:289:289)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1232:1232:1232)) + (PORT datab (1348:1348:1348) (1355:1355:1355)) + (PORT datac (154:154:154) (185:185:185)) + (PORT datad (799:799:799) (808:808:808)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1134:1134:1134) (1201:1201:1201)) + (PORT datab (894:894:894) (940:940:940)) + (PORT datac (892:892:892) (941:941:941)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~2) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (707:707:707)) + (PORT datac (1039:1039:1039) (1035:1035:1035)) + (PORT datad (806:806:806) (815:815:815)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux72\~0) + (DELAY + (ABSOLUTE + (PORT datab (2824:2824:2824) (2811:2811:2811)) + (PORT datac (845:845:845) (884:884:884)) + (PORT datad (254:254:254) (322:322:322)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux72\~1) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (955:955:955)) + (PORT datab (2825:2825:2825) (2812:2812:2812)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (337:337:337) (335:335:335)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux84\~0) + (DELAY + (ABSOLUTE + (PORT datac (229:229:229) (306:306:306)) + (PORT datad (689:689:689) (727:727:727)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux84\~1) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (452:452:452)) + (PORT datab (272:272:272) (356:356:356)) + (PORT datac (236:236:236) (316:316:316)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux3\~0) + (DELAY + (ABSOLUTE + (PORT datab (2828:2828:2828) (2818:2818:2818)) + (PORT datac (1064:1064:1064) (1082:1082:1082)) + (PORT datad (255:255:255) (325:325:325)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (961:961:961)) + (PORT datab (2828:2828:2828) (2820:2820:2820)) + (PORT datac (291:291:291) (294:294:294)) + (PORT datad (323:323:323) (324:324:324)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux2\~0) + (DELAY + (ABSOLUTE + (PORT datab (2826:2826:2826) (2813:2813:2813)) + (PORT datac (1044:1044:1044) (1072:1072:1072)) + (PORT datad (258:258:258) (328:328:328)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (962:962:962)) + (PORT datab (2833:2833:2833) (2819:2819:2819)) + (PORT datac (320:320:320) (331:331:331)) + (PORT datad (583:583:583) (594:594:594)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux1\~0) + (DELAY + (ABSOLUTE + (PORT datab (2832:2832:2832) (2818:2818:2818)) + (PORT datac (1041:1041:1041) (1073:1073:1073)) + (PORT datad (253:253:253) (320:320:320)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (961:961:961)) + (PORT datab (2819:2819:2819) (2818:2818:2818)) + (PORT datac (567:567:567) (547:547:547)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT datab (2821:2821:2821) (2820:2820:2820)) + (PORT datac (903:903:903) (941:941:941)) + (PORT datad (257:257:257) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (962:962:962)) + (PORT datab (2831:2831:2831) (2818:2818:2818)) + (PORT datac (295:295:295) (304:304:304)) + (PORT datad (568:568:568) (579:579:579)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux73\~0) + (DELAY + (ABSOLUTE + (PORT datab (2823:2823:2823) (2814:2814:2814)) + (PORT datac (1378:1378:1378) (1423:1423:1423)) + (PORT datad (255:255:255) (322:322:322)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux73\~1) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (960:960:960)) + (PORT datab (2820:2820:2820) (2818:2818:2818)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (570:570:570) (583:583:583)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux74\~0) + (DELAY + (ABSOLUTE + (PORT datab (2827:2827:2827) (2816:2816:2816)) + (PORT datac (855:855:855) (891:891:891)) + (PORT datad (253:253:253) (321:321:321)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux74\~1) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (955:955:955)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (2789:2789:2789) (2780:2780:2780)) + (PORT datad (586:586:586) (607:607:607)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux75\~0) + (DELAY + (ABSOLUTE + (PORT datac (1406:1406:1406) (1471:1471:1471)) + (PORT datad (1269:1269:1269) (1252:1252:1252)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|mclk_r\~0) @@ -52162,9 +54507,9 @@ (INSTANCE ula_\|i2s_intf_\|mclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1675:1675:1675) (1695:1695:1695)) + (PORT clk (1702:1702:1702) (1723:1723:1723)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1392:1392:1392) (1374:1374:1374)) + (PORT clrn (1387:1387:1387) (1366:1366:1366)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52179,8 +54524,8 @@ (DELAY (ABSOLUTE (PORT clk (1332:1332:1332) (1349:1349:1349)) - (PORT d (2140:2140:2140) (2106:2106:2106)) - (PORT clrn (1565:1565:1565) (1601:1601:1601)) + (PORT d (867:867:867) (919:919:919)) + (PORT clrn (1555:1555:1555) (1589:1589:1589)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) ) @@ -52195,8 +54540,8 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~1) (DELAY (ABSOLUTE - (PORT dataa (636:636:636) (678:678:678)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (638:638:638) (665:665:665)) + (IOPATH datab cout (385:385:385) (280:280:280)) ) ) ) @@ -52205,7 +54550,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (228:228:228) (301:301:301)) + (PORT datab (228:228:228) (300:300:300)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -52219,10 +54564,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~2) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (250:250:250)) - (PORT datac (158:158:158) (190:190:190)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (189:189:189) (217:217:217)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -52231,9 +54576,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1674:1674:1674) (1694:1694:1694)) + (PORT clk (1677:1677:1677) (1697:1697:1697)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1391:1391:1391) (1373:1373:1373)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52247,7 +54592,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~4) (DELAY (ABSOLUTE - (PORT dataa (370:370:370) (423:423:423)) + (PORT dataa (371:371:371) (423:423:423)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -52261,8 +54606,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]\~8) (DELAY (ABSOLUTE - (PORT datad (304:304:304) (309:309:309)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datac (296:296:296) (302:302:302)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) @@ -52271,9 +54616,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1674:1674:1674) (1694:1694:1694)) + (PORT clk (1677:1677:1677) (1698:1698:1698)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1391:1391:1391) (1373:1373:1373)) + (PORT clrn (1387:1387:1387) (1366:1366:1366)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52287,9 +54632,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~6) (DELAY (ABSOLUTE - (PORT datab (365:365:365) (408:408:408)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (399:399:399) (445:445:445)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -52301,8 +54646,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]\~7) (DELAY (ABSOLUTE - (PORT datac (324:324:324) (326:326:326)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datad (522:522:522) (517:517:517)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -52311,9 +54656,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1674:1674:1674) (1695:1695:1695)) + (PORT clk (1702:1702:1702) (1723:1723:1723)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1392:1392:1392) (1374:1374:1374)) + (PORT clrn (1387:1387:1387) (1366:1366:1366)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52327,7 +54672,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~8) (DELAY (ABSOLUTE - (PORT datab (227:227:227) (301:301:301)) + (PORT datab (229:229:229) (302:302:302)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -52341,10 +54686,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~1) (DELAY (ABSOLUTE - (PORT dataa (211:211:211) (254:254:254)) - (PORT datac (156:156:156) (185:185:185)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datad (191:191:191) (216:216:216)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -52353,9 +54698,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1674:1674:1674) (1694:1694:1694)) + (PORT clk (1677:1677:1677) (1697:1697:1697)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1391:1391:1391) (1373:1373:1373)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52369,9 +54714,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~10) (DELAY (ABSOLUTE - (PORT datab (229:229:229) (301:301:301)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (411:411:411) (445:445:445)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -52383,7 +54728,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]\~6) (DELAY (ABSOLUTE - (PORT datad (160:160:160) (182:182:182)) + (PORT datad (293:293:293) (299:299:299)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -52393,9 +54738,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]) (DELAY (ABSOLUTE - (PORT clk (1674:1674:1674) (1694:1694:1694)) + (PORT clk (1677:1677:1677) (1698:1698:1698)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1391:1391:1391) (1373:1373:1373)) + (PORT clrn (1387:1387:1387) (1366:1366:1366)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52409,10 +54754,10 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (373:373:373) (424:424:424)) - (PORT datab (228:228:228) (302:302:302)) - (PORT datac (340:340:340) (382:382:382)) - (PORT datad (205:205:205) (268:268:268)) + (PORT dataa (370:370:370) (423:423:423)) + (PORT datab (227:227:227) (300:300:300)) + (PORT datac (359:359:359) (407:407:407)) + (PORT datad (362:362:362) (401:401:401)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -52425,9 +54770,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~12) (DELAY (ABSOLUTE - (PORT dataa (396:396:396) (438:438:438)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (399:399:399) (435:435:435)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -52439,7 +54784,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]\~5) (DELAY (ABSOLUTE - (PORT datad (316:316:316) (315:315:315)) + (PORT datad (306:306:306) (314:314:314)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -52449,9 +54794,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]) (DELAY (ABSOLUTE - (PORT clk (1674:1674:1674) (1695:1695:1695)) + (PORT clk (1677:1677:1677) (1698:1698:1698)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1392:1392:1392) (1374:1374:1374)) + (PORT clrn (1387:1387:1387) (1366:1366:1366)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52465,7 +54810,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~14) (DELAY (ABSOLUTE - (PORT dataa (411:411:411) (446:446:446)) + (PORT dataa (368:368:368) (420:420:420)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -52479,8 +54824,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]\~4) (DELAY (ABSOLUTE - (PORT datad (309:309:309) (315:315:315)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datac (313:313:313) (322:322:322)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) @@ -52489,9 +54834,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]) (DELAY (ABSOLUTE - (PORT clk (1674:1674:1674) (1694:1694:1694)) + (PORT clk (1677:1677:1677) (1698:1698:1698)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1391:1391:1391) (1373:1373:1373)) + (PORT clrn (1387:1387:1387) (1366:1366:1366)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52505,9 +54850,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~16) (DELAY (ABSOLUTE - (PORT dataa (371:371:371) (416:416:416)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (229:229:229) (301:301:301)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -52519,10 +54864,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~0) (DELAY (ABSOLUTE - (PORT datab (353:353:353) (353:353:353)) - (PORT datac (357:357:357) (365:365:365)) + (PORT datab (184:184:184) (217:217:217)) + (PORT datad (192:192:192) (217:217:217)) (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -52531,9 +54876,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[8\]) (DELAY (ABSOLUTE - (PORT clk (1674:1674:1674) (1695:1695:1695)) + (PORT clk (1677:1677:1677) (1697:1697:1697)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1392:1392:1392) (1374:1374:1374)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52547,7 +54892,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~18) (DELAY (ABSOLUTE - (PORT datad (353:353:353) (394:394:394)) + (PORT datad (352:352:352) (394:394:394)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) ) @@ -52558,8 +54903,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]\~3) (DELAY (ABSOLUTE - (PORT datad (314:314:314) (314:314:314)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datac (322:322:322) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) @@ -52568,9 +54913,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]) (DELAY (ABSOLUTE - (PORT clk (1674:1674:1674) (1695:1695:1695)) + (PORT clk (1676:1676:1676) (1696:1696:1696)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1392:1392:1392) (1374:1374:1374)) + (PORT clrn (1385:1385:1385) (1364:1364:1364)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52584,13 +54929,13 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (372:372:372) (418:418:418)) - (PORT datab (394:394:394) (432:432:432)) - (PORT datac (361:361:361) (405:405:405)) - (PORT datad (361:361:361) (398:398:398)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (370:370:370) (421:421:421)) + (PORT datab (393:393:393) (430:430:430)) + (PORT datac (199:199:199) (270:270:270)) + (PORT datad (364:364:364) (400:400:400)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -52600,10 +54945,10 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) + (PORT dataa (183:183:183) (220:220:220)) (PORT datab (225:225:225) (297:297:297)) - (PORT datac (606:606:606) (644:644:644)) - (PORT datad (162:162:162) (183:183:183)) + (PORT datac (294:294:294) (300:300:300)) + (PORT datad (603:603:603) (632:632:632)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -52611,30 +54956,20 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2feeder) - (DELAY - (ABSOLUTE - (PORT datad (180:180:180) (203:203:203)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1364:1364:1364)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1374:1374:1374)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT asdata (484:484:484) (510:510:510)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) ) ) (CELL @@ -52642,8 +54977,8 @@ (INSTANCE ula_\|i2s_intf_\|lrclk_r\~0) (DELAY (ABSOLUTE - (PORT datab (826:826:826) (840:840:840)) - (PORT datad (213:213:213) (274:274:274)) + (PORT datab (892:892:892) (897:897:897)) + (PORT datad (211:211:211) (271:271:271)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -52655,8 +54990,8 @@ (DELAY (ABSOLUTE (PORT clk (1330:1330:1330) (1348:1348:1348)) - (PORT d (2112:2112:2112) (2168:2168:2168)) - (PORT clrn (1563:1563:1563) (1599:1599:1599)) + (PORT d (1272:1272:1272) (1289:1289:1289)) + (PORT clrn (1553:1553:1553) (1587:1587:1587)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) ) @@ -52672,8 +55007,8 @@ (DELAY (ABSOLUTE (PORT clk (1331:1331:1331) (1348:1348:1348)) - (PORT d (2331:2331:2331) (2378:2378:2378)) - (PORT clrn (1564:1564:1564) (1600:1600:1600)) + (PORT d (1275:1275:1275) (1288:1288:1288)) + (PORT clrn (1554:1554:1554) (1588:1588:1588)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) ) @@ -52683,25 +55018,66 @@ (HOLD d (posedge clk) (86:86:86)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~18) + (DELAY + (ABSOLUTE + (PORT dataa (394:394:394) (404:404:404)) + (PORT datab (894:894:894) (902:902:902)) + (PORT datad (197:197:197) (228:228:228)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]\~5) (DELAY (ABSOLUTE - (PORT datab (225:225:225) (298:298:298)) + (PORT datab (229:229:229) (301:301:301)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datab cout (385:385:385) (280:280:280)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1feeder) + (DELAY + (ABSOLUTE + (PORT datac (175:175:175) (206:206:206)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1348:1348:1348) (1365:1365:1365)) + (PORT clk (1355:1355:1355) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1394:1394:1394) (1375:1375:1375)) + (PORT clrn (1391:1391:1391) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52715,12 +55091,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~15) (DELAY (ABSOLUTE - (PORT datab (208:208:208) (255:255:255)) - (PORT datac (805:805:805) (797:797:797)) - (PORT datad (220:220:220) (284:284:284)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (850:850:850) (855:855:855)) + (PORT datab (248:248:248) (329:329:329)) + (PORT datac (184:184:184) (219:219:219)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -52729,11 +55105,11 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]) (DELAY (ABSOLUTE - (PORT clk (1348:1348:1348) (1365:1365:1365)) + (PORT clk (1355:1355:1355) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (2512:2512:2512) (2492:2492:2492)) - (PORT clrn (1394:1394:1394) (1375:1375:1375)) - (PORT sload (1349:1349:1349) (1372:1372:1372)) + (PORT asdata (511:511:511) (549:549:549)) + (PORT clrn (1391:1391:1391) (1369:1369:1369)) + (PORT sload (1375:1375:1375) (1412:1412:1412)) (PORT ena (716:716:716) (714:714:714)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) @@ -52751,7 +55127,7 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]\~7) (DELAY (ABSOLUTE - (PORT datab (226:226:226) (297:297:297)) + (PORT datab (229:229:229) (301:301:301)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -52765,11 +55141,11 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]) (DELAY (ABSOLUTE - (PORT clk (1348:1348:1348) (1365:1365:1365)) + (PORT clk (1355:1355:1355) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (2511:2511:2511) (2491:2491:2491)) - (PORT clrn (1394:1394:1394) (1375:1375:1375)) - (PORT sload (1349:1349:1349) (1372:1372:1372)) + (PORT asdata (511:511:511) (550:550:550)) + (PORT clrn (1391:1391:1391) (1369:1369:1369)) + (PORT sload (1375:1375:1375) (1412:1412:1412)) (PORT ena (716:716:716) (714:714:714)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) @@ -52787,7 +55163,7 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]\~9) (DELAY (ABSOLUTE - (PORT datab (227:227:227) (298:298:298)) + (PORT datab (228:228:228) (302:302:302)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -52801,11 +55177,11 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]) (DELAY (ABSOLUTE - (PORT clk (1348:1348:1348) (1365:1365:1365)) + (PORT clk (1355:1355:1355) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (2510:2510:2510) (2491:2491:2491)) - (PORT clrn (1394:1394:1394) (1375:1375:1375)) - (PORT sload (1349:1349:1349) (1372:1372:1372)) + (PORT asdata (509:509:509) (545:545:545)) + (PORT clrn (1391:1391:1391) (1369:1369:1369)) + (PORT sload (1375:1375:1375) (1412:1412:1412)) (PORT ena (716:716:716) (714:714:714)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) @@ -52823,9 +55199,9 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]\~11) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (307:307:307)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (241:241:241) (311:311:311)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -52837,11 +55213,44 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]) (DELAY (ABSOLUTE - (PORT clk (1348:1348:1348) (1365:1365:1365)) + (PORT clk (1355:1355:1355) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (2510:2510:2510) (2490:2490:2490)) - (PORT clrn (1394:1394:1394) (1375:1375:1375)) - (PORT sload (1349:1349:1349) (1372:1372:1372)) + (PORT asdata (509:509:509) (546:546:546)) + (PORT clrn (1391:1391:1391) (1369:1369:1369)) + (PORT sload (1375:1375:1375) (1412:1412:1412)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (323:323:323)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH cin combout (408:408:408) (387:387:387)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (510:510:510) (548:548:548)) + (PORT clrn (1391:1391:1391) (1369:1369:1369)) + (PORT sload (1375:1375:1375) (1412:1412:1412)) (PORT ena (716:716:716) (714:714:714)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) @@ -52859,56 +55268,39 @@ (INSTANCE ula_\|i2s_intf_\|LessThan0\~0) (DELAY (ABSOLUTE - (PORT dataa (229:229:229) (306:306:306)) - (PORT datab (229:229:229) (302:302:302)) - (PORT datac (201:201:201) (272:272:272)) - (PORT datad (205:205:205) (267:267:267)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (380:380:380) (422:422:422)) + (PORT datab (227:227:227) (299:299:299)) + (PORT datac (200:200:200) (270:270:270)) + (PORT datad (203:203:203) (264:264:264)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]\~1) (DELAY (ABSOLUTE - (PORT datab (241:241:241) (318:318:318)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH cin combout (408:408:408) (387:387:387)) + (PORT dataa (356:356:356) (411:411:411)) + (PORT datab (514:514:514) (502:502:502)) + (PORT datac (214:214:214) (292:292:292)) + (PORT datad (172:172:172) (199:199:199)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1365:1365:1365)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (2509:2509:2509) (2490:2490:2490)) - (PORT clrn (1394:1394:1394) (1375:1375:1375)) - (PORT sload (1349:1349:1349) (1372:1372:1372)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|Add2\~7) (DELAY (ABSOLUTE - (PORT dataa (427:427:427) (477:477:477)) + (PORT dataa (389:389:389) (452:452:452)) (IOPATH dataa cout (376:376:376) (275:275:275)) ) ) @@ -52918,9 +55310,9 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~8) (DELAY (ABSOLUTE - (PORT dataa (231:231:231) (308:308:308)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (229:229:229) (302:302:302)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -52932,13 +55324,13 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~20) (DELAY (ABSOLUTE - (PORT dataa (429:429:429) (479:479:479)) - (PORT datab (826:826:826) (840:840:840)) - (PORT datac (184:184:184) (220:220:220)) - (PORT datad (160:160:160) (182:182:182)) + (PORT dataa (391:391:391) (449:449:449)) + (PORT datab (896:896:896) (902:902:902)) + (PORT datac (295:295:295) (298:298:298)) + (PORT datad (196:196:196) (227:227:227)) (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -52948,9 +55340,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1364:1364:1364)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1374:1374:1374)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52964,9 +55356,9 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~10) (DELAY (ABSOLUTE - (PORT dataa (373:373:373) (418:418:418)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (534:534:534) (565:565:565)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -52978,12 +55370,12 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~17) (DELAY (ABSOLUTE - (PORT dataa (207:207:207) (259:259:259)) - (PORT datab (208:208:208) (257:257:257)) - (PORT datac (805:805:805) (799:799:799)) - (PORT datad (315:315:315) (317:317:317)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (395:395:395) (405:405:405)) + (PORT datab (892:892:892) (904:904:904)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (306:306:306) (314:314:314)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -52994,9 +55386,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1348:1348:1348) (1365:1365:1365)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1394:1394:1394) (1375:1375:1375)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53010,7 +55402,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~12) (DELAY (ABSOLUTE - (PORT datab (229:229:229) (304:304:304)) + (PORT datab (228:228:228) (298:298:298)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -53024,12 +55416,12 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~19) (DELAY (ABSOLUTE - (PORT dataa (430:430:430) (479:479:479)) - (PORT datab (827:827:827) (841:841:841)) - (PORT datac (185:185:185) (221:221:221)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) + (PORT dataa (393:393:393) (453:453:453)) + (PORT datab (183:183:183) (217:217:217)) + (PORT datac (815:815:815) (808:808:808)) + (PORT datad (199:199:199) (230:230:230)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -53040,9 +55432,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1364:1364:1364)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1374:1374:1374)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53056,7 +55448,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~14) (DELAY (ABSOLUTE - (PORT datad (336:336:336) (373:373:373)) + (PORT datad (208:208:208) (270:270:270)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) ) @@ -53067,12 +55459,12 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~16) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (260:260:260)) - (PORT datab (208:208:208) (260:260:260)) - (PORT datac (805:805:805) (800:800:800)) - (PORT datad (316:316:316) (317:317:317)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (393:393:393) (403:403:403)) + (PORT datab (894:894:894) (902:902:902)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (308:308:308) (315:315:315)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -53083,9 +55475,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1348:1348:1348) (1365:1365:1365)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1394:1394:1394) (1375:1375:1375)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53099,72 +55491,25 @@ (INSTANCE ula_\|i2s_intf_\|Equal1\~0) (DELAY (ABSOLUTE - (PORT dataa (231:231:231) (309:309:309)) - (PORT datab (229:229:229) (303:303:303)) - (PORT datac (345:345:345) (385:385:385)) - (PORT datad (335:335:335) (371:371:371)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (315:315:315)) - (PORT datab (195:195:195) (237:237:237)) - (PORT datac (215:215:215) (292:292:292)) - (PORT datad (350:350:350) (354:354:354)) + (PORT dataa (228:228:228) (302:302:302)) + (PORT datab (226:226:226) (298:298:298)) + (PORT datac (201:201:201) (270:270:270)) + (PORT datad (511:511:511) (533:533:533)) (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~18) - (DELAY - (ABSOLUTE - (PORT dataa (834:834:834) (831:831:831)) - (PORT datab (208:208:208) (258:258:258)) - (PORT datad (352:352:352) (355:355:355)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1365:1365:1365)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1394:1394:1394) (1375:1375:1375)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|Equal1\~1) (DELAY (ABSOLUTE - (PORT datac (358:358:358) (401:401:401)) - (PORT datad (348:348:348) (351:351:351)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datab (225:225:225) (265:265:265)) + (PORT datad (368:368:368) (413:413:413)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53174,10 +55519,10 @@ (INSTANCE ula_\|i2s_intf_\|bclk_r\~0) (DELAY (ABSOLUTE - (PORT datab (195:195:195) (237:237:237)) - (PORT datac (213:213:213) (291:291:291)) - (PORT datad (217:217:217) (281:281:281)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (PORT dataa (198:198:198) (240:240:240)) + (PORT datac (216:216:216) (295:295:295)) + (PORT datad (223:223:223) (297:297:297)) + (IOPATH dataa combout (307:307:307) (306:306:306)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -53188,12 +55533,13 @@ (INSTANCE ula_\|i2s_intf_\|bclk_r\~1) (DELAY (ABSOLUTE - (PORT dataa (207:207:207) (258:258:258)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datad (799:799:799) (786:786:786)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (509:509:509) (505:505:505)) + (PORT datab (246:246:246) (327:327:327)) + (PORT datac (822:822:822) (824:824:824)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53204,8 +55550,8 @@ (DELAY (ABSOLUTE (PORT clk (1330:1330:1330) (1347:1347:1347)) - (PORT d (2095:2095:2095) (2177:2177:2177)) - (PORT clrn (1562:1562:1562) (1599:1599:1599)) + (PORT d (1369:1369:1369) (1409:1409:1409)) + (PORT clrn (1552:1552:1552) (1587:1587:1587)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) ) @@ -53220,7 +55566,7 @@ (INSTANCE ula_\|pcm_outl\[13\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (795:795:795) (814:814:814)) + (PORT datad (862:862:862) (880:880:880)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53230,12 +55576,12 @@ (INSTANCE ula_\|always0\~2) (DELAY (ABSOLUTE - (PORT dataa (1624:1624:1624) (1662:1662:1662)) - (PORT datab (1477:1477:1477) (1531:1531:1531)) - (PORT datac (1100:1100:1100) (1115:1115:1115)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datab (1728:1728:1728) (1814:1814:1814)) + (PORT datac (2848:2848:2848) (2969:2969:2969)) + (PORT datad (2391:2391:2391) (2369:2369:2369)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -53244,13 +55590,13 @@ (INSTANCE ula_\|always0\~3) (DELAY (ABSOLUTE - (PORT dataa (634:634:634) (680:680:680)) - (PORT datab (1157:1157:1157) (1194:1194:1194)) - (PORT datac (1107:1107:1107) (1125:1125:1125)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (2375:2375:2375) (2516:2516:2516)) + (PORT datab (1137:1137:1137) (1186:1186:1186)) + (PORT datac (1944:1944:1944) (1968:1968:1968)) + (PORT datad (1020:1020:1020) (970:970:970)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53262,7 +55608,7 @@ (ABSOLUTE (PORT clk (1344:1344:1344) (1362:1362:1362)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1849:1849:1849) (1846:1846:1846)) + (PORT ena (910:910:910) (910:910:910)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -53276,12 +55622,12 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~19) (DELAY (ABSOLUTE - (PORT dataa (206:206:206) (254:254:254)) - (PORT datab (194:194:194) (234:234:234)) - (PORT datac (215:215:215) (292:292:292)) - (PORT datad (219:219:219) (283:283:283)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT dataa (514:514:514) (511:511:511)) + (PORT datab (249:249:249) (334:334:334)) + (PORT datac (218:218:218) (296:296:296)) + (PORT datad (173:173:173) (201:201:201)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -53301,11 +55647,11 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~20) (DELAY (ABSOLUTE - (PORT dataa (1260:1260:1260) (1257:1257:1257)) - (PORT datab (1218:1218:1218) (1254:1254:1254)) - (PORT datad (705:705:705) (672:672:672)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT dataa (899:899:899) (933:933:933)) + (PORT datab (531:531:531) (514:514:514)) + (PORT datad (693:693:693) (657:657:657)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -53316,9 +55662,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (1658:1658:1658) (1671:1671:1671)) + (PORT clk (1686:1686:1686) (1709:1709:1709)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) + (PORT clrn (1393:1393:1393) (1371:1371:1371)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53332,24 +55678,24 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~18) (DELAY (ABSOLUTE - (PORT datab (223:223:223) (291:291:291)) - (PORT datad (1171:1171:1171) (1205:1205:1205)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT datac (847:847:847) (868:868:868)) + (PORT datad (201:201:201) (259:259:259)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~2) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]\~2) (DELAY (ABSOLUTE - (PORT datab (207:207:207) (255:255:255)) - (PORT datac (805:805:805) (796:796:796)) - (PORT datad (220:220:220) (284:284:284)) - (IOPATH datab combout (273:273:273) (275:275:275)) + (PORT dataa (847:847:847) (857:857:857)) + (PORT datab (249:249:249) (333:333:333)) + (PORT datac (182:182:182) (216:216:216)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -53358,10 +55704,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1363:1363:1363) (1385:1385:1385)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1393:1393:1393) (1371:1371:1371)) + (PORT ena (1270:1270:1270) (1221:1221:1221)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53376,9 +55722,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~17) (DELAY (ABSOLUTE - (PORT datac (196:196:196) (263:263:263)) - (PORT datad (1171:1171:1171) (1213:1213:1213)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT datac (866:866:866) (887:887:887)) + (PORT datad (200:200:200) (257:257:257)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53388,10 +55734,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[2\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1363:1363:1363) (1385:1385:1385)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1393:1393:1393) (1371:1371:1371)) + (PORT ena (1270:1270:1270) (1221:1221:1221)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53406,10 +55752,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~16) (DELAY (ABSOLUTE - (PORT datab (223:223:223) (293:293:293)) - (PORT datad (1179:1179:1179) (1213:1213:1213)) + (PORT datab (224:224:224) (293:293:293)) + (PORT datac (861:861:861) (883:883:883)) (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) @@ -53418,10 +55764,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[3\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1363:1363:1363) (1385:1385:1385)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1393:1393:1393) (1371:1371:1371)) + (PORT ena (1270:1270:1270) (1221:1221:1221)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53436,9 +55782,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~15) (DELAY (ABSOLUTE - (PORT datab (224:224:224) (294:294:294)) - (PORT datad (1188:1188:1188) (1224:1224:1224)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT datac (845:845:845) (878:878:878)) + (PORT datad (199:199:199) (255:255:255)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53448,10 +55794,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1363:1363:1363) (1385:1385:1385)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1393:1393:1393) (1371:1371:1371)) + (PORT ena (1270:1270:1270) (1221:1221:1221)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53466,10 +55812,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~14) (DELAY (ABSOLUTE - (PORT datab (223:223:223) (293:293:293)) - (PORT datad (1187:1187:1187) (1223:1223:1223)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT dataa (225:225:225) (299:299:299)) + (PORT datac (867:867:867) (889:889:889)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) @@ -53478,10 +55824,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1363:1363:1363) (1385:1385:1385)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1393:1393:1393) (1371:1371:1371)) + (PORT ena (1270:1270:1270) (1221:1221:1221)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53496,9 +55842,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~13) (DELAY (ABSOLUTE - (PORT dataa (225:225:225) (298:298:298)) - (PORT datad (1181:1181:1181) (1219:1219:1219)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT datac (859:859:859) (872:872:872)) + (PORT datad (200:200:200) (258:258:258)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53508,10 +55854,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1363:1363:1363) (1385:1385:1385)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1393:1393:1393) (1371:1371:1371)) + (PORT ena (1270:1270:1270) (1221:1221:1221)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53526,9 +55872,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~12) (DELAY (ABSOLUTE - (PORT datab (223:223:223) (292:292:292)) - (PORT datad (1168:1168:1168) (1206:1206:1206)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT datac (866:866:866) (893:893:893)) + (PORT datad (200:200:200) (256:256:256)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53538,10 +55884,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1363:1363:1363) (1385:1385:1385)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1393:1393:1393) (1371:1371:1371)) + (PORT ena (1270:1270:1270) (1221:1221:1221)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53556,10 +55902,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~11) (DELAY (ABSOLUTE - (PORT datac (195:195:195) (262:262:262)) - (PORT datad (1169:1169:1169) (1206:1206:1206)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datab (222:222:222) (291:291:291)) + (PORT datac (868:868:868) (891:891:891)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) @@ -53568,10 +55914,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1363:1363:1363) (1385:1385:1385)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1393:1393:1393) (1371:1371:1371)) + (PORT ena (1270:1270:1270) (1221:1221:1221)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53586,9 +55932,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~10) (DELAY (ABSOLUTE - (PORT datab (223:223:223) (292:292:292)) - (PORT datad (1170:1170:1170) (1215:1215:1215)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT datac (867:867:867) (894:894:894)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53598,10 +55944,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[9\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1363:1363:1363) (1385:1385:1385)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1393:1393:1393) (1371:1371:1371)) + (PORT ena (1270:1270:1270) (1221:1221:1221)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53616,10 +55962,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~9) (DELAY (ABSOLUTE - (PORT datac (198:198:198) (265:265:265)) - (PORT datad (1186:1186:1186) (1225:1225:1225)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datab (223:223:223) (293:293:293)) + (PORT datac (867:867:867) (889:889:889)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) @@ -53628,10 +55974,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[10\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1363:1363:1363) (1385:1385:1385)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1393:1393:1393) (1371:1371:1371)) + (PORT ena (1270:1270:1270) (1221:1221:1221)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53646,9 +55992,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~8) (DELAY (ABSOLUTE - (PORT dataa (224:224:224) (297:297:297)) - (PORT datad (1188:1188:1188) (1223:1223:1223)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT datac (869:869:869) (892:892:892)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53658,10 +56004,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[11\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1363:1363:1363) (1385:1385:1385)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1393:1393:1393) (1371:1371:1371)) + (PORT ena (1270:1270:1270) (1221:1221:1221)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53676,9 +56022,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~7) (DELAY (ABSOLUTE - (PORT datab (223:223:223) (292:292:292)) - (PORT datad (1185:1185:1185) (1226:1226:1226)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT datac (846:846:846) (867:867:867)) + (PORT datad (201:201:201) (259:259:259)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53688,10 +56034,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[12\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1363:1363:1363) (1385:1385:1385)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1393:1393:1393) (1371:1371:1371)) + (PORT ena (1270:1270:1270) (1221:1221:1221)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53706,9 +56052,9 @@ (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1297:1297:1297) (1331:1331:1331)) - (PORT datab (821:821:821) (835:835:835)) - (PORT datad (212:212:212) (272:272:272)) + (PORT dataa (423:423:423) (468:468:468)) + (PORT datab (894:894:894) (905:905:905)) + (PORT datad (214:214:214) (277:277:277)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -53721,9 +56067,9 @@ (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1364:1364:1364)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1374:1374:1374)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53737,9 +56083,9 @@ (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1296:1296:1296) (1330:1330:1330)) - (PORT datab (821:821:821) (835:835:835)) - (PORT datad (212:212:212) (272:272:272)) + (PORT dataa (423:423:423) (468:468:468)) + (PORT datab (893:893:893) (905:905:905)) + (PORT datad (214:214:214) (276:276:276)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -53752,9 +56098,9 @@ (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1364:1364:1364)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1374:1374:1374)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53768,9 +56114,9 @@ (INSTANCE ula_\|pcm_outr\~0) (DELAY (ABSOLUTE - (PORT datac (198:198:198) (266:266:266)) - (PORT datad (200:200:200) (258:258:258)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (224:224:224) (297:297:297)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53780,9 +56126,9 @@ (INSTANCE ula_\|pcm_outl\[12\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1365:1365:1365)) + (PORT clk (1348:1348:1348) (1365:1365:1365)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1939:1939:1939) (1935:1935:1935)) + (PORT ena (2727:2727:2727) (2696:2696:2696)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -53796,11 +56142,11 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~6) (DELAY (ABSOLUTE - (PORT datab (1224:1224:1224) (1262:1262:1262)) - (PORT datac (197:197:197) (264:264:264)) - (PORT datad (1242:1242:1242) (1258:1258:1258)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (224:224:224) (298:298:298)) + (PORT datac (858:858:858) (874:874:874)) + (PORT datad (337:337:337) (378:378:378)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53810,10 +56156,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[13\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1363:1363:1363) (1385:1385:1385)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1393:1393:1393) (1371:1371:1371)) + (PORT ena (1270:1270:1270) (1221:1221:1221)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53828,10 +56174,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~5) (DELAY (ABSOLUTE - (PORT datab (1134:1134:1134) (1192:1192:1192)) - (PORT datac (196:196:196) (262:262:262)) - (PORT datad (1187:1187:1187) (1227:1227:1227)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT datab (1308:1308:1308) (1326:1326:1326)) + (PORT datac (848:848:848) (868:868:868)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -53842,10 +56188,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[14\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1363:1363:1363) (1385:1385:1385)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1393:1393:1393) (1371:1371:1371)) + (PORT ena (1270:1270:1270) (1221:1221:1221)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53855,14 +56201,24 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|pcm_outl\[14\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (553:553:553) (541:541:541)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|pcm_outl\[14\]) (DELAY (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT clk (1344:1344:1344) (1362:1362:1362)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (2079:2079:2079) (2031:2031:2031)) + (PORT ena (910:910:910) (910:910:910)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -53876,9 +56232,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~4) (DELAY (ABSOLUTE - (PORT dataa (1121:1121:1121) (1163:1163:1163)) - (PORT datac (903:903:903) (960:960:960)) - (PORT datad (609:609:609) (605:605:605)) + (PORT dataa (242:242:242) (315:315:315)) + (PORT datac (846:846:846) (876:876:876)) + (PORT datad (1384:1384:1384) (1435:1435:1435)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -53890,10 +56246,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[15\]) (DELAY (ABSOLUTE - (PORT clk (1679:1679:1679) (1704:1704:1704)) + (PORT clk (1363:1363:1363) (1385:1385:1385)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1395:1395:1395) (1376:1376:1376)) - (PORT ena (1059:1059:1059) (1025:1025:1025)) + (PORT clrn (1393:1393:1393) (1371:1371:1371)) + (PORT ena (1270:1270:1270) (1221:1221:1221)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53908,9 +56264,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~3) (DELAY (ABSOLUTE - (PORT datac (196:196:196) (262:262:262)) - (PORT datad (610:610:610) (609:609:609)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT datab (581:581:581) (579:579:579)) + (PORT datad (617:617:617) (641:641:641)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53920,10 +56276,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[16\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1366:1366:1366)) + (PORT clk (1687:1687:1687) (1712:1712:1712)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1395:1395:1395) (1376:1376:1376)) - (PORT ena (1094:1094:1094) (1068:1068:1068)) + (PORT clrn (1389:1389:1389) (1367:1367:1367)) + (PORT ena (1327:1327:1327) (1282:1282:1282)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53938,9 +56294,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~0) (DELAY (ABSOLUTE - (PORT datab (221:221:221) (290:290:290)) - (PORT datad (606:606:606) (607:607:607)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT datab (578:578:578) (579:579:579)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53951,9 +56307,9 @@ (DELAY (ABSOLUTE (PORT clk (1334:1334:1334) (1351:1351:1351)) - (PORT d (1371:1371:1371) (1418:1418:1418)) - (PORT clrn (1567:1567:1567) (1603:1603:1603)) - (PORT ena (1582:1582:1582) (1591:1591:1591)) + (PORT d (1040:1040:1040) (1074:1074:1074)) + (PORT clrn (1557:1557:1557) (1591:1591:1591)) + (PORT ena (793:793:793) (769:769:769)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) ) @@ -53967,106 +56323,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan2\~0) + (INSTANCE ula_\|border\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (264:264:264) (341:341:341)) - (PORT datab (246:246:246) (316:316:316)) - (PORT datac (236:236:236) (305:305:305)) - (PORT datad (222:222:222) (283:283:283)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (239:239:239) (310:310:310)) - (PORT datab (237:237:237) (305:305:305)) - (PORT datac (230:230:230) (298:298:298)) - (PORT datad (216:216:216) (274:274:274)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (479:479:479)) - (PORT datab (244:244:244) (316:316:316)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (337:337:337) (335:335:335)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (265:265:265) (343:343:343)) - (PORT datab (220:220:220) (254:254:254)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (246:246:246) (323:323:323)) - (PORT datab (238:238:238) (306:306:306)) - (PORT datad (224:224:224) (287:287:287)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|disp_enable\~0) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (385:385:385) (430:430:430)) - (PORT datad (608:608:608) (642:642:642)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|disp_enable\~1) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (236:236:236)) - (PORT datab (189:189:189) (227:227:227)) - (PORT datad (324:324:324) (328:328:328)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT datad (1072:1072:1072) (1068:1068:1068)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54076,28 +56336,44 @@ (INSTANCE ula_\|border\[1\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1365:1365:1365)) - (PORT asdata (485:485:485) (512:512:512)) - (PORT ena (1939:1939:1939) (1935:1935:1935)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1647:1647:1647) (1622:1622:1622)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) + (HOLD d (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (333:333:333)) + (PORT datab (237:237:237) (306:306:306)) + (PORT datac (211:211:211) (277:277:277)) + (PORT datad (214:214:214) (271:271:271)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|LessThan6\~1) (DELAY (ABSOLUTE - (PORT dataa (421:421:421) (479:479:479)) - (PORT datab (429:429:429) (487:487:487)) - (PORT datac (394:394:394) (447:447:447)) - (PORT datad (384:384:384) (395:395:395)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (258:258:258) (331:331:331)) + (PORT datab (256:256:256) (326:326:326)) + (PORT datac (370:370:370) (406:406:406)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -54108,11 +56384,11 @@ (INSTANCE ula_\|video_\|LessThan4\~0) (DELAY (ABSOLUTE - (PORT dataa (246:246:246) (322:322:322)) - (PORT datab (248:248:248) (320:320:320)) + (PORT dataa (413:413:413) (452:452:452)) + (PORT datab (246:246:246) (317:317:317)) (PORT datad (214:214:214) (271:271:271)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -54123,13 +56399,13 @@ (INSTANCE ula_\|video_\|screen_en\~0) (DELAY (ABSOLUTE - (PORT dataa (412:412:412) (463:463:463)) - (PORT datab (426:426:426) (480:480:480)) - (PORT datac (508:508:508) (501:501:501)) - (PORT datad (602:602:602) (632:632:632)) + (PORT dataa (386:386:386) (451:451:451)) + (PORT datab (632:632:632) (650:650:650)) + (PORT datac (567:567:567) (589:589:589)) + (PORT datad (482:482:482) (467:467:467)) (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54139,10 +56415,10 @@ (INSTANCE ula_\|video_\|screen_en\~1) (DELAY (ABSOLUTE - (PORT dataa (640:640:640) (667:667:667)) - (PORT datab (450:450:450) (495:495:495)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (160:160:160) (180:180:180)) + (PORT dataa (252:252:252) (329:329:329)) + (PORT datab (262:262:262) (333:333:333)) + (PORT datac (322:322:322) (324:324:324)) + (PORT datad (159:159:159) (180:180:180)) (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -54152,10 +56428,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) + (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1363:1363:1363) (1338:1338:1338)) + (PORT datad (841:841:841) (826:826:826)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54165,25 +56441,25 @@ (INSTANCE ula_\|video_\|Decoder0\~1) (DELAY (ABSOLUTE - (PORT dataa (1152:1152:1152) (1187:1187:1187)) - (PORT datab (893:893:893) (951:951:951)) - (PORT datac (887:887:887) (938:938:938)) - (PORT datad (256:256:256) (324:324:324)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (415:415:415) (491:491:491)) + (PORT datab (900:900:900) (926:926:926)) + (PORT datac (639:639:639) (679:679:679)) + (PORT datad (687:687:687) (719:719:719)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]) + (INSTANCE ula_\|video_\|attr_prefetch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1725:1725:1725) (1744:1744:1744)) + (PORT clk (1694:1694:1694) (1714:1714:1714)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1341:1341:1341) (1316:1316:1316)) + (PORT ena (1119:1119:1119) (1089:1089:1089)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54197,10 +56473,10 @@ (INSTANCE ula_\|video_\|Decoder0\~0) (DELAY (ABSOLUTE - (PORT dataa (1153:1153:1153) (1187:1187:1187)) - (PORT datab (894:894:894) (950:950:950)) - (PORT datac (887:887:887) (937:937:937)) - (PORT datad (256:256:256) (325:325:325)) + (PORT dataa (412:412:412) (488:488:488)) + (PORT datab (896:896:896) (921:921:921)) + (PORT datac (639:639:639) (681:681:681)) + (PORT datad (684:684:684) (714:714:714)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -54208,98 +56484,14 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1372:1372:1372)) - (PORT asdata (1649:1649:1649) (1651:1651:1651)) - (PORT ena (1303:1303:1303) (1280:1280:1280)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1431:1431:1431) (1390:1390:1390)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1725:1725:1725) (1744:1744:1744)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1341:1341:1341) (1316:1316:1316)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1372:1372:1372)) - (PORT asdata (929:929:929) (964:964:964)) - (PORT ena (1303:1303:1303) (1280:1280:1280)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1117:1117:1117) (1124:1124:1124)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1725:1725:1725) (1744:1744:1744)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1341:1341:1341) (1316:1316:1316)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|attr\[7\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) - (PORT asdata (927:927:927) (957:957:957)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) + (PORT clk (1361:1361:1361) (1378:1378:1378)) + (PORT asdata (1059:1059:1059) (1073:1073:1073)) + (PORT ena (1120:1120:1120) (1090:1090:1090)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54313,9 +56505,10 @@ (INSTANCE ula_\|video_\|frame\[0\]\~12) (DELAY (ABSOLUTE - (PORT dataa (577:577:577) (563:563:563)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT datab (1087:1087:1087) (1064:1064:1064)) + (PORT datad (205:205:205) (266:266:266)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -54324,13 +56517,13 @@ (INSTANCE ula_\|video_\|frame\[0\]) (DELAY (ABSOLUTE - (PORT clk (1360:1360:1360) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) + (PORT clk (1662:1662:1662) (1675:1675:1675)) + (PORT asdata (468:468:468) (494:494:494)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) ) ) (CELL @@ -54338,8 +56531,8 @@ (INSTANCE ula_\|video_\|frame\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (568:568:568) (589:589:589)) - (PORT datab (222:222:222) (290:290:290)) + (PORT dataa (360:360:360) (405:405:405)) + (PORT datab (229:229:229) (300:300:300)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datab combout (306:306:306) (324:324:324)) @@ -54353,9 +56546,9 @@ (INSTANCE ula_\|video_\|frame\[1\]) (DELAY (ABSOLUTE - (PORT clk (1359:1359:1359) (1375:1375:1375)) + (PORT clk (1358:1358:1358) (1374:1374:1374)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1137:1137:1137) (1114:1114:1114)) + (PORT ena (1617:1617:1617) (1564:1564:1564)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54369,9 +56562,9 @@ (INSTANCE ula_\|video_\|frame\[2\]\~6) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (295:295:295)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (222:222:222) (291:291:291)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -54383,9 +56576,9 @@ (INSTANCE ula_\|video_\|frame\[2\]) (DELAY (ABSOLUTE - (PORT clk (1359:1359:1359) (1375:1375:1375)) + (PORT clk (1358:1358:1358) (1374:1374:1374)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1137:1137:1137) (1114:1114:1114)) + (PORT ena (1617:1617:1617) (1564:1564:1564)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54399,7 +56592,7 @@ (INSTANCE ula_\|video_\|frame\[3\]\~8) (DELAY (ABSOLUTE - (PORT datab (221:221:221) (290:290:290)) + (PORT datab (222:222:222) (291:291:291)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -54413,9 +56606,9 @@ (INSTANCE ula_\|video_\|frame\[3\]) (DELAY (ABSOLUTE - (PORT clk (1359:1359:1359) (1375:1375:1375)) + (PORT clk (1358:1358:1358) (1374:1374:1374)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1137:1137:1137) (1114:1114:1114)) + (PORT ena (1617:1617:1617) (1564:1564:1564)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54429,8 +56622,8 @@ (INSTANCE ula_\|video_\|frame\[4\]\~10) (DELAY (ABSOLUTE - (PORT dataa (241:241:241) (315:315:315)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT datad (359:359:359) (390:390:390)) + (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) ) ) @@ -54440,14 +56633,14 @@ (INSTANCE ula_\|video_\|frame\[4\]) (DELAY (ABSOLUTE - (PORT clk (1359:1359:1359) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1137:1137:1137) (1114:1114:1114)) + (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT asdata (605:605:605) (603:603:603)) + (PORT ena (1617:1617:1617) (1564:1564:1564)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) @@ -54456,7 +56649,7 @@ (INSTANCE ula_\|video_\|inverted) (DELAY (ABSOLUTE - (PORT datad (346:346:346) (380:380:380)) + (PORT datad (622:622:622) (639:639:639)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -54467,7 +56660,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1072:1072:1072) (1077:1077:1077)) + (PORT datad (994:994:994) (968:968:968)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54477,13 +56670,13 @@ (INSTANCE ula_\|video_\|Decoder0\~2) (DELAY (ABSOLUTE - (PORT dataa (1153:1153:1153) (1184:1184:1184)) - (PORT datab (895:895:895) (950:950:950)) - (PORT datac (886:886:886) (939:939:939)) - (PORT datad (254:254:254) (323:323:323)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (413:413:413) (488:488:488)) + (PORT datab (898:898:898) (923:923:923)) + (PORT datac (641:641:641) (681:681:681)) + (PORT datad (686:686:686) (717:717:717)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54493,9 +56686,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1697:1697:1697) (1712:1712:1712)) + (PORT clk (1666:1666:1666) (1677:1677:1677)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1345:1345:1345) (1319:1319:1319)) + (PORT ena (1120:1120:1120) (1099:1099:1099)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54504,29 +56697,19 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (568:568:568) (601:601:601)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits\[6\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) + (PORT clk (1361:1361:1361) (1378:1378:1378)) + (PORT asdata (1213:1213:1213) (1239:1239:1239)) + (PORT ena (1120:1120:1120) (1090:1090:1090)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) @@ -54535,7 +56718,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1430:1430:1430) (1388:1388:1388)) + (PORT datad (1320:1320:1320) (1304:1304:1304)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54545,9 +56728,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1697:1697:1697) (1712:1712:1712)) + (PORT clk (1666:1666:1666) (1677:1677:1677)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1345:1345:1345) (1319:1319:1319)) + (PORT ena (1120:1120:1120) (1099:1099:1099)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54561,9 +56744,9 @@ (INSTANCE ula_\|video_\|bits\[4\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) - (PORT asdata (915:915:915) (943:943:943)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) + (PORT clk (1361:1361:1361) (1378:1378:1378)) + (PORT asdata (888:888:888) (933:933:933)) + (PORT ena (1120:1120:1120) (1090:1090:1090)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54577,7 +56760,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (876:876:876) (871:871:871)) + (PORT datad (869:869:869) (866:866:866)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54587,9 +56770,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1697:1697:1697) (1712:1712:1712)) + (PORT clk (1666:1666:1666) (1677:1677:1677)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1345:1345:1345) (1319:1319:1319)) + (PORT ena (1120:1120:1120) (1099:1099:1099)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54603,7 +56786,7 @@ (INSTANCE ula_\|video_\|bits\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (600:600:600) (633:633:633)) + (PORT datad (602:602:602) (641:641:641)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54613,9 +56796,9 @@ (INSTANCE ula_\|video_\|bits\[5\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT clk (1361:1361:1361) (1378:1378:1378)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) + (PORT ena (1120:1120:1120) (1090:1090:1090)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54629,7 +56812,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1123:1123:1123) (1128:1128:1128)) + (PORT datad (838:838:838) (824:824:824)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54639,9 +56822,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1697:1697:1697) (1712:1712:1712)) + (PORT clk (1666:1666:1666) (1677:1677:1677)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1345:1345:1345) (1319:1319:1319)) + (PORT ena (1120:1120:1120) (1099:1099:1099)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54655,9 +56838,9 @@ (INSTANCE ula_\|video_\|bits\[7\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) - (PORT asdata (1123:1123:1123) (1142:1142:1142)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) + (PORT clk (1361:1361:1361) (1378:1378:1378)) + (PORT asdata (916:916:916) (947:947:947)) + (PORT ena (1120:1120:1120) (1090:1090:1090)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54671,11 +56854,11 @@ (INSTANCE ula_\|video_\|Mux0\~0) (DELAY (ABSOLUTE - (PORT dataa (362:362:362) (409:409:409)) - (PORT datab (258:258:258) (340:340:340)) - (PORT datad (592:592:592) (624:624:624)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (278:278:278) (367:367:367)) + (PORT datab (220:220:220) (289:289:289)) + (PORT datad (352:352:352) (387:387:387)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -54686,9 +56869,9 @@ (INSTANCE ula_\|video_\|Mux0\~1) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (294:294:294)) - (PORT datab (255:255:255) (335:335:335)) - (PORT datad (161:161:161) (182:182:182)) + (PORT dataa (276:276:276) (363:363:363)) + (PORT datab (222:222:222) (291:291:291)) + (PORT datad (159:159:159) (179:179:179)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -54701,7 +56884,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (817:817:817) (812:812:812)) + (PORT datad (966:966:966) (931:931:931)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54711,9 +56894,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1697:1697:1697) (1712:1712:1712)) + (PORT clk (1666:1666:1666) (1677:1677:1677)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1345:1345:1345) (1319:1319:1319)) + (PORT ena (1120:1120:1120) (1099:1099:1099)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54727,7 +56910,7 @@ (INSTANCE ula_\|video_\|bits\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (590:590:590) (620:620:620)) + (PORT datad (591:591:591) (633:633:633)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54737,9 +56920,9 @@ (INSTANCE ula_\|video_\|bits\[2\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT clk (1361:1361:1361) (1378:1378:1378)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) + (PORT ena (1120:1120:1120) (1090:1090:1090)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54753,7 +56936,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1359:1359:1359) (1296:1296:1296)) + (PORT datad (846:846:846) (822:822:822)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54763,9 +56946,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1697:1697:1697) (1712:1712:1712)) + (PORT clk (1666:1666:1666) (1677:1677:1677)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1345:1345:1345) (1319:1319:1319)) + (PORT ena (1120:1120:1120) (1099:1099:1099)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54779,9 +56962,9 @@ (INSTANCE ula_\|video_\|bits\[0\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) - (PORT asdata (902:902:902) (926:926:926)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) + (PORT clk (1361:1361:1361) (1378:1378:1378)) + (PORT asdata (1370:1370:1370) (1397:1397:1397)) + (PORT ena (1120:1120:1120) (1090:1090:1090)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54795,7 +56978,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1360:1360:1360) (1334:1334:1334)) + (PORT datad (600:600:600) (587:587:587)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54805,9 +56988,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1697:1697:1697) (1712:1712:1712)) + (PORT clk (1666:1666:1666) (1677:1677:1677)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1345:1345:1345) (1319:1319:1319)) + (PORT ena (1120:1120:1120) (1099:1099:1099)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54821,7 +57004,7 @@ (INSTANCE ula_\|video_\|bits\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (591:591:591) (619:619:619)) + (PORT datad (599:599:599) (636:636:636)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54831,9 +57014,9 @@ (INSTANCE ula_\|video_\|bits\[1\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT clk (1361:1361:1361) (1378:1378:1378)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) + (PORT ena (1120:1120:1120) (1090:1090:1090)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54847,7 +57030,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1179:1179:1179) (1117:1117:1117)) + (PORT datad (856:856:856) (854:854:854)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54857,9 +57040,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1697:1697:1697) (1712:1712:1712)) + (PORT clk (1666:1666:1666) (1677:1677:1677)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1345:1345:1345) (1319:1319:1319)) + (PORT ena (1120:1120:1120) (1099:1099:1099)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54873,9 +57056,9 @@ (INSTANCE ula_\|video_\|bits\[3\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) - (PORT asdata (1335:1335:1335) (1311:1311:1311)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) + (PORT clk (1361:1361:1361) (1378:1378:1378)) + (PORT asdata (1068:1068:1068) (1081:1081:1081)) + (PORT ena (1120:1120:1120) (1090:1090:1090)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54889,11 +57072,11 @@ (INSTANCE ula_\|video_\|Mux0\~2) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (293:293:293)) - (PORT datab (255:255:255) (335:335:335)) - (PORT datad (589:589:589) (620:620:620)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (281:281:281) (368:368:368)) + (PORT datab (221:221:221) (290:290:290)) + (PORT datad (354:354:354) (390:390:390)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -54904,9 +57087,9 @@ (INSTANCE ula_\|video_\|Mux0\~3) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (293:293:293)) - (PORT datab (258:258:258) (340:340:340)) - (PORT datad (161:161:161) (182:182:182)) + (PORT dataa (282:282:282) (368:368:368)) + (PORT datab (220:220:220) (288:288:288)) + (PORT datad (157:157:157) (178:178:178)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -54916,44 +57099,217 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|cindex\[1\]\~0) + (INSTANCE ula_\|video_\|cindex\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (377:377:377) (425:425:425)) - (PORT datab (181:181:181) (215:215:215)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (158:158:158) (180:180:180)) - (IOPATH dataa combout (299:299:299) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1319:1319:1319) (1304:1304:1304)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1694:1694:1694) (1714:1714:1714)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1119:1119:1119) (1089:1089:1089)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1361:1361:1361) (1378:1378:1378)) + (PORT asdata (916:916:916) (962:962:962)) + (PORT ena (1120:1120:1120) (1090:1090:1090)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (601:601:601) (587:587:587)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1694:1694:1694) (1714:1714:1714)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1119:1119:1119) (1089:1089:1089)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1362:1362:1362) (1378:1378:1378)) + (PORT asdata (918:918:918) (949:949:949)) + (PORT ena (1340:1340:1340) (1302:1302:1302)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|cindex\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (223:223:223) (296:296:296)) - (PORT datad (322:322:322) (326:326:326)) - (IOPATH dataa combout (273:273:273) (269:269:269)) + (PORT dataa (197:197:197) (241:241:241)) + (PORT datad (326:326:326) (364:364:364)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (446:446:446)) + (PORT datab (261:261:261) (334:334:334)) + (PORT datac (224:224:224) (299:299:299)) + (PORT datad (238:238:238) (301:301:301)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (631:631:631)) + (PORT datab (435:435:435) (467:467:467)) + (PORT datac (154:154:154) (185:185:185)) + (PORT datad (330:330:330) (329:329:329)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (451:451:451)) + (PORT datab (436:436:436) (470:470:470)) + (PORT datac (175:175:175) (207:207:207)) + (PORT datad (327:327:327) (327:327:327)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (311:311:311)) + (PORT datad (224:224:224) (287:287:287)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|disp_enable\~0) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (642:642:642)) + (PORT datab (238:238:238) (306:306:306)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|disp_enable\~1) + (DELAY + (ABSOLUTE + (PORT datab (188:188:188) (224:224:224)) + (PORT datac (175:175:175) (207:207:207)) + (PORT datad (473:473:473) (467:467:467)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|VGA_R\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (372:372:372) (405:405:405)) - (PORT datab (1379:1379:1379) (1403:1403:1403)) - (PORT datac (212:212:212) (254:254:254)) - (PORT datad (165:165:165) (188:188:188)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (1332:1332:1332) (1361:1361:1361)) + (PORT datab (212:212:212) (252:252:252)) + (PORT datac (305:305:305) (313:313:313)) + (PORT datad (186:186:186) (212:212:212)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -54964,7 +57320,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1074:1074:1074) (1080:1080:1080)) + (PORT datad (994:994:994) (965:965:965)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54974,9 +57330,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1725:1725:1725) (1744:1744:1744)) + (PORT clk (1694:1694:1694) (1714:1714:1714)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1341:1341:1341) (1316:1316:1316)) + (PORT ena (1119:1119:1119) (1089:1089:1089)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54990,9 +57346,9 @@ (INSTANCE ula_\|video_\|attr\[6\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) - (PORT asdata (1117:1117:1117) (1123:1123:1123)) - (PORT ena (1513:1513:1513) (1457:1457:1457)) + (PORT clk (1361:1361:1361) (1377:1377:1377)) + (PORT asdata (893:893:893) (923:923:923)) + (PORT ena (1180:1180:1180) (1163:1163:1163)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -55006,11 +57362,11 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (194:194:194) (237:237:237)) - (PORT datab (189:189:189) (228:228:228)) - (PORT datad (325:325:325) (328:328:328)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (341:341:341) (352:352:352)) + (PORT datab (1019:1019:1019) (1026:1026:1026)) + (PORT datad (167:167:167) (193:193:193)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -55021,11 +57377,21 @@ (INSTANCE ula_\|video_\|VGA_R\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (290:290:290)) - (PORT datac (364:364:364) (382:382:382)) - (PORT datad (165:165:165) (187:187:187)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (337:337:337) (351:351:351)) + (PORT datab (213:213:213) (255:255:255)) + (PORT datac (304:304:304) (313:313:313)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|border\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1220:1220:1220) (1200:1200:1200)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55035,35 +57401,9 @@ (INSTANCE ula_\|border\[2\]) (DELAY (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (882:882:882) (867:867:867)) - (PORT ena (735:735:735) (734:734:734)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (817:817:817) (811:811:811)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1725:1725:1725) (1744:1744:1744)) + (PORT clk (1349:1349:1349) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1341:1341:1341) (1316:1316:1316)) + (PORT ena (1784:1784:1784) (1772:1772:1772)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -55072,28 +57412,12 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) - (PORT asdata (1104:1104:1104) (1120:1120:1120)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|attr_prefetch\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (874:874:874) (869:869:869)) + (PORT datad (866:866:866) (863:863:863)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55103,9 +57427,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1725:1725:1725) (1744:1744:1744)) + (PORT clk (1694:1694:1694) (1714:1714:1714)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1341:1341:1341) (1316:1316:1316)) + (PORT ena (1119:1119:1119) (1089:1089:1089)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -55119,9 +57443,51 @@ (INSTANCE ula_\|video_\|attr\[5\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) - (PORT asdata (910:910:910) (932:932:932)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) + (PORT clk (1361:1361:1361) (1378:1378:1378)) + (PORT asdata (923:923:923) (963:963:963)) + (PORT ena (1120:1120:1120) (1090:1090:1090)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (967:967:967) (931:931:931)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1694:1694:1694) (1714:1714:1714)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1119:1119:1119) (1089:1089:1089)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1361:1361:1361) (1378:1378:1378)) + (PORT asdata (1319:1319:1319) (1307:1307:1307)) + (PORT ena (1120:1120:1120) (1090:1090:1090)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -55135,9 +57501,9 @@ (INSTANCE ula_\|video_\|cindex\[2\]\~2) (DELAY (ABSOLUTE - (PORT datab (221:221:221) (290:290:290)) - (PORT datad (185:185:185) (209:209:209)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (199:199:199) (243:243:243)) + (PORT datad (198:198:198) (256:256:256)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -55148,10 +57514,10 @@ (INSTANCE ula_\|video_\|VGA_G\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (2150:2150:2150) (2222:2222:2222)) - (PORT datab (379:379:379) (407:407:407)) - (PORT datac (355:355:355) (376:376:376)) - (PORT datad (510:510:510) (500:500:500)) + (PORT dataa (209:209:209) (247:247:247)) + (PORT datab (215:215:215) (258:258:258)) + (PORT datac (795:795:795) (825:825:825)) + (PORT datad (297:297:297) (303:303:303)) (IOPATH dataa combout (307:307:307) (280:280:280)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -55164,11 +57530,21 @@ (INSTANCE ula_\|video_\|VGA_G\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (594:594:594) (592:592:592)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datad (352:352:352) (352:352:352)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (335:335:335) (350:350:350)) + (PORT datac (560:560:560) (545:545:545)) + (PORT datad (294:294:294) (300:300:300)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|border\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (539:539:539) (527:527:527)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55178,9 +57554,51 @@ (INSTANCE ula_\|border\[0\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1365:1365:1365)) - (PORT asdata (1352:1352:1352) (1356:1356:1356)) - (PORT ena (1939:1939:1939) (1935:1935:1935)) + (PORT clk (1336:1336:1336) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1584:1584:1584) (1548:1548:1548)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (848:848:848) (823:823:823)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1694:1694:1694) (1714:1714:1714)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1119:1119:1119) (1089:1089:1089)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1362:1362:1362) (1378:1378:1378)) + (PORT asdata (893:893:893) (929:929:929)) + (PORT ena (1340:1340:1340) (1302:1302:1302)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -55189,64 +57607,12 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1358:1358:1358) (1299:1299:1299)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1725:1725:1725) (1744:1744:1744)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1341:1341:1341) (1316:1316:1316)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (782:782:782) (789:789:789)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1372:1372:1372)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1303:1303:1303) (1280:1280:1280)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|attr_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1179:1179:1179) (1118:1118:1118)) + (PORT datad (860:860:860) (858:858:858)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55256,9 +57622,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1725:1725:1725) (1744:1744:1744)) + (PORT clk (1694:1694:1694) (1714:1714:1714)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1341:1341:1341) (1316:1316:1316)) + (PORT ena (1119:1119:1119) (1089:1089:1089)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -55272,9 +57638,9 @@ (INSTANCE ula_\|video_\|attr\[3\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) - (PORT asdata (884:884:884) (917:917:917)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) + (PORT clk (1361:1361:1361) (1378:1378:1378)) + (PORT asdata (893:893:893) (929:929:929)) + (PORT ena (1120:1120:1120) (1090:1090:1090)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -55288,8 +57654,8 @@ (INSTANCE ula_\|video_\|cindex\[0\]\~3) (DELAY (ABSOLUTE - (PORT datab (358:358:358) (403:403:403)) - (PORT datad (186:186:186) (210:210:210)) + (PORT datab (351:351:351) (398:398:398)) + (PORT datad (172:172:172) (202:202:202)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -55301,13 +57667,13 @@ (INSTANCE ula_\|video_\|VGA_B\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (372:372:372) (405:405:405)) - (PORT datab (1541:1541:1541) (1559:1559:1559)) - (PORT datac (210:210:210) (254:254:254)) - (PORT datad (311:311:311) (320:320:320)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (1586:1586:1586) (1650:1650:1650)) + (PORT datab (202:202:202) (236:236:236)) + (PORT datac (343:343:343) (345:345:345)) + (PORT datad (346:346:346) (347:347:347)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55317,11 +57683,11 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~2) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (290:290:290)) - (PORT datac (364:364:364) (381:381:381)) - (PORT datad (316:316:316) (325:325:325)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (338:338:338) (351:351:351)) + (PORT datab (327:327:327) (340:340:340)) + (PORT datad (348:348:348) (351:351:351)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55331,11 +57697,11 @@ (INSTANCE ula_\|video_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (636:636:636) (662:662:662)) - (PORT datab (256:256:256) (325:325:325)) - (PORT datad (601:601:601) (629:629:629)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (833:833:833) (851:851:851)) + (PORT datac (784:784:784) (795:795:795)) + (PORT datad (1043:1043:1043) (1048:1048:1048)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55345,7 +57711,7 @@ (INSTANCE ula_\|video_\|VGA_HS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1372:1372:1372)) + (PORT clk (1360:1360:1360) (1377:1377:1377)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -55359,9 +57725,9 @@ (INSTANCE ula_\|video_\|Selector0\~0) (DELAY (ABSOLUTE - (PORT dataa (946:946:946) (919:919:919)) - (PORT datab (207:207:207) (244:244:244)) - (PORT datad (529:529:529) (511:511:511)) + (PORT dataa (184:184:184) (220:220:220)) + (PORT datab (373:373:373) (384:384:384)) + (PORT datad (338:338:338) (336:336:336)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -55375,7 +57741,7 @@ (DELAY (ABSOLUTE (PORT clk (1335:1335:1335) (1352:1352:1352)) - (PORT d (1573:1573:1573) (1534:1534:1534)) + (PORT d (2121:2121:2121) (2113:2113:2113)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) ) ) @@ -55389,7 +57755,7 @@ (INSTANCE ula_\|video_\|VGA_VS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1360:1360:1360) (1375:1375:1375)) + (PORT clk (1361:1361:1361) (1377:1377:1377)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -55403,11 +57769,11 @@ (INSTANCE ula_\|video_\|Selector1\~0) (DELAY (ABSOLUTE - (PORT dataa (576:576:576) (562:562:562)) - (PORT datab (1088:1088:1088) (1059:1059:1059)) - (PORT datad (635:635:635) (679:679:679)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (273:273:273) (275:275:275)) + (PORT dataa (259:259:259) (342:342:342)) + (PORT datab (499:499:499) (489:489:489)) + (PORT datad (1356:1356:1356) (1332:1332:1332)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -55419,7 +57785,7 @@ (DELAY (ABSOLUTE (PORT clk (1333:1333:1333) (1351:1351:1351)) - (PORT d (1652:1652:1652) (1646:1646:1646)) + (PORT d (1430:1430:1430) (1495:1495:1495)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) ) ) @@ -55433,7 +57799,7 @@ (INSTANCE z80_\|memory_ifc_\|q1\~feeder) (DELAY (ABSOLUTE - (PORT datad (576:576:576) (598:598:598)) + (PORT datad (229:229:229) (290:290:290)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55443,10 +57809,10 @@ (INSTANCE z80_\|memory_ifc_\|q1) (DELAY (ABSOLUTE - (PORT clk (1359:1359:1359) (1380:1380:1380)) + (PORT clk (1346:1346:1346) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1405:1405:1405) (1376:1376:1376)) - (PORT ena (1358:1358:1358) (1339:1339:1339)) + (PORT clrn (1403:1403:1403) (1369:1369:1369)) + (PORT ena (1133:1133:1133) (1118:1118:1118)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -55461,10 +57827,10 @@ (INSTANCE z80_\|memory_ifc_\|q2) (DELAY (ABSOLUTE - (PORT clk (1359:1359:1359) (1380:1380:1380)) - (PORT asdata (507:507:507) (569:569:569)) - (PORT clrn (1405:1405:1405) (1376:1376:1376)) - (PORT ena (1358:1358:1358) (1339:1339:1339)) + (PORT clk (1346:1346:1346) (1366:1366:1366)) + (PORT asdata (504:504:504) (566:566:566)) + (PORT clrn (1403:1403:1403) (1369:1369:1369)) + (PORT ena (1133:1133:1133) (1118:1118:1118)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -55479,7 +57845,7 @@ (INSTANCE z80_\|memory_ifc_\|nRFSH_out\~0) (DELAY (ABSOLUTE - (PORT datad (577:577:577) (598:598:598)) + (PORT datad (229:229:229) (289:289:289)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -55490,8 +57856,8 @@ (INSTANCE z80_\|memory_ifc_\|nM1_out) (DELAY (ABSOLUTE - (PORT datac (1191:1191:1191) (1223:1223:1223)) - (PORT datad (578:578:578) (601:601:601)) + (PORT datac (1360:1360:1360) (1342:1342:1342)) + (PORT datad (228:228:228) (289:289:289)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -55502,10 +57868,10 @@ (INSTANCE ula_\|beep\~0) (DELAY (ABSOLUTE - (PORT datab (1602:1602:1602) (1633:1633:1633)) - (PORT datac (2798:2798:2798) (3004:3004:3004)) - (PORT datad (1172:1172:1172) (1181:1181:1181)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (908:908:908) (923:923:923)) + (PORT datac (3029:3029:3029) (3293:3293:3293)) + (PORT datad (553:553:553) (541:541:541)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -55516,9 +57882,9 @@ (INSTANCE ula_\|beep) (DELAY (ABSOLUTE - (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT clk (1344:1344:1344) (1362:1362:1362)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (2376:2376:2376) (2363:2363:2363)) + (PORT ena (910:910:910) (910:910:910)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -55527,4 +57893,2294 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux26\~4) + (DELAY + (ABSOLUTE + (PORT dataa (2141:2141:2141) (2278:2278:2278)) + (PORT datab (873:873:873) (871:871:871)) + (PORT datad (1320:1320:1320) (1366:1366:1366)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT datac (909:909:909) (982:982:982)) + (PORT datad (1662:1662:1662) (1718:1718:1718)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (841:841:841) (862:862:862)) + (PORT datab (761:761:761) (826:826:826)) + (PORT datac (716:716:716) (788:788:788)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (264:264:264) (337:337:337)) + (PORT datac (539:539:539) (540:540:540)) + (PORT datad (258:258:258) (325:325:325)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (950:950:950) (998:998:998)) + (PORT datab (954:954:954) (988:988:988)) + (PORT datac (968:968:968) (1026:1026:1026)) + (PORT datad (552:552:552) (548:548:548)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1210:1210:1210) (1275:1275:1275)) + (PORT datab (1743:1743:1743) (1802:1802:1802)) + (PORT datac (911:911:911) (980:980:980)) + (PORT datad (725:725:725) (709:709:709)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (1203:1203:1203) (1248:1248:1248)) + (PORT datac (1713:1713:1713) (1778:1778:1778)) + (PORT datad (908:908:908) (967:967:967)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (867:867:867)) + (PORT datab (760:760:760) (831:831:831)) + (PORT datac (162:162:162) (197:197:197)) + (PORT datad (165:165:165) (191:191:191)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1210:1210:1210) (1275:1275:1275)) + (PORT datab (188:188:188) (222:222:222)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.bank\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1357:1357:1357)) + (PORT d (1636:1636:1636) (1697:1697:1697)) + (PORT ena (1640:1640:1640) (1571:1571:1571)) + (IOPATH (posedge clk) q (524:524:524) (534:534:534)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (77:77:77)) + (SETUP ena (posedge clk) (77:77:77)) + (HOLD d (posedge clk) (86:86:86)) + (HOLD ena (posedge clk) (86:86:86)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux25\~4) + (DELAY + (ABSOLUTE + (PORT dataa (2141:2141:2141) (2279:2279:2279)) + (PORT datab (1327:1327:1327) (1387:1387:1387)) + (PORT datad (849:849:849) (841:841:841)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.bank\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1359:1359:1359)) + (PORT d (2129:2129:2129) (2198:2198:2198)) + (PORT ena (1478:1478:1478) (1426:1426:1426)) + (IOPATH (posedge clk) q (524:524:524) (534:534:534)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (77:77:77)) + (SETUP ena (posedge clk) (77:77:77)) + (HOLD d (posedge clk) (86:86:86)) + (HOLD ena (posedge clk) (86:86:86)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~5) + (DELAY + (ABSOLUTE + (PORT dataa (976:976:976) (1062:1062:1062)) + (PORT datab (936:936:936) (988:988:988)) + (PORT datac (1069:1069:1069) (1053:1053:1053)) + (PORT datad (918:918:918) (956:956:956)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~0) + (DELAY + (ABSOLUTE + (PORT datab (1291:1291:1291) (1358:1358:1358)) + (PORT datac (1454:1454:1454) (1501:1501:1501)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~7) + (DELAY + (ABSOLUTE + (PORT datab (1581:1581:1581) (1681:1681:1681)) + (PORT datac (199:199:199) (269:269:269)) + (PORT datad (2418:2418:2418) (2528:2528:2528)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (691:691:691)) + (PORT datab (184:184:184) (217:217:217)) + (PORT datac (162:162:162) (195:195:195)) + (PORT datad (168:168:168) (193:193:193)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1197:1197:1197) (1252:1252:1252)) + (PORT datab (1366:1366:1366) (1394:1394:1394)) + (PORT datac (1455:1455:1455) (1501:1501:1501)) + (PORT datad (1254:1254:1254) (1323:1323:1323)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1197:1197:1197) (1252:1252:1252)) + (PORT datab (930:930:930) (1000:1000:1000)) + (PORT datac (154:154:154) (185:185:185)) + (PORT datad (170:170:170) (198:198:198)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1010:1010:1010) (1003:1003:1003)) + (PORT datab (195:195:195) (235:235:235)) + (PORT datac (946:946:946) (1027:1027:1027)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~4) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (217:217:217)) + (PORT datab (195:195:195) (234:234:234)) + (PORT datac (155:155:155) (184:184:184)) + (PORT datad (908:908:908) (969:969:969)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.dq_masks\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1356:1356:1356)) + (PORT d (1348:1348:1348) (1388:1388:1388)) + (IOPATH (posedge clk) q (524:524:524) (534:534:534)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (77:77:77)) + (HOLD d (posedge clk) (86:86:86)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.dq_masks\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1356:1356:1356)) + (PORT d (1333:1333:1333) (1375:1375:1375)) + (IOPATH (posedge clk) q (524:524:524) (534:534:534)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (77:77:77)) + (HOLD d (posedge clk) (86:86:86)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT datac (1449:1449:1449) (1494:1494:1494)) + (PORT datad (908:908:908) (970:970:970)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~3) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (360:360:360)) + (PORT datab (1373:1373:1373) (1412:1412:1412)) + (PORT datac (1231:1231:1231) (1313:1313:1313)) + (PORT datad (327:327:327) (332:332:332)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~5) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (463:463:463)) + (PORT datab (638:638:638) (688:688:688)) + (PORT datac (539:539:539) (540:540:540)) + (PORT datad (258:258:258) (325:325:325)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~4) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (338:338:338)) + (PORT datab (1251:1251:1251) (1312:1312:1312)) + (PORT datac (805:805:805) (806:806:806)) + (PORT datad (1335:1335:1335) (1378:1378:1378)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1263:1263:1263) (1352:1352:1352)) + (PORT datab (1252:1252:1252) (1307:1307:1307)) + (PORT datac (804:804:804) (804:804:804)) + (PORT datad (1158:1158:1158) (1202:1202:1202)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (698:698:698) (776:776:776)) + (PORT datab (273:273:273) (351:351:351)) + (PORT datac (575:575:575) (602:602:602)) + (PORT datad (688:688:688) (743:743:743)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~2) + (DELAY + (ABSOLUTE + (PORT datab (419:419:419) (450:450:450)) + (PORT datac (387:387:387) (422:422:422)) + (PORT datad (548:548:548) (569:569:569)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~3) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (439:439:439)) + (PORT datab (248:248:248) (319:319:319)) + (PORT datac (158:158:158) (188:188:188)) + (PORT datad (395:395:395) (427:427:427)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (438:438:438)) + (PORT datab (420:420:420) (453:453:453)) + (PORT datac (329:329:329) (336:336:336)) + (PORT datad (383:383:383) (417:417:417)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~4) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (395:395:395) (436:436:436)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (628:628:628) (676:676:676)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1323:1323:1323) (1363:1363:1363)) + (PORT datab (1494:1494:1494) (1550:1550:1550)) + (PORT datac (1222:1222:1222) (1279:1279:1279)) + (PORT datad (310:310:310) (320:320:320)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~0) + (DELAY + (ABSOLUTE + (PORT datab (1250:1250:1250) (1314:1314:1314)) + (PORT datad (1457:1457:1457) (1518:1518:1518)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~6) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (374:374:374)) + (PORT datab (593:593:593) (601:601:601)) + (PORT datac (157:157:157) (189:189:189)) + (PORT datad (167:167:167) (191:191:191)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~7) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (1154:1154:1154) (1217:1217:1217)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (160:160:160) (180:180:180)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1328:1328:1328) (1347:1347:1347)) + (PORT d (1353:1353:1353) (1397:1397:1397)) + (IOPATH (posedge clk) q (549:549:549) (552:552:552)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (75:75:75)) + (HOLD d (posedge clk) (89:89:89)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~11) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (978:978:978)) + (PORT datab (936:936:936) (990:990:990)) + (PORT datac (1069:1069:1069) (1055:1055:1055)) + (PORT datad (919:919:919) (958:958:958)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~6) + (DELAY + (ABSOLUTE + (PORT dataa (973:973:973) (1061:1061:1061)) + (PORT datab (189:189:189) (224:224:224)) + (PORT datac (983:983:983) (974:974:974)) + (PORT datad (892:892:892) (958:958:958)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1251:1251:1251)) + (PORT datab (1292:1292:1292) (1359:1359:1359)) + (PORT datac (874:874:874) (942:942:942)) + (PORT datad (583:583:583) (593:593:593)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~7) + (DELAY + (ABSOLUTE + (PORT dataa (973:973:973) (1062:1062:1062)) + (PORT datab (1291:1291:1291) (1361:1361:1361)) + (PORT datac (874:874:874) (949:949:949)) + (PORT datad (892:892:892) (958:958:958)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~8) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (222:222:222)) + (PORT datab (931:931:931) (1005:1005:1005)) + (PORT datac (163:163:163) (197:197:197)) + (PORT datad (165:165:165) (191:191:191)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~9) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (203:203:203) (236:236:236)) + (PORT datac (162:162:162) (195:195:195)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1328:1328:1328) (1347:1347:1347)) + (PORT d (1146:1146:1146) (1216:1216:1216)) + (IOPATH (posedge clk) q (549:549:549) (552:552:552)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (75:75:75)) + (HOLD d (posedge clk) (89:89:89)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ena_reg") + (INSTANCE sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl_e_DRAM_CLK.extena0_reg) + (DELAY + (ABSOLUTE + (PORT d (252:252:252) (230:230:230)) + (PORT clk (0:0:0) (0:0:0)) + (IOPATH (posedge clk) q (148:148:148) (148:148:148)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (81:81:81)) + (HOLD d (posedge clk) (77:77:77)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ena_reg") + (INSTANCE sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl_e_DRAM_CLK.extena1_reg) + (DELAY + (ABSOLUTE + (PORT d (0:0:0) (0:0:0)) + (PORT clk (0:0:0) (0:0:0)) + (IOPATH (posedge clk) q (247:247:247) (230:230:230)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (81:81:81)) + (HOLD d (posedge clk) (77:77:77)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~2) + (DELAY + (ABSOLUTE + (PORT dataa (690:690:690) (767:767:767)) + (PORT datab (713:713:713) (776:776:776)) + (PORT datad (246:246:246) (317:317:317)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1387:1387:1387) (1441:1441:1441)) + (PORT datab (597:597:597) (624:624:624)) + (PORT datac (156:156:156) (185:185:185)) + (PORT datad (1307:1307:1307) (1342:1342:1342)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1256:1256:1256) (1343:1343:1343)) + (PORT datab (1252:1252:1252) (1314:1314:1314)) + (PORT datac (587:587:587) (589:589:589)) + (PORT datad (303:303:303) (305:305:305)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1257:1257:1257) (1343:1343:1343)) + (PORT datab (1253:1253:1253) (1314:1314:1314)) + (PORT datac (1458:1458:1458) (1507:1507:1507)) + (PORT datad (1162:1162:1162) (1207:1207:1207)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~6) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (981:981:981)) + (PORT datab (934:934:934) (1004:1004:1004)) + (PORT datac (949:949:949) (1030:1030:1030)) + (PORT datad (895:895:895) (959:959:959)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~7) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (869:869:869)) + (PORT datab (760:760:760) (825:825:825)) + (PORT datac (717:717:717) (793:793:793)) + (PORT datad (288:288:288) (295:295:295)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1324:1324:1324) (1365:1365:1365)) + (PORT datab (1150:1150:1150) (1216:1216:1216)) + (PORT datac (807:807:807) (807:807:807)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~8) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (220:220:220)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (550:550:550) (543:543:543)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1326:1326:1326) (1341:1341:1341)) + (PORT d (1667:1667:1667) (1728:1728:1728)) + (IOPATH (posedge clk) q (549:549:549) (552:552:552)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (75:75:75)) + (HOLD d (posedge clk) (89:89:89)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~2) + (DELAY + (ABSOLUTE + (PORT dataa (717:717:717) (772:772:772)) + (PORT datab (695:695:695) (765:765:765)) + (PORT datac (698:698:698) (779:779:779)) + (PORT datad (801:801:801) (785:785:785)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (2837:2837:2837) (2923:2923:2923)) + (PORT datab (567:567:567) (594:594:594)) + (PORT datac (957:957:957) (1018:1018:1018)) + (PORT datad (591:591:591) (593:593:593)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (560:560:560)) + (PORT datab (901:901:901) (969:969:969)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1257:1257:1257) (1344:1344:1344)) + (PORT datab (1154:1154:1154) (1221:1221:1221)) + (PORT datac (1458:1458:1458) (1508:1508:1508)) + (PORT datad (1336:1336:1336) (1375:1375:1375)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1264:1264:1264) (1353:1353:1353)) + (PORT datab (1149:1149:1149) (1214:1214:1214)) + (PORT datac (1453:1453:1453) (1500:1500:1500)) + (PORT datad (1340:1340:1340) (1380:1380:1380)) + (IOPATH dataa combout (299:299:299) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~5) + (DELAY + (ABSOLUTE + (PORT datab (1252:1252:1252) (1307:1307:1307)) + (PORT datac (159:159:159) (190:190:190)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[0\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1378:1378:1378)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (473:473:473) (502:502:502)) + (PORT sload (1491:1491:1491) (1583:1583:1583)) + (PORT ena (1138:1138:1138) (1126:1126:1126)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2837:2837:2837) (2921:2921:2921)) + (PORT datab (567:567:567) (594:594:594)) + (PORT datac (346:346:346) (361:361:361)) + (PORT datad (591:591:591) (589:589:589)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~4) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (845:845:845)) + (PORT datab (569:569:569) (596:596:596)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (1023:1023:1023) (1045:1045:1045)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[0\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT datab (974:974:974) (1022:1022:1022)) + (PORT datac (162:162:162) (194:194:194)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1328:1328:1328) (1344:1344:1344)) + (PORT d (1837:1837:1837) (1871:1871:1871)) + (PORT ena (1552:1552:1552) (1523:1523:1523)) + (IOPATH (posedge clk) q (549:549:549) (552:552:552)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (75:75:75)) + (SETUP ena (posedge clk) (75:75:75)) + (HOLD d (posedge clk) (89:89:89)) + (HOLD ena (posedge clk) (89:89:89)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~_Duplicate_1feeder) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (232:232:232)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~4) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (998:998:998)) + (PORT datab (227:227:227) (301:301:301)) + (PORT datac (1184:1184:1184) (1205:1205:1205)) + (PORT datad (306:306:306) (326:326:326)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (774:774:774)) + (PORT datab (713:713:713) (780:780:780)) + (PORT datac (571:571:571) (600:600:600)) + (PORT datad (248:248:248) (318:318:318)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~5) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (1002:1002:1002)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (889:889:889) (928:928:928)) + (PORT datad (803:803:803) (798:798:798)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~6) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (1000:1000:1000)) + (PORT datab (990:990:990) (1063:1063:1063)) + (PORT datac (156:156:156) (185:185:185)) + (PORT datad (811:811:811) (789:789:789)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1174:1174:1174) (1236:1236:1236)) + (PORT datab (998:998:998) (1049:1049:1049)) + (PORT datac (1153:1153:1153) (1230:1230:1230)) + (PORT datad (918:918:918) (956:956:956)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[1\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1348:1348:1348) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (472:472:472) (503:503:503)) + (PORT sload (1552:1552:1552) (1520:1520:1520)) + (PORT ena (1182:1182:1182) (1169:1169:1169)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1212:1212:1212) (1288:1288:1288)) + (PORT datab (332:332:332) (356:356:356)) + (PORT datac (890:890:890) (926:926:926)) + (PORT datad (908:908:908) (960:960:960)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1213:1213:1213) (1289:1289:1289)) + (PORT datac (487:487:487) (478:478:478)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1287:1287:1287)) + (PORT datab (2416:2416:2416) (2514:2514:2514)) + (PORT datac (1607:1607:1607) (1622:1622:1622)) + (PORT datad (911:911:911) (967:967:967)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (227:227:227) (299:299:299)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (234:234:234)) + (PORT datab (187:187:187) (222:222:222)) + (PORT datac (935:935:935) (997:997:997)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1359:1359:1359)) + (PORT d (1386:1386:1386) (1431:1431:1431)) + (PORT ena (1771:1771:1771) (1743:1743:1743)) + (IOPATH (posedge clk) q (524:524:524) (534:534:534)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (77:77:77)) + (SETUP ena (posedge clk) (77:77:77)) + (HOLD d (posedge clk) (86:86:86)) + (HOLD ena (posedge clk) (86:86:86)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1206:1206:1206) (1279:1279:1279)) + (PORT datab (953:953:953) (991:991:991)) + (PORT datac (935:935:935) (999:999:999)) + (PORT datad (913:913:913) (970:970:970)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT datab (953:953:953) (989:989:989)) + (PORT datad (1185:1185:1185) (1248:1248:1248)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux21\~0) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (260:260:260)) + (PORT datab (985:985:985) (1059:1059:1059)) + (PORT datac (292:292:292) (295:295:295)) + (PORT datad (179:179:179) (201:201:201)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux22\~0) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (657:657:657)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (808:808:808) (811:811:811)) + (PORT datad (589:589:589) (590:590:590)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1688:1688:1688) (1756:1756:1756)) + (PORT datab (933:933:933) (1004:1004:1004)) + (PORT datac (716:716:716) (793:793:793)) + (PORT datad (720:720:720) (795:795:795)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (746:746:746) (819:819:819)) + (PORT datac (1713:1713:1713) (1779:1779:1779)) + (PORT datad (907:907:907) (968:968:968)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (861:861:861)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (1714:1714:1714) (1776:1776:1776)) + (PORT datad (1135:1135:1135) (1180:1180:1180)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1210:1210:1210) (1275:1275:1275)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (1296:1296:1296) (1317:1317:1317)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1689:1689:1689) (1755:1755:1755)) + (PORT datab (933:933:933) (1002:1002:1002)) + (PORT datac (716:716:716) (791:791:791)) + (PORT datad (721:721:721) (793:793:793)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (863:863:863)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (1296:1296:1296) (1316:1316:1316)) + (PORT datad (908:908:908) (967:967:967)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (239:239:239)) + (PORT datab (188:188:188) (223:223:223)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (1131:1131:1131) (1176:1176:1176)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datac (908:908:908) (978:978:978)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1359:1359:1359)) + (PORT d (1691:1691:1691) (1769:1769:1769)) + (PORT ena (1674:1674:1674) (1638:1638:1638)) + (IOPATH (posedge clk) q (524:524:524) (534:534:534)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (77:77:77)) + (SETUP ena (posedge clk) (77:77:77)) + (HOLD d (posedge clk) (86:86:86)) + (HOLD ena (posedge clk) (86:86:86)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux21\~1) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (653:653:653)) + (PORT datab (202:202:202) (236:236:236)) + (PORT datac (175:175:175) (206:206:206)) + (PORT datad (591:591:591) (593:593:593)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1358:1358:1358)) + (PORT d (1422:1422:1422) (1472:1472:1472)) + (PORT ena (1482:1482:1482) (1446:1446:1446)) + (IOPATH (posedge clk) q (524:524:524) (534:534:534)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (77:77:77)) + (SETUP ena (posedge clk) (77:77:77)) + (HOLD d (posedge clk) (86:86:86)) + (HOLD ena (posedge clk) (86:86:86)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~4) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (773:773:773)) + (PORT datab (713:713:713) (777:777:777)) + (PORT datad (245:245:245) (316:316:316)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~7) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (987:987:987)) + (PORT datab (2453:2453:2453) (2560:2560:2560)) + (PORT datac (1557:1557:1557) (1658:1658:1658)) + (PORT datad (862:862:862) (879:879:879)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~7) + (DELAY + (ABSOLUTE + (PORT dataa (728:728:728) (820:820:820)) + (PORT datab (839:839:839) (822:822:822)) + (PORT datac (1162:1162:1162) (1238:1238:1238)) + (PORT datad (762:762:762) (752:752:752)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~8) + (DELAY + (ABSOLUTE + (PORT dataa (953:953:953) (1002:1002:1002)) + (PORT datab (882:882:882) (889:889:889)) + (PORT datac (1153:1153:1153) (1234:1234:1234)) + (PORT datad (1147:1147:1147) (1199:1199:1199)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1178:1178:1178) (1244:1244:1244)) + (PORT datab (606:606:606) (632:632:632)) + (PORT datac (540:540:540) (529:529:529)) + (PORT datad (166:166:166) (189:189:189)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1174:1174:1174) (1237:1237:1237)) + (PORT datab (608:608:608) (636:636:636)) + (PORT datac (539:539:539) (526:526:526)) + (PORT datad (165:165:165) (187:187:187)) + (IOPATH dataa combout (307:307:307) (289:289:289)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~11) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (437:437:437)) + (PORT datab (833:833:833) (849:849:849)) + (PORT datac (295:295:295) (304:304:304)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[4\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1379:1379:1379)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (628:628:628) (625:625:625)) + (PORT sload (1515:1515:1515) (1612:1612:1612)) + (PORT ena (894:894:894) (882:882:882)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~12) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (720:720:720)) + (PORT datab (1919:1919:1919) (1988:1988:1988)) + (PORT datac (2115:2115:2115) (2205:2205:2205)) + (PORT datad (801:801:801) (815:815:815)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~5) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (597:597:597) (623:623:623)) + (PORT datac (1458:1458:1458) (1518:1518:1518)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~6) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (586:586:586)) + (PORT datab (834:834:834) (851:851:851)) + (PORT datac (915:915:915) (966:966:966)) + (PORT datad (356:356:356) (399:399:399)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[4\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1173:1173:1173) (1236:1236:1236)) + (PORT datab (567:567:567) (588:588:588)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[4\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT datab (998:998:998) (1050:1050:1050)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (179:179:179) (200:200:200)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1360:1360:1360)) + (PORT d (1565:1565:1565) (1579:1579:1579)) + (PORT ena (2120:2120:2120) (2104:2104:2104)) + (IOPATH (posedge clk) q (524:524:524) (534:534:534)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (77:77:77)) + (SETUP ena (posedge clk) (77:77:77)) + (HOLD d (posedge clk) (86:86:86)) + (HOLD ena (posedge clk) (86:86:86)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~1) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (775:775:775)) + (PORT datab (714:714:714) (778:778:778)) + (PORT datac (574:574:574) (601:601:601)) + (PORT datad (247:247:247) (315:315:315)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1174:1174:1174) (1238:1238:1238)) + (PORT datac (539:539:539) (528:528:528)) + (PORT datad (551:551:551) (547:547:547)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1243:1243:1243)) + (PORT datab (977:977:977) (1024:1024:1024)) + (PORT datac (1156:1156:1156) (1231:1231:1231)) + (PORT datad (166:166:166) (188:188:188)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1246:1246:1246)) + (PORT datab (978:978:978) (1026:1026:1026)) + (PORT datac (1153:1153:1153) (1235:1235:1235)) + (PORT datad (167:167:167) (191:191:191)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1284:1284:1284) (1274:1274:1274)) + (PORT datab (369:369:369) (427:427:427)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[5\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1379:1379:1379)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (474:474:474) (503:503:503)) + (PORT sload (1515:1515:1515) (1612:1612:1612)) + (PORT ena (894:894:894) (882:882:882)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~2) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (823:823:823) (849:849:849)) + (PORT datac (1456:1456:1456) (1518:1518:1518)) + (PORT datad (583:583:583) (629:629:629)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~3) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (583:583:583)) + (PORT datab (980:980:980) (1025:1025:1025)) + (PORT datac (1258:1258:1258) (1241:1241:1241)) + (PORT datad (346:346:346) (395:395:395)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[5\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1180:1180:1180) (1244:1244:1244)) + (PORT datab (602:602:602) (607:607:607)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[5\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (217:217:217)) + (PORT datab (999:999:999) (1055:1055:1055)) + (PORT datac (163:163:163) (197:197:197)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1357:1357:1357)) + (PORT d (1320:1320:1320) (1356:1356:1356)) + (PORT ena (2030:2030:2030) (1971:1971:1971)) + (IOPATH (posedge clk) q (524:524:524) (534:534:534)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (77:77:77)) + (SETUP ena (posedge clk) (77:77:77)) + (HOLD d (posedge clk) (86:86:86)) + (HOLD ena (posedge clk) (86:86:86)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux18\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2228:2228:2228) (2383:2383:2383)) + (PORT datac (1144:1144:1144) (1206:1206:1206)) + (PORT datad (613:613:613) (614:614:614)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1358:1358:1358)) + (PORT d (1406:1406:1406) (1451:1451:1451)) + (PORT ena (1482:1482:1482) (1446:1446:1446)) + (IOPATH (posedge clk) q (524:524:524) (534:534:534)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (77:77:77)) + (SETUP ena (posedge clk) (77:77:77)) + (HOLD d (posedge clk) (86:86:86)) + (HOLD ena (posedge clk) (86:86:86)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2225:2225:2225) (2380:2380:2380)) + (PORT datac (1400:1400:1400) (1411:1411:1411)) + (PORT datad (613:613:613) (613:613:613)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1335:1335:1335) (1356:1356:1356)) + (PORT d (1841:1841:1841) (1877:1877:1877)) + (PORT ena (1484:1484:1484) (1508:1508:1508)) + (IOPATH (posedge clk) q (524:524:524) (534:534:534)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (77:77:77)) + (SETUP ena (posedge clk) (77:77:77)) + (HOLD d (posedge clk) (86:86:86)) + (HOLD ena (posedge clk) (86:86:86)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux16\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2235:2235:2235) (2391:2391:2391)) + (PORT datac (219:219:219) (288:288:288)) + (PORT datad (613:613:613) (614:614:614)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1326:1326:1326) (1342:1342:1342)) + (PORT d (1957:1957:1957) (2019:2019:2019)) + (PORT ena (1306:1306:1306) (1295:1295:1295)) + (IOPATH (posedge clk) q (549:549:549) (552:552:552)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (75:75:75)) + (SETUP ena (posedge clk) (75:75:75)) + (HOLD d (posedge clk) (89:89:89)) + (HOLD ena (posedge clk) (89:89:89)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux15\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2237:2237:2237) (2391:2391:2391)) + (PORT datab (864:864:864) (921:921:921)) + (PORT datad (614:614:614) (619:619:619)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1328:1328:1328) (1344:1344:1344)) + (PORT d (1962:1962:1962) (2046:2046:2046)) + (PORT ena (1339:1339:1339) (1340:1340:1340)) + (IOPATH (posedge clk) q (549:549:549) (552:552:552)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (75:75:75)) + (SETUP ena (posedge clk) (75:75:75)) + (HOLD d (posedge clk) (89:89:89)) + (HOLD ena (posedge clk) (89:89:89)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (650:650:650)) + (PORT datab (649:649:649) (721:721:721)) + (PORT datac (1155:1155:1155) (1214:1214:1214)) + (PORT datad (166:166:166) (187:187:187)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~1) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (645:645:645)) + (PORT datab (375:375:375) (422:422:422)) + (PORT datac (954:954:954) (1014:1014:1014)) + (PORT datad (586:586:586) (586:586:586)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[10\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (901:901:901) (970:970:970)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[10\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1355:1355:1355) (1378:1378:1378)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (472:472:472) (501:501:501)) + (PORT sload (1491:1491:1491) (1583:1583:1583)) + (PORT ena (1138:1138:1138) (1126:1126:1126)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~4) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (817:817:817)) + (PORT datab (373:373:373) (420:420:420)) + (PORT datac (624:624:624) (668:668:668)) + (PORT datad (627:627:627) (647:647:647)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~2) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (654:654:654)) + (PORT datab (650:650:650) (721:721:721)) + (PORT datac (1152:1152:1152) (1217:1217:1217)) + (PORT datad (166:166:166) (188:188:188)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~3) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (372:372:372) (418:418:418)) + (PORT datac (347:347:347) (362:362:362)) + (PORT datad (591:591:591) (589:589:589)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[10\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT datab (975:975:975) (1027:1027:1027)) + (PORT datac (163:163:163) (197:197:197)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1319:1319:1319) (1334:1334:1334)) + (PORT d (1341:1341:1341) (1380:1380:1380)) + (PORT ena (1549:1549:1549) (1506:1506:1506)) + (IOPATH (posedge clk) q (549:549:549) (552:552:552)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (75:75:75)) + (SETUP ena (posedge clk) (75:75:75)) + (HOLD d (posedge clk) (89:89:89)) + (HOLD ena (posedge clk) (89:89:89)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (696:696:696) (760:760:760)) + (PORT datac (1161:1161:1161) (1230:1230:1230)) + (PORT datad (672:672:672) (730:730:730)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (965:965:965)) + (PORT datab (200:200:200) (233:233:233)) + (PORT datac (203:203:203) (274:274:274)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (307:307:307) (289:289:289)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_2feeder) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (238:238:238)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_2) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1377:1377:1377)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (480:480:480) (516:516:516)) + (PORT sload (1199:1199:1199) (1301:1301:1301)) + (PORT ena (1179:1179:1179) (1184:1184:1184)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~10) + (DELAY + (ABSOLUTE + (PORT datab (226:226:226) (298:298:298)) + (PORT datac (702:702:702) (786:786:786)) + (PORT datad (625:625:625) (687:687:687)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~6) + (DELAY + (ABSOLUTE + (PORT dataa (722:722:722) (813:813:813)) + (PORT datab (837:837:837) (819:819:819)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (760:760:760) (750:750:750)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (243:243:243)) + (PORT datab (674:674:674) (748:748:748)) + (PORT datac (171:171:171) (210:210:210)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1332:1332:1332) (1350:1350:1350)) + (PORT d (1146:1146:1146) (1213:1213:1213)) + (PORT ena (1296:1296:1296) (1252:1252:1252)) + (IOPATH (posedge clk) q (549:549:549) (552:552:552)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (75:75:75)) + (SETUP ena (posedge clk) (75:75:75)) + (HOLD d (posedge clk) (89:89:89)) + (HOLD ena (posedge clk) (89:89:89)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_1SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (240:240:240)) + (PORT datab (674:674:674) (744:744:744)) + (PORT datac (170:170:170) (208:208:208)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1324:1324:1324) (1339:1339:1339)) + (PORT d (1564:1564:1564) (1606:1606:1606)) + (PORT ena (1576:1576:1576) (1542:1542:1542)) + (IOPATH (posedge clk) q (549:549:549) (552:552:552)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (75:75:75)) + (SETUP ena (posedge clk) (75:75:75)) + (HOLD d (posedge clk) (89:89:89)) + (HOLD ena (posedge clk) (89:89:89)) + ) + ) ) diff --git a/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo b/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo index ef4a25d..ca61a7e 100644 --- a/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo +++ b/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "04/01/2022 18:55:51" +// DATE "04/02/2022 14:51:20" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -50,14 +50,24 @@ module spectrum ( SW, GPIO_1, buzzer_out, - raw_loader_in); + raw_loader_in, + DRAM_BA, + DRAM_DQM, + DRAM_RAS_N, + DRAM_CAS_N, + DRAM_CKE, + DRAM_CLK, + DRAM_WE_N, + DRAM_CS_N, + DRAM_DQ, + DRAM_ADDR); output [7:0] LED; input CLOCK_50; input [1:0] KEY; input PS2_CLK; input PS2_DAT; -output I2C_SCLK; -output I2C_SDAT; +inout I2C_SCLK; +inout I2C_SDAT; output AUD_XCK; output AUD_ADCLRCK; output AUD_DACLRCK; @@ -73,6 +83,16 @@ input [3:0] SW; output [33:0] GPIO_1; output buzzer_out; input raw_loader_in; +output [1:0] DRAM_BA; +output [1:0] DRAM_DQM; +output DRAM_RAS_N; +output DRAM_CAS_N; +output DRAM_CKE; +output DRAM_CLK; +output DRAM_WE_N; +output DRAM_CS_N; +inout [15:0] DRAM_DQ; +output [12:0] DRAM_ADDR; // Design Ports Information // LED[0] => Location: PIN_A15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -139,8 +159,47 @@ input raw_loader_in; // GPIO_1[32] => Location: PIN_J13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // GPIO_1[33] => Location: PIN_J14, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // buzzer_out => Location: PIN_A6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_BA[0] => Location: PIN_M7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_BA[1] => Location: PIN_M6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQM[0] => Location: PIN_R6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQM[1] => Location: PIN_T5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_RAS_N => Location: PIN_L2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_CAS_N => Location: PIN_L1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_CKE => Location: PIN_L7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_CLK => Location: PIN_R4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_WE_N => Location: PIN_C2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_CS_N => Location: PIN_P6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[0] => Location: PIN_P2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[1] => Location: PIN_N5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[2] => Location: PIN_N6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[3] => Location: PIN_M8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[4] => Location: PIN_P8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[5] => Location: PIN_T7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[6] => Location: PIN_N8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[7] => Location: PIN_T6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[8] => Location: PIN_R1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[9] => Location: PIN_P1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[10] => Location: PIN_N2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[11] => Location: PIN_N1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[12] => Location: PIN_L4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // I2C_SCLK => Location: PIN_F2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // I2C_SDAT => Location: PIN_F1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[0] => Location: PIN_G2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[1] => Location: PIN_G1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[2] => Location: PIN_L8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[3] => Location: PIN_K5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[4] => Location: PIN_K2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[5] => Location: PIN_J2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[6] => Location: PIN_J1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[7] => Location: PIN_R7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[8] => Location: PIN_T4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[9] => Location: PIN_T2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[10] => Location: PIN_T3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[11] => Location: PIN_R3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[12] => Location: PIN_R5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[13] => Location: PIN_P3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[14] => Location: PIN_N3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[15] => Location: PIN_K1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // SW[1] => Location: PIN_T8, I/O Standard: 3.3-V LVTTL, Current Strength: Default // SW[2] => Location: PIN_B9, I/O Standard: 3.3-V LVTTL, Current Strength: Default // raw_loader_in => Location: PIN_B6, I/O Standard: 3.3-V LVTTL, Current Strength: Default @@ -170,6 +229,22 @@ initial $sdf_annotate("spectrum_6_1200mv_85c_v_slow.sdo"); wire \SW[0]~input_o ; wire \SW[3]~input_o ; wire \I2C_SCLK~input_o ; +wire \DRAM_DQ[0]~input_o ; +wire \DRAM_DQ[1]~input_o ; +wire \DRAM_DQ[2]~input_o ; +wire \DRAM_DQ[3]~input_o ; +wire \DRAM_DQ[4]~input_o ; +wire \DRAM_DQ[5]~input_o ; +wire \DRAM_DQ[6]~input_o ; +wire \DRAM_DQ[7]~input_o ; +wire \DRAM_DQ[8]~input_o ; +wire \DRAM_DQ[9]~input_o ; +wire \DRAM_DQ[10]~input_o ; +wire \DRAM_DQ[11]~input_o ; +wire \DRAM_DQ[12]~input_o ; +wire \DRAM_DQ[13]~input_o ; +wire \DRAM_DQ[14]~input_o ; +wire \DRAM_DQ[15]~input_o ; wire \CLOCK_50~input_o ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_fbout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ; @@ -178,692 +253,8 @@ wire \SW[2]~input_o ; wire \ula_|clocks_|clk_cpu~0_combout ; wire \ula_|clocks_|clk_cpu~q ; wire \ula_|clocks_|clk_cpu~clkctrl_outclk ; -wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; -wire \z80_|sequencer_|ena_M~combout ; wire \KEY[1]~input_o ; wire \z80_|interrupts_|nmi_armed~feeder_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; -wire \z80_|interrupts_|nmi_armed~q ; -wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ; -wire \z80_|execute_|ctl_eval_cond~0_combout ; -wire \z80_|execute_|ixy_d~4_combout ; -wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M3_ff~q ; -wire \z80_|execute_|fIOWrite~1_combout ; -wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M4_ff~q ; -wire \z80_|pla_decode_|Equal32~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; -wire \z80_|decode_state_|table_xx~0_combout ; -wire \z80_|pla_decode_|Equal1~7_combout ; -wire \z80_|pla_decode_|Equal2~0_combout ; -wire \z80_|pla_decode_|Equal36~0_combout ; -wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; -wire \z80_|execute_|ctl_state_tbl_we~8_combout ; -wire \z80_|decode_state_|DFFE_instCB~q ; -wire \z80_|pla_decode_|Equal52~0_combout ; -wire \z80_|pla_decode_|Equal2~1_combout ; -wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; -wire \z80_|decode_state_|DFFE_instED~q ; -wire \z80_|pla_decode_|Equal13~0_combout ; -wire \z80_|pla_decode_|Equal33~0_combout ; -wire \z80_|execute_|ctl_im_we~combout ; -wire \z80_|pla_decode_|Equal49~0_combout ; -wire \z80_|pla_decode_|Equal33~1_combout ; -wire \z80_|pla_decode_|Equal6~0_combout ; -wire \z80_|execute_|ctl_mRead~14_combout ; -wire \z80_|pla_decode_|Equal12~0_combout ; -wire \z80_|execute_|ctl_sw_1d~8_combout ; -wire \z80_|nM1_int~2_combout ; -wire \z80_|execute_|ctl_sw_1d~5_combout ; -wire \z80_|pla_decode_|Equal3~0_combout ; -wire \z80_|execute_|ctl_mRead~4_combout ; -wire \z80_|execute_|ixy_d~7_combout ; -wire \z80_|execute_|ctl_state_alu~4_combout ; -wire \z80_|execute_|ctl_sw_1d~4_combout ; -wire \z80_|pla_decode_|Equal40~1_combout ; -wire \z80_|pla_decode_|Equal39~0_combout ; -wire \z80_|execute_|ctl_bus_db_oe~1_combout ; -wire \z80_|pla_decode_|Equal13~1_combout ; -wire \z80_|pla_decode_|Equal13~2_combout ; -wire \z80_|pla_decode_|Equal3~2_combout ; -wire \z80_|execute_|ctl_state_iy_set~2_combout ; -wire \z80_|execute_|ixy_d~8_combout ; -wire \z80_|execute_|ixy_d~6_combout ; -wire \z80_|execute_|ixy_d~9_combout ; -wire \z80_|execute_|ixy_d~12_combout ; -wire \z80_|execute_|ixy_d~10_combout ; -wire \z80_|pla_decode_|Equal44~0_combout ; -wire \z80_|execute_|ixy_d~16_combout ; -wire \z80_|execute_|ixy_d~13_combout ; -wire \z80_|pla_decode_|Equal50~0_combout ; -wire \z80_|pla_decode_|Equal33~2_combout ; -wire \z80_|execute_|ixy_d~17_combout ; -wire \z80_|execute_|ixy_d~5_combout ; -wire \z80_|execute_|ixy_d~14_combout ; -wire \z80_|execute_|ixy_d~11_combout ; -wire \z80_|execute_|ixy_d~15_combout ; -wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; -wire \z80_|decode_state_|DFFE_instIY1~q ; -wire \z80_|execute_|ctl_ir_we~5_combout ; -wire \z80_|execute_|ctl_ir_we~14_combout ; -wire \z80_|execute_|ctl_mWrite~2_combout ; -wire \z80_|execute_|ctl_mWrite~16_combout ; -wire \z80_|execute_|ctl_flags_alu~18_combout ; -wire \z80_|execute_|ctl_mRead~26_combout ; -wire \z80_|execute_|ctl_mRead~27_combout ; -wire \z80_|execute_|ctl_bus_db_oe~7_combout ; -wire \z80_|execute_|ctl_sw_2d~5_combout ; -wire \z80_|execute_|ctl_mRead~18_combout ; -wire \z80_|pla_decode_|Equal55~0_combout ; -wire \z80_|execute_|comb~1_combout ; -wire \z80_|execute_|ctl_mRead~15_combout ; -wire \z80_|execute_|ctl_mRead~17_combout ; -wire \z80_|execute_|ctl_reg_in_hi~5_combout ; -wire \z80_|execute_|ctl_mRead~9_combout ; -wire \z80_|pla_decode_|Equal9~0_combout ; -wire \z80_|execute_|ctl_mRead~10_combout ; -wire \z80_|execute_|ctl_mRead~8_combout ; -wire \z80_|execute_|ctl_mRead~20_combout ; -wire \z80_|pla_decode_|Equal12~1_combout ; -wire \z80_|pla_decode_|Equal9~1_combout ; -wire \z80_|pla_decode_|Equal25~0_combout ; -wire \z80_|execute_|ctl_mRead~21_combout ; -wire \z80_|execute_|ctl_state_alu~6_combout ; -wire \z80_|pla_decode_|Equal19~0_combout ; -wire \z80_|pla_decode_|Equal1~4_combout ; -wire \z80_|pla_decode_|Equal29~0_combout ; -wire \z80_|pla_decode_|Equal24~1_combout ; -wire \z80_|pla_decode_|Equal34~0_combout ; -wire \z80_|pla_decode_|Equal37~0_combout ; -wire \z80_|pla_decode_|Equal35~0_combout ; -wire \z80_|pla_decode_|Equal38~2_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; -wire \z80_|execute_|comb~0_combout ; -wire \z80_|pla_decode_|Equal47~0_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; -wire \z80_|execute_|ctl_mRead~22_combout ; -wire \z80_|execute_|ctl_mRead~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_in_hi~6_combout ; -wire \z80_|pla_decode_|Equal6~1_combout ; -wire \z80_|execute_|ctl_mRead~16_combout ; -wire \z80_|sequencer_|M5~0_combout ; -wire \z80_|sequencer_|M5~q ; -wire \z80_|execute_|ctl_reg_in_hi~2_combout ; -wire \z80_|execute_|setM1~29_combout ; -wire \z80_|execute_|ctl_mRead~25_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; -wire \z80_|execute_|ctl_ir_we~7_combout ; -wire \z80_|pla_decode_|Equal52~1_combout ; -wire \z80_|execute_|ctl_state_alu~14_combout ; -wire \z80_|execute_|ctl_state_alu~8_combout ; -wire \z80_|pla_decode_|Equal24~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~1_combout ; -wire \z80_|reg_control_|reg_sel_pc~2_combout ; -wire \z80_|execute_|fMRead~17_combout ; -wire \z80_|execute_|ctl_mRead~6_combout ; -wire \z80_|pla_decode_|Equal11~0_combout ; -wire \z80_|pla_decode_|Equal10~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; -wire \z80_|execute_|ctl_sw_2d~4_combout ; -wire \z80_|execute_|ctl_ir_we~15_combout ; -wire \z80_|execute_|fMRead~16_combout ; -wire \z80_|execute_|ctl_ir_we~9_combout ; -wire \z80_|pla_decode_|Equal46~0_combout ; -wire \z80_|execute_|ctl_ir_we~10_combout ; -wire \z80_|execute_|ctl_flags_alu~17_combout ; -wire \z80_|execute_|ctl_flags_alu~6_combout ; -wire \z80_|execute_|ctl_ir_we~6_combout ; -wire \z80_|execute_|ctl_ir_we~8_combout ; -wire \z80_|execute_|ctl_flags_alu~16_combout ; -wire \z80_|execute_|ctl_reg_in_hi~3_combout ; -wire \z80_|execute_|ctl_mWrite~8_combout ; -wire \z80_|execute_|fMRead~18_combout ; -wire \z80_|execute_|fMRead~19_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; -wire \z80_|execute_|ctl_mRead~36_combout ; -wire \z80_|execute_|ctl_alu_op_low~9_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; -wire \z80_|execute_|ctl_mRead~11_combout ; -wire \z80_|execute_|ctl_sw_2d~6_combout ; -wire \z80_|execute_|ctl_sw_2d~7_combout ; -wire \z80_|execute_|ctl_mWrite~7_combout ; -wire \z80_|execute_|ctl_ir_we~11_combout ; -wire \z80_|execute_|ctl_ir_we~12_combout ; -wire \z80_|execute_|ctl_flags_sz_we~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; -wire \z80_|execute_|ctl_sw_2d~8_combout ; -wire \z80_|execute_|ctl_sw_2d~9_combout ; -wire \z80_|execute_|ctl_sw_1d~6_combout ; -wire \z80_|execute_|ctl_sw_1d~7_combout ; -wire \z80_|execute_|ctl_alu_op_low~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; -wire \z80_|execute_|ctl_reg_out_hi~4_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; -wire \z80_|alu_|db_low[2]~4_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ; -wire \z80_|execute_|ctl_sw_4u~1_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; -wire \z80_|pla_decode_|Equal69~0_combout ; -wire \z80_|pla_decode_|Equal1~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~14_combout ; -wire \z80_|execute_|ctl_alu_op_low~12_combout ; -wire \z80_|pla_decode_|Equal56~0_combout ; -wire \z80_|execute_|ctl_alu_op_low~11_combout ; -wire \z80_|execute_|nextM~2_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~5_combout ; -wire \z80_|execute_|ctl_alu_oe~3_combout ; -wire \z80_|execute_|ctl_alu_op_low~15_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; -wire \z80_|execute_|ctl_alu_core_R~3_combout ; -wire \z80_|execute_|ctl_alu_core_R~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; -wire \z80_|pla_decode_|Equal48~0_combout ; -wire \z80_|execute_|ctl_flags_hf2_we~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; -wire \z80_|execute_|ctl_flags_xy_we~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; -wire \z80_|execute_|ctl_iorw~10_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~13_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; -wire \z80_|execute_|ctl_bus_db_oe~3_combout ; -wire \z80_|pla_decode_|Equal20~0_combout ; -wire \z80_|pla_decode_|Equal68~2_combout ; -wire \z80_|execute_|ctl_flags_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op_low~13_combout ; -wire \z80_|execute_|ctl_flags_bus~15_combout ; -wire \z80_|execute_|ctl_flags_bus~11_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ; -wire \z80_|execute_|ctl_flags_bus~10_combout ; -wire \z80_|execute_|ctl_flags_bus~8_combout ; -wire \z80_|execute_|ctl_flags_bus~9_combout ; -wire \z80_|execute_|ctl_flags_bus~12_combout ; -wire \z80_|execute_|ctl_flags_xy_we~11_combout ; -wire \z80_|execute_|ctl_flags_xy_we~12_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; -wire \z80_|execute_|ctl_ir_we~4_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; -wire \z80_|execute_|ctl_bus_db_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; -wire \z80_|execute_|ctl_66_oe~2_combout ; -wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; -wire \z80_|execute_|ctl_alu_op_low~10_combout ; -wire \z80_|execute_|fMWrite~11_combout ; -wire \z80_|execute_|ctl_alu_op_low~21_combout ; -wire \z80_|execute_|ctl_alu_op_low~22_combout ; -wire \z80_|execute_|ctl_alu_op_low~16_combout ; -wire \z80_|execute_|ctl_alu_op_low~17_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; -wire \z80_|execute_|ctl_reg_gp_sel~36_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~4_combout ; -wire \z80_|execute_|ctl_state_alu~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~18_combout ; -wire \z80_|execute_|ctl_alu_op_low~19_combout ; -wire \z80_|execute_|ctl_alu_op_low~33_combout ; -wire \z80_|execute_|ctl_alu_op_low~20_combout ; -wire \z80_|execute_|ctl_alu_op_low~23_combout ; -wire \z80_|execute_|ctl_alu_op_low~24_combout ; -wire \z80_|execute_|ctl_alu_op_low~25_combout ; -wire \z80_|execute_|ctl_alu_op_low~34_combout ; -wire \z80_|execute_|ctl_alu_op_low~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~14_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; -wire \z80_|execute_|ctl_reg_use_sp~0_combout ; -wire \z80_|execute_|ctl_reg_use_sp~1_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; -wire \z80_|execute_|ctl_reg_in_lo~9_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; -wire \z80_|execute_|ctl_flags_xy_we~8_combout ; -wire \z80_|execute_|ctl_flags_xy_we~9_combout ; -wire \z80_|pla_decode_|Equal8~0_combout ; -wire \z80_|execute_|ctl_flags_alu~9_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; -wire \z80_|execute_|ctl_flags_sz_we~3_combout ; -wire \z80_|pla_decode_|Equal11~1_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; -wire \z80_|execute_|ctl_flags_alu~10_combout ; -wire \z80_|execute_|ctl_flags_alu~11_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; -wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; -wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; -wire \z80_|execute_|ctl_flags_cf_we~7_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~2_combout ; -wire \z80_|execute_|ctl_alu_oe~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~25_combout ; -wire \z80_|execute_|ctl_flags_hf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; -wire \z80_|execute_|ctl_flags_pf_we~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~3_combout ; -wire \z80_|execute_|ctl_flags_xy_we~17_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; -wire \z80_|execute_|ctl_flags_xy_we~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; -wire \z80_|execute_|ctl_state_alu~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~1_combout ; -wire \z80_|execute_|ctl_flags_cf_we~2_combout ; -wire \z80_|execute_|ctl_alu_core_S~6_combout ; -wire \z80_|execute_|ctl_alu_core_S~7_combout ; -wire \z80_|execute_|ctl_alu_core_S~4_combout ; -wire \z80_|execute_|ctl_alu_core_S~5_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; -wire \z80_|execute_|ctl_alu_res_oe~0_combout ; -wire \z80_|execute_|ctl_alu_oe~15_combout ; -wire \z80_|execute_|ctl_alu_res_oe~1_combout ; -wire \z80_|execute_|ctl_alu_res_oe~2_combout ; -wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; -wire \z80_|alu_|db_high[3]~2_combout ; -wire \z80_|alu_|db_high[3]~3_combout ; -wire \z80_|alu_|db_low[2]~24_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~7_combout ; -wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_in_hi~8_combout ; -wire \z80_|execute_|ctl_alu_oe~8_combout ; -wire \z80_|execute_|ctl_alu_oe~4_combout ; -wire \z80_|execute_|ctl_mWrite~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~10_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; -wire \z80_|execute_|ctl_bus_db_we~5_combout ; -wire \z80_|execute_|ctl_alu_oe~9_combout ; -wire \z80_|execute_|ctl_alu_oe~11_combout ; -wire \z80_|execute_|ctl_alu_oe~5_combout ; -wire \z80_|execute_|ctl_alu_core_S~11_combout ; -wire \z80_|execute_|ctl_alu_oe~6_combout ; -wire \z80_|execute_|ctl_alu_oe~7_combout ; -wire \z80_|execute_|ctl_alu_oe~12_combout ; -wire \z80_|execute_|ctl_alu_oe~13_combout ; -wire \z80_|execute_|ctl_alu_oe~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ; -wire \z80_|execute_|ctl_reg_out_hi~8_combout ; -wire \z80_|execute_|setM1~54_combout ; -wire \z80_|execute_|ctl_sw_2u~1_combout ; -wire \z80_|execute_|ctl_sw_2u~4_combout ; -wire \z80_|execute_|ctl_sw_2u~5_combout ; -wire \z80_|execute_|ctl_sw_2u~6_combout ; -wire \z80_|execute_|ctl_inc_cy~35_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; -wire \z80_|execute_|ctl_mWrite~6_combout ; -wire \z80_|execute_|ctl_sw_2u~2_combout ; -wire \z80_|execute_|ctl_sw_2u~0_combout ; -wire \z80_|execute_|ctl_sw_2u~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; -wire \z80_|execute_|ctl_reg_out_lo~2_combout ; -wire \z80_|execute_|rsel3~combout ; -wire \z80_|execute_|ctl_reg_out_hi~5_combout ; -wire \z80_|execute_|ctl_reg_out_hi~6_combout ; -wire \z80_|execute_|ctl_reg_out_hi~7_combout ; -wire \z80_|execute_|rsel0~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ; -wire \z80_|execute_|ctl_reg_out_lo~6_combout ; -wire \z80_|execute_|ctl_reg_out_lo~7_combout ; -wire \z80_|execute_|ctl_iorw~11_combout ; -wire \z80_|execute_|ctl_sw_2d~10_combout ; -wire \z80_|execute_|ctl_sw_2d~14_combout ; -wire \z80_|execute_|ctl_sw_2d~11_combout ; -wire \z80_|execute_|ctl_sw_2d~12_combout ; -wire \z80_|execute_|ctl_sw_2d~13_combout ; -wire \z80_|execute_|ctl_66_oe~combout ; -wire \z80_|execute_|ctl_inc_cy~34_combout ; -wire \z80_|execute_|ctl_apin_mux~0_combout ; -wire \z80_|execute_|ctl_sw_4u~5_combout ; -wire \z80_|execute_|ctl_inc_cy~75_combout ; -wire \z80_|execute_|ctl_inc_cy~76_combout ; -wire \z80_|pla_decode_|Equal4~0_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; -wire \z80_|execute_|ctl_inc_cy~53_combout ; -wire \z80_|execute_|ctl_inc_cy~92_combout ; -wire \z80_|pla_decode_|Equal19~1_combout ; -wire \z80_|execute_|ctl_sw_4u~0_combout ; -wire \z80_|execute_|ctl_inc_cy~38_combout ; -wire \z80_|execute_|ctl_inc_cy~93_combout ; -wire \z80_|execute_|ctl_inc_cy~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~24_combout ; -wire \z80_|execute_|ctl_reg_gp_we~1_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; -wire \z80_|execute_|ctl_reg_gp_we~0_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; -wire \z80_|execute_|ctl_sw_4u~2_combout ; -wire \z80_|execute_|ctl_sw_4u~3_combout ; -wire \z80_|execute_|fMRead~3_combout ; -wire \z80_|execute_|ctl_sw_4u~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ; -wire \z80_|execute_|ctl_inc_cy~94_combout ; -wire \z80_|execute_|ctl_inc_cy~87_combout ; -wire \z80_|execute_|ctl_inc_cy~42_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; -wire \z80_|execute_|ctl_sw_4u~6_combout ; -wire \z80_|pla_decode_|Equal2~2_combout ; -wire \z80_|pla_decode_|Equal1~6_combout ; -wire \z80_|reg_control_|bank_exx~2_combout ; -wire \z80_|reg_control_|bank_exx~q ; -wire \z80_|reg_control_|bank_hl_de1~0_combout ; -wire \z80_|reg_control_|bank_hl_de1~q ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~12_combout ; -wire \z80_|execute_|ctl_mRead~7_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~13_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; -wire \z80_|execute_|fMWrite~3_combout ; -wire \z80_|execute_|ctl_flags_bus~5_combout ; -wire \z80_|execute_|fMRead~2_combout ; -wire \z80_|execute_|ctl_mRead~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~7_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; -wire \z80_|execute_|ctl_reg_use_sp~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; -wire \z80_|execute_|ctl_reg_use_sp~3_combout ; -wire \z80_|execute_|ctl_sw_1d~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~21_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~22_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~14_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; -wire \z80_|execute_|setM1~47_combout ; -wire \z80_|execute_|setM1~48_combout ; -wire \z80_|execute_|ctl_al_we~13_combout ; -wire \z80_|execute_|ctl_flags_oe~0_combout ; -wire \z80_|execute_|ctl_flags_oe~1_combout ; -wire \z80_|execute_|ctl_reg_in_hi~13_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; -wire \z80_|execute_|ctl_inc_cy~40_combout ; -wire \z80_|execute_|ctl_inc_dec~2_combout ; -wire \z80_|execute_|ctl_inc_dec~12_combout ; -wire \z80_|execute_|ctl_inc_cy~43_combout ; -wire \z80_|execute_|ctl_inc_dec~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; -wire \z80_|execute_|fMRead~6_combout ; -wire \z80_|execute_|fMRead~7_combout ; -wire \z80_|execute_|fMRead~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; -wire \z80_|execute_|ctl_state_alu~13_combout ; -wire \z80_|execute_|ctl_state_alu~10_combout ; -wire \z80_|execute_|ctl_state_alu~11_combout ; -wire \z80_|execute_|ctl_state_alu~9_combout ; -wire \z80_|pla_decode_|Equal62~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; -wire \z80_|pla_decode_|Equal64~0_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_state_alu~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; -wire \z80_|reg_control_|reg_sel_de2~5_combout ; -wire \z80_|reg_control_|reg_sel_de2~6_combout ; -wire \z80_|reg_control_|reg_sel_hl~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~q ; -wire \z80_|reg_control_|reg_sel_hl2~0_combout ; -wire \z80_|execute_|ctl_reg_in_hi~7_combout ; -wire \z80_|execute_|ctl_reg_gp_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_we~3_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_we~2_combout ; -wire \z80_|execute_|ctl_reg_gp_we~5_combout ; -wire \z80_|execute_|ctl_reg_gp_we~6_combout ; -wire \z80_|execute_|ctl_al_we~14_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; -wire \z80_|execute_|setM1~40_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~93_combout ; -wire \z80_|reg_control_|reg_sel_de~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; -wire \z80_|execute_|ctl_reg_in_hi~9_combout ; -wire \z80_|execute_|ctl_reg_in_hi~10_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; -wire \z80_|execute_|ctl_reg_in_lo~8_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; -wire \z80_|execute_|ctl_reg_use_sp~4_combout ; -wire \z80_|execute_|ctl_reg_use_sp~5_combout ; -wire \z80_|execute_|ctl_reg_use_sp~6_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; -wire \z80_|pla_decode_|Equal21~2_combout ; -wire \z80_|reg_control_|bank_af~0_combout ; -wire \z80_|reg_control_|bank_af~q ; -wire \z80_|reg_control_|reg_sel_af~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|reg_control_|reg_sel_af2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; -wire \z80_|execute_|ctl_flags_bus~4_combout ; -wire \z80_|execute_|ctl_flags_bus~6_combout ; -wire \z80_|execute_|ctl_flags_bus~7_combout ; -wire \z80_|execute_|fMRead~24_combout ; -wire \z80_|execute_|ctl_flags_bus~13_combout ; -wire \z80_|execute_|ctl_flags_bus~combout ; -wire \z80_|execute_|ctl_inc_dec~3_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; -wire \z80_|execute_|ctl_mRead~13_combout ; -wire \z80_|execute_|pc_inc_hold~49_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; -wire \z80_|execute_|pc_inc_hold~28_combout ; -wire \z80_|execute_|setM1~35_combout ; -wire \z80_|execute_|setM1~36_combout ; -wire \z80_|execute_|fMRead~5_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; -wire \z80_|execute_|pc_inc_hold~29_combout ; -wire \z80_|execute_|ctl_reg_sys_we~1_combout ; -wire \z80_|execute_|ctl_reg_sys_we~2_combout ; -wire \z80_|pla_decode_|Equal33~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~2_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~4_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~combout ; -wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; -wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; -wire \z80_|execute_|ctl_reg_out_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; -wire \z80_|execute_|ctl_reg_in_hi~4_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~5_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; -wire \z80_|execute_|ctl_al_we~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; -wire \z80_|execute_|fMRead~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; -wire \z80_|execute_|ctl_inc_dec~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; -wire \z80_|execute_|ctl_al_we~5_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; -wire \z80_|execute_|fMRead~1_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; -wire \z80_|execute_|ctl_inc_cy~77_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; -wire \z80_|execute_|ctl_sw_4d~3_combout ; -wire \z80_|execute_|ctl_sw_4d~4_combout ; -wire \z80_|execute_|ctl_sw_4d~2_combout ; -wire \z80_|execute_|ctl_sw_4d~5_combout ; -wire \z80_|execute_|setM1~45_combout ; -wire \z80_|execute_|setM1~46_combout ; -wire \z80_|execute_|ctl_sw_4d~1_combout ; -wire \z80_|execute_|ctl_sw_4d~0_combout ; -wire \z80_|execute_|ctl_sw_4d~6_combout ; -wire \z80_|execute_|fMRead~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~20_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; -wire \z80_|reg_control_|reg_sel_pc~3_combout ; -wire \z80_|reg_control_|reg_sel_pc~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; -wire \z80_|reg_file_|db_lo_as[0]~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; -wire \z80_|reg_file_|db_lo_as[7]~22_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; -wire \z80_|reg_file_|db_lo_as[7]~23_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; -wire \z80_|resets_|DFFE_intr_ff3~q ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ; wire \KEY[0]~input_o ; wire \reset~combout ; @@ -872,77 +263,13 @@ wire \z80_|fpga_reset~feeder_combout ; wire \z80_|fpga_reset~q ; wire \z80_|fpga_reset~clkctrl_outclk ; wire \z80_|resets_|x1~q ; -wire \z80_|resets_|clrpc_int~0_combout ; -wire \z80_|resets_|clrpc_int~q ; -wire \z80_|resets_|clrpc~0_combout ; -wire \z80_|execute_|ctl_apin_mux~1_combout ; -wire \z80_|execute_|ctl_al_we~6_combout ; -wire \z80_|execute_|ctl_al_we~7_combout ; -wire \z80_|execute_|ctl_al_we~8_combout ; -wire \z80_|execute_|ctl_alu_oe~10_combout ; -wire \z80_|execute_|ctl_al_we~9_combout ; -wire \z80_|execute_|ctl_al_we~10_combout ; -wire \z80_|execute_|ctl_al_we~11_combout ; -wire \z80_|execute_|ctl_al_we~12_combout ; -wire \z80_|execute_|ctl_inc_dec~6_combout ; -wire \z80_|execute_|fIOWrite~0_combout ; -wire \z80_|execute_|ctl_inc_dec~8_combout ; -wire \z80_|execute_|ctl_inc_dec~9_combout ; -wire \z80_|execute_|ctl_inc_dec~10_combout ; -wire \z80_|execute_|ctl_inc_dec~7_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; -wire \z80_|reg_control_|reg_sel_de2~4_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; -wire \z80_|reg_control_|reg_sel_iy~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; -wire \z80_|reg_file_|db_lo_as[2]~7_combout ; -wire \z80_|reg_file_|db_lo_as[2]~8_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; -wire \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; -wire \z80_|reg_file_|db_lo_as[0]~0_combout ; -wire \z80_|reg_file_|db_lo_as[0]~1_combout ; -wire \z80_|execute_|ctl_inc_cy~72_combout ; +wire \z80_|resets_|x3~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; +wire \z80_|interrupts_|nmi_armed~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; -wire \ula_|video_|Add0~15 ; -wire \ula_|video_|Add0~16_combout ; -wire \ula_|video_|vga_hc~2_combout ; -wire \ula_|video_|Add0~17 ; -wire \ula_|video_|Add0~18_combout ; -wire \ula_|video_|vga_hc~1_combout ; wire \ula_|video_|Add0~0_combout ; wire \ula_|video_|vga_hc~3_combout ; wire \ula_|video_|Add0~1 ; @@ -952,12 +279,8 @@ wire \ula_|video_|Add0~3 ; wire \ula_|video_|Add0~4_combout ; wire \ula_|video_|Add0~5 ; wire \ula_|video_|Add0~6_combout ; -wire \ula_|video_|vga_hc[3]~feeder_combout ; wire \ula_|video_|Add0~7 ; wire \ula_|video_|Add0~8_combout ; -wire \ula_|video_|Equal0~0_combout ; -wire \ula_|video_|Equal0~1_combout ; -wire \ula_|video_|Equal1~0_combout ; wire \ula_|video_|Add0~9 ; wire \ula_|video_|Add0~10_combout ; wire \ula_|video_|vga_hc~0_combout ; @@ -965,7 +288,18 @@ wire \ula_|video_|Add0~11 ; wire \ula_|video_|Add0~12_combout ; wire \ula_|video_|Add0~13 ; wire \ula_|video_|Add0~14_combout ; -wire \ula_|video_|Add1~0_combout ; +wire \ula_|video_|Equal0~0_combout ; +wire \ula_|video_|Equal0~1_combout ; +wire \ula_|video_|Add0~15 ; +wire \ula_|video_|Add0~16_combout ; +wire \ula_|video_|vga_hc~2_combout ; +wire \ula_|video_|Add0~17 ; +wire \ula_|video_|Add0~18_combout ; +wire \ula_|video_|vga_hc~1_combout ; +wire \ula_|video_|Equal1~0_combout ; +wire \ula_|video_|Add1~1 ; +wire \ula_|video_|Add1~2_combout ; +wire \ula_|video_|vga_vc[1]~1_combout ; wire \ula_|video_|Add1~3 ; wire \ula_|video_|Add1~4_combout ; wire \ula_|video_|vga_vc[2]~2_combout ; @@ -990,809 +324,1661 @@ wire \ula_|video_|vga_vc[8]~7_combout ; wire \ula_|video_|Add1~17 ; wire \ula_|video_|Add1~18_combout ; wire \ula_|video_|vga_vc[9]~9_combout ; -wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Equal3~0_combout ; +wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Equal3~1_combout ; +wire \ula_|video_|Add1~0_combout ; wire \ula_|video_|vga_vc[0]~0_combout ; -wire \ula_|video_|Add1~1 ; -wire \ula_|video_|Add1~2_combout ; -wire \ula_|video_|vga_vc[1]~1_combout ; -wire \SW[1]~input_o ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; -wire \z80_|pla_decode_|Equal79~0_combout ; -wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \z80_|interrupts_|DFFE_instIFF2~q ; -wire \z80_|interrupts_|iff1~0_combout ; -wire \z80_|interrupts_|iff1~1_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|interrupts_|iff1~q ; wire \ula_|video_|Equal2~1_combout ; wire \ula_|video_|Equal2~2_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ; -wire \z80_|interrupts_|int_armed~q ; -wire \z80_|interrupts_|DFFE_inst44~q ; -wire \z80_|execute_|pc_inc_hold~38_combout ; -wire \z80_|execute_|ctl_inc_cy~91_combout ; -wire \z80_|execute_|pc_inc_hold~45_combout ; -wire \z80_|execute_|pc_inc_hold~44_combout ; -wire \z80_|execute_|pc_inc_hold~46_combout ; -wire \z80_|execute_|pc_inc_hold~37_combout ; -wire \z80_|execute_|pc_inc_hold~50_combout ; -wire \z80_|execute_|pc_inc_hold~33_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; -wire \z80_|execute_|pc_inc_hold~31_combout ; -wire \z80_|execute_|pc_inc_hold~32_combout ; -wire \z80_|execute_|pc_inc_hold~34_combout ; -wire \z80_|execute_|pc_inc_hold~51_combout ; -wire \z80_|execute_|pc_inc_hold~30_combout ; -wire \z80_|execute_|pc_inc_hold~52_combout ; -wire \z80_|execute_|pc_inc_hold~35_combout ; -wire \z80_|execute_|pc_inc_hold~36_combout ; -wire \z80_|execute_|ctl_inc_cy~44_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; -wire \z80_|execute_|ctl_inc_cy~45_combout ; -wire \z80_|execute_|pc_inc_hold~43_combout ; -wire \z80_|execute_|ctl_inc_cy~71_combout ; -wire \z80_|execute_|ctl_inc_cy~73_combout ; +wire \SW[1]~input_o ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; +wire \z80_|execute_|ctl_mWrite~4_combout ; +wire \z80_|pla_decode_|Equal0~0_combout ; +wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M3_ff~q ; +wire \z80_|execute_|ixy_d~6_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ; +wire \z80_|pla_decode_|Equal33~0_combout ; +wire \z80_|execute_|ctl_mRead~5_combout ; +wire \z80_|pla_decode_|Equal77~0_combout ; +wire \z80_|pla_decode_|Equal50~0_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ; +wire \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ; +wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; +wire \z80_|clk_delay_|DFF_inst5~q ; +wire \z80_|clk_delay_|hold_clk_iorq~combout ; +wire \z80_|sequencer_|DFFE_T5_ff~q ; +wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; +wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; +wire \z80_|decode_state_|DFFE_inst4~q ; +wire \z80_|execute_|fMWrite~3_combout ; +wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M4_ff~q ; +wire \z80_|execute_|fMWrite~2_combout ; +wire \z80_|pla_decode_|Equal13~1_combout ; +wire \z80_|pla_decode_|Equal13~2_combout ; +wire \z80_|execute_|ixy_d~4_combout ; +wire \z80_|execute_|fIOWrite~1_combout ; +wire \z80_|execute_|ctl_mWrite~5_combout ; +wire \z80_|execute_|fMRead~2_combout ; +wire \z80_|execute_|ctl_state_alu~2_combout ; +wire \z80_|execute_|ctl_iorw~11_combout ; +wire \z80_|execute_|fIOWrite~2_combout ; +wire \z80_|pla_decode_|Equal2~0_combout ; +wire \z80_|decode_state_|table_xx~0_combout ; +wire \z80_|pla_decode_|Equal1~7_combout ; +wire \z80_|pla_decode_|Equal21~0_combout ; +wire \z80_|execute_|ctl_mRead~3_combout ; +wire \z80_|execute_|fIOWrite~3_combout ; +wire \z80_|execute_|ixy_d~5_combout ; +wire \z80_|execute_|fIOWrite~4_combout ; +wire \z80_|execute_|fIOWrite~5_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; +wire \z80_|execute_|ctl_state_alu~3_combout ; +wire \z80_|pla_decode_|Equal3~1_combout ; +wire \z80_|execute_|ctl_mWrite~6_combout ; +wire \z80_|execute_|ctl_ir_we~4_combout ; +wire \z80_|pla_decode_|Equal9~0_combout ; +wire \z80_|pla_decode_|Equal9~1_combout ; +wire \z80_|execute_|ctl_sw_2u~0_combout ; +wire \z80_|pla_decode_|Equal11~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~14_combout ; wire \z80_|execute_|ctl_inc_cy~46_combout ; -wire \z80_|execute_|pc_inc_hold~53_combout ; -wire \z80_|execute_|pc_inc_hold~39_combout ; -wire \z80_|execute_|pc_inc_hold~47_combout ; -wire \z80_|execute_|ctl_inc_cy~74_combout ; -wire \z80_|execute_|ctl_inc_cy~78_combout ; -wire \z80_|execute_|ctl_inc_cy~79_combout ; -wire \z80_|execute_|ctl_inc_cy~80_combout ; -wire \z80_|execute_|ctl_inc_cy~81_combout ; -wire \z80_|execute_|ctl_inc_cy~82_combout ; -wire \z80_|execute_|ctl_inc_cy~83_combout ; -wire \z80_|execute_|ctl_inc_cy~84_combout ; -wire \z80_|execute_|pc_inc_hold~42_combout ; -wire \z80_|execute_|ctl_inc_cy~90_combout ; -wire \z80_|execute_|pc_inc_hold~41_combout ; -wire \z80_|execute_|ctl_inc_cy~66_combout ; -wire \z80_|execute_|ctl_inc_cy~67_combout ; -wire \z80_|execute_|ctl_inc_cy~68_combout ; -wire \z80_|execute_|ctl_inc_cy~64_combout ; -wire \z80_|execute_|ctl_inc_cy~63_combout ; -wire \z80_|execute_|ctl_inc_cy~65_combout ; -wire \z80_|execute_|ctl_inc_cy~69_combout ; -wire \z80_|execute_|ctl_inc_cy~49_combout ; -wire \z80_|execute_|ctl_inc_cy~50_combout ; -wire \z80_|execute_|ctl_inc_cy~51_combout ; -wire \z80_|execute_|ctl_inc_cy~52_combout ; -wire \z80_|execute_|ctl_inc_cy~36_combout ; -wire \z80_|execute_|ctl_inc_cy~37_combout ; -wire \z80_|execute_|ctl_inc_cy~54_combout ; -wire \z80_|execute_|ctl_inc_cy~41_combout ; -wire \z80_|execute_|ctl_inc_cy~58_combout ; -wire \z80_|execute_|ctl_inc_cy~55_combout ; -wire \z80_|execute_|ctl_inc_cy~56_combout ; -wire \z80_|execute_|ctl_inc_cy~89_combout ; -wire \z80_|execute_|ctl_inc_cy~57_combout ; -wire \z80_|execute_|ctl_inc_cy~59_combout ; -wire \z80_|execute_|ctl_inc_cy~60_combout ; wire \z80_|execute_|ctl_inc_cy~47_combout ; -wire \z80_|execute_|ctl_inc_cy~88_combout ; +wire \z80_|pla_decode_|Equal19~0_combout ; +wire \z80_|pla_decode_|Equal34~0_combout ; +wire \z80_|execute_|comb~0_combout ; +wire \z80_|pla_decode_|Equal47~0_combout ; +wire \z80_|execute_|ctl_inc_cy~45_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; +wire \z80_|sequencer_|M5~0_combout ; +wire \z80_|sequencer_|M5~q ; +wire \z80_|execute_|ctl_alu_oe~2_combout ; +wire \z80_|execute_|ixy_d~7_combout ; +wire \z80_|execute_|ctl_inc_cy~44_combout ; +wire \z80_|execute_|ctl_apin_mux~0_combout ; +wire \z80_|execute_|ctl_mRead~4_combout ; +wire \z80_|execute_|ctl_ir_we~5_combout ; +wire \z80_|execute_|ctl_ir_we~15_combout ; +wire \z80_|execute_|ctl_ir_we~14_combout ; +wire \z80_|execute_|ctl_ir_we~7_combout ; +wire \z80_|execute_|fMWrite~0_combout ; +wire \z80_|execute_|ctl_inc_cy~97_combout ; +wire \z80_|execute_|ctl_inc_cy~96_combout ; +wire \z80_|execute_|ctl_inc_cy~98_combout ; wire \z80_|execute_|ctl_inc_cy~48_combout ; -wire \z80_|execute_|pc_inc_hold~40_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; +wire \z80_|execute_|fMWrite~1_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; +wire \z80_|execute_|ctl_mRead~6_combout ; +wire \z80_|execute_|ctl_reg_in_hi~2_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; +wire \z80_|execute_|ctl_mWrite~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; +wire \z80_|execute_|ctl_mWrite~17_combout ; +wire \z80_|execute_|fMWrite~4_combout ; +wire \z80_|execute_|ctl_state_alu~4_combout ; +wire \z80_|execute_|ctl_inc_cy~49_combout ; +wire \z80_|execute_|ctl_inc_dec~2_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; +wire \z80_|execute_|fMWrite~8_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~51_combout ; +wire \z80_|execute_|ctl_ir_we~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~10_combout ; +wire \z80_|pla_decode_|Equal46~0_combout ; +wire \z80_|execute_|ctl_ir_we~10_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; +wire \z80_|execute_|ctl_ir_we~6_combout ; +wire \z80_|execute_|ctl_ir_we~8_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; +wire \z80_|pla_decode_|Equal55~0_combout ; +wire \z80_|execute_|ctl_mRead~7_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; +wire \z80_|pin_control_|bus_db_pin_oe~17_combout ; +wire \z80_|execute_|fIOWrite~0_combout ; +wire \z80_|execute_|fMWrite~6_combout ; +wire \z80_|execute_|ctl_mWrite~8_combout ; +wire \z80_|execute_|fMWrite~5_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; +wire \z80_|execute_|fMRead~3_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; +wire \z80_|execute_|ctl_sw_4u~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ; +wire \z80_|execute_|fMWrite~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~15_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~16_combout ; +wire \z80_|execute_|ctl_mRead~9_combout ; +wire \z80_|pla_decode_|Equal24~0_combout ; +wire \z80_|execute_|nextM~4_combout ; +wire \z80_|pla_decode_|Equal3~0_combout ; +wire \z80_|execute_|ctl_eval_cond~0_combout ; +wire \z80_|execute_|ctl_iorw~12_combout ; +wire \z80_|execute_|ctl_iorw~8_combout ; +wire \z80_|execute_|ctl_iorw~9_combout ; +wire \z80_|memory_ifc_|DFFE_iorq_ff1~q ; +wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ; +wire \z80_|memory_ifc_|wait_iorq~feeder_combout ; +wire \z80_|memory_ifc_|wait_iorq~q ; +wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; +wire \z80_|memory_ifc_|iorq~0_combout ; +wire \z80_|pla_decode_|Equal33~2_combout ; +wire \z80_|execute_|ixy_d~17_combout ; +wire \z80_|execute_|ctl_mWrite~15_combout ; +wire \z80_|execute_|ctl_mWrite~18_combout ; +wire \z80_|execute_|ctl_mWrite~12_combout ; +wire \z80_|execute_|ctl_flags_alu~21_combout ; +wire \z80_|execute_|ctl_flags_alu~20_combout ; +wire \z80_|execute_|ctl_reg_in_hi~3_combout ; +wire \z80_|execute_|ctl_flags_alu~10_combout ; +wire \z80_|execute_|ctl_mWrite~10_combout ; +wire \z80_|execute_|ctl_mWrite~13_combout ; +wire \z80_|execute_|ixy_d~9_combout ; +wire \z80_|execute_|ctl_inc_cy~51_combout ; +wire \z80_|execute_|ctl_inc_dec~12_combout ; +wire \z80_|execute_|ctl_inc_dec~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; +wire \z80_|execute_|ctl_mWrite~11_combout ; +wire \z80_|execute_|ctl_mRead~25_combout ; +wire \z80_|execute_|ctl_flags_alu~22_combout ; +wire \z80_|execute_|ctl_mRead~24_combout ; +wire \z80_|execute_|ctl_bus_db_oe~7_combout ; +wire \z80_|execute_|ctl_mWrite~14_combout ; +wire \z80_|execute_|ixy_d~8_combout ; +wire \z80_|execute_|ctl_mWrite~16_combout ; +wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; +wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; +wire \z80_|memory_ifc_|wait_mwr~q ; +wire \z80_|memory_ifc_|mwr_wr~feeder_combout ; +wire \z80_|memory_ifc_|mwr_wr~q ; +wire \z80_|memory_ifc_|nWR_out~0_combout ; +wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; +wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; +wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; +wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; +wire \z80_|memory_ifc_|nRD_out~0_combout ; +wire \z80_|execute_|ctl_mRead~2_combout ; +wire \z80_|execute_|fIORead~0_combout ; +wire \z80_|execute_|ctl_iorw~10_combout ; +wire \z80_|pla_decode_|Equal1~4_combout ; +wire \z80_|execute_|ctl_alu_op_low~15_combout ; +wire \z80_|execute_|fIORead~1_combout ; +wire \z80_|execute_|fIORead~2_combout ; +wire \z80_|execute_|fIORead~3_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; +wire \z80_|execute_|ctl_im_we~combout ; +wire \z80_|interrupts_|im2~q ; +wire \z80_|execute_|ctl_mRead~10_combout ; +wire \z80_|pla_decode_|Equal33~3_combout ; +wire \z80_|pla_decode_|Equal6~1_combout ; +wire \z80_|execute_|ctl_mRead~30_combout ; +wire \z80_|execute_|ctl_mRead~31_combout ; +wire \z80_|execute_|ctl_ir_we~12_combout ; +wire \z80_|execute_|ctl_flags_bus~5_combout ; +wire \z80_|pla_decode_|Equal44~0_combout ; +wire \z80_|execute_|ctl_state_alu~6_combout ; +wire \z80_|execute_|fMRead~5_combout ; +wire \z80_|execute_|ctl_mRead~17_combout ; +wire \z80_|execute_|ctl_mRead~12_combout ; +wire \z80_|pla_decode_|Equal49~0_combout ; +wire \z80_|execute_|setM1~57_combout ; +wire \z80_|execute_|ctl_mRead~15_combout ; +wire \z80_|pla_decode_|Equal25~0_combout ; +wire \z80_|pla_decode_|Equal12~1_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; +wire \z80_|execute_|ixy_d~10_combout ; +wire \z80_|execute_|ixy_d~16_combout ; +wire \z80_|execute_|ctl_al_we~4_combout ; +wire \z80_|execute_|fMRead~4_combout ; +wire \z80_|pla_decode_|Equal29~0_combout ; +wire \z80_|execute_|setM1~38_combout ; +wire \z80_|pla_decode_|Equal35~0_combout ; +wire \z80_|execute_|pc_inc_hold~33_combout ; +wire \z80_|execute_|comb~1_combout ; +wire \z80_|execute_|ctl_mRead~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; +wire \z80_|pla_decode_|Equal40~2_combout ; +wire \z80_|execute_|setM1~36_combout ; +wire \z80_|execute_|pc_inc_hold~14_combout ; +wire \z80_|execute_|setM1~37_combout ; +wire \z80_|execute_|ctl_mRead~14_combout ; +wire \z80_|execute_|setM1~39_combout ; +wire \z80_|execute_|ctl_mRead~32_combout ; +wire \z80_|pla_decode_|Equal40~0_combout ; +wire \z80_|pla_decode_|Equal21~2_combout ; +wire \z80_|pla_decode_|Equal37~0_combout ; +wire \z80_|execute_|ctl_mRead~26_combout ; +wire \z80_|pla_decode_|Equal12~0_combout ; +wire \z80_|execute_|ctl_mRead~16_combout ; +wire \z80_|execute_|ctl_reg_in_hi~5_combout ; +wire \z80_|execute_|ctl_mRead~19_combout ; +wire \z80_|pla_decode_|Equal24~1_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~0_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~1_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; +wire \z80_|execute_|ctl_mRead~18_combout ; +wire \z80_|execute_|ctl_mRead~20_combout ; +wire \z80_|execute_|ctl_mRead~22_combout ; +wire \z80_|pla_decode_|Equal52~1_combout ; +wire \z80_|execute_|ctl_mRead~23_combout ; +wire \z80_|execute_|ctl_mRead~27_combout ; +wire \z80_|execute_|ctl_mRead~28_combout ; +wire \z80_|execute_|nextM~3_combout ; +wire \z80_|execute_|ctl_mRead~29_combout ; +wire \z80_|execute_|ctl_mRead~33_combout ; +wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; +wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; +wire \z80_|memory_ifc_|wait_mrd~q ; +wire \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ; +wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; +wire \z80_|memory_ifc_|nRD_out~1_combout ; +wire \z80_|memory_ifc_|nRD_out~2_combout ; +wire \Equal2~1_combout ; +wire \PS2_DAT~input_o ; +wire \reset~clkctrl_outclk ; +wire \ula_|ps2_keyboard_|bit_count~2_combout ; +wire \PS2_CLK~input_o ; +wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~0_combout ; +wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~1_combout ; +wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~q ; +wire \ula_|ps2_keyboard_|clk_edge~0_combout ; +wire \ula_|ps2_keyboard_|clk_edge~q ; +wire \ula_|ps2_keyboard_|bit_count~3_combout ; +wire \ula_|ps2_keyboard_|bit_count~1_combout ; +wire \ula_|ps2_keyboard_|bit_count~0_combout ; +wire \ula_|ps2_keyboard_|LessThan0~0_combout ; +wire \ula_|ps2_keyboard_|always1~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; +wire \ula_|zx_keyboard_|Equal0~0_combout ; +wire \ula_|zx_keyboard_|Equal0~1_combout ; +wire \ula_|ps2_keyboard_|WideXor0~1_combout ; +wire \ula_|ps2_keyboard_|WideXor0~0_combout ; +wire \ula_|ps2_keyboard_|WideXor0~2_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~q ; +wire \ula_|zx_keyboard_|released~0_combout ; +wire \ula_|zx_keyboard_|released~q ; +wire \ula_|zx_keyboard_|Equal0~2_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~50_combout ; +wire \ula_|zx_keyboard_|extended~0_combout ; +wire \ula_|zx_keyboard_|extended~q ; +wire \ula_|zx_keyboard_|keys[7][4]~15_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~52_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~53_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~q ; +wire \z80_|resets_|clrpc_int~0_combout ; +wire \z80_|resets_|clrpc_int~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; +wire \z80_|resets_|DFFE_intr_ff3~q ; +wire \z80_|resets_|clrpc~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; +wire \z80_|pla_decode_|Equal21~1_combout ; +wire \z80_|pla_decode_|Equal40~1_combout ; +wire \z80_|pla_decode_|Equal39~0_combout ; +wire \z80_|execute_|ctl_bus_db_oe~1_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; +wire \z80_|execute_|ctl_inc_dec~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; +wire \z80_|execute_|ctl_al_we~5_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; +wire \z80_|execute_|ctl_al_we~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; +wire \z80_|pla_decode_|Equal10~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~6_combout ; +wire \z80_|execute_|ctl_bus_db_oe~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ; +wire \z80_|reg_control_|reg_sel_pc~1_combout ; +wire \z80_|reg_control_|reg_sel_pc~0_combout ; +wire \z80_|reg_control_|reg_sel_pc~2_combout ; +wire \z80_|pla_decode_|Equal56~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~18_combout ; +wire \z80_|execute_|ctl_alu_op_low~17_combout ; +wire \z80_|execute_|ctl_alu_oe~4_combout ; +wire \z80_|execute_|ctl_reg_in_hi~4_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; +wire \z80_|execute_|ctl_inc_dec~3_combout ; +wire \z80_|execute_|fMRead~6_combout ; +wire \z80_|nM1_int~2_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_inc_cy~94_combout ; +wire \z80_|execute_|ctl_inc_cy~50_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; +wire \z80_|execute_|ctl_inc_cy~99_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; +wire \z80_|execute_|ctl_reg_out_hi~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_in_lo~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; +wire \z80_|pla_decode_|Equal1~5_combout ; +wire \z80_|execute_|ctl_alu_op_low~20_combout ; +wire \z80_|pla_decode_|Equal48~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; +wire \z80_|execute_|ctl_flags_bus~4_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; +wire \z80_|execute_|fMRead~7_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; +wire \z80_|execute_|ctl_reg_sys_we~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we~1_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; +wire \z80_|execute_|ctl_reg_sys_we~2_combout ; +wire \z80_|pla_decode_|Equal8~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~1_combout ; +wire \z80_|alu_control_|sel[1]~0_combout ; +wire \z80_|execute_|ctl_state_alu~7_combout ; +wire \z80_|execute_|ctl_state_alu~11_combout ; +wire \z80_|execute_|ctl_state_alu~9_combout ; +wire \z80_|execute_|ctl_state_alu~5_combout ; +wire \z80_|execute_|ctl_state_alu~10_combout ; +wire \z80_|execute_|ctl_state_alu~8_combout ; +wire \z80_|pla_decode_|Equal62~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~5_combout ; +wire \z80_|execute_|ctl_ir_we~11_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~7_combout ; +wire \z80_|execute_|ctl_bus_db_oe~3_combout ; +wire \z80_|execute_|ctl_flags_xy_we~19_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; +wire \z80_|execute_|ctl_alu_op_low~19_combout ; +wire \z80_|execute_|ctl_flags_bus~15_combout ; +wire \z80_|execute_|ctl_flags_bus~9_combout ; +wire \z80_|pla_decode_|Equal20~0_combout ; +wire \z80_|pla_decode_|Equal68~2_combout ; +wire \z80_|execute_|ctl_flags_bus~14_combout ; +wire \z80_|pla_decode_|Equal63~0_combout ; +wire \z80_|pla_decode_|Equal76~2_combout ; +wire \z80_|execute_|ctl_flags_bus~8_combout ; +wire \z80_|execute_|ctl_flags_bus~6_combout ; +wire \z80_|execute_|ctl_flags_bus~7_combout ; +wire \z80_|execute_|ctl_flags_bus~10_combout ; +wire \z80_|execute_|ctl_flags_xy_we~11_combout ; +wire \z80_|execute_|ctl_flags_hf2_we~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; +wire \z80_|execute_|ctl_reg_gp_sel~7_combout ; +wire \z80_|execute_|ctl_state_alu~12_combout ; +wire \z80_|pla_decode_|Equal62~3_combout ; +wire \z80_|execute_|ctl_flags_pf_we~6_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; +wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; +wire \z80_|execute_|ctl_flags_cf_we~7_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~10_combout ; +wire \z80_|execute_|ctl_flags_hf_we~5_combout ; +wire \z80_|execute_|ctl_flags_pf_we~11_combout ; +wire \z80_|execute_|ctl_flags_pf_we~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~3_combout ; +wire \z80_|pla_decode_|Equal10~1_combout ; +wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; +wire \z80_|pla_decode_|Equal69~0_combout ; +wire \z80_|execute_|ctl_flags_pf_we~7_combout ; +wire \z80_|execute_|ctl_flags_pf_we~8_combout ; +wire \z80_|execute_|ctl_flags_pf_we~9_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~13_combout ; +wire \z80_|execute_|ctl_flags_pf_we~10_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; +wire \z80_|execute_|ctl_flags_xy_we~18_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~21_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~20_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ; +wire \z80_|execute_|ctl_reg_out_lo~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; +wire \z80_|execute_|ctl_al_we~14_combout ; +wire \z80_|execute_|ctl_sw_4d~1_combout ; +wire \z80_|execute_|ctl_alu_oe~5_combout ; +wire \z80_|execute_|setM1~47_combout ; +wire \z80_|execute_|ctl_sw_4d~0_combout ; +wire \z80_|execute_|ctl_sw_4d~4_combout ; +wire \z80_|execute_|fMRead~8_combout ; +wire \z80_|execute_|fMRead~9_combout ; +wire \z80_|execute_|fMRead~10_combout ; +wire \z80_|execute_|ctl_sw_4d~2_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; +wire \z80_|pla_decode_|Equal4~0_combout ; +wire \z80_|execute_|setM1~41_combout ; +wire \z80_|pla_decode_|Equal2~1_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_sw_1d~4_combout ; +wire \z80_|execute_|ctl_sw_4d~3_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; +wire \z80_|execute_|ctl_sw_4d~5_combout ; +wire \z80_|execute_|ctl_sw_4d~6_combout ; +wire \z80_|reg_control_|reg_sel_pc~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; +wire \z80_|execute_|ctl_sw_4u~1_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; +wire \z80_|reg_control_|reg_sel_pc~3_combout ; +wire \z80_|reg_control_|reg_sel_pc~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; +wire \z80_|pla_decode_|Equal1~6_combout ; +wire \z80_|reg_control_|bank_exx~2_combout ; +wire \z80_|reg_control_|bank_exx~q ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_sw_2u~1_combout ; +wire \z80_|execute_|ctl_alu_oe~3_combout ; +wire \z80_|execute_|ctl_sw_2u~4_combout ; +wire \z80_|execute_|setM1~56_combout ; +wire \z80_|execute_|ctl_sw_2u~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; +wire \z80_|execute_|ctl_state_alu~13_combout ; +wire \z80_|execute_|ctl_flags_xy_we~12_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; wire \z80_|execute_|ctl_inc_cy~61_combout ; -wire \z80_|execute_|ctl_inc_cy~62_combout ; -wire \z80_|execute_|ctl_inc_cy~70_combout ; -wire \z80_|execute_|ctl_inc_cy~85_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[0]~3_combout ; -wire \z80_|address_latch_|Q[0]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; -wire \z80_|reg_file_|db_lo_as[1]~4_combout ; -wire \z80_|reg_file_|db_lo_as[1]~5_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; -wire \z80_|reg_file_|db_lo_as[1]~6_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[2]~9_combout ; -wire \z80_|address_latch_|Q[2]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; wire \z80_|execute_|ctl_inc_cy~86_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|execute_|ctl_inc_dec~11_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; -wire \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; -wire \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ; +wire \z80_|execute_|ctl_inc_cy~87_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~52_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~49_combout ; +wire \z80_|execute_|ctl_reg_gp_we~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; +wire \z80_|execute_|ctl_alu_oe~7_combout ; +wire \z80_|execute_|ctl_alu_oe~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_flags_oe~0_combout ; +wire \z80_|execute_|ctl_flags_oe~1_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~8_combout ; +wire \z80_|execute_|setM1~48_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; +wire \z80_|execute_|nextM~2_combout ; +wire \z80_|execute_|setM1~49_combout ; +wire \z80_|execute_|ctl_reg_in_hi~12_combout ; +wire \z80_|execute_|ctl_sw_1d~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; +wire \z80_|execute_|ctl_sw_2u~2_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; +wire \z80_|execute_|nextM~11_combout ; +wire \z80_|execute_|ctl_reg_use_sp~0_combout ; +wire \z80_|execute_|ctl_reg_use_sp~2_combout ; +wire \z80_|execute_|ctl_reg_use_sp~3_combout ; +wire \z80_|execute_|ctl_sw_1d~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~13_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; +wire \z80_|execute_|setM1~30_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~14_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~22_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; +wire \z80_|reg_control_|reg_sel_de2~2_combout ; +wire \z80_|reg_control_|reg_sel_de2~4_combout ; +wire \z80_|pla_decode_|Equal2~2_combout ; +wire \z80_|reg_control_|bank_hl_de1~0_combout ; +wire \z80_|reg_control_|bank_hl_de1~q ; +wire \z80_|reg_control_|reg_sel_hl~0_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~50_combout ; +wire \z80_|execute_|ctl_reg_gp_we~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ; +wire \z80_|execute_|rsel3~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; +wire \z80_|execute_|rsel0~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; +wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; +wire \z80_|execute_|ctl_reg_in_hi~7_combout ; +wire \z80_|execute_|ctl_reg_gp_we~6_combout ; +wire \z80_|execute_|ctl_reg_gp_we~9_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; +wire \z80_|execute_|ctl_reg_gp_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; +wire \z80_|execute_|ctl_reg_gp_we~5_combout ; +wire \z80_|execute_|ctl_reg_gp_we~7_combout ; +wire \z80_|execute_|ctl_sw_4u~2_combout ; +wire \z80_|execute_|ctl_sw_4u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_we~8_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; +wire \z80_|reg_control_|bank_hl_de2~0_combout ; +wire \z80_|reg_control_|bank_hl_de2~q ; +wire \z80_|reg_control_|reg_sel_hl2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; +wire \z80_|execute_|ctl_flags_sz_we~1_combout ; +wire \z80_|execute_|ctl_reg_in_hi~8_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ; +wire \z80_|execute_|ctl_reg_in_hi~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; +wire \z80_|execute_|ctl_reg_in_lo~8_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; +wire \z80_|execute_|ctl_sw_2d~6_combout ; +wire \z80_|execute_|ctl_sw_2d~7_combout ; +wire \z80_|execute_|ctl_sw_2d~8_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; +wire \z80_|execute_|ctl_sw_2d~4_combout ; +wire \z80_|execute_|fMRead~18_combout ; +wire \z80_|execute_|fMRead~19_combout ; +wire \z80_|execute_|fMRead~20_combout ; +wire \z80_|execute_|ctl_reg_in_hi~6_combout ; +wire \z80_|execute_|fMRead~21_combout ; +wire \z80_|execute_|ctl_sw_2d~5_combout ; +wire \z80_|execute_|ctl_sw_2d~9_combout ; +wire \z80_|execute_|ctl_sw_1d~5_combout ; +wire \z80_|execute_|ctl_sw_1d~6_combout ; +wire \z80_|execute_|ctl_sw_1d~7_combout ; +wire \z80_|execute_|ctl_alu_op_low~41_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op_low~26_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; +wire \z80_|execute_|ctl_alu_op_low~27_combout ; +wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; +wire \z80_|pla_decode_|Equal61~2_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; +wire \z80_|execute_|ctl_alu_core_hf~12_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; +wire \z80_|execute_|ctl_flags_sz_we~3_combout ; +wire \z80_|execute_|ctl_flags_alu~13_combout ; +wire \z80_|execute_|ctl_flags_alu~14_combout ; +wire \z80_|execute_|ctl_flags_alu~15_combout ; +wire \z80_|execute_|ctl_reg_use_sp~1_combout ; +wire \z80_|execute_|ctl_alu_op_low~16_combout ; +wire \z80_|execute_|ctl_flags_xy_we~17_combout ; +wire \z80_|execute_|ctl_flags_sz_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ; +wire \z80_|execute_|ctl_alu_op_low~39_combout ; +wire \z80_|execute_|ctl_flags_alu~16_combout ; +wire \z80_|execute_|ctl_flags_alu~17_combout ; +wire \z80_|execute_|ctl_alu_op_low~23_combout ; +wire \z80_|execute_|ctl_flags_alu~18_combout ; +wire \z80_|execute_|ctl_flags_alu~11_combout ; +wire \z80_|execute_|ctl_alu_core_R~0_combout ; +wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~1_combout ; +wire \z80_|execute_|ctl_flags_alu~23_combout ; +wire \z80_|execute_|ctl_flags_alu~12_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~11_combout ; +wire \z80_|execute_|ctl_alu_oe~6_combout ; +wire \z80_|execute_|setM1~17_combout ; +wire \z80_|execute_|ctl_alu_op_low~22_combout ; +wire \z80_|execute_|ctl_flags_xy_we~6_combout ; +wire \z80_|execute_|ctl_flags_xy_we~7_combout ; +wire \z80_|execute_|ctl_flags_sz_we~2_combout ; +wire \z80_|execute_|ctl_flags_alu~19_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; +wire \z80_|execute_|fMRead~26_combout ; +wire \z80_|execute_|ctl_flags_bus~11_combout ; +wire \z80_|execute_|ctl_flags_bus~12_combout ; +wire \z80_|execute_|ctl_flags_bus~13_combout ; +wire \z80_|execute_|ctl_flags_bus~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~12_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~18_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; +wire \z80_|execute_|ctl_alu_op_low~24_combout ; +wire \z80_|execute_|ctl_alu_op_low~25_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~17_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; +wire \z80_|execute_|ctl_flags_xy_we~10_combout ; +wire \z80_|execute_|ctl_flags_cf_we~2_combout ; +wire \z80_|execute_|ctl_alu_core_S~6_combout ; +wire \z80_|execute_|ctl_alu_core_S~7_combout ; +wire \z80_|execute_|ctl_alu_core_S~4_combout ; +wire \z80_|execute_|ctl_alu_core_S~5_combout ; +wire \z80_|execute_|ctl_alu_oe~15_combout ; +wire \z80_|execute_|ctl_alu_res_oe~0_combout ; +wire \z80_|execute_|ctl_alu_res_oe~1_combout ; +wire \z80_|execute_|ctl_alu_res_oe~2_combout ; +wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; +wire \z80_|alu_|db_high[3]~0_combout ; +wire \z80_|execute_|ctl_reg_out_hi~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ; +wire \z80_|execute_|ctl_sw_2u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; +wire \z80_|execute_|ctl_sw_2u~6_combout ; +wire \z80_|execute_|ctl_reg_out_lo~2_combout ; +wire \z80_|execute_|ctl_reg_out_hi~5_combout ; +wire \z80_|execute_|ctl_reg_out_hi~6_combout ; +wire \z80_|execute_|ctl_reg_out_hi~7_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~40_combout ; +wire \z80_|execute_|ctl_reg_use_sp~4_combout ; +wire \z80_|execute_|ctl_reg_use_sp~5_combout ; +wire \z80_|execute_|ctl_reg_use_sp~6_combout ; +wire \z80_|reg_control_|bank_af~0_combout ; +wire \z80_|reg_control_|bank_af~q ; +wire \z80_|reg_control_|reg_sel_af~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~41_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ; -wire \z80_|execute_|ctl_reg_in_hi~11_combout ; -wire \z80_|execute_|ctl_reg_in_hi~12_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~44_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~32_combout ; +wire \z80_|reg_control_|reg_sel_de2~3_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_control_|reg_sel_de~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~31_combout ; wire \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ; +wire \z80_|reg_control_|reg_sel_iy~2_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~43_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~34_combout ; +wire \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; +wire \z80_|execute_|ctl_sw_4u~4_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~45_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~36_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~42_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~46_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~47_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~33_combout ; +wire \z80_|reg_control_|reg_sel_af2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; +wire \z80_|execute_|ctl_reg_in_hi~10_combout ; +wire \z80_|execute_|ctl_reg_in_hi~11_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~35_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~37_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~38_combout ; +wire \z80_|execute_|ctl_sw_4u~5_combout ; +wire \z80_|execute_|ctl_sw_4u~6_combout ; wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; -wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; -wire \z80_|reg_file_|db_hi_as[1]~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; -wire \z80_|reg_file_|db_hi_as[1]~1_combout ; -wire \z80_|reg_file_|db_hi_as[0]~2_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; -wire \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; -wire \z80_|reg_file_|db_hi_as[0]~4_combout ; -wire \z80_|reg_file_|db_hi_as[0]~5_combout ; -wire \z80_|reg_file_|db_hi_as[0]~6_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[1]~3_combout ; -wire \z80_|address_latch_|Q[9]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~32_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~35_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~34_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~33_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~36_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~37_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~31_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~38_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~39_combout ; -wire \z80_|reg_file_|db_hi_as[2]~7_combout ; -wire \z80_|reg_file_|db_hi_as[2]~8_combout ; -wire \z80_|reg_file_|db_hi_as[2]~9_combout ; -wire \z80_|address_latch_|Q[10]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; -wire \z80_|reg_file_|db_hi_as[3]~10_combout ; -wire \z80_|reg_file_|db_hi_as[3]~11_combout ; -wire \z80_|reg_file_|db_hi_as[3]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~48_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; -wire \z80_|alu_|alu_op1[3]~3_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; -wire \z80_|execute_|ctl_alu_core_R~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~5_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~20_combout ; -wire \z80_|execute_|ctl_state_alu~12_combout ; -wire \z80_|execute_|ctl_alu_core_hf~18_combout ; -wire \z80_|pla_decode_|Equal61~2_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~21_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~20_combout ; -wire \z80_|execute_|ctl_flags_sz_we~4_combout ; -wire \z80_|pla_decode_|Equal71~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; -wire \z80_|execute_|ctl_alu_op_low~31_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ; -wire \z80_|pla_decode_|Equal72~2_combout ; -wire \z80_|pla_decode_|Equal73~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~0_combout ; -wire \z80_|execute_|ctl_flags_nf_we~1_combout ; -wire \z80_|execute_|ctl_flags_nf_we~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~3_combout ; -wire \z80_|execute_|ctl_flags_sz_we~5_combout ; -wire \z80_|execute_|ctl_flags_sz_we~6_combout ; -wire \z80_|execute_|ctl_flags_nf_we~4_combout ; -wire \z80_|execute_|setM1~15_combout ; -wire \z80_|execute_|setM1~16_combout ; -wire \z80_|execute_|ctl_flags_xy_we~6_combout ; -wire \z80_|execute_|ctl_flags_xy_we~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~2_combout ; -wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~1_combout ; -wire \z80_|execute_|ctl_flags_alu~7_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~8_combout ; -wire \z80_|execute_|ctl_flags_alu~8_combout ; -wire \z80_|execute_|ctl_flags_xy_we~16_combout ; -wire \z80_|execute_|ctl_flags_alu~12_combout ; -wire \z80_|execute_|ctl_flags_alu~13_combout ; -wire \z80_|execute_|ctl_flags_alu~14_combout ; -wire \z80_|execute_|ctl_flags_alu~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~19_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; -wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~18_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; -wire \z80_|alu_|alu_op2[1]~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|execute_|ctl_alu_core_S~9_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ; -wire \z80_|alu_|alu_op2[0]~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ; -wire \z80_|execute_|ctl_alu_core_S~8_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|execute_|ctl_alu_core_hf~21_combout ; -wire \z80_|execute_|ctl_alu_core_hf~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~19_combout ; -wire \z80_|execute_|ctl_alu_op_low~27_combout ; -wire \z80_|execute_|ctl_alu_op_low~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~23_combout ; -wire \z80_|execute_|ctl_alu_core_hf~37_combout ; -wire \z80_|execute_|ctl_alu_core_hf~38_combout ; -wire \z80_|execute_|ctl_alu_core_hf~24_combout ; -wire \z80_|execute_|ctl_alu_core_hf~25_combout ; -wire \z80_|execute_|ctl_alu_core_hf~26_combout ; -wire \z80_|execute_|ctl_alu_core_hf~27_combout ; -wire \z80_|execute_|ctl_alu_core_hf~28_combout ; -wire \z80_|execute_|ctl_alu_op_low~30_combout ; -wire \z80_|execute_|ctl_alu_core_hf~34_combout ; -wire \z80_|execute_|ctl_alu_core_hf~32_combout ; -wire \z80_|execute_|ctl_alu_core_hf~43_combout ; -wire \z80_|execute_|ctl_alu_core_hf~33_combout ; -wire \z80_|execute_|ctl_alu_core_hf~42_combout ; -wire \z80_|execute_|ctl_alu_core_hf~35_combout ; -wire \z80_|execute_|ctl_alu_core_hf~41_combout ; -wire \z80_|execute_|ctl_alu_core_hf~30_combout ; -wire \z80_|execute_|ctl_mWrite~10_combout ; -wire \z80_|execute_|ctl_alu_core_hf~31_combout ; -wire \z80_|execute_|ctl_alu_core_hf~44_combout ; -wire \z80_|execute_|ctl_alu_core_hf~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~36_combout ; -wire \z80_|execute_|ctl_alu_core_hf~39_combout ; -wire \z80_|execute_|ctl_alu_core_hf~40_combout ; -wire \z80_|execute_|ctl_flags_hf_we~2_combout ; -wire \z80_|execute_|ctl_alu_core_R~2_combout ; -wire \z80_|execute_|ctl_alu_core_R~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ; -wire \z80_|alu_|alu_op2[3]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; -wire \z80_|execute_|ctl_flags_hf_we~3_combout ; -wire \z80_|execute_|ctl_flags_hf_we~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; -wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~13_combout ; -wire \z80_|alu_flags_|flags_hf~combout ; -wire \z80_|alu_control_|alu_core_cf_in~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; -wire \z80_|alu_|db_high[0]~23_combout ; -wire \z80_|address_latch_|Q[12]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[4]~16_combout ; -wire \z80_|reg_file_|db_hi_as[4]~17_combout ; -wire \z80_|reg_file_|db_hi_as[4]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~62_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~63_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~61_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~64_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~58_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~65_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~66_combout ; -wire \z80_|alu_|db[4]~16_combout ; -wire \z80_|alu_|db[7]~26_combout ; -wire \z80_|alu_|db[4]~17_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; -wire \z80_|alu_|db_high[0]~24_combout ; -wire \z80_|alu_|db_high[0]~21_combout ; -wire \z80_|alu_|db_high[0]~22_combout ; -wire \z80_|alu_|db_high[0]~25_combout ; -wire \z80_|alu_|db_high[0]~26_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; -wire \z80_|alu_|alu_op1[0]~1_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; -wire \z80_|alu_|alu_op1[1]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; -wire \z80_|alu_|alu_op1[2]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~5_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~69_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~70_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~72_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~71_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~73_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~67_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~68_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~74_combout ; -wire \z80_|reg_file_|db_hi_as[7]~19_combout ; -wire \z80_|reg_file_|db_hi_as[7]~20_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~54_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~53_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~51_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~52_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~55_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~49_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~50_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~56_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~57_combout ; -wire \z80_|reg_file_|db_hi_as[5]~13_combout ; -wire \z80_|reg_file_|db_hi_as[5]~14_combout ; -wire \z80_|reg_file_|db_hi_as[5]~15_combout ; -wire \z80_|address_latch_|Q[13]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~76_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~80_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~79_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~78_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~81_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~82_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~77_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~83_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~84_combout ; -wire \z80_|reg_file_|db_hi_as[6]~22_combout ; -wire \z80_|reg_file_|db_hi_as[6]~23_combout ; -wire \z80_|reg_file_|db_hi_as[6]~24_combout ; -wire \z80_|address_latch_|Q[14]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|reg_file_|db_hi_as[7]~21_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~75_combout ; -wire \z80_|alu_|db[7]~20_combout ; -wire \z80_|alu_|db[7]~21_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; -wire \z80_|execute_|ctl_flags_cf_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf_we~5_combout ; -wire \z80_|execute_|ctl_flags_cf_we~3_combout ; -wire \z80_|execute_|ctl_flags_cf_we~6_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~2_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; -wire \z80_|alu_|db_high[3]~5_combout ; -wire \z80_|alu_|db_high[3]~6_combout ; -wire \z80_|alu_|db_high[3]~4_combout ; -wire \z80_|alu_|db_high[3]~27_combout ; -wire \z80_|alu_|db_high[3]~7_combout ; -wire \z80_|alu_|db_high[3]~8_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ; -wire \z80_|alu_|db_low[3]~9_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; -wire \z80_|alu_|db_low[3]~10_combout ; -wire \z80_|alu_|db_low[3]~7_combout ; -wire \z80_|alu_|db_low[3]~8_combout ; -wire \z80_|alu_|db_low[3]~11_combout ; -wire \z80_|alu_|db_low[3]~25_combout ; -wire \z80_|alu_|db[3]~10_combout ; -wire \z80_|alu_|db[3]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~39_combout ; +wire \z80_|alu_|db[3]~13_combout ; +wire \z80_|execute_|ctl_sw_2d~12_combout ; +wire \z80_|execute_|ctl_sw_2d~10_combout ; +wire \z80_|execute_|ctl_sw_2d~14_combout ; +wire \z80_|execute_|ctl_sw_2d~11_combout ; +wire \z80_|execute_|ctl_sw_2d~13_combout ; +wire \z80_|execute_|ctl_bus_db_we~5_combout ; +wire \z80_|execute_|ctl_alu_oe~9_combout ; +wire \z80_|execute_|ctl_alu_oe~10_combout ; wire \z80_|execute_|ctl_sw_2u~7_combout ; -wire \z80_|execute_|setM1~49_combout ; -wire \z80_|execute_|ctl_flags_oe~2_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|execute_|ctl_flags_sz_we~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ; wire \z80_|execute_|ctl_flags_xy_we~13_combout ; wire \z80_|execute_|ctl_flags_xy_we~14_combout ; wire \z80_|execute_|ctl_flags_xy_we~15_combout ; +wire \z80_|execute_|ctl_flags_sz_we~5_combout ; +wire \z80_|execute_|ctl_flags_sz_we~6_combout ; +wire \z80_|execute_|ctl_flags_sz_we~7_combout ; +wire \z80_|execute_|ctl_flags_xy_we~16_combout ; wire \z80_|alu_flags_|flags_xf~q ; -wire \z80_|alu_control_|db[3]~33_combout ; +wire \z80_|execute_|setM1~50_combout ; +wire \z80_|execute_|ctl_flags_oe~2_combout ; +wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; +wire \z80_|alu_control_|db[3]~34_combout ; +wire \z80_|sw1_|db_down[3]~3_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~42_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~91_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; +wire \z80_|reg_file_|db_lo_as[3]~10_combout ; +wire \z80_|reg_file_|db_lo_as[3]~11_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; +wire \z80_|execute_|ctl_inc_cy~88_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; +wire \z80_|execute_|ctl_inc_dec~6_combout ; +wire \z80_|reg_file_|db_lo_as[0]~2_combout ; +wire \z80_|execute_|pc_inc_hold~25_combout ; +wire \z80_|execute_|ctl_inc_cy~67_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~64_combout ; +wire \z80_|execute_|ctl_inc_cy~65_combout ; +wire \z80_|execute_|ctl_inc_cy~63_combout ; +wire \z80_|execute_|ctl_inc_cy~66_combout ; +wire \z80_|execute_|ctl_inc_cy~68_combout ; +wire \z80_|execute_|ctl_inc_cy~58_combout ; +wire \z80_|execute_|ctl_inc_cy~59_combout ; +wire \z80_|execute_|ctl_inc_cy~60_combout ; +wire \z80_|execute_|ctl_inc_cy~57_combout ; +wire \z80_|execute_|ctl_inc_cy~62_combout ; +wire \z80_|execute_|pc_inc_hold~18_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; +wire \z80_|execute_|pc_inc_hold~17_combout ; +wire \z80_|execute_|pc_inc_hold~19_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; +wire \z80_|execute_|pc_inc_hold~20_combout ; +wire \z80_|execute_|pc_inc_hold~36_combout ; +wire \z80_|execute_|pc_inc_hold~15_combout ; +wire \z80_|execute_|pc_inc_hold~16_combout ; +wire \z80_|execute_|pc_inc_hold~21_combout ; +wire \z80_|execute_|ctl_inc_cy~69_combout ; +wire \z80_|execute_|ctl_inc_cy~52_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; +wire \z80_|execute_|pc_inc_hold~34_combout ; +wire \z80_|execute_|pc_inc_hold~22_combout ; +wire \z80_|execute_|pc_inc_hold~23_combout ; +wire \z80_|execute_|pc_inc_hold~35_combout ; +wire \z80_|execute_|pc_inc_hold~24_combout ; +wire \z80_|execute_|ctl_inc_cy~53_combout ; +wire \z80_|execute_|ctl_inc_cy~54_combout ; +wire \z80_|execute_|ctl_inc_cy~74_combout ; +wire \z80_|execute_|ctl_inc_cy~75_combout ; +wire \z80_|execute_|ctl_inc_cy~73_combout ; +wire \z80_|execute_|ctl_inc_cy~76_combout ; +wire \z80_|execute_|ctl_inc_cy~95_combout ; +wire \z80_|execute_|ctl_inc_cy~72_combout ; +wire \z80_|execute_|pc_inc_hold~27_combout ; +wire \z80_|execute_|ctl_inc_cy~77_combout ; +wire \z80_|execute_|ctl_inc_cy~78_combout ; +wire \z80_|execute_|ctl_inc_cy~79_combout ; +wire \z80_|execute_|ctl_inc_cy~70_combout ; +wire \z80_|execute_|ctl_inc_cy~71_combout ; +wire \z80_|execute_|ctl_inc_cy~80_combout ; +wire \z80_|execute_|ctl_inc_cy~55_combout ; +wire \z80_|execute_|pc_inc_hold~26_combout ; +wire \z80_|execute_|ctl_inc_cy~56_combout ; +wire \z80_|execute_|ctl_inc_cy~81_combout ; +wire \z80_|execute_|ctl_inc_cy~85_combout ; +wire \z80_|execute_|ctl_inc_cy~89_combout ; +wire \z80_|execute_|ctl_inc_cy~90_combout ; +wire \z80_|execute_|ctl_inc_cy~91_combout ; +wire \z80_|execute_|ctl_inc_cy~83_combout ; +wire \z80_|execute_|ctl_inc_cy~84_combout ; +wire \z80_|execute_|ctl_inc_cy~100_combout ; +wire \z80_|execute_|ctl_inc_cy~92_combout ; +wire \z80_|execute_|pc_inc_hold~28_combout ; +wire \z80_|execute_|ctl_inc_cy~82_combout ; +wire \z80_|execute_|pc_inc_hold~29_combout ; +wire \z80_|execute_|pc_inc_hold~30_combout ; +wire \z80_|execute_|pc_inc_hold~31_combout ; +wire \z80_|execute_|pc_inc_hold~32_combout ; +wire \z80_|execute_|ctl_inc_cy~93_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; +wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; +wire \z80_|alu_control_|db[0]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; +wire \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ; +wire \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; +wire \z80_|execute_|ctl_inc_dec~8_combout ; +wire \z80_|execute_|ctl_inc_dec~9_combout ; +wire \z80_|execute_|ctl_inc_dec~10_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|execute_|ctl_inc_dec~7_combout ; +wire \z80_|execute_|ctl_inc_dec~11_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; +wire \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; +wire \z80_|alu_|db_low[2]~9_combout ; +wire \z80_|alu_|db_low[2]~10_combout ; +wire \z80_|alu_|db_high[3]~1_combout ; +wire \z80_|execute_|ctl_flags_pf_we~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ; +wire \z80_|execute_|ctl_alu_op_low~38_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ; +wire \z80_|execute_|ctl_alu_core_S~8_combout ; +wire \z80_|execute_|ctl_alu_core_R~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~3_combout ; +wire \z80_|execute_|ctl_alu_core_R~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; +wire \z80_|execute_|ctl_alu_core_S~11_combout ; +wire \z80_|execute_|ctl_alu_core_S~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~combout ; +wire \z80_|pla_decode_|Equal73~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~5_combout ; +wire \z80_|execute_|ctl_alu_core_R~combout ; +wire \z80_|execute_|ctl_alu_op_low~28_combout ; +wire \z80_|execute_|ctl_alu_op_low~29_combout ; +wire \z80_|execute_|ctl_alu_op_low~30_combout ; +wire \z80_|execute_|ctl_alu_op_low~31_combout ; +wire \z80_|execute_|ctl_alu_op_low~32_combout ; +wire \z80_|execute_|ctl_alu_op_low~40_combout ; +wire \z80_|execute_|ctl_alu_op_low~33_combout ; +wire \z80_|execute_|ctl_alu_op_low~combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~59_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~58_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~61_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~62_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~63_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~60_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~64_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~65_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; +wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; +wire \z80_|reg_file_|db_hi_as[7]~16_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; +wire \z80_|reg_file_|db_hi_as[7]~17_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; +wire \z80_|reg_file_|db_hi_as[1]~0_combout ; +wire \z80_|reg_file_|db_hi_as[1]~1_combout ; +wire \z80_|execute_|ctl_al_we~6_combout ; +wire \z80_|execute_|ctl_al_we~9_combout ; +wire \z80_|execute_|ctl_al_we~10_combout ; +wire \z80_|execute_|ctl_al_we~7_combout ; +wire \z80_|execute_|ctl_al_we~8_combout ; +wire \z80_|execute_|ctl_al_we~11_combout ; +wire \z80_|execute_|ctl_al_we~12_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~82_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~81_combout ; +wire \z80_|alu_control_|db[6]~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|execute_|ctl_flags_sz_we~8_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; +wire \z80_|alu_control_|db[7]~18_combout ; +wire \z80_|alu_control_|db[7]~19_combout ; +wire \z80_|alu_control_|db[7]~20_combout ; +wire \z80_|alu_control_|db[7]~37_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; +wire \z80_|reg_file_|db_lo_as[7]~22_combout ; +wire \z80_|reg_file_|db_lo_as[7]~23_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[7]~24_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[1]~3_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~44_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~45_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~42_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~43_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~46_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~40_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~41_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~47_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~48_combout ; +wire \z80_|reg_file_|db_hi_as[2]~10_combout ; +wire \z80_|reg_file_|db_hi_as[2]~11_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[2]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~50_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~49_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~51_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~52_combout ; +wire \z80_|alu_|db[4]~8_combout ; +wire \z80_|alu_|db[4]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~53_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~54_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~55_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~56_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~57_combout ; +wire \z80_|reg_file_|db_hi_as[4]~13_combout ; +wire \z80_|reg_file_|db_hi_as[4]~14_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[4]~15_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~76_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~77_combout ; +wire \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~79_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; +wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; +wire \z80_|alu_|db_low[1]~18_combout ; +wire \z80_|alu_|db_low[1]~19_combout ; +wire \z80_|alu_|db_low[1]~16_combout ; +wire \z80_|alu_|db_low[1]~15_combout ; +wire \z80_|alu_|db_low[1]~17_combout ; +wire \z80_|alu_|db_low[1]~20_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; +wire \z80_|alu_|alu_op2[1]~2_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; +wire \z80_|alu_|db_high[2]~10_combout ; +wire \z80_|alu_|db_high[2]~8_combout ; +wire \z80_|alu_|db_high[2]~9_combout ; +wire \z80_|alu_|db_high[2]~11_combout ; +wire \z80_|alu_|db_high[2]~12_combout ; +wire \z80_|alu_|db_high[2]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~68_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~67_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~72_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~70_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~69_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~71_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~73_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~74_combout ; +wire \z80_|reg_file_|db_hi_as[6]~19_combout ; +wire \z80_|reg_file_|db_hi_as[6]~20_combout ; +wire \z80_|reg_file_|db_hi_as[6]~21_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~75_combout ; +wire \z80_|alu_|db[6]~21_combout ; +wire \z80_|alu_|db[6]~22_combout ; +wire \z80_|alu_|db_high[1]~16_combout ; +wire \z80_|alu_|db_high[1]~17_combout ; +wire \z80_|alu_|db_high[1]~14_combout ; +wire \z80_|alu_|db_high[1]~15_combout ; +wire \z80_|alu_|db_high[1]~18_combout ; +wire \z80_|alu_|db_high[1]~19_combout ; +wire \z80_|alu_|db[5]~23_combout ; +wire \z80_|alu_|db[5]~24_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~80_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~81_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~78_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~82_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~83_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~84_combout ; +wire \z80_|reg_file_|db_hi_as[5]~22_combout ; +wire \z80_|reg_file_|db_hi_as[5]~23_combout ; +wire \z80_|reg_file_|db_hi_as[5]~24_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|reg_file_|db_hi_as[7]~18_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~66_combout ; +wire \z80_|alu_|db[7]~19_combout ; +wire \z80_|alu_|db[7]~20_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ; +wire \z80_|alu_|alu_op1[3]~0_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ; +wire \z80_|alu_|alu_op2[2]~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; +wire \z80_|execute_|ctl_flags_cf_we~3_combout ; +wire \z80_|execute_|ctl_flags_hf_we~2_combout ; +wire \z80_|execute_|ctl_flags_cf_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf_we~5_combout ; +wire \z80_|execute_|ctl_flags_cf_we~6_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~6_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~5_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; +wire \z80_|alu_|db_low[0]~21_combout ; +wire \z80_|alu_|db_low[0]~22_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ; +wire \z80_|alu_|db_low[0]~24_combout ; +wire \z80_|alu_|db_low[0]~23_combout ; +wire \z80_|alu_|db_low[0]~25_combout ; +wire \z80_|alu_|db_low[0]~27_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ; +wire \z80_|alu_|alu_op2[0]~3_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|execute_|ctl_alu_op_low~34_combout ; +wire \z80_|execute_|ctl_alu_op_low~36_combout ; +wire \z80_|execute_|ctl_alu_op_low~35_combout ; +wire \z80_|execute_|ctl_alu_core_hf~13_combout ; +wire \z80_|execute_|ctl_alu_core_hf~14_combout ; +wire \z80_|execute_|ctl_alu_core_hf~15_combout ; +wire \z80_|execute_|ctl_alu_core_hf~16_combout ; +wire \z80_|execute_|ctl_alu_core_hf~17_combout ; +wire \z80_|execute_|ctl_alu_core_hf~37_combout ; +wire \z80_|execute_|ctl_alu_core_hf~38_combout ; +wire \z80_|execute_|ctl_alu_core_hf~36_combout ; +wire \z80_|execute_|ctl_alu_core_hf~23_combout ; +wire \z80_|execute_|ctl_alu_core_hf~34_combout ; +wire \z80_|execute_|ctl_alu_core_hf~29_combout ; +wire \z80_|execute_|ctl_alu_core_hf~26_combout ; +wire \z80_|execute_|ctl_alu_core_hf~35_combout ; +wire \z80_|execute_|ctl_alu_core_hf~27_combout ; +wire \z80_|execute_|ctl_alu_core_hf~28_combout ; +wire \z80_|execute_|ctl_alu_core_hf~30_combout ; +wire \z80_|execute_|ctl_alu_op_low~37_combout ; +wire \z80_|execute_|ctl_alu_core_hf~24_combout ; +wire \z80_|execute_|ctl_alu_core_hf~25_combout ; +wire \z80_|execute_|ctl_alu_core_hf~31_combout ; +wire \z80_|execute_|ctl_alu_core_hf~20_combout ; +wire \z80_|execute_|ctl_alu_core_hf~21_combout ; +wire \z80_|execute_|ctl_alu_core_hf~18_combout ; +wire \z80_|execute_|ctl_alu_core_hf~19_combout ; +wire \z80_|execute_|ctl_alu_core_hf~22_combout ; +wire \z80_|execute_|ctl_alu_core_hf~32_combout ; +wire \z80_|execute_|ctl_alu_core_hf~33_combout ; +wire \z80_|alu_control_|alu_core_cf_in~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; +wire \z80_|alu_|db_high[0]~21_combout ; +wire \z80_|alu_|db_high[0]~22_combout ; +wire \z80_|alu_|db_high[0]~23_combout ; +wire \z80_|alu_|db_high[0]~20_combout ; +wire \z80_|alu_|db_high[0]~24_combout ; +wire \z80_|alu_|db_high[0]~25_combout ; +wire \z80_|alu_|alu_op1[0]~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; +wire \z80_|alu_|db_low[2]~11_combout ; +wire \z80_|alu_|db_low[2]~12_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; +wire \z80_|alu_|db_low[2]~13_combout ; +wire \z80_|alu_|db_low[2]~14_combout ; +wire \z80_|alu_|db[2]~11_combout ; +wire \z80_|alu_|db[2]~12_combout ; +wire \z80_|alu_control_|db[2]~28_combout ; +wire \z80_|alu_flags_|flags_hf2~0_combout ; +wire \z80_|alu_flags_|flags_hf2~q ; +wire \z80_|alu_control_|out[6]~0_combout ; +wire \z80_|execute_|ctl_66_oe~combout ; +wire \z80_|alu_control_|db[2]~24_combout ; wire \z80_|execute_|ctl_reg_out_lo~3_combout ; wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; wire \z80_|execute_|ctl_reg_out_lo~4_combout ; wire \z80_|execute_|ctl_reg_out_lo~5_combout ; -wire \z80_|execute_|ctl_reg_out_lo~8_combout ; -wire \z80_|sw1_|db_down[3]~1_combout ; -wire \z80_|alu_control_|db[3]~34_combout ; -wire \z80_|alu_control_|db[3]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~52_combout ; -wire \z80_|reg_file_|db_lo_as[3]~10_combout ; -wire \z80_|reg_file_|db_lo_as[3]~11_combout ; -wire \z80_|reg_file_|db_lo_as[3]~12_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ; +wire \z80_|reg_file_|db_lo_ds[2]~1_combout ; +wire \z80_|alu_control_|db[2]~29_combout ; +wire \z80_|alu_control_|db[2]~30_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; +wire \z80_|reg_file_|db_lo_as[2]~7_combout ; +wire \z80_|reg_file_|db_lo_as[2]~8_combout ; +wire \z80_|reg_file_|db_lo_as[2]~9_combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~62_combout ; -wire \z80_|reg_file_|db_lo_as[4]~13_combout ; -wire \z80_|reg_file_|db_lo_as[4]~14_combout ; -wire \z80_|reg_file_|db_lo_as[4]~15_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; -wire \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~62_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~72_combout ; wire \z80_|reg_file_|db_lo_as[5]~16_combout ; wire \z80_|reg_file_|db_lo_as[5]~17_combout ; wire \z80_|reg_file_|db_lo_as[5]~18_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ; wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~72_combout ; +wire \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ; wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; wire \z80_|reg_file_|db_lo_as[6]~19_combout ; wire \z80_|reg_file_|db_lo_as[6]~20_combout ; wire \z80_|reg_file_|db_lo_as[6]~21_combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[7]~24_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~92_combout ; -wire \z80_|reg_file_|db_lo_ds[7]~0_combout ; -wire \z80_|interrupts_|im2~q ; -wire \z80_|execute_|ctl_mRead~12_combout ; -wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; -wire \z80_|alu_control_|db[7]~17_combout ; -wire \z80_|alu_control_|db[7]~16_combout ; -wire \z80_|alu_control_|db[7]~18_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|execute_|ctl_flags_sz_we~8_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; -wire \z80_|pla_decode_|Equal62~3_combout ; -wire \z80_|execute_|ctl_flags_pf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~6_combout ; -wire \z80_|execute_|ctl_flags_pf_we~7_combout ; -wire \z80_|execute_|ctl_flags_pf_we~8_combout ; -wire \z80_|execute_|ctl_flags_pf_we~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[0]~4_combout ; +wire \z80_|reg_file_|db_hi_as[0]~5_combout ; +wire \z80_|reg_file_|db_hi_as[0]~6_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; +wire \z80_|alu_|db[0]~17_combout ; +wire \z80_|alu_|db[0]~18_combout ; +wire \z80_|sw2_|db_up[0]~0_combout ; +wire \z80_|alu_control_|db[0]~11_combout ; +wire \z80_|alu_control_|db[0]~14_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; +wire \z80_|reg_file_|db_lo_as[0]~0_combout ; +wire \z80_|reg_file_|db_lo_as[0]~1_combout ; +wire \z80_|reg_file_|db_lo_as[0]~3_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; +wire \z80_|reg_file_|db_lo_as[1]~4_combout ; +wire \z80_|reg_file_|db_lo_as[1]~5_combout ; +wire \z80_|reg_file_|db_lo_as[1]~6_combout ; +wire \z80_|address_latch_|Q[1]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; +wire \z80_|reg_file_|db_lo_as[3]~12_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; +wire \z80_|alu_control_|db[3]~35_combout ; +wire \z80_|alu_control_|db[3]~36_combout ; +wire \z80_|alu_|db[3]~14_combout ; +wire \z80_|alu_|db_low[3]~4_combout ; +wire \z80_|alu_|db_low[3]~5_combout ; +wire \z80_|alu_|db_low[3]~6_combout ; +wire \z80_|alu_|db_low[3]~7_combout ; +wire \z80_|alu_|db_low[3]~8_combout ; +wire \z80_|alu_|db_low[3]~26_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ; +wire \z80_|alu_|alu_op2[3]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ; +wire \z80_|alu_|db_high[3]~4_combout ; +wire \z80_|alu_|db_high[3]~2_combout ; +wire \z80_|alu_|db_high[3]~3_combout ; +wire \z80_|alu_|db_high[3]~5_combout ; +wire \z80_|alu_|db_high[3]~6_combout ; +wire \z80_|alu_|db_high[3]~7_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; +wire \z80_|execute_|ctl_flags_nf_we~0_combout ; +wire \z80_|execute_|ctl_flags_nf_we~1_combout ; +wire \z80_|execute_|ctl_flags_nf_we~2_combout ; +wire \z80_|execute_|ctl_flags_nf_we~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; +wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; +wire \z80_|execute_|ctl_flags_cf_set~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; +wire \z80_|alu_control_|out[6]~1_combout ; +wire \z80_|alu_control_|out[6]~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; +wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; +wire \z80_|execute_|ctl_alu_op_low~21_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; +wire \z80_|pla_decode_|Equal64~0_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; +wire \z80_|alu_flags_|flags_cf~combout ; +wire \z80_|execute_|ctl_flags_hf_we~3_combout ; +wire \z80_|execute_|ctl_flags_hf_we~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; +wire \z80_|execute_|ctl_flags_hf_cpl~9_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; +wire \z80_|alu_flags_|flags_hf~combout ; +wire \z80_|alu_control_|db[4]~31_combout ; +wire \z80_|alu_control_|db[4]~32_combout ; +wire \z80_|alu_control_|db[4]~33_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~52_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; +wire \z80_|reg_file_|db_lo_as[4]~13_combout ; +wire \z80_|reg_file_|db_lo_as[4]~14_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[4]~15_combout ; wire \z80_|decode_state_|DFFE_instNonRep~2_combout ; wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; wire \z80_|decode_state_|DFFE_instNonRep~4_combout ; wire \z80_|decode_state_|DFFE_instNonRep~5_combout ; wire \z80_|decode_state_|DFFE_instNonRep~q ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; +wire \z80_|pla_decode_|Equal79~0_combout ; +wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|interrupts_|DFFE_instIFF2~q ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; +wire \z80_|execute_|ctl_pf_sel[1]~12_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~11_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; wire \z80_|alu_|alu_parity_out~0_combout ; wire \z80_|alu_|alu_parity_out~combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~q ; -wire \z80_|alu_control_|sel[1]~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; wire \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ; wire \z80_|alu_control_|flags_cond_true~0_combout ; wire \z80_|alu_control_|flags_cond_true~q ; -wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; -wire \z80_|reg_file_|db_lo_ds[1]~1_combout ; -wire \z80_|alu_control_|db[1]~25_combout ; -wire \z80_|alu_control_|db[1]~24_combout ; -wire \z80_|alu_control_|db[1]~26_combout ; -wire \z80_|alu_|db[1]~12_combout ; -wire \z80_|alu_|db[1]~13_combout ; -wire \z80_|alu_|db_low[0]~21_combout ; -wire \z80_|alu_|db_low[0]~22_combout ; -wire \z80_|alu_|db_low[0]~18_combout ; -wire \z80_|alu_|db_low[0]~19_combout ; -wire \z80_|alu_|db_low[0]~20_combout ; -wire \z80_|alu_|db_low[0]~23_combout ; -wire \z80_|alu_|db[0]~18_combout ; -wire \z80_|alu_|db[0]~19_combout ; -wire \z80_|alu_|db_low[1]~15_combout ; -wire \z80_|alu_|db_low[1]~16_combout ; -wire \z80_|alu_|db_low[1]~12_combout ; -wire \z80_|alu_|db_low[1]~13_combout ; -wire \z80_|alu_|db_low[1]~14_combout ; -wire \z80_|alu_|db_low[1]~17_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ; -wire \z80_|alu_control_|out[6]~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; -wire \z80_|alu_flags_|flags_hf2~0_combout ; -wire \z80_|alu_flags_|flags_hf2~q ; -wire \z80_|alu_control_|db[2]~23_combout ; -wire \z80_|reg_file_|db_lo_ds[2]~2_combout ; -wire \z80_|alu_control_|db[2]~28_combout ; -wire \z80_|alu_control_|db[2]~27_combout ; -wire \z80_|alu_control_|db[2]~29_combout ; -wire \z80_|alu_|db[2]~14_combout ; -wire \z80_|alu_|db[2]~15_combout ; -wire \z80_|alu_|db_low[2]~2_combout ; -wire \z80_|alu_|db_low[2]~3_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ; -wire \z80_|alu_|db_low[2]~5_combout ; -wire \z80_|alu_|db_low[2]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ; -wire \z80_|alu_|alu_op2[2]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; -wire \z80_|alu_|db_high[2]~9_combout ; -wire \z80_|alu_|db_high[2]~11_combout ; -wire \z80_|alu_|db_high[2]~12_combout ; -wire \z80_|alu_|db_high[2]~10_combout ; -wire \z80_|alu_|db_high[2]~13_combout ; -wire \z80_|alu_|db_high[2]~14_combout ; -wire \z80_|alu_|db[6]~22_combout ; -wire \z80_|alu_|db[6]~23_combout ; -wire \z80_|alu_control_|out[6]~1_combout ; -wire \z80_|alu_control_|out[6]~2_combout ; -wire \z80_|alu_control_|db[6]~19_combout ; -wire \z80_|alu_control_|db[6]~20_combout ; -wire \z80_|alu_control_|db[6]~21_combout ; -wire \z80_|alu_control_|db[6]~22_combout ; -wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; -wire \z80_|interrupts_|im1~q ; -wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; -wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; -wire \z80_|bus_control_|db[0]~4_combout ; -wire \z80_|bus_control_|db[6]~8_combout ; -wire \z80_|execute_|ctl_mRead~37_combout ; -wire \z80_|execute_|ctl_mRead~28_combout ; -wire \z80_|execute_|ctl_mRead~29_combout ; -wire \z80_|execute_|ctl_mRead~30_combout ; -wire \z80_|execute_|setM1~37_combout ; -wire \z80_|execute_|setM1~55_combout ; -wire \z80_|execute_|setM1~38_combout ; -wire \z80_|execute_|ctl_mRead~34_combout ; -wire \z80_|execute_|nextM~3_combout ; -wire \z80_|execute_|ctl_mRead~31_combout ; -wire \z80_|execute_|ctl_mRead~32_combout ; -wire \z80_|execute_|ctl_mRead~33_combout ; -wire \z80_|execute_|ctl_mRead~35_combout ; -wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; -wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; -wire \z80_|memory_ifc_|wait_mrd~q ; -wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; -wire \z80_|memory_ifc_|nRD_out~1_combout ; -wire \z80_|execute_|nextM~4_combout ; -wire \z80_|execute_|ctl_iorw~12_combout ; -wire \z80_|execute_|ctl_iorw~8_combout ; -wire \z80_|execute_|ctl_iorw~9_combout ; -wire \z80_|memory_ifc_|DFFE_iorq_ff1~q ; -wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ; -wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ; -wire \z80_|memory_ifc_|wait_iorq~q ; -wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; -wire \z80_|memory_ifc_|iorq~0_combout ; -wire \z80_|execute_|fIORead~1_combout ; -wire \z80_|execute_|fIORead~2_combout ; -wire \z80_|execute_|fIORead~0_combout ; -wire \z80_|execute_|fIORead~3_combout ; -wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; -wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; -wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; -wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; -wire \z80_|memory_ifc_|nRD_out~0_combout ; -wire \z80_|memory_ifc_|nRD_out~2_combout ; -wire \Equal2~1_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~0_combout ; -wire \z80_|execute_|fMWrite~5_combout ; -wire \z80_|execute_|fMWrite~6_combout ; -wire \z80_|execute_|fMWrite~2_combout ; -wire \z80_|execute_|fMWrite~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~1_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; -wire \z80_|execute_|fMWrite~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; -wire \z80_|execute_|fMWrite~9_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; -wire \z80_|execute_|fMWrite~8_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; -wire \z80_|execute_|fMWrite~10_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; -wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; -wire \z80_|clk_delay_|DFF_inst5~q ; -wire \z80_|memory_ifc_|wait_iorqinta~feeder_combout ; -wire \z80_|memory_ifc_|wait_iorqinta~q ; -wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; -wire \z80_|memory_ifc_|nIORQ_out~0_combout ; -wire \Equal2~0_combout ; -wire \ExtRamWE~0_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; +wire \z80_|reg_file_|db_hi_as[0]~2_combout ; +wire \z80_|reg_file_|db_hi_as[3]~7_combout ; +wire \z80_|reg_file_|db_hi_as[3]~8_combout ; +wire \z80_|reg_file_|db_hi_as[3]~9_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; wire \z80_|execute_|ctl_apin_mux2~0_combout ; wire \z80_|pin_control_|bus_ab_pin_we~2_combout ; wire \z80_|pin_control_|bus_ab_pin_we~3_combout ; -wire \z80_|address_pins_|abus[13]~20_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; -wire \z80_|address_pins_|abus[14]~23_combout ; +wire \z80_|address_pins_|abus[11]~19_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; +wire \z80_|address_pins_|abus[10]~20_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~19_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~48_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~51_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~q ; +wire \D[2]~43_combout ; +wire \ula_|zx_keyboard_|WideOr17~0_combout ; +wire \ula_|zx_keyboard_|shifted~2_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~11_combout ; +wire \ula_|zx_keyboard_|shifted~0_combout ; +wire \ula_|zx_keyboard_|shifted~3_combout ; +wire \ula_|zx_keyboard_|shifted~q ; +wire \ula_|zx_keyboard_|keys[5][0]~62_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~32_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~63_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~64_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~65_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~q ; wire \z80_|address_pins_|DFFE_apin_latch[15]~15_combout ; -wire \z80_|address_pins_|abus[15]~22_combout ; -wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; +wire \z80_|address_pins_|abus[15]~21_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; +wire \z80_|address_pins_|abus[14]~22_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~57_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~58_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~59_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~28_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~60_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~56_combout ; +wire \ula_|zx_keyboard_|Selector13~0_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~q ; +wire \D[2]~44_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; +wire \z80_|address_pins_|abus[12]~24_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~29_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~54_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~55_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~q ; +wire \ula_|zx_keyboard_|key_row~1_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~127_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~66_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~128_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~67_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~q ; +wire \D[2]~45_combout ; wire \z80_|address_pins_|abus[0]~16_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~43_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~44_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~45_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~46_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~q ; +wire \ula_|zx_keyboard_|keys[0][2]~47_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~49_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~q ; +wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; +wire \z80_|address_pins_|abus[9]~17_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; +wire \z80_|address_pins_|abus[8]~18_combout ; +wire \D[2]~42_combout ; +wire \D[2]~46_combout ; +wire \z80_|memory_ifc_|wait_iorqinta~q ; +wire \z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ; +wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; +wire \z80_|control_pins_|pin_nIORQ~1_combout ; +wire \Equal2~0_combout ; +wire \z80_|address_pins_|abus[13]~23_combout ; +wire \ExtRamWE~0_combout ; +wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; wire \z80_|address_pins_|DFFE_apin_latch[1]~1_combout ; wire \z80_|address_pins_|abus[1]~25_combout ; wire \z80_|address_pins_|DFFE_apin_latch[2]~2_combout ; @@ -1807,30 +1993,20 @@ wire \z80_|address_pins_|DFFE_apin_latch[6]~6_combout ; wire \z80_|address_pins_|abus[6]~30_combout ; wire \z80_|address_pins_|DFFE_apin_latch[7]~7_combout ; wire \z80_|address_pins_|abus[7]~31_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; -wire \z80_|address_pins_|abus[8]~18_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; -wire \z80_|address_pins_|abus[9]~17_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; -wire \z80_|address_pins_|abus[10]~24_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; -wire \z80_|address_pins_|abus[11]~19_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; -wire \z80_|address_pins_|abus[12]~21_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; -wire \D[6]~90_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; -wire \D[6]~91_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; +wire \D[2]~50_combout ; +wire \D[2]~51_combout ; wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ; wire \CLOCK_50~inputclkctrl_outclk ; wire \~GND~combout ; -wire \ula_|video_|vram_address[0]~feeder_combout ; wire \ula_|video_|vram_address~0_combout ; +wire \ula_|video_|vram_address[1]~feeder_combout ; wire \ula_|video_|vram_address[2]~4_combout ; wire \ula_|video_|Add3~0_combout ; wire \ula_|video_|Add3~1_combout ; @@ -1842,638 +2018,521 @@ wire \ula_|video_|Add4~7 ; wire \ula_|video_|Add4~8_combout ; wire \ula_|video_|Add4~9 ; wire \ula_|video_|Add4~10_combout ; +wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Add4~11 ; wire \ula_|video_|Add4~12_combout ; -wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Selector6~0_combout ; -wire \ula_|video_|vram_address[9]~1_combout ; +wire \ula_|video_|vram_address[8]~1_combout ; wire \ula_|video_|Add4~13 ; wire \ula_|video_|Add4~14_combout ; wire \ula_|video_|Add4~2_combout ; wire \ula_|video_|Selector5~0_combout ; -wire \ula_|video_|Add4~4_combout ; wire \ula_|video_|vram_address[10]~2_combout ; +wire \ula_|video_|Add4~4_combout ; wire \ula_|video_|vram_address[10]~3_combout ; wire \ula_|video_|Selector3~0_combout ; wire \ula_|video_|Selector2~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \D[6]~87_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \D[6]~88_combout ; -wire \D[6]~89_combout ; -wire \D[6]~111_combout ; -wire \raw_loader_in~input_o ; -wire \D[6]~86_combout ; -wire \D[6]~100_combout ; -wire \D[6]~101_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \D[2]~47_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \D[2]~48_combout ; +wire \D[2]~49_combout ; +wire \D[2]~119_combout ; +wire \D[2]~52_combout ; +wire \D[2]~53_combout ; wire \z80_|pin_control_|bus_db_pin_re~2_combout ; wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; -wire \z80_|bus_control_|db[6]~9_combout ; -wire \z80_|ir_|opcode[6]~feeder_combout ; +wire \z80_|bus_control_|db[2]~12_combout ; +wire \z80_|bus_control_|db[0]~6_combout ; +wire \z80_|bus_control_|db[2]~13_combout ; +wire \z80_|ir_|opcode[2]~feeder_combout ; wire \z80_|execute_|ctl_ir_we~13_combout ; -wire \z80_|pla_decode_|Equal41~0_combout ; -wire \z80_|pla_decode_|Equal41~1_combout ; -wire \z80_|pla_decode_|Equal41~2_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~combout ; -wire \z80_|alu_|db_high[1]~15_combout ; -wire \z80_|alu_|db_high[1]~16_combout ; -wire \z80_|alu_|db_high[1]~17_combout ; -wire \z80_|alu_|db_high[1]~18_combout ; -wire \z80_|alu_|db_high[1]~19_combout ; -wire \z80_|alu_|db_high[1]~20_combout ; -wire \z80_|alu_|db[5]~24_combout ; -wire \z80_|alu_|db[5]~25_combout ; -wire \z80_|sw1_|db_down[5]~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; -wire \z80_|alu_flags_|flags_yf~q ; -wire \z80_|alu_control_|db[5]~13_combout ; -wire \z80_|alu_control_|db[5]~14_combout ; -wire \z80_|alu_control_|db[5]~15_combout ; -wire \D[0]~107_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \Mux2~0_combout ; -wire \Mux2~1_combout ; -wire \D[5]~110_combout ; -wire \D[5]~85_combout ; -wire \D[5]~99_combout ; -wire \z80_|bus_control_|db[5]~14_combout ; -wire \z80_|bus_control_|db[5]~15_combout ; -wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|decode_state_|DFFE_inst4~q ; -wire \z80_|decode_state_|use_ixiy~combout ; -wire \z80_|execute_|ctl_mRead~23_combout ; -wire \z80_|execute_|fMRead~34_combout ; -wire \z80_|execute_|fMRead~31_combout ; +wire \z80_|execute_|ctl_mRead~34_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ; +wire \z80_|execute_|ctl_reg_out_lo~6_combout ; +wire \z80_|execute_|ctl_reg_out_lo~7_combout ; +wire \z80_|execute_|ctl_reg_out_lo~8_combout ; +wire \z80_|alu_control_|db[6]~13_combout ; +wire \z80_|alu_control_|db[6]~21_combout ; +wire \z80_|alu_control_|db[6]~22_combout ; +wire \z80_|reg_file_|db_lo_ds[6]~0_combout ; +wire \z80_|sw1_|db_down[6]~1_combout ; +wire \z80_|alu_control_|db[6]~23_combout ; +wire \z80_|bus_control_|db[6]~8_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; +wire \D[6]~103_combout ; +wire \D[6]~104_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \D[6]~100_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \D[6]~101_combout ; +wire \D[6]~102_combout ; +wire \D[6]~127_combout ; +wire \raw_loader_in~input_o ; +wire \D[6]~99_combout ; +wire \D[6]~114_combout ; +wire \D[6]~115_combout ; +wire \z80_|bus_control_|db[6]~9_combout ; +wire \z80_|pla_decode_|Equal13~0_combout ; +wire \z80_|pla_decode_|Equal38~2_combout ; +wire \z80_|interrupts_|iff1~0_combout ; +wire \z80_|interrupts_|iff1~1_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|interrupts_|iff1~q ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ; +wire \z80_|interrupts_|int_armed~q ; +wire \z80_|interrupts_|DFFE_inst44~q ; +wire \z80_|decode_state_|in_halt~0_combout ; +wire \z80_|pla_decode_|Equal77~1_combout ; +wire \z80_|decode_state_|in_halt~1_combout ; +wire \z80_|decode_state_|in_halt~q ; +wire \z80_|execute_|ctl_mRead~21_combout ; +wire \z80_|execute_|fMRead~35_combout ; +wire \z80_|execute_|fMRead~23_combout ; +wire \z80_|execute_|fMRead~27_combout ; +wire \z80_|execute_|fMRead~28_combout ; wire \z80_|execute_|fMRead~29_combout ; wire \z80_|execute_|fMRead~30_combout ; -wire \z80_|execute_|fMRead~28_combout ; +wire \z80_|execute_|fMRead~31_combout ; wire \z80_|execute_|fMRead~32_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; -wire \z80_|execute_|fMRead~14_combout ; -wire \z80_|execute_|fMRead~10_combout ; -wire \z80_|execute_|fMRead~9_combout ; +wire \z80_|execute_|fMRead~37_combout ; +wire \z80_|execute_|fMRead~33_combout ; +wire \z80_|execute_|fMRead~24_combout ; +wire \z80_|execute_|fMRead~25_combout ; +wire \z80_|execute_|fMRead~16_combout ; wire \z80_|execute_|fMRead~11_combout ; wire \z80_|execute_|fMRead~12_combout ; wire \z80_|execute_|fMRead~13_combout ; +wire \z80_|execute_|fMRead~14_combout ; wire \z80_|execute_|fMRead~15_combout ; -wire \z80_|execute_|fMRead~20_combout ; -wire \z80_|execute_|pc_inc_hold~48_combout ; +wire \z80_|execute_|fMRead~17_combout ; wire \z80_|execute_|fMRead~22_combout ; -wire \z80_|execute_|fMRead~21_combout ; -wire \z80_|execute_|fMRead~23_combout ; -wire \z80_|execute_|fMRead~26_combout ; -wire \z80_|execute_|fMRead~25_combout ; -wire \z80_|execute_|fMRead~27_combout ; -wire \z80_|execute_|fMRead~33_combout ; -wire \z80_|execute_|fMRead~35_combout ; +wire \z80_|execute_|fMRead~34_combout ; +wire \z80_|execute_|fMRead~36_combout ; wire \z80_|pin_control_|bus_db_pin_re~combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \Selector1~0_combout ; -wire \Selector1~1_combout ; -wire \D[1]~103_combout ; -wire \PS2_DAT~input_o ; -wire \reset~clkctrl_outclk ; -wire \ula_|ps2_keyboard_|bit_count~0_combout ; -wire \PS2_CLK~input_o ; -wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~0_combout ; -wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~1_combout ; -wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~q ; -wire \ula_|ps2_keyboard_|clk_edge~0_combout ; -wire \ula_|ps2_keyboard_|clk_edge~q ; -wire \ula_|ps2_keyboard_|bit_count~1_combout ; -wire \ula_|ps2_keyboard_|bit_count~3_combout ; -wire \ula_|ps2_keyboard_|bit_count~2_combout ; -wire \ula_|ps2_keyboard_|always1~0_combout ; -wire \ula_|ps2_keyboard_|LessThan0~0_combout ; -wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; -wire \ula_|zx_keyboard_|Equal0~0_combout ; -wire \ula_|zx_keyboard_|Equal0~1_combout ; -wire \ula_|zx_keyboard_|extended~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~1_combout ; -wire \ula_|ps2_keyboard_|WideXor0~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~2_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~q ; -wire \ula_|zx_keyboard_|extended~q ; -wire \ula_|zx_keyboard_|keys[0][0]~15_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; -wire \ula_|zx_keyboard_|shifted~0_combout ; -wire \ula_|zx_keyboard_|released~0_combout ; -wire \ula_|zx_keyboard_|released~q ; -wire \ula_|zx_keyboard_|WideOr17~0_combout ; -wire \ula_|zx_keyboard_|shifted~2_combout ; -wire \ula_|zx_keyboard_|shifted~3_combout ; -wire \ula_|zx_keyboard_|shifted~q ; -wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~103_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~20_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~21_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~q ; +wire \ula_|zx_keyboard_|keys[3][0]~73_combout ; +wire \ula_|zx_keyboard_|Selector5~0_combout ; +wire \ula_|zx_keyboard_|Selector5~1_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~129_combout ; +wire \ula_|zx_keyboard_|WideOr16~1_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~105_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~130_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~q ; +wire \D[3]~74_combout ; wire \ula_|zx_keyboard_|keys[5][1]~39_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~q ; -wire \ula_|zx_keyboard_|keys[4][1]~31_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~23_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~32_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~33_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~34_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~q ; -wire \D[1]~30_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~24_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~29_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~30_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~25_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~26_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~27_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~q ; -wire \ula_|zx_keyboard_|key_row~0_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~17_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~18_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~q ; -wire \ula_|zx_keyboard_|keys[7][4]~19_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~20_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~21_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~22_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~q ; -wire \D[1]~28_combout ; -wire \D[1]~29_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~43_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~44_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~q ; -wire \ula_|zx_keyboard_|keys[7][1]~45_combout ; -wire \ula_|zx_keyboard_|WideOr16~5_combout ; -wire \ula_|zx_keyboard_|WideOr16~2_combout ; -wire \ula_|zx_keyboard_|WideOr16~4_combout ; -wire \ula_|zx_keyboard_|WideOr16~7_combout ; -wire \ula_|zx_keyboard_|WideOr16~6_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~46_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~q ; -wire \D[1]~31_combout ; -wire \D[1]~32_combout ; -wire \D[1]~33_combout ; -wire \D[1]~34_combout ; -wire \z80_|bus_control_|db[1]~10_combout ; -wire \z80_|bus_control_|db[1]~11_combout ; -wire \z80_|ir_|opcode[1]~feeder_combout ; -wire \z80_|pla_decode_|Equal40~0_combout ; -wire \z80_|pla_decode_|Equal21~1_combout ; -wire \z80_|execute_|ctl_alu_op_low~26_combout ; -wire \z80_|execute_|ctl_alu_op_low~28_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; -wire \z80_|execute_|ctl_alu_op_low~32_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; -wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~10_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; -wire \z80_|execute_|ctl_flags_cf_set~0_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~9_combout ; -wire \z80_|alu_flags_|flags_cf~combout ; -wire \z80_|alu_control_|db[0]~8_combout ; -wire \z80_|sw2_|db_up[0]~0_combout ; -wire \z80_|alu_control_|db[0]~9_combout ; -wire \z80_|alu_control_|db[0]~12_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~67_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~81_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~82_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~83_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~q ; -wire \ula_|zx_keyboard_|keys[4][0]~84_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~85_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~86_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~q ; -wire \D[0]~49_combout ; -wire \ula_|zx_keyboard_|WideOr4~0_combout ; -wire \ula_|zx_keyboard_|keys~76_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~73_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~47_combout ; -wire \ula_|zx_keyboard_|WideOr0~0_combout ; -wire \ula_|zx_keyboard_|keys~74_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~75_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~77_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~q ; -wire \ula_|zx_keyboard_|keys[1][0]~71_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~72_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~q ; -wire \D[0]~47_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~80_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~q ; -wire \ula_|zx_keyboard_|keys[3][0]~78_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~79_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~q ; -wire \ula_|zx_keyboard_|key_row~1_combout ; -wire \D[0]~48_combout ; -wire \ula_|zx_keyboard_|shifted~1_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~91_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~92_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~q ; -wire \ula_|zx_keyboard_|keys[5][4]~63_combout ; -wire \ula_|zx_keyboard_|WideOr16~3_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~132_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~88_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~89_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~q ; -wire \D[0]~50_combout ; -wire \D[0]~51_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~55_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \D[0]~56_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \D[0]~52_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~53_combout ; -wire \D[0]~54_combout ; -wire \D[0]~106_combout ; -wire \D[0]~57_combout ; -wire \D[0]~58_combout ; -wire \z80_|bus_control_|db[0]~16_combout ; -wire \z80_|bus_control_|db[0]~17_combout ; -wire \z80_|pla_decode_|Equal63~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; -wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; -wire \z80_|alu_control_|db[6]~10_combout ; -wire \z80_|alu_control_|db[6]~11_combout ; -wire \z80_|alu_control_|db[4]~30_combout ; -wire \z80_|alu_control_|db[4]~31_combout ; -wire \z80_|alu_control_|db[4]~32_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~119_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~120_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~95_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~121_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~q ; -wire \ula_|zx_keyboard_|keys[3][4]~117_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~136_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~130_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~118_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~q ; -wire \D[4]~78_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~126_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~128_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~129_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~q ; -wire \ula_|zx_keyboard_|keys[6][4]~127_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~q ; -wire \ula_|zx_keyboard_|Equal0~2_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~51_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~125_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~q ; -wire \D[4]~79_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~122_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~123_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~q ; -wire \ula_|zx_keyboard_|key_row~3_combout ; -wire \D[4]~80_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~111_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~97_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~116_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~115_combout ; -wire \ula_|zx_keyboard_|keys[1][4]~q ; -wire \D[4]~77_combout ; -wire \D[4]~81_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \Selector4~0_combout ; -wire \Selector4~1_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ; -wire \D[4]~109_combout ; -wire \D[4]~97_combout ; -wire \D[4]~98_combout ; -wire \z80_|bus_control_|db[4]~18_combout ; -wire \z80_|bus_control_|db[4]~19_combout ; -wire \z80_|pla_decode_|Equal21~0_combout ; -wire \z80_|execute_|ctl_mRead~5_combout ; -wire \z80_|execute_|fIOWrite~2_combout ; -wire \z80_|execute_|fIOWrite~3_combout ; -wire \z80_|execute_|fIOWrite~4_combout ; -wire \z80_|execute_|fIOWrite~5_combout ; -wire \z80_|execute_|ctl_mWrite~11_combout ; -wire \z80_|execute_|ctl_mWrite~12_combout ; -wire \z80_|execute_|ctl_mWrite~13_combout ; -wire \z80_|execute_|ctl_mWrite~14_combout ; -wire \z80_|execute_|ctl_mWrite~15_combout ; -wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; -wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; -wire \z80_|memory_ifc_|wait_mwr~q ; -wire \z80_|memory_ifc_|mwr_wr~q ; -wire \z80_|memory_ifc_|nWR_out~0_combout ; -wire \D[5]~84_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~100_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~99_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~q ; +wire \ula_|zx_keyboard_|keys[3][3]~97_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~98_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~q ; +wire \D[3]~73_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~108_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~109_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~110_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~q ; +wire \ula_|zx_keyboard_|keys[6][3]~111_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~112_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~132_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~133_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~q ; +wire \D[3]~75_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~94_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~93_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~95_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~96_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~q ; +wire \ula_|zx_keyboard_|keys[1][3]~91_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~92_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~q ; +wire \D[3]~72_combout ; +wire \D[3]~76_combout ; +wire \D[3]~122_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \D[3]~79_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \D[3]~77_combout ; +wire \D[3]~80_combout ; +wire \D[3]~81_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \D[3]~124_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \D[3]~123_combout ; +wire \D[3]~78_combout ; +wire \D[3]~82_combout ; +wire \D[3]~108_combout ; +wire \D[3]~109_combout ; +wire \z80_|bus_control_|db[3]~20_combout ; +wire \z80_|bus_control_|db[3]~21_combout ; +wire \z80_|pla_decode_|Equal33~1_combout ; +wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; +wire \z80_|bus_control_|db[0]~4_combout ; +wire \z80_|bus_control_|db[7]~5_combout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ; +wire \D[5]~97_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; wire \Mux0~0_combout ; wire \Mux0~1_combout ; -wire \D[7]~112_combout ; -wire \D[7]~94_combout ; -wire \D[7]~102_combout ; -wire \z80_|bus_control_|db[7]~5_combout ; +wire \D[7]~116_combout ; +wire \D[7]~117_combout ; wire \z80_|bus_control_|db[7]~7_combout ; -wire \z80_|pla_decode_|Equal77~0_combout ; -wire \z80_|execute_|ctl_mWrite~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; -wire \z80_|execute_|ctl_bus_db_we~3_combout ; -wire \z80_|execute_|ctl_bus_db_we~8_combout ; -wire \z80_|execute_|ctl_bus_db_we~2_combout ; -wire \z80_|execute_|ctl_bus_db_we~4_combout ; -wire \z80_|execute_|ctl_bus_db_we~6_combout ; -wire \z80_|execute_|ctl_bus_db_we~7_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~50_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~52_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~q ; -wire \ula_|zx_keyboard_|keys[3][3]~48_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~49_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~q ; -wire \D[2]~35_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~57_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~58_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~q ; -wire \ula_|zx_keyboard_|keys[4][2]~59_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~131_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~60_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~q ; -wire \D[2]~37_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~53_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~55_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~56_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~q ; -wire \ula_|zx_keyboard_|keys[3][2]~54_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~q ; -wire \D[2]~36_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~68_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~69_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~70_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~q ; -wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~62_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~64_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~65_combout ; -wire \ula_|zx_keyboard_|Selector13~0_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~66_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~q ; -wire \D[2]~38_combout ; -wire \D[2]~39_combout ; -wire \D[2]~104_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \D[2]~43_combout ; -wire \D[2]~44_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \D[2]~40_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \D[2]~41_combout ; -wire \D[2]~42_combout ; -wire \D[2]~105_combout ; -wire \D[2]~45_combout ; -wire \D[2]~46_combout ; -wire \z80_|bus_control_|db[2]~12_combout ; -wire \z80_|bus_control_|db[2]~13_combout ; -wire \z80_|pla_decode_|Equal3~1_combout ; -wire \z80_|pla_decode_|Equal43~0_combout ; -wire \z80_|interrupts_|test1~2_combout ; -wire \z80_|interrupts_|test1~3_combout ; -wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ; -wire \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ; -wire \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ; -wire \z80_|clk_delay_|hold_clk_iorq~combout ; -wire \z80_|sequencer_|DFFE_T1_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; -wire \z80_|sequencer_|DFFE_T2_ff~q ; -wire \z80_|resets_|x3~combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \z80_|sequencer_|DFFE_M1_ff~q ; -wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M2_ff~q ; -wire \z80_|execute_|ctl_mWrite~3_combout ; -wire \z80_|execute_|nextM~11_combout ; -wire \z80_|execute_|nextM~8_combout ; -wire \z80_|execute_|nextM~9_combout ; -wire \z80_|execute_|nextM~10_combout ; -wire \z80_|execute_|nextM~12_combout ; -wire \z80_|execute_|nextM~15_combout ; -wire \z80_|execute_|nextM~6_combout ; -wire \z80_|execute_|nextM~7_combout ; -wire \z80_|execute_|nextM~13_combout ; -wire \z80_|execute_|setM1~39_combout ; -wire \z80_|execute_|nextM~5_combout ; -wire \z80_|execute_|nextM~14_combout ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|sequencer_|DFFE_T4_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|sequencer_|DFFE_T5_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; -wire \z80_|sequencer_|T6~q ; -wire \z80_|execute_|setM1~13_combout ; -wire \z80_|pla_decode_|Equal77~1_combout ; -wire \z80_|execute_|setM1~12_combout ; -wire \z80_|execute_|setM1~14_combout ; -wire \z80_|execute_|setM1~41_combout ; -wire \z80_|execute_|setM1~42_combout ; -wire \z80_|execute_|setM1~43_combout ; -wire \z80_|execute_|setM1~44_combout ; -wire \z80_|execute_|setM1~50_combout ; -wire \z80_|execute_|setM1~51_combout ; -wire \z80_|execute_|setM1~6_combout ; -wire \z80_|execute_|setM1~7_combout ; -wire \z80_|execute_|setM1~8_combout ; -wire \z80_|execute_|setM1~9_combout ; -wire \z80_|execute_|setM1~10_combout ; -wire \z80_|execute_|setM1~11_combout ; -wire \z80_|execute_|setM1~17_combout ; -wire \z80_|execute_|setM1~31_combout ; -wire \z80_|execute_|setM1~28_combout ; -wire \z80_|execute_|setM1~30_combout ; -wire \z80_|execute_|setM1~32_combout ; -wire \z80_|execute_|setM1~33_combout ; -wire \z80_|execute_|setM1~25_combout ; -wire \z80_|execute_|setM1~26_combout ; -wire \z80_|execute_|setM1~24_combout ; -wire \z80_|execute_|setM1~27_combout ; -wire \z80_|execute_|setM1~22_combout ; -wire \z80_|execute_|setM1~21_combout ; -wire \z80_|execute_|setM1~53_combout ; -wire \z80_|execute_|setM1~23_combout ; -wire \z80_|execute_|setM1~18_combout ; -wire \z80_|execute_|setM1~19_combout ; -wire \z80_|execute_|setM1~20_combout ; -wire \z80_|execute_|setM1~34_combout ; -wire \z80_|execute_|setM1~52_combout ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; -wire \z80_|sequencer_|DFFE_T3_ff~q ; -wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; -wire \z80_|decode_state_|in_halt~0_combout ; -wire \z80_|decode_state_|in_halt~1_combout ; -wire \z80_|decode_state_|in_halt~q ; +wire \z80_|pla_decode_|Equal41~0_combout ; +wire \z80_|pla_decode_|Equal41~1_combout ; +wire \z80_|pla_decode_|Equal41~2_combout ; +wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; +wire \z80_|execute_|ctl_state_tbl_we~8_combout ; +wire \z80_|decode_state_|DFFE_instCB~q ; +wire \z80_|pla_decode_|Equal52~0_combout ; +wire \z80_|execute_|ctl_66_oe~2_combout ; +wire \z80_|interrupts_|im1~q ; +wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; +wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; wire \z80_|execute_|ctl_bus_db_oe~2_combout ; wire \z80_|execute_|ctl_bus_db_oe~5_combout ; wire \z80_|execute_|ctl_bus_db_oe~6_combout ; wire \z80_|execute_|ctl_bus_db_oe~4_combout ; wire \z80_|execute_|ctl_bus_db_oe~combout ; -wire \z80_|bus_control_|db[0]~6_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~93_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~94_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~q ; -wire \ula_|zx_keyboard_|keys[0][3]~96_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~98_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~q ; -wire \D[3]~65_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~99_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~100_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~q ; -wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~133_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~103_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~q ; -wire \D[3]~66_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~105_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~q ; -wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; -wire \ula_|zx_keyboard_|Selector5~1_combout ; -wire \ula_|zx_keyboard_|Selector5~0_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~134_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~135_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~108_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~q ; -wire \D[3]~67_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~112_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~113_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~114_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~q ; -wire \ula_|zx_keyboard_|keys[6][3]~109_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~110_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~137_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~138_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~q ; +wire \ula_|zx_keyboard_|keys[6][0]~88_combout ; +wire \ula_|zx_keyboard_|shifted~1_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~89_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~q ; +wire \ula_|zx_keyboard_|keys[7][0]~84_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~78_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~85_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~86_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~q ; +wire \D[0]~57_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~81_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~82_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~40_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~83_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~q ; +wire \ula_|zx_keyboard_|keys[5][0]~79_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~80_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~q ; +wire \D[0]~56_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~76_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~77_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~q ; +wire \ula_|zx_keyboard_|keys[4][3]~68_combout ; +wire \ula_|zx_keyboard_|WideOr0~0_combout ; +wire \ula_|zx_keyboard_|keys~69_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~70_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~27_combout ; +wire \ula_|zx_keyboard_|WideOr4~0_combout ; +wire \ula_|zx_keyboard_|keys~71_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~72_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~q ; wire \ula_|zx_keyboard_|key_row~2_combout ; -wire \D[3]~68_combout ; -wire \D[3]~69_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \D[3]~73_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; -wire \D[3]~74_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \D[3]~70_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~71_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~72_combout ; -wire \D[3]~108_combout ; -wire \D[3]~95_combout ; -wire \D[3]~96_combout ; -wire \z80_|bus_control_|db[3]~20_combout ; -wire \z80_|bus_control_|db[3]~21_combout ; -wire \z80_|execute_|ctl_mWrite~4_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~22_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~75_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~q ; +wire \ula_|zx_keyboard_|keys[3][1]~24_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~74_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~q ; +wire \D[0]~54_combout ; +wire \D[0]~55_combout ; +wire \D[0]~58_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; +wire \D[0]~62_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \D[0]~63_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \D[0]~59_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \D[0]~60_combout ; +wire \D[0]~61_combout ; +wire \D[0]~120_combout ; +wire \D[0]~64_combout ; +wire \D[0]~65_combout ; +wire \z80_|bus_control_|db[0]~16_combout ; +wire \z80_|bus_control_|db[0]~17_combout ; +wire \z80_|pla_decode_|Equal3~2_combout ; +wire \z80_|execute_|ctl_state_iy_set~2_combout ; +wire \z80_|decode_state_|DFFE_instIY1~q ; +wire \z80_|decode_state_|use_ixiy~combout ; +wire \z80_|execute_|ixy_d~12_combout ; +wire \z80_|execute_|ixy_d~13_combout ; +wire \z80_|execute_|ixy_d~14_combout ; +wire \z80_|execute_|ixy_d~11_combout ; +wire \z80_|execute_|ixy_d~15_combout ; +wire \z80_|execute_|ctl_flags_xy_we~8_combout ; +wire \z80_|execute_|ctl_flags_xy_we~9_combout ; +wire \z80_|execute_|ctl_alu_oe~11_combout ; +wire \z80_|execute_|ctl_alu_oe~12_combout ; +wire \z80_|execute_|ctl_alu_oe~13_combout ; +wire \z80_|execute_|ctl_alu_oe~14_combout ; +wire \z80_|alu_|db[7]~9_combout ; +wire \z80_|alu_|db[1]~15_combout ; +wire \z80_|alu_|db[1]~16_combout ; +wire \z80_|alu_control_|db[1]~25_combout ; +wire \z80_|alu_control_|db[1]~26_combout ; +wire \z80_|sw1_|db_down[1]~2_combout ; +wire \z80_|alu_control_|db[1]~27_combout ; +wire \z80_|bus_control_|db[1]~10_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~41_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~42_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~q ; +wire \ula_|zx_keyboard_|keys[4][1]~30_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~q ; +wire \ula_|zx_keyboard_|key_row~0_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~36_combout ; +wire \ula_|zx_keyboard_|WideOr16~3_combout ; +wire \ula_|zx_keyboard_|WideOr16~0_combout ; +wire \ula_|zx_keyboard_|WideOr16~2_combout ; +wire \ula_|zx_keyboard_|WideOr16~4_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~37_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~q ; +wire \ula_|zx_keyboard_|keys[6][1]~33_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~34_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~31_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~35_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~q ; +wire \D[1]~32_combout ; +wire \D[1]~33_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~16_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~17_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~18_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~q ; +wire \ula_|zx_keyboard_|keys[0][1]~12_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~13_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~10_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~q ; +wire \D[1]~30_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~25_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~26_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~q ; +wire \ula_|zx_keyboard_|keys[2][1]~23_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~q ; +wire \D[1]~31_combout ; +wire \D[1]~34_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \D[1]~38_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \D[1]~39_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \D[1]~35_combout ; +wire \D[1]~36_combout ; +wire \D[1]~37_combout ; +wire \D[1]~118_combout ; +wire \D[1]~40_combout ; +wire \D[1]~41_combout ; +wire \z80_|bus_control_|db[1]~11_combout ; +wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; +wire \z80_|decode_state_|DFFE_instED~q ; +wire \z80_|pla_decode_|Equal6~0_combout ; +wire \z80_|execute_|ctl_mRead~8_combout ; +wire \z80_|execute_|ctl_bus_db_we~2_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; +wire \z80_|execute_|ctl_bus_db_we~3_combout ; +wire \z80_|execute_|ctl_bus_db_we~8_combout ; +wire \z80_|execute_|ctl_bus_db_we~4_combout ; +wire \z80_|execute_|ctl_bus_db_we~6_combout ; +wire \z80_|execute_|ctl_bus_db_we~7_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~126_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~q ; +wire \ula_|zx_keyboard_|keys[7][4]~125_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~q ; +wire \D[4]~88_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~120_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~121_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~q ; +wire \ula_|zx_keyboard_|keys[4][4]~122_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~123_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~q ; +wire \D[4]~87_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~115_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~116_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~117_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~q ; +wire \ula_|zx_keyboard_|key_row~3_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~118_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~131_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~119_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~q ; +wire \ula_|zx_keyboard_|keys[0][4]~114_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~q ; +wire \ula_|zx_keyboard_|keys[1][4]~113_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~q ; +wire \D[4]~85_combout ; +wire \D[4]~86_combout ; +wire \D[4]~89_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; +wire \D[4]~93_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; +wire \D[4]~94_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \D[4]~90_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \D[4]~91_combout ; +wire \D[4]~92_combout ; +wire \D[4]~125_combout ; +wire \D[4]~110_combout ; +wire \D[4]~111_combout ; +wire \z80_|bus_control_|db[4]~18_combout ; +wire \z80_|bus_control_|db[4]~19_combout ; +wire \z80_|pla_decode_|Equal32~0_combout ; +wire \z80_|pla_decode_|Equal36~0_combout ; +wire \z80_|pla_decode_|Equal43~0_combout ; +wire \z80_|interrupts_|test1~2_combout ; +wire \z80_|interrupts_|test1~3_combout ; +wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ; +wire \z80_|sw1_|db_down[5]~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; +wire \z80_|alu_flags_|flags_yf~q ; +wire \z80_|alu_control_|db[5]~15_combout ; +wire \z80_|alu_control_|db[5]~16_combout ; +wire \z80_|alu_control_|db[5]~17_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \Mux2~0_combout ; +wire \Mux2~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ; +wire \D[5]~112_combout ; +wire \D[5]~113_combout ; +wire \z80_|bus_control_|db[5]~14_combout ; +wire \z80_|bus_control_|db[5]~15_combout ; +wire \z80_|execute_|ctl_mRead~11_combout ; +wire \z80_|execute_|setM1~46_combout ; +wire \z80_|execute_|setM1~40_combout ; +wire \z80_|execute_|nextM~5_combout ; +wire \z80_|execute_|nextM~6_combout ; +wire \z80_|execute_|nextM~7_combout ; +wire \z80_|execute_|nextM~9_combout ; +wire \z80_|execute_|nextM~10_combout ; +wire \z80_|execute_|nextM~8_combout ; +wire \z80_|execute_|nextM~12_combout ; +wire \z80_|execute_|nextM~15_combout ; +wire \z80_|execute_|nextM~13_combout ; +wire \z80_|execute_|nextM~14_combout ; +wire \z80_|sequencer_|ena_M~combout ; +wire \z80_|sequencer_|DFFE_T1_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; +wire \z80_|sequencer_|DFFE_T2_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; +wire \z80_|sequencer_|DFFE_T3_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|sequencer_|DFFE_T4_ff~q ; +wire \z80_|execute_|ctl_mWrite~9_combout ; +wire \z80_|execute_|ctl_flags_sz_we~0_combout ; +wire \z80_|execute_|setM1~54_combout ; +wire \z80_|execute_|setM1~25_combout ; +wire \z80_|execute_|setM1~26_combout ; +wire \z80_|execute_|setM1~27_combout ; +wire \z80_|execute_|setM1~22_combout ; +wire \z80_|execute_|setM1~55_combout ; +wire \z80_|execute_|setM1~23_combout ; +wire \z80_|execute_|setM1~24_combout ; +wire \z80_|execute_|setM1~28_combout ; +wire \z80_|execute_|setM1~11_combout ; +wire \z80_|execute_|setM1~33_combout ; +wire \z80_|execute_|setM1~29_combout ; +wire \z80_|execute_|setM1~31_combout ; +wire \z80_|execute_|setM1~32_combout ; +wire \z80_|execute_|setM1~34_combout ; +wire \z80_|execute_|setM1~20_combout ; +wire \z80_|execute_|setM1~21_combout ; +wire \z80_|execute_|setM1~35_combout ; +wire \z80_|execute_|setM1~15_combout ; +wire \z80_|execute_|setM1~14_combout ; +wire \z80_|execute_|setM1~16_combout ; +wire \z80_|execute_|setM1~10_combout ; +wire \z80_|execute_|setM1~12_combout ; +wire \z80_|execute_|setM1~8_combout ; +wire \z80_|execute_|setM1~9_combout ; +wire \z80_|execute_|setM1~13_combout ; +wire \z80_|execute_|setM1~18_combout ; +wire \z80_|execute_|setM1~19_combout ; +wire \z80_|execute_|setM1~43_combout ; +wire \z80_|execute_|setM1~42_combout ; +wire \z80_|execute_|setM1~44_combout ; +wire \z80_|execute_|setM1~45_combout ; +wire \z80_|execute_|setM1~51_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; +wire \z80_|sequencer_|T6~q ; +wire \z80_|execute_|setM1~52_combout ; +wire \z80_|execute_|setM1~53_combout ; +wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M1_ff~q ; +wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~q ; +wire \z80_|execute_|ctl_apin_mux~1_combout ; wire \z80_|execute_|ctl_apin_mux~2_combout ; wire \z80_|address_pins_|DFFE_apin_latch[0]~0_combout ; -wire \D[0]~59_combout ; -wire \D[0]~60_combout ; -wire \D[1]~61_combout ; -wire \D[1]~62_combout ; -wire \D[2]~63_combout ; -wire \D[2]~64_combout ; -wire \D[3]~75_combout ; -wire \D[3]~76_combout ; -wire \D[4]~82_combout ; -wire \D[4]~83_combout ; -wire \D[6]~92_combout ; -wire \D[6]~93_combout ; +wire \D[0]~66_combout ; +wire \D[0]~67_combout ; +wire \D[0]~121_combout ; +wire \D[1]~68_combout ; +wire \D[1]~69_combout ; +wire \D[2]~70_combout ; +wire \D[2]~71_combout ; +wire \D[3]~83_combout ; +wire \D[3]~84_combout ; +wire \D[4]~95_combout ; +wire \D[4]~96_combout ; +wire \D[5]~126_combout ; +wire \D[5]~98_combout ; +wire \D[6]~105_combout ; +wire \D[6]~106_combout ; +wire \D[7]~128_combout ; +wire \D[7]~107_combout ; +wire \z80_|memory_ifc_|nIORQ_out~0_combout ; wire \z80_|nM1_int~3_combout ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ; @@ -2482,26 +2541,43 @@ wire \z80_|memory_ifc_|DFFE_mreq_ff2~q ; wire \z80_|memory_ifc_|nMREQ_out~0_combout ; wire \z80_|memory_ifc_|nMREQ_out~1_combout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ; -wire \ula_|i2c_loader_|state.Idle~feeder_combout ; wire \ula_|i2c_loader_|divider[0]~15_combout ; wire \ula_|i2c_loader_|divider[1]~5_combout ; wire \ula_|i2c_loader_|divider[1]~6 ; wire \ula_|i2c_loader_|divider[2]~7_combout ; wire \ula_|i2c_loader_|divider[2]~8 ; wire \ula_|i2c_loader_|divider[3]~9_combout ; +wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|divider[3]~10 ; wire \ula_|i2c_loader_|divider[4]~11_combout ; wire \ula_|i2c_loader_|divider[4]~12 ; wire \ula_|i2c_loader_|divider[5]~13_combout ; -wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|WideAnd0~combout ; +wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; +wire \ula_|i2c_loader_|state.Idle~feeder_combout ; wire \ula_|i2c_loader_|state.Idle~q ; wire \ula_|i2c_loader_|phase~0_combout ; wire \ula_|i2c_loader_|phase~1_combout ; -wire \ula_|i2c_loader_|nbit~5_combout ; -wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; wire \ula_|i2c_loader_|Mux42~0_combout ; +wire \ula_|i2c_loader_|nbyte~0_combout ; +wire \ula_|i2c_loader_|nbit~4_combout ; wire \ula_|i2c_loader_|nbyte~4_combout ; +wire \ula_|i2c_loader_|nbit[0]~1_combout ; +wire \ula_|i2c_loader_|nbit[0]~2_combout ; +wire \ula_|i2c_loader_|nbit[0]~3_combout ; +wire \ula_|i2c_loader_|nbit~5_combout ; +wire \ula_|i2c_loader_|state.Pause~1_combout ; +wire \ula_|i2c_loader_|state~27_combout ; +wire \ula_|i2c_loader_|state~24_combout ; +wire \ula_|i2c_loader_|state~26_combout ; +wire \ula_|i2c_loader_|state.Data~0_combout ; +wire \ula_|i2c_loader_|state.Data~q ; +wire \ula_|i2c_loader_|nbit~0_combout ; +wire \ula_|i2c_loader_|state.Pause~0_combout ; +wire \ula_|i2c_loader_|state.Idle~0_combout ; +wire \ula_|i2c_loader_|state.Ack~0_combout ; +wire \ula_|i2c_loader_|state.Ack~1_combout ; +wire \ula_|i2c_loader_|state.Ack~q ; wire \ula_|i2c_loader_|thisbyte[0]~7_combout ; wire \I2C_SDAT~input_o ; wire \ula_|i2c_loader_|nbyte[0]~1_combout ; @@ -2510,12 +2586,8 @@ wire \ula_|i2c_loader_|nbyte[0]~3_combout ; wire \ula_|i2c_loader_|state.Stop~0_combout ; wire \ula_|i2c_loader_|state.Stop~1_combout ; wire \ula_|i2c_loader_|state.Stop~q ; -wire \ula_|i2c_loader_|state.Idle~0_combout ; -wire \ula_|i2c_loader_|nbit~0_combout ; -wire \ula_|i2c_loader_|state.Done~0_combout ; -wire \ula_|i2c_loader_|state.Ack~0_combout ; -wire \ula_|i2c_loader_|state.Ack~1_combout ; -wire \ula_|i2c_loader_|state.Ack~q ; +wire \ula_|i2c_loader_|state.Pause~2_combout ; +wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; wire \ula_|i2c_loader_|nbyte[1]~5_combout ; wire \ula_|i2c_loader_|thisbyte[0]~18_combout ; wire \ula_|i2c_loader_|thisbyte[0]~9 ; @@ -2525,56 +2597,43 @@ wire \ula_|i2c_loader_|thisbyte[2]~12_combout ; wire \ula_|i2c_loader_|thisbyte[2]~13 ; wire \ula_|i2c_loader_|thisbyte[3]~14_combout ; wire \ula_|i2c_loader_|Equal2~0_combout ; -wire \ula_|i2c_loader_|state.Pause~0_combout ; wire \ula_|i2c_loader_|thisbyte[3]~15 ; wire \ula_|i2c_loader_|thisbyte[4]~16_combout ; -wire \ula_|i2c_loader_|state.Pause~1_combout ; -wire \ula_|i2c_loader_|state.Done~2_combout ; -wire \ula_|i2c_loader_|state.Pause~2_combout ; wire \ula_|i2c_loader_|state.Pause~3_combout ; +wire \ula_|i2c_loader_|scl_out~0_combout ; +wire \ula_|i2c_loader_|state.Pause~4_combout ; +wire \ula_|i2c_loader_|state.Pause~5_combout ; +wire \ula_|i2c_loader_|state.Pause~6_combout ; wire \ula_|i2c_loader_|state.Pause~q ; wire \ula_|i2c_loader_|state~25_combout ; wire \ula_|i2c_loader_|state.Start~q ; -wire \ula_|i2c_loader_|nbyte~0_combout ; -wire \ula_|i2c_loader_|nbit[0]~1_combout ; -wire \ula_|i2c_loader_|nbit[0]~2_combout ; -wire \ula_|i2c_loader_|nbit[0]~3_combout ; -wire \ula_|i2c_loader_|nbit[0]~4_combout ; -wire \ula_|i2c_loader_|nbit~6_combout ; -wire \ula_|i2c_loader_|state.Done~1_combout ; -wire \ula_|i2c_loader_|state~27_combout ; -wire \ula_|i2c_loader_|state~24_combout ; -wire \ula_|i2c_loader_|state~26_combout ; -wire \ula_|i2c_loader_|state.Data~0_combout ; -wire \ula_|i2c_loader_|state.Data~q ; -wire \ula_|i2c_loader_|scl_out~0_combout ; -wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; wire \ula_|i2c_loader_|scl_out~1_combout ; wire \ula_|i2c_loader_|scl_out~2_combout ; wire \ula_|i2c_loader_|scl_out~q ; wire \ula_|i2c_loader_|sda_out~_Duplicate_1_q ; -wire \ula_|i2c_loader_|shiftreg~4_combout ; wire \ula_|i2c_loader_|Mux35~0_combout ; -wire \ula_|i2c_loader_|shiftreg~13_combout ; -wire \ula_|i2c_loader_|shiftreg~14_combout ; -wire \ula_|i2c_loader_|shiftreg~15_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~24_combout ; +wire \ula_|i2c_loader_|shiftreg~4_combout ; +wire \ula_|i2c_loader_|shiftreg~19_combout ; +wire \ula_|i2c_loader_|shiftreg~20_combout ; +wire \ula_|i2c_loader_|shiftreg~22_combout ; +wire \ula_|i2c_loader_|shiftreg~23_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~25_combout ; wire \ula_|i2c_loader_|shiftreg[0]~6_combout ; wire \ula_|i2c_loader_|shiftreg[0]~7_combout ; wire \ula_|i2c_loader_|shiftreg[0]~8_combout ; -wire \ula_|i2c_loader_|shiftreg~21_combout ; -wire \ula_|i2c_loader_|shiftreg~22_combout ; -wire \ula_|i2c_loader_|shiftreg~23_combout ; +wire \ula_|i2c_loader_|shiftreg~24_combout ; wire \ula_|i2c_loader_|shiftreg[6]~10_combout ; wire \ula_|i2c_loader_|shiftreg[6]~11_combout ; -wire \ula_|i2c_loader_|shiftreg~18_combout ; -wire \ula_|i2c_loader_|shiftreg~19_combout ; -wire \ula_|i2c_loader_|shiftreg~20_combout ; -wire \ula_|i2c_loader_|shiftreg~16_combout ; +wire \ula_|i2c_loader_|shiftreg[6]~12_combout ; +wire \ula_|i2c_loader_|shiftreg~21_combout ; wire \ula_|i2c_loader_|shiftreg~17_combout ; +wire \ula_|i2c_loader_|shiftreg~15_combout ; +wire \ula_|i2c_loader_|shiftreg~18_combout ; +wire \ula_|i2c_loader_|shiftreg~27_combout ; +wire \ula_|i2c_loader_|shiftreg~14_combout ; +wire \ula_|i2c_loader_|shiftreg~16_combout ; wire \ula_|i2c_loader_|shiftreg~26_combout ; -wire \ula_|i2c_loader_|shiftreg~25_combout ; -wire \ula_|i2c_loader_|shiftreg~12_combout ; +wire \ula_|i2c_loader_|shiftreg~13_combout ; wire \ula_|i2c_loader_|shiftreg~9_combout ; wire \ula_|i2c_loader_|shiftreg[7]~5_combout ; wire \ula_|i2c_loader_|sda_out~0_combout ; @@ -2583,6 +2642,142 @@ wire \ula_|i2c_loader_|sda_out~2_combout ; wire \ula_|i2c_loader_|sda_out~3_combout ; wire \ula_|i2c_loader_|sda_out~4_combout ; wire \ula_|i2c_loader_|sda_out~q ; +wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_fbout ; +wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \sdram_|Mux38~0_combout ; +wire \sdram_|r.rd_pending~q ; +wire \sdram_|r.rf_counter[0]~12_combout ; +wire \sdram_|r.rf_counter[3]~32_combout ; +wire \sdram_|r.rf_counter[0]~13 ; +wire \sdram_|r.rf_counter[1]~14_combout ; +wire \sdram_|r.rf_counter[1]~15 ; +wire \sdram_|r.rf_counter[2]~16_combout ; +wire \sdram_|r.rf_counter[2]~17 ; +wire \sdram_|r.rf_counter[3]~18_combout ; +wire \sdram_|r.rf_counter[3]~19 ; +wire \sdram_|r.rf_counter[4]~20_combout ; +wire \sdram_|r.rf_counter[4]~21 ; +wire \sdram_|r.rf_counter[5]~22_combout ; +wire \sdram_|r.rf_counter[5]~23 ; +wire \sdram_|r.rf_counter[6]~24_combout ; +wire \sdram_|r.rf_counter[6]~25 ; +wire \sdram_|r.rf_counter[7]~26_combout ; +wire \sdram_|Equal0~1_combout ; +wire \sdram_|r.rf_counter[7]~27 ; +wire \sdram_|r.rf_counter[8]~28_combout ; +wire \sdram_|Equal0~0_combout ; +wire \sdram_|r.rf_counter[8]~29 ; +wire \sdram_|r.rf_counter[9]~30_combout ; +wire \sdram_|Equal0~2_combout ; +wire \sdram_|Mux13~8_combout ; +wire \sdram_|Mux37~0_combout ; +wire \sdram_|r.rf_pending~q ; +wire \sdram_|Mux4~0_combout ; +wire \sdram_|Mux4~1_combout ; +wire \sdram_|Mux4~2_combout ; +wire \sdram_|Mux4~3_combout ; +wire \sdram_|r.act_row[1]~0_combout ; +wire \sdram_|process_0~2_combout ; +wire \sdram_|r.act_row[1]~1_combout ; +wire \sdram_|r.act_row[2]~feeder_combout ; +wire \sdram_|Equal7~1_combout ; +wire \sdram_|Equal7~0_combout ; +wire \sdram_|Equal7~2_combout ; +wire \sdram_|Mux39~0_combout ; +wire \sdram_|Mux39~1_combout ; +wire \sdram_|Mux39~2_combout ; +wire \sdram_|r.wr_pending~q ; +wire \sdram_|Mux9~8_combout ; +wire \sdram_|Mux9~9_combout ; +wire \sdram_|Mux6~3_combout ; +wire \sdram_|Mux6~4_combout ; +wire \sdram_|Mux6~2_combout ; +wire \sdram_|Mux6~5_combout ; +wire \sdram_|process_0~3_combout ; +wire \sdram_|Mux6~0_combout ; +wire \sdram_|Mux6~1_combout ; +wire \sdram_|Mux6~6_combout ; +wire \sdram_|r.address[3]~6_combout ; +wire \sdram_|Mux7~2_combout ; +wire \sdram_|n~3_combout ; +wire \sdram_|Mux7~3_combout ; +wire \sdram_|Mux7~4_combout ; +wire \sdram_|Mux7~5_combout ; +wire \sdram_|Mux23~0_combout ; +wire \sdram_|Mux13~7_combout ; +wire \sdram_|Mux10~10_combout ; +wire \sdram_|Mux7~1_combout ; +wire \sdram_|Mux7~6_combout ; +wire \sdram_|Mux5~2_combout ; +wire \sdram_|Mux5~10_combout ; +wire \sdram_|Mux5~3_combout ; +wire \sdram_|Mux5~4_combout ; +wire \sdram_|Mux5~7_combout ; +wire \sdram_|Mux5~8_combout ; +wire \sdram_|Mux5~5_combout ; +wire \sdram_|Mux5~6_combout ; +wire \sdram_|Mux5~9_combout ; +wire \sdram_|n~2_combout ; +wire \sdram_|Mux8~3_combout ; +wire \sdram_|Mux8~4_combout ; +wire \sdram_|Mux9~10_combout ; +wire \sdram_|r.init_counter[0]~0_combout ; +wire \sdram_|Add1~1_cout ; +wire \sdram_|Add1~2_combout ; +wire \sdram_|Add1~3 ; +wire \sdram_|Add1~4_combout ; +wire \sdram_|Add1~5 ; +wire \sdram_|Add1~6_combout ; +wire \sdram_|r.init_counter[3]~1_combout ; +wire \sdram_|Add1~7 ; +wire \sdram_|Add1~8_combout ; +wire \sdram_|Add1~9 ; +wire \sdram_|Add1~10_combout ; +wire \sdram_|Add1~11 ; +wire \sdram_|Add1~12_combout ; +wire \sdram_|Add1~13 ; +wire \sdram_|Add1~14_combout ; +wire \sdram_|Add1~15 ; +wire \sdram_|Add1~16_combout ; +wire \sdram_|Add1~17 ; +wire \sdram_|Add1~18_combout ; +wire \sdram_|Add1~19 ; +wire \sdram_|Add1~20_combout ; +wire \sdram_|Equal2~0_combout ; +wire \sdram_|Equal2~1_combout ; +wire \sdram_|Add1~21 ; +wire \sdram_|Add1~22_combout ; +wire \sdram_|Add1~23 ; +wire \sdram_|Add1~24_combout ; +wire \sdram_|Add1~25 ; +wire \sdram_|Add1~26_combout ; +wire \sdram_|Add1~27 ; +wire \sdram_|Add1~28_combout ; +wire \sdram_|process_0~5_combout ; +wire \sdram_|Equal2~2_combout ; +wire \sdram_|Mux9~11_combout ; +wire \sdram_|Mux9~12_combout ; +wire \sdram_|Mux9~13_combout ; +wire \sdram_|Mux8~0_combout ; +wire \sdram_|Mux8~1_combout ; +wire \sdram_|Mux8~2_combout ; +wire \sdram_|Mux72~0_combout ; +wire \sdram_|Mux72~1_combout ; +wire \sdram_|Mux84~0_combout ; +wire \sdram_|Mux84~1_combout ; +wire \sdram_|Mux3~0_combout ; +wire \sdram_|Mux3~1_combout ; +wire \sdram_|Mux2~0_combout ; +wire \sdram_|Mux2~1_combout ; +wire \sdram_|Mux1~0_combout ; +wire \sdram_|Mux1~1_combout ; +wire \sdram_|Mux0~0_combout ; +wire \sdram_|Mux0~1_combout ; +wire \sdram_|Mux73~0_combout ; +wire \sdram_|Mux73~1_combout ; +wire \sdram_|Mux74~0_combout ; +wire \sdram_|Mux74~1_combout ; +wire \sdram_|Mux75~0_combout ; wire \ula_|i2s_intf_|mclk_r~0_combout ; wire \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|mclk_r~q ; @@ -2616,12 +2811,13 @@ wire \ula_|i2s_intf_|Add0~18_combout ; wire \ula_|i2s_intf_|lrdivider[9]~3_combout ; wire \ula_|i2s_intf_|Equal0~0_combout ; wire \ula_|i2s_intf_|Equal0~2_combout ; -wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; wire \ula_|i2s_intf_|lrclk_r~0_combout ; wire \ula_|i2s_intf_|lrclk_r~q ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_1_q ; +wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|bitcount[0]~5_combout ; +wire \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ; wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|bitcount[4]~15_combout ; wire \ula_|i2s_intf_|bitcount[0]~6 ; @@ -2630,9 +2826,10 @@ wire \ula_|i2s_intf_|bitcount[1]~8 ; wire \ula_|i2s_intf_|bitcount[2]~9_combout ; wire \ula_|i2s_intf_|bitcount[2]~10 ; wire \ula_|i2s_intf_|bitcount[3]~11_combout ; -wire \ula_|i2s_intf_|LessThan0~0_combout ; wire \ula_|i2s_intf_|bitcount[3]~12 ; wire \ula_|i2s_intf_|bitcount[4]~13_combout ; +wire \ula_|i2s_intf_|LessThan0~0_combout ; +wire \ula_|i2s_intf_|shiftreg[1]~1_combout ; wire \ula_|i2s_intf_|Add2~7_cout ; wire \ula_|i2s_intf_|Add2~8_combout ; wire \ula_|i2s_intf_|Add2~20_combout ; @@ -2646,8 +2843,6 @@ wire \ula_|i2s_intf_|Add2~13 ; wire \ula_|i2s_intf_|Add2~14_combout ; wire \ula_|i2s_intf_|Add2~16_combout ; wire \ula_|i2s_intf_|Equal1~0_combout ; -wire \ula_|i2s_intf_|shiftreg[4]~1_combout ; -wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|Equal1~1_combout ; wire \ula_|i2s_intf_|bclk_r~0_combout ; wire \ula_|i2s_intf_|bclk_r~1_combout ; @@ -2659,7 +2854,7 @@ wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; wire \AUD_ADCDAT~input_o ; wire \ula_|i2s_intf_|shiftreg[0]~20_combout ; wire \ula_|i2s_intf_|shiftreg~18_combout ; -wire \ula_|i2s_intf_|shiftreg[4]~2_combout ; +wire \ula_|i2s_intf_|shiftreg[1]~2_combout ; wire \ula_|i2s_intf_|shiftreg~17_combout ; wire \ula_|i2s_intf_|shiftreg~16_combout ; wire \ula_|i2s_intf_|shiftreg~15_combout ; @@ -2676,28 +2871,20 @@ wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; wire \ula_|pcm_outr~0_combout ; wire \ula_|i2s_intf_|shiftreg~6_combout ; wire \ula_|i2s_intf_|shiftreg~5_combout ; +wire \ula_|pcm_outl[14]~feeder_combout ; wire \ula_|i2s_intf_|shiftreg~4_combout ; wire \ula_|i2s_intf_|shiftreg~3_combout ; wire \ula_|i2s_intf_|shiftreg~0_combout ; -wire \ula_|video_|LessThan2~0_combout ; +wire \ula_|border[1]~feeder_combout ; wire \ula_|video_|LessThan6~0_combout ; -wire \ula_|video_|LessThan2~1_combout ; -wire \ula_|video_|LessThan3~0_combout ; -wire \ula_|video_|LessThan0~0_combout ; -wire \ula_|video_|disp_enable~0_combout ; -wire \ula_|video_|disp_enable~1_combout ; wire \ula_|video_|LessThan6~1_combout ; wire \ula_|video_|LessThan4~0_combout ; wire \ula_|video_|screen_en~0_combout ; wire \ula_|video_|screen_en~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; -wire \ula_|video_|attr_prefetch[1]~feeder_combout ; -wire \ula_|video_|Decoder0~1_combout ; -wire \ula_|video_|Decoder0~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; -wire \ula_|video_|attr_prefetch[4]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; wire \ula_|video_|attr_prefetch[7]~feeder_combout ; +wire \ula_|video_|Decoder0~1_combout ; +wire \ula_|video_|Decoder0~0_combout ; wire \ula_|video_|frame[0]~12_combout ; wire \ula_|video_|frame[1]~4_combout ; wire \ula_|video_|frame[1]~5 ; @@ -2710,7 +2897,7 @@ wire \ula_|video_|inverted~combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[6]~feeder_combout ; wire \ula_|video_|Decoder0~2_combout ; -wire \ula_|video_|bits[6]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[4]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[5]~feeder_combout ; @@ -2723,25 +2910,35 @@ wire \ula_|video_|bits_prefetch[2]~feeder_combout ; wire \ula_|video_|bits[2]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[0]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[1]~feeder_combout ; wire \ula_|video_|bits[1]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[3]~feeder_combout ; wire \ula_|video_|Mux0~2_combout ; wire \ula_|video_|Mux0~3_combout ; -wire \ula_|video_|cindex[1]~0_combout ; +wire \ula_|video_|cindex[2]~0_combout ; +wire \ula_|video_|attr_prefetch[4]~feeder_combout ; +wire \ula_|video_|attr_prefetch[1]~feeder_combout ; wire \ula_|video_|cindex[1]~1_combout ; +wire \ula_|video_|LessThan2~0_combout ; +wire \ula_|video_|LessThan2~1_combout ; +wire \ula_|video_|LessThan3~0_combout ; +wire \ula_|video_|LessThan0~0_combout ; +wire \ula_|video_|disp_enable~0_combout ; +wire \ula_|video_|disp_enable~1_combout ; wire \ula_|video_|VGA_R[0]~0_combout ; wire \ula_|video_|attr_prefetch[6]~feeder_combout ; wire \ula_|video_|VGA_B[1]~0_combout ; wire \ula_|video_|VGA_R[1]~1_combout ; -wire \ula_|video_|attr_prefetch[2]~feeder_combout ; +wire \ula_|border[2]~feeder_combout ; wire \ula_|video_|attr_prefetch[5]~feeder_combout ; +wire \ula_|video_|attr_prefetch[2]~feeder_combout ; wire \ula_|video_|cindex[2]~2_combout ; wire \ula_|video_|VGA_G[0]~0_combout ; wire \ula_|video_|VGA_G[1]~1_combout ; +wire \ula_|border[0]~feeder_combout ; wire \ula_|video_|attr_prefetch[0]~feeder_combout ; -wire \ula_|video_|attr[0]~feeder_combout ; wire \ula_|video_|attr_prefetch[3]~feeder_combout ; wire \ula_|video_|cindex[0]~3_combout ; wire \ula_|video_|VGA_B[0]~1_combout ; @@ -2760,23 +2957,171 @@ wire \z80_|memory_ifc_|nRFSH_out~0_combout ; wire \z80_|memory_ifc_|nM1_out~combout ; wire \ula_|beep~0_combout ; wire \ula_|beep~q ; -wire [0:0] \ram0|altsyncram_component|auto_generated|address_reg_a ; +wire \sdram_|Mux26~4_combout ; +wire \sdram_|r.bank[0]~7_combout ; +wire \sdram_|r.bank[0]~11_combout ; +wire \sdram_|r.bank[0]~4_combout ; +wire \sdram_|r.bank[0]~5_combout ; +wire \sdram_|r.bank[0]~6_combout ; +wire \sdram_|r.bank[0]~8_combout ; +wire \sdram_|r.bank[0]~12_combout ; +wire \sdram_|r.bank[0]~9_combout ; +wire \sdram_|Mux25~4_combout ; +wire \sdram_|Mux24~5_combout ; +wire \sdram_|Mux71~0_combout ; +wire \sdram_|process_0~7_combout ; +wire \sdram_|process_0~4_combout ; +wire \sdram_|Mux71~1_combout ; +wire \sdram_|Mux71~2_combout ; +wire \sdram_|Mux71~3_combout ; +wire \sdram_|Mux71~4_combout ; +wire \sdram_|r.bank[0]~10_combout ; +wire \sdram_|Mux9~3_combout ; +wire \sdram_|n~5_combout ; +wire \sdram_|Mux9~4_combout ; +wire \sdram_|Mux9~2_combout ; +wire \sdram_|Equal2~3_combout ; +wire \sdram_|Mux10~2_combout ; +wire \sdram_|Mux10~3_combout ; +wire \sdram_|process_0~6_combout ; +wire \sdram_|Mux10~4_combout ; +wire \sdram_|Mux9~5_combout ; +wire \sdram_|Mux7~0_combout ; +wire \sdram_|Mux9~6_combout ; +wire \sdram_|Mux9~7_combout ; +wire \sdram_|Mux10~11_combout ; +wire \sdram_|Mux10~6_combout ; +wire \sdram_|Mux10~5_combout ; +wire \sdram_|Mux10~7_combout ; +wire \sdram_|Mux10~8_combout ; +wire \sdram_|Mux10~9_combout ; +wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK_outclk ; +wire \sdram_|Mux11~2_combout ; +wire \sdram_|Mux11~3_combout ; +wire \sdram_|Mux11~4_combout ; +wire \sdram_|Mux11~5_combout ; +wire \sdram_|Mux11~6_combout ; +wire \sdram_|Mux11~7_combout ; +wire \sdram_|Mux11~9_combout ; +wire \sdram_|Mux11~8_combout ; +wire \sdram_|Mux24~2_combout ; +wire \sdram_|r.address[0]~7_combout ; +wire \sdram_|r.address[0]~0_combout ; +wire \sdram_|Mux13~9_combout ; +wire \sdram_|Mux13~4_combout ; +wire \sdram_|Mux13~5_combout ; +wire \sdram_|r.address[0]~_Duplicate_1_q ; +wire \sdram_|Mux24~3_combout ; +wire \sdram_|Mux24~4_combout ; +wire \sdram_|r.address[0]~SLOAD_MUX_combout ; +wire \sdram_|r.address[1]~_Duplicate_1feeder_combout ; +wire \sdram_|Mux23~4_combout ; +wire \sdram_|Equal5~0_combout ; +wire \sdram_|Mux23~5_combout ; +wire \sdram_|Mux23~6_combout ; +wire \sdram_|Mux19~0_combout ; +wire \sdram_|r.address[1]~_Duplicate_1_q ; +wire \sdram_|Mux23~2_combout ; +wire \sdram_|Mux23~3_combout ; +wire \sdram_|Mux23~1_combout ; +wire \sdram_|r.address[1]~1_combout ; +wire \sdram_|r.address[1]~SLOAD_MUX_combout ; +wire \sdram_|r.address[3]~8_combout ; +wire \sdram_|r.address[3]~9_combout ; +wire \sdram_|Mux21~0_combout ; +wire \sdram_|Mux22~0_combout ; +wire \sdram_|r.address[3]~10_combout ; +wire \sdram_|r.address[3]~11_combout ; +wire \sdram_|r.address[3]~12_combout ; +wire \sdram_|r.address[3]~13_combout ; +wire \sdram_|r.address[3]~14_combout ; +wire \sdram_|r.address[3]~15_combout ; +wire \sdram_|r.address[3]~16_combout ; +wire \sdram_|r.address[3]~17_combout ; +wire \sdram_|Mux21~1_combout ; +wire \sdram_|Mux20~4_combout ; +wire \sdram_|Mux20~7_combout ; +wire \sdram_|Mux23~7_combout ; +wire \sdram_|Mux20~8_combout ; +wire \sdram_|Mux20~10_combout ; +wire \sdram_|Mux20~9_combout ; +wire \sdram_|Mux20~11_combout ; +wire \sdram_|r.address[4]~_Duplicate_1_q ; +wire \sdram_|Mux20~12_combout ; +wire \sdram_|Mux20~5_combout ; +wire \sdram_|Mux20~6_combout ; +wire \sdram_|r.address[4]~2_combout ; +wire \sdram_|r.address[4]~SLOAD_MUX_combout ; +wire \sdram_|Mux19~1_combout ; +wire \sdram_|Mux19~4_combout ; +wire \sdram_|Mux19~5_combout ; +wire \sdram_|Mux19~6_combout ; +wire \sdram_|Mux19~7_combout ; +wire \sdram_|r.address[5]~_Duplicate_1_q ; +wire \sdram_|Mux19~2_combout ; +wire \sdram_|Mux19~3_combout ; +wire \sdram_|r.address[5]~3_combout ; +wire \sdram_|r.address[5]~SLOAD_MUX_combout ; +wire \sdram_|Mux18~0_combout ; +wire \sdram_|Mux17~0_combout ; +wire \sdram_|Mux16~0_combout ; +wire \sdram_|Mux15~2_combout ; +wire \sdram_|Mux14~0_combout ; +wire \sdram_|Mux14~1_combout ; +wire \sdram_|r.address[10]~4_combout ; +wire \sdram_|r.address[10]~_Duplicate_1_q ; +wire \sdram_|n~4_combout ; +wire \sdram_|Mux14~2_combout ; +wire \sdram_|Mux14~3_combout ; +wire \sdram_|r.address[10]~SLOAD_MUX_combout ; +wire \sdram_|r.address[11]~18_combout ; +wire \sdram_|r.address[11]~5_combout ; +wire \sdram_|r.address[11]~_Duplicate_2feeder_combout ; +wire \sdram_|r.address[11]~_Duplicate_2_q ; +wire \sdram_|Mux13~10_combout ; +wire \sdram_|Mux13~6_combout ; +wire \sdram_|r.address[11]~SLOAD_MUX_combout ; +wire \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout ; +wire \sdram_|r.address[11]~_Duplicate_1_q ; +wire [9:0] \sdram_|r.rf_counter ; +wire [12:0] \sdram_|r.address ; +wire [15:0] \ula_|pcm_outl ; +wire [1:0] \ula_|i2c_loader_|nbyte ; +wire [4:0] \ula_|i2s_intf_|bitcount ; +wire [4:0] \ula_|video_|frame ; +wire [7:0] \ula_|video_|attr_prefetch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_ix_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_pc_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_wz_hi|latch ; wire [1:0] \ram1|altsyncram_component|auto_generated|address_reg_a ; -wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode244w ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode223w ; +wire [3:0] \z80_|alu_|op2_low ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; +wire [15:0] \z80_|address_latch_|abusz ; +wire [7:0] \z80_|data_pins_|dout ; +wire [8:0] \sdram_|r.state ; +wire [14:0] \sdram_|r.init_counter ; +wire [1:0] \sdram_|r.bank ; +wire [12:0] \sdram_|r.act_row ; wire [2:0] \ula_|border ; wire [0:0] \ula_|clocks_|counter ; -wire [7:0] \ula_|i2c_loader_|shiftreg ; -wire [1:0] \ula_|i2c_loader_|nbyte ; -wire [5:0] \ula_|i2c_loader_|divider ; -wire [17:0] \ula_|i2s_intf_|shiftreg ; -wire [4:0] \ula_|i2s_intf_|bitcount ; -wire [15:0] \ula_|i2s_intf_|PCM_INR ; -wire [9:0] \ula_|video_|vga_vc ; -wire [4:0] \ula_|video_|frame ; -wire [7:0] \ula_|video_|bits_prefetch ; -wire [7:0] \ula_|video_|attr_prefetch ; -wire [7:0] \ula_|ps2_keyboard_|clk_filter ; +wire [4:0] \ula_|i2c_loader_|thisbyte ; +wire [1:0] \ula_|i2c_loader_|phase ; +wire [2:0] \ula_|i2c_loader_|nbit ; +wire [9:0] \ula_|i2s_intf_|lrdivider ; +wire [4:0] \ula_|i2s_intf_|bdivider ; +wire [15:0] \ula_|i2s_intf_|PCM_INL ; +wire [12:0] \ula_|video_|vram_address ; +wire [9:0] \ula_|video_|vga_hc ; +wire [7:0] \ula_|video_|bits ; +wire [7:0] \ula_|video_|attr ; +wire [8:0] \ula_|ps2_keyboard_|shiftreg ; +wire [3:0] \ula_|ps2_keyboard_|bit_count ; wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; @@ -2790,126 +3135,119 @@ wire [7:0] \z80_|reg_file_|b2v_latch_iy_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_pc_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_sp_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; -wire [3:0] \z80_|alu_|op2_low ; -wire [3:0] \z80_|alu_|op1_low ; -wire [15:0] \z80_|address_latch_|Q ; -wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; -wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; -wire [7:0] \z80_|data_pins_|dout ; -wire [7:0] \z80_|ir_|opcode ; wire [0:0] \ram0|altsyncram_component|auto_generated|out_address_reg_a ; wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode252w ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode236w ; -wire [15:0] \ula_|pcm_outl ; -wire [4:0] \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk ; -wire [4:0] \ula_|i2c_loader_|thisbyte ; -wire [1:0] \ula_|i2c_loader_|phase ; -wire [2:0] \ula_|i2c_loader_|nbit ; -wire [9:0] \ula_|i2s_intf_|lrdivider ; -wire [4:0] \ula_|i2s_intf_|bdivider ; -wire [15:0] \ula_|i2s_intf_|PCM_INL ; -wire [12:0] \ula_|video_|vram_address ; -wire [9:0] \ula_|video_|vga_hc ; -wire [7:0] \ula_|video_|bits ; -wire [7:0] \ula_|video_|attr ; -wire [8:0] \ula_|ps2_keyboard_|shiftreg ; -wire [3:0] \ula_|ps2_keyboard_|bit_count ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_ix_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_iy_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_pc_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_sp_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_wz_hi|latch ; wire [3:0] \z80_|alu_|result_lo ; wire [3:0] \z80_|alu_|op2_high ; wire [3:0] \z80_|alu_|op1_high ; wire [3:0] \z80_|alu_|b2v_op1_latch_mux_high|Q ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; -wire [15:0] \z80_|address_latch_|abusz ; +wire [15:0] \z80_|address_latch_|Q ; +wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; +wire [7:0] \z80_|ir_|opcode ; +wire [1:0] \sdram_|r.dq_masks ; +wire [4:0] \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk ; +wire [4:0] \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk ; +wire [7:0] \ula_|i2c_loader_|shiftreg ; +wire [5:0] \ula_|i2c_loader_|divider ; +wire [17:0] \ula_|i2s_intf_|shiftreg ; +wire [15:0] \ula_|i2s_intf_|PCM_INR ; +wire [9:0] \ula_|video_|vga_vc ; +wire [7:0] \ula_|video_|bits_prefetch ; +wire [7:0] \ula_|ps2_keyboard_|clk_filter ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_iy_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_sp_hi|latch ; +wire [0:0] \ram0|altsyncram_component|auto_generated|address_reg_a ; +wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode244w ; +wire [3:0] \z80_|alu_|op1_low ; +wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; +wire [4:0] \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus ; wire [4:0] \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; + +assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [0] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [1] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [2] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [3] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [4] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [4]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [0] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [0]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [1] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [1]; @@ -2917,24 +3255,24 @@ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [2] = \ula_|pll_ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [3] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [3]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [4] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [4]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; - assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0]; @@ -2947,12 +3285,12 @@ assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; @@ -2965,55 +3303,47 @@ assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \r assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; @@ -3025,6 +3355,14 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0]; @@ -3037,19 +3375,11 @@ assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; @@ -3061,6 +3391,14 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; + // Location: IOOBUF_X53_Y21_N23 cycloneive_io_obuf \GPIO_1[0]~output ( .i(\z80_|address_pins_|DFFE_apin_latch [0]), @@ -3271,8 +3609,8 @@ defparam \GPIO_1[15]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N9 cycloneive_io_obuf \GPIO_1[16]~output ( - .i(\D[0]~60_combout ), - .oe(\D[0]~107_combout ), + .i(\D[0]~67_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[16]), @@ -3284,8 +3622,8 @@ defparam \GPIO_1[16]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y12_N2 cycloneive_io_obuf \GPIO_1[17]~output ( - .i(\D[1]~62_combout ), - .oe(\D[0]~107_combout ), + .i(\D[1]~69_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[17]), @@ -3297,8 +3635,8 @@ defparam \GPIO_1[17]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y8_N23 cycloneive_io_obuf \GPIO_1[18]~output ( - .i(\D[2]~64_combout ), - .oe(\D[0]~107_combout ), + .i(\D[2]~71_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[18]), @@ -3310,8 +3648,8 @@ defparam \GPIO_1[18]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N2 cycloneive_io_obuf \GPIO_1[19]~output ( - .i(\D[3]~76_combout ), - .oe(\D[0]~107_combout ), + .i(\D[3]~84_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[19]), @@ -3323,8 +3661,8 @@ defparam \GPIO_1[19]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y6_N16 cycloneive_io_obuf \GPIO_1[20]~output ( - .i(\D[4]~83_combout ), - .oe(\D[0]~107_combout ), + .i(\D[4]~96_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[20]), @@ -3336,8 +3674,8 @@ defparam \GPIO_1[20]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y7_N9 cycloneive_io_obuf \GPIO_1[21]~output ( - .i(\D[5]~85_combout ), - .oe(\D[0]~107_combout ), + .i(\D[5]~98_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[21]), @@ -3349,8 +3687,8 @@ defparam \GPIO_1[21]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y0_N2 cycloneive_io_obuf \GPIO_1[22]~output ( - .i(\D[6]~93_combout ), - .oe(\D[0]~107_combout ), + .i(\D[6]~106_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[22]), @@ -3362,8 +3700,8 @@ defparam \GPIO_1[22]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y9_N23 cycloneive_io_obuf \GPIO_1[23]~output ( - .i(\D[7]~94_combout ), - .oe(\D[0]~107_combout ), + .i(\D[7]~107_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[23]), @@ -3401,7 +3739,7 @@ defparam \GPIO_1[28]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y10_N16 cycloneive_io_obuf \GPIO_1[29]~output ( - .i(!\z80_|memory_ifc_|nIORQ_out~0_combout ), + .i(\z80_|memory_ifc_|nIORQ_out~0_combout ), .oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3867,6 +4205,305 @@ defparam \buzzer_out~output .bus_hold = "false"; defparam \buzzer_out~output .open_drain_output = "false"; // synopsys translate_on +// Location: IOOBUF_X11_Y0_N16 +cycloneive_io_obuf \DRAM_BA[0]~output ( + .i(\sdram_|r.bank [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_BA[0]), + .obar()); +// synopsys translate_off +defparam \DRAM_BA[0]~output .bus_hold = "false"; +defparam \DRAM_BA[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y0_N9 +cycloneive_io_obuf \DRAM_BA[1]~output ( + .i(\sdram_|r.bank [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_BA[1]), + .obar()); +// synopsys translate_off +defparam \DRAM_BA[1]~output .bus_hold = "false"; +defparam \DRAM_BA[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y0_N9 +cycloneive_io_obuf \DRAM_DQM[0]~output ( + .i(\sdram_|r.dq_masks [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQM[0]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQM[0]~output .bus_hold = "false"; +defparam \DRAM_DQM[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y0_N16 +cycloneive_io_obuf \DRAM_DQM[1]~output ( + .i(\sdram_|r.dq_masks [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQM[1]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQM[1]~output .bus_hold = "false"; +defparam \DRAM_DQM[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y11_N2 +cycloneive_io_obuf \DRAM_RAS_N~output ( + .i(\sdram_|r.state [2]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_RAS_N), + .obar()); +// synopsys translate_off +defparam \DRAM_RAS_N~output .bus_hold = "false"; +defparam \DRAM_RAS_N~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y11_N9 +cycloneive_io_obuf \DRAM_CAS_N~output ( + .i(\sdram_|r.state [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_CAS_N), + .obar()); +// synopsys translate_off +defparam \DRAM_CAS_N~output .bus_hold = "false"; +defparam \DRAM_CAS_N~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N23 +cycloneive_io_obuf \DRAM_CKE~output ( + .i(vcc), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_CKE), + .obar()); +// synopsys translate_off +defparam \DRAM_CKE~output .bus_hold = "false"; +defparam \DRAM_CKE~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y0_N23 +cycloneive_io_obuf \DRAM_CLK~output ( + .i(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK_outclk ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_CLK), + .obar()); +// synopsys translate_off +defparam \DRAM_CLK~output .bus_hold = "false"; +defparam \DRAM_CLK~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y27_N2 +cycloneive_io_obuf \DRAM_WE_N~output ( + .i(\sdram_|r.state [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_WE_N), + .obar()); +// synopsys translate_off +defparam \DRAM_WE_N~output .bus_hold = "false"; +defparam \DRAM_WE_N~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y0_N23 +cycloneive_io_obuf \DRAM_CS_N~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_CS_N), + .obar()); +// synopsys translate_off +defparam \DRAM_CS_N~output .bus_hold = "false"; +defparam \DRAM_CS_N~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y4_N16 +cycloneive_io_obuf \DRAM_ADDR[0]~output ( + .i(\sdram_|r.address [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[0]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[0]~output .bus_hold = "false"; +defparam \DRAM_ADDR[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y0_N9 +cycloneive_io_obuf \DRAM_ADDR[1]~output ( + .i(\sdram_|r.address [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[1]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[1]~output .bus_hold = "false"; +defparam \DRAM_ADDR[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y0_N2 +cycloneive_io_obuf \DRAM_ADDR[2]~output ( + .i(\sdram_|r.address [2]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[2]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[2]~output .bus_hold = "false"; +defparam \DRAM_ADDR[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X20_Y0_N9 +cycloneive_io_obuf \DRAM_ADDR[3]~output ( + .i(\sdram_|r.address [3]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[3]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[3]~output .bus_hold = "false"; +defparam \DRAM_ADDR[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X25_Y0_N16 +cycloneive_io_obuf \DRAM_ADDR[4]~output ( + .i(\sdram_|r.address [4]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[4]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[4]~output .bus_hold = "false"; +defparam \DRAM_ADDR[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y0_N23 +cycloneive_io_obuf \DRAM_ADDR[5]~output ( + .i(\sdram_|r.address [5]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[5]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[5]~output .bus_hold = "false"; +defparam \DRAM_ADDR[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X20_Y0_N2 +cycloneive_io_obuf \DRAM_ADDR[6]~output ( + .i(\sdram_|r.address [6]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[6]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[6]~output .bus_hold = "false"; +defparam \DRAM_ADDR[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y0_N2 +cycloneive_io_obuf \DRAM_ADDR[7]~output ( + .i(\sdram_|r.address [7]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[7]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[7]~output .bus_hold = "false"; +defparam \DRAM_ADDR[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y5_N23 +cycloneive_io_obuf \DRAM_ADDR[8]~output ( + .i(\sdram_|r.address [8]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[8]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[8]~output .bus_hold = "false"; +defparam \DRAM_ADDR[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y4_N23 +cycloneive_io_obuf \DRAM_ADDR[9]~output ( + .i(\sdram_|r.address [9]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[9]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[9]~output .bus_hold = "false"; +defparam \DRAM_ADDR[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y8_N23 +cycloneive_io_obuf \DRAM_ADDR[10]~output ( + .i(\sdram_|r.address [10]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[10]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[10]~output .bus_hold = "false"; +defparam \DRAM_ADDR[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y7_N2 +cycloneive_io_obuf \DRAM_ADDR[11]~output ( + .i(\sdram_|r.address [11]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[11]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[11]~output .bus_hold = "false"; +defparam \DRAM_ADDR[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y6_N16 +cycloneive_io_obuf \DRAM_ADDR[12]~output ( + .i(\sdram_|r.address[11]~_Duplicate_1_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[12]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[12]~output .bus_hold = "false"; +defparam \DRAM_ADDR[12]~output .open_drain_output = "false"; +// synopsys translate_on + // Location: IOOBUF_X0_Y24_N23 cycloneive_io_obuf \I2C_SCLK~output ( .i(\ula_|i2c_loader_|scl_out~q ), @@ -3893,6 +4530,214 @@ defparam \I2C_SDAT~output .bus_hold = "false"; defparam \I2C_SDAT~output .open_drain_output = "true"; // synopsys translate_on +// Location: IOOBUF_X0_Y23_N16 +cycloneive_io_obuf \DRAM_DQ[0]~output ( + .i(\sdram_|Mux72~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[0]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[0]~output .bus_hold = "false"; +defparam \DRAM_DQ[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y23_N23 +cycloneive_io_obuf \DRAM_DQ[1]~output ( + .i(\sdram_|Mux3~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[1]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[1]~output .bus_hold = "false"; +defparam \DRAM_DQ[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y0_N9 +cycloneive_io_obuf \DRAM_DQ[2]~output ( + .i(\sdram_|Mux2~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[2]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[2]~output .bus_hold = "false"; +defparam \DRAM_DQ[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y7_N9 +cycloneive_io_obuf \DRAM_DQ[3]~output ( + .i(\sdram_|Mux1~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[3]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[3]~output .bus_hold = "false"; +defparam \DRAM_DQ[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y12_N2 +cycloneive_io_obuf \DRAM_DQ[4]~output ( + .i(\sdram_|Mux0~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[4]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[4]~output .bus_hold = "false"; +defparam \DRAM_DQ[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y15_N2 +cycloneive_io_obuf \DRAM_DQ[5]~output ( + .i(\sdram_|Mux73~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[5]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[5]~output .bus_hold = "false"; +defparam \DRAM_DQ[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y15_N9 +cycloneive_io_obuf \DRAM_DQ[6]~output ( + .i(\sdram_|Mux74~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[6]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[6]~output .bus_hold = "false"; +defparam \DRAM_DQ[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N16 +cycloneive_io_obuf \DRAM_DQ[7]~output ( + .i(\sdram_|Mux75~0_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[7]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[7]~output .bus_hold = "false"; +defparam \DRAM_DQ[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y0_N16 +cycloneive_io_obuf \DRAM_DQ[8]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[8]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[8]~output .bus_hold = "false"; +defparam \DRAM_DQ[8]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y0_N2 +cycloneive_io_obuf \DRAM_DQ[9]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[9]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[9]~output .bus_hold = "false"; +defparam \DRAM_DQ[9]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y0_N2 +cycloneive_io_obuf \DRAM_DQ[10]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[10]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[10]~output .bus_hold = "false"; +defparam \DRAM_DQ[10]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y0_N9 +cycloneive_io_obuf \DRAM_DQ[11]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[11]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[11]~output .bus_hold = "false"; +defparam \DRAM_DQ[11]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y0_N23 +cycloneive_io_obuf \DRAM_DQ[12]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[12]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[12]~output .bus_hold = "false"; +defparam \DRAM_DQ[12]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y0_N16 +cycloneive_io_obuf \DRAM_DQ[13]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[13]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[13]~output .bus_hold = "false"; +defparam \DRAM_DQ[13]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y0_N23 +cycloneive_io_obuf \DRAM_DQ[14]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[14]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[14]~output .bus_hold = "false"; +defparam \DRAM_DQ[14]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y12_N9 +cycloneive_io_obuf \DRAM_DQ[15]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[15]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[15]~output .bus_hold = "false"; +defparam \DRAM_DQ[15]~output .open_drain_output = "true"; +// synopsys translate_on + // Location: IOIBUF_X27_Y0_N22 cycloneive_io_ibuf \CLOCK_50~input ( .i(CLOCK_50), @@ -4024,7 +4869,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N4 +// Location: LCCOMB_X25_Y33_N0 cycloneive_lcell_comb \ula_|clocks_|counter[0]~0 ( // Equation(s): // \ula_|clocks_|counter[0]~0_combout = !\ula_|clocks_|counter [0] @@ -4041,7 +4886,7 @@ defparam \ula_|clocks_|counter[0]~0 .lut_mask = 16'h0F0F; defparam \ula_|clocks_|counter[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N5 +// Location: FF_X25_Y33_N1 dffeas \ula_|clocks_|counter[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|counter[0]~0_combout ), @@ -4070,7 +4915,7 @@ defparam \SW[2]~input .bus_hold = "false"; defparam \SW[2]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N10 +// Location: LCCOMB_X25_Y33_N4 cycloneive_lcell_comb \ula_|clocks_|clk_cpu~0 ( // Equation(s): // \ula_|clocks_|clk_cpu~0_combout = \ula_|clocks_|clk_cpu~q $ (((\SW[2]~input_o ) # (!\ula_|clocks_|counter [0]))) @@ -4087,7 +4932,7 @@ defparam \ula_|clocks_|clk_cpu~0 .lut_mask = 16'h0FC3; defparam \ula_|clocks_|clk_cpu~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N11 +// Location: FF_X25_Y33_N5 dffeas \ula_|clocks_|clk_cpu ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|clk_cpu~0_combout ), @@ -4119,40 +4964,6 @@ defparam \ula_|clocks_|clk_cpu~clkctrl .clock_type = "global clock"; defparam \ula_|clocks_|clk_cpu~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N20 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hAAA0; -defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N12 -cycloneive_lcell_comb \z80_|sequencer_|ena_M ( -// Equation(s): -// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|ena_M~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; -defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: IOIBUF_X0_Y16_N8 cycloneive_io_ibuf \KEY[1]~input ( .i(KEY[1]), @@ -4163,7 +4974,7 @@ defparam \KEY[1]~input .bus_hold = "false"; defparam \KEY[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N6 +// Location: LCCOMB_X35_Y10_N0 cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( // Equation(s): // \z80_|interrupts_|nmi_armed~feeder_combout = VCC @@ -4180,11775 +4991,6 @@ defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N2 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hAAFF; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y15_N7 -dffeas \z80_|interrupts_|nmi_armed ( - .clk(!\KEY[1]~input_o ), - .d(\z80_|interrupts_|nmi_armed~feeder_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|nmi_armed~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; -defparam \z80_|interrupts_|nmi_armed .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N12 -cycloneive_lcell_comb \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder ( -// Equation(s): -// \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout = \z80_|interrupts_|nmi_armed~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|interrupts_|nmi_armed~q ), - .cin(gnd), - .combout(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .lut_mask = 16'hFF00; -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( -// Equation(s): -// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_eval_cond~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( -// Equation(s): -// \z80_|execute_|ixy_d~4_combout = (!\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h1100; -defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N30 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N31 -dffeas \z80_|sequencer_|DFFE_M3_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M3_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( -// Equation(s): -// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hD0D0; -defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N2 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N3 -dffeas \z80_|sequencer_|DFFE_M4_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M4_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal32~0_combout = (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(gnd), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal32~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h00CC; -defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N14 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF33; -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N10 -cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( -// Equation(s): -// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instED~q ) # (\z80_|decode_state_|DFFE_instCB~q ) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|decode_state_|table_xx~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; -defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~0_combout = (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal41~2_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal36~0_combout )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|pla_decode_|Equal36~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|pla_decode_|Equal36~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hB3A0; -defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N29 -dffeas \z80_|decode_state_|DFFE_instCB ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instCB~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h0020; -defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_ed_set~combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal2~1_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N17 -dffeas \z80_|decode_state_|DFFE_instED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instED~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & \z80_|decode_state_|DFFE_instED~q )) - - .dataa(\z80_|ir_|opcode [7]), - .datab(gnd), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( -// Equation(s): -// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_im_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal49~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout )) - - .dataa(gnd), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal49~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h3000; -defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~1_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [3])) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; -defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~14_combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~8_combout = (((!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h4FFF; -defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N12 -cycloneive_lcell_comb \z80_|nM1_int~2 ( -// Equation(s): -// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|nM1_int~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|nM1_int~2 .lut_mask = 16'h0055; -defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal49~0_combout ) # ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hEF00; -defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( -// Equation(s): -// \z80_|execute_|ixy_d~7_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & -// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & \z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; -defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal39~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; -defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~2_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal3~2_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal3~2_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( -// Equation(s): -// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( -// Equation(s): -// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( -// Equation(s): -// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( -// Equation(s): -// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~8_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( -// Equation(s): -// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal44~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal44~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0002; -defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( -// Equation(s): -// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hC800; -defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( -// Equation(s): -// \z80_|execute_|ixy_d~13_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|execute_|ixy_d~16_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(gnd), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal50~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h3000; -defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h8800; -defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( -// Equation(s): -// \z80_|execute_|ixy_d~17_combout = (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|pla_decode_|Equal50~0_combout & ((!\z80_|pla_decode_|Equal33~2_combout )))) # (!\z80_|decode_state_|DFFE_inst4~q & (((!\z80_|pla_decode_|Equal50~0_combout & -// !\z80_|pla_decode_|Equal33~2_combout )) # (!\z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal50~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h0537; -defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( -// Equation(s): -// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( -// Equation(s): -// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~12_combout & (((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ixy_d~12_combout & -// (!\z80_|execute_|ixy_d~13_combout & (\z80_|execute_|ixy_d~17_combout ))) - - .dataa(\z80_|execute_|ixy_d~12_combout ), - .datab(\z80_|execute_|ixy_d~13_combout ), - .datac(\z80_|execute_|ixy_d~17_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h30BA; -defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( -// Equation(s): -// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T5_ff~q ) # ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hCC8C; -defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( -// Equation(s): -// \z80_|execute_|ixy_d~15_combout = ((\z80_|pla_decode_|Equal49~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|execute_|ixy_d~11_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) - - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|ixy_d~14_combout ), - .datad(\z80_|execute_|ixy_d~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|execute_|ixy_d~15_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T5_ff~q & -// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N23 -dffeas \z80_|decode_state_|DFFE_instIY1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_iy_set~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instIY1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q )) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(gnd), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0500; -defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~14_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~2 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~18_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~26_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~27_combout = (\z80_|pla_decode_|Equal13~2_combout & \z80_|ir_|opcode [3]) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (((!\z80_|execute_|ctl_mRead~26_combout & !\z80_|execute_|ctl_mRead~27_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_mRead~27_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h02AA; -defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h5D00; -defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~18_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal12~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal55~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0500; -defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|comb~1 ( -// Equation(s): -// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|comb~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~1 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|comb~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~17_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~18_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~17_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~9_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~10_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~8_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~20_combout = (\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h2200; -defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal25~0_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal25~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~21_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~17_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~1_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'hFDFC; -defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal32~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal29~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal41~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal34~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal37~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal35~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal38~2_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal38~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal35~0_combout ) # (\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~3_combout = (\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|pla_decode_|Equal29~0_combout ) # ((\z80_|pla_decode_|Equal24~1_combout ) # (\z80_|reg_control_|reg_sys_we_lo~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|pla_decode_|Equal24~1_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|comb~0 ( -// Equation(s): -// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|comb~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~0 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal47~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|comb~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N8 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|reg_control_|reg_sys_we_lo~3_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # -// (!\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|reg_control_|reg_sys_we_lo~3_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h153F; -defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~22_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (((!\z80_|execute_|ctl_mRead~20_combout & !\z80_|execute_|ctl_mRead~21_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~20_combout ), - .datab(\z80_|execute_|ctl_mRead~21_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~24_combout = (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~18_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_mRead~22_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h0313; -defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~16_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N16 -cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( -// Equation(s): -// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|M5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N17 -dffeas \z80_|sequencer_|M5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|M5~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|M5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|M5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~29 ( -// Equation(s): -// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & -// (((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~29 .lut_mask = 16'h0777; -defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~25_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~16_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout -// & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~17_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~17_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|setM1~29_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|setM1~29_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~7_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~1_combout = (!\z80_|decode_state_|DFFE_instED~q & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & !\z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~14_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~14 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_state_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~14_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((!\z80_|execute_|ctl_state_alu~14_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'h115F; -defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h1F3F; -defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|pla_decode_|Equal29~0_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal29~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|pla_decode_|Equal29~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; -defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (\z80_|reg_control_|reg_sel_pc~1_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~0_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h40C0; -defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( -// Equation(s): -// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|ctl_state_alu~8_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~8_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~17 .lut_mask = 16'h7000; -defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~6_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0004; -defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( -// Equation(s): -// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|execute_|ctl_mRead~18_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & -// (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~16 .lut_mask = 16'h135F; -defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|pla_decode_|Equal41~0_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal46~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [2] & \z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal46~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~17_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~6_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_flags_alu~17_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~6 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_flags_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]) - - .dataa(\z80_|ir_|opcode [6]), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0505; -defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~6_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~16_combout = (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|execute_|ctl_flags_alu~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & \z80_|execute_|ctl_reg_in_hi~3_combout )) - - .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( -// Equation(s): -// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|fMRead~17_combout & (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|fMRead~16_combout & \z80_|execute_|ctl_mWrite~8_combout ))) - - .dataa(\z80_|execute_|fMRead~17_combout ), - .datab(\z80_|execute_|ctl_sw_2d~4_combout ), - .datac(\z80_|execute_|fMRead~16_combout ), - .datad(\z80_|execute_|ctl_mWrite~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( -// Equation(s): -// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_mRead~24_combout & (\z80_|execute_|ctl_reg_in_hi~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|fMRead~18_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~24_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datad(\z80_|execute_|fMRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~36 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~36_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~36 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~9_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~9 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_op_low~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h007F; -defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~11_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h00AA; -defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal9~1_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ixy_d~6_combout & -// (((!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_mRead~11_combout ))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~4_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~7_combout & (!\z80_|execute_|ctl_ir_we~11_combout & ((!\z80_|execute_|ctl_ir_we~12_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout & (((!\z80_|execute_|ctl_ir_we~12_combout ) # -// (!\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0577; -defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~8_combout = (\z80_|execute_|ctl_alu_shift_oe~44_combout & (\z80_|execute_|ctl_sw_2d~7_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datab(\z80_|execute_|ctl_sw_2d~7_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~5_combout & (\z80_|execute_|fMRead~19_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & \z80_|execute_|ctl_sw_2d~8_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~5_combout ), - .datab(\z80_|execute_|fMRead~19_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datad(\z80_|execute_|ctl_sw_2d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (!\z80_|execute_|ctl_sw_1d~5_combout & (\z80_|execute_|ctl_sw_1d~4_combout & \z80_|execute_|ctl_sw_2d~9_combout ))) - - .dataa(\z80_|execute_|ctl_im_we~combout ), - .datab(\z80_|execute_|ctl_sw_1d~5_combout ), - .datac(\z80_|execute_|ctl_sw_1d~4_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal47~0_combout ))) # (!\z80_|execute_|ctl_sw_1d~6_combout ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7333; -defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~8_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~8 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_alu_op_low~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal2~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'h0111; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0088; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0037; -defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_zero~combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~4 ( -// Equation(s): -// \z80_|alu_|db_low[2]~4_combout = ((\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~4 .lut_mask = 16'h555D; -defparam \z80_|alu_|db_low[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_sw_4u~1_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # -// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_shift_oe~30_combout & (\z80_|execute_|ctl_alu_shift_oe~29_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal69~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal69~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~5_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [5]) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h00AA; -defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~5_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~12_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~12 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_alu_op_low~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal56~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal56~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~11_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~11 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op_low~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|nextM~2 ( -// Equation(s): -// \z80_|execute_|nextM~2_combout = (!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0011; -defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~4_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal69~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .lut_mask = 16'h0103; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~5_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hC0D0; -defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~15_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h0F3F; -defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_ir_we~7_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # -// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # -// (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~15_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~3_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ctl_ir_we~11_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h3000; -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_alu_core_R~4_combout & !\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout -// ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal48~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~18_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'hBBBF; -defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~17_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0100; -defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~18_combout = ((!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|ctl_iorw~10_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (\z80_|execute_|ctl_alu_shift_oe~18_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~19_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~13_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~13 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_alu_bs_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_alu_bs_oe~13_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~13_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal20~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal20~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal68~2_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|pla_decode_|Equal68~2_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~13 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_op_low~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~15_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_alu_op_low~13_combout & !\z80_|execute_|ctl_alu_op_low~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hBBBF; -defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_flags_bus~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~11 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .lut_mask = 16'hAFBF; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h70F0; -defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~8_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|execute_|ixy_d~10_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~9_combout = ((!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_flags_bus~8_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_flags_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_flags_bus~14_combout & (\z80_|execute_|ctl_flags_bus~11_combout & (\z80_|execute_|ctl_flags_bus~10_combout & \z80_|execute_|ctl_flags_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~14_combout ), - .datab(\z80_|execute_|ctl_flags_bus~11_combout ), - .datac(\z80_|execute_|ctl_flags_bus~10_combout ), - .datad(\z80_|execute_|ctl_flags_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_flags_xy_we~18_combout & (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout ))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datad(\z80_|execute_|ctl_flags_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & ((!\z80_|execute_|ctl_state_alu~14_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|execute_|ctl_ir_we~14_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) # -// (!\z80_|execute_|ctl_mWrite~3_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h3030; -defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h3700; -defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|pla_decode_|Equal41~2_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|execute_|ctl_bus_db_oe~0_combout & \z80_|execute_|ctl_alu_op1_sel_bus~12_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~13_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal48~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (((\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h1100; -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[2]~14_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N17 -dffeas \z80_|alu_|op1_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'h88C8; -defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~10_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~10 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op_low~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|fMWrite~11 ( -// Equation(s): -// \z80_|execute_|fMWrite~11_combout = ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~11 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|fMWrite~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~21_combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (\z80_|execute_|ctl_alu_op_low~9_combout ))) # (!\z80_|execute_|fMWrite~11_combout ) - - .dataa(\z80_|execute_|fMWrite~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~22_combout = ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~10_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~10_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~16_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h7737; -defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~17_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~16_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h2200; -defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel~36_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel~36 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & (\z80_|execute_|ctl_state_alu~8_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datab(\z80_|execute_|ctl_state_alu~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~18_combout = (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_mWrite~3_combout & -// (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~11_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~19_combout = ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|execute_|ctl_alu_op_low~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~33_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~12_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'h77F7; -defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'hF0FF; -defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~23_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_mRead~36_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|execute_|ctl_alu_op_low~22_combout ) # (((\z80_|execute_|ctl_alu_op_low~20_combout ) # (\z80_|execute_|ctl_alu_op_low~23_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ixy_d~9_combout & (((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|execute_|ixy_d~5_combout & -// (\z80_|pla_decode_|Equal40~1_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'hEAE0; -defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~34_combout = (\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFF08; -defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~combout = ((\z80_|execute_|ctl_alu_op_low~24_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~26_combout ))) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~26_combout ) # (\z80_|execute_|ctl_mRead~27_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~18_combout ) - - .dataa(\z80_|execute_|ctl_mRead~26_combout ), - .datab(\z80_|execute_|ctl_mRead~27_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hEF0F; -defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~39_combout = (\z80_|execute_|ctl_alu_shift_oe~37_combout ) # (((\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~42_combout = (\z80_|execute_|ctl_alu_shift_oe~40_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'hF200; -defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~21_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~22_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h3F20; -defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~23_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~22_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~22_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h0CEC; -defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~23_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~23_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'h32F0; -defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~25_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~24_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|ctl_alu_shift_oe~24_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h22EA; -defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~14_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~14 .lut_mask = 16'hC0C8; -defparam \z80_|execute_|ctl_alu_bs_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~26_combout = (!\z80_|execute_|ctl_alu_bs_oe~14_combout & ((\z80_|execute_|ctl_alu_shift_oe~25_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_bus_db_oe~1_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & -// (\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_bus_db_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~28_combout = ((\z80_|execute_|ctl_alu_shift_oe~27_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~20_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~44_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'hFF5F; -defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~4_combout -// & (\z80_|execute_|ctl_ir_we~10_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hEAC8; -defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|execute_|ctl_alu_bs_oe~10_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~32_combout = (!\z80_|execute_|ctl_alu_bs_oe~11_combout & ((\z80_|execute_|ctl_alu_shift_oe~28_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h00CF; -defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~32_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_alu_shift_oe~16_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout )))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hFF51; -defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|execute_|ctl_alu_op_low~11_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_state_alu~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_ir_we~7_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # -// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h3F20; -defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_ir_we~10_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~36_combout = (((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~12_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~26_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~36_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~9_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q ))) # (!\z80_|pla_decode_|Equal47~0_combout ) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~0_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hFDDD; -defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (\z80_|pla_decode_|Equal48~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h0088; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~9_combout = (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & (\z80_|execute_|ctl_flags_xy_we~8_combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h1300; -defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal8~0_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h0C00; -defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~9_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~9 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal39~0_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & -// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~1_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~1 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal11~1_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal11~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~10_combout = (\z80_|execute_|ctl_flags_alu~9_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_flags_sz_we~3_combout & !\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~9_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_alu~10_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~7_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal13~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~2 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~2_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) - - .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~2 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_pf_sel[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~2_combout = (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~25_combout = (\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_ir_we~14_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout ) # -// (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~25 .lut_mask = 16'h0377; -defparam \z80_|execute_|ctl_bus_inc_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~25_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hCC8C; -defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~10_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hCCC4; -defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'h3331; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~17_combout = (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~5_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h5557; -defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~6_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|reg_control_|reg_sys_we_lo~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'h7000; -defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & -// (((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal2~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|table_xx~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h0002; -defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|ctl_state_alu~7_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~2_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|nM1_int~2_combout & -// (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_mWrite~3_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & -// (((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h02AA; -defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & (\z80_|execute_|ctl_alu_res_oe~0_combout & !\z80_|execute_|ctl_alu_oe~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~11_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_alu_res_oe~1_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'h8C88; -defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( -// Equation(s): -// \z80_|alu_|db_high[3]~2_combout = (\z80_|execute_|ctl_alu_bs_oe~combout ) # ((\z80_|execute_|ctl_alu_op1_oe~1_combout ) # ((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFFEF; -defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( -// Equation(s): -// \z80_|alu_|db_high[3]~3_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout ) # (\z80_|alu_|db_high[3]~2_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(gnd), - .datac(\z80_|alu_|db_high[3]~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hFAFA; -defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~24 ( -// Equation(s): -// \z80_|alu_|db_low[2]~24_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[2]~3_combout & (\z80_|alu_|db_low[2]~6_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[2]~3_combout & -// \z80_|alu_|db_low[2]~6_combout )) # (!\z80_|alu_|db_high[3]~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[2]~3_combout ), - .datac(\z80_|alu_|db_low[2]~6_combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~24 .lut_mask = 16'hC0D5; -defparam \z80_|alu_|db_low[2]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~7 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~7_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~7 .lut_mask = 16'h0AAA; -defparam \z80_|reg_control_|reg_sys_we_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = ((!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|reg_control_|reg_sys_we_lo~7_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~10_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hFF57; -defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~43_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'hFF57; -defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~26_combout = (\z80_|execute_|ctl_alu_core_S~10_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & \z80_|execute_|ctl_bus_inc_oe~25_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_mWrite~9_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~9_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|execute_|ctl_alu_oe~8_combout & (\z80_|execute_|ctl_alu_oe~4_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|ctl_bus_db_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~8_combout ), - .datab(\z80_|execute_|ctl_alu_oe~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mWrite~16_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~6_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~7_combout = (\z80_|execute_|ctl_alu_oe~6_combout & (((!\z80_|execute_|ctl_mRead~27_combout & !\z80_|execute_|ctl_mRead~26_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~27_combout ), - .datac(\z80_|execute_|ctl_mRead~26_combout ), - .datad(\z80_|execute_|ctl_alu_oe~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~12_combout = (\z80_|execute_|ctl_alu_oe~11_combout ) # (((!\z80_|execute_|ctl_alu_oe~7_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_oe~5_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), - .datab(\z80_|execute_|ctl_alu_oe~5_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), - .datad(\z80_|execute_|ctl_alu_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_alu_oe~12_combout ) # (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_flags_alu~10_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~12_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~14_combout = (\z80_|execute_|ctl_alu_oe~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_oe~13_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hF5F5; -defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & -// (((!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mRead~26_combout ))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|nextM~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~53 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'h8C00; -defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~54 ( -// Equation(s): -// \z80_|execute_|setM1~54_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~54 .lut_mask = 16'hABFF; -defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~7_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((!\z80_|execute_|ctl_alu_oe~3_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout )) # -// (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_alu_oe~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|setM1~54_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_sw_2u~4_combout )) - - .dataa(\z80_|execute_|setM1~54_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~1_combout ), - .datad(\z80_|execute_|ctl_sw_2u~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_reg_gp_sel~36_combout & (\z80_|execute_|comb~0_combout $ ((!\z80_|ir_|opcode [0])))) # (!\z80_|execute_|ctl_reg_gp_sel~36_combout & (!\z80_|execute_|ctl_sw_2u~5_combout & -// (\z80_|execute_|comb~0_combout $ (!\z80_|ir_|opcode [0])))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'h82C3; -defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~35_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (\z80_|execute_|ctl_inc_cy~35_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_inc_cy~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hBF00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~6_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & -// (((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~2_combout & (\z80_|execute_|ctl_sw_2u~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|execute_|ctl_mRead~8_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(\z80_|execute_|ctl_sw_2u~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~10_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_op_low~13_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|rsel3 ( -// Equation(s): -// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|rsel3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel3 .lut_mask = 16'h7878; -defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & -// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7707; -defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~6_combout = (!\z80_|execute_|ctl_sw_2u~6_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout & \z80_|execute_|ctl_reg_out_hi~5_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2u~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~7_combout = ((\z80_|execute_|ctl_reg_out_hi~8_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|rsel0 ( -// Equation(s): -// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|rsel0~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel0 .lut_mask = 16'h5AAA; -defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .lut_mask = 16'h0444; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h7030; -defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~11_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~11_combout )) # (!\z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~14_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal77~0_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h0D0F; -defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_1d~8_combout ) # (!\z80_|execute_|ctl_sw_2d~14_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2d~10_combout ), - .datab(\z80_|execute_|ctl_sw_2d~14_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hBFAA; -defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # (\z80_|execute_|ctl_alu_shift_oe~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFEAA; -defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~11_combout ) # ((\z80_|execute_|ctl_sw_2d~12_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~11_combout ), - .datac(\z80_|execute_|ctl_sw_2d~12_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~34_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_alu_oe~2_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_inc_cy~34_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~75_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|pla_decode_|Equal38~2_combout & ((!\z80_|pla_decode_|Equal37~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|pla_decode_|Equal38~2_combout -// & !\z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|pla_decode_|Equal38~2_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal37~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~75_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal29~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal4~0_combout = (\z80_|execute_|comb~1_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|execute_|comb~1_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~48_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~46_combout = (\z80_|execute_|ctl_bus_inc_oe~48_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|pla_decode_|Equal4~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & ((!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & -// !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~92 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~92_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~92 .lut_mask = 16'h5F7F; -defparam \z80_|execute_|ctl_inc_cy~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~1 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal19~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~38_combout = (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal3~1_combout )) # (!\z80_|pla_decode_|Equal19~1_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal19~1_combout ), - .datac(\z80_|execute_|ctl_sw_4u~0_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~93 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~93_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~93 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~39_combout = (\z80_|execute_|ctl_inc_cy~93_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_inc_cy~93_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~24_combout = (\z80_|execute_|ctl_inc_cy~92_combout & (\z80_|execute_|ctl_inc_cy~38_combout & \z80_|execute_|ctl_inc_cy~39_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~92_combout ), - .datac(\z80_|execute_|ctl_inc_cy~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~24 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_bus_inc_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~1_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (\z80_|execute_|ctl_bus_inc_oe~46_combout & (\z80_|execute_|ctl_inc_cy~53_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~53_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~1 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~44_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'h1333; -defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~0_combout = (\z80_|execute_|ctl_bus_inc_oe~44_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & ((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~0 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_reg_gp_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (\z80_|execute_|ctl_reg_gp_we~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout & -// (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h3F15; -defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_sw_4u~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datad(\z80_|execute_|ctl_sw_4u~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( -// Equation(s): -// \z80_|execute_|fMRead~3_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|execute_|ctl_state_alu~14_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) # -// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_mRead~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h135F; -defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~15_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~12_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_sw_4u~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & -// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~94 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~94_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~94_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~94 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~87_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) - - .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~94_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~16_combout = (\z80_|execute_|fMRead~3_combout & (\z80_|execute_|ctl_reg_sel_wz~15_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ))) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~6_combout = ((\z80_|execute_|ctl_sw_4u~5_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout ))) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|execute_|ctl_sw_4u~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~6_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal1~5_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N22 -cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( -// Equation(s): -// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal1~6_combout & \z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal1~6_combout ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_exx~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N23 -dffeas \z80_|reg_control_|bank_exx ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_exx~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_exx~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_exx .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N26 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de1~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hF0D2; -defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N27 -dffeas \z80_|reg_control_|bank_hl_de1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal2~1_combout & \z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal2~1_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hC888; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h00FE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~12_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~13_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal50~0_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hEEEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( -// Equation(s): -// \z80_|execute_|fMWrite~3_combout = (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h0001; -defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [2]) # ((\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFAF; -defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( -// Equation(s): -// \z80_|execute_|fMRead~2_combout = (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_flags_bus~5_combout )) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~14_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMRead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h1010; -defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~19_combout = (\z80_|execute_|fMWrite~3_combout & (\z80_|execute_|fMRead~2_combout & !\z80_|execute_|ctl_ir_we~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|fMWrite~3_combout ), - .datac(\z80_|execute_|fMRead~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'h00C0; -defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [2] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h50F0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~14_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hC5CD; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~15_combout )))) # (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout & ((\z80_|execute_|ctl_ir_we~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_ir_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hCAC0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'h0050; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~47_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q ))) # (!\z80_|execute_|ctl_mRead~8_combout ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'hFF37; -defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|ctl_reg_use_sp~2_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_bus_inc_oe~47_combout & \z80_|execute_|nextM~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal6~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0050; -defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~21_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~5_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_sw_1d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & -// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'hAB00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~20_combout = (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mRead~14_combout & !\z80_|pla_decode_|Equal49~0_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .lut_mask = 16'h0101; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~22_combout = (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~21_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & ((\z80_|sequencer_|M5~q ) # (\z80_|sequencer_|DFFE_M4_ff~q )))) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|decode_state_|DFFE_instED~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'h0032; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout & \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~36_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h20AA; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|pla_decode_|Equal20~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h0505; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~14_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~14 .lut_mask = 16'hF0FF; -defparam \z80_|execute_|ctl_flags_hf_cpl~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (!\z80_|pla_decode_|Equal68~2_combout & (!\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_flags_hf_cpl~14_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|pla_decode_|Equal68~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~47 ( -// Equation(s): -// \z80_|execute_|setM1~47_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0015; -defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~48 ( -// Equation(s): -// \z80_|execute_|setM1~48_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|execute_|ctl_flags_hf_cpl~10_combout & (\z80_|execute_|setM1~47_combout & \z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .datac(\z80_|execute_|setM1~47_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~48 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~13_combout = (\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_iorw~10_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_flags_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~48_combout )))) - - .dataa(\z80_|execute_|setM1~48_combout ), - .datab(\z80_|execute_|ctl_flags_oe~1_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h0070; -defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~28_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & !\z80_|execute_|ctl_reg_in_hi~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~40_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~40_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~40_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~12_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~43_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~12_combout & (\z80_|execute_|ctl_inc_cy~43_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_inc_cy~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( -// Equation(s): -// \z80_|execute_|fMRead~6_combout = (\z80_|pla_decode_|Equal29~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ixy_d~7_combout ))) # (!\z80_|pla_decode_|Equal29~0_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & -// !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal29~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h0357; -defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( -// Equation(s): -// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & -// !\z80_|execute_|ctl_mRead~16_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h111F; -defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( -// Equation(s): -// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|fMRead~7_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|fMRead~7_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h10F0; -defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .datac(\z80_|execute_|fMRead~6_combout ), - .datad(\z80_|execute_|fMRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~13_combout = (\z80_|execute_|ctl_state_alu~8_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal52~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~8_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~10_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'h3331; -defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) # -// (!\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~9_combout = (\z80_|execute_|ctl_state_alu~14_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|execute_|ctl_state_alu~14_combout & (\z80_|pla_decode_|Equal52~1_combout & -// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'hF3A2; -defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~13_combout ), - .datab(\z80_|execute_|ctl_state_alu~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~9_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hFD00; -defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~4_combout = (((\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal62~2_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = ((!\z80_|execute_|ctl_mRead~4_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h373F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~13_combout ), - .datab(\z80_|execute_|ctl_state_alu~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~9_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h00FD; -defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~3 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~3_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal64~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal64~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~3 .lut_mask = 16'hEEFF; -defparam \z80_|execute_|ctl_pf_sel[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_flags_pf_we~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & (\z80_|execute_|ctl_alu_oe~7_combout & \z80_|execute_|ctl_pf_sel[0]~3_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .datac(\z80_|execute_|ctl_alu_oe~7_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_state_alu~14_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~15 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_state_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [4] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (\z80_|execute_|ctl_state_alu~15_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )) - - .dataa(\z80_|execute_|ctl_state_alu~15_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h00A0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~29_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ) # (((\z80_|execute_|ctl_reg_gp_sel[1]~23_combout & \z80_|ir_|opcode [5])) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal11~0_combout & -// ((\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mRead~5_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((\z80_|ir_|opcode [1] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(\z80_|execute_|ctl_sw_2u~5_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hFF70; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~20_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hF7F7; -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ctl_reg_sys_hilo~20_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h22A2; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N18 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0010; -defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h0F0B; -defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h00E4; -defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; -defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N15 -dffeas \z80_|reg_control_|bank_hl_de2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de2~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))))) - - .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hAC00; -defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & (((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~4_combout = (!\z80_|execute_|ctl_reg_in_hi~7_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & \z80_|execute_|ctl_state_alu~15_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_state_alu~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'h1100; -defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout & ((!\z80_|execute_|ctl_iorw~10_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datac(\z80_|execute_|ctl_iorw~10_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h004C; -defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout -// )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|pla_decode_|Equal25~0_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .lut_mask = 16'hA200; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout & !\z80_|execute_|ctl_sw_1d~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), - .datad(\z80_|execute_|ctl_sw_1d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & \z80_|execute_|ctl_reg_gp_we~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~6_combout = (((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_reg_gp_we~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .datab(\z80_|execute_|ctl_sw_4u~3_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~7_combout & (((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h00F7; -defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_flags_oe~1_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h1033; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_al_we~14_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFBF0; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = (\z80_|execute_|rsel3~combout & (((!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'h40CC; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (((\z80_|execute_|ctl_ir_we~7_combout ) # (\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo~20_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_iorw~11_combout ) # ((\z80_|execute_|ctl_state_alu~14_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout )))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~25_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ) # -// (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hF5FF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|execute_|rsel0~combout & ((\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & -// (((\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )) # (!\z80_|execute_|setM1~48_combout ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'hCD05; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~6_combout & (!\z80_|execute_|ixy_d~9_combout ))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|pla_decode_|Equal10~0_combout )) # -// (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h1357; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal2~1_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~40 ( -// Equation(s): -// \z80_|execute_|setM1~40_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal8~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~40 .lut_mask = 16'h1155; -defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & ((\z80_|execute_|setM1~40_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h1101; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~93 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~93_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & ((\z80_|reg_control_|reg_sel_hl~0_combout ) # (\z80_|reg_control_|reg_sel_hl2~0_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .lut_mask = 16'h0E00; -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h00D8; -defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h0F00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout -// & (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~10_combout = (\z80_|execute_|ctl_reg_in_hi~9_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_gp_we~5_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~19_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_mRead~22_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~8_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # (\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h00B0; -defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFECC; -defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~3_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout )) - - .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & !\z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N20 -cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( -// Equation(s): -// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|pla_decode_|Equal21~2_combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y12_N21 -dffeas \z80_|reg_control_|bank_af ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_af~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_af~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_af .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (!\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h1000; -defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; -defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h2200; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal19~0_combout & ((!\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout ) # -// (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'h035F; -defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal33~0_combout )) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hF8F8; -defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~7_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~6_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_bus~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( -// Equation(s): -// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~24 .lut_mask = 16'h0777; -defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~13_combout = (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datad(\z80_|execute_|ctl_flags_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~combout = (\z80_|execute_|ctl_flags_bus~7_combout ) # (((\z80_|execute_|ctl_flags_hf2_we~combout ) # (!\z80_|execute_|ctl_flags_bus~13_combout )) # (!\z80_|execute_|fMRead~24_combout )) - - .dataa(\z80_|execute_|ctl_flags_bus~7_combout ), - .datab(\z80_|execute_|fMRead~24_combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mWrite~2_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h3777; -defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_dec~3_combout & (!\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|fMRead~3_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|fMRead~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h7757; -defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h04CC; -defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|execute_|ixy_d~16_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & -// (((!\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|execute_|ixy_d~16_combout ))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|execute_|ixy_d~16_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h557F; -defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~3_combout & (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & \z80_|execute_|ctl_reg_sel_pc~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & -// (((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'h88F8; -defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~8_combout ) # (\z80_|execute_|ctl_mRead~17_combout )))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_reg_sel_pc~10_combout & (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .datab(\z80_|execute_|ctl_inc_cy~94_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout & -// !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~29_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|ir_|opcode [5]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~14_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h5455; -defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~49 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~49_combout = (!\z80_|pla_decode_|Equal35~0_combout & (((\z80_|ir_|opcode [3]) # (\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal24~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~49 .lut_mask = 16'h00FD; -defparam \z80_|execute_|pc_inc_hold~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_mRead~15_combout & (!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout )) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0A00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~28_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal33~2_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal50~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'h0515; -defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~35 ( -// Equation(s): -// \z80_|execute_|setM1~35_combout = (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~35 .lut_mask = 16'h0003; -defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~36 ( -// Equation(s): -// \z80_|execute_|setM1~36_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|execute_|ctl_mRead~9_combout & (\z80_|execute_|pc_inc_hold~28_combout & \z80_|execute_|setM1~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~28_combout ), - .datad(\z80_|execute_|setM1~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~36 .lut_mask = 16'h2000; -defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( -// Equation(s): -// \z80_|execute_|fMRead~5_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|setM1~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|setM1~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0100; -defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & (((\z80_|execute_|ctl_bus_inc_oe~29_combout & \z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'hA222; -defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'hC8C8; -defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~1_combout = (\z80_|execute_|pc_inc_hold~29_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(gnd), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'hEE00; -defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~2_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'h1113; -defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|pc_inc_hold~49_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|pc_inc_hold~49_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hF0B0; -defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~3_combout = (((\z80_|execute_|ctl_reg_sys_we~0_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout )) # (!\z80_|execute_|ctl_reg_sys_we~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~3 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_sys_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~2_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~3_combout = (\z80_|execute_|ctl_reg_sys_we_lo~2_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_reg_sys_we_lo~3_combout & \z80_|sequencer_|DFFE_M2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|execute_|ctl_reg_sys_we~3_combout ) # ((\z80_|execute_|ctl_reg_sys_we_lo~4_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~7_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hEFFF; -defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h3330; -defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_flags_bus~4_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_flags_bus~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hFF5D; -defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~34_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_inc_cy~34_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal48~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal48~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hF2F0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = (((\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'hBF3F; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_alu_oe~4_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) - - .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_alu_oe~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~4_combout = ((!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|pla_decode_|Equal3~1_combout ) # (!\z80_|pla_decode_|Equal19~1_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal19~1_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~4 .lut_mask = 16'h5777; -defparam \z80_|execute_|ctl_reg_sel_wz~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~5_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~5 .lut_mask = 16'h001F; -defparam \z80_|execute_|ctl_reg_sel_wz~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~6_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & \z80_|execute_|ctl_reg_sel_wz~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_in_hi~4_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & \z80_|execute_|ctl_reg_sel_wz~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~16_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~14_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .lut_mask = 16'h80C0; -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~16_combout & (((!\z80_|execute_|ctl_mRead~36_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'hE0F0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_al_we~13_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'h80AA; -defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|ctl_reg_sel_pc~12_combout & (\z80_|execute_|setM1~52_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ctl_mRead~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ixy_d~16_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h2022; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~0 ( -// Equation(s): -// \z80_|execute_|fMRead~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMRead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~0 .lut_mask = 16'h5D5D; -defparam \z80_|execute_|fMRead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal52~1_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h0030; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|fMRead~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h050F; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~4_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h0FAF; -defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_reg_sys_hilo~20_combout & ((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) # -// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datac(\z80_|execute_|ctl_inc_dec~4_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hD0DD; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~9_combout = (!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_ir_we~14_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_M2_ff~q )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout -// )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00C4; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~49_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h08CC; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~17_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h4455; -defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h5554; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & ((\z80_|execute_|fMRead~0_combout ) # ((!\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|pc_inc_hold~28_combout )))) - - .dataa(\z80_|execute_|fMRead~0_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h00BA; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_al_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h4404; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~18_combout = (\z80_|alu_control_|flags_cond_true~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~38_combout = ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~38_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_state_alu~14_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal6~1_combout & ((!\z80_|pla_decode_|Equal33~2_combout ) # (!\z80_|decode_state_|use_ixiy~combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~45_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~1 ( -// Equation(s): -// \z80_|execute_|fMRead~1_combout = ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~1 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|fMRead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|fMRead~1_combout ))) - - .dataa(\z80_|execute_|fMRead~1_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hF0D0; -defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~27_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_bus_inc_oe~47_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_bus_inc_oe~27_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~28_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~46_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_bus_inc_oe~45_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~37_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~39_combout & \z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~35_combout = ((\z80_|execute_|ctl_alu_oe~2_combout & ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout ) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~77_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_sw_4u~0_combout ), - .datac(\z80_|execute_|ctl_inc_cy~76_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ixy_d~9_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|pla_decode_|Equal10~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # -// (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|ctl_mWrite~2_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~33_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (\z80_|execute_|ctl_bus_inc_oe~32_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~34_combout = (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~53_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), - .datab(\z80_|execute_|ctl_inc_cy~77_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_bus_inc_oe~40_combout ) # (((\z80_|execute_|ctl_bus_inc_oe~35_combout ) # (\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~10_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # ((!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & -// (((!\z80_|execute_|ctl_alu_oe~2_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'hA0F3; -defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & \z80_|execute_|ctl_reg_sel_wz~10_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout )) - - .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ixy_d~6_combout & -// ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h2A3F; -defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|fMRead~6_combout ), - .datad(\z80_|execute_|fMRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_reg_sel_wz~11_combout & (\z80_|execute_|ctl_sw_4d~3_combout & (\z80_|execute_|ctl_sw_4d~4_combout & \z80_|execute_|ctl_sw_4d~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .datab(\z80_|execute_|ctl_sw_4d~3_combout ), - .datac(\z80_|execute_|ctl_sw_4d~4_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~45 ( -// Equation(s): -// \z80_|execute_|setM1~45_combout = (!\z80_|execute_|ctl_iorw~11_combout & (\z80_|execute_|ctl_mRead~19_combout & (!\z80_|execute_|ctl_mRead~13_combout & !\z80_|execute_|ctl_iorw~10_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_mRead~19_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0004; -defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~46 ( -// Equation(s): -// \z80_|execute_|setM1~46_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|setM1~45_combout & !\z80_|execute_|ctl_mWrite~6_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_al_we~13_combout ), - .datac(\z80_|execute_|setM1~45_combout ), - .datad(\z80_|execute_|ctl_mWrite~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~46 .lut_mask = 16'h00C0; -defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~1_combout = ((!\z80_|decode_state_|use_ixiy~combout & ((\z80_|pla_decode_|Equal50~0_combout ) # (\z80_|pla_decode_|Equal49~0_combout )))) # (!\z80_|execute_|setM1~46_combout ) - - .dataa(\z80_|pla_decode_|Equal50~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|execute_|setM1~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'h32FF; -defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_al_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_al_we~14_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~6_combout = ((\z80_|execute_|ctl_sw_4d~0_combout ) # ((\z80_|execute_|ctl_sw_4d~1_combout & \z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_sw_4d~5_combout ) - - .dataa(\z80_|execute_|ctl_sw_4d~5_combout ), - .datab(\z80_|execute_|ctl_sw_4d~1_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_sw_4d~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( -// Equation(s): -// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~4_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0A00; -defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|fMRead~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h5DFF; -defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal21~1_combout & (((\z80_|decode_state_|table_xx~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h00DF; -defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~20_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~20 .lut_mask = 16'h5010; -defparam \z80_|execute_|ctl_reg_sel_pc~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|setM1~36_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .datab(\z80_|execute_|setM1~36_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .datad(\z80_|execute_|fMRead~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hF0F7; -defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~17_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~18_combout = (((!\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'h4FFF; -defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~19_combout = ((\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (\z80_|execute_|ctl_reg_sel_pc~18_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & \z80_|execute_|ctl_reg_sel_wz~4_combout ))) - - .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h0800; -defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N18 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~combout = (!\z80_|execute_|ctl_reg_sel_wz~18_combout & (\z80_|execute_|ctl_reg_sel_pc~19_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|reg_control_|reg_sel_pc~3_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0400; -defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # ((\z80_|execute_|ctl_sw_4d~6_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|execute_|ctl_sw_4d~6_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[7]~92_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N25 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N26 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0F0F; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N27 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N9 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N29 -dffeas \z80_|resets_|DFFE_intr_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - // Location: IOIBUF_X53_Y14_N1 cycloneive_io_ibuf \KEY[0]~input ( .i(KEY[0]), @@ -15959,7 +5001,7 @@ defparam \KEY[0]~input .bus_hold = "false"; defparam \KEY[0]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X52_Y14_N4 +// Location: LCCOMB_X52_Y14_N12 cycloneive_lcell_comb reset( // Equation(s): // \reset~combout = (!\KEY[0]~input_o ) # (!\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ) @@ -15976,7 +5018,7 @@ defparam reset.lut_mask = 16'h0FFF; defparam reset.sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y13_N26 +// Location: LCCOMB_X52_Y14_N18 cycloneive_lcell_comb \z80_|resets_|x1~0 ( // Equation(s): // \z80_|resets_|x1~0_combout = !\reset~combout @@ -15993,7 +5035,7 @@ defparam \z80_|resets_|x1~0 .lut_mask = 16'h00FF; defparam \z80_|resets_|x1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N0 +// Location: LCCOMB_X26_Y32_N8 cycloneive_lcell_comb \z80_|fpga_reset~feeder ( // Equation(s): // \z80_|fpga_reset~feeder_combout = VCC @@ -16010,7 +5052,7 @@ defparam \z80_|fpga_reset~feeder .lut_mask = 16'hFFFF; defparam \z80_|fpga_reset~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N1 +// Location: FF_X26_Y32_N9 dffeas \z80_|fpga_reset ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|fpga_reset~feeder_combout ), @@ -16029,7 +5071,7 @@ defparam \z80_|fpga_reset .is_wysiwyg = "true"; defparam \z80_|fpga_reset .power_up = "low"; // synopsys translate_on -// Location: CLKCTRL_G12 +// Location: CLKCTRL_G10 cycloneive_clkctrl \z80_|fpga_reset~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\z80_|fpga_reset~q }), @@ -16042,7 +5084,7 @@ defparam \z80_|fpga_reset~clkctrl .clock_type = "global clock"; defparam \z80_|fpga_reset~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X35_Y13_N27 +// Location: FF_X52_Y14_N19 dffeas \z80_|resets_|x1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|resets_|x1~0_combout ), @@ -16061,1677 +5103,106 @@ defparam \z80_|resets_|x1 .is_wysiwyg = "true"; defparam \z80_|resets_|x1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y17_N18 -cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( +// Location: LCCOMB_X31_Y14_N0 +cycloneive_lcell_comb \z80_|resets_|x3 ( // Equation(s): -// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # -// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) +// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|resets_|clrpc_int~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), .datad(\z80_|resets_|x1~q ), .cin(gnd), - .combout(\z80_|resets_|clrpc_int~0_combout ), + .combout(\z80_|resets_|x3~combout ), .cout()); // synopsys translate_off -defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; -defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; +defparam \z80_|resets_|x3 .lut_mask = 16'hFF50; +defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y17_N19 -dffeas \z80_|resets_|clrpc_int ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|clrpc_int~0_combout ), +// Location: FF_X31_Y14_N1 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|x3~combout ), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(\z80_|fpga_reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|resets_|clrpc_int~q ), + .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; -defparam \z80_|resets_|clrpc_int .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N28 -cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( -// Equation(s): -// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_10~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|clrpc_int~q ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .datac(\z80_|resets_|DFFE_intr_ff3~q ), - .datad(\z80_|resets_|clrpc_int~q ), - .cin(gnd), - .combout(\z80_|resets_|clrpc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; -defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( -// Equation(s): -// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [7]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h5550; -defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )) # (!\z80_|execute_|ctl_al_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|execute_|ctl_al_we~14_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & (\z80_|execute_|ctl_ir_we~4_combout & -// ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_al_we~13_combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'h0EEE; -defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~8_combout = ((\z80_|execute_|ctl_al_we~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_al_we~7_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~9_combout = (((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout )) # (!\z80_|execute_|ctl_al_we~4_combout )) # (!\z80_|execute_|ctl_alu_oe~10_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~10_combout ), - .datab(\z80_|execute_|ctl_al_we~4_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~8_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_al_we~9_combout ) # (!\z80_|execute_|setM1~45_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~8_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|setM1~45_combout ), - .datad(\z80_|execute_|ctl_al_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEEAE; -defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~10_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) - - .dataa(\z80_|execute_|ctl_al_we~6_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_4d~5_combout ), - .datad(\z80_|execute_|ctl_al_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFFAF; -defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~12_combout = (\z80_|execute_|ctl_al_we~11_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|setM1~52_combout )) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_al_we~11_combout ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N5 -dffeas \z80_|address_latch_|Q[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [7]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~6_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( -// Equation(s): -// \z80_|execute_|fIOWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h3373; -defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~4_combout & (((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|fIOWrite~0_combout )) # (!\z80_|execute_|ctl_inc_dec~4_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~4_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~9_combout = ((\z80_|execute_|ctl_inc_dec~8_combout ) # ((!\z80_|execute_|ctl_reg_gp_we~0_combout & \z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_inc_dec~3_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_inc_dec~3_combout ), - .datad(\z80_|execute_|ctl_inc_dec~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hFF4F; -defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|execute_|ctl_inc_dec~9_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hF3F3; -defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout ) - - .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h55FF; -defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N1 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N3 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hCA00; -defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h1000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|gdfx_temp0[2]~36_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hA2A2; -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|alu_control_|db[2]~29_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|alu_control_|db[2]~29_combout & -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) - - .dataa(\z80_|alu_control_|db[2]~29_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .datac(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'h8CAF; -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_iy~2_combout = (\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0020; -defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|reg_control_|reg_sel_iy~2_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N15 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~42_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N29 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~37_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & \z80_|reg_file_|gdfx_temp0[2]~35_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~40_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~42_combout = ((\z80_|reg_file_|gdfx_temp0[2]~41_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[2]~42_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .datad(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|gdfx_temp0[0]~10_combout & (\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .datab(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'h8088; -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder ( +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( // Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout +// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .sum_lutc_input = "datac"; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hFF0F; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), +// Location: FF_X35_Y10_N1 +dffeas \z80_|interrupts_|nmi_armed ( + .clk(!\KEY[1]~input_o ), + .d(\z80_|interrupts_|nmi_armed~feeder_combout ), .asdata(vcc), - .clrn(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .q(\z80_|interrupts_|nmi_armed~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; +defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; +defparam \z80_|interrupts_|nmi_armed .power_up = "low"; // synopsys translate_on -// Location: FF_X29_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), +// Location: CLKCTRL_G7 +cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), + .clkselect(2'b00), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .prn(vcc)); + .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X29_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( +// Location: LCCOMB_X32_Y12_N30 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~15_combout & (\z80_|reg_file_|gdfx_temp0[0]~14_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .datad(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hA200; -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[0]~12_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .datad(\z80_|alu_control_|db[0]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N7 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~11_combout & (\z80_|reg_file_|gdfx_temp0[0]~16_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & \z80_|reg_file_|gdfx_temp0[0]~13_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hC4FF; -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|reg_file_|gdfx_temp0[0]~22_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) +// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) .dataa(gnd), - .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hCF00; -defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~72_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF33; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; // synopsys translate_on // Location: CLKCTRL_G18 @@ -17747,158 +5218,33 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add0~14 ( -// Equation(s): -// \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) -// \ula_|video_|Add0~15 = CARRY((!\ula_|video_|Add0~13 ) # (!\ula_|video_|vga_hc [7])) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~13 ), - .combout(\ula_|video_|Add0~14_combout ), - .cout(\ula_|video_|Add0~15 )); -// synopsys translate_off -defparam \ula_|video_|Add0~14 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Add0~16 ( -// Equation(s): -// \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) -// \ula_|video_|Add0~17 = CARRY((\ula_|video_|vga_hc [8] & !\ula_|video_|Add0~15 )) - - .dataa(\ula_|video_|vga_hc [8]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~15 ), - .combout(\ula_|video_|Add0~16_combout ), - .cout(\ula_|video_|Add0~17 )); -// synopsys translate_off -defparam \ula_|video_|Add0~16 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N26 -cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( -// Equation(s): -// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Equal1~0_combout ), - .datad(\ula_|video_|Add0~16_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hF000; -defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y33_N27 -dffeas \ula_|video_|vga_hc[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N20 -cycloneive_lcell_comb \ula_|video_|Add0~18 ( -// Equation(s): -// \ula_|video_|Add0~18_combout = \ula_|video_|Add0~17 $ (\ula_|video_|vga_hc [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [9]), - .cin(\ula_|video_|Add0~17 ), - .combout(\ula_|video_|Add0~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add0~18 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( -// Equation(s): -// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~18_combout ) - - .dataa(gnd), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(gnd), - .datad(\ula_|video_|Add0~18_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hCC00; -defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y33_N21 -dffeas \ula_|video_|vga_hc[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N2 +// Location: LCCOMB_X29_Y30_N8 cycloneive_lcell_comb \ula_|video_|Add0~0 ( // Equation(s): // \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) // \ula_|video_|Add0~1 = CARRY(\ula_|video_|vga_hc [0]) - .dataa(gnd), - .datab(\ula_|video_|vga_hc [0]), + .dataa(\ula_|video_|vga_hc [0]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(gnd), .combout(\ula_|video_|Add0~0_combout ), .cout(\ula_|video_|Add0~1 )); // synopsys translate_off -defparam \ula_|video_|Add0~0 .lut_mask = 16'h33CC; +defparam \ula_|video_|Add0~0 .lut_mask = 16'h55AA; defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N0 +// Location: LCCOMB_X29_Y29_N14 cycloneive_lcell_comb \ula_|video_|vga_hc~3 ( // Equation(s): -// \ula_|video_|vga_hc~3_combout = (\ula_|video_|Add0~0_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~3_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~0_combout ) .dataa(gnd), .datab(gnd), - .datac(\ula_|video_|Add0~0_combout ), - .datad(\ula_|video_|Equal1~0_combout ), + .datac(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~0_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~3_combout ), .cout()); @@ -17907,7 +5253,7 @@ defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hF000; defparam \ula_|video_|vga_hc~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y31_N1 +// Location: FF_X29_Y29_N15 dffeas \ula_|video_|vga_hc[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_hc~3_combout ), @@ -17926,7 +5272,7 @@ defparam \ula_|video_|vga_hc[0] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N4 +// Location: LCCOMB_X29_Y30_N10 cycloneive_lcell_comb \ula_|video_|Add0~2 ( // Equation(s): // \ula_|video_|Add0~2_combout = (\ula_|video_|vga_hc [1] & (!\ula_|video_|Add0~1 )) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|Add0~1 ) # (GND))) @@ -17944,7 +5290,7 @@ defparam \ula_|video_|Add0~2 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N16 +// Location: LCCOMB_X30_Y30_N22 cycloneive_lcell_comb \ula_|video_|vga_hc[1]~feeder ( // Equation(s): // \ula_|video_|vga_hc[1]~feeder_combout = \ula_|video_|Add0~2_combout @@ -17961,7 +5307,7 @@ defparam \ula_|video_|vga_hc[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|vga_hc[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N17 +// Location: FF_X30_Y30_N23 dffeas \ula_|video_|vga_hc[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_hc[1]~feeder_combout ), @@ -17980,7 +5326,7 @@ defparam \ula_|video_|vga_hc[1] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N6 +// Location: LCCOMB_X29_Y30_N12 cycloneive_lcell_comb \ula_|video_|Add0~4 ( // Equation(s): // \ula_|video_|Add0~4_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add0~3 $ (GND))) # (!\ula_|video_|vga_hc [2] & (!\ula_|video_|Add0~3 & VCC)) @@ -17998,7 +5344,7 @@ defparam \ula_|video_|Add0~4 .lut_mask = 16'hC30C; defparam \ula_|video_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X39_Y33_N23 +// Location: FF_X29_Y30_N31 dffeas \ula_|video_|vga_hc[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -18017,50 +5363,33 @@ defparam \ula_|video_|vga_hc[2] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N8 +// Location: LCCOMB_X29_Y30_N14 cycloneive_lcell_comb \ula_|video_|Add0~6 ( // Equation(s): // \ula_|video_|Add0~6_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|Add0~5 )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Add0~5 ) # (GND))) // \ula_|video_|Add0~7 = CARRY((!\ula_|video_|Add0~5 ) # (!\ula_|video_|vga_hc [3])) - .dataa(gnd), - .datab(\ula_|video_|vga_hc [3]), + .dataa(\ula_|video_|vga_hc [3]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~5 ), .combout(\ula_|video_|Add0~6_combout ), .cout(\ula_|video_|Add0~7 )); // synopsys translate_off -defparam \ula_|video_|Add0~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add0~6 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N8 -cycloneive_lcell_comb \ula_|video_|vga_hc[3]~feeder ( -// Equation(s): -// \ula_|video_|vga_hc[3]~feeder_combout = \ula_|video_|Add0~6_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Add0~6_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vga_hc[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y33_N9 +// Location: FF_X30_Y30_N11 dffeas \ula_|video_|vga_hc[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc[3]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|Add0~6_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18071,7 +5400,7 @@ defparam \ula_|video_|vga_hc[3] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N10 +// Location: LCCOMB_X29_Y30_N16 cycloneive_lcell_comb \ula_|video_|Add0~8 ( // Equation(s): // \ula_|video_|Add0~8_combout = (\ula_|video_|vga_hc [4] & (\ula_|video_|Add0~7 $ (GND))) # (!\ula_|video_|vga_hc [4] & (!\ula_|video_|Add0~7 & VCC)) @@ -18089,7 +5418,7 @@ defparam \ula_|video_|Add0~8 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X39_Y33_N31 +// Location: FF_X29_Y30_N7 dffeas \ula_|video_|vga_hc[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -18108,101 +5437,50 @@ defparam \ula_|video_|vga_hc[4] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N18 -cycloneive_lcell_comb \ula_|video_|Equal0~0 ( -// Equation(s): -// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N30 -cycloneive_lcell_comb \ula_|video_|Equal0~1 ( -// Equation(s): -// \ula_|video_|Equal0~1_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [7] & (!\ula_|video_|vga_hc [4] & \ula_|video_|Equal0~0_combout ))) - - .dataa(\ula_|video_|vga_hc [5]), - .datab(\ula_|video_|vga_hc [7]), - .datac(\ula_|video_|vga_hc [4]), - .datad(\ula_|video_|Equal0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0200; -defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Equal1~0 ( -// Equation(s): -// \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|Equal0~1_combout )) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9]) - - .dataa(\ula_|video_|vga_hc [9]), - .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal1~0 .lut_mask = 16'hF7FF; -defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N12 +// Location: LCCOMB_X29_Y30_N18 cycloneive_lcell_comb \ula_|video_|Add0~10 ( // Equation(s): // \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) // \ula_|video_|Add0~11 = CARRY((!\ula_|video_|Add0~9 ) # (!\ula_|video_|vga_hc [5])) - .dataa(\ula_|video_|vga_hc [5]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [5]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~9 ), .combout(\ula_|video_|Add0~10_combout ), .cout(\ula_|video_|Add0~11 )); // synopsys translate_off -defparam \ula_|video_|Add0~10 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add0~10 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N0 +// Location: LCCOMB_X29_Y30_N30 cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( // Equation(s): -// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~10_combout ) +// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Add0~10_combout & \ula_|video_|Equal1~0_combout ) .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Equal1~0_combout ), - .datad(\ula_|video_|Add0~10_combout ), + .datab(\ula_|video_|Add0~10_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hF000; +defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hCC00; defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y33_N1 +// Location: FF_X29_Y30_N1 dffeas \ula_|video_|vga_hc[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~0_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|vga_hc~0_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18213,25 +5491,25 @@ defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N14 +// Location: LCCOMB_X29_Y30_N20 cycloneive_lcell_comb \ula_|video_|Add0~12 ( // Equation(s): // \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) // \ula_|video_|Add0~13 = CARRY((\ula_|video_|vga_hc [6] & !\ula_|video_|Add0~11 )) - .dataa(\ula_|video_|vga_hc [6]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [6]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~11 ), .combout(\ula_|video_|Add0~12_combout ), .cout(\ula_|video_|Add0~13 )); // synopsys translate_off -defparam \ula_|video_|Add0~12 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add0~12 .lut_mask = 16'hC30C; defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X39_Y33_N29 +// Location: FF_X29_Y30_N29 dffeas \ula_|video_|vga_hc[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -18250,7 +5528,25 @@ defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X39_Y33_N25 +// Location: LCCOMB_X29_Y30_N22 +cycloneive_lcell_comb \ula_|video_|Add0~14 ( +// Equation(s): +// \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) +// \ula_|video_|Add0~15 = CARRY((!\ula_|video_|Add0~13 ) # (!\ula_|video_|vga_hc [7])) + + .dataa(\ula_|video_|vga_hc [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~13 ), + .combout(\ula_|video_|Add0~14_combout ), + .cout(\ula_|video_|Add0~15 )); +// synopsys translate_off +defparam \ula_|video_|Add0~14 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y30_N3 dffeas \ula_|video_|vga_hc[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -18269,578 +5565,218 @@ defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N0 +// Location: LCCOMB_X30_Y29_N12 +cycloneive_lcell_comb \ula_|video_|Equal0~0 ( +// Equation(s): +// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [0] & (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [1]))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N26 +cycloneive_lcell_comb \ula_|video_|Equal0~1 ( +// Equation(s): +// \ula_|video_|Equal0~1_combout = (!\ula_|video_|vga_hc [7] & (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [4] & \ula_|video_|Equal0~0_combout ))) + + .dataa(\ula_|video_|vga_hc [7]), + .datab(\ula_|video_|vga_hc [5]), + .datac(\ula_|video_|vga_hc [4]), + .datad(\ula_|video_|Equal0~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0400; +defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N24 +cycloneive_lcell_comb \ula_|video_|Add0~16 ( +// Equation(s): +// \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) +// \ula_|video_|Add0~17 = CARRY((\ula_|video_|vga_hc [8] & !\ula_|video_|Add0~15 )) + + .dataa(\ula_|video_|vga_hc [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~15 ), + .combout(\ula_|video_|Add0~16_combout ), + .cout(\ula_|video_|Add0~17 )); +// synopsys translate_off +defparam \ula_|video_|Add0~16 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N28 +cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( +// Equation(s): +// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Add0~16_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Add0~16_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y30_N17 +dffeas \ula_|video_|vga_hc[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~2_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N26 +cycloneive_lcell_comb \ula_|video_|Add0~18 ( +// Equation(s): +// \ula_|video_|Add0~18_combout = \ula_|video_|vga_hc [9] $ (\ula_|video_|Add0~17 ) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [9]), + .datac(gnd), + .datad(gnd), + .cin(\ula_|video_|Add0~17 ), + .combout(\ula_|video_|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add0~18 .lut_mask = 16'h3C3C; +defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N2 +cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( +// Equation(s): +// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Add0~18_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Add0~18_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y30_N5 +dffeas \ula_|video_|vga_hc[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~1_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N0 +cycloneive_lcell_comb \ula_|video_|Equal1~0 ( +// Equation(s): +// \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9])) # (!\ula_|video_|Equal0~1_combout ) + + .dataa(\ula_|video_|Equal0~1_combout ), + .datab(\ula_|video_|vga_hc [9]), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [8]), + .cin(gnd), + .combout(\ula_|video_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal1~0 .lut_mask = 16'hF7FF; +defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N0 cycloneive_lcell_comb \ula_|video_|Add1~0 ( // Equation(s): // \ula_|video_|Add1~0_combout = \ula_|video_|vga_vc [0] $ (VCC) // \ula_|video_|Add1~1 = CARRY(\ula_|video_|vga_vc [0]) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [0]), + .dataa(\ula_|video_|vga_vc [0]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(gnd), .combout(\ula_|video_|Add1~0_combout ), .cout(\ula_|video_|Add1~1 )); // synopsys translate_off -defparam \ula_|video_|Add1~0 .lut_mask = 16'h33CC; +defparam \ula_|video_|Add1~0 .lut_mask = 16'h55AA; defparam \ula_|video_|Add1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N2 +// Location: LCCOMB_X32_Y29_N2 cycloneive_lcell_comb \ula_|video_|Add1~2 ( // Equation(s): // \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) // \ula_|video_|Add1~3 = CARRY((!\ula_|video_|Add1~1 ) # (!\ula_|video_|vga_vc [1])) - .dataa(\ula_|video_|vga_vc [1]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [1]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~1 ), .combout(\ula_|video_|Add1~2_combout ), .cout(\ula_|video_|Add1~3 )); // synopsys translate_off -defparam \ula_|video_|Add1~2 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add1~2 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Add1~4 ( -// Equation(s): -// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) -// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) - - .dataa(\ula_|video_|vga_vc [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~3 ), - .combout(\ula_|video_|Add1~4_combout ), - .cout(\ula_|video_|Add1~5 )); -// synopsys translate_off -defparam \ula_|video_|Add1~4 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N12 -cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( -// Equation(s): -// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [2]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~4_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~4_combout ), - .datac(\ula_|video_|vga_vc [2]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N13 -dffeas \ula_|video_|vga_vc[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[2]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N6 -cycloneive_lcell_comb \ula_|video_|Add1~6 ( -// Equation(s): -// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) -// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~5 ), - .combout(\ula_|video_|Add1~6_combout ), - .cout(\ula_|video_|Add1~7 )); -// synopsys translate_off -defparam \ula_|video_|Add1~6 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( -// Equation(s): -// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) - - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|Add1~6_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h5140; -defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N3 -dffeas \ula_|video_|vga_vc[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_vc[3]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N8 -cycloneive_lcell_comb \ula_|video_|Add1~8 ( -// Equation(s): -// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) -// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~7 ), - .combout(\ula_|video_|Add1~8_combout ), - .cout(\ula_|video_|Add1~9 )); -// synopsys translate_off -defparam \ula_|video_|Add1~8 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( -// Equation(s): -// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~8_combout ), - .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[4]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N21 -dffeas \ula_|video_|vga_vc[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[4]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N10 -cycloneive_lcell_comb \ula_|video_|Add1~10 ( -// Equation(s): -// \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) -// \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~9 ), - .combout(\ula_|video_|Add1~10_combout ), - .cout(\ula_|video_|Add1~11 )); -// synopsys translate_off -defparam \ula_|video_|Add1~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N22 -cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( -// Equation(s): -// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [5])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~10_combout ))))) - - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(\ula_|video_|vga_vc [5]), - .datad(\ula_|video_|Add1~10_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[5]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h5140; -defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N17 -dffeas \ula_|video_|vga_vc[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_vc[5]~8_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N12 -cycloneive_lcell_comb \ula_|video_|Add1~12 ( -// Equation(s): -// \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) -// \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [6]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~11 ), - .combout(\ula_|video_|Add1~12_combout ), - .cout(\ula_|video_|Add1~13 )); -// synopsys translate_off -defparam \ula_|video_|Add1~12 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N6 -cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( -// Equation(s): -// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [6]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~12_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~12_combout ), - .datac(\ula_|video_|vga_vc [6]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[6]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N7 -dffeas \ula_|video_|vga_vc[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[6]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Add1~14 ( -// Equation(s): -// \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) -// \ula_|video_|Add1~15 = CARRY((!\ula_|video_|Add1~13 ) # (!\ula_|video_|vga_vc [7])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~13 ), - .combout(\ula_|video_|Add1~14_combout ), - .cout(\ula_|video_|Add1~15 )); -// synopsys translate_off -defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N14 -cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( -// Equation(s): -// \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~14_combout ), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[7]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N15 -dffeas \ula_|video_|vga_vc[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[7]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add1~16 ( -// Equation(s): -// \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) -// \ula_|video_|Add1~17 = CARRY((\ula_|video_|vga_vc [8] & !\ula_|video_|Add1~15 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [8]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~15 ), - .combout(\ula_|video_|Add1~16_combout ), - .cout(\ula_|video_|Add1~17 )); -// synopsys translate_off -defparam \ula_|video_|Add1~16 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N24 -cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( -// Equation(s): -// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~16_combout ), - .datac(\ula_|video_|vga_vc [8]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[8]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N25 -dffeas \ula_|video_|vga_vc[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[8]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Add1~18 ( -// Equation(s): -// \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_vc [9]), - .cin(\ula_|video_|Add1~17 ), - .combout(\ula_|video_|Add1~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N10 -cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( -// Equation(s): -// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [9]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~18_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~18_combout ), - .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[9]~9_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N11 -dffeas \ula_|video_|vga_vc[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[9]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Equal2~0 ( -// Equation(s): -// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [4] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [4]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [8]), - .cin(gnd), - .combout(\ula_|video_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y33_N30 -cycloneive_lcell_comb \ula_|video_|Equal3~0 ( -// Equation(s): -// \ula_|video_|Equal3~0_combout = (\ula_|video_|vga_vc [3] & (\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [1] & \ula_|video_|vga_vc [0]))) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal3~0 .lut_mask = 16'h0800; -defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Equal3~1 ( -// Equation(s): -// \ula_|video_|Equal3~1_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal2~0_combout & \ula_|video_|Equal3~0_combout ))) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|Equal2~0_combout ), - .datad(\ula_|video_|Equal3~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal3~1 .lut_mask = 16'h4000; -defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N28 -cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( -// Equation(s): -// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [0]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~0_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~0_combout ), - .datac(\ula_|video_|vga_vc [0]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N29 -dffeas \ula_|video_|vga_vc[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[0]~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N22 +// Location: LCCOMB_X32_Y30_N30 cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( // Equation(s): -// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [1]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~2_combout )))) +// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [1])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~2_combout ))))) .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~2_combout ), + .datab(\ula_|video_|Equal3~1_combout ), .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|Equal3~1_combout ), + .datad(\ula_|video_|Add1~2_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h3120; defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y33_N23 +// Location: FF_X32_Y30_N31 dffeas \ula_|video_|vga_vc[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[1]~1_combout ), @@ -18859,6 +5795,558 @@ defparam \ula_|video_|vga_vc[1] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[1] .power_up = "low"; // synopsys translate_on +// Location: LCCOMB_X32_Y29_N4 +cycloneive_lcell_comb \ula_|video_|Add1~4 ( +// Equation(s): +// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) +// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~3 ), + .combout(\ula_|video_|Add1~4_combout ), + .cout(\ula_|video_|Add1~5 )); +// synopsys translate_off +defparam \ula_|video_|Add1~4 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N20 +cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( +// Equation(s): +// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [2]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~4_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~4_combout ), + .datac(\ula_|video_|vga_vc [2]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y30_N21 +dffeas \ula_|video_|vga_vc[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[2]~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N6 +cycloneive_lcell_comb \ula_|video_|Add1~6 ( +// Equation(s): +// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) +// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~5 ), + .combout(\ula_|video_|Add1~6_combout ), + .cout(\ula_|video_|Add1~7 )); +// synopsys translate_off +defparam \ula_|video_|Add1~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N26 +cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( +// Equation(s): +// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|Add1~6_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y30_N27 +dffeas \ula_|video_|vga_vc[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[3]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N8 +cycloneive_lcell_comb \ula_|video_|Add1~8 ( +// Equation(s): +// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) +// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~7 ), + .combout(\ula_|video_|Add1~8_combout ), + .cout(\ula_|video_|Add1~9 )); +// synopsys translate_off +defparam \ula_|video_|Add1~8 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N22 +cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( +// Equation(s): +// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~8_combout ), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y30_N23 +dffeas \ula_|video_|vga_vc[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[4]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N10 +cycloneive_lcell_comb \ula_|video_|Add1~10 ( +// Equation(s): +// \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) +// \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~9 ), + .combout(\ula_|video_|Add1~10_combout ), + .cout(\ula_|video_|Add1~11 )); +// synopsys translate_off +defparam \ula_|video_|Add1~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N8 +cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( +// Equation(s): +// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [5])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~10_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Add1~10_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[5]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y30_N9 +dffeas \ula_|video_|vga_vc[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[5]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N12 +cycloneive_lcell_comb \ula_|video_|Add1~12 ( +// Equation(s): +// \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) +// \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~11 ), + .combout(\ula_|video_|Add1~12_combout ), + .cout(\ula_|video_|Add1~13 )); +// synopsys translate_off +defparam \ula_|video_|Add1~12 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N16 +cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( +// Equation(s): +// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [6])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~12_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [6]), + .datad(\ula_|video_|Add1~12_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[6]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y30_N17 +dffeas \ula_|video_|vga_vc[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[6]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N14 +cycloneive_lcell_comb \ula_|video_|Add1~14 ( +// Equation(s): +// \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) +// \ula_|video_|Add1~15 = CARRY((!\ula_|video_|Add1~13 ) # (!\ula_|video_|vga_vc [7])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [7]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~13 ), + .combout(\ula_|video_|Add1~14_combout ), + .cout(\ula_|video_|Add1~15 )); +// synopsys translate_off +defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N22 +cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( +// Equation(s): +// \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~14_combout ), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[7]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y30_N23 +dffeas \ula_|video_|vga_vc[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[7]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N16 +cycloneive_lcell_comb \ula_|video_|Add1~16 ( +// Equation(s): +// \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) +// \ula_|video_|Add1~17 = CARRY((\ula_|video_|vga_vc [8] & !\ula_|video_|Add1~15 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [8]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~15 ), + .combout(\ula_|video_|Add1~16_combout ), + .cout(\ula_|video_|Add1~17 )); +// synopsys translate_off +defparam \ula_|video_|Add1~16 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N20 +cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( +// Equation(s): +// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~16_combout ), + .datac(\ula_|video_|vga_vc [8]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[8]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y30_N21 +dffeas \ula_|video_|vga_vc[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[8]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N18 +cycloneive_lcell_comb \ula_|video_|Add1~18 ( +// Equation(s): +// \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc [9]), + .cin(\ula_|video_|Add1~17 ), + .combout(\ula_|video_|Add1~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N8 +cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( +// Equation(s): +// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [9])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~18_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [9]), + .datad(\ula_|video_|Add1~18_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y30_N9 +dffeas \ula_|video_|vga_vc[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[9]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N10 +cycloneive_lcell_comb \ula_|video_|Equal3~0 ( +// Equation(s): +// \ula_|video_|Equal3~0_combout = (!\ula_|video_|vga_vc [1] & (\ula_|video_|vga_vc [2] & (\ula_|video_|vga_vc [3] & \ula_|video_|vga_vc [0]))) + + .dataa(\ula_|video_|vga_vc [1]), + .datab(\ula_|video_|vga_vc [2]), + .datac(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|vga_vc [0]), + .cin(gnd), + .combout(\ula_|video_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal3~0 .lut_mask = 16'h4000; +defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N30 +cycloneive_lcell_comb \ula_|video_|Equal2~0 ( +// Equation(s): +// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [4]))) + + .dataa(\ula_|video_|vga_vc [8]), + .datab(\ula_|video_|vga_vc [6]), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|vga_vc [4]), + .cin(gnd), + .combout(\ula_|video_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N16 +cycloneive_lcell_comb \ula_|video_|Equal3~1 ( +// Equation(s): +// \ula_|video_|Equal3~1_combout = (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal3~0_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) + + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|Equal3~0_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Equal2~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal3~1 .lut_mask = 16'h0800; +defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N24 +cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( +// Equation(s): +// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [0])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~0_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [0]), + .datad(\ula_|video_|Add1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y30_N25 +dffeas \ula_|video_|vga_vc[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N18 +cycloneive_lcell_comb \ula_|video_|Equal2~1 ( +// Equation(s): +// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [0] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & !\ula_|video_|vga_vc [9]))) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [2]), + .datac(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|vga_vc [9]), + .cin(gnd), + .combout(\ula_|video_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal2~1 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N12 +cycloneive_lcell_comb \ula_|video_|Equal2~2 ( +// Equation(s): +// \ula_|video_|Equal2~2_combout = (\ula_|video_|Equal2~1_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout )) + + .dataa(\ula_|video_|Equal2~1_combout ), + .datab(gnd), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Equal2~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal2~2 .lut_mask = 16'h0A00; +defparam \ula_|video_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: IOIBUF_X27_Y0_N15 cycloneive_io_ibuf \SW[1]~input ( .i(SW[1]), @@ -18869,15 +6357,15 @@ defparam \SW[1]~input .bus_hold = "false"; defparam \SW[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X34_Y33_N30 +// Location: LCCOMB_X31_Y27_N2 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_vc [1] & (!\SW[1]~input_o & !\ula_|video_|vga_hc [9]))) +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_vc [1] & (!\ula_|video_|vga_hc [9] & !\SW[1]~input_o ))) .dataa(\ula_|video_|vga_hc [8]), .datab(\ula_|video_|vga_vc [1]), - .datac(\SW[1]~input_o ), - .datad(\ula_|video_|vga_hc [9]), + .datac(\ula_|video_|vga_hc [9]), + .datad(\SW[1]~input_o ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), .cout()); @@ -18886,18144 +6374,249 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .lut_mask = 16'h0001; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( +// Location: LCCOMB_X30_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( // Equation(s): -// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal79~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N16 -cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( -// Equation(s): -// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|interrupts_|DFFE_instIFF2~q -// ))))) # (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal79~0_combout ), - .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hB8F0; -defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N28 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|interrupts_|DFFE_inst44~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h7733; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G16 -cycloneive_clkctrl \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: FF_X35_Y17_N17 -dffeas \z80_|interrupts_|DFFE_instIFF2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|DFFE_instIFF2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N2 -cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( -// Equation(s): -// \z80_|interrupts_|iff1~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|interrupts_|iff1~q ), - .datac(\z80_|pla_decode_|Equal79~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|interrupts_|iff1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hEC4C; -defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N18 -cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( -// Equation(s): -// \z80_|interrupts_|iff1~1_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|pla_decode_|Equal38~2_combout & ((\z80_|interrupts_|iff1~0_combout ))))) # -// (!\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|interrupts_|iff1~0_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|interrupts_|DFFE_instIFF2~q ), - .datac(\z80_|pla_decode_|Equal38~2_combout ), - .datad(\z80_|interrupts_|iff1~0_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|iff1~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hDF80; -defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N12 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|interrupts_|DFFE_inst44~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFF3; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N19 -dffeas \z80_|interrupts_|iff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|iff1~1_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|iff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|iff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Equal2~1 ( -// Equation(s): -// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [3] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [0]))) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal2~1 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Equal2~2 ( -// Equation(s): -// \ula_|video_|Equal2~2_combout = (\ula_|video_|Equal2~1_combout & (\ula_|video_|Equal2~0_combout & !\ula_|video_|vga_vc [5])) - - .dataa(gnd), - .datab(\ula_|video_|Equal2~1_combout ), - .datac(\ula_|video_|Equal2~0_combout ), - .datad(\ula_|video_|vga_vc [5]), - .cin(gnd), - .combout(\ula_|video_|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal2~2 .lut_mask = 16'h00C0; -defparam \ula_|video_|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y31_N28 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (!\ula_|video_|vga_hc [7] & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & (\z80_|interrupts_|iff1~q & \ula_|video_|Equal2~2_combout ))) - - .dataa(\ula_|video_|vga_hc [7]), - .datab(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), - .datac(\z80_|interrupts_|iff1~q ), - .datad(\ula_|video_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h4000; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y31_N29 -dffeas \z80_|interrupts_|int_armed ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|int_armed~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; -defparam \z80_|interrupts_|int_armed .power_up = "low"; -// synopsys translate_on - -// Location: FF_X32_Y15_N11 -dffeas \z80_|interrupts_|DFFE_inst44 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|interrupts_|int_armed~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|interrupts_|test1~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|DFFE_inst44~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~38 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~38_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|decode_state_|in_halt~q ) # (\z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .datab(gnd), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~38 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|pc_inc_hold~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~91 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~91_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~91 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~45 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~45_combout = (\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) # (!\z80_|pla_decode_|Equal19~0_combout & -// (((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~45 .lut_mask = 16'hF888; -defparam \z80_|execute_|pc_inc_hold~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~44 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~44_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((!\z80_|execute_|pc_inc_hold~49_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|pc_inc_hold~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~44 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|pc_inc_hold~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~46 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~46_combout = (\z80_|execute_|pc_inc_hold~45_combout ) # ((\z80_|execute_|pc_inc_hold~44_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~49_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~45_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|pc_inc_hold~44_combout ), - .datad(\z80_|execute_|pc_inc_hold~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~46 .lut_mask = 16'hFAFE; -defparam \z80_|execute_|pc_inc_hold~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~37 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~37_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|pc_inc_hold~29_combout ) # ((\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & -// (\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~37 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|pc_inc_hold~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~50 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~50_combout = (\z80_|execute_|pc_inc_hold~37_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|execute_|pc_inc_hold~37_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~50 .lut_mask = 16'hECCC; -defparam \z80_|execute_|pc_inc_hold~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~33_combout = (\z80_|execute_|ctl_mRead~10_combout & (((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|pla_decode_|Equal6~1_combout & -// ((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~2_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|pc_inc_hold~28_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|execute_|pc_inc_hold~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hECEE; -defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|execute_|ctl_mRead~15_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hEEA0; -defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|execute_|pc_inc_hold~33_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # ((\z80_|execute_|pc_inc_hold~31_combout ) # (\z80_|execute_|pc_inc_hold~32_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~33_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|pc_inc_hold~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~51 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~51_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ixy_d~15_combout ), .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~51_combout ), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~51 .lut_mask = 16'h57FF; -defparam \z80_|execute_|pc_inc_hold~51 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( +// Location: LCCOMB_X37_Y6_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) +// \z80_|execute_|ctl_mWrite~4_combout = (\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~30_combout ), + .combout(\z80_|execute_|ctl_mWrite~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~52 ( +// Location: LCCOMB_X36_Y6_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal0~0 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~52_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~52 .lut_mask = 16'hA800; -defparam \z80_|execute_|pc_inc_hold~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~35_combout = (!\z80_|execute_|pc_inc_hold~34_combout & (\z80_|execute_|pc_inc_hold~51_combout & (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~52_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~34_combout ), - .datab(\z80_|execute_|pc_inc_hold~51_combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|pc_inc_hold~52_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'h0040; -defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~36_combout = ((\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|execute_|pc_inc_hold~35_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hCF8F; -defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~44_combout = (((!\z80_|pla_decode_|Equal21~0_combout & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ixy_d~10_combout )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~45_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_inc_cy~44_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~50_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_inc_cy~44_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~43 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~43_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~43 .lut_mask = 16'hC080; -defparam \z80_|execute_|pc_inc_hold~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~71_combout = (\z80_|execute_|ctl_inc_cy~91_combout & (!\z80_|execute_|pc_inc_hold~46_combout & (\z80_|execute_|ctl_inc_cy~45_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~91_combout ), - .datab(\z80_|execute_|pc_inc_hold~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~45_combout ), - .datad(\z80_|execute_|pc_inc_hold~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~73_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~72_combout & \z80_|execute_|ctl_inc_cy~71_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_inc_cy~72_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~71_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_mWrite~16_combout & ((\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'h8C00; -defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~53 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~53_combout = (\z80_|pla_decode_|Equal11~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~53 .lut_mask = 16'hE000; -defparam \z80_|execute_|pc_inc_hold~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~39 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~39_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~53_combout & (\z80_|execute_|pc_inc_hold~35_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~50_combout ), - .datab(\z80_|execute_|pc_inc_hold~53_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~39 .lut_mask = 16'h0010; -defparam \z80_|execute_|pc_inc_hold~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~47 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~47_combout = (\z80_|execute_|pc_inc_hold~46_combout ) # ((\z80_|execute_|pc_inc_hold~43_combout ) # ((!\z80_|execute_|ctl_inc_cy~44_combout ) # (!\z80_|execute_|pc_inc_hold~39_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~46_combout ), - .datab(\z80_|execute_|pc_inc_hold~43_combout ), - .datac(\z80_|execute_|pc_inc_hold~39_combout ), - .datad(\z80_|execute_|ctl_inc_cy~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~47 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|pc_inc_hold~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~74_combout = (((!\z80_|execute_|ctl_inc_cy~40_combout ) # (!\z80_|execute_|ctl_inc_cy~34_combout )) # (!\z80_|execute_|ctl_inc_cy~35_combout )) # (!\z80_|execute_|ctl_inc_cy~43_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~43_combout ), - .datab(\z80_|execute_|ctl_inc_cy~35_combout ), - .datac(\z80_|execute_|ctl_inc_cy~34_combout ), - .datad(\z80_|execute_|ctl_inc_cy~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~78_combout = ((\z80_|execute_|ctl_inc_cy~74_combout ) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~39_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~39_combout ), - .datac(\z80_|execute_|ctl_inc_cy~77_combout ), - .datad(\z80_|execute_|ctl_inc_cy~74_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (((!\z80_|execute_|pc_inc_hold~47_combout & \z80_|execute_|ctl_inc_cy~91_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~47_combout ), - .datab(\z80_|execute_|ctl_inc_cy~78_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~91_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'h4C0C; -defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~45_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|pc_inc_hold~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal19~1_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hA800; -defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~82_combout = (\z80_|execute_|ctl_inc_cy~81_combout ) # ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~81_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|pc_inc_hold~47_combout & (!\z80_|execute_|pc_inc_hold~38_combout & ((\z80_|execute_|ctl_inc_cy~82_combout ) # (!\z80_|execute_|ctl_inc_cy~38_combout )))) # (!\z80_|execute_|pc_inc_hold~47_combout -// & ((\z80_|execute_|ctl_inc_cy~82_combout ) # ((!\z80_|execute_|ctl_inc_cy~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~47_combout ), - .datab(\z80_|execute_|ctl_inc_cy~82_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'h4C5F; -defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~84_combout = (\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~79_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|execute_|ctl_inc_cy~83_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~42 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~42_combout = ((\z80_|execute_|pc_inc_hold~34_combout ) # (\z80_|execute_|pc_inc_hold~52_combout )) # (!\z80_|execute_|pc_inc_hold~30_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|pc_inc_hold~52_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~42 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|pc_inc_hold~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~90 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~90_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~8_combout ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~90 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~41 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~41_combout = (\z80_|execute_|pc_inc_hold~31_combout ) # ((\z80_|execute_|pc_inc_hold~32_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~31_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|execute_|pc_inc_hold~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~41 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|pc_inc_hold~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~66_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'h0004; -defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~66_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~20_combout & !\z80_|execute_|pc_inc_hold~31_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|ctl_inc_cy~66_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hAA02; -defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~67_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|pc_inc_hold~41_combout & \z80_|execute_|ctl_mRead~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|pc_inc_hold~41_combout ), - .datac(\z80_|execute_|ctl_inc_cy~67_combout ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hF2F0; -defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~64_combout = (!\z80_|execute_|pc_inc_hold~31_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|pc_inc_hold~34_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_sw_4u~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h0C08; -defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~65_combout = (\z80_|execute_|ctl_inc_cy~63_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((\z80_|execute_|ctl_inc_cy~64_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|execute_|ctl_inc_cy~64_combout ), - .datad(\z80_|execute_|ctl_inc_cy~63_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hFFC4; -defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|ctl_inc_cy~68_combout ) # ((\z80_|execute_|ctl_inc_cy~65_combout ) # ((!\z80_|execute_|pc_inc_hold~42_combout & !\z80_|execute_|ctl_inc_cy~90_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~42_combout ), - .datab(\z80_|execute_|ctl_inc_cy~90_combout ), - .datac(\z80_|execute_|ctl_inc_cy~68_combout ), - .datad(\z80_|execute_|ctl_inc_cy~65_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~49_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_inc_cy~92_combout ) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_inc_cy~92_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~50_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) # (!\z80_|execute_|ixy_d~9_combout & -// (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_mRead~11_combout )) # (!\z80_|execute_|ctl_inc_cy~94_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|execute_|ctl_inc_cy~94_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_inc_cy~51_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~51_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~36_combout = ((!\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_mWrite~4_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~36_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_sw_2u~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~54_combout = ((\z80_|execute_|ctl_inc_cy~49_combout ) # ((\z80_|execute_|ctl_inc_cy~52_combout ) # (!\z80_|execute_|ctl_inc_cy~37_combout ))) # (!\z80_|execute_|ctl_inc_cy~53_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), - .datab(\z80_|execute_|ctl_inc_cy~49_combout ), - .datac(\z80_|execute_|ctl_inc_cy~52_combout ), - .datad(\z80_|execute_|ctl_inc_cy~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~41_combout = (!\z80_|execute_|ctl_mRead~17_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'h0045; -defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~58_combout = (\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_inc_cy~41_combout )) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~41_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'hEEFF; -defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout ) # ((\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & -// ((\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~56_combout = (((!\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|fMRead~3_combout ) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~89 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~89_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~89 .lut_mask = 16'hA020; -defparam \z80_|execute_|ctl_inc_cy~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_inc_cy~56_combout ) # (\z80_|execute_|ctl_inc_cy~89_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ctl_inc_cy~55_combout ), - .datac(\z80_|execute_|ctl_inc_cy~56_combout ), - .datad(\z80_|execute_|ctl_inc_cy~89_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_inc_cy~57_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~58_combout ) # (!\z80_|execute_|fMRead~5_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_inc_cy~58_combout ), - .datac(\z80_|execute_|fMRead~5_combout ), - .datad(\z80_|execute_|ctl_inc_cy~57_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'hFF8A; -defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~60_combout = (\z80_|execute_|pc_inc_hold~38_combout & (\z80_|execute_|pc_inc_hold~35_combout & (\z80_|execute_|ctl_inc_cy~54_combout ))) # (!\z80_|execute_|pc_inc_hold~38_combout & (((\z80_|execute_|ctl_inc_cy~54_combout ) # -// (\z80_|execute_|ctl_inc_cy~59_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|pc_inc_hold~35_combout ), - .datac(\z80_|execute_|ctl_inc_cy~54_combout ), - .datad(\z80_|execute_|ctl_inc_cy~59_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'hD5D0; -defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|pc_inc_hold~50_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|pc_inc_hold~50_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~88_combout = (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ) # ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~47_combout ) # ((\z80_|execute_|ctl_inc_cy~88_combout & ((\z80_|execute_|pc_inc_hold~39_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~39_combout ), - .datab(\z80_|execute_|ctl_inc_cy~47_combout ), - .datac(\z80_|execute_|ctl_inc_cy~88_combout ), - .datad(\z80_|execute_|pc_inc_hold~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'hECFC; -defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~40 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~40_combout = (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~34_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~40 .lut_mask = 16'h0C0C; -defparam \z80_|execute_|pc_inc_hold~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~61_combout = (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h3200; -defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~62_combout = (\z80_|execute_|ctl_inc_cy~61_combout ) # ((!\z80_|execute_|ctl_inc_cy~42_combout & ((\z80_|execute_|pc_inc_hold~40_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|pc_inc_hold~40_combout ), - .datac(\z80_|execute_|ctl_inc_cy~61_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hF0FD; -defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~69_combout ) # ((\z80_|execute_|ctl_inc_cy~60_combout ) # ((\z80_|execute_|ctl_inc_cy~48_combout ) # (\z80_|execute_|ctl_inc_cy~62_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), - .datab(\z80_|execute_|ctl_inc_cy~60_combout ), - .datac(\z80_|execute_|ctl_inc_cy~48_combout ), - .datad(\z80_|execute_|ctl_inc_cy~62_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~85_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~84_combout ) # (\z80_|execute_|ctl_inc_cy~70_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), - .datab(\z80_|execute_|ctl_inc_cy~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~84_combout ), - .datad(\z80_|execute_|ctl_inc_cy~70_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (\z80_|execute_|ctl_inc_cy~85_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_cy~85_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hAF2F; -defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( -// Equation(s): -// \z80_|address_latch_|abusz [0] = (\z80_|reg_file_|db_lo_as[0]~3_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [0]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|Q[0]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[0]~feeder_combout = \z80_|address_latch_|abusz [0] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [0]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N23 -dffeas \z80_|address_latch_|Q[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[0]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X31_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[1]~32_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .datad(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_cy~85_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h6A6A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hAF2F; -defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( -// Equation(s): -// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [1]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h3300; -defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N19 -dffeas \z80_|address_latch_|Q[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [1]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout = \z80_|address_latch_|Q [1] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|address_latch_|Q [1]), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .lut_mask = 16'h0F87; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & (\z80_|execute_|ctl_inc_cy~85_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hF575; -defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( -// Equation(s): -// \z80_|address_latch_|abusz [2] = (\z80_|reg_file_|db_lo_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [2]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h00AA; -defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N14 -cycloneive_lcell_comb \z80_|address_latch_|Q[2]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[2]~feeder_combout = \z80_|address_latch_|abusz [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [2]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N15 -dffeas \z80_|address_latch_|Q[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[2]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|address_latch_|Q [2] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|address_latch_|Q [2]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h40BF; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~86_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), - .datab(\z80_|execute_|ctl_inc_cy~79_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|execute_|ctl_inc_cy~83_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~86_combout ) # -// (\z80_|execute_|ctl_inc_cy~70_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datab(\z80_|execute_|ctl_inc_cy~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~86_combout ), - .datad(\z80_|execute_|ctl_inc_cy~70_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hAAA8; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~11_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout )) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout = (\z80_|execute_|ctl_inc_cy~85_combout & ((\z80_|address_latch_|Q [1] & (!\z80_|execute_|ctl_inc_dec~11_combout & \z80_|address_latch_|Q [0])) # (!\z80_|address_latch_|Q -// [1] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [0])))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_cy~85_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .lut_mask = 16'h2400; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout -// ))) - - .dataa(gnd), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h3FC0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N11 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N5 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'h3F3B; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~29_combout ) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|setM1~29_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_al_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'hB3F3; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & !\z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ) # ((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hF7F5; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = ((\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|execute_|setM1~46_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datad(\z80_|execute_|setM1~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'h5DDD; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ) # (!\z80_|execute_|ctl_reg_gp_we~2_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~40 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[3]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~41 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[3]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hB3FF; -defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~12_combout = (\z80_|execute_|ctl_reg_in_hi~11_combout ) # (((!\z80_|execute_|ctl_reg_in_hi~4_combout ) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~44_combout = (\z80_|alu_|db[3]~11_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[3]~11_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~44 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~48_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h4444; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h4000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|execute_|ctl_reg_gp_we~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~43_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h5450; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # (\z80_|execute_|ctl_reg_sys_we_lo~3_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hFB33; -defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~combout = ((\z80_|reg_control_|reg_sys_we_hi~0_combout ) # (\z80_|execute_|ctl_reg_sys_we~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF3; -defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~45 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[3]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0002; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h0400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0008; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~42_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~42 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[3]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~46_combout = (\z80_|reg_file_|gdfx_temp1[3]~44_combout & (\z80_|reg_file_|gdfx_temp1[3]~43_combout & (\z80_|reg_file_|gdfx_temp1[3]~45_combout & \z80_|reg_file_|gdfx_temp1[3]~42_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~46 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~47_combout = (\z80_|reg_file_|gdfx_temp1[3]~40_combout & (\z80_|reg_file_|gdfx_temp1[3]~41_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout & \z80_|reg_file_|gdfx_temp1[3]~46_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~47 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFF8; -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~16_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|reg_control_|reg_sel_pc~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N11 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|alu_|db[1]~13_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[1]~13_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[1]~13_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~21_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~12_combout & (\z80_|reg_file_|gdfx_temp1[1]~10_combout & \z80_|reg_file_|gdfx_temp1[1]~11_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~8_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout & (\z80_|reg_file_|gdfx_temp1[1]~14_combout & \z80_|reg_file_|gdfx_temp1[1]~9_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .datac(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (!\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_control_|reg_sys_we_lo~combout ) # ((!\z80_|execute_|ctl_reg_sel_ir~1_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'h8AAA; -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_file_|gdfx_temp1[1]~21_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[1]~21_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|reg_control_|reg_sel_pc~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # (\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|address_latch_|Q [7] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [8]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'h96CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|alu_|db[0]~19_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[0]~19_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[0]~19_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~24_combout & (\z80_|reg_file_|gdfx_temp1[0]~26_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & \z80_|reg_file_|gdfx_temp1[0]~27_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|gdfx_temp1[0]~28_combout & \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .datad(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( -// Equation(s): -// \z80_|address_latch_|abusz [8] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[0]~6_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [8]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N9 -dffeas \z80_|address_latch_|Q[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [8]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N18 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|address_latch_|Q [7] & (\z80_|address_latch_|Q [8] & !\z80_|execute_|ctl_inc_dec~11_combout -// )) # (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [8] & \z80_|execute_|ctl_inc_dec~11_combout )))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [8]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h1800; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N24 -cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( -// Equation(s): -// \z80_|address_latch_|abusz [9] = (\z80_|reg_file_|db_hi_as[1]~3_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [9]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|Q[9]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[9]~feeder_combout = \z80_|address_latch_|abusz [9] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [9]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[9]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[9]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[9]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N5 -dffeas \z80_|address_latch_|Q[9] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[9]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ -// (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [9]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~32 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~35_combout = (\z80_|alu_|db[2]~15_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[2]~15_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[2]~15_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~35 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~34 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~33_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~33 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N1 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~36 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~37_combout = (\z80_|reg_file_|gdfx_temp1[2]~35_combout & (\z80_|reg_file_|gdfx_temp1[2]~34_combout & (\z80_|reg_file_|gdfx_temp1[2]~33_combout & \z80_|reg_file_|gdfx_temp1[2]~36_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~37 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~31 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~38_combout = (\z80_|reg_file_|gdfx_temp1[2]~32_combout & (\z80_|reg_file_|gdfx_temp1[2]~37_combout & (\z80_|reg_file_|gdfx_temp1[2]~31_combout & \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~38 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~39_combout = ((\z80_|reg_file_|gdfx_temp1[2]~38_combout & ((\z80_|reg_file_|db_hi_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~39 .lut_mask = 16'h8FAF; -defparam \z80_|reg_file_|gdfx_temp1[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp1[2]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[2]~39_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~7 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~8_combout = (\z80_|reg_file_|db_hi_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~7_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~8 .lut_mask = 16'hCC44; -defparam \z80_|reg_file_|db_hi_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~9 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~9_combout = ((\z80_|reg_file_|db_hi_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[2]~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~9 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N0 -cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( -// Equation(s): -// \z80_|address_latch_|abusz [10] = (\z80_|reg_file_|db_hi_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [10]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|Q[10]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[10]~feeder_combout = \z80_|address_latch_|abusz [10] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [10]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[10]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[10]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N27 -dffeas \z80_|address_latch_|Q[10] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[10]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [10] & (\z80_|address_latch_|Q [9] & -// !\z80_|execute_|ctl_inc_dec~11_combout )) # (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [9] & \z80_|execute_|ctl_inc_dec~11_combout )))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [9]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h1800; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( -// Equation(s): -// \z80_|address_latch_|abusz [11] = (\z80_|reg_file_|db_hi_as[3]~12_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h00CC; -defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N15 -dffeas \z80_|address_latch_|Q[11] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [11]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout $ (\z80_|address_latch_|Q [11]) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(gnd), - .datac(\z80_|address_latch_|Q [11]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h5A5A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp1[3]~48_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[3]~48_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~11 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~11_combout = (\z80_|reg_file_|db_hi_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[3]~10_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~11 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|db_hi_as[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~12_combout = ((\z80_|reg_file_|db_hi_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[3]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~12 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~48_combout = ((\z80_|reg_file_|gdfx_temp1[3]~47_combout & ((\z80_|reg_file_|db_hi_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~48 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'h888A; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hC0E0; -defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[3]~8_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N7 -dffeas \z80_|alu_|op1_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~3 ( -// Equation(s): -// \z80_|alu_|alu_op1[3]~3_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])) - - .dataa(gnd), - .datab(\z80_|alu_|op1_high [3]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[3]~3 .lut_mask = 16'hF0CC; -defparam \z80_|alu_|alu_op1[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [2])))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|alu_|alu_op2[2]~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0305; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = ((\z80_|pla_decode_|Equal8~0_combout & (\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mWrite~2_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|pla_decode_|Equal8~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'hAAFB; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~0_combout = (\z80_|pla_decode_|Equal1~5_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~5_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) # (((\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = ((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) # -// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .lut_mask = 16'h5050; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_zero~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFFFA; -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N1 -dffeas \z80_|alu_|op2_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[1]~20_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N23 -dffeas \z80_|alu_|op1_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))))) - - .dataa(\z80_|alu_|op1_low [1]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'h8C80; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|alu_|db_low[1]~17_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .datac(\z80_|alu_|db_low[1]~17_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N21 -dffeas \z80_|alu_|op2_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~20_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal68~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal68~2_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .lut_mask = 16'h0D0F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|execute_|ctl_state_alu~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # ((\z80_|execute_|ctl_state_alu~11_combout ) # (!\z80_|execute_|ctl_state_alu~8_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~9_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datac(\z80_|execute_|ctl_state_alu~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~18_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~12_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h7577; -defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) +// \z80_|pla_decode_|Equal0~0_combout = (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~4_combout ) .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal61~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal61~2_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M4_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'hFC00; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~20_combout & (\z80_|execute_|ctl_alu_core_hf~18_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~21_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~17_combout & (((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~4_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout -// ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & (\z80_|execute_|ctl_alu_core_S~4_combout & \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_ir_we~11_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .lut_mask = 16'hC4CC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~20_combout = ((\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout ))) # (!\z80_|execute_|ctl_state_alu~12_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal71~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal71~2_combout = (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~12_combout & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal71~2 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_alu_core_hf~20_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & !\z80_|pla_decode_|Equal71~2_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|pla_decode_|Equal71~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'h0080; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~31_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~9_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'h1333; -defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (\z80_|pla_decode_|Equal21~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal3~0_combout & -// ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'hFCA8; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout = (\z80_|pla_decode_|Equal13~1_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal13~1_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N16 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & \z80_|pla_decode_|Equal63~0_combout -// ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'hFFEC; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (\z80_|execute_|ctl_alu_op_low~31_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & !\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'h0080; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal72~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal72~2_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal72~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal72~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal72~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal73~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|pla_decode_|Equal61~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal61~2_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (!\z80_|pla_decode_|Equal72~2_combout & (!\z80_|pla_decode_|Equal73~2_combout & \z80_|execute_|ctl_flags_nf_we~0_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datab(\z80_|pla_decode_|Equal72~2_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~3_combout = ((\z80_|execute_|ctl_flags_nf_we~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout )) # (!\z80_|execute_|ctl_flags_nf_we~1_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFAFF; -defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|pla_decode_|Equal48~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|execute_|ctl_flags_sz_we~5_combout & \z80_|execute_|ctl_alu_core_R~0_combout )))) # -// (!\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_flags_sz_we~5_combout & ((\z80_|execute_|ctl_alu_core_R~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hECA0; -defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~4_combout = (((\z80_|execute_|ctl_flags_nf_we~3_combout ) # (\z80_|execute_|ctl_flags_sz_we~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~12_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~15 ( -// Equation(s): -// \z80_|execute_|setM1~15_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_state_alu~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~15 .lut_mask = 16'h5000; -defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~16 ( -// Equation(s): -// \z80_|execute_|setM1~16_combout = (\z80_|execute_|setM1~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~31_combout ))) - - .dataa(\z80_|execute_|setM1~15_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0200; -defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|setM1~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|setM1~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & \z80_|execute_|ctl_alu_oe~5_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (\z80_|execute_|ctl_flags_xy_we~7_combout & \z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) - - .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~7_combout ), .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .combout(\z80_|pla_decode_|Equal0~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal0~0 .lut_mask = 16'h5500; +defparam \z80_|pla_decode_|Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 ( +// Location: LCCOMB_X40_Y13_N8 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( // Equation(s): -// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal11~1_combout & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) +// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal11~1_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), + .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88C0; +defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), - .cout()); +// Location: FF_X40_Y13_N9 +dffeas \z80_|sequencer_|DFFE_M3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M3_ff~q ), + .prn(vcc)); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFBAA; -defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~7_combout = (\z80_|execute_|ctl_alu_core_R~1_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_flags_alu~18_combout )) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~7 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_flags_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~8 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~8_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal56~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~8 .lut_mask = 16'h7F00; -defparam \z80_|reg_control_|reg_sys_we_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~8_combout = ((\z80_|execute_|ctl_flags_alu~7_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~8_combout ) # (!\z80_|execute_|ctl_flags_alu~16_combout ))) # (!\z80_|execute_|ctl_flags_alu~6_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), - .datab(\z80_|execute_|ctl_flags_alu~7_combout ), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~8 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_alu_op_low~10_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal20~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~10_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'h0070; -defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~13_combout = (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_flags_xy_we~16_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_alu~12_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datac(\z80_|execute_|ctl_sw_2d~4_combout ), - .datad(\z80_|execute_|ctl_flags_alu~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_alu_op_low~15_combout & (\z80_|execute_|ctl_sw_4u~1_combout & \z80_|execute_|ctl_flags_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|execute_|ctl_flags_alu~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~15_combout = ((\z80_|execute_|ctl_flags_alu~8_combout ) # ((!\z80_|execute_|ctl_flags_alu~11_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_alu~8_combout ), - .datac(\z80_|execute_|ctl_flags_alu~14_combout ), - .datad(\z80_|execute_|ctl_flags_alu~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N12 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFCEC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~19_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ) # ((\z80_|alu_control_|db[1]~26_combout & \z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), - .datac(\z80_|alu_control_|db[1]~26_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEEE; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X37_Y9_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( +cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( // Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|execute_|ctl_flags_alu~15_combout & \z80_|alu_|db_high[3]~8_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) +// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFFB3; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'h3070; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .lut_mask = 16'h0800; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) - - .dataa(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .lut_mask = 16'hD850; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y9_N27 -dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) # (!\z80_|sequencer_|DFFE_M2_ff~q & -// (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'h7707; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = ((\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'hB3BB; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~11_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~18_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~15_combout & \z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .lut_mask = 16'hFDF5; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal13~2_combout & \z80_|sequencer_|DFFE_M3_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~1 ( -// Equation(s): -// \z80_|alu_|alu_op2[1]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [1])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [1]))))) - - .dataa(\z80_|alu_|op2_high [1]), - .datab(\z80_|alu_|op2_low [1]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[1]~1 .lut_mask = 16'h5A3C; -defparam \z80_|alu_|alu_op2[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high -// [1]))))) - - .dataa(\z80_|alu_|alu_op2[1]~1_combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h1015; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~9_combout = (((\z80_|pla_decode_|Equal71~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_core_S~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), - .datad(\z80_|pla_decode_|Equal71~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout = (\z80_|alu_|db_high[0]~26_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|alu_|db_low[0]~23_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # -// (!\z80_|alu_|db_high[0]~26_combout & (\z80_|alu_|db_low[0]~23_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout ))) - - .dataa(\z80_|alu_|db_high[0]~26_combout ), - .datab(\z80_|alu_|db_low[0]~23_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .lut_mask = 16'hEAC0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) - - .dataa(gnd), + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N7 -dffeas \z80_|alu_|op2_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( -// Equation(s): -// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|alu_|op2_high [0]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h3C5A; -defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~12 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & ((\z80_|ir_|opcode [3]) # ((!\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal62~2_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .lut_mask = 16'hB0F0; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & \z80_|execute_|ctl_alu_core_S~7_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~9_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # -// (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h37FF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_alu_core_hf~20_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .datac(gnd), .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .combout(\z80_|execute_|ixy_d~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( +// Location: LCCOMB_X36_Y6_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 ( // Equation(s): -// \z80_|execute_|ctl_alu_core_hf~22_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~21_combout )) # (!\z80_|execute_|ctl_alu_core_hf~18_combout ) +// \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal0~0_combout & (\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [1]))) - .dataa(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal0~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'hD5FF; -defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( +// Location: LCCOMB_X36_Y6_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( // Equation(s): -// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hA0E0; -defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (((\z80_|execute_|ctl_alu_op_low~22_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~29_combout = (\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~23_combout = (\z80_|execute_|ctl_alu_core_hf~22_combout & (((\z80_|execute_|ctl_alu_core_hf~19_combout & !\z80_|execute_|ctl_alu_op_low~29_combout )) # (!\z80_|execute_|ctl_alu_op_low~28_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~22_combout & (\z80_|execute_|ctl_alu_core_hf~19_combout & (!\z80_|execute_|ctl_alu_op_low~29_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h0CAE; -defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|pla_decode_|Equal39~0_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal40~1_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hFF30; -defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~25_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'hEFEE; -defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'hA0A8; -defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~26_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hDFCC; -defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~28_combout = (\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_alu_op_low~20_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h22F2; -defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (((\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datab(\z80_|execute_|ctl_state_alu~13_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout & !\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~7_combout & -// ((!\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hC0CA; -defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~43_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|ctl_mRead~6_combout & (\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # -// ((\z80_|execute_|ctl_mRead~6_combout & \z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~43 .lut_mask = 16'hD5C0; -defparam \z80_|execute_|ctl_alu_core_hf~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~33_combout = (!\z80_|execute_|ctl_alu_core_hf~43_combout & ((\z80_|execute_|ctl_alu_core_hf~32_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~32_combout & (\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'h00E8; -defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~42 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~42_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~42 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_alu_core_hf~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~42_combout & ((\z80_|execute_|ctl_alu_core_hf~34_combout ) # (\z80_|execute_|ctl_alu_core_hf~33_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~41_combout = (!\z80_|execute_|ctl_state_alu~4_combout & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal10~0_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~41 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_alu_core_hf~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & -// (\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~10_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal11~1_combout & \z80_|execute_|ctl_mWrite~2_combout ))) +// \z80_|pla_decode_|Equal33~0_combout = (\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0])) .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal11~1_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~31_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_mWrite~10_combout & ((\z80_|execute_|ctl_alu_core_hf~41_combout ) # (\z80_|execute_|ctl_alu_core_hf~30_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~41_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'h0054; -defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~44_combout = (\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~44 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_core_hf~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~29_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & ((\z80_|execute_|ctl_alu_core_hf~44_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~44_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'h0E0A; -defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # ((!\z80_|execute_|ctl_alu_op_low~30_combout & \z80_|execute_|ctl_alu_core_hf~35_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'hFFF4; -defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~39_combout = (\z80_|execute_|ctl_alu_core_hf~28_combout ) # ((\z80_|execute_|ctl_alu_core_hf~36_combout ) # ((\z80_|execute_|ctl_alu_core_hf~38_combout & !\z80_|execute_|ctl_alu_op_low~24_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~39 .lut_mask = 16'hFCFE; -defparam \z80_|execute_|ctl_alu_core_hf~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~40_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((\z80_|execute_|ctl_alu_core_hf~39_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~40 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_alu_core_hf~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datad(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~combout = (\z80_|execute_|ctl_alu_core_R~2_combout ) # (((\z80_|pla_decode_|Equal73~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_R~2_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .lut_mask = 16'hC0D0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_high[3]~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), - .datad(\z80_|alu_|db_high[3]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .lut_mask = 16'h5450; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N9 -dffeas \z80_|alu_|op2_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [3]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ) # ((\z80_|alu_|db_low[3]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), - .datac(\z80_|alu_|db_low[3]~25_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N19 -dffeas \z80_|alu_|op2_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~2 ( -// Equation(s): -// \z80_|alu_|alu_op2[3]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [3])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [3]))))) - - .dataa(\z80_|alu_|op2_high [3]), - .datab(\z80_|alu_|op2_low [3]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[3]~2 .lut_mask = 16'h5A3C; -defparam \z80_|alu_|alu_op2[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[3]~3_combout & \z80_|alu_|alu_op2[3]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|alu_|alu_op1[3]~3_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datac(\z80_|alu_|alu_op2[3]~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [3])))) - - .dataa(\z80_|alu_|alu_op2[3]~2_combout ), - .datab(\z80_|alu_|op1_high [3]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0511; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_R~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hAFAE; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # -// (!\z80_|execute_|ctl_flags_bus~combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'h8F88; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((\z80_|pla_decode_|Equal10~0_combout & -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hFC88; -defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~14_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~14_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) - - .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datad(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hCCE4; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N7 -dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|pla_decode_|Equal52~1_combout ) # (\z80_|execute_|ctl_state_alu~14_combout )) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~12_combout = ((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_alu_op_low~12_combout ))) # (!\z80_|execute_|ctl_flags_hf_cpl~10_combout ) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .datab(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~13_combout = (\z80_|execute_|ctl_flags_hf_cpl~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|alu_flags_|DFFE_inst_latch_nf~q ))) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~13 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_hf_cpl~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N8 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( -// Equation(s): -// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~13_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h559A; -defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N30 -cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( -// Equation(s): -// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~40_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~40_combout & (\z80_|alu_flags_|flags_cf~combout )) - - .dataa(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .datab(\z80_|alu_flags_|flags_cf~combout ), + .datab(\z80_|ir_|opcode [1]), .datac(gnd), - .datad(\z80_|alu_flags_|flags_hf~combout ), + .datad(\z80_|ir_|opcode [0]), .cin(gnd), - .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .combout(\z80_|pla_decode_|Equal33~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hEE44; -defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_control_|alu_core_cf_in~0_combout & \z80_|alu_|alu_op1[0]~1_combout )))) -// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|alu_|alu_op1[0]~1_combout )))) - - .dataa(\z80_|alu_|alu_op2[0]~3_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op1[0]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( -// Equation(s): -// \z80_|alu_|db_high[0]~23_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~25_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[3]~11_combout ), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hE4E4; -defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( -// Equation(s): -// \z80_|address_latch_|abusz [12] = (\z80_|reg_file_|db_hi_as[4]~18_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [12]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|Q[12]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[12]~feeder_combout = \z80_|address_latch_|abusz [12] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [12]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[12]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[12]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[12]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N15 -dffeas \z80_|address_latch_|Q[12] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[12]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ -// (\z80_|address_latch_|Q [11]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hD278; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~16 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~16_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~16 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|db_hi_as[4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~17 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~17_combout = (\z80_|reg_file_|db_hi_as[4]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .datad(\z80_|reg_file_|db_hi_as[4]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~17 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|db_hi_as[4]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~18 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~18_combout = ((\z80_|reg_file_|db_hi_as[4]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[4]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~18 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[4]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N11 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~62_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [4] & ((\z80_|alu_|db[4]~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~12_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[4]~17_combout )) # (!\z80_|execute_|ctl_reg_in_hi~12_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .datad(\z80_|alu_|db[4]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~62 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y11_N29 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~63_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~63 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[4]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N23 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~61_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~61 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp1[4]~66_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~60_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~60 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~64_combout = (\z80_|reg_file_|gdfx_temp1[4]~62_combout & (\z80_|reg_file_|gdfx_temp1[4]~63_combout & (\z80_|reg_file_|gdfx_temp1[4]~61_combout & \z80_|reg_file_|gdfx_temp1[4]~60_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~64 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~59 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~58 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~65_combout = (\z80_|reg_file_|gdfx_temp1[4]~64_combout & (\z80_|reg_file_|gdfx_temp1[4]~59_combout & (\z80_|reg_file_|gdfx_temp1[4]~58_combout & \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~65 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~66_combout = ((\z80_|reg_file_|gdfx_temp1[4]~65_combout & ((\z80_|reg_file_|db_hi_as[4]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~66 .lut_mask = 16'hD5F5; -defparam \z80_|reg_file_|gdfx_temp1[4]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db[4]~16 ( -// Equation(s): -// \z80_|alu_|db[4]~16_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[4]~32_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[4]~32_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~16 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|db[7]~26 ( -// Equation(s): -// \z80_|alu_|db[7]~26_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout ) # ((\z80_|execute_|ctl_alu_oe~13_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_alu_oe~13_combout ), - .datac(\z80_|execute_|ctl_alu_oe~9_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~26 .lut_mask = 16'hFFEF; -defparam \z80_|alu_|db[7]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db[4]~17 ( -// Equation(s): -// \z80_|alu_|db[4]~17_combout = ((\z80_|alu_|db[4]~16_combout & ((\z80_|alu_|db_high[0]~26_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[4]~16_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db_high[0]~26_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~17 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[4]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & \z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h00C8; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~6_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( -// Equation(s): -// \z80_|alu_|db_high[0]~24_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[0]~23_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[4]~17_combout ))) - - .dataa(\z80_|alu_|db_high[0]~23_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[4]~17_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hAAF0; -defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( -// Equation(s): -// \z80_|alu_|db_high[0]~21_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'h5575; -defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|alu_|db_high[0]~26_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[0]~26_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N21 -dffeas \z80_|alu_|op1_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( -// Equation(s): -// \z80_|alu_|db_high[0]~22_combout = (\z80_|alu_|op1_high [0] & (((\z80_|alu_|op2_high [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [0] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [0]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [0]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( -// Equation(s): -// \z80_|alu_|db_high[0]~25_combout = (\z80_|alu_|db_high[0]~21_combout & (\z80_|alu_|db_high[0]~22_combout & ((\z80_|alu_|db_high[0]~24_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[0]~24_combout ), - .datab(\z80_|alu_|db_high[0]~21_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[0]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'h8C00; -defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~26 ( -// Equation(s): -// \z80_|alu_|db_high[0]~26_combout = ((\z80_|alu_|db_high[0]~25_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|db_high[0]~25_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~26 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|db_low[0]~23_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) # -// (!\z80_|alu_|db_low[0]~23_combout & (((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) - - .dataa(\z80_|alu_|db_low[0]~23_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datad(\z80_|alu_|db_high[0]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFEFE; -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N31 -dffeas \z80_|alu_|op1_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( -// Equation(s): -// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [0]))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_low [0]), - .datac(\z80_|alu_|op1_high [0]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|alu_|alu_op1[0]~1_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[0]~23_combout )))) # -// (!\z80_|alu_|alu_op1[0]~1_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & ((\z80_|alu_|db_low[0]~23_combout )))) - - .dataa(\z80_|alu_|alu_op1[0]~1_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_low[0]~23_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h5050; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N15 -dffeas \z80_|alu_|op2_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(gnd), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hF0AA; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op1[0]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hF660; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~9_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & -// \z80_|execute_|ctl_alu_core_S~8_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hF1F0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op1[1]~0 ( -// Equation(s): -// \z80_|alu_|alu_op1[1]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(gnd), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[1]~0 .lut_mask = 16'hDD88; -defparam \z80_|alu_|alu_op1[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[1]~0_combout & \z80_|alu_|alu_op2[1]~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datac(\z80_|alu_|alu_op1[1]~0_combout ), - .datad(\z80_|alu_|alu_op2[1]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hFBBB; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # -// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h0F01; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op1[2]~2 ( -// Equation(s): -// \z80_|alu_|alu_op1[2]~2_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(gnd), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[2]~2 .lut_mask = 16'hEE22; -defparam \z80_|alu_|alu_op1[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op2[2]~0_combout & \z80_|alu_|alu_op1[2]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|alu_|alu_op2[2]~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datac(\z80_|alu_|alu_op1[2]~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hFF0B; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & \z80_|execute_|ctl_alu_core_S~8_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .lut_mask = 16'h5F5D; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op1[3]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & -// \z80_|alu_|alu_op2[3]~2_combout )))) # (!\z80_|alu_|alu_op1[3]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[3]~2_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) - - .dataa(\z80_|alu_|alu_op1[3]~3_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|alu_op2[3]~2_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'hFB20; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp1[7]~75_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~69_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~69 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[7]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~70 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~72_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~72 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[7]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~71_combout = (\z80_|alu_|db[7]~21_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[7]~21_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~71 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[7]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~73_combout = (\z80_|reg_file_|gdfx_temp1[7]~69_combout & (\z80_|reg_file_|gdfx_temp1[7]~70_combout & (\z80_|reg_file_|gdfx_temp1[7]~72_combout & \z80_|reg_file_|gdfx_temp1[7]~71_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~73 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~67 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[7]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~68 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~74_combout = (\z80_|reg_file_|gdfx_temp1[7]~73_combout & (\z80_|reg_file_|gdfx_temp1[7]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout & \z80_|reg_file_|gdfx_temp1[7]~68_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~74 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~19 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~75_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~75_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~19 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[7]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~20 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~20_combout = (\z80_|reg_file_|db_hi_as[7]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[7]~19_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~20 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|db_hi_as[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [12] & -// !\z80_|address_latch_|Q [11])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [12] & \z80_|address_latch_|Q [11])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~54 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[5]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~53_combout = (\z80_|alu_|db[5]~25_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[5]~25_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[5]~25_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~53 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[5]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~57_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~51_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~51 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[5]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N11 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~52_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~52 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[5]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~55_combout = (\z80_|reg_file_|gdfx_temp1[5]~54_combout & (\z80_|reg_file_|gdfx_temp1[5]~53_combout & (\z80_|reg_file_|gdfx_temp1[5]~51_combout & \z80_|reg_file_|gdfx_temp1[5]~52_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~55 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~49 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~50 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[5]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~56_combout = (\z80_|reg_file_|gdfx_temp1[5]~55_combout & (\z80_|reg_file_|gdfx_temp1[5]~49_combout & (\z80_|reg_file_|gdfx_temp1[5]~50_combout & \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~56 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~57_combout = ((\z80_|reg_file_|gdfx_temp1[5]~56_combout & ((\z80_|reg_file_|db_hi_as[5]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), - .datac(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~57 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~13 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~13_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[5]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~14 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~14_combout = (\z80_|reg_file_|db_hi_as[5]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|db_hi_as[5]~13_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~14 .lut_mask = 16'hC4C4; -defparam \z80_|reg_file_|db_hi_as[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~15 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~15_combout = ((\z80_|reg_file_|db_hi_as[5]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[5]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~15 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[5]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( -// Equation(s): -// \z80_|address_latch_|abusz [13] = (\z80_|reg_file_|db_hi_as[5]~15_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [13]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|Q[13]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[13]~feeder_combout = \z80_|address_latch_|abusz [13] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [13]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[13]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[13]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N23 -dffeas \z80_|address_latch_|Q[13] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[13]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|execute_|ctl_inc_dec~11_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( -// Equation(s): -// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~21_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N27 -dffeas \z80_|address_latch_|Q[15] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [15]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [13]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [14]), - .datad(\z80_|execute_|ctl_inc_dec~11_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'hB478; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~76 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~80_combout = (\z80_|alu_|db[6]~23_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[6]~23_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[6]~23_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~80 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N17 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~79_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~79 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~78 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~81 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~82_combout = (\z80_|reg_file_|gdfx_temp1[6]~80_combout & (\z80_|reg_file_|gdfx_temp1[6]~79_combout & (\z80_|reg_file_|gdfx_temp1[6]~78_combout & \z80_|reg_file_|gdfx_temp1[6]~81_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~82 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~77 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~83_combout = (\z80_|reg_file_|gdfx_temp1[6]~76_combout & (\z80_|reg_file_|gdfx_temp1[6]~82_combout & (\z80_|reg_file_|gdfx_temp1[6]~77_combout & \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~83 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~84_combout = ((\z80_|reg_file_|gdfx_temp1[6]~83_combout & ((\z80_|reg_file_|db_hi_as[6]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), - .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~84 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~22 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~22_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~22 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~23 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~23_combout = (\z80_|reg_file_|db_hi_as[6]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .datab(\z80_|reg_file_|db_hi_as[6]~22_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~23 .lut_mask = 16'h88CC; -defparam \z80_|reg_file_|db_hi_as[6]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~24 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~24_combout = ((\z80_|reg_file_|db_hi_as[6]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_file_|db_hi_as[6]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~24 .lut_mask = 16'hBF33; -defparam \z80_|reg_file_|db_hi_as[6]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( -// Equation(s): -// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~24_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|Q[14]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[14]~feeder_combout = \z80_|address_latch_|abusz [14] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [14]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[14]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[14]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N5 -dffeas \z80_|address_latch_|Q[14] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[14]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|address_latch_|Q [14]), - .datac(\z80_|execute_|ctl_inc_dec~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h3363; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~21 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~21_combout = ((\z80_|reg_file_|db_hi_as[7]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[7]~20_combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~21 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_hi_as[7]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~75_combout = ((\z80_|reg_file_|gdfx_temp1[7]~74_combout & ((\z80_|reg_file_|db_hi_as[7]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), - .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~75 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[7]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( -// Equation(s): -// \z80_|alu_|db[7]~20_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[7]~75_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .datad(\z80_|alu_control_|db[7]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db[7]~21 ( -// Equation(s): -// \z80_|alu_|db[7]~21_combout = ((\z80_|alu_|db[7]~20_combout & ((\z80_|alu_|db_high[3]~8_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[7]~20_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~21 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[7]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N22 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (\z80_|alu_|db[7]~21_combout & ((\z80_|ir_|opcode [3])))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & -// (\z80_|alu_|db[7]~21_combout )))) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hB822; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (\z80_|alu_control_|db[0]~12_combout & (\z80_|execute_|ctl_flags_bus~combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & -// ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[0]~12_combout & \z80_|execute_|ctl_flags_bus~combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datab(\z80_|alu_control_|db[0]~12_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'hD5C0; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hF4FC; -defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~6_combout = ((\z80_|execute_|ctl_flags_cf_we~5_combout ) # ((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~2 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_flags_cf2_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~4_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal10~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'hE000; -defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~3_combout = (\z80_|execute_|ctl_flags_cf2_we~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|ixy_d~15_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_flags_cf2_we~2_combout ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_flags_cf2_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~3_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0B8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y9_N3 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N0 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h0A88; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N4 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout & !\z80_|ir_|opcode [4])) - - .dataa(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .datac(gnd), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hCCEE; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( -// Equation(s): -// \z80_|alu_|db_high[3]~5_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[6]~23_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .datac(\z80_|alu_|db[6]~23_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( -// Equation(s): -// \z80_|alu_|db_high[3]~6_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[3]~5_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[7]~21_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(\z80_|alu_|db_high[3]~5_combout ), - .datac(\z80_|alu_|db[7]~21_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( -// Equation(s): -// \z80_|alu_|db_high[3]~4_combout = (\z80_|alu_|op2_high [3] & (((\z80_|alu_|op1_high [3])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_high [3] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [3]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_high [3]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_high [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~27 ( -// Equation(s): -// \z80_|alu_|db_high[3]~27_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~27 .lut_mask = 16'hD555; -defparam \z80_|alu_|db_high[3]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( -// Equation(s): -// \z80_|alu_|db_high[3]~7_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~27_combout & ((\z80_|alu_|db_high[3]~6_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[3]~6_combout ), - .datab(\z80_|alu_|db_high[3]~4_combout ), - .datac(\z80_|alu_|db_high[3]~27_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'h80C0; -defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~8 ( -// Equation(s): -// \z80_|alu_|db_high[3]~8_combout = ((\z80_|alu_|db_high[3]~7_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|db_high[3]~7_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~8 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[3]~8_combout )))) - - .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N15 -dffeas \z80_|alu_|op1_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~9 ( -// Equation(s): -// \z80_|alu_|db_low[3]~9_combout = (\z80_|alu_|op1_low [3] & (((\z80_|alu_|op2_low [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_low [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [3]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_low [3]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_low [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~9 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_low[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[4]~19_combout & \z80_|bus_control_|db[3]~21_combout ) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hCC00; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~10 ( -// Equation(s): -// \z80_|alu_|db_low[3]~10_combout = (\z80_|alu_|db_low[3]~9_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|bus_control_|db[5]~15_combout ), - .datab(\z80_|alu_|db_low[3]~9_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~10 .lut_mask = 16'h4C0C; -defparam \z80_|alu_|db_low[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N15 -dffeas \z80_|alu_|result_lo[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~7 ( -// Equation(s): -// \z80_|alu_|db_low[3]~7_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~17_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) - - .dataa(\z80_|alu_|db[4]~17_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[2]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~7 .lut_mask = 16'hAFA0; -defparam \z80_|alu_|db_low[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~8 ( -// Equation(s): -// \z80_|alu_|db_low[3]~8_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~7_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~11_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_low[3]~7_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~8 .lut_mask = 16'hF3BB; -defparam \z80_|alu_|db_low[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~11 ( -// Equation(s): -// \z80_|alu_|db_low[3]~11_combout = (\z80_|alu_|db_low[3]~10_combout & (\z80_|alu_|db_low[3]~8_combout & ((\z80_|alu_|result_lo [3]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[3]~10_combout ), - .datab(\z80_|alu_|result_lo [3]), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_low[3]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~11 .lut_mask = 16'hA800; -defparam \z80_|alu_|db_low[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~25 ( -// Equation(s): -// \z80_|alu_|db_low[3]~25_combout = (\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|alu_|db_low[3]~11_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~25 .lut_mask = 16'hF1F1; -defparam \z80_|alu_|db_low[3]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N12 -cycloneive_lcell_comb \z80_|alu_|db[3]~10 ( -// Equation(s): -// \z80_|alu_|db[3]~10_combout = (\z80_|execute_|ctl_alu_oe~14_combout & (\z80_|alu_|db_low[3]~25_combout & ((\z80_|reg_file_|gdfx_temp1[3]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_alu_oe~14_combout & -// (((\z80_|reg_file_|gdfx_temp1[3]~48_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .datad(\z80_|alu_|db_low[3]~25_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~10 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|db[3]~11 ( -// Equation(s): -// \z80_|alu_|db[3]~11_combout = ((\z80_|alu_|db[3]~10_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[3]~10_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[3]~35_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~11 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_alu_oe~9_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~3_combout ), - .datac(\z80_|execute_|ctl_alu_oe~9_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~49 ( -// Equation(s): -// \z80_|execute_|setM1~49_combout = (\z80_|execute_|setM1~48_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~49 .lut_mask = 16'h0070; -defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~14_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~49_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|setM1~49_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h0B0F; -defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|alu_|db_low[3]~25_combout & ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[3]~35_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_low[3]~25_combout & -// (\z80_|alu_control_|db[3]~35_combout & (\z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|alu_|db_low[3]~25_combout ), - .datab(\z80_|alu_control_|db[3]~35_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hEAC0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout = (\z80_|pla_decode_|Equal56~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # ((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # -// (!\z80_|execute_|ctl_flags_xy_we~10_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~14_combout = (((\z80_|execute_|ctl_flags_xy_we~13_combout ) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) - - .dataa(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~15_combout = (((\z80_|execute_|ctl_flags_xy_we~14_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N31 -dffeas \z80_|alu_flags_|flags_xf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_xf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_xf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( -// Equation(s): -// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_flags_|flags_xf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hF030; -defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFEFA; -defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|execute_|ixy_d~7_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFAEA; -defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N16 -cycloneive_lcell_comb \z80_|sw1_|db_down[3]~1 ( -// Equation(s): -// \z80_|sw1_|db_down[3]~1_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[3]~1 .lut_mask = 16'hFF8C; -defparam \z80_|sw1_|db_down[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( -// Equation(s): -// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & (\z80_|sw1_|db_down[3]~1_combout & ((\z80_|reg_file_|gdfx_temp0[3]~52_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datab(\z80_|alu_control_|db[3]~33_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|sw1_|db_down[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'h8C00; -defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( -// Equation(s): -// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~11_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[3]~34_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hBF33; -defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [3] & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[3]~35_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .datad(\z80_|alu_control_|db[3]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|gdfx_temp0[3]~46_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .datab(gnd), - .datac(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~49_combout & \z80_|reg_file_|gdfx_temp0[3]~47_combout )) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N31 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N5 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~51_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & (\z80_|reg_file_|gdfx_temp0[3]~50_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~52_combout = ((\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp0[3]~52_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[3]~52_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hAA0A; -defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( -// Equation(s): -// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [3]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h3030; -defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N17 -dffeas \z80_|address_latch_|Q[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [3]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout = \z80_|address_latch_|Q [3] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .lut_mask = 16'h40BF; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout )))) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h6AAA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|gdfx_temp0[4]~53_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|alu_control_|db[4]~32_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hBB00; -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N27 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N1 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~58_combout & (\z80_|reg_file_|gdfx_temp0[4]~59_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'hA200; -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N21 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N11 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N1 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N7 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|gdfx_temp0[4]~55_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~61_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & (\z80_|reg_file_|gdfx_temp0[4]~60_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & \z80_|reg_file_|gdfx_temp0[4]~56_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~62_combout = ((\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|reg_file_|gdfx_temp0[4]~62_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[4]~62_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hCC0C; -defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N16 -cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( -// Equation(s): -// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~15_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [4]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h3300; -defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N23 -dffeas \z80_|address_latch_|Q[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [4]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|address_latch_|Q [4]), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout -// ))) - - .dataa(\z80_|address_latch_|Q [5]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h6A6A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N23 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N13 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N21 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N5 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [5] & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[5]~15_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .datad(\z80_|alu_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|gdfx_temp0[5]~66_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .datad(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N3 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~67_combout & (\z80_|reg_file_|gdfx_temp0[5]~65_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~68_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~71_combout = (\z80_|reg_file_|gdfx_temp0[5]~64_combout & (\z80_|reg_file_|gdfx_temp0[5]~63_combout & \z80_|reg_file_|gdfx_temp0[5]~70_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~72_combout = ((\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .lut_mask = 16'hD5F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|reg_file_|gdfx_temp0[5]~72_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[5]~72_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'hF050; -defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( -// Equation(s): -// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~18_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [5]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N27 -dffeas \z80_|address_latch_|Q[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [5]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N26 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout = \z80_|address_latch_|Q [5] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout ))) - - .dataa(\z80_|address_latch_|Q [5]), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .lut_mask = 16'h5595; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N17 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N7 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N19 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N5 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N3 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[6]~22_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|gdfx_temp0[6]~76_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~78_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & \z80_|reg_file_|gdfx_temp0[6]~77_combout )) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N5 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~74_combout & (\z80_|reg_file_|gdfx_temp0[6]~73_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & \z80_|reg_file_|gdfx_temp0[6]~75_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[6]~82_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .datad(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( -// Equation(s): -// \z80_|address_latch_|abusz [6] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[6]~21_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N23 -dffeas \z80_|address_latch_|Q[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [6]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # (\z80_|execute_|ctl_inc_dec~7_combout ))))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h001E; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h55AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'hF575; -defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N25 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N29 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N19 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N11 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~92_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|gdfx_temp0[7]~86_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .datad(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[7]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & \z80_|reg_file_|gdfx_temp0[7]~89_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~91_combout = (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~84_combout & \z80_|reg_file_|gdfx_temp0[7]~90_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~92 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~92_combout = ((\z80_|reg_file_|gdfx_temp0[7]~91_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[7]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[7]~0_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[7]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[7]~0 .lut_mask = 16'hF0F8; -defparam \z80_|reg_file_|db_lo_ds[7]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N11 -dffeas \z80_|interrupts_|im2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~12_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|interrupts_|im2~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h5000; -defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|execute_|ctl_mRead~12_combout & \z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~17 ( -// Equation(s): -// \z80_|alu_control_|db[7]~17_combout = (\z80_|reg_file_|db_lo_ds[7]~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|reg_file_|db_lo_ds[7]~0_combout ), - .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|bus_control_|db[7]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~17 .lut_mask = 16'h2A0A; -defparam \z80_|alu_control_|db[7]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~16 ( -// Equation(s): -// \z80_|alu_control_|db[7]~16_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[7]~21_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (\z80_|execute_|ctl_sw_2u~7_combout & (!\z80_|alu_|db[7]~21_combout ))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_|db[7]~21_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~16 .lut_mask = 16'h0CAE; -defparam \z80_|alu_control_|db[7]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( -// Equation(s): -// \z80_|alu_control_|db[7]~18_combout = ((\z80_|alu_control_|db[7]~17_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & !\z80_|alu_control_|db[7]~16_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[7]~17_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_control_|db[7]~16_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h33B3; -defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[7]~18_combout ) # ((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout -// & (((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[7]~18_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~7_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~3_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y9_N9 -dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'h008C; -defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h0088; +defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X37_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( // Equation(s): -// \z80_|execute_|ctl_flags_pf_we~8_combout = (((\z80_|execute_|ctl_flags_pf_we~5_combout ) # (\z80_|execute_|ctl_flags_pf_we~7_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ) - - .dataa(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # ((!\z80_|execute_|ctl_pf_sel[0]~3_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~11_combout ) - - .dataa(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|execute_|ctl_flags_bus~combout & (\z80_|alu_control_|db[2]~29_combout ))) # (!\z80_|execute_|ctl_flags_pf_we~9_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[2]~29_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'h88F0; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (((!\z80_|pla_decode_|Equal62~3_combout & !\z80_|execute_|ctl_alu_op_low~13_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h3070; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ))))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h152A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h3B00; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N24 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [14] & (!\z80_|address_latch_|Q [12] & (!\z80_|address_latch_|Q [15] & !\z80_|address_latch_|Q [13]))) - - .dataa(\z80_|address_latch_|Q [14]), - .datab(\z80_|address_latch_|Q [12]), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|Q [13]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N16 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~3_combout = (!\z80_|address_latch_|Q [1] & (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [3] & !\z80_|address_latch_|Q [2]))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|address_latch_|Q [0]), - .datac(\z80_|address_latch_|Q [3]), - .datad(\z80_|address_latch_|Q [2]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0004; -defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N14 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [6] & (!\z80_|address_latch_|Q [5] & !\z80_|address_latch_|Q [4]))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [6]), - .datac(\z80_|address_latch_|Q [5]), - .datad(\z80_|address_latch_|Q [4]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N8 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [11] & (!\z80_|address_latch_|Q [9] & !\z80_|address_latch_|Q [8]))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [11]), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|Q [8]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N18 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~0_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & (\z80_|decode_state_|DFFE_instNonRep~2_combout & \z80_|decode_state_|DFFE_instNonRep~1_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instNonRep~0_combout ), - .datab(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; -defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N16 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~9_combout & -// ((\z80_|decode_state_|DFFE_instNonRep~4_combout ))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|decode_state_|DFFE_instNonRep~q )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~q ), - .datad(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hF4B0; -defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y16_N17 -dffeas \z80_|decode_state_|DFFE_instNonRep ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instNonRep~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N12 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|pla_decode_|Equal62~3_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h0040; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & -// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - - .dataa(\z80_|interrupts_|DFFE_instIFF2~q ), - .datab(\z80_|decode_state_|DFFE_instNonRep~q ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'hA030; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout & -// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'h808C; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N23 -dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|alu_parity_out~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55FD; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & -// \z80_|alu_|alu_op1[1]~0_combout )))) # (!\z80_|alu_|alu_op2[1]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[1]~0_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[1]~1_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|alu_|alu_op1[1]~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'hFB20; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( -// Equation(s): -// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'hA55A; -defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( -// Equation(s): -// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout $ (\z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .datad(\z80_|alu_|alu_parity_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out .lut_mask = 16'hA956; -defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'hFFEF; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h20A0; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_|alu_parity_out~combout & \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .datac(\z80_|alu_|alu_parity_out~combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFEEE; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout & \z80_|execute_|ctl_flags_alu~15_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'hECCC; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N15 -dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( -// Equation(s): -// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal40~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ))) +// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal40~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|sel[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h70F0; -defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout = (!\z80_|alu_|db_high[1]~20_combout & (!\z80_|alu_|db_high[3]~8_combout & (!\z80_|alu_|db_high[2]~14_combout & !\z80_|alu_|db_high[0]~26_combout ))) - - .dataa(\z80_|alu_|db_high[1]~20_combout ), - .datab(\z80_|alu_|db_high[3]~8_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|alu_|db_high[0]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .lut_mask = 16'h0001; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout = (\z80_|alu_control_|db[6]~22_combout & \z80_|execute_|ctl_flags_bus~combout ) - - .dataa(\z80_|alu_control_|db[6]~22_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .lut_mask = 16'hAA00; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N14 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[3]~11_combout & (\z80_|alu_|db_high[3]~3_combout & ((!\z80_|alu_|db_low[2]~3_combout ) # (!\z80_|alu_|db_low[2]~6_combout )))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|alu_|db_low[2]~3_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h1300; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_low[1]~17_combout & (\z80_|execute_|ctl_flags_alu~15_combout & (!\z80_|alu_|db_low[0]~23_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_flags_alu~15_combout ), - .datac(\z80_|alu_|db_low[0]~23_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0400; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hF7FF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hEC00; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y13_N27 -dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|alu_control_|sel[1]~0_combout & (((\z80_|ir_|opcode [4])))) # (!\z80_|alu_control_|sel[1]~0_combout & ((\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ))) # (!\z80_|ir_|opcode [4] -// & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(\z80_|alu_control_|sel[1]~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hFC0A; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & (\z80_|alu_flags_|DFFE_inst_latch_sf~q )) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_pf~q ))))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datac(\z80_|alu_control_|sel[1]~0_combout ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hAFC0; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( -// Equation(s): -// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((\z80_|alu_control_|flags_cond_true~q )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|flags_cond_true~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hB874; -defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N21 -dffeas \z80_|alu_control_|flags_cond_true ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_control_|flags_cond_true~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|flags_cond_true~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; -defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~13_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sel_wz~14_combout ) # (((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~11_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|gdfx_temp0[0]~93_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~20_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N23 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X31_Y10_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .datad(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & (((\z80_|alu_control_|db[1]~26_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[1]~26_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N3 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N9 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~28_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & (\z80_|reg_file_|gdfx_temp0[1]~29_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N27 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N25 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~23_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'hF733; -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[1]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[1]~1_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[1]~1 .lut_mask = 16'hF0F8; -defparam \z80_|reg_file_|db_lo_ds[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N30 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( -// Equation(s): -// \z80_|alu_control_|db[1]~25_combout = (\z80_|reg_file_|db_lo_ds[1]~1_combout & (((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[1]~11_combout ), - .datab(\z80_|reg_file_|db_lo_ds[1]~1_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h0C8C; -defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~24 ( -// Equation(s): -// \z80_|alu_control_|db[1]~24_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[1]~13_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (\z80_|execute_|ctl_sw_2u~7_combout & ((!\z80_|alu_|db[1]~13_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_|db[1]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~24 .lut_mask = 16'h0ACE; -defparam \z80_|alu_control_|db[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( -// Equation(s): -// \z80_|alu_control_|db[1]~26_combout = ((\z80_|alu_control_|db[1]~25_combout & (\z80_|alu_control_|db[2]~23_combout & !\z80_|alu_control_|db[1]~24_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[1]~25_combout ), - .datab(\z80_|alu_control_|db[2]~23_combout ), - .datac(\z80_|alu_control_|db[6]~11_combout ), - .datad(\z80_|alu_control_|db[1]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h0F8F; -defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db[1]~12 ( -// Equation(s): -// \z80_|alu_|db[1]~12_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[1]~26_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~12 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db[1]~13 ( -// Equation(s): -// \z80_|alu_|db[1]~13_combout = ((\z80_|alu_|db[1]~12_combout & ((\z80_|alu_|db_low[1]~17_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[1]~12_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_low[1]~17_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~13 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( -// Equation(s): -// \z80_|alu_|db_low[0]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~13_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hF5A0; -defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( -// Equation(s): -// \z80_|alu_|db_low[0]~22_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[0]~21_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[0]~19_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db_low[0]~21_combout ), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~18 ( -// Equation(s): -// \z80_|alu_|db_low[0]~18_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~18 .lut_mask = 16'h5557; -defparam \z80_|alu_|db_low[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~19 ( -// Equation(s): -// \z80_|alu_|db_low[0]~19_combout = (\z80_|alu_|op2_low [0] & (((\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [0]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_low [0]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~19 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_low[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N25 -dffeas \z80_|alu_|result_lo[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~20 ( -// Equation(s): -// \z80_|alu_|db_low[0]~20_combout = (\z80_|alu_|db_low[0]~18_combout & (\z80_|alu_|db_low[0]~19_combout & ((\z80_|alu_|result_lo [0]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[0]~18_combout ), - .datab(\z80_|alu_|db_low[0]~19_combout ), - .datac(\z80_|alu_|result_lo [0]), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~20 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( -// Equation(s): -// \z80_|alu_|db_low[0]~23_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[0]~22_combout & ((\z80_|alu_|db_low[0]~20_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[0]~20_combout ) # -// (!\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|alu_|db_low[0]~22_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_low[0]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'hAF03; -defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( -// Equation(s): -// \z80_|alu_|db[0]~18_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|alu_|db_low[0]~23_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_|db_low[0]~23_combout ) # ((!\z80_|execute_|ctl_alu_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_|db_low[0]~23_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~18 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|db[0]~19 ( -// Equation(s): -// \z80_|alu_|db[0]~19_combout = ((\z80_|alu_|db[0]~18_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[0]~12_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~19 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( -// Equation(s): -// \z80_|alu_|db_low[1]~15_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~19_combout )) - - .dataa(\z80_|alu_|db[0]~19_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[2]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( -// Equation(s): -// \z80_|alu_|db_low[1]~16_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[1]~15_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[1]~13_combout ))) - - .dataa(\z80_|alu_|db_low[1]~15_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hAAF0; -defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( -// Equation(s): -// \z80_|alu_|db_low[1]~12_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'h5755; -defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~13 ( -// Equation(s): -// \z80_|alu_|db_low[1]~13_combout = (\z80_|alu_|op2_low [1] & (((\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [1] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [1]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [1]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~13 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_low[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N21 -dffeas \z80_|alu_|result_lo[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~14 ( -// Equation(s): -// \z80_|alu_|db_low[1]~14_combout = (\z80_|alu_|db_low[1]~12_combout & (\z80_|alu_|db_low[1]~13_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[1]~12_combout ), - .datab(\z80_|alu_|db_low[1]~13_combout ), - .datac(\z80_|alu_|result_lo [1]), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~14 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( -// Equation(s): -// \z80_|alu_|db_low[1]~17_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~16_combout & \z80_|alu_|db_low[1]~14_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~14_combout )) # -// (!\z80_|alu_|db_high[3]~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|alu_|db_low[1]~16_combout ), - .datad(\z80_|alu_|db_low[1]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'hF511; -defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # -// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N1 -dffeas \z80_|alu_|op1_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N28 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( -// Equation(s): -// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [1]) # (\z80_|alu_|op1_low [2]))) - - .dataa(gnd), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hF0C0; -defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0F00; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N8 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( -// Equation(s): -// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & -// (((\z80_|alu_flags_|flags_hf2~q )))) - - .dataa(\z80_|alu_control_|db[4]~32_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .datac(\z80_|alu_flags_|flags_hf2~q ), - .datad(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hEEF0; -defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N9 -dffeas \z80_|alu_flags_|flags_hf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|flags_hf2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_hf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~23 ( -// Equation(s): -// \z80_|alu_control_|db[2]~23_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|alu_flags_|flags_hf2~q ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~combout ), - .datab(\z80_|alu_control_|out[6]~0_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|alu_flags_|flags_hf2~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~23 .lut_mask = 16'hFFEF; -defparam \z80_|alu_control_|db[2]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[2]~2_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[2]~2 .lut_mask = 16'hFF40; -defparam \z80_|reg_file_|db_lo_ds[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( -// Equation(s): -// \z80_|alu_control_|db[2]~28_combout = (\z80_|reg_file_|db_lo_ds[2]~2_combout & (((\z80_|bus_control_|db[2]~13_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[2]~13_combout ), - .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h2F00; -defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~27 ( -// Equation(s): -// \z80_|alu_control_|db[2]~27_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((!\z80_|alu_|db[2]~15_combout & \z80_|execute_|ctl_sw_2u~7_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (!\z80_|alu_|db[2]~15_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|alu_|db[2]~15_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~27 .lut_mask = 16'h3B0A; -defparam \z80_|alu_control_|db[2]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( -// Equation(s): -// \z80_|alu_control_|db[2]~29_combout = ((\z80_|alu_control_|db[2]~23_combout & (\z80_|alu_control_|db[2]~28_combout & !\z80_|alu_control_|db[2]~27_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[2]~23_combout ), - .datac(\z80_|alu_control_|db[2]~28_combout ), - .datad(\z80_|alu_control_|db[2]~27_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h55D5; -defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db[2]~14 ( -// Equation(s): -// \z80_|alu_|db[2]~14_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[2]~39_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[2]~29_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[2]~29_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~14 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[2]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db[2]~15 ( -// Equation(s): -// \z80_|alu_|db[2]~15_combout = ((\z80_|alu_|db[2]~14_combout & ((\z80_|alu_|db_low[2]~24_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_low[2]~24_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[2]~14_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~15 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[2]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N4 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~2 ( -// Equation(s): -// \z80_|alu_|db_low[2]~2_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[1]~13_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[3]~11_combout ), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~2 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|db_low[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~3 ( -// Equation(s): -// \z80_|alu_|db_low[2]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~15_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[2]~15_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_low[2]~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~3 .lut_mask = 16'hF3BB; -defparam \z80_|alu_|db_low[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_high[3]~3_combout ), - .datac(\z80_|alu_|db_low[2]~3_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .lut_mask = 16'hB300; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'h3222; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N25 -dffeas \z80_|alu_|op1_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ) # ((\z80_|alu_|db_low[2]~24_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), - .datac(\z80_|alu_|db_low[2]~24_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N13 -dffeas \z80_|alu_|op2_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~5 ( -// Equation(s): -// \z80_|alu_|db_low[2]~5_combout = (\z80_|alu_|op2_low [2] & ((\z80_|alu_|op1_low [2]) # ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_low [2] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [2]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [2]), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~5 .lut_mask = 16'h8ACF; -defparam \z80_|alu_|db_low[2]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N13 -dffeas \z80_|alu_|result_lo[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~6 ( -// Equation(s): -// \z80_|alu_|db_low[2]~6_combout = (\z80_|alu_|db_low[2]~4_combout & (\z80_|alu_|db_low[2]~5_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [2])))) - - .dataa(\z80_|alu_|db_low[2]~4_combout ), - .datab(\z80_|alu_|db_low[2]~5_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|result_lo [2]), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~6 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[2]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_low[2]~3_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h80F0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N27 -dffeas \z80_|alu_|op2_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~0 ( -// Equation(s): -// \z80_|alu_|alu_op2[2]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) - - .dataa(\z80_|alu_|op2_high [2]), - .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|alu_|op2_low [2]), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[2]~0 .lut_mask = 16'h4B78; -defparam \z80_|alu_|alu_op2[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h0BFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[2]~2_combout & -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|alu_|alu_op2[2]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[2]~2_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[2]~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .datac(\z80_|alu_|alu_op1[2]~2_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hECC8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( -// Equation(s): -// \z80_|alu_|db_high[2]~9_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'h55D5; -defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( -// Equation(s): -// \z80_|alu_|db_high[2]~11_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~21_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~25_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(\z80_|alu_|db[7]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'hFA50; -defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( -// Equation(s): -// \z80_|alu_|db_high[2]~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[2]~11_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[6]~23_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[2]~11_combout ), - .datac(\z80_|alu_|db[6]~23_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( -// Equation(s): -// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [2]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( -// Equation(s): -// \z80_|alu_|db_high[2]~13_combout = (\z80_|alu_|db_high[2]~9_combout & (\z80_|alu_|db_high[2]~10_combout & ((\z80_|alu_|db_high[2]~12_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[2]~9_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[2]~12_combout ), - .datad(\z80_|alu_|db_high[2]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hA200; -defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~14 ( -// Equation(s): -// \z80_|alu_|db_high[2]~14_combout = ((\z80_|alu_|db_high[2]~13_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .datab(\z80_|alu_|db_high[3]~3_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_high[2]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~14 .lut_mask = 16'hFB33; -defparam \z80_|alu_|db_high[2]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( -// Equation(s): -// \z80_|alu_|db[6]~22_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .datad(\z80_|alu_control_|db[6]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db[6]~23 ( -// Equation(s): -// \z80_|alu_|db[6]~23_combout = ((\z80_|alu_|db[6]~22_combout & ((\z80_|alu_|db_high[2]~14_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_high[2]~14_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~23 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[6]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N10 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( -// Equation(s): -// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_|op1_high [0] & \z80_|alu_control_|out[6]~0_combout ))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|alu_|op1_high [0]), - .datac(\z80_|alu_|op1_high [1]), - .datad(\z80_|alu_control_|out[6]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEFA; -defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N26 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( -// Equation(s): -// \z80_|alu_control_|out[6]~2_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) - - .dataa(\z80_|execute_|ctl_66_oe~combout ), - .datab(\z80_|alu_control_|out[6]~1_combout ), - .datac(\z80_|alu_|op1_high [3]), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFFEA; -defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~19 ( -// Equation(s): -// \z80_|alu_control_|db[6]~19_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & -// (!\z80_|execute_|ctl_flags_oe~2_combout & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|out[6]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~19 .lut_mask = 16'hAF8C; -defparam \z80_|alu_control_|db[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~20 ( -// Equation(s): -// \z80_|alu_control_|db[6]~20_combout = (\z80_|alu_control_|db[6]~19_combout & ((\z80_|alu_|db[6]~23_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db[6]~23_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[6]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~20 .lut_mask = 16'hCF00; -defparam \z80_|alu_control_|db[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( -// Equation(s): -// \z80_|alu_control_|db[6]~21_combout = (\z80_|alu_control_|db[6]~20_combout & (((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[6]~9_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|alu_control_|db[6]~20_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'h30B0; -defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( -// Equation(s): -// \z80_|alu_control_|db[6]~22_combout = ((\z80_|alu_control_|db[6]~21_combout & ((\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[6]~21_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'hD5DD; -defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal33~1_combout & ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .combout(\z80_|execute_|ctl_mRead~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'hC800; -defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( +// Location: LCCOMB_X37_Y6_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( // Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[3]~21_combout ) +// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) - .dataa(gnd), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[3]~21_combout ), + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .combout(\z80_|pla_decode_|Equal77~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h00CC; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0100; +defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y10_N9 -dffeas \z80_|interrupts_|im1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( +// Location: LCCOMB_X37_Y12_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( // Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|interrupts_|im1~q ), - .datac(\z80_|interrupts_|im2~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hDC00; -defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & -// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h40EE; -defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N0 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( -// Equation(s): -// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) +// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout )) .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[0]~4_combout ), + .combout(\z80_|pla_decode_|Equal50~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hFF31; -defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N6 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( +// Location: LCCOMB_X40_Y13_N16 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( // Equation(s): -// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) +// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) - .dataa(gnd), - .datab(\z80_|alu_control_|db[6]~22_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[6]~8_combout ), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~37 ( +// Location: LCCOMB_X30_Y11_N20 +cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( // Equation(s): -// \z80_|execute_|ctl_mRead~37_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|sequencer_|DFFE_T5_ff~q ) +// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|interrupts_|DFFE_inst44~q & !\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~37 .lut_mask = 16'hDDDF; -defparam \z80_|execute_|ctl_mRead~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~37_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~37_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ctl_mRead~28_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~28_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_mRead~29_combout & (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & !\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ))) - - .dataa(\z80_|execute_|ctl_mRead~29_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_mRead~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~37 ( -// Equation(s): -// \z80_|execute_|setM1~37_combout = (!\z80_|pla_decode_|Equal9~1_combout & (!\z80_|pla_decode_|Equal29~0_combout & (\z80_|execute_|ctl_al_we~4_combout & \z80_|execute_|ctl_inc_cy~41_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|execute_|ctl_al_we~4_combout ), - .datad(\z80_|execute_|ctl_inc_cy~41_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~37 .lut_mask = 16'h1000; -defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~55 ( -// Equation(s): -// \z80_|execute_|setM1~55_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~55 .lut_mask = 16'h3233; -defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~38 ( -// Equation(s): -// \z80_|execute_|setM1~38_combout = (!\z80_|execute_|ctl_mRead~16_combout & (\z80_|execute_|setM1~37_combout & (\z80_|execute_|setM1~55_combout & \z80_|execute_|setM1~36_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|setM1~37_combout ), - .datac(\z80_|execute_|setM1~55_combout ), - .datad(\z80_|execute_|setM1~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~38 .lut_mask = 16'h4000; -defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~34_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|setM1~38_combout ))) - - .dataa(\z80_|execute_|setM1~38_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~3 ( -// Equation(s): -// \z80_|execute_|nextM~3_combout = (!\z80_|pla_decode_|Equal41~2_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ixy_d~16_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0003; -defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|nextM~3_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_mRead~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|execute_|ctl_mRead~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFC0; -defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~35 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~35_combout = ((\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|execute_|ctl_mRead~31_combout ) # (\z80_|execute_|ctl_mRead~33_combout ))) # (!\z80_|execute_|ctl_mRead~30_combout ) - - .dataa(\z80_|execute_|ctl_mRead~30_combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|ctl_mRead~31_combout ), - .datad(\z80_|execute_|ctl_mRead~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~35 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_mRead~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N23 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mRead~35_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N24 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X46_Y15_N25 -dffeas \z80_|memory_ifc_|wait_mrd ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mrd~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N3 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_mrd~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N8 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & !\z80_|memory_ifc_|DFFE_mrd_ff3~q ) - - .dataa(\z80_|memory_ifc_|wait_mrd~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0055; -defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|nextM~4 ( -// Equation(s): -// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout ) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~4 .lut_mask = 16'h373F; -defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~12_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_iorw~12_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~11_combout & \z80_|execute_|ctl_mWrite~16_combout ))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|nextM~4_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_iorw~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N7 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_iorw~9_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N26 -cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder ( -// Equation(s): -// \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout = \z80_|memory_ifc_|DFFE_iorq_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N27 -dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N9 -dffeas \z80_|memory_ifc_|wait_iorq ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorq~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N13 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorq~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( -// Equation(s): -// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|wait_iorq~q ), - .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|iorq~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; -defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( -// Equation(s): -// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hA800; -defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( -// Equation(s): -// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_alu_op_low~9_combout ) # ((\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|fIOWrite~0_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|fIORead~1_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFFF2; -defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( -// Equation(s): -// \z80_|execute_|fIORead~0_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hA080; -defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( -// Equation(s): -// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|fIOWrite~1_combout ), - .datab(\z80_|execute_|fIORead~2_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|fIORead~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N25 -dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|setM1~52_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_m1_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N14 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( -// Equation(s): -// \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_m1_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N15 -dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N21 -dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_m1_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N20 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|interrupts_|DFFE_inst44~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # (\z80_|memory_ifc_|DFFE_m1_ff3~q )))) # (!\z80_|interrupts_|DFFE_inst44~q & -// ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # ((\z80_|memory_ifc_|DFFE_m1_ff3~q )))) - - .dataa(\z80_|interrupts_|DFFE_inst44~q ), - .datab(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .datac(\z80_|memory_ifc_|DFFE_m1_ff3~q ), + .datac(\z80_|interrupts_|DFFE_inst44~q ), .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~0_combout ), + .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hFC54; -defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0010; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N18 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~2_combout = ((\z80_|memory_ifc_|nRD_out~0_combout ) # ((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIORead~3_combout ))) # (!\z80_|memory_ifc_|nRD_out~1_combout ) - - .dataa(\z80_|memory_ifc_|nRD_out~1_combout ), - .datab(\z80_|memory_ifc_|iorq~0_combout ), - .datac(\z80_|execute_|fIORead~3_combout ), - .datad(\z80_|memory_ifc_|nRD_out~0_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~2_combout ), - .cout()); +// Location: FF_X30_Y11_N21 +dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .prn(vcc)); // synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hFFD5; -defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N24 -cycloneive_lcell_comb \Equal2~1 ( -// Equation(s): -// \Equal2~1_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~1 .lut_mask = 16'h4040; -defparam \Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~0 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~0 .lut_mask = 16'hFFAA; -defparam \z80_|pin_control_|bus_db_pin_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( -// Equation(s): -// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h3F33; -defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( -// Equation(s): -// \z80_|execute_|fMWrite~6_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) - - .dataa(\z80_|execute_|fMWrite~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'h5554; -defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( -// Equation(s): -// \z80_|execute_|fMWrite~2_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h555F; -defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( -// Equation(s): -// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fMWrite~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|fMWrite~2_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h00EF; -defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~1 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~1_combout = (\z80_|execute_|ctl_bus_inc_oe~24_combout & (!\z80_|execute_|fIOWrite~5_combout & (!\z80_|execute_|fMWrite~6_combout & !\z80_|execute_|fMWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .datab(\z80_|execute_|fIOWrite~5_combout ), - .datac(\z80_|execute_|fMWrite~6_combout ), - .datad(\z80_|execute_|fMWrite~4_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~1 .lut_mask = 16'h0002; -defparam \z80_|pin_control_|bus_db_pin_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'h135F; -defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N24 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|pin_control_|bus_db_pin_oe~2_combout & (((\z80_|execute_|ixy_d~4_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'hA2AA; -defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( -// Equation(s): -// \z80_|execute_|fMWrite~7_combout = (!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_mRead~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'h0003; -defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~7_combout ) # ((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|fMWrite~7_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'hCD00; -defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~10_combout & ((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h0777; -defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N4 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|fMRead~1_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout )) # -// (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|fMRead~1_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h3715; -defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|fMWrite~9 ( -// Equation(s): -// \z80_|execute_|fMWrite~9_combout = (\z80_|pla_decode_|Equal46~0_combout ) # (((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout )) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~9 .lut_mask = 16'hCEFF; -defparam \z80_|execute_|fMWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|execute_|fIOWrite~0_combout & ((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) # (!\z80_|execute_|ctl_mWrite~6_combout & -// (((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|fMWrite~2_combout ), - .datad(\z80_|execute_|fMWrite~9_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'hDDD0; -defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N0 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (\z80_|execute_|fMWrite~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout )) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .datab(\z80_|execute_|fMWrite~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h0808; -defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( -// Equation(s): -// \z80_|execute_|fMWrite~8_combout = (\z80_|execute_|ctl_state_alu~6_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & (\z80_|execute_|ctl_reg_sel_wz~5_combout & (!\z80_|execute_|fMWrite~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .datac(\z80_|execute_|fMWrite~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h0800; -defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|pin_control_|bus_db_pin_oe~7_combout & (\z80_|pin_control_|bus_db_pin_oe~6_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~5_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|fMWrite~10 ( -// Equation(s): -// \z80_|execute_|fMWrite~10_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|execute_|ctl_alu_oe~2_combout & -// ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~10 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N0 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|pin_control_|bus_db_pin_oe~10_combout & (!\z80_|execute_|fMWrite~10_combout & \z80_|execute_|ctl_bus_inc_oe~28_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .datac(\z80_|execute_|fMWrite~10_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h0800; -defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~3_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h2A00; -defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (\z80_|pin_control_|bus_db_pin_oe~1_combout & (\z80_|pin_control_|bus_db_pin_oe~12_combout & \z80_|execute_|ctl_inc_cy~37_combout ))) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .datad(\z80_|execute_|ctl_inc_cy~37_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N28 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout ))) # -// (!\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|fIOWrite~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'hF222; -defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N0 +// Location: LCCOMB_X39_Y14_N26 cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( // Equation(s): // \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q @@ -37040,7 +6633,7 @@ defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y15_N1 +// Location: FF_X39_Y14_N27 dffeas \z80_|clk_delay_|DFF_inst5 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), @@ -37059,3754 +6652,96 @@ defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y15_N22 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorqinta~feeder ( +// Location: LCCOMB_X39_Y14_N4 +cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( // Equation(s): -// \z80_|memory_ifc_|wait_iorqinta~feeder_combout = \z80_|clk_delay_|DFF_inst5~q +// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|DFF_inst5~q & !\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ) - .dataa(gnd), + .dataa(\z80_|clk_delay_|DFF_inst5~q ), .datab(gnd), .datac(gnd), - .datad(\z80_|clk_delay_|DFF_inst5~q ), + .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), .cin(gnd), - .combout(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), + .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .sum_lutc_input = "datac"; +defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0055; +defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y15_N23 -dffeas \z80_|memory_ifc_|wait_iorqinta ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), +// Location: FF_X40_Y13_N17 +dffeas \z80_|sequencer_|DFFE_T5_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorqinta~q ), + .q(\z80_|sequencer_|DFFE_T5_ff~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; +defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; // synopsys translate_on -// Location: FF_X43_Y15_N13 -dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Location: LCCOMB_X32_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( // Equation(s): -// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|wait_iorqinta~q ) # ((\z80_|memory_ifc_|DFFE_intr_ff3~q ) # (\z80_|memory_ifc_|iorq~0_combout )) +// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) - .dataa(\z80_|memory_ifc_|wait_iorqinta~q ), - .datab(gnd), - .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .datad(\z80_|memory_ifc_|iorq~0_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFFFA; -defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N18 -cycloneive_lcell_comb \Equal2~0 ( -// Equation(s): -// \Equal2~0_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~0 .lut_mask = 16'h4000; -defparam \Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N22 -cycloneive_lcell_comb \ExtRamWE~0 ( -// Equation(s): -// \ExtRamWE~0_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\ExtRamWE~0_combout ), - .cout()); -// synopsys translate_off -defparam \ExtRamWE~0 .lut_mask = 16'h0020; -defparam \ExtRamWE~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [13]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [13]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|ixy_d~15_combout ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), + .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h0B0B; -defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N28 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~2_combout = (((\z80_|execute_|fMRead~35_combout ) # (\z80_|execute_|fIORead~3_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .datac(\z80_|execute_|fMRead~35_combout ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFFF7; -defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N2 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pin_control_|bus_ab_pin_we~2_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T3_ff~q & -// (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pin_control_|bus_ab_pin_we~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h3B0A; -defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .asdata(\z80_|address_latch_|Q [13]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[13]~20 ( -// Equation(s): -// \z80_|address_pins_|abus[13]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[13]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[13]~20 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[13]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [14])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [14]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [14]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .asdata(\z80_|address_latch_|Q [14]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N4 -cycloneive_lcell_comb \z80_|address_pins_|abus[14]~23 ( -// Equation(s): -// \z80_|address_pins_|abus[14]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[14]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[14]~23 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[14]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [15]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .asdata(\z80_|address_latch_|Q [15]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N12 -cycloneive_lcell_comb \z80_|address_pins_|abus[15]~22 ( -// Equation(s): -// \z80_|address_pins_|abus[15]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[15]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[15]~22 .lut_mask = 16'hF3F3; -defparam \z80_|address_pins_|abus[15]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h0800; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00C0; -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( -// Equation(s): -// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [1]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [1]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .asdata(\z80_|address_latch_|Q [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( -// Equation(s): -// \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [1]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [2]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .asdata(\z80_|address_latch_|Q [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N26 -cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( -// Equation(s): -// \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [2]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[2]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N0 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [3])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [3]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N1 -dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .asdata(\z80_|address_latch_|Q [3]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N12 -cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( -// Equation(s): -// \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [3]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[3]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N30 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [4])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [4]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N31 -dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .asdata(\z80_|address_latch_|Q [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N2 -cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( -// Equation(s): -// \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [4]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[4]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N12 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [5]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N13 -dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .asdata(\z80_|address_latch_|Q [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( -// Equation(s): -// \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[5]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hF3F3; -defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [6])) - - .dataa(\z80_|address_latch_|abusz [6]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .asdata(\z80_|address_latch_|Q [6]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N28 -cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( -// Equation(s): -// \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [6]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[6]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hCFCF; -defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N30 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [7]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N31 -dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .asdata(\z80_|address_latch_|Q [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N22 -cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( -// Equation(s): -// \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [7]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[7]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N20 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [8])) - - .dataa(\z80_|address_latch_|abusz [8]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N21 -dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .asdata(\z80_|address_latch_|Q [8]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N30 -cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( -// Equation(s): -// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [8]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[8]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N16 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [9]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [9]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N17 -dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .asdata(\z80_|address_latch_|Q [9]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N4 -cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( -// Equation(s): -// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [9]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[9]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N24 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [10]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .datab(\z80_|address_latch_|abusz [10]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N25 -dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .asdata(\z80_|address_latch_|Q [10]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N24 -cycloneive_lcell_comb \z80_|address_pins_|abus[10]~24 ( -// Equation(s): -// \z80_|address_pins_|abus[10]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [10]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[10]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[10]~24 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[10]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N6 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datab(\z80_|address_latch_|abusz [11]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N7 -dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .asdata(\z80_|address_latch_|Q [11]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( -// Equation(s): -// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [11]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[11]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N16 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [12])) - - .dataa(\z80_|address_latch_|abusz [12]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N17 -dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .asdata(\z80_|address_latch_|Q [12]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N30 -cycloneive_lcell_comb \z80_|address_pins_|abus[12]~21 ( -// Equation(s): -// \z80_|address_pins_|abus[12]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [12]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[12]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[12]~21 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[12]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y11_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X32_Y14_N31 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[13]~20_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X32_Y14_N1 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N12 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0200; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N18 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h000C; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: FF_X29_Y14_N5 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[14]~23_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N21 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N24 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h2000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N26 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h0C00; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N10 -cycloneive_lcell_comb \D[6]~90 ( -// Equation(s): -// \D[6]~90_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .cin(gnd), - .combout(\D[6]~90_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~90 .lut_mask = 16'hCCE2; -defparam \D[6]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N20 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hF333; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N16 -cycloneive_lcell_comb \D[6]~91 ( -// Equation(s): -// \D[6]~91_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~90_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ))) # (!\D[6]~90_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~90_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[6]~90_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), - .cin(gnd), - .combout(\D[6]~91_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~91 .lut_mask = 16'hF838; -defparam \D[6]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N2 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h0020; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G15 -cycloneive_clkctrl \CLOCK_50~inputclkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\CLOCK_50~inputclkctrl_outclk )); -// synopsys translate_off -defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; -defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y24_N16 -cycloneive_lcell_comb \~GND ( -// Equation(s): -// \~GND~combout = GND - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\~GND~combout ), - .cout()); -// synopsys translate_off -defparam \~GND .lut_mask = 16'h0000; -defparam \~GND .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vram_address[0]~feeder ( -// Equation(s): -// \ula_|video_|vram_address[0]~feeder_combout = \ula_|video_|vga_hc [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [4]), - .cin(gnd), - .combout(\ula_|video_|vram_address[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vram_address[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N4 -cycloneive_lcell_comb \ula_|video_|vram_address~0 ( -// Equation(s): -// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N21 -dffeas \ula_|video_|vram_address[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X34_Y33_N19 -dffeas \ula_|video_|vram_address[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N0 -cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( -// Equation(s): -// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|video_|vram_address[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; -defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N1 -dffeas \ula_|video_|vram_address[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N26 -cycloneive_lcell_comb \ula_|video_|Add3~0 ( -// Equation(s): -// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|Add3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N27 -dffeas \ula_|video_|vram_address[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N28 -cycloneive_lcell_comb \ula_|video_|Add3~1 ( -// Equation(s): -// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) - - .dataa(\ula_|video_|vga_hc [6]), - .datab(gnd), - .datac(\ula_|video_|vga_hc [8]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|Add3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~1 .lut_mask = 16'hA50F; -defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N29 -dffeas \ula_|video_|vram_address[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N2 -cycloneive_lcell_comb \ula_|video_|Add4~0 ( -// Equation(s): -// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) -// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) - - .dataa(\ula_|video_|vga_vc [0]), - .datab(\ula_|video_|vga_vc [1]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add4~0_combout ), - .cout(\ula_|video_|Add4~1 )); -// synopsys translate_off -defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; -defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Add4~2 ( -// Equation(s): -// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) -// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~1 ), - .combout(\ula_|video_|Add4~2_combout ), - .cout(\ula_|video_|Add4~3 )); -// synopsys translate_off -defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; -defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N6 -cycloneive_lcell_comb \ula_|video_|Add4~4 ( -// Equation(s): -// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) -// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~3 ), - .combout(\ula_|video_|Add4~4_combout ), - .cout(\ula_|video_|Add4~5 )); -// synopsys translate_off -defparam \ula_|video_|Add4~4 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N8 -cycloneive_lcell_comb \ula_|video_|Add4~6 ( -// Equation(s): -// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) -// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~5 ), - .combout(\ula_|video_|Add4~6_combout ), - .cout(\ula_|video_|Add4~7 )); -// synopsys translate_off -defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N9 -dffeas \ula_|video_|vram_address[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N10 -cycloneive_lcell_comb \ula_|video_|Add4~8 ( -// Equation(s): -// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) -// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~7 ), - .combout(\ula_|video_|Add4~8_combout ), - .cout(\ula_|video_|Add4~9 )); -// synopsys translate_off -defparam \ula_|video_|Add4~8 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N11 -dffeas \ula_|video_|vram_address[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N12 -cycloneive_lcell_comb \ula_|video_|Add4~10 ( -// Equation(s): -// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) -// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~9 ), - .combout(\ula_|video_|Add4~10_combout ), - .cout(\ula_|video_|Add4~11 )); -// synopsys translate_off -defparam \ula_|video_|Add4~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N13 -dffeas \ula_|video_|vram_address[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Add4~12 ( -// Equation(s): -// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) -// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~11 ), - .combout(\ula_|video_|Add4~12_combout ), - .cout(\ula_|video_|Add4~13 )); -// synopsys translate_off -defparam \ula_|video_|Add4~12 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N22 -cycloneive_lcell_comb \ula_|video_|Selector6~0 ( -// Equation(s): -// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~12_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~0_combout ))) - - .dataa(gnd), - .datab(\ula_|video_|Add4~12_combout ), - .datac(\ula_|video_|Add4~0_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector6~0 .lut_mask = 16'hCCF0; -defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N14 -cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( -// Equation(s): -// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address[9]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N23 -dffeas \ula_|video_|vram_address[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector6~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add4~14 ( -// Equation(s): -// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_vc [8]), - .cin(\ula_|video_|Add4~13 ), - .combout(\ula_|video_|Add4~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; -defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N20 -cycloneive_lcell_comb \ula_|video_|Selector5~0 ( -// Equation(s): -// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) - - .dataa(\ula_|video_|Add4~14_combout ), - .datab(gnd), - .datac(\ula_|video_|Add4~2_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector5~0 .lut_mask = 16'hAAF0; -defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N21 -dffeas \ula_|video_|vram_address[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector5~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N28 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( -// Equation(s): -// \ula_|video_|vram_address[10]~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N30 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( -// Equation(s): -// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & (\ula_|video_|vga_hc [1]))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) - - .dataa(\ula_|video_|Add4~4_combout ), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vram_address [10]), - .datad(\ula_|video_|vram_address[10]~2_combout ), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'h88F0; -defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N31 -dffeas \ula_|video_|vram_address[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[10]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N16 -cycloneive_lcell_comb \ula_|video_|Selector3~0 ( -// Equation(s): -// \ula_|video_|Selector3~0_combout = (\ula_|video_|Add4~12_combout ) # (\ula_|video_|vga_hc [2]) - - .dataa(gnd), - .datab(\ula_|video_|Add4~12_combout ), - .datac(gnd), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFCC; -defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N17 -dffeas \ula_|video_|vram_address[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N26 -cycloneive_lcell_comb \ula_|video_|Selector2~0 ( -// Equation(s): -// \ula_|video_|Selector2~0_combout = (\ula_|video_|Add4~14_combout ) # (\ula_|video_|vga_hc [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Add4~14_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFFF0; -defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N27 -dffeas \ula_|video_|vram_address[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[12] .power_up = "low"; -// synopsys translate_on - -// Location: M9K_X33_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N22 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|abus[13]~20_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N23 -dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y14_N1 -dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(gnd), - .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N10 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h0080; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y33_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N2 -cycloneive_lcell_comb \D[6]~87 ( -// Equation(s): -// \D[6]~87_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .cin(gnd), - .combout(\D[6]~87_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~87 .lut_mask = 16'hE6A2; -defparam \D[6]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y1_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N6 -cycloneive_lcell_comb \D[6]~88 ( -// Equation(s): -// \D[6]~88_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ (((\D[6]~87_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~87_combout )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datad(\D[6]~87_combout ), - .cin(gnd), - .combout(\D[6]~88_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~88 .lut_mask = 16'h22D8; -defparam \D[6]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N20 -cycloneive_lcell_comb \D[6]~89 ( -// Equation(s): -// \D[6]~89_combout = (\D[6]~87_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~88_combout )))) # (!\D[6]~87_combout & -// (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \D[6]~88_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datab(\D[6]~87_combout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\D[6]~88_combout ), - .cin(gnd), - .combout(\D[6]~89_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~89 .lut_mask = 16'hC3C8; -defparam \D[6]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N14 -cycloneive_lcell_comb \D[6]~111 ( -// Equation(s): -// \D[6]~111_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\D[6]~91_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\D[6]~89_combout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[6]~91_combout )) - - .dataa(\D[6]~91_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\D[6]~89_combout ), - .cin(gnd), - .combout(\D[6]~111_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~111 .lut_mask = 16'hAEA2; -defparam \D[6]~111 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X16_Y34_N8 -cycloneive_io_ibuf \raw_loader_in~input ( - .i(raw_loader_in), - .ibar(gnd), - .o(\raw_loader_in~input_o )); -// synopsys translate_off -defparam \raw_loader_in~input .bus_hold = "false"; -defparam \raw_loader_in~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N18 -cycloneive_lcell_comb \D[6]~86 ( -// Equation(s): -// \D[6]~86_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(gnd), - .datac(\raw_loader_in~input_o ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\D[6]~86_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~86 .lut_mask = 16'hFAFF; -defparam \D[6]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N28 -cycloneive_lcell_comb \D[6]~100 ( -// Equation(s): -// \D[6]~100_combout = ((\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout ))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~1_combout ), - .datab(\Equal2~0_combout ), - .datac(\D[6]~111_combout ), - .datad(\D[6]~86_combout ), - .cin(gnd), - .combout(\D[6]~100_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~100 .lut_mask = 16'hFD75; -defparam \D[6]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N4 -cycloneive_lcell_comb \D[6]~101 ( -// Equation(s): -// \D[6]~101_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [6] & \D[6]~100_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[6]~100_combout )) # (!\Equal2~1_combout ))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[6]~100_combout ), - .cin(gnd), - .combout(\D[6]~101_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~101 .lut_mask = 16'hCF05; -defparam \D[6]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N12 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[6]~101_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\D[6]~101_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[6]~9_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|fIORead~3_combout )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # -// ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|fIORead~3_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hDC50; -defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N16 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|execute_|fMRead~35_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEA; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N13 -dffeas \z80_|data_pins_|dout[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N16 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( -// Equation(s): -// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[6]~8_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|execute_|ctl_bus_db_oe~combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'h8AFF; -defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N8 -cycloneive_lcell_comb \z80_|ir_|opcode[6]~feeder ( -// Equation(s): -// \z80_|ir_|opcode[6]~feeder_combout = \z80_|bus_control_|db[6]~9_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[6]~9_combout ), - .cin(gnd), - .combout(\z80_|ir_|opcode[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|ir_|opcode[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|ir_|opcode[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_ir_we~5_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N9 -dffeas \z80_|ir_|opcode[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|ir_|opcode[6]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~1_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~2_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~1_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|pla_decode_|Equal41~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal41~2_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFF08; -defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( -// Equation(s): -// \z80_|alu_|db_high[1]~15_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'h7555; -defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( -// Equation(s): -// \z80_|alu_|db_high[1]~16_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [1]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [1]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( -// Equation(s): -// \z80_|alu_|db_high[1]~17_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~23_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~17_combout ))) - - .dataa(\z80_|alu_|db[6]~23_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[4]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hAFA0; -defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( -// Equation(s): -// \z80_|alu_|db_high[1]~18_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[1]~17_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[5]~25_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[1]~17_combout ), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( -// Equation(s): -// \z80_|alu_|db_high[1]~19_combout = (\z80_|alu_|db_high[1]~15_combout & (\z80_|alu_|db_high[1]~16_combout & ((\z80_|alu_|db_high[1]~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[1]~15_combout ), - .datab(\z80_|alu_|db_high[1]~16_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[1]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~20 ( -// Equation(s): -// \z80_|alu_|db_high[1]~20_combout = ((\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~20 .lut_mask = 16'hA8FF; -defparam \z80_|alu_|db_high[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( -// Equation(s): -// \z80_|alu_|db[5]~24_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[5]~15_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_control_|db[5]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db[5]~25 ( -// Equation(s): -// \z80_|alu_|db[5]~25_combout = ((\z80_|alu_|db[5]~24_combout & ((\z80_|alu_|db_high[1]~20_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_high[1]~20_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db[5]~24_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~25 .lut_mask = 16'hB3F3; -defparam \z80_|alu_|db[5]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N14 -cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( -// Equation(s): -// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_1d~6_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[5]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hEFCC; -defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_control_|db[5]~15_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|alu_control_|db[5]~15_combout -// & (\z80_|alu_|db_high[1]~20_combout & ((\z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|alu_control_|db[5]~15_combout ), - .datab(\z80_|alu_|db_high[1]~20_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hECA0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N23 -dffeas \z80_|alu_flags_|flags_yf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_yf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_yf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~13 ( -// Equation(s): -// \z80_|alu_control_|db[5]~13_combout = (\z80_|alu_flags_|flags_yf~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|flags_yf~q & (!\z80_|execute_|ctl_flags_oe~2_combout & -// ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) - - .dataa(\z80_|alu_flags_|flags_yf~q ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|out[6]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~13 .lut_mask = 16'hAF8C; -defparam \z80_|alu_control_|db[5]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~14 ( -// Equation(s): -// \z80_|alu_control_|db[5]~14_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~13_combout & ((\z80_|reg_file_|gdfx_temp0[5]~72_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|sw1_|db_down[5]~0_combout ), - .datab(\z80_|alu_control_|db[5]~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~14 .lut_mask = 16'h8088; -defparam \z80_|alu_control_|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( -// Equation(s): -// \z80_|alu_control_|db[5]~15_combout = ((\z80_|alu_control_|db[5]~14_combout & ((\z80_|alu_|db[5]~25_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_|db[5]~25_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[5]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hDF55; -defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N10 -cycloneive_lcell_comb \D[0]~107 ( -// Equation(s): -// \D[0]~107_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout ) # ((!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nRD_out~2_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|memory_ifc_|nRD_out~2_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[0]~107_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~107 .lut_mask = 16'hFF40; -defparam \D[0]~107 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y9_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: M9K_X22_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .lut_mask = 16'hDC98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y23_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hF838; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y29_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; -// synopsys translate_on - -// Location: M9K_X33_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'hE10F8B8C100323720BEBBDEBB81DF13FF97B252E2CB4F27BA091FBD0002D1A611E1EDBBC716D44D2912B80041C44558060CFCF15955C0D780DD5E71393920844F25E16C87C5D0308EEC52C011514BBC13AFA1028924D0C7CE738105BD47A10AA5B5C1D9D4193E4339F492B0E1A64E13AE35BE6B67AC8057BDACC155F14E906A017A1841358335450D4B26CD2A21B3D8F2211080B81EC040D7FA0B51CD48008112508062020A02490900092D2040259108806A328F4006D2AA514B42FB006ECCCCB9A360865678449975A8AE72B5C0F7BA800C1B5DC55D7D6FE2EF4EED85D00AB111821321BA426A4FE4956B43595832C271E83E060341AE5F2023FC808177383; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h1A2955372D510AC266A5445146E27000020C320FAE1557E37154040A13202DC6F40B840FB9A59B6DBB296562CB6220EFBE99D2776A202044D9101006FD221D305519198C859000004012AFF4FB060307C92BB732203BFDFEFFFFFFDFFF87FCFFFBFFEFF03FFE0FFFBFAFE0FF80787FFF7FFF83F7F87003FFBFFFFBFFFBFF0FFC0FF81FFF7FFBFFDFFFBFFFE1FF0086F3141AAB6005810A0621595A893F9D85983B9254954341968BAC8C141C90938C05B2C9CD267E11650407375FEDD6A2FEB346AAF6CFDC0791AA97B741995A3B3981E06D1A44D3711955197BB9910FCA20744915C84D6C24BAF53929814CA8A4697E8F4201145AE7415DC122A5F010436107; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h02E84F969E3C800AC610D276182020227809001A50DDDBA3487BB6AE802BA06509312DA0E620656EAF24D57C08FFB14D289613DC32083803B84DC6415FD5EDC000300A8D128FA20030ACCBAFA237B7024504D36A4BA26081137F059E78991154FE2AC2A884A8CC7FBBB21C851CC92B12E15593C0C020FFEE066558590E882D5B67459F1A8C3240FE4E6A8D028C0C088FCF471D400A19B38211004DD122212288B111114514CB11840E04828849C621392041163C00808C67223422F00110201DD18FCFFFF3FFE7F9FFFFFFF82C0B422D214711E08904524A069491774E663F48F665955B4E2C63DAC0078652D10120900298F7EE380092442AFD400BEC43C003; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; -// synopsys translate_on - -// Location: M9K_X33_Y29_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80000001C000000160F000FF70C0007F78C00000F05001007870010010000000000800000038000000F000000070000000300000006000000000000040000000F00000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000001D108000BEDA9FA9698A000000000000000000000000FFFFFFFF408102048004188297E014DA9FA9E9CA00000000000000000000000000000000FFFFFFFC800400CA972208DA9FA9CD8E00000000000000000000000000000000FFFFFFFC8004046A97A289FA9FA9CDC20000000000000000000000007FFFFFFC8000000280040E2A97A2997A9DA9CFC20000000000000000000000007FFFFFFE8000000280042EB28002BE369DA9274200000000000000000000000040810206BFFFFFFE9FE430A29D82AC3E8009E34A000000000000000000000000000000023FFFFFFC9FE4B1829FA2800E8009436A; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h9FE8334E88F827C697F88D1600A80A44809E8FC2B86999C2B85B3A82B1D32A869FE8336A88F807CA97F88F96A0A80EC2838E8D42B9E98FC2B86B3B82B0D7B2D2800832E288F827CA97F88B82A0080EC683869542B939B8C2B1AB0F8290B730C2800826EA8878078297F88AD2A0280EC283E694C2B83A3BC2A3AB3E8291A316AA800826EE881807C69DE8ABD6A0280BC282209CD2BA2A3D42A2737F82918314E2800806E6981805C69D48AED6A1E80BCA82709FC2BB223DC2A07B7F8295DF11C2800886E6980805869848AAC6A1E42DC281789DC2BBAA3DC6A02B7582955F00928008A6EE98082D9618088AC8A0F40FC289E89DC2BBCA3DC2A18B7782154F02F0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N0 -cycloneive_lcell_comb \Mux2~0 ( -// Equation(s): -// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .cin(gnd), - .combout(\Mux2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Mux2~0 .lut_mask = 16'hBA98; -defparam \Mux2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N2 -cycloneive_lcell_comb \Mux2~1 ( -// Equation(s): -// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datad(\Mux2~0_combout ), - .cin(gnd), - .combout(\Mux2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Mux2~1 .lut_mask = 16'hBBC0; -defparam \Mux2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N20 -cycloneive_lcell_comb \D[5]~110 ( -// Equation(s): -// \D[5]~110_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux2~1_combout ))))) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) - - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\Mux2~1_combout ), - .cin(gnd), - .combout(\D[5]~110_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~110 .lut_mask = 16'hAEA2; -defparam \D[5]~110 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N28 -cycloneive_lcell_comb \D[5]~85 ( -// Equation(s): -// \D[5]~85_combout = (\D[5]~84_combout & (\D[5]~110_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & (((\z80_|data_pins_|dout [5])) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout ))) - - .dataa(\D[5]~84_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\z80_|data_pins_|dout [5]), - .datad(\D[5]~110_combout ), - .cin(gnd), - .combout(\D[5]~85_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~85 .lut_mask = 16'hF351; -defparam \D[5]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N24 -cycloneive_lcell_comb \D[5]~99 ( -// Equation(s): -// \D[5]~99_combout = (\D[5]~85_combout ) # (!\D[0]~107_combout ) - - .dataa(\D[0]~107_combout ), - .datab(gnd), - .datac(gnd), - .datad(\D[5]~85_combout ), - .cin(gnd), - .combout(\D[5]~99_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~99 .lut_mask = 16'hFF55; -defparam \D[5]~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N14 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[5]~15_combout ) # ((\D[5]~99_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[5]~99_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[5]~99_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N15 -dffeas \z80_|data_pins_|dout[5] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( -// Equation(s): -// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|data_pins_|dout [5]), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hF300; -defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( -// Equation(s): -// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|alu_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[5]~14_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[5]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hF755; -defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N13 -dffeas \z80_|ir_|opcode[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[5]~15_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N20 +// Location: LCCOMB_X37_Y7_N24 cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( // Equation(s): -// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|ir_|opcode [5] & -// ((\z80_|pla_decode_|Equal3~2_combout )))) +// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|ir_|opcode [5] & +// \z80_|pla_decode_|Equal3~2_combout )))) - .dataa(\z80_|ir_|opcode [5]), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|pla_decode_|Equal3~2_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~2_combout ), .cin(gnd), .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h3350; +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2722; defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y15_N21 +// Location: LCCOMB_X37_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T2_ff~q & +// (((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hF222; +defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y7_N25 dffeas \z80_|decode_state_|DFFE_inst4 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), @@ -40825,7174 +6760,2555 @@ defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y18_N4 -cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( +// Location: LCCOMB_X37_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( // Equation(s): -// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q ) +// \z80_|execute_|fMWrite~3_combout = (!\z80_|execute_|ctl_mRead~5_combout & (((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )) # (!\z80_|pla_decode_|Equal50~0_combout ))) - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(gnd), + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|pla_decode_|Equal50~0_combout ), .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(gnd), + .datad(\z80_|decode_state_|DFFE_inst4~q ), .cin(gnd), - .combout(\z80_|decode_state_|use_ixiy~combout ), + .combout(\z80_|execute_|fMWrite~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFAFA; -defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h5551; +defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( +// Location: LCCOMB_X40_Y13_N0 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( // Equation(s): -// \z80_|execute_|ctl_mRead~23_combout = (!\z80_|decode_state_|use_ixiy~combout & (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) +// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~23_combout ), + .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88C0; +defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( -// Equation(s): -// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMWrite~3_combout )) - - .dataa(\z80_|execute_|ctl_mRead~23_combout ), - .datab(\z80_|execute_|fMWrite~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( -// Equation(s): -// \z80_|execute_|fMRead~31_combout = (\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|pla_decode_|Equal33~3_combout ) # (\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( -// Equation(s): -// \z80_|execute_|fMRead~29_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((\z80_|ir_|opcode [6]) # (\z80_|ir_|opcode [7])))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC800; -defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( -// Equation(s): -// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~9_combout ) # ((\z80_|execute_|fMRead~29_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|fMRead~29_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( -// Equation(s): -// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|nextM~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( -// Equation(s): -// \z80_|execute_|fMRead~32_combout = ((\z80_|execute_|fMRead~31_combout ) # ((\z80_|execute_|fMRead~30_combout ) # (\z80_|execute_|fMRead~28_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .datab(\z80_|execute_|fMRead~31_combout ), - .datac(\z80_|execute_|fMRead~30_combout ), - .datad(\z80_|execute_|fMRead~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (\z80_|execute_|ctl_inc_cy~77_combout & \z80_|execute_|ctl_inc_cy~53_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datab(\z80_|execute_|ctl_inc_cy~77_combout ), - .datac(\z80_|execute_|ctl_inc_cy~53_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( -// Equation(s): -// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_mRead~23_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_ir_we~12_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~23_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( -// Equation(s): -// \z80_|execute_|fMRead~10_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0100; -defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( -// Equation(s): -// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|pc_inc_hold~28_combout )) - - .dataa(\z80_|execute_|ctl_mRead~23_combout ), - .datab(\z80_|execute_|pc_inc_hold~28_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|nextM~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~9 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( -// Equation(s): -// \z80_|execute_|fMRead~11_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|fMRead~9_combout )) # (!\z80_|execute_|fMRead~10_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|fMRead~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|fMRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hAAA2; -defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( -// Equation(s): -// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~12 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( -// Equation(s): -// \z80_|execute_|fMRead~13_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|fMRead~12_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|ctl_mRead~6_combout )))) - - .dataa(\z80_|execute_|fMRead~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|fMWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~13 .lut_mask = 16'h00FE; -defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( -// Equation(s): -// \z80_|execute_|fMRead~15_combout = (\z80_|execute_|fMRead~11_combout ) # ((\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|fMRead~14_combout ), - .datab(\z80_|execute_|fMRead~11_combout ), - .datac(\z80_|execute_|fMRead~13_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~15 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( -// Equation(s): -// \z80_|execute_|fMRead~20_combout = (((\z80_|execute_|fMRead~15_combout ) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|fMRead~19_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .datab(\z80_|execute_|fMRead~19_combout ), - .datac(\z80_|execute_|fMRead~15_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~20 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~48 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~48_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~48 .lut_mask = 16'hE0C0; -defparam \z80_|execute_|pc_inc_hold~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( -// Equation(s): -// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_mRead~17_combout & (\z80_|execute_|ctl_mRead~18_combout & -// ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( -// Equation(s): -// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|fMRead~2_combout ))) - - .dataa(\z80_|execute_|fMRead~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|fMRead~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~21 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( -// Equation(s): -// \z80_|execute_|fMRead~23_combout = ((\z80_|execute_|pc_inc_hold~48_combout ) # ((\z80_|execute_|fMRead~22_combout ) # (\z80_|execute_|fMRead~21_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|pc_inc_hold~48_combout ), - .datac(\z80_|execute_|fMRead~22_combout ), - .datad(\z80_|execute_|fMRead~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( -// Equation(s): -// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~26 .lut_mask = 16'hCCEC; -defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( -// Equation(s): -// \z80_|execute_|fMRead~25_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ctl_mRead~14_combout ))) # (!\z80_|execute_|fMRead~24_combout ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|fMRead~24_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~25 .lut_mask = 16'h2F0F; -defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( -// Equation(s): -// \z80_|execute_|fMRead~27_combout = ((\z80_|execute_|fMRead~25_combout ) # ((\z80_|execute_|fMRead~26_combout & \z80_|execute_|ctl_ir_we~4_combout ))) # (!\z80_|execute_|fMRead~3_combout ) - - .dataa(\z80_|execute_|fMRead~26_combout ), - .datab(\z80_|execute_|fMRead~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|fMRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~27 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( -// Equation(s): -// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~32_combout ) # ((\z80_|execute_|fMRead~20_combout ) # ((\z80_|execute_|fMRead~23_combout ) # (\z80_|execute_|fMRead~27_combout ))) - - .dataa(\z80_|execute_|fMRead~32_combout ), - .datab(\z80_|execute_|fMRead~20_combout ), - .datac(\z80_|execute_|fMRead~23_combout ), - .datad(\z80_|execute_|fMRead~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( -// Equation(s): -// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((\z80_|execute_|fMRead~34_combout & !\z80_|execute_|fMRead~0_combout ))) - - .dataa(\z80_|execute_|fMRead~34_combout ), - .datab(\z80_|execute_|fMRead~33_combout ), - .datac(\z80_|execute_|fMRead~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFFCE; -defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(gnd), - .datab(\z80_|execute_|fMRead~35_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFC0; -defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: M9K_X33_Y18_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N28 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .lut_mask = 16'hDC98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y19_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y20_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N16 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout )) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hEC64; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y24_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y32_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; -// synopsys translate_on - -// Location: M9K_X33_Y21_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; -// synopsys translate_on - -// Location: M9K_X33_Y22_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X32_Y18_N0 -cycloneive_lcell_comb \Selector1~0 ( -// Equation(s): -// \Selector1~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .cin(gnd), - .combout(\Selector1~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector1~0 .lut_mask = 16'hBA98; -defparam \Selector1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y18_N2 -cycloneive_lcell_comb \Selector1~1 ( -// Equation(s): -// \Selector1~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector1~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector1~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector1~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datad(\Selector1~0_combout ), - .cin(gnd), - .combout(\Selector1~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector1~1 .lut_mask = 16'hBBC0; -defparam \Selector1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y18_N12 -cycloneive_lcell_comb \D[1]~103 ( -// Equation(s): -// \D[1]~103_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Selector1~1_combout -// ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), - .datad(\Selector1~1_combout ), - .cin(gnd), - .combout(\D[1]~103_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~103 .lut_mask = 16'hF2D0; -defparam \D[1]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X18_Y34_N1 -cycloneive_io_ibuf \PS2_DAT~input ( - .i(PS2_DAT), - .ibar(gnd), - .o(\PS2_DAT~input_o )); -// synopsys translate_off -defparam \PS2_DAT~input .bus_hold = "false"; -defparam \PS2_DAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: CLKCTRL_G5 -cycloneive_clkctrl \reset~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\reset~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\reset~clkctrl_outclk )); -// synopsys translate_off -defparam \reset~clkctrl .clock_type = "global clock"; -defparam \reset~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [2])) # (!\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [0]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; -defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X9_Y34_N8 -cycloneive_io_ibuf \PS2_CLK~input ( - .i(PS2_CLK), - .ibar(gnd), - .o(\PS2_CLK~input_o )); -// synopsys translate_off -defparam \PS2_CLK~input .bus_hold = "false"; -defparam \PS2_CLK~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\PS2_CLK~input_o ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N1 -dffeas \ula_|ps2_keyboard_|clk_filter[7] ( +// Location: FF_X40_Y13_N1 +dffeas \z80_|sequencer_|DFFE_M4_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [7]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N7 -dffeas \ula_|ps2_keyboard_|clk_filter[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N20 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N21 -dffeas \ula_|ps2_keyboard_|clk_filter[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N18 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N19 -dffeas \ula_|ps2_keyboard_|clk_filter[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [6] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [5] & !\ula_|ps2_keyboard_|clk_filter [4]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [6]), - .datab(\ula_|ps2_keyboard_|clk_filter [7]), - .datac(\ula_|ps2_keyboard_|clk_filter [5]), - .datad(\ula_|ps2_keyboard_|clk_filter [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N3 -dffeas \ula_|ps2_keyboard_|clk_filter[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N29 -dffeas \ula_|ps2_keyboard_|clk_filter[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N23 -dffeas \ula_|ps2_keyboard_|clk_filter[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N16 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|clk_filter [2] & (!\ula_|ps2_keyboard_|clk_filter [1] & !\ula_|ps2_keyboard_|clk_filter [3]))) - - .dataa(\ula_|ps2_keyboard_|Equal0~0_combout ), - .datab(\ula_|ps2_keyboard_|clk_filter [2]), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0002; -defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N10 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N11 -dffeas \ula_|ps2_keyboard_|clk_filter[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFC30; -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N27 -dffeas \ula_|ps2_keyboard_|ps2_clk_in ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N4 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0C00; -defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N5 -dffeas \ula_|ps2_keyboard_|clk_edge ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_edge~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y21_N3 -dffeas \ula_|ps2_keyboard_|bit_count[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [2]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; -defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N1 -dffeas \ula_|ps2_keyboard_|bit_count[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N16 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [1] & -// (!\ula_|ps2_keyboard_|bit_count [2] & (\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [3]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h1810; -defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N17 -dffeas \ula_|ps2_keyboard_|bit_count[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [3] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [3] & -// ((\ula_|ps2_keyboard_|bit_count [1] $ (\ula_|ps2_keyboard_|bit_count [0])))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h0750; -defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N27 -dffeas \ula_|ps2_keyboard_|bit_count[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [3] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [2]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\PS2_DAT~input_o ), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|always1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [1]) # (\ula_|ps2_keyboard_|bit_count [2]))) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCCC0; -defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (\ula_|ps2_keyboard_|clk_edge~q & (!\ula_|ps2_keyboard_|LessThan0~0_combout & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) - - .dataa(\ula_|ps2_keyboard_|always1~0_combout ), - .datab(\ula_|ps2_keyboard_|bit_count [0]), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h00D0; -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N9 -dffeas \ula_|ps2_keyboard_|shiftreg[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\PS2_DAT~input_o ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N15 -dffeas \ula_|ps2_keyboard_|shiftreg[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [8]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N5 -dffeas \ula_|ps2_keyboard_|shiftreg[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [7]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N11 -dffeas \ula_|ps2_keyboard_|shiftreg[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [6]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N11 -dffeas \ula_|ps2_keyboard_|shiftreg[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [5]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N25 -dffeas \ula_|ps2_keyboard_|shiftreg[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [4]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N29 -dffeas \ula_|ps2_keyboard_|shiftreg[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [3]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N1 -dffeas \ula_|ps2_keyboard_|shiftreg[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [2]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N17 -dffeas \ula_|ps2_keyboard_|shiftreg[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [1]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|Equal0~0_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( -// Equation(s): -// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|extended~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hF300; -defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|shiftreg [8]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|WideXor0~0_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .datad(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hC33C; -defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|LessThan0~0_combout & (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|WideXor0~2_combout ))) - - .dataa(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .datab(\PS2_DAT~input_o ), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N9 -dffeas \ula_|ps2_keyboard_|scan_code_ready ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|scan_code_ready~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y20_N1 -dffeas \ula_|zx_keyboard_|extended ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|extended~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|extended~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|extended .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~15 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~15_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & !\ula_|ps2_keyboard_|shiftreg [7])) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~15 .lut_mask = 16'h0202; -defparam \ula_|zx_keyboard_|keys[0][0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[0][0]~15_combout )) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0500; -defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][1]~36_combout & \ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( -// Equation(s): -// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & -// (((\ula_|zx_keyboard_|released~q )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|released~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hC8F0; -defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N19 -dffeas \ula_|zx_keyboard_|released ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|released~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|released~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|released .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|zx_keyboard_|WideOr17~0_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(\ula_|zx_keyboard_|WideOr17~0_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # -// (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|shifted~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|zx_keyboard_|shifted~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y21_N3 -dffeas \ula_|zx_keyboard_|shifted ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|shifted~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|shifted~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|shifted .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hFF88; -defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~38_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'h0003; -defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~39_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[5][1]~38_combout & (!\ula_|zx_keyboard_|keys[5][1]~35_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~38_combout & -// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~35_combout ), - .datac(\ula_|zx_keyboard_|keys[5][1]~q ), - .datad(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N19 -dffeas \ula_|zx_keyboard_|keys[5][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~31 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~31_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~31 .lut_mask = 16'h00CC; -defparam \ula_|zx_keyboard_|keys[4][1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~23 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~23_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q )) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~23 .lut_mask = 16'h1010; -defparam \ula_|zx_keyboard_|keys[7][1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~32 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~32_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~32 .lut_mask = 16'h000C; -defparam \ula_|zx_keyboard_|keys[7][2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~33 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~33_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[7][2]~32_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~33 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[5][2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~34 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~34_combout = (\ula_|zx_keyboard_|keys[4][1]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[4][1]~q -// )))) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~34 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N9 -dffeas \ula_|zx_keyboard_|keys[4][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N24 -cycloneive_lcell_comb \D[1]~30 ( -// Equation(s): -// \D[1]~30_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][1]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~30 .lut_mask = 16'hBB0B; -defparam \D[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~24 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~24_combout = (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~24 .lut_mask = 16'hA0A0; -defparam \ula_|zx_keyboard_|keys[5][4]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~28_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~24_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~29 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~29_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~29 .lut_mask = 16'h00C0; -defparam \ula_|zx_keyboard_|keys[3][1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~30 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~30_combout = (\ula_|zx_keyboard_|keys[3][1]~28_combout & ((\ula_|zx_keyboard_|keys[3][1]~29_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[3][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~30 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N17 -dffeas \ula_|zx_keyboard_|keys[3][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~25 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~25 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[1][4]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~26 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~26_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & \ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~26 .lut_mask = 16'h4040; -defparam \ula_|zx_keyboard_|keys[2][1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~27 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~27_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # -// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][1]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~27 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[2][1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N17 -dffeas \ula_|zx_keyboard_|keys[2][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][1]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [10]), - .datad(\ula_|zx_keyboard_|keys[2][1]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hF3FF; -defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'hCCCF; -defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h0060; -defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~17 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~17_combout = (\ula_|zx_keyboard_|keys[0][1]~16_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [4])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~17 .lut_mask = 16'h2040; -defparam \ula_|zx_keyboard_|keys[0][1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~18 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~18_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~17_combout & (!\ula_|zx_keyboard_|keys[0][1]~14_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~17_combout & -// ((\ula_|zx_keyboard_|keys[0][1]~q ))))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .datac(\ula_|zx_keyboard_|keys[0][1]~q ), - .datad(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~18 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y21_N7 -dffeas \ula_|zx_keyboard_|keys[0][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~19 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|scan_code_ready~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~19 .lut_mask = 16'h0100; -defparam \ula_|zx_keyboard_|keys[7][4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~20 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~20_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~20 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[6][4]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~21 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~21_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~21 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[1][1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~22 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~22_combout = (\ula_|zx_keyboard_|keys[1][1]~21_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][1]~21_combout & (\ula_|zx_keyboard_|keys[1][1]~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[1][1]~21_combout ), - .datac(\ula_|zx_keyboard_|keys[1][1]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~22 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[1][1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N13 -dffeas \ula_|zx_keyboard_|keys[1][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N2 -cycloneive_lcell_comb \D[1]~28 ( -// Equation(s): -// \D[1]~28_combout = (\ula_|zx_keyboard_|keys[0][1]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) # (!\ula_|zx_keyboard_|keys[0][1]~q & -// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][1]~q ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\ula_|zx_keyboard_|keys[1][1]~q ), - .cin(gnd), - .combout(\D[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~28 .lut_mask = 16'hD0DD; -defparam \D[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N26 -cycloneive_lcell_comb \D[1]~29 ( -// Equation(s): -// \D[1]~29_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~28_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][1]~q ), - .datab(\ula_|zx_keyboard_|key_row~0_combout ), - .datac(\z80_|address_pins_|abus[11]~19_combout ), - .datad(\D[1]~28_combout ), - .cin(gnd), - .combout(\D[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~29 .lut_mask = 16'hC400; -defparam \D[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~41_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[0][0]~15_combout ))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h0240; -defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~43 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~43_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[6][1]~42_combout )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~43 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[6][1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'hEAEA; -defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~44 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~44_combout = (\ula_|zx_keyboard_|keys[6][1]~43_combout & ((!\ula_|zx_keyboard_|keys[6][1]~40_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~43_combout & (\ula_|zx_keyboard_|keys[6][1]~q )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\ula_|zx_keyboard_|keys[6][1]~40_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~44 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[6][1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N25 -dffeas \ula_|zx_keyboard_|keys[6][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~45 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~45_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [7]))) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [7]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~45 .lut_mask = 16'h0002; -defparam \ula_|zx_keyboard_|keys[7][1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & -// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h0A38; -defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h0044; -defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h0140; -defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~4_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & (!\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|WideOr16~4_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'hF022; -defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~7_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~5_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|WideOr16~5_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|WideOr16~7_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hF808; -defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~46 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~46_combout = (\ula_|zx_keyboard_|keys[7][1]~45_combout & ((\ula_|zx_keyboard_|WideOr16~6_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~6_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # -// (!\ula_|zx_keyboard_|keys[7][1]~45_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][1]~q ), - .datad(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~46 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N31 -dffeas \ula_|zx_keyboard_|keys[7][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N20 -cycloneive_lcell_comb \D[1]~31 ( -// Equation(s): -// \D[1]~31_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][1]~q & -// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[6][1]~q ), - .datac(\z80_|address_pins_|abus[15]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[7][1]~q ), - .cin(gnd), - .combout(\D[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~31 .lut_mask = 16'hB0BB; -defparam \D[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N18 -cycloneive_lcell_comb \D[1]~32 ( -// Equation(s): -// \D[1]~32_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~30_combout & (\D[1]~29_combout & \D[1]~31_combout ))) - - .dataa(\D[1]~30_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[1]~29_combout ), - .datad(\D[1]~31_combout ), - .cin(gnd), - .combout(\D[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~32 .lut_mask = 16'hECCC; -defparam \D[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N4 -cycloneive_lcell_comb \D[1]~33 ( -// Equation(s): -// \D[1]~33_combout = ((\Equal2~0_combout & ((\D[1]~32_combout ))) # (!\Equal2~0_combout & (\D[1]~103_combout ))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[1]~103_combout ), - .datad(\D[1]~32_combout ), - .cin(gnd), - .combout(\D[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~33 .lut_mask = 16'hFB73; -defparam \D[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N8 -cycloneive_lcell_comb \D[1]~34 ( -// Equation(s): -// \D[1]~34_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout & \z80_|data_pins_|dout [1])))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[1]~33_combout ), - .datad(\z80_|data_pins_|dout [1]), - .cin(gnd), - .combout(\D[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~34 .lut_mask = 16'hF151; -defparam \D[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N18 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[1]~11_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[1]~11_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\D[1]~34_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N19 -dffeas \z80_|data_pins_|dout[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N30 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( -// Equation(s): -// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N24 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~11 ( -// Equation(s): -// \z80_|bus_control_|db[1]~11_combout = ((\z80_|bus_control_|db[1]~10_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(\z80_|data_pins_|dout [1]), - .datac(\z80_|bus_control_|db[1]~10_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'hD0FF; -defparam \z80_|bus_control_|db[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N14 -cycloneive_lcell_comb \z80_|ir_|opcode[1]~feeder ( -// Equation(s): -// \z80_|ir_|opcode[1]~feeder_combout = \z80_|bus_control_|db[1]~11_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[1]~11_combout ), - .cin(gnd), - .combout(\z80_|ir_|opcode[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|ir_|opcode[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|ir_|opcode[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N15 -dffeas \z80_|ir_|opcode[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|ir_|opcode[1]~feeder_combout ), + .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0005; -defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hC080; -defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~3_combout = (\z80_|execute_|ctl_alu_op_low~28_combout & (\z80_|pla_decode_|Equal64~0_combout & ((\z80_|pla_decode_|Equal9~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|pla_decode_|Equal64~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|pla_decode_|Equal61~2_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h001F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & -// (((!\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'h153F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'h8000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h0088; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h4000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_flags_cf_cpl~2_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'h040C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout = (((!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .lut_mask = 16'h777F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'h0F0C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hC0E0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hAAA8; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_flags_nf_we~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & !\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ))) - - .dataa(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'h0008; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal62~2_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'h20A0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal21~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'hCECC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|execute_|ctl_alu_op_low~32_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFFEF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N24 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~20_combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ) - - .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'hFFB3; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout = (\z80_|execute_|ctl_state_alu~12_combout & ((\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|ir_|opcode [3] & ((!\z80_|ir_|opcode [5]))))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .lut_mask = 16'h8500; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~21_combout )) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hF0AA; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_control_|out[6]~2_combout )) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|out[6]~2_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hFA50; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout & ((!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout -// & ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h11D8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~3_combout & (\z80_|execute_|ctl_flags_cf2_sel_daa~combout $ ((!\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'h99F8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y9_N31 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .q(\z80_|sequencer_|DFFE_M4_ff~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; +defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( +// Location: LCCOMB_X37_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( // Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~10_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h0B00; -defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~14_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~11_combout ) # (((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout )) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout )) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ))) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hF0E4; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout & \z80_|execute_|ctl_alu_op_low~28_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .lut_mask = 16'hFEFA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~10_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_alu_op_low~12_combout ))) +// \z80_|execute_|fMWrite~2_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .lut_mask = 16'hFF40; -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~10_combout ) # ((\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~19_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~5_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_alu_op_low~12_combout ) # (\z80_|execute_|ctl_state_alu~7_combout )))) # (!\z80_|execute_|ctl_state_alu~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_state_alu~15_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_state_alu~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h3F3B; -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal68~2_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|pla_decode_|Equal68~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hAA20; -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFF32; -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_set~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_set~0_combout = (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~12_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_set~0 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_flags_cf_set~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hC0CC; -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~9_combout = (\z80_|execute_|ctl_flags_cf_cpl~8_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|execute_|ctl_flags_cf_set~0_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .datac(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N4 -cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( -// Equation(s): -// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~9_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_cf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0C48; -defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~8 ( -// Equation(s): -// \z80_|alu_control_|db[0]~8_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((\z80_|bus_control_|db[0]~17_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|bus_control_|db[0]~17_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~8 .lut_mask = 16'h22A2; -defparam \z80_|alu_control_|db[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N20 -cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( -// Equation(s): -// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~19_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_|db[0]~19_combout ), - .cin(gnd), - .combout(\z80_|sw2_|db_up[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hFF0F; -defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N4 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~9 ( -// Equation(s): -// \z80_|alu_control_|db[0]~9_combout = (\z80_|alu_control_|db[0]~8_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[0]~8_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|sw2_|db_up[0]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~9 .lut_mask = 16'h8A00; -defparam \z80_|alu_control_|db[0]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~12 ( -// Equation(s): -// \z80_|alu_control_|db[0]~12_combout = ((\z80_|alu_control_|db[0]~9_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|db[0]~9_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~12 .lut_mask = 16'hB0FF; -defparam \z80_|alu_control_|db[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~67 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~67_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~67 .lut_mask = 16'hFF50; -defparam \ula_|zx_keyboard_|keys[5][0]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~81 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~81_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~81_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~81 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[5][0]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~82 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~82_combout = (\ula_|zx_keyboard_|keys[5][0]~81_combout & (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~81_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~82 .lut_mask = 16'h2800; -defparam \ula_|zx_keyboard_|keys[5][0]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~83 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~83_combout = (\ula_|zx_keyboard_|keys[5][0]~82_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~82_combout & ((\ula_|zx_keyboard_|keys[5][0]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .datab(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .datac(\ula_|zx_keyboard_|keys[5][0]~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), .datad(gnd), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~83_combout ), + .combout(\z80_|execute_|fMWrite~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~83 .lut_mask = 16'h7474; -defparam \ula_|zx_keyboard_|keys[5][0]~83 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h2F2F; +defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y20_N11 -dffeas \ula_|zx_keyboard_|keys[5][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][0]~83_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~84 ( +// Location: LCCOMB_X38_Y11_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~84_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [3])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~84_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~84 .lut_mask = 16'h0160; -defparam \ula_|zx_keyboard_|keys[4][0]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~85 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~85_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~85 .lut_mask = 16'hBABA; -defparam \ula_|zx_keyboard_|keys[4][0]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~86 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~86_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[4][0]~84_combout & ((!\ula_|zx_keyboard_|keys[4][0]~85_combout ))) # (!\ula_|zx_keyboard_|keys[4][0]~84_combout & -// (\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datab(\ula_|zx_keyboard_|keys[4][0]~84_combout ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~86 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][0]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N27 -dffeas \ula_|zx_keyboard_|keys[4][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N20 -cycloneive_lcell_comb \D[0]~49 ( -// Equation(s): -// \D[0]~49_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][0]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][0]~q ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[0]~49_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~49 .lut_mask = 16'hBB0B; -defparam \D[0]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [5] & ((\ula_|ps2_keyboard_|shiftreg [6])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & -// (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'h8810; -defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~76 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~76_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout )) # (!\ula_|zx_keyboard_|WideOr4~0_combout ))) - - .dataa(\ula_|zx_keyboard_|WideOr4~0_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~76_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~76 .lut_mask = 16'h3313; -defparam \ula_|zx_keyboard_|keys~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~73 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~73_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~73_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~73 .lut_mask = 16'hF000; -defparam \ula_|zx_keyboard_|keys[4][3]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~47 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~47_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~47 .lut_mask = 16'h0808; -defparam \ula_|zx_keyboard_|keys[6][4]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// ((\ula_|ps2_keyboard_|shiftreg [2]))))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0310; -defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~74 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~74_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~74_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~74 .lut_mask = 16'h353F; -defparam \ula_|zx_keyboard_|keys~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~75 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~75_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][3]~73_combout & !\ula_|zx_keyboard_|keys~74_combout )) # (!\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~73_combout ), - .datab(\ula_|zx_keyboard_|keys~74_combout ), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~75_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~75 .lut_mask = 16'h2F00; -defparam \ula_|zx_keyboard_|keys[0][0]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~77 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~77_combout = (\ula_|zx_keyboard_|keys~76_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) # (!\ula_|zx_keyboard_|keys~76_combout & ((\ula_|zx_keyboard_|keys[0][0]~75_combout & ((!\ula_|zx_keyboard_|released~q ))) # -// (!\ula_|zx_keyboard_|keys[0][0]~75_combout & (\ula_|zx_keyboard_|keys[0][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys~76_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~75_combout ), - .datac(\ula_|zx_keyboard_|keys[0][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~77_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~77 .lut_mask = 16'hB0F4; -defparam \ula_|zx_keyboard_|keys[0][0]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N15 -dffeas \ula_|zx_keyboard_|keys[0][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][0]~77_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~71 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~71_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~71_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~71 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[1][0]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~72 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~72_combout = (\ula_|zx_keyboard_|keys[1][0]~71_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][0]~71_combout & (\ula_|zx_keyboard_|keys[1][0]~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[1][0]~71_combout ), - .datac(\ula_|zx_keyboard_|keys[1][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~72 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[1][0]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N17 -dffeas \ula_|zx_keyboard_|keys[1][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N30 -cycloneive_lcell_comb \D[0]~47 ( -// Equation(s): -// \D[0]~47_combout = (\ula_|zx_keyboard_|keys[0][0]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~q & -// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~q ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\ula_|zx_keyboard_|keys[1][0]~q ), - .cin(gnd), - .combout(\D[0]~47_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~47 .lut_mask = 16'hD0DD; -defparam \D[0]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~80 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][0]~80_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # -// (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][0]~80_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0]~80 .lut_mask = 16'hB1F0; -defparam \ula_|zx_keyboard_|keys[2][0]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N23 -dffeas \ula_|zx_keyboard_|keys[2][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][0]~80_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~78 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~78 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|keys[3][0]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~79 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~79_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & ((\ula_|zx_keyboard_|keys[3][1]~28_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (\ula_|zx_keyboard_|keys[3][0]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][0]~78_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~79 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[3][0]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N5 -dffeas \ula_|zx_keyboard_|keys[3][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~1_combout = ((\z80_|address_pins_|DFFE_apin_latch [11]) # (!\ula_|zx_keyboard_|keys[3][0]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [11]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hFF3F; -defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N4 -cycloneive_lcell_comb \D[0]~48 ( -// Equation(s): -// \D[0]~48_combout = (\D[0]~47_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][0]~q )))) - - .dataa(\D[0]~47_combout ), - .datab(\z80_|address_pins_|abus[10]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|key_row~1_combout ), - .cin(gnd), - .combout(\D[0]~48_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~48 .lut_mask = 16'h8A00; -defparam \D[0]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~91 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~91_combout = (\ula_|zx_keyboard_|shifted~1_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[6][0]~90_combout & \ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|shifted~1_combout ), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[6][0]~90_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~91 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[6][0]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~92 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~92_combout = (\ula_|zx_keyboard_|keys[6][0]~91_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][0]~91_combout & ((\ula_|zx_keyboard_|keys[6][0]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][0]~q ), - .datad(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~92 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[6][0]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N21 -dffeas \ula_|zx_keyboard_|keys[6][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~63 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~63_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~63 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[5][4]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h0303; -defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[5][4]~63_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|WideOr16~3_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~132 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~132_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~132_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~132 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[7][0]~132 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~88 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~88_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & ((\ula_|zx_keyboard_|keys[7][0]~87_combout ) # (\ula_|zx_keyboard_|keys[7][0]~132_combout )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .datad(\ula_|zx_keyboard_|keys[7][0]~132_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~88 .lut_mask = 16'h8880; -defparam \ula_|zx_keyboard_|keys[7][0]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~89 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~89_combout = (\ula_|zx_keyboard_|keys[7][0]~88_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][0]~88_combout & (\ula_|zx_keyboard_|keys[7][0]~q )) - - .dataa(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~89 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[7][0]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N7 -dffeas \ula_|zx_keyboard_|keys[7][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N28 -cycloneive_lcell_comb \D[0]~50 ( -// Equation(s): -// \D[0]~50_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][0]~q & -// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[6][0]~q ), - .datac(\z80_|address_pins_|abus[15]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[7][0]~q ), - .cin(gnd), - .combout(\D[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~50 .lut_mask = 16'hB0BB; -defparam \D[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N10 -cycloneive_lcell_comb \D[0]~51 ( -// Equation(s): -// \D[0]~51_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~49_combout & (\D[0]~48_combout & \D[0]~50_combout ))) - - .dataa(\D[0]~49_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[0]~48_combout ), - .datad(\D[0]~50_combout ), - .cin(gnd), - .combout(\D[0]~51_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~51 .lut_mask = 16'hECCC; -defparam \D[0]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y16_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N14 -cycloneive_lcell_comb \D[0]~55 ( -// Equation(s): -// \D[0]~55_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\D[0]~55_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~55 .lut_mask = 16'hE3E0; -defparam \D[0]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N22 -cycloneive_lcell_comb \D[0]~56 ( -// Equation(s): -// \D[0]~56_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~55_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout )) # (!\D[0]~55_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~55_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[0]~55_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .cin(gnd), - .combout(\D[0]~56_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~56 .lut_mask = 16'hBCB0; -defparam \D[0]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y28_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X22_Y30_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; -// synopsys translate_on - -// Location: M9K_X22_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N4 -cycloneive_lcell_comb \D[0]~52 ( -// Equation(s): -// \D[0]~52_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\z80_|address_pins_|abus[14]~23_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .cin(gnd), - .combout(\D[0]~52_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~52 .lut_mask = 16'hF858; -defparam \D[0]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y20_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N28 -cycloneive_lcell_comb \D[0]~53 ( -// Equation(s): -// \D[0]~53_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout $ ((\D[0]~52_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & (((!\D[0]~52_combout & -// \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datab(\z80_|address_pins_|abus[15]~22_combout ), - .datac(\D[0]~52_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\D[0]~53_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~53 .lut_mask = 16'h4B48; -defparam \D[0]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N16 -cycloneive_lcell_comb \D[0]~54 ( -// Equation(s): -// \D[0]~54_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~52_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~52_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & !\D[0]~53_combout )) # (!\D[0]~52_combout & ((\D[0]~53_combout ))))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[0]~52_combout ), - .datad(\D[0]~53_combout ), - .cin(gnd), - .combout(\D[0]~54_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~54 .lut_mask = 16'hC3E0; -defparam \D[0]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N8 -cycloneive_lcell_comb \D[0]~106 ( -// Equation(s): -// \D[0]~106_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[0]~56_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[0]~54_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[0]~56_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[0]~56_combout ), - .datad(\D[0]~54_combout ), - .cin(gnd), - .combout(\D[0]~106_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~106 .lut_mask = 16'hF4B0; -defparam \D[0]~106 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N14 -cycloneive_lcell_comb \D[0]~57 ( -// Equation(s): -// \D[0]~57_combout = ((\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout )))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~1_combout ), - .datab(\D[0]~51_combout ), - .datac(\D[0]~106_combout ), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[0]~57_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~57 .lut_mask = 16'hDDF5; -defparam \D[0]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N0 -cycloneive_lcell_comb \D[0]~58 ( -// Equation(s): -// \D[0]~58_combout = (\D[0]~57_combout & (((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[0]~57_combout & (!\Equal2~1_combout & ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [0]), - .datac(\D[0]~57_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[0]~58_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~58 .lut_mask = 16'hC0F5; -defparam \D[0]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N0 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[0]~17_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[0]~17_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\D[0]~58_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N1 -dffeas \z80_|data_pins_|dout[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N4 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( -// Equation(s): -// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(\z80_|data_pins_|dout [0]), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'hC0CC; -defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( -// Equation(s): -// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|alu_control_|db[0]~12_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~16_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'hDF55; -defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y13_N27 -dffeas \z80_|ir_|opcode[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[0]~17_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) +// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2])) .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), .cin(gnd), - .combout(\z80_|pla_decode_|Equal63~0_combout ), + .combout(\z80_|pla_decode_|Equal13~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; +defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( +// Location: LCCOMB_X38_Y11_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( // Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) +// \z80_|pla_decode_|Equal13~2_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .combout(\z80_|pla_decode_|Equal13~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N20 -cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( +// Location: LCCOMB_X36_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( // Equation(s): -// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h070F; -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( -// Equation(s): -// \z80_|alu_control_|db[6]~10_combout = ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|execute_|ctl_flags_oe~2_combout )) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) - - .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|execute_|ctl_flags_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hFFF5; -defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( -// Equation(s): -// \z80_|alu_control_|db[6]~11_combout = (\z80_|alu_control_|db[6]~10_combout ) # ((\z80_|execute_|ctl_sw_1d~7_combout ) # (\z80_|execute_|ctl_reg_out_lo~8_combout )) - - .dataa(\z80_|alu_control_|db[6]~10_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFEFE; -defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( -// Equation(s): -// \z80_|alu_control_|db[4]~30_combout = (\z80_|alu_|db[4]~17_combout & (\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|reg_file_|gdfx_temp0[4]~62_combout ))) # (!\z80_|alu_|db[4]~17_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((\z80_|execute_|ctl_reg_out_lo~8_combout & !\z80_|reg_file_|gdfx_temp0[4]~62_combout )))) - - .dataa(\z80_|alu_|db[4]~17_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h5D0C; -defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( -// Equation(s): -// \z80_|alu_control_|db[4]~31_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[4]~30_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_flags_|flags_hf~combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_control_|db[4]~30_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h00B0; -defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( -// Equation(s): -// \z80_|alu_control_|db[4]~32_combout = ((\z80_|alu_control_|db[4]~31_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|alu_control_|db[4]~31_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'hBF33; -defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~119 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~119_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & -// (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~119_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~119 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[2][4]~119 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~120 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~120_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][4]~119_combout & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|zx_keyboard_|keys[2][4]~119_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~120_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~120 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[2][4]~120 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~95 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~95_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~95_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~95 .lut_mask = 16'hAFAA; -defparam \ula_|zx_keyboard_|keys[2][4]~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~121 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~121_combout = (\ula_|zx_keyboard_|keys[2][4]~120_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[2][4]~120_combout & (\ula_|zx_keyboard_|keys[2][4]~q )) - - .dataa(\ula_|zx_keyboard_|keys[2][4]~120_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~121_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~121 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[2][4]~121 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N23 -dffeas \ula_|zx_keyboard_|keys[2][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][4]~121_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~117 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~117_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~117_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~117 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|keys[3][4]~117 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~136 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~136_combout = (\ula_|zx_keyboard_|keys[3][4]~117_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[3][4]~117_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~136_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~136 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[3][4]~136 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~130 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~130_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~130_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~130 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[3][4]~130 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~118 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~118_combout = (\ula_|zx_keyboard_|keys[3][4]~136_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[3][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~136_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][4]~136_combout ), - .datac(\ula_|zx_keyboard_|keys[3][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~118 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][4]~118 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N9 -dffeas \ula_|zx_keyboard_|keys[3][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N18 -cycloneive_lcell_comb \D[4]~78 ( -// Equation(s): -// \D[4]~78_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # ((!\ula_|zx_keyboard_|keys[2][4]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][4]~q & -// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\z80_|address_pins_|abus[10]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~q ), - .cin(gnd), - .combout(\D[4]~78_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~78 .lut_mask = 16'h8ACF; -defparam \D[4]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~126 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~126_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~126 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[6][4]~126 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~128 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~128_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~128_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~128 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[5][4]~128 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~129 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~129_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[5][4]~128_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~128_combout & -// (\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~128_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~129_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~129 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][4]~129 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y19_N9 -dffeas \ula_|zx_keyboard_|keys[5][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][4]~129_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~127 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~127_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~20_combout & ((\ula_|zx_keyboard_|keys[6][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~127_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~127 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[6][4]~127 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N5 -dffeas \ula_|zx_keyboard_|keys[6][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][4]~127_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~51 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~51_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~51 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[7][4]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~125 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~125_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~51_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) -// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~1_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~125_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~125 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][4]~125 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N11 -dffeas \ula_|zx_keyboard_|keys[7][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][4]~125_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N30 -cycloneive_lcell_comb \D[4]~79 ( -// Equation(s): -// \D[4]~79_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\z80_|address_pins_|abus[14]~23_combout ) # ((!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][4]~q & -// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\z80_|address_pins_|abus[14]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~q ), - .cin(gnd), - .combout(\D[4]~79_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~79 .lut_mask = 16'h8ACF; -defparam \D[4]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~122 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q )) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & -// \ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~122 .lut_mask = 16'h4422; -defparam \ula_|zx_keyboard_|keys[4][4]~122 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~123 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~123_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][4]~122_combout ))) - - .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~123 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][4]~123 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & ((\ula_|zx_keyboard_|keys[4][4]~123_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~123_combout & ((\ula_|zx_keyboard_|keys[4][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[4][4]~q ), - .datad(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N25 -dffeas \ula_|zx_keyboard_|keys[4][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\ula_|zx_keyboard_|keys[4][4]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|execute_|ixy_d~4_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_T3_ff~q )) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [12]), - .datad(\ula_|zx_keyboard_|keys[4][4]~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~3_combout ), + .combout(\z80_|execute_|ixy_d~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hF3FF; -defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h000C; +defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y19_N8 -cycloneive_lcell_comb \D[4]~80 ( +// Location: LCCOMB_X38_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( // Equation(s): -// \D[4]~80_combout = (\D[4]~79_combout & (\ula_|zx_keyboard_|key_row~3_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) +// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) - .dataa(\ula_|zx_keyboard_|keys[5][4]~q ), - .datab(\D[4]~79_combout ), - .datac(\z80_|address_pins_|abus[13]~20_combout ), - .datad(\ula_|zx_keyboard_|key_row~3_combout ), - .cin(gnd), - .combout(\D[4]~80_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~80 .lut_mask = 16'hC400; -defparam \D[4]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~111 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~111_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|zx_keyboard_|released~q ), + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), .datab(gnd), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~111_combout ), + .combout(\z80_|execute_|fIOWrite~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~111 .lut_mask = 16'hFAAA; -defparam \ula_|zx_keyboard_|keys[0][4]~111 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hAA0A; +defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~97 ( +// Location: LCCOMB_X38_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~97_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~97 .lut_mask = 16'h0060; -defparam \ula_|zx_keyboard_|keys[0][4]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~116 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~116_combout = (\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & (!\ula_|zx_keyboard_|keys[0][4]~111_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & -// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~116_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~116 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][4]~116 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N11 -dffeas \ula_|zx_keyboard_|keys[0][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][4]~116_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~115 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~115_combout = (\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[1][4]~q )))) # -// (!\ula_|zx_keyboard_|Equal0~2_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) - - .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[1][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~115_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~115 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][4]~115 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N7 -dffeas \ula_|zx_keyboard_|keys[1][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][4]~115_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N28 -cycloneive_lcell_comb \D[4]~77 ( -// Equation(s): -// \D[4]~77_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][4]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][4]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[1][4]~q ), - .cin(gnd), - .combout(\D[4]~77_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~77 .lut_mask = 16'h8ACF; -defparam \D[4]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N26 -cycloneive_lcell_comb \D[4]~81 ( -// Equation(s): -// \D[4]~81_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~78_combout & (\D[4]~80_combout & \D[4]~77_combout ))) - - .dataa(\z80_|address_pins_|abus[0]~16_combout ), - .datab(\D[4]~78_combout ), - .datac(\D[4]~80_combout ), - .datad(\D[4]~77_combout ), - .cin(gnd), - .combout(\D[4]~81_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~81 .lut_mask = 16'hEAAA; -defparam \D[4]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y1_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; -// synopsys translate_on - -// Location: M9K_X22_Y22_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y3_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; -// synopsys translate_on - -// Location: M9K_X22_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N2 -cycloneive_lcell_comb \Selector4~0 ( -// Equation(s): -// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .cin(gnd), - .combout(\Selector4~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector4~0 .lut_mask = 16'hBA98; -defparam \Selector4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N26 -cycloneive_lcell_comb \Selector4~1 ( -// Equation(s): -// \Selector4~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector4~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # (!\Selector4~0_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector4~0_combout )))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datad(\Selector4~0_combout ), - .cin(gnd), - .combout(\Selector4~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector4~1 .lut_mask = 16'hF388; -defparam \Selector4~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y16_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y3_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N20 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .lut_mask = 16'hE5E0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N10 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .lut_mask = 16'hAFC0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N6 -cycloneive_lcell_comb \D[4]~109 ( -// Equation(s): -// \D[4]~109_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\Selector4~1_combout -// )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ))))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\Selector4~1_combout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), - .cin(gnd), - .combout(\D[4]~109_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~109 .lut_mask = 16'hFB40; -defparam \D[4]~109 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N18 -cycloneive_lcell_comb \D[4]~97 ( -// Equation(s): -// \D[4]~97_combout = ((\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout )))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\D[4]~81_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[4]~109_combout ), - .cin(gnd), - .combout(\D[4]~97_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~97 .lut_mask = 16'hDF8F; -defparam \D[4]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N30 -cycloneive_lcell_comb \D[4]~98 ( -// Equation(s): -// \D[4]~98_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [4] & ((\D[4]~97_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[4]~97_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[4]~97_combout ), - .cin(gnd), - .combout(\D[4]~98_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~98 .lut_mask = 16'hBB03; -defparam \D[4]~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N24 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[4]~19_combout ) # ((\D[4]~98_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[4]~98_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[4]~98_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N25 -dffeas \z80_|data_pins_|dout[4] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N20 -cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( -// Equation(s): -// \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[4]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'h88CC; -defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N18 -cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( -// Equation(s): -// \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[4]~18_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hDF55; -defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N19 -dffeas \z80_|ir_|opcode[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[4]~19_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~0_combout = (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) +// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) .dataa(gnd), .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~0_combout ), + .combout(\z80_|execute_|ctl_mWrite~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( +// Location: LCCOMB_X34_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( // Equation(s): -// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) +// \z80_|execute_|fMRead~2_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~5_combout ), + .combout(\z80_|execute_|fMRead~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h3F0F; +defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N22 +// Location: LCCOMB_X34_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~2_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~2 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_state_alu~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~11_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N2 cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( // Equation(s): -// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|fMRead~0_combout )))) +// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|fMRead~2_combout )))) - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), - .datad(\z80_|execute_|fMRead~0_combout ), + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|fMRead~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), .cin(gnd), .combout(\z80_|execute_|fIOWrite~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hFB00; defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( +// Location: LCCOMB_X39_Y7_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( // Equation(s): -// \z80_|execute_|fIOWrite~3_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) +// \z80_|pla_decode_|Equal2~0_combout = (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h00CC; +defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N2 +cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( +// Equation(s): +// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instCB~q ) # (\z80_|decode_state_|DFFE_instED~q ) + + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|decode_state_|table_xx~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; +defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|table_xx~0_combout & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~0_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~3 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~3_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~3 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( +// Equation(s): +// \z80_|execute_|fIOWrite~3_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), .cin(gnd), .combout(\z80_|execute_|fIOWrite~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3F0F; +defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3B3B; defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y18_N2 +// Location: LCCOMB_X39_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( +// Equation(s): +// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N16 cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( // Equation(s): -// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) +// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|fIOWrite~3_combout ), + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|fIOWrite~3_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), .cin(gnd), .combout(\z80_|execute_|fIOWrite~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hA8AA; +defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hCC8C; defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N4 +// Location: LCCOMB_X38_Y13_N4 cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( // Equation(s): -// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~5_combout ))) +// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~3_combout ))) .dataa(\z80_|execute_|fIOWrite~1_combout ), - .datab(\z80_|execute_|ctl_mRead~5_combout ), - .datac(\z80_|execute_|fIOWrite~2_combout ), + .datab(\z80_|execute_|fIOWrite~2_combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), .datad(\z80_|execute_|fIOWrite~4_combout ), .cin(gnd), .combout(\z80_|execute_|fIOWrite~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFFEC; defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( +// Location: LCCOMB_X37_Y8_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~11_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) +// \z80_|pin_control_|bus_db_pin_oe~4_combout = (!\z80_|execute_|fIOWrite~5_combout & ((\z80_|execute_|fMWrite~2_combout ) # ((\z80_|execute_|fMWrite~3_combout & !\z80_|pla_decode_|Equal13~2_combout )))) - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mWrite~10_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .dataa(\z80_|execute_|fMWrite~3_combout ), + .datab(\z80_|execute_|fMWrite~2_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|fIOWrite~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~11_combout ), + .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; +defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'h00CE; +defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( +// Location: LCCOMB_X40_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~3 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~12_combout = (\z80_|execute_|ctl_mWrite~8_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) +// \z80_|execute_|ctl_state_alu~3_combout = (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~3 .lut_mask = 16'h0C0C; +defparam \z80_|execute_|ctl_state_alu~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~1_combout = (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h3300; +defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~6_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~4_combout = (\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; +defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0100; +defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~46_combout = ((!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|execute_|ctl_mWrite~6_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~46_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2u~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal19~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal34~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h0400; +defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|comb~0 ( +// Equation(s): +// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|comb~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~0 .lut_mask = 16'hCC00; +defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal47~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|execute_|comb~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~45_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & +// (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (\z80_|execute_|ctl_inc_cy~45_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal19~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_inc_cy~45_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N10 +cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( +// Equation(s): +// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|M5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88C0; +defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N11 +dffeas \z80_|sequencer_|M5 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|M5~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|M5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|M5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( +// Equation(s): +// \z80_|execute_|ixy_d~7_combout = (\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h00AA; +defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~44_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ctl_alu_oe~2_combout & +// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_inc_cy~44_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|ctl_inc_cy~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q )) + + .dataa(gnd), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0300; +defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~14_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~7_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N24 +cycloneive_lcell_comb \z80_|execute_|fMWrite~0 ( +// Equation(s): +// \z80_|execute_|fMWrite~0_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~0 .lut_mask = 16'h0001; +defparam \z80_|execute_|fMWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~97 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~97_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~97_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~97 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~96 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~96_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal19~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~96_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~96 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~98 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~98_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~98_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~98 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~98_combout & (((!\z80_|execute_|ctl_alu_op_low~14_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_inc_cy~98_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_inc_cy~97_combout & (\z80_|execute_|ctl_inc_cy~96_combout & \z80_|execute_|ctl_inc_cy~48_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~97_combout ), + .datab(\z80_|execute_|ctl_inc_cy~96_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_cy~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|fMWrite~1 ( +// Equation(s): +// \z80_|execute_|fMWrite~1_combout = (\z80_|sequencer_|M5~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|sequencer_|M5~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # +// (\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~1 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMWrite~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N18 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|execute_|ctl_bus_inc_oe~28_combout & ((\z80_|execute_|fMWrite~0_combout ) # (!\z80_|execute_|fMWrite~1_combout ))) + + .dataa(\z80_|execute_|fMWrite~0_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .datac(gnd), + .datad(\z80_|execute_|fMWrite~1_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'h88CC; +defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N4 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|execute_|ctl_inc_cy~47_combout & (\z80_|execute_|ctl_apin_mux~0_combout & \z80_|pin_control_|bus_db_pin_oe~3_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .datab(\z80_|execute_|ctl_inc_cy~47_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~6_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|execute_|ctl_mRead~6_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h153F; +defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~7_combout = (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N22 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|pin_control_|bus_db_pin_oe~6_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((!\z80_|execute_|ctl_mWrite~7_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'hB0F0; +defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~17 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~17_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~17 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_mWrite~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( +// Equation(s): +// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|ctl_mWrite~17_combout & (!\z80_|execute_|ctl_mWrite~6_combout & !\z80_|execute_|ctl_mRead~5_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_mWrite~11_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~12_combout ), + .combout(\z80_|execute_|fMWrite~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h0003; +defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( +// Location: LCCOMB_X37_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~9_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) +// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - .dataa(\z80_|execute_|ctl_mWrite~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datac(\z80_|execute_|ctl_mWrite~9_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~13_combout ), + .combout(\z80_|execute_|ctl_state_alu~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( +// Location: LCCOMB_X39_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) +// \z80_|execute_|ctl_inc_cy~49_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout +// & (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~14_combout ), + .combout(\z80_|execute_|ctl_inc_cy~49_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N28 +// Location: LCCOMB_X36_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~49_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~49_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~4_combout ) # ((!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|fMWrite~4_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_inc_dec~2_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'hCD00; +defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( +// Equation(s): +// \z80_|execute_|fMWrite~8_combout = (\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ctl_alu_oe~2_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (\z80_|execute_|ctl_mRead~8_combout & +// ((\z80_|execute_|ctl_alu_oe~2_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~51 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~51_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~51 .lut_mask = 16'hABFF; +defparam \z80_|execute_|ctl_bus_inc_oe~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|M5~q )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~15_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hABFF; +defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal46~0_combout = (\z80_|ir_|opcode [2] & (\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [0] & \z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal46~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~10_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~45_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'hF3F7; +defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [7]), + .datac(gnd), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0033; +defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|decode_state_|DFFE_instCB~q )))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~29_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout ))) # (!\z80_|execute_|ctl_alu_oe~2_combout & (((!\z80_|execute_|ixy_d~7_combout )) # +// (!\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h1357; +defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|ctl_alu_core_S~10_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & \z80_|execute_|ctl_bus_inc_oe~29_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_S~10_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal55~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0044; +defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout )) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~7_combout & ((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & +// (((!\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ctl_bus_inc_oe~51_combout & (\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|execute_|ctl_bus_inc_oe~31_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~51_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N6 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~17 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~17_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~17 .lut_mask = 16'h1333; +defparam \z80_|pin_control_|bus_db_pin_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( +// Equation(s): +// \z80_|execute_|fIOWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h3733; +defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N0 +cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( +// Equation(s): +// \z80_|execute_|fMWrite~6_combout = ((\z80_|pla_decode_|Equal46~0_combout ) # ((!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) # (!\z80_|execute_|ctl_ir_we~5_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'hF7F5; +defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( +// Equation(s): +// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h3737; +defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N0 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|execute_|fIOWrite~0_combout & ((\z80_|execute_|fMWrite~6_combout ) # ((\z80_|execute_|fMWrite~5_combout )))) # (!\z80_|execute_|fIOWrite~0_combout & (!\z80_|execute_|ctl_mWrite~8_combout & +// ((\z80_|execute_|fMWrite~6_combout ) # (\z80_|execute_|fMWrite~5_combout )))) + + .dataa(\z80_|execute_|fIOWrite~0_combout ), + .datab(\z80_|execute_|fMWrite~6_combout ), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|execute_|fMWrite~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'hAF8C; +defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( +// Equation(s): +// \z80_|execute_|fMRead~3_combout = ((!\z80_|execute_|ctl_ir_we~5_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|ir_|opcode [7]) + + .dataa(\z80_|ir_|opcode [7]), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~4_combout & \z80_|execute_|fMRead~3_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~4_combout )) # +// (!\z80_|execute_|ctl_alu_oe~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|fMRead~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h1F15; +defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N24 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~8_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & +// (((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~5_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h0777; +defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N6 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~17_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~10_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~17_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|execute_|comb~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'h0313; +defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_reg_sel_wz~6_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|M5~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout = (\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~8_combout & +// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .lut_mask = 16'h0537; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( +// Equation(s): +// \z80_|execute_|fMWrite~7_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # (\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|pin_control_|bus_db_pin_oe~12_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & !\z80_|execute_|fMWrite~7_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .datad(\z80_|execute_|fMWrite~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h0080; +defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N2 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (!\z80_|execute_|fMWrite~8_combout & (\z80_|execute_|ctl_bus_inc_oe~32_combout & \z80_|pin_control_|bus_db_pin_oe~13_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .datab(\z80_|execute_|fMWrite~8_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'h2000; +defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~15 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~15_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout & (\z80_|pin_control_|bus_db_pin_oe~5_combout & (\z80_|pin_control_|bus_db_pin_oe~7_combout & \z80_|pin_control_|bus_db_pin_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~15 .lut_mask = 16'h4000; +defparam \z80_|pin_control_|bus_db_pin_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N8 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'hFCFC; +defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~16 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~16_combout = (\z80_|sequencer_|DFFE_T4_ff~q & ((\z80_|execute_|fIOWrite~5_combout ) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout & \z80_|pin_control_|bus_db_pin_oe~2_combout )))) # (!\z80_|sequencer_|DFFE_T4_ff~q & +// (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (\z80_|pin_control_|bus_db_pin_oe~2_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .datad(\z80_|execute_|fIOWrite~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~16 .lut_mask = 16'hBA30; +defparam \z80_|pin_control_|bus_db_pin_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|nextM~4 ( +// Equation(s): +// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout ) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~4 .lut_mask = 16'h373F; +defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( +// Equation(s): +// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_eval_cond~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h0A0A; +defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~12_combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_iorw~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|ctl_mWrite~17_combout ))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|nextM~4_combout ), + .datad(\z80_|execute_|ctl_iorw~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y11_N21 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_iorw~9_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y11_N17 +dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N14 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorq~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_iorq~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_iorq~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y11_N15 +dffeas \z80_|memory_ifc_|wait_iorq ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorq~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y11_N23 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorq~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N22 +cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( +// Equation(s): +// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) + + .dataa(gnd), + .datab(\z80_|memory_ifc_|wait_iorq~q ), + .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|iorq~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; +defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'hA000; +defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( +// Equation(s): +// \z80_|execute_|ixy_d~17_combout = (\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|decode_state_|DFFE_instIY1~q & !\z80_|decode_state_|DFFE_inst4~q )))) # (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|decode_state_|DFFE_instIY1~q & +// !\z80_|decode_state_|DFFE_inst4~q )) # (!\z80_|pla_decode_|Equal50~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~2_combout ), + .datab(\z80_|pla_decode_|Equal50~0_combout ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h111F; +defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N14 cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~15_combout = ((\z80_|execute_|ctl_mWrite~14_combout ) # ((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout ))) # (!\z80_|execute_|ctl_mWrite~13_combout ) +// \z80_|execute_|ctl_mWrite~15_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~7_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|execute_|ctl_mWrite~7_combout ))) - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|execute_|ctl_mWrite~13_combout ), - .datac(\z80_|execute_|ctl_mWrite~14_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_mWrite~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hF7F3; +defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hEAC0; defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N29 +// Location: LCCOMB_X34_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~18 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~18_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal11~0_combout & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~18 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_mWrite~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~12_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~21 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~21_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~21 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_flags_alu~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~20 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~20_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~20 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~10_combout = (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~10_combout = (\z80_|execute_|ctl_flags_alu~21_combout & (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & \z80_|execute_|ctl_flags_alu~10_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~21_combout ), + .datab(\z80_|execute_|ctl_flags_alu~20_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_mWrite~10_combout & ((!\z80_|execute_|ctl_mWrite~8_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~12_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|execute_|ctl_mWrite~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( +// Equation(s): +// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~9_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~12_combout = (\z80_|execute_|ctl_inc_cy~51_combout & (((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|execute_|ctl_inc_cy~51_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (\z80_|execute_|ctl_inc_dec~12_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_inc_dec~2_combout ), + .datac(\z80_|execute_|ctl_inc_dec~12_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~11_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~25_combout = (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~22 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~22_combout = (((!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~22 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_flags_alu~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~24_combout = (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~22_combout & (((!\z80_|execute_|ctl_mRead~25_combout & !\z80_|execute_|ctl_mRead~24_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~25_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ctl_flags_alu~22_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_mWrite~13_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~11_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~11_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( +// Equation(s): +// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|execute_|ctl_mWrite~15_combout ) # (((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout )) # (!\z80_|execute_|ctl_mWrite~14_combout )) + + .dataa(\z80_|execute_|ixy_d~17_combout ), + .datab(\z80_|execute_|ctl_mWrite~15_combout ), + .datac(\z80_|execute_|ctl_mWrite~14_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'hDFCF; +defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N1 dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mWrite~15_combout ), + .d(\z80_|execute_|ctl_mWrite~16_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -48008,7 +9324,7 @@ defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N4 +// Location: LCCOMB_X37_Y14_N12 cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( // Equation(s): // \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q @@ -48025,7 +9341,7 @@ defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N5 +// Location: FF_X37_Y14_N13 dffeas \z80_|memory_ifc_|wait_mwr ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), @@ -48044,15 +9360,32 @@ defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; // synopsys translate_on -// Location: FF_X43_Y17_N17 +// Location: LCCOMB_X40_Y11_N20 +cycloneive_lcell_comb \z80_|memory_ifc_|mwr_wr~feeder ( +// Equation(s): +// \z80_|memory_ifc_|mwr_wr~feeder_combout = \z80_|memory_ifc_|wait_mwr~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|wait_mwr~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|mwr_wr~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|mwr_wr~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|mwr_wr~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y11_N21 dffeas \z80_|memory_ifc_|mwr_wr ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_mwr~q ), + .d(\z80_|memory_ifc_|mwr_wr~feeder_combout ), + .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), @@ -48063,1063 +9396,1523 @@ defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N16 +// Location: LCCOMB_X40_Y11_N24 cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( // Equation(s): -// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|memory_ifc_|iorq~0_combout )) +// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIOWrite~5_combout )) - .dataa(\z80_|execute_|fIOWrite~5_combout ), - .datab(\z80_|memory_ifc_|iorq~0_combout ), - .datac(\z80_|memory_ifc_|mwr_wr~q ), + .dataa(\z80_|memory_ifc_|iorq~0_combout ), + .datab(\z80_|memory_ifc_|mwr_wr~q ), + .datac(\z80_|execute_|fIOWrite~5_combout ), .datad(gnd), .cin(gnd), .combout(\z80_|memory_ifc_|nWR_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hF8F8; +defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hECEC; defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N4 -cycloneive_lcell_comb \D[5]~84 ( -// Equation(s): -// \D[5]~84_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\D[5]~84_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~84 .lut_mask = 16'h0040; -defparam \D[5]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y5_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: M9K_X33_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N14 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # -// ((\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// (\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .lut_mask = 16'hBA98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N4 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hF858; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y24_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y30_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; -// synopsys translate_on - -// Location: M9K_X22_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; -// synopsys translate_on - -// Location: M9K_X33_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N18 -cycloneive_lcell_comb \Mux0~0 ( -// Equation(s): -// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .cin(gnd), - .combout(\Mux0~0_combout ), - .cout()); -// synopsys translate_off -defparam \Mux0~0 .lut_mask = 16'hBA98; -defparam \Mux0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N12 -cycloneive_lcell_comb \Mux0~1 ( -// Equation(s): -// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\Mux0~0_combout ), - .cin(gnd), - .combout(\Mux0~1_combout ), - .cout()); -// synopsys translate_off -defparam \Mux0~1 .lut_mask = 16'hBBC0; -defparam \Mux0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N22 -cycloneive_lcell_comb \D[7]~112 ( -// Equation(s): -// \D[7]~112_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Mux0~1_combout ))) -// # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), - .datad(\Mux0~1_combout ), - .cin(gnd), - .combout(\D[7]~112_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~112 .lut_mask = 16'hF4B0; -defparam \D[7]~112 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N30 -cycloneive_lcell_comb \D[7]~94 ( -// Equation(s): -// \D[7]~94_combout = (\D[5]~84_combout & (\D[7]~112_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & ((\z80_|data_pins_|dout [7]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\D[5]~84_combout ), - .datab(\z80_|data_pins_|dout [7]), - .datac(\D[7]~112_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[7]~94_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~94 .lut_mask = 16'hC4F5; -defparam \D[7]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N26 -cycloneive_lcell_comb \D[7]~102 ( -// Equation(s): -// \D[7]~102_combout = (\D[7]~94_combout ) # (!\D[0]~107_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\D[7]~94_combout ), - .datad(\D[0]~107_combout ), - .cin(gnd), - .combout(\D[7]~102_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~102 .lut_mask = 16'hF0FF; -defparam \D[7]~102 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N26 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\D[7]~102_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[7]~7_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[7]~102_combout & (\z80_|bus_control_|db[7]~7_combout -// & ((\z80_|execute_|ctl_bus_db_we~7_combout )))) - - .dataa(\D[7]~102_combout ), - .datab(\z80_|bus_control_|db[7]~7_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hECA0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N27 -dffeas \z80_|data_pins_|dout[7] ( +// Location: FF_X40_Y11_N17 +dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .d(\z80_|execute_|setM1~53_combout ), .asdata(vcc), - .clrn(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|data_pins_|dout [7]), + .q(\z80_|memory_ifc_|DFFE_m1_ff1~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[7] .power_up = "low"; +defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N2 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( +// Location: LCCOMB_X40_Y11_N8 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( // Equation(s): -// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) +// \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q .dataa(gnd), - .datab(\z80_|alu_control_|db[7]~18_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_m1_ff1~q ), .cin(gnd), - .combout(\z80_|bus_control_|db[7]~5_combout ), + .combout(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N8 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( -// Equation(s): -// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|data_pins_|dout [7]), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|bus_control_|db[7]~5_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[7]~7_combout ), - .cout()); +// Location: FF_X40_Y11_N9 +dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), + .prn(vcc)); // synopsys translate_off -defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hBF0F; -defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; // synopsys translate_on -// Location: FF_X32_Y13_N21 -dffeas \z80_|ir_|opcode[7] ( +// Location: FF_X40_Y11_N7 +dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|bus_control_|db[7]~7_combout ), + .asdata(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [7]), + .q(\z80_|memory_ifc_|DFFE_m1_ff3~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[7] .power_up = "low"; +defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y13_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( +// Location: LCCOMB_X40_Y11_N6 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( // Equation(s): -// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) +// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # ((\z80_|memory_ifc_|DFFE_m1_ff3~q )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & +// (!\z80_|interrupts_|DFFE_inst44~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # (\z80_|memory_ifc_|DFFE_m1_ff3~q )))) - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), + .datac(\z80_|memory_ifc_|DFFE_m1_ff3~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~0_combout ), + .combout(\z80_|memory_ifc_|nRD_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0010; -defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hA8FC; +defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( +// Location: LCCOMB_X29_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~2 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|pla_decode_|Equal77~0_combout & (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~1_combout ))) +// \z80_|execute_|ctl_mRead~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal2~0_combout ))) - .dataa(\z80_|pla_decode_|Equal77~0_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal2~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~5_combout ), + .combout(\z80_|execute_|ctl_mRead~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( +// Location: LCCOMB_X38_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( // Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_ir_we~4_combout & (\z80_|pla_decode_|Equal8~0_combout & !\z80_|ir_|opcode [3]))) +// \z80_|execute_|fIORead~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hC080; +defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h0033; +defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~15_combout = (\z80_|execute_|ctl_mWrite~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal1~4_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( +// Equation(s): +// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hC080; +defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( +// Equation(s): +// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|ctl_alu_op_low~15_combout ) # ((\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|fIOWrite~0_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~10_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datac(\z80_|execute_|fIOWrite~0_combout ), + .datad(\z80_|execute_|fIORead~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFFCE; +defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( +// Equation(s): +// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|ctl_mRead~2_combout & \z80_|execute_|fIOWrite~1_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|fIORead~0_combout ), + .datac(\z80_|execute_|fIOWrite~1_combout ), + .datad(\z80_|execute_|fIORead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hAA00; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( +// Equation(s): +// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_im_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N23 +dffeas \z80_|interrupts_|im2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_im_we~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|im2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~10_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|im2~q ), + .datac(gnd), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~1_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ctl_mRead~30_combout ) # ((\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mRead~10_combout ), + .datac(\z80_|execute_|ctl_mRead~30_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'hFCF0; +defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [1]) # ((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~4_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFCF; +defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal44~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal44~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0010; +defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~6_combout = (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|DFFE_inst4~q ))) + + .dataa(\z80_|pla_decode_|Equal44~0_combout ), + .datab(\z80_|decode_state_|DFFE_instIY1~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( +// Equation(s): +// \z80_|execute_|fMRead~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|pla_decode_|Equal13~2_combout )) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMRead~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0202; +defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~17_combout = (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|fMWrite~0_combout & \z80_|execute_|fMRead~5_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|fMWrite~0_combout ), + .datad(\z80_|execute_|fMRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~12_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h00A0; +defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal49~0_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal77~0_combout & !\z80_|decode_state_|in_halt~q )) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal77~0_combout ), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal49~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h0808; +defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~57 ( +// Equation(s): +// \z80_|execute_|setM1~57_combout = (!\z80_|execute_|ctl_mRead~12_combout & (((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )) # (!\z80_|pla_decode_|Equal49~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~57 .lut_mask = 16'h5551; +defparam \z80_|execute_|setM1~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~15_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal25~0_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal25~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_ir_we~6_combout & (\z80_|pla_decode_|Equal55~0_combout & !\z80_|decode_state_|table_xx~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_ir_we~6_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|decode_state_|table_xx~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h3303; +defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( +// Equation(s): +// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( +// Equation(s): +// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) + + .dataa(\z80_|pla_decode_|Equal44~0_combout ), + .datab(\z80_|decode_state_|DFFE_instIY1~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hA080; +defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ixy_d~10_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ctl_mRead~3_combout & !\z80_|execute_|ctl_mRead~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~10_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( +// Equation(s): +// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_al_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0A00; +defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal29~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal29~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~38 ( +// Equation(s): +// \z80_|execute_|setM1~38_combout = (\z80_|execute_|fMRead~4_combout & (!\z80_|pla_decode_|Equal29~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) + + .dataa(\z80_|execute_|fMRead~4_combout ), + .datab(\z80_|pla_decode_|Equal29~0_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|setM1~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~38 .lut_mask = 16'h0202; +defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal35~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~33_combout = (!\z80_|pla_decode_|Equal35~0_combout & ((\z80_|ir_|opcode [4]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|pla_decode_|Equal24~0_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), .datad(\z80_|ir_|opcode [3]), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .combout(\z80_|execute_|pc_inc_hold~33_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'h0F0B; +defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( +// Location: LCCOMB_X38_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|comb~1 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) +// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .dataa(gnd), + .datab(\z80_|ir_|opcode [5]), + .datac(gnd), + .datad(\z80_|ir_|opcode [4]), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), + .combout(\z80_|execute_|comb~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; +defparam \z80_|execute_|comb~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( +// Location: LCCOMB_X38_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~8_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|M5~q & ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) +// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|comb~1_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), + .combout(\z80_|execute_|ctl_mRead~13_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h3020; -defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( +// Location: LCCOMB_X38_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) +// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|pla_decode_|Equal41~2_combout ))) - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .dataa(\z80_|execute_|ctl_mRead~13_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( +// Location: LCCOMB_X39_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) +// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|pc_inc_hold~33_combout & (!\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout )) - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), + .dataa(gnd), + .datab(\z80_|execute_|pc_inc_hold~33_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC8C0; -defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0C00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( +// Location: LCCOMB_X36_Y6_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~2 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~6_combout = (((\z80_|execute_|ctl_bus_db_we~4_combout ) # (!\z80_|execute_|ctl_sw_2u~3_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) +// \z80_|pla_decode_|Equal40~2_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [2]))) - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~4_combout ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [2]), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), + .combout(\z80_|pla_decode_|Equal40~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal40~2 .lut_mask = 16'h0010; +defparam \z80_|pla_decode_|Equal40~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( +// Location: LCCOMB_X36_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~36 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~3_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|execute_|ctl_bus_db_we~2_combout ) # (\z80_|execute_|ctl_bus_db_we~6_combout ))) +// \z80_|execute_|setM1~36_combout = (!\z80_|pla_decode_|Equal6~1_combout & (((!\z80_|ir_|opcode [5] & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal40~2_combout ))) - .dataa(\z80_|execute_|ctl_bus_db_we~3_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~6_combout ), + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|pla_decode_|Equal40~2_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), + .combout(\z80_|execute_|setM1~36_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; +defparam \z80_|execute_|setM1~36 .lut_mask = 16'h1115; +defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~50 ( +// Location: LCCOMB_X37_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~14 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) +// \z80_|execute_|pc_inc_hold~14_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|pla_decode_|Equal33~2_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|pla_decode_|Equal50~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~14 .lut_mask = 16'h1115; +defparam \z80_|execute_|pc_inc_hold~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~37 ( +// Equation(s): +// \z80_|execute_|setM1~37_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (\z80_|execute_|setM1~36_combout & (\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datab(\z80_|execute_|setM1~36_combout ), + .datac(\z80_|execute_|pc_inc_hold~14_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~37 .lut_mask = 16'h0080; +defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~14_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~39 ( +// Equation(s): +// \z80_|execute_|setM1~39_combout = (\z80_|execute_|setM1~57_combout & (\z80_|execute_|setM1~38_combout & (\z80_|execute_|setM1~37_combout & !\z80_|execute_|ctl_mRead~14_combout ))) + + .dataa(\z80_|execute_|setM1~57_combout ), + .datab(\z80_|execute_|setM1~38_combout ), + .datac(\z80_|execute_|setM1~37_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0080; +defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((!\z80_|execute_|setM1~39_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|ctl_mRead~17_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|setM1~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0011; +defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal40~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h4040; +defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal37~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0400; +defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~26_combout = (\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~2_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~16_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal12~0_combout & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal12~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~13_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~19_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~1_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal38~2_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|pla_decode_|Equal35~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~0 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N8 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~1_combout = (\z80_|pla_decode_|Equal24~1_combout ) # ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|reg_control_|reg_sys_we_lo~0_combout ) # (\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~1_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~0_combout ), + .datad(\z80_|pla_decode_|Equal29~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~1 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|reg_control_|reg_sys_we_lo~1_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # +// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|reg_control_|reg_sys_we_lo~1_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~1_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'h153F; +defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~18_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~20_combout = (\z80_|reg_control_|reg_sys_we_lo~2_combout & (((!\z80_|execute_|ctl_mRead~19_combout & !\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~19_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~22_combout = (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~20_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~16_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datab(\z80_|execute_|ctl_mRead~16_combout ), + .datac(\z80_|execute_|ctl_mRead~20_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~1_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|DFFE_instED~q & !\z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0008; +defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~23_combout = (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_mRead~14_combout & +// (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~14_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~27_combout = (\z80_|execute_|ctl_mRead~23_combout & (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal38~2_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|ctl_mRead~27_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~26_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mRead~22_combout ), + .datad(\z80_|execute_|ctl_mRead~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~3 ( +// Equation(s): +// \z80_|execute_|nextM~3_combout = (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|pla_decode_|Equal41~2_combout )) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ixy_d~10_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0011; +defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|execute_|nextM~3_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h8F00; +defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~31_combout ) # ((\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_mRead~29_combout ) # (!\z80_|execute_|ctl_mRead~28_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~31_combout ), + .datab(\z80_|execute_|ctl_mRead~32_combout ), + .datac(\z80_|execute_|ctl_mRead~28_combout ), + .datad(\z80_|execute_|ctl_mRead~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y11_N19 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mRead~33_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N28 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q .dataa(gnd), .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~50 .lut_mask = 16'h000F; -defparam \ula_|zx_keyboard_|keys[0][2]~50 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~52 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~52_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[0][2]~50_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[0][2]~50_combout & ((\ula_|zx_keyboard_|keys[0][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[0][2]~q ), - .datad(\ula_|zx_keyboard_|keys[0][2]~50_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~52_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~52 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][2]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N17 -dffeas \ula_|zx_keyboard_|keys[0][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][2]~52_combout ), +// Location: FF_X40_Y11_N29 +dffeas \z80_|memory_ifc_|wait_mrd ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][2]~q ), + .q(\z80_|memory_ifc_|wait_mrd~q ), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; +defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~48 ( +// Location: LCCOMB_X40_Y11_N10 +cycloneive_lcell_comb \z80_|memory_ifc_|DFFE_mrd_ff3~feeder ( // Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~48_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~48 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|keys[3][3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~49 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~49_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[6][4]~47_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout & (\ula_|zx_keyboard_|keys[1][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[1][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .datab(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~49 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][2]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N23 -dffeas \ula_|zx_keyboard_|keys[1][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N22 -cycloneive_lcell_comb \D[2]~35 ( -// Equation(s): -// \D[2]~35_combout = (\z80_|address_pins_|abus[8]~18_combout & (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) # (!\z80_|address_pins_|abus[8]~18_combout & (!\ula_|zx_keyboard_|keys[0][2]~q & -// ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) - - .dataa(\z80_|address_pins_|abus[8]~18_combout ), - .datab(\ula_|zx_keyboard_|keys[0][2]~q ), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\z80_|address_pins_|abus[9]~17_combout ), - .cin(gnd), - .combout(\D[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~35 .lut_mask = 16'hBB0B; -defparam \D[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~57 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~57_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]) +// \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout = \z80_|memory_ifc_|wait_mrd~q .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(gnd), .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\z80_|memory_ifc_|wait_mrd~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~57_combout ), + .combout(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~57 .lut_mask = 16'h3300; -defparam \ula_|zx_keyboard_|keys[5][2]~57 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~58 ( +// Location: FF_X40_Y11_N11 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N0 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~58_combout = (\ula_|zx_keyboard_|keys[5][2]~57_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[5][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[5][2]~57_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) +// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|wait_mrd~q ) - .dataa(\ula_|zx_keyboard_|keys[5][2]~57_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[5][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), + .dataa(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|wait_mrd~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~58_combout ), + .combout(\z80_|memory_ifc_|nRD_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~58 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][2]~58 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0055; +defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y18_N15 -dffeas \ula_|zx_keyboard_|keys[5][2] ( +// Location: LCCOMB_X40_Y11_N12 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~2_combout = (\z80_|memory_ifc_|nRD_out~0_combout ) # (((\z80_|execute_|fIORead~3_combout & \z80_|memory_ifc_|iorq~0_combout )) # (!\z80_|memory_ifc_|nRD_out~1_combout )) + + .dataa(\z80_|memory_ifc_|nRD_out~0_combout ), + .datab(\z80_|execute_|fIORead~3_combout ), + .datac(\z80_|memory_ifc_|iorq~0_combout ), + .datad(\z80_|memory_ifc_|nRD_out~1_combout ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hEAFF; +defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N12 +cycloneive_lcell_comb \Equal2~1 ( +// Equation(s): +// \Equal2~1_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nRD_out~2_combout )) + + .dataa(gnd), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nRD_out~2_combout ), + .cin(gnd), + .combout(\Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~1 .lut_mask = 16'h3000; +defparam \Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y34_N1 +cycloneive_io_ibuf \PS2_DAT~input ( + .i(PS2_DAT), + .ibar(gnd), + .o(\PS2_DAT~input_o )); +// synopsys translate_off +defparam \PS2_DAT~input .bus_hold = "false"; +defparam \PS2_DAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G9 +cycloneive_clkctrl \reset~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\reset~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\reset~clkctrl_outclk )); +// synopsys translate_off +defparam \reset~clkctrl .clock_type = "global clock"; +defparam \reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N18 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [1] & ((!\ula_|ps2_keyboard_|bit_count [2]) # (!\ula_|ps2_keyboard_|bit_count [3])))) # (!\ula_|ps2_keyboard_|bit_count [0] & +// (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [1]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [1]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h121A; +defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y34_N8 +cycloneive_io_ibuf \PS2_CLK~input ( + .i(PS2_CLK), + .ibar(gnd), + .o(\PS2_CLK~input_o )); +// synopsys translate_off +defparam \PS2_CLK~input .bus_hold = "false"; +defparam \PS2_CLK~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N24 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\PS2_CLK~input_o ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N25 +dffeas \ula_|ps2_keyboard_|clk_filter[7] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][2]~58_combout ), + .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49128,70 +10921,827 @@ dffeas \ula_|zx_keyboard_|keys[5][2] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][2]~q ), + .q(\ula_|ps2_keyboard_|clk_filter [7]), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; +defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~59 ( +// Location: LCCOMB_X17_Y27_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~59_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|extended~q ))) +// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|extended~q ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [7]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~59_combout ), + .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~59 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[4][2]~59 .sum_lutc_input = "datac"; +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~131 ( +// Location: FF_X17_Y27_N3 +dffeas \ula_|ps2_keyboard_|clk_filter[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~131_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[4][2]~59_combout & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [0]))) +// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [6]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N13 +dffeas \ula_|ps2_keyboard_|clk_filter[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N18 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N19 +dffeas \ula_|ps2_keyboard_|clk_filter[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [4]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N11 +dffeas \ula_|ps2_keyboard_|clk_filter[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N20 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [5] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [4] & !\ula_|ps2_keyboard_|clk_filter [6]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [5]), + .datab(\ula_|ps2_keyboard_|clk_filter [7]), + .datac(\ula_|ps2_keyboard_|clk_filter [4]), + .datad(\ula_|ps2_keyboard_|clk_filter [6]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N1 +dffeas \ula_|ps2_keyboard_|clk_filter[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N23 +dffeas \ula_|ps2_keyboard_|clk_filter[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|clk_filter [3] & (\ula_|ps2_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|clk_filter [1] & !\ula_|ps2_keyboard_|clk_filter [2]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [3]), + .datab(\ula_|ps2_keyboard_|Equal0~0_combout ), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0004; +defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N27 +dffeas \ula_|ps2_keyboard_|clk_filter[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|clk_filter [0])) # (!\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|ps2_clk_in~q ))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hAAF0; +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N7 +dffeas \ula_|ps2_keyboard_|ps2_clk_in ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|clk_filter [0] & !\ula_|ps2_keyboard_|ps2_clk_in~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datac(\ula_|ps2_keyboard_|clk_filter [0]), + .datad(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h00C0; +defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N17 +dffeas \ula_|ps2_keyboard_|clk_edge ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_edge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; +// synopsys translate_on + +// Location: FF_X18_Y12_N19 +dffeas \ula_|ps2_keyboard_|bit_count[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [2]))) # (!\ula_|ps2_keyboard_|bit_count [1] & +// (((\ula_|ps2_keyboard_|bit_count [3] & !\ula_|ps2_keyboard_|bit_count [2])))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [1]), + .datac(\ula_|ps2_keyboard_|bit_count [3]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h0830; +defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y12_N29 +dffeas \ula_|ps2_keyboard_|bit_count[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [0] & \ula_|ps2_keyboard_|bit_count [1]))))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [2]), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; +defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y12_N13 +dffeas \ula_|ps2_keyboard_|bit_count[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [2] & !\ula_|ps2_keyboard_|bit_count [1])) # (!\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [2]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [0]), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; +defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y12_N23 +dffeas \ula_|ps2_keyboard_|bit_count[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [2]) # (\ula_|ps2_keyboard_|bit_count [1]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [2]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCC88; +defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [3] & !\PS2_DAT~input_o ))) + + .dataa(\ula_|ps2_keyboard_|bit_count [2]), + .datab(\ula_|ps2_keyboard_|bit_count [1]), + .datac(\ula_|ps2_keyboard_|bit_count [3]), + .datad(\PS2_DAT~input_o ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (!\ula_|ps2_keyboard_|LessThan0~0_combout & (\ula_|ps2_keyboard_|clk_edge~q & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|always1~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h2030; +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y10_N5 +dffeas \ula_|ps2_keyboard_|shiftreg[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\PS2_DAT~input_o ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y10_N27 +dffeas \ula_|ps2_keyboard_|shiftreg[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [8]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y10_N13 +dffeas \ula_|ps2_keyboard_|shiftreg[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [7]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y8_N21 +dffeas \ula_|ps2_keyboard_|shiftreg[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [6]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y10_N31 +dffeas \ula_|ps2_keyboard_|shiftreg[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [5]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X20_Y8_N17 +dffeas \ula_|ps2_keyboard_|shiftreg[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [4]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X20_Y8_N31 +dffeas \ula_|ps2_keyboard_|shiftreg[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [3]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X20_Y8_N23 +dffeas \ula_|ps2_keyboard_|shiftreg[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [2]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y10_N23 +dffeas \ula_|ps2_keyboard_|shiftreg[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [1]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [6]))) .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[4][2]~59_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|zx_keyboard_|Equal0~0_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~131_combout ), + .combout(\ula_|zx_keyboard_|Equal0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~131 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[4][2]~131 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~60 ( +// Location: LCCOMB_X19_Y10_N4 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~60_combout = (\ula_|zx_keyboard_|keys[4][2]~131_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[4][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[4][2]~131_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) +// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [6]))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[4][2]~131_combout ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [8]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~60_combout ), + .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~60 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[4][2]~60 .sum_lutc_input = "datac"; +defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y18_N15 -dffeas \ula_|zx_keyboard_|keys[4][2] ( +// Location: LCCOMB_X19_Y10_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N24 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~0_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hC33C; +defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N24 +cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|WideXor0~2_combout & (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|LessThan0~0_combout ))) + + .dataa(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .datab(\PS2_DAT~input_o ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y12_N25 +dffeas \ula_|ps2_keyboard_|scan_code_ready ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][2]~60_combout ), + .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49200,86 +11750,175 @@ dffeas \ula_|zx_keyboard_|keys[4][2] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][2]~q ), + .q(\ula_|ps2_keyboard_|scan_code_ready~q ), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; +defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N4 -cycloneive_lcell_comb \D[2]~37 ( +// Location: LCCOMB_X20_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( // Equation(s): -// \D[2]~37_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][2]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) +// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|released~q ) # (\ula_|ps2_keyboard_|shiftreg [4])))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & +// (((\ula_|zx_keyboard_|released~q )))) - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~q ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~37 .lut_mask = 16'hBB0B; -defparam \D[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~53 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~53_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .dataa(\ula_|zx_keyboard_|Equal0~1_combout ), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|zx_keyboard_|released~q ), .datad(\ula_|ps2_keyboard_|shiftreg [4]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~53_combout ), + .combout(\ula_|zx_keyboard_|released~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~53 .lut_mask = 16'h00F0; -defparam \ula_|zx_keyboard_|keys[3][2]~53 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hB8B0; +defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~55 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~55_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) +// Location: FF_X20_Y9_N27 +dffeas \ula_|zx_keyboard_|released ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|released~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|released~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|released .power_up = "low"; +// synopsys translate_on - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), +// Location: LCCOMB_X21_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(gnd), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~55_combout ), + .combout(\ula_|zx_keyboard_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~55 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[2][2]~55 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h1010; +defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~56 ( +// Location: LCCOMB_X20_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~50 ( // Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~56_combout = (\ula_|zx_keyboard_|keys[2][2]~55_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~55_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) +// \ula_|zx_keyboard_|keys[3][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~50 .lut_mask = 16'h5500; +defparam \ula_|zx_keyboard_|keys[3][2]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( +// Equation(s): +// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|zx_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|extended~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hA0AA; +defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N1 +dffeas \ula_|zx_keyboard_|extended ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|extended~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|extended~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|extended .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~15 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~15_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~15 .lut_mask = 16'h0010; +defparam \ula_|zx_keyboard_|keys[7][4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~52 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~52_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[3][2]~50_combout & \ula_|zx_keyboard_|keys[7][4]~15_combout ))) + + .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .datad(\ula_|zx_keyboard_|keys[7][4]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~52_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~52 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[2][2]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~53 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~53_combout = (\ula_|zx_keyboard_|keys[2][2]~52_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~52_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), .datac(\ula_|zx_keyboard_|keys[2][2]~q ), - .datad(\ula_|zx_keyboard_|keys[2][2]~55_combout ), + .datad(\ula_|zx_keyboard_|keys[2][2]~52_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~56_combout ), + .combout(\ula_|zx_keyboard_|keys[2][2]~53_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~56 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[2][2]~56 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][2]~53 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[2][2]~53 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y20_N27 +// Location: FF_X20_Y9_N25 dffeas \ula_|zx_keyboard_|keys[2][2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][2]~56_combout ), + .d(\ula_|zx_keyboard_|keys[2][2]~53_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49295,28 +11934,27482 @@ defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~54 ( +// Location: LCCOMB_X31_Y14_N4 +cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~54_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][2]~53_combout & ((\ula_|zx_keyboard_|keys[3][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) +// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # +// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[3][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][2]~53_combout ), + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|resets_|clrpc_int~q ), + .datad(\z80_|resets_|x1~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~54_combout ), + .combout(\z80_|resets_|clrpc_int~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~54 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[3][2]~54 .sum_lutc_input = "datac"; +defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; +defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y20_N29 +// Location: FF_X31_Y14_N5 +dffeas \z80_|resets_|clrpc_int ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|clrpc_int~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|clrpc_int~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; +defparam \z80_|resets_|clrpc_int .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N0 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0F0F; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N1 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N14 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_9~feeder ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout = \z80_|resets_|SYNTHESIZED_WIRE_10~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .lut_mask = 16'hFF00; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N15 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y12_N27 +dffeas \z80_|resets_|DFFE_intr_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N26 +cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( +// Equation(s): +// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|clrpc_int~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|SYNTHESIZED_WIRE_10~q ))) + + .dataa(\z80_|resets_|clrpc_int~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .datac(\z80_|resets_|DFFE_intr_ff3~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .cin(gnd), + .combout(\z80_|resets_|clrpc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; +defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_al_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h4044; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~1_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal40~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal40~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal40~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; +defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal39~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal40~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal40~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0003; +defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal6~1_combout )) + + .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h000A; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ))) + + .dataa(\z80_|execute_|fMRead~2_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h0555; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_alu_oe~2_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h5554; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & ((\z80_|execute_|fMRead~2_combout ) # ((\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~14_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .datad(\z80_|execute_|fMRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h0F02; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~10_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_mRead~13_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'h0003; +defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~20_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hDFDF; +defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~4_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h33BB; +defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_reg_sys_hilo~20_combout & (((\z80_|execute_|ctl_inc_dec~4_combout )) # (!\z80_|pla_decode_|Equal33~3_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo~20_combout & +// (!\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datab(\z80_|pla_decode_|Equal33~3_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_inc_dec~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hAF23; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & ((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout +// )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00D0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~33_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|pc_inc_hold~33_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h50D0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & \z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|execute_|ctl_mRead~7_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .datac(\z80_|execute_|ctl_al_we~5_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h4044; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~13_combout = ((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'hF0D0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~16_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~12_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~16 .lut_mask = 16'h8808; +defparam \z80_|execute_|ctl_reg_sys_hilo~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~16_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_mWrite~9_combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h010F; +defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_al_we~13_combout & \z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'hB300; +defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|setM1~53_combout & (\z80_|execute_|ctl_reg_sel_pc~12_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~6_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~6 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_alu_bs_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~6_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~2_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal29~0_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout & +// (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|pla_decode_|Equal29~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; +defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal9~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h3777; +defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N0 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~1_combout & (\z80_|reg_control_|reg_sel_pc~0_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal38~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h7000; +defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal56~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal56~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~18_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~17_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|execute_|ctl_alu_op_low~17_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_oe~4_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~9_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_in_hi~4_combout & \z80_|execute_|ctl_reg_in_hi~3_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|execute_|ctl_mWrite~9_combout ) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~9_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h337F; +defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( +// Equation(s): +// \z80_|execute_|fMRead~6_combout = (\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|execute_|ctl_alu_op_low~14_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_mRead~13_combout )))) # +// (!\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N28 +cycloneive_lcell_comb \z80_|nM1_int~2 ( +// Equation(s): +// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|nM1_int~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|nM1_int~2 .lut_mask = 16'h000F; +defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_dec~3_combout & (\z80_|execute_|fMRead~6_combout & (!\z80_|nM1_int~2_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), + .datab(\z80_|execute_|fMRead~6_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~94 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~94_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~94_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~94 .lut_mask = 16'h7F7F; +defparam \z80_|execute_|ctl_inc_cy~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~50_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hF5F7; +defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ixy_d~16_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & +// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ixy_d~16_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~15_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ixy_d~10_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h373F; +defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~13_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h3F37; +defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & (\z80_|execute_|ctl_reg_sel_pc~4_combout & \z80_|execute_|ctl_reg_sel_pc~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & +// (!\z80_|pla_decode_|Equal12~1_combout & ((\z80_|pla_decode_|Equal25~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(\z80_|pla_decode_|Equal24~0_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'hB3A0; +defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|execute_|ctl_reg_sel_pc~8_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h020A; +defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~99 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~99_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~99_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~99 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_inc_cy~99 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~50_combout & (\z80_|execute_|ctl_reg_sel_pc~10_combout & \z80_|execute_|ctl_inc_cy~99_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), + .datab(\z80_|execute_|ctl_inc_cy~50_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .datad(\z80_|execute_|ctl_inc_cy~99_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & +// !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~9_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal47~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF1FF; +defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'hEAFF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~5_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal48~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal48~0_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal48~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h5444; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ))) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~13_combout = (\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout & !\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout )) # +// (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h131F; +defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h00FC; +defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((!\z80_|execute_|ctl_flags_bus~4_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hFF73; +defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( +// Equation(s): +// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|setM1~37_combout & (!\z80_|execute_|ctl_mRead~11_combout & (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal21~1_combout ))) + + .dataa(\z80_|execute_|setM1~37_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h0002; +defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~33_combout = (!\z80_|execute_|ctl_mRead~12_combout & ((\z80_|ir_|opcode [3]) # ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal12~0_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal12~0_combout ), + .datad(\z80_|execute_|ctl_mRead~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h00EF; +defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~35_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & (((\z80_|execute_|fMRead~7_combout & \z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) + + .dataa(\z80_|execute_|fMRead~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'h8C0C; +defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~34_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|pc_inc_hold~33_combout & ((!\z80_|decode_state_|use_ixiy~combout ) # (!\z80_|pla_decode_|Equal33~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|pla_decode_|Equal33~2_combout ), + .datac(\z80_|execute_|pc_inc_hold~33_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h1050; +defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_mWrite~9_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_mRead~34_combout +// & ((\z80_|execute_|ctl_mWrite~9_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~9_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~1_combout = (!\z80_|execute_|ctl_reg_sys_we~0_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'h0155; +defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal48~0_combout & \z80_|sequencer_|DFFE_T4_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~2_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~34_combout & \z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'hFF4F; +defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal8~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0])) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h4400; +defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~1_combout = (\z80_|execute_|ctl_reg_sys_we_lo~0_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( +// Equation(s): +// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal40~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal40~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|sel[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h2AAA; +defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & +// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal52~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h053F; +defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~7_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|execute_|ctl_state_alu~7_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hAA2A; +defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'h00EF; +defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~5_combout = (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|table_xx~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0002; +defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~10_combout = (\z80_|pla_decode_|Equal52~1_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # ((\z80_|execute_|ctl_state_alu~9_combout & \z80_|execute_|ctl_state_alu~5_combout )))) # (!\z80_|pla_decode_|Equal52~1_combout +// & (\z80_|execute_|ctl_state_alu~9_combout & ((\z80_|execute_|ctl_state_alu~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~9_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_state_alu~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'hECA0; +defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|pla_decode_|Equal52~1_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_state_alu~6_combout & +// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'hFA32; +defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~11_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hAAA2; +defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~5_combout = (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal62~2_combout )) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal62~2_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hF777; +defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hABFF; +defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~7_combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~7 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_alu_bs_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~7_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~19_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~19 .lut_mask = 16'hDDDF; +defparam \z80_|execute_|ctl_flags_xy_we~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~2_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~25_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~26_combout = ((!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|execute_|ctl_mRead~34_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_iorw~10_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~28_combout = (\z80_|execute_|ctl_alu_shift_oe~25_combout & (\z80_|execute_|ctl_alu_shift_oe~26_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~27_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~19_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal6~0_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hFF37; +defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~9_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|execute_|ctl_flags_bus~15_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h5070; +defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal20~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|comb~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal20~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal68~2_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|pla_decode_|Equal68~2_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF57; +defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal63~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|execute_|comb~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal63~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal76~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal76~2_combout = (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal76~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal76~2 .lut_mask = 16'h0A00; +defparam \z80_|pla_decode_|Equal76~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~8_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal76~2_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal76~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal32~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|execute_|ixy_d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~7_combout = ((!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_flags_bus~6_combout & !\z80_|pla_decode_|Equal13~2_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~6_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|execute_|ctl_flags_bus~9_combout & (\z80_|execute_|ctl_flags_bus~14_combout & (\z80_|execute_|ctl_flags_bus~8_combout & \z80_|execute_|ctl_flags_bus~7_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~9_combout ), + .datab(\z80_|execute_|ctl_flags_bus~14_combout ), + .datac(\z80_|execute_|ctl_flags_bus~8_combout ), + .datad(\z80_|execute_|ctl_flags_bus~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_bus_db_oe~3_combout & (\z80_|execute_|ctl_flags_xy_we~19_combout & (\z80_|execute_|ctl_alu_shift_oe~28_combout & \z80_|execute_|ctl_flags_bus~10_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datad(\z80_|execute_|ctl_flags_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf2_we~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h0155; +defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel~7_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|decode_state_|table_xx~0_combout ), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel~7 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~12_combout = ((\z80_|execute_|ctl_reg_gp_sel~7_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout ))) # (!\z80_|execute_|ctl_state_alu~7_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|ctl_state_alu~12_combout & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal62~3_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_alu_op_low~19_combout & !\z80_|execute_|ctl_iorw~10_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datab(\z80_|execute_|ctl_iorw~10_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'hFFF1; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~7_combout = (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~10 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~10_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~10 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_pf_sel[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~29_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hAAA2; +defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~11_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~11 .lut_mask = 16'hCCC4; +defparam \z80_|execute_|ctl_flags_pf_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & (\z80_|execute_|ctl_pf_sel[0]~10_combout & \z80_|execute_|ctl_flags_pf_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~10_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal10~1_combout = (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal10~1 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal10~1_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal10~1_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal69~0_combout = (\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal69~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'h0A02; +defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~8_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_pf_we~7_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~13 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~13_combout = (\z80_|ir_|opcode [5]) # (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_state_alu~12_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~13 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_pf_sel[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~10_combout = (((\z80_|execute_|ctl_flags_pf_we~9_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout )) # (!\z80_|execute_|ctl_flags_xy_we~11_combout )) # (!\z80_|execute_|ctl_flags_pf_we~5_combout ) + + .dataa(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N20 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~3_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'h0F1F; +defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~18_combout = (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N0 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|reg_control_|reg_sys_we_lo~3_combout & (\z80_|execute_|ctl_flags_xy_we~18_combout & ((!\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h40C0; +defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~5_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h7700; +defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N10 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~6_combout = (((\z80_|execute_|ctl_reg_sys_we_lo~1_combout & \z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~5_combout ) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'hDF5F; +defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout ) # ((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hFBFB; +defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~21_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (\z80_|execute_|ctl_mRead~20_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datac(\z80_|execute_|ctl_mRead~20_combout ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~21 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_sel_wz~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~20_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal35~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~20 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout = (\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|sequencer_|M5~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~44_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|M5~q ))) + + .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'hAA2A; +defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hF2F0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = (((\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'hF777; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout = ((\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~21_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h4040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~5_combout & ((\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~4_combout )))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_mRead~5_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h2333; +defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~1_combout = (\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((!\z80_|execute_|ctl_al_we~14_combout & \z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~14_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) + + .dataa(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'hABFF; +defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~47 ( +// Equation(s): +// \z80_|execute_|setM1~47_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|setM1~46_combout & !\z80_|execute_|ctl_mWrite~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_al_we~13_combout ), + .datac(\z80_|execute_|setM1~46_combout ), + .datad(\z80_|execute_|ctl_mWrite~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~47 .lut_mask = 16'h00C0; +defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|execute_|ctl_alu_oe~5_combout & !\z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|setM1~47_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~5_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|setM1~47_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ixy_d~6_combout & +// ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h2A3F; +defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( +// Equation(s): +// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal9~1_combout & ((!\z80_|pla_decode_|Equal29~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal9~1_combout & +// !\z80_|pla_decode_|Equal29~0_combout )) # (!\z80_|execute_|ctl_state_alu~3_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|pla_decode_|Equal29~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h0537; +defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( +// Equation(s): +// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~14_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal37~0_combout & +// !\z80_|execute_|ctl_mRead~14_combout )) # (!\z80_|execute_|ctl_state_alu~3_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~9 .lut_mask = 16'h111F; +defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( +// Equation(s): +// \z80_|execute_|fMRead~10_combout = (\z80_|execute_|fMRead~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|fMRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h3700; +defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|fMRead~8_combout & \z80_|execute_|fMRead~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datac(\z80_|execute_|fMRead~8_combout ), + .datad(\z80_|execute_|fMRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|pla_decode_|Equal11~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal4~0_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|execute_|comb~1_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|execute_|comb~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~41 ( +// Equation(s): +// \z80_|execute_|setM1~41_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal4~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~41 .lut_mask = 16'h003F; +defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal2~1_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal2~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & ((\z80_|execute_|setM1~41_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|setM1~41_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h0051; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~3_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~3_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_sw_1d~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datad(\z80_|execute_|ctl_sw_1d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & +// (!\z80_|execute_|ctl_alu_oe~2_combout & ((!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hC0DD; +defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sel_wz~11_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_sw_4d~4_combout & (\z80_|execute_|ctl_sw_4d~2_combout & (\z80_|execute_|ctl_sw_4d~3_combout & \z80_|execute_|ctl_reg_sel_wz~12_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~4_combout ), + .datab(\z80_|execute_|ctl_sw_4d~2_combout ), + .datac(\z80_|execute_|ctl_sw_4d~3_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~6_combout = (\z80_|execute_|ctl_sw_4d~1_combout ) # ((\z80_|execute_|ctl_sw_4d~0_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_4d~1_combout ), + .datac(\z80_|execute_|ctl_sw_4d~0_combout ), + .datad(\z80_|execute_|ctl_sw_4d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N30 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~4_combout = ((!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|alu_control_|flags_cond_true~q ) # (!\z80_|pla_decode_|Equal35~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~4 .lut_mask = 16'h337F; +defparam \z80_|reg_control_|reg_sel_pc~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((!\z80_|execute_|fMRead~4_combout & \z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .datab(\z80_|execute_|fMRead~4_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h7F5F; +defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~17_combout = (\z80_|nM1_int~2_combout ) # (((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|ctl_inc_dec~3_combout )) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_inc_dec~3_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'hBBFB; +defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~19_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal33~3_combout ), + .datac(\z80_|execute_|ctl_al_we~5_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'h4500; +defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal21~1_combout & ((!\z80_|pla_decode_|Equal52~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h030F; +defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sel_pc~14_combout ) # (!\z80_|execute_|setM1~37_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .datab(\z80_|execute_|setM1~37_combout ), + .datac(\z80_|execute_|fMRead~2_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hABAF; +defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~18_combout = (\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~17_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (!\z80_|execute_|ctl_sw_4u~1_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~19_combout = (((!\z80_|pla_decode_|Equal34~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_wz~19_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h0080; +defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~combout = (\z80_|reg_control_|reg_sel_pc~4_combout & (\z80_|reg_control_|reg_sel_pc~3_combout & ((\z80_|execute_|ctl_reg_sel_pc~18_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_pc~4_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~3_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h80A0; +defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h4040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~6_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal1~5_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N24 +cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( +// Equation(s): +// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal1~6_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|reg_control_|bank_exx~q ), + .datad(\z80_|pla_decode_|Equal1~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_exx~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y14_N25 +dffeas \z80_|reg_control_|bank_exx ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_exx~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_exx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_exx .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|execute_|ctl_state_alu~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal77~0_combout ), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hC0C4; +defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mWrite~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout ) # +// (!\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h0737; +defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~56 ( +// Equation(s): +// \z80_|execute_|setM1~56_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~56 .lut_mask = 16'hFF1F; +defparam \z80_|execute_|setM1~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (\z80_|execute_|ctl_sw_2u~4_combout & \z80_|execute_|setM1~56_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_2u~1_combout ), + .datac(\z80_|execute_|ctl_sw_2u~4_combout ), + .datad(\z80_|execute_|setM1~56_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|ir_|opcode [1] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'h30F0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|pla_decode_|Equal11~0_combout & (((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (\z80_|execute_|ctl_mRead~3_combout & +// ((\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hEEC0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~13_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hFF37; +defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & (\z80_|execute_|ctl_state_alu~13_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datac(\z80_|execute_|ctl_state_alu~13_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~61_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|execute_|ixy_d~5_combout & +// !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|execute_|ctl_mRead~14_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h0357; +defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~86_combout = (\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ixy_d~5_combout & +// !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'h111F; +defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~87_combout = (\z80_|execute_|ctl_inc_cy~86_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~86_combout ), + .datab(\z80_|pla_decode_|Equal29~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h222A; +defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~52 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~52_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~52 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_bus_inc_oe~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~49 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~49_combout = (\z80_|execute_|ctl_bus_inc_oe~52_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal4~0_combout )) # (!\z80_|sequencer_|DFFE_T5_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(\z80_|execute_|ctl_bus_inc_oe~52_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal4~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~49 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_bus_inc_oe~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_inc_cy~61_combout & (\z80_|execute_|ctl_bus_inc_oe~28_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_bus_inc_oe~49_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .datac(\z80_|execute_|ctl_inc_cy~87_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|fMRead~10_combout & (\z80_|execute_|fMRead~8_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_reg_gp_we~3_combout ))) + + .dataa(\z80_|execute_|fMRead~10_combout ), + .datab(\z80_|execute_|fMRead~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = ((!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h15FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~7_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h0105; +defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|execute_|ctl_alu_oe~7_combout & (((!\z80_|execute_|ctl_mRead~25_combout & !\z80_|execute_|ctl_mRead~24_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~25_combout ), + .datac(\z80_|execute_|ctl_mRead~24_combout ), + .datad(\z80_|execute_|ctl_alu_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & (\z80_|execute_|ctl_flags_pf_we~5_combout & (\z80_|execute_|ctl_pf_sel[0]~13_combout & \z80_|execute_|ctl_alu_oe~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .datad(\z80_|execute_|ctl_alu_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_mRead~4_combout & !\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (!\z80_|pla_decode_|Equal13~2_combout & (\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|ctl_flags_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~12_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [4]), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hCCFF; +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~8_combout = (!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ctl_alu_op_low~19_combout & (\z80_|execute_|ctl_flags_hf_cpl~12_combout & !\z80_|pla_decode_|Equal68~2_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .datad(\z80_|pla_decode_|Equal68~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~8 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_flags_hf_cpl~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~48 ( +// Equation(s): +// \z80_|execute_|setM1~48_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~48 .lut_mask = 16'h0013; +defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|pla_decode_|Equal20~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h0033; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~2 ( +// Equation(s): +// \z80_|execute_|nextM~2_combout = (!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|execute_|ctl_alu_op_low~18_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0003; +defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~49 ( +// Equation(s): +// \z80_|execute_|setM1~49_combout = (\z80_|execute_|ctl_flags_hf_cpl~8_combout & (\z80_|execute_|setM1~48_combout & (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & \z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), + .datab(\z80_|execute_|setM1~48_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~49 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~12_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|setM1~49_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_flags_oe~1_combout ), + .datad(\z80_|execute_|setM1~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'h0444; +defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~8_combout = (((\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal12~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h77F7; +defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_sw_1d~8_combout ), + .datac(\z80_|execute_|ctl_sw_1d~4_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h40F0; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|execute_|ctl_mRead~24_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|execute_|ctl_mRead~24_combout & +// (((!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal20~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~24_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_mWrite~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ctl_mWrite~8_combout & +// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (!\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~25_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|nextM~11 ( +// Equation(s): +// \z80_|execute_|nextM~11_combout = ((!\z80_|execute_|ctl_alu_op_low~18_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_mWrite~5_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~11 .lut_mask = 16'h5557; +defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|execute_|ctl_alu_op_low~18_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|nextM~11_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_bus_inc_oe~51_combout & \z80_|execute_|ctl_reg_use_sp~2_combout ))) + + .dataa(\z80_|execute_|nextM~11_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~51_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal6~1_combout )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0500; +defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~13_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_sw_1d~9_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .lut_mask = 16'h0133; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~12_combout = (!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & !\z80_|pla_decode_|Equal49~0_combout )) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_oe~3_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .lut_mask = 16'h0005; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & +// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'hF010; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # (\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~30 ( +// Equation(s): +// \z80_|execute_|setM1~30_combout = (\z80_|execute_|ctl_mRead~15_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|execute_|ctl_mRead~15_combout & +// (((!\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~30 .lut_mask = 16'h0777; +defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|ctl_mRead~23_combout & (\z80_|execute_|setM1~30_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ctl_mRead~23_combout ), + .datac(\z80_|execute_|setM1~30_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~14_combout = (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((!\z80_|execute_|ctl_reg_sys_hilo~20_combout & \z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h4F00; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|execute_|ctl_mRead~5_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal2~1_combout & \z80_|pla_decode_|Equal1~4_combout )))) + + .dataa(\z80_|pla_decode_|Equal2~1_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal4~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'hF080; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~20_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .lut_mask = 16'h3332; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~21_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal11~0_combout ))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h7F00; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ) # ((\z80_|ir_|opcode [2] & ((!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .datab(\z80_|execute_|ctl_sw_2u~5_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'hBFAA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|decode_state_|DFFE_instIY1~q ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|pla_decode_|Equal50~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hEEEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_mRead~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hA2AA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ) # ((\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & ((\z80_|sequencer_|M5~q ) # (\z80_|sequencer_|DFFE_M4_ff~q )))) + + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h1110; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~36_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [6] & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [7]))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|ir_|opcode [3] & (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal12~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hA2AF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~8_combout )) # (!\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout & \z80_|execute_|ctl_ir_we~6_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_ir_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hACA0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'hB030; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N2 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~2_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~2 .lut_mask = 16'h00F0; +defparam \z80_|reg_control_|reg_sel_de2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~4_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|decode_state_|DFFE_inst4~q & !\z80_|decode_state_|DFFE_instIY1~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'h0004; +defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N12 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((!\z80_|reg_control_|bank_exx~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal2~2_combout )))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|reg_control_|bank_hl_de1~q ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hE1F0; +defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N13 +dffeas \z80_|reg_control_|bank_hl_de1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N28 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~2_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~4_combout ))))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|reg_control_|reg_sel_de2~2_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|reg_control_|bank_hl_de1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h4450; +defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal8~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~50 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~50_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~50 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_bus_inc_oe~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_bus_inc_oe~50_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~50_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & (\z80_|execute_|ctl_reg_gp_we~2_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h1500; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|execute_|ixy_d~9_combout ) # +// (!\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h0737; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h3230; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # ((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|ctl_mRead~23_combout ) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ctl_mRead~23_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'hFBF3; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (\z80_|execute_|ctl_ir_we~7_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~20_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ) # ((\z80_|execute_|ctl_iorw~11_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .datab(\z80_|execute_|ctl_iorw~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h00A0; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'h0133; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # +// (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|rsel3 ( +// Equation(s): +// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(gnd), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|rsel3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel3 .lut_mask = 16'h5AAA; +defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = (\z80_|execute_|rsel3~combout & (((\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'h08CC; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_flags_oe~1_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h040F; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~14_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFDF0; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel~7_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|rsel0 ( +// Equation(s): +// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|rsel0~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel0 .lut_mask = 16'h66AA; +defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout & ((\z80_|execute_|rsel0~combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|execute_|setM1~49_combout )))) # +// (!\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|execute_|setM1~49_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|setM1~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'h888F; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal3~1_combout & !\z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_sw_1d~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~6_combout = (!\z80_|execute_|ctl_reg_in_hi~7_combout & (\z80_|execute_|ctl_state_alu~13_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & !\z80_|execute_|ctl_reg_in_hi~12_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .datab(\z80_|execute_|ctl_state_alu~13_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'h0004; +defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~9_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~16_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_sw_1d~9_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~9 .lut_mask = 16'h070F; +defparam \z80_|execute_|ctl_reg_gp_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'h0015; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (\z80_|execute_|ctl_reg_gp_we~9_combout & \z80_|execute_|ctl_alu_sel_op2_neg~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~9_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h5155; +defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~7_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & (\z80_|execute_|ctl_reg_gp_we~5_combout & \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((!\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h31F5; +defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|ctl_sw_4u~2_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datac(\z80_|execute_|ctl_sw_4u~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~8_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (((!\z80_|execute_|ctl_sw_4u~3_combout ) # (!\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(\z80_|execute_|ctl_sw_4u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~8 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_gp_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|reg_control_|reg_sel_hl~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N16 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|reg_control_|bank_exx~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal2~2_combout )))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; +defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N17 +dffeas \z80_|reg_control_|bank_hl_de2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de2~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~2_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~4_combout )))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|reg_control_|bank_hl_de2~q ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hA820; +defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|reg_control_|reg_sel_hl2~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|reg_control_|reg_sel_hl2~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|pla_decode_|Equal52~1_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_state_alu~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout = (\z80_|sequencer_|DFFE_M3_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal3~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal24~0_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|execute_|ctl_reg_in_hi~8_combout & (!\z80_|execute_|ctl_66_oe~2_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout & \z80_|execute_|ctl_reg_gp_we~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~8_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~21_combout ) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h070F; +defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|pla_decode_|Equal6~1_combout & !\z80_|execute_|ctl_mRead~2_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_sw_2d~6_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~8_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_alu_shift_oe~44_combout & \z80_|execute_|ctl_sw_2d~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .datad(\z80_|execute_|ctl_sw_2d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h5500; +defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N4 +cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( +// Equation(s): +// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|execute_|ctl_mRead~16_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & +// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( +// Equation(s): +// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~7_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~7_combout ), + .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h0888; +defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( +// Equation(s): +// \z80_|execute_|fMRead~20_combout = (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|ctl_mWrite~10_combout & (\z80_|execute_|fMRead~18_combout & \z80_|execute_|fMRead~19_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~10_combout ), + .datac(\z80_|execute_|fMRead~18_combout ), + .datad(\z80_|execute_|fMRead~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~20 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h1115; +defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Equation(s): +// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|fMRead~20_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_in_hi~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~22_combout ), + .datab(\z80_|execute_|fMRead~20_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~21 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h20AA; +defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & (\z80_|execute_|fMRead~21_combout & \z80_|execute_|ctl_sw_2d~5_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~8_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .datac(\z80_|execute_|fMRead~21_combout ), + .datad(\z80_|execute_|ctl_sw_2d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|pla_decode_|Equal49~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hAA8A; +defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (\z80_|execute_|ctl_sw_2d~9_combout & (!\z80_|execute_|ctl_sw_1d~5_combout & \z80_|execute_|ctl_sw_1d~4_combout ))) + + .dataa(\z80_|execute_|ctl_im_we~combout ), + .datab(\z80_|execute_|ctl_sw_2d~9_combout ), + .datac(\z80_|execute_|ctl_sw_1d~5_combout ), + .datad(\z80_|execute_|ctl_sw_1d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|execute_|ctl_66_oe~2_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7733; +defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~41_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~18_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~41 .lut_mask = 16'h3BFF; +defparam \z80_|execute_|ctl_alu_op_low~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal44~0_combout & ((\z80_|ir_|opcode [0]) # (!\z80_|execute_|comb~0_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|comb~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal44~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & !\z80_|execute_|ctl_reg_gp_sel~7_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~7_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|execute_|ctl_alu_op_low~17_combout & (((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) # (!\z80_|execute_|ctl_alu_op_low~17_combout & +// (\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0155; +defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~27_combout = ((\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~20_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~26_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & ((\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~41_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hF300; +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal61~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal61~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h222A; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~12_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~12 .lut_mask = 16'h3B3F; +defparam \z80_|execute_|ctl_alu_core_hf~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_core_hf~12_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & +// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~13_combout = (((!\z80_|execute_|ixy_d~6_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_flags_sz_we~3_combout & (\z80_|execute_|ctl_flags_alu~13_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & !\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datab(\z80_|execute_|ctl_flags_alu~13_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~15_combout = (\z80_|execute_|ctl_flags_alu~14_combout & (\z80_|execute_|ctl_flags_xy_we~9_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|execute_|ctl_flags_alu~14_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|nextM~11_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~16_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~17_combout = (\z80_|execute_|ctl_alu_op_low~16_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal20~0_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'hF070; +defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .lut_mask = 16'h010F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~39_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~39 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~16_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (!\z80_|execute_|ctl_alu_op_low~39_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~39_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h020A; +defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~17_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_alu~16_combout ))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datac(\z80_|execute_|ctl_sw_2d~4_combout ), + .datad(\z80_|execute_|ctl_flags_alu~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~23_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'h0F5F; +defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~18_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_alu_op_low~23_combout & \z80_|execute_|ctl_sw_4u~1_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datab(\z80_|execute_|ctl_flags_alu~17_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~11_combout = (((!\z80_|execute_|ctl_flags_alu~10_combout ) # (!\z80_|execute_|ctl_flags_alu~22_combout )) # (!\z80_|execute_|ctl_flags_alu~20_combout )) # (!\z80_|execute_|ctl_flags_alu~21_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~21_combout ), + .datab(\z80_|execute_|ctl_flags_alu~20_combout ), + .datac(\z80_|execute_|ctl_flags_alu~22_combout ), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal1~5_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal1~5_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .lut_mask = 16'h0050; +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFFC4; +defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~23 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~23_combout = (\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~23 .lut_mask = 16'hF040; +defparam \z80_|execute_|ctl_flags_alu~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_flags_alu~11_combout ) # (((\z80_|execute_|ctl_alu_core_R~1_combout ) # (\z80_|execute_|ctl_flags_alu~23_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~3_combout )) + + .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datad(\z80_|execute_|ctl_flags_alu~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~11_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .lut_mask = 16'hF5F1; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~6_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mWrite~17_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (((!\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~17 ( +// Equation(s): +// \z80_|execute_|setM1~17_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (!\z80_|execute_|ctl_alu_shift_oe~15_combout & \z80_|execute_|ctl_state_alu~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_2u~1_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~17 .lut_mask = 16'h0C00; +defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~22_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'h0015; +defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|execute_|setM1~17_combout & (!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|setM1~17_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_alu_oe~6_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & \z80_|execute_|ctl_flags_xy_we~18_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~6_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~11_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_flags_xy_we~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~19_combout = (((\z80_|execute_|ctl_flags_alu~12_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_alu~18_combout )) # (!\z80_|execute_|ctl_flags_alu~15_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), + .datab(\z80_|execute_|ctl_flags_alu~18_combout ), + .datac(\z80_|execute_|ctl_flags_alu~12_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~19 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_alu~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFFE0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( +// Equation(s): +// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~12_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # +// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~26 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal52~0_combout )) + + .dataa(\z80_|pla_decode_|Equal44~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'hEEAA; +defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~11_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_bus~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'hF070; +defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~13_combout = ((\z80_|execute_|ctl_flags_hf2_we~combout ) # (\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|fMRead~26_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|fMRead~26_combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'hFFF3; +defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~combout = ((\z80_|execute_|ctl_flags_bus~13_combout ) # ((!\z80_|execute_|ctl_flags_bus~10_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~28_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~3_combout ) + + .dataa(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datab(\z80_|execute_|ctl_flags_bus~13_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datad(\z80_|execute_|ctl_flags_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|alu_control_|db[1]~27_combout & \z80_|execute_|ctl_flags_bus~combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .datab(\z80_|alu_control_|db[1]~27_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEFA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~12_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|nextM~11_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFEAA; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = (\z80_|execute_|ctl_alu_op_low~39_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~39_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~18_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datad(\z80_|pla_decode_|Equal48~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~18 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h0507; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_ir_we~14_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout +// & (((!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_flags_alu~20_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~18_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~18_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~25_combout ) # (\z80_|execute_|ctl_mRead~24_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~19_combout ) + + .dataa(\z80_|execute_|ctl_mRead~25_combout ), + .datab(\z80_|execute_|ctl_mRead~24_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hE0FF; +defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~24_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'h0BFF; +defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ctl_alu_op_low~24_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'h2200; +defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~17_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .lut_mask = 16'h3230; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (!\z80_|execute_|ctl_alu_op1_sel_bus~17_combout & (!\z80_|execute_|ctl_alu_op_low~20_combout & ((!\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0105; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & \z80_|execute_|ctl_alu_shift_oe~38_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|execute_|ctl_ir_we~11_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|execute_|ctl_alu_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAA20; +defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~39_combout = ((\z80_|execute_|ctl_alu_shift_oe~37_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~42_combout = ((\z80_|execute_|ctl_alu_shift_oe~40_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # (!\z80_|execute_|ctl_alu_op_low~25_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hC0C8; +defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~8_combout = (\z80_|execute_|ctl_alu_bs_oe~12_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~7_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|execute_|ctl_ir_we~7_combout & (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # +// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h7740; +defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_ir_we~10_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h5540; +defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~36_combout = ((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~1_combout ) # (!\z80_|execute_|ctl_flags_bus~10_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .datac(\z80_|execute_|ctl_flags_bus~10_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~7_combout )))) # (!\z80_|execute_|ctl_bus_db_oe~1_combout & ((\z80_|execute_|ixy_d~7_combout ) +// # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~7_combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'hF444; +defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~29_combout = ((\z80_|execute_|ctl_alu_shift_oe~24_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~28_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~44_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_ir_we~7_combout & (((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~10_combout +// & (\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'hECE0; +defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~8_combout ) # ((\z80_|pla_decode_|Equal41~2_combout & \z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~23_combout = (!\z80_|execute_|ctl_alu_bs_oe~combout & (((\z80_|execute_|ixy_d~15_combout & !\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~23_combout ))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h020F; +defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) # +// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (\z80_|execute_|ctl_sw_4u~1_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~32_combout = (\z80_|execute_|ctl_alu_shift_oe~30_combout & (\z80_|execute_|ctl_alu_shift_oe~31_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~7_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~23_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~10_combout & ((\z80_|execute_|ctl_alu_shift_oe~29_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hCCEF; +defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~17_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h88A8; +defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~18_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h7740; +defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~18_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~18_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'h5F40; +defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_alu_shift_oe~19_combout ) # (\z80_|execute_|ctl_mWrite~9_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~19_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h7470; +defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~20_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~20_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'h5C4C; +defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~22_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~21_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h0E0C; +defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~36_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~22_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & +// (((!\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~2_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & \z80_|reg_control_|reg_sys_we_lo~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_ir_we~9_combout & +// (((!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_ir_we~10_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|nM1_int~2_combout & +// (((!\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & (!\z80_|execute_|ctl_alu_oe~15_combout & \z80_|execute_|ctl_alu_res_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datac(\z80_|execute_|ctl_alu_oe~15_combout ), + .datad(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~15_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_alu_res_oe~1_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datad(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'hA0E0; +defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~0_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hEFCF; +defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~0 ( +// Equation(s): +// \z80_|alu_|db_high[3]~0_combout = (\z80_|execute_|ctl_alu_bs_oe~combout ) # (((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (\z80_|execute_|ctl_alu_op1_oe~1_combout )) # (!\z80_|execute_|ctl_alu_res_oe~2_combout )) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~0 .lut_mask = 16'hFFFB; +defparam \z80_|alu_|db_high[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'h0103; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout & (\z80_|execute_|nextM~11_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .datac(\z80_|execute_|nextM~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~53 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|pla_decode_|Equal21~1_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_sw_2u~2_combout & ((!\z80_|execute_|ctl_mRead~6_combout ) # (!\z80_|execute_|ctl_alu_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2u~0_combout ), + .datab(\z80_|execute_|ctl_sw_2u~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_sw_2u~5_combout & (\z80_|execute_|ctl_reg_gp_sel~7_combout & (\z80_|ir_|opcode [0] $ (!\z80_|execute_|comb~0_combout )))) # (!\z80_|execute_|ctl_sw_2u~5_combout & ((\z80_|ir_|opcode [0] $ +// (!\z80_|execute_|comb~0_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2u~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'hD00D; +defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFAEA; +defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~3_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|rsel3~combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7077; +defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout & (!\z80_|execute_|ctl_sw_2u~6_combout & \z80_|execute_|ctl_reg_out_hi~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .datac(\z80_|execute_|ctl_sw_2u~6_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~7_combout = ((\z80_|execute_|ctl_reg_out_hi~8_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ))) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = ((\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|execute_|setM1~47_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datab(\z80_|execute_|setM1~47_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'h7F0F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'h0EFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~30_combout ) + + .dataa(\z80_|execute_|ctl_al_we~14_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|setM1~30_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'hDF0F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & !\z80_|execute_|rsel3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFCFD; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ) # ((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hFF75; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # (!\z80_|execute_|ctl_reg_gp_we~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h2202; +defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~15_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~6_combout = ((\z80_|execute_|ctl_reg_use_sp~5_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout )) # (!\z80_|execute_|ctl_reg_use_sp~3_combout ) + + .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hFF5F; +defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N26 +cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( +// Equation(s): +// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal21~2_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N27 +dffeas \z80_|reg_control_|bank_af ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_af~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_af~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_af .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N30 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h4040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~32 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[3]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~3_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~4_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~2_combout ))))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|reg_control_|bank_hl_de2~q ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~3 .lut_mask = 16'hA280; +defparam \z80_|reg_control_|reg_sel_de2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~4_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~2_combout )))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|reg_control_|reg_sel_de2~2_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|reg_control_|bank_hl_de1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h5044; +defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_de~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_de~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~31 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[3]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_iy~2_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|decode_state_|DFFE_inst4~q & \z80_|decode_state_|DFFE_instIY1~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hCC00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h4000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h3030; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|decode_state_|DFFE_inst4~q & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h4000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~34_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~34 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~15_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # (((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout )) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~16_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ctl_sw_4u~4_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h0015; +defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~50_combout & \z80_|execute_|ctl_inc_cy~99_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_cy~50_combout ), + .datad(\z80_|execute_|ctl_inc_cy~99_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & (\z80_|execute_|fMRead~6_combout & (\z80_|execute_|ctl_reg_sel_wz~16_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .datab(\z80_|execute_|fMRead~6_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~18_combout = ((\z80_|execute_|ctl_reg_sel_wz~15_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~21_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~17_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~18_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~18_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~36_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~36 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[3]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h1000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~33 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[3]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; +defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~10_combout = (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|execute_|ctl_reg_in_hi~10_combout ) # (!\z80_|execute_|ctl_reg_in_hi~9_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout )) # (!\z80_|execute_|ctl_reg_in_hi~3_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [3] & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[3]~14_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .datad(\z80_|alu_|db[3]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~37_combout = (\z80_|reg_file_|gdfx_temp1[3]~34_combout & (\z80_|reg_file_|gdfx_temp1[3]~36_combout & (\z80_|reg_file_|gdfx_temp1[3]~33_combout & \z80_|reg_file_|gdfx_temp1[3]~35_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~37 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~38_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout & (\z80_|reg_file_|gdfx_temp1[3]~32_combout & (\z80_|reg_file_|gdfx_temp1[3]~31_combout & \z80_|reg_file_|gdfx_temp1[3]~37_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~38 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # (((\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hEAFF; +defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~6_combout = ((\z80_|execute_|ctl_sw_4u~5_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~17_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout ))) # (!\z80_|execute_|ctl_sw_4u~3_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~3_combout ), + .datab(\z80_|execute_|ctl_sw_4u~5_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFEC; +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~11_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~16_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~39_combout = ((\z80_|reg_file_|gdfx_temp1[3]~38_combout & ((\z80_|reg_file_|db_hi_as[3]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~39 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|gdfx_temp1[3]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N24 +cycloneive_lcell_comb \z80_|alu_|db[3]~13 ( +// Equation(s): +// \z80_|alu_|db[3]~13_combout = (\z80_|alu_|db_low[3]~26_combout & (((\z80_|reg_file_|gdfx_temp1[3]~39_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) # (!\z80_|alu_|db_low[3]~26_combout & (!\z80_|execute_|ctl_alu_oe~14_combout & +// ((\z80_|reg_file_|gdfx_temp1[3]~39_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) + + .dataa(\z80_|alu_|db_low[3]~26_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .datad(\z80_|execute_|ctl_alu_oe~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~13 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~20_combout ) # (\z80_|execute_|ctl_alu_shift_oe~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hEEEA; +defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~11_combout )) # (!\z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|nextM~2_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|rsel3~combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'hC444; +defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~12_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal77~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h3313; +defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_2d~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~8_combout ), + .datac(\z80_|execute_|ctl_sw_2d~10_combout ), + .datad(\z80_|execute_|ctl_sw_2d~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hF2FA; +defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~12_combout ) # ((\z80_|execute_|ctl_sw_2d~11_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~12_combout ), + .datac(\z80_|execute_|ctl_sw_2d~11_combout ), + .datad(\z80_|execute_|ctl_sw_2d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~30_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ctl_mRead~24_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datac(\z80_|execute_|ctl_mWrite~11_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|execute_|ctl_bus_db_we~5_combout & (\z80_|execute_|ctl_alu_oe~9_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|ctl_alu_oe~4_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~5_combout ), + .datab(\z80_|execute_|ctl_alu_oe~9_combout ), + .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datad(\z80_|execute_|ctl_alu_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_alu_oe~10_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .datac(\z80_|execute_|ctl_alu_oe~10_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|alu_control_|db[3]~36_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_flags_alu~19_combout )))) # (!\z80_|alu_control_|db[3]~36_combout & +// (((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_flags_alu~19_combout )))) + + .dataa(\z80_|alu_control_|db[3]~36_combout ), + .datab(\z80_|execute_|ctl_flags_bus~combout ), + .datac(\z80_|alu_|db_low[3]~26_combout ), + .datad(\z80_|execute_|ctl_flags_alu~19_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_ir_we~12_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & \z80_|pla_decode_|Equal56~0_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal56~0_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~14_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_flags_xy_we~13_combout ) # (!\z80_|execute_|ctl_flags_xy_we~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hFFCF; +defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~15_combout = (\z80_|execute_|ctl_flags_xy_we~14_combout ) # (((!\z80_|execute_|ctl_flags_xy_we~17_combout ) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) + + .dataa(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|execute_|ctl_flags_sz_we~5_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # +// (!\z80_|execute_|ctl_alu_core_R~0_combout & (\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_flags_xy_we~15_combout ) # (((!\z80_|execute_|ctl_flags_pf_we~5_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) + + .dataa(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N19 +dffeas \z80_|alu_flags_|flags_xf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_xf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_xf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~50 ( +// Equation(s): +// \z80_|execute_|setM1~50_combout = (!\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|setM1~49_combout & ((!\z80_|pla_decode_|Equal3~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|setM1~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~50 .lut_mask = 16'h0700; +defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )) # (!\z80_|execute_|setM1~50_combout ))) + + .dataa(\z80_|execute_|setM1~50_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_flags_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h3133; +defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( +// Equation(s): +// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h1333; +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( +// Equation(s): +// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) + + .dataa(\z80_|alu_flags_|flags_xf~q ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(gnd), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'hBB00; +defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N0 +cycloneive_lcell_comb \z80_|sw1_|db_down[3]~3 ( +// Equation(s): +// \z80_|sw1_|db_down[3]~3_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_sw_1d~6_combout ), + .datab(\z80_|bus_control_|db[3]~21_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[3]~3 .lut_mask = 16'hECEE; +defparam \z80_|sw1_|db_down[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h5500; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h0808; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h4400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N9 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~51_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N7 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h4040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h0008; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[3]~36_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .datad(\z80_|alu_control_|db[3]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hC4C4; +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|decode_state_|DFFE_inst4~q & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h4000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h2000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0100; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0004; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & (\z80_|reg_file_|gdfx_temp0[3]~46_combout & \z80_|reg_file_|gdfx_temp0[3]~47_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_de~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~51_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_de~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N13 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~42 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[3]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N15 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~49_combout & (\z80_|reg_file_|gdfx_temp0[3]~42_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~42_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~91 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~91_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & ((\z80_|reg_control_|reg_sel_hl2~0_combout ) # (\z80_|reg_control_|reg_sel_hl~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~91_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~91 .lut_mask = 16'h2220; +defparam \z80_|reg_file_|gdfx_temp0[0]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # (\z80_|execute_|ctl_sw_4u~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~19_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~91_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ) # (\z80_|reg_file_|gdfx_temp0[0]~20_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~91_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal11~0_combout )) # +// (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h113F; +defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~43_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & (\z80_|execute_|ctl_bus_inc_oe~42_combout & (\z80_|execute_|ctl_bus_inc_oe~28_combout & !\z80_|execute_|ctl_reg_sys_we~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~88_combout = (\z80_|execute_|ctl_inc_cy~87_combout & (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_inc_cy~87_combout ), + .datac(\z80_|execute_|ctl_sw_4u~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_inc_cy~61_combout & (\z80_|execute_|ctl_inc_cy~88_combout & \z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), + .datab(\z80_|execute_|ctl_inc_cy~88_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~38_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|fMRead~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), + .datad(\z80_|execute_|fMRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hA8AA; +defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_bus_inc_oe~38_combout ) # (((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~49_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~32_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_mRead~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|pla_decode_|Equal13~2_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~47_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((!\z80_|execute_|ctl_bus_inc_oe~34_combout ) # (!\z80_|execute_|nextM~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~48_combout = (\z80_|execute_|ctl_bus_inc_oe~47_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~37_combout & (\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'hCCEC; +defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~46_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~4_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'h00C8; +defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_bus_inc_oe~39_combout ) # (((\z80_|execute_|ctl_bus_inc_oe~48_combout ) # (\z80_|execute_|ctl_bus_inc_oe~46_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~50_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~39_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~50_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~44_combout = (((\z80_|execute_|ctl_bus_inc_oe~40_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~6_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (\z80_|execute_|ctl_apin_mux~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datad(\z80_|execute_|ctl_apin_mux~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h0700; +defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|execute_|ctl_sw_4d~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~44_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~25 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~25_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|decode_state_|in_halt~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(gnd), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~25 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|pc_inc_hold~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~67_combout = ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout ) # (\z80_|execute_|ctl_mRead~2_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~64_combout = ((!\z80_|execute_|ctl_alu_op_low~14_combout & ((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) # (!\z80_|pla_decode_|Equal10~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h1F3F; +defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~65_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ) # (!\z80_|execute_|ctl_inc_cy~64_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout )) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .datad(\z80_|execute_|ctl_inc_cy~64_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~34_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h80A0; +defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~66_combout = ((\z80_|execute_|ctl_inc_cy~65_combout ) # (\z80_|execute_|ctl_inc_cy~63_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datab(\z80_|execute_|ctl_inc_cy~65_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_cy~63_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'hFFDD; +defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~66_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~67_combout ) # (!\z80_|execute_|fMRead~7_combout )))) + + .dataa(\z80_|execute_|fMRead~7_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_inc_cy~67_combout ), + .datad(\z80_|execute_|ctl_inc_cy~66_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hFFC4; +defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~58_combout = (\z80_|execute_|ctl_mWrite~6_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ixy_d~9_combout )))) # (!\z80_|execute_|ctl_mWrite~6_combout & +// (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'hECA0; +defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_inc_cy~58_combout ) # (((\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|execute_|ctl_inc_cy~99_combout )) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|execute_|ctl_inc_cy~58_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_inc_cy~99_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'hECFF; +defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~60_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_inc_cy~59_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datad(\z80_|execute_|ctl_inc_cy~59_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|ctl_inc_cy~97_combout ) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_inc_cy~97_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hEF0F; +defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~62_combout = ((\z80_|execute_|ctl_inc_cy~60_combout ) # ((\z80_|execute_|ctl_inc_cy~57_combout ) # (!\z80_|execute_|ctl_inc_cy~47_combout ))) # (!\z80_|execute_|ctl_inc_cy~61_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), + .datab(\z80_|execute_|ctl_inc_cy~60_combout ), + .datac(\z80_|execute_|ctl_inc_cy~57_combout ), + .datad(\z80_|execute_|ctl_inc_cy~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~18 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~18_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ctl_mRead~13_combout +// & (\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~18 .lut_mask = 16'hEAC8; +defparam \z80_|execute_|pc_inc_hold~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal33~2_combout & \z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal33~2_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~17 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~17_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # (!\z80_|execute_|pc_inc_hold~14_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|pc_inc_hold~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~17 .lut_mask = 16'hECFC; +defparam \z80_|execute_|pc_inc_hold~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~19 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~19_combout = (\z80_|pla_decode_|Equal6~1_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_mRead~8_combout & +// ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~19 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|pc_inc_hold~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~20 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~20_combout = (\z80_|execute_|pc_inc_hold~18_combout ) # ((\z80_|execute_|pc_inc_hold~17_combout ) # ((\z80_|execute_|pc_inc_hold~19_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~18_combout ), + .datab(\z80_|execute_|pc_inc_hold~17_combout ), + .datac(\z80_|execute_|pc_inc_hold~19_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~20 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|pc_inc_hold~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~36_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hA080; +defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~15 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~15_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~15 .lut_mask = 16'hFF57; +defparam \z80_|execute_|pc_inc_hold~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~16 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~16_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~16 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|pc_inc_hold~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~21 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~21_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|pc_inc_hold~15_combout & \z80_|execute_|pc_inc_hold~16_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~20_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|pc_inc_hold~15_combout ), + .datad(\z80_|execute_|pc_inc_hold~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~21 .lut_mask = 16'h1000; +defparam \z80_|execute_|pc_inc_hold~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|pc_inc_hold~25_combout & (((\z80_|execute_|ctl_inc_cy~62_combout & \z80_|execute_|pc_inc_hold~21_combout )))) # (!\z80_|execute_|pc_inc_hold~25_combout & ((\z80_|execute_|ctl_inc_cy~68_combout ) # +// ((\z80_|execute_|ctl_inc_cy~62_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~25_combout ), + .datab(\z80_|execute_|ctl_inc_cy~68_combout ), + .datac(\z80_|execute_|ctl_inc_cy~62_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hF454; +defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~52_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|pla_decode_|Equal24~0_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ixy_d~10_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ixy_d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hC800; +defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~22 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~22_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~22 .lut_mask = 16'hCCC0; +defparam \z80_|execute_|pc_inc_hold~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~23 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~23_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|pc_inc_hold~22_combout )))) # +// (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|pc_inc_hold~22_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|pc_inc_hold~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~23 .lut_mask = 16'hECA0; +defparam \z80_|execute_|pc_inc_hold~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~35_combout = (\z80_|execute_|pc_inc_hold~23_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|pc_inc_hold~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'hFF80; +defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~24 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~24_combout = (!\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout & (!\z80_|execute_|pc_inc_hold~34_combout & (!\z80_|execute_|pc_inc_hold~35_combout & \z80_|execute_|pc_inc_hold~21_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .datab(\z80_|execute_|pc_inc_hold~34_combout ), + .datac(\z80_|execute_|pc_inc_hold~35_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~24 .lut_mask = 16'h0100; +defparam \z80_|execute_|pc_inc_hold~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_inc_cy~52_combout & \z80_|execute_|pc_inc_hold~24_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~52_combout ), + .datac(gnd), + .datad(\z80_|execute_|pc_inc_hold~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~54_combout = (\z80_|execute_|ctl_mWrite~17_combout & (\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_inc_cy~53_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_inc_cy~53_combout ), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'h8088; +defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~74_combout = (((!\z80_|pla_decode_|Equal33~1_combout ) # (!\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~75_combout = ((!\z80_|execute_|pc_inc_hold~17_combout & (\z80_|execute_|ctl_inc_cy~74_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ))) # (!\z80_|execute_|pc_inc_hold~25_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|ctl_inc_cy~74_combout ), + .datac(\z80_|execute_|pc_inc_hold~25_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h0F4F; +defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~73_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|execute_|ctl_sw_4u~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), + .datab(\z80_|execute_|pc_inc_hold~20_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h3020; +defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~75_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_inc_cy~73_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~95 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~95_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~95_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~95 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_inc_cy~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~72_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|pc_inc_hold~15_combout & !\z80_|execute_|ctl_inc_cy~95_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~20_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|pc_inc_hold~15_combout ), + .datad(\z80_|execute_|ctl_inc_cy~95_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~27 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~27_combout = (\z80_|execute_|pc_inc_hold~18_combout ) # ((\z80_|execute_|pc_inc_hold~17_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~18_combout ), + .datab(\z80_|execute_|pc_inc_hold~17_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~27 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|pc_inc_hold~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~77_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & (\z80_|execute_|ctl_mRead~12_combout & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~78_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~77_combout ) # ((!\z80_|execute_|pc_inc_hold~17_combout & !\z80_|execute_|ctl_reg_sys_hilo~20_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|pc_inc_hold~17_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datad(\z80_|execute_|ctl_inc_cy~77_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'hAA02; +defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout ) # ((!\z80_|execute_|pc_inc_hold~27_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~27_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|ctl_inc_cy~78_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'hFF40; +defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # ((\z80_|execute_|pc_inc_hold~25_combout & ((\z80_|execute_|pc_inc_hold~20_combout ) # (!\z80_|execute_|pc_inc_hold~15_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), + .datab(\z80_|execute_|pc_inc_hold~15_combout ), + .datac(\z80_|execute_|pc_inc_hold~25_combout ), + .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFABA; +defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~71_combout = ((!\z80_|execute_|ctl_inc_cy~64_combout & (!\z80_|execute_|pc_inc_hold~34_combout & \z80_|execute_|pc_inc_hold~21_combout ))) # (!\z80_|execute_|ctl_inc_cy~70_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~64_combout ), + .datab(\z80_|execute_|pc_inc_hold~34_combout ), + .datac(\z80_|execute_|ctl_inc_cy~70_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h1F0F; +defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~76_combout ) # ((\z80_|execute_|ctl_inc_cy~72_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout ) # (\z80_|execute_|ctl_inc_cy~71_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), + .datab(\z80_|execute_|ctl_inc_cy~72_combout ), + .datac(\z80_|execute_|ctl_inc_cy~79_combout ), + .datad(\z80_|execute_|ctl_inc_cy~71_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & ((\z80_|execute_|pc_inc_hold~24_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) # +// (!\z80_|execute_|ctl_inc_cy~94_combout & (((\z80_|execute_|pc_inc_hold~24_combout )) # (!\z80_|execute_|pc_inc_hold~25_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), + .datab(\z80_|execute_|pc_inc_hold~25_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datad(\z80_|execute_|pc_inc_hold~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hF531; +defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~26 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~26_combout = (\z80_|execute_|pc_inc_hold~34_combout ) # ((\z80_|execute_|pc_inc_hold~35_combout ) # (!\z80_|execute_|pc_inc_hold~21_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|pc_inc_hold~34_combout ), + .datac(\z80_|execute_|pc_inc_hold~35_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~26 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|pc_inc_hold~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~56_combout = (\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|pc_inc_hold~26_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~55_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'hAAEA; +defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|execute_|ctl_inc_cy~69_combout ) # ((\z80_|execute_|ctl_inc_cy~54_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~56_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), + .datab(\z80_|execute_|ctl_inc_cy~54_combout ), + .datac(\z80_|execute_|ctl_inc_cy~80_combout ), + .datad(\z80_|execute_|ctl_inc_cy~56_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~85_combout = (((!\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|ctl_inc_cy~49_combout )) # (!\z80_|execute_|ctl_inc_cy~51_combout )) # (!\z80_|execute_|ctl_inc_cy~44_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), + .datab(\z80_|execute_|ctl_inc_cy~51_combout ), + .datac(\z80_|execute_|ctl_inc_cy~49_combout ), + .datad(\z80_|execute_|ctl_inc_cy~45_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~89 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~89_combout = (\z80_|execute_|ctl_inc_cy~85_combout ) # ((!\z80_|execute_|ctl_inc_cy~48_combout ) # (!\z80_|execute_|ctl_inc_cy~88_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~85_combout ), + .datab(\z80_|execute_|ctl_inc_cy~88_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_cy~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~89_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~89 .lut_mask = 16'hBBFF; +defparam \z80_|execute_|ctl_inc_cy~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~90 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~90_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~90_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~90 .lut_mask = 16'h0515; +defparam \z80_|execute_|ctl_inc_cy~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~91 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~91_combout = (\z80_|execute_|ctl_inc_cy~89_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_inc_cy~90_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~89_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_inc_cy~90_combout ), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~91_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~91 .lut_mask = 16'hEAEE; +defparam \z80_|execute_|ctl_inc_cy~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~84_combout = ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_inc_cy~83_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_inc_cy~96_combout ) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_inc_cy~83_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_inc_cy~96_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~100 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~100_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~100_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~100 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~100 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~92 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~92_combout = (\z80_|execute_|ctl_inc_cy~84_combout ) # ((\z80_|execute_|ctl_inc_cy~91_combout & ((\z80_|execute_|ctl_inc_cy~100_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~91_combout ), + .datab(\z80_|execute_|ctl_inc_cy~84_combout ), + .datac(\z80_|execute_|ctl_inc_cy~100_combout ), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~92_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~92 .lut_mask = 16'hECEE; +defparam \z80_|execute_|ctl_inc_cy~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~28_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~9_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'hC080; +defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~82_combout = (\z80_|execute_|pc_inc_hold~24_combout & (!\z80_|execute_|pc_inc_hold~28_combout & (\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout & \z80_|execute_|ctl_inc_cy~52_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~24_combout ), + .datab(\z80_|execute_|pc_inc_hold~28_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .datad(\z80_|execute_|ctl_inc_cy~52_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((!\z80_|execute_|pc_inc_hold~33_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datad(\z80_|execute_|pc_inc_hold~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'h8AAA; +defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|pc_inc_hold~22_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|pc_inc_hold~22_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|pc_inc_hold~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hF888; +defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|pc_inc_hold~29_combout ) # ((\z80_|execute_|pc_inc_hold~30_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~33_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|pc_inc_hold~33_combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|pc_inc_hold~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hFFF2; +defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|pc_inc_hold~31_combout ) # (((\z80_|execute_|pc_inc_hold~28_combout ) # (!\z80_|execute_|pc_inc_hold~24_combout )) # (!\z80_|execute_|ctl_inc_cy~52_combout )) + + .dataa(\z80_|execute_|pc_inc_hold~31_combout ), + .datab(\z80_|execute_|ctl_inc_cy~52_combout ), + .datac(\z80_|execute_|pc_inc_hold~28_combout ), + .datad(\z80_|execute_|pc_inc_hold~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~93 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~93_combout = (\z80_|execute_|ctl_inc_cy~82_combout ) # ((\z80_|execute_|ctl_inc_cy~92_combout & ((!\z80_|execute_|pc_inc_hold~25_combout ) # (!\z80_|execute_|pc_inc_hold~32_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~92_combout ), + .datab(\z80_|execute_|ctl_inc_cy~82_combout ), + .datac(\z80_|execute_|pc_inc_hold~32_combout ), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~93_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~93 .lut_mask = 16'hCEEE; +defparam \z80_|execute_|ctl_inc_cy~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N14 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~81_combout ), + .datac(\z80_|execute_|ctl_inc_cy~93_combout ), + .datad(\z80_|address_latch_|Q [0]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h03FC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N19 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y17_N17 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal47~0_combout & !\z80_|execute_|ctl_mRead~10_combout ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~10 ( +// Equation(s): +// \z80_|alu_control_|db[0]~10_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[0]~17_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|bus_control_|db[0]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~10 .lut_mask = 16'h4C0C; +defparam \z80_|alu_control_|db[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N31 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|alu_|db[0]~18_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[0]~18_combout & (!\z80_|execute_|ctl_reg_in_hi~11_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~27_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & (\z80_|reg_file_|gdfx_temp1[0]~24_combout & \z80_|reg_file_|gdfx_temp1[0]~26_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout & \z80_|reg_file_|gdfx_temp1[0]~28_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_inc_dec~4_combout )) # (!\z80_|execute_|fIOWrite~0_combout ))) + + .dataa(\z80_|execute_|fIOWrite~0_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~9_combout = (\z80_|execute_|ctl_inc_dec~8_combout ) # (((\z80_|ir_|opcode [3] & !\z80_|execute_|ctl_reg_gp_we~2_combout )) # (!\z80_|execute_|ctl_inc_dec~3_combout )) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .datac(\z80_|execute_|ctl_inc_dec~8_combout ), + .datad(\z80_|execute_|ctl_inc_dec~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hF2FF; +defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_dec~9_combout ), + .datad(\z80_|execute_|ctl_inc_dec~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hF0FF; +defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) + + .dataa(\z80_|address_latch_|Q [4]), + .datab(\z80_|execute_|ctl_inc_dec~5_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h5595; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h5F5F; +defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~11_combout = (((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|execute_|ctl_inc_dec~5_combout ), + .datac(\z80_|execute_|ctl_inc_dec~9_combout ), + .datad(\z80_|execute_|ctl_inc_dec~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ) + + .dataa(\z80_|address_latch_|Q [2]), + .datab(gnd), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h5A5A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N5 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y17_N3 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N5 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|execute_|ctl_reg_sel_wz~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N11 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h2220; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|DFFE_instCB~q & \z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_ir_we~5_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~6_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hECCC; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~9 ( +// Equation(s): +// \z80_|alu_|db_low[2]~9_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[3]~14_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[1]~16_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[3]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~9 .lut_mask = 16'hFC0C; +defparam \z80_|alu_|db_low[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~10 ( +// Equation(s): +// \z80_|alu_|db_low[2]~10_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~9_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~12_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(\z80_|alu_|db[2]~12_combout ), + .datad(\z80_|alu_|db_low[2]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~10 .lut_mask = 16'hFD75; +defparam \z80_|alu_|db_low[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~1 ( +// Equation(s): +// \z80_|alu_|db_high[3]~1_combout = (\z80_|alu_|db_high[3]~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|db_high[3]~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~1 .lut_mask = 16'hFFF0; +defparam \z80_|alu_|db_high[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~4_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'hFFF5; +defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~10 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & (\z80_|execute_|ctl_flags_pf_we~4_combout & \z80_|execute_|ctl_flags_hf_we~5_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datac(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .lut_mask = 16'h8080; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~17 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~17_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_iorw~10_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~17 .lut_mask = 16'h0054; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~18 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~18_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|ir_|opcode [4] & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~18 .lut_mask = 16'h2030; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~38_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~38 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_alu_op_low~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~11 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout = (!\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout & (\z80_|execute_|ctl_alu_op_low~38_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .lut_mask = 16'h1050; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~12 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & ((!\z80_|pla_decode_|Equal62~2_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .lut_mask = 16'h4C00; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~15_combout & ((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # +// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_alu_core_R~2_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_S~8_combout & \z80_|execute_|ctl_alu_core_R~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|execute_|ctl_ir_we~11_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~10_combout )))) # +// (!\z80_|execute_|ctl_ir_we~7_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_ir_we~10_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~10_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h222A; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~11_combout & \z80_|execute_|ctl_alu_core_R~3_combout +// ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFCD; +defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~9_combout = ((!\z80_|execute_|ctl_alu_core_S~11_combout ) # (!\z80_|execute_|ctl_alu_core_S~5_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_core_S~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'h77FF; +defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~combout = ((\z80_|execute_|ctl_alu_core_S~9_combout ) # ((\z80_|pla_decode_|Equal62~2_combout & \z80_|pla_decode_|Equal9~0_combout ))) # (!\z80_|execute_|ctl_alu_core_S~8_combout ) + + .dataa(\z80_|pla_decode_|Equal62~2_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_alu_core_S .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal73~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hE000; +defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~combout = ((\z80_|pla_decode_|Equal73~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~5_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout ))) # (!\z80_|execute_|ctl_alu_core_R~3_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~3_combout ), + .datab(\z80_|pla_decode_|Equal73~2_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~41_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hF3F3; +defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~29_combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # (!\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_alu_op_low~16_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~34_combout & (((\z80_|pla_decode_|Equal39~0_combout & +// \z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFA88; +defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~31_combout = ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~29_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) # (!\z80_|execute_|ctl_alu_op_low~25_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((\z80_|pla_decode_|Equal40~1_combout & +// \z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'hF8C8; +defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~40_combout = (\z80_|execute_|ctl_alu_op_low~32_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~40 .lut_mask = 16'hCCEC; +defparam \z80_|execute_|ctl_alu_op_low~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~33_combout = (\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'hE000; +defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~combout = (\z80_|execute_|ctl_alu_op_low~31_combout ) # ((\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~33_combout ) # (!\z80_|execute_|ctl_alu_op_low~23_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~33_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~59 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~58 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N11 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~61_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~61 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[7]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y12_N19 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~62_combout = (\z80_|alu_|db[7]~20_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ))) # (!\z80_|alu_|db[7]~20_combout & (!\z80_|execute_|ctl_reg_in_hi~11_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .datad(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~62 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[7]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N21 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~63 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[7]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~60 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~64_combout = (\z80_|reg_file_|gdfx_temp1[7]~61_combout & (\z80_|reg_file_|gdfx_temp1[7]~62_combout & (\z80_|reg_file_|gdfx_temp1[7]~63_combout & \z80_|reg_file_|gdfx_temp1[7]~60_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~61_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~62_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~63_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~60_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~64 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~65_combout = (\z80_|reg_file_|gdfx_temp1[7]~59_combout & (\z80_|reg_file_|gdfx_temp1[7]~58_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout & \z80_|reg_file_|gdfx_temp1[7]~64_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~59_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~58_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~64_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~65 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[7]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_control_|reg_sys_we_lo~combout ) # (!\z80_|execute_|ctl_reg_sel_ir~1_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'hF700; +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~16 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~16_combout = (\z80_|reg_file_|gdfx_temp1[7]~66_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~66_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~16 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[7]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N17 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[7]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~17 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~17_combout = (\z80_|reg_file_|db_hi_as[7]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[7]~16_combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~17 .lut_mask = 16'h88AA; +defparam \z80_|reg_file_|db_hi_as[7]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N25 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N1 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [1] & ((\z80_|alu_|db[1]~16_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[1]~16_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .datad(\z80_|alu_|db[1]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~10_combout & (\z80_|reg_file_|gdfx_temp1[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~11_combout & \z80_|reg_file_|gdfx_temp1[1]~12_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~8_combout & (\z80_|reg_file_|gdfx_temp1[1]~9_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout & \z80_|reg_file_|gdfx_temp1[1]~14_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hBB00; +defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N6 +cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( +// Equation(s): +// \z80_|address_latch_|abusz [8] = (\z80_|reg_file_|db_hi_as[0]~6_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [8]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h0A0A; +defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )) # (!\z80_|execute_|ctl_al_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~14_combout ), + .datab(\z80_|execute_|ctl_al_we~5_combout ), + .datac(\z80_|execute_|ctl_apin_mux~1_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hF070; +defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~9_combout = (\z80_|execute_|ctl_al_we~13_combout & (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & +// (((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h7770; +defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~9_combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) + + .dataa(\z80_|execute_|ctl_al_we~9_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEAFF; +defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~7_combout = ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_alu_oe~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~5_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .datad(\z80_|execute_|ctl_mWrite~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~8_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_al_we~7_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )) # (!\z80_|execute_|setM1~46_combout ))) + + .dataa(\z80_|execute_|setM1~46_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_al_we~4_combout ), + .datad(\z80_|execute_|ctl_al_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~10_combout ) # ((\z80_|execute_|ctl_al_we~8_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~6_combout ), + .datab(\z80_|execute_|ctl_al_we~10_combout ), + .datac(\z80_|execute_|ctl_al_we~8_combout ), + .datad(\z80_|execute_|ctl_sw_4d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~12_combout = (\z80_|execute_|ctl_al_we~11_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|setM1~53_combout )) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_al_we~11_combout ), + .datad(\z80_|execute_|setM1~53_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hF8FF; +defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N7 +dffeas \z80_|address_latch_|Q[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [8]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y15_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~82_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~82 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[7]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N25 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~81 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[7]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~12 ( +// Equation(s): +// \z80_|alu_control_|db[6]~12_combout = ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|execute_|ctl_flags_oe~2_combout )) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) + + .dataa(gnd), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~12 .lut_mask = 16'hFFF3; +defparam \z80_|alu_control_|db[6]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|alu_|db_high[3]~7_combout & ((\z80_|execute_|ctl_flags_alu~19_combout ) # ((\z80_|alu_control_|db[7]~37_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_high[3]~7_combout & +// (((\z80_|alu_control_|db[7]~37_combout & \z80_|execute_|ctl_flags_bus~combout )))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_flags_alu~19_combout ), + .datac(\z80_|alu_control_|db[7]~37_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~3_combout ) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N11 +dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( +// Equation(s): +// \z80_|alu_control_|db[7]~18_combout = (\z80_|alu_|db[7]~20_combout & (((!\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_|db[7]~20_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((!\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h4F44; +defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~19 ( +// Equation(s): +// \z80_|alu_control_|db[7]~19_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[7]~18_combout & ((\z80_|reg_file_|gdfx_temp0[7]~90_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .datad(\z80_|alu_control_|db[7]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~19 .lut_mask = 16'h00C4; +defparam \z80_|alu_control_|db[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~20 ( +// Equation(s): +// \z80_|alu_control_|db[7]~20_combout = (\z80_|alu_control_|db[7]~19_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datab(\z80_|bus_control_|db[7]~7_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|alu_control_|db[7]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~20 .lut_mask = 16'h4F00; +defparam \z80_|alu_control_|db[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~37 ( +// Equation(s): +// \z80_|alu_control_|db[7]~37_combout = (\z80_|alu_control_|db[7]~20_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|alu_control_|db[6]~12_combout & !\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datab(\z80_|alu_control_|db[6]~12_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|alu_control_|db[7]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~37 .lut_mask = 16'hFF01; +defparam \z80_|alu_control_|db[7]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~37_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|alu_control_|db[7]~37_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~90_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|gdfx_temp0[7]~84_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .datad(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y17_N29 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|gdfx_temp0[7]~87_combout & (\z80_|reg_file_|gdfx_temp0[7]~86_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & \z80_|reg_file_|gdfx_temp0[7]~83_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|gdfx_temp0[7]~82_combout & (\z80_|reg_file_|gdfx_temp0[7]~81_combout & \z80_|reg_file_|gdfx_temp0[7]~88_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~82_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~81_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~90_combout = ((\z80_|reg_file_|gdfx_temp0[7]~89_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .datab(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8AFF; +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[7]~90_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .datab(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) + + .dataa(gnd), + .datab(\z80_|address_latch_|Q [7]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h33CC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'h8AFF; +defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( +// Equation(s): +// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [7]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N3 +dffeas \z80_|address_latch_|Q[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [7]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [8] & !\z80_|address_latch_|Q +// [7])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [8] & \z80_|address_latch_|Q [7])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [8]), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h2008; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N18 +cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( +// Equation(s): +// \z80_|address_latch_|abusz [9] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[1]~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [9]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N19 +dffeas \z80_|address_latch_|Q[9] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [9]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y16_N21 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [2] & ((\z80_|alu_|db[2]~12_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[2]~12_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~44 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[2]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N17 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~45_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~45 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[2]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~42 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~43_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~43 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[2]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~46_combout = (\z80_|reg_file_|gdfx_temp1[2]~44_combout & (\z80_|reg_file_|gdfx_temp1[2]~45_combout & (\z80_|reg_file_|gdfx_temp1[2]~42_combout & \z80_|reg_file_|gdfx_temp1[2]~43_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~46 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~48_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~40 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~41 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~47_combout = (\z80_|reg_file_|gdfx_temp1[2]~46_combout & (\z80_|reg_file_|gdfx_temp1[2]~40_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout & \z80_|reg_file_|gdfx_temp1[2]~41_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~47 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~48_combout = ((\z80_|reg_file_|gdfx_temp1[2]~47_combout & ((\z80_|reg_file_|db_hi_as[2]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~48 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp1[2]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~10 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [2] & ((\z80_|reg_file_|gdfx_temp1[2]~48_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[2]~48_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~10 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|db_hi_as[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~11 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~11_combout = (\z80_|reg_file_|db_hi_as[2]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[2]~10_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~11 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|db_hi_as[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N22 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ +// (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [10]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~12 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~12_combout = ((\z80_|reg_file_|db_hi_as[2]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|reg_file_|db_hi_as[2]~11_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~12 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|db_hi_as[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N0 +cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( +// Equation(s): +// \z80_|address_latch_|abusz [10] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[2]~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [10]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N1 +dffeas \z80_|address_latch_|Q[10] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [10]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [9] & (!\z80_|execute_|ctl_inc_dec~11_combout & +// \z80_|address_latch_|Q [10])) # (!\z80_|address_latch_|Q [9] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [10])))) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [10]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h2400; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~50 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~49 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~51_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~51 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~52_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~52 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[4]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N8 +cycloneive_lcell_comb \z80_|alu_|db[4]~8 ( +// Equation(s): +// \z80_|alu_|db[4]~8_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~57_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[4]~33_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[4]~33_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~8 .lut_mask = 16'hF351; +defparam \z80_|alu_|db[4]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N2 +cycloneive_lcell_comb \z80_|alu_|db[4]~10 ( +// Equation(s): +// \z80_|alu_|db[4]~10_combout = ((\z80_|alu_|db[4]~8_combout & ((\z80_|alu_|db_high[0]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[4]~8_combout ), + .datad(\z80_|alu_|db_high[0]~25_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~10 .lut_mask = 16'hF575; +defparam \z80_|alu_|db[4]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~53_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [4] & ((\z80_|alu_|db[4]~10_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[4]~10_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .datad(\z80_|alu_|db[4]~10_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~53 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N25 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~54_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~54 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[4]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~55_combout = (\z80_|reg_file_|gdfx_temp1[4]~51_combout & (\z80_|reg_file_|gdfx_temp1[4]~52_combout & (\z80_|reg_file_|gdfx_temp1[4]~53_combout & \z80_|reg_file_|gdfx_temp1[4]~54_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~51_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~52_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~53_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~54_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~55 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~56_combout = (\z80_|reg_file_|gdfx_temp1[4]~50_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout & (\z80_|reg_file_|gdfx_temp1[4]~49_combout & \z80_|reg_file_|gdfx_temp1[4]~55_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~50_combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~49_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~55_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~56 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~57_combout = ((\z80_|reg_file_|gdfx_temp1[4]~56_combout & ((\z80_|reg_file_|db_hi_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~56_combout ), + .datac(\z80_|reg_file_|db_hi_as[4]~15_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~57 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|gdfx_temp1[4]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[4]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~13 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~13_combout = (\z80_|reg_file_|gdfx_temp1[4]~57_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[4]~57_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~13 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[4]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[4]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~14 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~14_combout = (\z80_|reg_file_|db_hi_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[4]~13_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~14 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|db_hi_as[4]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N14 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ +// (\z80_|address_latch_|Q [11]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [12]), + .datad(\z80_|address_latch_|Q [11]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hD278; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~15 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~15_combout = ((\z80_|reg_file_|db_hi_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datab(\z80_|reg_file_|db_hi_as[4]~14_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~15 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|db_hi_as[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N12 +cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( +// Equation(s): +// \z80_|address_latch_|abusz [12] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[4]~15_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(\z80_|reg_file_|db_hi_as[4]~15_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [12]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h3030; +defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N13 +dffeas \z80_|address_latch_|Q[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [12]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [12] & +// !\z80_|address_latch_|Q [11])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [12] & \z80_|address_latch_|Q [11])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [12]), + .datad(\z80_|address_latch_|Q [11]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2008; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h55AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[5]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~76 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[5]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~77 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[5]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~84_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~79_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~79 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[5]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op_low~23_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_alu_oe~3_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (((\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_66_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h0088; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFCC; +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N25 +dffeas \z80_|alu_|op1_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h00A0; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_zero~combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~18 ( +// Equation(s): +// \z80_|alu_|db_low[1]~18_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~12_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~18 .lut_mask = 16'hFA0A; +defparam \z80_|alu_|db_low[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~19 ( +// Equation(s): +// \z80_|alu_|db_low[1]~19_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[1]~18_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[1]~16_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[1]~16_combout ), + .datac(\z80_|alu_|db_low[1]~18_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~19 .lut_mask = 16'hF0CC; +defparam \z80_|alu_|db_low[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( +// Equation(s): +// \z80_|alu_|db_low[1]~16_combout = (\z80_|alu_|op1_low [1] & (((\z80_|alu_|op2_low [1])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_low [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [1]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_low [1]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op2_low [1]), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hAF23; +defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( +// Equation(s): +// \z80_|alu_|db_low[1]~15_combout = ((\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'h0F2F; +defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N27 +dffeas \z80_|alu_|result_lo[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N26 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( +// Equation(s): +// \z80_|alu_|db_low[1]~17_combout = (\z80_|alu_|db_low[1]~16_combout & (\z80_|alu_|db_low[1]~15_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) + + .dataa(\z80_|alu_|db_low[1]~16_combout ), + .datab(\z80_|alu_|db_low[1]~15_combout ), + .datac(\z80_|alu_|result_lo [1]), + .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'h8880; +defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~20 ( +// Equation(s): +// \z80_|alu_|db_low[1]~20_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[1]~19_combout & ((\z80_|alu_|db_low[1]~17_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~17_combout ) # +// (!\z80_|alu_|db_high[3]~0_combout )))) + + .dataa(\z80_|alu_|db_low[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[3]~0_combout ), + .datad(\z80_|alu_|db_low[1]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~20 .lut_mask = 16'hBB03; +defparam \z80_|alu_|db_low[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & \z80_|alu_|db_low[1]~20_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|alu_|db_low[1]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'hF000; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hAE00; +defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[1]~19_combout )))) + + .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|alu_|db_high[1]~19_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .lut_mask = 16'h00EA; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFFFC; +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N21 +dffeas \z80_|alu_|op1_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'hCE00; +defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [1]), + .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'hE200; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[1]~20_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .datad(\z80_|alu_|db_low[1]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h3230; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # (\z80_|execute_|ctl_alu_op2_sel_zero~combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFEFE; +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N9 +dffeas \z80_|alu_|op2_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~14_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y6_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout )) # (!\z80_|execute_|ctl_alu_op_low~41_combout +// )) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~10_combout & (\z80_|execute_|ctl_flags_alu~21_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & \z80_|execute_|ctl_alu_core_S~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datab(\z80_|execute_|ctl_flags_alu~21_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ) # ((!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ) # (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~2_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout +// )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFBF3; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout = (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[1]~20_combout )))) # +// (!\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[1]~20_combout )))) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datad(\z80_|alu_|db_low[1]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N11 +dffeas \z80_|alu_|op2_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~25_combout ) # (\z80_|execute_|ctl_mRead~24_combout )))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) + + .dataa(\z80_|execute_|ctl_mRead~25_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'hCF8F; +defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N16 +cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~2 ( +// Equation(s): +// \z80_|alu_|alu_op2[1]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [1]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [1])))) + + .dataa(\z80_|alu_|op2_low [1]), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|alu_|op2_high [1]), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[1]~2 .lut_mask = 16'h3C66; +defparam \z80_|alu_|alu_op2[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[1]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|alu_|alu_op2[1]~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hC808; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[1]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high +// [1])))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|alu_|alu_op2[1]~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0131; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hF1F1; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & (!\z80_|execute_|ctl_alu_core_S~combout & +// !\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h3337; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ) # +// ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'h3F0A; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & (\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_bus~16_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h3000; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N29 +dffeas \z80_|alu_|op1_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout = (\z80_|alu_|db_high[2]~13_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[2]~14_combout )))) # +// (!\z80_|alu_|db_high[2]~13_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[2]~14_combout )))) + + .dataa(\z80_|alu_|db_high[2]~13_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datad(\z80_|alu_|db_low[2]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h0A0A; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N3 +dffeas \z80_|alu_|op2_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( +// Equation(s): +// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op2_high [2]), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hAF23; +defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~8 ( +// Equation(s): +// \z80_|alu_|db_high[2]~8_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db[7]~20_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~8 .lut_mask = 16'hCFC0; +defparam \z80_|alu_|db_high[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( +// Equation(s): +// \z80_|alu_|db_high[2]~9_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[2]~8_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[6]~22_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(\z80_|alu_|db[6]~22_combout ), + .datad(\z80_|alu_|db_high[2]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'hFD75; +defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( +// Equation(s): +// \z80_|alu_|db_high[2]~11_combout = (!\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[4]~19_combout )) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'h4400; +defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( +// Equation(s): +// \z80_|alu_|db_high[2]~12_combout = (\z80_|alu_|db_high[2]~10_combout & (\z80_|alu_|db_high[2]~9_combout & ((\z80_|alu_|db_high[2]~11_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|alu_|db_high[2]~10_combout ), + .datac(\z80_|alu_|db_high[2]~9_combout ), + .datad(\z80_|alu_|db_high[2]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hC040; +defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( +// Equation(s): +// \z80_|alu_|db_high[2]~13_combout = ((\z80_|alu_|db_high[2]~12_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_high[2]~12_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hBBB3; +defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~68 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~75_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~67 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N25 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N19 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~72 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~70 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~69 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~71_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [6] & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .datad(\z80_|alu_|db[6]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~71 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~73_combout = (\z80_|reg_file_|gdfx_temp1[6]~72_combout & (\z80_|reg_file_|gdfx_temp1[6]~70_combout & (\z80_|reg_file_|gdfx_temp1[6]~69_combout & \z80_|reg_file_|gdfx_temp1[6]~71_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~73 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~74_combout = (\z80_|reg_file_|gdfx_temp1[6]~68_combout & (\z80_|reg_file_|gdfx_temp1[6]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout & \z80_|reg_file_|gdfx_temp1[6]~73_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~74 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N26 +cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( +// Equation(s): +// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~21_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h3300; +defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N27 +dffeas \z80_|address_latch_|Q[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [14]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datac(\z80_|address_latch_|Q [14]), + .datad(\z80_|execute_|ctl_inc_dec~11_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'hB478; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~19 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp1[6]~75_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[6]~75_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~19 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~20_combout = (\z80_|reg_file_|db_hi_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~19_combout ), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~20 .lut_mask = 16'hF030; +defparam \z80_|reg_file_|db_hi_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~21_combout = ((\z80_|reg_file_|db_hi_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[6]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~21 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_hi_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~75_combout = ((\z80_|reg_file_|gdfx_temp1[6]~74_combout & ((\z80_|reg_file_|db_hi_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~75 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|gdfx_temp1[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N16 +cycloneive_lcell_comb \z80_|alu_|db[6]~21 ( +// Equation(s): +// \z80_|alu_|db[6]~21_combout = (\z80_|alu_control_|db[6]~23_combout & (((\z80_|reg_file_|gdfx_temp1[6]~75_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[6]~23_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[6]~75_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) + + .dataa(\z80_|alu_control_|db[6]~23_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~21 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N26 +cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( +// Equation(s): +// \z80_|alu_|db[6]~22_combout = ((\z80_|alu_|db[6]~21_combout & ((\z80_|alu_|db_high[2]~13_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|alu_|db[6]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF755; +defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( +// Equation(s): +// \z80_|alu_|db_high[1]~16_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_|db[6]~22_combout ), + .datad(\z80_|alu_|db[4]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hF3C0; +defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( +// Equation(s): +// \z80_|alu_|db_high[1]~17_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[1]~16_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[5]~24_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datad(\z80_|alu_|db_high[1]~16_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hFC0C; +defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~14 ( +// Equation(s): +// \z80_|alu_|db_high[1]~14_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[4]~19_combout ), + .datab(\z80_|bus_control_|db[3]~21_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~14 .lut_mask = 16'h4F0F; +defparam \z80_|alu_|db_high[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( +// Equation(s): +// \z80_|alu_|db_high[1]~15_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [1]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_high [1]), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( +// Equation(s): +// \z80_|alu_|db_high[1]~18_combout = (\z80_|alu_|db_high[1]~14_combout & (\z80_|alu_|db_high[1]~15_combout & ((\z80_|alu_|db_high[1]~17_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[1]~17_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[1]~14_combout ), + .datad(\z80_|alu_|db_high[1]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hB000; +defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( +// Equation(s): +// \z80_|alu_|db_high[1]~19_combout = ((\z80_|alu_|db_high[1]~18_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datac(\z80_|alu_|db_high[1]~18_combout ), + .datad(\z80_|alu_|db_high[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'hE0FF; +defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N4 +cycloneive_lcell_comb \z80_|alu_|db[5]~23 ( +// Equation(s): +// \z80_|alu_|db[5]~23_combout = (\z80_|reg_file_|gdfx_temp1[5]~84_combout & (((\z80_|alu_control_|db[5]~17_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) # (!\z80_|reg_file_|gdfx_temp1[5]~84_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[5]~17_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[5]~17_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~23 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db[5]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N10 +cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( +// Equation(s): +// \z80_|alu_|db[5]~24_combout = ((\z80_|alu_|db[5]~23_combout & ((\z80_|alu_|db_high[1]~19_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[5]~23_combout ), + .datad(\z80_|alu_|db[7]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hB0FF; +defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~80_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [5] & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[5]~24_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~80 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[5]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~81_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~81 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[5]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~78 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[5]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~82_combout = (\z80_|reg_file_|gdfx_temp1[5]~79_combout & (\z80_|reg_file_|gdfx_temp1[5]~80_combout & (\z80_|reg_file_|gdfx_temp1[5]~81_combout & \z80_|reg_file_|gdfx_temp1[5]~78_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~79_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~80_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~81_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~78_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~82 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~83_combout = (\z80_|reg_file_|gdfx_temp1[5]~76_combout & (\z80_|reg_file_|gdfx_temp1[5]~77_combout & (\z80_|reg_file_|gdfx_temp1[5]~82_combout & \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~76_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~77_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~82_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~83 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~84_combout = ((\z80_|reg_file_|gdfx_temp1[5]~83_combout & ((\z80_|reg_file_|db_hi_as[5]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[5]~24_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~83_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~84 .lut_mask = 16'h8CFF; +defparam \z80_|reg_file_|gdfx_temp1[5]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[5]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~22 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~22_combout = (\z80_|reg_file_|gdfx_temp1[5]~84_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[5]~84_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~22 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[5]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~23 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~23_combout = (\z80_|reg_file_|db_hi_as[5]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .datab(\z80_|reg_file_|db_hi_as[5]~22_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~23 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_hi_as[5]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~24 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~24_combout = ((\z80_|reg_file_|db_hi_as[5]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[5]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~24 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_hi_as[5]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N20 +cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( +// Equation(s): +// \z80_|address_latch_|abusz [13] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[5]~24_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(\z80_|reg_file_|db_hi_as[5]~24_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [13]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h3030; +defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N21 +dffeas \z80_|address_latch_|Q[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [13]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q [13]) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [13]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h3C3C; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N6 +cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( +// Equation(s): +// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~18_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[7]~18_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h00AA; +defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N7 +dffeas \z80_|address_latch_|Q[15] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [15]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|address_latch_|Q [14]), + .datac(\z80_|execute_|ctl_inc_dec~7_combout ), + .datad(\z80_|execute_|ctl_inc_dec~6_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h3633; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N8 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~18 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~18_combout = ((\z80_|reg_file_|db_hi_as[7]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|reg_file_|db_hi_as[7]~17_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~18 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|db_hi_as[7]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~66_combout = ((\z80_|reg_file_|gdfx_temp1[7]~65_combout & ((\z80_|reg_file_|db_hi_as[7]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~65_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_hi_as[7]~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~66 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp1[7]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N4 +cycloneive_lcell_comb \z80_|alu_|db[7]~19 ( +// Equation(s): +// \z80_|alu_|db[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~66_combout & (((\z80_|alu_control_|db[7]~37_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~66_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[7]~37_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~19 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N18 +cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( +// Equation(s): +// \z80_|alu_|db[7]~20_combout = ((\z80_|alu_|db[7]~19_combout & ((\z80_|alu_|db_high[3]~7_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[7]~19_combout ), + .datad(\z80_|alu_|db_high[3]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hF575; +defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N8 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (((\z80_|alu_|db[7]~20_combout & \z80_|ir_|opcode [3])))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) # (!\z80_|ir_|opcode [3] & +// ((\z80_|alu_|db[7]~20_combout ))))) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|alu_|db[7]~20_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hE230; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((\z80_|alu_|db_low[3]~8_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_low[3]~8_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|alu_|db_high[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'hC0D0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 .lut_mask = 16'h00F8; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N5 +dffeas \z80_|alu_|op1_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|alu_|db_high[3]~7_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h0088; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N11 +dffeas \z80_|alu_|op1_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N18 +cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~0 ( +// Equation(s): +// \z80_|alu_|alu_op1[3]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [3]))) + + .dataa(\z80_|alu_|op1_low [3]), + .datab(\z80_|alu_|op1_high [3]), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[3]~0 .lut_mask = 16'hAACC; +defparam \z80_|alu_|alu_op1[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (\z80_|alu_|db_low[2]~14_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # +// (!\z80_|alu_|db_low[2]~14_combout & (\z80_|alu_|db_high[2]~13_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|alu_|db_low[2]~14_combout ), + .datab(\z80_|alu_|db_high[2]~13_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N7 +dffeas \z80_|alu_|op1_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [2]))))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|alu_|op1_high [2]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .lut_mask = 16'h88A0; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[2]~14_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|alu_|db_low[2]~14_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .lut_mask = 16'h0F08; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N31 +dffeas \z80_|alu_|op2_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N0 +cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~1 ( +// Equation(s): +// \z80_|alu_|alu_op2[2]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) + + .dataa(\z80_|alu_|op2_high [2]), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datad(\z80_|alu_|op2_low [2]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[2]~1 .lut_mask = 16'h636C; +defparam \z80_|alu_|alu_op2[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [2]))))) + + .dataa(\z80_|alu_|op1_low [2]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_high [2]), + .datad(\z80_|alu_|alu_op2[2]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0047; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[2]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) + + .dataa(\z80_|alu_|alu_op2[2]~1_combout ), + .datab(\z80_|alu_|op1_high [2]), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hA088; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_S~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFF0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hAAFB; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op1[3]~0_combout & ((\z80_|alu_|alu_op2[3]~0_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ))) # +// (!\z80_|alu_|alu_op1[3]~0_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & \z80_|alu_|alu_op2[3]~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(\z80_|alu_|alu_op1[3]~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_|alu_op2[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hEFAE; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout & (\z80_|execute_|ctl_flags_alu~19_combout & !\z80_|execute_|ctl_alu_core_R~combout )) + + .dataa(gnd), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|execute_|ctl_flags_alu~19_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'h00C0; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[0]~14_combout )) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datac(gnd), + .datad(\z80_|alu_control_|db[0]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hEECC; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~4_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) + + .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_bus~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hBAFA; +defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~6_combout = (\z80_|execute_|ctl_flags_cf_we~3_combout ) # (((\z80_|execute_|ctl_flags_cf_we~5_combout ) # (!\z80_|execute_|ctl_flags_hf_we~2_combout )) # (!\z80_|execute_|ctl_flags_cf_we~2_combout )) + + .dataa(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datac(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~4_combout = ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal0~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal0~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~6 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_cf2_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~5_combout = (\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~6_combout ) # ((\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_we~6_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~5 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_flags_cf2_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~5_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~5_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'hF0B8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N21 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N2 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h20A8; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N30 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((!\z80_|ir_|opcode [4] & \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout )) + + .dataa(\z80_|ir_|opcode [4]), + .datab(gnd), + .datac(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hFF50; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( +// Equation(s): +// \z80_|alu_|db_low[0]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_|db[1]~16_combout ), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hF3C0; +defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( +// Equation(s): +// \z80_|alu_|db_low[0]~22_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[0]~21_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[0]~18_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datab(\z80_|alu_|db[0]~18_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[0]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hEF4F; +defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|db_high[0]~25_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & \z80_|alu_|db_low[0]~27_combout )))) # +// (!\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & (\z80_|alu_|db_low[0]~27_combout ))) + + .dataa(\z80_|alu_|db_high[0]~25_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(\z80_|alu_|db_low[0]~27_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N31 +dffeas \z80_|alu_|op1_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~24 ( +// Equation(s): +// \z80_|alu_|db_low[0]~24_combout = (\z80_|alu_|op2_low [0] & (((\z80_|alu_|op1_low [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_low [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [0]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op1_low [0]), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~24 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_low[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N23 +dffeas \z80_|alu_|result_lo[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( +// Equation(s): +// \z80_|alu_|db_low[0]~23_combout = ((!\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'h0F1F; +defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~25 ( +// Equation(s): +// \z80_|alu_|db_low[0]~25_combout = (\z80_|alu_|db_low[0]~24_combout & (\z80_|alu_|db_low[0]~23_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [0])))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(\z80_|alu_|db_low[0]~24_combout ), + .datac(\z80_|alu_|result_lo [0]), + .datad(\z80_|alu_|db_low[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~25 .lut_mask = 16'hC800; +defparam \z80_|alu_|db_low[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~27 ( +// Equation(s): +// \z80_|alu_|db_low[0]~27_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[0]~22_combout & (\z80_|alu_|db_low[0]~25_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[0]~22_combout & +// \z80_|alu_|db_low[0]~25_combout )) # (!\z80_|alu_|db_high[3]~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_low[0]~22_combout ), + .datac(\z80_|alu_|db_low[0]~25_combout ), + .datad(\z80_|alu_|db_high[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~27 .lut_mask = 16'hC0D5; +defparam \z80_|alu_|db_low[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])))) + + .dataa(\z80_|alu_|op1_high [0]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [0]), + .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hE200; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[0]~27_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|alu_|db_low[0]~27_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h0F08; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N15 +dffeas \z80_|alu_|op2_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_high[0]~25_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[0]~27_combout )))) # +// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[0]~27_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|db_high[0]~25_combout ), + .datad(\z80_|alu_|db_low[0]~27_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N17 +dffeas \z80_|alu_|op2_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N10 +cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( +// Equation(s): +// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|alu_|op2_high [0]), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h1DE2; +defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_R~3_combout )) # +// (!\z80_|execute_|ctl_alu_core_S~8_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h1FFF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~34_combout = (((\z80_|execute_|ctl_alu_op_low~29_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_alu_op_low~41_combout )) # (!\z80_|execute_|ctl_alu_op_low~25_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~36_combout = (\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~36 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|ctl_alu_op_low~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~35_combout = (\z80_|execute_|ctl_alu_op_low~33_combout ) # ((\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~33_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~35 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op_low~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~13_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~13 .lut_mask = 16'hD0C0; +defparam \z80_|execute_|ctl_alu_core_hf~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~14_combout = (\z80_|ir_|opcode [5]) # (((!\z80_|pla_decode_|Equal9~0_combout & !\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout )) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~14 .lut_mask = 16'hCFDF; +defparam \z80_|execute_|ctl_alu_core_hf~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~15_combout = (\z80_|execute_|ctl_alu_core_hf~14_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~15 .lut_mask = 16'h8CCC; +defparam \z80_|execute_|ctl_alu_core_hf~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~16_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~15_combout )) # (!\z80_|execute_|ctl_alu_core_hf~12_combout ) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~16 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|ctl_alu_core_hf~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~17_combout = (\z80_|execute_|ctl_alu_op_low~36_combout & (!\z80_|execute_|ctl_alu_op_low~35_combout & ((\z80_|execute_|ctl_alu_core_hf~16_combout )))) # (!\z80_|execute_|ctl_alu_op_low~36_combout & +// ((\z80_|execute_|ctl_alu_core_hf~13_combout ) # ((!\z80_|execute_|ctl_alu_op_low~35_combout & \z80_|execute_|ctl_alu_core_hf~16_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~36_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~13_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~17 .lut_mask = 16'h7350; +defparam \z80_|execute_|ctl_alu_core_hf~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|execute_|ixy_d~6_combout ) # ((!\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ixy_d~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hF3F0; +defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout & !\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'h88C8; +defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ctl_alu_op_low~18_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~23_combout = (!\z80_|execute_|ctl_alu_op_low~27_combout & ((\z80_|execute_|ctl_alu_core_hf~36_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|execute_|ctl_alu_op_low~17_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h0E0A; +defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~34_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'h1333; +defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~29_combout = (\z80_|execute_|ctl_mRead~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((!\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'hB0A0; +defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|execute_|ctl_mRead~4_combout +// & (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal56~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_alu_op_low~17_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((\z80_|execute_|ixy_d~7_combout ) # (\z80_|execute_|ctl_alu_core_hf~35_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & +// (((\z80_|execute_|ctl_alu_core_hf~35_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'h7740; +defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~28_combout = (\z80_|execute_|ctl_alu_core_hf~26_combout & ((\z80_|execute_|ctl_alu_core_hf~27_combout ) # ((\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'hAA80; +defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~34_combout & ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # (\z80_|execute_|ctl_alu_core_hf~28_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~37_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (((\z80_|execute_|ctl_alu_op_low~20_combout ) # (!\z80_|execute_|ctl_state_alu~11_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|execute_|ctl_state_alu~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~37 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_op_low~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_state_alu~2_combout & (((\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # +// (\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'hFC20; +defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~25_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (!\z80_|execute_|ctl_alu_op_low~20_combout & ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_alu_core_hf~24_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'h0032; +defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~31_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((\z80_|execute_|ctl_alu_core_hf~25_combout ) # ((\z80_|execute_|ctl_alu_core_hf~30_combout & !\z80_|execute_|ctl_alu_op_low~37_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~37_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'hFFAE; +defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~20_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hD0C0; +defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~20_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hCEEE; +defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~18_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~18_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~22_combout = (\z80_|execute_|ctl_alu_op_low~34_combout & (((!\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_alu_core_hf~19_combout )))) # (!\z80_|execute_|ctl_alu_op_low~34_combout & +// ((\z80_|execute_|ctl_alu_core_hf~21_combout ) # ((!\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_alu_core_hf~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'h4F44; +defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((\z80_|execute_|ctl_alu_core_hf~22_combout ) # ((\z80_|execute_|ctl_alu_core_hf~38_combout & !\z80_|execute_|ctl_alu_op_low~31_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hFCFE; +defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~33_combout = (\z80_|execute_|ctl_alu_core_hf~17_combout ) # ((\z80_|execute_|ctl_alu_core_hf~32_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N20 +cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( +// Equation(s): +// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~33_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~33_combout & (\z80_|alu_flags_|flags_cf~combout )) + + .dataa(\z80_|alu_flags_|flags_cf~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .datad(\z80_|alu_flags_|flags_hf~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hFA0A; +defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[0]~1_combout & \z80_|alu_control_|alu_core_cf_in~0_combout )))) +// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_control_|alu_core_cf_in~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[0]~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_|alu_op1[0]~1_combout ), + .datad(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( +// Equation(s): +// \z80_|alu_|db_high[0]~21_combout = (\z80_|alu_|op2_high [0] & (((\z80_|alu_|op1_high [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_high [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [0]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|alu_|op2_high [0]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|alu_|op1_high [0]), + .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N16 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( +// Equation(s): +// \z80_|alu_|db_high[0]~22_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~14_combout )) + + .dataa(\z80_|ir_|opcode [3]), + .datab(gnd), + .datac(\z80_|alu_|db[3]~14_combout ), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hFA50; +defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N2 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( +// Equation(s): +// \z80_|alu_|db_high[0]~23_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[0]~22_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[4]~10_combout )) + + .dataa(\z80_|alu_|db[4]~10_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(gnd), + .datad(\z80_|alu_|db_high[0]~22_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hEE22; +defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~20 ( +// Equation(s): +// \z80_|alu_|db_high[0]~20_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[4]~19_combout ), + .datab(\z80_|bus_control_|db[3]~21_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~20 .lut_mask = 16'h1F0F; +defparam \z80_|alu_|db_high[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( +// Equation(s): +// \z80_|alu_|db_high[0]~24_combout = (\z80_|alu_|db_high[0]~21_combout & (\z80_|alu_|db_high[0]~20_combout & ((\z80_|alu_|db_high[0]~23_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[0]~21_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[0]~23_combout ), + .datad(\z80_|alu_|db_high[0]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hA200; +defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( +// Equation(s): +// \z80_|alu_|db_high[0]~25_combout = ((\z80_|alu_|db_high[0]~24_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datac(\z80_|alu_|db_high[0]~24_combout ), + .datad(\z80_|alu_|db_high[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'hE0FF; +defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(\z80_|alu_|db_high[0]~25_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h0088; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N23 +dffeas \z80_|alu_|op1_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( +// Equation(s): +// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_high [0]), + .datad(\z80_|alu_|op1_low [0]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hFC30; +defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|alu_|op2_high [0]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hE2E2; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_|alu_op1[0]~1_combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|alu_|alu_op1[0]~1_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hBE28; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|execute_|ctl_alu_core_R~combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|execute_|ctl_alu_core_S~combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(\z80_|execute_|ctl_alu_core_R~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h0032; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h0F0E; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55F7; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hF2A2; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N19 +dffeas \z80_|alu_|result_lo[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~11 ( +// Equation(s): +// \z80_|alu_|db_low[2]~11_combout = (\z80_|alu_|result_lo [2]) # (\z80_|execute_|ctl_alu_res_oe~2_combout ) + + .dataa(gnd), + .datab(\z80_|alu_|result_lo [2]), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~11 .lut_mask = 16'hFFCC; +defparam \z80_|alu_|db_low[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N2 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~12 ( +// Equation(s): +// \z80_|alu_|db_low[2]~12_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [2] & ((\z80_|alu_|op2_low [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [2]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_low [2]), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~12 .lut_mask = 16'hDD0D; +defparam \z80_|alu_|db_low[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h5500; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~13 ( +// Equation(s): +// \z80_|alu_|db_low[2]~13_combout = (\z80_|alu_|db_low[2]~12_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|alu_|db_low[2]~12_combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~13 .lut_mask = 16'h7050; +defparam \z80_|alu_|db_low[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N28 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~14 ( +// Equation(s): +// \z80_|alu_|db_low[2]~14_combout = ((\z80_|alu_|db_low[2]~10_combout & (\z80_|alu_|db_low[2]~11_combout & \z80_|alu_|db_low[2]~13_combout ))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_low[2]~10_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|alu_|db_low[2]~11_combout ), + .datad(\z80_|alu_|db_low[2]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~14 .lut_mask = 16'hB333; +defparam \z80_|alu_|db_low[2]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N24 +cycloneive_lcell_comb \z80_|alu_|db[2]~11 ( +// Equation(s): +// \z80_|alu_|db[2]~11_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[2]~48_combout & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[2]~30_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .datad(\z80_|alu_control_|db[2]~30_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~11 .lut_mask = 16'hF531; +defparam \z80_|alu_|db[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N22 +cycloneive_lcell_comb \z80_|alu_|db[2]~12 ( +// Equation(s): +// \z80_|alu_|db[2]~12_combout = ((\z80_|alu_|db[2]~11_combout & ((\z80_|alu_|db_low[2]~14_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db_low[2]~14_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[2]~11_combout ), + .datad(\z80_|alu_|db[7]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~12 .lut_mask = 16'hB0FF; +defparam \z80_|alu_|db[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( +// Equation(s): +// \z80_|alu_control_|db[2]~28_combout = (\z80_|alu_|db[2]~12_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~q & ((\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_|db[2]~12_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((!\z80_|alu_flags_|DFFE_inst_latch_pf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_|db[2]~12_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h7350; +defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N12 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( +// Equation(s): +// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~33_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & +// (((\z80_|alu_flags_|flags_hf2~q )))) + + .dataa(\z80_|alu_control_|db[4]~33_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datac(\z80_|alu_flags_|flags_hf2~q ), + .datad(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hEEF0; +defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N13 +dffeas \z80_|alu_flags_|flags_hf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|flags_hf2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_hf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N12 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( +// Equation(s): +// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [2]) # (\z80_|alu_|op1_low [1]))) + + .dataa(gnd), + .datab(\z80_|alu_|op1_low [3]), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hCCC0; +defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~combout = (\z80_|pla_decode_|Equal47~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~24 ( +// Equation(s): +// \z80_|alu_control_|db[2]~24_combout = (\z80_|alu_flags_|flags_hf2~q ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|execute_|ctl_66_oe~combout ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|alu_flags_|flags_hf2~q ), + .datab(\z80_|alu_control_|out[6]~0_combout ), + .datac(\z80_|execute_|ctl_66_oe~combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~24 .lut_mask = 16'hFEFF; +defparam \z80_|alu_control_|db[2]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datac(\z80_|execute_|rsel3~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # (\z80_|pla_decode_|Equal40~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout )) + + .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[2]~1_combout = (\z80_|reg_file_|gdfx_temp0[2]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[2]~1 .lut_mask = 16'hCCEC; +defparam \z80_|reg_file_|db_lo_ds[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N18 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( +// Equation(s): +// \z80_|alu_control_|db[2]~29_combout = (\z80_|reg_file_|db_lo_ds[2]~1_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[2]~13_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), + .datab(\z80_|reg_file_|db_lo_ds[2]~1_combout ), + .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datad(\z80_|bus_control_|db[2]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h4C44; +defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~30 ( +// Equation(s): +// \z80_|alu_control_|db[2]~30_combout = ((!\z80_|alu_control_|db[2]~28_combout & (\z80_|alu_control_|db[2]~24_combout & \z80_|alu_control_|db[2]~29_combout ))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_control_|db[2]~28_combout ), + .datab(\z80_|alu_control_|db[2]~24_combout ), + .datac(\z80_|alu_control_|db[6]~13_combout ), + .datad(\z80_|alu_control_|db[2]~29_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~30 .lut_mask = 16'h4F0F; +defparam \z80_|alu_control_|db[2]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [2] & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|alu_control_|db[2]~30_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .datad(\z80_|alu_control_|db[2]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N31 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~41_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~41_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y17_N29 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & (\z80_|reg_file_|gdfx_temp0[2]~37_combout & \z80_|reg_file_|gdfx_temp0[2]~36_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~35_combout & (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~39_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~41_combout = ((\z80_|reg_file_|gdfx_temp0[2]~40_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .datac(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp0[2]~41_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[2]~41_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hCC0C; +defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hDF55; +defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N26 +cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( +// Equation(s): +// \z80_|address_latch_|abusz [2] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[2]~9_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [2]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N27 +dffeas \z80_|address_latch_|Q[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [2]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N18 +cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( +// Equation(s): +// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [3]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N21 +dffeas \z80_|address_latch_|Q[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_latch_|abusz [3]), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [2] & +// !\z80_|address_latch_|Q [3])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [2] & \z80_|address_latch_|Q [3])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [2]), + .datad(\z80_|address_latch_|Q [3]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h2008; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [4] $ +// (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [4]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [5]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N15 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[5]~17_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .datad(\z80_|alu_control_|db[5]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|gdfx_temp0[5]~65_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hC4C4; +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N15 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N31 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y17_N25 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|gdfx_temp0[5]~67_combout & (\z80_|reg_file_|gdfx_temp0[5]~66_combout & (\z80_|reg_file_|gdfx_temp0[5]~68_combout & \z80_|reg_file_|gdfx_temp0[5]~64_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N9 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~62_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~62 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[5]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~63_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~62_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~62_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~71_combout = ((\z80_|reg_file_|gdfx_temp0[5]~70_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'h8AFF; +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .datad(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .datab(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .datab(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'h8CFF; +defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N30 +cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( +// Equation(s): +// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~18_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [5]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N31 +dffeas \z80_|address_latch_|Q[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [5]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout = \z80_|address_latch_|Q [5] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|address_latch_|Q [5]), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0F4B; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N31 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N21 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~72 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[6]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|execute_|ctl_reg_sel_wz~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & ((\z80_|alu_control_|db[6]~23_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|alu_control_|db[6]~23_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .datad(\z80_|alu_control_|db[6]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y17_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout & (\z80_|reg_file_|gdfx_temp0[6]~77_combout & (\z80_|reg_file_|gdfx_temp0[6]~75_combout & \z80_|reg_file_|gdfx_temp0[6]~76_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N27 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~80_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N21 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|gdfx_temp0[6]~73_combout & (\z80_|reg_file_|gdfx_temp0[6]~72_combout & (\z80_|reg_file_|gdfx_temp0[6]~78_combout & \z80_|reg_file_|gdfx_temp0[6]~74_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~72_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~80_combout = ((\z80_|reg_file_|gdfx_temp0[6]~79_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hCC44; +defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datab(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'h8CFF; +defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( +// Equation(s): +// \z80_|address_latch_|abusz [6] = (\z80_|reg_file_|db_lo_as[6]~21_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h00CC; +defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N15 +dffeas \z80_|address_latch_|Q[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [6]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~7_combout ) # (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|execute_|ctl_inc_dec~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h0312; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q [7]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [8]), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'hD278; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [0] & ((\z80_|reg_file_|gdfx_temp1[0]~30_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[0]~30_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hAA22; +defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hB3BB; +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N20 +cycloneive_lcell_comb \z80_|alu_|db[0]~17 ( +// Equation(s): +// \z80_|alu_|db[0]~17_combout = (\z80_|reg_file_|gdfx_temp1[0]~30_combout & (((\z80_|alu_|db_low[0]~27_combout )) # (!\z80_|execute_|ctl_alu_oe~14_combout ))) # (!\z80_|reg_file_|gdfx_temp1[0]~30_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_|db_low[0]~27_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db_low[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~17 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N30 +cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( +// Equation(s): +// \z80_|alu_|db[0]~18_combout = ((\z80_|alu_|db[0]~17_combout & ((\z80_|alu_control_|db[0]~14_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_control_|db[0]~14_combout ), + .datab(\z80_|alu_|db[0]~17_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|alu_|db[7]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~18 .lut_mask = 16'h8CFF; +defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N20 +cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( +// Equation(s): +// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~18_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|sw2_|db_up[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hAAFF; +defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~11 ( +// Equation(s): +// \z80_|alu_control_|db[0]~11_combout = (\z80_|alu_control_|db[0]~10_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|alu_control_|db[0]~10_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datad(\z80_|sw2_|db_up[0]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~11 .lut_mask = 16'h8A00; +defparam \z80_|alu_control_|db[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~14 ( +// Equation(s): +// \z80_|alu_control_|db[0]~14_combout = ((\z80_|alu_control_|db[0]~11_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_control_|db[0]~11_combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|db[6]~13_combout ), + .datad(\z80_|alu_flags_|flags_cf~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~14 .lut_mask = 16'hAF2F; +defparam \z80_|alu_control_|db[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[0]~14_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .datad(\z80_|alu_control_|db[0]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y17_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) # (!\z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N1 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout & (\z80_|reg_file_|gdfx_temp0[0]~10_combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .datad(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'hC400; +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~14_combout & (\z80_|reg_file_|gdfx_temp0[0]~15_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .datab(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'h8C00; +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~13_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & (\z80_|reg_file_|gdfx_temp0[0]~11_combout & \z80_|reg_file_|gdfx_temp0[0]~16_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hB0FF; +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[0]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hAA0A; +defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hDF55; +defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N16 +cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( +// Equation(s): +// \z80_|address_latch_|abusz [0] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[0]~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [0]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N17 +dffeas \z80_|address_latch_|Q[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [0]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ ((((\z80_|execute_|ctl_inc_dec~7_combout ) # (\z80_|execute_|ctl_inc_dec~9_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~6_combout ), + .datab(\z80_|address_latch_|Q [0]), + .datac(\z80_|execute_|ctl_inc_dec~7_combout ), + .datad(\z80_|execute_|ctl_inc_dec~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h3339; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout +// ))))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|execute_|ctl_inc_cy~81_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datad(\z80_|execute_|ctl_inc_cy~93_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h5A6A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N17 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N15 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hC4C4; +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|alu_control_|db[1]~27_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|alu_control_|db[1]~27_combout & +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) + + .dataa(\z80_|alu_control_|db[1]~27_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hBB0B; +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~28_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & \z80_|reg_file_|gdfx_temp0[1]~29_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N3 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N15 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N13 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~23_combout & (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .datab(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'h8AFF; +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[1]~32_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .datad(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hF755; +defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( +// Equation(s): +// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [1]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N0 +cycloneive_lcell_comb \z80_|address_latch_|Q[1]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[1]~feeder_combout = \z80_|address_latch_|abusz [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [1]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N1 +dffeas \z80_|address_latch_|Q[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[1]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|execute_|ctl_inc_dec~9_combout ), + .datac(\z80_|execute_|ctl_inc_dec~7_combout ), + .datad(\z80_|execute_|ctl_inc_dec~6_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h5655; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout & +// ((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datab(\z80_|execute_|ctl_inc_cy~81_combout ), + .datac(\z80_|execute_|ctl_inc_cy~93_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .lut_mask = 16'hA800; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q +// [2]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [2]), + .datad(\z80_|address_latch_|Q [3]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'hD728; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~51_combout = ((\z80_|reg_file_|gdfx_temp0[3]~50_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( +// Equation(s): +// \z80_|alu_control_|db[3]~35_combout = (\z80_|alu_control_|db[3]~34_combout & (\z80_|sw1_|db_down[3]~3_combout & ((\z80_|reg_file_|gdfx_temp0[3]~51_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|alu_control_|db[3]~34_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|sw1_|db_down[3]~3_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hA020; +defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~36 ( +// Equation(s): +// \z80_|alu_control_|db[3]~36_combout = ((\z80_|alu_control_|db[3]~35_combout & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_|db[3]~14_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_control_|db[6]~13_combout ), + .datad(\z80_|alu_control_|db[3]~35_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~36 .lut_mask = 16'hBF0F; +defparam \z80_|alu_control_|db[3]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N26 +cycloneive_lcell_comb \z80_|alu_|db[3]~14 ( +// Equation(s): +// \z80_|alu_|db[3]~14_combout = ((\z80_|alu_|db[3]~13_combout & ((\z80_|alu_control_|db[3]~36_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~9_combout ), + .datab(\z80_|alu_|db[3]~13_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|alu_control_|db[3]~36_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~14 .lut_mask = 16'hDD5D; +defparam \z80_|alu_|db[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N0 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~4 ( +// Equation(s): +// \z80_|alu_|db_low[3]~4_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[2]~12_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_|db[2]~12_combout ), + .datad(\z80_|alu_|db[4]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~4 .lut_mask = 16'hFC30; +defparam \z80_|alu_|db_low[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N10 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~5 ( +// Equation(s): +// \z80_|alu_|db_low[3]~5_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~4_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~14_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db[3]~14_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datad(\z80_|alu_|db_low[3]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~5 .lut_mask = 16'hFD5D; +defparam \z80_|alu_|db_low[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N25 +dffeas \z80_|alu_|result_lo[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~6 ( +// Equation(s): +// \z80_|alu_|db_low[3]~6_combout = (\z80_|alu_|op1_low [3] & (((\z80_|alu_|op2_low [3])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_low [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [3]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_low [3]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op2_low [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~6 .lut_mask = 16'hAF23; +defparam \z80_|alu_|db_low[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~7 ( +// Equation(s): +// \z80_|alu_|db_low[3]~7_combout = (\z80_|alu_|db_low[3]~6_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|alu_|db_low[3]~6_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~7 .lut_mask = 16'h2A0A; +defparam \z80_|alu_|db_low[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~8 ( +// Equation(s): +// \z80_|alu_|db_low[3]~8_combout = (\z80_|alu_|db_low[3]~5_combout & (\z80_|alu_|db_low[3]~7_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [3])))) + + .dataa(\z80_|alu_|db_low[3]~5_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|result_lo [3]), + .datad(\z80_|alu_|db_low[3]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~8 .lut_mask = 16'hA800; +defparam \z80_|alu_|db_low[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~26 ( +// Equation(s): +// \z80_|alu_|db_low[3]~26_combout = (\z80_|alu_|db_low[3]~8_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[3]~0_combout ), + .datad(\z80_|alu_|db_low[3]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~26 .lut_mask = 16'hFF03; +defparam \z80_|alu_|db_low[3]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) + + .dataa(\z80_|alu_|op1_high [3]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [3]), + .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .lut_mask = 16'hE200; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[3]~26_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|alu_|db_low[3]~26_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .lut_mask = 16'h0F08; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N13 +dffeas \z80_|alu_|op2_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_high[3]~7_combout ) # ((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # +// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|alu_|db_high[3]~7_combout ), + .datac(\z80_|alu_|db_low[3]~26_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N21 +dffeas \z80_|alu_|op2_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N14 +cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~0 ( +// Equation(s): +// \z80_|alu_|alu_op2[3]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [3]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [3])))) + + .dataa(\z80_|alu_|op2_low [3]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|alu_|op2_high [3]), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[3]~0 .lut_mask = 16'h1DE2; +defparam \z80_|alu_|alu_op2[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op2[3]~0_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & \z80_|alu_|alu_op1[3]~0_combout )) # (!\z80_|alu_|alu_op2[3]~0_combout & +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & !\z80_|alu_|alu_op1[3]~0_combout )) + + .dataa(\z80_|alu_|alu_op2[3]~0_combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_|alu_op1[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'h0A50; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout & (\z80_|alu_|alu_op2[3]~0_combout )) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout & +// (((!\z80_|execute_|ctl_alu_core_R~4_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[3]~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .lut_mask = 16'hAA3F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( +// Equation(s): +// \z80_|alu_|db_high[3]~4_combout = (\z80_|alu_|op1_high [3] & (((\z80_|alu_|op2_high [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [3]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [3]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_high [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( +// Equation(s): +// \z80_|alu_|db_high[3]~2_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_|db[6]~22_combout ), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFC30; +defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( +// Equation(s): +// \z80_|alu_|db_high[3]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[3]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[7]~20_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datab(\z80_|alu_|db[7]~20_combout ), + .datac(\z80_|alu_|db_high[3]~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hE4FF; +defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( +// Equation(s): +// \z80_|alu_|db_high[3]~5_combout = (\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[4]~19_combout )) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'h8800; +defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( +// Equation(s): +// \z80_|alu_|db_high[3]~6_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~3_combout & ((\z80_|alu_|db_high[3]~5_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|alu_|db_high[3]~4_combout ), + .datab(\z80_|alu_|db_high[3]~3_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|db_high[3]~5_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'h8808; +defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( +// Equation(s): +// \z80_|alu_|db_high[3]~7_combout = ((\z80_|alu_|db_high[3]~6_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|db_high[3]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'hFB33; +defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|execute_|ctl_flags_alu~19_combout & \z80_|alu_|db_high[3]~7_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datab(\z80_|execute_|ctl_flags_alu~19_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .datad(\z80_|alu_|db_high[3]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFDF5; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_shift_oe~38_combout & \z80_|execute_|ctl_alu_core_S~11_combout +// ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~11_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout & (((!\z80_|execute_|ctl_state_alu~12_combout ) # (!\z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'h7F00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (!\z80_|pla_decode_|Equal73~2_combout & (!\z80_|execute_|ctl_alu_sel_op2_neg~16_combout & !\z80_|execute_|ctl_alu_op_low~39_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .datab(\z80_|pla_decode_|Equal73~2_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h0002; +defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout & (\z80_|execute_|ctl_alu_core_hf~14_combout & (\z80_|execute_|ctl_flags_nf_we~0_combout & \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal61~2_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~3_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_nf_we~2_combout ) # (!\z80_|execute_|ctl_flags_xy_we~12_combout ))) # (!\z80_|execute_|ctl_flags_nf_we~1_combout ) + + .dataa(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~14 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~14_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (((!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~14 .lut_mask = 16'h0155; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~13 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout & \z80_|execute_|ctl_alu_core_hf~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~13 .lut_mask = 16'hF000; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~15 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~15_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (!\z80_|pla_decode_|Equal73~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .datab(\z80_|pla_decode_|Equal73~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~15 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~16 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~16_combout = (\z80_|execute_|ctl_flags_nf_we~3_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~3_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .datab(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~16 .lut_mask = 16'hB830; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N25 +dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~3_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_op_low~18_combout )))) # (!\z80_|execute_|ctl_state_alu~13_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datad(\z80_|execute_|ctl_state_alu~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'h32FF; +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal68~2_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .datad(\z80_|pla_decode_|Equal68~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hA2A0; +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~5_combout = (\z80_|execute_|ctl_flags_cf_cpl~4_combout ) # ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'hF0FE; +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_set~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_set~0_combout = (\z80_|execute_|ctl_state_alu~12_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal9~0_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~12_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_set~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_set~0 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_cf_set~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_state_alu~3_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout & +// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), + .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~2_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((\z80_|execute_|ctl_flags_cf_set~0_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~6_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .datac(\z80_|execute_|ctl_flags_cf_set~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N18 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( +// Equation(s): +// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [1]) # ((\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [0] & \z80_|alu_control_|out[6]~0_combout ))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|alu_|op1_high [0]), + .datac(\z80_|alu_|op1_high [2]), + .datad(\z80_|alu_control_|out[6]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEFA; +defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( +// Equation(s): +// \z80_|alu_control_|out[6]~2_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_|op1_high [3] & \z80_|alu_control_|out[6]~1_combout ))) + + .dataa(\z80_|alu_|op1_high [3]), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|execute_|ctl_66_oe~combout ), + .datad(\z80_|alu_control_|out[6]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFEFC; +defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~18_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_|db[7]~20_combout ), + .datad(\z80_|alu_|db[0]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hFC30; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N12 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|execute_|ctl_alu_core_R~combout +// & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hCC50; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_we~5_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~5_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_flags_cf2_we~5_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h7430; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N30 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_control_|out[6]~2_combout & !\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|alu_control_|out[6]~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'hF0F8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N31 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~10_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h4050; +defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal10~0_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|pla_decode_|Equal20~0_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h00EC; +defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~11_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout ))) + + .dataa(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hAAAC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N14 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = (\z80_|execute_|ctl_state_alu~12_combout & ((\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'h8044; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal63~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'hAEAA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~21_combout = (\z80_|pla_decode_|Equal10~1_combout & (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|pla_decode_|Equal10~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ) # ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~21_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'hFEFF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ) # ((\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFF8F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) # ((\z80_|execute_|ctl_alu_op_low~35_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'hFFEA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_state_alu~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~1_combout = (\z80_|pla_decode_|Equal64~0_combout & (\z80_|execute_|ctl_alu_op_low~35_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal64~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~1 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_flags_cf_cpl~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'hA8A0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout & ((\z80_|execute_|ctl_alu_op_low~30_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~40_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~40_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'hCCC8; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|pla_decode_|Equal61~2_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .lut_mask = 16'h0313; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout = (\z80_|execute_|ctl_alu_core_R~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & \z80_|execute_|ctl_flags_alu~10_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_R~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .lut_mask = 16'h8800; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|nM1_int~2_combout & +// (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal56~0_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .lut_mask = 16'h135F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~0 .lut_mask = 16'hFCEC; +defparam \z80_|execute_|ctl_flags_cf_cpl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_flags_cf_cpl~0_combout ) # (!\z80_|execute_|ctl_alu_op_low~34_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h040C; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = ((!\z80_|pla_decode_|Equal39~0_combout & ((!\z80_|pla_decode_|Equal40~2_combout ) # (!\z80_|ir_|opcode [5])))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal40~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h5777; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'h3330; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & \z80_|execute_|ctl_flags_nf_we~0_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .datad(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N2 +cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( +// Equation(s): +// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~1_combout ))))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_cf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h3600; +defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & (((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (\z80_|nM1_int~2_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (\z80_|pla_decode_|Equal10~0_combout & +// (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hECE0; +defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~18_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ) # ((\z80_|alu_control_|db[4]~33_combout & \z80_|execute_|ctl_flags_bus~combout )) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[4]~33_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'hFCF0; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N30 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_hf~q )))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (((\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )))) + + .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hFD20; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N31 +dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~9_combout = ((!\z80_|pla_decode_|Equal52~0_combout & ((\z80_|decode_state_|use_ixiy~combout ) # (!\z80_|pla_decode_|Equal44~0_combout )))) # (!\z80_|pla_decode_|Equal33~0_combout ) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~9 .lut_mask = 16'h45FF; +defparam \z80_|execute_|ctl_flags_hf_cpl~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (\z80_|execute_|ctl_alu_op_low~18_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_hf_cpl~10_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~8_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), + .datad(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'h2202; +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N12 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( +// Equation(s): +// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) + + .dataa(\z80_|alu_flags_|flags_cf~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h393C; +defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( +// Equation(s): +// \z80_|alu_control_|db[4]~31_combout = (\z80_|execute_|ctl_reg_out_lo~8_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[4]~10_combout )) # (!\z80_|reg_file_|gdfx_temp0[4]~61_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~8_combout & +// (\z80_|execute_|ctl_sw_2u~7_combout & ((!\z80_|alu_|db[4]~10_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .datad(\z80_|alu_|db[4]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h0ACE; +defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( +// Equation(s): +// \z80_|alu_control_|db[4]~32_combout = (!\z80_|alu_control_|db[4]~31_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_flags_|flags_hf~combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|db[4]~31_combout ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'h0B00; +defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~33 ( +// Equation(s): +// \z80_|alu_control_|db[4]~33_combout = ((\z80_|alu_control_|db[4]~32_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_control_|db[6]~13_combout ), + .datab(\z80_|execute_|ctl_sw_1d~7_combout ), + .datac(\z80_|bus_control_|db[4]~19_combout ), + .datad(\z80_|alu_control_|db[4]~32_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~33 .lut_mask = 16'hF755; +defparam \z80_|alu_control_|db[4]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N15 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N29 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~52_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~52 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[4]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|gdfx_temp0[4]~52_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|alu_control_|db[4]~33_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~52_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hDD00; +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N23 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y15_N3 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y17_N9 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N1 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y17_N11 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N19 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|gdfx_temp0[4]~58_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datad(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'h8808; +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~56_combout & (\z80_|reg_file_|gdfx_temp0[4]~53_combout & (\z80_|reg_file_|gdfx_temp0[4]~55_combout & \z80_|reg_file_|gdfx_temp0[4]~59_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~61_combout = ((\z80_|reg_file_|gdfx_temp0[4]~60_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .datab(gnd), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hAF00; +defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N22 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ) + + .dataa(\z80_|address_latch_|Q [4]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h55AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .datab(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N4 +cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( +// Equation(s): +// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~15_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [4]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N5 +dffeas \z80_|address_latch_|Q[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [4]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N6 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [4] & (!\z80_|address_latch_|Q [5] & (!\z80_|address_latch_|Q [6] & !\z80_|address_latch_|Q [7]))) + + .dataa(\z80_|address_latch_|Q [4]), + .datab(\z80_|address_latch_|Q [5]), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N30 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [8] & (!\z80_|address_latch_|Q [9] & !\z80_|address_latch_|Q [11]))) + + .dataa(\z80_|address_latch_|Q [10]), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|Q [11]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N20 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~3_combout = (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [3] & (!\z80_|address_latch_|Q [2] & !\z80_|address_latch_|Q [1]))) + + .dataa(\z80_|address_latch_|Q [0]), + .datab(\z80_|address_latch_|Q [3]), + .datac(\z80_|address_latch_|Q [2]), + .datad(\z80_|address_latch_|Q [1]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0002; +defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N16 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [13] & (!\z80_|address_latch_|Q [12] & (!\z80_|address_latch_|Q [15] & !\z80_|address_latch_|Q [14]))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|address_latch_|Q [12]), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|Q [14]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N26 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~2_combout & (\z80_|decode_state_|DFFE_instNonRep~1_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & \z80_|decode_state_|DFFE_instNonRep~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; +defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N12 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~9_combout & +// ((\z80_|decode_state_|DFFE_instNonRep~4_combout ))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|decode_state_|DFFE_instNonRep~q )))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hF4B0; +defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N13 +dffeas \z80_|decode_state_|DFFE_instNonRep ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instNonRep~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N30 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & (!\z80_|pla_decode_|Equal62~3_combout & (\z80_|execute_|ctl_pf_sel[0]~13_combout & \z80_|execute_|ctl_pf_sel[0]~10_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datab(\z80_|pla_decode_|Equal62~3_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h1000; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N18 +cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( +// Equation(s): +// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & (\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal79~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|pla_decode_|Equal79~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hD8F0; +defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N4 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|interrupts_|DFFE_inst44~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h5F0F; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G16 +cycloneive_clkctrl \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X30_Y12_N19 +dffeas \z80_|interrupts_|DFFE_instIFF2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|DFFE_instIFF2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'h80C4; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & +// (!\z80_|decode_state_|DFFE_instNonRep~q )))) + + .dataa(\z80_|decode_state_|DFFE_instNonRep~q ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'hC500; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|pla_decode_|Equal62~3_combout ) # (\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout ) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|pla_decode_|Equal62~3_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'hFFFD; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|execute_|ctl_pf_sel[0]~13_combout & (\z80_|execute_|ctl_pf_sel[0]~10_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'h4C00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[1]~12 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[1]~12_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[1]~12 .lut_mask = 16'h0031; +defparam \z80_|execute_|ctl_pf_sel[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~11 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~11_combout = (\z80_|nM1_int~2_combout & (((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|pla_decode_|Equal62~3_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|pla_decode_|Equal62~3_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~11 .lut_mask = 16'hFD00; +defparam \z80_|execute_|ctl_pf_sel[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (!\z80_|execute_|ctl_pf_sel[1]~12_combout & (((\z80_|execute_|ctl_pf_sel[0]~11_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~10_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .datab(\z80_|execute_|ctl_pf_sel[1]~12_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~11_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h3133; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ (((\z80_|execute_|ctl_alu_core_R~combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ))))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h6500; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N17 +dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|alu_parity_out~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N2 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( +// Equation(s): +// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'h6996; +defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( +// Equation(s): +// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .datad(\z80_|alu_|alu_parity_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out .lut_mask = 16'h03FC; +defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout & \z80_|alu_|alu_parity_out~combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .datad(\z80_|alu_|alu_parity_out~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'hFEFA; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~10_combout & (((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[2]~30_combout )))) # (!\z80_|execute_|ctl_flags_pf_we~10_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_pf~q )) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datab(\z80_|execute_|ctl_flags_bus~combout ), + .datac(\z80_|alu_control_|db[2]~30_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'hC0AA; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout & \z80_|execute_|ctl_flags_alu~19_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .datac(\z80_|execute_|ctl_flags_alu~19_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFF80; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y11_N25 +dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal13~0_combout ) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hF7FF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[2]~14_combout & (!\z80_|alu_|db_low[0]~27_combout & (!\z80_|alu_|db_low[3]~26_combout & !\z80_|alu_|db_low[1]~20_combout ))) + + .dataa(\z80_|alu_|db_low[2]~14_combout ), + .datab(\z80_|alu_|db_low[0]~27_combout ), + .datac(\z80_|alu_|db_low[3]~26_combout ), + .datad(\z80_|alu_|db_low[1]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_high[1]~19_combout & (!\z80_|alu_|db_high[0]~25_combout & (!\z80_|alu_|db_high[2]~13_combout & !\z80_|alu_|db_high[3]~7_combout ))) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|alu_|db_high[0]~25_combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|alu_|db_high[3]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout = (\z80_|execute_|ctl_flags_alu~19_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_alu~19_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hC000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ) # ((\z80_|alu_control_|db[6]~23_combout & \z80_|execute_|ctl_flags_bus~combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .datab(\z80_|alu_control_|db[6]~23_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hA8A0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N25 +dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ) # ((\z80_|alu_control_|sel[1]~0_combout )))) # (!\z80_|ir_|opcode [4] & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & +// !\z80_|alu_control_|sel[1]~0_combout )))) + + .dataa(\z80_|alu_flags_|flags_cf~combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|alu_control_|sel[1]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hF0AC; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) + + .dataa(\z80_|alu_control_|sel[1]~0_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hF588; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N8 +cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( +// Equation(s): +// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((\z80_|alu_control_|flags_cond_true~q )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|flags_cond_true~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hD872; +defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N9 +dffeas \z80_|alu_control_|flags_cond_true ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_control_|flags_cond_true~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|flags_cond_true~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; +defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|execute_|ctl_reg_sys_we_lo~1_combout ) # (\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hA8FF; +defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~combout = (((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (\z80_|reg_control_|reg_sys_we_hi~0_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF7; +defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~44_combout ) # ((\z80_|reg_control_|reg_sw_4d_hi~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datac(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~7 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~7_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [3] & ((\z80_|reg_file_|gdfx_temp1[3]~39_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[3]~39_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~7 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|db_hi_as[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~8 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~8_combout = (\z80_|reg_file_|db_hi_as[3]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[3]~7_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~8 .lut_mask = 16'hAA22; +defparam \z80_|reg_file_|db_hi_as[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~9 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~9_combout = ((\z80_|reg_file_|db_hi_as[3]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datac(\z80_|reg_file_|db_hi_as[3]~8_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~9 .lut_mask = 16'hD5F5; +defparam \z80_|reg_file_|db_hi_as[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N12 +cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( +// Equation(s): +// \z80_|address_latch_|abusz [11] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[3]~9_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N13 +dffeas \z80_|address_latch_|Q[11] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [11]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|Q [11] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [11]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N14 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [11]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h5505; +defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N6 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~2_combout = (\z80_|execute_|fIORead~3_combout ) # (((\z80_|execute_|fMRead~36_combout ) # (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )) + + .dataa(\z80_|execute_|fIORead~3_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datac(\z80_|execute_|fMRead~36_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFBFF; +defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N12 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|pin_control_|bus_ab_pin_we~2_combout & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) # (!\z80_|pin_control_|bus_ab_pin_we~2_combout & +// (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h22F2; +defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N15 +dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .asdata(\z80_|address_latch_|Q [11]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y4_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( +// Equation(s): +// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [11]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[11]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N4 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [10])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [10]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N5 +dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .asdata(\z80_|address_latch_|Q [10]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[10]~20 ( +// Equation(s): +// \z80_|address_pins_|abus[10]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [10]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[10]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[10]~20 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[10]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~19 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|extended~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~19 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|keys[7][1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~48 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~48_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~48_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~48 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[7][4]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~51 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~51_combout = (\ula_|zx_keyboard_|keys[3][2]~50_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[3][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][2]~50_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .datac(\ula_|zx_keyboard_|keys[3][2]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~51 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][2]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N7 dffeas \ula_|zx_keyboard_|keys[3][2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][2]~54_combout ), + .d(\ula_|zx_keyboard_|keys[3][2]~51_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49332,80 +39425,221 @@ defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N8 -cycloneive_lcell_comb \D[2]~36 ( +// Location: LCCOMB_X23_Y9_N26 +cycloneive_lcell_comb \D[2]~43 ( // Equation(s): -// \D[2]~36_combout = (\ula_|zx_keyboard_|keys[2][2]~q & (\z80_|address_pins_|abus[10]~24_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) # (!\ula_|zx_keyboard_|keys[2][2]~q & -// (((\z80_|address_pins_|abus[11]~19_combout )) # (!\ula_|zx_keyboard_|keys[3][2]~q ))) +// \D[2]~43_combout = (\ula_|zx_keyboard_|keys[2][2]~q & (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) # (!\ula_|zx_keyboard_|keys[2][2]~q & +// ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][2]~q )))) .dataa(\ula_|zx_keyboard_|keys[2][2]~q ), - .datab(\ula_|zx_keyboard_|keys[3][2]~q ), - .datac(\z80_|address_pins_|abus[10]~24_combout ), - .datad(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\z80_|address_pins_|abus[11]~19_combout ), + .datac(\z80_|address_pins_|abus[10]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[3][2]~q ), .cin(gnd), - .combout(\D[2]~36_combout ), + .combout(\D[2]~43_combout ), .cout()); // synopsys translate_off -defparam \D[2]~36 .lut_mask = 16'hF531; -defparam \D[2]~36 .sum_lutc_input = "datac"; +defparam \D[2]~43 .lut_mask = 16'hC4F5; +defparam \D[2]~43 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y19_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~68 ( +// Location: LCCOMB_X20_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~68_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [1]))) +// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|WideOr17~0_combout )) .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|WideOr17~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .combout(\ula_|zx_keyboard_|shifted~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~68 .lut_mask = 16'h0180; -defparam \ula_|zx_keyboard_|keys[6][2]~68 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y20_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~69 ( +// Location: LCCOMB_X19_Y10_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~11 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~69_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~68_combout )) +// \ula_|zx_keyboard_|keys[0][0]~11_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|Equal0~1_combout )) - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~11 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|keys[0][0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h000A; +defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~0_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # +// (!\ula_|zx_keyboard_|shifted~2_combout & (((\ula_|zx_keyboard_|shifted~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|shifted~2_combout ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|shifted~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y8_N31 +dffeas \ula_|zx_keyboard_|shifted ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|shifted~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|shifted~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|shifted .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~62 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~62_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~62_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~62 .lut_mask = 16'hF0FC; +defparam \ula_|zx_keyboard_|keys[5][0]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~32 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~32_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|zx_keyboard_|extended~q & \ula_|zx_keyboard_|keys[0][0]~11_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~32 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~63 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~63_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~63_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~63 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[6][2]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~64 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~64_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~63_combout ) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .datad(\ula_|zx_keyboard_|keys[6][2]~63_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .combout(\ula_|zx_keyboard_|keys[6][2]~64_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~69 .lut_mask = 16'h2200; -defparam \ula_|zx_keyboard_|keys[6][2]~69 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][2]~64 .lut_mask = 16'h5500; +defparam \ula_|zx_keyboard_|keys[6][2]~64 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~70 ( +// Location: LCCOMB_X21_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~65 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~70_combout = (\ula_|zx_keyboard_|keys[6][2]~69_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~69_combout & ((\ula_|zx_keyboard_|keys[6][2]~q ))) +// \ula_|zx_keyboard_|keys[6][2]~65_combout = (\ula_|zx_keyboard_|keys[6][1]~32_combout & ((\ula_|zx_keyboard_|keys[6][2]~64_combout & (!\ula_|zx_keyboard_|keys[5][0]~62_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~64_combout & +// ((\ula_|zx_keyboard_|keys[6][2]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~32_combout & (((\ula_|zx_keyboard_|keys[6][2]~q )))) - .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .datab(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .dataa(\ula_|zx_keyboard_|keys[5][0]~62_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~32_combout ), .datac(\ula_|zx_keyboard_|keys[6][2]~q ), - .datad(gnd), + .datad(\ula_|zx_keyboard_|keys[6][2]~64_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~70_combout ), + .combout(\ula_|zx_keyboard_|keys[6][2]~65_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~70 .lut_mask = 16'h7474; -defparam \ula_|zx_keyboard_|keys[6][2]~70 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][2]~65 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[6][2]~65 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y20_N1 +// Location: FF_X21_Y9_N5 dffeas \ula_|zx_keyboard_|keys[6][2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][2]~70_combout ), + .d(\ula_|zx_keyboard_|keys[6][2]~65_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49421,112 +39655,253 @@ defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( +// Location: LCCOMB_X31_Y16_N18 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~61_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) +// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) + + .dataa(\z80_|address_latch_|abusz [15]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N19 +dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .asdata(\z80_|address_latch_|Q [15]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[15]~21 ( +// Equation(s): +// \z80_|address_pins_|abus[15]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .combout(\z80_|address_pins_|abus[15]~21_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[15]~21 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[15]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~62 ( +// Location: LCCOMB_X31_Y16_N22 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~62_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[7][2]~61_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0]))) +// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [14])) + + .dataa(\z80_|address_latch_|abusz [14]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N23 +dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .asdata(\z80_|address_latch_|Q [14]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N14 +cycloneive_lcell_comb \z80_|address_pins_|abus[14]~22 ( +// Equation(s): +// \z80_|address_pins_|abus[14]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[14]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[14]~22 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[14]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~57 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~57_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~57_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~57 .lut_mask = 16'h3030; +defparam \ula_|zx_keyboard_|keys[7][2]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~58 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~58_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~57_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[7][2]~57_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~58_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~58 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[7][2]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~59 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~59_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~59 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|keys[5][4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~28 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~28_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5])) .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(gnd), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~62_combout ), + .combout(\ula_|zx_keyboard_|keys[7][2]~28_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~62 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[7][2]~62 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[7][2]~28 .lut_mask = 16'h0404; +defparam \ula_|zx_keyboard_|keys[7][2]~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~64 ( +// Location: LCCOMB_X21_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~60 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~64_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~62_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~63_combout & \ula_|zx_keyboard_|keys[7][2]~32_combout )))) +// \ula_|zx_keyboard_|keys[7][2]~60_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~58_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~59_combout & \ula_|zx_keyboard_|keys[7][2]~28_combout )))) - .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .dataa(\ula_|zx_keyboard_|keys[7][2]~58_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~59_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .combout(\ula_|zx_keyboard_|keys[7][2]~60_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~64 .lut_mask = 16'hC8C0; -defparam \ula_|zx_keyboard_|keys[7][2]~64 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[7][2]~60 .lut_mask = 16'hE0A0; +defparam \ula_|zx_keyboard_|keys[7][2]~60 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~65 ( +// Location: LCCOMB_X20_Y8_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~56 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~65_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~15_combout & \ula_|zx_keyboard_|keys[7][2]~64_combout ))) +// \ula_|zx_keyboard_|keys[7][2]~56_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[0][0]~11_combout & !\ula_|zx_keyboard_|extended~q )) .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~65_combout ), + .combout(\ula_|zx_keyboard_|keys[7][2]~56_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~65 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|keys[7][2]~65 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[7][2]~56 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|keys[7][2]~56 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N22 +// Location: LCCOMB_X23_Y8_N28 cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( // Equation(s): -// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [5])) +// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q )) - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|released~q ), + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), .cin(gnd), .combout(\ula_|zx_keyboard_|Selector13~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hFF22; +defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hF5F0; defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~66 ( +// Location: LCCOMB_X23_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~66_combout = (\ula_|zx_keyboard_|keys[7][2]~65_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~65_combout & (\ula_|zx_keyboard_|keys[7][2]~q )) +// \ula_|zx_keyboard_|keys[7][2]~61_combout = (\ula_|zx_keyboard_|keys[7][2]~60_combout & ((\ula_|zx_keyboard_|keys[7][2]~56_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~56_combout & +// (\ula_|zx_keyboard_|keys[7][2]~q )))) # (!\ula_|zx_keyboard_|keys[7][2]~60_combout & (((\ula_|zx_keyboard_|keys[7][2]~q )))) - .dataa(\ula_|zx_keyboard_|keys[7][2]~65_combout ), - .datab(gnd), + .dataa(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .datab(\ula_|zx_keyboard_|keys[7][2]~56_combout ), .datac(\ula_|zx_keyboard_|keys[7][2]~q ), .datad(\ula_|zx_keyboard_|Selector13~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~66_combout ), + .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~66 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[7][2]~66 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y21_N13 +// Location: FF_X23_Y8_N1 dffeas \ula_|zx_keyboard_|keys[7][2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][2]~66_combout ), + .d(\ula_|zx_keyboard_|keys[7][2]~61_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49542,173 +39917,1135 @@ defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N0 -cycloneive_lcell_comb \D[2]~38 ( +// Location: LCCOMB_X23_Y9_N10 +cycloneive_lcell_comb \D[2]~44 ( // Equation(s): -// \D[2]~38_combout = (\z80_|address_pins_|abus[15]~22_combout & (((\z80_|address_pins_|abus[14]~23_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~q ))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][2]~q & -// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) +// \D[2]~44_combout = (\ula_|zx_keyboard_|keys[6][2]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][2]~q )))) # (!\ula_|zx_keyboard_|keys[6][2]~q & +// ((\z80_|address_pins_|abus[15]~21_combout ) # ((!\ula_|zx_keyboard_|keys[7][2]~q )))) - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ula_|zx_keyboard_|keys[6][2]~q ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), + .dataa(\ula_|zx_keyboard_|keys[6][2]~q ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), .datad(\ula_|zx_keyboard_|keys[7][2]~q ), .cin(gnd), - .combout(\D[2]~38_combout ), + .combout(\D[2]~44_combout ), .cout()); // synopsys translate_off -defparam \D[2]~38 .lut_mask = 16'hA2F3; -defparam \D[2]~38 .sum_lutc_input = "datac"; +defparam \D[2]~44 .lut_mask = 16'hC4F5; +defparam \D[2]~44 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N14 -cycloneive_lcell_comb \D[2]~39 ( +// Location: LCCOMB_X31_Y16_N24 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( // Equation(s): -// \D[2]~39_combout = (\D[2]~35_combout & (\D[2]~37_combout & (\D[2]~36_combout & \D[2]~38_combout ))) +// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [12])) - .dataa(\D[2]~35_combout ), - .datab(\D[2]~37_combout ), - .datac(\D[2]~36_combout ), - .datad(\D[2]~38_combout ), + .dataa(\z80_|address_latch_|abusz [12]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), .cin(gnd), - .combout(\D[2]~39_combout ), + .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), .cout()); // synopsys translate_off -defparam \D[2]~39 .lut_mask = 16'h8000; -defparam \D[2]~39 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N14 -cycloneive_lcell_comb \D[2]~104 ( +// Location: FF_X31_Y16_N25 +dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .asdata(\z80_|address_latch_|Q [12]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[12]~24 ( // Equation(s): -// \D[2]~104_combout = ((\z80_|address_pins_|DFFE_apin_latch [0]) # (\D[2]~39_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|address_pins_|abus[12]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [12]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[12]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[12]~24 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[12]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N0 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [13]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datab(\z80_|address_latch_|abusz [13]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N1 +dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .asdata(\z80_|address_latch_|Q [13]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~29 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~29_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[7][2]~28_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~29_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~29 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[5][2]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~54 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~54_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~54_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~54 .lut_mask = 16'h0C0C; +defparam \ula_|zx_keyboard_|keys[5][2]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~55 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~55_combout = (\ula_|zx_keyboard_|keys[5][2]~29_combout & ((\ula_|zx_keyboard_|keys[5][2]~54_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][2]~54_combout & ((\ula_|zx_keyboard_|keys[5][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~29_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~29_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[5][2]~q ), + .datad(\ula_|zx_keyboard_|keys[5][2]~54_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~55_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~55 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][2]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y10_N31 +dffeas \ula_|zx_keyboard_|keys[5][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][2]~55_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~1_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # ((!\ula_|zx_keyboard_|keys[5][2]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|zx_keyboard_|keys[5][2]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hCFFF; +defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~127 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~127_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|Equal0~1_combout ))) + + .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~127_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~127 .lut_mask = 16'h0008; +defparam \ula_|zx_keyboard_|keys[3][4]~127 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~66 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~66_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~66_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~66 .lut_mask = 16'h0240; +defparam \ula_|zx_keyboard_|keys[4][2]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~128 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~128_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[4][2]~66_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|keys[4][2]~66_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~128_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~128 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[4][2]~128 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~67 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~67_combout = (\ula_|zx_keyboard_|keys[3][4]~127_combout & ((\ula_|zx_keyboard_|keys[4][2]~128_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][2]~128_combout & ((\ula_|zx_keyboard_|keys[4][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~127_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][4]~127_combout ), + .datac(\ula_|zx_keyboard_|keys[4][2]~q ), + .datad(\ula_|zx_keyboard_|keys[4][2]~128_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~67_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~67 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][2]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N23 +dffeas \ula_|zx_keyboard_|keys[4][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][2]~67_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N18 +cycloneive_lcell_comb \D[2]~45 ( +// Equation(s): +// \D[2]~45_combout = (\D[2]~44_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\D[2]~44_combout ), + .datab(\z80_|address_pins_|abus[12]~24_combout ), + .datac(\ula_|zx_keyboard_|key_row~1_combout ), + .datad(\ula_|zx_keyboard_|keys[4][2]~q ), + .cin(gnd), + .combout(\D[2]~45_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~45 .lut_mask = 16'h80A0; +defparam \D[2]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N26 +cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( +// Equation(s): +// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [0]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~43 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~43_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~43_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~43 .lut_mask = 16'h0808; +defparam \ula_|zx_keyboard_|keys[6][4]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~44 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~44_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[7][1]~19_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~44_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~44 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][4]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~45 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~45_combout = (\ula_|zx_keyboard_|keys[6][4]~43_combout & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~44_combout )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[6][4]~43_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[6][4]~44_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~45_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~45 .lut_mask = 16'h0C00; +defparam \ula_|zx_keyboard_|keys[1][2]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~46 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~46_combout = (\ula_|zx_keyboard_|keys[1][2]~45_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][2]~45_combout & ((\ula_|zx_keyboard_|keys[1][2]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[1][2]~q ), + .datad(\ula_|zx_keyboard_|keys[1][2]~45_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~46_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~46 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[1][2]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y9_N15 +dffeas \ula_|zx_keyboard_|keys[1][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][2]~46_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~47 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~47_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~47 .lut_mask = 16'h0055; +defparam \ula_|zx_keyboard_|keys[0][2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~49 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~49_combout = (\ula_|zx_keyboard_|keys[0][2]~47_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[0][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[0][2]~47_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[0][2]~47_combout ), + .datac(\ula_|zx_keyboard_|keys[0][2]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~49_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~49 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[0][2]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N13 +dffeas \ula_|zx_keyboard_|keys[0][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][2]~49_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N8 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [9])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [9]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N9 +dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .asdata(\z80_|address_latch_|Q [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N28 +cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( +// Equation(s): +// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [9]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[9]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N24 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [8]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [8]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N25 +dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .asdata(\z80_|address_latch_|Q [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N24 +cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( +// Equation(s): +// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [8]), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[8]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hCCFF; +defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N20 +cycloneive_lcell_comb \D[2]~42 ( +// Equation(s): +// \D[2]~42_combout = (\ula_|zx_keyboard_|keys[1][2]~q & (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][2]~q )))) # (!\ula_|zx_keyboard_|keys[1][2]~q & +// (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[1][2]~q ), + .datab(\ula_|zx_keyboard_|keys[0][2]~q ), + .datac(\z80_|address_pins_|abus[9]~17_combout ), + .datad(\z80_|address_pins_|abus[8]~18_combout ), + .cin(gnd), + .combout(\D[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~42 .lut_mask = 16'hF531; +defparam \D[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N24 +cycloneive_lcell_comb \D[2]~46 ( +// Equation(s): +// \D[2]~46_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[2]~43_combout & (\D[2]~45_combout & \D[2]~42_combout ))) + + .dataa(\D[2]~43_combout ), + .datab(\D[2]~45_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[2]~42_combout ), + .cin(gnd), + .combout(\D[2]~46_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~46 .lut_mask = 16'hF8F0; +defparam \D[2]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y14_N3 +dffeas \z80_|memory_ifc_|wait_iorqinta ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|clk_delay_|DFF_inst5~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorqinta~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N0 +cycloneive_lcell_comb \z80_|memory_ifc_|DFFE_intr_ff3~feeder ( +// Equation(s): +// \z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout = \z80_|memory_ifc_|wait_iorqinta~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|wait_iorqinta~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_intr_ff3~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|DFFE_intr_ff3~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y14_N1 +dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N8 +cycloneive_lcell_comb \z80_|control_pins_|pin_nIORQ~1 ( +// Equation(s): +// \z80_|control_pins_|pin_nIORQ~1_combout = ((!\z80_|memory_ifc_|iorq~0_combout & (!\z80_|memory_ifc_|DFFE_intr_ff3~q & !\z80_|memory_ifc_|wait_iorqinta~q ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|memory_ifc_|iorq~0_combout ), + .datab(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|wait_iorqinta~q ), + .cin(gnd), + .combout(\z80_|control_pins_|pin_nIORQ~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|control_pins_|pin_nIORQ~1 .lut_mask = 16'h0F1F; +defparam \z80_|control_pins_|pin_nIORQ~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N8 +cycloneive_lcell_comb \Equal2~0 ( +// Equation(s): +// \Equal2~0_combout = (\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|control_pins_|pin_nIORQ~1_combout ))) + + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), + .cin(gnd), + .combout(\Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~0 .lut_mask = 16'h0020; +defparam \Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N30 +cycloneive_lcell_comb \z80_|address_pins_|abus[13]~23 ( +// Equation(s): +// \z80_|address_pins_|abus[13]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[13]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[13]~23 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[13]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N18 +cycloneive_lcell_comb \ExtRamWE~0 ( +// Equation(s): +// \ExtRamWE~0_combout = (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|control_pins_|pin_nIORQ~1_combout ))) + + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), + .cin(gnd), + .combout(\ExtRamWE~0_combout ), + .cout()); +// synopsys translate_off +defparam \ExtRamWE~0 .lut_mask = 16'h4000; +defparam \ExtRamWE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N6 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h2000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y8_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|address_pins_|DFFE_apin_latch [14])) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h5000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N28 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [1]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .datab(\z80_|address_latch_|abusz [1]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N29 +dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .asdata(\z80_|address_latch_|Q [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N16 +cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( +// Equation(s): +// \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hF5F5; +defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N10 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) + + .dataa(\z80_|address_latch_|abusz [2]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hEE22; +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N11 +dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .asdata(\z80_|address_latch_|Q [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N20 +cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( +// Equation(s): +// \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [2]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[2]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N28 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [3]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [3]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y12_N29 +dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .asdata(\z80_|address_latch_|Q [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( +// Equation(s): +// \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [3]), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[3]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hCCFF; +defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N12 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [4]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .datab(\z80_|address_latch_|abusz [4]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N13 +dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .asdata(\z80_|address_latch_|Q [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N10 +cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( +// Equation(s): +// \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(\D[2]~39_combout ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [4]), .cin(gnd), - .combout(\D[2]~104_combout ), + .combout(\z80_|address_pins_|abus[4]~28_combout ), .cout()); // synopsys translate_off -defparam \D[2]~104 .lut_mask = 16'hFFF3; -defparam \D[2]~104 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF33; +defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: LCCOMB_X30_Y14_N8 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) + + .dataa(\z80_|address_latch_|abusz [5]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE22; +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N9 +dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .asdata(\z80_|address_latch_|Q [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), - .portbdataout()); + .q(\z80_|address_pins_|DFFE_apin_latch [5]), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y12_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: LCCOMB_X25_Y12_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( +// Equation(s): +// \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [5]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[5]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N18 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [6])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [6]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [6]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N19 +dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .asdata(\z80_|address_latch_|Q [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); + .q(\z80_|address_pins_|DFFE_apin_latch [6]), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y9_N0 +// Location: LCCOMB_X25_Y12_N10 +cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( +// Equation(s): +// \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [6]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[6]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N26 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) + + .dataa(\z80_|address_latch_|abusz [7]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y12_N27 +dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .asdata(\z80_|address_latch_|Q [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N12 +cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( +// Equation(s): +// \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [7]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[7]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hF5F5; +defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y5_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), @@ -49724,8 +41061,8 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -49765,7 +41102,79 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y12_N0 +// Location: FF_X24_Y19_N11 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[13]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y19_N3 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[14]~22_combout & (\ExtRamWE~0_combout & !\z80_|address_pins_|abus[13]~23_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ExtRamWE~0_combout ), + .datad(\z80_|address_pins_|abus[13]~23_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0020; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y8_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h0050; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y8_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), @@ -49781,8 +41190,8 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -49822,60 +41231,58 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N8 -cycloneive_lcell_comb \D[2]~43 ( +// Location: LCCOMB_X21_Y13_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( // Equation(s): -// \D[2]~43_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) +// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & (!\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\ExtRamWE~0_combout ), .cin(gnd), - .combout(\D[2]~43_combout ), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .cout()); // synopsys translate_off -defparam \D[2]~43 .lut_mask = 16'hB9A8; -defparam \D[2]~43 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h0800; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N6 -cycloneive_lcell_comb \D[2]~44 ( +// Location: LCCOMB_X25_Y8_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( // Equation(s): -// \D[2]~44_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~43_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout )) # (!\D[2]~43_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~43_combout )))) +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])) - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\D[2]~43_combout ), + .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), .cin(gnd), - .combout(\D[2]~44_combout ), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), .cout()); // synopsys translate_off -defparam \D[2]~44 .lut_mask = 16'hBBC0; -defparam \D[2]~44 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00A0; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y17_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(vcc), +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -49884,39 +41291,1006 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y28_N0 +// Location: FF_X25_Y19_N15 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y19_N19 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y8_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hAF0F; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y3_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N10 +cycloneive_lcell_comb \D[2]~50 ( +// Equation(s): +// \D[2]~50_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), + .cin(gnd), + .combout(\D[2]~50_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~50 .lut_mask = 16'hF838; +defparam \D[2]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N26 +cycloneive_lcell_comb \D[2]~51 ( +// Equation(s): +// \D[2]~51_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~50_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~50_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )) # (!\D[2]~50_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\D[2]~50_combout ), + .cin(gnd), + .combout(\D[2]~51_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~51 .lut_mask = 16'hEE30; +defparam \D[2]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N24 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (!\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h1000; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G15 +cycloneive_clkctrl \CLOCK_50~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\CLOCK_50~inputclkctrl_outclk )); +// synopsys translate_off +defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; +defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N30 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N8 +cycloneive_lcell_comb \ula_|video_|vram_address~0 ( +// Equation(s): +// \ula_|video_|vram_address~0_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|vram_address~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address~0 .lut_mask = 16'h1040; +defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N25 +dffeas \ula_|video_|vram_address[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N30 +cycloneive_lcell_comb \ula_|video_|vram_address[1]~feeder ( +// Equation(s): +// \ula_|video_|vram_address[1]~feeder_combout = \ula_|video_|vga_hc [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [5]), + .cin(gnd), + .combout(\ula_|video_|vram_address[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vram_address[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N31 +dffeas \ula_|video_|vram_address[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N4 +cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( +// Equation(s): +// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|video_|vram_address[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; +defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N5 +dffeas \ula_|video_|vram_address[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[2]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N22 +cycloneive_lcell_comb \ula_|video_|Add3~0 ( +// Equation(s): +// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N23 +dffeas \ula_|video_|vram_address[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N16 +cycloneive_lcell_comb \ula_|video_|Add3~1 ( +// Equation(s): +// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) + + .dataa(\ula_|video_|vga_hc [6]), + .datab(\ula_|video_|vga_hc [7]), + .datac(gnd), + .datad(\ula_|video_|vga_hc [8]), + .cin(gnd), + .combout(\ula_|video_|Add3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~1 .lut_mask = 16'h8877; +defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N17 +dffeas \ula_|video_|vram_address[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N8 +cycloneive_lcell_comb \ula_|video_|Add4~0 ( +// Equation(s): +// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) +// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add4~0_combout ), + .cout(\ula_|video_|Add4~1 )); +// synopsys translate_off +defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; +defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N10 +cycloneive_lcell_comb \ula_|video_|Add4~2 ( +// Equation(s): +// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) +// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) + + .dataa(\ula_|video_|vga_vc [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~1 ), + .combout(\ula_|video_|Add4~2_combout ), + .cout(\ula_|video_|Add4~3 )); +// synopsys translate_off +defparam \ula_|video_|Add4~2 .lut_mask = 16'hA505; +defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N12 +cycloneive_lcell_comb \ula_|video_|Add4~4 ( +// Equation(s): +// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) +// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) + + .dataa(\ula_|video_|vga_vc [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~3 ), + .combout(\ula_|video_|Add4~4_combout ), + .cout(\ula_|video_|Add4~5 )); +// synopsys translate_off +defparam \ula_|video_|Add4~4 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N14 +cycloneive_lcell_comb \ula_|video_|Add4~6 ( +// Equation(s): +// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) +// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [4]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~5 ), + .combout(\ula_|video_|Add4~6_combout ), + .cout(\ula_|video_|Add4~7 )); +// synopsys translate_off +defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y29_N15 +dffeas \ula_|video_|vram_address[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N16 +cycloneive_lcell_comb \ula_|video_|Add4~8 ( +// Equation(s): +// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) +// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) + + .dataa(\ula_|video_|vga_vc [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~7 ), + .combout(\ula_|video_|Add4~8_combout ), + .cout(\ula_|video_|Add4~9 )); +// synopsys translate_off +defparam \ula_|video_|Add4~8 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y29_N17 +dffeas \ula_|video_|vram_address[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N18 +cycloneive_lcell_comb \ula_|video_|Add4~10 ( +// Equation(s): +// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) +// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [6]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~9 ), + .combout(\ula_|video_|Add4~10_combout ), + .cout(\ula_|video_|Add4~11 )); +// synopsys translate_off +defparam \ula_|video_|Add4~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y29_N19 +dffeas \ula_|video_|vram_address[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N20 +cycloneive_lcell_comb \ula_|video_|Add4~12 ( +// Equation(s): +// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) +// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~11 ), + .combout(\ula_|video_|Add4~12_combout ), + .cout(\ula_|video_|Add4~13 )); +// synopsys translate_off +defparam \ula_|video_|Add4~12 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N28 +cycloneive_lcell_comb \ula_|video_|Selector6~0 ( +// Equation(s): +// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~12_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~0_combout )) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(gnd), + .datac(\ula_|video_|Add4~0_combout ), + .datad(\ula_|video_|Add4~12_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector6~0 .lut_mask = 16'hFA50; +defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N2 +cycloneive_lcell_comb \ula_|video_|vram_address[8]~1 ( +// Equation(s): +// \ula_|video_|vram_address[8]~1_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|vram_address[8]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[8]~1 .lut_mask = 16'h1040; +defparam \ula_|video_|vram_address[8]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y29_N29 +dffeas \ula_|video_|vram_address[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[8]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N22 +cycloneive_lcell_comb \ula_|video_|Add4~14 ( +// Equation(s): +// \ula_|video_|Add4~14_combout = \ula_|video_|vga_vc [8] $ (!\ula_|video_|Add4~13 ) + + .dataa(\ula_|video_|vga_vc [8]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|video_|Add4~13 ), + .combout(\ula_|video_|Add4~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add4~14 .lut_mask = 16'hA5A5; +defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N6 +cycloneive_lcell_comb \ula_|video_|Selector5~0 ( +// Equation(s): +// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(gnd), + .datac(\ula_|video_|Add4~14_combout ), + .datad(\ula_|video_|Add4~2_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector5~0 .lut_mask = 16'hF5A0; +defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y29_N7 +dffeas \ula_|video_|vram_address[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[8]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N28 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( +// Equation(s): +// \ula_|video_|vram_address[10]~2_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h1040; +defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N18 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( +// Equation(s): +// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) + + .dataa(\ula_|video_|vram_address[10]~2_combout ), + .datab(\ula_|video_|Add4~4_combout ), + .datac(\ula_|video_|vram_address [10]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'hD850; +defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N19 +dffeas \ula_|video_|vram_address[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[10]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N24 +cycloneive_lcell_comb \ula_|video_|Selector3~0 ( +// Equation(s): +// \ula_|video_|Selector3~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|Add4~12_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFF0; +defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y29_N25 +dffeas \ula_|video_|vram_address[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[8]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N2 +cycloneive_lcell_comb \ula_|video_|Selector2~0 ( +// Equation(s): +// \ula_|video_|Selector2~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~14_combout ) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(gnd), + .datac(\ula_|video_|Add4~14_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|video_|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFAFA; +defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y29_N3 +dffeas \ula_|video_|vram_address[12] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[8]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[12] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X22_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N28 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~23_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~23_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y19_N29 +dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N20 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|address_reg_a [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y19_N21 +dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N0 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\z80_|address_pins_|abus[14]~22_combout & (!\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~23_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h2000; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y23_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), @@ -49926,14 +42300,14 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -49989,97 +42363,83 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N12 -cycloneive_lcell_comb \D[2]~40 ( -// Equation(s): -// \D[2]~40_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .cin(gnd), - .combout(\D[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~40 .lut_mask = 16'hEA62; -defparam \D[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y31_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), +// Location: M9K_X33_Y20_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); // synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; // synopsys translate_on -// Location: M9K_X33_Y17_N0 +// Location: LCCOMB_X25_Y19_N22 +cycloneive_lcell_comb \D[2]~47 ( +// Equation(s): +// \D[2]~47_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\D[2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~47 .lut_mask = 16'hE6A2; +defparam \D[2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y32_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( .portawe(vcc), .portare(vcc), @@ -50089,14 +42449,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -50137,113 +42497,148 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N16 -cycloneive_lcell_comb \D[2]~41 ( +// Location: LCCOMB_X25_Y19_N24 +cycloneive_lcell_comb \D[2]~48 ( // Equation(s): -// \D[2]~41_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout $ (\D[2]~40_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout & ((!\D[2]~40_combout )))) +// \D[2]~48_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout $ ((\D[2]~47_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[2]~47_combout & +// \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\D[2]~40_combout ), + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\D[2]~47_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), .cin(gnd), - .combout(\D[2]~41_combout ), + .combout(\D[2]~48_combout ), .cout()); // synopsys translate_off -defparam \D[2]~41 .lut_mask = 16'h0AE4; -defparam \D[2]~41 .sum_lutc_input = "datac"; +defparam \D[2]~48 .lut_mask = 16'h4B48; +defparam \D[2]~48 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N30 -cycloneive_lcell_comb \D[2]~42 ( +// Location: LCCOMB_X25_Y19_N16 +cycloneive_lcell_comb \D[2]~49 ( // Equation(s): -// \D[2]~42_combout = (\D[2]~40_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout & !\D[2]~41_combout )))) # (!\D[2]~40_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~41_combout )))) +// \D[2]~49_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~47_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~47_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout & !\D[2]~48_combout )) # (!\D[2]~47_combout & ((\D[2]~48_combout ))))) - .dataa(\D[2]~40_combout ), + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datad(\D[2]~41_combout ), + .datac(\D[2]~47_combout ), + .datad(\D[2]~48_combout ), .cin(gnd), - .combout(\D[2]~42_combout ), + .combout(\D[2]~49_combout ), .cout()); // synopsys translate_off -defparam \D[2]~42 .lut_mask = 16'h99A8; -defparam \D[2]~42 .sum_lutc_input = "datac"; +defparam \D[2]~49 .lut_mask = 16'hC3E0; +defparam \D[2]~49 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N0 -cycloneive_lcell_comb \D[2]~105 ( +// Location: LCCOMB_X25_Y19_N6 +cycloneive_lcell_comb \D[2]~119 ( // Equation(s): -// \D[2]~105_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[2]~44_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[2]~42_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[2]~44_combout )))) +// \D[2]~119_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[2]~51_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[2]~49_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[2]~51_combout )))) - .dataa(\D[2]~44_combout ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[2]~42_combout ), + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\D[2]~51_combout ), + .datad(\D[2]~49_combout ), .cin(gnd), - .combout(\D[2]~105_combout ), + .combout(\D[2]~119_combout ), .cout()); // synopsys translate_off -defparam \D[2]~105 .lut_mask = 16'hBA8A; -defparam \D[2]~105 .sum_lutc_input = "datac"; +defparam \D[2]~119 .lut_mask = 16'hF4B0; +defparam \D[2]~119 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N28 -cycloneive_lcell_comb \D[2]~45 ( +// Location: LCCOMB_X24_Y19_N20 +cycloneive_lcell_comb \D[2]~52 ( // Equation(s): -// \D[2]~45_combout = ((\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout )))) # (!\Equal2~1_combout ) +// \D[2]~52_combout = ((\Equal2~0_combout & (\D[2]~46_combout )) # (!\Equal2~0_combout & ((\D[2]~119_combout )))) # (!\Equal2~1_combout ) - .dataa(\Equal2~0_combout ), + .dataa(\D[2]~46_combout ), .datab(\Equal2~1_combout ), - .datac(\D[2]~104_combout ), - .datad(\D[2]~105_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[2]~119_combout ), .cin(gnd), - .combout(\D[2]~45_combout ), + .combout(\D[2]~52_combout ), .cout()); // synopsys translate_off -defparam \D[2]~45 .lut_mask = 16'hF7B3; -defparam \D[2]~45 .sum_lutc_input = "datac"; +defparam \D[2]~52 .lut_mask = 16'hBFB3; +defparam \D[2]~52 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N30 -cycloneive_lcell_comb \D[2]~46 ( +// Location: LCCOMB_X24_Y19_N26 +cycloneive_lcell_comb \D[2]~53 ( // Equation(s): -// \D[2]~46_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [2] & ((\D[2]~45_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[2]~45_combout ) # (!\Equal2~1_combout )))) +// \D[2]~53_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [2] & \D[2]~52_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[2]~52_combout )) # (!\Equal2~1_combout ))) - .dataa(\z80_|data_pins_|dout [2]), + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[2]~45_combout ), + .datac(\z80_|data_pins_|dout [2]), + .datad(\D[2]~52_combout ), .cin(gnd), - .combout(\D[2]~46_combout ), + .combout(\D[2]~53_combout ), .cout()); // synopsys translate_off -defparam \D[2]~46 .lut_mask = 16'hAF03; -defparam \D[2]~46 .sum_lutc_input = "datac"; +defparam \D[2]~53 .lut_mask = 16'hF511; +defparam \D[2]~53 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N2 +// Location: LCCOMB_X29_Y12_N16 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[2]~13_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[2]~46_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[2]~46_combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|bus_control_|db[2]~13_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\D[2]~53_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|bus_control_|db[2]~13_combout & (\D[2]~53_combout +// & ((\z80_|pin_control_|bus_db_pin_re~combout )))) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\D[2]~46_combout ), - .datad(\z80_|bus_control_|db[2]~13_combout ), + .dataa(\z80_|bus_control_|db[2]~13_combout ), + .datab(\D[2]~53_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hECA0; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y12_N3 +// Location: LCCOMB_X32_Y12_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|execute_|fIORead~3_combout & ((\z80_|sequencer_|DFFE_T3_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|execute_|fIORead~3_combout & +// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|execute_|fIORead~3_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hA0EC; +defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N16 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .datac(\z80_|execute_|fMRead~36_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEC; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N17 dffeas \z80_|data_pins_|dout[2] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), @@ -50262,44 +42657,95 @@ defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N18 +// Location: LCCOMB_X29_Y12_N0 cycloneive_lcell_comb \z80_|bus_control_|db[2]~12 ( // Equation(s): -// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) +// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - .dataa(gnd), - .datab(\z80_|alu_control_|db[2]~29_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(\z80_|alu_control_|db[2]~30_combout ), + .datad(gnd), .cin(gnd), .combout(\z80_|bus_control_|db[2]~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hCF00; +defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hC4C4; defparam \z80_|bus_control_|db[2]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N12 +// Location: LCCOMB_X29_Y12_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( +// Equation(s): +// \z80_|bus_control_|db[0]~6_combout = ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (\z80_|execute_|ctl_bus_db_oe~combout )) # (!\z80_|execute_|ctl_bus_db_oe~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFFF5; +defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N10 cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( // Equation(s): // \z80_|bus_control_|db[2]~13_combout = ((\z80_|bus_control_|db[2]~12_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) .dataa(\z80_|data_pins_|dout [2]), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~combout ), - .datad(\z80_|bus_control_|db[2]~12_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|bus_control_|db[2]~12_combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[2]~13_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hBF33; +defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hB0FF; defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y12_N13 +// Location: LCCOMB_X29_Y13_N8 +cycloneive_lcell_comb \z80_|ir_|opcode[2]~feeder ( +// Equation(s): +// \z80_|ir_|opcode[2]~feeder_combout = \z80_|bus_control_|db[2]~13_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[2]~13_combout ), + .cin(gnd), + .combout(\z80_|ir_|opcode[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|ir_|opcode[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_ir_we~5_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hDDD5; +defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N9 dffeas \z80_|ir_|opcode[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[2]~13_combout ), + .d(\z80_|ir_|opcode[2]~feeder_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -50315,662 +42761,1129 @@ defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y16_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( +// Location: LCCOMB_X39_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( // Equation(s): -// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) +// \z80_|execute_|ctl_mRead~34_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .lut_mask = 16'h1500; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h2A22; +defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hFF5F; +defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~13 ( +// Equation(s): +// \z80_|alu_control_|db[6]~13_combout = (\z80_|execute_|ctl_reg_out_lo~8_combout ) # ((\z80_|alu_control_|db[6]~12_combout ) # (\z80_|execute_|ctl_sw_1d~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datab(\z80_|alu_control_|db[6]~12_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~13 .lut_mask = 16'hFEFE; +defparam \z80_|alu_control_|db[6]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( +// Equation(s): +// \z80_|alu_control_|db[6]~21_combout = (\z80_|alu_control_|out[6]~2_combout & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_control_|out[6]~2_combout & +// (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_control_|out[6]~2_combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'hF3A2; +defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( +// Equation(s): +// \z80_|alu_control_|db[6]~22_combout = (\z80_|alu_control_|db[6]~21_combout & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) + + .dataa(\z80_|alu_control_|db[6]~21_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_|db[6]~22_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'hA2A2; +defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[6]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[6]~0_combout = (\z80_|reg_file_|gdfx_temp0[6]~80_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[6]~0 .lut_mask = 16'hCCEC; +defparam \z80_|reg_file_|db_lo_ds[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N2 +cycloneive_lcell_comb \z80_|sw1_|db_down[6]~1 ( +// Equation(s): +// \z80_|sw1_|db_down[6]~1_combout = ((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) + + .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), + .datab(gnd), + .datac(\z80_|bus_control_|db[6]~9_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[6]~1 .lut_mask = 16'h55F5; +defparam \z80_|sw1_|db_down[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N20 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~23 ( +// Equation(s): +// \z80_|alu_control_|db[6]~23_combout = ((\z80_|alu_control_|db[6]~22_combout & (\z80_|reg_file_|db_lo_ds[6]~0_combout & \z80_|sw1_|db_down[6]~1_combout ))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_control_|db[6]~13_combout ), + .datab(\z80_|alu_control_|db[6]~22_combout ), + .datac(\z80_|reg_file_|db_lo_ds[6]~0_combout ), + .datad(\z80_|sw1_|db_down[6]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~23 .lut_mask = 16'hD555; +defparam \z80_|alu_control_|db[6]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N22 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( +// Equation(s): +// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~23_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(gnd), + .datad(\z80_|alu_control_|db[6]~23_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hCC44; +defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y17_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: M9K_X22_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N2 +cycloneive_lcell_comb \D[6]~103 ( +// Equation(s): +// \D[6]~103_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .cin(gnd), + .combout(\D[6]~103_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~103 .lut_mask = 16'hEA4A; +defparam \D[6]~103 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N30 +cycloneive_lcell_comb \D[6]~104 ( +// Equation(s): +// \D[6]~104_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~103_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~103_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )) # (!\D[6]~103_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\D[6]~103_combout ), + .cin(gnd), + .combout(\D[6]~104_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~104 .lut_mask = 16'hEE30; +defparam \D[6]~104 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X22_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y30_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N14 +cycloneive_lcell_comb \D[6]~100 ( +// Equation(s): +// \D[6]~100_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\z80_|address_pins_|abus[14]~22_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\z80_|address_pins_|abus[14]~22_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .cin(gnd), + .combout(\D[6]~100_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~100 .lut_mask = 16'hBCB0; +defparam \D[6]~100 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y22_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N12 +cycloneive_lcell_comb \D[6]~101 ( +// Equation(s): +// \D[6]~101_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ ((\D[6]~100_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[6]~100_combout & +// \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datac(\D[6]~100_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .cin(gnd), + .combout(\D[6]~101_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~101 .lut_mask = 16'h2D28; +defparam \D[6]~101 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N0 +cycloneive_lcell_comb \D[6]~102 ( +// Equation(s): +// \D[6]~102_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~100_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~100_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~101_combout )) # (!\D[6]~100_combout & ((\D[6]~101_combout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[6]~100_combout ), + .datad(\D[6]~101_combout ), + .cin(gnd), + .combout(\D[6]~102_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~102 .lut_mask = 16'hC3E0; +defparam \D[6]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N8 +cycloneive_lcell_comb \D[6]~127 ( +// Equation(s): +// \D[6]~127_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[6]~104_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[6]~102_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[6]~104_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\D[6]~104_combout ), + .datad(\D[6]~102_combout ), + .cin(gnd), + .combout(\D[6]~127_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~127 .lut_mask = 16'hF4B0; +defparam \D[6]~127 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y34_N8 +cycloneive_io_ibuf \raw_loader_in~input ( + .i(raw_loader_in), + .ibar(gnd), + .o(\raw_loader_in~input_o )); +// synopsys translate_off +defparam \raw_loader_in~input .bus_hold = "false"; +defparam \raw_loader_in~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N28 +cycloneive_lcell_comb \D[6]~99 ( +// Equation(s): +// \D[6]~99_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\raw_loader_in~input_o ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~1_combout ), + .combout(\D[6]~99_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00F0; -defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; +defparam \D[6]~99 .lut_mask = 16'hFFCF; +defparam \D[6]~99 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( +// Location: LCCOMB_X23_Y19_N10 +cycloneive_lcell_comb \D[6]~114 ( // Equation(s): -// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) +// \D[6]~114_combout = ((\Equal2~0_combout & ((\D[6]~99_combout ))) # (!\Equal2~0_combout & (\D[6]~127_combout ))) # (!\Equal2~1_combout ) - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), + .dataa(\Equal2~0_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[6]~127_combout ), + .datad(\D[6]~99_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal43~0_combout ), + .combout(\D[6]~114_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; +defparam \D[6]~114 .lut_mask = 16'hFB73; +defparam \D[6]~114 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N24 -cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( +// Location: LCCOMB_X23_Y19_N12 +cycloneive_lcell_comb \D[6]~115 ( // Equation(s): -// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal43~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal36~0_combout ))) +// \D[6]~115_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [6] & \D[6]~114_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[6]~114_combout )) # (!\Equal2~1_combout ))) - .dataa(\z80_|pla_decode_|Equal43~0_combout ), - .datab(\z80_|pla_decode_|Equal3~2_combout ), - .datac(\z80_|pla_decode_|Equal79~0_combout ), - .datad(\z80_|pla_decode_|Equal36~0_combout ), + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\Equal2~1_combout ), + .datac(\z80_|data_pins_|dout [6]), + .datad(\D[6]~114_combout ), .cin(gnd), - .combout(\z80_|interrupts_|test1~2_combout ), + .combout(\D[6]~115_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; -defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; +defparam \D[6]~115 .lut_mask = 16'hF511; +defparam \D[6]~115 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y15_N26 -cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( +// Location: LCCOMB_X28_Y12_N14 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( // Equation(s): -// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|interrupts_|test1~2_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\D[6]~115_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[6]~9_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[6]~115_combout & +// (((\z80_|bus_control_|db[6]~9_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|interrupts_|test1~2_combout ), + .dataa(\D[6]~115_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|bus_control_|db[6]~9_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), .cin(gnd), - .combout(\z80_|interrupts_|test1~3_combout ), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h5545; -defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y15_N13 -dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), +// Location: FF_X28_Y12_N15 +dffeas \z80_|data_pins_|dout[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N14 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( +// Equation(s): +// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[6]~8_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|data_pins_|dout [6]), + .datad(\z80_|bus_control_|db[0]~6_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'hA2FF; +defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N3 +dffeas \z80_|ir_|opcode[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[6]~9_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~0_combout = (\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6])) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h0A00; +defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal38~2_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal38~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N0 +cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Equation(s): +// \z80_|interrupts_|iff1~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|interrupts_|iff1~q ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal79~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hE4CC; +defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N4 +cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( +// Equation(s): +// \z80_|interrupts_|iff1~1_combout = (\z80_|pla_decode_|Equal38~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|interrupts_|iff1~0_combout )))) # +// (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|iff1~0_combout )) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|interrupts_|iff1~0_combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hE4CC; +defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N24 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|interrupts_|DFFE_inst44~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFF3; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N5 +dffeas \z80_|interrupts_|iff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|iff1~1_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|iff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|iff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y27_N8 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (\ula_|video_|Equal2~2_combout & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & (!\ula_|video_|vga_hc [7] & \z80_|interrupts_|iff1~q ))) + + .dataa(\ula_|video_|Equal2~2_combout ), + .datab(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), + .datac(\ula_|video_|vga_hc [7]), + .datad(\z80_|interrupts_|iff1~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0800; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y27_N9 +dffeas \z80_|interrupts_|int_armed ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|int_armed~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; +defparam \z80_|interrupts_|int_armed .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N25 +dffeas \z80_|interrupts_|DFFE_inst44 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|interrupts_|int_armed~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), .ena(\z80_|interrupts_|test1~3_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .q(\z80_|interrupts_|DFFE_inst44~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; +defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y15_N2 -cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( +// Location: LCCOMB_X30_Y11_N22 +cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( // Equation(s): -// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|interrupts_|DFFE_inst44~q ))) +// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & \z80_|decode_state_|in_halt~q )) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0100; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y15_N3 -dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N20 -cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( -// Equation(s): -// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q & !\z80_|clk_delay_|DFF_inst5~q ) - - .dataa(gnd), - .datab(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), .datac(gnd), - .datad(\z80_|clk_delay_|DFF_inst5~q ), + .datad(\z80_|decode_state_|in_halt~q ), .cin(gnd), - .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), + .combout(\z80_|decode_state_|in_halt~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0033; -defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h1100; +defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N13 -dffeas \z80_|sequencer_|DFFE_T1_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|ena_M~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T1_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N4 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0050; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N5 -dffeas \z80_|sequencer_|DFFE_T2_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T2_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N10 -cycloneive_lcell_comb \z80_|resets_|x3 ( -// Equation(s): -// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(\z80_|resets_|x1~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|resets_|x3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|x3 .lut_mask = 16'hF0FA; -defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N11 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|x3~combout ), - .asdata(vcc), - .clrn(\z80_|fpga_reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; -// synopsys translate_on - -// Location: CLKCTRL_G7 -cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: FF_X32_Y17_N21 -dffeas \z80_|sequencer_|DFFE_M1_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M1_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N10 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h22A0; -defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N11 -dffeas \z80_|sequencer_|DFFE_M2_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M2_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~3 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~3_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~3 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~11 ( -// Equation(s): -// \z80_|execute_|nextM~11_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ctl_mWrite~3_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~11 .lut_mask = 16'h5557; -defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~8 ( -// Equation(s): -// \z80_|execute_|nextM~8_combout = (\z80_|alu_control_|flags_cond_true~q & (((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) # (!\z80_|alu_control_|flags_cond_true~q & ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout -// ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~8 .lut_mask = 16'h44F4; -defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~9 ( -// Equation(s): -// \z80_|execute_|nextM~9_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # (\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~9 .lut_mask = 16'h8880; -defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|nextM~10 ( -// Equation(s): -// \z80_|execute_|nextM~10_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datab(\z80_|execute_|nextM~9_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~12 ( -// Equation(s): -// \z80_|execute_|nextM~12_combout = ((\z80_|execute_|nextM~8_combout ) # ((\z80_|execute_|nextM~10_combout ) # (\z80_|execute_|ctl_alu_op_low~32_combout ))) # (!\z80_|execute_|nextM~11_combout ) - - .dataa(\z80_|execute_|nextM~11_combout ), - .datab(\z80_|execute_|nextM~8_combout ), - .datac(\z80_|execute_|nextM~10_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|nextM~15 ( -// Equation(s): -// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|fMRead~10_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|fMRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~15 .lut_mask = 16'h80A0; -defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|nextM~6 ( -// Equation(s): -// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|ixy_d~17_combout ) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|nextM~3_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~6 .lut_mask = 16'hDF5F; -defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~7 ( -// Equation(s): -// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ixy_d~8_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|execute_|nextM~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|nextM~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~7 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~13 ( -// Equation(s): -// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~12_combout ) # ((\z80_|execute_|nextM~15_combout ) # (\z80_|execute_|nextM~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|nextM~12_combout ), - .datac(\z80_|execute_|nextM~15_combout ), - .datad(\z80_|execute_|nextM~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~39 ( -// Equation(s): -// \z80_|execute_|setM1~39_combout = (!\z80_|execute_|ctl_mWrite~5_combout & \z80_|execute_|setM1~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|setM1~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0F00; -defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~5 ( -// Equation(s): -// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~45_combout ) # (!\z80_|execute_|nextM~2_combout )) # (!\z80_|execute_|setM1~39_combout ))) - - .dataa(\z80_|execute_|setM1~39_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|setM1~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~5 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|nextM~14 ( -// Equation(s): -// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~13_combout ) # (((\z80_|execute_|nextM~5_combout ) # (!\z80_|execute_|ctl_mRead~30_combout )) # (!\z80_|execute_|ctl_mWrite~13_combout )) - - .dataa(\z80_|execute_|nextM~13_combout ), - .datab(\z80_|execute_|ctl_mWrite~13_combout ), - .datac(\z80_|execute_|ctl_mRead~30_combout ), - .datad(\z80_|execute_|nextM~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~14 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N14 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00C0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N15 -dffeas \z80_|sequencer_|DFFE_T4_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T4_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N18 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N19 -dffeas \z80_|sequencer_|DFFE_T5_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T5_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N26 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00C0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N27 -dffeas \z80_|sequencer_|T6 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|T6~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|T6 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~13 ( -// Equation(s): -// \z80_|execute_|setM1~13_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|pla_decode_|Equal33~0_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal21~2_combout )))) # (!\z80_|pla_decode_|Equal13~0_combout & -// (((!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal21~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal21~2_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~13 .lut_mask = 16'h153F; -defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N4 +// Location: LCCOMB_X34_Y11_N16 cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( // Equation(s): -// \z80_|pla_decode_|Equal77~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) +// \z80_|pla_decode_|Equal77~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal21~0_combout ))) .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), .cin(gnd), .combout(\z80_|pla_decode_|Equal77~1_combout ), .cout()); @@ -50979,660 +43892,24 @@ defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~12 ( -// Equation(s): -// \z80_|execute_|setM1~12_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|pla_decode_|Equal2~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal77~1_combout ), - .datab(\z80_|execute_|ctl_alu_oe~3_combout ), - .datac(\z80_|pla_decode_|Equal1~6_combout ), - .datad(\z80_|pla_decode_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~14 ( -// Equation(s): -// \z80_|execute_|setM1~14_combout = (\z80_|execute_|setM1~13_combout & (\z80_|interrupts_|test1~2_combout & \z80_|execute_|setM1~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|setM1~13_combout ), - .datac(\z80_|interrupts_|test1~2_combout ), - .datad(\z80_|execute_|setM1~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~14 .lut_mask = 16'hC000; -defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~41 ( -// Equation(s): -// \z80_|execute_|setM1~41_combout = (!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_ir_we~10_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~41 .lut_mask = 16'h0005; -defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~42 ( -// Equation(s): -// \z80_|execute_|setM1~42_combout = (!\z80_|pla_decode_|Equal38~2_combout & (!\z80_|pla_decode_|Equal37~0_combout & (!\z80_|pla_decode_|Equal47~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0100; -defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~43 ( -// Equation(s): -// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~41_combout & (!\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|setM1~42_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|setM1~41_combout ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|execute_|setM1~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0400; -defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~44 ( -// Equation(s): -// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (\z80_|execute_|setM1~40_combout & ((!\z80_|pla_decode_|Equal2~1_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|execute_|setM1~43_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|pla_decode_|Equal2~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~44 .lut_mask = 16'h20A0; -defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~50 ( -// Equation(s): -// \z80_|execute_|setM1~50_combout = (\z80_|execute_|setM1~46_combout & (\z80_|execute_|setM1~14_combout & (\z80_|execute_|setM1~44_combout & \z80_|execute_|setM1~49_combout ))) - - .dataa(\z80_|execute_|setM1~46_combout ), - .datab(\z80_|execute_|setM1~14_combout ), - .datac(\z80_|execute_|setM1~44_combout ), - .datad(\z80_|execute_|setM1~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~50 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~51 ( -// Equation(s): -// \z80_|execute_|setM1~51_combout = (\z80_|sequencer_|T6~q & (((\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~39_combout )) # (!\z80_|execute_|setM1~40_combout ))) # (!\z80_|sequencer_|T6~q & (\z80_|execute_|setM1~50_combout & -// ((\z80_|execute_|setM1~39_combout )))) - - .dataa(\z80_|sequencer_|T6~q ), - .datab(\z80_|execute_|setM1~50_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|execute_|setM1~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~51 .lut_mask = 16'hCE0A; -defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~6 ( -// Equation(s): -// \z80_|execute_|setM1~6_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|sequencer_|M5~q & (\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & -// \z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~6 .lut_mask = 16'hD5C0; -defparam \z80_|execute_|setM1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~7 ( -// Equation(s): -// \z80_|execute_|setM1~7_combout = ((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|setM1~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~7 .lut_mask = 16'hF333; -defparam \z80_|execute_|setM1~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~8 ( -// Equation(s): -// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|fMWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~8 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~9 ( -// Equation(s): -// \z80_|execute_|setM1~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~9 .lut_mask = 16'hF1F0; -defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~10 ( -// Equation(s): -// \z80_|execute_|setM1~10_combout = ((\z80_|execute_|setM1~8_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout & \z80_|execute_|setM1~9_combout ))) # (!\z80_|execute_|nextM~2_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|setM1~8_combout ), - .datad(\z80_|execute_|setM1~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~11 ( -// Equation(s): -// \z80_|execute_|setM1~11_combout = (\z80_|execute_|setM1~7_combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|setM1~10_combout )) # (!\z80_|reg_control_|reg_sel_pc~3_combout )) - - .dataa(\z80_|execute_|setM1~7_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|setM1~10_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~11 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~17 ( -// Equation(s): -// \z80_|execute_|setM1~17_combout = ((\z80_|execute_|setM1~11_combout ) # ((!\z80_|execute_|setM1~14_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|setM1~16_combout ) - - .dataa(\z80_|execute_|setM1~16_combout ), - .datab(\z80_|execute_|setM1~14_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~17 .lut_mask = 16'hFF75; -defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~31 ( -// Equation(s): -// \z80_|execute_|setM1~31_combout = (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout & \z80_|execute_|ctl_mRead~18_combout )))) # (!\z80_|pla_decode_|Equal35~0_combout & -// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|execute_|ctl_mRead~18_combout )))) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~31 .lut_mask = 16'hECA0; -defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~28 ( -// Equation(s): -// \z80_|execute_|setM1~28_combout = ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~30 ( -// Equation(s): -// \z80_|execute_|setM1~30_combout = (((\z80_|execute_|ctl_state_alu~6_combout & \z80_|execute_|setM1~28_combout )) # (!\z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~54_combout ) - - .dataa(\z80_|execute_|setM1~54_combout ), - .datab(\z80_|execute_|setM1~29_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|setM1~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~30 .lut_mask = 16'hF777; -defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~32 ( -// Equation(s): -// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|setM1~9_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|setM1~9_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~32 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~33 ( -// Equation(s): -// \z80_|execute_|setM1~33_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~30_combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|setM1~32_combout ))) - - .dataa(\z80_|execute_|setM1~31_combout ), - .datab(\z80_|execute_|setM1~30_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|setM1~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~25 ( -// Equation(s): -// \z80_|execute_|setM1~25_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~25 .lut_mask = 16'hAF0F; -defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~26 ( -// Equation(s): -// \z80_|execute_|setM1~26_combout = ((\z80_|execute_|ctl_mRead~13_combout ) # ((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~26 .lut_mask = 16'hF7F5; -defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~24 ( -// Equation(s): -// \z80_|execute_|setM1~24_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_mRead~12_combout ))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & ((!\z80_|alu_control_|flags_cond_true~q )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|alu_control_|flags_cond_true~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~24 .lut_mask = 16'h0ACE; -defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~27 ( -// Equation(s): -// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|setM1~25_combout ) # (\z80_|execute_|setM1~26_combout )))) - - .dataa(\z80_|execute_|setM1~25_combout ), - .datab(\z80_|execute_|setM1~26_combout ), - .datac(\z80_|execute_|setM1~24_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~27 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~22 ( -// Equation(s): -// \z80_|execute_|setM1~22_combout = (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|execute_|fMWrite~9_combout & (!\z80_|execute_|ctl_mRead~8_combout & \z80_|execute_|fMWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|fMWrite~9_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~22 .lut_mask = 16'h0400; -defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~21 ( -// Equation(s): -// \z80_|execute_|setM1~21_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|decode_state_|DFFE_instNonRep~q ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~21 .lut_mask = 16'hF1F0; -defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~53 ( -// Equation(s): -// \z80_|execute_|setM1~53_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|execute_|setM1~21_combout & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~21_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~53 .lut_mask = 16'hC888; -defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~23 ( -// Equation(s): -// \z80_|execute_|setM1~23_combout = (\z80_|execute_|setM1~22_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) # (!\z80_|execute_|setM1~22_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # -// ((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) - - .dataa(\z80_|execute_|setM1~22_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|setM1~53_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~23 .lut_mask = 16'h4F44; -defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~18 ( -// Equation(s): -// \z80_|execute_|setM1~18_combout = (\z80_|execute_|ctl_mRead~11_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~18 .lut_mask = 16'h08CC; -defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~19 ( -// Equation(s): -// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~18_combout ) # ((\z80_|execute_|ixy_d~8_combout & (\z80_|pla_decode_|Equal10~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ))) - - .dataa(\z80_|execute_|setM1~18_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~19 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~20 ( -// Equation(s): -// \z80_|execute_|setM1~20_combout = ((\z80_|execute_|setM1~19_combout ) # ((\z80_|execute_|ctl_iorw~11_combout & \z80_|execute_|ctl_mWrite~3_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datad(\z80_|execute_|setM1~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~20 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~34 ( -// Equation(s): -// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~33_combout ) # ((\z80_|execute_|setM1~27_combout ) # ((\z80_|execute_|setM1~23_combout ) # (\z80_|execute_|setM1~20_combout ))) - - .dataa(\z80_|execute_|setM1~33_combout ), - .datab(\z80_|execute_|setM1~27_combout ), - .datac(\z80_|execute_|setM1~23_combout ), - .datad(\z80_|execute_|setM1~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~52 ( -// Equation(s): -// \z80_|execute_|setM1~52_combout = (!\z80_|execute_|setM1~17_combout & (!\z80_|execute_|setM1~34_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~51_combout )))) - - .dataa(\z80_|execute_|setM1~51_combout ), - .datab(\z80_|execute_|setM1~17_combout ), - .datac(\z80_|execute_|setM1~34_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~52 .lut_mask = 16'h0301; -defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N24 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N25 -dffeas \z80_|sequencer_|DFFE_T3_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T3_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N24 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( -// Equation(s): -// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|decode_state_|in_halt~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h0050; -defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N24 +// Location: LCCOMB_X30_Y11_N12 cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( // Equation(s): -// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|decode_state_|in_halt~q & \z80_|pla_decode_|Equal77~1_combout ))) +// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|pla_decode_|Equal77~1_combout & (!\z80_|decode_state_|in_halt~q & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|decode_state_|in_halt~0_combout ), + .dataa(\z80_|decode_state_|in_halt~0_combout ), + .datab(\z80_|pla_decode_|Equal77~1_combout ), .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|pla_decode_|Equal77~1_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), .cin(gnd), .combout(\z80_|decode_state_|in_halt~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hCECC; +defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hAEAA; defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y13_N25 +// Location: FF_X30_Y11_N13 dffeas \z80_|decode_state_|in_halt ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|decode_state_|in_halt~1_combout ), @@ -51651,434 +43928,489 @@ defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; defparam \z80_|decode_state_|in_halt .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Location: LCCOMB_X34_Y6_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_zero_oe~0_combout & (!\z80_|execute_|ctl_bus_ff_oe~1_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) +// \z80_|execute_|ctl_mRead~21_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal77~0_combout ))) .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .combout(\z80_|execute_|ctl_mRead~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0031; -defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( +// Location: LCCOMB_X34_Y6_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|pla_decode_|Equal41~2_combout ))) +// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|ctl_mRead~21_combout ) # (((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|fMWrite~0_combout )) # (!\z80_|execute_|fMRead~7_combout )) + + .dataa(\z80_|execute_|ctl_mRead~21_combout ), + .datab(\z80_|execute_|fMRead~7_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|fMWrite~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( +// Equation(s): +// \z80_|execute_|fMRead~23_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|fMRead~4_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|fMRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hA2AA; +defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( +// Equation(s): +// \z80_|execute_|fMRead~27_combout = ((\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ixy_d~4_combout & \z80_|sequencer_|DFFE_M2_ff~q ))) # (!\z80_|execute_|fMRead~26_combout ) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|fMRead~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~27 .lut_mask = 16'h20FF; +defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Equation(s): +// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|pla_decode_|Equal41~2_combout ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hFB33; +defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( +// Equation(s): +// \z80_|execute_|fMRead~29_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((\z80_|ir_|opcode [7]) # (\z80_|ir_|opcode [6])))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|fMRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC080; +defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( +// Equation(s): +// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~10_combout ) # ((\z80_|execute_|ctl_ir_we~9_combout ) # (\z80_|execute_|fMRead~29_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|fMRead~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( +// Equation(s): +// \z80_|execute_|fMRead~31_combout = (\z80_|pla_decode_|Equal33~3_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal33~3_combout & (\z80_|pla_decode_|Equal6~1_combout & +// ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Equation(s): +// \z80_|execute_|fMRead~32_combout = (\z80_|execute_|fMRead~28_combout ) # ((\z80_|execute_|fMRead~30_combout ) # ((\z80_|execute_|fMRead~31_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ))) + + .dataa(\z80_|execute_|fMRead~28_combout ), + .datab(\z80_|execute_|fMRead~30_combout ), + .datac(\z80_|execute_|fMRead~31_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~37 ( +// Equation(s): +// \z80_|execute_|fMRead~37_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_mRead~13_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~37 .lut_mask = 16'h0E00; +defparam \z80_|execute_|fMRead~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Equation(s): +// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~27_combout ) # (((\z80_|execute_|fMRead~32_combout ) # (\z80_|execute_|fMRead~37_combout )) # (!\z80_|execute_|fMRead~6_combout )) + + .dataa(\z80_|execute_|fMRead~27_combout ), + .datab(\z80_|execute_|fMRead~6_combout ), + .datac(\z80_|execute_|fMRead~32_combout ), + .datad(\z80_|execute_|fMRead~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( +// Equation(s): +// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & (\z80_|execute_|ctl_alu_oe~2_combout & +// ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~16_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ctl_mRead~16_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~24 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( +// Equation(s): +// \z80_|execute_|fMRead~25_combout = ((\z80_|execute_|fMRead~24_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~33_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|pc_inc_hold~33_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|fMRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~25 .lut_mask = 16'hFF2F; +defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( +// Equation(s): +// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_ir_we~12_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~21_combout ) # (\z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_mRead~21_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~16 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( +// Equation(s): +// \z80_|execute_|fMRead~11_combout = ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ctl_mRead~21_combout ) # (!\z80_|execute_|nextM~3_combout ))) # (!\z80_|execute_|pc_inc_hold~14_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~14_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_mRead~21_combout ), + .datad(\z80_|execute_|nextM~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Equation(s): +// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (!\z80_|execute_|ctl_mRead~2_combout & (!\z80_|pla_decode_|Equal6~1_combout & !\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datab(\z80_|execute_|ctl_mRead~2_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~12 .lut_mask = 16'h0002; +defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Equation(s): +// \z80_|execute_|fMRead~13_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|fMRead~11_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # (!\z80_|execute_|fMRead~12_combout )))) + + .dataa(\z80_|execute_|fMRead~11_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|fMRead~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~13 .lut_mask = 16'hC8CC; +defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Equation(s): +// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout ))) .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFBFA; +defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N10 +cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Equation(s): +// \z80_|execute_|fMRead~15_combout = (!\z80_|execute_|fMWrite~2_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|fMRead~14_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|fMWrite~2_combout ), .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|fMRead~14_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .combout(\z80_|execute_|fMRead~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~15 .lut_mask = 16'h3332; +defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( +// Location: LCCOMB_X34_Y6_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_bus_db_oe~5_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) +// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~15_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|fMRead~16_combout ))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|fMRead~16_combout ), + .datac(\z80_|execute_|fMRead~13_combout ), + .datad(\z80_|execute_|fMRead~15_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .combout(\z80_|execute_|fMRead~17_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFDF5; -defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~17 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( +// Location: LCCOMB_X34_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) +// \z80_|execute_|fMRead~22_combout = (((\z80_|execute_|fMRead~17_combout ) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|fMRead~21_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datab(\z80_|execute_|fMRead~21_combout ), + .datac(\z80_|execute_|fMRead~17_combout ), + .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( +// Equation(s): +// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|fMRead~23_combout ) # ((\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|fMRead~25_combout ) # (\z80_|execute_|fMRead~22_combout ))) + + .dataa(\z80_|execute_|fMRead~23_combout ), + .datab(\z80_|execute_|fMRead~33_combout ), + .datac(\z80_|execute_|fMRead~25_combout ), + .datad(\z80_|execute_|fMRead~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~36 ( +// Equation(s): +// \z80_|execute_|fMRead~36_combout = (\z80_|execute_|fMRead~34_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((\z80_|execute_|fMRead~35_combout & !\z80_|execute_|fMRead~2_combout ))) + + .dataa(\z80_|execute_|fMRead~35_combout ), + .datab(\z80_|execute_|fMRead~34_combout ), + .datac(\z80_|execute_|fMRead~2_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~36 .lut_mask = 16'hFFCE; +defparam \z80_|execute_|fMRead~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout )) .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|fMRead~36_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .combout(\z80_|pin_control_|bus_db_pin_re~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; -defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; +defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFC0; +defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Location: LCCOMB_X21_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~103 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (\z80_|execute_|ctl_bus_db_oe~4_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hAAA2; -defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( -// Equation(s): -// \z80_|bus_control_|db[0]~6_combout = (\z80_|execute_|ctl_bus_db_oe~combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) - - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFAFF; -defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~93 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~93_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~47_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~93_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~93 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[1][3]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~94 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~94_combout = (\ula_|zx_keyboard_|keys[1][3]~93_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # -// (!\ula_|zx_keyboard_|keys[1][3]~93_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[1][3]~93_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~94 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][3]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N31 -dffeas \ula_|zx_keyboard_|keys[1][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) +// \ula_|zx_keyboard_|keys[5][3]~103_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5])) .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .combout(\ula_|zx_keyboard_|keys[5][3]~103_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][3]~103 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|keys[5][3]~103 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~98 ( +// Location: LCCOMB_X20_Y10_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~20 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~98_combout = (\ula_|zx_keyboard_|keys[0][3]~96_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & -// (\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][3]~96_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) +// \ula_|zx_keyboard_|keys[5][4]~20_combout = (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) - .dataa(\ula_|zx_keyboard_|keys[0][3]~96_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .datac(\ula_|zx_keyboard_|keys[0][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~98_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~98 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[0][3]~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N1 -dffeas \ula_|zx_keyboard_|keys[0][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][3]~98_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N4 -cycloneive_lcell_comb \D[3]~65 ( -// Equation(s): -// \D[3]~65_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][3]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][3]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][3]~q ), - .cin(gnd), - .combout(\D[3]~65_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~65 .lut_mask = 16'h8CAF; -defparam \D[3]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~99 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~99_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), .datad(gnd), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~99_combout ), + .combout(\ula_|zx_keyboard_|keys[5][4]~20_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~99 .lut_mask = 16'h4040; -defparam \ula_|zx_keyboard_|keys[3][3]~99 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][4]~20 .lut_mask = 16'hC0C0; +defparam \ula_|zx_keyboard_|keys[5][4]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~100 ( +// Location: LCCOMB_X20_Y10_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~21 ( // Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~100_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[3][3]~99_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][3]~99_combout & (\ula_|zx_keyboard_|keys[3][3]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[3][3]~q )))) +// \ula_|zx_keyboard_|keys[1][4]~21_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) - .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .datab(\ula_|zx_keyboard_|keys[3][3]~99_combout ), - .datac(\ula_|zx_keyboard_|keys[3][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~100_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~100 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[3][3]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N9 -dffeas \ula_|zx_keyboard_|keys[3][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][3]~100_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'hCCDD; -defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .combout(\ula_|zx_keyboard_|keys[1][4]~21_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[1][4]~21 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[1][4]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~133 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~133_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][3]~102_combout & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|zx_keyboard_|keys[2][3]~102_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~133_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~133 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[2][3]~133 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~103 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~103_combout = (\ula_|zx_keyboard_|keys[2][3]~133_combout & (!\ula_|zx_keyboard_|keys[2][3]~101_combout )) # (!\ula_|zx_keyboard_|keys[2][3]~133_combout & ((\ula_|zx_keyboard_|keys[2][3]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[2][3]~101_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][3]~133_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~103 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[2][3]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N3 -dffeas \ula_|zx_keyboard_|keys[2][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N28 -cycloneive_lcell_comb \D[3]~66 ( -// Equation(s): -// \D[3]~66_combout = (\z80_|address_pins_|abus[11]~19_combout & (((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & -// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[3][3]~q ), - .datac(\z80_|address_pins_|abus[10]~24_combout ), - .datad(\ula_|zx_keyboard_|keys[2][3]~q ), - .cin(gnd), - .combout(\D[3]~66_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~66 .lut_mask = 16'hB0BB; -defparam \D[3]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N12 +// Location: LCCOMB_X21_Y8_N24 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) +// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|zx_keyboard_|keys[5][3]~103_combout & ((\ula_|zx_keyboard_|keys[1][4]~21_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][4]~21_combout & ((\ula_|zx_keyboard_|keys[5][3]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][3]~103_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(gnd), + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[5][3]~103_combout ), + .datac(\ula_|zx_keyboard_|keys[5][3]~q ), + .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h0808; +defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h74F0; defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y19_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~105 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~105_combout = (\ula_|zx_keyboard_|keys[5][3]~104_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[5][3]~q -// )))) # (!\ula_|zx_keyboard_|keys[5][3]~104_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][3]~104_combout ), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[5][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~105_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~105 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][3]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N23 +// Location: FF_X21_Y8_N25 dffeas \ula_|zx_keyboard_|keys[5][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][3]~105_combout ), + .d(\ula_|zx_keyboard_|keys[5][3]~104_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52094,32 +44426,49 @@ defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y19_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( +// Location: LCCOMB_X19_Y9_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~73 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|WideOr16~2_combout ))) +// \ula_|zx_keyboard_|keys[3][0]~73_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1])) - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .combout(\ula_|zx_keyboard_|keys[3][0]~73_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[3][0]~73 .lut_mask = 16'h0500; +defparam \ula_|zx_keyboard_|keys[3][0]~73 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( +// Location: LCCOMB_X19_Y10_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( // Equation(s): -// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) +// \ula_|zx_keyboard_|Selector5~0_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[3][0]~73_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]))) .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|zx_keyboard_|keys[3][0]~73_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), .cin(gnd), .combout(\ula_|zx_keyboard_|Selector5~1_combout ), .cout()); @@ -52128,96 +44477,113 @@ defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h0800; defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( +// Location: LCCOMB_X19_Y10_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~129 ( // Equation(s): -// \ula_|zx_keyboard_|Selector5~0_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5]))) +// \ula_|zx_keyboard_|keys[4][3]~129_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|Selector5~1_combout ))) - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~134 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~134_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|zx_keyboard_|Selector5~1_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|Selector5~1_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), .datab(\ula_|zx_keyboard_|Selector5~0_combout ), .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|Selector5~1_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~134_combout ), + .combout(\ula_|zx_keyboard_|keys[4][3]~129_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~134 .lut_mask = 16'hCECC; -defparam \ula_|zx_keyboard_|keys[4][3]~134 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[4][3]~129 .lut_mask = 16'hCECC; +defparam \ula_|zx_keyboard_|keys[4][3]~129 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N6 +// Location: LCCOMB_X21_Y10_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~1 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~1_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~1 .lut_mask = 16'h0030; +defparam \ula_|zx_keyboard_|WideOr16~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~105 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~105_combout = (\ula_|zx_keyboard_|WideOr16~1_combout & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) + + .dataa(\ula_|zx_keyboard_|WideOr16~1_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~105_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~105 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][3]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|zx_keyboard_|extended~q & (((\ula_|zx_keyboard_|keys[4][3]~105_combout )))) # (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~129_combout & (\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~129_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[4][3]~105_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'hEC20; +defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~130 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~130_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~130_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~130 .lut_mask = 16'hAAAE; +defparam \ula_|zx_keyboard_|keys[4][3]~130 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N2 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~107 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~106_combout )) # (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][3]~134_combout )))) +// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & ((\ula_|zx_keyboard_|keys[4][3]~106_combout & ((!\ula_|zx_keyboard_|keys[4][3]~130_combout ))) # (!\ula_|zx_keyboard_|keys[4][3]~106_combout & +// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) - .dataa(\ula_|zx_keyboard_|extended~q ), + .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), .datab(\ula_|zx_keyboard_|keys[4][3]~106_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][3]~134_combout ), + .datac(\ula_|zx_keyboard_|keys[4][3]~q ), + .datad(\ula_|zx_keyboard_|keys[4][3]~130_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[4][3]~107_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'hD888; +defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'h70F8; defparam \ula_|zx_keyboard_|keys[4][3]~107 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~135 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~135_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q ))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~135_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~135 .lut_mask = 16'hCDCC; -defparam \ula_|zx_keyboard_|keys[4][3]~135 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~108 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~108_combout = (\ula_|zx_keyboard_|keys[4][3]~107_combout & ((\ula_|zx_keyboard_|keys[0][0]~15_combout & ((!\ula_|zx_keyboard_|keys[4][3]~135_combout ))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & -// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[4][3]~107_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~107_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\ula_|zx_keyboard_|keys[4][3]~135_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~108_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~108 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][3]~108 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N23 +// Location: FF_X21_Y8_N3 dffeas \ula_|zx_keyboard_|keys[4][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][3]~108_combout ), + .d(\ula_|zx_keyboard_|keys[4][3]~107_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52233,79 +44599,257 @@ defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y19_N20 -cycloneive_lcell_comb \D[3]~67 ( +// Location: LCCOMB_X21_Y8_N12 +cycloneive_lcell_comb \D[3]~74 ( // Equation(s): -// \D[3]~67_combout = (\ula_|zx_keyboard_|keys[5][3]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][3]~q & -// (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) +// \D[3]~74_combout = (\z80_|address_pins_|abus[12]~24_combout & (((\z80_|address_pins_|abus[13]~23_combout )) # (!\ula_|zx_keyboard_|keys[5][3]~q ))) # (!\z80_|address_pins_|abus[12]~24_combout & (!\ula_|zx_keyboard_|keys[4][3]~q & +// ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) - .dataa(\ula_|zx_keyboard_|keys[5][3]~q ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), + .dataa(\z80_|address_pins_|abus[12]~24_combout ), + .datab(\ula_|zx_keyboard_|keys[5][3]~q ), + .datac(\z80_|address_pins_|abus[13]~23_combout ), + .datad(\ula_|zx_keyboard_|keys[4][3]~q ), .cin(gnd), - .combout(\D[3]~67_combout ), + .combout(\D[3]~74_combout ), .cout()); // synopsys translate_off -defparam \D[3]~67 .lut_mask = 16'hDD0D; -defparam \D[3]~67 .sum_lutc_input = "datac"; +defparam \D[3]~74 .lut_mask = 16'hA2F3; +defparam \D[3]~74 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~112 ( +// Location: LCCOMB_X20_Y8_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~112_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~32_combout ) # ((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~61_combout )))) +// \ula_|zx_keyboard_|keys[5][1]~39_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[0][0]~11_combout & !\ula_|zx_keyboard_|extended~q )) - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~112_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~112 .lut_mask = 16'hA888; -defparam \ula_|zx_keyboard_|keys[7][3]~112 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~113 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~113_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][3]~112_combout & (\ula_|zx_keyboard_|keys[0][0]~15_combout & !\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[7][3]~112_combout ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[0][0]~11_combout ), .datad(\ula_|zx_keyboard_|extended~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~113_combout ), + .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~113 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[7][3]~113 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~114 ( +// Location: LCCOMB_X21_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~100 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~114_combout = (\ula_|zx_keyboard_|keys[7][3]~113_combout & ((!\ula_|zx_keyboard_|keys[0][4]~111_combout ))) # (!\ula_|zx_keyboard_|keys[7][3]~113_combout & (\ula_|zx_keyboard_|keys[7][3]~q )) +// \ula_|zx_keyboard_|keys[2][3]~100_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & +// !\ula_|ps2_keyboard_|shiftreg [2])) .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[7][3]~113_combout ), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~111_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .combout(\ula_|zx_keyboard_|keys[2][3]~100_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~114 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[7][3]~114 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][3]~100 .lut_mask = 16'h0C30; +defparam \ula_|zx_keyboard_|keys[2][3]~100 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y20_N9 +// Location: LCCOMB_X21_Y10_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|keys[2][3]~100_combout & (\ula_|zx_keyboard_|keys[5][4]~59_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (!\ula_|ps2_keyboard_|shiftreg [3])))) + + .dataa(\ula_|zx_keyboard_|keys[2][3]~100_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[5][4]~59_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'h8200; +defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~99 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~99_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~99 .lut_mask = 16'hF0F5; +defparam \ula_|zx_keyboard_|keys[2][3]~99 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & ((\ula_|zx_keyboard_|keys[2][3]~101_combout & ((!\ula_|zx_keyboard_|keys[2][3]~99_combout ))) # (!\ula_|zx_keyboard_|keys[2][3]~101_combout & +// (\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~39_combout & (((\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .datab(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .datac(\ula_|zx_keyboard_|keys[2][3]~q ), + .datad(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y7_N23 +dffeas \ula_|zx_keyboard_|keys[2][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~97 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~97_combout = (\ula_|zx_keyboard_|keys[6][4]~44_combout & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[5][4]~59_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~44_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[5][4]~59_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~97_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~97 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[3][3]~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~98 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~98_combout = (\ula_|zx_keyboard_|keys[3][3]~97_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][3]~97_combout & ((\ula_|zx_keyboard_|keys[3][3]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][3]~97_combout ), + .datac(\ula_|zx_keyboard_|keys[3][3]~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~98_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~98 .lut_mask = 16'h7474; +defparam \ula_|zx_keyboard_|keys[3][3]~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y7_N25 +dffeas \ula_|zx_keyboard_|keys[3][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][3]~98_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N20 +cycloneive_lcell_comb \D[3]~73 ( +// Equation(s): +// \D[3]~73_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~20_combout ) # ((!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & +// ((\z80_|address_pins_|abus[10]~20_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\z80_|address_pins_|abus[10]~20_combout ), + .datac(\ula_|zx_keyboard_|keys[2][3]~q ), + .datad(\ula_|zx_keyboard_|keys[3][3]~q ), + .cin(gnd), + .combout(\D[3]~73_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~73 .lut_mask = 16'h8ACF; +defparam \D[3]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~108 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~108_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~108 .lut_mask = 16'hFAF0; +defparam \ula_|zx_keyboard_|keys[0][4]~108 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~109 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~109_combout = (\ula_|zx_keyboard_|WideOr16~1_combout & ((\ula_|zx_keyboard_|keys[7][2]~28_combout ) # ((\ula_|zx_keyboard_|keys[7][2]~57_combout & \ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~57_combout ), + .datab(\ula_|zx_keyboard_|keys[7][2]~28_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|WideOr16~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~109_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~109 .lut_mask = 16'hEC00; +defparam \ula_|zx_keyboard_|keys[7][3]~109 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~110 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~110_combout = (\ula_|zx_keyboard_|keys[7][3]~109_combout & ((\ula_|zx_keyboard_|keys[7][2]~56_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[7][2]~56_combout & +// ((\ula_|zx_keyboard_|keys[7][3]~q ))))) # (!\ula_|zx_keyboard_|keys[7][3]~109_combout & (((\ula_|zx_keyboard_|keys[7][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .datab(\ula_|zx_keyboard_|keys[7][3]~109_combout ), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\ula_|zx_keyboard_|keys[7][2]~56_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~110_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~110 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[7][3]~110 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y8_N23 dffeas \ula_|zx_keyboard_|keys[7][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .d(\ula_|zx_keyboard_|keys[7][3]~110_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52321,79 +44865,79 @@ defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~109 ( +// Location: LCCOMB_X20_Y8_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~111 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~109_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [5]))) +// \ula_|zx_keyboard_|keys[6][3]~111_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), .datad(\ula_|ps2_keyboard_|shiftreg [5]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~109_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~111_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~109 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|keys[6][3]~109 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~111 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][3]~111 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~110 ( +// Location: LCCOMB_X20_Y8_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~112 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~110_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~109_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][2]~32_combout ))) +// \ula_|zx_keyboard_|keys[6][3]~112_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~111_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & ((\ula_|zx_keyboard_|keys[7][2]~28_combout )))) .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|zx_keyboard_|keys[6][3]~109_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|zx_keyboard_|keys[6][3]~111_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~112_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~110 .lut_mask = 16'hF088; -defparam \ula_|zx_keyboard_|keys[6][3]~110 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~112 .lut_mask = 16'hCAC0; +defparam \ula_|zx_keyboard_|keys[6][3]~112 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~137 ( +// Location: LCCOMB_X20_Y8_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~132 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~137_combout = (\ula_|zx_keyboard_|extended~q ) # (((!\ula_|zx_keyboard_|keys[0][0]~15_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][3]~110_combout )) +// \ula_|zx_keyboard_|keys[6][3]~132_combout = (((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][3]~112_combout )) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout ) - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .datab(\ula_|zx_keyboard_|keys[6][3]~112_combout ), .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~132_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~137 .lut_mask = 16'hBFFF; -defparam \ula_|zx_keyboard_|keys[6][3]~137 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~132 .lut_mask = 16'hFF7F; +defparam \ula_|zx_keyboard_|keys[6][3]~132 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~138 ( +// Location: LCCOMB_X23_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~133 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~138_combout = (\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~137_combout & ((\ula_|zx_keyboard_|keys[6][3]~q ))) # (!\ula_|zx_keyboard_|keys[6][3]~137_combout & -// (!\ula_|zx_keyboard_|Selector13~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|zx_keyboard_|keys[6][3]~q )))) +// \ula_|zx_keyboard_|keys[6][3]~133_combout = (\ula_|zx_keyboard_|keys[6][3]~132_combout & (((\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[6][3]~132_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & +// ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[6][3]~q )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|Selector13~0_combout ), + .dataa(\ula_|zx_keyboard_|keys[6][3]~132_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), .datac(\ula_|zx_keyboard_|keys[6][3]~q ), - .datad(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .datad(\ula_|zx_keyboard_|Selector13~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~133_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~138 .lut_mask = 16'hF072; -defparam \ula_|zx_keyboard_|keys[6][3]~138 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~133 .lut_mask = 16'hB0F4; +defparam \ula_|zx_keyboard_|keys[6][3]~133 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y21_N29 +// Location: FF_X23_Y8_N5 dffeas \ula_|zx_keyboard_|keys[6][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .d(\ula_|zx_keyboard_|keys[6][3]~133_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52409,115 +44953,220 @@ defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( +// Location: LCCOMB_X23_Y8_N30 +cycloneive_lcell_comb \D[3]~75 ( // Equation(s): -// \ula_|zx_keyboard_|key_row~2_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # ((!\ula_|zx_keyboard_|keys[6][3]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) +// \D[3]~75_combout = (\ula_|zx_keyboard_|keys[7][3]~q & (\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[7][3]~q & +// ((\z80_|address_pins_|abus[14]~22_combout ) # ((!\ula_|zx_keyboard_|keys[6][3]~q )))) - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [14]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|zx_keyboard_|keys[6][3]~q ), + .dataa(\ula_|zx_keyboard_|keys[7][3]~q ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ula_|zx_keyboard_|keys[6][3]~q ), + .datad(\z80_|address_pins_|abus[15]~21_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~2_combout ), + .combout(\D[3]~75_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hCFFF; -defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; +defparam \D[3]~75 .lut_mask = 16'hCF45; +defparam \D[3]~75 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N8 -cycloneive_lcell_comb \D[3]~68 ( +// Location: LCCOMB_X23_Y8_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~94 ( // Equation(s): -// \D[3]~68_combout = (\D[3]~67_combout & (\ula_|zx_keyboard_|key_row~2_combout & ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) +// \ula_|zx_keyboard_|keys[0][3]~94_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\D[3]~67_combout ), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|key_row~2_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\D[3]~68_combout ), + .combout(\ula_|zx_keyboard_|keys[0][3]~94_combout ), .cout()); // synopsys translate_off -defparam \D[3]~68 .lut_mask = 16'h8C00; -defparam \D[3]~68 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[0][3]~94 .lut_mask = 16'h2004; +defparam \ula_|zx_keyboard_|keys[0][3]~94 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N30 -cycloneive_lcell_comb \D[3]~69 ( +// Location: LCCOMB_X23_Y8_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~93 ( // Equation(s): -// \D[3]~69_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[3]~65_combout & (\D[3]~66_combout & \D[3]~68_combout ))) +// \ula_|zx_keyboard_|keys[2][4]~93_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|shifted~q )) - .dataa(\D[3]~65_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[3]~66_combout ), - .datad(\D[3]~68_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), .cin(gnd), - .combout(\D[3]~69_combout ), + .combout(\ula_|zx_keyboard_|keys[2][4]~93_combout ), .cout()); // synopsys translate_off -defparam \D[3]~69 .lut_mask = 16'hECCC; -defparam \D[3]~69 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][4]~93 .lut_mask = 16'hF0FA; +defparam \ula_|zx_keyboard_|keys[2][4]~93 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y11_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: LCCOMB_X23_Y7_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~95 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~95_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~95 .lut_mask = 16'h0060; +defparam \ula_|zx_keyboard_|keys[0][4]~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|zx_keyboard_|keys[0][3]~94_combout & ((\ula_|zx_keyboard_|keys[0][4]~95_combout & (!\ula_|zx_keyboard_|keys[2][4]~93_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & +// ((\ula_|zx_keyboard_|keys[0][3]~q ))))) # (!\ula_|zx_keyboard_|keys[0][3]~94_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][3]~94_combout ), + .datab(\ula_|zx_keyboard_|keys[2][4]~93_combout ), + .datac(\ula_|zx_keyboard_|keys[0][3]~q ), + .datad(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y8_N3 +dffeas \ula_|zx_keyboard_|keys[0][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), - .portbdataout()); + .q(\ula_|zx_keyboard_|keys[0][3]~q ), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; // synopsys translate_on -// Location: M9K_X22_Y15_N0 +// Location: LCCOMB_X19_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~91 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~91_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][4]~15_combout & \ula_|zx_keyboard_|keys[6][4]~43_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[7][4]~15_combout ), + .datad(\ula_|zx_keyboard_|keys[6][4]~43_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~91_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~91 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[1][3]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~92 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~92_combout = (\ula_|zx_keyboard_|keys[1][3]~91_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # +// (!\ula_|zx_keyboard_|keys[1][3]~91_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][3]~91_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~92 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][3]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y9_N5 +dffeas \ula_|zx_keyboard_|keys[1][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N8 +cycloneive_lcell_comb \D[3]~72 ( +// Equation(s): +// \D[3]~72_combout = (\z80_|address_pins_|abus[9]~17_combout & (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][3]~q ))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][3]~q & +// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\z80_|address_pins_|abus[9]~17_combout ), + .datab(\ula_|zx_keyboard_|keys[0][3]~q ), + .datac(\z80_|address_pins_|abus[8]~18_combout ), + .datad(\ula_|zx_keyboard_|keys[1][3]~q ), + .cin(gnd), + .combout(\D[3]~72_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~72 .lut_mask = 16'hA2F3; +defparam \D[3]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N10 +cycloneive_lcell_comb \D[3]~76 ( +// Equation(s): +// \D[3]~76_combout = (\D[3]~74_combout & (\D[3]~73_combout & (\D[3]~75_combout & \D[3]~72_combout ))) + + .dataa(\D[3]~74_combout ), + .datab(\D[3]~73_combout ), + .datac(\D[3]~75_combout ), + .datad(\D[3]~72_combout ), + .cin(gnd), + .combout(\D[3]~76_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~76 .lut_mask = 16'h8000; +defparam \D[3]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N2 +cycloneive_lcell_comb \D[3]~122 ( +// Equation(s): +// \D[3]~122_combout = (\Equal2~0_combout & ((\D[3]~76_combout ) # ((\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) + + .dataa(\D[3]~76_combout ), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\Equal2~0_combout ), + .cin(gnd), + .combout(\D[3]~122_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~122 .lut_mask = 16'hEF00; +defparam \D[3]~122 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y14_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), @@ -52533,8 +45182,8 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52574,7 +45223,24 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; // synopsys translate_on -// Location: M9K_X22_Y18_N0 +// Location: LCCOMB_X25_Y15_N28 +cycloneive_lcell_comb \D[3]~79 ( +// Equation(s): +// \D[3]~79_combout = (!\Equal2~0_combout & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\Equal2~0_combout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\D[3]~79_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~79 .lut_mask = 16'h3332; +defparam \D[3]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), @@ -52590,8 +45256,8 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52631,25 +45297,7 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N14 -cycloneive_lcell_comb \D[3]~73 ( -// Equation(s): -// \D[3]~73_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .cin(gnd), - .combout(\D[3]~73_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~73 .lut_mask = 16'hCCE2; -defparam \D[3]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y5_N0 +// Location: M9K_X22_Y15_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), .portare(vcc), @@ -52665,8 +45313,8 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52706,42 +45354,24 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N16 -cycloneive_lcell_comb \D[3]~74 ( -// Equation(s): -// \D[3]~74_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\D[3]~73_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ))) # (!\D[3]~73_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[3]~73_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datac(\D[3]~73_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), - .cin(gnd), - .combout(\D[3]~74_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~74 .lut_mask = 16'hF858; -defparam \D[3]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y19_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(vcc), +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52750,39 +45380,238 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y23_N0 +// Location: M9K_X33_Y12_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N20 +cycloneive_lcell_comb \D[3]~77 ( +// Equation(s): +// \D[3]~77_combout = (\z80_|address_pins_|abus[15]~21_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) # (!\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # +// ((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\D[3]~77_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~77 .lut_mask = 16'hF5E4; +defparam \D[3]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N22 +cycloneive_lcell_comb \D[3]~80 ( +// Equation(s): +// \D[3]~80_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~77_combout ))) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\D[3]~77_combout ), + .cin(gnd), + .combout(\D[3]~80_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~80 .lut_mask = 16'hCFC0; +defparam \D[3]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N4 +cycloneive_lcell_comb \D[3]~81 ( +// Equation(s): +// \D[3]~81_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[3]~80_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout +// )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datac(\D[3]~80_combout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\D[3]~81_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~81 .lut_mask = 16'hF0DD; +defparam \D[3]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N30 +cycloneive_lcell_comb \D[3]~124 ( +// Equation(s): +// \D[3]~124_combout = (\D[3]~77_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ) # ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datad(\D[3]~77_combout ), + .cin(gnd), + .combout(\D[3]~124_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~124 .lut_mask = 16'hF200; +defparam \D[3]~124 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y23_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), @@ -52792,14 +45621,14 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52855,26 +45684,8 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N24 -cycloneive_lcell_comb \D[3]~70 ( -// Equation(s): -// \D[3]~70_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~23_combout )) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\z80_|address_pins_|abus[14]~23_combout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .cin(gnd), - .combout(\D[3]~70_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~70 .lut_mask = 16'hEC64; -defparam \D[3]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y21_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( +// Location: M9K_X22_Y32_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), @@ -52883,14 +45694,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52899,217 +45710,143 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N22 -cycloneive_lcell_comb \D[3]~71 ( +// Location: LCCOMB_X25_Y15_N0 +cycloneive_lcell_comb \D[3]~123 ( // Equation(s): -// \D[3]~71_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout $ (((\D[3]~70_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout & !\D[3]~70_combout )))) +// \D[3]~123_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & (\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # (!\z80_|address_pins_|DFFE_apin_latch [14] & +// ((\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datad(\D[3]~70_combout ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), .cin(gnd), - .combout(\D[3]~71_combout ), + .combout(\D[3]~123_combout ), .cout()); // synopsys translate_off -defparam \D[3]~71 .lut_mask = 16'h22D8; -defparam \D[3]~71 .sum_lutc_input = "datac"; +defparam \D[3]~123 .lut_mask = 16'hF2D0; +defparam \D[3]~123 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y31_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N20 -cycloneive_lcell_comb \D[3]~72 ( +// Location: LCCOMB_X25_Y15_N10 +cycloneive_lcell_comb \D[3]~78 ( // Equation(s): -// \D[3]~72_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\D[3]~70_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~70_combout & (!\D[3]~71_combout & -// \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout )) # (!\D[3]~70_combout & (\D[3]~71_combout )))) +// \D[3]~78_combout = (!\Equal2~0_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~123_combout ))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\D[3]~124_combout )))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\D[3]~70_combout ), - .datac(\D[3]~71_combout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .dataa(\Equal2~0_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[3]~124_combout ), + .datad(\D[3]~123_combout ), .cin(gnd), - .combout(\D[3]~72_combout ), + .combout(\D[3]~78_combout ), .cout()); // synopsys translate_off -defparam \D[3]~72 .lut_mask = 16'h9C98; -defparam \D[3]~72 .sum_lutc_input = "datac"; +defparam \D[3]~78 .lut_mask = 16'h5410; +defparam \D[3]~78 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N28 +// Location: LCCOMB_X25_Y15_N6 +cycloneive_lcell_comb \D[3]~82 ( +// Equation(s): +// \D[3]~82_combout = (\z80_|address_pins_|abus[15]~21_combout & (\D[3]~79_combout & (\D[3]~81_combout ))) # (!\z80_|address_pins_|abus[15]~21_combout & (((\D[3]~78_combout )))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\D[3]~79_combout ), + .datac(\D[3]~81_combout ), + .datad(\D[3]~78_combout ), + .cin(gnd), + .combout(\D[3]~82_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~82 .lut_mask = 16'hD580; +defparam \D[3]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N26 cycloneive_lcell_comb \D[3]~108 ( // Equation(s): -// \D[3]~108_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[3]~74_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[3]~72_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[3]~74_combout )))) +// \D[3]~108_combout = ((\D[3]~122_combout ) # (\D[3]~82_combout )) # (!\Equal2~1_combout ) - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\D[3]~74_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[3]~72_combout ), + .dataa(\Equal2~1_combout ), + .datab(\D[3]~122_combout ), + .datac(gnd), + .datad(\D[3]~82_combout ), .cin(gnd), .combout(\D[3]~108_combout ), .cout()); // synopsys translate_off -defparam \D[3]~108 .lut_mask = 16'hDC8C; +defparam \D[3]~108 .lut_mask = 16'hFFDD; defparam \D[3]~108 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N4 -cycloneive_lcell_comb \D[3]~95 ( +// Location: LCCOMB_X25_Y15_N8 +cycloneive_lcell_comb \D[3]~109 ( // Equation(s): -// \D[3]~95_combout = ((\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout )))) # (!\Equal2~1_combout ) +// \D[3]~109_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [3] & (\D[3]~108_combout ))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[3]~108_combout ) # (!\Equal2~1_combout )))) - .dataa(\D[3]~69_combout ), - .datab(\Equal2~1_combout ), - .datac(\Equal2~0_combout ), - .datad(\D[3]~108_combout ), + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|data_pins_|dout [3]), + .datac(\D[3]~108_combout ), + .datad(\Equal2~1_combout ), .cin(gnd), - .combout(\D[3]~95_combout ), + .combout(\D[3]~109_combout ), .cout()); // synopsys translate_off -defparam \D[3]~95 .lut_mask = 16'hBFB3; -defparam \D[3]~95 .sum_lutc_input = "datac"; +defparam \D[3]~109 .lut_mask = 16'hD0D5; +defparam \D[3]~109 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N26 -cycloneive_lcell_comb \D[3]~96 ( -// Equation(s): -// \D[3]~96_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [3] & \D[3]~95_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[3]~95_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [3]), - .datad(\D[3]~95_combout ), - .cin(gnd), - .combout(\D[3]~96_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~96 .lut_mask = 16'hF511; -defparam \D[3]~96 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N6 +// Location: LCCOMB_X28_Y12_N4 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[3]~21_combout ) # ((\D[3]~96_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[3]~96_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[3]~109_combout ) # ((\z80_|bus_control_|db[3]~21_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & +// (((\z80_|bus_control_|db[3]~21_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[3]~96_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), + .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), + .datab(\D[3]~109_combout ), + .datac(\z80_|bus_control_|db[3]~21_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hF888; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N7 +// Location: FF_X28_Y12_N5 dffeas \z80_|data_pins_|dout[3] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), @@ -53128,41 +45865,41 @@ defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N4 +// Location: LCCOMB_X28_Y12_N22 cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( // Equation(s): // \z80_|bus_control_|db[3]~20_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(\z80_|data_pins_|dout [3]), - .datac(gnd), + .dataa(gnd), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|data_pins_|dout [3]), .datad(\z80_|bus_control_|db[0]~4_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[3]~20_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hDD00; +defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hF300; defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N0 +// Location: LCCOMB_X27_Y12_N28 cycloneive_lcell_comb \z80_|bus_control_|db[3]~21 ( // Equation(s): -// \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~36_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|bus_control_|db[0]~6_combout ), + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), .datab(\z80_|bus_control_|db[3]~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|alu_control_|db[3]~36_combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[3]~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hDD5D; +defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hC4FF; defparam \z80_|bus_control_|db[3]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y10_N1 +// Location: FF_X27_Y12_N29 dffeas \z80_|ir_|opcode[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|bus_control_|db[3]~21_combout ), @@ -53181,41 +45918,7772 @@ defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( +// Location: LCCOMB_X39_Y8_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~4_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) +// \z80_|pla_decode_|Equal33~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4])) .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal52~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~4_combout ), + .combout(\z80_|pla_decode_|Equal33~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N20 +// Location: LCCOMB_X36_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N4 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( +// Equation(s): +// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hCECF; +defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N6 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( +// Equation(s): +// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|bus_control_|db[0]~4_combout ), + .datab(\z80_|alu_control_|db[7]~37_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'h88AA; +defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y1_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 .lut_mask = 16'hCFA0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N2 +cycloneive_lcell_comb \D[5]~97 ( +// Equation(s): +// \D[5]~97_combout = (\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|control_pins_|pin_nIORQ~1_combout ))) + + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), + .cin(gnd), + .combout(\D[5]~97_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~97 .lut_mask = 16'h2000; +defparam \D[5]~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y21_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y3_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: M9K_X33_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y27_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N6 +cycloneive_lcell_comb \Mux0~0 ( +// Equation(s): +// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) # (!\z80_|address_pins_|abus[14]~22_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~0 .lut_mask = 16'hB9A8; +defparam \Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N4 +cycloneive_lcell_comb \Mux0~1 ( +// Equation(s): +// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datad(\Mux0~0_combout ), + .cin(gnd), + .combout(\Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~1 .lut_mask = 16'hDDA0; +defparam \Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N20 +cycloneive_lcell_comb \D[7]~116 ( +// Equation(s): +// \D[7]~116_combout = ((\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )) # (!\z80_|address_pins_|abus[15]~21_combout & ((\Mux0~1_combout )))) # (!\D[5]~97_combout ) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .datab(\D[5]~97_combout ), + .datac(\z80_|address_pins_|abus[15]~21_combout ), + .datad(\Mux0~1_combout ), + .cin(gnd), + .combout(\D[7]~116_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~116 .lut_mask = 16'hBFB3; +defparam \D[7]~116 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N26 +cycloneive_lcell_comb \D[7]~117 ( +// Equation(s): +// \D[7]~117_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [7] & \D[7]~116_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[7]~116_combout )) # (!\Equal2~1_combout ))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [7]), + .datad(\D[7]~116_combout ), + .cin(gnd), + .combout(\D[7]~117_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~117 .lut_mask = 16'hF311; +defparam \D[7]~117 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N0 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\z80_|bus_control_|db[7]~7_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[7]~117_combout )))) # (!\z80_|bus_control_|db[7]~7_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[7]~117_combout ))) + + .dataa(\z80_|bus_control_|db[7]~7_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\D[7]~117_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N1 +dffeas \z80_|data_pins_|dout[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N20 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( +// Equation(s): +// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[7]~5_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|bus_control_|db[0]~6_combout ), + .datad(\z80_|data_pins_|dout [7]), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hAF2F; +defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N13 +dffeas \z80_|ir_|opcode[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[7]~7_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~2_combout = (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~0_combout & \z80_|pla_decode_|Equal41~1_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datad(\z80_|pla_decode_|Equal41~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|pla_decode_|Equal36~0_combout & (((\z80_|pla_decode_|Equal41~2_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # +// (!\z80_|pla_decode_|Equal36~0_combout & (\z80_|pla_decode_|Equal41~2_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal36~0_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hC0EA; +defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h3222; +defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y7_N9 +dffeas \z80_|decode_state_|DFFE_instCB ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instCB~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|execute_|comb~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N29 +dffeas \z80_|interrupts_|im1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_im_we~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|im1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|interrupts_|im1~q ), + .datad(\z80_|interrupts_|im2~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hC4C0; +defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & +// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h4F0A; +defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_ff_oe~1_combout & (!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0203; +defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_bus_db_oe~5_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; +defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (\z80_|execute_|ctl_bus_db_oe~4_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hAAA2; +defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~88 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~88_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~88_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~88 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[6][0]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~1_combout = (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~89 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~89_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|zx_keyboard_|keys[6][0]~88_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|shifted~1_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .datab(\ula_|zx_keyboard_|keys[6][0]~88_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|shifted~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~89 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[6][0]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|zx_keyboard_|keys[6][0]~89_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][0]~89_combout & ((\ula_|zx_keyboard_|keys[6][0]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[6][0]~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h7272; +defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y10_N23 +dffeas \ula_|zx_keyboard_|keys[6][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~84 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~84_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~84_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~84 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[7][0]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~78 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~78_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~78 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[5][0]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~85 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~85_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[5][0]~78_combout ) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[5][0]~78_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~85_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~85 .lut_mask = 16'h3300; +defparam \ula_|zx_keyboard_|keys[7][0]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~86 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~86_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[3][0]~73_combout & (\ula_|zx_keyboard_|keys[5][4]~20_combout ))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|keys[7][0]~85_combout +// )))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~73_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~20_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|keys[7][0]~85_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~86 .lut_mask = 16'h8F80; +defparam \ula_|zx_keyboard_|keys[7][0]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[7][0]~84_combout & ((\ula_|zx_keyboard_|keys[7][0]~86_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][0]~86_combout & ((\ula_|zx_keyboard_|keys[7][0]~q +// ))))) # (!\ula_|zx_keyboard_|keys[7][0]~84_combout & (((\ula_|zx_keyboard_|keys[7][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][0]~84_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[7][0]~q ), + .datad(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y10_N1 +dffeas \ula_|zx_keyboard_|keys[7][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N28 +cycloneive_lcell_comb \D[0]~57 ( +// Equation(s): +// \D[0]~57_combout = (\ula_|zx_keyboard_|keys[6][0]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\ula_|zx_keyboard_|keys[6][0]~q & +// (((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][0]~q ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[15]~21_combout ), + .datad(\ula_|zx_keyboard_|keys[7][0]~q ), + .cin(gnd), + .combout(\D[0]~57_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~57 .lut_mask = 16'hD0DD; +defparam \D[0]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~81 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~81_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [5]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & +// (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [5])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~81_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~81 .lut_mask = 16'h1024; +defparam \ula_|zx_keyboard_|keys[4][0]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~82 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~82_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~82_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~82 .lut_mask = 16'hF0FA; +defparam \ula_|zx_keyboard_|keys[4][0]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~40 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~40_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][1]~39_combout & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~40 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[5][1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~83 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~83_combout = (\ula_|zx_keyboard_|keys[4][0]~81_combout & ((\ula_|zx_keyboard_|keys[5][1]~40_combout & (!\ula_|zx_keyboard_|keys[4][0]~82_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~40_combout & +// ((\ula_|zx_keyboard_|keys[4][0]~q ))))) # (!\ula_|zx_keyboard_|keys[4][0]~81_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][0]~81_combout ), + .datab(\ula_|zx_keyboard_|keys[4][0]~82_combout ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~40_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~83_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~83 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][0]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y8_N23 +dffeas \ula_|zx_keyboard_|keys[4][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][0]~83_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~79 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~79_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (((!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[5][0]~78_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & +// ((\ula_|zx_keyboard_|keys[3][0]~73_combout ) # (\ula_|zx_keyboard_|keys[5][0]~78_combout )))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~73_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[5][0]~78_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~79_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~79 .lut_mask = 16'h3C20; +defparam \ula_|zx_keyboard_|keys[5][0]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~80 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~80_combout = (\ula_|zx_keyboard_|keys[6][1]~32_combout & ((\ula_|zx_keyboard_|keys[5][0]~79_combout & (!\ula_|zx_keyboard_|keys[5][0]~62_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~79_combout & +// ((\ula_|zx_keyboard_|keys[5][0]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~32_combout & (((\ula_|zx_keyboard_|keys[5][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~62_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~32_combout ), + .datac(\ula_|zx_keyboard_|keys[5][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][0]~79_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~80 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[5][0]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y9_N15 +dffeas \ula_|zx_keyboard_|keys[5][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N2 +cycloneive_lcell_comb \D[0]~56 ( +// Equation(s): +// \D[0]~56_combout = (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\z80_|address_pins_|abus[13]~23_combout & (!\ula_|zx_keyboard_|keys[5][0]~q & +// ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~23_combout ), + .datab(\z80_|address_pins_|abus[12]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][0]~q ), + .cin(gnd), + .combout(\D[0]~56_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~56 .lut_mask = 16'h8ACF; +defparam \D[0]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~76 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~76_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~21_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~76_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~76 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[1][0]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~77 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~77_combout = (\ula_|zx_keyboard_|keys[1][0]~76_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][0]~76_combout & ((\ula_|zx_keyboard_|keys[1][0]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[1][0]~q ), + .datad(\ula_|zx_keyboard_|keys[1][0]~76_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~77_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~77 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[1][0]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N23 +dffeas \ula_|zx_keyboard_|keys[1][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][0]~77_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~68 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~68_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~68_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~68 .lut_mask = 16'hC0C0; +defparam \ula_|zx_keyboard_|keys[4][3]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [2] & ((!\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & +// \ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0130; +defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~69 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~69_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|zx_keyboard_|WideOr0~0_combout )) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|keys[6][4]~43_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[6][4]~43_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~69_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~69 .lut_mask = 16'h2777; +defparam \ula_|zx_keyboard_|keys~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~70 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~70_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][3]~68_combout & !\ula_|zx_keyboard_|keys~69_combout )) # (!\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .datab(\ula_|zx_keyboard_|keys[4][3]~68_combout ), + .datac(\ula_|zx_keyboard_|keys~69_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~70_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~70 .lut_mask = 16'h08AA; +defparam \ula_|zx_keyboard_|keys[0][0]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~27 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~27_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~27 .lut_mask = 16'h3030; +defparam \ula_|zx_keyboard_|keys[4][1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & +// (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'hC002; +defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~71 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~71_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|WideOr4~0_combout )) # (!\ula_|zx_keyboard_|keys[4][1]~27_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[4][1]~27_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|WideOr4~0_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~71_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~71 .lut_mask = 16'h3313; +defparam \ula_|zx_keyboard_|keys~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~72 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~72_combout = (\ula_|zx_keyboard_|keys[0][0]~70_combout & ((\ula_|zx_keyboard_|keys~71_combout & ((\ula_|zx_keyboard_|keys[0][0]~q ))) # (!\ula_|zx_keyboard_|keys~71_combout & (!\ula_|zx_keyboard_|released~q )))) # +// (!\ula_|zx_keyboard_|keys[0][0]~70_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~70_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[0][0]~q ), + .datad(\ula_|zx_keyboard_|keys~71_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~72_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~72 .lut_mask = 16'hF072; +defparam \ula_|zx_keyboard_|keys[0][0]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y8_N11 +dffeas \ula_|zx_keyboard_|keys[0][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][0]~72_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~2_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # ((!\ula_|zx_keyboard_|keys[0][0]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [8]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hAFFF; +defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~22 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~22_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~21_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~22 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|keys[2][1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~75 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][0]~75_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~22_combout & (!\ula_|zx_keyboard_|released~q )) # +// (!\ula_|zx_keyboard_|keys[2][1]~22_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~22_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][0]~75_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0]~75 .lut_mask = 16'hD1F0; +defparam \ula_|zx_keyboard_|keys[2][0]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N15 +dffeas \ula_|zx_keyboard_|keys[2][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][0]~75_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~24 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~24_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~24 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[3][1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~74 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~74_combout = (\ula_|zx_keyboard_|keys[3][0]~73_combout & ((\ula_|zx_keyboard_|keys[3][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~24_combout & ((\ula_|zx_keyboard_|keys[3][0]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][0]~73_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][0]~73_combout ), + .datac(\ula_|zx_keyboard_|keys[3][0]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~24_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~74_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~74 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][0]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N17 +dffeas \ula_|zx_keyboard_|keys[3][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][0]~74_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N0 +cycloneive_lcell_comb \D[0]~54 ( +// Equation(s): +// \D[0]~54_combout = (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][0]~q )))) # (!\z80_|address_pins_|abus[10]~20_combout & (!\ula_|zx_keyboard_|keys[2][0]~q & +// ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][0]~q )))) + + .dataa(\z80_|address_pins_|abus[10]~20_combout ), + .datab(\z80_|address_pins_|abus[11]~19_combout ), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|keys[3][0]~q ), + .cin(gnd), + .combout(\D[0]~54_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~54 .lut_mask = 16'h8CAF; +defparam \D[0]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N12 +cycloneive_lcell_comb \D[0]~55 ( +// Equation(s): +// \D[0]~55_combout = (\ula_|zx_keyboard_|key_row~2_combout & (\D[0]~54_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][0]~q ), + .datab(\z80_|address_pins_|abus[9]~17_combout ), + .datac(\ula_|zx_keyboard_|key_row~2_combout ), + .datad(\D[0]~54_combout ), + .cin(gnd), + .combout(\D[0]~55_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~55 .lut_mask = 16'hD000; +defparam \D[0]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N0 +cycloneive_lcell_comb \D[0]~58 ( +// Equation(s): +// \D[0]~58_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~57_combout & (\D[0]~56_combout & \D[0]~55_combout ))) + + .dataa(\D[0]~57_combout ), + .datab(\D[0]~56_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[0]~55_combout ), + .cin(gnd), + .combout(\D[0]~58_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~58 .lut_mask = 16'hF8F0; +defparam \D[0]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N12 +cycloneive_lcell_comb \D[0]~62 ( +// Equation(s): +// \D[0]~62_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .cin(gnd), + .combout(\D[0]~62_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~62 .lut_mask = 16'hEC64; +defparam \D[0]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N8 +cycloneive_lcell_comb \D[0]~63 ( +// Equation(s): +// \D[0]~63_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~62_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~62_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # (!\D[0]~62_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[0]~62_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\D[0]~63_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~63 .lut_mask = 16'hE3E0; +defparam \D[0]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y29_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y4_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N6 +cycloneive_lcell_comb \D[0]~59 ( +// Equation(s): +// \D[0]~59_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout & +// (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .cin(gnd), + .combout(\D[0]~59_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~59 .lut_mask = 16'hE6A2; +defparam \D[0]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y29_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y11_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N28 +cycloneive_lcell_comb \D[0]~60 ( +// Equation(s): +// \D[0]~60_combout = (\z80_|address_pins_|abus[15]~21_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout $ (\D[0]~59_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout & ((!\D[0]~59_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datac(\z80_|address_pins_|abus[15]~21_combout ), + .datad(\D[0]~59_combout ), + .cin(gnd), + .combout(\D[0]~60_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~60 .lut_mask = 16'h30CA; +defparam \D[0]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N10 +cycloneive_lcell_comb \D[0]~61 ( +// Equation(s): +// \D[0]~61_combout = (\D[0]~59_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & !\D[0]~60_combout )))) # (!\D[0]~59_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~60_combout )))) + + .dataa(\D[0]~59_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datad(\D[0]~60_combout ), + .cin(gnd), + .combout(\D[0]~61_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~61 .lut_mask = 16'h99A8; +defparam \D[0]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N18 +cycloneive_lcell_comb \D[0]~120 ( +// Equation(s): +// \D[0]~120_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[0]~63_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[0]~61_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[0]~63_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\D[0]~63_combout ), + .datad(\D[0]~61_combout ), + .cin(gnd), + .combout(\D[0]~120_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~120 .lut_mask = 16'hF4B0; +defparam \D[0]~120 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N26 +cycloneive_lcell_comb \D[0]~64 ( +// Equation(s): +// \D[0]~64_combout = ((\Equal2~0_combout & (\D[0]~58_combout )) # (!\Equal2~0_combout & ((\D[0]~120_combout )))) # (!\Equal2~1_combout ) + + .dataa(\D[0]~58_combout ), + .datab(\Equal2~0_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[0]~120_combout ), + .cin(gnd), + .combout(\D[0]~64_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~64 .lut_mask = 16'hBF8F; +defparam \D[0]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N16 +cycloneive_lcell_comb \D[0]~65 ( +// Equation(s): +// \D[0]~65_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [0] & (\D[0]~64_combout ))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[0]~64_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [0]), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\D[0]~64_combout ), + .datad(\Equal2~1_combout ), + .cin(gnd), + .combout(\D[0]~65_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~65 .lut_mask = 16'hB0B3; +defparam \D[0]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N26 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\D[0]~65_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[0]~17_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[0]~65_combout & +// (((\z80_|bus_control_|db[0]~17_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) + + .dataa(\D[0]~65_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|bus_control_|db[0]~17_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N27 +dffeas \z80_|data_pins_|dout[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N30 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( +// Equation(s): +// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|bus_control_|db[0]~4_combout ), + .datad(\z80_|data_pins_|dout [0]), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'hF030; +defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N12 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( +// Equation(s): +// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~14_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~16_combout ), + .datab(\z80_|alu_control_|db[0]~14_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'h8AFF; +defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N19 +dffeas \z80_|ir_|opcode[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[0]~17_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal3~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal3~2_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pla_decode_|Equal3~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y7_N31 +dffeas \z80_|decode_state_|DFFE_instIY1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_iy_set~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instIY1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N16 +cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( +// Equation(s): +// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|decode_state_|use_ixiy~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFFF0; +defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( +// Equation(s): +// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~9_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~8_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; +defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( +// Equation(s): +// \z80_|execute_|ixy_d~13_combout = (\z80_|execute_|ixy_d~16_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|pla_decode_|Equal41~2_combout )) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ixy_d~10_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( +// Equation(s): +// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~5_combout & (((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )))) # (!\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ixy_d~12_combout ) # +// ((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ixy_d~12_combout ), + .datac(\z80_|execute_|ixy_d~13_combout ), + .datad(\z80_|execute_|ixy_d~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h4F44; +defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( +// Equation(s): +// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hAA8A; +defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( +// Equation(s): +// \z80_|execute_|ixy_d~15_combout = ((\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal49~0_combout & \z80_|execute_|ixy_d~11_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|ixy_d~14_combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|execute_|ixy_d~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'hB333; +defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~9_combout = (\z80_|execute_|ctl_flags_xy_we~8_combout & (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h0070; +defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~12_combout = ((\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_ir_we~12_combout ) # (\z80_|execute_|ctl_ir_we~11_combout )))) # (!\z80_|execute_|ctl_alu_oe~6_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hBBB3; +defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_alu_oe~11_combout ) # ((\z80_|execute_|ctl_alu_oe~12_combout ) # (!\z80_|execute_|ctl_alu_oe~8_combout ))) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~11_combout ), + .datac(\z80_|execute_|ctl_alu_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~14_combout = ((\z80_|execute_|ctl_alu_oe~13_combout ) # ((!\z80_|execute_|ctl_alu_oe~10_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~9_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~13_combout ), + .datac(\z80_|execute_|ctl_flags_alu~14_combout ), + .datad(\z80_|execute_|ctl_alu_oe~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N6 +cycloneive_lcell_comb \z80_|alu_|db[7]~9 ( +// Equation(s): +// \z80_|alu_|db[7]~9_combout = (\z80_|execute_|ctl_alu_oe~14_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (\z80_|execute_|ctl_reg_out_hi~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~9 .lut_mask = 16'hFFFC; +defparam \z80_|alu_|db[7]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N0 +cycloneive_lcell_comb \z80_|alu_|db[1]~15 ( +// Equation(s): +// \z80_|alu_|db[1]~15_combout = (\z80_|alu_control_|db[1]~27_combout & (((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[1]~27_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) + + .dataa(\z80_|alu_control_|db[1]~27_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~15 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N14 +cycloneive_lcell_comb \z80_|alu_|db[1]~16 ( +// Equation(s): +// \z80_|alu_|db[1]~16_combout = ((\z80_|alu_|db[1]~15_combout & ((\z80_|alu_|db_low[1]~20_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db_low[1]~20_combout ), + .datad(\z80_|alu_|db[1]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~16 .lut_mask = 16'hF755; +defparam \z80_|alu_|db[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( +// Equation(s): +// \z80_|alu_control_|db[1]~25_combout = (\z80_|alu_|db[1]~16_combout & (\z80_|execute_|ctl_flags_oe~2_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) # (!\z80_|alu_|db[1]~16_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((\z80_|execute_|ctl_flags_oe~2_combout & !\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) + + .dataa(\z80_|alu_|db[1]~16_combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h50DC; +defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( +// Equation(s): +// \z80_|alu_control_|db[1]~26_combout = (!\z80_|alu_control_|db[1]~25_combout & (\z80_|alu_control_|db[2]~24_combout & ((\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|alu_control_|db[1]~25_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .datad(\z80_|alu_control_|db[2]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h5100; +defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N6 +cycloneive_lcell_comb \z80_|sw1_|db_down[1]~2 ( +// Equation(s): +// \z80_|sw1_|db_down[1]~2_combout = ((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) + + .dataa(\z80_|bus_control_|db[1]~11_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datad(\z80_|execute_|ctl_sw_1d~7_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[1]~2 .lut_mask = 16'h0AFF; +defparam \z80_|sw1_|db_down[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~27 ( +// Equation(s): +// \z80_|alu_control_|db[1]~27_combout = ((\z80_|alu_control_|db[1]~26_combout & \z80_|sw1_|db_down[1]~2_combout )) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[1]~26_combout ), + .datac(\z80_|alu_control_|db[6]~13_combout ), + .datad(\z80_|sw1_|db_down[1]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~27 .lut_mask = 16'hCF0F; +defparam \z80_|alu_control_|db[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N12 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( +// Equation(s): +// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~27_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|alu_control_|db[1]~27_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[0]~4_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hBB00; +defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~38_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'hFAF0; +defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~41 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~41_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~41 .lut_mask = 16'h0005; +defparam \ula_|zx_keyboard_|keys[5][1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~42 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~42_combout = (\ula_|zx_keyboard_|keys[5][1]~41_combout & ((\ula_|zx_keyboard_|keys[5][1]~40_combout & (!\ula_|zx_keyboard_|keys[5][1]~38_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~40_combout & +// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~41_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~38_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~41_combout ), + .datac(\ula_|zx_keyboard_|keys[5][1]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~40_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~42 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[5][1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y8_N9 +dffeas \ula_|zx_keyboard_|keys[5][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][1]~42_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~30 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~30_combout = (\ula_|zx_keyboard_|keys[5][2]~29_combout & ((\ula_|zx_keyboard_|keys[4][1]~27_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][1]~27_combout & ((\ula_|zx_keyboard_|keys[4][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~29_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~29_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][1]~q ), + .datad(\ula_|zx_keyboard_|keys[4][1]~27_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~30 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y10_N9 +dffeas \ula_|zx_keyboard_|keys[4][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][1]~30_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~0_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # ((!\ula_|zx_keyboard_|keys[4][1]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [12]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|zx_keyboard_|keys[4][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hCFFF; +defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~36 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~36_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~36 .lut_mask = 16'h0010; +defparam \ula_|zx_keyboard_|keys[7][1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~3_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & +// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h444A; +defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [0] & +// (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~0 .lut_mask = 16'h0120; +defparam \ula_|zx_keyboard_|WideOr16~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~2_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~1_combout & (!\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|zx_keyboard_|WideOr16~1_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|WideOr16~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'hF202; +defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~4_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~2_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~3_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|WideOr16~3_combout ), + .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'hEA40; +defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~37 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~37_combout = (\ula_|zx_keyboard_|keys[7][1]~36_combout & ((\ula_|zx_keyboard_|WideOr16~4_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~4_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # +// (!\ula_|zx_keyboard_|keys[7][1]~36_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[7][1]~36_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~q ), + .datad(\ula_|zx_keyboard_|WideOr16~4_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~37 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[7][1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y10_N25 +dffeas \ula_|zx_keyboard_|keys[7][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][1]~37_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~33 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~33_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & +// (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~33 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[6][1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~34 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~34_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|zx_keyboard_|keys[6][1]~33_combout & \ula_|zx_keyboard_|keys[6][1]~32_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|zx_keyboard_|keys[6][1]~33_combout ), + .datad(\ula_|zx_keyboard_|keys[6][1]~32_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~34 .lut_mask = 16'hC000; +defparam \ula_|zx_keyboard_|keys[6][1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~31 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~31_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|shifted~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~31 .lut_mask = 16'hFCF0; +defparam \ula_|zx_keyboard_|keys[6][1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~35 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~35_combout = (\ula_|zx_keyboard_|keys[6][1]~34_combout & ((!\ula_|zx_keyboard_|keys[6][1]~31_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~34_combout & (\ula_|zx_keyboard_|keys[6][1]~q )) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~34_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[6][1]~q ), + .datad(\ula_|zx_keyboard_|keys[6][1]~31_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~35 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[6][1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y9_N31 +dffeas \ula_|zx_keyboard_|keys[6][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][1]~35_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N28 +cycloneive_lcell_comb \D[1]~32 ( +// Equation(s): +// \D[1]~32_combout = (\ula_|zx_keyboard_|keys[7][1]~q & (\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) # (!\ula_|zx_keyboard_|keys[7][1]~q & +// ((\z80_|address_pins_|abus[14]~22_combout ) # ((!\ula_|zx_keyboard_|keys[6][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~q ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ula_|zx_keyboard_|keys[6][1]~q ), + .datad(\z80_|address_pins_|abus[15]~21_combout ), + .cin(gnd), + .combout(\D[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~32 .lut_mask = 16'hCF45; +defparam \D[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N12 +cycloneive_lcell_comb \D[1]~33 ( +// Equation(s): +// \D[1]~33_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~32_combout & ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~q ), + .datac(\ula_|zx_keyboard_|key_row~0_combout ), + .datad(\D[1]~32_combout ), + .cin(gnd), + .combout(\D[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~33 .lut_mask = 16'hB000; +defparam \D[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~16 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~16_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~16 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[6][4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~17 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~17_combout = (\ula_|zx_keyboard_|keys[6][4]~16_combout & (\ula_|zx_keyboard_|keys[7][4]~15_combout & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~16_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~15_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~17 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[1][1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~18 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~18_combout = (\ula_|zx_keyboard_|keys[1][1]~17_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][1]~17_combout & ((\ula_|zx_keyboard_|keys[1][1]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[1][1]~17_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[1][1]~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~18 .lut_mask = 16'h7272; +defparam \ula_|zx_keyboard_|keys[1][1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y9_N9 +dffeas \ula_|zx_keyboard_|keys[1][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][1]~18_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~12 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~12_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~12 .lut_mask = 16'h0048; +defparam \ula_|zx_keyboard_|keys[0][1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~13 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~13_combout = (\ula_|zx_keyboard_|keys[0][1]~12_combout & ((\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [4] & +// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~13 .lut_mask = 16'h2400; +defparam \ula_|zx_keyboard_|keys[0][1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~10 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~10_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~10 .lut_mask = 16'hF0F3; +defparam \ula_|zx_keyboard_|keys[0][1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~13_combout & ((!\ula_|zx_keyboard_|keys[0][1]~10_combout ))) # (!\ula_|zx_keyboard_|keys[0][1]~13_combout & +// (\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~0_combout ), + .datab(\ula_|zx_keyboard_|keys[0][1]~13_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\ula_|zx_keyboard_|keys[0][1]~10_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y9_N21 +dffeas \ula_|zx_keyboard_|keys[0][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N16 +cycloneive_lcell_comb \D[1]~30 ( +// Equation(s): +// \D[1]~30_combout = (\ula_|zx_keyboard_|keys[1][1]~q & (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|keys[1][1]~q & +// (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[1][1]~q ), + .datab(\ula_|zx_keyboard_|keys[0][1]~q ), + .datac(\z80_|address_pins_|abus[9]~17_combout ), + .datad(\z80_|address_pins_|abus[8]~18_combout ), + .cin(gnd), + .combout(\D[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~30 .lut_mask = 16'hF531; +defparam \D[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~25 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~25 .lut_mask = 16'h3000; +defparam \ula_|zx_keyboard_|keys[3][1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~26 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~26_combout = (\ula_|zx_keyboard_|keys[3][1]~25_combout & ((\ula_|zx_keyboard_|keys[3][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~24_combout & ((\ula_|zx_keyboard_|keys[3][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~25_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][1]~25_combout ), + .datac(\ula_|zx_keyboard_|keys[3][1]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~24_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~26 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N31 +dffeas \ula_|zx_keyboard_|keys[3][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~23 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~23_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~22_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~22_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # +// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[2][1]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~22_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~23 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[2][1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N21 +dffeas \ula_|zx_keyboard_|keys[2][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][1]~23_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N8 +cycloneive_lcell_comb \D[1]~31 ( +// Equation(s): +// \D[1]~31_combout = (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][1]~q )))) # (!\z80_|address_pins_|abus[10]~20_combout & (!\ula_|zx_keyboard_|keys[2][1]~q & +// ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\z80_|address_pins_|abus[10]~20_combout ), + .datab(\z80_|address_pins_|abus[11]~19_combout ), + .datac(\ula_|zx_keyboard_|keys[3][1]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~q ), + .cin(gnd), + .combout(\D[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~31 .lut_mask = 16'h8ACF; +defparam \D[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N6 +cycloneive_lcell_comb \D[1]~34 ( +// Equation(s): +// \D[1]~34_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~33_combout & (\D[1]~30_combout & \D[1]~31_combout ))) + + .dataa(\D[1]~33_combout ), + .datab(\D[1]~30_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[1]~31_combout ), + .cin(gnd), + .combout(\D[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~34 .lut_mask = 16'hF8F0; +defparam \D[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N22 +cycloneive_lcell_comb \D[1]~38 ( +// Equation(s): +// \D[1]~38_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .cin(gnd), + .combout(\D[1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~38 .lut_mask = 16'hE6A2; +defparam \D[1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N4 +cycloneive_lcell_comb \D[1]~39 ( +// Equation(s): +// \D[1]~39_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[1]~38_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\D[1]~38_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\D[1]~38_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datac(\D[1]~38_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .cin(gnd), + .combout(\D[1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~39 .lut_mask = 16'hE5E0; +defparam \D[1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y2_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +// synopsys translate_on + +// Location: M9K_X22_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +// synopsys translate_on + +// Location: M9K_X22_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N24 +cycloneive_lcell_comb \D[1]~35 ( +// Equation(s): +// \D[1]~35_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout & +// (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .cin(gnd), + .combout(\D[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~35 .lut_mask = 16'hEA62; +defparam \D[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N14 +cycloneive_lcell_comb \D[1]~36 ( +// Equation(s): +// \D[1]~36_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout $ (((\D[1]~35_combout ))))) # (!\z80_|address_pins_|abus[15]~21_combout & +// (((\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout & !\D[1]~35_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\D[1]~35_combout ), + .cin(gnd), + .combout(\D[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~36 .lut_mask = 16'h44B8; +defparam \D[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N0 +cycloneive_lcell_comb \D[1]~37 ( +// Equation(s): +// \D[1]~37_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[1]~35_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[1]~36_combout & ((!\D[1]~35_combout ))) # (!\D[1]~36_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout & \D[1]~35_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datac(\D[1]~36_combout ), + .datad(\D[1]~35_combout ), + .cin(gnd), + .combout(\D[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~37 .lut_mask = 16'hAE50; +defparam \D[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N20 +cycloneive_lcell_comb \D[1]~118 ( +// Equation(s): +// \D[1]~118_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[1]~39_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[1]~37_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[1]~39_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\D[1]~39_combout ), + .datad(\D[1]~37_combout ), + .cin(gnd), + .combout(\D[1]~118_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~118 .lut_mask = 16'hF4B0; +defparam \D[1]~118 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N2 +cycloneive_lcell_comb \D[1]~40 ( +// Equation(s): +// \D[1]~40_combout = ((\Equal2~0_combout & (\D[1]~34_combout )) # (!\Equal2~0_combout & ((\D[1]~118_combout )))) # (!\Equal2~1_combout ) + + .dataa(\D[1]~34_combout ), + .datab(\Equal2~0_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[1]~118_combout ), + .cin(gnd), + .combout(\D[1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~40 .lut_mask = 16'hBF8F; +defparam \D[1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N12 +cycloneive_lcell_comb \D[1]~41 ( +// Equation(s): +// \D[1]~41_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~40_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[1]~40_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [1]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[1]~40_combout ), + .cin(gnd), + .combout(\D[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~41 .lut_mask = 16'hAF03; +defparam \D[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N28 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\D[1]~41_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[1]~11_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[1]~41_combout & +// (((\z80_|bus_control_|db[1]~11_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) + + .dataa(\D[1]~41_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|bus_control_|db[1]~11_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N29 +dffeas \z80_|data_pins_|dout[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N8 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~11 ( +// Equation(s): +// \z80_|bus_control_|db[1]~11_combout = ((\z80_|bus_control_|db[1]~10_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[1]~10_combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\z80_|bus_control_|db[0]~6_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'h8FAF; +defparam \z80_|bus_control_|db[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N9 +dffeas \z80_|ir_|opcode[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[1]~11_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_ed_set~combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|pla_decode_|Equal2~1_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y7_N29 +dffeas \z80_|decode_state_|DFFE_instED ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instED~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; +defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~8_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~8_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFAEA; +defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~8_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h00C8; +defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~6_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC888; +defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~6_combout = (\z80_|execute_|ctl_bus_db_we~4_combout ) # (((!\z80_|execute_|ctl_sw_2u~3_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) + + .dataa(\z80_|execute_|ctl_bus_db_we~4_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~2_combout ) # ((\z80_|execute_|ctl_bus_db_we~3_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # (\z80_|execute_|ctl_bus_db_we~6_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~2_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~3_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~126 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~126_combout = (\ula_|zx_keyboard_|keys[6][4]~16_combout & ((\ula_|zx_keyboard_|keys[6][4]~44_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~44_combout & ((\ula_|zx_keyboard_|keys[6][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~16_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~16_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~44_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~126_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~126 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[6][4]~126 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y9_N1 +dffeas \ula_|zx_keyboard_|keys[6][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][4]~126_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~125 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~125_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) +// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|shifted~1_combout ), + .datac(\ula_|zx_keyboard_|keys[7][4]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~125_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~125 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[7][4]~125 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N11 +dffeas \ula_|zx_keyboard_|keys[7][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][4]~125_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N16 +cycloneive_lcell_comb \D[4]~88 ( +// Equation(s): +// \D[4]~88_combout = (\ula_|zx_keyboard_|keys[6][4]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][4]~q )))) # (!\ula_|zx_keyboard_|keys[6][4]~q & +// (((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~q ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[15]~21_combout ), + .datad(\ula_|zx_keyboard_|keys[7][4]~q ), + .cin(gnd), + .combout(\D[4]~88_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~88 .lut_mask = 16'hD0DD; +defparam \D[4]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~120 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~120_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~120_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~120 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[5][4]~120 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~121 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~121_combout = (\ula_|zx_keyboard_|keys[6][4]~44_combout & ((\ula_|zx_keyboard_|keys[5][4]~120_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~120_combout & (\ula_|zx_keyboard_|keys[5][4]~q +// )))) # (!\ula_|zx_keyboard_|keys[6][4]~44_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~44_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~120_combout ), + .datac(\ula_|zx_keyboard_|keys[5][4]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~121_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~121 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][4]~121 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y9_N31 +dffeas \ula_|zx_keyboard_|keys[5][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][4]~121_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~122 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q )) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & +// \ula_|zx_keyboard_|extended~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~122_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~122 .lut_mask = 16'h300C; +defparam \ula_|zx_keyboard_|keys[4][4]~122 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~123 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~123_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[4][4]~122_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[4][4]~122_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~123_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~123 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][4]~123 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & ((\ula_|zx_keyboard_|keys[4][4]~123_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~123_combout & ((\ula_|zx_keyboard_|keys[4][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .datac(\ula_|zx_keyboard_|keys[4][4]~q ), + .datad(\ula_|zx_keyboard_|keys[4][4]~123_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y9_N9 +dffeas \ula_|zx_keyboard_|keys[4][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N28 +cycloneive_lcell_comb \D[4]~87 ( +// Equation(s): +// \D[4]~87_combout = (\z80_|address_pins_|abus[12]~24_combout & ((\z80_|address_pins_|abus[13]~23_combout ) # ((!\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\z80_|address_pins_|abus[12]~24_combout & (!\ula_|zx_keyboard_|keys[4][4]~q & +// ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\z80_|address_pins_|abus[12]~24_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[5][4]~q ), + .datad(\ula_|zx_keyboard_|keys[4][4]~q ), + .cin(gnd), + .combout(\D[4]~87_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~87 .lut_mask = 16'h8ACF; +defparam \D[4]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~115 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~115_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [5] & +// (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~115_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~115 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[2][4]~115 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~116 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~116_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[2][4]~115_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[2][4]~115_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~116_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~116 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[2][4]~116 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~117 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~117_combout = (\ula_|zx_keyboard_|keys[2][4]~116_combout & (!\ula_|zx_keyboard_|keys[2][4]~93_combout )) # (!\ula_|zx_keyboard_|keys[2][4]~116_combout & ((\ula_|zx_keyboard_|keys[2][4]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[2][4]~93_combout ), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~116_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~117_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~117 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[2][4]~117 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y8_N25 +dffeas \ula_|zx_keyboard_|keys[2][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][4]~117_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][4]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [10]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[2][4]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hDDFF; +defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~118 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~118_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~118_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~118 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|keys[3][4]~118 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~131 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~131_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[3][4]~118_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[3][4]~118_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~131_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~131 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[3][4]~131 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~119 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~119_combout = (\ula_|zx_keyboard_|keys[3][4]~127_combout & ((\ula_|zx_keyboard_|keys[3][4]~131_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~131_combout & ((\ula_|zx_keyboard_|keys[3][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~127_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][4]~127_combout ), + .datac(\ula_|zx_keyboard_|keys[3][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~131_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~119_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~119 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][4]~119 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N21 +dffeas \ula_|zx_keyboard_|keys[3][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][4]~119_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~114 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~114_combout = (\ula_|zx_keyboard_|keys[0][4]~95_combout & ((\ula_|zx_keyboard_|keys[3][1]~25_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[3][1]~25_combout & +// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .datac(\ula_|zx_keyboard_|keys[0][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~25_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~114_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~114 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[0][4]~114 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y8_N21 +dffeas \ula_|zx_keyboard_|keys[0][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][4]~114_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~113 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~113_combout = (\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~21_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][4]~21_combout & ((\ula_|zx_keyboard_|keys[1][4]~q ))))) # +// (!\ula_|zx_keyboard_|Equal0~2_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|Equal0~2_combout ), + .datac(\ula_|zx_keyboard_|keys[1][4]~q ), + .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~113_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~113 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[1][4]~113 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y8_N15 +dffeas \ula_|zx_keyboard_|keys[1][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][4]~113_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N6 +cycloneive_lcell_comb \D[4]~85 ( +// Equation(s): +// \D[4]~85_combout = (\z80_|address_pins_|abus[9]~17_combout & (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~q ))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][4]~q & +// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\z80_|address_pins_|abus[9]~17_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~q ), + .datac(\z80_|address_pins_|abus[8]~18_combout ), + .datad(\ula_|zx_keyboard_|keys[1][4]~q ), + .cin(gnd), + .combout(\D[4]~85_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~85 .lut_mask = 16'hA2F3; +defparam \D[4]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y11_N20 +cycloneive_lcell_comb \D[4]~86 ( +// Equation(s): +// \D[4]~86_combout = (\ula_|zx_keyboard_|key_row~3_combout & (\D[4]~85_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][4]~q )))) + + .dataa(\ula_|zx_keyboard_|key_row~3_combout ), + .datab(\z80_|address_pins_|abus[11]~19_combout ), + .datac(\ula_|zx_keyboard_|keys[3][4]~q ), + .datad(\D[4]~85_combout ), + .cin(gnd), + .combout(\D[4]~86_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~86 .lut_mask = 16'h8A00; +defparam \D[4]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N24 +cycloneive_lcell_comb \D[4]~89 ( +// Equation(s): +// \D[4]~89_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~88_combout & (\D[4]~87_combout & \D[4]~86_combout ))) + + .dataa(\D[4]~88_combout ), + .datab(\D[4]~87_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[4]~86_combout ), + .cin(gnd), + .combout(\D[4]~89_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~89 .lut_mask = 16'hF8F0; +defparam \D[4]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N18 +cycloneive_lcell_comb \D[4]~93 ( +// Equation(s): +// \D[4]~93_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), + .cin(gnd), + .combout(\D[4]~93_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~93 .lut_mask = 16'hF838; +defparam \D[4]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N4 +cycloneive_lcell_comb \D[4]~94 ( +// Equation(s): +// \D[4]~94_combout = (\D[4]~93_combout & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )))) # (!\D[4]~93_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datab(\D[4]~93_combout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), + .cin(gnd), + .combout(\D[4]~94_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~94 .lut_mask = 16'hCEC2; +defparam \D[4]~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y22_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X22_Y21_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y33_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N8 +cycloneive_lcell_comb \D[4]~90 ( +// Equation(s): +// \D[4]~90_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .cin(gnd), + .combout(\D[4]~90_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~90 .lut_mask = 16'hE6A2; +defparam \D[4]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y30_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N22 +cycloneive_lcell_comb \D[4]~91 ( +// Equation(s): +// \D[4]~91_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout $ ((\D[4]~90_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[4]~90_combout & +// \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\D[4]~90_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .cin(gnd), + .combout(\D[4]~91_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~91 .lut_mask = 16'h4B48; +defparam \D[4]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N28 +cycloneive_lcell_comb \D[4]~92 ( +// Equation(s): +// \D[4]~92_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[4]~90_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[4]~90_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout & !\D[4]~91_combout )) # (!\D[4]~90_combout & ((\D[4]~91_combout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[4]~90_combout ), + .datad(\D[4]~91_combout ), + .cin(gnd), + .combout(\D[4]~92_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~92 .lut_mask = 16'hC3E0; +defparam \D[4]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N8 +cycloneive_lcell_comb \D[4]~125 ( +// Equation(s): +// \D[4]~125_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\D[4]~94_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\D[4]~92_combout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (((\D[4]~94_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\D[4]~94_combout ), + .datad(\D[4]~92_combout ), + .cin(gnd), + .combout(\D[4]~125_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~125 .lut_mask = 16'hF2D0; +defparam \D[4]~125 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N30 +cycloneive_lcell_comb \D[4]~110 ( +// Equation(s): +// \D[4]~110_combout = ((\Equal2~0_combout & (\D[4]~89_combout )) # (!\Equal2~0_combout & ((\D[4]~125_combout )))) # (!\Equal2~1_combout ) + + .dataa(\D[4]~89_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[4]~125_combout ), + .datad(\Equal2~1_combout ), + .cin(gnd), + .combout(\D[4]~110_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~110 .lut_mask = 16'hB8FF; +defparam \D[4]~110 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N4 +cycloneive_lcell_comb \D[4]~111 ( +// Equation(s): +// \D[4]~111_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[4]~110_combout & \z80_|data_pins_|dout [4])))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[4]~110_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[4]~110_combout ), + .datad(\z80_|data_pins_|dout [4]), + .cin(gnd), + .combout(\D[4]~111_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~111 .lut_mask = 16'hF151; +defparam \D[4]~111 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N10 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\D[4]~111_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[4]~19_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[4]~111_combout & +// (((\z80_|bus_control_|db[4]~19_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) + + .dataa(\D[4]~111_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|bus_control_|db[4]~19_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N11 +dffeas \z80_|data_pins_|dout[4] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N18 +cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( +// Equation(s): +// \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|data_pins_|dout [4]), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[0]~4_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'hBB00; +defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N6 +cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( +// Equation(s): +// \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[4]~18_combout ), + .datac(\z80_|alu_control_|db[4]~33_combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[4]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hC4FF; +defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N23 +dffeas \z80_|ir_|opcode[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[4]~19_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal32~0_combout = (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal32~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N26 +cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( +// Equation(s): +// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal36~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal43~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal36~0_combout ), + .datab(\z80_|pla_decode_|Equal3~2_combout ), + .datac(\z80_|pla_decode_|Equal79~0_combout ), + .datad(\z80_|pla_decode_|Equal43~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|test1~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; +defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N30 +cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( +// Equation(s): +// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~53_combout & (((\z80_|interrupts_|test1~2_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|interrupts_|test1~2_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|setM1~53_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|test1~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h00FD; +defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N7 +dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|interrupts_|nmi_armed~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|interrupts_|test1~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N16 +cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( +// Equation(s): +// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hF8FC; +defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_flags_alu~19_combout ) # ((\z80_|alu_control_|db[5]~17_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_high[1]~19_combout & +// (((\z80_|alu_control_|db[5]~17_combout & \z80_|execute_|ctl_flags_bus~combout )))) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_flags_alu~19_combout ), + .datac(\z80_|alu_control_|db[5]~17_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N3 +dffeas \z80_|alu_flags_|flags_yf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_yf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_yf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N18 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( +// Equation(s): +// \z80_|alu_control_|db[5]~15_combout = (\z80_|alu_control_|out[6]~2_combout & (((\z80_|alu_flags_|flags_yf~q )) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_control_|out[6]~2_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & +// ((\z80_|alu_flags_|flags_yf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_control_|out[6]~2_combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_flags_|flags_yf~q ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hF3A2; +defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N12 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~16 ( +// Equation(s): +// \z80_|alu_control_|db[5]~16_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~15_combout & ((\z80_|reg_file_|gdfx_temp0[5]~71_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|sw1_|db_down[5]~0_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .datad(\z80_|alu_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~16 .lut_mask = 16'hA200; +defparam \z80_|alu_control_|db[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~17 ( +// Equation(s): +// \z80_|alu_control_|db[5]~17_combout = ((\z80_|alu_control_|db[5]~16_combout & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_control_|db[5]~16_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_control_|db[6]~13_combout ), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~17 .lut_mask = 16'hAF2F; +defparam \z80_|alu_control_|db[5]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y33_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; +// synopsys translate_on + +// Location: M9K_X33_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80000001C000000160F000FF70C0007F78C00000F05001007870010010000000000800000038000000F000000070000000300000006000000000000040000000F00000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000001D108000BEDA9FA9698A000000000000000000000000FFFFFFFF408102048004188297E014DA9FA9E9CA00000000000000000000000000000000FFFFFFFC800400CA972208DA9FA9CD8E00000000000000000000000000000000FFFFFFFC8004046A97A289FA9FA9CDC20000000000000000000000007FFFFFFC8000000280040E2A97A2997A9DA9CFC20000000000000000000000007FFFFFFE8000000280042EB28002BE369DA9274200000000000000000000000040810206BFFFFFFE9FE430A29D82AC3E8009E34A000000000000000000000000000000023FFFFFFC9FE4B1829FA2800E8009436A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h9FE8334E88F827C697F88D1600A80A44809E8FC2B86999C2B85B3A82B1D32A869FE8336A88F807CA97F88F96A0A80EC2838E8D42B9E98FC2B86B3B82B0D7B2D2800832E288F827CA97F88B82A0080EC683869542B939B8C2B1AB0F8290B730C2800826EA8878078297F88AD2A0280EC283E694C2B83A3BC2A3AB3E8291A316AA800826EE881807C69DE8ABD6A0280BC282209CD2BA2A3D42A2737F82918314E2800806E6981805C69D48AED6A1E80BCA82709FC2BB223DC2A07B7F8295DF11C2800886E6980805869848AAC6A1E42DC281789DC2BBAA3DC6A02B7582955F00928008A6EE98082D9618088AC8A0F40FC289E89DC2BBCA3DC2A18B7782154F02F0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y6_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'hE10F8B8C100323720BEBBDEBB81DF13FF97B252E2CB4F27BA091FBD0002D1A611E1EDBBC716D44D2912B80041C44558060CFCF15955C0D780DD5E71393920844F25E16C87C5D0308EEC52C011514BBC13AFA1028924D0C7CE738105BD47A10AA5B5C1D9D4193E4339F492B0E1A64E13AE35BE6B67AC8057BDACC155F14E906A017A1841358335450D4B26CD2A21B3D8F2211080B81EC040D7FA0B51CD48008112508062020A02490900092D2040259108806A328F4006D2AA514B42FB006ECCCCB9A360865678449975A8AE72B5C0F7BA800C1B5DC55D7D6FE2EF4EED85D00AB111821321BA426A4FE4956B43595832C271E83E060341AE5F2023FC808177383; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h1A2955372D510AC266A5445146E27000020C320FAE1557E37154040A13202DC6F40B840FB9A59B6DBB296562CB6220EFBE99D2776A202044D9101006FD221D305519198C859000004012AFF4FB060307C92BB732203BFDFEFFFFFFDFFF87FCFFFBFFEFF03FFE0FFFBFAFE0FF80787FFF7FFF83F7F87003FFBFFFFBFFFBFF0FFC0FF81FFF7FFBFFDFFFBFFFE1FF0086F3141AAB6005810A0621595A893F9D85983B9254954341968BAC8C141C90938C05B2C9CD267E11650407375FEDD6A2FEB346AAF6CFDC0791AA97B741995A3B3981E06D1A44D3711955197BB9910FCA20744915C84D6C24BAF53929814CA8A4697E8F4201145AE7415DC122A5F010436107; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h02E84F969E3C800AC610D276182020227809001A50DDDBA3487BB6AE802BA06509312DA0E620656EAF24D57C08FFB14D289613DC32083803B84DC6415FD5EDC000300A8D128FA20030ACCBAFA237B7024504D36A4BA26081137F059E78991154FE2AC2A884A8CC7FBBB21C851CC92B12E15593C0C020FFEE066558590E882D5B67459F1A8C3240FE4E6A8D028C0C088FCF471D400A19B38211004DD122212288B111114514CB11840E04828849C621392041163C00808C67223422F00110201DD18FCFFFF3FFE7F9FFFFFFF82C0B422D214711E08904524A069491774E663F48F665955B4E2C63DAC0078652D10120900298F7EE380092442AFD400BEC43C003; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N2 +cycloneive_lcell_comb \Mux2~0 ( +// Equation(s): +// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~22_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .cin(gnd), + .combout(\Mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux2~0 .lut_mask = 16'hB9A8; +defparam \Mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N24 +cycloneive_lcell_comb \Mux2~1 ( +// Equation(s): +// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datad(\Mux2~0_combout ), + .cin(gnd), + .combout(\Mux2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Mux2~1 .lut_mask = 16'hBBC0; +defparam \Mux2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y2_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # +// (\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout & +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 .lut_mask = 16'hCEC2; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 .lut_mask = 16'hBCB0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N30 +cycloneive_lcell_comb \D[5]~112 ( +// Equation(s): +// \D[5]~112_combout = ((\z80_|address_pins_|abus[15]~21_combout & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ))) # (!\z80_|address_pins_|abus[15]~21_combout & (\Mux2~1_combout ))) # (!\D[5]~97_combout ) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\D[5]~97_combout ), + .datac(\Mux2~1_combout ), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .cin(gnd), + .combout(\D[5]~112_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~112 .lut_mask = 16'hFB73; +defparam \D[5]~112 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N8 +cycloneive_lcell_comb \D[5]~113 ( +// Equation(s): +// \D[5]~113_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[5]~112_combout & \z80_|data_pins_|dout [5])))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[5]~112_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[5]~112_combout ), + .datad(\z80_|data_pins_|dout [5]), + .cin(gnd), + .combout(\D[5]~113_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~113 .lut_mask = 16'hF151; +defparam \D[5]~113 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N24 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|bus_control_|db[5]~15_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[5]~113_combout )))) # (!\z80_|bus_control_|db[5]~15_combout & +// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[5]~113_combout )))) + + .dataa(\z80_|bus_control_|db[5]~15_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\D[5]~113_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N25 +dffeas \z80_|data_pins_|dout[5] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N20 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( +// Equation(s): +// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(gnd), + .datab(\z80_|data_pins_|dout [5]), + .datac(\z80_|bus_control_|db[0]~4_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hC0F0; +defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( +// Equation(s): +// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~17_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|alu_control_|db[5]~17_combout ), + .datab(\z80_|bus_control_|db[0]~6_combout ), + .datac(\z80_|bus_control_|db[5]~14_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hB3F3; +defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N25 +dffeas \z80_|ir_|opcode[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[5]~15_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~11_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~46 ( +// Equation(s): +// \z80_|execute_|setM1~46_combout = (!\z80_|execute_|ctl_mRead~11_combout & (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_iorw~10_combout & \z80_|execute_|ctl_mRead~17_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|ctl_iorw~11_combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|execute_|ctl_mRead~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~46 .lut_mask = 16'h0100; +defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~40 ( +// Equation(s): +// \z80_|execute_|setM1~40_combout = (!\z80_|execute_|ctl_mWrite~7_combout & \z80_|execute_|setM1~39_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|setM1~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~40 .lut_mask = 16'h0F00; +defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|nextM~5 ( +// Equation(s): +// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|setM1~40_combout )) # (!\z80_|execute_|setM1~46_combout ))) + + .dataa(\z80_|execute_|setM1~46_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|setM1~40_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~5 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|nextM~6 ( +// Equation(s): +// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|nextM~3_combout ) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|nextM~3_combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|execute_|ixy_d~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~6 .lut_mask = 16'hB3FF; +defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|nextM~7 ( +// Equation(s): +// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~8_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|nextM~6_combout ), + .datac(\z80_|execute_|ixy_d~8_combout ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~7 .lut_mask = 16'hC8FF; +defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|nextM~9 ( +// Equation(s): +// \z80_|execute_|nextM~9_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~9 .lut_mask = 16'hE000; +defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|nextM~10 ( +// Equation(s): +// \z80_|execute_|nextM~10_combout = (\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ctl_mRead~34_combout ))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|nextM~9_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~8 ( +// Equation(s): +// \z80_|execute_|nextM~8_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ixy_d~8_combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ixy_d~8_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~8 .lut_mask = 16'h2F22; +defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|nextM~12 ( +// Equation(s): +// \z80_|execute_|nextM~12_combout = (\z80_|execute_|ctl_alu_op_low~21_combout ) # (((\z80_|execute_|nextM~10_combout ) # (\z80_|execute_|nextM~8_combout )) # (!\z80_|execute_|nextM~11_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~21_combout ), + .datab(\z80_|execute_|nextM~11_combout ), + .datac(\z80_|execute_|nextM~10_combout ), + .datad(\z80_|execute_|nextM~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|nextM~15 ( +// Equation(s): +// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|fMRead~12_combout )))) + + .dataa(\z80_|execute_|fMRead~12_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~15 .lut_mask = 16'hC040; +defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|nextM~13 ( +// Equation(s): +// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~7_combout ) # ((\z80_|execute_|nextM~12_combout ) # (\z80_|execute_|nextM~15_combout )) + + .dataa(\z80_|execute_|nextM~7_combout ), + .datab(\z80_|execute_|nextM~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~14 ( +// Equation(s): +// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~5_combout ) # ((\z80_|execute_|nextM~13_combout ) # ((!\z80_|execute_|ctl_mWrite~14_combout ) # (!\z80_|execute_|ctl_mRead~28_combout ))) + + .dataa(\z80_|execute_|nextM~5_combout ), + .datab(\z80_|execute_|nextM~13_combout ), + .datac(\z80_|execute_|ctl_mRead~28_combout ), + .datad(\z80_|execute_|ctl_mWrite~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~14 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N22 +cycloneive_lcell_comb \z80_|sequencer_|ena_M ( +// Equation(s): +// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|ena_M~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; +defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N23 +dffeas \z80_|sequencer_|DFFE_T1_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|ena_M~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T1_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N26 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0050; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N27 +dffeas \z80_|sequencer_|DFFE_T2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T2_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N30 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N31 +dffeas \z80_|sequencer_|DFFE_T3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T3_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N20 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N21 +dffeas \z80_|sequencer_|DFFE_T4_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T4_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~9_combout & (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|execute_|ctl_mWrite~9_combout & (((!\z80_|execute_|ctl_mWrite~5_combout ) # +// (!\z80_|execute_|ctl_ir_we~12_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0757; +defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~54 ( +// Equation(s): +// \z80_|execute_|setM1~54_combout = ((\z80_|execute_|ctl_iorw~11_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_iorw~11_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~54 .lut_mask = 16'hD555; +defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~25 ( +// Equation(s): +// \z80_|execute_|setM1~25_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_mRead~10_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~25 .lut_mask = 16'h2F22; +defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~26 ( +// Equation(s): +// \z80_|execute_|setM1~26_combout = (\z80_|execute_|ctl_mRead~11_combout ) # (((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~26 .lut_mask = 16'hDCFF; +defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~27 ( +// Equation(s): +// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~26_combout ) # (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|execute_|setM1~26_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~27 .lut_mask = 16'hECFF; +defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~22 ( +// Equation(s): +// \z80_|execute_|setM1~22_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~22 .lut_mask = 16'hFF04; +defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~55 ( +// Equation(s): +// \z80_|execute_|setM1~55_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|execute_|setM1~22_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|setM1~22_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~55 .lut_mask = 16'hF080; +defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~23 ( +// Equation(s): +// \z80_|execute_|setM1~23_combout = (\z80_|execute_|fMWrite~0_combout & (!\z80_|execute_|ctl_mRead~8_combout & (\z80_|execute_|fMWrite~6_combout & !\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|fMWrite~0_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|fMWrite~6_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~23 .lut_mask = 16'h0020; +defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~24 ( +// Equation(s): +// \z80_|execute_|setM1~24_combout = (\z80_|execute_|setM1~55_combout & (((\z80_|execute_|ctl_reg_in_hi~2_combout & !\z80_|execute_|setM1~23_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|setM1~55_combout & +// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|execute_|setM1~23_combout )))) + + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|setM1~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~24 .lut_mask = 16'h0ACE; +defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~28 ( +// Equation(s): +// \z80_|execute_|setM1~28_combout = (\z80_|execute_|setM1~25_combout ) # ((\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|setM1~27_combout & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|setM1~25_combout ), + .datab(\z80_|execute_|setM1~27_combout ), + .datac(\z80_|execute_|setM1~24_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~11 ( +// Equation(s): +// \z80_|execute_|setM1~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~11 .lut_mask = 16'hFF04; +defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~33 ( +// Equation(s): +// \z80_|execute_|setM1~33_combout = (\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mRead~2_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|setM1~11_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|setM1~11_combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~29 ( +// Equation(s): +// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~5_combout ) # (((\z80_|execute_|ctl_mRead~13_combout ) # (\z80_|execute_|ctl_mRead~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~29 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~31 ( +// Equation(s): +// \z80_|execute_|setM1~31_combout = (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~30_combout )) # (!\z80_|execute_|setM1~56_combout ) + + .dataa(\z80_|execute_|setM1~56_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|setM1~29_combout ), + .datad(\z80_|execute_|setM1~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~31 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~32 ( +// Equation(s): +// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~16_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & +// (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~32 .lut_mask = 16'hECA0; +defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~34 ( +// Equation(s): +// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~32_combout ) # ((\z80_|execute_|setM1~33_combout & \z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|setM1~33_combout ), + .datab(\z80_|execute_|setM1~31_combout ), + .datac(\z80_|execute_|setM1~32_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~20 ( +// Equation(s): +// \z80_|execute_|setM1~20_combout = (\z80_|execute_|ctl_mRead~9_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_flags_bus~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~20 .lut_mask = 16'h20F0; +defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~21 ( +// Equation(s): +// \z80_|execute_|setM1~21_combout = (\z80_|execute_|setM1~20_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & (\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|ixy_d~8_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|setM1~20_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~21 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~35 ( +// Equation(s): +// \z80_|execute_|setM1~35_combout = (\z80_|execute_|setM1~54_combout ) # ((\z80_|execute_|setM1~28_combout ) # ((\z80_|execute_|setM1~34_combout ) # (\z80_|execute_|setM1~21_combout ))) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(\z80_|execute_|setM1~28_combout ), + .datac(\z80_|execute_|setM1~34_combout ), + .datad(\z80_|execute_|setM1~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~35 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~15 ( +// Equation(s): +// \z80_|execute_|setM1~15_combout = (\z80_|pla_decode_|Equal21~2_combout & (!\z80_|pla_decode_|Equal32~0_combout & ((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )))) # (!\z80_|pla_decode_|Equal21~2_combout & +// (((!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~2_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~15 .lut_mask = 16'h153F; +defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~14 ( +// Equation(s): +// \z80_|execute_|setM1~14_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|execute_|ctl_alu_oe~3_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal77~1_combout ), + .datac(\z80_|pla_decode_|Equal1~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~14 .lut_mask = 16'h0003; +defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~16 ( +// Equation(s): +// \z80_|execute_|setM1~16_combout = (\z80_|interrupts_|test1~2_combout & (\z80_|execute_|setM1~15_combout & (\z80_|execute_|setM1~14_combout & !\z80_|pla_decode_|Equal2~2_combout ))) + + .dataa(\z80_|interrupts_|test1~2_combout ), + .datab(\z80_|execute_|setM1~15_combout ), + .datac(\z80_|execute_|setM1~14_combout ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0080; +defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~10 ( +// Equation(s): +// \z80_|execute_|setM1~10_combout = (\z80_|pla_decode_|Equal6~1_combout ) # (((\z80_|execute_|ctl_mWrite~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|fMWrite~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|fMWrite~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~12 ( +// Equation(s): +// \z80_|execute_|setM1~12_combout = ((\z80_|execute_|setM1~10_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout & \z80_|execute_|setM1~11_combout ))) # (!\z80_|execute_|nextM~2_combout ) + + .dataa(\z80_|execute_|nextM~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|setM1~11_combout ), + .datad(\z80_|execute_|setM1~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~12 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~8 ( +// Equation(s): +// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_al_we~13_combout & (((\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & +// \z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~8 .lut_mask = 16'hF444; +defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~9 ( +// Equation(s): +// \z80_|execute_|setM1~9_combout = ((\z80_|execute_|setM1~8_combout & \z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|execute_|ctl_flags_xy_we~17_combout ) + + .dataa(\z80_|execute_|setM1~8_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~9 .lut_mask = 16'hA0FF; +defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~13 ( +// Equation(s): +// \z80_|execute_|setM1~13_combout = ((\z80_|execute_|setM1~9_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|setM1~12_combout ))) # (!\z80_|reg_control_|reg_sel_pc~3_combout ) + + .dataa(\z80_|reg_control_|reg_sel_pc~3_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|setM1~12_combout ), + .datad(\z80_|execute_|setM1~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~13 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~18 ( +// Equation(s): +// \z80_|execute_|setM1~18_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|execute_|setM1~17_combout & (\z80_|execute_|ctl_alu_op_low~38_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|setM1~17_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~18 .lut_mask = 16'h0040; +defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~19 ( +// Equation(s): +// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~13_combout ) # (((!\z80_|execute_|setM1~16_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|setM1~18_combout )) + + .dataa(\z80_|execute_|setM1~16_combout ), + .datab(\z80_|execute_|setM1~13_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|setM1~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~19 .lut_mask = 16'hDCFF; +defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~43 ( +// Equation(s): +// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|pla_decode_|Equal37~0_combout & !\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0004; +defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~42 ( +// Equation(s): +// \z80_|execute_|setM1~42_combout = (!\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout )) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|setM1~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0101; +defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~44 ( +// Equation(s): +// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~42_combout & !\z80_|pla_decode_|Equal48~0_combout ))) + + .dataa(\z80_|execute_|setM1~43_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|setM1~42_combout ), + .datad(\z80_|pla_decode_|Equal48~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~44 .lut_mask = 16'h0020; +defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~45 ( +// Equation(s): +// \z80_|execute_|setM1~45_combout = (\z80_|execute_|setM1~41_combout & (\z80_|execute_|setM1~44_combout & ((!\z80_|pla_decode_|Equal1~4_combout ) # (!\z80_|pla_decode_|Equal2~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal2~1_combout ), + .datab(\z80_|execute_|setM1~41_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|execute_|setM1~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~45 .lut_mask = 16'h4C00; +defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~51 ( +// Equation(s): +// \z80_|execute_|setM1~51_combout = (\z80_|execute_|setM1~45_combout & (\z80_|execute_|setM1~47_combout & (\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~16_combout ))) + + .dataa(\z80_|execute_|setM1~45_combout ), + .datab(\z80_|execute_|setM1~47_combout ), + .datac(\z80_|execute_|setM1~50_combout ), + .datad(\z80_|execute_|setM1~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~51 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N18 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N19 +dffeas \z80_|sequencer_|T6 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|T6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|T6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~52 ( +// Equation(s): +// \z80_|execute_|setM1~52_combout = (\z80_|execute_|setM1~51_combout & ((\z80_|execute_|setM1~40_combout ) # ((\z80_|sequencer_|T6~q & !\z80_|execute_|setM1~41_combout )))) # (!\z80_|execute_|setM1~51_combout & (\z80_|sequencer_|T6~q & +// (!\z80_|execute_|setM1~41_combout ))) + + .dataa(\z80_|execute_|setM1~51_combout ), + .datab(\z80_|sequencer_|T6~q ), + .datac(\z80_|execute_|setM1~41_combout ), + .datad(\z80_|execute_|setM1~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~52 .lut_mask = 16'hAE0C; +defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~53 ( +// Equation(s): +// \z80_|execute_|setM1~53_combout = (!\z80_|execute_|setM1~35_combout & (!\z80_|execute_|setM1~19_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~52_combout )))) + + .dataa(\z80_|execute_|setM1~35_combout ), + .datab(\z80_|execute_|setM1~19_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|setM1~52_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~53 .lut_mask = 16'h1011; +defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N14 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hCCC0; +defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N15 +dffeas \z80_|sequencer_|DFFE_M1_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M1_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N28 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h44C0; +defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N29 +dffeas \z80_|sequencer_|DFFE_M2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M2_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h0F0C; +defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N28 cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( // Equation(s): -// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_apin_mux~1_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) +// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_apin_mux~1_combout ), - .datac(\z80_|execute_|ctl_inc_dec~6_combout ), - .datad(gnd), + .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_dec~6_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_apin_mux~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'h8F8F; +defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'h88FF; defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y16_N18 +// Location: LCCOMB_X28_Y16_N20 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[0]~0 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [0]))) @@ -53232,7 +53700,7 @@ defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hDD88; defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y16_N19 +// Location: FF_X28_Y16_N21 dffeas \z80_|address_pins_|DFFE_apin_latch[0] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), @@ -53251,228 +53719,332 @@ defparam \z80_|address_pins_|DFFE_apin_latch[0] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N12 -cycloneive_lcell_comb \D[0]~59 ( +// Location: LCCOMB_X24_Y15_N30 +cycloneive_lcell_comb \D[0]~66 ( // Equation(s): -// \D[0]~59_combout = (\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout ))) - - .dataa(\Equal2~0_combout ), - .datab(\D[0]~51_combout ), - .datac(\D[0]~106_combout ), - .datad(gnd), - .cin(gnd), - .combout(\D[0]~59_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~59 .lut_mask = 16'hD8D8; -defparam \D[0]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N8 -cycloneive_lcell_comb \D[0]~60 ( -// Equation(s): -// \D[0]~60_combout = (\Equal2~1_combout & (\D[0]~59_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [0]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [0]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[0]~59_combout ), - .cin(gnd), - .combout(\D[0]~60_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~60 .lut_mask = 16'hCF45; -defparam \D[0]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y18_N20 -cycloneive_lcell_comb \D[1]~61 ( -// Equation(s): -// \D[1]~61_combout = (\Equal2~0_combout & (\D[1]~32_combout )) # (!\Equal2~0_combout & ((\D[1]~103_combout ))) - - .dataa(\Equal2~0_combout ), - .datab(gnd), - .datac(\D[1]~32_combout ), - .datad(\D[1]~103_combout ), - .cin(gnd), - .combout(\D[1]~61_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~61 .lut_mask = 16'hF5A0; -defparam \D[1]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y18_N22 -cycloneive_lcell_comb \D[1]~62 ( -// Equation(s): -// \D[1]~62_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~61_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~61_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [1]), - .datad(\D[1]~61_combout ), - .cin(gnd), - .combout(\D[1]~62_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~62 .lut_mask = 16'hF531; -defparam \D[1]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N12 -cycloneive_lcell_comb \D[2]~63 ( -// Equation(s): -// \D[2]~63_combout = (\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout ))) - - .dataa(\Equal2~0_combout ), - .datab(gnd), - .datac(\D[2]~104_combout ), - .datad(\D[2]~105_combout ), - .cin(gnd), - .combout(\D[2]~63_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~63 .lut_mask = 16'hF5A0; -defparam \D[2]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N26 -cycloneive_lcell_comb \D[2]~64 ( -// Equation(s): -// \D[2]~64_combout = (\z80_|data_pins_|dout [2] & (((\D[2]~63_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [2] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[2]~63_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [2]), - .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[2]~63_combout ), - .cin(gnd), - .combout(\D[2]~64_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~64 .lut_mask = 16'hAF23; -defparam \D[2]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N2 -cycloneive_lcell_comb \D[3]~75 ( -// Equation(s): -// \D[3]~75_combout = (\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout ))) - - .dataa(\D[3]~69_combout ), - .datab(gnd), - .datac(\Equal2~0_combout ), - .datad(\D[3]~108_combout ), - .cin(gnd), - .combout(\D[3]~75_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~75 .lut_mask = 16'hAFA0; -defparam \D[3]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N20 -cycloneive_lcell_comb \D[3]~76 ( -// Equation(s): -// \D[3]~76_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~75_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[3]~75_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [3]), - .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[3]~75_combout ), - .cin(gnd), - .combout(\D[3]~76_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~76 .lut_mask = 16'hAF23; -defparam \D[3]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N24 -cycloneive_lcell_comb \D[4]~82 ( -// Equation(s): -// \D[4]~82_combout = (\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout ))) - - .dataa(\Equal2~0_combout ), - .datab(\D[4]~81_combout ), - .datac(gnd), - .datad(\D[4]~109_combout ), - .cin(gnd), - .combout(\D[4]~82_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~82 .lut_mask = 16'hDD88; -defparam \D[4]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N26 -cycloneive_lcell_comb \D[4]~83 ( -// Equation(s): -// \D[4]~83_combout = (\Equal2~1_combout & (\D[4]~82_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [4]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [4]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[4]~82_combout ), - .cin(gnd), - .combout(\D[4]~83_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~83 .lut_mask = 16'hCF45; -defparam \D[4]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N24 -cycloneive_lcell_comb \D[6]~92 ( -// Equation(s): -// \D[6]~92_combout = (\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout )) +// \D[0]~66_combout = (\Equal2~0_combout & (\D[0]~58_combout )) # (!\Equal2~0_combout & ((\D[0]~120_combout ))) .dataa(gnd), .datab(\Equal2~0_combout ), - .datac(\D[6]~111_combout ), - .datad(\D[6]~86_combout ), + .datac(\D[0]~58_combout ), + .datad(\D[0]~120_combout ), .cin(gnd), - .combout(\D[6]~92_combout ), + .combout(\D[0]~66_combout ), .cout()); // synopsys translate_off -defparam \D[6]~92 .lut_mask = 16'hFC30; -defparam \D[6]~92 .sum_lutc_input = "datac"; +defparam \D[0]~66 .lut_mask = 16'hF3C0; +defparam \D[0]~66 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N10 -cycloneive_lcell_comb \D[6]~93 ( +// Location: LCCOMB_X25_Y15_N18 +cycloneive_lcell_comb \D[0]~67 ( // Equation(s): -// \D[6]~93_combout = (\Equal2~1_combout & (\D[6]~92_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [6]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) +// \D[0]~67_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [0] & ((\D[0]~66_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[0]~66_combout ) # (!\Equal2~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[6]~92_combout ), + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|data_pins_|dout [0]), + .datac(\Equal2~1_combout ), + .datad(\D[0]~66_combout ), .cin(gnd), - .combout(\D[6]~93_combout ), + .combout(\D[0]~67_combout ), .cout()); // synopsys translate_off -defparam \D[6]~93 .lut_mask = 16'hCF45; -defparam \D[6]~93 .sum_lutc_input = "datac"; +defparam \D[0]~67 .lut_mask = 16'hDD0D; +defparam \D[0]~67 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N0 -cycloneive_lcell_comb \z80_|nM1_int~3 ( +// Location: LCCOMB_X25_Y17_N24 +cycloneive_lcell_comb \D[0]~121 ( // Equation(s): -// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) +// \D[0]~121_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout ) # ((\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .cin(gnd), + .combout(\D[0]~121_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~121 .lut_mask = 16'hFF20; +defparam \D[0]~121 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N16 +cycloneive_lcell_comb \D[1]~68 ( +// Equation(s): +// \D[1]~68_combout = (\Equal2~0_combout & (\D[1]~34_combout )) # (!\Equal2~0_combout & ((\D[1]~118_combout ))) .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|setM1~52_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[1]~34_combout ), + .datad(\D[1]~118_combout ), + .cin(gnd), + .combout(\D[1]~68_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~68 .lut_mask = 16'hF3C0; +defparam \D[1]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N14 +cycloneive_lcell_comb \D[1]~69 ( +// Equation(s): +// \D[1]~69_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~68_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[1]~68_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\Equal2~1_combout ), + .datad(\D[1]~68_combout ), + .cin(gnd), + .combout(\D[1]~69_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~69 .lut_mask = 16'hDD0D; +defparam \D[1]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N16 +cycloneive_lcell_comb \D[2]~70 ( +// Equation(s): +// \D[2]~70_combout = (\Equal2~0_combout & (\D[2]~46_combout )) # (!\Equal2~0_combout & ((\D[2]~119_combout ))) + + .dataa(gnd), + .datab(\D[2]~46_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[2]~119_combout ), + .cin(gnd), + .combout(\D[2]~70_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~70 .lut_mask = 16'hCFC0; +defparam \D[2]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N14 +cycloneive_lcell_comb \D[2]~71 ( +// Equation(s): +// \D[2]~71_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [2] & ((\D[2]~70_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[2]~70_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\Equal2~1_combout ), + .datac(\z80_|data_pins_|dout [2]), + .datad(\D[2]~70_combout ), + .cin(gnd), + .combout(\D[2]~71_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~71 .lut_mask = 16'hF531; +defparam \D[2]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N24 +cycloneive_lcell_comb \D[3]~83 ( +// Equation(s): +// \D[3]~83_combout = (\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(gnd), + .datac(\z80_|data_pins_|dout [3]), + .datad(gnd), + .cin(gnd), + .combout(\D[3]~83_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~83 .lut_mask = 16'hF5F5; +defparam \D[3]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N6 +cycloneive_lcell_comb \D[3]~84 ( +// Equation(s): +// \D[3]~84_combout = (\D[3]~83_combout & ((\D[3]~122_combout ) # ((\D[3]~82_combout ) # (!\Equal2~1_combout )))) + + .dataa(\D[3]~122_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[3]~82_combout ), + .datad(\D[3]~83_combout ), + .cin(gnd), + .combout(\D[3]~84_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~84 .lut_mask = 16'hFB00; +defparam \D[3]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N20 +cycloneive_lcell_comb \D[4]~95 ( +// Equation(s): +// \D[4]~95_combout = (\Equal2~0_combout & (\D[4]~89_combout )) # (!\Equal2~0_combout & ((\D[4]~125_combout ))) + + .dataa(\D[4]~89_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[4]~125_combout ), + .datad(gnd), + .cin(gnd), + .combout(\D[4]~95_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~95 .lut_mask = 16'hB8B8; +defparam \D[4]~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N6 +cycloneive_lcell_comb \D[4]~96 ( +// Equation(s): +// \D[4]~96_combout = (\z80_|data_pins_|dout [4] & (((\D[4]~95_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [4] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[4]~95_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [4]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[4]~95_combout ), + .cin(gnd), + .combout(\D[4]~96_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~96 .lut_mask = 16'hAF23; +defparam \D[4]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N18 +cycloneive_lcell_comb \D[5]~126 ( +// Equation(s): +// \D[5]~126_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\Mux2~1_combout )) # +// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ))))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\Mux2~1_combout ), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .cin(gnd), + .combout(\D[5]~126_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~126 .lut_mask = 16'hFB40; +defparam \D[5]~126 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N0 +cycloneive_lcell_comb \D[5]~98 ( +// Equation(s): +// \D[5]~98_combout = (\z80_|data_pins_|dout [5] & (((\D[5]~126_combout )) # (!\D[5]~97_combout ))) # (!\z80_|data_pins_|dout [5] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[5]~126_combout ) # (!\D[5]~97_combout )))) + + .dataa(\z80_|data_pins_|dout [5]), + .datab(\D[5]~97_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[5]~126_combout ), + .cin(gnd), + .combout(\D[5]~98_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~98 .lut_mask = 16'hAF23; +defparam \D[5]~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N18 +cycloneive_lcell_comb \D[6]~105 ( +// Equation(s): +// \D[6]~105_combout = (\Equal2~0_combout & ((\D[6]~99_combout ))) # (!\Equal2~0_combout & (\D[6]~127_combout )) + + .dataa(gnd), + .datab(\Equal2~0_combout ), + .datac(\D[6]~127_combout ), + .datad(\D[6]~99_combout ), + .cin(gnd), + .combout(\D[6]~105_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~105 .lut_mask = 16'hFC30; +defparam \D[6]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N0 +cycloneive_lcell_comb \D[6]~106 ( +// Equation(s): +// \D[6]~106_combout = (\z80_|data_pins_|dout [6] & (((\D[6]~105_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [6] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[6]~105_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [6]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[6]~105_combout ), + .cin(gnd), + .combout(\D[6]~106_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~106 .lut_mask = 16'hAF23; +defparam \D[6]~106 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N10 +cycloneive_lcell_comb \D[7]~128 ( +// Equation(s): +// \D[7]~128_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux0~1_combout ))))) # +// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .datad(\Mux0~1_combout ), + .cin(gnd), + .combout(\D[7]~128_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~128 .lut_mask = 16'hF2D0; +defparam \D[7]~128 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N16 +cycloneive_lcell_comb \D[7]~107 ( +// Equation(s): +// \D[7]~107_combout = (\z80_|data_pins_|dout [7] & (((\D[7]~128_combout ) # (!\D[5]~97_combout )))) # (!\z80_|data_pins_|dout [7] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[7]~128_combout ) # (!\D[5]~97_combout )))) + + .dataa(\z80_|data_pins_|dout [7]), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\D[5]~97_combout ), + .datad(\D[7]~128_combout ), + .cin(gnd), + .combout(\D[7]~107_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~107 .lut_mask = 16'hBB0B; +defparam \D[7]~107 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N6 +cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nIORQ_out~0_combout = (!\z80_|memory_ifc_|DFFE_intr_ff3~q & (!\z80_|memory_ifc_|iorq~0_combout & !\z80_|memory_ifc_|wait_iorqinta~q )) + + .dataa(gnd), + .datab(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .datac(\z80_|memory_ifc_|iorq~0_combout ), + .datad(\z80_|memory_ifc_|wait_iorqinta~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'h0003; +defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N12 +cycloneive_lcell_comb \z80_|nM1_int~3 ( +// Equation(s): +// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), .combout(\z80_|nM1_int~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|nM1_int~3 .lut_mask = 16'hFC00; +defparam \z80_|nM1_int~3 .lut_mask = 16'hCCC0; defparam \z80_|nM1_int~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N1 +// Location: FF_X40_Y13_N13 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|nM1_int~3_combout ), @@ -53491,7 +54063,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N30 +// Location: LCCOMB_X40_Y11_N4 cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder ( // Equation(s): // \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -53508,7 +54080,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N31 +// Location: FF_X40_Y11_N5 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ), @@ -53527,7 +54099,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .power_up = "low"; // synopsys translate_on -// Location: FF_X43_Y17_N25 +// Location: FF_X40_Y11_N27 dffeas \z80_|memory_ifc_|DFFE_mreq_ff2 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -53546,31 +54118,31 @@ defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N24 +// Location: LCCOMB_X40_Y11_N26 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~0 ( // Equation(s): // \z80_|memory_ifc_|nMREQ_out~0_combout = (\z80_|memory_ifc_|wait_mwr~q ) # ((\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q & !\z80_|memory_ifc_|DFFE_mreq_ff2~q ))) - .dataa(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), - .datab(\z80_|memory_ifc_|wait_mwr~q ), + .dataa(\z80_|memory_ifc_|wait_mwr~q ), + .datab(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), .datac(\z80_|memory_ifc_|DFFE_mreq_ff2~q ), .datad(\z80_|memory_ifc_|mwr_wr~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFCE; +defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFAE; defparam \z80_|memory_ifc_|nMREQ_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N2 +// Location: LCCOMB_X40_Y11_N2 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~1 ( // Equation(s): -// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nMREQ_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|nRD_out~0_combout ))) +// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nMREQ_out~0_combout & !\z80_|memory_ifc_|nRD_out~0_combout ))) - .dataa(\z80_|memory_ifc_|wait_mrd~q ), - .datab(\z80_|memory_ifc_|nMREQ_out~0_combout ), - .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .dataa(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .datab(\z80_|memory_ifc_|wait_mrd~q ), + .datac(\z80_|memory_ifc_|nMREQ_out~0_combout ), .datad(\z80_|memory_ifc_|nRD_out~0_combout ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~1_combout ), @@ -53593,24 +54165,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( -// Equation(s): -// \ula_|i2c_loader_|state.Idle~feeder_combout = VCC - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Idle~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; -defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y24_N0 +// Location: LCCOMB_X1_Y24_N18 cycloneive_lcell_comb \ula_|i2c_loader_|divider[0]~15 ( // Equation(s): // \ula_|i2c_loader_|divider[0]~15_combout = !\ula_|i2c_loader_|divider [0] @@ -53627,7 +54182,7 @@ defparam \ula_|i2c_loader_|divider[0]~15 .lut_mask = 16'h0F0F; defparam \ula_|i2c_loader_|divider[0]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X4_Y24_N1 +// Location: FF_X1_Y24_N19 dffeas \ula_|i2c_loader_|divider[0] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[0]~15_combout ), @@ -53646,14 +54201,14 @@ defparam \ula_|i2c_loader_|divider[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N10 +// Location: LCCOMB_X1_Y24_N8 cycloneive_lcell_comb \ula_|i2c_loader_|divider[1]~5 ( // Equation(s): -// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] $ (VCC))) # (!\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] & VCC)) -// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [1] & \ula_|i2c_loader_|divider [0])) +// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] $ (VCC))) # (!\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] & VCC)) +// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [0] & \ula_|i2c_loader_|divider [1])) - .dataa(\ula_|i2c_loader_|divider [1]), - .datab(\ula_|i2c_loader_|divider [0]), + .dataa(\ula_|i2c_loader_|divider [0]), + .datab(\ula_|i2c_loader_|divider [1]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -53664,7 +54219,7 @@ defparam \ula_|i2c_loader_|divider[1]~5 .lut_mask = 16'h6688; defparam \ula_|i2c_loader_|divider[1]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X4_Y24_N11 +// Location: FF_X1_Y24_N9 dffeas \ula_|i2c_loader_|divider[1] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[1]~5_combout ), @@ -53683,7 +54238,7 @@ defparam \ula_|i2c_loader_|divider[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N12 +// Location: LCCOMB_X1_Y24_N10 cycloneive_lcell_comb \ula_|i2c_loader_|divider[2]~7 ( // Equation(s): // \ula_|i2c_loader_|divider[2]~7_combout = (\ula_|i2c_loader_|divider [2] & (!\ula_|i2c_loader_|divider[1]~6 )) # (!\ula_|i2c_loader_|divider [2] & ((\ula_|i2c_loader_|divider[1]~6 ) # (GND))) @@ -53701,7 +54256,7 @@ defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|divider[2]~7 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N13 +// Location: FF_X1_Y24_N11 dffeas \ula_|i2c_loader_|divider[2] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[2]~7_combout ), @@ -53720,25 +54275,25 @@ defparam \ula_|i2c_loader_|divider[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N14 +// Location: LCCOMB_X1_Y24_N12 cycloneive_lcell_comb \ula_|i2c_loader_|divider[3]~9 ( // Equation(s): // \ula_|i2c_loader_|divider[3]~9_combout = (\ula_|i2c_loader_|divider [3] & (\ula_|i2c_loader_|divider[2]~8 $ (GND))) # (!\ula_|i2c_loader_|divider [3] & (!\ula_|i2c_loader_|divider[2]~8 & VCC)) // \ula_|i2c_loader_|divider[3]~10 = CARRY((\ula_|i2c_loader_|divider [3] & !\ula_|i2c_loader_|divider[2]~8 )) - .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [3]), + .dataa(\ula_|i2c_loader_|divider [3]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|divider[2]~8 ), .combout(\ula_|i2c_loader_|divider[3]~9_combout ), .cout(\ula_|i2c_loader_|divider[3]~10 )); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[3]~9 .lut_mask = 16'hC30C; +defparam \ula_|i2c_loader_|divider[3]~9 .lut_mask = 16'hA50A; defparam \ula_|i2c_loader_|divider[3]~9 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N15 +// Location: FF_X1_Y24_N13 dffeas \ula_|i2c_loader_|divider[3] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[3]~9_combout ), @@ -53757,7 +54312,24 @@ defparam \ula_|i2c_loader_|divider[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N16 +// Location: LCCOMB_X1_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( +// Equation(s): +// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [1])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [3]) + + .dataa(\ula_|i2c_loader_|divider [3]), + .datab(\ula_|i2c_loader_|divider [0]), + .datac(\ula_|i2c_loader_|divider [1]), + .datad(\ula_|i2c_loader_|divider [2]), + .cin(gnd), + .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; +defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N14 cycloneive_lcell_comb \ula_|i2c_loader_|divider[4]~11 ( // Equation(s): // \ula_|i2c_loader_|divider[4]~11_combout = (\ula_|i2c_loader_|divider [4] & (!\ula_|i2c_loader_|divider[3]~10 )) # (!\ula_|i2c_loader_|divider [4] & ((\ula_|i2c_loader_|divider[3]~10 ) # (GND))) @@ -53775,7 +54347,7 @@ defparam \ula_|i2c_loader_|divider[4]~11 .lut_mask = 16'h3C3F; defparam \ula_|i2c_loader_|divider[4]~11 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N17 +// Location: FF_X1_Y24_N15 dffeas \ula_|i2c_loader_|divider[4] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[4]~11_combout ), @@ -53794,7 +54366,7 @@ defparam \ula_|i2c_loader_|divider[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N18 +// Location: LCCOMB_X1_Y24_N16 cycloneive_lcell_comb \ula_|i2c_loader_|divider[5]~13 ( // Equation(s): // \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider[4]~12 $ (!\ula_|i2c_loader_|divider [5]) @@ -53811,7 +54383,7 @@ defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hF00F; defparam \ula_|i2c_loader_|divider[5]~13 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N19 +// Location: FF_X1_Y24_N17 dffeas \ula_|i2c_loader_|divider[5] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[5]~13_combout ), @@ -53830,1115 +54402,23 @@ defparam \ula_|i2c_loader_|divider[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( -// Equation(s): -// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [3])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [1]) - - .dataa(\ula_|i2c_loader_|divider [1]), - .datab(\ula_|i2c_loader_|divider [0]), - .datac(\ula_|i2c_loader_|divider [3]), - .datad(\ula_|i2c_loader_|divider [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; -defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y24_N8 +// Location: LCCOMB_X1_Y24_N30 cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0 ( // Equation(s): -// \ula_|i2c_loader_|WideAnd0~combout = ((\ula_|i2c_loader_|WideAnd0~0_combout ) # (!\ula_|i2c_loader_|divider [4])) # (!\ula_|i2c_loader_|divider [5]) +// \ula_|i2c_loader_|WideAnd0~combout = (\ula_|i2c_loader_|WideAnd0~0_combout ) # ((!\ula_|i2c_loader_|divider [5]) # (!\ula_|i2c_loader_|divider [4])) .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [5]), - .datac(\ula_|i2c_loader_|WideAnd0~0_combout ), - .datad(\ula_|i2c_loader_|divider [4]), + .datab(\ula_|i2c_loader_|WideAnd0~0_combout ), + .datac(\ula_|i2c_loader_|divider [4]), + .datad(\ula_|i2c_loader_|divider [5]), .cin(gnd), .combout(\ula_|i2c_loader_|WideAnd0~combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hF3FF; +defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hCFFF; defparam \ula_|i2c_loader_|WideAnd0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N1 -dffeas \ula_|i2c_loader_|state.Idle ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Idle~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Idle~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Idle .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Idle .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|phase~0 ( -// Equation(s): -// \ula_|i2c_loader_|phase~0_combout = (!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|phase~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|phase~0 .lut_mask = 16'h0F00; -defparam \ula_|i2c_loader_|phase~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N5 -dffeas \ula_|i2c_loader_|phase[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|phase~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|phase [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|phase[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|phase[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|phase~1 ( -// Equation(s): -// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [0] $ (\ula_|i2c_loader_|phase [1]))) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|phase~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h3C00; -defparam \ula_|i2c_loader_|phase~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N15 -dffeas \ula_|i2c_loader_|phase[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|phase~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|phase [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|phase[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|phase[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~5_combout = (!\ula_|i2c_loader_|nbit [0]) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbit [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h5F5F; -defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) -// \ula_|i2c_loader_|thisbyte[0]~9 = CARRY(\ula_|i2c_loader_|thisbyte [0]) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~8_combout ), - .cout(\ula_|i2c_loader_|thisbyte[0]~9 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; -defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( -// Equation(s): -// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Mux42~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hF000; -defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [0] $ (!\ula_|i2c_loader_|nbyte [1])))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Start~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hFF84; -defparam \ula_|i2c_loader_|nbyte~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state.Ack~q ) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hC0C0; -defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X0_Y23_N1 -cycloneive_io_ibuf \I2C_SDAT~input ( - .i(I2C_SDAT), - .ibar(gnd), - .o(\I2C_SDAT~input_o )); -// synopsys translate_off -defparam \I2C_SDAT~input .bus_hold = "false"; -defparam \I2C_SDAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hEFE0; -defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|thisbyte[0]~7_combout & \ula_|i2c_loader_|nbyte[0]~1_combout )))) - - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hD888; -defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~3_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|nbyte[0]~2_combout )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), - .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h3000; -defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N29 -dffeas \ula_|i2c_loader_|nbyte[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbyte~4_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbyte [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbyte[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Stop~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h1010; -defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Stop~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))) # -// (!\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Stop~q )))) - - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Stop~q ), - .datad(\ula_|i2c_loader_|state.Stop~0_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Stop~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF4B0; -defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N3 -dffeas \ula_|i2c_loader_|state.Stop ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Stop~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Stop~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Ack~q ))) - - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Ack~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Idle~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; -defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])))) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|nbit [0]), - .datac(\ula_|i2c_loader_|nbit [2]), - .datad(\ula_|i2c_loader_|nbit [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; -defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N1 -dffeas \ula_|i2c_loader_|nbit[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~0_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [0]))) - - .dataa(\ula_|i2c_loader_|nbit [1]), - .datab(\ula_|i2c_loader_|nbit [2]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|nbit [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~0 .lut_mask = 16'h0010; -defparam \ula_|i2c_loader_|state.Done~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Done~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|state.Idle~0_combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), - .datad(\ula_|i2c_loader_|state.Done~0_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hAF2F; -defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Data~q ))))) # -// (!\ula_|i2c_loader_|state.Ack~0_combout & (((\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|state.Ack~0_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF2D0; -defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N31 -dffeas \ula_|i2c_loader_|state.Ack ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Ack~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Ack~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hEFE0; -defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[1]~5_combout ))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h0800; -defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y23_N15 -dffeas \ula_|i2c_loader_|thisbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), - .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; -defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N17 -dffeas \ula_|i2c_loader_|thisbyte[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) -// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), - .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hC30C; -defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N19 -dffeas \ula_|i2c_loader_|thisbyte[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), - .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; -defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N21 -dffeas \ula_|i2c_loader_|thisbyte[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( -// Equation(s): -// \ula_|i2c_loader_|Equal2~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0002; -defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~0_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]))) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Stop~q )))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h5FCC; -defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) - - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), - .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; -defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N23 -dffeas \ula_|i2c_loader_|thisbyte[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~1_combout = (\ula_|i2c_loader_|state.Pause~0_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|Equal2~0_combout ), - .datac(\ula_|i2c_loader_|state.Pause~0_combout ), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h30F0; -defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~2_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Done~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & -// (\ula_|i2c_loader_|state.Data~q & ((!\ula_|i2c_loader_|state.Done~1_combout )))) - - .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Done~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~2 .lut_mask = 16'h0ACE; -defparam \ula_|i2c_loader_|state.Done~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~2_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Done~2_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Done~2_combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'hC4FF; -defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Pause~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~2_combout & (\ula_|i2c_loader_|state.Pause~1_combout )) # -// (!\ula_|i2c_loader_|state.Pause~2_combout & ((\ula_|i2c_loader_|state.Pause~q ))))) - - .dataa(\ula_|i2c_loader_|state.Pause~1_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Pause~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'hE2F0; -defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N23 -dffeas \ula_|i2c_loader_|state.Pause ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Pause~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Pause~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( -// Equation(s): -// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # -// (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Pause~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h38FF; -defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N31 -dffeas \ula_|i2c_loader_|state.Start ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state~25_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Start~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Start .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Start~q )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [0]), - .datad(\ula_|i2c_loader_|state.Start~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h000C; -defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N11 -dffeas \ula_|i2c_loader_|nbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbyte~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & !\ula_|i2c_loader_|state.Data~q )) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0005; -defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h47CF; -defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # ((\ula_|i2c_loader_|nbit[0]~2_combout ) # (\ula_|i2c_loader_|state.Done~0_combout )))) - - .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), - .datab(\ula_|i2c_loader_|nbit[0]~2_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Done~0_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h0F0E; -defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~4 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~4_combout = (!\ula_|i2c_loader_|nbit[0]~3_combout & (\ula_|i2c_loader_|Mux42~0_combout & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q ))) - - .dataa(\ula_|i2c_loader_|nbit[0]~3_combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~4 .lut_mask = 16'h0400; -defparam \ula_|i2c_loader_|nbit[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N3 -dffeas \ula_|i2c_loader_|nbit[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~5_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbit [1]), - .datad(\ula_|i2c_loader_|nbit [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hF55F; -defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N13 -dffeas \ula_|i2c_loader_|nbit[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~6_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~1_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & !\ula_|i2c_loader_|nbit [0])) - - .dataa(\ula_|i2c_loader_|nbit [1]), - .datab(\ula_|i2c_loader_|nbit [2]), - .datac(gnd), - .datad(\ula_|i2c_loader_|nbit [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~1 .lut_mask = 16'h0011; -defparam \ula_|i2c_loader_|state.Done~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( -// Equation(s): -// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Done~1_combout ) # (!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Done~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h5FFF; -defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( -// Equation(s): -// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hE0E0; -defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( -// Equation(s): -// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state~24_combout )) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state~24_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hA000; -defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~27_combout )) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~26_combout ))) - - .dataa(\ula_|i2c_loader_|state~27_combout ), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state~26_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Data~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hAFA0; -defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N29 -dffeas \ula_|i2c_loader_|state.Data ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Data~0_combout ), - .asdata(\ula_|i2c_loader_|Mux42~0_combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2c_loader_|state.Start~q ), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Data~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Data .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( -// Equation(s): -// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Stop~q )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Stop~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|scl_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0003; -defparam \ula_|i2c_loader_|scl_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: FF_X1_Y23_N13 dffeas \ula_|i2c_loader_|scl_out~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), @@ -54958,38 +54438,1113 @@ defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~1 ( +// Location: LCCOMB_X2_Y24_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( // Equation(s): -// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Start~q $ (((!\ula_|i2c_loader_|scl_out~_Duplicate_1_q ))))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # -// ((\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|scl_out~_Duplicate_1_q )))) +// \ula_|i2c_loader_|state.Idle~feeder_combout = VCC - .dataa(\ula_|i2c_loader_|state.Start~q ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Idle~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; +defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N23 +dffeas \ula_|i2c_loader_|state.Idle ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Idle~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Idle~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Idle .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Idle .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|phase~0 ( +// Equation(s): +// \ula_|i2c_loader_|phase~0_combout = (!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|phase~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|phase~0 .lut_mask = 16'h0F00; +defparam \ula_|i2c_loader_|phase~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N9 +dffeas \ula_|i2c_loader_|phase[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|phase~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|phase [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|phase[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|phase[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|phase~1 ( +// Equation(s): +// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [0] $ (\ula_|i2c_loader_|phase [1]))) + + .dataa(gnd), .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|phase~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h3C00; +defparam \ula_|i2c_loader_|phase~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y24_N29 +dffeas \ula_|i2c_loader_|phase[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|phase~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|phase [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|phase[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|phase[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( +// Equation(s): +// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|phase [0]) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|Mux42~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hC0C0; +defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|phase [0])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|phase [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y25_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~4_combout = (!\ula_|i2c_loader_|state.Data~q ) # (!\ula_|i2c_loader_|nbit [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|nbit [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~4 .lut_mask = 16'h0FFF; +defparam \ula_|i2c_loader_|nbit~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [0] $ (!\ula_|i2c_loader_|nbyte [1])))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|phase [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hEDCC; +defparam \ula_|i2c_loader_|nbyte~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y23_N31 +dffeas \ula_|i2c_loader_|nbyte[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbyte~4_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbyte [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbyte[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~1_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'hFC00; +defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Start~q ) # ((!\ula_|i2c_loader_|state.Pause~0_combout & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # (\ula_|i2c_loader_|state.Data~q )))) + + .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Pause~0_combout ), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'hCFCE; +defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~3_combout = (\ula_|i2c_loader_|Mux42~0_combout & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|nbit[0]~2_combout ))) + + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|nbit[0]~2_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h2000; +defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y25_N27 +dffeas \ula_|i2c_loader_|nbit[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~4_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y25_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~5_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(gnd), + .datac(\ula_|i2c_loader_|nbit [1]), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'hF55F; +defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y25_N1 +dffeas \ula_|i2c_loader_|nbit[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~5_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y25_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~1_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [1] & !\ula_|i2c_loader_|nbit [0])) + + .dataa(\ula_|i2c_loader_|nbit [2]), + .datab(\ula_|i2c_loader_|nbit [1]), + .datac(gnd), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h0011; +defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( +// Equation(s): +// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Pause~1_combout ) # (!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Pause~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h3FFF; +defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( +// Equation(s): +// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hFC00; +defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( +// Equation(s): +// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state~24_combout )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state~24_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hC000; +defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~27_combout )) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~26_combout ))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state~27_combout ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|state~26_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Data~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hCFC0; +defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N5 +dffeas \ula_|i2c_loader_|state.Data ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Data~0_combout ), + .asdata(\ula_|i2c_loader_|Mux42~0_combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2c_loader_|state.Start~q ), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Data~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Data .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y25_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [1] & !\ula_|i2c_loader_|nbit [0])))) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|nbit [1]), + .datac(\ula_|i2c_loader_|nbit [2]), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; +defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y25_N13 +dffeas \ula_|i2c_loader_|nbit[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y25_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~0_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [0] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [1]))) + + .dataa(\ula_|i2c_loader_|nbit [2]), + .datab(\ula_|i2c_loader_|nbit [0]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|nbit [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h0010; +defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Pause~q ))) + + .dataa(\ula_|i2c_loader_|state.Stop~q ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Pause~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Idle~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; +defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Pause~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|state.Pause~0_combout ), + .datad(\ula_|i2c_loader_|state.Idle~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hB3BB; +defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|state.Data~q ))) # +// (!\ula_|i2c_loader_|state.Ack~0_combout & (\ula_|i2c_loader_|state.Ack~q )))) + + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|state.Ack~0_combout ), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF4B0; +defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N25 +dffeas \ula_|i2c_loader_|state.Ack ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Ack~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Ack~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state.Ack~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hF000; +defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y23_N1 +cycloneive_io_ibuf \I2C_SDAT~input ( + .i(I2C_SDAT), + .ibar(gnd), + .o(\I2C_SDAT~input_o )); +// synopsys translate_off +defparam \I2C_SDAT~input .bus_hold = "false"; +defparam \I2C_SDAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hFBC8; +defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|Mux42~0_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|thisbyte[0]~7_combout & ((\ula_|i2c_loader_|nbyte[0]~1_combout )))) + + .dataa(\ula_|i2c_loader_|thisbyte[0]~7_combout ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hCAC0; +defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~3_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[0]~2_combout )) + + .dataa(\ula_|i2c_loader_|state.Idle~q ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(gnd), + .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h2200; +defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y23_N21 +dffeas \ula_|i2c_loader_|nbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|i2c_loader_|nbyte~0_combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Stop~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Stop~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))))) # +// (!\ula_|i2c_loader_|Mux42~0_combout & (((\ula_|i2c_loader_|state.Stop~q )))) + + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Stop~q ), + .datad(\ula_|i2c_loader_|state.Stop~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Stop~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF2D0; +defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N7 +dffeas \ula_|i2c_loader_|state.Stop ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Stop~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Stop~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0]) # (!\ula_|i2c_loader_|phase [1])))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state.Stop~q )) + + .dataa(\ula_|i2c_loader_|state.Stop~q ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|phase [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'h2EEE; +defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) +// \ula_|i2c_loader_|thisbyte[0]~9 = CARRY(\ula_|i2c_loader_|thisbyte [0]) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~8_combout ), + .cout(\ula_|i2c_loader_|thisbyte[0]~9 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; +defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hFBC8; +defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~18_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q & (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|nbyte[1]~5_combout ))) + + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h4000; +defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y23_N19 +dffeas \ula_|i2c_loader_|thisbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), + .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y23_N21 +dffeas \ula_|i2c_loader_|thisbyte[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) +// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) + + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), + .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hA50A; +defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y23_N23 +dffeas \ula_|i2c_loader_|thisbyte[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), + .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y23_N25 +dffeas \ula_|i2c_loader_|thisbyte[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( +// Equation(s): +// \ula_|i2c_loader_|Equal2~0_combout = (!\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte [3]))) + + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0010; +defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) + + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), + .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; +defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y23_N27 +dffeas \ula_|i2c_loader_|thisbyte[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|state.Pause~2_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Pause~2_combout ), + .datac(\ula_|i2c_loader_|Equal2~0_combout ), + .datad(\ula_|i2c_loader_|thisbyte [4]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'h0CCC; +defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( +// Equation(s): +// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Data~q )) + + .dataa(\ula_|i2c_loader_|state.Stop~q ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|scl_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0011; +defparam \ula_|i2c_loader_|scl_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~4 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~4_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Pause~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & +// (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Pause~1_combout )))) + + .dataa(\ula_|i2c_loader_|scl_out~0_combout ), + .datab(\ula_|i2c_loader_|state.Pause~q ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|state.Pause~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~4 .lut_mask = 16'h22F2; +defparam \ula_|i2c_loader_|state.Pause~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~5 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~5_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Pause~4_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Pause~4_combout ), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|Mux42~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~5 .lut_mask = 16'hF733; +defparam \ula_|i2c_loader_|state.Pause~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~6 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~6_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Pause~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~5_combout & (\ula_|i2c_loader_|state.Pause~3_combout )) # +// (!\ula_|i2c_loader_|state.Pause~5_combout & ((\ula_|i2c_loader_|state.Pause~q ))))) + + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|state.Pause~3_combout ), + .datac(\ula_|i2c_loader_|state.Pause~q ), + .datad(\ula_|i2c_loader_|state.Pause~5_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~6 .lut_mask = 16'hE4F0; +defparam \ula_|i2c_loader_|state.Pause~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N21 +dffeas \ula_|i2c_loader_|state.Pause ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Pause~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Pause~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( +// Equation(s): +// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # +// (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|state.Pause~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h58FF; +defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N31 +dffeas \ula_|i2c_loader_|state.Start ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state~25_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Start~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Start .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~1 ( +// Equation(s): +// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|scl_out~_Duplicate_1_q $ (((!\ula_|i2c_loader_|state.Start~q ))))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # +// ((\ula_|i2c_loader_|scl_out~_Duplicate_1_q & \ula_|i2c_loader_|state.Start~q )))) + + .dataa(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|phase [0]), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hBA74; +defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hA5EC; defparam \ula_|i2c_loader_|scl_out~1 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X1_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~2 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|scl_out~1_combout & ((\ula_|i2c_loader_|state.Start~q ))) # (!\ula_|i2c_loader_|scl_out~1_combout & (!\ula_|i2c_loader_|scl_out~0_combout & !\ula_|i2c_loader_|state.Start~q )) +// \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|scl_out~1_combout & (\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|scl_out~1_combout & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|scl_out~0_combout )) - .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(\ula_|i2c_loader_|scl_out~1_combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|state.Start~q ), + .dataa(\ula_|i2c_loader_|scl_out~1_combout ), + .datab(gnd), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|scl_out~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hCC11; +defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hA0A5; defparam \ula_|i2c_loader_|scl_out~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -55031,15 +55586,32 @@ defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N10 +// Location: LCCOMB_X3_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( +// Equation(s): +// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [3]) # (!\ula_|i2c_loader_|thisbyte [1])))) + + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Mux35~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h20A0; +defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~4 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Start~q ) +// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Data~q ) .dataa(gnd), .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~4_combout ), .cout()); @@ -55048,146 +55620,146 @@ defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h000F; defparam \ula_|i2c_loader_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( +// Location: LCCOMB_X3_Y23_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( // Equation(s): -// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [1]) # (!\ula_|i2c_loader_|thisbyte [3])))) +// \ula_|i2c_loader_|shiftreg~19_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1])) # (!\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [3]))))) .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [1]), - .datad(\ula_|i2c_loader_|thisbyte [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Mux35~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h2A00; -defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) - - .dataa(\ula_|i2c_loader_|thisbyte [4]), .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h001A; -defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~14_combout = (\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2]) - - .dataa(gnd), - .datab(gnd), .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [3]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~14_combout ), + .combout(\ula_|i2c_loader_|shiftreg~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h00F0; -defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h202A; +defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( +// Location: LCCOMB_X3_Y23_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|shiftreg~13_combout ) # ((!\ula_|i2c_loader_|thisbyte [3] & (\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|shiftreg~14_combout ))) +// \ula_|i2c_loader_|shiftreg~20_combout = ((\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|shiftreg~19_combout ))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) - .dataa(\ula_|i2c_loader_|shiftreg~13_combout ), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|shiftreg~14_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'hAABA; -defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~24 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~24_combout = (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|thisbyte [0])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|shiftreg~4_combout ), + .datac(\ula_|i2c_loader_|shiftreg~19_combout ), .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~24_combout ), + .combout(\ula_|i2c_loader_|shiftreg~20_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~24 .lut_mask = 16'h0300; -defparam \ula_|i2c_loader_|shiftreg[0]~24 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'h73FB; +defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N14 +// Location: LCCOMB_X3_Y23_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [3]))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [3])))) + + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [0]), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h8804; +defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~23 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~23_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~22_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) + + .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|shiftreg~22_combout ), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hA0A8; +defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~25 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[0]~25_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|thisbyte [3] & \ula_|i2c_loader_|thisbyte [0])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|thisbyte [3]), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg[0]~25 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|shiftreg[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N12 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~6 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~6_combout = (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|shiftreg[0]~6_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|phase [0] & !\ula_|i2c_loader_|phase [1])) - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|phase [1]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h5000; +defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h00C0; defparam \ula_|i2c_loader_|shiftreg[0]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N0 +// Location: LCCOMB_X2_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~7 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|state~24_combout )))) +// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state~24_combout ) # (\ula_|i2c_loader_|state.Start~q )))) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|shiftreg[0]~6_combout ), - .datad(\ula_|i2c_loader_|state~24_combout ), + .dataa(\ula_|i2c_loader_|shiftreg[0]~6_combout ), + .datab(\ula_|i2c_loader_|state~24_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|Mux42~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFCF8; +defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFEAA; defparam \ula_|i2c_loader_|shiftreg[0]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N10 +// Location: LCCOMB_X2_Y24_N0 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~8 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~8_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|shiftreg[0]~7_combout )) +// \ula_|i2c_loader_|shiftreg[0]~8_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|shiftreg[0]~7_combout & \ula_|i2c_loader_|state.Idle~q )) - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Idle~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|shiftreg[0]~7_combout ), + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|shiftreg[0]~7_combout ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Idle~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h0C00; +defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h4400; defparam \ula_|i2c_loader_|shiftreg[0]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N13 +// Location: FF_X3_Y24_N21 dffeas \ula_|i2c_loader_|shiftreg[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg[0]~24_combout ), + .d(\ula_|i2c_loader_|shiftreg[0]~25_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -55203,102 +55775,85 @@ defparam \ula_|i2c_loader_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( +// Location: LCCOMB_X3_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~24 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte [2]))) # (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2])))) +// \ula_|i2c_loader_|shiftreg~24_combout = (\ula_|i2c_loader_|shiftreg~23_combout ) # ((\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [0])) - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~21_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hC010; -defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~21_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) - - .dataa(\ula_|i2c_loader_|shiftreg~21_combout ), - .datab(\ula_|i2c_loader_|shiftreg~4_combout ), - .datac(\ula_|i2c_loader_|thisbyte [1]), - .datad(\ula_|i2c_loader_|thisbyte [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h88C8; -defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~23 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~23_combout = (\ula_|i2c_loader_|shiftreg~22_combout ) # ((\ula_|i2c_loader_|shiftreg [0] & \ula_|i2c_loader_|state.Data~q )) - - .dataa(\ula_|i2c_loader_|shiftreg [0]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|shiftreg~23_combout ), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~22_combout ), + .datad(\ula_|i2c_loader_|shiftreg [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~23_combout ), + .combout(\ula_|i2c_loader_|shiftreg~24_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hFFA0; -defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~24 .lut_mask = 16'hFCCC; +defparam \ula_|i2c_loader_|shiftreg~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N10 +// Location: LCCOMB_X2_Y24_N6 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~10 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state.Start~q ) # ((!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|state~24_combout )))) # (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Data~q -// & (!\ula_|i2c_loader_|state.Start~q ))) +// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|phase [1]) # (!\ula_|i2c_loader_|phase [0])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state~24_combout )) - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state~24_combout ), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|state~24_combout ), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|phase [1]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hA6A4; +defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hBB1B; defparam \ula_|i2c_loader_|shiftreg[6]~10 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X2_Y24_N24 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~11 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|shiftreg[6]~10_combout ))) +// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg[6]~10_combout ) # ((!\ula_|i2c_loader_|Mux42~0_combout & +// !\ula_|i2c_loader_|state.Data~q )))) - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), .datad(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~11 .lut_mask = 16'h2000; +defparam \ula_|i2c_loader_|shiftreg[6]~11 .lut_mask = 16'h5F51; defparam \ula_|i2c_loader_|shiftreg[6]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N23 +// Location: LCCOMB_X2_Y24_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~12 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[6]~12_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (!\ula_|i2c_loader_|shiftreg[6]~11_combout & \ula_|i2c_loader_|state.Idle~q )) + + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg[6]~12 .lut_mask = 16'h1100; +defparam \ula_|i2c_loader_|shiftreg[6]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N13 dffeas \ula_|i2c_loader_|shiftreg[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~23_combout ), + .d(\ula_|i2c_loader_|shiftreg~24_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [1]), @@ -55308,67 +55863,33 @@ defparam \ula_|i2c_loader_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( +// Location: LCCOMB_X3_Y24_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [1]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [3])))) +// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|shiftreg~20_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h10B0; -defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~19_combout = ((\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [0])) # (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|shiftreg~18_combout )))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(\ula_|i2c_loader_|shiftreg~18_combout ), - .datad(\ula_|i2c_loader_|shiftreg~4_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h74FF; -defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~20_combout = (\ula_|i2c_loader_|shiftreg~19_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) - - .dataa(\ula_|i2c_loader_|shiftreg [1]), + .dataa(\ula_|i2c_loader_|shiftreg~20_combout ), .datab(gnd), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~19_combout ), + .datad(\ula_|i2c_loader_|shiftreg [1]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~20_combout ), + .combout(\ula_|i2c_loader_|shiftreg~21_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'hAF00; -defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hAA0A; +defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N3 +// Location: FF_X3_Y24_N11 dffeas \ula_|i2c_loader_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~20_combout ), + .d(\ula_|i2c_loader_|shiftreg~21_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [2]), @@ -55378,67 +55899,84 @@ defparam \ula_|i2c_loader_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( +// Location: LCCOMB_X3_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) +// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) .dataa(\ula_|i2c_loader_|thisbyte [2]), .datab(\ula_|i2c_loader_|thisbyte [1]), .datac(\ula_|i2c_loader_|thisbyte [4]), .datad(\ula_|i2c_loader_|thisbyte [3]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'h10BA; -defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~16_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [3] & ((!\ula_|i2c_loader_|shiftreg~14_combout )))) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|shiftreg~16_combout ), - .datad(\ula_|i2c_loader_|shiftreg~14_combout ), - .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'hA0E4; +defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'h10BA; defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( +// Location: LCCOMB_X3_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [2])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg~17_combout )))) +// \ula_|i2c_loader_|shiftreg~15_combout = (!\ula_|i2c_loader_|thisbyte [2] & \ula_|i2c_loader_|thisbyte [4]) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|shiftreg [2]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~17_combout ), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(gnd), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(gnd), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~26_combout ), + .combout(\ula_|i2c_loader_|shiftreg~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hC5C0; -defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'h5050; +defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N7 +// Location: LCCOMB_X3_Y24_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|shiftreg~17_combout )) # (!\ula_|i2c_loader_|thisbyte [0] & (((!\ula_|i2c_loader_|shiftreg~15_combout & \ula_|i2c_loader_|thisbyte [3])))) + + .dataa(\ula_|i2c_loader_|shiftreg~17_combout ), + .datab(\ula_|i2c_loader_|shiftreg~15_combout ), + .datac(\ula_|i2c_loader_|thisbyte [3]), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'hAA30; +defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~27 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~27_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [2])) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|shiftreg~18_combout )))) + + .dataa(\ula_|i2c_loader_|shiftreg [2]), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg~18_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~27 .lut_mask = 16'hA3A0; +defparam \ula_|i2c_loader_|shiftreg~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N23 dffeas \ula_|i2c_loader_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~26_combout ), + .d(\ula_|i2c_loader_|shiftreg~27_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [3]), @@ -55448,33 +55986,67 @@ defparam \ula_|i2c_loader_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~25 ( +// Location: LCCOMB_X3_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg~15_combout ) # ((\ula_|i2c_loader_|state.Start~q )))) +// \ula_|i2c_loader_|shiftreg~14_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) - .dataa(\ula_|i2c_loader_|shiftreg~15_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|shiftreg [3]), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~25_combout ), + .combout(\ula_|i2c_loader_|shiftreg~14_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hFE32; -defparam \ula_|i2c_loader_|shiftreg~25 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h0150; +defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N1 +// Location: LCCOMB_X3_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|shiftreg~14_combout ) # ((\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [3] & !\ula_|i2c_loader_|shiftreg~15_combout ))) + + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|shiftreg~14_combout ), + .datac(\ula_|i2c_loader_|thisbyte [3]), + .datad(\ula_|i2c_loader_|shiftreg~15_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'hCCCE; +defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [3])) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|shiftreg~16_combout )))) + + .dataa(\ula_|i2c_loader_|shiftreg [3]), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg~16_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hAFAC; +defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N15 dffeas \ula_|i2c_loader_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~25_combout ), + .d(\ula_|i2c_loader_|shiftreg~26_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [4]), @@ -55484,33 +56056,33 @@ defparam \ula_|i2c_loader_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~12 ( +// Location: LCCOMB_X4_Y24_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~12_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) +// \ula_|i2c_loader_|shiftreg~13_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) .dataa(\ula_|i2c_loader_|Mux35~0_combout ), .datab(\ula_|i2c_loader_|state.Data~q ), .datac(gnd), .datad(\ula_|i2c_loader_|shiftreg [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~12_combout ), + .combout(\ula_|i2c_loader_|shiftreg~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~12 .lut_mask = 16'hEE22; -defparam \ula_|i2c_loader_|shiftreg~12 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'hEE22; +defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N5 +// Location: FF_X4_Y24_N5 dffeas \ula_|i2c_loader_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~12_combout ), + .d(\ula_|i2c_loader_|shiftreg~13_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(\ula_|i2c_loader_|state.Start~q ), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [5]), @@ -55520,24 +56092,24 @@ defparam \ula_|i2c_loader_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N18 +// Location: LCCOMB_X3_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~9 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~9_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [5])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) +// \ula_|i2c_loader_|shiftreg~9_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [5]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) .dataa(gnd), - .datab(\ula_|i2c_loader_|shiftreg [5]), + .datab(\ula_|i2c_loader_|Mux35~0_combout ), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|Mux35~0_combout ), + .datad(\ula_|i2c_loader_|shiftreg [5]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hCFC0; +defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hFC0C; defparam \ula_|i2c_loader_|shiftreg~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N19 +// Location: FF_X3_Y24_N3 dffeas \ula_|i2c_loader_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~9_combout ), @@ -55546,7 +56118,7 @@ dffeas \ula_|i2c_loader_|shiftreg[6] ( .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [6]), @@ -55556,7 +56128,7 @@ defparam \ula_|i2c_loader_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N4 +// Location: LCCOMB_X3_Y24_N28 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[7]~5 ( // Equation(s): // \ula_|i2c_loader_|shiftreg[7]~5_combout = (\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [6]) @@ -55573,7 +56145,7 @@ defparam \ula_|i2c_loader_|shiftreg[7]~5 .lut_mask = 16'hF000; defparam \ula_|i2c_loader_|shiftreg[7]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N5 +// Location: FF_X3_Y24_N29 dffeas \ula_|i2c_loader_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg[7]~5_combout ), @@ -55592,42 +56164,42 @@ defparam \ula_|i2c_loader_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N12 +// Location: LCCOMB_X2_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~0 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|shiftreg [7]))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|state.Data~q & +// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|shiftreg [7])) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|state.Ack~q ))))) # (!\ula_|i2c_loader_|state.Data~q & // (((\ula_|i2c_loader_|state.Ack~q )))) - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|phase [0]), + .dataa(\ula_|i2c_loader_|shiftreg [7]), + .datab(\ula_|i2c_loader_|state.Data~q ), .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|shiftreg [7]), + .datad(\ula_|i2c_loader_|phase [0]), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hF870; +defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hB8F0; defparam \ula_|i2c_loader_|sda_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N6 +// Location: LCCOMB_X1_Y23_N18 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~1 ( // Equation(s): // \ula_|i2c_loader_|sda_out~1_combout = (\ula_|i2c_loader_|sda_out~0_combout & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|shiftreg~4_combout & !\I2C_SDAT~input_o )))) - .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), + .dataa(\ula_|i2c_loader_|sda_out~0_combout ), .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|sda_out~0_combout ), + .datac(\ula_|i2c_loader_|shiftreg~4_combout ), .datad(\I2C_SDAT~input_o ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'hC0E0; +defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'h88A8; defparam \ula_|i2c_loader_|sda_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N8 +// Location: LCCOMB_X1_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~2 ( // Equation(s): // \ula_|i2c_loader_|sda_out~2_combout = (!\ula_|i2c_loader_|sda_out~_Duplicate_1_q & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|phase [1] & !\ula_|i2c_loader_|sda_out~1_combout )))) @@ -55644,7 +56216,7 @@ defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h4454; defparam \ula_|i2c_loader_|sda_out~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N2 +// Location: LCCOMB_X1_Y23_N6 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~3 ( // Equation(s): // \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )) # (!\ula_|i2c_loader_|phase [1] & ((!\ula_|i2c_loader_|sda_out~1_combout ))))) # (!\ula_|i2c_loader_|phase @@ -55698,7 +56270,2727 @@ defparam \ula_|i2c_loader_|sda_out .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out .power_up = "high"; // synopsys translate_on -// Location: LCCOMB_X27_Y23_N16 +// Location: PLL_1 +cycloneive_pll \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 ( + .areset(gnd), + .pfdena(vcc), + .fbin(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\CLOCK_50~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(), + .vcooverrange(), + .vcounderrange(), + .fbout(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c0_high = 3; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c0_initial = 2; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c0_low = 2; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c0_mode = "odd"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c0_ph = 4; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_high = 3; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_initial = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_low = 2; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_mode = "odd"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk0_counter = "c1"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk0_divide_by = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk0_multiply_by = 2; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk1_counter = "c0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk1_divide_by = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk1_multiply_by = 2; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk1_phase_shift = "3000"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .m = 10; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .n = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .pll_compensation_delay = 5611; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 250; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N14 +cycloneive_lcell_comb \sdram_|Mux38~0 ( +// Equation(s): +// \sdram_|Mux38~0_combout = (\sdram_|r.rd_pending~q & (((\sdram_|Mux39~1_combout )))) # (!\sdram_|r.rd_pending~q & (\z80_|control_pins_|pin_nIORQ~1_combout & (\Equal2~1_combout ))) + + .dataa(\z80_|control_pins_|pin_nIORQ~1_combout ), + .datab(\Equal2~1_combout ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Mux39~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux38~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux38~0 .lut_mask = 16'hF808; +defparam \sdram_|Mux38~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y12_N15 +dffeas \sdram_|r.rd_pending ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux38~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rd_pending~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rd_pending .is_wysiwyg = "true"; +defparam \sdram_|r.rd_pending .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N0 +cycloneive_lcell_comb \sdram_|r.rf_counter[0]~12 ( +// Equation(s): +// \sdram_|r.rf_counter[0]~12_combout = \sdram_|r.rf_counter [0] $ (VCC) +// \sdram_|r.rf_counter[0]~13 = CARRY(\sdram_|r.rf_counter [0]) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_|r.rf_counter[0]~12_combout ), + .cout(\sdram_|r.rf_counter[0]~13 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[0]~12 .lut_mask = 16'h33CC; +defparam \sdram_|r.rf_counter[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N26 +cycloneive_lcell_comb \sdram_|r.rf_counter[3]~32 ( +// Equation(s): +// \sdram_|r.rf_counter[3]~32_combout = ((!\sdram_|r.state [5] & (\sdram_|r.address[3]~6_combout & !\sdram_|r.state [4]))) # (!\sdram_|Equal0~2_combout ) + + .dataa(\sdram_|Equal0~2_combout ), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.address[3]~6_combout ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|r.rf_counter[3]~32_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.rf_counter[3]~32 .lut_mask = 16'h5575; +defparam \sdram_|r.rf_counter[3]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y13_N1 +dffeas \sdram_|r.rf_counter[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[0]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[0] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N2 +cycloneive_lcell_comb \sdram_|r.rf_counter[1]~14 ( +// Equation(s): +// \sdram_|r.rf_counter[1]~14_combout = (\sdram_|r.rf_counter [1] & (!\sdram_|r.rf_counter[0]~13 )) # (!\sdram_|r.rf_counter [1] & ((\sdram_|r.rf_counter[0]~13 ) # (GND))) +// \sdram_|r.rf_counter[1]~15 = CARRY((!\sdram_|r.rf_counter[0]~13 ) # (!\sdram_|r.rf_counter [1])) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[0]~13 ), + .combout(\sdram_|r.rf_counter[1]~14_combout ), + .cout(\sdram_|r.rf_counter[1]~15 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[1]~14 .lut_mask = 16'h3C3F; +defparam \sdram_|r.rf_counter[1]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N3 +dffeas \sdram_|r.rf_counter[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[1]~14_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[1] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N4 +cycloneive_lcell_comb \sdram_|r.rf_counter[2]~16 ( +// Equation(s): +// \sdram_|r.rf_counter[2]~16_combout = (\sdram_|r.rf_counter [2] & (\sdram_|r.rf_counter[1]~15 $ (GND))) # (!\sdram_|r.rf_counter [2] & (!\sdram_|r.rf_counter[1]~15 & VCC)) +// \sdram_|r.rf_counter[2]~17 = CARRY((\sdram_|r.rf_counter [2] & !\sdram_|r.rf_counter[1]~15 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[1]~15 ), + .combout(\sdram_|r.rf_counter[2]~16_combout ), + .cout(\sdram_|r.rf_counter[2]~17 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[2]~16 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[2]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N5 +dffeas \sdram_|r.rf_counter[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[2]~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[2] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N6 +cycloneive_lcell_comb \sdram_|r.rf_counter[3]~18 ( +// Equation(s): +// \sdram_|r.rf_counter[3]~18_combout = (\sdram_|r.rf_counter [3] & (!\sdram_|r.rf_counter[2]~17 )) # (!\sdram_|r.rf_counter [3] & ((\sdram_|r.rf_counter[2]~17 ) # (GND))) +// \sdram_|r.rf_counter[3]~19 = CARRY((!\sdram_|r.rf_counter[2]~17 ) # (!\sdram_|r.rf_counter [3])) + + .dataa(\sdram_|r.rf_counter [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[2]~17 ), + .combout(\sdram_|r.rf_counter[3]~18_combout ), + .cout(\sdram_|r.rf_counter[3]~19 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[3]~18 .lut_mask = 16'h5A5F; +defparam \sdram_|r.rf_counter[3]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N7 +dffeas \sdram_|r.rf_counter[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[3]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[3] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N8 +cycloneive_lcell_comb \sdram_|r.rf_counter[4]~20 ( +// Equation(s): +// \sdram_|r.rf_counter[4]~20_combout = (\sdram_|r.rf_counter [4] & (\sdram_|r.rf_counter[3]~19 $ (GND))) # (!\sdram_|r.rf_counter [4] & (!\sdram_|r.rf_counter[3]~19 & VCC)) +// \sdram_|r.rf_counter[4]~21 = CARRY((\sdram_|r.rf_counter [4] & !\sdram_|r.rf_counter[3]~19 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[3]~19 ), + .combout(\sdram_|r.rf_counter[4]~20_combout ), + .cout(\sdram_|r.rf_counter[4]~21 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[4]~20 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[4]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N9 +dffeas \sdram_|r.rf_counter[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[4]~20_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[4] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N10 +cycloneive_lcell_comb \sdram_|r.rf_counter[5]~22 ( +// Equation(s): +// \sdram_|r.rf_counter[5]~22_combout = (\sdram_|r.rf_counter [5] & (!\sdram_|r.rf_counter[4]~21 )) # (!\sdram_|r.rf_counter [5] & ((\sdram_|r.rf_counter[4]~21 ) # (GND))) +// \sdram_|r.rf_counter[5]~23 = CARRY((!\sdram_|r.rf_counter[4]~21 ) # (!\sdram_|r.rf_counter [5])) + + .dataa(\sdram_|r.rf_counter [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[4]~21 ), + .combout(\sdram_|r.rf_counter[5]~22_combout ), + .cout(\sdram_|r.rf_counter[5]~23 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[5]~22 .lut_mask = 16'h5A5F; +defparam \sdram_|r.rf_counter[5]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N11 +dffeas \sdram_|r.rf_counter[5] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[5]~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[5] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N12 +cycloneive_lcell_comb \sdram_|r.rf_counter[6]~24 ( +// Equation(s): +// \sdram_|r.rf_counter[6]~24_combout = (\sdram_|r.rf_counter [6] & (\sdram_|r.rf_counter[5]~23 $ (GND))) # (!\sdram_|r.rf_counter [6] & (!\sdram_|r.rf_counter[5]~23 & VCC)) +// \sdram_|r.rf_counter[6]~25 = CARRY((\sdram_|r.rf_counter [6] & !\sdram_|r.rf_counter[5]~23 )) + + .dataa(\sdram_|r.rf_counter [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[5]~23 ), + .combout(\sdram_|r.rf_counter[6]~24_combout ), + .cout(\sdram_|r.rf_counter[6]~25 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[6]~24 .lut_mask = 16'hA50A; +defparam \sdram_|r.rf_counter[6]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N13 +dffeas \sdram_|r.rf_counter[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[6]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[6] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N14 +cycloneive_lcell_comb \sdram_|r.rf_counter[7]~26 ( +// Equation(s): +// \sdram_|r.rf_counter[7]~26_combout = (\sdram_|r.rf_counter [7] & (!\sdram_|r.rf_counter[6]~25 )) # (!\sdram_|r.rf_counter [7] & ((\sdram_|r.rf_counter[6]~25 ) # (GND))) +// \sdram_|r.rf_counter[7]~27 = CARRY((!\sdram_|r.rf_counter[6]~25 ) # (!\sdram_|r.rf_counter [7])) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[6]~25 ), + .combout(\sdram_|r.rf_counter[7]~26_combout ), + .cout(\sdram_|r.rf_counter[7]~27 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[7]~26 .lut_mask = 16'h3C3F; +defparam \sdram_|r.rf_counter[7]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N15 +dffeas \sdram_|r.rf_counter[7] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[7]~26_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[7] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N24 +cycloneive_lcell_comb \sdram_|Equal0~1 ( +// Equation(s): +// \sdram_|Equal0~1_combout = (\sdram_|r.rf_counter [5]) # ((\sdram_|r.rf_counter [7]) # ((\sdram_|r.rf_counter [4]) # (\sdram_|r.rf_counter [6]))) + + .dataa(\sdram_|r.rf_counter [5]), + .datab(\sdram_|r.rf_counter [7]), + .datac(\sdram_|r.rf_counter [4]), + .datad(\sdram_|r.rf_counter [6]), + .cin(gnd), + .combout(\sdram_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~1 .lut_mask = 16'hFFFE; +defparam \sdram_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N16 +cycloneive_lcell_comb \sdram_|r.rf_counter[8]~28 ( +// Equation(s): +// \sdram_|r.rf_counter[8]~28_combout = (\sdram_|r.rf_counter [8] & (\sdram_|r.rf_counter[7]~27 $ (GND))) # (!\sdram_|r.rf_counter [8] & (!\sdram_|r.rf_counter[7]~27 & VCC)) +// \sdram_|r.rf_counter[8]~29 = CARRY((\sdram_|r.rf_counter [8] & !\sdram_|r.rf_counter[7]~27 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[7]~27 ), + .combout(\sdram_|r.rf_counter[8]~28_combout ), + .cout(\sdram_|r.rf_counter[8]~29 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[8]~28 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[8]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N17 +dffeas \sdram_|r.rf_counter[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[8]~28_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[8] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N30 +cycloneive_lcell_comb \sdram_|Equal0~0 ( +// Equation(s): +// \sdram_|Equal0~0_combout = (\sdram_|r.rf_counter [3]) # ((\sdram_|r.rf_counter [0]) # ((\sdram_|r.rf_counter [2]) # (!\sdram_|r.rf_counter [1]))) + + .dataa(\sdram_|r.rf_counter [3]), + .datab(\sdram_|r.rf_counter [0]), + .datac(\sdram_|r.rf_counter [2]), + .datad(\sdram_|r.rf_counter [1]), + .cin(gnd), + .combout(\sdram_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~0 .lut_mask = 16'hFEFF; +defparam \sdram_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N18 +cycloneive_lcell_comb \sdram_|r.rf_counter[9]~30 ( +// Equation(s): +// \sdram_|r.rf_counter[9]~30_combout = \sdram_|r.rf_counter[8]~29 $ (\sdram_|r.rf_counter [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_|r.rf_counter [9]), + .cin(\sdram_|r.rf_counter[8]~29 ), + .combout(\sdram_|r.rf_counter[9]~30_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.rf_counter[9]~30 .lut_mask = 16'h0FF0; +defparam \sdram_|r.rf_counter[9]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N19 +dffeas \sdram_|r.rf_counter[9] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[9]~30_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[9] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N22 +cycloneive_lcell_comb \sdram_|Equal0~2 ( +// Equation(s): +// \sdram_|Equal0~2_combout = (\sdram_|Equal0~1_combout ) # (((\sdram_|Equal0~0_combout ) # (!\sdram_|r.rf_counter [9])) # (!\sdram_|r.rf_counter [8])) + + .dataa(\sdram_|Equal0~1_combout ), + .datab(\sdram_|r.rf_counter [8]), + .datac(\sdram_|Equal0~0_combout ), + .datad(\sdram_|r.rf_counter [9]), + .cin(gnd), + .combout(\sdram_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~2 .lut_mask = 16'hFBFF; +defparam \sdram_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N28 +cycloneive_lcell_comb \sdram_|Mux13~8 ( +// Equation(s): +// \sdram_|Mux13~8_combout = (\sdram_|r.state [4] & !\sdram_|r.state [5]) + + .dataa(gnd), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [5]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|Mux13~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~8 .lut_mask = 16'h0C0C; +defparam \sdram_|Mux13~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N20 +cycloneive_lcell_comb \sdram_|Mux37~0 ( +// Equation(s): +// \sdram_|Mux37~0_combout = (\sdram_|r.rf_pending~q & (((!\sdram_|Mux13~8_combout ) # (!\sdram_|r.address[3]~6_combout )))) # (!\sdram_|r.rf_pending~q & (!\sdram_|Equal0~2_combout )) + + .dataa(\sdram_|Equal0~2_combout ), + .datab(\sdram_|r.address[3]~6_combout ), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Mux13~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux37~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux37~0 .lut_mask = 16'h35F5; +defparam \sdram_|Mux37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y13_N21 +dffeas \sdram_|r.rf_pending ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux37~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_pending~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_pending .is_wysiwyg = "true"; +defparam \sdram_|r.rf_pending .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N14 +cycloneive_lcell_comb \sdram_|Mux4~0 ( +// Equation(s): +// \sdram_|Mux4~0_combout = (!\sdram_|r.wr_pending~q & (\sdram_|r.rd_pending~q & (!\sdram_|r.rf_pending~q & \sdram_|Equal7~2_combout ))) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~0 .lut_mask = 16'h0400; +defparam \sdram_|Mux4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N0 +cycloneive_lcell_comb \sdram_|Mux4~1 ( +// Equation(s): +// \sdram_|Mux4~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [5] $ ((!\sdram_|r.state [4])))) # (!\sdram_|r.state [6] & (\sdram_|r.state [5] & ((!\sdram_|Mux4~0_combout ) # (!\sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|Mux4~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~1 .lut_mask = 16'h86C6; +defparam \sdram_|Mux4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N2 +cycloneive_lcell_comb \sdram_|Mux4~2 ( +// Equation(s): +// \sdram_|Mux4~2_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [5]) # ((\sdram_|r.state [4])))) # (!\sdram_|r.state [6] & ((\sdram_|Mux4~0_combout ) # ((!\sdram_|r.state [5] & \sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|Mux4~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~2 .lut_mask = 16'hFDB8; +defparam \sdram_|Mux4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N30 +cycloneive_lcell_comb \sdram_|Mux4~3 ( +// Equation(s): +// \sdram_|Mux4~3_combout = (\sdram_|Mux4~2_combout & (\sdram_|r.state [8] $ (((\sdram_|Mux4~1_combout & \sdram_|r.state [7]))))) # (!\sdram_|Mux4~2_combout & (\sdram_|r.state [8] & (\sdram_|Mux4~1_combout $ (\sdram_|r.state [7])))) + + .dataa(\sdram_|Mux4~1_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux4~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~3 .lut_mask = 16'h7860; +defparam \sdram_|Mux4~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y15_N31 +dffeas \sdram_|r.state[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux4~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[8] .is_wysiwyg = "true"; +defparam \sdram_|r.state[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N6 +cycloneive_lcell_comb \sdram_|r.act_row[1]~0 ( +// Equation(s): +// \sdram_|r.act_row[1]~0_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [6] & (\sdram_|r.state [5] & \sdram_|r.state [8])) # (!\sdram_|r.state [6] & (!\sdram_|r.state [5] & !\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.act_row[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.act_row[1]~0 .lut_mask = 16'h8004; +defparam \sdram_|r.act_row[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N18 +cycloneive_lcell_comb \sdram_|process_0~2 ( +// Equation(s): +// \sdram_|process_0~2_combout = (\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|process_0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~2 .lut_mask = 16'hFFF0; +defparam \sdram_|process_0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N0 +cycloneive_lcell_comb \sdram_|r.act_row[1]~1 ( +// Equation(s): +// \sdram_|r.act_row[1]~1_combout = (\sdram_|r.act_row[1]~0_combout & (\sdram_|process_0~2_combout & (\sdram_|r.state [7] $ (!\sdram_|r.state [8])))) + + .dataa(\sdram_|r.act_row[1]~0_combout ), + .datab(\sdram_|process_0~2_combout ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.act_row[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.act_row[1]~1 .lut_mask = 16'h8008; +defparam \sdram_|r.act_row[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y13_N9 +dffeas \sdram_|r.act_row[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\z80_|address_pins_|abus[15]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.act_row[1]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[4] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y13_N23 +dffeas \sdram_|r.act_row[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[1]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[3] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N20 +cycloneive_lcell_comb \sdram_|r.act_row[2]~feeder ( +// Equation(s): +// \sdram_|r.act_row[2]~feeder_combout = \z80_|address_pins_|abus[13]~23_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~23_combout ), + .cin(gnd), + .combout(\sdram_|r.act_row[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.act_row[2]~feeder .lut_mask = 16'hFF00; +defparam \sdram_|r.act_row[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y13_N21 +dffeas \sdram_|r.act_row[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.act_row[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.act_row[1]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[2] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N22 +cycloneive_lcell_comb \sdram_|Equal7~1 ( +// Equation(s): +// \sdram_|Equal7~1_combout = (\z80_|address_pins_|abus[14]~22_combout & (\sdram_|r.act_row [3] & (\z80_|address_pins_|abus[13]~23_combout $ (!\sdram_|r.act_row [2])))) # (!\z80_|address_pins_|abus[14]~22_combout & (!\sdram_|r.act_row [3] & +// (\z80_|address_pins_|abus[13]~23_combout $ (!\sdram_|r.act_row [2])))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\sdram_|r.act_row [3]), + .datad(\sdram_|r.act_row [2]), + .cin(gnd), + .combout(\sdram_|Equal7~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal7~1 .lut_mask = 16'h8421; +defparam \sdram_|Equal7~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y13_N3 +dffeas \sdram_|r.act_row[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[12]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[1]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[1] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y13_N13 +dffeas \sdram_|r.act_row[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[11]~19_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[1]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[0] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N2 +cycloneive_lcell_comb \sdram_|Equal7~0 ( +// Equation(s): +// \sdram_|Equal7~0_combout = (\z80_|address_pins_|abus[11]~19_combout & (\sdram_|r.act_row [0] & (\z80_|address_pins_|abus[12]~24_combout $ (!\sdram_|r.act_row [1])))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\sdram_|r.act_row [0] & +// (\z80_|address_pins_|abus[12]~24_combout $ (!\sdram_|r.act_row [1])))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\z80_|address_pins_|abus[12]~24_combout ), + .datac(\sdram_|r.act_row [1]), + .datad(\sdram_|r.act_row [0]), + .cin(gnd), + .combout(\sdram_|Equal7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal7~0 .lut_mask = 16'h8241; +defparam \sdram_|Equal7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N30 +cycloneive_lcell_comb \sdram_|Equal7~2 ( +// Equation(s): +// \sdram_|Equal7~2_combout = (\sdram_|Equal7~1_combout & (\sdram_|Equal7~0_combout & (\z80_|address_pins_|abus[15]~21_combout $ (!\sdram_|r.act_row [4])))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\sdram_|r.act_row [4]), + .datac(\sdram_|Equal7~1_combout ), + .datad(\sdram_|Equal7~0_combout ), + .cin(gnd), + .combout(\sdram_|Equal7~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal7~2 .lut_mask = 16'h9000; +defparam \sdram_|Equal7~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N4 +cycloneive_lcell_comb \sdram_|Mux39~0 ( +// Equation(s): +// \sdram_|Mux39~0_combout = (\sdram_|r.state [5] & (\sdram_|r.state [7] & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & (\sdram_|r.state [8] & (!\sdram_|r.state [7] & !\sdram_|r.state [4]))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux39~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux39~0 .lut_mask = 16'h8024; +defparam \sdram_|Mux39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N12 +cycloneive_lcell_comb \sdram_|Mux39~1 ( +// Equation(s): +// \sdram_|Mux39~1_combout = (\sdram_|r.state [6]) # ((!\sdram_|Mux39~0_combout ) # (!\sdram_|Equal7~2_combout )) + + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|Mux39~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux39~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux39~1 .lut_mask = 16'hAFFF; +defparam \sdram_|Mux39~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N24 +cycloneive_lcell_comb \sdram_|Mux39~2 ( +// Equation(s): +// \sdram_|Mux39~2_combout = (\sdram_|r.wr_pending~q & (\sdram_|Mux39~1_combout )) # (!\sdram_|r.wr_pending~q & (((\z80_|address_pins_|abus[15]~21_combout & \ExtRamWE~0_combout )))) + + .dataa(\sdram_|Mux39~1_combout ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\sdram_|r.wr_pending~q ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux39~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux39~2 .lut_mask = 16'hACA0; +defparam \sdram_|Mux39~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y12_N25 +dffeas \sdram_|r.wr_pending ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux39~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.wr_pending~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.wr_pending .is_wysiwyg = "true"; +defparam \sdram_|r.wr_pending .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N8 +cycloneive_lcell_comb \sdram_|Mux9~8 ( +// Equation(s): +// \sdram_|Mux9~8_combout = (\sdram_|r.state [8] & !\sdram_|r.state [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux9~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~8 .lut_mask = 16'h00F0; +defparam \sdram_|Mux9~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N20 +cycloneive_lcell_comb \sdram_|Mux9~9 ( +// Equation(s): +// \sdram_|Mux9~9_combout = (!\sdram_|r.rd_pending~q & (!\sdram_|r.rf_pending~q & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.wr_pending~q )))) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux9~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~9 .lut_mask = 16'h0405; +defparam \sdram_|Mux9~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N26 +cycloneive_lcell_comb \sdram_|Mux6~3 ( +// Equation(s): +// \sdram_|Mux6~3_combout = (\sdram_|r.state [6] & (((!\sdram_|Mux9~9_combout ) # (!\sdram_|Mux9~8_combout )))) # (!\sdram_|r.state [6] & (\sdram_|r.wr_pending~q & (\sdram_|Mux9~8_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|Mux9~8_combout ), + .datad(\sdram_|Mux9~9_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~3 .lut_mask = 16'h4AEA; +defparam \sdram_|Mux6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N0 +cycloneive_lcell_comb \sdram_|Mux6~4 ( +// Equation(s): +// \sdram_|Mux6~4_combout = (\sdram_|r.state [6]) # ((!\sdram_|r.rf_pending~q & \sdram_|Equal7~2_combout )) + + .dataa(gnd), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux6~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~4 .lut_mask = 16'hFF30; +defparam \sdram_|Mux6~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N6 +cycloneive_lcell_comb \sdram_|Mux6~2 ( +// Equation(s): +// \sdram_|Mux6~2_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [8]) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & ((\sdram_|r.state [4]))) + + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~2 .lut_mask = 16'hF5AA; +defparam \sdram_|Mux6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N10 +cycloneive_lcell_comb \sdram_|Mux6~5 ( +// Equation(s): +// \sdram_|Mux6~5_combout = (\sdram_|r.state [5] & (((\sdram_|Mux6~2_combout )))) # (!\sdram_|r.state [5] & (\sdram_|Mux6~3_combout & (\sdram_|Mux6~4_combout ))) + + .dataa(\sdram_|Mux6~3_combout ), + .datab(\sdram_|Mux6~4_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|Mux6~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~5 .lut_mask = 16'hF808; +defparam \sdram_|Mux6~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N8 +cycloneive_lcell_comb \sdram_|process_0~3 ( +// Equation(s): +// \sdram_|process_0~3_combout = (\sdram_|r.wr_pending~q & \sdram_|Equal7~2_combout ) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(gnd), + .datac(\sdram_|Equal7~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|process_0~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~3 .lut_mask = 16'hA0A0; +defparam \sdram_|process_0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N14 +cycloneive_lcell_comb \sdram_|Mux6~0 ( +// Equation(s): +// \sdram_|Mux6~0_combout = (\sdram_|r.state [8] & (\sdram_|r.state [4] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|process_0~3_combout )))) # (!\sdram_|r.state [8] & (!\sdram_|r.rf_pending~q & (\sdram_|process_0~3_combout & !\sdram_|r.state [4]))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|process_0~3_combout ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~0 .lut_mask = 16'h8A10; +defparam \sdram_|Mux6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N16 +cycloneive_lcell_comb \sdram_|Mux6~1 ( +// Equation(s): +// \sdram_|Mux6~1_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] $ (((\sdram_|r.state [6]) # (\sdram_|Mux6~0_combout ))))) # (!\sdram_|r.state [5] & (\sdram_|r.state [6] & ((\sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|Mux6~0_combout ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~1 .lut_mask = 16'h46A8; +defparam \sdram_|Mux6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N24 +cycloneive_lcell_comb \sdram_|Mux6~6 ( +// Equation(s): +// \sdram_|Mux6~6_combout = (\sdram_|r.state [7] & ((\sdram_|Mux6~1_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux6~5_combout )) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux6~5_combout ), + .datad(\sdram_|Mux6~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~6 .lut_mask = 16'hFC30; +defparam \sdram_|Mux6~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y15_N25 +dffeas \sdram_|r.state[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux6~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[6] .is_wysiwyg = "true"; +defparam \sdram_|r.state[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N12 +cycloneive_lcell_comb \sdram_|r.address[3]~6 ( +// Equation(s): +// \sdram_|r.address[3]~6_combout = (!\sdram_|r.state [6] & (!\sdram_|r.state [7] & !\sdram_|r.state [8])) + + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.address[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~6 .lut_mask = 16'h0005; +defparam \sdram_|r.address[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N22 +cycloneive_lcell_comb \sdram_|Mux7~2 ( +// Equation(s): +// \sdram_|Mux7~2_combout = (!\sdram_|r.state [5] & (\sdram_|r.state [4] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|r.address[3]~6_combout )))) + + .dataa(\sdram_|r.address[3]~6_combout ), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux7~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~2 .lut_mask = 16'h3100; +defparam \sdram_|Mux7~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N12 +cycloneive_lcell_comb \sdram_|n~3 ( +// Equation(s): +// \sdram_|n~3_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q ))) + + .dataa(gnd), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|n~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|n~3 .lut_mask = 16'hFC00; +defparam \sdram_|n~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N6 +cycloneive_lcell_comb \sdram_|Mux7~3 ( +// Equation(s): +// \sdram_|Mux7~3_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [6]) # (!\sdram_|r.rd_pending~q ))) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|r.state [6]), + .datac(gnd), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux7~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~3 .lut_mask = 16'h7700; +defparam \sdram_|Mux7~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N28 +cycloneive_lcell_comb \sdram_|Mux7~4 ( +// Equation(s): +// \sdram_|Mux7~4_combout = (\sdram_|r.state [6] & (\sdram_|Mux7~3_combout & (!\sdram_|r.wr_pending~q & \sdram_|r.state [7]))) # (!\sdram_|r.state [6] & (\sdram_|Mux7~3_combout $ (((\sdram_|r.state [7]))))) + + .dataa(\sdram_|Mux7~3_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux7~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~4 .lut_mask = 16'h1922; +defparam \sdram_|Mux7~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N10 +cycloneive_lcell_comb \sdram_|Mux7~5 ( +// Equation(s): +// \sdram_|Mux7~5_combout = (\sdram_|r.state [6] & (((\sdram_|r.rf_pending~q & \sdram_|Mux7~4_combout )))) # (!\sdram_|r.state [6] & (!\sdram_|Mux7~4_combout & ((\sdram_|r.rf_pending~q ) # (!\sdram_|n~3_combout )))) + + .dataa(\sdram_|n~3_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Mux7~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux7~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~5 .lut_mask = 16'hC031; +defparam \sdram_|Mux7~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N0 +cycloneive_lcell_comb \sdram_|Mux23~0 ( +// Equation(s): +// \sdram_|Mux23~0_combout = (\sdram_|r.state [8] & \sdram_|r.state [6]) + + .dataa(gnd), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [6]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|Mux23~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~0 .lut_mask = 16'hC0C0; +defparam \sdram_|Mux23~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N24 +cycloneive_lcell_comb \sdram_|Mux13~7 ( +// Equation(s): +// \sdram_|Mux13~7_combout = (!\sdram_|r.state [4] & \sdram_|r.state [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), + .cin(gnd), + .combout(\sdram_|Mux13~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~7 .lut_mask = 16'h0F00; +defparam \sdram_|Mux13~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N20 +cycloneive_lcell_comb \sdram_|Mux10~10 ( +// Equation(s): +// \sdram_|Mux10~10_combout = (!\sdram_|r.state [8] & (((\sdram_|r.state [6]) # (\sdram_|r.rf_pending~q )) # (!\sdram_|n~3_combout ))) + + .dataa(\sdram_|n~3_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.rf_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux10~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~10 .lut_mask = 16'h3331; +defparam \sdram_|Mux10~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N18 +cycloneive_lcell_comb \sdram_|Mux7~1 ( +// Equation(s): +// \sdram_|Mux7~1_combout = (\sdram_|Mux13~7_combout & ((\sdram_|Mux23~0_combout ) # ((\sdram_|Mux10~10_combout ) # (!\sdram_|r.state [7])))) + + .dataa(\sdram_|Mux23~0_combout ), + .datab(\sdram_|Mux13~7_combout ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|Mux10~10_combout ), + .cin(gnd), + .combout(\sdram_|Mux7~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~1 .lut_mask = 16'hCC8C; +defparam \sdram_|Mux7~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N22 +cycloneive_lcell_comb \sdram_|Mux7~6 ( +// Equation(s): +// \sdram_|Mux7~6_combout = (\sdram_|Mux7~2_combout ) # ((\sdram_|Mux7~1_combout ) # ((\sdram_|Mux7~5_combout & \sdram_|r.state [8]))) + + .dataa(\sdram_|Mux7~2_combout ), + .datab(\sdram_|Mux7~5_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux7~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux7~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~6 .lut_mask = 16'hFFEA; +defparam \sdram_|Mux7~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y15_N23 +dffeas \sdram_|r.state[5] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux7~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[5] .is_wysiwyg = "true"; +defparam \sdram_|r.state[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N6 +cycloneive_lcell_comb \sdram_|Mux5~2 ( +// Equation(s): +// \sdram_|Mux5~2_combout = (\sdram_|Mux13~7_combout & ((\sdram_|r.state [6]) # ((!\sdram_|Mux4~0_combout & !\sdram_|r.state [8])))) + + .dataa(\sdram_|Mux4~0_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux13~7_combout ), + .cin(gnd), + .combout(\sdram_|Mux5~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~2 .lut_mask = 16'hCD00; +defparam \sdram_|Mux5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N18 +cycloneive_lcell_comb \sdram_|Mux5~10 ( +// Equation(s): +// \sdram_|Mux5~10_combout = (\sdram_|r.state [6] & (\sdram_|r.state [8] & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q )))) # (!\sdram_|r.state [6] & (((!\sdram_|r.state [8])))) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux5~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~10 .lut_mask = 16'hE00F; +defparam \sdram_|Mux5~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N16 +cycloneive_lcell_comb \sdram_|Mux5~3 ( +// Equation(s): +// \sdram_|Mux5~3_combout = ((\sdram_|Mux5~10_combout ) # ((!\sdram_|r.state [6] & !\sdram_|Mux4~0_combout ))) # (!\sdram_|r.state [5]) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|Mux4~0_combout ), + .datad(\sdram_|Mux5~10_combout ), + .cin(gnd), + .combout(\sdram_|Mux5~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~3 .lut_mask = 16'hFF37; +defparam \sdram_|Mux5~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N30 +cycloneive_lcell_comb \sdram_|Mux5~4 ( +// Equation(s): +// \sdram_|Mux5~4_combout = (\sdram_|r.state [7] & ((\sdram_|Mux5~2_combout ) # ((\sdram_|Mux5~3_combout & \sdram_|r.state [4])))) + + .dataa(\sdram_|Mux5~2_combout ), + .datab(\sdram_|Mux5~3_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux5~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~4 .lut_mask = 16'hEA00; +defparam \sdram_|Mux5~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N18 +cycloneive_lcell_comb \sdram_|Mux5~7 ( +// Equation(s): +// \sdram_|Mux5~7_combout = (!\sdram_|r.state [8] & (\sdram_|r.state [4] & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.rd_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux5~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~7 .lut_mask = 16'h4440; +defparam \sdram_|Mux5~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N4 +cycloneive_lcell_comb \sdram_|Mux5~8 ( +// Equation(s): +// \sdram_|Mux5~8_combout = (!\sdram_|r.state [6] & ((\sdram_|r.state [7]) # ((\sdram_|Mux5~7_combout & !\sdram_|r.rf_pending~q )))) + + .dataa(\sdram_|Mux5~7_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux5~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~8 .lut_mask = 16'h3302; +defparam \sdram_|Mux5~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N26 +cycloneive_lcell_comb \sdram_|Mux5~5 ( +// Equation(s): +// \sdram_|Mux5~5_combout = (!\sdram_|r.state [7] & (((\sdram_|r.rf_pending~q ) # (!\sdram_|Equal7~2_combout )) # (!\sdram_|r.rd_pending~q ))) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux5~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~5 .lut_mask = 16'h00DF; +defparam \sdram_|Mux5~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N12 +cycloneive_lcell_comb \sdram_|Mux5~6 ( +// Equation(s): +// \sdram_|Mux5~6_combout = (\sdram_|Mux9~8_combout & ((\sdram_|Mux5~5_combout ) # ((!\sdram_|r.state [6] & \sdram_|process_0~3_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|process_0~3_combout ), + .datac(\sdram_|Mux9~8_combout ), + .datad(\sdram_|Mux5~5_combout ), + .cin(gnd), + .combout(\sdram_|Mux5~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~6 .lut_mask = 16'hF040; +defparam \sdram_|Mux5~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N20 +cycloneive_lcell_comb \sdram_|Mux5~9 ( +// Equation(s): +// \sdram_|Mux5~9_combout = (\sdram_|Mux5~4_combout ) # ((!\sdram_|r.state [5] & ((\sdram_|Mux5~8_combout ) # (\sdram_|Mux5~6_combout )))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|Mux5~4_combout ), + .datac(\sdram_|Mux5~8_combout ), + .datad(\sdram_|Mux5~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux5~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~9 .lut_mask = 16'hDDDC; +defparam \sdram_|Mux5~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y15_N21 +dffeas \sdram_|r.state[7] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux5~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[7] .is_wysiwyg = "true"; +defparam \sdram_|r.state[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N8 +cycloneive_lcell_comb \sdram_|n~2 ( +// Equation(s): +// \sdram_|n~2_combout = (\sdram_|r.rd_pending~q ) # ((\sdram_|r.rf_pending~q ) # (\sdram_|r.wr_pending~q )) + + .dataa(gnd), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|n~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|n~2 .lut_mask = 16'hFFFC; +defparam \sdram_|n~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N8 +cycloneive_lcell_comb \sdram_|Mux8~3 ( +// Equation(s): +// \sdram_|Mux8~3_combout = (\sdram_|r.state [5] & (\sdram_|n~2_combout & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & (((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) + + .dataa(\sdram_|n~2_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux8~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~3 .lut_mask = 16'h8C2F; +defparam \sdram_|Mux8~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N6 +cycloneive_lcell_comb \sdram_|Mux8~4 ( +// Equation(s): +// \sdram_|Mux8~4_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [6] $ (\sdram_|Mux8~3_combout )))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [4] & ((\sdram_|r.state [6]) # (\sdram_|Mux8~3_combout )))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|Mux8~3_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux8~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~4 .lut_mask = 16'h3C54; +defparam \sdram_|Mux8~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N4 +cycloneive_lcell_comb \sdram_|Mux9~10 ( +// Equation(s): +// \sdram_|Mux9~10_combout = (!\sdram_|r.state [4] & ((!\sdram_|r.state [8]) # (!\sdram_|Mux9~9_combout ))) + + .dataa(gnd), + .datab(\sdram_|Mux9~9_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux9~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~10 .lut_mask = 16'h003F; +defparam \sdram_|Mux9~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N28 +cycloneive_lcell_comb \sdram_|r.init_counter[0]~0 ( +// Equation(s): +// \sdram_|r.init_counter[0]~0_combout = !\sdram_|r.init_counter [0] + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.init_counter [0]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.init_counter[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.init_counter[0]~0 .lut_mask = 16'h0F0F; +defparam \sdram_|r.init_counter[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y7_N29 +dffeas \sdram_|r.init_counter[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.init_counter[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[0] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N2 +cycloneive_lcell_comb \sdram_|Add1~1 ( +// Equation(s): +// \sdram_|Add1~1_cout = CARRY(\sdram_|r.init_counter [0]) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\sdram_|Add1~1_cout )); +// synopsys translate_off +defparam \sdram_|Add1~1 .lut_mask = 16'h00CC; +defparam \sdram_|Add1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N4 +cycloneive_lcell_comb \sdram_|Add1~2 ( +// Equation(s): +// \sdram_|Add1~2_combout = (\sdram_|r.init_counter [1] & (\sdram_|Add1~1_cout & VCC)) # (!\sdram_|r.init_counter [1] & (!\sdram_|Add1~1_cout )) +// \sdram_|Add1~3 = CARRY((!\sdram_|r.init_counter [1] & !\sdram_|Add1~1_cout )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~1_cout ), + .combout(\sdram_|Add1~2_combout ), + .cout(\sdram_|Add1~3 )); +// synopsys translate_off +defparam \sdram_|Add1~2 .lut_mask = 16'hC303; +defparam \sdram_|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N5 +dffeas \sdram_|r.init_counter[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[1] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N6 +cycloneive_lcell_comb \sdram_|Add1~4 ( +// Equation(s): +// \sdram_|Add1~4_combout = (\sdram_|r.init_counter [2] & ((GND) # (!\sdram_|Add1~3 ))) # (!\sdram_|r.init_counter [2] & (\sdram_|Add1~3 $ (GND))) +// \sdram_|Add1~5 = CARRY((\sdram_|r.init_counter [2]) # (!\sdram_|Add1~3 )) + + .dataa(\sdram_|r.init_counter [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~3 ), + .combout(\sdram_|Add1~4_combout ), + .cout(\sdram_|Add1~5 )); +// synopsys translate_off +defparam \sdram_|Add1~4 .lut_mask = 16'h5AAF; +defparam \sdram_|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N7 +dffeas \sdram_|r.init_counter[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[2] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N8 +cycloneive_lcell_comb \sdram_|Add1~6 ( +// Equation(s): +// \sdram_|Add1~6_combout = (\sdram_|r.init_counter [3] & (!\sdram_|Add1~5 )) # (!\sdram_|r.init_counter [3] & (\sdram_|Add1~5 & VCC)) +// \sdram_|Add1~7 = CARRY((\sdram_|r.init_counter [3] & !\sdram_|Add1~5 )) + + .dataa(\sdram_|r.init_counter [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~5 ), + .combout(\sdram_|Add1~6_combout ), + .cout(\sdram_|Add1~7 )); +// synopsys translate_off +defparam \sdram_|Add1~6 .lut_mask = 16'h5A0A; +defparam \sdram_|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N2 +cycloneive_lcell_comb \sdram_|r.init_counter[3]~1 ( +// Equation(s): +// \sdram_|r.init_counter[3]~1_combout = !\sdram_|Add1~6_combout + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|Add1~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.init_counter[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.init_counter[3]~1 .lut_mask = 16'h0F0F; +defparam \sdram_|r.init_counter[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y3_N3 +dffeas \sdram_|r.init_counter[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.init_counter[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[3] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N10 +cycloneive_lcell_comb \sdram_|Add1~8 ( +// Equation(s): +// \sdram_|Add1~8_combout = (\sdram_|r.init_counter [4] & ((GND) # (!\sdram_|Add1~7 ))) # (!\sdram_|r.init_counter [4] & (\sdram_|Add1~7 $ (GND))) +// \sdram_|Add1~9 = CARRY((\sdram_|r.init_counter [4]) # (!\sdram_|Add1~7 )) + + .dataa(\sdram_|r.init_counter [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~7 ), + .combout(\sdram_|Add1~8_combout ), + .cout(\sdram_|Add1~9 )); +// synopsys translate_off +defparam \sdram_|Add1~8 .lut_mask = 16'h5AAF; +defparam \sdram_|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N11 +dffeas \sdram_|r.init_counter[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[4] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N12 +cycloneive_lcell_comb \sdram_|Add1~10 ( +// Equation(s): +// \sdram_|Add1~10_combout = (\sdram_|r.init_counter [5] & (\sdram_|Add1~9 & VCC)) # (!\sdram_|r.init_counter [5] & (!\sdram_|Add1~9 )) +// \sdram_|Add1~11 = CARRY((!\sdram_|r.init_counter [5] & !\sdram_|Add1~9 )) + + .dataa(\sdram_|r.init_counter [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~9 ), + .combout(\sdram_|Add1~10_combout ), + .cout(\sdram_|Add1~11 )); +// synopsys translate_off +defparam \sdram_|Add1~10 .lut_mask = 16'hA505; +defparam \sdram_|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N13 +dffeas \sdram_|r.init_counter[5] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[5] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N14 +cycloneive_lcell_comb \sdram_|Add1~12 ( +// Equation(s): +// \sdram_|Add1~12_combout = (\sdram_|r.init_counter [6] & ((GND) # (!\sdram_|Add1~11 ))) # (!\sdram_|r.init_counter [6] & (\sdram_|Add1~11 $ (GND))) +// \sdram_|Add1~13 = CARRY((\sdram_|r.init_counter [6]) # (!\sdram_|Add1~11 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~11 ), + .combout(\sdram_|Add1~12_combout ), + .cout(\sdram_|Add1~13 )); +// synopsys translate_off +defparam \sdram_|Add1~12 .lut_mask = 16'h3CCF; +defparam \sdram_|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N15 +dffeas \sdram_|r.init_counter[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[6] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N16 +cycloneive_lcell_comb \sdram_|Add1~14 ( +// Equation(s): +// \sdram_|Add1~14_combout = (\sdram_|r.init_counter [7] & (\sdram_|Add1~13 & VCC)) # (!\sdram_|r.init_counter [7] & (!\sdram_|Add1~13 )) +// \sdram_|Add1~15 = CARRY((!\sdram_|r.init_counter [7] & !\sdram_|Add1~13 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~13 ), + .combout(\sdram_|Add1~14_combout ), + .cout(\sdram_|Add1~15 )); +// synopsys translate_off +defparam \sdram_|Add1~14 .lut_mask = 16'hC303; +defparam \sdram_|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N17 +dffeas \sdram_|r.init_counter[7] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~14_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[7] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N18 +cycloneive_lcell_comb \sdram_|Add1~16 ( +// Equation(s): +// \sdram_|Add1~16_combout = (\sdram_|r.init_counter [8] & ((GND) # (!\sdram_|Add1~15 ))) # (!\sdram_|r.init_counter [8] & (\sdram_|Add1~15 $ (GND))) +// \sdram_|Add1~17 = CARRY((\sdram_|r.init_counter [8]) # (!\sdram_|Add1~15 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~15 ), + .combout(\sdram_|Add1~16_combout ), + .cout(\sdram_|Add1~17 )); +// synopsys translate_off +defparam \sdram_|Add1~16 .lut_mask = 16'h3CCF; +defparam \sdram_|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N19 +dffeas \sdram_|r.init_counter[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[8] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N20 +cycloneive_lcell_comb \sdram_|Add1~18 ( +// Equation(s): +// \sdram_|Add1~18_combout = (\sdram_|r.init_counter [9] & (\sdram_|Add1~17 & VCC)) # (!\sdram_|r.init_counter [9] & (!\sdram_|Add1~17 )) +// \sdram_|Add1~19 = CARRY((!\sdram_|r.init_counter [9] & !\sdram_|Add1~17 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [9]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~17 ), + .combout(\sdram_|Add1~18_combout ), + .cout(\sdram_|Add1~19 )); +// synopsys translate_off +defparam \sdram_|Add1~18 .lut_mask = 16'hC303; +defparam \sdram_|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N21 +dffeas \sdram_|r.init_counter[9] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[9] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N22 +cycloneive_lcell_comb \sdram_|Add1~20 ( +// Equation(s): +// \sdram_|Add1~20_combout = (\sdram_|r.init_counter [10] & ((GND) # (!\sdram_|Add1~19 ))) # (!\sdram_|r.init_counter [10] & (\sdram_|Add1~19 $ (GND))) +// \sdram_|Add1~21 = CARRY((\sdram_|r.init_counter [10]) # (!\sdram_|Add1~19 )) + + .dataa(\sdram_|r.init_counter [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~19 ), + .combout(\sdram_|Add1~20_combout ), + .cout(\sdram_|Add1~21 )); +// synopsys translate_off +defparam \sdram_|Add1~20 .lut_mask = 16'h5AAF; +defparam \sdram_|Add1~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N23 +dffeas \sdram_|r.init_counter[10] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~20_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[10] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N22 +cycloneive_lcell_comb \sdram_|Equal2~0 ( +// Equation(s): +// \sdram_|Equal2~0_combout = (!\sdram_|r.init_counter [9] & (!\sdram_|r.init_counter [8] & (!\sdram_|r.init_counter [4] & !\sdram_|r.init_counter [10]))) + + .dataa(\sdram_|r.init_counter [9]), + .datab(\sdram_|r.init_counter [8]), + .datac(\sdram_|r.init_counter [4]), + .datad(\sdram_|r.init_counter [10]), + .cin(gnd), + .combout(\sdram_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~0 .lut_mask = 16'h0001; +defparam \sdram_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N0 +cycloneive_lcell_comb \sdram_|Equal2~1 ( +// Equation(s): +// \sdram_|Equal2~1_combout = (!\sdram_|r.init_counter [6] & (!\sdram_|r.init_counter [5] & \sdram_|r.init_counter [3])) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [6]), + .datac(\sdram_|r.init_counter [5]), + .datad(\sdram_|r.init_counter [3]), + .cin(gnd), + .combout(\sdram_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~1 .lut_mask = 16'h0300; +defparam \sdram_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N24 +cycloneive_lcell_comb \sdram_|Add1~22 ( +// Equation(s): +// \sdram_|Add1~22_combout = (\sdram_|r.init_counter [11] & (\sdram_|Add1~21 & VCC)) # (!\sdram_|r.init_counter [11] & (!\sdram_|Add1~21 )) +// \sdram_|Add1~23 = CARRY((!\sdram_|r.init_counter [11] & !\sdram_|Add1~21 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [11]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~21 ), + .combout(\sdram_|Add1~22_combout ), + .cout(\sdram_|Add1~23 )); +// synopsys translate_off +defparam \sdram_|Add1~22 .lut_mask = 16'hC303; +defparam \sdram_|Add1~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N25 +dffeas \sdram_|r.init_counter[11] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[11] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N26 +cycloneive_lcell_comb \sdram_|Add1~24 ( +// Equation(s): +// \sdram_|Add1~24_combout = (\sdram_|r.init_counter [12] & ((GND) # (!\sdram_|Add1~23 ))) # (!\sdram_|r.init_counter [12] & (\sdram_|Add1~23 $ (GND))) +// \sdram_|Add1~25 = CARRY((\sdram_|r.init_counter [12]) # (!\sdram_|Add1~23 )) + + .dataa(\sdram_|r.init_counter [12]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~23 ), + .combout(\sdram_|Add1~24_combout ), + .cout(\sdram_|Add1~25 )); +// synopsys translate_off +defparam \sdram_|Add1~24 .lut_mask = 16'h5AAF; +defparam \sdram_|Add1~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N27 +dffeas \sdram_|r.init_counter[12] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[12] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N28 +cycloneive_lcell_comb \sdram_|Add1~26 ( +// Equation(s): +// \sdram_|Add1~26_combout = (\sdram_|r.init_counter [13] & (\sdram_|Add1~25 & VCC)) # (!\sdram_|r.init_counter [13] & (!\sdram_|Add1~25 )) +// \sdram_|Add1~27 = CARRY((!\sdram_|r.init_counter [13] & !\sdram_|Add1~25 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [13]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~25 ), + .combout(\sdram_|Add1~26_combout ), + .cout(\sdram_|Add1~27 )); +// synopsys translate_off +defparam \sdram_|Add1~26 .lut_mask = 16'hC303; +defparam \sdram_|Add1~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N29 +dffeas \sdram_|r.init_counter[13] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~26_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[13] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N30 +cycloneive_lcell_comb \sdram_|Add1~28 ( +// Equation(s): +// \sdram_|Add1~28_combout = \sdram_|r.init_counter [14] $ (\sdram_|Add1~27 ) + + .dataa(\sdram_|r.init_counter [14]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sdram_|Add1~27 ), + .combout(\sdram_|Add1~28_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Add1~28 .lut_mask = 16'h5A5A; +defparam \sdram_|Add1~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N31 +dffeas \sdram_|r.init_counter[14] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~28_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[14] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N0 +cycloneive_lcell_comb \sdram_|process_0~5 ( +// Equation(s): +// \sdram_|process_0~5_combout = (!\sdram_|r.init_counter [14] & (!\sdram_|r.init_counter [11] & (!\sdram_|r.init_counter [12] & !\sdram_|r.init_counter [13]))) + + .dataa(\sdram_|r.init_counter [14]), + .datab(\sdram_|r.init_counter [11]), + .datac(\sdram_|r.init_counter [12]), + .datad(\sdram_|r.init_counter [13]), + .cin(gnd), + .combout(\sdram_|process_0~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~5 .lut_mask = 16'h0001; +defparam \sdram_|process_0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N6 +cycloneive_lcell_comb \sdram_|Equal2~2 ( +// Equation(s): +// \sdram_|Equal2~2_combout = (\sdram_|Equal2~0_combout & (\sdram_|Equal2~1_combout & (\sdram_|process_0~5_combout & !\sdram_|r.init_counter [2]))) + + .dataa(\sdram_|Equal2~0_combout ), + .datab(\sdram_|Equal2~1_combout ), + .datac(\sdram_|process_0~5_combout ), + .datad(\sdram_|r.init_counter [2]), + .cin(gnd), + .combout(\sdram_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~2 .lut_mask = 16'h0080; +defparam \sdram_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N10 +cycloneive_lcell_comb \sdram_|Mux9~11 ( +// Equation(s): +// \sdram_|Mux9~11_combout = (!\sdram_|r.init_counter [1] & (\sdram_|r.init_counter [0] & !\sdram_|r.init_counter [7])) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [0]), + .datac(gnd), + .datad(\sdram_|r.init_counter [7]), + .cin(gnd), + .combout(\sdram_|Mux9~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~11 .lut_mask = 16'h0044; +defparam \sdram_|Mux9~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N24 +cycloneive_lcell_comb \sdram_|Mux9~12 ( +// Equation(s): +// \sdram_|Mux9~12_combout = (\sdram_|r.state [4] & (!\sdram_|n~2_combout )) # (!\sdram_|r.state [4] & (((\sdram_|Equal2~2_combout & \sdram_|Mux9~11_combout )))) + + .dataa(\sdram_|n~2_combout ), + .datab(\sdram_|Equal2~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|Mux9~11_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~12 .lut_mask = 16'h5C50; +defparam \sdram_|Mux9~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N0 +cycloneive_lcell_comb \sdram_|Mux9~13 ( +// Equation(s): +// \sdram_|Mux9~13_combout = (\sdram_|r.state [8] & (!\sdram_|r.state [4] & (\sdram_|n~2_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux9~12_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|n~2_combout ), + .datad(\sdram_|Mux9~12_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~13_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~13 .lut_mask = 16'h7520; +defparam \sdram_|Mux9~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N2 +cycloneive_lcell_comb \sdram_|Mux8~0 ( +// Equation(s): +// \sdram_|Mux8~0_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [5]) # ((\sdram_|Mux9~10_combout )))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [5] & ((\sdram_|Mux9~13_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|Mux9~10_combout ), + .datad(\sdram_|Mux9~13_combout ), + .cin(gnd), + .combout(\sdram_|Mux8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~0 .lut_mask = 16'hB9A8; +defparam \sdram_|Mux8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N16 +cycloneive_lcell_comb \sdram_|Mux8~1 ( +// Equation(s): +// \sdram_|Mux8~1_combout = (\sdram_|r.state [5] & (((!\sdram_|r.state [8] & \sdram_|Mux8~0_combout )) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [5] & (((\sdram_|Mux8~0_combout )))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|Mux8~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux8~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~1 .lut_mask = 16'h7F50; +defparam \sdram_|Mux8~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N20 +cycloneive_lcell_comb \sdram_|Mux8~2 ( +// Equation(s): +// \sdram_|Mux8~2_combout = (\sdram_|r.state [7] & (\sdram_|Mux8~4_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux8~1_combout ))) + + .dataa(\sdram_|r.state [7]), + .datab(gnd), + .datac(\sdram_|Mux8~4_combout ), + .datad(\sdram_|Mux8~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux8~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~2 .lut_mask = 16'hF5A0; +defparam \sdram_|Mux8~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y15_N21 +dffeas \sdram_|r.state[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux8~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[4] .is_wysiwyg = "true"; +defparam \sdram_|r.state[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N4 +cycloneive_lcell_comb \sdram_|Mux72~0 ( +// Equation(s): +// \sdram_|Mux72~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [0]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux72~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux72~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux72~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N2 +cycloneive_lcell_comb \sdram_|Mux72~1 ( +// Equation(s): +// \sdram_|Mux72~1_combout = (\sdram_|Mux72~0_combout & ((\D[0]~64_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\sdram_|Mux72~0_combout ), + .datad(\D[0]~64_combout ), + .cin(gnd), + .combout(\sdram_|Mux72~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux72~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux72~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N0 +cycloneive_lcell_comb \sdram_|Mux84~0 ( +// Equation(s): +// \sdram_|Mux84~0_combout = (\sdram_|r.state [5]) # (\sdram_|r.state [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux84~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux84~0 .lut_mask = 16'hFFF0; +defparam \sdram_|Mux84~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N2 +cycloneive_lcell_comb \sdram_|Mux84~1 ( +// Equation(s): +// \sdram_|Mux84~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [7] & (!\sdram_|r.state [8] & \sdram_|Mux84~0_combout ))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [7] & (\sdram_|r.state [8] & !\sdram_|Mux84~0_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux84~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux84~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux84~1 .lut_mask = 16'h0810; +defparam \sdram_|Mux84~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N16 +cycloneive_lcell_comb \sdram_|Mux3~0 ( +// Equation(s): +// \sdram_|Mux3~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [1]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux3~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N18 +cycloneive_lcell_comb \sdram_|Mux3~1 ( +// Equation(s): +// \sdram_|Mux3~1_combout = (\sdram_|Mux3~0_combout & ((\D[1]~40_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\sdram_|Mux3~0_combout ), + .datad(\D[1]~40_combout ), + .cin(gnd), + .combout(\sdram_|Mux3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux3~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N0 +cycloneive_lcell_comb \sdram_|Mux2~0 ( +// Equation(s): +// \sdram_|Mux2~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [2]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux2~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N30 +cycloneive_lcell_comb \sdram_|Mux2~1 ( +// Equation(s): +// \sdram_|Mux2~1_combout = (\sdram_|Mux2~0_combout & ((\D[2]~52_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\sdram_|Mux2~0_combout ), + .datad(\D[2]~52_combout ), + .cin(gnd), + .combout(\sdram_|Mux2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux2~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N28 +cycloneive_lcell_comb \sdram_|Mux1~0 ( +// Equation(s): +// \sdram_|Mux1~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [3]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux1~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N10 +cycloneive_lcell_comb \sdram_|Mux1~1 ( +// Equation(s): +// \sdram_|Mux1~1_combout = (\sdram_|Mux1~0_combout & ((\D[3]~108_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\D[3]~108_combout ), + .datad(\sdram_|Mux1~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux1~1 .lut_mask = 16'hF100; +defparam \sdram_|Mux1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N12 +cycloneive_lcell_comb \sdram_|Mux0~0 ( +// Equation(s): +// \sdram_|Mux0~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [4]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux0~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N26 +cycloneive_lcell_comb \sdram_|Mux0~1 ( +// Equation(s): +// \sdram_|Mux0~1_combout = (\sdram_|Mux0~0_combout & ((\D[4]~110_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\sdram_|Mux0~0_combout ), + .datad(\D[4]~110_combout ), + .cin(gnd), + .combout(\sdram_|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux0~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N8 +cycloneive_lcell_comb \sdram_|Mux73~0 ( +// Equation(s): +// \sdram_|Mux73~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [5]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux73~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux73~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux73~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N14 +cycloneive_lcell_comb \sdram_|Mux73~1 ( +// Equation(s): +// \sdram_|Mux73~1_combout = (\sdram_|Mux73~0_combout & ((\D[5]~112_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\sdram_|Mux73~0_combout ), + .datad(\D[5]~112_combout ), + .cin(gnd), + .combout(\sdram_|Mux73~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux73~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux73~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N24 +cycloneive_lcell_comb \sdram_|Mux74~0 ( +// Equation(s): +// \sdram_|Mux74~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [6]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux74~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux74~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux74~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N6 +cycloneive_lcell_comb \sdram_|Mux74~1 ( +// Equation(s): +// \sdram_|Mux74~1_combout = (\sdram_|Mux74~0_combout & ((\D[6]~114_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\sdram_|Mux74~0_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[6]~114_combout ), + .cin(gnd), + .combout(\sdram_|Mux74~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux74~1 .lut_mask = 16'hCC04; +defparam \sdram_|Mux74~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y4_N28 +cycloneive_lcell_comb \sdram_|Mux75~0 ( +// Equation(s): +// \sdram_|Mux75~0_combout = (\sdram_|r.state [4] & \D[7]~117_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\D[7]~117_combout ), + .cin(gnd), + .combout(\sdram_|Mux75~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux75~0 .lut_mask = 16'hF000; +defparam \sdram_|Mux75~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y32_N8 cycloneive_lcell_comb \ula_|i2s_intf_|mclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|mclk_r~0_combout = !\ula_|i2s_intf_|mclk_r~_Duplicate_1_q @@ -55715,7 +59007,7 @@ defparam \ula_|i2s_intf_|mclk_r~0 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|mclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y23_N17 +// Location: FF_X20_Y32_N9 dffeas \ula_|i2s_intf_|mclk_r~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|mclk_r~0_combout ), @@ -55753,24 +59045,24 @@ defparam \ula_|i2s_intf_|mclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|mclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N6 +// Location: LCCOMB_X20_Y31_N12 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~1 ( // Equation(s): // \ula_|i2s_intf_|Add0~1_cout = CARRY(!\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ) - .dataa(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), .datac(gnd), .datad(vcc), .cin(gnd), .combout(), .cout(\ula_|i2s_intf_|Add0~1_cout )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0033; defparam \ula_|i2s_intf_|Add0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N8 +// Location: LCCOMB_X20_Y31_N14 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~2 ( // Equation(s): // \ula_|i2s_intf_|Add0~2_combout = (\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Add0~1_cout & VCC)) # (!\ula_|i2s_intf_|lrdivider [1] & (!\ula_|i2s_intf_|Add0~1_cout )) @@ -55788,24 +59080,24 @@ defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hC303; defparam \ula_|i2s_intf_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N28 +// Location: LCCOMB_X20_Y31_N0 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~2 ( // Equation(s): -// \ula_|i2s_intf_|lrdivider~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~2_combout ) +// \ula_|i2s_intf_|lrdivider~2_combout = (\ula_|i2s_intf_|Add0~2_combout & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(gnd), .datab(gnd), .datac(\ula_|i2s_intf_|Add0~2_combout ), - .datad(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h5050; +defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h00F0; defparam \ula_|i2s_intf_|lrdivider~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N29 +// Location: FF_X20_Y31_N1 dffeas \ula_|i2s_intf_|lrdivider[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~2_combout ), @@ -55824,7 +59116,7 @@ defparam \ula_|i2s_intf_|lrdivider[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N10 +// Location: LCCOMB_X20_Y31_N16 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~4 ( // Equation(s): // \ula_|i2s_intf_|Add0~4_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|Add0~3 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add0~3 ))) @@ -55842,24 +59134,24 @@ defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hA55F; defparam \ula_|i2s_intf_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X30_Y23_N6 +// Location: LCCOMB_X21_Y31_N6 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[2]~8 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[2]~8_combout = !\ula_|i2s_intf_|Add0~4_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~4_combout ), + .datac(\ula_|i2s_intf_|Add0~4_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[2]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[2]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y23_N7 +// Location: FF_X21_Y31_N7 dffeas \ula_|i2s_intf_|lrdivider[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[2]~8_combout ), @@ -55878,42 +59170,42 @@ defparam \ula_|i2s_intf_|lrdivider[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N12 +// Location: LCCOMB_X20_Y31_N18 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~6 ( // Equation(s): // \ula_|i2s_intf_|Add0~6_combout = (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|Add0~5 )) # (!\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|Add0~5 & VCC)) // \ula_|i2s_intf_|Add0~7 = CARRY((\ula_|i2s_intf_|lrdivider [3] & !\ula_|i2s_intf_|Add0~5 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [3]), + .dataa(\ula_|i2s_intf_|lrdivider [3]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~5 ), .combout(\ula_|i2s_intf_|Add0~6_combout ), .cout(\ula_|i2s_intf_|Add0~7 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h3C0C; +defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h5A0A; defparam \ula_|i2s_intf_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N6 +// Location: LCCOMB_X20_Y32_N30 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[3]~7 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[3]~7_combout = !\ula_|i2s_intf_|Add0~6_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~6_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~6_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[3]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[3]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N7 +// Location: FF_X20_Y32_N31 dffeas \ula_|i2s_intf_|lrdivider[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[3]~7_combout ), @@ -55932,7 +59224,7 @@ defparam \ula_|i2s_intf_|lrdivider[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N14 +// Location: LCCOMB_X20_Y31_N20 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~8 ( // Equation(s): // \ula_|i2s_intf_|Add0~8_combout = (\ula_|i2s_intf_|lrdivider [4] & ((GND) # (!\ula_|i2s_intf_|Add0~7 ))) # (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|Add0~7 $ (GND))) @@ -55950,24 +59242,24 @@ defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N4 +// Location: LCCOMB_X20_Y31_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~1 ( // Equation(s): -// \ula_|i2s_intf_|lrdivider~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~8_combout ) +// \ula_|i2s_intf_|lrdivider~1_combout = (\ula_|i2s_intf_|Add0~8_combout & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~8_combout ), - .datad(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|Add0~8_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h5050; +defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h00CC; defparam \ula_|i2s_intf_|lrdivider~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N5 +// Location: FF_X20_Y31_N5 dffeas \ula_|i2s_intf_|lrdivider[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~1_combout ), @@ -55986,25 +59278,25 @@ defparam \ula_|i2s_intf_|lrdivider[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N16 +// Location: LCCOMB_X20_Y31_N22 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~10 ( // Equation(s): // \ula_|i2s_intf_|Add0~10_combout = (\ula_|i2s_intf_|lrdivider [5] & (!\ula_|i2s_intf_|Add0~9 )) # (!\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|Add0~9 & VCC)) // \ula_|i2s_intf_|Add0~11 = CARRY((\ula_|i2s_intf_|lrdivider [5] & !\ula_|i2s_intf_|Add0~9 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [5]), + .dataa(\ula_|i2s_intf_|lrdivider [5]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~9 ), .combout(\ula_|i2s_intf_|Add0~10_combout ), .cout(\ula_|i2s_intf_|Add0~11 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h3C0C; +defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h5A0A; defparam \ula_|i2s_intf_|Add0~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N2 +// Location: LCCOMB_X21_Y31_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[5]~6 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[5]~6_combout = !\ula_|i2s_intf_|Add0~10_combout @@ -56021,7 +59313,7 @@ defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[5]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N3 +// Location: FF_X21_Y31_N5 dffeas \ula_|i2s_intf_|lrdivider[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[5]~6_combout ), @@ -56040,7 +59332,7 @@ defparam \ula_|i2s_intf_|lrdivider[5] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N26 +// Location: LCCOMB_X20_Y31_N10 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~1 ( // Equation(s): // \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [2] & (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|lrdivider [3] & \ula_|i2s_intf_|lrdivider [5]))) @@ -56057,25 +59349,25 @@ defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h2000; defparam \ula_|i2s_intf_|Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N18 +// Location: LCCOMB_X20_Y31_N24 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~12 ( // Equation(s): // \ula_|i2s_intf_|Add0~12_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|Add0~11 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [6] & ((GND) # (!\ula_|i2s_intf_|Add0~11 ))) // \ula_|i2s_intf_|Add0~13 = CARRY((!\ula_|i2s_intf_|Add0~11 ) # (!\ula_|i2s_intf_|lrdivider [6])) - .dataa(\ula_|i2s_intf_|lrdivider [6]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [6]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~11 ), .combout(\ula_|i2s_intf_|Add0~12_combout ), .cout(\ula_|i2s_intf_|Add0~13 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hC33F; defparam \ula_|i2s_intf_|Add0~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N26 +// Location: LCCOMB_X21_Y31_N22 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[6]~5 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[6]~5_combout = !\ula_|i2s_intf_|Add0~12_combout @@ -56092,7 +59384,7 @@ defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[6]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N27 +// Location: FF_X21_Y31_N23 dffeas \ula_|i2s_intf_|lrdivider[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[6]~5_combout ), @@ -56111,7 +59403,7 @@ defparam \ula_|i2s_intf_|lrdivider[6] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N20 +// Location: LCCOMB_X20_Y31_N26 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~14 ( // Equation(s): // \ula_|i2s_intf_|Add0~14_combout = (\ula_|i2s_intf_|lrdivider [7] & (!\ula_|i2s_intf_|Add0~13 )) # (!\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|Add0~13 & VCC)) @@ -56129,24 +59421,24 @@ defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h5A0A; defparam \ula_|i2s_intf_|Add0~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X30_Y23_N4 +// Location: LCCOMB_X21_Y31_N20 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[7]~4 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[7]~4_combout = !\ula_|i2s_intf_|Add0~14_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~14_combout ), + .datac(\ula_|i2s_intf_|Add0~14_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[7]~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[7]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y23_N5 +// Location: FF_X21_Y31_N21 dffeas \ula_|i2s_intf_|lrdivider[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[7]~4_combout ), @@ -56165,42 +59457,42 @@ defparam \ula_|i2s_intf_|lrdivider[7] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N22 +// Location: LCCOMB_X20_Y31_N28 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~16 ( // Equation(s): // \ula_|i2s_intf_|Add0~16_combout = (\ula_|i2s_intf_|lrdivider [8] & ((GND) # (!\ula_|i2s_intf_|Add0~15 ))) # (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|Add0~15 $ (GND))) // \ula_|i2s_intf_|Add0~17 = CARRY((\ula_|i2s_intf_|lrdivider [8]) # (!\ula_|i2s_intf_|Add0~15 )) - .dataa(\ula_|i2s_intf_|lrdivider [8]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [8]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~15 ), .combout(\ula_|i2s_intf_|Add0~16_combout ), .cout(\ula_|i2s_intf_|Add0~17 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h5AAF; +defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|Add0~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N16 +// Location: LCCOMB_X20_Y31_N8 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~0 ( // Equation(s): // \ula_|i2s_intf_|lrdivider~0_combout = (\ula_|i2s_intf_|Add0~16_combout & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), .datab(\ula_|i2s_intf_|Add0~16_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h0C0C; +defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h00CC; defparam \ula_|i2s_intf_|lrdivider~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N17 +// Location: FF_X20_Y31_N9 dffeas \ula_|i2s_intf_|lrdivider[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~0_combout ), @@ -56219,7 +59511,7 @@ defparam \ula_|i2s_intf_|lrdivider[8] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N24 +// Location: LCCOMB_X20_Y31_N30 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~18 ( // Equation(s): // \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|Add0~17 $ (\ula_|i2s_intf_|lrdivider [9]) @@ -56236,24 +59528,24 @@ defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h0FF0; defparam \ula_|i2s_intf_|Add0~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N24 +// Location: LCCOMB_X19_Y31_N24 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[9]~3 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[9]~3_combout = !\ula_|i2s_intf_|Add0~18_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~18_combout ), + .datac(\ula_|i2s_intf_|Add0~18_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[9]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[9]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N25 +// Location: FF_X19_Y31_N25 dffeas \ula_|i2s_intf_|lrdivider[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[9]~3_combout ), @@ -56272,32 +59564,32 @@ defparam \ula_|i2s_intf_|lrdivider[9] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N0 +// Location: LCCOMB_X20_Y31_N6 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~0 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~0_combout = (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|lrdivider [9] & (\ula_|i2s_intf_|lrdivider [6] & \ula_|i2s_intf_|lrdivider [7]))) +// \ula_|i2s_intf_|Equal0~0_combout = (\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|lrdivider [9] & (!\ula_|i2s_intf_|lrdivider [8] & \ula_|i2s_intf_|lrdivider [6]))) - .dataa(\ula_|i2s_intf_|lrdivider [8]), + .dataa(\ula_|i2s_intf_|lrdivider [7]), .datab(\ula_|i2s_intf_|lrdivider [9]), - .datac(\ula_|i2s_intf_|lrdivider [6]), - .datad(\ula_|i2s_intf_|lrdivider [7]), + .datac(\ula_|i2s_intf_|lrdivider [8]), + .datad(\ula_|i2s_intf_|lrdivider [6]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h4000; +defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h0800; defparam \ula_|i2s_intf_|Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N30 +// Location: LCCOMB_X20_Y31_N2 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~2 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & \ula_|i2s_intf_|Equal0~0_combout ))) +// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Equal0~0_combout & \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ))) .dataa(\ula_|i2s_intf_|Equal0~1_combout ), .datab(\ula_|i2s_intf_|lrdivider [1]), - .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|Equal0~0_combout ), + .datac(\ula_|i2s_intf_|Equal0~0_combout ), + .datad(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~2_combout ), .cout()); @@ -56306,32 +59598,15 @@ defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h2000; defparam \ula_|i2s_intf_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder ( -// Equation(s): -// \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout = \ula_|i2s_intf_|lrclk_r~0_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .lut_mask = 16'hFF00; -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N25 +// Location: FF_X23_Y32_N29 dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|i2s_intf_|lrclk_r~0_combout ), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -56342,7 +59617,7 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N0 +// Location: LCCOMB_X23_Y32_N30 cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|Equal0~2_combout $ (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ) @@ -56397,516 +59672,13 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] -// \ula_|i2s_intf_|bitcount[0]~6 = CARRY(!\ula_|i2s_intf_|bitcount [0]) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [0]), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|bitcount[0]~5_combout ), - .cout(\ula_|i2s_intf_|bitcount[0]~6 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; -defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N11 -dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bclk_r~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & !\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hF0FC; -defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N1 -dffeas \ula_|i2s_intf_|bitcount[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) -// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[0]~6 ), - .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .cout(\ula_|i2s_intf_|bitcount[1]~8 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y22_N3 -dffeas \ula_|i2s_intf_|bitcount[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) -// \ula_|i2s_intf_|bitcount[2]~10 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[1]~8 ), - .combout(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .cout(\ula_|i2s_intf_|bitcount[2]~10 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; -defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y22_N5 -dffeas \ula_|i2s_intf_|bitcount[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N6 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) -// \ula_|i2s_intf_|bitcount[3]~12 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~10 )) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[2]~10 ), - .combout(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .cout(\ula_|i2s_intf_|bitcount[3]~12 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hA505; -defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y22_N7 -dffeas \ula_|i2s_intf_|bitcount[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( -// Equation(s): -// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # (((\ula_|i2s_intf_|bitcount [2]) # (\ula_|i2s_intf_|bitcount [1])) # (!\ula_|i2s_intf_|bitcount [0])) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(\ula_|i2s_intf_|bitcount [0]), - .datac(\ula_|i2s_intf_|bitcount [2]), - .datad(\ula_|i2s_intf_|bitcount [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFFB; -defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [4]), - .datac(gnd), - .datad(gnd), - .cin(\ula_|i2s_intf_|bitcount[3]~12 ), - .combout(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h3C3C; -defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y22_N9 -dffeas \ula_|i2s_intf_|bitcount[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(), - .cout(\ula_|i2s_intf_|Add2~7_cout )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; -defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) -// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) - - .dataa(\ula_|i2s_intf_|bdivider [1]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~7_cout ), - .combout(\ula_|i2s_intf_|Add2~8_combout ), - .cout(\ula_|i2s_intf_|Add2~9 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hA505; -defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Equal1~0_combout ), - .datad(\ula_|i2s_intf_|Add2~8_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h1300; -defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N13 -dffeas \ula_|i2s_intf_|bdivider[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~20_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) -// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) - - .dataa(\ula_|i2s_intf_|bdivider [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~9 ), - .combout(\ula_|i2s_intf_|Add2~10_combout ), - .cout(\ula_|i2s_intf_|Add2~11 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hA55F; -defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add2~10_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h0203; -defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N17 -dffeas \ula_|i2s_intf_|bdivider[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~17_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) -// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~11 ), - .combout(\ula_|i2s_intf_|Add2~12_combout ), - .cout(\ula_|i2s_intf_|Add2~13 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~19_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~12_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Equal1~0_combout ), - .datad(\ula_|i2s_intf_|Add2~12_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h1300; -defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N3 -dffeas \ula_|i2s_intf_|bdivider[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~19_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|bdivider [4]), - .cin(\ula_|i2s_intf_|Add2~13 ), - .combout(\ula_|i2s_intf_|Add2~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; -defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add2~14_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0203; -defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N19 -dffeas \ula_|i2s_intf_|bdivider[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( -// Equation(s): -// \ula_|i2s_intf_|Equal1~0_combout = (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|bdivider [2] & \ula_|i2s_intf_|bdivider [4]))) - - .dataa(\ula_|i2s_intf_|bdivider [1]), - .datab(\ula_|i2s_intf_|bdivider [3]), - .datac(\ula_|i2s_intf_|bdivider [2]), - .datad(\ula_|i2s_intf_|bdivider [4]), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h1000; -defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~1 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[4]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|LessThan0~0_combout ), - .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4]~1 .lut_mask = 16'h8A00; -defparam \ula_|i2s_intf_|shiftreg[4]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N12 +// Location: LCCOMB_X23_Y32_N8 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( // Equation(s): -// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[4]~1_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) +// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(\ula_|i2s_intf_|bdivider [0]), .datad(\ula_|i2s_intf_|Equal1~0_combout ), .cin(gnd), @@ -56917,7 +59689,7 @@ defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1101; defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y22_N13 +// Location: FF_X23_Y32_N9 dffeas \ula_|i2s_intf_|bdivider[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~18_combout ), @@ -56936,54 +59708,574 @@ defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( +// Location: LCCOMB_X24_Y32_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( // Equation(s): -// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|bdivider [0] & \ula_|i2s_intf_|Equal1~0_combout ) +// \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] +// \ula_|i2s_intf_|bitcount[0]~6 = CARRY(!\ula_|i2s_intf_|bitcount [0]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [0]), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|bitcount[0]~5_combout ), + .cout(\ula_|i2s_intf_|bitcount[0]~6 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; +defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder ( +// Equation(s): +// \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout = \ula_|i2s_intf_|bclk_r~1_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|bdivider [0]), + .datac(\ula_|i2s_intf_|bclk_r~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .lut_mask = 16'hF0F0; +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y32_N25 +dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[1]~1_combout )) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datac(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hBABA; +defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y32_N15 +dffeas \ula_|i2s_intf_|bitcount[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) +// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[0]~6 ), + .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .cout(\ula_|i2s_intf_|bitcount[1]~8 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y32_N17 +dffeas \ula_|i2s_intf_|bitcount[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) +// \ula_|i2s_intf_|bitcount[2]~10 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[1]~8 ), + .combout(\ula_|i2s_intf_|bitcount[2]~9_combout ), + .cout(\ula_|i2s_intf_|bitcount[2]~10 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; +defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y32_N19 +dffeas \ula_|i2s_intf_|bitcount[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) +// \ula_|i2s_intf_|bitcount[3]~12 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~10 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[2]~10 ), + .combout(\ula_|i2s_intf_|bitcount[3]~11_combout ), + .cout(\ula_|i2s_intf_|bitcount[3]~12 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y32_N21 +dffeas \ula_|i2s_intf_|bitcount[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) + + .dataa(\ula_|i2s_intf_|bitcount [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2s_intf_|bitcount[3]~12 ), + .combout(\ula_|i2s_intf_|bitcount[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h5A5A; +defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y32_N23 +dffeas \ula_|i2s_intf_|bitcount[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( +// Equation(s): +// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # ((\ula_|i2s_intf_|bitcount [2]) # ((\ula_|i2s_intf_|bitcount [1]) # (!\ula_|i2s_intf_|bitcount [0]))) + + .dataa(\ula_|i2s_intf_|bitcount [3]), + .datab(\ula_|i2s_intf_|bitcount [2]), + .datac(\ula_|i2s_intf_|bitcount [0]), + .datad(\ula_|i2s_intf_|bitcount [1]), + .cin(gnd), + .combout(\ula_|i2s_intf_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFEF; +defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[1]~1 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[1]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Equal1~0_combout ), + .datac(\ula_|i2s_intf_|bitcount [4]), + .datad(\ula_|i2s_intf_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[1]~1 .lut_mask = 16'h8808; +defparam \ula_|i2s_intf_|shiftreg[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\ula_|i2s_intf_|Add2~7_cout )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) +// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~7_cout ), + .combout(\ula_|i2s_intf_|Add2~8_combout ), + .cout(\ula_|i2s_intf_|Add2~9 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Add2~8_combout ), .datad(\ula_|i2s_intf_|Equal1~0_combout ), .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h1030; +defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y32_N5 +dffeas \ula_|i2s_intf_|bdivider[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) +// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~9 ), + .combout(\ula_|i2s_intf_|Add2~10_combout ), + .cout(\ula_|i2s_intf_|Add2~11 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hC33F; +defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) + + .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Add2~10_combout ), + .datad(\ula_|i2s_intf_|Equal1~1_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h1101; +defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y32_N17 +dffeas \ula_|i2s_intf_|bdivider[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~17_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) +// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~11 ), + .combout(\ula_|i2s_intf_|Add2~12_combout ), + .cout(\ula_|i2s_intf_|Add2~13 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~19_combout = (\ula_|i2s_intf_|Add2~12_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Add2~12_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h040C; +defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y32_N15 +dffeas \ula_|i2s_intf_|bdivider[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~19_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|bdivider [4]), + .cin(\ula_|i2s_intf_|Add2~13 ), + .combout(\ula_|i2s_intf_|Add2~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; +defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) + + .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Add2~14_combout ), + .datad(\ula_|i2s_intf_|Equal1~1_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h1101; +defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y32_N7 +dffeas \ula_|i2s_intf_|bdivider[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~0_combout = (\ula_|i2s_intf_|bdivider [4] & (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & \ula_|i2s_intf_|bdivider [2]))) + + .dataa(\ula_|i2s_intf_|bdivider [4]), + .datab(\ula_|i2s_intf_|bdivider [1]), + .datac(\ula_|i2s_intf_|bdivider [3]), + .datad(\ula_|i2s_intf_|bdivider [2]), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h0200; +defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|Equal1~0_combout & \ula_|i2s_intf_|bdivider [0]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal1~0_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|bdivider [0]), + .cin(gnd), .combout(\ula_|i2s_intf_|Equal1~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hF000; +defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hCC00; defparam \ula_|i2s_intf_|Equal1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N14 +// Location: LCCOMB_X24_Y32_N12 cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|bclk_r~0_combout = \ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]))) - .dataa(gnd), - .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .dataa(\ula_|i2s_intf_|LessThan0~0_combout ), + .datab(gnd), .datac(\ula_|i2s_intf_|bitcount [4]), .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), .cin(gnd), .combout(\ula_|i2s_intf_|bclk_r~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h30CF; +defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h50AF; defparam \ula_|i2s_intf_|bclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N10 +// Location: LCCOMB_X24_Y32_N26 cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~1 ( // Equation(s): -// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~0_combout )) # (!\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))))) +// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~0_combout ))) # (!\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )))) .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|bclk_r~0_combout ), - .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|bclk_r~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|bclk_r~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h00D8; +defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h0E04; defparam \ula_|i2s_intf_|bclk_r~1 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57006,15 +60298,15 @@ defparam \ula_|i2s_intf_|bclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N24 +// Location: LCCOMB_X23_Y19_N16 cycloneive_lcell_comb \ula_|pcm_outl[13]~feeder ( // Equation(s): -// \ula_|pcm_outl[13]~feeder_combout = \D[3]~96_combout +// \ula_|pcm_outl[13]~feeder_combout = \D[3]~109_combout .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(\D[3]~96_combout ), + .datad(\D[3]~109_combout ), .cin(gnd), .combout(\ula_|pcm_outl[13]~feeder_combout ), .cout()); @@ -57023,41 +60315,41 @@ defparam \ula_|pcm_outl[13]~feeder .lut_mask = 16'hFF00; defparam \ula_|pcm_outl[13]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N2 +// Location: LCCOMB_X24_Y19_N30 cycloneive_lcell_comb \ula_|always0~2 ( // Equation(s): -// \ula_|always0~2_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) +// \ula_|always0~2_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nRD_out~2_combout )) - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .dataa(gnd), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), + .datad(\z80_|memory_ifc_|nRD_out~2_combout ), .cin(gnd), .combout(\ula_|always0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~2 .lut_mask = 16'h2020; +defparam \ula_|always0~2 .lut_mask = 16'h00C0; defparam \ula_|always0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N20 +// Location: LCCOMB_X23_Y19_N2 cycloneive_lcell_comb \ula_|always0~3 ( // Equation(s): -// \ula_|always0~3_combout = (!\z80_|address_pins_|DFFE_apin_latch [0] & (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~2_combout ))) +// \ula_|always0~3_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [0] & (!\z80_|control_pins_|pin_nIORQ~1_combout & \ula_|always0~2_combout ))) - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|control_pins_|pin_nIORQ~1_combout ), .datad(\ula_|always0~2_combout ), .cin(gnd), .combout(\ula_|always0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~3 .lut_mask = 16'h4000; +defparam \ula_|always0~3 .lut_mask = 16'h0200; defparam \ula_|always0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y19_N25 +// Location: FF_X23_Y19_N17 dffeas \ula_|pcm_outl[13] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|pcm_outl[13]~feeder_combout ), @@ -57076,20 +60368,20 @@ defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N26 +// Location: LCCOMB_X24_Y32_N0 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( // Equation(s): // \ula_|i2s_intf_|shiftreg[0]~19_combout = (\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|LessThan0~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h008A; +defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h2202; defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57103,25 +60395,25 @@ defparam \AUD_ADCDAT~input .bus_hold = "false"; defparam \AUD_ADCDAT~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N20 +// Location: LCCOMB_X23_Y33_N6 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~20 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [0])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\AUD_ADCDAT~input_o ))))) # -// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (((\ula_|i2s_intf_|shiftreg [0])))) +// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|shiftreg [0])))) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\AUD_ADCDAT~input_o ))) # +// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (\ula_|i2s_intf_|shiftreg [0])))) - .dataa(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|shiftreg[0]~19_combout ), .datac(\ula_|i2s_intf_|shiftreg [0]), .datad(\AUD_ADCDAT~input_o ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[0]~20_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF2D0; +defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF4B0; defparam \ula_|i2s_intf_|shiftreg[0]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N21 +// Location: FF_X23_Y33_N7 dffeas \ula_|i2s_intf_|shiftreg[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg[0]~20_combout ), @@ -57140,41 +60432,41 @@ defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N26 +// Location: LCCOMB_X23_Y33_N28 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~18 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~18_combout = (\ula_|i2s_intf_|shiftreg [0] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [0]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [0]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [0]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~2 ( +// Location: LCCOMB_X24_Y32_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[1]~2 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg[4]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & \ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) +// \ula_|i2s_intf_|shiftreg[1]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[1]~1_combout )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datac(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .datad(gnd), .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .combout(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4]~2 .lut_mask = 16'hFCF0; -defparam \ula_|i2s_intf_|shiftreg[4]~2 .sum_lutc_input = "datac"; +defparam \ula_|i2s_intf_|shiftreg[1]~2 .lut_mask = 16'hEAEA; +defparam \ula_|i2s_intf_|shiftreg[1]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N27 +// Location: FF_X23_Y33_N29 dffeas \ula_|i2s_intf_|shiftreg[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~18_combout ), @@ -57183,7 +60475,7 @@ dffeas \ula_|i2s_intf_|shiftreg[1] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [1]), @@ -57193,24 +60485,24 @@ defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N24 +// Location: LCCOMB_X23_Y33_N14 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~17_combout = (\ula_|i2s_intf_|shiftreg [1] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [1]) .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|shiftreg [1]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [1]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N25 +// Location: FF_X23_Y33_N15 dffeas \ula_|i2s_intf_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~17_combout ), @@ -57219,7 +60511,7 @@ dffeas \ula_|i2s_intf_|shiftreg[2] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [2]), @@ -57229,24 +60521,24 @@ defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N18 +// Location: LCCOMB_X23_Y33_N16 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~16_combout = (\ula_|i2s_intf_|shiftreg [2] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), .datab(\ula_|i2s_intf_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N19 +// Location: FF_X23_Y33_N17 dffeas \ula_|i2s_intf_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~16_combout ), @@ -57255,7 +60547,7 @@ dffeas \ula_|i2s_intf_|shiftreg[3] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [3]), @@ -57265,24 +60557,24 @@ defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N0 +// Location: LCCOMB_X23_Y33_N22 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~15_combout = (\ula_|i2s_intf_|shiftreg [3] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~15_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [3]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [3]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [3]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N1 +// Location: FF_X23_Y33_N23 dffeas \ula_|i2s_intf_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~15_combout ), @@ -57291,7 +60583,7 @@ dffeas \ula_|i2s_intf_|shiftreg[4] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [4]), @@ -57301,24 +60593,24 @@ defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N10 +// Location: LCCOMB_X23_Y33_N12 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~14_combout = (\ula_|i2s_intf_|shiftreg [4] & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [4]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|shiftreg [4]), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~14_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h0A0A; defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N11 +// Location: FF_X23_Y33_N13 dffeas \ula_|i2s_intf_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~14_combout ), @@ -57327,7 +60619,7 @@ dffeas \ula_|i2s_intf_|shiftreg[5] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [5]), @@ -57337,24 +60629,24 @@ defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N16 +// Location: LCCOMB_X23_Y33_N18 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~13_combout = (\ula_|i2s_intf_|shiftreg [5] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~13_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [5]) - .dataa(\ula_|i2s_intf_|shiftreg [5]), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [5]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N17 +// Location: FF_X23_Y33_N19 dffeas \ula_|i2s_intf_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~13_combout ), @@ -57363,7 +60655,7 @@ dffeas \ula_|i2s_intf_|shiftreg[6] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [6]), @@ -57373,24 +60665,24 @@ defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N30 +// Location: LCCOMB_X23_Y33_N8 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~12_combout = (\ula_|i2s_intf_|shiftreg [6] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~12_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [6]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [6]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [6]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N31 +// Location: FF_X23_Y33_N9 dffeas \ula_|i2s_intf_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~12_combout ), @@ -57399,7 +60691,7 @@ dffeas \ula_|i2s_intf_|shiftreg[7] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [7]), @@ -57409,24 +60701,24 @@ defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N28 +// Location: LCCOMB_X23_Y33_N2 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~11_combout = (\ula_|i2s_intf_|shiftreg [7] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|shiftreg [7]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|shiftreg [7]), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~11_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N29 +// Location: FF_X23_Y33_N3 dffeas \ula_|i2s_intf_|shiftreg[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~11_combout ), @@ -57435,7 +60727,7 @@ dffeas \ula_|i2s_intf_|shiftreg[8] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [8]), @@ -57445,24 +60737,24 @@ defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N22 +// Location: LCCOMB_X23_Y33_N4 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~10_combout = (\ula_|i2s_intf_|shiftreg [8] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~10_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [8]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [8]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [8]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N23 +// Location: FF_X23_Y33_N5 dffeas \ula_|i2s_intf_|shiftreg[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~10_combout ), @@ -57471,7 +60763,7 @@ dffeas \ula_|i2s_intf_|shiftreg[9] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [9]), @@ -57481,24 +60773,24 @@ defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N12 +// Location: LCCOMB_X23_Y33_N10 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [9] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|shiftreg [9]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|shiftreg [9]), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N13 +// Location: FF_X23_Y33_N11 dffeas \ula_|i2s_intf_|shiftreg[10] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~9_combout ), @@ -57507,7 +60799,7 @@ dffeas \ula_|i2s_intf_|shiftreg[10] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [10]), @@ -57517,24 +60809,24 @@ defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N2 +// Location: LCCOMB_X23_Y33_N0 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~8_combout = (\ula_|i2s_intf_|shiftreg [10] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~8_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [10]) - .dataa(\ula_|i2s_intf_|shiftreg [10]), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [10]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N3 +// Location: FF_X23_Y33_N1 dffeas \ula_|i2s_intf_|shiftreg[11] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~8_combout ), @@ -57543,7 +60835,7 @@ dffeas \ula_|i2s_intf_|shiftreg[11] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [11]), @@ -57553,24 +60845,24 @@ defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N8 +// Location: LCCOMB_X23_Y33_N26 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~7_combout = (\ula_|i2s_intf_|shiftreg [11] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~7_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [11]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [11]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [11]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N9 +// Location: FF_X23_Y33_N27 dffeas \ula_|i2s_intf_|shiftreg[12] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~7_combout ), @@ -57579,7 +60871,7 @@ dffeas \ula_|i2s_intf_|shiftreg[12] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [12]), @@ -57589,7 +60881,7 @@ defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N30 +// Location: LCCOMB_X23_Y32_N10 cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( // Equation(s): // \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INR [14]))))) # @@ -57607,7 +60899,7 @@ defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hB8F0; defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N31 +// Location: FF_X23_Y32_N11 dffeas \ula_|i2s_intf_|PCM_INR[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), @@ -57626,7 +60918,7 @@ defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N28 +// Location: LCCOMB_X23_Y32_N12 cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INL[14]~0 ( // Equation(s): // \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INL [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])))) # @@ -57644,7 +60936,7 @@ defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF0B8; defparam \ula_|i2s_intf_|PCM_INL[14]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N29 +// Location: FF_X23_Y32_N13 dffeas \ula_|i2s_intf_|PCM_INL[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), @@ -57663,24 +60955,24 @@ defparam \ula_|i2s_intf_|PCM_INL[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|PCM_INL[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N6 +// Location: LCCOMB_X23_Y32_N0 cycloneive_lcell_comb \ula_|pcm_outr~0 ( // Equation(s): // \ula_|pcm_outr~0_combout = (\ula_|i2s_intf_|PCM_INR [14]) # (\ula_|i2s_intf_|PCM_INL [14]) - .dataa(gnd), + .dataa(\ula_|i2s_intf_|PCM_INR [14]), .datab(gnd), - .datac(\ula_|i2s_intf_|PCM_INR [14]), + .datac(gnd), .datad(\ula_|i2s_intf_|PCM_INL [14]), .cin(gnd), .combout(\ula_|pcm_outr~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFF0; +defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFAA; defparam \ula_|pcm_outr~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N7 +// Location: FF_X23_Y32_N1 dffeas \ula_|pcm_outl[12] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|pcm_outr~0_combout ), @@ -57699,24 +60991,24 @@ defparam \ula_|pcm_outl[12] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N14 +// Location: LCCOMB_X23_Y33_N20 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~6 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [12]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [12])) - .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg [12]), + .dataa(\ula_|i2s_intf_|shiftreg [12]), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), .datad(\ula_|pcm_outl [12]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFC30; +defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFA0A; defparam \ula_|i2s_intf_|shiftreg~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N15 +// Location: FF_X23_Y33_N21 dffeas \ula_|i2s_intf_|shiftreg[13] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~6_combout ), @@ -57725,7 +61017,7 @@ dffeas \ula_|i2s_intf_|shiftreg[13] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [13]), @@ -57735,24 +61027,24 @@ defparam \ula_|i2s_intf_|shiftreg[13] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N4 +// Location: LCCOMB_X23_Y33_N30 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) .dataa(gnd), .datab(\ula_|pcm_outl [13]), - .datac(\ula_|i2s_intf_|shiftreg [13]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [13]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hCCF0; +defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hCFC0; defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N5 +// Location: FF_X23_Y33_N31 dffeas \ula_|i2s_intf_|shiftreg[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~5_combout ), @@ -57761,7 +61053,7 @@ dffeas \ula_|i2s_intf_|shiftreg[14] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [14]), @@ -57771,10 +61063,27 @@ defparam \ula_|i2s_intf_|shiftreg[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[14] .power_up = "low"; // synopsys translate_on -// Location: FF_X29_Y14_N31 +// Location: LCCOMB_X23_Y19_N22 +cycloneive_lcell_comb \ula_|pcm_outl[14]~feeder ( +// Equation(s): +// \ula_|pcm_outl[14]~feeder_combout = \D[4]~111_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\D[4]~111_combout ), + .cin(gnd), + .combout(\ula_|pcm_outl[14]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|pcm_outl[14]~feeder .lut_mask = 16'hFF00; +defparam \ula_|pcm_outl[14]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N23 dffeas \ula_|pcm_outl[14] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\D[4]~98_combout ), + .d(\ula_|pcm_outl[14]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -57790,24 +61099,24 @@ defparam \ula_|pcm_outl[14] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y22_N4 +// Location: LCCOMB_X23_Y33_N24 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~4 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) .dataa(\ula_|i2s_intf_|shiftreg [14]), .datab(gnd), - .datac(\ula_|pcm_outl [14]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|pcm_outl [14]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hF0AA; +defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hFA0A; defparam \ula_|i2s_intf_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y22_N5 +// Location: FF_X23_Y33_N25 dffeas \ula_|i2s_intf_|shiftreg[15] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~4_combout ), @@ -57816,7 +61125,7 @@ dffeas \ula_|i2s_intf_|shiftreg[15] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [15]), @@ -57826,24 +61135,24 @@ defparam \ula_|i2s_intf_|shiftreg[15] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y22_N0 +// Location: LCCOMB_X20_Y33_N0 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~3 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~3_combout = (\ula_|i2s_intf_|shiftreg [15] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~3_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [15]) .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|shiftreg [15]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [15]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h3300; defparam \ula_|i2s_intf_|shiftreg~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y22_N1 +// Location: FF_X20_Y33_N1 dffeas \ula_|i2s_intf_|shiftreg[16] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~3_combout ), @@ -57852,7 +61161,7 @@ dffeas \ula_|i2s_intf_|shiftreg[16] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [16]), @@ -57862,20 +61171,20 @@ defparam \ula_|i2s_intf_|shiftreg[16] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y22_N10 +// Location: LCCOMB_X20_Y33_N14 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~0 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~0_combout = (\ula_|i2s_intf_|shiftreg [16] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [16]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [16]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [16]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h3300; defparam \ula_|i2s_intf_|shiftreg~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57888,7 +61197,7 @@ dffeas \ula_|i2s_intf_|shiftreg[17] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [17]), @@ -57898,135 +61207,32 @@ defparam \ula_|i2s_intf_|shiftreg[17] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N8 -cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Location: LCCOMB_X27_Y18_N12 +cycloneive_lcell_comb \ula_|border[1]~feeder ( // Equation(s): -// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [6]))) +// \ula_|border[1]~feeder_combout = \D[1]~41_combout - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|vga_vc [8]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [6]), - .cin(gnd), - .combout(\ula_|video_|LessThan2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N4 -cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( -// Equation(s): -// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) - - .dataa(\ula_|video_|vga_vc [2]), - .datab(\ula_|video_|vga_vc [3]), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|LessThan6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0111; -defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N30 -cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( -// Equation(s): -// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(\ula_|video_|vga_vc [4]), - .datac(\ula_|video_|LessThan2~0_combout ), - .datad(\ula_|video_|LessThan6~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan2~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7050; -defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N16 -cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( -// Equation(s): -// \ula_|video_|LessThan3~0_combout = ((\ula_|video_|LessThan6~0_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) # (!\ula_|video_|vga_vc [9]) - - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|LessThan6~0_combout ), - .datac(\ula_|video_|vga_vc [5]), - .datad(\ula_|video_|Equal2~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h5D55; -defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N22 -cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( -// Equation(s): -// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [6] & !\ula_|video_|vga_hc [5])) - - .dataa(\ula_|video_|vga_hc [4]), - .datab(\ula_|video_|vga_hc [6]), + .dataa(gnd), + .datab(gnd), .datac(gnd), - .datad(\ula_|video_|vga_hc [5]), + .datad(\D[1]~41_combout ), .cin(gnd), - .combout(\ula_|video_|LessThan0~0_combout ), + .combout(\ula_|border[1]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0011; -defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; +defparam \ula_|border[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|border[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N24 -cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( -// Equation(s): -// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((\ula_|video_|LessThan0~0_combout & !\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # -// ((!\ula_|video_|LessThan0~0_combout & \ula_|video_|vga_hc [7])))) - - .dataa(\ula_|video_|LessThan0~0_combout ), - .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|vga_hc [7]), - .datad(\ula_|video_|vga_hc [9]), - .cin(gnd), - .combout(\ula_|video_|disp_enable~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h3BDC; -defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N2 -cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( -// Equation(s): -// \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) - - .dataa(\ula_|video_|LessThan2~1_combout ), - .datab(\ula_|video_|LessThan3~0_combout ), - .datac(gnd), - .datad(\ula_|video_|disp_enable~0_combout ), - .cin(gnd), - .combout(\ula_|video_|disp_enable~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h4400; -defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N11 +// Location: FF_X27_Y18_N13 dffeas \ula_|border[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\D[1]~34_combout ), + .d(\ula_|border[1]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58037,58 +61243,75 @@ defparam \ula_|border[1] .is_wysiwyg = "true"; defparam \ula_|border[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N8 +// Location: LCCOMB_X32_Y30_N28 +cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( +// Equation(s): +// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) + + .dataa(\ula_|video_|vga_vc [1]), + .datab(\ula_|video_|vga_vc [2]), + .datac(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|vga_vc [0]), + .cin(gnd), + .combout(\ula_|video_|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0103; +defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N14 cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( // Equation(s): // \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) - .dataa(\ula_|video_|vga_vc [6]), + .dataa(\ula_|video_|vga_vc [4]), .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|vga_vc [4]), + .datac(\ula_|video_|vga_vc [6]), .datad(\ula_|video_|LessThan6~0_combout ), .cin(gnd), .combout(\ula_|video_|LessThan6~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h7757; +defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h3F1F; defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N28 +// Location: LCCOMB_X29_Y30_N6 cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( // Equation(s): -// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) +// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [5] & !\ula_|video_|vga_hc [4])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) - .dataa(\ula_|video_|vga_hc [4]), - .datab(\ula_|video_|vga_hc [5]), - .datac(\ula_|video_|vga_hc [6]), + .dataa(\ula_|video_|vga_hc [5]), + .datab(\ula_|video_|vga_hc [6]), + .datac(\ula_|video_|vga_hc [4]), .datad(\ula_|video_|vga_hc [7]), .cin(gnd), .combout(\ula_|video_|LessThan4~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h1FFF; +defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h37FF; defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N10 +// Location: LCCOMB_X31_Y30_N10 cycloneive_lcell_comb \ula_|video_|screen_en~0 ( // Equation(s): // \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) - .dataa(\ula_|video_|vga_hc [9]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|LessThan4~0_combout ), - .datad(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|vga_hc [9]), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|LessThan4~0_combout ), .cin(gnd), .combout(\ula_|video_|screen_en~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1121; +defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1411; defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N22 +// Location: LCCOMB_X31_Y30_N24 cycloneive_lcell_comb \ula_|video_|screen_en~1 ( // Equation(s): // \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # @@ -58106,151 +61329,7 @@ defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE700; defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N28 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N10 -cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( -// Equation(s): -// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h0080; -defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N29 -dffeas \ula_|video_|attr_prefetch[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N12 -cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( -// Equation(s): -// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & \ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; -defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y33_N27 -dffeas \ula_|video_|attr[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N10 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N11 -dffeas \ula_|video_|attr_prefetch[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y33_N13 -dffeas \ula_|video_|attr[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N24 +// Location: LCCOMB_X30_Y28_N0 cycloneive_lcell_comb \ula_|video_|attr_prefetch[7]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 @@ -58267,7 +61346,24 @@ defparam \ula_|video_|attr_prefetch[7]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N25 +// Location: LCCOMB_X30_Y29_N20 +cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( +// Equation(s): +// \ula_|video_|Decoder0~1_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & \ula_|video_|vga_hc [1]))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h4000; +defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N1 dffeas \ula_|video_|attr_prefetch[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[7]~feeder_combout ), @@ -58286,7 +61382,24 @@ defparam \ula_|video_|attr_prefetch[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[7] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N5 +// Location: LCCOMB_X30_Y29_N10 +cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( +// Equation(s): +// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & \ula_|video_|vga_hc [1]))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; +defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y30_N7 dffeas \ula_|video_|attr[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58305,32 +61418,32 @@ defparam \ula_|video_|attr[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y33_N22 +// Location: LCCOMB_X34_Y30_N4 cycloneive_lcell_comb \ula_|video_|frame[0]~12 ( // Equation(s): // \ula_|video_|frame[0]~12_combout = \ula_|video_|Equal3~1_combout $ (\ula_|video_|frame [0]) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(gnd), - .datac(\ula_|video_|frame [0]), - .datad(gnd), + .dataa(gnd), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(gnd), + .datad(\ula_|video_|frame [0]), .cin(gnd), .combout(\ula_|video_|frame[0]~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h5A5A; +defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h33CC; defparam \ula_|video_|frame[0]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y33_N23 +// Location: FF_X34_Y30_N21 dffeas \ula_|video_|frame[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[0]~12_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|frame[0]~12_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -58341,14 +61454,14 @@ defparam \ula_|video_|frame[0] .is_wysiwyg = "true"; defparam \ula_|video_|frame[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N24 +// Location: LCCOMB_X34_Y30_N14 cycloneive_lcell_comb \ula_|video_|frame[1]~4 ( // Equation(s): -// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [0] & (\ula_|video_|frame [1] $ (VCC))) # (!\ula_|video_|frame [0] & (\ula_|video_|frame [1] & VCC)) -// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [0] & \ula_|video_|frame [1])) +// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [1] & (\ula_|video_|frame [0] $ (VCC))) # (!\ula_|video_|frame [1] & (\ula_|video_|frame [0] & VCC)) +// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [1] & \ula_|video_|frame [0])) - .dataa(\ula_|video_|frame [0]), - .datab(\ula_|video_|frame [1]), + .dataa(\ula_|video_|frame [1]), + .datab(\ula_|video_|frame [0]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -58359,7 +61472,7 @@ defparam \ula_|video_|frame[1]~4 .lut_mask = 16'h6688; defparam \ula_|video_|frame[1]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y33_N25 +// Location: FF_X34_Y30_N15 dffeas \ula_|video_|frame[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[1]~4_combout ), @@ -58378,25 +61491,25 @@ defparam \ula_|video_|frame[1] .is_wysiwyg = "true"; defparam \ula_|video_|frame[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N26 +// Location: LCCOMB_X34_Y30_N16 cycloneive_lcell_comb \ula_|video_|frame[2]~6 ( // Equation(s): // \ula_|video_|frame[2]~6_combout = (\ula_|video_|frame [2] & (!\ula_|video_|frame[1]~5 )) # (!\ula_|video_|frame [2] & ((\ula_|video_|frame[1]~5 ) # (GND))) // \ula_|video_|frame[2]~7 = CARRY((!\ula_|video_|frame[1]~5 ) # (!\ula_|video_|frame [2])) - .dataa(\ula_|video_|frame [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|frame [2]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|frame[1]~5 ), .combout(\ula_|video_|frame[2]~6_combout ), .cout(\ula_|video_|frame[2]~7 )); // synopsys translate_off -defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h3C3F; defparam \ula_|video_|frame[2]~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N27 +// Location: FF_X34_Y30_N17 dffeas \ula_|video_|frame[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[2]~6_combout ), @@ -58415,7 +61528,7 @@ defparam \ula_|video_|frame[2] .is_wysiwyg = "true"; defparam \ula_|video_|frame[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N28 +// Location: LCCOMB_X34_Y30_N18 cycloneive_lcell_comb \ula_|video_|frame[3]~8 ( // Equation(s): // \ula_|video_|frame[3]~8_combout = (\ula_|video_|frame [3] & (\ula_|video_|frame[2]~7 $ (GND))) # (!\ula_|video_|frame [3] & (!\ula_|video_|frame[2]~7 & VCC)) @@ -58433,7 +61546,7 @@ defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hC30C; defparam \ula_|video_|frame[3]~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N29 +// Location: FF_X34_Y30_N19 dffeas \ula_|video_|frame[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[3]~8_combout ), @@ -58452,32 +61565,32 @@ defparam \ula_|video_|frame[3] .is_wysiwyg = "true"; defparam \ula_|video_|frame[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N30 +// Location: LCCOMB_X34_Y30_N20 cycloneive_lcell_comb \ula_|video_|frame[4]~10 ( // Equation(s): -// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame [4] $ (\ula_|video_|frame[3]~9 ) +// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame[3]~9 $ (\ula_|video_|frame [4]) - .dataa(\ula_|video_|frame [4]), + .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|video_|frame [4]), .cin(\ula_|video_|frame[3]~9 ), .combout(\ula_|video_|frame[4]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h5A5A; +defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h0FF0; defparam \ula_|video_|frame[4]~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N31 +// Location: FF_X34_Y30_N5 dffeas \ula_|video_|frame[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[4]~10_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|frame[4]~10_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|video_|Equal3~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58488,7 +61601,7 @@ defparam \ula_|video_|frame[4] .is_wysiwyg = "true"; defparam \ula_|video_|frame[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N4 +// Location: LCCOMB_X30_Y30_N6 cycloneive_lcell_comb \ula_|video_|inverted ( // Equation(s): // \ula_|video_|inverted~combout = (\ula_|video_|attr [7] & \ula_|video_|frame [4]) @@ -58505,7 +61618,7 @@ defparam \ula_|video_|inverted .lut_mask = 16'hF000; defparam \ula_|video_|inverted .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N12 +// Location: LCCOMB_X30_Y28_N28 cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 @@ -58522,24 +61635,24 @@ defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N8 +// Location: LCCOMB_X30_Y29_N14 cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( // Equation(s): -// \ula_|video_|Decoder0~2_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) +// \ula_|video_|Decoder0~2_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [1]))) - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), .cin(gnd), .combout(\ula_|video_|Decoder0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0008; +defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0040; defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N13 +// Location: FF_X30_Y28_N29 dffeas \ula_|video_|bits_prefetch[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), @@ -58558,32 +61671,15 @@ defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N6 -cycloneive_lcell_comb \ula_|video_|bits[6]~feeder ( -// Equation(s): -// \ula_|video_|bits[6]~feeder_combout = \ula_|video_|bits_prefetch [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|bits_prefetch [6]), - .cin(gnd), - .combout(\ula_|video_|bits[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y33_N7 +// Location: FF_X30_Y30_N5 dffeas \ula_|video_|bits[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits[6]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [6]), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58594,7 +61690,7 @@ defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; defparam \ula_|video_|bits[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N22 +// Location: LCCOMB_X30_Y28_N26 cycloneive_lcell_comb \ula_|video_|bits_prefetch[4]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 @@ -58611,7 +61707,7 @@ defparam \ula_|video_|bits_prefetch[4]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[4]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N23 +// Location: FF_X30_Y28_N27 dffeas \ula_|video_|bits_prefetch[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[4]~feeder_combout ), @@ -58630,7 +61726,7 @@ defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N23 +// Location: FF_X30_Y30_N29 dffeas \ula_|video_|bits[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58649,7 +61745,7 @@ defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; defparam \ula_|video_|bits[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N18 +// Location: LCCOMB_X30_Y28_N14 cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 @@ -58666,7 +61762,7 @@ defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N19 +// Location: FF_X30_Y28_N15 dffeas \ula_|video_|bits_prefetch[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), @@ -58685,7 +61781,7 @@ defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N18 +// Location: LCCOMB_X30_Y30_N24 cycloneive_lcell_comb \ula_|video_|bits[5]~feeder ( // Equation(s): // \ula_|video_|bits[5]~feeder_combout = \ula_|video_|bits_prefetch [5] @@ -58702,7 +61798,7 @@ defparam \ula_|video_|bits[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N19 +// Location: FF_X30_Y30_N25 dffeas \ula_|video_|bits[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[5]~feeder_combout ), @@ -58721,7 +61817,7 @@ defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; defparam \ula_|video_|bits[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N0 +// Location: LCCOMB_X30_Y28_N12 cycloneive_lcell_comb \ula_|video_|bits_prefetch[7]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 @@ -58738,7 +61834,7 @@ defparam \ula_|video_|bits_prefetch[7]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N1 +// Location: FF_X30_Y28_N13 dffeas \ula_|video_|bits_prefetch[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[7]~feeder_combout ), @@ -58757,7 +61853,7 @@ defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N1 +// Location: FF_X30_Y30_N19 dffeas \ula_|video_|bits[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58776,41 +61872,41 @@ defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; defparam \ula_|video_|bits[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N0 +// Location: LCCOMB_X30_Y30_N18 cycloneive_lcell_comb \ula_|video_|Mux0~0 ( // Equation(s): // \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [5])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [7]))))) - .dataa(\ula_|video_|bits [5]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [5]), .datac(\ula_|video_|bits [7]), .datad(\ula_|video_|vga_hc [2]), .cin(gnd), .combout(\ula_|video_|Mux0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE30; +defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE50; defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N22 +// Location: LCCOMB_X30_Y30_N28 cycloneive_lcell_comb \ula_|video_|Mux0~1 ( // Equation(s): // \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) - .dataa(\ula_|video_|bits [6]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [6]), .datac(\ula_|video_|bits [4]), .datad(\ula_|video_|Mux0~0_combout ), .cin(gnd), .combout(\ula_|video_|Mux0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF388; +defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF588; defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N16 +// Location: LCCOMB_X30_Y28_N20 cycloneive_lcell_comb \ula_|video_|bits_prefetch[2]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 @@ -58827,7 +61923,7 @@ defparam \ula_|video_|bits_prefetch[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N17 +// Location: FF_X30_Y28_N21 dffeas \ula_|video_|bits_prefetch[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[2]~feeder_combout ), @@ -58846,7 +61942,7 @@ defparam \ula_|video_|bits_prefetch[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N12 +// Location: LCCOMB_X30_Y30_N14 cycloneive_lcell_comb \ula_|video_|bits[2]~feeder ( // Equation(s): // \ula_|video_|bits[2]~feeder_combout = \ula_|video_|bits_prefetch [2] @@ -58863,7 +61959,7 @@ defparam \ula_|video_|bits[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N13 +// Location: FF_X30_Y30_N15 dffeas \ula_|video_|bits[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[2]~feeder_combout ), @@ -58882,7 +61978,7 @@ defparam \ula_|video_|bits[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N14 +// Location: LCCOMB_X30_Y28_N18 cycloneive_lcell_comb \ula_|video_|bits_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -58899,7 +61995,7 @@ defparam \ula_|video_|bits_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N15 +// Location: FF_X30_Y28_N19 dffeas \ula_|video_|bits_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[0]~feeder_combout ), @@ -58918,7 +62014,7 @@ defparam \ula_|video_|bits_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N3 +// Location: FF_X30_Y30_N1 dffeas \ula_|video_|bits[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58937,7 +62033,7 @@ defparam \ula_|video_|bits[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N6 +// Location: LCCOMB_X30_Y28_N6 cycloneive_lcell_comb \ula_|video_|bits_prefetch[1]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 @@ -58954,7 +62050,7 @@ defparam \ula_|video_|bits_prefetch[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N7 +// Location: FF_X30_Y28_N7 dffeas \ula_|video_|bits_prefetch[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[1]~feeder_combout ), @@ -58973,7 +62069,7 @@ defparam \ula_|video_|bits_prefetch[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N26 +// Location: LCCOMB_X30_Y30_N20 cycloneive_lcell_comb \ula_|video_|bits[1]~feeder ( // Equation(s): // \ula_|video_|bits[1]~feeder_combout = \ula_|video_|bits_prefetch [1] @@ -58990,7 +62086,7 @@ defparam \ula_|video_|bits[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N27 +// Location: FF_X30_Y30_N21 dffeas \ula_|video_|bits[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[1]~feeder_combout ), @@ -59009,7 +62105,7 @@ defparam \ula_|video_|bits[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N4 +// Location: LCCOMB_X30_Y28_N24 cycloneive_lcell_comb \ula_|video_|bits_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 @@ -59026,7 +62122,7 @@ defparam \ula_|video_|bits_prefetch[3]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N5 +// Location: FF_X30_Y28_N25 dffeas \ula_|video_|bits_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[3]~feeder_combout ), @@ -59045,7 +62141,7 @@ defparam \ula_|video_|bits_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N25 +// Location: FF_X30_Y30_N3 dffeas \ula_|video_|bits[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59064,92 +62160,305 @@ defparam \ula_|video_|bits[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N24 +// Location: LCCOMB_X30_Y30_N2 cycloneive_lcell_comb \ula_|video_|Mux0~2 ( // Equation(s): // \ula_|video_|Mux0~2_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [1])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [3]))))) - .dataa(\ula_|video_|bits [1]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [1]), .datac(\ula_|video_|bits [3]), .datad(\ula_|video_|vga_hc [2]), .cin(gnd), .combout(\ula_|video_|Mux0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE30; +defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE50; defparam \ula_|video_|Mux0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N2 +// Location: LCCOMB_X30_Y30_N0 cycloneive_lcell_comb \ula_|video_|Mux0~3 ( // Equation(s): // \ula_|video_|Mux0~3_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~2_combout & ((\ula_|video_|bits [0]))) # (!\ula_|video_|Mux0~2_combout & (\ula_|video_|bits [2])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~2_combout )))) - .dataa(\ula_|video_|bits [2]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [2]), .datac(\ula_|video_|bits [0]), .datad(\ula_|video_|Mux0~2_combout ), .cin(gnd), .combout(\ula_|video_|Mux0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF388; +defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF588; defparam \ula_|video_|Mux0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N10 -cycloneive_lcell_comb \ula_|video_|cindex[1]~0 ( +// Location: LCCOMB_X30_Y30_N10 +cycloneive_lcell_comb \ula_|video_|cindex[2]~0 ( // Equation(s): -// \ula_|video_|cindex[1]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~3_combout ))) # (!\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~1_combout )))) +// \ula_|video_|cindex[2]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~3_combout ))) # (!\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~1_combout )))) - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|inverted~combout ), - .datac(\ula_|video_|Mux0~1_combout ), + .dataa(\ula_|video_|inverted~combout ), + .datab(\ula_|video_|Mux0~1_combout ), + .datac(\ula_|video_|vga_hc [3]), .datad(\ula_|video_|Mux0~3_combout ), .cin(gnd), - .combout(\ula_|video_|cindex[1]~0_combout ), + .combout(\ula_|video_|cindex[2]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h369C; -defparam \ula_|video_|cindex[1]~0 .sum_lutc_input = "datac"; +defparam \ula_|video_|cindex[2]~0 .lut_mask = 16'h56A6; +defparam \ula_|video_|cindex[2]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N12 +// Location: LCCOMB_X30_Y28_N10 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N11 +dffeas \ula_|video_|attr_prefetch[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y30_N17 +dffeas \ula_|video_|attr[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y28_N4 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N5 +dffeas \ula_|video_|attr_prefetch[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y30_N19 +dffeas \ula_|video_|attr[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y30_N16 cycloneive_lcell_comb \ula_|video_|cindex[1]~1 ( // Equation(s): -// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [1])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [4]))) +// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [1]))) # (!\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [4])) - .dataa(\ula_|video_|attr [1]), + .dataa(\ula_|video_|cindex[2]~0_combout ), .datab(gnd), .datac(\ula_|video_|attr [4]), - .datad(\ula_|video_|cindex[1]~0_combout ), + .datad(\ula_|video_|attr [1]), .cin(gnd), .combout(\ula_|video_|cindex[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hAAF0; +defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hFA50; defparam \ula_|video_|cindex[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N24 +// Location: LCCOMB_X31_Y30_N4 +cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Equation(s): +// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) + + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|vga_vc [6]), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|vga_vc [8]), + .cin(gnd), + .combout(\ula_|video_|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N2 +cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( +// Equation(s): +// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|vga_vc [5]), + .datac(\ula_|video_|LessThan2~0_combout ), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7030; +defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N14 +cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( +// Equation(s): +// \ula_|video_|LessThan3~0_combout = ((!\ula_|video_|vga_vc [5] & (\ula_|video_|Equal2~0_combout & \ula_|video_|LessThan6~0_combout ))) # (!\ula_|video_|vga_vc [9]) + + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|vga_vc [5]), + .datac(\ula_|video_|Equal2~0_combout ), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h7555; +defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N0 +cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( +// Equation(s): +// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [5] & !\ula_|video_|vga_hc [6])) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(gnd), + .datac(\ula_|video_|vga_hc [5]), + .datad(\ula_|video_|vga_hc [6]), + .cin(gnd), + .combout(\ula_|video_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0005; +defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N4 +cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( +// Equation(s): +// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((!\ula_|video_|vga_hc [7] & \ula_|video_|LessThan0~0_combout )) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # ((\ula_|video_|vga_hc [7] & +// !\ula_|video_|LessThan0~0_combout )))) + + .dataa(\ula_|video_|vga_hc [7]), + .datab(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [9]), + .datad(\ula_|video_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|video_|disp_enable~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h7C3E; +defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N12 +cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( +// Equation(s): +// \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) + + .dataa(gnd), + .datab(\ula_|video_|LessThan2~1_combout ), + .datac(\ula_|video_|LessThan3~0_combout ), + .datad(\ula_|video_|disp_enable~0_combout ), + .cin(gnd), + .combout(\ula_|video_|disp_enable~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h3000; +defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N26 cycloneive_lcell_comb \ula_|video_|VGA_R[0]~0 ( // Equation(s): // \ula_|video_|VGA_R[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[1]~1_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [1])))) - .dataa(\ula_|video_|disp_enable~1_combout ), - .datab(\ula_|border [1]), - .datac(\ula_|video_|screen_en~1_combout ), - .datad(\ula_|video_|cindex[1]~1_combout ), + .dataa(\ula_|border [1]), + .datab(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|cindex[1]~1_combout ), + .datad(\ula_|video_|disp_enable~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hA808; +defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hE200; defparam \ula_|video_|VGA_R[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N26 +// Location: LCCOMB_X30_Y28_N22 cycloneive_lcell_comb \ula_|video_|attr_prefetch[6]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 @@ -59166,7 +62475,7 @@ defparam \ula_|video_|attr_prefetch[6]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N27 +// Location: FF_X30_Y28_N23 dffeas \ula_|video_|attr_prefetch[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[6]~feeder_combout ), @@ -59185,7 +62494,7 @@ defparam \ula_|video_|attr_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X38_Y33_N1 +// Location: FF_X31_Y30_N29 dffeas \ula_|video_|attr[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59204,49 +62513,66 @@ defparam \ula_|video_|attr[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N0 +// Location: LCCOMB_X31_Y30_N28 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~0 ( // Equation(s): -// \ula_|video_|VGA_B[1]~0_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & (\ula_|video_|attr [6] & \ula_|video_|disp_enable~0_combout ))) +// \ula_|video_|VGA_B[1]~0_combout = (\ula_|video_|LessThan3~0_combout & (\ula_|video_|disp_enable~0_combout & (\ula_|video_|attr [6] & !\ula_|video_|LessThan2~1_combout ))) - .dataa(\ula_|video_|LessThan2~1_combout ), - .datab(\ula_|video_|LessThan3~0_combout ), + .dataa(\ula_|video_|LessThan3~0_combout ), + .datab(\ula_|video_|disp_enable~0_combout ), .datac(\ula_|video_|attr [6]), - .datad(\ula_|video_|disp_enable~0_combout ), + .datad(\ula_|video_|LessThan2~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h4000; +defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h0080; defparam \ula_|video_|VGA_B[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N2 +// Location: LCCOMB_X31_Y30_N6 cycloneive_lcell_comb \ula_|video_|VGA_R[1]~1 ( // Equation(s): -// \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[1]~1_combout )) +// \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[1]~1_combout )) - .dataa(\ula_|video_|screen_en~1_combout ), - .datab(gnd), - .datac(\ula_|video_|VGA_B[1]~0_combout ), - .datad(\ula_|video_|cindex[1]~1_combout ), + .dataa(\ula_|video_|VGA_B[1]~0_combout ), + .datab(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|cindex[1]~1_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|VGA_R[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'hA000; +defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'h8080; defparam \ula_|video_|VGA_R[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y12_N17 +// Location: LCCOMB_X30_Y27_N20 +cycloneive_lcell_comb \ula_|border[2]~feeder ( +// Equation(s): +// \ula_|border[2]~feeder_combout = \D[2]~53_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\D[2]~53_combout ), + .cin(gnd), + .combout(\ula_|border[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|border[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|border[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y27_N21 dffeas \ula_|border[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\D[2]~46_combout ), + .d(\ula_|border[2]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -59257,62 +62583,7 @@ defparam \ula_|border[2] .is_wysiwyg = "true"; defparam \ula_|border[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N8 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N9 -dffeas \ula_|video_|attr_prefetch[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y33_N21 -dffeas \ula_|video_|attr[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N30 +// Location: LCCOMB_X30_Y28_N30 cycloneive_lcell_comb \ula_|video_|attr_prefetch[5]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 @@ -59329,7 +62600,7 @@ defparam \ula_|video_|attr_prefetch[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N31 +// Location: FF_X30_Y28_N31 dffeas \ula_|video_|attr_prefetch[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[5]~feeder_combout ), @@ -59348,7 +62619,7 @@ defparam \ula_|video_|attr_prefetch[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[5] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N15 +// Location: FF_X30_Y30_N31 dffeas \ula_|video_|attr[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59367,66 +62638,138 @@ defparam \ula_|video_|attr[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N14 -cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( +// Location: LCCOMB_X30_Y28_N16 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( // Equation(s): -// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [2])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [5]))) +// \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 .dataa(gnd), - .datab(\ula_|video_|attr [2]), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N17 +dffeas \ula_|video_|attr_prefetch[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y30_N13 +dffeas \ula_|video_|attr[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y30_N30 +cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( +// Equation(s): +// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [2]))) # (!\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [5])) + + .dataa(\ula_|video_|cindex[2]~0_combout ), + .datab(gnd), .datac(\ula_|video_|attr [5]), - .datad(\ula_|video_|cindex[1]~0_combout ), + .datad(\ula_|video_|attr [2]), .cin(gnd), .combout(\ula_|video_|cindex[2]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hCCF0; +defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hFA50; defparam \ula_|video_|cindex[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N26 +// Location: LCCOMB_X31_Y30_N0 cycloneive_lcell_comb \ula_|video_|VGA_G[0]~0 ( // Equation(s): // \ula_|video_|VGA_G[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[2]~2_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [2])))) - .dataa(\ula_|border [2]), + .dataa(\ula_|video_|disp_enable~1_combout ), .datab(\ula_|video_|screen_en~1_combout ), - .datac(\ula_|video_|disp_enable~1_combout ), + .datac(\ula_|border [2]), .datad(\ula_|video_|cindex[2]~2_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hE020; +defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hA820; defparam \ula_|video_|VGA_G[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N20 +// Location: LCCOMB_X31_Y30_N18 cycloneive_lcell_comb \ula_|video_|VGA_G[1]~1 ( // Equation(s): -// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|cindex[2]~2_combout & \ula_|video_|screen_en~1_combout )) +// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[2]~2_combout )) .dataa(\ula_|video_|VGA_B[1]~0_combout ), - .datab(\ula_|video_|cindex[2]~2_combout ), - .datac(gnd), - .datad(\ula_|video_|screen_en~1_combout ), + .datab(gnd), + .datac(\ula_|video_|screen_en~1_combout ), + .datad(\ula_|video_|cindex[2]~2_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_G[1]~1 .lut_mask = 16'h8800; +defparam \ula_|video_|VGA_G[1]~1 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_G[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N1 +// Location: LCCOMB_X26_Y15_N4 +cycloneive_lcell_comb \ula_|border[0]~feeder ( +// Equation(s): +// \ula_|border[0]~feeder_combout = \D[0]~65_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\D[0]~65_combout ), + .cin(gnd), + .combout(\ula_|border[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|border[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|border[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y15_N5 dffeas \ula_|border[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\D[0]~58_combout ), + .d(\ula_|border[0]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -59437,7 +62780,7 @@ defparam \ula_|border[0] .is_wysiwyg = "true"; defparam \ula_|border[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N20 +// Location: LCCOMB_X30_Y28_N8 cycloneive_lcell_comb \ula_|video_|attr_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -59454,7 +62797,7 @@ defparam \ula_|video_|attr_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N21 +// Location: FF_X30_Y28_N9 dffeas \ula_|video_|attr_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[0]~feeder_combout ), @@ -59473,32 +62816,15 @@ defparam \ula_|video_|attr_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N28 -cycloneive_lcell_comb \ula_|video_|attr[0]~feeder ( -// Equation(s): -// \ula_|video_|attr[0]~feeder_combout = \ula_|video_|attr_prefetch [0] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|attr_prefetch [0]), - .cin(gnd), - .combout(\ula_|video_|attr[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y33_N29 +// Location: FF_X29_Y30_N23 dffeas \ula_|video_|attr[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr[0]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [0]), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -59509,7 +62835,7 @@ defparam \ula_|video_|attr[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N2 +// Location: LCCOMB_X30_Y28_N2 cycloneive_lcell_comb \ula_|video_|attr_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 @@ -59526,7 +62852,7 @@ defparam \ula_|video_|attr_prefetch[3]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N3 +// Location: FF_X30_Y28_N3 dffeas \ula_|video_|attr_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[3]~feeder_combout ), @@ -59545,7 +62871,7 @@ defparam \ula_|video_|attr_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N29 +// Location: FF_X30_Y30_N9 dffeas \ula_|video_|attr[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59564,15 +62890,15 @@ defparam \ula_|video_|attr[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N28 +// Location: LCCOMB_X30_Y30_N8 cycloneive_lcell_comb \ula_|video_|cindex[0]~3 ( // Equation(s): -// \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [3]))) +// \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [3]))) .dataa(gnd), .datab(\ula_|video_|attr [0]), .datac(\ula_|video_|attr [3]), - .datad(\ula_|video_|cindex[1]~0_combout ), + .datad(\ula_|video_|cindex[2]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[0]~3_combout ), .cout()); @@ -59581,58 +62907,58 @@ defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hCCF0; defparam \ula_|video_|cindex[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N30 +// Location: LCCOMB_X30_Y30_N26 cycloneive_lcell_comb \ula_|video_|VGA_B[0]~1 ( // Equation(s): // \ula_|video_|VGA_B[0]~1_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[0]~3_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [0])))) - .dataa(\ula_|video_|disp_enable~1_combout ), - .datab(\ula_|border [0]), - .datac(\ula_|video_|screen_en~1_combout ), - .datad(\ula_|video_|cindex[0]~3_combout ), + .dataa(\ula_|border [0]), + .datab(\ula_|video_|cindex[0]~3_combout ), + .datac(\ula_|video_|disp_enable~1_combout ), + .datad(\ula_|video_|screen_en~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[0]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hA808; +defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hC0A0; defparam \ula_|video_|VGA_B[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N0 +// Location: LCCOMB_X30_Y30_N12 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~2 ( // Equation(s): -// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[0]~3_combout )) +// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|cindex[0]~3_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|screen_en~1_combout )) - .dataa(\ula_|video_|screen_en~1_combout ), - .datab(gnd), - .datac(\ula_|video_|VGA_B[1]~0_combout ), - .datad(\ula_|video_|cindex[0]~3_combout ), + .dataa(\ula_|video_|cindex[0]~3_combout ), + .datab(\ula_|video_|VGA_B[1]~0_combout ), + .datac(gnd), + .datad(\ula_|video_|screen_en~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[1]~2 .lut_mask = 16'hA000; +defparam \ula_|video_|VGA_B[1]~2 .lut_mask = 16'h8800; defparam \ula_|video_|VGA_B[1]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N26 +// Location: LCCOMB_X29_Y29_N12 cycloneive_lcell_comb \ula_|video_|Equal0~2 ( // Equation(s): -// \ula_|video_|Equal0~2_combout = (\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [9] & !\ula_|video_|vga_hc [8])) +// \ula_|video_|Equal0~2_combout = (!\ula_|video_|vga_hc [9] & (!\ula_|video_|vga_hc [8] & \ula_|video_|vga_hc [6])) - .dataa(\ula_|video_|vga_hc [6]), - .datab(\ula_|video_|vga_hc [9]), - .datac(gnd), - .datad(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_hc [9]), + .datab(gnd), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|vga_hc [6]), .cin(gnd), .combout(\ula_|video_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0022; +defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0500; defparam \ula_|video_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y33_N7 +// Location: FF_X29_Y29_N1 dffeas \ula_|video_|VGA_HS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector0~0_combout ), @@ -59651,7 +62977,7 @@ defparam \ula_|video_|VGA_HS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N6 +// Location: LCCOMB_X29_Y29_N0 cycloneive_lcell_comb \ula_|video_|Selector0~0 ( // Equation(s): // \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|Equal1~0_combout & \ula_|video_|VGA_HS~_Duplicate_1_q )))) # (!\ula_|video_|Equal0~2_combout & (\ula_|video_|Equal1~0_combout & @@ -59688,7 +63014,7 @@ defparam \ula_|video_|VGA_HS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS .power_up = "low"; // synopsys translate_on -// Location: FF_X34_Y33_N25 +// Location: FF_X32_Y30_N1 dffeas \ula_|video_|VGA_VS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector1~0_combout ), @@ -59707,21 +63033,21 @@ defparam \ula_|video_|VGA_VS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y33_N24 +// Location: LCCOMB_X32_Y30_N0 cycloneive_lcell_comb \ula_|video_|Selector1~0 ( // Equation(s): -// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal3~1_combout & (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1])))) # (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|VGA_VS~_Duplicate_1_q ) # ((\ula_|video_|Equal2~2_combout & -// \ula_|video_|vga_vc [1])))) +// \ula_|video_|Selector1~0_combout = (\ula_|video_|vga_vc [1] & ((\ula_|video_|Equal2~2_combout ) # ((\ula_|video_|VGA_VS~_Duplicate_1_q & !\ula_|video_|Equal3~1_combout )))) # (!\ula_|video_|vga_vc [1] & (((\ula_|video_|VGA_VS~_Duplicate_1_q & +// !\ula_|video_|Equal3~1_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), + .dataa(\ula_|video_|vga_vc [1]), .datab(\ula_|video_|Equal2~2_combout ), .datac(\ula_|video_|VGA_VS~_Duplicate_1_q ), - .datad(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector1~0 .lut_mask = 16'hDC50; +defparam \ula_|video_|Selector1~0 .lut_mask = 16'h88F8; defparam \ula_|video_|Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59744,7 +63070,7 @@ defparam \ula_|video_|VGA_VS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N4 +// Location: LCCOMB_X40_Y13_N4 cycloneive_lcell_comb \z80_|memory_ifc_|q1~feeder ( // Equation(s): // \z80_|memory_ifc_|q1~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -59761,7 +63087,7 @@ defparam \z80_|memory_ifc_|q1~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|q1~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X47_Y17_N5 +// Location: FF_X40_Y13_N5 dffeas \z80_|memory_ifc_|q1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|q1~feeder_combout ), @@ -59780,7 +63106,7 @@ defparam \z80_|memory_ifc_|q1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q1 .power_up = "low"; // synopsys translate_on -// Location: FF_X47_Y17_N25 +// Location: FF_X40_Y13_N3 dffeas \z80_|memory_ifc_|q2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -59799,7 +63125,7 @@ defparam \z80_|memory_ifc_|q2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N24 +// Location: LCCOMB_X40_Y13_N2 cycloneive_lcell_comb \z80_|memory_ifc_|nRFSH_out~0 ( // Equation(s): // \z80_|memory_ifc_|nRFSH_out~0_combout = (!\z80_|memory_ifc_|q2~q & \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) @@ -59816,7 +63142,7 @@ defparam \z80_|memory_ifc_|nRFSH_out~0 .lut_mask = 16'h0F00; defparam \z80_|memory_ifc_|nRFSH_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N26 +// Location: LCCOMB_X40_Y13_N24 cycloneive_lcell_comb \z80_|memory_ifc_|nM1_out ( // Equation(s): // \z80_|memory_ifc_|nM1_out~combout = (\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) @@ -59833,24 +63159,24 @@ defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF0F; defparam \z80_|memory_ifc_|nM1_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y26_N0 +// Location: LCCOMB_X23_Y19_N24 cycloneive_lcell_comb \ula_|beep~0 ( // Equation(s): -// \ula_|beep~0_combout = \D[4]~98_combout $ (\raw_loader_in~input_o $ (\D[3]~96_combout )) +// \ula_|beep~0_combout = \D[3]~109_combout $ (\raw_loader_in~input_o $ (\D[4]~111_combout )) - .dataa(gnd), - .datab(\D[4]~98_combout ), + .dataa(\D[3]~109_combout ), + .datab(gnd), .datac(\raw_loader_in~input_o ), - .datad(\D[3]~96_combout ), + .datad(\D[4]~111_combout ), .cin(gnd), .combout(\ula_|beep~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|beep~0 .lut_mask = 16'hC33C; +defparam \ula_|beep~0 .lut_mask = 16'hA55A; defparam \ula_|beep~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y26_N1 +// Location: FF_X23_Y19_N25 dffeas \ula_|beep ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|beep~0_combout ), @@ -59869,6 +63195,2526 @@ defparam \ula_|beep .is_wysiwyg = "true"; defparam \ula_|beep .power_up = "low"; // synopsys translate_on +// Location: LCCOMB_X23_Y10_N4 +cycloneive_lcell_comb \sdram_|Mux26~4 ( +// Equation(s): +// \sdram_|Mux26~4_combout = (!\sdram_|r.address[3]~6_combout & ((\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\sdram_|r.address[3]~6_combout ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [9]), + .cin(gnd), + .combout(\sdram_|Mux26~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux26~4 .lut_mask = 16'h3311; +defparam \sdram_|Mux26~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N10 +cycloneive_lcell_comb \sdram_|r.bank[0]~7 ( +// Equation(s): +// \sdram_|r.bank[0]~7_combout = (\sdram_|r.state [6] & \sdram_|r.state [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|r.bank[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~7 .lut_mask = 16'hF000; +defparam \sdram_|r.bank[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N8 +cycloneive_lcell_comb \sdram_|r.bank[0]~11 ( +// Equation(s): +// \sdram_|r.bank[0]~11_combout = (\sdram_|r.rd_pending~q & ((\sdram_|Equal7~2_combout ) # ((\sdram_|r.bank[0]~7_combout )))) # (!\sdram_|r.rd_pending~q & (((\sdram_|r.wr_pending~q & \sdram_|r.bank[0]~7_combout )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.bank[0]~7_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~11 .lut_mask = 16'hFCA0; +defparam \sdram_|r.bank[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N28 +cycloneive_lcell_comb \sdram_|r.bank[0]~4 ( +// Equation(s): +// \sdram_|r.bank[0]~4_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q ))) + + .dataa(gnd), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~4 .lut_mask = 16'hF0C0; +defparam \sdram_|r.bank[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N28 +cycloneive_lcell_comb \sdram_|r.bank[0]~5 ( +// Equation(s): +// \sdram_|r.bank[0]~5_combout = (\sdram_|r.state [5] & (!\sdram_|r.state [4] & ((!\sdram_|r.bank[0]~4_combout ) # (!\sdram_|r.state [7])))) # (!\sdram_|r.state [5] & (((\sdram_|r.state [7])))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.bank[0]~4_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~5 .lut_mask = 16'h3474; +defparam \sdram_|r.bank[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N4 +cycloneive_lcell_comb \sdram_|r.bank[0]~6 ( +// Equation(s): +// \sdram_|r.bank[0]~6_combout = (\sdram_|r.state [8] & (((\sdram_|r.state [6])))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & ((!\sdram_|r.bank[0]~5_combout ) # (!\sdram_|r.state [6]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [6]) # +// (\sdram_|r.bank[0]~5_combout ))))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.bank[0]~5_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~6 .lut_mask = 16'hB5F4; +defparam \sdram_|r.bank[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N28 +cycloneive_lcell_comb \sdram_|r.bank[0]~8 ( +// Equation(s): +// \sdram_|r.bank[0]~8_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] & \sdram_|r.state [7])) # (!\sdram_|r.state [5] & (!\sdram_|r.state [4] & !\sdram_|r.state [7])) + + .dataa(gnd), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.bank[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~8 .lut_mask = 16'hC003; +defparam \sdram_|r.bank[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N18 +cycloneive_lcell_comb \sdram_|r.bank[0]~12 ( +// Equation(s): +// \sdram_|r.bank[0]~12_combout = (\sdram_|r.bank[0]~8_combout & ((\sdram_|r.bank[0]~11_combout ) # ((\sdram_|Equal7~2_combout & \sdram_|r.wr_pending~q )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.bank[0]~11_combout ), + .datad(\sdram_|r.bank[0]~8_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~12 .lut_mask = 16'hF800; +defparam \sdram_|r.bank[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N2 +cycloneive_lcell_comb \sdram_|r.bank[0]~9 ( +// Equation(s): +// \sdram_|r.bank[0]~9_combout = (\sdram_|r.state [8] & (\sdram_|r.bank[0]~12_combout & ((\sdram_|r.bank[0]~11_combout ) # (!\sdram_|r.bank[0]~6_combout )))) # (!\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~6_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.bank[0]~11_combout ), + .datac(\sdram_|r.bank[0]~6_combout ), + .datad(\sdram_|r.bank[0]~12_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~9 .lut_mask = 16'h8F05; +defparam \sdram_|r.bank[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X11_Y0_N18 +dffeas \sdram_|r.bank[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux26~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.bank[0]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.bank [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.bank[0] .is_wysiwyg = "true"; +defparam \sdram_|r.bank[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N2 +cycloneive_lcell_comb \sdram_|Mux25~4 ( +// Equation(s): +// \sdram_|Mux25~4_combout = (!\sdram_|r.address[3]~6_combout & ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [10]), + .datac(gnd), + .datad(\sdram_|r.address[3]~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux25~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux25~4 .lut_mask = 16'h00DD; +defparam \sdram_|Mux25~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X7_Y0_N11 +dffeas \sdram_|r.bank[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux25~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.bank[0]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.bank [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.bank[1] .is_wysiwyg = "true"; +defparam \sdram_|r.bank[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N6 +cycloneive_lcell_comb \sdram_|Mux24~5 ( +// Equation(s): +// \sdram_|Mux24~5_combout = (!\sdram_|r.state [6] & (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|Equal7~2_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux24~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~5 .lut_mask = 16'h0515; +defparam \sdram_|Mux24~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N24 +cycloneive_lcell_comb \sdram_|Mux71~0 ( +// Equation(s): +// \sdram_|Mux71~0_combout = (!\sdram_|r.state [4] & !\sdram_|r.state [5]) + + .dataa(gnd), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [5]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|Mux71~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~0 .lut_mask = 16'h0303; +defparam \sdram_|Mux71~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N4 +cycloneive_lcell_comb \sdram_|process_0~7 ( +// Equation(s): +// \sdram_|process_0~7_combout = \sdram_|r.act_row [4] $ (((\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\sdram_|r.act_row [4]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\sdram_|process_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~7 .lut_mask = 16'h3C0F; +defparam \sdram_|process_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N28 +cycloneive_lcell_comb \sdram_|process_0~4 ( +// Equation(s): +// \sdram_|process_0~4_combout = ((\sdram_|process_0~7_combout ) # ((!\sdram_|Equal7~0_combout ) # (!\sdram_|Equal7~1_combout ))) # (!\sdram_|r.rd_pending~q ) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|process_0~7_combout ), + .datac(\sdram_|Equal7~1_combout ), + .datad(\sdram_|Equal7~0_combout ), + .cin(gnd), + .combout(\sdram_|process_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~4 .lut_mask = 16'hDFFF; +defparam \sdram_|process_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N30 +cycloneive_lcell_comb \sdram_|Mux71~1 ( +// Equation(s): +// \sdram_|Mux71~1_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [6]) # ((!\sdram_|r.state [4]) # (!\sdram_|r.state [5])))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [6] & ((\sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux71~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~1 .lut_mask = 16'h9BAA; +defparam \sdram_|Mux71~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N28 +cycloneive_lcell_comb \sdram_|Mux71~2 ( +// Equation(s): +// \sdram_|Mux71~2_combout = (\sdram_|r.state [7] & ((\sdram_|Mux71~1_combout ) # ((!\sdram_|r.state [8] & \sdram_|Mux71~0_combout )))) # (!\sdram_|r.state [7] & (!\sdram_|r.state [8])) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux71~1_combout ), + .datad(\sdram_|Mux71~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux71~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~2 .lut_mask = 16'hD5D1; +defparam \sdram_|Mux71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N14 +cycloneive_lcell_comb \sdram_|Mux71~3 ( +// Equation(s): +// \sdram_|Mux71~3_combout = (\sdram_|Mux71~2_combout ) # ((\sdram_|process_0~4_combout & (\sdram_|Mux71~0_combout & \sdram_|r.state [6]))) + + .dataa(\sdram_|process_0~4_combout ), + .datab(\sdram_|Mux71~0_combout ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux71~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux71~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~3 .lut_mask = 16'hFF80; +defparam \sdram_|Mux71~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N4 +cycloneive_lcell_comb \sdram_|Mux71~4 ( +// Equation(s): +// \sdram_|Mux71~4_combout = (\sdram_|Mux71~3_combout ) # ((\sdram_|Mux24~5_combout & ((\sdram_|Mux71~0_combout ) # (\sdram_|r.state [7])))) + + .dataa(\sdram_|Mux24~5_combout ), + .datab(\sdram_|Mux71~0_combout ), + .datac(\sdram_|Mux71~3_combout ), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux71~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~4 .lut_mask = 16'hFAF8; +defparam \sdram_|Mux71~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X14_Y0_N11 +dffeas \sdram_|r.dq_masks[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux71~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.dq_masks [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.dq_masks[0] .is_wysiwyg = "true"; +defparam \sdram_|r.dq_masks[0] .power_up = "low"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X14_Y0_N18 +dffeas \sdram_|r.dq_masks[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux71~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.dq_masks [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.dq_masks[1] .is_wysiwyg = "true"; +defparam \sdram_|r.dq_masks[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N2 +cycloneive_lcell_comb \sdram_|r.bank[0]~10 ( +// Equation(s): +// \sdram_|r.bank[0]~10_combout = \sdram_|r.state [5] $ (\sdram_|r.state [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.bank[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~10 .lut_mask = 16'h0FF0; +defparam \sdram_|r.bank[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N18 +cycloneive_lcell_comb \sdram_|Mux9~3 ( +// Equation(s): +// \sdram_|Mux9~3_combout = (\sdram_|r.bank[0]~10_combout ) # ((!\sdram_|n~2_combout & (\sdram_|r.state [6] & \sdram_|r.state [4]))) + + .dataa(\sdram_|n~2_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.bank[0]~10_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~3 .lut_mask = 16'hFF40; +defparam \sdram_|Mux9~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N30 +cycloneive_lcell_comb \sdram_|n~5 ( +// Equation(s): +// \sdram_|n~5_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|Equal7~2_combout ) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|n~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|n~5 .lut_mask = 16'h3031; +defparam \sdram_|n~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N12 +cycloneive_lcell_comb \sdram_|Mux9~4 ( +// Equation(s): +// \sdram_|Mux9~4_combout = (\sdram_|Mux9~3_combout ) # ((\sdram_|r.state [7] & (\sdram_|n~5_combout & !\sdram_|r.state [6]))) + + .dataa(\sdram_|Mux9~3_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|n~5_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux9~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~4 .lut_mask = 16'hAAEA; +defparam \sdram_|Mux9~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N4 +cycloneive_lcell_comb \sdram_|Mux9~2 ( +// Equation(s): +// \sdram_|Mux9~2_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [4] & (!\sdram_|r.state [7])) # (!\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (\sdram_|n~5_combout ))))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|n~5_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux9~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~2 .lut_mask = 16'h7600; +defparam \sdram_|Mux9~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N30 +cycloneive_lcell_comb \sdram_|Equal2~3 ( +// Equation(s): +// \sdram_|Equal2~3_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [0] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [7]))) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [0]), + .datac(\sdram_|Equal2~2_combout ), + .datad(\sdram_|r.init_counter [7]), + .cin(gnd), + .combout(\sdram_|Equal2~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~3 .lut_mask = 16'h2000; +defparam \sdram_|Equal2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N8 +cycloneive_lcell_comb \sdram_|Mux10~2 ( +// Equation(s): +// \sdram_|Mux10~2_combout = (\sdram_|r.init_counter [6]) # ((\sdram_|r.init_counter [5]) # (\sdram_|r.init_counter [4])) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [6]), + .datac(\sdram_|r.init_counter [5]), + .datad(\sdram_|r.init_counter [4]), + .cin(gnd), + .combout(\sdram_|Mux10~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~2 .lut_mask = 16'hFFFC; +defparam \sdram_|Mux10~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N26 +cycloneive_lcell_comb \sdram_|Mux10~3 ( +// Equation(s): +// \sdram_|Mux10~3_combout = (\sdram_|r.init_counter [1] & ((\sdram_|r.init_counter [2] & (!\sdram_|r.init_counter [3])) # (!\sdram_|r.init_counter [2] & (\sdram_|r.init_counter [3] & !\sdram_|Mux10~2_combout )))) + + .dataa(\sdram_|r.init_counter [2]), + .datab(\sdram_|r.init_counter [3]), + .datac(\sdram_|Mux10~2_combout ), + .datad(\sdram_|r.init_counter [1]), + .cin(gnd), + .combout(\sdram_|Mux10~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~3 .lut_mask = 16'h2600; +defparam \sdram_|Mux10~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N4 +cycloneive_lcell_comb \sdram_|process_0~6 ( +// Equation(s): +// \sdram_|process_0~6_combout = (!\sdram_|r.init_counter [9] & (!\sdram_|r.init_counter [8] & (\sdram_|process_0~5_combout & !\sdram_|r.init_counter [10]))) + + .dataa(\sdram_|r.init_counter [9]), + .datab(\sdram_|r.init_counter [8]), + .datac(\sdram_|process_0~5_combout ), + .datad(\sdram_|r.init_counter [10]), + .cin(gnd), + .combout(\sdram_|process_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~6 .lut_mask = 16'h0010; +defparam \sdram_|process_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N24 +cycloneive_lcell_comb \sdram_|Mux10~4 ( +// Equation(s): +// \sdram_|Mux10~4_combout = ((\sdram_|r.init_counter [7]) # ((!\sdram_|r.init_counter [0]) # (!\sdram_|process_0~6_combout ))) # (!\sdram_|Mux10~3_combout ) + + .dataa(\sdram_|Mux10~3_combout ), + .datab(\sdram_|r.init_counter [7]), + .datac(\sdram_|process_0~6_combout ), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Mux10~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~4 .lut_mask = 16'hDFFF; +defparam \sdram_|Mux10~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N22 +cycloneive_lcell_comb \sdram_|Mux9~5 ( +// Equation(s): +// \sdram_|Mux9~5_combout = (\sdram_|r.state [6]) # ((\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|n~2_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|n~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~5 .lut_mask = 16'hEAEE; +defparam \sdram_|Mux9~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N20 +cycloneive_lcell_comb \sdram_|Mux7~0 ( +// Equation(s): +// \sdram_|Mux7~0_combout = (!\sdram_|r.state [7] & !\sdram_|r.state [4]) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(gnd), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~0 .lut_mask = 16'h0033; +defparam \sdram_|Mux7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N10 +cycloneive_lcell_comb \sdram_|Mux9~6 ( +// Equation(s): +// \sdram_|Mux9~6_combout = (\sdram_|Mux9~5_combout ) # ((!\sdram_|Equal2~3_combout & (\sdram_|Mux10~4_combout & \sdram_|Mux7~0_combout ))) + + .dataa(\sdram_|Equal2~3_combout ), + .datab(\sdram_|Mux10~4_combout ), + .datac(\sdram_|Mux9~5_combout ), + .datad(\sdram_|Mux7~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~6 .lut_mask = 16'hF4F0; +defparam \sdram_|Mux9~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N24 +cycloneive_lcell_comb \sdram_|Mux9~7 ( +// Equation(s): +// \sdram_|Mux9~7_combout = (\sdram_|Mux9~4_combout ) # ((\sdram_|Mux9~2_combout ) # ((!\sdram_|r.state [8] & \sdram_|Mux9~6_combout ))) + + .dataa(\sdram_|Mux9~4_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux9~2_combout ), + .datad(\sdram_|Mux9~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~7 .lut_mask = 16'hFBFA; +defparam \sdram_|Mux9~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y11_N4 +dffeas \sdram_|r.state[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux9~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[2] .is_wysiwyg = "true"; +defparam \sdram_|r.state[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N16 +cycloneive_lcell_comb \sdram_|Mux10~11 ( +// Equation(s): +// \sdram_|Mux10~11_combout = (\sdram_|r.rf_pending~q & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q )))) # (!\sdram_|r.rf_pending~q & (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|Equal7~2_combout ))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux10~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~11 .lut_mask = 16'hAF9D; +defparam \sdram_|Mux10~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N12 +cycloneive_lcell_comb \sdram_|Mux10~6 ( +// Equation(s): +// \sdram_|Mux10~6_combout = (\sdram_|r.state [6] & (((\sdram_|process_0~4_combout ) # (!\sdram_|r.state [8])))) # (!\sdram_|r.state [6] & (\sdram_|Mux10~11_combout & ((\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Mux10~11_combout ), + .datac(\sdram_|process_0~4_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux10~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~6 .lut_mask = 16'hE4AA; +defparam \sdram_|Mux10~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N26 +cycloneive_lcell_comb \sdram_|Mux10~5 ( +// Equation(s): +// \sdram_|Mux10~5_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [4]) # ((\sdram_|r.rf_pending~q )))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & (!\sdram_|r.rf_pending~q )) # (!\sdram_|r.state [4] & ((\sdram_|Mux10~4_combout ))))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Mux10~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~5 .lut_mask = 16'hBDAC; +defparam \sdram_|Mux10~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N10 +cycloneive_lcell_comb \sdram_|Mux10~7 ( +// Equation(s): +// \sdram_|Mux10~7_combout = (\sdram_|r.state [6] & (((!\sdram_|r.state [8]) # (!\sdram_|r.rf_pending~q )) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & ((\sdram_|r.rf_pending~q ) # (\sdram_|r.state [4] $ (\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux10~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~7 .lut_mask = 16'h7BFE; +defparam \sdram_|Mux10~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N20 +cycloneive_lcell_comb \sdram_|Mux10~8 ( +// Equation(s): +// \sdram_|Mux10~8_combout = (\sdram_|r.state [7] & ((\sdram_|Mux10~7_combout ) # ((\sdram_|Mux10~11_combout )))) # (!\sdram_|r.state [7] & (((\sdram_|Mux10~5_combout )))) + + .dataa(\sdram_|Mux10~7_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux10~5_combout ), + .datad(\sdram_|Mux10~11_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~8 .lut_mask = 16'hFCB8; +defparam \sdram_|Mux10~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N22 +cycloneive_lcell_comb \sdram_|Mux10~9 ( +// Equation(s): +// \sdram_|Mux10~9_combout = (\sdram_|r.bank[0]~10_combout ) # ((\sdram_|Mux10~8_combout ) # ((\sdram_|Mux10~6_combout & !\sdram_|Mux10~5_combout ))) + + .dataa(\sdram_|Mux10~6_combout ), + .datab(\sdram_|r.bank[0]~10_combout ), + .datac(\sdram_|Mux10~5_combout ), + .datad(\sdram_|Mux10~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~9 .lut_mask = 16'hFFCE; +defparam \sdram_|Mux10~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y11_N11 +dffeas \sdram_|r.state[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux10~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[1] .is_wysiwyg = "true"; +defparam \sdram_|r.state[1] .power_up = "low"; +// synopsys translate_on + +// Location: CLKCTRL_PLL1E0 +cycloneive_clkctrl \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [1]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK_outclk )); +// synopsys translate_off +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK .clock_type = "external clock output"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK .ena_register_mode = "double register"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N8 +cycloneive_lcell_comb \sdram_|Mux11~2 ( +// Equation(s): +// \sdram_|Mux11~2_combout = (\sdram_|r.init_counter [7] $ (!\sdram_|r.init_counter [0])) # (!\sdram_|r.init_counter [1]) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [7]), + .datac(gnd), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Mux11~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~2 .lut_mask = 16'hDD77; +defparam \sdram_|Mux11~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N6 +cycloneive_lcell_comb \sdram_|Mux11~3 ( +// Equation(s): +// \sdram_|Mux11~3_combout = (!\sdram_|r.state [8] & (!\sdram_|r.state [6] & ((\sdram_|Mux11~2_combout ) # (!\sdram_|Equal2~2_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Equal2~2_combout ), + .datac(\sdram_|Mux11~2_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux11~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~3 .lut_mask = 16'h0051; +defparam \sdram_|Mux11~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N26 +cycloneive_lcell_comb \sdram_|Mux11~4 ( +// Equation(s): +// \sdram_|Mux11~4_combout = (!\sdram_|r.state [7] & ((\sdram_|Mux11~3_combout ) # ((\sdram_|r.state [4] & !\sdram_|Mux23~0_combout )))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux23~0_combout ), + .datad(\sdram_|Mux11~3_combout ), + .cin(gnd), + .combout(\sdram_|Mux11~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~4 .lut_mask = 16'h3302; +defparam \sdram_|Mux11~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N28 +cycloneive_lcell_comb \sdram_|Mux11~5 ( +// Equation(s): +// \sdram_|Mux11~5_combout = (\sdram_|r.state [7] & ((\sdram_|r.state [4] $ (\sdram_|r.state [8])) # (!\sdram_|r.state [5]))) # (!\sdram_|r.state [7] & (((\sdram_|r.state [5])))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux11~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~5 .lut_mask = 16'h7CBC; +defparam \sdram_|Mux11~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N0 +cycloneive_lcell_comb \sdram_|Mux11~6 ( +// Equation(s): +// \sdram_|Mux11~6_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|r.state [7]) # ((!\sdram_|r.state [6] & \sdram_|r.state [8])))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux11~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~6 .lut_mask = 16'h4544; +defparam \sdram_|Mux11~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N30 +cycloneive_lcell_comb \sdram_|Mux11~7 ( +// Equation(s): +// \sdram_|Mux11~7_combout = (!\sdram_|r.wr_pending~q & (\sdram_|Mux11~6_combout & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.rd_pending~q )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Mux11~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux11~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~7 .lut_mask = 16'h2300; +defparam \sdram_|Mux11~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N16 +cycloneive_lcell_comb \sdram_|Mux11~9 ( +// Equation(s): +// \sdram_|Mux11~9_combout = (\sdram_|r.state [6] & (((\sdram_|n~5_combout ) # (!\sdram_|Mux7~0_combout )) # (!\sdram_|r.state [8]))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|n~5_combout ), + .datad(\sdram_|Mux7~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux11~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~9 .lut_mask = 16'hA2AA; +defparam \sdram_|Mux11~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N14 +cycloneive_lcell_comb \sdram_|Mux11~8 ( +// Equation(s): +// \sdram_|Mux11~8_combout = (\sdram_|Mux11~4_combout ) # ((\sdram_|Mux11~5_combout ) # ((\sdram_|Mux11~7_combout ) # (\sdram_|Mux11~9_combout ))) + + .dataa(\sdram_|Mux11~4_combout ), + .datab(\sdram_|Mux11~5_combout ), + .datac(\sdram_|Mux11~7_combout ), + .datad(\sdram_|Mux11~9_combout ), + .cin(gnd), + .combout(\sdram_|Mux11~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~8 .lut_mask = 16'hFFFE; +defparam \sdram_|Mux11~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y27_N4 +dffeas \sdram_|r.state[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux11~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[0] .is_wysiwyg = "true"; +defparam \sdram_|r.state[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N20 +cycloneive_lcell_comb \sdram_|Mux24~2 ( +// Equation(s): +// \sdram_|Mux24~2_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q & !\sdram_|r.state [6])))) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux24~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~2 .lut_mask = 16'hCE00; +defparam \sdram_|Mux24~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N2 +cycloneive_lcell_comb \sdram_|r.address[0]~7 ( +// Equation(s): +// \sdram_|r.address[0]~7_combout = (\sdram_|r.state [4] & ((\sdram_|process_0~2_combout & (\z80_|address_pins_|abus[11]~19_combout )) # (!\sdram_|process_0~2_combout & ((\sdram_|r.address[0]~_Duplicate_1_q ))))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\sdram_|r.address[0]~_Duplicate_1_q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|r.address[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[0]~7 .lut_mask = 16'hA0C0; +defparam \sdram_|r.address[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N12 +cycloneive_lcell_comb \sdram_|r.address[0]~0 ( +// Equation(s): +// \sdram_|r.address[0]~0_combout = (\sdram_|r.state [8] & (!\sdram_|Mux24~2_combout & (\sdram_|r.address[0]~_Duplicate_1_q ))) # (!\sdram_|r.state [8] & (((\sdram_|r.address[0]~7_combout )))) + + .dataa(\sdram_|Mux24~2_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.address[0]~_Duplicate_1_q ), + .datad(\sdram_|r.address[0]~7_combout ), + .cin(gnd), + .combout(\sdram_|r.address[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[0]~0 .lut_mask = 16'h7340; +defparam \sdram_|r.address[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N30 +cycloneive_lcell_comb \sdram_|Mux13~9 ( +// Equation(s): +// \sdram_|Mux13~9_combout = (!\sdram_|r.state [5] & ((\sdram_|r.state [8] & (!\sdram_|r.state [4])) # (!\sdram_|r.state [8] & ((!\sdram_|r.state [6]))))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux13~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~9 .lut_mask = 16'h0407; +defparam \sdram_|Mux13~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N0 +cycloneive_lcell_comb \sdram_|Mux13~4 ( +// Equation(s): +// \sdram_|Mux13~4_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] & (\sdram_|r.state [8] $ (!\sdram_|r.state [5])))) # (!\sdram_|r.state [6] & (\sdram_|r.state [5] & (\sdram_|r.state [4] $ (!\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux13~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~4 .lut_mask = 16'h8290; +defparam \sdram_|Mux13~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N2 +cycloneive_lcell_comb \sdram_|Mux13~5 ( +// Equation(s): +// \sdram_|Mux13~5_combout = (\sdram_|r.state [7] & ((\sdram_|Mux13~4_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux13~9_combout )) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux13~9_combout ), + .datad(\sdram_|Mux13~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux13~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~5 .lut_mask = 16'hFC30; +defparam \sdram_|Mux13~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y11_N13 +dffeas \sdram_|r.address[0]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[0]~0_combout ), + .asdata(\sdram_|Mux24~4_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\sdram_|r.state [7]), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[0]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[0]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[0]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N4 +cycloneive_lcell_comb \sdram_|Mux24~3 ( +// Equation(s): +// \sdram_|Mux24~3_combout = (\sdram_|Mux23~0_combout & ((\sdram_|process_0~2_combout & (\z80_|address_pins_|abus[11]~19_combout )) # (!\sdram_|process_0~2_combout & ((\sdram_|r.address[0]~_Duplicate_1_q ))))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\sdram_|r.address[0]~_Duplicate_1_q ), + .datac(\sdram_|Mux23~0_combout ), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux24~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~3 .lut_mask = 16'hA0C0; +defparam \sdram_|Mux24~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N14 +cycloneive_lcell_comb \sdram_|Mux24~4 ( +// Equation(s): +// \sdram_|Mux24~4_combout = (\sdram_|Mux24~3_combout ) # ((!\sdram_|n~3_combout & (\sdram_|r.address[0]~_Duplicate_1_q & !\sdram_|r.state [6]))) + + .dataa(\sdram_|n~3_combout ), + .datab(\sdram_|r.address[0]~_Duplicate_1_q ), + .datac(\sdram_|Mux24~3_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux24~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~4 .lut_mask = 16'hF0F4; +defparam \sdram_|Mux24~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N24 +cycloneive_lcell_comb \sdram_|r.address[0]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[0]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux24~4_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[0]~0_combout ))) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux24~4_combout ), + .datad(\sdram_|r.address[0]~0_combout ), + .cin(gnd), + .combout(\sdram_|r.address[0]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[0]~SLOAD_MUX .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[0]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y4_N18 +dffeas \sdram_|r.address[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[0]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[0] .is_wysiwyg = "true"; +defparam \sdram_|r.address[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N16 +cycloneive_lcell_comb \sdram_|r.address[1]~_Duplicate_1feeder ( +// Equation(s): +// \sdram_|r.address[1]~_Duplicate_1feeder_combout = \sdram_|r.address[1]~1_combout + + .dataa(\sdram_|r.address[1]~1_combout ), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[1]~_Duplicate_1feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~_Duplicate_1feeder .lut_mask = 16'hAAAA; +defparam \sdram_|r.address[1]~_Duplicate_1feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N20 +cycloneive_lcell_comb \sdram_|Mux23~4 ( +// Equation(s): +// \sdram_|Mux23~4_combout = (\sdram_|r.state [8] & (\sdram_|r.address[1]~_Duplicate_1_q )) # (!\sdram_|r.state [8] & ((\sdram_|process_0~2_combout & ((\z80_|address_pins_|abus[12]~24_combout ))) # (!\sdram_|process_0~2_combout & +// (\sdram_|r.address[1]~_Duplicate_1_q )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.address[1]~_Duplicate_1_q ), + .datac(\z80_|address_pins_|abus[12]~24_combout ), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux23~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~4 .lut_mask = 16'hD8CC; +defparam \sdram_|Mux23~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N16 +cycloneive_lcell_comb \sdram_|Equal5~0 ( +// Equation(s): +// \sdram_|Equal5~0_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [0]))) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [7]), + .datac(\sdram_|Equal2~2_combout ), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Equal5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal5~0 .lut_mask = 16'h2000; +defparam \sdram_|Equal5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N14 +cycloneive_lcell_comb \sdram_|Mux23~5 ( +// Equation(s): +// \sdram_|Mux23~5_combout = (\sdram_|r.state [8] & (\sdram_|Mux23~4_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & (\sdram_|Mux23~4_combout )) # (!\sdram_|r.state [4] & ((\sdram_|Equal5~0_combout ))))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux23~4_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|Equal5~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux23~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~5 .lut_mask = 16'hCDC8; +defparam \sdram_|Mux23~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N8 +cycloneive_lcell_comb \sdram_|Mux23~6 ( +// Equation(s): +// \sdram_|Mux23~6_combout = (\sdram_|Mux23~5_combout & (((\sdram_|r.state [4]) # (!\sdram_|Mux24~2_combout )) # (!\sdram_|r.state [8]))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|Mux23~5_combout ), + .datad(\sdram_|Mux24~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux23~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~6 .lut_mask = 16'hD0F0; +defparam \sdram_|Mux23~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N2 +cycloneive_lcell_comb \sdram_|Mux19~0 ( +// Equation(s): +// \sdram_|Mux19~0_combout = (\sdram_|r.state [7] & (\sdram_|r.state [5] $ (((!\sdram_|r.state [8] & \sdram_|r.state [6]))))) # (!\sdram_|r.state [7] & (!\sdram_|r.state [5] & ((\sdram_|r.state [8]) # (!\sdram_|r.state [6])))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [5]), + .cin(gnd), + .combout(\sdram_|Mux19~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~0 .lut_mask = 16'h8C63; +defparam \sdram_|Mux19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y12_N17 +dffeas \sdram_|r.address[1]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[1]~_Duplicate_1feeder_combout ), + .asdata(\sdram_|Mux23~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(!\sdram_|r.state [7]), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[1]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[1]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[1]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N28 +cycloneive_lcell_comb \sdram_|Mux23~2 ( +// Equation(s): +// \sdram_|Mux23~2_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] & ((\sdram_|process_0~2_combout ) # (!\sdram_|r.state [8])))) # (!\sdram_|r.state [6] & (\sdram_|process_0~2_combout & (\sdram_|r.state [4] $ (!\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|process_0~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux23~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~2 .lut_mask = 16'hC0A4; +defparam \sdram_|Mux23~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N30 +cycloneive_lcell_comb \sdram_|Mux23~3 ( +// Equation(s): +// \sdram_|Mux23~3_combout = (\sdram_|Mux23~2_combout & ((\sdram_|r.state [6]) # (\sdram_|Equal7~2_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|Mux23~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux23~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~3 .lut_mask = 16'hFA00; +defparam \sdram_|Mux23~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N18 +cycloneive_lcell_comb \sdram_|Mux23~1 ( +// Equation(s): +// \sdram_|Mux23~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [8] & ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) + + .dataa(\sdram_|r.state [6]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [12]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux23~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~1 .lut_mask = 16'hA200; +defparam \sdram_|Mux23~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N22 +cycloneive_lcell_comb \sdram_|r.address[1]~1 ( +// Equation(s): +// \sdram_|r.address[1]~1_combout = (\sdram_|Mux23~3_combout & ((\sdram_|Mux23~1_combout ))) # (!\sdram_|Mux23~3_combout & (\sdram_|r.address[1]~_Duplicate_1_q )) + + .dataa(gnd), + .datab(\sdram_|r.address[1]~_Duplicate_1_q ), + .datac(\sdram_|Mux23~3_combout ), + .datad(\sdram_|Mux23~1_combout ), + .cin(gnd), + .combout(\sdram_|r.address[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~1 .lut_mask = 16'hFC0C; +defparam \sdram_|r.address[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N2 +cycloneive_lcell_comb \sdram_|r.address[1]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[1]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|r.address[1]~1_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux23~6_combout ))) + + .dataa(\sdram_|r.address[1]~1_combout ), + .datab(\sdram_|Mux23~6_combout ), + .datac(\sdram_|r.state [7]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[1]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~SLOAD_MUX .lut_mask = 16'hACAC; +defparam \sdram_|r.address[1]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X5_Y0_N11 +dffeas \sdram_|r.address[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[1]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[1] .is_wysiwyg = "true"; +defparam \sdram_|r.address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N10 +cycloneive_lcell_comb \sdram_|r.address[3]~8 ( +// Equation(s): +// \sdram_|r.address[3]~8_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [5])) # (!\sdram_|r.state [6] & (((\sdram_|r.state [7]) # (\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.address[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~8 .lut_mask = 16'h7772; +defparam \sdram_|r.address[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N24 +cycloneive_lcell_comb \sdram_|r.address[3]~9 ( +// Equation(s): +// \sdram_|r.address[3]~9_combout = (\sdram_|r.state [5] & \sdram_|r.state [6]) + + .dataa(gnd), + .datab(\sdram_|r.state [5]), + .datac(gnd), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|r.address[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~9 .lut_mask = 16'hCC00; +defparam \sdram_|r.address[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N26 +cycloneive_lcell_comb \sdram_|Mux21~0 ( +// Equation(s): +// \sdram_|Mux21~0_combout = (!\sdram_|r.address[3]~8_combout & ((\sdram_|r.address[3]~9_combout ) # ((\sdram_|r.address[3]~6_combout & \sdram_|r.state [4])))) + + .dataa(\sdram_|r.address[3]~6_combout ), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.address[3]~9_combout ), + .datad(\sdram_|r.address[3]~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux21~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux21~0 .lut_mask = 16'h00F8; +defparam \sdram_|Mux21~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N18 +cycloneive_lcell_comb \sdram_|Mux22~0 ( +// Equation(s): +// \sdram_|Mux22~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|abus[1]~25_combout ) # ((\z80_|address_pins_|abus[13]~23_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~8_combout & +// (((\z80_|address_pins_|abus[13]~23_combout & \sdram_|Mux21~0_combout )))) + + .dataa(\sdram_|r.address[3]~8_combout ), + .datab(\z80_|address_pins_|abus[1]~25_combout ), + .datac(\z80_|address_pins_|abus[13]~23_combout ), + .datad(\sdram_|Mux21~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux22~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux22~0 .lut_mask = 16'hF888; +defparam \sdram_|Mux22~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N20 +cycloneive_lcell_comb \sdram_|r.address[3]~10 ( +// Equation(s): +// \sdram_|r.address[3]~10_combout = (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|r.state [7])) # (!\sdram_|r.state [4]) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|r.address[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~10 .lut_mask = 16'h777F; +defparam \sdram_|r.address[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N14 +cycloneive_lcell_comb \sdram_|r.address[3]~11 ( +// Equation(s): +// \sdram_|r.address[3]~11_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [7]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|r.rd_pending~q ))) + + .dataa(gnd), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.address[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~11 .lut_mask = 16'h0FF3; +defparam \sdram_|r.address[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N0 +cycloneive_lcell_comb \sdram_|r.address[3]~12 ( +// Equation(s): +// \sdram_|r.address[3]~12_combout = (\sdram_|r.address[3]~11_combout ) # ((\sdram_|r.state [4] & ((\sdram_|r.state [8]))) # (!\sdram_|r.state [4] & ((!\sdram_|r.state [8]) # (!\sdram_|Equal7~2_combout )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.address[3]~11_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.address[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~12 .lut_mask = 16'hFDCF; +defparam \sdram_|r.address[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N6 +cycloneive_lcell_comb \sdram_|r.address[3]~13 ( +// Equation(s): +// \sdram_|r.address[3]~13_combout = (\sdram_|r.state [5] & (((\sdram_|r.address[3]~10_combout )) # (!\sdram_|r.state [8]))) # (!\sdram_|r.state [5] & (((\sdram_|r.address[3]~12_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.address[3]~10_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.address[3]~12_combout ), + .cin(gnd), + .combout(\sdram_|r.address[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~13 .lut_mask = 16'hDFD0; +defparam \sdram_|r.address[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N16 +cycloneive_lcell_comb \sdram_|r.address[3]~14 ( +// Equation(s): +// \sdram_|r.address[3]~14_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [7]) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) # (!\sdram_|r.state [4] & (\sdram_|r.state [7] & (!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q ))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|r.address[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~14 .lut_mask = 16'h888E; +defparam \sdram_|r.address[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N22 +cycloneive_lcell_comb \sdram_|r.address[3]~15 ( +// Equation(s): +// \sdram_|r.address[3]~15_combout = (\sdram_|r.address[3]~14_combout ) # ((\sdram_|r.state [5] & ((!\sdram_|r.state [7]) # (!\sdram_|Equal7~2_combout ))) # (!\sdram_|r.state [5] & ((\sdram_|r.state [7])))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.address[3]~14_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.address[3]~15_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~15 .lut_mask = 16'hDFFC; +defparam \sdram_|r.address[3]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N24 +cycloneive_lcell_comb \sdram_|r.address[3]~16 ( +// Equation(s): +// \sdram_|r.address[3]~16_combout = (\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~8_combout )) # (!\sdram_|n~3_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|r.address[3]~15_combout )))) + + .dataa(\sdram_|n~3_combout ), + .datab(\sdram_|r.bank[0]~8_combout ), + .datac(\sdram_|r.address[3]~15_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.address[3]~16_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~16 .lut_mask = 16'h77F0; +defparam \sdram_|r.address[3]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N26 +cycloneive_lcell_comb \sdram_|r.address[3]~17 ( +// Equation(s): +// \sdram_|r.address[3]~17_combout = (\sdram_|r.state [6] & (!\sdram_|r.address[3]~13_combout )) # (!\sdram_|r.state [6] & ((!\sdram_|r.address[3]~16_combout ))) + + .dataa(\sdram_|r.address[3]~13_combout ), + .datab(gnd), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.address[3]~16_combout ), + .cin(gnd), + .combout(\sdram_|r.address[3]~17_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~17 .lut_mask = 16'h505F; +defparam \sdram_|r.address[3]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X5_Y0_N4 +dffeas \sdram_|r.address[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux22~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[2] .is_wysiwyg = "true"; +defparam \sdram_|r.address[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N2 +cycloneive_lcell_comb \sdram_|Mux21~1 ( +// Equation(s): +// \sdram_|Mux21~1_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|abus[2]~26_combout ) # ((\z80_|address_pins_|abus[14]~22_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~8_combout & +// (((\z80_|address_pins_|abus[14]~22_combout & \sdram_|Mux21~0_combout )))) + + .dataa(\sdram_|r.address[3]~8_combout ), + .datab(\z80_|address_pins_|abus[2]~26_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\sdram_|Mux21~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux21~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux21~1 .lut_mask = 16'hF888; +defparam \sdram_|Mux21~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X20_Y0_N11 +dffeas \sdram_|r.address[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux21~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[3] .is_wysiwyg = "true"; +defparam \sdram_|r.address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N22 +cycloneive_lcell_comb \sdram_|Mux20~4 ( +// Equation(s): +// \sdram_|Mux20~4_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & \sdram_|r.init_counter [0])) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [7]), + .datac(gnd), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Mux20~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~4 .lut_mask = 16'h2200; +defparam \sdram_|Mux20~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N26 +cycloneive_lcell_comb \sdram_|Mux20~7 ( +// Equation(s): +// \sdram_|Mux20~7_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\sdram_|r.state [6] & (!\z80_|address_pins_|DFFE_apin_latch [15])) # (!\sdram_|r.state [6] & ((!\z80_|address_pins_|DFFE_apin_latch [3]))))) + + .dataa(\sdram_|r.state [6]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\z80_|address_pins_|DFFE_apin_latch [3]), + .cin(gnd), + .combout(\sdram_|Mux20~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~7 .lut_mask = 16'h084C; +defparam \sdram_|Mux20~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N10 +cycloneive_lcell_comb \sdram_|Mux23~7 ( +// Equation(s): +// \sdram_|Mux23~7_combout = (\sdram_|r.state [4] & (\sdram_|process_0~2_combout & ((\sdram_|r.state [6]) # (\sdram_|Equal7~2_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux23~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~7 .lut_mask = 16'hE000; +defparam \sdram_|Mux23~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N10 +cycloneive_lcell_comb \sdram_|Mux20~8 ( +// Equation(s): +// \sdram_|Mux20~8_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] $ (((\sdram_|r.state [8]))))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [4] & (\sdram_|n~3_combout & !\sdram_|r.state [8]))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|n~3_combout ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux20~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~8 .lut_mask = 16'h50A4; +defparam \sdram_|Mux20~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N18 +cycloneive_lcell_comb \sdram_|Mux20~10 ( +// Equation(s): +// \sdram_|Mux20~10_combout = (\sdram_|r.state [8] & (\sdram_|Mux20~7_combout & (\sdram_|Mux23~7_combout & !\sdram_|Mux20~8_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux20~8_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux20~7_combout ), + .datac(\sdram_|Mux23~7_combout ), + .datad(\sdram_|Mux20~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~10 .lut_mask = 16'h5580; +defparam \sdram_|Mux20~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N0 +cycloneive_lcell_comb \sdram_|Mux20~9 ( +// Equation(s): +// \sdram_|Mux20~9_combout = (\sdram_|r.state [8] & (!\sdram_|Mux20~7_combout & (\sdram_|Mux23~7_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux20~8_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux20~7_combout ), + .datac(\sdram_|Mux23~7_combout ), + .datad(\sdram_|Mux20~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~9 .lut_mask = 16'h7520; +defparam \sdram_|Mux20~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N24 +cycloneive_lcell_comb \sdram_|Mux20~11 ( +// Equation(s): +// \sdram_|Mux20~11_combout = (\sdram_|Mux20~10_combout & (((\z80_|address_pins_|abus[3]~27_combout & \sdram_|Mux20~9_combout )))) # (!\sdram_|Mux20~10_combout & ((\sdram_|r.address[4]~_Duplicate_1_q ) # ((\sdram_|Mux20~9_combout )))) + + .dataa(\sdram_|r.address[4]~_Duplicate_1_q ), + .datab(\z80_|address_pins_|abus[3]~27_combout ), + .datac(\sdram_|Mux20~10_combout ), + .datad(\sdram_|Mux20~9_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~11 .lut_mask = 16'hCF0A; +defparam \sdram_|Mux20~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y11_N5 +dffeas \sdram_|r.address[4]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[4]~2_combout ), + .asdata(\sdram_|Mux20~11_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\sdram_|r.state [7]), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[4]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[4]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[4]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N2 +cycloneive_lcell_comb \sdram_|Mux20~12 ( +// Equation(s): +// \sdram_|Mux20~12_combout = (\sdram_|process_0~2_combout & (((\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) # (!\sdram_|process_0~2_combout & (\sdram_|r.address[4]~_Duplicate_1_q )) + + .dataa(\sdram_|r.address[4]~_Duplicate_1_q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~12 .lut_mask = 16'hCFAA; +defparam \sdram_|Mux20~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N4 +cycloneive_lcell_comb \sdram_|Mux20~5 ( +// Equation(s): +// \sdram_|Mux20~5_combout = (\sdram_|r.state [4] & (((\sdram_|Mux20~12_combout )))) # (!\sdram_|r.state [4] & (\sdram_|Mux20~4_combout & (\sdram_|Equal2~2_combout ))) + + .dataa(\sdram_|Mux20~4_combout ), + .datab(\sdram_|Equal2~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|Mux20~12_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~5 .lut_mask = 16'hF808; +defparam \sdram_|Mux20~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N16 +cycloneive_lcell_comb \sdram_|Mux20~6 ( +// Equation(s): +// \sdram_|Mux20~6_combout = (\sdram_|Mux24~2_combout & ((\sdram_|r.state [4] & ((\sdram_|r.address[4]~_Duplicate_1_q ))) # (!\sdram_|r.state [4] & (\z80_|address_pins_|abus[3]~27_combout )))) # (!\sdram_|Mux24~2_combout & +// (((\sdram_|r.address[4]~_Duplicate_1_q )))) + + .dataa(\sdram_|Mux24~2_combout ), + .datab(\z80_|address_pins_|abus[3]~27_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.address[4]~_Duplicate_1_q ), + .cin(gnd), + .combout(\sdram_|Mux20~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~6 .lut_mask = 16'hFD08; +defparam \sdram_|Mux20~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N4 +cycloneive_lcell_comb \sdram_|r.address[4]~2 ( +// Equation(s): +// \sdram_|r.address[4]~2_combout = (\sdram_|r.state [8] & ((\sdram_|Mux20~6_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux20~5_combout )) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux20~5_combout ), + .datac(gnd), + .datad(\sdram_|Mux20~6_combout ), + .cin(gnd), + .combout(\sdram_|r.address[4]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[4]~2 .lut_mask = 16'hEE44; +defparam \sdram_|r.address[4]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N8 +cycloneive_lcell_comb \sdram_|r.address[4]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[4]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux20~11_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[4]~2_combout )) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.address[4]~2_combout ), + .datad(\sdram_|Mux20~11_combout ), + .cin(gnd), + .combout(\sdram_|r.address[4]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[4]~SLOAD_MUX .lut_mask = 16'hFC30; +defparam \sdram_|r.address[4]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X25_Y0_N18 +dffeas \sdram_|r.address[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[4]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[4] .is_wysiwyg = "true"; +defparam \sdram_|r.address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N26 +cycloneive_lcell_comb \sdram_|Mux19~1 ( +// Equation(s): +// \sdram_|Mux19~1_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [0]))) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [7]), + .datac(\sdram_|Equal2~2_combout ), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Mux19~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~1 .lut_mask = 16'h2000; +defparam \sdram_|Mux19~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N12 +cycloneive_lcell_comb \sdram_|Mux19~4 ( +// Equation(s): +// \sdram_|Mux19~4_combout = (\sdram_|r.state [8] & (\sdram_|Mux23~7_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.bank[0]~4_combout ))) + + .dataa(\sdram_|r.state [8]), + .datab(gnd), + .datac(\sdram_|Mux23~7_combout ), + .datad(\sdram_|r.bank[0]~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux19~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~4 .lut_mask = 16'hF5A0; +defparam \sdram_|Mux19~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N22 +cycloneive_lcell_comb \sdram_|Mux19~5 ( +// Equation(s): +// \sdram_|Mux19~5_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [8] & (\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & (\sdram_|Mux19~4_combout & ((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux19~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux19~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~5 .lut_mask = 16'h4B40; +defparam \sdram_|Mux19~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N20 +cycloneive_lcell_comb \sdram_|Mux19~6 ( +// Equation(s): +// \sdram_|Mux19~6_combout = (\sdram_|r.state [8] & (\sdram_|r.state [4] & (\sdram_|r.state [6] & \sdram_|Mux19~4_combout ))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux19~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux19~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~6 .lut_mask = 16'h8000; +defparam \sdram_|Mux19~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N14 +cycloneive_lcell_comb \sdram_|Mux19~7 ( +// Equation(s): +// \sdram_|Mux19~7_combout = (\sdram_|Mux19~5_combout & ((\sdram_|Mux19~6_combout & ((\sdram_|r.address[5]~_Duplicate_1_q ))) # (!\sdram_|Mux19~6_combout & (\z80_|address_pins_|abus[4]~28_combout )))) # (!\sdram_|Mux19~5_combout & +// (((\sdram_|r.address[5]~_Duplicate_1_q & !\sdram_|Mux19~6_combout )))) + + .dataa(\z80_|address_pins_|abus[4]~28_combout ), + .datab(\sdram_|r.address[5]~_Duplicate_1_q ), + .datac(\sdram_|Mux19~5_combout ), + .datad(\sdram_|Mux19~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux19~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~7 .lut_mask = 16'hC0AC; +defparam \sdram_|Mux19~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y11_N31 +dffeas \sdram_|r.address[5]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[5]~3_combout ), + .asdata(\sdram_|Mux19~7_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\sdram_|r.state [7]), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[5]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[5]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[5]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N20 +cycloneive_lcell_comb \sdram_|Mux19~2 ( +// Equation(s): +// \sdram_|Mux19~2_combout = (\sdram_|r.state [4] & (((!\sdram_|process_0~2_combout & \sdram_|r.address[5]~_Duplicate_1_q )))) # (!\sdram_|r.state [4] & (\sdram_|Mux19~1_combout )) + + .dataa(\sdram_|Mux19~1_combout ), + .datab(\sdram_|process_0~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.address[5]~_Duplicate_1_q ), + .cin(gnd), + .combout(\sdram_|Mux19~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~2 .lut_mask = 16'h3A0A; +defparam \sdram_|Mux19~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N6 +cycloneive_lcell_comb \sdram_|Mux19~3 ( +// Equation(s): +// \sdram_|Mux19~3_combout = (\sdram_|Mux24~2_combout & ((\sdram_|r.state [4] & ((\sdram_|r.address[5]~_Duplicate_1_q ))) # (!\sdram_|r.state [4] & (\z80_|address_pins_|abus[4]~28_combout )))) # (!\sdram_|Mux24~2_combout & +// (((\sdram_|r.address[5]~_Duplicate_1_q )))) + + .dataa(\sdram_|Mux24~2_combout ), + .datab(\sdram_|r.state [4]), + .datac(\z80_|address_pins_|abus[4]~28_combout ), + .datad(\sdram_|r.address[5]~_Duplicate_1_q ), + .cin(gnd), + .combout(\sdram_|Mux19~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~3 .lut_mask = 16'hFD20; +defparam \sdram_|Mux19~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N30 +cycloneive_lcell_comb \sdram_|r.address[5]~3 ( +// Equation(s): +// \sdram_|r.address[5]~3_combout = (\sdram_|r.state [8] & ((\sdram_|Mux19~3_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux19~2_combout )) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux19~2_combout ), + .datac(gnd), + .datad(\sdram_|Mux19~3_combout ), + .cin(gnd), + .combout(\sdram_|r.address[5]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[5]~3 .lut_mask = 16'hEE44; +defparam \sdram_|r.address[5]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N26 +cycloneive_lcell_comb \sdram_|r.address[5]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[5]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux19~7_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[5]~3_combout )) + + .dataa(\sdram_|r.address[5]~3_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux19~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[5]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[5]~SLOAD_MUX .lut_mask = 16'hE2E2; +defparam \sdram_|r.address[5]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X18_Y0_N25 +dffeas \sdram_|r.address[5] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[5]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[5] .is_wysiwyg = "true"; +defparam \sdram_|r.address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N6 +cycloneive_lcell_comb \sdram_|Mux18~0 ( +// Equation(s): +// \sdram_|Mux18~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [5]), + .datad(\sdram_|r.address[3]~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux18~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux18~0 .lut_mask = 16'hF500; +defparam \sdram_|Mux18~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X20_Y0_N4 +dffeas \sdram_|r.address[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux18~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[6] .is_wysiwyg = "true"; +defparam \sdram_|r.address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N4 +cycloneive_lcell_comb \sdram_|Mux17~0 ( +// Equation(s): +// \sdram_|Mux17~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [6]), + .datad(\sdram_|r.address[3]~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux17~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux17~0 .lut_mask = 16'hF500; +defparam \sdram_|Mux17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X14_Y0_N4 +dffeas \sdram_|r.address[7] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux17~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[7] .is_wysiwyg = "true"; +defparam \sdram_|r.address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N22 +cycloneive_lcell_comb \sdram_|Mux16~0 ( +// Equation(s): +// \sdram_|Mux16~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [7]), + .datad(\sdram_|r.address[3]~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux16~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux16~0 .lut_mask = 16'hF500; +defparam \sdram_|Mux16~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y5_N25 +dffeas \sdram_|r.address[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux16~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[8] .is_wysiwyg = "true"; +defparam \sdram_|r.address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N30 +cycloneive_lcell_comb \sdram_|Mux15~2 ( +// Equation(s): +// \sdram_|Mux15~2_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [8]), + .datac(gnd), + .datad(\sdram_|r.address[3]~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux15~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux15~2 .lut_mask = 16'hDD00; +defparam \sdram_|Mux15~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y4_N25 +dffeas \sdram_|r.address[9] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux15~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[9] .is_wysiwyg = "true"; +defparam \sdram_|r.address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N22 +cycloneive_lcell_comb \sdram_|Mux14~0 ( +// Equation(s): +// \sdram_|Mux14~0_combout = (\sdram_|r.rf_pending~q ) # ((\sdram_|n~4_combout & ((\sdram_|r.state [6]) # (!\sdram_|process_0~3_combout )))) + + .dataa(\sdram_|process_0~3_combout ), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|n~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux14~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~0 .lut_mask = 16'hFDCC; +defparam \sdram_|Mux14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N28 +cycloneive_lcell_comb \sdram_|Mux14~1 ( +// Equation(s): +// \sdram_|Mux14~1_combout = (\sdram_|r.state [4] & (((\sdram_|r.address[10]~_Duplicate_1_q & !\sdram_|process_0~2_combout )))) # (!\sdram_|r.state [4] & (\sdram_|Equal2~3_combout )) + + .dataa(\sdram_|Equal2~3_combout ), + .datab(\sdram_|r.address[10]~_Duplicate_1_q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux14~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~1 .lut_mask = 16'h0ACA; +defparam \sdram_|Mux14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N10 +cycloneive_lcell_comb \sdram_|r.address[10]~4 ( +// Equation(s): +// \sdram_|r.address[10]~4_combout = (\sdram_|r.state [8] & (\sdram_|Mux14~0_combout )) # (!\sdram_|r.state [8] & ((\sdram_|Mux14~1_combout ))) + + .dataa(\sdram_|Mux14~0_combout ), + .datab(\sdram_|r.state [8]), + .datac(gnd), + .datad(\sdram_|Mux14~1_combout ), + .cin(gnd), + .combout(\sdram_|r.address[10]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[10]~4 .lut_mask = 16'hBB88; +defparam \sdram_|r.address[10]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y11_N11 +dffeas \sdram_|r.address[10]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[10]~4_combout ), + .asdata(\sdram_|Mux14~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\sdram_|r.state [7]), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[10]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[10]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[10]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N16 +cycloneive_lcell_comb \sdram_|n~4 ( +// Equation(s): +// \sdram_|n~4_combout = (\sdram_|r.rd_pending~q & (!\sdram_|Equal7~2_combout )) # (!\sdram_|r.rd_pending~q & (((\sdram_|r.address[10]~_Duplicate_1_q ) # (\sdram_|r.wr_pending~q )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.address[10]~_Duplicate_1_q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|n~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|n~4 .lut_mask = 16'h5F5C; +defparam \sdram_|n~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N30 +cycloneive_lcell_comb \sdram_|Mux14~2 ( +// Equation(s): +// \sdram_|Mux14~2_combout = (!\sdram_|r.state [6] & ((\sdram_|r.rf_pending~q ) # ((!\sdram_|process_0~3_combout & \sdram_|n~4_combout )))) + + .dataa(\sdram_|process_0~3_combout ), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|n~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux14~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~2 .lut_mask = 16'h0D0C; +defparam \sdram_|Mux14~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N8 +cycloneive_lcell_comb \sdram_|Mux14~3 ( +// Equation(s): +// \sdram_|Mux14~3_combout = (\sdram_|Mux14~2_combout ) # ((\sdram_|r.address[10]~_Duplicate_1_q & (\sdram_|Mux23~0_combout & !\sdram_|process_0~2_combout ))) + + .dataa(\sdram_|Mux14~2_combout ), + .datab(\sdram_|r.address[10]~_Duplicate_1_q ), + .datac(\sdram_|Mux23~0_combout ), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux14~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~3 .lut_mask = 16'hAAEA; +defparam \sdram_|Mux14~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N26 +cycloneive_lcell_comb \sdram_|r.address[10]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[10]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux14~3_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[10]~4_combout ))) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux14~3_combout ), + .datad(\sdram_|r.address[10]~4_combout ), + .cin(gnd), + .combout(\sdram_|r.address[10]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[10]~SLOAD_MUX .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[10]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y8_N25 +dffeas \sdram_|r.address[10] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[10]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[10] .is_wysiwyg = "true"; +defparam \sdram_|r.address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N28 +cycloneive_lcell_comb \sdram_|r.address[11]~18 ( +// Equation(s): +// \sdram_|r.address[11]~18_combout = (!\sdram_|r.rd_pending~q & (\sdram_|r.state [4] & !\sdram_|r.wr_pending~q )) + + .dataa(gnd), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|r.address[11]~18_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~18 .lut_mask = 16'h0030; +defparam \sdram_|r.address[11]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N26 +cycloneive_lcell_comb \sdram_|r.address[11]~5 ( +// Equation(s): +// \sdram_|r.address[11]~5_combout = (\sdram_|r.address[11]~_Duplicate_2_q & ((\sdram_|r.state [8] & (!\sdram_|Mux24~2_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.address[11]~18_combout ))))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux24~2_combout ), + .datac(\sdram_|r.address[11]~_Duplicate_2_q ), + .datad(\sdram_|r.address[11]~18_combout ), + .cin(gnd), + .combout(\sdram_|r.address[11]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~5 .lut_mask = 16'h7020; +defparam \sdram_|r.address[11]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N4 +cycloneive_lcell_comb \sdram_|r.address[11]~_Duplicate_2feeder ( +// Equation(s): +// \sdram_|r.address[11]~_Duplicate_2feeder_combout = \sdram_|r.address[11]~5_combout + + .dataa(\sdram_|r.address[11]~5_combout ), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[11]~_Duplicate_2feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~_Duplicate_2feeder .lut_mask = 16'hAAAA; +defparam \sdram_|r.address[11]~_Duplicate_2feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y11_N5 +dffeas \sdram_|r.address[11]~_Duplicate_2 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[11]~_Duplicate_2feeder_combout ), + .asdata(\sdram_|Mux13~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\sdram_|r.state [7]), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[11]~_Duplicate_2_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[11]~_Duplicate_2 .is_wysiwyg = "true"; +defparam \sdram_|r.address[11]~_Duplicate_2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N8 +cycloneive_lcell_comb \sdram_|Mux13~10 ( +// Equation(s): +// \sdram_|Mux13~10_combout = (\sdram_|r.address[11]~_Duplicate_2_q & ((\sdram_|r.state [8]) # (!\sdram_|r.state [6]))) + + .dataa(gnd), + .datab(\sdram_|r.address[11]~_Duplicate_2_q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux13~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~10 .lut_mask = 16'hCC0C; +defparam \sdram_|Mux13~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N22 +cycloneive_lcell_comb \sdram_|Mux13~6 ( +// Equation(s): +// \sdram_|Mux13~6_combout = (\sdram_|Mux13~10_combout & (((!\sdram_|r.state [6] & !\sdram_|Equal7~2_combout )) # (!\sdram_|process_0~2_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|Mux13~10_combout ), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux13~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~6 .lut_mask = 16'h10F0; +defparam \sdram_|Mux13~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N12 +cycloneive_lcell_comb \sdram_|r.address[11]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[11]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux13~6_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[11]~5_combout ))) + + .dataa(\sdram_|Mux13~6_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.address[11]~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[11]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~SLOAD_MUX .lut_mask = 16'hB8B8; +defparam \sdram_|r.address[11]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y7_N4 +dffeas \sdram_|r.address[11] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[11]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[11] .is_wysiwyg = "true"; +defparam \sdram_|r.address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N6 +cycloneive_lcell_comb \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux13~6_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[11]~5_combout ))) + + .dataa(\sdram_|Mux13~6_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.address[11]~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX .lut_mask = 16'hB8B8; +defparam \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y6_N18 +dffeas \sdram_|r.address[11]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[11]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[11]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[11]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + // Location: IOIBUF_X0_Y16_N22 cycloneive_io_ibuf \SW[0]~input ( .i(SW[0]), @@ -59899,4 +65745,164 @@ defparam \I2C_SCLK~input .bus_hold = "false"; defparam \I2C_SCLK~input .simulate_z_as = "z"; // synopsys translate_on +// Location: IOIBUF_X0_Y23_N15 +cycloneive_io_ibuf \DRAM_DQ[0]~input ( + .i(DRAM_DQ[0]), + .ibar(gnd), + .o(\DRAM_DQ[0]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[0]~input .bus_hold = "false"; +defparam \DRAM_DQ[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y23_N22 +cycloneive_io_ibuf \DRAM_DQ[1]~input ( + .i(DRAM_DQ[1]), + .ibar(gnd), + .o(\DRAM_DQ[1]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[1]~input .bus_hold = "false"; +defparam \DRAM_DQ[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N8 +cycloneive_io_ibuf \DRAM_DQ[2]~input ( + .i(DRAM_DQ[2]), + .ibar(gnd), + .o(\DRAM_DQ[2]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[2]~input .bus_hold = "false"; +defparam \DRAM_DQ[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y7_N8 +cycloneive_io_ibuf \DRAM_DQ[3]~input ( + .i(DRAM_DQ[3]), + .ibar(gnd), + .o(\DRAM_DQ[3]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[3]~input .bus_hold = "false"; +defparam \DRAM_DQ[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y12_N1 +cycloneive_io_ibuf \DRAM_DQ[4]~input ( + .i(DRAM_DQ[4]), + .ibar(gnd), + .o(\DRAM_DQ[4]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[4]~input .bus_hold = "false"; +defparam \DRAM_DQ[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y15_N1 +cycloneive_io_ibuf \DRAM_DQ[5]~input ( + .i(DRAM_DQ[5]), + .ibar(gnd), + .o(\DRAM_DQ[5]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[5]~input .bus_hold = "false"; +defparam \DRAM_DQ[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y15_N8 +cycloneive_io_ibuf \DRAM_DQ[6]~input ( + .i(DRAM_DQ[6]), + .ibar(gnd), + .o(\DRAM_DQ[6]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[6]~input .bus_hold = "false"; +defparam \DRAM_DQ[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y0_N15 +cycloneive_io_ibuf \DRAM_DQ[7]~input ( + .i(DRAM_DQ[7]), + .ibar(gnd), + .o(\DRAM_DQ[7]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[7]~input .bus_hold = "false"; +defparam \DRAM_DQ[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y0_N15 +cycloneive_io_ibuf \DRAM_DQ[8]~input ( + .i(DRAM_DQ[8]), + .ibar(gnd), + .o(\DRAM_DQ[8]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[8]~input .bus_hold = "false"; +defparam \DRAM_DQ[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y0_N1 +cycloneive_io_ibuf \DRAM_DQ[9]~input ( + .i(DRAM_DQ[9]), + .ibar(gnd), + .o(\DRAM_DQ[9]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[9]~input .bus_hold = "false"; +defparam \DRAM_DQ[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X1_Y0_N1 +cycloneive_io_ibuf \DRAM_DQ[10]~input ( + .i(DRAM_DQ[10]), + .ibar(gnd), + .o(\DRAM_DQ[10]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[10]~input .bus_hold = "false"; +defparam \DRAM_DQ[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X1_Y0_N8 +cycloneive_io_ibuf \DRAM_DQ[11]~input ( + .i(DRAM_DQ[11]), + .ibar(gnd), + .o(\DRAM_DQ[11]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[11]~input .bus_hold = "false"; +defparam \DRAM_DQ[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y0_N22 +cycloneive_io_ibuf \DRAM_DQ[12]~input ( + .i(DRAM_DQ[12]), + .ibar(gnd), + .o(\DRAM_DQ[12]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[12]~input .bus_hold = "false"; +defparam \DRAM_DQ[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X1_Y0_N15 +cycloneive_io_ibuf \DRAM_DQ[13]~input ( + .i(DRAM_DQ[13]), + .ibar(gnd), + .o(\DRAM_DQ[13]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[13]~input .bus_hold = "false"; +defparam \DRAM_DQ[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X1_Y0_N22 +cycloneive_io_ibuf \DRAM_DQ[14]~input ( + .i(DRAM_DQ[14]), + .ibar(gnd), + .o(\DRAM_DQ[14]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[14]~input .bus_hold = "false"; +defparam \DRAM_DQ[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y12_N8 +cycloneive_io_ibuf \DRAM_DQ[15]~input ( + .i(DRAM_DQ[15]), + .ibar(gnd), + .o(\DRAM_DQ[15]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[15]~input .bus_hold = "false"; +defparam \DRAM_DQ[15]~input .simulate_z_as = "z"; +// synopsys translate_on + endmodule diff --git a/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo b/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo index 55e5471..83e1ca8 100644 --- a/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo +++ b/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "04/01/2022 18:55:52") + (DATE "04/02/2022 14:51:21") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,8 +41,8 @@ (INSTANCE GPIO_1\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (2109:2109:2109) (2123:2123:2123)) - (PORT oe (1638:1638:1638) (1708:1708:1708)) + (PORT i (1504:1504:1504) (1598:1598:1598)) + (PORT oe (1712:1712:1712) (1779:1779:1779)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -53,8 +53,8 @@ (INSTANCE GPIO_1\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (2133:2133:2133) (2174:2174:2174)) - (PORT oe (1897:1897:1897) (1931:1931:1931)) + (PORT i (2050:2050:2050) (2110:2110:2110)) + (PORT oe (1688:1688:1688) (1781:1781:1781)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -65,8 +65,8 @@ (INSTANCE GPIO_1\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1984:1984:1984) (2083:2083:2083)) - (PORT oe (1897:1897:1897) (1931:1931:1931)) + (PORT i (2228:2228:2228) (2262:2262:2262)) + (PORT oe (1688:1688:1688) (1781:1781:1781)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -77,8 +77,8 @@ (INSTANCE GPIO_1\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (2218:2218:2218) (2284:2284:2284)) - (PORT oe (2147:2147:2147) (2236:2236:2236)) + (PORT i (1814:1814:1814) (1854:1854:1854)) + (PORT oe (2105:2105:2105) (2195:2195:2195)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -89,8 +89,8 @@ (INSTANCE GPIO_1\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (2271:2271:2271) (2432:2432:2432)) - (PORT oe (2147:2147:2147) (2236:2236:2236)) + (PORT i (1890:1890:1890) (1931:1931:1931)) + (PORT oe (2105:2105:2105) (2195:2195:2195)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -101,8 +101,8 @@ (INSTANCE GPIO_1\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1973:1973:1973) (2011:2011:2011)) - (PORT oe (1910:1910:1910) (2005:2005:2005)) + (PORT i (1532:1532:1532) (1676:1676:1676)) + (PORT oe (2346:2346:2346) (2450:2450:2450)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -113,8 +113,8 @@ (INSTANCE GPIO_1\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1640:1640:1640) (1716:1716:1716)) - (PORT oe (1910:1910:1910) (2005:2005:2005)) + (PORT i (1646:1646:1646) (1694:1694:1694)) + (PORT oe (2346:2346:2346) (2450:2450:2450)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -125,8 +125,8 @@ (INSTANCE GPIO_1\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (1960:1960:1960) (2148:2148:2148)) - (PORT oe (1910:1910:1910) (2005:2005:2005)) + (PORT i (1651:1651:1651) (1747:1747:1747)) + (PORT oe (2346:2346:2346) (2450:2450:2450)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -137,8 +137,8 @@ (INSTANCE GPIO_1\[8\]\~output) (DELAY (ABSOLUTE - (PORT i (976:976:976) (1064:1064:1064)) - (PORT oe (2161:2161:2161) (2266:2266:2266)) + (PORT i (1458:1458:1458) (1517:1517:1517)) + (PORT oe (2627:2627:2627) (2741:2741:2741)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -149,8 +149,8 @@ (INSTANCE GPIO_1\[9\]\~output) (DELAY (ABSOLUTE - (PORT i (1717:1717:1717) (1803:1803:1803)) - (PORT oe (2161:2161:2161) (2266:2266:2266)) + (PORT i (1614:1614:1614) (1659:1659:1659)) + (PORT oe (2627:2627:2627) (2741:2741:2741)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -161,8 +161,8 @@ (INSTANCE GPIO_1\[10\]\~output) (DELAY (ABSOLUTE - (PORT i (1939:1939:1939) (1996:1996:1996)) - (PORT oe (2404:2404:2404) (2537:2537:2537)) + (PORT i (1699:1699:1699) (1833:1833:1833)) + (PORT oe (2364:2364:2364) (2456:2456:2456)) (IOPATH i o (4557:4557:4557) (4190:4190:4190)) (IOPATH oe o (4578:4578:4578) (4159:4159:4159)) ) @@ -173,8 +173,8 @@ (INSTANCE GPIO_1\[11\]\~output) (DELAY (ABSOLUTE - (PORT i (1417:1417:1417) (1462:1462:1462)) - (PORT oe (2161:2161:2161) (2266:2266:2266)) + (PORT i (1560:1560:1560) (1602:1602:1602)) + (PORT oe (2627:2627:2627) (2741:2741:2741)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -185,8 +185,8 @@ (INSTANCE GPIO_1\[12\]\~output) (DELAY (ABSOLUTE - (PORT i (2181:2181:2181) (2209:2209:2209)) - (PORT oe (1700:1700:1700) (1736:1736:1736)) + (PORT i (1639:1639:1639) (1709:1709:1709)) + (PORT oe (1712:1712:1712) (1796:1796:1796)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -197,8 +197,8 @@ (INSTANCE GPIO_1\[13\]\~output) (DELAY (ABSOLUTE - (PORT i (2231:2231:2231) (2361:2361:2361)) - (PORT oe (2404:2404:2404) (2537:2537:2537)) + (PORT i (1649:1649:1649) (1732:1732:1732)) + (PORT oe (2364:2364:2364) (2456:2456:2456)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -209,8 +209,8 @@ (INSTANCE GPIO_1\[14\]\~output) (DELAY (ABSOLUTE - (PORT i (1625:1625:1625) (1715:1715:1715)) - (PORT oe (2140:2140:2140) (2250:2250:2250)) + (PORT i (1435:1435:1435) (1557:1557:1557)) + (PORT oe (2114:2114:2114) (2280:2280:2280)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -221,8 +221,8 @@ (INSTANCE GPIO_1\[15\]\~output) (DELAY (ABSOLUTE - (PORT i (1724:1724:1724) (1854:1854:1854)) - (PORT oe (1916:1916:1916) (1948:1948:1948)) + (PORT i (1807:1807:1807) (1861:1861:1861)) + (PORT oe (1901:1901:1901) (1995:1995:1995)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -233,8 +233,8 @@ (INSTANCE GPIO_1\[16\]\~output) (DELAY (ABSOLUTE - (PORT i (1202:1202:1202) (1265:1265:1265)) - (PORT oe (2441:2441:2441) (2523:2523:2523)) + (PORT i (1165:1165:1165) (1241:1241:1241)) + (PORT oe (1397:1397:1397) (1462:1462:1462)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -245,8 +245,8 @@ (INSTANCE GPIO_1\[17\]\~output) (DELAY (ABSOLUTE - (PORT i (1216:1216:1216) (1287:1287:1287)) - (PORT oe (2442:2442:2442) (2524:2524:2524)) + (PORT i (1217:1217:1217) (1281:1281:1281)) + (PORT oe (1676:1676:1676) (1756:1756:1756)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -257,8 +257,8 @@ (INSTANCE GPIO_1\[18\]\~output) (DELAY (ABSOLUTE - (PORT i (1118:1118:1118) (1163:1163:1163)) - (PORT oe (2137:2137:2137) (2196:2196:2196)) + (PORT i (1447:1447:1447) (1518:1518:1518)) + (PORT oe (1644:1644:1644) (1702:1702:1702)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -269,8 +269,8 @@ (INSTANCE GPIO_1\[19\]\~output) (DELAY (ABSOLUTE - (PORT i (1161:1161:1161) (1237:1237:1237)) - (PORT oe (2441:2441:2441) (2523:2523:2523)) + (PORT i (1400:1400:1400) (1428:1428:1428)) + (PORT oe (1397:1397:1397) (1462:1462:1462)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -281,8 +281,8 @@ (INSTANCE GPIO_1\[20\]\~output) (DELAY (ABSOLUTE - (PORT i (1455:1455:1455) (1530:1530:1530)) - (PORT oe (2096:2096:2096) (2158:2158:2158)) + (PORT i (1625:1625:1625) (1682:1682:1682)) + (PORT oe (1412:1412:1412) (1478:1478:1478)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -293,8 +293,8 @@ (INSTANCE GPIO_1\[21\]\~output) (DELAY (ABSOLUTE - (PORT i (1343:1343:1343) (1352:1352:1352)) - (PORT oe (2136:2136:2136) (2195:2195:2195)) + (PORT i (1455:1455:1455) (1530:1530:1530)) + (PORT oe (1701:1701:1701) (1755:1755:1755)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -305,8 +305,8 @@ (INSTANCE GPIO_1\[22\]\~output) (DELAY (ABSOLUTE - (PORT i (1213:1213:1213) (1275:1275:1275)) - (PORT oe (2035:2035:2035) (2069:2069:2069)) + (PORT i (1615:1615:1615) (1704:1704:1704)) + (PORT oe (1627:1627:1627) (1676:1676:1676)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -317,8 +317,8 @@ (INSTANCE GPIO_1\[23\]\~output) (DELAY (ABSOLUTE - (PORT i (1131:1131:1131) (1146:1146:1146)) - (PORT oe (2405:2405:2405) (2466:2466:2466)) + (PORT i (1389:1389:1389) (1468:1468:1468)) + (PORT oe (1392:1392:1392) (1455:1455:1455)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -329,8 +329,8 @@ (INSTANCE GPIO_1\[27\]\~output) (DELAY (ABSOLUTE - (PORT i (1412:1412:1412) (1417:1417:1417)) - (PORT oe (1643:1643:1643) (1693:1693:1693)) + (PORT i (1446:1446:1446) (1447:1447:1447)) + (PORT oe (1534:1534:1534) (1631:1631:1631)) (IOPATH i o (2378:2378:2378) (2455:2455:2455)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -341,8 +341,8 @@ (INSTANCE GPIO_1\[28\]\~output) (DELAY (ABSOLUTE - (PORT i (1794:1794:1794) (1688:1688:1688)) - (PORT oe (1916:1916:1916) (1948:1948:1948)) + (PORT i (1260:1260:1260) (1241:1241:1241)) + (PORT oe (1901:1901:1901) (1995:1995:1995)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -353,9 +353,9 @@ (INSTANCE GPIO_1\[29\]\~output) (DELAY (ABSOLUTE - (PORT i (1533:1533:1533) (1531:1531:1531)) - (PORT oe (1352:1352:1352) (1405:1405:1405)) - (IOPATH i o (2502:2502:2502) (2582:2582:2582)) + (PORT i (1183:1183:1183) (1166:1166:1166)) + (PORT oe (1856:1856:1856) (1947:1947:1947)) + (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) ) @@ -365,8 +365,8 @@ (INSTANCE GPIO_1\[30\]\~output) (DELAY (ABSOLUTE - (PORT i (1050:1050:1050) (1062:1062:1062)) - (PORT oe (1327:1327:1327) (1369:1369:1369)) + (PORT i (1167:1167:1167) (1158:1158:1158)) + (PORT oe (1000:1000:1000) (1069:1069:1069)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -387,7 +387,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1030:1030:1030) (1018:1018:1018)) + (PORT i (1031:1031:1031) (1018:1018:1018)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -397,7 +397,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1304:1304:1304) (1340:1340:1340)) + (PORT i (1473:1473:1473) (1574:1574:1574)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -452,7 +452,7 @@ (INSTANCE VGA_R\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1164:1164:1164) (1204:1204:1204)) + (PORT i (1116:1116:1116) (1178:1178:1178)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -462,7 +462,7 @@ (INSTANCE VGA_R\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1073:1073:1073) (1104:1104:1104)) + (PORT i (1137:1137:1137) (1173:1173:1173)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -472,7 +472,7 @@ (INSTANCE VGA_R\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (774:774:774) (751:751:751)) + (PORT i (869:869:869) (884:884:884)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -482,7 +482,7 @@ (INSTANCE VGA_R\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (986:986:986) (968:968:968)) + (PORT i (820:820:820) (820:820:820)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -492,7 +492,7 @@ (INSTANCE VGA_G\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (972:972:972) (958:958:958)) + (PORT i (576:576:576) (580:580:580)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -502,7 +502,7 @@ (INSTANCE VGA_G\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (721:721:721) (699:699:699)) + (PORT i (555:555:555) (581:581:581)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -512,7 +512,7 @@ (INSTANCE VGA_G\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (843:843:843) (812:812:812)) + (PORT i (1282:1282:1282) (1290:1290:1290)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -522,7 +522,7 @@ (INSTANCE VGA_G\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (843:843:843) (812:812:812)) + (PORT i (1282:1282:1282) (1290:1290:1290)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -532,7 +532,7 @@ (INSTANCE VGA_B\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (717:717:717) (702:702:702)) + (PORT i (1111:1111:1111) (1161:1161:1161)) (IOPATH i o (4557:4557:4557) (4190:4190:4190)) ) ) @@ -542,7 +542,7 @@ (INSTANCE VGA_B\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (692:692:692) (667:667:667)) + (PORT i (1244:1244:1244) (1229:1229:1229)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -552,7 +552,7 @@ (INSTANCE VGA_B\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (952:952:952) (940:940:940)) + (PORT i (1131:1131:1131) (1197:1197:1197)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -562,7 +562,7 @@ (INSTANCE VGA_B\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1378:1378:1378) (1350:1350:1350)) + (PORT i (1135:1135:1135) (1193:1193:1193)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -590,7 +590,7 @@ (INSTANCE GPIO_1\[25\]\~output) (DELAY (ABSOLUTE - (PORT i (2048:2048:2048) (1957:1957:1957)) + (PORT i (1748:1748:1748) (1663:1663:1663)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) ) ) @@ -600,7 +600,7 @@ (INSTANCE GPIO_1\[26\]\~output) (DELAY (ABSOLUTE - (PORT i (1307:1307:1307) (1281:1281:1281)) + (PORT i (1132:1132:1132) (1158:1158:1158)) (IOPATH i o (4127:4127:4127) (4477:4477:4477)) ) ) @@ -610,7 +610,7 @@ (INSTANCE GPIO_1\[31\]\~output) (DELAY (ABSOLUTE - (PORT i (927:927:927) (923:923:923)) + (PORT i (888:888:888) (865:865:865)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) ) ) @@ -620,11 +620,201 @@ (INSTANCE buzzer_out\~output) (DELAY (ABSOLUTE - (PORT i (1348:1348:1348) (1373:1373:1373)) + (PORT i (1643:1643:1643) (1721:1721:1721)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_BA\[0\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2051:2051:2051) (1961:1961:1961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_BA\[1\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2051:2051:2051) (1961:1961:1961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQM\[0\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2051:2051:2051) (1961:1961:1961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQM\[1\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2051:2051:2051) (1961:1961:1961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_RAS_N\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2144:2144:2144) (2064:2064:2064)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_CAS_N\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2144:2144:2144) (2064:2064:2064)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_CLK\~output) + (DELAY + (ABSOLUTE + (PORT i (1764:1764:1764) (1783:1783:1783)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_WE_N\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2144:2144:2144) (2064:2064:2064)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[0\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2144:2144:2144) (2064:2064:2064)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[1\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2051:2051:2051) (1961:1961:1961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[2\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2051:2051:2051) (1961:1961:1961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[3\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2051:2051:2051) (1961:1961:1961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[4\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2051:2051:2051) (1961:1961:1961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[5\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2051:2051:2051) (1961:1961:1961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[6\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2051:2051:2051) (1961:1961:1961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[7\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2051:2051:2051) (1961:1961:1961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[8\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2017:2017:2017) (1940:1940:1940)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[9\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2144:2144:2144) (2064:2064:2064)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[10\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2144:2144:2144) (2064:2064:2064)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[11\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2144:2144:2144) (2064:2064:2064)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[12\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2017:2017:2017) (1940:1940:1940)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_obuf") (INSTANCE I2C_SCLK\~output) @@ -643,6 +833,182 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1255:1255:1255) (1335:1335:1335)) + (PORT oe (1717:1717:1717) (1786:1786:1786)) + (IOPATH i o (2582:2582:2582) (2502:2502:2502)) + (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1398:1398:1398) (1454:1454:1454)) + (PORT oe (1717:1717:1717) (1786:1786:1786)) + (IOPATH i o (2582:2582:2582) (2502:2502:2502)) + (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1113:1113:1113) (1148:1148:1148)) + (PORT oe (1376:1376:1376) (1434:1434:1434)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1206:1206:1206) (1278:1278:1278)) + (PORT oe (1471:1471:1471) (1583:1583:1583)) + (IOPATH i o (2455:2455:2455) (2378:2378:2378)) + (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1183:1183:1183) (1228:1228:1228)) + (PORT oe (1200:1200:1200) (1240:1240:1240)) + (IOPATH i o (2582:2582:2582) (2502:2502:2502)) + (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1419:1419:1419) (1515:1515:1515)) + (PORT oe (1364:1364:1364) (1339:1339:1339)) + (IOPATH i o (2582:2582:2582) (2502:2502:2502)) + (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1148:1148:1148) (1200:1200:1200)) + (PORT oe (1364:1364:1364) (1339:1339:1339)) + (IOPATH i o (2582:2582:2582) (2502:2502:2502)) + (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (558:558:558) (558:558:558)) + (PORT oe (1367:1367:1367) (1406:1406:1406)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1686:1686:1686) (1628:1628:1628)) + (IOPATH i o (2445:2445:2445) (2535:2535:2535)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1476:1476:1476) (1402:1402:1402)) + (IOPATH i o (2445:2445:2445) (2535:2535:2535)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1459:1459:1459) (1382:1382:1382)) + (IOPATH i o (2445:2445:2445) (2535:2535:2535)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1459:1459:1459) (1382:1382:1382)) + (IOPATH i o (2445:2445:2445) (2535:2535:2535)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1653:1653:1653) (1629:1629:1629)) + (IOPATH i o (2445:2445:2445) (2535:2535:2535)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1679:1679:1679) (1615:1615:1615)) + (IOPATH i o (2445:2445:2445) (2535:2535:2535)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[14\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1679:1679:1679) (1615:1615:1615)) + (IOPATH i o (2445:2445:2445) (2535:2535:2535)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[15\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1240:1240:1240) (1200:1200:1200)) + (IOPATH i o (2502:2502:2502) (2582:2582:2582)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE CLOCK_50\~input) @@ -707,8 +1073,8 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~0) (DELAY (ABSOLUTE - (PORT datab (245:245:245) (328:328:328)) - (PORT datad (552:552:552) (573:573:573)) + (PORT datab (243:243:243) (326:326:326)) + (PORT datad (551:551:551) (574:574:574)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -734,32 +1100,7 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (716:716:716) (747:747:747)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1158:1158:1158)) - (PORT datad (1110:1110:1110) (1159:1159:1159)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|ena_M) - (DELAY - (ABSOLUTE - (PORT datac (1094:1094:1094) (1132:1132:1132)) - (PORT datad (1106:1106:1106) (1160:1160:1160)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT inclk[0] (720:720:720) (751:751:751)) ) ) ) @@ -772,10573 +1113,6 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (490:490:490)) - (PORT datad (1994:1994:1994) (2109:2109:2109)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|nmi_armed) - (DELAY - (ABSOLUTE - (PORT clk (1476:1476:1476) (1490:1490:1490)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1325:1325:1325) (1320:1320:1320)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (790:790:790) (826:826:826)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) - (DELAY - (ABSOLUTE - (PORT datac (243:243:243) (323:323:323)) - (PORT datad (252:252:252) (325:325:325)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (2418:2418:2418) (2567:2567:2567)) - (PORT datab (2411:2411:2411) (2541:2541:2541)) - (PORT datad (1577:1577:1577) (1737:1737:1737)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M3_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1115:1115:1115) (1160:1160:1160)) - (PORT datab (408:408:408) (481:481:481)) - (PORT datad (1111:1111:1111) (1161:1161:1161)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M3_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1355:1355:1355) (1381:1381:1381)) - (PORT datab (1537:1537:1537) (1647:1647:1647)) - (PORT datac (1348:1348:1348) (1441:1441:1441)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M4_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1178:1178:1178)) - (PORT datab (413:413:413) (488:488:488)) - (PORT datad (1104:1104:1104) (1156:1156:1156)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M4_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal32\~0) - (DELAY - (ABSOLUTE - (PORT datab (393:393:393) (466:466:466)) - (PORT datad (667:667:667) (742:742:742)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) - (DELAY - (ABSOLUTE - (PORT datab (2598:2598:2598) (2742:2742:2742)) - (PORT datad (1607:1607:1607) (1729:1729:1729)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|table_xx\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1365:1365:1365) (1484:1484:1484)) - (PORT datad (1197:1197:1197) (1317:1317:1317)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1675:1675:1675) (1712:1712:1712)) - (PORT datab (945:945:945) (983:983:983)) - (PORT datac (2134:2134:2134) (2287:2287:2287)) - (PORT datad (1162:1162:1162) (1232:1232:1232)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT datac (1459:1459:1459) (1537:1537:1537)) - (PORT datad (2262:2262:2262) (2332:2332:2332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal36\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1246:1246:1246) (1343:1343:1343)) - (PORT datab (1671:1671:1671) (1786:1786:1786)) - (PORT datac (906:906:906) (959:959:959)) - (PORT datad (943:943:943) (998:998:998)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) - (DELAY - (ABSOLUTE - (PORT dataa (1739:1739:1739) (1786:1786:1786)) - (PORT datab (1426:1426:1426) (1455:1455:1455)) - (PORT datac (846:846:846) (882:882:882)) - (PORT datad (789:789:789) (792:792:792)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1224:1224:1224) (1329:1329:1329)) - (PORT datab (2644:2644:2644) (2764:2764:2764)) - (PORT datac (844:844:844) (879:879:879)) - (PORT datad (972:972:972) (1035:1035:1035)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instCB) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1588:1588:1588) (1563:1563:1563)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~0) - (DELAY - (ABSOLUTE - (PORT dataa (711:711:711) (808:808:808)) - (PORT datab (1233:1233:1233) (1347:1347:1347)) - (PORT datac (988:988:988) (1067:1067:1067)) - (PORT datad (1323:1323:1323) (1441:1441:1441)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2337:2337:2337) (2490:2490:2490)) - (PORT datab (1667:1667:1667) (1786:1786:1786)) - (PORT datac (905:905:905) (957:957:957)) - (PORT datad (672:672:672) (720:720:720)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) - (DELAY - (ABSOLUTE - (PORT dataa (1761:1761:1761) (1838:1838:1838)) - (PORT datab (839:839:839) (854:854:854)) - (PORT datac (1396:1396:1396) (1420:1420:1420)) - (PORT datad (2042:2042:2042) (2106:2106:2106)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instED) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1588:1588:1588) (1563:1563:1563)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (810:810:810)) - (PORT datac (981:981:981) (1058:1058:1058)) - (PORT datad (1323:1323:1323) (1434:1434:1434)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2169:2169:2169) (2327:2327:2327)) - (PORT datac (1460:1460:1460) (1537:1537:1537)) - (PORT datad (2263:2263:2263) (2329:2329:2329)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_im_we) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (636:636:636)) - (PORT datab (1050:1050:1050) (1169:1169:1169)) - (PORT datac (1337:1337:1337) (1469:1469:1469)) - (PORT datad (915:915:915) (959:959:959)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal49\~0) - (DELAY - (ABSOLUTE - (PORT datab (997:997:997) (1105:1105:1105)) - (PORT datac (656:656:656) (719:719:719)) - (PORT datad (1244:1244:1244) (1328:1328:1328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1410:1410:1410) (1499:1499:1499)) - (PORT datab (1489:1489:1489) (1614:1614:1614)) - (PORT datac (1433:1433:1433) (1524:1524:1524)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (711:711:711) (809:809:809)) - (PORT datab (1233:1233:1233) (1347:1347:1347)) - (PORT datac (989:989:989) (1067:1067:1067)) - (PORT datad (1323:1323:1323) (1441:1441:1441)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1232:1232:1232) (1301:1301:1301)) - (PORT datab (1273:1273:1273) (1368:1368:1368)) - (PORT datad (711:711:711) (773:773:773)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2639:2639:2639) (2814:2814:2814)) - (PORT datab (899:899:899) (934:934:934)) - (PORT datac (1110:1110:1110) (1167:1167:1167)) - (PORT datad (1150:1150:1150) (1194:1194:1194)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (933:933:933) (1033:1033:1033)) - (PORT datab (1561:1561:1561) (1662:1662:1662)) - (PORT datac (1411:1411:1411) (1476:1476:1476)) - (PORT datad (201:201:201) (238:238:238)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|nM1_int\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1239:1239:1239)) - (PORT datad (2109:2109:2109) (2254:2254:2254)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1086:1086:1086) (1149:1149:1149)) - (PORT datab (1113:1113:1113) (1123:1123:1123)) - (PORT datac (333:333:333) (359:359:359)) - (PORT datad (689:689:689) (743:743:743)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT datac (1439:1439:1439) (1545:1545:1545)) - (PORT datad (1464:1464:1464) (1551:1551:1551)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1247:1247:1247) (1335:1335:1335)) - (PORT datab (1669:1669:1669) (1782:1782:1782)) - (PORT datac (1700:1700:1700) (1785:1785:1785)) - (PORT datad (944:944:944) (1001:1001:1001)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~7) - (DELAY - (ABSOLUTE - (PORT datac (1974:1974:1974) (2154:2154:2154)) - (PORT datad (1235:1235:1235) (1306:1306:1306)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1939:1939:1939) (2060:2060:2060)) - (PORT datac (2560:2560:2560) (2661:2661:2661)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (937:937:937)) - (PORT datab (1029:1029:1029) (1093:1093:1093)) - (PORT datac (849:849:849) (913:913:913)) - (PORT datad (929:929:929) (973:973:973)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~1) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (941:941:941)) - (PORT datab (898:898:898) (917:917:917)) - (PORT datac (919:919:919) (1011:1011:1011)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (940:940:940)) - (PORT datab (901:901:901) (913:913:913)) - (PORT datac (920:920:920) (1009:1009:1009)) - (PORT datad (1166:1166:1166) (1216:1216:1216)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (896:896:896)) - (PORT datac (977:977:977) (1048:1048:1048)) - (PORT datad (1170:1170:1170) (1184:1184:1184)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2169:2169:2169) (2322:2322:2322)) - (PORT datac (1461:1461:1461) (1534:1534:1534)) - (PORT datad (2261:2261:2261) (2326:2326:2326)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~2) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (972:972:972)) - (PORT datab (1721:1721:1721) (1812:1812:1812)) - (PORT datac (1148:1148:1148) (1153:1153:1153)) - (PORT datad (650:650:650) (690:690:690)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (944:944:944) (975:975:975)) - (PORT datab (2317:2317:2317) (2471:2471:2471)) - (PORT datac (1702:1702:1702) (1788:1788:1788)) - (PORT datad (669:669:669) (716:716:716)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1211:1211:1211) (1331:1331:1331)) - (PORT datab (2075:2075:2075) (2256:2256:2256)) - (PORT datac (862:862:862) (881:881:881)) - (PORT datad (1458:1458:1458) (1561:1561:1561)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~8) - (DELAY - (ABSOLUTE - (PORT datab (1418:1418:1418) (1489:1489:1489)) - (PORT datac (1562:1562:1562) (1631:1631:1631)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~6) - (DELAY - (ABSOLUTE - (PORT datac (1595:1595:1595) (1686:1686:1686)) - (PORT datad (1897:1897:1897) (2018:2018:2018)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~9) - (DELAY - (ABSOLUTE - (PORT datac (1033:1033:1033) (1103:1103:1103)) - (PORT datad (985:985:985) (1046:1046:1046)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1003:1003:1003) (1060:1060:1060)) - (PORT datab (989:989:989) (1052:1052:1052)) - (PORT datac (903:903:903) (941:941:941)) - (PORT datad (2055:2055:2055) (2108:2108:2108)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (461:461:461)) - (PORT datab (1160:1160:1160) (1195:1195:1195)) - (PORT datac (623:623:623) (685:685:685)) - (PORT datad (1108:1108:1108) (1138:1138:1138)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal44\~0) - (DELAY - (ABSOLUTE - (PORT dataa (711:711:711) (810:810:810)) - (PORT datab (1238:1238:1238) (1352:1352:1352)) - (PORT datac (982:982:982) (1059:1059:1059)) - (PORT datad (1323:1323:1323) (1435:1435:1435)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~16) - (DELAY - (ABSOLUTE - (PORT dataa (976:976:976) (1074:1074:1074)) - (PORT datab (1336:1336:1336) (1358:1358:1358)) - (PORT datac (931:931:931) (1016:1016:1016)) - (PORT datad (1108:1108:1108) (1132:1132:1132)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~13) - (DELAY - (ABSOLUTE - (PORT datab (836:836:836) (897:897:897)) - (PORT datac (619:619:619) (671:671:671)) - (PORT datad (213:213:213) (245:245:245)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal50\~0) - (DELAY - (ABSOLUTE - (PORT datab (998:998:998) (1107:1107:1107)) - (PORT datac (656:656:656) (717:717:717)) - (PORT datad (1193:1193:1193) (1255:1255:1255)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1233:1233:1233) (1300:1300:1300)) - (PORT datab (1273:1273:1273) (1368:1368:1368)) - (PORT datad (711:711:711) (773:773:773)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~17) - (DELAY - (ABSOLUTE - (PORT dataa (967:967:967) (1063:1063:1063)) - (PORT datab (1112:1112:1112) (1107:1107:1107)) - (PORT datac (928:928:928) (1011:1011:1011)) - (PORT datad (1085:1085:1085) (1082:1082:1082)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~5) - (DELAY - (ABSOLUTE - (PORT datac (1607:1607:1607) (1722:1722:1722)) - (PORT datad (984:984:984) (1047:1047:1047)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (674:674:674)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (199:199:199) (237:237:237)) - (PORT datad (1103:1103:1103) (1112:1112:1112)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1593:1593:1593) (1671:1671:1671)) - (PORT datab (1420:1420:1420) (1492:1492:1492)) - (PORT datac (372:372:372) (399:399:399)) - (PORT datad (1786:1786:1786) (1904:1904:1904)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1089:1089:1089) (1107:1107:1107)) - (PORT datab (236:236:236) (282:282:282)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1302:1302:1302) (1399:1399:1399)) - (PORT datab (1499:1499:1499) (1604:1604:1604)) - (PORT datac (1460:1460:1460) (1551:1551:1551)) - (PORT datad (2054:2054:2054) (2222:2222:2222)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instIY1) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1586:1586:1586) (1563:1563:1563)) - (PORT ena (820:820:820) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (960:960:960)) - (PORT datac (643:643:643) (708:708:708)) - (PORT datad (1365:1365:1365) (1481:1481:1481)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1259:1259:1259) (1368:1368:1368)) - (PORT datab (463:463:463) (524:524:524)) - (PORT datac (1699:1699:1699) (1754:1754:1754)) - (PORT datad (267:267:267) (321:321:321)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (709:709:709) (805:805:805)) - (PORT datab (1019:1019:1019) (1101:1101:1101)) - (PORT datac (676:676:676) (769:769:769)) - (PORT datad (1322:1322:1322) (1435:1435:1435)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1624:1624:1624) (1717:1717:1717)) - (PORT datab (1533:1533:1533) (1585:1585:1585)) - (PORT datac (1709:1709:1709) (1830:1830:1830)) - (PORT datad (1494:1494:1494) (1626:1626:1626)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1299:1299:1299) (1388:1388:1388)) - (PORT datab (1243:1243:1243) (1323:1323:1323)) - (PORT datac (1034:1034:1034) (1082:1082:1082)) - (PORT datad (1678:1678:1678) (1738:1738:1738)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~26) - (DELAY - (ABSOLUTE - (PORT datac (685:685:685) (734:734:734)) - (PORT datad (1734:1734:1734) (1851:1851:1851)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (666:666:666)) - (PORT datac (1102:1102:1102) (1151:1151:1151)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (252:252:252)) - (PORT datab (244:244:244) (291:291:291)) - (PORT datac (669:669:669) (688:688:688)) - (PORT datad (2054:2054:2054) (2107:2107:2107)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1002:1002:1002) (1065:1065:1065)) - (PORT datab (1219:1219:1219) (1281:1281:1281)) - (PORT datac (688:688:688) (740:740:740)) - (PORT datad (179:179:179) (206:206:206)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (1031:1031:1031)) - (PORT datab (1557:1557:1557) (1661:1661:1661)) - (PORT datac (1407:1407:1407) (1474:1474:1474)) - (PORT datad (203:203:203) (238:238:238)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal55\~0) - (DELAY - (ABSOLUTE - (PORT dataa (288:288:288) (386:386:386)) - (PORT datac (902:902:902) (964:964:964)) - (PORT datad (928:928:928) (984:984:984)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1762:1762:1762) (1872:1872:1872)) - (PORT datac (1146:1146:1146) (1226:1226:1226)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (664:664:664)) - (PORT datab (1178:1178:1178) (1215:1215:1215)) - (PORT datac (934:934:934) (1030:1030:1030)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (723:723:723)) - (PORT datab (653:653:653) (674:674:674)) - (PORT datac (936:936:936) (1036:1036:1036)) - (PORT datad (898:898:898) (943:943:943)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (958:958:958)) - (PORT datab (1199:1199:1199) (1222:1222:1222)) - (PORT datac (1813:1813:1813) (1890:1890:1890)) - (PORT datad (871:871:871) (910:910:910)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1687:1687:1687) (1746:1746:1746)) - (PORT datac (1659:1659:1659) (1737:1737:1737)) - (PORT datad (1165:1165:1165) (1209:1209:1209)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~0) - (DELAY - (ABSOLUTE - (PORT datac (826:826:826) (880:880:880)) - (PORT datad (900:900:900) (971:971:971)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1685:1685:1685) (1750:1750:1750)) - (PORT datab (1691:1691:1691) (1776:1776:1776)) - (PORT datac (1479:1479:1479) (1575:1575:1575)) - (PORT datad (1244:1244:1244) (1311:1311:1311)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1465:1465:1465) (1537:1537:1537)) - (PORT datab (1233:1233:1233) (1318:1318:1318)) - (PORT datac (1424:1424:1424) (1514:1514:1514)) - (PORT datad (825:825:825) (838:838:838)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (914:914:914)) - (PORT datab (1241:1241:1241) (1279:1279:1279)) - (PORT datac (1377:1377:1377) (1384:1384:1384)) - (PORT datad (1263:1263:1263) (1301:1301:1301)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~1) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (657:657:657)) - (PORT datab (963:963:963) (1059:1059:1059)) - (PORT datad (1154:1154:1154) (1176:1176:1176)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1565:1565:1565) (1659:1659:1659)) - (PORT datab (982:982:982) (1039:1039:1039)) - (PORT datac (1634:1634:1634) (1749:1749:1749)) - (PORT datad (1216:1216:1216) (1293:1293:1293)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal25\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1460:1460:1460) (1559:1559:1559)) - (PORT datab (1540:1540:1540) (1676:1676:1676)) - (PORT datac (1379:1379:1379) (1439:1439:1439)) - (PORT datad (1566:1566:1566) (1596:1596:1596)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (894:894:894) (913:913:913)) - (PORT datab (1819:1819:1819) (1900:1900:1900)) - (PORT datac (867:867:867) (883:883:883)) - (PORT datad (1475:1475:1475) (1552:1552:1552)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1220:1220:1220) (1307:1307:1307)) - (PORT datac (948:948:948) (1024:1024:1024)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~0) - (DELAY - (ABSOLUTE - (PORT dataa (940:940:940) (969:969:969)) - (PORT datab (936:936:936) (992:992:992)) - (PORT datac (1633:1633:1633) (1753:1753:1753)) - (PORT datad (1215:1215:1215) (1294:1294:1294)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~4) - (DELAY - (ABSOLUTE - (PORT datac (1720:1720:1720) (1792:1792:1792)) - (PORT datad (2039:2039:2039) (2100:2100:2100)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal29\~0) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (1158:1158:1158) (1201:1201:1201)) - (PORT datac (1618:1618:1618) (1607:1607:1607)) - (PORT datad (1454:1454:1454) (1538:1538:1538)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1564:1564:1564) (1657:1657:1657)) - (PORT datab (978:978:978) (1038:1038:1038)) - (PORT datac (1634:1634:1634) (1759:1759:1759)) - (PORT datad (1220:1220:1220) (1302:1302:1302)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal34\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2169:2169:2169) (2326:2326:2326)) - (PORT datab (948:948:948) (988:988:988)) - (PORT datac (193:193:193) (227:227:227)) - (PORT datad (416:416:416) (461:461:461)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (445:445:445) (500:500:500)) - (PORT datab (942:942:942) (982:982:982)) - (PORT datac (2138:2138:2138) (2282:2282:2282)) - (PORT datad (1141:1141:1141) (1176:1176:1176)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal35\~0) - (DELAY - (ABSOLUTE - (PORT dataa (446:446:446) (504:504:504)) - (PORT datab (946:946:946) (982:982:982)) - (PORT datac (2134:2134:2134) (2284:2284:2284)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal38\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1627:1627:1627) (1717:1717:1717)) - (PORT datab (1533:1533:1533) (1663:1663:1663)) - (PORT datac (1709:1709:1709) (1827:1827:1827)) - (PORT datad (1445:1445:1445) (1492:1492:1492)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1114:1114:1114) (1137:1137:1137)) - (PORT datab (1107:1107:1107) (1172:1172:1172)) - (PORT datac (580:580:580) (611:611:611)) - (PORT datad (895:895:895) (945:945:945)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (867:867:867) (927:927:927)) - (PORT datab (1362:1362:1362) (1426:1426:1426)) - (PORT datac (584:584:584) (617:617:617)) - (PORT datad (583:583:583) (602:602:602)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~0) - (DELAY - (ABSOLUTE - (PORT datab (1940:1940:1940) (2011:2011:2011)) - (PORT datac (1163:1163:1163) (1222:1222:1222)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (450:450:450) (507:507:507)) - (PORT datab (949:949:949) (988:988:988)) - (PORT datac (2135:2135:2135) (2282:2282:2282)) - (PORT datad (364:364:364) (385:385:385)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1290:1290:1290) (1360:1360:1360)) - (PORT datab (1193:1193:1193) (1242:1242:1242)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (1264:1264:1264) (1365:1365:1365)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (717:717:717)) - (PORT datab (639:639:639) (661:661:661)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (1158:1158:1158) (1203:1203:1203)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (939:939:939) (959:959:959)) - (PORT datab (231:231:231) (282:282:282)) - (PORT datac (629:629:629) (651:651:651)) - (PORT datad (649:649:649) (681:681:681)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (1447:1447:1447) (1493:1493:1493)) - (PORT datab (1229:1229:1229) (1315:1315:1315)) - (PORT datac (680:680:680) (717:717:717)) - (PORT datad (1141:1141:1141) (1161:1161:1161)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (708:708:708) (759:759:759)) - (PORT datab (1141:1141:1141) (1169:1169:1169)) - (PORT datac (1819:1819:1819) (1896:1896:1896)) - (PORT datad (588:588:588) (613:613:613)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1461:1461:1461) (1560:1560:1560)) - (PORT datab (1137:1137:1137) (1179:1179:1179)) - (PORT datac (1192:1192:1192) (1287:1287:1287)) - (PORT datad (655:655:655) (686:686:686)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1468:1468:1468) (1566:1566:1566)) - (PORT datab (683:683:683) (725:725:725)) - (PORT datac (1193:1193:1193) (1278:1278:1278)) - (PORT datad (1406:1406:1406) (1445:1445:1445)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|M5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1173:1173:1173)) - (PORT datab (267:267:267) (350:350:350)) - (PORT datad (1104:1104:1104) (1160:1160:1160)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|M5) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) - (DELAY - (ABSOLUTE - (PORT datab (1589:1589:1589) (1719:1719:1719)) - (PORT datac (2606:2606:2606) (2704:2704:2704)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~29) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (665:665:665)) - (PORT datab (931:931:931) (978:978:978)) - (PORT datac (1004:1004:1004) (1061:1061:1061)) - (PORT datad (662:662:662) (691:691:691)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1946:1946:1946) (2050:2050:2050)) - (PORT datab (687:687:687) (729:729:729)) - (PORT datac (658:658:658) (709:709:709)) - (PORT datad (585:585:585) (615:615:615)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1904:1904:1904) (1999:1999:1999)) - (PORT datab (898:898:898) (961:961:961)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (187:187:187) (219:219:219)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1259:1259:1259) (1371:1371:1371)) - (PORT datab (464:464:464) (522:522:522)) - (PORT datac (1696:1696:1696) (1755:1755:1755)) - (PORT datad (268:268:268) (323:323:323)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1366:1366:1366) (1481:1481:1481)) - (PORT datab (934:934:934) (992:992:992)) - (PORT datac (958:958:958) (990:990:990)) - (PORT datad (1201:1201:1201) (1318:1318:1318)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~14) - (DELAY - (ABSOLUTE - (PORT dataa (972:972:972) (1071:1071:1071)) - (PORT datab (1335:1335:1335) (1360:1360:1360)) - (PORT datac (927:927:927) (1015:1015:1015)) - (PORT datad (1107:1107:1107) (1130:1130:1130)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (679:679:679)) - (PORT datab (1262:1262:1262) (1301:1301:1301)) - (PORT datac (566:566:566) (573:573:573)) - (PORT datad (1626:1626:1626) (1701:1701:1701)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~0) - (DELAY - (ABSOLUTE - (PORT dataa (708:708:708) (808:808:808)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (255:255:255) (343:343:343)) - (PORT datad (881:881:881) (941:941:941)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (933:933:933)) - (PORT datab (1109:1109:1109) (1175:1175:1175)) - (PORT datac (1089:1089:1089) (1121:1121:1121)) - (PORT datad (673:673:673) (713:713:713)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) - (DELAY - (ABSOLUTE - (PORT dataa (449:449:449) (492:492:492)) - (PORT datab (1938:1938:1938) (2051:2051:2051)) - (PORT datac (1035:1035:1035) (1084:1084:1084)) - (PORT datad (1561:1561:1561) (1612:1612:1612)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (1000:1000:1000)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (895:895:895) (945:945:945)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (683:683:683)) - (PORT datab (1196:1196:1196) (1213:1213:1213)) - (PORT datac (208:208:208) (248:248:248)) - (PORT datad (624:624:624) (642:642:642)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (458:458:458)) - (PORT datab (1170:1170:1170) (1201:1201:1201)) - (PORT datac (620:620:620) (684:684:684)) - (PORT datad (1113:1113:1113) (1142:1142:1142)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1626:1626:1626) (1717:1717:1717)) - (PORT datab (1533:1533:1533) (1584:1584:1584)) - (PORT datac (1703:1703:1703) (1827:1827:1827)) - (PORT datad (1490:1490:1490) (1625:1625:1625)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1624:1624:1624) (1719:1719:1719)) - (PORT datab (1534:1534:1534) (1581:1581:1581)) - (PORT datac (1711:1711:1711) (1826:1826:1826)) - (PORT datad (1494:1494:1494) (1620:1620:1620)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1688:1688:1688) (1727:1727:1727)) - (PORT datab (1470:1470:1470) (1564:1564:1564)) - (PORT datac (2563:2563:2563) (2660:2660:2660)) - (PORT datad (1901:1901:1901) (2013:2013:2013)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (682:682:682)) - (PORT datab (1262:1262:1262) (1302:1302:1302)) - (PORT datac (1116:1116:1116) (1135:1135:1135)) - (PORT datad (553:553:553) (571:571:571)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1260:1260:1260) (1370:1370:1370)) - (PORT datab (464:464:464) (521:521:521)) - (PORT datac (1697:1697:1697) (1755:1755:1755)) - (PORT datad (267:267:267) (323:323:323)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1107:1107:1107) (1153:1153:1153)) - (PORT datab (1145:1145:1145) (1184:1184:1184)) - (PORT datac (548:548:548) (563:563:563)) - (PORT datad (609:609:609) (634:634:634)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (291:291:291) (358:358:358)) - (PORT datab (465:465:465) (519:519:519)) - (PORT datac (191:191:191) (223:223:223)) - (PORT datad (1368:1368:1368) (1479:1479:1479)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal46\~0) - (DELAY - (ABSOLUTE - (PORT dataa (286:286:286) (382:382:382)) - (PORT datab (952:952:952) (1018:1018:1018)) - (PORT datac (903:903:903) (963:963:963)) - (PORT datad (1192:1192:1192) (1312:1312:1312)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1252:1252:1252) (1367:1367:1367)) - (PORT datab (866:866:866) (891:891:891)) - (PORT datac (1704:1704:1704) (1755:1755:1755)) - (PORT datad (263:263:263) (316:316:316)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) - (DELAY - (ABSOLUTE - (PORT dataa (2111:2111:2111) (2254:2254:2254)) - (PORT datab (2048:2048:2048) (2161:2161:2161)) - (PORT datac (986:986:986) (1043:1043:1043)) - (PORT datad (1210:1210:1210) (1253:1253:1253)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1380:1380:1380) (1424:1424:1424)) - (PORT datab (1059:1059:1059) (1143:1143:1143)) - (PORT datac (754:754:754) (762:762:762)) - (PORT datad (1235:1235:1235) (1269:1269:1269)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (982:982:982) (1061:1061:1061)) - (PORT datac (1148:1148:1148) (1203:1203:1203)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (296:296:296) (369:369:369)) - (PORT datab (465:465:465) (518:518:518)) - (PORT datac (1197:1197:1197) (1289:1289:1289)) - (PORT datad (1363:1363:1363) (1476:1476:1476)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1248:1248:1248)) - (PORT datab (2197:2197:2197) (2296:2296:2296)) - (PORT datac (1334:1334:1334) (1445:1445:1445)) - (PORT datad (959:959:959) (1022:1022:1022)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1792:1792:1792) (1883:1883:1883)) - (PORT datab (1288:1288:1288) (1337:1337:1337)) - (PORT datac (1377:1377:1377) (1384:1384:1384)) - (PORT datad (883:883:883) (905:905:905)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (635:635:635)) - (PORT datac (550:550:550) (559:559:559)) - (PORT datad (1232:1232:1232) (1290:1290:1290)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (861:861:861) (876:876:876)) - (PORT datad (848:848:848) (889:889:889)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) - (DELAY - (ABSOLUTE - (PORT datac (2061:2061:2061) (2184:2184:2184)) - (PORT datad (959:959:959) (1014:1014:1014)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1615:1615:1615) (1714:1714:1714)) - (PORT datab (1532:1532:1532) (1580:1580:1580)) - (PORT datac (1706:1706:1706) (1825:1825:1825)) - (PORT datad (1489:1489:1489) (1621:1621:1621)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~9) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (717:717:717)) - (PORT datab (1494:1494:1494) (1553:1553:1553)) - (PORT datac (1138:1138:1138) (1205:1205:1205)) - (PORT datad (1383:1383:1383) (1432:1432:1432)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (2148:2148:2148) (2325:2325:2325)) - (PORT datab (675:675:675) (746:746:746)) - (PORT datac (1715:1715:1715) (1794:1794:1794)) - (PORT datad (205:205:205) (235:235:235)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1299:1299:1299) (1399:1399:1399)) - (PORT datad (2046:2046:2046) (2211:2211:2211)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (999:999:999)) - (PORT datab (454:454:454) (482:482:482)) - (PORT datac (408:408:408) (448:448:448)) - (PORT datad (1564:1564:1564) (1622:1622:1622)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (651:651:651)) - (PORT datab (1155:1155:1155) (1200:1200:1200)) - (PORT datac (1451:1451:1451) (1502:1502:1502)) - (PORT datad (337:337:337) (358:358:358)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~7) - (DELAY - (ABSOLUTE - (PORT datac (1520:1520:1520) (1613:1613:1613)) - (PORT datad (1159:1159:1159) (1225:1225:1225)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1261:1261:1261) (1371:1371:1371)) - (PORT datab (865:865:865) (889:889:889)) - (PORT datac (1688:1688:1688) (1749:1749:1749)) - (PORT datad (267:267:267) (323:323:323)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1260:1260:1260) (1371:1371:1371)) - (PORT datab (465:465:465) (519:519:519)) - (PORT datac (1689:1689:1689) (1752:1752:1752)) - (PORT datad (268:268:268) (320:320:320)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1420:1420:1420) (1451:1451:1451)) - (PORT datab (1101:1101:1101) (1122:1122:1122)) - (PORT datac (1072:1072:1072) (1084:1084:1084)) - (PORT datad (939:939:939) (973:973:973)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (719:719:719)) - (PORT datab (1167:1167:1167) (1240:1240:1240)) - (PORT datac (1455:1455:1455) (1509:1509:1509)) - (PORT datad (1468:1468:1468) (1520:1520:1520)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (420:420:420)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (623:623:623) (666:666:666)) - (PORT datad (189:189:189) (220:220:220)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (566:566:566) (593:593:593)) - (PORT datab (860:860:860) (886:886:886)) - (PORT datac (854:854:854) (889:889:889)) - (PORT datad (805:805:805) (822:822:822)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1150:1150:1150) (1163:1163:1163)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (186:186:186) (228:228:228)) - (PORT datad (179:179:179) (206:206:206)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (483:483:483)) - (PORT datab (1218:1218:1218) (1272:1272:1272)) - (PORT datac (679:679:679) (709:709:709)) - (PORT datad (1295:1295:1295) (1387:1387:1387)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~8) - (DELAY - (ABSOLUTE - (PORT datab (2915:2915:2915) (3094:3094:3094)) - (PORT datac (2028:2028:2028) (2098:2098:2098)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1889:1889:1889) (1934:1934:1934)) - (PORT datab (2084:2084:2084) (2215:2215:2215)) - (PORT datac (1111:1111:1111) (1144:1144:1144)) - (PORT datad (208:208:208) (238:238:238)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) - (DELAY - (ABSOLUTE - (PORT datac (1234:1234:1234) (1326:1326:1326)) - (PORT datad (625:625:625) (665:665:665)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1232:1232:1232)) - (PORT datab (906:906:906) (961:961:961)) - (PORT datac (2032:2032:2032) (2056:2056:2056)) - (PORT datad (1479:1479:1479) (1541:1541:1541)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) - (DELAY - (ABSOLUTE - (PORT dataa (1057:1057:1057) (1151:1151:1151)) - (PORT datab (2381:2381:2381) (2493:2493:2493)) - (PORT datad (2113:2113:2113) (2257:2257:2257)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1487:1487:1487) (1536:1536:1536)) - (PORT datab (1011:1011:1011) (1078:1078:1078)) - (PORT datac (900:900:900) (921:921:921)) - (PORT datad (1172:1172:1172) (1187:1187:1187)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1450:1450:1450) (1479:1479:1479)) - (PORT datab (1137:1137:1137) (1178:1178:1178)) - (PORT datac (337:337:337) (365:365:365)) - (PORT datad (1137:1137:1137) (1159:1159:1159)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (412:412:412)) - (PORT datab (1088:1088:1088) (1114:1114:1114)) - (PORT datac (1575:1575:1575) (1617:1617:1617)) - (PORT datad (811:811:811) (828:828:828)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (1142:1142:1142) (1206:1206:1206)) - (PORT datab (1169:1169:1169) (1204:1204:1204)) - (PORT datac (835:835:835) (863:863:863)) - (PORT datad (800:800:800) (827:827:827)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1212:1212:1212)) - (PORT datab (286:286:286) (351:351:351)) - (PORT datac (253:253:253) (312:312:312)) - (PORT datad (252:252:252) (297:297:297)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) - (DELAY - (ABSOLUTE - (PORT datac (948:948:948) (1024:1024:1024)) - (PORT datad (2023:2023:2023) (2146:2146:2146)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (897:897:897)) - (PORT datab (1012:1012:1012) (1081:1081:1081)) - (PORT datac (1223:1223:1223) (1284:1284:1284)) - (PORT datad (1171:1171:1171) (1183:1183:1183)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) - (DELAY - (ABSOLUTE - (PORT datab (219:219:219) (257:257:257)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1230:1230:1230)) - (PORT datab (1013:1013:1013) (1082:1082:1082)) - (PORT datac (2030:2030:2030) (2056:2056:2056)) - (PORT datad (1479:1479:1479) (1543:1543:1543)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1303:1303:1303) (1377:1377:1377)) - (PORT datab (1170:1170:1170) (1231:1231:1231)) - (PORT datac (840:840:840) (887:887:887)) - (PORT datad (1322:1322:1322) (1434:1434:1434)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (984:984:984)) - (PORT datab (941:941:941) (1009:1009:1009)) - (PORT datac (1210:1210:1210) (1289:1289:1289)) - (PORT datad (658:658:658) (688:688:688)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1353:1353:1353) (1482:1482:1482)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (382:382:382) (410:410:410)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal69\~0) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (968:968:968)) - (PORT datab (1718:1718:1718) (1808:1808:1808)) - (PORT datac (1144:1144:1144) (1148:1148:1148)) - (PORT datad (653:653:653) (693:693:693)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1201:1201:1201) (1290:1290:1290)) - (PORT datad (1198:1198:1198) (1259:1259:1259)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1009:1009:1009) (1044:1044:1044)) - (PORT datab (2023:2023:2023) (2060:2060:2060)) - (PORT datac (1148:1148:1148) (1153:1153:1153)) - (PORT datad (650:650:650) (690:690:690)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1758:1758:1758) (1876:1876:1876)) - (PORT datab (915:915:915) (977:977:977)) - (PORT datad (216:216:216) (242:242:242)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal56\~0) - (DELAY - (ABSOLUTE - (PORT dataa (670:670:670) (725:725:725)) - (PORT datab (1178:1178:1178) (1215:1215:1215)) - (PORT datac (934:934:934) (1029:1029:1029)) - (PORT datad (903:903:903) (950:950:950)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1467:1467:1467) (1537:1537:1537)) - (PORT datab (1228:1228:1228) (1312:1312:1312)) - (PORT datac (1432:1432:1432) (1520:1520:1520)) - (PORT datad (820:820:820) (833:833:833)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~2) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (845:845:845)) - (PORT datab (854:854:854) (887:887:887)) - (PORT datad (673:673:673) (693:693:693)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) - (DELAY - (ABSOLUTE - (PORT dataa (2011:2011:2011) (2114:2114:2114)) - (PORT datab (2111:2111:2111) (2221:2221:2221)) - (PORT datac (547:547:547) (569:569:569)) - (PORT datad (1739:1739:1739) (1782:1782:1782)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (882:882:882)) - (PORT datab (952:952:952) (1011:1011:1011)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (1472:1472:1472) (1533:1533:1533)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~5) - (DELAY - (ABSOLUTE - (PORT datac (1162:1162:1162) (1174:1174:1174)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1237:1237:1237) (1303:1303:1303)) - (PORT datab (992:992:992) (1101:1101:1101)) - (PORT datac (657:657:657) (716:716:716)) - (PORT datad (1239:1239:1239) (1323:1323:1323)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) - (DELAY - (ABSOLUTE - (PORT datab (1082:1082:1082) (1193:1193:1193)) - (PORT datac (1465:1465:1465) (1548:1548:1548)) - (PORT datad (2348:2348:2348) (2497:2497:2497)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (726:726:726)) - (PORT datab (1800:1800:1800) (1830:1830:1830)) - (PORT datac (988:988:988) (1048:1048:1048)) - (PORT datad (1210:1210:1210) (1257:1257:1257)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1026:1026:1026) (1084:1084:1084)) - (PORT datab (1248:1248:1248) (1292:1292:1292)) - (PORT datac (1097:1097:1097) (1128:1128:1128)) - (PORT datad (183:183:183) (212:212:212)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) - (DELAY - (ABSOLUTE - (PORT dataa (942:942:942) (983:983:983)) - (PORT datab (1091:1091:1091) (1163:1163:1163)) - (PORT datac (985:985:985) (1050:1050:1050)) - (PORT datad (1157:1157:1157) (1206:1206:1206)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1013:1013:1013) (1086:1086:1086)) - (PORT datab (197:197:197) (234:234:234)) - (PORT datac (1253:1253:1253) (1320:1320:1320)) - (PORT datad (1054:1054:1054) (1123:1123:1123)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) - (DELAY - (ABSOLUTE - (PORT datab (1514:1514:1514) (1650:1650:1650)) - (PORT datac (1504:1504:1504) (1617:1617:1617)) - (PORT datad (1306:1306:1306) (1325:1325:1325)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (831:831:831)) - (PORT datab (860:860:860) (870:870:870)) - (PORT datac (1242:1242:1242) (1262:1262:1262)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1415:1415:1415) (1454:1454:1454)) - (PORT datab (2084:2084:2084) (2114:2114:2114)) - (PORT datac (835:835:835) (859:859:859)) - (PORT datad (788:788:788) (798:798:798)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal48\~0) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (968:968:968)) - (PORT datab (1718:1718:1718) (1807:1807:1807)) - (PORT datac (1144:1144:1144) (1148:1148:1148)) - (PORT datad (654:654:654) (693:693:693)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) - (DELAY - (ABSOLUTE - (PORT dataa (922:922:922) (998:998:998)) - (PORT datab (900:900:900) (985:985:985)) - (PORT datac (966:966:966) (1015:1015:1015)) - (PORT datad (1295:1295:1295) (1365:1365:1365)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (1246:1246:1246) (1336:1336:1336)) - (PORT datab (1005:1005:1005) (1056:1056:1056)) - (PORT datac (209:209:209) (248:248:248)) - (PORT datad (1195:1195:1195) (1244:1244:1244)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1847:1847:1847) (1960:1960:1960)) - (PORT datab (1294:1294:1294) (1397:1397:1397)) - (PORT datac (2030:2030:2030) (2118:2118:2118)) - (PORT datad (836:836:836) (843:843:843)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1215:1215:1215) (1251:1251:1251)) - (PORT datab (1013:1013:1013) (1076:1076:1076)) - (PORT datac (621:621:621) (659:659:659)) - (PORT datad (1176:1176:1176) (1188:1188:1188)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) - (DELAY - (ABSOLUTE - (PORT dataa (886:886:886) (945:945:945)) - (PORT datab (1062:1062:1062) (1128:1128:1128)) - (PORT datac (579:579:579) (602:602:602)) - (PORT datad (1089:1089:1089) (1104:1104:1104)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1618:1618:1618) (1711:1711:1711)) - (PORT datab (1527:1527:1527) (1658:1658:1658)) - (PORT datac (1710:1710:1710) (1825:1825:1825)) - (PORT datad (1448:1448:1448) (1496:1496:1496)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1670:1670:1670) (1753:1753:1753)) - (PORT datab (1528:1528:1528) (1617:1617:1617)) - (PORT datac (966:966:966) (1014:1014:1014)) - (PORT datad (1159:1159:1159) (1218:1218:1218)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (622:622:622)) - (PORT datab (923:923:923) (944:944:944)) - (PORT datac (969:969:969) (1018:1018:1018)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1638:1638:1638) (1764:1764:1764)) - (PORT datab (1075:1075:1075) (1149:1149:1149)) - (PORT datac (1806:1806:1806) (1948:1948:1948)) - (PORT datad (942:942:942) (974:974:974)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1241:1241:1241) (1294:1294:1294)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (972:972:972) (992:992:992)) - (PORT datad (902:902:902) (955:955:955)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1348:1348:1348) (1398:1398:1398)) - (PORT datab (1002:1002:1002) (1057:1057:1057)) - (PORT datac (575:575:575) (596:596:596)) - (PORT datad (637:637:637) (681:681:681)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal20\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1988:1988:1988) (2128:2128:2128)) - (PORT datab (1534:1534:1534) (1632:1632:1632)) - (PORT datac (227:227:227) (272:272:272)) - (PORT datad (1108:1108:1108) (1149:1149:1149)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal68\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1617:1617:1617) (1711:1711:1711)) - (PORT datab (1528:1528:1528) (1657:1657:1657)) - (PORT datac (1709:1709:1709) (1824:1824:1824)) - (PORT datad (1448:1448:1448) (1496:1496:1496)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (922:922:922) (983:983:983)) - (PORT datab (1427:1427:1427) (1510:1510:1510)) - (PORT datac (1333:1333:1333) (1448:1448:1448)) - (PORT datad (1550:1550:1550) (1659:1659:1659)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~13) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (721:721:721)) - (PORT datab (1637:1637:1637) (1642:1642:1642)) - (PORT datac (1298:1298:1298) (1314:1314:1314)) - (PORT datad (1443:1443:1443) (1563:1563:1563)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1580:1580:1580) (1703:1703:1703)) - (PORT datab (1365:1365:1365) (1479:1479:1479)) - (PORT datac (1152:1152:1152) (1186:1186:1186)) - (PORT datad (832:832:832) (834:834:834)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (672:672:672) (729:729:729)) - (PORT datab (995:995:995) (1057:1057:1057)) - (PORT datac (1074:1074:1074) (1196:1196:1196)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~11) - (DELAY - (ABSOLUTE - (PORT dataa (2265:2265:2265) (2414:2414:2414)) - (PORT datab (848:848:848) (886:886:886)) - (PORT datac (2113:2113:2113) (2221:2221:2221)) - (PORT datad (669:669:669) (694:694:694)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (996:996:996)) - (PORT datab (1005:1005:1005) (1060:1060:1060)) - (PORT datac (1413:1413:1413) (1487:1487:1487)) - (PORT datad (1522:1522:1522) (1622:1622:1622)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (684:684:684)) - (PORT datab (440:440:440) (477:477:477)) - (PORT datac (202:202:202) (238:238:238)) - (PORT datad (1428:1428:1428) (1432:1432:1432)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (662:662:662)) - (PORT datab (1001:1001:1001) (1053:1053:1053)) - (PORT datac (870:870:870) (914:914:914)) - (PORT datad (809:809:809) (854:854:854)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (392:392:392)) - (PORT datab (331:331:331) (360:360:360)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (228:228:228) (271:271:271)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (657:657:657)) - (PORT datab (1415:1415:1415) (1491:1491:1491)) - (PORT datac (638:638:638) (658:658:658)) - (PORT datad (1624:1624:1624) (1706:1706:1706)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (702:702:702)) - (PORT datab (995:995:995) (1056:1056:1056)) - (PORT datac (1075:1075:1075) (1194:1194:1194)) - (PORT datad (2306:2306:2306) (2342:2342:2342)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (980:980:980)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (346:346:346) (371:371:371)) - (PORT datad (2307:2307:2307) (2344:2344:2344)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~4) - (DELAY - (ABSOLUTE - (PORT datab (1060:1060:1060) (1178:1178:1178)) - (PORT datac (1452:1452:1452) (1530:1530:1530)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1391:1391:1391) (1453:1453:1453)) - (PORT datab (942:942:942) (993:993:993)) - (PORT datac (1045:1045:1045) (1115:1115:1115)) - (PORT datad (1421:1421:1421) (1470:1470:1470)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (969:969:969) (1009:1009:1009)) - (PORT datab (1445:1445:1445) (1500:1500:1500)) - (PORT datac (972:972:972) (995:995:995)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1123:1123:1123)) - (PORT datab (1196:1196:1196) (1246:1246:1246)) - (PORT datac (663:663:663) (712:712:712)) - (PORT datad (879:879:879) (931:931:931)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (616:616:616)) - (PORT datac (573:573:573) (593:593:593)) - (PORT datad (531:531:531) (543:543:543)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (303:303:303)) - (PORT datab (1244:1244:1244) (1269:1269:1269)) - (PORT datac (1174:1174:1174) (1214:1214:1214)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (925:925:925)) - (PORT datab (852:852:852) (865:865:865)) - (PORT datac (342:342:342) (367:367:367)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1987:1987:1987) (2132:2132:2132)) - (PORT datab (903:903:903) (955:955:955)) - (PORT datac (224:224:224) (269:269:269)) - (PORT datad (1402:1402:1402) (1466:1466:1466)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) - (DELAY - (ABSOLUTE - (PORT dataa (1798:1798:1798) (1933:1933:1933)) - (PORT datab (1613:1613:1613) (1726:1726:1726)) - (PORT datad (1409:1409:1409) (1475:1475:1475)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) - (DELAY - (ABSOLUTE - (PORT dataa (2050:2050:2050) (2089:2089:2089)) - (PORT datab (946:946:946) (1023:1023:1023)) - (PORT datac (1099:1099:1099) (1158:1158:1158)) - (PORT datad (914:914:914) (1002:1002:1002)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1335:1335:1335) (1354:1354:1354)) - (PORT datab (1166:1166:1166) (1239:1239:1239)) - (PORT datac (1485:1485:1485) (1514:1514:1514)) - (PORT datad (1468:1468:1468) (1520:1520:1520)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (1144:1144:1144) (1189:1189:1189)) - (PORT datab (222:222:222) (269:269:269)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (836:836:836) (868:868:868)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT datab (963:963:963) (1010:1010:1010)) - (PORT datac (601:601:601) (607:607:607)) - (PORT datad (676:676:676) (718:718:718)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) - (DELAY - (ABSOLUTE - (PORT datac (928:928:928) (973:973:973)) - (PORT datad (680:680:680) (720:720:720)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) - (DELAY - (ABSOLUTE - (PORT dataa (1003:1003:1003) (1064:1064:1064)) - (PORT datab (717:717:717) (774:774:774)) - (PORT datac (903:903:903) (944:944:944)) - (PORT datad (1740:1740:1740) (1858:1858:1858)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1494:1494:1494) (1600:1600:1600)) - (PORT datab (1475:1475:1475) (1582:1582:1582)) - (PORT datac (1847:1847:1847) (1916:1916:1916)) - (PORT datad (402:402:402) (439:439:439)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1219:1219:1219) (1306:1306:1306)) - (PORT datac (943:943:943) (1021:1021:1021)) - (PORT datad (1208:1208:1208) (1293:1293:1293)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1221:1221:1221) (1285:1285:1285)) - (PORT datab (1430:1430:1430) (1456:1456:1456)) - (PORT datac (1096:1096:1096) (1116:1116:1116)) - (PORT datad (1325:1325:1325) (1332:1332:1332)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) - (DELAY - (ABSOLUTE - (PORT datab (934:934:934) (968:968:968)) - (PORT datac (531:531:531) (544:544:544)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1001:1001:1001) (1063:1063:1063)) - (PORT datab (717:717:717) (773:773:773)) - (PORT datac (901:901:901) (942:942:942)) - (PORT datad (1738:1738:1738) (1857:1857:1857)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1357:1357:1357) (1397:1397:1397)) - (PORT datab (917:917:917) (962:962:962)) - (PORT datad (619:619:619) (654:654:654)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (864:864:864) (915:915:915)) - (PORT datab (1463:1463:1463) (1548:1548:1548)) - (PORT datac (1313:1313:1313) (1405:1405:1405)) - (PORT datad (2215:2215:2215) (2336:2336:2336)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~36) - (DELAY - (ABSOLUTE - (PORT dataa (2340:2340:2340) (2463:2463:2463)) - (PORT datab (901:901:901) (951:951:951)) - (PORT datac (370:370:370) (398:398:398)) - (PORT datad (1461:1461:1461) (1558:1558:1558)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (258:258:258)) - (PORT datab (239:239:239) (284:284:284)) - (PORT datac (839:839:839) (874:874:874)) - (PORT datad (554:554:554) (572:572:572)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~5) - (DELAY - (ABSOLUTE - (PORT datac (2441:2441:2441) (2623:2623:2623)) - (PORT datad (1996:1996:1996) (2085:2085:2085)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE 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(193:193:193) (226:226:226)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) - (DELAY - (ABSOLUTE - (PORT dataa (819:819:819) (841:841:841)) - (PORT datab (697:697:697) (728:728:728)) - (PORT datac (916:916:916) (968:968:968)) - (PORT datad (816:816:816) (839:839:839)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) - (DELAY - (ABSOLUTE - (PORT datab (869:869:869) (890:890:890)) - (PORT datad (810:810:810) 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(242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1437:1437:1437) (1451:1451:1451)) - (PORT datab (1439:1439:1439) (1497:1497:1497)) - (PORT datac (974:974:974) (995:995:995)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1814:1814:1814) (1850:1850:1850)) - (PORT datab (1003:1003:1003) (1029:1029:1029)) - (PORT datac (315:315:315) (336:336:336)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (706:706:706)) - (PORT datab (608:608:608) (621:621:621)) - (PORT datac (813:813:813) (840:840:840)) - (PORT datad (337:337:337) (356:356:356)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1292:1292:1292) (1357:1357:1357)) - (PORT datab (986:986:986) (1070:1070:1070)) - (PORT datac (1073:1073:1073) (1153:1153:1153)) - (PORT datad (966:966:966) (1077:1077:1077)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1463:1463:1463) (1478:1478:1478)) - (PORT datab (1379:1379:1379) (1398:1398:1398)) - (PORT datac (1618:1618:1618) (1662:1662:1662)) - (PORT datad (1263:1263:1263) (1327:1327:1327)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1202:1202:1202) (1231:1231:1231)) - (PORT datab (1048:1048:1048) (1149:1149:1149)) - (PORT datad (1348:1348:1348) (1490:1490:1490)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (681:681:681) (736:736:736)) - (PORT datab (1001:1001:1001) (1033:1033:1033)) - (PORT datac (553:553:553) (568:568:568)) - (PORT datad (222:222:222) (249:249:249)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (737:737:737) (798:798:798)) - (PORT datab (948:948:948) (1025:1025:1025)) - (PORT datac (1099:1099:1099) (1159:1159:1159)) - (PORT datad (909:909:909) (998:998:998)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1225:1225:1225) (1294:1294:1294)) - (PORT datab (224:224:224) (271:271:271)) - (PORT datac (2351:2351:2351) (2449:2449:2449)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal8\~0) - (DELAY - (ABSOLUTE - (PORT datab (2076:2076:2076) (2143:2143:2143)) - (PORT datac (1719:1719:1719) (1796:1796:1796)) - (PORT datad (1155:1155:1155) (1236:1236:1236)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1450:1450:1450) (1501:1501:1501)) - (PORT datab (1425:1425:1425) (1462:1462:1462)) - (PORT datac (836:836:836) (865:865:865)) - (PORT datad (394:394:394) (429:429:429)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (894:894:894)) - (PORT datab (1197:1197:1197) (1223:1223:1223)) - (PORT datac (981:981:981) (1043:1043:1043)) - (PORT datad (972:972:972) (1036:1036:1036)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (2006:2006:2006) (2147:2147:2147)) - (PORT datab (450:450:450) (480:480:480)) - (PORT datac (1000:1000:1000) (1045:1045:1045)) - (PORT datad (900:900:900) (950:950:950)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~1) - (DELAY - (ABSOLUTE - (PORT datac (1589:1589:1589) (1676:1676:1676)) - (PORT datad (1494:1494:1494) (1621:1621:1621)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) - (DELAY - (ABSOLUTE - (PORT dataa (959:959:959) (1016:1016:1016)) - (PORT datab (1194:1194:1194) (1223:1223:1223)) - (PORT datac (1942:1942:1942) (2000:2000:2000)) - (PORT datad (641:641:641) (693:693:693)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (627:627:627) (662:662:662)) - (PORT datac (1683:1683:1683) (1789:1789:1789)) - (PORT datad (633:633:633) (651:651:651)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1500:1500:1500) (1575:1575:1575)) - (PORT datab (362:362:362) (397:397:397)) - (PORT datac (2091:2091:2091) (2220:2220:2220)) - (PORT datad (590:590:590) (607:607:607)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (736:736:736) (800:800:800)) - (PORT datab (947:947:947) (1025:1025:1025)) - (PORT datac (1098:1098:1098) (1158:1158:1158)) - (PORT datad (911:911:911) (1001:1001:1001)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) - (DELAY - (ABSOLUTE - (PORT dataa (1465:1465:1465) (1539:1539:1539)) - (PORT datab (1227:1227:1227) (1318:1318:1318)) - (PORT datac (1459:1459:1459) (1517:1517:1517)) - (PORT datad (1138:1138:1138) (1159:1159:1159)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1840:1840:1840) (1939:1939:1939)) - (PORT datab (2068:2068:2068) (2187:2187:2187)) - (PORT datac (1327:1327:1327) (1336:1336:1336)) - (PORT datad (2013:2013:2013) (2125:2125:2125)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1215:1215:1215)) - (PORT datab (653:653:653) (674:674:674)) - (PORT datac (1214:1214:1214) (1294:1294:1294)) - (PORT datad (596:596:596) (619:619:619)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1170:1170:1170)) - (PORT datab (841:841:841) (864:864:864)) - (PORT datad (579:579:579) (590:590:590)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) - (DELAY - (ABSOLUTE - (PORT datac (1753:1753:1753) (1873:1873:1873)) - (PORT datad (1571:1571:1571) (1694:1694:1694)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1025:1025:1025) (1056:1056:1056)) - (PORT datab (1039:1039:1039) (1096:1096:1096)) - (PORT datac (1052:1052:1052) (1117:1117:1117)) - (PORT datad (625:625:625) (651:651:651)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1581:1581:1581) (1726:1726:1726)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (1053:1053:1053) (1117:1117:1117)) - (PORT datad (1795:1795:1795) (1930:1930:1930)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1219:1219:1219) (1272:1272:1272)) - (PORT datab (689:689:689) (706:706:706)) - (PORT datac (1267:1267:1267) (1395:1395:1395)) - (PORT datad (1570:1570:1570) (1720:1720:1720)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (1265:1265:1265) (1395:1395:1395)) - (PORT datad (1573:1573:1573) (1723:1723:1723)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1230:1230:1230) (1277:1277:1277)) - (PORT datab (1647:1647:1647) (1673:1673:1673)) - (PORT datac (777:777:777) (786:786:786)) - (PORT datad (581:581:581) (600:600:600)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (652:652:652)) - (PORT datab (656:656:656) (711:711:711)) - (PORT datac (680:680:680) (730:730:730)) - (PORT datad (800:800:800) (871:871:871)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1001:1001:1001) (1087:1087:1087)) - (PORT datab (1683:1683:1683) (1741:1741:1741)) - (PORT datac (1582:1582:1582) (1690:1690:1690)) - (PORT datad (964:964:964) (1004:1004:1004)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1288:1288:1288) (1342:1342:1342)) - (PORT datab (935:935:935) (949:949:949)) - (PORT datac (978:978:978) (1043:1043:1043)) - (PORT datad (1176:1176:1176) (1188:1188:1188)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (390:390:390)) - (PORT datab (1476:1476:1476) (1506:1506:1506)) - (PORT datac (1080:1080:1080) (1084:1084:1084)) - (PORT datad (1360:1360:1360) (1375:1375:1375)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (392:392:392)) - (PORT datab (238:238:238) (276:276:276)) - (PORT datac (1044:1044:1044) (1080:1080:1080)) - (PORT datad (1386:1386:1386) (1428:1428:1428)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (869:869:869) (907:907:907)) - (PORT datab (364:364:364) (400:400:400)) - (PORT datac (656:656:656) (701:701:701)) - (PORT datad (837:837:837) (878:878:878)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (810:810:810)) - (PORT datab (933:933:933) (988:988:988)) - (PORT datac (981:981:981) (1058:1058:1058)) - (PORT datad (194:194:194) (218:218:218)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1441:1441:1441) (1552:1552:1552)) - (PORT datab (614:614:614) (644:644:644)) - (PORT datac (1197:1197:1197) (1258:1258:1258)) - (PORT datad (844:844:844) (855:855:855)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (275:275:275)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (588:588:588) (608:608:608)) - (PORT datad (876:876:876) (896:896:896)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1212:1212:1212) (1250:1250:1250)) - (PORT datab (965:965:965) (1013:1013:1013)) - (PORT datac (1049:1049:1049) (1111:1111:1111)) - (PORT datad (1444:1444:1444) (1477:1477:1477)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1082:1082:1082) (1153:1153:1153)) - (PORT datab (970:970:970) (1019:1019:1019)) - (PORT datac (308:308:308) (334:334:334)) - (PORT datad (628:628:628) (654:654:654)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1024:1024:1024) (1085:1085:1085)) - (PORT datab (1386:1386:1386) (1414:1414:1414)) - (PORT datac (1180:1180:1180) (1211:1211:1211)) - (PORT datad (1209:1209:1209) (1252:1252:1252)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (1246:1246:1246) (1296:1296:1296)) - (PORT datac (984:984:984) (1048:1048:1048)) - (PORT datad (625:625:625) (654:654:654)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (910:910:910)) - (PORT datab (1428:1428:1428) (1466:1466:1466)) - (PORT datac (1688:1688:1688) (1726:1726:1726)) - (PORT datad (2057:2057:2057) (2190:2190:2190)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (642:642:642)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (1398:1398:1398) (1422:1422:1422)) - (PORT datad (1424:1424:1424) (1462:1462:1462)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1803:1803:1803) (1945:1945:1945)) - (PORT datab (847:847:847) (858:858:858)) - (PORT datac (838:838:838) (869:869:869)) - (PORT datad (2056:2056:2056) (2191:2191:2191)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (847:847:847)) - (PORT datab (783:783:783) (809:809:809)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (382:382:382)) - (PORT datab (220:220:220) (258:258:258)) - (PORT datac (193:193:193) (227:227:227)) - (PORT datad (539:539:539) (561:561:561)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (952:952:952) (1004:1004:1004)) - (PORT datab (876:876:876) (893:893:893)) - (PORT datac (1689:1689:1689) (1781:1781:1781)) - (PORT datad (1175:1175:1175) (1232:1232:1232)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1346:1346:1346) (1340:1340:1340)) - (PORT datab (1176:1176:1176) (1219:1219:1219)) - (PORT datac (1123:1123:1123) (1137:1137:1137)) - (PORT datad (665:665:665) (719:719:719)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1197:1197:1197) (1247:1247:1247)) - (PORT datac (582:582:582) (614:614:614)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1190:1190:1190) (1242:1242:1242)) - (PORT datab (650:650:650) (679:679:679)) - (PORT datac (191:191:191) (237:237:237)) - (PORT datad (607:607:607) (635:635:635)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (274:274:274)) - (PORT datac (2094:2094:2094) (2219:2219:2219)) - (PORT datad (1462:1462:1462) (1527:1527:1527)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (461:461:461)) - (PORT datab (1161:1161:1161) (1190:1190:1190)) - (PORT datac (1460:1460:1460) (1518:1518:1518)) - (PORT datad (1106:1106:1106) (1136:1136:1136)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1080:1080:1080) (1147:1147:1147)) - (PORT datab (1037:1037:1037) (1105:1105:1105)) - (PORT datac (1180:1180:1180) (1210:1210:1210)) - (PORT datad (1210:1210:1210) (1252:1252:1252)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (919:919:919)) - (PORT datab (661:661:661) (705:705:705)) - (PORT datac (1104:1104:1104) (1117:1117:1117)) - (PORT datad (766:766:766) (786:786:786)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1156:1156:1156)) - (PORT datab (1528:1528:1528) (1657:1657:1657)) - (PORT datac (609:609:609) (665:665:665)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (734:734:734) (762:762:762)) - (PORT datab (849:849:849) (885:885:885)) - (PORT datac (787:787:787) (804:804:804)) - (PORT datad (670:670:670) (694:694:694)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1025:1025:1025) (1084:1084:1084)) - (PORT datab (969:969:969) (1019:1019:1019)) - (PORT datac (192:192:192) (223:223:223)) - (PORT datad (1444:1444:1444) (1475:1475:1475)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1298:1298:1298) (1390:1390:1390)) - (PORT datab (968:968:968) (1017:1017:1017)) - (PORT datac (1050:1050:1050) (1110:1110:1110)) - (PORT datad (1553:1553:1553) (1682:1682:1682)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1298:1298:1298) (1391:1391:1391)) - (PORT datab (1247:1247:1247) (1291:1291:1291)) - (PORT datac (985:985:985) (1043:1043:1043)) - (PORT datad (1553:1553:1553) (1682:1682:1682)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (564:564:564) (579:579:579)) - (PORT datab (244:244:244) (288:288:288)) - (PORT datac (543:543:543) (551:551:551)) - (PORT datad (1454:1454:1454) (1511:1511:1511)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (1400:1400:1400) (1422:1422:1422)) - (PORT datac (572:572:572) (596:596:596)) - (PORT datad (602:602:602) (630:630:630)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (681:681:681) (737:737:737)) - (PORT datab (1115:1115:1115) (1164:1164:1164)) - (PORT datac (969:969:969) (1001:1001:1001)) - (PORT datad (1160:1160:1160) (1223:1223:1223)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (984:984:984)) - (PORT datab (941:941:941) (1009:1009:1009)) - (PORT datac (1210:1210:1210) (1289:1289:1289)) - (PORT datad (381:381:381) (406:406:406)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1765:1765:1765) (1808:1808:1808)) - (PORT datab (1620:1620:1620) (1658:1658:1658)) - (PORT datac (1305:1305:1305) (1421:1421:1421)) - (PORT datad (1541:1541:1541) (1677:1677:1677)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1103:1103:1103) (1119:1119:1119)) - (PORT datab (1046:1046:1046) (1094:1094:1094)) - (PORT datac (952:952:952) (984:984:984)) - (PORT datad (819:819:819) (844:844:844)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (982:982:982) (1023:1023:1023)) - (PORT datab (700:700:700) (721:721:721)) - (PORT datac (216:216:216) (260:260:260)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (874:874:874)) - (PORT datab (648:648:648) (669:669:669)) - (PORT datac (877:877:877) (899:899:899)) - (PORT datad (813:813:813) (834:834:834)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (363:363:363) (397:397:397)) - (PORT datac (964:964:964) (1033:1033:1033)) - (PORT datad (590:590:590) (607:607:607)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datac (1711:1711:1711) (1773:1773:1773)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (296:296:296)) - (PORT datab (1200:1200:1200) (1240:1240:1240)) - (PORT datac (1213:1213:1213) (1232:1232:1232)) - (PORT datad (559:559:559) (571:571:571)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1102:1102:1102) (1121:1121:1121)) - (PORT datab (246:246:246) (294:294:294)) - (PORT datac (901:901:901) (943:943:943)) - (PORT datad (1975:1975:1975) (2012:2012:2012)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (823:823:823) (840:840:840)) - (PORT datab (850:850:850) (877:877:877)) - (PORT datac (595:595:595) (617:617:617)) - (PORT datad (811:811:811) (824:824:824)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (2154:2154:2154) (2304:2304:2304)) - (PORT datab (1756:1756:1756) (1875:1875:1875)) - (PORT datac (868:868:868) (905:905:905)) - (PORT datad (2343:2343:2343) (2450:2450:2450)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (963:963:963) (1025:1025:1025)) - (PORT datab (2108:2108:2108) (2222:2222:2222)) - (PORT datac (548:548:548) (573:573:573)) - (PORT datad (1982:1982:1982) (2069:2069:2069)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~54) - (DELAY - (ABSOLUTE - (PORT dataa (1779:1779:1779) (1888:1888:1888)) - (PORT datab (1077:1077:1077) (1152:1152:1152)) - (PORT datac (971:971:971) (991:991:991)) - (PORT datad (2049:2049:2049) (2156:2156:2156)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1244:1244:1244)) - (PORT datab (1192:1192:1192) (1241:1241:1241)) - (PORT datac (610:610:610) (626:626:626)) - (PORT datad (2306:2306:2306) (2345:2345:2345)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (998:998:998) (1033:1033:1033)) - (PORT datab (1150:1150:1150) (1177:1177:1177)) - (PORT datac (346:346:346) (385:385:385)) - (PORT datad (630:630:630) (669:669:669)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (890:890:890)) - (PORT datac (839:839:839) (858:858:858)) - (PORT datad (520:520:520) (531:531:531)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (288:288:288)) - (PORT datab (250:250:250) (300:300:300)) - (PORT datac (1960:1960:1960) (2089:2089:2089)) - (PORT datad (202:202:202) (238:238:238)) - (IOPATH dataa combout (303:303:303) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1352:1352:1352) (1478:1478:1478)) - (PORT datab (1346:1346:1346) (1363:1363:1363)) - (PORT datac (870:870:870) (896:896:896)) - (PORT datad (1449:1449:1449) (1511:1511:1511)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1104:1104:1104) (1189:1189:1189)) - (PORT datab (685:685:685) (754:754:754)) - (PORT datac (958:958:958) (1039:1039:1039)) - (PORT datad (613:613:613) (629:629:629)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (664:664:664)) - (PORT datab (973:973:973) (1069:1069:1069)) - (PORT datac (1733:1733:1733) (1832:1832:1832)) - (PORT datad (1149:1149:1149) (1173:1173:1173)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1999:1999:1999) (2036:2036:2036)) - (PORT datab (872:872:872) (899:899:899)) - (PORT datac (1356:1356:1356) (1432:1432:1432)) - (PORT datad (1348:1348:1348) (1396:1396:1396)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (650:650:650)) - (PORT datab (1061:1061:1061) (1123:1123:1123)) - (PORT datac (208:208:208) (247:247:247)) - (PORT datad (864:864:864) (923:923:923)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (632:632:632)) - (PORT datab (203:203:203) (245:245:245)) - (PORT datac (877:877:877) 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- (PORT datab (1166:1166:1166) (1236:1236:1236)) - (PORT datac (1485:1485:1485) (1511:1511:1511)) - (PORT datad (1469:1469:1469) (1516:1516:1516)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (880:880:880)) - (PORT datab (1385:1385:1385) (1395:1395:1395)) - (PORT datac (777:777:777) (796:796:796)) - (PORT datad (1739:1739:1739) (1779:1779:1779)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel3) - (DELAY - (ABSOLUTE - (PORT dataa (1404:1404:1404) (1480:1480:1480)) - (PORT datab (2358:2358:2358) (2492:2492:2492)) - (PORT datac (1133:1133:1133) (1174:1174:1174)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (966:966:966) (1016:1016:1016)) - (PORT datab (1031:1031:1031) (1053:1053:1053)) - (PORT datac (181:181:181) (219:219:219)) - (PORT datad (652:652:652) (692:692:692)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (616:616:616)) - (PORT datab (672:672:672) (701:701:701)) - (PORT datac (510:510:510) (522:522:522)) - (PORT datad (840:840:840) (853:853:853)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (256:256:256)) - (PORT datab (884:884:884) (911:911:911)) - (PORT datac (866:866:866) (930:930:930)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel0) - (DELAY - (ABSOLUTE - (PORT dataa (2169:2169:2169) (2322:2322:2322)) - (PORT datac (1461:1461:1461) (1534:1534:1534)) - (PORT datad (2260:2260:2260) (2326:2326:2326)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) - (DELAY - (ABSOLUTE - (PORT datab (924:924:924) (1011:1011:1011)) - (PORT datac (1545:1545:1545) (1672:1672:1672)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (705:705:705) (747:747:747)) - (PORT datab (868:868:868) (890:890:890)) - (PORT datac (1285:1285:1285) (1378:1378:1378)) - (PORT datad (896:896:896) (936:936:936)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1484:1484:1484) (1547:1547:1547)) - (PORT datab (205:205:205) (245:245:245)) - (PORT datac (988:988:988) (1034:1034:1034)) - (PORT datad (1031:1031:1031) (1081:1081:1081)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (236:236:236) (286:286:286)) - (PORT datab (373:373:373) (398:398:398)) - (PORT datac (599:599:599) (641:641:641)) - (PORT datad (200:200:200) (235:235:235)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1623:1623:1623) (1713:1713:1713)) - (PORT datab (1529:1529:1529) (1662:1662:1662)) - (PORT datac (1705:1705:1705) (1826:1826:1826)) - (PORT datad (1447:1447:1447) (1495:1495:1495)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1779:1779:1779) (1826:1826:1826)) - (PORT datab (681:681:681) (732:732:732)) - (PORT datac (551:551:551) (571:571:571)) - (PORT datad (1134:1134:1134) (1177:1177:1177)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (688:688:688) (759:759:759)) - (PORT datab (1001:1001:1001) (1109:1109:1109)) - (PORT datac (192:192:192) (226:226:226)) - (PORT datad (1242:1242:1242) (1328:1328:1328)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (598:598:598) (630:630:630)) - (PORT datab (875:875:875) (920:920:920)) - (PORT datac (338:338:338) (364:364:364)) - (PORT datad (685:685:685) (739:739:739)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (707:707:707)) - (PORT datab (950:950:950) (1008:1008:1008)) - (PORT datac (590:590:590) (605:605:605)) - (PORT datad (654:654:654) (692:692:692)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1138:1138:1138) (1171:1171:1171)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (566:566:566) (595:595:595)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (494:494:494)) - (PORT datab (1299:1299:1299) (1396:1396:1396)) - (PORT datac (680:680:680) (764:764:764)) - (PORT datad (1300:1300:1300) (1391:1391:1391)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1581:1581:1581) (1626:1626:1626)) - (PORT datab (906:906:906) (950:950:950)) - (PORT datac (1263:1263:1263) (1320:1320:1320)) - (PORT datad (1666:1666:1666) (1688:1688:1688)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (401:401:401)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (653:653:653) (714:714:714)) - (PORT datad (1668:1668:1668) (1689:1689:1689)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1304:1304:1304) (1373:1373:1373)) - (PORT datab (1184:1184:1184) (1235:1235:1235)) - (PORT datac (1139:1139:1139) (1197:1197:1197)) - (PORT datad (1323:1323:1323) (1433:1433:1433)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) - (DELAY - (ABSOLUTE - (PORT dataa (908:908:908) (940:940:940)) - (PORT datab (380:380:380) (410:410:410)) - (PORT datac (654:654:654) (698:698:698)) - (PORT datad (1204:1204:1204) (1277:1277:1277)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1116:1116:1116)) - (PORT datab (917:917:917) (963:963:963)) - (PORT datac (1010:1010:1010) (1060:1060:1060)) - (PORT datad (924:924:924) (954:954:954)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (251:251:251)) - (PORT datab (964:964:964) (1061:1061:1061)) - (PORT datac (844:844:844) (886:886:886)) - (PORT datad (905:905:905) (950:950:950)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) - (DELAY - (ABSOLUTE - (PORT dataa (998:998:998) (1084:1084:1084)) - (PORT datab (1205:1205:1205) (1272:1272:1272)) - (PORT datac (1579:1579:1579) (1687:1687:1687)) - (PORT datad (1138:1138:1138) (1195:1195:1195)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (653:653:653)) - (PORT datab (2073:2073:2073) (2252:2252:2252)) - (PORT datac (861:861:861) (894:894:894)) - (PORT datad (1257:1257:1257) (1349:1349:1349)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (961:961:961)) - (PORT datab (916:916:916) (955:955:955)) - (PORT datac (1131:1131:1131) (1156:1156:1156)) - (PORT datad (926:926:926) (955:955:955)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~92) - (DELAY - (ABSOLUTE - (PORT dataa (1028:1028:1028) (1147:1147:1147)) - (PORT datab (1588:1588:1588) (1723:1723:1723)) - (PORT datac (637:637:637) (656:656:656)) - (PORT datad (1691:1691:1691) (1790:1790:1790)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2337:2337:2337) (2490:2490:2490)) - (PORT datab (1668:1668:1668) (1785:1785:1785)) - (PORT datac (905:905:905) (956:956:956)) - (PORT datad (672:672:672) (720:720:720)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1009:1009:1009) (1130:1130:1130)) - (PORT datad (1542:1542:1542) (1657:1657:1657)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1306:1306:1306) (1373:1373:1373)) - (PORT datab (656:656:656) (703:703:703)) - (PORT datac (1351:1351:1351) (1409:1409:1409)) - (PORT datad (881:881:881) (908:908:908)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~93) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1148:1148:1148)) - (PORT datab (1720:1720:1720) (1825:1825:1825)) - (PORT datac (1557:1557:1557) (1685:1685:1685)) - (PORT datad (1001:1001:1001) (1102:1102:1102)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1356:1356:1356) (1478:1478:1478)) - (PORT datab (827:827:827) (854:854:854)) - (PORT datac (1113:1113:1113) (1149:1149:1149)) - (PORT datad (635:635:635) (687:687:687)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~24) - (DELAY - (ABSOLUTE - (PORT datab (1169:1169:1169) (1230:1230:1230)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (183:183:183) (212:212:212)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (851:851:851) (919:919:919)) - (PORT datac (194:194:194) (241:241:241)) - (PORT datad (673:673:673) (732:732:732)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) - (DELAY - (ABSOLUTE - (PORT dataa (968:968:968) (1052:1052:1052)) - (PORT datab (936:936:936) (1006:1006:1006)) - (PORT datac (1407:1407:1407) (1449:1449:1449)) - (PORT datad (537:537:537) (548:548:548)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (620:620:620)) - (PORT datab (867:867:867) (902:902:902)) - (PORT datac (1366:1366:1366) (1470:1470:1470)) - (PORT datad (1496:1496:1496) (1606:1606:1606)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (951:951:951) (985:985:985)) - (PORT datab (916:916:916) (957:957:957)) - (PORT datac (915:915:915) (950:950:950)) - (PORT datad (1540:1540:1540) (1625:1625:1625)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1174:1174:1174) (1214:1214:1214)) - (PORT datab (649:649:649) (694:694:694)) - (PORT datac (902:902:902) (950:950:950)) - (PORT datad (338:338:338) (355:355:355)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) - (DELAY - (ABSOLUTE - (PORT datab (1511:1511:1511) (1618:1618:1618)) - (PORT datac (1726:1726:1726) (1837:1837:1837)) - (PORT datad (1072:1072:1072) (1082:1082:1082)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (734:734:734)) - (PORT datab (1163:1163:1163) (1210:1210:1210)) - (PORT datac (852:852:852) (881:881:881)) - (PORT datad (1173:1173:1173) (1254:1254:1254)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (966:966:966) (1001:1001:1001)) - (PORT datab (946:946:946) (986:986:986)) - (PORT datac (632:632:632) (678:678:678)) - (PORT datad (1150:1150:1150) (1195:1195:1195)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) - (DELAY - (ABSOLUTE - (PORT datab (865:865:865) (918:918:918)) - (PORT datac (179:179:179) (213:213:213)) - (PORT datad (851:851:851) (896:896:896)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1052:1052:1052) (1077:1077:1077)) - (PORT datab (1450:1450:1450) (1521:1521:1521)) - (PORT datac (1291:1291:1291) (1321:1321:1321)) - (PORT datad (856:856:856) (875:875:875)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1685:1685:1685) (1750:1750:1750)) - (PORT datab (1695:1695:1695) (1779:1779:1779)) - (PORT datac (1479:1479:1479) (1576:1576:1576)) - (PORT datad (855:855:855) (874:874:874)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (1444:1444:1444) (1505:1505:1505)) - (PORT datab (1695:1695:1695) (1774:1774:1774)) - (PORT datac (1653:1653:1653) (1704:1704:1704)) - (PORT datad (1165:1165:1165) (1208:1208:1208)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) - (DELAY - (ABSOLUTE - (PORT dataa (829:829:829) (902:902:902)) - (PORT datab (612:612:612) (626:626:626)) - (PORT datac (1486:1486:1486) (1525:1525:1525)) - (PORT datad (572:572:572) (587:587:587)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (953:953:953)) - (PORT datab (920:920:920) (939:939:939)) - (PORT datac (888:888:888) (933:933:933)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~94) - (DELAY - (ABSOLUTE - (PORT dataa (1805:1805:1805) (1846:1846:1846)) - (PORT datab (1718:1718:1718) (1824:1824:1824)) - (PORT datac (1560:1560:1560) (1684:1684:1684)) - (PORT datad (1003:1003:1003) (1103:1103:1103)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) - (DELAY - (ABSOLUTE - (PORT dataa (1617:1617:1617) (1736:1736:1736)) - (PORT datac (2516:2516:2516) (2621:2621:2621)) - (PORT datad (1496:1496:1496) (1610:1610:1610)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1204:1204:1204)) - (PORT datab (1153:1153:1153) (1208:1208:1208)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (861:861:861) (880:880:880)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT datab (684:684:684) (709:709:709)) - (PORT datac (378:378:378) (413:413:413)) - (PORT datad (203:203:203) (232:232:232)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) - (DELAY - (ABSOLUTE - (PORT dataa (454:454:454) (494:494:494)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (807:807:807) (827:827:827)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (413:413:413)) - (PORT datab (907:907:907) (914:914:914)) - (PORT datac (619:619:619) (656:656:656)) - (PORT datad (1190:1190:1190) (1243:1243:1243)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1250:1250:1250) (1344:1344:1344)) - (PORT datab (1673:1673:1673) (1790:1790:1790)) - (PORT datac (909:909:909) (958:958:958)) - (PORT datad (940:940:940) (995:995:995)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1458:1458:1458) (1556:1556:1556)) - (PORT datab (1664:1664:1664) (1735:1735:1735)) - (PORT datac (847:847:847) (861:861:861)) - (PORT datad (654:654:654) (683:683:683)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_exx\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1407:1407:1407) (1552:1552:1552)) - (PORT datab (901:901:901) (929:929:929)) - (PORT datad (2354:2354:2354) (2501:2501:2501)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_exx) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1532:1532:1532)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1555:1555:1555)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1165:1165:1165) (1200:1200:1200)) - (PORT datab (1193:1193:1193) (1243:1243:1243)) - (PORT datad (1206:1206:1206) (1288:1288:1288)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de1) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1593:1593:1593) (1569:1569:1569)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (961:961:961)) - (PORT datab (2051:2051:2051) (2083:2083:2083)) - (PORT datac (805:805:805) (817:817:817)) - (PORT datad (336:336:336) (360:360:360)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (965:965:965) (998:998:998)) - (PORT datab (1733:1733:1733) (1770:1770:1770)) - (PORT datac (1229:1229:1229) (1327:1327:1327)) - (PORT datad (1151:1151:1151) (1194:1194:1194)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (766:766:766) (785:785:785)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1230:1230:1230) (1329:1329:1329)) - (PORT datad (1542:1542:1542) (1627:1627:1627)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1235:1235:1235) (1298:1298:1298)) - (PORT datab (1276:1276:1276) (1367:1367:1367)) - (PORT datac (1156:1156:1156) (1195:1195:1195)) - (PORT datad (711:711:711) (777:777:777)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (656:656:656)) - (PORT datab (603:603:603) (615:615:615)) - (PORT datac (902:902:902) (950:950:950)) - (PORT datad (1750:1750:1750) (1806:1806:1806)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (937:937:937) (985:985:985)) - (PORT datab (359:359:359) (388:388:388)) - (PORT datac (1182:1182:1182) (1242:1242:1242)) - (PORT datad (2028:2028:2028) (2153:2153:2153)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (372:372:372)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (878:878:878) (913:913:913)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1069:1069:1069)) - (PORT datab (913:913:913) (1002:1002:1002)) - (PORT datac (1084:1084:1084) (1074:1074:1074)) - (PORT datad (1060:1060:1060) (1062:1062:1062)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1344:1344:1344) (1441:1441:1441)) - (PORT datab (898:898:898) (946:946:946)) - (PORT datac (669:669:669) (692:692:692)) - (PORT datad (1162:1162:1162) (1228:1228:1228)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) - (DELAY - (ABSOLUTE - (PORT dataa (2046:2046:2046) (2143:2143:2143)) - (PORT datac (1652:1652:1652) (1690:1690:1690)) - (PORT datad (1726:1726:1726) (1766:1766:1766)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~2) - (DELAY - (ABSOLUTE - (PORT dataa (985:985:985) (1068:1068:1068)) - (PORT datab (1320:1320:1320) (1358:1358:1358)) - (PORT datac (1320:1320:1320) (1375:1375:1375)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~19) - (DELAY - (ABSOLUTE - (PORT datab (667:667:667) (677:677:677)) - (PORT datac (650:650:650) (674:674:674)) - (PORT datad (899:899:899) (937:937:937)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (691:691:691)) - (PORT datab (711:711:711) (745:745:745)) - (PORT datac (675:675:675) (730:730:730)) - (PORT datad (832:832:832) (843:843:843)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (889:889:889)) - (PORT datac (1915:1915:1915) (1982:1982:1982)) - (PORT datad (200:200:200) (239:239:239)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (677:677:677)) - (PORT datab (864:864:864) (932:932:932)) - (PORT datac (1099:1099:1099) (1123:1123:1123)) - (PORT datad (830:830:830) (852:852:852)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1058:1058:1058) (1166:1166:1166)) - (PORT datab (1000:1000:1000) (1115:1115:1115)) - (PORT datac (1411:1411:1411) (1477:1477:1477)) - (PORT datad (203:203:203) (239:239:239)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1061:1061:1061) (1166:1166:1166)) - (PORT datab (1976:1976:1976) (2065:2065:2065)) - (PORT datac (1151:1151:1151) (1205:1205:1205)) - (PORT datad (941:941:941) (1012:1012:1012)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (2603:2603:2603) (2772:2772:2772)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (1032:1032:1032)) - (PORT datac (1109:1109:1109) (1164:1164:1164)) - (PORT datad (1148:1148:1148) (1191:1191:1191)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) - (DELAY - (ABSOLUTE - (PORT dataa (988:988:988) (1040:1040:1040)) - (PORT datab (845:845:845) (850:850:850)) - (PORT datac (2021:2021:2021) (2050:2050:2050)) - (PORT datad (1388:1388:1388) (1426:1426:1426)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1582:1582:1582) (1703:1703:1703)) - (PORT datab (917:917:917) (971:971:971)) - (PORT datac (929:929:929) (1008:1008:1008)) - (PORT datad (1530:1530:1530) (1630:1630:1630)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (674:674:674)) - (PORT datab (871:871:871) (890:890:890)) - (PORT datac (598:598:598) (661:661:661)) - (PORT datad (809:809:809) (825:825:825)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1239:1239:1239)) - (PORT datac (1383:1383:1383) (1458:1458:1458)) - (PORT datad (2108:2108:2108) (2253:2253:2253)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (896:896:896) (968:968:968)) - (PORT datab (1559:1559:1559) (1655:1655:1655)) - (PORT datac (211:211:211) (252:252:252)) - (PORT datad (618:618:618) (634:634:634)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1375:1375:1375) (1445:1445:1445)) - (PORT datab (619:619:619) (640:640:640)) - (PORT datac (776:776:776) (799:799:799)) - (PORT datad (597:597:597) (614:614:614)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1683:1683:1683) (1739:1739:1739)) - (PORT datab (1115:1115:1115) (1125:1125:1125)) - (PORT datac (1054:1054:1054) (1110:1110:1110)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1324:1324:1324) (1411:1411:1411)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (592:592:592) (627:627:627)) - (PORT datad (1466:1466:1466) (1538:1538:1538)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (576:576:576) (604:604:604)) - (PORT datab (614:614:614) (675:675:675)) - (PORT datac (611:611:611) (636:636:636)) - (PORT datad (573:573:573) (586:586:586)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (2248:2248:2248) (2386:2386:2386)) - (PORT datab (260:260:260) (341:341:341)) - (PORT datac (1161:1161:1161) (1218:1218:1218)) - (PORT datad (235:235:235) (303:303:303)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (874:874:874) (909:909:909)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT datab (208:208:208) (250:250:250)) - (PORT datad (663:663:663) (707:707:707)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (266:266:266)) - (PORT datab (1027:1027:1027) (1068:1068:1068)) - (PORT datac (332:332:332) (358:358:358)) - (PORT datad (688:688:688) (740:740:740)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1247:1247:1247)) - (PORT datac (887:887:887) (944:944:944)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~14) - (DELAY - (ABSOLUTE - (PORT datac (663:663:663) (747:747:747)) - (PORT datad (890:890:890) (915:915:915)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1435:1435:1435) (1516:1516:1516)) - (PORT datab (619:619:619) (646:646:646)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (1126:1126:1126) (1172:1172:1172)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~47) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (640:640:640)) - (PORT datab (648:648:648) (672:672:672)) - (PORT datac (891:891:891) (929:929:929)) - (PORT datad (873:873:873) (908:908:908)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~48) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (385:385:385)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (616:616:616) (658:658:658)) - (PORT datad (1046:1046:1046) (1069:1069:1069)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (2048:2048:2048) (2143:2143:2143)) - (PORT datac (1652:1652:1652) (1688:1688:1688)) - (PORT datad (1726:1726:1726) (1766:1766:1766)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1331:1331:1331) (1424:1424:1424)) - (PORT datab (1098:1098:1098) (1141:1141:1141)) - (PORT datac (923:923:923) (945:945:945)) - (PORT datad (569:569:569) (578:578:578)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (278:278:278)) - (PORT datab (229:229:229) (272:272:272)) - (PORT datac (1186:1186:1186) (1234:1234:1234)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) - (DELAY - (ABSOLUTE - (PORT dataa (816:816:816) (855:855:855)) - (PORT datab (1257:1257:1257) (1326:1326:1326)) - (PORT datac (1798:1798:1798) (1932:1932:1932)) - (PORT datad (2112:2112:2112) (2257:2257:2257)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (632:632:632) (652:652:652)) - (PORT datac (595:595:595) (618:618:618)) - (PORT datad (847:847:847) (860:860:860)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1357:1357:1357) (1484:1484:1484)) - (PORT datab (742:742:742) (806:806:806)) - (PORT datac (873:873:873) (902:902:902)) - (PORT datad (887:887:887) (943:943:943)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (916:916:916)) - (PORT datab (683:683:683) (749:749:749)) - (PORT datac (971:971:971) (1032:1032:1032)) - (PORT datad (1783:1783:1783) (1858:1858:1858)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1298:1298:1298) (1401:1401:1401)) - (PORT datab (881:881:881) (925:925:925)) - (PORT datac (637:637:637) (657:657:657)) - (PORT datad (1737:1737:1737) (1788:1788:1788)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1357:1357:1357) (1486:1486:1486)) - (PORT datab (643:643:643) (709:709:709)) - (PORT datac (874:874:874) (901:901:901)) - (PORT datad (380:380:380) (406:406:406)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (953:953:953)) - (PORT datab (685:685:685) (750:750:750)) - (PORT datac (967:967:967) (1028:1028:1028)) - (PORT datad (629:629:629) (639:639:639)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1456:1456:1456) (1534:1534:1534)) - (PORT datab (926:926:926) (971:971:971)) - (PORT datac (191:191:191) (224:224:224)) - (PORT datad (1396:1396:1396) (1442:1442:1442)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1587:1587:1587) (1654:1654:1654)) - (PORT datab (1578:1578:1578) (1625:1625:1625)) - (PORT datac (1000:1000:1000) (1045:1045:1045)) - (PORT datad (1562:1562:1562) (1620:1620:1620)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1452:1452:1452) (1526:1526:1526)) - (PORT datab (898:898:898) (959:959:959)) - (PORT datac (823:823:823) (876:876:876)) - (PORT datad (584:584:584) (613:613:613)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1449:1449:1449) (1523:1523:1523)) - (PORT datab (899:899:899) (962:962:962)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (914:914:914) (977:977:977)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (613:613:613)) - (PORT datab (864:864:864) (919:919:919)) - (PORT datac (792:792:792) (849:849:849)) - (PORT datad (781:781:781) (835:835:835)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (652:652:652) (665:665:665)) - (PORT datab (238:238:238) (284:284:284)) - (PORT datac (1314:1314:1314) (1404:1404:1404)) - (PORT datad (2218:2218:2218) (2338:2338:2338)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1788:1788:1788) (1938:1938:1938)) - (PORT datab (1645:1645:1645) (1766:1766:1766)) - (PORT datac (1304:1304:1304) (1398:1398:1398)) - (PORT datad (2565:2565:2565) (2702:2702:2702)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1255:1255:1255) (1317:1317:1317)) - (PORT datab (870:870:870) (893:893:893)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (588:588:588) (606:606:606)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1443:1443:1443) (1548:1548:1548)) - (PORT datab (263:263:263) (309:309:309)) - (PORT datac (1197:1197:1197) (1255:1255:1255)) - (PORT datad (842:842:842) (854:854:854)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~2) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (910:910:910)) - (PORT datab (891:891:891) (912:912:912)) - (PORT datac (859:859:859) (877:877:877)) - (PORT datad (902:902:902) (978:978:978)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (921:921:921)) - (PORT datab (937:937:937) (1012:1012:1012)) - (PORT datac (195:195:195) (239:239:239)) - (PORT datad (1152:1152:1152) (1199:1199:1199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1470:1470:1470) (1476:1476:1476)) - (PORT datab (1497:1497:1497) (1569:1569:1569)) - (PORT datac (1102:1102:1102) (1120:1120:1120)) - (PORT datad (400:400:400) (436:436:436)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (854:854:854) (906:906:906)) - (PORT datab (893:893:893) (913:913:913)) - (PORT datac (861:861:861) (879:879:879)) - (PORT datad (904:904:904) (979:979:979)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (805:805:805)) - (PORT datab (775:775:775) (880:880:880)) - (PORT datad (1178:1178:1178) (1197:1197:1197)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (619:619:619)) - (PORT datab (1166:1166:1166) (1207:1207:1207)) - (PORT datac (854:854:854) (905:905:905)) - (PORT datad (902:902:902) (956:956:956)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1440:1440:1440) (1550:1550:1550)) - (PORT datab (866:866:866) (895:895:895)) - (PORT datac (1284:1284:1284) (1336:1336:1336)) - (PORT datad (1607:1607:1607) (1729:1729:1729)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1494:1494:1494) (1601:1601:1601)) - (PORT datab (1439:1439:1439) (1451:1451:1451)) - (PORT datac (1444:1444:1444) (1551:1551:1551)) - (PORT datad (402:402:402) (439:439:439)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1017:1017:1017) (1057:1057:1057)) - (PORT datac (793:793:793) (802:802:802)) - (PORT datad (1022:1022:1022) (1048:1048:1048)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (397:397:397) (440:440:440)) - (PORT datac (980:980:980) (992:992:992)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (373:373:373)) - (PORT datab (198:198:198) (235:235:235)) - (PORT datac (586:586:586) (613:613:613)) - (PORT datad (1522:1522:1522) (1622:1622:1622)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1222:1222:1222) (1272:1272:1272)) - (PORT datab (1222:1222:1222) (1263:1263:1263)) - (PORT datac (892:892:892) (922:922:922)) - (PORT datad (1507:1507:1507) (1624:1624:1624)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (886:886:886)) - (PORT datab (227:227:227) (274:274:274)) - (PORT datac (1160:1160:1160) (1222:1222:1222)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1685:1685:1685) (1744:1744:1744)) - (PORT datab (1695:1695:1695) (1779:1779:1779)) - (PORT datac (1482:1482:1482) (1577:1577:1577)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (934:934:934) (1034:1034:1034)) - (PORT datab (206:206:206) (246:246:246)) - (PORT datac (1192:1192:1192) (1254:1254:1254)) - (PORT datad (882:882:882) (917:917:917)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) - (DELAY - (ABSOLUTE - (PORT datab (1193:1193:1193) (1230:1230:1230)) - (PORT datac (1251:1251:1251) (1308:1308:1308)) - (PORT datad (780:780:780) (799:799:799)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) - (DELAY - (ABSOLUTE - (PORT dataa (896:896:896) (976:976:976)) - (PORT datab (940:940:940) (1022:1022:1022)) - (PORT datac (1140:1140:1140) (1178:1178:1178)) - (PORT datad (375:375:375) (417:417:417)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1284:1284:1284) (1345:1345:1345)) - (PORT datab (1189:1189:1189) (1228:1228:1228)) - (PORT datac (1135:1135:1135) (1177:1177:1177)) - (PORT datad (780:780:780) (799:799:799)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (343:343:343)) - (PORT datab (224:224:224) (272:272:272)) - (PORT datac (342:342:342) (371:371:371)) - (PORT datad (1219:1219:1219) (1301:1301:1301)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1167:1167:1167) (1203:1203:1203)) - (PORT datab (1191:1191:1191) (1242:1242:1242)) - (PORT datad (1220:1220:1220) (1299:1299:1299)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de2) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1593:1593:1593) (1569:1569:1569)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (405:405:405)) - (PORT datab (224:224:224) (269:269:269)) - (PORT datac (222:222:222) (302:302:302)) - (PORT datad (1202:1202:1202) (1285:1285:1285)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (568:568:568) (586:586:586)) - (PORT datab (1028:1028:1028) (1073:1073:1073)) - (PORT datac (338:338:338) (364:364:364)) - (PORT datad (686:686:686) (739:739:739)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (687:687:687)) - (PORT datab (1720:1720:1720) (1802:1802:1802)) - (PORT datad (879:879:879) (876:876:876)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (2640:2640:2640) (2740:2740:2740)) - (PORT datab (1718:1718:1718) (1823:1823:1823)) - (PORT datac (1017:1017:1017) (1049:1049:1049)) - (PORT datad (1534:1534:1534) (1564:1564:1564)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (277:277:277)) - (PORT datab (894:894:894) (923:923:923)) - (PORT datac (1486:1486:1486) (1564:1564:1564)) - (PORT datad (1217:1217:1217) (1256:1256:1256)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) - (DELAY - (ABSOLUTE - (PORT dataa (985:985:985) (1038:1038:1038)) - (PORT datab (204:204:204) (246:246:246)) - (PORT datac (946:946:946) (1014:1014:1014)) - (PORT datad (209:209:209) (240:240:240)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla30npla13M5T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (1011:1011:1011)) - (PORT datab (229:229:229) (278:278:278)) - (PORT datac (1408:1408:1408) (1479:1479:1479)) - (PORT datad (1499:1499:1499) (1550:1550:1550)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1150:1150:1150) (1181:1181:1181)) - (PORT datab (1549:1549:1549) (1573:1573:1573)) - (PORT datac (592:592:592) (626:626:626)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (391:391:391)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (178:178:178) (207:207:207)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (910:910:910) (934:934:934)) - (PORT datab (654:654:654) (689:689:689)) - (PORT datac (1104:1104:1104) (1117:1117:1117)) - (PORT datad (766:766:766) (786:786:786)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1624:1624:1624) (1711:1711:1711)) - (PORT datab (1531:1531:1531) (1582:1582:1582)) - (PORT datac (1704:1704:1704) (1824:1824:1824)) - (PORT datad (1073:1073:1073) (1075:1075:1075)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (2002:2002:2002) (2195:2195:2195)) - (PORT datab (1455:1455:1455) (1549:1549:1549)) - (PORT datac (1508:1508:1508) (1592:1592:1592)) - (PORT datad (1918:1918:1918) (1978:1978:1978)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (965:965:965)) - (PORT datab (871:871:871) (909:909:909)) - (PORT datac (803:803:803) (870:870:870)) - (PORT datad (1526:1526:1526) (1620:1620:1620)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (664:664:664)) - (PORT datab (678:678:678) (735:735:735)) - (PORT datac (919:919:919) (966:966:966)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (728:728:728)) - (PORT datab (1191:1191:1191) (1244:1244:1244)) - (PORT datac (669:669:669) (694:694:694)) - (PORT datad (1304:1304:1304) (1397:1397:1397)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1369:1369:1369) (1431:1431:1431)) - (PORT datab (643:643:643) (680:680:680)) - (PORT datac (1322:1322:1322) (1362:1362:1362)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1105:1105:1105) (1190:1190:1190)) - (PORT datab (1820:1820:1820) (1897:1897:1897)) - (PORT datad (966:966:966) (1074:1074:1074)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (932:932:932)) - (PORT datab (680:680:680) (741:741:741)) - (PORT datac (202:202:202) (239:239:239)) - (PORT datad (2206:2206:2206) (2251:2251:2251)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1252:1252:1252) (1348:1348:1348)) - (PORT datab (1492:1492:1492) (1598:1598:1598)) - (PORT datac (1226:1226:1226) (1277:1277:1277)) - (PORT datad (1231:1231:1231) (1263:1263:1263)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1906:1906:1906) (2000:2000:2000)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (869:869:869) (926:926:926)) - (PORT datad (188:188:188) (220:220:220)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (635:635:635)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (898:898:898) (931:931:931)) - (PORT datad (816:816:816) (860:860:860)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (810:810:810) (881:881:881)) - (PORT datab (206:206:206) (246:246:246)) - (PORT datac (561:561:561) (575:575:575)) - (PORT datad (613:613:613) (668:668:668)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (889:889:889)) - (PORT datac (208:208:208) (251:251:251)) - (PORT datad (202:202:202) (238:238:238)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1311:1311:1311) (1368:1368:1368)) - (PORT datab (614:614:614) (640:640:640)) - (PORT datac (842:842:842) (872:872:872)) - (PORT datad (607:607:607) (635:635:635)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1417:1417:1417) (1464:1464:1464)) - (PORT datab (910:910:910) (954:954:954)) - (PORT datac (1136:1136:1136) (1177:1177:1177)) - (PORT datad (1173:1173:1173) (1255:1255:1255)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1757:1757:1757) (1831:1831:1831)) - (PORT datab (836:836:836) (849:849:849)) - (PORT datac (2018:2018:2018) (2050:2050:2050)) - (PORT datad (2040:2040:2040) (2102:2102:2102)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~40) - (DELAY - (ABSOLUTE - (PORT dataa (927:927:927) (961:961:961)) - (PORT datab (1098:1098:1098) (1150:1150:1150)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (535:535:535) (566:566:566)) - (PORT datab (662:662:662) (694:694:694)) - (PORT datac (2000:2000:2000) (2031:2031:2031)) - (PORT datad (538:538:538) (549:549:549)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (852:852:852) (924:924:924)) - (PORT datac (179:179:179) (214:214:214)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (855:855:855) (863:863:863)) - (PORT datac (568:568:568) (591:591:591)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~93) - (DELAY - (ABSOLUTE - (PORT dataa (1191:1191:1191) (1227:1227:1227)) - (PORT datab (1050:1050:1050) (1057:1057:1057)) - (PORT datac (1185:1185:1185) (1207:1207:1207)) - (PORT datad (1343:1343:1343) (1388:1388:1388)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) - (DELAY - (ABSOLUTE - (PORT dataa (249:249:249) (338:338:338)) - (PORT datab (223:223:223) (268:268:268)) - (PORT datac (337:337:337) (367:367:367)) - (PORT datad (1203:1203:1203) (1285:1285:1285)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) - (DELAY - (ABSOLUTE - (PORT datab (1384:1384:1384) (1432:1432:1432)) - (PORT datac (1179:1179:1179) (1200:1200:1200)) - (PORT datad (594:594:594) (610:610:610)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) - (DELAY - (ABSOLUTE - (PORT datac (900:900:900) (943:943:943)) - (PORT datad (1328:1328:1328) (1383:1383:1383)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1165:1165:1165) (1261:1261:1261)) - (PORT datab (223:223:223) (270:270:270)) - (PORT datac (1141:1141:1141) (1178:1178:1178)) - (PORT datad (671:671:671) (721:721:721)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) - (DELAY - (ABSOLUTE - (PORT dataa (704:704:704) (769:769:769)) - (PORT datab (1469:1469:1469) (1552:1552:1552)) - (PORT datac (1145:1145:1145) (1180:1180:1180)) - (PORT datad (199:199:199) (235:235:235)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (766:766:766)) - (PORT datab (1471:1471:1471) (1557:1557:1557)) - (PORT datac (1138:1138:1138) (1176:1176:1176)) - (PORT datad (196:196:196) (232:232:232)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1346:1346:1346) (1411:1411:1411)) - (PORT datab (869:869:869) (903:903:903)) - (PORT datac (1807:1807:1807) (1896:1896:1896)) - (PORT datad (1570:1570:1570) (1608:1608:1608)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datad (868:868:868) (885:885:885)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) - (DELAY - (ABSOLUTE - (PORT dataa (981:981:981) (1092:1092:1092)) - (PORT datab (657:657:657) (681:681:681)) - (PORT datac (908:908:908) (975:975:975)) - (PORT datad (1438:1438:1438) (1536:1536:1536)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (1101:1101:1101) (1154:1154:1154)) - (PORT datab (701:701:701) (782:782:782)) - (PORT datac (1444:1444:1444) (1551:1551:1551)) - (PORT datad (1465:1465:1465) (1554:1554:1554)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (634:634:634)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (622:622:622) (651:651:651)) - (PORT datad (1082:1082:1082) (1107:1107:1107)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (419:419:419)) - (PORT datab (1179:1179:1179) (1229:1229:1229)) - (PORT datac (351:351:351) (380:380:380)) - (PORT datad (1087:1087:1087) (1108:1108:1108)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1246:1246:1246) (1335:1335:1335)) - (PORT datab (1577:1577:1577) (1714:1714:1714)) - (PORT datac (2188:2188:2188) (2312:2312:2312)) - (PORT datad (1069:1069:1069) (1164:1164:1164)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) - (DELAY - (ABSOLUTE - (PORT dataa (942:942:942) (1012:1012:1012)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1253:1253:1253) (1293:1293:1293)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (660:660:660)) - (PORT datac (659:659:659) (688:688:688)) - (PORT datad (550:550:550) (559:559:559)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1144:1144:1144) (1180:1180:1180)) - (PORT datab (218:218:218) (265:265:265)) - (PORT datac (1135:1135:1135) (1168:1168:1168)) - (PORT datad (665:665:665) (712:712:712)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~2) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (938:938:938)) - (PORT datab (900:900:900) (913:913:913)) - (PORT datac (920:920:920) (1008:1008:1008)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (700:700:700) (751:751:751)) - (PORT datab (1166:1166:1166) (1198:1198:1198)) - (PORT datad (948:948:948) (968:968:968)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_af) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1142:1142:1142) (1184:1184:1184)) - (PORT datab (248:248:248) (332:332:332)) - (PORT datac (1144:1144:1144) (1179:1179:1179)) - (PORT datad (672:672:672) (720:720:720)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (703:703:703)) - (PORT datab (1351:1351:1351) (1386:1386:1386)) - (PORT datad (908:908:908) (958:958:958)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1142:1142:1142) (1183:1183:1183)) - (PORT datab (250:250:250) (335:335:335)) - (PORT datac (1137:1137:1137) (1173:1173:1173)) - (PORT datad (664:664:664) (718:718:718)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) - (DELAY - (ABSOLUTE - (PORT dataa (1721:1721:1721) (1780:1780:1780)) - (PORT datab (1170:1170:1170) (1223:1223:1223)) - (PORT datad (792:792:792) (797:797:797)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) - (DELAY - (ABSOLUTE - (PORT dataa (709:709:709) (761:761:761)) - (PORT datab (914:914:914) (975:975:975)) - (PORT datac (1817:1817:1817) (1896:1896:1896)) - (PORT datad (1153:1153:1153) (1178:1178:1178)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1482:1482:1482) (1581:1581:1581)) - (PORT datac (1016:1016:1016) (1055:1055:1055)) - (PORT datad (321:321:321) (344:344:344)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1428:1428:1428) (1487:1487:1487)) - (PORT datab (1168:1168:1168) (1215:1215:1215)) - (PORT datac (2035:2035:2035) (2124:2124:2124)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1158:1158:1158) (1200:1200:1200)) - (PORT datab (2031:2031:2031) (2127:2127:2127)) - (PORT datac (969:969:969) (1020:1020:1020)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (826:826:826) (902:902:902)) - (PORT datab (1517:1517:1517) (1560:1560:1560)) - (PORT datac (1294:1294:1294) (1324:1324:1324)) - (PORT datad (862:862:862) (880:880:880)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) - (DELAY - (ABSOLUTE - (PORT datab (229:229:229) (272:272:272)) - (PORT datac (202:202:202) (239:239:239)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (1544:1544:1544) (1653:1653:1653)) - (PORT datac (208:208:208) (246:246:246)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (620:620:620)) - (PORT datab (876:876:876) (893:893:893)) - (PORT datac (1384:1384:1384) (1444:1444:1444)) - (PORT datad (1947:1947:1947) (1977:1977:1977)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (266:266:266)) - (PORT datab (2017:2017:2017) (2075:2075:2075)) - (PORT datac (804:804:804) (827:827:827)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (740:740:740)) - (PORT datab (1445:1445:1445) (1514:1514:1514)) - (PORT datac (360:360:360) (389:389:389)) - (PORT datad (1121:1121:1121) (1177:1177:1177)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (277:277:277)) - (PORT datab (558:558:558) (578:578:578)) - (PORT datac (804:804:804) (818:818:818)) - (PORT datad (595:595:595) (633:633:633)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1170:1170:1170) (1229:1229:1229)) - (PORT datab (599:599:599) (614:614:614)) - (PORT datac (654:654:654) (698:698:698)) - (PORT datad (866:866:866) (893:893:893)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) - (DELAY - (ABSOLUTE - (PORT dataa (692:692:692) (737:737:737)) - (PORT datab (1195:1195:1195) (1210:1210:1210)) - (PORT datac (1157:1157:1157) (1193:1193:1193)) - (PORT datad (590:590:590) (602:602:602)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (936:936:936)) - (PORT datab (1199:1199:1199) (1253:1253:1253)) - (PORT datac (889:889:889) (931:931:931)) - (PORT datad (630:630:630) (687:687:687)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (601:601:601)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (951:951:951)) - (PORT datab (1199:1199:1199) (1252:1252:1252)) - (PORT datac (361:361:361) (394:394:394)) - (PORT datad (1118:1118:1118) (1176:1176:1176)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1169:1169:1169) (1230:1230:1230)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1158:1158:1158) (1196:1196:1196)) - (PORT datad (863:863:863) (892:892:892)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (252:252:252)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (652:652:652) (697:697:697)) - (PORT datad (845:845:845) (894:894:894)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (637:637:637)) - (PORT datab (686:686:686) (707:707:707)) - (PORT datac (378:378:378) (410:410:410)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (607:607:607) (625:625:625)) - (PORT datac (530:530:530) (542:542:542)) - (PORT datad (838:838:838) (876:876:876)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (962:962:962)) - (PORT datab (1558:1558:1558) (1661:1661:1661)) - (PORT datac (1407:1407:1407) (1474:1474:1474)) - (PORT datad (200:200:200) (235:235:235)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (660:660:660)) - (PORT datab (965:965:965) (1060:1060:1060)) - (PORT datac (1732:1732:1732) (1835:1835:1835)) - (PORT datad (1150:1150:1150) (1179:1179:1179)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1102:1102:1102) (1150:1150:1150)) - (PORT datab (1473:1473:1473) (1583:1583:1583)) - (PORT datac (1614:1614:1614) (1681:1681:1681)) - (PORT datad (1173:1173:1173) (1219:1219:1219)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1405:1405:1405) (1418:1418:1418)) - (PORT datab (1241:1241:1241) (1276:1276:1276)) - (PORT datac (1251:1251:1251) (1275:1275:1275)) - (PORT datad (1260:1260:1260) (1298:1298:1298)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1121:1121:1121) (1151:1151:1151)) - (PORT datac (613:613:613) (636:636:636)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~28) - (DELAY - (ABSOLUTE - (PORT dataa (236:236:236) (284:284:284)) - (PORT datab (219:219:219) (256:256:256)) - (PORT datac (1148:1148:1148) (1190:1190:1190)) - (PORT datad (194:194:194) (218:218:218)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~35) - (DELAY - (ABSOLUTE - (PORT datab (2004:2004:2004) (2134:2134:2134)) - (PORT datac (1351:1351:1351) (1365:1365:1365)) - (PORT datad (859:859:859) (872:872:872)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~36) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (267:267:267)) - (PORT datab (910:910:910) (941:941:941)) - (PORT datac (621:621:621) (645:645:645)) - (PORT datad (924:924:924) (962:962:962)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1513:1513:1513) (1596:1596:1596)) - (PORT datab (1166:1166:1166) (1202:1202:1202)) - (PORT datac (1104:1104:1104) (1142:1142:1142)) - (PORT datad (548:548:548) (560:560:560)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (650:650:650)) - (PORT datab (234:234:234) (278:278:278)) - (PORT datac (1132:1132:1132) (1164:1164:1164)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1646:1646:1646) (1763:1763:1763)) - (PORT datab (1008:1008:1008) (1101:1101:1101)) - (PORT datac (1033:1033:1033) (1107:1107:1107)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1208:1208:1208)) - (PORT datab (1537:1537:1537) (1621:1621:1621)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (923:923:923)) - (PORT datab (570:570:570) (590:590:590)) - (PORT datac (603:603:603) (628:628:628)) - (PORT datad (595:595:595) (619:619:619)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1229:1229:1229) (1305:1305:1305)) - (PORT datab (1275:1275:1275) (1372:1372:1372)) - (PORT datac (1155:1155:1155) (1192:1192:1192)) - (PORT datad (709:709:709) (772:772:772)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (690:690:690) (719:719:719)) - (PORT datab (1344:1344:1344) (1367:1367:1367)) - (PORT datac (1222:1222:1222) (1269:1269:1269)) - (PORT datad (1654:1654:1654) (1748:1748:1748)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1005:1005:1005) (1089:1089:1089)) - (PORT datab (887:887:887) (923:923:923)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (221:221:221) (249:249:249)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1035:1035:1035) (1133:1133:1133)) - (PORT datac (2185:2185:2185) (2272:2272:2272)) - (PORT datad (654:654:654) (711:711:711)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (718:718:718) (782:782:782)) - (PORT datab (1135:1135:1135) (1159:1159:1159)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1153:1153:1153) (1186:1186:1186)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1016:1016:1016) (1112:1112:1112)) - (PORT datab (668:668:668) (685:685:685)) - (PORT datac (1012:1012:1012) (1113:1113:1113)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (933:933:933) (975:975:975)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) - (DELAY - (ABSOLUTE - (PORT datab (278:278:278) (366:366:366)) - (PORT datac (241:241:241) (319:319:319)) - (PORT datad (246:246:246) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (971:971:971)) - (PORT datab (218:218:218) (257:257:257)) - (PORT datac (1095:1095:1095) (1116:1116:1116)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1104:1104:1104) (1192:1192:1192)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (650:650:650) (716:716:716)) - (PORT datad (966:966:966) (1077:1077:1077)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (2563:2563:2563) (2705:2705:2705)) - (PORT datab (1595:1595:1595) (1711:1711:1711)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (218:218:218) (258:258:258)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1067:1067:1067) (1148:1148:1148)) - (PORT datab (204:204:204) (245:245:245)) - (PORT datac (880:880:880) (911:911:911)) - (PORT datad (824:824:824) (834:834:834)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) - (DELAY - (ABSOLUTE - (PORT datab (931:931:931) (1002:1002:1002)) - (PORT datad (625:625:625) (662:662:662)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (663:663:663)) - (PORT datab (924:924:924) (986:986:986)) - (PORT datac (1079:1079:1079) (1113:1113:1113)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~4) - (DELAY - (ABSOLUTE - (PORT dataa (882:882:882) (951:951:951)) - (PORT datab (902:902:902) (933:933:933)) - (PORT datac (628:628:628) (672:672:672)) - (PORT datad (883:883:883) (909:909:909)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (1992:1992:1992) (2133:2133:2133)) - (PORT datab (907:907:907) (958:958:958)) - (PORT datac (224:224:224) (265:265:265)) - (PORT datad (1139:1139:1139) (1178:1178:1178)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~5) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (951:951:951)) - (PORT datab (917:917:917) (970:970:970)) - (PORT datac (879:879:879) (911:911:911)) - (PORT datad (593:593:593) (627:627:627)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (926:926:926)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1074:1074:1074) (1121:1121:1121)) - (PORT datab (894:894:894) (950:950:950)) - (PORT datac (601:601:601) (665:665:665)) - (PORT datad (855:855:855) (908:908:908)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~16) - (DELAY - (ABSOLUTE - (PORT dataa (2419:2419:2419) (2569:2569:2569)) - (PORT datab (1823:1823:1823) (1925:1925:1925)) - (PORT datac (1074:1074:1074) (1067:1067:1067)) - (PORT datad (1576:1576:1576) (1735:1735:1735)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) - (DELAY - (ABSOLUTE - (PORT dataa (827:827:827) (849:849:849)) - (PORT datab (912:912:912) (944:944:944)) - (PORT datac (835:835:835) (868:868:868)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (2421:2421:2421) (2571:2571:2571)) - (PORT datab (2408:2408:2408) (2540:2540:2540)) - (PORT datac (1413:1413:1413) (1473:1473:1473)) - (PORT datad (1573:1573:1573) (1734:1734:1734)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (229:229:229) (272:272:272)) - (PORT datac (202:202:202) (241:241:241)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1252:1252:1252) (1310:1310:1310)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (832:832:832) (831:831:831)) - (PORT datad (872:872:872) (917:917:917)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (882:882:882) (898:898:898)) - (PORT datab (237:237:237) (281:281:281)) - (PORT datac (619:619:619) (671:671:671)) - (PORT datad (1350:1350:1350) (1391:1391:1391)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1228:1228:1228) (1318:1318:1318)) - (PORT datab (1384:1384:1384) (1497:1497:1497)) - (PORT datac (857:857:857) (917:917:917)) - (PORT datad (831:831:831) (860:860:860)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2065:2065:2065) (2136:2136:2136)) - (PORT datab (2504:2504:2504) (2706:2706:2706)) - (PORT datac (2886:2886:2886) (3058:3058:3058)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (845:845:845) (894:894:894)) - (PORT datac (990:990:990) (1030:1030:1030)) - (PORT datad (1379:1379:1379) (1425:1425:1425)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (268:268:268)) - (PORT datac (663:663:663) (700:700:700)) - (PORT datad (1031:1031:1031) (1094:1094:1094)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1328:1328:1328) (1447:1447:1447)) - (PORT datac (1179:1179:1179) (1239:1239:1239)) - (PORT datad (2024:2024:2024) (2146:2146:2146)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1166:1166:1166)) - (PORT datab (226:226:226) (266:266:266)) - (PORT datac (604:604:604) (622:622:622)) - (PORT datad (1151:1151:1151) (1191:1191:1191)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1230:1230:1230)) - (PORT datac (1131:1131:1131) (1168:1168:1168)) - (PORT datad (957:957:957) (1017:1017:1017)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) - (DELAY - (ABSOLUTE - (PORT datab (2109:2109:2109) (2224:2224:2224)) - (PORT datac (925:925:925) (983:983:983)) - (PORT datad (1982:1982:1982) (2072:2072:2072)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1189:1189:1189) (1250:1250:1250)) - (PORT datab (599:599:599) (617:617:617)) - (PORT datac (871:871:871) (913:913:913)) - (PORT datad (1143:1143:1143) (1193:1193:1193)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1120:1120:1120) (1154:1154:1154)) - (PORT datab (595:595:595) (609:609:609)) - (PORT datac (1115:1115:1115) (1174:1174:1174)) - (PORT datad (878:878:878) (910:910:910)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1801:1801:1801) (1843:1843:1843)) - (PORT datab (1573:1573:1573) (1608:1608:1608)) - (PORT datad (985:985:985) (1020:1020:1020)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (957:957:957)) - (PORT datab (1162:1162:1162) (1232:1232:1232)) - (PORT datac (1480:1480:1480) (1554:1554:1554)) - (PORT datad (1102:1102:1102) (1119:1119:1119)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (702:702:702) (740:740:740)) - (PORT datab (913:913:913) (942:942:942)) - (PORT datac (618:618:618) (642:642:642)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (1512:1512:1512) (1540:1540:1540)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (926:926:926) (959:959:959)) - (PORT datab (887:887:887) (953:953:953)) - (PORT datac (185:185:185) (226:226:226)) - (PORT datad (885:885:885) (902:902:902)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (1725:1725:1725) (1783:1783:1783)) - (PORT datad (330:330:330) (351:351:351)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1198:1198:1198) (1240:1240:1240)) - (PORT datab (835:835:835) (861:861:861)) - (PORT datac (841:841:841) (865:865:865)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1551:1551:1551) (1610:1610:1610)) - (PORT datab (1763:1763:1763) (1826:1826:1826)) - (PORT datac (2606:2606:2606) (2704:2704:2704)) - (PORT datad (1157:1157:1157) (1177:1177:1177)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (2641:2641:2641) (2744:2744:2744)) - (PORT datab (1587:1587:1587) (1722:1722:1722)) - (PORT datac (639:639:639) (659:659:659)) - (PORT datad (202:202:202) (233:233:233)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (638:638:638)) - (PORT datab (653:653:653) (683:683:683)) - (PORT datac (637:637:637) (684:684:684)) - (PORT datad (847:847:847) (906:906:906)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) - (DELAY - (ABSOLUTE - (PORT datab (707:707:707) (739:739:739)) - (PORT datac (1055:1055:1055) (1068:1068:1068)) - (PORT datad (921:921:921) (956:956:956)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (401:401:401)) - (PORT datab (1114:1114:1114) (1146:1146:1146)) - (PORT datac (1038:1038:1038) (1080:1080:1080)) - (PORT datad (853:853:853) (854:854:854)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1748:1748:1748) (1768:1768:1768)) - (PORT datab (881:881:881) (907:907:907)) - (PORT datac (1501:1501:1501) (1630:1630:1630)) - (PORT datad (1129:1129:1129) (1199:1199:1199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1137:1137:1137) (1170:1170:1170)) - (PORT datab (1651:1651:1651) (1721:1721:1721)) - (PORT datac (1148:1148:1148) (1186:1186:1186)) - (PORT datad (212:212:212) (247:247:247)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (671:671:671) (702:702:702)) - (PORT datab (1148:1148:1148) (1207:1207:1207)) - (PORT datac (1182:1182:1182) (1237:1237:1237)) - (PORT datad (969:969:969) (1043:1043:1043)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~1) - (DELAY - (ABSOLUTE - (PORT dataa (294:294:294) (365:365:365)) - (PORT datac (1702:1702:1702) (1757:1757:1757)) - (PORT datad (437:437:437) (482:482:482)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (685:685:685)) - (PORT datab (1154:1154:1154) (1208:1208:1208)) - (PORT datac (1484:1484:1484) (1544:1544:1544)) - (PORT datad (1270:1270:1270) (1331:1331:1331)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1443:1443:1443) (1501:1501:1501)) - (PORT datab (912:912:912) (961:961:961)) - (PORT datac (896:896:896) (925:925:925)) - (PORT datad (962:962:962) (988:988:988)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) - (DELAY - (ABSOLUTE - (PORT dataa (874:874:874) (897:897:897)) - (PORT datac (992:992:992) (1045:1045:1045)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1066:1066:1066) (1139:1139:1139)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1089:1089:1089) (1116:1116:1116)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (374:374:374)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (345:345:345) (385:385:385)) - (PORT datad (858:858:858) (866:866:866)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1408:1408:1408) (1444:1444:1444)) - (PORT datab (814:814:814) (844:844:844)) - (PORT datac (1711:1711:1711) (1730:1730:1730)) - (PORT datad (911:911:911) (949:949:949)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) - (DELAY - (ABSOLUTE - (PORT dataa (1097:1097:1097) (1124:1124:1124)) - (PORT datab (662:662:662) (693:693:693)) - (PORT datac (868:868:868) (892:892:892)) - (PORT datad (871:871:871) (914:914:914)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (275:275:275)) - (PORT datab (642:642:642) (663:663:663)) - (PORT datac (1367:1367:1367) (1431:1431:1431)) - (PORT datad (1132:1132:1132) (1158:1158:1158)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1647:1647:1647) (1764:1764:1764)) - (PORT datab (1009:1009:1009) (1098:1098:1098)) - (PORT datac (1939:1939:1939) (1965:1965:1965)) - (PORT datad (1664:1664:1664) (1726:1726:1726)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (264:264:264)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (646:646:646) (703:703:703)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (275:275:275)) - (PORT datab (645:645:645) (669:669:669)) - (PORT datac (199:199:199) (236:236:236)) - (PORT datad (1191:1191:1191) (1215:1215:1215)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (1028:1028:1028) (1084:1084:1084)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (593:593:593) (617:617:617)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) - (DELAY - (ABSOLUTE - (PORT dataa (896:896:896) (960:960:960)) - (PORT datab (1128:1128:1128) (1156:1156:1156)) - (PORT datac (886:886:886) (918:918:918)) - (PORT datad (1142:1142:1142) (1198:1198:1198)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) - (DELAY - (ABSOLUTE - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (593:593:593) (653:653:653)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) - (DELAY - (ABSOLUTE - (PORT dataa (214:214:214) (264:264:264)) - (PORT datac (557:557:557) (571:571:571)) - (PORT datad (812:812:812) (882:882:882)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1301:1301:1301) (1363:1363:1363)) - (PORT datab (670:670:670) (695:695:695)) - (PORT datac (195:195:195) (228:228:228)) - (PORT datad (1179:1179:1179) (1216:1216:1216)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) - (DELAY - (ABSOLUTE - (PORT dataa (565:565:565) (585:585:585)) - (PORT datac (793:793:793) (849:849:849)) - (PORT datad (781:781:781) (835:835:835)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (914:914:914) (932:932:932)) - (PORT datab (670:670:670) (713:713:713)) - (PORT datac (371:371:371) (406:406:406)) - (PORT datad (595:595:595) (643:643:643)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~45) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (677:677:677)) - (PORT datab (867:867:867) (880:880:880)) - (PORT datac (866:866:866) (892:892:892)) - (PORT datad (646:646:646) (680:680:680)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~46) - (DELAY - (ABSOLUTE - (PORT datab (821:821:821) (842:842:842)) - (PORT datac (201:201:201) (237:237:237)) - (PORT datad (1425:1425:1425) (1509:1509:1509)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) - (DELAY - (ABSOLUTE - (PORT dataa (599:599:599) (610:610:610)) - (PORT datab (926:926:926) (956:956:956)) - (PORT datac (586:586:586) (596:596:596)) - (PORT datad (582:582:582) (613:613:613)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1011:1011:1011)) - (PORT datab (1561:1561:1561) (1659:1659:1659)) - (PORT datac (842:842:842) (876:876:876)) - (PORT datad (371:371:371) (400:400:400)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (251:251:251)) - (PORT datab (340:340:340) (371:371:371)) - (PORT datac (211:211:211) (252:252:252)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~4) - (DELAY - (ABSOLUTE - (PORT dataa (926:926:926) (963:963:963)) - (PORT datac (857:857:857) (921:921:921)) - (PORT datad (828:828:828) (859:859:859)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (681:681:681)) - (PORT datab (1486:1486:1486) (1550:1550:1550)) - (PORT datac (820:820:820) (856:856:856)) - (PORT datad (815:815:815) (871:871:871)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) - (DELAY - (ABSOLUTE - (PORT dataa (446:446:446) (504:504:504)) - (PORT datab (946:946:946) (986:986:986)) - (PORT datac (374:374:374) (405:405:405)) - (PORT datad (1915:1915:1915) (2040:2040:2040)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~20) - (DELAY - (ABSOLUTE - (PORT dataa (2472:2472:2472) (2661:2661:2661)) - (PORT datab (554:554:554) (575:575:575)) - (PORT datac (892:892:892) (956:956:956)) - (PORT datad (1125:1125:1125) (1142:1142:1142)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (677:677:677)) - (PORT datab (581:581:581) (596:596:596)) - (PORT datac (785:785:785) (834:834:834)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (619:619:619)) - (PORT datab (876:876:876) (893:893:893)) - (PORT datac (1988:1988:1988) (2046:2046:2046)) - (PORT datad (596:596:596) (620:620:620)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1153:1153:1153) (1167:1167:1167)) - (PORT datab (1567:1567:1567) (1688:1688:1688)) - (PORT datac (635:635:635) (692:692:692)) - (PORT datad (604:604:604) (642:642:642)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (914:914:914)) - (PORT datab (562:562:562) (571:571:571)) - (PORT datac (611:611:611) (649:649:649)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (663:663:663)) - (PORT datab (925:925:925) (986:986:986)) - (PORT datac (532:532:532) (538:538:538)) - (PORT datad (873:873:873) (880:880:880)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (276:276:276)) - (PORT datab (643:643:643) (675:675:675)) - (PORT datac (842:842:842) (864:864:864)) - (PORT datad (344:344:344) (366:366:366)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) - (DELAY - (ABSOLUTE - (PORT datab (1438:1438:1438) (1508:1508:1508)) - (PORT datac (915:915:915) (945:945:945)) - (PORT datad (819:819:819) (835:835:835)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (275:275:275)) - (PORT datab (1330:1330:1330) (1334:1334:1334)) - (PORT datac (1375:1375:1375) (1393:1393:1393)) - (PORT datad (312:312:312) (330:330:330)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) - (DELAY - (ABSOLUTE - (PORT datab (949:949:949) (999:999:999)) - (PORT datac (1439:1439:1439) (1498:1498:1498)) - (PORT datad (671:671:671) (702:702:702)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (974:974:974) (1028:1028:1028)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1880:1880:1880) (1905:1905:1905)) - (PORT datab (702:702:702) (730:730:730)) - (PORT datad (1198:1198:1198) (1238:1238:1238)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) - (DELAY - (ABSOLUTE - (PORT datab (709:709:709) (737:737:737)) - (PORT datac (1057:1057:1057) (1070:1070:1070)) - (PORT datad (923:923:923) (954:954:954)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (738:738:738) (772:772:772)) - (PORT datac (609:609:609) (659:659:659)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT datac (1990:1990:1990) (2095:2095:2095)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT asdata (567:567:567) (646:646:646)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT asdata (569:569:569) (648:648:648)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE KEY\[0\]\~input) @@ -11353,8 +1127,8 @@ (INSTANCE reset) (DELAY (ABSOLUTE - (PORT datac (1566:1566:1566) (1527:1527:1527)) - (PORT datad (531:531:531) (524:524:524)) + (PORT datac (1565:1565:1565) (1526:1526:1526)) + (PORT datad (529:529:529) (525:525:525)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -11365,7 +1139,7 @@ (INSTANCE z80_\|resets_\|x1\~0) (DELAY (ABSOLUTE - (PORT datad (1474:1474:1474) (1549:1549:1549)) + (PORT datad (198:198:198) (224:224:224)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -11375,7 +1149,7 @@ (INSTANCE z80_\|fpga_reset) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1542:1542:1542)) + (PORT clk (1527:1527:1527) (1539:1539:1539)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -11389,7 +1163,7 @@ (INSTANCE z80_\|fpga_reset\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (727:727:727) (752:752:752)) + (PORT inclk[0] (753:753:753) (788:788:788)) ) ) ) @@ -11398,9 +1172,9 @@ (INSTANCE z80_\|resets_\|x1) (DELAY (ABSOLUTE - (PORT clk (1523:1523:1523) (1527:1527:1527)) + (PORT clk (1539:1539:1539) (1540:1540:1540)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1883:1883:1883) (1869:1869:1869)) + (PORT clrn (1574:1574:1574) (1552:1552:1552)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -11411,27 +1185,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc_int\~0) + (INSTANCE z80_\|resets_\|x3) (DELAY (ABSOLUTE - (PORT dataa (649:649:649) (728:728:728)) - (PORT datab (605:605:605) (665:665:665)) - (PORT datad (1168:1168:1168) (1217:1217:1217)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (1901:1901:1901) (2085:2085:2085)) + (PORT datac (1463:1463:1463) (1532:1532:1532)) + (PORT datad (1153:1153:1153) (1264:1264:1264)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|clrpc_int) + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) (DELAY (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) + (PORT clk (1533:1533:1533) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1597:1597:1597) (1572:1572:1572)) + (PORT clrn (1577:1577:1577) (1554:1554:1554)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -11442,166 +1215,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc\~0) + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) (DELAY (ABSOLUTE - (PORT dataa (251:251:251) (340:340:340)) - (PORT datab (253:253:253) (339:339:339)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[7\]) - (DELAY - (ABSOLUTE - (PORT datac (657:657:657) (695:695:695)) - (PORT datad (609:609:609) (638:638:638)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2470:2470:2470) (2664:2664:2664)) - (PORT datac (891:891:891) (959:959:959)) - (PORT datad (1997:1997:1997) (2087:2087:2087)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (394:394:394)) - (PORT datab (558:558:558) (580:580:580)) - (PORT datac (844:844:844) (879:879:879)) - (PORT datad (1124:1124:1124) (1141:1141:1141)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1113:1113:1113) (1149:1149:1149)) - (PORT datab (1162:1162:1162) (1184:1184:1184)) - (PORT datac (794:794:794) (810:810:810)) - (PORT datad (642:642:642) (654:654:654)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (985:985:985) (1053:1053:1053)) - (PORT datab (1645:1645:1645) (1657:1657:1657)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (1141:1141:1141) (1167:1167:1167)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1232:1232:1232) (1303:1303:1303)) - (PORT datab (1001:1001:1001) (1111:1111:1111)) - (PORT datac (655:655:655) (722:722:722)) - (PORT datad (1242:1242:1242) (1330:1330:1330)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (789:789:789) (798:798:798)) - (PORT datab (653:653:653) (676:676:676)) - (PORT datac (834:834:834) (870:870:870)) - (PORT datad (1032:1032:1032) (1091:1091:1091)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (714:714:714) (749:749:749)) - (PORT datac (201:201:201) (236:236:236)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datac (180:180:180) (218:218:218)) - (PORT datad (538:538:538) (562:562:562)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1254:1254:1254) (1307:1307:1307)) - (PORT datab (845:845:845) (854:854:854)) - (PORT datac (835:835:835) (832:832:832)) - (PORT datad (874:874:874) (917:917:917)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT datac (727:727:727) (823:823:823)) + (PORT datad (308:308:308) (411:411:411)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -11609,1226 +1227,37 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[7\]) + (INSTANCE z80_\|interrupts_\|nmi_armed) (DELAY (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT clk (2148:2148:2148) (2241:2241:2241)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2152:2152:2152) (2220:2220:2220)) + (PORT clrn (1481:1481:1481) (1494:1494:1494)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) (DELAY (ABSOLUTE - (PORT dataa (407:407:407) (434:434:434)) - (PORT datab (1814:1814:1814) (1895:1895:1895)) - (PORT datac (201:201:201) (236:236:236)) - (PORT datad (644:644:644) (699:699:699)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT inclk[0] (2234:2234:2234) (2331:2331:2331)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~0) + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) (DELAY (ABSOLUTE - (PORT dataa (1218:1218:1218) (1307:1307:1307)) - (PORT datab (2009:2009:2009) (2129:2129:2129)) - (PORT datac (1296:1296:1296) (1407:1407:1407)) - (PORT datad (2028:2028:2028) (2149:2149:2149)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT datab (1470:1470:1470) (1557:1557:1557)) + (PORT datad (1650:1650:1650) (1825:1825:1825)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (412:412:412)) - (PORT datab (213:213:213) (258:258:258)) - (PORT datac (1100:1100:1100) (1149:1149:1149)) - (PORT datad (1205:1205:1205) (1229:1229:1229)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (1709:1709:1709) (1797:1797:1797)) - (PORT datac (549:549:549) (562:562:562)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) - (DELAY - (ABSOLUTE - (PORT datab (988:988:988) (1021:1021:1021)) - (PORT datac (1126:1126:1126) (1145:1145:1145)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1002:1002:1002) (1072:1072:1072)) - (PORT datad (1126:1126:1126) (1143:1143:1143)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) - (DELAY - (ABSOLUTE - (PORT datab (1546:1546:1546) (1602:1602:1602)) - (PORT datac (1206:1206:1206) (1268:1268:1268)) - (PORT datad (1073:1073:1073) (1099:1099:1099)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) - (DELAY - (ABSOLUTE - (PORT datab (1543:1543:1543) (1602:1602:1602)) - (PORT datac (1215:1215:1215) (1279:1279:1279)) - (PORT datad (985:985:985) (1033:1033:1033)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) - (DELAY - (ABSOLUTE - (PORT datab (1542:1542:1542) (1602:1602:1602)) - (PORT datac (1217:1217:1217) (1279:1279:1279)) - (PORT datad (1074:1074:1074) (1100:1100:1100)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1413:1413:1413) (1448:1448:1448)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) - (DELAY - (ABSOLUTE - (PORT datab (1547:1547:1547) (1607:1607:1607)) - (PORT datac (1199:1199:1199) (1261:1261:1261)) - (PORT datad (990:990:990) (1037:1037:1037)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1413:1413:1413) (1447:1447:1447)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (916:916:916)) - (PORT datab (971:971:971) (1024:1024:1024)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) - (DELAY - (ABSOLUTE - (PORT datab (1381:1381:1381) (1428:1428:1428)) - (PORT datac (1185:1185:1185) (1207:1207:1207)) - (PORT datad (589:589:589) (605:605:605)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (726:726:726) (753:753:753)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (407:407:407)) - (PORT datab (224:224:224) (272:272:272)) - (PORT datac (222:222:222) (301:301:301)) - (PORT datad (1218:1218:1218) (1299:1299:1299)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) - (DELAY - (ABSOLUTE - (PORT datab (1209:1209:1209) (1234:1234:1234)) - (PORT datac (637:637:637) (665:665:665)) - (PORT datad (1346:1346:1346) (1393:1393:1393)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT datab (1212:1212:1212) (1239:1239:1239)) - (PORT datac (637:637:637) (665:665:665)) - (PORT datad (1342:1342:1342) (1391:1391:1391)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (725:725:725) (752:752:752)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (261:261:261) (314:314:314)) - (PORT datad (232:232:232) (270:270:270)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) - (DELAY - (ABSOLUTE - (PORT datac (898:898:898) (941:941:941)) - (PORT datad (1326:1326:1326) (1381:1381:1381)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (770:770:770)) - (PORT datab (1175:1175:1175) (1215:1215:1215)) - (PORT datac (195:195:195) (238:238:238)) - (PORT datad (1436:1436:1436) (1519:1519:1519)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1192:1192:1192) (1227:1227:1227)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (765:765:765)) - (PORT datab (1172:1172:1172) (1214:1214:1214)) - (PORT datac (195:195:195) (237:237:237)) - (PORT datad (1438:1438:1438) (1518:1518:1518)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1193:1193:1193) (1225:1225:1225)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (467:467:467) (505:505:505)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (640:640:640) (663:663:663)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (658:658:658)) - (PORT datab (950:950:950) (994:994:994)) - (PORT datad (672:672:672) (698:698:698)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1673:1673:1673) (1678:1678:1678)) - (PORT ena (1499:1499:1499) (1507:1507:1507)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (674:674:674)) - (PORT datab (1409:1409:1409) (1424:1424:1424)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1144:1144:1144) (1180:1180:1180)) - (PORT datab (1171:1171:1171) (1213:1213:1213)) - (PORT datac (195:195:195) (238:238:238)) - (PORT datad (664:664:664) (715:715:715)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1225:1225:1225) (1263:1263:1263)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (962:962:962)) - (PORT datab (414:414:414) (473:473:473)) - (PORT datac (913:913:913) (963:963:963)) - (PORT datad (609:609:609) (629:629:629)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) - (DELAY - (ABSOLUTE - (PORT dataa (896:896:896) (973:973:973)) - (PORT datab (938:938:938) (1019:1019:1019)) - (PORT datac (1135:1135:1135) (1179:1179:1179)) - (PORT datad (378:378:378) (412:412:412)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) - (DELAY - (ABSOLUTE - (PORT datab (929:929:929) (993:993:993)) - (PORT datac (1324:1324:1324) (1357:1357:1357)) - (PORT datad (891:891:891) (947:947:947)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1168:1168:1168) (1265:1265:1265)) - (PORT datab (1178:1178:1178) (1216:1216:1216)) - (PORT datac (195:195:195) (239:239:239)) - (PORT datad (671:671:671) (719:719:719)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1674:1674:1674) (1676:1676:1676)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) - (DELAY - (ABSOLUTE - (PORT dataa (1791:1791:1791) (1805:1805:1805)) - (PORT datab (916:916:916) (986:986:986)) - (PORT datad (905:905:905) (958:958:958)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1226:1226:1226) (1265:1265:1265)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (433:433:433) (465:465:465)) - (PORT datab (634:634:634) (665:665:665)) - (PORT datad (357:357:357) (410:410:410)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) - (DELAY - (ABSOLUTE - (PORT dataa (1721:1721:1721) (1780:1780:1780)) - (PORT datab (1171:1171:1171) (1225:1225:1225)) - (PORT datad (792:792:792) (797:797:797)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1407:1407:1407) (1434:1434:1434)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (841:841:841) (868:868:868)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT datab (1032:1032:1032) (1065:1065:1065)) - (PORT datac (905:905:905) (951:951:951)) - (PORT datad (876:876:876) (937:937:937)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (407:407:407) (468:468:468)) - (PORT datab (590:590:590) (630:630:630)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (530:530:530) (540:540:540)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (699:699:699)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datad (780:780:780) (810:810:810)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (397:397:397)) - (PORT datab (625:625:625) (654:654:654)) - (PORT datac (1393:1393:1393) (1416:1416:1416)) - (PORT datad (618:618:618) (673:673:673)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1402:1402:1402) (1441:1441:1441)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (264:264:264)) - (PORT datab (1232:1232:1232) (1270:1270:1270)) - (PORT datad (658:658:658) (688:688:688)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (671:671:671) (703:703:703)) - (PORT datac (1147:1147:1147) (1188:1188:1188)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1460:1460:1460) (1492:1492:1492)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1460:1460:1460) (1491:1491:1491)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (262:262:262) (315:315:315)) - (PORT datad (233:233:233) (271:271:271)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT asdata (1185:1185:1185) (1213:1213:1213)) - (PORT ena (816:816:816) (813:813:813)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|db\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1227:1227:1227)) - (PORT datab (1541:1541:1541) (1602:1602:1602)) - (PORT datad (1074:1074:1074) (1100:1100:1100)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1483:1483:1483) (1519:1519:1519)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (688:688:688)) - (PORT datab (1088:1088:1088) (1097:1097:1097)) - (PORT datad (940:940:940) (980:980:980)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1236:1236:1236) (1247:1247:1247)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1237:1237:1237) (1246:1246:1246)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (696:696:696)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (367:367:367) (395:395:395)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1461:1461:1461) (1534:1534:1534)) - (PORT ena (1505:1505:1505) (1518:1518:1518)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (347:347:347) (372:372:372)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1458:1458:1458) (1530:1530:1530)) - (PORT ena (1407:1407:1407) (1382:1382:1382)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (430:430:430) (499:499:499)) - (PORT datab (652:652:652) (676:676:676)) - (PORT datad (827:827:827) (837:837:837)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1212:1212:1212) (1256:1256:1256)) - (PORT datab (919:919:919) (944:944:944)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (939:939:939) (964:964:964)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (455:455:455) (491:491:491)) - (PORT datab (1133:1133:1133) (1178:1178:1178)) - (PORT datad (539:539:539) (559:559:559)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1719:1719:1719) (1765:1765:1765)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1719:1719:1719) (1768:1768:1768)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (470:470:470)) - (PORT datab (585:585:585) (623:623:623)) - (PORT datad (216:216:216) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (635:635:635)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (344:344:344) (368:368:368)) - (PORT datad (597:597:597) (607:607:607)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1201:1201:1201) (1235:1235:1235)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (1104:1104:1104) (1151:1151:1151)) - (PORT datad (820:820:820) (839:839:839)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1589:1589:1589) (1608:1608:1608)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1178:1178:1178) (1198:1198:1198)) - (PORT datab (697:697:697) (724:724:724)) - (PORT datad (1194:1194:1194) (1230:1230:1230)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT datab (243:243:243) (325:325:325)) - (PORT datac (706:706:706) (737:737:737)) - (PORT datad (842:842:842) (876:876:876)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) - (DELAY - (ABSOLUTE - (PORT dataa (938:938:938) (985:985:985)) - (PORT datab (912:912:912) (985:985:985)) - (PORT datac (1500:1500:1500) (1547:1547:1547)) - (PORT datad (662:662:662) (730:730:730)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -12842,105 +1271,14 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~14) - (DELAY - (ABSOLUTE - (PORT datab (1393:1393:1393) (1462:1462:1462)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (265:265:265) (352:352:352)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~2) - (DELAY - (ABSOLUTE - (PORT datac (830:830:830) (872:872:872)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~18) - (DELAY - (ABSOLUTE - (PORT datad (660:660:660) (722:722:722)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~1) - (DELAY - (ABSOLUTE - (PORT datab (230:230:230) (272:272:272)) - (PORT datad (560:560:560) (588:588:588)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~0) (DELAY (ABSOLUTE - (PORT datab (1071:1071:1071) (1110:1110:1110)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (670:670:670) (741:741:741)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -12950,8 +1288,8 @@ (INSTANCE ula_\|video_\|vga_hc\~3) (DELAY (ABSOLUTE - (PORT datac (830:830:830) (865:865:865)) - (PORT datad (903:903:903) (941:941:941)) + (PORT datac (372:372:372) (407:407:407)) + (PORT datad (630:630:630) (642:642:642)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -12962,7 +1300,7 @@ (INSTANCE ula_\|video_\|vga_hc\[0\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) + (PORT clk (1540:1540:1540) (1552:1552:1552)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -12976,7 +1314,7 @@ (INSTANCE ula_\|video_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (672:672:672) (727:727:727)) + (PORT datab (460:460:460) (524:524:524)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -12990,7 +1328,7 @@ (INSTANCE ula_\|video_\|vga_hc\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (590:590:590) (612:612:612)) + (PORT datad (330:330:330) (344:344:344)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13000,7 +1338,7 @@ (INSTANCE ula_\|video_\|vga_hc\[1\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13014,7 +1352,7 @@ (INSTANCE ula_\|video_\|Add0\~4) (DELAY (ABSOLUTE - (PORT datab (410:410:410) (485:485:485)) + (PORT datab (411:411:411) (488:488:488)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13028,8 +1366,8 @@ (INSTANCE ula_\|video_\|vga_hc\[2\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) - (PORT asdata (663:663:663) (679:679:679)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (865:865:865) (873:873:873)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13042,37 +1380,27 @@ (INSTANCE ula_\|video_\|Add0\~6) (DELAY (ABSOLUTE - (PORT datab (693:693:693) (745:745:745)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (643:643:643) (698:698:698)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (558:558:558) (581:581:581)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|vga_hc\[3\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (870:870:870) (883:883:883)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL @@ -13080,7 +1408,7 @@ (INSTANCE ula_\|video_\|Add0\~8) (DELAY (ABSOLUTE - (PORT dataa (1094:1094:1094) (1127:1127:1127)) + (PORT dataa (642:642:642) (711:711:711)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13094,8 +1422,104 @@ (INSTANCE ula_\|video_\|vga_hc\[4\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) - (PORT asdata (662:662:662) (678:678:678)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (876:876:876) (877:877:877)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT datab (827:827:827) (881:881:881)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\~0) + (DELAY + (ABSOLUTE + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (626:626:626) (651:651:651)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (518:518:518) (549:549:549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (1373:1373:1373) (1418:1418:1418)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (658:658:658) (673:673:673)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (731:731:731)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (1457:1457:1457) (1474:1474:1474)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13108,10 +1532,10 @@ (INSTANCE ula_\|video_\|Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (1251:1251:1251) (1340:1340:1340)) - (PORT datab (983:983:983) (1062:1062:1062)) - (PORT datac (978:978:978) (1050:1050:1050)) - (PORT datad (282:282:282) (366:366:366)) + (PORT dataa (442:442:442) (542:542:542)) + (PORT datab (973:973:973) (1044:1044:1044)) + (PORT datac (708:708:708) (773:773:773)) + (PORT datad (740:740:740) (794:794:794)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -13124,39 +1548,24 @@ (INSTANCE ula_\|video_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (687:687:687) (737:737:737)) - (PORT datab (1394:1394:1394) (1464:1464:1464)) - (PORT datad (941:941:941) (937:937:937)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (523:523:523)) - (PORT datab (684:684:684) (758:758:758)) - (PORT datac (646:646:646) (716:716:716)) - (PORT datad (570:570:570) (576:576:576)) + (PORT dataa (1238:1238:1238) (1307:1307:1307)) + (PORT datab (920:920:920) (963:963:963)) + (PORT datac (651:651:651) (705:705:705)) + (PORT datad (174:174:174) (200:200:200)) (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~10) + (INSTANCE ula_\|video_\|Add0\~16) (DELAY (ABSOLUTE - (PORT dataa (684:684:684) (734:734:734)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (1079:1079:1079) (1140:1140:1140)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -13166,22 +1575,130 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~0) + (INSTANCE ula_\|video_\|vga_hc\~2) (DELAY (ABSOLUTE - (PORT datac (833:833:833) (875:875:875)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datad (626:626:626) (651:651:651)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[5\]) + (INSTANCE ula_\|video_\|vga_hc\[8\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (868:868:868) (876:876:876)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datab (265:265:265) (348:348:348)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\~1) + (DELAY + (ABSOLUTE + (PORT datab (344:344:344) (377:377:377)) + (PORT datad (627:627:627) (653:653:653)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (1429:1429:1429) (1430:1430:1430)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (269:269:269)) + (PORT datab (1253:1253:1253) (1334:1334:1334)) + (PORT datac (909:909:909) (963:963:963)) + (PORT datad (873:873:873) (928:928:928)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1244:1244:1244) (1316:1316:1316)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (711:711:711) (769:769:769)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (703:703:703)) + (PORT datab (1503:1503:1503) (1521:1521:1521)) + (PORT datad (594:594:594) (607:607:607)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1552:1552:1552)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13190,82 +1707,14 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~12) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (686:686:686)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) - (PORT asdata (516:516:516) (547:547:547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) - (PORT asdata (869:869:869) (872:872:872)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~0) - (DELAY - (ABSOLUTE - (PORT datab (720:720:720) (795:795:795)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~2) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (782:782:782)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~4) (DELAY (ABSOLUTE - (PORT dataa (679:679:679) (747:747:747)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (678:678:678) (738:738:738)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -13277,9 +1726,9 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (517:517:517) (564:564:564)) - (PORT datab (595:595:595) (609:609:609)) - (PORT datad (899:899:899) (922:922:922)) + (PORT dataa (657:657:657) (705:705:705)) + (PORT datab (638:638:638) (664:664:664)) + (PORT datad (1466:1466:1466) (1485:1485:1485)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -13292,7 +1741,7 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1541:1541:1541) (1552:1552:1552)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13306,9 +1755,9 @@ (INSTANCE ula_\|video_\|Add1\~6) (DELAY (ABSOLUTE - (PORT dataa (712:712:712) (782:782:782)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (704:704:704) (764:764:764)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -13320,13 +1769,12 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (616:616:616) (648:648:648)) - (PORT datab (645:645:645) (692:692:692)) - (PORT datac (679:679:679) (747:747:747)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (654:654:654) (701:701:701)) + (PORT datab (1504:1504:1504) (1520:1520:1520)) + (PORT datad (597:597:597) (611:611:611)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13336,13 +1784,13 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1361:1361:1361) (1352:1352:1352)) + (PORT clk (1541:1541:1541) (1552:1552:1552)) + (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) ) ) (CELL @@ -13350,9 +1798,9 @@ (INSTANCE ula_\|video_\|Add1\~8) (DELAY (ABSOLUTE - (PORT datab (680:680:680) (762:762:762)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (965:965:965) (1008:1008:1008)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -13364,9 +1812,9 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]\~5) (DELAY (ABSOLUTE - (PORT dataa (516:516:516) (565:565:565)) - (PORT datab (625:625:625) (643:643:643)) - (PORT datad (899:899:899) (921:921:921)) + (PORT dataa (653:653:653) (704:704:704)) + (PORT datab (669:669:669) (683:683:683)) + (PORT datad (1464:1464:1464) (1484:1484:1484)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -13379,7 +1827,7 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1541:1541:1541) (1552:1552:1552)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13393,9 +1841,9 @@ (INSTANCE ula_\|video_\|Add1\~10) (DELAY (ABSOLUTE - (PORT dataa (690:690:690) (785:785:785)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (735:735:735) (804:804:804)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -13407,13 +1855,12 @@ (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) (DELAY (ABSOLUTE - (PORT dataa (616:616:616) (645:645:645)) - (PORT datab (645:645:645) (689:689:689)) - (PORT datac (698:698:698) (778:778:778)) - (PORT datad (175:175:175) (199:199:199)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (660:660:660) (706:706:706)) + (PORT datab (1508:1508:1508) (1524:1524:1524)) + (PORT datad (585:585:585) (600:600:600)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13423,13 +1870,13 @@ (INSTANCE ula_\|video_\|vga_vc\[5\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (884:884:884) (883:883:883)) + (PORT clk (1541:1541:1541) (1552:1552:1552)) + (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) ) ) (CELL @@ -13437,9 +1884,9 @@ (INSTANCE ula_\|video_\|Add1\~12) (DELAY (ABSOLUTE - (PORT datab (720:720:720) (789:789:789)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (966:966:966) (1010:1010:1010)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -13451,11 +1898,11 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]\~4) (DELAY (ABSOLUTE - (PORT dataa (519:519:519) (562:562:562)) - (PORT datab (588:588:588) (607:607:607)) - (PORT datad (902:902:902) (917:917:917)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (701:701:701) (726:726:726)) + (PORT datab (586:586:586) (616:616:616)) + (PORT datad (775:775:775) (772:772:772)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13466,7 +1913,7 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13480,7 +1927,7 @@ (INSTANCE ula_\|video_\|Add1\~14) (DELAY (ABSOLUTE - (PORT datab (691:691:691) (762:762:762)) + (PORT datab (965:965:965) (1025:1025:1025)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13494,9 +1941,9 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]\~6) (DELAY (ABSOLUTE - (PORT dataa (517:517:517) (566:566:566)) - (PORT datab (1177:1177:1177) (1178:1178:1178)) - (PORT datad (900:900:900) (920:920:920)) + (PORT dataa (699:699:699) (723:723:723)) + (PORT datab (1070:1070:1070) (1068:1068:1068)) + (PORT datad (558:558:558) (576:576:576)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -13509,7 +1956,7 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13523,7 +1970,7 @@ (INSTANCE ula_\|video_\|Add1\~16) (DELAY (ABSOLUTE - (PORT datab (743:743:743) (817:817:817)) + (PORT datab (954:954:954) (1004:1004:1004)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13537,9 +1984,9 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]\~7) (DELAY (ABSOLUTE - (PORT dataa (517:517:517) (558:558:558)) - (PORT datab (998:998:998) (1000:1000:1000)) - (PORT datad (899:899:899) (916:916:916)) + (PORT dataa (700:700:700) (726:726:726)) + (PORT datab (1128:1128:1128) (1126:1126:1126)) + (PORT datad (558:558:558) (578:578:578)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -13552,7 +1999,7 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13566,7 +2013,7 @@ (INSTANCE ula_\|video_\|Add1\~18) (DELAY (ABSOLUTE - (PORT datad (650:650:650) (707:707:707)) + (PORT datad (644:644:644) (702:702:702)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -13577,11 +2024,11 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]\~9) (DELAY (ABSOLUTE - (PORT dataa (518:518:518) (565:565:565)) - (PORT datab (1005:1005:1005) (1007:1007:1007)) - (PORT datad (899:899:899) (922:922:922)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (702:702:702) (724:724:724)) + (PORT datab (586:586:586) (613:613:613)) + (PORT datad (781:781:781) (782:782:782)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13592,7 +2039,7 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13603,31 +2050,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal2\~0) + (INSTANCE ula_\|video_\|Equal3\~0) (DELAY (ABSOLUTE - (PORT dataa (272:272:272) (361:361:361)) - (PORT datab (270:270:270) (356:356:356)) - (PORT datac (263:263:263) (343:343:343)) - (PORT datad (244:244:244) (317:317:317)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (282:282:282) (378:378:378)) + (PORT datab (715:715:715) (775:775:775)) + (PORT datac (648:648:648) (714:714:714)) + (PORT datad (1179:1179:1179) (1245:1245:1245)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal3\~0) + (INSTANCE ula_\|video_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (1173:1173:1173) (1262:1262:1262)) - (PORT datab (846:846:846) (922:922:922)) - (PORT datac (628:628:628) (679:679:679)) - (PORT datad (673:673:673) (746:746:746)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (426:426:426) (493:493:493)) + (PORT datab (290:290:290) (374:374:374)) + (PORT datac (250:250:250) (333:333:333)) + (PORT datad (421:421:421) (482:482:482)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13638,13 +2085,13 @@ (INSTANCE ula_\|video_\|Equal3\~1) (DELAY (ABSOLUTE - (PORT dataa (635:635:635) (701:701:701)) - (PORT datab (664:664:664) (725:725:725)) - (PORT datac (564:564:564) (582:582:582)) - (PORT datad (306:306:306) (321:321:321)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (400:400:400) (484:484:484)) + (PORT datab (873:873:873) (896:896:896)) + (PORT datac (620:620:620) (674:674:674)) + (PORT datad (590:590:590) (603:603:603)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13654,11 +2101,11 @@ (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (518:518:518) (561:561:561)) - (PORT datab (553:553:553) (567:567:567)) - (PORT datad (900:900:900) (915:915:915)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (653:653:653) (704:704:704)) + (PORT datab (1503:1503:1503) (1523:1523:1523)) + (PORT datad (313:313:313) (333:333:333)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13669,7 +2116,7 @@ (INSTANCE ula_\|video_\|vga_vc\[0\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1541:1541:1541) (1552:1552:1552)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13680,32 +2127,33 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (INSTANCE ula_\|video_\|Equal2\~1) (DELAY (ABSOLUTE - (PORT dataa (516:516:516) (560:560:560)) - (PORT datab (566:566:566) (575:575:575)) - (PORT datad (899:899:899) (916:916:916)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (414:414:414) (488:488:488)) + (PORT datab (715:715:715) (775:775:775)) + (PORT datac (648:648:648) (712:712:712)) + (PORT datad (372:372:372) (442:442:442)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[1\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal2\~2) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT dataa (345:345:345) (385:385:385)) + (PORT datac (620:620:620) (674:674:674)) + (PORT datad (591:591:591) (604:604:604)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_io_ibuf") @@ -13721,10 +2169,10 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13\~0) (DELAY (ABSOLUTE - (PORT dataa (1420:1420:1420) (1497:1497:1497)) - (PORT datab (716:716:716) (801:801:801)) - (PORT datac (1844:1844:1844) (1733:1733:1733)) - (PORT datad (677:677:677) (732:732:732)) + (PORT dataa (919:919:919) (997:997:997)) + (PORT datab (946:946:946) (1004:1004:1004)) + (PORT datac (905:905:905) (970:970:970)) + (PORT datad (1292:1292:1292) (1213:1213:1213)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -13734,15 +2182,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal79\~0) + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) (DELAY (ABSOLUTE - (PORT dataa (1251:1251:1251) (1348:1348:1348)) - (PORT datab (976:976:976) (1034:1034:1034)) - (PORT datac (1637:1637:1637) (1758:1758:1758)) - (PORT datad (1191:1191:1191) (1306:1306:1306)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT datac (1393:1393:1393) (1460:1460:1460)) + (PORT datad (1899:1899:1899) (2006:2006:2006)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13750,50 +2194,55 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) + (INSTANCE z80_\|execute_\|ctl_mWrite\~4) (DELAY (ABSOLUTE - (PORT dataa (1500:1500:1500) (1602:1602:1602)) - (PORT datab (361:361:361) (391:391:391)) - (PORT datad (665:665:665) (720:720:720)) + (PORT dataa (784:784:784) (852:852:852)) + (PORT datab (1496:1496:1496) (1609:1609:1609)) + (PORT datac (1839:1839:1839) (1973:1973:1973)) + (PORT datad (1690:1690:1690) (1763:1763:1763)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1772:1772:1772) (1878:1878:1878)) + (PORT datad (331:331:331) (359:359:359)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M3_ff\~0) + (DELAY + (ABSOLUTE + (PORT dataa (408:408:408) (485:485:485)) + (PORT datab (707:707:707) (759:759:759)) + (PORT datad (898:898:898) (912:912:912)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (495:495:495)) - (PORT datab (2014:2014:2014) (2140:2140:2140)) - (PORT datad (275:275:275) (358:358:358)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (1586:1586:1586) (1625:1625:1625)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) + (INSTANCE z80_\|sequencer_\|DFFE_M3_ff) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1553:1553:1553)) + (PORT clk (1525:1525:1525) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1552:1552:1552) (1543:1543:1543)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -13804,31 +2253,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~0) + (INSTANCE z80_\|execute_\|ixy_d\~6) (DELAY (ABSOLUTE - (PORT dataa (706:706:706) (765:765:765)) - (PORT datab (266:266:266) (349:349:349)) - (PORT datac (204:204:204) (241:241:241)) - (PORT datad (1456:1456:1456) (1550:1550:1550)) + (PORT dataa (1418:1418:1418) (1546:1546:1546)) + (PORT datad (934:934:934) (1041:1041:1041)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla12M3T3_3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1912:1912:1912) (2001:2001:2001)) + (PORT datab (207:207:207) (250:250:250)) + (PORT datac (622:622:622) (681:681:681)) + (PORT datad (1605:1605:1605) (1758:1758:1758)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1287:1287:1287) (1330:1330:1330)) - (PORT datab (266:266:266) (349:349:349)) - (PORT datac (888:888:888) (913:913:913)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13836,631 +2281,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) + (INSTANCE z80_\|pla_decode_\|Equal33\~0) (DELAY (ABSOLUTE - (PORT datab (1431:1431:1431) (1492:1492:1492)) - (PORT datac (1518:1518:1518) (1551:1551:1551)) - (PORT datad (1267:1267:1267) (1335:1335:1335)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|iff1) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1403:1403:1403) (1412:1412:1412)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1600:1600:1600) (1657:1657:1657)) - (PORT datab (843:843:843) (917:917:917)) - (PORT datac (633:633:633) (688:688:688)) - (PORT datad (427:427:427) (498:498:498)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (565:565:565) (583:583:583)) - (PORT datad (436:436:436) (516:516:516)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) - (DELAY - (ABSOLUTE - (PORT dataa (1175:1175:1175) (1240:1240:1240)) - (PORT datab (630:630:630) (645:645:645)) - (PORT datac (1541:1541:1541) (1636:1636:1636)) - (PORT datad (848:848:848) (861:861:861)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|int_armed) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1542:1542:1542)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1562:1562:1562) (1552:1552:1552)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|DFFE_inst44) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1552:1552:1552)) - (PORT asdata (2158:2158:2158) (2284:2284:2284)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (1669:1669:1669) (1678:1678:1678)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~38) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (487:487:487)) - (PORT datac (1180:1180:1180) (1261:1261:1261)) - (PORT datad (269:269:269) (350:350:350)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~91) - (DELAY - (ABSOLUTE - (PORT dataa (1671:1671:1671) (1790:1790:1790)) - (PORT datab (1251:1251:1251) (1347:1347:1347)) - (PORT datac (971:971:971) (1065:1065:1065)) - (PORT datad (862:862:862) (887:887:887)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1089:1089:1089) (1139:1139:1139)) - (PORT datab (699:699:699) (765:765:765)) - (PORT datac (1191:1191:1191) (1271:1271:1271)) - (PORT datad (626:626:626) (668:668:668)) + (PORT dataa (1771:1771:1771) (1874:1874:1874)) + (PORT datab (1642:1642:1642) (1796:1796:1796)) + (PORT datad (1883:1883:1883) (1955:1955:1955)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~44) + (INSTANCE z80_\|execute_\|ctl_mRead\~5) (DELAY (ABSOLUTE - (PORT dataa (1090:1090:1090) (1140:1140:1140)) - (PORT datab (909:909:909) (981:981:981)) - (PORT datac (856:856:856) (898:898:898)) - (PORT datad (1096:1096:1096) (1107:1107:1107)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~46) - (DELAY - (ABSOLUTE - (PORT dataa (338:338:338) (372:372:372)) - (PORT datab (702:702:702) (770:770:770)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (1101:1101:1101) (1112:1112:1112)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1161:1161:1161) (1207:1207:1207)) - (PORT datab (884:884:884) (933:933:933)) - (PORT datac (1058:1058:1058) (1098:1098:1098)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~50) - (DELAY - (ABSOLUTE - (PORT dataa (830:830:830) (863:863:863)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1604:1604:1604) (1719:1719:1719)) - (PORT datad (2285:2285:2285) (2389:2389:2389)) + (PORT dataa (1549:1549:1549) (1644:1644:1644)) + (PORT datab (263:263:263) (310:310:310)) + (PORT datac (1465:1465:1465) (1503:1503:1503)) + (PORT datad (1184:1184:1184) (1237:1237:1237)) (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~33) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (276:276:276)) - (PORT datab (1151:1151:1151) (1219:1219:1219)) - (PORT datac (1080:1080:1080) (1126:1126:1126)) - (PORT datad (596:596:596) (629:629:629)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (1685:1685:1685) (1750:1750:1750)) - (PORT datab (623:623:623) (672:672:672)) - (PORT datac (1663:1663:1663) (1743:1743:1743)) - (PORT datad (1164:1164:1164) (1212:1212:1212)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (825:825:825)) - (PORT datab (672:672:672) (761:761:761)) - (PORT datac (1148:1148:1148) (1186:1186:1186)) - (PORT datad (212:212:212) (247:247:247)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1165:1165:1165)) - (PORT datab (850:850:850) (866:866:866)) - (PORT datac (1208:1208:1208) (1236:1236:1236)) - (PORT datad (822:822:822) (834:834:834)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1110:1110:1110) (1168:1168:1168)) - (PORT datab (622:622:622) (673:673:673)) - (PORT datac (209:209:209) (250:250:250)) - (PORT datad (1641:1641:1641) (1711:1711:1711)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~34) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (193:193:193) (238:238:238)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1149:1149:1149) (1191:1191:1191)) - (PORT datab (1399:1399:1399) (1505:1505:1505)) - (PORT datac (2514:2514:2514) (2618:2618:2618)) - (PORT datad (1497:1497:1497) (1611:1611:1611)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~30) - (DELAY - (ABSOLUTE - (PORT dataa (691:691:691) (738:738:738)) - (PORT datab (1144:1144:1144) (1210:1210:1210)) - (PORT datac (365:365:365) (393:393:393)) - (PORT datad (865:865:865) (890:890:890)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1521:1521:1521) (1648:1648:1648)) - (PORT datab (1395:1395:1395) (1501:1501:1501)) - (PORT datac (2518:2518:2518) (2621:2621:2621)) - (PORT datad (1054:1054:1054) (1086:1086:1086)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~35) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (406:406:406)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (619:619:619) (652:652:652)) - (PORT datad (179:179:179) (207:207:207)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1104:1104:1104) (1123:1123:1123)) - (PORT datab (643:643:643) (662:662:662)) - (PORT datac (625:625:625) (646:646:646)) - (PORT datad (1379:1379:1379) (1419:1419:1419)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) - (DELAY - (ABSOLUTE - (PORT dataa (2071:2071:2071) (2185:2185:2185)) - (PORT datab (910:910:910) (981:981:981)) - (PORT datac (1397:1397:1397) (1483:1483:1483)) - (PORT datad (646:646:646) (677:677:677)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (1333:1333:1333) (1437:1437:1437)) - (PORT datab (1764:1764:1764) (1881:1881:1881)) - (PORT datad (630:630:630) (685:685:685)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (266:266:266)) - (PORT datab (216:216:216) (261:261:261)) - (PORT datac (670:670:670) (716:716:716)) - (PORT datad (570:570:570) (590:590:590)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1409:1409:1409) (1454:1454:1454)) - (PORT datab (666:666:666) (697:697:697)) - (PORT datac (1989:1989:1989) (2085:2085:2085)) - (PORT datad (1246:1246:1246) (1294:1294:1294)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (635:635:635) (682:682:682)) - (PORT datad (190:190:190) (223:223:223)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (421:421:421)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (637:637:637) (672:672:672)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (722:722:722)) - (PORT datab (699:699:699) (766:766:766)) - (PORT datac (639:639:639) (671:671:671)) - (PORT datad (1153:1153:1153) (1224:1224:1224)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1647:1647:1647) (1764:1764:1764)) - (PORT datab (1067:1067:1067) (1136:1136:1136)) - (PORT datac (612:612:612) (631:631:631)) - (PORT datad (973:973:973) (1058:1058:1058)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~39) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (264:264:264)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (623:623:623) (647:647:647)) - (PORT datad (565:565:565) (585:585:585)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~47) - (DELAY - (ABSOLUTE - (PORT dataa (399:399:399) (422:422:422)) - (PORT datab (212:212:212) (257:257:257)) - (PORT datac (620:620:620) (677:677:677)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (881:881:881) (895:895:895)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) - (DELAY - (ABSOLUTE - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (636:636:636) (661:661:661)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (257:257:257)) - (PORT datab (341:341:341) (376:376:376)) - (PORT datac (639:639:639) (674:674:674)) - (PORT datad (182:182:182) (213:213:213)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (725:725:725)) - (PORT datab (911:911:911) (985:985:985)) - (PORT datac (1190:1190:1190) (1272:1272:1272)) - (PORT datad (188:188:188) (220:220:220)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) - (DELAY - (ABSOLUTE - (PORT dataa (868:868:868) (915:915:915)) - (PORT datab (682:682:682) (741:741:741)) - (PORT datac (965:965:965) (1027:1027:1027)) - (PORT datad (621:621:621) (668:668:668)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14468,281 +2311,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) + (INSTANCE z80_\|pla_decode_\|Equal77\~0) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (684:684:684) (749:749:749)) - (PORT datac (972:972:972) (1033:1033:1033)) - (PORT datad (1668:1668:1668) (1690:1690:1690)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (255:255:255)) - (PORT datab (340:340:340) (370:370:370)) - (PORT datac (638:638:638) (672:672:672)) - (PORT datad (357:357:357) (377:377:377)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) - (DELAY - (ABSOLUTE - (PORT datab (205:205:205) (245:245:245)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (180:180:180) (207:207:207)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~42) - (DELAY - (ABSOLUTE - (PORT datab (652:652:652) (687:687:687)) - (PORT datac (339:339:339) (370:370:370)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~90) - (DELAY - (ABSOLUTE - (PORT dataa (1017:1017:1017) (1099:1099:1099)) - (PORT datab (1086:1086:1086) (1123:1123:1123)) - (PORT datac (1171:1171:1171) (1232:1232:1232)) - (PORT datad (1497:1497:1497) (1611:1611:1611)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~41) - (DELAY - (ABSOLUTE - (PORT dataa (227:227:227) (279:279:279)) - (PORT datab (627:627:627) (674:674:674)) - (PORT datac (208:208:208) (246:246:246)) - (PORT datad (180:180:180) (207:207:207)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (494:494:494)) - (PORT datab (902:902:902) (935:935:935)) - (PORT datac (1178:1178:1178) (1261:1261:1261)) - (PORT datad (273:273:273) (355:355:355)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1166:1166:1166)) - (PORT datab (227:227:227) (270:270:270)) - (PORT datac (194:194:194) (242:242:242)) - (PORT datad (872:872:872) (923:923:923)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) - (DELAY - (ABSOLUTE - (PORT dataa (1443:1443:1443) (1505:1505:1505)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (1642:1642:1642) (1712:1712:1712)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) - (DELAY - (ABSOLUTE - (PORT dataa (1110:1110:1110) (1166:1166:1166)) - (PORT datab (235:235:235) (278:278:278)) - (PORT datac (195:195:195) (241:241:241)) - (PORT datad (596:596:596) (630:630:630)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (888:888:888)) - (PORT datab (1133:1133:1133) (1145:1145:1145)) - (PORT datac (343:343:343) (372:372:372)) - (PORT datad (854:854:854) (886:886:886)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) - (DELAY - (ABSOLUTE - (PORT dataa (1157:1157:1157) (1221:1221:1221)) - (PORT datab (375:375:375) (398:398:398)) - (PORT datac (308:308:308) (325:325:325)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (330:330:330) (348:348:348)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) - (DELAY - (ABSOLUTE - (PORT dataa (663:663:663) (715:715:715)) - (PORT datab (410:410:410) (440:440:440)) - (PORT datac (1131:1131:1131) (1156:1156:1156)) - (PORT datad (854:854:854) (887:887:887)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) - (DELAY - (ABSOLUTE - (PORT dataa (663:663:663) (719:719:719)) - (PORT datab (946:946:946) (985:985:985)) - (PORT datac (1123:1123:1123) (1165:1165:1165)) - (PORT datad (1721:1721:1721) (1778:1778:1778)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (395:395:395)) - (PORT datab (1129:1129:1129) (1184:1184:1184)) - (PORT datac (1040:1040:1040) (1054:1054:1054)) - (PORT datad (1204:1204:1204) (1229:1229:1229)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (717:717:717)) - (PORT datab (921:921:921) (959:959:959)) - (PORT datac (913:913:913) (949:949:949)) - (PORT datad (313:313:313) (331:331:331)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) - (DELAY - (ABSOLUTE - (PORT dataa (902:902:902) (981:981:981)) - (PORT datab (893:893:893) (932:932:932)) - (PORT datac (1434:1434:1434) (1470:1470:1470)) - (PORT datad (843:843:843) (890:890:890)) + (PORT dataa (787:787:787) (855:855:855)) + (PORT datab (770:770:770) (837:837:837)) + (PORT datac (1831:1831:1831) (1966:1966:1966)) + (PORT datad (1685:1685:1685) (1757:1757:1757)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -14752,15 +2327,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) + (INSTANCE z80_\|pla_decode_\|Equal50\~0) (DELAY (ABSOLUTE - (PORT dataa (1466:1466:1466) (1512:1512:1512)) - (PORT datab (915:915:915) (968:968:968)) - (PORT datac (321:321:321) (356:356:356)) - (PORT datad (174:174:174) (200:200:200)) + (PORT dataa (1231:1231:1231) (1295:1295:1295)) + (PORT datac (924:924:924) (977:977:977)) + (PORT datad (1184:1184:1184) (1237:1237:1237)) (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14768,109 +2341,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (280:280:280)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (588:588:588) (601:601:601)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) - (DELAY - (ABSOLUTE - (PORT dataa (1188:1188:1188) (1234:1234:1234)) - (PORT datab (1144:1144:1144) (1214:1214:1214)) - (PORT datac (364:364:364) (396:396:396)) - (PORT datad (1141:1141:1141) (1188:1188:1188)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1132:1132:1132)) - (PORT datab (1153:1153:1153) (1193:1193:1193)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) - (DELAY - (ABSOLUTE - (PORT dataa (956:956:956) (987:987:987)) - (PORT datab (921:921:921) (959:959:959)) - (PORT datac (635:635:635) (676:676:676)) - (PORT datad (1543:1543:1543) (1626:1626:1626)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) - (DELAY - (ABSOLUTE - (PORT dataa (457:457:457) (498:498:498)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (805:805:805) (826:826:826)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~89) - (DELAY - (ABSOLUTE - (PORT dataa (1333:1333:1333) (1437:1437:1437)) - (PORT datab (1163:1163:1163) (1169:1169:1169)) - (PORT datac (1430:1430:1430) (1469:1469:1469)) - (PORT datad (844:844:844) (894:894:894)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (254:254:254)) - (PORT datab (828:828:828) (830:830:830)) - (PORT datac (314:314:314) (333:333:333)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (642:642:642) (713:713:713)) + (PORT datac (679:679:679) (726:726:726)) + (PORT datad (895:895:895) (912:912:912)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14878,15 +2355,115 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) (DELAY (ABSOLUTE - (PORT dataa (907:907:907) (937:937:937)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (590:590:590) (602:602:602)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (1354:1354:1354) (1515:1515:1515)) + (PORT datab (2217:2217:2217) (2404:2404:2404)) + (PORT datac (387:387:387) (452:452:452)) + (PORT datad (308:308:308) (411:411:411)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1590:1590:1590) (1567:1567:1567)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|DFF_inst5\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1182:1182:1182) (1247:1247:1247)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|DFF_inst5) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (344:344:344)) + (PORT datad (1180:1180:1180) (1243:1243:1243)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT ena (1243:1243:1243) (1234:1234:1234)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) + (DELAY + (ABSOLUTE + (PORT datab (1537:1537:1537) (1637:1637:1637)) + (PORT datac (1180:1180:1180) (1248:1248:1248)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1204:1204:1204) (1263:1263:1263)) + (PORT datab (1222:1222:1222) (1236:1236:1236)) + (PORT datac (2271:2271:2271) (2399:2399:2399)) + (PORT datad (364:364:364) (396:396:396)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14894,16 +2471,505 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) + (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) (DELAY (ABSOLUTE - (PORT dataa (1157:1157:1157) (1220:1220:1220)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (563:563:563) (566:566:566)) - (PORT datad (559:559:559) (582:582:582)) - (IOPATH dataa combout (337:337:337) (338:338:338)) + (PORT dataa (2287:2287:2287) (2396:2396:2396)) + (PORT datab (2178:2178:2178) (2359:2359:2359)) + (PORT datac (1216:1216:1216) (1300:1300:1300)) + (PORT datad (874:874:874) (939:939:939)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_inst4) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1565:1565:1565) (1545:1545:1545)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~3) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (434:434:434)) + (PORT datab (224:224:224) (271:271:271)) + (PORT datac (1000:1000:1000) (1080:1080:1080)) + (PORT datad (1503:1503:1503) (1556:1556:1556)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M4_ff\~0) + (DELAY + (ABSOLUTE + (PORT dataa (420:420:420) (502:502:502)) + (PORT datab (708:708:708) (757:757:757)) + (PORT datad (899:899:899) (915:915:915)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M4_ff) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2484:2484:2484) (2682:2682:2682)) + (PORT datab (1562:1562:1562) (1651:1651:1651)) + (PORT datac (1193:1193:1193) (1280:1280:1280)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2561:2561:2561) (2633:2633:2633)) + (PORT datac (2429:2429:2429) (2625:2625:2625)) + (PORT datad (1838:1838:1838) (1929:1929:1929)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1982:1982:1982) (2048:2048:2048)) + (PORT datab (2103:2103:2103) (2239:2239:2239)) + (PORT datac (1465:1465:1465) (1540:1540:1540)) + (PORT datad (209:209:209) (246:246:246)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~4) + (DELAY + (ABSOLUTE + (PORT datab (2490:2490:2490) (2690:2690:2690)) + (PORT datac (2152:2152:2152) (2252:2252:2252)) + (PORT datad (1470:1470:1470) (1560:1560:1560)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (722:722:722)) + (PORT datac (1428:1428:1428) (1511:1511:1511)) + (PORT datad (659:659:659) (735:735:735)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~5) + (DELAY + (ABSOLUTE + (PORT datac (590:590:590) (659:659:659)) + (PORT datad (661:661:661) (738:738:738)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~2) + (DELAY + (ABSOLUTE + (PORT datab (1181:1181:1181) (1258:1258:1258)) + (PORT datac (1491:1491:1491) (1604:1604:1604)) + (PORT datad (1204:1204:1204) (1275:1275:1275)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~2) + (DELAY + (ABSOLUTE + (PORT datab (1624:1624:1624) (1780:1780:1780)) + (PORT datad (1680:1680:1680) (1802:1802:1802)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~11) + (DELAY + (ABSOLUTE + (PORT dataa (2561:2561:2561) (2630:2630:2630)) + (PORT datab (2468:2468:2468) (2666:2666:2666)) + (PORT datac (1469:1469:1469) (1544:1544:1544)) + (PORT datad (1838:1838:1838) (1932:1932:1932)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (258:258:258) (308:308:308)) + (PORT datab (897:897:897) (907:907:907)) + (PORT datac (1280:1280:1280) (1332:1332:1332)) + (PORT datad (793:793:793) (839:839:839)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT datab (1654:1654:1654) (1808:1808:1808)) + (PORT datad (1815:1815:1815) (1894:1894:1894)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|table_xx\~0) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (501:501:501)) + (PORT datad (247:247:247) (319:319:319)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1699:1699:1699) (1795:1795:1795)) + (PORT datab (1125:1125:1125) (1202:1202:1202)) + (PORT datac (896:896:896) (937:937:937)) + (PORT datad (1966:1966:1966) (2037:2037:2037)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~0) + (DELAY + (ABSOLUTE + (PORT datac (1044:1044:1044) (1135:1135:1135)) + (PORT datad (1269:1269:1269) (1357:1357:1357)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1067:1067:1067)) + (PORT datab (1506:1506:1506) (1576:1576:1576)) + (PORT datac (1078:1078:1078) (1094:1094:1094)) + (PORT datad (201:201:201) (229:229:229)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~3) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1081:1081:1081)) + (PORT datab (741:741:741) (845:845:845)) + (PORT datac (909:909:909) (983:983:983)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~5) + (DELAY + (ABSOLUTE + (PORT datac (705:705:705) (809:809:809)) + (PORT datad (697:697:697) (796:796:796)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (681:681:681)) + (PORT datab (640:640:640) (663:663:663)) + (PORT datac (341:341:341) (362:362:362)) + (PORT datad (609:609:609) (621:621:621)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (1625:1625:1625) (1667:1667:1667)) + (PORT datad (616:616:616) (648:648:648)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (922:922:922)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datac (1049:1049:1049) (1089:1089:1089)) + (PORT datad (1211:1211:1211) (1321:1321:1321)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~3) + (DELAY + (ABSOLUTE + (PORT datab (745:745:745) (845:845:845)) + (PORT datac (970:970:970) (1032:1032:1032)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT datab (1607:1607:1607) (1747:1747:1747)) + (PORT datad (1859:1859:1859) (1958:1958:1958)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (236:236:236) (286:286:286)) + (PORT datab (1368:1368:1368) (1395:1395:1395)) + (PORT datac (1649:1649:1649) (1746:1746:1746)) + (PORT datad (1692:1692:1692) (1750:1750:1750)) + (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~4) + (DELAY + (ABSOLUTE + (PORT datac (667:667:667) (737:737:737)) + (PORT datad (669:669:669) (753:753:753)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~0) + (DELAY + (ABSOLUTE + (PORT datac (1044:1044:1044) (1136:1136:1136)) + (PORT datad (1269:1269:1269) (1359:1359:1359)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2136:2136:2136) (2306:2306:2306)) + (PORT datab (1472:1472:1472) (1496:1496:1496)) + (PORT datac (1120:1120:1120) (1150:1150:1150)) + (PORT datad (648:648:648) (671:671:671)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1142:1142:1142) (1181:1181:1181)) + (PORT datab (899:899:899) (952:952:952)) + (PORT datac (1409:1409:1409) (1473:1473:1473)) + (PORT datad (637:637:637) (678:678:678)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1859:1859:1859) (1941:1941:1941)) + (PORT datab (1653:1653:1653) (1803:1803:1803)) + (PORT datac (1713:1713:1713) (1796:1796:1796)) + (PORT datad (879:879:879) (896:896:896)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) + (DELAY + (ABSOLUTE + (PORT datab (1578:1578:1578) (1721:1721:1721)) + (PORT datac (1756:1756:1756) (1850:1850:1850)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1417:1417:1417) (1491:1491:1491)) + (PORT datab (1499:1499:1499) (1601:1601:1601)) + (PORT datac (1236:1236:1236) (1278:1278:1278)) + (PORT datad (1212:1212:1212) (1250:1250:1250)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -14911,1393 +2977,14 @@ (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1096:1096:1096) (1139:1139:1139)) - (PORT datab (213:213:213) (256:256:256)) - (PORT datac (1061:1061:1061) (1099:1099:1099)) - (PORT datad (189:189:189) (222:222:222)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) - (DELAY - (ABSOLUTE - (PORT dataa (1618:1618:1618) (1736:1736:1736)) - (PORT datab (867:867:867) (905:905:905)) - (PORT datac (2517:2517:2517) (2622:2622:2622)) - (PORT datad (1493:1493:1493) (1607:1607:1607)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (611:611:611)) - (PORT datab (580:580:580) (593:593:593)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1133:1133:1133) (1184:1184:1184)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~40) - (DELAY - (ABSOLUTE - (PORT datab (652:652:652) (686:686:686)) - (PORT datac (338:338:338) (369:369:369)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (277:277:277)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (1058:1058:1058) (1099:1099:1099)) - (PORT datad (1134:1134:1134) (1161:1161:1161)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) - (DELAY - (ABSOLUTE - (PORT dataa (1157:1157:1157) (1225:1225:1225)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (551:551:551) (564:564:564)) - (PORT datad (399:399:399) (430:430:430)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (169:169:169) (201:201:201)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1138:1138:1138)) - (PORT datab (1105:1105:1105) (1122:1122:1122)) - (PORT datac (1065:1065:1065) (1088:1088:1088)) - (PORT datad (1172:1172:1172) (1217:1217:1217)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) - (DELAY - (ABSOLUTE - (PORT datac (700:700:700) (784:784:784)) - (PORT datad (365:365:365) (386:386:386)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (958:958:958) (1001:1001:1001)) - (PORT datac (681:681:681) (720:720:720)) - (PORT datad (339:339:339) (361:361:361)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[0\]) - (DELAY - (ABSOLUTE - (PORT datac (1006:1006:1006) (1012:1012:1012)) - (PORT datad (924:924:924) (943:943:943)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (179:179:179) (207:207:207)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2096:2096:2096) (2133:2133:2133)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) - (DELAY - (ABSOLUTE - (PORT dataa (1158:1158:1158) (1184:1184:1184)) - (PORT datab (989:989:989) (1022:1022:1022)) - (PORT datac (696:696:696) (778:778:778)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (985:985:985) (1033:1033:1033)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (396:396:396)) - (PORT datab (697:697:697) (726:726:726)) - (PORT datad (1194:1194:1194) (1231:1231:1231)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (740:740:740) (774:774:774)) - (PORT datac (217:217:217) (294:294:294)) - (PORT datad (608:608:608) (657:657:657)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (905:905:905)) - (PORT datab (402:402:402) (425:425:425)) - (PORT datac (194:194:194) (227:227:227)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (244:244:244)) - (PORT datab (959:959:959) (1000:1000:1000)) - (PORT datac (683:683:683) (721:721:721)) - (PORT datad (341:341:341) (359:359:359)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[1\]) - (DELAY - (ABSOLUTE - (PORT datab (396:396:396) (421:421:421)) - (PORT datad (345:345:345) (371:371:371)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT asdata (537:537:537) (568:568:568)) - (PORT clrn (1597:1597:1597) (1572:1572:1572)) - (PORT ena (2143:2143:2143) (2210:2210:2210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1005:1005:1005) (1069:1069:1069)) - (PORT datab (1154:1154:1154) (1178:1178:1178)) - (PORT datac (812:812:812) (866:866:866)) - (PORT datad (359:359:359) (383:383:383)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (443:443:443)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (236:236:236) (311:311:311)) - (PORT datad (327:327:327) (348:348:348)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (716:716:716) (758:758:758)) - (PORT datab (962:962:962) (1001:1001:1001)) - (PORT datac (617:617:617) (670:670:670)) - (PORT datad (532:532:532) (544:544:544)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (553:553:553) (579:579:579)) - (PORT datad (214:214:214) (247:247:247)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (195:195:195) (220:220:220)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1597:1597:1597) (1572:1572:1572)) - (PORT ena (2146:2146:2146) (2210:2210:2210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) - (DELAY - (ABSOLUTE - (PORT dataa (386:386:386) (424:424:424)) - (PORT datab (1154:1154:1154) (1182:1182:1182)) - (PORT datac (966:966:966) (1033:1033:1033)) - (PORT datad (394:394:394) (449:449:449)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (179:179:179) (208:208:208)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (441:441:441)) - (PORT datab (1103:1103:1103) (1121:1121:1121)) - (PORT datac (1068:1068:1068) (1079:1079:1079)) - (PORT datad (1177:1177:1177) (1222:1222:1222)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1182:1182:1182)) - (PORT datab (983:983:983) (1021:1021:1021)) - (PORT datac (960:960:960) (1025:1025:1025)) - (PORT datad (1127:1127:1127) (1138:1138:1138)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (846:846:846) (907:907:907)) - (PORT datab (1376:1376:1376) (1400:1400:1400)) - (PORT datac (695:695:695) (778:778:778)) - (PORT datad (369:369:369) (389:389:389)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) - (DELAY - (ABSOLUTE - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (331:331:331) (357:357:357)) - (PORT datad (244:244:244) (316:316:316)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1394:1394:1394) (1425:1425:1425)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1396:1396:1396) (1427:1427:1427)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (413:413:413) (478:478:478)) - (PORT datab (593:593:593) (633:633:633)) - (PORT datad (219:219:219) (288:288:288)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (815:815:815) (857:857:857)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1407:1407:1407) (1382:1382:1382)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1165:1165:1165) (1197:1197:1197)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (678:678:678)) - (PORT datab (842:842:842) (870:870:870)) - (PORT datad (643:643:643) (672:672:672)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1201:1201:1201) (1243:1243:1243)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1200:1200:1200) (1247:1247:1247)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (705:705:705)) - (PORT datab (245:245:245) (328:328:328)) - (PORT datad (369:369:369) (400:400:400)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (812:812:812) (855:855:855)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1505:1505:1505) (1518:1518:1518)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1168:1168:1168) (1200:1200:1200)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (934:934:934) (963:963:963)) - (PORT datab (606:606:606) (617:617:617)) - (PORT datac (548:548:548) (570:570:570)) - (PORT datad (1519:1519:1519) (1633:1633:1633)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (968:968:968) (1020:1020:1020)) - (PORT datab (580:580:580) (595:595:595)) - (PORT datac (1000:1000:1000) (1021:1021:1021)) - (PORT datad (861:861:861) (896:896:896)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (681:681:681) (737:737:737)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (542:542:542) (562:562:562)) - (PORT datab (612:612:612) (638:638:638)) - (PORT datac (854:854:854) (888:888:888)) - (PORT datad (607:607:607) (635:635:635)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (687:687:687)) - (PORT datab (643:643:643) (681:681:681)) - (PORT datac (1161:1161:1161) (1210:1210:1210)) - (PORT datad (581:581:581) (616:616:616)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (255:255:255)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (603:603:603) (634:634:634)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) - (DELAY - (ABSOLUTE - (PORT datab (1437:1437:1437) (1505:1505:1505)) - (PORT datac (1211:1211:1211) (1273:1273:1273)) - (PORT datad (849:849:849) (886:886:886)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT datab (1435:1435:1435) (1506:1506:1506)) - (PORT datac (1214:1214:1214) (1277:1277:1277)) - (PORT datad (841:841:841) (870:870:870)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) - (DELAY - (ABSOLUTE - (PORT datab (1431:1431:1431) (1499:1499:1499)) - (PORT datac (1202:1202:1202) (1265:1265:1265)) - (PORT datad (842:842:842) (868:868:868)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1009:1009:1009) (1065:1065:1065)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) - (DELAY - (ABSOLUTE - (PORT datab (1431:1431:1431) (1500:1500:1500)) - (PORT datac (1204:1204:1204) (1267:1267:1267)) - (PORT datad (851:851:851) (887:887:887)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1012:1012:1012) (1067:1067:1067)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (523:523:523)) - (PORT datab (490:490:490) (541:541:541)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) - (DELAY - (ABSOLUTE - (PORT datab (1436:1436:1436) (1501:1501:1501)) - (PORT datac (1209:1209:1209) (1271:1271:1271)) - (PORT datad (1072:1072:1072) (1103:1103:1103)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) - (DELAY - (ABSOLUTE - (PORT datab (1436:1436:1436) (1506:1506:1506)) - (PORT datac (1213:1213:1213) (1276:1276:1276)) - (PORT datad (987:987:987) (1036:1036:1036)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1181:1181:1181) (1200:1200:1200)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) - (DELAY - (ABSOLUTE - (PORT datab (1437:1437:1437) (1502:1502:1502)) - (PORT datac (1212:1212:1212) (1275:1275:1275)) - (PORT datad (1074:1074:1074) (1101:1101:1101)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1183:1183:1183) (1203:1203:1203)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) - (DELAY - (ABSOLUTE - (PORT datab (1438:1438:1438) (1503:1503:1503)) - (PORT datac (1218:1218:1218) (1279:1279:1279)) - (PORT datad (985:985:985) (1032:1032:1032)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (988:988:988)) - (PORT datab (242:242:242) (325:325:325)) - (PORT datad (882:882:882) (948:948:948)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) - (DELAY - (ABSOLUTE - (PORT datab (1221:1221:1221) (1292:1292:1292)) - (PORT datac (894:894:894) (941:941:941)) - (PORT datad (886:886:886) (945:945:945)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1204:1204:1204) (1243:1243:1243)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (936:936:936) (997:997:997)) - (PORT datab (1221:1221:1221) (1285:1285:1285)) - (PORT datad (879:879:879) (935:935:935)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1180:1180:1180) (1217:1217:1217)) - (PORT datab (204:204:204) (246:246:246)) - (PORT datac (1821:1821:1821) (1898:1898:1898)) - (PORT datad (203:203:203) (239:239:239)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (899:899:899)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (601:601:601) (662:662:662)) - (PORT datad (870:870:870) (912:912:912)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) - (DELAY - (ABSOLUTE - (PORT dataa (1473:1473:1473) (1527:1527:1527)) - (PORT datac (833:833:833) (838:838:838)) - (PORT datad (1122:1122:1122) (1157:1157:1157)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (981:981:981) (1026:1026:1026)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) - (DELAY - (ABSOLUTE - (PORT dataa (1475:1475:1475) (1527:1527:1527)) - (PORT datac (835:835:835) (838:838:838)) - (PORT datad (1125:1125:1125) (1158:1158:1158)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1083:1083:1083) (1099:1099:1099)) - (PORT datab (1166:1166:1166) (1217:1217:1217)) - (PORT datad (239:239:239) (279:279:279)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (656:656:656) (709:709:709)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) - (DELAY - (ABSOLUTE - (PORT datab (1122:1122:1122) (1149:1149:1149)) - (PORT datac (1397:1397:1397) (1448:1448:1448)) - (PORT datad (822:822:822) (857:857:857)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (987:987:987)) - (PORT datab (1220:1220:1220) (1288:1288:1288)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (403:403:403) (454:454:454)) - (PORT datab (944:944:944) (1025:1025:1025)) - (PORT datac (1146:1146:1146) (1186:1186:1186)) - (PORT datad (666:666:666) (686:686:686)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) - (DELAY - (ABSOLUTE - (PORT datac (1438:1438:1438) (1484:1484:1484)) - (PORT datad (1123:1123:1123) (1155:1155:1155)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1170:1170:1170) (1265:1265:1265)) - (PORT datab (813:813:813) (832:832:832)) - (PORT datac (1134:1134:1134) (1171:1171:1171)) - (PORT datad (664:664:664) (713:713:713)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1504:1504:1504) (1545:1545:1545)) - (PORT ena (1131:1131:1131) (1098:1098:1098)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) - (DELAY - (ABSOLUTE - (PORT datab (1121:1121:1121) (1148:1148:1148)) - (PORT datac (1398:1398:1398) (1447:1447:1447)) - (PORT datad (821:821:821) (856:856:856)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (453:453:453)) - (PORT datab (887:887:887) (923:923:923)) - (PORT datad (364:364:364) (388:388:388)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) - (DELAY - (ABSOLUTE - (PORT dataa (408:408:408) (464:464:464)) - (PORT datab (1404:1404:1404) (1437:1437:1437)) - (PORT datac (1139:1139:1139) (1179:1179:1179)) - (PORT datad (663:663:663) (683:683:683)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1146:1146:1146) (1180:1180:1180)) - (PORT datab (815:815:815) (833:833:833)) - (PORT datac (1143:1143:1143) (1180:1180:1180)) - (PORT datad (671:671:671) (721:721:721)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1782:1782:1782) (1906:1906:1906)) - (PORT datab (973:973:973) (1022:1022:1022)) - (PORT datac (1471:1471:1471) (1489:1489:1489)) - (PORT datad (1978:1978:1978) (2013:2013:2013)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (660:660:660)) - (PORT datab (1249:1249:1249) (1275:1275:1275)) - (PORT datac (1822:1822:1822) (1900:1900:1900)) - (PORT datad (1106:1106:1106) (1134:1134:1134)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (687:687:687)) - (PORT datab (905:905:905) (971:971:971)) - (PORT datac (861:861:861) (888:888:888)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) (DELAY (ABSOLUTE (PORT dataa (208:208:208) (256:256:256)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1153:1153:1153) (1178:1178:1178)) - (PORT datad (204:204:204) (241:241:241)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT datab (1120:1120:1120) (1175:1175:1175)) + (PORT datac (1695:1695:1695) (1735:1735:1735)) + (PORT datad (989:989:989) (1018:1018:1018)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16305,134 +2992,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) + (INSTANCE z80_\|pla_decode_\|Equal19\~0) (DELAY (ABSOLUTE - (PORT dataa (713:713:713) (766:766:766)) - (PORT datab (205:205:205) (245:245:245)) - (PORT datac (346:346:346) (370:370:370)) - (PORT datad (1145:1145:1145) (1176:1176:1176)) + (PORT dataa (889:889:889) (948:948:948)) + (PORT datab (683:683:683) (708:708:708)) + (PORT datac (2084:2084:2084) (2256:2256:2256)) + (PORT datad (909:909:909) (931:931:931)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) - (DELAY - (ABSOLUTE - (PORT datab (922:922:922) (944:944:944)) - (PORT datac (595:595:595) (615:615:615)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (900:900:900)) - (PORT datac (1144:1144:1144) (1163:1163:1163)) - (PORT datad (832:832:832) (861:861:861)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1506:1506:1506) (1545:1545:1545)) - (PORT ena (1261:1261:1261) (1299:1299:1299)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) - (DELAY - (ABSOLUTE - (PORT dataa (874:874:874) (899:899:899)) - (PORT datac (1138:1138:1138) (1159:1159:1159)) - (PORT datad (835:835:835) (861:861:861)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1100:1100:1100) (1149:1149:1149)) - (PORT datab (1280:1280:1280) (1386:1386:1386)) - (PORT datad (842:842:842) (869:869:869)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (693:693:693)) - (PORT datab (1259:1259:1259) (1346:1346:1346)) - (PORT datac (1146:1146:1146) (1187:1187:1187)) - (PORT datad (374:374:374) (412:412:412)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (990:990:990) (1035:1035:1035)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) + (INSTANCE z80_\|pla_decode_\|Equal34\~0) (DELAY (ABSOLUTE - (PORT dataa (404:404:404) (462:462:462)) - (PORT datab (1258:1258:1258) (1341:1341:1341)) - (PORT datac (1142:1142:1142) (1186:1186:1186)) - (PORT datad (664:664:664) (686:686:686)) + (PORT dataa (1700:1700:1700) (1791:1791:1791)) + (PORT datab (250:250:250) (300:300:300)) + (PORT datac (899:899:899) (937:937:937)) + (PORT datad (928:928:928) (989:989:989)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -16442,1198 +3024,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) + (INSTANCE z80_\|execute_\|comb\~0) (DELAY (ABSOLUTE - (PORT dataa (639:639:639) (696:696:696)) - (PORT datab (1255:1255:1255) (1339:1339:1339)) - (PORT datac (1141:1141:1141) (1184:1184:1184)) - (PORT datad (375:375:375) (413:413:413)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (989:989:989) (1035:1035:1035)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (402:402:402) (457:457:457)) - (PORT datab (1258:1258:1258) (1344:1344:1344)) - (PORT datac (1146:1146:1146) (1187:1187:1187)) - (PORT datad (666:666:666) (682:682:682)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (1659:1659:1659) (1811:1811:1811)) + (PORT datad (1814:1814:1814) (1891:1891:1891)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~42) + (INSTANCE z80_\|pla_decode_\|Equal47\~0) (DELAY (ABSOLUTE - (PORT dataa (423:423:423) (485:485:485)) - (PORT datab (1600:1600:1600) (1653:1653:1653)) - (PORT datad (1181:1181:1181) (1221:1221:1221)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (634:634:634)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (787:787:787) (785:785:785)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (623:623:623) (653:653:653)) - (PORT datab (336:336:336) (368:368:368)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (626:626:626) (642:642:642)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (988:988:988)) - (PORT datab (218:218:218) (257:257:257)) - (PORT datac (618:618:618) (661:661:661)) - (PORT datad (787:787:787) (791:791:791)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1064:1064:1064) (1103:1103:1103)) - (PORT datab (836:836:836) (868:868:868)) - (PORT datac (218:218:218) (261:261:261)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (671:671:671)) - (PORT datab (834:834:834) (892:892:892)) - (PORT datac (174:174:174) (207:207:207)) - (PORT datad (874:874:874) (899:899:899)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1547:1547:1547) (1564:1564:1564)) - (PORT datab (851:851:851) (910:910:910)) - (PORT datac (1130:1130:1130) (1151:1151:1151)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) - (DELAY - (ABSOLUTE - (PORT dataa (1308:1308:1308) (1399:1399:1399)) - (PORT datac (1141:1141:1141) (1164:1164:1164)) - (PORT datad (832:832:832) (866:866:866)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1187:1187:1187) (1229:1229:1229)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1186:1186:1186) (1227:1227:1227)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (460:460:460) (523:523:523)) - (PORT datab (492:492:492) (541:541:541)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1950:1950:1950) (1996:1996:1996)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (937:937:937) (991:991:991)) - (PORT datab (1222:1222:1222) (1291:1291:1291)) - (PORT datad (879:879:879) (935:935:935)) + (PORT dataa (1700:1700:1700) (1795:1795:1795)) + (PORT datab (250:250:250) (298:298:298)) + (PORT datac (898:898:898) (934:934:934)) + (PORT datad (1153:1153:1153) (1208:1208:1208)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (545:545:545) (579:579:579)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1716:1716:1716) (1767:1767:1767)) - (PORT ena (1261:1261:1261) (1299:1299:1299)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1098:1098:1098) (1151:1151:1151)) - (PORT datab (648:648:648) (728:728:728)) - (PORT datad (845:845:845) (876:876:876)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (2219:2219:2219) (2260:2260:2260)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (881:881:881)) - (PORT datab (1166:1166:1166) (1218:1218:1218)) - (PORT datad (240:240:240) (280:280:280)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1976:1976:1976) (2020:2020:2020)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1977:1977:1977) (2023:2023:2023)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (466:466:466)) - (PORT datab (1593:1593:1593) (1643:1643:1643)) - (PORT datad (1180:1180:1180) (1216:1216:1216)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1715:1715:1715) (1766:1766:1766)) - (PORT ena (1131:1131:1131) (1098:1098:1098)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1611:1611:1611) (1650:1650:1650)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (433:433:433)) - (PORT datab (886:886:886) (923:923:923)) - (PORT datad (859:859:859) (925:925:925)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (632:632:632) (649:649:649)) - (PORT datac (338:338:338) (358:358:358)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (2372:2372:2372) (2423:2423:2423)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (2371:2371:2371) (2423:2423:2423)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (926:926:926) (986:986:986)) - (PORT datab (911:911:911) (986:986:986)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (672:672:672)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (596:596:596) (613:613:613)) - (PORT datad (313:313:313) (323:323:323)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (944:944:944)) - (PORT datab (543:543:543) (563:563:563)) - (PORT datac (1049:1049:1049) (1102:1102:1102)) - (PORT datad (1297:1297:1297) (1338:1338:1338)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (911:911:911)) - (PORT datac (1138:1138:1138) (1159:1159:1159)) - (PORT datad (844:844:844) (869:869:869)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (909:909:909)) - (PORT datac (1140:1140:1140) (1164:1164:1164)) - (PORT datad (844:844:844) (871:871:871)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (1391:1391:1391) (1443:1443:1443)) - (PORT ena (935:935:935) (924:924:924)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1171:1171:1171) (1195:1195:1195)) - (PORT datab (835:835:835) (855:855:855)) - (PORT datac (1143:1143:1143) (1163:1163:1163)) - (PORT datad (844:844:844) (868:868:868)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (276:276:276)) - (PORT datab (409:409:409) (450:450:450)) - (PORT datad (382:382:382) (419:419:419)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) - (DELAY - (ABSOLUTE - (PORT dataa (1308:1308:1308) (1398:1398:1398)) - (PORT datac (1141:1141:1141) (1165:1165:1165)) - (PORT datad (832:832:832) (866:866:866)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datac (762:762:762) (815:815:815)) - (PORT datad (642:642:642) (666:666:666)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (239:239:239) (292:292:292)) - (PORT datab (235:235:235) (277:277:277)) - (PORT datac (1097:1097:1097) (1113:1113:1113)) - (PORT datad (212:212:212) (246:246:246)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (418:418:418) (508:508:508)) - (PORT datab (279:279:279) (364:364:364)) - (PORT datac (1332:1332:1332) (1337:1337:1337)) - (PORT datad (184:184:184) (216:216:216)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (842:842:842) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (951:951:951) (975:975:975)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (951:951:951) (974:974:974)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (978:978:978)) - (PORT datab (914:914:914) (989:989:989)) - (PORT datad (214:214:214) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1393:1393:1393) (1432:1432:1432)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1390:1390:1390) (1429:1429:1429)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (517:517:517)) - (PORT datab (496:496:496) (537:537:537)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1278:1278:1278) (1308:1308:1308)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1278:1278:1278) (1306:1306:1306)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (458:458:458)) - (PORT datab (1599:1599:1599) (1646:1646:1646)) - (PORT datad (1181:1181:1181) (1215:1215:1215)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1228:1228:1228) (1277:1277:1277)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1058:1058:1058) (1070:1070:1070)) - (PORT datab (1167:1167:1167) (1216:1216:1216)) - (PORT datad (237:237:237) (277:277:277)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (810:810:810) (862:862:862)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1214:1214:1214) (1210:1210:1210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1259:1259:1259) (1290:1290:1290)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (243:243:243) (289:289:289)) - (PORT datad (875:875:875) (901:901:901)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (689:689:689) (709:709:709)) - (PORT ena (1404:1404:1404) (1382:1382:1382)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1474:1474:1474) (1488:1488:1488)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1058:1058:1058) (1072:1072:1072)) - (PORT datab (1270:1270:1270) (1360:1360:1360)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (838:838:838) (872:872:872)) - (PORT datab (1030:1030:1030) (1072:1072:1072)) - (PORT datac (803:803:803) (856:856:856)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (969:969:969) (986:986:986)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (986:986:986)) - (PORT datab (1221:1221:1221) (1292:1292:1292)) - (PORT datad (887:887:887) (945:945:945)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (380:380:380) (429:429:429)) - (PORT datab (829:829:829) (880:880:880)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (558:558:558) (582:582:582)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (834:834:834) (864:864:864)) - (PORT datab (867:867:867) (903:903:903)) - (PORT datac (808:808:808) (862:862:862)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT asdata (881:881:881) (888:888:888)) - (PORT ena (940:940:940) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (288:288:288)) - (PORT datab (905:905:905) (941:941:941)) - (PORT datad (211:211:211) (245:245:245)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (288:288:288)) - (PORT datac (214:214:214) (290:290:290)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1135:1135:1135) (1153:1153:1153)) - (PORT datab (827:827:827) (837:837:837)) - (PORT datac (199:199:199) (234:234:234)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[8\]) - (DELAY - (ABSOLUTE - (PORT dataa (688:688:688) (733:733:733)) - (PORT datac (799:799:799) (817:817:817)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2152:2152:2152) (2220:2220:2220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (422:422:422) (513:513:513)) - (PORT datab (280:280:280) (369:369:369)) - (PORT datac (1329:1329:1329) (1334:1334:1334)) - (PORT datad (189:189:189) (221:221:221)) - (IOPATH dataa combout (301:301:301) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) - (DELAY - (ABSOLUTE - (PORT datac (248:248:248) (337:337:337)) - (PORT datad (324:324:324) (346:346:346)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (712:712:712) (756:756:756)) - (PORT datac (810:810:810) (842:842:842)) - (PORT datad (578:578:578) (586:586:586)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -17641,672 +3052,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[9\]) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) (DELAY (ABSOLUTE - (PORT datab (355:355:355) (385:385:385)) - (PORT datac (880:880:880) (911:911:911)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[9\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (554:554:554) (561:561:561)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2096:2096:2096) (2133:2133:2133)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (268:268:268) (364:364:364)) - (PORT datab (279:279:279) (374:374:374)) - (PORT datac (1335:1335:1335) (1349:1349:1349)) - (PORT datad (325:325:325) (343:343:343)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (1678:1678:1678) (1695:1695:1695)) + (PORT datab (1374:1374:1374) (1396:1396:1396)) + (PORT datac (2514:2514:2514) (2557:2557:2557)) + (PORT datad (1128:1128:1128) (1145:1145:1145)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1106:1106:1106) (1145:1145:1145)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1107:1107:1107) (1146:1146:1146)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~32) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) (DELAY (ABSOLUTE - (PORT dataa (921:921:921) (980:980:980)) - (PORT datab (914:914:914) (982:982:982)) - (PORT datad (216:216:216) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1947:1947:1947) (2004:2004:2004)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (812:812:812) (827:827:827)) - (PORT datab (1168:1168:1168) (1216:1216:1216)) - (PORT datad (240:240:240) (281:281:281)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1439:1439:1439) (1508:1508:1508)) - (PORT ena (1131:1131:1131) (1098:1098:1098)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (778:778:778) (850:850:850)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (433:433:433)) - (PORT datab (886:886:886) (923:923:923)) - (PORT datad (350:350:350) (406:406:406)) + (PORT dataa (889:889:889) (940:940:940)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datac (1113:1113:1113) (1189:1189:1189)) + (PORT datad (961:961:961) (1053:1053:1053)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1005:1005:1005) (1055:1055:1055)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1994:1994:1994) (2075:2075:2075)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (568:568:568) (641:641:641)) - (PORT datab (1599:1599:1599) (1649:1649:1649)) - (PORT datad (1179:1179:1179) (1219:1219:1219)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1439:1439:1439) (1506:1506:1506)) - (PORT ena (1261:1261:1261) (1299:1299:1299)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1100:1100:1100) (1147:1147:1147)) - (PORT datab (678:678:678) (753:753:753)) - (PORT datad (849:849:849) (878:878:878)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (653:653:653)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (599:599:599) (617:617:617)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (2176:2176:2176) (2269:2269:2269)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (2177:2177:2177) (2273:2273:2273)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (524:524:524)) - (PORT datab (243:243:243) (326:326:326)) - (PORT datad (454:454:454) (497:497:497)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (2201:2201:2201) (2285:2285:2285)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (990:990:990)) - (PORT datab (1220:1220:1220) (1290:1290:1290)) - (PORT datad (884:884:884) (941:941:941)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (773:773:773) (837:837:837)) - (PORT datab (560:560:560) (597:597:597)) - (PORT datac (558:558:558) (555:555:555)) - (PORT datad (850:850:850) (877:877:877)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (909:909:909)) - (PORT datab (396:396:396) (421:421:421)) - (PORT datac (848:848:848) (907:907:907)) - (PORT datad (1297:1297:1297) (1337:1337:1337)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT asdata (545:545:545) (579:579:579)) - (PORT ena (940:940:940) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1897:1897:1897) (1987:1987:1987)) - (PORT datab (235:235:235) (281:281:281)) - (PORT datad (211:211:211) (246:246:246)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (842:842:842) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (287:287:287)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datad (354:354:354) (413:413:413)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1139:1139:1139) (1156:1156:1156)) - (PORT datab (545:545:545) (561:561:561)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[10\]) - (DELAY - (ABSOLUTE - (PORT datac (200:200:200) (235:235:235)) - (PORT datad (869:869:869) (899:899:899)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[10\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (531:531:531) (546:546:546)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2096:2096:2096) (2133:2133:2133)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (270:270:270) (368:368:368)) - (PORT datab (276:276:276) (370:370:370)) - (PORT datac (1338:1338:1338) (1352:1352:1352)) - (PORT datad (324:324:324) (345:345:345)) - (IOPATH dataa combout (301:301:301) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[11\]) - (DELAY - (ABSOLUTE - (PORT datab (602:602:602) (632:632:632)) - (PORT datad (924:924:924) (945:945:945)) (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2096:2096:2096) (2133:2133:2133)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datac (568:568:568) (632:632:632)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (738:738:738) (772:772:772)) - (PORT ena (935:935:935) (924:924:924)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (407:407:407) (446:446:446)) - (PORT datad (388:388:388) (422:422:422)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (335:335:335)) - (PORT datac (823:823:823) (870:870:870)) - (PORT datad (639:639:639) (664:664:664)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (565:565:565) (577:577:577)) - (PORT datab (846:846:846) (883:883:883)) - (PORT datac (679:679:679) (728:728:728)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18314,106 +3084,69 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~48) + (INSTANCE z80_\|sequencer_\|M5\~0) (DELAY (ABSOLUTE - (PORT dataa (612:612:612) (644:644:644)) - (PORT datab (820:820:820) (880:880:880)) - (PORT datac (393:393:393) (430:430:430)) - (PORT datad (1301:1301:1301) (1333:1333:1333)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (872:872:872) (916:916:916)) - (PORT datab (223:223:223) (272:272:272)) - (PORT datac (1159:1159:1159) (1203:1203:1203)) - (PORT datad (607:607:607) (634:634:634)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) - (DELAY - (ABSOLUTE - (PORT dataa (1004:1004:1004) (1068:1068:1068)) - (PORT datab (2092:2092:2092) (2152:2152:2152)) - (PORT datac (686:686:686) (739:739:739)) - (PORT datad (1737:1737:1737) (1857:1857:1857)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT datab (964:964:964) (1009:1009:1009)) - (PORT datac (1166:1166:1166) (1163:1163:1163)) - (PORT datad (680:680:680) (717:717:717)) + (PORT dataa (442:442:442) (510:510:510)) + (PORT datab (706:706:706) (761:761:761)) + (PORT datad (892:892:892) (915:915:915)) + (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[3\]) + (INSTANCE z80_\|sequencer_\|M5) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) + (PORT clk (1525:1525:1525) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[3\]\~3) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) (DELAY (ABSOLUTE - (PORT datab (652:652:652) (711:711:711)) - (PORT datac (647:647:647) (707:707:707)) - (PORT datad (634:634:634) (661:661:661)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (980:980:980) (1079:1079:1079)) + (PORT datac (670:670:670) (776:776:776)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (2272:2272:2272) (2458:2458:2458)) + (PORT datad (1247:1247:1247) (1340:1340:1340)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) (DELAY (ABSOLUTE - (PORT dataa (638:638:638) (713:713:713)) - (PORT datab (641:641:641) (708:708:708)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (575:575:575) (599:599:599)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (643:643:643) (677:677:677)) + (PORT datab (1376:1376:1376) (1393:1393:1393)) + (PORT datac (1649:1649:1649) (1659:1659:1659)) + (PORT datad (908:908:908) (928:928:928)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -18422,15 +3155,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) + (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) (DELAY (ABSOLUTE - (PORT dataa (1127:1127:1127) (1169:1169:1169)) - (PORT datab (1268:1268:1268) (1379:1379:1379)) - (PORT datac (613:613:613) (634:634:634)) - (PORT datad (1131:1131:1131) (1134:1134:1134)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (890:890:890) (938:938:938)) + (PORT datab (348:348:348) (377:377:377)) + (PORT datac (614:614:614) (637:637:637)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18438,29 +3171,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) + (INSTANCE z80_\|execute_\|ctl_mRead\~4) (DELAY (ABSOLUTE - (PORT dataa (2003:2003:2003) (2192:2192:2192)) - (PORT datab (1271:1271:1271) (1346:1346:1346)) - (PORT datac (994:994:994) (1035:1035:1035)) - (PORT datad (1461:1461:1461) (1531:1531:1531)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1013:1013:1013) (1048:1048:1048)) - (PORT datab (1598:1598:1598) (1713:1713:1713)) - (PORT datac (1145:1145:1145) (1147:1147:1147)) - (PORT datad (654:654:654) (698:698:698)) + (PORT dataa (1325:1325:1325) (1382:1382:1382)) + (PORT datab (967:967:967) (991:991:991)) + (PORT datac (1402:1402:1402) (1542:1542:1542)) + (PORT datad (1180:1180:1180) (1240:1240:1240)) (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -18470,31 +3187,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~5) + (INSTANCE z80_\|execute_\|ctl_ir_we\~5) (DELAY (ABSOLUTE - (PORT dataa (2564:2564:2564) (2702:2702:2702)) - (PORT datab (1558:1558:1558) (1680:1680:1680)) - (PORT datac (866:866:866) (908:908:908)) - (PORT datad (191:191:191) (224:224:224)) + (PORT datab (260:260:260) (343:343:343)) + (PORT datac (234:234:234) (310:310:310)) + (PORT datad (391:391:391) (462:462:462)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (475:475:475) (503:503:503)) + (PORT datab (1696:1696:1696) (1768:1768:1768)) + (PORT datac (1831:1831:1831) (1963:1963:1963)) + (PORT datad (780:780:780) (842:842:842)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (475:475:475) (504:504:504)) + (PORT datab (1697:1697:1697) (1767:1767:1767)) + (PORT datac (1832:1832:1832) (1964:1964:1964)) + (PORT datad (781:781:781) (840:840:840)) (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (411:411:411)) - (PORT datab (804:804:804) (851:851:851)) - (PORT datac (829:829:829) (862:862:862)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18502,15 +3233,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) + (INSTANCE z80_\|execute_\|ctl_ir_we\~7) (DELAY (ABSOLUTE - (PORT dataa (647:647:647) (668:668:668)) - (PORT datab (1164:1164:1164) (1226:1226:1226)) - (PORT datac (562:562:562) (562:562:562)) - (PORT datad (595:595:595) (626:626:626)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (479:479:479) (505:505:505)) + (PORT datab (1700:1700:1700) (1770:1770:1770)) + (PORT datac (1842:1842:1842) (1975:1975:1975)) + (PORT datad (787:787:787) (845:845:845)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1450:1450:1450) (1501:1501:1501)) + (PORT datab (641:641:641) (679:679:679)) + (PORT datac (647:647:647) (693:693:693)) + (PORT datad (648:648:648) (679:679:679)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18518,149 +3265,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~5) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~97) (DELAY (ABSOLUTE - (PORT dataa (588:588:588) (616:616:616)) - (PORT datab (1125:1125:1125) (1173:1173:1173)) - (PORT datac (561:561:561) (579:579:579)) - (PORT datad (905:905:905) (952:952:952)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (702:702:702) (774:774:774)) + (PORT datab (1409:1409:1409) (1519:1519:1519)) + (PORT datac (1370:1370:1370) (1480:1480:1480)) + (PORT datad (682:682:682) (744:744:744)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~6) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~96) (DELAY (ABSOLUTE - (PORT dataa (258:258:258) (332:332:332)) - (PORT datac (170:170:170) (202:202:202)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) - (DELAY - (ABSOLUTE - (PORT dataa (263:263:263) (339:339:339)) - (PORT datac (1090:1090:1090) (1144:1144:1144)) - (PORT datad (902:902:902) (951:951:951)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT datab (968:968:968) (1010:1010:1010)) - (PORT datac (370:370:370) (404:404:404)) - (PORT datad (675:675:675) (715:715:715)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (733:733:733)) - (PORT datab (1128:1128:1128) (1182:1182:1182)) - (PORT datac (588:588:588) (620:620:620)) - (PORT datad (380:380:380) (439:439:439)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1172:1172:1172) (1272:1272:1272)) + (PORT datab (969:969:969) (1014:1014:1014)) + (PORT datac (672:672:672) (779:779:779)) + (PORT datad (693:693:693) (794:794:794)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~98) (DELAY (ABSOLUTE - (PORT dataa (264:264:264) (340:340:340)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (556:556:556) (578:578:578)) - (PORT datad (900:900:900) (949:949:949)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1468:1468:1468) (1479:1479:1479)) - (PORT datab (1497:1497:1497) (1572:1572:1572)) - (PORT datac (1847:1847:1847) (1915:1915:1915)) - (PORT datad (402:402:402) (438:438:438)) + (PORT dataa (1401:1401:1401) (1407:1407:1407)) + (PORT datab (1154:1154:1154) (1254:1254:1254)) + (PORT datac (671:671:671) (779:779:779)) + (PORT datad (693:693:693) (794:794:794)) (IOPATH dataa combout (325:325:325) (328:328:328)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -18670,251 +3313,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~20) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) (DELAY (ABSOLUTE - (PORT dataa (1433:1433:1433) (1518:1518:1518)) - (PORT datab (1643:1643:1643) (1769:1769:1769)) - (PORT datac (1052:1052:1052) (1102:1102:1102)) - (PORT datad (1294:1294:1294) (1385:1385:1385)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (2512:2512:2512) (2579:2579:2579)) + (PORT datab (239:239:239) (277:277:277)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (1711:1711:1711) (1689:1689:1689)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~12) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) (DELAY (ABSOLUTE - (PORT dataa (885:885:885) (898:898:898)) - (PORT datab (943:943:943) (983:983:983)) - (PORT datac (858:858:858) (877:877:877)) - (PORT datad (654:654:654) (664:664:664)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) - (DELAY - (ABSOLUTE - (PORT dataa (480:480:480) (518:518:518)) - (PORT datab (1187:1187:1187) (1249:1249:1249)) - (PORT datac (925:925:925) (1011:1011:1011)) - (PORT datad (1383:1383:1383) (1482:1482:1482)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal61\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1746:1746:1746) (1869:1869:1869)) - (PORT datab (1375:1375:1375) (1426:1426:1426)) - (PORT datac (1591:1591:1591) (1672:1672:1672)) - (PORT datad (1495:1495:1495) (1627:1627:1627)) + (PORT dataa (861:861:861) (935:935:935)) + (PORT datab (348:348:348) (381:381:381)) + (PORT datad (336:336:336) (362:362:362)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) + (INSTANCE z80_\|execute_\|fMWrite\~1) (DELAY (ABSOLUTE - (PORT datab (1828:1828:1828) (1926:1926:1926)) - (PORT datac (1699:1699:1699) (1792:1792:1792)) - (PORT datad (926:926:926) (994:994:994)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1872:1872:1872) (1889:1889:1889)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (880:880:880) (886:886:886)) - (PORT datad (803:803:803) (814:814:814)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1342:1342:1342) (1440:1440:1440)) - (PORT datab (1765:1765:1765) (1873:1873:1873)) - (PORT datac (1447:1447:1447) (1536:1536:1536)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1520:1520:1520) (1609:1609:1609)) - (PORT datab (925:925:925) (988:988:988)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (203:203:203) (232:232:232)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (262:262:262)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (177:177:177) (214:214:214)) - (PORT datad (182:182:182) (212:212:212)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1766:1766:1766) (1808:1808:1808)) - (PORT datab (836:836:836) (862:862:862)) - (PORT datac (1306:1306:1306) (1421:1421:1421)) - (PORT datad (2555:2555:2555) (2677:2677:2677)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) - (DELAY - (ABSOLUTE - (PORT dataa (582:582:582) (614:614:614)) - (PORT datab (246:246:246) (286:286:286)) - (PORT datac (221:221:221) (257:257:257)) - (PORT datad (904:904:904) (976:976:976)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1051:1051:1051) (1075:1075:1075)) - (PORT datab (1615:1615:1615) (1655:1655:1655)) - (PORT datac (1187:1187:1187) (1227:1227:1227)) - (PORT datad (1742:1742:1742) (1769:1769:1769)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal71\~2) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (921:921:921)) - (PORT datab (941:941:941) (1014:1014:1014)) - (PORT datac (219:219:219) (254:254:254)) - (PORT datad (903:903:903) (974:974:974)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (258:258:258)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1219:1219:1219) (1272:1272:1272)) - (PORT datab (227:227:227) (268:268:268)) - (PORT datac (2061:2061:2061) (2171:2171:2171)) - (PORT datad (1409:1409:1409) (1503:1503:1503)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (718:718:718)) - (PORT datab (1484:1484:1484) (1542:1542:1542)) - (PORT datac (1486:1486:1486) (1511:1511:1511)) - (PORT datad (640:640:640) (654:654:654)) + (PORT dataa (1633:1633:1633) (1765:1765:1765)) + (PORT datab (1559:1559:1559) (1648:1648:1648)) + (PORT datac (1677:1677:1677) (1756:1756:1756)) + (PORT datad (1743:1743:1743) (1852:1852:1852)) (IOPATH dataa combout (341:341:341) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -18924,384 +3359,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla25M1T1_3) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) (DELAY (ABSOLUTE - (PORT dataa (837:837:837) (857:857:857)) - (PORT datab (1485:1485:1485) (1542:1542:1542)) - (PORT datac (1608:1608:1608) (1613:1613:1613)) - (PORT datad (1444:1444:1444) (1563:1563:1563)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (213:213:213) (257:257:257)) - (PORT datac (838:838:838) (870:870:870)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (341:341:341) (319:319:319)) + (PORT dataa (1155:1155:1155) (1190:1190:1190)) + (PORT datab (1492:1492:1492) (1531:1531:1531)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (1070:1070:1070) (1092:1092:1092)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal72\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1402:1402:1402) (1477:1477:1477)) - (PORT datab (2359:2359:2359) (2492:2492:2492)) - (PORT datac (1132:1132:1132) (1171:1171:1171)) - (PORT datad (855:855:855) (857:857:857)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal73\~2) - (DELAY - (ABSOLUTE - (PORT dataa (2002:2002:2002) (2149:2149:2149)) - (PORT datab (1120:1120:1120) (1189:1189:1189)) - (PORT datac (1350:1350:1350) (1403:1403:1403)) - (PORT datad (855:855:855) (872:872:872)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (975:975:975) (1049:1049:1049)) - (PORT datab (960:960:960) (1047:1047:1047)) - (PORT datac (1782:1782:1782) (1803:1803:1803)) - (PORT datad (1450:1450:1450) (1533:1533:1533)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1044:1044:1044) (1059:1059:1059)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (616:616:616) (640:640:640)) - (PORT datad (601:601:601) (613:613:613)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1518:1518:1518) (1586:1586:1586)) - (PORT datab (1962:1962:1962) (1991:1991:1991)) - (PORT datac (1263:1263:1263) (1313:1313:1313)) - (PORT datad (933:933:933) (1002:1002:1002)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) - (DELAY - (ABSOLUTE - (PORT datab (864:864:864) (893:893:893)) - (PORT datac (819:819:819) (853:853:853)) - (PORT datad (811:811:811) (845:845:845)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (2565:2565:2565) (2704:2704:2704)) - (PORT datac (1529:1529:1529) (1648:1648:1648)) - (PORT datad (1533:1533:1533) (1667:1667:1667)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (304:304:304)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datac (1176:1176:1176) (1212:1212:1212)) - (PORT datad (191:191:191) (224:224:224)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (808:808:808) (859:859:859)) - (PORT datab (618:618:618) (647:647:647)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (802:802:802) (881:881:881)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~15) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (957:957:957)) - (PORT datac (824:824:824) (856:856:856)) - (PORT datad (647:647:647) (680:680:680)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~16) - (DELAY - (ABSOLUTE - (PORT dataa (912:912:912) (960:960:960)) - (PORT datab (362:362:362) (394:394:394)) - (PORT datac (591:591:591) (619:619:619)) - (PORT datad (338:338:338) (357:357:357)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) - (DELAY - (ABSOLUTE - (PORT datac (891:891:891) (933:933:933)) - (PORT datad (831:831:831) (843:843:843)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (649:649:649)) - (PORT datab (1105:1105:1105) (1114:1114:1114)) - (PORT datac (753:753:753) (781:781:781)) - (PORT datad (613:613:613) (631:631:631)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (917:917:917) (942:942:942)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2002:2002:2002) (2062:2062:2062)) - (PORT datab (228:228:228) (270:270:270)) - (PORT datac (1707:1707:1707) (1823:1823:1823)) - (PORT datad (1505:1505:1505) (1539:1539:1539)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1137:1137:1137) (1211:1211:1211)) - (PORT datab (1568:1568:1568) (1705:1705:1705)) - (PORT datac (2532:2532:2532) (2663:2663:2663)) - (PORT datad (189:189:189) (222:222:222)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1005:1005:1005) (1063:1063:1063)) - (PORT datab (1299:1299:1299) (1349:1349:1349)) - (PORT datac (890:890:890) (914:914:914)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (665:665:665)) - (PORT datab (2303:2303:2303) (2383:2383:2383)) - (PORT datac (2057:2057:2057) (2199:2199:2199)) - (PORT datad (1163:1163:1163) (1186:1186:1186)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (640:640:640)) - (PORT datab (608:608:608) (638:638:638)) - (PORT datac (549:549:549) (557:557:557)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1025:1025:1025) (1068:1068:1068)) - (PORT datab (2030:2030:2030) (2166:2166:2166)) - (PORT datac (821:821:821) (831:831:831)) - (PORT datad (2503:2503:2503) (2629:2629:2629)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1546:1546:1546) (1624:1624:1624)) - (PORT datab (938:938:938) (1017:1017:1017)) - (PORT datac (601:601:601) (662:662:662)) - (PORT datad (580:580:580) (585:585:585)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (920:920:920)) - (PORT datab (220:220:220) (258:258:258)) - (PORT datac (666:666:666) (685:685:685)) + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (781:781:781) (835:835:835)) + (PORT datac (973:973:973) (1029:1029:1029)) (PORT datad (173:173:173) (198:198:198)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) @@ -19312,187 +3389,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) + (INSTANCE z80_\|execute_\|ctl_mRead\~6) (DELAY (ABSOLUTE - (PORT dataa (658:658:658) (680:680:680)) - (PORT datab (1172:1172:1172) (1198:1198:1198)) - (PORT datac (636:636:636) (693:693:693)) - (PORT datad (307:307:307) (324:324:324)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (694:694:694)) - (PORT datab (806:806:806) (876:876:876)) - (PORT datac (1101:1101:1101) (1130:1130:1130)) - (PORT datad (589:589:589) (627:627:627)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (667:667:667)) - (PORT datab (654:654:654) (679:679:679)) - (PORT datac (936:936:936) (1033:1033:1033)) - (PORT datad (830:830:830) (861:861:861)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1518:1518:1518) (1588:1588:1588)) - (PORT datab (1051:1051:1051) (1075:1075:1075)) - (PORT datac (1263:1263:1263) (1316:1316:1316)) - (PORT datad (930:930:930) (999:999:999)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1452:1452:1452) (1482:1482:1482)) - (PORT datab (1142:1142:1142) (1181:1181:1181)) - (PORT datac (1196:1196:1196) (1287:1287:1287)) - (PORT datad (1139:1139:1139) (1160:1160:1160)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (646:646:646)) - (PORT datab (1014:1014:1014) (1076:1076:1076)) - (PORT datac (798:798:798) (807:807:807)) - (PORT datad (619:619:619) (632:632:632)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (276:276:276)) - (PORT datab (1030:1030:1030) (1067:1067:1067)) - (PORT datac (871:871:871) (866:866:866)) - (PORT datad (599:599:599) (614:614:614)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (619:619:619)) - (PORT datab (225:225:225) (273:273:273)) - (PORT datac (824:824:824) (846:846:846)) - (PORT datad (1377:1377:1377) (1491:1491:1491)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~9) - (DELAY - (ABSOLUTE - (PORT dataa (780:780:780) (837:837:837)) - (PORT datab (827:827:827) (864:864:864)) - (PORT datac (762:762:762) (835:835:835)) - (PORT datad (767:767:767) (810:810:810)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~10) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1230:1230:1230) (1277:1277:1277)) - (PORT datab (699:699:699) (755:755:755)) - (PORT datac (917:917:917) (964:964:964)) - (PORT datad (1070:1070:1070) (1101:1101:1101)) - (IOPATH dataa combout (304:304:304) (299:299:299)) + (PORT dataa (1813:1813:1813) (1882:1882:1882)) + (PORT datab (1074:1074:1074) (1139:1139:1139)) + (PORT datac (1722:1722:1722) (1803:1803:1803)) + (PORT datad (217:217:217) (256:256:256)) + (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -19501,406 +3405,74 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) (DELAY (ABSOLUTE - (PORT dataa (625:625:625) (667:667:667)) - (PORT datab (653:653:653) (673:673:673)) - (PORT datac (935:935:935) (1036:1036:1036)) - (PORT datad (387:387:387) (408:408:408)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) - (DELAY - (ABSOLUTE - (PORT dataa (971:971:971) (1042:1042:1042)) - (PORT datab (1807:1807:1807) (1835:1835:1835)) - (PORT datac (1262:1262:1262) (1315:1315:1315)) - (PORT datad (1069:1069:1069) (1081:1081:1081)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) - (DELAY - (ABSOLUTE - (PORT dataa (2018:2018:2018) (2105:2105:2105)) - (PORT datab (2408:2408:2408) (2537:2537:2537)) - (PORT datac (1381:1381:1381) (1441:1441:1441)) - (PORT datad (1576:1576:1576) (1733:1733:1733)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1517:1517:1517) (1579:1579:1579)) - (PORT datab (385:385:385) (404:404:404)) - (PORT datac (1263:1263:1263) (1308:1308:1308)) - (PORT datad (871:871:871) (923:923:923)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1215:1215:1215) (1269:1269:1269)) - (PORT datab (340:340:340) (375:375:375)) - (PORT datac (1057:1057:1057) (1084:1084:1084)) - (PORT datad (337:337:337) (358:358:358)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (385:385:385)) - (PORT datab (643:643:643) (665:665:665)) - (PORT datac (169:169:169) (201:201:201)) - (PORT datad (616:616:616) (624:624:624)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~18) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (887:887:887)) - (PORT datab (1118:1118:1118) (1197:1197:1197)) - (PORT datac (848:848:848) (898:898:898)) - (PORT datad (364:364:364) (426:426:426)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) - (DELAY - (ABSOLUTE - (PORT dataa (2563:2563:2563) (2705:2705:2705)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (1385:1385:1385) (1391:1391:1391)) - (PORT datad (1888:1888:1888) (1980:1980:1980)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (455:455:455) (529:529:529)) - (PORT datab (452:452:452) (522:522:522)) - (PORT datac (877:877:877) (897:897:897)) - (PORT datad (660:660:660) (680:680:680)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (546:546:546) (573:573:573)) - (PORT datab (633:633:633) (685:685:685)) - (PORT datac (619:619:619) (639:639:639)) - (PORT datad (630:630:630) (672:672:672)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) - (DELAY - (ABSOLUTE - (PORT dataa (815:815:815) (850:850:850)) - (PORT datab (621:621:621) (640:640:640)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (182:182:182) (212:212:212)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (811:811:811) (823:823:823)) - (PORT datab (610:610:610) (633:633:633)) - (PORT datac (1092:1092:1092) (1142:1142:1142)) - (PORT datad (895:895:895) (948:948:948)) + (PORT dataa (1366:1366:1366) (1474:1474:1474)) + (PORT datad (1994:1994:1994) (2071:2071:2071)) (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~8) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) (DELAY (ABSOLUTE - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (232:232:232) (287:287:287)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (432:432:432) (521:521:521)) - (PORT datab (682:682:682) (739:739:739)) - (PORT datac (877:877:877) (897:897:897)) - (PORT datad (660:660:660) (685:685:685)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~12) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (922:922:922)) - (PORT datab (224:224:224) (269:269:269)) - (PORT datac (826:826:826) (848:848:848)) - (PORT datad (904:904:904) (974:974:974)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) - (DELAY - (ABSOLUTE - (PORT dataa (786:786:786) (842:842:842)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (1821:1821:1821) (1815:1815:1815)) - (PORT datad (790:790:790) (826:826:826)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (684:684:684) (706:706:706)) - (PORT datab (1772:1772:1772) (1798:1798:1798)) - (PORT datac (179:179:179) (214:214:214)) - (PORT datad (823:823:823) (837:837:837)) + (PORT dataa (1446:1446:1446) (1484:1484:1484)) + (PORT datab (854:854:854) (902:902:902)) + (PORT datac (909:909:909) (971:971:971)) + (PORT datad (616:616:616) (647:647:647)) (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) - (DELAY - (ABSOLUTE - (PORT dataa (2390:2390:2390) (2544:2544:2544)) - (PORT datab (1497:1497:1497) (1581:1581:1581)) - (PORT datac (874:874:874) (897:897:897)) - (PORT datad (1014:1014:1014) (1128:1128:1128)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) - (DELAY - (ABSOLUTE - (PORT dataa (578:578:578) (605:605:605)) - (PORT datab (974:974:974) (1056:1056:1056)) - (PORT datac (672:672:672) (715:715:715)) - (PORT datad (819:819:819) (820:820:820)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) - (DELAY - (ABSOLUTE - (PORT dataa (987:987:987) (1039:1039:1039)) - (PORT datab (434:434:434) (474:474:474)) - (PORT datac (947:947:947) (1015:1015:1015)) - (PORT datad (1175:1175:1175) (1235:1235:1235)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (285:285:285)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (208:208:208) (238:238:238)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) - (DELAY - (ABSOLUTE - (PORT datab (229:229:229) (278:278:278)) - (PORT datac (193:193:193) (235:235:235)) - (PORT datad (374:374:374) (396:396:396)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (639:639:639) (661:661:661)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) - (DELAY - (ABSOLUTE - (PORT datab (1269:1269:1269) (1380:1380:1380)) - (PORT datac (901:901:901) (917:917:917)) - (PORT datad (1177:1177:1177) (1191:1191:1191)) (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) + (INSTANCE z80_\|execute_\|ctl_mWrite\~7) (DELAY (ABSOLUTE - (PORT dataa (1285:1285:1285) (1340:1340:1340)) - (PORT datab (1007:1007:1007) (1075:1075:1075)) - (PORT datac (1456:1456:1456) (1496:1496:1496)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (304:304:304) (307:307:307)) + (PORT dataa (1230:1230:1230) (1296:1296:1296)) + (PORT datab (266:266:266) (314:314:314)) + (PORT datac (928:928:928) (983:983:983)) + (PORT datad (1184:1184:1184) (1243:1243:1243)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (591:591:591)) + (PORT datab (1349:1349:1349) (1470:1470:1470)) + (PORT datac (808:808:808) (820:820:820)) + (PORT datad (834:834:834) (910:910:910)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1860:1860:1860) (1945:1945:1945)) + (PORT datab (1656:1656:1656) (1813:1813:1813)) + (PORT datac (1723:1723:1723) (1804:1804:1804)) + (PORT datad (880:880:880) (899:899:899)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -19909,15 +3481,213 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) + (INSTANCE z80_\|execute_\|fMWrite\~4) (DELAY (ABSOLUTE - (PORT dataa (2050:2050:2050) (2087:2087:2087)) - (PORT datab (943:943:943) (1022:1022:1022)) - (PORT datac (1211:1211:1211) (1239:1239:1239)) - (PORT datad (1083:1083:1083) (1126:1126:1126)) + (PORT datab (1616:1616:1616) (1771:1771:1771)) + (PORT datac (1389:1389:1389) (1456:1456:1456)) + (PORT datad (1311:1311:1311) (1374:1374:1374)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~4) + (DELAY + (ABSOLUTE + (PORT datab (2076:2076:2076) (2209:2209:2209)) + (PORT datad (933:933:933) (1039:1039:1039)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) + (DELAY + (ABSOLUTE + (PORT dataa (934:934:934) (985:985:985)) + (PORT datab (1376:1376:1376) (1394:1394:1394)) + (PORT datac (1649:1649:1649) (1659:1659:1659)) + (PORT datad (1168:1168:1168) (1213:1213:1213)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (935:935:935)) + (PORT datab (698:698:698) (760:760:760)) + (PORT datac (915:915:915) (959:959:959)) + (PORT datad (661:661:661) (719:719:719)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1181:1181:1181) (1224:1224:1224)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (873:873:873) (934:934:934)) + (PORT datad (183:183:183) (213:213:213)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1020:1020:1020) (1059:1059:1059)) + (PORT datab (1999:1999:1999) (2042:2042:2042)) + (PORT datac (1001:1001:1001) (1029:1029:1029)) + (PORT datad (1097:1097:1097) (1148:1148:1148)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~51) + (DELAY + (ABSOLUTE + (PORT dataa (2428:2428:2428) (2599:2599:2599)) + (PORT datab (1208:1208:1208) (1296:1296:1296)) + (PORT datac (1399:1399:1399) (1508:1508:1508)) + (PORT datad (555:555:555) (574:574:574)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (474:474:474) (509:509:509)) + (PORT datab (767:767:767) (841:841:841)) + (PORT datac (1069:1069:1069) (1085:1085:1085)) + (PORT datad (787:787:787) (850:850:850)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) + (DELAY + (ABSOLUTE + (PORT dataa (2204:2204:2204) (2398:2398:2398)) + (PORT datab (686:686:686) (707:707:707)) + (PORT datac (835:835:835) (875:875:875)) + (PORT datad (1872:1872:1872) (2005:2005:2005)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal46\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1772:1772:1772) (1872:1872:1872)) + (PORT datab (739:739:739) (800:800:800)) + (PORT datac (1861:1861:1861) (1915:1915:1915)) + (PORT datad (1607:1607:1607) (1753:1753:1753)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (812:812:812) (894:894:894)) + (PORT datab (1876:1876:1876) (2012:2012:2012)) + (PORT datac (328:328:328) (351:351:351)) + (PORT datad (1690:1690:1690) (1763:1763:1763)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (1013:1013:1013)) + (PORT datab (1893:1893:1893) (2038:2038:2038)) + (PORT datac (2174:2174:2174) (2358:2358:2358)) + (PORT datad (955:955:955) (995:995:995)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~6) + (DELAY + (ABSOLUTE + (PORT datab (1677:1677:1677) (1729:1729:1729)) + (PORT datad (2190:2190:2190) (2227:2227:2227)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1285:1285:1285) (1356:1356:1356)) + (PORT datab (662:662:662) (720:720:720)) + (PORT datac (856:856:856) (884:884:884)) + (PORT datad (846:846:846) (874:874:874)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19925,159 +3695,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) (DELAY (ABSOLUTE - (PORT dataa (923:923:923) (949:949:949)) - (PORT datab (1060:1060:1060) (1085:1085:1085)) - (PORT datac (892:892:892) (934:934:934)) - (PORT datad (568:568:568) (571:571:571)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1490:1490:1490) (1592:1592:1592)) - (PORT datab (438:438:438) (472:472:472)) - (PORT datac (945:945:945) (997:997:997)) - (PORT datad (1178:1178:1178) (1233:1233:1233)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1493:1493:1493) (1597:1597:1597)) - (PORT datab (234:234:234) (278:278:278)) - (PORT datac (2021:2021:2021) (2050:2050:2050)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (609:609:609) (638:638:638)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (258:258:258)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (817:817:817) (862:862:862)) - (PORT datad (554:554:554) (572:572:572)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1462:1462:1462) (1525:1525:1525)) - (PORT datab (1404:1404:1404) (1424:1424:1424)) - (PORT datac (1574:1574:1574) (1618:1618:1618)) - (PORT datad (1065:1065:1065) (1079:1079:1079)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) - (DELAY - (ABSOLUTE - (PORT dataa (734:734:734) (759:759:759)) - (PORT datab (699:699:699) (730:730:730)) - (PORT datac (1599:1599:1599) (1604:1604:1604)) - (PORT datad (1436:1436:1436) (1479:1479:1479)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1343:1343:1343) (1425:1425:1425)) - (PORT datab (1086:1086:1086) (1110:1110:1110)) - (PORT datac (1574:1574:1574) (1614:1614:1614)) - (PORT datad (1794:1794:1794) (1911:1911:1911)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (843:843:843) (880:880:880)) - (PORT datac (1602:1602:1602) (1608:1608:1608)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~42) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (867:867:867)) - (PORT datab (1092:1092:1092) (1116:1116:1116)) - (PORT datac (2113:2113:2113) (2219:2219:2219)) - (PORT datad (1789:1789:1789) (1904:1904:1904)) + (PORT dataa (1444:1444:1444) (1482:1482:1482)) + (PORT datab (1494:1494:1494) (1558:1558:1558)) + (PORT datac (1227:1227:1227) (1257:1257:1257)) + (PORT datad (932:932:932) (1002:1002:1002)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20085,63 +3711,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) (DELAY (ABSOLUTE (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1016:1016:1016) (1027:1027:1027)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~41) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (702:702:702)) - (PORT datab (2051:2051:2051) (2134:2134:2134)) - (PORT datac (1486:1486:1486) (1540:1540:1540)) - (PORT datad (1327:1327:1327) (1454:1454:1454)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1519:1519:1519) (1580:1580:1580)) - (PORT datab (1960:1960:1960) (1986:1986:1986)) - (PORT datac (1263:1263:1263) (1313:1313:1313)) - (PORT datad (869:869:869) (922:922:922)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1748:1748:1748) (1872:1872:1872)) - (PORT datab (1028:1028:1028) (1083:1083:1083)) - (PORT datac (199:199:199) (235:235:235)) - (PORT datad (1506:1506:1506) (1541:1541:1541)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (897:897:897) (961:961:961)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20149,31 +3725,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) + (INSTANCE z80_\|pla_decode_\|Equal55\~0) (DELAY (ABSOLUTE - (PORT dataa (1165:1165:1165) (1194:1194:1194)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1359:1359:1359) (1382:1382:1382)) + (PORT dataa (1756:1756:1756) (1851:1851:1851)) + (PORT datab (1657:1657:1657) (1809:1809:1809)) + (PORT datad (1812:1812:1812) (1893:1893:1893)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~44) + (INSTANCE z80_\|execute_\|ctl_mRead\~7) (DELAY (ABSOLUTE - (PORT dataa (819:819:819) (841:841:841)) - (PORT datab (1818:1818:1818) (1968:1968:1968)) - (PORT datac (1306:1306:1306) (1386:1386:1386)) - (PORT datad (1794:1794:1794) (1911:1911:1911)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (994:994:994) (1075:1075:1075)) + (PORT datac (1310:1310:1310) (1404:1404:1404)) + (PORT datad (914:914:914) (958:958:958)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20181,255 +3753,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (699:699:699) (733:733:733)) - (PORT datac (862:862:862) (901:901:901)) - (PORT datad (693:693:693) (717:717:717)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) - (DELAY - (ABSOLUTE - (PORT dataa (532:532:532) (551:551:551)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (641:641:641) (659:659:659)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~39) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (620:620:620)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (603:603:603) (622:622:622)) - (PORT datad (345:345:345) (359:359:359)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~40) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (917:917:917) (956:956:956)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (317:317:317) (337:337:337)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1666:1666:1666) (1754:1754:1754)) - (PORT datab (1416:1416:1416) (1493:1493:1493)) - (PORT datac (639:639:639) (659:659:659)) - (PORT datad (847:847:847) (875:875:875)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1450:1450:1450) (1506:1506:1506)) - (PORT datab (849:849:849) (859:859:859)) - (PORT datac (836:836:836) (864:864:864)) - (PORT datad (1389:1389:1389) (1423:1423:1423)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R) - (DELAY - (ABSOLUTE - (PORT dataa (831:831:831) (869:869:869)) - (PORT datab (1772:1772:1772) (1798:1798:1798)) - (PORT datac (618:618:618) (638:638:638)) - (PORT datad (822:822:822) (837:837:837)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1198:1198:1198) (1248:1248:1248)) - (PORT datab (223:223:223) (268:268:268)) - (PORT datac (914:914:914) (947:947:947)) - (PORT datad (607:607:607) (631:631:631)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (263:263:263) (334:334:334)) - (PORT datab (944:944:944) (991:991:991)) - (PORT datac (535:535:535) (545:545:545)) - (PORT datad (1139:1139:1139) (1125:1125:1125)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (673:673:673)) - (PORT datab (1125:1125:1125) (1173:1173:1173)) - (PORT datac (583:583:583) (615:615:615)) - (PORT datad (389:389:389) (443:443:443)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (263:263:263) (340:340:340)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (559:559:559) (583:583:583)) - (PORT datad (901:901:901) (948:948:948)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (511:511:511)) - (PORT datab (419:419:419) (499:499:499)) - (PORT datac (878:878:878) (901:901:901)) - (PORT datad (657:657:657) (678:678:678)) - (IOPATH dataa combout (324:324:324) (328:328:328)) + (PORT dataa (2680:2680:2680) (2765:2765:2765)) + (PORT datab (751:751:751) (781:781:781)) + (PORT datac (998:998:998) (1052:1052:1052)) + (PORT datad (890:890:890) (939:939:939)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (638:638:638) (659:659:659)) - (PORT datac (355:355:355) (378:378:378)) - (PORT datad (830:830:830) (837:837:837)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (419:419:419)) - (PORT datab (653:653:653) (711:711:711)) - (PORT datac (647:647:647) (707:707:707)) - (PORT datad (635:635:635) (659:659:659)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20437,670 +3769,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) (DELAY (ABSOLUTE - (PORT dataa (413:413:413) (443:443:443)) - (PORT datab (239:239:239) (284:284:284)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (709:709:709) (742:742:742)) - (PORT datab (1178:1178:1178) (1274:1274:1274)) - (PORT datac (855:855:855) (865:865:865)) - (PORT datad (674:674:674) (693:693:693)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1304:1304:1304) (1358:1358:1358)) - (PORT datab (1962:1962:1962) (1990:1990:1990)) - (PORT datac (1486:1486:1486) (1545:1545:1545)) - (PORT datad (1495:1495:1495) (1557:1557:1557)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1144:1144:1144) (1179:1179:1179)) - (PORT datab (609:609:609) (638:638:638)) - (PORT datac (820:820:820) (842:842:842)) + (PORT dataa (1003:1003:1003) (1052:1052:1052)) + (PORT datac (1080:1080:1080) (1095:1095:1095)) (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (257:257:257)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datad (798:798:798) (805:805:805)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1152:1152:1152) (1175:1175:1175)) - (PORT datac (567:567:567) (576:576:576)) - (PORT datad (1627:1627:1627) (1703:1703:1703)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (927:927:927)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1829:1829:1829) (1911:1911:1911)) - (PORT datad (562:562:562) (570:570:570)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~13) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (415:415:415)) - (PORT datab (2086:2086:2086) (2229:2229:2229)) - (PORT datac (1314:1314:1314) (1402:1402:1402)) - (PORT datad (902:902:902) (968:968:968)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (462:462:462)) - (PORT datab (612:612:612) (633:633:633)) - (PORT datac (1175:1175:1175) (1235:1235:1235)) - (PORT datad (822:822:822) (844:844:844)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) - (DELAY - (ABSOLUTE - (PORT dataa (572:572:572) (597:597:597)) - (PORT datab (615:615:615) (638:638:638)) - (PORT datad (567:567:567) (574:574:574)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (685:685:685)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (807:807:807) (808:808:808)) - (PORT datad (203:203:203) (232:232:232)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1698:1698:1698) (1789:1789:1789)) - (PORT datab (919:919:919) (952:952:952)) - (PORT datac (888:888:888) (909:909:909)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[12\]) - (DELAY - (ABSOLUTE - (PORT datab (403:403:403) (448:448:448)) - (PORT datac (885:885:885) (915:915:915)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[12\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (314:314:314) (333:333:333)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1561:1561:1561)) - (PORT ena (2058:2058:2058) (2109:2109:2109)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (638:638:638)) - (PORT datab (903:903:903) (926:926:926)) - (PORT datac (240:240:240) (327:327:327)) - (PORT datad (577:577:577) (639:639:639)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (1270:1270:1270) (1318:1318:1318)) - (PORT ena (935:935:935) (924:924:924)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (460:460:460)) - (PORT datab (412:412:412) (448:448:448)) - (PORT datad (194:194:194) (218:218:218)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (717:717:717)) - (PORT datac (216:216:216) (293:293:293)) - (PORT datad (775:775:775) (807:807:807)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (418:418:418)) - (PORT datab (838:838:838) (875:875:875)) - (PORT datac (679:679:679) (721:721:721)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (2041:2041:2041) (2053:2053:2053)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (437:437:437)) - (PORT datab (1165:1165:1165) (1216:1216:1216)) - (PORT datad (739:739:739) (751:751:751)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (2041:2041:2041) (2050:2050:2050)) - (PORT ena (1236:1236:1236) (1273:1273:1273)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (692:692:692) (780:780:780)) - (PORT datab (884:884:884) (909:909:909)) - (PORT datad (866:866:866) (902:902:902)) (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1376:1376:1376) (1427:1427:1427)) - (PORT ena (1214:1214:1214) (1210:1210:1210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1376:1376:1376) (1429:1429:1429)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (905:905:905) (945:945:945)) - (PORT datab (244:244:244) (290:290:290)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1394:1394:1394) (1418:1418:1418)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1721:1721:1721) (1742:1742:1742)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (392:392:392) (467:467:467)) - (PORT datab (1593:1593:1593) (1645:1645:1645)) - (PORT datad (1180:1180:1180) (1215:1215:1215)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (809:809:809) (810:810:810)) - (PORT datad (610:610:610) (622:622:622)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1872:1872:1872) (1943:1943:1943)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1872:1872:1872) (1942:1942:1942)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (991:991:991)) - (PORT datab (912:912:912) (981:981:981)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1938:1938:1938) (1952:1952:1952)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1936:1936:1936) (1952:1952:1952)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (519:519:519)) - (PORT datab (492:492:492) (537:537:537)) - (PORT datad (217:217:217) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1867:1867:1867) (1935:1935:1935)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (988:988:988)) - (PORT datab (1221:1221:1221) (1295:1295:1295)) - (PORT datad (887:887:887) (943:943:943)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (697:697:697)) - (PORT datab (331:331:331) (360:360:360)) - (PORT datac (577:577:577) (594:594:594)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -21108,2955 +3783,25 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~66) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) (DELAY (ABSOLUTE - (PORT dataa (883:883:883) (947:947:947)) - (PORT datab (844:844:844) (916:916:916)) - (PORT datac (840:840:840) (851:851:851)) - (PORT datad (1298:1298:1298) (1335:1335:1335)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1304:1304:1304) (1356:1356:1356)) - (PORT datab (968:968:968) (1024:1024:1024)) - (PORT datac (891:891:891) (908:908:908)) - (PORT datad (1445:1445:1445) (1454:1454:1454)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1289:1289:1289) (1337:1337:1337)) - (PORT datab (1225:1225:1225) (1251:1251:1251)) - (PORT datac (904:904:904) (947:947:947)) - (PORT datad (928:928:928) (986:986:986)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (251:251:251)) - (PORT datab (249:249:249) (305:305:305)) - (PORT datac (1067:1067:1067) (1064:1064:1064)) - (PORT datad (949:949:949) (996:996:996)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1286:1286:1286) (1354:1354:1354)) - (PORT datab (933:933:933) (990:990:990)) - (PORT datac (372:372:372) (402:402:402)) - (PORT datad (1200:1200:1200) (1314:1314:1314)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1230:1230:1230)) - (PORT datab (1831:1831:1831) (1921:1921:1921)) - (PORT datac (881:881:881) (935:935:935)) - (PORT datad (1554:1554:1554) (1661:1661:1661)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) - (DELAY - (ABSOLUTE - (PORT dataa (923:923:923) (987:987:987)) - (PORT datab (637:637:637) (672:672:672)) - (PORT datac (1395:1395:1395) (1470:1470:1470)) - (PORT datad (580:580:580) (617:617:617)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datac (935:935:935) (965:965:965)) - (PORT datad (241:241:241) (282:282:282)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1212:1212:1212)) - (PORT datab (290:290:290) (355:355:355)) - (PORT datac (254:254:254) (314:314:314)) - (PORT datad (246:246:246) (292:292:292)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT datab (359:359:359) (395:395:395)) - (PORT datac (927:927:927) (982:982:982)) - (PORT datad (676:676:676) (714:714:714)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (695:695:695)) - (PORT datab (1175:1175:1175) (1218:1218:1218)) - (PORT datac (649:649:649) (707:707:707)) - (PORT datad (660:660:660) (719:719:719)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (598:598:598) (629:629:629)) - (PORT datab (329:329:329) (356:356:356)) - (PORT datac (1163:1163:1163) (1203:1203:1203)) - (PORT datad (530:530:530) (548:548:548)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (679:679:679)) - (PORT datab (998:998:998) (1032:1032:1032)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (220:220:220) (263:263:263)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (621:621:621)) - (PORT datab (963:963:963) (1009:1009:1009)) - (PORT datac (864:864:864) (907:907:907)) - (PORT datad (337:337:337) (357:357:357)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (674:674:674) (713:713:713)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (963:963:963)) - (PORT datab (719:719:719) (762:762:762)) - (PORT datac (929:929:929) (980:980:980)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (678:678:678)) - (PORT datab (640:640:640) (697:697:697)) - (PORT datac (608:608:608) (646:646:646)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (648:648:648)) - (PORT datab (935:935:935) (984:984:984)) - (PORT datac (1093:1093:1093) (1149:1149:1149)) - (PORT datad (575:575:575) (595:595:595)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (263:263:263) (339:339:339)) - (PORT datac (171:171:171) (204:204:204)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (431:431:431) (524:524:524)) - (PORT datac (650:650:650) (711:711:711)) - (PORT datad (658:658:658) (684:684:684)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (600:600:600)) - (PORT datab (826:826:826) (830:830:830)) - (PORT datac (805:805:805) (806:806:806)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (688:688:688) (712:712:712)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datac (203:203:203) (240:240:240)) - (PORT datad (818:818:818) (831:831:831)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (676:676:676)) - (PORT datab (632:632:632) (684:684:684)) - (PORT datad (630:630:630) (672:672:672)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (704:704:704)) - (PORT datab (860:860:860) (876:876:876)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (515:515:515) (526:526:526)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (252:252:252)) - (PORT datab (213:213:213) (257:257:257)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (182:182:182) (212:212:212)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (690:690:690)) - (PORT datab (662:662:662) (696:696:696)) - (PORT datad (604:604:604) (655:655:655)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (369:369:369) (405:405:405)) - (PORT datab (638:638:638) (659:659:659)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (830:830:830) (837:837:837)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (410:410:410)) - (PORT datab (394:394:394) (423:423:423)) - (PORT datac (177:177:177) (214:214:214)) - (PORT datad (368:368:368) (390:390:390)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) - (DELAY - (ABSOLUTE - (PORT datac (1740:1740:1740) (1766:1766:1766)) - (PORT datad (822:822:822) (836:836:836)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (410:410:410)) - (PORT datab (234:234:234) (279:279:279)) - (PORT datac (177:177:177) (213:213:213)) - (PORT datad (179:179:179) (207:207:207)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (236:236:236) (281:281:281)) - (PORT datac (354:354:354) (379:379:379)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1068:1068:1068) (1102:1102:1102)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1435:1435:1435) (1482:1482:1482)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (1596:1596:1596) (1648:1648:1648)) - (PORT datad (1179:1179:1179) (1221:1221:1221)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1647:1647:1647) (1718:1718:1718)) - (PORT ena (1214:1214:1214) (1210:1210:1210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1644:1644:1644) (1714:1714:1714)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (902:902:902) (942:942:942)) - (PORT datab (245:245:245) (290:290:290)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1405:1405:1405) (1471:1471:1471)) - (PORT ena (1236:1236:1236) (1273:1273:1273)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (798:798:798)) - (PORT datab (884:884:884) (909:909:909)) - (PORT datad (866:866:866) (902:902:902)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1404:1404:1404) (1472:1472:1472)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (1391:1391:1391) (1418:1418:1418)) - (PORT datab (1167:1167:1167) (1217:1217:1217)) - (PORT datad (238:238:238) (279:279:279)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (820:820:820) (843:843:843)) - (PORT datab (1070:1070:1070) (1130:1130:1130)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1442:1442:1442) (1490:1490:1490)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1439:1439:1439) (1490:1490:1490)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (523:523:523)) - (PORT datab (492:492:492) (536:536:536)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1377:1377:1377) (1423:1423:1423)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (938:938:938) (994:994:994)) - (PORT datab (1222:1222:1222) (1294:1294:1294)) - (PORT datad (881:881:881) (941:941:941)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1195:1195:1195) (1249:1249:1249)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1195:1195:1195) (1248:1248:1248)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (924:924:924) (985:985:985)) - (PORT datab (910:910:910) (988:988:988)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (410:410:410)) - (PORT datab (634:634:634) (661:661:661)) - (PORT datac (637:637:637) (673:673:673)) - (PORT datad (789:789:789) (853:853:853)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (1138:1138:1138) (1178:1178:1178)) - (PORT ena (935:935:935) (924:924:924)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (407:407:407) (446:446:446)) - (PORT datad (387:387:387) (422:422:422)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (860:860:860)) - (PORT datac (214:214:214) (289:289:289)) - (PORT datad (646:646:646) (672:672:672)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (623:623:623) (634:634:634)) - (PORT datab (906:906:906) (933:933:933)) - (PORT datac (239:239:239) (322:322:322)) - (PORT datad (576:576:576) (636:636:636)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) - (DELAY - (ABSOLUTE - (PORT datac (258:258:258) (345:345:345)) - (PORT datad (187:187:187) (220:220:220)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1405:1405:1405) (1477:1477:1477)) - (PORT ena (1261:1261:1261) (1299:1299:1299)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (1099:1099:1099) (1151:1151:1151)) - (PORT datab (881:881:881) (915:915:915)) - (PORT datad (665:665:665) (744:744:744)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (2052:2052:2052) (2111:2111:2111)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1647:1647:1647) (1654:1654:1654)) - (PORT datab (1164:1164:1164) (1211:1211:1211)) - (PORT datad (231:231:231) (271:271:271)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1101:1101:1101) (1166:1166:1166)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1418:1418:1418) (1481:1481:1481)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (380:380:380) (459:459:459)) - (PORT datab (1594:1594:1594) (1651:1651:1651)) - (PORT datad (1178:1178:1178) (1221:1221:1221)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1799:1799:1799) (1855:1855:1855)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1406:1406:1406) (1476:1476:1476)) - (PORT ena (1131:1131:1131) (1098:1098:1098)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (478:478:478)) - (PORT datab (881:881:881) (916:916:916)) - (PORT datad (364:364:364) (384:384:384)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (338:338:338) (368:368:368)) - (PORT datac (804:804:804) (808:808:808)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1448:1448:1448) (1498:1498:1498)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1448:1448:1448) (1501:1501:1501)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (518:518:518)) - (PORT datab (240:240:240) (322:322:322)) - (PORT datad (458:458:458) (504:504:504)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1721:1721:1721) (1779:1779:1779)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1723:1723:1723) (1782:1782:1782)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (989:989:989)) - (PORT datab (243:243:243) (326:326:326)) - (PORT datad (883:883:883) (941:941:941)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1771:1771:1771) (1829:1829:1829)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (989:989:989)) - (PORT datab (1220:1220:1220) (1296:1296:1296)) - (PORT datad (884:884:884) (944:944:944)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (699:699:699)) - (PORT datab (825:825:825) (869:869:869)) - (PORT datac (606:606:606) (632:632:632)) - (PORT datad (842:842:842) (848:848:848)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (884:884:884) (946:946:946)) - (PORT datab (197:197:197) (234:234:234)) - (PORT datac (817:817:817) (863:863:863)) - (PORT datad (1298:1298:1298) (1332:1332:1332)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (1159:1159:1159) (1205:1205:1205)) - (PORT ena (935:935:935) (924:924:924)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (459:459:459)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datad (386:386:386) (413:413:413)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (716:716:716)) - (PORT datab (379:379:379) (421:421:421)) - (PORT datac (215:215:215) (292:292:292)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (567:567:567) (582:582:582)) - (PORT datab (844:844:844) (883:883:883)) - (PORT datac (682:682:682) (722:722:722)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[13\]) - (DELAY - (ABSOLUTE - (PORT datab (383:383:383) (425:425:425)) - (PORT datac (886:886:886) (918:918:918)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[13\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (335:335:335) (352:352:352)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1561:1561:1561)) - (PORT ena (2058:2058:2058) (2109:2109:2109)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) - (DELAY - (ABSOLUTE - (PORT datac (258:258:258) (345:345:345)) - (PORT datad (869:869:869) (891:891:891)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[15\]) - (DELAY - (ABSOLUTE - (PORT datac (356:356:356) (377:377:377)) - (PORT datad (867:867:867) (889:889:889)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1561:1561:1561)) - (PORT ena (2058:2058:2058) (2109:2109:2109)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) - (DELAY - (ABSOLUTE - (PORT dataa (290:290:290) (385:385:385)) - (PORT datab (215:215:215) (260:260:260)) - (PORT datac (245:245:245) (326:326:326)) - (PORT datad (866:866:866) (891:891:891)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (2284:2284:2284) (2422:2422:2422)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (2284:2284:2284) (2422:2422:2422)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (524:524:524)) - (PORT datab (491:491:491) (541:541:541)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1879:1879:1879) (1975:1975:1975)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (818:818:818) (835:835:835)) - (PORT datab (1168:1168:1168) (1216:1216:1216)) - (PORT datad (239:239:239) (281:281:281)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1192:1192:1192) (1258:1258:1258)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (2131:2131:2131) (2211:2211:2211)) - (PORT ena (1131:1131:1131) (1098:1098:1098)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (460:460:460)) - (PORT datab (883:883:883) (917:917:917)) - (PORT datad (364:364:364) (384:384:384)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1453:1453:1453) (1497:1497:1497)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1453:1453:1453) (1497:1497:1497)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (1297:1297:1297) (1353:1353:1353)) - (PORT datab (1218:1218:1218) (1255:1255:1255)) - (PORT datad (214:214:214) (282:282:282)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (2133:2133:2133) (2211:2211:2211)) - (PORT ena (1261:1261:1261) (1299:1299:1299)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (1100:1100:1100) (1146:1146:1146)) - (PORT datab (681:681:681) (756:756:756)) - (PORT datad (848:848:848) (874:874:874)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (624:624:624)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (595:595:595) (612:612:612)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1205:1205:1205) (1270:1270:1270)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1205:1205:1205) (1270:1270:1270)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (985:985:985)) - (PORT datab (912:912:912) (982:982:982)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (2162:2162:2162) (2212:2212:2212)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (939:939:939) (997:997:997)) - (PORT datab (1220:1220:1220) (1296:1296:1296)) - (PORT datad (879:879:879) (940:940:940)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (650:650:650)) - (PORT datab (632:632:632) (657:657:657)) - (PORT datac (489:489:489) (507:507:507)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (944:944:944)) - (PORT datab (672:672:672) (688:688:688)) - (PORT datac (786:786:786) (839:839:839)) - (PORT datad (1301:1301:1301) (1333:1333:1333)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (1132:1132:1132) (1183:1183:1183)) - (PORT ena (935:935:935) (924:924:924)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (466:466:466)) - (PORT datab (218:218:218) (258:258:258)) - (PORT datad (382:382:382) (412:412:412)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (332:332:332)) - (PORT datab (670:670:670) (688:688:688)) - (PORT datad (645:645:645) (672:672:672)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (401:401:401)) - (PORT datab (712:712:712) (754:754:754)) - (PORT datac (808:808:808) (840:840:840)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[14\]) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (955:955:955)) - (PORT datac (361:361:361) (395:395:395)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[14\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (320:320:320) (331:331:331)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1561:1561:1561)) - (PORT ena (2058:2058:2058) (2109:2109:2109)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (1141:1141:1141) (1169:1169:1169)) - (PORT datab (404:404:404) (477:477:477)) - (PORT datac (1110:1110:1110) (1117:1117:1117)) - (PORT datad (632:632:632) (663:663:663)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (214:214:214) (258:258:258)) - (PORT datac (232:232:232) (316:316:316)) - (PORT datad (339:339:339) (360:360:360)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (417:417:417)) - (PORT datab (712:712:712) (760:760:760)) - (PORT datac (814:814:814) (847:847:847)) - (PORT datad (550:550:550) (569:569:569)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (880:880:880) (950:950:950)) - (PORT datab (664:664:664) (704:704:704)) - (PORT datac (792:792:792) (834:834:834)) - (PORT datad (1297:1297:1297) (1337:1337:1337)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1297:1297:1297) (1347:1347:1347)) - (PORT datab (973:973:973) (1026:1026:1026)) - (PORT datac (1877:1877:1877) (1946:1946:1946)) - (PORT datad (831:831:831) (844:844:844)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datab (256:256:256) (314:314:314)) - (PORT datac (1193:1193:1193) (1204:1204:1204)) - (PORT datad (945:945:945) (989:989:989)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (933:933:933) (970:970:970)) - (PORT datab (1223:1223:1223) (1296:1296:1296)) - (PORT datac (905:905:905) (924:924:924)) - (PORT datad (1385:1385:1385) (1451:1451:1451)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (893:893:893) (902:902:902)) - (PORT datab (661:661:661) (697:697:697)) - (PORT datac (670:670:670) (697:697:697)) - (PORT datad (675:675:675) (694:694:694)) - (IOPATH dataa combout (325:325:325) (320:320:320)) + (PORT datab (1557:1557:1557) (1643:1643:1643)) + (PORT datac (1196:1196:1196) (1284:1284:1284)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) (DELAY (ABSOLUTE - (PORT dataa (1512:1512:1512) (1612:1612:1612)) - (PORT datab (1393:1393:1393) (1508:1508:1508)) - (PORT datac (1411:1411:1411) (1459:1459:1459)) - (PORT datad (835:835:835) (870:870:870)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (635:635:635)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (1083:1083:1083) (1127:1127:1127)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1159:1159:1159) (1199:1199:1199)) - (PORT datab (1007:1007:1007) (1063:1063:1063)) - (PORT datac (212:212:212) (252:252:252)) - (PORT datad (1995:1995:1995) (2085:2085:2085)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (211:211:211) (260:260:260)) - (PORT datab (634:634:634) (650:650:650)) - (PORT datac (599:599:599) (616:616:616)) - (PORT datad (610:610:610) (626:626:626)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~2) - (DELAY - (ABSOLUTE - (PORT datab (701:701:701) (761:761:761)) - (PORT datac (1331:1331:1331) (1352:1352:1352)) - (PORT datad (1148:1148:1148) (1179:1179:1179)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1693:1693:1693) (1732:1732:1732)) - (PORT datab (1474:1474:1474) (1569:1569:1569)) - (PORT datac (2562:2562:2562) (2664:2664:2664)) - (PORT datad (1898:1898:1898) (2017:2017:2017)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1942:1942:1942) (2062:2062:2062)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (918:918:918) (965:965:965)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (664:664:664)) - (PORT datab (640:640:640) (658:658:658)) - (PORT datad (880:880:880) (936:936:936)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1199:1199:1199) (1286:1286:1286)) - (PORT datab (255:255:255) (340:340:340)) - (PORT datac (1353:1353:1353) (1415:1415:1415)) - (PORT datad (1199:1199:1199) (1262:1262:1262)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datad (1171:1171:1171) (1244:1244:1244)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (219:219:219) (259:259:259)) - (PORT datac (882:882:882) (919:919:919)) - (PORT datad (1382:1382:1382) (1453:1453:1453)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (442:442:442)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (896:896:896) (932:932:932)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (511:511:511)) - (PORT datab (1166:1166:1166) (1210:1210:1210)) - (PORT datac (593:593:593) (646:646:646)) - (PORT datad (662:662:662) (719:719:719)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1177:1177:1177) (1208:1208:1208)) - (PORT datab (281:281:281) (344:344:344)) - (PORT datac (245:245:245) (304:304:304)) - (PORT datad (256:256:256) (301:301:301)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (378:378:378)) - (PORT datab (802:802:802) (831:831:831)) - (PORT datac (498:498:498) (504:504:504)) - (PORT datad (1104:1104:1104) (1147:1147:1147)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (639:639:639)) - (PORT datab (999:999:999) (1033:1033:1033)) - (PORT datac (589:589:589) (604:604:604)) - (PORT datad (221:221:221) (264:264:264)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (404:404:404)) - (PORT datab (893:893:893) (942:942:942)) - (PORT datac (1167:1167:1167) (1166:1166:1166)) - (PORT datad (680:680:680) (715:715:715)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (756:756:756)) - (PORT datab (1177:1177:1177) (1222:1222:1222)) - (PORT datac (613:613:613) (678:678:678)) - (PORT datad (666:666:666) (725:725:725)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) - (DELAY - (ABSOLUTE - (PORT datab (288:288:288) (350:350:350)) - (PORT datad (251:251:251) (296:296:296)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (285:285:285) (347:347:347)) - (PORT datab (620:620:620) (638:638:638)) - (PORT datac (1141:1141:1141) (1167:1167:1167)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1287:1287:1287)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (968:968:968) (996:996:996)) - (PORT datac (1660:1660:1660) (1742:1742:1742)) - (PORT datad (1418:1418:1418) (1445:1445:1445)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1138:1138:1138) (1168:1168:1168)) - (PORT datab (1129:1129:1129) (1182:1182:1182)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (241:241:241) (282:282:282)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (522:522:522) (538:538:538)) - (PORT datab (879:879:879) (956:956:956)) - (PORT datac (959:959:959) (990:990:990)) - (PORT datad (594:594:594) (608:608:608)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1196:1196:1196) (1243:1243:1243)) - (PORT datab (609:609:609) (645:645:645)) - (PORT datac (193:193:193) (235:235:235)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (695:695:695)) - (PORT datab (912:912:912) (959:959:959)) - (PORT datac (854:854:854) (883:883:883)) - (PORT datad (1144:1144:1144) (1179:1179:1179)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (678:678:678)) - (PORT datab (961:961:961) (1023:1023:1023)) - (PORT datac (1152:1152:1152) (1178:1178:1178)) - (PORT datad (225:225:225) (270:270:270)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (279:279:279)) - (PORT datab (1448:1448:1448) (1517:1517:1517)) - (PORT datac (1115:1115:1115) (1163:1163:1163)) - (PORT datad (178:178:178) (206:206:206)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1187:1187:1187) (1261:1261:1261)) - (PORT datab (930:930:930) (959:959:959)) - (PORT datac (533:533:533) (553:553:553)) - (PORT datad (844:844:844) (856:856:856)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1441:1441:1441) (1548:1548:1548)) - (PORT datab (218:218:218) (257:257:257)) - (PORT datac (235:235:235) (277:277:277)) - (PORT datad (1401:1401:1401) (1453:1453:1453)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (663:663:663)) - (PORT datab (615:615:615) (664:664:664)) - (PORT datac (664:664:664) (693:693:693)) - (PORT datad (680:680:680) (701:701:701)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) - (DELAY - (ABSOLUTE - (PORT datab (614:614:614) (644:644:644)) - (PORT datad (801:801:801) (877:877:877)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla69M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (665:665:665)) - (PORT datab (2306:2306:2306) (2385:2385:2385)) - (PORT datac (2054:2054:2054) (2198:2198:2198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (377:377:377) (426:426:426)) - (PORT datab (1624:1624:1624) (1701:1701:1701)) - (PORT datac (829:829:829) (848:848:848)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (816:816:816) (877:877:877)) - (PORT datab (360:360:360) (396:396:396)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (1002:1002:1002)) - (PORT datab (692:692:692) (710:710:710)) - (PORT datac (563:563:563) (586:586:586)) - (PORT datad (616:616:616) (630:630:630)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_xf) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~33) - (DELAY - (ABSOLUTE - (PORT datab (957:957:957) (981:981:981)) - (PORT datac (645:645:645) (694:694:694)) - (PORT datad (656:656:656) (712:712:712)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (378:378:378)) - (PORT datab (209:209:209) (251:251:251)) - (PORT datac (177:177:177) (213:213:213)) - (PORT datad (652:652:652) (692:692:692)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (904:904:904)) - (PORT datab (994:994:994) (1026:1026:1026)) - (PORT datac (1433:1433:1433) (1520:1520:1520)) - (PORT datad (1142:1142:1142) (1160:1160:1160)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (697:697:697)) - (PORT datab (936:936:936) (950:950:950)) - (PORT datac (1455:1455:1455) (1497:1497:1497)) - (PORT datad (1163:1163:1163) (1183:1183:1183)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (638:638:638)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datac (881:881:881) (909:909:909)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) - (DELAY - (ABSOLUTE - (PORT datab (1639:1639:1639) (1704:1704:1704)) - (PORT datac (1440:1440:1440) (1481:1481:1481)) - (PORT datad (1160:1160:1160) (1199:1199:1199)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (500:500:500)) - (PORT datab (1223:1223:1223) (1282:1282:1282)) - (PORT datac (1145:1145:1145) (1179:1179:1179)) - (PORT datad (899:899:899) (938:938:938)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (868:868:868) (917:917:917)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (870:870:870) (900:900:900)) - (PORT datad (616:616:616) (665:665:665)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (647:647:647)) - (PORT datab (247:247:247) (295:295:295)) - (PORT datac (1154:1154:1154) (1184:1184:1184)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (474:474:474) (512:512:512)) - (PORT datab (1141:1141:1141) (1188:1188:1188)) - (PORT datad (1463:1463:1463) (1479:1479:1479)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (486:486:486)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (1618:1618:1618) (1617:1617:1617)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) - (DELAY - (ABSOLUTE - (PORT datab (353:353:353) (390:390:390)) - (PORT datac (784:784:784) (794:794:794)) - (PORT datad (320:320:320) (341:341:341)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (970:970:970) (1022:1022:1022)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (970:970:970) (1022:1022:1022)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (336:336:336)) - (PORT datab (975:975:975) (1029:1029:1029)) - (PORT datad (845:845:845) (875:875:875)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (868:868:868) (877:877:877)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (869:869:869) (877:877:877)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (246:246:246) (333:333:333)) - (PORT datab (260:260:260) (314:314:314)) - (PORT datad (229:229:229) (267:267:267)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (870:870:870)) - (PORT datab (202:202:202) (242:242:242)) - (PORT datac (607:607:607) (626:626:626)) - (PORT datad (625:625:625) (639:639:639)) + (PORT dataa (994:994:994) (1076:1076:1076)) + (PORT datab (1450:1450:1450) (1484:1484:1484)) + (PORT datac (1313:1313:1313) (1404:1404:1404)) + (PORT datad (917:917:917) (957:957:957)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -24066,2295 +3811,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~52) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~17) (DELAY (ABSOLUTE - (PORT dataa (858:858:858) (895:895:895)) - (PORT datab (609:609:609) (627:627:627)) - (PORT datac (332:332:332) (359:359:359)) - (PORT datad (1115:1115:1115) (1138:1138:1138)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (957:957:957) (1002:1002:1002)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1331:1331:1331) (1374:1374:1374)) - (PORT datab (697:697:697) (731:731:731)) - (PORT datad (1194:1194:1194) (1238:1238:1238)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (669:669:669)) - (PORT datac (704:704:704) (742:742:742)) - (PORT datad (220:220:220) (290:290:290)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (401:401:401)) - (PORT datab (960:960:960) (999:999:999)) - (PORT datac (683:683:683) (718:718:718)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[3\]) - (DELAY - (ABSOLUTE - (PORT datab (240:240:240) (286:286:286)) - (PORT datac (548:548:548) (560:560:560)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT asdata (870:870:870) (882:882:882)) - (PORT clrn (1597:1597:1597) (1572:1572:1572)) - (PORT ena (2143:2143:2143) (2210:2210:2210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~4) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (429:429:429)) - (PORT datab (1153:1153:1153) (1183:1183:1183)) - (PORT datac (963:963:963) (1032:1032:1032)) - (PORT datad (244:244:244) (316:316:316)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (392:392:392)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (340:340:340) (367:367:367)) - (PORT datad (324:324:324) (346:346:346)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (265:265:265) (352:352:352)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (332:332:332) (358:358:358)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1239:1239:1239) (1260:1260:1260)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1236:1236:1236) (1256:1256:1256)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (258:258:258) (310:310:310)) - (PORT datad (228:228:228) (266:266:266)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (663:663:663)) - (PORT datab (1133:1133:1133) (1182:1182:1182)) - (PORT datad (630:630:630) (644:644:644)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1202:1202:1202) (1222:1222:1222)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1206:1206:1206) (1227:1227:1227)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (408:408:408) (466:466:466)) - (PORT datab (591:591:591) (631:631:631)) - (PORT datad (218:218:218) (288:288:288)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1505:1505:1505) (1518:1518:1518)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (958:958:958) (967:967:967)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (960:960:960) (969:969:969)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (467:467:467) (505:505:505)) - (PORT datab (668:668:668) (703:703:703)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (665:665:665)) - (PORT datab (920:920:920) (943:943:943)) - (PORT datac (213:213:213) (288:288:288)) - (PORT datad (335:335:335) (356:356:356)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (993:993:993) (1020:1020:1020)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (995:995:995) (1022:1022:1022)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (875:875:875) (922:922:922)) - (PORT datab (965:965:965) (1021:1021:1021)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (984:984:984) (1006:1006:1006)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (982:982:982) (1003:1003:1003)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (700:700:700)) - (PORT datab (396:396:396) (436:436:436)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (875:875:875) (882:882:882)) - (PORT ena (1407:1407:1407) (1382:1382:1382)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (527:527:527) (547:547:547)) - (PORT datad (825:825:825) (835:835:835)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (377:377:377)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1018:1018:1018) (1019:1019:1019)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (856:856:856) (875:875:875)) - (PORT datac (1094:1094:1094) (1126:1126:1126)) - (PORT datad (1162:1162:1162) (1190:1190:1190)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1359:1359:1359) (1370:1370:1370)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (911:911:911)) - (PORT datab (1236:1236:1236) (1275:1275:1275)) - (PORT datad (664:664:664) (688:688:688)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (624:624:624) (675:675:675)) - (PORT datac (704:704:704) (739:739:739)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (401:401:401)) - (PORT datab (959:959:959) (1001:1001:1001)) - (PORT datac (682:682:682) (721:721:721)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[4\]) - (DELAY - (ABSOLUTE - (PORT datab (238:238:238) (283:283:283)) - (PORT datad (529:529:529) (540:540:540)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT asdata (852:852:852) (858:858:858)) - (PORT clrn (1597:1597:1597) (1572:1572:1572)) - (PORT ena (2143:2143:2143) (2210:2210:2210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1182:1182:1182)) - (PORT datab (985:985:985) (1022:1022:1022)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (770:770:770)) - (PORT datab (1162:1162:1162) (1199:1199:1199)) - (PORT datac (626:626:626) (647:647:647)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (879:879:879) (891:891:891)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (878:878:878) (893:893:893)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (966:966:966) (1022:1022:1022)) - (PORT datad (843:843:843) (873:873:873)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (692:692:692) (715:715:715)) - (PORT ena (1477:1477:1477) (1472:1472:1472)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (692:692:692) (713:713:713)) - (PORT ena (1247:1247:1247) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1134:1134:1134)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (658:658:658) (679:679:679)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1437:1437:1437) (1460:1460:1460)) - (PORT ena (1505:1505:1505) (1518:1518:1518)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1457:1457:1457) (1472:1472:1472)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (458:458:458) (494:494:494)) - (PORT datab (1132:1132:1132) (1177:1177:1177)) - (PORT datad (626:626:626) (636:636:636)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) - (DELAY - (ABSOLUTE - (PORT datab (918:918:918) (940:940:940)) - (PORT datad (338:338:338) (359:359:359)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1214:1214:1214) (1217:1217:1217)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1214:1214:1214) (1215:1215:1215)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (467:467:467)) - (PORT datab (592:592:592) (632:632:632)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1471:1471:1471) (1477:1477:1477)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (607:607:607) (622:622:622)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (693:693:693)) - (PORT datab (390:390:390) (429:429:429)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (853:853:853) (859:859:859)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1407:1407:1407) (1382:1382:1382)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1457:1457:1457) (1474:1474:1474)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (574:574:574) (638:638:638)) - (PORT datab (836:836:836) (860:860:860)) - (PORT datad (645:645:645) (669:669:669)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (656:656:656)) - (PORT datab (1118:1118:1118) (1148:1148:1148)) - (PORT datac (339:339:339) (359:359:359)) - (PORT datad (587:587:587) (601:601:601)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (394:394:394)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (175:175:175) (202:202:202)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (699:699:699)) - (PORT datab (929:929:929) (992:992:992)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1608:1608:1608) (1611:1611:1611)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1227:1227:1227) (1243:1243:1243)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1190:1190:1190) (1197:1197:1197)) - (PORT datab (1236:1236:1236) (1275:1275:1275)) - (PORT datad (664:664:664) (688:688:688)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (275:275:275)) - (PORT datac (613:613:613) (632:632:632)) - (PORT datad (219:219:219) (288:288:288)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (670:670:670)) - (PORT datab (1331:1331:1331) (1335:1335:1335)) - (PORT datac (192:192:192) (224:224:224)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[5\]) - (DELAY - (ABSOLUTE - (PORT datac (653:653:653) (693:693:693)) - (PORT datad (834:834:834) (843:843:843)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2152:2152:2152) (2220:2220:2220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~4) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (994:994:994)) - (PORT datab (1154:1154:1154) (1178:1178:1178)) - (PORT datac (960:960:960) (1026:1026:1026)) - (PORT datad (362:362:362) (387:387:387)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (687:687:687)) - (PORT datab (1161:1161:1161) (1198:1198:1198)) - (PORT datac (811:811:811) (865:865:865)) - (PORT datad (615:615:615) (643:643:643)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1676:1676:1676) (1684:1684:1684)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1342:1342:1342) (1345:1345:1345)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (918:918:918)) - (PORT datab (966:966:966) (1020:1020:1020)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (1896:1896:1896) (1881:1881:1881)) - (PORT ena (1477:1477:1477) (1472:1472:1472)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (1893:1893:1893) (1878:1878:1878)) - (PORT ena (1247:1247:1247) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (1092:1092:1092) (1133:1133:1133)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (654:654:654) (676:676:676)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (2168:2168:2168) (2154:2154:2154)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1053:1053:1053) (1073:1073:1073)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (435:435:435) (470:470:470)) - (PORT datab (637:637:637) (669:669:669)) - (PORT datad (374:374:374) (432:432:432)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1463:1463:1463) (1454:1454:1454)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (689:689:689) (771:771:771)) - (PORT datab (945:945:945) (995:995:995)) - (PORT datac (878:878:878) (894:894:894)) - (PORT datad (606:606:606) (625:625:625)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (2168:2168:2168) (2153:2153:2153)) - (PORT ena (1499:1499:1499) (1507:1507:1507)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1302:1302:1302) (1310:1310:1310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1608:1608:1608) (1628:1628:1628)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (503:503:503)) - (PORT datab (242:242:242) (324:324:324)) - (PORT datad (640:640:640) (666:666:666)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) - (DELAY - (ABSOLUTE - (PORT datab (1410:1410:1410) (1425:1425:1425)) - (PORT datad (563:563:563) (574:574:574)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) - (DELAY - (ABSOLUTE - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1342:1342:1342) (1366:1366:1366)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1430:1430:1430) (1466:1466:1466)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (471:471:471)) - (PORT datab (584:584:584) (622:622:622)) - (PORT datad (835:835:835) (900:900:900)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (399:399:399)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (794:794:794) (791:791:791)) - (PORT datad (776:776:776) (774:774:774)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (625:625:625)) - (PORT datab (658:658:658) (716:716:716)) - (PORT datac (1393:1393:1393) (1416:1416:1416)) - (PORT datad (599:599:599) (618:618:618)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (967:967:967) (1025:1025:1025)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1322:1322:1322) (1350:1350:1350)) - (PORT datab (1232:1232:1232) (1270:1270:1270)) - (PORT datad (660:660:660) (687:687:687)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (673:673:673) (705:705:705)) - (PORT datac (668:668:668) (749:749:749)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (760:760:760)) - (PORT datab (648:648:648) (689:689:689)) - (PORT datac (926:926:926) (965:965:965)) - (PORT datad (593:593:593) (644:644:644)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[6\]) - (DELAY - (ABSOLUTE - (PORT datac (652:652:652) (694:694:694)) - (PORT datad (819:819:819) (838:838:838)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2152:2152:2152) (2220:2220:2220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (670:670:670)) - (PORT datab (632:632:632) (673:673:673)) - (PORT datac (811:811:811) (863:863:863)) - (PORT datad (1165:1165:1165) (1193:1193:1193)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (1158:1158:1158) (1194:1194:1194)) - (PORT datac (628:628:628) (651:651:651)) - (PORT datad (616:616:616) (644:644:644)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (515:515:515)) - (PORT datad (190:190:190) (222:222:222)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (708:708:708) (752:752:752)) - (PORT datab (962:962:962) (1002:1002:1002)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (619:619:619) (645:645:645)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (1212:1212:1212) (1251:1251:1251)) - (PORT ena (1477:1477:1477) (1472:1472:1472)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (1211:1211:1211) (1254:1254:1254)) - (PORT ena (1247:1247:1247) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (1092:1092:1092) (1137:1137:1137)) - (PORT datab (243:243:243) (325:325:325)) - (PORT datad (656:656:656) (679:679:679)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1408:1408:1408) (1437:1437:1437)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1410:1410:1410) (1439:1439:1439)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (876:876:876) (924:924:924)) - (PORT datab (963:963:963) (1013:1013:1013)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1934:1934:1934) (1968:1968:1968)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1624:1624:1624) (1645:1645:1645)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (435:435:435) (469:469:469)) - (PORT datab (636:636:636) (669:669:669)) - (PORT datad (370:370:370) (429:429:429)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1932:1932:1932) (1967:1967:1967)) - (PORT ena (1499:1499:1499) (1507:1507:1507)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1954:1954:1954) (1989:1989:1989)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1954:1954:1954) (1989:1989:1989)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (459:459:459) (495:495:495)) - (PORT datab (241:241:241) (322:322:322)) - (PORT datad (640:640:640) (664:664:664)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) - (DELAY - (ABSOLUTE - (PORT datab (1411:1411:1411) (1427:1427:1427)) - (PORT datad (587:587:587) (598:598:598)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1731:1731:1731) (1772:1772:1772)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1730:1730:1730) (1774:1774:1774)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (407:407:407) (467:467:467)) - (PORT datab (591:591:591) (631:631:631)) - (PORT datad (216:216:216) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1463:1463:1463) (1454:1454:1454)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (738:738:738)) - (PORT datab (944:944:944) (996:996:996)) - (PORT datac (844:844:844) (845:845:845)) - (PORT datad (606:606:606) (623:623:623)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (496:496:496) (503:503:503)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (364:364:364) (385:385:385)) - (PORT datad (573:573:573) (586:586:586)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~92) - (DELAY - (ABSOLUTE - (PORT dataa (667:667:667) (723:723:723)) - (PORT datab (660:660:660) (704:704:704)) - (PORT datac (1391:1391:1391) (1414:1414:1414)) - (PORT datad (597:597:597) (618:618:618)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[7\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1484:1484:1484) (1528:1528:1528)) - (PORT datab (1645:1645:1645) (1711:1711:1711)) - (PORT datac (872:872:872) (914:914:914)) - (PORT datad (1163:1163:1163) (1203:1203:1203)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im2) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1550:1550:1550)) - (PORT ena (1258:1258:1258) (1280:1280:1280)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (492:492:492)) - (PORT datac (1227:1227:1227) (1295:1295:1295)) - (PORT datad (274:274:274) (356:356:356)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (494:494:494)) - (PORT datab (716:716:716) (747:747:747)) - (PORT datac (192:192:192) (224:224:224)) - (PORT datad (1301:1301:1301) (1395:1395:1395)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (881:881:881) (903:903:903)) - (PORT datab (928:928:928) (957:957:957)) - (PORT datac (631:631:631) (687:687:687)) - (PORT datad (632:632:632) (647:647:647)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (841:841:841) (861:861:861)) - (PORT datab (852:852:852) (879:879:879)) - (PORT datac (900:900:900) (940:940:940)) - (PORT datad (639:639:639) (700:700:700)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datab (244:244:244) (291:291:291)) - (PORT datac (645:645:645) (698:698:698)) - (PORT datad (617:617:617) (628:628:628)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (693:693:693) (738:738:738)) - (PORT datab (889:889:889) (932:932:932)) - (PORT datac (869:869:869) (862:862:862)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1252:1252:1252) (1344:1344:1344)) - (PORT datab (857:857:857) (911:911:911)) - (PORT datac (614:614:614) (652:652:652)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (843:843:843) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1466:1466:1466) (1594:1594:1594)) - (PORT datab (1469:1469:1469) (1553:1553:1553)) - (PORT datac (1102:1102:1102) (1148:1148:1148)) - (PORT datad (647:647:647) (684:684:684)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1119:1119:1119) (1156:1156:1156)) - (PORT datab (747:747:747) (772:772:772)) - (PORT datac (1394:1394:1394) (1464:1464:1464)) - (PORT datad (1189:1189:1189) (1225:1225:1225)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (1006:1006:1006)) - (PORT datab (1150:1150:1150) (1220:1220:1220)) - (PORT datac (733:733:733) (829:829:829)) - (PORT datad (1883:1883:1883) (2044:2044:2044)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (737:737:737) (802:802:802)) - (PORT datab (1392:1392:1392) (1509:1509:1509)) - (PORT datac (1112:1112:1112) (1157:1157:1157)) - (PORT datad (198:198:198) (235:235:235)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (653:653:653) (668:668:668)) - (PORT datab (819:819:819) (840:840:840)) - (PORT datac (1123:1123:1123) (1137:1137:1137)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (696:696:696)) - (PORT datab (1031:1031:1031) (1083:1083:1083)) - (PORT datac (562:562:562) (584:584:584)) - (PORT datad (901:901:901) (957:957:957)) + (PORT dataa (1212:1212:1212) (1288:1288:1288)) + (PORT datab (627:627:627) (676:676:676)) + (PORT datac (1171:1171:1171) (1187:1187:1187)) + (PORT datad (1954:1954:1954) (2068:2068:2068)) (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -26362,47 +3827,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (INSTANCE z80_\|execute_\|fIOWrite\~0) (DELAY (ABSOLUTE - (PORT dataa (704:704:704) (741:741:741)) - (PORT datab (618:618:618) (633:633:633)) - (PORT datac (237:237:237) (315:315:315)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1120:1120:1120) (1156:1156:1156)) - (PORT datab (746:746:746) (770:770:770)) - (PORT datac (899:899:899) (956:956:956)) - (PORT datad (1169:1169:1169) (1206:1206:1206)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1433:1433:1433) (1488:1488:1488)) - (PORT datab (677:677:677) (711:711:711)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1402:1402:1402) (1440:1440:1440)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (1205:1205:1205) (1328:1328:1328)) + (PORT datab (1374:1374:1374) (1512:1512:1512)) + (PORT datac (2247:2247:2247) (2354:2354:2354)) + (PORT datad (2399:2399:2399) (2556:2556:2556)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -26410,157 +3843,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) + (INSTANCE z80_\|execute_\|fMWrite\~6) (DELAY (ABSOLUTE - (PORT dataa (1422:1422:1422) (1463:1463:1463)) - (PORT datab (746:746:746) (770:770:770)) - (PORT datac (1125:1125:1125) (1193:1193:1193)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (496:496:496)) - (PORT datab (268:268:268) (357:357:357)) - (PORT datac (230:230:230) (313:313:313)) - (PORT datad (609:609:609) (655:655:655)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (908:908:908)) - (PORT datab (730:730:730) (816:816:816)) - (PORT datad (395:395:395) (453:453:453)) + (PORT dataa (810:810:810) (885:885:885)) + (PORT datab (1869:1869:1869) (2005:2005:2005)) + (PORT datac (325:325:325) (347:347:347)) + (PORT datad (1684:1684:1684) (1756:1756:1756)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) - (DELAY - (ABSOLUTE - (PORT dataa (422:422:422) (513:513:513)) - (PORT datab (390:390:390) (465:465:465)) - (PORT datac (675:675:675) (735:735:735)) - (PORT datad (679:679:679) (752:752:752)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) - (DELAY - (ABSOLUTE - (PORT dataa (269:269:269) (367:367:367)) - (PORT datab (598:598:598) (665:665:665)) - (PORT datac (245:245:245) (334:334:334)) - (PORT datad (371:371:371) (425:425:425)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (599:599:599)) - (PORT datab (914:914:914) (923:923:923)) - (PORT datac (565:565:565) (580:580:580)) - (PORT datad (307:307:307) (323:323:323)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1424:1424:1424) (1466:1466:1466)) - (PORT datab (1535:1535:1535) (1597:1597:1597)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1559:1559:1559)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1118:1118:1118) (1158:1158:1158)) - (PORT datab (675:675:675) (710:710:710)) - (PORT datac (900:900:900) (960:960:960)) - (PORT datad (1167:1167:1167) (1206:1206:1206)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) - (DELAY - (ABSOLUTE - (PORT dataa (979:979:979) (1040:1040:1040)) - (PORT datab (271:271:271) (356:356:356)) - (PORT datac (1122:1122:1122) (1190:1190:1190)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -26568,202 +3859,59 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) + (INSTANCE z80_\|execute_\|ctl_mWrite\~8) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (746:746:746) (769:769:769)) - (PORT datac (1390:1390:1390) (1425:1425:1425)) - (PORT datad (245:245:245) (316:316:316)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1349:1349:1349) (1393:1393:1393)) + (PORT datab (650:650:650) (695:695:695)) + (PORT datac (2228:2228:2228) (2301:2301:2301)) + (PORT datad (2014:2014:2014) (2108:2108:2108)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~5) (DELAY (ABSOLUTE - (PORT clk (1518:1518:1518) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1287:1287:1287)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT dataa (1206:1206:1206) (1327:1327:1327)) + (PORT datab (1429:1429:1429) (1544:1544:1544)) + (PORT datac (2248:2248:2248) (2352:2352:2352)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) (DELAY (ABSOLUTE (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (545:545:545) (570:570:570)) - (PORT datab (213:213:213) (257:257:257)) - (PORT datac (177:177:177) (214:214:214)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (813:813:813) (826:826:826)) - (PORT datac (328:328:328) (358:358:358)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (381:381:381)) - (PORT datab (662:662:662) (697:697:697)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1118:1118:1118) (1161:1161:1161)) - (PORT datab (1154:1154:1154) (1224:1224:1224)) - (PORT datac (1392:1392:1392) (1427:1427:1427)) - (PORT datad (1169:1169:1169) (1209:1209:1209)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) - (DELAY - (ABSOLUTE - (PORT dataa (933:933:933) (998:998:998)) - (PORT datab (748:748:748) (772:772:772)) - (PORT datac (646:646:646) (675:675:675)) + (PORT datab (363:363:363) (394:394:394)) + (PORT datac (810:810:810) (838:838:838)) (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (1374:1374:1374) (1429:1429:1429)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~10) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (341:341:341) (367:367:367)) - (PORT datac (1214:1214:1214) (1255:1255:1255)) - (PORT datad (677:677:677) (698:698:698)) - (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) + (INSTANCE z80_\|execute_\|fMRead\~3) (DELAY (ABSOLUTE - (PORT dataa (922:922:922) (946:946:946)) - (PORT datab (2012:2012:2012) (2066:2066:2066)) - (PORT datac (919:919:919) (1015:1015:1015)) - (PORT datad (863:863:863) (877:877:877)) + (PORT dataa (1654:1654:1654) (1725:1725:1725)) + (PORT datac (907:907:907) (930:930:930)) + (PORT datad (1391:1391:1391) (1460:1460:1460)) (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~2) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (447:447:447)) - (PORT datab (1195:1195:1195) (1198:1198:1198)) - (PORT datac (601:601:601) (607:607:607)) - (PORT datad (334:334:334) (359:359:359)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -26771,1773 +3919,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_12) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) (DELAY (ABSOLUTE - (PORT dataa (825:825:825) (855:855:855)) - (PORT datad (337:337:337) (354:354:354)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (278:278:278)) - (PORT datab (223:223:223) (271:271:271)) - (PORT datac (616:616:616) (645:645:645)) - (PORT datad (216:216:216) (258:258:258)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (621:621:621)) - (PORT datab (686:686:686) (701:701:701)) - (PORT datac (562:562:562) (583:583:583)) - (PORT datad (312:312:312) (322:322:322)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (661:661:661)) - (PORT datab (654:654:654) (674:674:674)) - (PORT datac (240:240:240) (317:317:317)) - (PORT datad (385:385:385) (407:407:407)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (692:692:692)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (610:610:610) (651:651:651)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1530:1530:1530)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1244:1244:1244) (1250:1250:1250)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1638:1638:1638) (1703:1703:1703)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (884:884:884) (949:949:949)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (747:747:747)) - (PORT datab (659:659:659) (717:717:717)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1816:1816:1816) (1911:1911:1911)) - (PORT datab (2014:2014:2014) (2068:2068:2068)) - (PORT datad (173:173:173) (199:199:199)) + (PORT dataa (1571:1571:1571) (1642:1642:1642)) + (PORT datab (2001:2001:2001) (2042:2042:2042)) + (PORT datac (1133:1133:1133) (1159:1159:1159)) + (PORT datad (197:197:197) (223:223:223)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|flags_cond_true) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1527:1527:1527)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (663:663:663)) - (PORT datab (1772:1772:1772) (1863:1863:1863)) - (PORT datac (1815:1815:1815) (1893:1893:1893)) - (PORT datad (552:552:552) (570:570:570)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (256:256:256)) - (PORT datab (230:230:230) (280:280:280)) - (PORT datac (563:563:563) (592:592:592)) - (PORT datad (181:181:181) (211:211:211)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (905:905:905)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datac (623:623:623) (650:650:650)) - (PORT datad (1193:1193:1193) (1247:1247:1247)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (658:658:658)) - (PORT datab (949:949:949) (994:994:994)) - (PORT datad (671:671:671) (699:699:699)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (694:694:694)) - (PORT datab (517:517:517) (537:537:537)) - (PORT datac (742:742:742) (744:744:744)) - (PORT datad (1107:1107:1107) (1107:1107:1107)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (545:545:545) (573:573:573)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (580:580:580) (606:606:606)) - (PORT datad (621:621:621) (643:643:643)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (242:242:242)) - (PORT datab (259:259:259) (310:310:310)) - (PORT datac (607:607:607) (617:617:617)) - (PORT datad (236:236:236) (276:276:276)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1881:1881:1881) (1885:1885:1885)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1836:1836:1836) (1841:1841:1841)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (434:434:434) (465:465:465)) - (PORT datab (378:378:378) (448:448:448)) - (PORT datad (608:608:608) (629:629:629)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1836:1836:1836) (1841:1841:1841)) - (PORT ena (1499:1499:1499) (1507:1507:1507)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (2122:2122:2122) (2138:2138:2138)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT asdata (2124:2124:2124) (2160:2160:2160)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (498:498:498)) - (PORT datab (667:667:667) (706:706:706)) - (PORT datad (632:632:632) (685:685:685)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (1411:1411:1411) (1423:1423:1423)) - (PORT datad (585:585:585) (594:594:594)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1880:1880:1880) (1884:1884:1884)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (709:709:709)) - (PORT datab (945:945:945) (994:994:994)) - (PORT datac (888:888:888) (910:910:910)) - (PORT datad (609:609:609) (625:625:625)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1630:1630:1630) (1644:1644:1644)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (823:823:823) (864:864:864)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (473:473:473)) - (PORT datab (583:583:583) (621:621:621)) - (PORT datad (584:584:584) (628:628:628)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (551:551:551) (556:556:556)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1532:1532:1532) (1549:1549:1549)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1857:1857:1857) (1863:1863:1863)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (328:328:328)) - (PORT datab (962:962:962) (1016:1016:1016)) - (PORT datad (847:847:847) (873:873:873)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (712:712:712) (740:740:740)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (712:712:712) (740:740:740)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (329:329:329)) - (PORT datab (263:263:263) (316:316:316)) - (PORT datad (234:234:234) (273:273:273)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (684:684:684) (726:726:726)) - (PORT datab (635:635:635) (674:674:674)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1349:1349:1349) (1373:1373:1373)) - (PORT datab (623:623:623) (653:653:653)) - (PORT datac (643:643:643) (694:694:694)) - (PORT datad (308:308:308) (323:323:323)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1481:1481:1481) (1531:1531:1531)) - (PORT datab (1644:1644:1644) (1715:1715:1715)) - (PORT datac (1522:1522:1522) (1538:1538:1538)) - (PORT datad (1165:1165:1165) (1205:1205:1205)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (978:978:978) (996:996:996)) - (PORT datab (878:878:878) (913:913:913)) - (PORT datac (923:923:923) (978:978:978)) - (PORT datad (879:879:879) (914:914:914)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (696:696:696) (721:721:721)) - (PORT datab (1150:1150:1150) (1186:1186:1186)) - (PORT datac (887:887:887) (975:975:975)) - (PORT datad (1184:1184:1184) (1219:1219:1219)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (248:248:248)) - (PORT datab (943:943:943) (996:996:996)) - (PORT datac (648:648:648) (674:674:674)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1303:1303:1303) (1352:1352:1352)) - (PORT datab (933:933:933) (975:975:975)) - (PORT datac (1446:1446:1446) (1491:1491:1491)) - (PORT datad (926:926:926) (983:983:983)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (248:248:248)) - (PORT datab (986:986:986) (1033:1033:1033)) - (PORT datac (900:900:900) (933:933:933)) - (PORT datad (222:222:222) (267:267:267)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1695:1695:1695) (1783:1783:1783)) - (PORT datac (897:897:897) (925:925:925)) - (PORT datad (364:364:364) (385:385:385)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (926:926:926) (952:952:952)) - (PORT datad (237:237:237) (274:274:274)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1212:1212:1212)) - (PORT datab (286:286:286) (347:347:347)) - (PORT datac (254:254:254) (311:311:311)) - (PORT datad (254:254:254) (300:300:300)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (432:432:432) (525:525:525)) - (PORT datab (1170:1170:1170) (1217:1217:1217)) - (PORT datac (1156:1156:1156) (1212:1212:1212)) - (PORT datad (661:661:661) (724:724:724)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1535:1535:1535)) - (PORT asdata (672:672:672) (698:698:698)) - (PORT ena (1283:1283:1283) (1287:1287:1287)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (638:638:638)) - (PORT datab (368:368:368) (389:389:389)) - (PORT datad (1139:1139:1139) (1146:1146:1146)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (597:597:597)) - (PORT datab (220:220:220) (258:258:258)) - (PORT datac (1124:1124:1124) (1146:1146:1146)) - (PORT datad (335:335:335) (355:355:355)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1292:1292:1292) (1345:1345:1345)) - (PORT datab (915:915:915) (937:937:937)) - (PORT datac (1123:1123:1123) (1144:1144:1144)) - (PORT datad (945:945:945) (995:995:995)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (964:964:964) (1020:1020:1020)) - (PORT datac (806:806:806) (813:813:813)) - (PORT datad (227:227:227) (273:273:273)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (999:999:999)) - (PORT datac (1663:1663:1663) (1739:1739:1739)) - (PORT datad (1415:1415:1415) (1442:1442:1442)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datac (902:902:902) (931:931:931)) - (PORT datad (239:239:239) (281:281:281)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1211:1211:1211)) - (PORT datab (286:286:286) (349:349:349)) - (PORT datac (255:255:255) (313:313:313)) - (PORT datad (248:248:248) (293:293:293)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (671:671:671) (728:728:728)) - (PORT datab (1171:1171:1171) (1217:1217:1217)) - (PORT datac (615:615:615) (673:673:673)) - (PORT datad (661:661:661) (723:723:723)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1535:1535:1535)) - (PORT asdata (1127:1127:1127) (1132:1132:1132)) - (PORT ena (1283:1283:1283) (1287:1287:1287)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (549:549:549) (578:578:578)) - (PORT datab (331:331:331) (362:362:362)) - (PORT datad (1138:1138:1138) (1145:1145:1145)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (703:703:703)) - (PORT datab (359:359:359) (389:389:389)) - (PORT datac (797:797:797) (800:800:800)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (588:588:588) (619:619:619)) - (PORT datab (968:968:968) (1015:1015:1015)) - (PORT datac (371:371:371) (403:403:403)) - (PORT datad (863:863:863) (917:917:917)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (681:681:681) (721:721:721)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (264:264:264) (346:346:346)) - (PORT datac (235:235:235) (311:311:311)) - (PORT datad (235:235:235) (303:303:303)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) - (DELAY - (ABSOLUTE - (PORT datac (852:852:852) (861:861:861)) - (PORT datad (679:679:679) (700:700:700)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (690:690:690) (732:732:732)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datad (621:621:621) (632:632:632)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_hf2) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1183:1183:1183) (1231:1231:1231)) - (PORT datab (681:681:681) (697:697:697)) - (PORT datac (1123:1123:1123) (1203:1203:1203)) - (PORT datad (667:667:667) (721:721:721)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1196:1196:1196) (1252:1252:1252)) - (PORT datab (1640:1640:1640) (1708:1708:1708)) - (PORT datac (1440:1440:1440) (1482:1482:1482)) - (PORT datad (844:844:844) (890:890:890)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (686:686:686)) - (PORT datab (928:928:928) (956:956:956)) - (PORT datac (630:630:630) (688:688:688)) - (PORT datad (848:848:848) (847:847:847)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (856:856:856)) - (PORT datab (904:904:904) (946:946:946)) - (PORT datac (412:412:412) (479:479:479)) - (PORT datad (832:832:832) (862:862:862)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (712:712:712)) - (PORT datab (943:943:943) (996:996:996)) - (PORT datac (576:576:576) (598:598:598)) - (PORT datad (316:316:316) (337:337:337)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1305:1305:1305) (1357:1357:1357)) - (PORT datab (967:967:967) (1024:1024:1024)) - (PORT datac (922:922:922) (952:952:952)) - (PORT datad (1557:1557:1557) (1610:1610:1610)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (642:642:642)) - (PORT datab (987:987:987) (1034:1034:1034)) - (PORT datac (175:175:175) (210:210:210)) - (PORT datad (221:221:221) (266:266:266)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1693:1693:1693) (1778:1778:1778)) - (PORT datab (916:916:916) (942:942:942)) - (PORT datac (904:904:904) (929:929:929)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1446:1446:1446) (1487:1487:1487)) - (PORT datab (1129:1129:1129) (1183:1183:1183)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (234:234:234) (275:275:275)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (274:274:274)) - (PORT datab (246:246:246) (301:301:301)) - (PORT datac (617:617:617) (647:647:647)) - (PORT datad (845:845:845) (875:875:875)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (549:549:549) (580:580:580)) - (PORT datab (714:714:714) (753:753:753)) - (PORT datac (601:601:601) (608:608:608)) - (PORT datad (865:865:865) (915:915:915)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (718:718:718)) - (PORT datab (1128:1128:1128) (1175:1175:1175)) - (PORT datac (587:587:587) (617:617:617)) - (PORT datad (401:401:401) (459:459:459)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (261:261:261) (336:336:336)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (559:559:559) (578:578:578)) - (PORT datad (903:903:903) (954:954:954)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (460:460:460) (538:538:538)) - (PORT datab (638:638:638) (705:705:705)) - (PORT datac (1102:1102:1102) (1133:1133:1133)) - (PORT datad (662:662:662) (719:719:719)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1287:1287:1287)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (368:368:368)) - (PORT datab (597:597:597) (636:636:636)) - (PORT datac (965:965:965) (999:999:999)) - (PORT datad (590:590:590) (645:645:645)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (276:276:276)) - (PORT datab (653:653:653) (675:675:675)) - (PORT datac (916:916:916) (949:949:949)) - (PORT datad (220:220:220) (264:264:264)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (263:263:263) (337:337:337)) - (PORT datab (596:596:596) (614:614:614)) - (PORT datac (585:585:585) (589:589:589)) - (PORT datad (896:896:896) (944:944:944)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (534:534:534)) - (PORT datab (695:695:695) (720:720:720)) - (PORT datac (877:877:877) (900:900:900)) - (PORT datad (417:417:417) (490:490:490)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (411:411:411)) - (PORT datab (395:395:395) (424:424:424)) - (PORT datac (177:177:177) (214:214:214)) - (PORT datad (345:345:345) (368:368:368)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (407:407:407)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (354:354:354) (383:383:383)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1176:1176:1176) (1207:1207:1207)) - (PORT datab (281:281:281) (344:344:344)) - (PORT datac (244:244:244) (303:303:303)) - (PORT datad (255:255:255) (301:301:301)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1695:1695:1695) (1779:1779:1779)) - (PORT datac (887:887:887) (904:904:904)) - (PORT datad (883:883:883) (900:900:900)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (911:911:911) (960:960:960)) - (PORT datad (237:237:237) (277:277:277)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (711:711:711)) - (PORT datab (1166:1166:1166) (1213:1213:1213)) - (PORT datac (421:421:421) (493:493:493)) - (PORT datad (662:662:662) (719:719:719)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (1116:1116:1116) (1164:1164:1164)) - (PORT datac (603:603:603) (622:622:622)) - (PORT datad (629:629:629) (654:654:654)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1253:1253:1253) (1347:1347:1347)) - (PORT datab (239:239:239) (295:295:295)) - (PORT datac (959:959:959) (993:993:993)) - (PORT datad (329:329:329) (348:348:348)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1295:1295:1295) (1347:1347:1347)) - (PORT datab (963:963:963) (1021:1021:1021)) - (PORT datac (1621:1621:1621) (1653:1653:1653)) - (PORT datad (867:867:867) (886:886:886)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (667:667:667)) - (PORT datab (983:983:983) (1034:1034:1034)) - (PORT datac (313:313:313) (343:343:343)) - (PORT datad (228:228:228) (273:273:273)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (465:465:465)) - (PORT datab (263:263:263) (345:345:345)) - (PORT datac (236:236:236) (312:312:312)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1227:1227:1227)) - (PORT datab (658:658:658) (671:671:671)) - (PORT datac (632:632:632) (691:691:691)) - (PORT datad (234:234:234) (310:310:310)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1213:1213:1213)) - (PORT datab (894:894:894) (942:942:942)) - (PORT datac (660:660:660) (687:687:687)) - (PORT datad (883:883:883) (901:901:901)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (924:924:924) (933:933:933)) - (PORT datac (1121:1121:1121) (1153:1153:1153)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1018:1018:1018)) - (PORT datab (950:950:950) (1001:1001:1001)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (876:876:876) (911:911:911)) - (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (689:689:689) (714:714:714)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (1597:1597:1597) (1627:1627:1627)) - (PORT datad (861:861:861) (875:875:875)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (655:655:655)) - (PORT datab (1245:1245:1245) (1272:1272:1272)) - (PORT datac (1147:1147:1147) (1195:1195:1195)) - (PORT datad (336:336:336) (365:365:365)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) - (DELAY - (ABSOLUTE - (PORT datab (287:287:287) (348:348:348)) - (PORT datad (249:249:249) (295:295:295)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im1) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1550:1550:1550)) - (PORT ena (1258:1258:1258) (1280:1280:1280)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1215:1215:1215) (1260:1260:1260)) - (PORT datab (1208:1208:1208) (1291:1291:1291)) - (PORT datac (1222:1222:1222) (1290:1290:1290)) - (PORT datad (272:272:272) (349:349:349)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (485:485:485)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (1143:1143:1143) (1174:1174:1174)) - (PORT datad (1174:1174:1174) (1212:1212:1212)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (993:993:993) (1051:1051:1051)) - (PORT datab (1152:1152:1152) (1212:1212:1212)) - (PORT datac (671:671:671) (716:716:716)) - (PORT datad (621:621:621) (670:670:670)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (864:864:864) (885:885:885)) - (PORT datac (946:946:946) (986:986:986)) - (PORT datad (214:214:214) (249:249:249)) - (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28545,127 +3935,79 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~37) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) (DELAY (ABSOLUTE - (PORT dataa (1300:1300:1300) (1399:1399:1399)) - (PORT datab (2075:2075:2075) (2259:2259:2259)) - (PORT datac (822:822:822) (879:879:879)) - (PORT datad (913:913:913) (964:964:964)) + (PORT dataa (2683:2683:2683) (2764:2764:2764)) + (PORT datab (1030:1030:1030) (1061:1061:1061)) + (PORT datac (798:798:798) (876:876:876)) + (PORT datad (715:715:715) (740:740:740)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (624:624:624)) + (PORT datab (789:789:789) (834:834:834)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (1008:1008:1008)) + (PORT datab (1184:1184:1184) (1250:1250:1250)) + (PORT datac (1904:1904:1904) (1966:1966:1966)) + (PORT datad (644:644:644) (669:669:669)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1681:1681:1681) (1756:1756:1756)) + (PORT datab (574:574:574) (580:580:580)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (352:352:352) (375:375:375)) (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1269:1269:1269) (1304:1304:1304)) - (PORT datac (1404:1404:1404) (1456:1456:1456)) - (PORT datad (913:913:913) (977:977:977)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (241:241:241) (281:281:281)) - (PORT datac (1941:1941:1941) (2072:2072:2072)) - (PORT datad (187:187:187) (218:218:218)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (875:875:875) (914:914:914)) - (PORT datab (230:230:230) (277:277:277)) - (PORT datac (631:631:631) (653:653:653)) - (PORT datad (955:955:955) (999:999:999)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1051:1051:1051) (1095:1095:1095)) - (PORT datab (1067:1067:1067) (1105:1105:1105)) - (PORT datac (1033:1033:1033) (1064:1064:1064)) - (PORT datad (634:634:634) (644:644:644)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~55) - (DELAY - (ABSOLUTE - (PORT dataa (960:960:960) (1056:1056:1056)) - (PORT datab (1130:1130:1130) (1132:1132:1132)) - (PORT datac (939:939:939) (1031:1031:1031)) - (PORT datad (1060:1060:1060) (1062:1062:1062)) - (IOPATH dataa combout (303:303:303) (299:299:299)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~38) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) (DELAY (ABSOLUTE - (PORT dataa (888:888:888) (940:940:940)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (539:539:539) (555:555:555)) - (PORT datad (545:545:545) (556:556:556)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (715:715:715)) - (PORT datab (898:898:898) (929:929:929)) - (PORT datac (1980:1980:1980) (2019:2019:2019)) - (PORT datad (830:830:830) (842:842:842)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (379:379:379) (418:418:418)) + (PORT datab (925:925:925) (988:988:988)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1103:1103:1103) (1103:1103:1103)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28673,12 +4015,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~3) + (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) (DELAY (ABSOLUTE - (PORT datab (833:833:833) (894:894:894)) - (PORT datac (622:622:622) (675:675:675)) - (PORT datad (207:207:207) (239:239:239)) + (PORT datab (1374:1374:1374) (1494:1494:1494)) + (PORT datad (976:976:976) (1058:1058:1058)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (657:657:657)) + (PORT datab (814:814:814) (879:879:879)) + (PORT datac (1743:1743:1743) (1807:1807:1807)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -28687,29 +4043,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~31) + (INSTANCE z80_\|execute_\|fMWrite\~7) (DELAY (ABSOLUTE - (PORT dataa (231:231:231) (279:279:279)) - (PORT datab (238:238:238) (284:284:284)) - (PORT datac (356:356:356) (385:385:385)) - (PORT datad (1060:1060:1060) (1062:1062:1062)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (719:719:719) (787:787:787)) - (PORT datab (1609:1609:1609) (1627:1627:1627)) - (PORT datac (617:617:617) (649:649:649)) - (PORT datad (544:544:544) (562:562:562)) + (PORT dataa (1202:1202:1202) (1255:1255:1255)) + (PORT datab (805:805:805) (887:887:887)) + (PORT datac (798:798:798) (880:880:880)) + (PORT datad (889:889:889) (937:937:937)) (IOPATH dataa combout (341:341:341) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -28719,13 +4059,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~33) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) (DELAY (ABSOLUTE - (PORT datab (553:553:553) (575:575:575)) - (PORT datac (1318:1318:1318) (1317:1317:1317)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1253:1253:1253) (1284:1284:1284)) + (PORT datac (1036:1036:1036) (1054:1054:1054)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28733,92 +4075,88 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~35) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) (DELAY (ABSOLUTE - (PORT dataa (1048:1048:1048) (1070:1070:1070)) - (PORT datab (577:577:577) (591:591:591)) - (PORT datac (783:783:783) (785:785:785)) - (PORT datad (770:770:770) (770:770:770)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (872:872:872) (909:909:909)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (195:195:195) (229:229:229)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~15) (DELAY (ABSOLUTE - (PORT datad (815:815:815) (866:866:866)) + (PORT dataa (638:638:638) (656:656:656)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (353:353:353) (384:384:384)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mrd) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1588:1588:1588) (1565:1565:1565)) - (PORT ena (1172:1172:1172) (1151:1151:1151)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + (PORT datab (1558:1558:1558) (1645:1645:1645)) + (PORT datac (1678:1678:1678) (1754:1754:1754)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT asdata (1226:1226:1226) (1290:1290:1290)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~16) (DELAY (ABSOLUTE - (PORT dataa (909:909:909) (983:983:983)) - (PORT datad (215:215:215) (284:284:284)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (1366:1366:1366) (1468:1468:1468)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (1209:1209:1209) (1317:1317:1317)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1935:1935:1935) (2103:2103:2103)) + (PORT datac (1169:1169:1169) (1247:1247:1247)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~0) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (295:295:295)) + (PORT datab (1549:1549:1549) (1663:1663:1663)) + (PORT datac (1712:1712:1712) (1799:1799:1799)) + (PORT datad (1313:1313:1313) (1326:1326:1326)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -28828,10 +4166,10 @@ (INSTANCE z80_\|execute_\|nextM\~4) (DELAY (ABSOLUTE - (PORT dataa (233:233:233) (281:281:281)) - (PORT datab (702:702:702) (781:781:781)) - (PORT datac (856:856:856) (898:898:898)) - (PORT datad (1074:1074:1074) (1111:1111:1111)) + (PORT dataa (1524:1524:1524) (1519:1519:1519)) + (PORT datab (1191:1191:1191) (1249:1249:1249)) + (PORT datac (630:630:630) (682:682:682)) + (PORT datad (632:632:632) (687:687:687)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -28839,18 +4177,42 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT datac (1044:1044:1044) (1133:1133:1133)) + (PORT datad (1271:1271:1271) (1354:1354:1354)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2306:2306:2306) (2424:2424:2424)) + (PORT datac (1346:1346:1346) (1529:1529:1529)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_iorw\~12) (DELAY (ABSOLUTE - (PORT dataa (1890:1890:1890) (1960:1960:1960)) - (PORT datab (1472:1472:1472) (1522:1522:1522)) - (PORT datac (1489:1489:1489) (1536:1536:1536)) - (PORT datad (1919:1919:1919) (1985:1985:1985)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1886:1886:1886) (2000:2000:2000)) + (PORT datab (1612:1612:1612) (1752:1752:1752)) + (PORT datac (1469:1469:1469) (1530:1530:1530)) + (PORT datad (1053:1053:1053) (1100:1100:1100)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -28860,13 +4222,13 @@ (INSTANCE z80_\|execute_\|ctl_iorw\~8) (DELAY (ABSOLUTE - (PORT dataa (1104:1104:1104) (1152:1152:1152)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (201:201:201) (236:236:236)) - (PORT datad (679:679:679) (747:747:747)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (640:640:640) (658:658:658)) + (PORT datab (1360:1360:1360) (1377:1377:1377)) + (PORT datac (631:631:631) (639:639:639)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -28876,13 +4238,13 @@ (INSTANCE z80_\|execute_\|ctl_iorw\~9) (DELAY (ABSOLUTE - (PORT dataa (876:876:876) (891:891:891)) - (PORT datab (1170:1170:1170) (1227:1227:1227)) - (PORT datac (822:822:822) (840:840:840)) - (PORT datad (805:805:805) (814:814:814)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (1185:1185:1185) (1212:1212:1212)) + (PORT datab (661:661:661) (716:716:716)) + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (595:595:595) (628:628:628)) + (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -28892,10 +4254,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) + (PORT clk (1520:1520:1520) (1540:1540:1540)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) + (PORT clrn (1580:1580:1580) (1557:1557:1557)) + (PORT ena (1244:1244:1244) (1252:1252:1252)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -28905,43 +4267,15 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (220:220:220) (290:290:290)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorq) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT asdata (581:581:581) (655:655:655)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) + (PORT clk (1520:1520:1520) (1539:1539:1539)) + (PORT asdata (702:702:702) (770:770:770)) + (PORT clrn (1579:1579:1579) (1556:1556:1556)) + (PORT ena (1442:1442:1442) (1450:1450:1450)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -28951,15 +4285,43 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_iorq\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (655:655:655) (727:727:727)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorq) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1581:1581:1581) (1557:1557:1557)) + (PORT ena (1253:1253:1253) (1263:1263:1263)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) (DELAY (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT asdata (567:567:567) (645:645:645)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) + (PORT clk (1532:1532:1532) (1530:1530:1530)) + (PORT asdata (567:567:567) (643:643:643)) + (PORT clrn (1581:1581:1581) (1557:1557:1557)) + (PORT ena (1253:1253:1253) (1263:1263:1263)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -28974,8 +4336,8 @@ (INSTANCE z80_\|memory_ifc_\|iorq\~0) (DELAY (ABSOLUTE - (PORT datab (250:250:250) (335:335:335)) - (PORT datad (613:613:613) (663:663:663)) + (PORT datab (250:250:250) (333:333:333)) + (PORT datad (655:655:655) (722:722:722)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -28984,15 +4346,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~1) + (INSTANCE z80_\|pla_decode_\|Equal33\~2) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (941:941:941) (1024:1024:1024)) - (PORT datac (374:374:374) (401:401:401)) - (PORT datad (217:217:217) (243:243:243)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (1548:1548:1548) (1644:1644:1644)) + (PORT datac (1464:1464:1464) (1503:1503:1503)) + (PORT datad (1184:1184:1184) (1237:1237:1237)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29000,31 +4360,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~2) + (INSTANCE z80_\|execute_\|ixy_d\~17) (DELAY (ABSOLUTE - (PORT dataa (888:888:888) (913:913:913)) - (PORT datab (215:215:215) (260:260:260)) - (PORT datac (1187:1187:1187) (1208:1208:1208)) - (PORT datad (1091:1091:1091) (1137:1137:1137)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (229:229:229) (278:278:278)) + (PORT datab (221:221:221) (268:268:268)) + (PORT datac (996:996:996) (1082:1082:1082)) + (PORT datad (1499:1499:1499) (1549:1549:1549)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~0) + (INSTANCE z80_\|execute_\|ctl_mWrite\~15) (DELAY (ABSOLUTE - (PORT dataa (1889:1889:1889) (1932:1932:1932)) - (PORT datab (1525:1525:1525) (1597:1597:1597)) - (PORT datac (2202:2202:2202) (2248:2248:2248)) - (PORT datad (210:210:210) (242:242:242)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (1218:1218:1218) (1276:1276:1276)) + (PORT datab (1869:1869:1869) (1945:1945:1945)) + (PORT datac (1029:1029:1029) (1095:1095:1095)) + (PORT datad (1021:1021:1021) (1078:1078:1078)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29032,17 +4392,423 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~3) + (INSTANCE z80_\|execute_\|ctl_mWrite\~18) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (263:263:263)) - (PORT datab (336:336:336) (366:366:366)) - (PORT datac (586:586:586) (589:589:589)) - (PORT datad (351:351:351) (382:382:382)) + (PORT dataa (1764:1764:1764) (1856:1856:1856)) + (PORT datab (654:654:654) (690:690:690)) + (PORT datad (1598:1598:1598) (1743:1743:1743)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~12) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (958:958:958)) + (PORT datab (1244:1244:1244) (1298:1298:1298)) + (PORT datac (827:827:827) (870:870:870)) + (PORT datad (189:189:189) (219:219:219)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~21) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (1017:1017:1017)) + (PORT datab (993:993:993) (1040:1040:1040)) + (PORT datac (2018:2018:2018) (2124:2124:2124)) + (PORT datad (1484:1484:1484) (1600:1600:1600)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~20) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (687:687:687)) + (PORT datab (1506:1506:1506) (1597:1597:1597)) + (PORT datac (1719:1719:1719) (1859:1859:1859)) + (PORT datad (646:646:646) (663:663:663)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (658:658:658)) + (PORT datab (1777:1777:1777) (1839:1839:1839)) + (PORT datac (901:901:901) (951:951:951)) + (PORT datad (577:577:577) (582:582:582)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (640:640:640)) + (PORT datab (656:656:656) (693:693:693)) + (PORT datac (1397:1397:1397) (1513:1513:1513)) + (PORT datad (1771:1771:1771) (1867:1867:1867)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~10) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (674:674:674)) + (PORT datab (1187:1187:1187) (1225:1225:1225)) + (PORT datac (905:905:905) (945:945:945)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~13) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (647:647:647)) + (PORT datab (1785:1785:1785) (1851:1851:1851)) + (PORT datac (843:843:843) (884:884:884)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~9) + (DELAY + (ABSOLUTE + (PORT datab (2599:2599:2599) (2784:2784:2784)) + (PORT datac (2013:2013:2013) (2151:2151:2151)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1681:1681:1681) (1696:1696:1696)) + (PORT datab (1665:1665:1665) (1691:1691:1691)) + (PORT datac (1340:1340:1340) (1357:1357:1357)) + (PORT datad (1137:1137:1137) (1157:1157:1157)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) + (DELAY + (ABSOLUTE + (PORT dataa (934:934:934) (966:966:966)) + (PORT datab (1226:1226:1226) (1311:1311:1311)) + (PORT datac (667:667:667) (748:748:748)) + (PORT datad (672:672:672) (721:721:721)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) + (DELAY + (ABSOLUTE + (PORT dataa (689:689:689) (763:763:763)) + (PORT datab (205:205:205) (246:246:246)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1172:1172:1172) (1211:1211:1211)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1266:1266:1266) (1320:1320:1320)) + (PORT datab (1090:1090:1090) (1146:1146:1146)) + (PORT datac (1387:1387:1387) (1457:1457:1457)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1449:1449:1449) (1553:1553:1553)) + (PORT datab (1507:1507:1507) (1626:1626:1626)) + (PORT datac (1410:1410:1410) (1520:1520:1520)) + (PORT datad (1406:1406:1406) (1453:1453:1453)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~11) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (265:265:265)) + (PORT datab (640:640:640) (681:681:681)) + (PORT datac (1761:1761:1761) (1841:1841:1841)) + (PORT datad (650:650:650) (681:681:681)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~25) + (DELAY + (ABSOLUTE + (PORT datac (1195:1195:1195) (1279:1279:1279)) + (PORT datad (1192:1192:1192) (1245:1245:1245)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1453:1453:1453) (1558:1558:1558)) + (PORT datab (1151:1151:1151) (1192:1192:1192)) + (PORT datac (647:647:647) (693:693:693)) + (PORT datad (1478:1478:1478) (1588:1588:1588)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~24) + (DELAY + (ABSOLUTE + (PORT datac (1200:1200:1200) (1285:1285:1285)) + (PORT datad (1195:1195:1195) (1248:1248:1248)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (698:698:698)) + (PORT datab (247:247:247) (290:290:290)) + (PORT datac (913:913:913) (969:969:969)) + (PORT datad (845:845:845) (863:863:863)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~14) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (966:966:966)) + (PORT datab (897:897:897) (948:948:948)) + (PORT datac (882:882:882) (919:919:919)) + (PORT datad (593:593:593) (606:606:606)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1415:1415:1415) (1541:1541:1541)) + (PORT datad (1222:1222:1222) (1311:1311:1311)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~16) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (655:655:655)) + (PORT datab (821:821:821) (865:865:865)) + (PORT datac (1104:1104:1104) (1130:1130:1130)) + (PORT datad (2384:2384:2384) (2430:2430:2430)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1585:1585:1585) (1562:1562:1562)) + (PORT ena (1197:1197:1197) (1197:1197:1197)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (218:218:218) (288:288:288)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mwr) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1585:1585:1585) (1562:1562:1562)) + (PORT ena (1171:1171:1171) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|mwr_wr\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (882:882:882) (959:959:959)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|mwr_wr) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1581:1581:1581) (1557:1557:1557)) + (PORT ena (1253:1253:1253) (1263:1263:1263)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (275:275:275)) + (PORT datab (248:248:248) (331:331:331)) + (PORT datac (1026:1026:1026) (1073:1073:1073)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -29051,10 +4817,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff1) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1541:1541:1541)) + (PORT clk (1532:1532:1532) (1530:1530:1530)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1588:1588:1588) (1563:1563:1563)) - (PORT ena (1810:1810:1810) (1851:1851:1851)) + (PORT clrn (1581:1581:1581) (1557:1557:1557)) + (PORT ena (1253:1253:1253) (1263:1263:1263)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -29069,7 +4835,7 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1\~0) (DELAY (ABSOLUTE - (PORT datad (586:586:586) (642:642:642)) + (PORT datad (219:219:219) (287:287:287)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -29079,10 +4845,10 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1) (DELAY (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1530:1530:1530)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) + (PORT clrn (1581:1581:1581) (1557:1557:1557)) + (PORT ena (1253:1253:1253) (1263:1263:1263)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -29097,10 +4863,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff3) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) - (PORT asdata (568:568:568) (646:646:646)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) + (PORT clk (1521:1521:1521) (1541:1541:1541)) + (PORT asdata (566:566:566) (642:642:642)) + (PORT clrn (1581:1581:1581) (1557:1557:1557)) + (PORT ena (1280:1280:1280) (1296:1296:1296)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -29115,478 +4881,11 @@ (INSTANCE z80_\|memory_ifc_\|nRD_out\~0) (DELAY (ABSOLUTE - (PORT dataa (1456:1456:1456) (1520:1520:1520)) - (PORT datab (251:251:251) (336:336:336)) - (PORT datad (1485:1485:1485) (1574:1574:1574)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (376:376:376)) - (PORT datab (352:352:352) (391:391:391)) - (PORT datac (1027:1027:1027) (1030:1030:1030)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1747:1747:1747) (1852:1852:1852)) - (PORT datab (1597:1597:1597) (1730:1730:1730)) - (PORT datac (1200:1200:1200) (1265:1265:1265)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2395:2395:2395) (2551:2551:2551)) - (PORT datad (1014:1014:1014) (1128:1128:1128)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~5) - (DELAY - (ABSOLUTE - (PORT datab (1342:1342:1342) (1445:1445:1445)) - (PORT datac (2885:2885:2885) (3060:3060:3060)) - (PORT datad (2470:2470:2470) (2672:2672:2672)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (401:401:401)) - (PORT datab (883:883:883) (892:892:892)) - (PORT datac (957:957:957) (1029:1029:1029)) - (PORT datad (1073:1073:1073) (1058:1058:1058)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (1027:1027:1027)) - (PORT datac (1189:1189:1189) (1270:1270:1270)) - (PORT datad (2029:2029:2029) (2154:2154:2154)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1470:1470:1470) (1514:1514:1514)) - (PORT datab (897:897:897) (976:976:976)) - (PORT datac (362:362:362) (383:383:383)) - (PORT datad (193:193:193) (218:218:218)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (736:736:736)) - (PORT datab (837:837:837) (873:873:873)) - (PORT datac (876:876:876) (891:891:891)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1253:1253:1253) (1311:1311:1311)) - (PORT datab (870:870:870) (881:881:881)) - (PORT datac (1299:1299:1299) (1298:1298:1298)) - (PORT datad (625:625:625) (681:681:681)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (242:242:242)) - (PORT datab (1100:1100:1100) (1104:1104:1104)) - (PORT datac (369:369:369) (395:395:395)) - (PORT datad (1798:1798:1798) (1887:1887:1887)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~7) - (DELAY - (ABSOLUTE - (PORT datab (916:916:916) (964:964:964)) - (PORT datac (850:850:850) (896:896:896)) - (PORT datad (781:781:781) (791:791:791)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1515:1515:1515) (1583:1583:1583)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (1714:1714:1714) (1760:1760:1760)) - (PORT datad (881:881:881) (920:920:920)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1447:1447:1447) (1506:1506:1506)) - (PORT datab (1169:1169:1169) (1174:1174:1174)) - (PORT datac (894:894:894) (923:923:923)) - (PORT datad (781:781:781) (794:794:794)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1513:1513:1513) (1581:1581:1581)) - (PORT datab (1150:1150:1150) (1204:1204:1204)) - (PORT datac (1094:1094:1094) (1111:1111:1111)) - (PORT datad (616:616:616) (634:634:634)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1253:1253:1253) (1361:1361:1361)) - (PORT datab (869:869:869) (894:894:894)) - (PORT datac (1706:1706:1706) (1761:1761:1761)) - (PORT datad (263:263:263) (315:315:315)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1146:1146:1146) (1188:1188:1188)) - (PORT datab (214:214:214) (258:258:258)) - (PORT datac (192:192:192) (225:225:225)) - (PORT datad (621:621:621) (651:651:651)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (1051:1051:1051) (1068:1068:1068)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1101:1101:1101) (1104:1104:1104)) - (PORT datab (879:879:879) (888:888:888)) - (PORT datac (609:609:609) (624:624:624)) - (PORT datad (1198:1198:1198) (1221:1221:1221)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (927:927:927)) - (PORT datab (206:206:206) (246:246:246)) - (PORT datac (583:583:583) (601:601:601)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (332:332:332) (351:351:351)) - (PORT datad (813:813:813) (840:840:840)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~10) - (DELAY - (ABSOLUTE - (PORT dataa (881:881:881) (906:906:906)) - (PORT datab (1043:1043:1043) (1098:1098:1098)) - (PORT datac (1093:1093:1093) (1111:1111:1111)) - (PORT datad (1130:1130:1130) (1132:1132:1132)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (247:247:247)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (572:572:572) (605:605:605)) - (PORT datab (1113:1113:1113) (1136:1136:1136)) - (PORT datac (1714:1714:1714) (1760:1760:1760)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (1120:1120:1120) (1187:1187:1187)) + (PORT datab (249:249:249) (332:332:332)) + (PORT datad (1382:1382:1382) (1442:1442:1442)) (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (726:726:726)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (612:612:612) (639:639:639)) - (PORT datad (196:196:196) (220:220:220)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (930:930:930) (979:979:979)) - (PORT datac (1054:1054:1054) (1167:1167:1167)) - (PORT datad (1137:1137:1137) (1183:1183:1183)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|DFF_inst5\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (225:225:225) (296:296:296)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|DFF_inst5) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1587:1587:1587) (1563:1563:1563)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_iorqinta\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (228:228:228) (301:301:301)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1587:1587:1587) (1563:1563:1563)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1547:1547:1547)) - (PORT asdata (568:568:568) (647:647:647)) - (PORT clrn (1587:1587:1587) (1563:1563:1563)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (342:342:342)) - (PORT datad (605:605:605) (631:631:631)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29594,13 +4893,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal2\~0) + (INSTANCE z80_\|execute_\|ctl_mRead\~2) (DELAY (ABSOLUTE - (PORT dataa (1750:1750:1750) (1853:1853:1853)) - (PORT datab (1593:1593:1593) (1734:1734:1734)) - (PORT datac (1199:1199:1199) (1264:1264:1264)) - (PORT datad (1222:1222:1222) (1307:1307:1307)) + (PORT dataa (993:993:993) (1073:1073:1073)) + (PORT datab (236:236:236) (281:281:281)) + (PORT datac (1079:1079:1079) (1095:1095:1095)) + (PORT datad (1469:1469:1469) (1538:1538:1538)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -29610,13 +4909,289 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ExtRamWE\~0) + (INSTANCE z80_\|execute_\|fIORead\~0) (DELAY (ABSOLUTE - (PORT dataa (1747:1747:1747) (1852:1852:1852)) - (PORT datab (1597:1597:1597) (1730:1730:1730)) - (PORT datac (1200:1200:1200) (1265:1265:1265)) - (PORT datad (1220:1220:1220) (1307:1307:1307)) + (PORT dataa (1309:1309:1309) (1371:1371:1371)) + (PORT datab (927:927:927) (1024:1024:1024)) + (PORT datac (1164:1164:1164) (1225:1225:1225)) + (PORT datad (1430:1430:1430) (1462:1462:1462)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1747:1747:1747) (1845:1845:1845)) + (PORT datab (1652:1652:1652) (1803:1803:1803)) + (PORT datac (1044:1044:1044) (1103:1103:1103)) + (PORT datad (1815:1815:1815) (1893:1893:1893)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~4) + (DELAY + (ABSOLUTE + (PORT datab (1607:1607:1607) (1746:1746:1746)) + (PORT datad (1856:1856:1856) (1958:1958:1958)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) + (DELAY + (ABSOLUTE + (PORT dataa (259:259:259) (311:311:311)) + (PORT datab (1677:1677:1677) (1826:1826:1826)) + (PORT datac (1288:1288:1288) (1378:1378:1378)) + (PORT datad (2871:2871:2871) (2927:2927:2927)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~1) + (DELAY + (ABSOLUTE + (PORT dataa (259:259:259) (312:312:312)) + (PORT datab (927:927:927) (1024:1024:1024)) + (PORT datac (1164:1164:1164) (1225:1225:1225)) + (PORT datad (1753:1753:1753) (1784:1784:1784)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1132:1132:1132) (1179:1179:1179)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (1409:1409:1409) (1398:1398:1398)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1622:1622:1622) (1658:1658:1658)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) + (DELAY + (ABSOLUTE + (PORT dataa (448:448:448) (509:509:509)) + (PORT datad (602:602:602) (624:624:624)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_im_we) + (DELAY + (ABSOLUTE + (PORT dataa (1454:1454:1454) (1538:1538:1538)) + (PORT datab (1435:1435:1435) (1471:1471:1471)) + (PORT datac (1347:1347:1347) (1529:1529:1529)) + (PORT datad (2534:2534:2534) (2622:2622:2622)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im2) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (980:980:980) (1001:1001:1001)) + (PORT clrn (1577:1577:1577) (1557:1557:1557)) + (PORT ena (968:968:968) (972:972:972)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (447:447:447)) + (PORT datab (862:862:862) (915:915:915)) + (PORT datad (269:269:269) (350:350:350)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1545:1545:1545) (1642:1642:1642)) + (PORT datab (265:265:265) (310:310:310)) + (PORT datac (1461:1461:1461) (1499:1499:1499)) + (PORT datad (1184:1184:1184) (1243:1243:1243)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1684:1684:1684) (1788:1788:1788)) + (PORT datab (243:243:243) (287:287:287)) + (PORT datac (1764:1764:1764) (1827:1827:1827)) + (PORT datad (810:810:810) (866:866:866)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (451:451:451) (489:489:489)) + (PORT datab (1270:1270:1270) (1351:1351:1351)) + (PORT datac (1326:1326:1326) (1377:1377:1377)) + (PORT datad (651:651:651) (674:674:674)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~31) + (DELAY + (ABSOLUTE + (PORT datab (654:654:654) (678:678:678)) + (PORT datac (852:852:852) (873:873:873)) + (PORT datad (866:866:866) (881:881:881)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (474:474:474) (510:510:510)) + (PORT datab (1700:1700:1700) (1774:1774:1774)) + (PORT datac (1844:1844:1844) (1971:1971:1971)) + (PORT datad (788:788:788) (851:851:851)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) + (DELAY + (ABSOLUTE + (PORT datab (1461:1461:1461) (1510:1510:1510)) + (PORT datac (1183:1183:1183) (1237:1237:1237)) + (PORT datad (1434:1434:1434) (1514:1514:1514)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal44\~0) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (855:855:855)) + (PORT datab (768:768:768) (840:840:840)) + (PORT datac (1827:1827:1827) (1972:1972:1972)) + (PORT datad (1687:1687:1687) (1760:1760:1760)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~6) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (928:928:928)) + (PORT datab (1029:1029:1029) (1113:1113:1113)) + (PORT datac (1460:1460:1460) (1500:1500:1500)) + (PORT datad (1502:1502:1502) (1555:1555:1555)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -29626,12 +5201,25858 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) + (INSTANCE z80_\|execute_\|fMRead\~5) (DELAY (ABSOLUTE - (PORT dataa (1796:1796:1796) (1810:1810:1810)) - (PORT datab (849:849:849) (873:873:873)) - (PORT datad (335:335:335) (353:353:353)) + (PORT dataa (916:916:916) (960:960:960)) + (PORT datab (880:880:880) (969:969:969)) + (PORT datac (1051:1051:1051) (1088:1088:1088)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~17) + (DELAY + (ABSOLUTE + (PORT datab (631:631:631) (694:694:694)) + (PORT datac (802:802:802) (833:833:833)) + (PORT datad (852:852:852) (894:894:894)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1545:1545:1545) (1645:1645:1645)) + (PORT datac (1461:1461:1461) (1503:1503:1503)) + (PORT datad (1184:1184:1184) (1243:1243:1243)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal49\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1495:1495:1495) (1540:1540:1540)) + (PORT datab (958:958:958) (1015:1015:1015)) + (PORT datac (1200:1200:1200) (1255:1255:1255)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1231:1231:1231) (1240:1240:1240)) + (PORT datab (660:660:660) (687:687:687)) + (PORT datac (1667:1667:1667) (1700:1700:1700)) + (PORT datad (907:907:907) (984:984:984)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1812:1812:1812) (1880:1880:1880)) + (PORT datab (1075:1075:1075) (1143:1143:1143)) + (PORT datac (1721:1721:1721) (1798:1798:1798)) + (PORT datad (218:218:218) (257:257:257)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal25\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2132:2132:2132) (2307:2307:2307)) + (PORT datab (2626:2626:2626) (2718:2718:2718)) + (PORT datac (1370:1370:1370) (1475:1475:1475)) + (PORT datad (874:874:874) (899:899:899)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2265:2265:2265) (2343:2343:2343)) + (PORT datab (228:228:228) (270:270:270)) + (PORT datac (623:623:623) (663:663:663)) + (PORT datad (1014:1014:1014) (1053:1053:1053)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) + (DELAY + (ABSOLUTE + (PORT datab (1599:1599:1599) (1667:1667:1667)) + (PORT datac (1208:1208:1208) (1265:1265:1265)) + (PORT datad (1110:1110:1110) (1156:1156:1156)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1318:1318:1318) (1375:1375:1375)) + (PORT datab (970:970:970) (996:996:996)) + (PORT datac (1388:1388:1388) (1527:1527:1527)) + (PORT datad (1184:1184:1184) (1246:1246:1246)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~16) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (928:928:928)) + (PORT datab (1028:1028:1028) (1113:1113:1113)) + (PORT datac (1466:1466:1466) (1505:1505:1505)) + (PORT datad (1497:1497:1497) (1547:1547:1547)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (829:829:829) (834:834:834)) + (PORT datab (606:606:606) (630:630:630)) + (PORT datac (1624:1624:1624) (1671:1671:1671)) + (PORT datad (1597:1597:1597) (1618:1618:1618)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (703:703:703)) + (PORT datac (1119:1119:1119) (1126:1126:1126)) + (PORT datad (794:794:794) (865:865:865)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal29\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2137:2137:2137) (2307:2307:2307)) + (PORT datab (686:686:686) (711:711:711)) + (PORT datac (1044:1044:1044) (1121:1121:1121)) + (PORT datad (863:863:863) (904:904:904)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~38) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (407:407:407)) + (PORT datab (389:389:389) (421:421:421)) + (PORT datac (657:657:657) (706:706:706)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal35\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1421:1421:1421) (1449:1449:1449)) + (PORT datab (1932:1932:1932) (2005:2005:2005)) + (PORT datac (896:896:896) (938:938:938)) + (PORT datad (226:226:226) (261:261:261)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~33) + (DELAY + (ABSOLUTE + (PORT dataa (3083:3083:3083) (3178:3178:3178)) + (PORT datab (849:849:849) (890:890:890)) + (PORT datac (1445:1445:1445) (1544:1544:1544)) + (PORT datad (1991:1991:1991) (2046:2046:2046)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~1) + (DELAY + (ABSOLUTE + (PORT datab (1812:1812:1812) (1916:1916:1916)) + (PORT datad (2317:2317:2317) (2381:2381:2381)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (910:910:910)) + (PORT datab (393:393:393) (426:426:426)) + (PORT datac (1765:1765:1765) (1827:1827:1827)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1189:1189:1189) (1249:1249:1249)) + (PORT datab (1776:1776:1776) (1843:1843:1843)) + (PORT datac (593:593:593) (619:619:619)) + (PORT datad (613:613:613) (635:635:635)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (894:894:894) (917:917:917)) + (PORT datac (935:935:935) (977:977:977)) + (PORT datad (586:586:586) (595:595:595)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1910:1910:1910) (1994:1994:1994)) + (PORT datab (1648:1648:1648) (1797:1797:1797)) + (PORT datac (611:611:611) (649:649:649)) + (PORT datad (1744:1744:1744) (1826:1826:1826)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~36) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (901:901:901)) + (PORT datab (349:349:349) (382:382:382)) + (PORT datac (2016:2016:2016) (2128:2128:2128)) + (PORT datad (1098:1098:1098) (1111:1111:1111)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~14) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (275:275:275)) + (PORT datab (264:264:264) (310:310:310)) + (PORT datac (339:339:339) (366:366:366)) + (PORT datad (194:194:194) (230:230:230)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1164:1164:1164) (1218:1218:1218)) + (PORT datab (662:662:662) (682:682:682)) + (PORT datac (928:928:928) (996:996:996)) + (PORT datad (1139:1139:1139) (1210:1210:1210)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1684:1684:1684) (1791:1791:1791)) + (PORT datab (1366:1366:1366) (1397:1397:1397)) + (PORT datac (1763:1763:1763) (1830:1830:1830)) + (PORT datad (219:219:219) (255:255:255)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~39) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (624:624:624) (657:657:657)) + (PORT datad (827:827:827) (857:857:857)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1250:1250:1250)) + (PORT datab (366:366:366) (399:399:399)) + (PORT datac (1834:1834:1834) (1907:1907:1907)) + (PORT datad (603:603:603) (616:616:616)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2560:2560:2560) (2631:2631:2631)) + (PORT datab (2467:2467:2467) (2664:2664:2664)) + (PORT datad (1837:1837:1837) (1931:1931:1931)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1916:1916:1916) (2018:2018:2018)) + (PORT datab (894:894:894) (927:927:927)) + (PORT datac (1604:1604:1604) (1723:1723:1723)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1703:1703:1703) (1792:1792:1792)) + (PORT datab (1079:1079:1079) (1158:1158:1158)) + (PORT datac (897:897:897) (935:935:935)) + (PORT datad (225:225:225) (260:260:260)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (978:978:978)) + (PORT datab (1423:1423:1423) (1444:1444:1444)) + (PORT datac (618:618:618) (657:657:657)) + (PORT datad (823:823:823) (839:839:839)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1910:1910:1910) (1993:1993:1993)) + (PORT datab (1647:1647:1647) (1796:1796:1796)) + (PORT datac (610:610:610) (648:648:648)) + (PORT datad (1744:1744:1744) (1826:1826:1826)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (2257:2257:2257) (2334:2334:2334)) + (PORT datab (879:879:879) (911:911:911)) + (PORT datac (1573:1573:1573) (1705:1705:1705)) + (PORT datad (1688:1688:1688) (1747:1747:1747)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (940:940:940)) + (PORT datab (1609:1609:1609) (1651:1651:1651)) + (PORT datac (1191:1191:1191) (1251:1251:1251)) + (PORT datad (1658:1658:1658) (1714:1714:1714)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (728:728:728) (796:796:796)) + (PORT datab (1599:1599:1599) (1668:1668:1668)) + (PORT datac (1208:1208:1208) (1265:1265:1265)) + (PORT datad (1111:1111:1111) (1156:1156:1156)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2134:2134:2134) (2303:2303:2303)) + (PORT datab (1470:1470:1470) (1496:1496:1496)) + (PORT datac (1118:1118:1118) (1150:1150:1150)) + (PORT datad (645:645:645) (670:670:670)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~0) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (988:988:988)) + (PORT datab (557:557:557) (587:587:587)) + (PORT datac (569:569:569) (575:575:575)) + (PORT datad (573:573:573) (586:586:586)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~1) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (171:171:171) (202:202:202)) + (PORT datad (221:221:221) (250:250:250)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (956:956:956)) + (PORT datab (691:691:691) (757:757:757)) + (PORT datac (1338:1338:1338) (1342:1342:1342)) + (PORT datad (1183:1183:1183) (1212:1212:1212)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (954:954:954)) + (PORT datab (1459:1459:1459) (1512:1512:1512)) + (PORT datac (877:877:877) (900:900:900)) + (PORT datad (215:215:215) (248:248:248)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (919:919:919)) + (PORT datab (689:689:689) (761:761:761)) + (PORT datac (320:320:320) (344:344:344)) + (PORT datad (842:842:842) (871:871:871)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (686:686:686)) + (PORT datab (895:895:895) (931:931:931)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (882:882:882) (910:910:910)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~1) + (DELAY + (ABSOLUTE + (PORT dataa (474:474:474) (506:506:506)) + (PORT datab (1099:1099:1099) (1115:1115:1115)) + (PORT datac (742:742:742) (814:814:814)) + (PORT datad (730:730:730) (803:803:803)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (659:659:659)) + (PORT datab (660:660:660) (693:693:693)) + (PORT datac (576:576:576) (604:604:604)) + (PORT datad (663:663:663) (683:683:683)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (891:891:891)) + (PORT datab (616:616:616) (645:645:645)) + (PORT datac (1506:1506:1506) (1571:1571:1571)) + (PORT datad (192:192:192) (225:225:225)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (899:899:899) (928:928:928)) + (PORT datac (570:570:570) (592:592:592)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~3) + (DELAY + (ABSOLUTE + (PORT dataa (623:623:623) (660:660:660)) + (PORT datab (1247:1247:1247) (1277:1277:1277)) + (PORT datad (874:874:874) (919:919:919)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1203:1203:1203) (1236:1236:1236)) + (PORT datab (638:638:638) (670:670:670)) + (PORT datac (200:200:200) (236:236:236)) + (PORT datad (2384:2384:2384) (2430:2430:2430)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (835:835:835)) + (PORT datab (590:590:590) (599:599:599)) + (PORT datac (836:836:836) (870:870:870)) + (PORT datad (988:988:988) (1049:1049:1049)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1581:1581:1581) (1557:1557:1557)) + (PORT ena (1280:1280:1280) (1296:1296:1296)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (218:218:218) (287:287:287)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mrd) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1581:1581:1581) (1557:1557:1557)) + (PORT ena (1253:1253:1253) (1263:1263:1263)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (235:235:235) (312:312:312)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1581:1581:1581) (1557:1557:1557)) + (PORT ena (1253:1253:1253) (1263:1263:1263)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (249:249:249) (340:340:340)) + (PORT datad (234:234:234) (311:311:311)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (824:824:824) (842:842:842)) + (PORT datac (202:202:202) (240:240:240)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~1) + (DELAY + (ABSOLUTE + (PORT datab (1866:1866:1866) (2020:2020:2020)) + (PORT datac (3074:3074:3074) (3300:3300:3300)) + (PORT datad (2568:2568:2568) (2680:2680:2680)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_DAT\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (843:843:843) (859:859:859)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (373:373:373)) + (PORT datab (291:291:291) (383:383:383)) + (PORT datad (249:249:249) (334:334:334)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_CLK\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3310:3310:3310) (3637:3637:3637)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (228:228:228) (301:301:301)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (225:225:225) (298:298:298)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (227:227:227) (302:302:302)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (240:240:240) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (344:344:344)) + (PORT datab (250:250:250) (336:336:336)) + (PORT datac (375:375:375) (441:441:441)) + (PORT datad (226:226:226) (299:299:299)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (226:226:226) (298:298:298)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (228:228:228) (301:301:301)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (344:344:344)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (224:224:224) (304:304:304)) + (PORT datad (228:228:228) (301:301:301)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (225:225:225) (304:304:304)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) + (DELAY + (ABSOLUTE + (PORT dataa (256:256:256) (346:346:346)) + (PORT datad (183:183:183) (212:212:212)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) + (DELAY + (ABSOLUTE + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (225:225:225) (308:308:308)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1548:1548:1548) (1540:1540:1540)) + (PORT ena (2142:2142:2142) (2242:2242:2242)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (368:368:368)) + (PORT datab (277:277:277) (367:367:367)) + (PORT datad (249:249:249) (333:333:333)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1548:1548:1548) (1540:1540:1540)) + (PORT ena (2142:2142:2142) (2242:2242:2242)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (374:374:374)) + (PORT datab (293:293:293) (386:386:386)) + (PORT datad (250:250:250) (330:330:330)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1548:1548:1548) (1540:1540:1540)) + (PORT ena (2142:2142:2142) (2242:2242:2242)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (377:377:377)) + (PORT datab (289:289:289) (381:381:381)) + (PORT datad (247:247:247) (326:326:326)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1548:1548:1548) (1540:1540:1540)) + (PORT ena (2142:2142:2142) (2242:2242:2242)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (275:275:275) (373:373:373)) + (PORT datab (292:292:292) (384:384:384)) + (PORT datad (250:250:250) (329:329:329)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (373:373:373)) + (PORT datab (276:276:276) (369:369:369)) + (PORT datac (384:384:384) (445:445:445)) + (PORT datad (3313:3313:3313) (3645:3645:3645)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (368:368:368)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (1497:1497:1497) (1608:1608:1608)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT asdata (3641:3641:3641) (3987:3987:3987)) + (PORT clrn (1545:1545:1545) (1538:1538:1538)) + (PORT ena (1641:1641:1641) (1638:1638:1638)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT asdata (703:703:703) (765:765:765)) + (PORT clrn (1545:1545:1545) (1538:1538:1538)) + (PORT ena (1641:1641:1641) (1638:1638:1638)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT asdata (613:613:613) (718:718:718)) + (PORT clrn (1545:1545:1545) (1538:1538:1538)) + (PORT ena (1641:1641:1641) (1638:1638:1638)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT asdata (1312:1312:1312) (1370:1370:1370)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) + (PORT ena (1685:1685:1685) (1687:1687:1687)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT asdata (1237:1237:1237) (1318:1318:1318)) + (PORT clrn (1545:1545:1545) (1538:1538:1538)) + (PORT ena (1641:1641:1641) (1638:1638:1638)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT asdata (1368:1368:1368) (1443:1443:1443)) + (PORT clrn (1542:1542:1542) (1535:1535:1535)) + (PORT ena (1425:1425:1425) (1453:1453:1453)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT asdata (1184:1184:1184) (1233:1233:1233)) + (PORT clrn (1542:1542:1542) (1535:1535:1535)) + (PORT ena (1425:1425:1425) (1453:1453:1453)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT asdata (608:608:608) (699:699:699)) + (PORT clrn (1542:1542:1542) (1535:1535:1535)) + (PORT ena (1425:1425:1425) (1453:1453:1453)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT asdata (1274:1274:1274) (1331:1331:1331)) + (PORT clrn (1545:1545:1545) (1538:1538:1538)) + (PORT ena (1641:1641:1641) (1638:1638:1638)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (416:416:416)) + (PORT datab (930:930:930) (1010:1010:1010)) + (PORT datac (251:251:251) (336:336:336)) + (PORT datad (944:944:944) (1019:1019:1019)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (780:780:780) (879:879:879)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (927:927:927) (986:986:986)) + (PORT datad (264:264:264) (344:344:344)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (301:301:301) (422:422:422)) + (PORT datab (985:985:985) (1056:1056:1056)) + (PORT datad (264:264:264) (344:344:344)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (916:916:916) (985:985:985)) + (PORT datab (960:960:960) (1023:1023:1023)) + (PORT datad (755:755:755) (838:838:838)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) + (DELAY + (ABSOLUTE + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (236:236:236) (312:312:312)) + (PORT datad (311:311:311) (327:327:327)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) + (DELAY + (ABSOLUTE + (PORT dataa (672:672:672) (692:692:692)) + (PORT datab (3347:3347:3347) (3682:3682:3682)) + (PORT datac (1498:1498:1498) (1609:1609:1609)) + (PORT datad (185:185:185) (215:215:215)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1548:1548:1548) (1540:1540:1540)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|released\~0) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (714:714:714)) + (PORT datab (877:877:877) (947:947:947)) + (PORT datad (704:704:704) (775:775:775)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|released) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (795:795:795)) + (PORT datab (791:791:791) (877:877:877)) + (PORT datac (707:707:707) (797:797:797)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (729:729:729) (814:814:814)) + (PORT datad (750:750:750) (828:828:828)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|extended\~0) + (DELAY + (ABSOLUTE + (PORT dataa (698:698:698) (717:717:717)) + (PORT datad (699:699:699) (766:766:766)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|extended) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (PORT ena (1489:1489:1489) (1540:1540:1540)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (291:291:291) (409:409:409)) + (PORT datab (677:677:677) (741:741:741)) + (PORT datac (912:912:912) (970:970:970)) + (PORT datad (268:268:268) (348:348:348)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (690:690:690)) + (PORT datab (762:762:762) (850:850:850)) + (PORT datac (182:182:182) (219:219:219)) + (PORT datad (1129:1129:1129) (1155:1155:1155)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (436:436:436)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|clrpc_int\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1901:1901:1901) (2085:2085:2085)) + (PORT datab (1495:1495:1495) (1563:1563:1563)) + (PORT datad (1153:1153:1153) (1262:1262:1262)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|clrpc_int) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1931:1931:1931) (1907:1907:1907)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT datac (949:949:949) (997:997:997)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (225:225:225) (298:298:298)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1530:1530:1530)) + (PORT asdata (568:568:568) (646:646:646)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|clrpc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (728:728:728)) + (PORT datab (252:252:252) (337:337:337)) + (PORT datad (226:226:226) (299:299:299)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1278:1278:1278) (1382:1382:1382)) + (PORT datab (977:977:977) (1078:1078:1078)) + (PORT datac (624:624:624) (676:676:676)) + (PORT datad (886:886:886) (918:918:918)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1916:1916:1916) (2016:2016:2016)) + (PORT datab (1192:1192:1192) (1204:1204:1204)) + (PORT datac (1608:1608:1608) (1722:1722:1722)) + (PORT datad (856:856:856) (886:886:886)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1916:1916:1916) (2016:2016:2016)) + (PORT datab (893:893:893) (925:925:925)) + (PORT datac (1608:1608:1608) (1721:1721:1721)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1915:1915:1915) (2019:2019:2019)) + (PORT datab (1746:1746:1746) (1780:1780:1780)) + (PORT datac (1605:1605:1605) (1722:1722:1722)) + (PORT datad (856:856:856) (890:890:890)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (300:300:300)) + (PORT datac (256:256:256) (311:311:311)) + (PORT datad (245:245:245) (296:296:296)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (667:667:667)) + (PORT datac (1675:1675:1675) (1746:1746:1746)) + (PORT datad (1137:1137:1137) (1176:1176:1176)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (683:683:683)) + (PORT datac (621:621:621) (640:640:640)) + (PORT datad (1221:1221:1221) (1279:1279:1279)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (700:700:700)) + (PORT datab (1445:1445:1445) (1504:1504:1504)) + (PORT datac (586:586:586) (606:606:606)) + (PORT datad (1117:1117:1117) (1138:1138:1138)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (686:686:686)) + (PORT datab (939:939:939) (980:980:980)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (887:887:887) (909:909:909)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) + (DELAY + (ABSOLUTE + (PORT datab (1493:1493:1493) (1554:1554:1554)) + (PORT datac (1223:1223:1223) (1253:1253:1253)) + (PORT datad (1403:1403:1403) (1470:1470:1470)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1350:1350:1350) (1394:1394:1394)) + (PORT datab (1605:1605:1605) (1734:1734:1734)) + (PORT datac (622:622:622) (664:664:664)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1978:1978:1978) (2137:2137:2137)) + (PORT datab (2591:2591:2591) (2768:2768:2768)) + (PORT datad (1697:1697:1697) (1792:1792:1792)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1450:1450:1450) (1523:1523:1523)) + (PORT datab (976:976:976) (983:983:983)) + (PORT datac (868:868:868) (907:907:907)) + (PORT datad (918:918:918) (955:955:955)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) + (DELAY + (ABSOLUTE + (PORT dataa (2356:2356:2356) (2462:2462:2462)) + (PORT datac (1864:1864:1864) (1892:1892:1892)) + (PORT datad (1772:1772:1772) (1886:1886:1886)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (966:966:966) (1020:1020:1020)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1187:1187:1187) (1271:1271:1271)) + (PORT datab (627:627:627) (649:649:649)) + (PORT datac (902:902:902) (931:931:931)) + (PORT datad (859:859:859) (879:879:879)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (891:891:891) (925:925:925)) + (PORT datac (619:619:619) (660:660:660)) + (PORT datad (620:620:620) (668:668:668)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (907:907:907)) + (PORT datab (1517:1517:1517) (1628:1628:1628)) + (PORT datac (622:622:622) (674:674:674)) + (PORT datad (1219:1219:1219) (1277:1277:1277)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (185:185:185) (224:224:224)) + (PORT datad (1252:1252:1252) (1309:1309:1309)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~13) + (DELAY + (ABSOLUTE + (PORT datab (2733:2733:2733) (2908:2908:2908)) + (PORT datac (1737:1737:1737) (1813:1813:1813)) + (PORT datad (839:839:839) (867:867:867)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1578:1578:1578) (1687:1687:1687)) + (PORT datab (2007:2007:2007) (2122:2122:2122)) + (PORT datac (2198:2198:2198) (2304:2304:2304)) + (PORT datad (1762:1762:1762) (1853:1853:1853)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1771:1771:1771) (1876:1876:1876)) + (PORT datab (356:356:356) (392:392:392)) + (PORT datac (1865:1865:1865) (1919:1919:1919)) + (PORT datad (1599:1599:1599) (1746:1746:1746)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~16) + (DELAY + (ABSOLUTE + (PORT dataa (2343:2343:2343) (2509:2509:2509)) + (PORT datab (1128:1128:1128) (1167:1167:1167)) + (PORT datac (1549:1549:1549) (1649:1649:1649)) + (PORT datad (1983:1983:1983) (2085:2085:2085)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (931:931:931)) + (PORT datab (822:822:822) (869:869:869)) + (PORT datac (169:169:169) (202:202:202)) + (PORT datad (1639:1639:1639) (1711:1711:1711)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (287:287:287)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (650:650:650) (707:707:707)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1143:1143:1143) (1214:1214:1214)) + (PORT datab (849:849:849) (876:876:876)) + (PORT datac (1180:1180:1180) (1245:1245:1245)) + (PORT datad (894:894:894) (941:941:941)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1536:1536:1536) (1600:1600:1600)) + (PORT datab (1096:1096:1096) (1128:1128:1128)) + (PORT datac (1717:1717:1717) (1793:1793:1793)) + (PORT datad (1165:1165:1165) (1203:1203:1203)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1531:1531:1531) (1599:1599:1599)) + (PORT datab (216:216:216) (261:261:261)) + (PORT datac (1264:1264:1264) (1333:1333:1333)) + (PORT datad (1159:1159:1159) (1219:1219:1219)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~2) + (DELAY + (ABSOLUTE + (PORT dataa (277:277:277) (348:348:348)) + (PORT datab (250:250:250) (300:300:300)) + (PORT datac (248:248:248) (306:306:306)) + (PORT datad (1436:1436:1436) (1458:1458:1458)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (632:632:632)) + (PORT datab (853:853:853) (859:859:859)) + (PORT datac (371:371:371) (388:388:388)) + (PORT datad (899:899:899) (949:949:949)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (615:615:615)) + (PORT datab (226:226:226) (267:267:267)) + (PORT datac (1119:1119:1119) (1151:1151:1151)) + (PORT datad (880:880:880) (918:918:918)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1108:1108:1108) (1164:1164:1164)) + (PORT datab (229:229:229) (271:271:271)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal56\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1086:1086:1086) (1166:1166:1166)) + (PORT datab (2009:2009:2009) (2098:2098:2098)) + (PORT datac (1374:1374:1374) (1482:1482:1482)) + (PORT datad (1892:1892:1892) (1950:1950:1950)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1682:1682:1682) (1789:1789:1789)) + (PORT datab (654:654:654) (672:672:672)) + (PORT datac (1764:1764:1764) (1827:1827:1827)) + (PORT datad (1054:1054:1054) (1101:1101:1101)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1684:1684:1684) (1793:1793:1793)) + (PORT datab (653:653:653) (674:674:674)) + (PORT datac (1763:1763:1763) (1832:1832:1832)) + (PORT datad (1052:1052:1052) (1102:1102:1102)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1222:1222:1222) (1238:1238:1238)) + (PORT datab (886:886:886) (929:929:929)) + (PORT datac (942:942:942) (998:998:998)) + (PORT datad (944:944:944) (995:995:995)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (436:436:436)) + (PORT datab (948:948:948) (982:982:982)) + (PORT datac (584:584:584) (628:628:628)) + (PORT datad (223:223:223) (253:253:253)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (962:962:962)) + (PORT datab (942:942:942) (963:963:963)) + (PORT datac (638:638:638) (669:669:669)) + (PORT datad (1172:1172:1172) (1244:1244:1244)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (1052:1052:1052)) + (PORT datab (987:987:987) (1030:1030:1030)) + (PORT datac (1171:1171:1171) (1219:1219:1219)) + (PORT datad (986:986:986) (1036:1036:1036)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (673:673:673)) + (PORT datab (1462:1462:1462) (1514:1514:1514)) + (PORT datac (830:830:830) (908:908:908)) + (PORT datad (1914:1914:1914) (1984:1984:1984)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|nM1_int\~2) + (DELAY + (ABSOLUTE + (PORT datac (1322:1322:1322) (1471:1471:1471)) + (PORT datad (2189:2189:2189) (2361:2361:2361)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (881:881:881)) + (PORT datab (217:217:217) (263:263:263)) + (PORT datac (1159:1159:1159) (1177:1177:1177)) + (PORT datad (639:639:639) (677:677:677)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~94) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (999:999:999)) + (PORT datab (1472:1472:1472) (1516:1516:1516)) + (PORT datac (1410:1410:1410) (1502:1502:1502)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (645:645:645)) + (PORT datab (228:228:228) (270:270:270)) + (PORT datac (826:826:826) (838:838:838)) + (PORT datad (789:789:789) (845:845:845)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) + (DELAY + (ABSOLUTE + (PORT dataa (2006:2006:2006) (2078:2078:2078)) + (PORT datab (611:611:611) (626:626:626)) + (PORT datac (831:831:831) (870:870:870)) + (PORT datad (705:705:705) (742:742:742)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1665:1665:1665) (1731:1731:1731)) + (PORT datab (1778:1778:1778) (1843:1843:1843)) + (PORT datac (897:897:897) (948:948:948)) + (PORT datad (703:703:703) (737:737:737)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (936:936:936)) + (PORT datab (1991:1991:1991) (2053:2053:2053)) + (PORT datac (1786:1786:1786) (1813:1813:1813)) + (PORT datad (1444:1444:1444) (1438:1438:1438)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (644:644:644)) + (PORT datab (740:740:740) (777:777:777)) + (PORT datac (1151:1151:1151) (1208:1208:1208)) + (PORT datad (804:804:804) (817:817:817)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (658:658:658)) + (PORT datab (742:742:742) (780:780:780)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (607:607:607) (632:632:632)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (376:376:376)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1656:1656:1656) (1674:1674:1674)) + (PORT datab (832:832:832) (856:856:856)) + (PORT datac (874:874:874) (900:900:900)) + (PORT datad (583:583:583) (602:602:602)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1662:1662:1662) (1727:1727:1727)) + (PORT datab (609:609:609) (623:623:623)) + (PORT datac (171:171:171) (202:202:202)) + (PORT datad (1964:1964:1964) (2030:2030:2030)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (874:874:874)) + (PORT datab (1111:1111:1111) (1163:1163:1163)) + (PORT datac (760:760:760) (817:817:817)) + (PORT datad (648:648:648) (669:669:669)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~99) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (816:816:816)) + (PORT datab (2351:2351:2351) (2480:2480:2480)) + (PORT datac (750:750:750) (859:859:859)) + (PORT datad (1843:1843:1843) (1894:1894:1894)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (275:275:275)) + (PORT datab (615:615:615) (668:668:668)) + (PORT datac (355:355:355) (385:385:385)) + (PORT datad (820:820:820) (847:847:847)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) + (DELAY + (ABSOLUTE + (PORT datac (2110:2110:2110) (2222:2222:2222)) + (PORT datad (1649:1649:1649) (1827:1827:1827)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (265:265:265)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (886:886:886) (924:924:924)) + (PORT datad (364:364:364) (387:387:387)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (389:389:389)) + (PORT datab (613:613:613) (635:635:635)) + (PORT datac (585:585:585) (595:595:595)) + (PORT datad (816:816:816) (824:824:824)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (276:276:276) (346:346:346)) + (PORT datab (1766:1766:1766) (1810:1810:1810)) + (PORT datac (251:251:251) (310:310:310)) + (PORT datad (225:225:225) (265:265:265)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (1008:1008:1008)) + (PORT datab (964:964:964) (1028:1028:1028)) + (PORT datac (1904:1904:1904) (1967:1967:1967)) + (PORT datad (644:644:644) (671:671:671)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (1056:1056:1056)) + (PORT datab (1415:1415:1415) (1547:1547:1547)) + (PORT datac (943:943:943) (1040:1040:1040)) + (PORT datad (818:818:818) (824:824:824)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (717:717:717)) + (PORT datab (1612:1612:1612) (1652:1652:1652)) + (PORT datac (1279:1279:1279) (1317:1317:1317)) + (PORT datad (1153:1153:1153) (1159:1159:1159)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~5) + (DELAY + (ABSOLUTE + (PORT datac (1943:1943:1943) (2004:2004:2004)) + (PORT datad (2062:2062:2062) (2197:2197:2197)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (266:266:266)) + (PORT datab (1497:1497:1497) (1573:1573:1573)) + (PORT datac (1953:1953:1953) (2008:2008:2008)) + (PORT datad (206:206:206) (244:244:244)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal48\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1982:1982:1982) (2045:2045:2045)) + (PORT datab (2098:2098:2098) (2238:2238:2238)) + (PORT datac (1468:1468:1468) (1539:1539:1539)) + (PORT datad (211:211:211) (249:249:249)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1990:1990:1990) (2089:2089:2089)) + (PORT datab (1214:1214:1214) (1264:1264:1264)) + (PORT datac (1724:1724:1724) (1792:1792:1792)) + (PORT datad (935:935:935) (979:979:979)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1491:1491:1491) (1544:1544:1544)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (1386:1386:1386) (1421:1421:1421)) + (PORT datad (614:614:614) (649:649:649)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1176:1176:1176) (1199:1199:1199)) + (PORT datab (1612:1612:1612) (1652:1652:1652)) + (PORT datac (885:885:885) (930:930:930)) + (PORT datad (893:893:893) (940:940:940)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (256:256:256)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (178:178:178) (215:215:215)) + (PORT datad (211:211:211) (242:242:242)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) + (DELAY + (ABSOLUTE + (PORT datab (2102:2102:2102) (2242:2242:2242)) + (PORT datac (1464:1464:1464) (1539:1539:1539)) + (PORT datad (208:208:208) (246:246:246)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) + (DELAY + (ABSOLUTE + (PORT datab (1474:1474:1474) (1558:1558:1558)) + (PORT datac (2114:2114:2114) (2223:2223:2223)) + (PORT datad (1649:1649:1649) (1828:1828:1828)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) + (DELAY + (ABSOLUTE + (PORT dataa (955:955:955) (1004:1004:1004)) + (PORT datab (1085:1085:1085) (1111:1111:1111)) + (PORT datac (644:644:644) (684:684:684)) + (PORT datad (629:629:629) (644:644:644)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~7) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (629:629:629)) + (PORT datab (917:917:917) (949:949:949)) + (PORT datac (586:586:586) (598:598:598)) + (PORT datad (1627:1627:1627) (1648:1648:1648)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (2251:2251:2251) (2329:2329:2329)) + (PORT datab (1611:1611:1611) (1741:1741:1741)) + (PORT datac (847:847:847) (879:879:879)) + (PORT datad (871:871:871) (887:887:887)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (686:686:686)) + (PORT datab (874:874:874) (906:906:906)) + (PORT datac (1698:1698:1698) (1732:1732:1732)) + (PORT datad (1500:1500:1500) (1556:1556:1556)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1145:1145:1145) (1213:1213:1213)) + (PORT datab (624:624:624) (655:655:655)) + (PORT datac (657:657:657) (701:701:701)) + (PORT datad (1183:1183:1183) (1213:1213:1213)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1234:1234:1234) (1292:1292:1292)) + (PORT datab (986:986:986) (1027:1027:1027)) + (PORT datac (1677:1677:1677) (1709:1709:1709)) + (PORT datad (1375:1375:1375) (1426:1426:1426)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (255:255:255)) + (PORT datab (1011:1011:1011) (1072:1072:1072)) + (PORT datac (1770:1770:1770) (1905:1905:1905)) + (PORT datad (1375:1375:1375) (1425:1425:1425)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (1014:1014:1014)) + (PORT datab (946:946:946) (992:992:992)) + (PORT datad (890:890:890) (963:963:963)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (271:271:271)) + (PORT datab (989:989:989) (1051:1051:1051)) + (PORT datac (804:804:804) (824:824:824)) + (PORT datad (1395:1395:1395) (1406:1406:1406)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1775:1775:1775) (1871:1871:1871)) + (PORT datab (1638:1638:1638) (1787:1787:1787)) + (PORT datad (1885:1885:1885) (1952:1952:1952)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1063:1063:1063) (1146:1146:1146)) + (PORT datac (1745:1745:1745) (1882:1882:1882)) + (PORT datad (635:635:635) (694:694:694)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1074:1074:1074) (1159:1159:1159)) + (PORT datab (921:921:921) (984:984:984)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (566:566:566) (581:581:581)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1917:1917:1917) (2022:2022:2022)) + (PORT datab (1506:1506:1506) (1587:1587:1587)) + (PORT datac (1606:1606:1606) (1725:1725:1725)) + (PORT datad (857:857:857) (891:891:891)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1474:1474:1474) (1533:1533:1533)) + (PORT datab (1245:1245:1245) (1280:1280:1280)) + (PORT datac (931:931:931) (1004:1004:1004)) + (PORT datad (845:845:845) (854:854:854)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (296:296:296)) + (PORT datab (1965:1965:1965) (2057:2057:2057)) + (PORT datac (1434:1434:1434) (1491:1491:1491)) + (PORT datad (1510:1510:1510) (1653:1653:1653)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1364:1364:1364) (1466:1466:1466)) + (PORT datab (1561:1561:1561) (1650:1650:1650)) + (PORT datac (2446:2446:2446) (2642:2642:2642)) + (PORT datad (1222:1222:1222) (1355:1355:1355)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1651:1651:1651) (1723:1723:1723)) + (PORT datab (935:935:935) (964:964:964)) + (PORT datac (2570:2570:2570) (2619:2619:2619)) + (PORT datad (771:771:771) (818:818:818)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1479:1479:1479) (1540:1540:1540)) + (PORT datab (603:603:603) (620:620:620)) + (PORT datac (1131:1131:1131) (1166:1166:1166)) + (PORT datad (578:578:578) (596:596:596)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1475:1475:1475) (1536:1536:1536)) + (PORT datab (1418:1418:1418) (1464:1464:1464)) + (PORT datac (928:928:928) (1006:1006:1006)) + (PORT datad (1413:1413:1413) (1432:1432:1432)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1777:1777:1777) (1900:1900:1900)) + (PORT datab (217:217:217) (256:256:256)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (723:723:723) (797:797:797)) + (PORT datab (1182:1182:1182) (1233:1233:1233)) + (PORT datac (1221:1221:1221) (1278:1278:1278)) + (PORT datad (894:894:894) (946:946:946)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (896:896:896)) + (PORT datab (1880:1880:1880) (2010:2010:2010)) + (PORT datac (329:329:329) (351:351:351)) + (PORT datad (1691:1691:1691) (1766:1766:1766)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (2180:2180:2180) (2359:2359:2359)) + (PORT datab (1395:1395:1395) (1458:1458:1458)) + (PORT datac (1425:1425:1425) (1436:1436:1436)) + (PORT datad (2268:2268:2268) (2359:2359:2359)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1302:1302:1302) (1373:1373:1373)) + (PORT datab (1199:1199:1199) (1239:1239:1239)) + (PORT datac (650:650:650) (720:720:720)) + (PORT datad (1152:1152:1152) (1181:1181:1181)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1459:1459:1459) (1482:1482:1482)) + (PORT datab (1177:1177:1177) (1245:1245:1245)) + (PORT datac (653:653:653) (721:721:721)) + (PORT datad (187:187:187) (219:219:219)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~19) + (DELAY + (ABSOLUTE + (PORT dataa (2144:2144:2144) (2265:2265:2265)) + (PORT datab (1689:1689:1689) (1868:1868:1868)) + (PORT datac (1147:1147:1147) (1206:1206:1206)) + (PORT datad (1953:1953:1953) (2015:2015:2015)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (894:894:894)) + (PORT datab (919:919:919) (952:952:952)) + (PORT datac (564:564:564) (581:581:581)) + (PORT datad (1104:1104:1104) (1103:1103:1103)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (938:938:938)) + (PORT datab (1034:1034:1034) (1098:1098:1098)) + (PORT datac (1178:1178:1178) (1210:1210:1210)) + (PORT datad (634:634:634) (667:667:667)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (687:687:687)) + (PORT datab (662:662:662) (710:710:710)) + (PORT datac (629:629:629) (681:681:681)) + (PORT datad (1142:1142:1142) (1152:1152:1152)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (670:670:670)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1177:1177:1177) (1212:1212:1212)) + (PORT datad (560:560:560) (587:587:587)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1325:1325:1325) (1384:1384:1384)) + (PORT datab (1536:1536:1536) (1559:1559:1559)) + (PORT datac (1403:1403:1403) (1539:1539:1539)) + (PORT datad (2538:2538:2538) (2656:2656:2656)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1484:1484:1484) (1532:1532:1532)) + (PORT datab (1506:1506:1506) (1597:1597:1597)) + (PORT datac (1663:1663:1663) (1679:1679:1679)) + (PORT datad (1485:1485:1485) (1617:1617:1617)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1250:1250:1250) (1306:1306:1306)) + (PORT datab (672:672:672) (706:706:706)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (678:678:678) (701:701:701)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2311:2311:2311) (2479:2479:2479)) + (PORT datab (2245:2245:2245) (2328:2328:2328)) + (PORT datac (1401:1401:1401) (1542:1542:1542)) + (PORT datad (1158:1158:1158) (1220:1220:1220)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal68\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1759:1759:1759) (1850:1850:1850)) + (PORT datab (1660:1660:1660) (1809:1809:1809)) + (PORT datac (1036:1036:1036) (1100:1100:1100)) + (PORT datad (1815:1815:1815) (1892:1892:1892)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1443:1443:1443) (1550:1550:1550)) + (PORT datab (1149:1149:1149) (1188:1188:1188)) + (PORT datac (809:809:809) (820:820:820)) + (PORT datad (1490:1490:1490) (1622:1622:1622)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal63\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1059:1059:1059) (1127:1127:1127)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datac (1714:1714:1714) (1797:1797:1797)) + (PORT datad (1525:1525:1525) (1626:1626:1626)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal76\~2) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (691:691:691)) + (PORT datac (2229:2229:2229) (2297:2297:2297)) + (PORT datad (1684:1684:1684) (1744:1744:1744)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (670:670:670)) + (PORT datab (1492:1492:1492) (1549:1549:1549)) + (PORT datac (1215:1215:1215) (1263:1263:1263)) + (PORT datad (558:558:558) (582:582:582)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1853:1853:1853) (1956:1956:1956)) + (PORT datab (895:895:895) (912:912:912)) + (PORT datac (850:850:850) (899:899:899)) + (PORT datad (1512:1512:1512) (1544:1544:1544)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1106:1106:1106) (1144:1144:1144)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1215:1215:1215) (1263:1263:1263)) + (PORT datad (914:914:914) (954:954:954)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (705:705:705)) + (PORT datab (384:384:384) (412:412:412)) + (PORT datac (1156:1156:1156) (1181:1181:1181)) + (PORT datad (941:941:941) (985:985:985)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) + (DELAY + (ABSOLUTE + (PORT dataa (1248:1248:1248) (1328:1328:1328)) + (PORT datab (986:986:986) (1055:1055:1055)) + (PORT datac (840:840:840) (878:878:878)) + (PORT datad (1355:1355:1355) (1447:1447:1447)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (936:936:936)) + (PORT datab (1220:1220:1220) (1268:1268:1268)) + (PORT datac (1208:1208:1208) (1289:1289:1289)) + (PORT datad (683:683:683) (740:740:740)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (2075:2075:2075) (2210:2210:2210)) + (PORT datab (1511:1511:1511) (1577:1577:1577)) + (PORT datac (590:590:590) (639:639:639)) + (PORT datad (2101:2101:2101) (2201:2201:2201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~7) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (976:976:976)) + (PORT datab (251:251:251) (299:299:299)) + (PORT datac (1219:1219:1219) (1264:1264:1264)) + (PORT datad (1755:1755:1755) (1827:1827:1827)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (296:296:296)) + (PORT datab (645:645:645) (664:664:664)) + (PORT datac (180:180:180) (215:215:215)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~3) + (DELAY + (ABSOLUTE + (PORT dataa (997:997:997) (1069:1069:1069)) + (PORT datab (877:877:877) (902:902:902)) + (PORT datac (1046:1046:1046) (1134:1134:1134)) + (PORT datad (1269:1269:1269) (1355:1355:1355)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (913:913:913)) + (PORT datab (636:636:636) (660:660:660)) + (PORT datac (1654:1654:1654) (1746:1746:1746)) + (PORT datad (1116:1116:1116) (1186:1186:1186)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (724:724:724) (791:791:791)) + (PORT datab (1248:1248:1248) (1307:1307:1307)) + (PORT datac (1288:1288:1288) (1402:1402:1402)) + (PORT datad (896:896:896) (946:946:946)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (397:397:397) (427:427:427)) + (PORT datab (1208:1208:1208) (1268:1268:1268)) + (PORT datac (959:959:959) (1038:1038:1038)) + (PORT datad (1924:1924:1924) (2082:2082:2082)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) + (DELAY + (ABSOLUTE + (PORT dataa (1318:1318:1318) (1375:1375:1375)) + (PORT datab (1540:1540:1540) (1661:1661:1661)) + (PORT datac (2217:2217:2217) (2299:2299:2299)) + (PORT datad (919:919:919) (967:967:967)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (2563:2563:2563) (2766:2766:2766)) + (PORT datab (1244:1244:1244) (1298:1298:1298)) + (PORT datac (873:873:873) (937:937:937)) + (PORT datad (2161:2161:2161) (2331:2331:2331)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1265:1265:1265) (1296:1296:1296)) + (PORT datac (1421:1421:1421) (1419:1419:1419)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (671:671:671)) + (PORT datab (1250:1250:1250) (1279:1279:1279)) + (PORT datac (1879:1879:1879) (2050:2050:2050)) + (PORT datad (1649:1649:1649) (1832:1832:1832)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1274:1274:1274)) + (PORT datab (571:571:571) (582:582:582)) + (PORT datac (2046:2046:2046) (2173:2173:2173)) + (PORT datad (1308:1308:1308) (1448:1448:1448)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (278:278:278)) + (PORT datab (686:686:686) (703:703:703)) + (PORT datac (878:878:878) (936:936:936)) + (PORT datad (312:312:312) (329:329:329)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1624:1624:1624) (1672:1672:1672)) + (PORT datab (1493:1493:1493) (1610:1610:1610)) + (PORT datac (178:178:178) (216:216:216)) + (PORT datad (694:694:694) (748:748:748)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal10\~1) + (DELAY + (ABSOLUTE + (PORT datac (2148:2148:2148) (2195:2195:2195)) + (PORT datad (1421:1421:1421) (1470:1470:1470)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) + (DELAY + (ABSOLUTE + (PORT dataa (1212:1212:1212) (1275:1275:1275)) + (PORT datab (1443:1443:1443) (1483:1483:1483)) + (PORT datac (178:178:178) (216:216:216)) + (PORT datad (1433:1433:1433) (1518:1518:1518)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal69\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1981:1981:1981) (2045:2045:2045)) + (PORT datab (2097:2097:2097) (2238:2238:2238)) + (PORT datac (1468:1468:1468) (1539:1539:1539)) + (PORT datad (211:211:211) (249:249:249)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1873:1873:1873) (1941:1941:1941)) + (PORT datab (1345:1345:1345) (1486:1486:1486)) + (PORT datac (2046:2046:2046) (2172:2172:2172)) + (PORT datad (2102:2102:2102) (2203:2203:2203)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1755:1755:1755) (1823:1823:1823)) + (PORT datab (924:924:924) (949:949:949)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (621:621:621) (652:652:652)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (641:641:641) (662:662:662)) + (PORT datac (603:603:603) (623:623:623)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (995:995:995) (1066:1066:1066)) + (PORT datab (876:876:876) (900:900:900)) + (PORT datac (1640:1640:1640) (1827:1827:1827)) + (PORT datad (2138:2138:2138) (2305:2305:2305)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1112:1112:1112) (1152:1152:1152)) + (PORT datab (216:216:216) (259:259:259)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (863:863:863) (899:899:899)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (285:285:285) (352:352:352)) + (PORT datab (251:251:251) (304:304:304)) + (PORT datac (1170:1170:1170) (1219:1219:1219)) + (PORT datad (248:248:248) (302:302:302)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1554:1554:1554) (1689:1689:1689)) + (PORT datab (1993:1993:1993) (2047:2047:2047)) + (PORT datac (873:873:873) (939:939:939)) + (PORT datad (1697:1697:1697) (1792:1792:1792)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1238:1238:1238) (1290:1290:1290)) + (PORT datab (616:616:616) (641:641:641)) + (PORT datac (619:619:619) (670:670:670)) + (PORT datad (890:890:890) (915:915:915)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1847:1847:1847) (1963:1963:1963)) + (PORT datab (926:926:926) (986:986:986)) + (PORT datad (638:638:638) (671:671:671)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (1154:1154:1154) (1181:1181:1181)) + (PORT datac (320:320:320) (344:344:344)) + (PORT datad (663:663:663) (726:726:726)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (227:227:227) (267:267:267)) + (PORT datac (613:613:613) (637:637:637)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1847:1847:1847) (1960:1960:1960)) + (PORT datab (674:674:674) (708:708:708)) + (PORT datac (179:179:179) (213:213:213)) + (PORT datad (903:903:903) (947:947:947)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~20) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1091:1091:1091)) + (PORT datab (1843:1843:1843) (1936:1936:1936)) + (PORT datac (990:990:990) (1056:1056:1056)) + (PORT datad (1223:1223:1223) (1265:1265:1265)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (2284:2284:2284) (2463:2463:2463)) + (PORT datab (1844:1844:1844) (1935:1935:1935)) + (PORT datac (867:867:867) (913:913:913)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (852:852:852) (886:886:886)) + (PORT datab (1403:1403:1403) (1513:1513:1513)) + (PORT datac (650:650:650) (711:711:711)) + (PORT datad (671:671:671) (755:755:755)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (277:277:277) (348:348:348)) + (PORT datab (250:250:250) (300:300:300)) + (PORT datac (247:247:247) (306:306:306)) + (PORT datad (1203:1203:1203) (1275:1275:1275)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (793:793:793) (857:857:857)) + (PORT datab (630:630:630) (708:708:708)) + (PORT datac (832:832:832) (885:885:885)) + (PORT datad (661:661:661) (724:724:724)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (1562:1562:1562) (1606:1606:1606)) + (PORT datac (2770:2770:2770) (2816:2816:2816)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (703:703:703)) + (PORT datab (377:377:377) (403:403:403)) + (PORT datac (180:180:180) (218:218:218)) + (PORT datad (896:896:896) (921:921:921)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) + (DELAY + (ABSOLUTE + (PORT dataa (1286:1286:1286) (1375:1375:1375)) + (PORT datab (1004:1004:1004) (1054:1054:1054)) + (PORT datac (959:959:959) (1026:1026:1026)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1222:1222:1222) (1224:1224:1224)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) + (DELAY + (ABSOLUTE + (PORT dataa (1286:1286:1286) (1372:1372:1372)) + (PORT datab (1005:1005:1005) (1052:1052:1052)) + (PORT datac (959:959:959) (1023:1023:1023)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1461:1461:1461) (1557:1557:1557)) + (PORT datab (1071:1071:1071) (1131:1131:1131)) + (PORT datac (1183:1183:1183) (1237:1237:1237)) + (PORT datad (1422:1422:1422) (1471:1471:1471)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (656:656:656)) + (PORT datab (204:204:204) (244:244:244)) + (PORT datac (1380:1380:1380) (1388:1388:1388)) + (PORT datad (1256:1256:1256) (1311:1311:1311)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1542:1542:1542) (1647:1647:1647)) + (PORT datab (1761:1761:1761) (1804:1804:1804)) + (PORT datac (605:605:605) (628:628:628)) + (PORT datad (631:631:631) (654:654:654)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~47) + (DELAY + (ABSOLUTE + (PORT datab (688:688:688) (737:737:737)) + (PORT datac (381:381:381) (410:410:410)) + (PORT datad (853:853:853) (891:891:891)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (939:939:939)) + (PORT datab (1244:1244:1244) (1260:1260:1260)) + (PORT datac (187:187:187) (227:227:227)) + (PORT datad (1433:1433:1433) (1449:1449:1449)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (925:925:925)) + (PORT datab (684:684:684) (737:737:737)) + (PORT datac (875:875:875) (914:914:914)) + (PORT datad (1472:1472:1472) (1513:1513:1513)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (671:671:671)) + (PORT datab (684:684:684) (737:737:737)) + (PORT datac (1663:1663:1663) (1676:1676:1676)) + (PORT datad (367:367:367) (388:388:388)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (673:673:673)) + (PORT datab (1692:1692:1692) (1710:1710:1710)) + (PORT datac (836:836:836) (839:839:839)) + (PORT datad (827:827:827) (859:859:859)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (669:669:669)) + (PORT datab (901:901:901) (931:931:931)) + (PORT datac (1661:1661:1661) (1674:1674:1674)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) + (DELAY + (ABSOLUTE + (PORT datab (637:637:637) (657:657:657)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (1340:1340:1340) (1496:1496:1496)) + (PORT datac (1960:1960:1960) (2130:2130:2130)) + (PORT datad (1151:1151:1151) (1205:1205:1205)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1798:1798:1798) (1873:1873:1873)) + (PORT datab (247:247:247) (295:295:295)) + (PORT datac (880:880:880) (894:894:894)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~41) + (DELAY + (ABSOLUTE + (PORT datab (924:924:924) (979:979:979)) + (PORT datac (1035:1035:1035) (1109:1109:1109)) + (PORT datad (617:617:617) (626:626:626)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1681:1681:1681) (1791:1791:1791)) + (PORT datab (1812:1812:1812) (1917:1917:1917)) + (PORT datac (1337:1337:1337) (1365:1365:1365)) + (PORT datad (637:637:637) (687:687:687)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (974:974:974)) + (PORT datab (1062:1062:1062) (1114:1114:1114)) + (PORT datac (1488:1488:1488) (1575:1575:1575)) + (PORT datad (1194:1194:1194) (1262:1262:1262)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (250:250:250)) + (PORT datab (1520:1520:1520) (1602:1602:1602)) + (PORT datac (1087:1087:1087) (1105:1105:1105)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (960:960:960)) + (PORT datab (1658:1658:1658) (1699:1699:1699)) + (PORT datac (1280:1280:1280) (1331:1331:1331)) + (PORT datad (1594:1594:1594) (1614:1614:1614)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (668:668:668)) + (PORT datac (1213:1213:1213) (1256:1256:1256)) + (PORT datad (886:886:886) (936:936:936)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1441:1441:1441) (1479:1479:1479)) + (PORT datab (646:646:646) (667:667:667)) + (PORT datac (177:177:177) (213:213:213)) + (PORT datad (939:939:939) (976:976:976)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) + (DELAY + (ABSOLUTE + (PORT datac (588:588:588) (596:596:596)) + (PORT datad (863:863:863) (883:883:883)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (830:830:830) (842:842:842)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) + (DELAY + (ABSOLUTE + (PORT datab (366:366:366) (387:387:387)) + (PORT datac (593:593:593) (608:608:608)) + (PORT datad (614:614:614) (631:631:631)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1311:1311:1311) (1357:1357:1357)) + (PORT datab (1610:1610:1610) (1651:1651:1651)) + (PORT datac (968:968:968) (1039:1039:1039)) + (PORT datad (2195:2195:2195) (2176:2176:2176)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (859:859:859)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (965:965:965) (1009:1009:1009)) + (PORT datad (1114:1114:1114) (1140:1140:1140)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1155:1155:1155) (1199:1199:1199)) + (PORT datab (902:902:902) (932:932:932)) + (PORT datac (956:956:956) (1022:1022:1022)) + (PORT datad (196:196:196) (233:233:233)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1279:1279:1279) (1383:1383:1383)) + (PORT datab (637:637:637) (659:659:659)) + (PORT datac (187:187:187) (227:227:227)) + (PORT datad (955:955:955) (1046:1046:1046)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) + (DELAY + (ABSOLUTE + (PORT datab (1245:1245:1245) (1295:1295:1295)) + (PORT datac (935:935:935) (984:984:984)) + (PORT datad (898:898:898) (966:966:966)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1175:1175:1175) (1219:1219:1219)) + (PORT datab (911:911:911) (944:944:944)) + (PORT datac (1136:1136:1136) (1156:1156:1156)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) + (DELAY + (ABSOLUTE + (PORT datab (1342:1342:1342) (1372:1372:1372)) + (PORT datad (1144:1144:1144) (1175:1175:1175)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (670:670:670)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (817:817:817) (835:835:835)) + (PORT datad (822:822:822) (842:842:842)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (675:675:675)) + (PORT datab (983:983:983) (1074:1074:1074)) + (PORT datac (1087:1087:1087) (1097:1097:1097)) + (PORT datad (1806:1806:1806) (1916:1916:1916)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (674:674:674)) + (PORT datab (947:947:947) (979:979:979)) + (PORT datac (371:371:371) (399:399:399)) + (PORT datad (179:179:179) (206:206:206)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (618:618:618) (631:631:631)) + (PORT datac (871:871:871) (877:877:877)) + (PORT datad (577:577:577) (595:595:595)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) + (DELAY + (ABSOLUTE + (PORT dataa (1287:1287:1287) (1376:1376:1376)) + (PORT datab (978:978:978) (1026:1026:1026)) + (PORT datac (966:966:966) (1015:1015:1015)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) + (DELAY + (ABSOLUTE + (PORT dataa (1276:1276:1276) (1362:1362:1362)) + (PORT datab (973:973:973) (1025:1025:1025)) + (PORT datac (974:974:974) (1023:1023:1023)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (536:536:536) (565:565:565)) + (PORT ena (1237:1237:1237) (1220:1220:1220)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (969:969:969)) + (PORT datab (2629:2629:2629) (2685:2685:2685)) + (PORT datac (187:187:187) (228:228:228)) + (PORT datad (1382:1382:1382) (1417:1417:1417)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_exx\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1904:1904:1904) (2087:2087:2087)) + (PORT datab (1498:1498:1498) (1565:1565:1565)) + (PORT datad (1153:1153:1153) (1185:1185:1185)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_exx) + (DELAY + (ABSOLUTE + (PORT clk (1533:1533:1533) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1931:1931:1931) (1907:1907:1907)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1652:1652:1652) (1684:1684:1684)) + (PORT datab (1728:1728:1728) (1737:1737:1737)) + (PORT datac (1191:1191:1191) (1239:1239:1239)) + (PORT datad (1223:1223:1223) (1265:1265:1265)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1220:1220:1220) (1242:1242:1242)) + (PORT datab (1206:1206:1206) (1263:1263:1263)) + (PORT datac (1663:1663:1663) (1680:1680:1680)) + (PORT datad (577:577:577) (596:596:596)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1493:1493:1493) (1541:1541:1541)) + (PORT datab (957:957:957) (1012:1012:1012)) + (PORT datac (1200:1200:1200) (1254:1254:1254)) + (PORT datad (1188:1188:1188) (1238:1238:1238)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (653:653:653)) + (PORT datab (1866:1866:1866) (1943:1943:1943)) + (PORT datac (1028:1028:1028) (1092:1092:1092)) + (PORT datad (2619:2619:2619) (2697:2697:2697)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~56) + (DELAY + (ABSOLUTE + (PORT dataa (1223:1223:1223) (1275:1275:1275)) + (PORT datab (1259:1259:1259) (1303:1303:1303)) + (PORT datac (863:863:863) (935:935:935)) + (PORT datad (890:890:890) (967:967:967)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) + (DELAY + (ABSOLUTE + (PORT datab (908:908:908) (944:944:944)) + (PORT datac (636:636:636) (655:655:655)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (232:232:232) (283:283:283)) + (PORT datac (2706:2706:2706) (2903:2903:2903)) + (PORT datad (218:218:218) (253:253:253)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1596:1596:1596) (1646:1646:1646)) + (PORT datab (1499:1499:1499) (1573:1573:1573)) + (PORT datac (1471:1471:1471) (1570:1570:1570)) + (PORT datad (1124:1124:1124) (1141:1141:1141)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1244:1244:1244) (1329:1329:1329)) + (PORT datab (984:984:984) (1057:1057:1057)) + (PORT datac (1948:1948:1948) (2028:2028:2028)) + (PORT datad (1356:1356:1356) (1450:1450:1450)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1478:1478:1478) (1539:1539:1539)) + (PORT datab (1303:1303:1303) (1403:1403:1403)) + (PORT datac (929:929:929) (1005:1005:1005)) + (PORT datad (1508:1508:1508) (1652:1652:1652)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (1003:1003:1003)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (592:592:592) (642:642:642)) + (PORT datad (1235:1235:1235) (1275:1275:1275)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1525:1525:1525) (1588:1588:1588)) + (PORT datab (901:901:901) (934:934:934)) + (PORT datac (1455:1455:1455) (1495:1495:1495)) + (PORT datad (682:682:682) (736:736:736)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (956:956:956) (974:974:974)) + (PORT datac (625:625:625) (647:647:647)) + (PORT datad (575:575:575) (606:606:606)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) + (DELAY + (ABSOLUTE + (PORT dataa (679:679:679) (725:725:725)) + (PORT datab (1120:1120:1120) (1176:1176:1176)) + (PORT datac (1928:1928:1928) (1998:1998:1998)) + (PORT datad (809:809:809) (845:845:845)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (989:989:989)) + (PORT datab (556:556:556) (587:587:587)) + (PORT datac (963:963:963) (1008:1008:1008)) + (PORT datad (929:929:929) (951:951:951)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (376:376:376)) + (PORT datab (249:249:249) (290:290:290)) + (PORT datac (963:963:963) (1005:1005:1005)) + (PORT datad (929:929:929) (948:948:948)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~52) + (DELAY + (ABSOLUTE + (PORT dataa (983:983:983) (1101:1101:1101)) + (PORT datab (783:783:783) (890:890:890)) + (PORT datac (726:726:726) (838:838:838)) + (PORT datad (626:626:626) (675:675:675)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1200:1200:1200) (1286:1286:1286)) + (PORT datab (342:342:342) (372:372:372)) + (PORT datac (1901:1901:1901) (2064:2064:2064)) + (PORT datad (617:617:617) (629:629:629)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (278:278:278)) + (PORT datab (397:397:397) (437:437:437)) + (PORT datac (975:975:975) (1014:1014:1014)) + (PORT datad (812:812:812) (837:837:837)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (1213:1213:1213) (1257:1257:1257)) + (PORT datad (323:323:323) (347:347:347)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1627:1627:1627) (1675:1675:1675)) + (PORT datab (1195:1195:1195) (1246:1246:1246)) + (PORT datac (1289:1289:1289) (1403:1403:1403)) + (PORT datad (691:691:691) (746:746:746)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (274:274:274)) + (PORT datab (614:614:614) (638:638:638)) + (PORT datac (1132:1132:1132) (1151:1151:1151)) + (PORT datad (696:696:696) (744:744:744)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (726:726:726) (791:791:791)) + (PORT datab (668:668:668) (719:719:719)) + (PORT datac (639:639:639) (684:684:684)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (220:220:220) (258:258:258)) + (PORT datac (1154:1154:1154) (1175:1175:1175)) + (PORT datad (179:179:179) (207:207:207)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (639:639:639)) + (PORT datab (1176:1176:1176) (1220:1220:1220)) + (PORT datac (1428:1428:1428) (1462:1462:1462)) + (PORT datad (862:862:862) (888:888:888)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (239:239:239) (291:291:291)) + (PORT datab (986:986:986) (1028:1028:1028)) + (PORT datac (645:645:645) (702:702:702)) + (PORT datad (319:319:319) (331:331:331)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) + (DELAY + (ABSOLUTE + (PORT datab (3601:3601:3601) (3704:3704:3704)) + (PORT datad (1514:1514:1514) (1586:1586:1586)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~8) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (641:641:641)) + (PORT datab (1172:1172:1172) (1203:1203:1203)) + (PORT datac (626:626:626) (659:659:659)) + (PORT datad (828:828:828) (846:846:846)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~48) + (DELAY + (ABSOLUTE + (PORT dataa (1853:1853:1853) (1955:1955:1955)) + (PORT datab (899:899:899) (946:946:946)) + (PORT datac (894:894:894) (920:920:920)) + (PORT datad (854:854:854) (879:879:879)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) + (DELAY + (ABSOLUTE + (PORT datab (672:672:672) (700:700:700)) + (PORT datad (1120:1120:1120) (1145:1145:1145)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~2) + (DELAY + (ABSOLUTE + (PORT datab (885:885:885) (918:918:918)) + (PORT datac (1069:1069:1069) (1130:1130:1130)) + (PORT datad (1496:1496:1496) (1538:1538:1538)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~49) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (390:390:390)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (552:552:552) (564:564:564)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1647:1647:1647) (1826:1826:1826)) + (PORT datab (1263:1263:1263) (1332:1332:1332)) + (PORT datac (1375:1375:1375) (1403:1403:1403)) + (PORT datad (588:588:588) (608:608:608)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2251:2251:2251) (2328:2328:2328)) + (PORT datab (879:879:879) (911:911:911)) + (PORT datac (1575:1575:1575) (1707:1707:1707)) + (PORT datad (1688:1688:1688) (1747:1747:1747)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (972:972:972)) + (PORT datab (1342:1342:1342) (1395:1395:1395)) + (PORT datac (866:866:866) (929:929:929)) + (PORT datad (1427:1427:1427) (1449:1449:1449)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (725:725:725)) + (PORT datab (1471:1471:1471) (1517:1517:1517)) + (PORT datac (849:849:849) (874:874:874)) + (PORT datad (669:669:669) (723:723:723)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1233:1233:1233) (1315:1315:1315)) + (PORT datab (936:936:936) (978:978:978)) + (PORT datac (1411:1411:1411) (1475:1475:1475)) + (PORT datad (1767:1767:1767) (1823:1823:1823)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT datac (859:859:859) (876:876:876)) + (PORT datad (327:327:327) (351:351:351)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (655:655:655) (688:688:688)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (975:975:975)) + (PORT datab (986:986:986) (1041:1041:1041)) + (PORT datac (871:871:871) (933:933:933)) + (PORT datad (885:885:885) (915:915:915)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1793:1793:1793) (1875:1875:1875)) + (PORT datab (1527:1527:1527) (1572:1572:1572)) + (PORT datac (1068:1068:1068) (1127:1127:1127)) + (PORT datad (856:856:856) (879:879:879)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1174:1174:1174) (1222:1222:1222)) + (PORT datab (882:882:882) (915:915:915)) + (PORT datac (1069:1069:1069) (1128:1128:1128)) + (PORT datad (1492:1492:1492) (1533:1533:1533)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1761:1761:1761) (1832:1832:1832)) + (PORT datab (1926:1926:1926) (1967:1967:1967)) + (PORT datac (1557:1557:1557) (1584:1584:1584)) + (PORT datad (1049:1049:1049) (1102:1102:1102)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) + (DELAY + (ABSOLUTE + (PORT dataa (239:239:239) (287:287:287)) + (PORT datab (237:237:237) (282:282:282)) + (PORT datac (1015:1015:1015) (1061:1061:1061)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1650:1650:1650) (1827:1827:1827)) + (PORT datac (1232:1232:1232) (1346:1346:1346)) + (PORT datad (1116:1116:1116) (1144:1144:1144)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1406:1406:1406) (1446:1446:1446)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (825:825:825) (841:841:841)) + (PORT datad (838:838:838) (886:886:886)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1230:1230:1230)) + (PORT datac (917:917:917) (956:956:956)) + (PORT datad (859:859:859) (899:899:899)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1321:1321:1321) (1383:1383:1383)) + (PORT datab (933:933:933) (971:971:971)) + (PORT datac (1396:1396:1396) (1536:1536:1536)) + (PORT datad (1181:1181:1181) (1244:1244:1244)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (978:978:978)) + (PORT datab (1540:1540:1540) (1664:1664:1664)) + (PORT datac (2216:2216:2216) (2296:2296:2296)) + (PORT datad (1530:1530:1530) (1622:1622:1622)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (276:276:276)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (1184:1184:1184) (1245:1245:1245)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1647:1647:1647) (1822:1822:1822)) + (PORT datab (355:355:355) (385:385:385)) + (PORT datac (1228:1228:1228) (1341:1341:1341)) + (PORT datad (604:604:604) (639:639:639)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~30) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (641:641:641)) + (PORT datab (966:966:966) (999:999:999)) + (PORT datac (663:663:663) (694:694:694)) + (PORT datad (594:594:594) (614:614:614)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (901:901:901)) + (PORT datab (211:211:211) (255:255:255)) + (PORT datac (192:192:192) (223:223:223)) + (PORT datad (1560:1560:1560) (1654:1654:1654)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (631:631:631)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (628:628:628) (658:658:658)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (643:643:643) (669:669:669)) + (PORT datac (823:823:823) (829:829:829)) + (PORT datad (1688:1688:1688) (1742:1742:1742)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (393:393:393)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (1204:1204:1204) (1257:1257:1257)) + (PORT datad (1048:1048:1048) (1082:1082:1082)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) + (DELAY + (ABSOLUTE + (PORT dataa (1360:1360:1360) (1460:1460:1460)) + (PORT datab (1167:1167:1167) (1197:1197:1197)) + (PORT datad (1607:1607:1607) (1719:1719:1719)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1598:1598:1598) (1645:1645:1645)) + (PORT datab (1618:1618:1618) (1773:1773:1773)) + (PORT datac (872:872:872) (933:933:933)) + (PORT datad (1311:1311:1311) (1374:1374:1374)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (440:440:440)) + (PORT datab (246:246:246) (294:294:294)) + (PORT datac (1467:1467:1467) (1528:1528:1528)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1424:1424:1424) (1502:1502:1502)) + (PORT datab (1104:1104:1104) (1116:1116:1116)) + (PORT datac (1503:1503:1503) (1564:1564:1564)) + (PORT datad (635:635:635) (657:657:657)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (647:647:647)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (617:617:617) (656:656:656)) + (PORT datad (631:631:631) (650:650:650)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1232:1232:1232) (1293:1293:1293)) + (PORT datab (2419:2419:2419) (2477:2477:2477)) + (PORT datac (1675:1675:1675) (1710:1710:1710)) + (PORT datad (985:985:985) (1038:1038:1038)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (982:982:982) (1100:1100:1100)) + (PORT datab (759:759:759) (866:866:866)) + (PORT datac (608:608:608) (629:629:629)) + (PORT datad (884:884:884) (917:917:917)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1159:1159:1159) (1204:1204:1204)) + (PORT datab (372:372:372) (397:397:397)) + (PORT datac (920:920:920) (973:973:973)) + (PORT datad (818:818:818) (865:865:865)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (242:242:242) (289:289:289)) + (PORT datac (202:202:202) (247:247:247)) + (PORT datad (868:868:868) (925:925:925)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1541:1541:1541) (1598:1598:1598)) + (PORT datab (1027:1027:1027) (1116:1116:1116)) + (PORT datac (337:337:337) (366:366:366)) + (PORT datad (196:196:196) (232:232:232)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1398:1398:1398) (1425:1425:1425)) + (PORT datab (1123:1123:1123) (1145:1145:1145)) + (PORT datac (1387:1387:1387) (1417:1417:1417)) + (PORT datad (337:337:337) (362:362:362)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (955:955:955)) + (PORT datab (705:705:705) (772:772:772)) + (PORT datac (665:665:665) (748:748:748)) + (PORT datad (575:575:575) (591:591:591)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (500:500:500)) + (PORT datab (269:269:269) (353:353:353)) + (PORT datac (1395:1395:1395) (1507:1507:1507)) + (PORT datad (1175:1175:1175) (1258:1258:1258)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1596:1596:1596) (1729:1729:1729)) + (PORT datab (1938:1938:1938) (2043:2043:2043)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (2588:2588:2588) (2666:2666:2666)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2229:2229:2229) (2274:2274:2274)) + (PORT datab (2486:2486:2486) (2693:2693:2693)) + (PORT datac (2230:2230:2230) (2299:2299:2299)) + (PORT datad (1642:1642:1642) (1694:1694:1694)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1211:1211:1211) (1286:1286:1286)) + (PORT datab (879:879:879) (905:905:905)) + (PORT datac (2230:2230:2230) (2302:2302:2302)) + (PORT datad (2452:2452:2452) (2652:2652:2652)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (2068:2068:2068) (2112:2112:2112)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (865:865:865)) + (PORT datab (828:828:828) (846:846:846)) + (PORT datac (1565:1565:1565) (1694:1694:1694)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (400:400:400)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (1200:1200:1200) (1252:1252:1252)) + (PORT datad (861:861:861) (911:911:911)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~2) + (DELAY + (ABSOLUTE + (PORT datac (858:858:858) (869:869:869)) + (PORT datad (1351:1351:1351) (1366:1366:1366)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1499:1499:1499) (1515:1515:1515)) + (PORT datab (1191:1191:1191) (1239:1239:1239)) + (PORT datac (1752:1752:1752) (1874:1874:1874)) + (PORT datad (1446:1446:1446) (1521:1521:1521)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (947:947:947)) + (PORT datab (683:683:683) (705:705:705)) + (PORT datac (2071:2071:2071) (2251:2251:2251)) + (PORT datad (1432:1432:1432) (1451:1451:1451)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (752:752:752) (844:844:844)) + (PORT datab (887:887:887) (909:909:909)) + (PORT datad (1197:1197:1197) (1224:1224:1224)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (306:306:306) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de1) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1591:1591:1591) (1568:1568:1568)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (751:751:751) (842:842:842)) + (PORT datab (225:225:225) (273:273:273)) + (PORT datac (788:788:788) (792:792:792)) + (PORT datad (224:224:224) (296:296:296)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) + (DELAY + (ABSOLUTE + (PORT dataa (1063:1063:1063) (1149:1149:1149)) + (PORT datab (922:922:922) (983:983:983)) + (PORT datac (1898:1898:1898) (2064:2064:2064)) + (PORT datad (1207:1207:1207) (1289:1289:1289)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~50) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (939:939:939)) + (PORT datab (457:457:457) (532:532:532)) + (PORT datac (420:420:420) (489:489:489)) + (PORT datad (984:984:984) (1034:1034:1034)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1830:1830:1830) (1974:1974:1974)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (678:678:678) (727:727:727)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1113:1113:1113) (1151:1151:1151)) + (PORT datab (1237:1237:1237) (1272:1272:1272)) + (PORT datac (1201:1201:1201) (1255:1255:1255)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (700:700:700) (759:759:759)) + (PORT datab (1508:1508:1508) (1551:1551:1551)) + (PORT datac (1985:1985:1985) (2041:2041:2041)) + (PORT datad (1440:1440:1440) (1501:1501:1501)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (933:933:933)) + (PORT datab (219:219:219) (256:256:256)) + (PORT datac (316:316:316) (335:335:335)) + (PORT datad (590:590:590) (623:623:623)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (2828:2828:2828) (3036:3036:3036)) + (PORT datab (1101:1101:1101) (1114:1114:1114)) + (PORT datac (1504:1504:1504) (1566:1566:1566)) + (PORT datad (1269:1269:1269) (1342:1342:1342)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (900:900:900)) + (PORT datab (215:215:215) (260:260:260)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1558:1558:1558) (1654:1654:1654)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1205:1205:1205) (1284:1284:1284)) + (PORT datab (1396:1396:1396) (1445:1445:1445)) + (PORT datac (1194:1194:1194) (1232:1232:1232)) + (PORT datad (1411:1411:1411) (1507:1507:1507)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1245:1245:1245) (1304:1304:1304)) + (PORT datab (865:865:865) (920:920:920)) + (PORT datac (1734:1734:1734) (1769:1769:1769)) + (PORT datad (823:823:823) (888:888:888)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (723:723:723) (790:790:790)) + (PORT datac (1371:1371:1371) (1479:1479:1479)) + (PORT datad (672:672:672) (752:752:752)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1087:1087:1087) (1120:1120:1120)) + (PORT datab (228:228:228) (269:269:269)) + (PORT datac (1374:1374:1374) (1452:1452:1452)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (773:773:773)) + (PORT datab (666:666:666) (735:735:735)) + (PORT datac (1203:1203:1203) (1259:1259:1259)) + (PORT datad (1108:1108:1108) (1151:1151:1151)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1122:1122:1122) (1172:1172:1172)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel3) + (DELAY + (ABSOLUTE + (PORT dataa (2260:2260:2260) (2337:2337:2337)) + (PORT datac (1572:1572:1572) (1704:1704:1704)) + (PORT datad (1683:1683:1683) (1743:1743:1743)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1463:1463:1463) (1491:1491:1491)) + (PORT datab (1113:1113:1113) (1143:1143:1143)) + (PORT datac (321:321:321) (347:347:347)) + (PORT datad (606:606:606) (641:641:641)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (1280:1280:1280) (1380:1380:1380)) + (PORT datab (980:980:980) (1076:1076:1076)) + (PORT datac (892:892:892) (917:917:917)) + (PORT datad (615:615:615) (665:665:665)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (661:661:661)) + (PORT datab (1481:1481:1481) (1539:1539:1539)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (1257:1257:1257) (1315:1315:1315)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1002:1002:1002) (1063:1063:1063)) + (PORT datab (906:906:906) (923:923:923)) + (PORT datac (174:174:174) (207:207:207)) + (PORT datad (890:890:890) (926:926:926)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (233:233:233) (284:284:284)) + (PORT datac (865:865:865) (890:890:890)) + (PORT datad (217:217:217) (249:249:249)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel0) + (DELAY + (ABSOLUTE + (PORT dataa (2362:2362:2362) (2435:2435:2435)) + (PORT datab (2736:2736:2736) (2936:2936:2936)) + (PORT datad (869:869:869) (926:926:926)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (668:668:668)) + (PORT datab (632:632:632) (661:661:661)) + (PORT datac (624:624:624) (652:652:652)) + (PORT datad (1153:1153:1153) (1193:1193:1193)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (664:664:664)) + (PORT datab (641:641:641) (658:658:658)) + (PORT datac (649:649:649) (669:669:669)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) + (DELAY + (ABSOLUTE + (PORT dataa (1429:1429:1429) (1578:1578:1578)) + (PORT datab (948:948:948) (1000:1000:1000)) + (PORT datac (1287:1287:1287) (1342:1342:1342)) + (PORT datad (1181:1181:1181) (1244:1244:1244)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (920:920:920) (973:973:973)) + (PORT datab (1342:1342:1342) (1392:1392:1392)) + (PORT datac (326:326:326) (353:353:353)) + (PORT datad (1427:1427:1427) (1449:1449:1449)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (656:656:656) (678:678:678)) + (PORT datac (928:928:928) (941:941:941)) + (PORT datad (180:180:180) (211:211:211)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (914:914:914)) + (PORT datab (1416:1416:1416) (1546:1546:1546)) + (PORT datac (565:565:565) (575:575:575)) + (PORT datad (936:936:936) (1040:1040:1040)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) + (DELAY + (ABSOLUTE + (PORT dataa (1341:1341:1341) (1375:1375:1375)) + (PORT datab (1855:1855:1855) (2010:2010:2010)) + (PORT datac (1899:1899:1899) (2062:2062:2062)) + (PORT datad (1056:1056:1056) (1088:1088:1088)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (294:294:294)) + (PORT datab (908:908:908) (935:935:935)) + (PORT datac (1721:1721:1721) (1807:1807:1807)) + (PORT datad (644:644:644) (655:655:655)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1030:1030:1030) (1022:1022:1022)) + (PORT datab (1458:1458:1458) (1479:1479:1479)) + (PORT datac (1863:1863:1863) (1883:1883:1883)) + (PORT datad (891:891:891) (942:942:942)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) + (DELAY + (ABSOLUTE + (PORT datab (899:899:899) (963:963:963)) + (PORT datac (1275:1275:1275) (1353:1353:1353)) + (PORT datad (819:819:819) (820:820:820)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (961:961:961) (1011:1011:1011)) + (PORT datab (1539:1539:1539) (1661:1661:1661)) + (PORT datac (2217:2217:2217) (2294:2294:2294)) + (PORT datad (1527:1527:1527) (1620:1620:1620)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (950:950:950) (1002:1002:1002)) + (PORT datab (1222:1222:1222) (1268:1268:1268)) + (PORT datac (825:825:825) (834:834:834)) + (PORT datad (586:586:586) (604:604:604)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (1191:1191:1191) (1202:1202:1202)) + (PORT datac (550:550:550) (570:570:570)) + (PORT datad (623:623:623) (657:657:657)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1148:1148:1148) (1198:1198:1198)) + (PORT datab (1473:1473:1473) (1535:1535:1535)) + (PORT datac (1063:1063:1063) (1084:1084:1084)) + (PORT datad (1433:1433:1433) (1485:1485:1485)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) + (DELAY + (ABSOLUTE + (PORT datab (349:349:349) (382:382:382)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (842:842:842) (885:885:885)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (404:404:404) (433:433:433)) + (PORT datab (229:229:229) (278:278:278)) + (PORT datac (1189:1189:1189) (1253:1253:1253)) + (PORT datad (646:646:646) (683:683:683)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (875:875:875)) + (PORT datab (1717:1717:1717) (1789:1789:1789)) + (PORT datad (1811:1811:1811) (1901:1901:1901)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (753:753:753) (846:846:846)) + (PORT datab (887:887:887) (908:908:908)) + (PORT datad (1196:1196:1196) (1223:1223:1223)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de2) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1591:1591:1591) (1568:1568:1568)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (750:750:750) (841:841:841)) + (PORT datab (248:248:248) (331:331:331)) + (PORT datac (787:787:787) (792:792:792)) + (PORT datad (197:197:197) (232:232:232)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (288:288:288)) + (PORT datac (1412:1412:1412) (1417:1417:1417)) + (PORT datad (1852:1852:1852) (1892:1892:1892)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) + (DELAY + (ABSOLUTE + (PORT dataa (236:236:236) (287:287:287)) + (PORT datac (1407:1407:1407) (1415:1415:1415)) + (PORT datad (1854:1854:1854) (1894:1894:1894)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (991:991:991) (1026:1026:1026)) + (PORT ena (1426:1426:1426) (1409:1409:1409)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) + (DELAY + (ABSOLUTE + (PORT datab (1717:1717:1717) (1793:1793:1793)) + (PORT datac (821:821:821) (841:841:841)) + (PORT datad (1809:1809:1809) (1899:1899:1899)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (994:994:994) (1029:1029:1029)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (319:319:319)) + (PORT datab (1080:1080:1080) (1115:1115:1115)) + (PORT datad (360:360:360) (421:421:421)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1479:1479:1479) (1540:1540:1540)) + (PORT datab (1114:1114:1114) (1149:1149:1149)) + (PORT datac (926:926:926) (1002:1002:1002)) + (PORT datad (579:579:579) (597:597:597)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (404:404:404) (437:437:437)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (204:204:204) (249:249:249)) + (PORT datad (1311:1311:1311) (1345:1345:1345)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37npla28M3T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (2034:2034:2034) (2206:2206:2206)) + (PORT datab (1368:1368:1368) (1522:1522:1522)) + (PORT datac (1094:1094:1094) (1159:1159:1159)) + (PORT datad (902:902:902) (911:911:911)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) + (DELAY + (ABSOLUTE + (PORT dataa (959:959:959) (1003:1003:1003)) + (PORT datab (1101:1101:1101) (1135:1135:1135)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (876:876:876) (901:901:901)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1199:1199:1199)) + (PORT datab (961:961:961) (1031:1031:1031)) + (PORT datac (1199:1199:1199) (1282:1282:1282)) + (PORT datad (2867:2867:2867) (2961:2961:2961)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (1363:1363:1363) (1378:1378:1378)) + (PORT datad (644:644:644) (658:658:658)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (2294:2294:2294) (2473:2473:2473)) + (PORT datab (1742:1742:1742) (1828:1828:1828)) + (PORT datac (1441:1441:1441) (1490:1490:1490)) + (PORT datad (1101:1101:1101) (1143:1143:1143)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1106:1106:1106) (1146:1146:1146)) + (PORT datab (1219:1219:1219) (1250:1250:1250)) + (PORT datac (1199:1199:1199) (1241:1241:1241)) + (PORT datad (2219:2219:2219) (2243:2243:2243)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1166:1166:1166) (1207:1207:1207)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (838:838:838) (886:886:886)) + (PORT datad (2017:2017:2017) (2045:2045:2045)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1213:1213:1213) (1272:1272:1272)) + (PORT datab (1362:1362:1362) (1402:1402:1402)) + (PORT datac (892:892:892) (931:931:931)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1263:1263:1263) (1355:1355:1355)) + (PORT datad (870:870:870) (922:922:922)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (986:986:986)) + (PORT datab (653:653:653) (692:692:692)) + (PORT datac (1951:1951:1951) (2031:2031:2031)) + (PORT datad (1598:1598:1598) (1743:1743:1743)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (975:975:975)) + (PORT datab (978:978:978) (1029:1029:1029)) + (PORT datac (1362:1362:1362) (1399:1399:1399)) + (PORT datad (597:597:597) (611:611:611)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1152:1152:1152) (1210:1210:1210)) + (PORT datab (654:654:654) (692:692:692)) + (PORT datac (923:923:923) (937:937:937)) + (PORT datad (855:855:855) (865:865:865)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (246:246:246) (301:301:301)) + (PORT datab (928:928:928) (974:974:974)) + (PORT datac (1453:1453:1453) (1529:1529:1529)) + (PORT datad (845:845:845) (857:857:857)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (574:574:574) (585:585:585)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (672:672:672) (720:720:720)) + (PORT datab (1610:1610:1610) (1651:1651:1651)) + (PORT datac (1280:1280:1280) (1319:1319:1319)) + (PORT datad (891:891:891) (939:939:939)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (634:634:634)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (614:614:614) (636:636:636)) + (PORT datad (913:913:913) (950:950:950)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (386:386:386)) + (PORT datab (1199:1199:1199) (1267:1267:1267)) + (PORT datac (1595:1595:1595) (1618:1618:1618)) + (PORT datad (972:972:972) (1026:1026:1026)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (622:622:622) (668:668:668)) + (PORT datad (869:869:869) (889:889:889)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1237:1237:1237) (1286:1286:1286)) + (PORT datab (1475:1475:1475) (1512:1512:1512)) + (PORT datac (1132:1132:1132) (1166:1166:1166)) + (PORT datad (1185:1185:1185) (1228:1228:1228)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (381:381:381)) + (PORT datab (1367:1367:1367) (1378:1378:1378)) + (PORT datac (1077:1077:1077) (1101:1101:1101)) + (PORT datad (1342:1342:1342) (1364:1364:1364)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (680:680:680) (741:741:741)) + (PORT datab (919:919:919) (951:951:951)) + (PORT datad (1175:1175:1175) (1224:1224:1224)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~41) + (DELAY + (ABSOLUTE + (PORT dataa (2212:2212:2212) (2402:2402:2402)) + (PORT datab (1581:1581:1581) (1722:1722:1722)) + (PORT datac (1487:1487:1487) (1611:1611:1611)) + (PORT datad (861:861:861) (890:890:890)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1794:1794:1794) (1871:1871:1871)) + (PORT datab (1184:1184:1184) (1250:1250:1250)) + (PORT datac (1904:1904:1904) (1967:1967:1967)) + (PORT datad (1103:1103:1103) (1118:1118:1118)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (401:401:401)) + (PORT datab (641:641:641) (670:670:670)) + (PORT datac (635:635:635) (656:656:656)) + (PORT datad (592:592:592) (611:611:611)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1106:1106:1106) (1171:1171:1171)) + (PORT datab (882:882:882) (919:919:919)) + (PORT datac (1764:1764:1764) (1841:1841:1841)) + (PORT datad (1133:1133:1133) (1176:1176:1176)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (957:957:957) (1028:1028:1028)) + (PORT datab (890:890:890) (914:914:914)) + (PORT datac (933:933:933) (977:977:977)) + (PORT datad (1405:1405:1405) (1453:1453:1453)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (269:269:269)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1187:1187:1187) (1232:1232:1232)) + (PORT datad (616:616:616) (660:660:660)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) + (DELAY + (ABSOLUTE + (PORT dataa (1180:1180:1180) (1278:1278:1278)) + (PORT datab (971:971:971) (1028:1028:1028)) + (PORT datac (871:871:871) (935:935:935)) + (PORT datad (1211:1211:1211) (1261:1261:1261)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) + (DELAY + (ABSOLUTE + (PORT datab (229:229:229) (271:271:271)) + (PORT datac (605:605:605) (631:631:631)) + (PORT datad (216:216:216) (242:242:242)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) + (DELAY + (ABSOLUTE + (PORT dataa (1244:1244:1244) (1332:1332:1332)) + (PORT datab (983:983:983) (1057:1057:1057)) + (PORT datac (644:644:644) (684:684:684)) + (PORT datad (1355:1355:1355) (1453:1453:1453)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (971:971:971)) + (PORT datab (1396:1396:1396) (1491:1491:1491)) + (PORT datac (646:646:646) (684:684:684)) + (PORT datad (359:359:359) (387:387:387)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal61\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1912:1912:1912) (1997:1997:1997)) + (PORT datab (1642:1642:1642) (1792:1792:1792)) + (PORT datac (607:607:607) (647:647:647)) + (PORT datad (1742:1742:1742) (1827:1827:1827)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1111:1111:1111) (1149:1149:1149)) + (PORT datab (933:933:933) (967:967:967)) + (PORT datac (2220:2220:2220) (2323:2323:2323)) + (PORT datad (1600:1600:1600) (1743:1743:1743)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1322:1322:1322) (1383:1383:1383)) + (PORT datab (934:934:934) (970:970:970)) + (PORT datac (2216:2216:2216) (2296:2296:2296)) + (PORT datad (1503:1503:1503) (1626:1626:1626)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~12) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1067:1067:1067)) + (PORT datab (877:877:877) (898:898:898)) + (PORT datac (210:210:210) (250:250:250)) + (PORT datad (202:202:202) (229:229:229)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (699:699:699)) + (PORT datab (1206:1206:1206) (1268:1268:1268)) + (PORT datac (1250:1250:1250) (1284:1284:1284)) + (PORT datad (568:568:568) (578:578:578)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1003:1003:1003) (1039:1039:1039)) + (PORT datab (1167:1167:1167) (1188:1188:1188)) + (PORT datac (1404:1404:1404) (1438:1438:1438)) + (PORT datad (912:912:912) (940:940:940)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (677:677:677)) + (PORT datab (921:921:921) (977:977:977)) + (PORT datac (1473:1473:1473) (1537:1537:1537)) + (PORT datad (1145:1145:1145) (1179:1179:1179)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (933:933:933)) + (PORT datab (1131:1131:1131) (1170:1170:1170)) + (PORT datac (367:367:367) (395:395:395)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1210:1210:1210) (1285:1285:1285)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (186:186:186) (225:225:225)) + (PORT datad (2031:2031:2031) (2148:2148:2148)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) + (DELAY + (ABSOLUTE + (PORT datab (237:237:237) (281:281:281)) + (PORT datac (208:208:208) (249:249:249)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) + (DELAY + (ABSOLUTE + (PORT dataa (3682:3682:3682) (3765:3765:3765)) + (PORT datab (960:960:960) (1060:1060:1060)) + (PORT datac (1232:1232:1232) (1308:1308:1308)) + (PORT datad (669:669:669) (723:723:723)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1998:1998:1998) (2157:2157:2157)) + (PORT datab (1471:1471:1471) (1519:1519:1519)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (1320:1320:1320) (1494:1494:1494)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (722:722:722) (790:790:790)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (1592:1592:1592) (1634:1634:1634)) + (PORT datad (1467:1467:1467) (1572:1572:1572)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1102:1102:1102)) + (PORT datab (786:786:786) (892:892:892)) + (PORT datac (1471:1471:1471) (1536:1536:1536)) + (PORT datad (633:633:633) (692:692:692)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2044:2044:2044) (2134:2134:2134)) + (PORT datab (1124:1124:1124) (1155:1155:1155)) + (PORT datac (860:860:860) (892:892:892)) + (PORT datad (666:666:666) (722:722:722)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~39) + (DELAY + (ABSOLUTE + (PORT dataa (983:983:983) (1100:1100:1100)) + (PORT datab (759:759:759) (866:866:866)) + (PORT datac (1473:1473:1473) (1536:1536:1536)) + (PORT datad (893:893:893) (939:939:939)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (1473:1473:1473) (1522:1522:1522)) + (PORT datac (1014:1014:1014) (1048:1048:1048)) + (PORT datad (607:607:607) (642:642:642)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) + (DELAY + (ABSOLUTE + (PORT dataa (963:963:963) (997:997:997)) + (PORT datab (1257:1257:1257) (1285:1285:1285)) + (PORT datac (177:177:177) (214:214:214)) + (PORT datad (867:867:867) (902:902:902)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1728:1728:1728) (1837:1837:1837)) + (PORT datac (1359:1359:1359) (1427:1427:1427)) + (PORT datad (1691:1691:1691) (1791:1791:1791)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) + (DELAY + (ABSOLUTE + (PORT dataa (625:625:625) (649:649:649)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (1066:1066:1066) (1088:1088:1088)) + (PORT datad (841:841:841) (877:877:877)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (672:672:672)) + (PORT datab (1188:1188:1188) (1223:1223:1223)) + (PORT datac (506:506:506) (518:518:518)) + (PORT datad (190:190:190) (222:222:222)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) + (DELAY + (ABSOLUTE + (PORT dataa (957:957:957) (1055:1055:1055)) + (PORT datab (1495:1495:1495) (1572:1572:1572)) + (PORT datac (190:190:190) (232:232:232)) + (PORT datad (205:205:205) (242:242:242)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1404:1404:1404) (1572:1572:1572)) + (PORT datac (1211:1211:1211) (1292:1292:1292)) + (PORT datad (1320:1320:1320) (1484:1484:1484)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1404:1404:1404) (1567:1567:1567)) + (PORT datab (1663:1663:1663) (1731:1731:1731)) + (PORT datac (1737:1737:1737) (1850:1850:1850)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1403:1403:1403) (1571:1571:1571)) + (PORT datab (2575:2575:2575) (2767:2767:2767)) + (PORT datac (1204:1204:1204) (1249:1249:1249)) + (PORT datad (887:887:887) (915:915:915)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1241:1241:1241) (1265:1265:1265)) + (PORT datab (618:618:618) (643:643:643)) + (PORT datac (209:209:209) (250:250:250)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1682:1682:1682) (1783:1783:1783)) + (PORT datab (2598:2598:2598) (2784:2784:2784)) + (PORT datac (1652:1652:1652) (1819:1819:1819)) + (PORT datad (1573:1573:1573) (1595:1595:1595)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1265:1265:1265) (1319:1319:1319)) + (PORT datab (1090:1090:1090) (1145:1145:1145)) + (PORT datac (1586:1586:1586) (1738:1738:1738)) + (PORT datad (1474:1474:1474) (1508:1508:1508)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~17) + (DELAY + (ABSOLUTE + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (1089:1089:1089) (1133:1133:1133)) + (PORT datad (218:218:218) (256:256:256)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1475:1475:1475) (1530:1530:1530)) + (PORT datab (1552:1552:1552) (1583:1583:1583)) + (PORT datac (1503:1503:1503) (1583:1583:1583)) + (PORT datad (1969:1969:1969) (2022:2022:2022)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (982:982:982)) + (PORT datab (685:685:685) (707:707:707)) + (PORT datac (623:623:623) (648:648:648)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (256:256:256)) + (PORT datab (648:648:648) (674:674:674)) + (PORT datac (902:902:902) (952:952:952)) + (PORT datad (923:923:923) (972:972:972)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) + (DELAY + (ABSOLUTE + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (1346:1346:1346) (1374:1374:1374)) + (PORT datad (825:825:825) (853:853:853)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~19) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (907:907:907)) + (PORT datab (1078:1078:1078) (1132:1132:1132)) + (PORT datac (515:515:515) (534:534:534)) + (PORT datad (522:522:522) (533:533:533)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1320:1320:1320) (1381:1381:1381)) + (PORT datab (2246:2246:2246) (2335:2335:2335)) + (PORT datac (1395:1395:1395) (1531:1531:1531)) + (PORT datad (908:908:908) (933:933:933)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1222:1222:1222)) + (PORT datab (1197:1197:1197) (1273:1273:1273)) + (PORT datac (877:877:877) (942:942:942)) + (PORT datad (1209:1209:1209) (1259:1259:1259)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (986:986:986)) + (PORT datab (935:935:935) (974:974:974)) + (PORT datac (1208:1208:1208) (1267:1267:1267)) + (PORT datad (580:580:580) (609:609:609)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1309:1309:1309) (1367:1367:1367)) + (PORT datab (1760:1760:1760) (1823:1823:1823)) + (PORT datac (780:780:780) (832:832:832)) + (PORT datad (2119:2119:2119) (2113:2113:2113)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1130:1130:1130) (1164:1164:1164)) + (PORT datab (1248:1248:1248) (1297:1297:1297)) + (PORT datad (900:900:900) (967:967:967)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (957:957:957) (1008:1008:1008)) + (PORT datab (667:667:667) (689:689:689)) + (PORT datac (844:844:844) (882:882:882)) + (PORT datad (865:865:865) (875:875:875)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) + (DELAY + (ABSOLUTE + (PORT datab (1146:1146:1146) (1171:1171:1171)) + (PORT datac (202:202:202) (240:240:240)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (705:705:705)) + (PORT datab (344:344:344) (376:376:376)) + (PORT datac (1158:1158:1158) (1183:1183:1183)) + (PORT datad (942:942:942) (987:987:987)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1122:1122:1122) (1155:1155:1155)) + (PORT datab (660:660:660) (713:713:713)) + (PORT datac (904:904:904) (922:922:922)) + (PORT datad (820:820:820) (840:840:840)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (266:266:266)) + (PORT datab (240:240:240) (286:286:286)) + (PORT datac (211:211:211) (254:254:254)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1301:1301:1301) (1320:1320:1320)) + (PORT datab (2020:2020:2020) (2143:2143:2143)) + (PORT datac (1955:1955:1955) (2058:2058:2058)) + (PORT datad (1295:1295:1295) (1376:1376:1376)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1214:1214:1214) (1262:1262:1262)) + (PORT datab (1197:1197:1197) (1269:1269:1269)) + (PORT datac (1021:1021:1021) (1050:1050:1050)) + (PORT datad (315:315:315) (333:333:333)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~18) + (DELAY + (ABSOLUTE + (PORT dataa (2144:2144:2144) (2265:2265:2265)) + (PORT datab (1690:1690:1690) (1867:1867:1867)) + (PORT datac (604:604:604) (619:619:619)) + (PORT datad (2025:2025:2025) (2071:2071:2071)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (2076:2076:2076) (2173:2173:2173)) + (PORT datab (1169:1169:1169) (1260:1260:1260)) + (PORT datac (1442:1442:1442) (1488:1488:1488)) + (PORT datad (1368:1368:1368) (1396:1396:1396)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (942:942:942)) + (PORT datab (677:677:677) (721:721:721)) + (PORT datac (1761:1761:1761) (1841:1841:1841)) + (PORT datad (1762:1762:1762) (1819:1819:1819)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1433:1433:1433) (1482:1482:1482)) + (PORT datab (910:910:910) (937:937:937)) + (PORT datac (1440:1440:1440) (1519:1519:1519)) + (PORT datad (838:838:838) (870:870:870)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (961:961:961)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (619:619:619) (672:672:672)) + (PORT datad (598:598:598) (648:648:648)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (911:911:911)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (812:812:812) (847:847:847)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (693:693:693)) + (PORT datab (661:661:661) (693:693:693)) + (PORT datac (634:634:634) (677:677:677)) + (PORT datad (348:348:348) (370:370:370)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1228:1228:1228) (1319:1319:1319)) + (PORT datab (1236:1236:1236) (1274:1274:1274)) + (PORT datac (625:625:625) (679:679:679)) + (PORT datad (1191:1191:1191) (1247:1247:1247)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (950:950:950) (979:979:979)) + (PORT datad (624:624:624) (649:649:649)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~17) + (DELAY + (ABSOLUTE + (PORT dataa (2353:2353:2353) (2461:2461:2461)) + (PORT datab (976:976:976) (1005:1005:1005)) + (PORT datac (1088:1088:1088) (1104:1104:1104)) + (PORT datad (1772:1772:1772) (1890:1890:1890)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (907:907:907) (918:918:918)) + (PORT datac (1188:1188:1188) (1230:1230:1230)) + (PORT datad (1430:1430:1430) (1500:1500:1500)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datac (1693:1693:1693) (1727:1727:1727)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (672:672:672)) + (PORT datab (578:578:578) (605:605:605)) + (PORT datac (1476:1476:1476) (1572:1572:1572)) + (PORT datad (1639:1639:1639) (1701:1701:1701)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1271:1271:1271) (1315:1315:1315)) + (PORT datab (1165:1165:1165) (1196:1196:1196)) + (PORT datac (912:912:912) (969:969:969)) + (PORT datad (314:314:314) (333:333:333)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (256:256:256)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (1047:1047:1047) (1053:1053:1053)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1758:1758:1758) (1900:1900:1900)) + (PORT datab (902:902:902) (950:950:950)) + (PORT datac (1212:1212:1212) (1261:1261:1261)) + (PORT datad (2454:2454:2454) (2652:2652:2652)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) + (DELAY + (ABSOLUTE + (PORT datab (664:664:664) (686:686:686)) + (PORT datac (185:185:185) (223:223:223)) + (PORT datad (190:190:190) (222:222:222)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1193:1193:1193) (1290:1290:1290)) + (PORT datab (1597:1597:1597) (1747:1747:1747)) + (PORT datac (1512:1512:1512) (1646:1646:1646)) + (PORT datad (1772:1772:1772) (1860:1860:1860)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (2076:2076:2076) (2171:2171:2171)) + (PORT datab (1273:1273:1273) (1341:1341:1341)) + (PORT datac (1497:1497:1497) (1578:1578:1578)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (332:332:332)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (420:420:420)) + (PORT datab (1273:1273:1273) (1342:1342:1342)) + (PORT datac (1152:1152:1152) (1193:1193:1193)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (269:269:269)) + (PORT datab (601:601:601) (645:645:645)) + (PORT datac (1369:1369:1369) (1405:1405:1405)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (725:725:725)) + (PORT datab (952:952:952) (1009:1009:1009)) + (PORT datac (1500:1500:1500) (1582:1582:1582)) + (PORT datad (1167:1167:1167) (1248:1248:1248)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) + (DELAY + (ABSOLUTE + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (1458:1458:1458) (1477:1477:1477)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1302:1302:1302) (1377:1377:1377)) + (PORT datab (1178:1178:1178) (1247:1247:1247)) + (PORT datac (1503:1503:1503) (1562:1562:1562)) + (PORT datad (642:642:642) (693:693:693)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (255:255:255)) + (PORT datab (1217:1217:1217) (1266:1266:1266)) + (PORT datac (1500:1500:1500) (1564:1564:1564)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1389:1389:1389) (1465:1465:1465)) + (PORT datab (1685:1685:1685) (1852:1852:1852)) + (PORT datac (982:982:982) (980:980:980)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1140:1140:1140) (1183:1183:1183)) + (PORT datab (662:662:662) (713:713:713)) + (PORT datac (627:627:627) (681:681:681)) + (PORT datad (640:640:640) (676:676:676)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1655:1655:1655) (1726:1726:1726)) + (PORT datab (1375:1375:1375) (1391:1391:1391)) + (PORT datac (1118:1118:1118) (1174:1174:1174)) + (PORT datad (624:624:624) (643:643:643)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1183:1183:1183) (1210:1210:1210)) + (PORT datab (1380:1380:1380) (1398:1398:1398)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (257:257:257)) + (PORT datab (663:663:663) (690:690:690)) + (PORT datac (188:188:188) (229:229:229)) + (PORT datad (187:187:187) (218:218:218)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (384:384:384)) + (PORT datab (811:811:811) (819:819:819)) + (PORT datac (1421:1421:1421) (1484:1484:1484)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1645:1645:1645) (1680:1680:1680)) + (PORT datab (1246:1246:1246) (1316:1316:1316)) + (PORT datac (1499:1499:1499) (1579:1579:1579)) + (PORT datad (2049:2049:2049) (2131:2131:2131)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1799:1799:1799) (1901:1901:1901)) + (PORT datab (1594:1594:1594) (1745:1745:1745)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1620:1620:1620) (1635:1635:1635)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1533:1533:1533) (1601:1601:1601)) + (PORT datab (1750:1750:1750) (1829:1829:1829)) + (PORT datac (1522:1522:1522) (1600:1600:1600)) + (PORT datad (337:337:337) (356:356:356)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (332:332:332)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) + (DELAY + (ABSOLUTE + (PORT dataa (680:680:680) (761:761:761)) + (PORT datab (915:915:915) (968:968:968)) + (PORT datac (1718:1718:1718) (1796:1796:1796)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1531:1531:1531) (1599:1599:1599)) + (PORT datab (1097:1097:1097) (1130:1130:1130)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1896:1896:1896) (1969:1969:1969)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (761:761:761)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1068:1068:1068) (1100:1100:1100)) + (PORT datad (1691:1691:1691) (1730:1730:1730)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1460:1460:1460) (1483:1483:1483)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (631:631:631) (655:655:655)) + (PORT datad (1901:1901:1901) (1974:1974:1974)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (690:690:690)) + (PORT datab (610:610:610) (635:635:635)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1434:1434:1434) (1482:1482:1482)) + (PORT datab (979:979:979) (1023:1023:1023)) + (PORT datac (1196:1196:1196) (1241:1241:1241)) + (PORT datad (1188:1188:1188) (1214:1214:1214)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1171:1171:1171) (1204:1204:1204)) + (PORT datab (1148:1148:1148) (1184:1184:1184)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1749:1749:1749) (1821:1821:1821)) + (PORT datab (1396:1396:1396) (1445:1445:1445)) + (PORT datac (1206:1206:1206) (1248:1248:1248)) + (PORT datad (1501:1501:1501) (1578:1578:1578)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1747:1747:1747) (1821:1821:1821)) + (PORT datab (1398:1398:1398) (1449:1449:1449)) + (PORT datac (1474:1474:1474) (1513:1513:1513)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1260:1260:1260) (1306:1306:1306)) + (PORT datab (1543:1543:1543) (1626:1626:1626)) + (PORT datac (912:912:912) (982:982:982)) + (PORT datad (959:959:959) (1003:1003:1003)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1181:1181:1181) (1240:1240:1240)) + (PORT datab (994:994:994) (1040:1040:1040)) + (PORT datac (909:909:909) (977:977:977)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (984:984:984)) + (PORT datab (1911:1911:1911) (2074:2074:2074)) + (PORT datac (1899:1899:1899) (2060:2060:2060)) + (PORT datad (1058:1058:1058) (1086:1086:1086)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1235:1235:1235) (1286:1286:1286)) + (PORT datab (1215:1215:1215) (1233:1233:1233)) + (PORT datac (833:833:833) (881:881:881)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (624:624:624) (649:649:649)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (926:926:926)) + (PORT datab (875:875:875) (918:918:918)) + (PORT datac (635:635:635) (664:664:664)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2896:2896:2896) (2954:2954:2954)) + (PORT datab (1052:1052:1052) (1116:1116:1116)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (2591:2591:2591) (2649:2649:2649)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1270:1270:1270)) + (PORT datab (1101:1101:1101) (1135:1135:1135)) + (PORT datac (1363:1363:1363) (1380:1380:1380)) + (PORT datad (1191:1191:1191) (1245:1245:1245)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1384:1384:1384) (1464:1464:1464)) + (PORT datab (628:628:628) (673:673:673)) + (PORT datac (611:611:611) (637:637:637)) + (PORT datad (697:697:697) (744:744:744)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (853:853:853) (883:883:883)) + (PORT datab (877:877:877) (946:946:946)) + (PORT datac (2034:2034:2034) (2072:2072:2072)) + (PORT datad (821:821:821) (867:867:867)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2352:2352:2352) (2460:2460:2460)) + (PORT datab (979:979:979) (1005:1005:1005)) + (PORT datac (1863:1863:1863) (1892:1892:1892)) + (PORT datad (1775:1775:1775) (1890:1890:1890)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) + (DELAY + (ABSOLUTE + (PORT datac (1179:1179:1179) (1246:1246:1246)) + (PORT datad (1693:1693:1693) (1817:1817:1817)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (2042:2042:2042) (2132:2132:2132)) + (PORT datab (661:661:661) (679:679:679)) + (PORT datac (861:861:861) (893:893:893)) + (PORT datad (666:666:666) (723:723:723)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (265:265:265)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (859:859:859) (874:874:874)) + (PORT datad (340:340:340) (363:363:363)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1882:1882:1882) (2069:2069:2069)) + (PORT datab (1503:1503:1503) (1598:1598:1598)) + (PORT datac (1200:1200:1200) (1277:1277:1277)) + (PORT datad (613:613:613) (652:652:652)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (591:591:591) (609:609:609)) + (PORT datad (832:832:832) (884:884:884)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1622:1622:1622) (1656:1656:1656)) + (PORT datab (1011:1011:1011) (1122:1122:1122)) + (PORT datac (2246:2246:2246) (2401:2401:2401)) + (PORT datad (640:640:640) (657:657:657)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (399:399:399)) + (PORT datab (886:886:886) (926:926:926)) + (PORT datac (2213:2213:2213) (2293:2293:2293)) + (PORT datad (1158:1158:1158) (1220:1220:1220)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (649:649:649)) + (PORT datab (610:610:610) (643:643:643)) + (PORT datac (1089:1089:1089) (1103:1103:1103)) + (PORT datad (1426:1426:1426) (1497:1497:1497)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (1047:1047:1047)) + (PORT datab (1328:1328:1328) (1357:1357:1357)) + (PORT datac (1395:1395:1395) (1452:1452:1452)) + (PORT datad (180:180:180) (211:211:211)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1158:1158:1158) (1195:1195:1195)) + (PORT datab (908:908:908) (926:926:926)) + (PORT datac (616:616:616) (647:647:647)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1485:1485:1485) (1546:1546:1546)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (316:316:316) (335:335:335)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (953:953:953)) + (PORT datab (214:214:214) (257:257:257)) + (PORT datac (606:606:606) (625:625:625)) + (PORT datad (1433:1433:1433) (1446:1446:1446)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (955:955:955)) + (PORT datab (968:968:968) (1012:1012:1012)) + (PORT datac (766:766:766) (778:778:778)) + (PORT datad (180:180:180) (210:210:210)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (661:661:661)) + (PORT datab (1887:1887:1887) (1914:1914:1914)) + (PORT datac (951:951:951) (996:996:996)) + (PORT datad (1256:1256:1256) (1314:1314:1314)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (198:198:198) (235:235:235)) + (PORT datac (574:574:574) (617:617:617)) + (PORT datad (1077:1077:1077) (1104:1104:1104)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (396:396:396)) + (PORT datab (632:632:632) (663:663:663)) + (PORT datac (612:612:612) (624:624:624)) + (PORT datad (624:624:624) (639:639:639)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (950:950:950)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (1118:1118:1118) (1174:1174:1174)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (904:904:904)) + (PORT datab (2215:2215:2215) (2381:2381:2381)) + (PORT datac (1232:1232:1232) (1373:1373:1373)) + (PORT datad (2798:2798:2798) (2994:2994:2994)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (638:638:638)) + (PORT datab (687:687:687) (717:717:717)) + (PORT datac (934:934:934) (966:966:966)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (631:631:631)) + (PORT datac (895:895:895) (905:905:905)) + (PORT datad (841:841:841) (853:853:853)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1988:1988:1988) (2068:2068:2068)) + (PORT datab (363:363:363) (394:394:394)) + (PORT datad (869:869:869) (931:931:931)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_af) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1589:1589:1589) (1566:1566:1566)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1426:1426:1426) (1475:1475:1475)) + (PORT datab (1193:1193:1193) (1241:1241:1241)) + (PORT datac (846:846:846) (891:891:891)) + (PORT datad (1379:1379:1379) (1380:1380:1380)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) + (DELAY + (ABSOLUTE + (PORT dataa (1682:1682:1682) (1803:1803:1803)) + (PORT datac (632:632:632) (678:678:678)) + (PORT datad (1446:1446:1446) (1513:1513:1513)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1183:1183:1183) (1262:1262:1262)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1485:1485:1485) (1554:1554:1554)) + (PORT datab (656:656:656) (705:705:705)) + (PORT datad (1630:1630:1630) (1739:1739:1739)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) + (DELAY + (ABSOLUTE + (PORT dataa (1285:1285:1285) (1362:1362:1362)) + (PORT datab (897:897:897) (934:934:934)) + (PORT datac (1431:1431:1431) (1496:1496:1496)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) + (DELAY + (ABSOLUTE + (PORT datab (1464:1464:1464) (1531:1531:1531)) + (PORT datac (876:876:876) (924:924:924)) + (PORT datad (1249:1249:1249) (1317:1317:1317)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1014:1014:1014) (1056:1056:1056)) + (PORT ena (1485:1485:1485) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) + (DELAY + (ABSOLUTE + (PORT dataa (1300:1300:1300) (1381:1381:1381)) + (PORT datab (894:894:894) (929:929:929)) + (PORT datac (1433:1433:1433) (1499:1499:1499)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1016:1016:1016) (1059:1059:1059)) + (PORT ena (1475:1475:1475) (1479:1479:1479)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) + (DELAY + (ABSOLUTE + (PORT datab (1468:1468:1468) (1530:1530:1530)) + (PORT datac (879:879:879) (925:925:925)) + (PORT datad (1241:1241:1241) (1311:1311:1311)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (977:977:977)) + (PORT datab (243:243:243) (326:326:326)) + (PORT datad (893:893:893) (937:937:937)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (751:751:751) (842:842:842)) + (PORT datab (249:249:249) (332:332:332)) + (PORT datac (787:787:787) (792:792:792)) + (PORT datad (199:199:199) (237:237:237)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT datab (1462:1462:1462) (1531:1531:1531)) + (PORT datac (860:860:860) (902:902:902)) + (PORT datad (1246:1246:1246) (1318:1318:1318)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) + (DELAY + (ABSOLUTE + (PORT dataa (747:747:747) (841:841:841)) + (PORT datab (223:223:223) (271:271:271)) + (PORT datac (787:787:787) (791:791:791)) + (PORT datad (224:224:224) (296:296:296)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) + (DELAY + (ABSOLUTE + (PORT datab (1466:1466:1466) (1528:1528:1528)) + (PORT datac (844:844:844) (888:888:888)) + (PORT datad (1241:1241:1241) (1313:1313:1313)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) + (DELAY + (ABSOLUTE + (PORT datab (1468:1468:1468) (1532:1532:1532)) + (PORT datac (861:861:861) (900:900:900)) + (PORT datad (1254:1254:1254) (1327:1327:1327)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1423:1423:1423) (1482:1482:1482)) + (PORT ena (1546:1546:1546) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) + (DELAY + (ABSOLUTE + (PORT datab (1465:1465:1465) (1532:1532:1532)) + (PORT datac (841:841:841) (888:888:888)) + (PORT datad (1245:1245:1245) (1318:1318:1318)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1421:1421:1421) (1478:1478:1478)) + (PORT ena (1446:1446:1446) (1455:1455:1455)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (999:999:999) (1057:1057:1057)) + (PORT datab (966:966:966) (1013:1013:1013)) + (PORT datad (357:357:357) (414:414:414)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (854:854:854) (911:911:911)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1512:1512:1512) (1527:1527:1527)) + (PORT datab (1198:1198:1198) (1246:1246:1246)) + (PORT datac (1748:1748:1748) (1867:1867:1867)) + (PORT datad (1449:1449:1449) (1522:1522:1522)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) + (DELAY + (ABSOLUTE + (PORT datab (1615:1615:1615) (1723:1723:1723)) + (PORT datac (1085:1085:1085) (1141:1141:1141)) + (PORT datad (346:346:346) (373:373:373)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) + (DELAY + (ABSOLUTE + (PORT datab (1612:1612:1612) (1721:1721:1721)) + (PORT datac (1083:1083:1083) (1140:1140:1140)) + (PORT datad (343:343:343) (371:371:371)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) + (DELAY + (ABSOLUTE + (PORT datab (1611:1611:1611) (1718:1718:1718)) + (PORT datad (1731:1731:1731) (1794:1794:1794)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1515:1515:1515) (1529:1529:1529)) + (PORT datab (1784:1784:1784) (1902:1902:1902)) + (PORT datac (337:337:337) (362:362:362)) + (PORT datad (1160:1160:1160) (1205:1205:1205)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1411:1411:1411) (1470:1470:1470)) + (PORT ena (1196:1196:1196) (1165:1165:1165)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) + (DELAY + (ABSOLUTE + (PORT datab (1610:1610:1610) (1716:1716:1716)) + (PORT datac (1084:1084:1084) (1136:1136:1136)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1497:1497:1497) (1513:1513:1513)) + (PORT datab (376:376:376) (408:408:408)) + (PORT datac (1753:1753:1753) (1874:1874:1874)) + (PORT datad (1153:1153:1153) (1198:1198:1198)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (473:473:473) (552:552:552)) + (PORT datab (498:498:498) (554:554:554)) + (PORT datad (627:627:627) (659:659:659)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (599:599:599) (636:636:636)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1426:1426:1426) (1476:1476:1476)) + (PORT datab (1193:1193:1193) (1241:1241:1241)) + (PORT datac (341:341:341) (367:367:367)) + (PORT datad (1380:1380:1380) (1380:1380:1380)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1476:1476:1476) (1478:1478:1478)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1514:1514:1514) (1527:1527:1527)) + (PORT datab (371:371:371) (402:402:402)) + (PORT datac (1398:1398:1398) (1441:1441:1441)) + (PORT datad (1158:1158:1158) (1204:1204:1204)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (706:706:706)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (180:180:180) (216:216:216)) + (PORT datad (208:208:208) (240:240:240)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (2055:2055:2055) (2081:2081:2081)) + (PORT datab (1404:1404:1404) (1511:1511:1511)) + (PORT datac (2090:2090:2090) (2260:2260:2260)) + (PORT datad (875:875:875) (901:901:901)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1051:1051:1051) (1073:1073:1073)) + (PORT datab (1268:1268:1268) (1350:1350:1350)) + (PORT datac (1926:1926:1926) (1930:1930:1930)) + (PORT datad (363:363:363) (385:385:385)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (276:276:276)) + (PORT datac (588:588:588) (636:636:636)) + (PORT datad (822:822:822) (847:847:847)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) + (DELAY + (ABSOLUTE + (PORT dataa (679:679:679) (721:721:721)) + (PORT datab (218:218:218) (264:264:264)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (263:263:263)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (860:860:860) (875:875:875)) + (PORT datad (642:642:642) (659:659:659)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) + (DELAY + (ABSOLUTE + (PORT dataa (964:964:964) (1041:1041:1041)) + (PORT datac (916:916:916) (968:968:968)) + (PORT datad (1214:1214:1214) (1282:1282:1282)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (950:950:950) (983:983:983)) + (PORT ena (1186:1186:1186) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) + (DELAY + (ABSOLUTE + (PORT dataa (963:963:963) (1034:1034:1034)) + (PORT datac (915:915:915) (966:966:966)) + (PORT datad (1213:1213:1213) (1277:1277:1277)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (328:328:328)) + (PORT datab (959:959:959) (999:999:999)) + (PORT datad (880:880:880) (921:921:921)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1509:1509:1509) (1526:1526:1526)) + (PORT datab (1196:1196:1196) (1249:1249:1249)) + (PORT datac (341:341:341) (369:369:369)) + (PORT datad (582:582:582) (643:643:643)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1509:1509:1509) (1526:1526:1526)) + (PORT datab (611:611:611) (683:683:683)) + (PORT datac (338:338:338) (364:364:364)) + (PORT datad (1156:1156:1156) (1205:1205:1205)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1439:1439:1439) (1498:1498:1498)) + (PORT ena (1163:1163:1163) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1506:1506:1506) (1523:1523:1523)) + (PORT datab (609:609:609) (680:680:680)) + (PORT datac (340:340:340) (366:366:366)) + (PORT datad (1150:1150:1150) (1203:1203:1203)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1444:1444:1444) (1503:1503:1503)) + (PORT ena (1213:1213:1213) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1511:1511:1511) (1527:1527:1527)) + (PORT datab (1197:1197:1197) (1246:1246:1246)) + (PORT datac (341:341:341) (368:368:368)) + (PORT datad (582:582:582) (639:639:639)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (705:705:705)) + (PORT datab (243:243:243) (326:326:326)) + (PORT datad (626:626:626) (663:663:663)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1429:1429:1429) (1476:1476:1476)) + (PORT datab (1197:1197:1197) (1247:1247:1247)) + (PORT datac (850:850:850) (893:893:893)) + (PORT datad (1383:1383:1383) (1381:1381:1381)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) + (DELAY + (ABSOLUTE + (PORT dataa (1488:1488:1488) (1561:1561:1561)) + (PORT datab (902:902:902) (929:929:929)) + (PORT datad (1637:1637:1637) (1751:1751:1751)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (1609:1609:1609) (1656:1656:1656)) + (PORT datac (887:887:887) (932:932:932)) + (PORT datad (209:209:209) (241:241:241)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1674:1674:1674) (1748:1748:1748)) + (PORT datab (392:392:392) (418:418:418)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (886:886:886) (902:902:902)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) + (DELAY + (ABSOLUTE + (PORT dataa (1486:1486:1486) (1558:1558:1558)) + (PORT datab (908:908:908) (935:935:935)) + (PORT datad (1629:1629:1629) (1743:1743:1743)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1414:1414:1414) (1474:1474:1474)) + (PORT ena (1256:1256:1256) (1255:1255:1255)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (984:984:984) (1031:1031:1031)) + (PORT datab (1291:1291:1291) (1331:1331:1331)) + (PORT datad (874:874:874) (906:906:906)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (1320:1320:1320) (1335:1335:1335)) + (PORT datac (335:335:335) (358:358:358)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (672:672:672)) + (PORT datab (555:555:555) (576:576:576)) + (PORT datac (825:825:825) (840:840:840)) + (PORT datad (1032:1032:1032) (1101:1101:1101)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (385:385:385)) + (PORT datab (1380:1380:1380) (1398:1398:1398)) + (PORT datac (1123:1123:1123) (1180:1180:1180)) + (PORT datad (622:622:622) (640:640:640)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (690:690:690) (732:732:732)) + (PORT datab (891:891:891) (930:930:930)) + (PORT datac (1215:1215:1215) (1263:1263:1263)) + (PORT datad (560:560:560) (577:577:577)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (264:264:264)) + (PORT datab (875:875:875) (893:893:893)) + (PORT datac (344:344:344) (372:372:372)) + (PORT datad (1110:1110:1110) (1122:1122:1122)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (220:220:220) (258:258:258)) + (PORT datac (615:615:615) (641:641:641)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (581:581:581) (593:593:593)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datac (195:195:195) (228:228:228)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (962:962:962)) + (PORT datab (1357:1357:1357) (1408:1408:1408)) + (PORT datac (1375:1375:1375) (1378:1378:1378)) + (PORT datad (793:793:793) (845:845:845)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (658:658:658)) + (PORT datab (1361:1361:1361) (1409:1409:1409)) + (PORT datac (412:412:412) (449:449:449)) + (PORT datad (209:209:209) (242:242:242)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1495:1495:1495) (1563:1563:1563)) + (PORT datab (841:841:841) (869:869:869)) + (PORT datac (809:809:809) (891:891:891)) + (PORT datad (837:837:837) (886:886:886)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) + (DELAY + (ABSOLUTE + (PORT dataa (964:964:964) (994:994:994)) + (PORT datab (1403:1403:1403) (1460:1460:1460)) + (PORT datac (1085:1085:1085) (1138:1138:1138)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1124:1124:1124) (1165:1165:1165)) + (PORT datab (1867:1867:1867) (1942:1942:1942)) + (PORT datac (842:842:842) (905:905:905)) + (PORT datad (626:626:626) (662:662:662)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1190:1190:1190) (1209:1209:1209)) + (PORT datab (1474:1474:1474) (1514:1514:1514)) + (PORT datac (1094:1094:1094) (1102:1102:1102)) + (PORT datad (1208:1208:1208) (1297:1297:1297)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1236:1236:1236) (1289:1289:1289)) + (PORT datab (1163:1163:1163) (1196:1196:1196)) + (PORT datac (917:917:917) (959:959:959)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) + (DELAY + (ABSOLUTE + (PORT dataa (854:854:854) (896:896:896)) + (PORT datab (814:814:814) (835:835:835)) + (PORT datac (1604:1604:1604) (1624:1624:1624)) + (PORT datad (1091:1091:1091) (1104:1104:1104)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1005:1005:1005) (1081:1081:1081)) + (PORT datab (643:643:643) (686:686:686)) + (PORT datac (880:880:880) (916:916:916)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1506:1506:1506) (1583:1583:1583)) + (PORT datab (645:645:645) (676:676:676)) + (PORT datac (924:924:924) (965:965:965)) + (PORT datad (1191:1191:1191) (1244:1244:1244)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (263:263:263)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1363:1363:1363) (1381:1381:1381)) + (PORT datad (584:584:584) (632:632:632)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1381:1381:1381) (1468:1468:1468)) + (PORT datab (376:376:376) (404:404:404)) + (PORT datac (631:631:631) (672:672:672)) + (PORT datad (695:695:695) (746:746:746)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (972:972:972) (1011:1011:1011)) + (PORT datab (845:845:845) (882:882:882)) + (PORT datac (544:544:544) (563:563:563)) + (PORT datad (1121:1121:1121) (1121:1121:1121)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1134:1134:1134) (1168:1168:1168)) + (PORT datab (927:927:927) (955:955:955)) + (PORT datac (1207:1207:1207) (1250:1250:1250)) + (PORT datad (1220:1220:1220) (1269:1269:1269)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) + (DELAY + (ABSOLUTE + (PORT datab (205:205:205) (246:246:246)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (175:175:175) (202:202:202)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1125:1125:1125) (1132:1132:1132)) + (PORT datab (613:613:613) (653:653:653)) + (PORT datac (186:186:186) (227:227:227)) + (PORT datad (836:836:836) (844:844:844)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) + (DELAY + (ABSOLUTE + (PORT datab (2020:2020:2020) (2146:2146:2146)) + (PORT datac (1954:1954:1954) (2061:2061:2061)) + (PORT datad (1620:1620:1620) (1793:1793:1793)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1338:1338:1338) (1426:1426:1426)) + (PORT datab (1201:1201:1201) (1270:1270:1270)) + (PORT datac (1175:1175:1175) (1230:1230:1230)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) + (DELAY + (ABSOLUTE + (PORT datac (842:842:842) (866:866:866)) + (PORT datad (625:625:625) (636:636:636)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (592:592:592)) + (PORT datab (387:387:387) (415:415:415)) + (PORT datac (1088:1088:1088) (1123:1123:1123)) + (PORT datad (809:809:809) (841:841:841)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_xf) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~50) + (DELAY + (ABSOLUTE + (PORT dataa (1561:1561:1561) (1660:1660:1660)) + (PORT datab (1645:1645:1645) (1688:1688:1688)) + (PORT datac (1674:1674:1674) (1745:1745:1745)) + (PORT datad (1153:1153:1153) (1190:1190:1190)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (717:717:717)) + (PORT datab (1418:1418:1418) (1466:1466:1466)) + (PORT datac (927:927:927) (1002:1002:1002)) + (PORT datad (320:320:320) (342:342:342)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (453:453:453)) + (PORT datab (381:381:381) (414:414:414)) + (PORT datac (948:948:948) (997:997:997)) + (PORT datad (902:902:902) (929:929:929)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (924:924:924)) + (PORT datab (1172:1172:1172) (1217:1217:1217)) + (PORT datad (586:586:586) (617:617:617)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (665:665:665)) + (PORT datab (400:400:400) (448:448:448)) + (PORT datac (903:903:903) (950:950:950)) + (PORT datad (1154:1154:1154) (1178:1178:1178)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1138:1138:1138) (1171:1171:1171)) + (PORT datad (1850:1850:1850) (1892:1892:1892)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1156:1156:1156) (1190:1190:1190)) + (PORT datab (1154:1154:1154) (1186:1186:1186)) + (PORT datac (1365:1365:1365) (1404:1404:1404)) + (PORT datad (1108:1108:1108) (1127:1127:1127)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (413:413:413)) + (PORT datab (1708:1708:1708) (1765:1765:1765)) + (PORT datac (1580:1580:1580) (1686:1686:1686)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) + (DELAY + (ABSOLUTE + (PORT datac (1414:1414:1414) (1421:1421:1421)) + (PORT datad (1852:1852:1852) (1893:1893:1893)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1157:1157:1157) (1191:1191:1191)) + (PORT datab (1155:1155:1155) (1186:1186:1186)) + (PORT datac (1366:1366:1366) (1405:1405:1405)) + (PORT datad (826:826:826) (842:842:842)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (681:681:681) (708:708:708)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (413:413:413)) + (PORT datab (1709:1709:1709) (1766:1766:1766)) + (PORT datac (1579:1579:1579) (1681:1681:1681)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1712:1712:1712) (1752:1752:1752)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (261:261:261) (325:325:325)) + (PORT datab (1404:1404:1404) (1519:1519:1519)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) + (DELAY + (ABSOLUTE + (PORT dataa (1297:1297:1297) (1374:1374:1374)) + (PORT datac (1019:1019:1019) (1043:1043:1043)) + (PORT datad (1368:1368:1368) (1412:1412:1412)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (1138:1138:1138) (1174:1174:1174)) + (PORT datab (371:371:371) (403:403:403)) + (PORT datad (1851:1851:1851) (1894:1894:1894)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) + (DELAY + (ABSOLUTE + (PORT dataa (1290:1290:1290) (1369:1369:1369)) + (PORT datac (1018:1018:1018) (1041:1041:1041)) + (PORT datad (1364:1364:1364) (1407:1407:1407)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1699:1699:1699) (1727:1727:1727)) + (PORT ena (1147:1147:1147) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (905:905:905) (954:954:954)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (1141:1141:1141) (1172:1172:1172)) + (PORT datab (368:368:368) (402:402:402)) + (PORT datad (1853:1853:1853) (1893:1893:1893)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1248:1248:1248) (1262:1262:1262)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (663:663:663)) + (PORT datab (940:940:940) (1000:1000:1000)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) + (DELAY + (ABSOLUTE + (PORT dataa (1281:1281:1281) (1368:1368:1368)) + (PORT datab (1005:1005:1005) (1055:1055:1055)) + (PORT datac (915:915:915) (968:968:968)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1377:1377:1377) (1394:1394:1394)) + (PORT datab (228:228:228) (270:270:270)) + (PORT datac (1112:1112:1112) (1132:1132:1132)) + (PORT datad (596:596:596) (654:654:654)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (838:838:838)) + (PORT datab (218:218:218) (257:257:257)) + (PORT datac (859:859:859) (867:867:867)) + (PORT datad (1351:1351:1351) (1364:1364:1364)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (970:970:970) (999:999:999)) + (PORT ena (1243:1243:1243) (1273:1273:1273)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1199:1199:1199) (1256:1256:1256)) + (PORT datab (676:676:676) (714:714:714)) + (PORT datad (959:959:959) (992:992:992)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) + (DELAY + (ABSOLUTE + (PORT dataa (1275:1275:1275) (1362:1362:1362)) + (PORT datab (1010:1010:1010) (1056:1056:1056)) + (PORT datac (916:916:916) (969:969:969)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (969:969:969) (1001:1001:1001)) + (PORT ena (1168:1168:1168) (1161:1161:1161)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (459:459:459)) + (PORT datab (197:197:197) (236:236:236)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1509:1509:1509) (1527:1527:1527)) + (PORT datab (1196:1196:1196) (1250:1250:1250)) + (PORT datac (1752:1752:1752) (1873:1873:1873)) + (PORT datad (543:543:543) (551:551:551)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT asdata (1136:1136:1136) (1158:1158:1158)) + (PORT ena (961:961:961) (970:970:970)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1742:1742:1742) (1856:1856:1856)) + (PORT datab (1391:1391:1391) (1393:1393:1393)) + (PORT datac (1113:1113:1113) (1130:1130:1130)) + (PORT datad (1127:1127:1127) (1128:1128:1128)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1151:1151:1151) (1170:1170:1170)) + (PORT datab (624:624:624) (692:692:692)) + (PORT datac (1345:1345:1345) (1352:1352:1352)) + (PORT datad (823:823:823) (830:830:830)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT asdata (1134:1134:1134) (1155:1155:1155)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1380:1380:1380) (1395:1395:1395)) + (PORT datab (227:227:227) (268:268:268)) + (PORT datac (1113:1113:1113) (1134:1134:1134)) + (PORT datad (597:597:597) (655:655:655)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (330:330:330)) + (PORT datab (247:247:247) (295:295:295)) + (PORT datad (211:211:211) (244:244:244)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (696:696:696)) + (PORT datab (660:660:660) (673:673:673)) + (PORT datac (762:762:762) (771:771:771)) + (PORT datad (596:596:596) (645:645:645)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) + (DELAY + (ABSOLUTE + (PORT dataa (1296:1296:1296) (1377:1377:1377)) + (PORT datac (840:840:840) (891:891:891)) + (PORT datad (1367:1367:1367) (1411:1411:1411)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) + (DELAY + (ABSOLUTE + (PORT dataa (1300:1300:1300) (1381:1381:1381)) + (PORT datac (861:861:861) (899:899:899)) + (PORT datad (1371:1371:1371) (1413:1413:1413)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT dataa (1300:1300:1300) (1380:1380:1380)) + (PORT datac (861:861:861) (899:899:899)) + (PORT datad (1371:1371:1371) (1413:1413:1413)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1201:1201:1201) (1221:1221:1221)) + (PORT ena (984:984:984) (983:983:983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (676:676:676) (712:712:712)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) + (DELAY + (ABSOLUTE + (PORT dataa (1299:1299:1299) (1381:1381:1381)) + (PORT datac (841:841:841) (888:888:888)) + (PORT datad (1369:1369:1369) (1414:1414:1414)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (923:923:923) (907:907:907)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (459:459:459)) + (PORT datab (449:449:449) (481:481:481)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1109:1109:1109) (1118:1118:1118)) + (PORT ena (1426:1426:1426) (1409:1409:1409)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1107:1107:1107) (1116:1116:1116)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (248:248:248) (312:312:312)) + (PORT datab (1080:1080:1080) (1119:1119:1119)) + (PORT datad (362:362:362) (415:415:415)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (701:701:701)) + (PORT datab (642:642:642) (676:676:676)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~91) + (DELAY + (ABSOLUTE + (PORT dataa (1879:1879:1879) (1937:1937:1937)) + (PORT datab (1816:1816:1816) (1903:1903:1903)) + (PORT datac (209:209:209) (252:252:252)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (892:892:892)) + (PORT datab (878:878:878) (922:922:922)) + (PORT datac (538:538:538) (540:540:540)) + (PORT datad (617:617:617) (645:645:645)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1174:1174:1174) (1222:1222:1222)) + (PORT datab (1045:1045:1045) (1100:1100:1100)) + (PORT datac (695:695:695) (747:747:747)) + (PORT datad (1116:1116:1116) (1134:1134:1134)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1256:1256:1256)) + (PORT datab (677:677:677) (742:742:742)) + (PORT datac (546:546:546) (556:556:556)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (528:528:528) (548:548:548)) + (PORT datab (646:646:646) (698:698:698)) + (PORT datac (641:641:641) (670:670:670)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1222:1222:1222) (1224:1224:1224)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (537:537:537) (568:568:568)) + (PORT ena (1237:1237:1237) (1220:1220:1220)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1466:1466:1466) (1518:1518:1518)) + (PORT datab (576:576:576) (596:596:596)) + (PORT datad (642:642:642) (669:669:669)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (460:460:460)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (607:607:607) (629:629:629)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (1052:1052:1052)) + (PORT datab (442:442:442) (513:513:513)) + (PORT datac (1170:1170:1170) (1219:1219:1219)) + (PORT datad (423:423:423) (496:496:496)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (1794:1794:1794) (1867:1867:1867)) + (PORT datab (1235:1235:1235) (1271:1271:1271)) + (PORT datac (1201:1201:1201) (1255:1255:1255)) + (PORT datad (985:985:985) (1038:1038:1038)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (910:910:910) (962:962:962)) + (PORT datad (182:182:182) (214:214:214)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) + (DELAY + (ABSOLUTE + (PORT dataa (1762:1762:1762) (1747:1747:1747)) + (PORT datab (1212:1212:1212) (1248:1248:1248)) + (PORT datac (634:634:634) (657:657:657)) + (PORT datad (825:825:825) (876:876:876)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (685:685:685)) + (PORT datab (647:647:647) (666:666:666)) + (PORT datad (880:880:880) (928:928:928)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (963:963:963)) + (PORT datab (1141:1141:1141) (1159:1159:1159)) + (PORT datac (1626:1626:1626) (1670:1670:1670)) + (PORT datad (878:878:878) (910:910:910)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (371:371:371)) + (PORT datab (915:915:915) (950:950:950)) + (PORT datac (1075:1075:1075) (1082:1082:1082)) + (PORT datad (1088:1088:1088) (1108:1108:1108)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1162:1162:1162) (1199:1199:1199)) + (PORT datab (826:826:826) (911:911:911)) + (PORT datac (1135:1135:1135) (1158:1158:1158)) + (PORT datad (788:788:788) (836:836:836)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1099:1099:1099) (1136:1136:1136)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (997:997:997) (1023:1023:1023)) + (PORT datad (886:886:886) (940:940:940)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1004:1004:1004) (1084:1084:1084)) + (PORT datab (954:954:954) (1049:1049:1049)) + (PORT datac (1094:1094:1094) (1101:1101:1101)) + (PORT datad (195:195:195) (232:232:232)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (947:947:947)) + (PORT datab (837:837:837) (839:839:839)) + (PORT datac (413:413:413) (484:484:484)) + (PORT datad (636:636:636) (716:716:716)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1143:1143:1143) (1162:1162:1162)) + (PORT datab (392:392:392) (471:471:471)) + (PORT datac (1098:1098:1098) (1115:1115:1115)) + (PORT datad (640:640:640) (718:718:718)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (636:636:636)) + (PORT datab (1622:1622:1622) (1684:1684:1684)) + (PORT datac (180:180:180) (218:218:218)) + (PORT datad (862:862:862) (899:899:899)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) + (DELAY + (ABSOLUTE + (PORT dataa (728:728:728) (795:795:795)) + (PORT datab (227:227:227) (268:268:268)) + (PORT datac (201:201:201) (238:238:238)) + (PORT datad (983:983:983) (1020:1020:1020)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1469:1469:1469) (1520:1520:1520)) + (PORT datab (636:636:636) (670:670:670)) + (PORT datac (1209:1209:1209) (1261:1261:1261)) + (PORT datad (653:653:653) (675:675:675)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~25) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (453:453:453)) + (PORT datab (293:293:293) (385:385:385)) + (PORT datad (251:251:251) (325:325:325)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (700:700:700)) + (PORT datab (1035:1035:1035) (1050:1050:1050)) + (PORT datac (1203:1203:1203) (1278:1278:1278)) + (PORT datad (2028:2028:2028) (2053:2053:2053)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla20M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (985:985:985) (1105:1105:1105)) + (PORT datab (783:783:783) (893:893:893)) + (PORT datac (1472:1472:1472) (1539:1539:1539)) + (PORT datad (893:893:893) (943:943:943)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) + (DELAY + (ABSOLUTE + (PORT dataa (725:725:725) (830:830:830)) + (PORT datab (2475:2475:2475) (2536:2536:2536)) + (PORT datac (1334:1334:1334) (1380:1380:1380)) + (PORT datad (707:707:707) (810:810:810)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (867:867:867)) + (PORT datab (655:655:655) (692:692:692)) + (PORT datac (845:845:845) (859:859:859)) + (PORT datad (831:831:831) (863:863:863)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) + (DELAY + (ABSOLUTE + (PORT dataa (1008:1008:1008) (1085:1085:1085)) + (PORT datab (899:899:899) (926:926:926)) + (PORT datac (925:925:925) (1014:1014:1014)) + (PORT datad (194:194:194) (228:228:228)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) + (DELAY + (ABSOLUTE + (PORT dataa (1046:1046:1046) (1122:1122:1122)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) + (DELAY + (ABSOLUTE + (PORT dataa (1231:1231:1231) (1258:1258:1258)) + (PORT datab (1956:1956:1956) (2026:2026:2026)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (575:575:575) (577:577:577)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) + (DELAY + (ABSOLUTE + (PORT dataa (1423:1423:1423) (1498:1498:1498)) + (PORT datab (1500:1500:1500) (1572:1572:1572)) + (PORT datac (866:866:866) (926:926:926)) + (PORT datad (1174:1174:1174) (1212:1212:1212)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1205:1205:1205)) + (PORT datab (873:873:873) (884:884:884)) + (PORT datac (670:670:670) (726:726:726)) + (PORT datad (1092:1092:1092) (1114:1114:1114)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) + (DELAY + (ABSOLUTE + (PORT dataa (1724:1724:1724) (1770:1770:1770)) + (PORT datab (1956:1956:1956) (2027:2027:2027)) + (PORT datac (609:609:609) (664:664:664)) + (PORT datad (828:828:828) (846:846:846)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1195:1195:1195) (1241:1241:1241)) + (PORT datab (704:704:704) (759:759:759)) + (PORT datac (192:192:192) (226:226:226)) + (PORT datad (683:683:683) (746:746:746)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (277:277:277)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (614:614:614) (645:645:645)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~18) + (DELAY + (ABSOLUTE + (PORT dataa (2201:2201:2201) (2281:2281:2281)) + (PORT datab (1459:1459:1459) (1512:1512:1512)) + (PORT datac (730:730:730) (781:781:781)) + (PORT datad (216:216:216) (249:249:249)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1006:1006:1006) (1082:1082:1082)) + (PORT datab (957:957:957) (1052:1052:1052)) + (PORT datac (599:599:599) (626:626:626)) + (PORT datad (1185:1185:1185) (1214:1214:1214)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~17) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (636:636:636)) + (PORT datab (580:580:580) (603:603:603)) + (PORT datac (2168:2168:2168) (2243:2243:2243)) + (PORT datad (533:533:533) (549:549:549)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1375:1375:1375) (1410:1410:1410)) + (PORT datab (757:757:757) (812:812:812)) + (PORT datac (2169:2169:2169) (2240:2240:2240)) + (PORT datad (1276:1276:1276) (1310:1310:1310)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (989:989:989) (1068:1068:1068)) + (PORT datab (1342:1342:1342) (1431:1431:1431)) + (PORT datac (728:728:728) (781:781:781)) + (PORT datad (915:915:915) (953:953:953)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~20) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (255:255:255)) + (PORT datab (236:236:236) (281:281:281)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~36) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (899:899:899)) + (PORT datab (777:777:777) (885:885:885)) + (PORT datac (628:628:628) (674:674:674)) + (PORT datad (707:707:707) (811:811:811)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~15) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (642:642:642)) + (PORT datab (744:744:744) (781:781:781)) + (PORT datac (1960:1960:1960) (2018:2018:2018)) + (PORT datad (808:808:808) (821:821:821)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~16) + (DELAY + (ABSOLUTE + (PORT dataa (748:748:748) (853:853:853)) + (PORT datab (779:779:779) (885:885:885)) + (PORT datac (754:754:754) (860:860:860)) + (PORT datad (1842:1842:1842) (1891:1891:1891)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~21) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (720:720:720)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (525:525:525) (536:536:536)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) + (DELAY + (ABSOLUTE + (PORT dataa (1156:1156:1156) (1178:1178:1178)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (809:809:809) (833:833:833)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1655:1655:1655) (1672:1672:1672)) + (PORT datab (1989:1989:1989) (2051:2051:2051)) + (PORT datac (877:877:877) (900:900:900)) + (PORT datad (1449:1449:1449) (1444:1444:1444)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) + (DELAY + (ABSOLUTE + (PORT datab (777:777:777) (881:881:881)) + (PORT datac (751:751:751) (853:853:853)) + (PORT datad (1014:1014:1014) (1034:1034:1034)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~34) + (DELAY + (ABSOLUTE + (PORT dataa (725:725:725) (827:827:827)) + (PORT datab (2350:2350:2350) (2475:2475:2475)) + (PORT datac (751:751:751) (853:853:853)) + (PORT datad (649:649:649) (694:694:694)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~22) + (DELAY + (ABSOLUTE + (PORT datab (1154:1154:1154) (1254:1254:1254)) + (PORT datac (908:908:908) (984:984:984)) + (PORT datad (695:695:695) (796:796:796)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~23) + (DELAY + (ABSOLUTE + (PORT dataa (2509:2509:2509) (2581:2581:2581)) + (PORT datab (930:930:930) (981:981:981)) + (PORT datac (1138:1138:1138) (1158:1158:1158)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~35) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (935:935:935)) + (PORT datab (776:776:776) (881:881:881)) + (PORT datac (751:751:751) (854:854:854)) + (PORT datad (563:563:563) (572:572:572)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~24) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (240:240:240)) + (PORT datab (213:213:213) (256:256:256)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (207:207:207) (237:237:237)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) + (DELAY + (ABSOLUTE + (PORT datab (390:390:390) (430:430:430)) + (PORT datad (887:887:887) (895:895:895)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) + (DELAY + (ABSOLUTE + (PORT dataa (1066:1066:1066) (1104:1104:1104)) + (PORT datab (452:452:452) (487:487:487)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (1994:1994:1994) (2001:2001:2001)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) + (DELAY + (ABSOLUTE + (PORT dataa (993:993:993) (1075:1075:1075)) + (PORT datab (1343:1343:1343) (1437:1437:1437)) + (PORT datac (2168:2168:2168) (2246:2246:2246)) + (PORT datad (914:914:914) (958:958:958)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (389:389:389)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1584:1584:1584) (1620:1620:1620)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (726:726:726)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (882:882:882) (905:905:905)) + (PORT datad (1416:1416:1416) (1450:1450:1450)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (1449:1449:1449) (1484:1484:1484)) + (PORT datac (344:344:344) (368:368:368)) + (PORT datad (215:215:215) (248:248:248)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~95) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (899:899:899)) + (PORT datab (2351:2351:2351) (2480:2480:2480)) + (PORT datac (628:628:628) (672:672:672)) + (PORT datad (671:671:671) (769:769:769)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (718:718:718)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (524:524:524) (535:535:535)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~27) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (257:257:257)) + (PORT datab (237:237:237) (282:282:282)) + (PORT datac (727:727:727) (782:782:782)) + (PORT datad (217:217:217) (251:251:251)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (439:439:439)) + (PORT datab (296:296:296) (390:390:390)) + (PORT datac (1137:1137:1137) (1168:1168:1168)) + (PORT datad (250:250:250) (323:323:323)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) + (DELAY + (ABSOLUTE + (PORT dataa (2200:2200:2200) (2281:2281:2281)) + (PORT datab (236:236:236) (278:278:278)) + (PORT datac (602:602:602) (659:659:659)) + (PORT datad (1039:1039:1039) (1034:1034:1034)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (1452:1452:1452) (1485:1485:1485)) + (PORT datac (1451:1451:1451) (1488:1488:1488)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) + (DELAY + (ABSOLUTE + (PORT dataa (580:580:580) (594:594:594)) + (PORT datab (550:550:550) (563:563:563)) + (PORT datac (1357:1357:1357) (1370:1370:1370)) + (PORT datad (647:647:647) (674:674:674)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (584:584:584)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (209:209:209) (241:241:241)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (634:634:634) (678:678:678)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (607:607:607) (648:648:648)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (902:902:902)) + (PORT datab (2019:2019:2019) (2038:2038:2038)) + (PORT datac (811:811:811) (824:824:824)) + (PORT datad (887:887:887) (895:895:895)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~26) + (DELAY + (ABSOLUTE + (PORT datab (217:217:217) (262:262:262)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (212:212:212) (244:244:244)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1970:1970:1970) (2029:2029:2029)) + (PORT datac (826:826:826) (890:890:890)) + (PORT datad (544:544:544) (549:549:549)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (415:415:415)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (608:608:608) (631:631:631)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (275:275:275)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~89) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (658:658:658)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datad (336:336:336) (360:360:360)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~90) + (DELAY + (ABSOLUTE + (PORT dataa (1211:1211:1211) (1241:1241:1241)) + (PORT datab (451:451:451) (487:487:487)) + (PORT datac (746:746:746) (800:800:800)) + (PORT datad (1929:1929:1929) (1986:1986:1986)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~91) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1218:1218:1218) (1238:1238:1238)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1992:1992:1992) (2003:2003:2003)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (957:957:957)) + (PORT datab (948:948:948) (988:988:988)) + (PORT datac (952:952:952) (1040:1040:1040)) + (PORT datad (1244:1244:1244) (1337:1337:1337)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (920:920:920)) + (PORT datab (555:555:555) (584:584:584)) + (PORT datac (2651:2651:2651) (2699:2699:2699)) + (PORT datad (325:325:325) (347:347:347)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~100) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1107:1107:1107)) + (PORT datab (787:787:787) (896:896:896)) + (PORT datac (722:722:722) (831:831:831)) + (PORT datad (1631:1631:1631) (1626:1626:1626)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~92) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (546:546:546) (547:547:547)) + (PORT datad (1991:1991:1991) (2002:2002:2002)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1291:1291:1291) (1360:1360:1360)) + (PORT datab (1487:1487:1487) (1548:1548:1548)) + (PORT datac (611:611:611) (675:675:675)) + (PORT datad (827:827:827) (876:876:876)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (906:906:906)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (1102:1102:1102) (1091:1091:1091)) + (PORT datad (362:362:362) (397:397:397)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~29) + (DELAY + (ABSOLUTE + (PORT dataa (2510:2510:2510) (2578:2578:2578)) + (PORT datab (968:968:968) (1013:1013:1013)) + (PORT datac (1329:1329:1329) (1335:1335:1335)) + (PORT datad (869:869:869) (880:880:880)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~30) + (DELAY + (ABSOLUTE + (PORT dataa (426:426:426) (476:476:476)) + (PORT datab (968:968:968) (1011:1011:1011)) + (PORT datac (1340:1340:1340) (1390:1390:1390)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~31) + (DELAY + (ABSOLUTE + (PORT dataa (426:426:426) (475:475:475)) + (PORT datab (896:896:896) (921:921:921)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~32) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (389:389:389)) + (PORT datab (388:388:388) (429:429:429)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (886:886:886) (895:895:895)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~93) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (1994:1994:1994) (2001:2001:2001)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) + (DELAY + (ABSOLUTE + (PORT datab (1398:1398:1398) (1449:1449:1449)) + (PORT datac (1373:1373:1373) (1416:1416:1416)) + (PORT datad (1070:1070:1070) (1118:1118:1118)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (990:990:990) (1026:1026:1026)) + (PORT ena (1147:1147:1147) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (990:990:990) (1026:1026:1026)) + (PORT ena (1248:1248:1248) (1262:1262:1262)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (664:664:664)) + (PORT datab (941:941:941) (1002:1002:1002)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (679:679:679) (694:694:694)) + (PORT ena (1243:1243:1243) (1273:1273:1273)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (448:448:448)) + (PORT datab (941:941:941) (971:971:971)) + (PORT datac (952:952:952) (1001:1001:1001)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (920:920:920)) + (PORT datab (889:889:889) (924:924:924)) + (PORT datac (807:807:807) (828:828:828)) + (PORT datad (558:558:558) (581:581:581)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1257:1257:1257) (1295:1295:1295)) + (PORT ena (1546:1546:1546) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1260:1260:1260) (1299:1299:1299)) + (PORT ena (1446:1446:1446) (1455:1455:1455)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1050:1050:1050)) + (PORT datab (965:965:965) (1007:1007:1007)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (978:978:978) (1023:1023:1023)) + (PORT ena (1475:1475:1475) (1479:1479:1479)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (637:637:637) (678:678:678)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1485:1485:1485) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (920:920:920) (979:979:979)) + (PORT datab (934:934:934) (981:981:981)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1132:1132:1132) (1209:1209:1209)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1492:1492:1492) (1562:1562:1562)) + (PORT datab (665:665:665) (715:715:715)) + (PORT datad (1640:1640:1640) (1755:1755:1755)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (631:631:631) (671:671:671)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1186:1186:1186) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1005:1005:1005) (1051:1051:1051)) + (PORT ena (1476:1476:1476) (1478:1478:1478)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (328:328:328)) + (PORT datab (957:957:957) (994:994:994)) + (PORT datad (880:880:880) (927:927:927)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1153:1153:1153) (1205:1205:1205)) + (PORT ena (1204:1204:1204) (1190:1190:1190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT asdata (1497:1497:1497) (1521:1521:1521)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (686:686:686) (744:744:744)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datad (587:587:587) (604:604:604)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1256:1256:1256) (1290:1290:1290)) + (PORT ena (1213:1213:1213) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1257:1257:1257) (1292:1292:1292)) + (PORT ena (1163:1163:1163) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (708:708:708)) + (PORT datab (242:242:242) (324:324:324)) + (PORT datad (625:625:625) (661:661:661)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT asdata (1551:1551:1551) (1646:1646:1646)) + (PORT ena (1256:1256:1256) (1263:1263:1263)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (912:912:912)) + (PORT datab (1255:1255:1255) (1305:1305:1305)) + (PORT datad (635:635:635) (652:652:652)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (685:685:685)) + (PORT datab (803:803:803) (863:863:863)) + (PORT datac (602:602:602) (611:611:611)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (867:867:867)) + (PORT datab (1027:1027:1027) (1075:1075:1075)) + (PORT datac (339:339:339) (360:360:360)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1158:1158:1158) (1174:1174:1174)) + (PORT datab (1389:1389:1389) (1427:1427:1427)) + (PORT datac (932:932:932) (1001:1001:1001)) + (PORT datad (1353:1353:1353) (1389:1389:1389)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) + (DELAY + (ABSOLUTE + (PORT dataa (2598:2598:2598) (2655:2655:2655)) + (PORT datab (203:203:203) (244:244:244)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) + (DELAY + (ABSOLUTE + (PORT datac (1110:1110:1110) (1142:1142:1142)) + (PORT datad (1438:1438:1438) (1486:1486:1486)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (710:710:710)) + (PORT datab (940:940:940) (967:967:967)) + (PORT datac (1128:1128:1128) (1173:1173:1173)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1160:1160:1160) (1209:1209:1209)) + (PORT datac (912:912:912) (935:935:935)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1157:1157:1157) (1206:1206:1206)) + (PORT datab (943:943:943) (970:970:970)) + (PORT datac (1105:1105:1105) (1135:1135:1135)) + (PORT datad (1434:1434:1434) (1479:1479:1479)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (430:430:430) (493:493:493)) + (PORT datac (568:568:568) (586:586:586)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (690:690:690) (717:717:717)) + (PORT ena (1147:1147:1147) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (690:690:690) (717:717:717)) + (PORT ena (1248:1248:1248) (1262:1262:1262)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (665:665:665)) + (PORT datab (946:946:946) (1002:1002:1002)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1265:1265:1265) (1314:1314:1314)) + (PORT ena (1426:1426:1426) (1409:1409:1409)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1265:1265:1265) (1316:1316:1316)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (312:312:312)) + (PORT datab (1085:1085:1085) (1113:1113:1113)) + (PORT datad (357:357:357) (417:417:417)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (919:919:919) (943:943:943)) + (PORT ena (923:923:923) (907:907:907)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (919:919:919) (943:943:943)) + (PORT ena (984:984:984) (983:983:983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (457:457:457)) + (PORT datab (240:240:240) (322:322:322)) + (PORT datad (417:417:417) (444:444:444)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1412:1412:1412) (1427:1427:1427)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1288:1288:1288) (1376:1376:1376)) + (PORT datab (1003:1003:1003) (1047:1047:1047)) + (PORT datad (892:892:892) (942:942:942)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1471:1471:1471) (1507:1507:1507)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1489:1489:1489) (1614:1614:1614)) + (PORT datab (1521:1521:1521) (1656:1656:1656)) + (PORT datac (2142:2142:2142) (2142:2142:2142)) + (PORT datad (646:646:646) (662:662:662)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (284:284:284)) + (PORT datab (736:736:736) (799:799:799)) + (PORT datac (897:897:897) (948:948:948)) + (PORT datad (1169:1169:1169) (1226:1226:1226)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (952:952:952)) + (PORT datab (644:644:644) (665:665:665)) + (PORT datac (1286:1286:1286) (1331:1331:1331)) + (PORT datad (335:335:335) (355:355:355)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT datab (829:829:829) (884:884:884)) + (PORT datac (710:710:710) (803:803:803)) + (PORT datad (644:644:644) (666:666:666)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (942:942:942)) + (PORT datab (1388:1388:1388) (1430:1430:1430)) + (PORT datac (205:205:205) (241:241:241)) + (PORT datad (172:172:172) (196:196:196)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (207:207:207) (245:245:245)) + (PORT datad (1277:1277:1277) (1328:1328:1328)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1277:1277:1277)) + (PORT datac (2040:2040:2040) (2164:2164:2164)) + (PORT datad (1304:1304:1304) (1444:1444:1444)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~10) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (693:693:693)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (546:546:546) (555:555:555)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1942:1942:1942) (2136:2136:2136)) + (PORT datab (1507:1507:1507) (1522:1522:1522)) + (PORT datac (1089:1089:1089) (1120:1120:1120)) + (PORT datad (1570:1570:1570) (1713:1713:1713)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1803:1803:1803) (1900:1900:1900)) + (PORT datab (1596:1596:1596) (1748:1748:1748)) + (PORT datac (3144:3144:3144) (3233:3233:3233)) + (PORT datad (1902:1902:1902) (2090:2090:2090)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1474:1474:1474) (1525:1525:1525)) + (PORT datab (1976:1976:1976) (2075:2075:2075)) + (PORT datac (1520:1520:1520) (1551:1551:1551)) + (PORT datad (1771:1771:1771) (1858:1858:1858)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~11) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (197:197:197) (234:234:234)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (1561:1561:1561) (1627:1627:1627)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~12) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (643:643:643)) + (PORT datab (602:602:602) (655:655:655)) + (PORT datac (616:616:616) (660:660:660)) + (PORT datad (343:343:343) (363:363:363)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (288:288:288)) + (PORT datab (665:665:665) (693:693:693)) + (PORT datac (1025:1025:1025) (1030:1030:1030)) + (PORT datad (584:584:584) (607:607:607)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) + (DELAY + (ABSOLUTE + (PORT dataa (957:957:957) (975:975:975)) + (PORT datab (657:657:657) (694:694:694)) + (PORT datac (1759:1759:1759) (1816:1816:1816)) + (PORT datad (562:562:562) (580:580:580)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (638:638:638)) + (PORT datab (656:656:656) (696:696:696)) + (PORT datac (178:178:178) (217:217:217)) + (PORT datad (943:943:943) (992:992:992)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) + (DELAY + (ABSOLUTE + (PORT datac (555:555:555) (591:591:591)) + (PORT datad (1085:1085:1085) (1092:1092:1092)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (2000:2000:2000) (2156:2156:2156)) + (PORT datab (1422:1422:1422) (1488:1488:1488)) + (PORT datad (1323:1323:1323) (1495:1495:1495)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (1021:1021:1021)) + (PORT datab (993:993:993) (1042:1042:1042)) + (PORT datac (1464:1464:1464) (1524:1524:1524)) + (PORT datad (1227:1227:1227) (1313:1313:1313)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (253:253:253)) + (PORT datab (965:965:965) (1025:1025:1025)) + (PORT datac (912:912:912) (977:977:977)) + (PORT datad (958:958:958) (998:998:998)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1856:1856:1856) (1890:1890:1890)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (584:584:584) (639:639:639)) + (PORT datad (1583:1583:1583) (1570:1570:1570)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1386:1386:1386) (1474:1474:1474)) + (PORT datab (1349:1349:1349) (1521:1521:1521)) + (PORT datac (1103:1103:1103) (1126:1126:1126)) + (PORT datad (1358:1358:1358) (1519:1519:1519)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (268:268:268)) + (PORT datab (642:642:642) (688:688:688)) + (PORT datad (333:333:333) (358:358:358)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S) + (DELAY + (ABSOLUTE + (PORT dataa (1090:1090:1090) (1128:1128:1128)) + (PORT datab (820:820:820) (850:850:850)) + (PORT datac (558:558:558) (591:591:591)) + (PORT datad (546:546:546) (551:551:551)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal73\~2) + (DELAY + (ABSOLUTE + (PORT dataa (997:997:997) (1074:1074:1074)) + (PORT datab (881:881:881) (904:904:904)) + (PORT datac (1049:1049:1049) (1138:1138:1138)) + (PORT datad (1271:1271:1271) (1360:1360:1360)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (734:734:734)) + (PORT datab (924:924:924) (980:980:980)) + (PORT datac (1471:1471:1471) (1536:1536:1536)) + (PORT datad (1149:1149:1149) (1181:1181:1181)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R) + (DELAY + (ABSOLUTE + (PORT dataa (1111:1111:1111) (1132:1132:1132)) + (PORT datab (360:360:360) (393:393:393)) + (PORT datac (555:555:555) (590:590:590)) + (PORT datad (1061:1061:1061) (1074:1074:1074)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) + (DELAY + (ABSOLUTE + (PORT datab (226:226:226) (267:267:267)) + (PORT datac (601:601:601) (626:626:626)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (266:266:266)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (861:861:861) (894:894:894)) + (PORT datad (593:593:593) (607:607:607)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (694:694:694)) + (PORT datab (1536:1536:1536) (1599:1599:1599)) + (PORT datac (961:961:961) (990:990:990)) + (PORT datad (1384:1384:1384) (1458:1458:1458)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (893:893:893)) + (PORT datab (563:563:563) (581:581:581)) + (PORT datac (801:801:801) (807:807:807)) + (PORT datad (831:831:831) (859:859:859)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (340:340:340)) + (PORT datab (1770:1770:1770) (1810:1810:1810)) + (PORT datac (255:255:255) (312:312:312)) + (PORT datad (1200:1200:1200) (1271:1271:1271)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1728:1728:1728) (1834:1834:1834)) + (PORT datab (887:887:887) (890:890:890)) + (PORT datac (859:859:859) (902:902:902)) + (PORT datad (1842:1842:1842) (2007:2007:2007)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1729:1729:1729) (1835:1835:1835)) + (PORT datab (1714:1714:1714) (1825:1825:1825)) + (PORT datac (859:859:859) (903:903:903)) + (PORT datad (2100:2100:2100) (2296:2296:2296)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (250:250:250)) + (PORT datab (221:221:221) (269:269:269)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (201:201:201) (229:229:229)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (719:719:719) (745:745:745)) + (PORT ena (1475:1475:1475) (1479:1479:1479)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (718:718:718) (747:747:747)) + (PORT ena (1485:1485:1485) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (982:982:982)) + (PORT datab (937:937:937) (984:984:984)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1270:1270:1270) (1302:1302:1302)) + (PORT ena (1546:1546:1546) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1271:1271:1271) (1304:1304:1304)) + (PORT ena (1446:1446:1446) (1455:1455:1455)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (998:998:998) (1056:1056:1056)) + (PORT datab (968:968:968) (1014:1014:1014)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (999:999:999) (1040:1040:1040)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1487:1487:1487) (1562:1562:1562)) + (PORT datab (657:657:657) (709:709:709)) + (PORT datad (1632:1632:1632) (1751:1751:1751)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT asdata (1772:1772:1772) (1847:1847:1847)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1916:1916:1916) (1967:1967:1967)) + (PORT ena (1196:1196:1196) (1165:1165:1165)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (700:700:700)) + (PORT datab (498:498:498) (553:553:553)) + (PORT datad (627:627:627) (659:659:659)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT asdata (1475:1475:1475) (1524:1524:1524)) + (PORT ena (1256:1256:1256) (1263:1263:1263)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (921:921:921)) + (PORT datab (672:672:672) (692:692:692)) + (PORT datad (1219:1219:1219) (1269:1269:1269)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1476:1476:1476) (1478:1478:1478)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (913:913:913) (927:927:927)) + (PORT ena (1186:1186:1186) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (972:972:972)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (917:917:917) (961:961:961)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1003:1003:1003) (1054:1054:1054)) + (PORT ena (1163:1163:1163) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1001:1001:1001) (1054:1054:1054)) + (PORT ena (1213:1213:1213) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (706:706:706)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datad (625:625:625) (656:656:656)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (666:666:666)) + (PORT datab (831:831:831) (898:898:898)) + (PORT datac (578:578:578) (588:588:588)) + (PORT datad (591:591:591) (603:603:603)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (843:843:843)) + (PORT datab (1032:1032:1032) (1063:1063:1063)) + (PORT datac (813:813:813) (859:859:859)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (1040:1040:1040)) + (PORT datac (960:960:960) (1021:1021:1021)) + (PORT datad (1216:1216:1216) (1283:1283:1283)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1164:1164:1164) (1183:1183:1183)) + (PORT ena (1164:1164:1164) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (965:965:965) (1036:1036:1036)) + (PORT datab (992:992:992) (1052:1052:1052)) + (PORT datac (1247:1247:1247) (1332:1332:1332)) + (PORT datad (1118:1118:1118) (1138:1138:1138)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1491:1491:1491) (1578:1578:1578)) + (PORT datab (588:588:588) (620:620:620)) + (PORT datad (574:574:574) (600:600:600)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (DELAY + (ABSOLUTE + (PORT datab (979:979:979) (1030:1030:1030)) + (PORT datac (935:935:935) (999:999:999)) + (PORT datad (1216:1216:1216) (1283:1283:1283)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1185:1185:1185) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) + (DELAY + (ABSOLUTE + (PORT datab (973:973:973) (1024:1024:1024)) + (PORT datac (931:931:931) (993:993:993)) + (PORT datad (1213:1213:1213) (1277:1277:1277)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (243:243:243) (325:325:325)) + (PORT datad (565:565:565) (592:592:592)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1185:1185:1185) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1019:1019:1019) (1071:1071:1071)) + (PORT ena (1546:1546:1546) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1018:1018:1018) (1071:1071:1071)) + (PORT ena (1446:1446:1446) (1455:1455:1455)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (997:997:997) (1051:1051:1051)) + (PORT datab (965:965:965) (1008:1008:1008)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (914:914:914) (930:930:930)) + (PORT ena (1475:1475:1475) (1479:1479:1479)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (914:914:914) (930:930:930)) + (PORT ena (1485:1485:1485) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (978:978:978)) + (PORT datab (931:931:931) (977:977:977)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1218:1218:1218) (1256:1256:1256)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1486:1486:1486) (1558:1558:1558)) + (PORT datab (659:659:659) (703:703:703)) + (PORT datad (1630:1630:1630) (1743:1743:1743)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1214:1214:1214) (1253:1253:1253)) + (PORT ena (1163:1163:1163) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1211:1211:1211) (1250:1250:1250)) + (PORT ena (1213:1213:1213) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (712:712:712)) + (PORT datab (242:242:242) (325:325:325)) + (PORT datad (623:623:623) (658:658:658)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (697:697:697) (721:721:721)) + (PORT ena (1186:1186:1186) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1476:1476:1476) (1478:1478:1478)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (968:968:968)) + (PORT datab (959:959:959) (996:996:996)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT asdata (1223:1223:1223) (1248:1248:1248)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1227:1227:1227) (1258:1258:1258)) + (PORT ena (1196:1196:1196) (1165:1165:1165)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (431:431:431) (520:520:520)) + (PORT datab (498:498:498) (554:554:554)) + (PORT datad (627:627:627) (659:659:659)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1229:1229:1229) (1261:1261:1261)) + (PORT ena (1256:1256:1256) (1255:1255:1255)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (984:984:984) (1035:1035:1035)) + (PORT datab (1291:1291:1291) (1330:1330:1330)) + (PORT datad (1490:1490:1490) (1545:1545:1545)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (369:369:369)) + (PORT datab (654:654:654) (670:670:670)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (382:382:382)) + (PORT datab (615:615:615) (642:642:642)) + (PORT datac (632:632:632) (658:658:658)) + (PORT datad (613:613:613) (637:637:637)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (847:847:847)) + (PORT datab (405:405:405) (445:445:445)) + (PORT datac (1349:1349:1349) (1373:1373:1373)) + (PORT datad (593:593:593) (611:611:611)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (895:895:895) (905:905:905)) + (PORT ena (1164:1164:1164) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (645:645:645)) + (PORT datab (1250:1250:1250) (1323:1323:1323)) + (PORT datad (563:563:563) (584:584:584)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (327:327:327)) + (PORT datab (589:589:589) (623:623:623)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[8\]) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (405:405:405)) + (PORT datac (883:883:883) (935:935:935)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (658:658:658)) + (PORT datab (215:215:215) (260:260:260)) + (PORT datac (179:179:179) (218:218:218)) + (PORT datad (603:603:603) (621:621:621)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (236:236:236) (288:288:288)) + (PORT datab (680:680:680) (738:738:738)) + (PORT datac (1196:1196:1196) (1238:1238:1238)) + (PORT datad (1772:1772:1772) (1834:1834:1834)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (860:860:860)) + (PORT datab (1104:1104:1104) (1147:1147:1147)) + (PORT datac (1002:1002:1002) (1071:1071:1071)) + (PORT datad (847:847:847) (873:873:873)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (941:941:941)) + (PORT datab (916:916:916) (948:948:948)) + (PORT datac (338:338:338) (357:357:357)) + (PORT datad (854:854:854) (893:893:893)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (422:422:422) (453:453:453)) + (PORT datab (1472:1472:1472) (1490:1490:1490)) + (PORT datac (1016:1016:1016) (1077:1077:1077)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (374:374:374)) + (PORT datab (663:663:663) (676:676:676)) + (PORT datac (551:551:551) (566:566:566)) + (PORT datad (616:616:616) (633:633:633)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1147:1147:1147) (1215:1215:1215)) + (PORT datab (1209:1209:1209) (1278:1278:1278)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (827:827:827) (839:839:839)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (1783:1783:1783) (1814:1814:1814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1222:1222:1222) (1224:1224:1224)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (900:900:900) (908:908:908)) + (PORT ena (1426:1426:1426) (1409:1409:1409)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (900:900:900) (911:911:911)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (246:246:246) (318:318:318)) + (PORT datab (1081:1081:1081) (1113:1113:1113)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1215:1215:1215) (1256:1256:1256)) + (PORT ena (984:984:984) (983:983:983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1217:1217:1217) (1254:1254:1254)) + (PORT ena (923:923:923) (907:907:907)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (462:462:462)) + (PORT datab (452:452:452) (481:481:481)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (621:621:621) (651:651:651)) + (PORT datac (1318:1318:1318) (1334:1334:1334)) + (PORT datad (1133:1133:1133) (1166:1166:1166)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (596:596:596)) + (PORT datab (1148:1148:1148) (1164:1164:1164)) + (PORT datac (1083:1083:1083) (1082:1082:1082)) + (PORT datad (819:819:819) (843:843:843)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (835:835:835)) + (PORT datab (390:390:390) (417:417:417)) + (PORT datac (1069:1069:1069) (1074:1074:1074)) + (PORT datad (1075:1075:1075) (1109:1109:1109)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (685:685:685)) + (PORT datab (1345:1345:1345) (1363:1363:1363)) + (PORT datac (653:653:653) (717:717:717)) + (PORT datad (1140:1140:1140) (1170:1170:1170)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (952:952:952)) + (PORT datab (882:882:882) (913:913:913)) + (PORT datac (1082:1082:1082) (1120:1120:1120)) + (PORT datad (836:836:836) (859:859:859)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (911:911:911)) + (PORT datab (599:599:599) (619:619:619)) + (PORT datac (802:802:802) (820:820:820)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (952:952:952)) + (PORT datab (903:903:903) (934:934:934)) + (PORT datac (806:806:806) (826:826:826)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (954:954:954)) + (PORT datab (891:891:891) (915:915:915)) + (PORT datac (862:862:862) (932:932:932)) + (PORT datad (1058:1058:1058) (1077:1077:1077)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT asdata (1695:1695:1695) (1745:1745:1745)) + (PORT ena (961:961:961) (970:970:970)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1005:1005:1005) (1047:1047:1047)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (841:841:841) (847:847:847)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (710:710:710)) + (PORT datab (244:244:244) (289:289:289)) + (PORT datad (547:547:547) (596:596:596)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1690:1690:1690) (1722:1722:1722)) + (PORT ena (1168:1168:1168) (1161:1161:1161)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT asdata (1694:1694:1694) (1745:1745:1745)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1687:1687:1687) (1719:1719:1719)) + (PORT ena (1243:1243:1243) (1273:1273:1273)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (759:759:759)) + (PORT datab (676:676:676) (718:718:718)) + (PORT datad (629:629:629) (658:658:658)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (411:411:411) (458:458:458)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1445:1445:1445) (1462:1462:1462)) + (PORT ena (1147:1147:1147) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1445:1445:1445) (1465:1465:1465)) + (PORT ena (1248:1248:1248) (1262:1262:1262)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (661:661:661)) + (PORT datab (941:941:941) (1000:1000:1000)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (622:622:622)) + (PORT datab (801:801:801) (823:823:823)) + (PORT datac (647:647:647) (685:685:685)) + (PORT datad (828:828:828) (870:870:870)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (704:704:704)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datad (622:622:622) (661:661:661)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (899:899:899)) + (PORT datab (353:353:353) (392:392:392)) + (PORT datac (1132:1132:1132) (1184:1184:1184)) + (PORT datad (670:670:670) (701:701:701)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (672:672:672) (695:695:695)) + (PORT ena (1237:1237:1237) (1220:1220:1220)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1469:1469:1469) (1520:1520:1520)) + (PORT datab (820:820:820) (835:835:835)) + (PORT datad (653:653:653) (675:675:675)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datad (607:607:607) (630:630:630)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) + (DELAY + (ABSOLUTE + (PORT datab (704:704:704) (782:782:782)) + (PORT datad (796:796:796) (798:798:798)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (1209:1209:1209) (1265:1265:1265)) + (PORT datad (217:217:217) (253:253:253)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (1104:1104:1104) (1132:1132:1132)) + (PORT datad (634:634:634) (652:652:652)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1592:1592:1592) (1568:1568:1568)) + (PORT ena (2023:2023:2023) (2039:2039:2039)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1245:1245:1245) (1250:1250:1250)) + (PORT datab (904:904:904) (935:935:935)) + (PORT datac (384:384:384) (452:452:452)) + (PORT datad (911:911:911) (971:971:971)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) + (DELAY + (ABSOLUTE + (PORT datac (390:390:390) (464:464:464)) + (PORT datad (189:189:189) (222:222:222)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1543:1543:1543) (1611:1611:1611)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (432:432:432) (479:479:479)) + (PORT datad (319:319:319) (341:341:341)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[9\]) + (DELAY + (ABSOLUTE + (PORT datac (880:880:880) (934:934:934)) + (PORT datad (313:313:313) (333:333:333)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (1783:1783:1783) (1814:1814:1814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (892:892:892) (909:909:909)) + (PORT ena (1203:1203:1203) (1189:1189:1189)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1387:1387:1387) (1394:1394:1394)) + (PORT ena (1256:1256:1256) (1255:1255:1255)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (983:983:983) (1035:1035:1035)) + (PORT datab (1288:1288:1288) (1327:1327:1327)) + (PORT datad (831:831:831) (901:901:901)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1476:1476:1476) (1478:1478:1478)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1200:1200:1200) (1214:1214:1214)) + (PORT ena (1186:1186:1186) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (330:330:330)) + (PORT datab (957:957:957) (998:998:998)) + (PORT datad (879:879:879) (924:924:924)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1245:1245:1245) (1259:1259:1259)) + (PORT ena (1163:1163:1163) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1245:1245:1245) (1259:1259:1259)) + (PORT ena (1213:1213:1213) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (706:706:706)) + (PORT datab (240:240:240) (322:322:322)) + (PORT datad (621:621:621) (655:655:655)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT asdata (1206:1206:1206) (1211:1211:1211)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1386:1386:1386) (1392:1392:1392)) + (PORT ena (1196:1196:1196) (1165:1165:1165)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (423:423:423) (513:513:513)) + (PORT datab (498:498:498) (557:557:557)) + (PORT datad (622:622:622) (662:662:662)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (674:674:674)) + (PORT datab (845:845:845) (862:862:862)) + (PORT datac (584:584:584) (597:597:597)) + (PORT datad (575:575:575) (585:585:585)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1426:1426:1426) (1436:1436:1436)) + (PORT ena (1546:1546:1546) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1076:1076:1076) (1088:1088:1088)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1446:1446:1446) (1455:1455:1455)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (998:998:998) (1056:1056:1056)) + (PORT datab (964:964:964) (1012:1012:1012)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1210:1210:1210) (1217:1217:1217)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1484:1484:1484) (1556:1556:1556)) + (PORT datab (656:656:656) (706:706:706)) + (PORT datad (1631:1631:1631) (1740:1740:1740)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (709:709:709) (736:736:736)) + (PORT ena (1485:1485:1485) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (709:709:709) (736:736:736)) + (PORT ena (1475:1475:1475) (1479:1479:1479)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (977:977:977)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datad (899:899:899) (938:938:938)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (672:672:672)) + (PORT datab (674:674:674) (694:694:694)) + (PORT datac (855:855:855) (905:905:905)) + (PORT datad (319:319:319) (339:339:339)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (579:579:579)) + (PORT datab (400:400:400) (438:438:438)) + (PORT datac (1346:1346:1346) (1369:1369:1369)) + (PORT datad (569:569:569) (587:587:587)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (694:694:694)) + (PORT datab (621:621:621) (667:667:667)) + (PORT datad (582:582:582) (592:592:592)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1185:1185:1185) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (403:403:403) (482:482:482)) + (PORT datad (585:585:585) (610:610:610)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (423:423:423) (508:508:508)) + (PORT datab (905:905:905) (932:932:932)) + (PORT datac (415:415:415) (484:484:484)) + (PORT datad (188:188:188) (218:218:218)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1540:1540:1540) (1609:1609:1609)) + (PORT datab (380:380:380) (414:414:414)) + (PORT datac (435:435:435) (484:484:484)) + (PORT datad (359:359:359) (378:378:378)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[10\]) + (DELAY + (ABSOLUTE + (PORT datac (883:883:883) (940:940:940)) + (PORT datad (333:333:333) (350:350:350)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (1783:1783:1783) (1814:1814:1814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (421:421:421) (503:503:503)) + (PORT datab (904:904:904) (930:930:930)) + (PORT datac (414:414:414) (483:483:483)) + (PORT datad (189:189:189) (222:222:222)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (2165:2165:2165) (2195:2195:2195)) + (PORT ena (1475:1475:1475) (1479:1479:1479)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (2167:2167:2167) (2197:2197:2197)) + (PORT ena (1485:1485:1485) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (982:982:982)) + (PORT datab (932:932:932) (982:982:982)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1965:1965:1965) (2001:2001:2001)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1487:1487:1487) (1563:1563:1563)) + (PORT datab (662:662:662) (714:714:714)) + (PORT datad (1637:1637:1637) (1748:1748:1748)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (959:959:959) (984:984:984)) + (PORT ena (1546:1546:1546) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (961:961:961) (982:982:982)) + (PORT ena (1446:1446:1446) (1455:1455:1455)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1058:1058:1058)) + (PORT datab (964:964:964) (1012:1012:1012)) + (PORT datad (353:353:353) (413:413:413)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1767:1767:1767) (1800:1800:1800)) + (PORT ena (1163:1163:1163) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1768:1768:1768) (1802:1802:1802)) + (PORT ena (1213:1213:1213) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (711:711:711)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (622:622:622) (656:656:656)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT asdata (1910:1910:1910) (1926:1926:1926)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1990:1990:1990) (2006:2006:2006)) + (PORT ena (1196:1196:1196) (1165:1165:1165)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (426:426:426) (514:514:514)) + (PORT datab (497:497:497) (558:558:558)) + (PORT datad (621:621:621) (655:655:655)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1990:1990:1990) (2008:2008:2008)) + (PORT ena (1256:1256:1256) (1255:1255:1255)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1099:1099:1099) (1111:1111:1111)) + (PORT datab (882:882:882) (895:895:895)) + (PORT datac (824:824:824) (834:834:834)) + (PORT datad (1128:1128:1128) (1146:1146:1146)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (715:715:715)) + (PORT datab (1096:1096:1096) (1104:1104:1104)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (950:950:950) (981:981:981)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (982:982:982) (1034:1034:1034)) + (PORT datab (1288:1288:1288) (1327:1327:1327)) + (PORT datad (844:844:844) (907:907:907)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1476:1476:1476) (1478:1478:1478)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (2137:2137:2137) (2157:2157:2157)) + (PORT ena (1186:1186:1186) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (327:327:327)) + (PORT datab (957:957:957) (993:993:993)) + (PORT datad (879:879:879) (921:921:921)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (701:701:701)) + (PORT datab (651:651:651) (704:704:704)) + (PORT datac (614:614:614) (661:661:661)) + (PORT datad (632:632:632) (653:653:653)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (636:636:636)) + (PORT datab (654:654:654) (706:706:706)) + (PORT datac (844:844:844) (895:895:895)) + (PORT datad (172:172:172) (196:196:196)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1377:1377:1377) (1408:1408:1408)) + (PORT datab (643:643:643) (692:692:692)) + (PORT datac (543:543:543) (567:567:567)) + (PORT datad (373:373:373) (401:401:401)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1137:1137:1137) (1157:1157:1157)) + (PORT ena (1164:1164:1164) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1624:1624:1624) (1648:1648:1648)) + (PORT datab (588:588:588) (621:621:621)) + (PORT datad (575:575:575) (600:600:600)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1185:1185:1185) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (215:215:215) (292:292:292)) + (PORT datad (565:565:565) (592:592:592)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (589:589:589)) + (PORT datab (711:711:711) (747:747:747)) + (PORT datac (381:381:381) (458:458:458)) + (PORT datad (623:623:623) (682:682:682)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (475:475:475) (521:521:521)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (519:519:519) (550:550:550)) + (PORT datad (1502:1502:1502) (1569:1569:1569)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[12\]) + (DELAY + (ABSOLUTE + (PORT datab (903:903:903) (949:949:949)) + (PORT datac (795:795:795) (815:815:815)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1559:1559:1559)) + (PORT ena (1762:1762:1762) (1780:1780:1780)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (591:591:591)) + (PORT datab (712:712:712) (749:749:749)) + (PORT datac (380:380:380) (454:454:454)) + (PORT datad (624:624:624) (682:682:682)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (427:427:427) (508:508:508)) + (PORT datad (187:187:187) (219:219:219)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1185:1185:1185) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (963:963:963) (1022:1022:1022)) + (PORT ena (1546:1546:1546) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (962:962:962) (1021:1021:1021)) + (PORT ena (1446:1446:1446) (1455:1455:1455)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (1000:1000:1000) (1057:1057:1057)) + (PORT datab (969:969:969) (1008:1008:1008)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (678:678:678) (714:714:714)) + (PORT ena (1475:1475:1475) (1479:1479:1479)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (678:678:678) (714:714:714)) + (PORT ena (1485:1485:1485) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (982:982:982)) + (PORT datab (937:937:937) (981:981:981)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (893:893:893) (927:927:927)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1710:1710:1710) (1763:1763:1763)) + (PORT ena (1196:1196:1196) (1165:1165:1165)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (700:700:700)) + (PORT datab (501:501:501) (558:558:558)) + (PORT datad (620:620:620) (655:655:655)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1710:1710:1710) (1761:1761:1761)) + (PORT ena (1256:1256:1256) (1255:1255:1255)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1133:1133:1133) (1144:1144:1144)) + (PORT datab (705:705:705) (763:763:763)) + (PORT datac (1078:1078:1078) (1114:1114:1114)) + (PORT datad (188:188:188) (223:223:223)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1291:1291:1291)) + (PORT datab (808:808:808) (845:845:845)) + (PORT datac (818:818:818) (868:868:868)) + (PORT datad (804:804:804) (813:813:813)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1247:1247:1247) (1330:1330:1330)) + (PORT datab (985:985:985) (1056:1056:1056)) + (PORT datac (647:647:647) (686:686:686)) + (PORT datad (1360:1360:1360) (1453:1453:1453)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (388:388:388)) + (PORT datab (889:889:889) (946:946:946)) + (PORT datac (612:612:612) (646:646:646)) + (PORT datad (933:933:933) (987:987:987)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (955:955:955) (970:970:970)) + (PORT datab (287:287:287) (346:346:346)) + (PORT datad (853:853:853) (856:856:856)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) + (DELAY + (ABSOLUTE + (PORT datab (285:285:285) (345:345:345)) + (PORT datad (854:854:854) (856:856:856)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) + (DELAY + (ABSOLUTE + (PORT dataa (2000:2000:2000) (2162:2162:2162)) + (PORT datac (1090:1090:1090) (1122:1122:1122)) + (PORT datad (1323:1323:1323) (1497:1497:1497)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (967:967:967)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (888:888:888) (937:937:937)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datac (698:698:698) (765:765:765)) + (PORT datad (855:855:855) (908:908:908)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (224:224:224) (265:265:265)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1323:1323:1323) (1378:1378:1378)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1541:1541:1541) (1629:1629:1629)) + (PORT datab (1591:1591:1591) (1670:1670:1670)) + (PORT datac (857:857:857) (918:918:918)) + (PORT datad (398:398:398) (467:467:467)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (445:445:445) (507:507:507)) + (PORT datab (587:587:587) (606:606:606)) + (PORT datac (849:849:849) (909:909:909)) + (PORT datad (239:239:239) (282:282:282)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (662:662:662) (679:679:679)) + (PORT ena (1474:1474:1474) (1475:1475:1475)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (663:663:663)) + (PORT datab (1117:1117:1117) (1151:1151:1151)) + (PORT datad (847:847:847) (870:870:870)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (662:662:662)) + (PORT datab (1316:1316:1316) (1369:1369:1369)) + (PORT datac (209:209:209) (247:247:247)) + (PORT datad (841:841:841) (848:848:848)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datac (252:252:252) (311:311:311)) + (PORT datad (347:347:347) (371:371:371)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (419:419:419)) + (PORT datab (1011:1011:1011) (1072:1072:1072)) + (PORT datac (1687:1687:1687) (1750:1750:1750)) + (PORT datad (1175:1175:1175) (1233:1233:1233)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (586:586:586) (607:607:607)) + (PORT datac (918:918:918) (934:934:934)) + (PORT datad (852:852:852) (859:859:859)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) + (DELAY + (ABSOLUTE + (PORT datab (593:593:593) (612:612:612)) + (PORT datac (250:250:250) (307:307:307)) + (PORT datad (858:858:858) (860:860:860)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (921:921:921)) + (PORT datab (1005:1005:1005) (1064:1064:1064)) + (PORT datac (1691:1691:1691) (1755:1755:1755)) + (PORT datad (1168:1168:1168) (1225:1225:1225)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (957:957:957) (1024:1024:1024)) + (PORT datab (1075:1075:1075) (1139:1139:1139)) + (PORT datac (867:867:867) (925:925:925)) + (PORT datad (646:646:646) (678:678:678)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (731:731:731)) + (PORT datab (660:660:660) (692:692:692)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (913:913:913) (955:955:955)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (725:725:725)) + (PORT datab (663:663:663) (713:713:713)) + (PORT datac (627:627:627) (659:659:659)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1454:1454:1454) (1593:1593:1593)) + (PORT datab (927:927:927) (972:972:972)) + (PORT datac (587:587:587) (604:604:604)) + (PORT datad (1544:1544:1544) (1686:1686:1686)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (951:951:951)) + (PORT datab (989:989:989) (1033:1033:1033)) + (PORT datac (1425:1425:1425) (1436:1436:1436)) + (PORT datad (651:651:651) (670:670:670)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1259:1259:1259) (1306:1306:1306)) + (PORT datab (621:621:621) (668:668:668)) + (PORT datac (1465:1465:1465) (1520:1520:1520)) + (PORT datad (628:628:628) (636:636:636)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nop3pla68M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1184:1184:1184) (1281:1281:1281)) + (PORT datab (1244:1244:1244) (1294:1294:1294)) + (PORT datac (877:877:877) (941:941:941)) + (PORT datad (194:194:194) (218:218:218)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1260:1260:1260) (1306:1306:1306)) + (PORT datab (1263:1263:1263) (1349:1349:1349)) + (PORT datac (2128:2128:2128) (2214:2214:2214)) + (PORT datad (1440:1440:1440) (1511:1511:1511)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (408:408:408)) + (PORT datab (654:654:654) (669:669:669)) + (PORT datac (357:357:357) (377:377:377)) + (PORT datad (316:316:316) (335:335:335)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (178:178:178) (216:216:216)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (392:392:392)) + (PORT datab (337:337:337) (369:369:369)) + (PORT datac (870:870:870) (876:876:876)) + (PORT datad (609:609:609) (634:634:634)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (248:248:248) (293:293:293)) + (PORT datab (893:893:893) (901:901:901)) + (PORT datac (366:366:366) (393:393:393)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (998:998:998)) + (PORT datab (218:218:218) (255:255:255)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (610:610:610) (646:646:646)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1366:1366:1366) (1381:1381:1381)) + (PORT datab (674:674:674) (719:719:719)) + (PORT datac (640:640:640) (688:688:688)) + (PORT datad (913:913:913) (955:955:955)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~7) + (DELAY + (ABSOLUTE + (PORT datac (625:625:625) (661:661:661)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (699:699:699)) + (PORT datab (247:247:247) (288:288:288)) + (PORT datac (828:828:828) (858:858:858)) + (PORT datad (843:843:843) (860:860:860)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (421:421:421) (508:508:508)) + (PORT datab (867:867:867) (892:892:892)) + (PORT datac (604:604:604) (651:651:651)) + (PORT datad (566:566:566) (585:585:585)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1180:1180:1180) (1252:1252:1252)) + (PORT datab (574:574:574) (587:587:587)) + (PORT datac (861:861:861) (886:886:886)) + (PORT datad (1797:1797:1797) (1884:1884:1884)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1183:1183:1183) (1255:1255:1255)) + (PORT datab (572:572:572) (588:588:588)) + (PORT datac (858:858:858) (886:886:886)) + (PORT datad (1798:1798:1798) (1887:1887:1887)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (298:298:298)) + (PORT datab (554:554:554) (571:571:571)) + (PORT datac (228:228:228) (266:266:266)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (265:265:265)) + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (214:214:214) (259:259:259)) + (PORT datad (204:204:204) (235:235:235)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (274:274:274)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT datab (825:825:825) (834:834:834)) + (PORT datac (556:556:556) (572:572:572)) + (PORT datad (330:330:330) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT asdata (690:690:690) (711:711:711)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1043:1043:1043) (1079:1079:1079)) + (PORT datab (664:664:664) (707:707:707)) + (PORT datac (633:633:633) (680:680:680)) + (PORT datad (584:584:584) (611:611:611)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datac (625:625:625) (657:657:657)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (992:992:992) (1100:1100:1100)) + (PORT datab (1591:1591:1591) (1671:1671:1671)) + (PORT datac (857:857:857) (917:917:917)) + (PORT datad (421:421:421) (491:491:491)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (710:710:710) (805:805:805)) + (PORT datad (847:847:847) (895:895:895)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (943:943:943)) + (PORT datab (1389:1389:1389) (1433:1433:1433)) + (PORT datac (204:204:204) (242:242:242)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (452:452:452) (514:514:514)) + (PORT datab (270:270:270) (325:325:325)) + (PORT datad (605:605:605) (628:628:628)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (886:886:886)) + (PORT datab (812:812:812) (875:875:875)) + (PORT datac (607:607:607) (626:626:626)) + (PORT datad (617:617:617) (630:630:630)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (227:227:227) (270:270:270)) + (PORT datac (843:843:843) (913:913:913)) + (PORT datad (662:662:662) (672:672:672)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1717:1717:1717) (1813:1813:1813)) + (PORT ena (1475:1475:1475) (1479:1479:1479)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1717:1717:1717) (1813:1813:1813)) + (PORT ena (1485:1485:1485) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (920:920:920) (976:976:976)) + (PORT datab (932:932:932) (975:975:975)) + (PORT datad (214:214:214) (282:282:282)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1677:1677:1677) (1751:1751:1751)) + (PORT ena (1546:1546:1546) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1074:1074:1074) (1150:1150:1150)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1446:1446:1446) (1455:1455:1455)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (997:997:997) (1053:1053:1053)) + (PORT datab (967:967:967) (1008:1008:1008)) + (PORT datad (216:216:216) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1419:1419:1419) (1492:1492:1492)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1488:1488:1488) (1562:1562:1562)) + (PORT datab (663:663:663) (712:712:712)) + (PORT datad (1638:1638:1638) (1752:1752:1752)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (957:957:957) (989:989:989)) + (PORT ena (1186:1186:1186) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (956:956:956) (987:987:987)) + (PORT ena (1476:1476:1476) (1478:1478:1478)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (970:970:970)) + (PORT datab (956:956:956) (998:998:998)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT asdata (1182:1182:1182) (1255:1255:1255)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1429:1429:1429) (1502:1502:1502)) + (PORT ena (1196:1196:1196) (1165:1165:1165)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (689:689:689)) + (PORT datab (456:456:456) (531:531:531)) + (PORT datad (627:627:627) (664:664:664)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1431:1431:1431) (1502:1502:1502)) + (PORT ena (1163:1163:1163) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1431:1431:1431) (1503:1503:1503)) + (PORT ena (1213:1213:1213) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (706:706:706)) + (PORT datab (239:239:239) (320:320:320)) + (PORT datad (626:626:626) (662:662:662)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1427:1427:1427) (1500:1500:1500)) + (PORT ena (1256:1256:1256) (1255:1255:1255)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (983:983:983) (1033:1033:1033)) + (PORT datab (1290:1290:1290) (1329:1329:1329)) + (PORT datad (808:808:808) (878:878:878)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (403:403:403)) + (PORT datab (862:862:862) (914:914:914)) + (PORT datac (576:576:576) (606:606:606)) + (PORT datad (807:807:807) (828:828:828)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (614:614:614)) + (PORT datab (839:839:839) (859:859:859)) + (PORT datac (619:619:619) (659:659:659)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[14\]) + (DELAY + (ABSOLUTE + (PORT datab (902:902:902) (944:944:944)) + (PORT datad (877:877:877) (887:887:887)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1559:1559:1559)) + (PORT ena (1762:1762:1762) (1780:1780:1780)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (510:510:510)) + (PORT datab (213:213:213) (259:259:259)) + (PORT datac (584:584:584) (636:636:636)) + (PORT datad (673:673:673) (710:710:710)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (761:761:761) (801:801:801)) + (PORT ena (1203:1203:1203) (1189:1189:1189)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (621:621:621) (663:663:663)) + (PORT datad (560:560:560) (586:586:586)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (538:538:538) (569:569:569)) + (PORT ena (1185:1185:1185) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (606:606:606) (648:648:648)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (395:395:395) (466:466:466)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1539:1539:1539) (1609:1609:1609)) + (PORT datab (534:534:534) (553:553:553)) + (PORT datac (434:434:434) (481:481:481)) + (PORT datad (345:345:345) (369:369:369)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (1357:1357:1357) (1408:1408:1408)) + (PORT datac (420:420:420) (460:460:460)) + (PORT datad (208:208:208) (240:240:240)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1018:1018:1018) (1067:1067:1067)) + (PORT datab (879:879:879) (898:898:898)) + (PORT datac (1268:1268:1268) (1345:1345:1345)) + (PORT datad (1057:1057:1057) (1068:1068:1068)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (685:685:685) (721:721:721)) + (PORT datab (1094:1094:1094) (1099:1099:1099)) + (PORT datac (994:994:994) (1030:1030:1030)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (743:743:743) (837:837:837)) + (PORT datac (199:199:199) (234:234:234)) + (PORT datad (227:227:227) (256:256:256)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (882:882:882) (933:933:933)) + (PORT datac (1359:1359:1359) (1403:1403:1403)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (674:674:674)) + (PORT datab (413:413:413) (463:463:463)) + (PORT datac (855:855:855) (912:912:912)) + (PORT datad (242:242:242) (285:285:285)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (728:728:728)) + (PORT datab (860:860:860) (903:903:903)) + (PORT datac (2033:2033:2033) (2070:2070:2070)) + (PORT datad (836:836:836) (928:928:928)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (445:445:445)) + (PORT datab (1316:1316:1316) (1370:1370:1370)) + (PORT datac (609:609:609) (627:627:627)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (915:915:915)) + (PORT datab (354:354:354) (389:389:389)) + (PORT datac (610:610:610) (623:623:623)) + (PORT datad (640:640:640) (654:654:654)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (949:949:949)) + (PORT datab (600:600:600) (621:621:621)) + (PORT datac (196:196:196) (230:230:230)) + (PORT datad (809:809:809) (832:832:832)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (744:744:744)) + (PORT datab (874:874:874) (931:931:931)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (217:217:217) (255:255:255)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1036:1036:1036)) + (PORT datab (1285:1285:1285) (1323:1323:1323)) + (PORT datad (1367:1367:1367) (1447:1447:1447)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1476:1476:1476) (1478:1478:1478)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (905:905:905) (935:935:935)) + (PORT ena (1186:1186:1186) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (326:326:326)) + (PORT datab (959:959:959) (996:996:996)) + (PORT datad (880:880:880) (920:920:920)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (966:966:966) (1015:1015:1015)) + (PORT ena (1163:1163:1163) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (969:969:969) (1017:1017:1017)) + (PORT ena (1213:1213:1213) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (711:711:711)) + (PORT datab (378:378:378) (450:450:450)) + (PORT datad (620:620:620) (653:653:653)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (1052:1052:1052) (1055:1055:1055)) + (PORT datad (328:328:328) (344:344:344)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1215:1215:1215) (1257:1257:1257)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1488:1488:1488) (1562:1562:1562)) + (PORT datab (662:662:662) (713:713:713)) + (PORT datad (1636:1636:1636) (1747:1747:1747)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (846:846:846)) + (PORT datab (915:915:915) (949:949:949)) + (PORT datac (338:338:338) (359:359:359)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (644:644:644)) + (PORT datab (645:645:645) (697:697:697)) + (PORT datac (1345:1345:1345) (1373:1373:1373)) + (PORT datad (375:375:375) (406:406:406)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (866:866:866) (878:878:878)) + (PORT ena (1164:1164:1164) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (608:608:608)) + (PORT datab (622:622:622) (664:664:664)) + (PORT datac (425:425:425) (498:498:498)) + (PORT datad (563:563:563) (590:590:590)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (432:432:432) (520:520:520)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datad (584:584:584) (613:613:613)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1538:1538:1538) (1606:1606:1606)) + (PORT datab (586:586:586) (605:605:605)) + (PORT datac (435:435:435) (481:481:481)) + (PORT datad (348:348:348) (372:372:372)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[13\]) + (DELAY + (ABSOLUTE + (PORT datab (902:902:902) (948:948:948)) + (PORT datac (775:775:775) (783:783:783)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1559:1559:1559)) + (PORT ena (1762:1762:1762) (1780:1780:1780)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) + (DELAY + (ABSOLUTE + (PORT datab (711:711:711) (744:744:744)) + (PORT datac (392:392:392) (466:466:466)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[15\]) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (887:887:887)) + (PORT datad (867:867:867) (907:907:907)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1559:1559:1559)) + (PORT ena (1762:1762:1762) (1780:1780:1780)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_16) + (DELAY + (ABSOLUTE + (PORT dataa (1143:1143:1143) (1199:1199:1199)) + (PORT datab (399:399:399) (474:474:474)) + (PORT datac (670:670:670) (691:691:691)) + (PORT datad (1153:1153:1153) (1200:1200:1200)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (213:213:213) (257:257:257)) + (PORT datac (548:548:548) (605:605:605)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1542:1542:1542) (1611:1611:1611)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (431:431:431) (485:485:485)) + (PORT datad (526:526:526) (542:542:542)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (638:638:638)) + (PORT datab (400:400:400) (442:442:442)) + (PORT datac (1344:1344:1344) (1372:1372:1372)) + (PORT datad (551:551:551) (569:569:569)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1203:1203:1203) (1249:1249:1249)) + (PORT datab (882:882:882) (895:895:895)) + (PORT datac (567:567:567) (583:583:583)) + (PORT datad (1058:1058:1058) (1064:1064:1064)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (721:721:721)) + (PORT datab (1094:1094:1094) (1103:1103:1103)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (813:813:813) (871:871:871)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (450:450:450) (491:491:491)) + (PORT datab (1860:1860:1860) (1955:1955:1955)) + (PORT datac (1054:1054:1054) (1101:1101:1101)) + (PORT datad (244:244:244) (315:315:315)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (807:807:807) (861:861:861)) + (PORT datab (385:385:385) (404:404:404)) + (PORT datac (252:252:252) (308:308:308)) + (PORT datad (343:343:343) (357:357:357)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (408:408:408) (431:431:431)) + (PORT datab (591:591:591) (610:610:610)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (857:857:857) (859:859:859)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (436:436:436)) + (PORT datab (285:285:285) (345:345:345)) + (PORT datad (856:856:856) (862:862:862)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (926:926:926)) + (PORT datab (716:716:716) (777:777:777)) + (PORT datad (886:886:886) (910:910:910)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (703:703:703)) + (PORT datab (606:606:606) (624:624:624)) + (PORT datac (249:249:249) (307:307:307)) + (PORT datad (554:554:554) (572:572:572)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (885:885:885) (899:899:899)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (581:581:581) (608:608:608)) + (PORT datab (718:718:718) (786:786:786)) + (PORT datac (966:966:966) (1066:1066:1066)) + (PORT datad (995:995:995) (1046:1046:1046)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (723:723:723)) + (PORT datab (618:618:618) (649:649:649)) + (PORT datac (628:628:628) (663:663:663)) + (PORT datad (356:356:356) (387:387:387)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (457:457:457) (532:532:532)) + (PORT datab (870:870:870) (896:896:896)) + (PORT datac (519:519:519) (536:536:536)) + (PORT datad (399:399:399) (466:466:466)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (415:415:415) (497:497:497)) + (PORT datab (1023:1023:1023) (1072:1072:1072)) + (PORT datac (819:819:819) (866:866:866)) + (PORT datad (625:625:625) (636:636:636)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (375:375:375) (399:399:399)) + (PORT datab (1228:1228:1228) (1318:1318:1318)) + (PORT datac (696:696:696) (757:757:757)) + (PORT datad (886:886:886) (912:912:912)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT datac (383:383:383) (414:414:414)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (663:663:663)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (585:585:585) (600:600:600)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (456:456:456)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (200:200:200) (237:237:237)) + (PORT datad (328:328:328) (349:349:349)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) + (DELAY + (ABSOLUTE + (PORT datab (646:646:646) (675:675:675)) + (PORT datac (810:810:810) (825:825:825)) + (PORT datad (655:655:655) (668:668:668)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (861:861:861)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datad (350:350:350) (366:366:366)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (275:275:275)) + (PORT datab (668:668:668) (691:691:691)) + (PORT datac (842:842:842) (879:879:879)) + (PORT datad (931:931:931) (964:964:964)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (946:946:946) (1005:1005:1005)) + (PORT datab (216:216:216) (260:260:260)) + (PORT datac (547:547:547) (557:557:557)) + (PORT datad (1236:1236:1236) (1277:1277:1277)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1336:1336:1336) (1342:1342:1342)) + (PORT datab (2282:2282:2282) (2366:2366:2366)) + (PORT datac (1180:1180:1180) (1239:1239:1239)) + (PORT datad (1331:1331:1331) (1363:1363:1363)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (622:622:622)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (1252:1252:1252) (1287:1287:1287)) + (PORT datad (952:952:952) (991:991:991)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (531:531:531) (556:556:556)) + (PORT datab (854:854:854) (864:864:864)) + (PORT datac (547:547:547) (558:558:558)) + (PORT datad (610:610:610) (649:649:649)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~4) + (DELAY + (ABSOLUTE + (PORT datab (844:844:844) (872:872:872)) + (PORT datac (829:829:829) (842:842:842)) + (PORT datad (1173:1173:1173) (1229:1229:1229)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1798:1798:1798) (1899:1899:1899)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datac (1834:1834:1834) (1965:1965:1965)) + (PORT datad (1601:1601:1601) (1748:1748:1748)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (1649:1649:1649) (1760:1760:1760)) + (PORT datac (1397:1397:1397) (1433:1433:1433)) + (PORT datad (2275:2275:2275) (2370:2370:2370)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datad (181:181:181) (211:211:211)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (362:362:362)) + (PORT datab (1863:1863:1863) (1958:1958:1958)) + (PORT datac (1087:1087:1087) (1133:1133:1133)) + (PORT datad (246:246:246) (318:318:318)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (359:359:359)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT datab (952:952:952) (1016:1016:1016)) + (PORT datac (1076:1076:1076) (1122:1122:1122)) + (PORT datad (632:632:632) (661:661:661)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1608:1608:1608) (1639:1639:1639)) + (PORT datab (964:964:964) (1002:1002:1002)) + (PORT datac (1030:1030:1030) (1064:1064:1064)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (694:694:694)) + (PORT datab (286:286:286) (344:344:344)) + (PORT datac (201:201:201) (239:239:239)) + (PORT datad (549:549:549) (567:567:567)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (884:884:884) (897:897:897)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (436:436:436) (530:530:530)) + (PORT datab (1590:1590:1590) (1672:1672:1672)) + (PORT datac (858:858:858) (922:922:922)) + (PORT datad (599:599:599) (660:660:660)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (669:669:669) (691:691:691)) + (PORT ena (1535:1535:1535) (1542:1542:1542)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (447:447:447) (510:510:510)) + (PORT datab (586:586:586) (606:606:606)) + (PORT datac (850:850:850) (911:911:911)) + (PORT datad (240:240:240) (284:284:284)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (912:912:912)) + (PORT datab (367:367:367) (387:387:387)) + (PORT datad (598:598:598) (630:630:630)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (859:859:859)) + (PORT datab (669:669:669) (685:685:685)) + (PORT datac (574:574:574) (583:583:583)) + (PORT datad (342:342:342) (354:354:354)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (991:991:991)) + (PORT datab (1072:1072:1072) (1137:1137:1137)) + (PORT datac (580:580:580) (650:650:650)) + (PORT datad (642:642:642) (673:673:673)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (726:726:726)) + (PORT datab (999:999:999) (1052:1052:1052)) + (PORT datac (627:627:627) (664:664:664)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (723:723:723)) + (PORT datab (665:665:665) (708:708:708)) + (PORT datac (575:575:575) (604:604:604)) + (PORT datad (972:972:972) (1013:1013:1013)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT datac (628:628:628) (662:662:662)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (434:434:434) (528:528:528)) + (PORT datab (591:591:591) (625:625:625)) + (PORT datac (435:435:435) (513:513:513)) + (PORT datad (830:830:830) (856:856:856)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (249:249:249) (304:304:304)) + (PORT datab (554:554:554) (570:570:570)) + (PORT datac (554:554:554) (586:586:586)) + (PORT datad (1081:1081:1081) (1087:1087:1087)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (892:892:892)) + (PORT datab (1082:1082:1082) (1083:1083:1083)) + (PORT datac (801:801:801) (808:808:808)) + (PORT datad (782:782:782) (795:795:795)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~36) + (DELAY + (ABSOLUTE + (PORT datab (224:224:224) (272:272:272)) + (PORT datac (217:217:217) (261:261:261)) + (PORT datad (831:831:831) (859:859:859)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~35) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (257:257:257)) + (PORT datab (225:225:225) (273:273:273)) + (PORT datac (217:217:217) (258:258:258)) + (PORT datad (832:832:832) (857:857:857)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1505:1505:1505) (1591:1591:1591)) + (PORT datab (1459:1459:1459) (1480:1480:1480)) + (PORT datac (1862:1862:1862) (1880:1880:1880)) + (PORT datad (1327:1327:1327) (1360:1360:1360)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1108:1108:1108) (1137:1137:1137)) + (PORT datab (1392:1392:1392) (1450:1450:1450)) + (PORT datac (798:798:798) (814:814:814)) + (PORT datad (1298:1298:1298) (1369:1369:1369)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1937:1937:1937) (2026:2026:2026)) + (PORT datab (212:212:212) (256:256:256)) + (PORT datac (1953:1953:1953) (2056:2056:2056)) + (PORT datad (1615:1615:1615) (1688:1688:1688)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1125:1125:1125) (1152:1152:1152)) + (PORT datab (370:370:370) (396:396:396)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (824:824:824) (863:863:863)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~17) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (528:528:528) (540:540:540)) + (PORT datad (580:580:580) (593:593:593)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) + (DELAY + (ABSOLUTE + (PORT datab (1770:1770:1770) (1810:1810:1810)) + (PORT datac (1173:1173:1173) (1220:1220:1220)) + (PORT datad (1440:1440:1440) (1461:1461:1461)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (340:340:340)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (254:254:254) (313:313:313)) + (PORT datad (1200:1200:1200) (1271:1271:1271)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) + (DELAY + (ABSOLUTE + (PORT dataa (2211:2211:2211) (2401:2401:2401)) + (PORT datab (1578:1578:1578) (1721:1721:1721)) + (PORT datac (1756:1756:1756) (1850:1850:1850)) + (PORT datad (857:857:857) (888:888:888)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (1859:1859:1859) (1955:1955:1955)) + (PORT datac (605:605:605) (631:631:631)) + (PORT datad (944:944:944) (992:992:992)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1804:1804:1804) (1902:1902:1902)) + (PORT datab (1429:1429:1429) (1461:1461:1461)) + (PORT datac (1430:1430:1430) (1464:1464:1464)) + (PORT datad (2319:2319:2319) (2472:2472:2472)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1547:1547:1547) (1642:1642:1642)) + (PORT datab (1225:1225:1225) (1267:1267:1267)) + (PORT datac (1428:1428:1428) (1462:1462:1462)) + (PORT datad (1636:1636:1636) (1711:1711:1711)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1464:1464:1464) (1499:1499:1499)) + (PORT datab (684:684:684) (724:724:724)) + (PORT datac (1191:1191:1191) (1233:1233:1233)) + (PORT datad (1662:1662:1662) (1693:1693:1693)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (671:671:671)) + (PORT datab (2007:2007:2007) (2122:2122:2122)) + (PORT datac (1547:1547:1547) (1649:1649:1649)) + (PORT datad (2319:2319:2319) (2472:2472:2472)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1548:1548:1548) (1643:1643:1643)) + (PORT datab (680:680:680) (721:721:721)) + (PORT datac (1534:1534:1534) (1622:1622:1622)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (332:332:332)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (681:681:681) (728:728:728)) + (PORT datac (2002:2002:2002) (2034:2034:2034)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (378:378:378)) + (PORT datab (375:375:375) (401:401:401)) + (PORT datac (317:317:317) (348:348:348)) + (PORT datad (875:875:875) (912:912:912)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~37) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (698:698:698)) + (PORT datab (643:643:643) (669:669:669)) + (PORT datac (1186:1186:1186) (1232:1232:1232)) + (PORT datad (366:366:366) (388:388:388)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (986:986:986)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (1404:1404:1404) (1439:1439:1439)) + (PORT datad (619:619:619) (649:649:649)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (704:704:704)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1184:1184:1184) (1224:1224:1224)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (680:680:680)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (581:581:581) (598:598:598)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1504:1504:1504) (1590:1590:1590)) + (PORT datab (1459:1459:1459) (1480:1480:1480)) + (PORT datac (1045:1045:1045) (1092:1092:1092)) + (PORT datad (1326:1326:1326) (1360:1360:1360)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (927:927:927) (983:983:983)) + (PORT datac (900:900:900) (967:967:967)) + (PORT datad (2255:2255:2255) (2330:2330:2330)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1308:1308:1308) (1389:1389:1389)) + (PORT datab (1282:1282:1282) (1317:1317:1317)) + (PORT datac (903:903:903) (968:968:968)) + (PORT datad (1147:1147:1147) (1224:1224:1224)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1465:1465:1465) (1478:1478:1478)) + (PORT datab (991:991:991) (1033:1033:1033)) + (PORT datac (382:382:382) (406:406:406)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (399:399:399)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (523:523:523) (528:528:528)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (896:896:896)) + (PORT datab (650:650:650) (675:675:675)) + (PORT datac (342:342:342) (365:365:365)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (882:882:882)) + (PORT datab (639:639:639) (683:683:683)) + (PORT datac (811:811:811) (813:813:813)) + (PORT datad (1234:1234:1234) (1284:1284:1284)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (704:704:704)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (181:181:181) (212:212:212)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (554:554:554) (564:564:564)) + (PORT datac (178:178:178) (216:216:216)) + (PORT datad (584:584:584) (600:600:600)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (473:473:473) (549:549:549)) + (PORT datab (1591:1591:1591) (1671:1671:1671)) + (PORT datac (998:998:998) (1082:1082:1082)) + (PORT datad (844:844:844) (897:897:897)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (726:726:726) (802:802:802)) + (PORT datac (204:204:204) (242:242:242)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (712:712:712)) + (PORT datab (1350:1350:1350) (1417:1417:1417)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (674:674:674)) + (PORT datab (413:413:413) (463:463:463)) + (PORT datac (854:854:854) (913:913:913)) + (PORT datad (244:244:244) (285:285:285)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (878:878:878)) + (PORT datab (1313:1313:1313) (1370:1370:1370)) + (PORT datac (768:768:768) (840:840:840)) + (PORT datad (753:753:753) (788:788:788)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (915:915:915)) + (PORT datab (354:354:354) (384:384:384)) + (PORT datac (570:570:570) (580:580:580)) + (PORT datad (640:640:640) (657:657:657)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (692:692:692)) + (PORT datab (288:288:288) (346:346:346)) + (PORT datad (853:853:853) (857:857:857)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (1027:1027:1027) (1080:1080:1080)) + (PORT datac (998:998:998) (1082:1082:1082)) + (PORT datad (598:598:598) (658:658:658)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (435:435:435) (524:524:524)) + (PORT datab (593:593:593) (621:621:621)) + (PORT datac (435:435:435) (509:509:509)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (867:867:867) (892:892:892)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (587:587:587) (604:604:604)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (302:302:302)) + (PORT datab (256:256:256) (302:302:302)) + (PORT datac (525:525:525) (539:539:539)) + (PORT datad (181:181:181) (211:211:211)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (426:426:426) (455:455:455)) + (PORT datab (394:394:394) (418:418:418)) + (PORT datac (381:381:381) (403:403:403)) + (PORT datad (335:335:335) (355:355:355)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (407:407:407)) + (PORT datab (215:215:215) (260:260:260)) + (PORT datac (587:587:587) (602:602:602)) + (PORT datad (179:179:179) (206:206:206)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (612:612:612) (629:629:629)) + (PORT datac (184:184:184) (224:224:224)) + (PORT datad (178:178:178) (206:206:206)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (558:558:558) (589:589:589)) + (PORT ena (1535:1535:1535) (1542:1542:1542)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (379:379:379) (448:448:448)) + (PORT datad (845:845:845) (867:867:867)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (961:961:961)) + (PORT datab (715:715:715) (786:786:786)) + (PORT datac (1555:1555:1555) (1630:1630:1630)) + (PORT datad (399:399:399) (466:466:466)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) + (DELAY + (ABSOLUTE + (PORT dataa (440:440:440) (500:500:500)) + (PORT datad (602:602:602) (625:625:625)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (810:810:810) (836:836:836)) + (PORT datab (1100:1100:1100) (1140:1140:1140)) + (PORT datac (379:379:379) (412:412:412)) + (PORT datad (895:895:895) (920:920:920)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (785:785:785) (808:808:808)) + (PORT datab (676:676:676) (693:693:693)) + (PORT datac (345:345:345) (369:369:369)) + (PORT datad (327:327:327) (345:345:345)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1107:1107:1107) (1118:1118:1118)) + (PORT datab (884:884:884) (901:901:901)) + (PORT datac (1027:1027:1027) (1078:1078:1078)) + (PORT datad (981:981:981) (1014:1014:1014)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (683:683:683)) + (PORT datab (1094:1094:1094) (1101:1101:1101)) + (PORT datac (530:530:530) (542:542:542)) + (PORT datad (658:658:658) (677:677:677)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (662:662:662)) + (PORT datab (676:676:676) (735:735:735)) + (PORT datac (1314:1314:1314) (1328:1328:1328)) + (PORT datad (1142:1142:1142) (1172:1172:1172)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1027:1027:1027) (1032:1032:1032)) + (PORT datab (1108:1108:1108) (1163:1163:1163)) + (PORT datad (1085:1085:1085) (1076:1076:1076)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_hf2) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (384:384:384) (458:458:458)) + (PORT datac (379:379:379) (440:440:440)) + (PORT datad (386:386:386) (446:446:446)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe) + (DELAY + (ABSOLUTE + (PORT dataa (990:990:990) (1041:1041:1041)) + (PORT datab (2280:2280:2280) (2375:2375:2375)) + (PORT datad (2190:2190:2190) (2361:2361:2361)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (329:329:329)) + (PORT datab (605:605:605) (655:655:655)) + (PORT datac (802:802:802) (820:820:820)) + (PORT datad (1419:1419:1419) (1423:1423:1423)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (1395:1395:1395) (1451:1451:1451)) + (PORT datad (182:182:182) (213:213:213)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1230:1230:1230) (1286:1286:1286)) + (PORT datab (947:947:947) (992:992:992)) + (PORT datac (1206:1206:1206) (1235:1235:1235)) + (PORT datad (1186:1186:1186) (1199:1199:1199)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (276:276:276) (346:346:346)) + (PORT datab (1765:1765:1765) (1806:1806:1806)) + (PORT datac (247:247:247) (305:305:305)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (671:671:671)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datac (1094:1094:1094) (1107:1107:1107)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (885:885:885)) + (PORT datab (910:910:910) (959:959:959)) + (PORT datac (827:827:827) (862:862:862)) + (PORT datad (816:816:816) (839:839:839)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (906:906:906)) + (PORT datab (202:202:202) (242:242:242)) + (PORT datac (630:630:630) (665:665:665)) + (PORT datad (625:625:625) (641:641:641)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (864:864:864)) + (PORT datab (205:205:205) (246:246:246)) + (PORT datac (885:885:885) (913:913:913)) + (PORT datad (176:176:176) (203:203:203)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (328:328:328)) + (PORT datab (1135:1135:1135) (1215:1215:1215)) + (PORT datad (1221:1221:1221) (1258:1258:1258)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (547:547:547) (582:582:582)) + (PORT ena (1248:1248:1248) (1256:1256:1256)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (923:923:923) (953:953:953)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (841:841:841) (847:847:847)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1256:1256:1256)) + (PORT datab (682:682:682) (747:747:747)) + (PORT datad (875:875:875) (945:945:945)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (625:625:625) (679:679:679)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (547:547:547) (582:582:582)) + (PORT ena (1275:1275:1275) (1314:1314:1314)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (787:787:787)) + (PORT datab (729:729:729) (781:781:781)) + (PORT datad (1021:1021:1021) (1061:1061:1061)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (680:680:680)) + (PORT datab (611:611:611) (638:638:638)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (412:412:412)) + (PORT datab (612:612:612) (639:639:639)) + (PORT datac (309:309:309) (325:325:325)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (262:262:262)) + (PORT datab (195:195:195) (234:234:234)) + (PORT datac (816:816:816) (831:831:831)) + (PORT datad (1118:1118:1118) (1134:1134:1134)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1241:1241:1241) (1251:1251:1251)) + (PORT ena (816:816:816) (813:813:813)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1096:1096:1096) (1126:1126:1126)) + (PORT datab (219:219:219) (259:259:259)) + (PORT datad (1117:1117:1117) (1141:1141:1141)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1252:1252:1252) (1240:1240:1240)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (624:624:624) (639:639:639)) + (PORT datac (666:666:666) (695:695:695)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (450:450:450)) + (PORT datab (626:626:626) (654:654:654)) + (PORT datac (1197:1197:1197) (1250:1250:1250)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (1110:1110:1110) (1140:1140:1140)) + (PORT datad (880:880:880) (895:895:895)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1592:1592:1592) (1568:1568:1568)) + (PORT ena (2023:2023:2023) (2039:2039:2039)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (1341:1341:1341) (1362:1362:1362)) + (PORT datad (370:370:370) (394:394:394)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1550:1550:1550)) + (PORT asdata (934:934:934) (951:951:951)) + (PORT clrn (1591:1591:1591) (1568:1568:1568)) + (PORT ena (2020:2020:2020) (2056:2056:2056)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (673:673:673)) + (PORT datab (614:614:614) (636:636:636)) + (PORT datac (590:590:590) (657:657:657)) + (PORT datad (665:665:665) (729:729:729)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (422:422:422) (513:513:513)) + (PORT datab (617:617:617) (639:639:639)) + (PORT datac (613:613:613) (666:666:666)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1222:1222:1222) (1224:1224:1224)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (537:537:537) (568:568:568)) + (PORT ena (1237:1237:1237) (1220:1220:1220)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (950:950:950) (978:978:978)) + (PORT ena (1426:1426:1426) (1409:1409:1409)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (950:950:950) (976:976:976)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (248:248:248) (316:316:316)) + (PORT datab (1080:1080:1080) (1115:1115:1115)) + (PORT datad (355:355:355) (415:415:415)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT asdata (1773:1773:1773) (1846:1846:1846)) + (PORT ena (961:961:961) (970:970:970)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT asdata (1773:1773:1773) (1845:1845:1845)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (330:330:330)) + (PORT datab (244:244:244) (292:292:292)) + (PORT datad (211:211:211) (244:244:244)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1770:1770:1770) (1824:1824:1824)) + (PORT ena (1243:1243:1243) (1273:1273:1273)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1253:1253:1253)) + (PORT datab (675:675:675) (717:717:717)) + (PORT datad (833:833:833) (842:842:842)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1772:1772:1772) (1824:1824:1824)) + (PORT ena (1168:1168:1168) (1161:1161:1161)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (456:456:456)) + (PORT datab (195:195:195) (234:234:234)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1712:1712:1712) (1752:1752:1752)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1111:1111:1111) (1133:1133:1133)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (260:260:260) (327:327:327)) + (PORT datab (242:242:242) (325:325:325)) + (PORT datad (1377:1377:1377) (1480:1480:1480)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (953:953:953) (981:981:981)) + (PORT ena (1147:1147:1147) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (953:953:953) (981:981:981)) + (PORT ena (1248:1248:1248) (1262:1262:1262)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (661:661:661)) + (PORT datab (942:942:942) (999:999:999)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (849:849:849)) + (PORT datab (643:643:643) (660:660:660)) + (PORT datac (593:593:593) (636:636:636)) + (PORT datad (620:620:620) (630:630:630)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1220:1220:1220) (1238:1238:1238)) + (PORT ena (923:923:923) (907:907:907)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1221:1221:1221) (1239:1239:1239)) + (PORT ena (984:984:984) (983:983:983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (459:459:459)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datad (417:417:417) (449:449:449)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (699:699:699)) + (PORT datab (864:864:864) (869:869:869)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (896:896:896)) + (PORT datab (400:400:400) (430:430:430)) + (PORT datac (1133:1133:1133) (1187:1187:1187)) + (PORT datad (666:666:666) (703:703:703)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1465:1465:1465) (1521:1521:1521)) + (PORT datab (675:675:675) (709:709:709)) + (PORT datad (326:326:326) (344:344:344)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (635:635:635)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datad (606:606:606) (629:629:629)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (894:894:894)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1210:1210:1210) (1264:1264:1264)) + (PORT datad (217:217:217) (253:253:253)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[5\]) + (DELAY + (ABSOLUTE + (PORT dataa (1110:1110:1110) (1140:1140:1140)) + (PORT datad (625:625:625) (641:641:641)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1592:1592:1592) (1568:1568:1568)) + (PORT ena (2023:2023:2023) (2039:2039:2039)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1147:1147:1147) (1181:1181:1181)) + (PORT datab (1473:1473:1473) (1524:1524:1524)) + (PORT datac (1184:1184:1184) (1245:1245:1245)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (623:623:623)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (624:624:624) (671:671:671)) + (PORT datad (181:181:181) (212:212:212)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1466:1466:1466) (1490:1490:1490)) + (PORT ena (1426:1426:1426) (1409:1409:1409)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1462:1462:1462) (1486:1486:1486)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (308:308:308)) + (PORT datab (1080:1080:1080) (1120:1120:1120)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1220:1220:1220) (1250:1250:1250)) + (PORT ena (984:984:984) (983:983:983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1220:1220:1220) (1249:1249:1249)) + (PORT ena (923:923:923) (907:907:907)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (463:463:463)) + (PORT datab (449:449:449) (477:477:477)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1192:1192:1192) (1211:1211:1211)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1274:1274:1274) (1361:1361:1361)) + (PORT datab (1009:1009:1009) (1055:1055:1055)) + (PORT datad (895:895:895) (946:946:946)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1870:1870:1870) (1916:1916:1916)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (259:259:259) (322:322:322)) + (PORT datab (1137:1137:1137) (1215:1215:1215)) + (PORT datad (855:855:855) (880:880:880)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT asdata (970:970:970) (997:997:997)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (958:958:958) (996:996:996)) + (PORT ena (1275:1275:1275) (1314:1314:1314)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (1150:1150:1150) (1226:1226:1226)) + (PORT datab (725:725:725) (775:775:775)) + (PORT datad (1020:1020:1020) (1061:1061:1061)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (958:958:958) (999:999:999)) + (PORT ena (1248:1248:1248) (1256:1256:1256)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1712:1712:1712) (1752:1752:1752)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (1178:1178:1178) (1252:1252:1252)) + (PORT datab (676:676:676) (740:740:740)) + (PORT datad (656:656:656) (714:714:714)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (692:692:692)) + (PORT datab (643:643:643) (692:692:692)) + (PORT datac (572:572:572) (583:583:583)) + (PORT datad (312:312:312) (330:330:330)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1247:1247:1247) (1278:1278:1278)) + (PORT ena (1147:1147:1147) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (640:640:640) (678:678:678)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1248:1248:1248) (1262:1262:1262)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (660:660:660)) + (PORT datab (942:942:942) (998:998:998)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (649:649:649)) + (PORT datab (327:327:327) (355:355:355)) + (PORT datac (341:341:341) (363:363:363)) + (PORT datad (335:335:335) (355:355:355)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (685:685:685)) + (PORT datab (701:701:701) (738:738:738)) + (PORT datac (1136:1136:1136) (1185:1185:1185)) + (PORT datad (522:522:522) (540:540:540)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (848:848:848) (860:860:860)) + (PORT ena (1237:1237:1237) (1220:1220:1220)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1468:1468:1468) (1518:1518:1518)) + (PORT datab (384:384:384) (417:417:417)) + (PORT datad (643:643:643) (665:665:665)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1252:1252:1252) (1240:1240:1240)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (706:706:706) (734:734:734)) + (PORT datab (332:332:332) (360:360:360)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (874:874:874)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (1197:1197:1197) (1251:1251:1251)) + (PORT datad (383:383:383) (403:403:403)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[6\]) + (DELAY + (ABSOLUTE + (PORT datab (802:802:802) (828:828:828)) + (PORT datad (1064:1064:1064) (1089:1089:1089)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1592:1592:1592) (1568:1568:1568)) + (PORT ena (2023:2023:2023) (2039:2039:2039)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (275:275:275)) + (PORT datab (876:876:876) (905:905:905)) + (PORT datac (623:623:623) (669:669:669)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (251:251:251)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (579:579:579) (585:585:585)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (1246:1246:1246) (1247:1247:1247)) + (PORT datab (907:907:907) (936:936:936)) + (PORT datac (385:385:385) (451:451:451)) + (PORT datad (914:914:914) (972:972:972)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (894:894:894) (915:915:915)) + (PORT ena (1203:1203:1203) (1189:1189:1189)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (694:694:694)) + (PORT datab (622:622:622) (668:668:668)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1185:1185:1185) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (608:608:608) (648:648:648)) + (PORT datad (418:418:418) (490:490:490)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (406:406:406)) + (PORT datab (403:403:403) (433:433:433)) + (PORT datac (434:434:434) (479:479:479)) + (PORT datad (1502:1502:1502) (1569:1569:1569)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (656:656:656)) + (PORT datab (234:234:234) (278:278:278)) + (PORT datac (550:550:550) (571:571:571)) + (PORT datad (1321:1321:1321) (1374:1374:1374)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (909:909:909)) + (PORT datab (873:873:873) (928:928:928)) + (PORT datac (632:632:632) (677:677:677)) + (PORT datad (805:805:805) (833:833:833)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1808:1808:1808) (1853:1853:1853)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (572:572:572) (589:589:589)) + (PORT datad (220:220:220) (259:259:259)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (912:912:912)) + (PORT datad (809:809:809) (836:836:836)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (247:247:247)) + (PORT datab (1225:1225:1225) (1265:1265:1265)) + (PORT datac (878:878:878) (918:918:918)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (900:900:900)) + (PORT datab (1164:1164:1164) (1207:1207:1207)) + (PORT datac (1156:1156:1156) (1177:1177:1177)) + (PORT datad (612:612:612) (661:661:661)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1200:1200:1200) (1256:1256:1256)) + (PORT datab (676:676:676) (714:714:714)) + (PORT datad (1092:1092:1092) (1117:1117:1117)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (1354:1354:1354) (1395:1395:1395)) + (PORT ena (1263:1263:1263) (1252:1252:1252)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|db\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1299:1299:1299) (1381:1381:1381)) + (PORT datab (920:920:920) (933:933:933)) + (PORT datad (1369:1369:1369) (1414:1414:1414)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1193:1193:1193) (1215:1215:1215)) + (PORT ena (1426:1426:1426) (1409:1409:1409)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1187:1187:1187) (1217:1217:1217)) + (PORT ena (984:984:984) (983:983:983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1189:1189:1189) (1217:1217:1217)) + (PORT ena (923:923:923) (907:907:907)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (464:464:464)) + (PORT datab (450:450:450) (488:488:488)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (798:798:798) (832:832:832)) + (PORT datab (631:631:631) (666:666:666)) + (PORT datad (614:614:614) (639:639:639)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1168:1168:1168) (1161:1161:1161)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT asdata (992:992:992) (1028:1028:1028)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT asdata (990:990:990) (1027:1027:1027)) + (PORT ena (961:961:961) (970:970:970)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (459:459:459)) + (PORT datab (245:245:245) (293:293:293)) + (PORT datad (209:209:209) (240:240:240)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1181:1181:1181) (1196:1196:1196)) + (PORT ena (1712:1712:1712) (1752:1752:1752)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1178:1178:1178) (1193:1193:1193)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (264:264:264) (330:330:330)) + (PORT datab (1409:1409:1409) (1523:1523:1523)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (605:605:605) (642:642:642)) + (PORT datac (377:377:377) (418:418:418)) + (PORT datad (312:312:312) (331:331:331)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (676:676:676)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datac (522:522:522) (536:536:536)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1068:1068:1068) (1068:1068:1068)) + (PORT datab (1183:1183:1183) (1199:1199:1199)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (660:660:660) (693:693:693)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1154:1154:1154) (1163:1163:1163)) + (PORT ena (1237:1237:1237) (1220:1220:1220)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1467:1467:1467) (1517:1517:1517)) + (PORT datab (1185:1185:1185) (1225:1225:1225)) + (PORT datad (651:651:651) (673:673:673)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1252:1252:1252) (1240:1240:1240)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (370:370:370)) + (PORT datac (665:665:665) (694:694:694)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (420:420:420) (444:444:444)) + (PORT datab (220:220:220) (257:257:257)) + (PORT datac (1193:1193:1193) (1246:1246:1246)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[0\]) + (DELAY + (ABSOLUTE + (PORT datac (880:880:880) (936:936:936)) + (PORT datad (786:786:786) (788:788:788)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (1783:1783:1783) (1814:1814:1814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) + (DELAY + (ABSOLUTE + (PORT dataa (1451:1451:1451) (1493:1493:1493)) + (PORT datab (1095:1095:1095) (1151:1151:1151)) + (PORT datac (670:670:670) (690:690:690)) + (PORT datad (1103:1103:1103) (1138:1138:1138)) + (IOPATH dataa combout (350:350:350) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (746:746:746)) + (PORT datab (1400:1400:1400) (1451:1451:1451)) + (PORT datac (177:177:177) (214:214:214)) + (PORT datad (1354:1354:1354) (1397:1397:1397)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1252:1252:1252) (1240:1240:1240)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1457:1457:1457) (1516:1516:1516)) + (PORT ena (984:984:984) (983:983:983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1460:1460:1460) (1519:1519:1519)) + (PORT ena (923:923:923) (907:907:907)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (462:462:462)) + (PORT datab (449:449:449) (476:476:476)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (989:989:989) (1030:1030:1030)) + (PORT ena (1248:1248:1248) (1256:1256:1256)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT asdata (1378:1378:1378) (1437:1437:1437)) + (PORT ena (841:841:841) (847:847:847)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1254:1254:1254)) + (PORT datab (678:678:678) (743:743:743)) + (PORT datad (876:876:876) (941:941:941)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT asdata (1476:1476:1476) (1497:1497:1497)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1423:1423:1423) (1461:1461:1461)) + (PORT ena (1243:1243:1243) (1273:1273:1273)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (688:688:688) (768:768:768)) + (PORT datab (677:677:677) (714:714:714)) + (PORT datad (632:632:632) (658:658:658)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1422:1422:1422) (1461:1461:1461)) + (PORT ena (1168:1168:1168) (1161:1161:1161)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (461:461:461)) + (PORT datab (195:195:195) (234:234:234)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (911:911:911) (922:922:922)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (965:965:965)) + (PORT datab (1338:1338:1338) (1383:1383:1383)) + (PORT datac (840:840:840) (853:853:853)) + (PORT datad (840:840:840) (891:891:891)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (375:375:375)) + (PORT datab (619:619:619) (654:654:654)) + (PORT datad (319:319:319) (337:337:337)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (931:931:931) (962:962:962)) + (PORT ena (1426:1426:1426) (1409:1409:1409)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (587:587:587) (620:620:620)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (318:318:318)) + (PORT datab (1080:1080:1080) (1113:1113:1113)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1220:1220:1220) (1247:1247:1247)) + (PORT ena (1147:1147:1147) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (641:641:641) (675:675:675)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1248:1248:1248) (1262:1262:1262)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (665:665:665)) + (PORT datab (940:940:940) (1003:1003:1003)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (525:525:525) (543:543:543)) + (PORT datab (371:371:371) (391:391:391)) + (PORT datac (833:833:833) (839:839:839)) + (PORT datad (313:313:313) (322:322:322)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (814:814:814) (843:843:843)) + (PORT datab (573:573:573) (588:588:588)) + (PORT datac (1136:1136:1136) (1189:1189:1189)) + (PORT datad (665:665:665) (698:698:698)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (850:850:850) (858:858:858)) + (PORT ena (1237:1237:1237) (1220:1220:1220)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1467:1467:1467) (1517:1517:1517)) + (PORT datab (384:384:384) (414:414:414)) + (PORT datad (644:644:644) (664:664:664)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (707:707:707) (735:735:735)) + (PORT datac (217:217:217) (294:294:294)) + (PORT datad (334:334:334) (353:353:353)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (446:446:446)) + (PORT datab (1227:1227:1227) (1282:1282:1282)) + (PORT datac (178:178:178) (215:215:215)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (1340:1340:1340) (1359:1359:1359)) + (PORT datad (533:533:533) (544:544:544)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (565:565:565) (575:575:575)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1592:1592:1592) (1568:1568:1568)) + (PORT ena (2023:2023:2023) (2039:2039:2039)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (680:680:680) (745:745:745)) + (PORT datab (1138:1138:1138) (1179:1179:1179)) + (PORT datac (669:669:669) (689:689:689)) + (PORT datad (1408:1408:1408) (1445:1445:1445)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (1399:1399:1399) (1450:1450:1450)) + (PORT datac (1371:1371:1371) (1414:1414:1414)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (678:678:678)) + (PORT datab (615:615:615) (637:637:637)) + (PORT datac (592:592:592) (659:659:659)) + (PORT datad (667:667:667) (730:730:730)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (1239:1239:1239) (1295:1295:1295)) + (PORT datac (880:880:880) (914:914:914)) + (PORT datad (215:215:215) (249:249:249)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (368:368:368)) + (PORT datab (707:707:707) (740:740:740)) + (PORT datac (1132:1132:1132) (1184:1184:1184)) + (PORT datad (367:367:367) (391:391:391)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (630:630:630)) + (PORT datab (412:412:412) (440:440:440)) + (PORT datac (542:542:542) (555:555:555)) + (PORT datad (611:611:611) (637:637:637)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (274:274:274)) + (PORT datab (1115:1115:1115) (1142:1142:1142)) + (PORT datac (844:844:844) (866:866:866)) + (PORT datad (341:341:341) (362:362:362)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (246:246:246) (300:300:300)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (572:572:572) (590:590:590)) + (PORT datad (193:193:193) (218:218:218)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (744:744:744) (833:833:833)) + (PORT datac (206:206:206) (244:244:244)) + (PORT datad (220:220:220) (248:248:248)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (945:945:945)) + (PORT datab (674:674:674) (710:710:710)) + (PORT datac (1356:1356:1356) (1400:1400:1400)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (889:889:889) (895:895:895)) + (PORT ena (1615:1615:1615) (1626:1626:1626)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (979:979:979)) + (PORT datab (1586:1586:1586) (1671:1671:1671)) + (PORT datac (857:857:857) (920:920:920)) + (PORT datad (419:419:419) (492:492:492)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (873:873:873)) + (PORT datab (262:262:262) (317:317:317)) + (PORT datac (849:849:849) (911:911:911)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (874:874:874)) + (PORT datab (880:880:880) (945:945:945)) + (PORT datad (741:741:741) (783:783:783)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (1309:1309:1309) (1365:1365:1365)) + (PORT datac (209:209:209) (249:249:249)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (999:999:999)) + (PORT datab (1075:1075:1075) (1142:1142:1142)) + (PORT datac (885:885:885) (962:962:962)) + (PORT datad (648:648:648) (680:680:680)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (726:726:726)) + (PORT datab (844:844:844) (863:863:863)) + (PORT datac (626:626:626) (661:661:661)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (724:724:724)) + (PORT datab (849:849:849) (909:909:909)) + (PORT datac (819:819:819) (834:834:834)) + (PORT datad (635:635:635) (671:671:671)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (625:625:625) (665:665:665)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (458:458:458) (536:536:536)) + (PORT datab (592:592:592) (622:622:622)) + (PORT datac (651:651:651) (713:713:713)) + (PORT datad (832:832:832) (855:855:855)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (387:387:387)) + (PORT datac (200:200:200) (235:235:235)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~1) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (390:390:390)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (344:344:344) (373:373:373)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (719:719:719)) + (PORT datab (857:857:857) (902:902:902)) + (PORT datac (2037:2037:2037) (2075:2075:2075)) + (PORT datad (827:827:827) (920:920:920)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (953:953:953) (1017:1017:1017)) + (PORT datac (663:663:663) (701:701:701)) + (PORT datad (629:629:629) (658:658:658)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1608:1608:1608) (1638:1638:1638)) + (PORT datab (724:724:724) (761:761:761)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (970:970:970) (1003:1003:1003)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (450:450:450) (514:514:514)) + (PORT datab (266:266:266) (322:322:322)) + (PORT datad (605:605:605) (629:629:629)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (647:647:647)) + (PORT datab (587:587:587) (595:595:595)) + (PORT datac (850:850:850) (906:906:906)) + (PORT datad (176:176:176) (203:203:203)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (594:594:594)) + (PORT datab (227:227:227) (269:269:269)) + (PORT datac (843:843:843) (914:914:914)) + (PORT datad (777:777:777) (827:827:827)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (685:685:685) (729:729:729)) + (PORT datab (1152:1152:1152) (1160:1160:1160)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (538:538:538) (551:551:551)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1856:1856:1856) (1889:1889:1889)) + (PORT datab (205:205:205) (246:246:246)) + (PORT datac (885:885:885) (932:932:932)) + (PORT datad (330:330:330) (354:354:354)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1105:1105:1105) (1134:1134:1134)) + (PORT datab (1396:1396:1396) (1456:1456:1456)) + (PORT datac (796:796:796) (811:811:811)) + (PORT datad (563:563:563) (577:577:577)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (801:801:801) (823:823:823)) + (PORT datab (363:363:363) (394:394:394)) + (PORT datac (1051:1051:1051) (1079:1079:1079)) + (PORT datad (1041:1041:1041) (1076:1076:1076)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (268:268:268)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (601:601:601) (617:617:617)) + (PORT datad (589:589:589) (602:602:602)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (990:990:990)) + (PORT datab (932:932:932) (968:968:968)) + (PORT datac (1207:1207:1207) (1265:1265:1265)) + (PORT datad (620:620:620) (652:652:652)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (228:228:228) (269:269:269)) + (PORT datac (859:859:859) (877:877:877)) + (PORT datad (619:619:619) (659:659:659)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~14) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (288:288:288)) + (PORT datab (1534:1534:1534) (1581:1581:1581)) + (PORT datac (1206:1206:1206) (1250:1250:1250)) + (PORT datad (685:685:685) (739:739:739)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~13) + (DELAY + (ABSOLUTE + (PORT datac (186:186:186) (225:225:225)) + (PORT datad (191:191:191) (224:224:224)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~15) + (DELAY + (ABSOLUTE + (PORT dataa (800:800:800) (827:827:827)) + (PORT datab (362:362:362) (398:398:398)) + (PORT datac (521:521:521) (537:537:537)) + (PORT datad (812:812:812) (823:823:823)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~16) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (663:663:663)) + (PORT datab (666:666:666) (681:681:681)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (640:640:640)) + (PORT datab (1418:1418:1418) (1463:1463:1463)) + (PORT datac (1454:1454:1454) (1487:1487:1487)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1202:1202:1202) (1281:1281:1281)) + (PORT datab (1419:1419:1419) (1462:1462:1462)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (831:831:831) (848:848:848)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1013:1013:1013)) + (PORT datab (1181:1181:1181) (1227:1227:1227)) + (PORT datac (632:632:632) (648:648:648)) + (PORT datad (1362:1362:1362) (1411:1411:1411)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_set\~0) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (848:848:848)) + (PORT datab (1395:1395:1395) (1453:1453:1453)) + (PORT datac (1074:1074:1074) (1096:1096:1096)) + (PORT datad (1683:1683:1683) (1743:1743:1743)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M2T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (1811:1811:1811) (1879:1879:1879)) + (PORT datab (676:676:676) (715:715:715)) + (PORT datac (1045:1045:1045) (1109:1109:1109)) + (PORT datad (333:333:333) (359:359:359)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (875:875:875)) + (PORT datab (631:631:631) (658:658:658)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (617:617:617) (665:665:665)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (570:570:570)) + (PORT datab (641:641:641) (662:662:662)) + (PORT datac (570:570:570) (588:588:588)) + (PORT datad (321:321:321) (344:344:344)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (946:946:946)) + (PORT datab (1101:1101:1101) (1148:1148:1148)) + (PORT datac (813:813:813) (870:870:870)) + (PORT datad (589:589:589) (601:601:601)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (943:943:943)) + (PORT datab (440:440:440) (502:502:502)) + (PORT datac (322:322:322) (346:346:346)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) + (DELAY + (ABSOLUTE + (PORT datab (956:956:956) (1019:1019:1019)) + (PORT datac (686:686:686) (722:722:722)) + (PORT datad (935:935:935) (962:962:962)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (710:710:710)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (616:616:616) (639:639:639)) + (PORT datad (1569:1569:1569) (1593:1593:1593)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (879:879:879)) + (PORT datab (204:204:204) (245:245:245)) + (PORT datac (222:222:222) (303:303:303)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (880:880:880)) + (PORT datab (350:350:350) (384:384:384)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1571:1571:1571) (1597:1597:1597)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1404:1404:1404) (1572:1572:1572)) + (PORT datab (2576:2576:2576) (2768:2768:2768)) + (PORT datac (1211:1211:1211) (1292:1292:1292)) + (PORT datad (1321:1321:1321) (1487:1487:1487)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) + (DELAY + (ABSOLUTE + (PORT dataa (402:402:402) (436:436:436)) + (PORT datab (642:642:642) (698:698:698)) + (PORT datac (1721:1721:1721) (1770:1770:1770)) + (PORT datad (842:842:842) (847:847:847)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (688:688:688)) + (PORT datab (673:673:673) (705:705:705)) + (PORT datad (1121:1121:1121) (1149:1149:1149)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1852:1852:1852) (1960:1960:1960)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (811:811:811) (834:834:834)) + (PORT datad (1186:1186:1186) (1218:1218:1218)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1152:1152:1152)) + (PORT datab (850:850:850) (888:888:888)) + (PORT datac (1161:1161:1161) (1194:1194:1194)) + (PORT datad (1113:1113:1113) (1135:1135:1135)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (340:340:340)) + (PORT datab (260:260:260) (342:342:342)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (853:853:853) (853:853:853)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) + (DELAY + (ABSOLUTE + (PORT dataa (993:993:993) (1071:1071:1071)) + (PORT datab (877:877:877) (903:903:903)) + (PORT datac (1043:1043:1043) (1136:1136:1136)) + (PORT datad (1269:1269:1269) (1356:1356:1356)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) + (DELAY + (ABSOLUTE + (PORT dataa (240:240:240) (283:283:283)) + (PORT datab (1397:1397:1397) (1493:1493:1493)) + (PORT datac (1951:1951:1951) (2029:2029:2029)) + (PORT datad (909:909:909) (935:935:935)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (255:255:255)) + (PORT datab (994:994:994) (1065:1065:1065)) + (PORT datac (1181:1181:1181) (1238:1238:1238)) + (PORT datad (1433:1433:1433) (1519:1519:1519)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1149:1149:1149) (1166:1166:1166)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (638:638:638) (669:669:669)) + (PORT datad (883:883:883) (915:915:915)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (689:689:689)) + (PORT datab (1238:1238:1238) (1272:1272:1272)) + (PORT datac (185:185:185) (224:224:224)) + (PORT datad (633:633:633) (665:665:665)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (665:665:665)) + (PORT datab (628:628:628) (640:640:640)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (320:320:320) (341:341:341)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal64\~0) + (DELAY + (ABSOLUTE + (PORT datac (962:962:962) (1026:1026:1026)) + (PORT datad (841:841:841) (860:860:860)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~1) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (629:629:629) (639:639:639)) + (PORT datac (207:207:207) (246:246:246)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (941:941:941)) + (PORT datab (1982:1982:1982) (2090:2090:2090)) + (PORT datac (1348:1348:1348) (1372:1372:1372)) + (PORT datad (2100:2100:2100) (2296:2296:2296)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (906:906:906)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (217:217:217) (260:260:260)) + (PORT datad (196:196:196) (229:229:229)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (914:914:914)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (1205:1205:1205) (1266:1266:1266)) + (PORT datad (904:904:904) (932:932:932)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (256:256:256)) + (PORT datab (1175:1175:1175) (1240:1240:1240)) + (PORT datad (184:184:184) (215:215:215)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1245:1245:1245) (1307:1307:1307)) + (PORT datab (684:684:684) (724:724:724)) + (PORT datac (794:794:794) (837:837:837)) + (PORT datad (1662:1662:1662) (1693:1693:1693)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (607:607:607)) + (PORT datab (815:815:815) (829:829:829)) + (PORT datac (585:585:585) (610:610:610)) + (PORT datad (651:651:651) (668:668:668)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (673:673:673) (690:690:690)) + (PORT datac (346:346:346) (370:370:370)) + (PORT datad (619:619:619) (643:643:643)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1355:1355:1355) (1407:1407:1407)) + (PORT datab (927:927:927) (984:984:984)) + (PORT datac (1048:1048:1048) (1096:1096:1096)) + (PORT datad (1421:1421:1421) (1444:1444:1444)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (401:401:401)) + (PORT datab (629:629:629) (655:655:655)) + (PORT datac (191:191:191) (224:224:224)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (693:693:693) (730:730:730)) + (PORT datab (988:988:988) (1020:1020:1020)) + (PORT datac (2018:2018:2018) (2126:2126:2126)) + (PORT datad (326:326:326) (345:345:345)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) + (DELAY + (ABSOLUTE + (PORT datab (806:806:806) (826:826:826)) + (PORT datac (215:215:215) (257:257:257)) + (PORT datad (831:831:831) (857:857:857)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (345:345:345) (376:376:376)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (613:613:613) (625:625:625)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_cf) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (648:648:648)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (575:575:575) (577:577:577)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1117:1117:1117) (1153:1153:1153)) + (PORT datab (1198:1198:1198) (1239:1239:1239)) + (PORT datac (1173:1173:1173) (1228:1228:1228)) + (PORT datad (1368:1368:1368) (1397:1397:1397)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1134:1134:1134) (1151:1151:1151)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (202:202:202) (239:239:239)) + (PORT datad (528:528:528) (546:546:546)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) + (DELAY + (ABSOLUTE + (PORT datab (847:847:847) (854:854:854)) + (PORT datac (1082:1082:1082) (1133:1133:1133)) + (PORT datad (828:828:828) (834:834:834)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (829:829:829)) + (PORT datab (897:897:897) (933:933:933)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~9) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (965:965:965)) + (PORT datab (912:912:912) (924:924:924)) + (PORT datac (1409:1409:1409) (1449:1449:1449)) + (PORT datad (873:873:873) (900:900:900)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1222:1222:1222) (1258:1258:1258)) + (PORT datab (887:887:887) (920:920:920)) + (PORT datac (1132:1132:1132) (1158:1158:1158)) + (PORT datad (950:950:950) (979:979:979)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1201:1201:1201) (1284:1284:1284)) + (PORT datab (1418:1418:1418) (1466:1466:1466)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (532:532:532) (548:548:548)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (702:702:702)) + (PORT datab (652:652:652) (733:733:733)) + (PORT datac (1060:1060:1060) (1092:1092:1092)) + (PORT datad (543:543:543) (547:547:547)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (722:722:722) (746:746:746)) + (PORT datab (1346:1346:1346) (1366:1366:1366)) + (PORT datac (956:956:956) (1016:1016:1016)) + (PORT datad (374:374:374) (392:392:392)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (252:252:252)) + (PORT datab (1175:1175:1175) (1216:1216:1216)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (590:590:590) (618:618:618)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (606:606:606)) + (PORT datab (829:829:829) (843:843:843)) + (PORT datac (563:563:563) (578:578:578)) + (PORT datad (562:562:562) (578:578:578)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1024:1024:1024) (1052:1052:1052)) + (PORT ena (984:984:984) (983:983:983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1024:1024:1024) (1053:1053:1053)) + (PORT ena (923:923:923) (907:907:907)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (464:464:464)) + (PORT datab (450:450:450) (485:485:485)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1198:1198:1198) (1257:1257:1257)) + (PORT datab (852:852:852) (879:879:879)) + (PORT datad (594:594:594) (619:619:619)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1191:1191:1191) (1216:1216:1216)) + (PORT ena (1248:1248:1248) (1256:1256:1256)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1010:1010:1010) (1041:1041:1041)) + (PORT ena (1712:1712:1712) (1752:1752:1752)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1012:1012:1012) (1044:1044:1044)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (264:264:264) (329:329:329)) + (PORT datab (1408:1408:1408) (1522:1522:1522)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (681:681:681) (743:743:743)) + (PORT datad (608:608:608) (631:631:631)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT asdata (969:969:969) (995:995:995)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1189:1189:1189) (1215:1215:1215)) + (PORT ena (1275:1275:1275) (1314:1314:1314)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (787:787:787)) + (PORT datab (725:725:725) (775:775:775)) + (PORT datad (1020:1020:1020) (1061:1061:1061)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1197:1197:1197) (1218:1218:1218)) + (PORT ena (1147:1147:1147) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1195:1195:1195) (1219:1219:1219)) + (PORT ena (1248:1248:1248) (1262:1262:1262)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (667:667:667)) + (PORT datab (947:947:947) (1004:1004:1004)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1168:1168:1168) (1161:1161:1161)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (697:697:697)) + (PORT datab (636:636:636) (670:670:670)) + (PORT datac (376:376:376) (420:420:420)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (811:811:811) (832:832:832)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (638:638:638) (670:670:670)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1182:1182:1182) (1199:1199:1199)) + (PORT datac (1095:1095:1095) (1092:1092:1092)) + (PORT datad (659:659:659) (693:693:693)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1466:1466:1466) (1517:1517:1517)) + (PORT datab (670:670:670) (708:708:708)) + (PORT datad (839:839:839) (834:834:834)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (420:420:420) (480:480:480)) + (PORT datac (666:666:666) (693:693:693)) + (PORT datad (331:331:331) (347:347:347)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (422:422:422) (511:511:511)) + (PORT datad (201:201:201) (229:229:229)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (591:591:591)) + (PORT datab (244:244:244) (291:291:291)) + (PORT datac (1211:1211:1211) (1265:1265:1265)) + (PORT datad (625:625:625) (637:637:637)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[4\]) + (DELAY + (ABSOLUTE + (PORT dataa (1104:1104:1104) (1133:1133:1133)) + (PORT datad (860:860:860) (861:861:861)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1592:1592:1592) (1568:1568:1568)) + (PORT ena (2023:2023:2023) (2039:2039:2039)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) + (DELAY + (ABSOLUTE + (PORT dataa (419:419:419) (509:509:509)) + (PORT datab (392:392:392) (466:466:466)) + (PORT datac (243:243:243) (322:322:322)) + (PORT datad (237:237:237) (305:305:305)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) + (DELAY + (ABSOLUTE + (PORT dataa (455:455:455) (527:527:527)) + (PORT datab (420:420:420) (490:490:490)) + (PORT datac (392:392:392) (467:467:467)) + (PORT datad (239:239:239) (308:308:308)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1314:1314:1314) (1365:1365:1365)) + (PORT datab (705:705:705) (774:774:774)) + (PORT datac (594:594:594) (664:664:664)) + (PORT datad (239:239:239) (309:309:309)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) + (DELAY + (ABSOLUTE + (PORT dataa (425:425:425) (509:509:509)) + (PORT datab (411:411:411) (493:493:493)) + (PORT datac (550:550:550) (609:609:609)) + (PORT datad (376:376:376) (439:439:439)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (895:895:895)) + (PORT datab (822:822:822) (844:844:844)) + (PORT datac (609:609:609) (631:631:631)) + (PORT datad (629:629:629) (662:662:662)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1022:1022:1022) (1069:1069:1069)) + (PORT datab (684:684:684) (720:720:720)) + (PORT datad (623:623:623) (638:638:638)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1574:1574:1574) (1553:1553:1553)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (964:964:964) (1023:1023:1023)) + (PORT datab (637:637:637) (662:662:662)) + (PORT datac (843:843:843) (877:877:877)) + (PORT datad (636:636:636) (678:678:678)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal79\~0) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (631:631:631)) + (PORT datab (2626:2626:2626) (2719:2719:2719)) + (PORT datac (2090:2090:2090) (2263:2263:2263)) + (PORT datad (1434:1434:1434) (1452:1452:1452)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (581:581:581) (604:604:604)) + (PORT datab (608:608:608) (677:677:677)) + (PORT datad (1145:1145:1145) (1180:1180:1180)) + (IOPATH dataa combout (301:301:301) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (446:446:446)) + (PORT datac (721:721:721) (815:815:815)) + (PORT datad (268:268:268) (348:348:348)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1240:1240:1240) (1269:1269:1269)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1545:1545:1545)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (1364:1364:1364) (1421:1421:1421)) + (PORT datac (853:853:853) (901:901:901)) + (PORT datad (232:232:232) (309:309:309)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) + (DELAY + (ABSOLUTE + (PORT dataa (260:260:260) (352:352:352)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (983:983:983) (1029:1029:1029)) + (PORT datad (837:837:837) (875:875:875)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1021:1021:1021) (1068:1068:1068)) + (PORT datab (1361:1361:1361) (1418:1418:1418)) + (PORT datac (607:607:607) (631:631:631)) + (PORT datad (920:920:920) (974:974:974)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (914:914:914)) + (PORT datab (641:641:641) (700:700:700)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (636:636:636) (677:677:677)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1022:1022:1022) (1066:1066:1066)) + (PORT datab (2171:2171:2171) (2355:2355:2355)) + (PORT datac (1335:1335:1335) (1387:1387:1387)) + (PORT datad (1335:1335:1335) (1492:1492:1492)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1026:1026:1026) (1071:1071:1071)) + (PORT datab (932:932:932) (993:993:993)) + (PORT datac (607:607:607) (627:627:627)) + (PORT datad (837:837:837) (870:870:870)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (872:872:872) (918:918:918)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (636:636:636) (681:681:681)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (387:387:387)) + (PORT datab (258:258:258) (300:300:300)) + (PORT datac (364:364:364) (389:389:389)) + (PORT datad (575:575:575) (588:588:588)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1867:1867:1867) (1883:1883:1883)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (414:414:414)) + (PORT datab (355:355:355) (391:391:391)) + (PORT datac (321:321:321) (346:346:346)) + (PORT datad (193:193:193) (218:218:218)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out) + (DELAY + (ABSOLUTE + (PORT datab (1247:1247:1247) (1295:1295:1295)) + (PORT datad (788:788:788) (792:792:792)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (509:509:509) (518:518:518)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (473:473:473)) + (PORT datab (966:966:966) (1019:1019:1019)) + (PORT datac (957:957:957) (996:996:996)) + (PORT datad (930:930:930) (961:961:961)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) + (DELAY + (ABSOLUTE + (PORT dataa (961:961:961) (1008:1008:1008)) + (PORT datab (792:792:792) (810:810:810)) + (PORT datac (831:831:831) (846:846:846)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1210:1210:1210) (1277:1277:1277)) + (PORT datab (1010:1010:1010) (1070:1070:1070)) + (PORT datac (1149:1149:1149) (1202:1202:1202)) + (PORT datad (1136:1136:1136) (1189:1189:1189)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (701:701:701)) + (PORT datab (228:228:228) (269:269:269)) + (PORT datac (538:538:538) (560:560:560)) + (PORT datad (348:348:348) (372:372:372)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) + (DELAY + (ABSOLUTE + (PORT dataa (843:843:843) (866:866:866)) + (PORT datab (626:626:626) (642:642:642)) + (PORT datac (556:556:556) (572:572:572)) + (PORT datad (542:542:542) (555:555:555)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11) + (DELAY + (ABSOLUTE + (PORT datab (1147:1147:1147) (1156:1156:1156)) + (PORT datac (312:312:312) (331:331:331)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (662:662:662)) + (PORT datab (1297:1297:1297) (1354:1354:1354)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (820:820:820) (839:839:839)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (699:699:699)) + (PORT datab (941:941:941) (1002:1002:1002)) + (PORT datac (1172:1172:1172) (1234:1234:1234)) + (PORT datad (786:786:786) (778:778:778)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (827:827:827)) + (PORT datab (677:677:677) (738:738:738)) + (PORT datac (656:656:656) (722:722:722)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) + (DELAY + (ABSOLUTE + (PORT dataa (679:679:679) (727:727:727)) + (PORT datab (986:986:986) (1058:1058:1058)) + (PORT datad (504:504:504) (504:504:504)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|flags_cond_true) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1310:1310:1310) (1360:1360:1360)) + (PORT datab (995:995:995) (1071:1071:1071)) + (PORT datac (1112:1112:1112) (1137:1137:1137)) + (PORT datad (1570:1570:1570) (1618:1618:1618)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1476:1476:1476) (1520:1520:1520)) + (PORT datab (1155:1155:1155) (1181:1181:1181)) + (PORT datac (1087:1087:1087) (1097:1097:1097)) + (PORT datad (600:600:600) (614:614:614)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (667:667:667)) + (PORT datab (227:227:227) (267:267:267)) + (PORT datac (613:613:613) (637:637:637)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) + (DELAY + (ABSOLUTE + (PORT dataa (963:963:963) (1037:1037:1037)) + (PORT datac (957:957:957) (1023:1023:1023)) + (PORT datad (1214:1214:1214) (1280:1280:1280)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (692:692:692)) + (PORT datab (1444:1444:1444) (1500:1500:1500)) + (PORT datac (590:590:590) (630:630:630)) + (PORT datad (582:582:582) (612:612:612)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (752:752:752) (788:788:788)) + (PORT ena (1203:1203:1203) (1189:1189:1189)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (690:690:690)) + (PORT datab (622:622:622) (668:668:668)) + (PORT datad (598:598:598) (635:635:635)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1185:1185:1185) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (581:581:581)) + (PORT datab (592:592:592) (627:627:627)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (474:474:474) (523:523:523)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1498:1498:1498) (1562:1562:1562)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[11\]) + (DELAY + (ABSOLUTE + (PORT datac (880:880:880) (938:938:938)) + (PORT datad (349:349:349) (365:365:365)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (1783:1783:1783) (1814:1814:1814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) + (DELAY + (ABSOLUTE + (PORT datac (415:415:415) (481:481:481)) + (PORT datad (341:341:341) (363:363:363)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1176:1176:1176) (1262:1262:1262)) + (PORT datab (390:390:390) (410:410:410)) + (PORT datad (553:553:553) (555:555:555)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -29643,12 +31064,12 @@ (INSTANCE z80_\|execute_\|ctl_apin_mux2\~0) (DELAY (ABSOLUTE - (PORT dataa (949:949:949) (1028:1028:1028)) - (PORT datab (994:994:994) (1080:1080:1080)) - (PORT datac (1875:1875:1875) (2047:2047:2047)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (1382:1382:1382) (1568:1568:1568)) + (PORT datac (1328:1328:1328) (1469:1469:1469)) + (PORT datad (2533:2533:2533) (2621:2621:2621)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -29657,13 +31078,13 @@ (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~2) (DELAY (ABSOLUTE - (PORT dataa (1686:1686:1686) (1827:1827:1827)) - (PORT datab (974:974:974) (1024:1024:1024)) - (PORT datac (941:941:941) (1003:1003:1003)) - (PORT datad (1201:1201:1201) (1259:1259:1259)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1134:1134:1134) (1163:1163:1163)) + (PORT datab (924:924:924) (979:979:979)) + (PORT datac (820:820:820) (846:846:846)) + (PORT datad (1655:1655:1655) (1830:1830:1830)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -29673,653 +31094,13 @@ (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~3) (DELAY (ABSOLUTE - (PORT dataa (948:948:948) (1027:1027:1027)) - (PORT datab (994:994:994) (1080:1080:1080)) - (PORT datac (1875:1875:1875) (2047:2047:2047)) - (PORT datad (622:622:622) (660:660:660)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (603:603:603) (689:689:689)) - (PORT sload (1125:1125:1125) (1169:1169:1169)) - (PORT ena (1155:1155:1155) (1129:1129:1129)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[13\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1195:1195:1195) (1254:1254:1254)) - (PORT datad (2019:2019:2019) (2140:2140:2140)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1794:1794:1794) (1807:1807:1807)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datad (320:320:320) (334:334:334)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (590:590:590) (668:668:668)) - (PORT sload (1125:1125:1125) (1169:1169:1169)) - (PORT ena (1155:1155:1155) (1129:1129:1129)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[14\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (2045:2045:2045) (2178:2178:2178)) - (PORT datad (1147:1147:1147) (1202:1202:1202)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1796:1796:1796) (1810:1810:1810)) - (PORT datab (337:337:337) (371:371:371)) - (PORT datad (554:554:554) (561:561:561)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (577:577:577) (658:658:658)) - (PORT sload (1125:1125:1125) (1169:1169:1169)) - (PORT ena (1155:1155:1155) (1129:1129:1129)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[15\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (1641:1641:1641) (1729:1729:1729)) - (PORT datac (1584:1584:1584) (1634:1634:1634)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (725:725:725)) - (PORT datab (261:261:261) (314:314:314)) - (PORT datac (366:366:366) (404:404:404)) - (PORT datad (1304:1304:1304) (1296:1296:1296)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (2037:2037:2037) (2174:2174:2174)) - (PORT datac (1153:1153:1153) (1208:1208:1208)) - (PORT datad (1144:1144:1144) (1203:1203:1203)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (971:971:971)) - (PORT datad (1987:1987:1987) (2083:2083:2083)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (854:854:854) (879:879:879)) - (PORT datab (373:373:373) (396:396:396)) - (PORT datad (334:334:334) (343:343:343)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1128:1128:1128) (1174:1174:1174)) - (PORT sload (1213:1213:1213) (1283:1283:1283)) - (PORT ena (1456:1456:1456) (1440:1440:1440)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1793:1793:1793) (1909:1909:1909)) - (PORT datad (678:678:678) (733:733:733)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (855:855:855) (880:880:880)) - (PORT datab (604:604:604) (620:620:620)) - (PORT datad (532:532:532) (544:544:544)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (992:992:992) (1045:1045:1045)) - (PORT sload (1213:1213:1213) (1283:1283:1283)) - (PORT ena (1456:1456:1456) (1440:1440:1440)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) - (DELAY - (ABSOLUTE - (PORT datac (1749:1749:1749) (1862:1862:1862)) - (PORT datad (642:642:642) (699:699:699)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (887:887:887)) - (PORT datab (535:535:535) (551:551:551)) - (PORT datad (339:339:339) (355:355:355)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (751:751:751) (807:807:807)) - (PORT sload (1213:1213:1213) (1283:1283:1283)) - (PORT ena (1456:1456:1456) (1440:1440:1440)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) - (DELAY - (ABSOLUTE - (PORT datac (1754:1754:1754) (1872:1872:1872)) - (PORT datad (367:367:367) (429:429:429)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (853:853:853) (880:880:880)) - (PORT datab (534:534:534) (559:559:559)) - (PORT datad (339:339:339) (357:357:357)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (979:979:979) (1031:1031:1031)) - (PORT sload (1213:1213:1213) (1283:1283:1283)) - (PORT ena (1456:1456:1456) (1440:1440:1440)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) - (DELAY - (ABSOLUTE - (PORT datac (1758:1758:1758) (1874:1874:1874)) - (PORT datad (652:652:652) (710:710:710)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1351:1351:1351) (1385:1385:1385)) - (PORT datab (337:337:337) (371:371:371)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1019:1019:1019) (1078:1078:1078)) - (PORT sload (1150:1150:1150) (1218:1218:1218)) - (PORT ena (1176:1176:1176) (1166:1166:1166)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) - (DELAY - (ABSOLUTE - (PORT datab (2021:2021:2021) (2124:2124:2124)) - (PORT datac (676:676:676) (743:743:743)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datad (1323:1323:1323) (1343:1343:1343)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1156:1156:1156) (1209:1209:1209)) - (PORT sload (1150:1150:1150) (1218:1218:1218)) - (PORT ena (1176:1176:1176) (1166:1166:1166)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) - (DELAY - (ABSOLUTE - (PORT datab (696:696:696) (759:759:759)) - (PORT datac (1750:1750:1750) (1863:1863:1863)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1354:1354:1354) (1387:1387:1387)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1639:1639:1639) (1657:1657:1657)) - (PORT sload (1150:1150:1150) (1218:1218:1218)) - (PORT ena (1176:1176:1176) (1166:1166:1166)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) - (DELAY - (ABSOLUTE - (PORT datac (1748:1748:1748) (1867:1867:1867)) - (PORT datad (927:927:927) (1010:1010:1010)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (380:380:380)) - (PORT datab (1361:1361:1361) (1369:1369:1369)) - (PORT datad (196:196:196) (222:222:222)) + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1914:1914:1914) (2085:2085:2085)) + (PORT datac (2116:2116:2116) (2227:2227:2227)) + (PORT datad (1650:1650:1650) (1834:1834:1834)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (597:597:597) (678:678:678)) - (PORT sload (1150:1150:1150) (1218:1218:1218)) - (PORT ena (1176:1176:1176) (1166:1166:1166)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) - (DELAY - (ABSOLUTE - (PORT datab (948:948:948) (1009:1009:1009)) - (PORT datad (2008:2008:2008) (2130:2130:2130)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1391:1391:1391) (1422:1422:1422)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datad (552:552:552) (561:561:561)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (591:591:591) (677:677:677)) - (PORT sload (1117:1117:1117) (1168:1168:1168)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) - (DELAY - (ABSOLUTE - (PORT datac (1757:1757:1757) (1868:1868:1868)) - (PORT datad (678:678:678) (737:737:737)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (567:567:567) (585:585:585)) - (PORT datad (1365:1365:1365) (1379:1379:1379)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (580:580:580) (668:668:668)) - (PORT sload (1117:1117:1117) (1168:1168:1168)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[10\]\~24) - (DELAY - (ABSOLUTE - (PORT datac (910:910:910) (972:972:972)) - (PORT datad (1442:1442:1442) (1565:1565:1565)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (197:197:197) (234:234:234)) - (PORT datad (1362:1362:1362) (1374:1374:1374)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -30329,11 +31110,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT clk (1529:1529:1529) (1534:1534:1534)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (913:913:913) (972:972:972)) - (PORT sload (1117:1117:1117) (1168:1168:1168)) - (PORT ena (811:811:811) (804:804:804)) + (PORT asdata (1184:1184:1184) (1229:1229:1229)) + (PORT sload (1432:1432:1432) (1514:1514:1514)) + (PORT ena (1459:1459:1459) (1480:1480:1480)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -30349,37 +31130,37 @@ (INSTANCE z80_\|address_pins_\|abus\[11\]\~19) (DELAY (ABSOLUTE - (PORT dataa (942:942:942) (1010:1010:1010)) - (PORT datad (1442:1442:1442) (1566:1566:1566)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT datac (1399:1399:1399) (1483:1483:1483)) + (PORT datad (1955:1955:1955) (2153:2153:2153)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) (DELAY (ABSOLUTE - (PORT dataa (340:340:340) (375:375:375)) - (PORT datab (816:816:816) (834:834:834)) - (PORT datad (1561:1561:1561) (1571:1571:1571)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (1180:1180:1180) (1258:1258:1258)) + (PORT datab (195:195:195) (234:234:234)) + (PORT datad (566:566:566) (578:578:578)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) (DELAY (ABSOLUTE (PORT clk (1529:1529:1529) (1534:1534:1534)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (583:583:583) (667:667:667)) - (PORT sload (1125:1125:1125) (1169:1169:1169)) - (PORT ena (1155:1155:1155) (1129:1129:1129)) + (PORT asdata (753:753:753) (819:819:819)) + (PORT sload (1432:1432:1432) (1514:1514:1514)) + (PORT ena (1459:1459:1459) (1480:1480:1480)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -30392,206 +31173,205 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[12\]\~21) + (INSTANCE z80_\|address_pins_\|abus\[10\]\~20) (DELAY (ABSOLUTE - (PORT dataa (1791:1791:1791) (1903:1903:1903)) - (PORT datad (854:854:854) (913:913:913)) + (PORT dataa (2315:2315:2315) (2530:2530:2530)) + (PORT datad (1404:1404:1404) (1520:1520:1520)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~19) (DELAY (ABSOLUTE - (PORT d[0] (1010:1010:1010) (1062:1062:1062)) - (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT dataa (303:303:303) (420:420:420)) + (PORT datac (915:915:915) (973:973:973)) + (PORT datad (643:643:643) (704:704:704)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1009:1009:1009) (1047:1047:1047)) - (PORT d[1] (2076:2076:2076) (2305:2305:2305)) - (PORT d[2] (1463:1463:1463) (1514:1514:1514)) - (PORT d[3] (2867:2867:2867) (3072:3072:3072)) - (PORT d[4] (2625:2625:2625) (2841:2841:2841)) - (PORT d[5] (3152:3152:3152) (3353:3353:3353)) - (PORT d[6] (1368:1368:1368) (1453:1453:1453)) - (PORT d[7] (2906:2906:2906) (3079:3079:3079)) - (PORT d[8] (997:997:997) (1014:1014:1014)) - (PORT d[9] (1597:1597:1597) (1654:1654:1654)) - (PORT d[10] (1607:1607:1607) (1695:1695:1695)) - (PORT d[11] (2235:2235:2235) (2380:2380:2380)) - (PORT d[12] (1610:1610:1610) (1712:1712:1712)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (958:958:958) (934:934:934)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1883:1883:1883)) - (PORT d[0] (1472:1472:1472) (1458:1458:1458)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1816:1816:1816) (1842:1842:1842)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1896:1896:1896) (1918:1918:1918)) - (PORT asdata (2035:2035:2035) (2085:2085:2085)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT asdata (1451:1451:1451) (1488:1488:1488)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~48) (DELAY (ABSOLUTE - (PORT dataa (697:697:697) (725:725:725)) - (PORT datab (262:262:262) (316:316:316)) - (PORT datac (367:367:367) (405:405:405)) - (PORT datad (1303:1303:1303) (1300:1300:1300)) + (PORT dataa (617:617:617) (640:640:640)) + (PORT datab (1304:1304:1304) (1358:1358:1358)) + (PORT datac (728:728:728) (812:812:812)) + (PORT datad (618:618:618) (638:638:638)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (436:436:436)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datad (187:187:187) (218:218:218)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (716:716:716)) + (PORT datab (2772:2772:2772) (2956:2956:2956)) + (PORT datac (648:648:648) (682:682:682)) + (PORT datad (637:637:637) (706:706:706)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (276:276:276) (367:367:367)) + (PORT datab (955:955:955) (1021:1021:1021)) + (PORT datac (1004:1004:1004) (1065:1065:1065)) + (PORT datad (262:262:262) (340:340:340)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1065:1065:1065) (1138:1138:1138)) + (PORT datac (266:266:266) (360:360:360)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (299:299:299) (419:419:419)) + (PORT datac (911:911:911) (974:974:974)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1228:1228:1228) (1254:1254:1254)) + (PORT datac (699:699:699) (766:766:766)) + (PORT datad (614:614:614) (688:688:688)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~3) + (DELAY + (ABSOLUTE + (PORT dataa (786:786:786) (869:869:869)) + (PORT datab (336:336:336) (364:364:364)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|shifted) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~62) + (DELAY + (ABSOLUTE + (PORT datab (772:772:772) (854:854:854)) + (PORT datac (461:461:461) (534:534:534)) + (PORT datad (928:928:928) (988:988:988)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1002:1002:1002) (1071:1071:1071)) + (PORT datab (656:656:656) (730:730:730)) + (PORT datac (702:702:702) (766:766:766)) + (PORT datad (1186:1186:1186) (1205:1205:1205)) (IOPATH dataa combout (303:303:303) (299:299:299)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -30601,208 +31381,909 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~63) (DELAY (ABSOLUTE - (PORT datab (2042:2042:2042) (2178:2178:2178)) - (PORT datac (1154:1154:1154) (1211:1211:1211)) - (PORT datad (1145:1145:1145) (1206:1206:1206)) + (PORT dataa (1000:1000:1000) (1062:1062:1062)) + (PORT datab (770:770:770) (851:851:851)) + (PORT datac (697:697:697) (772:772:772)) + (PORT datad (969:969:969) (1035:1035:1035)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (748:748:748) (838:838:838)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (259:259:259)) + (PORT datab (562:562:562) (579:579:579)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1520:1520:1520)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datad (1121:1121:1121) (1187:1187:1187)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (895:895:895) (951:951:951)) + (PORT sload (1199:1199:1199) (1277:1277:1277)) + (PORT ena (1447:1447:1447) (1469:1469:1469)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[15\]\~21) + (DELAY + (ABSOLUTE + (PORT datac (1681:1681:1681) (1850:1850:1850)) + (PORT datad (2616:2616:2616) (2812:2812:2812)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (350:350:350) (377:377:377)) + (PORT datad (1120:1120:1120) (1184:1184:1184)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (928:928:928) (977:977:977)) + (PORT sload (1199:1199:1199) (1277:1277:1277)) + (PORT ena (1447:1447:1447) (1469:1469:1469)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[14\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (2421:2421:2421) (2631:2631:2631)) + (PORT datad (1663:1663:1663) (1788:1788:1788)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (1293:1293:1293) (1369:1369:1369)) + (PORT datac (707:707:707) (797:797:797)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (871:871:871)) + (PORT datab (699:699:699) (763:763:763)) + (PORT datac (704:704:704) (770:770:770)) + (PORT datad (183:183:183) (213:213:213)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT datac (680:680:680) (750:750:750)) + (PORT datad (740:740:740) (823:823:823)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (817:817:817)) + (PORT datab (1292:1292:1292) (1364:1364:1364)) + (PORT datac (707:707:707) (793:793:793)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (213:213:213) (256:256:256)) + (PORT datac (762:762:762) (842:842:842)) + (PORT datad (206:206:206) (236:236:236)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (298:298:298) (396:396:396)) + (PORT datac (848:848:848) (867:867:867)) + (PORT datad (709:709:709) (783:783:783)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (757:757:757)) + (PORT datac (984:984:984) (1047:1047:1047)) + (PORT datad (652:652:652) (732:732:732)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (942:942:942)) + (PORT datab (605:605:605) (646:646:646)) + (PORT datad (184:184:184) (214:214:214)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1511:1511:1511) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1538:1538:1538)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (712:712:712)) + (PORT datab (1468:1468:1468) (1492:1492:1492)) + (PORT datac (912:912:912) (969:969:969)) + (PORT datad (362:362:362) (421:421:421)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (220:220:220) (258:258:258)) + (PORT datad (1120:1120:1120) (1184:1184:1184)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (726:726:726) (799:799:799)) + (PORT sload (1199:1199:1199) (1277:1277:1277)) + (PORT ena (1447:1447:1447) (1469:1469:1469)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[12\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (1811:1811:1811) (1928:1928:1928)) + (PORT datac (2265:2265:2265) (2463:2463:2463)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (397:397:397)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datad (1124:1124:1124) (1188:1188:1188)) + (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (741:741:741) (815:815:815)) + (PORT sload (1199:1199:1199) (1277:1277:1277)) + (PORT ena (1447:1447:1447) (1469:1469:1469)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (436:436:436)) + (PORT datab (764:764:764) (853:853:853)) + (PORT datac (695:695:695) (784:784:784)) + (PORT datad (346:346:346) (371:371:371)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~54) (DELAY (ABSOLUTE - (PORT d[0] (991:991:991) (1045:1045:1045)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1010:1010:1010) (1048:1048:1048)) - (PORT d[1] (2092:2092:2092) (2316:2316:2316)) - (PORT d[2] (3345:3345:3345) (3458:3458:3458)) - (PORT d[3] (2859:2859:2859) (3062:3062:3062)) - (PORT d[4] (2566:2566:2566) (2775:2775:2775)) - (PORT d[5] (3169:3169:3169) (3393:3393:3393)) - (PORT d[6] (1618:1618:1618) (1695:1695:1695)) - (PORT d[7] (2898:2898:2898) (3057:3057:3057)) - (PORT d[8] (1024:1024:1024) (1046:1046:1046)) - (PORT d[9] (3241:3241:3241) (3372:3372:3372)) - (PORT d[10] (1642:1642:1642) (1735:1735:1735)) - (PORT d[11] (1916:1916:1916) (2070:2070:2070)) - (PORT d[12] (1870:1870:1870) (1971:1971:1971)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (950:950:950) (925:925:925)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1881:1881:1881)) - (PORT d[0] (1713:1713:1713) (1683:1683:1683)) + (PORT datab (426:426:426) (500:500:500)) + (PORT datac (745:745:745) (821:821:821)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~55) (DELAY (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1840:1840:1840)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1003:1003:1003)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + (PORT dataa (211:211:211) (259:259:259)) + (PORT datab (769:769:769) (850:850:850)) + (PORT datad (176:176:176) (203:203:203)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT asdata (1470:1470:1470) (1518:1518:1518)) + (PORT clk (1506:1506:1506) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1546:1546:1546) (1539:1539:1539)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~1) + (DELAY + (ABSOLUTE + (PORT datab (1971:1971:1971) (2134:2134:2134)) + (PORT datac (2268:2268:2268) (2463:2463:2463)) + (PORT datad (668:668:668) (730:730:730)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~127) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (1011:1011:1011)) + (PORT datab (983:983:983) (1055:1055:1055)) + (PORT datad (204:204:204) (233:233:233)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (1032:1032:1032) (1104:1104:1104)) + (PORT datab (287:287:287) (378:378:378)) + (PORT datac (245:245:245) (328:328:328)) + (PORT datad (709:709:709) (788:788:788)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~128) + (DELAY + (ABSOLUTE + (PORT dataa (1066:1066:1066) (1139:1139:1139)) + (PORT datab (956:956:956) (1026:1026:1026)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (436:436:436)) + (PORT datab (631:631:631) (655:655:655)) + (PORT datad (794:794:794) (817:817:817)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (230:230:230) (272:272:272)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (634:634:634) (705:705:705)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT datac (2534:2534:2534) (2773:2773:2773)) + (PORT datad (1184:1184:1184) (1290:1290:1290)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (736:736:736) (825:825:825)) + (PORT datab (932:932:932) (1013:1013:1013)) + (PORT datac (754:754:754) (837:837:837)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (992:992:992)) + (PORT datab (738:738:738) (804:804:804)) + (PORT datac (695:695:695) (782:782:782)) + (PORT datad (355:355:355) (387:387:387)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (217:217:217) (263:263:263)) + (PORT datac (471:471:471) (550:550:550)) + (PORT datad (633:633:633) (650:650:650)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~46) + (DELAY + (ABSOLUTE + (PORT datab (500:500:500) (572:572:572)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1504:1504:1504) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (728:728:728) (813:813:813)) + (PORT datad (750:750:750) (828:828:828)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (441:441:441)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datad (188:188:188) (220:220:220)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1176:1176:1176) (1258:1258:1258)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datad (319:319:319) (337:337:337)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (736:736:736) (808:808:808)) + (PORT sload (1432:1432:1432) (1514:1514:1514)) + (PORT ena (1459:1459:1459) (1480:1480:1480)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (2312:2312:2312) (2526:2526:2526)) + (PORT datad (1425:1425:1425) (1538:1538:1538)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1176:1176:1176) (1257:1257:1257)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT asdata (706:706:706) (770:770:770)) + (PORT clk (1529:1529:1529) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (734:734:734) (795:795:795)) + (PORT sload (1432:1432:1432) (1514:1514:1514)) + (PORT ena (1459:1459:1459) (1480:1480:1480)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (931:931:931) (1029:1029:1029)) + (PORT datad (2391:2391:2391) (2584:2584:2584)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (785:785:785)) + (PORT datab (676:676:676) (757:757:757)) + (PORT datac (673:673:673) (715:715:715)) + (PORT datad (1494:1494:1494) (1586:1586:1586)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (2355:2355:2355) (2578:2578:2578)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1533:1533:1533)) + (PORT asdata (569:569:569) (649:649:649)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) (TIMINGCHECK (HOLD asdata (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (232:232:232) (306:306:306)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|control_pins_\|pin_nIORQ\~1) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (916:916:916)) + (PORT datab (249:249:249) (333:333:333)) + (PORT datac (994:994:994) (1049:1049:1049)) + (PORT datad (230:230:230) (303:303:303)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2634:2634:2634) (2764:2764:2764)) + (PORT datab (1939:1939:1939) (2080:2080:2080)) + (PORT datac (2770:2770:2770) (3002:3002:3002)) + (PORT datad (2212:2212:2212) (2284:2284:2284)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[13\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (1973:1973:1973) (2138:2138:2138)) + (PORT datac (2265:2265:2265) (2462:2462:2462)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ExtRamWE\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2634:2634:2634) (2769:2769:2769)) + (PORT datab (1937:1937:1937) (2082:2082:2082)) + (PORT datac (2770:2770:2770) (3003:3003:3003)) + (PORT datad (2214:2214:2214) (2287:2287:2287)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (700:700:700) (726:726:726)) - (PORT datab (266:266:266) (319:319:319)) - (PORT datac (371:371:371) (404:404:404)) - (PORT datad (1304:1304:1304) (1295:1295:1295)) + (PORT dataa (409:409:409) (462:462:462)) + (PORT datab (1257:1257:1257) (1295:1295:1295)) + (PORT datac (1233:1233:1233) (1265:1265:1265)) + (PORT datad (1391:1391:1391) (1417:1417:1417)) (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -30815,21 +32296,2740 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) (DELAY (ABSOLUTE - (PORT datab (2038:2038:2038) (2171:2171:2171)) - (PORT datac (1153:1153:1153) (1206:1206:1206)) - (PORT datad (1143:1143:1143) (1202:1202:1202)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (1921:1921:1921) (2116:2116:2116)) + (PORT datac (1982:1982:1982) (2198:2198:2198)) + (PORT datad (1426:1426:1426) (1533:1533:1533)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (253:253:253)) + (PORT datab (616:616:616) (630:630:630)) + (PORT datad (908:908:908) (944:944:944)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (995:995:995) (1050:1050:1050)) + (PORT sload (1199:1199:1199) (1276:1276:1276)) + (PORT ena (1212:1212:1212) (1237:1237:1237)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (2422:2422:2422) (2631:2631:2631)) + (PORT datac (1069:1069:1069) (1151:1151:1151)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1695:1695:1695) (1773:1773:1773)) + (PORT datad (325:325:325) (351:351:351)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (938:938:938) (1005:1005:1005)) + (PORT sload (1638:1638:1638) (1687:1687:1687)) + (PORT ena (1450:1450:1450) (1447:1447:1447)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1175:1175:1175) (1227:1227:1227)) + (PORT datad (2391:2391:2391) (2584:2584:2584)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (891:891:891)) + (PORT datab (1716:1716:1716) (1784:1784:1784)) + (PORT datad (875:875:875) (908:908:908)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (1270:1270:1270) (1328:1328:1328)) + (PORT sload (1357:1357:1357) (1408:1408:1408)) + (PORT ena (1406:1406:1406) (1406:1406:1406)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (264:264:264) (345:345:345)) + (PORT datad (2385:2385:2385) (2578:2578:2578)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (267:267:267)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datad (1658:1658:1658) (1733:1733:1733)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (899:899:899) (959:959:959)) + (PORT sload (1638:1638:1638) (1687:1687:1687)) + (PORT ena (1450:1450:1450) (1447:1447:1447)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (282:282:282) (364:364:364)) + (PORT datad (377:377:377) (439:439:439)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1695:1695:1695) (1769:1769:1769)) + (PORT datad (195:195:195) (219:219:219)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (959:959:959) (1008:1008:1008)) + (PORT sload (1638:1638:1638) (1687:1687:1687)) + (PORT ena (1450:1450:1450) (1447:1447:1447)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) + (DELAY + (ABSOLUTE + (PORT datac (1237:1237:1237) (1358:1358:1358)) + (PORT datad (2381:2381:2381) (2572:2572:2572)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (561:561:561)) + (PORT datab (1692:1692:1692) (1769:1769:1769)) + (PORT datad (316:316:316) (329:329:329)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (588:588:588) (666:666:666)) + (PORT sload (1638:1638:1638) (1687:1687:1687)) + (PORT ena (1450:1450:1450) (1447:1447:1447)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) + (DELAY + (ABSOLUTE + (PORT datac (1495:1495:1495) (1601:1601:1601)) + (PORT datad (2387:2387:2387) (2578:2578:2578)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1071:1071:1071) (1094:1094:1094)) + (PORT datab (898:898:898) (948:948:948)) + (PORT datad (1691:1691:1691) (1747:1747:1747)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (1266:1266:1266) (1347:1347:1347)) + (PORT sload (1357:1357:1357) (1408:1408:1408)) + (PORT ena (1406:1406:1406) (1406:1406:1406)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (2419:2419:2419) (2625:2625:2625)) + (PORT datac (245:245:245) (324:324:324)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1325:1325:1325) (1393:1393:1393)) + (PORT clk (1847:1847:1847) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2362:2362:2362) (2570:2570:2570)) + (PORT d[1] (2582:2582:2582) (2663:2663:2663)) + (PORT d[2] (1885:1885:1885) (2005:2005:2005)) + (PORT d[3] (1262:1262:1262) (1338:1338:1338)) + (PORT d[4] (2266:2266:2266) (2355:2355:2355)) + (PORT d[5] (1286:1286:1286) (1366:1366:1366)) + (PORT d[6] (1452:1452:1452) (1480:1480:1480)) + (PORT d[7] (2355:2355:2355) (2491:2491:2491)) + (PORT d[8] (2239:2239:2239) (2395:2395:2395)) + (PORT d[9] (1053:1053:1053) (1110:1110:1110)) + (PORT d[10] (1026:1026:1026) (1074:1074:1074)) + (PORT d[11] (1436:1436:1436) (1501:1501:1501)) + (PORT d[12] (756:756:756) (816:816:816)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1782:1782:1782) (1767:1767:1767)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (1825:1825:1825) (1809:1809:1809)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1807:1807:1807) (1834:1834:1834)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (992:992:992) (997:997:997)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1887:1887:1887) (1911:1911:1911)) + (PORT asdata (2020:2020:2020) (2056:2056:2056)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1760:1760:1760) (1806:1806:1806)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (974:974:974) (1013:1013:1013)) + (PORT datab (895:895:895) (947:947:947)) + (PORT datac (1141:1141:1141) (1200:1200:1200)) + (PORT datad (964:964:964) (1019:1019:1019)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1919:1919:1919) (2115:2115:2115)) + (PORT datac (1982:1982:1982) (2200:2200:2200)) + (PORT datad (1422:1422:1422) (1531:1531:1531)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1512:1512:1512) (1551:1551:1551)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1938:1938:1938) (2080:2080:2080)) + (PORT d[1] (2501:2501:2501) (2527:2527:2527)) + (PORT d[2] (2588:2588:2588) (2765:2765:2765)) + (PORT d[3] (1139:1139:1139) (1178:1178:1178)) + (PORT d[4] (2415:2415:2415) (2565:2565:2565)) + (PORT d[5] (3170:3170:3170) (3226:3226:3226)) + (PORT d[6] (2192:2192:2192) (2289:2289:2289)) + (PORT d[7] (1851:1851:1851) (1867:1867:1867)) + (PORT d[8] (2510:2510:2510) (2632:2632:2632)) + (PORT d[9] (1705:1705:1705) (1750:1750:1750)) + (PORT d[10] (2512:2512:2512) (2611:2611:2611)) + (PORT d[11] (4013:4013:4013) (4323:4323:4323)) + (PORT d[12] (2512:2512:2512) (2564:2564:2564)) + (PORT clk (1847:1847:1847) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2002:2002:2002) (1964:1964:1964)) + (PORT clk (1847:1847:1847) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT d[0] (2197:2197:2197) (2152:2152:2152)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1836:1836:1836)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (462:462:462)) + (PORT datab (1257:1257:1257) (1300:1300:1300)) + (PORT datac (1234:1234:1234) (1270:1270:1270)) + (PORT datad (1392:1392:1392) (1420:1420:1420)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1920:1920:1920) (2115:2115:2115)) + (PORT datac (1982:1982:1982) (2197:2197:2197)) + (PORT datad (1425:1425:1425) (1529:1529:1529)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (852:852:852) (854:854:854)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2917:2917:2917) (3108:3108:3108)) + (PORT d[1] (3323:3323:3323) (3498:3498:3498)) + (PORT d[2] (1499:1499:1499) (1573:1573:1573)) + (PORT d[3] (3966:3966:3966) (4139:4139:4139)) + (PORT d[4] (2897:2897:2897) (3086:3086:3086)) + (PORT d[5] (4427:4427:4427) (4564:4564:4564)) + (PORT d[6] (2208:2208:2208) (2294:2294:2294)) + (PORT d[7] (3987:3987:3987) (4071:4071:4071)) + (PORT d[8] (1521:1521:1521) (1551:1551:1551)) + (PORT d[9] (2130:2130:2130) (2218:2218:2218)) + (PORT d[10] (2303:2303:2303) (2371:2371:2371)) + (PORT d[11] (3139:3139:3139) (3345:3345:3345)) + (PORT d[12] (4131:4131:4131) (4403:4403:4403)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1928:1928:1928) (1901:1901:1901)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (2721:2721:2721) (2738:2738:2738)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1492:1492:1492) (1564:1564:1564)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (944:944:944) (997:997:997)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (411:411:411) (465:465:465)) + (PORT datab (1252:1252:1252) (1298:1298:1298)) + (PORT datac (1232:1232:1232) (1268:1268:1268)) + (PORT datad (1391:1391:1391) (1418:1418:1418)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1915:1915:1915) (2111:2111:2111)) + (PORT datac (1984:1984:1984) (2198:2198:2198)) + (PORT datad (1420:1420:1420) (1527:1527:1527)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1308:1308:1308) (1374:1374:1374)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2112:2112:2112) (2310:2310:2310)) + (PORT d[1] (2254:2254:2254) (2334:2334:2334)) + (PORT d[2] (1596:1596:1596) (1699:1699:1699)) + (PORT d[3] (2501:2501:2501) (2593:2593:2593)) + (PORT d[4] (2291:2291:2291) (2367:2367:2367)) + (PORT d[5] (1576:1576:1576) (1652:1652:1652)) + (PORT d[6] (1720:1720:1720) (1763:1763:1763)) + (PORT d[7] (2216:2216:2216) (2273:2273:2273)) + (PORT d[8] (2483:2483:2483) (2655:2655:2655)) + (PORT d[9] (1067:1067:1067) (1146:1146:1146)) + (PORT d[10] (1734:1734:1734) (1816:1816:1816)) + (PORT d[11] (1425:1425:1425) (1474:1474:1474)) + (PORT d[12] (1019:1019:1019) (1090:1090:1090)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1513:1513:1513) (1529:1529:1529)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT d[0] (2023:2023:2023) (2001:2001:2001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (1095:1095:1095) (1125:1125:1125)) + (PORT datab (1546:1546:1546) (1595:1595:1595)) + (PORT datac (1417:1417:1417) (1491:1491:1491)) + (PORT datad (1479:1479:1479) (1560:1560:1560)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1299:1299:1299) (1351:1351:1351)) + (PORT datab (1832:1832:1832) (1977:1977:1977)) + (PORT datac (1662:1662:1662) (1715:1715:1715)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (463:463:463)) + (PORT datab (1250:1250:1250) (1293:1293:1293)) + (PORT datac (1232:1232:1232) (1265:1265:1265)) + (PORT datad (1387:1387:1387) (1415:1415:1415)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE CLOCK_50\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (154:154:154) (138:138:138)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\~0) + (DELAY + (ABSOLUTE + (PORT dataa (446:446:446) (541:541:541)) + (PORT datab (973:973:973) (1044:1044:1044)) + (PORT datac (711:711:711) (774:774:774)) + (PORT datad (740:740:740) (796:796:796)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1552:1552:1552)) + (PORT asdata (996:996:996) (1046:1046:1046)) + (PORT ena (817:817:817) (814:814:814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (885:885:885) (926:926:926)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1552:1552:1552)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (817:817:817) (814:814:814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT datac (911:911:911) (966:966:966)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1552:1552:1552)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (817:817:817) (814:814:814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~0) + (DELAY + (ABSOLUTE + (PORT datac (915:915:915) (971:971:971)) + (PORT datad (883:883:883) (943:943:943)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1552:1552:1552)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (817:817:817) (814:814:814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (953:953:953) (1011:1011:1011)) + (PORT datab (911:911:911) (982:982:982)) + (PORT datad (876:876:876) (933:933:933)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1552:1552:1552)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (817:817:817) (814:814:814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1271:1271:1271) (1341:1341:1341)) + (PORT datab (629:629:629) (682:682:682)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (744:744:744) (808:808:808)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~4) + (DELAY + (ABSOLUTE + (PORT dataa (679:679:679) (756:756:756)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~6) + (DELAY + (ABSOLUTE + (PORT datab (941:941:941) (983:983:983)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (946:946:946) (928:928:928)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~8) + (DELAY + (ABSOLUTE + (PORT dataa (952:952:952) (1009:1009:1009)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (946:946:946) (928:928:928)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~10) + (DELAY + (ABSOLUTE + (PORT datab (959:959:959) (1008:1008:1008)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (946:946:946) (928:928:928)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~12) + (DELAY + (ABSOLUTE + (PORT dataa (710:710:710) (781:781:781)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (960:960:960) (1021:1021:1021)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[8\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (447:447:447) (541:541:541)) + (PORT datab (970:970:970) (1040:1040:1040)) + (PORT datac (712:712:712) (775:775:775)) + (PORT datad (738:738:738) (793:793:793)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (980:980:980) (984:984:984)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1125:1125:1125) (1173:1173:1173)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (955:955:955) (1015:1015:1015)) + (PORT datac (181:181:181) (217:217:217)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (980:980:980) (984:984:984)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (446:446:446) (542:542:542)) + (PORT datab (979:979:979) (1050:1050:1050)) + (PORT datac (707:707:707) (769:769:769)) + (PORT datad (744:744:744) (801:801:801)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (375:375:375)) + (PORT datab (378:378:378) (404:404:404)) + (PORT datad (742:742:742) (802:802:802)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1552:1552:1552)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT datac (920:920:920) (981:981:981)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (980:980:980) (984:984:984)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (954:954:954) (1014:1014:1014)) + (PORT datac (182:182:182) (220:220:220)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (980:980:980) (984:984:984)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1277:1277:1277) (1338:1338:1338)) + (PORT clk (1855:1855:1855) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2788:2788:2788) (2939:2939:2939)) + (PORT d[1] (2965:2965:2965) (3112:3112:3112)) + (PORT d[2] (1934:1934:1934) (2074:2074:2074)) + (PORT d[3] (2167:2167:2167) (2291:2291:2291)) + (PORT d[4] (2059:2059:2059) (2183:2183:2183)) + (PORT d[5] (1870:1870:1870) (1973:1973:1973)) + (PORT d[6] (2323:2323:2323) (2459:2459:2459)) + (PORT d[7] (1899:1899:1899) (1971:1971:1971)) + (PORT d[8] (3189:3189:3189) (3291:3291:3291)) + (PORT d[9] (2017:2017:2017) (2163:2163:2163)) + (PORT d[10] (3596:3596:3596) (3781:3781:3781)) + (PORT d[11] (2378:2378:2378) (2513:2513:2513)) + (PORT d[12] (1977:1977:1977) (2130:2130:2130)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1790:1790:1790) (1802:1802:1802)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1883:1883:1883)) + (PORT d[0] (3272:3272:3272) (3205:3205:3205)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1808:1808:1808)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1867:1867:1867) (1911:1911:1911)) + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4490:4490:4490) (4600:4600:4600)) + (PORT d[1] (4410:4410:4410) (4523:4523:4523)) + (PORT d[2] (4538:4538:4538) (4602:4602:4602)) + (PORT d[3] (4281:4281:4281) (4370:4370:4370)) + (PORT d[4] (4381:4381:4381) (4456:4456:4456)) + (PORT d[5] (4418:4418:4418) (4548:4548:4548)) + (PORT d[6] (4415:4415:4415) (4506:4506:4506)) + (PORT d[7] (4377:4377:4377) (4507:4507:4507)) + (PORT d[8] (4645:4645:4645) (4750:4750:4750)) + (PORT d[9] (4429:4429:4429) (4513:4513:4513)) + (PORT d[10] (4448:4448:4448) (4509:4509:4509)) + (PORT d[11] (4414:4414:4414) (4551:4551:4551)) + (PORT d[12] (4365:4365:4365) (4449:4449:4449)) + (PORT clk (1816:1816:1816) (1810:1810:1810)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1810:1810:1810)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1452:1452:1452) (1517:1517:1517)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (218:218:218) (288:288:288)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1166:1166:1166) (1252:1252:1252)) + (PORT datab (1269:1269:1269) (1318:1318:1318)) + (PORT datac (1435:1435:1435) (1491:1491:1491)) + (PORT datad (1131:1131:1131) (1204:1204:1204)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1222:1222:1222) (1232:1232:1232)) + (PORT clk (1846:1846:1846) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3085:3085:3085) (3257:3257:3257)) + (PORT d[1] (2119:2119:2119) (2225:2225:2225)) + (PORT d[2] (1627:1627:1627) (1738:1738:1738)) + (PORT d[3] (1538:1538:1538) (1637:1637:1637)) + (PORT d[4] (2666:2666:2666) (2815:2815:2815)) + (PORT d[5] (1574:1574:1574) (1655:1655:1655)) + (PORT d[6] (2028:2028:2028) (2134:2134:2134)) + (PORT d[7] (1881:1881:1881) (1932:1932:1932)) + (PORT d[8] (3473:3473:3473) (3592:3592:3592)) + (PORT d[9] (1702:1702:1702) (1822:1822:1822)) + (PORT d[10] (1648:1648:1648) (1760:1760:1760)) + (PORT d[11] (1603:1603:1603) (1685:1685:1685)) + (PORT d[12] (1677:1677:1677) (1804:1804:1804)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1434:1434:1434) (1404:1404:1404)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1875:1875:1875)) + (PORT d[0] (2896:2896:2896) (2932:2932:2932)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1801:1801:1801) (1800:1800:1800)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1527:1527:1527) (1568:1568:1568)) + (PORT clk (1811:1811:1811) (1806:1806:1806)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4450:4450:4450) (4537:4537:4537)) + (PORT d[1] (4347:4347:4347) (4424:4424:4424)) + (PORT d[2] (4406:4406:4406) (4467:4467:4467)) + (PORT d[3] (4294:4294:4294) (4374:4374:4374)) + (PORT d[4] (4350:4350:4350) (4425:4425:4425)) + (PORT d[5] (4369:4369:4369) (4474:4474:4474)) + (PORT d[6] (4390:4390:4390) (4426:4426:4426)) + (PORT d[7] (4335:4335:4335) (4462:4462:4462)) + (PORT d[8] (4444:4444:4444) (4576:4576:4576)) + (PORT d[9] (4472:4472:4472) (4577:4577:4577)) + (PORT d[10] (4487:4487:4487) (4606:4606:4606)) + (PORT d[11] (4466:4466:4466) (4582:4582:4582)) + (PORT d[12] (4367:4367:4367) (4452:4452:4452)) + (PORT clk (1807:1807:1807) (1802:1802:1802)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1806:1806:1806)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3185:3185:3185) (3417:3417:3417)) + (PORT d[1] (3332:3332:3332) (3484:3484:3484)) + (PORT d[2] (1430:1430:1430) (1497:1497:1497)) + (PORT d[3] (3934:3934:3934) (4092:4092:4092)) + (PORT d[4] (2918:2918:2918) (3104:3104:3104)) + (PORT d[5] (4421:4421:4421) (4553:4553:4553)) + (PORT d[6] (2796:2796:2796) (2911:2911:2911)) + (PORT d[7] (1726:1726:1726) (1774:1774:1774)) + (PORT d[8] (1980:1980:1980) (2009:2009:2009)) + (PORT d[9] (2141:2141:2141) (2210:2210:2210)) + (PORT d[10] (2312:2312:2312) (2391:2391:2391)) + (PORT d[11] (3101:3101:3101) (3331:3331:3331)) + (PORT d[12] (4277:4277:4277) (4540:4540:4540)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1882:1882:1882)) + (PORT d[0] (1940:1940:1940) (1958:1958:1958)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (1021:1021:1021)) + (PORT datab (305:305:305) (397:397:397)) + (PORT datac (887:887:887) (916:916:916)) + (PORT datad (1045:1045:1045) (1066:1066:1066)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1950:1950:1950) (2052:2052:2052)) + (PORT d[1] (2560:2560:2560) (2687:2687:2687)) + (PORT d[2] (2359:2359:2359) (2509:2509:2509)) + (PORT d[3] (3005:3005:3005) (3111:3111:3111)) + (PORT d[4] (2278:2278:2278) (2362:2362:2362)) + (PORT d[5] (3097:3097:3097) (3185:3185:3185)) + (PORT d[6] (2841:2841:2841) (2965:2965:2965)) + (PORT d[7] (3148:3148:3148) (3225:3225:3225)) + (PORT d[8] (2385:2385:2385) (2466:2466:2466)) + (PORT d[9] (3043:3043:3043) (3176:3176:3176)) + (PORT d[10] (2289:2289:2289) (2338:2338:2338)) + (PORT d[11] (2469:2469:2469) (2631:2631:2631)) + (PORT d[12] (3226:3226:3226) (3408:3408:3408)) + (PORT clk (1868:1868:1868) (1894:1894:1894)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1868:1868:1868) (1894:1894:1894)) + (PORT d[0] (2959:2959:2959) (2871:2871:2871)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1831:1831:1831) (1857:1857:1857)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1020:1020:1020)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (1095:1095:1095) (1122:1122:1122)) + (PORT datab (1468:1468:1468) (1531:1531:1531)) + (PORT datac (178:178:178) (214:214:214)) + (PORT datad (1667:1667:1667) (1758:1758:1758)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1164:1164:1164) (1231:1231:1231)) + (PORT datab (307:307:307) (400:400:400)) + (PORT datac (180:180:180) (216:216:216)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~119) + (DELAY + (ABSOLUTE + (PORT dataa (1416:1416:1416) (1483:1483:1483)) + (PORT datab (2298:2298:2298) (2535:2535:2535)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1231:1231:1231) (1308:1308:1308)) + (PORT datab (635:635:635) (668:668:668)) + (PORT datac (844:844:844) (889:889:889)) + (PORT datad (327:327:327) (350:350:350)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (2195:2195:2195) (2276:2276:2276)) + (PORT datab (637:637:637) (668:668:668)) + (PORT datac (1697:1697:1697) (1792:1792:1792)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (1431:1431:1431) (1450:1450:1450)) + (PORT datac (1093:1093:1093) (1122:1122:1122)) + (PORT datad (344:344:344) (358:358:358)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1131:1131:1131) (1163:1163:1163)) + (PORT datab (1474:1474:1474) (1564:1564:1564)) + (PORT datac (2114:2114:2114) (2227:2227:2227)) + (PORT datad (1651:1651:1651) (1831:1831:1831)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) + (DELAY + (ABSOLUTE + (PORT dataa (1685:1685:1685) (1762:1762:1762)) + (PORT datab (537:537:537) (564:564:564)) + (PORT datac (1014:1014:1014) (1023:1023:1023)) + (PORT datad (1124:1124:1124) (1159:1159:1159)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1155:1155:1155) (1140:1140:1140)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1129:1129:1129) (1166:1166:1166)) + (PORT datab (245:245:245) (289:289:289)) + (PORT datac (847:847:847) (855:855:855)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (253:253:253)) + (PORT datac (1091:1091:1091) (1119:1119:1119)) + (PORT datad (224:224:224) (259:259:259)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (470:470:470)) + (PORT datab (253:253:253) (303:303:303)) + (PORT datac (340:340:340) (362:362:362)) + (PORT datad (217:217:217) (254:254:254)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|ir_\|opcode\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (621:621:621) (634:634:634)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1154:1154:1154) (1207:1207:1207)) + (PORT datab (2915:2915:2915) (2999:2999:2999)) + (PORT datac (1369:1369:1369) (1427:1427:1427)) + (PORT datad (800:800:800) (850:850:850)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1591:1591:1591) (1568:1568:1568)) + (PORT ena (2213:2213:2213) (2213:2213:2213)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1858:1858:1858) (1939:1939:1939)) + (PORT datab (1661:1661:1661) (1809:1809:1809)) + (PORT datac (1723:1723:1723) (1805:1805:1805)) + (PORT datad (882:882:882) (900:900:900)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (711:711:711)) + (PORT datab (826:826:826) (874:874:874)) + (PORT datac (346:346:346) (370:370:370)) + (PORT datad (611:611:611) (623:623:623)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (896:896:896) (958:958:958)) + (PORT datab (1170:1170:1170) (1229:1229:1229)) + (PORT datac (1138:1138:1138) (1178:1178:1178)) + (PORT datad (1161:1161:1161) (1197:1197:1197)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (377:377:377)) + (PORT datab (218:218:218) (257:257:257)) + (PORT datac (867:867:867) (893:893:893)) + (PORT datad (217:217:217) (253:253:253)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (892:892:892)) + (PORT datac (794:794:794) (839:839:839)) + (PORT datad (815:815:815) (833:833:833)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (954:954:954)) + (PORT datab (902:902:902) (931:931:931)) + (PORT datac (806:806:806) (822:822:822)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (639:639:639)) + (PORT datab (1166:1166:1166) (1208:1208:1208)) + (PORT datac (909:909:909) (953:953:953)) + (PORT datad (585:585:585) (613:613:613)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (1349:1349:1349) (1369:1369:1369)) + (PORT datac (628:628:628) (663:663:663)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[6\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (830:830:830) (884:884:884)) + (PORT datab (668:668:668) (707:707:707)) + (PORT datac (825:825:825) (860:860:860)) + (PORT datad (819:819:819) (837:837:837)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (855:855:855)) + (PORT datac (354:354:354) (381:381:381)) + (PORT datad (849:849:849) (871:871:871)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (950:950:950)) + (PORT datab (637:637:637) (657:657:657)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (594:594:594) (606:606:606)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1124:1124:1124) (1160:1160:1160)) + (PORT datab (246:246:246) (293:293:293)) + (PORT datad (1182:1182:1182) (1220:1220:1220)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1184:1184:1184) (1228:1228:1228)) + (PORT d[0] (1316:1316:1316) (1375:1375:1375)) (PORT clk (1845:1845:1845) (1873:1873:1873)) ) ) @@ -30842,19 +35042,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3973:3973:3973) (4187:4187:4187)) - (PORT d[1] (1695:1695:1695) (1858:1858:1858)) - (PORT d[2] (3329:3329:3329) (3462:3462:3462)) - (PORT d[3] (2153:2153:2153) (2276:2276:2276)) - (PORT d[4] (2142:2142:2142) (2252:2252:2252)) - (PORT d[5] (1659:1659:1659) (1777:1777:1777)) - (PORT d[6] (1754:1754:1754) (1804:1804:1804)) - (PORT d[7] (3063:3063:3063) (3210:3210:3210)) - (PORT d[8] (3317:3317:3317) (3546:3546:3546)) - (PORT d[9] (1753:1753:1753) (1814:1814:1814)) - (PORT d[10] (3216:3216:3216) (3426:3426:3426)) - (PORT d[11] (2090:2090:2090) (2212:2212:2212)) - (PORT d[12] (1771:1771:1771) (1834:1834:1834)) + (PORT d[0] (2397:2397:2397) (2589:2589:2589)) + (PORT d[1] (2605:2605:2605) (2682:2682:2682)) + (PORT d[2] (1244:1244:1244) (1312:1312:1312)) + (PORT d[3] (1263:1263:1263) (1323:1323:1323)) + (PORT d[4] (2021:2021:2021) (2110:2110:2110)) + (PORT d[5] (1254:1254:1254) (1323:1323:1323)) + (PORT d[6] (1478:1478:1478) (1511:1511:1511)) + (PORT d[7] (2356:2356:2356) (2492:2492:2492)) + (PORT d[8] (2505:2505:2505) (2668:2668:2668)) + (PORT d[9] (775:775:775) (840:840:840)) + (PORT d[10] (1752:1752:1752) (1831:1831:1831)) + (PORT d[11] (1174:1174:1174) (1217:1217:1217)) + (PORT d[12] (728:728:728) (783:783:783)) (PORT clk (1842:1842:1842) (1869:1869:1869)) ) ) @@ -30867,7 +35067,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2235:2235:2235) (2268:2268:2268)) + (PORT d[0] (1797:1797:1797) (1781:1781:1781)) (PORT clk (1842:1842:1842) (1869:1869:1869)) ) ) @@ -30881,7 +35081,7 @@ (DELAY (ABSOLUTE (PORT clk (1845:1845:1845) (1873:1873:1873)) - (PORT d[0] (2962:2962:2962) (3024:3024:3024)) + (PORT d[0] (1825:1825:1825) (1808:1808:1808)) ) ) ) @@ -30978,48 +35178,308 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~90) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (602:602:602) (616:616:616)) - (PORT datab (976:976:976) (1039:1039:1039)) - (PORT datac (828:828:828) (832:832:832)) - (PORT datad (1142:1142:1142) (1222:1222:1222)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT d[0] (961:961:961) (961:961:961)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2420:2420:2420) (2630:2630:2630)) + (PORT d[1] (1241:1241:1241) (1313:1313:1313)) + (PORT d[2] (1662:1662:1662) (1741:1741:1741)) + (PORT d[3] (1596:1596:1596) (1691:1691:1691)) + (PORT d[4] (2978:2978:2978) (3155:3155:3155)) + (PORT d[5] (1264:1264:1264) (1317:1317:1317)) + (PORT d[6] (1560:1560:1560) (1657:1657:1657)) + (PORT d[7] (1291:1291:1291) (1338:1338:1338)) + (PORT d[8] (1256:1256:1256) (1319:1319:1319)) + (PORT d[9] (1080:1080:1080) (1170:1170:1170)) + (PORT d[10] (1071:1071:1071) (1158:1158:1158)) + (PORT d[11] (2213:2213:2213) (2338:2338:2338)) + (PORT d[12] (1088:1088:1088) (1179:1179:1179)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1220:1220:1220) (1163:1163:1163)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2327:2327:2327) (2302:2302:2302)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) (DELAY (ABSOLUTE - (PORT dataa (700:700:700) (731:731:731)) - (PORT datab (265:265:265) (319:319:319)) - (PORT datac (371:371:371) (408:408:408)) - (PORT datad (1303:1303:1303) (1299:1299:1299)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) (DELAY (ABSOLUTE - (PORT datab (2046:2046:2046) (2179:2179:2179)) - (PORT datac (1157:1157:1157) (1209:1209:1209)) - (PORT datad (1148:1148:1148) (1203:1203:1203)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1310:1310:1310) (1368:1368:1368)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2700:2700:2700) (2899:2899:2899)) + (PORT d[1] (2882:2882:2882) (2995:2995:2995)) + (PORT d[2] (1236:1236:1236) (1287:1287:1287)) + (PORT d[3] (979:979:979) (1033:1033:1033)) + (PORT d[4] (2053:2053:2053) (2138:2138:2138)) + (PORT d[5] (951:951:951) (1003:1003:1003)) + (PORT d[6] (1440:1440:1440) (1451:1451:1451)) + (PORT d[7] (2650:2650:2650) (2803:2803:2803)) + (PORT d[8] (2518:2518:2518) (2699:2699:2699)) + (PORT d[9] (743:743:743) (798:798:798)) + (PORT d[10] (755:755:755) (811:811:811)) + (PORT d[11] (2821:2821:2821) (3003:3003:3003)) + (PORT d[12] (715:715:715) (752:752:752)) + (PORT clk (1838:1838:1838) (1865:1865:1865)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1241:1241:1241) (1217:1217:1217)) + (PORT clk (1838:1838:1838) (1865:1865:1865)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1869:1869:1869)) + (PORT d[0] (1450:1450:1450) (1417:1417:1417)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1801:1801:1801) (1828:1828:1828)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (986:986:986) (991:991:991)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) @@ -31028,8 +35488,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1196:1196:1196) (1209:1209:1209)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (677:677:677) (699:699:699)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) ) ) (TIMINGCHECK @@ -31041,20 +35501,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (4200:4200:4200) (4456:4456:4456)) - (PORT d[1] (2340:2340:2340) (2537:2537:2537)) - (PORT d[2] (3231:3231:3231) (3326:3326:3326)) - (PORT d[3] (2575:2575:2575) (2761:2761:2761)) - (PORT d[4] (2559:2559:2559) (2766:2766:2766)) - (PORT d[5] (2828:2828:2828) (3008:3008:3008)) - (PORT d[6] (1911:1911:1911) (2053:2053:2053)) - (PORT d[7] (2601:2601:2601) (2739:2739:2739)) - (PORT d[8] (3332:3332:3332) (3618:3618:3618)) - (PORT d[9] (2924:2924:2924) (3075:3075:3075)) - (PORT d[10] (5088:5088:5088) (5359:5359:5359)) - (PORT d[11] (1899:1899:1899) (2034:2034:2034)) - (PORT d[12] (2169:2169:2169) (2292:2292:2292)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) + (PORT d[0] (2669:2669:2669) (2901:2901:2901)) + (PORT d[1] (1288:1288:1288) (1360:1360:1360)) + (PORT d[2] (1665:1665:1665) (1743:1743:1743)) + (PORT d[3] (1565:1565:1565) (1640:1640:1640)) + (PORT d[4] (2970:2970:2970) (3148:3148:3148)) + (PORT d[5] (1271:1271:1271) (1329:1329:1329)) + (PORT d[6] (1509:1509:1509) (1602:1602:1602)) + (PORT d[7] (1615:1615:1615) (1649:1649:1649)) + (PORT d[8] (1553:1553:1553) (1653:1653:1653)) + (PORT d[9] (1383:1383:1383) (1478:1478:1478)) + (PORT d[10] (1335:1335:1335) (1424:1424:1424)) + (PORT d[11] (1876:1876:1876) (1999:1999:1999)) + (PORT d[12] (1381:1381:1381) (1486:1486:1486)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) (TIMINGCHECK @@ -31066,8 +35526,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2009:2009:2009) (1965:1965:1965)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) + (PORT d[0] (1236:1236:1236) (1214:1214:1214)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) (TIMINGCHECK @@ -31079,8 +35539,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1854:1854:1854) (1881:1881:1881)) - (PORT d[0] (2224:2224:2224) (2198:2198:2198)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (2701:2701:2701) (2725:2725:2725)) ) ) ) @@ -31089,7 +35549,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -31099,7 +35559,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -31109,7 +35569,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -31119,7 +35579,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -31129,7 +35589,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1814:1814:1814) (1840:1840:1840)) + (PORT clk (1811:1811:1811) (1838:1838:1838)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -31143,7 +35603,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (999:999:999) (1003:1003:1003)) + (PORT clk (996:996:996) (1001:1001:1001)) ) ) ) @@ -31152,7 +35612,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) + (PORT clk (997:997:997) (1002:1002:1002)) ) ) ) @@ -31161,7 +35621,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) + (PORT clk (997:997:997) (1002:1002:1002)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -31171,536 +35631,49 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) + (PORT clk (997:997:997) (1002:1002:1002)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~91) + (INSTANCE D\[6\]\~103) (DELAY (ABSOLUTE - (PORT dataa (837:837:837) (859:859:859)) - (PORT datab (1432:1432:1432) (1519:1519:1519)) - (PORT datac (318:318:318) (339:339:339)) - (PORT datad (1100:1100:1100) (1101:1101:1101)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (698:698:698) (723:723:723)) - (PORT datab (257:257:257) (310:310:310)) - (PORT datac (364:364:364) (402:402:402)) - (PORT datad (1304:1304:1304) (1295:1295:1295)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE CLOCK_50\~inputclkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (154:154:154) (138:138:138)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1044:1044:1044) (1098:1098:1098)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1253:1253:1253) (1340:1340:1340)) - (PORT datab (987:987:987) (1065:1065:1065)) - (PORT datac (971:971:971) (1042:1042:1042)) - (PORT datad (277:277:277) (361:361:361)) + (PORT dataa (1456:1456:1456) (1532:1532:1532)) + (PORT datab (1228:1228:1228) (1286:1286:1286)) + (PORT datad (1444:1444:1444) (1432:1432:1432)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT asdata (1205:1205:1205) (1280:1280:1280)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT datac (896:896:896) (972:972:972)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~0) - (DELAY - (ABSOLUTE - (PORT datac (891:891:891) (968:968:968)) - (PORT datad (1442:1442:1442) (1493:1493:1493)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (1008:1008:1008)) - (PORT datac (1383:1383:1383) (1458:1458:1458)) - (PORT datad (1442:1442:1442) (1493:1493:1493)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (779:779:779)) - (PORT datab (721:721:721) (803:803:803)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~2) - (DELAY - (ABSOLUTE - (PORT datab (644:644:644) (722:722:722)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~4) - (DELAY - (ABSOLUTE - (PORT datab (706:706:706) (772:772:772)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~6) - (DELAY - (ABSOLUTE - (PORT datab (682:682:682) (766:766:766)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~8) - (DELAY - (ABSOLUTE - (PORT dataa (700:700:700) (788:788:788)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~10) - (DELAY - (ABSOLUTE - (PORT dataa (980:980:980) (1052:1052:1052)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~12) - (DELAY - (ABSOLUTE - (PORT datab (694:694:694) (766:766:766)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector6\~0) - (DELAY - (ABSOLUTE - (PORT datab (610:610:610) (638:638:638)) - (PORT datac (561:561:561) (582:582:582)) - (PORT datad (957:957:957) (1029:1029:1029)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[9\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1254:1254:1254) (1344:1344:1344)) - (PORT datab (987:987:987) (1066:1066:1066)) - (PORT datac (976:976:976) (1049:1049:1049)) - (PORT datad (282:282:282) (366:366:366)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (820:820:820) (826:826:826)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~14) - (DELAY - (ABSOLUTE - (PORT datad (708:708:708) (780:780:780)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (677:677:677)) - (PORT datac (792:792:792) (807:807:807)) - (PORT datad (957:957:957) (1033:1033:1033)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (820:820:820) (826:826:826)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1251:1251:1251) (1338:1338:1338)) - (PORT datab (981:981:981) (1058:1058:1058)) - (PORT datac (980:980:980) (1051:1051:1051)) - (PORT datad (285:285:285) (369:369:369)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (644:644:644)) - (PORT datab (1014:1014:1014) (1089:1089:1089)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector3\~0) + (INSTANCE D\[6\]\~104) (DELAY (ABSOLUTE - (PORT datab (613:613:613) (639:639:639)) - (PORT datad (958:958:958) (1031:1031:1031)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (820:820:820) (826:826:826)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector2\~0) - (DELAY - (ABSOLUTE - (PORT datac (618:618:618) (638:638:638)) - (PORT datad (957:957:957) (1029:1029:1029)) + (PORT dataa (1513:1513:1513) (1583:1583:1583)) + (PORT datab (1831:1831:1831) (1977:1977:1977)) + (PORT datac (1437:1437:1437) (1482:1482:1482)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (820:820:820) (826:826:826)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1548:1548:1548) (1620:1620:1620)) - (PORT clk (1864:1864:1864) (1891:1891:1891)) + (PORT d[0] (1260:1260:1260) (1277:1277:1277)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) ) ) (TIMINGCHECK @@ -31712,20 +35685,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2599:2599:2599) (2697:2697:2697)) - (PORT d[1] (2358:2358:2358) (2589:2589:2589)) - (PORT d[2] (2326:2326:2326) (2476:2476:2476)) - (PORT d[3] (1990:1990:1990) (2063:2063:2063)) - (PORT d[4] (2926:2926:2926) (3182:3182:3182)) - (PORT d[5] (2089:2089:2089) (2294:2294:2294)) - (PORT d[6] (1566:1566:1566) (1667:1667:1667)) - (PORT d[7] (1626:1626:1626) (1711:1711:1711)) - (PORT d[8] (2773:2773:2773) (3020:3020:3020)) - (PORT d[9] (2077:2077:2077) (2186:2186:2186)) - (PORT d[10] (2124:2124:2124) (2247:2247:2247)) - (PORT d[11] (3187:3187:3187) (3328:3328:3328)) - (PORT d[12] (2201:2201:2201) (2298:2298:2298)) - (PORT clk (1861:1861:1861) (1887:1887:1887)) + (PORT d[0] (2793:2793:2793) (2950:2950:2950)) + (PORT d[1] (1830:1830:1830) (1942:1942:1942)) + (PORT d[2] (1907:1907:1907) (2035:2035:2035)) + (PORT d[3] (2153:2153:2153) (2289:2289:2289)) + (PORT d[4] (2370:2370:2370) (2502:2502:2502)) + (PORT d[5] (1869:1869:1869) (1972:1972:1972)) + (PORT d[6] (2343:2343:2343) (2464:2464:2464)) + (PORT d[7] (2215:2215:2215) (2277:2277:2277)) + (PORT d[8] (3168:3168:3168) (3268:3268:3268)) + (PORT d[9] (1739:1739:1739) (1883:1883:1883)) + (PORT d[10] (1634:1634:1634) (1763:1763:1763)) + (PORT d[11] (2386:2386:2386) (2535:2535:2535)) + (PORT d[12] (2455:2455:2455) (2610:2610:2610)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) ) ) (TIMINGCHECK @@ -31737,8 +35710,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2768:2768:2768) (2740:2740:2740)) - (PORT clk (1861:1861:1861) (1887:1887:1887)) + (PORT d[0] (1782:1782:1782) (1793:1793:1793)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) ) ) (TIMINGCHECK @@ -31750,8 +35723,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1864:1864:1864) (1891:1891:1891)) - (PORT d[0] (2876:2876:2876) (2827:2827:2827)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (PORT d[0] (3271:3271:3271) (3211:3211:3211)) ) ) ) @@ -31760,7 +35733,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -31770,7 +35743,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -31780,7 +35753,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -31790,7 +35763,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -31800,7 +35773,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1819:1819:1819) (1816:1816:1816)) + (PORT clk (1807:1807:1807) (1805:1805:1805)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -31814,8 +35787,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2147:2147:2147) (2193:2193:2193)) - (PORT clk (1829:1829:1829) (1822:1822:1822)) + (PORT d[0] (1887:1887:1887) (1934:1934:1934)) + (PORT clk (1817:1817:1817) (1811:1811:1811)) ) ) (TIMINGCHECK @@ -31827,20 +35800,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4636:4636:4636) (4688:4688:4688)) - (PORT d[1] (4395:4395:4395) (4383:4383:4383)) - (PORT d[2] (4558:4558:4558) (4624:4624:4624)) - (PORT d[3] (4721:4721:4721) (4720:4720:4720)) - (PORT d[4] (4265:4265:4265) (4262:4262:4262)) - (PORT d[5] (4417:4417:4417) (4355:4355:4355)) - (PORT d[6] (4638:4638:4638) (4708:4708:4708)) - (PORT d[7] (4394:4394:4394) (4343:4343:4343)) - (PORT d[8] (4731:4731:4731) (4705:4705:4705)) - (PORT d[9] (4601:4601:4601) (4791:4791:4791)) - (PORT d[10] (4436:4436:4436) (4445:4445:4445)) - (PORT d[11] (4654:4654:4654) (4682:4682:4682)) - (PORT d[12] (4454:4454:4454) (4466:4466:4466)) - (PORT clk (1825:1825:1825) (1818:1818:1818)) + (PORT d[0] (4443:4443:4443) (4548:4548:4548)) + (PORT d[1] (4421:4421:4421) (4559:4559:4559)) + (PORT d[2] (4547:4547:4547) (4625:4625:4625)) + (PORT d[3] (4250:4250:4250) (4323:4323:4323)) + (PORT d[4] (4357:4357:4357) (4435:4435:4435)) + (PORT d[5] (4381:4381:4381) (4503:4503:4503)) + (PORT d[6] (4351:4351:4351) (4470:4470:4470)) + (PORT d[7] (4377:4377:4377) (4506:4506:4506)) + (PORT d[8] (4630:4630:4630) (4748:4748:4748)) + (PORT d[9] (4422:4422:4422) (4527:4527:4527)) + (PORT d[10] (4416:4416:4416) (4515:4515:4515)) + (PORT d[11] (4442:4442:4442) (4583:4583:4583)) + (PORT d[12] (4386:4386:4386) (4473:4473:4473)) + (PORT clk (1813:1813:1813) (1807:1807:1807)) ) ) (TIMINGCHECK @@ -31852,7 +35825,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1829:1829:1829) (1822:1822:1822)) + (PORT clk (1817:1817:1817) (1811:1811:1811)) ) ) ) @@ -31861,7 +35834,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1830:1830:1830) (1823:1823:1823)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -31871,7 +35844,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1830:1830:1830) (1823:1823:1823)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) ) ) @@ -31881,7 +35854,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1830:1830:1830) (1823:1823:1823)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -31891,7 +35864,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1830:1830:1830) (1823:1823:1823)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -31901,7 +35874,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) (DELAY (ABSOLUTE - (PORT clk (1821:1821:1821) (1818:1818:1818)) + (PORT clk (1809:1809:1809) (1807:1807:1807)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -31910,67 +35883,13 @@ (HOLD d (posedge clk) (159:159:159)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1203:1203:1203) (1298:1298:1298)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1923:1923:1923) (1947:1947:1947)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT asdata (1724:1724:1724) (1774:1774:1774)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (726:726:726)) - (PORT datab (262:262:262) (315:315:315)) - (PORT datac (366:366:366) (405:405:405)) - (PORT datad (1303:1303:1303) (1300:1300:1300)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1513:1513:1513) (1593:1593:1593)) - (PORT clk (1857:1857:1857) (1885:1885:1885)) + (PORT d[0] (1228:1228:1228) (1270:1270:1270)) + (PORT clk (1849:1849:1849) (1877:1877:1877)) ) ) (TIMINGCHECK @@ -31982,20 +35901,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2905:2905:2905) (3002:3002:3002)) - (PORT d[1] (2381:2381:2381) (2621:2621:2621)) - (PORT d[2] (1221:1221:1221) (1275:1275:1275)) - (PORT d[3] (2017:2017:2017) (2080:2080:2080)) - (PORT d[4] (2910:2910:2910) (3179:3179:3179)) - (PORT d[5] (2405:2405:2405) (2631:2631:2631)) - (PORT d[6] (1533:1533:1533) (1608:1608:1608)) - (PORT d[7] (1282:1282:1282) (1365:1365:1365)) - (PORT d[8] (1697:1697:1697) (1794:1794:1794)) - (PORT d[9] (1564:1564:1564) (1639:1639:1639)) - (PORT d[10] (2164:2164:2164) (2311:2311:2311)) - (PORT d[11] (3205:3205:3205) (3345:3345:3345)) - (PORT d[12] (1922:1922:1922) (2027:2027:2027)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (2794:2794:2794) (2951:2951:2951)) + (PORT d[1] (1828:1828:1828) (1938:1938:1938)) + (PORT d[2] (2259:2259:2259) (2395:2395:2395)) + (PORT d[3] (2157:2157:2157) (2295:2295:2295)) + (PORT d[4] (2357:2357:2357) (2500:2500:2500)) + (PORT d[5] (1865:1865:1865) (1964:1964:1964)) + (PORT d[6] (1845:1845:1845) (1965:1965:1965)) + (PORT d[7] (1871:1871:1871) (1918:1918:1918)) + (PORT d[8] (3142:3142:3142) (3254:3254:3254)) + (PORT d[9] (1716:1716:1716) (1858:1858:1858)) + (PORT d[10] (3925:3925:3925) (4111:4111:4111)) + (PORT d[11] (2389:2389:2389) (2540:2540:2540)) + (PORT d[12] (1686:1686:1686) (1819:1819:1819)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) ) ) (TIMINGCHECK @@ -32007,8 +35926,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2709:2709:2709) (2650:2650:2650)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (1704:1704:1704) (1656:1656:1656)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) ) ) (TIMINGCHECK @@ -32020,8 +35939,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1857:1857:1857) (1885:1885:1885)) - (PORT d[0] (3090:3090:3090) (3120:3120:3120)) + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (PORT d[0] (2935:2935:2935) (2984:2984:2984)) ) ) ) @@ -32030,7 +35949,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -32040,7 +35959,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -32050,7 +35969,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -32060,7 +35979,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -32070,7 +35989,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1812:1812:1812) (1810:1810:1810)) + (PORT clk (1804:1804:1804) (1802:1802:1802)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -32084,8 +36003,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2167:2167:2167) (2208:2208:2208)) - (PORT clk (1822:1822:1822) (1816:1816:1816)) + (PORT d[0] (1853:1853:1853) (1917:1917:1917)) + (PORT clk (1814:1814:1814) (1808:1808:1808)) ) ) (TIMINGCHECK @@ -32097,20 +36016,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4624:4624:4624) (4660:4660:4660)) - (PORT d[1] (4162:4162:4162) (4152:4152:4152)) - (PORT d[2] (4263:4263:4263) (4325:4325:4325)) - (PORT d[3] (4486:4486:4486) (4524:4524:4524)) - (PORT d[4] (4333:4333:4333) (4346:4346:4346)) - (PORT d[5] (4356:4356:4356) (4399:4399:4399)) - (PORT d[6] (4459:4459:4459) (4542:4542:4542)) - (PORT d[7] (4161:4161:4161) (4129:4129:4129)) - (PORT d[8] (4409:4409:4409) (4389:4389:4389)) - (PORT d[9] (4581:4581:4581) (4772:4772:4772)) - (PORT d[10] (4418:4418:4418) (4409:4409:4409)) - (PORT d[11] (4535:4535:4535) (4594:4594:4594)) - (PORT d[12] (4450:4450:4450) (4459:4459:4459)) - (PORT clk (1818:1818:1818) (1812:1812:1812)) + (PORT d[0] (4455:4455:4455) (4544:4544:4544)) + (PORT d[1] (4366:4366:4366) (4482:4482:4482)) + (PORT d[2] (4416:4416:4416) (4497:4497:4497)) + (PORT d[3] (4264:4264:4264) (4327:4327:4327)) + (PORT d[4] (4354:4354:4354) (4419:4419:4419)) + (PORT d[5] (4403:4403:4403) (4526:4526:4526)) + (PORT d[6] (4425:4425:4425) (4522:4522:4522)) + (PORT d[7] (4346:4346:4346) (4468:4468:4468)) + (PORT d[8] (4655:4655:4655) (4776:4776:4776)) + (PORT d[9] (4485:4485:4485) (4573:4573:4573)) + (PORT d[10] (4462:4462:4462) (4577:4577:4577)) + (PORT d[11] (4470:4470:4470) (4590:4590:4590)) + (PORT d[12] (4386:4386:4386) (4471:4471:4471)) + (PORT clk (1810:1810:1810) (1804:1804:1804)) ) ) (TIMINGCHECK @@ -32122,7 +36041,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1822:1822:1822) (1816:1816:1816)) + (PORT clk (1814:1814:1814) (1808:1808:1808)) ) ) ) @@ -32131,7 +36050,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) + (PORT clk (1815:1815:1815) (1809:1809:1809)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -32141,7 +36060,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) + (PORT clk (1815:1815:1815) (1809:1809:1809)) ) ) ) @@ -32150,7 +36069,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) + (PORT clk (1815:1815:1815) (1809:1809:1809)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -32160,7 +36079,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) + (PORT clk (1815:1815:1815) (1809:1809:1809)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -32170,20 +36089,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2533:2533:2533) (2623:2623:2623)) - (PORT d[1] (2220:2220:2220) (2418:2418:2418)) - (PORT d[2] (2325:2325:2325) (2498:2498:2498)) - (PORT d[3] (2178:2178:2178) (2338:2338:2338)) - (PORT d[4] (2896:2896:2896) (3148:3148:3148)) - (PORT d[5] (2277:2277:2277) (2465:2465:2465)) - (PORT d[6] (1866:1866:1866) (1991:1991:1991)) - (PORT d[7] (2226:2226:2226) (2303:2303:2303)) - (PORT d[8] (2742:2742:2742) (2980:2980:2980)) - (PORT d[9] (1744:1744:1744) (1855:1855:1855)) - (PORT d[10] (1754:1754:1754) (1834:1834:1834)) - (PORT d[11] (3116:3116:3116) (3240:3240:3240)) - (PORT d[12] (1285:1285:1285) (1359:1359:1359)) - (PORT clk (1869:1869:1869) (1894:1894:1894)) + (PORT d[0] (2492:2492:2492) (2622:2622:2622)) + (PORT d[1] (2647:2647:2647) (2790:2790:2790)) + (PORT d[2] (2231:2231:2231) (2391:2391:2391)) + (PORT d[3] (2097:2097:2097) (2237:2237:2237)) + (PORT d[4] (1753:1753:1753) (1859:1859:1859)) + (PORT d[5] (2146:2146:2146) (2271:2271:2271)) + (PORT d[6] (2408:2408:2408) (2553:2553:2553)) + (PORT d[7] (3417:3417:3417) (3493:3493:3493)) + (PORT d[8] (2875:2875:2875) (2972:2972:2972)) + (PORT d[9] (2055:2055:2055) (2224:2224:2224)) + (PORT d[10] (1917:1917:1917) (2062:2062:2062)) + (PORT d[11] (2114:2114:2114) (2235:2235:2235)) + (PORT d[12] (2265:2265:2265) (2423:2423:2423)) + (PORT clk (1859:1859:1859) (1884:1884:1884)) ) ) (TIMINGCHECK @@ -32195,8 +36114,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1869:1869:1869) (1894:1894:1894)) - (PORT d[0] (2187:2187:2187) (2254:2254:2254)) + (PORT clk (1859:1859:1859) (1884:1884:1884)) + (PORT d[0] (2593:2593:2593) (2672:2672:2672)) ) ) ) @@ -32205,7 +36124,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1870:1870:1870) (1895:1895:1895)) + (PORT clk (1860:1860:1860) (1885:1885:1885)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -32215,7 +36134,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1832:1832:1832) (1857:1857:1857)) + (PORT clk (1822:1822:1822) (1847:1847:1847)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -32229,7 +36148,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1017:1017:1017) (1020:1020:1020)) + (PORT clk (1007:1007:1007) (1010:1010:1010)) ) ) ) @@ -32238,7 +36157,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) + (PORT clk (1008:1008:1008) (1011:1011:1011)) ) ) ) @@ -32247,7 +36166,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) + (PORT clk (1008:1008:1008) (1011:1011:1011)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -32257,22 +36176,22 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) + (PORT clk (1008:1008:1008) (1011:1011:1011)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~87) + (INSTANCE D\[6\]\~100) (DELAY (ABSOLUTE - (PORT dataa (1348:1348:1348) (1400:1400:1400)) - (PORT datab (276:276:276) (364:364:364)) - (PORT datac (1381:1381:1381) (1421:1421:1421)) - (PORT datad (1657:1657:1657) (1684:1684:1684)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1168:1168:1168) (1225:1225:1225)) + (PORT datab (307:307:307) (399:399:399)) + (PORT datac (1148:1148:1148) (1222:1222:1222)) + (PORT datad (1447:1447:1447) (1525:1525:1525)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32283,20 +36202,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3643:3643:3643) (3885:3885:3885)) - (PORT d[1] (2602:2602:2602) (2837:2837:2837)) - (PORT d[2] (2449:2449:2449) (2542:2542:2542)) - (PORT d[3] (2141:2141:2141) (2296:2296:2296)) - (PORT d[4] (2227:2227:2227) (2405:2405:2405)) - (PORT d[5] (2065:2065:2065) (2249:2249:2249)) - (PORT d[6] (1926:1926:1926) (2066:2066:2066)) - (PORT d[7] (1993:1993:1993) (2107:2107:2107)) - (PORT d[8] (2992:2992:2992) (3233:3233:3233)) - (PORT d[9] (2617:2617:2617) (2763:2763:2763)) - (PORT d[10] (4742:4742:4742) (4968:4968:4968)) - (PORT d[11] (2083:2083:2083) (2222:2222:2222)) - (PORT d[12] (2446:2446:2446) (2592:2592:2592)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (1960:1960:1960) (2070:2070:2070)) + (PORT d[1] (3002:3002:3002) (3172:3172:3172)) + (PORT d[2] (2265:2265:2265) (2363:2363:2363)) + (PORT d[3] (3641:3641:3641) (3796:3796:3796)) + (PORT d[4] (2594:2594:2594) (2773:2773:2773)) + (PORT d[5] (4146:4146:4146) (4262:4262:4262)) + (PORT d[6] (2765:2765:2765) (2873:2873:2873)) + (PORT d[7] (3716:3716:3716) (3795:3795:3795)) + (PORT d[8] (2020:2020:2020) (2071:2071:2071)) + (PORT d[9] (2145:2145:2145) (2236:2236:2236)) + (PORT d[10] (2368:2368:2368) (2463:2463:2463)) + (PORT d[11] (2810:2810:2810) (2995:2995:2995)) + (PORT d[12] (3841:3841:3841) (4091:4091:4091)) + (PORT clk (1854:1854:1854) (1880:1880:1880)) ) ) (TIMINGCHECK @@ -32308,8 +36227,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (3176:3176:3176) (3088:3088:3088)) + (PORT clk (1854:1854:1854) (1880:1880:1880)) + (PORT d[0] (2266:2266:2266) (2242:2242:2242)) ) ) ) @@ -32318,7 +36237,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) + (PORT clk (1855:1855:1855) (1881:1881:1881)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -32328,7 +36247,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) + (PORT clk (1817:1817:1817) (1843:1843:1843)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -32342,7 +36261,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) + (PORT clk (1002:1002:1002) (1006:1006:1006)) ) ) ) @@ -32351,7 +36270,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) + (PORT clk (1003:1003:1003) (1007:1007:1007)) ) ) ) @@ -32360,7 +36279,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) + (PORT clk (1003:1003:1003) (1007:1007:1007)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -32370,38 +36289,22 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) + (PORT clk (1003:1003:1003) (1007:1007:1007)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~88) + (INSTANCE D\[6\]\~101) (DELAY (ABSOLUTE - (PORT dataa (1285:1285:1285) (1292:1292:1292)) - (PORT datab (1157:1157:1157) (1165:1165:1165)) - (PORT datac (1614:1614:1614) (1636:1636:1636)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (1434:1434:1434) (1498:1498:1498)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (624:624:624) (685:685:685)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (1307:1307:1307) (1342:1342:1342)) + (PORT datab (1229:1229:1229) (1288:1288:1288)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (1047:1047:1047) (1066:1066:1066)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32409,16 +36312,32 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~111) + (INSTANCE D\[6\]\~102) (DELAY (ABSOLUTE - (PORT dataa (642:642:642) (683:683:683)) - (PORT datab (2010:2010:2010) (2117:2117:2117)) - (PORT datac (918:918:918) (1000:1000:1000)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1163:1163:1163) (1237:1237:1237)) + (PORT datab (309:309:309) (401:401:401)) + (PORT datac (180:180:180) (215:215:215)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~127) + (DELAY + (ABSOLUTE + (PORT dataa (1415:1415:1415) (1483:1483:1483)) + (PORT datab (2298:2298:2298) (2535:2535:2535)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -32434,29 +36353,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~86) + (INSTANCE D\[6\]\~99) (DELAY (ABSOLUTE - (PORT dataa (909:909:909) (967:967:967)) - (PORT datac (1544:1544:1544) (1682:1682:1682)) - (PORT datad (1984:1984:1984) (2079:2079:2079)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (1221:1221:1221) (1330:1330:1330)) + (PORT datac (2534:2534:2534) (2774:2774:2774)) + (PORT datad (1462:1462:1462) (1583:1583:1583)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~100) + (INSTANCE D\[6\]\~114) (DELAY (ABSOLUTE - (PORT dataa (952:952:952) (1002:1002:1002)) - (PORT datab (1379:1379:1379) (1383:1383:1383)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (1558:1558:1558) (1597:1597:1597)) + (PORT datab (435:435:435) (477:477:477)) + (PORT datac (597:597:597) (599:599:599)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32464,16 +36383,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~101) + (INSTANCE D\[6\]\~115) (DELAY (ABSOLUTE - (PORT dataa (947:947:947) (995:995:995)) - (PORT datab (894:894:894) (965:965:965)) - (PORT datac (1645:1645:1645) (1669:1669:1669)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (2243:2243:2243) (2321:2321:2321)) + (PORT datab (436:436:436) (477:477:477)) + (PORT datac (1209:1209:1209) (1322:1322:1322)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -32483,10 +36402,10 @@ (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) (DELAY (ABSOLUTE - (PORT dataa (275:275:275) (336:336:336)) - (PORT datab (1389:1389:1389) (1429:1429:1429)) - (PORT datac (938:938:938) (1004:1004:1004)) - (PORT datad (830:830:830) (833:833:833)) + (PORT dataa (1886:1886:1886) (1930:1930:1930)) + (PORT datab (426:426:426) (464:464:464)) + (PORT datac (349:349:349) (377:377:377)) + (PORT datad (1129:1129:1129) (1163:1163:1163)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -32494,44 +36413,12 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1684:1684:1684) (1826:1826:1826)) - (PORT datab (754:754:754) (857:857:857)) - (PORT datac (961:961:961) (1023:1023:1023)) - (PORT datad (1204:1204:1204) (1263:1263:1263)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) - (DELAY - (ABSOLUTE - (PORT dataa (971:971:971) (1041:1041:1041)) - (PORT datab (973:973:973) (1033:1033:1033)) - (PORT datac (961:961:961) (1024:1024:1024)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|data_pins_\|dout\[6\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT clk (1527:1527:1527) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) (PORT ena (841:841:841) (846:846:846)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -32548,37 +36435,11 @@ (DELAY (ABSOLUTE (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (1178:1178:1178) (1226:1226:1226)) - (PORT datac (224:224:224) (273:273:273)) - (PORT datad (210:210:210) (243:243:243)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|ir_\|opcode\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (195:195:195) (219:219:219)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1107:1107:1107) (1191:1191:1191)) - (PORT datab (909:909:909) (972:972:972)) - (PORT datac (661:661:661) (712:712:712)) - (PORT datad (375:375:375) (392:392:392)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT datab (252:252:252) (303:303:303)) + (PORT datac (575:575:575) (628:628:628)) + (PORT datad (216:216:216) (251:251:251)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32589,74 +36450,28 @@ (INSTANCE z80_\|ir_\|opcode\[6\]) (DELAY (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1557:1557:1557)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (694:694:694) (717:717:717)) + (PORT clrn (1577:1577:1577) (1558:1558:1558)) + (PORT ena (1917:1917:1917) (1918:1918:1918)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~0) + (INSTANCE z80_\|pla_decode_\|Equal13\~0) (DELAY (ABSOLUTE - (PORT datac (1703:1703:1703) (1754:1754:1754)) - (PORT datad (1223:1223:1223) (1322:1322:1322)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1499:1499:1499) (1573:1573:1573)) - (PORT datab (2298:2298:2298) (2366:2366:2366)) - (PORT datac (2132:2132:2132) (2282:2282:2282)) - (PORT datad (1454:1454:1454) (1538:1538:1538)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~2) - (DELAY - (ABSOLUTE - (PORT dataa (450:450:450) (502:502:502)) - (PORT datab (1649:1649:1649) (1644:1644:1644)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (1095:1095:1095) (1127:1127:1127)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) - (DELAY - (ABSOLUTE - (PORT dataa (1962:1962:1962) (2070:2070:2070)) - (PORT datab (1125:1125:1125) (1133:1133:1133)) - (PORT datac (2059:2059:2059) (2181:2181:2181)) - (PORT datad (179:179:179) (207:207:207)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (779:779:779) (847:847:847)) + (PORT datac (1845:1845:1845) (1972:1972:1972)) + (PORT datad (1691:1691:1691) (1766:1766:1766)) + (IOPATH dataa combout (303:303:303) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32664,14 +36479,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~15) + (INSTANCE z80_\|pla_decode_\|Equal38\~2) (DELAY (ABSOLUTE - (PORT dataa (1180:1180:1180) (1214:1214:1214)) - (PORT datab (292:292:292) (354:354:354)) - (PORT datac (259:259:259) (316:316:316)) - (PORT datad (245:245:245) (290:290:290)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (1757:1757:1757) (1850:1850:1850)) + (PORT datab (1655:1655:1655) (1806:1806:1806)) + (PORT datac (1039:1039:1039) (1104:1104:1104)) + (PORT datad (1816:1816:1816) (1892:1892:1892)) + (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -32680,15 +36495,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~16) + (INSTANCE z80_\|interrupts_\|iff1\~0) (DELAY (ABSOLUTE - (PORT dataa (1130:1130:1130) (1202:1202:1202)) - (PORT datab (1172:1172:1172) (1221:1221:1221)) - (PORT datac (419:419:419) (491:491:491)) - (PORT datad (660:660:660) (723:723:723)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (583:583:583) (608:608:608)) + (PORT datab (263:263:263) (345:345:345)) + (PORT datac (614:614:614) (677:677:677)) + (PORT datad (1147:1147:1147) (1181:1181:1181)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32696,43 +36511,171 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~17) + (INSTANCE z80_\|interrupts_\|iff1\~1) (DELAY (ABSOLUTE - (PORT dataa (952:952:952) (1002:1002:1002)) - (PORT datac (1667:1667:1667) (1748:1748:1748)) - (PORT datad (900:900:900) (923:923:923)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1670:1670:1670) (1698:1698:1698)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (366:366:366) (433:433:433)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~18) + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT datab (201:201:201) (240:240:240)) - (PORT datac (891:891:891) (913:913:913)) - (PORT datad (244:244:244) (286:286:286)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (760:760:760) (855:855:855)) + (PORT datad (307:307:307) (414:414:414)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|iff1) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1224:1224:1224) (1228:1228:1228)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (883:883:883)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (1149:1149:1149) (1212:1212:1212)) + (PORT datad (1552:1552:1552) (1679:1679:1679)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|int_armed) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1552:1552:1552)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|DFFE_inst44) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT asdata (1861:1861:1861) (1999:1999:1999)) + (PORT clrn (1590:1590:1590) (1567:1567:1567)) + (PORT ena (993:993:993) (1000:1000:1000)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|in_halt\~0) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (459:459:459)) + (PORT datab (294:294:294) (388:388:388)) + (PORT datad (252:252:252) (326:326:326)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~19) + (INSTANCE z80_\|pla_decode_\|Equal77\~1) (DELAY (ABSOLUTE - (PORT dataa (369:369:369) (390:390:390)) - (PORT datab (631:631:631) (659:659:659)) - (PORT datac (1160:1160:1160) (1204:1204:1204)) - (PORT datad (606:606:606) (623:623:623)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (2306:2306:2306) (2453:2453:2453)) + (PORT datab (1239:1239:1239) (1285:1285:1285)) + (PORT datac (1152:1152:1152) (1203:1203:1203)) + (PORT datad (1219:1219:1219) (1229:1229:1229)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|in_halt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (248:248:248)) + (PORT datab (703:703:703) (722:722:722)) + (PORT datad (905:905:905) (936:936:936)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|in_halt) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1590:1590:1590) (1567:1567:1567)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1544:1544:1544) (1649:1649:1649)) + (PORT datab (634:634:634) (661:661:661)) + (PORT datac (1250:1250:1250) (1279:1279:1279)) + (PORT datad (632:632:632) (654:654:654)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32740,14 +36683,222 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~20) + (INSTANCE z80_\|execute_\|fMRead\~35) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (999:999:999) (1032:1032:1032)) - (PORT datac (582:582:582) (614:614:614)) - (PORT datad (221:221:221) (263:263:263)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT dataa (220:220:220) (270:270:270)) + (PORT datab (218:218:218) (257:257:257)) + (PORT datac (590:590:590) (610:610:610)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (949:949:949)) + (PORT datab (631:631:631) (656:656:656)) + (PORT datac (835:835:835) (860:860:860)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (935:935:935)) + (PORT datab (1457:1457:1457) (1548:1548:1548)) + (PORT datac (589:589:589) (657:657:657)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (716:716:716)) + (PORT datab (861:861:861) (893:893:893)) + (PORT datac (854:854:854) (895:895:895)) + (PORT datad (1006:1006:1006) (1056:1056:1056)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1114:1114:1114) (1204:1204:1204)) + (PORT datab (1249:1249:1249) (1294:1294:1294)) + (PORT datac (1289:1289:1289) (1340:1340:1340)) + (PORT datad (1967:1967:1967) (2036:2036:2036)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (945:945:945)) + (PORT datab (1896:1896:1896) (1915:1915:1915)) + (PORT datac (1165:1165:1165) (1201:1201:1201)) + (PORT datad (827:827:827) (850:850:850)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~31) + (DELAY + (ABSOLUTE + (PORT dataa (453:453:453) (492:492:492)) + (PORT datab (1030:1030:1030) (1095:1095:1095)) + (PORT datac (1325:1325:1325) (1379:1379:1379)) + (PORT datad (1076:1076:1076) (1126:1126:1126)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (171:171:171) (202:202:202)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~37) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (677:677:677)) + (PORT datab (1463:1463:1463) (1517:1517:1517)) + (PORT datac (1482:1482:1482) (1554:1554:1554)) + (PORT datad (1619:1619:1619) (1692:1692:1692)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (660:660:660)) + (PORT datab (216:216:216) (261:261:261)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~24) + (DELAY + (ABSOLUTE + (PORT dataa (2969:2969:2969) (3039:3039:3039)) + (PORT datab (641:641:641) (702:702:702)) + (PORT datac (613:613:613) (625:625:625)) + (PORT datad (215:215:215) (241:241:241)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~25) + (DELAY + (ABSOLUTE + (PORT dataa (428:428:428) (478:478:478)) + (PORT datab (895:895:895) (922:922:922)) + (PORT datac (1121:1121:1121) (1142:1142:1142)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (645:645:645)) + (PORT datab (644:644:644) (686:686:686)) + (PORT datac (188:188:188) (228:228:228)) + (PORT datad (1149:1149:1149) (1174:1174:1174)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1159:1159:1159) (1207:1207:1207)) + (PORT datab (916:916:916) (951:951:951)) + (PORT datac (188:188:188) (231:231:231)) + (PORT datad (1147:1147:1147) (1187:1187:1187)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -32756,15 +36907,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~24) + (INSTANCE z80_\|execute_\|fMRead\~12) (DELAY (ABSOLUTE - (PORT dataa (1300:1300:1300) (1351:1351:1351)) - (PORT datab (940:940:940) (958:958:958)) - (PORT datac (1822:1822:1822) (1884:1884:1884)) - (PORT datad (931:931:931) (981:981:981)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (870:870:870) (921:921:921)) + (PORT datab (1617:1617:1617) (1648:1648:1648)) + (PORT datac (1115:1115:1115) (1177:1177:1177)) + (PORT datad (1411:1411:1411) (1437:1437:1437)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (886:886:886) (911:911:911)) + (PORT datac (648:648:648) (694:694:694)) + (PORT datad (1181:1181:1181) (1217:1217:1217)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (944:944:944)) + (PORT datab (1282:1282:1282) (1314:1314:1314)) + (PORT datac (648:648:648) (693:693:693)) + (PORT datad (1402:1402:1402) (1434:1434:1434)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32772,14 +36955,334 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~25) + (INSTANCE z80_\|execute_\|fMRead\~15) (DELAY (ABSOLUTE - (PORT dataa (647:647:647) (673:673:673)) - (PORT datab (255:255:255) (313:313:313)) - (PORT datac (175:175:175) (209:209:209)) - (PORT datad (945:945:945) (988:988:988)) + (PORT dataa (1449:1449:1449) (1502:1502:1502)) + (PORT datab (1085:1085:1085) (1133:1133:1133)) + (PORT datac (651:651:651) (687:687:687)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (966:966:966) (1015:1015:1015)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (257:257:257)) + (PORT datab (654:654:654) (703:703:703)) + (PORT datac (610:610:610) (654:654:654)) + (PORT datad (624:624:624) (633:633:633)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1183:1183:1183)) + (PORT datab (954:954:954) (995:995:995)) + (PORT datac (602:602:602) (625:625:625)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~36) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (952:952:952)) + (PORT datab (673:673:673) (691:691:691)) + (PORT datac (958:958:958) (973:973:973)) + (PORT datad (1082:1082:1082) (1103:1103:1103)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re) + (DELAY + (ABSOLUTE + (PORT datab (1455:1455:1455) (1545:1545:1545)) + (PORT datac (1016:1016:1016) (1022:1022:1022)) + (PORT datad (509:509:509) (525:525:525)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~103) + (DELAY + (ABSOLUTE + (PORT dataa (497:497:497) (577:577:577)) + (PORT datac (977:977:977) (1064:1064:1064)) + (PORT datad (614:614:614) (684:684:684)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (774:774:774) (853:853:853)) + (PORT datac (679:679:679) (730:730:730)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (431:431:431)) + (PORT datab (763:763:763) (849:849:849)) + (PORT datac (702:702:702) (763:763:763)) + (PORT datad (193:193:193) (229:229:229)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (870:870:870)) + (PORT datab (200:200:200) (238:238:238)) + (PORT datad (591:591:591) (603:603:603)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (730:730:730) (820:820:820)) + (PORT datac (935:935:935) (1021:1021:1021)) + (PORT datad (904:904:904) (975:975:975)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (781:781:781) (879:879:879)) + (PORT datab (652:652:652) (684:684:684)) + (PORT datac (896:896:896) (981:981:981)) + (PORT datad (267:267:267) (345:345:345)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (283:283:283) (376:376:376)) + (PORT datab (931:931:931) (1011:1011:1011)) + (PORT datac (928:928:928) (989:989:989)) + (PORT datad (753:753:753) (839:839:839)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~129) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (1020:1020:1020)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~1) + (DELAY + (ABSOLUTE + (PORT datab (789:789:789) (873:873:873)) + (PORT datac (683:683:683) (751:751:751)) + (PORT datad (735:735:735) (817:817:817)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~105) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (412:412:412)) + (PORT datab (740:740:740) (807:807:807)) + (PORT datac (888:888:888) (952:952:952)) + (PORT datad (199:199:199) (235:235:235)) (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (399:399:399)) + (PORT datab (624:624:624) (685:685:685)) + (PORT datac (677:677:677) (727:727:727)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~130) + (DELAY + (ABSOLUTE + (PORT dataa (786:786:786) (870:870:870)) + (PORT datab (416:416:416) (496:496:496)) + (PORT datad (936:936:936) (1016:1016:1016)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) + (DELAY + (ABSOLUTE + (PORT dataa (1227:1227:1227) (1254:1254:1254)) + (PORT datab (632:632:632) (647:647:647)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (1268:1268:1268) (1342:1342:1342)) + (PORT datab (242:242:242) (324:324:324)) + (PORT datac (882:882:882) (907:907:907)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -32788,79 +37291,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~39) (DELAY (ABSOLUTE - (PORT dataa (361:361:361) (501:501:501)) - (PORT datab (1351:1351:1351) (1413:1413:1413)) - (PORT datac (1147:1147:1147) (1181:1181:1181)) - (PORT datad (1196:1196:1196) (1243:1243:1243)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1065:1065:1065) (1137:1137:1137)) + (PORT datac (848:848:848) (867:867:867)) + (PORT datad (708:708:708) (782:782:782)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~100) (DELAY (ABSOLUTE - (PORT dataa (556:556:556) (578:578:578)) - (PORT datab (623:623:623) (651:651:651)) - (PORT datac (663:663:663) (695:695:695)) - (PORT datad (679:679:679) (697:697:697)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_yf) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (702:702:702)) - (PORT datab (900:900:900) (949:949:949)) - (PORT datac (666:666:666) (693:693:693)) - (PORT datad (888:888:888) (905:905:905)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (740:740:740) (830:830:830)) + (PORT datac (1262:1262:1262) (1334:1334:1334)) + (PORT datad (969:969:969) (1032:1032:1032)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~14) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) (DELAY (ABSOLUTE - (PORT dataa (969:969:969) (987:987:987)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (948:948:948) (982:982:982)) - (PORT datad (864:864:864) (880:880:880)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (1060:1060:1060) (1130:1130:1130)) + (PORT datac (759:759:759) (838:838:838)) + (PORT datad (189:189:189) (222:222:222)) + (IOPATH dataa combout (303:303:303) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32868,15 +37335,60 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~15) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~99) (DELAY (ABSOLUTE - (PORT dataa (685:685:685) (717:717:717)) - (PORT datab (1197:1197:1197) (1212:1212:1212)) - (PORT datac (1119:1119:1119) (1150:1150:1150)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (772:772:772) (855:855:855)) + (PORT datac (971:971:971) (1051:1051:1051)) + (PORT datad (645:645:645) (724:724:724)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (948:948:948)) + (PORT datab (888:888:888) (920:920:920)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1548:1548:1548) (1540:1540:1540)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~97) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (395:395:395)) + (PORT datab (1062:1062:1062) (1131:1131:1131)) + (PORT datac (708:708:708) (773:773:773)) + (PORT datad (190:190:190) (222:222:222)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32884,671 +37396,383 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~107) + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~98) (DELAY (ABSOLUTE - (PORT dataa (1749:1749:1749) (1858:1858:1858)) - (PORT datab (1231:1231:1231) (1298:1298:1298)) - (PORT datac (1559:1559:1559) (1700:1700:1700)) - (PORT datad (1126:1126:1126) (1171:1171:1171)) + (PORT dataa (998:998:998) (1087:1087:1087)) + (PORT datab (920:920:920) (962:962:962)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1548:1548:1548) (1540:1540:1540)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (1168:1168:1168) (1214:1214:1214)) + (PORT datab (714:714:714) (771:771:771)) + (PORT datac (214:214:214) (291:291:291)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~108) + (DELAY + (ABSOLUTE + (PORT dataa (1236:1236:1236) (1327:1327:1327)) + (PORT datac (984:984:984) (1047:1047:1047)) + (PORT datad (651:651:651) (732:732:732)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~109) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (256:256:256)) + (PORT datab (229:229:229) (271:271:271)) + (PORT datac (705:705:705) (774:774:774)) + (PORT datad (204:204:204) (235:235:235)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~110) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (257:257:257)) + (PORT datab (923:923:923) (952:952:952)) + (PORT datad (573:573:573) (604:604:604)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1511:1511:1511) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1538:1538:1538)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~111) + (DELAY + (ABSOLUTE + (PORT dataa (1064:1064:1064) (1138:1138:1138)) + (PORT datab (420:420:420) (502:502:502)) + (PORT datac (998:998:998) (1056:1056:1056)) + (PORT datad (603:603:603) (663:663:663)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~112) + (DELAY + (ABSOLUTE + (PORT dataa (302:302:302) (404:404:404)) + (PORT datab (201:201:201) (240:240:240)) + (PORT datac (665:665:665) (729:729:729)) + (PORT datad (635:635:635) (652:652:652)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~132) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (907:907:907)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datad (711:711:711) (785:785:785)) (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~133) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (663:663:663)) + (PORT datab (759:759:759) (844:844:844)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1511:1511:1511) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1538:1538:1538)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (328:328:328)) + (PORT datab (909:909:909) (965:965:965)) + (PORT datac (217:217:217) (293:293:293)) + (PORT datad (1398:1398:1398) (1439:1439:1439)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~94) + (DELAY + (ABSOLUTE + (PORT dataa (1235:1235:1235) (1327:1327:1327)) + (PORT datab (1300:1300:1300) (1375:1375:1375)) + (PORT datac (685:685:685) (784:784:784)) + (PORT datad (717:717:717) (806:806:806)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (1235:1235:1235) (1326:1326:1326)) + (PORT datac (985:985:985) (1050:1050:1050)) + (PORT datad (653:653:653) (736:736:736)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~95) + (DELAY + (ABSOLUTE + (PORT dataa (1042:1042:1042) (1125:1125:1125)) + (PORT datab (948:948:948) (1016:1016:1016)) + (PORT datac (900:900:900) (914:914:914)) + (PORT datad (729:729:729) (803:803:803)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) (DELAY (ABSOLUTE - (PORT d[0] (1190:1190:1190) (1230:1230:1230)) - (PORT clk (1845:1845:1845) (1873:1873:1873)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (208:208:208) (249:249:249)) + (PORT datad (619:619:619) (630:630:630)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1511:1511:1511) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1538:1538:1538)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) + (HOLD d (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~91) (DELAY (ABSOLUTE - (PORT d[0] (3686:3686:3686) (3900:3900:3900)) - (PORT d[1] (1735:1735:1735) (1904:1904:1904)) - (PORT d[2] (3045:3045:3045) (3164:3164:3164)) - (PORT d[3] (1901:1901:1901) (2003:2003:2003)) - (PORT d[4] (2206:2206:2206) (2342:2342:2342)) - (PORT d[5] (2677:2677:2677) (2865:2865:2865)) - (PORT d[6] (2060:2060:2060) (2133:2133:2133)) - (PORT d[7] (2769:2769:2769) (2894:2894:2894)) - (PORT d[8] (3033:3033:3033) (3241:3241:3241)) - (PORT d[9] (2831:2831:2831) (2926:2926:2926)) - (PORT d[10] (3516:3516:3516) (3751:3751:3751)) - (PORT d[11] (1807:1807:1807) (1907:1907:1907)) - (PORT d[12] (2081:2081:2081) (2168:2168:2168)) - (PORT clk (1842:1842:1842) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1939:1939:1939) (1956:1956:1956)) - (PORT clk (1842:1842:1842) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1873:1873:1873)) - (PORT d[0] (2676:2676:2676) (2715:2715:2715)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1805:1805:1805) (1832:1832:1832)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (990:990:990) (995:995:995)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1180:1180:1180) (1209:1209:1209)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3984:3984:3984) (4216:4216:4216)) - (PORT d[1] (1704:1704:1704) (1855:1855:1855)) - (PORT d[2] (3307:3307:3307) (3443:3443:3443)) - (PORT d[3] (1880:1880:1880) (1997:1997:1997)) - (PORT d[4] (1863:1863:1863) (1963:1963:1963)) - (PORT d[5] (1643:1643:1643) (1769:1769:1769)) - (PORT d[6] (1761:1761:1761) (1817:1817:1817)) - (PORT d[7] (3056:3056:3056) (3189:3189:3189)) - (PORT d[8] (3324:3324:3324) (3551:3551:3551)) - (PORT d[9] (2869:2869:2869) (2985:2985:2985)) - (PORT d[10] (3454:3454:3454) (3652:3652:3652)) - (PORT d[11] (1540:1540:1540) (1618:1618:1618)) - (PORT d[12] (1726:1726:1726) (1787:1787:1787)) - (PORT clk (1840:1840:1840) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1932:1932:1932) (1890:1890:1890)) - (PORT clk (1840:1840:1840) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1871:1871:1871)) - (PORT d[0] (2406:2406:2406) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1803:1803:1803) (1830:1830:1830)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (988:988:988) (993:993:993)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1218:1218:1218) (1268:1268:1268)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3686:3686:3686) (3901:3901:3901)) - (PORT d[1] (1692:1692:1692) (1858:1858:1858)) - (PORT d[2] (2977:2977:2977) (3118:3118:3118)) - (PORT d[3] (2124:2124:2124) (2230:2230:2230)) - (PORT d[4] (2237:2237:2237) (2352:2352:2352)) - (PORT d[5] (2684:2684:2684) (2875:2875:2875)) - (PORT d[6] (1801:1801:1801) (1880:1880:1880)) - (PORT d[7] (2772:2772:2772) (2901:2901:2901)) - (PORT d[8] (3346:3346:3346) (3575:3575:3575)) - (PORT d[9] (2889:2889:2889) (3004:3004:3004)) - (PORT d[10] (3484:3484:3484) (3709:3709:3709)) - (PORT d[11] (1816:1816:1816) (1924:1924:1924)) - (PORT d[12] (2023:2023:2023) (2090:2090:2090)) - (PORT clk (1840:1840:1840) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1889:1889:1889) (1883:1883:1883)) - (PORT clk (1840:1840:1840) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1871:1871:1871)) - (PORT d[0] (2482:2482:2482) (2488:2488:2488)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1803:1803:1803) (1830:1830:1830)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (988:988:988) (993:993:993)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + (PORT dataa (509:509:509) (588:588:588)) + (PORT datab (887:887:887) (942:942:942)) + (PORT datac (616:616:616) (637:637:637)) + (PORT datad (190:190:190) (222:222:222)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~4) + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~92) (DELAY (ABSOLUTE - (PORT dataa (1446:1446:1446) (1499:1499:1499)) - (PORT datab (1431:1431:1431) (1517:1517:1517)) - (PORT datac (1141:1141:1141) (1132:1132:1132)) - (PORT datad (1111:1111:1111) (1136:1136:1136)) + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (973:973:973) (1052:1052:1052)) + (PORT datad (462:462:462) (533:533:533)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) (DELAY (ABSOLUTE - (PORT d[0] (1272:1272:1272) (1326:1326:1326)) - (PORT clk (1855:1855:1855) (1883:1883:1883)) + (PORT clk (1504:1504:1504) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) + (HOLD d (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~72) (DELAY (ABSOLUTE - (PORT d[0] (2887:2887:2887) (3004:3004:3004)) - (PORT d[1] (2662:2662:2662) (2916:2916:2916)) - (PORT d[2] (1218:1218:1218) (1257:1257:1257)) - (PORT d[3] (1701:1701:1701) (1750:1750:1750)) - (PORT d[4] (2885:2885:2885) (3119:3119:3119)) - (PORT d[5] (2382:2382:2382) (2607:2607:2607)) - (PORT d[6] (1263:1263:1263) (1339:1339:1339)) - (PORT d[7] (1323:1323:1323) (1404:1404:1404)) - (PORT d[8] (1739:1739:1739) (1814:1814:1814)) - (PORT d[9] (1262:1262:1262) (1335:1335:1335)) - (PORT d[10] (2409:2409:2409) (2560:2560:2560)) - (PORT d[11] (3166:3166:3166) (3381:3381:3381)) - (PORT d[12] (2205:2205:2205) (2307:2307:2307)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1501:1501:1501) (1496:1496:1496)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (PORT d[0] (2128:2128:2128) (2120:2120:2120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1842:1842:1842)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + (PORT dataa (711:711:711) (751:751:751)) + (PORT datab (240:240:240) (322:322:322)) + (PORT datac (2427:2427:2427) (2603:2603:2603)) + (PORT datad (882:882:882) (935:935:935)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) + (INSTANCE D\[3\]\~76) (DELAY (ABSOLUTE - (PORT dataa (1130:1130:1130) (1175:1175:1175)) - (PORT datab (1704:1704:1704) (1781:1781:1781)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1426:1426:1426) (1482:1482:1482)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (888:888:888) (920:920:920)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (344:344:344) (365:365:365)) + (PORT datad (615:615:615) (626:626:626)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~122) + (DELAY + (ABSOLUTE + (PORT dataa (1105:1105:1105) (1131:1131:1131)) + (PORT datab (1259:1259:1259) (1374:1374:1374)) + (PORT datac (2575:2575:2575) (2806:2806:2806)) + (PORT datad (635:635:635) (671:671:671)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1607:1607:1607) (1720:1720:1720)) - (PORT clk (1852:1852:1852) (1880:1880:1880)) + (PORT d[0] (1120:1120:1120) (1113:1113:1113)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) ) ) (TIMINGCHECK @@ -33557,307 +37781,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3186:3186:3186) (3300:3300:3300)) - (PORT d[1] (2007:2007:2007) (2188:2188:2188)) - (PORT d[2] (2193:2193:2193) (2290:2290:2290)) - (PORT d[3] (1861:1861:1861) (1989:1989:1989)) - (PORT d[4] (2485:2485:2485) (2606:2606:2606)) - (PORT d[5] (2236:2236:2236) (2402:2402:2402)) - (PORT d[6] (1711:1711:1711) (1755:1755:1755)) - (PORT d[7] (1687:1687:1687) (1776:1776:1776)) - (PORT d[8] (2608:2608:2608) (2791:2791:2791)) - (PORT d[9] (1955:1955:1955) (2077:2077:2077)) - (PORT d[10] (2011:2011:2011) (2111:2111:2111)) - (PORT d[11] (2425:2425:2425) (2555:2555:2555)) - (PORT d[12] (2552:2552:2552) (2625:2625:2625)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2563:2563:2563) (2536:2536:2536)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (PORT d[0] (3968:3968:3968) (4054:4054:4054)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1805:1805:1805)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1738:1738:1738) (1727:1727:1727)) - (PORT clk (1817:1817:1817) (1811:1811:1811)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4391:4391:4391) (4458:4458:4458)) - (PORT d[1] (4215:4215:4215) (4261:4261:4261)) - (PORT d[2] (4322:4322:4322) (4388:4388:4388)) - (PORT d[3] (4683:4683:4683) (4718:4718:4718)) - (PORT d[4] (4355:4355:4355) (4366:4366:4366)) - (PORT d[5] (4618:4618:4618) (4672:4672:4672)) - (PORT d[6] (4745:4745:4745) (4781:4781:4781)) - (PORT d[7] (4330:4330:4330) (4399:4399:4399)) - (PORT d[8] (4420:4420:4420) (4455:4455:4455)) - (PORT d[9] (4477:4477:4477) (4721:4721:4721)) - (PORT d[10] (4604:4604:4604) (4600:4600:4600)) - (PORT d[11] (4406:4406:4406) (4437:4437:4437)) - (PORT d[12] (4503:4503:4503) (4638:4638:4638)) - (PORT clk (1813:1813:1813) (1807:1807:1807)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1817:1817:1817) (1811:1811:1811)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2857:2857:2857) (2972:2972:2972)) - (PORT d[1] (1730:1730:1730) (1897:1897:1897)) - (PORT d[2] (1950:1950:1950) (2070:2070:2070)) - (PORT d[3] (1897:1897:1897) (2023:2023:2023)) - (PORT d[4] (2739:2739:2739) (2895:2895:2895)) - (PORT d[5] (2232:2232:2232) (2412:2412:2412)) - (PORT d[6] (1964:1964:1964) (2031:2031:2031)) - (PORT d[7] (2136:2136:2136) (2268:2268:2268)) - (PORT d[8] (2383:2383:2383) (2561:2561:2561)) - (PORT d[9] (1973:1973:1973) (2079:2079:2079)) - (PORT d[10] (1681:1681:1681) (1740:1740:1740)) - (PORT d[11] (2036:2036:2036) (2101:2101:2101)) - (PORT d[12] (2509:2509:2509) (2578:2578:2578)) - (PORT clk (1857:1857:1857) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1882:1882:1882)) - (PORT d[0] (2716:2716:2716) (2794:2794:2794)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3922:3922:3922) (4160:4160:4160)) - (PORT d[1] (2875:2875:2875) (3108:3108:3108)) - (PORT d[2] (2719:2719:2719) (2815:2815:2815)) - (PORT d[3] (2274:2274:2274) (2436:2436:2436)) - (PORT d[4] (2511:2511:2511) (2691:2691:2691)) - (PORT d[5] (2520:2520:2520) (2696:2696:2696)) - (PORT d[6] (1898:1898:1898) (2018:2018:2018)) - (PORT d[7] (2284:2284:2284) (2398:2398:2398)) - (PORT d[8] (3090:3090:3090) (3363:3363:3363)) - (PORT d[9] (2691:2691:2691) (2835:2835:2835)) - (PORT d[10] (4531:4531:4531) (4774:4774:4774)) - (PORT d[11] (1925:1925:1925) (2083:2083:2083)) - (PORT d[12] (2422:2422:2422) (2553:2553:2553)) + (PORT d[0] (2540:2540:2540) (2718:2718:2718)) + (PORT d[1] (3611:3611:3611) (3828:3828:3828)) + (PORT d[2] (2390:2390:2390) (2485:2485:2485)) + (PORT d[3] (4294:4294:4294) (4502:4502:4502)) + (PORT d[4] (3192:3192:3192) (3431:3431:3431)) + (PORT d[5] (4755:4755:4755) (4922:4922:4922)) + (PORT d[6] (2539:2539:2539) (2642:2642:2642)) + (PORT d[7] (1407:1407:1407) (1444:1444:1444)) + (PORT d[8] (2834:2834:2834) (2992:2992:2992)) + (PORT d[9] (1811:1811:1811) (1840:1840:1840)) + (PORT d[10] (1723:1723:1723) (1759:1759:1759)) + (PORT d[11] (3413:3413:3413) (3683:3683:3683)) + (PORT d[12] (4600:4600:4600) (4890:4890:4890)) (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) @@ -33867,27 +37806,70 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) (DELAY (ABSOLUTE + (PORT d[0] (1678:1678:1678) (1622:1622:1622)) (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (3644:3644:3644) (3567:3567:3567)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (2247:2247:2247) (2230:2230:2230)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1820:1820:1820) (1846:1846:1846)) @@ -33901,7 +37883,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1005:1005:1005) (1009:1009:1009)) @@ -33910,7 +37892,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -33919,7 +37901,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -33929,7 +37911,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -33938,12 +37920,28 @@ ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~79) (DELAY (ABSOLUTE - (PORT d[0] (1502:1502:1502) (1566:1566:1566)) - (PORT clk (1869:1869:1869) (1895:1895:1895)) + (PORT dataa (1166:1166:1166) (1276:1276:1276)) + (PORT datab (667:667:667) (705:705:705)) + (PORT datac (1386:1386:1386) (1467:1467:1467)) + (PORT datad (1101:1101:1101) (1113:1113:1113)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1145:1145:1145) (1137:1137:1137)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) ) ) (TIMINGCHECK @@ -33952,23 +37950,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2818:2818:2818) (2896:2896:2896)) - (PORT d[1] (2077:2077:2077) (2294:2294:2294)) - (PORT d[2] (2223:2223:2223) (2370:2370:2370)) - (PORT d[3] (2274:2274:2274) (2375:2375:2375)) - (PORT d[4] (2928:2928:2928) (3204:3204:3204)) - (PORT d[5] (2379:2379:2379) (2550:2550:2550)) - (PORT d[6] (1572:1572:1572) (1678:1678:1678)) - (PORT d[7] (1564:1564:1564) (1666:1666:1666)) - (PORT d[8] (2761:2761:2761) (2991:2991:2991)) - (PORT d[9] (2092:2092:2092) (2225:2225:2225)) - (PORT d[10] (1872:1872:1872) (1997:1997:1997)) - (PORT d[11] (2890:2890:2890) (3011:3011:3011)) - (PORT d[12] (1605:1605:1605) (1686:1686:1686)) - (PORT clk (1866:1866:1866) (1891:1891:1891)) + (PORT d[0] (1692:1692:1692) (1821:1821:1821)) + (PORT d[1] (2831:2831:2831) (2904:2904:2904)) + (PORT d[2] (2412:2412:2412) (2479:2479:2479)) + (PORT d[3] (4272:4272:4272) (4479:4479:4479)) + (PORT d[4] (990:990:990) (1023:1023:1023)) + (PORT d[5] (2242:2242:2242) (2271:2271:2271)) + (PORT d[6] (2540:2540:2540) (2643:2643:2643)) + (PORT d[7] (1371:1371:1371) (1386:1386:1386)) + (PORT d[8] (2806:2806:2806) (2960:2960:2960)) + (PORT d[9] (1487:1487:1487) (1517:1517:1517)) + (PORT d[10] (1989:1989:1989) (2026:2026:2026)) + (PORT d[11] (3414:3414:3414) (3684:3684:3684)) + (PORT d[12] (4681:4681:4681) (4989:4989:4989)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) ) ) (TIMINGCHECK @@ -33977,11 +37975,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2511:2511:2511) (2509:2509:2509)) - (PORT clk (1866:1866:1866) (1891:1891:1891)) + (PORT d[0] (2538:2538:2538) (2548:2548:2548)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) ) ) (TIMINGCHECK @@ -33990,17 +37988,4629 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1869:1869:1869) (1895:1895:1895)) - (PORT d[0] (2908:2908:2908) (2850:2850:2850)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT d[0] (2226:2226:2226) (2231:2231:2231)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (743:743:743) (772:772:772)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3064:3064:3064) (3319:3319:3319)) + (PORT d[1] (1624:1624:1624) (1726:1726:1726)) + (PORT d[2] (1003:1003:1003) (1056:1056:1056)) + (PORT d[3] (954:954:954) (1004:1004:1004)) + (PORT d[4] (3267:3267:3267) (3445:3445:3445)) + (PORT d[5] (969:969:969) (999:999:999)) + (PORT d[6] (1577:1577:1577) (1697:1697:1697)) + (PORT d[7] (987:987:987) (1009:1009:1009)) + (PORT d[8] (1275:1275:1275) (1343:1343:1343)) + (PORT d[9] (1064:1064:1064) (1130:1130:1130)) + (PORT d[10] (1030:1030:1030) (1088:1088:1088)) + (PORT d[11] (2187:2187:2187) (2344:2344:2344)) + (PORT d[12] (1076:1076:1076) (1160:1160:1160)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (956:956:956) (917:917:917)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (2993:2993:2993) (3045:3045:3045)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (997:997:997) (1025:1025:1025)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3012:3012:3012) (3251:3251:3251)) + (PORT d[1] (1609:1609:1609) (1697:1697:1697)) + (PORT d[2] (983:983:983) (1016:1016:1016)) + (PORT d[3] (961:961:961) (994:994:994)) + (PORT d[4] (1434:1434:1434) (1457:1457:1457)) + (PORT d[5] (948:948:948) (977:977:977)) + (PORT d[6] (1862:1862:1862) (1998:1998:1998)) + (PORT d[7] (940:940:940) (959:959:959)) + (PORT d[8] (1274:1274:1274) (1339:1339:1339)) + (PORT d[9] (752:752:752) (813:813:813)) + (PORT d[10] (755:755:755) (815:815:815)) + (PORT d[11] (2517:2517:2517) (2676:2676:2676)) + (PORT d[12] (773:773:773) (837:837:837)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (682:682:682) (624:624:624)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT d[0] (1782:1782:1782) (1777:1777:1777)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2263:2263:2263) (2427:2427:2427)) + (PORT d[1] (2806:2806:2806) (2855:2855:2855)) + (PORT d[2] (2405:2405:2405) (2483:2483:2483)) + (PORT d[3] (4558:4558:4558) (4765:4765:4765)) + (PORT d[4] (1002:1002:1002) (1050:1050:1050)) + (PORT d[5] (2195:2195:2195) (2238:2238:2238)) + (PORT d[6] (924:924:924) (944:944:944)) + (PORT d[7] (1330:1330:1330) (1332:1332:1332)) + (PORT d[8] (2826:2826:2826) (2976:2976:2976)) + (PORT d[9] (1473:1473:1473) (1523:1523:1523)) + (PORT d[10] (1998:1998:1998) (2047:2047:2047)) + (PORT d[11] (3718:3718:3718) (4008:4008:4008)) + (PORT d[12] (4709:4709:4709) (5022:5022:5022)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1880:1880:1880)) + (PORT d[0] (1305:1305:1305) (1337:1337:1337)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (1966:1966:1966) (2027:2027:2027)) + (PORT datab (1520:1520:1520) (1598:1598:1598)) + (PORT datac (885:885:885) (908:908:908)) + (PORT datad (1061:1061:1061) (1077:1077:1077)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~80) + (DELAY + (ABSOLUTE + (PORT datab (915:915:915) (934:934:934)) + (PORT datac (1386:1386:1386) (1466:1466:1466)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (1493:1493:1493) (1589:1589:1589)) + (PORT datab (1130:1130:1130) (1152:1152:1152)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (1801:1801:1801) (1899:1899:1899)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1438:1438:1438) (1489:1489:1489)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2489:2489:2489) (2600:2600:2600)) + (PORT d[1] (2698:2698:2698) (2838:2838:2838)) + (PORT d[2] (2572:2572:2572) (2698:2698:2698)) + (PORT d[3] (3356:3356:3356) (3488:3488:3488)) + (PORT d[4] (2297:2297:2297) (2449:2449:2449)) + (PORT d[5] (3794:3794:3794) (3901:3901:3901)) + (PORT d[6] (2564:2564:2564) (2676:2676:2676)) + (PORT d[7] (3403:3403:3403) (3457:3457:3457)) + (PORT d[8] (2931:2931:2931) (3032:3032:3032)) + (PORT d[9] (2737:2737:2737) (2834:2834:2834)) + (PORT d[10] (2604:2604:2604) (2714:2714:2714)) + (PORT d[11] (2512:2512:2512) (2702:2702:2702)) + (PORT d[12] (3523:3523:3523) (3743:3743:3743)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2846:2846:2846) (2893:2893:2893)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (3535:3535:3535) (3484:3484:3484)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1813:1813:1813)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2458:2458:2458) (2451:2451:2451)) + (PORT clk (1825:1825:1825) (1819:1819:1819)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4479:4479:4479) (4514:4514:4514)) + (PORT d[1] (4465:4465:4465) (4517:4517:4517)) + (PORT d[2] (4544:4544:4544) (4551:4551:4551)) + (PORT d[3] (4403:4403:4403) (4415:4415:4415)) + (PORT d[4] (4292:4292:4292) (4432:4432:4432)) + (PORT d[5] (4375:4375:4375) (4440:4440:4440)) + (PORT d[6] (4446:4446:4446) (4486:4486:4486)) + (PORT d[7] (4358:4358:4358) (4399:4399:4399)) + (PORT d[8] (4409:4409:4409) (4489:4489:4489)) + (PORT d[9] (4419:4419:4419) (4498:4498:4498)) + (PORT d[10] (4270:4270:4270) (4305:4305:4305)) + (PORT d[11] (4393:4393:4393) (4493:4493:4493)) + (PORT d[12] (4247:4247:4247) (4253:4253:4253)) + (PORT clk (1821:1821:1821) (1815:1815:1815)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1819:1819:1819)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1815:1815:1815)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~124) + (DELAY + (ABSOLUTE + (PORT dataa (2618:2618:2618) (2852:2852:2852)) + (PORT datab (2469:2469:2469) (2595:2595:2595)) + (PORT datac (1575:1575:1575) (1686:1686:1686)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1395:1395:1395) (1438:1438:1438)) + (PORT clk (1855:1855:1855) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1950:1950:1950) (2069:2069:2069)) + (PORT d[1] (3022:3022:3022) (3167:3167:3167)) + (PORT d[2] (1806:1806:1806) (1910:1910:1910)) + (PORT d[3] (3658:3658:3658) (3808:3808:3808)) + (PORT d[4] (2619:2619:2619) (2778:2778:2778)) + (PORT d[5] (4118:4118:4118) (4230:4230:4230)) + (PORT d[6] (2735:2735:2735) (2827:2827:2827)) + (PORT d[7] (1984:1984:1984) (2046:2046:2046)) + (PORT d[8] (1994:1994:1994) (2040:2040:2040)) + (PORT d[9] (2437:2437:2437) (2548:2548:2548)) + (PORT d[10] (2646:2646:2646) (2757:2757:2757)) + (PORT d[11] (2789:2789:2789) (2994:2994:2994)) + (PORT d[12] (4582:4582:4582) (4832:4832:4832)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1561:1561:1561) (1515:1515:1515)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1883:1883:1883)) + (PORT d[0] (3203:3203:3203) (3240:3240:3240)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1808:1808:1808)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2190:2190:2190) (2181:2181:2181)) + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4546:4546:4546) (4580:4580:4580)) + (PORT d[1] (4461:4461:4461) (4513:4513:4513)) + (PORT d[2] (4466:4466:4466) (4476:4476:4476)) + (PORT d[3] (4422:4422:4422) (4460:4460:4460)) + (PORT d[4] (4363:4363:4363) (4523:4523:4523)) + (PORT d[5] (4348:4348:4348) (4415:4415:4415)) + (PORT d[6] (4445:4445:4445) (4467:4467:4467)) + (PORT d[7] (4345:4345:4345) (4449:4449:4449)) + (PORT d[8] (4480:4480:4480) (4560:4560:4560)) + (PORT d[9] (4577:4577:4577) (4641:4641:4641)) + (PORT d[10] (4311:4311:4311) (4390:4390:4390)) + (PORT d[11] (4436:4436:4436) (4532:4532:4532)) + (PORT d[12] (4251:4251:4251) (4274:4274:4274)) + (PORT clk (1816:1816:1816) (1810:1810:1810)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2469:2469:2469) (2602:2602:2602)) + (PORT d[1] (2377:2377:2377) (2524:2524:2524)) + (PORT d[2] (2274:2274:2274) (2431:2431:2431)) + (PORT d[3] (2180:2180:2180) (2330:2330:2330)) + (PORT d[4] (2086:2086:2086) (2172:2172:2172)) + (PORT d[5] (2417:2417:2417) (2540:2540:2540)) + (PORT d[6] (2442:2442:2442) (2606:2606:2606)) + (PORT d[7] (3149:3149:3149) (3211:3211:3211)) + (PORT d[8] (2864:2864:2864) (2942:2942:2942)) + (PORT d[9] (2362:2362:2362) (2550:2550:2550)) + (PORT d[10] (3296:3296:3296) (3440:3440:3440)) + (PORT d[11] (2098:2098:2098) (2200:2200:2200)) + (PORT d[12] (2283:2283:2283) (2461:2461:2461)) + (PORT clk (1859:1859:1859) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (PORT d[0] (2575:2575:2575) (2667:2667:2667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1848:1848:1848)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1007:1007:1007) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1012:1012:1012)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1012:1012:1012)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1012:1012:1012)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~123) + (DELAY + (ABSOLUTE + (PORT dataa (2613:2613:2613) (2845:2845:2845)) + (PORT datab (2470:2470:2470) (2597:2597:2597)) + (PORT datac (1305:1305:1305) (1374:1374:1374)) + (PORT datad (1662:1662:1662) (1719:1719:1719)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (1252:1252:1252) (1292:1292:1292)) + (PORT datab (741:741:741) (851:851:851)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (1965:1965:1965) (2023:2023:2023)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~108) + (DELAY + (ABSOLUTE + (PORT dataa (1550:1550:1550) (1580:1580:1580)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~109) + (DELAY + (ABSOLUTE + (PORT dataa (2783:2783:2783) (2886:2886:2886)) + (PORT datab (938:938:938) (1032:1032:1032)) + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (1506:1506:1506) (1530:1530:1530)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (297:297:297)) + (PORT datab (859:859:859) (885:885:885)) + (PORT datac (623:623:623) (656:656:656)) + (PORT datad (1129:1129:1129) (1160:1160:1160)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (420:420:420) (450:450:450)) + (PORT datac (363:363:363) (431:431:431)) + (PORT datad (386:386:386) (412:412:412)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1294:1294:1294) (1315:1315:1315)) + (PORT datab (372:372:372) (397:397:397)) + (PORT datac (825:825:825) (876:876:876)) + (PORT datad (567:567:567) (578:578:578)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1558:1558:1558)) + (PORT ena (1940:1940:1940) (1962:1962:1962)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2251:2251:2251) (2328:2328:2328)) + (PORT datac (1575:1575:1575) (1707:1707:1707)) + (PORT datad (1688:1688:1688) (1747:1747:1747)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (897:897:897)) + (PORT datab (1870:1870:1870) (1946:1946:1946)) + (PORT datac (1151:1151:1151) (1176:1176:1176)) + (PORT datad (624:624:624) (661:661:661)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (678:678:678)) + (PORT datab (204:204:204) (246:246:246)) + (PORT datac (1170:1170:1170) (1209:1209:1209)) + (PORT datad (844:844:844) (899:899:899)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (458:458:458)) + (PORT datab (603:603:603) (621:621:621)) + (PORT datad (1132:1132:1132) (1160:1160:1160)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1500:1500:1500) (1546:1546:1546)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2373:2373:2373) (2567:2567:2567)) + (PORT d[1] (2551:2551:2551) (2651:2651:2651)) + (PORT d[2] (1549:1549:1549) (1634:1634:1634)) + (PORT d[3] (1265:1265:1265) (1340:1340:1340)) + (PORT d[4] (2004:2004:2004) (2083:2083:2083)) + (PORT d[5] (1260:1260:1260) (1335:1335:1335)) + (PORT d[6] (1712:1712:1712) (1742:1742:1742)) + (PORT d[7] (2350:2350:2350) (2481:2481:2481)) + (PORT d[8] (2475:2475:2475) (2633:2633:2633)) + (PORT d[9] (1038:1038:1038) (1095:1095:1095)) + (PORT d[10] (1743:1743:1743) (1843:1843:1843)) + (PORT d[11] (1460:1460:1460) (1528:1528:1528)) + (PORT d[12] (1011:1011:1011) (1068:1068:1068)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1776:1776:1776) (1775:1775:1775)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT d[0] (2106:2106:2106) (2095:2095:2095)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1472:1472:1472) (1514:1514:1514)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2336:2336:2336) (2510:2510:2510)) + (PORT d[1] (1981:1981:1981) (2064:2064:2064)) + (PORT d[2] (1851:1851:1851) (1954:1954:1954)) + (PORT d[3] (2217:2217:2217) (2311:2311:2311)) + (PORT d[4] (2028:2028:2028) (2096:2096:2096)) + (PORT d[5] (1586:1586:1586) (1680:1680:1680)) + (PORT d[6] (1724:1724:1724) (1771:1771:1771)) + (PORT d[7] (2272:2272:2272) (2376:2376:2376)) + (PORT d[8] (2487:2487:2487) (2660:2660:2660)) + (PORT d[9] (1183:1183:1183) (1248:1248:1248)) + (PORT d[10] (1648:1648:1648) (1719:1719:1719)) + (PORT d[11] (1194:1194:1194) (1243:1243:1243)) + (PORT d[12] (1050:1050:1050) (1129:1129:1129)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1540:1540:1540) (1561:1561:1561)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (1987:1987:1987) (1984:1984:1984)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (914:914:914) (933:933:933)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2902:2902:2902) (3119:3119:3119)) + (PORT d[1] (3573:3573:3573) (3763:3763:3763)) + (PORT d[2] (1956:1956:1956) (2034:2034:2034)) + (PORT d[3] (3972:3972:3972) (4152:4152:4152)) + (PORT d[4] (3177:3177:3177) (3389:3389:3389)) + (PORT d[5] (4728:4728:4728) (4845:4845:4845)) + (PORT d[6] (2221:2221:2221) (2292:2292:2292)) + (PORT d[7] (1688:1688:1688) (1718:1718:1718)) + (PORT d[8] (3114:3114:3114) (3291:3291:3291)) + (PORT d[9] (1819:1819:1819) (1883:1883:1883)) + (PORT d[10] (2034:2034:2034) (2098:2098:2098)) + (PORT d[11] (3078:3078:3078) (3310:3310:3310)) + (PORT d[12] (4587:4587:4587) (4856:4856:4856)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2278:2278:2278) (2264:2264:2264)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (2520:2520:2520) (2539:2539:2539)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1187:1187:1187) (1212:1212:1212)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2569:2569:2569) (2756:2756:2756)) + (PORT d[1] (3637:3637:3637) (3813:3813:3813)) + (PORT d[2] (2109:2109:2109) (2190:2190:2190)) + (PORT d[3] (4259:4259:4259) (4451:4451:4451)) + (PORT d[4] (3209:3209:3209) (3444:3444:3444)) + (PORT d[5] (4699:4699:4699) (4855:4855:4855)) + (PORT d[6] (2574:2574:2574) (2667:2667:2667)) + (PORT d[7] (1420:1420:1420) (1439:1439:1439)) + (PORT d[8] (3134:3134:3134) (3310:3310:3310)) + (PORT d[9] (1832:1832:1832) (1888:1888:1888)) + (PORT d[10] (2003:2003:2003) (2057:2057:2057)) + (PORT d[11] (3398:3398:3398) (3651:3651:3651)) + (PORT d[12] (4571:4571:4571) (4836:4836:4836)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1591:1591:1591) (1527:1527:1527)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (2499:2499:2499) (2455:2455:2455)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (844:844:844)) + (PORT datab (1180:1180:1180) (1276:1276:1276)) + (PORT datac (1196:1196:1196) (1251:1251:1251)) + (PORT datad (1097:1097:1097) (1132:1132:1132)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1234:1234:1234) (1290:1290:1290)) + (PORT datab (1272:1272:1272) (1332:1332:1332)) + (PORT datac (1738:1738:1738) (1814:1814:1814)) + (PORT datad (313:313:313) (331:331:331)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~97) + (DELAY + (ABSOLUTE + (PORT dataa (2634:2634:2634) (2764:2764:2764)) + (PORT datab (1940:1940:1940) (2085:2085:2085)) + (PORT datac (2774:2774:2774) (3006:3006:3006)) + (PORT datad (2211:2211:2211) (2282:2282:2282)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1585:1585:1585) (1668:1668:1668)) + (PORT clk (1858:1858:1858) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3186:3186:3186) (3418:3418:3418)) + (PORT d[1] (3339:3339:3339) (3475:3475:3475)) + (PORT d[2] (2251:2251:2251) (2357:2357:2357)) + (PORT d[3] (3642:3642:3642) (3797:3797:3797)) + (PORT d[4] (2928:2928:2928) (3138:3138:3138)) + (PORT d[5] (4390:4390:4390) (4507:4507:4507)) + (PORT d[6] (1780:1780:1780) (1859:1859:1859)) + (PORT d[7] (1974:1974:1974) (2019:2019:2019)) + (PORT d[8] (2011:2011:2011) (2055:2055:2055)) + (PORT d[9] (2117:2117:2117) (2203:2203:2203)) + (PORT d[10] (2341:2341:2341) (2430:2430:2430)) + (PORT d[11] (2795:2795:2795) (3008:3008:3008)) + (PORT d[12] (4293:4293:4293) (4549:4549:4549)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1653:1653:1653) (1635:1635:1635)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT d[0] (2870:2870:2870) (2886:2886:2886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1813:1813:1813) (1811:1811:1811)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2178:2178:2178) (2158:2158:2158)) + (PORT clk (1823:1823:1823) (1817:1817:1817)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4523:4523:4523) (4579:4579:4579)) + (PORT d[1] (4471:4471:4471) (4537:4537:4537)) + (PORT d[2] (4520:4520:4520) (4549:4549:4549)) + (PORT d[3] (4434:4434:4434) (4448:4448:4448)) + (PORT d[4] (4399:4399:4399) (4562:4562:4562)) + (PORT d[5] (4336:4336:4336) (4388:4388:4388)) + (PORT d[6] (4419:4419:4419) (4461:4461:4461)) + (PORT d[7] (4386:4386:4386) (4436:4436:4436)) + (PORT d[8] (4545:4545:4545) (4646:4646:4646)) + (PORT d[9] (4542:4542:4542) (4602:4602:4602)) + (PORT d[10] (4589:4589:4589) (4649:4649:4649)) + (PORT d[11] (4439:4439:4439) (4545:4545:4545)) + (PORT d[12] (4288:4288:4288) (4293:4293:4293)) + (PORT clk (1819:1819:1819) (1813:1813:1813)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1818:1818:1818)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1682:1682:1682) (1815:1815:1815)) + (PORT d[1] (1648:1648:1648) (1686:1686:1686)) + (PORT d[2] (2268:2268:2268) (2431:2431:2431)) + (PORT d[3] (1863:1863:1863) (1918:1918:1918)) + (PORT d[4] (2378:2378:2378) (2506:2506:2506)) + (PORT d[5] (2549:2549:2549) (2590:2590:2590)) + (PORT d[6] (1990:1990:1990) (2063:2063:2063)) + (PORT d[7] (2031:2031:2031) (2099:2099:2099)) + (PORT d[8] (2125:2125:2125) (2219:2219:2219)) + (PORT d[9] (2009:2009:2009) (2078:2078:2078)) + (PORT d[10] (1655:1655:1655) (1716:1716:1716)) + (PORT d[11] (4351:4351:4351) (4669:4669:4669)) + (PORT d[12] (2155:2155:2155) (2206:2206:2206)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1882:1882:1882)) + (PORT d[0] (2116:2116:2116) (2085:2085:2085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1562:1562:1562) (1663:1663:1663)) + (PORT clk (1857:1857:1857) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1624:1624:1624) (1739:1739:1739)) + (PORT d[1] (2987:2987:2987) (3136:3136:3136)) + (PORT d[2] (2558:2558:2558) (2693:2693:2693)) + (PORT d[3] (3334:3334:3334) (3467:3467:3467)) + (PORT d[4] (2606:2606:2606) (2786:2786:2786)) + (PORT d[5] (3822:3822:3822) (3934:3934:3934)) + (PORT d[6] (2246:2246:2246) (2338:2338:2338)) + (PORT d[7] (3413:3413:3413) (3468:3468:3468)) + (PORT d[8] (2931:2931:2931) (3033:3033:3033)) + (PORT d[9] (2477:2477:2477) (2573:2573:2573)) + (PORT d[10] (2626:2626:2626) (2737:2737:2737)) + (PORT d[11] (2491:2491:2491) (2679:2679:2679)) + (PORT d[12] (4641:4641:4641) (4882:4882:4882)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2847:2847:2847) (2894:2894:2894)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1885:1885:1885)) + (PORT d[0] (3233:3233:3233) (3186:3186:3186)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1810:1810:1810)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1943:1943:1943) (1936:1936:1936)) + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4480:4480:4480) (4505:4505:4505)) + (PORT d[1] (4433:4433:4433) (4489:4489:4489)) + (PORT d[2] (4515:4515:4515) (4513:4513:4513)) + (PORT d[3] (4207:4207:4207) (4267:4267:4267)) + (PORT d[4] (4326:4326:4326) (4470:4470:4470)) + (PORT d[5] (4354:4354:4354) (4405:4405:4405)) + (PORT d[6] (4409:4409:4409) (4469:4469:4469)) + (PORT d[7] (4149:4149:4149) (4196:4196:4196)) + (PORT d[8] (4390:4390:4390) (4446:4446:4446)) + (PORT d[9] (4387:4387:4387) (4446:4446:4446)) + (PORT d[10] (4288:4288:4288) (4373:4373:4373)) + (PORT d[11] (4468:4468:4468) (4585:4585:4585)) + (PORT d[12] (4406:4406:4406) (4382:4382:4382)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1812:1812:1812)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1665:1665:1665) (1779:1779:1779)) + (PORT d[1] (2703:2703:2703) (2833:2833:2833)) + (PORT d[2] (2113:2113:2113) (2246:2246:2246)) + (PORT d[3] (3328:3328:3328) (3453:3453:3453)) + (PORT d[4] (2296:2296:2296) (2448:2448:2448)) + (PORT d[5] (3758:3758:3758) (3880:3880:3880)) + (PORT d[6] (2543:2543:2543) (2630:2630:2630)) + (PORT d[7] (3441:3441:3441) (3488:3488:3488)) + (PORT d[8] (2926:2926:2926) (3023:3023:3023)) + (PORT d[9] (2768:2768:2768) (2881:2881:2881)) + (PORT d[10] (2335:2335:2335) (2395:2395:2395)) + (PORT d[11] (2478:2478:2478) (2654:2654:2654)) + (PORT d[12] (3520:3520:3520) (3735:3735:3735)) + (PORT clk (1861:1861:1861) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1887:1887:1887)) + (PORT d[0] (2653:2653:2653) (2588:2588:2588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1850:1850:1850)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1009:1009:1009) (1013:1013:1013)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1010:1010:1010) (1014:1014:1014)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1010:1010:1010) (1014:1014:1014)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1010:1010:1010) (1014:1014:1014)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1215:1215:1215) (1288:1288:1288)) + (PORT datab (724:724:724) (782:782:782)) + (PORT datac (1333:1333:1333) (1353:1353:1353)) + (PORT datad (1400:1400:1400) (1484:1484:1484)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (765:765:765)) + (PORT datab (1092:1092:1092) (1091:1091:1091)) + (PORT datac (1528:1528:1528) (1658:1658:1658)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~116) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (256:256:256)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (973:973:973) (999:999:999)) + (PORT datad (615:615:615) (641:641:641)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~117) + (DELAY + (ABSOLUTE + (PORT dataa (1229:1229:1229) (1241:1241:1241)) + (PORT datab (2477:2477:2477) (2583:2583:2583)) + (PORT datac (1187:1187:1187) (1273:1273:1273)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (398:398:398)) + (PORT datab (431:431:431) (467:467:467)) + (PORT datac (1157:1157:1157) (1229:1229:1229)) + (PORT datad (1131:1131:1131) (1158:1158:1158)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (420:420:420) (454:454:454)) + (PORT datac (594:594:594) (602:602:602)) + (PORT datad (240:240:240) (310:310:310)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (675:675:675) (698:698:698)) + (PORT clrn (1577:1577:1577) (1558:1558:1558)) + (PORT ena (1917:1917:1917) (1918:1918:1918)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~0) + (DELAY + (ABSOLUTE + (PORT datac (1095:1095:1095) (1167:1167:1167)) + (PORT datad (1964:1964:1964) (2035:2035:2035)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2561:2561:2561) (2630:2630:2630)) + (PORT datab (2099:2099:2099) (2235:2235:2235)) + (PORT datac (2435:2435:2435) (2634:2634:2634)) + (PORT datad (1838:1838:1838) (1932:1932:1932)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1616:1616:1616) (1664:1664:1664)) + (PORT datab (568:568:568) (584:584:584)) + (PORT datac (848:848:848) (863:863:863)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) + (DELAY + (ABSOLUTE + (PORT dataa (677:677:677) (699:699:699)) + (PORT datab (856:856:856) (930:930:930)) + (PORT datac (1457:1457:1457) (1472:1472:1472)) + (PORT datad (1160:1160:1160) (1214:1214:1214)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2288:2288:2288) (2394:2394:2394)) + (PORT datab (2179:2179:2179) (2358:2358:2358)) + (PORT datac (1178:1178:1178) (1292:1292:1292)) + (PORT datad (819:819:819) (892:892:892)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instCB) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1565:1565:1565) (1545:1545:1545)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~0) + (DELAY + (ABSOLUTE + (PORT dataa (786:786:786) (855:855:855)) + (PORT datab (770:770:770) (837:837:837)) + (PORT datac (1830:1830:1830) (1968:1968:1968)) + (PORT datad (1686:1686:1686) (1757:1757:1757)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (1012:1012:1012)) + (PORT datab (1179:1179:1179) (1247:1247:1247)) + (PORT datac (1905:1905:1905) (1971:1971:1971)) + (PORT datad (1431:1431:1431) (1464:1464:1464)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im1) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (929:929:929) (946:946:946)) + (PORT clrn (1577:1577:1577) (1557:1557:1557)) + (PORT ena (968:968:968) (972:972:972)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (674:674:674)) + (PORT datab (968:968:968) (1029:1029:1029)) + (PORT datad (359:359:359) (423:423:423)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (959:959:959)) + (PORT datab (989:989:989) (1031:1031:1031)) + (PORT datac (617:617:617) (643:643:643)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (674:674:674)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (1172:1172:1172) (1212:1212:1212)) + (PORT datad (839:839:839) (895:895:895)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1508:1508:1508) (1611:1611:1611)) + (PORT datab (1253:1253:1253) (1278:1278:1278)) + (PORT datac (1153:1153:1153) (1183:1183:1183)) + (PORT datad (1488:1488:1488) (1524:1524:1524)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (677:677:677)) + (PORT datab (1453:1453:1453) (1487:1487:1487)) + (PORT datac (508:508:508) (517:517:517)) + (PORT datad (952:952:952) (989:989:989)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) + (DELAY + (ABSOLUTE + (PORT datac (901:901:901) (942:942:942)) + (PORT datad (617:617:617) (659:659:659)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (256:256:256)) + (PORT datab (382:382:382) (410:410:410)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (525:525:525) (533:533:533)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (1019:1019:1019)) + (PORT datab (931:931:931) (1012:1012:1012)) + (PORT datac (252:252:252) (337:337:337)) + (PORT datad (268:268:268) (347:347:347)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~1) + (DELAY + (ABSOLUTE + (PORT datac (738:738:738) (815:815:815)) + (PORT datad (1023:1023:1023) (1090:1090:1090)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (437:437:437)) + (PORT datab (337:337:337) (366:366:366)) + (PORT datac (734:734:734) (821:821:821)) + (PORT datad (581:581:581) (597:597:597)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (771:771:771) (850:850:850)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1506:1506:1506) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1546:1546:1546) (1539:1539:1539)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (301:301:301) (418:418:418)) + (PORT datab (680:680:680) (747:747:747)) + (PORT datac (912:912:912) (975:975:975)) + (PORT datad (946:946:946) (1019:1019:1019)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (838:838:838)) + (PORT datab (771:771:771) (853:853:853)) + (PORT datac (697:697:697) (771:771:771)) + (PORT datad (966:966:966) (1032:1032:1032)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~85) + (DELAY + (ABSOLUTE + (PORT datab (1063:1063:1063) (1128:1128:1128)) + (PORT datad (184:184:184) (213:213:213)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (684:684:684)) + (PORT datab (225:225:225) (273:273:273)) + (PORT datac (710:710:710) (772:772:772)) + (PORT datad (520:520:520) (531:531:531)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (376:376:376)) + (PORT datab (775:775:775) (855:855:855)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1506:1506:1506) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1546:1546:1546) (1539:1539:1539)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (328:328:328)) + (PORT datab (947:947:947) (978:978:978)) + (PORT datac (785:785:785) (819:819:819)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (497:497:497) (573:573:573)) + (PORT datab (1005:1005:1005) (1093:1093:1093)) + (PORT datac (669:669:669) (725:725:725)) + (PORT datad (618:618:618) (686:686:686)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (497:497:497) (573:573:573)) + (PORT datac (755:755:755) (829:829:829)) + (PORT datad (392:392:392) (458:458:458)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1043:1043:1043) (1127:1127:1127)) + (PORT datac (901:901:901) (915:915:915)) + (PORT datad (729:729:729) (803:803:803)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (246:246:246)) + (PORT datab (201:201:201) (240:240:240)) + (PORT datad (576:576:576) (586:586:586)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (620:620:620)) + (PORT datab (1063:1063:1063) (1128:1128:1128)) + (PORT datac (731:731:731) (807:807:807)) + (PORT datad (184:184:184) (213:213:213)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (259:259:259)) + (PORT datab (559:559:559) (578:578:578)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1520:1520:1520)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (233:233:233) (282:282:282)) + (PORT datab (228:228:228) (268:268:268)) + (PORT datac (931:931:931) (977:977:977)) + (PORT datad (617:617:617) (661:661:661)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (718:718:718) (817:817:817)) + (PORT datab (1016:1016:1016) (1083:1083:1083)) + (PORT datac (962:962:962) (1040:1040:1040)) + (PORT datad (577:577:577) (602:602:602)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (1292:1292:1292) (1396:1396:1396)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1509:1509:1509) (1524:1524:1524)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1550:1550:1550) (1542:1542:1542)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~68) + (DELAY + (ABSOLUTE + (PORT datab (644:644:644) (706:706:706)) + (PORT datac (1000:1000:1000) (1060:1060:1060)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (735:735:735) (825:825:825)) + (PORT datab (970:970:970) (1056:1056:1056)) + (PORT datac (753:753:753) (841:841:841)) + (PORT datad (904:904:904) (978:978:978)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~69) + (DELAY + (ABSOLUTE + (PORT dataa (506:506:506) (584:584:584)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (937:937:937) (1017:1017:1017)) + (PORT datad (192:192:192) (225:225:225)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (905:905:905)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datac (606:606:606) (617:617:617)) + (PORT datad (714:714:714) (785:785:785)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (425:425:425) (501:501:501)) + (PORT datac (745:745:745) (823:823:823)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1065:1065:1065) (1137:1137:1137)) + (PORT datab (593:593:593) (663:663:663)) + (PORT datac (1004:1004:1004) (1060:1060:1060)) + (PORT datad (609:609:609) (666:666:666)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~71) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (688:688:688)) + (PORT datab (750:750:750) (829:829:829)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (262:262:262) (341:341:341)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (245:245:245)) + (PORT datab (744:744:744) (816:816:816)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1542:1542:1542) (1535:1535:1535)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1478:1478:1478) (1551:1551:1551)) + (PORT datac (2279:2279:2279) (2486:2486:2486)) + (PORT datad (872:872:872) (942:942:942)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (718:718:718) (814:814:814)) + (PORT datac (962:962:962) (1038:1038:1038)) + (PORT datad (578:578:578) (600:600:600)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (1295:1295:1295) (1399:1399:1399)) + (PORT datab (1016:1016:1016) (1082:1082:1082)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1509:1509:1509) (1524:1524:1524)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1550:1550:1550) (1542:1542:1542)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (436:436:436)) + (PORT datab (739:739:739) (806:806:806)) + (PORT datac (888:888:888) (956:956:956)) + (PORT datad (198:198:198) (235:235:235)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (1294:1294:1294) (1399:1399:1399)) + (PORT datab (957:957:957) (996:996:996)) + (PORT datad (592:592:592) (615:615:615)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1509:1509:1509) (1524:1524:1524)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1550:1550:1550) (1542:1542:1542)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (276:276:276)) + (PORT datab (2799:2799:2799) (3004:3004:3004)) + (PORT datac (215:215:215) (290:290:290)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (931:931:931)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (2354:2354:2354) (2577:2577:2577)) + (PORT datad (621:621:621) (631:631:631)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1207:1207:1207) (1245:1245:1245)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2687:2687:2687) (2899:2899:2899)) + (PORT d[1] (2871:2871:2871) (2966:2966:2966)) + (PORT d[2] (1020:1020:1020) (1070:1070:1070)) + (PORT d[3] (974:974:974) (1029:1029:1029)) + (PORT d[4] (2049:2049:2049) (2146:2146:2146)) + (PORT d[5] (972:972:972) (1026:1026:1026)) + (PORT d[6] (1699:1699:1699) (1745:1745:1745)) + (PORT d[7] (2654:2654:2654) (2813:2813:2813)) + (PORT d[8] (2491:2491:2491) (2668:2668:2668)) + (PORT d[9] (756:756:756) (799:799:799)) + (PORT d[10] (747:747:747) (789:789:789)) + (PORT d[11] (2820:2820:2820) (3002:3002:3002)) + (PORT d[12] (430:430:430) (463:463:463)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1529:1529:1529) (1497:1497:1497)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1871:1871:1871)) + (PORT d[0] (1469:1469:1469) (1447:1447:1447)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1830:1830:1830)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (988:988:988) (993:993:993)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (947:947:947) (971:971:971)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3042:3042:3042) (3290:3290:3290)) + (PORT d[1] (1608:1608:1608) (1696:1696:1696)) + (PORT d[2] (994:994:994) (1040:1040:1040)) + (PORT d[3] (946:946:946) (995:995:995)) + (PORT d[4] (1164:1164:1164) (1193:1193:1193)) + (PORT d[5] (957:957:957) (1004:1004:1004)) + (PORT d[6] (1556:1556:1556) (1674:1674:1674)) + (PORT d[7] (976:976:976) (1018:1018:1018)) + (PORT d[8] (1289:1289:1289) (1377:1377:1377)) + (PORT d[9] (775:775:775) (838:838:838)) + (PORT d[10] (729:729:729) (784:784:784)) + (PORT d[11] (2477:2477:2477) (2650:2650:2650)) + (PORT d[12] (1069:1069:1069) (1134:1134:1134)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (940:940:940) (896:896:896)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (2042:2042:2042) (2033:2033:2033)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1001:1001:1001) (1045:1045:1045)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3024:3024:3024) (3251:3251:3251)) + (PORT d[1] (1903:1903:1903) (2000:2000:2000)) + (PORT d[2] (1280:1280:1280) (1322:1322:1322)) + (PORT d[3] (1267:1267:1267) (1318:1318:1318)) + (PORT d[4] (1471:1471:1471) (1527:1527:1527)) + (PORT d[5] (661:661:661) (688:688:688)) + (PORT d[6] (1836:1836:1836) (1967:1967:1967)) + (PORT d[7] (2929:2929:2929) (3085:3085:3085)) + (PORT d[8] (1275:1275:1275) (1340:1340:1340)) + (PORT d[9] (1006:1006:1006) (1059:1059:1059)) + (PORT d[10] (723:723:723) (773:773:773)) + (PORT d[11] (2518:2518:2518) (2677:2677:2677)) + (PORT d[12] (772:772:772) (836:836:836)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (942:942:942) (897:897:897)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT d[0] (1808:1808:1808) (1808:1808:1808)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (1055:1055:1055) (1145:1145:1145)) + (PORT datab (960:960:960) (1036:1036:1036)) + (PORT datac (887:887:887) (907:907:907)) + (PORT datad (932:932:932) (969:969:969)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1406:1406:1406) (1432:1432:1432)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2471:2471:2471) (2605:2605:2605)) + (PORT d[1] (2523:2523:2523) (2576:2576:2576)) + (PORT d[2] (2567:2567:2567) (2747:2747:2747)) + (PORT d[3] (4593:4593:4593) (4820:4820:4820)) + (PORT d[4] (2930:2930:2930) (3056:3056:3056)) + (PORT d[5] (3148:3148:3148) (3203:3203:3203)) + (PORT d[6] (1481:1481:1481) (1477:1477:1477)) + (PORT d[7] (1396:1396:1396) (1430:1430:1430)) + (PORT d[8] (2490:2490:2490) (2615:2615:2615)) + (PORT d[9] (1697:1697:1697) (1729:1729:1729)) + (PORT d[10] (2540:2540:2540) (2643:2643:2643)) + (PORT d[11] (3702:3702:3702) (3993:3993:3993)) + (PORT d[12] (2490:2490:2490) (2565:2565:2565)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1996:1996:1996) (1955:1955:1955)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (1950:1950:1950) (1919:1919:1919)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (1203:1203:1203) (1219:1219:1219)) + (PORT datab (1550:1550:1550) (1670:1670:1670)) + (PORT datac (349:349:349) (375:375:375)) + (PORT datad (1314:1314:1314) (1366:1366:1366)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1584:1584:1584) (1654:1654:1654)) + (PORT clk (1860:1860:1860) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2492:2492:2492) (2623:2623:2623)) + (PORT d[1] (2117:2117:2117) (2250:2250:2250)) + (PORT d[2] (2413:2413:2413) (2548:2548:2548)) + (PORT d[3] (2100:2100:2100) (2226:2226:2226)) + (PORT d[4] (2068:2068:2068) (2175:2175:2175)) + (PORT d[5] (2319:2319:2319) (2438:2438:2438)) + (PORT d[6] (2333:2333:2333) (2448:2448:2448)) + (PORT d[7] (3448:3448:3448) (3532:3532:3532)) + (PORT d[8] (2854:2854:2854) (2949:2949:2949)) + (PORT d[9] (2032:2032:2032) (2198:2198:2198)) + (PORT d[10] (3609:3609:3609) (3784:3784:3784)) + (PORT d[11] (2147:2147:2147) (2282:2282:2282)) + (PORT d[12] (1982:1982:1982) (2139:2139:2139)) + (PORT clk (1857:1857:1857) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1972:1972:1972) (1939:1939:1939)) + (PORT clk (1857:1857:1857) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1886:1886:1886)) + (PORT d[0] (3223:3223:3223) (3296:3296:3296)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1811:1811:1811)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2151:2151:2151) (2201:2201:2201)) + (PORT clk (1825:1825:1825) (1817:1817:1817)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4343:4343:4343) (4403:4403:4403)) + (PORT d[1] (4498:4498:4498) (4585:4585:4585)) + (PORT d[2] (4548:4548:4548) (4611:4611:4611)) + (PORT d[3] (4307:4307:4307) (4402:4402:4402)) + (PORT d[4] (4392:4392:4392) (4483:4483:4483)) + (PORT d[5] (4431:4431:4431) (4542:4542:4542)) + (PORT d[6] (4555:4555:4555) (4660:4660:4660)) + (PORT d[7] (4287:4287:4287) (4335:4335:4335)) + (PORT d[8] (4389:4389:4389) (4493:4493:4493)) + (PORT d[9] (4480:4480:4480) (4525:4525:4525)) + (PORT d[10] (4429:4429:4429) (4529:4529:4529)) + (PORT d[11] (4427:4427:4427) (4554:4554:4554)) + (PORT d[12] (4332:4332:4332) (4318:4318:4318)) + (PORT clk (1821:1821:1821) (1813:1813:1813)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1817:1817:1817)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1818:1818:1818)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1978:1978:1978) (2105:2105:2105)) + (PORT d[1] (2195:2195:2195) (2216:2216:2216)) + (PORT d[2] (2233:2233:2233) (2405:2405:2405)) + (PORT d[3] (1730:1730:1730) (1765:1765:1765)) + (PORT d[4] (2301:2301:2301) (2429:2429:2429)) + (PORT d[5] (2806:2806:2806) (2865:2865:2865)) + (PORT d[6] (1746:1746:1746) (1828:1828:1828)) + (PORT d[7] (1972:1972:1972) (2011:2011:2011)) + (PORT d[8] (2183:2183:2183) (2302:2302:2302)) + (PORT d[9] (2006:2006:2006) (2072:2072:2072)) + (PORT d[10] (2505:2505:2505) (2578:2578:2578)) + (PORT d[11] (4321:4321:4321) (4631:4631:4631)) + (PORT d[12] (2164:2164:2164) (2232:2232:2232)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1880:1880:1880)) + (PORT d[0] (2147:2147:2147) (2137:2137:2137)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (978:978:978)) + (PORT datab (772:772:772) (880:880:880)) + (PORT datac (1200:1200:1200) (1239:1239:1239)) + (PORT datad (1667:1667:1667) (1720:1720:1720)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1483:1483:1483) (1518:1518:1518)) + (PORT clk (1869:1869:1869) (1895:1895:1895)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2205:2205:2205) (2306:2306:2306)) + (PORT d[1] (2632:2632:2632) (2785:2785:2785)) + (PORT d[2] (2362:2362:2362) (2492:2492:2492)) + (PORT d[3] (3051:3051:3051) (3158:3158:3158)) + (PORT d[4] (2271:2271:2271) (2411:2411:2411)) + (PORT d[5] (3452:3452:3452) (3554:3554:3554)) + (PORT d[6] (2543:2543:2543) (2661:2661:2661)) + (PORT d[7] (2952:2952:2952) (3038:3038:3038)) + (PORT d[8] (2643:2643:2643) (2727:2727:2727)) + (PORT d[9] (2971:2971:2971) (3112:3112:3112)) + (PORT d[10] (2322:2322:2322) (2378:2378:2378)) + (PORT d[11] (2215:2215:2215) (2364:2364:2364)) + (PORT d[12] (3539:3539:3539) (3735:3735:3735)) + (PORT clk (1866:1866:1866) (1891:1891:1891)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2575:2575:2575) (2593:2593:2593)) + (PORT clk (1866:1866:1866) (1891:1891:1891)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (PORT d[0] (3571:3571:3571) (3500:3500:3500)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1870:1870:1870) (1896:1896:1896)) @@ -34010,7 +42620,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1870:1870:1870) (1896:1896:1896)) @@ -34020,7 +42630,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1870:1870:1870) (1896:1896:1896)) @@ -34030,7 +42640,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1870:1870:1870) (1896:1896:1896)) @@ -34040,7 +42650,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1824:1824:1824) (1820:1820:1820)) @@ -34054,10 +42664,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2487:2487:2487) (2567:2567:2567)) + (PORT d[0] (2190:2190:2190) (2175:2175:2175)) (PORT clk (1834:1834:1834) (1826:1826:1826)) ) ) @@ -34067,22 +42677,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4515:4515:4515) (4502:4502:4502)) - (PORT d[1] (4098:4098:4098) (4096:4096:4096)) - (PORT d[2] (4387:4387:4387) (4416:4416:4416)) - (PORT d[3] (4466:4466:4466) (4494:4494:4494)) - (PORT d[4] (4550:4550:4550) (4547:4547:4547)) - (PORT d[5] (4395:4395:4395) (4433:4433:4433)) - (PORT d[6] (4601:4601:4601) (4650:4650:4650)) - (PORT d[7] (4160:4160:4160) (4143:4143:4143)) - (PORT d[8] (4661:4661:4661) (4689:4689:4689)) - (PORT d[9] (4502:4502:4502) (4695:4695:4695)) - (PORT d[10] (4622:4622:4622) (4632:4632:4632)) - (PORT d[11] (4398:4398:4398) (4428:4428:4428)) - (PORT d[12] (4464:4464:4464) (4487:4487:4487)) + (PORT d[0] (4505:4505:4505) (4525:4525:4525)) + (PORT d[1] (4469:4469:4469) (4501:4501:4501)) + (PORT d[2] (4469:4469:4469) (4476:4476:4476)) + (PORT d[3] (4421:4421:4421) (4437:4437:4437)) + (PORT d[4] (4275:4275:4275) (4372:4372:4372)) + (PORT d[5] (4447:4447:4447) (4521:4521:4521)) + (PORT d[6] (4240:4240:4240) (4335:4335:4335)) + (PORT d[7] (4388:4388:4388) (4448:4448:4448)) + (PORT d[8] (4382:4382:4382) (4489:4489:4489)) + (PORT d[9] (4346:4346:4346) (4404:4404:4404)) + (PORT d[10] (4279:4279:4279) (4347:4347:4347)) + (PORT d[11] (4488:4488:4488) (4529:4529:4529)) + (PORT d[12] (4294:4294:4294) (4294:4294:4294)) (PORT clk (1830:1830:1830) (1822:1822:1822)) ) ) @@ -34092,7 +42702,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1834:1834:1834) (1826:1826:1826)) @@ -34101,7 +42711,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) (DELAY (ABSOLUTE (PORT clk (1835:1835:1835) (1827:1827:1827)) @@ -34111,7 +42721,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1835:1835:1835) (1827:1827:1827)) @@ -34121,7 +42731,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1835:1835:1835) (1827:1827:1827)) @@ -34131,7 +42741,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1835:1835:1835) (1827:1827:1827)) @@ -34141,7 +42751,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) (DELAY (ABSOLUTE (PORT clk (1826:1826:1826) (1822:1822:1822)) @@ -34154,103 +42764,204 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~0) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT dataa (1428:1428:1428) (1500:1500:1500)) - (PORT datab (969:969:969) (1047:1047:1047)) - (PORT datac (1170:1170:1170) (1197:1197:1197)) - (PORT datad (1685:1685:1685) (1714:1714:1714)) + (PORT d[0] (2240:2240:2240) (2401:2401:2401)) + (PORT d[1] (1094:1094:1094) (1093:1093:1093)) + (PORT d[2] (2654:2654:2654) (2732:2732:2732)) + (PORT d[3] (4596:4596:4596) (4810:4810:4810)) + (PORT d[4] (1006:1006:1006) (1054:1054:1054)) + (PORT d[5] (2205:2205:2205) (2223:2223:2223)) + (PORT d[6] (2849:2849:2849) (2950:2950:2950)) + (PORT d[7] (1412:1412:1412) (1409:1409:1409)) + (PORT d[8] (2768:2768:2768) (2898:2898:2898)) + (PORT d[9] (1486:1486:1486) (1518:1518:1518)) + (PORT d[10] (2026:2026:2026) (2083:2083:2083)) + (PORT d[11] (3734:3734:3734) (3998:3998:3998)) + (PORT d[12] (1704:1704:1704) (1711:1711:1711)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1879:1879:1879)) + (PORT d[0] (1336:1336:1336) (1345:1345:1345)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1816:1816:1816) (1842:1842:1842)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1001:1001:1001) (1005:1005:1005)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (1157:1157:1157) (1202:1202:1202)) + (PORT datab (947:947:947) (970:970:970)) + (PORT datac (998:998:998) (1057:1057:1057)) + (PORT datad (183:183:183) (213:213:213)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (772:772:772) (884:884:884)) + (PORT datac (1893:1893:1893) (1938:1938:1938)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~120) + (DELAY + (ABSOLUTE + (PORT dataa (1727:1727:1727) (1787:1787:1787)) + (PORT datab (3006:3006:3006) (3258:3258:3258)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (966:966:966)) + (PORT datab (902:902:902) (924:924:924)) + (PORT datac (1649:1649:1649) (1666:1666:1666)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (1188:1188:1188) (1288:1288:1288)) + (PORT datab (2963:2963:2963) (3072:3072:3072)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (1441:1441:1441) (1491:1491:1491)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (1194:1194:1194) (1194:1194:1194)) + (PORT datab (424:424:424) (459:459:459)) + (PORT datac (371:371:371) (400:400:400)) + (PORT datad (1127:1127:1127) (1155:1155:1155)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1516:1516:1516) (1602:1602:1602)) - (PORT datab (970:970:970) (1048:1048:1048)) - (PORT datac (1706:1706:1706) (1767:1767:1767)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (246:246:246)) - (PORT datab (1206:1206:1206) (1299:1299:1299)) - (PORT datac (1658:1658:1658) (1693:1693:1693)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (1382:1382:1382) (1395:1395:1395)) - (PORT datab (1382:1382:1382) (1409:1409:1409)) - (PORT datac (842:842:842) (919:919:919)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~99) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (832:832:832)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) - (DELAY - (ABSOLUTE - (PORT dataa (972:972:972) (1043:1043:1043)) - (PORT datab (1039:1039:1039) (1071:1071:1071)) - (PORT datac (240:240:240) (293:293:293)) - (PORT datad (948:948:948) (984:984:984)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[5\]) + (INSTANCE z80_\|data_pins_\|dout\[0\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT clk (1527:1527:1527) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) (PORT ena (841:841:841) (846:846:846)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -34263,43 +42974,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~14) + (INSTANCE z80_\|bus_control_\|db\[0\]\~16) (DELAY (ABSOLUTE - (PORT datab (707:707:707) (729:729:729)) - (PORT datac (235:235:235) (309:309:309)) - (PORT datad (359:359:359) (384:384:384)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (253:253:253) (299:299:299)) + (PORT datac (220:220:220) (264:264:264)) + (PORT datad (2132:2132:2132) (2201:2201:2201)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~15) + (INSTANCE z80_\|bus_control_\|db\[0\]\~17) (DELAY (ABSOLUTE - (PORT dataa (980:980:980) (1004:1004:1004)) - (PORT datab (917:917:917) (967:967:967)) - (PORT datac (825:825:825) (825:825:825)) - (PORT datad (891:891:891) (919:919:919)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (1434:1434:1434) (1471:1471:1471)) + (PORT datac (1092:1092:1092) (1123:1123:1123)) + (PORT datad (217:217:217) (254:254:254)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[5\]) + (INSTANCE z80_\|ir_\|opcode\[0\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT asdata (598:598:598) (653:653:653)) - (PORT clrn (1571:1571:1571) (1550:1550:1550)) - (PORT ena (1479:1479:1479) (1488:1488:1488)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (714:714:714) (741:741:741)) + (PORT clrn (1577:1577:1577) (1558:1558:1558)) + (PORT ena (1917:1917:1917) (1918:1918:1918)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -34311,29 +43022,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) + (INSTANCE z80_\|pla_decode_\|Equal3\~2) (DELAY (ABSOLUTE - (PORT dataa (1209:1209:1209) (1333:1333:1333)) - (PORT datab (857:857:857) (877:877:877)) - (PORT datac (862:862:862) (884:884:884)) - (PORT datad (1897:1897:1897) (1952:1952:1952)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1683:1683:1683) (1793:1793:1793)) + (PORT datab (1366:1366:1366) (1396:1396:1396)) + (PORT datac (208:208:208) (251:251:251)) + (PORT datad (1331:1331:1331) (1338:1338:1338)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2302:2302:2302) (2437:2437:2437)) + (PORT datab (2181:2181:2181) (2361:2361:2361)) + (PORT datac (2247:2247:2247) (2350:2350:2350)) + (PORT datad (365:365:365) (398:398:398)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_inst4) + (INSTANCE z80_\|decode_state_\|DFFE_instIY1) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) + (PORT clk (1516:1516:1516) (1529:1529:1529)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1586:1586:1586) (1563:1563:1563)) - (PORT ena (820:820:820) (825:825:825)) + (PORT clrn (1565:1565:1565) (1545:1545:1545)) + (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -34348,166 +43075,24 @@ (INSTANCE z80_\|decode_state_\|use_ixiy) (DELAY (ABSOLUTE - (PORT dataa (974:974:974) (1072:1072:1072)) - (PORT datac (930:930:930) (1012:1012:1012)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1192:1192:1192) (1230:1230:1230)) - (PORT datab (998:998:998) (1107:1107:1107)) - (PORT datac (657:657:657) (721:721:721)) - (PORT datad (1243:1243:1243) (1329:1329:1329)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datac (996:996:996) (1081:1081:1081)) + (PORT datad (1502:1502:1502) (1553:1553:1553)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~34) + (INSTANCE z80_\|execute_\|ixy_d\~12) (DELAY (ABSOLUTE - (PORT dataa (888:888:888) (915:915:915)) - (PORT datab (667:667:667) (679:679:679)) - (PORT datac (904:904:904) (934:934:934)) - (PORT datad (360:360:360) (382:382:382)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1168:1168:1168) (1211:1211:1211)) - (PORT datab (1607:1607:1607) (1625:1625:1625)) - (PORT datac (614:614:614) (646:646:646)) - (PORT datad (1081:1081:1081) (1126:1126:1126)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1255:1255:1255) (1363:1363:1363)) - (PORT datab (469:469:469) (523:523:523)) - (PORT datac (1707:1707:1707) (1763:1763:1763)) - (PORT datad (264:264:264) (317:317:317)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (441:441:441)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (1072:1072:1072) (1108:1108:1108)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1172:1172:1172) (1212:1212:1212)) - (PORT datab (568:568:568) (599:599:599)) - (PORT datac (1103:1103:1103) (1115:1115:1115)) - (PORT datad (317:317:317) (336:336:336)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (898:898:898)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (590:590:590) (597:597:597)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (903:903:903) (948:948:948)) + (PORT datab (1697:1697:1697) (1728:1728:1728)) + (PORT datac (1067:1067:1067) (1109:1109:1109)) + (PORT datad (812:812:812) (861:861:861)) (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (275:275:275)) - (PORT datab (645:645:645) (670:670:670)) - (PORT datac (194:194:194) (238:238:238)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (914:914:914)) - (PORT datab (1115:1115:1115) (1147:1147:1147)) - (PORT datac (1402:1402:1402) (1464:1464:1464)) - (PORT datad (899:899:899) (942:942:942)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (895:895:895)) - (PORT datab (939:939:939) (994:994:994)) - (PORT datac (959:959:959) (1031:1031:1031)) - (PORT datad (1113:1113:1113) (1143:1143:1143)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -34515,15 +43100,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~9) + (INSTANCE z80_\|execute_\|ixy_d\~13) (DELAY (ABSOLUTE - (PORT dataa (889:889:889) (916:916:916)) - (PORT datab (876:876:876) (896:896:896)) - (PORT datac (1106:1106:1106) (1134:1134:1134)) - (PORT datad (326:326:326) (350:350:350)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (PORT dataa (624:624:624) (662:662:662)) + (PORT datab (1244:1244:1244) (1274:1274:1274)) + (PORT datad (871:871:871) (916:916:916)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1085:1085:1085) (1153:1153:1153)) + (PORT datab (609:609:609) (654:654:654)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (597:597:597) (613:613:613)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (719:719:719)) + (PORT datab (700:700:700) (775:775:775)) + (PORT datac (1424:1424:1424) (1508:1508:1508)) + (PORT datad (601:601:601) (661:661:661)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1203:1203:1203) (1234:1234:1234)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (610:610:610) (637:637:637)) + (PORT datad (772:772:772) (823:823:823)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -34531,14 +43162,62 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~11) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) (DELAY (ABSOLUTE - (PORT dataa (1572:1572:1572) (1664:1664:1664)) - (PORT datab (205:205:205) (245:245:245)) - (PORT datac (1885:1885:1885) (1936:1936:1936)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) + (PORT dataa (1245:1245:1245) (1333:1333:1333)) + (PORT datab (390:390:390) (423:423:423)) + (PORT datac (956:956:956) (1024:1024:1024)) + (PORT datad (1355:1355:1355) (1444:1444:1444)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1284:1284:1284)) + (PORT datab (1539:1539:1539) (1640:1640:1640)) + (PORT datac (578:578:578) (588:588:588)) + (PORT datad (863:863:863) (880:880:880)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1381:1381:1381) (1463:1463:1463)) + (PORT datab (2126:2126:2126) (2263:2263:2263)) + (PORT datac (1615:1615:1615) (1658:1658:1658)) + (PORT datad (695:695:695) (742:742:742)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (724:724:724) (791:791:791)) + (PORT datab (649:649:649) (670:670:670)) + (PORT datac (1593:1593:1593) (1630:1630:1630)) + (PORT datad (1465:1465:1465) (1570:1570:1570)) + (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -34547,62 +43226,76 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~12) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) (DELAY (ABSOLUTE - (PORT dataa (1126:1126:1126) (1249:1249:1249)) - (PORT datab (997:997:997) (1061:1061:1061)) - (PORT datac (1628:1628:1628) (1678:1678:1678)) - (PORT datad (1161:1161:1161) (1198:1198:1198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1424:1424:1424) (1425:1425:1425)) - (PORT datab (1116:1116:1116) (1146:1146:1146)) - (PORT datac (1040:1040:1040) (1082:1082:1082)) - (PORT datad (337:337:337) (357:357:357)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (594:594:594) (614:614:614)) + (PORT dataa (1163:1163:1163) (1216:1216:1216)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (181:181:181) (210:210:210)) (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~20) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) (DELAY (ABSOLUTE - (PORT dataa (631:631:631) (644:644:644)) - (PORT datab (1041:1041:1041) (1082:1082:1082)) - (PORT datac (571:571:571) (588:588:588)) - (PORT datad (598:598:598) (647:647:647)) - (IOPATH dataa combout (325:325:325) (320:320:320)) + (PORT dataa (217:217:217) (266:266:266)) + (PORT datab (627:627:627) (678:678:678)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (349:349:349) (364:364:364)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~9) + (DELAY + (ABSOLUTE + (PORT datab (874:874:874) (925:925:925)) + (PORT datac (570:570:570) (586:586:586)) + (PORT datad (809:809:809) (832:832:832)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (621:621:621)) + (PORT datab (601:601:601) (620:620:620)) + (PORT datac (899:899:899) (936:936:936)) + (PORT datad (809:809:809) (837:837:837)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (297:297:297)) + (PORT datab (874:874:874) (928:928:928)) + (PORT datac (650:650:650) (693:693:693)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -34611,15 +43304,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~48) + (INSTANCE z80_\|alu_control_\|db\[1\]\~25) (DELAY (ABSOLUTE - (PORT dataa (886:886:886) (933:933:933)) - (PORT datab (1205:1205:1205) (1227:1227:1227)) - (PORT datac (1512:1512:1512) (1585:1585:1585)) - (PORT datad (674:674:674) (712:712:712)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (1079:1079:1079) (1133:1133:1133)) + (PORT datab (1173:1173:1173) (1212:1212:1212)) + (PORT datac (1315:1315:1315) (1328:1328:1328)) + (PORT datad (1358:1358:1358) (1425:1425:1425)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -34627,15 +43320,316 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~22) + (INSTANCE z80_\|alu_control_\|db\[1\]\~26) (DELAY (ABSOLUTE - (PORT dataa (1353:1353:1353) (1383:1383:1383)) - (PORT datab (852:852:852) (880:880:880)) - (PORT datac (1075:1075:1075) (1109:1109:1109)) - (PORT datad (195:195:195) (220:220:220)) + (PORT dataa (645:645:645) (661:661:661)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (851:851:851) (873:873:873)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (649:649:649)) + (PORT datac (630:630:630) (662:662:662)) + (PORT datad (838:838:838) (858:858:858)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (883:883:883) (909:909:909)) + (PORT datad (177:177:177) (203:203:203)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (910:910:910)) + (PORT datab (1157:1157:1157) (1201:1201:1201)) + (PORT datad (384:384:384) (414:414:414)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (498:498:498) (573:573:573)) + (PORT datac (751:751:751) (825:825:825)) + (PORT datad (387:387:387) (454:454:454)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (764:764:764)) + (PORT datac (977:977:977) (1063:1063:1063)) + (PORT datad (614:614:614) (686:686:686)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (247:247:247)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datad (578:578:578) (587:587:587)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (774:774:774) (851:851:851)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1506:1506:1506) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1546:1546:1546) (1539:1539:1539)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~0) + (DELAY + (ABSOLUTE + (PORT datab (1813:1813:1813) (1930:1930:1930)) + (PORT datac (2265:2265:2265) (2466:2466:2466)) + (PORT datad (915:915:915) (970:970:970)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (305:305:305) (422:422:422)) + (PORT datab (682:682:682) (750:750:750)) + (PORT datac (916:916:916) (978:978:978)) + (PORT datad (948:948:948) (1021:1021:1021)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (792:792:792)) + (PORT datab (793:793:793) (875:875:875)) + (PORT datac (1034:1034:1034) (1097:1097:1097)) + (PORT datad (738:738:738) (822:822:822)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~0) + (DELAY + (ABSOLUTE + (PORT dataa (716:716:716) (796:796:796)) + (PORT datab (792:792:792) (873:873:873)) + (PORT datac (1031:1031:1031) (1096:1096:1096)) + (PORT datad (735:735:735) (819:819:819)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (278:278:278)) + (PORT datab (1063:1063:1063) (1131:1131:1131)) + (PORT datac (1262:1262:1262) (1333:1333:1333)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) + (DELAY + (ABSOLUTE + (PORT dataa (738:738:738) (816:816:816)) + (PORT datab (1297:1297:1297) (1371:1371:1371)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (174:174:174) (201:201:201)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (741:741:741) (812:812:812)) + (PORT datab (607:607:607) (611:611:611)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1547:1547:1547) (1540:1540:1540)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (748:748:748) (837:837:837)) + (PORT datab (726:726:726) (804:804:804)) + (PORT datac (739:739:739) (817:817:817)) + (PORT datad (1023:1023:1023) (1086:1086:1086)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (995:995:995) (1074:1074:1074)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (522:522:522) (541:541:541)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (1062:1062:1062) (1126:1126:1126)) + (PORT datac (461:461:461) (535:535:535)) + (PORT datad (928:928:928) (988:988:988)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -34643,30 +43637,136 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~21) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~35) (DELAY (ABSOLUTE - (PORT dataa (870:870:870) (942:942:942)) - (PORT datab (941:941:941) (1018:1018:1018)) - (PORT datac (1551:1551:1551) (1591:1591:1591)) - (PORT datad (1215:1215:1215) (1217:1217:1217)) - (IOPATH dataa combout (301:301:301) (299:299:299)) + (PORT dataa (202:202:202) (246:246:246)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1520:1520:1520)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (988:988:988)) + (PORT datab (945:945:945) (1001:1001:1001)) + (PORT datac (641:641:641) (696:696:696)) + (PORT datad (1431:1431:1431) (1449:1449:1449)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (281:281:281)) + (PORT datab (921:921:921) (969:969:969)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~23) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~16) (DELAY (ABSOLUTE - (PORT dataa (867:867:867) (909:909:909)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (806:806:806) (819:819:819)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (350:350:350) (366:366:366)) + (PORT dataa (511:511:511) (591:591:591)) + (PORT datab (930:930:930) (1017:1017:1017)) + (PORT datac (753:753:753) (840:840:840)) + (PORT datad (703:703:703) (775:775:775)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (258:258:258)) + (PORT datab (652:652:652) (674:674:674)) + (PORT datac (937:937:937) (1024:1024:1024)) + (PORT datad (888:888:888) (925:925:925)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (500:500:500) (572:572:572)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1504:1504:1504) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (594:594:594)) + (PORT datab (970:970:970) (1057:1057:1057)) + (PORT datac (753:753:753) (842:842:842)) + (PORT datad (702:702:702) (779:779:779)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -34675,79 +43775,168 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~26) + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~13) (DELAY (ABSOLUTE - (PORT dataa (2068:2068:2068) (2159:2159:2159)) - (PORT datab (1202:1202:1202) (1215:1215:1215)) - (PORT datac (1137:1137:1137) (1179:1179:1179)) - (PORT datad (1150:1150:1150) (1187:1187:1187)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (2504:2504:2504) (2616:2616:2616)) - (PORT datab (576:576:576) (586:586:586)) - (PORT datac (193:193:193) (227:227:227)) - (PORT datad (981:981:981) (1012:1012:1012)) - (IOPATH dataa combout (304:304:304) (299:299:299)) + (PORT dataa (733:733:733) (820:820:820)) + (PORT datab (1305:1305:1305) (1362:1362:1362)) + (PORT datac (732:732:732) (817:817:817)) + (PORT datad (312:312:312) (329:329:329)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~27) + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~10) (DELAY (ABSOLUTE - (PORT dataa (1663:1663:1663) (1697:1697:1697)) - (PORT datab (833:833:833) (893:893:893)) - (PORT datac (1036:1036:1036) (1091:1091:1091)) - (PORT datad (770:770:770) (816:816:816)) - (IOPATH dataa combout (327:327:327) (347:347:347)) + (PORT datab (767:767:767) (847:847:847)) + (PORT datac (462:462:462) (540:540:540)) + (PORT datad (925:925:925) (984:984:984)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~33) + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) (DELAY (ABSOLUTE - (PORT dataa (1031:1031:1031) (1043:1043:1043)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (819:819:819) (869:869:869)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (642:642:642) (674:674:674)) + (PORT datab (336:336:336) (366:366:366)) + (PORT datad (175:175:175) (202:202:202)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1520:1520:1520)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (724:724:724)) + (PORT datab (669:669:669) (741:741:741)) + (PORT datac (672:672:672) (714:714:714)) + (PORT datad (1494:1494:1494) (1585:1585:1585)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~35) + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~25) (DELAY (ABSOLUTE - (PORT dataa (865:865:865) (888:888:888)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (821:821:821) (872:872:872)) - (PORT datad (195:195:195) (219:219:219)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT datab (1299:1299:1299) (1375:1375:1375)) + (PORT datac (685:685:685) (784:784:784)) + (PORT datad (717:717:717) (806:806:806)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1291:1291:1291) (1397:1397:1397)) + (PORT datab (659:659:659) (682:682:682)) + (PORT datad (593:593:593) (616:616:616)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1509:1509:1509) (1524:1524:1524)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1550:1550:1550) (1542:1542:1542)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1293:1293:1293) (1401:1401:1401)) + (PORT datab (1016:1016:1016) (1083:1083:1083)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1509:1509:1509) (1524:1524:1524)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1550:1550:1550) (1542:1542:1542)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (277:277:277)) + (PORT datab (2798:2798:2798) (3000:3000:3000)) + (PORT datac (216:216:216) (292:292:292)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -34755,178 +43944,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re) + (INSTANCE D\[1\]\~34) (DELAY (ABSOLUTE - (PORT datab (974:974:974) (1035:1035:1035)) - (PORT datac (964:964:964) (1026:1026:1026)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (2352:2352:2352) (2576:2576:2576)) + (PORT datad (570:570:570) (582:582:582)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1008:1008:1008) (1080:1080:1080)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1191:1191:1191) (1224:1224:1224)) - (PORT d[1] (2415:2415:2415) (2649:2649:2649)) - (PORT d[2] (1758:1758:1758) (1803:1803:1803)) - (PORT d[3] (1013:1013:1013) (1063:1063:1063)) - (PORT d[4] (2608:2608:2608) (2826:2826:2826)) - (PORT d[5] (3496:3496:3496) (3699:3699:3699)) - (PORT d[6] (1026:1026:1026) (1099:1099:1099)) - (PORT d[7] (3197:3197:3197) (3375:3375:3375)) - (PORT d[8] (1246:1246:1246) (1270:1270:1270)) - (PORT d[9] (1026:1026:1026) (1088:1088:1088)) - (PORT d[10] (1315:1315:1315) (1388:1388:1388)) - (PORT d[11] (2503:2503:2503) (2659:2659:2659)) - (PORT d[12] (1307:1307:1307) (1387:1387:1387)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (944:944:944) (900:900:900)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (1721:1721:1721) (1677:1677:1677)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (708:708:708) (754:754:754)) - (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (1278:1278:1278) (1317:1317:1317)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) ) ) (TIMINGCHECK @@ -34938,20 +43976,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (966:966:966) (1010:1010:1010)) - (PORT d[1] (2966:2966:2966) (3237:3237:3237)) - (PORT d[2] (1238:1238:1238) (1256:1256:1256)) - (PORT d[3] (1302:1302:1302) (1383:1383:1383)) - (PORT d[4] (2581:2581:2581) (2796:2796:2796)) - (PORT d[5] (2980:2980:2980) (3208:3208:3208)) - (PORT d[6] (692:692:692) (727:727:727)) - (PORT d[7] (705:705:705) (744:744:744)) - (PORT d[8] (1011:1011:1011) (1032:1032:1032)) - (PORT d[9] (717:717:717) (757:757:757)) - (PORT d[10] (1036:1036:1036) (1102:1102:1102)) - (PORT d[11] (2544:2544:2544) (2757:2757:2757)) - (PORT d[12] (1267:1267:1267) (1319:1319:1319)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (2420:2420:2420) (2614:2614:2614)) + (PORT d[1] (2542:2542:2542) (2641:2641:2641)) + (PORT d[2] (1265:1265:1265) (1333:1333:1333)) + (PORT d[3] (1256:1256:1256) (1301:1301:1301)) + (PORT d[4] (2037:2037:2037) (2116:2116:2116)) + (PORT d[5] (1268:1268:1268) (1326:1326:1326)) + (PORT d[6] (1448:1448:1448) (1473:1473:1473)) + (PORT d[7] (2668:2668:2668) (2814:2814:2814)) + (PORT d[8] (2486:2486:2486) (2658:2658:2658)) + (PORT d[9] (774:774:774) (839:839:839)) + (PORT d[10] (732:732:732) (787:787:787)) + (PORT d[11] (1198:1198:1198) (1240:1240:1240)) + (PORT d[12] (723:723:723) (773:773:773)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) ) ) (TIMINGCHECK @@ -34963,8 +44001,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (967:967:967) (945:945:945)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (1249:1249:1249) (1220:1220:1220)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) ) ) (TIMINGCHECK @@ -34976,8 +44014,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1860:1860:1860) (1888:1888:1888)) - (PORT d[0] (2089:2089:2089) (2073:2073:2073)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + (PORT d[0] (1711:1711:1711) (1677:1677:1677)) ) ) ) @@ -34986,7 +44024,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1844:1844:1844) (1872:1872:1872)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -34996,7 +44034,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1844:1844:1844) (1872:1872:1872)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -35006,7 +44044,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1844:1844:1844) (1872:1872:1872)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -35016,7 +44054,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1844:1844:1844) (1872:1872:1872)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -35026,7 +44064,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1820:1820:1820) (1847:1847:1847)) + (PORT clk (1803:1803:1803) (1830:1830:1830)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -35040,7 +44078,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1005:1005:1005) (1010:1010:1010)) + (PORT clk (988:988:988) (993:993:993)) ) ) ) @@ -35049,7 +44087,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) + (PORT clk (989:989:989) (994:994:994)) ) ) ) @@ -35058,7 +44096,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) + (PORT clk (989:989:989) (994:994:994)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -35068,24 +44106,161 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) + (PORT clk (989:989:989) (994:994:994)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~0) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (682:682:682) (752:752:752)) - (PORT datab (688:688:688) (754:754:754)) - (PORT datac (786:786:786) (795:795:795)) - (PORT datad (864:864:864) (896:896:896)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT d[0] (1001:1001:1001) (1024:1024:1024)) + (PORT clk (1847:1847:1847) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2737:2737:2737) (2961:2961:2961)) + (PORT d[1] (1936:1936:1936) (2018:2018:2018)) + (PORT d[2] (998:998:998) (1029:1029:1029)) + (PORT d[3] (969:969:969) (994:994:994)) + (PORT d[4] (1425:1425:1425) (1469:1469:1469)) + (PORT d[5] (958:958:958) (992:992:992)) + (PORT d[6] (1158:1158:1158) (1170:1170:1170)) + (PORT d[7] (2950:2950:2950) (3104:3104:3104)) + (PORT d[8] (1588:1588:1588) (1675:1675:1675)) + (PORT d[9] (737:737:737) (777:777:777)) + (PORT d[10] (715:715:715) (752:752:752)) + (PORT d[11] (2487:2487:2487) (2667:2667:2667)) + (PORT d[12] (760:760:760) (814:814:814)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (948:948:948) (922:922:922)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (3281:3281:3281) (3342:3342:3342)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1807:1807:1807) (1834:1834:1834)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (992:992:992) (997:997:997)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) @@ -35094,7 +44269,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (700:700:700) (744:744:744)) + (PORT d[0] (1192:1192:1192) (1163:1163:1163)) (PORT clk (1860:1860:1860) (1887:1887:1887)) ) ) @@ -35107,19 +44282,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3167:3167:3167) (3303:3303:3303)) - (PORT d[1] (2937:2937:2937) (3208:3208:3208)) - (PORT d[2] (967:967:967) (987:987:987)) - (PORT d[3] (1341:1341:1341) (1401:1401:1401)) - (PORT d[4] (2612:2612:2612) (2843:2843:2843)) - (PORT d[5] (2651:2651:2651) (2894:2894:2894)) - (PORT d[6] (960:960:960) (1001:1001:1001)) - (PORT d[7] (1270:1270:1270) (1343:1343:1343)) - (PORT d[8] (1442:1442:1442) (1513:1513:1513)) - (PORT d[9] (971:971:971) (1019:1019:1019)) - (PORT d[10] (1031:1031:1031) (1057:1057:1057)) - (PORT d[11] (2872:2872:2872) (3095:3095:3095)) - (PORT d[12] (969:969:969) (1020:1020:1020)) + (PORT d[0] (2546:2546:2546) (2729:2729:2729)) + (PORT d[1] (3618:3618:3618) (3824:3824:3824)) + (PORT d[2] (2381:2381:2381) (2458:2458:2458)) + (PORT d[3] (4288:4288:4288) (4492:4492:4492)) + (PORT d[4] (3170:3170:3170) (3405:3405:3405)) + (PORT d[5] (4727:4727:4727) (4889:4889:4889)) + (PORT d[6] (2532:2532:2532) (2627:2627:2627)) + (PORT d[7] (1392:1392:1392) (1407:1407:1407)) + (PORT d[8] (3122:3122:3122) (3282:3282:3282)) + (PORT d[9] (1802:1802:1802) (1840:1840:1840)) + (PORT d[10] (1997:1997:1997) (2034:2034:2034)) + (PORT d[11] (3401:3401:3401) (3659:3659:3659)) + (PORT d[12] (4693:4693:4693) (4992:4992:4992)) (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) @@ -35132,7 +44307,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1245:1245:1245) (1221:1221:1221)) + (PORT d[0] (1888:1888:1888) (1943:1943:1943)) (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) @@ -35146,7 +44321,7 @@ (DELAY (ABSOLUTE (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (2049:2049:2049) (2003:2003:2003)) + (PORT d[0] (2445:2445:2445) (2405:2405:2405)) ) ) ) @@ -35242,170 +44417,17 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (743:743:743) (772:772:772)) - (PORT clk (1859:1859:1859) (1886:1886:1886)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3188:3188:3188) (3327:3327:3327)) - (PORT d[1] (2678:2678:2678) (2951:2951:2951)) - (PORT d[2] (1298:1298:1298) (1309:1309:1309)) - (PORT d[3] (1348:1348:1348) (1402:1402:1402)) - (PORT d[4] (2616:2616:2616) (2850:2850:2850)) - (PORT d[5] (2675:2675:2675) (2903:2903:2903)) - (PORT d[6] (1230:1230:1230) (1289:1289:1289)) - (PORT d[7] (1132:1132:1132) (1148:1148:1148)) - (PORT d[8] (1470:1470:1470) (1552:1552:1552)) - (PORT d[9] (1550:1550:1550) (1617:1617:1617)) - (PORT d[10] (724:724:724) (767:767:767)) - (PORT d[11] (2854:2854:2854) (3086:3086:3086)) - (PORT d[12] (971:971:971) (1034:1034:1034)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1229:1229:1229) (1208:1208:1208)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1886:1886:1886)) - (PORT d[0] (1822:1822:1822) (1811:1811:1811)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) + (INSTANCE D\[1\]\~38) (DELAY (ABSOLUTE - (PORT dataa (1242:1242:1242) (1299:1299:1299)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (968:968:968) (1003:1003:1003)) - (PORT datad (1089:1089:1089) (1119:1119:1119)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (983:983:983) (1077:1077:1077)) + (PORT datab (1231:1231:1231) (1326:1326:1326)) + (PORT datac (912:912:912) (954:954:954)) + (PORT datad (1090:1090:1090) (1094:1094:1094)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -35413,11 +44435,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (746:746:746) (776:776:776)) - (PORT clk (1853:1853:1853) (1881:1881:1881)) + (PORT d[0] (1370:1370:1370) (1410:1410:1410)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) ) ) (TIMINGCHECK @@ -35426,23 +44448,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2906:2906:2906) (3003:3003:3003)) - (PORT d[1] (2374:2374:2374) (2624:2624:2624)) - (PORT d[2] (1590:1590:1590) (1604:1604:1604)) - (PORT d[3] (1983:1983:1983) (2059:2059:2059)) - (PORT d[4] (2920:2920:2920) (3176:3176:3176)) - (PORT d[5] (2692:2692:2692) (2903:2903:2903)) - (PORT d[6] (1267:1267:1267) (1350:1350:1350)) - (PORT d[7] (1307:1307:1307) (1395:1395:1395)) - (PORT d[8] (1742:1742:1742) (1842:1842:1842)) - (PORT d[9] (1557:1557:1557) (1621:1621:1621)) - (PORT d[10] (2161:2161:2161) (2306:2306:2306)) - (PORT d[11] (3233:3233:3233) (3375:3375:3375)) - (PORT d[12] (1281:1281:1281) (1357:1357:1357)) - (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT d[0] (2461:2461:2461) (2613:2613:2613)) + (PORT d[1] (2479:2479:2479) (2511:2511:2511)) + (PORT d[2] (2577:2577:2577) (2775:2775:2775)) + (PORT d[3] (1707:1707:1707) (1744:1744:1744)) + (PORT d[4] (2415:2415:2415) (2564:2564:2564)) + (PORT d[5] (3183:3183:3183) (3261:3261:3261)) + (PORT d[6] (2218:2218:2218) (2320:2320:2320)) + (PORT d[7] (1719:1719:1719) (1754:1754:1754)) + (PORT d[8] (2452:2452:2452) (2554:2554:2554)) + (PORT d[9] (1710:1710:1710) (1761:1761:1761)) + (PORT d[10] (2530:2530:2530) (2628:2628:2628)) + (PORT d[11] (4031:4031:4031) (4326:4326:4326)) + (PORT d[12] (2475:2475:2475) (2545:2545:2545)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) ) ) (TIMINGCHECK @@ -35451,11 +44473,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2941:2941:2941) (2895:2895:2895)) - (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT d[0] (2002:2002:2002) (1964:1964:1964)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) ) ) (TIMINGCHECK @@ -35464,60 +44486,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (PORT d[0] (3092:3092:3092) (3136:3136:3136)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2204:2204:2204) (2160:2160:2160)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) + (PORT clk (1853:1853:1853) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) + (PORT clk (1853:1853:1853) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) + (PORT clk (1853:1853:1853) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) + (PORT clk (1853:1853:1853) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1808:1808:1808) (1806:1806:1806)) + (PORT clk (1812:1812:1812) (1838:1838:1838)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -35528,281 +44550,55 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (2118:2118:2118) (2165:2165:2165)) - (PORT clk (1818:1818:1818) (1812:1812:1812)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4374:4374:4374) (4418:4418:4418)) - (PORT d[1] (4140:4140:4140) (4128:4128:4128)) - (PORT d[2] (4277:4277:4277) (4327:4327:4327)) - (PORT d[3] (4389:4389:4389) (4374:4374:4374)) - (PORT d[4] (4369:4369:4369) (4385:4385:4385)) - (PORT d[5] (4402:4402:4402) (4357:4357:4357)) - (PORT d[6] (4635:4635:4635) (4717:4717:4717)) - (PORT d[7] (4444:4444:4444) (4393:4393:4393)) - (PORT d[8] (4445:4445:4445) (4433:4433:4433)) - (PORT d[9] (4508:4508:4508) (4699:4699:4699)) - (PORT d[10] (4409:4409:4409) (4440:4440:4440)) - (PORT d[11] (4509:4509:4509) (4563:4563:4563)) - (PORT d[12] (4429:4429:4429) (4547:4547:4547)) - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) + (PORT clk (997:997:997) (1001:1001:1001)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + (PORT clk (998:998:998) (1002:1002:1002)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) + (PORT clk (998:998:998) (1002:1002:1002)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) + (PORT clk (998:998:998) (1002:1002:1002)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~39) (DELAY (ABSOLUTE - (PORT d[0] (2570:2570:2570) (2648:2648:2648)) - (PORT d[1] (2033:2033:2033) (2232:2232:2232)) - (PORT d[2] (2324:2324:2324) (2498:2498:2498)) - (PORT d[3] (2521:2521:2521) (2687:2687:2687)) - (PORT d[4] (2940:2940:2940) (3191:3191:3191)) - (PORT d[5] (2266:2266:2266) (2447:2447:2447)) - (PORT d[6] (1866:1866:1866) (1990:1990:1990)) - (PORT d[7] (2543:2543:2543) (2628:2628:2628)) - (PORT d[8] (2767:2767:2767) (2988:2988:2988)) - (PORT d[9] (1759:1759:1759) (1863:1863:1863)) - (PORT d[10] (1515:1515:1515) (1609:1609:1609)) - (PORT d[11] (3453:3453:3453) (3586:3586:3586)) - (PORT d[12] (1542:1542:1542) (1649:1649:1649)) - (PORT clk (1868:1868:1868) (1894:1894:1894)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1868:1868:1868) (1894:1894:1894)) - (PORT d[0] (2191:2191:2191) (2247:2247:2247)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1895:1895:1895)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1831:1831:1831) (1857:1857:1857)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1016:1016:1016) (1020:1020:1020)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1021:1021:1021)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1511:1511:1511) (1554:1554:1554)) - (PORT d[1] (2684:2684:2684) (2948:2948:2948)) - (PORT d[2] (989:989:989) (1036:1036:1036)) - (PORT d[3] (1684:1684:1684) (1752:1752:1752)) - (PORT d[4] (2594:2594:2594) (2826:2826:2826)) - (PORT d[5] (2711:2711:2711) (2920:2920:2920)) - (PORT d[6] (973:973:973) (1031:1031:1031)) - (PORT d[7] (964:964:964) (1018:1018:1018)) - (PORT d[8] (1426:1426:1426) (1505:1505:1505)) - (PORT d[9] (1567:1567:1567) (1660:1660:1660)) - (PORT d[10] (2478:2478:2478) (2623:2623:2623)) - (PORT d[11] (2885:2885:2885) (3126:3126:3126)) - (PORT d[12] (1271:1271:1271) (1324:1324:1324)) - (PORT clk (1855:1855:1855) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (PORT d[0] (872:872:872) (859:859:859)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + (PORT dataa (1520:1520:1520) (1636:1636:1636)) + (PORT datab (1198:1198:1198) (1226:1226:1226)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1384:1384:1384) (1422:1422:1422)) + (IOPATH dataa combout (341:341:341) (320:320:320)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -35811,8 +44607,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (926:926:926) (931:931:931)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (1498:1498:1498) (1529:1529:1529)) + (PORT clk (1866:1866:1866) (1893:1893:1893)) ) ) (TIMINGCHECK @@ -35824,20 +44620,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3174:3174:3174) (3295:3295:3295)) - (PORT d[1] (2670:2670:2670) (2938:2938:2938)) - (PORT d[2] (1591:1591:1591) (1604:1604:1604)) - (PORT d[3] (1700:1700:1700) (1749:1749:1749)) - (PORT d[4] (2908:2908:2908) (3176:3176:3176)) - (PORT d[5] (2711:2711:2711) (2920:2920:2920)) - (PORT d[6] (974:974:974) (1032:1032:1032)) - (PORT d[7] (1544:1544:1544) (1607:1607:1607)) - (PORT d[8] (3051:3051:3051) (3314:3314:3314)) - (PORT d[9] (996:996:996) (1062:1062:1062)) - (PORT d[10] (2482:2482:2482) (2620:2620:2620)) - (PORT d[11] (2859:2859:2859) (3096:3096:3096)) - (PORT d[12] (2233:2233:2233) (2338:2338:2338)) - (PORT clk (1854:1854:1854) (1880:1880:1880)) + (PORT d[0] (2502:2502:2502) (2600:2600:2600)) + (PORT d[1] (2280:2280:2280) (2376:2376:2376)) + (PORT d[2] (2063:2063:2063) (2187:2187:2187)) + (PORT d[3] (3319:3319:3319) (3431:3431:3431)) + (PORT d[4] (2302:2302:2302) (2458:2458:2458)) + (PORT d[5] (3776:3776:3776) (3885:3885:3885)) + (PORT d[6] (2525:2525:2525) (2638:2638:2638)) + (PORT d[7] (2494:2494:2494) (2555:2555:2555)) + (PORT d[8] (2947:2947:2947) (3049:3049:3049)) + (PORT d[9] (2749:2749:2749) (2863:2863:2863)) + (PORT d[10] (2929:2929:2929) (3041:3041:3041)) + (PORT d[11] (2742:2742:2742) (2907:2907:2907)) + (PORT d[12] (3512:3512:3512) (3716:3716:3716)) + (PORT clk (1863:1863:1863) (1889:1889:1889)) ) ) (TIMINGCHECK @@ -35849,8 +44645,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3083:3083:3083) (3081:3081:3081)) - (PORT clk (1854:1854:1854) (1880:1880:1880)) + (PORT d[0] (2834:2834:2834) (2862:2862:2862)) + (PORT clk (1863:1863:1863) (1889:1889:1889)) ) ) (TIMINGCHECK @@ -35862,8 +44658,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (PORT d[0] (1803:1803:1803) (1787:1787:1787)) + (PORT clk (1866:1866:1866) (1893:1893:1893)) + (PORT d[0] (3571:3571:3571) (3500:3500:3500)) ) ) ) @@ -35872,7 +44668,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) + (PORT clk (1867:1867:1867) (1894:1894:1894)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -35882,7 +44678,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) + (PORT clk (1867:1867:1867) (1894:1894:1894)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -35892,7 +44688,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) + (PORT clk (1867:1867:1867) (1894:1894:1894)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -35902,7 +44698,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) + (PORT clk (1867:1867:1867) (1894:1894:1894)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -35912,7 +44708,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1812:1812:1812) (1809:1809:1809)) + (PORT clk (1821:1821:1821) (1818:1818:1818)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -35926,8 +44722,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2405:2405:2405) (2433:2433:2433)) - (PORT clk (1822:1822:1822) (1815:1815:1815)) + (PORT d[0] (2189:2189:2189) (2175:2175:2175)) + (PORT clk (1831:1831:1831) (1824:1824:1824)) ) ) (TIMINGCHECK @@ -35939,20 +44735,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4622:4622:4622) (4649:4649:4649)) - (PORT d[1] (4242:4242:4242) (4320:4320:4320)) - (PORT d[2] (4251:4251:4251) (4295:4295:4295)) - (PORT d[3] (4399:4399:4399) (4422:4422:4422)) - (PORT d[4] (4340:4340:4340) (4354:4354:4354)) - (PORT d[5] (4534:4534:4534) (4546:4546:4546)) - (PORT d[6] (4731:4731:4731) (4801:4801:4801)) - (PORT d[7] (4488:4488:4488) (4531:4531:4531)) - (PORT d[8] (4436:4436:4436) (4436:4436:4436)) - (PORT d[9] (4525:4525:4525) (4711:4711:4711)) - (PORT d[10] (4473:4473:4473) (4495:4495:4495)) - (PORT d[11] (4414:4414:4414) (4386:4386:4386)) - (PORT d[12] (4391:4391:4391) (4381:4381:4381)) - (PORT clk (1818:1818:1818) (1811:1811:1811)) + (PORT d[0] (4520:4520:4520) (4545:4545:4545)) + (PORT d[1] (4445:4445:4445) (4516:4516:4516)) + (PORT d[2] (4525:4525:4525) (4596:4596:4596)) + (PORT d[3] (4398:4398:4398) (4408:4408:4408)) + (PORT d[4] (4281:4281:4281) (4404:4404:4404)) + (PORT d[5] (4393:4393:4393) (4465:4465:4465)) + (PORT d[6] (4259:4259:4259) (4355:4355:4355)) + (PORT d[7] (4414:4414:4414) (4478:4478:4478)) + (PORT d[8] (4545:4545:4545) (4666:4666:4666)) + (PORT d[9] (4382:4382:4382) (4434:4434:4434)) + (PORT d[10] (4247:4247:4247) (4300:4300:4300)) + (PORT d[11] (4433:4433:4433) (4558:4558:4558)) + (PORT d[12] (4266:4266:4266) (4271:4271:4271)) + (PORT clk (1827:1827:1827) (1820:1820:1820)) ) ) (TIMINGCHECK @@ -35964,7 +44760,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1822:1822:1822) (1815:1815:1815)) + (PORT clk (1831:1831:1831) (1824:1824:1824)) ) ) ) @@ -35973,7 +44769,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) + (PORT clk (1832:1832:1832) (1825:1825:1825)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -35983,7 +44779,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) + (PORT clk (1832:1832:1832) (1825:1825:1825)) (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) ) ) @@ -35993,7 +44789,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) + (PORT clk (1832:1832:1832) (1825:1825:1825)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -36003,7 +44799,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) + (PORT clk (1832:1832:1832) (1825:1825:1825)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -36013,7 +44809,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) (DELAY (ABSOLUTE - (PORT clk (1814:1814:1814) (1811:1811:1811)) + (PORT clk (1823:1823:1823) (1820:1820:1820)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -36022,3309 +44818,24 @@ (HOLD d (posedge clk) (159:159:159)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (731:731:731)) - (PORT datab (1192:1192:1192) (1240:1240:1240)) - (PORT datac (825:825:825) (833:833:833)) - (PORT datad (890:890:890) (911:911:911)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1189:1189:1189) (1198:1198:1198)) - (PORT datab (1192:1192:1192) (1240:1240:1240)) - (PORT datac (1509:1509:1509) (1586:1586:1586)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~103) - (DELAY - (ABSOLUTE - (PORT dataa (1738:1738:1738) (1846:1846:1846)) - (PORT datab (1412:1412:1412) (1506:1506:1506)) - (PORT datac (648:648:648) (701:701:701)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_DAT\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (479:479:479) (732:732:732)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE reset\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (842:842:842) (859:859:859)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) - (DELAY - (ABSOLUTE - (PORT dataa (282:282:282) (386:386:386)) - (PORT datab (291:291:291) (382:382:382)) - (PORT datad (245:245:245) (325:325:325)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_CLK\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (479:479:479) (732:732:732)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (3358:3358:3358) (3700:3700:3700)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (225:225:225) (297:297:297)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (227:227:227) (302:302:302)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (239:239:239) (309:309:309)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (342:342:342)) - (PORT datab (250:250:250) (335:335:335)) - (PORT datac (380:380:380) (441:441:441)) - (PORT datad (225:225:225) (298:298:298)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (227:227:227) (299:299:299)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (228:228:228) (301:301:301)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (226:226:226) (298:298:298)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (252:252:252) (337:337:337)) - (PORT datac (225:225:225) (305:305:305)) - (PORT datad (227:227:227) (299:299:299)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (226:226:226) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) - (DELAY - (ABSOLUTE - (PORT datab (208:208:208) (249:249:249)) - (PORT datad (227:227:227) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) - (DELAY - (ABSOLUTE - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (218:218:218) (295:295:295)) - (PORT datad (224:224:224) (296:296:296)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1562:1562:1562)) - (PORT ena (2016:2016:2016) (2055:2055:2055)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) - (DELAY - (ABSOLUTE - (PORT dataa (282:282:282) (387:387:387)) - (PORT datab (292:292:292) (383:383:383)) - (PORT datad (240:240:240) (317:317:317)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1562:1562:1562)) - (PORT ena (2016:2016:2016) (2055:2055:2055)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) - (DELAY - (ABSOLUTE - (PORT dataa (279:279:279) (382:382:382)) - (PORT datab (278:278:278) (373:373:373)) - (PORT datad (242:242:242) (321:321:321)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1562:1562:1562)) - (PORT ena (2016:2016:2016) (2055:2055:2055)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (480:480:480)) - (PORT datab (279:279:279) (374:374:374)) - (PORT datad (243:243:243) (322:322:322)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1562:1562:1562)) - (PORT ena (2016:2016:2016) (2055:2055:2055)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|always1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (275:275:275) (377:377:377)) - (PORT datab (288:288:288) (377:377:377)) - (PORT datac (3414:3414:3414) (3775:3775:3775)) - (PORT datad (251:251:251) (331:331:331)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT datab (289:289:289) (380:380:380)) - (PORT datac (247:247:247) (341:341:341)) - (PORT datad (248:248:248) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (264:264:264) (354:354:354)) - (PORT datac (1368:1368:1368) (1427:1427:1427)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT asdata (3957:3957:3957) (4311:4311:4311)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (1226:1226:1226) (1215:1215:1215)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT asdata (560:560:560) (634:634:634)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (1226:1226:1226) (1215:1215:1215)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT asdata (602:602:602) (685:685:685)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (1226:1226:1226) (1215:1215:1215)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT asdata (588:588:588) (665:665:665)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (1226:1226:1226) (1215:1215:1215)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT asdata (958:958:958) (1010:1010:1010)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT asdata (960:960:960) (1018:1018:1018)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (1226:1226:1226) (1215:1215:1215)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT asdata (951:951:951) (1014:1014:1014)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT asdata (761:761:761) (840:840:840)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT asdata (791:791:791) (867:867:867)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (990:990:990) (1075:1075:1075)) - (PORT datab (675:675:675) (742:742:742)) - (PORT datac (757:757:757) (876:876:876)) - (PORT datad (781:781:781) (888:888:888)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1415:1415:1415) (1549:1549:1549)) - (PORT datab (937:937:937) (1037:1037:1037)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (763:763:763) (875:875:875)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|extended\~0) - (DELAY - (ABSOLUTE - (PORT datab (1062:1062:1062) (1155:1155:1155)) - (PORT datad (785:785:785) (795:795:795)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (664:664:664) (722:722:722)) - (PORT datab (288:288:288) (378:378:378)) - (PORT datad (833:833:833) (880:880:880)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (741:741:741) (827:827:827)) - (PORT datab (669:669:669) (749:749:749)) - (PORT datac (655:655:655) (721:721:721)) - (PORT datad (438:438:438) (511:511:511)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) - (DELAY - (ABSOLUTE - (PORT datab (668:668:668) (736:736:736)) - (PORT datac (345:345:345) (369:369:369)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (255:255:255)) - (PORT datab (3434:3434:3434) (3812:3812:3812)) - (PORT datac (1368:1368:1368) (1428:1428:1428)) - (PORT datad (358:358:358) (390:390:390)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1562:1562:1562)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|extended) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1764:1764:1764) (1796:1796:1796)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (758:758:758)) - (PORT datab (664:664:664) (692:692:692)) - (PORT datac (260:260:260) (346:346:346)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (553:553:553)) - (PORT datac (1367:1367:1367) (1453:1453:1453)) - (PORT datad (841:841:841) (864:864:864)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1265:1265:1265)) - (PORT datac (641:641:641) (670:670:670)) - (PORT datad (910:910:910) (977:977:977)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~0) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (426:426:426)) - (PORT datac (615:615:615) (667:667:667)) - (PORT datad (726:726:726) (803:803:803)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|released\~0) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (736:736:736)) - (PORT datab (663:663:663) (694:694:694)) - (PORT datad (1337:1337:1337) (1379:1379:1379)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|released) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) - (DELAY - (ABSOLUTE - (PORT dataa (488:488:488) (568:568:568)) - (PORT datab (663:663:663) (740:740:740)) - (PORT datac (606:606:606) (673:673:673)) - (PORT datad (259:259:259) (336:336:336)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~2) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (247:247:247)) - (PORT datac (416:416:416) (498:498:498)) - (PORT datad (651:651:651) (725:725:725)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~3) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (616:616:616)) - (PORT datab (428:428:428) (507:507:507)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|shifted) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (744:744:744) (848:848:848)) - (PORT datab (984:984:984) (1072:1072:1072)) - (PORT datad (962:962:962) (1042:1042:1042)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT datab (751:751:751) (858:858:858)) - (PORT datac (739:739:739) (840:840:840)) - (PORT datad (729:729:729) (835:835:835)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (394:394:394)) - (PORT datab (201:201:201) (241:241:241)) - (PORT datad (175:175:175) (202:202:202)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT datab (963:963:963) (1041:1041:1041)) - (PORT datad (729:729:729) (834:834:834)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (740:740:740) (827:827:827)) - (PORT datab (290:290:290) (378:378:378)) - (PORT datac (649:649:649) (725:725:725)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~32) - (DELAY - (ABSOLUTE - (PORT datab (655:655:655) (729:729:729)) - (PORT datac (395:395:395) (471:471:471)) - (PORT datad (657:657:657) (716:716:716)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (418:418:418)) - (PORT datab (223:223:223) (270:270:270)) - (PORT datac (658:658:658) (723:723:723)) - (PORT datad (433:433:433) (507:507:507)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (269:269:269)) - (PORT datab (622:622:622) (671:671:671)) - (PORT datad (962:962:962) (1038:1038:1038)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1160:1160:1160) (1230:1230:1230)) - (PORT datab (241:241:241) (321:321:321)) - (PORT datac (215:215:215) (291:291:291)) - (PORT datad (548:548:548) (570:570:570)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (969:969:969) (1044:1044:1044)) - (PORT datac (902:902:902) (995:995:995)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1413:1413:1413) (1549:1549:1549)) - (PORT datab (696:696:696) (729:729:729)) - (PORT datac (959:959:959) (1041:1041:1041)) - (PORT datad (190:190:190) (224:224:224)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT datab (981:981:981) (1070:1070:1070)) - (PORT datac (721:721:721) (830:830:830)) - (PORT datad (729:729:729) (838:838:838)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (908:908:908)) - (PORT datab (667:667:667) (685:685:685)) - (PORT datad (496:496:496) (512:512:512)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1414:1414:1414) (1542:1542:1542)) - (PORT datab (213:213:213) (258:258:258)) - (PORT datac (667:667:667) (692:692:692)) - (PORT datad (766:766:766) (872:872:872)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (716:716:716) (818:818:818)) - (PORT datab (363:363:363) (394:394:394)) - (PORT datac (717:717:717) (819:819:819)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1555:1555:1555) (1666:1666:1666)) - (PORT datab (982:982:982) (1037:1037:1037)) - (PORT datad (518:518:518) (530:530:530)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~0) - (DELAY - (ABSOLUTE - (PORT datab (1469:1469:1469) (1606:1606:1606)) - (PORT datac (912:912:912) (975:975:975)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (425:425:425) (503:503:503)) - (PORT datac (1117:1117:1117) (1170:1170:1170)) - (PORT datad (651:651:651) (723:723:723)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (693:693:693) (776:776:776)) - (PORT datab (412:412:412) (493:493:493)) - (PORT datac (606:606:606) (674:674:674)) - (PORT datad (261:261:261) (340:340:340)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (490:490:490) (569:569:569)) - (PORT datab (664:664:664) (741:741:741)) - (PORT datac (497:497:497) (515:515:515)) - (PORT datad (655:655:655) (724:724:724)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (615:615:615)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (768:768:768)) - (PORT datab (1230:1230:1230) (1291:1291:1291)) - (PORT datac (443:443:443) (506:506:506)) - (PORT datad (1066:1066:1066) (1109:1109:1109)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (752:752:752) (844:844:844)) - (PORT datab (1400:1400:1400) (1489:1489:1489)) - (PORT datac (917:917:917) (988:988:988)) - (PORT datad (854:854:854) (921:921:921)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (279:279:279)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (739:739:739) (839:839:839)) - (PORT datad (1547:1547:1547) (1637:1637:1637)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (523:523:523) (533:533:533)) - (PORT datad (944:944:944) (998:998:998)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (670:670:670) (729:729:729)) - (PORT datab (1120:1120:1120) (1195:1195:1195)) - (PORT datac (633:633:633) (694:694:694)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (687:687:687) (745:745:745)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (195:195:195) (228:228:228)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (484:484:484) (550:550:550)) - (PORT datab (1228:1228:1228) (1291:1291:1291)) - (PORT datac (741:741:741) (842:842:842)) - (PORT datad (842:842:842) (867:867:867)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (875:875:875)) - (PORT datab (913:913:913) (986:986:986)) - (PORT datac (1115:1115:1115) (1162:1162:1162)) - (PORT datad (710:710:710) (791:791:791)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (325:325:325)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (395:395:395)) - (PORT datac (700:700:700) (784:784:784)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (776:776:776) (868:868:868)) - (PORT datab (912:912:912) (984:984:984)) - (PORT datac (659:659:659) (735:735:735)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (710:710:710)) - (PORT datab (496:496:496) (580:580:580)) - (PORT datac (396:396:396) (470:470:470)) - (PORT datad (601:601:601) (643:643:643)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (937:937:937)) - (PORT datab (941:941:941) (1038:1038:1038)) - (PORT datac (758:758:758) (878:878:878)) - (PORT datad (764:764:764) (871:871:871)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) - (DELAY - (ABSOLUTE - (PORT dataa (820:820:820) (932:932:932)) - (PORT datab (788:788:788) (904:904:904)) - (PORT datad (763:763:763) (876:876:876)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) - (DELAY - (ABSOLUTE - (PORT dataa (824:824:824) (935:935:935)) - (PORT datab (938:938:938) (1037:1037:1037)) - (PORT datac (757:757:757) (875:875:875)) - (PORT datad (764:764:764) (875:875:875)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~7) - (DELAY - (ABSOLUTE - (PORT dataa (232:232:232) (279:279:279)) - (PORT datab (941:941:941) (1039:1039:1039)) - (PORT datac (311:311:311) (337:337:337)) - (PORT datad (1387:1387:1387) (1504:1504:1504)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1416:1416:1416) (1544:1544:1544)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (932:932:932) (1003:1003:1003)) - (PORT datad (517:517:517) (528:528:528)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (398:398:398)) - (PORT datab (274:274:274) (359:359:359)) - (PORT datad (604:604:604) (617:617:617)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1387:1387:1387) (1447:1447:1447)) - (PORT datab (411:411:411) (471:471:471)) - (PORT datac (1375:1375:1375) (1408:1408:1408)) - (PORT datad (583:583:583) (631:631:631)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (804:804:804)) - (PORT datab (3348:3348:3348) (3488:3488:3488)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1705:1705:1705) (1713:1713:1713)) - (PORT datab (1225:1225:1225) (1301:1301:1301)) - (PORT datac (636:636:636) (675:675:675)) - (PORT datad (1144:1144:1144) (1160:1160:1160)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1504:1504:1504) (1628:1628:1628)) - (PORT datab (1226:1226:1226) (1302:1302:1302)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1240:1240:1240) (1368:1368:1368)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1042:1042:1042)) - (PORT datab (636:636:636) (676:676:676)) - (PORT datac (240:240:240) (293:293:293)) - (PORT datad (1667:1667:1667) (1728:1728:1728)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT datab (912:912:912) (931:931:931)) - (PORT datac (945:945:945) (986:986:986)) - (PORT datad (219:219:219) (254:254:254)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (310:310:310)) - (PORT datab (705:705:705) (769:769:769)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (208:208:208) (240:240:240)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|ir_\|opcode\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (195:195:195) (220:220:220)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1557:1557:1557)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (284:284:284) (380:380:380)) - (PORT datac (903:903:903) (966:966:966)) - (PORT datad (928:928:928) (982:982:982)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1410:1410:1410) (1521:1521:1521)) - (PORT datab (897:897:897) (911:911:911)) - (PORT datac (924:924:924) (1011:1011:1011)) - (PORT datad (876:876:876) (894:894:894)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1572:1572:1572) (1710:1710:1710)) - (PORT datab (2337:2337:2337) (2410:2410:2410)) - (PORT datac (671:671:671) (718:718:718)) - (PORT datad (2748:2748:2748) (2873:2873:2873)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (232:232:232) (283:283:283)) - (PORT datac (195:195:195) (238:238:238)) - (PORT datad (371:371:371) (399:399:399)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (658:658:658)) - (PORT datab (427:427:427) (471:471:471)) - (PORT datac (543:543:543) (559:559:559)) - (PORT datad (1164:1164:1164) (1218:1218:1218)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1490:1490:1490) (1592:1592:1592)) - (PORT datab (438:438:438) (474:474:474)) - (PORT datac (943:943:943) (994:994:994)) - (PORT datad (211:211:211) (243:243:243)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) - (DELAY - (ABSOLUTE - (PORT dataa (974:974:974) (1047:1047:1047)) - (PORT datab (1110:1110:1110) (1179:1179:1179)) - (PORT datac (1261:1261:1261) (1313:1313:1313)) - (PORT datad (1359:1359:1359) (1384:1384:1384)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1101:1101:1101) (1122:1122:1122)) - (PORT datab (961:961:961) (1050:1050:1050)) - (PORT datac (1264:1264:1264) (1310:1310:1310)) - (PORT datad (1206:1206:1206) (1270:1270:1270)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1505:1505:1505) (1526:1526:1526)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (868:868:868) (865:865:865)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1606:1606:1606) (1627:1627:1627)) - (PORT datab (831:831:831) (859:859:859)) - (PORT datad (1029:1029:1029) (1028:1028:1028)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1568:1568:1568) (1597:1597:1597)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (643:643:643) (684:684:684)) - (PORT datad (555:555:555) (558:558:558)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (650:650:650)) - (PORT datab (552:552:552) (565:565:565)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (372:372:372) (397:397:397)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~21) - (DELAY - (ABSOLUTE - (PORT dataa (2257:2257:2257) (2337:2337:2337)) - (PORT datab (1549:1549:1549) (1673:1673:1673)) - (PORT datac (902:902:902) (922:922:922)) - (PORT datad (1165:1165:1165) (1178:1178:1178)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) - (DELAY - (ABSOLUTE - (PORT datab (230:230:230) (277:277:277)) - (PORT datac (343:343:343) (365:365:365)) - (PORT datad (369:369:369) (394:394:394)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1298:1298:1298) (1395:1395:1395)) - (PORT datab (927:927:927) (974:974:974)) - (PORT datac (1940:1940:1940) (2070:2070:2070)) - (PORT datad (2052:2052:2052) (2214:2214:2214)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) - (DELAY - (ABSOLUTE - (PORT dataa (855:855:855) (906:906:906)) - (PORT datab (230:230:230) (277:277:277)) - (PORT datac (196:196:196) (240:240:240)) - (PORT datad (370:370:370) (394:394:394)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1167:1167:1167)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (222:222:222) (268:268:268)) - (PORT datac (200:200:200) (236:236:236)) - (PORT datad (223:223:223) (250:250:250)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1938:1938:1938) (2062:2062:2062)) - (PORT datab (2594:2594:2594) (2695:2695:2695)) - (PORT datad (1436:1436:1436) (1528:1528:1528)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (720:720:720)) - (PORT datab (699:699:699) (758:758:758)) - (PORT datac (1095:1095:1095) (1090:1090:1090)) - (PORT datad (644:644:644) (692:692:692)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (611:611:611) (632:632:632)) - (PORT datad (777:777:777) (789:789:789)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (890:890:890)) - (PORT datab (332:332:332) (362:362:362)) - (PORT datac (372:372:372) (397:397:397)) - (PORT datad (604:604:604) (626:626:626)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1811:1811:1811) (1903:1903:1903)) - (PORT datab (921:921:921) (989:989:989)) - (PORT datac (923:923:923) (1008:1008:1008)) - (PORT datad (436:436:436) (468:468:468)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (966:966:966)) - (PORT datac (902:902:902) (921:921:921)) - (PORT datad (1383:1383:1383) (1455:1455:1455)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (418:418:418) (444:444:444)) - (PORT datac (192:192:192) (225:225:225)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1154:1154:1154) (1242:1242:1242)) - (PORT datab (196:196:196) (236:236:236)) - (PORT datac (593:593:593) (604:604:604)) - (PORT datad (376:376:376) (396:396:396)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1240:1240:1240)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datad (877:877:877) (932:932:932)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) - (DELAY - (ABSOLUTE - (PORT dataa (2446:2446:2446) (2535:2535:2535)) - (PORT datab (1615:1615:1615) (1728:1728:1728)) - (PORT datac (1769:1769:1769) (1897:1897:1897)) - (PORT datad (1666:1666:1666) (1684:1684:1684)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1432:1432:1432) (1515:1515:1515)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (1052:1052:1052) (1100:1100:1100)) - (PORT datad (1335:1335:1335) (1356:1356:1356)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1121:1121:1121) (1241:1241:1241)) - (PORT datac (884:884:884) (939:939:939)) - (PORT datad (957:957:957) (1022:1022:1022)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (935:935:935)) - (PORT datab (944:944:944) (1021:1021:1021)) - (PORT datac (588:588:588) (603:603:603)) - (PORT datad (537:537:537) (536:536:536)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (838:838:838) (860:860:860)) - (PORT datac (169:169:169) (202:202:202)) - (PORT datad (195:195:195) (228:228:228)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1156:1156:1156) (1255:1255:1255)) - (PORT datab (257:257:257) (345:345:345)) - (PORT datac (214:214:214) (290:290:290)) - (PORT datad (580:580:580) (615:615:615)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~20) - (DELAY - (ABSOLUTE - (PORT dataa (572:572:572) (607:607:607)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (590:590:590) (613:613:613)) - (PORT datad (600:600:600) (615:615:615)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1561:1561:1561) (1706:1706:1706)) - (PORT datab (2568:2568:2568) (2670:2670:2670)) - (PORT datac (1057:1057:1057) (1083:1083:1083)) - (PORT datad (862:862:862) (898:898:898)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1089:1089:1089) (1120:1120:1120)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1186:1186:1186) (1228:1228:1228)) - (PORT datad (564:564:564) (579:579:579)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (920:920:920)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (237:237:237) (278:278:278)) - (PORT datad (594:594:594) (611:611:611)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) - (DELAY - (ABSOLUTE - (PORT dataa (948:948:948) (1036:1036:1036)) - (PORT datab (263:263:263) (310:310:310)) - (PORT datac (1393:1393:1393) (1475:1475:1475)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) - (DELAY - (ABSOLUTE - (PORT dataa (923:923:923) (950:950:950)) - (PORT datab (1129:1129:1129) (1199:1199:1199)) - (PORT datac (889:889:889) (932:932:932)) - (PORT datad (1015:1015:1015) (1011:1011:1011)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_set\~0) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (514:514:514)) - (PORT datab (896:896:896) (914:914:914)) - (PORT datac (922:922:922) (1007:1007:1007)) - (PORT datad (405:405:405) (434:434:434)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) - (DELAY - (ABSOLUTE - (PORT datab (1062:1062:1062) (1088:1088:1088)) - (PORT datac (208:208:208) (250:250:250)) - (PORT datad (209:209:209) (241:241:241)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~9) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (524:524:524) (539:539:539)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_cf) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (240:240:240)) - (PORT datab (594:594:594) (613:613:613)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (567:567:567) (592:592:592)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (746:746:746)) - (PORT datab (661:661:661) (721:721:721)) - (PORT datac (883:883:883) (903:903:903)) - (PORT datad (893:893:893) (916:916:916)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (1154:1154:1154) (1188:1188:1188)) - (PORT datad (629:629:629) (643:643:643)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (408:408:408)) - (PORT datab (644:644:644) (678:678:678)) - (PORT datac (871:871:871) (896:896:896)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (701:701:701) (721:721:721)) - (PORT datab (956:956:956) (981:981:981)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (217:217:217) (250:250:250)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (688:688:688) (772:772:772)) - (PORT datac (1115:1115:1115) (1160:1160:1160)) - (PORT datad (739:739:739) (827:827:827)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (785:785:785) (871:871:871)) - (PORT datab (725:725:725) (810:810:810)) - (PORT datac (1118:1118:1118) (1161:1161:1161)) - (PORT datad (711:711:711) (788:788:788)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (915:915:915) (989:989:989)) - (PORT datac (1116:1116:1116) (1162:1162:1162)) - (PORT datad (329:329:329) (349:349:349)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (212:212:212) (261:261:261)) - (PORT datab (199:199:199) (239:239:239)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (727:727:727) (814:814:814)) - (PORT datab (981:981:981) (1068:1068:1068)) - (PORT datac (722:722:722) (831:831:831)) - (PORT datad (729:729:729) (835:835:835)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (903:903:903)) - (PORT datab (736:736:736) (834:834:834)) - (PORT datac (710:710:710) (811:811:811)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (390:390:390)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datad (338:338:338) (357:357:357)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1159:1159:1159) (1230:1230:1230)) - (PORT datab (724:724:724) (793:793:793)) - (PORT datac (214:214:214) (291:291:291)) - (PORT datad (550:550:550) (572:572:572)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (949:949:949) (1028:1028:1028)) - (PORT datab (779:779:779) (879:879:879)) - (PORT datac (1365:1365:1365) (1458:1458:1458)) - (PORT datad (1189:1189:1189) (1251:1251:1251)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~76) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (382:382:382)) - (PORT datab (281:281:281) (364:364:364)) - (PORT datac (928:928:928) (975:975:975)) - (PORT datad (1494:1494:1494) (1585:1585:1585)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~73) - (DELAY - (ABSOLUTE - (PORT datac (740:740:740) (842:842:842)) - (PORT datad (1190:1190:1190) (1255:1255:1255)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (782:782:782) (872:872:872)) - (PORT datab (728:728:728) (815:815:815)) - (PORT datac (884:884:884) (953:953:953)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (751:751:751) (844:844:844)) - (PORT datab (1502:1502:1502) (1605:1605:1605)) - (PORT datac (916:916:916) (991:991:991)) - (PORT datad (852:852:852) (919:919:919)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~74) - (DELAY - (ABSOLUTE - (PORT dataa (588:588:588) (610:610:610)) - (PORT datab (344:344:344) (369:369:369)) - (PORT datac (1366:1366:1366) (1452:1452:1452)) - (PORT datad (1547:1547:1547) (1637:1637:1637)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (245:245:245)) - (PORT datab (201:201:201) (241:241:241)) - (PORT datac (448:448:448) (513:513:513)) - (PORT datad (841:841:841) (864:864:864)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (556:556:556) (571:571:571)) - (PORT datab (335:335:335) (364:364:364)) - (PORT datad (736:736:736) (824:824:824)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (758:758:758) (862:862:862)) - (PORT datab (729:729:729) (828:828:828)) - (PORT datac (335:335:335) (363:363:363)) - (PORT datad (1132:1132:1132) (1201:1201:1201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~72) - (DELAY - (ABSOLUTE - (PORT datab (199:199:199) (239:239:239)) - (PORT datad (718:718:718) (814:814:814)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (455:455:455)) - (PORT datab (1124:1124:1124) (1199:1199:1199)) - (PORT datac (636:636:636) (698:698:698)) - (PORT datad (629:629:629) (680:680:680)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (1557:1557:1557) (1665:1665:1665)) - (PORT datab (981:981:981) (1035:1035:1035)) - (PORT datad (515:515:515) (529:529:529)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (489:489:489) (569:569:569)) - (PORT datac (607:607:607) (672:672:672)) - (PORT datad (260:260:260) (335:335:335)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (404:404:404) (428:428:428)) - (PORT datab (848:848:848) (850:850:850)) - (PORT datad (734:734:734) (821:821:821)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~1) - (DELAY - (ABSOLUTE - (PORT datab (1472:1472:1472) (1607:1607:1607)) - (PORT datac (347:347:347) (411:411:411)) - (PORT datad (901:901:901) (962:962:962)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (220:220:220) (260:260:260)) - (PORT datac (215:215:215) (291:291:291)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~1) - (DELAY - (ABSOLUTE - (PORT datac (1076:1076:1076) (1171:1171:1171)) - (PORT datad (1031:1031:1031) (1115:1115:1115)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (1413:1413:1413) (1543:1543:1543)) - (PORT datab (788:788:788) (903:903:903)) - (PORT datac (960:960:960) (1037:1037:1037)) - (PORT datad (777:777:777) (882:882:882)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (256:256:256)) - (PORT datab (675:675:675) (704:704:704)) - (PORT datac (604:604:604) (622:622:622)) - (PORT datad (901:901:901) (976:976:976)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~92) - (DELAY - (ABSOLUTE - (PORT datab (968:968:968) (1057:1057:1057)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~63) - (DELAY - (ABSOLUTE - (PORT datac (654:654:654) (724:724:724)) - (PORT datad (637:637:637) (707:707:707)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) - (DELAY - (ABSOLUTE - (PORT datab (654:654:654) (726:726:726)) - (PORT datac (693:693:693) (782:782:782)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (258:258:258)) - (PORT datab (473:473:473) (549:549:549)) - (PORT datac (637:637:637) (704:704:704)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~132) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (277:277:277)) - (PORT datab (665:665:665) (741:741:741)) - (PORT datad (650:650:650) (727:727:727)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (926:926:926)) - (PORT datab (223:223:223) (262:262:262)) - (PORT datac (337:337:337) (360:360:360)) - (PORT datad (543:543:543) (562:562:562)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (815:815:815) (820:820:820)) - (PORT datad (946:946:946) (995:995:995)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1387:1387:1387) (1444:1444:1444)) - (PORT datab (598:598:598) (652:652:652)) - (PORT datac (1375:1375:1375) (1406:1406:1406)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (804:804:804)) - (PORT datab (3349:3349:3349) (3490:3490:3490)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (891:891:891) (902:902:902)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1236:1236:1236) (1280:1280:1280)) - (PORT d[1] (983:983:983) (1045:1045:1045)) - (PORT d[2] (962:962:962) (977:977:977)) - (PORT d[3] (1021:1021:1021) (1074:1074:1074)) - (PORT d[4] (2601:2601:2601) (2818:2818:2818)) - (PORT d[5] (1028:1028:1028) (1063:1063:1063)) - (PORT d[6] (994:994:994) (1056:1056:1056)) - (PORT d[7] (954:954:954) (1016:1016:1016)) - (PORT d[8] (1046:1046:1046) (1093:1093:1093)) - (PORT d[9] (998:998:998) (1055:1055:1055)) - (PORT d[10] (1047:1047:1047) (1121:1121:1121)) - (PORT d[11] (2576:2576:2576) (2762:2762:2762)) - (PORT d[12] (1307:1307:1307) (1386:1386:1386)) + (PORT d[0] (1902:1902:1902) (2025:2025:2025)) + (PORT d[1] (1666:1666:1666) (1705:1705:1705)) + (PORT d[2] (1974:1974:1974) (2139:2139:2139)) + (PORT d[3] (1912:1912:1912) (1969:1969:1969)) + (PORT d[4] (2671:2671:2671) (2790:2790:2790)) + (PORT d[5] (2298:2298:2298) (2357:2357:2357)) + (PORT d[6] (1731:1731:1731) (1793:1793:1793)) + (PORT d[7] (2013:2013:2013) (2076:2076:2076)) + (PORT d[8] (1842:1842:1842) (1934:1934:1934)) + (PORT d[9] (2037:2037:2037) (2110:2110:2110)) + (PORT d[10] (1682:1682:1682) (1747:1747:1747)) + (PORT d[11] (4325:4325:4325) (4639:4639:4639)) + (PORT d[12] (1649:1649:1649) (1703:1703:1703)) (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) @@ -39334,70 +44845,27 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) (DELAY (ABSOLUTE - (PORT d[0] (951:951:951) (911:911:911)) (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (1484:1484:1484) (1455:1455:1455)) + (PORT d[0] (1818:1818:1818) (1849:1849:1849)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) + (PORT clk (1858:1858:1858) (1884:1884:1884)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1820:1820:1820) (1846:1846:1846)) @@ -39411,7 +44879,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1005:1005:1005) (1009:1009:1009)) @@ -39420,7 +44888,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -39429,7 +44897,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -39439,7 +44907,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -39449,729 +44917,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (980:980:980) (991:991:991)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (706:706:706) (727:727:727)) - (PORT d[1] (2392:2392:2392) (2624:2624:2624)) - (PORT d[2] (1503:1503:1503) (1540:1540:1540)) - (PORT d[3] (981:981:981) (1040:1040:1040)) - (PORT d[4] (2591:2591:2591) (2807:2807:2807)) - (PORT d[5] (3468:3468:3468) (3668:3668:3668)) - (PORT d[6] (1271:1271:1271) (1334:1334:1334)) - (PORT d[7] (3191:3191:3191) (3366:3366:3366)) - (PORT d[8] (691:691:691) (713:713:713)) - (PORT d[9] (1603:1603:1603) (1661:1661:1661)) - (PORT d[10] (1346:1346:1346) (1434:1434:1434)) - (PORT d[11] (2230:2230:2230) (2413:2413:2413)) - (PORT d[12] (1570:1570:1570) (1649:1649:1649)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (671:671:671) (627:627:627)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (1485:1485:1485) (1441:1441:1441)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1101:1101:1101) (1111:1111:1111)) - (PORT clk (1859:1859:1859) (1886:1886:1886)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (986:986:986) (1014:1014:1014)) - (PORT d[1] (3450:3450:3450) (3742:3742:3742)) - (PORT d[2] (1249:1249:1249) (1290:1290:1290)) - (PORT d[3] (1284:1284:1284) (1331:1331:1331)) - (PORT d[4] (2575:2575:2575) (2806:2806:2806)) - (PORT d[5] (3485:3485:3485) (3709:3709:3709)) - (PORT d[6] (1317:1317:1317) (1415:1415:1415)) - (PORT d[7] (1218:1218:1218) (1279:1279:1279)) - (PORT d[8] (1003:1003:1003) (1027:1027:1027)) - (PORT d[9] (1567:1567:1567) (1623:1623:1623)) - (PORT d[10] (1356:1356:1356) (1454:1454:1454)) - (PORT d[11] (2251:2251:2251) (2436:2436:2436)) - (PORT d[12] (1606:1606:1606) (1702:1702:1702)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (963:963:963) (919:919:919)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1886:1886:1886)) - (PORT d[0] (1702:1702:1702) (1655:1655:1655)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (409:409:409)) - (PORT datab (686:686:686) (752:752:752)) - (PORT datac (651:651:651) (716:716:716)) - (PORT datad (645:645:645) (655:655:655)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1183:1183:1183) (1208:1208:1208)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3642:3642:3642) (3824:3824:3824)) - (PORT d[1] (1366:1366:1366) (1493:1493:1493)) - (PORT d[2] (2003:2003:2003) (2099:2099:2099)) - (PORT d[3] (2459:2459:2459) (2585:2585:2585)) - (PORT d[4] (2200:2200:2200) (2332:2332:2332)) - (PORT d[5] (1345:1345:1345) (1450:1450:1450)) - (PORT d[6] (1456:1456:1456) (1487:1487:1487)) - (PORT d[7] (3346:3346:3346) (3494:3494:3494)) - (PORT d[8] (3607:3607:3607) (3856:3856:3856)) - (PORT d[9] (3167:3167:3167) (3306:3306:3306)) - (PORT d[10] (3154:3154:3154) (3327:3327:3327)) - (PORT d[11] (1793:1793:1793) (1891:1891:1891)) - (PORT d[12] (1416:1416:1416) (1454:1454:1454)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1620:1620:1620) (1580:1580:1580)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (PORT d[0] (2766:2766:2766) (2809:2809:2809)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1837:1837:1837)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (1047:1047:1047) (1075:1075:1075)) - (PORT datab (1410:1410:1410) (1504:1504:1504)) - (PORT datac (532:532:532) (545:545:545)) - (PORT datad (1173:1173:1173) (1173:1173:1173)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1641:1641:1641) (1729:1729:1729)) - (PORT clk (1857:1857:1857) (1885:1885:1885)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2872:2872:2872) (2966:2966:2966)) - (PORT d[1] (2017:2017:2017) (2182:2182:2182)) - (PORT d[2] (1954:1954:1954) (2061:2061:2061)) - (PORT d[3] (1897:1897:1897) (2022:2022:2022)) - (PORT d[4] (3021:3021:3021) (3172:3172:3172)) - (PORT d[5] (2229:2229:2229) (2391:2391:2391)) - (PORT d[6] (1711:1711:1711) (1774:1774:1774)) - (PORT d[7] (2133:2133:2133) (2250:2250:2250)) - (PORT d[8] (2427:2427:2427) (2610:2610:2610)) - (PORT d[9] (1679:1679:1679) (1785:1785:1785)) - (PORT d[10] (1442:1442:1442) (1508:1508:1508)) - (PORT d[11] (1723:1723:1723) (1780:1780:1780)) - (PORT d[12] (2286:2286:2286) (2347:2347:2347)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2567:2567:2567) (2620:2620:2620)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1885:1885:1885)) - (PORT d[0] (3733:3733:3733) (3648:3648:3648)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1810:1810:1810)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2034:2034:2034) (2028:2028:2028)) - (PORT clk (1822:1822:1822) (1816:1816:1816)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4393:4393:4393) (4461:4461:4461)) - (PORT d[1] (4131:4131:4131) (4181:4181:4181)) - (PORT d[2] (4247:4247:4247) (4323:4323:4323)) - (PORT d[3] (4546:4546:4546) (4614:4614:4614)) - (PORT d[4] (4322:4322:4322) (4309:4309:4309)) - (PORT d[5] (4617:4617:4617) (4651:4651:4651)) - (PORT d[6] (4408:4408:4408) (4485:4485:4485)) - (PORT d[7] (4302:4302:4302) (4274:4274:4274)) - (PORT d[8] (4572:4572:4572) (4637:4637:4637)) - (PORT d[9] (4446:4446:4446) (4691:4691:4691)) - (PORT d[10] (4705:4705:4705) (4743:4743:4743)) - (PORT d[11] (4358:4358:4358) (4390:4390:4390)) - (PORT d[12] (4507:4507:4507) (4645:4645:4645)) - (PORT clk (1818:1818:1818) (1812:1812:1812)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1816:1816:1816)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1812:1812:1812)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2840:2840:2840) (2949:2949:2949)) - (PORT d[1] (1732:1732:1732) (1897:1897:1897)) - (PORT d[2] (1932:1932:1932) (2053:2053:2053)) - (PORT d[3] (1899:1899:1899) (2019:2019:2019)) - (PORT d[4] (2772:2772:2772) (2916:2916:2916)) - (PORT d[5] (2232:2232:2232) (2415:2415:2415)) - (PORT d[6] (2007:2007:2007) (2069:2069:2069)) - (PORT d[7] (2130:2130:2130) (2260:2260:2260)) - (PORT d[8] (2390:2390:2390) (2571:2571:2571)) - (PORT d[9] (1959:1959:1959) (2082:2082:2082)) - (PORT d[10] (1985:1985:1985) (2067:2067:2067)) - (PORT d[11] (2017:2017:2017) (2091:2091:2091)) - (PORT d[12] (2566:2566:2566) (2656:2656:2656)) + (PORT d[0] (2479:2479:2479) (2628:2628:2628)) + (PORT d[1] (2661:2661:2661) (2805:2805:2805)) + (PORT d[2] (2218:2218:2218) (2383:2383:2383)) + (PORT d[3] (2113:2113:2113) (2258:2258:2258)) + (PORT d[4] (2079:2079:2079) (2164:2164:2164)) + (PORT d[5] (2439:2439:2439) (2558:2558:2558)) + (PORT d[6] (2443:2443:2443) (2606:2606:2606)) + (PORT d[7] (3431:3431:3431) (3496:3496:3496)) + (PORT d[8] (2846:2846:2846) (2932:2932:2932)) + (PORT d[9] (2326:2326:2326) (2495:2495:2495)) + (PORT d[10] (3304:3304:3304) (3449:3449:3449)) + (PORT d[11] (2127:2127:2127) (2238:2238:2238)) + (PORT d[12] (2274:2274:2274) (2444:2444:2444)) (PORT clk (1859:1859:1859) (1884:1884:1884)) ) ) @@ -40181,17 +44942,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1859:1859:1859) (1884:1884:1884)) - (PORT d[0] (2730:2730:2730) (2796:2796:2796)) + (PORT d[0] (2586:2586:2586) (2674:2674:2674)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1860:1860:1860) (1885:1885:1885)) @@ -40201,7 +44962,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1822:1822:1822) (1847:1847:1847)) @@ -40215,7 +44976,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1007:1007:1007) (1010:1010:1010)) @@ -40224,7 +44985,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1008:1008:1008) (1011:1011:1011)) @@ -40233,7 +44994,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1008:1008:1008) (1011:1011:1011)) @@ -40243,7 +45004,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1008:1008:1008) (1011:1011:1011)) @@ -40253,11 +45014,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1622:1622:1622) (1706:1706:1706)) - (PORT clk (1855:1855:1855) (1883:1883:1883)) + (PORT d[0] (1617:1617:1617) (1708:1708:1708)) + (PORT clk (1857:1857:1857) (1885:1885:1885)) ) ) (TIMINGCHECK @@ -40266,23 +45027,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2870:2870:2870) (2964:2964:2964)) - (PORT d[1] (2048:2048:2048) (2231:2231:2231)) - (PORT d[2] (1893:1893:1893) (1990:1990:1990)) - (PORT d[3] (1883:1883:1883) (2014:2014:2014)) - (PORT d[4] (3037:3037:3037) (3174:3174:3174)) - (PORT d[5] (1957:1957:1957) (2122:2122:2122)) - (PORT d[6] (1728:1728:1728) (1783:1783:1783)) - (PORT d[7] (1821:1821:1821) (1856:1856:1856)) - (PORT d[8] (2421:2421:2421) (2612:2612:2612)) - (PORT d[9] (1968:1968:1968) (2080:2080:2080)) - (PORT d[10] (2002:2002:2002) (2089:2089:2089)) - (PORT d[11] (2528:2528:2528) (2597:2597:2597)) - (PORT d[12] (2240:2240:2240) (2309:2309:2309)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2779:2779:2779) (2918:2918:2918)) + (PORT d[1] (2949:2949:2949) (3110:3110:3110)) + (PORT d[2] (1977:1977:1977) (2112:2112:2112)) + (PORT d[3] (1867:1867:1867) (1994:1994:1994)) + (PORT d[4] (2099:2099:2099) (2223:2223:2223)) + (PORT d[5] (2640:2640:2640) (2717:2717:2717)) + (PORT d[6] (2148:2148:2148) (2291:2291:2291)) + (PORT d[7] (3421:3421:3421) (3502:3502:3502)) + (PORT d[8] (3155:3155:3155) (3258:3258:3258)) + (PORT d[9] (2282:2282:2282) (2439:2439:2439)) + (PORT d[10] (1914:1914:1914) (2041:2041:2041)) + (PORT d[11] (2100:2100:2100) (2231:2231:2231)) + (PORT d[12] (2417:2417:2417) (2564:2564:2564)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) ) ) (TIMINGCHECK @@ -40291,11 +45052,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2519:2519:2519) (2503:2503:2503)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2032:2032:2032) (1996:1996:1996)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) ) ) (TIMINGCHECK @@ -40304,60 +45065,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (PORT d[0] (3674:3674:3674) (3756:3756:3756)) + (PORT clk (1857:1857:1857) (1885:1885:1885)) + (PORT d[0] (3200:3200:3200) (3274:3274:3274)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) + (PORT clk (1858:1858:1858) (1886:1886:1886)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) + (PORT clk (1858:1858:1858) (1886:1886:1886)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) + (PORT clk (1858:1858:1858) (1886:1886:1886)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) + (PORT clk (1858:1858:1858) (1886:1886:1886)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1810:1810:1810) (1808:1808:1808)) + (PORT clk (1812:1812:1812) (1810:1810:1810)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -40368,11 +45129,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2034:2034:2034) (2023:2023:2023)) - (PORT clk (1820:1820:1820) (1814:1814:1814)) + (PORT d[0] (2121:2121:2121) (2166:2166:2166)) + (PORT clk (1822:1822:1822) (1816:1816:1816)) ) ) (TIMINGCHECK @@ -40381,23 +45142,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4437:4437:4437) (4508:4508:4508)) - (PORT d[1] (4211:4211:4211) (4251:4251:4251)) - (PORT d[2] (4278:4278:4278) (4341:4341:4341)) - (PORT d[3] (4543:4543:4543) (4609:4609:4609)) - (PORT d[4] (4346:4346:4346) (4342:4342:4342)) - (PORT d[5] (4610:4610:4610) (4641:4641:4641)) - (PORT d[6] (4708:4708:4708) (4757:4757:4757)) - (PORT d[7] (4312:4312:4312) (4268:4268:4268)) - (PORT d[8] (4489:4489:4489) (4504:4504:4504)) - (PORT d[9] (4453:4453:4453) (4722:4722:4722)) - (PORT d[10] (4622:4622:4622) (4654:4654:4654)) - (PORT d[11] (4366:4366:4366) (4392:4392:4392)) - (PORT d[12] (4506:4506:4506) (4645:4645:4645)) - (PORT clk (1816:1816:1816) (1810:1810:1810)) + (PORT d[0] (4469:4469:4469) (4578:4578:4578)) + (PORT d[1] (4411:4411:4411) (4529:4529:4529)) + (PORT d[2] (4405:4405:4405) (4501:4501:4501)) + (PORT d[3] (4285:4285:4285) (4378:4378:4378)) + (PORT d[4] (4390:4390:4390) (4479:4479:4479)) + (PORT d[5] (4452:4452:4452) (4565:4565:4565)) + (PORT d[6] (4355:4355:4355) (4476:4476:4476)) + (PORT d[7] (4330:4330:4330) (4373:4373:4373)) + (PORT d[8] (4626:4626:4626) (4732:4732:4732)) + (PORT d[9] (4460:4460:4460) (4519:4519:4519)) + (PORT d[10] (4392:4392:4392) (4490:4490:4490)) + (PORT d[11] (4393:4393:4393) (4515:4515:4515)) + (PORT d[12] (4353:4353:4353) (4336:4336:4336)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) ) ) (TIMINGCHECK @@ -40406,206 +45167,109 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1820:1820:1820) (1814:1814:1814)) + (PORT clk (1822:1822:1822) (1816:1816:1816)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) + (PORT clk (1823:1823:1823) (1817:1817:1817)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) + (PORT clk (1823:1823:1823) (1817:1817:1817)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) + (PORT clk (1823:1823:1823) (1817:1817:1817)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) + (PORT clk (1823:1823:1823) (1817:1817:1817)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~52) + (INSTANCE D\[1\]\~35) (DELAY (ABSOLUTE - (PORT dataa (1206:1206:1206) (1287:1287:1287)) - (PORT datab (1437:1437:1437) (1489:1489:1489)) - (PORT datac (1126:1126:1126) (1177:1177:1177)) - (PORT datad (1429:1429:1429) (1485:1485:1485)) + (PORT dataa (931:931:931) (978:978:978)) + (PORT datab (772:772:772) (879:879:879)) + (PORT datac (1450:1450:1450) (1528:1528:1528)) + (PORT datad (1149:1149:1149) (1208:1208:1208)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~36) (DELAY (ABSOLUTE - (PORT d[0] (3633:3633:3633) (3814:3814:3814)) - (PORT d[1] (2642:2642:2642) (2867:2867:2867)) - (PORT d[2] (1648:1648:1648) (1726:1726:1726)) - (PORT d[3] (2160:2160:2160) (2263:2263:2263)) - (PORT d[4] (2162:2162:2162) (2254:2254:2254)) - (PORT d[5] (1662:1662:1662) (1786:1786:1786)) - (PORT d[6] (1132:1132:1132) (1171:1171:1171)) - (PORT d[7] (1160:1160:1160) (1190:1190:1190)) - (PORT d[8] (2171:2171:2171) (2353:2353:2353)) - (PORT d[9] (2266:2266:2266) (2413:2413:2413)) - (PORT d[10] (2562:2562:2562) (2693:2693:2693)) - (PORT d[11] (915:915:915) (961:961:961)) - (PORT d[12] (1750:1750:1750) (1775:1775:1775)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1874:1874:1874)) - (PORT d[0] (3453:3453:3453) (3330:3330:3330)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1837:1837:1837)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + (PORT dataa (1069:1069:1069) (1095:1095:1095)) + (PORT datab (1028:1028:1028) (1086:1086:1086)) + (PORT datac (1634:1634:1634) (1682:1682:1682)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~53) + (INSTANCE D\[1\]\~37) (DELAY (ABSOLUTE - (PORT dataa (1208:1208:1208) (1217:1217:1217)) - (PORT datab (1079:1079:1079) (1088:1088:1088)) - (PORT datac (181:181:181) (219:219:219)) - (PORT datad (1384:1384:1384) (1408:1408:1408)) + (PORT dataa (751:751:751) (855:855:855)) + (PORT datab (1736:1736:1736) (1857:1857:1857)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (182:182:182) (212:212:212)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~54) + (INSTANCE D\[1\]\~118) (DELAY (ABSOLUTE - (PORT dataa (1502:1502:1502) (1614:1614:1614)) - (PORT datab (951:951:951) (1007:1007:1007)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~106) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (778:778:778)) - (PORT datab (1164:1164:1164) (1255:1255:1255)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (174:174:174) (198:198:198)) + (PORT dataa (1727:1727:1727) (1788:1788:1788)) + (PORT datab (3006:3006:3006) (3259:3259:3259)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (175:175:175) (201:201:201)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -40615,45 +45279,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~57) + (INSTANCE D\[1\]\~40) (DELAY (ABSOLUTE - (PORT dataa (1972:1972:1972) (2064:2064:2064)) - (PORT datab (1148:1148:1148) (1200:1200:1200)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (843:843:843) (868:868:868)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (933:933:933) (952:952:952)) + (PORT datab (904:904:904) (927:927:927)) + (PORT datac (1645:1645:1645) (1661:1661:1661)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~58) + (INSTANCE D\[1\]\~41) (DELAY (ABSOLUTE - (PORT dataa (1975:1975:1975) (2066:2066:2066)) - (PORT datab (647:647:647) (708:708:708)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1634:1634:1634) (1673:1673:1673)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1165:1165:1165) (1251:1251:1251)) + (PORT datab (1465:1465:1465) (1529:1529:1529)) + (PORT datac (3210:3210:3210) (3305:3305:3305)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) (DELAY (ABSOLUTE - (PORT dataa (977:977:977) (1044:1044:1044)) - (PORT datab (918:918:918) (964:964:964)) - (PORT datac (244:244:244) (297:297:297)) - (PORT datad (1588:1588:1588) (1606:1606:1606)) + (PORT dataa (932:932:932) (991:991:991)) + (PORT datab (424:424:424) (459:459:459)) + (PORT datac (194:194:194) (228:228:228)) + (PORT datad (1128:1128:1128) (1155:1155:1155)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -40663,10 +45327,10 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[0\]) + (INSTANCE z80_\|data_pins_\|dout\[1\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT clk (1527:1527:1527) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) (PORT ena (841:841:841) (846:846:846)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -40679,28 +45343,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~16) + (INSTANCE z80_\|bus_control_\|db\[1\]\~11) (DELAY (ABSOLUTE - (PORT datab (393:393:393) (423:423:423)) - (PORT datac (407:407:407) (468:468:468)) - (PORT datad (674:674:674) (692:692:692)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (981:981:981) (1004:1004:1004)) - (PORT datab (1377:1377:1377) (1376:1376:1376)) - (PORT datac (889:889:889) (939:939:939)) - (PORT datad (892:892:892) (894:894:894)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (266:266:266) (349:349:349)) + (PORT datac (596:596:596) (602:602:602)) + (PORT datad (384:384:384) (411:411:411)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -40709,31 +45359,81 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[0\]) + (INSTANCE z80_\|ir_\|opcode\[1\]) (DELAY (ABSOLUTE - (PORT clk (1519:1519:1519) (1532:1532:1532)) - (PORT asdata (1523:1523:1523) (1555:1555:1555)) - (PORT clrn (1576:1576:1576) (1555:1555:1555)) - (PORT ena (1506:1506:1506) (1484:1484:1484)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1558:1558:1558)) + (PORT ena (1917:1917:1917) (1918:1918:1918)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal63\~0) + (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) (DELAY (ABSOLUTE - (PORT dataa (1988:1988:1988) (2128:2128:2128)) - (PORT datab (1534:1534:1534) (1633:1633:1633)) - (PORT datac (227:227:227) (272:272:272)) - (PORT datad (1108:1108:1108) (1149:1149:1149)) + (PORT dataa (1600:1600:1600) (1731:1731:1731)) + (PORT datab (1942:1942:1942) (2048:2048:2048)) + (PORT datac (365:365:365) (407:407:407)) + (PORT datad (1162:1162:1162) (1219:1219:1219)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instED) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1565:1565:1565) (1545:1545:1545)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (778:778:778) (849:849:849)) + (PORT datab (767:767:767) (837:837:837)) + (PORT datac (1838:1838:1838) (1974:1974:1974)) + (PORT datad (1691:1691:1691) (1759:1759:1759)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2118:2118:2118) (2286:2286:2286)) + (PORT datab (1408:1408:1408) (1515:1515:1515)) + (PORT datac (1119:1119:1119) (1147:1147:1147)) + (PORT datad (878:878:878) (904:904:904)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -40743,15 +45443,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) (DELAY (ABSOLUTE - (PORT dataa (1494:1494:1494) (1599:1599:1599)) - (PORT datab (1480:1480:1480) (1588:1588:1588)) - (PORT datac (1844:1844:1844) (1910:1910:1910)) - (PORT datad (400:400:400) (434:434:434)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (1624:1624:1624) (1656:1656:1656)) + (PORT datab (641:641:641) (673:673:673)) + (PORT datac (1029:1029:1029) (1091:1091:1091)) + (PORT datad (2619:2619:2619) (2695:2695:2695)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -40759,29 +45459,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) (DELAY (ABSOLUTE - (PORT dataa (357:357:357) (496:496:496)) - (PORT datab (712:712:712) (746:746:746)) - (PORT datac (1434:1434:1434) (1535:1535:1535)) - (PORT datad (1300:1300:1300) (1393:1393:1393)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1812:1812:1812) (1882:1882:1882)) + (PORT datab (1076:1076:1076) (1143:1143:1143)) + (PORT datac (829:829:829) (850:850:850)) + (PORT datad (2598:2598:2598) (2658:2658:2658)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~10) + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) (DELAY (ABSOLUTE - (PORT dataa (684:684:684) (734:734:734)) - (PORT datac (1154:1154:1154) (1186:1186:1186)) - (PORT datad (918:918:918) (942:942:942)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (877:877:877) (938:938:938)) + (PORT datab (1059:1059:1059) (1129:1129:1129)) + (PORT datac (1832:1832:1832) (1913:1913:1913)) + (PORT datad (626:626:626) (665:665:665)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1622:1622:1622) (1655:1655:1655)) + (PORT datab (2274:2274:2274) (2434:2434:2434)) + (PORT datac (617:617:617) (675:675:675)) + (PORT datad (986:986:986) (1083:1083:1083)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -40789,304 +45507,60 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~11) + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) (DELAY (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (661:661:661) (720:720:720)) - (PORT datac (871:871:871) (900:900:900)) + (PORT dataa (708:708:708) (768:768:768)) + (PORT datab (947:947:947) (968:968:968)) + (PORT datac (1488:1488:1488) (1481:1481:1481)) + (PORT datad (637:637:637) (690:690:690)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (625:625:625) (645:645:645)) + (PORT datab (1172:1172:1172) (1176:1176:1176)) + (PORT datac (553:553:553) (580:580:580)) + (PORT datad (640:640:640) (656:656:656)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (173:173:173) (197:197:197)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (530:530:530) (558:558:558)) - (PORT datab (903:903:903) (932:932:932)) - (PORT datac (591:591:591) (604:604:604)) - (PORT datad (1156:1156:1156) (1185:1185:1185)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (673:673:673)) - (PORT datab (955:955:955) (981:981:981)) - (PORT datac (646:646:646) (694:694:694)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (897:897:897) (931:931:931)) - (PORT datab (243:243:243) (291:291:291)) - (PORT datac (626:626:626) (680:680:680)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~119) - (DELAY - (ABSOLUTE - (PORT dataa (757:757:757) (859:859:859)) - (PORT datab (722:722:722) (821:821:821)) - (PORT datac (1142:1142:1142) (1227:1227:1227)) - (PORT datad (912:912:912) (978:978:978)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~120) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (707:707:707)) - (PORT datab (345:345:345) (371:371:371)) - (PORT datac (711:711:711) (812:812:812)) - (PORT datad (733:733:733) (834:834:834)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~95) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (904:904:904)) - (PORT datac (708:708:708) (801:801:801)) - (PORT datad (1136:1136:1136) (1221:1221:1221)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~121) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (243:243:243)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~117) - (DELAY - (ABSOLUTE - (PORT dataa (444:444:444) (535:535:535)) - (PORT datab (659:659:659) (735:735:735)) - (PORT datad (723:723:723) (804:804:804)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~136) - (DELAY - (ABSOLUTE - (PORT dataa (563:563:563) (585:585:585)) - (PORT datab (451:451:451) (519:519:519)) - (PORT datad (651:651:651) (723:723:723)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~130) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (763:763:763)) - (PORT datab (663:663:663) (692:692:692)) - (PORT datad (833:833:833) (881:881:881)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~118) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (905:905:905)) - (PORT datab (628:628:628) (650:650:650)) - (PORT datad (616:616:616) (634:634:634)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (894:894:894) (906:906:906)) - (PORT datab (874:874:874) (902:902:902)) - (PORT datac (610:610:610) (671:671:671)) - (PORT datad (657:657:657) (708:708:708)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~126) (DELAY (ABSOLUTE - (PORT dataa (822:822:822) (934:934:934)) - (PORT datab (697:697:697) (727:727:727)) - (PORT datac (960:960:960) (1039:1039:1039)) - (PORT datad (1384:1384:1384) (1501:1501:1501)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~128) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1046:1046:1046)) - (PORT datab (788:788:788) (902:902:902)) - (PORT datac (903:903:903) (997:997:997)) - (PORT datad (767:767:767) (878:878:878)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~129) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (385:385:385)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datad (904:904:904) (977:977:977)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~127) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (636:636:636)) - (PORT datab (964:964:964) (1050:1050:1050)) - (PORT datad (568:568:568) (584:584:584)) + (PORT dataa (210:210:210) (257:257:257)) + (PORT datab (501:501:501) (575:575:575)) + (PORT datad (632:632:632) (650:650:650)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -41099,9 +45573,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) + (PORT clk (1504:1504:1504) (1518:1518:1518)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -41110,46 +45584,16 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1590:1590:1590) (1687:1687:1687)) - (PORT datac (744:744:744) (848:848:848)) - (PORT datad (713:713:713) (799:799:799)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (730:730:730)) - (PORT datab (1231:1231:1231) (1291:1291:1291)) - (PORT datac (920:920:920) (989:989:989)) - (PORT datad (331:331:331) (350:350:350)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~125) (DELAY (ABSOLUTE - (PORT dataa (210:210:210) (260:260:260)) - (PORT datab (965:965:965) (1053:1053:1053)) - (PORT datad (361:361:361) (388:388:388)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (PORT dataa (330:330:330) (441:441:441)) + (PORT datab (383:383:383) (413:413:413)) + (PORT datad (188:188:188) (221:221:221)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -41160,9 +45604,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) + (PORT clk (1505:1505:1505) (1519:1519:1519)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -41173,30 +45617,77 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~79) + (INSTANCE D\[4\]\~88) (DELAY (ABSOLUTE - (PORT dataa (1349:1349:1349) (1392:1392:1392)) - (PORT datab (1223:1223:1223) (1278:1278:1278)) - (PORT datac (216:216:216) (293:293:293)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (415:415:415) (477:477:477)) + (PORT datab (947:947:947) (1001:1001:1001)) + (PORT datac (849:849:849) (861:861:861)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~120) + (DELAY + (ABSOLUTE + (PORT dataa (515:515:515) (595:595:595)) + (PORT datab (932:932:932) (1014:1014:1014)) + (PORT datac (754:754:754) (837:837:837)) + (PORT datad (707:707:707) (775:775:775)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~121) + (DELAY + (ABSOLUTE + (PORT dataa (679:679:679) (702:702:702)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (456:456:456) (525:525:525)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1504:1504:1504) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~122) (DELAY (ABSOLUTE - (PORT dataa (447:447:447) (536:536:536)) - (PORT datab (659:659:659) (734:734:734)) - (PORT datad (725:725:725) (804:804:804)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datab (785:785:785) (866:866:866)) + (PORT datac (1271:1271:1271) (1329:1329:1329)) + (PORT datad (241:241:241) (310:310:310)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -41206,10 +45697,10 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~123) (DELAY (ABSOLUTE - (PORT dataa (585:585:585) (608:608:608)) - (PORT datab (728:728:728) (826:826:826)) - (PORT datac (1546:1546:1546) (1656:1656:1656)) - (PORT datad (580:580:580) (596:596:596)) + (PORT dataa (730:730:730) (818:818:818)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (729:729:729) (816:816:816)) + (PORT datad (620:620:620) (641:641:641)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -41222,11 +45713,11 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~124) (DELAY (ABSOLUTE - (PORT dataa (656:656:656) (689:689:689)) - (PORT datab (745:745:745) (852:852:852)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (PORT dataa (504:504:504) (578:578:578)) + (PORT datab (1381:1381:1381) (1376:1376:1376)) + (PORT datad (316:316:316) (326:326:326)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -41237,9 +45728,86 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1505:1505:1505) (1520:1520:1520)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (1270:1270:1270) (1344:1344:1344)) + (PORT datab (912:912:912) (941:941:941)) + (PORT datac (606:606:606) (657:657:657)) + (PORT datad (645:645:645) (700:700:700)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~115) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (755:755:755)) + (PORT datab (722:722:722) (807:807:807)) + (PORT datac (1231:1231:1231) (1295:1295:1295)) + (PORT datad (1207:1207:1207) (1281:1281:1281)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~116) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (647:647:647)) + (PORT datab (754:754:754) (844:844:844)) + (PORT datac (685:685:685) (783:783:783)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~117) + (DELAY + (ABSOLUTE + (PORT datab (207:207:207) (249:249:249)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1511:1511:1511) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1538:1538:1538)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -41253,10 +45821,26 @@ (INSTANCE ula_\|zx_keyboard_\|key_row\~3) (DELAY (ABSOLUTE - (PORT datab (1510:1510:1510) (1603:1603:1603)) - (PORT datac (869:869:869) (961:961:961)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (2314:2314:2314) (2533:2533:2533)) + (PORT datab (1430:1430:1430) (1559:1559:1559)) + (PORT datad (666:666:666) (718:718:718)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~118) + (DELAY + (ABSOLUTE + (PORT dataa (298:298:298) (401:401:401)) + (PORT datab (954:954:954) (1025:1025:1025)) + (PORT datac (1000:1000:1000) (1060:1060:1060)) + (PORT datad (711:711:711) (787:787:787)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -41264,60 +45848,60 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~80) + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~131) (DELAY (ABSOLUTE - (PORT dataa (377:377:377) (453:453:453)) - (PORT datab (632:632:632) (659:659:659)) - (PORT datac (1349:1349:1349) (1408:1408:1408)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~111) - (DELAY - (ABSOLUTE - (PORT dataa (793:793:793) (903:903:903)) - (PORT datac (702:702:702) (794:794:794)) - (PORT datad (1130:1130:1130) (1214:1214:1214)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~97) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1266:1266:1266)) - (PORT datab (724:724:724) (824:824:824)) - (PORT datac (642:642:642) (670:670:670)) - (PORT datad (909:909:909) (977:977:977)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~116) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (411:411:411)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datad (183:183:183) (213:213:213)) + (PORT dataa (1064:1064:1064) (1139:1139:1139)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (259:259:259) (337:337:337)) (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~119) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (440:440:440)) + (PORT datab (631:631:631) (657:657:657)) + (PORT datad (832:832:832) (834:834:834)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~114) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (259:259:259)) + (PORT datab (653:653:653) (667:667:667)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -41328,9 +45912,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1511:1511:1511) (1525:1525:1525)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (PORT clrn (1545:1545:1545) (1538:1538:1538)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -41341,14 +45925,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~115) + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~113) (DELAY (ABSOLUTE - (PORT dataa (585:585:585) (605:605:605)) - (PORT datab (363:363:363) (394:394:394)) - (PORT datad (717:717:717) (811:811:811)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (787:787:787) (871:871:871)) + (PORT datab (612:612:612) (637:637:637)) + (PORT datad (589:589:589) (605:605:605)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -41359,9 +45943,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1508:1508:1508) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -41372,658 +45956,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~77) + (INSTANCE D\[4\]\~85) (DELAY (ABSOLUTE - (PORT dataa (1136:1136:1136) (1168:1168:1168)) - (PORT datab (1142:1142:1142) (1214:1214:1214)) - (PORT datac (639:639:639) (698:698:698)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (1616:1616:1616) (1662:1662:1662)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3349:3349:3349) (3565:3565:3565)) - (PORT d[1] (1605:1605:1605) (1743:1743:1743)) - (PORT d[2] (2398:2398:2398) (2522:2522:2522)) - (PORT d[3] (1878:1878:1878) (1993:1993:1993)) - (PORT d[4] (1904:1904:1904) (2011:2011:2011)) - (PORT d[5] (2072:2072:2072) (2262:2262:2262)) - (PORT d[6] (2267:2267:2267) (2352:2352:2352)) - (PORT d[7] (2156:2156:2156) (2268:2268:2268)) - (PORT d[8] (2927:2927:2927) (3117:3117:3117)) - (PORT d[9] (2257:2257:2257) (2323:2323:2323)) - (PORT d[10] (4015:4015:4015) (4256:4256:4256)) - (PORT d[11] (1788:1788:1788) (1883:1883:1883)) - (PORT d[12] (2324:2324:2324) (2423:2423:2423)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (2435:2435:2435) (2530:2530:2530)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1496:1496:1496) (1570:1570:1570)) - (PORT clk (1848:1848:1848) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3471:3471:3471) (3598:3598:3598)) - (PORT d[1] (1681:1681:1681) (1841:1841:1841)) - (PORT d[2] (1803:1803:1803) (1868:1868:1868)) - (PORT d[3] (2137:2137:2137) (2245:2245:2245)) - (PORT d[4] (2206:2206:2206) (2306:2306:2306)) - (PORT d[5] (1648:1648:1648) (1787:1787:1787)) - (PORT d[6] (1447:1447:1447) (1468:1468:1468)) - (PORT d[7] (1455:1455:1455) (1504:1504:1504)) - (PORT d[8] (2907:2907:2907) (3106:3106:3106)) - (PORT d[9] (2261:2261:2261) (2404:2404:2404)) - (PORT d[10] (2303:2303:2303) (2432:2432:2432)) - (PORT d[11] (2139:2139:2139) (2251:2251:2251)) - (PORT d[12] (2022:2022:2022) (2077:2077:2077)) - (PORT clk (1845:1845:1845) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2862:2862:2862) (2854:2854:2854)) - (PORT clk (1845:1845:1845) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (PORT d[0] (4272:4272:4272) (4376:4376:4376)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1803:1803:1803) (1801:1801:1801)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1739:1739:1739) (1715:1715:1715)) - (PORT clk (1813:1813:1813) (1807:1807:1807)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4403:4403:4403) (4442:4442:4442)) - (PORT d[1] (4232:4232:4232) (4305:4305:4305)) - (PORT d[2] (4291:4291:4291) (4336:4336:4336)) - (PORT d[3] (4528:4528:4528) (4564:4564:4564)) - (PORT d[4] (4637:4637:4637) (4664:4664:4664)) - (PORT d[5] (4315:4315:4315) (4358:4358:4358)) - (PORT d[6] (4706:4706:4706) (4798:4798:4798)) - (PORT d[7] (4277:4277:4277) (4349:4349:4349)) - (PORT d[8] (4511:4511:4511) (4526:4526:4526)) - (PORT d[9] (4469:4469:4469) (4738:4738:4738)) - (PORT d[10] (4368:4368:4368) (4407:4407:4407)) - (PORT d[11] (4392:4392:4392) (4374:4374:4374)) - (PORT d[12] (4337:4337:4337) (4342:4342:4342)) - (PORT clk (1809:1809:1809) (1803:1803:1803)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1813:1813:1813) (1807:1807:1807)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4186:4186:4186) (4425:4425:4425)) - (PORT d[1] (2884:2884:2884) (3131:3131:3131)) - (PORT d[2] (2708:2708:2708) (2819:2819:2819)) - (PORT d[3] (2283:2283:2283) (2458:2458:2458)) - (PORT d[4] (2517:2517:2517) (2710:2710:2710)) - (PORT d[5] (2529:2529:2529) (2722:2722:2722)) - (PORT d[6] (1890:1890:1890) (2008:2008:2008)) - (PORT d[7] (2314:2314:2314) (2443:2443:2443)) - (PORT d[8] (3115:3115:3115) (3376:3376:3376)) - (PORT d[9] (2627:2627:2627) (2762:2762:2762)) - (PORT d[10] (4822:4822:4822) (5078:5078:5078)) - (PORT d[11] (1897:1897:1897) (2050:2050:2050)) - (PORT d[12] (2209:2209:2209) (2354:2354:2354)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1882:1882:1882)) - (PORT d[0] (3638:3638:3638) (3555:3555:3555)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1555:1555:1555) (1647:1647:1647)) - (PORT clk (1849:1849:1849) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3013:3013:3013) (3193:3193:3193)) - (PORT d[1] (2314:2314:2314) (2501:2501:2501)) - (PORT d[2] (2182:2182:2182) (2293:2293:2293)) - (PORT d[3] (1900:1900:1900) (2029:2029:2029)) - (PORT d[4] (2430:2430:2430) (2538:2538:2538)) - (PORT d[5] (1950:1950:1950) (2108:2108:2108)) - (PORT d[6] (1747:1747:1747) (1762:1762:1762)) - (PORT d[7] (2376:2376:2376) (2506:2506:2506)) - (PORT d[8] (2895:2895:2895) (3077:3077:3077)) - (PORT d[9] (1983:1983:1983) (2113:2113:2113)) - (PORT d[10] (2017:2017:2017) (2125:2125:2125)) - (PORT d[11] (2437:2437:2437) (2546:2546:2546)) - (PORT d[12] (2561:2561:2561) (2626:2626:2626)) - (PORT clk (1846:1846:1846) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2577:2577:2577) (2632:2632:2632)) - (PORT clk (1846:1846:1846) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (PORT d[0] (4055:4055:4055) (3952:3952:3952)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1804:1804:1804) (1802:1802:1802)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2048:2048:2048) (2021:2021:2021)) - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4402:4402:4402) (4453:4453:4453)) - (PORT d[1] (4222:4222:4222) (4285:4285:4285)) - (PORT d[2] (4296:4296:4296) (4356:4356:4356)) - (PORT d[3] (4467:4467:4467) (4510:4510:4510)) - (PORT d[4] (4361:4361:4361) (4378:4378:4378)) - (PORT d[5] (4645:4645:4645) (4676:4676:4676)) - (PORT d[6] (4445:4445:4445) (4533:4533:4533)) - (PORT d[7] (4329:4329:4329) (4398:4398:4398)) - (PORT d[8] (4517:4517:4517) (4536:4536:4536)) - (PORT d[9] (4456:4456:4456) (4702:4702:4702)) - (PORT d[10] (4317:4317:4317) (4323:4323:4323)) - (PORT d[11] (4684:4684:4684) (4714:4714:4714)) - (PORT d[12] (4438:4438:4438) (4553:4553:4553)) - (PORT clk (1810:1810:1810) (1804:1804:1804)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1806:1806:1806) (1804:1804:1804)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1163:1163:1163) (1219:1219:1219)) - (PORT datab (947:947:947) (1002:1002:1002)) - (PORT datac (1385:1385:1385) (1418:1418:1418)) - (PORT datad (1436:1436:1436) (1475:1475:1475)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (711:711:711) (751:751:751)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datac (2427:2427:2427) (2603:2603:2603)) + (PORT datad (633:633:633) (684:684:684)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -42031,476 +45972,33 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~1) + (INSTANCE D\[4\]\~86) (DELAY (ABSOLUTE - (PORT dataa (1314:1314:1314) (1369:1369:1369)) - (PORT datab (951:951:951) (1008:1008:1008)) - (PORT datac (1440:1440:1440) (1502:1502:1502)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (592:592:592) (622:622:622)) + (PORT datab (2465:2465:2465) (2646:2646:2646)) + (PORT datac (928:928:928) (975:975:975)) + (PORT datad (597:597:597) (633:633:633)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~89) (DELAY (ABSOLUTE - (PORT d[0] (901:901:901) (939:939:939)) - (PORT clk (1851:1851:1851) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3349:3349:3349) (3527:3527:3527)) - (PORT d[1] (1734:1734:1734) (1904:1904:1904)) - (PORT d[2] (1993:1993:1993) (2068:2068:2068)) - (PORT d[3] (2163:2163:2163) (2257:2257:2257)) - (PORT d[4] (1834:1834:1834) (1918:1918:1918)) - (PORT d[5] (1363:1363:1363) (1460:1460:1460)) - (PORT d[6] (1449:1449:1449) (1474:1474:1474)) - (PORT d[7] (3354:3354:3354) (3503:3503:3503)) - (PORT d[8] (2447:2447:2447) (2653:2653:2653)) - (PORT d[9] (3517:3517:3517) (3682:3682:3682)) - (PORT d[10] (2917:2917:2917) (3102:3102:3102)) - (PORT d[11] (1485:1485:1485) (1553:1553:1553)) - (PORT d[12] (1460:1460:1460) (1502:1502:1502)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3345:3345:3345) (3355:3355:3355)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (1944:1944:1944) (1906:1906:1906)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1470:1470:1470) (1515:1515:1515)) - (PORT clk (1841:1841:1841) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3671:3671:3671) (3886:3886:3886)) - (PORT d[1] (1690:1690:1690) (1854:1854:1854)) - (PORT d[2] (3275:3275:3275) (3430:3430:3430)) - (PORT d[3] (2158:2158:2158) (2262:2262:2262)) - (PORT d[4] (2542:2542:2542) (2676:2676:2676)) - (PORT d[5] (1672:1672:1672) (1804:1804:1804)) - (PORT d[6] (1797:1797:1797) (1871:1871:1871)) - (PORT d[7] (1692:1692:1692) (1762:1762:1762)) - (PORT d[8] (3323:3323:3323) (3550:3550:3550)) - (PORT d[9] (2846:2846:2846) (2959:2959:2959)) - (PORT d[10] (3476:3476:3476) (3688:3688:3688)) - (PORT d[11] (1790:1790:1790) (1894:1894:1894)) - (PORT d[12] (1727:1727:1727) (1788:1788:1788)) - (PORT clk (1838:1838:1838) (1865:1865:1865)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1941:1941:1941) (1913:1913:1913)) - (PORT clk (1838:1838:1838) (1865:1865:1865)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1869:1869:1869)) - (PORT d[0] (2779:2779:2779) (2775:2775:2775)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1801:1801:1801) (1828:1828:1828)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (986:986:986) (991:991:991)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (987:987:987) (992:992:992)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (987:987:987) (992:992:992)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (987:987:987) (992:992:992)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1247:1247:1247) (1305:1305:1305)) - (PORT clk (1851:1851:1851) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3351:3351:3351) (3542:3542:3542)) - (PORT d[1] (1331:1331:1331) (1442:1442:1442)) - (PORT d[2] (1949:1949:1949) (2052:2052:2052)) - (PORT d[3] (1549:1549:1549) (1617:1617:1617)) - (PORT d[4] (1868:1868:1868) (1957:1957:1957)) - (PORT d[5] (1641:1641:1641) (1721:1721:1721)) - (PORT d[6] (1178:1178:1178) (1228:1228:1228)) - (PORT d[7] (1451:1451:1451) (1507:1507:1507)) - (PORT d[8] (2507:2507:2507) (2697:2697:2697)) - (PORT d[9] (3505:3505:3505) (3649:3649:3649)) - (PORT d[10] (2878:2878:2878) (3044:3044:3044)) - (PORT d[11] (1237:1237:1237) (1307:1307:1307)) - (PORT d[12] (1108:1108:1108) (1125:1125:1125)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2872:2872:2872) (2909:2909:2909)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (3248:3248:3248) (3325:3325:3325)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + (PORT dataa (1158:1158:1158) (1204:1204:1204)) + (PORT datab (1206:1206:1206) (1216:1216:1216)) + (PORT datac (3269:3269:3269) (3535:3535:3535)) + (PORT datad (596:596:596) (633:633:633)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -42509,8 +46007,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1750:1750:1750) (1835:1835:1835)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT d[0] (1025:1025:1025) (1033:1033:1033)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) ) ) (TIMINGCHECK @@ -42522,20 +46020,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3365:3365:3365) (3581:3581:3581)) - (PORT d[1] (1702:1702:1702) (1864:1864:1864)) - (PORT d[2] (2694:2694:2694) (2816:2816:2816)) - (PORT d[3] (2143:2143:2143) (2257:2257:2257)) - (PORT d[4] (2191:2191:2191) (2314:2314:2314)) - (PORT d[5] (2392:2392:2392) (2607:2607:2607)) - (PORT d[6] (2106:2106:2106) (2209:2209:2209)) - (PORT d[7] (2467:2467:2467) (2597:2597:2597)) - (PORT d[8] (3036:3036:3036) (3248:3248:3248)) - (PORT d[9] (2577:2577:2577) (2669:2669:2669)) - (PORT d[10] (3785:3785:3785) (4034:4034:4034)) - (PORT d[11] (1778:1778:1778) (1856:1856:1856)) - (PORT d[12] (2315:2315:2315) (2396:2396:2396)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) + (PORT d[0] (3329:3329:3329) (3586:3586:3586)) + (PORT d[1] (1573:1573:1573) (1649:1649:1649)) + (PORT d[2] (1037:1037:1037) (1080:1080:1080)) + (PORT d[3] (1599:1599:1599) (1696:1696:1696)) + (PORT d[4] (2959:2959:2959) (3149:3149:3149)) + (PORT d[5] (970:970:970) (999:999:999)) + (PORT d[6] (1576:1576:1576) (1694:1694:1694)) + (PORT d[7] (1281:1281:1281) (1303:1303:1303)) + (PORT d[8] (1219:1219:1219) (1280:1280:1280)) + (PORT d[9] (1098:1098:1098) (1184:1184:1184)) + (PORT d[10] (1037:1037:1037) (1112:1112:1112)) + (PORT d[11] (2217:2217:2217) (2342:2342:2342)) + (PORT d[12] (1083:1083:1083) (1173:1173:1173)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) (TIMINGCHECK @@ -42547,8 +46045,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2267:2267:2267) (2265:2265:2265)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) + (PORT d[0] (1196:1196:1196) (1145:1145:1145)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) (TIMINGCHECK @@ -42560,8 +46058,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (PORT d[0] (2685:2685:2685) (2695:2695:2695)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (2363:2363:2363) (2340:2340:2340)) ) ) ) @@ -42570,7 +46068,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -42580,7 +46078,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -42590,7 +46088,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -42600,7 +46098,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -42610,7 +46108,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1810:1810:1810) (1837:1837:1837)) + (PORT clk (1811:1811:1811) (1838:1838:1838)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -42624,7 +46122,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) + (PORT clk (996:996:996) (1001:1001:1001)) ) ) ) @@ -42633,7 +46131,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) + (PORT clk (997:997:997) (1002:1002:1002)) ) ) ) @@ -42642,7 +46140,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) + (PORT clk (997:997:997) (1002:1002:1002)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -42650,6 +46148,312 @@ (CELL (CELLTYPE "cycloneive_ram_pulse_generator") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1004:1004:1004) (1015:1015:1015)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3337:3337:3337) (3609:3609:3609)) + (PORT d[1] (1306:1306:1306) (1388:1388:1388)) + (PORT d[2] (1698:1698:1698) (1789:1789:1789)) + (PORT d[3] (1595:1595:1595) (1675:1675:1675)) + (PORT d[4] (2970:2970:2970) (3138:3138:3138)) + (PORT d[5] (1270:1270:1270) (1328:1328:1328)) + (PORT d[6] (1305:1305:1305) (1402:1402:1402)) + (PORT d[7] (1331:1331:1331) (1362:1362:1362)) + (PORT d[8] (1550:1550:1550) (1637:1637:1637)) + (PORT d[9] (1103:1103:1103) (1195:1195:1195)) + (PORT d[10] (1045:1045:1045) (1128:1128:1128)) + (PORT d[11] (2177:2177:2177) (2321:2321:2321)) + (PORT d[12] (1373:1373:1373) (1464:1464:1464)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1223:1223:1223) (1198:1198:1198)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2348:2348:2348) (2353:2353:2353)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (930:930:930) (956:956:956)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2672:2672:2672) (2905:2905:2905)) + (PORT d[1] (1536:1536:1536) (1605:1605:1605)) + (PORT d[2] (1356:1356:1356) (1434:1434:1434)) + (PORT d[3] (1321:1321:1321) (1406:1406:1406)) + (PORT d[4] (2655:2655:2655) (2825:2825:2825)) + (PORT d[5] (1588:1588:1588) (1655:1655:1655)) + (PORT d[6] (1518:1518:1518) (1625:1625:1625)) + (PORT d[7] (1580:1580:1580) (1612:1612:1612)) + (PORT d[8] (1535:1535:1535) (1634:1634:1634)) + (PORT d[9] (1648:1648:1648) (1754:1754:1754)) + (PORT d[10] (1343:1343:1343) (1445:1445:1445)) + (PORT d[11] (1880:1880:1880) (2005:2005:2005)) + (PORT d[12] (1391:1391:1391) (1503:1503:1503)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1260:1260:1260) (1255:1255:1255)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT d[0] (2386:2386:2386) (2419:2419:2419)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1001:1001:1001)) @@ -42659,46 +46463,826 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~2) + (INSTANCE D\[4\]\~93) (DELAY (ABSOLUTE - (PORT dataa (1829:1829:1829) (1854:1854:1854)) - (PORT datab (1177:1177:1177) (1181:1181:1181)) - (PORT datad (1696:1696:1696) (1748:1748:1748)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (904:904:904) (927:927:927)) + (PORT datab (1237:1237:1237) (1338:1338:1338)) + (PORT datad (912:912:912) (935:935:935)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~3) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (1465:1465:1465) (1535:1535:1535)) - (PORT datab (1484:1484:1484) (1501:1501:1501)) - (PORT datac (2124:2124:2124) (2189:2189:2189)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT d[0] (1378:1378:1378) (1455:1455:1455)) + (PORT clk (1845:1845:1845) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2978:2978:2978) (3192:3192:3192)) + (PORT d[1] (2894:2894:2894) (2985:2985:2985)) + (PORT d[2] (1003:1003:1003) (1051:1051:1051)) + (PORT d[3] (1298:1298:1298) (1337:1337:1337)) + (PORT d[4] (2072:2072:2072) (2172:2172:2172)) + (PORT d[5] (945:945:945) (991:991:991)) + (PORT d[6] (1183:1183:1183) (1217:1217:1217)) + (PORT d[7] (2655:2655:2655) (2814:2814:2814)) + (PORT d[8] (1565:1565:1565) (1650:1650:1650)) + (PORT d[9] (437:437:437) (473:473:473)) + (PORT d[10] (428:428:428) (460:460:460)) + (PORT d[11] (2780:2780:2780) (2977:2977:2977)) + (PORT d[12] (751:751:751) (792:792:792)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1248:1248:1248) (1217:1217:1217)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1873:1873:1873)) + (PORT d[0] (1747:1747:1747) (1726:1726:1726)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1805:1805:1805) (1832:1832:1832)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (990:990:990) (995:995:995)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~94) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (999:999:999)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1205:1205:1205) (1303:1303:1303)) + (PORT datad (1455:1455:1455) (1474:1474:1474)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~109) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (680:680:680) (777:777:777)) - (PORT datab (1164:1164:1164) (1255:1255:1255)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (173:173:173) (197:197:197)) + (PORT d[0] (1196:1196:1196) (1180:1180:1180)) + (PORT clk (1848:1848:1848) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3089:3089:3089) (3264:3264:3264)) + (PORT d[1] (2104:2104:2104) (2210:2210:2210)) + (PORT d[2] (1617:1617:1617) (1719:1719:1719)) + (PORT d[3] (1520:1520:1520) (1615:1615:1615)) + (PORT d[4] (2696:2696:2696) (2843:2843:2843)) + (PORT d[5] (1573:1573:1573) (1654:1654:1654)) + (PORT d[6] (1510:1510:1510) (1578:1578:1578)) + (PORT d[7] (1930:1930:1930) (1965:1965:1965)) + (PORT d[8] (3501:3501:3501) (3625:3625:3625)) + (PORT d[9] (1426:1426:1426) (1546:1546:1546)) + (PORT d[10] (1668:1668:1668) (1771:1771:1771)) + (PORT d[11] (1859:1859:1859) (1961:1961:1961)) + (PORT d[12] (1669:1669:1669) (1783:1783:1783)) + (PORT clk (1845:1845:1845) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1494:1494:1494) (1487:1487:1487)) + (PORT clk (1845:1845:1845) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (PORT d[0] (2934:2934:2934) (2899:2899:2899)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1801:1801:1801)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1828:1828:1828) (1871:1871:1871)) + (PORT clk (1813:1813:1813) (1807:1807:1807)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4466:4466:4466) (4538:4538:4538)) + (PORT d[1] (4377:4377:4377) (4452:4452:4452)) + (PORT d[2] (4406:4406:4406) (4485:4485:4485)) + (PORT d[3] (4268:4268:4268) (4360:4360:4360)) + (PORT d[4] (4331:4331:4331) (4392:4392:4392)) + (PORT d[5] (4400:4400:4400) (4521:4521:4521)) + (PORT d[6] (4441:4441:4441) (4502:4502:4502)) + (PORT d[7] (4358:4358:4358) (4460:4460:4460)) + (PORT d[8] (4443:4443:4443) (4575:4575:4575)) + (PORT d[9] (4525:4525:4525) (4647:4647:4647)) + (PORT d[10] (4496:4496:4496) (4633:4633:4633)) + (PORT d[11] (4458:4458:4458) (4561:4561:4561)) + (PORT d[12] (4363:4363:4363) (4422:4422:4422)) + (PORT clk (1809:1809:1809) (1803:1803:1803)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1813:1813:1813) (1807:1807:1807)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1805:1805:1805) (1803:1803:1803)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1223:1223:1223) (1232:1232:1232)) + (PORT clk (1849:1849:1849) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3089:3089:3089) (3264:3264:3264)) + (PORT d[1] (1541:1541:1541) (1607:1607:1607)) + (PORT d[2] (1629:1629:1629) (1719:1719:1719)) + (PORT d[3] (1525:1525:1525) (1604:1604:1604)) + (PORT d[4] (2654:2654:2654) (2816:2816:2816)) + (PORT d[5] (1569:1569:1569) (1645:1645:1645)) + (PORT d[6] (1544:1544:1544) (1658:1658:1658)) + (PORT d[7] (1663:1663:1663) (1702:1702:1702)) + (PORT d[8] (1535:1535:1535) (1635:1635:1635)) + (PORT d[9] (1398:1398:1398) (1514:1514:1514)) + (PORT d[10] (1375:1375:1375) (1487:1487:1487)) + (PORT d[11] (1846:1846:1846) (1959:1959:1959)) + (PORT d[12] (1391:1391:1391) (1504:1504:1504)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1426:1426:1426) (1391:1391:1391)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (PORT d[0] (2602:2602:2602) (2625:2625:2625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1804:1804:1804) (1802:1802:1802)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1838:1838:1838) (1888:1888:1888)) + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4461:4461:4461) (4563:4563:4563)) + (PORT d[1] (4338:4338:4338) (4416:4416:4416)) + (PORT d[2] (4451:4451:4451) (4534:4534:4534)) + (PORT d[3] (4291:4291:4291) (4385:4385:4385)) + (PORT d[4] (4329:4329:4329) (4390:4390:4390)) + (PORT d[5] (4364:4364:4364) (4463:4463:4463)) + (PORT d[6] (4404:4404:4404) (4467:4467:4467)) + (PORT d[7] (4337:4337:4337) (4441:4441:4441)) + (PORT d[8] (4412:4412:4412) (4536:4536:4536)) + (PORT d[9] (4443:4443:4443) (4552:4552:4552)) + (PORT d[10] (4533:4533:4533) (4643:4643:4643)) + (PORT d[11] (4480:4480:4480) (4587:4587:4587)) + (PORT d[12] (4342:4342:4342) (4404:4404:4404)) + (PORT clk (1810:1810:1810) (1804:1804:1804)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2135:2135:2135) (2270:2270:2270)) + (PORT d[1] (2360:2360:2360) (2503:2503:2503)) + (PORT d[2] (2439:2439:2439) (2591:2591:2591)) + (PORT d[3] (2316:2316:2316) (2447:2447:2447)) + (PORT d[4] (2038:2038:2038) (2142:2142:2142)) + (PORT d[5] (2419:2419:2419) (2559:2559:2559)) + (PORT d[6] (2470:2470:2470) (2638:2638:2638)) + (PORT d[7] (2535:2535:2535) (2601:2601:2601)) + (PORT d[8] (2536:2536:2536) (2603:2603:2603)) + (PORT d[9] (2337:2337:2337) (2521:2521:2521)) + (PORT d[10] (3019:3019:3019) (3165:3165:3165)) + (PORT d[11] (2078:2078:2078) (2172:2172:2172)) + (PORT d[12] (2284:2284:2284) (2462:2462:2462)) + (PORT clk (1860:1860:1860) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1886:1886:1886)) + (PORT d[0] (2624:2624:2624) (2721:2721:2721)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1849:1849:1849)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1012:1012:1012)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1009:1009:1009) (1013:1013:1013)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1009:1009:1009) (1013:1013:1013)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1009:1009:1009) (1013:1013:1013)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (1215:1215:1215) (1289:1289:1289)) + (PORT datab (720:720:720) (782:782:782)) + (PORT datac (933:933:933) (942:942:942)) + (PORT datad (1202:1202:1202) (1232:1232:1232)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2194:2194:2194) (2311:2311:2311)) + (PORT d[1] (2390:2390:2390) (2538:2538:2538)) + (PORT d[2] (2577:2577:2577) (2693:2693:2693)) + (PORT d[3] (3028:3028:3028) (3132:3132:3132)) + (PORT d[4] (1942:1942:1942) (2079:2079:2079)) + (PORT d[5] (3464:3464:3464) (3577:3577:3577)) + (PORT d[6] (2798:2798:2798) (2911:2911:2911)) + (PORT d[7] (3363:3363:3363) (3428:3428:3428)) + (PORT d[8] (2099:2099:2099) (2185:2185:2185)) + (PORT d[9] (3054:3054:3054) (3173:3173:3173)) + (PORT d[10] (2331:2331:2331) (2396:2396:2396)) + (PORT d[11] (2463:2463:2463) (2612:2612:2612)) + (PORT d[12] (3239:3239:3239) (3438:3438:3438)) + (PORT clk (1867:1867:1867) (1892:1892:1892)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1892:1892:1892)) + (PORT d[0] (2930:2930:2930) (2859:2859:2859)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1868:1868:1868) (1893:1893:1893)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1855:1855:1855)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1015:1015:1015) (1018:1018:1018)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1019:1019:1019)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1019:1019:1019)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1019:1019:1019)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~91) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (931:931:931)) + (PORT datab (1317:1317:1317) (1343:1343:1343)) + (PORT datac (180:180:180) (216:216:216)) + (PORT datad (1569:1569:1569) (1584:1584:1584)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -42706,32 +47290,64 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~97) + (INSTANCE D\[4\]\~92) (DELAY (ABSOLUTE - (PORT dataa (887:887:887) (916:916:916)) - (PORT datab (1551:1551:1551) (1605:1605:1605)) - (PORT datac (1462:1462:1462) (1538:1538:1538)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (975:975:975) (990:990:990)) + (PORT datab (721:721:721) (781:781:781)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (312:312:312) (330:330:330)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~98) + (INSTANCE D\[4\]\~125) (DELAY (ABSOLUTE - (PORT dataa (1168:1168:1168) (1244:1244:1244)) - (PORT datab (1665:1665:1665) (1708:1708:1708)) - (PORT datac (1463:1463:1463) (1538:1538:1538)) - (PORT datad (173:173:173) (198:198:198)) + (PORT dataa (2570:2570:2570) (2815:2815:2815)) + (PORT datab (1396:1396:1396) (1468:1468:1468)) + (PORT datac (570:570:570) (585:585:585)) + (PORT datad (318:318:318) (337:337:337)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~110) + (DELAY + (ABSOLUTE + (PORT dataa (916:916:916) (976:976:976)) + (PORT datab (920:920:920) (940:940:940)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (632:632:632) (657:657:657)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~111) + (DELAY + (ABSOLUTE + (PORT dataa (2246:2246:2246) (2318:2318:2318)) + (PORT datab (436:436:436) (473:473:473)) + (PORT datac (194:194:194) (228:228:228)) + (PORT datad (1262:1262:1262) (1331:1331:1331)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -42741,13 +47357,13 @@ (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) (DELAY (ABSOLUTE - (PORT dataa (970:970:970) (1037:1037:1037)) - (PORT datab (1506:1506:1506) (1524:1524:1524)) - (PORT datac (236:236:236) (289:289:289)) - (PORT datad (1153:1153:1153) (1165:1165:1165)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1678:1678:1678) (1784:1784:1784)) + (PORT datab (426:426:426) (465:465:465)) + (PORT datac (536:536:536) (545:545:545)) + (PORT datad (1131:1131:1131) (1161:1161:1161)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -42757,7 +47373,7 @@ (INSTANCE z80_\|data_pins_\|dout\[4\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT clk (1527:1527:1527) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) (PORT ena (841:841:841) (846:846:846)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -42773,11 +47389,11 @@ (INSTANCE z80_\|bus_control_\|db\[4\]\~18) (DELAY (ABSOLUTE - (PORT dataa (395:395:395) (471:471:471)) - (PORT datab (388:388:388) (422:422:422)) - (PORT datad (671:671:671) (693:693:693)) + (PORT dataa (264:264:264) (351:351:351)) + (PORT datab (420:420:420) (454:454:454)) + (PORT datad (386:386:386) (415:415:415)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -42787,13 +47403,13 @@ (INSTANCE z80_\|bus_control_\|db\[4\]\~19) (DELAY (ABSOLUTE - (PORT dataa (981:981:981) (1007:1007:1007)) - (PORT datab (922:922:922) (965:965:965)) - (PORT datac (888:888:888) (938:938:938)) - (PORT datad (898:898:898) (913:913:913)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1128:1128:1128) (1161:1161:1161)) + (PORT datab (335:335:335) (364:364:364)) + (PORT datac (525:525:525) (531:531:531)) + (PORT datad (218:218:218) (250:250:250)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -42803,244 +47419,10 @@ (INSTANCE z80_\|ir_\|opcode\[4\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1550:1550:1550)) - (PORT ena (1479:1479:1479) (1488:1488:1488)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~0) - (DELAY - (ABSOLUTE - (PORT datac (1440:1440:1440) (1546:1546:1546)) - (PORT datad (1464:1464:1464) (1552:1552:1552)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1381:1381:1381) (1434:1434:1434)) - (PORT datab (981:981:981) (1038:1038:1038)) - (PORT datac (1636:1636:1636) (1757:1757:1757)) - (PORT datad (1217:1217:1217) (1298:1298:1298)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1286:1286:1286) (1367:1367:1367)) - (PORT datab (1528:1528:1528) (1599:1599:1599)) - (PORT datac (821:821:821) (830:830:830)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~3) - (DELAY - (ABSOLUTE - (PORT datab (1536:1536:1536) (1647:1647:1647)) - (PORT datac (1349:1349:1349) (1441:1441:1441)) - (PORT datad (2442:2442:2442) (2633:2633:2633)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (915:915:915)) - (PORT datab (925:925:925) (953:953:953)) - (PORT datac (1717:1717:1717) (1764:1764:1764)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (455:455:455)) - (PORT datab (1184:1184:1184) (1238:1238:1238)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (360:360:360) (383:383:383)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~11) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (953:953:953)) - (PORT datab (618:618:618) (660:660:660)) - (PORT datac (888:888:888) (936:936:936)) - (PORT datad (892:892:892) (905:905:905)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~12) - (DELAY - (ABSOLUTE - (PORT dataa (2004:2004:2004) (2054:2054:2054)) - (PORT datab (1141:1141:1141) (1140:1140:1140)) - (PORT datac (850:850:850) (856:856:856)) - (PORT datad (641:641:641) (681:681:681)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~13) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (243:243:243)) - (PORT datab (596:596:596) (607:607:607)) - (PORT datac (532:532:532) (546:546:546)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1573:1573:1573) (1667:1667:1667)) - (PORT datab (881:881:881) (895:895:895)) - (PORT datac (1465:1465:1465) (1505:1505:1505)) - (PORT datad (1073:1073:1073) (1063:1063:1063)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~15) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (652:652:652)) - (PORT datab (877:877:877) (906:906:906)) - (PORT datac (864:864:864) (874:874:874)) - (PORT datad (1193:1193:1193) (1249:1249:1249)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (219:219:219) (289:289:289)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mwr) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|mwr_wr) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT asdata (567:567:567) (645:645:645)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (903:903:903) (914:914:914)) + (PORT clrn (1578:1578:1578) (1558:1558:1558)) + (PORT ena (1940:1940:1940) (1962:1962:1962)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -43052,683 +47434,200 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) + (INSTANCE z80_\|pla_decode_\|Equal32\~0) (DELAY (ABSOLUTE - (PORT dataa (870:870:870) (890:890:890)) - (PORT datab (351:351:351) (390:390:390)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT datac (1946:1946:1946) (2006:2006:2006)) + (PORT datad (2593:2593:2593) (2646:2646:2646)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~84) + (INSTANCE z80_\|pla_decode_\|Equal36\~0) (DELAY (ABSOLUTE - (PORT dataa (1754:1754:1754) (1854:1854:1854)) - (PORT datab (1594:1594:1594) (1729:1729:1729)) - (PORT datac (1191:1191:1191) (1256:1256:1256)) - (PORT datad (1224:1224:1224) (1308:1308:1308)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (890:890:890) (951:951:951)) + (PORT datab (684:684:684) (704:704:704)) + (PORT datac (2073:2073:2073) (2242:2242:2242)) + (PORT datad (1433:1433:1433) (1451:1451:1451)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (288:288:288)) + (PORT datab (911:911:911) (925:925:925)) + (PORT datac (1751:1751:1751) (1844:1844:1844)) + (PORT datad (635:635:635) (684:684:684)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (699:699:699)) + (PORT datab (388:388:388) (432:432:432)) + (PORT datac (1409:1409:1409) (1477:1477:1477)) + (PORT datad (351:351:351) (382:382:382)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2309:2309:2309) (2429:2429:2429)) + (PORT datab (1622:1622:1622) (1658:1658:1658)) + (PORT datac (1347:1347:1347) (1529:1529:1529)) + (PORT datad (1271:1271:1271) (1279:1279:1279)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) (DELAY (ABSOLUTE - (PORT d[0] (1170:1170:1170) (1220:1220:1220)) - (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT asdata (1203:1203:1203) (1245:1245:1245)) + (PORT clrn (1590:1590:1590) (1567:1567:1567)) + (PORT ena (993:993:993) (1000:1000:1000)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) (DELAY (ABSOLUTE - (PORT d[0] (4199:4199:4199) (4456:4456:4456)) - (PORT d[1] (2869:2869:2869) (3121:3121:3121)) - (PORT d[2] (3253:3253:3253) (3349:3349:3349)) - (PORT d[3] (2536:2536:2536) (2717:2717:2717)) - (PORT d[4] (2232:2232:2232) (2420:2420:2420)) - (PORT d[5] (2568:2568:2568) (2749:2749:2749)) - (PORT d[6] (1862:1862:1862) (1979:1979:1979)) - (PORT d[7] (2324:2324:2324) (2461:2461:2461)) - (PORT d[8] (3106:3106:3106) (3383:3383:3383)) - (PORT d[9] (2915:2915:2915) (3048:3048:3048)) - (PORT d[10] (4807:4807:4807) (5077:5077:5077)) - (PORT d[11] (2186:2186:2186) (2342:2342:2342)) - (PORT d[12] (2200:2200:2200) (2338:2338:2338)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1968:1968:1968) (1944:1944:1944)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1883:1883:1883)) - (PORT d[0] (2326:2326:2326) (2304:2304:2304)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1816:1816:1816) (1842:1842:1842)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1193:1193:1193) (1222:1222:1222)) - (PORT clk (1858:1858:1858) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4194:4194:4194) (4449:4449:4449)) - (PORT d[1] (2891:2891:2891) (3144:3144:3144)) - (PORT d[2] (2764:2764:2764) (2858:2858:2858)) - (PORT d[3] (2536:2536:2536) (2713:2713:2713)) - (PORT d[4] (2253:2253:2253) (2443:2443:2443)) - (PORT d[5] (2541:2541:2541) (2717:2717:2717)) - (PORT d[6] (1898:1898:1898) (2008:2008:2008)) - (PORT d[7] (2297:2297:2297) (2428:2428:2428)) - (PORT d[8] (3124:3124:3124) (3401:3401:3401)) - (PORT d[9] (2609:2609:2609) (2741:2741:2741)) - (PORT d[10] (4803:4803:4803) (5068:5068:5068)) - (PORT d[11] (1891:1891:1891) (2036:2036:2036)) - (PORT d[12] (2208:2208:2208) (2353:2353:2353)) - (PORT clk (1855:1855:1855) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2383:2383:2383) (2365:2365:2365)) - (PORT clk (1855:1855:1855) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (PORT d[0] (2857:2857:2857) (2839:2839:2839)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1843:1843:1843)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (880:880:880) (918:918:918)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1334:1334:1334) (1380:1380:1380)) - (PORT d[1] (2044:2044:2044) (2248:2248:2248)) - (PORT d[2] (3016:3016:3016) (3126:3126:3126)) - (PORT d[3] (2584:2584:2584) (2783:2783:2783)) - (PORT d[4] (2569:2569:2569) (2761:2761:2761)) - (PORT d[5] (2836:2836:2836) (3029:3029:3029)) - (PORT d[6] (1949:1949:1949) (2075:2075:2075)) - (PORT d[7] (2609:2609:2609) (2760:2760:2760)) - (PORT d[8] (3388:3388:3388) (3680:3680:3680)) - (PORT d[9] (2935:2935:2935) (3067:3067:3067)) - (PORT d[10] (5109:5109:5109) (5374:5374:5374)) - (PORT d[11] (1927:1927:1927) (2066:2066:2066)) - (PORT d[12] (1910:1910:1910) (2033:2033:2033)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1228:1228:1228) (1223:1223:1223)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1879:1879:1879)) - (PORT d[0] (2528:2528:2528) (2496:2496:2496)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + (PORT dataa (685:685:685) (746:746:746)) + (PORT datab (925:925:925) (959:959:959)) + (PORT datac (1056:1056:1056) (1099:1099:1099)) + (PORT datad (1179:1179:1179) (1228:1228:1228)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~6) + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) (DELAY (ABSOLUTE - (PORT dataa (1430:1430:1430) (1510:1510:1510)) - (PORT datab (977:977:977) (1037:1037:1037)) - (PORT datac (1084:1084:1084) (1106:1106:1106)) - (PORT datad (833:833:833) (863:863:863)) + (PORT dataa (846:846:846) (868:868:868)) + (PORT datab (1152:1152:1152) (1165:1165:1165)) + (PORT datac (1037:1037:1037) (1033:1033:1033)) + (PORT datad (823:823:823) (844:844:844)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_yf) (DELAY (ABSOLUTE - (PORT d[0] (1183:1183:1183) (1216:1216:1216)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~15) (DELAY (ABSOLUTE - (PORT d[0] (3355:3355:3355) (3572:3572:3572)) - (PORT d[1] (1697:1697:1697) (1865:1865:1865)) - (PORT d[2] (2991:2991:2991) (3133:3133:3133)) - (PORT d[3] (2197:2197:2197) (2290:2290:2290)) - (PORT d[4] (2502:2502:2502) (2653:2653:2653)) - (PORT d[5] (2405:2405:2405) (2601:2601:2601)) - (PORT d[6] (2102:2102:2102) (2200:2200:2200)) - (PORT d[7] (2478:2478:2478) (2588:2588:2588)) - (PORT d[8] (3018:3018:3018) (3244:3244:3244)) - (PORT d[9] (2534:2534:2534) (2624:2624:2624)) - (PORT d[10] (3776:3776:3776) (4011:4011:4011)) - (PORT d[11] (1726:1726:1726) (1804:1804:1804)) - (PORT d[12] (2323:2323:2323) (2409:2409:2409)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2206:2206:2206) (2199:2199:2199)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (PORT d[0] (2749:2749:2749) (2715:2715:2715)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1809:1809:1809) (1835:1835:1835)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + (PORT dataa (604:604:604) (648:648:648)) + (PORT datab (1173:1173:1173) (1220:1220:1220)) + (PORT datac (656:656:656) (717:717:717)) + (PORT datad (590:590:590) (621:621:621)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) + (INSTANCE z80_\|alu_control_\|db\[5\]\~16) (DELAY (ABSOLUTE - (PORT dataa (1449:1449:1449) (1499:1499:1499)) - (PORT datab (1154:1154:1154) (1180:1180:1180)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1425:1425:1425) (1425:1425:1425)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (843:843:843) (895:895:895)) + (PORT datab (619:619:619) (657:657:657)) + (PORT datac (1400:1400:1400) (1464:1464:1464)) + (PORT datad (616:616:616) (628:628:628)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (248:248:248)) + (PORT datab (1116:1116:1116) (1138:1138:1138)) + (PORT datac (843:843:843) (863:863:863)) + (PORT datad (202:202:202) (229:229:229)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1785:1785:1785) (1834:1834:1834)) + (PORT d[0] (1475:1475:1475) (1500:1500:1500)) (PORT clk (1844:1844:1844) (1873:1873:1873)) ) ) @@ -43738,22 +47637,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3330:3330:3330) (3510:3510:3510)) - (PORT d[1] (2345:2345:2345) (2548:2548:2548)) - (PORT d[2] (2224:2224:2224) (2307:2307:2307)) - (PORT d[3] (1895:1895:1895) (2026:2026:2026)) - (PORT d[4] (2445:2445:2445) (2553:2553:2553)) - (PORT d[5] (1968:1968:1968) (2118:2118:2118)) - (PORT d[6] (1422:1422:1422) (1463:1463:1463)) - (PORT d[7] (1469:1469:1469) (1501:1501:1501)) - (PORT d[8] (2903:2903:2903) (3100:3100:3100)) - (PORT d[9] (1984:1984:1984) (2114:2114:2114)) - (PORT d[10] (1991:1991:1991) (2095:2095:2095)) - (PORT d[11] (1441:1441:1441) (1479:1479:1479)) - (PORT d[12] (2020:2020:2020) (2065:2065:2065)) + (PORT d[0] (3077:3077:3077) (3235:3235:3235)) + (PORT d[1] (1841:1841:1841) (1953:1953:1953)) + (PORT d[2] (1661:1661:1661) (1762:1762:1762)) + (PORT d[3] (2157:2157:2157) (2296:2296:2296)) + (PORT d[4] (2379:2379:2379) (2508:2508:2508)) + (PORT d[5] (2076:2076:2076) (2143:2143:2143)) + (PORT d[6] (1866:1866:1866) (1988:1988:1988)) + (PORT d[7] (1974:1974:1974) (2008:2008:2008)) + (PORT d[8] (3446:3446:3446) (3559:3559:3559)) + (PORT d[9] (1737:1737:1737) (1876:1876:1876)) + (PORT d[10] (3876:3876:3876) (4076:4076:4076)) + (PORT d[11] (2655:2655:2655) (2799:2799:2799)) + (PORT d[12] (2471:2471:2471) (2621:2621:2621)) (PORT clk (1841:1841:1841) (1869:1869:1869)) ) ) @@ -43763,10 +47662,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2835:2835:2835) (2823:2823:2823)) + (PORT d[0] (2338:2338:2338) (2292:2292:2292)) (PORT clk (1841:1841:1841) (1869:1869:1869)) ) ) @@ -43776,17 +47675,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1844:1844:1844) (1873:1873:1873)) - (PORT d[0] (3960:3960:3960) (4062:4062:4062)) + (PORT d[0] (2885:2885:2885) (2929:2929:2929)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1845:1845:1845) (1874:1874:1874)) @@ -43796,7 +47695,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1845:1845:1845) (1874:1874:1874)) @@ -43806,7 +47705,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1845:1845:1845) (1874:1874:1874)) @@ -43816,7 +47715,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1845:1845:1845) (1874:1874:1874)) @@ -43826,7 +47725,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1799:1799:1799) (1798:1798:1798)) @@ -43840,10 +47739,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1198:1198:1198) (1181:1181:1181)) + (PORT d[0] (1821:1821:1821) (1865:1865:1865)) (PORT clk (1809:1809:1809) (1804:1804:1804)) ) ) @@ -43853,22 +47752,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4418:4418:4418) (4468:4468:4468)) - (PORT d[1] (4222:4222:4222) (4280:4280:4280)) - (PORT d[2] (4287:4287:4287) (4334:4334:4334)) - (PORT d[3] (4530:4530:4530) (4580:4580:4580)) - (PORT d[4] (4340:4340:4340) (4354:4354:4354)) - (PORT d[5] (4359:4359:4359) (4381:4381:4381)) - (PORT d[6] (4659:4659:4659) (4748:4748:4748)) - (PORT d[7] (4373:4373:4373) (4445:4445:4445)) - (PORT d[8] (4529:4529:4529) (4546:4546:4546)) - (PORT d[9] (4710:4710:4710) (4968:4968:4968)) - (PORT d[10] (4380:4380:4380) (4418:4418:4418)) - (PORT d[11] (4364:4364:4364) (4385:4385:4385)) - (PORT d[12] (4681:4681:4681) (4658:4658:4658)) + (PORT d[0] (4361:4361:4361) (4440:4440:4440)) + (PORT d[1] (4289:4289:4289) (4412:4412:4412)) + (PORT d[2] (4396:4396:4396) (4476:4476:4476)) + (PORT d[3] (4255:4255:4255) (4328:4328:4328)) + (PORT d[4] (4433:4433:4433) (4506:4506:4506)) + (PORT d[5] (4377:4377:4377) (4495:4495:4495)) + (PORT d[6] (4340:4340:4340) (4393:4393:4393)) + (PORT d[7] (4339:4339:4339) (4447:4447:4447)) + (PORT d[8] (4420:4420:4420) (4484:4484:4484)) + (PORT d[9] (4471:4471:4471) (4559:4559:4559)) + (PORT d[10] (4423:4423:4423) (4538:4538:4538)) + (PORT d[11] (4470:4470:4470) (4589:4589:4589)) + (PORT d[12] (4307:4307:4307) (4348:4348:4348)) (PORT clk (1805:1805:1805) (1800:1800:1800)) ) ) @@ -43878,7 +47777,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1809:1809:1809) (1804:1804:1804)) @@ -43887,7 +47786,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) (DELAY (ABSOLUTE (PORT clk (1810:1810:1810) (1805:1805:1805)) @@ -43897,7 +47796,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1810:1810:1810) (1805:1805:1805)) @@ -43906,7 +47805,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1810:1810:1810) (1805:1805:1805)) @@ -43916,7 +47815,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1810:1810:1810) (1805:1805:1805)) @@ -43926,23 +47825,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2604:2604:2604) (2682:2682:2682)) - (PORT d[1] (2063:2063:2063) (2283:2283:2283)) - (PORT d[2] (2289:2289:2289) (2441:2441:2441)) - (PORT d[3] (2285:2285:2285) (2377:2377:2377)) - (PORT d[4] (2950:2950:2950) (3220:3220:3220)) - (PORT d[5] (2075:2075:2075) (2260:2260:2260)) - (PORT d[6] (1854:1854:1854) (1963:1963:1963)) - (PORT d[7] (2555:2555:2555) (2658:2658:2658)) - (PORT d[8] (2752:2752:2752) (3006:3006:3006)) - (PORT d[9] (1553:1553:1553) (1673:1673:1673)) - (PORT d[10] (1845:1845:1845) (1962:1962:1962)) - (PORT d[11] (2882:2882:2882) (3002:3002:3002)) - (PORT d[12] (1537:1537:1537) (1640:1640:1640)) - (PORT clk (1867:1867:1867) (1892:1892:1892)) + (PORT d[0] (1663:1663:1663) (1779:1779:1779)) + (PORT d[1] (2732:2732:2732) (2838:2838:2838)) + (PORT d[2] (2573:2573:2573) (2708:2708:2708)) + (PORT d[3] (2470:2470:2470) (2584:2584:2584)) + (PORT d[4] (2444:2444:2444) (2531:2531:2531)) + (PORT d[5] (2902:2902:2902) (3012:3012:3012)) + (PORT d[6] (2795:2795:2795) (2926:2926:2926)) + (PORT d[7] (3199:3199:3199) (3295:3295:3295)) + (PORT d[8] (2328:2328:2328) (2401:2401:2401)) + (PORT d[9] (3071:3071:3071) (3209:3209:3209)) + (PORT d[10] (2336:2336:2336) (2406:2406:2406)) + (PORT d[11] (2497:2497:2497) (2660:2660:2660)) + (PORT d[12] (2947:2947:2947) (3126:3126:3126)) + (PORT clk (1869:1869:1869) (1894:1894:1894)) ) ) (TIMINGCHECK @@ -43951,30 +47850,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1867:1867:1867) (1892:1892:1892)) - (PORT d[0] (2184:2184:2184) (2245:2245:2245)) + (PORT clk (1869:1869:1869) (1894:1894:1894)) + (PORT d[0] (2872:2872:2872) (2960:2960:2960)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1868:1868:1868) (1893:1893:1893)) + (PORT clk (1870:1870:1870) (1895:1895:1895)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1830:1830:1830) (1855:1855:1855)) + (PORT clk (1832:1832:1832) (1857:1857:1857)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -43985,60 +47884,418 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1015:1015:1015) (1018:1018:1018)) + (PORT clk (1017:1017:1017) (1020:1020:1020)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1016:1016:1016) (1019:1019:1019)) + (PORT clk (1018:1018:1018) (1021:1021:1021)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1016:1016:1016) (1019:1019:1019)) + (PORT clk (1018:1018:1018) (1021:1021:1021)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1016:1016:1016) (1019:1019:1019)) + (PORT clk (1018:1018:1018) (1021:1021:1021)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3543:3543:3543) (3733:3733:3733)) - (PORT d[1] (1715:1715:1715) (1880:1880:1880)) - (PORT d[2] (2685:2685:2685) (2807:2807:2807)) - (PORT d[3] (2133:2133:2133) (2228:2228:2228)) - (PORT d[4] (1902:1902:1902) (2026:2026:2026)) - (PORT d[5] (2379:2379:2379) (2573:2573:2573)) - (PORT d[6] (2329:2329:2329) (2418:2418:2418)) - (PORT d[7] (2458:2458:2458) (2570:2570:2570)) - (PORT d[8] (2691:2691:2691) (2888:2888:2888)) - (PORT d[9] (2519:2519:2519) (2590:2590:2590)) - (PORT d[10] (3815:3815:3815) (4071:4071:4071)) - (PORT d[11] (1813:1813:1813) (1894:1894:1894)) - (PORT d[12] (2372:2372:2372) (2459:2459:2459)) + (PORT d[0] (1398:1398:1398) (1419:1419:1419)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1941:1941:1941) (2052:2052:2052)) + (PORT d[1] (3029:3029:3029) (3163:3163:3163)) + (PORT d[2] (1746:1746:1746) (1840:1840:1840)) + (PORT d[3] (3627:3627:3627) (3762:3762:3762)) + (PORT d[4] (2618:2618:2618) (2777:2777:2777)) + (PORT d[5] (4105:4105:4105) (4233:4233:4233)) + (PORT d[6] (2302:2302:2302) (2398:2398:2398)) + (PORT d[7] (3712:3712:3712) (3787:3787:3787)) + (PORT d[8] (1894:1894:1894) (1995:1995:1995)) + (PORT d[9] (2469:2469:2469) (2541:2541:2541)) + (PORT d[10] (2650:2650:2650) (2739:2739:2739)) + (PORT d[11] (2800:2800:2800) (3007:3007:3007)) + (PORT d[12] (4296:4296:4296) (4557:4557:4557)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3119:3119:3119) (3165:3165:3165)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (PORT d[0] (3232:3232:3232) (3186:3186:3186)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1808:1808:1808) (1806:1806:1806)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2181:2181:2181) (2164:2164:2164)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4392:4392:4392) (4469:4469:4469)) + (PORT d[1] (4472:4472:4472) (4532:4532:4532)) + (PORT d[2] (4387:4387:4387) (4471:4471:4471)) + (PORT d[3] (4388:4388:4388) (4400:4400:4400)) + (PORT d[4] (4258:4258:4258) (4352:4352:4352)) + (PORT d[5] (4349:4349:4349) (4405:4405:4405)) + (PORT d[6] (4400:4400:4400) (4441:4441:4441)) + (PORT d[7] (4176:4176:4176) (4227:4227:4227)) + (PORT d[8] (4465:4465:4465) (4525:4525:4525)) + (PORT d[9] (4604:4604:4604) (4650:4650:4650)) + (PORT d[10] (4270:4270:4270) (4329:4329:4329)) + (PORT d[11] (4396:4396:4396) (4516:4516:4516)) + (PORT d[12] (4242:4242:4242) (4248:4248:4248)) + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1808:1808:1808)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1707:1707:1707) (1838:1838:1838)) + (PORT d[1] (1389:1389:1389) (1409:1409:1409)) + (PORT d[2] (2239:2239:2239) (2416:2416:2416)) + (PORT d[3] (1717:1717:1717) (1771:1771:1771)) + (PORT d[4] (2431:2431:2431) (2579:2579:2579)) + (PORT d[5] (2815:2815:2815) (2865:2865:2865)) + (PORT d[6] (1980:1980:1980) (2073:2073:2073)) + (PORT d[7] (1698:1698:1698) (1754:1754:1754)) + (PORT d[8] (2198:2198:2198) (2300:2300:2300)) + (PORT d[9] (1738:1738:1738) (1793:1793:1793)) + (PORT d[10] (2522:2522:2522) (2606:2606:2606)) + (PORT d[11] (4027:4027:4027) (4320:4320:4320)) + (PORT d[12] (1372:1372:1372) (1411:1411:1411)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1877:1877:1877)) + (PORT d[0] (2104:2104:2104) (2139:2139:2139)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1840:1840:1840)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (999:999:999) (1003:1003:1003)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1215:1215:1215) (1290:1290:1290)) + (PORT datab (725:725:725) (787:787:787)) + (PORT datac (1356:1356:1356) (1394:1394:1394)) + (PORT datad (1654:1654:1654) (1694:1694:1694)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1212:1212:1212) (1241:1241:1241)) + (PORT datab (720:720:720) (781:781:781)) + (PORT datac (1876:1876:1876) (1912:1912:1912)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1300:1300:1300) (1346:1346:1346)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2285:2285:2285) (2467:2467:2467)) + (PORT d[1] (2246:2246:2246) (2325:2325:2325)) + (PORT d[2] (1845:1845:1845) (1951:1951:1951)) + (PORT d[3] (2514:2514:2514) (2600:2600:2600)) + (PORT d[4] (2048:2048:2048) (2130:2130:2130)) + (PORT d[5] (1563:1563:1563) (1637:1637:1637)) + (PORT d[6] (1751:1751:1751) (1801:1801:1801)) + (PORT d[7] (2365:2365:2365) (2488:2488:2488)) + (PORT d[8] (2486:2486:2486) (2660:2660:2660)) + (PORT d[9] (1246:1246:1246) (1313:1313:1313)) + (PORT d[10] (1642:1642:1642) (1713:1713:1713)) + (PORT d[11] (1161:1161:1161) (1207:1207:1207)) + (PORT d[12] (1023:1023:1023) (1096:1096:1096)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -44048,27 +48305,70 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) (DELAY (ABSOLUTE + (PORT d[0] (1539:1539:1539) (1561:1561:1561)) (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (2529:2529:2529) (2434:2434:2434)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (2040:2040:2040) (2017:2017:2017)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1811:1811:1811) (1838:1838:1838)) @@ -44082,7 +48382,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1001:1001:1001)) @@ -44091,7 +48391,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1002:1002:1002)) @@ -44100,7 +48400,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1002:1002:1002)) @@ -44110,7 +48410,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1002:1002:1002)) @@ -44120,10 +48420,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1649:1649:1649) (1736:1736:1736)) + (PORT d[0] (1174:1174:1174) (1169:1169:1169)) (PORT clk (1860:1860:1860) (1888:1888:1888)) ) ) @@ -44133,22 +48433,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2915:2915:2915) (3030:3030:3030)) - (PORT d[1] (2366:2366:2366) (2611:2611:2611)) - (PORT d[2] (2597:2597:2597) (2777:2777:2777)) - (PORT d[3] (2017:2017:2017) (2075:2075:2075)) - (PORT d[4] (2919:2919:2919) (3173:3173:3173)) - (PORT d[5] (2370:2370:2370) (2578:2578:2578)) - (PORT d[6] (1866:1866:1866) (1962:1962:1962)) - (PORT d[7] (1642:1642:1642) (1751:1751:1751)) - (PORT d[8] (3027:3027:3027) (3282:3282:3282)) - (PORT d[9] (1219:1219:1219) (1304:1304:1304)) - (PORT d[10] (2155:2155:2155) (2296:2296:2296)) - (PORT d[11] (3694:3694:3694) (3833:3833:3833)) - (PORT d[12] (1894:1894:1894) (1995:1995:1995)) + (PORT d[0] (2884:2884:2884) (3084:3084:3084)) + (PORT d[1] (3296:3296:3296) (3485:3485:3485)) + (PORT d[2] (1967:1967:1967) (2035:2035:2035)) + (PORT d[3] (3971:3971:3971) (4151:4151:4151)) + (PORT d[4] (2885:2885:2885) (3085:3085:3085)) + (PORT d[5] (4454:4454:4454) (4597:4597:4597)) + (PORT d[6] (2220:2220:2220) (2291:2291:2291)) + (PORT d[7] (1721:1721:1721) (1766:1766:1766)) + (PORT d[8] (3141:3141:3141) (3324:3324:3324)) + (PORT d[9] (1847:1847:1847) (1916:1916:1916)) + (PORT d[10] (2061:2061:2061) (2130:2130:2130)) + (PORT d[11] (3118:3118:3118) (3322:3322:3322)) + (PORT d[12] (4307:4307:4307) (4577:4577:4577)) (PORT clk (1857:1857:1857) (1884:1884:1884)) ) ) @@ -44158,10 +48458,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2802:2802:2802) (2787:2787:2787)) + (PORT d[0] (1635:1635:1635) (1573:1573:1573)) (PORT clk (1857:1857:1857) (1884:1884:1884)) ) ) @@ -44171,17 +48471,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1860:1860:1860) (1888:1888:1888)) - (PORT d[0] (3138:3138:3138) (3102:3102:3102)) + (PORT d[0] (2528:2528:2528) (2508:2508:2508)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1861:1861:1861) (1889:1889:1889)) @@ -44191,7 +48491,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1861:1861:1861) (1889:1889:1889)) @@ -44201,7 +48501,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1861:1861:1861) (1889:1889:1889)) @@ -44211,7 +48511,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1861:1861:1861) (1889:1889:1889)) @@ -44221,2180 +48521,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1813:1813:1813)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2176:2176:2176) (2231:2231:2231)) - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4610:4610:4610) (4658:4658:4658)) - (PORT d[1] (4157:4157:4157) (4160:4160:4160)) - (PORT d[2] (4196:4196:4196) (4284:4284:4284)) - (PORT d[3] (4718:4718:4718) (4716:4716:4716)) - (PORT d[4] (4356:4356:4356) (4386:4386:4386)) - (PORT d[5] (4428:4428:4428) (4381:4381:4381)) - (PORT d[6] (4640:4640:4640) (4703:4703:4703)) - (PORT d[7] (4181:4181:4181) (4140:4140:4140)) - (PORT d[8] (4708:4708:4708) (4720:4720:4720)) - (PORT d[9] (4594:4594:4594) (4806:4806:4806)) - (PORT d[10] (4407:4407:4407) (4422:4422:4422)) - (PORT d[11] (4504:4504:4504) (4555:4555:4555)) - (PORT d[12] (4480:4480:4480) (4497:4497:4497)) - (PORT clk (1821:1821:1821) (1815:1815:1815)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1817:1817:1817) (1815:1815:1815)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1424:1424:1424) (1496:1496:1496)) - (PORT datab (973:973:973) (1052:1052:1052)) - (PORT datac (1431:1431:1431) (1467:1467:1467)) - (PORT datad (1389:1389:1389) (1443:1443:1443)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1500:1500:1500) (1615:1615:1615)) - (PORT datab (972:972:972) (1051:1051:1051)) - (PORT datac (1456:1456:1456) (1510:1510:1510)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~112) - (DELAY - (ABSOLUTE - (PORT dataa (1480:1480:1480) (1579:1579:1579)) - (PORT datab (1206:1206:1206) (1296:1296:1296)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~94) - (DELAY - (ABSOLUTE - (PORT dataa (1382:1382:1382) (1396:1396:1396)) - (PORT datab (885:885:885) (963:963:963)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1346:1346:1346) (1371:1371:1371)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~102) - (DELAY - (ABSOLUTE - (PORT datac (191:191:191) (224:224:224)) - (PORT datad (781:781:781) (792:792:792)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) - (DELAY - (ABSOLUTE - (PORT dataa (968:968:968) (1025:1025:1025)) - (PORT datab (229:229:229) (272:272:272)) - (PORT datac (239:239:239) (287:287:287)) - (PORT datad (858:858:858) (899:899:899)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (1164:1164:1164) (1192:1192:1192)) - (PORT datac (942:942:942) (1003:1003:1003)) - (PORT datad (367:367:367) (390:390:390)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (267:267:267) (355:355:355)) - (PORT datab (711:711:711) (731:731:731)) - (PORT datac (879:879:879) (883:883:883)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1535:1535:1535)) - (PORT asdata (546:546:546) (581:581:581)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1501:1501:1501) (1488:1488:1488)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~0) - (DELAY - (ABSOLUTE - (PORT dataa (711:711:711) (814:814:814)) - (PORT datab (1235:1235:1235) (1355:1355:1355)) - (PORT datac (985:985:985) (1064:1064:1064)) - (PORT datad (1322:1322:1322) (1437:1437:1437)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (690:690:690) (756:756:756)) - (PORT datab (994:994:994) (1104:1104:1104)) - (PORT datac (1148:1148:1148) (1191:1191:1191)) - (PORT datad (1194:1194:1194) (1254:1254:1254)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (717:717:717) (780:780:780)) - (PORT datab (376:376:376) (417:417:417)) - (PORT datac (1100:1100:1100) (1123:1123:1123)) - (PORT datad (1740:1740:1740) (1811:1811:1811)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (999:999:999) (1037:1037:1037)) - (PORT datab (1148:1148:1148) (1181:1181:1181)) - (PORT datac (1118:1118:1118) (1156:1156:1156)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1747:1747:1747) (1768:1768:1768)) - (PORT datab (1063:1063:1063) (1181:1181:1181)) - (PORT datac (1205:1205:1205) (1277:1277:1277)) - (PORT datad (1152:1152:1152) (1188:1188:1188)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1745:1745:1745) (1764:1764:1764)) - (PORT datab (372:372:372) (420:420:420)) - (PORT datac (1499:1499:1499) (1632:1632:1632)) - (PORT datad (1111:1111:1111) (1140:1140:1140)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (232:232:232) (279:279:279)) - (PORT datab (1037:1037:1037) (1088:1088:1088)) - (PORT datac (1095:1095:1095) (1134:1134:1134)) - (PORT datad (1073:1073:1073) (1110:1110:1110)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (880:880:880) (904:904:904)) - (PORT datab (1509:1509:1509) (1569:1569:1569)) - (PORT datac (829:829:829) (848:848:848)) - (PORT datad (860:860:860) (875:875:875)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~50) - (DELAY - (ABSOLUTE - (PORT datac (1078:1078:1078) (1174:1174:1174)) - (PORT datad (1031:1031:1031) (1116:1116:1116)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (403:403:403) (436:436:436)) - (PORT datab (968:968:968) (1056:1056:1056)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (280:280:280)) - (PORT datab (775:775:775) (874:874:874)) - (PORT datac (1366:1366:1366) (1453:1453:1453)) - (PORT datad (1546:1546:1546) (1637:1637:1637)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (379:379:379)) - (PORT datab (222:222:222) (260:260:260)) - (PORT datad (739:739:739) (824:824:824)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (2308:2308:2308) (2488:2488:2488)) - (PORT datab (241:241:241) (322:322:322)) - (PORT datac (574:574:574) (621:621:621)) - (PORT datad (1325:1325:1325) (1345:1345:1345)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~57) - (DELAY - (ABSOLUTE - (PORT datab (965:965:965) (1048:1048:1048)) - (PORT datad (728:728:728) (839:839:839)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (622:622:622) (672:672:672)) - (PORT datad (961:961:961) (1040:1040:1040)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (489:489:489) (568:568:568)) - (PORT datab (664:664:664) (740:740:740)) - (PORT datac (606:606:606) (671:671:671)) - (PORT datad (721:721:721) (799:799:799)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~131) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (538:538:538)) - (PORT datab (342:342:342) (377:377:377)) - (PORT datad (260:260:260) (338:338:338)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (908:908:908)) - (PORT datab (1091:1091:1091) (1095:1095:1095)) - (PORT datad (617:617:617) (636:636:636)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1224:1224:1224)) - (PORT datab (240:240:240) (321:321:321)) - (PORT datac (568:568:568) (626:626:626)) - (PORT datad (553:553:553) (572:572:572)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~53) - (DELAY - (ABSOLUTE - (PORT datac (1077:1077:1077) (1170:1170:1170)) - (PORT datad (1031:1031:1031) (1112:1112:1112)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (227:227:227) (285:285:285)) - (PORT datab (390:390:390) (410:410:410)) - (PORT datac (918:918:918) (988:988:988)) - (PORT datad (328:328:328) (348:348:348)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~56) - (DELAY - (ABSOLUTE - (PORT datab (969:969:969) (1059:1059:1059)) - (PORT datad (338:338:338) (357:357:357)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (406:406:406) (439:439:439)) - (PORT datab (969:969:969) (1059:1059:1059)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (330:330:330)) - (PORT datab (242:242:242) (324:324:324)) - (PORT datac (559:559:559) (587:587:587)) - (PORT datad (556:556:556) (572:572:572)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (963:963:963) (1040:1040:1040)) - (PORT datab (793:793:793) (911:911:911)) - (PORT datac (907:907:907) (1000:1000:1000)) - (PORT datad (764:764:764) (871:871:871)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (395:395:395)) - (PORT datab (737:737:737) (825:825:825)) - (PORT datad (589:589:589) (600:600:600)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (213:213:213) (262:262:262)) - (PORT datab (201:201:201) (241:241:241)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) - (DELAY - (ABSOLUTE - (PORT datac (244:244:244) (324:324:324)) - (PORT datad (831:831:831) (879:879:879)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (764:764:764)) - (PORT datab (349:349:349) (382:382:382)) - (PORT datac (658:658:658) (727:727:727)) - (PORT datad (638:638:638) (705:705:705)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (257:257:257)) - (PORT datab (471:471:471) (546:546:546)) - (PORT datac (352:352:352) (381:381:381)) - (PORT datad (197:197:197) (232:232:232)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (734:734:734) (824:824:824)) - (PORT datab (493:493:493) (577:577:577)) - (PORT datac (572:572:572) (608:608:608)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (747:747:747) (849:849:849)) - (PORT datab (773:773:773) (872:872:872)) - (PORT datad (959:959:959) (1036:1036:1036)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (370:370:370)) - (PORT datad (635:635:635) (675:675:675)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1664:1664:1664) (1689:1689:1689)) - (PORT datab (618:618:618) (678:678:678)) - (PORT datac (1058:1058:1058) (1128:1128:1128)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (634:634:634) (655:655:655)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (589:589:589) (603:603:603)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~104) - (DELAY - (ABSOLUTE - (PORT datab (1233:1233:1233) (1299:1299:1299)) - (PORT datac (655:655:655) (738:738:738)) - (PORT datad (1395:1395:1395) (1412:1412:1412)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (947:947:947) (974:974:974)) - (PORT clk (1850:1850:1850) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1333:1333:1333) (1379:1379:1379)) - (PORT d[1] (1965:1965:1965) (2168:2168:2168)) - (PORT d[2] (3064:3064:3064) (3182:3182:3182)) - (PORT d[3] (2837:2837:2837) (3038:3038:3038)) - (PORT d[4] (2548:2548:2548) (2738:2738:2738)) - (PORT d[5] (2841:2841:2841) (3039:3039:3039)) - (PORT d[6] (1923:1923:1923) (2045:2045:2045)) - (PORT d[7] (2590:2590:2590) (2742:2742:2742)) - (PORT d[8] (3415:3415:3415) (3712:3712:3712)) - (PORT d[9] (1607:1607:1607) (1686:1686:1686)) - (PORT d[10] (5088:5088:5088) (5355:5355:5355)) - (PORT d[11] (1909:1909:1909) (2057:2057:2057)) - (PORT d[12] (1909:1909:1909) (2032:2032:2032)) - (PORT clk (1847:1847:1847) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1221:1221:1221) (1217:1217:1217)) - (PORT clk (1847:1847:1847) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (PORT d[0] (2517:2517:2517) (2474:2474:2474)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1836:1836:1836)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1000:1000:1000)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1000:1000:1000)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (704:704:704) (727:727:727)) - (PORT clk (1858:1858:1858) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1274:1274:1274) (1301:1301:1301)) - (PORT d[1] (2099:2099:2099) (2330:2330:2330)) - (PORT d[2] (1248:1248:1248) (1286:1286:1286)) - (PORT d[3] (1307:1307:1307) (1357:1357:1357)) - (PORT d[4] (2610:2610:2610) (2833:2833:2833)) - (PORT d[5] (3471:3471:3471) (3676:3676:3676)) - (PORT d[6] (1323:1323:1323) (1420:1420:1420)) - (PORT d[7] (2887:2887:2887) (3061:3061:3061)) - (PORT d[8] (985:985:985) (1023:1023:1023)) - (PORT d[9] (1296:1296:1296) (1359:1359:1359)) - (PORT d[10] (1357:1357:1357) (1455:1455:1455)) - (PORT d[11] (2476:2476:2476) (2609:2609:2609)) - (PORT d[12] (1610:1610:1610) (1711:1711:1711)) - (PORT clk (1855:1855:1855) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (979:979:979) (953:953:953)) - (PORT clk (1855:1855:1855) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (PORT d[0] (1492:1492:1492) (1460:1460:1460)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1843:1843:1843)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (947:947:947) (973:973:973)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1343:1343:1343) (1413:1413:1413)) - (PORT d[1] (3163:3163:3163) (3436:3436:3436)) - (PORT d[2] (3532:3532:3532) (3625:3625:3625)) - (PORT d[3] (2837:2837:2837) (3043:3043:3043)) - (PORT d[4] (2558:2558:2558) (2781:2781:2781)) - (PORT d[5] (2869:2869:2869) (3072:3072:3072)) - (PORT d[6] (1676:1676:1676) (1759:1759:1759)) - (PORT d[7] (1505:1505:1505) (1586:1586:1586)) - (PORT d[8] (3442:3442:3442) (3720:3720:3720)) - (PORT d[9] (3231:3231:3231) (3382:3382:3382)) - (PORT d[10] (5089:5089:5089) (5374:5374:5374)) - (PORT d[11] (1942:1942:1942) (2100:2100:2100)) - (PORT d[12] (1901:1901:1901) (2017:2017:2017)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1717:1717:1717) (1648:1648:1648)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1879:1879:1879)) - (PORT d[0] (2052:2052:2052) (2017:2017:2017)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1152:1152:1152) (1168:1168:1168)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3672:3672:3672) (3852:3852:3852)) - (PORT d[1] (1686:1686:1686) (1851:1851:1851)) - (PORT d[2] (1971:1971:1971) (2046:2046:2046)) - (PORT d[3] (2163:2163:2163) (2263:2263:2263)) - (PORT d[4] (2177:2177:2177) (2306:2306:2306)) - (PORT d[5] (1373:1373:1373) (1485:1485:1485)) - (PORT d[6] (1492:1492:1492) (1541:1541:1541)) - (PORT d[7] (1731:1731:1731) (1802:1802:1802)) - (PORT d[8] (3606:3606:3606) (3855:3855:3855)) - (PORT d[9] (3144:3144:3144) (3281:3281:3281)) - (PORT d[10] (3176:3176:3176) (3363:3363:3363)) - (PORT d[11] (2072:2072:2072) (2195:2195:2195)) - (PORT d[12] (1417:1417:1417) (1455:1455:1455)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1662:1662:1662) (1645:1645:1645)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (PORT d[0] (2686:2686:2686) (2681:2681:2681)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1809:1809:1809) (1835:1835:1835)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (980:980:980) (1035:1035:1035)) - (PORT datab (1190:1190:1190) (1238:1238:1238)) - (PORT datac (820:820:820) (836:836:836)) - (PORT datad (1047:1047:1047) (1047:1047:1047)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1175:1175:1175) (1168:1168:1168)) - (PORT datab (1602:1602:1602) (1692:1692:1692)) - (PORT datac (1163:1163:1163) (1158:1158:1158)) - (PORT datad (312:312:312) (328:328:328)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3036:3036:3036) (3209:3209:3209)) - (PORT d[1] (2901:2901:2901) (3127:3127:3127)) - (PORT d[2] (1663:1663:1663) (1761:1761:1761)) - (PORT d[3] (1512:1512:1512) (1583:1583:1583)) - (PORT d[4] (1858:1858:1858) (1967:1967:1967)) - (PORT d[5] (1341:1341:1341) (1451:1451:1451)) - (PORT d[6] (1141:1141:1141) (1162:1162:1162)) - (PORT d[7] (1474:1474:1474) (1532:1532:1532)) - (PORT d[8] (2472:2472:2472) (2678:2678:2678)) - (PORT d[9] (3827:3827:3827) (3998:3998:3998)) - (PORT d[10] (2576:2576:2576) (2725:2725:2725)) - (PORT d[11] (1801:1801:1801) (1882:1882:1882)) - (PORT d[12] (2041:2041:2041) (2064:2064:2064)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1875:1875:1875)) - (PORT d[0] (1267:1267:1267) (1274:1274:1274)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1634:1634:1634) (1680:1680:1680)) - (PORT clk (1866:1866:1866) (1893:1893:1893)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2598:2598:2598) (2696:2696:2696)) - (PORT d[1] (2070:2070:2070) (2298:2298:2298)) - (PORT d[2] (2574:2574:2574) (2730:2730:2730)) - (PORT d[3] (2266:2266:2266) (2351:2351:2351)) - (PORT d[4] (2949:2949:2949) (3214:3214:3214)) - (PORT d[5] (2088:2088:2088) (2293:2293:2293)) - (PORT d[6] (1571:1571:1571) (1677:1677:1677)) - (PORT d[7] (2825:2825:2825) (2918:2918:2918)) - (PORT d[8] (2797:2797:2797) (3045:3045:3045)) - (PORT d[9] (2076:2076:2076) (2185:2185:2185)) - (PORT d[10] (1851:1851:1851) (1973:1973:1973)) - (PORT d[11] (3686:3686:3686) (3803:3803:3803)) - (PORT d[12] (1884:1884:1884) (1967:1967:1967)) - (PORT clk (1863:1863:1863) (1889:1889:1889)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3175:3175:3175) (3145:3145:3145)) - (PORT clk (1863:1863:1863) (1889:1889:1889)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1866:1866:1866) (1893:1893:1893)) - (PORT d[0] (2870:2870:2870) (2913:2913:2913)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1818:1818:1818)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2160:2160:2160) (2219:2219:2219)) - (PORT clk (1831:1831:1831) (1824:1824:1824)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4537:4537:4537) (4504:4504:4504)) - (PORT d[1] (4325:4325:4325) (4356:4356:4356)) - (PORT d[2] (4543:4543:4543) (4609:4609:4609)) - (PORT d[3] (4478:4478:4478) (4499:4499:4499)) - (PORT d[4] (4324:4324:4324) (4305:4305:4305)) - (PORT d[5] (4367:4367:4367) (4410:4410:4410)) - (PORT d[6] (4631:4631:4631) (4697:4697:4697)) - (PORT d[7] (4151:4151:4151) (4116:4116:4116)) - (PORT d[8] (4445:4445:4445) (4476:4476:4476)) - (PORT d[9] (4629:4629:4629) (4823:4823:4823)) - (PORT d[10] (4475:4475:4475) (4482:4482:4482)) - (PORT d[11] (4668:4668:4668) (4671:4671:4671)) - (PORT d[12] (4491:4491:4491) (4515:4515:4515)) - (PORT clk (1827:1827:1827) (1820:1820:1820)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1831:1831:1831) (1824:1824:1824)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1345:1345:1345) (1398:1398:1398)) - (PORT datab (279:279:279) (367:367:367)) - (PORT datac (1350:1350:1350) (1376:1376:1376)) - (PORT datad (1465:1465:1465) (1526:1526:1526)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1584:1584:1584) (1645:1645:1645)) - (PORT clk (1870:1870:1870) (1897:1897:1897)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2320:2320:2320) (2387:2387:2387)) - (PORT d[1] (2054:2054:2054) (2261:2261:2261)) - (PORT d[2] (2320:2320:2320) (2490:2490:2490)) - (PORT d[3] (2275:2275:2275) (2437:2437:2437)) - (PORT d[4] (2932:2932:2932) (3188:3188:3188)) - (PORT d[5] (2382:2382:2382) (2576:2576:2576)) - (PORT d[6] (1862:1862:1862) (1984:1984:1984)) - (PORT d[7] (2524:2524:2524) (2619:2619:2619)) - (PORT d[8] (3132:3132:3132) (3396:3396:3396)) - (PORT d[9] (1782:1782:1782) (1897:1897:1897)) - (PORT d[10] (1810:1810:1810) (1908:1908:1908)) - (PORT d[11] (2927:2927:2927) (3048:3048:3048)) - (PORT d[12] (1876:1876:1876) (1989:1989:1989)) - (PORT clk (1867:1867:1867) (1893:1893:1893)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2203:2203:2203) (2195:2195:2195)) - (PORT clk (1867:1867:1867) (1893:1893:1893)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1897:1897:1897)) - (PORT d[0] (3171:3171:3171) (3110:3110:3110)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1822:1822:1822)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2476:2476:2476) (2528:2528:2528)) - (PORT clk (1835:1835:1835) (1828:1828:1828)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4504:4504:4504) (4508:4508:4508)) - (PORT d[1] (4109:4109:4109) (4118:4118:4118)) - (PORT d[2] (4505:4505:4505) (4547:4547:4547)) - (PORT d[3] (4566:4566:4566) (4624:4624:4624)) - (PORT d[4] (4563:4563:4563) (4541:4541:4541)) - (PORT d[5] (4668:4668:4668) (4705:4705:4705)) - (PORT d[6] (4650:4650:4650) (4703:4703:4703)) - (PORT d[7] (4197:4197:4197) (4161:4161:4161)) - (PORT d[8] (4693:4693:4693) (4743:4743:4743)) - (PORT d[9] (4535:4535:4535) (4748:4748:4748)) - (PORT d[10] (4537:4537:4537) (4522:4522:4522)) - (PORT d[11] (4499:4499:4499) (4551:4551:4551)) - (PORT d[12] (4595:4595:4595) (4623:4623:4623)) - (PORT clk (1831:1831:1831) (1824:1824:1824)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1828:1828:1828)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1827:1827:1827) (1824:1824:1824)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (987:987:987) (1035:1035:1035)) - (PORT d[1] (989:989:989) (1045:1045:1045)) - (PORT d[2] (1232:1232:1232) (1248:1248:1248)) - (PORT d[3] (1325:1325:1325) (1386:1386:1386)) - (PORT d[4] (2598:2598:2598) (2808:2808:2808)) - (PORT d[5] (2981:2981:2981) (3208:3208:3208)) - (PORT d[6] (983:983:983) (1027:1027:1027)) - (PORT d[7] (1279:1279:1279) (1356:1356:1356)) - (PORT d[8] (1032:1032:1032) (1055:1055:1055)) - (PORT d[9] (975:975:975) (1020:1020:1020)) - (PORT d[10] (1319:1319:1319) (1384:1384:1384)) - (PORT d[11] (2558:2558:2558) (2742:2742:2742)) - (PORT d[12] (1296:1296:1296) (1368:1368:1368)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (PORT d[0] (574:574:574) (581:581:581)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1820:1820:1820) (1847:1847:1847)) @@ -46408,7 +48535,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1005:1005:1005) (1010:1010:1010)) @@ -46417,7 +48544,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1011:1011:1011)) @@ -46426,7 +48553,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1011:1011:1011)) @@ -46436,7 +48563,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1011:1011:1011)) @@ -46445,63 +48572,353 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~41) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (1284:1284:1284) (1294:1294:1294)) - (PORT datab (865:865:865) (914:914:914)) - (PORT datac (861:861:861) (866:866:866)) - (PORT datad (181:181:181) (211:211:211)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT d[0] (1400:1400:1400) (1441:1441:1441)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2235:2235:2235) (2389:2389:2389)) + (PORT d[1] (1122:1122:1122) (1125:1125:1125)) + (PORT d[2] (2684:2684:2684) (2759:2759:2759)) + (PORT d[3] (4593:4593:4593) (4819:4819:4819)) + (PORT d[4] (965:965:965) (1020:1020:1020)) + (PORT d[5] (1653:1653:1653) (1677:1677:1677)) + (PORT d[6] (1443:1443:1443) (1505:1505:1505)) + (PORT d[7] (1417:1417:1417) (1425:1425:1425)) + (PORT d[8] (2517:2517:2517) (2647:2647:2647)) + (PORT d[9] (1142:1142:1142) (1167:1167:1167)) + (PORT d[10] (2053:2053:2053) (2116:2116:2116)) + (PORT d[11] (3735:3735:3735) (3999:3999:3999)) + (PORT d[12] (2464:2464:2464) (2535:2535:2535)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2814:2814:2814) (2818:2818:2818)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (1909:1909:1909) (1894:1894:1894)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1840:1840:1840)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (999:999:999) (1003:1003:1003)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (885:885:885)) + (PORT datab (1257:1257:1257) (1321:1321:1321)) + (PORT datac (1457:1457:1457) (1543:1543:1543)) + (PORT datad (1415:1415:1415) (1470:1470:1470)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~42) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (255:255:255)) - (PORT datab (282:282:282) (370:370:370)) - (PORT datac (1627:1627:1627) (1645:1645:1645)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT d[0] (1461:1461:1461) (1498:1498:1498)) + (PORT clk (1856:1856:1856) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1675:1675:1675) (1799:1799:1799)) + (PORT d[1] (2219:2219:2219) (2269:2269:2269)) + (PORT d[2] (2260:2260:2260) (2441:2441:2441)) + (PORT d[3] (1737:1737:1737) (1761:1761:1761)) + (PORT d[4] (2421:2421:2421) (2555:2555:2555)) + (PORT d[5] (2836:2836:2836) (2889:2889:2889)) + (PORT d[6] (2028:2028:2028) (2126:2126:2126)) + (PORT d[7] (1728:1728:1728) (1790:1790:1790)) + (PORT d[8] (2170:2170:2170) (2268:2268:2268)) + (PORT d[9] (1998:1998:1998) (2050:2050:2050)) + (PORT d[10] (2212:2212:2212) (2291:2291:2291)) + (PORT d[11] (4313:4313:4313) (4609:4609:4609)) + (PORT d[12] (2203:2203:2203) (2259:2259:2259)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1909:1909:1909) (1957:1957:1957)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT d[0] (1899:1899:1899) (1859:1859:1859)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1816:1816:1816) (1842:1842:1842)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1001:1001:1001) (1005:1005:1005)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~105) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~1) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (928:928:928) (981:981:981)) - (PORT datac (1193:1193:1193) (1255:1255:1255)) - (PORT datad (572:572:572) (583:583:583)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (410:410:410)) - (PORT datab (234:234:234) (278:278:278)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (183:183:183) (212:212:212)) + (PORT dataa (1194:1194:1194) (1262:1262:1262)) + (PORT datab (1708:1708:1708) (1802:1802:1802)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (1682:1682:1682) (1783:1783:1783)) (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~112) + (DELAY + (ABSOLUTE + (PORT dataa (1742:1742:1742) (1794:1794:1794)) + (PORT datab (667:667:667) (692:692:692)) + (PORT datac (628:628:628) (640:640:640)) + (PORT datad (319:319:319) (340:340:340)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -46510,44 +48927,44 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~46) + (INSTANCE D\[5\]\~113) (DELAY (ABSOLUTE - (PORT dataa (415:415:415) (501:501:501)) - (PORT datab (234:234:234) (278:278:278)) - (PORT datac (1139:1139:1139) (1183:1183:1183)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (2496:2496:2496) (2561:2561:2561)) + (PORT datab (700:700:700) (722:722:722)) + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (1174:1174:1174) (1248:1248:1248)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) (DELAY (ABSOLUTE - (PORT dataa (978:978:978) (1031:1031:1031)) - (PORT datab (648:648:648) (673:673:673)) - (PORT datac (597:597:597) (612:612:612)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (664:664:664) (690:690:690)) + (PORT datab (1158:1158:1158) (1194:1194:1194)) + (PORT datac (219:219:219) (257:257:257)) + (PORT datad (1559:1559:1559) (1584:1584:1584)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[2\]) + (INSTANCE z80_\|data_pins_\|dout\[5\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1530:1530:1530)) + (PORT clk (1527:1527:1527) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1245:1245:1245) (1226:1226:1226)) + (PORT ena (841:841:841) (846:846:846)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -46558,43 +48975,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~12) + (INSTANCE z80_\|bus_control_\|db\[5\]\~14) (DELAY (ABSOLUTE - (PORT datab (920:920:920) (962:962:962)) - (PORT datac (944:944:944) (990:990:990)) - (PORT datad (218:218:218) (253:253:253)) + (PORT datab (431:431:431) (490:490:490)) + (PORT datac (218:218:218) (263:263:263)) + (PORT datad (227:227:227) (264:264:264)) (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~13) + (INSTANCE z80_\|bus_control_\|db\[5\]\~15) (DELAY (ABSOLUTE - (PORT dataa (439:439:439) (507:507:507)) - (PORT datab (236:236:236) (280:280:280)) - (PORT datac (225:225:225) (274:274:274)) - (PORT datad (173:173:173) (199:199:199)) + (PORT dataa (873:873:873) (882:882:882)) + (PORT datab (592:592:592) (613:613:613)) + (PORT datac (532:532:532) (547:547:547)) + (PORT datad (1104:1104:1104) (1122:1122:1122)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[2\]) + (INSTANCE z80_\|ir_\|opcode\[5\]) (DELAY (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1557:1557:1557)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) + (PORT clrn (1578:1578:1578) (1558:1558:1558)) + (PORT ena (1940:1940:1940) (1962:1962:1962)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -46606,27 +49023,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~1) + (INSTANCE z80_\|execute_\|ctl_mRead\~11) (DELAY (ABSOLUTE - (PORT datac (1460:1460:1460) (1533:1533:1533)) - (PORT datad (2264:2264:2264) (2327:2327:2327)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (944:944:944) (975:975:975)) - (PORT datab (940:940:940) (997:997:997)) - (PORT datac (1637:1637:1637) (1758:1758:1758)) - (PORT datad (1220:1220:1220) (1303:1303:1303)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (2126:2126:2126) (2295:2295:2295)) + (PORT datab (2009:2009:2009) (2098:2098:2098)) + (PORT datac (1374:1374:1374) (1481:1481:1481)) + (PORT datad (877:877:877) (904:904:904)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -46634,63 +49039,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~2) + (INSTANCE z80_\|execute_\|setM1\~46) (DELAY (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (198:198:198) (235:235:235)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~3) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (859:859:859)) - (PORT datab (2054:2054:2054) (2187:2187:2187)) - (PORT datac (1260:1260:1260) (1358:1358:1358)) - (PORT datad (1087:1087:1087) (1084:1084:1084)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (1669:1669:1669) (1678:1678:1678)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) - (DELAY - (ABSOLUTE - (PORT dataa (1217:1217:1217) (1308:1308:1308)) - (PORT datab (2052:2052:2052) (2184:2184:2184)) - (PORT datac (1270:1270:1270) (1384:1384:1384)) - (PORT datad (1880:1880:1880) (1934:1934:1934)) + (PORT dataa (1208:1208:1208) (1251:1251:1251)) + (PORT datab (660:660:660) (700:700:700)) + (PORT datac (1413:1413:1413) (1458:1458:1458)) + (PORT datad (334:334:334) (357:357:357)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -46699,29 +49054,183 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~40) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1587:1587:1587) (1563:1563:1563)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + (PORT datac (1029:1029:1029) (1089:1089:1089)) + (PORT datad (603:603:603) (614:614:614)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) + (INSTANCE z80_\|execute_\|nextM\~5) (DELAY (ABSOLUTE - (PORT datab (252:252:252) (337:337:337)) - (PORT datad (226:226:226) (299:299:299)) + (PORT dataa (220:220:220) (263:263:263)) + (PORT datab (1871:1871:1871) (1947:1947:1947)) + (PORT datac (195:195:195) (228:228:228)) + (PORT datad (1085:1085:1085) (1121:1121:1121)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1202:1202:1202) (1239:1239:1239)) + (PORT datab (230:230:230) (272:272:272)) + (PORT datac (611:611:611) (641:641:641)) + (PORT datad (596:596:596) (616:616:616)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1281:1281:1281) (1354:1354:1354)) + (PORT datab (757:757:757) (812:812:812)) + (PORT datac (1936:1936:1936) (1953:1953:1953)) + (PORT datad (827:827:827) (852:852:852)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~9) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (683:683:683)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (1472:1472:1472) (1542:1542:1542)) + (PORT datad (632:632:632) (697:697:697)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1686:1686:1686) (1728:1728:1728)) + (PORT datab (924:924:924) (949:949:949)) + (PORT datac (1405:1405:1405) (1437:1437:1437)) + (PORT datad (869:869:869) (884:884:884)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~8) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (692:692:692)) + (PORT datab (1323:1323:1323) (1377:1377:1377)) + (PORT datac (213:213:213) (245:245:245)) + (PORT datad (1699:1699:1699) (1713:1713:1713)) + (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~12) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (267:267:267)) + (PORT datab (658:658:658) (707:707:707)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~15) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (890:890:890)) + (PORT datab (2358:2358:2358) (2453:2453:2453)) + (PORT datac (1473:1473:1473) (1589:1589:1589)) + (PORT datad (1034:1034:1034) (1093:1093:1093)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~13) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (941:941:941)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~14) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (247:247:247)) + (PORT datab (588:588:588) (602:602:602)) + (PORT datac (587:587:587) (646:646:646)) + (PORT datad (1400:1400:1400) (1419:1419:1419)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|ena_M) + (DELAY + (ABSOLUTE + (PORT datac (679:679:679) (727:727:727)) + (PORT datad (889:889:889) (908:908:908)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -46731,10 +49240,10 @@ (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT clk (1525:1525:1525) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT ena (1243:1243:1243) (1234:1234:1234)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -46749,9 +49258,9 @@ (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) (DELAY (ABSOLUTE - (PORT dataa (267:267:267) (353:353:353)) - (PORT datac (1094:1094:1094) (1135:1135:1135)) - (PORT datad (1105:1105:1105) (1151:1151:1151)) + (PORT dataa (698:698:698) (774:774:774)) + (PORT datac (683:683:683) (724:724:724)) + (PORT datad (890:890:890) (904:904:904)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -46763,10 +49272,10 @@ (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT clk (1525:1525:1525) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT ena (1243:1243:1243) (1234:1234:1234)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -46778,40 +49287,692 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|x3) + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) (DELAY (ABSOLUTE - (PORT dataa (2393:2393:2393) (2551:2551:2551)) - (PORT datac (239:239:239) (317:317:317)) - (PORT datad (1364:1364:1364) (1506:1506:1506)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (266:266:266) (354:354:354)) + (PORT datac (685:685:685) (725:725:725)) + (PORT datad (891:891:891) (904:904:904)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) + (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) (DELAY (ABSOLUTE - (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT clk (1525:1525:1525) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1883:1883:1883) (1869:1869:1869)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT ena (1243:1243:1243) (1234:1234:1234)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT inclk[0] (1583:1583:1583) (1637:1637:1637)) + (PORT dataa (267:267:267) (355:355:355)) + (PORT datac (680:680:680) (727:727:727)) + (PORT datad (893:893:893) (910:910:910)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT ena (1243:1243:1243) (1234:1234:1234)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~9) + (DELAY + (ABSOLUTE + (PORT datac (695:695:695) (789:789:789)) + (PORT datad (2317:2317:2317) (2438:2438:2438)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1194:1194:1194) (1283:1283:1283)) + (PORT datab (1491:1491:1491) (1605:1605:1605)) + (PORT datac (1593:1593:1593) (1631:1631:1631)) + (PORT datad (953:953:953) (980:980:980)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~54) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1176:1176:1176)) + (PORT datab (662:662:662) (691:691:691)) + (PORT datac (1163:1163:1163) (1238:1238:1238)) + (PORT datad (898:898:898) (985:985:985)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~25) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (689:689:689)) + (PORT datab (1319:1319:1319) (1372:1372:1372)) + (PORT datac (624:624:624) (642:642:642)) + (PORT datad (866:866:866) (881:881:881)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1220:1220:1220) (1259:1259:1259)) + (PORT datab (974:974:974) (1000:1000:1000)) + (PORT datac (255:255:255) (313:313:313)) + (PORT datad (1134:1134:1134) (1181:1181:1181)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1200:1200:1200) (1254:1254:1254)) + (PORT datab (606:606:606) (649:649:649)) + (PORT datac (872:872:872) (901:901:901)) + (PORT datad (807:807:807) (862:862:862)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~22) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (1002:1002:1002)) + (PORT datab (1460:1460:1460) (1527:1527:1527)) + (PORT datac (2859:2859:2859) (2966:2966:2966)) + (PORT datad (229:229:229) (304:304:304)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~55) + (DELAY + (ABSOLUTE + (PORT dataa (1419:1419:1419) (1546:1546:1546)) + (PORT datab (1084:1084:1084) (1106:1106:1106)) + (PORT datac (1238:1238:1238) (1330:1330:1330)) + (PORT datad (2052:2052:2052) (2171:2171:2171)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1120:1120:1120) (1150:1150:1150)) + (PORT datab (384:384:384) (410:410:410)) + (PORT datac (820:820:820) (894:894:894)) + (PORT datad (1655:1655:1655) (1717:1717:1717)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~24) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (927:927:927) (989:989:989)) + (PORT datac (864:864:864) (890:890:890)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~28) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (570:570:570)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (611:611:611) (630:630:630)) + (PORT datad (875:875:875) (908:908:908)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1084:1084:1084) (1172:1172:1172)) + (PORT datab (1952:1952:1952) (2000:2000:2000)) + (PORT datac (939:939:939) (1020:1020:1020)) + (PORT datad (1208:1208:1208) (1249:1249:1249)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1722:1722:1722) (1767:1767:1767)) + (PORT datab (2033:2033:2033) (2073:2073:2073)) + (PORT datac (1628:1628:1628) (1671:1671:1671)) + (PORT datad (1597:1597:1597) (1619:1619:1619)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~29) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (886:886:886)) + (PORT datab (832:832:832) (896:896:896)) + (PORT datac (869:869:869) (939:939:939)) + (PORT datad (1271:1271:1271) (1354:1354:1354)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1178:1178:1178) (1190:1190:1190)) + (PORT datab (884:884:884) (932:932:932)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1296:1296:1296) (1353:1353:1353)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~32) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (942:942:942)) + (PORT datab (1536:1536:1536) (1590:1590:1590)) + (PORT datac (1141:1141:1141) (1163:1163:1163)) + (PORT datad (1571:1571:1571) (1615:1615:1615)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~34) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (883:883:883)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (845:845:845) (843:843:843)) + (PORT datad (1659:1659:1659) (1685:1685:1685)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~20) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (988:988:988)) + (PORT datab (261:261:261) (343:343:343)) + (PORT datac (1656:1656:1656) (1675:1675:1675)) + (PORT datad (928:928:928) (961:961:961)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1199:1199:1199) (1254:1254:1254)) + (PORT datab (1283:1283:1283) (1356:1356:1356)) + (PORT datac (899:899:899) (912:912:912)) + (PORT datad (812:812:812) (861:861:861)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~35) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~15) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (662:662:662)) + (PORT datab (1239:1239:1239) (1284:1284:1284)) + (PORT datac (1420:1420:1420) (1516:1516:1516)) + (PORT datad (610:610:610) (633:633:633)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~14) + (DELAY + (ABSOLUTE + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (607:607:607) (632:632:632)) + (PORT datad (1915:1915:1915) (1966:1966:1966)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1167:1167:1167) (1219:1219:1219)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1354:1354:1354) (1355:1355:1355)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1152:1152:1152) (1228:1228:1228)) + (PORT datab (1143:1143:1143) (1197:1197:1197)) + (PORT datac (1388:1388:1388) (1456:1456:1456)) + (PORT datad (1311:1311:1311) (1375:1375:1375)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1124:1124:1124) (1140:1140:1140)) + (PORT datab (1614:1614:1614) (1768:1768:1768)) + (PORT datac (1340:1340:1340) (1376:1376:1376)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (938:938:938)) + (PORT datab (1149:1149:1149) (1249:1249:1249)) + (PORT datac (666:666:666) (774:774:774)) + (PORT datad (876:876:876) (897:897:897)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~9) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (949:949:949)) + (PORT datac (1502:1502:1502) (1602:1602:1602)) + (PORT datad (838:838:838) (846:846:846)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~13) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (262:262:262)) + (PORT datab (1193:1193:1193) (1237:1237:1237)) + (PORT datac (1207:1207:1207) (1228:1228:1228)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~18) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (979:979:979)) + (PORT datab (685:685:685) (706:706:706)) + (PORT datac (179:179:179) (214:214:214)) + (PORT datad (1969:1969:1969) (2022:2022:2022)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~19) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (970:970:970)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1488:1488:1488) (1575:1575:1575)) + (PORT datad (633:633:633) (645:645:645)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1108:1108:1108) (1166:1166:1166)) + (PORT datab (1111:1111:1111) (1226:1226:1226)) + (PORT datac (565:565:565) (580:580:580)) + (PORT datad (818:818:818) (823:823:823)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~42) + (DELAY + (ABSOLUTE + (PORT dataa (1729:1729:1729) (1815:1815:1815)) + (PORT datab (1999:1999:1999) (2067:2067:2067)) + (PORT datac (939:939:939) (999:999:999)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1000:1000:1000) (1047:1047:1047)) + (PORT datab (1000:1000:1000) (1036:1036:1036)) + (PORT datac (170:170:170) (201:201:201)) + (PORT datad (937:937:937) (978:978:978)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1471:1471:1471) (1555:1555:1555)) + (PORT datab (1379:1379:1379) (1419:1419:1419)) + (PORT datac (1473:1473:1473) (1586:1586:1586)) + (PORT datad (591:591:591) (624:624:624)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~51) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (215:215:215) (260:260:260)) + (PORT datac (192:192:192) (226:226:226)) + (PORT datad (346:346:346) (362:362:362)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) + (DELAY + (ABSOLUTE + (PORT datab (266:266:266) (349:349:349)) + (PORT datac (680:680:680) (726:726:726)) + (PORT datad (894:894:894) (909:909:909)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|T6) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT ena (1243:1243:1243) (1234:1234:1234)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~52) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (915:915:915) (992:992:992)) + (PORT datac (1353:1353:1353) (1387:1387:1387)) + (PORT datad (360:360:360) (381:381:381)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~53) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (652:652:652)) + (PORT datab (1116:1116:1116) (1149:1149:1149)) + (PORT datac (905:905:905) (992:992:992)) + (PORT datad (546:546:546) (553:553:553)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) + (DELAY + (ABSOLUTE + (PORT datab (705:705:705) (765:765:765)) + (PORT datad (895:895:895) (911:911:911)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -46820,9 +49981,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M1_ff) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT clk (1525:1525:1525) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -46836,11 +49997,11 @@ (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (1130:1130:1130) (1176:1176:1176)) - (PORT datab (283:283:283) (372:372:372)) - (PORT datad (1106:1106:1106) (1160:1160:1160)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (PORT dataa (661:661:661) (724:724:724)) + (PORT datab (720:720:720) (764:764:764)) + (PORT datad (890:890:890) (904:904:904)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -46849,3104 +50010,29 @@ (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~3) - (DELAY - (ABSOLUTE - (PORT datac (1051:1051:1051) (1164:1164:1164)) - (PORT datad (2030:2030:2030) (2123:2123:2123)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1463:1463:1463) (1520:1520:1520)) - (PORT datab (853:853:853) (881:881:881)) - (PORT datac (791:791:791) (801:801:801)) - (PORT datad (672:672:672) (691:691:691)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~8) - (DELAY - (ABSOLUTE - (PORT dataa (996:996:996) (1076:1076:1076)) - (PORT datab (661:661:661) (685:685:685)) - (PORT datac (956:956:956) (1008:1008:1008)) - (PORT datad (2243:2243:2243) (2327:2327:2327)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~9) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (910:910:910)) - (PORT datab (847:847:847) (857:857:857)) - (PORT datac (945:945:945) (997:997:997)) - (PORT datad (402:402:402) (435:435:435)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~10) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (725:725:725)) - (PORT datab (334:334:334) (363:363:363)) - (PORT datac (1475:1475:1475) (1542:1542:1542)) - (PORT datad (2078:2078:2078) (2128:2128:2128)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~12) - (DELAY - (ABSOLUTE - (PORT dataa (402:402:402) (429:429:429)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~15) - (DELAY - (ABSOLUTE - (PORT dataa (2002:2002:2002) (2100:2100:2100)) - (PORT datab (880:880:880) (891:891:891)) - (PORT datac (1448:1448:1448) (1504:1504:1504)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~6) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (277:277:277)) - (PORT datab (236:236:236) (281:281:281)) - (PORT datac (354:354:354) (382:382:382)) - (PORT datad (1061:1061:1061) (1062:1062:1062)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~7) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (279:279:279)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (989:989:989) (1043:1043:1043)) - (PORT datad (780:780:780) (803:803:803)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~13) - (DELAY - (ABSOLUTE - (PORT datab (1104:1104:1104) (1138:1138:1138)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (316:316:316) (336:336:336)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~39) - (DELAY - (ABSOLUTE - (PORT datac (766:766:766) (771:771:771)) - (PORT datad (608:608:608) (623:623:623)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~5) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (252:252:252)) - (PORT datab (2053:2053:2053) (2084:2084:2084)) - (PORT datac (618:618:618) (675:675:675)) - (PORT datad (334:334:334) (341:341:341)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~14) - (DELAY - (ABSOLUTE - (PORT dataa (834:834:834) (843:843:843)) - (PORT datab (877:877:877) (909:909:909)) - (PORT datac (1022:1022:1022) (1035:1035:1035)) - (PORT datad (538:538:538) (551:551:551)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT datab (273:273:273) (358:358:358)) - (PORT datac (1093:1093:1093) (1130:1130:1130)) - (PORT datad (1107:1107:1107) (1155:1155:1155)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (1123:1123:1123) (1157:1157:1157)) - (PORT datac (246:246:246) (327:327:327)) - (PORT datad (1110:1110:1110) (1159:1159:1159)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) - (DELAY - (ABSOLUTE - (PORT datab (265:265:265) (348:348:348)) - (PORT datac (1077:1077:1077) (1114:1114:1114)) - (PORT datad (1111:1111:1111) (1161:1161:1161)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|T6) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~13) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (637:637:637)) - (PORT datab (872:872:872) (895:895:895)) - (PORT datac (589:589:589) (612:612:612)) - (PORT datad (914:914:914) (960:960:960)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1005:1005:1005) (1115:1115:1115)) - (PORT datab (1187:1187:1187) (1258:1258:1258)) - (PORT datac (655:655:655) (715:715:715)) - (PORT datad (1245:1245:1245) (1328:1328:1328)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~12) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (719:719:719)) - (PORT datab (1671:1671:1671) (1704:1704:1704)) - (PORT datac (864:864:864) (890:890:890)) - (PORT datad (857:857:857) (896:896:896)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~14) - (DELAY - (ABSOLUTE - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (631:631:631) (681:681:681)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~41) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (442:442:442)) - (PORT datac (1069:1069:1069) (1104:1104:1104)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~42) - (DELAY - (ABSOLUTE - (PORT dataa (937:937:937) (992:992:992)) - (PORT datab (1106:1106:1106) (1172:1172:1172)) - (PORT datac (411:411:411) (452:452:452)) - (PORT datad (2503:2503:2503) (2629:2629:2629)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~43) - (DELAY - (ABSOLUTE - (PORT dataa (2006:2006:2006) (2147:2147:2147)) - (PORT datab (771:771:771) (831:831:831)) - (PORT datac (960:960:960) (989:989:989)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~44) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (941:941:941)) - (PORT datab (355:355:355) (391:391:391)) - (PORT datac (202:202:202) (239:239:239)) - (PORT datad (759:759:759) (760:760:760)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~50) - (DELAY - (ABSOLUTE - (PORT dataa (377:377:377) (403:403:403)) - (PORT datab (1048:1048:1048) (1080:1080:1080)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (1303:1303:1303) (1325:1325:1325)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1188:1188:1188)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (200:200:200) (237:237:237)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~6) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (871:871:871)) - (PORT datab (1589:1589:1589) (1720:1720:1720)) - (PORT datac (636:636:636) (653:653:653)) - (PORT datad (1694:1694:1694) (1790:1790:1790)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~7) - (DELAY - (ABSOLUTE - (PORT datab (867:867:867) (913:913:913)) - (PORT datac (893:893:893) (946:946:946)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1439:1439:1439) (1482:1482:1482)) - (PORT datab (885:885:885) (895:895:895)) - (PORT datac (878:878:878) (926:926:926)) - (PORT datad (632:632:632) (642:642:642)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1493:1493:1493) (1600:1600:1600)) - (PORT datab (1951:1951:1951) (2023:2023:2023)) - (PORT datac (1350:1350:1350) (1424:1424:1424)) - (PORT datad (1111:1111:1111) (1134:1134:1134)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~10) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (1125:1125:1125) (1164:1164:1164)) - (PORT datac (514:514:514) (525:525:525)) - (PORT datad (639:639:639) (676:676:676)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~11) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1215:1215:1215) (1255:1255:1255)) - (PORT datac (1013:1013:1013) (1058:1058:1058)) - (PORT datad (342:342:342) (364:364:364)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~17) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (655:655:655)) - (PORT datab (1046:1046:1046) (1078:1078:1078)) - (PORT datac (2017:2017:2017) (2052:2052:2052)) - (PORT datad (621:621:621) (635:635:635)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~31) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (662:662:662)) - (PORT datab (914:914:914) (975:975:975)) - (PORT datac (1817:1817:1817) (1894:1894:1894)) - (PORT datad (898:898:898) (912:912:912)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~28) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (403:403:403)) - (PORT datab (1223:1223:1223) (1259:1259:1259)) - (PORT datac (1402:1402:1402) (1465:1465:1465)) - (PORT datad (856:856:856) (854:854:854)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~30) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (886:886:886)) - (PORT datab (916:916:916) (944:944:944)) - (PORT datac (906:906:906) (930:930:930)) - (PORT datad (843:843:843) (882:882:882)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~32) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (960:960:960)) - (PORT datab (360:360:360) (395:395:395)) - (PORT datac (859:859:859) (902:902:902)) - (PORT datad (1107:1107:1107) (1120:1120:1120)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~33) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (602:602:602)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (896:896:896) (935:935:935)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1215:1215:1215)) - (PORT datac (627:627:627) (650:650:650)) - (PORT datad (1592:1592:1592) (1700:1700:1700)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~26) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (906:906:906)) - (PORT datab (1566:1566:1566) (1611:1611:1611)) - (PORT datac (868:868:868) (891:891:891)) - (PORT datad (1122:1122:1122) (1151:1151:1151)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~24) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (723:723:723)) - (PORT datab (660:660:660) (684:684:684)) - (PORT datac (2018:2018:2018) (1985:1985:1985)) - (PORT datad (954:954:954) (1028:1028:1028)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~27) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (643:643:643) (693:693:693)) - (PORT datad (661:661:661) (727:727:727)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~22) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (949:949:949)) - (PORT datab (904:904:904) (924:924:924)) - (PORT datac (888:888:888) (932:932:932)) - (PORT datad (623:623:623) (628:628:628)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1744:1744:1744) (1869:1869:1869)) - (PORT datab (1550:1550:1550) (1688:1688:1688)) - (PORT datac (1209:1209:1209) (1285:1285:1285)) - (PORT datad (1505:1505:1505) (1539:1539:1539)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~53) - (DELAY - (ABSOLUTE - (PORT dataa (965:965:965) (1045:1045:1045)) - (PORT datab (936:936:936) (1009:1009:1009)) - (PORT datac (649:649:649) (669:669:669)) - (PORT datad (1286:1286:1286) (1339:1339:1339)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~23) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (240:240:240)) - (PORT datab (363:363:363) (396:396:396)) - (PORT datac (1524:1524:1524) (1571:1571:1571)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~18) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (412:412:412)) - (PORT datab (990:990:990) (1020:1020:1020)) - (PORT datac (1523:1523:1523) (1602:1602:1602)) - (PORT datad (193:193:193) (219:219:219)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~19) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (644:644:644)) - (PORT datab (693:693:693) (758:758:758)) - (PORT datac (646:646:646) (704:704:704)) - (PORT datad (1320:1320:1320) (1419:1419:1419)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~20) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (675:675:675)) - (PORT datab (1180:1180:1180) (1218:1218:1218)) - (PORT datac (868:868:868) (922:922:922)) - (PORT datad (604:604:604) (625:625:625)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~34) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (649:649:649)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (309:309:309) (334:334:334)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~52) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (312:312:312) (330:330:330)) - (PORT datad (970:970:970) (1032:1032:1032)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1167:1167:1167)) - (PORT datac (245:245:245) (326:326:326)) - (PORT datad (1111:1111:1111) (1159:1159:1159)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) - (DELAY - (ABSOLUTE - (PORT datac (984:984:984) (1073:1073:1073)) - (PORT datad (1348:1348:1348) (1490:1490:1490)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~0) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (497:497:497)) - (PORT datac (1177:1177:1177) (1261:1261:1261)) - (PORT datad (272:272:272) (353:353:353)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~1) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (697:697:697)) - (PORT datab (1593:1593:1593) (1628:1628:1628)) - (PORT datad (638:638:638) (679:679:679)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|in_halt) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1532:1532:1532)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1555:1555:1555)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (991:991:991) (1049:1049:1049)) - (PORT datab (1153:1153:1153) (1214:1214:1214)) - (PORT datac (671:671:671) (718:718:718)) - (PORT datad (624:624:624) (674:674:674)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1120:1120:1120) (1227:1227:1227)) - (PORT datab (994:994:994) (1058:1058:1058)) - (PORT datac (1165:1165:1165) (1211:1211:1211)) - (PORT datad (879:879:879) (933:933:933)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (401:401:401) (432:432:432)) - (PORT datab (689:689:689) (742:742:742)) - (PORT datac (882:882:882) (943:943:943)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) - (DELAY - (ABSOLUTE - (PORT datac (1080:1080:1080) (1100:1100:1100)) - (PORT datad (647:647:647) (663:663:663)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (954:954:954) (979:979:979)) - (PORT datac (638:638:638) (653:653:653)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (254:254:254) (309:309:309)) - (PORT datac (944:944:944) (985:985:985)) - (PORT datad (335:335:335) (356:356:356)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~93) - (DELAY - (ABSOLUTE - (PORT dataa (227:227:227) (285:285:285)) - (PORT datab (780:780:780) (881:881:881)) - (PORT datac (1368:1368:1368) (1458:1458:1458)) - (PORT datad (562:562:562) (568:568:568)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~94) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (659:659:659)) - (PORT datab (733:733:733) (831:831:831)) - (PORT datad (718:718:718) (812:812:812)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) - (DELAY - (ABSOLUTE - (PORT dataa (741:741:741) (849:849:849)) - (PORT datab (1176:1176:1176) (1266:1266:1266)) - (PORT datac (727:727:727) (821:821:821)) - (PORT datad (735:735:735) (837:837:837)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~98) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datab (208:208:208) (251:251:251)) - (PORT datad (184:184:184) (213:213:213)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (1136:1136:1136) (1168:1168:1168)) - (PORT datab (1145:1145:1145) (1215:1215:1215)) - (PORT datac (215:215:215) (292:292:292)) - (PORT datad (361:361:361) (417:417:417)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~99) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (873:873:873)) - (PORT datab (729:729:729) (817:817:817)) - (PORT datac (885:885:885) (954:954:954)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~100) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (378:378:378)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datad (735:735:735) (822:822:822)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (745:745:745) (850:850:850)) - (PORT datab (987:987:987) (1082:1082:1082)) - (PORT datad (938:938:938) (1011:1011:1011)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) - (DELAY - (ABSOLUTE - (PORT dataa (743:743:743) (852:852:852)) - (PORT datab (723:723:723) (826:826:826)) - (PORT datac (1146:1146:1146) (1231:1231:1231)) - (PORT datad (910:910:910) (977:977:977)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~133) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (704:704:704)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (728:728:728) (824:824:824)) - (PORT datad (731:731:731) (831:831:831)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~103) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datad (322:322:322) (345:345:345)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (622:622:622)) - (PORT datab (422:422:422) (485:485:485)) - (PORT datac (556:556:556) (585:585:585)) - (PORT datad (616:616:616) (671:671:671)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (816:816:816)) - (PORT datab (729:729:729) (827:827:827)) - (PORT datac (720:720:720) (822:822:822)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~105) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (245:245:245)) - (PORT datab (367:367:367) (395:395:395)) - (PORT datad (718:718:718) (814:814:814)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) - (DELAY - (ABSOLUTE - (PORT dataa (1414:1414:1414) (1548:1548:1548)) - (PORT datab (216:216:216) (261:261:261)) - (PORT datac (959:959:959) (1039:1039:1039)) - (PORT datad (204:204:204) (234:234:234)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (732:732:732) (817:817:817)) - (PORT datab (665:665:665) (745:745:745)) - (PORT datac (658:658:658) (727:727:727)) - (PORT datad (433:433:433) (505:505:505)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (279:279:279)) - (PORT datab (412:412:412) (492:492:492)) - (PORT datac (628:628:628) (701:701:701)) - (PORT datad (406:406:406) (471:471:471)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~134) - (DELAY - (ABSOLUTE - (PORT dataa (377:377:377) (399:399:399)) - (PORT datab (380:380:380) (403:403:403)) - (PORT datad (833:833:833) (879:879:879)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) - (DELAY - (ABSOLUTE - (PORT dataa (740:740:740) (824:824:824)) - (PORT datab (602:602:602) (630:630:630)) - (PORT datac (616:616:616) (675:675:675)) - (PORT datad (531:531:531) (537:537:537)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~135) - (DELAY - (ABSOLUTE - (PORT dataa (737:737:737) (827:827:827)) - (PORT datab (274:274:274) (360:360:360)) - (PORT datad (1094:1094:1094) (1148:1148:1148)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~108) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (245:245:245)) - (PORT datab (365:365:365) (407:407:407)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (330:330:330)) - (PORT datab (1198:1198:1198) (1264:1264:1264)) - (PORT datac (618:618:618) (676:676:676)) - (PORT datad (777:777:777) (790:790:790)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~112) - (DELAY - (ABSOLUTE - (PORT dataa (853:853:853) (877:877:877)) - (PORT datab (222:222:222) (269:269:269)) - (PORT datac (638:638:638) (702:702:702)) - (PORT datad (324:324:324) (344:344:344)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~113) - (DELAY - (ABSOLUTE - (PORT dataa (734:734:734) (817:817:817)) - (PORT datab (201:201:201) (241:241:241)) - (PORT datac (569:569:569) (605:605:605)) - (PORT datad (464:464:464) (535:535:535)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~114) - (DELAY - (ABSOLUTE - (PORT datab (562:562:562) (582:582:582)) - (PORT datad (867:867:867) (872:872:872)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1568:1568:1568) (1563:1563:1563)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~109) - (DELAY - (ABSOLUTE - (PORT dataa (740:740:740) (820:820:820)) - (PORT datab (654:654:654) (726:726:726)) - (PORT datac (638:638:638) (703:703:703)) - (PORT datad (802:802:802) (842:842:842)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (736:736:736) (822:822:822)) - (PORT datab (225:225:225) (273:273:273)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (638:638:638) (709:709:709)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~137) - (DELAY - (ABSOLUTE - (PORT dataa (734:734:734) (821:821:821)) - (PORT datab (334:334:334) (362:362:362)) - (PORT datad (340:340:340) (370:370:370)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~138) - (DELAY - (ABSOLUTE - (PORT dataa (1042:1042:1042) (1147:1147:1147)) - (PORT datab (671:671:671) (712:712:712)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~2) - (DELAY - (ABSOLUTE - (PORT datab (1402:1402:1402) (1455:1455:1455)) - (PORT datac (1615:1615:1615) (1701:1701:1701)) - (PORT datad (1189:1189:1189) (1294:1294:1294)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (277:277:277)) - (PORT datab (1199:1199:1199) (1232:1232:1232)) - (PORT datac (1173:1173:1173) (1255:1255:1255)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (1123:1123:1123) (1183:1183:1183)) - (PORT datab (3290:3290:3290) (3477:3477:3477)) - (PORT datac (1148:1148:1148) (1200:1200:1200)) - (PORT datad (561:561:561) (572:572:572)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1048:1048:1048) (1087:1087:1087)) - (PORT clk (1847:1847:1847) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3996:3996:3996) (4212:4212:4212)) - (PORT d[1] (1700:1700:1700) (1852:1852:1852)) - (PORT d[2] (1685:1685:1685) (1760:1760:1760)) - (PORT d[3] (1880:1880:1880) (1986:1986:1986)) - (PORT d[4] (2151:2151:2151) (2275:2275:2275)) - (PORT d[5] (1351:1351:1351) (1462:1462:1462)) - (PORT d[6] (1496:1496:1496) (1550:1550:1550)) - (PORT d[7] (3357:3357:3357) (3515:3515:3515)) - (PORT d[8] (3629:3629:3629) (3880:3880:3880)) - (PORT d[9] (1469:1469:1469) (1530:1530:1530)) - (PORT d[10] (3184:3184:3184) (3384:3384:3384)) - (PORT d[11] (2096:2096:2096) (2225:2225:2225)) - (PORT d[12] (1735:1735:1735) (1780:1780:1780)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2569:2569:2569) (2625:2625:2625)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1875:1875:1875)) - (PORT d[0] (2985:2985:2985) (3047:3047:3047)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1834:1834:1834)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (992:992:992) (997:997:997)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (672:672:672) (698:698:698)) - (PORT clk (1851:1851:1851) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3032:3032:3032) (3215:3215:3215)) - (PORT d[1] (1378:1378:1378) (1491:1491:1491)) - (PORT d[2] (2016:2016:2016) (2093:2093:2093)) - (PORT d[3] (2186:2186:2186) (2283:2283:2283)) - (PORT d[4] (1556:1556:1556) (1641:1641:1641)) - (PORT d[5] (1392:1392:1392) (1479:1479:1479)) - (PORT d[6] (1191:1191:1191) (1221:1221:1221)) - (PORT d[7] (3356:3356:3356) (3523:3523:3523)) - (PORT d[8] (2486:2486:2486) (2673:2673:2673)) - (PORT d[9] (3482:3482:3482) (3624:3624:3624)) - (PORT d[10] (2885:2885:2885) (3060:3060:3060)) - (PORT d[11] (1777:1777:1777) (1854:1854:1854)) - (PORT d[12] (1425:1425:1425) (1448:1448:1448)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1966:1966:1966) (1924:1924:1924)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (2989:2989:2989) (2983:2983:2983)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (988:988:988) (1034:1034:1034)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3012:3012:3012) (3174:3174:3174)) - (PORT d[1] (1364:1364:1364) (1477:1477:1477)) - (PORT d[2] (1640:1640:1640) (1735:1735:1735)) - (PORT d[3] (1512:1512:1512) (1577:1577:1577)) - (PORT d[4] (1911:1911:1911) (1988:1988:1988)) - (PORT d[5] (1627:1627:1627) (1743:1743:1743)) - (PORT d[6] (1358:1358:1358) (1370:1370:1370)) - (PORT d[7] (1444:1444:1444) (1493:1493:1493)) - (PORT d[8] (2152:2152:2152) (2337:2337:2337)) - (PORT d[9] (3818:3818:3818) (3964:3964:3964)) - (PORT d[10] (2602:2602:2602) (2756:2756:2756)) - (PORT d[11] (1824:1824:1824) (1907:1907:1907)) - (PORT d[12] (2034:2034:2034) (2077:2077:2077)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1660:1660:1660) (1642:1642:1642)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1879:1879:1879)) - (PORT d[0] (2201:2201:2201) (2225:2225:2225)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (653:653:653)) - (PORT datab (1345:1345:1345) (1422:1422:1422)) - (PORT datac (885:885:885) (921:921:921)) - (PORT datad (1162:1162:1162) (1219:1219:1219)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1287:1287:1287) (1355:1355:1355)) - (PORT clk (1847:1847:1847) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3658:3658:3658) (3886:3886:3886)) - (PORT d[1] (1696:1696:1696) (1864:1864:1864)) - (PORT d[2] (3022:3022:3022) (3145:3145:3145)) - (PORT d[3] (2178:2178:2178) (2273:2273:2273)) - (PORT d[4] (2261:2261:2261) (2381:2381:2381)) - (PORT d[5] (2406:2406:2406) (2602:2602:2602)) - (PORT d[6] (2067:2067:2067) (2147:2147:2147)) - (PORT d[7] (2761:2761:2761) (2873:2873:2873)) - (PORT d[8] (3032:3032:3032) (3240:3240:3240)) - (PORT d[9] (2561:2561:2561) (2657:2657:2657)) - (PORT d[10] (3754:3754:3754) (3977:3977:3977)) - (PORT d[11] (1812:1812:1812) (1889:1889:1889)) - (PORT d[12] (2036:2036:2036) (2121:2121:2121)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2791:2791:2791) (2784:2784:2784)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1875:1875:1875)) - (PORT d[0] (2736:2736:2736) (2702:2702:2702)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1834:1834:1834)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (992:992:992) (997:997:997)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (1203:1203:1203) (1271:1271:1271)) - (PORT datab (935:935:935) (963:963:963)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1431:1431:1431) (1479:1479:1479)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3642:3642:3642) (3806:3806:3806)) - (PORT d[1] (2601:2601:2601) (2824:2824:2824)) - (PORT d[2] (1657:1657:1657) (1747:1747:1747)) - (PORT d[3] (2161:2161:2161) (2264:2264:2264)) - (PORT d[4] (1866:1866:1866) (1940:1940:1940)) - (PORT d[5] (1348:1348:1348) (1465:1465:1465)) - (PORT d[6] (1148:1148:1148) (1176:1176:1176)) - (PORT d[7] (1458:1458:1458) (1492:1492:1492)) - (PORT d[8] (2173:2173:2173) (2360:2360:2360)) - (PORT d[9] (3841:3841:3841) (3989:3989:3989)) - (PORT d[10] (2571:2571:2571) (2714:2714:2714)) - (PORT d[11] (2100:2100:2100) (2188:2188:2188)) - (PORT d[12] (2024:2024:2024) (2056:2056:2056)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (3353:3353:3353) (3478:3478:3478)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1472:1472:1472) (1543:1543:1543)) - (PORT clk (1846:1846:1846) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3349:3349:3349) (3537:3537:3537)) - (PORT d[1] (2304:2304:2304) (2505:2505:2505)) - (PORT d[2] (2195:2195:2195) (2287:2287:2287)) - (PORT d[3] (1835:1835:1835) (1941:1941:1941)) - (PORT d[4] (2157:2157:2157) (2255:2255:2255)) - (PORT d[5] (1649:1649:1649) (1788:1788:1788)) - (PORT d[6] (1483:1483:1483) (1506:1506:1506)) - (PORT d[7] (1491:1491:1491) (1524:1524:1524)) - (PORT d[8] (2907:2907:2907) (3105:3105:3105)) - (PORT d[9] (2279:2279:2279) (2414:2414:2414)) - (PORT d[10] (2285:2285:2285) (2382:2382:2382)) - (PORT d[11] (2475:2475:2475) (2611:2611:2611)) - (PORT d[12] (1976:1976:1976) (2027:2027:2027)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2840:2840:2840) (2830:2830:2830)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (PORT d[0] (3982:3982:3982) (4087:4087:4087)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1801:1801:1801) (1800:1800:1800)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2301:2301:2301) (2290:2290:2290)) - (PORT clk (1811:1811:1811) (1806:1806:1806)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4340:4340:4340) (4420:4420:4420)) - (PORT d[1] (4239:4239:4239) (4282:4282:4282)) - (PORT d[2] (4257:4257:4257) (4315:4315:4315)) - (PORT d[3] (4538:4538:4538) (4588:4588:4588)) - (PORT d[4] (4287:4287:4287) (4306:4306:4306)) - (PORT d[5] (4351:4351:4351) (4371:4371:4371)) - (PORT d[6] (4481:4481:4481) (4572:4572:4572)) - (PORT d[7] (4342:4342:4342) (4398:4398:4398)) - (PORT d[8] (4597:4597:4597) (4592:4592:4592)) - (PORT d[9] (4469:4469:4469) (4739:4739:4739)) - (PORT d[10] (4352:4352:4352) (4394:4394:4394)) - (PORT d[11] (4350:4350:4350) (4370:4370:4370)) - (PORT d[12] (4626:4626:4626) (4608:4608:4608)) - (PORT clk (1807:1807:1807) (1802:1802:1802)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1806:1806:1806)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (886:886:886) (944:944:944)) - (PORT datab (1682:1682:1682) (1751:1751:1751)) - (PORT datac (910:910:910) (950:950:950)) - (PORT datad (1193:1193:1193) (1243:1243:1243)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3603:3603:3603) (3780:3780:3780)) - (PORT d[1] (2612:2612:2612) (2820:2820:2820)) - (PORT d[2] (1542:1542:1542) (1613:1613:1613)) - (PORT d[3] (2126:2126:2126) (2248:2248:2248)) - (PORT d[4] (2158:2158:2158) (2252:2252:2252)) - (PORT d[5] (1643:1643:1643) (1776:1776:1776)) - (PORT d[6] (1395:1395:1395) (1417:1417:1417)) - (PORT d[7] (1473:1473:1473) (1509:1509:1509)) - (PORT d[8] (2157:2157:2157) (2322:2322:2322)) - (PORT d[9] (2292:2292:2292) (2444:2444:2444)) - (PORT d[10] (2276:2276:2276) (2402:2402:2402)) - (PORT d[11] (2115:2115:2115) (2225:2225:2225)) - (PORT d[12] (2288:2288:2288) (2338:2338:2338)) - (PORT clk (1846:1846:1846) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1873:1873:1873)) - (PORT d[0] (3448:3448:3448) (3327:3327:3327)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1809:1809:1809) (1836:1836:1836)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (276:276:276)) - (PORT datab (906:906:906) (941:941:941)) - (PORT datac (1129:1129:1129) (1177:1177:1177)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1549:1549:1549) (1631:1631:1631)) - (PORT clk (1862:1862:1862) (1888:1888:1888)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2520:2520:2520) (2617:2617:2617)) - (PORT d[1] (1962:1962:1962) (2122:2122:2122)) - (PORT d[2] (1955:1955:1955) (2077:2077:2077)) - (PORT d[3] (1876:1876:1876) (2000:2000:2000)) - (PORT d[4] (2723:2723:2723) (2864:2864:2864)) - (PORT d[5] (2232:2232:2232) (2416:2416:2416)) - (PORT d[6] (2043:2043:2043) (2115:2115:2115)) - (PORT d[7] (2404:2404:2404) (2531:2531:2531)) - (PORT d[8] (2398:2398:2398) (2577:2577:2577)) - (PORT d[9] (1996:1996:1996) (2101:2101:2101)) - (PORT d[10] (1691:1691:1691) (1769:1769:1769)) - (PORT d[11] (2047:2047:2047) (2128:2128:2128)) - (PORT d[12] (2520:2520:2520) (2605:2605:2605)) - (PORT clk (1859:1859:1859) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2655:2655:2655) (2640:2640:2640)) - (PORT clk (1859:1859:1859) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1862:1862:1862) (1888:1888:1888)) - (PORT d[0] (3407:3407:3407) (3339:3339:3339)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1863:1863:1863) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1863:1863:1863) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1863:1863:1863) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1863:1863:1863) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1817:1817:1817) (1813:1813:1813)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2066:2066:2066) (2077:2077:2077)) - (PORT clk (1827:1827:1827) (1819:1819:1819)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4618:4618:4618) (4692:4692:4692)) - (PORT d[1] (4233:4233:4233) (4271:4271:4271)) - (PORT d[2] (4532:4532:4532) (4592:4592:4592)) - (PORT d[3] (4449:4449:4449) (4489:4489:4489)) - (PORT d[4] (4330:4330:4330) (4336:4336:4336)) - (PORT d[5] (4590:4590:4590) (4607:4607:4607)) - (PORT d[6] (4724:4724:4724) (4801:4801:4801)) - (PORT d[7] (4565:4565:4565) (4613:4613:4613)) - (PORT d[8] (4569:4569:4569) (4629:4629:4629)) - (PORT d[9] (4484:4484:4484) (4751:4751:4751)) - (PORT d[10] (4377:4377:4377) (4395:4395:4395)) - (PORT d[11] (4636:4636:4636) (4682:4682:4682)) - (PORT d[12] (4604:4604:4604) (4754:4754:4754)) - (PORT clk (1823:1823:1823) (1815:1815:1815)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1827:1827:1827) (1819:1819:1819)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1828:1828:1828) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1828:1828:1828) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1828:1828:1828) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1828:1828:1828) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1815:1815:1815)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (946:946:946)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (1482:1482:1482) (1521:1521:1521)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~108) - (DELAY - (ABSOLUTE - (PORT dataa (1613:1613:1613) (1669:1669:1669)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1616:1616:1616) (1701:1701:1701)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~95) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (257:257:257)) - (PORT datab (1399:1399:1399) (1458:1458:1458)) - (PORT datac (1325:1325:1325) (1390:1390:1390)) - (PORT datad (341:341:341) (359:359:359)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~96) - (DELAY - (ABSOLUTE - (PORT dataa (1628:1628:1628) (1657:1657:1657)) - (PORT datab (1397:1397:1397) (1455:1455:1455)) - (PORT datac (1102:1102:1102) (1179:1179:1179)) - (PORT datad (313:313:313) (331:331:331)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) - (DELAY - (ABSOLUTE - (PORT dataa (975:975:975) (1040:1040:1040)) - (PORT datab (1658:1658:1658) (1724:1724:1724)) - (PORT datac (239:239:239) (291:291:291)) - (PORT datad (875:875:875) (896:896:896)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (310:310:310)) - (PORT datab (660:660:660) (727:727:727)) - (PORT datad (213:213:213) (248:248:248)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (984:984:984) (1009:1009:1009)) - (PORT datab (906:906:906) (952:952:952)) - (PORT datac (884:884:884) (932:932:932)) - (PORT datad (924:924:924) (947:947:947)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[3\]) (DELAY (ABSOLUTE (PORT clk (1525:1525:1525) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1550:1550:1550)) - (PORT ena (1479:1479:1479) (1488:1488:1488)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~4) + (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) (DELAY (ABSOLUTE - (PORT dataa (1465:1465:1465) (1561:1561:1561)) - (PORT datab (1173:1173:1173) (1201:1201:1201)) - (PORT datac (1193:1193:1193) (1280:1280:1280)) - (PORT datad (1406:1406:1406) (1444:1444:1444)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (982:982:982) (1081:1081:1081)) + (PORT datac (1243:1243:1243) (1342:1342:1342)) + (PORT datad (957:957:957) (1051:1051:1051)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -49956,12 +50042,12 @@ (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) (DELAY (ABSOLUTE - (PORT dataa (894:894:894) (970:970:970)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datac (896:896:896) (900:900:900)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (1482:1482:1482) (1540:1540:1540)) + (PORT datad (1185:1185:1185) (1227:1227:1227)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -49970,9 +50056,9 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1391:1391:1391) (1424:1424:1424)) - (PORT datab (630:630:630) (671:671:671)) - (PORT datad (180:180:180) (209:209:209)) + (PORT dataa (1177:1177:1177) (1260:1260:1260)) + (PORT datab (837:837:837) (857:857:857)) + (PORT datad (173:173:173) (199:199:199)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -49984,11 +50070,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT clk (1529:1529:1529) (1534:1534:1534)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (580:580:580) (654:654:654)) - (PORT sload (1117:1117:1117) (1168:1168:1168)) - (PORT ena (811:811:811) (804:804:804)) + (PORT asdata (707:707:707) (769:769:769)) + (PORT sload (1432:1432:1432) (1514:1514:1514)) + (PORT ena (1459:1459:1459) (1480:1480:1480)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -50001,29 +50087,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~59) + (INSTANCE D\[0\]\~66) (DELAY (ABSOLUTE - (PORT dataa (884:884:884) (914:914:914)) - (PORT datab (1147:1147:1147) (1200:1200:1200)) - (PORT datac (179:179:179) (216:216:216)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT datab (902:902:902) (924:924:924)) + (PORT datac (872:872:872) (926:926:926)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~60) + (INSTANCE D\[0\]\~67) (DELAY (ABSOLUTE - (PORT dataa (948:948:948) (996:996:996)) - (PORT datab (642:642:642) (701:701:701)) - (PORT datac (1642:1642:1642) (1669:1669:1669)) - (PORT datad (329:329:329) (345:345:345)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (2781:2781:2781) (2888:2888:2888)) + (PORT datab (1476:1476:1476) (1559:1559:1559)) + (PORT datac (1480:1480:1480) (1521:1521:1521)) + (PORT datad (308:308:308) (323:323:323)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50031,13 +50117,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~61) + (INSTANCE D\[0\]\~121) (DELAY (ABSOLUTE - (PORT dataa (1445:1445:1445) (1468:1468:1468)) - (PORT datac (831:831:831) (845:845:845)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT dataa (2634:2634:2634) (2765:2765:2765)) + (PORT datab (1935:1935:1935) (2079:2079:2079)) + (PORT datac (2771:2771:2771) (3001:3001:3001)) + (PORT datad (2441:2441:2441) (2545:2545:2545)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~68) + (DELAY + (ABSOLUTE + (PORT datab (669:669:669) (709:709:709)) + (PORT datac (1085:1085:1085) (1132:1132:1132)) + (PORT datad (350:350:350) (367:367:367)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50045,13 +50147,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~62) + (INSTANCE D\[1\]\~69) (DELAY (ABSOLUTE - (PORT dataa (1402:1402:1402) (1476:1476:1476)) - (PORT datab (940:940:940) (1026:1026:1026)) - (PORT datac (962:962:962) (1081:1081:1081)) - (PORT datad (173:173:173) (198:198:198)) + (PORT dataa (2782:2782:2782) (2888:2888:2888)) + (PORT datab (949:949:949) (1041:1041:1041)) + (PORT datac (1479:1479:1479) (1520:1520:1520)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~70) + (DELAY + (ABSOLUTE + (PORT datab (1161:1161:1161) (1224:1224:1224)) + (PORT datac (844:844:844) (887:887:887)) + (PORT datad (326:326:326) (348:348:348)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (2196:2196:2196) (2279:2279:2279)) + (PORT datab (635:635:635) (666:666:666)) + (PORT datac (1696:1696:1696) (1794:1794:1794)) + (PORT datad (173:173:173) (199:199:199)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -50061,13 +50193,73 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~63) + (INSTANCE D\[3\]\~83) (DELAY (ABSOLUTE - (PORT dataa (365:365:365) (413:413:413)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT dataa (2780:2780:2780) (2885:2885:2885)) + (PORT datac (912:912:912) (1002:1002:1002)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (409:409:409)) + (PORT datab (946:946:946) (982:982:982)) + (PORT datac (332:332:332) (348:348:348)) + (PORT datad (334:334:334) (351:351:351)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~95) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (978:978:978)) + (PORT datab (917:917:917) (942:942:942)) + (PORT datac (181:181:181) (218:218:218)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~96) + (DELAY + (ABSOLUTE + (PORT dataa (1289:1289:1289) (1374:1374:1374)) + (PORT datab (436:436:436) (474:474:474)) + (PORT datac (2209:2209:2209) (2279:2279:2279)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~126) + (DELAY + (ABSOLUTE + (PORT dataa (1874:1874:1874) (1923:1923:1923)) + (PORT datab (3091:3091:3091) (3312:3312:3312)) + (PORT datac (627:627:627) (639:639:639)) + (PORT datad (321:321:321) (343:343:343)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50075,12 +50267,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~64) + (INSTANCE D\[5\]\~98) (DELAY (ABSOLUTE - (PORT dataa (414:414:414) (500:500:500)) - (PORT datab (233:233:233) (277:277:277)) - (PORT datac (1139:1139:1139) (1183:1183:1183)) + (PORT dataa (1201:1201:1201) (1291:1291:1291)) + (PORT datab (672:672:672) (697:697:697)) + (PORT datac (2459:2459:2459) (2525:2525:2525)) (PORT datad (174:174:174) (200:200:200)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (381:381:381) (380:380:380)) @@ -50091,72 +50283,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~75) + (INSTANCE D\[6\]\~105) (DELAY (ABSOLUTE - (PORT dataa (211:211:211) (260:260:260)) - (PORT datac (1325:1325:1325) (1392:1392:1392)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (1121:1121:1121) (1209:1209:1209)) - (PORT datab (1140:1140:1140) (1196:1196:1196)) - (PORT datac (1527:1527:1527) (1561:1561:1561)) - (PORT datad (328:328:328) (343:343:343)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (917:917:917)) - (PORT datab (1549:1549:1549) (1602:1602:1602)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (952:952:952) (1002:1002:1002)) - (PORT datab (1444:1444:1444) (1508:1508:1508)) - (PORT datac (1641:1641:1641) (1667:1667:1667)) - (PORT datad (330:330:330) (348:348:348)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~92) - (DELAY - (ABSOLUTE - (PORT datab (1379:1379:1379) (1383:1383:1383)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (180:180:180) (207:207:207)) + (PORT datab (873:873:873) (921:921:921)) + (PORT datac (364:364:364) (389:389:389)) + (PORT datad (349:349:349) (365:365:365)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -50165,15 +50297,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~93) + (INSTANCE D\[6\]\~106) (DELAY (ABSOLUTE - (PORT dataa (948:948:948) (1000:1000:1000)) - (PORT datab (894:894:894) (967:967:967)) - (PORT datac (1642:1642:1642) (1672:1672:1672)) + (PORT dataa (1214:1214:1214) (1328:1328:1328)) + (PORT datab (636:636:636) (664:664:664)) + (PORT datac (2169:2169:2169) (2244:2244:2244)) (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~128) + (DELAY + (ABSOLUTE + (PORT dataa (2802:2802:2802) (3046:3046:3046)) + (PORT datab (2034:2034:2034) (2097:2097:2097)) + (PORT datac (180:180:180) (219:219:219)) + (PORT datad (615:615:615) (641:641:641)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~107) + (DELAY + (ABSOLUTE + (PORT dataa (1207:1207:1207) (1304:1304:1304)) + (PORT datab (2479:2479:2479) (2586:2586:2586)) + (PORT datac (346:346:346) (370:370:370)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) + (DELAY + (ABSOLUTE + (PORT datab (249:249:249) (333:333:333)) + (PORT datac (857:857:857) (879:879:879)) + (PORT datad (230:230:230) (303:303:303)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50184,11 +50362,11 @@ (INSTANCE z80_\|nM1_int\~3) (DELAY (ABSOLUTE - (PORT datab (1365:1365:1365) (1505:1505:1505)) - (PORT datac (2335:2335:2335) (2467:2467:2467)) - (PORT datad (554:554:554) (564:564:564)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (706:706:706) (760:760:760)) + (PORT datac (668:668:668) (739:739:739)) + (PORT datad (617:617:617) (675:675:675)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50198,10 +50376,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_16) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) + (PORT clk (1525:1525:1525) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT ena (1243:1243:1243) (1234:1234:1234)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50216,7 +50394,7 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17\~feeder) (DELAY (ABSOLUTE - (PORT datad (242:242:242) (312:312:312)) + (PORT datad (673:673:673) (730:730:730)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50226,10 +50404,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17) (DELAY (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1530:1530:1530)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) + (PORT clrn (1581:1581:1581) (1557:1557:1557)) + (PORT ena (1253:1253:1253) (1263:1263:1263)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50244,10 +50422,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_mreq_ff2) (DELAY (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT asdata (565:565:565) (644:644:644)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) + (PORT clk (1532:1532:1532) (1530:1530:1530)) + (PORT asdata (569:569:569) (648:648:648)) + (PORT clrn (1581:1581:1581) (1557:1557:1557)) + (PORT ena (1253:1253:1253) (1263:1263:1263)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50262,9 +50440,9 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~0) (DELAY (ABSOLUTE - (PORT dataa (251:251:251) (340:340:340)) - (PORT datab (251:251:251) (335:335:335)) - (PORT datad (216:216:216) (283:283:283)) + (PORT dataa (915:915:915) (998:998:998)) + (PORT datab (253:253:253) (338:338:338)) + (PORT datad (224:224:224) (295:295:295)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -50277,12 +50455,13 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~1) (DELAY (ABSOLUTE - (PORT dataa (912:912:912) (985:985:985)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datad (182:182:182) (211:211:211)) + (PORT dataa (249:249:249) (340:340:340)) + (PORT datab (259:259:259) (348:348:348)) + (PORT datac (174:174:174) (207:207:207)) + (PORT datad (180:180:180) (210:210:210)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50310,9 +50489,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[0\]) (DELAY (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) + (PORT clk (1911:1911:1911) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50326,8 +50505,8 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (345:345:345)) - (PORT datab (251:251:251) (337:337:337)) + (PORT dataa (406:406:406) (480:480:480)) + (PORT datab (251:251:251) (336:336:336)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datab combout (344:344:344) (369:369:369)) @@ -50341,9 +50520,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) + (PORT clk (1911:1911:1911) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50357,7 +50536,7 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]\~7) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (343:343:343)) + (PORT dataa (253:253:253) (344:344:344)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -50371,9 +50550,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) + (PORT clk (1911:1911:1911) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50387,9 +50566,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[3\]\~9) (DELAY (ABSOLUTE - (PORT datab (252:252:252) (338:338:338)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (254:254:254) (346:346:346)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -50401,66 +50580,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) + (PORT clk (1911:1911:1911) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) - (DELAY - (ABSOLUTE - (PORT datab (251:251:251) (337:337:337)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT datad (226:226:226) (299:299:299)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50474,8 +50596,8 @@ (INSTANCE ula_\|i2c_loader_\|WideAnd0\~0) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (343:343:343)) - (PORT datab (253:253:253) (339:339:339)) + (PORT dataa (252:252:252) (342:342:342)) + (PORT datab (264:264:264) (347:347:347)) (PORT datac (223:223:223) (302:302:302)) (PORT datad (225:225:225) (297:297:297)) (IOPATH dataa combout (324:324:324) (328:328:328)) @@ -50485,29 +50607,104 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (338:338:338)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) + (DELAY + (ABSOLUTE + (PORT datad (226:226:226) (298:298:298)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|WideAnd0) (DELAY (ABSOLUTE - (PORT datab (250:250:250) (334:334:334)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (225:225:225) (296:296:296)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (202:202:202) (242:242:242)) + (PORT datac (224:224:224) (305:305:305)) + (PORT datad (225:225:225) (295:295:295)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|scl_out\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1547:1547:1547)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1560:1560:1560)) + (PORT ena (1023:1023:1023) (976:976:976)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2c_loader_\|state\.Idle) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) + (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) - (PORT ena (1428:1428:1428) (1403:1403:1403)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (1502:1502:1502) (1473:1473:1473)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50522,7 +50719,7 @@ (INSTANCE ula_\|i2c_loader_\|phase\~0) (DELAY (ABSOLUTE - (PORT datad (245:245:245) (317:317:317)) + (PORT datad (410:410:410) (477:477:477)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50533,10 +50730,10 @@ (INSTANCE ula_\|i2c_loader_\|phase\[0\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) + (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) - (PORT ena (1428:1428:1428) (1403:1403:1403)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (1502:1502:1502) (1473:1473:1473)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50551,8 +50748,8 @@ (INSTANCE ula_\|i2c_loader_\|phase\~1) (DELAY (ABSOLUTE - (PORT datab (333:333:333) (440:440:440)) - (PORT datad (247:247:247) (319:319:319)) + (PORT datab (453:453:453) (522:522:522)) + (PORT datad (395:395:395) (465:465:465)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -50562,12 +50759,146 @@ (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2c_loader_\|phase\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (PORT ena (881:881:881) (820:820:820)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|Mux42\~0) + (DELAY + (ABSOLUTE + (PORT datab (455:455:455) (531:531:531)) + (PORT datac (266:266:266) (353:353:353)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbyte\~0) + (DELAY + (ABSOLUTE + (PORT datab (471:471:471) (542:542:542)) + (PORT datac (574:574:574) (630:630:630)) + (PORT datad (871:871:871) (934:934:934)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~4) + (DELAY + (ABSOLUTE + (PORT datad (701:701:701) (764:764:764)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbyte\~4) + (DELAY + (ABSOLUTE + (PORT dataa (420:420:420) (494:494:494)) + (PORT datab (652:652:652) (716:716:716)) + (PORT datad (718:718:718) (781:781:781)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) (DELAY (ABSOLUTE (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) - (PORT ena (1428:1428:1428) (1403:1403:1403)) + (PORT clrn (1566:1566:1566) (1560:1560:1560)) + (PORT ena (820:820:820) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (469:469:469) (541:541:541)) + (PORT datac (593:593:593) (652:652:652)) + (PORT datad (281:281:281) (362:362:362)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (247:247:247)) + (PORT datab (605:605:605) (665:665:665)) + (PORT datac (628:628:628) (682:682:682)) + (PORT datad (856:856:856) (911:911:911)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (687:687:687)) + (PORT datab (642:642:642) (659:659:659)) + (PORT datac (634:634:634) (701:701:701)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1904:1904:1904) (1924:1924:1924)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1568:1568:1568) (1561:1561:1561)) + (PORT ena (1204:1204:1204) (1189:1189:1189)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50582,31 +50913,69 @@ (INSTANCE ula_\|i2c_loader_\|nbit\~5) (DELAY (ABSOLUTE - (PORT dataa (636:636:636) (709:709:709)) + (PORT dataa (739:739:739) (807:807:807)) + (PORT datad (388:388:388) (450:450:450)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) (DELAY (ABSOLUTE - (PORT datab (307:307:307) (404:404:404)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT clk (1534:1534:1534) (1548:1548:1548)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1568:1568:1568) (1561:1561:1561)) + (PORT ena (1235:1235:1235) (1239:1239:1239)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (344:344:344)) + (PORT datab (262:262:262) (351:351:351)) + (PORT datad (381:381:381) (445:445:445)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|Mux42\~0) + (INSTANCE ula_\|i2c_loader_\|state\~27) (DELAY (ABSOLUTE - (PORT datac (700:700:700) (774:774:774)) - (PORT datad (677:677:677) (746:746:746)) + (PORT datab (456:456:456) (528:528:528)) + (PORT datac (269:269:269) (358:358:358)) + (PORT datad (668:668:668) (706:706:706)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~24) + (DELAY + (ABSOLUTE + (PORT datab (473:473:473) (541:541:541)) + (PORT datac (595:595:595) (653:653:653)) + (PORT datad (282:282:282) (363:363:363)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50614,28 +50983,174 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\~4) + (INSTANCE ula_\|i2c_loader_\|state\~26) (DELAY (ABSOLUTE - (PORT dataa (286:286:286) (381:381:381)) - (PORT datab (336:336:336) (443:443:443)) - (PORT datad (634:634:634) (704:704:704)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT datab (457:457:457) (530:530:530)) + (PORT datac (268:268:268) (356:356:356)) + (PORT datad (336:336:336) (359:359:359)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) + (DELAY + (ABSOLUTE + (PORT datab (200:200:200) (239:239:239)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Data) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (688:688:688) (708:708:708)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT sload (875:875:875) (1000:1000:1000)) + (PORT ena (1502:1502:1502) (1473:1473:1473)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~0) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (809:809:809)) + (PORT datab (260:260:260) (350:350:350)) + (PORT datad (384:384:384) (449:449:449)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1548:1548:1548)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1568:1568:1568) (1561:1561:1561)) + (PORT ena (1235:1235:1235) (1239:1239:1239)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (344:344:344)) + (PORT datab (407:407:407) (482:482:482)) + (PORT datac (887:887:887) (938:938:938)) + (PORT datad (236:236:236) (314:314:314)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) + (DELAY + (ABSOLUTE + (PORT dataa (273:273:273) (364:364:364)) + (PORT datab (308:308:308) (401:401:401)) + (PORT datac (572:572:572) (628:628:628)) + (PORT datad (619:619:619) (673:673:673)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (690:690:690)) + (PORT datab (661:661:661) (732:732:732)) + (PORT datac (627:627:627) (680:680:680)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (667:667:667)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datad (857:857:857) (913:913:913)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Ack) + (DELAY + (ABSOLUTE + (PORT clk (1927:1927:1927) (1950:1950:1950)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~7) (DELAY (ABSOLUTE - (PORT datab (290:290:290) (381:381:381)) - (PORT datac (578:578:578) (623:623:623)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datac (668:668:668) (736:736:736)) + (PORT datad (436:436:436) (501:501:501)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -50653,13 +51168,13 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (284:284:284) (379:379:379)) - (PORT datab (272:272:272) (359:359:359)) - (PORT datac (301:301:301) (403:403:403)) - (PORT datad (516:516:516) (513:513:513)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (418:418:418) (494:494:494)) + (PORT datab (754:754:754) (826:826:826)) + (PORT datac (239:239:239) (316:316:316)) + (PORT datad (508:508:508) (502:502:502)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50669,13 +51184,13 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~2) (DELAY (ABSOLUTE - (PORT dataa (662:662:662) (747:747:747)) - (PORT datab (653:653:653) (670:670:670)) - (PORT datac (172:172:172) (206:206:206)) + (PORT dataa (347:347:347) (376:376:376)) + (PORT datab (646:646:646) (667:667:667)) + (PORT datac (618:618:618) (676:676:676)) (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50685,30 +51200,30 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~3) (DELAY (ABSOLUTE - (PORT datab (835:835:835) (857:857:857)) - (PORT datac (423:423:423) (492:492:492)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (633:633:633) (712:712:712)) + (PORT datab (626:626:626) (641:641:641)) + (PORT datad (174:174:174) (201:201:201)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) + (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]) (DELAY (ABSOLUTE (PORT clk (1532:1532:1532) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) + (PORT asdata (689:689:689) (712:712:712)) + (PORT clrn (1566:1566:1566) (1560:1560:1560)) (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -50717,12 +51232,12 @@ (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) (DELAY (ABSOLUTE - (PORT dataa (677:677:677) (755:755:755)) - (PORT datab (713:713:713) (770:770:770)) - (PORT datac (253:253:253) (337:337:337)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (471:471:471) (540:540:540)) + (PORT datac (593:593:593) (650:650:650)) + (PORT datad (278:278:278) (360:360:360)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -50731,11 +51246,11 @@ (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) (DELAY (ABSOLUTE - (PORT dataa (596:596:596) (620:620:620)) - (PORT datab (263:263:263) (314:314:314)) - (PORT datad (341:341:341) (360:360:360)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (PORT dataa (663:663:663) (689:689:689)) + (PORT datab (639:639:639) (655:655:655)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50746,9 +51261,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Stop) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1927:1927:1927) (1950:1950:1950)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50759,15 +51274,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) (DELAY (ABSOLUTE - (PORT dataa (291:291:291) (389:389:389)) - (PORT datab (261:261:261) (350:350:350)) - (PORT datac (232:232:232) (318:318:318)) - (PORT datad (567:567:567) (616:616:616)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (272:272:272) (362:362:362)) + (PORT datab (886:886:886) (951:951:951)) + (PORT datac (804:804:804) (848:848:848)) + (PORT datad (872:872:872) (930:930:930)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50775,112 +51290,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~0) + (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) (DELAY (ABSOLUTE - (PORT dataa (637:637:637) (710:710:710)) - (PORT datab (267:267:267) (356:356:356)) - (PORT datad (234:234:234) (311:311:311)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT datab (296:296:296) (389:389:389)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT ena (1191:1191:1191) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~0) - (DELAY - (ABSOLUTE - (PORT dataa (259:259:259) (351:351:351)) - (PORT datab (249:249:249) (335:335:335)) - (PORT datac (602:602:602) (665:665:665)) - (PORT datad (238:238:238) (316:316:316)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (399:399:399)) - (PORT datab (370:370:370) (392:392:392)) - (PORT datac (920:920:920) (977:977:977)) - (PORT datad (327:327:327) (351:351:351)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (247:247:247)) - (PORT datab (562:562:562) (591:591:591)) - (PORT datad (443:443:443) (515:515:515)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Ack) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (285:285:285) (380:380:380)) - (PORT datab (272:272:272) (356:356:356)) - (PORT datac (302:302:302) (404:404:404)) - (PORT datad (517:517:517) (510:510:510)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (596:596:596) (655:655:655)) + (PORT datab (936:936:936) (980:980:980)) + (PORT datac (623:623:623) (676:676:676)) + (PORT datad (708:708:708) (690:690:690)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50890,13 +51321,13 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~18) (DELAY (ABSOLUTE - (PORT dataa (416:416:416) (489:489:489)) - (PORT datab (587:587:587) (640:640:640)) - (PORT datac (850:850:850) (859:859:859)) - (PORT datad (309:309:309) (325:325:325)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (604:604:604) (640:640:640)) + (PORT datab (457:457:457) (514:514:514)) + (PORT datac (786:786:786) (833:833:833)) + (PORT datad (176:176:176) (203:203:203)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50906,12 +51337,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1898:1898:1898) (1914:1914:1914)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1124:1124:1124) (1148:1148:1148)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sload (1067:1067:1067) (1036:1036:1036)) - (PORT ena (794:794:794) (792:792:792)) + (PORT asdata (2650:2650:2650) (2671:2671:2671)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT sload (1538:1538:1538) (1516:1516:1516)) + (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50928,7 +51359,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]\~10) (DELAY (ABSOLUTE - (PORT datab (297:297:297) (392:392:392)) + (PORT datab (293:293:293) (394:394:394)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -50942,12 +51373,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1898:1898:1898) (1914:1914:1914)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1125:1125:1125) (1149:1149:1149)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sload (1067:1067:1067) (1036:1036:1036)) - (PORT ena (794:794:794) (792:792:792)) + (PORT asdata (2650:2650:2650) (2671:2671:2671)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT sload (1538:1538:1538) (1516:1516:1516)) + (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50964,9 +51395,9 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]\~12) (DELAY (ABSOLUTE - (PORT datab (288:288:288) (380:380:380)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (300:300:300) (412:412:412)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -50978,11 +51409,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1898:1898:1898) (1914:1914:1914)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sload (1067:1067:1067) (1036:1036:1036)) - (PORT ena (794:794:794) (792:792:792)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT sload (1538:1538:1538) (1516:1516:1516)) + (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50999,7 +51430,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]\~14) (DELAY (ABSOLUTE - (PORT datab (306:306:306) (403:403:403)) + (PORT datab (299:299:299) (395:395:395)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -51013,12 +51444,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1898:1898:1898) (1914:1914:1914)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1125:1125:1125) (1150:1150:1150)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sload (1067:1067:1067) (1036:1036:1036)) - (PORT ena (794:794:794) (792:792:792)) + (PORT asdata (2652:2652:2652) (2668:2668:2668)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT sload (1538:1538:1538) (1516:1516:1516)) + (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51035,29 +51466,13 @@ (INSTANCE ula_\|i2c_loader_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (426:426:426) (508:508:508)) - (PORT datab (298:298:298) (392:392:392)) - (PORT datac (277:277:277) (365:365:365)) - (PORT datad (279:279:279) (363:363:363)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (798:798:798)) - (PORT datab (261:261:261) (350:350:350)) - (PORT datac (704:704:704) (778:778:778)) - (PORT datad (260:260:260) (337:337:337)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (430:430:430) (520:520:520)) + (PORT datab (294:294:294) (394:394:394)) + (PORT datac (269:269:269) (375:375:375)) + (PORT datad (277:277:277) (359:359:359)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51067,7 +51482,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]\~16) (DELAY (ABSOLUTE - (PORT dataa (308:308:308) (413:413:413)) + (PORT dataa (298:298:298) (405:405:405)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -51078,11 +51493,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1898:1898:1898) (1914:1914:1914)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sload (1067:1067:1067) (1036:1036:1036)) - (PORT ena (794:794:794) (792:792:792)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT sload (1538:1538:1538) (1516:1516:1516)) + (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51096,29 +51511,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~3) (DELAY (ABSOLUTE - (PORT datab (622:622:622) (640:640:640)) - (PORT datac (335:335:335) (357:357:357)) - (PORT datad (658:658:658) (710:710:710)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~2) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (267:267:267)) - (PORT datab (286:286:286) (376:376:376)) - (PORT datac (231:231:231) (314:314:314)) - (PORT datad (487:487:487) (489:489:489)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (349:349:349) (374:374:374)) + (PORT datad (401:401:401) (464:464:464)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51126,15 +51525,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) + (INSTANCE ula_\|i2c_loader_\|scl_out\~0) (DELAY (ABSOLUTE - (PORT dataa (345:345:345) (374:374:374)) - (PORT datab (266:266:266) (320:320:320)) - (PORT datac (261:261:261) (352:352:352)) - (PORT datad (421:421:421) (491:491:491)) + (PORT dataa (409:409:409) (485:485:485)) + (PORT datab (477:477:477) (546:546:546)) + (PORT datad (869:869:869) (920:920:920)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~4) + (DELAY + (ABSOLUTE + (PORT dataa (553:553:553) (572:572:572)) + (PORT datab (273:273:273) (357:357:357)) + (PORT datac (255:255:255) (340:340:340)) + (PORT datad (668:668:668) (704:704:704)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~5) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (432:432:432) (515:515:515)) + (PORT datac (261:261:261) (346:346:346)) + (PORT datad (220:220:220) (258:258:258)) (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51142,14 +51571,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~3) + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~6) (DELAY (ABSOLUTE - (PORT dataa (343:343:343) (380:380:380)) - (PORT datab (590:590:590) (613:613:613)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (910:910:910) (941:941:941)) + (PORT datab (630:630:630) (649:649:649)) + (PORT datad (173:173:173) (200:200:200)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51160,9 +51589,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51176,11 +51605,11 @@ (INSTANCE ula_\|i2c_loader_\|state\~25) (DELAY (ABSOLUTE - (PORT dataa (264:264:264) (356:356:356)) - (PORT datab (267:267:267) (321:321:321)) - (PORT datad (419:419:419) (488:488:488)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT dataa (249:249:249) (302:302:302)) + (PORT datab (274:274:274) (359:359:359)) + (PORT datad (405:405:405) (476:476:476)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51189,277 +51618,12 @@ (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2c_loader_\|state\.Start) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1192:1192:1192) (1154:1154:1154)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\~0) - (DELAY - (ABSOLUTE - (PORT datab (330:330:330) (437:437:437)) - (PORT datad (630:630:630) (700:700:700)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) - (PORT ena (820:820:820) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (749:749:749)) - (PORT datac (684:684:684) (733:733:733)) - (PORT datad (441:441:441) (514:514:514)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1033:1033:1033) (1086:1086:1086)) - (PORT datab (486:486:486) (561:561:561)) - (PORT datac (255:255:255) (338:338:338)) - (PORT datad (669:669:669) (726:726:726)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (590:590:590) (648:648:648)) - (PORT datad (326:326:326) (348:348:348)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (387:387:387)) - (PORT datab (262:262:262) (314:314:314)) - (PORT datac (556:556:556) (578:578:578)) - (PORT datad (424:424:424) (491:491:491)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1900:1900:1900) (1919:1919:1919)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT ena (1160:1160:1160) (1135:1135:1135)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~6) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (707:707:707)) - (PORT datad (241:241:241) (319:319:319)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) (DELAY (ABSOLUTE (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT ena (1191:1191:1191) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~1) - (DELAY - (ABSOLUTE - (PORT dataa (260:260:260) (355:355:355)) - (PORT datab (252:252:252) (338:338:338)) - (PORT datad (241:241:241) (319:319:319)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~27) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (793:793:793)) - (PORT datac (701:701:701) (775:775:775)) - (PORT datad (486:486:486) (488:488:488)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~24) - (DELAY - (ABSOLUTE - (PORT dataa (677:677:677) (753:753:753)) - (PORT datab (714:714:714) (770:770:770)) - (PORT datac (251:251:251) (332:332:332)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~26) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (798:798:798)) - (PORT datac (702:702:702) (777:777:777)) - (PORT datad (347:347:347) (368:368:368)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (248:248:248)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Data) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (578:578:578) (625:625:625)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT sload (875:875:875) (1003:1003:1003)) - (PORT ena (1192:1192:1192) (1154:1154:1154)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|scl_out\~0) - (DELAY - (ABSOLUTE - (PORT datab (288:288:288) (379:379:379)) - (PORT datac (607:607:607) (657:657:657)) - (PORT datad (233:233:233) (310:310:310)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|scl_out\~_Duplicate_1) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) - (PORT ena (1428:1428:1428) (1403:1403:1403)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (1502:1502:1502) (1473:1473:1473)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51474,12 +51638,12 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~1) (DELAY (ABSOLUTE - (PORT dataa (661:661:661) (746:746:746)) - (PORT datab (330:330:330) (435:435:435)) - (PORT datac (260:260:260) (348:348:348)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (246:246:246) (333:333:333)) + (PORT datab (701:701:701) (768:768:768)) + (PORT datac (620:620:620) (679:679:679)) + (PORT datad (717:717:717) (779:779:779)) + (IOPATH dataa combout (341:341:341) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51490,11 +51654,11 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~2) (DELAY (ABSOLUTE - (PORT dataa (650:650:650) (670:670:670)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datad (630:630:630) (699:699:699)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (202:202:202) (247:247:247)) + (PORT datac (617:617:617) (676:676:676)) + (PORT datad (204:204:204) (234:234:234)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51506,8 +51670,8 @@ (ABSOLUTE (PORT clk (1473:1473:1473) (1495:1495:1495)) (PORT d (958:958:958) (1002:1002:1002)) - (PORT aload (1710:1710:1710) (1775:1775:1775)) - (PORT ena (885:885:885) (884:884:884)) + (PORT aload (1697:1697:1697) (1760:1760:1760)) + (PORT ena (723:723:723) (714:714:714)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) (IOPATH (posedge aload) q (513:513:513) (508:508:508)) ) @@ -51526,8 +51690,8 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) - (PORT ena (1428:1428:1428) (1403:1403:1403)) + (PORT clrn (1566:1566:1566) (1560:1560:1560)) + (PORT ena (1023:1023:1023) (976:976:976)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51537,29 +51701,29 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) - (DELAY - (ABSOLUTE - (PORT datac (887:887:887) (940:940:940)) - (PORT datad (610:610:610) (673:673:673)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|Mux35\~0) (DELAY (ABSOLUTE - (PORT dataa (442:442:442) (520:520:520)) - (PORT datab (457:457:457) (520:520:520)) - (PORT datac (391:391:391) (449:449:449)) - (PORT datad (395:395:395) (456:456:456)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT dataa (431:431:431) (516:516:516)) + (PORT datab (290:290:290) (389:389:389)) + (PORT datac (264:264:264) (368:368:368)) + (PORT datad (275:275:275) (353:353:353)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) + (DELAY + (ABSOLUTE + (PORT datac (616:616:616) (672:672:672)) + (PORT datad (868:868:868) (917:917:917)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51567,56 +51731,76 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) (DELAY (ABSOLUTE - (PORT dataa (306:306:306) (409:409:409)) - (PORT datab (298:298:298) (389:389:389)) - (PORT datac (278:278:278) (370:370:370)) - (PORT datad (262:262:262) (338:338:338)) + (PORT dataa (433:433:433) (517:517:517)) + (PORT datab (292:292:292) (393:393:393)) + (PORT datac (276:276:276) (370:370:370)) + (PORT datad (273:273:273) (355:355:355)) (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) (DELAY (ABSOLUTE - (PORT datac (274:274:274) (369:369:369)) - (PORT datad (260:260:260) (337:337:337)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (302:302:302) (419:419:419)) + (PORT datab (584:584:584) (592:592:592)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (269:269:269) (349:349:349)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) (DELAY (ABSOLUTE - (PORT dataa (203:203:203) (248:248:248)) - (PORT datab (307:307:307) (404:404:404)) - (PORT datac (278:278:278) (370:370:370)) - (PORT datad (198:198:198) (224:224:224)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (303:303:303) (418:418:418)) + (PORT datab (294:294:294) (385:385:385)) + (PORT datac (278:278:278) (369:369:369)) + (PORT datad (274:274:274) (355:355:355)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~24) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) (DELAY (ABSOLUTE - (PORT datab (456:456:456) (520:520:520)) - (PORT datac (890:890:890) (943:943:943)) - (PORT datad (414:414:414) (478:478:478)) + (PORT dataa (557:557:557) (586:586:586)) + (PORT datab (293:293:293) (393:393:393)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (269:269:269) (349:349:349)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (493:493:493) (580:580:580)) + (PORT datac (679:679:679) (744:744:744)) + (PORT datad (662:662:662) (723:723:723)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -51628,11 +51812,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~6) (DELAY (ABSOLUTE - (PORT dataa (707:707:707) (795:795:795)) - (PORT datac (702:702:702) (777:777:777)) - (PORT datad (261:261:261) (341:341:341)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (280:280:280) (368:368:368)) + (PORT datac (265:265:265) (353:353:353)) + (PORT datad (417:417:417) (491:491:491)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51642,13 +51826,13 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~7) (DELAY (ABSOLUTE - (PORT dataa (294:294:294) (393:393:393)) - (PORT datab (263:263:263) (313:313:313)) - (PORT datac (173:173:173) (205:205:205)) - (PORT datad (350:350:350) (370:370:370)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (365:365:365) (400:400:400)) + (PORT datac (264:264:264) (352:352:352)) + (PORT datad (215:215:215) (253:253:253)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51658,11 +51842,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~8) (DELAY (ABSOLUTE - (PORT datab (447:447:447) (530:530:530)) - (PORT datac (557:557:557) (581:581:581)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (910:910:910) (936:936:936)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datad (410:410:410) (480:480:480)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51672,11 +51856,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sclr (1104:1104:1104) (1198:1198:1198)) - (PORT ena (1397:1397:1397) (1366:1366:1366)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT sclr (1298:1298:1298) (1370:1370:1370)) + (PORT ena (949:949:949) (938:938:938)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51689,46 +51873,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~24) (DELAY (ABSOLUTE - (PORT dataa (305:305:305) (408:408:408)) - (PORT datab (305:305:305) (398:398:398)) - (PORT datac (278:278:278) (369:369:369)) - (PORT datad (262:262:262) (338:338:338)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (397:397:397)) - (PORT datab (373:373:373) (401:401:401)) - (PORT datac (390:390:390) (448:448:448)) - (PORT datad (413:413:413) (480:480:480)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (334:334:334)) - (PORT datac (893:893:893) (946:946:946)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (629:629:629) (656:656:656)) + (PORT datac (457:457:457) (542:542:542)) + (PORT datad (219:219:219) (289:289:289)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51738,13 +51890,13 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~10) (DELAY (ABSOLUTE - (PORT dataa (712:712:712) (775:775:775)) - (PORT datab (482:482:482) (560:560:560)) - (PORT datac (588:588:588) (650:650:650)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (428:428:428) (516:516:516)) + (PORT datab (365:365:365) (396:396:396)) + (PORT datac (266:266:266) (352:352:352)) + (PORT datad (420:420:420) (487:487:487)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51754,13 +51906,27 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~11) (DELAY (ABSOLUTE - (PORT dataa (1032:1032:1032) (1083:1083:1083)) - (PORT datab (561:561:561) (587:587:587)) - (PORT datac (921:921:921) (976:976:976)) + (PORT dataa (247:247:247) (300:300:300)) + (PORT datab (281:281:281) (369:369:369)) + (PORT datac (258:258:258) (346:346:346)) (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (940:940:940)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datad (409:409:409) (478:478:478)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51770,10 +51936,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT ena (1207:1207:1207) (1188:1188:1188)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (961:961:961) (968:968:968)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51785,45 +51951,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) (DELAY (ABSOLUTE - (PORT dataa (305:305:305) (410:410:410)) - (PORT datab (303:303:303) (399:399:399)) - (PORT datac (274:274:274) (364:364:364)) - (PORT datad (268:268:268) (349:349:349)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) - (DELAY - (ABSOLUTE - (PORT dataa (445:445:445) (522:522:522)) - (PORT datab (419:419:419) (491:491:491)) - (PORT datac (308:308:308) (330:330:330)) - (PORT datad (197:197:197) (222:222:222)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (337:337:337)) - (PORT datac (886:886:886) (938:938:938)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (304:304:304) (307:307:307)) + (PORT dataa (632:632:632) (649:649:649)) + (PORT datac (456:456:456) (542:542:542)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51834,10 +51968,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[2\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT ena (1207:1207:1207) (1188:1188:1188)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (961:961:961) (968:968:968)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51849,13 +51983,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) (DELAY (ABSOLUTE - (PORT dataa (424:424:424) (505:505:505)) - (PORT datab (298:298:298) (389:389:389)) - (PORT datac (273:273:273) (368:368:368)) - (PORT datad (278:278:278) (358:358:358)) + (PORT dataa (302:302:302) (418:418:418)) + (PORT datab (293:293:293) (393:393:393)) + (PORT datac (277:277:277) (370:370:370)) + (PORT datad (274:274:274) (355:355:355)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -51865,31 +51999,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) (DELAY (ABSOLUTE - (PORT dataa (441:441:441) (526:526:526)) - (PORT datab (454:454:454) (519:519:519)) - (PORT datac (501:501:501) (509:509:509)) - (PORT datad (352:352:352) (369:369:369)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (304:304:304) (418:418:418)) + (PORT datac (279:279:279) (373:373:373)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (625:625:625)) + (PORT datab (349:349:349) (382:382:382)) + (PORT datac (681:681:681) (740:740:740)) + (PORT datad (662:662:662) (720:720:720)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~27) (DELAY (ABSOLUTE - (PORT dataa (639:639:639) (715:715:715)) - (PORT datab (244:244:244) (327:327:327)) - (PORT datac (888:888:888) (940:940:940)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (247:247:247) (334:334:334)) + (PORT datab (831:831:831) (881:881:881)) + (PORT datac (460:460:460) (539:539:539)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51900,10 +52046,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT ena (1207:1207:1207) (1188:1188:1188)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (961:961:961) (968:968:968)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51915,16 +52061,48 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~25) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (679:679:679) (734:734:734)) - (PORT datac (620:620:620) (667:667:667)) - (PORT datad (364:364:364) (423:423:423)) + (PORT dataa (303:303:303) (418:418:418)) + (PORT datab (295:295:295) (395:395:395)) + (PORT datac (277:277:277) (371:371:371)) + (PORT datad (270:270:270) (351:351:351)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) + (DELAY + (ABSOLUTE + (PORT dataa (687:687:687) (761:761:761)) + (PORT datab (657:657:657) (669:669:669)) + (PORT datac (679:679:679) (740:740:740)) + (PORT datad (329:329:329) (349:349:349)) (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (335:335:335)) + (PORT datab (832:832:832) (884:884:884)) + (PORT datac (457:457:457) (542:542:542)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51934,10 +52112,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[4\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT ena (1410:1410:1410) (1399:1399:1399)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (961:961:961) (968:968:968)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51949,12 +52127,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~12) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) (DELAY (ABSOLUTE - (PORT dataa (544:544:544) (558:558:558)) - (PORT datab (488:488:488) (559:559:559)) - (PORT datad (364:364:364) (420:420:420)) + (PORT dataa (640:640:640) (656:656:656)) + (PORT datab (622:622:622) (686:686:686)) + (PORT datad (360:360:360) (411:411:411)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -51966,11 +52144,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1530:1530:1530) (1543:1543:1543)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT sload (1203:1203:1203) (1299:1299:1299)) - (PORT ena (812:812:812) (805:805:805)) + (PORT clrn (1564:1564:1564) (1556:1556:1556)) + (PORT sload (1218:1218:1218) (1319:1319:1319)) + (PORT ena (1180:1180:1180) (1175:1175:1175)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51987,11 +52165,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~9) (DELAY (ABSOLUTE - (PORT datab (642:642:642) (706:706:706)) - (PORT datac (893:893:893) (946:946:946)) - (PORT datad (198:198:198) (224:224:224)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (637:637:637) (656:656:656)) + (PORT datac (454:454:454) (537:537:537)) + (PORT datad (386:386:386) (445:445:445)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52001,11 +52179,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sclr (1104:1104:1104) (1198:1198:1198)) - (PORT ena (1207:1207:1207) (1188:1188:1188)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT sclr (1298:1298:1298) (1370:1370:1370)) + (PORT ena (961:961:961) (968:968:968)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52021,8 +52199,8 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]\~5) (DELAY (ABSOLUTE - (PORT datac (887:887:887) (939:939:939)) - (PORT datad (218:218:218) (287:287:287)) + (PORT datac (461:461:461) (545:545:545)) + (PORT datad (221:221:221) (290:290:290)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52033,11 +52211,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sclr (1104:1104:1104) (1198:1198:1198)) - (PORT ena (1397:1397:1397) (1366:1366:1366)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT sclr (1298:1298:1298) (1370:1370:1370)) + (PORT ena (949:949:949) (938:938:938)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52053,12 +52231,12 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~0) (DELAY (ABSOLUTE - (PORT dataa (683:683:683) (742:742:742)) - (PORT datab (416:416:416) (490:490:490)) - (PORT datac (558:558:558) (607:607:607)) - (PORT datad (384:384:384) (444:444:444)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (674:674:674) (733:733:733)) + (PORT datab (883:883:883) (952:952:952)) + (PORT datac (406:406:406) (468:468:468)) + (PORT datad (869:869:869) (932:932:932)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52069,13 +52247,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~1) (DELAY (ABSOLUTE - (PORT dataa (537:537:537) (561:561:561)) - (PORT datab (327:327:327) (433:433:433)) - (PORT datac (345:345:345) (368:368:368)) - (PORT datad (517:517:517) (510:510:510)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (342:342:342) (381:381:381)) + (PORT datab (755:755:755) (824:824:824)) + (PORT datac (195:195:195) (229:229:229)) + (PORT datad (507:507:507) (501:501:501)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52085,10 +52263,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~2) (DELAY (ABSOLUTE - (PORT dataa (254:254:254) (345:345:345)) - (PORT datab (329:329:329) (434:434:434)) - (PORT datac (260:260:260) (345:345:345)) - (PORT datad (181:181:181) (208:208:208)) + (PORT dataa (253:253:253) (345:345:345)) + (PORT datab (758:758:758) (822:822:822)) + (PORT datac (668:668:668) (731:731:731)) + (PORT datad (181:181:181) (209:209:209)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -52101,10 +52279,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~3) (DELAY (ABSOLUTE - (PORT dataa (255:255:255) (348:348:348)) - (PORT datab (324:324:324) (431:431:431)) - (PORT datac (261:261:261) (346:346:346)) - (PORT datad (180:180:180) (208:208:208)) + (PORT dataa (254:254:254) (345:345:345)) + (PORT datab (758:758:758) (822:822:822)) + (PORT datac (668:668:668) (732:732:732)) + (PORT datad (181:181:181) (209:209:209)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -52117,10 +52295,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~4) (DELAY (ABSOLUTE - (PORT dataa (663:663:663) (743:743:743)) - (PORT datab (802:802:802) (828:828:828)) + (PORT dataa (830:830:830) (894:894:894)) + (PORT datab (231:231:231) (274:274:274)) (PORT datac (173:173:173) (206:206:206)) - (PORT datad (175:175:175) (201:201:201)) + (PORT datad (175:175:175) (200:200:200)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -52135,8 +52313,8 @@ (ABSOLUTE (PORT clk (1475:1475:1475) (1497:1497:1497)) (PORT d (691:691:691) (730:730:730)) - (PORT aload (1726:1726:1726) (1792:1792:1792)) - (PORT ena (1272:1272:1272) (1294:1294:1294)) + (PORT aload (1698:1698:1698) (1763:1763:1763)) + (PORT ena (942:942:942) (938:938:938)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) (IOPATH (posedge aload) q (513:513:513) (508:508:508)) ) @@ -52148,6 +52326,2173 @@ (HOLD ena (posedge clk) (101:101:101)) ) ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2334:2334:2334) (2334:2334:2334)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1890:1890:1890) (1874:1874:1874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux38\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1565:1565:1565) (1641:1641:1641)) + (PORT datab (1300:1300:1300) (1343:1343:1343)) + (PORT datad (181:181:181) (212:212:212)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rd_pending) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (248:248:248) (334:334:334)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[3\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (256:256:256)) + (PORT datab (969:969:969) (1051:1051:1051)) + (PORT datac (661:661:661) (684:684:684)) + (PORT datad (1347:1347:1347) (1447:1447:1447)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (671:671:671) (734:734:734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (248:248:248) (333:333:333)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (671:671:671) (734:734:734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[2\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (249:249:249) (335:335:335)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (671:671:671) (734:734:734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[3\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (343:343:343)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (671:671:671) (734:734:734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[4\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (336:336:336)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (671:671:671) (734:734:734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[5\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (345:345:345)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (671:671:671) (734:734:734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[6\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (343:343:343)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (671:671:671) (734:734:734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[7\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (338:338:338)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (671:671:671) (734:734:734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (343:343:343)) + (PORT datab (251:251:251) (335:335:335)) + (PORT datac (223:223:223) (303:303:303)) + (PORT datad (225:225:225) (298:298:298)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[8\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (338:338:338)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (671:671:671) (734:734:734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (255:255:255) (347:347:347)) + (PORT datab (254:254:254) (340:340:340)) + (PORT datac (226:226:226) (306:306:306)) + (PORT datad (228:228:228) (300:300:300)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[9\]\~30) + (DELAY + (ABSOLUTE + (PORT datad (226:226:226) (299:299:299)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (671:671:671) (734:734:734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (374:374:374)) + (PORT datab (252:252:252) (336:336:336)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (225:225:225) (296:296:296)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~8) + (DELAY + (ABSOLUTE + (PORT datab (1384:1384:1384) (1487:1487:1487)) + (PORT datac (941:941:941) (1018:1018:1018)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (259:259:259)) + (PORT datab (688:688:688) (717:717:717)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_pending) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (774:774:774) (867:867:867)) + (PORT datab (765:765:765) (851:851:851)) + (PORT datac (642:642:642) (726:726:726)) + (PORT datad (862:862:862) (889:889:889)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (928:928:928)) + (PORT datab (1028:1028:1028) (1104:1104:1104)) + (PORT datac (1269:1269:1269) (1392:1392:1392)) + (PORT datad (571:571:571) (585:585:585)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (928:928:928)) + (PORT datab (1028:1028:1028) (1103:1103:1103)) + (PORT datac (1269:1269:1269) (1391:1391:1391)) + (PORT datad (571:571:571) (585:585:585)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux4\~3) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (687:687:687)) + (PORT datab (305:305:305) (398:398:398)) + (PORT datad (604:604:604) (636:636:636)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.act_row\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1303:1303:1303) (1433:1433:1433)) + (PORT datab (1067:1067:1067) (1184:1184:1184)) + (PORT datac (1412:1412:1412) (1458:1458:1458)) + (PORT datad (995:995:995) (1084:1084:1084)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~2) + (DELAY + (ABSOLUTE + (PORT datac (264:264:264) (345:345:345)) + (PORT datad (285:285:285) (364:364:364)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.act_row\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (364:364:364) (399:399:399)) + (PORT datac (1029:1029:1029) (1132:1132:1132)) + (PORT datad (996:996:996) (1087:1087:1087)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1547:1547:1547)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (966:966:966) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1547:1547:1547)) + (PORT asdata (1576:1576:1576) (1606:1606:1606)) + (PORT ena (966:966:966) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.act_row\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1215:1215:1215) (1258:1258:1258)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1547:1547:1547)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (966:966:966) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal7\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1264:1264:1264) (1305:1305:1305)) + (PORT datab (1250:1250:1250) (1293:1293:1293)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1547:1547:1547)) + (PORT asdata (1323:1323:1323) (1390:1390:1390)) + (PORT ena (966:966:966) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1547:1547:1547)) + (PORT asdata (3043:3043:3043) (3212:3212:3212)) + (PORT ena (966:966:966) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2732:2732:2732) (2911:2911:2911)) + (PORT datab (1007:1007:1007) (1081:1081:1081)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal7\~2) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (468:468:468)) + (PORT datab (252:252:252) (337:337:337)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (183:183:183) (213:213:213)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1442:1442:1442) (1496:1496:1496)) + (PORT datab (1034:1034:1034) (1124:1124:1124)) + (PORT datac (1028:1028:1028) (1131:1131:1131)) + (PORT datad (1030:1030:1030) (1145:1145:1145)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1281:1281:1281) (1388:1388:1388)) + (PORT datac (582:582:582) (600:600:600)) + (PORT datad (340:340:340) (361:361:361)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~2) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (253:253:253)) + (PORT datab (661:661:661) (681:681:681)) + (PORT datad (1354:1354:1354) (1381:1381:1381)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.wr_pending) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~8) + (DELAY + (ABSOLUTE + (PORT datac (1172:1172:1172) (1258:1258:1258)) + (PORT datad (1054:1054:1054) (1165:1165:1165)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~9) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (522:522:522)) + (PORT datab (614:614:614) (638:638:638)) + (PORT datac (668:668:668) (744:744:744)) + (PORT datad (286:286:286) (365:365:365)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1283:1283:1283) (1389:1389:1389)) + (PORT datab (311:311:311) (401:401:401)) + (PORT datac (195:195:195) (229:229:229)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~4) + (DELAY + (ABSOLUTE + (PORT datab (692:692:692) (771:771:771)) + (PORT datac (580:580:580) (597:597:597)) + (PORT datad (1249:1249:1249) (1337:1337:1337)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1279:1279:1279) (1385:1385:1385)) + (PORT datac (1172:1172:1172) (1258:1258:1258)) + (PORT datad (1055:1055:1055) (1166:1166:1166)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~5) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (969:969:969) (1043:1043:1043)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (988:988:988)) + (PORT datac (793:793:793) (832:832:832)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (291:291:291) (388:388:388)) + (PORT datab (724:724:724) (811:811:811)) + (PORT datac (201:201:201) (238:238:238)) + (PORT datad (738:738:738) (805:805:805)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (283:283:283) (378:378:378)) + (PORT datab (299:299:299) (395:395:395)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (739:739:739) (807:807:807)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~6) + (DELAY + (ABSOLUTE + (PORT datab (304:304:304) (399:399:399)) + (PORT datac (605:605:605) (644:644:644)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1305:1305:1305) (1435:1435:1435)) + (PORT datac (1028:1028:1028) (1132:1132:1132)) + (PORT datad (990:990:990) (1085:1085:1085)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~2) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (628:628:628)) + (PORT datab (1461:1461:1461) (1510:1510:1510)) + (PORT datac (668:668:668) (746:746:746)) + (PORT datad (1051:1051:1051) (1164:1164:1164)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~3) + (DELAY + (ABSOLUTE + (PORT datab (828:828:828) (934:934:934)) + (PORT datac (781:781:781) (892:892:892)) + (PORT datad (869:869:869) (909:909:909)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~3) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (1007:1007:1007)) + (PORT datab (297:297:297) (391:391:391)) + (PORT datad (739:739:739) (802:802:802)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~4) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (247:247:247)) + (PORT datab (297:297:297) (388:388:388)) + (PORT datac (870:870:870) (951:951:951)) + (PORT datad (275:275:275) (355:355:355)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~5) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (963:963:963)) + (PORT datab (300:300:300) (396:396:396)) + (PORT datac (690:690:690) (777:777:777)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~0) + (DELAY + (ABSOLUTE + (PORT datab (992:992:992) (1065:1065:1065)) + (PORT datac (1256:1256:1256) (1350:1350:1350)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~7) + (DELAY + (ABSOLUTE + (PORT datac (1261:1261:1261) (1385:1385:1385)) + (PORT datad (986:986:986) (1059:1059:1059)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~10) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (958:958:958)) + (PORT datab (995:995:995) (1070:1070:1070)) + (PORT datac (1256:1256:1256) (1357:1357:1357)) + (PORT datad (685:685:685) (768:768:768)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~1) + (DELAY + (ABSOLUTE + (PORT dataa (421:421:421) (450:450:450)) + (PORT datab (382:382:382) (407:407:407)) + (PORT datac (1029:1029:1029) (1106:1106:1106)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~6) + (DELAY + (ABSOLUTE + (PORT dataa (796:796:796) (830:830:830)) + (PORT datab (344:344:344) (369:369:369)) + (PORT datac (259:259:259) (349:349:349)) + (PORT datad (838:838:838) (843:843:843)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (401:401:401)) + (PORT datab (1287:1287:1287) (1386:1386:1386)) + (PORT datac (961:961:961) (1031:1031:1031)) + (PORT datad (347:347:347) (368:368:368)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~10) + (DELAY + (ABSOLUTE + (PORT dataa (777:777:777) (870:870:870)) + (PORT datab (765:765:765) (853:853:853)) + (PORT datac (766:766:766) (877:877:877)) + (PORT datad (675:675:675) (776:776:776)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~3) + (DELAY + (ABSOLUTE + (PORT dataa (801:801:801) (923:923:923)) + (PORT datab (1024:1024:1024) (1102:1102:1102)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~4) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (389:389:389)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datac (1262:1262:1262) (1383:1383:1383)) + (PORT datad (711:711:711) (805:805:805)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~7) + (DELAY + (ABSOLUTE + (PORT dataa (290:290:290) (388:388:388)) + (PORT datab (775:775:775) (845:845:845)) + (PORT datac (870:870:870) (953:953:953)) + (PORT datad (889:889:889) (964:964:964)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~8) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (378:378:378)) + (PORT datab (297:297:297) (392:392:392)) + (PORT datac (689:689:689) (775:775:775)) + (PORT datad (275:275:275) (357:357:357)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~5) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (1011:1011:1011)) + (PORT datab (726:726:726) (812:812:812)) + (PORT datac (796:796:796) (836:836:836)) + (PORT datad (274:274:274) (354:354:354)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~6) + (DELAY + (ABSOLUTE + (PORT dataa (431:431:431) (511:511:511)) + (PORT datab (229:229:229) (271:271:271)) + (PORT datac (631:631:631) (672:672:672)) + (PORT datad (914:914:914) (945:945:945)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~9) + (DELAY + (ABSOLUTE + (PORT dataa (284:284:284) (379:379:379)) + (PORT datab (669:669:669) (707:707:707)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~2) + (DELAY + (ABSOLUTE + (PORT datab (1023:1023:1023) (1112:1112:1112)) + (PORT datac (948:948:948) (1070:1070:1070)) + (PORT datad (994:994:994) (1080:1080:1080)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~3) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (396:396:396)) + (PORT datab (1264:1264:1264) (1347:1347:1347)) + (PORT datac (1576:1576:1576) (1655:1655:1655)) + (PORT datad (1570:1570:1570) (1693:1693:1693)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1366:1366:1366) (1517:1517:1517)) + (PORT datab (1478:1478:1478) (1602:1602:1602)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1253:1253:1253) (1313:1313:1313)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~10) + (DELAY + (ABSOLUTE + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (1172:1172:1172) (1258:1258:1258)) + (PORT datad (1055:1055:1055) (1165:1165:1165)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.init_counter\[0\]\~0) + (DELAY + (ABSOLUTE + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1561:1561:1561)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~1) + (DELAY + (ABSOLUTE + (PORT datab (734:734:734) (825:825:825)) + (IOPATH datab cout (446:446:446) (318:318:318)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (282:282:282) (364:364:364)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (264:264:264) (351:351:351)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (437:437:437) (497:497:497)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.init_counter\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (345:345:345) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1553:1553:1553)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (265:265:265) (353:353:353)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (265:265:265) (353:353:353)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~12) + (DELAY + (ABSOLUTE + (PORT datab (264:264:264) (347:347:347)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~14) + (DELAY + (ABSOLUTE + (PORT datab (284:284:284) (367:367:367)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~16) + (DELAY + (ABSOLUTE + (PORT datab (264:264:264) (347:347:347)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~18) + (DELAY + (ABSOLUTE + (PORT datab (264:264:264) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~20) + (DELAY + (ABSOLUTE + (PORT dataa (266:266:266) (352:352:352)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (496:496:496)) + (PORT datab (447:447:447) (515:515:515)) + (PORT datac (387:387:387) (456:456:456)) + (PORT datad (407:407:407) (472:472:472)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT datab (449:449:449) (514:514:514)) + (PORT datac (416:416:416) (481:481:481)) + (PORT datad (244:244:244) (315:315:315)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~22) + (DELAY + (ABSOLUTE + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~24) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (341:341:341)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~26) + (DELAY + (ABSOLUTE + (PORT datab (249:249:249) (333:333:333)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~28) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (344:344:344)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (345:345:345)) + (PORT datab (252:252:252) (337:337:337)) + (PORT datac (224:224:224) (306:306:306)) + (PORT datad (227:227:227) (299:299:299)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (353:353:353) (381:381:381)) + (PORT datad (388:388:388) (451:451:451)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~11) + (DELAY + (ABSOLUTE + (PORT dataa (744:744:744) (865:865:865)) + (PORT datab (304:304:304) (399:399:399)) + (PORT datad (752:752:752) (835:835:835)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~12) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (608:608:608)) + (PORT datab (662:662:662) (714:714:714)) + (PORT datac (1575:1575:1575) (1693:1693:1693)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1512:1512:1512) (1632:1632:1632)) + (PORT datab (1378:1378:1378) (1503:1503:1503)) + (PORT datac (566:566:566) (574:574:574)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (341:341:341) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1278:1278:1278) (1384:1384:1384)) + (PORT datab (1463:1463:1463) (1512:1512:1512)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (862:862:862) (878:878:878)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1217:1217:1217) (1339:1339:1339)) + (PORT datab (975:975:975) (1056:1056:1056)) + (PORT datac (968:968:968) (1042:1042:1042)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~2) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (811:811:811)) + (PORT datac (1118:1118:1118) (1180:1180:1180)) + (PORT datad (873:873:873) (903:903:903)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux72\~0) + (DELAY + (ABSOLUTE + (PORT datab (3068:3068:3068) (3183:3183:3183)) + (PORT datac (902:902:902) (1002:1002:1002)) + (PORT datad (278:278:278) (362:362:362)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux72\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1025:1025:1025) (1085:1085:1085)) + (PORT datab (3069:3069:3069) (3185:3185:3185)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (360:360:360) (379:379:379)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux84\~0) + (DELAY + (ABSOLUTE + (PORT datac (252:252:252) (338:338:338)) + (PORT datad (739:739:739) (806:806:806)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux84\~1) + (DELAY + (ABSOLUTE + (PORT dataa (429:429:429) (511:511:511)) + (PORT datab (303:303:303) (398:398:398)) + (PORT datac (261:261:261) (351:351:351)) + (PORT datad (171:171:171) (197:197:197)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux3\~0) + (DELAY + (ABSOLUTE + (PORT datab (3069:3069:3069) (3191:3191:3191)) + (PORT datac (1141:1141:1141) (1223:1223:1223)) + (PORT datad (280:280:280) (365:365:365)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1024:1024:1024) (1092:1092:1092)) + (PORT datab (3070:3070:3070) (3193:3193:3193)) + (PORT datac (312:312:312) (331:331:331)) + (PORT datad (343:343:343) (365:365:365)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux2\~0) + (DELAY + (ABSOLUTE + (PORT datab (3070:3070:3070) (3185:3185:3185)) + (PORT datac (1121:1121:1121) (1216:1216:1216)) + (PORT datad (283:283:283) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1027:1027:1027) (1093:1093:1093)) + (PORT datab (3073:3073:3073) (3192:3192:3192)) + (PORT datac (347:347:347) (370:370:370)) + (PORT datad (628:628:628) (674:674:674)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux1\~0) + (DELAY + (ABSOLUTE + (PORT datab (3073:3073:3073) (3191:3191:3191)) + (PORT datac (1123:1123:1123) (1214:1214:1214)) + (PORT datad (280:280:280) (360:360:360)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1024:1024:1024) (1093:1093:1093)) + (PORT datab (3064:3064:3064) (3191:3191:3191)) + (PORT datac (609:609:609) (617:617:617)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT datab (3064:3064:3064) (3190:3190:3190)) + (PORT datac (972:972:972) (1042:1042:1042)) + (PORT datad (282:282:282) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1027:1027:1027) (1093:1093:1093)) + (PORT datab (3072:3072:3072) (3191:3191:3191)) + (PORT datac (312:312:312) (340:340:340)) + (PORT datad (608:608:608) (655:655:655)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux73\~0) + (DELAY + (ABSOLUTE + (PORT datab (3066:3066:3066) (3187:3187:3187)) + (PORT datac (1488:1488:1488) (1592:1592:1592)) + (PORT datad (279:279:279) (362:362:362)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux73\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1024:1024:1024) (1090:1090:1090)) + (PORT datab (3063:3063:3063) (3193:3193:3193)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (611:611:611) (659:659:659)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux74\~0) + (DELAY + (ABSOLUTE + (PORT datab (3072:3072:3072) (3189:3189:3189)) + (PORT datac (922:922:922) (1010:1010:1010)) + (PORT datad (277:277:277) (361:361:361)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux74\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1025:1025:1025) (1085:1085:1085)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (3027:3027:3027) (3147:3147:3147)) + (PORT datad (635:635:635) (683:683:683)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux75\~0) + (DELAY + (ABSOLUTE + (PORT datac (1505:1505:1505) (1638:1638:1638)) + (PORT datad (1359:1359:1359) (1405:1405:1405)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|mclk_r\~0) @@ -52162,9 +54507,9 @@ (INSTANCE ula_\|i2s_intf_\|mclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1921:1921:1921) (1947:1947:1947)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1564:1564:1564) (1556:1556:1556)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52179,8 +54524,8 @@ (DELAY (ABSOLUTE (PORT clk (1506:1506:1506) (1528:1528:1528)) - (PORT d (2379:2379:2379) (2282:2282:2282)) - (PORT clrn (1763:1763:1763) (1815:1815:1815)) + (PORT d (976:976:976) (1002:1002:1002)) + (PORT clrn (1750:1750:1750) (1800:1800:1800)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -52195,8 +54540,8 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~1) (DELAY (ABSOLUTE - (PORT dataa (697:697:697) (777:777:777)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (684:684:684) (751:751:751)) + (IOPATH datab cout (446:446:446) (318:318:318)) ) ) ) @@ -52219,10 +54564,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~2) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (277:277:277)) - (PORT datac (174:174:174) (208:208:208)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (210:210:210) (240:240:240)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -52231,9 +54576,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1895:1895:1895) (1917:1917:1917)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1563:1563:1563) (1555:1555:1555)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52247,7 +54592,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~4) (DELAY (ABSOLUTE - (PORT dataa (398:398:398) (479:479:479)) + (PORT dataa (399:399:399) (480:480:480)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52261,8 +54606,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]\~8) (DELAY (ABSOLUTE - (PORT datad (328:328:328) (343:343:343)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (315:315:315) (334:334:334)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -52271,9 +54616,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1915:1915:1915)) + (PORT clk (1895:1895:1895) (1918:1918:1918)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1568:1568:1568)) + (PORT clrn (1564:1564:1564) (1555:1555:1555)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52287,9 +54632,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~6) (DELAY (ABSOLUTE - (PORT datab (391:391:391) (458:458:458)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (435:435:435) (503:503:503)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52301,8 +54646,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]\~7) (DELAY (ABSOLUTE - (PORT datac (345:345:345) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datad (557:557:557) (571:571:571)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -52311,9 +54656,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1921:1921:1921) (1947:1947:1947)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1564:1564:1564) (1556:1556:1556)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52327,7 +54672,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~8) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (337:337:337)) + (PORT datab (252:252:252) (338:338:338)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52341,10 +54686,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~1) (DELAY (ABSOLUTE - (PORT dataa (231:231:231) (281:281:281)) - (PORT datac (172:172:172) (204:204:204)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datad (209:209:209) (240:240:240)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -52353,9 +54698,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1895:1895:1895) (1917:1917:1917)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1563:1563:1563) (1555:1555:1555)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52369,9 +54714,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~10) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (337:337:337)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (438:438:438) (505:505:505)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52383,7 +54728,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]\~6) (DELAY (ABSOLUTE - (PORT datad (175:175:175) (201:201:201)) + (PORT datad (314:314:314) (330:330:330)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52393,9 +54738,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1895:1895:1895) (1918:1918:1918)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1564:1564:1564) (1555:1555:1555)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52409,10 +54754,10 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (400:400:400) (481:481:481)) - (PORT datab (252:252:252) (338:338:338)) - (PORT datac (365:365:365) (427:427:427)) - (PORT datad (227:227:227) (300:300:300)) + (PORT dataa (398:398:398) (480:480:480)) + (PORT datab (250:250:250) (336:336:336)) + (PORT datac (395:395:395) (461:461:461)) + (PORT datad (394:394:394) (457:457:457)) (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -52425,9 +54770,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~12) (DELAY (ABSOLUTE - (PORT dataa (427:427:427) (491:491:491)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (426:426:426) (495:495:495)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52439,7 +54784,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]\~5) (DELAY (ABSOLUTE - (PORT datad (338:338:338) (357:357:357)) + (PORT datad (330:330:330) (348:348:348)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52449,9 +54794,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1895:1895:1895) (1918:1918:1918)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1564:1564:1564) (1555:1555:1555)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52465,7 +54810,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~14) (DELAY (ABSOLUTE - (PORT dataa (438:438:438) (507:507:507)) + (PORT dataa (396:396:396) (477:477:477)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52479,8 +54824,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]\~4) (DELAY (ABSOLUTE - (PORT datad (333:333:333) (348:348:348)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (335:335:335) (357:357:357)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -52489,9 +54834,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1915:1915:1915)) + (PORT clk (1895:1895:1895) (1918:1918:1918)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1568:1568:1568)) + (PORT clrn (1564:1564:1564) (1555:1555:1555)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52505,9 +54850,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~16) (DELAY (ABSOLUTE - (PORT dataa (396:396:396) (467:467:467)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (253:253:253) (338:338:338)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52519,10 +54864,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~0) (DELAY (ABSOLUTE - (PORT datab (376:376:376) (401:401:401)) - (PORT datac (380:380:380) (411:411:411)) + (PORT datab (201:201:201) (240:240:240)) + (PORT datad (210:210:210) (241:241:241)) (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -52531,9 +54876,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[8\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1895:1895:1895) (1917:1917:1917)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1563:1563:1563) (1555:1555:1555)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52547,7 +54892,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~18) (DELAY (ABSOLUTE - (PORT datad (383:383:383) (442:442:442)) + (PORT datad (383:383:383) (441:441:441)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -52558,8 +54903,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]\~3) (DELAY (ABSOLUTE - (PORT datad (337:337:337) (357:357:357)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (343:343:343) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -52568,9 +54913,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1893:1893:1893) (1916:1916:1916)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1562:1562:1562) (1554:1554:1554)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52584,13 +54929,13 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (397:397:397) (468:468:468)) - (PORT datab (423:423:423) (484:484:484)) - (PORT datac (392:392:392) (453:453:453)) - (PORT datad (393:393:393) (454:454:454)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (398:398:398) (478:478:478)) + (PORT datab (422:422:422) (482:482:482)) + (PORT datac (222:222:222) (301:301:301)) + (PORT datad (393:393:393) (456:456:456)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52600,10 +54945,10 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (249:249:249) (333:333:333)) - (PORT datac (664:664:664) (736:736:736)) - (PORT datad (176:176:176) (202:202:202)) + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (248:248:248) (333:333:333)) + (PORT datac (317:317:317) (336:336:336)) + (PORT datad (650:650:650) (712:712:712)) (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -52611,30 +54956,20 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2feeder) - (DELAY - (ABSOLUTE - (PORT datad (198:198:198) (224:224:224)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (535:535:535) (565:565:565)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL @@ -52642,8 +54977,8 @@ (INSTANCE ula_\|i2s_intf_\|lrclk_r\~0) (DELAY (ABSOLUTE - (PORT datab (905:905:905) (938:938:938)) - (PORT datad (233:233:233) (308:308:308)) + (PORT datab (962:962:962) (999:999:999)) + (PORT datad (231:231:231) (304:304:304)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52655,8 +54990,8 @@ (DELAY (ABSOLUTE (PORT clk (1505:1505:1505) (1526:1526:1526)) - (PORT d (2289:2289:2289) (2450:2450:2450)) - (PORT clrn (1761:1761:1761) (1813:1813:1813)) + (PORT d (1379:1379:1379) (1433:1433:1433)) + (PORT clrn (1748:1748:1748) (1798:1798:1798)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -52672,8 +55007,8 @@ (DELAY (ABSOLUTE (PORT clk (1505:1505:1505) (1527:1527:1527)) - (PORT d (2528:2528:2528) (2663:2663:2663)) - (PORT clrn (1762:1762:1762) (1814:1814:1814)) + (PORT d (1386:1386:1386) (1428:1428:1428)) + (PORT clrn (1749:1749:1749) (1799:1799:1799)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -52683,25 +55018,66 @@ (HOLD d (posedge clk) (97:97:97)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~18) + (DELAY + (ABSOLUTE + (PORT dataa (426:426:426) (458:458:458)) + (PORT datab (965:965:965) (1004:1004:1004)) + (PORT datad (217:217:217) (253:253:253)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]\~5) (DELAY (ABSOLUTE - (PORT datab (248:248:248) (334:334:334)) + (PORT datab (252:252:252) (337:337:337)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1feeder) + (DELAY + (ABSOLUTE + (PORT datac (193:193:193) (226:226:226)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52715,12 +55091,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~15) (DELAY (ABSOLUTE - (PORT datab (235:235:235) (283:283:283)) - (PORT datac (873:873:873) (896:896:896)) - (PORT datad (241:241:241) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (913:913:913) (945:945:945)) + (PORT datab (277:277:277) (369:369:369)) + (PORT datac (204:204:204) (241:241:241)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -52729,11 +55105,11 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2714:2714:2714) (2746:2746:2746)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (PORT sload (1479:1479:1479) (1529:1529:1529)) + (PORT asdata (570:570:570) (611:611:611)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) + (PORT sload (1495:1495:1495) (1558:1558:1558)) (PORT ena (790:790:790) (783:783:783)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -52751,7 +55127,7 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]\~7) (DELAY (ABSOLUTE - (PORT datab (248:248:248) (333:333:333)) + (PORT datab (251:251:251) (337:337:337)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52765,11 +55141,11 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2713:2713:2713) (2746:2746:2746)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (PORT sload (1479:1479:1479) (1529:1529:1529)) + (PORT asdata (570:570:570) (612:612:612)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) + (PORT sload (1495:1495:1495) (1558:1558:1558)) (PORT ena (790:790:790) (783:783:783)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -52787,7 +55163,7 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]\~9) (DELAY (ABSOLUTE - (PORT datab (250:250:250) (335:335:335)) + (PORT datab (252:252:252) (338:338:338)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52801,11 +55177,11 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2711:2711:2711) (2744:2744:2744)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (PORT sload (1479:1479:1479) (1529:1529:1529)) + (PORT asdata (567:567:567) (608:608:608)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) + (PORT sload (1495:1495:1495) (1558:1558:1558)) (PORT ena (790:790:790) (783:783:783)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -52823,9 +55199,9 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]\~11) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (343:343:343)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (264:264:264) (348:348:348)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52837,11 +55213,44 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2711:2711:2711) (2744:2744:2744)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (PORT sload (1479:1479:1479) (1529:1529:1529)) + (PORT asdata (568:568:568) (608:608:608)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) + (PORT sload (1495:1495:1495) (1558:1558:1558)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (366:366:366)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (568:568:568) (610:610:610)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) + (PORT sload (1495:1495:1495) (1558:1558:1558)) (PORT ena (790:790:790) (783:783:783)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -52859,56 +55268,39 @@ (INSTANCE ula_\|i2s_intf_\|LessThan0\~0) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (343:343:343)) - (PORT datab (252:252:252) (338:338:338)) - (PORT datac (223:223:223) (303:303:303)) - (PORT datad (227:227:227) (299:299:299)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (409:409:409) (479:479:479)) + (PORT datab (251:251:251) (335:335:335)) + (PORT datac (223:223:223) (301:301:301)) + (PORT datad (225:225:225) (296:296:296)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]\~1) (DELAY (ABSOLUTE - (PORT datab (269:269:269) (360:360:360)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH cin combout (455:455:455) (437:437:437)) + (PORT dataa (384:384:384) (461:461:461)) + (PORT datab (551:551:551) (565:565:565)) + (PORT datac (238:238:238) (326:326:326)) + (PORT datad (188:188:188) (220:220:220)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2710:2710:2710) (2743:2743:2743)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (PORT sload (1479:1479:1479) (1529:1529:1529)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|Add2\~7) (DELAY (ABSOLUTE - (PORT dataa (467:467:467) (538:538:538)) + (PORT dataa (415:415:415) (507:507:507)) (IOPATH dataa cout (436:436:436) (315:315:315)) ) ) @@ -52918,9 +55310,9 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~8) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (344:344:344)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (252:252:252) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52932,13 +55324,13 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~20) (DELAY (ABSOLUTE - (PORT dataa (470:470:470) (540:540:540)) - (PORT datab (903:903:903) (940:940:940)) - (PORT datac (205:205:205) (243:243:243)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (417:417:417) (505:505:505)) + (PORT datab (966:966:966) (1004:1004:1004)) + (PORT datac (318:318:318) (335:335:335)) + (PORT datad (217:217:217) (252:252:252)) (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52948,9 +55340,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52964,9 +55356,9 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~10) (DELAY (ABSOLUTE - (PORT dataa (399:399:399) (472:472:472)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (573:573:573) (642:642:642)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52978,12 +55370,12 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~17) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (284:284:284)) - (PORT datab (234:234:234) (285:285:285)) - (PORT datac (875:875:875) (898:898:898)) - (PORT datad (338:338:338) (359:359:359)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (427:427:427) (459:459:459)) + (PORT datab (962:962:962) (1006:1006:1006)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (331:331:331) (353:353:353)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52994,9 +55386,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53010,7 +55402,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~12) (DELAY (ABSOLUTE - (PORT datab (253:253:253) (339:339:339)) + (PORT datab (251:251:251) (335:335:335)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53024,12 +55416,12 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~19) (DELAY (ABSOLUTE - (PORT dataa (471:471:471) (539:539:539)) - (PORT datab (906:906:906) (939:939:939)) - (PORT datac (206:206:206) (243:243:243)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (419:419:419) (509:509:509)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (879:879:879) (891:891:891)) + (PORT datad (219:219:219) (255:255:255)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53040,9 +55432,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53056,7 +55448,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~14) (DELAY (ABSOLUTE - (PORT datad (362:362:362) (417:417:417)) + (PORT datad (227:227:227) (301:301:301)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -53067,12 +55459,12 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~16) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (285:285:285)) - (PORT datab (235:235:235) (288:288:288)) - (PORT datac (875:875:875) (900:900:900)) - (PORT datad (339:339:339) (359:359:359)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (426:426:426) (457:457:457)) + (PORT datab (965:965:965) (1004:1004:1004)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (333:333:333) (353:353:353)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53083,9 +55475,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53099,72 +55491,25 @@ (INSTANCE ula_\|i2s_intf_\|Equal1\~0) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (345:345:345)) - (PORT datab (253:253:253) (339:339:339)) - (PORT datac (368:368:368) (430:430:430)) - (PORT datad (361:361:361) (415:415:415)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (266:266:266) (353:353:353)) - (PORT datab (217:217:217) (263:263:263)) - (PORT datac (241:241:241) (328:328:328)) - (PORT datad (373:373:373) (399:399:399)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (251:251:251) (339:339:339)) + (PORT datab (249:249:249) (333:333:333)) + (PORT datac (223:223:223) (302:302:302)) + (PORT datad (549:549:549) (606:606:606)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~18) - (DELAY - (ABSOLUTE - (PORT dataa (908:908:908) (938:938:938)) - (PORT datab (235:235:235) (286:286:286)) - (PORT datad (375:375:375) (401:401:401)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|Equal1\~1) (DELAY (ABSOLUTE - (PORT datac (382:382:382) (450:450:450)) - (PORT datad (371:371:371) (396:396:396)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (246:246:246) (293:293:293)) + (PORT datad (391:391:391) (462:462:462)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53174,10 +55519,10 @@ (INSTANCE ula_\|i2s_intf_\|bclk_r\~0) (DELAY (ABSOLUTE - (PORT datab (216:216:216) (262:262:262)) - (PORT datac (239:239:239) (326:326:326)) - (PORT datad (238:238:238) (316:316:316)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (216:216:216) (267:267:267)) + (PORT datac (241:241:241) (330:330:330)) + (PORT datad (251:251:251) (332:332:332)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53188,12 +55533,13 @@ (INSTANCE ula_\|i2s_intf_\|bclk_r\~1) (DELAY (ABSOLUTE - (PORT dataa (226:226:226) (283:283:283)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datad (869:869:869) (882:882:882)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (546:546:546) (569:569:569)) + (PORT datab (276:276:276) (367:367:367)) + (PORT datac (881:881:881) (906:906:906)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53204,8 +55550,8 @@ (DELAY (ABSOLUTE (PORT clk (1504:1504:1504) (1526:1526:1526)) - (PORT d (2278:2278:2278) (2430:2430:2430)) - (PORT clrn (1761:1761:1761) (1813:1813:1813)) + (PORT d (1492:1492:1492) (1572:1572:1572)) + (PORT clrn (1748:1748:1748) (1798:1798:1798)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -53220,7 +55566,7 @@ (INSTANCE ula_\|pcm_outl\[13\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (861:861:861) (917:917:917)) + (PORT datad (931:931:931) (990:990:990)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53230,12 +55576,12 @@ (INSTANCE ula_\|always0\~2) (DELAY (ABSOLUTE - (PORT dataa (1754:1754:1754) (1860:1860:1860)) - (PORT datab (1594:1594:1594) (1730:1730:1730)) - (PORT datac (1193:1193:1193) (1255:1255:1255)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (1869:1869:1869) (2024:2024:2024)) + (PORT datac (3075:3075:3075) (3301:3301:3301)) + (PORT datad (2569:2569:2569) (2679:2679:2679)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -53244,13 +55590,13 @@ (INSTANCE ula_\|always0\~3) (DELAY (ABSOLUTE - (PORT dataa (686:686:686) (777:777:777)) - (PORT datab (1248:1248:1248) (1347:1347:1347)) - (PORT datac (1200:1200:1200) (1266:1266:1266)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (2571:2571:2571) (2819:2819:2819)) + (PORT datab (1226:1226:1226) (1334:1334:1334)) + (PORT datac (2100:2100:2100) (2229:2229:2229)) + (PORT datad (1093:1093:1093) (1082:1082:1082)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53262,7 +55608,7 @@ (ABSOLUTE (PORT clk (1522:1522:1522) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2002:2002:2002) (1998:1998:1998)) + (PORT ena (997:997:997) (1007:1007:1007)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -53276,12 +55622,12 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~19) (DELAY (ABSOLUTE - (PORT dataa (225:225:225) (279:279:279)) - (PORT datab (216:216:216) (259:259:259)) - (PORT datac (241:241:241) (328:328:328)) - (PORT datad (239:239:239) (317:317:317)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (551:551:551) (575:575:575)) + (PORT datab (279:279:279) (373:373:373)) + (PORT datac (242:242:242) (331:331:331)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53301,11 +55647,11 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~20) (DELAY (ABSOLUTE - (PORT dataa (1354:1354:1354) (1417:1417:1417)) - (PORT datab (1297:1297:1297) (1385:1385:1385)) - (PORT datad (764:764:764) (757:757:757)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) + (PORT dataa (985:985:985) (1054:1054:1054)) + (PORT datab (567:567:567) (582:582:582)) + (PORT datad (752:752:752) (742:742:742)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53316,9 +55662,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (1877:1877:1877) (1887:1887:1887)) + (PORT clk (1908:1908:1908) (1928:1928:1928)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53332,24 +55678,24 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~18) (DELAY (ABSOLUTE - (PORT datab (244:244:244) (327:327:327)) - (PORT datad (1250:1250:1250) (1334:1334:1334)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datac (928:928:928) (981:981:981)) + (PORT datad (220:220:220) (290:290:290)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~2) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]\~2) (DELAY (ABSOLUTE - (PORT datab (234:234:234) (283:283:283)) - (PORT datac (872:872:872) (895:895:895)) - (PORT datad (240:240:240) (318:318:318)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (911:911:911) (946:946:946)) + (PORT datab (278:278:278) (373:373:373)) + (PORT datac (202:202:202) (239:239:239)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -53358,10 +55704,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53376,9 +55722,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~17) (DELAY (ABSOLUTE - (PORT datac (216:216:216) (293:293:293)) - (PORT datad (1250:1250:1250) (1341:1341:1341)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datac (945:945:945) (999:999:999)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53388,10 +55734,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[2\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53406,10 +55752,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~16) (DELAY (ABSOLUTE - (PORT datab (245:245:245) (328:328:328)) - (PORT datad (1259:1259:1259) (1340:1340:1340)) + (PORT datab (245:245:245) (329:329:329)) + (PORT datac (941:941:941) (995:995:995)) (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -53418,10 +55764,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[3\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53436,9 +55782,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~15) (DELAY (ABSOLUTE - (PORT datab (246:246:246) (330:330:330)) - (PORT datad (1269:1269:1269) (1352:1352:1352)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datac (925:925:925) (991:991:991)) + (PORT datad (219:219:219) (287:287:287)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53448,10 +55794,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53466,10 +55812,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~14) (DELAY (ABSOLUTE - (PORT datab (245:245:245) (328:328:328)) - (PORT datad (1270:1270:1270) (1351:1351:1351)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (248:248:248) (336:336:336)) + (PORT datac (946:946:946) (1001:1001:1001)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -53478,10 +55824,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53496,9 +55842,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~13) (DELAY (ABSOLUTE - (PORT dataa (247:247:247) (335:335:335)) - (PORT datad (1261:1261:1261) (1348:1348:1348)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT datac (939:939:939) (985:985:985)) + (PORT datad (219:219:219) (289:289:289)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53508,10 +55854,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53526,9 +55872,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~12) (DELAY (ABSOLUTE - (PORT datab (245:245:245) (328:328:328)) - (PORT datad (1246:1246:1246) (1335:1335:1335)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datac (946:946:946) (1005:1005:1005)) + (PORT datad (219:219:219) (287:287:287)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53538,10 +55884,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53556,10 +55902,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~11) (DELAY (ABSOLUTE - (PORT datac (216:216:216) (292:292:292)) - (PORT datad (1248:1248:1248) (1334:1334:1334)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (244:244:244) (327:327:327)) + (PORT datac (949:949:949) (1004:1004:1004)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -53568,10 +55914,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53586,9 +55932,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~10) (DELAY (ABSOLUTE - (PORT datab (244:244:244) (327:327:327)) - (PORT datad (1249:1249:1249) (1344:1344:1344)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datac (948:948:948) (1006:1006:1006)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53598,10 +55944,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[9\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53616,10 +55962,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~9) (DELAY (ABSOLUTE - (PORT datac (218:218:218) (296:296:296)) - (PORT datad (1269:1269:1269) (1350:1350:1350)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (245:245:245) (328:328:328)) + (PORT datac (947:947:947) (1002:1002:1002)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -53628,10 +55974,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[10\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53646,9 +55992,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~8) (DELAY (ABSOLUTE - (PORT dataa (246:246:246) (334:334:334)) - (PORT datad (1268:1268:1268) (1351:1351:1351)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT datac (950:950:950) (1004:1004:1004)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53658,10 +56004,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[11\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53676,9 +56022,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~7) (DELAY (ABSOLUTE - (PORT datab (244:244:244) (327:327:327)) - (PORT datad (1265:1265:1265) (1355:1355:1355)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datac (927:927:927) (980:980:980)) + (PORT datad (221:221:221) (291:291:291)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53688,10 +56034,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[12\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53706,9 +56052,9 @@ (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1406:1406:1406) (1457:1457:1457)) - (PORT datab (896:896:896) (935:935:935)) - (PORT datad (232:232:232) (306:306:306)) + (PORT dataa (462:462:462) (530:530:530)) + (PORT datab (964:964:964) (1007:1007:1007)) + (PORT datad (235:235:235) (310:310:310)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -53721,9 +56067,9 @@ (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53737,9 +56083,9 @@ (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1405:1405:1405) (1456:1456:1456)) - (PORT datab (896:896:896) (934:934:934)) - (PORT datad (232:232:232) (306:306:306)) + (PORT dataa (462:462:462) (530:530:530)) + (PORT datab (964:964:964) (1006:1006:1006)) + (PORT datad (234:234:234) (310:310:310)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -53752,9 +56098,9 @@ (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53768,9 +56114,9 @@ (INSTANCE ula_\|pcm_outr\~0) (DELAY (ABSOLUTE - (PORT datac (218:218:218) (296:296:296)) - (PORT datad (219:219:219) (289:289:289)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (246:246:246) (334:334:334)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53780,9 +56126,9 @@ (INSTANCE ula_\|pcm_outl\[12\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT clk (1527:1527:1527) (1539:1539:1539)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2116:2116:2116) (2146:2146:2146)) + (PORT ena (2947:2947:2947) (2964:2964:2964)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -53796,11 +56142,11 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~6) (DELAY (ABSOLUTE - (PORT datab (1303:1303:1303) (1391:1391:1391)) - (PORT datac (218:218:218) (295:295:295)) - (PORT datad (1337:1337:1337) (1421:1421:1421)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (247:247:247) (335:335:335)) + (PORT datac (938:938:938) (987:987:987)) + (PORT datad (368:368:368) (428:428:428)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53810,10 +56156,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[13\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53828,10 +56174,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~5) (DELAY (ABSOLUTE - (PORT datab (1222:1222:1222) (1334:1334:1334)) - (PORT datac (217:217:217) (292:292:292)) - (PORT datad (1267:1267:1267) (1356:1356:1356)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT datab (1401:1401:1401) (1507:1507:1507)) + (PORT datac (929:929:929) (981:981:981)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53842,10 +56188,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[14\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53855,14 +56201,24 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|pcm_outl\[14\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (595:595:595) (610:610:610)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|pcm_outl\[14\]) (DELAY (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2262:2262:2262) (2235:2235:2235)) + (PORT ena (997:997:997) (1007:1007:1007)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -53876,9 +56232,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~4) (DELAY (ABSOLUTE - (PORT dataa (1212:1212:1212) (1296:1296:1296)) - (PORT datac (981:981:981) (1087:1087:1087)) - (PORT datad (656:656:656) (680:680:680)) + (PORT dataa (266:266:266) (354:354:354)) + (PORT datac (926:926:926) (989:989:989)) + (PORT datad (1495:1495:1495) (1587:1587:1587)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53890,10 +56246,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[15\]) (DELAY (ABSOLUTE - (PORT clk (1895:1895:1895) (1927:1927:1927)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1569:1569:1569)) - (PORT ena (1154:1154:1154) (1136:1136:1136)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53908,9 +56264,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~3) (DELAY (ABSOLUTE - (PORT datac (216:216:216) (293:293:293)) - (PORT datad (656:656:656) (683:683:683)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (619:619:619) (640:640:640)) + (PORT datad (664:664:664) (716:716:716)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53920,10 +56276,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[16\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1541:1541:1541)) + (PORT clk (1907:1907:1907) (1932:1932:1932)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1569:1569:1569)) - (PORT ena (1190:1190:1190) (1184:1184:1184)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1437:1437:1437) (1422:1422:1422)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53938,9 +56294,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~0) (DELAY (ABSOLUTE - (PORT datab (243:243:243) (325:325:325)) - (PORT datad (652:652:652) (681:681:681)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datab (615:615:615) (638:638:638)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53951,9 +56307,9 @@ (DELAY (ABSOLUTE (PORT clk (1508:1508:1508) (1530:1530:1530)) - (PORT d (1487:1487:1487) (1588:1588:1588)) - (PORT clrn (1765:1765:1765) (1817:1817:1817)) - (PORT ena (1717:1717:1717) (1806:1806:1806)) + (PORT d (1138:1138:1138) (1176:1176:1176)) + (PORT clrn (1752:1752:1752) (1802:1802:1802)) + (PORT ena (867:867:867) (864:864:864)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -53967,106 +56323,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan2\~0) + (INSTANCE ula_\|border\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (291:291:291) (381:381:381)) - (PORT datab (270:270:270) (353:353:353)) - (PORT datac (262:262:262) (341:341:341)) - (PORT datad (244:244:244) (316:316:316)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (263:263:263) (348:348:348)) - (PORT datab (260:260:260) (342:342:342)) - (PORT datac (255:255:255) (332:332:332)) - (PORT datad (237:237:237) (307:307:307)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (457:457:457) (540:540:540)) - (PORT datab (270:270:270) (354:354:354)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (356:356:356) (374:374:374)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (291:291:291) (383:383:383)) - (PORT datab (241:241:241) (280:280:280)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (271:271:271) (361:361:361)) - (PORT datab (261:261:261) (343:343:343)) - (PORT datad (247:247:247) (320:320:320)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|disp_enable\~0) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (410:410:410) (484:484:484)) - (PORT datad (659:659:659) (717:717:717)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|disp_enable\~1) - (DELAY - (ABSOLUTE - (PORT dataa (211:211:211) (260:260:260)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datad (348:348:348) (371:371:371)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT datad (1169:1169:1169) (1173:1173:1173)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54076,28 +56336,44 @@ (INSTANCE ula_\|border\[1\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) - (PORT asdata (537:537:537) (568:568:568)) - (PORT ena (2116:2116:2116) (2146:2146:2146)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1802:1802:1802) (1799:1799:1799)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (371:371:371)) + (PORT datab (261:261:261) (342:342:342)) + (PORT datac (234:234:234) (309:309:309)) + (PORT datad (236:236:236) (304:304:304)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|LessThan6\~1) (DELAY (ABSOLUTE - (PORT dataa (453:453:453) (541:541:541)) - (PORT datab (461:461:461) (551:551:551)) - (PORT datac (424:424:424) (504:504:504)) - (PORT datad (416:416:416) (444:444:444)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (284:284:284) (371:371:371)) + (PORT datab (282:282:282) (365:365:365)) + (PORT datac (395:395:395) (452:452:452)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54108,11 +56384,11 @@ (INSTANCE ula_\|video_\|LessThan4\~0) (DELAY (ABSOLUTE - (PORT dataa (271:271:271) (361:361:361)) - (PORT datab (273:273:273) (358:358:358)) + (PORT dataa (446:446:446) (511:511:511)) + (PORT datab (270:270:270) (355:355:355)) (PORT datad (236:236:236) (304:304:304)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54123,13 +56399,13 @@ (INSTANCE ula_\|video_\|screen_en\~0) (DELAY (ABSOLUTE - (PORT dataa (446:446:446) (522:522:522)) - (PORT datab (461:461:461) (542:542:542)) - (PORT datac (543:543:543) (561:561:561)) - (PORT datad (646:646:646) (718:718:718)) + (PORT dataa (412:412:412) (506:506:506)) + (PORT datab (678:678:678) (734:734:734)) + (PORT datac (607:607:607) (669:669:669)) + (PORT datad (515:515:515) (528:528:528)) (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54139,9 +56415,9 @@ (INSTANCE ula_\|video_\|screen_en\~1) (DELAY (ABSOLUTE - (PORT dataa (683:683:683) (744:744:744)) - (PORT datab (483:483:483) (561:561:561)) - (PORT datac (172:172:172) (205:205:205)) + (PORT dataa (279:279:279) (371:371:371)) + (PORT datab (288:288:288) (373:373:373)) + (PORT datac (344:344:344) (366:366:366)) (PORT datad (174:174:174) (199:199:199)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (336:336:336) (325:325:325)) @@ -54152,10 +56428,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) + (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1472:1472:1472) (1505:1505:1505)) + (PORT datad (897:897:897) (930:930:930)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54165,25 +56441,25 @@ (INSTANCE ula_\|video_\|Decoder0\~1) (DELAY (ABSOLUTE - (PORT dataa (1252:1252:1252) (1343:1343:1343)) - (PORT datab (984:984:984) (1066:1066:1066)) - (PORT datac (973:973:973) (1043:1043:1043)) - (PORT datad (280:280:280) (364:364:364)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (445:445:445) (545:545:545)) + (PORT datab (978:978:978) (1051:1051:1051)) + (PORT datac (708:708:708) (773:773:773)) + (PORT datad (743:743:743) (801:801:801)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]) + (INSTANCE ula_\|video_\|attr_prefetch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) + (PORT clk (1912:1912:1912) (1935:1935:1935)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) + (PORT ena (1216:1216:1216) (1204:1204:1204)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54197,10 +56473,10 @@ (INSTANCE ula_\|video_\|Decoder0\~0) (DELAY (ABSOLUTE - (PORT dataa (1252:1252:1252) (1342:1342:1342)) - (PORT datab (985:985:985) (1065:1065:1065)) - (PORT datac (974:974:974) (1042:1042:1042)) - (PORT datad (280:280:280) (364:364:364)) + (PORT dataa (443:443:443) (543:543:543)) + (PORT datab (973:973:973) (1046:1046:1046)) + (PORT datac (708:708:708) (775:775:775)) + (PORT datad (740:740:740) (796:796:796)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -54208,98 +56484,14 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1788:1788:1788) (1847:1847:1847)) - (PORT ena (1421:1421:1421) (1414:1414:1414)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1546:1546:1546) (1544:1544:1544)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1012:1012:1012) (1085:1085:1085)) - (PORT ena (1421:1421:1421) (1414:1414:1414)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1196:1196:1196) (1239:1239:1239)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|attr\[7\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (1010:1010:1010) (1078:1078:1078)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (1142:1142:1142) (1195:1195:1195)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54313,9 +56505,10 @@ (INSTANCE ula_\|video_\|frame\[0\]\~12) (DELAY (ABSOLUTE - (PORT dataa (620:620:620) (643:643:643)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT datab (1176:1176:1176) (1194:1194:1194)) + (PORT datad (226:226:226) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -54324,13 +56517,13 @@ (INSTANCE ula_\|video_\|frame\[0\]) (DELAY (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1878:1878:1878) (1891:1891:1891)) + (PORT asdata (517:517:517) (548:548:548)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL @@ -54338,8 +56531,8 @@ (INSTANCE ula_\|video_\|frame\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (613:613:613) (667:667:667)) - (PORT datab (243:243:243) (325:325:325)) + (PORT dataa (389:389:389) (459:459:459)) + (PORT datab (251:251:251) (336:336:336)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datab combout (344:344:344) (369:369:369)) @@ -54353,9 +56546,9 @@ (INSTANCE ula_\|video_\|frame\[1\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT clk (1538:1538:1538) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1236:1236:1236) (1237:1237:1237)) + (PORT ena (1765:1765:1765) (1740:1740:1740)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54369,9 +56562,9 @@ (INSTANCE ula_\|video_\|frame\[2\]\~6) (DELAY (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (243:243:243) (326:326:326)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -54383,9 +56576,9 @@ (INSTANCE ula_\|video_\|frame\[2\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT clk (1538:1538:1538) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1236:1236:1236) (1237:1237:1237)) + (PORT ena (1765:1765:1765) (1740:1740:1740)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54399,7 +56592,7 @@ (INSTANCE ula_\|video_\|frame\[3\]\~8) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (324:324:324)) + (PORT datab (243:243:243) (326:326:326)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -54413,9 +56606,9 @@ (INSTANCE ula_\|video_\|frame\[3\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT clk (1538:1538:1538) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1236:1236:1236) (1237:1237:1237)) + (PORT ena (1765:1765:1765) (1740:1740:1740)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54429,8 +56622,8 @@ (INSTANCE ula_\|video_\|frame\[4\]\~10) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (353:353:353)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT datad (380:380:380) (439:439:439)) + (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) ) @@ -54440,14 +56633,14 @@ (INSTANCE ula_\|video_\|frame\[4\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1236:1236:1236) (1237:1237:1237)) + (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT asdata (661:661:661) (675:675:675)) + (PORT ena (1765:1765:1765) (1740:1740:1740)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -54456,7 +56649,7 @@ (INSTANCE ula_\|video_\|inverted) (DELAY (ABSOLUTE - (PORT datad (372:372:372) (423:423:423)) + (PORT datad (663:663:663) (721:721:721)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54467,7 +56660,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1154:1154:1154) (1160:1160:1160)) + (PORT datad (1069:1069:1069) (1058:1058:1058)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54477,13 +56670,13 @@ (INSTANCE ula_\|video_\|Decoder0\~2) (DELAY (ABSOLUTE - (PORT dataa (1252:1252:1252) (1340:1340:1340)) - (PORT datab (986:986:986) (1064:1064:1064)) - (PORT datac (973:973:973) (1044:1044:1044)) - (PORT datad (279:279:279) (363:363:363)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (444:444:444) (543:543:543)) + (PORT datab (975:975:975) (1047:1047:1047)) + (PORT datac (710:710:710) (775:775:775)) + (PORT datad (742:742:742) (800:800:800)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54493,9 +56686,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1883:1883:1883) (1894:1894:1894)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1217:1217:1217) (1218:1218:1218)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54504,29 +56697,19 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (609:609:609) (678:678:678)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits\[6\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (1321:1321:1321) (1397:1397:1397)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -54535,7 +56718,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1545:1545:1545) (1541:1541:1541)) + (PORT datad (1432:1432:1432) (1427:1427:1427)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54545,9 +56728,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1883:1883:1883) (1894:1894:1894)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1217:1217:1217) (1218:1218:1218)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54561,9 +56744,9 @@ (INSTANCE ula_\|video_\|bits\[4\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (997:997:997) (1070:1070:1070)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (973:973:973) (1033:1033:1033)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54577,7 +56760,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (937:937:937) (955:955:955)) + (PORT datad (933:933:933) (975:975:975)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54587,9 +56770,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1883:1883:1883) (1894:1894:1894)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1217:1217:1217) (1218:1218:1218)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54603,7 +56786,7 @@ (INSTANCE ula_\|video_\|bits\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (651:651:651) (725:725:725)) + (PORT datad (650:650:650) (704:704:704)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54613,9 +56796,9 @@ (INSTANCE ula_\|video_\|bits\[5\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54629,7 +56812,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1201:1201:1201) (1243:1243:1243)) + (PORT datad (894:894:894) (929:929:929)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54639,9 +56822,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1883:1883:1883) (1894:1894:1894)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1217:1217:1217) (1218:1218:1218)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54655,9 +56838,9 @@ (INSTANCE ula_\|video_\|bits\[7\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (1216:1216:1216) (1295:1295:1295)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (991:991:991) (1050:1050:1050)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54671,11 +56854,11 @@ (INSTANCE ula_\|video_\|Mux0\~0) (DELAY (ABSOLUTE - (PORT dataa (385:385:385) (460:460:460)) - (PORT datab (288:288:288) (377:377:377)) - (PORT datad (636:636:636) (698:698:698)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (306:306:306) (408:408:408)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (378:378:378) (431:431:431)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54686,9 +56869,9 @@ (INSTANCE ula_\|video_\|Mux0\~1) (DELAY (ABSOLUTE - (PORT dataa (244:244:244) (330:330:330)) - (PORT datab (287:287:287) (374:374:374)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (304:304:304) (404:404:404)) + (PORT datab (243:243:243) (325:325:325)) + (PORT datad (173:173:173) (198:198:198)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -54701,7 +56884,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (883:883:883) (890:890:890)) + (PORT datad (1044:1044:1044) (1032:1032:1032)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54711,9 +56894,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1883:1883:1883) (1894:1894:1894)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1217:1217:1217) (1218:1218:1218)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54727,7 +56910,7 @@ (INSTANCE ula_\|video_\|bits\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (640:640:640) (711:711:711)) + (PORT datad (645:645:645) (702:702:702)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54737,9 +56920,9 @@ (INSTANCE ula_\|video_\|bits\[2\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54753,7 +56936,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1463:1463:1463) (1429:1429:1429)) + (PORT datad (910:910:910) (917:917:917)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54763,9 +56946,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1883:1883:1883) (1894:1894:1894)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1217:1217:1217) (1218:1218:1218)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54779,9 +56962,9 @@ (INSTANCE ula_\|video_\|bits\[0\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (978:978:978) (1047:1047:1047)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (1488:1488:1488) (1559:1559:1559)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54795,7 +56978,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1470:1470:1470) (1502:1502:1502)) + (PORT datad (645:645:645) (655:655:655)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54805,9 +56988,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1883:1883:1883) (1894:1894:1894)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1217:1217:1217) (1218:1218:1218)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54821,7 +57004,7 @@ (INSTANCE ula_\|video_\|bits\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (642:642:642) (704:704:704)) + (PORT datad (643:643:643) (702:702:702)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54831,9 +57014,9 @@ (INSTANCE ula_\|video_\|bits\[1\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54847,7 +57030,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1276:1276:1276) (1241:1241:1241)) + (PORT datad (925:925:925) (942:942:942)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54857,9 +57040,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1883:1883:1883) (1894:1894:1894)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1217:1217:1217) (1218:1218:1218)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54873,9 +57056,9 @@ (INSTANCE ula_\|video_\|bits\[3\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (1448:1448:1448) (1474:1474:1474)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (1153:1153:1153) (1205:1205:1205)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54889,11 +57072,11 @@ (INSTANCE ula_\|video_\|Mux0\~2) (DELAY (ABSOLUTE - (PORT dataa (242:242:242) (328:328:328)) - (PORT datab (286:286:286) (373:373:373)) - (PORT datad (633:633:633) (694:694:694)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (309:309:309) (409:409:409)) + (PORT datab (243:243:243) (325:325:325)) + (PORT datad (381:381:381) (435:435:435)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54904,9 +57087,9 @@ (INSTANCE ula_\|video_\|Mux0\~3) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (329:329:329)) - (PORT datab (287:287:287) (377:377:377)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (309:309:309) (409:409:409)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (172:172:172) (197:197:197)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -54916,44 +57099,217 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|cindex\[1\]\~0) + (INSTANCE ula_\|video_\|cindex\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (401:401:401) (477:477:477)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (173:173:173) (206:206:206)) + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (200:200:200) (239:239:239)) (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (337:337:337) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1431:1431:1431) (1427:1427:1427)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1912:1912:1912) (1935:1935:1935)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1216:1216:1216) (1204:1204:1204)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (999:999:999) (1058:1058:1058)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (645:645:645) (655:655:655)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1912:1912:1912) (1935:1935:1935)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1216:1216:1216) (1204:1204:1204)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (998:998:998) (1057:1057:1057)) + (PORT ena (1452:1452:1452) (1445:1445:1445)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|cindex\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (245:245:245) (332:332:332)) - (PORT datad (347:347:347) (363:363:363)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT dataa (216:216:216) (266:266:266)) + (PORT datad (351:351:351) (406:406:406)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (411:411:411) (501:501:501)) + (PORT datab (289:289:289) (374:374:374)) + (PORT datac (249:249:249) (334:334:334)) + (PORT datad (264:264:264) (337:337:337)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (705:705:705)) + (PORT datab (467:467:467) (530:530:530)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (350:350:350) (372:372:372)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (504:504:504)) + (PORT datab (468:468:468) (533:533:533)) + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (348:348:348) (370:370:370)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (262:262:262) (348:348:348)) + (PORT datad (248:248:248) (321:321:321)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|disp_enable\~0) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (727:727:727)) + (PORT datab (261:261:261) (343:343:343)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|disp_enable\~1) + (DELAY + (ABSOLUTE + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (511:511:511) (525:525:525)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|VGA_R\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (398:398:398) (453:453:453)) - (PORT datab (1490:1490:1490) (1585:1585:1585)) - (PORT datac (235:235:235) (278:278:278)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (1435:1435:1435) (1539:1539:1539)) + (PORT datab (236:236:236) (279:279:279)) + (PORT datac (325:325:325) (348:348:348)) + (PORT datad (204:204:204) (234:234:234)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54964,7 +57320,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1157:1157:1157) (1161:1161:1161)) + (PORT datad (1068:1068:1068) (1056:1056:1056)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54974,9 +57330,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) + (PORT clk (1912:1912:1912) (1935:1935:1935)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) + (PORT ena (1216:1216:1216) (1204:1204:1204)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54990,9 +57346,9 @@ (INSTANCE ula_\|video_\|attr\[6\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1216:1216:1216) (1269:1269:1269)) - (PORT ena (1638:1638:1638) (1616:1616:1616)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (970:970:970) (1019:1019:1019)) + (PORT ena (1289:1289:1289) (1289:1289:1289)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55006,11 +57362,11 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (212:212:212) (261:261:261)) - (PORT datab (208:208:208) (249:249:249)) - (PORT datad (348:348:348) (371:371:371)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (365:365:365) (395:395:395)) + (PORT datab (1103:1103:1103) (1116:1116:1116)) + (PORT datad (184:184:184) (213:213:213)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55021,11 +57377,21 @@ (INSTANCE ula_\|video_\|VGA_R\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (269:269:269) (322:322:322)) - (PORT datac (391:391:391) (430:430:430)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (362:362:362) (395:395:395)) + (PORT datab (237:237:237) (282:282:282)) + (PORT datac (325:325:325) (348:348:348)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|border\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1310:1310:1310) (1352:1352:1352)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55035,35 +57401,9 @@ (INSTANCE ula_\|border\[2\]) (DELAY (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT asdata (956:956:956) (977:977:977)) - (PORT ena (812:812:812) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (884:884:884) (889:889:889)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) + (PORT clk (1527:1527:1527) (1540:1540:1540)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) + (PORT ena (1944:1944:1944) (1933:1933:1933)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55072,28 +57412,12 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (1208:1208:1208) (1265:1265:1265)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|attr_prefetch\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (935:935:935) (952:952:952)) + (PORT datad (930:930:930) (973:973:973)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55103,9 +57427,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) + (PORT clk (1912:1912:1912) (1935:1935:1935)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) + (PORT ena (1216:1216:1216) (1204:1204:1204)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55119,9 +57443,51 @@ (INSTANCE ula_\|video_\|attr\[5\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (993:993:993) (1051:1051:1051)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (1010:1010:1010) (1067:1067:1067)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1045:1045:1045) (1032:1032:1032)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1912:1912:1912) (1935:1935:1935)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1216:1216:1216) (1204:1204:1204)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (1430:1430:1430) (1470:1470:1470)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55135,9 +57501,9 @@ (INSTANCE ula_\|video_\|cindex\[2\]\~2) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (324:324:324)) - (PORT datad (203:203:203) (232:232:232)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (217:217:217) (269:269:269)) + (PORT datad (218:218:218) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55148,10 +57514,10 @@ (INSTANCE ula_\|video_\|VGA_G\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (2313:2313:2313) (2480:2480:2480)) - (PORT datab (411:411:411) (449:449:449)) - (PORT datac (384:384:384) (420:420:420)) - (PORT datad (547:547:547) (557:557:557)) + (PORT dataa (230:230:230) (275:275:275)) + (PORT datab (240:240:240) (285:285:285)) + (PORT datac (859:859:859) (931:931:931)) + (PORT datad (318:318:318) (335:335:335)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -55164,11 +57530,21 @@ (INSTANCE ula_\|video_\|VGA_G\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (636:636:636) (662:662:662)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datad (378:378:378) (398:398:398)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (360:360:360) (394:394:394)) + (PORT datac (603:603:603) (618:618:618)) + (PORT datad (315:315:315) (331:331:331)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|border\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (578:578:578) (598:598:598)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55178,9 +57554,51 @@ (INSTANCE ula_\|border\[0\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) - (PORT asdata (1466:1466:1466) (1519:1519:1519)) - (PORT ena (2116:2116:2116) (2146:2146:2146)) + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1726:1726:1726) (1702:1702:1702)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (912:912:912) (918:918:918)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1912:1912:1912) (1935:1935:1935)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1216:1216:1216) (1204:1204:1204)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (973:973:973) (1033:1033:1033)) + (PORT ena (1452:1452:1452) (1445:1445:1445)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55189,64 +57607,12 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1462:1462:1462) (1430:1430:1430)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (839:839:839) (888:888:888)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1421:1421:1421) (1414:1414:1414)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|attr_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1276:1276:1276) (1242:1242:1242)) + (PORT datad (929:929:929) (945:945:945)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55256,9 +57622,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) + (PORT clk (1912:1912:1912) (1935:1935:1935)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) + (PORT ena (1216:1216:1216) (1204:1204:1204)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55272,9 +57638,9 @@ (INSTANCE ula_\|video_\|attr\[3\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (965:965:965) (1040:1040:1040)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (974:974:974) (1030:1030:1030)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55288,8 +57654,8 @@ (INSTANCE ula_\|video_\|cindex\[0\]\~3) (DELAY (ABSOLUTE - (PORT datab (384:384:384) (459:459:459)) - (PORT datad (204:204:204) (232:232:232)) + (PORT datab (379:379:379) (445:445:445)) + (PORT datad (187:187:187) (222:222:222)) (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -55301,13 +57667,13 @@ (INSTANCE ula_\|video_\|VGA_B\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (399:399:399) (453:453:453)) - (PORT datab (1662:1662:1662) (1745:1745:1745)) - (PORT datac (233:233:233) (279:279:279)) - (PORT datad (334:334:334) (354:354:354)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1720:1720:1720) (1842:1842:1842)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (364:364:364) (389:389:389)) + (PORT datad (369:369:369) (393:393:393)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55317,11 +57683,11 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~2) (DELAY (ABSOLUTE - (PORT dataa (269:269:269) (323:323:323)) - (PORT datac (391:391:391) (429:429:429)) - (PORT datad (340:340:340) (359:359:359)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (358:358:358) (393:393:393)) + (PORT datab (348:348:348) (385:385:385)) + (PORT datad (371:371:371) (397:397:397)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55331,11 +57697,11 @@ (INSTANCE ula_\|video_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (681:681:681) (753:753:753)) - (PORT datab (282:282:282) (364:364:364)) - (PORT datad (645:645:645) (715:715:715)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (895:895:895) (960:960:960)) + (PORT datac (851:851:851) (897:897:897)) + (PORT datad (1129:1129:1129) (1171:1171:1171)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55345,7 +57711,7 @@ (INSTANCE ula_\|video_\|VGA_HS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT clk (1540:1540:1540) (1552:1552:1552)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -55359,9 +57725,9 @@ (INSTANCE ula_\|video_\|Selector0\~0) (DELAY (ABSOLUTE - (PORT dataa (1030:1030:1030) (1035:1035:1035)) - (PORT datab (228:228:228) (270:270:270)) - (PORT datad (571:571:571) (575:575:575)) + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (401:401:401) (435:435:435)) + (PORT datad (362:362:362) (380:380:380)) (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -55375,7 +57741,7 @@ (DELAY (ABSOLUTE (PORT clk (1509:1509:1509) (1531:1531:1531)) - (PORT d (1715:1715:1715) (1721:1721:1721)) + (PORT d (2297:2297:2297) (2325:2325:2325)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -55389,7 +57755,7 @@ (INSTANCE ula_\|video_\|VGA_VS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) + (PORT clk (1541:1541:1541) (1552:1552:1552)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -55403,11 +57769,11 @@ (INSTANCE ula_\|video_\|Selector1\~0) (DELAY (ABSOLUTE - (PORT dataa (620:620:620) (642:642:642)) - (PORT datab (1174:1174:1174) (1179:1179:1179)) - (PORT datad (691:691:691) (762:762:762)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (284:284:284) (381:381:381)) + (PORT datab (527:527:527) (549:549:549)) + (PORT datad (1470:1470:1470) (1488:1488:1488)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55419,7 +57785,7 @@ (DELAY (ABSOLUTE (PORT clk (1507:1507:1507) (1529:1529:1529)) - (PORT d (1805:1805:1805) (1839:1839:1839)) + (PORT d (1566:1566:1566) (1671:1671:1671)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -55433,7 +57799,7 @@ (INSTANCE z80_\|memory_ifc_\|q1\~feeder) (DELAY (ABSOLUTE - (PORT datad (620:620:620) (667:667:667)) + (PORT datad (252:252:252) (325:325:325)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55443,10 +57809,10 @@ (INSTANCE z80_\|memory_ifc_\|q1) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1553:1553:1553)) + (PORT clk (1525:1525:1525) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (1483:1483:1483) (1473:1473:1473)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT ena (1243:1243:1243) (1234:1234:1234)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55461,10 +57827,10 @@ (INSTANCE z80_\|memory_ifc_\|q2) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1553:1553:1553)) - (PORT asdata (560:560:560) (634:634:634)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (1483:1483:1483) (1473:1473:1473)) + (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT asdata (558:558:558) (632:632:632)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT ena (1243:1243:1243) (1234:1234:1234)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55479,7 +57845,7 @@ (INSTANCE z80_\|memory_ifc_\|nRFSH_out\~0) (DELAY (ABSOLUTE - (PORT datad (621:621:621) (666:666:666)) + (PORT datad (252:252:252) (324:324:324)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55490,8 +57856,8 @@ (INSTANCE z80_\|memory_ifc_\|nM1_out) (DELAY (ABSOLUTE - (PORT datac (1282:1282:1282) (1346:1346:1346)) - (PORT datad (621:621:621) (669:669:669)) + (PORT datac (1472:1472:1472) (1513:1513:1513)) + (PORT datad (250:250:250) (324:324:324)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55502,10 +57868,10 @@ (INSTANCE ula_\|beep\~0) (DELAY (ABSOLUTE - (PORT datab (1714:1714:1714) (1839:1839:1839)) - (PORT datac (3217:3217:3217) (3502:3502:3502)) - (PORT datad (1247:1247:1247) (1342:1342:1342)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (973:973:973) (1037:1037:1037)) + (PORT datac (3465:3465:3465) (3837:3837:3837)) + (PORT datad (596:596:596) (610:610:610)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55516,9 +57882,9 @@ (INSTANCE ula_\|beep) (DELAY (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2564:2564:2564) (2572:2572:2572)) + (PORT ena (997:997:997) (1007:1007:1007)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55527,4 +57893,2294 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux26\~4) + (DELAY + (ABSOLUTE + (PORT dataa (2317:2317:2317) (2532:2532:2532)) + (PORT datab (938:938:938) (974:974:974)) + (PORT datad (1425:1425:1425) (1536:1536:1536)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT datac (989:989:989) (1111:1111:1111)) + (PORT datad (1785:1785:1785) (1929:1929:1929)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (953:953:953)) + (PORT datab (830:830:830) (930:930:930)) + (PORT datac (782:782:782) (889:889:889)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (292:292:292) (378:378:378)) + (PORT datac (585:585:585) (604:604:604)) + (PORT datad (284:284:284) (364:364:364)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1030:1030:1030) (1121:1121:1121)) + (PORT datab (1035:1035:1035) (1089:1089:1089)) + (PORT datac (1056:1056:1056) (1136:1136:1136)) + (PORT datad (599:599:599) (611:611:611)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1315:1315:1315) (1427:1427:1427)) + (PORT datab (1874:1874:1874) (2002:2002:2002)) + (PORT datac (992:992:992) (1110:1110:1110)) + (PORT datad (778:778:778) (811:811:811)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (1299:1299:1299) (1369:1369:1369)) + (PORT datac (1841:1841:1841) (1973:1973:1973)) + (PORT datad (995:995:995) (1099:1099:1099)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (958:958:958)) + (PORT datab (829:829:829) (935:935:935)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (181:181:181) (211:211:211)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1316:1316:1316) (1427:1427:1427)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.bank\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1539:1539:1539)) + (PORT d (1777:1777:1777) (1875:1875:1875)) + (PORT ena (1774:1774:1774) (1775:1775:1775)) + (IOPATH (posedge clk) q (586:586:586) (589:589:589)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (82:82:82)) + (SETUP ena (posedge clk) (82:82:82)) + (HOLD d (posedge clk) (97:97:97)) + (HOLD ena (posedge clk) (97:97:97)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux25\~4) + (DELAY + (ABSOLUTE + (PORT dataa (2317:2317:2317) (2534:2534:2534)) + (PORT datab (1431:1431:1431) (1561:1561:1561)) + (PORT datad (913:913:913) (939:939:939)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.bank\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1540:1540:1540)) + (PORT d (2321:2321:2321) (2432:2432:2432)) + (PORT ena (1597:1597:1597) (1608:1608:1608)) + (IOPATH (posedge clk) q (586:586:586) (589:589:589)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (82:82:82)) + (SETUP ena (posedge clk) (82:82:82)) + (HOLD d (posedge clk) (97:97:97)) + (HOLD ena (posedge clk) (97:97:97)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1066:1066:1066) (1202:1202:1202)) + (PORT datab (1024:1024:1024) (1113:1113:1113)) + (PORT datac (1152:1152:1152) (1196:1196:1196)) + (PORT datad (994:994:994) (1081:1081:1081)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~0) + (DELAY + (ABSOLUTE + (PORT datab (1399:1399:1399) (1527:1527:1527)) + (PORT datac (1575:1575:1575) (1656:1656:1656)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~7) + (DELAY + (ABSOLUTE + (PORT datab (1709:1709:1709) (1882:1882:1882)) + (PORT datac (221:221:221) (300:300:300)) + (PORT datad (2617:2617:2617) (2813:2813:2813)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (704:704:704) (772:772:772)) + (PORT datab (201:201:201) (240:240:240)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (183:183:183) (213:213:213)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1307:1307:1307) (1422:1422:1422)) + (PORT datab (1474:1474:1474) (1580:1580:1580)) + (PORT datac (1576:1576:1576) (1657:1657:1657)) + (PORT datad (1362:1362:1362) (1488:1488:1488)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1306:1306:1306) (1421:1421:1421)) + (PORT datab (1020:1020:1020) (1139:1139:1139)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (189:189:189) (219:219:219)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1090:1090:1090) (1128:1128:1128)) + (PORT datab (215:215:215) (260:260:260)) + (PORT datac (1032:1032:1032) (1159:1159:1159)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~4) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (171:171:171) (202:202:202)) + (PORT datad (996:996:996) (1103:1103:1103)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.dq_masks\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1537:1537:1537)) + (PORT d (1467:1467:1467) (1545:1545:1545)) + (IOPATH (posedge clk) q (586:586:586) (589:589:589)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (82:82:82)) + (HOLD d (posedge clk) (97:97:97)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.dq_masks\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1537:1537:1537)) + (PORT d (1454:1454:1454) (1530:1530:1530)) + (IOPATH (posedge clk) q (586:586:586) (589:589:589)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (82:82:82)) + (HOLD d (posedge clk) (97:97:97)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT datac (1570:1570:1570) (1649:1649:1649)) + (PORT datad (996:996:996) (1103:1103:1103)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~3) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (399:399:399)) + (PORT datab (1477:1477:1477) (1604:1604:1604)) + (PORT datac (1329:1329:1329) (1470:1470:1470)) + (PORT datad (353:353:353) (368:368:368)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~5) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (521:521:521)) + (PORT datab (698:698:698) (778:778:778)) + (PORT datac (586:586:586) (604:604:604)) + (PORT datad (285:285:285) (364:364:364)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~4) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (378:378:378)) + (PORT datab (1370:1370:1370) (1466:1466:1466)) + (PORT datac (882:882:882) (893:893:893)) + (PORT datad (1440:1440:1440) (1565:1565:1565)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1366:1366:1366) (1518:1518:1518)) + (PORT datab (1371:1371:1371) (1460:1460:1460)) + (PORT datac (881:881:881) (891:891:891)) + (PORT datad (1253:1253:1253) (1312:1312:1312)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (870:870:870)) + (PORT datab (302:302:302) (394:394:394)) + (PORT datac (631:631:631) (680:680:680)) + (PORT datad (754:754:754) (832:832:832)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~2) + (DELAY + (ABSOLUTE + (PORT datab (449:449:449) (513:513:513)) + (PORT datac (415:415:415) (481:481:481)) + (PORT datad (588:588:588) (645:645:645)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~3) + (DELAY + (ABSOLUTE + (PORT dataa (420:420:420) (498:498:498)) + (PORT datab (272:272:272) (357:357:357)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (425:425:425) (483:483:483)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (418:418:418) (497:497:497)) + (PORT datab (450:450:450) (516:516:516)) + (PORT datac (353:353:353) (381:381:381)) + (PORT datad (411:411:411) (473:473:473)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~4) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (423:423:423) (493:493:493)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (683:683:683) (766:766:766)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1426:1426:1426) (1547:1547:1547)) + (PORT datab (1604:1604:1604) (1732:1732:1732)) + (PORT datac (1336:1336:1336) (1427:1427:1427)) + (PORT datad (332:332:332) (354:354:354)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~0) + (DELAY + (ABSOLUTE + (PORT datab (1369:1369:1369) (1466:1466:1466)) + (PORT datad (1568:1568:1568) (1695:1695:1695)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~6) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (423:423:423)) + (PORT datab (643:643:643) (685:685:685)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~7) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (1269:1269:1269) (1350:1350:1350)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1498:1498:1498) (1529:1529:1529)) + (PORT d (1472:1472:1472) (1557:1557:1557)) + (IOPATH (posedge clk) q (617:617:617) (612:612:612)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (80:80:80)) + (HOLD d (posedge clk) (101:101:101)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~11) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1112:1112:1112)) + (PORT datab (1023:1023:1023) (1115:1115:1115)) + (PORT datac (1152:1152:1152) (1199:1199:1199)) + (PORT datad (995:995:995) (1083:1083:1083)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1063:1063:1063) (1201:1201:1201)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (1060:1060:1060) (1092:1092:1092)) + (PORT datad (968:968:968) (1089:1089:1089)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1306:1306:1306) (1421:1421:1421)) + (PORT datab (1399:1399:1399) (1528:1528:1528)) + (PORT datac (948:948:948) (1069:1069:1069)) + (PORT datad (635:635:635) (671:671:671)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1062:1062:1062) (1202:1202:1202)) + (PORT datab (1398:1398:1398) (1531:1531:1531)) + (PORT datac (948:948:948) (1074:1074:1074)) + (PORT datad (968:968:968) (1089:1089:1089)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~8) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (1021:1021:1021) (1144:1144:1144)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~9) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1498:1498:1498) (1529:1529:1529)) + (PORT d (1253:1253:1253) (1356:1356:1356)) + (IOPATH (posedge clk) q (617:617:617) (612:612:612)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (80:80:80)) + (HOLD d (posedge clk) (101:101:101)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ena_reg") + (INSTANCE sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl_e_DRAM_CLK.extena0_reg) + (DELAY + (ABSOLUTE + (PORT d (288:288:288) (259:259:259)) + (PORT clk (0:0:0) (0:0:0)) + (IOPATH (posedge clk) q (166:166:166) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (94:94:94)) + (HOLD d (posedge clk) (83:83:83)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ena_reg") + (INSTANCE sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl_e_DRAM_CLK.extena1_reg) + (DELAY + (ABSOLUTE + (PORT d (0:0:0) (0:0:0)) + (PORT clk (0:0:0) (0:0:0)) + (IOPATH (posedge clk) q (281:281:281) (258:258:258)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (94:94:94)) + (HOLD d (posedge clk) (83:83:83)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~2) + (DELAY + (ABSOLUTE + (PORT dataa (743:743:743) (861:861:861)) + (PORT datab (780:780:780) (870:870:870)) + (PORT datad (273:273:273) (356:356:356)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1511:1511:1511) (1631:1631:1631)) + (PORT datab (655:655:655) (707:707:707)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1409:1409:1409) (1518:1518:1518)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1360:1360:1360) (1508:1508:1508)) + (PORT datab (1372:1372:1372) (1466:1466:1466)) + (PORT datac (626:626:626) (666:666:666)) + (PORT datad (323:323:323) (345:345:345)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1359:1359:1359) (1509:1509:1509)) + (PORT datab (1372:1372:1372) (1466:1466:1466)) + (PORT datac (1581:1581:1581) (1661:1661:1661)) + (PORT datad (1257:1257:1257) (1317:1317:1317)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~6) + (DELAY + (ABSOLUTE + (PORT dataa (985:985:985) (1116:1116:1116)) + (PORT datab (1024:1024:1024) (1143:1143:1143)) + (PORT datac (1035:1035:1035) (1162:1162:1162)) + (PORT datad (971:971:971) (1090:1090:1090)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~7) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (960:960:960)) + (PORT datab (829:829:829) (930:930:930)) + (PORT datac (783:783:783) (893:893:893)) + (PORT datad (313:313:313) (331:331:331)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1426:1426:1426) (1549:1549:1549)) + (PORT datab (1264:1264:1264) (1350:1350:1350)) + (PORT datac (883:883:883) (894:894:894)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~8) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (597:597:597) (604:604:604)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1495:1495:1495) (1520:1520:1520)) + (PORT d (1809:1809:1809) (1935:1935:1935)) + (IOPATH (posedge clk) q (617:617:617) (612:612:612)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (80:80:80)) + (HOLD d (posedge clk) (101:101:101)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~2) + (DELAY + (ABSOLUTE + (PORT dataa (776:776:776) (869:869:869)) + (PORT datab (765:765:765) (852:852:852)) + (PORT datac (764:764:764) (877:877:877)) + (PORT datad (860:860:860) (888:888:888)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (3061:3061:3061) (3225:3225:3225)) + (PORT datab (612:612:612) (668:668:668)) + (PORT datac (1038:1038:1038) (1141:1141:1141)) + (PORT datad (632:632:632) (661:661:661)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (632:632:632)) + (PORT datab (993:993:993) (1068:1068:1068)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1359:1359:1359) (1510:1510:1510)) + (PORT datab (1269:1269:1269) (1353:1353:1353)) + (PORT datac (1581:1581:1581) (1661:1661:1661)) + (PORT datad (1441:1441:1441) (1561:1561:1561)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1367:1367:1367) (1518:1518:1518)) + (PORT datab (1264:1264:1264) (1346:1346:1346)) + (PORT datac (1575:1575:1575) (1654:1654:1654)) + (PORT datad (1444:1444:1444) (1567:1567:1567)) + (IOPATH dataa combout (337:337:337) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~5) + (DELAY + (ABSOLUTE + (PORT datab (1371:1371:1371) (1460:1460:1460)) + (PORT datac (175:175:175) (208:208:208)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[0\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1560:1560:1560)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (523:523:523) (557:557:557)) + (PORT sload (1639:1639:1639) (1751:1751:1751)) + (PORT ena (1247:1247:1247) (1254:1254:1254)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~3) + (DELAY + (ABSOLUTE + (PORT dataa (3061:3061:3061) (3223:3223:3223)) + (PORT datab (613:613:613) (668:668:668)) + (PORT datac (380:380:380) (405:405:405)) + (PORT datad (632:632:632) (657:657:657)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~4) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (956:956:956)) + (PORT datab (614:614:614) (671:671:671)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1100:1100:1100) (1185:1185:1185)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[0\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT datab (1063:1063:1063) (1134:1134:1134)) + (PORT datac (179:179:179) (214:214:214)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1497:1497:1497) (1522:1522:1522)) + (PORT d (2000:2000:2000) (2102:2102:2102)) + (PORT ena (1672:1672:1672) (1717:1717:1717)) + (IOPATH (posedge clk) q (617:617:617) (612:612:612)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (80:80:80)) + (SETUP ena (posedge clk) (80:80:80)) + (HOLD d (posedge clk) (101:101:101)) + (HOLD ena (posedge clk) (101:101:101)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~_Duplicate_1feeder) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (257:257:257)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1030:1030:1030) (1137:1137:1137)) + (PORT datab (251:251:251) (337:337:337)) + (PORT datac (1288:1288:1288) (1347:1347:1347)) + (PORT datad (333:333:333) (361:361:361)) + (IOPATH dataa combout (301:301:301) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (748:748:748) (867:867:867)) + (PORT datab (780:780:780) (874:874:874)) + (PORT datac (627:627:627) (678:678:678)) + (PORT datad (275:275:275) (357:357:357)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1030:1030:1030) (1138:1138:1138)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (957:957:957) (1041:1041:1041)) + (PORT datad (864:864:864) (898:898:898)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1033:1033:1033) (1138:1138:1138)) + (PORT datab (1067:1067:1067) (1184:1184:1184)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (886:886:886) (884:884:884)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1284:1284:1284) (1361:1361:1361)) + (PORT datab (1090:1090:1090) (1165:1165:1165)) + (PORT datac (1257:1257:1257) (1368:1368:1368)) + (PORT datad (1000:1000:1000) (1053:1053:1053)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[1\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (523:523:523) (558:558:558)) + (PORT sload (1747:1747:1747) (1674:1674:1674)) + (PORT ena (1291:1291:1291) (1292:1292:1292)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1311:1311:1311) (1441:1441:1441)) + (PORT datab (360:360:360) (395:395:395)) + (PORT datac (957:957:957) (1039:1039:1039)) + (PORT datad (989:989:989) (1074:1074:1074)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1312:1312:1312) (1442:1442:1442)) + (PORT datac (518:518:518) (537:537:537)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1308:1308:1308) (1440:1440:1440)) + (PORT datab (2607:2607:2607) (2785:2785:2785)) + (PORT datac (1734:1734:1734) (1812:1812:1812)) + (PORT datad (991:991:991) (1080:1080:1080)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (335:335:335)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (258:258:258)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (1028:1028:1028) (1131:1131:1131)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1540:1540:1540)) + (PORT d (1503:1503:1503) (1609:1609:1609)) + (PORT ena (1911:1911:1911) (1938:1938:1938)) + (IOPATH (posedge clk) q (586:586:586) (589:589:589)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (82:82:82)) + (SETUP ena (posedge clk) (82:82:82)) + (HOLD d (posedge clk) (97:97:97)) + (HOLD ena (posedge clk) (97:97:97)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1304:1304:1304) (1437:1437:1437)) + (PORT datab (1036:1036:1036) (1094:1094:1094)) + (PORT datac (1028:1028:1028) (1133:1133:1133)) + (PORT datad (990:990:990) (1085:1085:1085)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT datab (1036:1036:1036) (1091:1091:1091)) + (PORT datad (1280:1280:1280) (1394:1394:1394)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux21\~0) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (287:287:287)) + (PORT datab (1062:1062:1062) (1180:1180:1180)) + (PORT datac (314:314:314) (333:333:333)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux22\~0) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (748:748:748)) + (PORT datab (220:220:220) (260:260:260)) + (PORT datac (879:879:879) (894:894:894)) + (PORT datad (635:635:635) (660:660:660)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1813:1813:1813) (1972:1972:1972)) + (PORT datab (1021:1021:1021) (1144:1144:1144)) + (PORT datac (781:781:781) (894:894:894)) + (PORT datad (790:790:790) (895:895:895)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (816:816:816) (925:925:925)) + (PORT datac (1840:1840:1840) (1973:1973:1973)) + (PORT datad (994:994:994) (1103:1103:1103)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (953:953:953)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datac (1841:1841:1841) (1971:1971:1971)) + (PORT datad (1238:1238:1238) (1284:1284:1284)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1315:1315:1315) (1427:1427:1427)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (1396:1396:1396) (1469:1469:1469)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1812:1812:1812) (1971:1971:1971)) + (PORT datab (1021:1021:1021) (1141:1141:1141)) + (PORT datac (782:782:782) (892:892:892)) + (PORT datad (790:790:790) (893:893:893)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (954:954:954)) + (PORT datab (199:199:199) (236:236:236)) + (PORT datac (1395:1395:1395) (1469:1469:1469)) + (PORT datad (994:994:994) (1100:1100:1100)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (265:265:265)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1233:1233:1233) (1279:1279:1279)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datac (988:988:988) (1107:1107:1107)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1540:1540:1540)) + (PORT d (1841:1841:1841) (1973:1973:1973)) + (PORT ena (1809:1809:1809) (1846:1846:1846)) + (IOPATH (posedge clk) q (586:586:586) (589:589:589)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (82:82:82)) + (SETUP ena (posedge clk) (82:82:82)) + (HOLD d (posedge clk) (97:97:97)) + (HOLD ena (posedge clk) (97:97:97)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux21\~1) + (DELAY + (ABSOLUTE + (PORT dataa (696:696:696) (743:743:743)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (194:194:194) (226:226:226)) + (PORT datad (638:638:638) (663:663:663)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1539:1539:1539)) + (PORT d (1556:1556:1556) (1651:1651:1651)) + (PORT ena (1611:1611:1611) (1629:1629:1629)) + (IOPATH (posedge clk) q (586:586:586) (589:589:589)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (82:82:82)) + (SETUP ena (posedge clk) (82:82:82)) + (HOLD d (posedge clk) (97:97:97)) + (HOLD ena (posedge clk) (97:97:97)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~4) + (DELAY + (ABSOLUTE + (PORT dataa (748:748:748) (867:867:867)) + (PORT datab (781:781:781) (871:871:871)) + (PORT datad (273:273:273) (355:355:355)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1010:1010:1010) (1114:1114:1114)) + (PORT datab (2651:2651:2651) (2850:2850:2850)) + (PORT datac (1684:1684:1684) (1854:1854:1854)) + (PORT datad (931:931:931) (983:983:983)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~7) + (DELAY + (ABSOLUTE + (PORT dataa (799:799:799) (926:926:926)) + (PORT datab (897:897:897) (930:930:930)) + (PORT datac (1265:1265:1265) (1390:1390:1390)) + (PORT datad (820:820:820) (839:839:839)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1032:1032:1032) (1126:1126:1126)) + (PORT datab (959:959:959) (1003:1003:1003)) + (PORT datac (1256:1256:1256) (1370:1370:1370)) + (PORT datad (1256:1256:1256) (1321:1321:1321)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1285:1285:1285) (1370:1370:1370)) + (PORT datab (658:658:658) (687:687:687)) + (PORT datac (589:589:589) (593:593:593)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1285:1285:1285) (1362:1362:1362)) + (PORT datab (660:660:660) (691:691:691)) + (PORT datac (588:588:588) (590:590:590)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH dataa combout (341:341:341) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~11) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (492:492:492)) + (PORT datab (904:904:904) (946:946:946)) + (PORT datac (312:312:312) (339:339:339)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[4\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1561:1561:1561)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (684:684:684) (700:700:700)) + (PORT sload (1665:1665:1665) (1784:1784:1784)) + (PORT ena (980:980:980) (972:972:972)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~12) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (813:813:813)) + (PORT datab (2069:2069:2069) (2248:2248:2248)) + (PORT datac (2283:2283:2283) (2471:2471:2471)) + (PORT datad (867:867:867) (902:902:902)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~5) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (654:654:654) (706:706:706)) + (PORT datac (1578:1578:1578) (1695:1695:1695)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~6) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (658:658:658)) + (PORT datab (905:905:905) (948:948:948)) + (PORT datac (994:994:994) (1085:1085:1085)) + (PORT datad (378:378:378) (448:448:448)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[4\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1283:1283:1283) (1363:1363:1363)) + (PORT datab (616:616:616) (667:667:667)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[4\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT datab (1089:1089:1089) (1165:1165:1165)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1542:1542:1542)) + (PORT d (1700:1700:1700) (1761:1761:1761)) + (PORT ena (2295:2295:2295) (2346:2346:2346)) + (IOPATH (posedge clk) q (586:586:586) (589:589:589)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (82:82:82)) + (SETUP ena (posedge clk) (82:82:82)) + (HOLD d (posedge clk) (97:97:97)) + (HOLD ena (posedge clk) (97:97:97)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~1) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (869:869:869)) + (PORT datab (781:781:781) (872:872:872)) + (PORT datac (630:630:630) (679:679:679)) + (PORT datad (274:274:274) (354:354:354)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1285:1285:1285) (1367:1367:1367)) + (PORT datac (589:589:589) (593:593:593)) + (PORT datad (598:598:598) (611:611:611)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1289:1289:1289) (1364:1364:1364)) + (PORT datab (1055:1055:1055) (1148:1148:1148)) + (PORT datac (1259:1259:1259) (1369:1369:1369)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1285:1285:1285) (1371:1371:1371)) + (PORT datab (1057:1057:1057) (1150:1150:1150)) + (PORT datac (1257:1257:1257) (1371:1371:1371)) + (PORT datad (181:181:181) (211:211:211)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1377:1377:1377) (1426:1426:1426)) + (PORT datab (404:404:404) (482:482:482)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[5\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1561:1561:1561)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (524:524:524) (559:559:559)) + (PORT sload (1665:1665:1665) (1784:1784:1784)) + (PORT ena (980:980:980) (972:972:972)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~2) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (889:889:889) (939:939:939)) + (PORT datac (1575:1575:1575) (1696:1696:1696)) + (PORT datad (635:635:635) (714:714:714)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~3) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (656:656:656)) + (PORT datab (1058:1058:1058) (1148:1148:1148)) + (PORT datac (1348:1348:1348) (1386:1386:1386)) + (PORT datad (380:380:380) (445:445:445)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[5\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1290:1290:1290) (1371:1371:1371)) + (PORT datab (642:642:642) (688:688:688)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[5\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (1091:1091:1091) (1170:1170:1170)) + (PORT datac (181:181:181) (218:218:218)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1539:1539:1539)) + (PORT d (1443:1443:1443) (1520:1520:1520)) + (PORT ena (2198:2198:2198) (2202:2202:2202)) + (IOPATH (posedge clk) q (586:586:586) (589:589:589)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (82:82:82)) + (SETUP ena (posedge clk) (82:82:82)) + (HOLD d (posedge clk) (97:97:97)) + (HOLD ena (posedge clk) (97:97:97)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux18\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2415:2415:2415) (2626:2626:2626)) + (PORT datac (1237:1237:1237) (1358:1358:1358)) + (PORT datad (667:667:667) (699:699:699)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1539:1539:1539)) + (PORT d (1527:1527:1527) (1623:1623:1623)) + (PORT ena (1611:1611:1611) (1629:1629:1629)) + (IOPATH (posedge clk) q (586:586:586) (589:589:589)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (82:82:82)) + (SETUP ena (posedge clk) (82:82:82)) + (HOLD d (posedge clk) (97:97:97)) + (HOLD ena (posedge clk) (97:97:97)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2411:2411:2411) (2624:2624:2624)) + (PORT datac (1497:1497:1497) (1597:1597:1597)) + (PORT datad (667:667:667) (698:698:698)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1537:1537:1537)) + (PORT d (1993:1993:1993) (2101:2101:2101)) + (PORT ena (1609:1609:1609) (1676:1676:1676)) + (IOPATH (posedge clk) q (586:586:586) (589:589:589)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (82:82:82)) + (SETUP ena (posedge clk) (82:82:82)) + (HOLD d (posedge clk) (97:97:97)) + (HOLD ena (posedge clk) (97:97:97)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux16\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2422:2422:2422) (2635:2635:2635)) + (PORT datac (243:243:243) (322:322:322)) + (PORT datad (667:667:667) (698:698:698)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1495:1495:1495) (1520:1520:1520)) + (PORT d (2142:2142:2142) (2266:2266:2266)) + (PORT ena (1415:1415:1415) (1456:1456:1456)) + (IOPATH (posedge clk) q (617:617:617) (612:612:612)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (80:80:80)) + (SETUP ena (posedge clk) (80:80:80)) + (HOLD d (posedge clk) (101:101:101)) + (HOLD ena (posedge clk) (101:101:101)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux15\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2424:2424:2424) (2635:2635:2635)) + (PORT datab (933:933:933) (1032:1032:1032)) + (PORT datad (667:667:667) (702:702:702)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1497:1497:1497) (1522:1522:1522)) + (PORT d (2142:2142:2142) (2261:2261:2261)) + (PORT ena (1453:1453:1453) (1505:1505:1505)) + (IOPATH (posedge clk) q (617:617:617) (612:612:612)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (80:80:80)) + (SETUP ena (posedge clk) (80:80:80)) + (HOLD d (posedge clk) (101:101:101)) + (HOLD ena (posedge clk) (101:101:101)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (737:737:737)) + (PORT datab (711:711:711) (800:800:800)) + (PORT datac (1260:1260:1260) (1352:1352:1352)) + (PORT datad (181:181:181) (207:207:207)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~1) + (DELAY + (ABSOLUTE + (PORT dataa (686:686:686) (729:729:729)) + (PORT datab (407:407:407) (478:478:478)) + (PORT datac (1035:1035:1035) (1137:1137:1137)) + (PORT datad (627:627:627) (654:654:654)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[10\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (993:993:993) (1068:1068:1068)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[10\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1560:1560:1560)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (523:523:523) (557:557:557)) + (PORT sload (1639:1639:1639) (1751:1751:1751)) + (PORT ena (1247:1247:1247) (1254:1254:1254)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~4) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (923:923:923)) + (PORT datab (406:406:406) (476:476:476)) + (PORT datac (676:676:676) (747:747:747)) + (PORT datad (675:675:675) (725:725:725)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~2) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (740:740:740)) + (PORT datab (712:712:712) (801:801:801)) + (PORT datac (1257:1257:1257) (1357:1357:1357)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~3) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (406:406:406) (474:474:474)) + (PORT datac (381:381:381) (407:407:407)) + (PORT datad (632:632:632) (657:657:657)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[10\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT datab (1064:1064:1064) (1139:1139:1139)) + (PORT datac (181:181:181) (217:217:217)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1488:1488:1488) (1513:1513:1513)) + (PORT d (1458:1458:1458) (1539:1539:1539)) + (PORT ena (1669:1669:1669) (1698:1698:1698)) + (IOPATH (posedge clk) q (617:617:617) (612:612:612)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (80:80:80)) + (SETUP ena (posedge clk) (80:80:80)) + (HOLD d (posedge clk) (101:101:101)) + (HOLD ena (posedge clk) (101:101:101)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (766:766:766) (848:848:848)) + (PORT datac (1262:1262:1262) (1381:1381:1381)) + (PORT datad (735:735:735) (822:822:822)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1000:1000:1000) (1091:1091:1091)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (225:225:225) (305:305:305)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (341:341:341) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_2feeder) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (266:266:266)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_2) + (DELAY + (ABSOLUTE + (PORT clk (1536:1536:1536) (1559:1559:1559)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (530:530:530) (570:570:570)) + (PORT sload (1322:1322:1322) (1457:1457:1457)) + (PORT ena (1290:1290:1290) (1318:1318:1318)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~10) + (DELAY + (ABSOLUTE + (PORT datab (249:249:249) (334:334:334)) + (PORT datac (768:768:768) (884:884:884)) + (PORT datad (677:677:677) (777:777:777)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~6) + (DELAY + (ABSOLUTE + (PORT dataa (793:793:793) (920:920:920)) + (PORT datab (895:895:895) (926:926:926)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (818:818:818) (836:836:836)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (270:270:270)) + (PORT datab (737:737:737) (847:847:847)) + (PORT datac (189:189:189) (231:231:231)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1502:1502:1502) (1530:1530:1530)) + (PORT d (1252:1252:1252) (1354:1354:1354)) + (PORT ena (1396:1396:1396) (1412:1412:1412)) + (IOPATH (posedge clk) q (617:617:617) (612:612:612)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (80:80:80)) + (SETUP ena (posedge clk) (80:80:80)) + (HOLD d (posedge clk) (101:101:101)) + (HOLD ena (posedge clk) (101:101:101)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_1SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (267:267:267)) + (PORT datab (738:738:738) (843:843:843)) + (PORT datac (187:187:187) (229:229:229)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1493:1493:1493) (1518:1518:1518)) + (PORT d (1706:1706:1706) (1798:1798:1798)) + (PORT ena (1700:1700:1700) (1737:1737:1737)) + (IOPATH (posedge clk) q (617:617:617) (612:612:612)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (80:80:80)) + (SETUP ena (posedge clk) (80:80:80)) + (HOLD d (posedge clk) (101:101:101)) + (HOLD ena (posedge clk) (101:101:101)) + ) + ) ) diff --git a/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo b/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo index 1f3d9fd..749c3f8 100644 --- a/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo +++ b/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "04/01/2022 18:55:51" +// DATE "04/02/2022 14:51:20" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -50,14 +50,24 @@ module spectrum ( SW, GPIO_1, buzzer_out, - raw_loader_in); + raw_loader_in, + DRAM_BA, + DRAM_DQM, + DRAM_RAS_N, + DRAM_CAS_N, + DRAM_CKE, + DRAM_CLK, + DRAM_WE_N, + DRAM_CS_N, + DRAM_DQ, + DRAM_ADDR); output [7:0] LED; input CLOCK_50; input [1:0] KEY; input PS2_CLK; input PS2_DAT; -output I2C_SCLK; -output I2C_SDAT; +inout I2C_SCLK; +inout I2C_SDAT; output AUD_XCK; output AUD_ADCLRCK; output AUD_DACLRCK; @@ -73,6 +83,16 @@ input [3:0] SW; output [33:0] GPIO_1; output buzzer_out; input raw_loader_in; +output [1:0] DRAM_BA; +output [1:0] DRAM_DQM; +output DRAM_RAS_N; +output DRAM_CAS_N; +output DRAM_CKE; +output DRAM_CLK; +output DRAM_WE_N; +output DRAM_CS_N; +inout [15:0] DRAM_DQ; +output [12:0] DRAM_ADDR; // Design Ports Information // LED[0] => Location: PIN_A15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -139,8 +159,47 @@ input raw_loader_in; // GPIO_1[32] => Location: PIN_J13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // GPIO_1[33] => Location: PIN_J14, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // buzzer_out => Location: PIN_A6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_BA[0] => Location: PIN_M7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_BA[1] => Location: PIN_M6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQM[0] => Location: PIN_R6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQM[1] => Location: PIN_T5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_RAS_N => Location: PIN_L2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_CAS_N => Location: PIN_L1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_CKE => Location: PIN_L7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_CLK => Location: PIN_R4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_WE_N => Location: PIN_C2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_CS_N => Location: PIN_P6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[0] => Location: PIN_P2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[1] => Location: PIN_N5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[2] => Location: PIN_N6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[3] => Location: PIN_M8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[4] => Location: PIN_P8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[5] => Location: PIN_T7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[6] => Location: PIN_N8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[7] => Location: PIN_T6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[8] => Location: PIN_R1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[9] => Location: PIN_P1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[10] => Location: PIN_N2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[11] => Location: PIN_N1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_ADDR[12] => Location: PIN_L4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // I2C_SCLK => Location: PIN_F2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // I2C_SDAT => Location: PIN_F1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[0] => Location: PIN_G2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[1] => Location: PIN_G1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[2] => Location: PIN_L8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[3] => Location: PIN_K5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[4] => Location: PIN_K2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[5] => Location: PIN_J2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[6] => Location: PIN_J1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[7] => Location: PIN_R7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[8] => Location: PIN_T4, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[9] => Location: PIN_T2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[10] => Location: PIN_T3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[11] => Location: PIN_R3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[12] => Location: PIN_R5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[13] => Location: PIN_P3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[14] => Location: PIN_N3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +// DRAM_DQ[15] => Location: PIN_K1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA // SW[1] => Location: PIN_T8, I/O Standard: 3.3-V LVTTL, Current Strength: Default // SW[2] => Location: PIN_B9, I/O Standard: 3.3-V LVTTL, Current Strength: Default // raw_loader_in => Location: PIN_B6, I/O Standard: 3.3-V LVTTL, Current Strength: Default @@ -170,6 +229,22 @@ initial $sdf_annotate("spectrum_min_1200mv_0c_v_fast.sdo"); wire \SW[0]~input_o ; wire \SW[3]~input_o ; wire \I2C_SCLK~input_o ; +wire \DRAM_DQ[0]~input_o ; +wire \DRAM_DQ[1]~input_o ; +wire \DRAM_DQ[2]~input_o ; +wire \DRAM_DQ[3]~input_o ; +wire \DRAM_DQ[4]~input_o ; +wire \DRAM_DQ[5]~input_o ; +wire \DRAM_DQ[6]~input_o ; +wire \DRAM_DQ[7]~input_o ; +wire \DRAM_DQ[8]~input_o ; +wire \DRAM_DQ[9]~input_o ; +wire \DRAM_DQ[10]~input_o ; +wire \DRAM_DQ[11]~input_o ; +wire \DRAM_DQ[12]~input_o ; +wire \DRAM_DQ[13]~input_o ; +wire \DRAM_DQ[14]~input_o ; +wire \DRAM_DQ[15]~input_o ; wire \CLOCK_50~input_o ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_fbout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ; @@ -178,692 +253,8 @@ wire \SW[2]~input_o ; wire \ula_|clocks_|clk_cpu~0_combout ; wire \ula_|clocks_|clk_cpu~q ; wire \ula_|clocks_|clk_cpu~clkctrl_outclk ; -wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; -wire \z80_|sequencer_|ena_M~combout ; wire \KEY[1]~input_o ; wire \z80_|interrupts_|nmi_armed~feeder_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; -wire \z80_|interrupts_|nmi_armed~q ; -wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ; -wire \z80_|execute_|ctl_eval_cond~0_combout ; -wire \z80_|execute_|ixy_d~4_combout ; -wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M3_ff~q ; -wire \z80_|execute_|fIOWrite~1_combout ; -wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M4_ff~q ; -wire \z80_|pla_decode_|Equal32~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; -wire \z80_|decode_state_|table_xx~0_combout ; -wire \z80_|pla_decode_|Equal1~7_combout ; -wire \z80_|pla_decode_|Equal2~0_combout ; -wire \z80_|pla_decode_|Equal36~0_combout ; -wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; -wire \z80_|execute_|ctl_state_tbl_we~8_combout ; -wire \z80_|decode_state_|DFFE_instCB~q ; -wire \z80_|pla_decode_|Equal52~0_combout ; -wire \z80_|pla_decode_|Equal2~1_combout ; -wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; -wire \z80_|decode_state_|DFFE_instED~q ; -wire \z80_|pla_decode_|Equal13~0_combout ; -wire \z80_|pla_decode_|Equal33~0_combout ; -wire \z80_|execute_|ctl_im_we~combout ; -wire \z80_|pla_decode_|Equal49~0_combout ; -wire \z80_|pla_decode_|Equal33~1_combout ; -wire \z80_|pla_decode_|Equal6~0_combout ; -wire \z80_|execute_|ctl_mRead~14_combout ; -wire \z80_|pla_decode_|Equal12~0_combout ; -wire \z80_|execute_|ctl_sw_1d~8_combout ; -wire \z80_|nM1_int~2_combout ; -wire \z80_|execute_|ctl_sw_1d~5_combout ; -wire \z80_|pla_decode_|Equal3~0_combout ; -wire \z80_|execute_|ctl_mRead~4_combout ; -wire \z80_|execute_|ixy_d~7_combout ; -wire \z80_|execute_|ctl_state_alu~4_combout ; -wire \z80_|execute_|ctl_sw_1d~4_combout ; -wire \z80_|pla_decode_|Equal40~1_combout ; -wire \z80_|pla_decode_|Equal39~0_combout ; -wire \z80_|execute_|ctl_bus_db_oe~1_combout ; -wire \z80_|pla_decode_|Equal13~1_combout ; -wire \z80_|pla_decode_|Equal13~2_combout ; -wire \z80_|pla_decode_|Equal3~2_combout ; -wire \z80_|execute_|ctl_state_iy_set~2_combout ; -wire \z80_|execute_|ixy_d~8_combout ; -wire \z80_|execute_|ixy_d~6_combout ; -wire \z80_|execute_|ixy_d~9_combout ; -wire \z80_|execute_|ixy_d~12_combout ; -wire \z80_|execute_|ixy_d~10_combout ; -wire \z80_|pla_decode_|Equal44~0_combout ; -wire \z80_|execute_|ixy_d~16_combout ; -wire \z80_|execute_|ixy_d~13_combout ; -wire \z80_|pla_decode_|Equal50~0_combout ; -wire \z80_|pla_decode_|Equal33~2_combout ; -wire \z80_|execute_|ixy_d~17_combout ; -wire \z80_|execute_|ixy_d~5_combout ; -wire \z80_|execute_|ixy_d~14_combout ; -wire \z80_|execute_|ixy_d~11_combout ; -wire \z80_|execute_|ixy_d~15_combout ; -wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; -wire \z80_|decode_state_|DFFE_instIY1~q ; -wire \z80_|execute_|ctl_ir_we~5_combout ; -wire \z80_|execute_|ctl_ir_we~14_combout ; -wire \z80_|execute_|ctl_mWrite~2_combout ; -wire \z80_|execute_|ctl_mWrite~16_combout ; -wire \z80_|execute_|ctl_flags_alu~18_combout ; -wire \z80_|execute_|ctl_mRead~26_combout ; -wire \z80_|execute_|ctl_mRead~27_combout ; -wire \z80_|execute_|ctl_bus_db_oe~7_combout ; -wire \z80_|execute_|ctl_sw_2d~5_combout ; -wire \z80_|execute_|ctl_mRead~18_combout ; -wire \z80_|pla_decode_|Equal55~0_combout ; -wire \z80_|execute_|comb~1_combout ; -wire \z80_|execute_|ctl_mRead~15_combout ; -wire \z80_|execute_|ctl_mRead~17_combout ; -wire \z80_|execute_|ctl_reg_in_hi~5_combout ; -wire \z80_|execute_|ctl_mRead~9_combout ; -wire \z80_|pla_decode_|Equal9~0_combout ; -wire \z80_|execute_|ctl_mRead~10_combout ; -wire \z80_|execute_|ctl_mRead~8_combout ; -wire \z80_|execute_|ctl_mRead~20_combout ; -wire \z80_|pla_decode_|Equal12~1_combout ; -wire \z80_|pla_decode_|Equal9~1_combout ; -wire \z80_|pla_decode_|Equal25~0_combout ; -wire \z80_|execute_|ctl_mRead~21_combout ; -wire \z80_|execute_|ctl_state_alu~6_combout ; -wire \z80_|pla_decode_|Equal19~0_combout ; -wire \z80_|pla_decode_|Equal1~4_combout ; -wire \z80_|pla_decode_|Equal29~0_combout ; -wire \z80_|pla_decode_|Equal24~1_combout ; -wire \z80_|pla_decode_|Equal34~0_combout ; -wire \z80_|pla_decode_|Equal37~0_combout ; -wire \z80_|pla_decode_|Equal35~0_combout ; -wire \z80_|pla_decode_|Equal38~2_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; -wire \z80_|execute_|comb~0_combout ; -wire \z80_|pla_decode_|Equal47~0_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; -wire \z80_|execute_|ctl_mRead~22_combout ; -wire \z80_|execute_|ctl_mRead~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_in_hi~6_combout ; -wire \z80_|pla_decode_|Equal6~1_combout ; -wire \z80_|execute_|ctl_mRead~16_combout ; -wire \z80_|sequencer_|M5~0_combout ; -wire \z80_|sequencer_|M5~q ; -wire \z80_|execute_|ctl_reg_in_hi~2_combout ; -wire \z80_|execute_|setM1~29_combout ; -wire \z80_|execute_|ctl_mRead~25_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; -wire \z80_|execute_|ctl_ir_we~7_combout ; -wire \z80_|pla_decode_|Equal52~1_combout ; -wire \z80_|execute_|ctl_state_alu~14_combout ; -wire \z80_|execute_|ctl_state_alu~8_combout ; -wire \z80_|pla_decode_|Equal24~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~1_combout ; -wire \z80_|reg_control_|reg_sel_pc~2_combout ; -wire \z80_|execute_|fMRead~17_combout ; -wire \z80_|execute_|ctl_mRead~6_combout ; -wire \z80_|pla_decode_|Equal11~0_combout ; -wire \z80_|pla_decode_|Equal10~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; -wire \z80_|execute_|ctl_sw_2d~4_combout ; -wire \z80_|execute_|ctl_ir_we~15_combout ; -wire \z80_|execute_|fMRead~16_combout ; -wire \z80_|execute_|ctl_ir_we~9_combout ; -wire \z80_|pla_decode_|Equal46~0_combout ; -wire \z80_|execute_|ctl_ir_we~10_combout ; -wire \z80_|execute_|ctl_flags_alu~17_combout ; -wire \z80_|execute_|ctl_flags_alu~6_combout ; -wire \z80_|execute_|ctl_ir_we~6_combout ; -wire \z80_|execute_|ctl_ir_we~8_combout ; -wire \z80_|execute_|ctl_flags_alu~16_combout ; -wire \z80_|execute_|ctl_reg_in_hi~3_combout ; -wire \z80_|execute_|ctl_mWrite~8_combout ; -wire \z80_|execute_|fMRead~18_combout ; -wire \z80_|execute_|fMRead~19_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; -wire \z80_|execute_|ctl_mRead~36_combout ; -wire \z80_|execute_|ctl_alu_op_low~9_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; -wire \z80_|execute_|ctl_mRead~11_combout ; -wire \z80_|execute_|ctl_sw_2d~6_combout ; -wire \z80_|execute_|ctl_sw_2d~7_combout ; -wire \z80_|execute_|ctl_mWrite~7_combout ; -wire \z80_|execute_|ctl_ir_we~11_combout ; -wire \z80_|execute_|ctl_ir_we~12_combout ; -wire \z80_|execute_|ctl_flags_sz_we~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; -wire \z80_|execute_|ctl_sw_2d~8_combout ; -wire \z80_|execute_|ctl_sw_2d~9_combout ; -wire \z80_|execute_|ctl_sw_1d~6_combout ; -wire \z80_|execute_|ctl_sw_1d~7_combout ; -wire \z80_|execute_|ctl_alu_op_low~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; -wire \z80_|execute_|ctl_reg_out_hi~4_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; -wire \z80_|alu_|db_low[2]~4_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ; -wire \z80_|execute_|ctl_sw_4u~1_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; -wire \z80_|pla_decode_|Equal69~0_combout ; -wire \z80_|pla_decode_|Equal1~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~14_combout ; -wire \z80_|execute_|ctl_alu_op_low~12_combout ; -wire \z80_|pla_decode_|Equal56~0_combout ; -wire \z80_|execute_|ctl_alu_op_low~11_combout ; -wire \z80_|execute_|nextM~2_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~5_combout ; -wire \z80_|execute_|ctl_alu_oe~3_combout ; -wire \z80_|execute_|ctl_alu_op_low~15_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; -wire \z80_|execute_|ctl_alu_core_R~3_combout ; -wire \z80_|execute_|ctl_alu_core_R~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; -wire \z80_|pla_decode_|Equal48~0_combout ; -wire \z80_|execute_|ctl_flags_hf2_we~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; -wire \z80_|execute_|ctl_flags_xy_we~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; -wire \z80_|execute_|ctl_iorw~10_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~13_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; -wire \z80_|execute_|ctl_bus_db_oe~3_combout ; -wire \z80_|pla_decode_|Equal20~0_combout ; -wire \z80_|pla_decode_|Equal68~2_combout ; -wire \z80_|execute_|ctl_flags_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op_low~13_combout ; -wire \z80_|execute_|ctl_flags_bus~15_combout ; -wire \z80_|execute_|ctl_flags_bus~11_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ; -wire \z80_|execute_|ctl_flags_bus~10_combout ; -wire \z80_|execute_|ctl_flags_bus~8_combout ; -wire \z80_|execute_|ctl_flags_bus~9_combout ; -wire \z80_|execute_|ctl_flags_bus~12_combout ; -wire \z80_|execute_|ctl_flags_xy_we~11_combout ; -wire \z80_|execute_|ctl_flags_xy_we~12_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; -wire \z80_|execute_|ctl_ir_we~4_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; -wire \z80_|execute_|ctl_bus_db_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; -wire \z80_|execute_|ctl_66_oe~2_combout ; -wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; -wire \z80_|execute_|ctl_alu_op_low~10_combout ; -wire \z80_|execute_|fMWrite~11_combout ; -wire \z80_|execute_|ctl_alu_op_low~21_combout ; -wire \z80_|execute_|ctl_alu_op_low~22_combout ; -wire \z80_|execute_|ctl_alu_op_low~16_combout ; -wire \z80_|execute_|ctl_alu_op_low~17_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; -wire \z80_|execute_|ctl_reg_gp_sel~36_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~4_combout ; -wire \z80_|execute_|ctl_state_alu~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~18_combout ; -wire \z80_|execute_|ctl_alu_op_low~19_combout ; -wire \z80_|execute_|ctl_alu_op_low~33_combout ; -wire \z80_|execute_|ctl_alu_op_low~20_combout ; -wire \z80_|execute_|ctl_alu_op_low~23_combout ; -wire \z80_|execute_|ctl_alu_op_low~24_combout ; -wire \z80_|execute_|ctl_alu_op_low~25_combout ; -wire \z80_|execute_|ctl_alu_op_low~34_combout ; -wire \z80_|execute_|ctl_alu_op_low~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~14_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; -wire \z80_|execute_|ctl_reg_use_sp~0_combout ; -wire \z80_|execute_|ctl_reg_use_sp~1_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; -wire \z80_|execute_|ctl_reg_in_lo~9_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; -wire \z80_|execute_|ctl_flags_xy_we~8_combout ; -wire \z80_|execute_|ctl_flags_xy_we~9_combout ; -wire \z80_|pla_decode_|Equal8~0_combout ; -wire \z80_|execute_|ctl_flags_alu~9_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; -wire \z80_|execute_|ctl_flags_sz_we~3_combout ; -wire \z80_|pla_decode_|Equal11~1_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; -wire \z80_|execute_|ctl_flags_alu~10_combout ; -wire \z80_|execute_|ctl_flags_alu~11_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; -wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; -wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; -wire \z80_|execute_|ctl_flags_cf_we~7_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~2_combout ; -wire \z80_|execute_|ctl_alu_oe~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~25_combout ; -wire \z80_|execute_|ctl_flags_hf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; -wire \z80_|execute_|ctl_flags_pf_we~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~3_combout ; -wire \z80_|execute_|ctl_flags_xy_we~17_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; -wire \z80_|execute_|ctl_flags_xy_we~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; -wire \z80_|execute_|ctl_state_alu~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~1_combout ; -wire \z80_|execute_|ctl_flags_cf_we~2_combout ; -wire \z80_|execute_|ctl_alu_core_S~6_combout ; -wire \z80_|execute_|ctl_alu_core_S~7_combout ; -wire \z80_|execute_|ctl_alu_core_S~4_combout ; -wire \z80_|execute_|ctl_alu_core_S~5_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; -wire \z80_|execute_|ctl_alu_res_oe~0_combout ; -wire \z80_|execute_|ctl_alu_oe~15_combout ; -wire \z80_|execute_|ctl_alu_res_oe~1_combout ; -wire \z80_|execute_|ctl_alu_res_oe~2_combout ; -wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; -wire \z80_|alu_|db_high[3]~2_combout ; -wire \z80_|alu_|db_high[3]~3_combout ; -wire \z80_|alu_|db_low[2]~24_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~7_combout ; -wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_in_hi~8_combout ; -wire \z80_|execute_|ctl_alu_oe~8_combout ; -wire \z80_|execute_|ctl_alu_oe~4_combout ; -wire \z80_|execute_|ctl_mWrite~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~10_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; -wire \z80_|execute_|ctl_bus_db_we~5_combout ; -wire \z80_|execute_|ctl_alu_oe~9_combout ; -wire \z80_|execute_|ctl_alu_oe~11_combout ; -wire \z80_|execute_|ctl_alu_oe~5_combout ; -wire \z80_|execute_|ctl_alu_core_S~11_combout ; -wire \z80_|execute_|ctl_alu_oe~6_combout ; -wire \z80_|execute_|ctl_alu_oe~7_combout ; -wire \z80_|execute_|ctl_alu_oe~12_combout ; -wire \z80_|execute_|ctl_alu_oe~13_combout ; -wire \z80_|execute_|ctl_alu_oe~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ; -wire \z80_|execute_|ctl_reg_out_hi~8_combout ; -wire \z80_|execute_|setM1~54_combout ; -wire \z80_|execute_|ctl_sw_2u~1_combout ; -wire \z80_|execute_|ctl_sw_2u~4_combout ; -wire \z80_|execute_|ctl_sw_2u~5_combout ; -wire \z80_|execute_|ctl_sw_2u~6_combout ; -wire \z80_|execute_|ctl_inc_cy~35_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; -wire \z80_|execute_|ctl_mWrite~6_combout ; -wire \z80_|execute_|ctl_sw_2u~2_combout ; -wire \z80_|execute_|ctl_sw_2u~0_combout ; -wire \z80_|execute_|ctl_sw_2u~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; -wire \z80_|execute_|ctl_reg_out_lo~2_combout ; -wire \z80_|execute_|rsel3~combout ; -wire \z80_|execute_|ctl_reg_out_hi~5_combout ; -wire \z80_|execute_|ctl_reg_out_hi~6_combout ; -wire \z80_|execute_|ctl_reg_out_hi~7_combout ; -wire \z80_|execute_|rsel0~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ; -wire \z80_|execute_|ctl_reg_out_lo~6_combout ; -wire \z80_|execute_|ctl_reg_out_lo~7_combout ; -wire \z80_|execute_|ctl_iorw~11_combout ; -wire \z80_|execute_|ctl_sw_2d~10_combout ; -wire \z80_|execute_|ctl_sw_2d~14_combout ; -wire \z80_|execute_|ctl_sw_2d~11_combout ; -wire \z80_|execute_|ctl_sw_2d~12_combout ; -wire \z80_|execute_|ctl_sw_2d~13_combout ; -wire \z80_|execute_|ctl_66_oe~combout ; -wire \z80_|execute_|ctl_inc_cy~34_combout ; -wire \z80_|execute_|ctl_apin_mux~0_combout ; -wire \z80_|execute_|ctl_sw_4u~5_combout ; -wire \z80_|execute_|ctl_inc_cy~75_combout ; -wire \z80_|execute_|ctl_inc_cy~76_combout ; -wire \z80_|pla_decode_|Equal4~0_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; -wire \z80_|execute_|ctl_inc_cy~53_combout ; -wire \z80_|execute_|ctl_inc_cy~92_combout ; -wire \z80_|pla_decode_|Equal19~1_combout ; -wire \z80_|execute_|ctl_sw_4u~0_combout ; -wire \z80_|execute_|ctl_inc_cy~38_combout ; -wire \z80_|execute_|ctl_inc_cy~93_combout ; -wire \z80_|execute_|ctl_inc_cy~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~24_combout ; -wire \z80_|execute_|ctl_reg_gp_we~1_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; -wire \z80_|execute_|ctl_reg_gp_we~0_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; -wire \z80_|execute_|ctl_sw_4u~2_combout ; -wire \z80_|execute_|ctl_sw_4u~3_combout ; -wire \z80_|execute_|fMRead~3_combout ; -wire \z80_|execute_|ctl_sw_4u~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ; -wire \z80_|execute_|ctl_inc_cy~94_combout ; -wire \z80_|execute_|ctl_inc_cy~87_combout ; -wire \z80_|execute_|ctl_inc_cy~42_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; -wire \z80_|execute_|ctl_sw_4u~6_combout ; -wire \z80_|pla_decode_|Equal2~2_combout ; -wire \z80_|pla_decode_|Equal1~6_combout ; -wire \z80_|reg_control_|bank_exx~2_combout ; -wire \z80_|reg_control_|bank_exx~q ; -wire \z80_|reg_control_|bank_hl_de1~0_combout ; -wire \z80_|reg_control_|bank_hl_de1~q ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~12_combout ; -wire \z80_|execute_|ctl_mRead~7_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~13_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; -wire \z80_|execute_|fMWrite~3_combout ; -wire \z80_|execute_|ctl_flags_bus~5_combout ; -wire \z80_|execute_|fMRead~2_combout ; -wire \z80_|execute_|ctl_mRead~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~7_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; -wire \z80_|execute_|ctl_reg_use_sp~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; -wire \z80_|execute_|ctl_reg_use_sp~3_combout ; -wire \z80_|execute_|ctl_sw_1d~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~21_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~22_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~14_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; -wire \z80_|execute_|setM1~47_combout ; -wire \z80_|execute_|setM1~48_combout ; -wire \z80_|execute_|ctl_al_we~13_combout ; -wire \z80_|execute_|ctl_flags_oe~0_combout ; -wire \z80_|execute_|ctl_flags_oe~1_combout ; -wire \z80_|execute_|ctl_reg_in_hi~13_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; -wire \z80_|execute_|ctl_inc_cy~40_combout ; -wire \z80_|execute_|ctl_inc_dec~2_combout ; -wire \z80_|execute_|ctl_inc_dec~12_combout ; -wire \z80_|execute_|ctl_inc_cy~43_combout ; -wire \z80_|execute_|ctl_inc_dec~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; -wire \z80_|execute_|fMRead~6_combout ; -wire \z80_|execute_|fMRead~7_combout ; -wire \z80_|execute_|fMRead~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; -wire \z80_|execute_|ctl_state_alu~13_combout ; -wire \z80_|execute_|ctl_state_alu~10_combout ; -wire \z80_|execute_|ctl_state_alu~11_combout ; -wire \z80_|execute_|ctl_state_alu~9_combout ; -wire \z80_|pla_decode_|Equal62~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; -wire \z80_|pla_decode_|Equal64~0_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_state_alu~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; -wire \z80_|reg_control_|reg_sel_de2~5_combout ; -wire \z80_|reg_control_|reg_sel_de2~6_combout ; -wire \z80_|reg_control_|reg_sel_hl~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~q ; -wire \z80_|reg_control_|reg_sel_hl2~0_combout ; -wire \z80_|execute_|ctl_reg_in_hi~7_combout ; -wire \z80_|execute_|ctl_reg_gp_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_we~3_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_we~2_combout ; -wire \z80_|execute_|ctl_reg_gp_we~5_combout ; -wire \z80_|execute_|ctl_reg_gp_we~6_combout ; -wire \z80_|execute_|ctl_al_we~14_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; -wire \z80_|execute_|setM1~40_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~93_combout ; -wire \z80_|reg_control_|reg_sel_de~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; -wire \z80_|execute_|ctl_reg_in_hi~9_combout ; -wire \z80_|execute_|ctl_reg_in_hi~10_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; -wire \z80_|execute_|ctl_reg_in_lo~8_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; -wire \z80_|execute_|ctl_reg_use_sp~4_combout ; -wire \z80_|execute_|ctl_reg_use_sp~5_combout ; -wire \z80_|execute_|ctl_reg_use_sp~6_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; -wire \z80_|pla_decode_|Equal21~2_combout ; -wire \z80_|reg_control_|bank_af~0_combout ; -wire \z80_|reg_control_|bank_af~q ; -wire \z80_|reg_control_|reg_sel_af~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|reg_control_|reg_sel_af2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; -wire \z80_|execute_|ctl_flags_bus~4_combout ; -wire \z80_|execute_|ctl_flags_bus~6_combout ; -wire \z80_|execute_|ctl_flags_bus~7_combout ; -wire \z80_|execute_|fMRead~24_combout ; -wire \z80_|execute_|ctl_flags_bus~13_combout ; -wire \z80_|execute_|ctl_flags_bus~combout ; -wire \z80_|execute_|ctl_inc_dec~3_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; -wire \z80_|execute_|ctl_mRead~13_combout ; -wire \z80_|execute_|pc_inc_hold~49_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; -wire \z80_|execute_|pc_inc_hold~28_combout ; -wire \z80_|execute_|setM1~35_combout ; -wire \z80_|execute_|setM1~36_combout ; -wire \z80_|execute_|fMRead~5_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; -wire \z80_|execute_|pc_inc_hold~29_combout ; -wire \z80_|execute_|ctl_reg_sys_we~1_combout ; -wire \z80_|execute_|ctl_reg_sys_we~2_combout ; -wire \z80_|pla_decode_|Equal33~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~2_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~4_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~combout ; -wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; -wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; -wire \z80_|execute_|ctl_reg_out_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; -wire \z80_|execute_|ctl_reg_in_hi~4_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~5_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; -wire \z80_|execute_|ctl_al_we~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; -wire \z80_|execute_|fMRead~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; -wire \z80_|execute_|ctl_inc_dec~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; -wire \z80_|execute_|ctl_al_we~5_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; -wire \z80_|execute_|fMRead~1_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; -wire \z80_|execute_|ctl_inc_cy~77_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; -wire \z80_|execute_|ctl_sw_4d~3_combout ; -wire \z80_|execute_|ctl_sw_4d~4_combout ; -wire \z80_|execute_|ctl_sw_4d~2_combout ; -wire \z80_|execute_|ctl_sw_4d~5_combout ; -wire \z80_|execute_|setM1~45_combout ; -wire \z80_|execute_|setM1~46_combout ; -wire \z80_|execute_|ctl_sw_4d~1_combout ; -wire \z80_|execute_|ctl_sw_4d~0_combout ; -wire \z80_|execute_|ctl_sw_4d~6_combout ; -wire \z80_|execute_|fMRead~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~20_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; -wire \z80_|reg_control_|reg_sel_pc~3_combout ; -wire \z80_|reg_control_|reg_sel_pc~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; -wire \z80_|reg_file_|db_lo_as[0]~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; -wire \z80_|reg_file_|db_lo_as[7]~22_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; -wire \z80_|reg_file_|db_lo_as[7]~23_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; -wire \z80_|resets_|DFFE_intr_ff3~q ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ; wire \KEY[0]~input_o ; wire \reset~combout ; @@ -872,77 +263,13 @@ wire \z80_|fpga_reset~feeder_combout ; wire \z80_|fpga_reset~q ; wire \z80_|fpga_reset~clkctrl_outclk ; wire \z80_|resets_|x1~q ; -wire \z80_|resets_|clrpc_int~0_combout ; -wire \z80_|resets_|clrpc_int~q ; -wire \z80_|resets_|clrpc~0_combout ; -wire \z80_|execute_|ctl_apin_mux~1_combout ; -wire \z80_|execute_|ctl_al_we~6_combout ; -wire \z80_|execute_|ctl_al_we~7_combout ; -wire \z80_|execute_|ctl_al_we~8_combout ; -wire \z80_|execute_|ctl_alu_oe~10_combout ; -wire \z80_|execute_|ctl_al_we~9_combout ; -wire \z80_|execute_|ctl_al_we~10_combout ; -wire \z80_|execute_|ctl_al_we~11_combout ; -wire \z80_|execute_|ctl_al_we~12_combout ; -wire \z80_|execute_|ctl_inc_dec~6_combout ; -wire \z80_|execute_|fIOWrite~0_combout ; -wire \z80_|execute_|ctl_inc_dec~8_combout ; -wire \z80_|execute_|ctl_inc_dec~9_combout ; -wire \z80_|execute_|ctl_inc_dec~10_combout ; -wire \z80_|execute_|ctl_inc_dec~7_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; -wire \z80_|reg_control_|reg_sel_de2~4_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; -wire \z80_|reg_control_|reg_sel_iy~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; -wire \z80_|reg_file_|db_lo_as[2]~7_combout ; -wire \z80_|reg_file_|db_lo_as[2]~8_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; -wire \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; -wire \z80_|reg_file_|db_lo_as[0]~0_combout ; -wire \z80_|reg_file_|db_lo_as[0]~1_combout ; -wire \z80_|execute_|ctl_inc_cy~72_combout ; +wire \z80_|resets_|x3~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; +wire \z80_|interrupts_|nmi_armed~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; -wire \ula_|video_|Add0~15 ; -wire \ula_|video_|Add0~16_combout ; -wire \ula_|video_|vga_hc~2_combout ; -wire \ula_|video_|Add0~17 ; -wire \ula_|video_|Add0~18_combout ; -wire \ula_|video_|vga_hc~1_combout ; wire \ula_|video_|Add0~0_combout ; wire \ula_|video_|vga_hc~3_combout ; wire \ula_|video_|Add0~1 ; @@ -952,12 +279,8 @@ wire \ula_|video_|Add0~3 ; wire \ula_|video_|Add0~4_combout ; wire \ula_|video_|Add0~5 ; wire \ula_|video_|Add0~6_combout ; -wire \ula_|video_|vga_hc[3]~feeder_combout ; wire \ula_|video_|Add0~7 ; wire \ula_|video_|Add0~8_combout ; -wire \ula_|video_|Equal0~0_combout ; -wire \ula_|video_|Equal0~1_combout ; -wire \ula_|video_|Equal1~0_combout ; wire \ula_|video_|Add0~9 ; wire \ula_|video_|Add0~10_combout ; wire \ula_|video_|vga_hc~0_combout ; @@ -965,7 +288,18 @@ wire \ula_|video_|Add0~11 ; wire \ula_|video_|Add0~12_combout ; wire \ula_|video_|Add0~13 ; wire \ula_|video_|Add0~14_combout ; -wire \ula_|video_|Add1~0_combout ; +wire \ula_|video_|Equal0~0_combout ; +wire \ula_|video_|Equal0~1_combout ; +wire \ula_|video_|Add0~15 ; +wire \ula_|video_|Add0~16_combout ; +wire \ula_|video_|vga_hc~2_combout ; +wire \ula_|video_|Add0~17 ; +wire \ula_|video_|Add0~18_combout ; +wire \ula_|video_|vga_hc~1_combout ; +wire \ula_|video_|Equal1~0_combout ; +wire \ula_|video_|Add1~1 ; +wire \ula_|video_|Add1~2_combout ; +wire \ula_|video_|vga_vc[1]~1_combout ; wire \ula_|video_|Add1~3 ; wire \ula_|video_|Add1~4_combout ; wire \ula_|video_|vga_vc[2]~2_combout ; @@ -990,809 +324,1661 @@ wire \ula_|video_|vga_vc[8]~7_combout ; wire \ula_|video_|Add1~17 ; wire \ula_|video_|Add1~18_combout ; wire \ula_|video_|vga_vc[9]~9_combout ; -wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Equal3~0_combout ; +wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Equal3~1_combout ; +wire \ula_|video_|Add1~0_combout ; wire \ula_|video_|vga_vc[0]~0_combout ; -wire \ula_|video_|Add1~1 ; -wire \ula_|video_|Add1~2_combout ; -wire \ula_|video_|vga_vc[1]~1_combout ; -wire \SW[1]~input_o ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; -wire \z80_|pla_decode_|Equal79~0_combout ; -wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \z80_|interrupts_|DFFE_instIFF2~q ; -wire \z80_|interrupts_|iff1~0_combout ; -wire \z80_|interrupts_|iff1~1_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|interrupts_|iff1~q ; wire \ula_|video_|Equal2~1_combout ; wire \ula_|video_|Equal2~2_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ; -wire \z80_|interrupts_|int_armed~q ; -wire \z80_|interrupts_|DFFE_inst44~q ; -wire \z80_|execute_|pc_inc_hold~38_combout ; -wire \z80_|execute_|ctl_inc_cy~91_combout ; -wire \z80_|execute_|pc_inc_hold~45_combout ; -wire \z80_|execute_|pc_inc_hold~44_combout ; -wire \z80_|execute_|pc_inc_hold~46_combout ; -wire \z80_|execute_|pc_inc_hold~37_combout ; -wire \z80_|execute_|pc_inc_hold~50_combout ; -wire \z80_|execute_|pc_inc_hold~33_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; -wire \z80_|execute_|pc_inc_hold~31_combout ; -wire \z80_|execute_|pc_inc_hold~32_combout ; -wire \z80_|execute_|pc_inc_hold~34_combout ; -wire \z80_|execute_|pc_inc_hold~51_combout ; -wire \z80_|execute_|pc_inc_hold~30_combout ; -wire \z80_|execute_|pc_inc_hold~52_combout ; -wire \z80_|execute_|pc_inc_hold~35_combout ; -wire \z80_|execute_|pc_inc_hold~36_combout ; -wire \z80_|execute_|ctl_inc_cy~44_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; -wire \z80_|execute_|ctl_inc_cy~45_combout ; -wire \z80_|execute_|pc_inc_hold~43_combout ; -wire \z80_|execute_|ctl_inc_cy~71_combout ; -wire \z80_|execute_|ctl_inc_cy~73_combout ; +wire \SW[1]~input_o ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; +wire \z80_|execute_|ctl_mWrite~4_combout ; +wire \z80_|pla_decode_|Equal0~0_combout ; +wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M3_ff~q ; +wire \z80_|execute_|ixy_d~6_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ; +wire \z80_|pla_decode_|Equal33~0_combout ; +wire \z80_|execute_|ctl_mRead~5_combout ; +wire \z80_|pla_decode_|Equal77~0_combout ; +wire \z80_|pla_decode_|Equal50~0_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ; +wire \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ; +wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; +wire \z80_|clk_delay_|DFF_inst5~q ; +wire \z80_|clk_delay_|hold_clk_iorq~combout ; +wire \z80_|sequencer_|DFFE_T5_ff~q ; +wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; +wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; +wire \z80_|decode_state_|DFFE_inst4~q ; +wire \z80_|execute_|fMWrite~3_combout ; +wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M4_ff~q ; +wire \z80_|execute_|fMWrite~2_combout ; +wire \z80_|pla_decode_|Equal13~1_combout ; +wire \z80_|pla_decode_|Equal13~2_combout ; +wire \z80_|execute_|ixy_d~4_combout ; +wire \z80_|execute_|fIOWrite~1_combout ; +wire \z80_|execute_|ctl_mWrite~5_combout ; +wire \z80_|execute_|fMRead~2_combout ; +wire \z80_|execute_|ctl_state_alu~2_combout ; +wire \z80_|execute_|ctl_iorw~11_combout ; +wire \z80_|execute_|fIOWrite~2_combout ; +wire \z80_|pla_decode_|Equal2~0_combout ; +wire \z80_|decode_state_|table_xx~0_combout ; +wire \z80_|pla_decode_|Equal1~7_combout ; +wire \z80_|pla_decode_|Equal21~0_combout ; +wire \z80_|execute_|ctl_mRead~3_combout ; +wire \z80_|execute_|fIOWrite~3_combout ; +wire \z80_|execute_|ixy_d~5_combout ; +wire \z80_|execute_|fIOWrite~4_combout ; +wire \z80_|execute_|fIOWrite~5_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; +wire \z80_|execute_|ctl_state_alu~3_combout ; +wire \z80_|pla_decode_|Equal3~1_combout ; +wire \z80_|execute_|ctl_mWrite~6_combout ; +wire \z80_|execute_|ctl_ir_we~4_combout ; +wire \z80_|pla_decode_|Equal9~0_combout ; +wire \z80_|pla_decode_|Equal9~1_combout ; +wire \z80_|execute_|ctl_sw_2u~0_combout ; +wire \z80_|pla_decode_|Equal11~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~14_combout ; wire \z80_|execute_|ctl_inc_cy~46_combout ; -wire \z80_|execute_|pc_inc_hold~53_combout ; -wire \z80_|execute_|pc_inc_hold~39_combout ; -wire \z80_|execute_|pc_inc_hold~47_combout ; -wire \z80_|execute_|ctl_inc_cy~74_combout ; -wire \z80_|execute_|ctl_inc_cy~78_combout ; -wire \z80_|execute_|ctl_inc_cy~79_combout ; -wire \z80_|execute_|ctl_inc_cy~80_combout ; -wire \z80_|execute_|ctl_inc_cy~81_combout ; -wire \z80_|execute_|ctl_inc_cy~82_combout ; -wire \z80_|execute_|ctl_inc_cy~83_combout ; -wire \z80_|execute_|ctl_inc_cy~84_combout ; -wire \z80_|execute_|pc_inc_hold~42_combout ; -wire \z80_|execute_|ctl_inc_cy~90_combout ; -wire \z80_|execute_|pc_inc_hold~41_combout ; -wire \z80_|execute_|ctl_inc_cy~66_combout ; -wire \z80_|execute_|ctl_inc_cy~67_combout ; -wire \z80_|execute_|ctl_inc_cy~68_combout ; -wire \z80_|execute_|ctl_inc_cy~64_combout ; -wire \z80_|execute_|ctl_inc_cy~63_combout ; -wire \z80_|execute_|ctl_inc_cy~65_combout ; -wire \z80_|execute_|ctl_inc_cy~69_combout ; -wire \z80_|execute_|ctl_inc_cy~49_combout ; -wire \z80_|execute_|ctl_inc_cy~50_combout ; -wire \z80_|execute_|ctl_inc_cy~51_combout ; -wire \z80_|execute_|ctl_inc_cy~52_combout ; -wire \z80_|execute_|ctl_inc_cy~36_combout ; -wire \z80_|execute_|ctl_inc_cy~37_combout ; -wire \z80_|execute_|ctl_inc_cy~54_combout ; -wire \z80_|execute_|ctl_inc_cy~41_combout ; -wire \z80_|execute_|ctl_inc_cy~58_combout ; -wire \z80_|execute_|ctl_inc_cy~55_combout ; -wire \z80_|execute_|ctl_inc_cy~56_combout ; -wire \z80_|execute_|ctl_inc_cy~89_combout ; -wire \z80_|execute_|ctl_inc_cy~57_combout ; -wire \z80_|execute_|ctl_inc_cy~59_combout ; -wire \z80_|execute_|ctl_inc_cy~60_combout ; wire \z80_|execute_|ctl_inc_cy~47_combout ; -wire \z80_|execute_|ctl_inc_cy~88_combout ; +wire \z80_|pla_decode_|Equal19~0_combout ; +wire \z80_|pla_decode_|Equal34~0_combout ; +wire \z80_|execute_|comb~0_combout ; +wire \z80_|pla_decode_|Equal47~0_combout ; +wire \z80_|execute_|ctl_inc_cy~45_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; +wire \z80_|sequencer_|M5~0_combout ; +wire \z80_|sequencer_|M5~q ; +wire \z80_|execute_|ctl_alu_oe~2_combout ; +wire \z80_|execute_|ixy_d~7_combout ; +wire \z80_|execute_|ctl_inc_cy~44_combout ; +wire \z80_|execute_|ctl_apin_mux~0_combout ; +wire \z80_|execute_|ctl_mRead~4_combout ; +wire \z80_|execute_|ctl_ir_we~5_combout ; +wire \z80_|execute_|ctl_ir_we~15_combout ; +wire \z80_|execute_|ctl_ir_we~14_combout ; +wire \z80_|execute_|ctl_ir_we~7_combout ; +wire \z80_|execute_|fMWrite~0_combout ; +wire \z80_|execute_|ctl_inc_cy~97_combout ; +wire \z80_|execute_|ctl_inc_cy~96_combout ; +wire \z80_|execute_|ctl_inc_cy~98_combout ; wire \z80_|execute_|ctl_inc_cy~48_combout ; -wire \z80_|execute_|pc_inc_hold~40_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; +wire \z80_|execute_|fMWrite~1_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; +wire \z80_|execute_|ctl_mRead~6_combout ; +wire \z80_|execute_|ctl_reg_in_hi~2_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; +wire \z80_|execute_|ctl_mWrite~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; +wire \z80_|execute_|ctl_mWrite~17_combout ; +wire \z80_|execute_|fMWrite~4_combout ; +wire \z80_|execute_|ctl_state_alu~4_combout ; +wire \z80_|execute_|ctl_inc_cy~49_combout ; +wire \z80_|execute_|ctl_inc_dec~2_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; +wire \z80_|execute_|fMWrite~8_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~51_combout ; +wire \z80_|execute_|ctl_ir_we~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~10_combout ; +wire \z80_|pla_decode_|Equal46~0_combout ; +wire \z80_|execute_|ctl_ir_we~10_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; +wire \z80_|execute_|ctl_ir_we~6_combout ; +wire \z80_|execute_|ctl_ir_we~8_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; +wire \z80_|pla_decode_|Equal55~0_combout ; +wire \z80_|execute_|ctl_mRead~7_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; +wire \z80_|pin_control_|bus_db_pin_oe~17_combout ; +wire \z80_|execute_|fIOWrite~0_combout ; +wire \z80_|execute_|fMWrite~6_combout ; +wire \z80_|execute_|ctl_mWrite~8_combout ; +wire \z80_|execute_|fMWrite~5_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; +wire \z80_|execute_|fMRead~3_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; +wire \z80_|execute_|ctl_sw_4u~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ; +wire \z80_|execute_|fMWrite~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~15_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~16_combout ; +wire \z80_|execute_|ctl_mRead~9_combout ; +wire \z80_|pla_decode_|Equal24~0_combout ; +wire \z80_|execute_|nextM~4_combout ; +wire \z80_|pla_decode_|Equal3~0_combout ; +wire \z80_|execute_|ctl_eval_cond~0_combout ; +wire \z80_|execute_|ctl_iorw~12_combout ; +wire \z80_|execute_|ctl_iorw~8_combout ; +wire \z80_|execute_|ctl_iorw~9_combout ; +wire \z80_|memory_ifc_|DFFE_iorq_ff1~q ; +wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ; +wire \z80_|memory_ifc_|wait_iorq~feeder_combout ; +wire \z80_|memory_ifc_|wait_iorq~q ; +wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; +wire \z80_|memory_ifc_|iorq~0_combout ; +wire \z80_|pla_decode_|Equal33~2_combout ; +wire \z80_|execute_|ixy_d~17_combout ; +wire \z80_|execute_|ctl_mWrite~15_combout ; +wire \z80_|execute_|ctl_mWrite~18_combout ; +wire \z80_|execute_|ctl_mWrite~12_combout ; +wire \z80_|execute_|ctl_flags_alu~21_combout ; +wire \z80_|execute_|ctl_flags_alu~20_combout ; +wire \z80_|execute_|ctl_reg_in_hi~3_combout ; +wire \z80_|execute_|ctl_flags_alu~10_combout ; +wire \z80_|execute_|ctl_mWrite~10_combout ; +wire \z80_|execute_|ctl_mWrite~13_combout ; +wire \z80_|execute_|ixy_d~9_combout ; +wire \z80_|execute_|ctl_inc_cy~51_combout ; +wire \z80_|execute_|ctl_inc_dec~12_combout ; +wire \z80_|execute_|ctl_inc_dec~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; +wire \z80_|execute_|ctl_mWrite~11_combout ; +wire \z80_|execute_|ctl_mRead~25_combout ; +wire \z80_|execute_|ctl_flags_alu~22_combout ; +wire \z80_|execute_|ctl_mRead~24_combout ; +wire \z80_|execute_|ctl_bus_db_oe~7_combout ; +wire \z80_|execute_|ctl_mWrite~14_combout ; +wire \z80_|execute_|ixy_d~8_combout ; +wire \z80_|execute_|ctl_mWrite~16_combout ; +wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; +wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; +wire \z80_|memory_ifc_|wait_mwr~q ; +wire \z80_|memory_ifc_|mwr_wr~feeder_combout ; +wire \z80_|memory_ifc_|mwr_wr~q ; +wire \z80_|memory_ifc_|nWR_out~0_combout ; +wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; +wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; +wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; +wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; +wire \z80_|memory_ifc_|nRD_out~0_combout ; +wire \z80_|execute_|ctl_mRead~2_combout ; +wire \z80_|execute_|fIORead~0_combout ; +wire \z80_|execute_|ctl_iorw~10_combout ; +wire \z80_|pla_decode_|Equal1~4_combout ; +wire \z80_|execute_|ctl_alu_op_low~15_combout ; +wire \z80_|execute_|fIORead~1_combout ; +wire \z80_|execute_|fIORead~2_combout ; +wire \z80_|execute_|fIORead~3_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; +wire \z80_|execute_|ctl_im_we~combout ; +wire \z80_|interrupts_|im2~q ; +wire \z80_|execute_|ctl_mRead~10_combout ; +wire \z80_|pla_decode_|Equal33~3_combout ; +wire \z80_|pla_decode_|Equal6~1_combout ; +wire \z80_|execute_|ctl_mRead~30_combout ; +wire \z80_|execute_|ctl_mRead~31_combout ; +wire \z80_|execute_|ctl_ir_we~12_combout ; +wire \z80_|execute_|ctl_flags_bus~5_combout ; +wire \z80_|pla_decode_|Equal44~0_combout ; +wire \z80_|execute_|ctl_state_alu~6_combout ; +wire \z80_|execute_|fMRead~5_combout ; +wire \z80_|execute_|ctl_mRead~17_combout ; +wire \z80_|execute_|ctl_mRead~12_combout ; +wire \z80_|pla_decode_|Equal49~0_combout ; +wire \z80_|execute_|setM1~57_combout ; +wire \z80_|execute_|ctl_mRead~15_combout ; +wire \z80_|pla_decode_|Equal25~0_combout ; +wire \z80_|pla_decode_|Equal12~1_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; +wire \z80_|execute_|ixy_d~10_combout ; +wire \z80_|execute_|ixy_d~16_combout ; +wire \z80_|execute_|ctl_al_we~4_combout ; +wire \z80_|execute_|fMRead~4_combout ; +wire \z80_|pla_decode_|Equal29~0_combout ; +wire \z80_|execute_|setM1~38_combout ; +wire \z80_|pla_decode_|Equal35~0_combout ; +wire \z80_|execute_|pc_inc_hold~33_combout ; +wire \z80_|execute_|comb~1_combout ; +wire \z80_|execute_|ctl_mRead~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; +wire \z80_|pla_decode_|Equal40~2_combout ; +wire \z80_|execute_|setM1~36_combout ; +wire \z80_|execute_|pc_inc_hold~14_combout ; +wire \z80_|execute_|setM1~37_combout ; +wire \z80_|execute_|ctl_mRead~14_combout ; +wire \z80_|execute_|setM1~39_combout ; +wire \z80_|execute_|ctl_mRead~32_combout ; +wire \z80_|pla_decode_|Equal40~0_combout ; +wire \z80_|pla_decode_|Equal21~2_combout ; +wire \z80_|pla_decode_|Equal37~0_combout ; +wire \z80_|execute_|ctl_mRead~26_combout ; +wire \z80_|pla_decode_|Equal12~0_combout ; +wire \z80_|execute_|ctl_mRead~16_combout ; +wire \z80_|execute_|ctl_reg_in_hi~5_combout ; +wire \z80_|execute_|ctl_mRead~19_combout ; +wire \z80_|pla_decode_|Equal24~1_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~0_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~1_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; +wire \z80_|execute_|ctl_mRead~18_combout ; +wire \z80_|execute_|ctl_mRead~20_combout ; +wire \z80_|execute_|ctl_mRead~22_combout ; +wire \z80_|pla_decode_|Equal52~1_combout ; +wire \z80_|execute_|ctl_mRead~23_combout ; +wire \z80_|execute_|ctl_mRead~27_combout ; +wire \z80_|execute_|ctl_mRead~28_combout ; +wire \z80_|execute_|nextM~3_combout ; +wire \z80_|execute_|ctl_mRead~29_combout ; +wire \z80_|execute_|ctl_mRead~33_combout ; +wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; +wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; +wire \z80_|memory_ifc_|wait_mrd~q ; +wire \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ; +wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; +wire \z80_|memory_ifc_|nRD_out~1_combout ; +wire \z80_|memory_ifc_|nRD_out~2_combout ; +wire \Equal2~1_combout ; +wire \PS2_DAT~input_o ; +wire \reset~clkctrl_outclk ; +wire \ula_|ps2_keyboard_|bit_count~2_combout ; +wire \PS2_CLK~input_o ; +wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~0_combout ; +wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~1_combout ; +wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~q ; +wire \ula_|ps2_keyboard_|clk_edge~0_combout ; +wire \ula_|ps2_keyboard_|clk_edge~q ; +wire \ula_|ps2_keyboard_|bit_count~3_combout ; +wire \ula_|ps2_keyboard_|bit_count~1_combout ; +wire \ula_|ps2_keyboard_|bit_count~0_combout ; +wire \ula_|ps2_keyboard_|LessThan0~0_combout ; +wire \ula_|ps2_keyboard_|always1~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; +wire \ula_|zx_keyboard_|Equal0~0_combout ; +wire \ula_|zx_keyboard_|Equal0~1_combout ; +wire \ula_|ps2_keyboard_|WideXor0~1_combout ; +wire \ula_|ps2_keyboard_|WideXor0~0_combout ; +wire \ula_|ps2_keyboard_|WideXor0~2_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~q ; +wire \ula_|zx_keyboard_|released~0_combout ; +wire \ula_|zx_keyboard_|released~q ; +wire \ula_|zx_keyboard_|Equal0~2_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~50_combout ; +wire \ula_|zx_keyboard_|extended~0_combout ; +wire \ula_|zx_keyboard_|extended~q ; +wire \ula_|zx_keyboard_|keys[7][4]~15_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~52_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~53_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~q ; +wire \z80_|resets_|clrpc_int~0_combout ; +wire \z80_|resets_|clrpc_int~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; +wire \z80_|resets_|DFFE_intr_ff3~q ; +wire \z80_|resets_|clrpc~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; +wire \z80_|pla_decode_|Equal21~1_combout ; +wire \z80_|pla_decode_|Equal40~1_combout ; +wire \z80_|pla_decode_|Equal39~0_combout ; +wire \z80_|execute_|ctl_bus_db_oe~1_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; +wire \z80_|execute_|ctl_inc_dec~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; +wire \z80_|execute_|ctl_al_we~5_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; +wire \z80_|execute_|ctl_al_we~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; +wire \z80_|pla_decode_|Equal10~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~6_combout ; +wire \z80_|execute_|ctl_bus_db_oe~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ; +wire \z80_|reg_control_|reg_sel_pc~1_combout ; +wire \z80_|reg_control_|reg_sel_pc~0_combout ; +wire \z80_|reg_control_|reg_sel_pc~2_combout ; +wire \z80_|pla_decode_|Equal56~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~18_combout ; +wire \z80_|execute_|ctl_alu_op_low~17_combout ; +wire \z80_|execute_|ctl_alu_oe~4_combout ; +wire \z80_|execute_|ctl_reg_in_hi~4_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; +wire \z80_|execute_|ctl_inc_dec~3_combout ; +wire \z80_|execute_|fMRead~6_combout ; +wire \z80_|nM1_int~2_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_inc_cy~94_combout ; +wire \z80_|execute_|ctl_inc_cy~50_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; +wire \z80_|execute_|ctl_inc_cy~99_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; +wire \z80_|execute_|ctl_reg_out_hi~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_in_lo~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; +wire \z80_|pla_decode_|Equal1~5_combout ; +wire \z80_|execute_|ctl_alu_op_low~20_combout ; +wire \z80_|pla_decode_|Equal48~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; +wire \z80_|execute_|ctl_flags_bus~4_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; +wire \z80_|execute_|fMRead~7_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; +wire \z80_|execute_|ctl_reg_sys_we~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we~1_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; +wire \z80_|execute_|ctl_reg_sys_we~2_combout ; +wire \z80_|pla_decode_|Equal8~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~1_combout ; +wire \z80_|alu_control_|sel[1]~0_combout ; +wire \z80_|execute_|ctl_state_alu~7_combout ; +wire \z80_|execute_|ctl_state_alu~11_combout ; +wire \z80_|execute_|ctl_state_alu~9_combout ; +wire \z80_|execute_|ctl_state_alu~5_combout ; +wire \z80_|execute_|ctl_state_alu~10_combout ; +wire \z80_|execute_|ctl_state_alu~8_combout ; +wire \z80_|pla_decode_|Equal62~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~5_combout ; +wire \z80_|execute_|ctl_ir_we~11_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~7_combout ; +wire \z80_|execute_|ctl_bus_db_oe~3_combout ; +wire \z80_|execute_|ctl_flags_xy_we~19_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; +wire \z80_|execute_|ctl_alu_op_low~19_combout ; +wire \z80_|execute_|ctl_flags_bus~15_combout ; +wire \z80_|execute_|ctl_flags_bus~9_combout ; +wire \z80_|pla_decode_|Equal20~0_combout ; +wire \z80_|pla_decode_|Equal68~2_combout ; +wire \z80_|execute_|ctl_flags_bus~14_combout ; +wire \z80_|pla_decode_|Equal63~0_combout ; +wire \z80_|pla_decode_|Equal76~2_combout ; +wire \z80_|execute_|ctl_flags_bus~8_combout ; +wire \z80_|execute_|ctl_flags_bus~6_combout ; +wire \z80_|execute_|ctl_flags_bus~7_combout ; +wire \z80_|execute_|ctl_flags_bus~10_combout ; +wire \z80_|execute_|ctl_flags_xy_we~11_combout ; +wire \z80_|execute_|ctl_flags_hf2_we~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; +wire \z80_|execute_|ctl_reg_gp_sel~7_combout ; +wire \z80_|execute_|ctl_state_alu~12_combout ; +wire \z80_|pla_decode_|Equal62~3_combout ; +wire \z80_|execute_|ctl_flags_pf_we~6_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; +wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; +wire \z80_|execute_|ctl_flags_cf_we~7_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~10_combout ; +wire \z80_|execute_|ctl_flags_hf_we~5_combout ; +wire \z80_|execute_|ctl_flags_pf_we~11_combout ; +wire \z80_|execute_|ctl_flags_pf_we~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~3_combout ; +wire \z80_|pla_decode_|Equal10~1_combout ; +wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; +wire \z80_|pla_decode_|Equal69~0_combout ; +wire \z80_|execute_|ctl_flags_pf_we~7_combout ; +wire \z80_|execute_|ctl_flags_pf_we~8_combout ; +wire \z80_|execute_|ctl_flags_pf_we~9_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~13_combout ; +wire \z80_|execute_|ctl_flags_pf_we~10_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; +wire \z80_|execute_|ctl_flags_xy_we~18_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~21_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~20_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ; +wire \z80_|execute_|ctl_reg_out_lo~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; +wire \z80_|execute_|ctl_al_we~14_combout ; +wire \z80_|execute_|ctl_sw_4d~1_combout ; +wire \z80_|execute_|ctl_alu_oe~5_combout ; +wire \z80_|execute_|setM1~47_combout ; +wire \z80_|execute_|ctl_sw_4d~0_combout ; +wire \z80_|execute_|ctl_sw_4d~4_combout ; +wire \z80_|execute_|fMRead~8_combout ; +wire \z80_|execute_|fMRead~9_combout ; +wire \z80_|execute_|fMRead~10_combout ; +wire \z80_|execute_|ctl_sw_4d~2_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; +wire \z80_|pla_decode_|Equal4~0_combout ; +wire \z80_|execute_|setM1~41_combout ; +wire \z80_|pla_decode_|Equal2~1_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_sw_1d~4_combout ; +wire \z80_|execute_|ctl_sw_4d~3_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; +wire \z80_|execute_|ctl_sw_4d~5_combout ; +wire \z80_|execute_|ctl_sw_4d~6_combout ; +wire \z80_|reg_control_|reg_sel_pc~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; +wire \z80_|execute_|ctl_sw_4u~1_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; +wire \z80_|reg_control_|reg_sel_pc~3_combout ; +wire \z80_|reg_control_|reg_sel_pc~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; +wire \z80_|pla_decode_|Equal1~6_combout ; +wire \z80_|reg_control_|bank_exx~2_combout ; +wire \z80_|reg_control_|bank_exx~q ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_sw_2u~1_combout ; +wire \z80_|execute_|ctl_alu_oe~3_combout ; +wire \z80_|execute_|ctl_sw_2u~4_combout ; +wire \z80_|execute_|setM1~56_combout ; +wire \z80_|execute_|ctl_sw_2u~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; +wire \z80_|execute_|ctl_state_alu~13_combout ; +wire \z80_|execute_|ctl_flags_xy_we~12_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; wire \z80_|execute_|ctl_inc_cy~61_combout ; -wire \z80_|execute_|ctl_inc_cy~62_combout ; -wire \z80_|execute_|ctl_inc_cy~70_combout ; -wire \z80_|execute_|ctl_inc_cy~85_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[0]~3_combout ; -wire \z80_|address_latch_|Q[0]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; -wire \z80_|reg_file_|db_lo_as[1]~4_combout ; -wire \z80_|reg_file_|db_lo_as[1]~5_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; -wire \z80_|reg_file_|db_lo_as[1]~6_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[2]~9_combout ; -wire \z80_|address_latch_|Q[2]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; wire \z80_|execute_|ctl_inc_cy~86_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|execute_|ctl_inc_dec~11_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; -wire \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; -wire \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ; +wire \z80_|execute_|ctl_inc_cy~87_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~52_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~49_combout ; +wire \z80_|execute_|ctl_reg_gp_we~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; +wire \z80_|execute_|ctl_alu_oe~7_combout ; +wire \z80_|execute_|ctl_alu_oe~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_flags_oe~0_combout ; +wire \z80_|execute_|ctl_flags_oe~1_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~8_combout ; +wire \z80_|execute_|setM1~48_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; +wire \z80_|execute_|nextM~2_combout ; +wire \z80_|execute_|setM1~49_combout ; +wire \z80_|execute_|ctl_reg_in_hi~12_combout ; +wire \z80_|execute_|ctl_sw_1d~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; +wire \z80_|execute_|ctl_sw_2u~2_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; +wire \z80_|execute_|nextM~11_combout ; +wire \z80_|execute_|ctl_reg_use_sp~0_combout ; +wire \z80_|execute_|ctl_reg_use_sp~2_combout ; +wire \z80_|execute_|ctl_reg_use_sp~3_combout ; +wire \z80_|execute_|ctl_sw_1d~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~13_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; +wire \z80_|execute_|setM1~30_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~14_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~22_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; +wire \z80_|reg_control_|reg_sel_de2~2_combout ; +wire \z80_|reg_control_|reg_sel_de2~4_combout ; +wire \z80_|pla_decode_|Equal2~2_combout ; +wire \z80_|reg_control_|bank_hl_de1~0_combout ; +wire \z80_|reg_control_|bank_hl_de1~q ; +wire \z80_|reg_control_|reg_sel_hl~0_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~50_combout ; +wire \z80_|execute_|ctl_reg_gp_we~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ; +wire \z80_|execute_|rsel3~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; +wire \z80_|execute_|rsel0~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; +wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; +wire \z80_|execute_|ctl_reg_in_hi~7_combout ; +wire \z80_|execute_|ctl_reg_gp_we~6_combout ; +wire \z80_|execute_|ctl_reg_gp_we~9_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; +wire \z80_|execute_|ctl_reg_gp_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; +wire \z80_|execute_|ctl_reg_gp_we~5_combout ; +wire \z80_|execute_|ctl_reg_gp_we~7_combout ; +wire \z80_|execute_|ctl_sw_4u~2_combout ; +wire \z80_|execute_|ctl_sw_4u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_we~8_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; +wire \z80_|reg_control_|bank_hl_de2~0_combout ; +wire \z80_|reg_control_|bank_hl_de2~q ; +wire \z80_|reg_control_|reg_sel_hl2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; +wire \z80_|execute_|ctl_flags_sz_we~1_combout ; +wire \z80_|execute_|ctl_reg_in_hi~8_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ; +wire \z80_|execute_|ctl_reg_in_hi~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; +wire \z80_|execute_|ctl_reg_in_lo~8_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; +wire \z80_|execute_|ctl_sw_2d~6_combout ; +wire \z80_|execute_|ctl_sw_2d~7_combout ; +wire \z80_|execute_|ctl_sw_2d~8_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; +wire \z80_|execute_|ctl_sw_2d~4_combout ; +wire \z80_|execute_|fMRead~18_combout ; +wire \z80_|execute_|fMRead~19_combout ; +wire \z80_|execute_|fMRead~20_combout ; +wire \z80_|execute_|ctl_reg_in_hi~6_combout ; +wire \z80_|execute_|fMRead~21_combout ; +wire \z80_|execute_|ctl_sw_2d~5_combout ; +wire \z80_|execute_|ctl_sw_2d~9_combout ; +wire \z80_|execute_|ctl_sw_1d~5_combout ; +wire \z80_|execute_|ctl_sw_1d~6_combout ; +wire \z80_|execute_|ctl_sw_1d~7_combout ; +wire \z80_|execute_|ctl_alu_op_low~41_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op_low~26_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; +wire \z80_|execute_|ctl_alu_op_low~27_combout ; +wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; +wire \z80_|pla_decode_|Equal61~2_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; +wire \z80_|execute_|ctl_alu_core_hf~12_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; +wire \z80_|execute_|ctl_flags_sz_we~3_combout ; +wire \z80_|execute_|ctl_flags_alu~13_combout ; +wire \z80_|execute_|ctl_flags_alu~14_combout ; +wire \z80_|execute_|ctl_flags_alu~15_combout ; +wire \z80_|execute_|ctl_reg_use_sp~1_combout ; +wire \z80_|execute_|ctl_alu_op_low~16_combout ; +wire \z80_|execute_|ctl_flags_xy_we~17_combout ; +wire \z80_|execute_|ctl_flags_sz_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ; +wire \z80_|execute_|ctl_alu_op_low~39_combout ; +wire \z80_|execute_|ctl_flags_alu~16_combout ; +wire \z80_|execute_|ctl_flags_alu~17_combout ; +wire \z80_|execute_|ctl_alu_op_low~23_combout ; +wire \z80_|execute_|ctl_flags_alu~18_combout ; +wire \z80_|execute_|ctl_flags_alu~11_combout ; +wire \z80_|execute_|ctl_alu_core_R~0_combout ; +wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~1_combout ; +wire \z80_|execute_|ctl_flags_alu~23_combout ; +wire \z80_|execute_|ctl_flags_alu~12_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~11_combout ; +wire \z80_|execute_|ctl_alu_oe~6_combout ; +wire \z80_|execute_|setM1~17_combout ; +wire \z80_|execute_|ctl_alu_op_low~22_combout ; +wire \z80_|execute_|ctl_flags_xy_we~6_combout ; +wire \z80_|execute_|ctl_flags_xy_we~7_combout ; +wire \z80_|execute_|ctl_flags_sz_we~2_combout ; +wire \z80_|execute_|ctl_flags_alu~19_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; +wire \z80_|execute_|fMRead~26_combout ; +wire \z80_|execute_|ctl_flags_bus~11_combout ; +wire \z80_|execute_|ctl_flags_bus~12_combout ; +wire \z80_|execute_|ctl_flags_bus~13_combout ; +wire \z80_|execute_|ctl_flags_bus~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~12_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~18_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; +wire \z80_|execute_|ctl_alu_op_low~24_combout ; +wire \z80_|execute_|ctl_alu_op_low~25_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~17_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; +wire \z80_|execute_|ctl_flags_xy_we~10_combout ; +wire \z80_|execute_|ctl_flags_cf_we~2_combout ; +wire \z80_|execute_|ctl_alu_core_S~6_combout ; +wire \z80_|execute_|ctl_alu_core_S~7_combout ; +wire \z80_|execute_|ctl_alu_core_S~4_combout ; +wire \z80_|execute_|ctl_alu_core_S~5_combout ; +wire \z80_|execute_|ctl_alu_oe~15_combout ; +wire \z80_|execute_|ctl_alu_res_oe~0_combout ; +wire \z80_|execute_|ctl_alu_res_oe~1_combout ; +wire \z80_|execute_|ctl_alu_res_oe~2_combout ; +wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; +wire \z80_|alu_|db_high[3]~0_combout ; +wire \z80_|execute_|ctl_reg_out_hi~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ; +wire \z80_|execute_|ctl_sw_2u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; +wire \z80_|execute_|ctl_sw_2u~6_combout ; +wire \z80_|execute_|ctl_reg_out_lo~2_combout ; +wire \z80_|execute_|ctl_reg_out_hi~5_combout ; +wire \z80_|execute_|ctl_reg_out_hi~6_combout ; +wire \z80_|execute_|ctl_reg_out_hi~7_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~40_combout ; +wire \z80_|execute_|ctl_reg_use_sp~4_combout ; +wire \z80_|execute_|ctl_reg_use_sp~5_combout ; +wire \z80_|execute_|ctl_reg_use_sp~6_combout ; +wire \z80_|reg_control_|bank_af~0_combout ; +wire \z80_|reg_control_|bank_af~q ; +wire \z80_|reg_control_|reg_sel_af~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~41_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ; -wire \z80_|execute_|ctl_reg_in_hi~11_combout ; -wire \z80_|execute_|ctl_reg_in_hi~12_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~44_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~32_combout ; +wire \z80_|reg_control_|reg_sel_de2~3_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_control_|reg_sel_de~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~31_combout ; wire \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ; +wire \z80_|reg_control_|reg_sel_iy~2_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~43_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~34_combout ; +wire \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; +wire \z80_|execute_|ctl_sw_4u~4_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~45_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~36_combout ; wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~42_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~46_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~47_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~33_combout ; +wire \z80_|reg_control_|reg_sel_af2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; +wire \z80_|execute_|ctl_reg_in_hi~10_combout ; +wire \z80_|execute_|ctl_reg_in_hi~11_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~35_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~37_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~38_combout ; +wire \z80_|execute_|ctl_sw_4u~5_combout ; +wire \z80_|execute_|ctl_sw_4u~6_combout ; wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; -wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; -wire \z80_|reg_file_|db_hi_as[1]~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; -wire \z80_|reg_file_|db_hi_as[1]~1_combout ; -wire \z80_|reg_file_|db_hi_as[0]~2_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; -wire \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; -wire \z80_|reg_file_|db_hi_as[0]~4_combout ; -wire \z80_|reg_file_|db_hi_as[0]~5_combout ; -wire \z80_|reg_file_|db_hi_as[0]~6_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[1]~3_combout ; -wire \z80_|address_latch_|Q[9]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~32_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~35_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~34_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~33_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~36_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~37_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~31_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~38_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~39_combout ; -wire \z80_|reg_file_|db_hi_as[2]~7_combout ; -wire \z80_|reg_file_|db_hi_as[2]~8_combout ; -wire \z80_|reg_file_|db_hi_as[2]~9_combout ; -wire \z80_|address_latch_|Q[10]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; -wire \z80_|reg_file_|db_hi_as[3]~10_combout ; -wire \z80_|reg_file_|db_hi_as[3]~11_combout ; -wire \z80_|reg_file_|db_hi_as[3]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~48_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; -wire \z80_|alu_|alu_op1[3]~3_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; -wire \z80_|execute_|ctl_alu_core_R~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~5_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~20_combout ; -wire \z80_|execute_|ctl_state_alu~12_combout ; -wire \z80_|execute_|ctl_alu_core_hf~18_combout ; -wire \z80_|pla_decode_|Equal61~2_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~21_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~20_combout ; -wire \z80_|execute_|ctl_flags_sz_we~4_combout ; -wire \z80_|pla_decode_|Equal71~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; -wire \z80_|execute_|ctl_alu_op_low~31_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ; -wire \z80_|pla_decode_|Equal72~2_combout ; -wire \z80_|pla_decode_|Equal73~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~0_combout ; -wire \z80_|execute_|ctl_flags_nf_we~1_combout ; -wire \z80_|execute_|ctl_flags_nf_we~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~3_combout ; -wire \z80_|execute_|ctl_flags_sz_we~5_combout ; -wire \z80_|execute_|ctl_flags_sz_we~6_combout ; -wire \z80_|execute_|ctl_flags_nf_we~4_combout ; -wire \z80_|execute_|setM1~15_combout ; -wire \z80_|execute_|setM1~16_combout ; -wire \z80_|execute_|ctl_flags_xy_we~6_combout ; -wire \z80_|execute_|ctl_flags_xy_we~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~2_combout ; -wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~1_combout ; -wire \z80_|execute_|ctl_flags_alu~7_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~8_combout ; -wire \z80_|execute_|ctl_flags_alu~8_combout ; -wire \z80_|execute_|ctl_flags_xy_we~16_combout ; -wire \z80_|execute_|ctl_flags_alu~12_combout ; -wire \z80_|execute_|ctl_flags_alu~13_combout ; -wire \z80_|execute_|ctl_flags_alu~14_combout ; -wire \z80_|execute_|ctl_flags_alu~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~19_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; -wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~18_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; -wire \z80_|alu_|alu_op2[1]~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|execute_|ctl_alu_core_S~9_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ; -wire \z80_|alu_|alu_op2[0]~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ; -wire \z80_|execute_|ctl_alu_core_S~8_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|execute_|ctl_alu_core_hf~21_combout ; -wire \z80_|execute_|ctl_alu_core_hf~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~19_combout ; -wire \z80_|execute_|ctl_alu_op_low~27_combout ; -wire \z80_|execute_|ctl_alu_op_low~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~23_combout ; -wire \z80_|execute_|ctl_alu_core_hf~37_combout ; -wire \z80_|execute_|ctl_alu_core_hf~38_combout ; -wire \z80_|execute_|ctl_alu_core_hf~24_combout ; -wire \z80_|execute_|ctl_alu_core_hf~25_combout ; -wire \z80_|execute_|ctl_alu_core_hf~26_combout ; -wire \z80_|execute_|ctl_alu_core_hf~27_combout ; -wire \z80_|execute_|ctl_alu_core_hf~28_combout ; -wire \z80_|execute_|ctl_alu_op_low~30_combout ; -wire \z80_|execute_|ctl_alu_core_hf~34_combout ; -wire \z80_|execute_|ctl_alu_core_hf~32_combout ; -wire \z80_|execute_|ctl_alu_core_hf~43_combout ; -wire \z80_|execute_|ctl_alu_core_hf~33_combout ; -wire \z80_|execute_|ctl_alu_core_hf~42_combout ; -wire \z80_|execute_|ctl_alu_core_hf~35_combout ; -wire \z80_|execute_|ctl_alu_core_hf~41_combout ; -wire \z80_|execute_|ctl_alu_core_hf~30_combout ; -wire \z80_|execute_|ctl_mWrite~10_combout ; -wire \z80_|execute_|ctl_alu_core_hf~31_combout ; -wire \z80_|execute_|ctl_alu_core_hf~44_combout ; -wire \z80_|execute_|ctl_alu_core_hf~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~36_combout ; -wire \z80_|execute_|ctl_alu_core_hf~39_combout ; -wire \z80_|execute_|ctl_alu_core_hf~40_combout ; -wire \z80_|execute_|ctl_flags_hf_we~2_combout ; -wire \z80_|execute_|ctl_alu_core_R~2_combout ; -wire \z80_|execute_|ctl_alu_core_R~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ; -wire \z80_|alu_|alu_op2[3]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; -wire \z80_|execute_|ctl_flags_hf_we~3_combout ; -wire \z80_|execute_|ctl_flags_hf_we~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; -wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~13_combout ; -wire \z80_|alu_flags_|flags_hf~combout ; -wire \z80_|alu_control_|alu_core_cf_in~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; -wire \z80_|alu_|db_high[0]~23_combout ; -wire \z80_|address_latch_|Q[12]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[4]~16_combout ; -wire \z80_|reg_file_|db_hi_as[4]~17_combout ; -wire \z80_|reg_file_|db_hi_as[4]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~62_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~63_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~61_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~64_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~58_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~65_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~66_combout ; -wire \z80_|alu_|db[4]~16_combout ; -wire \z80_|alu_|db[7]~26_combout ; -wire \z80_|alu_|db[4]~17_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; -wire \z80_|alu_|db_high[0]~24_combout ; -wire \z80_|alu_|db_high[0]~21_combout ; -wire \z80_|alu_|db_high[0]~22_combout ; -wire \z80_|alu_|db_high[0]~25_combout ; -wire \z80_|alu_|db_high[0]~26_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; -wire \z80_|alu_|alu_op1[0]~1_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; -wire \z80_|alu_|alu_op1[1]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; -wire \z80_|alu_|alu_op1[2]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~5_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~69_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~70_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~72_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~71_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~73_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~67_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~68_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~74_combout ; -wire \z80_|reg_file_|db_hi_as[7]~19_combout ; -wire \z80_|reg_file_|db_hi_as[7]~20_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~54_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~53_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~51_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~52_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~55_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~49_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~50_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~56_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~57_combout ; -wire \z80_|reg_file_|db_hi_as[5]~13_combout ; -wire \z80_|reg_file_|db_hi_as[5]~14_combout ; -wire \z80_|reg_file_|db_hi_as[5]~15_combout ; -wire \z80_|address_latch_|Q[13]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~76_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~80_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~79_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~78_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~81_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~82_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~77_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~83_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~84_combout ; -wire \z80_|reg_file_|db_hi_as[6]~22_combout ; -wire \z80_|reg_file_|db_hi_as[6]~23_combout ; -wire \z80_|reg_file_|db_hi_as[6]~24_combout ; -wire \z80_|address_latch_|Q[14]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|reg_file_|db_hi_as[7]~21_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~75_combout ; -wire \z80_|alu_|db[7]~20_combout ; -wire \z80_|alu_|db[7]~21_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; -wire \z80_|execute_|ctl_flags_cf_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf_we~5_combout ; -wire \z80_|execute_|ctl_flags_cf_we~3_combout ; -wire \z80_|execute_|ctl_flags_cf_we~6_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~2_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; -wire \z80_|alu_|db_high[3]~5_combout ; -wire \z80_|alu_|db_high[3]~6_combout ; -wire \z80_|alu_|db_high[3]~4_combout ; -wire \z80_|alu_|db_high[3]~27_combout ; -wire \z80_|alu_|db_high[3]~7_combout ; -wire \z80_|alu_|db_high[3]~8_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ; -wire \z80_|alu_|db_low[3]~9_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; -wire \z80_|alu_|db_low[3]~10_combout ; -wire \z80_|alu_|db_low[3]~7_combout ; -wire \z80_|alu_|db_low[3]~8_combout ; -wire \z80_|alu_|db_low[3]~11_combout ; -wire \z80_|alu_|db_low[3]~25_combout ; -wire \z80_|alu_|db[3]~10_combout ; -wire \z80_|alu_|db[3]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~39_combout ; +wire \z80_|alu_|db[3]~13_combout ; +wire \z80_|execute_|ctl_sw_2d~12_combout ; +wire \z80_|execute_|ctl_sw_2d~10_combout ; +wire \z80_|execute_|ctl_sw_2d~14_combout ; +wire \z80_|execute_|ctl_sw_2d~11_combout ; +wire \z80_|execute_|ctl_sw_2d~13_combout ; +wire \z80_|execute_|ctl_bus_db_we~5_combout ; +wire \z80_|execute_|ctl_alu_oe~9_combout ; +wire \z80_|execute_|ctl_alu_oe~10_combout ; wire \z80_|execute_|ctl_sw_2u~7_combout ; -wire \z80_|execute_|setM1~49_combout ; -wire \z80_|execute_|ctl_flags_oe~2_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|execute_|ctl_flags_sz_we~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ; wire \z80_|execute_|ctl_flags_xy_we~13_combout ; wire \z80_|execute_|ctl_flags_xy_we~14_combout ; wire \z80_|execute_|ctl_flags_xy_we~15_combout ; +wire \z80_|execute_|ctl_flags_sz_we~5_combout ; +wire \z80_|execute_|ctl_flags_sz_we~6_combout ; +wire \z80_|execute_|ctl_flags_sz_we~7_combout ; +wire \z80_|execute_|ctl_flags_xy_we~16_combout ; wire \z80_|alu_flags_|flags_xf~q ; -wire \z80_|alu_control_|db[3]~33_combout ; +wire \z80_|execute_|setM1~50_combout ; +wire \z80_|execute_|ctl_flags_oe~2_combout ; +wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; +wire \z80_|alu_control_|db[3]~34_combout ; +wire \z80_|sw1_|db_down[3]~3_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~42_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~91_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; +wire \z80_|reg_file_|db_lo_as[3]~10_combout ; +wire \z80_|reg_file_|db_lo_as[3]~11_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; +wire \z80_|execute_|ctl_inc_cy~88_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; +wire \z80_|execute_|ctl_inc_dec~6_combout ; +wire \z80_|reg_file_|db_lo_as[0]~2_combout ; +wire \z80_|execute_|pc_inc_hold~25_combout ; +wire \z80_|execute_|ctl_inc_cy~67_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~64_combout ; +wire \z80_|execute_|ctl_inc_cy~65_combout ; +wire \z80_|execute_|ctl_inc_cy~63_combout ; +wire \z80_|execute_|ctl_inc_cy~66_combout ; +wire \z80_|execute_|ctl_inc_cy~68_combout ; +wire \z80_|execute_|ctl_inc_cy~58_combout ; +wire \z80_|execute_|ctl_inc_cy~59_combout ; +wire \z80_|execute_|ctl_inc_cy~60_combout ; +wire \z80_|execute_|ctl_inc_cy~57_combout ; +wire \z80_|execute_|ctl_inc_cy~62_combout ; +wire \z80_|execute_|pc_inc_hold~18_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; +wire \z80_|execute_|pc_inc_hold~17_combout ; +wire \z80_|execute_|pc_inc_hold~19_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; +wire \z80_|execute_|pc_inc_hold~20_combout ; +wire \z80_|execute_|pc_inc_hold~36_combout ; +wire \z80_|execute_|pc_inc_hold~15_combout ; +wire \z80_|execute_|pc_inc_hold~16_combout ; +wire \z80_|execute_|pc_inc_hold~21_combout ; +wire \z80_|execute_|ctl_inc_cy~69_combout ; +wire \z80_|execute_|ctl_inc_cy~52_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; +wire \z80_|execute_|pc_inc_hold~34_combout ; +wire \z80_|execute_|pc_inc_hold~22_combout ; +wire \z80_|execute_|pc_inc_hold~23_combout ; +wire \z80_|execute_|pc_inc_hold~35_combout ; +wire \z80_|execute_|pc_inc_hold~24_combout ; +wire \z80_|execute_|ctl_inc_cy~53_combout ; +wire \z80_|execute_|ctl_inc_cy~54_combout ; +wire \z80_|execute_|ctl_inc_cy~74_combout ; +wire \z80_|execute_|ctl_inc_cy~75_combout ; +wire \z80_|execute_|ctl_inc_cy~73_combout ; +wire \z80_|execute_|ctl_inc_cy~76_combout ; +wire \z80_|execute_|ctl_inc_cy~95_combout ; +wire \z80_|execute_|ctl_inc_cy~72_combout ; +wire \z80_|execute_|pc_inc_hold~27_combout ; +wire \z80_|execute_|ctl_inc_cy~77_combout ; +wire \z80_|execute_|ctl_inc_cy~78_combout ; +wire \z80_|execute_|ctl_inc_cy~79_combout ; +wire \z80_|execute_|ctl_inc_cy~70_combout ; +wire \z80_|execute_|ctl_inc_cy~71_combout ; +wire \z80_|execute_|ctl_inc_cy~80_combout ; +wire \z80_|execute_|ctl_inc_cy~55_combout ; +wire \z80_|execute_|pc_inc_hold~26_combout ; +wire \z80_|execute_|ctl_inc_cy~56_combout ; +wire \z80_|execute_|ctl_inc_cy~81_combout ; +wire \z80_|execute_|ctl_inc_cy~85_combout ; +wire \z80_|execute_|ctl_inc_cy~89_combout ; +wire \z80_|execute_|ctl_inc_cy~90_combout ; +wire \z80_|execute_|ctl_inc_cy~91_combout ; +wire \z80_|execute_|ctl_inc_cy~83_combout ; +wire \z80_|execute_|ctl_inc_cy~84_combout ; +wire \z80_|execute_|ctl_inc_cy~100_combout ; +wire \z80_|execute_|ctl_inc_cy~92_combout ; +wire \z80_|execute_|pc_inc_hold~28_combout ; +wire \z80_|execute_|ctl_inc_cy~82_combout ; +wire \z80_|execute_|pc_inc_hold~29_combout ; +wire \z80_|execute_|pc_inc_hold~30_combout ; +wire \z80_|execute_|pc_inc_hold~31_combout ; +wire \z80_|execute_|pc_inc_hold~32_combout ; +wire \z80_|execute_|ctl_inc_cy~93_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; +wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; +wire \z80_|alu_control_|db[0]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; +wire \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ; +wire \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; +wire \z80_|execute_|ctl_inc_dec~8_combout ; +wire \z80_|execute_|ctl_inc_dec~9_combout ; +wire \z80_|execute_|ctl_inc_dec~10_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|execute_|ctl_inc_dec~7_combout ; +wire \z80_|execute_|ctl_inc_dec~11_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; +wire \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; +wire \z80_|alu_|db_low[2]~9_combout ; +wire \z80_|alu_|db_low[2]~10_combout ; +wire \z80_|alu_|db_high[3]~1_combout ; +wire \z80_|execute_|ctl_flags_pf_we~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ; +wire \z80_|execute_|ctl_alu_op_low~38_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ; +wire \z80_|execute_|ctl_alu_core_S~8_combout ; +wire \z80_|execute_|ctl_alu_core_R~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~3_combout ; +wire \z80_|execute_|ctl_alu_core_R~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; +wire \z80_|execute_|ctl_alu_core_S~11_combout ; +wire \z80_|execute_|ctl_alu_core_S~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~combout ; +wire \z80_|pla_decode_|Equal73~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~5_combout ; +wire \z80_|execute_|ctl_alu_core_R~combout ; +wire \z80_|execute_|ctl_alu_op_low~28_combout ; +wire \z80_|execute_|ctl_alu_op_low~29_combout ; +wire \z80_|execute_|ctl_alu_op_low~30_combout ; +wire \z80_|execute_|ctl_alu_op_low~31_combout ; +wire \z80_|execute_|ctl_alu_op_low~32_combout ; +wire \z80_|execute_|ctl_alu_op_low~40_combout ; +wire \z80_|execute_|ctl_alu_op_low~33_combout ; +wire \z80_|execute_|ctl_alu_op_low~combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~59_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~58_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~61_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~62_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~63_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~60_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~64_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~65_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; +wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; +wire \z80_|reg_file_|db_hi_as[7]~16_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; +wire \z80_|reg_file_|db_hi_as[7]~17_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; +wire \z80_|reg_file_|db_hi_as[1]~0_combout ; +wire \z80_|reg_file_|db_hi_as[1]~1_combout ; +wire \z80_|execute_|ctl_al_we~6_combout ; +wire \z80_|execute_|ctl_al_we~9_combout ; +wire \z80_|execute_|ctl_al_we~10_combout ; +wire \z80_|execute_|ctl_al_we~7_combout ; +wire \z80_|execute_|ctl_al_we~8_combout ; +wire \z80_|execute_|ctl_al_we~11_combout ; +wire \z80_|execute_|ctl_al_we~12_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~82_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~81_combout ; +wire \z80_|alu_control_|db[6]~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|execute_|ctl_flags_sz_we~8_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; +wire \z80_|alu_control_|db[7]~18_combout ; +wire \z80_|alu_control_|db[7]~19_combout ; +wire \z80_|alu_control_|db[7]~20_combout ; +wire \z80_|alu_control_|db[7]~37_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; +wire \z80_|reg_file_|db_lo_as[7]~22_combout ; +wire \z80_|reg_file_|db_lo_as[7]~23_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[7]~24_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[1]~3_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~44_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~45_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~42_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~43_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~46_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~40_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~41_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~47_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~48_combout ; +wire \z80_|reg_file_|db_hi_as[2]~10_combout ; +wire \z80_|reg_file_|db_hi_as[2]~11_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[2]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~50_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~49_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~51_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~52_combout ; +wire \z80_|alu_|db[4]~8_combout ; +wire \z80_|alu_|db[4]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~53_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~54_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~55_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~56_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~57_combout ; +wire \z80_|reg_file_|db_hi_as[4]~13_combout ; +wire \z80_|reg_file_|db_hi_as[4]~14_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; +wire \z80_|reg_file_|db_hi_as[4]~15_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~76_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~77_combout ; +wire \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~79_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; +wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; +wire \z80_|alu_|db_low[1]~18_combout ; +wire \z80_|alu_|db_low[1]~19_combout ; +wire \z80_|alu_|db_low[1]~16_combout ; +wire \z80_|alu_|db_low[1]~15_combout ; +wire \z80_|alu_|db_low[1]~17_combout ; +wire \z80_|alu_|db_low[1]~20_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; +wire \z80_|alu_|alu_op2[1]~2_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; +wire \z80_|alu_|db_high[2]~10_combout ; +wire \z80_|alu_|db_high[2]~8_combout ; +wire \z80_|alu_|db_high[2]~9_combout ; +wire \z80_|alu_|db_high[2]~11_combout ; +wire \z80_|alu_|db_high[2]~12_combout ; +wire \z80_|alu_|db_high[2]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~68_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~67_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~72_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~70_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~69_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~71_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~73_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~74_combout ; +wire \z80_|reg_file_|db_hi_as[6]~19_combout ; +wire \z80_|reg_file_|db_hi_as[6]~20_combout ; +wire \z80_|reg_file_|db_hi_as[6]~21_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~75_combout ; +wire \z80_|alu_|db[6]~21_combout ; +wire \z80_|alu_|db[6]~22_combout ; +wire \z80_|alu_|db_high[1]~16_combout ; +wire \z80_|alu_|db_high[1]~17_combout ; +wire \z80_|alu_|db_high[1]~14_combout ; +wire \z80_|alu_|db_high[1]~15_combout ; +wire \z80_|alu_|db_high[1]~18_combout ; +wire \z80_|alu_|db_high[1]~19_combout ; +wire \z80_|alu_|db[5]~23_combout ; +wire \z80_|alu_|db[5]~24_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~80_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~81_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~78_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~82_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~83_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~84_combout ; +wire \z80_|reg_file_|db_hi_as[5]~22_combout ; +wire \z80_|reg_file_|db_hi_as[5]~23_combout ; +wire \z80_|reg_file_|db_hi_as[5]~24_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|reg_file_|db_hi_as[7]~18_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~66_combout ; +wire \z80_|alu_|db[7]~19_combout ; +wire \z80_|alu_|db[7]~20_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ; +wire \z80_|alu_|alu_op1[3]~0_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ; +wire \z80_|alu_|alu_op2[2]~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; +wire \z80_|execute_|ctl_flags_cf_we~3_combout ; +wire \z80_|execute_|ctl_flags_hf_we~2_combout ; +wire \z80_|execute_|ctl_flags_cf_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf_we~5_combout ; +wire \z80_|execute_|ctl_flags_cf_we~6_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~6_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~5_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; +wire \z80_|alu_|db_low[0]~21_combout ; +wire \z80_|alu_|db_low[0]~22_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ; +wire \z80_|alu_|db_low[0]~24_combout ; +wire \z80_|alu_|db_low[0]~23_combout ; +wire \z80_|alu_|db_low[0]~25_combout ; +wire \z80_|alu_|db_low[0]~27_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ; +wire \z80_|alu_|alu_op2[0]~3_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|execute_|ctl_alu_op_low~34_combout ; +wire \z80_|execute_|ctl_alu_op_low~36_combout ; +wire \z80_|execute_|ctl_alu_op_low~35_combout ; +wire \z80_|execute_|ctl_alu_core_hf~13_combout ; +wire \z80_|execute_|ctl_alu_core_hf~14_combout ; +wire \z80_|execute_|ctl_alu_core_hf~15_combout ; +wire \z80_|execute_|ctl_alu_core_hf~16_combout ; +wire \z80_|execute_|ctl_alu_core_hf~17_combout ; +wire \z80_|execute_|ctl_alu_core_hf~37_combout ; +wire \z80_|execute_|ctl_alu_core_hf~38_combout ; +wire \z80_|execute_|ctl_alu_core_hf~36_combout ; +wire \z80_|execute_|ctl_alu_core_hf~23_combout ; +wire \z80_|execute_|ctl_alu_core_hf~34_combout ; +wire \z80_|execute_|ctl_alu_core_hf~29_combout ; +wire \z80_|execute_|ctl_alu_core_hf~26_combout ; +wire \z80_|execute_|ctl_alu_core_hf~35_combout ; +wire \z80_|execute_|ctl_alu_core_hf~27_combout ; +wire \z80_|execute_|ctl_alu_core_hf~28_combout ; +wire \z80_|execute_|ctl_alu_core_hf~30_combout ; +wire \z80_|execute_|ctl_alu_op_low~37_combout ; +wire \z80_|execute_|ctl_alu_core_hf~24_combout ; +wire \z80_|execute_|ctl_alu_core_hf~25_combout ; +wire \z80_|execute_|ctl_alu_core_hf~31_combout ; +wire \z80_|execute_|ctl_alu_core_hf~20_combout ; +wire \z80_|execute_|ctl_alu_core_hf~21_combout ; +wire \z80_|execute_|ctl_alu_core_hf~18_combout ; +wire \z80_|execute_|ctl_alu_core_hf~19_combout ; +wire \z80_|execute_|ctl_alu_core_hf~22_combout ; +wire \z80_|execute_|ctl_alu_core_hf~32_combout ; +wire \z80_|execute_|ctl_alu_core_hf~33_combout ; +wire \z80_|alu_control_|alu_core_cf_in~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; +wire \z80_|alu_|db_high[0]~21_combout ; +wire \z80_|alu_|db_high[0]~22_combout ; +wire \z80_|alu_|db_high[0]~23_combout ; +wire \z80_|alu_|db_high[0]~20_combout ; +wire \z80_|alu_|db_high[0]~24_combout ; +wire \z80_|alu_|db_high[0]~25_combout ; +wire \z80_|alu_|alu_op1[0]~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; +wire \z80_|alu_|db_low[2]~11_combout ; +wire \z80_|alu_|db_low[2]~12_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; +wire \z80_|alu_|db_low[2]~13_combout ; +wire \z80_|alu_|db_low[2]~14_combout ; +wire \z80_|alu_|db[2]~11_combout ; +wire \z80_|alu_|db[2]~12_combout ; +wire \z80_|alu_control_|db[2]~28_combout ; +wire \z80_|alu_flags_|flags_hf2~0_combout ; +wire \z80_|alu_flags_|flags_hf2~q ; +wire \z80_|alu_control_|out[6]~0_combout ; +wire \z80_|execute_|ctl_66_oe~combout ; +wire \z80_|alu_control_|db[2]~24_combout ; wire \z80_|execute_|ctl_reg_out_lo~3_combout ; wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; wire \z80_|execute_|ctl_reg_out_lo~4_combout ; wire \z80_|execute_|ctl_reg_out_lo~5_combout ; -wire \z80_|execute_|ctl_reg_out_lo~8_combout ; -wire \z80_|sw1_|db_down[3]~1_combout ; -wire \z80_|alu_control_|db[3]~34_combout ; -wire \z80_|alu_control_|db[3]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~52_combout ; -wire \z80_|reg_file_|db_lo_as[3]~10_combout ; -wire \z80_|reg_file_|db_lo_as[3]~11_combout ; -wire \z80_|reg_file_|db_lo_as[3]~12_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ; +wire \z80_|reg_file_|db_lo_ds[2]~1_combout ; +wire \z80_|alu_control_|db[2]~29_combout ; +wire \z80_|alu_control_|db[2]~30_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; +wire \z80_|reg_file_|db_lo_as[2]~7_combout ; +wire \z80_|reg_file_|db_lo_as[2]~8_combout ; +wire \z80_|reg_file_|db_lo_as[2]~9_combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~62_combout ; -wire \z80_|reg_file_|db_lo_as[4]~13_combout ; -wire \z80_|reg_file_|db_lo_as[4]~14_combout ; -wire \z80_|reg_file_|db_lo_as[4]~15_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; -wire \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~62_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~72_combout ; wire \z80_|reg_file_|db_lo_as[5]~16_combout ; wire \z80_|reg_file_|db_lo_as[5]~17_combout ; wire \z80_|reg_file_|db_lo_as[5]~18_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ; wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~72_combout ; +wire \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ; wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; wire \z80_|reg_file_|db_lo_as[6]~19_combout ; wire \z80_|reg_file_|db_lo_as[6]~20_combout ; wire \z80_|reg_file_|db_lo_as[6]~21_combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[7]~24_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~92_combout ; -wire \z80_|reg_file_|db_lo_ds[7]~0_combout ; -wire \z80_|interrupts_|im2~q ; -wire \z80_|execute_|ctl_mRead~12_combout ; -wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; -wire \z80_|alu_control_|db[7]~17_combout ; -wire \z80_|alu_control_|db[7]~16_combout ; -wire \z80_|alu_control_|db[7]~18_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|execute_|ctl_flags_sz_we~8_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; -wire \z80_|pla_decode_|Equal62~3_combout ; -wire \z80_|execute_|ctl_flags_pf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~6_combout ; -wire \z80_|execute_|ctl_flags_pf_we~7_combout ; -wire \z80_|execute_|ctl_flags_pf_we~8_combout ; -wire \z80_|execute_|ctl_flags_pf_we~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[0]~4_combout ; +wire \z80_|reg_file_|db_hi_as[0]~5_combout ; +wire \z80_|reg_file_|db_hi_as[0]~6_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; +wire \z80_|alu_|db[0]~17_combout ; +wire \z80_|alu_|db[0]~18_combout ; +wire \z80_|sw2_|db_up[0]~0_combout ; +wire \z80_|alu_control_|db[0]~11_combout ; +wire \z80_|alu_control_|db[0]~14_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; +wire \z80_|reg_file_|db_lo_as[0]~0_combout ; +wire \z80_|reg_file_|db_lo_as[0]~1_combout ; +wire \z80_|reg_file_|db_lo_as[0]~3_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; +wire \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; +wire \z80_|reg_file_|db_lo_as[1]~4_combout ; +wire \z80_|reg_file_|db_lo_as[1]~5_combout ; +wire \z80_|reg_file_|db_lo_as[1]~6_combout ; +wire \z80_|address_latch_|Q[1]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; +wire \z80_|reg_file_|db_lo_as[3]~12_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; +wire \z80_|alu_control_|db[3]~35_combout ; +wire \z80_|alu_control_|db[3]~36_combout ; +wire \z80_|alu_|db[3]~14_combout ; +wire \z80_|alu_|db_low[3]~4_combout ; +wire \z80_|alu_|db_low[3]~5_combout ; +wire \z80_|alu_|db_low[3]~6_combout ; +wire \z80_|alu_|db_low[3]~7_combout ; +wire \z80_|alu_|db_low[3]~8_combout ; +wire \z80_|alu_|db_low[3]~26_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ; +wire \z80_|alu_|alu_op2[3]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ; +wire \z80_|alu_|db_high[3]~4_combout ; +wire \z80_|alu_|db_high[3]~2_combout ; +wire \z80_|alu_|db_high[3]~3_combout ; +wire \z80_|alu_|db_high[3]~5_combout ; +wire \z80_|alu_|db_high[3]~6_combout ; +wire \z80_|alu_|db_high[3]~7_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; +wire \z80_|execute_|ctl_flags_nf_we~0_combout ; +wire \z80_|execute_|ctl_flags_nf_we~1_combout ; +wire \z80_|execute_|ctl_flags_nf_we~2_combout ; +wire \z80_|execute_|ctl_flags_nf_we~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; +wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; +wire \z80_|execute_|ctl_flags_cf_set~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; +wire \z80_|alu_control_|out[6]~1_combout ; +wire \z80_|alu_control_|out[6]~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; +wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; +wire \z80_|execute_|ctl_alu_op_low~21_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; +wire \z80_|pla_decode_|Equal64~0_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; +wire \z80_|alu_flags_|flags_cf~combout ; +wire \z80_|execute_|ctl_flags_hf_we~3_combout ; +wire \z80_|execute_|ctl_flags_hf_we~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; +wire \z80_|execute_|ctl_flags_hf_cpl~9_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; +wire \z80_|alu_flags_|flags_hf~combout ; +wire \z80_|alu_control_|db[4]~31_combout ; +wire \z80_|alu_control_|db[4]~32_combout ; +wire \z80_|alu_control_|db[4]~33_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~52_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; +wire \z80_|reg_file_|db_lo_as[4]~13_combout ; +wire \z80_|reg_file_|db_lo_as[4]~14_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[4]~15_combout ; wire \z80_|decode_state_|DFFE_instNonRep~2_combout ; wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; wire \z80_|decode_state_|DFFE_instNonRep~4_combout ; wire \z80_|decode_state_|DFFE_instNonRep~5_combout ; wire \z80_|decode_state_|DFFE_instNonRep~q ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; +wire \z80_|pla_decode_|Equal79~0_combout ; +wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|interrupts_|DFFE_instIFF2~q ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; +wire \z80_|execute_|ctl_pf_sel[1]~12_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~11_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; wire \z80_|alu_|alu_parity_out~0_combout ; wire \z80_|alu_|alu_parity_out~combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~q ; -wire \z80_|alu_control_|sel[1]~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; wire \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ; wire \z80_|alu_control_|flags_cond_true~0_combout ; wire \z80_|alu_control_|flags_cond_true~q ; -wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; -wire \z80_|reg_file_|db_lo_ds[1]~1_combout ; -wire \z80_|alu_control_|db[1]~25_combout ; -wire \z80_|alu_control_|db[1]~24_combout ; -wire \z80_|alu_control_|db[1]~26_combout ; -wire \z80_|alu_|db[1]~12_combout ; -wire \z80_|alu_|db[1]~13_combout ; -wire \z80_|alu_|db_low[0]~21_combout ; -wire \z80_|alu_|db_low[0]~22_combout ; -wire \z80_|alu_|db_low[0]~18_combout ; -wire \z80_|alu_|db_low[0]~19_combout ; -wire \z80_|alu_|db_low[0]~20_combout ; -wire \z80_|alu_|db_low[0]~23_combout ; -wire \z80_|alu_|db[0]~18_combout ; -wire \z80_|alu_|db[0]~19_combout ; -wire \z80_|alu_|db_low[1]~15_combout ; -wire \z80_|alu_|db_low[1]~16_combout ; -wire \z80_|alu_|db_low[1]~12_combout ; -wire \z80_|alu_|db_low[1]~13_combout ; -wire \z80_|alu_|db_low[1]~14_combout ; -wire \z80_|alu_|db_low[1]~17_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ; -wire \z80_|alu_control_|out[6]~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; -wire \z80_|alu_flags_|flags_hf2~0_combout ; -wire \z80_|alu_flags_|flags_hf2~q ; -wire \z80_|alu_control_|db[2]~23_combout ; -wire \z80_|reg_file_|db_lo_ds[2]~2_combout ; -wire \z80_|alu_control_|db[2]~28_combout ; -wire \z80_|alu_control_|db[2]~27_combout ; -wire \z80_|alu_control_|db[2]~29_combout ; -wire \z80_|alu_|db[2]~14_combout ; -wire \z80_|alu_|db[2]~15_combout ; -wire \z80_|alu_|db_low[2]~2_combout ; -wire \z80_|alu_|db_low[2]~3_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ; -wire \z80_|alu_|db_low[2]~5_combout ; -wire \z80_|alu_|db_low[2]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ; -wire \z80_|alu_|alu_op2[2]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; -wire \z80_|alu_|db_high[2]~9_combout ; -wire \z80_|alu_|db_high[2]~11_combout ; -wire \z80_|alu_|db_high[2]~12_combout ; -wire \z80_|alu_|db_high[2]~10_combout ; -wire \z80_|alu_|db_high[2]~13_combout ; -wire \z80_|alu_|db_high[2]~14_combout ; -wire \z80_|alu_|db[6]~22_combout ; -wire \z80_|alu_|db[6]~23_combout ; -wire \z80_|alu_control_|out[6]~1_combout ; -wire \z80_|alu_control_|out[6]~2_combout ; -wire \z80_|alu_control_|db[6]~19_combout ; -wire \z80_|alu_control_|db[6]~20_combout ; -wire \z80_|alu_control_|db[6]~21_combout ; -wire \z80_|alu_control_|db[6]~22_combout ; -wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; -wire \z80_|interrupts_|im1~q ; -wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; -wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; -wire \z80_|bus_control_|db[0]~4_combout ; -wire \z80_|bus_control_|db[6]~8_combout ; -wire \z80_|execute_|ctl_mRead~37_combout ; -wire \z80_|execute_|ctl_mRead~28_combout ; -wire \z80_|execute_|ctl_mRead~29_combout ; -wire \z80_|execute_|ctl_mRead~30_combout ; -wire \z80_|execute_|setM1~37_combout ; -wire \z80_|execute_|setM1~55_combout ; -wire \z80_|execute_|setM1~38_combout ; -wire \z80_|execute_|ctl_mRead~34_combout ; -wire \z80_|execute_|nextM~3_combout ; -wire \z80_|execute_|ctl_mRead~31_combout ; -wire \z80_|execute_|ctl_mRead~32_combout ; -wire \z80_|execute_|ctl_mRead~33_combout ; -wire \z80_|execute_|ctl_mRead~35_combout ; -wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; -wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; -wire \z80_|memory_ifc_|wait_mrd~q ; -wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; -wire \z80_|memory_ifc_|nRD_out~1_combout ; -wire \z80_|execute_|nextM~4_combout ; -wire \z80_|execute_|ctl_iorw~12_combout ; -wire \z80_|execute_|ctl_iorw~8_combout ; -wire \z80_|execute_|ctl_iorw~9_combout ; -wire \z80_|memory_ifc_|DFFE_iorq_ff1~q ; -wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ; -wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ; -wire \z80_|memory_ifc_|wait_iorq~q ; -wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; -wire \z80_|memory_ifc_|iorq~0_combout ; -wire \z80_|execute_|fIORead~1_combout ; -wire \z80_|execute_|fIORead~2_combout ; -wire \z80_|execute_|fIORead~0_combout ; -wire \z80_|execute_|fIORead~3_combout ; -wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; -wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; -wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; -wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; -wire \z80_|memory_ifc_|nRD_out~0_combout ; -wire \z80_|memory_ifc_|nRD_out~2_combout ; -wire \Equal2~1_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~0_combout ; -wire \z80_|execute_|fMWrite~5_combout ; -wire \z80_|execute_|fMWrite~6_combout ; -wire \z80_|execute_|fMWrite~2_combout ; -wire \z80_|execute_|fMWrite~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~1_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; -wire \z80_|execute_|fMWrite~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; -wire \z80_|execute_|fMWrite~9_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; -wire \z80_|execute_|fMWrite~8_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; -wire \z80_|execute_|fMWrite~10_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; -wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; -wire \z80_|clk_delay_|DFF_inst5~q ; -wire \z80_|memory_ifc_|wait_iorqinta~feeder_combout ; -wire \z80_|memory_ifc_|wait_iorqinta~q ; -wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; -wire \z80_|memory_ifc_|nIORQ_out~0_combout ; -wire \Equal2~0_combout ; -wire \ExtRamWE~0_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; +wire \z80_|reg_file_|db_hi_as[0]~2_combout ; +wire \z80_|reg_file_|db_hi_as[3]~7_combout ; +wire \z80_|reg_file_|db_hi_as[3]~8_combout ; +wire \z80_|reg_file_|db_hi_as[3]~9_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; wire \z80_|execute_|ctl_apin_mux2~0_combout ; wire \z80_|pin_control_|bus_ab_pin_we~2_combout ; wire \z80_|pin_control_|bus_ab_pin_we~3_combout ; -wire \z80_|address_pins_|abus[13]~20_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; -wire \z80_|address_pins_|abus[14]~23_combout ; +wire \z80_|address_pins_|abus[11]~19_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; +wire \z80_|address_pins_|abus[10]~20_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~19_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~48_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~51_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~q ; +wire \D[2]~43_combout ; +wire \ula_|zx_keyboard_|WideOr17~0_combout ; +wire \ula_|zx_keyboard_|shifted~2_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~11_combout ; +wire \ula_|zx_keyboard_|shifted~0_combout ; +wire \ula_|zx_keyboard_|shifted~3_combout ; +wire \ula_|zx_keyboard_|shifted~q ; +wire \ula_|zx_keyboard_|keys[5][0]~62_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~32_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~63_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~64_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~65_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~q ; wire \z80_|address_pins_|DFFE_apin_latch[15]~15_combout ; -wire \z80_|address_pins_|abus[15]~22_combout ; -wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; +wire \z80_|address_pins_|abus[15]~21_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; +wire \z80_|address_pins_|abus[14]~22_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~57_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~58_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~59_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~28_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~60_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~56_combout ; +wire \ula_|zx_keyboard_|Selector13~0_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~q ; +wire \D[2]~44_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; +wire \z80_|address_pins_|abus[12]~24_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~29_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~54_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~55_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~q ; +wire \ula_|zx_keyboard_|key_row~1_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~127_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~66_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~128_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~67_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~q ; +wire \D[2]~45_combout ; wire \z80_|address_pins_|abus[0]~16_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~43_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~44_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~45_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~46_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~q ; +wire \ula_|zx_keyboard_|keys[0][2]~47_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~49_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~q ; +wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; +wire \z80_|address_pins_|abus[9]~17_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; +wire \z80_|address_pins_|abus[8]~18_combout ; +wire \D[2]~42_combout ; +wire \D[2]~46_combout ; +wire \z80_|memory_ifc_|wait_iorqinta~q ; +wire \z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ; +wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; +wire \z80_|control_pins_|pin_nIORQ~1_combout ; +wire \Equal2~0_combout ; +wire \z80_|address_pins_|abus[13]~23_combout ; +wire \ExtRamWE~0_combout ; +wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; wire \z80_|address_pins_|DFFE_apin_latch[1]~1_combout ; wire \z80_|address_pins_|abus[1]~25_combout ; wire \z80_|address_pins_|DFFE_apin_latch[2]~2_combout ; @@ -1807,30 +1993,20 @@ wire \z80_|address_pins_|DFFE_apin_latch[6]~6_combout ; wire \z80_|address_pins_|abus[6]~30_combout ; wire \z80_|address_pins_|DFFE_apin_latch[7]~7_combout ; wire \z80_|address_pins_|abus[7]~31_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; -wire \z80_|address_pins_|abus[8]~18_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; -wire \z80_|address_pins_|abus[9]~17_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; -wire \z80_|address_pins_|abus[10]~24_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; -wire \z80_|address_pins_|abus[11]~19_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; -wire \z80_|address_pins_|abus[12]~21_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; -wire \D[6]~90_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; -wire \D[6]~91_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; +wire \D[2]~50_combout ; +wire \D[2]~51_combout ; wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ; wire \CLOCK_50~inputclkctrl_outclk ; wire \~GND~combout ; -wire \ula_|video_|vram_address[0]~feeder_combout ; wire \ula_|video_|vram_address~0_combout ; +wire \ula_|video_|vram_address[1]~feeder_combout ; wire \ula_|video_|vram_address[2]~4_combout ; wire \ula_|video_|Add3~0_combout ; wire \ula_|video_|Add3~1_combout ; @@ -1842,638 +2018,521 @@ wire \ula_|video_|Add4~7 ; wire \ula_|video_|Add4~8_combout ; wire \ula_|video_|Add4~9 ; wire \ula_|video_|Add4~10_combout ; +wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Add4~11 ; wire \ula_|video_|Add4~12_combout ; -wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Selector6~0_combout ; -wire \ula_|video_|vram_address[9]~1_combout ; +wire \ula_|video_|vram_address[8]~1_combout ; wire \ula_|video_|Add4~13 ; wire \ula_|video_|Add4~14_combout ; wire \ula_|video_|Add4~2_combout ; wire \ula_|video_|Selector5~0_combout ; -wire \ula_|video_|Add4~4_combout ; wire \ula_|video_|vram_address[10]~2_combout ; +wire \ula_|video_|Add4~4_combout ; wire \ula_|video_|vram_address[10]~3_combout ; wire \ula_|video_|Selector3~0_combout ; wire \ula_|video_|Selector2~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \D[6]~87_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \D[6]~88_combout ; -wire \D[6]~89_combout ; -wire \D[6]~111_combout ; -wire \raw_loader_in~input_o ; -wire \D[6]~86_combout ; -wire \D[6]~100_combout ; -wire \D[6]~101_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \D[2]~47_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \D[2]~48_combout ; +wire \D[2]~49_combout ; +wire \D[2]~119_combout ; +wire \D[2]~52_combout ; +wire \D[2]~53_combout ; wire \z80_|pin_control_|bus_db_pin_re~2_combout ; wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; -wire \z80_|bus_control_|db[6]~9_combout ; -wire \z80_|ir_|opcode[6]~feeder_combout ; +wire \z80_|bus_control_|db[2]~12_combout ; +wire \z80_|bus_control_|db[0]~6_combout ; +wire \z80_|bus_control_|db[2]~13_combout ; +wire \z80_|ir_|opcode[2]~feeder_combout ; wire \z80_|execute_|ctl_ir_we~13_combout ; -wire \z80_|pla_decode_|Equal41~0_combout ; -wire \z80_|pla_decode_|Equal41~1_combout ; -wire \z80_|pla_decode_|Equal41~2_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~combout ; -wire \z80_|alu_|db_high[1]~15_combout ; -wire \z80_|alu_|db_high[1]~16_combout ; -wire \z80_|alu_|db_high[1]~17_combout ; -wire \z80_|alu_|db_high[1]~18_combout ; -wire \z80_|alu_|db_high[1]~19_combout ; -wire \z80_|alu_|db_high[1]~20_combout ; -wire \z80_|alu_|db[5]~24_combout ; -wire \z80_|alu_|db[5]~25_combout ; -wire \z80_|sw1_|db_down[5]~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; -wire \z80_|alu_flags_|flags_yf~q ; -wire \z80_|alu_control_|db[5]~13_combout ; -wire \z80_|alu_control_|db[5]~14_combout ; -wire \z80_|alu_control_|db[5]~15_combout ; -wire \D[0]~107_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \Mux2~0_combout ; -wire \Mux2~1_combout ; -wire \D[5]~110_combout ; -wire \D[5]~85_combout ; -wire \D[5]~99_combout ; -wire \z80_|bus_control_|db[5]~14_combout ; -wire \z80_|bus_control_|db[5]~15_combout ; -wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|decode_state_|DFFE_inst4~q ; -wire \z80_|decode_state_|use_ixiy~combout ; -wire \z80_|execute_|ctl_mRead~23_combout ; -wire \z80_|execute_|fMRead~34_combout ; -wire \z80_|execute_|fMRead~31_combout ; +wire \z80_|execute_|ctl_mRead~34_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ; +wire \z80_|execute_|ctl_reg_out_lo~6_combout ; +wire \z80_|execute_|ctl_reg_out_lo~7_combout ; +wire \z80_|execute_|ctl_reg_out_lo~8_combout ; +wire \z80_|alu_control_|db[6]~13_combout ; +wire \z80_|alu_control_|db[6]~21_combout ; +wire \z80_|alu_control_|db[6]~22_combout ; +wire \z80_|reg_file_|db_lo_ds[6]~0_combout ; +wire \z80_|sw1_|db_down[6]~1_combout ; +wire \z80_|alu_control_|db[6]~23_combout ; +wire \z80_|bus_control_|db[6]~8_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; +wire \D[6]~103_combout ; +wire \D[6]~104_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \D[6]~100_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \D[6]~101_combout ; +wire \D[6]~102_combout ; +wire \D[6]~127_combout ; +wire \raw_loader_in~input_o ; +wire \D[6]~99_combout ; +wire \D[6]~114_combout ; +wire \D[6]~115_combout ; +wire \z80_|bus_control_|db[6]~9_combout ; +wire \z80_|pla_decode_|Equal13~0_combout ; +wire \z80_|pla_decode_|Equal38~2_combout ; +wire \z80_|interrupts_|iff1~0_combout ; +wire \z80_|interrupts_|iff1~1_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|interrupts_|iff1~q ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ; +wire \z80_|interrupts_|int_armed~q ; +wire \z80_|interrupts_|DFFE_inst44~q ; +wire \z80_|decode_state_|in_halt~0_combout ; +wire \z80_|pla_decode_|Equal77~1_combout ; +wire \z80_|decode_state_|in_halt~1_combout ; +wire \z80_|decode_state_|in_halt~q ; +wire \z80_|execute_|ctl_mRead~21_combout ; +wire \z80_|execute_|fMRead~35_combout ; +wire \z80_|execute_|fMRead~23_combout ; +wire \z80_|execute_|fMRead~27_combout ; +wire \z80_|execute_|fMRead~28_combout ; wire \z80_|execute_|fMRead~29_combout ; wire \z80_|execute_|fMRead~30_combout ; -wire \z80_|execute_|fMRead~28_combout ; +wire \z80_|execute_|fMRead~31_combout ; wire \z80_|execute_|fMRead~32_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; -wire \z80_|execute_|fMRead~14_combout ; -wire \z80_|execute_|fMRead~10_combout ; -wire \z80_|execute_|fMRead~9_combout ; +wire \z80_|execute_|fMRead~37_combout ; +wire \z80_|execute_|fMRead~33_combout ; +wire \z80_|execute_|fMRead~24_combout ; +wire \z80_|execute_|fMRead~25_combout ; +wire \z80_|execute_|fMRead~16_combout ; wire \z80_|execute_|fMRead~11_combout ; wire \z80_|execute_|fMRead~12_combout ; wire \z80_|execute_|fMRead~13_combout ; +wire \z80_|execute_|fMRead~14_combout ; wire \z80_|execute_|fMRead~15_combout ; -wire \z80_|execute_|fMRead~20_combout ; -wire \z80_|execute_|pc_inc_hold~48_combout ; +wire \z80_|execute_|fMRead~17_combout ; wire \z80_|execute_|fMRead~22_combout ; -wire \z80_|execute_|fMRead~21_combout ; -wire \z80_|execute_|fMRead~23_combout ; -wire \z80_|execute_|fMRead~26_combout ; -wire \z80_|execute_|fMRead~25_combout ; -wire \z80_|execute_|fMRead~27_combout ; -wire \z80_|execute_|fMRead~33_combout ; -wire \z80_|execute_|fMRead~35_combout ; +wire \z80_|execute_|fMRead~34_combout ; +wire \z80_|execute_|fMRead~36_combout ; wire \z80_|pin_control_|bus_db_pin_re~combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \Selector1~0_combout ; -wire \Selector1~1_combout ; -wire \D[1]~103_combout ; -wire \PS2_DAT~input_o ; -wire \reset~clkctrl_outclk ; -wire \ula_|ps2_keyboard_|bit_count~0_combout ; -wire \PS2_CLK~input_o ; -wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~0_combout ; -wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~1_combout ; -wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~q ; -wire \ula_|ps2_keyboard_|clk_edge~0_combout ; -wire \ula_|ps2_keyboard_|clk_edge~q ; -wire \ula_|ps2_keyboard_|bit_count~1_combout ; -wire \ula_|ps2_keyboard_|bit_count~3_combout ; -wire \ula_|ps2_keyboard_|bit_count~2_combout ; -wire \ula_|ps2_keyboard_|always1~0_combout ; -wire \ula_|ps2_keyboard_|LessThan0~0_combout ; -wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; -wire \ula_|zx_keyboard_|Equal0~0_combout ; -wire \ula_|zx_keyboard_|Equal0~1_combout ; -wire \ula_|zx_keyboard_|extended~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~1_combout ; -wire \ula_|ps2_keyboard_|WideXor0~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~2_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~q ; -wire \ula_|zx_keyboard_|extended~q ; -wire \ula_|zx_keyboard_|keys[0][0]~15_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; -wire \ula_|zx_keyboard_|shifted~0_combout ; -wire \ula_|zx_keyboard_|released~0_combout ; -wire \ula_|zx_keyboard_|released~q ; -wire \ula_|zx_keyboard_|WideOr17~0_combout ; -wire \ula_|zx_keyboard_|shifted~2_combout ; -wire \ula_|zx_keyboard_|shifted~3_combout ; -wire \ula_|zx_keyboard_|shifted~q ; -wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~103_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~20_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~21_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~q ; +wire \ula_|zx_keyboard_|keys[3][0]~73_combout ; +wire \ula_|zx_keyboard_|Selector5~0_combout ; +wire \ula_|zx_keyboard_|Selector5~1_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~129_combout ; +wire \ula_|zx_keyboard_|WideOr16~1_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~105_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~130_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~q ; +wire \D[3]~74_combout ; wire \ula_|zx_keyboard_|keys[5][1]~39_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~q ; -wire \ula_|zx_keyboard_|keys[4][1]~31_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~23_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~32_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~33_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~34_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~q ; -wire \D[1]~30_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~24_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~29_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~30_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~25_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~26_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~27_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~q ; -wire \ula_|zx_keyboard_|key_row~0_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~17_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~18_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~q ; -wire \ula_|zx_keyboard_|keys[7][4]~19_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~20_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~21_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~22_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~q ; -wire \D[1]~28_combout ; -wire \D[1]~29_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~43_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~44_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~q ; -wire \ula_|zx_keyboard_|keys[7][1]~45_combout ; -wire \ula_|zx_keyboard_|WideOr16~5_combout ; -wire \ula_|zx_keyboard_|WideOr16~2_combout ; -wire \ula_|zx_keyboard_|WideOr16~4_combout ; -wire \ula_|zx_keyboard_|WideOr16~7_combout ; -wire \ula_|zx_keyboard_|WideOr16~6_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~46_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~q ; -wire \D[1]~31_combout ; -wire \D[1]~32_combout ; -wire \D[1]~33_combout ; -wire \D[1]~34_combout ; -wire \z80_|bus_control_|db[1]~10_combout ; -wire \z80_|bus_control_|db[1]~11_combout ; -wire \z80_|ir_|opcode[1]~feeder_combout ; -wire \z80_|pla_decode_|Equal40~0_combout ; -wire \z80_|pla_decode_|Equal21~1_combout ; -wire \z80_|execute_|ctl_alu_op_low~26_combout ; -wire \z80_|execute_|ctl_alu_op_low~28_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; -wire \z80_|execute_|ctl_alu_op_low~32_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; -wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~10_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; -wire \z80_|execute_|ctl_flags_cf_set~0_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~9_combout ; -wire \z80_|alu_flags_|flags_cf~combout ; -wire \z80_|alu_control_|db[0]~8_combout ; -wire \z80_|sw2_|db_up[0]~0_combout ; -wire \z80_|alu_control_|db[0]~9_combout ; -wire \z80_|alu_control_|db[0]~12_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~67_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~81_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~82_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~83_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~q ; -wire \ula_|zx_keyboard_|keys[4][0]~84_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~85_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~86_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~q ; -wire \D[0]~49_combout ; -wire \ula_|zx_keyboard_|WideOr4~0_combout ; -wire \ula_|zx_keyboard_|keys~76_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~73_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~47_combout ; -wire \ula_|zx_keyboard_|WideOr0~0_combout ; -wire \ula_|zx_keyboard_|keys~74_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~75_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~77_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~q ; -wire \ula_|zx_keyboard_|keys[1][0]~71_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~72_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~q ; -wire \D[0]~47_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~80_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~q ; -wire \ula_|zx_keyboard_|keys[3][0]~78_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~79_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~q ; -wire \ula_|zx_keyboard_|key_row~1_combout ; -wire \D[0]~48_combout ; -wire \ula_|zx_keyboard_|shifted~1_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~91_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~92_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~q ; -wire \ula_|zx_keyboard_|keys[5][4]~63_combout ; -wire \ula_|zx_keyboard_|WideOr16~3_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~132_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~88_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~89_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~q ; -wire \D[0]~50_combout ; -wire \D[0]~51_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~55_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \D[0]~56_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \D[0]~52_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~53_combout ; -wire \D[0]~54_combout ; -wire \D[0]~106_combout ; -wire \D[0]~57_combout ; -wire \D[0]~58_combout ; -wire \z80_|bus_control_|db[0]~16_combout ; -wire \z80_|bus_control_|db[0]~17_combout ; -wire \z80_|pla_decode_|Equal63~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; -wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; -wire \z80_|alu_control_|db[6]~10_combout ; -wire \z80_|alu_control_|db[6]~11_combout ; -wire \z80_|alu_control_|db[4]~30_combout ; -wire \z80_|alu_control_|db[4]~31_combout ; -wire \z80_|alu_control_|db[4]~32_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~119_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~120_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~95_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~121_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~q ; -wire \ula_|zx_keyboard_|keys[3][4]~117_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~136_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~130_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~118_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~q ; -wire \D[4]~78_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~126_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~128_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~129_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~q ; -wire \ula_|zx_keyboard_|keys[6][4]~127_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~q ; -wire \ula_|zx_keyboard_|Equal0~2_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~51_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~125_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~q ; -wire \D[4]~79_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~122_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~123_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~q ; -wire \ula_|zx_keyboard_|key_row~3_combout ; -wire \D[4]~80_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~111_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~97_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~116_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~115_combout ; -wire \ula_|zx_keyboard_|keys[1][4]~q ; -wire \D[4]~77_combout ; -wire \D[4]~81_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \Selector4~0_combout ; -wire \Selector4~1_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ; -wire \D[4]~109_combout ; -wire \D[4]~97_combout ; -wire \D[4]~98_combout ; -wire \z80_|bus_control_|db[4]~18_combout ; -wire \z80_|bus_control_|db[4]~19_combout ; -wire \z80_|pla_decode_|Equal21~0_combout ; -wire \z80_|execute_|ctl_mRead~5_combout ; -wire \z80_|execute_|fIOWrite~2_combout ; -wire \z80_|execute_|fIOWrite~3_combout ; -wire \z80_|execute_|fIOWrite~4_combout ; -wire \z80_|execute_|fIOWrite~5_combout ; -wire \z80_|execute_|ctl_mWrite~11_combout ; -wire \z80_|execute_|ctl_mWrite~12_combout ; -wire \z80_|execute_|ctl_mWrite~13_combout ; -wire \z80_|execute_|ctl_mWrite~14_combout ; -wire \z80_|execute_|ctl_mWrite~15_combout ; -wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; -wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; -wire \z80_|memory_ifc_|wait_mwr~q ; -wire \z80_|memory_ifc_|mwr_wr~q ; -wire \z80_|memory_ifc_|nWR_out~0_combout ; -wire \D[5]~84_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~100_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~99_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~q ; +wire \ula_|zx_keyboard_|keys[3][3]~97_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~98_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~q ; +wire \D[3]~73_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~108_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~109_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~110_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~q ; +wire \ula_|zx_keyboard_|keys[6][3]~111_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~112_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~132_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~133_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~q ; +wire \D[3]~75_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~94_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~93_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~95_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~96_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~q ; +wire \ula_|zx_keyboard_|keys[1][3]~91_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~92_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~q ; +wire \D[3]~72_combout ; +wire \D[3]~76_combout ; +wire \D[3]~122_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \D[3]~79_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \D[3]~77_combout ; +wire \D[3]~80_combout ; +wire \D[3]~81_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \D[3]~124_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \D[3]~123_combout ; +wire \D[3]~78_combout ; +wire \D[3]~82_combout ; +wire \D[3]~108_combout ; +wire \D[3]~109_combout ; +wire \z80_|bus_control_|db[3]~20_combout ; +wire \z80_|bus_control_|db[3]~21_combout ; +wire \z80_|pla_decode_|Equal33~1_combout ; +wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; +wire \z80_|bus_control_|db[0]~4_combout ; +wire \z80_|bus_control_|db[7]~5_combout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ; +wire \D[5]~97_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; wire \Mux0~0_combout ; wire \Mux0~1_combout ; -wire \D[7]~112_combout ; -wire \D[7]~94_combout ; -wire \D[7]~102_combout ; -wire \z80_|bus_control_|db[7]~5_combout ; +wire \D[7]~116_combout ; +wire \D[7]~117_combout ; wire \z80_|bus_control_|db[7]~7_combout ; -wire \z80_|pla_decode_|Equal77~0_combout ; -wire \z80_|execute_|ctl_mWrite~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; -wire \z80_|execute_|ctl_bus_db_we~3_combout ; -wire \z80_|execute_|ctl_bus_db_we~8_combout ; -wire \z80_|execute_|ctl_bus_db_we~2_combout ; -wire \z80_|execute_|ctl_bus_db_we~4_combout ; -wire \z80_|execute_|ctl_bus_db_we~6_combout ; -wire \z80_|execute_|ctl_bus_db_we~7_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~50_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~52_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~q ; -wire \ula_|zx_keyboard_|keys[3][3]~48_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~49_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~q ; -wire \D[2]~35_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~57_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~58_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~q ; -wire \ula_|zx_keyboard_|keys[4][2]~59_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~131_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~60_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~q ; -wire \D[2]~37_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~53_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~55_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~56_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~q ; -wire \ula_|zx_keyboard_|keys[3][2]~54_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~q ; -wire \D[2]~36_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~68_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~69_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~70_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~q ; -wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~62_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~64_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~65_combout ; -wire \ula_|zx_keyboard_|Selector13~0_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~66_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~q ; -wire \D[2]~38_combout ; -wire \D[2]~39_combout ; -wire \D[2]~104_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \D[2]~43_combout ; -wire \D[2]~44_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \D[2]~40_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \D[2]~41_combout ; -wire \D[2]~42_combout ; -wire \D[2]~105_combout ; -wire \D[2]~45_combout ; -wire \D[2]~46_combout ; -wire \z80_|bus_control_|db[2]~12_combout ; -wire \z80_|bus_control_|db[2]~13_combout ; -wire \z80_|pla_decode_|Equal3~1_combout ; -wire \z80_|pla_decode_|Equal43~0_combout ; -wire \z80_|interrupts_|test1~2_combout ; -wire \z80_|interrupts_|test1~3_combout ; -wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ; -wire \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ; -wire \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ; -wire \z80_|clk_delay_|hold_clk_iorq~combout ; -wire \z80_|sequencer_|DFFE_T1_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; -wire \z80_|sequencer_|DFFE_T2_ff~q ; -wire \z80_|resets_|x3~combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \z80_|sequencer_|DFFE_M1_ff~q ; -wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M2_ff~q ; -wire \z80_|execute_|ctl_mWrite~3_combout ; -wire \z80_|execute_|nextM~11_combout ; -wire \z80_|execute_|nextM~8_combout ; -wire \z80_|execute_|nextM~9_combout ; -wire \z80_|execute_|nextM~10_combout ; -wire \z80_|execute_|nextM~12_combout ; -wire \z80_|execute_|nextM~15_combout ; -wire \z80_|execute_|nextM~6_combout ; -wire \z80_|execute_|nextM~7_combout ; -wire \z80_|execute_|nextM~13_combout ; -wire \z80_|execute_|setM1~39_combout ; -wire \z80_|execute_|nextM~5_combout ; -wire \z80_|execute_|nextM~14_combout ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|sequencer_|DFFE_T4_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|sequencer_|DFFE_T5_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; -wire \z80_|sequencer_|T6~q ; -wire \z80_|execute_|setM1~13_combout ; -wire \z80_|pla_decode_|Equal77~1_combout ; -wire \z80_|execute_|setM1~12_combout ; -wire \z80_|execute_|setM1~14_combout ; -wire \z80_|execute_|setM1~41_combout ; -wire \z80_|execute_|setM1~42_combout ; -wire \z80_|execute_|setM1~43_combout ; -wire \z80_|execute_|setM1~44_combout ; -wire \z80_|execute_|setM1~50_combout ; -wire \z80_|execute_|setM1~51_combout ; -wire \z80_|execute_|setM1~6_combout ; -wire \z80_|execute_|setM1~7_combout ; -wire \z80_|execute_|setM1~8_combout ; -wire \z80_|execute_|setM1~9_combout ; -wire \z80_|execute_|setM1~10_combout ; -wire \z80_|execute_|setM1~11_combout ; -wire \z80_|execute_|setM1~17_combout ; -wire \z80_|execute_|setM1~31_combout ; -wire \z80_|execute_|setM1~28_combout ; -wire \z80_|execute_|setM1~30_combout ; -wire \z80_|execute_|setM1~32_combout ; -wire \z80_|execute_|setM1~33_combout ; -wire \z80_|execute_|setM1~25_combout ; -wire \z80_|execute_|setM1~26_combout ; -wire \z80_|execute_|setM1~24_combout ; -wire \z80_|execute_|setM1~27_combout ; -wire \z80_|execute_|setM1~22_combout ; -wire \z80_|execute_|setM1~21_combout ; -wire \z80_|execute_|setM1~53_combout ; -wire \z80_|execute_|setM1~23_combout ; -wire \z80_|execute_|setM1~18_combout ; -wire \z80_|execute_|setM1~19_combout ; -wire \z80_|execute_|setM1~20_combout ; -wire \z80_|execute_|setM1~34_combout ; -wire \z80_|execute_|setM1~52_combout ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; -wire \z80_|sequencer_|DFFE_T3_ff~q ; -wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; -wire \z80_|decode_state_|in_halt~0_combout ; -wire \z80_|decode_state_|in_halt~1_combout ; -wire \z80_|decode_state_|in_halt~q ; +wire \z80_|pla_decode_|Equal41~0_combout ; +wire \z80_|pla_decode_|Equal41~1_combout ; +wire \z80_|pla_decode_|Equal41~2_combout ; +wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; +wire \z80_|execute_|ctl_state_tbl_we~8_combout ; +wire \z80_|decode_state_|DFFE_instCB~q ; +wire \z80_|pla_decode_|Equal52~0_combout ; +wire \z80_|execute_|ctl_66_oe~2_combout ; +wire \z80_|interrupts_|im1~q ; +wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; +wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; wire \z80_|execute_|ctl_bus_db_oe~2_combout ; wire \z80_|execute_|ctl_bus_db_oe~5_combout ; wire \z80_|execute_|ctl_bus_db_oe~6_combout ; wire \z80_|execute_|ctl_bus_db_oe~4_combout ; wire \z80_|execute_|ctl_bus_db_oe~combout ; -wire \z80_|bus_control_|db[0]~6_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~93_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~94_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~q ; -wire \ula_|zx_keyboard_|keys[0][3]~96_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~98_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~q ; -wire \D[3]~65_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~99_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~100_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~q ; -wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~133_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~103_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~q ; -wire \D[3]~66_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~105_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~q ; -wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; -wire \ula_|zx_keyboard_|Selector5~1_combout ; -wire \ula_|zx_keyboard_|Selector5~0_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~134_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~135_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~108_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~q ; -wire \D[3]~67_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~112_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~113_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~114_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~q ; -wire \ula_|zx_keyboard_|keys[6][3]~109_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~110_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~137_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~138_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~q ; +wire \ula_|zx_keyboard_|keys[6][0]~88_combout ; +wire \ula_|zx_keyboard_|shifted~1_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~89_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~q ; +wire \ula_|zx_keyboard_|keys[7][0]~84_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~78_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~85_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~86_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~q ; +wire \D[0]~57_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~81_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~82_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~40_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~83_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~q ; +wire \ula_|zx_keyboard_|keys[5][0]~79_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~80_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~q ; +wire \D[0]~56_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~76_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~77_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~q ; +wire \ula_|zx_keyboard_|keys[4][3]~68_combout ; +wire \ula_|zx_keyboard_|WideOr0~0_combout ; +wire \ula_|zx_keyboard_|keys~69_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~70_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~27_combout ; +wire \ula_|zx_keyboard_|WideOr4~0_combout ; +wire \ula_|zx_keyboard_|keys~71_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~72_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~q ; wire \ula_|zx_keyboard_|key_row~2_combout ; -wire \D[3]~68_combout ; -wire \D[3]~69_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \D[3]~73_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; -wire \D[3]~74_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \D[3]~70_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~71_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~72_combout ; -wire \D[3]~108_combout ; -wire \D[3]~95_combout ; -wire \D[3]~96_combout ; -wire \z80_|bus_control_|db[3]~20_combout ; -wire \z80_|bus_control_|db[3]~21_combout ; -wire \z80_|execute_|ctl_mWrite~4_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~22_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~75_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~q ; +wire \ula_|zx_keyboard_|keys[3][1]~24_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~74_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~q ; +wire \D[0]~54_combout ; +wire \D[0]~55_combout ; +wire \D[0]~58_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; +wire \D[0]~62_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \D[0]~63_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \D[0]~59_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \D[0]~60_combout ; +wire \D[0]~61_combout ; +wire \D[0]~120_combout ; +wire \D[0]~64_combout ; +wire \D[0]~65_combout ; +wire \z80_|bus_control_|db[0]~16_combout ; +wire \z80_|bus_control_|db[0]~17_combout ; +wire \z80_|pla_decode_|Equal3~2_combout ; +wire \z80_|execute_|ctl_state_iy_set~2_combout ; +wire \z80_|decode_state_|DFFE_instIY1~q ; +wire \z80_|decode_state_|use_ixiy~combout ; +wire \z80_|execute_|ixy_d~12_combout ; +wire \z80_|execute_|ixy_d~13_combout ; +wire \z80_|execute_|ixy_d~14_combout ; +wire \z80_|execute_|ixy_d~11_combout ; +wire \z80_|execute_|ixy_d~15_combout ; +wire \z80_|execute_|ctl_flags_xy_we~8_combout ; +wire \z80_|execute_|ctl_flags_xy_we~9_combout ; +wire \z80_|execute_|ctl_alu_oe~11_combout ; +wire \z80_|execute_|ctl_alu_oe~12_combout ; +wire \z80_|execute_|ctl_alu_oe~13_combout ; +wire \z80_|execute_|ctl_alu_oe~14_combout ; +wire \z80_|alu_|db[7]~9_combout ; +wire \z80_|alu_|db[1]~15_combout ; +wire \z80_|alu_|db[1]~16_combout ; +wire \z80_|alu_control_|db[1]~25_combout ; +wire \z80_|alu_control_|db[1]~26_combout ; +wire \z80_|sw1_|db_down[1]~2_combout ; +wire \z80_|alu_control_|db[1]~27_combout ; +wire \z80_|bus_control_|db[1]~10_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~41_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~42_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~q ; +wire \ula_|zx_keyboard_|keys[4][1]~30_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~q ; +wire \ula_|zx_keyboard_|key_row~0_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~36_combout ; +wire \ula_|zx_keyboard_|WideOr16~3_combout ; +wire \ula_|zx_keyboard_|WideOr16~0_combout ; +wire \ula_|zx_keyboard_|WideOr16~2_combout ; +wire \ula_|zx_keyboard_|WideOr16~4_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~37_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~q ; +wire \ula_|zx_keyboard_|keys[6][1]~33_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~34_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~31_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~35_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~q ; +wire \D[1]~32_combout ; +wire \D[1]~33_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~16_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~17_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~18_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~q ; +wire \ula_|zx_keyboard_|keys[0][1]~12_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~13_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~10_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~q ; +wire \D[1]~30_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~25_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~26_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~q ; +wire \ula_|zx_keyboard_|keys[2][1]~23_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~q ; +wire \D[1]~31_combout ; +wire \D[1]~34_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \D[1]~38_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \D[1]~39_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \D[1]~35_combout ; +wire \D[1]~36_combout ; +wire \D[1]~37_combout ; +wire \D[1]~118_combout ; +wire \D[1]~40_combout ; +wire \D[1]~41_combout ; +wire \z80_|bus_control_|db[1]~11_combout ; +wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; +wire \z80_|decode_state_|DFFE_instED~q ; +wire \z80_|pla_decode_|Equal6~0_combout ; +wire \z80_|execute_|ctl_mRead~8_combout ; +wire \z80_|execute_|ctl_bus_db_we~2_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; +wire \z80_|execute_|ctl_bus_db_we~3_combout ; +wire \z80_|execute_|ctl_bus_db_we~8_combout ; +wire \z80_|execute_|ctl_bus_db_we~4_combout ; +wire \z80_|execute_|ctl_bus_db_we~6_combout ; +wire \z80_|execute_|ctl_bus_db_we~7_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~126_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~q ; +wire \ula_|zx_keyboard_|keys[7][4]~125_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~q ; +wire \D[4]~88_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~120_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~121_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~q ; +wire \ula_|zx_keyboard_|keys[4][4]~122_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~123_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~q ; +wire \D[4]~87_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~115_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~116_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~117_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~q ; +wire \ula_|zx_keyboard_|key_row~3_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~118_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~131_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~119_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~q ; +wire \ula_|zx_keyboard_|keys[0][4]~114_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~q ; +wire \ula_|zx_keyboard_|keys[1][4]~113_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~q ; +wire \D[4]~85_combout ; +wire \D[4]~86_combout ; +wire \D[4]~89_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; +wire \D[4]~93_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; +wire \D[4]~94_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \D[4]~90_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \D[4]~91_combout ; +wire \D[4]~92_combout ; +wire \D[4]~125_combout ; +wire \D[4]~110_combout ; +wire \D[4]~111_combout ; +wire \z80_|bus_control_|db[4]~18_combout ; +wire \z80_|bus_control_|db[4]~19_combout ; +wire \z80_|pla_decode_|Equal32~0_combout ; +wire \z80_|pla_decode_|Equal36~0_combout ; +wire \z80_|pla_decode_|Equal43~0_combout ; +wire \z80_|interrupts_|test1~2_combout ; +wire \z80_|interrupts_|test1~3_combout ; +wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ; +wire \z80_|sw1_|db_down[5]~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; +wire \z80_|alu_flags_|flags_yf~q ; +wire \z80_|alu_control_|db[5]~15_combout ; +wire \z80_|alu_control_|db[5]~16_combout ; +wire \z80_|alu_control_|db[5]~17_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \Mux2~0_combout ; +wire \Mux2~1_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ; +wire \D[5]~112_combout ; +wire \D[5]~113_combout ; +wire \z80_|bus_control_|db[5]~14_combout ; +wire \z80_|bus_control_|db[5]~15_combout ; +wire \z80_|execute_|ctl_mRead~11_combout ; +wire \z80_|execute_|setM1~46_combout ; +wire \z80_|execute_|setM1~40_combout ; +wire \z80_|execute_|nextM~5_combout ; +wire \z80_|execute_|nextM~6_combout ; +wire \z80_|execute_|nextM~7_combout ; +wire \z80_|execute_|nextM~9_combout ; +wire \z80_|execute_|nextM~10_combout ; +wire \z80_|execute_|nextM~8_combout ; +wire \z80_|execute_|nextM~12_combout ; +wire \z80_|execute_|nextM~15_combout ; +wire \z80_|execute_|nextM~13_combout ; +wire \z80_|execute_|nextM~14_combout ; +wire \z80_|sequencer_|ena_M~combout ; +wire \z80_|sequencer_|DFFE_T1_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; +wire \z80_|sequencer_|DFFE_T2_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; +wire \z80_|sequencer_|DFFE_T3_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|sequencer_|DFFE_T4_ff~q ; +wire \z80_|execute_|ctl_mWrite~9_combout ; +wire \z80_|execute_|ctl_flags_sz_we~0_combout ; +wire \z80_|execute_|setM1~54_combout ; +wire \z80_|execute_|setM1~25_combout ; +wire \z80_|execute_|setM1~26_combout ; +wire \z80_|execute_|setM1~27_combout ; +wire \z80_|execute_|setM1~22_combout ; +wire \z80_|execute_|setM1~55_combout ; +wire \z80_|execute_|setM1~23_combout ; +wire \z80_|execute_|setM1~24_combout ; +wire \z80_|execute_|setM1~28_combout ; +wire \z80_|execute_|setM1~11_combout ; +wire \z80_|execute_|setM1~33_combout ; +wire \z80_|execute_|setM1~29_combout ; +wire \z80_|execute_|setM1~31_combout ; +wire \z80_|execute_|setM1~32_combout ; +wire \z80_|execute_|setM1~34_combout ; +wire \z80_|execute_|setM1~20_combout ; +wire \z80_|execute_|setM1~21_combout ; +wire \z80_|execute_|setM1~35_combout ; +wire \z80_|execute_|setM1~15_combout ; +wire \z80_|execute_|setM1~14_combout ; +wire \z80_|execute_|setM1~16_combout ; +wire \z80_|execute_|setM1~10_combout ; +wire \z80_|execute_|setM1~12_combout ; +wire \z80_|execute_|setM1~8_combout ; +wire \z80_|execute_|setM1~9_combout ; +wire \z80_|execute_|setM1~13_combout ; +wire \z80_|execute_|setM1~18_combout ; +wire \z80_|execute_|setM1~19_combout ; +wire \z80_|execute_|setM1~43_combout ; +wire \z80_|execute_|setM1~42_combout ; +wire \z80_|execute_|setM1~44_combout ; +wire \z80_|execute_|setM1~45_combout ; +wire \z80_|execute_|setM1~51_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; +wire \z80_|sequencer_|T6~q ; +wire \z80_|execute_|setM1~52_combout ; +wire \z80_|execute_|setM1~53_combout ; +wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M1_ff~q ; +wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~q ; +wire \z80_|execute_|ctl_apin_mux~1_combout ; wire \z80_|execute_|ctl_apin_mux~2_combout ; wire \z80_|address_pins_|DFFE_apin_latch[0]~0_combout ; -wire \D[0]~59_combout ; -wire \D[0]~60_combout ; -wire \D[1]~61_combout ; -wire \D[1]~62_combout ; -wire \D[2]~63_combout ; -wire \D[2]~64_combout ; -wire \D[3]~75_combout ; -wire \D[3]~76_combout ; -wire \D[4]~82_combout ; -wire \D[4]~83_combout ; -wire \D[6]~92_combout ; -wire \D[6]~93_combout ; +wire \D[0]~66_combout ; +wire \D[0]~67_combout ; +wire \D[0]~121_combout ; +wire \D[1]~68_combout ; +wire \D[1]~69_combout ; +wire \D[2]~70_combout ; +wire \D[2]~71_combout ; +wire \D[3]~83_combout ; +wire \D[3]~84_combout ; +wire \D[4]~95_combout ; +wire \D[4]~96_combout ; +wire \D[5]~126_combout ; +wire \D[5]~98_combout ; +wire \D[6]~105_combout ; +wire \D[6]~106_combout ; +wire \D[7]~128_combout ; +wire \D[7]~107_combout ; +wire \z80_|memory_ifc_|nIORQ_out~0_combout ; wire \z80_|nM1_int~3_combout ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ; @@ -2482,26 +2541,43 @@ wire \z80_|memory_ifc_|DFFE_mreq_ff2~q ; wire \z80_|memory_ifc_|nMREQ_out~0_combout ; wire \z80_|memory_ifc_|nMREQ_out~1_combout ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ; -wire \ula_|i2c_loader_|state.Idle~feeder_combout ; wire \ula_|i2c_loader_|divider[0]~15_combout ; wire \ula_|i2c_loader_|divider[1]~5_combout ; wire \ula_|i2c_loader_|divider[1]~6 ; wire \ula_|i2c_loader_|divider[2]~7_combout ; wire \ula_|i2c_loader_|divider[2]~8 ; wire \ula_|i2c_loader_|divider[3]~9_combout ; +wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|divider[3]~10 ; wire \ula_|i2c_loader_|divider[4]~11_combout ; wire \ula_|i2c_loader_|divider[4]~12 ; wire \ula_|i2c_loader_|divider[5]~13_combout ; -wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|WideAnd0~combout ; +wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; +wire \ula_|i2c_loader_|state.Idle~feeder_combout ; wire \ula_|i2c_loader_|state.Idle~q ; wire \ula_|i2c_loader_|phase~0_combout ; wire \ula_|i2c_loader_|phase~1_combout ; -wire \ula_|i2c_loader_|nbit~5_combout ; -wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; wire \ula_|i2c_loader_|Mux42~0_combout ; +wire \ula_|i2c_loader_|nbyte~0_combout ; +wire \ula_|i2c_loader_|nbit~4_combout ; wire \ula_|i2c_loader_|nbyte~4_combout ; +wire \ula_|i2c_loader_|nbit[0]~1_combout ; +wire \ula_|i2c_loader_|nbit[0]~2_combout ; +wire \ula_|i2c_loader_|nbit[0]~3_combout ; +wire \ula_|i2c_loader_|nbit~5_combout ; +wire \ula_|i2c_loader_|state.Pause~1_combout ; +wire \ula_|i2c_loader_|state~27_combout ; +wire \ula_|i2c_loader_|state~24_combout ; +wire \ula_|i2c_loader_|state~26_combout ; +wire \ula_|i2c_loader_|state.Data~0_combout ; +wire \ula_|i2c_loader_|state.Data~q ; +wire \ula_|i2c_loader_|nbit~0_combout ; +wire \ula_|i2c_loader_|state.Pause~0_combout ; +wire \ula_|i2c_loader_|state.Idle~0_combout ; +wire \ula_|i2c_loader_|state.Ack~0_combout ; +wire \ula_|i2c_loader_|state.Ack~1_combout ; +wire \ula_|i2c_loader_|state.Ack~q ; wire \ula_|i2c_loader_|thisbyte[0]~7_combout ; wire \I2C_SDAT~input_o ; wire \ula_|i2c_loader_|nbyte[0]~1_combout ; @@ -2510,12 +2586,8 @@ wire \ula_|i2c_loader_|nbyte[0]~3_combout ; wire \ula_|i2c_loader_|state.Stop~0_combout ; wire \ula_|i2c_loader_|state.Stop~1_combout ; wire \ula_|i2c_loader_|state.Stop~q ; -wire \ula_|i2c_loader_|state.Idle~0_combout ; -wire \ula_|i2c_loader_|nbit~0_combout ; -wire \ula_|i2c_loader_|state.Done~0_combout ; -wire \ula_|i2c_loader_|state.Ack~0_combout ; -wire \ula_|i2c_loader_|state.Ack~1_combout ; -wire \ula_|i2c_loader_|state.Ack~q ; +wire \ula_|i2c_loader_|state.Pause~2_combout ; +wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; wire \ula_|i2c_loader_|nbyte[1]~5_combout ; wire \ula_|i2c_loader_|thisbyte[0]~18_combout ; wire \ula_|i2c_loader_|thisbyte[0]~9 ; @@ -2525,56 +2597,43 @@ wire \ula_|i2c_loader_|thisbyte[2]~12_combout ; wire \ula_|i2c_loader_|thisbyte[2]~13 ; wire \ula_|i2c_loader_|thisbyte[3]~14_combout ; wire \ula_|i2c_loader_|Equal2~0_combout ; -wire \ula_|i2c_loader_|state.Pause~0_combout ; wire \ula_|i2c_loader_|thisbyte[3]~15 ; wire \ula_|i2c_loader_|thisbyte[4]~16_combout ; -wire \ula_|i2c_loader_|state.Pause~1_combout ; -wire \ula_|i2c_loader_|state.Done~2_combout ; -wire \ula_|i2c_loader_|state.Pause~2_combout ; wire \ula_|i2c_loader_|state.Pause~3_combout ; +wire \ula_|i2c_loader_|scl_out~0_combout ; +wire \ula_|i2c_loader_|state.Pause~4_combout ; +wire \ula_|i2c_loader_|state.Pause~5_combout ; +wire \ula_|i2c_loader_|state.Pause~6_combout ; wire \ula_|i2c_loader_|state.Pause~q ; wire \ula_|i2c_loader_|state~25_combout ; wire \ula_|i2c_loader_|state.Start~q ; -wire \ula_|i2c_loader_|nbyte~0_combout ; -wire \ula_|i2c_loader_|nbit[0]~1_combout ; -wire \ula_|i2c_loader_|nbit[0]~2_combout ; -wire \ula_|i2c_loader_|nbit[0]~3_combout ; -wire \ula_|i2c_loader_|nbit[0]~4_combout ; -wire \ula_|i2c_loader_|nbit~6_combout ; -wire \ula_|i2c_loader_|state.Done~1_combout ; -wire \ula_|i2c_loader_|state~27_combout ; -wire \ula_|i2c_loader_|state~24_combout ; -wire \ula_|i2c_loader_|state~26_combout ; -wire \ula_|i2c_loader_|state.Data~0_combout ; -wire \ula_|i2c_loader_|state.Data~q ; -wire \ula_|i2c_loader_|scl_out~0_combout ; -wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; wire \ula_|i2c_loader_|scl_out~1_combout ; wire \ula_|i2c_loader_|scl_out~2_combout ; wire \ula_|i2c_loader_|scl_out~q ; wire \ula_|i2c_loader_|sda_out~_Duplicate_1_q ; -wire \ula_|i2c_loader_|shiftreg~4_combout ; wire \ula_|i2c_loader_|Mux35~0_combout ; -wire \ula_|i2c_loader_|shiftreg~13_combout ; -wire \ula_|i2c_loader_|shiftreg~14_combout ; -wire \ula_|i2c_loader_|shiftreg~15_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~24_combout ; +wire \ula_|i2c_loader_|shiftreg~4_combout ; +wire \ula_|i2c_loader_|shiftreg~19_combout ; +wire \ula_|i2c_loader_|shiftreg~20_combout ; +wire \ula_|i2c_loader_|shiftreg~22_combout ; +wire \ula_|i2c_loader_|shiftreg~23_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~25_combout ; wire \ula_|i2c_loader_|shiftreg[0]~6_combout ; wire \ula_|i2c_loader_|shiftreg[0]~7_combout ; wire \ula_|i2c_loader_|shiftreg[0]~8_combout ; -wire \ula_|i2c_loader_|shiftreg~21_combout ; -wire \ula_|i2c_loader_|shiftreg~22_combout ; -wire \ula_|i2c_loader_|shiftreg~23_combout ; +wire \ula_|i2c_loader_|shiftreg~24_combout ; wire \ula_|i2c_loader_|shiftreg[6]~10_combout ; wire \ula_|i2c_loader_|shiftreg[6]~11_combout ; -wire \ula_|i2c_loader_|shiftreg~18_combout ; -wire \ula_|i2c_loader_|shiftreg~19_combout ; -wire \ula_|i2c_loader_|shiftreg~20_combout ; -wire \ula_|i2c_loader_|shiftreg~16_combout ; +wire \ula_|i2c_loader_|shiftreg[6]~12_combout ; +wire \ula_|i2c_loader_|shiftreg~21_combout ; wire \ula_|i2c_loader_|shiftreg~17_combout ; +wire \ula_|i2c_loader_|shiftreg~15_combout ; +wire \ula_|i2c_loader_|shiftreg~18_combout ; +wire \ula_|i2c_loader_|shiftreg~27_combout ; +wire \ula_|i2c_loader_|shiftreg~14_combout ; +wire \ula_|i2c_loader_|shiftreg~16_combout ; wire \ula_|i2c_loader_|shiftreg~26_combout ; -wire \ula_|i2c_loader_|shiftreg~25_combout ; -wire \ula_|i2c_loader_|shiftreg~12_combout ; +wire \ula_|i2c_loader_|shiftreg~13_combout ; wire \ula_|i2c_loader_|shiftreg~9_combout ; wire \ula_|i2c_loader_|shiftreg[7]~5_combout ; wire \ula_|i2c_loader_|sda_out~0_combout ; @@ -2583,6 +2642,142 @@ wire \ula_|i2c_loader_|sda_out~2_combout ; wire \ula_|i2c_loader_|sda_out~3_combout ; wire \ula_|i2c_loader_|sda_out~4_combout ; wire \ula_|i2c_loader_|sda_out~q ; +wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_fbout ; +wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \sdram_|Mux38~0_combout ; +wire \sdram_|r.rd_pending~q ; +wire \sdram_|r.rf_counter[0]~12_combout ; +wire \sdram_|r.rf_counter[3]~32_combout ; +wire \sdram_|r.rf_counter[0]~13 ; +wire \sdram_|r.rf_counter[1]~14_combout ; +wire \sdram_|r.rf_counter[1]~15 ; +wire \sdram_|r.rf_counter[2]~16_combout ; +wire \sdram_|r.rf_counter[2]~17 ; +wire \sdram_|r.rf_counter[3]~18_combout ; +wire \sdram_|r.rf_counter[3]~19 ; +wire \sdram_|r.rf_counter[4]~20_combout ; +wire \sdram_|r.rf_counter[4]~21 ; +wire \sdram_|r.rf_counter[5]~22_combout ; +wire \sdram_|r.rf_counter[5]~23 ; +wire \sdram_|r.rf_counter[6]~24_combout ; +wire \sdram_|r.rf_counter[6]~25 ; +wire \sdram_|r.rf_counter[7]~26_combout ; +wire \sdram_|Equal0~1_combout ; +wire \sdram_|r.rf_counter[7]~27 ; +wire \sdram_|r.rf_counter[8]~28_combout ; +wire \sdram_|Equal0~0_combout ; +wire \sdram_|r.rf_counter[8]~29 ; +wire \sdram_|r.rf_counter[9]~30_combout ; +wire \sdram_|Equal0~2_combout ; +wire \sdram_|Mux13~8_combout ; +wire \sdram_|Mux37~0_combout ; +wire \sdram_|r.rf_pending~q ; +wire \sdram_|Mux4~0_combout ; +wire \sdram_|Mux4~1_combout ; +wire \sdram_|Mux4~2_combout ; +wire \sdram_|Mux4~3_combout ; +wire \sdram_|r.act_row[1]~0_combout ; +wire \sdram_|process_0~2_combout ; +wire \sdram_|r.act_row[1]~1_combout ; +wire \sdram_|r.act_row[2]~feeder_combout ; +wire \sdram_|Equal7~1_combout ; +wire \sdram_|Equal7~0_combout ; +wire \sdram_|Equal7~2_combout ; +wire \sdram_|Mux39~0_combout ; +wire \sdram_|Mux39~1_combout ; +wire \sdram_|Mux39~2_combout ; +wire \sdram_|r.wr_pending~q ; +wire \sdram_|Mux9~8_combout ; +wire \sdram_|Mux9~9_combout ; +wire \sdram_|Mux6~3_combout ; +wire \sdram_|Mux6~4_combout ; +wire \sdram_|Mux6~2_combout ; +wire \sdram_|Mux6~5_combout ; +wire \sdram_|process_0~3_combout ; +wire \sdram_|Mux6~0_combout ; +wire \sdram_|Mux6~1_combout ; +wire \sdram_|Mux6~6_combout ; +wire \sdram_|r.address[3]~6_combout ; +wire \sdram_|Mux7~2_combout ; +wire \sdram_|n~3_combout ; +wire \sdram_|Mux7~3_combout ; +wire \sdram_|Mux7~4_combout ; +wire \sdram_|Mux7~5_combout ; +wire \sdram_|Mux23~0_combout ; +wire \sdram_|Mux13~7_combout ; +wire \sdram_|Mux10~10_combout ; +wire \sdram_|Mux7~1_combout ; +wire \sdram_|Mux7~6_combout ; +wire \sdram_|Mux5~2_combout ; +wire \sdram_|Mux5~10_combout ; +wire \sdram_|Mux5~3_combout ; +wire \sdram_|Mux5~4_combout ; +wire \sdram_|Mux5~7_combout ; +wire \sdram_|Mux5~8_combout ; +wire \sdram_|Mux5~5_combout ; +wire \sdram_|Mux5~6_combout ; +wire \sdram_|Mux5~9_combout ; +wire \sdram_|n~2_combout ; +wire \sdram_|Mux8~3_combout ; +wire \sdram_|Mux8~4_combout ; +wire \sdram_|Mux9~10_combout ; +wire \sdram_|r.init_counter[0]~0_combout ; +wire \sdram_|Add1~1_cout ; +wire \sdram_|Add1~2_combout ; +wire \sdram_|Add1~3 ; +wire \sdram_|Add1~4_combout ; +wire \sdram_|Add1~5 ; +wire \sdram_|Add1~6_combout ; +wire \sdram_|r.init_counter[3]~1_combout ; +wire \sdram_|Add1~7 ; +wire \sdram_|Add1~8_combout ; +wire \sdram_|Add1~9 ; +wire \sdram_|Add1~10_combout ; +wire \sdram_|Add1~11 ; +wire \sdram_|Add1~12_combout ; +wire \sdram_|Add1~13 ; +wire \sdram_|Add1~14_combout ; +wire \sdram_|Add1~15 ; +wire \sdram_|Add1~16_combout ; +wire \sdram_|Add1~17 ; +wire \sdram_|Add1~18_combout ; +wire \sdram_|Add1~19 ; +wire \sdram_|Add1~20_combout ; +wire \sdram_|Equal2~0_combout ; +wire \sdram_|Equal2~1_combout ; +wire \sdram_|Add1~21 ; +wire \sdram_|Add1~22_combout ; +wire \sdram_|Add1~23 ; +wire \sdram_|Add1~24_combout ; +wire \sdram_|Add1~25 ; +wire \sdram_|Add1~26_combout ; +wire \sdram_|Add1~27 ; +wire \sdram_|Add1~28_combout ; +wire \sdram_|process_0~5_combout ; +wire \sdram_|Equal2~2_combout ; +wire \sdram_|Mux9~11_combout ; +wire \sdram_|Mux9~12_combout ; +wire \sdram_|Mux9~13_combout ; +wire \sdram_|Mux8~0_combout ; +wire \sdram_|Mux8~1_combout ; +wire \sdram_|Mux8~2_combout ; +wire \sdram_|Mux72~0_combout ; +wire \sdram_|Mux72~1_combout ; +wire \sdram_|Mux84~0_combout ; +wire \sdram_|Mux84~1_combout ; +wire \sdram_|Mux3~0_combout ; +wire \sdram_|Mux3~1_combout ; +wire \sdram_|Mux2~0_combout ; +wire \sdram_|Mux2~1_combout ; +wire \sdram_|Mux1~0_combout ; +wire \sdram_|Mux1~1_combout ; +wire \sdram_|Mux0~0_combout ; +wire \sdram_|Mux0~1_combout ; +wire \sdram_|Mux73~0_combout ; +wire \sdram_|Mux73~1_combout ; +wire \sdram_|Mux74~0_combout ; +wire \sdram_|Mux74~1_combout ; +wire \sdram_|Mux75~0_combout ; wire \ula_|i2s_intf_|mclk_r~0_combout ; wire \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|mclk_r~q ; @@ -2616,12 +2811,13 @@ wire \ula_|i2s_intf_|Add0~18_combout ; wire \ula_|i2s_intf_|lrdivider[9]~3_combout ; wire \ula_|i2s_intf_|Equal0~0_combout ; wire \ula_|i2s_intf_|Equal0~2_combout ; -wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; wire \ula_|i2s_intf_|lrclk_r~0_combout ; wire \ula_|i2s_intf_|lrclk_r~q ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_1_q ; +wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|bitcount[0]~5_combout ; +wire \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ; wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|bitcount[4]~15_combout ; wire \ula_|i2s_intf_|bitcount[0]~6 ; @@ -2630,9 +2826,10 @@ wire \ula_|i2s_intf_|bitcount[1]~8 ; wire \ula_|i2s_intf_|bitcount[2]~9_combout ; wire \ula_|i2s_intf_|bitcount[2]~10 ; wire \ula_|i2s_intf_|bitcount[3]~11_combout ; -wire \ula_|i2s_intf_|LessThan0~0_combout ; wire \ula_|i2s_intf_|bitcount[3]~12 ; wire \ula_|i2s_intf_|bitcount[4]~13_combout ; +wire \ula_|i2s_intf_|LessThan0~0_combout ; +wire \ula_|i2s_intf_|shiftreg[1]~1_combout ; wire \ula_|i2s_intf_|Add2~7_cout ; wire \ula_|i2s_intf_|Add2~8_combout ; wire \ula_|i2s_intf_|Add2~20_combout ; @@ -2646,8 +2843,6 @@ wire \ula_|i2s_intf_|Add2~13 ; wire \ula_|i2s_intf_|Add2~14_combout ; wire \ula_|i2s_intf_|Add2~16_combout ; wire \ula_|i2s_intf_|Equal1~0_combout ; -wire \ula_|i2s_intf_|shiftreg[4]~1_combout ; -wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|Equal1~1_combout ; wire \ula_|i2s_intf_|bclk_r~0_combout ; wire \ula_|i2s_intf_|bclk_r~1_combout ; @@ -2659,7 +2854,7 @@ wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; wire \AUD_ADCDAT~input_o ; wire \ula_|i2s_intf_|shiftreg[0]~20_combout ; wire \ula_|i2s_intf_|shiftreg~18_combout ; -wire \ula_|i2s_intf_|shiftreg[4]~2_combout ; +wire \ula_|i2s_intf_|shiftreg[1]~2_combout ; wire \ula_|i2s_intf_|shiftreg~17_combout ; wire \ula_|i2s_intf_|shiftreg~16_combout ; wire \ula_|i2s_intf_|shiftreg~15_combout ; @@ -2676,28 +2871,20 @@ wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; wire \ula_|pcm_outr~0_combout ; wire \ula_|i2s_intf_|shiftreg~6_combout ; wire \ula_|i2s_intf_|shiftreg~5_combout ; +wire \ula_|pcm_outl[14]~feeder_combout ; wire \ula_|i2s_intf_|shiftreg~4_combout ; wire \ula_|i2s_intf_|shiftreg~3_combout ; wire \ula_|i2s_intf_|shiftreg~0_combout ; -wire \ula_|video_|LessThan2~0_combout ; +wire \ula_|border[1]~feeder_combout ; wire \ula_|video_|LessThan6~0_combout ; -wire \ula_|video_|LessThan2~1_combout ; -wire \ula_|video_|LessThan3~0_combout ; -wire \ula_|video_|LessThan0~0_combout ; -wire \ula_|video_|disp_enable~0_combout ; -wire \ula_|video_|disp_enable~1_combout ; wire \ula_|video_|LessThan6~1_combout ; wire \ula_|video_|LessThan4~0_combout ; wire \ula_|video_|screen_en~0_combout ; wire \ula_|video_|screen_en~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; -wire \ula_|video_|attr_prefetch[1]~feeder_combout ; -wire \ula_|video_|Decoder0~1_combout ; -wire \ula_|video_|Decoder0~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; -wire \ula_|video_|attr_prefetch[4]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; wire \ula_|video_|attr_prefetch[7]~feeder_combout ; +wire \ula_|video_|Decoder0~1_combout ; +wire \ula_|video_|Decoder0~0_combout ; wire \ula_|video_|frame[0]~12_combout ; wire \ula_|video_|frame[1]~4_combout ; wire \ula_|video_|frame[1]~5 ; @@ -2710,7 +2897,7 @@ wire \ula_|video_|inverted~combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[6]~feeder_combout ; wire \ula_|video_|Decoder0~2_combout ; -wire \ula_|video_|bits[6]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[4]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[5]~feeder_combout ; @@ -2723,25 +2910,35 @@ wire \ula_|video_|bits_prefetch[2]~feeder_combout ; wire \ula_|video_|bits[2]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[0]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[1]~feeder_combout ; wire \ula_|video_|bits[1]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[3]~feeder_combout ; wire \ula_|video_|Mux0~2_combout ; wire \ula_|video_|Mux0~3_combout ; -wire \ula_|video_|cindex[1]~0_combout ; +wire \ula_|video_|cindex[2]~0_combout ; +wire \ula_|video_|attr_prefetch[4]~feeder_combout ; +wire \ula_|video_|attr_prefetch[1]~feeder_combout ; wire \ula_|video_|cindex[1]~1_combout ; +wire \ula_|video_|LessThan2~0_combout ; +wire \ula_|video_|LessThan2~1_combout ; +wire \ula_|video_|LessThan3~0_combout ; +wire \ula_|video_|LessThan0~0_combout ; +wire \ula_|video_|disp_enable~0_combout ; +wire \ula_|video_|disp_enable~1_combout ; wire \ula_|video_|VGA_R[0]~0_combout ; wire \ula_|video_|attr_prefetch[6]~feeder_combout ; wire \ula_|video_|VGA_B[1]~0_combout ; wire \ula_|video_|VGA_R[1]~1_combout ; -wire \ula_|video_|attr_prefetch[2]~feeder_combout ; +wire \ula_|border[2]~feeder_combout ; wire \ula_|video_|attr_prefetch[5]~feeder_combout ; +wire \ula_|video_|attr_prefetch[2]~feeder_combout ; wire \ula_|video_|cindex[2]~2_combout ; wire \ula_|video_|VGA_G[0]~0_combout ; wire \ula_|video_|VGA_G[1]~1_combout ; +wire \ula_|border[0]~feeder_combout ; wire \ula_|video_|attr_prefetch[0]~feeder_combout ; -wire \ula_|video_|attr[0]~feeder_combout ; wire \ula_|video_|attr_prefetch[3]~feeder_combout ; wire \ula_|video_|cindex[0]~3_combout ; wire \ula_|video_|VGA_B[0]~1_combout ; @@ -2760,23 +2957,171 @@ wire \z80_|memory_ifc_|nRFSH_out~0_combout ; wire \z80_|memory_ifc_|nM1_out~combout ; wire \ula_|beep~0_combout ; wire \ula_|beep~q ; -wire [0:0] \ram0|altsyncram_component|auto_generated|address_reg_a ; +wire \sdram_|Mux26~4_combout ; +wire \sdram_|r.bank[0]~7_combout ; +wire \sdram_|r.bank[0]~11_combout ; +wire \sdram_|r.bank[0]~4_combout ; +wire \sdram_|r.bank[0]~5_combout ; +wire \sdram_|r.bank[0]~6_combout ; +wire \sdram_|r.bank[0]~8_combout ; +wire \sdram_|r.bank[0]~12_combout ; +wire \sdram_|r.bank[0]~9_combout ; +wire \sdram_|Mux25~4_combout ; +wire \sdram_|Mux24~5_combout ; +wire \sdram_|Mux71~0_combout ; +wire \sdram_|process_0~7_combout ; +wire \sdram_|process_0~4_combout ; +wire \sdram_|Mux71~1_combout ; +wire \sdram_|Mux71~2_combout ; +wire \sdram_|Mux71~3_combout ; +wire \sdram_|Mux71~4_combout ; +wire \sdram_|r.bank[0]~10_combout ; +wire \sdram_|Mux9~3_combout ; +wire \sdram_|n~5_combout ; +wire \sdram_|Mux9~4_combout ; +wire \sdram_|Mux9~2_combout ; +wire \sdram_|Equal2~3_combout ; +wire \sdram_|Mux10~2_combout ; +wire \sdram_|Mux10~3_combout ; +wire \sdram_|process_0~6_combout ; +wire \sdram_|Mux10~4_combout ; +wire \sdram_|Mux9~5_combout ; +wire \sdram_|Mux7~0_combout ; +wire \sdram_|Mux9~6_combout ; +wire \sdram_|Mux9~7_combout ; +wire \sdram_|Mux10~11_combout ; +wire \sdram_|Mux10~6_combout ; +wire \sdram_|Mux10~5_combout ; +wire \sdram_|Mux10~7_combout ; +wire \sdram_|Mux10~8_combout ; +wire \sdram_|Mux10~9_combout ; +wire \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK_outclk ; +wire \sdram_|Mux11~2_combout ; +wire \sdram_|Mux11~3_combout ; +wire \sdram_|Mux11~4_combout ; +wire \sdram_|Mux11~5_combout ; +wire \sdram_|Mux11~6_combout ; +wire \sdram_|Mux11~7_combout ; +wire \sdram_|Mux11~9_combout ; +wire \sdram_|Mux11~8_combout ; +wire \sdram_|Mux24~2_combout ; +wire \sdram_|r.address[0]~7_combout ; +wire \sdram_|r.address[0]~0_combout ; +wire \sdram_|Mux13~9_combout ; +wire \sdram_|Mux13~4_combout ; +wire \sdram_|Mux13~5_combout ; +wire \sdram_|r.address[0]~_Duplicate_1_q ; +wire \sdram_|Mux24~3_combout ; +wire \sdram_|Mux24~4_combout ; +wire \sdram_|r.address[0]~SLOAD_MUX_combout ; +wire \sdram_|r.address[1]~_Duplicate_1feeder_combout ; +wire \sdram_|Mux23~4_combout ; +wire \sdram_|Equal5~0_combout ; +wire \sdram_|Mux23~5_combout ; +wire \sdram_|Mux23~6_combout ; +wire \sdram_|Mux19~0_combout ; +wire \sdram_|r.address[1]~_Duplicate_1_q ; +wire \sdram_|Mux23~2_combout ; +wire \sdram_|Mux23~3_combout ; +wire \sdram_|Mux23~1_combout ; +wire \sdram_|r.address[1]~1_combout ; +wire \sdram_|r.address[1]~SLOAD_MUX_combout ; +wire \sdram_|r.address[3]~8_combout ; +wire \sdram_|r.address[3]~9_combout ; +wire \sdram_|Mux21~0_combout ; +wire \sdram_|Mux22~0_combout ; +wire \sdram_|r.address[3]~10_combout ; +wire \sdram_|r.address[3]~11_combout ; +wire \sdram_|r.address[3]~12_combout ; +wire \sdram_|r.address[3]~13_combout ; +wire \sdram_|r.address[3]~14_combout ; +wire \sdram_|r.address[3]~15_combout ; +wire \sdram_|r.address[3]~16_combout ; +wire \sdram_|r.address[3]~17_combout ; +wire \sdram_|Mux21~1_combout ; +wire \sdram_|Mux20~4_combout ; +wire \sdram_|Mux20~7_combout ; +wire \sdram_|Mux23~7_combout ; +wire \sdram_|Mux20~8_combout ; +wire \sdram_|Mux20~10_combout ; +wire \sdram_|Mux20~9_combout ; +wire \sdram_|Mux20~11_combout ; +wire \sdram_|r.address[4]~_Duplicate_1_q ; +wire \sdram_|Mux20~12_combout ; +wire \sdram_|Mux20~5_combout ; +wire \sdram_|Mux20~6_combout ; +wire \sdram_|r.address[4]~2_combout ; +wire \sdram_|r.address[4]~SLOAD_MUX_combout ; +wire \sdram_|Mux19~1_combout ; +wire \sdram_|Mux19~4_combout ; +wire \sdram_|Mux19~5_combout ; +wire \sdram_|Mux19~6_combout ; +wire \sdram_|Mux19~7_combout ; +wire \sdram_|r.address[5]~_Duplicate_1_q ; +wire \sdram_|Mux19~2_combout ; +wire \sdram_|Mux19~3_combout ; +wire \sdram_|r.address[5]~3_combout ; +wire \sdram_|r.address[5]~SLOAD_MUX_combout ; +wire \sdram_|Mux18~0_combout ; +wire \sdram_|Mux17~0_combout ; +wire \sdram_|Mux16~0_combout ; +wire \sdram_|Mux15~2_combout ; +wire \sdram_|Mux14~0_combout ; +wire \sdram_|Mux14~1_combout ; +wire \sdram_|r.address[10]~4_combout ; +wire \sdram_|r.address[10]~_Duplicate_1_q ; +wire \sdram_|n~4_combout ; +wire \sdram_|Mux14~2_combout ; +wire \sdram_|Mux14~3_combout ; +wire \sdram_|r.address[10]~SLOAD_MUX_combout ; +wire \sdram_|r.address[11]~18_combout ; +wire \sdram_|r.address[11]~5_combout ; +wire \sdram_|r.address[11]~_Duplicate_2feeder_combout ; +wire \sdram_|r.address[11]~_Duplicate_2_q ; +wire \sdram_|Mux13~10_combout ; +wire \sdram_|Mux13~6_combout ; +wire \sdram_|r.address[11]~SLOAD_MUX_combout ; +wire \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout ; +wire \sdram_|r.address[11]~_Duplicate_1_q ; +wire [9:0] \sdram_|r.rf_counter ; +wire [12:0] \sdram_|r.address ; +wire [15:0] \ula_|pcm_outl ; +wire [1:0] \ula_|i2c_loader_|nbyte ; +wire [4:0] \ula_|i2s_intf_|bitcount ; +wire [4:0] \ula_|video_|frame ; +wire [7:0] \ula_|video_|attr_prefetch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_ix_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_pc_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_wz_hi|latch ; wire [1:0] \ram1|altsyncram_component|auto_generated|address_reg_a ; -wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode244w ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode223w ; +wire [3:0] \z80_|alu_|op2_low ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; +wire [15:0] \z80_|address_latch_|abusz ; +wire [7:0] \z80_|data_pins_|dout ; +wire [8:0] \sdram_|r.state ; +wire [14:0] \sdram_|r.init_counter ; +wire [1:0] \sdram_|r.bank ; +wire [12:0] \sdram_|r.act_row ; wire [2:0] \ula_|border ; wire [0:0] \ula_|clocks_|counter ; -wire [7:0] \ula_|i2c_loader_|shiftreg ; -wire [1:0] \ula_|i2c_loader_|nbyte ; -wire [5:0] \ula_|i2c_loader_|divider ; -wire [17:0] \ula_|i2s_intf_|shiftreg ; -wire [4:0] \ula_|i2s_intf_|bitcount ; -wire [15:0] \ula_|i2s_intf_|PCM_INR ; -wire [9:0] \ula_|video_|vga_vc ; -wire [4:0] \ula_|video_|frame ; -wire [7:0] \ula_|video_|bits_prefetch ; -wire [7:0] \ula_|video_|attr_prefetch ; -wire [7:0] \ula_|ps2_keyboard_|clk_filter ; +wire [4:0] \ula_|i2c_loader_|thisbyte ; +wire [1:0] \ula_|i2c_loader_|phase ; +wire [2:0] \ula_|i2c_loader_|nbit ; +wire [9:0] \ula_|i2s_intf_|lrdivider ; +wire [4:0] \ula_|i2s_intf_|bdivider ; +wire [15:0] \ula_|i2s_intf_|PCM_INL ; +wire [12:0] \ula_|video_|vram_address ; +wire [9:0] \ula_|video_|vga_hc ; +wire [7:0] \ula_|video_|bits ; +wire [7:0] \ula_|video_|attr ; +wire [8:0] \ula_|ps2_keyboard_|shiftreg ; +wire [3:0] \ula_|ps2_keyboard_|bit_count ; wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; @@ -2790,126 +3135,119 @@ wire [7:0] \z80_|reg_file_|b2v_latch_iy_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_pc_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_sp_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; -wire [3:0] \z80_|alu_|op2_low ; -wire [3:0] \z80_|alu_|op1_low ; -wire [15:0] \z80_|address_latch_|Q ; -wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; -wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; -wire [7:0] \z80_|data_pins_|dout ; -wire [7:0] \z80_|ir_|opcode ; wire [0:0] \ram0|altsyncram_component|auto_generated|out_address_reg_a ; wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode252w ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode236w ; -wire [15:0] \ula_|pcm_outl ; -wire [4:0] \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk ; -wire [4:0] \ula_|i2c_loader_|thisbyte ; -wire [1:0] \ula_|i2c_loader_|phase ; -wire [2:0] \ula_|i2c_loader_|nbit ; -wire [9:0] \ula_|i2s_intf_|lrdivider ; -wire [4:0] \ula_|i2s_intf_|bdivider ; -wire [15:0] \ula_|i2s_intf_|PCM_INL ; -wire [12:0] \ula_|video_|vram_address ; -wire [9:0] \ula_|video_|vga_hc ; -wire [7:0] \ula_|video_|bits ; -wire [7:0] \ula_|video_|attr ; -wire [8:0] \ula_|ps2_keyboard_|shiftreg ; -wire [3:0] \ula_|ps2_keyboard_|bit_count ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_ix_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_iy_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_pc_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_sp_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_wz_hi|latch ; wire [3:0] \z80_|alu_|result_lo ; wire [3:0] \z80_|alu_|op2_high ; wire [3:0] \z80_|alu_|op1_high ; wire [3:0] \z80_|alu_|b2v_op1_latch_mux_high|Q ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; -wire [15:0] \z80_|address_latch_|abusz ; +wire [15:0] \z80_|address_latch_|Q ; +wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; +wire [7:0] \z80_|ir_|opcode ; +wire [1:0] \sdram_|r.dq_masks ; +wire [4:0] \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk ; +wire [4:0] \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk ; +wire [7:0] \ula_|i2c_loader_|shiftreg ; +wire [5:0] \ula_|i2c_loader_|divider ; +wire [17:0] \ula_|i2s_intf_|shiftreg ; +wire [15:0] \ula_|i2s_intf_|PCM_INR ; +wire [9:0] \ula_|video_|vga_vc ; +wire [7:0] \ula_|video_|bits_prefetch ; +wire [7:0] \ula_|ps2_keyboard_|clk_filter ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_iy_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_sp_hi|latch ; +wire [0:0] \ram0|altsyncram_component|auto_generated|address_reg_a ; +wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode244w ; +wire [3:0] \z80_|alu_|op1_low ; +wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; +wire [4:0] \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus ; wire [4:0] \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; + +assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [0] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [1] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [2] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [3] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [4] = \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus [4]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [0] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [0]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [1] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [1]; @@ -2917,24 +3255,24 @@ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [2] = \ula_|pll_ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [3] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [3]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [4] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [4]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; - assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0]; @@ -2947,12 +3285,12 @@ assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; @@ -2965,55 +3303,47 @@ assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \r assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; @@ -3025,6 +3355,14 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0]; @@ -3037,19 +3375,11 @@ assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; @@ -3061,6 +3391,14 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; + // Location: IOOBUF_X53_Y21_N23 cycloneive_io_obuf \GPIO_1[0]~output ( .i(\z80_|address_pins_|DFFE_apin_latch [0]), @@ -3271,8 +3609,8 @@ defparam \GPIO_1[15]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N9 cycloneive_io_obuf \GPIO_1[16]~output ( - .i(\D[0]~60_combout ), - .oe(\D[0]~107_combout ), + .i(\D[0]~67_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[16]), @@ -3284,8 +3622,8 @@ defparam \GPIO_1[16]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y12_N2 cycloneive_io_obuf \GPIO_1[17]~output ( - .i(\D[1]~62_combout ), - .oe(\D[0]~107_combout ), + .i(\D[1]~69_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[17]), @@ -3297,8 +3635,8 @@ defparam \GPIO_1[17]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y8_N23 cycloneive_io_obuf \GPIO_1[18]~output ( - .i(\D[2]~64_combout ), - .oe(\D[0]~107_combout ), + .i(\D[2]~71_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[18]), @@ -3310,8 +3648,8 @@ defparam \GPIO_1[18]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N2 cycloneive_io_obuf \GPIO_1[19]~output ( - .i(\D[3]~76_combout ), - .oe(\D[0]~107_combout ), + .i(\D[3]~84_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[19]), @@ -3323,8 +3661,8 @@ defparam \GPIO_1[19]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y6_N16 cycloneive_io_obuf \GPIO_1[20]~output ( - .i(\D[4]~83_combout ), - .oe(\D[0]~107_combout ), + .i(\D[4]~96_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[20]), @@ -3336,8 +3674,8 @@ defparam \GPIO_1[20]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y7_N9 cycloneive_io_obuf \GPIO_1[21]~output ( - .i(\D[5]~85_combout ), - .oe(\D[0]~107_combout ), + .i(\D[5]~98_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[21]), @@ -3349,8 +3687,8 @@ defparam \GPIO_1[21]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y0_N2 cycloneive_io_obuf \GPIO_1[22]~output ( - .i(\D[6]~93_combout ), - .oe(\D[0]~107_combout ), + .i(\D[6]~106_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[22]), @@ -3362,8 +3700,8 @@ defparam \GPIO_1[22]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y9_N23 cycloneive_io_obuf \GPIO_1[23]~output ( - .i(\D[7]~94_combout ), - .oe(\D[0]~107_combout ), + .i(\D[7]~107_combout ), + .oe(\D[0]~121_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[23]), @@ -3401,7 +3739,7 @@ defparam \GPIO_1[28]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y10_N16 cycloneive_io_obuf \GPIO_1[29]~output ( - .i(!\z80_|memory_ifc_|nIORQ_out~0_combout ), + .i(\z80_|memory_ifc_|nIORQ_out~0_combout ), .oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -3867,6 +4205,305 @@ defparam \buzzer_out~output .bus_hold = "false"; defparam \buzzer_out~output .open_drain_output = "false"; // synopsys translate_on +// Location: IOOBUF_X11_Y0_N16 +cycloneive_io_obuf \DRAM_BA[0]~output ( + .i(\sdram_|r.bank [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_BA[0]), + .obar()); +// synopsys translate_off +defparam \DRAM_BA[0]~output .bus_hold = "false"; +defparam \DRAM_BA[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y0_N9 +cycloneive_io_obuf \DRAM_BA[1]~output ( + .i(\sdram_|r.bank [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_BA[1]), + .obar()); +// synopsys translate_off +defparam \DRAM_BA[1]~output .bus_hold = "false"; +defparam \DRAM_BA[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y0_N9 +cycloneive_io_obuf \DRAM_DQM[0]~output ( + .i(\sdram_|r.dq_masks [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQM[0]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQM[0]~output .bus_hold = "false"; +defparam \DRAM_DQM[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y0_N16 +cycloneive_io_obuf \DRAM_DQM[1]~output ( + .i(\sdram_|r.dq_masks [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQM[1]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQM[1]~output .bus_hold = "false"; +defparam \DRAM_DQM[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y11_N2 +cycloneive_io_obuf \DRAM_RAS_N~output ( + .i(\sdram_|r.state [2]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_RAS_N), + .obar()); +// synopsys translate_off +defparam \DRAM_RAS_N~output .bus_hold = "false"; +defparam \DRAM_RAS_N~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y11_N9 +cycloneive_io_obuf \DRAM_CAS_N~output ( + .i(\sdram_|r.state [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_CAS_N), + .obar()); +// synopsys translate_off +defparam \DRAM_CAS_N~output .bus_hold = "false"; +defparam \DRAM_CAS_N~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N23 +cycloneive_io_obuf \DRAM_CKE~output ( + .i(vcc), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_CKE), + .obar()); +// synopsys translate_off +defparam \DRAM_CKE~output .bus_hold = "false"; +defparam \DRAM_CKE~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y0_N23 +cycloneive_io_obuf \DRAM_CLK~output ( + .i(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK_outclk ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_CLK), + .obar()); +// synopsys translate_off +defparam \DRAM_CLK~output .bus_hold = "false"; +defparam \DRAM_CLK~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y27_N2 +cycloneive_io_obuf \DRAM_WE_N~output ( + .i(\sdram_|r.state [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_WE_N), + .obar()); +// synopsys translate_off +defparam \DRAM_WE_N~output .bus_hold = "false"; +defparam \DRAM_WE_N~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y0_N23 +cycloneive_io_obuf \DRAM_CS_N~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_CS_N), + .obar()); +// synopsys translate_off +defparam \DRAM_CS_N~output .bus_hold = "false"; +defparam \DRAM_CS_N~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y4_N16 +cycloneive_io_obuf \DRAM_ADDR[0]~output ( + .i(\sdram_|r.address [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[0]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[0]~output .bus_hold = "false"; +defparam \DRAM_ADDR[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y0_N9 +cycloneive_io_obuf \DRAM_ADDR[1]~output ( + .i(\sdram_|r.address [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[1]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[1]~output .bus_hold = "false"; +defparam \DRAM_ADDR[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y0_N2 +cycloneive_io_obuf \DRAM_ADDR[2]~output ( + .i(\sdram_|r.address [2]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[2]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[2]~output .bus_hold = "false"; +defparam \DRAM_ADDR[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X20_Y0_N9 +cycloneive_io_obuf \DRAM_ADDR[3]~output ( + .i(\sdram_|r.address [3]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[3]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[3]~output .bus_hold = "false"; +defparam \DRAM_ADDR[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X25_Y0_N16 +cycloneive_io_obuf \DRAM_ADDR[4]~output ( + .i(\sdram_|r.address [4]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[4]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[4]~output .bus_hold = "false"; +defparam \DRAM_ADDR[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y0_N23 +cycloneive_io_obuf \DRAM_ADDR[5]~output ( + .i(\sdram_|r.address [5]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[5]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[5]~output .bus_hold = "false"; +defparam \DRAM_ADDR[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X20_Y0_N2 +cycloneive_io_obuf \DRAM_ADDR[6]~output ( + .i(\sdram_|r.address [6]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[6]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[6]~output .bus_hold = "false"; +defparam \DRAM_ADDR[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y0_N2 +cycloneive_io_obuf \DRAM_ADDR[7]~output ( + .i(\sdram_|r.address [7]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[7]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[7]~output .bus_hold = "false"; +defparam \DRAM_ADDR[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y5_N23 +cycloneive_io_obuf \DRAM_ADDR[8]~output ( + .i(\sdram_|r.address [8]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[8]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[8]~output .bus_hold = "false"; +defparam \DRAM_ADDR[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y4_N23 +cycloneive_io_obuf \DRAM_ADDR[9]~output ( + .i(\sdram_|r.address [9]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[9]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[9]~output .bus_hold = "false"; +defparam \DRAM_ADDR[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y8_N23 +cycloneive_io_obuf \DRAM_ADDR[10]~output ( + .i(\sdram_|r.address [10]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[10]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[10]~output .bus_hold = "false"; +defparam \DRAM_ADDR[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y7_N2 +cycloneive_io_obuf \DRAM_ADDR[11]~output ( + .i(\sdram_|r.address [11]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[11]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[11]~output .bus_hold = "false"; +defparam \DRAM_ADDR[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y6_N16 +cycloneive_io_obuf \DRAM_ADDR[12]~output ( + .i(\sdram_|r.address[11]~_Duplicate_1_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_ADDR[12]), + .obar()); +// synopsys translate_off +defparam \DRAM_ADDR[12]~output .bus_hold = "false"; +defparam \DRAM_ADDR[12]~output .open_drain_output = "false"; +// synopsys translate_on + // Location: IOOBUF_X0_Y24_N23 cycloneive_io_obuf \I2C_SCLK~output ( .i(\ula_|i2c_loader_|scl_out~q ), @@ -3893,6 +4530,214 @@ defparam \I2C_SDAT~output .bus_hold = "false"; defparam \I2C_SDAT~output .open_drain_output = "true"; // synopsys translate_on +// Location: IOOBUF_X0_Y23_N16 +cycloneive_io_obuf \DRAM_DQ[0]~output ( + .i(\sdram_|Mux72~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[0]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[0]~output .bus_hold = "false"; +defparam \DRAM_DQ[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y23_N23 +cycloneive_io_obuf \DRAM_DQ[1]~output ( + .i(\sdram_|Mux3~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[1]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[1]~output .bus_hold = "false"; +defparam \DRAM_DQ[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y0_N9 +cycloneive_io_obuf \DRAM_DQ[2]~output ( + .i(\sdram_|Mux2~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[2]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[2]~output .bus_hold = "false"; +defparam \DRAM_DQ[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y7_N9 +cycloneive_io_obuf \DRAM_DQ[3]~output ( + .i(\sdram_|Mux1~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[3]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[3]~output .bus_hold = "false"; +defparam \DRAM_DQ[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y12_N2 +cycloneive_io_obuf \DRAM_DQ[4]~output ( + .i(\sdram_|Mux0~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[4]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[4]~output .bus_hold = "false"; +defparam \DRAM_DQ[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y15_N2 +cycloneive_io_obuf \DRAM_DQ[5]~output ( + .i(\sdram_|Mux73~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[5]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[5]~output .bus_hold = "false"; +defparam \DRAM_DQ[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y15_N9 +cycloneive_io_obuf \DRAM_DQ[6]~output ( + .i(\sdram_|Mux74~1_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[6]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[6]~output .bus_hold = "false"; +defparam \DRAM_DQ[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N16 +cycloneive_io_obuf \DRAM_DQ[7]~output ( + .i(\sdram_|Mux75~0_combout ), + .oe(\sdram_|Mux84~1_combout ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[7]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[7]~output .bus_hold = "false"; +defparam \DRAM_DQ[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y0_N16 +cycloneive_io_obuf \DRAM_DQ[8]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[8]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[8]~output .bus_hold = "false"; +defparam \DRAM_DQ[8]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y0_N2 +cycloneive_io_obuf \DRAM_DQ[9]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[9]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[9]~output .bus_hold = "false"; +defparam \DRAM_DQ[9]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y0_N2 +cycloneive_io_obuf \DRAM_DQ[10]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[10]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[10]~output .bus_hold = "false"; +defparam \DRAM_DQ[10]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y0_N9 +cycloneive_io_obuf \DRAM_DQ[11]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[11]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[11]~output .bus_hold = "false"; +defparam \DRAM_DQ[11]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y0_N23 +cycloneive_io_obuf \DRAM_DQ[12]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[12]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[12]~output .bus_hold = "false"; +defparam \DRAM_DQ[12]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y0_N16 +cycloneive_io_obuf \DRAM_DQ[13]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[13]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[13]~output .bus_hold = "false"; +defparam \DRAM_DQ[13]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y0_N23 +cycloneive_io_obuf \DRAM_DQ[14]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[14]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[14]~output .bus_hold = "false"; +defparam \DRAM_DQ[14]~output .open_drain_output = "true"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y12_N9 +cycloneive_io_obuf \DRAM_DQ[15]~output ( + .i(!\sdram_|Mux84~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(DRAM_DQ[15]), + .obar()); +// synopsys translate_off +defparam \DRAM_DQ[15]~output .bus_hold = "false"; +defparam \DRAM_DQ[15]~output .open_drain_output = "true"; +// synopsys translate_on + // Location: IOIBUF_X27_Y0_N22 cycloneive_io_ibuf \CLOCK_50~input ( .i(CLOCK_50), @@ -4024,7 +4869,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N4 +// Location: LCCOMB_X25_Y33_N0 cycloneive_lcell_comb \ula_|clocks_|counter[0]~0 ( // Equation(s): // \ula_|clocks_|counter[0]~0_combout = !\ula_|clocks_|counter [0] @@ -4041,7 +4886,7 @@ defparam \ula_|clocks_|counter[0]~0 .lut_mask = 16'h0F0F; defparam \ula_|clocks_|counter[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N5 +// Location: FF_X25_Y33_N1 dffeas \ula_|clocks_|counter[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|counter[0]~0_combout ), @@ -4070,7 +4915,7 @@ defparam \SW[2]~input .bus_hold = "false"; defparam \SW[2]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N10 +// Location: LCCOMB_X25_Y33_N4 cycloneive_lcell_comb \ula_|clocks_|clk_cpu~0 ( // Equation(s): // \ula_|clocks_|clk_cpu~0_combout = \ula_|clocks_|clk_cpu~q $ (((\SW[2]~input_o ) # (!\ula_|clocks_|counter [0]))) @@ -4087,7 +4932,7 @@ defparam \ula_|clocks_|clk_cpu~0 .lut_mask = 16'h0FC3; defparam \ula_|clocks_|clk_cpu~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N11 +// Location: FF_X25_Y33_N5 dffeas \ula_|clocks_|clk_cpu ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|clk_cpu~0_combout ), @@ -4119,40 +4964,6 @@ defparam \ula_|clocks_|clk_cpu~clkctrl .clock_type = "global clock"; defparam \ula_|clocks_|clk_cpu~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N20 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hAAA0; -defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N12 -cycloneive_lcell_comb \z80_|sequencer_|ena_M ( -// Equation(s): -// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|ena_M~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; -defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: IOIBUF_X0_Y16_N8 cycloneive_io_ibuf \KEY[1]~input ( .i(KEY[1]), @@ -4163,7 +4974,7 @@ defparam \KEY[1]~input .bus_hold = "false"; defparam \KEY[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N6 +// Location: LCCOMB_X35_Y10_N0 cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( // Equation(s): // \z80_|interrupts_|nmi_armed~feeder_combout = VCC @@ -4180,11775 +4991,6 @@ defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N2 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hAAFF; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X24_Y15_N7 -dffeas \z80_|interrupts_|nmi_armed ( - .clk(!\KEY[1]~input_o ), - .d(\z80_|interrupts_|nmi_armed~feeder_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|nmi_armed~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; -defparam \z80_|interrupts_|nmi_armed .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N12 -cycloneive_lcell_comb \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder ( -// Equation(s): -// \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout = \z80_|interrupts_|nmi_armed~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|interrupts_|nmi_armed~q ), - .cin(gnd), - .combout(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .lut_mask = 16'hFF00; -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( -// Equation(s): -// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_eval_cond~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( -// Equation(s): -// \z80_|execute_|ixy_d~4_combout = (!\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h1100; -defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N30 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N31 -dffeas \z80_|sequencer_|DFFE_M3_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M3_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( -// Equation(s): -// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hD0D0; -defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N2 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N3 -dffeas \z80_|sequencer_|DFFE_M4_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M4_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal32~0_combout = (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(gnd), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal32~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h00CC; -defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N14 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF33; -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N10 -cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( -// Equation(s): -// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instED~q ) # (\z80_|decode_state_|DFFE_instCB~q ) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|decode_state_|table_xx~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; -defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~0_combout = (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal41~2_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal36~0_combout )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|pla_decode_|Equal36~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|pla_decode_|Equal36~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hB3A0; -defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N29 -dffeas \z80_|decode_state_|DFFE_instCB ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instCB~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h0020; -defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_ed_set~combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal2~1_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N17 -dffeas \z80_|decode_state_|DFFE_instED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instED~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & \z80_|decode_state_|DFFE_instED~q )) - - .dataa(\z80_|ir_|opcode [7]), - .datab(gnd), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( -// Equation(s): -// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_im_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal49~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout )) - - .dataa(gnd), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal49~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h3000; -defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~1_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [3])) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; -defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~14_combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~8_combout = (((!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h4FFF; -defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N12 -cycloneive_lcell_comb \z80_|nM1_int~2 ( -// Equation(s): -// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|nM1_int~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|nM1_int~2 .lut_mask = 16'h0055; -defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal49~0_combout ) # ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hEF00; -defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( -// Equation(s): -// \z80_|execute_|ixy_d~7_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & -// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & \z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; -defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal39~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; -defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~2_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal3~2_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal3~2_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( -// Equation(s): -// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( -// Equation(s): -// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( -// Equation(s): -// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( -// Equation(s): -// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~8_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( -// Equation(s): -// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal44~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal44~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0002; -defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( -// Equation(s): -// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hC800; -defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( -// Equation(s): -// \z80_|execute_|ixy_d~13_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|execute_|ixy_d~16_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(gnd), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal50~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h3000; -defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h8800; -defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( -// Equation(s): -// \z80_|execute_|ixy_d~17_combout = (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|pla_decode_|Equal50~0_combout & ((!\z80_|pla_decode_|Equal33~2_combout )))) # (!\z80_|decode_state_|DFFE_inst4~q & (((!\z80_|pla_decode_|Equal50~0_combout & -// !\z80_|pla_decode_|Equal33~2_combout )) # (!\z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal50~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h0537; -defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( -// Equation(s): -// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( -// Equation(s): -// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~12_combout & (((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ixy_d~12_combout & -// (!\z80_|execute_|ixy_d~13_combout & (\z80_|execute_|ixy_d~17_combout ))) - - .dataa(\z80_|execute_|ixy_d~12_combout ), - .datab(\z80_|execute_|ixy_d~13_combout ), - .datac(\z80_|execute_|ixy_d~17_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h30BA; -defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( -// Equation(s): -// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T5_ff~q ) # ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hCC8C; -defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( -// Equation(s): -// \z80_|execute_|ixy_d~15_combout = ((\z80_|pla_decode_|Equal49~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|execute_|ixy_d~11_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) - - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|ixy_d~14_combout ), - .datad(\z80_|execute_|ixy_d~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|execute_|ixy_d~15_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T5_ff~q & -// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N23 -dffeas \z80_|decode_state_|DFFE_instIY1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_iy_set~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instIY1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q )) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(gnd), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0500; -defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~14_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~2 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~18_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~26_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~27_combout = (\z80_|pla_decode_|Equal13~2_combout & \z80_|ir_|opcode [3]) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (((!\z80_|execute_|ctl_mRead~26_combout & !\z80_|execute_|ctl_mRead~27_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_mRead~27_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h02AA; -defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h5D00; -defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~18_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal12~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal55~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0500; -defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|comb~1 ( -// Equation(s): -// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|comb~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~1 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|comb~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~17_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~18_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~17_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~9_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~10_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~8_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~20_combout = (\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h2200; -defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal25~0_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal25~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~21_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~17_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~1_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'hFDFC; -defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal32~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal29~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal41~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal34~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal37~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal35~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal38~2_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal38~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal35~0_combout ) # (\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~3_combout = (\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|pla_decode_|Equal29~0_combout ) # ((\z80_|pla_decode_|Equal24~1_combout ) # (\z80_|reg_control_|reg_sys_we_lo~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|pla_decode_|Equal24~1_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|comb~0 ( -// Equation(s): -// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|comb~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~0 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal47~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|comb~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N8 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|reg_control_|reg_sys_we_lo~3_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # -// (!\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|reg_control_|reg_sys_we_lo~3_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h153F; -defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~22_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (((!\z80_|execute_|ctl_mRead~20_combout & !\z80_|execute_|ctl_mRead~21_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~20_combout ), - .datab(\z80_|execute_|ctl_mRead~21_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~24_combout = (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~18_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_mRead~22_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h0313; -defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~16_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N16 -cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( -// Equation(s): -// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|M5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88A0; -defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N17 -dffeas \z80_|sequencer_|M5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|M5~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|M5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|M5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~29 ( -// Equation(s): -// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & -// (((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~29 .lut_mask = 16'h0777; -defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~25_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~16_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout -// & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~17_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~17_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|setM1~29_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|setM1~29_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~7_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~1_combout = (!\z80_|decode_state_|DFFE_instED~q & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & !\z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~14_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~14 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_state_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~14_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((!\z80_|execute_|ctl_state_alu~14_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'h115F; -defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h1F3F; -defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|pla_decode_|Equal29~0_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal29~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|pla_decode_|Equal29~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; -defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (\z80_|reg_control_|reg_sel_pc~1_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~0_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h40C0; -defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( -// Equation(s): -// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|ctl_state_alu~8_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~8_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~17 .lut_mask = 16'h7000; -defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~6_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0004; -defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( -// Equation(s): -// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|execute_|ctl_mRead~18_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & -// (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~16 .lut_mask = 16'h135F; -defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|pla_decode_|Equal41~0_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal46~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [2] & \z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal46~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~17_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~6_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_flags_alu~17_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~6 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_flags_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]) - - .dataa(\z80_|ir_|opcode [6]), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0505; -defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~6_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~16_combout = (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|execute_|ctl_flags_alu~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & \z80_|execute_|ctl_reg_in_hi~3_combout )) - - .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( -// Equation(s): -// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|fMRead~17_combout & (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|fMRead~16_combout & \z80_|execute_|ctl_mWrite~8_combout ))) - - .dataa(\z80_|execute_|fMRead~17_combout ), - .datab(\z80_|execute_|ctl_sw_2d~4_combout ), - .datac(\z80_|execute_|fMRead~16_combout ), - .datad(\z80_|execute_|ctl_mWrite~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( -// Equation(s): -// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_mRead~24_combout & (\z80_|execute_|ctl_reg_in_hi~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|fMRead~18_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~24_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datad(\z80_|execute_|fMRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~36 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~36_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~36 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~9_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~9 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_op_low~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h007F; -defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~11_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h00AA; -defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal9~1_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ixy_d~6_combout & -// (((!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_mRead~11_combout ))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~4_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~7_combout & (!\z80_|execute_|ctl_ir_we~11_combout & ((!\z80_|execute_|ctl_ir_we~12_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout & (((!\z80_|execute_|ctl_ir_we~12_combout ) # -// (!\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0577; -defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~8_combout = (\z80_|execute_|ctl_alu_shift_oe~44_combout & (\z80_|execute_|ctl_sw_2d~7_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datab(\z80_|execute_|ctl_sw_2d~7_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~5_combout & (\z80_|execute_|fMRead~19_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & \z80_|execute_|ctl_sw_2d~8_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~5_combout ), - .datab(\z80_|execute_|fMRead~19_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datad(\z80_|execute_|ctl_sw_2d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (!\z80_|execute_|ctl_sw_1d~5_combout & (\z80_|execute_|ctl_sw_1d~4_combout & \z80_|execute_|ctl_sw_2d~9_combout ))) - - .dataa(\z80_|execute_|ctl_im_we~combout ), - .datab(\z80_|execute_|ctl_sw_1d~5_combout ), - .datac(\z80_|execute_|ctl_sw_1d~4_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal47~0_combout ))) # (!\z80_|execute_|ctl_sw_1d~6_combout ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7333; -defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~8_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~8 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_alu_op_low~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal2~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'h0111; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0088; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0037; -defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_zero~combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~4 ( -// Equation(s): -// \z80_|alu_|db_low[2]~4_combout = ((\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~4 .lut_mask = 16'h555D; -defparam \z80_|alu_|db_low[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_sw_4u~1_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # -// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_shift_oe~30_combout & (\z80_|execute_|ctl_alu_shift_oe~29_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal69~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal69~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~5_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [5]) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h00AA; -defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~5_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~12_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~12 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_alu_op_low~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal56~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal56~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~11_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~11 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op_low~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|nextM~2 ( -// Equation(s): -// \z80_|execute_|nextM~2_combout = (!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0011; -defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~4_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal69~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .lut_mask = 16'h0103; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~5_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hC0D0; -defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~15_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h0F3F; -defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_ir_we~7_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # -// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # -// (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~15_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~3_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ctl_ir_we~11_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h3000; -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_alu_core_R~4_combout & !\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout -// ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal48~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~18_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'hBBBF; -defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~17_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0100; -defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~18_combout = ((!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|ctl_iorw~10_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (\z80_|execute_|ctl_alu_shift_oe~18_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~19_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~13_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~13 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_alu_bs_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_alu_bs_oe~13_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~13_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal20~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal20~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal68~2_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|pla_decode_|Equal68~2_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~13 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_op_low~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~15_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_alu_op_low~13_combout & !\z80_|execute_|ctl_alu_op_low~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hBBBF; -defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_flags_bus~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~11 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .lut_mask = 16'hAFBF; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h70F0; -defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~8_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|execute_|ixy_d~10_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~9_combout = ((!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_flags_bus~8_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_flags_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_flags_bus~14_combout & (\z80_|execute_|ctl_flags_bus~11_combout & (\z80_|execute_|ctl_flags_bus~10_combout & \z80_|execute_|ctl_flags_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~14_combout ), - .datab(\z80_|execute_|ctl_flags_bus~11_combout ), - .datac(\z80_|execute_|ctl_flags_bus~10_combout ), - .datad(\z80_|execute_|ctl_flags_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_flags_xy_we~18_combout & (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout ))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datad(\z80_|execute_|ctl_flags_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & ((!\z80_|execute_|ctl_state_alu~14_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|execute_|ctl_ir_we~14_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) # -// (!\z80_|execute_|ctl_mWrite~3_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h3030; -defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h3700; -defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|pla_decode_|Equal41~2_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|execute_|ctl_bus_db_oe~0_combout & \z80_|execute_|ctl_alu_op1_sel_bus~12_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~13_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal48~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (((\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h1100; -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[2]~14_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N17 -dffeas \z80_|alu_|op1_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'h88C8; -defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~10_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~10 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op_low~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|fMWrite~11 ( -// Equation(s): -// \z80_|execute_|fMWrite~11_combout = ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~11 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|fMWrite~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~21_combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (\z80_|execute_|ctl_alu_op_low~9_combout ))) # (!\z80_|execute_|fMWrite~11_combout ) - - .dataa(\z80_|execute_|fMWrite~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~22_combout = ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~10_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~10_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~16_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h7737; -defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~17_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~16_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h2200; -defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel~36_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel~36 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & (\z80_|execute_|ctl_state_alu~8_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datab(\z80_|execute_|ctl_state_alu~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~18_combout = (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_mWrite~3_combout & -// (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~11_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~19_combout = ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|execute_|ctl_alu_op_low~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~33_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~12_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'h77F7; -defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'hF0FF; -defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~23_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_mRead~36_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|execute_|ctl_alu_op_low~22_combout ) # (((\z80_|execute_|ctl_alu_op_low~20_combout ) # (\z80_|execute_|ctl_alu_op_low~23_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ixy_d~9_combout & (((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|execute_|ixy_d~5_combout & -// (\z80_|pla_decode_|Equal40~1_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'hEAE0; -defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~34_combout = (\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFF08; -defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~combout = ((\z80_|execute_|ctl_alu_op_low~24_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~26_combout ))) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~26_combout ) # (\z80_|execute_|ctl_mRead~27_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~18_combout ) - - .dataa(\z80_|execute_|ctl_mRead~26_combout ), - .datab(\z80_|execute_|ctl_mRead~27_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hEF0F; -defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~39_combout = (\z80_|execute_|ctl_alu_shift_oe~37_combout ) # (((\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~42_combout = (\z80_|execute_|ctl_alu_shift_oe~40_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'hF200; -defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~21_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~22_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h3F20; -defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~23_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~22_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~22_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h0CEC; -defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~23_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~23_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'h32F0; -defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~25_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~24_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|ctl_alu_shift_oe~24_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h22EA; -defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~14_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~14 .lut_mask = 16'hC0C8; -defparam \z80_|execute_|ctl_alu_bs_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~26_combout = (!\z80_|execute_|ctl_alu_bs_oe~14_combout & ((\z80_|execute_|ctl_alu_shift_oe~25_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_bus_db_oe~1_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & -// (\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_bus_db_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~28_combout = ((\z80_|execute_|ctl_alu_shift_oe~27_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~20_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~44_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'hFF5F; -defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~4_combout -// & (\z80_|execute_|ctl_ir_we~10_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hEAC8; -defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|execute_|ctl_alu_bs_oe~10_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~32_combout = (!\z80_|execute_|ctl_alu_bs_oe~11_combout & ((\z80_|execute_|ctl_alu_shift_oe~28_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h00CF; -defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~32_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_alu_shift_oe~16_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout )))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hFF51; -defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|execute_|ctl_alu_op_low~11_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_state_alu~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_ir_we~7_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # -// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h3F20; -defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_ir_we~10_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~36_combout = (((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~12_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~26_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~36_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~9_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q ))) # (!\z80_|pla_decode_|Equal47~0_combout ) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~0_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hFDDD; -defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (\z80_|pla_decode_|Equal48~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h0088; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~9_combout = (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & (\z80_|execute_|ctl_flags_xy_we~8_combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h1300; -defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal8~0_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h0C00; -defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~9_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~9 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal39~0_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & -// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~1_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~1 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal11~1_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal11~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~10_combout = (\z80_|execute_|ctl_flags_alu~9_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_flags_sz_we~3_combout & !\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~9_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_alu~10_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~7_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal13~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~2 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~2_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) - - .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~2 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_pf_sel[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~2_combout = (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~25_combout = (\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_ir_we~14_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout ) # -// (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~25 .lut_mask = 16'h0377; -defparam \z80_|execute_|ctl_bus_inc_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~25_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hCC8C; -defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~10_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hCCC4; -defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'h3331; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~17_combout = (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~5_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h5557; -defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~6_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|reg_control_|reg_sys_we_lo~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'h7000; -defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & -// (((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal2~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|table_xx~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h0002; -defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|ctl_state_alu~7_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~2_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|nM1_int~2_combout & -// (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_mWrite~3_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & -// (((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h02AA; -defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & (\z80_|execute_|ctl_alu_res_oe~0_combout & !\z80_|execute_|ctl_alu_oe~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~11_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_alu_res_oe~1_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'h8C88; -defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( -// Equation(s): -// \z80_|alu_|db_high[3]~2_combout = (\z80_|execute_|ctl_alu_bs_oe~combout ) # ((\z80_|execute_|ctl_alu_op1_oe~1_combout ) # ((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFFEF; -defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( -// Equation(s): -// \z80_|alu_|db_high[3]~3_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout ) # (\z80_|alu_|db_high[3]~2_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(gnd), - .datac(\z80_|alu_|db_high[3]~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hFAFA; -defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~24 ( -// Equation(s): -// \z80_|alu_|db_low[2]~24_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[2]~3_combout & (\z80_|alu_|db_low[2]~6_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[2]~3_combout & -// \z80_|alu_|db_low[2]~6_combout )) # (!\z80_|alu_|db_high[3]~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[2]~3_combout ), - .datac(\z80_|alu_|db_low[2]~6_combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~24 .lut_mask = 16'hC0D5; -defparam \z80_|alu_|db_low[2]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~7 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~7_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~7 .lut_mask = 16'h0AAA; -defparam \z80_|reg_control_|reg_sys_we_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = ((!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|reg_control_|reg_sys_we_lo~7_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~10_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hFF57; -defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~43_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'hFF57; -defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~26_combout = (\z80_|execute_|ctl_alu_core_S~10_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & \z80_|execute_|ctl_bus_inc_oe~25_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_mWrite~9_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~9_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|execute_|ctl_alu_oe~8_combout & (\z80_|execute_|ctl_alu_oe~4_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|ctl_bus_db_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~8_combout ), - .datab(\z80_|execute_|ctl_alu_oe~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mWrite~16_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~6_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~7_combout = (\z80_|execute_|ctl_alu_oe~6_combout & (((!\z80_|execute_|ctl_mRead~27_combout & !\z80_|execute_|ctl_mRead~26_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~27_combout ), - .datac(\z80_|execute_|ctl_mRead~26_combout ), - .datad(\z80_|execute_|ctl_alu_oe~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~12_combout = (\z80_|execute_|ctl_alu_oe~11_combout ) # (((!\z80_|execute_|ctl_alu_oe~7_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_oe~5_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), - .datab(\z80_|execute_|ctl_alu_oe~5_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), - .datad(\z80_|execute_|ctl_alu_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_alu_oe~12_combout ) # (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_flags_alu~10_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~12_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~14_combout = (\z80_|execute_|ctl_alu_oe~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_oe~13_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hF5F5; -defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & -// (((!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mRead~26_combout ))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|nextM~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~53 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'h8C00; -defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~54 ( -// Equation(s): -// \z80_|execute_|setM1~54_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~54 .lut_mask = 16'hABFF; -defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~7_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((!\z80_|execute_|ctl_alu_oe~3_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout )) # -// (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_alu_oe~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|setM1~54_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_sw_2u~4_combout )) - - .dataa(\z80_|execute_|setM1~54_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~1_combout ), - .datad(\z80_|execute_|ctl_sw_2u~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_reg_gp_sel~36_combout & (\z80_|execute_|comb~0_combout $ ((!\z80_|ir_|opcode [0])))) # (!\z80_|execute_|ctl_reg_gp_sel~36_combout & (!\z80_|execute_|ctl_sw_2u~5_combout & -// (\z80_|execute_|comb~0_combout $ (!\z80_|ir_|opcode [0])))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'h82C3; -defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~35_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (\z80_|execute_|ctl_inc_cy~35_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_inc_cy~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hBF00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~6_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & -// (((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~2_combout & (\z80_|execute_|ctl_sw_2u~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|execute_|ctl_mRead~8_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(\z80_|execute_|ctl_sw_2u~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~10_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_op_low~13_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|rsel3 ( -// Equation(s): -// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|rsel3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel3 .lut_mask = 16'h7878; -defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & -// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7707; -defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~6_combout = (!\z80_|execute_|ctl_sw_2u~6_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout & \z80_|execute_|ctl_reg_out_hi~5_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2u~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~7_combout = ((\z80_|execute_|ctl_reg_out_hi~8_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|rsel0 ( -// Equation(s): -// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|rsel0~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel0 .lut_mask = 16'h5AAA; -defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .lut_mask = 16'h0444; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h7030; -defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~11_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~11_combout )) # (!\z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~14_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal77~0_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h0D0F; -defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_1d~8_combout ) # (!\z80_|execute_|ctl_sw_2d~14_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2d~10_combout ), - .datab(\z80_|execute_|ctl_sw_2d~14_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hBFAA; -defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # (\z80_|execute_|ctl_alu_shift_oe~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFEAA; -defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~11_combout ) # ((\z80_|execute_|ctl_sw_2d~12_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~11_combout ), - .datac(\z80_|execute_|ctl_sw_2d~12_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~34_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_alu_oe~2_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_inc_cy~34_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~75_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|pla_decode_|Equal38~2_combout & ((!\z80_|pla_decode_|Equal37~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|pla_decode_|Equal38~2_combout -// & !\z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|pla_decode_|Equal38~2_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal37~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~75_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal29~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal4~0_combout = (\z80_|execute_|comb~1_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|execute_|comb~1_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~48_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~46_combout = (\z80_|execute_|ctl_bus_inc_oe~48_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|pla_decode_|Equal4~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .datad(\z80_|sequencer_|DFFE_T5_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & ((!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & -// !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~92 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~92_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~92 .lut_mask = 16'h5F7F; -defparam \z80_|execute_|ctl_inc_cy~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~1 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal19~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~38_combout = (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal3~1_combout )) # (!\z80_|pla_decode_|Equal19~1_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal19~1_combout ), - .datac(\z80_|execute_|ctl_sw_4u~0_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~93 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~93_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~93 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~39_combout = (\z80_|execute_|ctl_inc_cy~93_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_inc_cy~93_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~24_combout = (\z80_|execute_|ctl_inc_cy~92_combout & (\z80_|execute_|ctl_inc_cy~38_combout & \z80_|execute_|ctl_inc_cy~39_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~92_combout ), - .datac(\z80_|execute_|ctl_inc_cy~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~24 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_bus_inc_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~1_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (\z80_|execute_|ctl_bus_inc_oe~46_combout & (\z80_|execute_|ctl_inc_cy~53_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~53_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~1 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~44_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'h1333; -defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~0_combout = (\z80_|execute_|ctl_bus_inc_oe~44_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & ((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~0 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_reg_gp_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (\z80_|execute_|ctl_reg_gp_we~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout & -// (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h3F15; -defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_sw_4u~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datad(\z80_|execute_|ctl_sw_4u~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( -// Equation(s): -// \z80_|execute_|fMRead~3_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|execute_|ctl_state_alu~14_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) # -// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_mRead~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h135F; -defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~15_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~12_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_sw_4u~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & -// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~94 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~94_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~94_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~94 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~87_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) - - .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~94_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~16_combout = (\z80_|execute_|fMRead~3_combout & (\z80_|execute_|ctl_reg_sel_wz~15_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ))) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~6_combout = ((\z80_|execute_|ctl_sw_4u~5_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout ))) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|execute_|ctl_sw_4u~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~6_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal1~5_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N22 -cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( -// Equation(s): -// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal1~6_combout & \z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal1~6_combout ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_exx~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N23 -dffeas \z80_|reg_control_|bank_exx ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_exx~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_exx~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_exx .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N26 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de1~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hF0D2; -defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N27 -dffeas \z80_|reg_control_|bank_hl_de1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal2~1_combout & \z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal2~1_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hC888; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h00FE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~12_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~13_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal50~0_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hEEEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( -// Equation(s): -// \z80_|execute_|fMWrite~3_combout = (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h0001; -defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [2]) # ((\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFAF; -defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( -// Equation(s): -// \z80_|execute_|fMRead~2_combout = (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_flags_bus~5_combout )) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~14_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMRead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h1010; -defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~19_combout = (\z80_|execute_|fMWrite~3_combout & (\z80_|execute_|fMRead~2_combout & !\z80_|execute_|ctl_ir_we~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|fMWrite~3_combout ), - .datac(\z80_|execute_|fMRead~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'h00C0; -defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [2] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h50F0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~14_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hC5CD; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~15_combout )))) # (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout & ((\z80_|execute_|ctl_ir_we~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_ir_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hCAC0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'h0050; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~47_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q ))) # (!\z80_|execute_|ctl_mRead~8_combout ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'hFF37; -defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|ctl_reg_use_sp~2_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_bus_inc_oe~47_combout & \z80_|execute_|nextM~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal6~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0050; -defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~21_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~5_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_sw_1d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & -// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'hAB00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~20_combout = (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mRead~14_combout & !\z80_|pla_decode_|Equal49~0_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .lut_mask = 16'h0101; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~22_combout = (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~21_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & ((\z80_|sequencer_|M5~q ) # (\z80_|sequencer_|DFFE_M4_ff~q )))) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|decode_state_|DFFE_instED~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'h0032; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout & \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~36_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h20AA; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|pla_decode_|Equal20~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h0505; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~14_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~14 .lut_mask = 16'hF0FF; -defparam \z80_|execute_|ctl_flags_hf_cpl~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (!\z80_|pla_decode_|Equal68~2_combout & (!\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_flags_hf_cpl~14_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|pla_decode_|Equal68~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~47 ( -// Equation(s): -// \z80_|execute_|setM1~47_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0015; -defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~48 ( -// Equation(s): -// \z80_|execute_|setM1~48_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|execute_|ctl_flags_hf_cpl~10_combout & (\z80_|execute_|setM1~47_combout & \z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .datac(\z80_|execute_|setM1~47_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~48 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~13_combout = (\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_iorw~10_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_flags_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~48_combout )))) - - .dataa(\z80_|execute_|setM1~48_combout ), - .datab(\z80_|execute_|ctl_flags_oe~1_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h0070; -defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~28_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & !\z80_|execute_|ctl_reg_in_hi~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~40_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~40_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~40_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~12_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~43_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~12_combout & (\z80_|execute_|ctl_inc_cy~43_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_inc_cy~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( -// Equation(s): -// \z80_|execute_|fMRead~6_combout = (\z80_|pla_decode_|Equal29~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ixy_d~7_combout ))) # (!\z80_|pla_decode_|Equal29~0_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & -// !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal29~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h0357; -defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( -// Equation(s): -// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & -// !\z80_|execute_|ctl_mRead~16_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h111F; -defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( -// Equation(s): -// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|fMRead~7_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|fMRead~7_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h10F0; -defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .datac(\z80_|execute_|fMRead~6_combout ), - .datad(\z80_|execute_|fMRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~13_combout = (\z80_|execute_|ctl_state_alu~8_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal52~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~8_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~10_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'h3331; -defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) # -// (!\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~9_combout = (\z80_|execute_|ctl_state_alu~14_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|execute_|ctl_state_alu~14_combout & (\z80_|pla_decode_|Equal52~1_combout & -// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'hF3A2; -defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~13_combout ), - .datab(\z80_|execute_|ctl_state_alu~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~9_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hFD00; -defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~4_combout = (((\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal62~2_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = ((!\z80_|execute_|ctl_mRead~4_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h373F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~13_combout ), - .datab(\z80_|execute_|ctl_state_alu~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~9_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h00FD; -defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~3 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~3_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal64~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal64~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~3 .lut_mask = 16'hEEFF; -defparam \z80_|execute_|ctl_pf_sel[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_flags_pf_we~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & (\z80_|execute_|ctl_alu_oe~7_combout & \z80_|execute_|ctl_pf_sel[0]~3_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .datac(\z80_|execute_|ctl_alu_oe~7_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_state_alu~14_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~15 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_state_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [4] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (\z80_|execute_|ctl_state_alu~15_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )) - - .dataa(\z80_|execute_|ctl_state_alu~15_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h00A0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~29_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ) # (((\z80_|execute_|ctl_reg_gp_sel[1]~23_combout & \z80_|ir_|opcode [5])) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal11~0_combout & -// ((\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mRead~5_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((\z80_|ir_|opcode [1] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(\z80_|execute_|ctl_sw_2u~5_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hFF70; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~20_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hF7F7; -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ctl_reg_sys_hilo~20_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h22A2; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N18 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0010; -defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h0F0B; -defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h00E4; -defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; -defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N15 -dffeas \z80_|reg_control_|bank_hl_de2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de2~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))))) - - .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hAC00; -defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & (((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~4_combout = (!\z80_|execute_|ctl_reg_in_hi~7_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & \z80_|execute_|ctl_state_alu~15_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_state_alu~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'h1100; -defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout & ((!\z80_|execute_|ctl_iorw~10_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datac(\z80_|execute_|ctl_iorw~10_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h004C; -defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout -// )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|pla_decode_|Equal25~0_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .lut_mask = 16'hA200; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout & !\z80_|execute_|ctl_sw_1d~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), - .datad(\z80_|execute_|ctl_sw_1d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & \z80_|execute_|ctl_reg_gp_we~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~6_combout = (((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_reg_gp_we~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .datab(\z80_|execute_|ctl_sw_4u~3_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~7_combout & (((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h00F7; -defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_flags_oe~1_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h1033; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_al_we~14_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFBF0; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = (\z80_|execute_|rsel3~combout & (((!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'h40CC; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (((\z80_|execute_|ctl_ir_we~7_combout ) # (\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo~20_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_iorw~11_combout ) # ((\z80_|execute_|ctl_state_alu~14_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout )))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~25_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ) # -// (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hF5FF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|execute_|rsel0~combout & ((\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & -// (((\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )) # (!\z80_|execute_|setM1~48_combout ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'hCD05; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~6_combout & (!\z80_|execute_|ixy_d~9_combout ))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|pla_decode_|Equal10~0_combout )) # -// (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h1357; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal2~1_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~40 ( -// Equation(s): -// \z80_|execute_|setM1~40_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal8~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~40 .lut_mask = 16'h1155; -defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & ((\z80_|execute_|setM1~40_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h1101; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~93 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~93_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & ((\z80_|reg_control_|reg_sel_hl~0_combout ) # (\z80_|reg_control_|reg_sel_hl2~0_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .lut_mask = 16'h0E00; -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h00D8; -defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h0F00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout -// & (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~10_combout = (\z80_|execute_|ctl_reg_in_hi~9_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_gp_we~5_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~19_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_mRead~22_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~8_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # (\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h00B0; -defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFECC; -defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~3_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout )) - - .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & !\z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N20 -cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( -// Equation(s): -// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|pla_decode_|Equal21~2_combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y12_N21 -dffeas \z80_|reg_control_|bank_af ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_af~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_af~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_af .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (!\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h1000; -defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; -defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h2200; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal19~0_combout & ((!\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout ) # -// (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'h035F; -defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal33~0_combout )) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hF8F8; -defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~7_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~6_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_bus~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( -// Equation(s): -// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~24 .lut_mask = 16'h0777; -defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~13_combout = (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datad(\z80_|execute_|ctl_flags_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~combout = (\z80_|execute_|ctl_flags_bus~7_combout ) # (((\z80_|execute_|ctl_flags_hf2_we~combout ) # (!\z80_|execute_|ctl_flags_bus~13_combout )) # (!\z80_|execute_|fMRead~24_combout )) - - .dataa(\z80_|execute_|ctl_flags_bus~7_combout ), - .datab(\z80_|execute_|fMRead~24_combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mWrite~2_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h3777; -defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_dec~3_combout & (!\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|fMRead~3_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|fMRead~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h7757; -defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h04CC; -defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|execute_|ixy_d~16_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & -// (((!\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|execute_|ixy_d~16_combout ))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|execute_|ixy_d~16_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h557F; -defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~3_combout & (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & \z80_|execute_|ctl_reg_sel_pc~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & -// (((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'h88F8; -defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~8_combout ) # (\z80_|execute_|ctl_mRead~17_combout )))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_reg_sel_pc~10_combout & (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .datab(\z80_|execute_|ctl_inc_cy~94_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout & -// !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~29_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|ir_|opcode [5]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~14_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h5455; -defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~49 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~49_combout = (!\z80_|pla_decode_|Equal35~0_combout & (((\z80_|ir_|opcode [3]) # (\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal24~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~49 .lut_mask = 16'h00FD; -defparam \z80_|execute_|pc_inc_hold~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_mRead~15_combout & (!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout )) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0A00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~28_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal33~2_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal50~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'h0515; -defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~35 ( -// Equation(s): -// \z80_|execute_|setM1~35_combout = (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~35 .lut_mask = 16'h0003; -defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~36 ( -// Equation(s): -// \z80_|execute_|setM1~36_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|execute_|ctl_mRead~9_combout & (\z80_|execute_|pc_inc_hold~28_combout & \z80_|execute_|setM1~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~28_combout ), - .datad(\z80_|execute_|setM1~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~36 .lut_mask = 16'h2000; -defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( -// Equation(s): -// \z80_|execute_|fMRead~5_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|setM1~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|setM1~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0100; -defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & (((\z80_|execute_|ctl_bus_inc_oe~29_combout & \z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'hA222; -defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'hC8C8; -defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~1_combout = (\z80_|execute_|pc_inc_hold~29_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(gnd), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'hEE00; -defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~2_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'h1113; -defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|pc_inc_hold~49_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|pc_inc_hold~49_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hF0B0; -defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~3_combout = (((\z80_|execute_|ctl_reg_sys_we~0_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout )) # (!\z80_|execute_|ctl_reg_sys_we~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~3 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_sys_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~2_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~3_combout = (\z80_|execute_|ctl_reg_sys_we_lo~2_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_reg_sys_we_lo~3_combout & \z80_|sequencer_|DFFE_M2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|execute_|ctl_reg_sys_we~3_combout ) # ((\z80_|execute_|ctl_reg_sys_we_lo~4_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~7_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hEFFF; -defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h3330; -defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_flags_bus~4_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_flags_bus~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hFF5D; -defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~34_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_inc_cy~34_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal48~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal48~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hF2F0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = (((\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'hBF3F; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_alu_oe~4_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) - - .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_alu_oe~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~4_combout = ((!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|pla_decode_|Equal3~1_combout ) # (!\z80_|pla_decode_|Equal19~1_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal19~1_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~4 .lut_mask = 16'h5777; -defparam \z80_|execute_|ctl_reg_sel_wz~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~5_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~5 .lut_mask = 16'h001F; -defparam \z80_|execute_|ctl_reg_sel_wz~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~6_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & \z80_|execute_|ctl_reg_sel_wz~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_in_hi~4_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & \z80_|execute_|ctl_reg_sel_wz~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~16_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~14_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .lut_mask = 16'h80C0; -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~16_combout & (((!\z80_|execute_|ctl_mRead~36_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'hE0F0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_al_we~13_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'h80AA; -defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|ctl_reg_sel_pc~12_combout & (\z80_|execute_|setM1~52_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ctl_mRead~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ixy_d~16_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h2022; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~0 ( -// Equation(s): -// \z80_|execute_|fMRead~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMRead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~0 .lut_mask = 16'h5D5D; -defparam \z80_|execute_|fMRead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal52~1_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h0030; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|fMRead~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h050F; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~4_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h0FAF; -defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_reg_sys_hilo~20_combout & ((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) # -// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datac(\z80_|execute_|ctl_inc_dec~4_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hD0DD; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~9_combout = (!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_ir_we~14_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_M2_ff~q )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout -// )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00C4; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~49_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h08CC; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~17_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h4455; -defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h5554; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & ((\z80_|execute_|fMRead~0_combout ) # ((!\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|pc_inc_hold~28_combout )))) - - .dataa(\z80_|execute_|fMRead~0_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h00BA; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_al_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h4404; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~18_combout = (\z80_|alu_control_|flags_cond_true~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~38_combout = ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~38_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_state_alu~14_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal6~1_combout & ((!\z80_|pla_decode_|Equal33~2_combout ) # (!\z80_|decode_state_|use_ixiy~combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~45_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~1 ( -// Equation(s): -// \z80_|execute_|fMRead~1_combout = ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~1 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|fMRead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|fMRead~1_combout ))) - - .dataa(\z80_|execute_|fMRead~1_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hF0D0; -defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~27_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_bus_inc_oe~47_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_bus_inc_oe~27_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~28_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~46_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_bus_inc_oe~45_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~37_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~39_combout & \z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~35_combout = ((\z80_|execute_|ctl_alu_oe~2_combout & ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout ) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~77_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_sw_4u~0_combout ), - .datac(\z80_|execute_|ctl_inc_cy~76_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ixy_d~9_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|pla_decode_|Equal10~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # -// (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|ctl_mWrite~2_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~33_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (\z80_|execute_|ctl_bus_inc_oe~32_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~34_combout = (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~53_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), - .datab(\z80_|execute_|ctl_inc_cy~77_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_bus_inc_oe~40_combout ) # (((\z80_|execute_|ctl_bus_inc_oe~35_combout ) # (\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~10_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # ((!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & -// (((!\z80_|execute_|ctl_alu_oe~2_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'hA0F3; -defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & \z80_|execute_|ctl_reg_sel_wz~10_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout )) - - .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ixy_d~6_combout & -// ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h2A3F; -defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|fMRead~6_combout ), - .datad(\z80_|execute_|fMRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_reg_sel_wz~11_combout & (\z80_|execute_|ctl_sw_4d~3_combout & (\z80_|execute_|ctl_sw_4d~4_combout & \z80_|execute_|ctl_sw_4d~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .datab(\z80_|execute_|ctl_sw_4d~3_combout ), - .datac(\z80_|execute_|ctl_sw_4d~4_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~45 ( -// Equation(s): -// \z80_|execute_|setM1~45_combout = (!\z80_|execute_|ctl_iorw~11_combout & (\z80_|execute_|ctl_mRead~19_combout & (!\z80_|execute_|ctl_mRead~13_combout & !\z80_|execute_|ctl_iorw~10_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_mRead~19_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0004; -defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~46 ( -// Equation(s): -// \z80_|execute_|setM1~46_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|setM1~45_combout & !\z80_|execute_|ctl_mWrite~6_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_al_we~13_combout ), - .datac(\z80_|execute_|setM1~45_combout ), - .datad(\z80_|execute_|ctl_mWrite~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~46 .lut_mask = 16'h00C0; -defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~1_combout = ((!\z80_|decode_state_|use_ixiy~combout & ((\z80_|pla_decode_|Equal50~0_combout ) # (\z80_|pla_decode_|Equal49~0_combout )))) # (!\z80_|execute_|setM1~46_combout ) - - .dataa(\z80_|pla_decode_|Equal50~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|execute_|setM1~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'h32FF; -defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_al_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_al_we~14_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~6_combout = ((\z80_|execute_|ctl_sw_4d~0_combout ) # ((\z80_|execute_|ctl_sw_4d~1_combout & \z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_sw_4d~5_combout ) - - .dataa(\z80_|execute_|ctl_sw_4d~5_combout ), - .datab(\z80_|execute_|ctl_sw_4d~1_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_sw_4d~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( -// Equation(s): -// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~4_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0A00; -defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|fMRead~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h5DFF; -defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal21~1_combout & (((\z80_|decode_state_|table_xx~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h00DF; -defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~20_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~20 .lut_mask = 16'h5010; -defparam \z80_|execute_|ctl_reg_sel_pc~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|setM1~36_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .datab(\z80_|execute_|setM1~36_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .datad(\z80_|execute_|fMRead~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hF0F7; -defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~17_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~18_combout = (((!\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'h4FFF; -defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~19_combout = ((\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (\z80_|execute_|ctl_reg_sel_pc~18_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & \z80_|execute_|ctl_reg_sel_wz~4_combout ))) - - .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h0800; -defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N18 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~combout = (!\z80_|execute_|ctl_reg_sel_wz~18_combout & (\z80_|execute_|ctl_reg_sel_pc~19_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|reg_control_|reg_sel_pc~3_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0400; -defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # ((\z80_|execute_|ctl_sw_4d~6_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|execute_|ctl_sw_4d~6_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[7]~92_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N25 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N26 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0F0F; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N27 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N9 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N29 -dffeas \z80_|resets_|DFFE_intr_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - // Location: IOIBUF_X53_Y14_N1 cycloneive_io_ibuf \KEY[0]~input ( .i(KEY[0]), @@ -15959,7 +5001,7 @@ defparam \KEY[0]~input .bus_hold = "false"; defparam \KEY[0]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X52_Y14_N4 +// Location: LCCOMB_X52_Y14_N12 cycloneive_lcell_comb reset( // Equation(s): // \reset~combout = (!\KEY[0]~input_o ) # (!\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ) @@ -15976,7 +5018,7 @@ defparam reset.lut_mask = 16'h0FFF; defparam reset.sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y13_N26 +// Location: LCCOMB_X52_Y14_N18 cycloneive_lcell_comb \z80_|resets_|x1~0 ( // Equation(s): // \z80_|resets_|x1~0_combout = !\reset~combout @@ -15993,7 +5035,7 @@ defparam \z80_|resets_|x1~0 .lut_mask = 16'h00FF; defparam \z80_|resets_|x1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N0 +// Location: LCCOMB_X26_Y32_N8 cycloneive_lcell_comb \z80_|fpga_reset~feeder ( // Equation(s): // \z80_|fpga_reset~feeder_combout = VCC @@ -16010,7 +5052,7 @@ defparam \z80_|fpga_reset~feeder .lut_mask = 16'hFFFF; defparam \z80_|fpga_reset~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N1 +// Location: FF_X26_Y32_N9 dffeas \z80_|fpga_reset ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|fpga_reset~feeder_combout ), @@ -16029,7 +5071,7 @@ defparam \z80_|fpga_reset .is_wysiwyg = "true"; defparam \z80_|fpga_reset .power_up = "low"; // synopsys translate_on -// Location: CLKCTRL_G12 +// Location: CLKCTRL_G10 cycloneive_clkctrl \z80_|fpga_reset~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\z80_|fpga_reset~q }), @@ -16042,7 +5084,7 @@ defparam \z80_|fpga_reset~clkctrl .clock_type = "global clock"; defparam \z80_|fpga_reset~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X35_Y13_N27 +// Location: FF_X52_Y14_N19 dffeas \z80_|resets_|x1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|resets_|x1~0_combout ), @@ -16061,1677 +5103,106 @@ defparam \z80_|resets_|x1 .is_wysiwyg = "true"; defparam \z80_|resets_|x1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y17_N18 -cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( +// Location: LCCOMB_X31_Y14_N0 +cycloneive_lcell_comb \z80_|resets_|x3 ( // Equation(s): -// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # -// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) +// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|resets_|clrpc_int~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), .datad(\z80_|resets_|x1~q ), .cin(gnd), - .combout(\z80_|resets_|clrpc_int~0_combout ), + .combout(\z80_|resets_|x3~combout ), .cout()); // synopsys translate_off -defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; -defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; +defparam \z80_|resets_|x3 .lut_mask = 16'hFF50; +defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y17_N19 -dffeas \z80_|resets_|clrpc_int ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|clrpc_int~0_combout ), +// Location: FF_X31_Y14_N1 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|x3~combout ), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(\z80_|fpga_reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|resets_|clrpc_int~q ), + .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; -defparam \z80_|resets_|clrpc_int .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N28 -cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( -// Equation(s): -// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_10~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|clrpc_int~q ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .datac(\z80_|resets_|DFFE_intr_ff3~q ), - .datad(\z80_|resets_|clrpc_int~q ), - .cin(gnd), - .combout(\z80_|resets_|clrpc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; -defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( -// Equation(s): -// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [7]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h5550; -defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )) # (!\z80_|execute_|ctl_al_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|execute_|ctl_al_we~14_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & (\z80_|execute_|ctl_ir_we~4_combout & -// ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_al_we~13_combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'h0EEE; -defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~8_combout = ((\z80_|execute_|ctl_al_we~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_al_we~7_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~9_combout = (((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout )) # (!\z80_|execute_|ctl_al_we~4_combout )) # (!\z80_|execute_|ctl_alu_oe~10_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~10_combout ), - .datab(\z80_|execute_|ctl_al_we~4_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~8_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_al_we~9_combout ) # (!\z80_|execute_|setM1~45_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~8_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|setM1~45_combout ), - .datad(\z80_|execute_|ctl_al_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEEAE; -defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~10_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) - - .dataa(\z80_|execute_|ctl_al_we~6_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_4d~5_combout ), - .datad(\z80_|execute_|ctl_al_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFFAF; -defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~12_combout = (\z80_|execute_|ctl_al_we~11_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|setM1~52_combout )) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_al_we~11_combout ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N5 -dffeas \z80_|address_latch_|Q[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [7]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~6_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( -// Equation(s): -// \z80_|execute_|fIOWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h3373; -defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~4_combout & (((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|fIOWrite~0_combout )) # (!\z80_|execute_|ctl_inc_dec~4_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~4_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~9_combout = ((\z80_|execute_|ctl_inc_dec~8_combout ) # ((!\z80_|execute_|ctl_reg_gp_we~0_combout & \z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_inc_dec~3_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_inc_dec~3_combout ), - .datad(\z80_|execute_|ctl_inc_dec~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hFF4F; -defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|execute_|ctl_inc_dec~9_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hF3F3; -defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout ) - - .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h55FF; -defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N1 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N3 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hCA00; -defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h1000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|gdfx_temp0[2]~36_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hA2A2; -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|alu_control_|db[2]~29_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|alu_control_|db[2]~29_combout & -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) - - .dataa(\z80_|alu_control_|db[2]~29_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .datac(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'h8CAF; -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_iy~2_combout = (\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0020; -defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|reg_control_|reg_sel_iy~2_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N15 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~42_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N29 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~37_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & \z80_|reg_file_|gdfx_temp0[2]~35_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~40_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~42_combout = ((\z80_|reg_file_|gdfx_temp0[2]~41_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[2]~42_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .datad(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|gdfx_temp0[0]~10_combout & (\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .datab(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'h8088; -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X30_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder ( +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( // Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout +// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .sum_lutc_input = "datac"; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hFF0F; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), +// Location: FF_X35_Y10_N1 +dffeas \z80_|interrupts_|nmi_armed ( + .clk(!\KEY[1]~input_o ), + .d(\z80_|interrupts_|nmi_armed~feeder_combout ), .asdata(vcc), - .clrn(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .q(\z80_|interrupts_|nmi_armed~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; +defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; +defparam \z80_|interrupts_|nmi_armed .power_up = "low"; // synopsys translate_on -// Location: FF_X29_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), +// Location: CLKCTRL_G7 +cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), + .clkselect(2'b00), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .prn(vcc)); + .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X29_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( +// Location: LCCOMB_X32_Y12_N30 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~15_combout & (\z80_|reg_file_|gdfx_temp0[0]~14_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .datad(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hA200; -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[0]~12_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .datad(\z80_|alu_control_|db[0]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N7 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~11_combout & (\z80_|reg_file_|gdfx_temp0[0]~16_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & \z80_|reg_file_|gdfx_temp0[0]~13_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hC4FF; -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|reg_file_|gdfx_temp0[0]~22_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) +// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) .dataa(gnd), - .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hCF00; -defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~72_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF33; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; // synopsys translate_on // Location: CLKCTRL_G18 @@ -17747,158 +5218,33 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add0~14 ( -// Equation(s): -// \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) -// \ula_|video_|Add0~15 = CARRY((!\ula_|video_|Add0~13 ) # (!\ula_|video_|vga_hc [7])) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~13 ), - .combout(\ula_|video_|Add0~14_combout ), - .cout(\ula_|video_|Add0~15 )); -// synopsys translate_off -defparam \ula_|video_|Add0~14 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Add0~16 ( -// Equation(s): -// \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) -// \ula_|video_|Add0~17 = CARRY((\ula_|video_|vga_hc [8] & !\ula_|video_|Add0~15 )) - - .dataa(\ula_|video_|vga_hc [8]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~15 ), - .combout(\ula_|video_|Add0~16_combout ), - .cout(\ula_|video_|Add0~17 )); -// synopsys translate_off -defparam \ula_|video_|Add0~16 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N26 -cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( -// Equation(s): -// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Equal1~0_combout ), - .datad(\ula_|video_|Add0~16_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hF000; -defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y33_N27 -dffeas \ula_|video_|vga_hc[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N20 -cycloneive_lcell_comb \ula_|video_|Add0~18 ( -// Equation(s): -// \ula_|video_|Add0~18_combout = \ula_|video_|Add0~17 $ (\ula_|video_|vga_hc [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [9]), - .cin(\ula_|video_|Add0~17 ), - .combout(\ula_|video_|Add0~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add0~18 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( -// Equation(s): -// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~18_combout ) - - .dataa(gnd), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(gnd), - .datad(\ula_|video_|Add0~18_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hCC00; -defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y33_N21 -dffeas \ula_|video_|vga_hc[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N2 +// Location: LCCOMB_X29_Y30_N8 cycloneive_lcell_comb \ula_|video_|Add0~0 ( // Equation(s): // \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) // \ula_|video_|Add0~1 = CARRY(\ula_|video_|vga_hc [0]) - .dataa(gnd), - .datab(\ula_|video_|vga_hc [0]), + .dataa(\ula_|video_|vga_hc [0]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(gnd), .combout(\ula_|video_|Add0~0_combout ), .cout(\ula_|video_|Add0~1 )); // synopsys translate_off -defparam \ula_|video_|Add0~0 .lut_mask = 16'h33CC; +defparam \ula_|video_|Add0~0 .lut_mask = 16'h55AA; defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N0 +// Location: LCCOMB_X29_Y29_N14 cycloneive_lcell_comb \ula_|video_|vga_hc~3 ( // Equation(s): -// \ula_|video_|vga_hc~3_combout = (\ula_|video_|Add0~0_combout & \ula_|video_|Equal1~0_combout ) +// \ula_|video_|vga_hc~3_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~0_combout ) .dataa(gnd), .datab(gnd), - .datac(\ula_|video_|Add0~0_combout ), - .datad(\ula_|video_|Equal1~0_combout ), + .datac(\ula_|video_|Equal1~0_combout ), + .datad(\ula_|video_|Add0~0_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~3_combout ), .cout()); @@ -17907,7 +5253,7 @@ defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hF000; defparam \ula_|video_|vga_hc~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y31_N1 +// Location: FF_X29_Y29_N15 dffeas \ula_|video_|vga_hc[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_hc~3_combout ), @@ -17926,7 +5272,7 @@ defparam \ula_|video_|vga_hc[0] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N4 +// Location: LCCOMB_X29_Y30_N10 cycloneive_lcell_comb \ula_|video_|Add0~2 ( // Equation(s): // \ula_|video_|Add0~2_combout = (\ula_|video_|vga_hc [1] & (!\ula_|video_|Add0~1 )) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|Add0~1 ) # (GND))) @@ -17944,7 +5290,7 @@ defparam \ula_|video_|Add0~2 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N16 +// Location: LCCOMB_X30_Y30_N22 cycloneive_lcell_comb \ula_|video_|vga_hc[1]~feeder ( // Equation(s): // \ula_|video_|vga_hc[1]~feeder_combout = \ula_|video_|Add0~2_combout @@ -17961,7 +5307,7 @@ defparam \ula_|video_|vga_hc[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|vga_hc[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N17 +// Location: FF_X30_Y30_N23 dffeas \ula_|video_|vga_hc[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_hc[1]~feeder_combout ), @@ -17980,7 +5326,7 @@ defparam \ula_|video_|vga_hc[1] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N6 +// Location: LCCOMB_X29_Y30_N12 cycloneive_lcell_comb \ula_|video_|Add0~4 ( // Equation(s): // \ula_|video_|Add0~4_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add0~3 $ (GND))) # (!\ula_|video_|vga_hc [2] & (!\ula_|video_|Add0~3 & VCC)) @@ -17998,7 +5344,7 @@ defparam \ula_|video_|Add0~4 .lut_mask = 16'hC30C; defparam \ula_|video_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X39_Y33_N23 +// Location: FF_X29_Y30_N31 dffeas \ula_|video_|vga_hc[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -18017,50 +5363,33 @@ defparam \ula_|video_|vga_hc[2] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N8 +// Location: LCCOMB_X29_Y30_N14 cycloneive_lcell_comb \ula_|video_|Add0~6 ( // Equation(s): // \ula_|video_|Add0~6_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|Add0~5 )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Add0~5 ) # (GND))) // \ula_|video_|Add0~7 = CARRY((!\ula_|video_|Add0~5 ) # (!\ula_|video_|vga_hc [3])) - .dataa(gnd), - .datab(\ula_|video_|vga_hc [3]), + .dataa(\ula_|video_|vga_hc [3]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~5 ), .combout(\ula_|video_|Add0~6_combout ), .cout(\ula_|video_|Add0~7 )); // synopsys translate_off -defparam \ula_|video_|Add0~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add0~6 .lut_mask = 16'h5A5F; defparam \ula_|video_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N8 -cycloneive_lcell_comb \ula_|video_|vga_hc[3]~feeder ( -// Equation(s): -// \ula_|video_|vga_hc[3]~feeder_combout = \ula_|video_|Add0~6_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Add0~6_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vga_hc[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y33_N9 +// Location: FF_X30_Y30_N11 dffeas \ula_|video_|vga_hc[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc[3]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|Add0~6_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18071,7 +5400,7 @@ defparam \ula_|video_|vga_hc[3] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N10 +// Location: LCCOMB_X29_Y30_N16 cycloneive_lcell_comb \ula_|video_|Add0~8 ( // Equation(s): // \ula_|video_|Add0~8_combout = (\ula_|video_|vga_hc [4] & (\ula_|video_|Add0~7 $ (GND))) # (!\ula_|video_|vga_hc [4] & (!\ula_|video_|Add0~7 & VCC)) @@ -18089,7 +5418,7 @@ defparam \ula_|video_|Add0~8 .lut_mask = 16'hA50A; defparam \ula_|video_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X39_Y33_N31 +// Location: FF_X29_Y30_N7 dffeas \ula_|video_|vga_hc[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -18108,101 +5437,50 @@ defparam \ula_|video_|vga_hc[4] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N18 -cycloneive_lcell_comb \ula_|video_|Equal0~0 ( -// Equation(s): -// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N30 -cycloneive_lcell_comb \ula_|video_|Equal0~1 ( -// Equation(s): -// \ula_|video_|Equal0~1_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [7] & (!\ula_|video_|vga_hc [4] & \ula_|video_|Equal0~0_combout ))) - - .dataa(\ula_|video_|vga_hc [5]), - .datab(\ula_|video_|vga_hc [7]), - .datac(\ula_|video_|vga_hc [4]), - .datad(\ula_|video_|Equal0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0200; -defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Equal1~0 ( -// Equation(s): -// \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|Equal0~1_combout )) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9]) - - .dataa(\ula_|video_|vga_hc [9]), - .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal1~0 .lut_mask = 16'hF7FF; -defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N12 +// Location: LCCOMB_X29_Y30_N18 cycloneive_lcell_comb \ula_|video_|Add0~10 ( // Equation(s): // \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) // \ula_|video_|Add0~11 = CARRY((!\ula_|video_|Add0~9 ) # (!\ula_|video_|vga_hc [5])) - .dataa(\ula_|video_|vga_hc [5]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [5]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~9 ), .combout(\ula_|video_|Add0~10_combout ), .cout(\ula_|video_|Add0~11 )); // synopsys translate_off -defparam \ula_|video_|Add0~10 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add0~10 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N0 +// Location: LCCOMB_X29_Y30_N30 cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( // Equation(s): -// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~10_combout ) +// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Add0~10_combout & \ula_|video_|Equal1~0_combout ) .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Equal1~0_combout ), - .datad(\ula_|video_|Add0~10_combout ), + .datab(\ula_|video_|Add0~10_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), .cin(gnd), .combout(\ula_|video_|vga_hc~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hF000; +defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hCC00; defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X39_Y33_N1 +// Location: FF_X29_Y30_N1 dffeas \ula_|video_|vga_hc[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~0_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|vga_hc~0_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -18213,25 +5491,25 @@ defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N14 +// Location: LCCOMB_X29_Y30_N20 cycloneive_lcell_comb \ula_|video_|Add0~12 ( // Equation(s): // \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) // \ula_|video_|Add0~13 = CARRY((\ula_|video_|vga_hc [6] & !\ula_|video_|Add0~11 )) - .dataa(\ula_|video_|vga_hc [6]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [6]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add0~11 ), .combout(\ula_|video_|Add0~12_combout ), .cout(\ula_|video_|Add0~13 )); // synopsys translate_off -defparam \ula_|video_|Add0~12 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add0~12 .lut_mask = 16'hC30C; defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X39_Y33_N29 +// Location: FF_X29_Y30_N29 dffeas \ula_|video_|vga_hc[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -18250,7 +5528,25 @@ defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X39_Y33_N25 +// Location: LCCOMB_X29_Y30_N22 +cycloneive_lcell_comb \ula_|video_|Add0~14 ( +// Equation(s): +// \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) +// \ula_|video_|Add0~15 = CARRY((!\ula_|video_|Add0~13 ) # (!\ula_|video_|vga_hc [7])) + + .dataa(\ula_|video_|vga_hc [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~13 ), + .combout(\ula_|video_|Add0~14_combout ), + .cout(\ula_|video_|Add0~15 )); +// synopsys translate_off +defparam \ula_|video_|Add0~14 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y30_N3 dffeas \ula_|video_|vga_hc[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -18269,578 +5565,218 @@ defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; defparam \ula_|video_|vga_hc[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N0 +// Location: LCCOMB_X30_Y29_N12 +cycloneive_lcell_comb \ula_|video_|Equal0~0 ( +// Equation(s): +// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [0] & (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [1]))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N26 +cycloneive_lcell_comb \ula_|video_|Equal0~1 ( +// Equation(s): +// \ula_|video_|Equal0~1_combout = (!\ula_|video_|vga_hc [7] & (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [4] & \ula_|video_|Equal0~0_combout ))) + + .dataa(\ula_|video_|vga_hc [7]), + .datab(\ula_|video_|vga_hc [5]), + .datac(\ula_|video_|vga_hc [4]), + .datad(\ula_|video_|Equal0~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0400; +defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N24 +cycloneive_lcell_comb \ula_|video_|Add0~16 ( +// Equation(s): +// \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) +// \ula_|video_|Add0~17 = CARRY((\ula_|video_|vga_hc [8] & !\ula_|video_|Add0~15 )) + + .dataa(\ula_|video_|vga_hc [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~15 ), + .combout(\ula_|video_|Add0~16_combout ), + .cout(\ula_|video_|Add0~17 )); +// synopsys translate_off +defparam \ula_|video_|Add0~16 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N28 +cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( +// Equation(s): +// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Add0~16_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Add0~16_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y30_N17 +dffeas \ula_|video_|vga_hc[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~2_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N26 +cycloneive_lcell_comb \ula_|video_|Add0~18 ( +// Equation(s): +// \ula_|video_|Add0~18_combout = \ula_|video_|vga_hc [9] $ (\ula_|video_|Add0~17 ) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [9]), + .datac(gnd), + .datad(gnd), + .cin(\ula_|video_|Add0~17 ), + .combout(\ula_|video_|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add0~18 .lut_mask = 16'h3C3C; +defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N2 +cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( +// Equation(s): +// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Add0~18_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Add0~18_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y30_N5 +dffeas \ula_|video_|vga_hc[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~1_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N0 +cycloneive_lcell_comb \ula_|video_|Equal1~0 ( +// Equation(s): +// \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9])) # (!\ula_|video_|Equal0~1_combout ) + + .dataa(\ula_|video_|Equal0~1_combout ), + .datab(\ula_|video_|vga_hc [9]), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [8]), + .cin(gnd), + .combout(\ula_|video_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal1~0 .lut_mask = 16'hF7FF; +defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N0 cycloneive_lcell_comb \ula_|video_|Add1~0 ( // Equation(s): // \ula_|video_|Add1~0_combout = \ula_|video_|vga_vc [0] $ (VCC) // \ula_|video_|Add1~1 = CARRY(\ula_|video_|vga_vc [0]) - .dataa(gnd), - .datab(\ula_|video_|vga_vc [0]), + .dataa(\ula_|video_|vga_vc [0]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(gnd), .combout(\ula_|video_|Add1~0_combout ), .cout(\ula_|video_|Add1~1 )); // synopsys translate_off -defparam \ula_|video_|Add1~0 .lut_mask = 16'h33CC; +defparam \ula_|video_|Add1~0 .lut_mask = 16'h55AA; defparam \ula_|video_|Add1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N2 +// Location: LCCOMB_X32_Y29_N2 cycloneive_lcell_comb \ula_|video_|Add1~2 ( // Equation(s): // \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) // \ula_|video_|Add1~3 = CARRY((!\ula_|video_|Add1~1 ) # (!\ula_|video_|vga_vc [1])) - .dataa(\ula_|video_|vga_vc [1]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|vga_vc [1]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|Add1~1 ), .combout(\ula_|video_|Add1~2_combout ), .cout(\ula_|video_|Add1~3 )); // synopsys translate_off -defparam \ula_|video_|Add1~2 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add1~2 .lut_mask = 16'h3C3F; defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Add1~4 ( -// Equation(s): -// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) -// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) - - .dataa(\ula_|video_|vga_vc [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~3 ), - .combout(\ula_|video_|Add1~4_combout ), - .cout(\ula_|video_|Add1~5 )); -// synopsys translate_off -defparam \ula_|video_|Add1~4 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N12 -cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( -// Equation(s): -// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [2]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~4_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~4_combout ), - .datac(\ula_|video_|vga_vc [2]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N13 -dffeas \ula_|video_|vga_vc[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[2]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N6 -cycloneive_lcell_comb \ula_|video_|Add1~6 ( -// Equation(s): -// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) -// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~5 ), - .combout(\ula_|video_|Add1~6_combout ), - .cout(\ula_|video_|Add1~7 )); -// synopsys translate_off -defparam \ula_|video_|Add1~6 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( -// Equation(s): -// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) - - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|Add1~6_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h5140; -defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N3 -dffeas \ula_|video_|vga_vc[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_vc[3]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N8 -cycloneive_lcell_comb \ula_|video_|Add1~8 ( -// Equation(s): -// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) -// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~7 ), - .combout(\ula_|video_|Add1~8_combout ), - .cout(\ula_|video_|Add1~9 )); -// synopsys translate_off -defparam \ula_|video_|Add1~8 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( -// Equation(s): -// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~8_combout ), - .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[4]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N21 -dffeas \ula_|video_|vga_vc[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[4]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N10 -cycloneive_lcell_comb \ula_|video_|Add1~10 ( -// Equation(s): -// \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) -// \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~9 ), - .combout(\ula_|video_|Add1~10_combout ), - .cout(\ula_|video_|Add1~11 )); -// synopsys translate_off -defparam \ula_|video_|Add1~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N22 -cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( -// Equation(s): -// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [5])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~10_combout ))))) - - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(\ula_|video_|vga_vc [5]), - .datad(\ula_|video_|Add1~10_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[5]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h5140; -defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N17 -dffeas \ula_|video_|vga_vc[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_vc[5]~8_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N12 -cycloneive_lcell_comb \ula_|video_|Add1~12 ( -// Equation(s): -// \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) -// \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [6]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~11 ), - .combout(\ula_|video_|Add1~12_combout ), - .cout(\ula_|video_|Add1~13 )); -// synopsys translate_off -defparam \ula_|video_|Add1~12 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N6 -cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( -// Equation(s): -// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [6]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~12_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~12_combout ), - .datac(\ula_|video_|vga_vc [6]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[6]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N7 -dffeas \ula_|video_|vga_vc[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[6]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Add1~14 ( -// Equation(s): -// \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) -// \ula_|video_|Add1~15 = CARRY((!\ula_|video_|Add1~13 ) # (!\ula_|video_|vga_vc [7])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~13 ), - .combout(\ula_|video_|Add1~14_combout ), - .cout(\ula_|video_|Add1~15 )); -// synopsys translate_off -defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N14 -cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( -// Equation(s): -// \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~14_combout ), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[7]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N15 -dffeas \ula_|video_|vga_vc[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[7]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add1~16 ( -// Equation(s): -// \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) -// \ula_|video_|Add1~17 = CARRY((\ula_|video_|vga_vc [8] & !\ula_|video_|Add1~15 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [8]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~15 ), - .combout(\ula_|video_|Add1~16_combout ), - .cout(\ula_|video_|Add1~17 )); -// synopsys translate_off -defparam \ula_|video_|Add1~16 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N24 -cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( -// Equation(s): -// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~16_combout ), - .datac(\ula_|video_|vga_vc [8]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[8]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N25 -dffeas \ula_|video_|vga_vc[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[8]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Add1~18 ( -// Equation(s): -// \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_vc [9]), - .cin(\ula_|video_|Add1~17 ), - .combout(\ula_|video_|Add1~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N10 -cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( -// Equation(s): -// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [9]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~18_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~18_combout ), - .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[9]~9_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N11 -dffeas \ula_|video_|vga_vc[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[9]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Equal2~0 ( -// Equation(s): -// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [4] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [4]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [8]), - .cin(gnd), - .combout(\ula_|video_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y33_N30 -cycloneive_lcell_comb \ula_|video_|Equal3~0 ( -// Equation(s): -// \ula_|video_|Equal3~0_combout = (\ula_|video_|vga_vc [3] & (\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [1] & \ula_|video_|vga_vc [0]))) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal3~0 .lut_mask = 16'h0800; -defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Equal3~1 ( -// Equation(s): -// \ula_|video_|Equal3~1_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal2~0_combout & \ula_|video_|Equal3~0_combout ))) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|Equal2~0_combout ), - .datad(\ula_|video_|Equal3~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal3~1 .lut_mask = 16'h4000; -defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N28 -cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( -// Equation(s): -// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [0]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~0_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~0_combout ), - .datac(\ula_|video_|vga_vc [0]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N29 -dffeas \ula_|video_|vga_vc[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[0]~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N22 +// Location: LCCOMB_X32_Y30_N30 cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( // Equation(s): -// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [1]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~2_combout )))) +// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [1])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~2_combout ))))) .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~2_combout ), + .datab(\ula_|video_|Equal3~1_combout ), .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|Equal3~1_combout ), + .datad(\ula_|video_|Add1~2_combout ), .cin(gnd), .combout(\ula_|video_|vga_vc[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h3120; defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y33_N23 +// Location: FF_X32_Y30_N31 dffeas \ula_|video_|vga_vc[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|vga_vc[1]~1_combout ), @@ -18859,6 +5795,558 @@ defparam \ula_|video_|vga_vc[1] .is_wysiwyg = "true"; defparam \ula_|video_|vga_vc[1] .power_up = "low"; // synopsys translate_on +// Location: LCCOMB_X32_Y29_N4 +cycloneive_lcell_comb \ula_|video_|Add1~4 ( +// Equation(s): +// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) +// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~3 ), + .combout(\ula_|video_|Add1~4_combout ), + .cout(\ula_|video_|Add1~5 )); +// synopsys translate_off +defparam \ula_|video_|Add1~4 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N20 +cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( +// Equation(s): +// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [2]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~4_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~4_combout ), + .datac(\ula_|video_|vga_vc [2]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y30_N21 +dffeas \ula_|video_|vga_vc[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[2]~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N6 +cycloneive_lcell_comb \ula_|video_|Add1~6 ( +// Equation(s): +// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) +// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~5 ), + .combout(\ula_|video_|Add1~6_combout ), + .cout(\ula_|video_|Add1~7 )); +// synopsys translate_off +defparam \ula_|video_|Add1~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N26 +cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( +// Equation(s): +// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|Add1~6_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y30_N27 +dffeas \ula_|video_|vga_vc[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[3]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N8 +cycloneive_lcell_comb \ula_|video_|Add1~8 ( +// Equation(s): +// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) +// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~7 ), + .combout(\ula_|video_|Add1~8_combout ), + .cout(\ula_|video_|Add1~9 )); +// synopsys translate_off +defparam \ula_|video_|Add1~8 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N22 +cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( +// Equation(s): +// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~8_combout ), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y30_N23 +dffeas \ula_|video_|vga_vc[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[4]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N10 +cycloneive_lcell_comb \ula_|video_|Add1~10 ( +// Equation(s): +// \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) +// \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~9 ), + .combout(\ula_|video_|Add1~10_combout ), + .cout(\ula_|video_|Add1~11 )); +// synopsys translate_off +defparam \ula_|video_|Add1~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N8 +cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( +// Equation(s): +// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [5])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~10_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Add1~10_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[5]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y30_N9 +dffeas \ula_|video_|vga_vc[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[5]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N12 +cycloneive_lcell_comb \ula_|video_|Add1~12 ( +// Equation(s): +// \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) +// \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~11 ), + .combout(\ula_|video_|Add1~12_combout ), + .cout(\ula_|video_|Add1~13 )); +// synopsys translate_off +defparam \ula_|video_|Add1~12 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N16 +cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( +// Equation(s): +// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [6])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~12_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [6]), + .datad(\ula_|video_|Add1~12_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[6]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y30_N17 +dffeas \ula_|video_|vga_vc[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[6]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N14 +cycloneive_lcell_comb \ula_|video_|Add1~14 ( +// Equation(s): +// \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) +// \ula_|video_|Add1~15 = CARRY((!\ula_|video_|Add1~13 ) # (!\ula_|video_|vga_vc [7])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [7]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~13 ), + .combout(\ula_|video_|Add1~14_combout ), + .cout(\ula_|video_|Add1~15 )); +// synopsys translate_off +defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N22 +cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( +// Equation(s): +// \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~14_combout ), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[7]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y30_N23 +dffeas \ula_|video_|vga_vc[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[7]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N16 +cycloneive_lcell_comb \ula_|video_|Add1~16 ( +// Equation(s): +// \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) +// \ula_|video_|Add1~17 = CARRY((\ula_|video_|vga_vc [8] & !\ula_|video_|Add1~15 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [8]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~15 ), + .combout(\ula_|video_|Add1~16_combout ), + .cout(\ula_|video_|Add1~17 )); +// synopsys translate_off +defparam \ula_|video_|Add1~16 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N20 +cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( +// Equation(s): +// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~16_combout ), + .datac(\ula_|video_|vga_vc [8]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[8]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y30_N21 +dffeas \ula_|video_|vga_vc[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[8]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y29_N18 +cycloneive_lcell_comb \ula_|video_|Add1~18 ( +// Equation(s): +// \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc [9]), + .cin(\ula_|video_|Add1~17 ), + .combout(\ula_|video_|Add1~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N8 +cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( +// Equation(s): +// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [9])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~18_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [9]), + .datad(\ula_|video_|Add1~18_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y30_N9 +dffeas \ula_|video_|vga_vc[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[9]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N10 +cycloneive_lcell_comb \ula_|video_|Equal3~0 ( +// Equation(s): +// \ula_|video_|Equal3~0_combout = (!\ula_|video_|vga_vc [1] & (\ula_|video_|vga_vc [2] & (\ula_|video_|vga_vc [3] & \ula_|video_|vga_vc [0]))) + + .dataa(\ula_|video_|vga_vc [1]), + .datab(\ula_|video_|vga_vc [2]), + .datac(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|vga_vc [0]), + .cin(gnd), + .combout(\ula_|video_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal3~0 .lut_mask = 16'h4000; +defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N30 +cycloneive_lcell_comb \ula_|video_|Equal2~0 ( +// Equation(s): +// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [4]))) + + .dataa(\ula_|video_|vga_vc [8]), + .datab(\ula_|video_|vga_vc [6]), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|vga_vc [4]), + .cin(gnd), + .combout(\ula_|video_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N16 +cycloneive_lcell_comb \ula_|video_|Equal3~1 ( +// Equation(s): +// \ula_|video_|Equal3~1_combout = (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal3~0_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) + + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|Equal3~0_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Equal2~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal3~1 .lut_mask = 16'h0800; +defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N24 +cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( +// Equation(s): +// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [0])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~0_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [0]), + .datad(\ula_|video_|Add1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y30_N25 +dffeas \ula_|video_|vga_vc[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N18 +cycloneive_lcell_comb \ula_|video_|Equal2~1 ( +// Equation(s): +// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [0] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & !\ula_|video_|vga_vc [9]))) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [2]), + .datac(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|vga_vc [9]), + .cin(gnd), + .combout(\ula_|video_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal2~1 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N12 +cycloneive_lcell_comb \ula_|video_|Equal2~2 ( +// Equation(s): +// \ula_|video_|Equal2~2_combout = (\ula_|video_|Equal2~1_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout )) + + .dataa(\ula_|video_|Equal2~1_combout ), + .datab(gnd), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Equal2~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal2~2 .lut_mask = 16'h0A00; +defparam \ula_|video_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + // Location: IOIBUF_X27_Y0_N15 cycloneive_io_ibuf \SW[1]~input ( .i(SW[1]), @@ -18869,15 +6357,15 @@ defparam \SW[1]~input .bus_hold = "false"; defparam \SW[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X34_Y33_N30 +// Location: LCCOMB_X31_Y27_N2 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_vc [1] & (!\SW[1]~input_o & !\ula_|video_|vga_hc [9]))) +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_vc [1] & (!\ula_|video_|vga_hc [9] & !\SW[1]~input_o ))) .dataa(\ula_|video_|vga_hc [8]), .datab(\ula_|video_|vga_vc [1]), - .datac(\SW[1]~input_o ), - .datad(\ula_|video_|vga_hc [9]), + .datac(\ula_|video_|vga_hc [9]), + .datad(\SW[1]~input_o ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), .cout()); @@ -18886,18144 +6374,249 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .lut_mask = 16'h0001; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( +// Location: LCCOMB_X30_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( // Equation(s): -// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal79~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N16 -cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( -// Equation(s): -// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|interrupts_|DFFE_instIFF2~q -// ))))) # (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal79~0_combout ), - .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hB8F0; -defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N28 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|interrupts_|DFFE_inst44~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h7733; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G16 -cycloneive_clkctrl \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: FF_X35_Y17_N17 -dffeas \z80_|interrupts_|DFFE_instIFF2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|DFFE_instIFF2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N2 -cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( -// Equation(s): -// \z80_|interrupts_|iff1~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|interrupts_|iff1~q ), - .datac(\z80_|pla_decode_|Equal79~0_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|interrupts_|iff1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hEC4C; -defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N18 -cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( -// Equation(s): -// \z80_|interrupts_|iff1~1_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|pla_decode_|Equal38~2_combout & ((\z80_|interrupts_|iff1~0_combout ))))) # -// (!\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|interrupts_|iff1~0_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|interrupts_|DFFE_instIFF2~q ), - .datac(\z80_|pla_decode_|Equal38~2_combout ), - .datad(\z80_|interrupts_|iff1~0_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|iff1~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hDF80; -defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N12 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|interrupts_|DFFE_inst44~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFF3; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y17_N19 -dffeas \z80_|interrupts_|iff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|iff1~1_combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|iff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|iff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Equal2~1 ( -// Equation(s): -// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [3] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [0]))) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal2~1 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Equal2~2 ( -// Equation(s): -// \ula_|video_|Equal2~2_combout = (\ula_|video_|Equal2~1_combout & (\ula_|video_|Equal2~0_combout & !\ula_|video_|vga_vc [5])) - - .dataa(gnd), - .datab(\ula_|video_|Equal2~1_combout ), - .datac(\ula_|video_|Equal2~0_combout ), - .datad(\ula_|video_|vga_vc [5]), - .cin(gnd), - .combout(\ula_|video_|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal2~2 .lut_mask = 16'h00C0; -defparam \ula_|video_|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y31_N28 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (!\ula_|video_|vga_hc [7] & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & (\z80_|interrupts_|iff1~q & \ula_|video_|Equal2~2_combout ))) - - .dataa(\ula_|video_|vga_hc [7]), - .datab(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), - .datac(\z80_|interrupts_|iff1~q ), - .datad(\ula_|video_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h4000; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y31_N29 -dffeas \z80_|interrupts_|int_armed ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), - .asdata(vcc), - .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|int_armed~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; -defparam \z80_|interrupts_|int_armed .power_up = "low"; -// synopsys translate_on - -// Location: FF_X32_Y15_N11 -dffeas \z80_|interrupts_|DFFE_inst44 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|interrupts_|int_armed~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|interrupts_|test1~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|DFFE_inst44~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~38 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~38_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|decode_state_|in_halt~q ) # (\z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .datab(gnd), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~38 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|pc_inc_hold~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~91 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~91_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~91 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~45 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~45_combout = (\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) # (!\z80_|pla_decode_|Equal19~0_combout & -// (((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~45 .lut_mask = 16'hF888; -defparam \z80_|execute_|pc_inc_hold~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~44 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~44_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((!\z80_|execute_|pc_inc_hold~49_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|pc_inc_hold~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~44 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|pc_inc_hold~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~46 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~46_combout = (\z80_|execute_|pc_inc_hold~45_combout ) # ((\z80_|execute_|pc_inc_hold~44_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~49_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~45_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|pc_inc_hold~44_combout ), - .datad(\z80_|execute_|pc_inc_hold~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~46 .lut_mask = 16'hFAFE; -defparam \z80_|execute_|pc_inc_hold~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~37 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~37_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|pc_inc_hold~29_combout ) # ((\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & -// (\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~37 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|pc_inc_hold~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~50 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~50_combout = (\z80_|execute_|pc_inc_hold~37_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|execute_|pc_inc_hold~37_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~50 .lut_mask = 16'hECCC; -defparam \z80_|execute_|pc_inc_hold~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~33_combout = (\z80_|execute_|ctl_mRead~10_combout & (((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|pla_decode_|Equal6~1_combout & -// ((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~2_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|pc_inc_hold~28_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|execute_|pc_inc_hold~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hECEE; -defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|execute_|ctl_mRead~15_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hEEA0; -defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|execute_|pc_inc_hold~33_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # ((\z80_|execute_|pc_inc_hold~31_combout ) # (\z80_|execute_|pc_inc_hold~32_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~33_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|pc_inc_hold~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~51 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~51_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ixy_d~15_combout ), .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~51_combout ), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~51 .lut_mask = 16'h57FF; -defparam \z80_|execute_|pc_inc_hold~51 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( +// Location: LCCOMB_X37_Y6_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) +// \z80_|execute_|ctl_mWrite~4_combout = (\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~30_combout ), + .combout(\z80_|execute_|ctl_mWrite~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~52 ( +// Location: LCCOMB_X36_Y6_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal0~0 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~52_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~52 .lut_mask = 16'hA800; -defparam \z80_|execute_|pc_inc_hold~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~35_combout = (!\z80_|execute_|pc_inc_hold~34_combout & (\z80_|execute_|pc_inc_hold~51_combout & (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~52_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~34_combout ), - .datab(\z80_|execute_|pc_inc_hold~51_combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|pc_inc_hold~52_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'h0040; -defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~36_combout = ((\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|execute_|pc_inc_hold~35_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hCF8F; -defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~44_combout = (((!\z80_|pla_decode_|Equal21~0_combout & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ixy_d~10_combout )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~45_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_inc_cy~44_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~50_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_inc_cy~44_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~43 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~43_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~43 .lut_mask = 16'hC080; -defparam \z80_|execute_|pc_inc_hold~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~71_combout = (\z80_|execute_|ctl_inc_cy~91_combout & (!\z80_|execute_|pc_inc_hold~46_combout & (\z80_|execute_|ctl_inc_cy~45_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~91_combout ), - .datab(\z80_|execute_|pc_inc_hold~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~45_combout ), - .datad(\z80_|execute_|pc_inc_hold~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~73_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~72_combout & \z80_|execute_|ctl_inc_cy~71_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_inc_cy~72_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~71_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_mWrite~16_combout & ((\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'h8C00; -defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~53 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~53_combout = (\z80_|pla_decode_|Equal11~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~53 .lut_mask = 16'hE000; -defparam \z80_|execute_|pc_inc_hold~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~39 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~39_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~53_combout & (\z80_|execute_|pc_inc_hold~35_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~50_combout ), - .datab(\z80_|execute_|pc_inc_hold~53_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~39 .lut_mask = 16'h0010; -defparam \z80_|execute_|pc_inc_hold~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~47 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~47_combout = (\z80_|execute_|pc_inc_hold~46_combout ) # ((\z80_|execute_|pc_inc_hold~43_combout ) # ((!\z80_|execute_|ctl_inc_cy~44_combout ) # (!\z80_|execute_|pc_inc_hold~39_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~46_combout ), - .datab(\z80_|execute_|pc_inc_hold~43_combout ), - .datac(\z80_|execute_|pc_inc_hold~39_combout ), - .datad(\z80_|execute_|ctl_inc_cy~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~47 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|pc_inc_hold~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~74_combout = (((!\z80_|execute_|ctl_inc_cy~40_combout ) # (!\z80_|execute_|ctl_inc_cy~34_combout )) # (!\z80_|execute_|ctl_inc_cy~35_combout )) # (!\z80_|execute_|ctl_inc_cy~43_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~43_combout ), - .datab(\z80_|execute_|ctl_inc_cy~35_combout ), - .datac(\z80_|execute_|ctl_inc_cy~34_combout ), - .datad(\z80_|execute_|ctl_inc_cy~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~78_combout = ((\z80_|execute_|ctl_inc_cy~74_combout ) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~39_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~39_combout ), - .datac(\z80_|execute_|ctl_inc_cy~77_combout ), - .datad(\z80_|execute_|ctl_inc_cy~74_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (((!\z80_|execute_|pc_inc_hold~47_combout & \z80_|execute_|ctl_inc_cy~91_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~47_combout ), - .datab(\z80_|execute_|ctl_inc_cy~78_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~91_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'h4C0C; -defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~45_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|pc_inc_hold~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal19~1_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hA800; -defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~82_combout = (\z80_|execute_|ctl_inc_cy~81_combout ) # ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~81_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|pc_inc_hold~47_combout & (!\z80_|execute_|pc_inc_hold~38_combout & ((\z80_|execute_|ctl_inc_cy~82_combout ) # (!\z80_|execute_|ctl_inc_cy~38_combout )))) # (!\z80_|execute_|pc_inc_hold~47_combout -// & ((\z80_|execute_|ctl_inc_cy~82_combout ) # ((!\z80_|execute_|ctl_inc_cy~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~47_combout ), - .datab(\z80_|execute_|ctl_inc_cy~82_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'h4C5F; -defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~84_combout = (\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~79_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|execute_|ctl_inc_cy~83_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~42 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~42_combout = ((\z80_|execute_|pc_inc_hold~34_combout ) # (\z80_|execute_|pc_inc_hold~52_combout )) # (!\z80_|execute_|pc_inc_hold~30_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|pc_inc_hold~52_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~42 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|pc_inc_hold~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~90 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~90_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~8_combout ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~90 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~41 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~41_combout = (\z80_|execute_|pc_inc_hold~31_combout ) # ((\z80_|execute_|pc_inc_hold~32_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~31_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|execute_|pc_inc_hold~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~41 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|pc_inc_hold~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~66_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'h0004; -defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~66_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~20_combout & !\z80_|execute_|pc_inc_hold~31_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|ctl_inc_cy~66_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hAA02; -defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~67_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|pc_inc_hold~41_combout & \z80_|execute_|ctl_mRead~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|pc_inc_hold~41_combout ), - .datac(\z80_|execute_|ctl_inc_cy~67_combout ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hF2F0; -defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~64_combout = (!\z80_|execute_|pc_inc_hold~31_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|pc_inc_hold~34_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_sw_4u~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h0C08; -defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~65_combout = (\z80_|execute_|ctl_inc_cy~63_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((\z80_|execute_|ctl_inc_cy~64_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|execute_|ctl_inc_cy~64_combout ), - .datad(\z80_|execute_|ctl_inc_cy~63_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hFFC4; -defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|ctl_inc_cy~68_combout ) # ((\z80_|execute_|ctl_inc_cy~65_combout ) # ((!\z80_|execute_|pc_inc_hold~42_combout & !\z80_|execute_|ctl_inc_cy~90_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~42_combout ), - .datab(\z80_|execute_|ctl_inc_cy~90_combout ), - .datac(\z80_|execute_|ctl_inc_cy~68_combout ), - .datad(\z80_|execute_|ctl_inc_cy~65_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~49_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_inc_cy~92_combout ) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_inc_cy~92_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~50_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) # (!\z80_|execute_|ixy_d~9_combout & -// (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_mRead~11_combout )) # (!\z80_|execute_|ctl_inc_cy~94_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|execute_|ctl_inc_cy~94_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_inc_cy~51_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~51_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~36_combout = ((!\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_mWrite~4_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~36_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_sw_2u~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~54_combout = ((\z80_|execute_|ctl_inc_cy~49_combout ) # ((\z80_|execute_|ctl_inc_cy~52_combout ) # (!\z80_|execute_|ctl_inc_cy~37_combout ))) # (!\z80_|execute_|ctl_inc_cy~53_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), - .datab(\z80_|execute_|ctl_inc_cy~49_combout ), - .datac(\z80_|execute_|ctl_inc_cy~52_combout ), - .datad(\z80_|execute_|ctl_inc_cy~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~41_combout = (!\z80_|execute_|ctl_mRead~17_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'h0045; -defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~58_combout = (\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_inc_cy~41_combout )) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~41_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'hEEFF; -defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout ) # ((\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & -// ((\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~56_combout = (((!\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|fMRead~3_combout ) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~89 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~89_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~89 .lut_mask = 16'hA020; -defparam \z80_|execute_|ctl_inc_cy~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_inc_cy~56_combout ) # (\z80_|execute_|ctl_inc_cy~89_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ctl_inc_cy~55_combout ), - .datac(\z80_|execute_|ctl_inc_cy~56_combout ), - .datad(\z80_|execute_|ctl_inc_cy~89_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_inc_cy~57_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~58_combout ) # (!\z80_|execute_|fMRead~5_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_inc_cy~58_combout ), - .datac(\z80_|execute_|fMRead~5_combout ), - .datad(\z80_|execute_|ctl_inc_cy~57_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'hFF8A; -defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~60_combout = (\z80_|execute_|pc_inc_hold~38_combout & (\z80_|execute_|pc_inc_hold~35_combout & (\z80_|execute_|ctl_inc_cy~54_combout ))) # (!\z80_|execute_|pc_inc_hold~38_combout & (((\z80_|execute_|ctl_inc_cy~54_combout ) # -// (\z80_|execute_|ctl_inc_cy~59_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|pc_inc_hold~35_combout ), - .datac(\z80_|execute_|ctl_inc_cy~54_combout ), - .datad(\z80_|execute_|ctl_inc_cy~59_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'hD5D0; -defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|pc_inc_hold~50_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|pc_inc_hold~50_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~88_combout = (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ) # ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~47_combout ) # ((\z80_|execute_|ctl_inc_cy~88_combout & ((\z80_|execute_|pc_inc_hold~39_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~39_combout ), - .datab(\z80_|execute_|ctl_inc_cy~47_combout ), - .datac(\z80_|execute_|ctl_inc_cy~88_combout ), - .datad(\z80_|execute_|pc_inc_hold~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'hECFC; -defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~40 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~40_combout = (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~34_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~40 .lut_mask = 16'h0C0C; -defparam \z80_|execute_|pc_inc_hold~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~61_combout = (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h3200; -defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~62_combout = (\z80_|execute_|ctl_inc_cy~61_combout ) # ((!\z80_|execute_|ctl_inc_cy~42_combout & ((\z80_|execute_|pc_inc_hold~40_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|pc_inc_hold~40_combout ), - .datac(\z80_|execute_|ctl_inc_cy~61_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hF0FD; -defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~69_combout ) # ((\z80_|execute_|ctl_inc_cy~60_combout ) # ((\z80_|execute_|ctl_inc_cy~48_combout ) # (\z80_|execute_|ctl_inc_cy~62_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), - .datab(\z80_|execute_|ctl_inc_cy~60_combout ), - .datac(\z80_|execute_|ctl_inc_cy~48_combout ), - .datad(\z80_|execute_|ctl_inc_cy~62_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~85_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~84_combout ) # (\z80_|execute_|ctl_inc_cy~70_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), - .datab(\z80_|execute_|ctl_inc_cy~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~84_combout ), - .datad(\z80_|execute_|ctl_inc_cy~70_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (\z80_|execute_|ctl_inc_cy~85_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_cy~85_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hAF2F; -defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( -// Equation(s): -// \z80_|address_latch_|abusz [0] = (\z80_|reg_file_|db_lo_as[0]~3_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [0]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|Q[0]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[0]~feeder_combout = \z80_|address_latch_|abusz [0] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [0]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N23 -dffeas \z80_|address_latch_|Q[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[0]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X31_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[1]~32_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .datad(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_cy~85_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h6A6A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hAF2F; -defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( -// Equation(s): -// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [1]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h3300; -defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N19 -dffeas \z80_|address_latch_|Q[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [1]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout = \z80_|address_latch_|Q [1] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|address_latch_|Q [1]), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .lut_mask = 16'h0F87; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & (\z80_|execute_|ctl_inc_cy~85_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hF575; -defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( -// Equation(s): -// \z80_|address_latch_|abusz [2] = (\z80_|reg_file_|db_lo_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [2]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h00AA; -defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N14 -cycloneive_lcell_comb \z80_|address_latch_|Q[2]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[2]~feeder_combout = \z80_|address_latch_|abusz [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [2]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N15 -dffeas \z80_|address_latch_|Q[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[2]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|address_latch_|Q [2] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|address_latch_|Q [2]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h40BF; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~86_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), - .datab(\z80_|execute_|ctl_inc_cy~79_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|execute_|ctl_inc_cy~83_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~86_combout ) # -// (\z80_|execute_|ctl_inc_cy~70_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datab(\z80_|execute_|ctl_inc_cy~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~86_combout ), - .datad(\z80_|execute_|ctl_inc_cy~70_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hAAA8; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~11_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout )) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout = (\z80_|execute_|ctl_inc_cy~85_combout & ((\z80_|address_latch_|Q [1] & (!\z80_|execute_|ctl_inc_dec~11_combout & \z80_|address_latch_|Q [0])) # (!\z80_|address_latch_|Q -// [1] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [0])))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_cy~85_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .lut_mask = 16'h2400; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout -// ))) - - .dataa(gnd), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h3FC0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N11 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N5 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'h3F3B; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~29_combout ) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|setM1~29_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_al_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'hB3F3; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & !\z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ) # ((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hF7F5; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = ((\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|execute_|setM1~46_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datad(\z80_|execute_|setM1~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'h5DDD; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ) # (!\z80_|execute_|ctl_reg_gp_we~2_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~40 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[3]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~41 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[3]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hB3FF; -defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~12_combout = (\z80_|execute_|ctl_reg_in_hi~11_combout ) # (((!\z80_|execute_|ctl_reg_in_hi~4_combout ) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~44_combout = (\z80_|alu_|db[3]~11_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[3]~11_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~44 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~48_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h4444; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h4000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|execute_|ctl_reg_gp_we~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~43_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h5450; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # (\z80_|execute_|ctl_reg_sys_we_lo~3_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hFB33; -defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~combout = ((\z80_|reg_control_|reg_sys_we_hi~0_combout ) # (\z80_|execute_|ctl_reg_sys_we~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF3; -defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~45 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[3]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0002; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h0400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0008; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~42_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~42 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[3]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~46_combout = (\z80_|reg_file_|gdfx_temp1[3]~44_combout & (\z80_|reg_file_|gdfx_temp1[3]~43_combout & (\z80_|reg_file_|gdfx_temp1[3]~45_combout & \z80_|reg_file_|gdfx_temp1[3]~42_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~46 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~47_combout = (\z80_|reg_file_|gdfx_temp1[3]~40_combout & (\z80_|reg_file_|gdfx_temp1[3]~41_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout & \z80_|reg_file_|gdfx_temp1[3]~46_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~47 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFF8; -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~16_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|reg_control_|reg_sel_pc~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N11 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|alu_|db[1]~13_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[1]~13_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[1]~13_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~21_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~12_combout & (\z80_|reg_file_|gdfx_temp1[1]~10_combout & \z80_|reg_file_|gdfx_temp1[1]~11_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~8_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout & (\z80_|reg_file_|gdfx_temp1[1]~14_combout & \z80_|reg_file_|gdfx_temp1[1]~9_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .datac(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (!\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_control_|reg_sys_we_lo~combout ) # ((!\z80_|execute_|ctl_reg_sel_ir~1_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'h8AAA; -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_file_|gdfx_temp1[1]~21_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[1]~21_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|reg_control_|reg_sel_pc~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # (\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|address_latch_|Q [7] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [8]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'h96CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|alu_|db[0]~19_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[0]~19_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[0]~19_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~24_combout & (\z80_|reg_file_|gdfx_temp1[0]~26_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & \z80_|reg_file_|gdfx_temp1[0]~27_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|gdfx_temp1[0]~28_combout & \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .datad(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( -// Equation(s): -// \z80_|address_latch_|abusz [8] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[0]~6_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [8]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N9 -dffeas \z80_|address_latch_|Q[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [8]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N18 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|address_latch_|Q [7] & (\z80_|address_latch_|Q [8] & !\z80_|execute_|ctl_inc_dec~11_combout -// )) # (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [8] & \z80_|execute_|ctl_inc_dec~11_combout )))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [8]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h1800; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N24 -cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( -// Equation(s): -// \z80_|address_latch_|abusz [9] = (\z80_|reg_file_|db_hi_as[1]~3_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [9]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|Q[9]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[9]~feeder_combout = \z80_|address_latch_|abusz [9] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [9]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[9]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[9]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[9]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N5 -dffeas \z80_|address_latch_|Q[9] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[9]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ -// (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [9]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~32 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~35_combout = (\z80_|alu_|db[2]~15_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[2]~15_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[2]~15_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~35 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~34 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~33_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~33 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N1 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~36 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~37_combout = (\z80_|reg_file_|gdfx_temp1[2]~35_combout & (\z80_|reg_file_|gdfx_temp1[2]~34_combout & (\z80_|reg_file_|gdfx_temp1[2]~33_combout & \z80_|reg_file_|gdfx_temp1[2]~36_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~37 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~31 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~38_combout = (\z80_|reg_file_|gdfx_temp1[2]~32_combout & (\z80_|reg_file_|gdfx_temp1[2]~37_combout & (\z80_|reg_file_|gdfx_temp1[2]~31_combout & \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~38 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~39_combout = ((\z80_|reg_file_|gdfx_temp1[2]~38_combout & ((\z80_|reg_file_|db_hi_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~39 .lut_mask = 16'h8FAF; -defparam \z80_|reg_file_|gdfx_temp1[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp1[2]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[2]~39_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~7 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~8_combout = (\z80_|reg_file_|db_hi_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~7_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~8 .lut_mask = 16'hCC44; -defparam \z80_|reg_file_|db_hi_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~9 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~9_combout = ((\z80_|reg_file_|db_hi_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[2]~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~9 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N0 -cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( -// Equation(s): -// \z80_|address_latch_|abusz [10] = (\z80_|reg_file_|db_hi_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [10]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|Q[10]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[10]~feeder_combout = \z80_|address_latch_|abusz [10] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [10]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[10]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[10]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N27 -dffeas \z80_|address_latch_|Q[10] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[10]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [10] & (\z80_|address_latch_|Q [9] & -// !\z80_|execute_|ctl_inc_dec~11_combout )) # (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [9] & \z80_|execute_|ctl_inc_dec~11_combout )))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [9]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h1800; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( -// Equation(s): -// \z80_|address_latch_|abusz [11] = (\z80_|reg_file_|db_hi_as[3]~12_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h00CC; -defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N15 -dffeas \z80_|address_latch_|Q[11] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [11]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout $ (\z80_|address_latch_|Q [11]) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(gnd), - .datac(\z80_|address_latch_|Q [11]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h5A5A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp1[3]~48_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[3]~48_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~11 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~11_combout = (\z80_|reg_file_|db_hi_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[3]~10_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~11 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|db_hi_as[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~12_combout = ((\z80_|reg_file_|db_hi_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[3]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~12 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~48_combout = ((\z80_|reg_file_|gdfx_temp1[3]~47_combout & ((\z80_|reg_file_|db_hi_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~48 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'h888A; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hC0E0; -defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[3]~8_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N7 -dffeas \z80_|alu_|op1_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~3 ( -// Equation(s): -// \z80_|alu_|alu_op1[3]~3_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])) - - .dataa(gnd), - .datab(\z80_|alu_|op1_high [3]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[3]~3 .lut_mask = 16'hF0CC; -defparam \z80_|alu_|alu_op1[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [2])))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|alu_|alu_op2[2]~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0305; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = ((\z80_|pla_decode_|Equal8~0_combout & (\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mWrite~2_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|pla_decode_|Equal8~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'hAAFB; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~0_combout = (\z80_|pla_decode_|Equal1~5_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~5_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) # (((\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = ((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) # -// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .lut_mask = 16'h5050; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_zero~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFFFA; -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N1 -dffeas \z80_|alu_|op2_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[1]~20_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N23 -dffeas \z80_|alu_|op1_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))))) - - .dataa(\z80_|alu_|op1_low [1]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'h8C80; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|alu_|db_low[1]~17_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .datac(\z80_|alu_|db_low[1]~17_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N21 -dffeas \z80_|alu_|op2_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~20_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal68~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal68~2_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .lut_mask = 16'h0D0F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|execute_|ctl_state_alu~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # ((\z80_|execute_|ctl_state_alu~11_combout ) # (!\z80_|execute_|ctl_state_alu~8_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~9_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datac(\z80_|execute_|ctl_state_alu~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~18_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~12_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h7577; -defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) +// \z80_|pla_decode_|Equal0~0_combout = (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~4_combout ) .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal61~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal61~2_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M4_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'hFC00; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~20_combout & (\z80_|execute_|ctl_alu_core_hf~18_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~21_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~17_combout & (((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~4_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout -// ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & (\z80_|execute_|ctl_alu_core_S~4_combout & \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_ir_we~11_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .lut_mask = 16'hC4CC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~20_combout = ((\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout ))) # (!\z80_|execute_|ctl_state_alu~12_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal71~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal71~2_combout = (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~12_combout & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal71~2 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_alu_core_hf~20_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & !\z80_|pla_decode_|Equal71~2_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|pla_decode_|Equal71~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'h0080; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~31_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~9_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'h1333; -defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (\z80_|pla_decode_|Equal21~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal3~0_combout & -// ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'hFCA8; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout = (\z80_|pla_decode_|Equal13~1_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal13~1_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N16 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & \z80_|pla_decode_|Equal63~0_combout -// ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'hFFEC; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (\z80_|execute_|ctl_alu_op_low~31_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & !\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'h0080; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal72~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal72~2_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal72~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal72~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal72~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal73~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|pla_decode_|Equal61~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal61~2_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (!\z80_|pla_decode_|Equal72~2_combout & (!\z80_|pla_decode_|Equal73~2_combout & \z80_|execute_|ctl_flags_nf_we~0_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datab(\z80_|pla_decode_|Equal72~2_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~3_combout = ((\z80_|execute_|ctl_flags_nf_we~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout )) # (!\z80_|execute_|ctl_flags_nf_we~1_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFAFF; -defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|pla_decode_|Equal48~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|execute_|ctl_flags_sz_we~5_combout & \z80_|execute_|ctl_alu_core_R~0_combout )))) # -// (!\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_flags_sz_we~5_combout & ((\z80_|execute_|ctl_alu_core_R~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hECA0; -defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~4_combout = (((\z80_|execute_|ctl_flags_nf_we~3_combout ) # (\z80_|execute_|ctl_flags_sz_we~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~12_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~15 ( -// Equation(s): -// \z80_|execute_|setM1~15_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_state_alu~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~15 .lut_mask = 16'h5000; -defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~16 ( -// Equation(s): -// \z80_|execute_|setM1~16_combout = (\z80_|execute_|setM1~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~31_combout ))) - - .dataa(\z80_|execute_|setM1~15_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0200; -defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|setM1~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|setM1~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & \z80_|execute_|ctl_alu_oe~5_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (\z80_|execute_|ctl_flags_xy_we~7_combout & \z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) - - .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~7_combout ), .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .combout(\z80_|pla_decode_|Equal0~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal0~0 .lut_mask = 16'h5500; +defparam \z80_|pla_decode_|Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 ( +// Location: LCCOMB_X40_Y13_N8 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( // Equation(s): -// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal11~1_combout & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) +// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal11~1_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), + .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88C0; +defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), - .cout()); +// Location: FF_X40_Y13_N9 +dffeas \z80_|sequencer_|DFFE_M3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M3_ff~q ), + .prn(vcc)); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFBAA; -defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~7_combout = (\z80_|execute_|ctl_alu_core_R~1_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_flags_alu~18_combout )) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~7 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_flags_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~8 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~8_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal56~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~8 .lut_mask = 16'h7F00; -defparam \z80_|reg_control_|reg_sys_we_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~8_combout = ((\z80_|execute_|ctl_flags_alu~7_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~8_combout ) # (!\z80_|execute_|ctl_flags_alu~16_combout ))) # (!\z80_|execute_|ctl_flags_alu~6_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), - .datab(\z80_|execute_|ctl_flags_alu~7_combout ), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~8 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_alu_op_low~10_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal20~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~10_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'h0070; -defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~13_combout = (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_flags_xy_we~16_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_alu~12_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datac(\z80_|execute_|ctl_sw_2d~4_combout ), - .datad(\z80_|execute_|ctl_flags_alu~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_alu_op_low~15_combout & (\z80_|execute_|ctl_sw_4u~1_combout & \z80_|execute_|ctl_flags_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|execute_|ctl_flags_alu~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~15_combout = ((\z80_|execute_|ctl_flags_alu~8_combout ) # ((!\z80_|execute_|ctl_flags_alu~11_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_alu~8_combout ), - .datac(\z80_|execute_|ctl_flags_alu~14_combout ), - .datad(\z80_|execute_|ctl_flags_alu~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N12 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFCEC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~19_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ) # ((\z80_|alu_control_|db[1]~26_combout & \z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), - .datac(\z80_|alu_control_|db[1]~26_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEEE; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; // synopsys translate_on // Location: LCCOMB_X37_Y9_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( +cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( // Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|execute_|ctl_flags_alu~15_combout & \z80_|alu_|db_high[3]~8_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) +// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFFB3; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'h3070; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .lut_mask = 16'h0800; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) - - .dataa(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .lut_mask = 16'hD850; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y9_N27 -dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) # (!\z80_|sequencer_|DFFE_M2_ff~q & -// (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'h7707; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = ((\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'hB3BB; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~11_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~18_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~15_combout & \z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .lut_mask = 16'hFDF5; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal13~2_combout & \z80_|sequencer_|DFFE_M3_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~1 ( -// Equation(s): -// \z80_|alu_|alu_op2[1]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [1])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [1]))))) - - .dataa(\z80_|alu_|op2_high [1]), - .datab(\z80_|alu_|op2_low [1]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[1]~1 .lut_mask = 16'h5A3C; -defparam \z80_|alu_|alu_op2[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high -// [1]))))) - - .dataa(\z80_|alu_|alu_op2[1]~1_combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h1015; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~9_combout = (((\z80_|pla_decode_|Equal71~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_core_S~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), - .datad(\z80_|pla_decode_|Equal71~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout = (\z80_|alu_|db_high[0]~26_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|alu_|db_low[0]~23_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # -// (!\z80_|alu_|db_high[0]~26_combout & (\z80_|alu_|db_low[0]~23_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout ))) - - .dataa(\z80_|alu_|db_high[0]~26_combout ), - .datab(\z80_|alu_|db_low[0]~23_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .lut_mask = 16'hEAC0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) - - .dataa(gnd), + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N7 -dffeas \z80_|alu_|op2_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( -// Equation(s): -// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|alu_|op2_high [0]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h3C5A; -defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~12 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & ((\z80_|ir_|opcode [3]) # ((!\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal62~2_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .lut_mask = 16'hB0F0; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & \z80_|execute_|ctl_alu_core_S~7_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~9_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # -// (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h37FF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_alu_core_hf~20_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .datac(gnd), .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .combout(\z80_|execute_|ixy_d~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( +// Location: LCCOMB_X36_Y6_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 ( // Equation(s): -// \z80_|execute_|ctl_alu_core_hf~22_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~21_combout )) # (!\z80_|execute_|ctl_alu_core_hf~18_combout ) +// \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal0~0_combout & (\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [1]))) - .dataa(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal0~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'hD5FF; -defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( +// Location: LCCOMB_X36_Y6_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( // Equation(s): -// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hA0E0; -defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (((\z80_|execute_|ctl_alu_op_low~22_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~29_combout = (\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~23_combout = (\z80_|execute_|ctl_alu_core_hf~22_combout & (((\z80_|execute_|ctl_alu_core_hf~19_combout & !\z80_|execute_|ctl_alu_op_low~29_combout )) # (!\z80_|execute_|ctl_alu_op_low~28_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~22_combout & (\z80_|execute_|ctl_alu_core_hf~19_combout & (!\z80_|execute_|ctl_alu_op_low~29_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h0CAE; -defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|pla_decode_|Equal39~0_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal40~1_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hFF30; -defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~25_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'hEFEE; -defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'hA0A8; -defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~26_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hDFCC; -defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~28_combout = (\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_alu_op_low~20_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h22F2; -defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (((\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datab(\z80_|execute_|ctl_state_alu~13_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout & !\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~7_combout & -// ((!\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hC0CA; -defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~43_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|ctl_mRead~6_combout & (\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # -// ((\z80_|execute_|ctl_mRead~6_combout & \z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~43 .lut_mask = 16'hD5C0; -defparam \z80_|execute_|ctl_alu_core_hf~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~33_combout = (!\z80_|execute_|ctl_alu_core_hf~43_combout & ((\z80_|execute_|ctl_alu_core_hf~32_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~32_combout & (\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'h00E8; -defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~42 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~42_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~42 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_alu_core_hf~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~42_combout & ((\z80_|execute_|ctl_alu_core_hf~34_combout ) # (\z80_|execute_|ctl_alu_core_hf~33_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~41_combout = (!\z80_|execute_|ctl_state_alu~4_combout & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal10~0_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~41 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_alu_core_hf~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & -// (\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~10_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal11~1_combout & \z80_|execute_|ctl_mWrite~2_combout ))) +// \z80_|pla_decode_|Equal33~0_combout = (\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0])) .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal11~1_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~31_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_mWrite~10_combout & ((\z80_|execute_|ctl_alu_core_hf~41_combout ) # (\z80_|execute_|ctl_alu_core_hf~30_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~41_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'h0054; -defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~44_combout = (\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~44 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_core_hf~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~29_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & ((\z80_|execute_|ctl_alu_core_hf~44_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~44_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'h0E0A; -defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # ((!\z80_|execute_|ctl_alu_op_low~30_combout & \z80_|execute_|ctl_alu_core_hf~35_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'hFFF4; -defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~39_combout = (\z80_|execute_|ctl_alu_core_hf~28_combout ) # ((\z80_|execute_|ctl_alu_core_hf~36_combout ) # ((\z80_|execute_|ctl_alu_core_hf~38_combout & !\z80_|execute_|ctl_alu_op_low~24_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~39 .lut_mask = 16'hFCFE; -defparam \z80_|execute_|ctl_alu_core_hf~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~40_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((\z80_|execute_|ctl_alu_core_hf~39_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~40 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_alu_core_hf~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datad(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~combout = (\z80_|execute_|ctl_alu_core_R~2_combout ) # (((\z80_|pla_decode_|Equal73~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_R~2_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .lut_mask = 16'hC0D0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_high[3]~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), - .datad(\z80_|alu_|db_high[3]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .lut_mask = 16'h5450; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N9 -dffeas \z80_|alu_|op2_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [3]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ) # ((\z80_|alu_|db_low[3]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), - .datac(\z80_|alu_|db_low[3]~25_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N19 -dffeas \z80_|alu_|op2_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~2 ( -// Equation(s): -// \z80_|alu_|alu_op2[3]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [3])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [3]))))) - - .dataa(\z80_|alu_|op2_high [3]), - .datab(\z80_|alu_|op2_low [3]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[3]~2 .lut_mask = 16'h5A3C; -defparam \z80_|alu_|alu_op2[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[3]~3_combout & \z80_|alu_|alu_op2[3]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|alu_|alu_op1[3]~3_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datac(\z80_|alu_|alu_op2[3]~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [3])))) - - .dataa(\z80_|alu_|alu_op2[3]~2_combout ), - .datab(\z80_|alu_|op1_high [3]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0511; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_R~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hAFAE; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # -// (!\z80_|execute_|ctl_flags_bus~combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'h8F88; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((\z80_|pla_decode_|Equal10~0_combout & -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hFC88; -defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~14_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~14_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) - - .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datad(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hCCE4; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N7 -dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|pla_decode_|Equal52~1_combout ) # (\z80_|execute_|ctl_state_alu~14_combout )) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~12_combout = ((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_alu_op_low~12_combout ))) # (!\z80_|execute_|ctl_flags_hf_cpl~10_combout ) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .datab(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~13_combout = (\z80_|execute_|ctl_flags_hf_cpl~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|alu_flags_|DFFE_inst_latch_nf~q ))) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~13 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_hf_cpl~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N8 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( -// Equation(s): -// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~13_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h559A; -defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N30 -cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( -// Equation(s): -// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~40_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~40_combout & (\z80_|alu_flags_|flags_cf~combout )) - - .dataa(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .datab(\z80_|alu_flags_|flags_cf~combout ), + .datab(\z80_|ir_|opcode [1]), .datac(gnd), - .datad(\z80_|alu_flags_|flags_hf~combout ), + .datad(\z80_|ir_|opcode [0]), .cin(gnd), - .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .combout(\z80_|pla_decode_|Equal33~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hEE44; -defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_control_|alu_core_cf_in~0_combout & \z80_|alu_|alu_op1[0]~1_combout )))) -// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|alu_|alu_op1[0]~1_combout )))) - - .dataa(\z80_|alu_|alu_op2[0]~3_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op1[0]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( -// Equation(s): -// \z80_|alu_|db_high[0]~23_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~25_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[3]~11_combout ), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hE4E4; -defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( -// Equation(s): -// \z80_|address_latch_|abusz [12] = (\z80_|reg_file_|db_hi_as[4]~18_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [12]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|Q[12]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[12]~feeder_combout = \z80_|address_latch_|abusz [12] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [12]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[12]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[12]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[12]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N15 -dffeas \z80_|address_latch_|Q[12] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[12]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ -// (\z80_|address_latch_|Q [11]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hD278; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~16 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~16_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~16 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|db_hi_as[4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~17 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~17_combout = (\z80_|reg_file_|db_hi_as[4]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .datad(\z80_|reg_file_|db_hi_as[4]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~17 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|db_hi_as[4]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~18 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~18_combout = ((\z80_|reg_file_|db_hi_as[4]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[4]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~18 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[4]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N11 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~62_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [4] & ((\z80_|alu_|db[4]~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~12_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[4]~17_combout )) # (!\z80_|execute_|ctl_reg_in_hi~12_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .datad(\z80_|alu_|db[4]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~62 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y11_N29 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~63_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~63 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[4]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N23 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~61_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~61 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp1[4]~66_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~60_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~60 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~64_combout = (\z80_|reg_file_|gdfx_temp1[4]~62_combout & (\z80_|reg_file_|gdfx_temp1[4]~63_combout & (\z80_|reg_file_|gdfx_temp1[4]~61_combout & \z80_|reg_file_|gdfx_temp1[4]~60_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~64 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~59 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~58 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~65_combout = (\z80_|reg_file_|gdfx_temp1[4]~64_combout & (\z80_|reg_file_|gdfx_temp1[4]~59_combout & (\z80_|reg_file_|gdfx_temp1[4]~58_combout & \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~65 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~66_combout = ((\z80_|reg_file_|gdfx_temp1[4]~65_combout & ((\z80_|reg_file_|db_hi_as[4]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~66 .lut_mask = 16'hD5F5; -defparam \z80_|reg_file_|gdfx_temp1[4]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db[4]~16 ( -// Equation(s): -// \z80_|alu_|db[4]~16_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[4]~32_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[4]~32_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~16 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|db[7]~26 ( -// Equation(s): -// \z80_|alu_|db[7]~26_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout ) # ((\z80_|execute_|ctl_alu_oe~13_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_alu_oe~13_combout ), - .datac(\z80_|execute_|ctl_alu_oe~9_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~26 .lut_mask = 16'hFFEF; -defparam \z80_|alu_|db[7]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db[4]~17 ( -// Equation(s): -// \z80_|alu_|db[4]~17_combout = ((\z80_|alu_|db[4]~16_combout & ((\z80_|alu_|db_high[0]~26_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[4]~16_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db_high[0]~26_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~17 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[4]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & \z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h00C8; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~6_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( -// Equation(s): -// \z80_|alu_|db_high[0]~24_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[0]~23_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[4]~17_combout ))) - - .dataa(\z80_|alu_|db_high[0]~23_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[4]~17_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hAAF0; -defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( -// Equation(s): -// \z80_|alu_|db_high[0]~21_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'h5575; -defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|alu_|db_high[0]~26_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[0]~26_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N21 -dffeas \z80_|alu_|op1_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( -// Equation(s): -// \z80_|alu_|db_high[0]~22_combout = (\z80_|alu_|op1_high [0] & (((\z80_|alu_|op2_high [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [0] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [0]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [0]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( -// Equation(s): -// \z80_|alu_|db_high[0]~25_combout = (\z80_|alu_|db_high[0]~21_combout & (\z80_|alu_|db_high[0]~22_combout & ((\z80_|alu_|db_high[0]~24_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[0]~24_combout ), - .datab(\z80_|alu_|db_high[0]~21_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[0]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'h8C00; -defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~26 ( -// Equation(s): -// \z80_|alu_|db_high[0]~26_combout = ((\z80_|alu_|db_high[0]~25_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|db_high[0]~25_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~26 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|db_low[0]~23_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) # -// (!\z80_|alu_|db_low[0]~23_combout & (((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) - - .dataa(\z80_|alu_|db_low[0]~23_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datad(\z80_|alu_|db_high[0]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFEFE; -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N31 -dffeas \z80_|alu_|op1_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( -// Equation(s): -// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [0]))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_low [0]), - .datac(\z80_|alu_|op1_high [0]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|alu_|alu_op1[0]~1_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[0]~23_combout )))) # -// (!\z80_|alu_|alu_op1[0]~1_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & ((\z80_|alu_|db_low[0]~23_combout )))) - - .dataa(\z80_|alu_|alu_op1[0]~1_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_low[0]~23_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h5050; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N15 -dffeas \z80_|alu_|op2_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(gnd), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hF0AA; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op1[0]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hF660; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~9_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & -// \z80_|execute_|ctl_alu_core_S~8_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hF1F0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op1[1]~0 ( -// Equation(s): -// \z80_|alu_|alu_op1[1]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(gnd), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[1]~0 .lut_mask = 16'hDD88; -defparam \z80_|alu_|alu_op1[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[1]~0_combout & \z80_|alu_|alu_op2[1]~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datac(\z80_|alu_|alu_op1[1]~0_combout ), - .datad(\z80_|alu_|alu_op2[1]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hFBBB; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # -// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h0F01; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op1[2]~2 ( -// Equation(s): -// \z80_|alu_|alu_op1[2]~2_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(gnd), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[2]~2 .lut_mask = 16'hEE22; -defparam \z80_|alu_|alu_op1[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op2[2]~0_combout & \z80_|alu_|alu_op1[2]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|alu_|alu_op2[2]~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datac(\z80_|alu_|alu_op1[2]~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hFF0B; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & \z80_|execute_|ctl_alu_core_S~8_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .lut_mask = 16'h5F5D; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op1[3]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & -// \z80_|alu_|alu_op2[3]~2_combout )))) # (!\z80_|alu_|alu_op1[3]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[3]~2_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) - - .dataa(\z80_|alu_|alu_op1[3]~3_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|alu_op2[3]~2_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'hFB20; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp1[7]~75_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~69_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~69 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[7]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~70 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~72_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~72 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[7]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~71_combout = (\z80_|alu_|db[7]~21_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[7]~21_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~71 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[7]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~73_combout = (\z80_|reg_file_|gdfx_temp1[7]~69_combout & (\z80_|reg_file_|gdfx_temp1[7]~70_combout & (\z80_|reg_file_|gdfx_temp1[7]~72_combout & \z80_|reg_file_|gdfx_temp1[7]~71_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~73 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~67 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[7]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~68 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~74_combout = (\z80_|reg_file_|gdfx_temp1[7]~73_combout & (\z80_|reg_file_|gdfx_temp1[7]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout & \z80_|reg_file_|gdfx_temp1[7]~68_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~74 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~19 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~75_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~75_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~19 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[7]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~20 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~20_combout = (\z80_|reg_file_|db_hi_as[7]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[7]~19_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~20 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|db_hi_as[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [12] & -// !\z80_|address_latch_|Q [11])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [12] & \z80_|address_latch_|Q [11])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~54 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[5]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~53_combout = (\z80_|alu_|db[5]~25_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[5]~25_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[5]~25_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~53 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[5]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~57_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~51_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~51 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[5]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N11 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~52_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~52 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[5]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~55_combout = (\z80_|reg_file_|gdfx_temp1[5]~54_combout & (\z80_|reg_file_|gdfx_temp1[5]~53_combout & (\z80_|reg_file_|gdfx_temp1[5]~51_combout & \z80_|reg_file_|gdfx_temp1[5]~52_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~55 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~49 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~50 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[5]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~56_combout = (\z80_|reg_file_|gdfx_temp1[5]~55_combout & (\z80_|reg_file_|gdfx_temp1[5]~49_combout & (\z80_|reg_file_|gdfx_temp1[5]~50_combout & \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~56 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~57_combout = ((\z80_|reg_file_|gdfx_temp1[5]~56_combout & ((\z80_|reg_file_|db_hi_as[5]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), - .datac(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~57 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~13 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~13_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[5]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~14 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~14_combout = (\z80_|reg_file_|db_hi_as[5]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|db_hi_as[5]~13_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~14 .lut_mask = 16'hC4C4; -defparam \z80_|reg_file_|db_hi_as[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~15 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~15_combout = ((\z80_|reg_file_|db_hi_as[5]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[5]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~15 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[5]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( -// Equation(s): -// \z80_|address_latch_|abusz [13] = (\z80_|reg_file_|db_hi_as[5]~15_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [13]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|Q[13]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[13]~feeder_combout = \z80_|address_latch_|abusz [13] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [13]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[13]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[13]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N23 -dffeas \z80_|address_latch_|Q[13] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[13]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|execute_|ctl_inc_dec~11_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( -// Equation(s): -// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~21_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N27 -dffeas \z80_|address_latch_|Q[15] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [15]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [13]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [14]), - .datad(\z80_|execute_|ctl_inc_dec~11_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'hB478; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~76 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~80_combout = (\z80_|alu_|db[6]~23_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[6]~23_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[6]~23_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~80 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N17 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~79_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~79 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~78 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~81 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~82_combout = (\z80_|reg_file_|gdfx_temp1[6]~80_combout & (\z80_|reg_file_|gdfx_temp1[6]~79_combout & (\z80_|reg_file_|gdfx_temp1[6]~78_combout & \z80_|reg_file_|gdfx_temp1[6]~81_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~82 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~77 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~83_combout = (\z80_|reg_file_|gdfx_temp1[6]~76_combout & (\z80_|reg_file_|gdfx_temp1[6]~82_combout & (\z80_|reg_file_|gdfx_temp1[6]~77_combout & \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~83 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~84_combout = ((\z80_|reg_file_|gdfx_temp1[6]~83_combout & ((\z80_|reg_file_|db_hi_as[6]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), - .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~84 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~22 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~22_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~22 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~23 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~23_combout = (\z80_|reg_file_|db_hi_as[6]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .datab(\z80_|reg_file_|db_hi_as[6]~22_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~23 .lut_mask = 16'h88CC; -defparam \z80_|reg_file_|db_hi_as[6]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~24 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~24_combout = ((\z80_|reg_file_|db_hi_as[6]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_file_|db_hi_as[6]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~24 .lut_mask = 16'hBF33; -defparam \z80_|reg_file_|db_hi_as[6]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( -// Equation(s): -// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~24_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|Q[14]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[14]~feeder_combout = \z80_|address_latch_|abusz [14] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [14]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[14]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[14]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N5 -dffeas \z80_|address_latch_|Q[14] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[14]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|address_latch_|Q [14]), - .datac(\z80_|execute_|ctl_inc_dec~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h3363; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~21 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~21_combout = ((\z80_|reg_file_|db_hi_as[7]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[7]~20_combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~21 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_hi_as[7]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~75_combout = ((\z80_|reg_file_|gdfx_temp1[7]~74_combout & ((\z80_|reg_file_|db_hi_as[7]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), - .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~75 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[7]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( -// Equation(s): -// \z80_|alu_|db[7]~20_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[7]~75_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .datad(\z80_|alu_control_|db[7]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db[7]~21 ( -// Equation(s): -// \z80_|alu_|db[7]~21_combout = ((\z80_|alu_|db[7]~20_combout & ((\z80_|alu_|db_high[3]~8_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[7]~20_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~21 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[7]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N22 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (\z80_|alu_|db[7]~21_combout & ((\z80_|ir_|opcode [3])))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & -// (\z80_|alu_|db[7]~21_combout )))) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hB822; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (\z80_|alu_control_|db[0]~12_combout & (\z80_|execute_|ctl_flags_bus~combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & -// ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[0]~12_combout & \z80_|execute_|ctl_flags_bus~combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datab(\z80_|alu_control_|db[0]~12_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'hD5C0; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hF4FC; -defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~6_combout = ((\z80_|execute_|ctl_flags_cf_we~5_combout ) # ((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~2 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_flags_cf2_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~4_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal10~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'hE000; -defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~3_combout = (\z80_|execute_|ctl_flags_cf2_we~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|ixy_d~15_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_flags_cf2_we~2_combout ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_flags_cf2_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~3_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0B8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y9_N3 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N0 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h0A88; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N4 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout & !\z80_|ir_|opcode [4])) - - .dataa(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .datac(gnd), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hCCEE; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( -// Equation(s): -// \z80_|alu_|db_high[3]~5_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[6]~23_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .datac(\z80_|alu_|db[6]~23_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( -// Equation(s): -// \z80_|alu_|db_high[3]~6_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[3]~5_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[7]~21_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(\z80_|alu_|db_high[3]~5_combout ), - .datac(\z80_|alu_|db[7]~21_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( -// Equation(s): -// \z80_|alu_|db_high[3]~4_combout = (\z80_|alu_|op2_high [3] & (((\z80_|alu_|op1_high [3])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_high [3] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [3]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_high [3]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_high [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~27 ( -// Equation(s): -// \z80_|alu_|db_high[3]~27_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~27 .lut_mask = 16'hD555; -defparam \z80_|alu_|db_high[3]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( -// Equation(s): -// \z80_|alu_|db_high[3]~7_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~27_combout & ((\z80_|alu_|db_high[3]~6_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[3]~6_combout ), - .datab(\z80_|alu_|db_high[3]~4_combout ), - .datac(\z80_|alu_|db_high[3]~27_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'h80C0; -defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~8 ( -// Equation(s): -// \z80_|alu_|db_high[3]~8_combout = ((\z80_|alu_|db_high[3]~7_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|db_high[3]~7_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~8 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[3]~8_combout )))) - - .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N15 -dffeas \z80_|alu_|op1_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~9 ( -// Equation(s): -// \z80_|alu_|db_low[3]~9_combout = (\z80_|alu_|op1_low [3] & (((\z80_|alu_|op2_low [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_low [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [3]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_low [3]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_low [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~9 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_low[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[4]~19_combout & \z80_|bus_control_|db[3]~21_combout ) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hCC00; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~10 ( -// Equation(s): -// \z80_|alu_|db_low[3]~10_combout = (\z80_|alu_|db_low[3]~9_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|bus_control_|db[5]~15_combout ), - .datab(\z80_|alu_|db_low[3]~9_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~10 .lut_mask = 16'h4C0C; -defparam \z80_|alu_|db_low[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N15 -dffeas \z80_|alu_|result_lo[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~7 ( -// Equation(s): -// \z80_|alu_|db_low[3]~7_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~17_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) - - .dataa(\z80_|alu_|db[4]~17_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[2]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~7 .lut_mask = 16'hAFA0; -defparam \z80_|alu_|db_low[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~8 ( -// Equation(s): -// \z80_|alu_|db_low[3]~8_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~7_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~11_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_low[3]~7_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~8 .lut_mask = 16'hF3BB; -defparam \z80_|alu_|db_low[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~11 ( -// Equation(s): -// \z80_|alu_|db_low[3]~11_combout = (\z80_|alu_|db_low[3]~10_combout & (\z80_|alu_|db_low[3]~8_combout & ((\z80_|alu_|result_lo [3]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[3]~10_combout ), - .datab(\z80_|alu_|result_lo [3]), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_low[3]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~11 .lut_mask = 16'hA800; -defparam \z80_|alu_|db_low[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~25 ( -// Equation(s): -// \z80_|alu_|db_low[3]~25_combout = (\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|alu_|db_low[3]~11_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~25 .lut_mask = 16'hF1F1; -defparam \z80_|alu_|db_low[3]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N12 -cycloneive_lcell_comb \z80_|alu_|db[3]~10 ( -// Equation(s): -// \z80_|alu_|db[3]~10_combout = (\z80_|execute_|ctl_alu_oe~14_combout & (\z80_|alu_|db_low[3]~25_combout & ((\z80_|reg_file_|gdfx_temp1[3]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_alu_oe~14_combout & -// (((\z80_|reg_file_|gdfx_temp1[3]~48_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .datad(\z80_|alu_|db_low[3]~25_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~10 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|db[3]~11 ( -// Equation(s): -// \z80_|alu_|db[3]~11_combout = ((\z80_|alu_|db[3]~10_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[3]~10_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[3]~35_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~11 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_alu_oe~9_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~3_combout ), - .datac(\z80_|execute_|ctl_alu_oe~9_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~49 ( -// Equation(s): -// \z80_|execute_|setM1~49_combout = (\z80_|execute_|setM1~48_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~49 .lut_mask = 16'h0070; -defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~14_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~49_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|setM1~49_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h0B0F; -defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|alu_|db_low[3]~25_combout & ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[3]~35_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_low[3]~25_combout & -// (\z80_|alu_control_|db[3]~35_combout & (\z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|alu_|db_low[3]~25_combout ), - .datab(\z80_|alu_control_|db[3]~35_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hEAC0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout = (\z80_|pla_decode_|Equal56~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # ((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # -// (!\z80_|execute_|ctl_flags_xy_we~10_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~14_combout = (((\z80_|execute_|ctl_flags_xy_we~13_combout ) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) - - .dataa(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~15_combout = (((\z80_|execute_|ctl_flags_xy_we~14_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N31 -dffeas \z80_|alu_flags_|flags_xf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_xf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_xf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( -// Equation(s): -// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_flags_|flags_xf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hF030; -defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFEFA; -defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|execute_|ixy_d~7_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFAEA; -defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N16 -cycloneive_lcell_comb \z80_|sw1_|db_down[3]~1 ( -// Equation(s): -// \z80_|sw1_|db_down[3]~1_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[3]~1 .lut_mask = 16'hFF8C; -defparam \z80_|sw1_|db_down[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( -// Equation(s): -// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & (\z80_|sw1_|db_down[3]~1_combout & ((\z80_|reg_file_|gdfx_temp0[3]~52_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datab(\z80_|alu_control_|db[3]~33_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|sw1_|db_down[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'h8C00; -defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( -// Equation(s): -// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~11_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[3]~34_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hBF33; -defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [3] & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[3]~35_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .datad(\z80_|alu_control_|db[3]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|gdfx_temp0[3]~46_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .datab(gnd), - .datac(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~49_combout & \z80_|reg_file_|gdfx_temp0[3]~47_combout )) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N31 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N5 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~51_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & (\z80_|reg_file_|gdfx_temp0[3]~50_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~52_combout = ((\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp0[3]~52_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[3]~52_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hAA0A; -defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( -// Equation(s): -// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [3]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h3030; -defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N17 -dffeas \z80_|address_latch_|Q[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [3]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout = \z80_|address_latch_|Q [3] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .lut_mask = 16'h40BF; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout )))) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h6AAA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|gdfx_temp0[4]~53_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|alu_control_|db[4]~32_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hBB00; -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N27 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N1 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~58_combout & (\z80_|reg_file_|gdfx_temp0[4]~59_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'hA200; -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N21 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N11 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N1 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N7 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|gdfx_temp0[4]~55_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~61_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & (\z80_|reg_file_|gdfx_temp0[4]~60_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & \z80_|reg_file_|gdfx_temp0[4]~56_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~62_combout = ((\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|reg_file_|gdfx_temp0[4]~62_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[4]~62_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hCC0C; -defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N16 -cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( -// Equation(s): -// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~15_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [4]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h3300; -defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N23 -dffeas \z80_|address_latch_|Q[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [4]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|address_latch_|Q [4]), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout -// ))) - - .dataa(\z80_|address_latch_|Q [5]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h6A6A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N23 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N13 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N21 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N5 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [5] & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[5]~15_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .datad(\z80_|alu_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|gdfx_temp0[5]~66_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .datad(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N3 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~67_combout & (\z80_|reg_file_|gdfx_temp0[5]~65_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~68_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~71_combout = (\z80_|reg_file_|gdfx_temp0[5]~64_combout & (\z80_|reg_file_|gdfx_temp0[5]~63_combout & \z80_|reg_file_|gdfx_temp0[5]~70_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~72_combout = ((\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .lut_mask = 16'hD5F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|reg_file_|gdfx_temp0[5]~72_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[5]~72_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'hF050; -defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( -// Equation(s): -// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~18_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [5]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N27 -dffeas \z80_|address_latch_|Q[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [5]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N26 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout = \z80_|address_latch_|Q [5] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout ))) - - .dataa(\z80_|address_latch_|Q [5]), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .lut_mask = 16'h5595; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N17 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N7 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N19 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N5 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N3 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[6]~22_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|gdfx_temp0[6]~76_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~78_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & \z80_|reg_file_|gdfx_temp0[6]~77_combout )) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N5 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~74_combout & (\z80_|reg_file_|gdfx_temp0[6]~73_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & \z80_|reg_file_|gdfx_temp0[6]~75_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[6]~82_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .datad(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( -// Equation(s): -// \z80_|address_latch_|abusz [6] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[6]~21_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N23 -dffeas \z80_|address_latch_|Q[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [6]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # (\z80_|execute_|ctl_inc_dec~7_combout ))))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h001E; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h55AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'hF575; -defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N25 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N29 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N19 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N11 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~92_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|gdfx_temp0[7]~86_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .datad(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[7]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & \z80_|reg_file_|gdfx_temp0[7]~89_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~91_combout = (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~84_combout & \z80_|reg_file_|gdfx_temp0[7]~90_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~92 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~92_combout = ((\z80_|reg_file_|gdfx_temp0[7]~91_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[7]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[7]~0_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[7]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[7]~0 .lut_mask = 16'hF0F8; -defparam \z80_|reg_file_|db_lo_ds[7]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N11 -dffeas \z80_|interrupts_|im2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~12_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|interrupts_|im2~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h5000; -defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|execute_|ctl_mRead~12_combout & \z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~17 ( -// Equation(s): -// \z80_|alu_control_|db[7]~17_combout = (\z80_|reg_file_|db_lo_ds[7]~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|reg_file_|db_lo_ds[7]~0_combout ), - .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|bus_control_|db[7]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~17 .lut_mask = 16'h2A0A; -defparam \z80_|alu_control_|db[7]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~16 ( -// Equation(s): -// \z80_|alu_control_|db[7]~16_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[7]~21_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (\z80_|execute_|ctl_sw_2u~7_combout & (!\z80_|alu_|db[7]~21_combout ))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_|db[7]~21_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~16 .lut_mask = 16'h0CAE; -defparam \z80_|alu_control_|db[7]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( -// Equation(s): -// \z80_|alu_control_|db[7]~18_combout = ((\z80_|alu_control_|db[7]~17_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & !\z80_|alu_control_|db[7]~16_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[7]~17_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_control_|db[7]~16_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h33B3; -defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[7]~18_combout ) # ((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout -// & (((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[7]~18_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~7_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~3_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y9_N9 -dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'h008C; -defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h0088; +defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X37_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( // Equation(s): -// \z80_|execute_|ctl_flags_pf_we~8_combout = (((\z80_|execute_|ctl_flags_pf_we~5_combout ) # (\z80_|execute_|ctl_flags_pf_we~7_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ) - - .dataa(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # ((!\z80_|execute_|ctl_pf_sel[0]~3_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~11_combout ) - - .dataa(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|execute_|ctl_flags_bus~combout & (\z80_|alu_control_|db[2]~29_combout ))) # (!\z80_|execute_|ctl_flags_pf_we~9_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[2]~29_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'h88F0; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (((!\z80_|pla_decode_|Equal62~3_combout & !\z80_|execute_|ctl_alu_op_low~13_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h3070; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ))))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h152A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h3B00; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N24 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [14] & (!\z80_|address_latch_|Q [12] & (!\z80_|address_latch_|Q [15] & !\z80_|address_latch_|Q [13]))) - - .dataa(\z80_|address_latch_|Q [14]), - .datab(\z80_|address_latch_|Q [12]), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|Q [13]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N16 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~3_combout = (!\z80_|address_latch_|Q [1] & (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [3] & !\z80_|address_latch_|Q [2]))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|address_latch_|Q [0]), - .datac(\z80_|address_latch_|Q [3]), - .datad(\z80_|address_latch_|Q [2]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0004; -defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N14 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [6] & (!\z80_|address_latch_|Q [5] & !\z80_|address_latch_|Q [4]))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [6]), - .datac(\z80_|address_latch_|Q [5]), - .datad(\z80_|address_latch_|Q [4]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N8 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [11] & (!\z80_|address_latch_|Q [9] & !\z80_|address_latch_|Q [8]))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [11]), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|Q [8]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N18 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~0_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & (\z80_|decode_state_|DFFE_instNonRep~2_combout & \z80_|decode_state_|DFFE_instNonRep~1_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instNonRep~0_combout ), - .datab(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; -defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N16 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~9_combout & -// ((\z80_|decode_state_|DFFE_instNonRep~4_combout ))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|decode_state_|DFFE_instNonRep~q )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~q ), - .datad(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hF4B0; -defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y16_N17 -dffeas \z80_|decode_state_|DFFE_instNonRep ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instNonRep~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N12 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|pla_decode_|Equal62~3_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h0040; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & -// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - - .dataa(\z80_|interrupts_|DFFE_instIFF2~q ), - .datab(\z80_|decode_state_|DFFE_instNonRep~q ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'hA030; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout & -// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'h808C; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N23 -dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|alu_parity_out~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55FD; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & -// \z80_|alu_|alu_op1[1]~0_combout )))) # (!\z80_|alu_|alu_op2[1]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[1]~0_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[1]~1_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|alu_|alu_op1[1]~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'hFB20; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( -// Equation(s): -// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'hA55A; -defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( -// Equation(s): -// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout $ (\z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .datad(\z80_|alu_|alu_parity_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out .lut_mask = 16'hA956; -defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'hFFEF; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h20A0; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_|alu_parity_out~combout & \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .datac(\z80_|alu_|alu_parity_out~combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFEEE; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout & \z80_|execute_|ctl_flags_alu~15_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'hECCC; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N15 -dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( -// Equation(s): -// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal40~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ))) +// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal40~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|sel[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h70F0; -defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout = (!\z80_|alu_|db_high[1]~20_combout & (!\z80_|alu_|db_high[3]~8_combout & (!\z80_|alu_|db_high[2]~14_combout & !\z80_|alu_|db_high[0]~26_combout ))) - - .dataa(\z80_|alu_|db_high[1]~20_combout ), - .datab(\z80_|alu_|db_high[3]~8_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|alu_|db_high[0]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .lut_mask = 16'h0001; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout = (\z80_|alu_control_|db[6]~22_combout & \z80_|execute_|ctl_flags_bus~combout ) - - .dataa(\z80_|alu_control_|db[6]~22_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .lut_mask = 16'hAA00; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N14 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[3]~11_combout & (\z80_|alu_|db_high[3]~3_combout & ((!\z80_|alu_|db_low[2]~3_combout ) # (!\z80_|alu_|db_low[2]~6_combout )))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|alu_|db_low[2]~3_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h1300; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_low[1]~17_combout & (\z80_|execute_|ctl_flags_alu~15_combout & (!\z80_|alu_|db_low[0]~23_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_flags_alu~15_combout ), - .datac(\z80_|alu_|db_low[0]~23_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0400; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hF7FF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hEC00; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y13_N27 -dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|alu_control_|sel[1]~0_combout & (((\z80_|ir_|opcode [4])))) # (!\z80_|alu_control_|sel[1]~0_combout & ((\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ))) # (!\z80_|ir_|opcode [4] -// & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(\z80_|alu_control_|sel[1]~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hFC0A; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & (\z80_|alu_flags_|DFFE_inst_latch_sf~q )) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_pf~q ))))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datac(\z80_|alu_control_|sel[1]~0_combout ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hAFC0; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( -// Equation(s): -// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((\z80_|alu_control_|flags_cond_true~q )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|flags_cond_true~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hB874; -defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N21 -dffeas \z80_|alu_control_|flags_cond_true ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_control_|flags_cond_true~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|flags_cond_true~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; -defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~13_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sel_wz~14_combout ) # (((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~11_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|gdfx_temp0[0]~93_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~20_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N23 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X31_Y10_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .datad(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & (((\z80_|alu_control_|db[1]~26_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[1]~26_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N3 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N9 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~28_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & (\z80_|reg_file_|gdfx_temp0[1]~29_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N27 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N25 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~23_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'hF733; -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[1]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[1]~1_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[1]~1 .lut_mask = 16'hF0F8; -defparam \z80_|reg_file_|db_lo_ds[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N30 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( -// Equation(s): -// \z80_|alu_control_|db[1]~25_combout = (\z80_|reg_file_|db_lo_ds[1]~1_combout & (((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[1]~11_combout ), - .datab(\z80_|reg_file_|db_lo_ds[1]~1_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h0C8C; -defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~24 ( -// Equation(s): -// \z80_|alu_control_|db[1]~24_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[1]~13_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (\z80_|execute_|ctl_sw_2u~7_combout & ((!\z80_|alu_|db[1]~13_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_|db[1]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~24 .lut_mask = 16'h0ACE; -defparam \z80_|alu_control_|db[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( -// Equation(s): -// \z80_|alu_control_|db[1]~26_combout = ((\z80_|alu_control_|db[1]~25_combout & (\z80_|alu_control_|db[2]~23_combout & !\z80_|alu_control_|db[1]~24_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[1]~25_combout ), - .datab(\z80_|alu_control_|db[2]~23_combout ), - .datac(\z80_|alu_control_|db[6]~11_combout ), - .datad(\z80_|alu_control_|db[1]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h0F8F; -defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db[1]~12 ( -// Equation(s): -// \z80_|alu_|db[1]~12_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[1]~26_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~12 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db[1]~13 ( -// Equation(s): -// \z80_|alu_|db[1]~13_combout = ((\z80_|alu_|db[1]~12_combout & ((\z80_|alu_|db_low[1]~17_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[1]~12_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_low[1]~17_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~13 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( -// Equation(s): -// \z80_|alu_|db_low[0]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~13_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hF5A0; -defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( -// Equation(s): -// \z80_|alu_|db_low[0]~22_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[0]~21_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[0]~19_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db_low[0]~21_combout ), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~18 ( -// Equation(s): -// \z80_|alu_|db_low[0]~18_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~18 .lut_mask = 16'h5557; -defparam \z80_|alu_|db_low[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~19 ( -// Equation(s): -// \z80_|alu_|db_low[0]~19_combout = (\z80_|alu_|op2_low [0] & (((\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [0]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_low [0]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~19 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_low[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N25 -dffeas \z80_|alu_|result_lo[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~20 ( -// Equation(s): -// \z80_|alu_|db_low[0]~20_combout = (\z80_|alu_|db_low[0]~18_combout & (\z80_|alu_|db_low[0]~19_combout & ((\z80_|alu_|result_lo [0]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[0]~18_combout ), - .datab(\z80_|alu_|db_low[0]~19_combout ), - .datac(\z80_|alu_|result_lo [0]), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~20 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( -// Equation(s): -// \z80_|alu_|db_low[0]~23_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[0]~22_combout & ((\z80_|alu_|db_low[0]~20_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[0]~20_combout ) # -// (!\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|alu_|db_low[0]~22_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_low[0]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'hAF03; -defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( -// Equation(s): -// \z80_|alu_|db[0]~18_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|alu_|db_low[0]~23_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_|db_low[0]~23_combout ) # ((!\z80_|execute_|ctl_alu_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_|db_low[0]~23_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~18 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|db[0]~19 ( -// Equation(s): -// \z80_|alu_|db[0]~19_combout = ((\z80_|alu_|db[0]~18_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[0]~12_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~19 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( -// Equation(s): -// \z80_|alu_|db_low[1]~15_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~19_combout )) - - .dataa(\z80_|alu_|db[0]~19_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[2]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( -// Equation(s): -// \z80_|alu_|db_low[1]~16_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[1]~15_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[1]~13_combout ))) - - .dataa(\z80_|alu_|db_low[1]~15_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hAAF0; -defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( -// Equation(s): -// \z80_|alu_|db_low[1]~12_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'h5755; -defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~13 ( -// Equation(s): -// \z80_|alu_|db_low[1]~13_combout = (\z80_|alu_|op2_low [1] & (((\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [1] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [1]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [1]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~13 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_low[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N21 -dffeas \z80_|alu_|result_lo[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~14 ( -// Equation(s): -// \z80_|alu_|db_low[1]~14_combout = (\z80_|alu_|db_low[1]~12_combout & (\z80_|alu_|db_low[1]~13_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[1]~12_combout ), - .datab(\z80_|alu_|db_low[1]~13_combout ), - .datac(\z80_|alu_|result_lo [1]), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~14 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( -// Equation(s): -// \z80_|alu_|db_low[1]~17_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~16_combout & \z80_|alu_|db_low[1]~14_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~14_combout )) # -// (!\z80_|alu_|db_high[3]~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|alu_|db_low[1]~16_combout ), - .datad(\z80_|alu_|db_low[1]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'hF511; -defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # -// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N1 -dffeas \z80_|alu_|op1_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N28 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( -// Equation(s): -// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [1]) # (\z80_|alu_|op1_low [2]))) - - .dataa(gnd), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hF0C0; -defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0F00; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N8 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( -// Equation(s): -// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & -// (((\z80_|alu_flags_|flags_hf2~q )))) - - .dataa(\z80_|alu_control_|db[4]~32_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .datac(\z80_|alu_flags_|flags_hf2~q ), - .datad(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hEEF0; -defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N9 -dffeas \z80_|alu_flags_|flags_hf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|flags_hf2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_hf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~23 ( -// Equation(s): -// \z80_|alu_control_|db[2]~23_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|alu_flags_|flags_hf2~q ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~combout ), - .datab(\z80_|alu_control_|out[6]~0_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|alu_flags_|flags_hf2~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~23 .lut_mask = 16'hFFEF; -defparam \z80_|alu_control_|db[2]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[2]~2_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[2]~2 .lut_mask = 16'hFF40; -defparam \z80_|reg_file_|db_lo_ds[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( -// Equation(s): -// \z80_|alu_control_|db[2]~28_combout = (\z80_|reg_file_|db_lo_ds[2]~2_combout & (((\z80_|bus_control_|db[2]~13_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[2]~13_combout ), - .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h2F00; -defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~27 ( -// Equation(s): -// \z80_|alu_control_|db[2]~27_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((!\z80_|alu_|db[2]~15_combout & \z80_|execute_|ctl_sw_2u~7_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (!\z80_|alu_|db[2]~15_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|alu_|db[2]~15_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~27 .lut_mask = 16'h3B0A; -defparam \z80_|alu_control_|db[2]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( -// Equation(s): -// \z80_|alu_control_|db[2]~29_combout = ((\z80_|alu_control_|db[2]~23_combout & (\z80_|alu_control_|db[2]~28_combout & !\z80_|alu_control_|db[2]~27_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[2]~23_combout ), - .datac(\z80_|alu_control_|db[2]~28_combout ), - .datad(\z80_|alu_control_|db[2]~27_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h55D5; -defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db[2]~14 ( -// Equation(s): -// \z80_|alu_|db[2]~14_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[2]~39_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[2]~29_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[2]~29_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~14 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[2]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db[2]~15 ( -// Equation(s): -// \z80_|alu_|db[2]~15_combout = ((\z80_|alu_|db[2]~14_combout & ((\z80_|alu_|db_low[2]~24_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_low[2]~24_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[2]~14_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~15 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[2]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N4 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~2 ( -// Equation(s): -// \z80_|alu_|db_low[2]~2_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[1]~13_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[3]~11_combout ), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~2 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|db_low[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~3 ( -// Equation(s): -// \z80_|alu_|db_low[2]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~15_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[2]~15_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_low[2]~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~3 .lut_mask = 16'hF3BB; -defparam \z80_|alu_|db_low[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_high[3]~3_combout ), - .datac(\z80_|alu_|db_low[2]~3_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .lut_mask = 16'hB300; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'h3222; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N25 -dffeas \z80_|alu_|op1_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ) # ((\z80_|alu_|db_low[2]~24_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), - .datac(\z80_|alu_|db_low[2]~24_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N13 -dffeas \z80_|alu_|op2_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~5 ( -// Equation(s): -// \z80_|alu_|db_low[2]~5_combout = (\z80_|alu_|op2_low [2] & ((\z80_|alu_|op1_low [2]) # ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_low [2] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [2]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [2]), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~5 .lut_mask = 16'h8ACF; -defparam \z80_|alu_|db_low[2]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N13 -dffeas \z80_|alu_|result_lo[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~6 ( -// Equation(s): -// \z80_|alu_|db_low[2]~6_combout = (\z80_|alu_|db_low[2]~4_combout & (\z80_|alu_|db_low[2]~5_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [2])))) - - .dataa(\z80_|alu_|db_low[2]~4_combout ), - .datab(\z80_|alu_|db_low[2]~5_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|result_lo [2]), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~6 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[2]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_low[2]~3_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h80F0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N27 -dffeas \z80_|alu_|op2_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~0 ( -// Equation(s): -// \z80_|alu_|alu_op2[2]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) - - .dataa(\z80_|alu_|op2_high [2]), - .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|alu_|op2_low [2]), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[2]~0 .lut_mask = 16'h4B78; -defparam \z80_|alu_|alu_op2[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h0BFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[2]~2_combout & -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|alu_|alu_op2[2]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[2]~2_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[2]~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .datac(\z80_|alu_|alu_op1[2]~2_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hECC8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( -// Equation(s): -// \z80_|alu_|db_high[2]~9_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'h55D5; -defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( -// Equation(s): -// \z80_|alu_|db_high[2]~11_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~21_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~25_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(\z80_|alu_|db[7]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'hFA50; -defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( -// Equation(s): -// \z80_|alu_|db_high[2]~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[2]~11_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[6]~23_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[2]~11_combout ), - .datac(\z80_|alu_|db[6]~23_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( -// Equation(s): -// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [2]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( -// Equation(s): -// \z80_|alu_|db_high[2]~13_combout = (\z80_|alu_|db_high[2]~9_combout & (\z80_|alu_|db_high[2]~10_combout & ((\z80_|alu_|db_high[2]~12_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[2]~9_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[2]~12_combout ), - .datad(\z80_|alu_|db_high[2]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hA200; -defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~14 ( -// Equation(s): -// \z80_|alu_|db_high[2]~14_combout = ((\z80_|alu_|db_high[2]~13_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .datab(\z80_|alu_|db_high[3]~3_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_high[2]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~14 .lut_mask = 16'hFB33; -defparam \z80_|alu_|db_high[2]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( -// Equation(s): -// \z80_|alu_|db[6]~22_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .datad(\z80_|alu_control_|db[6]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db[6]~23 ( -// Equation(s): -// \z80_|alu_|db[6]~23_combout = ((\z80_|alu_|db[6]~22_combout & ((\z80_|alu_|db_high[2]~14_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_high[2]~14_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~23 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[6]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N10 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( -// Equation(s): -// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_|op1_high [0] & \z80_|alu_control_|out[6]~0_combout ))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|alu_|op1_high [0]), - .datac(\z80_|alu_|op1_high [1]), - .datad(\z80_|alu_control_|out[6]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEFA; -defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N26 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( -// Equation(s): -// \z80_|alu_control_|out[6]~2_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) - - .dataa(\z80_|execute_|ctl_66_oe~combout ), - .datab(\z80_|alu_control_|out[6]~1_combout ), - .datac(\z80_|alu_|op1_high [3]), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFFEA; -defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~19 ( -// Equation(s): -// \z80_|alu_control_|db[6]~19_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & -// (!\z80_|execute_|ctl_flags_oe~2_combout & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|out[6]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~19 .lut_mask = 16'hAF8C; -defparam \z80_|alu_control_|db[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~20 ( -// Equation(s): -// \z80_|alu_control_|db[6]~20_combout = (\z80_|alu_control_|db[6]~19_combout & ((\z80_|alu_|db[6]~23_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db[6]~23_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[6]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~20 .lut_mask = 16'hCF00; -defparam \z80_|alu_control_|db[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( -// Equation(s): -// \z80_|alu_control_|db[6]~21_combout = (\z80_|alu_control_|db[6]~20_combout & (((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[6]~9_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|alu_control_|db[6]~20_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'h30B0; -defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( -// Equation(s): -// \z80_|alu_control_|db[6]~22_combout = ((\z80_|alu_control_|db[6]~21_combout & ((\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[6]~21_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'hD5DD; -defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal33~1_combout & ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .combout(\z80_|execute_|ctl_mRead~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'hC800; -defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( +// Location: LCCOMB_X37_Y6_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( // Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[3]~21_combout ) +// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) - .dataa(gnd), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[3]~21_combout ), + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .combout(\z80_|pla_decode_|Equal77~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h00CC; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0100; +defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y10_N9 -dffeas \z80_|interrupts_|im1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( +// Location: LCCOMB_X37_Y12_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( // Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|interrupts_|im1~q ), - .datac(\z80_|interrupts_|im2~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hDC00; -defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & -// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h40EE; -defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N0 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( -// Equation(s): -// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) +// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout )) .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[0]~4_combout ), + .combout(\z80_|pla_decode_|Equal50~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hFF31; -defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N6 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( +// Location: LCCOMB_X40_Y13_N16 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( // Equation(s): -// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) +// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) - .dataa(gnd), - .datab(\z80_|alu_control_|db[6]~22_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[6]~8_combout ), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~37 ( +// Location: LCCOMB_X30_Y11_N20 +cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( // Equation(s): -// \z80_|execute_|ctl_mRead~37_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|sequencer_|DFFE_T5_ff~q ) +// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|interrupts_|DFFE_inst44~q & !\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~37 .lut_mask = 16'hDDDF; -defparam \z80_|execute_|ctl_mRead~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~37_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~37_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ctl_mRead~28_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~28_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_mRead~29_combout & (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & !\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ))) - - .dataa(\z80_|execute_|ctl_mRead~29_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_mRead~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~37 ( -// Equation(s): -// \z80_|execute_|setM1~37_combout = (!\z80_|pla_decode_|Equal9~1_combout & (!\z80_|pla_decode_|Equal29~0_combout & (\z80_|execute_|ctl_al_we~4_combout & \z80_|execute_|ctl_inc_cy~41_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|execute_|ctl_al_we~4_combout ), - .datad(\z80_|execute_|ctl_inc_cy~41_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~37 .lut_mask = 16'h1000; -defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~55 ( -// Equation(s): -// \z80_|execute_|setM1~55_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~55 .lut_mask = 16'h3233; -defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~38 ( -// Equation(s): -// \z80_|execute_|setM1~38_combout = (!\z80_|execute_|ctl_mRead~16_combout & (\z80_|execute_|setM1~37_combout & (\z80_|execute_|setM1~55_combout & \z80_|execute_|setM1~36_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|setM1~37_combout ), - .datac(\z80_|execute_|setM1~55_combout ), - .datad(\z80_|execute_|setM1~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~38 .lut_mask = 16'h4000; -defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~34_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|setM1~38_combout ))) - - .dataa(\z80_|execute_|setM1~38_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~3 ( -// Equation(s): -// \z80_|execute_|nextM~3_combout = (!\z80_|pla_decode_|Equal41~2_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ixy_d~16_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0003; -defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|nextM~3_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_mRead~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|execute_|ctl_mRead~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFC0; -defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~35 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~35_combout = ((\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|execute_|ctl_mRead~31_combout ) # (\z80_|execute_|ctl_mRead~33_combout ))) # (!\z80_|execute_|ctl_mRead~30_combout ) - - .dataa(\z80_|execute_|ctl_mRead~30_combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|ctl_mRead~31_combout ), - .datad(\z80_|execute_|ctl_mRead~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~35 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_mRead~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N23 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mRead~35_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N24 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X46_Y15_N25 -dffeas \z80_|memory_ifc_|wait_mrd ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mrd~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N3 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_mrd~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N8 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & !\z80_|memory_ifc_|DFFE_mrd_ff3~q ) - - .dataa(\z80_|memory_ifc_|wait_mrd~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0055; -defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|nextM~4 ( -// Equation(s): -// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout ) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~4 .lut_mask = 16'h373F; -defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~12_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_iorw~12_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~11_combout & \z80_|execute_|ctl_mWrite~16_combout ))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|nextM~4_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_iorw~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N7 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_iorw~9_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N26 -cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder ( -// Equation(s): -// \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout = \z80_|memory_ifc_|DFFE_iorq_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N27 -dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N9 -dffeas \z80_|memory_ifc_|wait_iorq ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorq~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N13 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorq~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( -// Equation(s): -// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|wait_iorq~q ), - .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|iorq~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; -defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( -// Equation(s): -// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hA800; -defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( -// Equation(s): -// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_alu_op_low~9_combout ) # ((\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|fIOWrite~0_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|fIORead~1_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFFF2; -defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( -// Equation(s): -// \z80_|execute_|fIORead~0_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hA080; -defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( -// Equation(s): -// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|fIOWrite~1_combout ), - .datab(\z80_|execute_|fIORead~2_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|fIORead~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N25 -dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|setM1~52_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_m1_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N14 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( -// Equation(s): -// \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_m1_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N15 -dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N21 -dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_m1_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N20 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|interrupts_|DFFE_inst44~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # (\z80_|memory_ifc_|DFFE_m1_ff3~q )))) # (!\z80_|interrupts_|DFFE_inst44~q & -// ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # ((\z80_|memory_ifc_|DFFE_m1_ff3~q )))) - - .dataa(\z80_|interrupts_|DFFE_inst44~q ), - .datab(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .datac(\z80_|memory_ifc_|DFFE_m1_ff3~q ), + .datac(\z80_|interrupts_|DFFE_inst44~q ), .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~0_combout ), + .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hFC54; -defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0010; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N18 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~2_combout = ((\z80_|memory_ifc_|nRD_out~0_combout ) # ((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIORead~3_combout ))) # (!\z80_|memory_ifc_|nRD_out~1_combout ) - - .dataa(\z80_|memory_ifc_|nRD_out~1_combout ), - .datab(\z80_|memory_ifc_|iorq~0_combout ), - .datac(\z80_|execute_|fIORead~3_combout ), - .datad(\z80_|memory_ifc_|nRD_out~0_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~2_combout ), - .cout()); +// Location: FF_X30_Y11_N21 +dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .prn(vcc)); // synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hFFD5; -defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N24 -cycloneive_lcell_comb \Equal2~1 ( -// Equation(s): -// \Equal2~1_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~1 .lut_mask = 16'h4040; -defparam \Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~0 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~0 .lut_mask = 16'hFFAA; -defparam \z80_|pin_control_|bus_db_pin_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( -// Equation(s): -// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h3F33; -defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( -// Equation(s): -// \z80_|execute_|fMWrite~6_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) - - .dataa(\z80_|execute_|fMWrite~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'h5554; -defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( -// Equation(s): -// \z80_|execute_|fMWrite~2_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h555F; -defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( -// Equation(s): -// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fMWrite~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|fMWrite~2_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h00EF; -defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~1 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~1_combout = (\z80_|execute_|ctl_bus_inc_oe~24_combout & (!\z80_|execute_|fIOWrite~5_combout & (!\z80_|execute_|fMWrite~6_combout & !\z80_|execute_|fMWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .datab(\z80_|execute_|fIOWrite~5_combout ), - .datac(\z80_|execute_|fMWrite~6_combout ), - .datad(\z80_|execute_|fMWrite~4_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~1 .lut_mask = 16'h0002; -defparam \z80_|pin_control_|bus_db_pin_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'h135F; -defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N24 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|pin_control_|bus_db_pin_oe~2_combout & (((\z80_|execute_|ixy_d~4_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'hA2AA; -defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( -// Equation(s): -// \z80_|execute_|fMWrite~7_combout = (!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_mRead~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'h0003; -defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~7_combout ) # ((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|fMWrite~7_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'hCD00; -defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~10_combout & ((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h0777; -defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N4 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|fMRead~1_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout )) # -// (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|fMRead~1_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h3715; -defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|fMWrite~9 ( -// Equation(s): -// \z80_|execute_|fMWrite~9_combout = (\z80_|pla_decode_|Equal46~0_combout ) # (((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout )) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~9 .lut_mask = 16'hCEFF; -defparam \z80_|execute_|fMWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|execute_|fIOWrite~0_combout & ((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) # (!\z80_|execute_|ctl_mWrite~6_combout & -// (((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|fMWrite~2_combout ), - .datad(\z80_|execute_|fMWrite~9_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'hDDD0; -defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N0 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (\z80_|execute_|fMWrite~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout )) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .datab(\z80_|execute_|fMWrite~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h0808; -defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( -// Equation(s): -// \z80_|execute_|fMWrite~8_combout = (\z80_|execute_|ctl_state_alu~6_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & (\z80_|execute_|ctl_reg_sel_wz~5_combout & (!\z80_|execute_|fMWrite~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .datac(\z80_|execute_|fMWrite~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h0800; -defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|pin_control_|bus_db_pin_oe~7_combout & (\z80_|pin_control_|bus_db_pin_oe~6_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~5_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|fMWrite~10 ( -// Equation(s): -// \z80_|execute_|fMWrite~10_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|execute_|ctl_alu_oe~2_combout & -// ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~10 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N0 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|pin_control_|bus_db_pin_oe~10_combout & (!\z80_|execute_|fMWrite~10_combout & \z80_|execute_|ctl_bus_inc_oe~28_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .datac(\z80_|execute_|fMWrite~10_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h0800; -defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~3_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h2A00; -defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (\z80_|pin_control_|bus_db_pin_oe~1_combout & (\z80_|pin_control_|bus_db_pin_oe~12_combout & \z80_|execute_|ctl_inc_cy~37_combout ))) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .datad(\z80_|execute_|ctl_inc_cy~37_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N28 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout ))) # -// (!\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|fIOWrite~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'hF222; -defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N0 +// Location: LCCOMB_X39_Y14_N26 cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( // Equation(s): // \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q @@ -37040,7 +6633,7 @@ defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y15_N1 +// Location: FF_X39_Y14_N27 dffeas \z80_|clk_delay_|DFF_inst5 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), @@ -37059,3754 +6652,96 @@ defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y15_N22 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorqinta~feeder ( +// Location: LCCOMB_X39_Y14_N4 +cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( // Equation(s): -// \z80_|memory_ifc_|wait_iorqinta~feeder_combout = \z80_|clk_delay_|DFF_inst5~q +// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|DFF_inst5~q & !\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ) - .dataa(gnd), + .dataa(\z80_|clk_delay_|DFF_inst5~q ), .datab(gnd), .datac(gnd), - .datad(\z80_|clk_delay_|DFF_inst5~q ), + .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), .cin(gnd), - .combout(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), + .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .sum_lutc_input = "datac"; +defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0055; +defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y15_N23 -dffeas \z80_|memory_ifc_|wait_iorqinta ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), +// Location: FF_X40_Y13_N17 +dffeas \z80_|sequencer_|DFFE_T5_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorqinta~q ), + .q(\z80_|sequencer_|DFFE_T5_ff~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; +defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; // synopsys translate_on -// Location: FF_X43_Y15_N13 -dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Location: LCCOMB_X32_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( // Equation(s): -// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|wait_iorqinta~q ) # ((\z80_|memory_ifc_|DFFE_intr_ff3~q ) # (\z80_|memory_ifc_|iorq~0_combout )) +// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) - .dataa(\z80_|memory_ifc_|wait_iorqinta~q ), - .datab(gnd), - .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .datad(\z80_|memory_ifc_|iorq~0_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFFFA; -defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N18 -cycloneive_lcell_comb \Equal2~0 ( -// Equation(s): -// \Equal2~0_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~0 .lut_mask = 16'h4000; -defparam \Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N22 -cycloneive_lcell_comb \ExtRamWE~0 ( -// Equation(s): -// \ExtRamWE~0_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\ExtRamWE~0_combout ), - .cout()); -// synopsys translate_off -defparam \ExtRamWE~0 .lut_mask = 16'h0020; -defparam \ExtRamWE~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [13]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [13]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|ixy_d~15_combout ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), + .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h0B0B; -defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N28 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~2_combout = (((\z80_|execute_|fMRead~35_combout ) # (\z80_|execute_|fIORead~3_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .datac(\z80_|execute_|fMRead~35_combout ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFFF7; -defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N2 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pin_control_|bus_ab_pin_we~2_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T3_ff~q & -// (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pin_control_|bus_ab_pin_we~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h3B0A; -defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .asdata(\z80_|address_latch_|Q [13]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[13]~20 ( -// Equation(s): -// \z80_|address_pins_|abus[13]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[13]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[13]~20 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[13]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [14])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [14]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [14]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .asdata(\z80_|address_latch_|Q [14]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N4 -cycloneive_lcell_comb \z80_|address_pins_|abus[14]~23 ( -// Equation(s): -// \z80_|address_pins_|abus[14]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[14]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[14]~23 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[14]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [15]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .asdata(\z80_|address_latch_|Q [15]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N12 -cycloneive_lcell_comb \z80_|address_pins_|abus[15]~22 ( -// Equation(s): -// \z80_|address_pins_|abus[15]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[15]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[15]~22 .lut_mask = 16'hF3F3; -defparam \z80_|address_pins_|abus[15]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h0800; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00C0; -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( -// Equation(s): -// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [1]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [1]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .asdata(\z80_|address_latch_|Q [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( -// Equation(s): -// \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [1]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [2]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .asdata(\z80_|address_latch_|Q [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N26 -cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( -// Equation(s): -// \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [2]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[2]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N0 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [3])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [3]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N1 -dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .asdata(\z80_|address_latch_|Q [3]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N12 -cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( -// Equation(s): -// \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [3]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[3]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N30 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [4])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [4]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N31 -dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .asdata(\z80_|address_latch_|Q [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N2 -cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( -// Equation(s): -// \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [4]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[4]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N12 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [5]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N13 -dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .asdata(\z80_|address_latch_|Q [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( -// Equation(s): -// \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[5]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hF3F3; -defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [6])) - - .dataa(\z80_|address_latch_|abusz [6]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .asdata(\z80_|address_latch_|Q [6]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N28 -cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( -// Equation(s): -// \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [6]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[6]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hCFCF; -defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N30 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [7]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N31 -dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .asdata(\z80_|address_latch_|Q [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N22 -cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( -// Equation(s): -// \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [7]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[7]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N20 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [8])) - - .dataa(\z80_|address_latch_|abusz [8]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N21 -dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .asdata(\z80_|address_latch_|Q [8]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N30 -cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( -// Equation(s): -// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [8]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[8]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N16 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [9]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [9]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N17 -dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .asdata(\z80_|address_latch_|Q [9]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N4 -cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( -// Equation(s): -// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [9]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[9]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N24 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [10]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .datab(\z80_|address_latch_|abusz [10]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N25 -dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .asdata(\z80_|address_latch_|Q [10]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N24 -cycloneive_lcell_comb \z80_|address_pins_|abus[10]~24 ( -// Equation(s): -// \z80_|address_pins_|abus[10]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [10]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[10]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[10]~24 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[10]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N6 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datab(\z80_|address_latch_|abusz [11]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N7 -dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .asdata(\z80_|address_latch_|Q [11]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( -// Equation(s): -// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [11]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[11]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N16 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [12])) - - .dataa(\z80_|address_latch_|abusz [12]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N17 -dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .asdata(\z80_|address_latch_|Q [12]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N30 -cycloneive_lcell_comb \z80_|address_pins_|abus[12]~21 ( -// Equation(s): -// \z80_|address_pins_|abus[12]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [12]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[12]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[12]~21 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[12]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y11_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X32_Y14_N31 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[13]~20_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X32_Y14_N1 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N12 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0200; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N18 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h000C; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: FF_X29_Y14_N5 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[14]~23_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N21 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N24 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h2000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N26 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h0C00; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N10 -cycloneive_lcell_comb \D[6]~90 ( -// Equation(s): -// \D[6]~90_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .cin(gnd), - .combout(\D[6]~90_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~90 .lut_mask = 16'hCCE2; -defparam \D[6]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N20 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hF333; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N16 -cycloneive_lcell_comb \D[6]~91 ( -// Equation(s): -// \D[6]~91_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~90_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ))) # (!\D[6]~90_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~90_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[6]~90_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), - .cin(gnd), - .combout(\D[6]~91_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~91 .lut_mask = 16'hF838; -defparam \D[6]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N2 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h0020; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G15 -cycloneive_clkctrl \CLOCK_50~inputclkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\CLOCK_50~inputclkctrl_outclk )); -// synopsys translate_off -defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; -defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y24_N16 -cycloneive_lcell_comb \~GND ( -// Equation(s): -// \~GND~combout = GND - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\~GND~combout ), - .cout()); -// synopsys translate_off -defparam \~GND .lut_mask = 16'h0000; -defparam \~GND .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vram_address[0]~feeder ( -// Equation(s): -// \ula_|video_|vram_address[0]~feeder_combout = \ula_|video_|vga_hc [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [4]), - .cin(gnd), - .combout(\ula_|video_|vram_address[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vram_address[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N4 -cycloneive_lcell_comb \ula_|video_|vram_address~0 ( -// Equation(s): -// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N21 -dffeas \ula_|video_|vram_address[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X34_Y33_N19 -dffeas \ula_|video_|vram_address[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N0 -cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( -// Equation(s): -// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|video_|vram_address[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; -defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N1 -dffeas \ula_|video_|vram_address[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N26 -cycloneive_lcell_comb \ula_|video_|Add3~0 ( -// Equation(s): -// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|Add3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N27 -dffeas \ula_|video_|vram_address[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N28 -cycloneive_lcell_comb \ula_|video_|Add3~1 ( -// Equation(s): -// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) - - .dataa(\ula_|video_|vga_hc [6]), - .datab(gnd), - .datac(\ula_|video_|vga_hc [8]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|Add3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~1 .lut_mask = 16'hA50F; -defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N29 -dffeas \ula_|video_|vram_address[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N2 -cycloneive_lcell_comb \ula_|video_|Add4~0 ( -// Equation(s): -// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) -// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) - - .dataa(\ula_|video_|vga_vc [0]), - .datab(\ula_|video_|vga_vc [1]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add4~0_combout ), - .cout(\ula_|video_|Add4~1 )); -// synopsys translate_off -defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; -defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Add4~2 ( -// Equation(s): -// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) -// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~1 ), - .combout(\ula_|video_|Add4~2_combout ), - .cout(\ula_|video_|Add4~3 )); -// synopsys translate_off -defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; -defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N6 -cycloneive_lcell_comb \ula_|video_|Add4~4 ( -// Equation(s): -// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) -// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~3 ), - .combout(\ula_|video_|Add4~4_combout ), - .cout(\ula_|video_|Add4~5 )); -// synopsys translate_off -defparam \ula_|video_|Add4~4 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N8 -cycloneive_lcell_comb \ula_|video_|Add4~6 ( -// Equation(s): -// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) -// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~5 ), - .combout(\ula_|video_|Add4~6_combout ), - .cout(\ula_|video_|Add4~7 )); -// synopsys translate_off -defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N9 -dffeas \ula_|video_|vram_address[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N10 -cycloneive_lcell_comb \ula_|video_|Add4~8 ( -// Equation(s): -// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) -// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~7 ), - .combout(\ula_|video_|Add4~8_combout ), - .cout(\ula_|video_|Add4~9 )); -// synopsys translate_off -defparam \ula_|video_|Add4~8 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N11 -dffeas \ula_|video_|vram_address[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N12 -cycloneive_lcell_comb \ula_|video_|Add4~10 ( -// Equation(s): -// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) -// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~9 ), - .combout(\ula_|video_|Add4~10_combout ), - .cout(\ula_|video_|Add4~11 )); -// synopsys translate_off -defparam \ula_|video_|Add4~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N13 -dffeas \ula_|video_|vram_address[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Add4~12 ( -// Equation(s): -// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) -// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~11 ), - .combout(\ula_|video_|Add4~12_combout ), - .cout(\ula_|video_|Add4~13 )); -// synopsys translate_off -defparam \ula_|video_|Add4~12 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N22 -cycloneive_lcell_comb \ula_|video_|Selector6~0 ( -// Equation(s): -// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~12_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~0_combout ))) - - .dataa(gnd), - .datab(\ula_|video_|Add4~12_combout ), - .datac(\ula_|video_|Add4~0_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector6~0 .lut_mask = 16'hCCF0; -defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N14 -cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( -// Equation(s): -// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address[9]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N23 -dffeas \ula_|video_|vram_address[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector6~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add4~14 ( -// Equation(s): -// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_vc [8]), - .cin(\ula_|video_|Add4~13 ), - .combout(\ula_|video_|Add4~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; -defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N20 -cycloneive_lcell_comb \ula_|video_|Selector5~0 ( -// Equation(s): -// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) - - .dataa(\ula_|video_|Add4~14_combout ), - .datab(gnd), - .datac(\ula_|video_|Add4~2_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector5~0 .lut_mask = 16'hAAF0; -defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N21 -dffeas \ula_|video_|vram_address[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector5~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N28 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( -// Equation(s): -// \ula_|video_|vram_address[10]~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N30 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( -// Equation(s): -// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & (\ula_|video_|vga_hc [1]))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) - - .dataa(\ula_|video_|Add4~4_combout ), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vram_address [10]), - .datad(\ula_|video_|vram_address[10]~2_combout ), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'h88F0; -defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N31 -dffeas \ula_|video_|vram_address[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[10]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N16 -cycloneive_lcell_comb \ula_|video_|Selector3~0 ( -// Equation(s): -// \ula_|video_|Selector3~0_combout = (\ula_|video_|Add4~12_combout ) # (\ula_|video_|vga_hc [2]) - - .dataa(gnd), - .datab(\ula_|video_|Add4~12_combout ), - .datac(gnd), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFCC; -defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N17 -dffeas \ula_|video_|vram_address[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N26 -cycloneive_lcell_comb \ula_|video_|Selector2~0 ( -// Equation(s): -// \ula_|video_|Selector2~0_combout = (\ula_|video_|Add4~14_combout ) # (\ula_|video_|vga_hc [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Add4~14_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFFF0; -defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N27 -dffeas \ula_|video_|vram_address[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[12] .power_up = "low"; -// synopsys translate_on - -// Location: M9K_X33_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N22 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|abus[13]~20_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N23 -dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y14_N1 -dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(gnd), - .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N10 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h0080; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y33_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N2 -cycloneive_lcell_comb \D[6]~87 ( -// Equation(s): -// \D[6]~87_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .cin(gnd), - .combout(\D[6]~87_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~87 .lut_mask = 16'hE6A2; -defparam \D[6]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y1_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N6 -cycloneive_lcell_comb \D[6]~88 ( -// Equation(s): -// \D[6]~88_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ (((\D[6]~87_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~87_combout )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datad(\D[6]~87_combout ), - .cin(gnd), - .combout(\D[6]~88_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~88 .lut_mask = 16'h22D8; -defparam \D[6]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N20 -cycloneive_lcell_comb \D[6]~89 ( -// Equation(s): -// \D[6]~89_combout = (\D[6]~87_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~88_combout )))) # (!\D[6]~87_combout & -// (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \D[6]~88_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datab(\D[6]~87_combout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\D[6]~88_combout ), - .cin(gnd), - .combout(\D[6]~89_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~89 .lut_mask = 16'hC3C8; -defparam \D[6]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N14 -cycloneive_lcell_comb \D[6]~111 ( -// Equation(s): -// \D[6]~111_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\D[6]~91_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\D[6]~89_combout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[6]~91_combout )) - - .dataa(\D[6]~91_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\D[6]~89_combout ), - .cin(gnd), - .combout(\D[6]~111_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~111 .lut_mask = 16'hAEA2; -defparam \D[6]~111 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X16_Y34_N8 -cycloneive_io_ibuf \raw_loader_in~input ( - .i(raw_loader_in), - .ibar(gnd), - .o(\raw_loader_in~input_o )); -// synopsys translate_off -defparam \raw_loader_in~input .bus_hold = "false"; -defparam \raw_loader_in~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N18 -cycloneive_lcell_comb \D[6]~86 ( -// Equation(s): -// \D[6]~86_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(gnd), - .datac(\raw_loader_in~input_o ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\D[6]~86_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~86 .lut_mask = 16'hFAFF; -defparam \D[6]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N28 -cycloneive_lcell_comb \D[6]~100 ( -// Equation(s): -// \D[6]~100_combout = ((\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout ))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~1_combout ), - .datab(\Equal2~0_combout ), - .datac(\D[6]~111_combout ), - .datad(\D[6]~86_combout ), - .cin(gnd), - .combout(\D[6]~100_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~100 .lut_mask = 16'hFD75; -defparam \D[6]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N4 -cycloneive_lcell_comb \D[6]~101 ( -// Equation(s): -// \D[6]~101_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [6] & \D[6]~100_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[6]~100_combout )) # (!\Equal2~1_combout ))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[6]~100_combout ), - .cin(gnd), - .combout(\D[6]~101_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~101 .lut_mask = 16'hCF05; -defparam \D[6]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N12 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[6]~101_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\D[6]~101_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[6]~9_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|fIORead~3_combout )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # -// ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|fIORead~3_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hDC50; -defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N16 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|execute_|fMRead~35_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEA; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N13 -dffeas \z80_|data_pins_|dout[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N16 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( -// Equation(s): -// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[6]~8_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|execute_|ctl_bus_db_oe~combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'h8AFF; -defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N8 -cycloneive_lcell_comb \z80_|ir_|opcode[6]~feeder ( -// Equation(s): -// \z80_|ir_|opcode[6]~feeder_combout = \z80_|bus_control_|db[6]~9_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[6]~9_combout ), - .cin(gnd), - .combout(\z80_|ir_|opcode[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|ir_|opcode[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|ir_|opcode[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_ir_we~5_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N9 -dffeas \z80_|ir_|opcode[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|ir_|opcode[6]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~1_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~2_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~1_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|pla_decode_|Equal41~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal41~2_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFF08; -defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( -// Equation(s): -// \z80_|alu_|db_high[1]~15_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'h7555; -defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( -// Equation(s): -// \z80_|alu_|db_high[1]~16_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [1]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [1]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( -// Equation(s): -// \z80_|alu_|db_high[1]~17_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~23_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~17_combout ))) - - .dataa(\z80_|alu_|db[6]~23_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[4]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hAFA0; -defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( -// Equation(s): -// \z80_|alu_|db_high[1]~18_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[1]~17_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[5]~25_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[1]~17_combout ), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( -// Equation(s): -// \z80_|alu_|db_high[1]~19_combout = (\z80_|alu_|db_high[1]~15_combout & (\z80_|alu_|db_high[1]~16_combout & ((\z80_|alu_|db_high[1]~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[1]~15_combout ), - .datab(\z80_|alu_|db_high[1]~16_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[1]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~20 ( -// Equation(s): -// \z80_|alu_|db_high[1]~20_combout = ((\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~20 .lut_mask = 16'hA8FF; -defparam \z80_|alu_|db_high[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( -// Equation(s): -// \z80_|alu_|db[5]~24_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[5]~15_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_control_|db[5]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db[5]~25 ( -// Equation(s): -// \z80_|alu_|db[5]~25_combout = ((\z80_|alu_|db[5]~24_combout & ((\z80_|alu_|db_high[1]~20_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_high[1]~20_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db[5]~24_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~25 .lut_mask = 16'hB3F3; -defparam \z80_|alu_|db[5]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N14 -cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( -// Equation(s): -// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_1d~6_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[5]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hEFCC; -defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_control_|db[5]~15_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|alu_control_|db[5]~15_combout -// & (\z80_|alu_|db_high[1]~20_combout & ((\z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|alu_control_|db[5]~15_combout ), - .datab(\z80_|alu_|db_high[1]~20_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hECA0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N23 -dffeas \z80_|alu_flags_|flags_yf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_yf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_yf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~13 ( -// Equation(s): -// \z80_|alu_control_|db[5]~13_combout = (\z80_|alu_flags_|flags_yf~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|flags_yf~q & (!\z80_|execute_|ctl_flags_oe~2_combout & -// ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) - - .dataa(\z80_|alu_flags_|flags_yf~q ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|out[6]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~13 .lut_mask = 16'hAF8C; -defparam \z80_|alu_control_|db[5]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~14 ( -// Equation(s): -// \z80_|alu_control_|db[5]~14_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~13_combout & ((\z80_|reg_file_|gdfx_temp0[5]~72_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|sw1_|db_down[5]~0_combout ), - .datab(\z80_|alu_control_|db[5]~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~14 .lut_mask = 16'h8088; -defparam \z80_|alu_control_|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( -// Equation(s): -// \z80_|alu_control_|db[5]~15_combout = ((\z80_|alu_control_|db[5]~14_combout & ((\z80_|alu_|db[5]~25_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_|db[5]~25_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[5]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hDF55; -defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N10 -cycloneive_lcell_comb \D[0]~107 ( -// Equation(s): -// \D[0]~107_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout ) # ((!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nRD_out~2_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|memory_ifc_|nRD_out~2_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[0]~107_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~107 .lut_mask = 16'hFF40; -defparam \D[0]~107 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y9_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: M9K_X22_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .lut_mask = 16'hDC98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y23_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hF838; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y29_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; -// synopsys translate_on - -// Location: M9K_X33_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'hE10F8B8C100323720BEBBDEBB81DF13FF97B252E2CB4F27BA091FBD0002D1A611E1EDBBC716D44D2912B80041C44558060CFCF15955C0D780DD5E71393920844F25E16C87C5D0308EEC52C011514BBC13AFA1028924D0C7CE738105BD47A10AA5B5C1D9D4193E4339F492B0E1A64E13AE35BE6B67AC8057BDACC155F14E906A017A1841358335450D4B26CD2A21B3D8F2211080B81EC040D7FA0B51CD48008112508062020A02490900092D2040259108806A328F4006D2AA514B42FB006ECCCCB9A360865678449975A8AE72B5C0F7BA800C1B5DC55D7D6FE2EF4EED85D00AB111821321BA426A4FE4956B43595832C271E83E060341AE5F2023FC808177383; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h1A2955372D510AC266A5445146E27000020C320FAE1557E37154040A13202DC6F40B840FB9A59B6DBB296562CB6220EFBE99D2776A202044D9101006FD221D305519198C859000004012AFF4FB060307C92BB732203BFDFEFFFFFFDFFF87FCFFFBFFEFF03FFE0FFFBFAFE0FF80787FFF7FFF83F7F87003FFBFFFFBFFFBFF0FFC0FF81FFF7FFBFFDFFFBFFFE1FF0086F3141AAB6005810A0621595A893F9D85983B9254954341968BAC8C141C90938C05B2C9CD267E11650407375FEDD6A2FEB346AAF6CFDC0791AA97B741995A3B3981E06D1A44D3711955197BB9910FCA20744915C84D6C24BAF53929814CA8A4697E8F4201145AE7415DC122A5F010436107; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h02E84F969E3C800AC610D276182020227809001A50DDDBA3487BB6AE802BA06509312DA0E620656EAF24D57C08FFB14D289613DC32083803B84DC6415FD5EDC000300A8D128FA20030ACCBAFA237B7024504D36A4BA26081137F059E78991154FE2AC2A884A8CC7FBBB21C851CC92B12E15593C0C020FFEE066558590E882D5B67459F1A8C3240FE4E6A8D028C0C088FCF471D400A19B38211004DD122212288B111114514CB11840E04828849C621392041163C00808C67223422F00110201DD18FCFFFF3FFE7F9FFFFFFF82C0B422D214711E08904524A069491774E663F48F665955B4E2C63DAC0078652D10120900298F7EE380092442AFD400BEC43C003; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; -// synopsys translate_on - -// Location: M9K_X33_Y29_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80000001C000000160F000FF70C0007F78C00000F05001007870010010000000000800000038000000F000000070000000300000006000000000000040000000F00000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000001D108000BEDA9FA9698A000000000000000000000000FFFFFFFF408102048004188297E014DA9FA9E9CA00000000000000000000000000000000FFFFFFFC800400CA972208DA9FA9CD8E00000000000000000000000000000000FFFFFFFC8004046A97A289FA9FA9CDC20000000000000000000000007FFFFFFC8000000280040E2A97A2997A9DA9CFC20000000000000000000000007FFFFFFE8000000280042EB28002BE369DA9274200000000000000000000000040810206BFFFFFFE9FE430A29D82AC3E8009E34A000000000000000000000000000000023FFFFFFC9FE4B1829FA2800E8009436A; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h9FE8334E88F827C697F88D1600A80A44809E8FC2B86999C2B85B3A82B1D32A869FE8336A88F807CA97F88F96A0A80EC2838E8D42B9E98FC2B86B3B82B0D7B2D2800832E288F827CA97F88B82A0080EC683869542B939B8C2B1AB0F8290B730C2800826EA8878078297F88AD2A0280EC283E694C2B83A3BC2A3AB3E8291A316AA800826EE881807C69DE8ABD6A0280BC282209CD2BA2A3D42A2737F82918314E2800806E6981805C69D48AED6A1E80BCA82709FC2BB223DC2A07B7F8295DF11C2800886E6980805869848AAC6A1E42DC281789DC2BBAA3DC6A02B7582955F00928008A6EE98082D9618088AC8A0F40FC289E89DC2BBCA3DC2A18B7782154F02F0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N0 -cycloneive_lcell_comb \Mux2~0 ( -// Equation(s): -// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .cin(gnd), - .combout(\Mux2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Mux2~0 .lut_mask = 16'hBA98; -defparam \Mux2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N2 -cycloneive_lcell_comb \Mux2~1 ( -// Equation(s): -// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datad(\Mux2~0_combout ), - .cin(gnd), - .combout(\Mux2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Mux2~1 .lut_mask = 16'hBBC0; -defparam \Mux2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N20 -cycloneive_lcell_comb \D[5]~110 ( -// Equation(s): -// \D[5]~110_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux2~1_combout ))))) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) - - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\Mux2~1_combout ), - .cin(gnd), - .combout(\D[5]~110_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~110 .lut_mask = 16'hAEA2; -defparam \D[5]~110 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N28 -cycloneive_lcell_comb \D[5]~85 ( -// Equation(s): -// \D[5]~85_combout = (\D[5]~84_combout & (\D[5]~110_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & (((\z80_|data_pins_|dout [5])) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout ))) - - .dataa(\D[5]~84_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\z80_|data_pins_|dout [5]), - .datad(\D[5]~110_combout ), - .cin(gnd), - .combout(\D[5]~85_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~85 .lut_mask = 16'hF351; -defparam \D[5]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N24 -cycloneive_lcell_comb \D[5]~99 ( -// Equation(s): -// \D[5]~99_combout = (\D[5]~85_combout ) # (!\D[0]~107_combout ) - - .dataa(\D[0]~107_combout ), - .datab(gnd), - .datac(gnd), - .datad(\D[5]~85_combout ), - .cin(gnd), - .combout(\D[5]~99_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~99 .lut_mask = 16'hFF55; -defparam \D[5]~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N14 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[5]~15_combout ) # ((\D[5]~99_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[5]~99_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[5]~99_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N15 -dffeas \z80_|data_pins_|dout[5] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( -// Equation(s): -// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|data_pins_|dout [5]), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hF300; -defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( -// Equation(s): -// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|alu_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[5]~14_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[5]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hF755; -defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N13 -dffeas \z80_|ir_|opcode[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[5]~15_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N20 +// Location: LCCOMB_X37_Y7_N24 cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( // Equation(s): -// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|ir_|opcode [5] & -// ((\z80_|pla_decode_|Equal3~2_combout )))) +// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|ir_|opcode [5] & +// \z80_|pla_decode_|Equal3~2_combout )))) - .dataa(\z80_|ir_|opcode [5]), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|pla_decode_|Equal3~2_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~2_combout ), .cin(gnd), .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h3350; +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2722; defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y15_N21 +// Location: LCCOMB_X37_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T2_ff~q & +// (((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hF222; +defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y7_N25 dffeas \z80_|decode_state_|DFFE_inst4 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), @@ -40825,7174 +6760,2555 @@ defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y18_N4 -cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( +// Location: LCCOMB_X37_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( // Equation(s): -// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q ) +// \z80_|execute_|fMWrite~3_combout = (!\z80_|execute_|ctl_mRead~5_combout & (((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )) # (!\z80_|pla_decode_|Equal50~0_combout ))) - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(gnd), + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|pla_decode_|Equal50~0_combout ), .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(gnd), + .datad(\z80_|decode_state_|DFFE_inst4~q ), .cin(gnd), - .combout(\z80_|decode_state_|use_ixiy~combout ), + .combout(\z80_|execute_|fMWrite~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFAFA; -defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h5551; +defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( +// Location: LCCOMB_X40_Y13_N0 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( // Equation(s): -// \z80_|execute_|ctl_mRead~23_combout = (!\z80_|decode_state_|use_ixiy~combout & (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) +// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~23_combout ), + .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88C0; +defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( -// Equation(s): -// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMWrite~3_combout )) - - .dataa(\z80_|execute_|ctl_mRead~23_combout ), - .datab(\z80_|execute_|fMWrite~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( -// Equation(s): -// \z80_|execute_|fMRead~31_combout = (\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|pla_decode_|Equal33~3_combout ) # (\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( -// Equation(s): -// \z80_|execute_|fMRead~29_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((\z80_|ir_|opcode [6]) # (\z80_|ir_|opcode [7])))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC800; -defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( -// Equation(s): -// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~9_combout ) # ((\z80_|execute_|fMRead~29_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|fMRead~29_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( -// Equation(s): -// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|nextM~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( -// Equation(s): -// \z80_|execute_|fMRead~32_combout = ((\z80_|execute_|fMRead~31_combout ) # ((\z80_|execute_|fMRead~30_combout ) # (\z80_|execute_|fMRead~28_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .datab(\z80_|execute_|fMRead~31_combout ), - .datac(\z80_|execute_|fMRead~30_combout ), - .datad(\z80_|execute_|fMRead~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (\z80_|execute_|ctl_inc_cy~77_combout & \z80_|execute_|ctl_inc_cy~53_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datab(\z80_|execute_|ctl_inc_cy~77_combout ), - .datac(\z80_|execute_|ctl_inc_cy~53_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( -// Equation(s): -// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_mRead~23_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_ir_we~12_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~23_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( -// Equation(s): -// \z80_|execute_|fMRead~10_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0100; -defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( -// Equation(s): -// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|pc_inc_hold~28_combout )) - - .dataa(\z80_|execute_|ctl_mRead~23_combout ), - .datab(\z80_|execute_|pc_inc_hold~28_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|nextM~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~9 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( -// Equation(s): -// \z80_|execute_|fMRead~11_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|fMRead~9_combout )) # (!\z80_|execute_|fMRead~10_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|fMRead~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|fMRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hAAA2; -defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( -// Equation(s): -// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~12 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( -// Equation(s): -// \z80_|execute_|fMRead~13_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|fMRead~12_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|ctl_mRead~6_combout )))) - - .dataa(\z80_|execute_|fMRead~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|fMWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~13 .lut_mask = 16'h00FE; -defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( -// Equation(s): -// \z80_|execute_|fMRead~15_combout = (\z80_|execute_|fMRead~11_combout ) # ((\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|fMRead~14_combout ), - .datab(\z80_|execute_|fMRead~11_combout ), - .datac(\z80_|execute_|fMRead~13_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~15 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( -// Equation(s): -// \z80_|execute_|fMRead~20_combout = (((\z80_|execute_|fMRead~15_combout ) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|fMRead~19_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .datab(\z80_|execute_|fMRead~19_combout ), - .datac(\z80_|execute_|fMRead~15_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~20 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~48 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~48_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~48 .lut_mask = 16'hE0C0; -defparam \z80_|execute_|pc_inc_hold~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( -// Equation(s): -// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_mRead~17_combout & (\z80_|execute_|ctl_mRead~18_combout & -// ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( -// Equation(s): -// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|fMRead~2_combout ))) - - .dataa(\z80_|execute_|fMRead~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|fMRead~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~21 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( -// Equation(s): -// \z80_|execute_|fMRead~23_combout = ((\z80_|execute_|pc_inc_hold~48_combout ) # ((\z80_|execute_|fMRead~22_combout ) # (\z80_|execute_|fMRead~21_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|pc_inc_hold~48_combout ), - .datac(\z80_|execute_|fMRead~22_combout ), - .datad(\z80_|execute_|fMRead~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( -// Equation(s): -// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~26 .lut_mask = 16'hCCEC; -defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( -// Equation(s): -// \z80_|execute_|fMRead~25_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ctl_mRead~14_combout ))) # (!\z80_|execute_|fMRead~24_combout ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|fMRead~24_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~25 .lut_mask = 16'h2F0F; -defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( -// Equation(s): -// \z80_|execute_|fMRead~27_combout = ((\z80_|execute_|fMRead~25_combout ) # ((\z80_|execute_|fMRead~26_combout & \z80_|execute_|ctl_ir_we~4_combout ))) # (!\z80_|execute_|fMRead~3_combout ) - - .dataa(\z80_|execute_|fMRead~26_combout ), - .datab(\z80_|execute_|fMRead~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|fMRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~27 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( -// Equation(s): -// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~32_combout ) # ((\z80_|execute_|fMRead~20_combout ) # ((\z80_|execute_|fMRead~23_combout ) # (\z80_|execute_|fMRead~27_combout ))) - - .dataa(\z80_|execute_|fMRead~32_combout ), - .datab(\z80_|execute_|fMRead~20_combout ), - .datac(\z80_|execute_|fMRead~23_combout ), - .datad(\z80_|execute_|fMRead~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( -// Equation(s): -// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((\z80_|execute_|fMRead~34_combout & !\z80_|execute_|fMRead~0_combout ))) - - .dataa(\z80_|execute_|fMRead~34_combout ), - .datab(\z80_|execute_|fMRead~33_combout ), - .datac(\z80_|execute_|fMRead~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFFCE; -defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(gnd), - .datab(\z80_|execute_|fMRead~35_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFC0; -defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: M9K_X33_Y18_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N28 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .lut_mask = 16'hDC98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y19_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y20_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N16 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout )) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hEC64; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y24_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y32_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; -// synopsys translate_on - -// Location: M9K_X33_Y21_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; -// synopsys translate_on - -// Location: M9K_X33_Y22_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X32_Y18_N0 -cycloneive_lcell_comb \Selector1~0 ( -// Equation(s): -// \Selector1~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .cin(gnd), - .combout(\Selector1~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector1~0 .lut_mask = 16'hBA98; -defparam \Selector1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y18_N2 -cycloneive_lcell_comb \Selector1~1 ( -// Equation(s): -// \Selector1~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector1~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector1~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector1~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datad(\Selector1~0_combout ), - .cin(gnd), - .combout(\Selector1~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector1~1 .lut_mask = 16'hBBC0; -defparam \Selector1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y18_N12 -cycloneive_lcell_comb \D[1]~103 ( -// Equation(s): -// \D[1]~103_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Selector1~1_combout -// ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), - .datad(\Selector1~1_combout ), - .cin(gnd), - .combout(\D[1]~103_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~103 .lut_mask = 16'hF2D0; -defparam \D[1]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X18_Y34_N1 -cycloneive_io_ibuf \PS2_DAT~input ( - .i(PS2_DAT), - .ibar(gnd), - .o(\PS2_DAT~input_o )); -// synopsys translate_off -defparam \PS2_DAT~input .bus_hold = "false"; -defparam \PS2_DAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: CLKCTRL_G5 -cycloneive_clkctrl \reset~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\reset~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\reset~clkctrl_outclk )); -// synopsys translate_off -defparam \reset~clkctrl .clock_type = "global clock"; -defparam \reset~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [2])) # (!\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [0]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; -defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X9_Y34_N8 -cycloneive_io_ibuf \PS2_CLK~input ( - .i(PS2_CLK), - .ibar(gnd), - .o(\PS2_CLK~input_o )); -// synopsys translate_off -defparam \PS2_CLK~input .bus_hold = "false"; -defparam \PS2_CLK~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\PS2_CLK~input_o ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N1 -dffeas \ula_|ps2_keyboard_|clk_filter[7] ( +// Location: FF_X40_Y13_N1 +dffeas \z80_|sequencer_|DFFE_M4_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [7]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N7 -dffeas \ula_|ps2_keyboard_|clk_filter[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N20 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N21 -dffeas \ula_|ps2_keyboard_|clk_filter[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N18 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N19 -dffeas \ula_|ps2_keyboard_|clk_filter[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [6] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [5] & !\ula_|ps2_keyboard_|clk_filter [4]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [6]), - .datab(\ula_|ps2_keyboard_|clk_filter [7]), - .datac(\ula_|ps2_keyboard_|clk_filter [5]), - .datad(\ula_|ps2_keyboard_|clk_filter [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N3 -dffeas \ula_|ps2_keyboard_|clk_filter[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N29 -dffeas \ula_|ps2_keyboard_|clk_filter[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N23 -dffeas \ula_|ps2_keyboard_|clk_filter[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N16 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|clk_filter [2] & (!\ula_|ps2_keyboard_|clk_filter [1] & !\ula_|ps2_keyboard_|clk_filter [3]))) - - .dataa(\ula_|ps2_keyboard_|Equal0~0_combout ), - .datab(\ula_|ps2_keyboard_|clk_filter [2]), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0002; -defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N10 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N11 -dffeas \ula_|ps2_keyboard_|clk_filter[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFC30; -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N27 -dffeas \ula_|ps2_keyboard_|ps2_clk_in ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N4 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0C00; -defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N5 -dffeas \ula_|ps2_keyboard_|clk_edge ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_edge~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y21_N3 -dffeas \ula_|ps2_keyboard_|bit_count[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [2]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; -defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N1 -dffeas \ula_|ps2_keyboard_|bit_count[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N16 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [1] & -// (!\ula_|ps2_keyboard_|bit_count [2] & (\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [3]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h1810; -defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N17 -dffeas \ula_|ps2_keyboard_|bit_count[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [3] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [3] & -// ((\ula_|ps2_keyboard_|bit_count [1] $ (\ula_|ps2_keyboard_|bit_count [0])))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h0750; -defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N27 -dffeas \ula_|ps2_keyboard_|bit_count[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [3] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [2]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\PS2_DAT~input_o ), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|always1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [1]) # (\ula_|ps2_keyboard_|bit_count [2]))) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCCC0; -defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (\ula_|ps2_keyboard_|clk_edge~q & (!\ula_|ps2_keyboard_|LessThan0~0_combout & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) - - .dataa(\ula_|ps2_keyboard_|always1~0_combout ), - .datab(\ula_|ps2_keyboard_|bit_count [0]), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h00D0; -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N9 -dffeas \ula_|ps2_keyboard_|shiftreg[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\PS2_DAT~input_o ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N15 -dffeas \ula_|ps2_keyboard_|shiftreg[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [8]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N5 -dffeas \ula_|ps2_keyboard_|shiftreg[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [7]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N11 -dffeas \ula_|ps2_keyboard_|shiftreg[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [6]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N11 -dffeas \ula_|ps2_keyboard_|shiftreg[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [5]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N25 -dffeas \ula_|ps2_keyboard_|shiftreg[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [4]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N29 -dffeas \ula_|ps2_keyboard_|shiftreg[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [3]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N1 -dffeas \ula_|ps2_keyboard_|shiftreg[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [2]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N17 -dffeas \ula_|ps2_keyboard_|shiftreg[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [1]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|Equal0~0_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( -// Equation(s): -// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|extended~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hF300; -defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|shiftreg [8]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|WideXor0~0_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .datad(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hC33C; -defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|LessThan0~0_combout & (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|WideXor0~2_combout ))) - - .dataa(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .datab(\PS2_DAT~input_o ), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N9 -dffeas \ula_|ps2_keyboard_|scan_code_ready ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|scan_code_ready~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y20_N1 -dffeas \ula_|zx_keyboard_|extended ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|extended~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|extended~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|extended .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~15 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~15_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & !\ula_|ps2_keyboard_|shiftreg [7])) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~15 .lut_mask = 16'h0202; -defparam \ula_|zx_keyboard_|keys[0][0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[0][0]~15_combout )) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0500; -defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][1]~36_combout & \ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( -// Equation(s): -// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & -// (((\ula_|zx_keyboard_|released~q )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|released~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hC8F0; -defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N19 -dffeas \ula_|zx_keyboard_|released ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|released~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|released~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|released .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|zx_keyboard_|WideOr17~0_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(\ula_|zx_keyboard_|WideOr17~0_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # -// (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|shifted~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|zx_keyboard_|shifted~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y21_N3 -dffeas \ula_|zx_keyboard_|shifted ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|shifted~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|shifted~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|shifted .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hFF88; -defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~38_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'h0003; -defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~39_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[5][1]~38_combout & (!\ula_|zx_keyboard_|keys[5][1]~35_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~38_combout & -// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~35_combout ), - .datac(\ula_|zx_keyboard_|keys[5][1]~q ), - .datad(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N19 -dffeas \ula_|zx_keyboard_|keys[5][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~31 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~31_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~31 .lut_mask = 16'h00CC; -defparam \ula_|zx_keyboard_|keys[4][1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~23 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~23_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q )) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~23 .lut_mask = 16'h1010; -defparam \ula_|zx_keyboard_|keys[7][1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~32 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~32_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~32 .lut_mask = 16'h000C; -defparam \ula_|zx_keyboard_|keys[7][2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~33 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~33_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[7][2]~32_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~33 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[5][2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~34 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~34_combout = (\ula_|zx_keyboard_|keys[4][1]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[4][1]~q -// )))) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~34 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N9 -dffeas \ula_|zx_keyboard_|keys[4][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N24 -cycloneive_lcell_comb \D[1]~30 ( -// Equation(s): -// \D[1]~30_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][1]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~30 .lut_mask = 16'hBB0B; -defparam \D[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~24 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~24_combout = (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~24 .lut_mask = 16'hA0A0; -defparam \ula_|zx_keyboard_|keys[5][4]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~28_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~24_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~29 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~29_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~29 .lut_mask = 16'h00C0; -defparam \ula_|zx_keyboard_|keys[3][1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~30 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~30_combout = (\ula_|zx_keyboard_|keys[3][1]~28_combout & ((\ula_|zx_keyboard_|keys[3][1]~29_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[3][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~30 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N17 -dffeas \ula_|zx_keyboard_|keys[3][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~25 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~25 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[1][4]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~26 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~26_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & \ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~26 .lut_mask = 16'h4040; -defparam \ula_|zx_keyboard_|keys[2][1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~27 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~27_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # -// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][1]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~27 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[2][1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N17 -dffeas \ula_|zx_keyboard_|keys[2][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][1]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [10]), - .datad(\ula_|zx_keyboard_|keys[2][1]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hF3FF; -defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'hCCCF; -defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h0060; -defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~17 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~17_combout = (\ula_|zx_keyboard_|keys[0][1]~16_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [4])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~17 .lut_mask = 16'h2040; -defparam \ula_|zx_keyboard_|keys[0][1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~18 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~18_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~17_combout & (!\ula_|zx_keyboard_|keys[0][1]~14_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~17_combout & -// ((\ula_|zx_keyboard_|keys[0][1]~q ))))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .datac(\ula_|zx_keyboard_|keys[0][1]~q ), - .datad(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~18 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y21_N7 -dffeas \ula_|zx_keyboard_|keys[0][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~19 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|scan_code_ready~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~19 .lut_mask = 16'h0100; -defparam \ula_|zx_keyboard_|keys[7][4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~20 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~20_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~20 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[6][4]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~21 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~21_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~21 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[1][1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~22 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~22_combout = (\ula_|zx_keyboard_|keys[1][1]~21_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][1]~21_combout & (\ula_|zx_keyboard_|keys[1][1]~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[1][1]~21_combout ), - .datac(\ula_|zx_keyboard_|keys[1][1]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~22 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[1][1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N13 -dffeas \ula_|zx_keyboard_|keys[1][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N2 -cycloneive_lcell_comb \D[1]~28 ( -// Equation(s): -// \D[1]~28_combout = (\ula_|zx_keyboard_|keys[0][1]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) # (!\ula_|zx_keyboard_|keys[0][1]~q & -// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][1]~q ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\ula_|zx_keyboard_|keys[1][1]~q ), - .cin(gnd), - .combout(\D[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~28 .lut_mask = 16'hD0DD; -defparam \D[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N26 -cycloneive_lcell_comb \D[1]~29 ( -// Equation(s): -// \D[1]~29_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~28_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][1]~q ), - .datab(\ula_|zx_keyboard_|key_row~0_combout ), - .datac(\z80_|address_pins_|abus[11]~19_combout ), - .datad(\D[1]~28_combout ), - .cin(gnd), - .combout(\D[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~29 .lut_mask = 16'hC400; -defparam \D[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~41_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[0][0]~15_combout ))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h0240; -defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~43 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~43_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[6][1]~42_combout )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~43 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[6][1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'hEAEA; -defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~44 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~44_combout = (\ula_|zx_keyboard_|keys[6][1]~43_combout & ((!\ula_|zx_keyboard_|keys[6][1]~40_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~43_combout & (\ula_|zx_keyboard_|keys[6][1]~q )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\ula_|zx_keyboard_|keys[6][1]~40_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~44 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[6][1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N25 -dffeas \ula_|zx_keyboard_|keys[6][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~45 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~45_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [7]))) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [7]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~45 .lut_mask = 16'h0002; -defparam \ula_|zx_keyboard_|keys[7][1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & -// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h0A38; -defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h0044; -defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h0140; -defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~4_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & (!\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|WideOr16~4_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'hF022; -defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~7_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~5_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|WideOr16~5_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|WideOr16~7_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hF808; -defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~46 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~46_combout = (\ula_|zx_keyboard_|keys[7][1]~45_combout & ((\ula_|zx_keyboard_|WideOr16~6_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~6_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # -// (!\ula_|zx_keyboard_|keys[7][1]~45_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][1]~q ), - .datad(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~46 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N31 -dffeas \ula_|zx_keyboard_|keys[7][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N20 -cycloneive_lcell_comb \D[1]~31 ( -// Equation(s): -// \D[1]~31_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][1]~q & -// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[6][1]~q ), - .datac(\z80_|address_pins_|abus[15]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[7][1]~q ), - .cin(gnd), - .combout(\D[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~31 .lut_mask = 16'hB0BB; -defparam \D[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N18 -cycloneive_lcell_comb \D[1]~32 ( -// Equation(s): -// \D[1]~32_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~30_combout & (\D[1]~29_combout & \D[1]~31_combout ))) - - .dataa(\D[1]~30_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[1]~29_combout ), - .datad(\D[1]~31_combout ), - .cin(gnd), - .combout(\D[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~32 .lut_mask = 16'hECCC; -defparam \D[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N4 -cycloneive_lcell_comb \D[1]~33 ( -// Equation(s): -// \D[1]~33_combout = ((\Equal2~0_combout & ((\D[1]~32_combout ))) # (!\Equal2~0_combout & (\D[1]~103_combout ))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[1]~103_combout ), - .datad(\D[1]~32_combout ), - .cin(gnd), - .combout(\D[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~33 .lut_mask = 16'hFB73; -defparam \D[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N8 -cycloneive_lcell_comb \D[1]~34 ( -// Equation(s): -// \D[1]~34_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout & \z80_|data_pins_|dout [1])))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[1]~33_combout ), - .datad(\z80_|data_pins_|dout [1]), - .cin(gnd), - .combout(\D[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~34 .lut_mask = 16'hF151; -defparam \D[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N18 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[1]~11_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[1]~11_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\D[1]~34_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N19 -dffeas \z80_|data_pins_|dout[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N30 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( -// Equation(s): -// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N24 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~11 ( -// Equation(s): -// \z80_|bus_control_|db[1]~11_combout = ((\z80_|bus_control_|db[1]~10_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(\z80_|data_pins_|dout [1]), - .datac(\z80_|bus_control_|db[1]~10_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'hD0FF; -defparam \z80_|bus_control_|db[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N14 -cycloneive_lcell_comb \z80_|ir_|opcode[1]~feeder ( -// Equation(s): -// \z80_|ir_|opcode[1]~feeder_combout = \z80_|bus_control_|db[1]~11_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[1]~11_combout ), - .cin(gnd), - .combout(\z80_|ir_|opcode[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|ir_|opcode[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|ir_|opcode[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N15 -dffeas \z80_|ir_|opcode[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|ir_|opcode[1]~feeder_combout ), + .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0005; -defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hC080; -defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~3_combout = (\z80_|execute_|ctl_alu_op_low~28_combout & (\z80_|pla_decode_|Equal64~0_combout & ((\z80_|pla_decode_|Equal9~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|pla_decode_|Equal64~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|pla_decode_|Equal61~2_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h001F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & -// (((!\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'h153F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'h8000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h0088; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h4000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_flags_cf_cpl~2_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'h040C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout = (((!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .lut_mask = 16'h777F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'h0F0C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hC0E0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hAAA8; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_flags_nf_we~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & !\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ))) - - .dataa(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'h0008; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal62~2_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'h20A0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal21~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'hCECC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|execute_|ctl_alu_op_low~32_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFFEF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N24 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~20_combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ) - - .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'hFFB3; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout = (\z80_|execute_|ctl_state_alu~12_combout & ((\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|ir_|opcode [3] & ((!\z80_|ir_|opcode [5]))))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .lut_mask = 16'h8500; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~21_combout )) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hF0AA; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_control_|out[6]~2_combout )) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|out[6]~2_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hFA50; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout & ((!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout -// & ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h11D8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~3_combout & (\z80_|execute_|ctl_flags_cf2_sel_daa~combout $ ((!\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'h99F8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y9_N31 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .q(\z80_|sequencer_|DFFE_M4_ff~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; +defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( +// Location: LCCOMB_X37_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( // Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~10_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h0B00; -defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~14_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~11_combout ) # (((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout )) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout )) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ))) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hF0E4; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout & \z80_|execute_|ctl_alu_op_low~28_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .lut_mask = 16'hFEFA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~10_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_alu_op_low~12_combout ))) +// \z80_|execute_|fMWrite~2_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .lut_mask = 16'hFF40; -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~10_combout ) # ((\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~19_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~5_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_alu_op_low~12_combout ) # (\z80_|execute_|ctl_state_alu~7_combout )))) # (!\z80_|execute_|ctl_state_alu~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_state_alu~15_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_state_alu~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h3F3B; -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal68~2_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|pla_decode_|Equal68~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hAA20; -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFF32; -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_set~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_set~0_combout = (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~12_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_set~0 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_flags_cf_set~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hC0CC; -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~9_combout = (\z80_|execute_|ctl_flags_cf_cpl~8_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|execute_|ctl_flags_cf_set~0_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .datac(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N4 -cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( -// Equation(s): -// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~9_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_cf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0C48; -defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~8 ( -// Equation(s): -// \z80_|alu_control_|db[0]~8_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((\z80_|bus_control_|db[0]~17_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|bus_control_|db[0]~17_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~8 .lut_mask = 16'h22A2; -defparam \z80_|alu_control_|db[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N20 -cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( -// Equation(s): -// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~19_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_|db[0]~19_combout ), - .cin(gnd), - .combout(\z80_|sw2_|db_up[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hFF0F; -defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N4 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~9 ( -// Equation(s): -// \z80_|alu_control_|db[0]~9_combout = (\z80_|alu_control_|db[0]~8_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[0]~8_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|sw2_|db_up[0]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~9 .lut_mask = 16'h8A00; -defparam \z80_|alu_control_|db[0]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~12 ( -// Equation(s): -// \z80_|alu_control_|db[0]~12_combout = ((\z80_|alu_control_|db[0]~9_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|db[0]~9_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~12 .lut_mask = 16'hB0FF; -defparam \z80_|alu_control_|db[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~67 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~67_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~67 .lut_mask = 16'hFF50; -defparam \ula_|zx_keyboard_|keys[5][0]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~81 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~81_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~81_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~81 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[5][0]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~82 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~82_combout = (\ula_|zx_keyboard_|keys[5][0]~81_combout & (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~81_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~82 .lut_mask = 16'h2800; -defparam \ula_|zx_keyboard_|keys[5][0]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~83 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~83_combout = (\ula_|zx_keyboard_|keys[5][0]~82_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~82_combout & ((\ula_|zx_keyboard_|keys[5][0]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .datab(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .datac(\ula_|zx_keyboard_|keys[5][0]~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), .datad(gnd), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~83_combout ), + .combout(\z80_|execute_|fMWrite~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~83 .lut_mask = 16'h7474; -defparam \ula_|zx_keyboard_|keys[5][0]~83 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h2F2F; +defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y20_N11 -dffeas \ula_|zx_keyboard_|keys[5][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][0]~83_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~84 ( +// Location: LCCOMB_X38_Y11_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~84_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [3])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~84_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~84 .lut_mask = 16'h0160; -defparam \ula_|zx_keyboard_|keys[4][0]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~85 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~85_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~85 .lut_mask = 16'hBABA; -defparam \ula_|zx_keyboard_|keys[4][0]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~86 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~86_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[4][0]~84_combout & ((!\ula_|zx_keyboard_|keys[4][0]~85_combout ))) # (!\ula_|zx_keyboard_|keys[4][0]~84_combout & -// (\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datab(\ula_|zx_keyboard_|keys[4][0]~84_combout ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~86 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][0]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N27 -dffeas \ula_|zx_keyboard_|keys[4][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N20 -cycloneive_lcell_comb \D[0]~49 ( -// Equation(s): -// \D[0]~49_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][0]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][0]~q ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[0]~49_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~49 .lut_mask = 16'hBB0B; -defparam \D[0]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [5] & ((\ula_|ps2_keyboard_|shiftreg [6])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & -// (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'h8810; -defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~76 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~76_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout )) # (!\ula_|zx_keyboard_|WideOr4~0_combout ))) - - .dataa(\ula_|zx_keyboard_|WideOr4~0_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~76_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~76 .lut_mask = 16'h3313; -defparam \ula_|zx_keyboard_|keys~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~73 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~73_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~73_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~73 .lut_mask = 16'hF000; -defparam \ula_|zx_keyboard_|keys[4][3]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~47 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~47_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~47 .lut_mask = 16'h0808; -defparam \ula_|zx_keyboard_|keys[6][4]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// ((\ula_|ps2_keyboard_|shiftreg [2]))))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0310; -defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~74 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~74_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~74_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~74 .lut_mask = 16'h353F; -defparam \ula_|zx_keyboard_|keys~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~75 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~75_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][3]~73_combout & !\ula_|zx_keyboard_|keys~74_combout )) # (!\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~73_combout ), - .datab(\ula_|zx_keyboard_|keys~74_combout ), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~75_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~75 .lut_mask = 16'h2F00; -defparam \ula_|zx_keyboard_|keys[0][0]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~77 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~77_combout = (\ula_|zx_keyboard_|keys~76_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) # (!\ula_|zx_keyboard_|keys~76_combout & ((\ula_|zx_keyboard_|keys[0][0]~75_combout & ((!\ula_|zx_keyboard_|released~q ))) # -// (!\ula_|zx_keyboard_|keys[0][0]~75_combout & (\ula_|zx_keyboard_|keys[0][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys~76_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~75_combout ), - .datac(\ula_|zx_keyboard_|keys[0][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~77_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~77 .lut_mask = 16'hB0F4; -defparam \ula_|zx_keyboard_|keys[0][0]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N15 -dffeas \ula_|zx_keyboard_|keys[0][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][0]~77_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~71 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~71_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~71_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~71 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[1][0]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~72 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~72_combout = (\ula_|zx_keyboard_|keys[1][0]~71_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][0]~71_combout & (\ula_|zx_keyboard_|keys[1][0]~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[1][0]~71_combout ), - .datac(\ula_|zx_keyboard_|keys[1][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~72 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[1][0]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N17 -dffeas \ula_|zx_keyboard_|keys[1][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N30 -cycloneive_lcell_comb \D[0]~47 ( -// Equation(s): -// \D[0]~47_combout = (\ula_|zx_keyboard_|keys[0][0]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~q & -// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~q ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\ula_|zx_keyboard_|keys[1][0]~q ), - .cin(gnd), - .combout(\D[0]~47_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~47 .lut_mask = 16'hD0DD; -defparam \D[0]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~80 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][0]~80_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # -// (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][0]~80_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0]~80 .lut_mask = 16'hB1F0; -defparam \ula_|zx_keyboard_|keys[2][0]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N23 -dffeas \ula_|zx_keyboard_|keys[2][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][0]~80_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~78 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~78 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|keys[3][0]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~79 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~79_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & ((\ula_|zx_keyboard_|keys[3][1]~28_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (\ula_|zx_keyboard_|keys[3][0]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][0]~78_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~79 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[3][0]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N5 -dffeas \ula_|zx_keyboard_|keys[3][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~1_combout = ((\z80_|address_pins_|DFFE_apin_latch [11]) # (!\ula_|zx_keyboard_|keys[3][0]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [11]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hFF3F; -defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N4 -cycloneive_lcell_comb \D[0]~48 ( -// Equation(s): -// \D[0]~48_combout = (\D[0]~47_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][0]~q )))) - - .dataa(\D[0]~47_combout ), - .datab(\z80_|address_pins_|abus[10]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|key_row~1_combout ), - .cin(gnd), - .combout(\D[0]~48_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~48 .lut_mask = 16'h8A00; -defparam \D[0]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~91 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~91_combout = (\ula_|zx_keyboard_|shifted~1_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[6][0]~90_combout & \ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|shifted~1_combout ), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[6][0]~90_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~91 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[6][0]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~92 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~92_combout = (\ula_|zx_keyboard_|keys[6][0]~91_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][0]~91_combout & ((\ula_|zx_keyboard_|keys[6][0]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][0]~q ), - .datad(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~92 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[6][0]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N21 -dffeas \ula_|zx_keyboard_|keys[6][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~63 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~63_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~63 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[5][4]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h0303; -defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[5][4]~63_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|WideOr16~3_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~132 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~132_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~132_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~132 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[7][0]~132 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~88 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~88_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & ((\ula_|zx_keyboard_|keys[7][0]~87_combout ) # (\ula_|zx_keyboard_|keys[7][0]~132_combout )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .datad(\ula_|zx_keyboard_|keys[7][0]~132_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~88 .lut_mask = 16'h8880; -defparam \ula_|zx_keyboard_|keys[7][0]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~89 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~89_combout = (\ula_|zx_keyboard_|keys[7][0]~88_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][0]~88_combout & (\ula_|zx_keyboard_|keys[7][0]~q )) - - .dataa(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~89 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[7][0]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N7 -dffeas \ula_|zx_keyboard_|keys[7][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N28 -cycloneive_lcell_comb \D[0]~50 ( -// Equation(s): -// \D[0]~50_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][0]~q & -// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[6][0]~q ), - .datac(\z80_|address_pins_|abus[15]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[7][0]~q ), - .cin(gnd), - .combout(\D[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~50 .lut_mask = 16'hB0BB; -defparam \D[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N10 -cycloneive_lcell_comb \D[0]~51 ( -// Equation(s): -// \D[0]~51_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~49_combout & (\D[0]~48_combout & \D[0]~50_combout ))) - - .dataa(\D[0]~49_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[0]~48_combout ), - .datad(\D[0]~50_combout ), - .cin(gnd), - .combout(\D[0]~51_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~51 .lut_mask = 16'hECCC; -defparam \D[0]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y16_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N14 -cycloneive_lcell_comb \D[0]~55 ( -// Equation(s): -// \D[0]~55_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\D[0]~55_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~55 .lut_mask = 16'hE3E0; -defparam \D[0]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N22 -cycloneive_lcell_comb \D[0]~56 ( -// Equation(s): -// \D[0]~56_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~55_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout )) # (!\D[0]~55_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~55_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[0]~55_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .cin(gnd), - .combout(\D[0]~56_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~56 .lut_mask = 16'hBCB0; -defparam \D[0]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y28_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X22_Y30_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; -// synopsys translate_on - -// Location: M9K_X22_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N4 -cycloneive_lcell_comb \D[0]~52 ( -// Equation(s): -// \D[0]~52_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\z80_|address_pins_|abus[14]~23_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .cin(gnd), - .combout(\D[0]~52_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~52 .lut_mask = 16'hF858; -defparam \D[0]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y20_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N28 -cycloneive_lcell_comb \D[0]~53 ( -// Equation(s): -// \D[0]~53_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout $ ((\D[0]~52_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & (((!\D[0]~52_combout & -// \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datab(\z80_|address_pins_|abus[15]~22_combout ), - .datac(\D[0]~52_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\D[0]~53_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~53 .lut_mask = 16'h4B48; -defparam \D[0]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N16 -cycloneive_lcell_comb \D[0]~54 ( -// Equation(s): -// \D[0]~54_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~52_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~52_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & !\D[0]~53_combout )) # (!\D[0]~52_combout & ((\D[0]~53_combout ))))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[0]~52_combout ), - .datad(\D[0]~53_combout ), - .cin(gnd), - .combout(\D[0]~54_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~54 .lut_mask = 16'hC3E0; -defparam \D[0]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N8 -cycloneive_lcell_comb \D[0]~106 ( -// Equation(s): -// \D[0]~106_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[0]~56_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[0]~54_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[0]~56_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[0]~56_combout ), - .datad(\D[0]~54_combout ), - .cin(gnd), - .combout(\D[0]~106_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~106 .lut_mask = 16'hF4B0; -defparam \D[0]~106 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N14 -cycloneive_lcell_comb \D[0]~57 ( -// Equation(s): -// \D[0]~57_combout = ((\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout )))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~1_combout ), - .datab(\D[0]~51_combout ), - .datac(\D[0]~106_combout ), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[0]~57_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~57 .lut_mask = 16'hDDF5; -defparam \D[0]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N0 -cycloneive_lcell_comb \D[0]~58 ( -// Equation(s): -// \D[0]~58_combout = (\D[0]~57_combout & (((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[0]~57_combout & (!\Equal2~1_combout & ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [0]), - .datac(\D[0]~57_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[0]~58_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~58 .lut_mask = 16'hC0F5; -defparam \D[0]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N0 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[0]~17_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[0]~17_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\D[0]~58_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N1 -dffeas \z80_|data_pins_|dout[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N4 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( -// Equation(s): -// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(\z80_|data_pins_|dout [0]), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'hC0CC; -defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( -// Equation(s): -// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|alu_control_|db[0]~12_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~16_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'hDF55; -defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y13_N27 -dffeas \z80_|ir_|opcode[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[0]~17_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) +// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2])) .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), .cin(gnd), - .combout(\z80_|pla_decode_|Equal63~0_combout ), + .combout(\z80_|pla_decode_|Equal13~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; +defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( +// Location: LCCOMB_X38_Y11_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( // Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) +// \z80_|pla_decode_|Equal13~2_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .combout(\z80_|pla_decode_|Equal13~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N20 -cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( +// Location: LCCOMB_X36_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( // Equation(s): -// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h070F; -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( -// Equation(s): -// \z80_|alu_control_|db[6]~10_combout = ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|execute_|ctl_flags_oe~2_combout )) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) - - .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|execute_|ctl_flags_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hFFF5; -defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( -// Equation(s): -// \z80_|alu_control_|db[6]~11_combout = (\z80_|alu_control_|db[6]~10_combout ) # ((\z80_|execute_|ctl_sw_1d~7_combout ) # (\z80_|execute_|ctl_reg_out_lo~8_combout )) - - .dataa(\z80_|alu_control_|db[6]~10_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFEFE; -defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( -// Equation(s): -// \z80_|alu_control_|db[4]~30_combout = (\z80_|alu_|db[4]~17_combout & (\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|reg_file_|gdfx_temp0[4]~62_combout ))) # (!\z80_|alu_|db[4]~17_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((\z80_|execute_|ctl_reg_out_lo~8_combout & !\z80_|reg_file_|gdfx_temp0[4]~62_combout )))) - - .dataa(\z80_|alu_|db[4]~17_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h5D0C; -defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( -// Equation(s): -// \z80_|alu_control_|db[4]~31_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[4]~30_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_flags_|flags_hf~combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_control_|db[4]~30_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h00B0; -defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( -// Equation(s): -// \z80_|alu_control_|db[4]~32_combout = ((\z80_|alu_control_|db[4]~31_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|alu_control_|db[4]~31_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'hBF33; -defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~119 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~119_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & -// (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~119_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~119 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[2][4]~119 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~120 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~120_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][4]~119_combout & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|zx_keyboard_|keys[2][4]~119_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~120_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~120 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[2][4]~120 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~95 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~95_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~95_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~95 .lut_mask = 16'hAFAA; -defparam \ula_|zx_keyboard_|keys[2][4]~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~121 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~121_combout = (\ula_|zx_keyboard_|keys[2][4]~120_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[2][4]~120_combout & (\ula_|zx_keyboard_|keys[2][4]~q )) - - .dataa(\ula_|zx_keyboard_|keys[2][4]~120_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~121_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~121 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[2][4]~121 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N23 -dffeas \ula_|zx_keyboard_|keys[2][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][4]~121_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~117 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~117_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~117_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~117 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|keys[3][4]~117 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~136 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~136_combout = (\ula_|zx_keyboard_|keys[3][4]~117_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[3][4]~117_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~136_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~136 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[3][4]~136 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~130 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~130_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~130_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~130 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[3][4]~130 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~118 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~118_combout = (\ula_|zx_keyboard_|keys[3][4]~136_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[3][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~136_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][4]~136_combout ), - .datac(\ula_|zx_keyboard_|keys[3][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~118 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][4]~118 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N9 -dffeas \ula_|zx_keyboard_|keys[3][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N18 -cycloneive_lcell_comb \D[4]~78 ( -// Equation(s): -// \D[4]~78_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # ((!\ula_|zx_keyboard_|keys[2][4]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][4]~q & -// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\z80_|address_pins_|abus[10]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~q ), - .cin(gnd), - .combout(\D[4]~78_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~78 .lut_mask = 16'h8ACF; -defparam \D[4]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~126 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~126_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~126 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[6][4]~126 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~128 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~128_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~128_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~128 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[5][4]~128 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~129 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~129_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[5][4]~128_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~128_combout & -// (\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~128_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~129_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~129 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][4]~129 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y19_N9 -dffeas \ula_|zx_keyboard_|keys[5][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][4]~129_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~127 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~127_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~20_combout & ((\ula_|zx_keyboard_|keys[6][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~127_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~127 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[6][4]~127 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N5 -dffeas \ula_|zx_keyboard_|keys[6][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][4]~127_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~51 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~51_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~51 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[7][4]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~125 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~125_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~51_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) -// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~1_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~125_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~125 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][4]~125 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N11 -dffeas \ula_|zx_keyboard_|keys[7][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][4]~125_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N30 -cycloneive_lcell_comb \D[4]~79 ( -// Equation(s): -// \D[4]~79_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\z80_|address_pins_|abus[14]~23_combout ) # ((!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][4]~q & -// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\z80_|address_pins_|abus[14]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~q ), - .cin(gnd), - .combout(\D[4]~79_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~79 .lut_mask = 16'h8ACF; -defparam \D[4]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~122 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q )) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & -// \ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~122 .lut_mask = 16'h4422; -defparam \ula_|zx_keyboard_|keys[4][4]~122 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~123 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~123_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][4]~122_combout ))) - - .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~123 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][4]~123 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & ((\ula_|zx_keyboard_|keys[4][4]~123_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~123_combout & ((\ula_|zx_keyboard_|keys[4][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[4][4]~q ), - .datad(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N25 -dffeas \ula_|zx_keyboard_|keys[4][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\ula_|zx_keyboard_|keys[4][4]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|execute_|ixy_d~4_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_T3_ff~q )) .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [12]), - .datad(\ula_|zx_keyboard_|keys[4][4]~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~3_combout ), + .combout(\z80_|execute_|ixy_d~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hF3FF; -defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h000C; +defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y19_N8 -cycloneive_lcell_comb \D[4]~80 ( +// Location: LCCOMB_X38_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( // Equation(s): -// \D[4]~80_combout = (\D[4]~79_combout & (\ula_|zx_keyboard_|key_row~3_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) +// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) - .dataa(\ula_|zx_keyboard_|keys[5][4]~q ), - .datab(\D[4]~79_combout ), - .datac(\z80_|address_pins_|abus[13]~20_combout ), - .datad(\ula_|zx_keyboard_|key_row~3_combout ), - .cin(gnd), - .combout(\D[4]~80_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~80 .lut_mask = 16'hC400; -defparam \D[4]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~111 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~111_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|zx_keyboard_|released~q ), + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), .datab(gnd), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~111_combout ), + .combout(\z80_|execute_|fIOWrite~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~111 .lut_mask = 16'hFAAA; -defparam \ula_|zx_keyboard_|keys[0][4]~111 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hAA0A; +defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~97 ( +// Location: LCCOMB_X38_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~97_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~97 .lut_mask = 16'h0060; -defparam \ula_|zx_keyboard_|keys[0][4]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~116 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~116_combout = (\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & (!\ula_|zx_keyboard_|keys[0][4]~111_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & -// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~116_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~116 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][4]~116 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N11 -dffeas \ula_|zx_keyboard_|keys[0][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][4]~116_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~115 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~115_combout = (\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[1][4]~q )))) # -// (!\ula_|zx_keyboard_|Equal0~2_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) - - .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[1][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~115_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~115 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][4]~115 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N7 -dffeas \ula_|zx_keyboard_|keys[1][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][4]~115_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N28 -cycloneive_lcell_comb \D[4]~77 ( -// Equation(s): -// \D[4]~77_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][4]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][4]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[1][4]~q ), - .cin(gnd), - .combout(\D[4]~77_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~77 .lut_mask = 16'h8ACF; -defparam \D[4]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N26 -cycloneive_lcell_comb \D[4]~81 ( -// Equation(s): -// \D[4]~81_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~78_combout & (\D[4]~80_combout & \D[4]~77_combout ))) - - .dataa(\z80_|address_pins_|abus[0]~16_combout ), - .datab(\D[4]~78_combout ), - .datac(\D[4]~80_combout ), - .datad(\D[4]~77_combout ), - .cin(gnd), - .combout(\D[4]~81_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~81 .lut_mask = 16'hEAAA; -defparam \D[4]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y1_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; -// synopsys translate_on - -// Location: M9K_X22_Y22_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y3_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; -// synopsys translate_on - -// Location: M9K_X22_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N2 -cycloneive_lcell_comb \Selector4~0 ( -// Equation(s): -// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .cin(gnd), - .combout(\Selector4~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector4~0 .lut_mask = 16'hBA98; -defparam \Selector4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N26 -cycloneive_lcell_comb \Selector4~1 ( -// Equation(s): -// \Selector4~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector4~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # (!\Selector4~0_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector4~0_combout )))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datad(\Selector4~0_combout ), - .cin(gnd), - .combout(\Selector4~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector4~1 .lut_mask = 16'hF388; -defparam \Selector4~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y16_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y3_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N20 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .lut_mask = 16'hE5E0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N10 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .lut_mask = 16'hAFC0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N6 -cycloneive_lcell_comb \D[4]~109 ( -// Equation(s): -// \D[4]~109_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\Selector4~1_combout -// )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ))))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\Selector4~1_combout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), - .cin(gnd), - .combout(\D[4]~109_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~109 .lut_mask = 16'hFB40; -defparam \D[4]~109 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N18 -cycloneive_lcell_comb \D[4]~97 ( -// Equation(s): -// \D[4]~97_combout = ((\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout )))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\D[4]~81_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[4]~109_combout ), - .cin(gnd), - .combout(\D[4]~97_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~97 .lut_mask = 16'hDF8F; -defparam \D[4]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N30 -cycloneive_lcell_comb \D[4]~98 ( -// Equation(s): -// \D[4]~98_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [4] & ((\D[4]~97_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[4]~97_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[4]~97_combout ), - .cin(gnd), - .combout(\D[4]~98_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~98 .lut_mask = 16'hBB03; -defparam \D[4]~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N24 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[4]~19_combout ) # ((\D[4]~98_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[4]~98_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[4]~98_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N25 -dffeas \z80_|data_pins_|dout[4] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N20 -cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( -// Equation(s): -// \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[4]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'h88CC; -defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N18 -cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( -// Equation(s): -// \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[4]~18_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hDF55; -defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N19 -dffeas \z80_|ir_|opcode[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[4]~19_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~0_combout = (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) +// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) .dataa(gnd), .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~0_combout ), + .combout(\z80_|execute_|ctl_mWrite~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( +// Location: LCCOMB_X34_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( // Equation(s): -// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) +// \z80_|execute_|fMRead~2_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~5_combout ), + .combout(\z80_|execute_|fMRead~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h3F0F; +defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N22 +// Location: LCCOMB_X34_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~2_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~2 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_state_alu~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~11_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N2 cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( // Equation(s): -// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|fMRead~0_combout )))) +// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|fMRead~2_combout )))) - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), - .datad(\z80_|execute_|fMRead~0_combout ), + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|fMRead~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), .cin(gnd), .combout(\z80_|execute_|fIOWrite~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hFB00; defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( +// Location: LCCOMB_X39_Y7_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( // Equation(s): -// \z80_|execute_|fIOWrite~3_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) +// \z80_|pla_decode_|Equal2~0_combout = (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h00CC; +defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N2 +cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( +// Equation(s): +// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instCB~q ) # (\z80_|decode_state_|DFFE_instED~q ) + + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|decode_state_|DFFE_instED~q ), + .cin(gnd), + .combout(\z80_|decode_state_|table_xx~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; +defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|table_xx~0_combout & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~0_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~3 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~3_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~3 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( +// Equation(s): +// \z80_|execute_|fIOWrite~3_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), .cin(gnd), .combout(\z80_|execute_|fIOWrite~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3F0F; +defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3B3B; defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y18_N2 +// Location: LCCOMB_X39_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( +// Equation(s): +// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hF000; +defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N16 cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( // Equation(s): -// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) +// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|fIOWrite~3_combout ), + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|fIOWrite~3_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), .cin(gnd), .combout(\z80_|execute_|fIOWrite~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hA8AA; +defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hCC8C; defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N4 +// Location: LCCOMB_X38_Y13_N4 cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( // Equation(s): -// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~5_combout ))) +// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~3_combout ))) .dataa(\z80_|execute_|fIOWrite~1_combout ), - .datab(\z80_|execute_|ctl_mRead~5_combout ), - .datac(\z80_|execute_|fIOWrite~2_combout ), + .datab(\z80_|execute_|fIOWrite~2_combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), .datad(\z80_|execute_|fIOWrite~4_combout ), .cin(gnd), .combout(\z80_|execute_|fIOWrite~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFFEC; defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( +// Location: LCCOMB_X37_Y8_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~11_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) +// \z80_|pin_control_|bus_db_pin_oe~4_combout = (!\z80_|execute_|fIOWrite~5_combout & ((\z80_|execute_|fMWrite~2_combout ) # ((\z80_|execute_|fMWrite~3_combout & !\z80_|pla_decode_|Equal13~2_combout )))) - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mWrite~10_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .dataa(\z80_|execute_|fMWrite~3_combout ), + .datab(\z80_|execute_|fMWrite~2_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|fIOWrite~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~11_combout ), + .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; +defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'h00CE; +defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( +// Location: LCCOMB_X40_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~3 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~12_combout = (\z80_|execute_|ctl_mWrite~8_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) +// \z80_|execute_|ctl_state_alu~3_combout = (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~3 .lut_mask = 16'h0C0C; +defparam \z80_|execute_|ctl_state_alu~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~1_combout = (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h3300; +defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~6_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~4_combout = (\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; +defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0100; +defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~46_combout = ((!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|execute_|ctl_mWrite~6_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~46_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2u~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal19~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal34~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h0400; +defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|comb~0 ( +// Equation(s): +// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|comb~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~0 .lut_mask = 16'hCC00; +defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal47~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|execute_|comb~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~45_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & +// (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (\z80_|execute_|ctl_inc_cy~45_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal19~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_inc_cy~45_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N10 +cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( +// Equation(s): +// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|M5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88C0; +defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N11 +dffeas \z80_|sequencer_|M5 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|M5~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|M5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|M5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( +// Equation(s): +// \z80_|execute_|ixy_d~7_combout = (\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h00AA; +defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~44_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ctl_alu_oe~2_combout & +// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_inc_cy~44_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|ctl_inc_cy~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q )) + + .dataa(gnd), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0300; +defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~14_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~7_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N24 +cycloneive_lcell_comb \z80_|execute_|fMWrite~0 ( +// Equation(s): +// \z80_|execute_|fMWrite~0_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~0 .lut_mask = 16'h0001; +defparam \z80_|execute_|fMWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~97 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~97_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~97_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~97 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~96 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~96_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal19~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~96_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~96 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~98 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~98_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~98_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~98 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~98_combout & (((!\z80_|execute_|ctl_alu_op_low~14_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_inc_cy~98_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_inc_cy~97_combout & (\z80_|execute_|ctl_inc_cy~96_combout & \z80_|execute_|ctl_inc_cy~48_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~97_combout ), + .datab(\z80_|execute_|ctl_inc_cy~96_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_cy~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|fMWrite~1 ( +// Equation(s): +// \z80_|execute_|fMWrite~1_combout = (\z80_|sequencer_|M5~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|sequencer_|M5~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # +// (\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~1 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMWrite~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N18 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|execute_|ctl_bus_inc_oe~28_combout & ((\z80_|execute_|fMWrite~0_combout ) # (!\z80_|execute_|fMWrite~1_combout ))) + + .dataa(\z80_|execute_|fMWrite~0_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .datac(gnd), + .datad(\z80_|execute_|fMWrite~1_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'h88CC; +defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N4 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|execute_|ctl_inc_cy~47_combout & (\z80_|execute_|ctl_apin_mux~0_combout & \z80_|pin_control_|bus_db_pin_oe~3_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .datab(\z80_|execute_|ctl_inc_cy~47_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~6_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|execute_|ctl_mRead~6_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h153F; +defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~7_combout = (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N22 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|pin_control_|bus_db_pin_oe~6_combout & ((\z80_|execute_|ixy_d~4_combout ) # ((!\z80_|execute_|ctl_mWrite~7_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )))) + + .dataa(\z80_|execute_|ixy_d~4_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'hB0F0; +defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~17 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~17_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~17 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_mWrite~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( +// Equation(s): +// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|ctl_mWrite~17_combout & (!\z80_|execute_|ctl_mWrite~6_combout & !\z80_|execute_|ctl_mRead~5_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_mWrite~11_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~12_combout ), + .combout(\z80_|execute_|fMWrite~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h0003; +defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( +// Location: LCCOMB_X37_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~9_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) +// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - .dataa(\z80_|execute_|ctl_mWrite~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datac(\z80_|execute_|ctl_mWrite~9_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~13_combout ), + .combout(\z80_|execute_|ctl_state_alu~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( +// Location: LCCOMB_X39_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) +// \z80_|execute_|ctl_inc_cy~49_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout +// & (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~14_combout ), + .combout(\z80_|execute_|ctl_inc_cy~49_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N28 +// Location: LCCOMB_X36_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~49_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~49_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~4_combout ) # ((!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|fMWrite~4_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_inc_dec~2_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'hCD00; +defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( +// Equation(s): +// \z80_|execute_|fMWrite~8_combout = (\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ctl_alu_oe~2_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (\z80_|execute_|ctl_mRead~8_combout & +// ((\z80_|execute_|ctl_alu_oe~2_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~51 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~51_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~51 .lut_mask = 16'hABFF; +defparam \z80_|execute_|ctl_bus_inc_oe~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|M5~q )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~15_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hABFF; +defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal46~0_combout = (\z80_|ir_|opcode [2] & (\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [0] & \z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal46~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~10_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~45_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'hF3F7; +defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [7]), + .datac(gnd), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0033; +defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|decode_state_|DFFE_instCB~q )))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~29_combout = (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout ))) # (!\z80_|execute_|ctl_alu_oe~2_combout & (((!\z80_|execute_|ixy_d~7_combout )) # +// (!\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h1357; +defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|ctl_alu_core_S~10_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & \z80_|execute_|ctl_bus_inc_oe~29_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_S~10_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal55~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0044; +defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout )) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~7_combout & ((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & +// (((!\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ctl_bus_inc_oe~51_combout & (\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|execute_|ctl_bus_inc_oe~31_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~51_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N6 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~17 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~17_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~17 .lut_mask = 16'h1333; +defparam \z80_|pin_control_|bus_db_pin_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( +// Equation(s): +// \z80_|execute_|fIOWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h3733; +defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N0 +cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( +// Equation(s): +// \z80_|execute_|fMWrite~6_combout = ((\z80_|pla_decode_|Equal46~0_combout ) # ((!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) # (!\z80_|execute_|ctl_ir_we~5_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'hF7F5; +defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( +// Equation(s): +// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h3737; +defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N0 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|execute_|fIOWrite~0_combout & ((\z80_|execute_|fMWrite~6_combout ) # ((\z80_|execute_|fMWrite~5_combout )))) # (!\z80_|execute_|fIOWrite~0_combout & (!\z80_|execute_|ctl_mWrite~8_combout & +// ((\z80_|execute_|fMWrite~6_combout ) # (\z80_|execute_|fMWrite~5_combout )))) + + .dataa(\z80_|execute_|fIOWrite~0_combout ), + .datab(\z80_|execute_|fMWrite~6_combout ), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|execute_|fMWrite~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'hAF8C; +defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( +// Equation(s): +// \z80_|execute_|fMRead~3_combout = ((!\z80_|execute_|ctl_ir_we~5_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|ir_|opcode [7]) + + .dataa(\z80_|ir_|opcode [7]), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h5FFF; +defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~4_combout & \z80_|execute_|fMRead~3_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~4_combout )) # +// (!\z80_|execute_|ctl_alu_oe~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|fMRead~3_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h1F15; +defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N24 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~8_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & +// (((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~5_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h0777; +defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N6 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~17_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~10_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~17_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|execute_|comb~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'h0313; +defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_reg_sel_wz~6_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|M5~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout = (\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~8_combout & +// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .lut_mask = 16'h0537; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( +// Equation(s): +// \z80_|execute_|fMWrite~7_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # (\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|pin_control_|bus_db_pin_oe~12_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & !\z80_|execute_|fMWrite~7_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .datad(\z80_|execute_|fMWrite~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h0080; +defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N2 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (!\z80_|execute_|fMWrite~8_combout & (\z80_|execute_|ctl_bus_inc_oe~32_combout & \z80_|pin_control_|bus_db_pin_oe~13_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .datab(\z80_|execute_|fMWrite~8_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'h2000; +defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~15 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~15_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout & (\z80_|pin_control_|bus_db_pin_oe~5_combout & (\z80_|pin_control_|bus_db_pin_oe~7_combout & \z80_|pin_control_|bus_db_pin_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~15 .lut_mask = 16'h4000; +defparam \z80_|pin_control_|bus_db_pin_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N8 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'hFCFC; +defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~16 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~16_combout = (\z80_|sequencer_|DFFE_T4_ff~q & ((\z80_|execute_|fIOWrite~5_combout ) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout & \z80_|pin_control_|bus_db_pin_oe~2_combout )))) # (!\z80_|sequencer_|DFFE_T4_ff~q & +// (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (\z80_|pin_control_|bus_db_pin_oe~2_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .datad(\z80_|execute_|fIOWrite~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~16 .lut_mask = 16'hBA30; +defparam \z80_|pin_control_|bus_db_pin_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|nextM~4 ( +// Equation(s): +// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout ) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~4 .lut_mask = 16'h373F; +defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( +// Equation(s): +// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_eval_cond~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h0A0A; +defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~12_combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_iorw~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|ctl_mWrite~17_combout ))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|nextM~4_combout ), + .datad(\z80_|execute_|ctl_iorw~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y11_N21 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_iorw~9_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y11_N17 +dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N14 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorq~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_iorq~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_iorq~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y11_N15 +dffeas \z80_|memory_ifc_|wait_iorq ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorq~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y11_N23 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorq~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N22 +cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( +// Equation(s): +// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) + + .dataa(gnd), + .datab(\z80_|memory_ifc_|wait_iorq~q ), + .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|iorq~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; +defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'hA000; +defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( +// Equation(s): +// \z80_|execute_|ixy_d~17_combout = (\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|decode_state_|DFFE_instIY1~q & !\z80_|decode_state_|DFFE_inst4~q )))) # (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|decode_state_|DFFE_instIY1~q & +// !\z80_|decode_state_|DFFE_inst4~q )) # (!\z80_|pla_decode_|Equal50~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~2_combout ), + .datab(\z80_|pla_decode_|Equal50~0_combout ), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h111F; +defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N14 cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~15_combout = ((\z80_|execute_|ctl_mWrite~14_combout ) # ((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout ))) # (!\z80_|execute_|ctl_mWrite~13_combout ) +// \z80_|execute_|ctl_mWrite~15_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~7_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|execute_|ctl_mWrite~7_combout ))) - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|execute_|ctl_mWrite~13_combout ), - .datac(\z80_|execute_|ctl_mWrite~14_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_mWrite~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hF7F3; +defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hEAC0; defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N29 +// Location: LCCOMB_X34_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~18 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~18_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal11~0_combout & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~18 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_mWrite~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~12_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~21 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~21_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~21 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_flags_alu~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~20 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~20_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~20 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~10_combout = (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~10_combout = (\z80_|execute_|ctl_flags_alu~21_combout & (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & \z80_|execute_|ctl_flags_alu~10_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~21_combout ), + .datab(\z80_|execute_|ctl_flags_alu~20_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_mWrite~10_combout & ((!\z80_|execute_|ctl_mWrite~8_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~12_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|execute_|ctl_mWrite~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( +// Equation(s): +// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~9_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~12_combout = (\z80_|execute_|ctl_inc_cy~51_combout & (((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|execute_|ctl_inc_cy~51_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (\z80_|execute_|ctl_inc_dec~12_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_inc_dec~2_combout ), + .datac(\z80_|execute_|ctl_inc_dec~12_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~11_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0A2A; +defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~25_combout = (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~22 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~22_combout = (((!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~22 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_flags_alu~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~24_combout = (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~22_combout & (((!\z80_|execute_|ctl_mRead~25_combout & !\z80_|execute_|ctl_mRead~24_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~25_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ctl_flags_alu~22_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_mWrite~13_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~11_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~11_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( +// Equation(s): +// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|execute_|ctl_mWrite~15_combout ) # (((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout )) # (!\z80_|execute_|ctl_mWrite~14_combout )) + + .dataa(\z80_|execute_|ixy_d~17_combout ), + .datab(\z80_|execute_|ctl_mWrite~15_combout ), + .datac(\z80_|execute_|ctl_mWrite~14_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'hDFCF; +defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N1 dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mWrite~15_combout ), + .d(\z80_|execute_|ctl_mWrite~16_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -48008,7 +9324,7 @@ defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N4 +// Location: LCCOMB_X37_Y14_N12 cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( // Equation(s): // \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q @@ -48025,7 +9341,7 @@ defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N5 +// Location: FF_X37_Y14_N13 dffeas \z80_|memory_ifc_|wait_mwr ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), @@ -48044,15 +9360,32 @@ defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; // synopsys translate_on -// Location: FF_X43_Y17_N17 +// Location: LCCOMB_X40_Y11_N20 +cycloneive_lcell_comb \z80_|memory_ifc_|mwr_wr~feeder ( +// Equation(s): +// \z80_|memory_ifc_|mwr_wr~feeder_combout = \z80_|memory_ifc_|wait_mwr~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|wait_mwr~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|mwr_wr~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|mwr_wr~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|mwr_wr~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y11_N21 dffeas \z80_|memory_ifc_|mwr_wr ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_mwr~q ), + .d(\z80_|memory_ifc_|mwr_wr~feeder_combout ), + .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), @@ -48063,1063 +9396,1523 @@ defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N16 +// Location: LCCOMB_X40_Y11_N24 cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( // Equation(s): -// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|memory_ifc_|iorq~0_combout )) +// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIOWrite~5_combout )) - .dataa(\z80_|execute_|fIOWrite~5_combout ), - .datab(\z80_|memory_ifc_|iorq~0_combout ), - .datac(\z80_|memory_ifc_|mwr_wr~q ), + .dataa(\z80_|memory_ifc_|iorq~0_combout ), + .datab(\z80_|memory_ifc_|mwr_wr~q ), + .datac(\z80_|execute_|fIOWrite~5_combout ), .datad(gnd), .cin(gnd), .combout(\z80_|memory_ifc_|nWR_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hF8F8; +defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hECEC; defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N4 -cycloneive_lcell_comb \D[5]~84 ( -// Equation(s): -// \D[5]~84_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\D[5]~84_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~84 .lut_mask = 16'h0040; -defparam \D[5]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y5_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: M9K_X33_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N14 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # -// ((\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// (\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .lut_mask = 16'hBA98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N4 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hF858; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y24_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y30_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; -// synopsys translate_on - -// Location: M9K_X22_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; -// synopsys translate_on - -// Location: M9K_X33_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N18 -cycloneive_lcell_comb \Mux0~0 ( -// Equation(s): -// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .cin(gnd), - .combout(\Mux0~0_combout ), - .cout()); -// synopsys translate_off -defparam \Mux0~0 .lut_mask = 16'hBA98; -defparam \Mux0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N12 -cycloneive_lcell_comb \Mux0~1 ( -// Equation(s): -// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\Mux0~0_combout ), - .cin(gnd), - .combout(\Mux0~1_combout ), - .cout()); -// synopsys translate_off -defparam \Mux0~1 .lut_mask = 16'hBBC0; -defparam \Mux0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N22 -cycloneive_lcell_comb \D[7]~112 ( -// Equation(s): -// \D[7]~112_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Mux0~1_combout ))) -// # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), - .datad(\Mux0~1_combout ), - .cin(gnd), - .combout(\D[7]~112_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~112 .lut_mask = 16'hF4B0; -defparam \D[7]~112 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N30 -cycloneive_lcell_comb \D[7]~94 ( -// Equation(s): -// \D[7]~94_combout = (\D[5]~84_combout & (\D[7]~112_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & ((\z80_|data_pins_|dout [7]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\D[5]~84_combout ), - .datab(\z80_|data_pins_|dout [7]), - .datac(\D[7]~112_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[7]~94_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~94 .lut_mask = 16'hC4F5; -defparam \D[7]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N26 -cycloneive_lcell_comb \D[7]~102 ( -// Equation(s): -// \D[7]~102_combout = (\D[7]~94_combout ) # (!\D[0]~107_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\D[7]~94_combout ), - .datad(\D[0]~107_combout ), - .cin(gnd), - .combout(\D[7]~102_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~102 .lut_mask = 16'hF0FF; -defparam \D[7]~102 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N26 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\D[7]~102_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[7]~7_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[7]~102_combout & (\z80_|bus_control_|db[7]~7_combout -// & ((\z80_|execute_|ctl_bus_db_we~7_combout )))) - - .dataa(\D[7]~102_combout ), - .datab(\z80_|bus_control_|db[7]~7_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hECA0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N27 -dffeas \z80_|data_pins_|dout[7] ( +// Location: FF_X40_Y11_N17 +dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .d(\z80_|execute_|setM1~53_combout ), .asdata(vcc), - .clrn(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|data_pins_|dout [7]), + .q(\z80_|memory_ifc_|DFFE_m1_ff1~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[7] .power_up = "low"; +defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N2 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( +// Location: LCCOMB_X40_Y11_N8 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( // Equation(s): -// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) +// \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q .dataa(gnd), - .datab(\z80_|alu_control_|db[7]~18_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_m1_ff1~q ), .cin(gnd), - .combout(\z80_|bus_control_|db[7]~5_combout ), + .combout(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N8 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( -// Equation(s): -// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|data_pins_|dout [7]), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|bus_control_|db[7]~5_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[7]~7_combout ), - .cout()); +// Location: FF_X40_Y11_N9 +dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), + .prn(vcc)); // synopsys translate_off -defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hBF0F; -defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; // synopsys translate_on -// Location: FF_X32_Y13_N21 -dffeas \z80_|ir_|opcode[7] ( +// Location: FF_X40_Y11_N7 +dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|bus_control_|db[7]~7_combout ), + .asdata(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [7]), + .q(\z80_|memory_ifc_|DFFE_m1_ff3~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[7] .power_up = "low"; +defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y13_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( +// Location: LCCOMB_X40_Y11_N6 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( // Equation(s): -// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) +// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # ((\z80_|memory_ifc_|DFFE_m1_ff3~q )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & +// (!\z80_|interrupts_|DFFE_inst44~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # (\z80_|memory_ifc_|DFFE_m1_ff3~q )))) - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), + .datac(\z80_|memory_ifc_|DFFE_m1_ff3~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~0_combout ), + .combout(\z80_|memory_ifc_|nRD_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0010; -defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hA8FC; +defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( +// Location: LCCOMB_X29_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~2 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|pla_decode_|Equal77~0_combout & (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~1_combout ))) +// \z80_|execute_|ctl_mRead~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal2~0_combout ))) - .dataa(\z80_|pla_decode_|Equal77~0_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal2~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~5_combout ), + .combout(\z80_|execute_|ctl_mRead~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( +// Location: LCCOMB_X38_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( // Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_ir_we~4_combout & (\z80_|pla_decode_|Equal8~0_combout & !\z80_|ir_|opcode [3]))) +// \z80_|execute_|fIORead~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hC080; +defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h0033; +defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~15_combout = (\z80_|execute_|ctl_mWrite~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal1~4_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( +// Equation(s): +// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hC080; +defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( +// Equation(s): +// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|ctl_alu_op_low~15_combout ) # ((\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|fIOWrite~0_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~10_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datac(\z80_|execute_|fIOWrite~0_combout ), + .datad(\z80_|execute_|fIORead~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFFCE; +defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( +// Equation(s): +// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|ctl_mRead~2_combout & \z80_|execute_|fIOWrite~1_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|fIORead~0_combout ), + .datac(\z80_|execute_|fIOWrite~1_combout ), + .datad(\z80_|execute_|fIORead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hAA00; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( +// Equation(s): +// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_im_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N23 +dffeas \z80_|interrupts_|im2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_im_we~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|im2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~10_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|im2~q ), + .datac(gnd), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~1_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ctl_mRead~30_combout ) # ((\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mRead~10_combout ), + .datac(\z80_|execute_|ctl_mRead~30_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'hFCF0; +defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|execute_|ctl_ir_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [1]) # ((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~4_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFCF; +defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal44~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal44~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0010; +defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~6_combout = (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|DFFE_inst4~q ))) + + .dataa(\z80_|pla_decode_|Equal44~0_combout ), + .datab(\z80_|decode_state_|DFFE_instIY1~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( +// Equation(s): +// \z80_|execute_|fMRead~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|pla_decode_|Equal13~2_combout )) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMRead~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0202; +defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~17_combout = (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|fMWrite~0_combout & \z80_|execute_|fMRead~5_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|fMWrite~0_combout ), + .datad(\z80_|execute_|fMRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~12_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h00A0; +defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal49~0_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal77~0_combout & !\z80_|decode_state_|in_halt~q )) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal77~0_combout ), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal49~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h0808; +defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~57 ( +// Equation(s): +// \z80_|execute_|setM1~57_combout = (!\z80_|execute_|ctl_mRead~12_combout & (((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )) # (!\z80_|pla_decode_|Equal49~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~57 .lut_mask = 16'h5551; +defparam \z80_|execute_|setM1~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~15_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal25~0_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal25~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_ir_we~6_combout & (\z80_|pla_decode_|Equal55~0_combout & !\z80_|decode_state_|table_xx~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_ir_we~6_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|decode_state_|table_xx~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h3303; +defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( +// Equation(s): +// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( +// Equation(s): +// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) + + .dataa(\z80_|pla_decode_|Equal44~0_combout ), + .datab(\z80_|decode_state_|DFFE_instIY1~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hA080; +defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ixy_d~10_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ctl_mRead~3_combout & !\z80_|execute_|ctl_mRead~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~10_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( +// Equation(s): +// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_al_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0A00; +defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal29~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal29~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~38 ( +// Equation(s): +// \z80_|execute_|setM1~38_combout = (\z80_|execute_|fMRead~4_combout & (!\z80_|pla_decode_|Equal29~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) + + .dataa(\z80_|execute_|fMRead~4_combout ), + .datab(\z80_|pla_decode_|Equal29~0_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|setM1~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~38 .lut_mask = 16'h0202; +defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal35~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; +defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~33_combout = (!\z80_|pla_decode_|Equal35~0_combout & ((\z80_|ir_|opcode [4]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|pla_decode_|Equal24~0_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), .datad(\z80_|ir_|opcode [3]), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .combout(\z80_|execute_|pc_inc_hold~33_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; +defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'h0F0B; +defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( +// Location: LCCOMB_X38_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|comb~1 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) +// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .dataa(gnd), + .datab(\z80_|ir_|opcode [5]), + .datac(gnd), + .datad(\z80_|ir_|opcode [4]), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), + .combout(\z80_|execute_|comb~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; +defparam \z80_|execute_|comb~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( +// Location: LCCOMB_X38_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~8_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|M5~q & ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) +// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|comb~1_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), + .combout(\z80_|execute_|ctl_mRead~13_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h3020; -defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( +// Location: LCCOMB_X38_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) +// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|pla_decode_|Equal41~2_combout ))) - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .dataa(\z80_|execute_|ctl_mRead~13_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( +// Location: LCCOMB_X39_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) +// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|pc_inc_hold~33_combout & (!\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout )) - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), + .dataa(gnd), + .datab(\z80_|execute_|pc_inc_hold~33_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC8C0; -defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0C00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( +// Location: LCCOMB_X36_Y6_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~2 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~6_combout = (((\z80_|execute_|ctl_bus_db_we~4_combout ) # (!\z80_|execute_|ctl_sw_2u~3_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) +// \z80_|pla_decode_|Equal40~2_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [2]))) - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~4_combout ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [2]), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), + .combout(\z80_|pla_decode_|Equal40~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal40~2 .lut_mask = 16'h0010; +defparam \z80_|pla_decode_|Equal40~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( +// Location: LCCOMB_X36_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~36 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~3_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|execute_|ctl_bus_db_we~2_combout ) # (\z80_|execute_|ctl_bus_db_we~6_combout ))) +// \z80_|execute_|setM1~36_combout = (!\z80_|pla_decode_|Equal6~1_combout & (((!\z80_|ir_|opcode [5] & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal40~2_combout ))) - .dataa(\z80_|execute_|ctl_bus_db_we~3_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~6_combout ), + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|pla_decode_|Equal40~2_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), + .combout(\z80_|execute_|setM1~36_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; +defparam \z80_|execute_|setM1~36 .lut_mask = 16'h1115; +defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~50 ( +// Location: LCCOMB_X37_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~14 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) +// \z80_|execute_|pc_inc_hold~14_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|pla_decode_|Equal33~2_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|pla_decode_|Equal50~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~14 .lut_mask = 16'h1115; +defparam \z80_|execute_|pc_inc_hold~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~37 ( +// Equation(s): +// \z80_|execute_|setM1~37_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (\z80_|execute_|setM1~36_combout & (\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datab(\z80_|execute_|setM1~36_combout ), + .datac(\z80_|execute_|pc_inc_hold~14_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~37 .lut_mask = 16'h0080; +defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~14_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~39 ( +// Equation(s): +// \z80_|execute_|setM1~39_combout = (\z80_|execute_|setM1~57_combout & (\z80_|execute_|setM1~38_combout & (\z80_|execute_|setM1~37_combout & !\z80_|execute_|ctl_mRead~14_combout ))) + + .dataa(\z80_|execute_|setM1~57_combout ), + .datab(\z80_|execute_|setM1~38_combout ), + .datac(\z80_|execute_|setM1~37_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0080; +defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((!\z80_|execute_|setM1~39_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|ctl_mRead~17_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|setM1~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0011; +defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal40~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h4040; +defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal37~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|decode_state_|table_xx~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0400; +defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~26_combout = (\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~2_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~16_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal12~0_combout & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal12~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~13_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~19_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~1_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal38~2_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|pla_decode_|Equal35~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~0 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N8 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~1_combout = (\z80_|pla_decode_|Equal24~1_combout ) # ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|reg_control_|reg_sys_we_lo~0_combout ) # (\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal24~1_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~0_combout ), + .datad(\z80_|pla_decode_|Equal29~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~1 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|reg_control_|reg_sys_we_lo~1_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # +// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|reg_control_|reg_sys_we_lo~1_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~1_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'h153F; +defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~18_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~6_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~20_combout = (\z80_|reg_control_|reg_sys_we_lo~2_combout & (((!\z80_|execute_|ctl_mRead~19_combout & !\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~19_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .datad(\z80_|execute_|ctl_mRead~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~22_combout = (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~20_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~16_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datab(\z80_|execute_|ctl_mRead~16_combout ), + .datac(\z80_|execute_|ctl_mRead~20_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~1_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|DFFE_instED~q & !\z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0008; +defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~23_combout = (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_mRead~14_combout & +// (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~14_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~27_combout = (\z80_|execute_|ctl_mRead~23_combout & (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal38~2_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|ctl_mRead~27_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~26_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mRead~22_combout ), + .datad(\z80_|execute_|ctl_mRead~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|nextM~3 ( +// Equation(s): +// \z80_|execute_|nextM~3_combout = (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|pla_decode_|Equal41~2_combout )) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ixy_d~10_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0011; +defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|execute_|nextM~3_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h8F00; +defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~31_combout ) # ((\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_mRead~29_combout ) # (!\z80_|execute_|ctl_mRead~28_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~31_combout ), + .datab(\z80_|execute_|ctl_mRead~32_combout ), + .datac(\z80_|execute_|ctl_mRead~28_combout ), + .datad(\z80_|execute_|ctl_mRead~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y11_N19 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mRead~33_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N28 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q .dataa(gnd), .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~50 .lut_mask = 16'h000F; -defparam \ula_|zx_keyboard_|keys[0][2]~50 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~52 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~52_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[0][2]~50_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[0][2]~50_combout & ((\ula_|zx_keyboard_|keys[0][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[0][2]~q ), - .datad(\ula_|zx_keyboard_|keys[0][2]~50_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~52_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~52 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][2]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N17 -dffeas \ula_|zx_keyboard_|keys[0][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][2]~52_combout ), +// Location: FF_X40_Y11_N29 +dffeas \z80_|memory_ifc_|wait_mrd ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][2]~q ), + .q(\z80_|memory_ifc_|wait_mrd~q ), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; +defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~48 ( +// Location: LCCOMB_X40_Y11_N10 +cycloneive_lcell_comb \z80_|memory_ifc_|DFFE_mrd_ff3~feeder ( // Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~48_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~48 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|keys[3][3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~49 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~49_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[6][4]~47_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout & (\ula_|zx_keyboard_|keys[1][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[1][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .datab(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~49 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][2]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N23 -dffeas \ula_|zx_keyboard_|keys[1][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N22 -cycloneive_lcell_comb \D[2]~35 ( -// Equation(s): -// \D[2]~35_combout = (\z80_|address_pins_|abus[8]~18_combout & (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) # (!\z80_|address_pins_|abus[8]~18_combout & (!\ula_|zx_keyboard_|keys[0][2]~q & -// ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) - - .dataa(\z80_|address_pins_|abus[8]~18_combout ), - .datab(\ula_|zx_keyboard_|keys[0][2]~q ), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\z80_|address_pins_|abus[9]~17_combout ), - .cin(gnd), - .combout(\D[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~35 .lut_mask = 16'hBB0B; -defparam \D[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~57 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~57_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]) +// \z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout = \z80_|memory_ifc_|wait_mrd~q .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(gnd), .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\z80_|memory_ifc_|wait_mrd~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~57_combout ), + .combout(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~57 .lut_mask = 16'h3300; -defparam \ula_|zx_keyboard_|keys[5][2]~57 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~58 ( +// Location: FF_X40_Y11_N11 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|DFFE_mrd_ff3~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N0 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~58_combout = (\ula_|zx_keyboard_|keys[5][2]~57_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[5][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[5][2]~57_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) +// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|wait_mrd~q ) - .dataa(\ula_|zx_keyboard_|keys[5][2]~57_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[5][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), + .dataa(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|wait_mrd~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~58_combout ), + .combout(\z80_|memory_ifc_|nRD_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~58 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][2]~58 .sum_lutc_input = "datac"; +defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0055; +defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y18_N15 -dffeas \ula_|zx_keyboard_|keys[5][2] ( +// Location: LCCOMB_X40_Y11_N12 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~2_combout = (\z80_|memory_ifc_|nRD_out~0_combout ) # (((\z80_|execute_|fIORead~3_combout & \z80_|memory_ifc_|iorq~0_combout )) # (!\z80_|memory_ifc_|nRD_out~1_combout )) + + .dataa(\z80_|memory_ifc_|nRD_out~0_combout ), + .datab(\z80_|execute_|fIORead~3_combout ), + .datac(\z80_|memory_ifc_|iorq~0_combout ), + .datad(\z80_|memory_ifc_|nRD_out~1_combout ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hEAFF; +defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N12 +cycloneive_lcell_comb \Equal2~1 ( +// Equation(s): +// \Equal2~1_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nRD_out~2_combout )) + + .dataa(gnd), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|nRD_out~2_combout ), + .cin(gnd), + .combout(\Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~1 .lut_mask = 16'h3000; +defparam \Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y34_N1 +cycloneive_io_ibuf \PS2_DAT~input ( + .i(PS2_DAT), + .ibar(gnd), + .o(\PS2_DAT~input_o )); +// synopsys translate_off +defparam \PS2_DAT~input .bus_hold = "false"; +defparam \PS2_DAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G9 +cycloneive_clkctrl \reset~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\reset~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\reset~clkctrl_outclk )); +// synopsys translate_off +defparam \reset~clkctrl .clock_type = "global clock"; +defparam \reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N18 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [1] & ((!\ula_|ps2_keyboard_|bit_count [2]) # (!\ula_|ps2_keyboard_|bit_count [3])))) # (!\ula_|ps2_keyboard_|bit_count [0] & +// (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [1]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [1]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h121A; +defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y34_N8 +cycloneive_io_ibuf \PS2_CLK~input ( + .i(PS2_CLK), + .ibar(gnd), + .o(\PS2_CLK~input_o )); +// synopsys translate_off +defparam \PS2_CLK~input .bus_hold = "false"; +defparam \PS2_CLK~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N24 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\PS2_CLK~input_o ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N25 +dffeas \ula_|ps2_keyboard_|clk_filter[7] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][2]~58_combout ), + .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49128,70 +10921,827 @@ dffeas \ula_|zx_keyboard_|keys[5][2] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][2]~q ), + .q(\ula_|ps2_keyboard_|clk_filter [7]), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; +defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~59 ( +// Location: LCCOMB_X17_Y27_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~59_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|extended~q ))) +// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|extended~q ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [7]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~59_combout ), + .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~59 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[4][2]~59 .sum_lutc_input = "datac"; +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~131 ( +// Location: FF_X17_Y27_N3 +dffeas \ula_|ps2_keyboard_|clk_filter[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~131_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[4][2]~59_combout & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [0]))) +// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [6]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N13 +dffeas \ula_|ps2_keyboard_|clk_filter[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N18 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N19 +dffeas \ula_|ps2_keyboard_|clk_filter[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [4]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N11 +dffeas \ula_|ps2_keyboard_|clk_filter[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N20 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [5] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [4] & !\ula_|ps2_keyboard_|clk_filter [6]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [5]), + .datab(\ula_|ps2_keyboard_|clk_filter [7]), + .datac(\ula_|ps2_keyboard_|clk_filter [4]), + .datad(\ula_|ps2_keyboard_|clk_filter [6]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N1 +dffeas \ula_|ps2_keyboard_|clk_filter[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N23 +dffeas \ula_|ps2_keyboard_|clk_filter[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|clk_filter [3] & (\ula_|ps2_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|clk_filter [1] & !\ula_|ps2_keyboard_|clk_filter [2]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [3]), + .datab(\ula_|ps2_keyboard_|Equal0~0_combout ), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0004; +defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N27 +dffeas \ula_|ps2_keyboard_|clk_filter[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|clk_filter [0])) # (!\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|ps2_clk_in~q ))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hAAF0; +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N7 +dffeas \ula_|ps2_keyboard_|ps2_clk_in ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|clk_filter [0] & !\ula_|ps2_keyboard_|ps2_clk_in~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datac(\ula_|ps2_keyboard_|clk_filter [0]), + .datad(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h00C0; +defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N17 +dffeas \ula_|ps2_keyboard_|clk_edge ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_edge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; +// synopsys translate_on + +// Location: FF_X18_Y12_N19 +dffeas \ula_|ps2_keyboard_|bit_count[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [2]))) # (!\ula_|ps2_keyboard_|bit_count [1] & +// (((\ula_|ps2_keyboard_|bit_count [3] & !\ula_|ps2_keyboard_|bit_count [2])))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [1]), + .datac(\ula_|ps2_keyboard_|bit_count [3]), + .datad(\ula_|ps2_keyboard_|bit_count [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h0830; +defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y12_N29 +dffeas \ula_|ps2_keyboard_|bit_count[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [0] & \ula_|ps2_keyboard_|bit_count [1]))))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [2]), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; +defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y12_N13 +dffeas \ula_|ps2_keyboard_|bit_count[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [2] & !\ula_|ps2_keyboard_|bit_count [1])) # (!\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [2]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [0]), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; +defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y12_N23 +dffeas \ula_|ps2_keyboard_|bit_count[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [2]) # (\ula_|ps2_keyboard_|bit_count [1]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [2]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCC88; +defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [3] & !\PS2_DAT~input_o ))) + + .dataa(\ula_|ps2_keyboard_|bit_count [2]), + .datab(\ula_|ps2_keyboard_|bit_count [1]), + .datac(\ula_|ps2_keyboard_|bit_count [3]), + .datad(\PS2_DAT~input_o ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (!\ula_|ps2_keyboard_|LessThan0~0_combout & (\ula_|ps2_keyboard_|clk_edge~q & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|always1~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h2030; +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y10_N5 +dffeas \ula_|ps2_keyboard_|shiftreg[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\PS2_DAT~input_o ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y10_N27 +dffeas \ula_|ps2_keyboard_|shiftreg[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [8]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y10_N13 +dffeas \ula_|ps2_keyboard_|shiftreg[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [7]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y8_N21 +dffeas \ula_|ps2_keyboard_|shiftreg[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [6]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y10_N31 +dffeas \ula_|ps2_keyboard_|shiftreg[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [5]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X20_Y8_N17 +dffeas \ula_|ps2_keyboard_|shiftreg[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [4]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X20_Y8_N31 +dffeas \ula_|ps2_keyboard_|shiftreg[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [3]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X20_Y8_N23 +dffeas \ula_|ps2_keyboard_|shiftreg[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [2]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y10_N23 +dffeas \ula_|ps2_keyboard_|shiftreg[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [1]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [6]))) .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[4][2]~59_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|zx_keyboard_|Equal0~0_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~131_combout ), + .combout(\ula_|zx_keyboard_|Equal0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~131 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[4][2]~131 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~60 ( +// Location: LCCOMB_X19_Y10_N4 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~60_combout = (\ula_|zx_keyboard_|keys[4][2]~131_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[4][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[4][2]~131_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) +// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [6]))) - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[4][2]~131_combout ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [8]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~60_combout ), + .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~60 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[4][2]~60 .sum_lutc_input = "datac"; +defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y18_N15 -dffeas \ula_|zx_keyboard_|keys[4][2] ( +// Location: LCCOMB_X19_Y10_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N24 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~0_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hC33C; +defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y12_N24 +cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|WideXor0~2_combout & (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|LessThan0~0_combout ))) + + .dataa(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .datab(\PS2_DAT~input_o ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X18_Y12_N25 +dffeas \ula_|ps2_keyboard_|scan_code_ready ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][2]~60_combout ), + .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49200,86 +11750,175 @@ dffeas \ula_|zx_keyboard_|keys[4][2] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][2]~q ), + .q(\ula_|ps2_keyboard_|scan_code_ready~q ), .prn(vcc)); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; +defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N4 -cycloneive_lcell_comb \D[2]~37 ( +// Location: LCCOMB_X20_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( // Equation(s): -// \D[2]~37_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][2]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) +// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|released~q ) # (\ula_|ps2_keyboard_|shiftreg [4])))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & +// (((\ula_|zx_keyboard_|released~q )))) - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~q ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~37 .lut_mask = 16'hBB0B; -defparam \D[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~53 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~53_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .dataa(\ula_|zx_keyboard_|Equal0~1_combout ), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|zx_keyboard_|released~q ), .datad(\ula_|ps2_keyboard_|shiftreg [4]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~53_combout ), + .combout(\ula_|zx_keyboard_|released~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~53 .lut_mask = 16'h00F0; -defparam \ula_|zx_keyboard_|keys[3][2]~53 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hB8B0; +defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~55 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~55_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) +// Location: FF_X20_Y9_N27 +dffeas \ula_|zx_keyboard_|released ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|released~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|released~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|released .power_up = "low"; +// synopsys translate_on - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), +// Location: LCCOMB_X21_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(gnd), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~55_combout ), + .combout(\ula_|zx_keyboard_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~55 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[2][2]~55 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h1010; +defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~56 ( +// Location: LCCOMB_X20_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~50 ( // Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~56_combout = (\ula_|zx_keyboard_|keys[2][2]~55_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~55_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) +// \ula_|zx_keyboard_|keys[3][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~50 .lut_mask = 16'h5500; +defparam \ula_|zx_keyboard_|keys[3][2]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( +// Equation(s): +// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|zx_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|extended~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hA0AA; +defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N1 +dffeas \ula_|zx_keyboard_|extended ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|extended~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|extended~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|extended .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~15 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~15_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~15 .lut_mask = 16'h0010; +defparam \ula_|zx_keyboard_|keys[7][4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~52 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~52_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[3][2]~50_combout & \ula_|zx_keyboard_|keys[7][4]~15_combout ))) + + .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .datad(\ula_|zx_keyboard_|keys[7][4]~15_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~52_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~52 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[2][2]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~53 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~53_combout = (\ula_|zx_keyboard_|keys[2][2]~52_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~52_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), .datac(\ula_|zx_keyboard_|keys[2][2]~q ), - .datad(\ula_|zx_keyboard_|keys[2][2]~55_combout ), + .datad(\ula_|zx_keyboard_|keys[2][2]~52_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~56_combout ), + .combout(\ula_|zx_keyboard_|keys[2][2]~53_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~56 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[2][2]~56 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][2]~53 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[2][2]~53 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y20_N27 +// Location: FF_X20_Y9_N25 dffeas \ula_|zx_keyboard_|keys[2][2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][2]~56_combout ), + .d(\ula_|zx_keyboard_|keys[2][2]~53_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49295,28 +11934,27482 @@ defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~54 ( +// Location: LCCOMB_X31_Y14_N4 +cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~54_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][2]~53_combout & ((\ula_|zx_keyboard_|keys[3][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) +// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # +// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[3][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][2]~53_combout ), + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|resets_|clrpc_int~q ), + .datad(\z80_|resets_|x1~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~54_combout ), + .combout(\z80_|resets_|clrpc_int~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~54 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[3][2]~54 .sum_lutc_input = "datac"; +defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; +defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y20_N29 +// Location: FF_X31_Y14_N5 +dffeas \z80_|resets_|clrpc_int ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|clrpc_int~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|clrpc_int~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; +defparam \z80_|resets_|clrpc_int .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N0 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0F0F; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N1 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N14 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_9~feeder ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout = \z80_|resets_|SYNTHESIZED_WIRE_10~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .lut_mask = 16'hFF00; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N15 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y12_N27 +dffeas \z80_|resets_|DFFE_intr_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N26 +cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( +// Equation(s): +// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|clrpc_int~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|SYNTHESIZED_WIRE_10~q ))) + + .dataa(\z80_|resets_|clrpc_int~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .datac(\z80_|resets_|DFFE_intr_ff3~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .cin(gnd), + .combout(\z80_|resets_|clrpc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; +defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_al_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h4044; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~1_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal40~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal40~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal40~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal40~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; +defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal39~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal40~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal40~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0003; +defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal6~1_combout )) + + .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h000A; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ))) + + .dataa(\z80_|execute_|fMRead~2_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h0555; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_alu_oe~2_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h5554; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & ((\z80_|execute_|fMRead~2_combout ) # ((\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~14_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .datad(\z80_|execute_|fMRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h0F02; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~10_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_mRead~13_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_ir_we~8_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'h0003; +defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~20_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hDFDF; +defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~4_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h33BB; +defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_reg_sys_hilo~20_combout & (((\z80_|execute_|ctl_inc_dec~4_combout )) # (!\z80_|pla_decode_|Equal33~3_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo~20_combout & +// (!\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datab(\z80_|pla_decode_|Equal33~3_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_inc_dec~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hAF23; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & ((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout +// )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00D0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~33_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|pc_inc_hold~33_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h50D0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & \z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|execute_|ctl_mRead~7_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .datac(\z80_|execute_|ctl_al_we~5_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h4044; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~13_combout = ((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'hF0D0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~16_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~12_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~16 .lut_mask = 16'h8808; +defparam \z80_|execute_|ctl_reg_sys_hilo~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~16_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_mWrite~9_combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h010F; +defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_al_we~13_combout & \z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'hB300; +defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|setM1~53_combout & (\z80_|execute_|ctl_reg_sel_pc~12_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~6_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~6 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_alu_bs_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~6_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~2_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal29~0_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout & +// (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|pla_decode_|Equal29~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; +defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal9~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h3777; +defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N0 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~1_combout & (\z80_|reg_control_|reg_sel_pc~0_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal38~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h7000; +defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal56~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal56~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~18_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~17_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|execute_|ctl_alu_op_low~17_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_oe~4_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~9_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_in_hi~4_combout & \z80_|execute_|ctl_reg_in_hi~3_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|execute_|ctl_mWrite~9_combout ) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~9_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h337F; +defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( +// Equation(s): +// \z80_|execute_|fMRead~6_combout = (\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|execute_|ctl_alu_op_low~14_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_mRead~13_combout )))) # +// (!\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N28 +cycloneive_lcell_comb \z80_|nM1_int~2 ( +// Equation(s): +// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|nM1_int~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|nM1_int~2 .lut_mask = 16'h000F; +defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_dec~3_combout & (\z80_|execute_|fMRead~6_combout & (!\z80_|nM1_int~2_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), + .datab(\z80_|execute_|fMRead~6_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~94 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~94_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~94_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~94 .lut_mask = 16'h7F7F; +defparam \z80_|execute_|ctl_inc_cy~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~50_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|execute_|ctl_sw_4u~0_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hF5F7; +defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ixy_d~16_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & +// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ixy_d~16_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~15_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ixy_d~10_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h373F; +defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~13_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h3F37; +defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & (\z80_|execute_|ctl_reg_sel_pc~4_combout & \z80_|execute_|ctl_reg_sel_pc~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & +// (!\z80_|pla_decode_|Equal12~1_combout & ((\z80_|pla_decode_|Equal25~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal12~1_combout ), + .datac(\z80_|pla_decode_|Equal24~0_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'hB3A0; +defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (\z80_|execute_|ctl_reg_sel_pc~8_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h020A; +defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~99 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~99_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~99_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~99 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_inc_cy~99 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~50_combout & (\z80_|execute_|ctl_reg_sel_pc~10_combout & \z80_|execute_|ctl_inc_cy~99_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), + .datab(\z80_|execute_|ctl_inc_cy~50_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .datad(\z80_|execute_|ctl_inc_cy~99_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & +// !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~9_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal47~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF1FF; +defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'hEAFF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~5_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal48~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal48~0_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal48~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h5444; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ))) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~13_combout = (\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout & !\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout )) # +// (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h131F; +defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h00FC; +defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((!\z80_|execute_|ctl_flags_bus~4_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hFF73; +defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( +// Equation(s): +// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|setM1~37_combout & (!\z80_|execute_|ctl_mRead~11_combout & (!\z80_|pla_decode_|Equal52~1_combout & !\z80_|pla_decode_|Equal21~1_combout ))) + + .dataa(\z80_|execute_|setM1~37_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h0002; +defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~33_combout = (!\z80_|execute_|ctl_mRead~12_combout & ((\z80_|ir_|opcode [3]) # ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal12~0_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal12~0_combout ), + .datad(\z80_|execute_|ctl_mRead~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h00EF; +defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~35_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & (((\z80_|execute_|fMRead~7_combout & \z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ))) + + .dataa(\z80_|execute_|fMRead~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'h8C0C; +defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~34_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|pc_inc_hold~33_combout & ((!\z80_|decode_state_|use_ixiy~combout ) # (!\z80_|pla_decode_|Equal33~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|pla_decode_|Equal33~2_combout ), + .datac(\z80_|execute_|pc_inc_hold~33_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h1050; +defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_mWrite~9_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_mRead~34_combout +// & ((\z80_|execute_|ctl_mWrite~9_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~9_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~1_combout = (!\z80_|execute_|ctl_reg_sys_we~0_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'h0155; +defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal48~0_combout & \z80_|sequencer_|DFFE_T4_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~2_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~34_combout & \z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'hFF4F; +defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal8~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0])) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h4400; +defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_we_lo~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~1_combout = (\z80_|execute_|ctl_reg_sys_we_lo~0_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we_lo~0_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_reg_sys_we_lo~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( +// Equation(s): +// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal40~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal40~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|sel[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h2AAA; +defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & +// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal52~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h053F; +defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~7_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|execute_|ctl_state_alu~7_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hAA2A; +defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'h00EF; +defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~5_combout = (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [6]), + .datad(\z80_|decode_state_|table_xx~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0002; +defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~10_combout = (\z80_|pla_decode_|Equal52~1_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # ((\z80_|execute_|ctl_state_alu~9_combout & \z80_|execute_|ctl_state_alu~5_combout )))) # (!\z80_|pla_decode_|Equal52~1_combout +// & (\z80_|execute_|ctl_state_alu~9_combout & ((\z80_|execute_|ctl_state_alu~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~9_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_state_alu~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'hECA0; +defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|pla_decode_|Equal52~1_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_state_alu~6_combout & +// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'hFA32; +defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~11_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hAAA2; +defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~5_combout = (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal62~2_combout )) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal62~2_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hF777; +defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal46~0_combout & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal46~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hABFF; +defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~7_combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~7 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_alu_bs_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~7_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~19_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~19 .lut_mask = 16'hDDDF; +defparam \z80_|execute_|ctl_flags_xy_we~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~2_combout ), + .datab(\z80_|pla_decode_|Equal40~1_combout ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~25_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~26_combout = ((!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|execute_|ctl_mRead~34_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_iorw~10_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~28_combout = (\z80_|execute_|ctl_alu_shift_oe~25_combout & (\z80_|execute_|ctl_alu_shift_oe~26_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~27_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~19_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal6~0_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_alu_op_low~18_combout & !\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hFF37; +defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~9_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|execute_|ctl_flags_bus~15_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h5070; +defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal20~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|comb~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal20~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal68~2_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|pla_decode_|Equal68~2_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF57; +defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal63~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|execute_|comb~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal63~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal76~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal76~2_combout = (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal76~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal76~2 .lut_mask = 16'h0A00; +defparam \z80_|pla_decode_|Equal76~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~8_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal76~2_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal76~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal32~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|execute_|ixy_d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~7_combout = ((!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_flags_bus~6_combout & !\z80_|pla_decode_|Equal13~2_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~6_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|execute_|ctl_flags_bus~9_combout & (\z80_|execute_|ctl_flags_bus~14_combout & (\z80_|execute_|ctl_flags_bus~8_combout & \z80_|execute_|ctl_flags_bus~7_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~9_combout ), + .datab(\z80_|execute_|ctl_flags_bus~14_combout ), + .datac(\z80_|execute_|ctl_flags_bus~8_combout ), + .datad(\z80_|execute_|ctl_flags_bus~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_bus_db_oe~3_combout & (\z80_|execute_|ctl_flags_xy_we~19_combout & (\z80_|execute_|ctl_alu_shift_oe~28_combout & \z80_|execute_|ctl_flags_bus~10_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datad(\z80_|execute_|ctl_flags_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf2_we~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h0155; +defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel~7_combout = (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|decode_state_|table_xx~0_combout ), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel~7 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~12_combout = ((\z80_|execute_|ctl_reg_gp_sel~7_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout ))) # (!\z80_|execute_|ctl_state_alu~7_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~7_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|ctl_state_alu~12_combout & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal62~3_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_alu_op_low~19_combout & !\z80_|execute_|ctl_iorw~10_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datab(\z80_|execute_|ctl_iorw~10_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'hFFF1; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~7_combout = (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~10 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~10_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~10 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_pf_sel[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~29_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hAAA2; +defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~11_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~11 .lut_mask = 16'hCCC4; +defparam \z80_|execute_|ctl_flags_pf_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & (\z80_|execute_|ctl_pf_sel[0]~10_combout & \z80_|execute_|ctl_flags_pf_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~10_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal10~1_combout = (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal10~1 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal10~1_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal10~1_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal69~0_combout = (\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal69~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'h0A02; +defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~8_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_pf_we~7_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~13 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~13_combout = (\z80_|ir_|opcode [5]) # (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_state_alu~12_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~13 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_pf_sel[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~10_combout = (((\z80_|execute_|ctl_flags_pf_we~9_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout )) # (!\z80_|execute_|ctl_flags_xy_we~11_combout )) # (!\z80_|execute_|ctl_flags_pf_we~5_combout ) + + .dataa(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N20 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~3_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'h0F1F; +defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~18_combout = (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N0 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|reg_control_|reg_sys_we_lo~3_combout & (\z80_|execute_|ctl_flags_xy_we~18_combout & ((!\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h40C0; +defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~5_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h7700; +defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N10 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~6_combout = (((\z80_|execute_|ctl_reg_sys_we_lo~1_combout & \z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~2_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~5_combout ) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'hDF5F; +defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout ) # ((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hFBFB; +defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~21_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (\z80_|execute_|ctl_mRead~20_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datac(\z80_|execute_|ctl_mRead~20_combout ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~21 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_sel_wz~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~20_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal35~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|pla_decode_|Equal35~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~20 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout = (\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|sequencer_|M5~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~44_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|M5~q ))) + + .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'hAA2A; +defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hF2F0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = (((\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'hF777; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout = ((\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~21_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h4040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~5_combout & ((\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~4_combout )))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_mRead~5_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h2333; +defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~1_combout = (\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((!\z80_|execute_|ctl_al_we~14_combout & \z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~14_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) + + .dataa(\z80_|decode_state_|in_halt~q ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'hABFF; +defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~47 ( +// Equation(s): +// \z80_|execute_|setM1~47_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|setM1~46_combout & !\z80_|execute_|ctl_mWrite~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_al_we~13_combout ), + .datac(\z80_|execute_|setM1~46_combout ), + .datad(\z80_|execute_|ctl_mWrite~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~47 .lut_mask = 16'h00C0; +defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|execute_|ctl_alu_oe~5_combout & !\z80_|decode_state_|use_ixiy~combout )) # (!\z80_|execute_|setM1~47_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~5_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|setM1~47_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ixy_d~6_combout & +// ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h2A3F; +defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( +// Equation(s): +// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal9~1_combout & ((!\z80_|pla_decode_|Equal29~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal9~1_combout & +// !\z80_|pla_decode_|Equal29~0_combout )) # (!\z80_|execute_|ctl_state_alu~3_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|pla_decode_|Equal29~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h0537; +defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( +// Equation(s): +// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~14_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|pla_decode_|Equal37~0_combout & +// !\z80_|execute_|ctl_mRead~14_combout )) # (!\z80_|execute_|ctl_state_alu~3_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~9 .lut_mask = 16'h111F; +defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( +// Equation(s): +// \z80_|execute_|fMRead~10_combout = (\z80_|execute_|fMRead~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|fMRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h3700; +defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|fMRead~8_combout & \z80_|execute_|fMRead~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datac(\z80_|execute_|fMRead~8_combout ), + .datad(\z80_|execute_|fMRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|pla_decode_|Equal11~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h5000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal4~0_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|execute_|comb~1_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|execute_|comb~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~41 ( +// Equation(s): +// \z80_|execute_|setM1~41_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal4~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~41 .lut_mask = 16'h003F; +defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal2~1_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal2~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & ((\z80_|execute_|setM1~41_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|setM1~41_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h0051; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~3_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~3_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_sw_1d~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datad(\z80_|execute_|ctl_sw_1d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & +// (!\z80_|execute_|ctl_alu_oe~2_combout & ((!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hC0DD; +defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sel_wz~11_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_sw_4d~4_combout & (\z80_|execute_|ctl_sw_4d~2_combout & (\z80_|execute_|ctl_sw_4d~3_combout & \z80_|execute_|ctl_reg_sel_wz~12_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~4_combout ), + .datab(\z80_|execute_|ctl_sw_4d~2_combout ), + .datac(\z80_|execute_|ctl_sw_4d~3_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~6_combout = (\z80_|execute_|ctl_sw_4d~1_combout ) # ((\z80_|execute_|ctl_sw_4d~0_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_4d~1_combout ), + .datac(\z80_|execute_|ctl_sw_4d~0_combout ), + .datad(\z80_|execute_|ctl_sw_4d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N30 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~4_combout = ((!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|alu_control_|flags_cond_true~q ) # (!\z80_|pla_decode_|Equal35~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~4 .lut_mask = 16'h337F; +defparam \z80_|reg_control_|reg_sel_pc~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((!\z80_|execute_|fMRead~4_combout & \z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .datab(\z80_|execute_|fMRead~4_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h7F5F; +defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~17_combout = (\z80_|nM1_int~2_combout ) # (((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|ctl_inc_dec~3_combout )) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_inc_dec~3_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'hBBFB; +defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~19_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal33~3_combout ), + .datac(\z80_|execute_|ctl_al_we~5_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'h4500; +defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal21~1_combout & ((!\z80_|pla_decode_|Equal52~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h030F; +defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sel_pc~14_combout ) # (!\z80_|execute_|setM1~37_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .datab(\z80_|execute_|setM1~37_combout ), + .datac(\z80_|execute_|fMRead~2_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hABAF; +defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~18_combout = (\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~17_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (!\z80_|execute_|ctl_sw_4u~1_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~19_combout = (((!\z80_|pla_decode_|Equal34~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_wz~19_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h0080; +defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~combout = (\z80_|reg_control_|reg_sel_pc~4_combout & (\z80_|reg_control_|reg_sel_pc~3_combout & ((\z80_|execute_|ctl_reg_sel_pc~18_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_pc~4_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~3_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h80A0; +defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h4040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~6_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal1~5_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N24 +cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( +// Equation(s): +// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal1~6_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|reg_control_|bank_exx~q ), + .datad(\z80_|pla_decode_|Equal1~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_exx~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y14_N25 +dffeas \z80_|reg_control_|bank_exx ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_exx~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_exx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_exx .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|execute_|ctl_state_alu~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal77~0_combout ), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hC0C4; +defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mWrite~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout ) # +// (!\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h0737; +defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~56 ( +// Equation(s): +// \z80_|execute_|setM1~56_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~56 .lut_mask = 16'hFF1F; +defparam \z80_|execute_|setM1~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (\z80_|execute_|ctl_sw_2u~4_combout & \z80_|execute_|setM1~56_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_2u~1_combout ), + .datac(\z80_|execute_|ctl_sw_2u~4_combout ), + .datad(\z80_|execute_|setM1~56_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|ir_|opcode [1] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'h30F0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|pla_decode_|Equal11~0_combout & (((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (\z80_|execute_|ctl_mRead~3_combout & +// ((\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hEEC0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~13_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hFF37; +defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & (\z80_|execute_|ctl_state_alu~13_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datac(\z80_|execute_|ctl_state_alu~13_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~61_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|execute_|ixy_d~5_combout & +// !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|execute_|ctl_mRead~14_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h0357; +defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~86_combout = (\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal38~2_combout & (((!\z80_|execute_|ixy_d~5_combout & +// !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'h111F; +defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~87_combout = (\z80_|execute_|ctl_inc_cy~86_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~86_combout ), + .datab(\z80_|pla_decode_|Equal29~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h222A; +defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~52 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~52_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~52 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_bus_inc_oe~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~49 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~49_combout = (\z80_|execute_|ctl_bus_inc_oe~52_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal4~0_combout )) # (!\z80_|sequencer_|DFFE_T5_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), + .datab(\z80_|execute_|ctl_bus_inc_oe~52_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal4~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~49 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_bus_inc_oe~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_inc_cy~61_combout & (\z80_|execute_|ctl_bus_inc_oe~28_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_bus_inc_oe~49_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .datac(\z80_|execute_|ctl_inc_cy~87_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|fMRead~10_combout & (\z80_|execute_|fMRead~8_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_reg_gp_we~3_combout ))) + + .dataa(\z80_|execute_|fMRead~10_combout ), + .datab(\z80_|execute_|fMRead~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = ((!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h15FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~7_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h0105; +defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|execute_|ctl_alu_oe~7_combout & (((!\z80_|execute_|ctl_mRead~25_combout & !\z80_|execute_|ctl_mRead~24_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~25_combout ), + .datac(\z80_|execute_|ctl_mRead~24_combout ), + .datad(\z80_|execute_|ctl_alu_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & (\z80_|execute_|ctl_flags_pf_we~5_combout & (\z80_|execute_|ctl_pf_sel[0]~13_combout & \z80_|execute_|ctl_alu_oe~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .datad(\z80_|execute_|ctl_alu_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_iorw~10_combout & (!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_mRead~4_combout & !\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (!\z80_|pla_decode_|Equal13~2_combout & (\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|ctl_flags_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~12_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [4]), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hCCFF; +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~8_combout = (!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ctl_alu_op_low~19_combout & (\z80_|execute_|ctl_flags_hf_cpl~12_combout & !\z80_|pla_decode_|Equal68~2_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .datad(\z80_|pla_decode_|Equal68~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~8 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_flags_hf_cpl~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~48 ( +// Equation(s): +// \z80_|execute_|setM1~48_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~48 .lut_mask = 16'h0013; +defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|pla_decode_|Equal20~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h0033; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~2 ( +// Equation(s): +// \z80_|execute_|nextM~2_combout = (!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|execute_|ctl_alu_op_low~18_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0003; +defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~49 ( +// Equation(s): +// \z80_|execute_|setM1~49_combout = (\z80_|execute_|ctl_flags_hf_cpl~8_combout & (\z80_|execute_|setM1~48_combout & (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & \z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), + .datab(\z80_|execute_|setM1~48_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~49 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~12_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|setM1~49_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_flags_oe~1_combout ), + .datad(\z80_|execute_|setM1~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'h0444; +defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~8_combout = (((\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal12~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h77F7; +defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_sw_1d~8_combout ), + .datac(\z80_|execute_|ctl_sw_1d~4_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h40F0; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|execute_|ctl_mRead~24_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|execute_|ctl_mRead~24_combout & +// (((!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal20~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~24_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_mWrite~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ctl_mWrite~8_combout & +// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (!\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~25_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|nextM~11 ( +// Equation(s): +// \z80_|execute_|nextM~11_combout = ((!\z80_|execute_|ctl_alu_op_low~18_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_mWrite~5_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~11 .lut_mask = 16'h5557; +defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|execute_|ctl_alu_op_low~18_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|nextM~11_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_bus_inc_oe~51_combout & \z80_|execute_|ctl_reg_use_sp~2_combout ))) + + .dataa(\z80_|execute_|nextM~11_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~51_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal6~1_combout )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0500; +defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~13_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_sw_1d~9_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .lut_mask = 16'h0133; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~12_combout = (!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & !\z80_|pla_decode_|Equal49~0_combout )) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_oe~3_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .lut_mask = 16'h0005; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & +// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'hF010; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # (\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~30 ( +// Equation(s): +// \z80_|execute_|setM1~30_combout = (\z80_|execute_|ctl_mRead~15_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|execute_|ctl_mRead~15_combout & +// (((!\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~30 .lut_mask = 16'h0777; +defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|ctl_mRead~23_combout & (\z80_|execute_|setM1~30_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ctl_mRead~23_combout ), + .datac(\z80_|execute_|setM1~30_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~14_combout = (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((!\z80_|execute_|ctl_reg_sys_hilo~20_combout & \z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h4F00; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|execute_|ctl_mRead~5_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal2~1_combout & \z80_|pla_decode_|Equal1~4_combout )))) + + .dataa(\z80_|pla_decode_|Equal2~1_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal4~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'hF080; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~20_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .lut_mask = 16'h3332; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~21_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal11~0_combout ))) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h7F00; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ) # ((\z80_|ir_|opcode [2] & ((!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .datab(\z80_|execute_|ctl_sw_2u~5_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'hBFAA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|decode_state_|DFFE_instIY1~q ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|pla_decode_|Equal50~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hEEEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_mRead~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hA2AA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ) # ((\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & ((\z80_|sequencer_|M5~q ) # (\z80_|sequencer_|DFFE_M4_ff~q )))) + + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h1110; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~36_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [6] & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [7]))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|ir_|opcode [3] & (\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal12~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hA2AF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~8_combout )) # (!\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout & \z80_|execute_|ctl_ir_we~6_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_ir_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hACA0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'hB030; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N2 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~2_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~2 .lut_mask = 16'h00F0; +defparam \z80_|reg_control_|reg_sel_de2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~4_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|decode_state_|DFFE_inst4~q & !\z80_|decode_state_|DFFE_instIY1~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'h0004; +defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N12 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((!\z80_|reg_control_|bank_exx~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal2~2_combout )))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|reg_control_|bank_hl_de1~q ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hE1F0; +defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N13 +dffeas \z80_|reg_control_|bank_hl_de1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N28 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~2_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~4_combout ))))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|reg_control_|reg_sel_de2~2_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|reg_control_|bank_hl_de1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h4450; +defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal8~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~50 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~50_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~50 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_bus_inc_oe~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_bus_inc_oe~50_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~50_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & (\z80_|execute_|ctl_reg_gp_we~2_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h1500; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|execute_|ixy_d~9_combout ) # +// (!\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h0737; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h3230; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # ((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|ctl_mRead~23_combout ) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ctl_mRead~23_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'hFBF3; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (\z80_|execute_|ctl_ir_we~7_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~20_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ) # ((\z80_|execute_|ctl_iorw~11_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .datab(\z80_|execute_|ctl_iorw~11_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h00A0; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'h0133; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal25~0_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # +// (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|rsel3 ( +// Equation(s): +// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(gnd), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|rsel3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel3 .lut_mask = 16'h5AAA; +defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = (\z80_|execute_|rsel3~combout & (((\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'h08CC; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_flags_oe~1_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h040F; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~14_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFDF0; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel~7_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|rsel0 ( +// Equation(s): +// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(gnd), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|rsel0~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel0 .lut_mask = 16'h66AA; +defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout & ((\z80_|execute_|rsel0~combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|execute_|setM1~49_combout )))) # +// (!\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|execute_|setM1~49_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|setM1~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'h888F; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal3~1_combout & !\z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_sw_1d~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~6_combout = (!\z80_|execute_|ctl_reg_in_hi~7_combout & (\z80_|execute_|ctl_state_alu~13_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & !\z80_|execute_|ctl_reg_in_hi~12_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .datab(\z80_|execute_|ctl_state_alu~13_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'h0004; +defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~9_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~16_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_sw_1d~9_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~9 .lut_mask = 16'h070F; +defparam \z80_|execute_|ctl_reg_gp_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'h0015; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (\z80_|execute_|ctl_reg_gp_we~9_combout & \z80_|execute_|ctl_alu_sel_op2_neg~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~9_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h5155; +defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~7_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & (\z80_|execute_|ctl_reg_gp_we~5_combout & \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((!\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h31F5; +defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|ctl_sw_4u~2_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datac(\z80_|execute_|ctl_sw_4u~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~8_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (((!\z80_|execute_|ctl_sw_4u~3_combout ) # (!\z80_|execute_|ctl_reg_gp_we~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datad(\z80_|execute_|ctl_sw_4u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~8 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_gp_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|reg_control_|reg_sel_hl~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N16 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|reg_control_|bank_exx~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal2~2_combout )))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; +defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N17 +dffeas \z80_|reg_control_|bank_hl_de2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de2~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~2_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~4_combout )))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|reg_control_|bank_hl_de2~q ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hA820; +defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|reg_control_|reg_sel_hl2~0_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|reg_control_|reg_sel_hl2~0_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|pla_decode_|Equal52~1_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_state_alu~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout = (\z80_|sequencer_|DFFE_M3_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal3~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal24~0_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|execute_|ctl_reg_in_hi~8_combout & (!\z80_|execute_|ctl_66_oe~2_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout & \z80_|execute_|ctl_reg_gp_we~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2~combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|pla_decode_|Equal24~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~8_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~21_combout ) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ))) # (!\z80_|execute_|ctl_reg_in_hi~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h070F; +defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|pla_decode_|Equal6~1_combout & !\z80_|execute_|ctl_mRead~2_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_sw_2d~6_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~8_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_alu_shift_oe~44_combout & \z80_|execute_|ctl_sw_2d~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .datad(\z80_|execute_|ctl_sw_2d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h5500; +defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N4 +cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( +// Equation(s): +// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|execute_|ctl_mRead~16_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & +// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( +// Equation(s): +// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~7_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~7_combout ), + .datab(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h0888; +defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( +// Equation(s): +// \z80_|execute_|fMRead~20_combout = (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|ctl_mWrite~10_combout & (\z80_|execute_|fMRead~18_combout & \z80_|execute_|fMRead~19_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~10_combout ), + .datac(\z80_|execute_|fMRead~18_combout ), + .datad(\z80_|execute_|fMRead~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~20 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h1115; +defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Equation(s): +// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|fMRead~20_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_in_hi~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~22_combout ), + .datab(\z80_|execute_|fMRead~20_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~21 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h20AA; +defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & (\z80_|execute_|fMRead~21_combout & \z80_|execute_|ctl_sw_2d~5_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~8_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .datac(\z80_|execute_|fMRead~21_combout ), + .datad(\z80_|execute_|ctl_sw_2d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|pla_decode_|Equal49~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hAA8A; +defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (\z80_|execute_|ctl_sw_2d~9_combout & (!\z80_|execute_|ctl_sw_1d~5_combout & \z80_|execute_|ctl_sw_1d~4_combout ))) + + .dataa(\z80_|execute_|ctl_im_we~combout ), + .datab(\z80_|execute_|ctl_sw_2d~9_combout ), + .datac(\z80_|execute_|ctl_sw_1d~5_combout ), + .datad(\z80_|execute_|ctl_sw_1d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|execute_|ctl_66_oe~2_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7733; +defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~41_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~18_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~41 .lut_mask = 16'h3BFF; +defparam \z80_|execute_|ctl_alu_op_low~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal44~0_combout & ((\z80_|ir_|opcode [0]) # (!\z80_|execute_|comb~0_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|comb~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal44~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = (\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~10_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & !\z80_|execute_|ctl_reg_gp_sel~7_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~7_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|execute_|ctl_alu_op_low~17_combout & (((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) # (!\z80_|execute_|ctl_alu_op_low~17_combout & +// (\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0155; +defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~27_combout = ((\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~20_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~26_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & ((\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~41_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hF300; +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal61~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal61~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h222A; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~12_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~12 .lut_mask = 16'h3B3F; +defparam \z80_|execute_|ctl_alu_core_hf~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_core_hf~12_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & +// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~13_combout = (((!\z80_|execute_|ixy_d~6_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_flags_sz_we~3_combout & (\z80_|execute_|ctl_flags_alu~13_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~2_combout & !\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datab(\z80_|execute_|ctl_flags_alu~13_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~15_combout = (\z80_|execute_|ctl_flags_alu~14_combout & (\z80_|execute_|ctl_flags_xy_we~9_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|execute_|ctl_flags_alu~14_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|nextM~11_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~16_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~17_combout = (\z80_|execute_|ctl_alu_op_low~16_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal20~0_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'hF070; +defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .lut_mask = 16'h010F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~39_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~39 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~16_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (!\z80_|execute_|ctl_alu_op_low~39_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~39_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h020A; +defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~17_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_alu~16_combout ))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datac(\z80_|execute_|ctl_sw_2d~4_combout ), + .datad(\z80_|execute_|ctl_flags_alu~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~23_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'h0F5F; +defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~18_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_alu_op_low~23_combout & \z80_|execute_|ctl_sw_4u~1_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datab(\z80_|execute_|ctl_flags_alu~17_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~11_combout = (((!\z80_|execute_|ctl_flags_alu~10_combout ) # (!\z80_|execute_|ctl_flags_alu~22_combout )) # (!\z80_|execute_|ctl_flags_alu~20_combout )) # (!\z80_|execute_|ctl_flags_alu~21_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~21_combout ), + .datab(\z80_|execute_|ctl_flags_alu~20_combout ), + .datac(\z80_|execute_|ctl_flags_alu~22_combout ), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal1~5_combout & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal1~5_combout ), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .lut_mask = 16'h0050; +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFFC4; +defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~23 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~23_combout = (\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~23 .lut_mask = 16'hF040; +defparam \z80_|execute_|ctl_flags_alu~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_flags_alu~11_combout ) # (((\z80_|execute_|ctl_alu_core_R~1_combout ) # (\z80_|execute_|ctl_flags_alu~23_combout )) # (!\z80_|reg_control_|reg_sys_we_lo~3_combout )) + + .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datad(\z80_|execute_|ctl_flags_alu~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~11_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .lut_mask = 16'hF5F1; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~6_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mWrite~17_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (((!\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~17 ( +// Equation(s): +// \z80_|execute_|setM1~17_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (!\z80_|execute_|ctl_alu_shift_oe~15_combout & \z80_|execute_|ctl_state_alu~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_2u~1_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~17 .lut_mask = 16'h0C00; +defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~22_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'h0015; +defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|execute_|setM1~17_combout & (!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|setM1~17_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_alu_oe~6_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & \z80_|execute_|ctl_flags_xy_we~18_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~6_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~11_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_flags_xy_we~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~19_combout = (((\z80_|execute_|ctl_flags_alu~12_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_alu~18_combout )) # (!\z80_|execute_|ctl_flags_alu~15_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), + .datab(\z80_|execute_|ctl_flags_alu~18_combout ), + .datac(\z80_|execute_|ctl_flags_alu~12_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~19 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_alu~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFFE0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( +// Equation(s): +// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~12_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # +// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~26 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal52~0_combout )) + + .dataa(\z80_|pla_decode_|Equal44~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal52~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'hEEAA; +defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~11_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_bus~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'hF070; +defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~13_combout = ((\z80_|execute_|ctl_flags_hf2_we~combout ) # (\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|fMRead~26_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|fMRead~26_combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|ctl_flags_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'hFFF3; +defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~combout = ((\z80_|execute_|ctl_flags_bus~13_combout ) # ((!\z80_|execute_|ctl_flags_bus~10_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~28_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~3_combout ) + + .dataa(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datab(\z80_|execute_|ctl_flags_bus~13_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datad(\z80_|execute_|ctl_flags_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|alu_control_|db[1]~27_combout & \z80_|execute_|ctl_flags_bus~combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .datab(\z80_|alu_control_|db[1]~27_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEFA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~12_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|nextM~11_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFEAA; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = (\z80_|execute_|ctl_alu_op_low~39_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~39_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~18_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datad(\z80_|pla_decode_|Equal48~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~18 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h0507; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_ir_we~14_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout +// & (((!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_flags_alu~20_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_flags_alu~20_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~18_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~14_combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~18_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~12_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~11_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~25_combout ) # (\z80_|execute_|ctl_mRead~24_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~19_combout ) + + .dataa(\z80_|execute_|ctl_mRead~25_combout ), + .datab(\z80_|execute_|ctl_mRead~24_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hE0FF; +defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~24_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'h0BFF; +defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ctl_alu_op_low~24_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'h2200; +defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~17_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .lut_mask = 16'h3230; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (!\z80_|execute_|ctl_alu_op1_sel_bus~17_combout & (!\z80_|execute_|ctl_alu_op_low~20_combout & ((!\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0105; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & \z80_|execute_|ctl_alu_shift_oe~38_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|execute_|ctl_ir_we~11_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|execute_|ctl_alu_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAA20; +defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~39_combout = ((\z80_|execute_|ctl_alu_shift_oe~37_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~42_combout = ((\z80_|execute_|ctl_alu_shift_oe~40_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # (!\z80_|execute_|ctl_alu_op_low~25_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hC0C8; +defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~8_combout = (\z80_|execute_|ctl_alu_bs_oe~12_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~7_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|execute_|ctl_ir_we~7_combout & (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # +// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h7740; +defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_ir_we~10_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h5540; +defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~36_combout = ((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~1_combout ) # (!\z80_|execute_|ctl_flags_bus~10_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .datac(\z80_|execute_|ctl_flags_bus~10_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~7_combout )))) # (!\z80_|execute_|ctl_bus_db_oe~1_combout & ((\z80_|execute_|ixy_d~7_combout ) +// # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_ir_we~7_combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'hF444; +defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~29_combout = ((\z80_|execute_|ctl_alu_shift_oe~24_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~28_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~44_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_ir_we~7_combout & (((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~10_combout +// & (\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'hECE0; +defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~8_combout ) # ((\z80_|pla_decode_|Equal41~2_combout & \z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~23_combout = (!\z80_|execute_|ctl_alu_bs_oe~combout & (((\z80_|execute_|ixy_d~15_combout & !\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~23_combout ))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h020F; +defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) # +// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_mWrite~17_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (\z80_|execute_|ctl_sw_4u~1_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~32_combout = (\z80_|execute_|ctl_alu_shift_oe~30_combout & (\z80_|execute_|ctl_alu_shift_oe~31_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~7_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~23_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~10_combout & ((\z80_|execute_|ctl_alu_shift_oe~29_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hCCEF; +defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~17_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h88A8; +defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~18_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h7740; +defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~18_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~18_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'h5F40; +defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_alu_shift_oe~19_combout ) # (\z80_|execute_|ctl_mWrite~9_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~19_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h7470; +defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~20_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~20_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'h5C4C; +defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~22_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~21_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h0E0C; +defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~36_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~22_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & +// (((!\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~2_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & \z80_|reg_control_|reg_sys_we_lo~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_ir_we~9_combout & +// (((!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_ir_we~10_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|nM1_int~2_combout & +// (((!\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & (!\z80_|execute_|ctl_alu_oe~15_combout & \z80_|execute_|ctl_alu_res_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datac(\z80_|execute_|ctl_alu_oe~15_combout ), + .datad(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~15_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_alu_res_oe~1_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datad(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'hA0E0; +defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~0_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hEFCF; +defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_alu_op1_oe~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~0 ( +// Equation(s): +// \z80_|alu_|db_high[3]~0_combout = (\z80_|execute_|ctl_alu_bs_oe~combout ) # (((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (\z80_|execute_|ctl_alu_op1_oe~1_combout )) # (!\z80_|execute_|ctl_alu_res_oe~2_combout )) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~0 .lut_mask = 16'hFFFB; +defparam \z80_|alu_|db_high[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'h0103; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout & (\z80_|execute_|nextM~11_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .datac(\z80_|execute_|nextM~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~53 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|pla_decode_|Equal21~1_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_sw_2u~2_combout & ((!\z80_|execute_|ctl_mRead~6_combout ) # (!\z80_|execute_|ctl_alu_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2u~0_combout ), + .datab(\z80_|execute_|ctl_sw_2u~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~2_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hDF00; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_sw_2u~5_combout & (\z80_|execute_|ctl_reg_gp_sel~7_combout & (\z80_|ir_|opcode [0] $ (!\z80_|execute_|comb~0_combout )))) # (!\z80_|execute_|ctl_sw_2u~5_combout & ((\z80_|ir_|opcode [0] $ +// (!\z80_|execute_|comb~0_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2u~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|comb~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'hD00D; +defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFAEA; +defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~3_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|rsel3~combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7077; +defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout & (!\z80_|execute_|ctl_sw_2u~6_combout & \z80_|execute_|ctl_reg_out_hi~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .datac(\z80_|execute_|ctl_sw_2u~6_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~7_combout = ((\z80_|execute_|ctl_reg_out_hi~8_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ))) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = ((\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|execute_|setM1~47_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datab(\z80_|execute_|setM1~47_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'h7F0F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'h0EFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~30_combout ) + + .dataa(\z80_|execute_|ctl_al_we~14_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|setM1~30_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'hDF0F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & !\z80_|execute_|rsel3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFCFD; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ) # ((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hFF75; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # (!\z80_|execute_|ctl_reg_gp_we~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h2202; +defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~15_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~6_combout = ((\z80_|execute_|ctl_reg_use_sp~5_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout )) # (!\z80_|execute_|ctl_reg_use_sp~3_combout ) + + .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hFF5F; +defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N26 +cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( +// Equation(s): +// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal21~2_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N27 +dffeas \z80_|reg_control_|bank_af ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_af~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_af~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_af .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N30 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h4040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_hl2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_hl~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~32 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[3]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~3_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~4_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~2_combout ))))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|reg_control_|bank_hl_de2~q ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~3 .lut_mask = 16'hA280; +defparam \z80_|reg_control_|reg_sel_de2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~4_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~2_combout )))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|reg_control_|reg_sel_de2~2_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), + .datad(\z80_|reg_control_|bank_hl_de1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h5044; +defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_de~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datac(\z80_|reg_control_|reg_sel_de~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~31 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[3]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_iy~2_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|decode_state_|DFFE_inst4~q & \z80_|decode_state_|DFFE_instIY1~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h3000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hCC00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h4000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h3030; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|decode_state_|DFFE_inst4~q & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h4000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~34_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~34 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~15_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # (((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout )) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~16_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ctl_sw_4u~4_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h0015; +defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~50_combout & \z80_|execute_|ctl_inc_cy~99_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_cy~50_combout ), + .datad(\z80_|execute_|ctl_inc_cy~99_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & (\z80_|execute_|fMRead~6_combout & (\z80_|execute_|ctl_reg_sel_wz~16_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), + .datab(\z80_|execute_|fMRead~6_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~16_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~18_combout = ((\z80_|execute_|ctl_reg_sel_wz~15_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~21_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~17_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~18_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_wz~18_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~36_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~36 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[3]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h1000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~33 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[3]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; +defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h0088; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~10_combout = (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|execute_|ctl_reg_in_hi~10_combout ) # (!\z80_|execute_|ctl_reg_in_hi~9_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout )) # (!\z80_|execute_|ctl_reg_in_hi~3_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [3] & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[3]~14_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .datad(\z80_|alu_|db[3]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~37_combout = (\z80_|reg_file_|gdfx_temp1[3]~34_combout & (\z80_|reg_file_|gdfx_temp1[3]~36_combout & (\z80_|reg_file_|gdfx_temp1[3]~33_combout & \z80_|reg_file_|gdfx_temp1[3]~35_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~34_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~36_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~33_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~37 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~38_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout & (\z80_|reg_file_|gdfx_temp1[3]~32_combout & (\z80_|reg_file_|gdfx_temp1[3]~31_combout & \z80_|reg_file_|gdfx_temp1[3]~37_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[3]~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~32_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~31_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~37_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~38 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~20_combout ) # (((\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hEAFF; +defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~6_combout = ((\z80_|execute_|ctl_sw_4u~5_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~17_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout ))) # (!\z80_|execute_|ctl_sw_4u~3_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~3_combout ), + .datab(\z80_|execute_|ctl_sw_4u~5_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFEC; +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~11_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~16_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~39_combout = ((\z80_|reg_file_|gdfx_temp1[3]~38_combout & ((\z80_|reg_file_|db_hi_as[3]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~38_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~39 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|gdfx_temp1[3]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N24 +cycloneive_lcell_comb \z80_|alu_|db[3]~13 ( +// Equation(s): +// \z80_|alu_|db[3]~13_combout = (\z80_|alu_|db_low[3]~26_combout & (((\z80_|reg_file_|gdfx_temp1[3]~39_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) # (!\z80_|alu_|db_low[3]~26_combout & (!\z80_|execute_|ctl_alu_oe~14_combout & +// ((\z80_|reg_file_|gdfx_temp1[3]~39_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) + + .dataa(\z80_|alu_|db_low[3]~26_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .datad(\z80_|execute_|ctl_alu_oe~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~13 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~20_combout ) # (\z80_|execute_|ctl_alu_shift_oe~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hEEEA; +defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~11_combout )) # (!\z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|nextM~2_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|rsel3~combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'hC444; +defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~12_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal77~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|pla_decode_|Equal77~0_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h3313; +defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_2d~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~8_combout ), + .datac(\z80_|execute_|ctl_sw_2d~10_combout ), + .datad(\z80_|execute_|ctl_sw_2d~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hF2FA; +defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~12_combout ) # ((\z80_|execute_|ctl_sw_2d~11_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~12_combout ), + .datac(\z80_|execute_|ctl_sw_2d~11_combout ), + .datad(\z80_|execute_|ctl_sw_2d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~30_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ctl_mRead~24_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datac(\z80_|execute_|ctl_mWrite~11_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|execute_|ctl_bus_db_we~5_combout & (\z80_|execute_|ctl_alu_oe~9_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|ctl_alu_oe~4_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~5_combout ), + .datab(\z80_|execute_|ctl_alu_oe~9_combout ), + .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datad(\z80_|execute_|ctl_alu_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_alu_oe~10_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .datac(\z80_|execute_|ctl_alu_oe~10_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|alu_control_|db[3]~36_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_flags_alu~19_combout )))) # (!\z80_|alu_control_|db[3]~36_combout & +// (((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_flags_alu~19_combout )))) + + .dataa(\z80_|alu_control_|db[3]~36_combout ), + .datab(\z80_|execute_|ctl_flags_bus~combout ), + .datac(\z80_|alu_|db_low[3]~26_combout ), + .datad(\z80_|execute_|ctl_flags_alu~19_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_ir_we~12_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & \z80_|pla_decode_|Equal56~0_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal56~0_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~14_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_flags_xy_we~13_combout ) # (!\z80_|execute_|ctl_flags_xy_we~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hFFCF; +defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~15_combout = (\z80_|execute_|ctl_flags_xy_we~14_combout ) # (((!\z80_|execute_|ctl_flags_xy_we~17_combout ) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) + + .dataa(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|execute_|ctl_flags_sz_we~5_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # +// (!\z80_|execute_|ctl_alu_core_R~0_combout & (\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_flags_xy_we~15_combout ) # (((!\z80_|execute_|ctl_flags_pf_we~5_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) + + .dataa(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N19 +dffeas \z80_|alu_flags_|flags_xf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_xf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_xf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~50 ( +// Equation(s): +// \z80_|execute_|setM1~50_combout = (!\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|setM1~49_combout & ((!\z80_|pla_decode_|Equal3~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|setM1~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~50 .lut_mask = 16'h0700; +defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )) # (!\z80_|execute_|setM1~50_combout ))) + + .dataa(\z80_|execute_|setM1~50_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_flags_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h3133; +defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( +// Equation(s): +// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h1333; +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( +// Equation(s): +// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) + + .dataa(\z80_|alu_flags_|flags_xf~q ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(gnd), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'hBB00; +defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N0 +cycloneive_lcell_comb \z80_|sw1_|db_down[3]~3 ( +// Equation(s): +// \z80_|sw1_|db_down[3]~3_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) + + .dataa(\z80_|execute_|ctl_sw_1d~6_combout ), + .datab(\z80_|bus_control_|db[3]~21_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[3]~3 .lut_mask = 16'hECEE; +defparam \z80_|sw1_|db_down[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h5500; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h0808; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h4400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N9 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~51_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N7 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h4040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (\z80_|reg_control_|bank_exx~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h0008; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[3]~36_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .datad(\z80_|alu_control_|db[3]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hC4C4; +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|decode_state_|DFFE_inst4~q & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h4000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) + + .dataa(\z80_|decode_state_|DFFE_inst4~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h2000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0100; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|reg_control_|bank_exx~q ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0004; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & (\z80_|reg_file_|gdfx_temp0[3]~46_combout & \z80_|reg_file_|gdfx_temp0[3]~47_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_de~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de2~3_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_de2~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~51_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_de~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_de~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N13 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~42 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[3]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N15 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~49_combout & (\z80_|reg_file_|gdfx_temp0[3]~42_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~42_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~91 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~91_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & ((\z80_|reg_control_|reg_sel_hl2~0_combout ) # (\z80_|reg_control_|reg_sel_hl~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~91_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~91 .lut_mask = 16'h2220; +defparam \z80_|reg_file_|gdfx_temp0[0]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # (\z80_|execute_|ctl_sw_4u~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~19_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~91_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ) # (\z80_|reg_file_|gdfx_temp0[0]~20_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~91_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal11~0_combout )) # +// (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h113F; +defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~43_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & (\z80_|execute_|ctl_bus_inc_oe~42_combout & (\z80_|execute_|ctl_bus_inc_oe~28_combout & !\z80_|execute_|ctl_reg_sys_we~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~88_combout = (\z80_|execute_|ctl_inc_cy~87_combout & (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_inc_cy~87_combout ), + .datac(\z80_|execute_|ctl_sw_4u~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'h444C; +defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_inc_cy~61_combout & (\z80_|execute_|ctl_inc_cy~88_combout & \z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), + .datab(\z80_|execute_|ctl_inc_cy~88_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~38_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|fMRead~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), + .datad(\z80_|execute_|fMRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hA8AA; +defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_bus_inc_oe~38_combout ) # (((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~49_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~32_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|ctl_mRead~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|pla_decode_|Equal13~2_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~47_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((!\z80_|execute_|ctl_bus_inc_oe~34_combout ) # (!\z80_|execute_|nextM~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~48_combout = (\z80_|execute_|ctl_bus_inc_oe~47_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~37_combout & (\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'hCCEC; +defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~46_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~4_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'h00C8; +defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_bus_inc_oe~39_combout ) # (((\z80_|execute_|ctl_bus_inc_oe~48_combout ) # (\z80_|execute_|ctl_bus_inc_oe~46_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~50_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~39_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~50_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~44_combout = (((\z80_|execute_|ctl_bus_inc_oe~40_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~6_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (\z80_|execute_|ctl_apin_mux~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datad(\z80_|execute_|ctl_apin_mux~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h0700; +defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|execute_|ctl_sw_4d~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~44_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~25 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~25_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|decode_state_|in_halt~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(gnd), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~25 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|pc_inc_hold~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~67_combout = ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout ) # (\z80_|execute_|ctl_mRead~2_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mWrite~4_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~64_combout = ((!\z80_|execute_|ctl_alu_op_low~14_combout & ((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) # (!\z80_|pla_decode_|Equal10~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h1F3F; +defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~65_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ) # (!\z80_|execute_|ctl_inc_cy~64_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout )) # (!\z80_|execute_|ctl_reg_sys_we~1_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .datad(\z80_|execute_|ctl_inc_cy~64_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~34_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h80A0; +defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~66_combout = ((\z80_|execute_|ctl_inc_cy~65_combout ) # (\z80_|execute_|ctl_inc_cy~63_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datab(\z80_|execute_|ctl_inc_cy~65_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_cy~63_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'hFFDD; +defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~66_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~67_combout ) # (!\z80_|execute_|fMRead~7_combout )))) + + .dataa(\z80_|execute_|fMRead~7_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_inc_cy~67_combout ), + .datad(\z80_|execute_|ctl_inc_cy~66_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hFFC4; +defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~58_combout = (\z80_|execute_|ctl_mWrite~6_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ixy_d~9_combout )))) # (!\z80_|execute_|ctl_mWrite~6_combout & +// (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'hECA0; +defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_inc_cy~58_combout ) # (((\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|execute_|ctl_inc_cy~99_combout )) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|execute_|ctl_inc_cy~58_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_inc_cy~99_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'hECFF; +defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~60_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_inc_cy~59_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datad(\z80_|execute_|ctl_inc_cy~59_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|ctl_inc_cy~97_combout ) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_inc_cy~97_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hEF0F; +defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~62_combout = ((\z80_|execute_|ctl_inc_cy~60_combout ) # ((\z80_|execute_|ctl_inc_cy~57_combout ) # (!\z80_|execute_|ctl_inc_cy~47_combout ))) # (!\z80_|execute_|ctl_inc_cy~61_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~61_combout ), + .datab(\z80_|execute_|ctl_inc_cy~60_combout ), + .datac(\z80_|execute_|ctl_inc_cy~57_combout ), + .datad(\z80_|execute_|ctl_inc_cy~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~18 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~18_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ctl_mRead~13_combout +// & (\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~18 .lut_mask = 16'hEAC8; +defparam \z80_|execute_|pc_inc_hold~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal33~2_combout & \z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal33~2_combout ), + .datad(\z80_|decode_state_|use_ixiy~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~17 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~17_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # (!\z80_|execute_|pc_inc_hold~14_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|pc_inc_hold~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~17 .lut_mask = 16'hECFC; +defparam \z80_|execute_|pc_inc_hold~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~19 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~19_combout = (\z80_|pla_decode_|Equal6~1_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout )))) # (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_mRead~8_combout & +// ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_alu_op_low~14_combout )))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~19 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|pc_inc_hold~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~20 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~20_combout = (\z80_|execute_|pc_inc_hold~18_combout ) # ((\z80_|execute_|pc_inc_hold~17_combout ) # ((\z80_|execute_|pc_inc_hold~19_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~18_combout ), + .datab(\z80_|execute_|pc_inc_hold~17_combout ), + .datac(\z80_|execute_|pc_inc_hold~19_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~20 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|pc_inc_hold~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~36_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hA080; +defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~15 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~15_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|pla_decode_|Equal12~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~15 .lut_mask = 16'hFF57; +defparam \z80_|execute_|pc_inc_hold~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~16 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~16_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~16 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|pc_inc_hold~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~21 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~21_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|pc_inc_hold~15_combout & \z80_|execute_|pc_inc_hold~16_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~20_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|pc_inc_hold~15_combout ), + .datad(\z80_|execute_|pc_inc_hold~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~21 .lut_mask = 16'h1000; +defparam \z80_|execute_|pc_inc_hold~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|pc_inc_hold~25_combout & (((\z80_|execute_|ctl_inc_cy~62_combout & \z80_|execute_|pc_inc_hold~21_combout )))) # (!\z80_|execute_|pc_inc_hold~25_combout & ((\z80_|execute_|ctl_inc_cy~68_combout ) # +// ((\z80_|execute_|ctl_inc_cy~62_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~25_combout ), + .datab(\z80_|execute_|ctl_inc_cy~68_combout ), + .datac(\z80_|execute_|ctl_inc_cy~62_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hF454; +defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y9_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~52_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~14_combout ) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|pla_decode_|Equal24~0_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ixy_d~10_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ixy_d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hC800; +defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~22 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~22_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~22 .lut_mask = 16'hCCC0; +defparam \z80_|execute_|pc_inc_hold~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~23 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~23_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|pc_inc_hold~22_combout )))) # +// (!\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|pc_inc_hold~22_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|pc_inc_hold~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~23 .lut_mask = 16'hECA0; +defparam \z80_|execute_|pc_inc_hold~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~35_combout = (\z80_|execute_|pc_inc_hold~23_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|pc_inc_hold~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'hFF80; +defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~24 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~24_combout = (!\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout & (!\z80_|execute_|pc_inc_hold~34_combout & (!\z80_|execute_|pc_inc_hold~35_combout & \z80_|execute_|pc_inc_hold~21_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .datab(\z80_|execute_|pc_inc_hold~34_combout ), + .datac(\z80_|execute_|pc_inc_hold~35_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~24 .lut_mask = 16'h0100; +defparam \z80_|execute_|pc_inc_hold~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_inc_cy~52_combout & \z80_|execute_|pc_inc_hold~24_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~52_combout ), + .datac(gnd), + .datad(\z80_|execute_|pc_inc_hold~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~54_combout = (\z80_|execute_|ctl_mWrite~17_combout & (\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_inc_cy~53_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_inc_cy~53_combout ), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'h8088; +defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~74_combout = (((!\z80_|pla_decode_|Equal33~1_combout ) # (!\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~75_combout = ((!\z80_|execute_|pc_inc_hold~17_combout & (\z80_|execute_|ctl_inc_cy~74_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ))) # (!\z80_|execute_|pc_inc_hold~25_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|ctl_inc_cy~74_combout ), + .datac(\z80_|execute_|pc_inc_hold~25_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h0F4F; +defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~73_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|execute_|ctl_sw_4u~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), + .datab(\z80_|execute_|pc_inc_hold~20_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h3020; +defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~75_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_inc_cy~73_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~95 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~95_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~95_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~95 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_inc_cy~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~72_combout = (!\z80_|execute_|pc_inc_hold~20_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|pc_inc_hold~15_combout & !\z80_|execute_|ctl_inc_cy~95_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~20_combout ), + .datab(\z80_|execute_|pc_inc_hold~36_combout ), + .datac(\z80_|execute_|pc_inc_hold~15_combout ), + .datad(\z80_|execute_|ctl_inc_cy~95_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~27 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~27_combout = (\z80_|execute_|pc_inc_hold~18_combout ) # ((\z80_|execute_|pc_inc_hold~17_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~18_combout ), + .datab(\z80_|execute_|pc_inc_hold~17_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~27 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|pc_inc_hold~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~77_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & (\z80_|execute_|ctl_mRead~12_combout & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~78_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|execute_|ctl_inc_cy~77_combout ) # ((!\z80_|execute_|pc_inc_hold~17_combout & !\z80_|execute_|ctl_reg_sys_hilo~20_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|execute_|pc_inc_hold~17_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), + .datad(\z80_|execute_|ctl_inc_cy~77_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'hAA02; +defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout ) # ((!\z80_|execute_|pc_inc_hold~27_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~27_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|ctl_inc_cy~78_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'hFF40; +defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # ((\z80_|execute_|pc_inc_hold~25_combout & ((\z80_|execute_|pc_inc_hold~20_combout ) # (!\z80_|execute_|pc_inc_hold~15_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), + .datab(\z80_|execute_|pc_inc_hold~15_combout ), + .datac(\z80_|execute_|pc_inc_hold~25_combout ), + .datad(\z80_|execute_|pc_inc_hold~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFABA; +defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~71_combout = ((!\z80_|execute_|ctl_inc_cy~64_combout & (!\z80_|execute_|pc_inc_hold~34_combout & \z80_|execute_|pc_inc_hold~21_combout ))) # (!\z80_|execute_|ctl_inc_cy~70_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~64_combout ), + .datab(\z80_|execute_|pc_inc_hold~34_combout ), + .datac(\z80_|execute_|ctl_inc_cy~70_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h1F0F; +defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~76_combout ) # ((\z80_|execute_|ctl_inc_cy~72_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout ) # (\z80_|execute_|ctl_inc_cy~71_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), + .datab(\z80_|execute_|ctl_inc_cy~72_combout ), + .datac(\z80_|execute_|ctl_inc_cy~79_combout ), + .datad(\z80_|execute_|ctl_inc_cy~71_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & ((\z80_|execute_|pc_inc_hold~24_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) # +// (!\z80_|execute_|ctl_inc_cy~94_combout & (((\z80_|execute_|pc_inc_hold~24_combout )) # (!\z80_|execute_|pc_inc_hold~25_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~94_combout ), + .datab(\z80_|execute_|pc_inc_hold~25_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datad(\z80_|execute_|pc_inc_hold~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hF531; +defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N0 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~26 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~26_combout = (\z80_|execute_|pc_inc_hold~34_combout ) # ((\z80_|execute_|pc_inc_hold~35_combout ) # (!\z80_|execute_|pc_inc_hold~21_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|pc_inc_hold~34_combout ), + .datac(\z80_|execute_|pc_inc_hold~35_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~26 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|pc_inc_hold~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~56_combout = (\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_alu_op_low~14_combout & (\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|pc_inc_hold~26_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~55_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'hAAEA; +defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|execute_|ctl_inc_cy~69_combout ) # ((\z80_|execute_|ctl_inc_cy~54_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~56_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), + .datab(\z80_|execute_|ctl_inc_cy~54_combout ), + .datac(\z80_|execute_|ctl_inc_cy~80_combout ), + .datad(\z80_|execute_|ctl_inc_cy~56_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~85_combout = (((!\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|ctl_inc_cy~49_combout )) # (!\z80_|execute_|ctl_inc_cy~51_combout )) # (!\z80_|execute_|ctl_inc_cy~44_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), + .datab(\z80_|execute_|ctl_inc_cy~51_combout ), + .datac(\z80_|execute_|ctl_inc_cy~49_combout ), + .datad(\z80_|execute_|ctl_inc_cy~45_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~89 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~89_combout = (\z80_|execute_|ctl_inc_cy~85_combout ) # ((!\z80_|execute_|ctl_inc_cy~48_combout ) # (!\z80_|execute_|ctl_inc_cy~88_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~85_combout ), + .datab(\z80_|execute_|ctl_inc_cy~88_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_cy~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~89_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~89 .lut_mask = 16'hBBFF; +defparam \z80_|execute_|ctl_inc_cy~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~90 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~90_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~14_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~90_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~90 .lut_mask = 16'h0515; +defparam \z80_|execute_|ctl_inc_cy~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~91 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~91_combout = (\z80_|execute_|ctl_inc_cy~89_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_inc_cy~90_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~89_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_inc_cy~90_combout ), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~91_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~91 .lut_mask = 16'hEAEE; +defparam \z80_|execute_|ctl_inc_cy~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~84_combout = ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_inc_cy~83_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_inc_cy~96_combout ) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_inc_cy~83_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_inc_cy~96_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~100 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~100_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~100_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~100 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~100 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~92 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~92_combout = (\z80_|execute_|ctl_inc_cy~84_combout ) # ((\z80_|execute_|ctl_inc_cy~91_combout & ((\z80_|execute_|ctl_inc_cy~100_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~91_combout ), + .datab(\z80_|execute_|ctl_inc_cy~84_combout ), + .datac(\z80_|execute_|ctl_inc_cy~100_combout ), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~92_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~92 .lut_mask = 16'hECEE; +defparam \z80_|execute_|ctl_inc_cy~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~28_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~9_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'hC080; +defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~82_combout = (\z80_|execute_|pc_inc_hold~24_combout & (!\z80_|execute_|pc_inc_hold~28_combout & (\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout & \z80_|execute_|ctl_inc_cy~52_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~24_combout ), + .datab(\z80_|execute_|pc_inc_hold~28_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .datad(\z80_|execute_|ctl_inc_cy~52_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|execute_|ctl_alu_op_low~14_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((!\z80_|execute_|pc_inc_hold~33_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datad(\z80_|execute_|pc_inc_hold~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'h8AAA; +defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|pc_inc_hold~22_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|pc_inc_hold~22_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|pc_inc_hold~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hF888; +defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|pc_inc_hold~29_combout ) # ((\z80_|execute_|pc_inc_hold~30_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~33_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|pc_inc_hold~33_combout ), + .datac(\z80_|execute_|pc_inc_hold~29_combout ), + .datad(\z80_|execute_|pc_inc_hold~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hFFF2; +defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N26 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|pc_inc_hold~31_combout ) # (((\z80_|execute_|pc_inc_hold~28_combout ) # (!\z80_|execute_|pc_inc_hold~24_combout )) # (!\z80_|execute_|ctl_inc_cy~52_combout )) + + .dataa(\z80_|execute_|pc_inc_hold~31_combout ), + .datab(\z80_|execute_|ctl_inc_cy~52_combout ), + .datac(\z80_|execute_|pc_inc_hold~28_combout ), + .datad(\z80_|execute_|pc_inc_hold~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~93 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~93_combout = (\z80_|execute_|ctl_inc_cy~82_combout ) # ((\z80_|execute_|ctl_inc_cy~92_combout & ((!\z80_|execute_|pc_inc_hold~25_combout ) # (!\z80_|execute_|pc_inc_hold~32_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~92_combout ), + .datab(\z80_|execute_|ctl_inc_cy~82_combout ), + .datac(\z80_|execute_|pc_inc_hold~32_combout ), + .datad(\z80_|execute_|pc_inc_hold~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~93_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~93 .lut_mask = 16'hCEEE; +defparam \z80_|execute_|ctl_inc_cy~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N14 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~81_combout ), + .datac(\z80_|execute_|ctl_inc_cy~93_combout ), + .datad(\z80_|address_latch_|Q [0]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h03FC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N19 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y17_N17 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal47~0_combout & !\z80_|execute_|ctl_mRead~10_combout ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~10 ( +// Equation(s): +// \z80_|alu_control_|db[0]~10_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[0]~17_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|bus_control_|db[0]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~10 .lut_mask = 16'h4C0C; +defparam \z80_|alu_control_|db[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N31 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) # (!\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|alu_|db[0]~18_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[0]~18_combout & (!\z80_|execute_|ctl_reg_in_hi~11_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~27_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & (\z80_|reg_file_|gdfx_temp1[0]~24_combout & \z80_|reg_file_|gdfx_temp1[0]~26_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout & \z80_|reg_file_|gdfx_temp1[0]~28_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[0]~15_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_inc_dec~4_combout )) # (!\z80_|execute_|fIOWrite~0_combout ))) + + .dataa(\z80_|execute_|fIOWrite~0_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~9_combout = (\z80_|execute_|ctl_inc_dec~8_combout ) # (((\z80_|ir_|opcode [3] & !\z80_|execute_|ctl_reg_gp_we~2_combout )) # (!\z80_|execute_|ctl_inc_dec~3_combout )) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .datac(\z80_|execute_|ctl_inc_dec~8_combout ), + .datad(\z80_|execute_|ctl_inc_dec~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hF2FF; +defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_dec~9_combout ), + .datad(\z80_|execute_|ctl_inc_dec~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hF0FF; +defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) + + .dataa(\z80_|address_latch_|Q [4]), + .datab(\z80_|execute_|ctl_inc_dec~5_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h5595; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h5F5F; +defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~11_combout = (((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|execute_|ctl_inc_dec~5_combout ), + .datac(\z80_|execute_|ctl_inc_dec~9_combout ), + .datad(\z80_|execute_|ctl_inc_dec~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ) + + .dataa(\z80_|address_latch_|Q [2]), + .datab(gnd), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h5A5A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N5 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y17_N3 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N5 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|execute_|ctl_reg_sel_wz~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N11 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h2220; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|DFFE_instCB~q & \z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_ir_we~5_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~6_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hECCC; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~9 ( +// Equation(s): +// \z80_|alu_|db_low[2]~9_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[3]~14_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[1]~16_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[3]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~9 .lut_mask = 16'hFC0C; +defparam \z80_|alu_|db_low[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~10 ( +// Equation(s): +// \z80_|alu_|db_low[2]~10_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~9_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~12_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(\z80_|alu_|db[2]~12_combout ), + .datad(\z80_|alu_|db_low[2]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~10 .lut_mask = 16'hFD75; +defparam \z80_|alu_|db_low[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~1 ( +// Equation(s): +// \z80_|alu_|db_high[3]~1_combout = (\z80_|alu_|db_high[3]~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|db_high[3]~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~1 .lut_mask = 16'hFFF0; +defparam \z80_|alu_|db_high[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~4_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'hFFF5; +defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~10 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & (\z80_|execute_|ctl_flags_pf_we~4_combout & \z80_|execute_|ctl_flags_hf_we~5_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datac(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .lut_mask = 16'h8080; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~17 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~17_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_iorw~10_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~17 .lut_mask = 16'h0054; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~18 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~18_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|ir_|opcode [4] & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~18 .lut_mask = 16'h2030; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~38_combout = (!\z80_|execute_|ctl_alu_op_low~15_combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~38 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_alu_op_low~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~11 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout = (!\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout & (\z80_|execute_|ctl_alu_op_low~38_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~17_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~18_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .lut_mask = 16'h1050; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y8_N22 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~12 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & ((!\z80_|pla_decode_|Equal62~2_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .lut_mask = 16'h4C00; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_ir_we~15_combout & ((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # +// (!\z80_|execute_|ctl_state_alu~2_combout & (((!\z80_|execute_|ctl_ir_we~9_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_alu_core_R~2_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_S~8_combout & \z80_|execute_|ctl_alu_core_R~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|execute_|ctl_ir_we~11_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~10_combout )))) # +// (!\z80_|execute_|ctl_ir_we~7_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_ir_we~10_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~10_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h222A; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~11_combout & \z80_|execute_|ctl_alu_core_R~3_combout +// ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFCD; +defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~9_combout = ((!\z80_|execute_|ctl_alu_core_S~11_combout ) # (!\z80_|execute_|ctl_alu_core_S~5_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_core_S~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'h77FF; +defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~combout = ((\z80_|execute_|ctl_alu_core_S~9_combout ) # ((\z80_|pla_decode_|Equal62~2_combout & \z80_|pla_decode_|Equal9~0_combout ))) # (!\z80_|execute_|ctl_alu_core_S~8_combout ) + + .dataa(\z80_|pla_decode_|Equal62~2_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_alu_core_S .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal73~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hE000; +defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~combout = ((\z80_|pla_decode_|Equal73~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~5_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout ))) # (!\z80_|execute_|ctl_alu_core_R~3_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~3_combout ), + .datab(\z80_|pla_decode_|Equal73~2_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_alu_op_low~41_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hF3F3; +defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~29_combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # (!\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_alu_op_low~16_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~16_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~34_combout & (((\z80_|pla_decode_|Equal39~0_combout & +// \z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFA88; +defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~31_combout = ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~29_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) # (!\z80_|execute_|ctl_alu_op_low~25_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((\z80_|pla_decode_|Equal40~1_combout & +// \z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'hF8C8; +defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~40_combout = (\z80_|execute_|ctl_alu_op_low~32_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~40 .lut_mask = 16'hCCEC; +defparam \z80_|execute_|ctl_alu_op_low~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~33_combout = (\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'hE000; +defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~combout = (\z80_|execute_|ctl_alu_op_low~31_combout ) # ((\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~33_combout ) # (!\z80_|execute_|ctl_alu_op_low~23_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~33_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~59 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~58 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N11 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~61_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~61 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[7]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y12_N19 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~62_combout = (\z80_|alu_|db[7]~20_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ))) # (!\z80_|alu_|db[7]~20_combout & (!\z80_|execute_|ctl_reg_in_hi~11_combout & +// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .datad(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~62 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp1[7]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N21 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~63 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[7]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~60 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~64_combout = (\z80_|reg_file_|gdfx_temp1[7]~61_combout & (\z80_|reg_file_|gdfx_temp1[7]~62_combout & (\z80_|reg_file_|gdfx_temp1[7]~63_combout & \z80_|reg_file_|gdfx_temp1[7]~60_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~61_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~62_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~63_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~60_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~64 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~65_combout = (\z80_|reg_file_|gdfx_temp1[7]~59_combout & (\z80_|reg_file_|gdfx_temp1[7]~58_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout & \z80_|reg_file_|gdfx_temp1[7]~64_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~59_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~58_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[7]~17_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~64_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~65 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[7]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_control_|reg_sys_we_lo~combout ) # (!\z80_|execute_|ctl_reg_sel_ir~1_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'hF700; +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~16 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~16_combout = (\z80_|reg_file_|gdfx_temp1[7]~66_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~66_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~16 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[7]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N17 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[7]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_pc~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~17 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~17_combout = (\z80_|reg_file_|db_hi_as[7]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[7]~16_combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~17 .lut_mask = 16'h88AA; +defparam \z80_|reg_file_|db_hi_as[7]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N25 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N1 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [1] & ((\z80_|alu_|db[1]~16_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[1]~16_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .datad(\z80_|alu_|db[1]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~10_combout & (\z80_|reg_file_|gdfx_temp1[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~11_combout & \z80_|reg_file_|gdfx_temp1[1]~12_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~8_combout & (\z80_|reg_file_|gdfx_temp1[1]~9_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout & \z80_|reg_file_|gdfx_temp1[1]~14_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[1]~14_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hBB00; +defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N6 +cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( +// Equation(s): +// \z80_|address_latch_|abusz [8] = (\z80_|reg_file_|db_hi_as[0]~6_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [8]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h0A0A; +defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )) # (!\z80_|execute_|ctl_al_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~14_combout ), + .datab(\z80_|execute_|ctl_al_we~5_combout ), + .datac(\z80_|execute_|ctl_apin_mux~1_combout ), + .datad(\z80_|pla_decode_|Equal33~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hF070; +defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~9_combout = (\z80_|execute_|ctl_al_we~13_combout & (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & +// (((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h7770; +defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~9_combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )) + + .dataa(\z80_|execute_|ctl_al_we~9_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEAFF; +defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~7_combout = ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_alu_oe~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~5_combout ), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .datad(\z80_|execute_|ctl_mWrite~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~8_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_al_we~7_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )) # (!\z80_|execute_|setM1~46_combout ))) + + .dataa(\z80_|execute_|setM1~46_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_al_we~4_combout ), + .datad(\z80_|execute_|ctl_al_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~10_combout ) # ((\z80_|execute_|ctl_al_we~8_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~6_combout ), + .datab(\z80_|execute_|ctl_al_we~10_combout ), + .datac(\z80_|execute_|ctl_al_we~8_combout ), + .datad(\z80_|execute_|ctl_sw_4d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~12_combout = (\z80_|execute_|ctl_al_we~11_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|setM1~53_combout )) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_al_we~11_combout ), + .datad(\z80_|execute_|setM1~53_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hF8FF; +defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N7 +dffeas \z80_|address_latch_|Q[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [8]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y15_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~82_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~82 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[7]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N25 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~81 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[7]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~12 ( +// Equation(s): +// \z80_|alu_control_|db[6]~12_combout = ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|execute_|ctl_flags_oe~2_combout )) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) + + .dataa(gnd), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~12 .lut_mask = 16'hFFF3; +defparam \z80_|alu_control_|db[6]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|alu_|db_high[3]~7_combout & ((\z80_|execute_|ctl_flags_alu~19_combout ) # ((\z80_|alu_control_|db[7]~37_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_high[3]~7_combout & +// (((\z80_|alu_control_|db[7]~37_combout & \z80_|execute_|ctl_flags_bus~combout )))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_flags_alu~19_combout ), + .datac(\z80_|alu_control_|db[7]~37_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~3_combout ) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N11 +dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( +// Equation(s): +// \z80_|alu_control_|db[7]~18_combout = (\z80_|alu_|db[7]~20_combout & (((!\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_|db[7]~20_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((!\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_|db[7]~20_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h4F44; +defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~19 ( +// Equation(s): +// \z80_|alu_control_|db[7]~19_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[7]~18_combout & ((\z80_|reg_file_|gdfx_temp0[7]~90_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .datad(\z80_|alu_control_|db[7]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~19 .lut_mask = 16'h00C4; +defparam \z80_|alu_control_|db[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~20 ( +// Equation(s): +// \z80_|alu_control_|db[7]~20_combout = (\z80_|alu_control_|db[7]~19_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datab(\z80_|bus_control_|db[7]~7_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|alu_control_|db[7]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~20 .lut_mask = 16'h4F00; +defparam \z80_|alu_control_|db[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~37 ( +// Equation(s): +// \z80_|alu_control_|db[7]~37_combout = (\z80_|alu_control_|db[7]~20_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|alu_control_|db[6]~12_combout & !\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datab(\z80_|alu_control_|db[6]~12_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|alu_control_|db[7]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~37 .lut_mask = 16'hFF01; +defparam \z80_|alu_control_|db[7]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~37_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|alu_control_|db[7]~37_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~90_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|gdfx_temp0[7]~84_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .datad(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y17_N29 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|gdfx_temp0[7]~87_combout & (\z80_|reg_file_|gdfx_temp0[7]~86_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & \z80_|reg_file_|gdfx_temp0[7]~83_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|gdfx_temp0[7]~82_combout & (\z80_|reg_file_|gdfx_temp0[7]~81_combout & \z80_|reg_file_|gdfx_temp0[7]~88_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~82_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~81_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~90_combout = ((\z80_|reg_file_|gdfx_temp0[7]~89_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .datab(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8AFF; +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[7]~90_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .datab(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) + + .dataa(gnd), + .datab(\z80_|address_latch_|Q [7]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h33CC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'h8AFF; +defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( +// Equation(s): +// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [7]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N3 +dffeas \z80_|address_latch_|Q[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [7]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [8] & !\z80_|address_latch_|Q +// [7])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [8] & \z80_|address_latch_|Q [7])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [8]), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h2008; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N18 +cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( +// Equation(s): +// \z80_|address_latch_|abusz [9] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[1]~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [9]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N19 +dffeas \z80_|address_latch_|Q[9] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [9]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y16_N21 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~44_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [2] & ((\z80_|alu_|db[2]~12_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[2]~12_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~44 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[2]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N17 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~45_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~45 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[2]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~42 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~43_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~43 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[2]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~46_combout = (\z80_|reg_file_|gdfx_temp1[2]~44_combout & (\z80_|reg_file_|gdfx_temp1[2]~45_combout & (\z80_|reg_file_|gdfx_temp1[2]~42_combout & \z80_|reg_file_|gdfx_temp1[2]~43_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~44_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~45_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~42_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~46 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~48_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~40 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~41 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~47_combout = (\z80_|reg_file_|gdfx_temp1[2]~46_combout & (\z80_|reg_file_|gdfx_temp1[2]~40_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout & \z80_|reg_file_|gdfx_temp1[2]~41_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~46_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~40_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[2]~13_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~41_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~47 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~48_combout = ((\z80_|reg_file_|gdfx_temp1[2]~47_combout & ((\z80_|reg_file_|db_hi_as[2]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~47_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~48 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp1[2]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~10 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [2] & ((\z80_|reg_file_|gdfx_temp1[2]~48_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[2]~48_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .datad(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~10 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|db_hi_as[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~11 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~11_combout = (\z80_|reg_file_|db_hi_as[2]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[2]~10_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~11 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|db_hi_as[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N22 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ +// (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [10]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~12 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~12_combout = ((\z80_|reg_file_|db_hi_as[2]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|reg_file_|db_hi_as[2]~11_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~12 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|db_hi_as[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N0 +cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( +// Equation(s): +// \z80_|address_latch_|abusz [10] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[2]~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[2]~12_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [10]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N1 +dffeas \z80_|address_latch_|Q[10] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [10]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [9] & (!\z80_|execute_|ctl_inc_dec~11_combout & +// \z80_|address_latch_|Q [10])) # (!\z80_|address_latch_|Q [9] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [10])))) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [10]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h2400; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~50 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~49 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~51_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~51 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~52_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~52 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[4]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N8 +cycloneive_lcell_comb \z80_|alu_|db[4]~8 ( +// Equation(s): +// \z80_|alu_|db[4]~8_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~57_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[4]~33_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[4]~33_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~8 .lut_mask = 16'hF351; +defparam \z80_|alu_|db[4]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N2 +cycloneive_lcell_comb \z80_|alu_|db[4]~10 ( +// Equation(s): +// \z80_|alu_|db[4]~10_combout = ((\z80_|alu_|db[4]~8_combout & ((\z80_|alu_|db_high[0]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[4]~8_combout ), + .datad(\z80_|alu_|db_high[0]~25_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~10 .lut_mask = 16'hF575; +defparam \z80_|alu_|db[4]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~53_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [4] & ((\z80_|alu_|db[4]~10_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[4]~10_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .datad(\z80_|alu_|db[4]~10_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~53 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N25 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~54_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~54 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[4]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~55_combout = (\z80_|reg_file_|gdfx_temp1[4]~51_combout & (\z80_|reg_file_|gdfx_temp1[4]~52_combout & (\z80_|reg_file_|gdfx_temp1[4]~53_combout & \z80_|reg_file_|gdfx_temp1[4]~54_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~51_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~52_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~53_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~54_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~55 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~56_combout = (\z80_|reg_file_|gdfx_temp1[4]~50_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout & (\z80_|reg_file_|gdfx_temp1[4]~49_combout & \z80_|reg_file_|gdfx_temp1[4]~55_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~50_combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|db[4]~16_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~49_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~55_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~56 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~57_combout = ((\z80_|reg_file_|gdfx_temp1[4]~56_combout & ((\z80_|reg_file_|db_hi_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~56_combout ), + .datac(\z80_|reg_file_|db_hi_as[4]~15_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~57 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|gdfx_temp1[4]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[4]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~13 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~13_combout = (\z80_|reg_file_|gdfx_temp1[4]~57_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[4]~57_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~57_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~13 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[4]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[4]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~14 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~14_combout = (\z80_|reg_file_|db_hi_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_hi_as[4]~13_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~14 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|db_hi_as[4]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N14 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ +// (\z80_|address_latch_|Q [11]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [12]), + .datad(\z80_|address_latch_|Q [11]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hD278; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~15 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~15_combout = ((\z80_|reg_file_|db_hi_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datab(\z80_|reg_file_|db_hi_as[4]~14_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~15 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|db_hi_as[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N12 +cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( +// Equation(s): +// \z80_|address_latch_|abusz [12] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[4]~15_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(\z80_|reg_file_|db_hi_as[4]~15_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [12]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h3030; +defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N13 +dffeas \z80_|address_latch_|Q[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [12]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [12] & +// !\z80_|address_latch_|Q [11])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [12] & \z80_|address_latch_|Q [11])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [12]), + .datad(\z80_|address_latch_|Q [11]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2008; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h55AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[5]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~76 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[5]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~77 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[5]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~84_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~79_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~79 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[5]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op_low~23_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_alu_oe~3_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (((\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_66_oe~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h0088; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFCC; +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N25 +dffeas \z80_|alu_|op1_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h00A0; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_zero~combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~18 ( +// Equation(s): +// \z80_|alu_|db_low[1]~18_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~12_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~18 .lut_mask = 16'hFA0A; +defparam \z80_|alu_|db_low[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~19 ( +// Equation(s): +// \z80_|alu_|db_low[1]~19_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[1]~18_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[1]~16_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[1]~16_combout ), + .datac(\z80_|alu_|db_low[1]~18_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~19 .lut_mask = 16'hF0CC; +defparam \z80_|alu_|db_low[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( +// Equation(s): +// \z80_|alu_|db_low[1]~16_combout = (\z80_|alu_|op1_low [1] & (((\z80_|alu_|op2_low [1])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_low [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [1]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_low [1]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op2_low [1]), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hAF23; +defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( +// Equation(s): +// \z80_|alu_|db_low[1]~15_combout = ((\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'h0F2F; +defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N27 +dffeas \z80_|alu_|result_lo[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N26 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( +// Equation(s): +// \z80_|alu_|db_low[1]~17_combout = (\z80_|alu_|db_low[1]~16_combout & (\z80_|alu_|db_low[1]~15_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) + + .dataa(\z80_|alu_|db_low[1]~16_combout ), + .datab(\z80_|alu_|db_low[1]~15_combout ), + .datac(\z80_|alu_|result_lo [1]), + .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'h8880; +defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~20 ( +// Equation(s): +// \z80_|alu_|db_low[1]~20_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[1]~19_combout & ((\z80_|alu_|db_low[1]~17_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~17_combout ) # +// (!\z80_|alu_|db_high[3]~0_combout )))) + + .dataa(\z80_|alu_|db_low[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[3]~0_combout ), + .datad(\z80_|alu_|db_low[1]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~20 .lut_mask = 16'hBB03; +defparam \z80_|alu_|db_low[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & \z80_|alu_|db_low[1]~20_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|alu_|db_low[1]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'hF000; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hAE00; +defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[1]~19_combout )))) + + .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|alu_|db_high[1]~19_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .lut_mask = 16'h00EA; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFFFC; +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N21 +dffeas \z80_|alu_|op1_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'hCE00; +defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [1]), + .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'hE200; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[1]~20_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), + .datad(\z80_|alu_|db_low[1]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h3230; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # (\z80_|execute_|ctl_alu_op2_sel_zero~combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFEFE; +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N9 +dffeas \z80_|alu_|op2_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~14_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y6_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout )) # (!\z80_|execute_|ctl_alu_op_low~41_combout +// )) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~10_combout & (\z80_|execute_|ctl_flags_alu~21_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & \z80_|execute_|ctl_alu_core_S~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datab(\z80_|execute_|ctl_flags_alu~21_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ) # ((!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ) # (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~2_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout +// )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFBF3; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout = (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[1]~20_combout )))) # +// (!\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[1]~20_combout )))) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datad(\z80_|alu_|db_low[1]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N11 +dffeas \z80_|alu_|op2_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~25_combout ) # (\z80_|execute_|ctl_mRead~24_combout )))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) + + .dataa(\z80_|execute_|ctl_mRead~25_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'hCF8F; +defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N16 +cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~2 ( +// Equation(s): +// \z80_|alu_|alu_op2[1]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [1]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [1])))) + + .dataa(\z80_|alu_|op2_low [1]), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|alu_|op2_high [1]), + .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[1]~2 .lut_mask = 16'h3C66; +defparam \z80_|alu_|alu_op2[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[1]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|alu_|alu_op2[1]~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hC808; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[1]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high +// [1])))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|alu_|alu_op2[1]~2_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0131; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hF1F1; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & (!\z80_|execute_|ctl_alu_core_S~combout & +// !\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h3337; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ) # +// ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'h3F0A; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & (\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_bus~16_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h3000; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N29 +dffeas \z80_|alu_|op1_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout = (\z80_|alu_|db_high[2]~13_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[2]~14_combout )))) # +// (!\z80_|alu_|db_high[2]~13_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[2]~14_combout )))) + + .dataa(\z80_|alu_|db_high[2]~13_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datad(\z80_|alu_|db_low[2]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h0A0A; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N3 +dffeas \z80_|alu_|op2_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( +// Equation(s): +// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op2_high [2]), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hAF23; +defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~8 ( +// Equation(s): +// \z80_|alu_|db_high[2]~8_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db[7]~20_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~8 .lut_mask = 16'hCFC0; +defparam \z80_|alu_|db_high[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( +// Equation(s): +// \z80_|alu_|db_high[2]~9_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[2]~8_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[6]~22_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(\z80_|alu_|db[6]~22_combout ), + .datad(\z80_|alu_|db_high[2]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'hFD75; +defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( +// Equation(s): +// \z80_|alu_|db_high[2]~11_combout = (!\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[4]~19_combout )) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'h4400; +defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( +// Equation(s): +// \z80_|alu_|db_high[2]~12_combout = (\z80_|alu_|db_high[2]~10_combout & (\z80_|alu_|db_high[2]~9_combout & ((\z80_|alu_|db_high[2]~11_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|alu_|db_high[2]~10_combout ), + .datac(\z80_|alu_|db_high[2]~9_combout ), + .datad(\z80_|alu_|db_high[2]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hC040; +defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( +// Equation(s): +// \z80_|alu_|db_high[2]~13_combout = ((\z80_|alu_|db_high[2]~12_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_high[2]~12_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hBBB3; +defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~68 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~75_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (\z80_|reg_file_|b2v_latch_de2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout & (((\z80_|reg_file_|b2v_latch_de_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~67 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N25 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N19 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~72 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~70 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~69 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~71_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [6] & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .datad(\z80_|alu_|db[6]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~71 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~73_combout = (\z80_|reg_file_|gdfx_temp1[6]~72_combout & (\z80_|reg_file_|gdfx_temp1[6]~70_combout & (\z80_|reg_file_|gdfx_temp1[6]~69_combout & \z80_|reg_file_|gdfx_temp1[6]~71_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~72_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~70_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~69_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~71_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~73 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~74_combout = (\z80_|reg_file_|gdfx_temp1[6]~68_combout & (\z80_|reg_file_|gdfx_temp1[6]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout & \z80_|reg_file_|gdfx_temp1[6]~73_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~68_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~67_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[6]~18_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~74 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N26 +cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( +// Equation(s): +// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~21_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h3300; +defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N27 +dffeas \z80_|address_latch_|Q[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [14]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datac(\z80_|address_latch_|Q [14]), + .datad(\z80_|execute_|ctl_inc_dec~11_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'hB478; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~19 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp1[6]~75_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[6]~75_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~19 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~20_combout = (\z80_|reg_file_|db_hi_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~19_combout ), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~20 .lut_mask = 16'hF030; +defparam \z80_|reg_file_|db_hi_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~21_combout = ((\z80_|reg_file_|db_hi_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[6]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~21 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_hi_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~75_combout = ((\z80_|reg_file_|gdfx_temp1[6]~74_combout & ((\z80_|reg_file_|db_hi_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~74_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~21_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~75 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|gdfx_temp1[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N16 +cycloneive_lcell_comb \z80_|alu_|db[6]~21 ( +// Equation(s): +// \z80_|alu_|db[6]~21_combout = (\z80_|alu_control_|db[6]~23_combout & (((\z80_|reg_file_|gdfx_temp1[6]~75_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[6]~23_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[6]~75_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) + + .dataa(\z80_|alu_control_|db[6]~23_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~75_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~21 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N26 +cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( +// Equation(s): +// \z80_|alu_|db[6]~22_combout = ((\z80_|alu_|db[6]~21_combout & ((\z80_|alu_|db_high[2]~13_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|alu_|db[6]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF755; +defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( +// Equation(s): +// \z80_|alu_|db_high[1]~16_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_|db[6]~22_combout ), + .datad(\z80_|alu_|db[4]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hF3C0; +defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( +// Equation(s): +// \z80_|alu_|db_high[1]~17_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[1]~16_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[5]~24_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datad(\z80_|alu_|db_high[1]~16_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hFC0C; +defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N4 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~14 ( +// Equation(s): +// \z80_|alu_|db_high[1]~14_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[4]~19_combout ), + .datab(\z80_|bus_control_|db[3]~21_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~14 .lut_mask = 16'h4F0F; +defparam \z80_|alu_|db_high[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( +// Equation(s): +// \z80_|alu_|db_high[1]~15_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [1]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_high [1]), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( +// Equation(s): +// \z80_|alu_|db_high[1]~18_combout = (\z80_|alu_|db_high[1]~14_combout & (\z80_|alu_|db_high[1]~15_combout & ((\z80_|alu_|db_high[1]~17_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[1]~17_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[1]~14_combout ), + .datad(\z80_|alu_|db_high[1]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hB000; +defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( +// Equation(s): +// \z80_|alu_|db_high[1]~19_combout = ((\z80_|alu_|db_high[1]~18_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datac(\z80_|alu_|db_high[1]~18_combout ), + .datad(\z80_|alu_|db_high[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'hE0FF; +defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N4 +cycloneive_lcell_comb \z80_|alu_|db[5]~23 ( +// Equation(s): +// \z80_|alu_|db[5]~23_combout = (\z80_|reg_file_|gdfx_temp1[5]~84_combout & (((\z80_|alu_control_|db[5]~17_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) # (!\z80_|reg_file_|gdfx_temp1[5]~84_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[5]~17_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[5]~17_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~23 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db[5]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N10 +cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( +// Equation(s): +// \z80_|alu_|db[5]~24_combout = ((\z80_|alu_|db[5]~23_combout & ((\z80_|alu_|db_high[1]~19_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[5]~23_combout ), + .datad(\z80_|alu_|db[7]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hB0FF; +defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~80_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [5] & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_reg_in_hi~11_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[5]~24_combout )) # (!\z80_|execute_|ctl_reg_in_hi~11_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~80 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[5]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~81_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~81 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp1[5]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~78 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[5]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~82_combout = (\z80_|reg_file_|gdfx_temp1[5]~79_combout & (\z80_|reg_file_|gdfx_temp1[5]~80_combout & (\z80_|reg_file_|gdfx_temp1[5]~81_combout & \z80_|reg_file_|gdfx_temp1[5]~78_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~79_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~80_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~81_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~78_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~82 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout = (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (\z80_|execute_|ctl_reg_gp_we~8_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 .lut_mask = 16'hFFF7; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~83_combout = (\z80_|reg_file_|gdfx_temp1[5]~76_combout & (\z80_|reg_file_|gdfx_temp1[5]~77_combout & (\z80_|reg_file_|gdfx_temp1[5]~82_combout & \z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~76_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~77_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~82_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[5]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~83 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~84_combout = ((\z80_|reg_file_|gdfx_temp1[5]~83_combout & ((\z80_|reg_file_|db_hi_as[5]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[5]~24_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~83_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~84 .lut_mask = 16'h8CFF; +defparam \z80_|reg_file_|gdfx_temp1[5]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[5]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~22 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~22_combout = (\z80_|reg_file_|gdfx_temp1[5]~84_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[5]~84_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~84_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~22 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[5]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~23 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~23_combout = (\z80_|reg_file_|db_hi_as[5]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .datab(\z80_|reg_file_|db_hi_as[5]~22_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~23 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_hi_as[5]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~24 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~24_combout = ((\z80_|reg_file_|db_hi_as[5]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[5]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~24 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_hi_as[5]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N20 +cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( +// Equation(s): +// \z80_|address_latch_|abusz [13] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[5]~24_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(\z80_|reg_file_|db_hi_as[5]~24_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [13]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h3030; +defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N21 +dffeas \z80_|address_latch_|Q[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [13]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q [13]) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [13]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h3C3C; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N6 +cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( +// Equation(s): +// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~18_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[7]~18_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h00AA; +defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N7 +dffeas \z80_|address_latch_|Q[15] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [15]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|address_latch_|Q [14]), + .datac(\z80_|execute_|ctl_inc_dec~7_combout ), + .datad(\z80_|execute_|ctl_inc_dec~6_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h3633; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N8 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~18 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~18_combout = ((\z80_|reg_file_|db_hi_as[7]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datab(\z80_|reg_file_|db_hi_as[7]~17_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~18 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|db_hi_as[7]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~66_combout = ((\z80_|reg_file_|gdfx_temp1[7]~65_combout & ((\z80_|reg_file_|db_hi_as[7]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~65_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_hi_as[7]~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~66 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp1[7]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N4 +cycloneive_lcell_comb \z80_|alu_|db[7]~19 ( +// Equation(s): +// \z80_|alu_|db[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~66_combout & (((\z80_|alu_control_|db[7]~37_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~66_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~66_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|alu_control_|db[7]~37_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~19 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N18 +cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( +// Equation(s): +// \z80_|alu_|db[7]~20_combout = ((\z80_|alu_|db[7]~19_combout & ((\z80_|alu_|db_high[3]~7_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[7]~19_combout ), + .datad(\z80_|alu_|db_high[3]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hF575; +defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N8 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (((\z80_|alu_|db[7]~20_combout & \z80_|ir_|opcode [3])))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~18_combout )) # (!\z80_|ir_|opcode [3] & +// ((\z80_|alu_|db[7]~20_combout ))))) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|alu_|db[7]~20_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hE230; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((\z80_|alu_|db_low[3]~8_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_low[3]~8_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|alu_|db_high[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'hC0D0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 .lut_mask = 16'h00F8; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N5 +dffeas \z80_|alu_|op1_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|alu_|db_high[3]~7_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h0088; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N11 +dffeas \z80_|alu_|op1_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N18 +cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~0 ( +// Equation(s): +// \z80_|alu_|alu_op1[3]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [3]))) + + .dataa(\z80_|alu_|op1_low [3]), + .datab(\z80_|alu_|op1_high [3]), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[3]~0 .lut_mask = 16'hAACC; +defparam \z80_|alu_|alu_op1[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (\z80_|alu_|db_low[2]~14_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # +// (!\z80_|alu_|db_low[2]~14_combout & (\z80_|alu_|db_high[2]~13_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|alu_|db_low[2]~14_combout ), + .datab(\z80_|alu_|db_high[2]~13_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N7 +dffeas \z80_|alu_|op1_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [2]))))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|alu_|op1_high [2]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .lut_mask = 16'h88A0; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[2]~14_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|alu_|db_low[2]~14_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .lut_mask = 16'h0F08; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N31 +dffeas \z80_|alu_|op2_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N0 +cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~1 ( +// Equation(s): +// \z80_|alu_|alu_op2[2]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) + + .dataa(\z80_|alu_|op2_high [2]), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datad(\z80_|alu_|op2_low [2]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[2]~1 .lut_mask = 16'h636C; +defparam \z80_|alu_|alu_op2[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [2]))))) + + .dataa(\z80_|alu_|op1_low [2]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_high [2]), + .datad(\z80_|alu_|alu_op2[2]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0047; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[2]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) + + .dataa(\z80_|alu_|alu_op2[2]~1_combout ), + .datab(\z80_|alu_|op1_high [2]), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hA088; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_S~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFF0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hAAFB; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op1[3]~0_combout & ((\z80_|alu_|alu_op2[3]~0_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ))) # +// (!\z80_|alu_|alu_op1[3]~0_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & \z80_|alu_|alu_op2[3]~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(\z80_|alu_|alu_op1[3]~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_|alu_op2[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hEFAE; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout & (\z80_|execute_|ctl_flags_alu~19_combout & !\z80_|execute_|ctl_alu_core_R~combout )) + + .dataa(gnd), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|execute_|ctl_flags_alu~19_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'h00C0; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[0]~14_combout )) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datac(gnd), + .datad(\z80_|alu_control_|db[0]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hEECC; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~4_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) + + .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datab(\z80_|execute_|ctl_flags_bus~5_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_flags_bus~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hBAFA; +defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~6_combout = (\z80_|execute_|ctl_flags_cf_we~3_combout ) # (((\z80_|execute_|ctl_flags_cf_we~5_combout ) # (!\z80_|execute_|ctl_flags_hf_we~2_combout )) # (!\z80_|execute_|ctl_flags_cf_we~2_combout )) + + .dataa(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datac(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~4_combout = ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y6_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|pla_decode_|Equal0~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal0~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~6 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_cf2_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~5_combout = (\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~6_combout ) # ((\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_we~6_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~5 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_flags_cf2_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~5_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~5_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'hF0B8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N21 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N2 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h20A8; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N30 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((!\z80_|ir_|opcode [4] & \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout )) + + .dataa(\z80_|ir_|opcode [4]), + .datab(gnd), + .datac(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hFF50; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( +// Equation(s): +// \z80_|alu_|db_low[0]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~16_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_|db[1]~16_combout ), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hF3C0; +defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( +// Equation(s): +// \z80_|alu_|db_low[0]~22_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[0]~21_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[0]~18_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datab(\z80_|alu_|db[0]~18_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[0]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hEF4F; +defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|db_high[0]~25_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & \z80_|alu_|db_low[0]~27_combout )))) # +// (!\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & (\z80_|alu_|db_low[0]~27_combout ))) + + .dataa(\z80_|alu_|db_high[0]~25_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(\z80_|alu_|db_low[0]~27_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N31 +dffeas \z80_|alu_|op1_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~24 ( +// Equation(s): +// \z80_|alu_|db_low[0]~24_combout = (\z80_|alu_|op2_low [0] & (((\z80_|alu_|op1_low [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_low [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [0]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op1_low [0]), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~24 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_low[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N23 +dffeas \z80_|alu_|result_lo[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( +// Equation(s): +// \z80_|alu_|db_low[0]~23_combout = ((!\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'h0F1F; +defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~25 ( +// Equation(s): +// \z80_|alu_|db_low[0]~25_combout = (\z80_|alu_|db_low[0]~24_combout & (\z80_|alu_|db_low[0]~23_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [0])))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(\z80_|alu_|db_low[0]~24_combout ), + .datac(\z80_|alu_|result_lo [0]), + .datad(\z80_|alu_|db_low[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~25 .lut_mask = 16'hC800; +defparam \z80_|alu_|db_low[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~27 ( +// Equation(s): +// \z80_|alu_|db_low[0]~27_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[0]~22_combout & (\z80_|alu_|db_low[0]~25_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[0]~22_combout & +// \z80_|alu_|db_low[0]~25_combout )) # (!\z80_|alu_|db_high[3]~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db_low[0]~22_combout ), + .datac(\z80_|alu_|db_low[0]~25_combout ), + .datad(\z80_|alu_|db_high[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~27 .lut_mask = 16'hC0D5; +defparam \z80_|alu_|db_low[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])))) + + .dataa(\z80_|alu_|op1_high [0]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [0]), + .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hE200; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[0]~27_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|alu_|db_low[0]~27_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h0F08; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N15 +dffeas \z80_|alu_|op2_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_high[0]~25_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[0]~27_combout )))) # +// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[0]~27_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|db_high[0]~25_combout ), + .datad(\z80_|alu_|db_low[0]~27_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N17 +dffeas \z80_|alu_|op2_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N10 +cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( +// Equation(s): +// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|alu_|op2_high [0]), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h1DE2; +defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_R~3_combout )) # +// (!\z80_|execute_|ctl_alu_core_S~8_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h1FFF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~34_combout = (((\z80_|execute_|ctl_alu_op_low~29_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_alu_op_low~41_combout )) # (!\z80_|execute_|ctl_alu_op_low~25_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~36_combout = (\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~36 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|ctl_alu_op_low~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~35_combout = (\z80_|execute_|ctl_alu_op_low~33_combout ) # ((\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~33_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~40_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~35 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op_low~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~13_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~13 .lut_mask = 16'hD0C0; +defparam \z80_|execute_|ctl_alu_core_hf~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~14_combout = (\z80_|ir_|opcode [5]) # (((!\z80_|pla_decode_|Equal9~0_combout & !\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout )) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~14 .lut_mask = 16'hCFDF; +defparam \z80_|execute_|ctl_alu_core_hf~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~15_combout = (\z80_|execute_|ctl_alu_core_hf~14_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~15 .lut_mask = 16'h8CCC; +defparam \z80_|execute_|ctl_alu_core_hf~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~16_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~15_combout )) # (!\z80_|execute_|ctl_alu_core_hf~12_combout ) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~16 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|ctl_alu_core_hf~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~17_combout = (\z80_|execute_|ctl_alu_op_low~36_combout & (!\z80_|execute_|ctl_alu_op_low~35_combout & ((\z80_|execute_|ctl_alu_core_hf~16_combout )))) # (!\z80_|execute_|ctl_alu_op_low~36_combout & +// ((\z80_|execute_|ctl_alu_core_hf~13_combout ) # ((!\z80_|execute_|ctl_alu_op_low~35_combout & \z80_|execute_|ctl_alu_core_hf~16_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~36_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~13_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~17 .lut_mask = 16'h7350; +defparam \z80_|execute_|ctl_alu_core_hf~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|execute_|ixy_d~6_combout ) # ((!\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ixy_d~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hF3F0; +defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout & !\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'h88C8; +defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ctl_alu_op_low~18_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~23_combout = (!\z80_|execute_|ctl_alu_op_low~27_combout & ((\z80_|execute_|ctl_alu_core_hf~36_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|execute_|ctl_alu_op_low~17_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h0E0A; +defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~34_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'h1333; +defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~29_combout = (\z80_|execute_|ctl_mRead~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((!\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'hB0A0; +defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|execute_|ctl_mRead~4_combout +// & (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal56~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_alu_op_low~17_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((\z80_|execute_|ixy_d~7_combout ) # (\z80_|execute_|ctl_alu_core_hf~35_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & +// (((\z80_|execute_|ctl_alu_core_hf~35_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'h7740; +defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~28_combout = (\z80_|execute_|ctl_alu_core_hf~26_combout & ((\z80_|execute_|ctl_alu_core_hf~27_combout ) # ((\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_op_low~14_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'hAA80; +defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~34_combout & ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # (\z80_|execute_|ctl_alu_core_hf~28_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~37_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (((\z80_|execute_|ctl_alu_op_low~20_combout ) # (!\z80_|execute_|ctl_state_alu~11_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), + .datad(\z80_|execute_|ctl_state_alu~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~37 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_alu_op_low~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_state_alu~2_combout & (((\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # +// (\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'hFC20; +defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~25_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (!\z80_|execute_|ctl_alu_op_low~20_combout & ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_alu_core_hf~24_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'h0032; +defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~31_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((\z80_|execute_|ctl_alu_core_hf~25_combout ) # ((\z80_|execute_|ctl_alu_core_hf~30_combout & !\z80_|execute_|ctl_alu_op_low~37_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~37_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'hFFAE; +defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~20_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hD0C0; +defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~20_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hCEEE; +defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~18_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~18_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~22_combout = (\z80_|execute_|ctl_alu_op_low~34_combout & (((!\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_alu_core_hf~19_combout )))) # (!\z80_|execute_|ctl_alu_op_low~34_combout & +// ((\z80_|execute_|ctl_alu_core_hf~21_combout ) # ((!\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_alu_core_hf~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'h4F44; +defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((\z80_|execute_|ctl_alu_core_hf~22_combout ) # ((\z80_|execute_|ctl_alu_core_hf~38_combout & !\z80_|execute_|ctl_alu_op_low~31_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hFCFE; +defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~33_combout = (\z80_|execute_|ctl_alu_core_hf~17_combout ) # ((\z80_|execute_|ctl_alu_core_hf~32_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N20 +cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( +// Equation(s): +// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~33_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~33_combout & (\z80_|alu_flags_|flags_cf~combout )) + + .dataa(\z80_|alu_flags_|flags_cf~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .datad(\z80_|alu_flags_|flags_hf~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hFA0A; +defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[0]~1_combout & \z80_|alu_control_|alu_core_cf_in~0_combout )))) +// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_control_|alu_core_cf_in~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[0]~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_|alu_op1[0]~1_combout ), + .datad(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( +// Equation(s): +// \z80_|alu_|db_high[0]~21_combout = (\z80_|alu_|op2_high [0] & (((\z80_|alu_|op1_high [0]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_high [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [0]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|alu_|op2_high [0]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|alu_|op1_high [0]), + .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N16 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( +// Equation(s): +// \z80_|alu_|db_high[0]~22_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~14_combout )) + + .dataa(\z80_|ir_|opcode [3]), + .datab(gnd), + .datac(\z80_|alu_|db[3]~14_combout ), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hFA50; +defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N2 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( +// Equation(s): +// \z80_|alu_|db_high[0]~23_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[0]~22_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[4]~10_combout )) + + .dataa(\z80_|alu_|db[4]~10_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(gnd), + .datad(\z80_|alu_|db_high[0]~22_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hEE22; +defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~20 ( +// Equation(s): +// \z80_|alu_|db_high[0]~20_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~15_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[4]~19_combout ), + .datab(\z80_|bus_control_|db[3]~21_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~20 .lut_mask = 16'h1F0F; +defparam \z80_|alu_|db_high[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N10 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( +// Equation(s): +// \z80_|alu_|db_high[0]~24_combout = (\z80_|alu_|db_high[0]~21_combout & (\z80_|alu_|db_high[0]~20_combout & ((\z80_|alu_|db_high[0]~23_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[0]~21_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[0]~23_combout ), + .datad(\z80_|alu_|db_high[0]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hA200; +defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( +// Equation(s): +// \z80_|alu_|db_high[0]~25_combout = ((\z80_|alu_|db_high[0]~24_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datac(\z80_|alu_|db_high[0]~24_combout ), + .datad(\z80_|alu_|db_high[3]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'hE0FF; +defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) + + .dataa(\z80_|alu_|db_high[0]~25_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h0088; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y10_N23 +dffeas \z80_|alu_|op1_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( +// Equation(s): +// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_high [0]), + .datad(\z80_|alu_|op1_low [0]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hFC30; +defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) + + .dataa(\z80_|alu_|op2_low [0]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|alu_|op2_high [0]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hE2E2; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_|alu_op1[0]~1_combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|alu_|alu_op1[0]~1_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hBE28; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|execute_|ctl_alu_core_R~combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|execute_|ctl_alu_core_S~combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(\z80_|execute_|ctl_alu_core_R~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h0032; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h0F0E; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55F7; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hF2A2; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N19 +dffeas \z80_|alu_|result_lo[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N8 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~11 ( +// Equation(s): +// \z80_|alu_|db_low[2]~11_combout = (\z80_|alu_|result_lo [2]) # (\z80_|execute_|ctl_alu_res_oe~2_combout ) + + .dataa(gnd), + .datab(\z80_|alu_|result_lo [2]), + .datac(gnd), + .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~11 .lut_mask = 16'hFFCC; +defparam \z80_|alu_|db_low[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N2 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~12 ( +// Equation(s): +// \z80_|alu_|db_low[2]~12_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [2] & ((\z80_|alu_|op2_low [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [2]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_low [2]), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~12 .lut_mask = 16'hDD0D; +defparam \z80_|alu_|db_low[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[4]~19_combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h5500; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~13 ( +// Equation(s): +// \z80_|alu_|db_low[2]~13_combout = (\z80_|alu_|db_low[2]~12_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|alu_|db_low[2]~12_combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~13 .lut_mask = 16'h7050; +defparam \z80_|alu_|db_low[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N28 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~14 ( +// Equation(s): +// \z80_|alu_|db_low[2]~14_combout = ((\z80_|alu_|db_low[2]~10_combout & (\z80_|alu_|db_low[2]~11_combout & \z80_|alu_|db_low[2]~13_combout ))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_low[2]~10_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|alu_|db_low[2]~11_combout ), + .datad(\z80_|alu_|db_low[2]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~14 .lut_mask = 16'hB333; +defparam \z80_|alu_|db_low[2]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N24 +cycloneive_lcell_comb \z80_|alu_|db[2]~11 ( +// Equation(s): +// \z80_|alu_|db[2]~11_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[2]~48_combout & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[2]~30_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~48_combout ), + .datad(\z80_|alu_control_|db[2]~30_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~11 .lut_mask = 16'hF531; +defparam \z80_|alu_|db[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N22 +cycloneive_lcell_comb \z80_|alu_|db[2]~12 ( +// Equation(s): +// \z80_|alu_|db[2]~12_combout = ((\z80_|alu_|db[2]~11_combout & ((\z80_|alu_|db_low[2]~14_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db_low[2]~14_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db[2]~11_combout ), + .datad(\z80_|alu_|db[7]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~12 .lut_mask = 16'hB0FF; +defparam \z80_|alu_|db[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( +// Equation(s): +// \z80_|alu_control_|db[2]~28_combout = (\z80_|alu_|db[2]~12_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~q & ((\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_|db[2]~12_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((!\z80_|alu_flags_|DFFE_inst_latch_pf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_|db[2]~12_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h7350; +defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N12 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( +// Equation(s): +// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~33_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & +// (((\z80_|alu_flags_|flags_hf2~q )))) + + .dataa(\z80_|alu_control_|db[4]~33_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datac(\z80_|alu_flags_|flags_hf2~q ), + .datad(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hEEF0; +defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N13 +dffeas \z80_|alu_flags_|flags_hf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|flags_hf2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_hf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N12 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( +// Equation(s): +// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [2]) # (\z80_|alu_|op1_low [1]))) + + .dataa(gnd), + .datab(\z80_|alu_|op1_low [3]), + .datac(\z80_|alu_|op1_low [2]), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hCCC0; +defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~combout = (\z80_|pla_decode_|Equal47~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~24 ( +// Equation(s): +// \z80_|alu_control_|db[2]~24_combout = (\z80_|alu_flags_|flags_hf2~q ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|execute_|ctl_66_oe~combout ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|alu_flags_|flags_hf2~q ), + .datab(\z80_|alu_control_|out[6]~0_combout ), + .datac(\z80_|execute_|ctl_66_oe~combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~24 .lut_mask = 16'hFEFF; +defparam \z80_|alu_control_|db[2]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datac(\z80_|execute_|rsel3~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # (\z80_|pla_decode_|Equal40~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout )) + + .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[2]~1_combout = (\z80_|reg_file_|gdfx_temp0[2]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[2]~1 .lut_mask = 16'hCCEC; +defparam \z80_|reg_file_|db_lo_ds[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N18 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( +// Equation(s): +// \z80_|alu_control_|db[2]~29_combout = (\z80_|reg_file_|db_lo_ds[2]~1_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[2]~13_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), + .datab(\z80_|reg_file_|db_lo_ds[2]~1_combout ), + .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datad(\z80_|bus_control_|db[2]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h4C44; +defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~30 ( +// Equation(s): +// \z80_|alu_control_|db[2]~30_combout = ((!\z80_|alu_control_|db[2]~28_combout & (\z80_|alu_control_|db[2]~24_combout & \z80_|alu_control_|db[2]~29_combout ))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_control_|db[2]~28_combout ), + .datab(\z80_|alu_control_|db[2]~24_combout ), + .datac(\z80_|alu_control_|db[6]~13_combout ), + .datad(\z80_|alu_control_|db[2]~29_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~30 .lut_mask = 16'h4F0F; +defparam \z80_|alu_control_|db[2]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [2] & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|alu_control_|db[2]~30_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .datad(\z80_|alu_control_|db[2]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N31 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~41_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~41_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y17_N29 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & (\z80_|reg_file_|gdfx_temp0[2]~37_combout & \z80_|reg_file_|gdfx_temp0[2]~36_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_lo|db[2]~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~35_combout & (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~39_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~41_combout = ((\z80_|reg_file_|gdfx_temp0[2]~40_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .datac(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp0[2]~41_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[2]~41_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hCC0C; +defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hDF55; +defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N26 +cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( +// Equation(s): +// \z80_|address_latch_|abusz [2] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[2]~9_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [2]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N27 +dffeas \z80_|address_latch_|Q[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [2]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N18 +cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( +// Equation(s): +// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [3]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N21 +dffeas \z80_|address_latch_|Q[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_latch_|abusz [3]), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [2] & +// !\z80_|address_latch_|Q [3])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [2] & \z80_|address_latch_|Q [3])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [2]), + .datad(\z80_|address_latch_|Q [3]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h2008; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [4] $ +// (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [4]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [5]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N15 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[5]~17_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .datad(\z80_|alu_control_|db[5]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|gdfx_temp0[5]~65_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hC4C4; +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N15 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N31 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y17_N25 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|gdfx_temp0[5]~67_combout & (\z80_|reg_file_|gdfx_temp0[5]~66_combout & (\z80_|reg_file_|gdfx_temp0[5]~68_combout & \z80_|reg_file_|gdfx_temp0[5]~64_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N9 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~62_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~62 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[5]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~63_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~62_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~62_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~71_combout = ((\z80_|reg_file_|gdfx_temp0[5]~70_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'h8AFF; +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .datad(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .datab(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .datab(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'h8CFF; +defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N30 +cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( +// Equation(s): +// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~18_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [5]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N31 +dffeas \z80_|address_latch_|Q[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [5]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout = \z80_|address_latch_|Q [5] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|execute_|ctl_inc_dec~6_combout ), + .datac(\z80_|address_latch_|Q [5]), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0F4B; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N31 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N21 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~72 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[6]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|execute_|ctl_reg_sel_wz~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & ((\z80_|alu_control_|db[6]~23_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|alu_control_|db[6]~23_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .datad(\z80_|alu_control_|db[6]~23_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y17_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout & (\z80_|reg_file_|gdfx_temp0[6]~77_combout & (\z80_|reg_file_|gdfx_temp0[6]~75_combout & \z80_|reg_file_|gdfx_temp0[6]~76_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_lo|db[6]~1_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N27 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~80_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N21 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|gdfx_temp0[6]~73_combout & (\z80_|reg_file_|gdfx_temp0[6]~72_combout & (\z80_|reg_file_|gdfx_temp0[6]~78_combout & \z80_|reg_file_|gdfx_temp0[6]~74_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~72_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~80_combout = ((\z80_|reg_file_|gdfx_temp0[6]~79_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hCC44; +defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datab(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'h8CFF; +defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( +// Equation(s): +// \z80_|address_latch_|abusz [6] = (\z80_|reg_file_|db_lo_as[6]~21_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h00CC; +defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N15 +dffeas \z80_|address_latch_|Q[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [6]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~7_combout ) # (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|execute_|ctl_inc_dec~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|execute_|ctl_inc_dec~10_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h0312; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q [7]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [8]), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'hD278; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [0] & ((\z80_|reg_file_|gdfx_temp1[0]~30_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[0]~30_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hAA22; +defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hB3BB; +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N20 +cycloneive_lcell_comb \z80_|alu_|db[0]~17 ( +// Equation(s): +// \z80_|alu_|db[0]~17_combout = (\z80_|reg_file_|gdfx_temp1[0]~30_combout & (((\z80_|alu_|db_low[0]~27_combout )) # (!\z80_|execute_|ctl_alu_oe~14_combout ))) # (!\z80_|reg_file_|gdfx_temp1[0]~30_combout & (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_|db_low[0]~27_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db_low[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~17 .lut_mask = 16'hA2F3; +defparam \z80_|alu_|db[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N30 +cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( +// Equation(s): +// \z80_|alu_|db[0]~18_combout = ((\z80_|alu_|db[0]~17_combout & ((\z80_|alu_control_|db[0]~14_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_control_|db[0]~14_combout ), + .datab(\z80_|alu_|db[0]~17_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|alu_|db[7]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~18 .lut_mask = 16'h8CFF; +defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N20 +cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( +// Equation(s): +// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~18_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) + + .dataa(\z80_|alu_|db[0]~18_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|sw2_|db_up[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hAAFF; +defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~11 ( +// Equation(s): +// \z80_|alu_control_|db[0]~11_combout = (\z80_|alu_control_|db[0]~10_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|alu_control_|db[0]~10_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datad(\z80_|sw2_|db_up[0]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~11 .lut_mask = 16'h8A00; +defparam \z80_|alu_control_|db[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~14 ( +// Equation(s): +// \z80_|alu_control_|db[0]~14_combout = ((\z80_|alu_control_|db[0]~11_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_control_|db[0]~11_combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|db[6]~13_combout ), + .datad(\z80_|alu_flags_|flags_cf~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~14 .lut_mask = 16'hAF2F; +defparam \z80_|alu_control_|db[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[0]~14_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .datad(\z80_|alu_control_|db[0]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y17_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) # (!\z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_hl~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N1 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout & (\z80_|reg_file_|gdfx_temp0[0]~10_combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_lo|db[0]~2_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .datad(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'hC400; +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~14_combout & (\z80_|reg_file_|gdfx_temp0[0]~15_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .datab(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'h8C00; +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~13_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & (\z80_|reg_file_|gdfx_temp0[0]~11_combout & \z80_|reg_file_|gdfx_temp0[0]~16_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hB0FF; +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[0]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hAA0A; +defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hDF55; +defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N16 +cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( +// Equation(s): +// \z80_|address_latch_|abusz [0] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[0]~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [0]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N17 +dffeas \z80_|address_latch_|Q[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [0]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ ((((\z80_|execute_|ctl_inc_dec~7_combout ) # (\z80_|execute_|ctl_inc_dec~9_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~6_combout ), + .datab(\z80_|address_latch_|Q [0]), + .datac(\z80_|execute_|ctl_inc_dec~7_combout ), + .datad(\z80_|execute_|ctl_inc_dec~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h3339; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout +// ))))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|execute_|ctl_inc_cy~81_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datad(\z80_|execute_|ctl_inc_cy~93_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h5A6A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N17 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N15 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hC4C4; +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|alu_control_|db[1]~27_combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|alu_control_|db[1]~27_combout & +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) + + .dataa(\z80_|alu_control_|db[1]~27_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hBB0B; +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~28_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & \z80_|reg_file_|gdfx_temp0[1]~29_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y15_N3 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N15 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N13 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~23_combout & (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .datab(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'h8AFF; +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[1]~32_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .datad(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hF755; +defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( +// Equation(s): +// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [1]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N0 +cycloneive_lcell_comb \z80_|address_latch_|Q[1]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[1]~feeder_combout = \z80_|address_latch_|abusz [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [1]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N1 +dffeas \z80_|address_latch_|Q[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[1]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(\z80_|execute_|ctl_inc_dec~9_combout ), + .datac(\z80_|execute_|ctl_inc_dec~7_combout ), + .datad(\z80_|execute_|ctl_inc_dec~6_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h5655; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout & +// ((\z80_|execute_|ctl_inc_cy~81_combout ) # (\z80_|execute_|ctl_inc_cy~93_combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .datab(\z80_|execute_|ctl_inc_cy~81_combout ), + .datac(\z80_|execute_|ctl_inc_cy~93_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .lut_mask = 16'hA800; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q +// [2]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [2]), + .datad(\z80_|address_latch_|Q [3]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'hD728; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~51_combout = ((\z80_|reg_file_|gdfx_temp0[3]~50_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( +// Equation(s): +// \z80_|alu_control_|db[3]~35_combout = (\z80_|alu_control_|db[3]~34_combout & (\z80_|sw1_|db_down[3]~3_combout & ((\z80_|reg_file_|gdfx_temp0[3]~51_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|alu_control_|db[3]~34_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|sw1_|db_down[3]~3_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hA020; +defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~36 ( +// Equation(s): +// \z80_|alu_control_|db[3]~36_combout = ((\z80_|alu_control_|db[3]~35_combout & ((\z80_|alu_|db[3]~14_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_|db[3]~14_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_control_|db[6]~13_combout ), + .datad(\z80_|alu_control_|db[3]~35_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~36 .lut_mask = 16'hBF0F; +defparam \z80_|alu_control_|db[3]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N26 +cycloneive_lcell_comb \z80_|alu_|db[3]~14 ( +// Equation(s): +// \z80_|alu_|db[3]~14_combout = ((\z80_|alu_|db[3]~13_combout & ((\z80_|alu_control_|db[3]~36_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~9_combout ), + .datab(\z80_|alu_|db[3]~13_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|alu_control_|db[3]~36_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~14 .lut_mask = 16'hDD5D; +defparam \z80_|alu_|db[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N0 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~4 ( +// Equation(s): +// \z80_|alu_|db_low[3]~4_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~10_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[2]~12_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_|db[2]~12_combout ), + .datad(\z80_|alu_|db[4]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~4 .lut_mask = 16'hFC30; +defparam \z80_|alu_|db_low[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N10 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~5 ( +// Equation(s): +// \z80_|alu_|db_low[3]~5_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~4_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~14_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|alu_|db[3]~14_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datad(\z80_|alu_|db_low[3]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~5 .lut_mask = 16'hFD5D; +defparam \z80_|alu_|db_low[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N25 +dffeas \z80_|alu_|result_lo[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~6 ( +// Equation(s): +// \z80_|alu_|db_low[3]~6_combout = (\z80_|alu_|op1_low [3] & (((\z80_|alu_|op2_low [3])) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))) # (!\z80_|alu_|op1_low [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [3]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_low [3]), + .datab(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op2_low [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~6 .lut_mask = 16'hAF23; +defparam \z80_|alu_|db_low[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~7 ( +// Equation(s): +// \z80_|alu_|db_low[3]~7_combout = (\z80_|alu_|db_low[3]~6_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|alu_|db_low[3]~6_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~7 .lut_mask = 16'h2A0A; +defparam \z80_|alu_|db_low[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~8 ( +// Equation(s): +// \z80_|alu_|db_low[3]~8_combout = (\z80_|alu_|db_low[3]~5_combout & (\z80_|alu_|db_low[3]~7_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [3])))) + + .dataa(\z80_|alu_|db_low[3]~5_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|alu_|result_lo [3]), + .datad(\z80_|alu_|db_low[3]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~8 .lut_mask = 16'hA800; +defparam \z80_|alu_|db_low[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~26 ( +// Equation(s): +// \z80_|alu_|db_low[3]~26_combout = (\z80_|alu_|db_low[3]~8_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[3]~0_combout ), + .datad(\z80_|alu_|db_low[3]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~26 .lut_mask = 16'hFF03; +defparam \z80_|alu_|db_low[3]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) + + .dataa(\z80_|alu_|op1_high [3]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [3]), + .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .lut_mask = 16'hE200; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & \z80_|alu_|db_low[3]~26_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|alu_|db_low[3]~26_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .lut_mask = 16'h0F08; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N13 +dffeas \z80_|alu_|op2_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & ((\z80_|alu_|db_high[3]~7_combout ) # ((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # +// (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((\z80_|alu_|db_low[3]~26_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|alu_|db_high[3]~7_combout ), + .datac(\z80_|alu_|db_low[3]~26_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y9_N21 +dffeas \z80_|alu_|op2_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N14 +cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~0 ( +// Equation(s): +// \z80_|alu_|alu_op2[3]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [3]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [3])))) + + .dataa(\z80_|alu_|op2_low [3]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|alu_|op2_high [3]), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[3]~0 .lut_mask = 16'h1DE2; +defparam \z80_|alu_|alu_op2[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op2[3]~0_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & \z80_|alu_|alu_op1[3]~0_combout )) # (!\z80_|alu_|alu_op2[3]~0_combout & +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & !\z80_|alu_|alu_op1[3]~0_combout )) + + .dataa(\z80_|alu_|alu_op2[3]~0_combout ), + .datab(gnd), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_|alu_op1[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'h0A50; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout & (\z80_|alu_|alu_op2[3]~0_combout )) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout & +// (((!\z80_|execute_|ctl_alu_core_R~4_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[3]~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .lut_mask = 16'hAA3F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( +// Equation(s): +// \z80_|alu_|db_high[3]~4_combout = (\z80_|alu_|op1_high [3] & (((\z80_|alu_|op2_high [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [3]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [3]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_high [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( +// Equation(s): +// \z80_|alu_|db_high[3]~2_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_|db[6]~22_combout ), + .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFC30; +defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( +// Equation(s): +// \z80_|alu_|db_high[3]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[3]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[7]~20_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datab(\z80_|alu_|db[7]~20_combout ), + .datac(\z80_|alu_|db_high[3]~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hE4FF; +defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( +// Equation(s): +// \z80_|alu_|db_high[3]~5_combout = (\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[4]~19_combout )) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'h8800; +defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( +// Equation(s): +// \z80_|alu_|db_high[3]~6_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~3_combout & ((\z80_|alu_|db_high[3]~5_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|alu_|db_high[3]~4_combout ), + .datab(\z80_|alu_|db_high[3]~3_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|db_high[3]~5_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'h8808; +defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( +// Equation(s): +// \z80_|alu_|db_high[3]~7_combout = ((\z80_|alu_|db_high[3]~6_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datad(\z80_|alu_|db_high[3]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'hFB33; +defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|execute_|ctl_flags_alu~19_combout & \z80_|alu_|db_high[3]~7_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datab(\z80_|execute_|ctl_flags_alu~19_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .datad(\z80_|alu_|db_high[3]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFDF5; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y9_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_alu_shift_oe~38_combout & \z80_|execute_|ctl_alu_core_S~11_combout +// ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~11_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout & (((!\z80_|execute_|ctl_state_alu~12_combout ) # (!\z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'h7F00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (!\z80_|pla_decode_|Equal73~2_combout & (!\z80_|execute_|ctl_alu_sel_op2_neg~16_combout & !\z80_|execute_|ctl_alu_op_low~39_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .datab(\z80_|pla_decode_|Equal73~2_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h0002; +defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout & (\z80_|execute_|ctl_alu_core_hf~14_combout & (\z80_|execute_|ctl_flags_nf_we~0_combout & \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal61~2_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~3_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_nf_we~2_combout ) # (!\z80_|execute_|ctl_flags_xy_we~12_combout ))) # (!\z80_|execute_|ctl_flags_nf_we~1_combout ) + + .dataa(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N4 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~14 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~14_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (((!\z80_|execute_|ctl_alu_op_low~17_combout & !\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~14 .lut_mask = 16'h0155; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~13 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout & \z80_|execute_|ctl_alu_core_hf~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~13 .lut_mask = 16'hF000; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~15 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~15_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (!\z80_|pla_decode_|Equal73~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), + .datab(\z80_|pla_decode_|Equal73~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~14_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~15 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~16 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~16_combout = (\z80_|execute_|ctl_flags_nf_we~3_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~3_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .datab(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~16 .lut_mask = 16'hB830; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N25 +dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_nf~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~3_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_op_low~18_combout )))) # (!\z80_|execute_|ctl_state_alu~13_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datad(\z80_|execute_|ctl_state_alu~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'h32FF; +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal68~2_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .datad(\z80_|pla_decode_|Equal68~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hA2A0; +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~5_combout = (\z80_|execute_|ctl_flags_cf_cpl~4_combout ) # ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'hF0FE; +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_set~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_set~0_combout = (\z80_|execute_|ctl_state_alu~12_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal9~0_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~12_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_set~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_set~0 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_cf_set~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout = (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_state_alu~3_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y7_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~27_combout & +// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2~combout ), + .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~2_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((\z80_|execute_|ctl_flags_cf_set~0_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~6_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .datac(\z80_|execute_|ctl_flags_cf_set~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N18 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( +// Equation(s): +// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [1]) # ((\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [0] & \z80_|alu_control_|out[6]~0_combout ))) + + .dataa(\z80_|alu_|op1_high [1]), + .datab(\z80_|alu_|op1_high [0]), + .datac(\z80_|alu_|op1_high [2]), + .datad(\z80_|alu_control_|out[6]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEFA; +defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( +// Equation(s): +// \z80_|alu_control_|out[6]~2_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_|op1_high [3] & \z80_|alu_control_|out[6]~1_combout ))) + + .dataa(\z80_|alu_|op1_high [3]), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|execute_|ctl_66_oe~combout ), + .datad(\z80_|alu_control_|out[6]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFEFC; +defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~18_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~20_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_|db[7]~20_combout ), + .datad(\z80_|alu_|db[0]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hFC30; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N12 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|execute_|ctl_alu_core_R~combout +// & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hCC50; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_we~5_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~5_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_flags_cf2_we~5_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h7430; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N30 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_control_|out[6]~2_combout & !\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|alu_control_|out[6]~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'hF0F8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y11_N31 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~10_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h4050; +defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal10~0_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|pla_decode_|Equal20~0_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y8_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h00EC; +defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~11_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout ))) + + .dataa(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datac(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hAAAC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N14 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = (\z80_|execute_|ctl_state_alu~12_combout & ((\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'h8044; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal63~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'hAEAA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~21_combout = (\z80_|pla_decode_|Equal10~1_combout & (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|pla_decode_|Equal10~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ) # ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~21_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'hFEFF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ) # ((\z80_|execute_|ctl_alu_op_low~28_combout & \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFF8F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) # ((\z80_|execute_|ctl_alu_op_low~35_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'hFFEA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_state_alu~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_state_alu~12_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~1_combout = (\z80_|pla_decode_|Equal64~0_combout & (\z80_|execute_|ctl_alu_op_low~35_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal64~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~35_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~1 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_flags_cf_cpl~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'hA8A0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N30 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout & ((\z80_|execute_|ctl_alu_op_low~30_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~40_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~40_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'hCCC8; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|pla_decode_|Equal61~2_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .lut_mask = 16'h0313; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y6_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout = (\z80_|execute_|ctl_alu_core_R~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & \z80_|execute_|ctl_flags_alu~10_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_R~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_alu~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .lut_mask = 16'h8800; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|nM1_int~2_combout & +// (((!\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal56~0_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .lut_mask = 16'h135F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y7_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~0 .lut_mask = 16'hFCEC; +defparam \z80_|execute_|ctl_flags_cf_cpl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y7_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_flags_cf_cpl~0_combout ) # (!\z80_|execute_|ctl_alu_op_low~34_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h040C; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y7_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = ((!\z80_|pla_decode_|Equal39~0_combout & ((!\z80_|pla_decode_|Equal40~2_combout ) # (!\z80_|ir_|opcode [5])))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal39~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal40~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h5777; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~30_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'h3330; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & \z80_|execute_|ctl_flags_nf_we~0_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .datad(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N2 +cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( +// Equation(s): +// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~1_combout ))))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~1_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_cf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h3600; +defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & (((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (\z80_|nM1_int~2_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (\z80_|pla_decode_|Equal10~0_combout & +// (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hECE0; +defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y8_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~18_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ) # ((\z80_|alu_control_|db[4]~33_combout & \z80_|execute_|ctl_flags_bus~combout )) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[4]~33_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'hFCF0; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N30 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_hf~q )))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (((\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )))) + + .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hFD20; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N31 +dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~9_combout = ((!\z80_|pla_decode_|Equal52~0_combout & ((\z80_|decode_state_|use_ixiy~combout ) # (!\z80_|pla_decode_|Equal44~0_combout )))) # (!\z80_|pla_decode_|Equal33~0_combout ) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~9 .lut_mask = 16'h45FF; +defparam \z80_|execute_|ctl_flags_hf_cpl~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y8_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (\z80_|execute_|ctl_alu_op_low~18_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~18_combout ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ctl_flags_hf_cpl~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y8_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_hf_cpl~10_combout ) # (!\z80_|execute_|ctl_flags_hf_cpl~8_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~8_combout ), + .datad(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'h2202; +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N12 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( +// Equation(s): +// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) + + .dataa(\z80_|alu_flags_|flags_cf~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h393C; +defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( +// Equation(s): +// \z80_|alu_control_|db[4]~31_combout = (\z80_|execute_|ctl_reg_out_lo~8_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[4]~10_combout )) # (!\z80_|reg_file_|gdfx_temp0[4]~61_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~8_combout & +// (\z80_|execute_|ctl_sw_2u~7_combout & ((!\z80_|alu_|db[4]~10_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .datad(\z80_|alu_|db[4]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h0ACE; +defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( +// Equation(s): +// \z80_|alu_control_|db[4]~32_combout = (!\z80_|alu_control_|db[4]~31_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_flags_|flags_hf~combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|db[4]~31_combout ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'h0B00; +defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~33 ( +// Equation(s): +// \z80_|alu_control_|db[4]~33_combout = ((\z80_|alu_control_|db[4]~32_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_control_|db[6]~13_combout ), + .datab(\z80_|execute_|ctl_sw_1d~7_combout ), + .datac(\z80_|bus_control_|db[4]~19_combout ), + .datad(\z80_|alu_control_|db[4]~32_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~33 .lut_mask = 16'hF755; +defparam \z80_|alu_control_|db[4]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N15 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y17_N29 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~52_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~52 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[4]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|gdfx_temp0[4]~52_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|alu_control_|db[4]~33_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[4]~52_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hDD00; +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y17_N23 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y15_N3 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y17_N9 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N1 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y17_N11 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N19 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|gdfx_temp0[4]~58_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datad(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'h8808; +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~56_combout & (\z80_|reg_file_|gdfx_temp0[4]~53_combout & (\z80_|reg_file_|gdfx_temp0[4]~55_combout & \z80_|reg_file_|gdfx_temp0[4]~59_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~61_combout = ((\z80_|reg_file_|gdfx_temp0[4]~60_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'hA2FF; +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .datab(gnd), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hAF00; +defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N22 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ) + + .dataa(\z80_|address_latch_|Q [4]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h55AA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .datab(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N4 +cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( +// Equation(s): +// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~15_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [4]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N5 +dffeas \z80_|address_latch_|Q[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [4]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N6 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [4] & (!\z80_|address_latch_|Q [5] & (!\z80_|address_latch_|Q [6] & !\z80_|address_latch_|Q [7]))) + + .dataa(\z80_|address_latch_|Q [4]), + .datab(\z80_|address_latch_|Q [5]), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N30 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [8] & (!\z80_|address_latch_|Q [9] & !\z80_|address_latch_|Q [11]))) + + .dataa(\z80_|address_latch_|Q [10]), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|Q [11]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N20 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~3_combout = (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [3] & (!\z80_|address_latch_|Q [2] & !\z80_|address_latch_|Q [1]))) + + .dataa(\z80_|address_latch_|Q [0]), + .datab(\z80_|address_latch_|Q [3]), + .datac(\z80_|address_latch_|Q [2]), + .datad(\z80_|address_latch_|Q [1]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0002; +defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N16 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [13] & (!\z80_|address_latch_|Q [12] & (!\z80_|address_latch_|Q [15] & !\z80_|address_latch_|Q [14]))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|address_latch_|Q [12]), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|Q [14]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N26 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~2_combout & (\z80_|decode_state_|DFFE_instNonRep~1_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & \z80_|decode_state_|DFFE_instNonRep~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; +defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N12 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~9_combout & +// ((\z80_|decode_state_|DFFE_instNonRep~4_combout ))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|decode_state_|DFFE_instNonRep~q )))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hF4B0; +defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N13 +dffeas \z80_|decode_state_|DFFE_instNonRep ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instNonRep~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N30 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & (!\z80_|pla_decode_|Equal62~3_combout & (\z80_|execute_|ctl_pf_sel[0]~13_combout & \z80_|execute_|ctl_pf_sel[0]~10_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datab(\z80_|pla_decode_|Equal62~3_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h1000; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N18 +cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( +// Equation(s): +// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & (\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal79~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|pla_decode_|Equal79~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hD8F0; +defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N4 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|interrupts_|DFFE_inst44~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h5F0F; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G16 +cycloneive_clkctrl \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X30_Y12_N19 +dffeas \z80_|interrupts_|DFFE_instIFF2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|DFFE_instIFF2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'h80C4; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & +// (!\z80_|decode_state_|DFFE_instNonRep~q )))) + + .dataa(\z80_|decode_state_|DFFE_instNonRep~q ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'hC500; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|pla_decode_|Equal62~3_combout ) # (\z80_|execute_|ctl_alu_op_low~19_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout ) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|pla_decode_|Equal69~0_combout ), + .datac(\z80_|pla_decode_|Equal62~3_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'hFFFD; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|execute_|ctl_pf_sel[0]~13_combout & (\z80_|execute_|ctl_pf_sel[0]~10_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # (!\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'h4C00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[1]~12 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[1]~12_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[1]~12 .lut_mask = 16'h0031; +defparam \z80_|execute_|ctl_pf_sel[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~11 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~11_combout = (\z80_|nM1_int~2_combout & (((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|pla_decode_|Equal62~3_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datac(\z80_|pla_decode_|Equal62~3_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~11 .lut_mask = 16'hFD00; +defparam \z80_|execute_|ctl_pf_sel[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (!\z80_|execute_|ctl_pf_sel[1]~12_combout & (((\z80_|execute_|ctl_pf_sel[0]~11_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~10_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~13_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~13_combout ), + .datab(\z80_|execute_|ctl_pf_sel[1]~12_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~11_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h3133; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout $ (((\z80_|execute_|ctl_alu_core_R~combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ))))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h6500; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N17 +dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|alu_parity_out~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N2 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( +// Equation(s): +// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'h6996; +defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N16 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( +// Equation(s): +// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .datad(\z80_|alu_|alu_parity_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out .lut_mask = 16'h03FC; +defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout & \z80_|alu_|alu_parity_out~combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .datad(\z80_|alu_|alu_parity_out~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'hFEFA; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~10_combout & (((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[2]~30_combout )))) # (!\z80_|execute_|ctl_flags_pf_we~10_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_pf~q )) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datab(\z80_|execute_|ctl_flags_bus~combout ), + .datac(\z80_|alu_control_|db[2]~30_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'hC0AA; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout & \z80_|execute_|ctl_flags_alu~19_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .datac(\z80_|execute_|ctl_flags_alu~19_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFF80; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y11_N25 +dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y9_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal13~0_combout ) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hF7FF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[2]~14_combout & (!\z80_|alu_|db_low[0]~27_combout & (!\z80_|alu_|db_low[3]~26_combout & !\z80_|alu_|db_low[1]~20_combout ))) + + .dataa(\z80_|alu_|db_low[2]~14_combout ), + .datab(\z80_|alu_|db_low[0]~27_combout ), + .datac(\z80_|alu_|db_low[3]~26_combout ), + .datad(\z80_|alu_|db_low[1]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_high[1]~19_combout & (!\z80_|alu_|db_high[0]~25_combout & (!\z80_|alu_|db_high[2]~13_combout & !\z80_|alu_|db_high[3]~7_combout ))) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|alu_|db_high[0]~25_combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|alu_|db_high[3]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N26 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout = (\z80_|execute_|ctl_flags_alu~19_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_alu~19_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hC000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ) # ((\z80_|alu_control_|db[6]~23_combout & \z80_|execute_|ctl_flags_bus~combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .datab(\z80_|alu_control_|db[6]~23_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hA8A0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N25 +dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N2 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ) # ((\z80_|alu_control_|sel[1]~0_combout )))) # (!\z80_|ir_|opcode [4] & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & +// !\z80_|alu_control_|sel[1]~0_combout )))) + + .dataa(\z80_|alu_flags_|flags_cf~combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|alu_control_|sel[1]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hF0AC; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N16 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) + + .dataa(\z80_|alu_control_|sel[1]~0_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hF588; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N8 +cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( +// Equation(s): +// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((\z80_|alu_control_|flags_cond_true~q )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|flags_cond_true~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hD872; +defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N9 +dffeas \z80_|alu_control_|flags_cond_true ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_control_|flags_cond_true~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|flags_cond_true~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; +defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|execute_|ctl_reg_sys_we_lo~1_combout ) # (\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~1_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hA8FF; +defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y10_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~combout = (((\z80_|execute_|ctl_reg_sys_we~2_combout ) # (\z80_|reg_control_|reg_sys_we_hi~0_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~35_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~35_combout ), + .datac(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF7; +defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~44_combout ) # ((\z80_|reg_control_|reg_sw_4d_hi~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datac(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~7 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~7_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (\z80_|reg_file_|b2v_latch_ir_hi|latch [3] & ((\z80_|reg_file_|gdfx_temp1[3]~39_combout ) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout & (((\z80_|reg_file_|gdfx_temp1[3]~39_combout )) # (!\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .datad(\z80_|reg_file_|gdfx_temp1[3]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~7 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|db_hi_as[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~8 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~8_combout = (\z80_|reg_file_|db_hi_as[3]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[3]~7_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~8 .lut_mask = 16'hAA22; +defparam \z80_|reg_file_|db_hi_as[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~9 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~9_combout = ((\z80_|reg_file_|db_hi_as[3]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datac(\z80_|reg_file_|db_hi_as[3]~8_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~9 .lut_mask = 16'hD5F5; +defparam \z80_|reg_file_|db_hi_as[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N12 +cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( +// Equation(s): +// \z80_|address_latch_|abusz [11] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[3]~9_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[3]~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N13 +dffeas \z80_|address_latch_|Q[11] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [11]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|Q [11] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [11]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N14 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [11]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h5505; +defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N6 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~2_combout = (\z80_|execute_|fIORead~3_combout ) # (((\z80_|execute_|fMRead~36_combout ) # (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )) + + .dataa(\z80_|execute_|fIORead~3_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datac(\z80_|execute_|fMRead~36_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFBFF; +defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N12 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|pin_control_|bus_ab_pin_we~2_combout & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) # (!\z80_|pin_control_|bus_ab_pin_we~2_combout & +// (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|pin_control_|bus_ab_pin_we~2_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h22F2; +defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N15 +dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .asdata(\z80_|address_latch_|Q [11]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y4_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( +// Equation(s): +// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [11]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[11]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N4 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [10])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [10]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N5 +dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .asdata(\z80_|address_latch_|Q [10]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[10]~20 ( +// Equation(s): +// \z80_|address_pins_|abus[10]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [10]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[10]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[10]~20 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[10]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~19 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|extended~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~19 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|keys[7][1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~48 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~48_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~48_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~48 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[7][4]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~51 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~51_combout = (\ula_|zx_keyboard_|keys[3][2]~50_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[3][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][2]~50_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .datac(\ula_|zx_keyboard_|keys[3][2]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~51 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][2]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N7 dffeas \ula_|zx_keyboard_|keys[3][2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][2]~54_combout ), + .d(\ula_|zx_keyboard_|keys[3][2]~51_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49332,80 +39425,221 @@ defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N8 -cycloneive_lcell_comb \D[2]~36 ( +// Location: LCCOMB_X23_Y9_N26 +cycloneive_lcell_comb \D[2]~43 ( // Equation(s): -// \D[2]~36_combout = (\ula_|zx_keyboard_|keys[2][2]~q & (\z80_|address_pins_|abus[10]~24_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) # (!\ula_|zx_keyboard_|keys[2][2]~q & -// (((\z80_|address_pins_|abus[11]~19_combout )) # (!\ula_|zx_keyboard_|keys[3][2]~q ))) +// \D[2]~43_combout = (\ula_|zx_keyboard_|keys[2][2]~q & (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) # (!\ula_|zx_keyboard_|keys[2][2]~q & +// ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][2]~q )))) .dataa(\ula_|zx_keyboard_|keys[2][2]~q ), - .datab(\ula_|zx_keyboard_|keys[3][2]~q ), - .datac(\z80_|address_pins_|abus[10]~24_combout ), - .datad(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\z80_|address_pins_|abus[11]~19_combout ), + .datac(\z80_|address_pins_|abus[10]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[3][2]~q ), .cin(gnd), - .combout(\D[2]~36_combout ), + .combout(\D[2]~43_combout ), .cout()); // synopsys translate_off -defparam \D[2]~36 .lut_mask = 16'hF531; -defparam \D[2]~36 .sum_lutc_input = "datac"; +defparam \D[2]~43 .lut_mask = 16'hC4F5; +defparam \D[2]~43 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y19_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~68 ( +// Location: LCCOMB_X20_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~68_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [1]))) +// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|WideOr17~0_combout )) .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|WideOr17~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .combout(\ula_|zx_keyboard_|shifted~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~68 .lut_mask = 16'h0180; -defparam \ula_|zx_keyboard_|keys[6][2]~68 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y20_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~69 ( +// Location: LCCOMB_X19_Y10_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~11 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~69_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~68_combout )) +// \ula_|zx_keyboard_|keys[0][0]~11_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|zx_keyboard_|Equal0~1_combout )) - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~11 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|keys[0][0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & (!\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h000A; +defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~0_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # +// (!\ula_|zx_keyboard_|shifted~2_combout & (((\ula_|zx_keyboard_|shifted~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|shifted~2_combout ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|shifted~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y8_N31 +dffeas \ula_|zx_keyboard_|shifted ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|shifted~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|shifted~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|shifted .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~62 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~62_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~62_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~62 .lut_mask = 16'hF0FC; +defparam \ula_|zx_keyboard_|keys[5][0]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~32 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~32_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|zx_keyboard_|extended~q & \ula_|zx_keyboard_|keys[0][0]~11_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~32 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~63 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~63_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~63_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~63 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[6][2]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~64 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~64_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~63_combout ) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .datad(\ula_|zx_keyboard_|keys[6][2]~63_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .combout(\ula_|zx_keyboard_|keys[6][2]~64_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~69 .lut_mask = 16'h2200; -defparam \ula_|zx_keyboard_|keys[6][2]~69 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][2]~64 .lut_mask = 16'h5500; +defparam \ula_|zx_keyboard_|keys[6][2]~64 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~70 ( +// Location: LCCOMB_X21_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~65 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~70_combout = (\ula_|zx_keyboard_|keys[6][2]~69_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~69_combout & ((\ula_|zx_keyboard_|keys[6][2]~q ))) +// \ula_|zx_keyboard_|keys[6][2]~65_combout = (\ula_|zx_keyboard_|keys[6][1]~32_combout & ((\ula_|zx_keyboard_|keys[6][2]~64_combout & (!\ula_|zx_keyboard_|keys[5][0]~62_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~64_combout & +// ((\ula_|zx_keyboard_|keys[6][2]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~32_combout & (((\ula_|zx_keyboard_|keys[6][2]~q )))) - .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .datab(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .dataa(\ula_|zx_keyboard_|keys[5][0]~62_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~32_combout ), .datac(\ula_|zx_keyboard_|keys[6][2]~q ), - .datad(gnd), + .datad(\ula_|zx_keyboard_|keys[6][2]~64_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~70_combout ), + .combout(\ula_|zx_keyboard_|keys[6][2]~65_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~70 .lut_mask = 16'h7474; -defparam \ula_|zx_keyboard_|keys[6][2]~70 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][2]~65 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[6][2]~65 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y20_N1 +// Location: FF_X21_Y9_N5 dffeas \ula_|zx_keyboard_|keys[6][2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][2]~70_combout ), + .d(\ula_|zx_keyboard_|keys[6][2]~65_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49421,112 +39655,253 @@ defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( +// Location: LCCOMB_X31_Y16_N18 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~61_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) +// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) + + .dataa(\z80_|address_latch_|abusz [15]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N19 +dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .asdata(\z80_|address_latch_|Q [15]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[15]~21 ( +// Equation(s): +// \z80_|address_pins_|abus[15]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .combout(\z80_|address_pins_|abus[15]~21_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[15]~21 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[15]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~62 ( +// Location: LCCOMB_X31_Y16_N22 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~62_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[7][2]~61_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0]))) +// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [14])) + + .dataa(\z80_|address_latch_|abusz [14]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N23 +dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .asdata(\z80_|address_latch_|Q [14]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N14 +cycloneive_lcell_comb \z80_|address_pins_|abus[14]~22 ( +// Equation(s): +// \z80_|address_pins_|abus[14]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[14]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[14]~22 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[14]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~57 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~57_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~57_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~57 .lut_mask = 16'h3030; +defparam \ula_|zx_keyboard_|keys[7][2]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~58 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~58_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~57_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[7][2]~57_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~58_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~58 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[7][2]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~59 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~59_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~59 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|keys[5][4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~28 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~28_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5])) .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(gnd), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~62_combout ), + .combout(\ula_|zx_keyboard_|keys[7][2]~28_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~62 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[7][2]~62 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[7][2]~28 .lut_mask = 16'h0404; +defparam \ula_|zx_keyboard_|keys[7][2]~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~64 ( +// Location: LCCOMB_X21_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~60 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~64_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~62_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~63_combout & \ula_|zx_keyboard_|keys[7][2]~32_combout )))) +// \ula_|zx_keyboard_|keys[7][2]~60_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~58_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~59_combout & \ula_|zx_keyboard_|keys[7][2]~28_combout )))) - .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~32_combout ), + .dataa(\ula_|zx_keyboard_|keys[7][2]~58_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~59_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .combout(\ula_|zx_keyboard_|keys[7][2]~60_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~64 .lut_mask = 16'hC8C0; -defparam \ula_|zx_keyboard_|keys[7][2]~64 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[7][2]~60 .lut_mask = 16'hE0A0; +defparam \ula_|zx_keyboard_|keys[7][2]~60 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~65 ( +// Location: LCCOMB_X20_Y8_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~56 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~65_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~15_combout & \ula_|zx_keyboard_|keys[7][2]~64_combout ))) +// \ula_|zx_keyboard_|keys[7][2]~56_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[0][0]~11_combout & !\ula_|zx_keyboard_|extended~q )) .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~65_combout ), + .combout(\ula_|zx_keyboard_|keys[7][2]~56_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~65 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|keys[7][2]~65 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[7][2]~56 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|keys[7][2]~56 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y18_N22 +// Location: LCCOMB_X23_Y8_N28 cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( // Equation(s): -// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [5])) +// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q )) - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|released~q ), + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), .cin(gnd), .combout(\ula_|zx_keyboard_|Selector13~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hFF22; +defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hF5F0; defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~66 ( +// Location: LCCOMB_X23_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~66_combout = (\ula_|zx_keyboard_|keys[7][2]~65_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~65_combout & (\ula_|zx_keyboard_|keys[7][2]~q )) +// \ula_|zx_keyboard_|keys[7][2]~61_combout = (\ula_|zx_keyboard_|keys[7][2]~60_combout & ((\ula_|zx_keyboard_|keys[7][2]~56_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~56_combout & +// (\ula_|zx_keyboard_|keys[7][2]~q )))) # (!\ula_|zx_keyboard_|keys[7][2]~60_combout & (((\ula_|zx_keyboard_|keys[7][2]~q )))) - .dataa(\ula_|zx_keyboard_|keys[7][2]~65_combout ), - .datab(gnd), + .dataa(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .datab(\ula_|zx_keyboard_|keys[7][2]~56_combout ), .datac(\ula_|zx_keyboard_|keys[7][2]~q ), .datad(\ula_|zx_keyboard_|Selector13~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~66_combout ), + .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~66 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[7][2]~66 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y21_N13 +// Location: FF_X23_Y8_N1 dffeas \ula_|zx_keyboard_|keys[7][2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][2]~66_combout ), + .d(\ula_|zx_keyboard_|keys[7][2]~61_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -49542,173 +39917,1135 @@ defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N0 -cycloneive_lcell_comb \D[2]~38 ( +// Location: LCCOMB_X23_Y9_N10 +cycloneive_lcell_comb \D[2]~44 ( // Equation(s): -// \D[2]~38_combout = (\z80_|address_pins_|abus[15]~22_combout & (((\z80_|address_pins_|abus[14]~23_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~q ))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][2]~q & -// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) +// \D[2]~44_combout = (\ula_|zx_keyboard_|keys[6][2]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][2]~q )))) # (!\ula_|zx_keyboard_|keys[6][2]~q & +// ((\z80_|address_pins_|abus[15]~21_combout ) # ((!\ula_|zx_keyboard_|keys[7][2]~q )))) - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ula_|zx_keyboard_|keys[6][2]~q ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), + .dataa(\ula_|zx_keyboard_|keys[6][2]~q ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), .datad(\ula_|zx_keyboard_|keys[7][2]~q ), .cin(gnd), - .combout(\D[2]~38_combout ), + .combout(\D[2]~44_combout ), .cout()); // synopsys translate_off -defparam \D[2]~38 .lut_mask = 16'hA2F3; -defparam \D[2]~38 .sum_lutc_input = "datac"; +defparam \D[2]~44 .lut_mask = 16'hC4F5; +defparam \D[2]~44 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y20_N14 -cycloneive_lcell_comb \D[2]~39 ( +// Location: LCCOMB_X31_Y16_N24 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( // Equation(s): -// \D[2]~39_combout = (\D[2]~35_combout & (\D[2]~37_combout & (\D[2]~36_combout & \D[2]~38_combout ))) +// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [12])) - .dataa(\D[2]~35_combout ), - .datab(\D[2]~37_combout ), - .datac(\D[2]~36_combout ), - .datad(\D[2]~38_combout ), + .dataa(\z80_|address_latch_|abusz [12]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), .cin(gnd), - .combout(\D[2]~39_combout ), + .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), .cout()); // synopsys translate_off -defparam \D[2]~39 .lut_mask = 16'h8000; -defparam \D[2]~39 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N14 -cycloneive_lcell_comb \D[2]~104 ( +// Location: FF_X31_Y16_N25 +dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .asdata(\z80_|address_latch_|Q [12]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[12]~24 ( // Equation(s): -// \D[2]~104_combout = ((\z80_|address_pins_|DFFE_apin_latch [0]) # (\D[2]~39_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|address_pins_|abus[12]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [12]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[12]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[12]~24 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[12]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N0 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [13]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datab(\z80_|address_latch_|abusz [13]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N1 +dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .asdata(\z80_|address_latch_|Q [13]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~29 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~29_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[7][2]~28_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~29_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~29 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[5][2]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~54 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~54_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~54_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~54 .lut_mask = 16'h0C0C; +defparam \ula_|zx_keyboard_|keys[5][2]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~55 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~55_combout = (\ula_|zx_keyboard_|keys[5][2]~29_combout & ((\ula_|zx_keyboard_|keys[5][2]~54_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][2]~54_combout & ((\ula_|zx_keyboard_|keys[5][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~29_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~29_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[5][2]~q ), + .datad(\ula_|zx_keyboard_|keys[5][2]~54_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~55_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~55 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][2]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y10_N31 +dffeas \ula_|zx_keyboard_|keys[5][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][2]~55_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~1_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # ((!\ula_|zx_keyboard_|keys[5][2]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|zx_keyboard_|keys[5][2]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hCFFF; +defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~127 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~127_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|Equal0~1_combout ))) + + .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~127_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~127 .lut_mask = 16'h0008; +defparam \ula_|zx_keyboard_|keys[3][4]~127 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~66 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~66_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~66_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~66 .lut_mask = 16'h0240; +defparam \ula_|zx_keyboard_|keys[4][2]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~128 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~128_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[4][2]~66_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|keys[4][2]~66_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~128_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~128 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[4][2]~128 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~67 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~67_combout = (\ula_|zx_keyboard_|keys[3][4]~127_combout & ((\ula_|zx_keyboard_|keys[4][2]~128_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][2]~128_combout & ((\ula_|zx_keyboard_|keys[4][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~127_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][4]~127_combout ), + .datac(\ula_|zx_keyboard_|keys[4][2]~q ), + .datad(\ula_|zx_keyboard_|keys[4][2]~128_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~67_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~67 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][2]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N23 +dffeas \ula_|zx_keyboard_|keys[4][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][2]~67_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N18 +cycloneive_lcell_comb \D[2]~45 ( +// Equation(s): +// \D[2]~45_combout = (\D[2]~44_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\D[2]~44_combout ), + .datab(\z80_|address_pins_|abus[12]~24_combout ), + .datac(\ula_|zx_keyboard_|key_row~1_combout ), + .datad(\ula_|zx_keyboard_|keys[4][2]~q ), + .cin(gnd), + .combout(\D[2]~45_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~45 .lut_mask = 16'h80A0; +defparam \D[2]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N26 +cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( +// Equation(s): +// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [0]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~43 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~43_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~43_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~43 .lut_mask = 16'h0808; +defparam \ula_|zx_keyboard_|keys[6][4]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~44 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~44_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[7][1]~19_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~44_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~44 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][4]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~45 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~45_combout = (\ula_|zx_keyboard_|keys[6][4]~43_combout & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~44_combout )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[6][4]~43_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[6][4]~44_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~45_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~45 .lut_mask = 16'h0C00; +defparam \ula_|zx_keyboard_|keys[1][2]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~46 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~46_combout = (\ula_|zx_keyboard_|keys[1][2]~45_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][2]~45_combout & ((\ula_|zx_keyboard_|keys[1][2]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[1][2]~q ), + .datad(\ula_|zx_keyboard_|keys[1][2]~45_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~46_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~46 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[1][2]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y9_N15 +dffeas \ula_|zx_keyboard_|keys[1][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][2]~46_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~47 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~47_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~47 .lut_mask = 16'h0055; +defparam \ula_|zx_keyboard_|keys[0][2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~49 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~49_combout = (\ula_|zx_keyboard_|keys[0][2]~47_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[0][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[0][2]~47_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[0][2]~47_combout ), + .datac(\ula_|zx_keyboard_|keys[0][2]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~49_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~49 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[0][2]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N13 +dffeas \ula_|zx_keyboard_|keys[0][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][2]~49_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N8 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [9])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [9]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N9 +dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .asdata(\z80_|address_latch_|Q [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N28 +cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( +// Equation(s): +// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [9]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[9]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N24 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [8]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [8]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y16_N25 +dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .asdata(\z80_|address_latch_|Q [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N24 +cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( +// Equation(s): +// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [8]), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[8]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hCCFF; +defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N20 +cycloneive_lcell_comb \D[2]~42 ( +// Equation(s): +// \D[2]~42_combout = (\ula_|zx_keyboard_|keys[1][2]~q & (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][2]~q )))) # (!\ula_|zx_keyboard_|keys[1][2]~q & +// (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[1][2]~q ), + .datab(\ula_|zx_keyboard_|keys[0][2]~q ), + .datac(\z80_|address_pins_|abus[9]~17_combout ), + .datad(\z80_|address_pins_|abus[8]~18_combout ), + .cin(gnd), + .combout(\D[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~42 .lut_mask = 16'hF531; +defparam \D[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N24 +cycloneive_lcell_comb \D[2]~46 ( +// Equation(s): +// \D[2]~46_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[2]~43_combout & (\D[2]~45_combout & \D[2]~42_combout ))) + + .dataa(\D[2]~43_combout ), + .datab(\D[2]~45_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[2]~42_combout ), + .cin(gnd), + .combout(\D[2]~46_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~46 .lut_mask = 16'hF8F0; +defparam \D[2]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y14_N3 +dffeas \z80_|memory_ifc_|wait_iorqinta ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|clk_delay_|DFF_inst5~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorqinta~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N0 +cycloneive_lcell_comb \z80_|memory_ifc_|DFFE_intr_ff3~feeder ( +// Equation(s): +// \z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout = \z80_|memory_ifc_|wait_iorqinta~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|wait_iorqinta~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_intr_ff3~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|DFFE_intr_ff3~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y14_N1 +dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|DFFE_intr_ff3~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N8 +cycloneive_lcell_comb \z80_|control_pins_|pin_nIORQ~1 ( +// Equation(s): +// \z80_|control_pins_|pin_nIORQ~1_combout = ((!\z80_|memory_ifc_|iorq~0_combout & (!\z80_|memory_ifc_|DFFE_intr_ff3~q & !\z80_|memory_ifc_|wait_iorqinta~q ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|memory_ifc_|iorq~0_combout ), + .datab(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|memory_ifc_|wait_iorqinta~q ), + .cin(gnd), + .combout(\z80_|control_pins_|pin_nIORQ~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|control_pins_|pin_nIORQ~1 .lut_mask = 16'h0F1F; +defparam \z80_|control_pins_|pin_nIORQ~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N8 +cycloneive_lcell_comb \Equal2~0 ( +// Equation(s): +// \Equal2~0_combout = (\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|control_pins_|pin_nIORQ~1_combout ))) + + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), + .cin(gnd), + .combout(\Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~0 .lut_mask = 16'h0020; +defparam \Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N30 +cycloneive_lcell_comb \z80_|address_pins_|abus[13]~23 ( +// Equation(s): +// \z80_|address_pins_|abus[13]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[13]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[13]~23 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[13]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N18 +cycloneive_lcell_comb \ExtRamWE~0 ( +// Equation(s): +// \ExtRamWE~0_combout = (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|control_pins_|pin_nIORQ~1_combout ))) + + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), + .cin(gnd), + .combout(\ExtRamWE~0_combout ), + .cout()); +// synopsys translate_off +defparam \ExtRamWE~0 .lut_mask = 16'h4000; +defparam \ExtRamWE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N6 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h2000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y8_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|address_pins_|DFFE_apin_latch [14])) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h5000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N28 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [1]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .datab(\z80_|address_latch_|abusz [1]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N29 +dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .asdata(\z80_|address_latch_|Q [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N16 +cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( +// Equation(s): +// \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hF5F5; +defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N10 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) + + .dataa(\z80_|address_latch_|abusz [2]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hEE22; +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N11 +dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .asdata(\z80_|address_latch_|Q [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N20 +cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( +// Equation(s): +// \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [2]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[2]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hAAFF; +defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N28 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [3]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [3]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y12_N29 +dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .asdata(\z80_|address_latch_|Q [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( +// Equation(s): +// \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [3]), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[3]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hCCFF; +defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N12 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [4]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .datab(\z80_|address_latch_|abusz [4]), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hAACC; +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N13 +dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .asdata(\z80_|address_latch_|Q [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N10 +cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( +// Equation(s): +// \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) .dataa(gnd), .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(\D[2]~39_combout ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [4]), .cin(gnd), - .combout(\D[2]~104_combout ), + .combout(\z80_|address_pins_|abus[4]~28_combout ), .cout()); // synopsys translate_off -defparam \D[2]~104 .lut_mask = 16'hFFF3; -defparam \D[2]~104 .sum_lutc_input = "datac"; +defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF33; +defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: LCCOMB_X30_Y14_N8 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) + + .dataa(\z80_|address_latch_|abusz [5]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE22; +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N9 +dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .asdata(\z80_|address_latch_|Q [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), - .portbdataout()); + .q(\z80_|address_pins_|DFFE_apin_latch [5]), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y12_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: LCCOMB_X25_Y12_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( +// Equation(s): +// \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [5]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[5]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N18 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [6])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [6]))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [6]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hBB88; +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y14_N19 +dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .asdata(\z80_|address_latch_|Q [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); + .q(\z80_|address_pins_|DFFE_apin_latch [6]), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y9_N0 +// Location: LCCOMB_X25_Y12_N10 +cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( +// Equation(s): +// \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [6]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|address_pins_|abus[6]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hF0FF; +defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N26 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) + + .dataa(\z80_|address_latch_|abusz [7]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y12_N27 +dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .asdata(\z80_|address_latch_|Q [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N12 +cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( +// Equation(s): +// \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [7]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[7]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hF5F5; +defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y5_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), @@ -49724,8 +41061,8 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -49765,7 +41102,79 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y12_N0 +// Location: FF_X24_Y19_N11 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[13]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y19_N3 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[14]~22_combout & (\ExtRamWE~0_combout & !\z80_|address_pins_|abus[13]~23_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ExtRamWE~0_combout ), + .datad(\z80_|address_pins_|abus[13]~23_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0020; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y8_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h0050; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y8_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), @@ -49781,8 +41190,8 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -49822,60 +41231,58 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N8 -cycloneive_lcell_comb \D[2]~43 ( +// Location: LCCOMB_X21_Y13_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( // Equation(s): -// \D[2]~43_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) +// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & (!\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\ExtRamWE~0_combout ), .cin(gnd), - .combout(\D[2]~43_combout ), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .cout()); // synopsys translate_off -defparam \D[2]~43 .lut_mask = 16'hB9A8; -defparam \D[2]~43 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h0800; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N6 -cycloneive_lcell_comb \D[2]~44 ( +// Location: LCCOMB_X25_Y8_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( // Equation(s): -// \D[2]~44_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~43_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout )) # (!\D[2]~43_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~43_combout )))) +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])) - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\D[2]~43_combout ), + .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), .cin(gnd), - .combout(\D[2]~44_combout ), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), .cout()); // synopsys translate_off -defparam \D[2]~44 .lut_mask = 16'hBBC0; -defparam \D[2]~44 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00A0; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y17_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(vcc), +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -49884,39 +41291,1006 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y28_N0 +// Location: FF_X25_Y19_N15 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y19_N19 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y8_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hAF0F; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y3_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N10 +cycloneive_lcell_comb \D[2]~50 ( +// Equation(s): +// \D[2]~50_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), + .cin(gnd), + .combout(\D[2]~50_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~50 .lut_mask = 16'hF838; +defparam \D[2]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N26 +cycloneive_lcell_comb \D[2]~51 ( +// Equation(s): +// \D[2]~51_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~50_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~50_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )) # (!\D[2]~50_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\D[2]~50_combout ), + .cin(gnd), + .combout(\D[2]~51_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~51 .lut_mask = 16'hEE30; +defparam \D[2]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N24 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (!\z80_|address_pins_|abus[15]~21_combout & (!\z80_|address_pins_|abus[13]~23_combout & (\z80_|address_pins_|abus[14]~22_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h1000; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G15 +cycloneive_clkctrl \CLOCK_50~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\CLOCK_50~inputclkctrl_outclk )); +// synopsys translate_off +defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; +defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N30 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N8 +cycloneive_lcell_comb \ula_|video_|vram_address~0 ( +// Equation(s): +// \ula_|video_|vram_address~0_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|vram_address~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address~0 .lut_mask = 16'h1040; +defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N25 +dffeas \ula_|video_|vram_address[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N30 +cycloneive_lcell_comb \ula_|video_|vram_address[1]~feeder ( +// Equation(s): +// \ula_|video_|vram_address[1]~feeder_combout = \ula_|video_|vga_hc [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [5]), + .cin(gnd), + .combout(\ula_|video_|vram_address[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vram_address[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N31 +dffeas \ula_|video_|vram_address[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N4 +cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( +// Equation(s): +// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|video_|vram_address[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; +defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N5 +dffeas \ula_|video_|vram_address[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[2]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N22 +cycloneive_lcell_comb \ula_|video_|Add3~0 ( +// Equation(s): +// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N23 +dffeas \ula_|video_|vram_address[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N16 +cycloneive_lcell_comb \ula_|video_|Add3~1 ( +// Equation(s): +// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) + + .dataa(\ula_|video_|vga_hc [6]), + .datab(\ula_|video_|vga_hc [7]), + .datac(gnd), + .datad(\ula_|video_|vga_hc [8]), + .cin(gnd), + .combout(\ula_|video_|Add3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~1 .lut_mask = 16'h8877; +defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N17 +dffeas \ula_|video_|vram_address[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N8 +cycloneive_lcell_comb \ula_|video_|Add4~0 ( +// Equation(s): +// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) +// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add4~0_combout ), + .cout(\ula_|video_|Add4~1 )); +// synopsys translate_off +defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; +defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N10 +cycloneive_lcell_comb \ula_|video_|Add4~2 ( +// Equation(s): +// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) +// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) + + .dataa(\ula_|video_|vga_vc [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~1 ), + .combout(\ula_|video_|Add4~2_combout ), + .cout(\ula_|video_|Add4~3 )); +// synopsys translate_off +defparam \ula_|video_|Add4~2 .lut_mask = 16'hA505; +defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N12 +cycloneive_lcell_comb \ula_|video_|Add4~4 ( +// Equation(s): +// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) +// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) + + .dataa(\ula_|video_|vga_vc [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~3 ), + .combout(\ula_|video_|Add4~4_combout ), + .cout(\ula_|video_|Add4~5 )); +// synopsys translate_off +defparam \ula_|video_|Add4~4 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N14 +cycloneive_lcell_comb \ula_|video_|Add4~6 ( +// Equation(s): +// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) +// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [4]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~5 ), + .combout(\ula_|video_|Add4~6_combout ), + .cout(\ula_|video_|Add4~7 )); +// synopsys translate_off +defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y29_N15 +dffeas \ula_|video_|vram_address[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N16 +cycloneive_lcell_comb \ula_|video_|Add4~8 ( +// Equation(s): +// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) +// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) + + .dataa(\ula_|video_|vga_vc [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~7 ), + .combout(\ula_|video_|Add4~8_combout ), + .cout(\ula_|video_|Add4~9 )); +// synopsys translate_off +defparam \ula_|video_|Add4~8 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y29_N17 +dffeas \ula_|video_|vram_address[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N18 +cycloneive_lcell_comb \ula_|video_|Add4~10 ( +// Equation(s): +// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) +// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [6]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~9 ), + .combout(\ula_|video_|Add4~10_combout ), + .cout(\ula_|video_|Add4~11 )); +// synopsys translate_off +defparam \ula_|video_|Add4~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y29_N19 +dffeas \ula_|video_|vram_address[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N20 +cycloneive_lcell_comb \ula_|video_|Add4~12 ( +// Equation(s): +// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) +// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~11 ), + .combout(\ula_|video_|Add4~12_combout ), + .cout(\ula_|video_|Add4~13 )); +// synopsys translate_off +defparam \ula_|video_|Add4~12 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N28 +cycloneive_lcell_comb \ula_|video_|Selector6~0 ( +// Equation(s): +// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~12_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~0_combout )) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(gnd), + .datac(\ula_|video_|Add4~0_combout ), + .datad(\ula_|video_|Add4~12_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector6~0 .lut_mask = 16'hFA50; +defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N2 +cycloneive_lcell_comb \ula_|video_|vram_address[8]~1 ( +// Equation(s): +// \ula_|video_|vram_address[8]~1_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|vram_address[8]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[8]~1 .lut_mask = 16'h1040; +defparam \ula_|video_|vram_address[8]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y29_N29 +dffeas \ula_|video_|vram_address[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[8]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N22 +cycloneive_lcell_comb \ula_|video_|Add4~14 ( +// Equation(s): +// \ula_|video_|Add4~14_combout = \ula_|video_|vga_vc [8] $ (!\ula_|video_|Add4~13 ) + + .dataa(\ula_|video_|vga_vc [8]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|video_|Add4~13 ), + .combout(\ula_|video_|Add4~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add4~14 .lut_mask = 16'hA5A5; +defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N6 +cycloneive_lcell_comb \ula_|video_|Selector5~0 ( +// Equation(s): +// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(gnd), + .datac(\ula_|video_|Add4~14_combout ), + .datad(\ula_|video_|Add4~2_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector5~0 .lut_mask = 16'hF5A0; +defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y29_N7 +dffeas \ula_|video_|vram_address[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[8]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N28 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( +// Equation(s): +// \ula_|video_|vram_address[10]~2_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h1040; +defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y29_N18 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( +// Equation(s): +// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) + + .dataa(\ula_|video_|vram_address[10]~2_combout ), + .datab(\ula_|video_|Add4~4_combout ), + .datac(\ula_|video_|vram_address [10]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'hD850; +defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y29_N19 +dffeas \ula_|video_|vram_address[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[10]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N24 +cycloneive_lcell_comb \ula_|video_|Selector3~0 ( +// Equation(s): +// \ula_|video_|Selector3~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|Add4~12_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFF0; +defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y29_N25 +dffeas \ula_|video_|vram_address[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[8]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y29_N2 +cycloneive_lcell_comb \ula_|video_|Selector2~0 ( +// Equation(s): +// \ula_|video_|Selector2~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~14_combout ) + + .dataa(\ula_|video_|vga_hc [2]), + .datab(gnd), + .datac(\ula_|video_|Add4~14_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|video_|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFAFA; +defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y29_N3 +dffeas \ula_|video_|vram_address[12] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[8]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[12] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X22_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N28 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~23_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~23_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y19_N29 +dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N20 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|address_reg_a [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y19_N21 +dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N0 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\z80_|address_pins_|abus[14]~22_combout & (!\z80_|address_pins_|abus[15]~21_combout & (\z80_|address_pins_|abus[13]~23_combout & \ExtRamWE~0_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\z80_|address_pins_|abus[13]~23_combout ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h2000; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y23_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), @@ -49926,14 +42300,14 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[2]~53_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -49989,97 +42363,83 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N12 -cycloneive_lcell_comb \D[2]~40 ( -// Equation(s): -// \D[2]~40_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .cin(gnd), - .combout(\D[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~40 .lut_mask = 16'hEA62; -defparam \D[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y31_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), +// Location: M9K_X33_Y20_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); // synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; // synopsys translate_on -// Location: M9K_X33_Y17_N0 +// Location: LCCOMB_X25_Y19_N22 +cycloneive_lcell_comb \D[2]~47 ( +// Equation(s): +// \D[2]~47_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\D[2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~47 .lut_mask = 16'hE6A2; +defparam \D[2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y32_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( .portawe(vcc), .portare(vcc), @@ -50089,14 +42449,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -50137,113 +42497,148 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048 defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N16 -cycloneive_lcell_comb \D[2]~41 ( +// Location: LCCOMB_X25_Y19_N24 +cycloneive_lcell_comb \D[2]~48 ( // Equation(s): -// \D[2]~41_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout $ (\D[2]~40_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout & ((!\D[2]~40_combout )))) +// \D[2]~48_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout $ ((\D[2]~47_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[2]~47_combout & +// \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\D[2]~40_combout ), + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\D[2]~47_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), .cin(gnd), - .combout(\D[2]~41_combout ), + .combout(\D[2]~48_combout ), .cout()); // synopsys translate_off -defparam \D[2]~41 .lut_mask = 16'h0AE4; -defparam \D[2]~41 .sum_lutc_input = "datac"; +defparam \D[2]~48 .lut_mask = 16'h4B48; +defparam \D[2]~48 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N30 -cycloneive_lcell_comb \D[2]~42 ( +// Location: LCCOMB_X25_Y19_N16 +cycloneive_lcell_comb \D[2]~49 ( // Equation(s): -// \D[2]~42_combout = (\D[2]~40_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout & !\D[2]~41_combout )))) # (!\D[2]~40_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~41_combout )))) +// \D[2]~49_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~47_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~47_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout & !\D[2]~48_combout )) # (!\D[2]~47_combout & ((\D[2]~48_combout ))))) - .dataa(\D[2]~40_combout ), + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datad(\D[2]~41_combout ), + .datac(\D[2]~47_combout ), + .datad(\D[2]~48_combout ), .cin(gnd), - .combout(\D[2]~42_combout ), + .combout(\D[2]~49_combout ), .cout()); // synopsys translate_off -defparam \D[2]~42 .lut_mask = 16'h99A8; -defparam \D[2]~42 .sum_lutc_input = "datac"; +defparam \D[2]~49 .lut_mask = 16'hC3E0; +defparam \D[2]~49 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N0 -cycloneive_lcell_comb \D[2]~105 ( +// Location: LCCOMB_X25_Y19_N6 +cycloneive_lcell_comb \D[2]~119 ( // Equation(s): -// \D[2]~105_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[2]~44_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[2]~42_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[2]~44_combout )))) +// \D[2]~119_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[2]~51_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[2]~49_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[2]~51_combout )))) - .dataa(\D[2]~44_combout ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[2]~42_combout ), + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\D[2]~51_combout ), + .datad(\D[2]~49_combout ), .cin(gnd), - .combout(\D[2]~105_combout ), + .combout(\D[2]~119_combout ), .cout()); // synopsys translate_off -defparam \D[2]~105 .lut_mask = 16'hBA8A; -defparam \D[2]~105 .sum_lutc_input = "datac"; +defparam \D[2]~119 .lut_mask = 16'hF4B0; +defparam \D[2]~119 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N28 -cycloneive_lcell_comb \D[2]~45 ( +// Location: LCCOMB_X24_Y19_N20 +cycloneive_lcell_comb \D[2]~52 ( // Equation(s): -// \D[2]~45_combout = ((\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout )))) # (!\Equal2~1_combout ) +// \D[2]~52_combout = ((\Equal2~0_combout & (\D[2]~46_combout )) # (!\Equal2~0_combout & ((\D[2]~119_combout )))) # (!\Equal2~1_combout ) - .dataa(\Equal2~0_combout ), + .dataa(\D[2]~46_combout ), .datab(\Equal2~1_combout ), - .datac(\D[2]~104_combout ), - .datad(\D[2]~105_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[2]~119_combout ), .cin(gnd), - .combout(\D[2]~45_combout ), + .combout(\D[2]~52_combout ), .cout()); // synopsys translate_off -defparam \D[2]~45 .lut_mask = 16'hF7B3; -defparam \D[2]~45 .sum_lutc_input = "datac"; +defparam \D[2]~52 .lut_mask = 16'hBFB3; +defparam \D[2]~52 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N30 -cycloneive_lcell_comb \D[2]~46 ( +// Location: LCCOMB_X24_Y19_N26 +cycloneive_lcell_comb \D[2]~53 ( // Equation(s): -// \D[2]~46_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [2] & ((\D[2]~45_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[2]~45_combout ) # (!\Equal2~1_combout )))) +// \D[2]~53_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [2] & \D[2]~52_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[2]~52_combout )) # (!\Equal2~1_combout ))) - .dataa(\z80_|data_pins_|dout [2]), + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[2]~45_combout ), + .datac(\z80_|data_pins_|dout [2]), + .datad(\D[2]~52_combout ), .cin(gnd), - .combout(\D[2]~46_combout ), + .combout(\D[2]~53_combout ), .cout()); // synopsys translate_off -defparam \D[2]~46 .lut_mask = 16'hAF03; -defparam \D[2]~46 .sum_lutc_input = "datac"; +defparam \D[2]~53 .lut_mask = 16'hF511; +defparam \D[2]~53 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N2 +// Location: LCCOMB_X29_Y12_N16 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[2]~13_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[2]~46_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[2]~46_combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|bus_control_|db[2]~13_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\D[2]~53_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|bus_control_|db[2]~13_combout & (\D[2]~53_combout +// & ((\z80_|pin_control_|bus_db_pin_re~combout )))) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\D[2]~46_combout ), - .datad(\z80_|bus_control_|db[2]~13_combout ), + .dataa(\z80_|bus_control_|db[2]~13_combout ), + .datab(\D[2]~53_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hECA0; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y12_N3 +// Location: LCCOMB_X32_Y12_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|execute_|fIORead~3_combout & ((\z80_|sequencer_|DFFE_T3_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|execute_|fIORead~3_combout & +// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|execute_|fIORead~3_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hA0EC; +defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N16 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .datac(\z80_|execute_|fMRead~36_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEC; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N17 dffeas \z80_|data_pins_|dout[2] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), @@ -50262,44 +42657,95 @@ defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N18 +// Location: LCCOMB_X29_Y12_N0 cycloneive_lcell_comb \z80_|bus_control_|db[2]~12 ( // Equation(s): -// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) +// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~30_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - .dataa(gnd), - .datab(\z80_|alu_control_|db[2]~29_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(\z80_|alu_control_|db[2]~30_combout ), + .datad(gnd), .cin(gnd), .combout(\z80_|bus_control_|db[2]~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hCF00; +defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hC4C4; defparam \z80_|bus_control_|db[2]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N12 +// Location: LCCOMB_X29_Y12_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( +// Equation(s): +// \z80_|bus_control_|db[0]~6_combout = ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (\z80_|execute_|ctl_bus_db_oe~combout )) # (!\z80_|execute_|ctl_bus_db_oe~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFFF5; +defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N10 cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( // Equation(s): // \z80_|bus_control_|db[2]~13_combout = ((\z80_|bus_control_|db[2]~12_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) .dataa(\z80_|data_pins_|dout [2]), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~combout ), - .datad(\z80_|bus_control_|db[2]~12_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|bus_control_|db[2]~12_combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[2]~13_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hBF33; +defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hB0FF; defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y12_N13 +// Location: LCCOMB_X29_Y13_N8 +cycloneive_lcell_comb \z80_|ir_|opcode[2]~feeder ( +// Equation(s): +// \z80_|ir_|opcode[2]~feeder_combout = \z80_|bus_control_|db[2]~13_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|bus_control_|db[2]~13_combout ), + .cin(gnd), + .combout(\z80_|ir_|opcode[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|ir_|opcode[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|ir_|opcode[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_ir_we~5_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hDDD5; +defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N9 dffeas \z80_|ir_|opcode[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[2]~13_combout ), + .d(\z80_|ir_|opcode[2]~feeder_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -50315,662 +42761,1129 @@ defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y16_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( +// Location: LCCOMB_X39_Y7_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( // Equation(s): -// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) +// \z80_|execute_|ctl_mRead~34_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .lut_mask = 16'h1500; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h2A22; +defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) + + .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hFF5F; +defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~13 ( +// Equation(s): +// \z80_|alu_control_|db[6]~13_combout = (\z80_|execute_|ctl_reg_out_lo~8_combout ) # ((\z80_|alu_control_|db[6]~12_combout ) # (\z80_|execute_|ctl_sw_1d~7_combout )) + + .dataa(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datab(\z80_|alu_control_|db[6]~12_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~13 .lut_mask = 16'hFEFE; +defparam \z80_|alu_control_|db[6]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( +// Equation(s): +// \z80_|alu_control_|db[6]~21_combout = (\z80_|alu_control_|out[6]~2_combout & (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_control_|out[6]~2_combout & +// (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_control_|out[6]~2_combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'hF3A2; +defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( +// Equation(s): +// \z80_|alu_control_|db[6]~22_combout = (\z80_|alu_control_|db[6]~21_combout & ((\z80_|alu_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) + + .dataa(\z80_|alu_control_|db[6]~21_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_|db[6]~22_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'hA2A2; +defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[6]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[6]~0_combout = (\z80_|reg_file_|gdfx_temp0[6]~80_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[6]~0 .lut_mask = 16'hCCEC; +defparam \z80_|reg_file_|db_lo_ds[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N2 +cycloneive_lcell_comb \z80_|sw1_|db_down[6]~1 ( +// Equation(s): +// \z80_|sw1_|db_down[6]~1_combout = ((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) + + .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), + .datab(gnd), + .datac(\z80_|bus_control_|db[6]~9_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[6]~1 .lut_mask = 16'h55F5; +defparam \z80_|sw1_|db_down[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N20 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~23 ( +// Equation(s): +// \z80_|alu_control_|db[6]~23_combout = ((\z80_|alu_control_|db[6]~22_combout & (\z80_|reg_file_|db_lo_ds[6]~0_combout & \z80_|sw1_|db_down[6]~1_combout ))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_control_|db[6]~13_combout ), + .datab(\z80_|alu_control_|db[6]~22_combout ), + .datac(\z80_|reg_file_|db_lo_ds[6]~0_combout ), + .datad(\z80_|sw1_|db_down[6]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~23 .lut_mask = 16'hD555; +defparam \z80_|alu_control_|db[6]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N22 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( +// Equation(s): +// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~23_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(gnd), + .datad(\z80_|alu_control_|db[6]~23_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hCC44; +defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y17_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: M9K_X22_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N2 +cycloneive_lcell_comb \D[6]~103 ( +// Equation(s): +// \D[6]~103_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .cin(gnd), + .combout(\D[6]~103_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~103 .lut_mask = 16'hEA4A; +defparam \D[6]~103 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N30 +cycloneive_lcell_comb \D[6]~104 ( +// Equation(s): +// \D[6]~104_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~103_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~103_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout )) # (!\D[6]~103_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datad(\D[6]~103_combout ), + .cin(gnd), + .combout(\D[6]~104_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~104 .lut_mask = 16'hEE30; +defparam \D[6]~104 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X22_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~115_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y30_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N14 +cycloneive_lcell_comb \D[6]~100 ( +// Equation(s): +// \D[6]~100_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~22_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\z80_|address_pins_|abus[14]~22_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\z80_|address_pins_|abus[14]~22_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .cin(gnd), + .combout(\D[6]~100_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~100 .lut_mask = 16'hBCB0; +defparam \D[6]~100 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y22_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N12 +cycloneive_lcell_comb \D[6]~101 ( +// Equation(s): +// \D[6]~101_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ ((\D[6]~100_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[6]~100_combout & +// \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datac(\D[6]~100_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .cin(gnd), + .combout(\D[6]~101_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~101 .lut_mask = 16'h2D28; +defparam \D[6]~101 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N0 +cycloneive_lcell_comb \D[6]~102 ( +// Equation(s): +// \D[6]~102_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~100_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~100_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~101_combout )) # (!\D[6]~100_combout & ((\D[6]~101_combout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[6]~100_combout ), + .datad(\D[6]~101_combout ), + .cin(gnd), + .combout(\D[6]~102_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~102 .lut_mask = 16'hC3E0; +defparam \D[6]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N8 +cycloneive_lcell_comb \D[6]~127 ( +// Equation(s): +// \D[6]~127_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[6]~104_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[6]~102_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[6]~104_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\D[6]~104_combout ), + .datad(\D[6]~102_combout ), + .cin(gnd), + .combout(\D[6]~127_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~127 .lut_mask = 16'hF4B0; +defparam \D[6]~127 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y34_N8 +cycloneive_io_ibuf \raw_loader_in~input ( + .i(raw_loader_in), + .ibar(gnd), + .o(\raw_loader_in~input_o )); +// synopsys translate_off +defparam \raw_loader_in~input .bus_hold = "false"; +defparam \raw_loader_in~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N28 +cycloneive_lcell_comb \D[6]~99 ( +// Equation(s): +// \D[6]~99_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\raw_loader_in~input_o ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~1_combout ), + .combout(\D[6]~99_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00F0; -defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; +defparam \D[6]~99 .lut_mask = 16'hFFCF; +defparam \D[6]~99 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( +// Location: LCCOMB_X23_Y19_N10 +cycloneive_lcell_comb \D[6]~114 ( // Equation(s): -// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) +// \D[6]~114_combout = ((\Equal2~0_combout & ((\D[6]~99_combout ))) # (!\Equal2~0_combout & (\D[6]~127_combout ))) # (!\Equal2~1_combout ) - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), + .dataa(\Equal2~0_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[6]~127_combout ), + .datad(\D[6]~99_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal43~0_combout ), + .combout(\D[6]~114_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; +defparam \D[6]~114 .lut_mask = 16'hFB73; +defparam \D[6]~114 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N24 -cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( +// Location: LCCOMB_X23_Y19_N12 +cycloneive_lcell_comb \D[6]~115 ( // Equation(s): -// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal43~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal36~0_combout ))) +// \D[6]~115_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [6] & \D[6]~114_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[6]~114_combout )) # (!\Equal2~1_combout ))) - .dataa(\z80_|pla_decode_|Equal43~0_combout ), - .datab(\z80_|pla_decode_|Equal3~2_combout ), - .datac(\z80_|pla_decode_|Equal79~0_combout ), - .datad(\z80_|pla_decode_|Equal36~0_combout ), + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\Equal2~1_combout ), + .datac(\z80_|data_pins_|dout [6]), + .datad(\D[6]~114_combout ), .cin(gnd), - .combout(\z80_|interrupts_|test1~2_combout ), + .combout(\D[6]~115_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; -defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; +defparam \D[6]~115 .lut_mask = 16'hF511; +defparam \D[6]~115 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y15_N26 -cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( +// Location: LCCOMB_X28_Y12_N14 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( // Equation(s): -// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|interrupts_|test1~2_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\D[6]~115_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[6]~9_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[6]~115_combout & +// (((\z80_|bus_control_|db[6]~9_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|interrupts_|test1~2_combout ), + .dataa(\D[6]~115_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|bus_control_|db[6]~9_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), .cin(gnd), - .combout(\z80_|interrupts_|test1~3_combout ), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h5545; -defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y15_N13 -dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), +// Location: FF_X28_Y12_N15 +dffeas \z80_|data_pins_|dout[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N14 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( +// Equation(s): +// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[6]~8_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|data_pins_|dout [6]), + .datad(\z80_|bus_control_|db[0]~6_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'hA2FF; +defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N3 +dffeas \z80_|ir_|opcode[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[6]~9_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~0_combout = (\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6])) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h0A00; +defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal38~2_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal38~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N0 +cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Equation(s): +// \z80_|interrupts_|iff1~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|interrupts_|iff1~q ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal79~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hE4CC; +defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N4 +cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( +// Equation(s): +// \z80_|interrupts_|iff1~1_combout = (\z80_|pla_decode_|Equal38~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|interrupts_|iff1~0_combout )))) # +// (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|iff1~0_combout )) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|interrupts_|iff1~0_combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hE4CC; +defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N24 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|interrupts_|DFFE_inst44~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFF3; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N5 +dffeas \z80_|interrupts_|iff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|iff1~1_combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|iff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|iff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y27_N8 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (\ula_|video_|Equal2~2_combout & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & (!\ula_|video_|vga_hc [7] & \z80_|interrupts_|iff1~q ))) + + .dataa(\ula_|video_|Equal2~2_combout ), + .datab(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), + .datac(\ula_|video_|vga_hc [7]), + .datad(\z80_|interrupts_|iff1~q ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0800; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y27_N9 +dffeas \z80_|interrupts_|int_armed ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), + .asdata(vcc), + .clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|int_armed~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; +defparam \z80_|interrupts_|int_armed .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N25 +dffeas \z80_|interrupts_|DFFE_inst44 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|interrupts_|int_armed~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), .ena(\z80_|interrupts_|test1~3_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .q(\z80_|interrupts_|DFFE_inst44~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; +defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y15_N2 -cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( +// Location: LCCOMB_X30_Y11_N22 +cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( // Equation(s): -// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|interrupts_|DFFE_inst44~q ))) +// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & \z80_|decode_state_|in_halt~q )) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0100; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y15_N3 -dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N20 -cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( -// Equation(s): -// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q & !\z80_|clk_delay_|DFF_inst5~q ) - - .dataa(gnd), - .datab(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), .datac(gnd), - .datad(\z80_|clk_delay_|DFF_inst5~q ), + .datad(\z80_|decode_state_|in_halt~q ), .cin(gnd), - .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), + .combout(\z80_|decode_state_|in_halt~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0033; -defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h1100; +defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N13 -dffeas \z80_|sequencer_|DFFE_T1_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|ena_M~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T1_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N4 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0050; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N5 -dffeas \z80_|sequencer_|DFFE_T2_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T2_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N10 -cycloneive_lcell_comb \z80_|resets_|x3 ( -// Equation(s): -// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(\z80_|resets_|x1~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|resets_|x3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|x3 .lut_mask = 16'hF0FA; -defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N11 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|x3~combout ), - .asdata(vcc), - .clrn(\z80_|fpga_reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; -// synopsys translate_on - -// Location: CLKCTRL_G7 -cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: FF_X32_Y17_N21 -dffeas \z80_|sequencer_|DFFE_M1_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M1_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N10 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( -// Equation(s): -// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h22A0; -defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N11 -dffeas \z80_|sequencer_|DFFE_M2_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M2_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~3 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~3_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~3 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~11 ( -// Equation(s): -// \z80_|execute_|nextM~11_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ctl_mWrite~3_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~11 .lut_mask = 16'h5557; -defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~8 ( -// Equation(s): -// \z80_|execute_|nextM~8_combout = (\z80_|alu_control_|flags_cond_true~q & (((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) # (!\z80_|alu_control_|flags_cond_true~q & ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout -// ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~8 .lut_mask = 16'h44F4; -defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~9 ( -// Equation(s): -// \z80_|execute_|nextM~9_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # (\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~9 .lut_mask = 16'h8880; -defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|nextM~10 ( -// Equation(s): -// \z80_|execute_|nextM~10_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datab(\z80_|execute_|nextM~9_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~12 ( -// Equation(s): -// \z80_|execute_|nextM~12_combout = ((\z80_|execute_|nextM~8_combout ) # ((\z80_|execute_|nextM~10_combout ) # (\z80_|execute_|ctl_alu_op_low~32_combout ))) # (!\z80_|execute_|nextM~11_combout ) - - .dataa(\z80_|execute_|nextM~11_combout ), - .datab(\z80_|execute_|nextM~8_combout ), - .datac(\z80_|execute_|nextM~10_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|nextM~15 ( -// Equation(s): -// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|fMRead~10_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|fMRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~15 .lut_mask = 16'h80A0; -defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|nextM~6 ( -// Equation(s): -// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|ixy_d~17_combout ) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|nextM~3_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~6 .lut_mask = 16'hDF5F; -defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~7 ( -// Equation(s): -// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ixy_d~8_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|execute_|nextM~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|nextM~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~7 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~13 ( -// Equation(s): -// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~12_combout ) # ((\z80_|execute_|nextM~15_combout ) # (\z80_|execute_|nextM~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|nextM~12_combout ), - .datac(\z80_|execute_|nextM~15_combout ), - .datad(\z80_|execute_|nextM~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~39 ( -// Equation(s): -// \z80_|execute_|setM1~39_combout = (!\z80_|execute_|ctl_mWrite~5_combout & \z80_|execute_|setM1~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|setM1~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0F00; -defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~5 ( -// Equation(s): -// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~45_combout ) # (!\z80_|execute_|nextM~2_combout )) # (!\z80_|execute_|setM1~39_combout ))) - - .dataa(\z80_|execute_|setM1~39_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|setM1~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~5 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|nextM~14 ( -// Equation(s): -// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~13_combout ) # (((\z80_|execute_|nextM~5_combout ) # (!\z80_|execute_|ctl_mRead~30_combout )) # (!\z80_|execute_|ctl_mWrite~13_combout )) - - .dataa(\z80_|execute_|nextM~13_combout ), - .datab(\z80_|execute_|ctl_mWrite~13_combout ), - .datac(\z80_|execute_|ctl_mRead~30_combout ), - .datad(\z80_|execute_|nextM~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~14 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N14 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00C0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N15 -dffeas \z80_|sequencer_|DFFE_T4_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T4_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N18 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N19 -dffeas \z80_|sequencer_|DFFE_T5_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T5_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N26 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00C0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N27 -dffeas \z80_|sequencer_|T6 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|T6~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|T6 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~13 ( -// Equation(s): -// \z80_|execute_|setM1~13_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|pla_decode_|Equal33~0_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal21~2_combout )))) # (!\z80_|pla_decode_|Equal13~0_combout & -// (((!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal21~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal21~2_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~13 .lut_mask = 16'h153F; -defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N4 +// Location: LCCOMB_X34_Y11_N16 cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( // Equation(s): -// \z80_|pla_decode_|Equal77~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) +// \z80_|pla_decode_|Equal77~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal21~0_combout ))) .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal21~0_combout ), .cin(gnd), .combout(\z80_|pla_decode_|Equal77~1_combout ), .cout()); @@ -50979,660 +43892,24 @@ defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~12 ( -// Equation(s): -// \z80_|execute_|setM1~12_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|pla_decode_|Equal2~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal77~1_combout ), - .datab(\z80_|execute_|ctl_alu_oe~3_combout ), - .datac(\z80_|pla_decode_|Equal1~6_combout ), - .datad(\z80_|pla_decode_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~14 ( -// Equation(s): -// \z80_|execute_|setM1~14_combout = (\z80_|execute_|setM1~13_combout & (\z80_|interrupts_|test1~2_combout & \z80_|execute_|setM1~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|setM1~13_combout ), - .datac(\z80_|interrupts_|test1~2_combout ), - .datad(\z80_|execute_|setM1~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~14 .lut_mask = 16'hC000; -defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~41 ( -// Equation(s): -// \z80_|execute_|setM1~41_combout = (!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_ir_we~10_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~41 .lut_mask = 16'h0005; -defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~42 ( -// Equation(s): -// \z80_|execute_|setM1~42_combout = (!\z80_|pla_decode_|Equal38~2_combout & (!\z80_|pla_decode_|Equal37~0_combout & (!\z80_|pla_decode_|Equal47~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0100; -defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~43 ( -// Equation(s): -// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~41_combout & (!\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|setM1~42_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|setM1~41_combout ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|execute_|setM1~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0400; -defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~44 ( -// Equation(s): -// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (\z80_|execute_|setM1~40_combout & ((!\z80_|pla_decode_|Equal2~1_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|execute_|setM1~43_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|pla_decode_|Equal2~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~44 .lut_mask = 16'h20A0; -defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~50 ( -// Equation(s): -// \z80_|execute_|setM1~50_combout = (\z80_|execute_|setM1~46_combout & (\z80_|execute_|setM1~14_combout & (\z80_|execute_|setM1~44_combout & \z80_|execute_|setM1~49_combout ))) - - .dataa(\z80_|execute_|setM1~46_combout ), - .datab(\z80_|execute_|setM1~14_combout ), - .datac(\z80_|execute_|setM1~44_combout ), - .datad(\z80_|execute_|setM1~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~50 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~51 ( -// Equation(s): -// \z80_|execute_|setM1~51_combout = (\z80_|sequencer_|T6~q & (((\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~39_combout )) # (!\z80_|execute_|setM1~40_combout ))) # (!\z80_|sequencer_|T6~q & (\z80_|execute_|setM1~50_combout & -// ((\z80_|execute_|setM1~39_combout )))) - - .dataa(\z80_|sequencer_|T6~q ), - .datab(\z80_|execute_|setM1~50_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|execute_|setM1~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~51 .lut_mask = 16'hCE0A; -defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~6 ( -// Equation(s): -// \z80_|execute_|setM1~6_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|sequencer_|M5~q & (\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & -// \z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~6 .lut_mask = 16'hD5C0; -defparam \z80_|execute_|setM1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~7 ( -// Equation(s): -// \z80_|execute_|setM1~7_combout = ((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|setM1~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~7 .lut_mask = 16'hF333; -defparam \z80_|execute_|setM1~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~8 ( -// Equation(s): -// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|fMWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~8 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~9 ( -// Equation(s): -// \z80_|execute_|setM1~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~9 .lut_mask = 16'hF1F0; -defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~10 ( -// Equation(s): -// \z80_|execute_|setM1~10_combout = ((\z80_|execute_|setM1~8_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout & \z80_|execute_|setM1~9_combout ))) # (!\z80_|execute_|nextM~2_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|setM1~8_combout ), - .datad(\z80_|execute_|setM1~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~11 ( -// Equation(s): -// \z80_|execute_|setM1~11_combout = (\z80_|execute_|setM1~7_combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|setM1~10_combout )) # (!\z80_|reg_control_|reg_sel_pc~3_combout )) - - .dataa(\z80_|execute_|setM1~7_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|setM1~10_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~11 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~17 ( -// Equation(s): -// \z80_|execute_|setM1~17_combout = ((\z80_|execute_|setM1~11_combout ) # ((!\z80_|execute_|setM1~14_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|setM1~16_combout ) - - .dataa(\z80_|execute_|setM1~16_combout ), - .datab(\z80_|execute_|setM1~14_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~17 .lut_mask = 16'hFF75; -defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~31 ( -// Equation(s): -// \z80_|execute_|setM1~31_combout = (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout & \z80_|execute_|ctl_mRead~18_combout )))) # (!\z80_|pla_decode_|Equal35~0_combout & -// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|execute_|ctl_mRead~18_combout )))) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~31 .lut_mask = 16'hECA0; -defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~28 ( -// Equation(s): -// \z80_|execute_|setM1~28_combout = ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~30 ( -// Equation(s): -// \z80_|execute_|setM1~30_combout = (((\z80_|execute_|ctl_state_alu~6_combout & \z80_|execute_|setM1~28_combout )) # (!\z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~54_combout ) - - .dataa(\z80_|execute_|setM1~54_combout ), - .datab(\z80_|execute_|setM1~29_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|setM1~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~30 .lut_mask = 16'hF777; -defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~32 ( -// Equation(s): -// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|setM1~9_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|setM1~9_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~32 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~33 ( -// Equation(s): -// \z80_|execute_|setM1~33_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~30_combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|setM1~32_combout ))) - - .dataa(\z80_|execute_|setM1~31_combout ), - .datab(\z80_|execute_|setM1~30_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|setM1~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~25 ( -// Equation(s): -// \z80_|execute_|setM1~25_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~25 .lut_mask = 16'hAF0F; -defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~26 ( -// Equation(s): -// \z80_|execute_|setM1~26_combout = ((\z80_|execute_|ctl_mRead~13_combout ) # ((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~26 .lut_mask = 16'hF7F5; -defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~24 ( -// Equation(s): -// \z80_|execute_|setM1~24_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_mRead~12_combout ))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & ((!\z80_|alu_control_|flags_cond_true~q )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|alu_control_|flags_cond_true~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~24 .lut_mask = 16'h0ACE; -defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~27 ( -// Equation(s): -// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|setM1~25_combout ) # (\z80_|execute_|setM1~26_combout )))) - - .dataa(\z80_|execute_|setM1~25_combout ), - .datab(\z80_|execute_|setM1~26_combout ), - .datac(\z80_|execute_|setM1~24_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~27 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~22 ( -// Equation(s): -// \z80_|execute_|setM1~22_combout = (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|execute_|fMWrite~9_combout & (!\z80_|execute_|ctl_mRead~8_combout & \z80_|execute_|fMWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|fMWrite~9_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~22 .lut_mask = 16'h0400; -defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~21 ( -// Equation(s): -// \z80_|execute_|setM1~21_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|decode_state_|DFFE_instNonRep~q ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~21 .lut_mask = 16'hF1F0; -defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~53 ( -// Equation(s): -// \z80_|execute_|setM1~53_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|execute_|setM1~21_combout & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~21_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~53 .lut_mask = 16'hC888; -defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~23 ( -// Equation(s): -// \z80_|execute_|setM1~23_combout = (\z80_|execute_|setM1~22_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) # (!\z80_|execute_|setM1~22_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # -// ((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) - - .dataa(\z80_|execute_|setM1~22_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|setM1~53_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~23 .lut_mask = 16'h4F44; -defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~18 ( -// Equation(s): -// \z80_|execute_|setM1~18_combout = (\z80_|execute_|ctl_mRead~11_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~18 .lut_mask = 16'h08CC; -defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~19 ( -// Equation(s): -// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~18_combout ) # ((\z80_|execute_|ixy_d~8_combout & (\z80_|pla_decode_|Equal10~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ))) - - .dataa(\z80_|execute_|setM1~18_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~19 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~20 ( -// Equation(s): -// \z80_|execute_|setM1~20_combout = ((\z80_|execute_|setM1~19_combout ) # ((\z80_|execute_|ctl_iorw~11_combout & \z80_|execute_|ctl_mWrite~3_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datad(\z80_|execute_|setM1~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~20 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~34 ( -// Equation(s): -// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~33_combout ) # ((\z80_|execute_|setM1~27_combout ) # ((\z80_|execute_|setM1~23_combout ) # (\z80_|execute_|setM1~20_combout ))) - - .dataa(\z80_|execute_|setM1~33_combout ), - .datab(\z80_|execute_|setM1~27_combout ), - .datac(\z80_|execute_|setM1~23_combout ), - .datad(\z80_|execute_|setM1~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~52 ( -// Equation(s): -// \z80_|execute_|setM1~52_combout = (!\z80_|execute_|setM1~17_combout & (!\z80_|execute_|setM1~34_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~51_combout )))) - - .dataa(\z80_|execute_|setM1~51_combout ), - .datab(\z80_|execute_|setM1~17_combout ), - .datac(\z80_|execute_|setM1~34_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~52 .lut_mask = 16'h0301; -defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N24 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N25 -dffeas \z80_|sequencer_|DFFE_T3_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T3_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N24 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( -// Equation(s): -// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|decode_state_|in_halt~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h0050; -defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N24 +// Location: LCCOMB_X30_Y11_N12 cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( // Equation(s): -// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|decode_state_|in_halt~q & \z80_|pla_decode_|Equal77~1_combout ))) +// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|pla_decode_|Equal77~1_combout & (!\z80_|decode_state_|in_halt~q & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|decode_state_|in_halt~0_combout ), + .dataa(\z80_|decode_state_|in_halt~0_combout ), + .datab(\z80_|pla_decode_|Equal77~1_combout ), .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|pla_decode_|Equal77~1_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), .cin(gnd), .combout(\z80_|decode_state_|in_halt~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hCECC; +defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hAEAA; defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y13_N25 +// Location: FF_X30_Y11_N13 dffeas \z80_|decode_state_|in_halt ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|decode_state_|in_halt~1_combout ), @@ -51651,434 +43928,489 @@ defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; defparam \z80_|decode_state_|in_halt .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Location: LCCOMB_X34_Y6_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_zero_oe~0_combout & (!\z80_|execute_|ctl_bus_ff_oe~1_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) +// \z80_|execute_|ctl_mRead~21_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal77~0_combout ))) .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .combout(\z80_|execute_|ctl_mRead~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0031; -defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( +// Location: LCCOMB_X34_Y6_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|pla_decode_|Equal41~2_combout ))) +// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|ctl_mRead~21_combout ) # (((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|fMWrite~0_combout )) # (!\z80_|execute_|fMRead~7_combout )) + + .dataa(\z80_|execute_|ctl_mRead~21_combout ), + .datab(\z80_|execute_|fMRead~7_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|fMWrite~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y8_N16 +cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( +// Equation(s): +// \z80_|execute_|fMRead~23_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|fMRead~4_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|fMRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hA2AA; +defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( +// Equation(s): +// \z80_|execute_|fMRead~27_combout = ((\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ixy_d~4_combout & \z80_|sequencer_|DFFE_M2_ff~q ))) # (!\z80_|execute_|fMRead~26_combout ) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|execute_|ixy_d~4_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|fMRead~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~27 .lut_mask = 16'h20FF; +defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Equation(s): +// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|pla_decode_|Equal41~2_combout ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hFB33; +defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( +// Equation(s): +// \z80_|execute_|fMRead~29_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((\z80_|ir_|opcode [7]) # (\z80_|ir_|opcode [6])))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|fMRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC080; +defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( +// Equation(s): +// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~10_combout ) # ((\z80_|execute_|ctl_ir_we~9_combout ) # (\z80_|execute_|fMRead~29_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|fMRead~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( +// Equation(s): +// \z80_|execute_|fMRead~31_combout = (\z80_|pla_decode_|Equal33~3_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|pla_decode_|Equal33~3_combout & (\z80_|pla_decode_|Equal6~1_combout & +// ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFAC8; +defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Equation(s): +// \z80_|execute_|fMRead~32_combout = (\z80_|execute_|fMRead~28_combout ) # ((\z80_|execute_|fMRead~30_combout ) # ((\z80_|execute_|fMRead~31_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ))) + + .dataa(\z80_|execute_|fMRead~28_combout ), + .datab(\z80_|execute_|fMRead~30_combout ), + .datac(\z80_|execute_|fMRead~31_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~37 ( +// Equation(s): +// \z80_|execute_|fMRead~37_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_mRead~13_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~37 .lut_mask = 16'h0E00; +defparam \z80_|execute_|fMRead~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Equation(s): +// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~27_combout ) # (((\z80_|execute_|fMRead~32_combout ) # (\z80_|execute_|fMRead~37_combout )) # (!\z80_|execute_|fMRead~6_combout )) + + .dataa(\z80_|execute_|fMRead~27_combout ), + .datab(\z80_|execute_|fMRead~6_combout ), + .datac(\z80_|execute_|fMRead~32_combout ), + .datad(\z80_|execute_|fMRead~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( +// Equation(s): +// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & (\z80_|execute_|ctl_alu_oe~2_combout & +// ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~16_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ctl_mRead~16_combout ), + .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~24 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( +// Equation(s): +// \z80_|execute_|fMRead~25_combout = ((\z80_|execute_|fMRead~24_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~33_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|pc_inc_hold~33_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|fMRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~25 .lut_mask = 16'hFF2F; +defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( +// Equation(s): +// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_ir_we~12_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~21_combout ) # (\z80_|execute_|ctl_mRead~13_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_mRead~21_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~16 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( +// Equation(s): +// \z80_|execute_|fMRead~11_combout = ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ctl_mRead~21_combout ) # (!\z80_|execute_|nextM~3_combout ))) # (!\z80_|execute_|pc_inc_hold~14_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~14_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_mRead~21_combout ), + .datad(\z80_|execute_|nextM~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Equation(s): +// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_bus_db_oe~1_combout & (!\z80_|execute_|ctl_mRead~2_combout & (!\z80_|pla_decode_|Equal6~1_combout & !\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datab(\z80_|execute_|ctl_mRead~2_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~12 .lut_mask = 16'h0002; +defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Equation(s): +// \z80_|execute_|fMRead~13_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|fMRead~11_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # (!\z80_|execute_|fMRead~12_combout )))) + + .dataa(\z80_|execute_|fMRead~11_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|fMRead~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~13 .lut_mask = 16'hC8CC; +defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Equation(s): +// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout ))) .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFBFA; +defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y6_N10 +cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Equation(s): +// \z80_|execute_|fMRead~15_combout = (!\z80_|execute_|fMWrite~2_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|fMRead~14_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~4_combout ), + .datab(\z80_|execute_|fMWrite~2_combout ), .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|fMRead~14_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .combout(\z80_|execute_|fMRead~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~15 .lut_mask = 16'h3332; +defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( +// Location: LCCOMB_X34_Y6_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_bus_db_oe~5_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) +// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~15_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|fMRead~16_combout ))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|fMRead~16_combout ), + .datac(\z80_|execute_|fMRead~13_combout ), + .datad(\z80_|execute_|fMRead~15_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .combout(\z80_|execute_|fMRead~17_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFDF5; -defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~17 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( +// Location: LCCOMB_X34_Y10_N10 +cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) +// \z80_|execute_|fMRead~22_combout = (((\z80_|execute_|fMRead~17_combout ) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|fMRead~21_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datab(\z80_|execute_|fMRead~21_combout ), + .datac(\z80_|execute_|fMRead~17_combout ), + .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y10_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( +// Equation(s): +// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|fMRead~23_combout ) # ((\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|fMRead~25_combout ) # (\z80_|execute_|fMRead~22_combout ))) + + .dataa(\z80_|execute_|fMRead~23_combout ), + .datab(\z80_|execute_|fMRead~33_combout ), + .datac(\z80_|execute_|fMRead~25_combout ), + .datad(\z80_|execute_|fMRead~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~36 ( +// Equation(s): +// \z80_|execute_|fMRead~36_combout = (\z80_|execute_|fMRead~34_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((\z80_|execute_|fMRead~35_combout & !\z80_|execute_|fMRead~2_combout ))) + + .dataa(\z80_|execute_|fMRead~35_combout ), + .datab(\z80_|execute_|fMRead~34_combout ), + .datac(\z80_|execute_|fMRead~2_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~36 .lut_mask = 16'hFFCE; +defparam \z80_|execute_|fMRead~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout )) .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|fMRead~36_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .combout(\z80_|pin_control_|bus_db_pin_re~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; -defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; +defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFC0; +defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Location: LCCOMB_X21_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~103 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (\z80_|execute_|ctl_bus_db_oe~4_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hAAA2; -defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( -// Equation(s): -// \z80_|bus_control_|db[0]~6_combout = (\z80_|execute_|ctl_bus_db_oe~combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) - - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFAFF; -defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~93 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~93_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~47_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~93_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~93 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[1][3]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~94 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~94_combout = (\ula_|zx_keyboard_|keys[1][3]~93_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # -// (!\ula_|zx_keyboard_|keys[1][3]~93_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[1][3]~93_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~94 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][3]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N31 -dffeas \ula_|zx_keyboard_|keys[1][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) +// \ula_|zx_keyboard_|keys[5][3]~103_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5])) .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .combout(\ula_|zx_keyboard_|keys[5][3]~103_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][3]~103 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|keys[5][3]~103 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~98 ( +// Location: LCCOMB_X20_Y10_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~20 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~98_combout = (\ula_|zx_keyboard_|keys[0][3]~96_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & -// (\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][3]~96_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) +// \ula_|zx_keyboard_|keys[5][4]~20_combout = (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) - .dataa(\ula_|zx_keyboard_|keys[0][3]~96_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .datac(\ula_|zx_keyboard_|keys[0][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~98_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~98 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[0][3]~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N1 -dffeas \ula_|zx_keyboard_|keys[0][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][3]~98_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N4 -cycloneive_lcell_comb \D[3]~65 ( -// Equation(s): -// \D[3]~65_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][3]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][3]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][3]~q ), - .cin(gnd), - .combout(\D[3]~65_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~65 .lut_mask = 16'h8CAF; -defparam \D[3]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~99 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~99_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), .datad(gnd), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~99_combout ), + .combout(\ula_|zx_keyboard_|keys[5][4]~20_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~99 .lut_mask = 16'h4040; -defparam \ula_|zx_keyboard_|keys[3][3]~99 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][4]~20 .lut_mask = 16'hC0C0; +defparam \ula_|zx_keyboard_|keys[5][4]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~100 ( +// Location: LCCOMB_X20_Y10_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~21 ( // Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~100_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[3][3]~99_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][3]~99_combout & (\ula_|zx_keyboard_|keys[3][3]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[3][3]~q )))) +// \ula_|zx_keyboard_|keys[1][4]~21_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) - .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .datab(\ula_|zx_keyboard_|keys[3][3]~99_combout ), - .datac(\ula_|zx_keyboard_|keys[3][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~100_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~100 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[3][3]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N9 -dffeas \ula_|zx_keyboard_|keys[3][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][3]~100_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'hCCDD; -defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .combout(\ula_|zx_keyboard_|keys[1][4]~21_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[1][4]~21 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[1][4]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~133 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~133_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][3]~102_combout & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|zx_keyboard_|keys[2][3]~102_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~133_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~133 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[2][3]~133 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~103 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~103_combout = (\ula_|zx_keyboard_|keys[2][3]~133_combout & (!\ula_|zx_keyboard_|keys[2][3]~101_combout )) # (!\ula_|zx_keyboard_|keys[2][3]~133_combout & ((\ula_|zx_keyboard_|keys[2][3]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[2][3]~101_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][3]~133_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~103 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[2][3]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N3 -dffeas \ula_|zx_keyboard_|keys[2][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N28 -cycloneive_lcell_comb \D[3]~66 ( -// Equation(s): -// \D[3]~66_combout = (\z80_|address_pins_|abus[11]~19_combout & (((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & -// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[3][3]~q ), - .datac(\z80_|address_pins_|abus[10]~24_combout ), - .datad(\ula_|zx_keyboard_|keys[2][3]~q ), - .cin(gnd), - .combout(\D[3]~66_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~66 .lut_mask = 16'hB0BB; -defparam \D[3]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N12 +// Location: LCCOMB_X21_Y8_N24 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( // Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) +// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|zx_keyboard_|keys[5][3]~103_combout & ((\ula_|zx_keyboard_|keys[1][4]~21_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][4]~21_combout & ((\ula_|zx_keyboard_|keys[5][3]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][3]~103_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(gnd), + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[5][3]~103_combout ), + .datac(\ula_|zx_keyboard_|keys[5][3]~q ), + .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h0808; +defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h74F0; defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y19_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~105 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~105_combout = (\ula_|zx_keyboard_|keys[5][3]~104_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[5][3]~q -// )))) # (!\ula_|zx_keyboard_|keys[5][3]~104_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][3]~104_combout ), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[5][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~105_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~105 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][3]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N23 +// Location: FF_X21_Y8_N25 dffeas \ula_|zx_keyboard_|keys[5][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][3]~105_combout ), + .d(\ula_|zx_keyboard_|keys[5][3]~104_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52094,32 +44426,49 @@ defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y19_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( +// Location: LCCOMB_X19_Y9_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~73 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|WideOr16~2_combout ))) +// \ula_|zx_keyboard_|keys[3][0]~73_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1])) - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .combout(\ula_|zx_keyboard_|keys[3][0]~73_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[3][0]~73 .lut_mask = 16'h0500; +defparam \ula_|zx_keyboard_|keys[3][0]~73 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( +// Location: LCCOMB_X19_Y10_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( // Equation(s): -// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) +// \ula_|zx_keyboard_|Selector5~0_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[3][0]~73_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]))) .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|zx_keyboard_|keys[3][0]~73_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), .cin(gnd), .combout(\ula_|zx_keyboard_|Selector5~1_combout ), .cout()); @@ -52128,96 +44477,113 @@ defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h0800; defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( +// Location: LCCOMB_X19_Y10_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~129 ( // Equation(s): -// \ula_|zx_keyboard_|Selector5~0_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5]))) +// \ula_|zx_keyboard_|keys[4][3]~129_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|Selector5~1_combout ))) - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~134 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~134_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|zx_keyboard_|Selector5~1_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|Selector5~1_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), .datab(\ula_|zx_keyboard_|Selector5~0_combout ), .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|Selector5~1_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~134_combout ), + .combout(\ula_|zx_keyboard_|keys[4][3]~129_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~134 .lut_mask = 16'hCECC; -defparam \ula_|zx_keyboard_|keys[4][3]~134 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[4][3]~129 .lut_mask = 16'hCECC; +defparam \ula_|zx_keyboard_|keys[4][3]~129 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N6 +// Location: LCCOMB_X21_Y10_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~1 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~1_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~1 .lut_mask = 16'h0030; +defparam \ula_|zx_keyboard_|WideOr16~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~105 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~105_combout = (\ula_|zx_keyboard_|WideOr16~1_combout & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) + + .dataa(\ula_|zx_keyboard_|WideOr16~1_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~105_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~105 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][3]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|zx_keyboard_|extended~q & (((\ula_|zx_keyboard_|keys[4][3]~105_combout )))) # (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~129_combout & (\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|zx_keyboard_|keys[4][3]~129_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[4][3]~105_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'hEC20; +defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~130 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~130_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~130_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~130 .lut_mask = 16'hAAAE; +defparam \ula_|zx_keyboard_|keys[4][3]~130 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N2 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~107 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~106_combout )) # (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][3]~134_combout )))) +// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & ((\ula_|zx_keyboard_|keys[4][3]~106_combout & ((!\ula_|zx_keyboard_|keys[4][3]~130_combout ))) # (!\ula_|zx_keyboard_|keys[4][3]~106_combout & +// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) - .dataa(\ula_|zx_keyboard_|extended~q ), + .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), .datab(\ula_|zx_keyboard_|keys[4][3]~106_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][3]~134_combout ), + .datac(\ula_|zx_keyboard_|keys[4][3]~q ), + .datad(\ula_|zx_keyboard_|keys[4][3]~130_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[4][3]~107_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'hD888; +defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'h70F8; defparam \ula_|zx_keyboard_|keys[4][3]~107 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~135 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~135_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q ))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|shifted~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~135_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~135 .lut_mask = 16'hCDCC; -defparam \ula_|zx_keyboard_|keys[4][3]~135 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~108 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~108_combout = (\ula_|zx_keyboard_|keys[4][3]~107_combout & ((\ula_|zx_keyboard_|keys[0][0]~15_combout & ((!\ula_|zx_keyboard_|keys[4][3]~135_combout ))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & -// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[4][3]~107_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~107_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\ula_|zx_keyboard_|keys[4][3]~135_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~108_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~108 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][3]~108 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N23 +// Location: FF_X21_Y8_N3 dffeas \ula_|zx_keyboard_|keys[4][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][3]~108_combout ), + .d(\ula_|zx_keyboard_|keys[4][3]~107_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52233,79 +44599,257 @@ defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y19_N20 -cycloneive_lcell_comb \D[3]~67 ( +// Location: LCCOMB_X21_Y8_N12 +cycloneive_lcell_comb \D[3]~74 ( // Equation(s): -// \D[3]~67_combout = (\ula_|zx_keyboard_|keys[5][3]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][3]~q & -// (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) +// \D[3]~74_combout = (\z80_|address_pins_|abus[12]~24_combout & (((\z80_|address_pins_|abus[13]~23_combout )) # (!\ula_|zx_keyboard_|keys[5][3]~q ))) # (!\z80_|address_pins_|abus[12]~24_combout & (!\ula_|zx_keyboard_|keys[4][3]~q & +// ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) - .dataa(\ula_|zx_keyboard_|keys[5][3]~q ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), + .dataa(\z80_|address_pins_|abus[12]~24_combout ), + .datab(\ula_|zx_keyboard_|keys[5][3]~q ), + .datac(\z80_|address_pins_|abus[13]~23_combout ), + .datad(\ula_|zx_keyboard_|keys[4][3]~q ), .cin(gnd), - .combout(\D[3]~67_combout ), + .combout(\D[3]~74_combout ), .cout()); // synopsys translate_off -defparam \D[3]~67 .lut_mask = 16'hDD0D; -defparam \D[3]~67 .sum_lutc_input = "datac"; +defparam \D[3]~74 .lut_mask = 16'hA2F3; +defparam \D[3]~74 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~112 ( +// Location: LCCOMB_X20_Y8_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~112_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~32_combout ) # ((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~61_combout )))) +// \ula_|zx_keyboard_|keys[5][1]~39_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[0][0]~11_combout & !\ula_|zx_keyboard_|extended~q )) - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~112_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~112 .lut_mask = 16'hA888; -defparam \ula_|zx_keyboard_|keys[7][3]~112 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~113 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~113_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][3]~112_combout & (\ula_|zx_keyboard_|keys[0][0]~15_combout & !\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[7][3]~112_combout ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[0][0]~11_combout ), .datad(\ula_|zx_keyboard_|extended~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~113_combout ), + .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~113 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[7][3]~113 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h0050; +defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X25_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~114 ( +// Location: LCCOMB_X21_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~100 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~114_combout = (\ula_|zx_keyboard_|keys[7][3]~113_combout & ((!\ula_|zx_keyboard_|keys[0][4]~111_combout ))) # (!\ula_|zx_keyboard_|keys[7][3]~113_combout & (\ula_|zx_keyboard_|keys[7][3]~q )) +// \ula_|zx_keyboard_|keys[2][3]~100_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & +// !\ula_|ps2_keyboard_|shiftreg [2])) .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[7][3]~113_combout ), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~111_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .combout(\ula_|zx_keyboard_|keys[2][3]~100_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~114 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[7][3]~114 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][3]~100 .lut_mask = 16'h0C30; +defparam \ula_|zx_keyboard_|keys[2][3]~100 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y20_N9 +// Location: LCCOMB_X21_Y10_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|keys[2][3]~100_combout & (\ula_|zx_keyboard_|keys[5][4]~59_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (!\ula_|ps2_keyboard_|shiftreg [3])))) + + .dataa(\ula_|zx_keyboard_|keys[2][3]~100_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[5][4]~59_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'h8200; +defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~99 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~99_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~99 .lut_mask = 16'hF0F5; +defparam \ula_|zx_keyboard_|keys[2][3]~99 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & ((\ula_|zx_keyboard_|keys[2][3]~101_combout & ((!\ula_|zx_keyboard_|keys[2][3]~99_combout ))) # (!\ula_|zx_keyboard_|keys[2][3]~101_combout & +// (\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~39_combout & (((\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .datab(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .datac(\ula_|zx_keyboard_|keys[2][3]~q ), + .datad(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y7_N23 +dffeas \ula_|zx_keyboard_|keys[2][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~97 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~97_combout = (\ula_|zx_keyboard_|keys[6][4]~44_combout & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[5][4]~59_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~44_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[5][4]~59_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~97_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~97 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[3][3]~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~98 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~98_combout = (\ula_|zx_keyboard_|keys[3][3]~97_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][3]~97_combout & ((\ula_|zx_keyboard_|keys[3][3]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][3]~97_combout ), + .datac(\ula_|zx_keyboard_|keys[3][3]~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~98_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~98 .lut_mask = 16'h7474; +defparam \ula_|zx_keyboard_|keys[3][3]~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y7_N25 +dffeas \ula_|zx_keyboard_|keys[3][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][3]~98_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N20 +cycloneive_lcell_comb \D[3]~73 ( +// Equation(s): +// \D[3]~73_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~20_combout ) # ((!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & +// ((\z80_|address_pins_|abus[10]~20_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\z80_|address_pins_|abus[10]~20_combout ), + .datac(\ula_|zx_keyboard_|keys[2][3]~q ), + .datad(\ula_|zx_keyboard_|keys[3][3]~q ), + .cin(gnd), + .combout(\D[3]~73_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~73 .lut_mask = 16'h8ACF; +defparam \D[3]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~108 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~108_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~108 .lut_mask = 16'hFAF0; +defparam \ula_|zx_keyboard_|keys[0][4]~108 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~109 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~109_combout = (\ula_|zx_keyboard_|WideOr16~1_combout & ((\ula_|zx_keyboard_|keys[7][2]~28_combout ) # ((\ula_|zx_keyboard_|keys[7][2]~57_combout & \ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~57_combout ), + .datab(\ula_|zx_keyboard_|keys[7][2]~28_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|WideOr16~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~109_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~109 .lut_mask = 16'hEC00; +defparam \ula_|zx_keyboard_|keys[7][3]~109 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~110 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~110_combout = (\ula_|zx_keyboard_|keys[7][3]~109_combout & ((\ula_|zx_keyboard_|keys[7][2]~56_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[7][2]~56_combout & +// ((\ula_|zx_keyboard_|keys[7][3]~q ))))) # (!\ula_|zx_keyboard_|keys[7][3]~109_combout & (((\ula_|zx_keyboard_|keys[7][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .datab(\ula_|zx_keyboard_|keys[7][3]~109_combout ), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\ula_|zx_keyboard_|keys[7][2]~56_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~110_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~110 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[7][3]~110 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y8_N23 dffeas \ula_|zx_keyboard_|keys[7][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .d(\ula_|zx_keyboard_|keys[7][3]~110_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52321,79 +44865,79 @@ defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~109 ( +// Location: LCCOMB_X20_Y8_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~111 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~109_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [5]))) +// \ula_|zx_keyboard_|keys[6][3]~111_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), .datad(\ula_|ps2_keyboard_|shiftreg [5]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~109_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~111_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~109 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|keys[6][3]~109 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~111 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][3]~111 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~110 ( +// Location: LCCOMB_X20_Y8_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~112 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~110_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~109_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][2]~32_combout ))) +// \ula_|zx_keyboard_|keys[6][3]~112_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~111_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & ((\ula_|zx_keyboard_|keys[7][2]~28_combout )))) .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|zx_keyboard_|keys[6][3]~109_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|zx_keyboard_|keys[6][3]~111_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|zx_keyboard_|keys[7][2]~28_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~112_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~110 .lut_mask = 16'hF088; -defparam \ula_|zx_keyboard_|keys[6][3]~110 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~112 .lut_mask = 16'hCAC0; +defparam \ula_|zx_keyboard_|keys[6][3]~112 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~137 ( +// Location: LCCOMB_X20_Y8_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~132 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~137_combout = (\ula_|zx_keyboard_|extended~q ) # (((!\ula_|zx_keyboard_|keys[0][0]~15_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][3]~110_combout )) +// \ula_|zx_keyboard_|keys[6][3]~132_combout = (((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][3]~112_combout )) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout ) - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .datab(\ula_|zx_keyboard_|keys[6][3]~112_combout ), .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~132_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~137 .lut_mask = 16'hBFFF; -defparam \ula_|zx_keyboard_|keys[6][3]~137 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~132 .lut_mask = 16'hFF7F; +defparam \ula_|zx_keyboard_|keys[6][3]~132 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~138 ( +// Location: LCCOMB_X23_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~133 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~138_combout = (\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~137_combout & ((\ula_|zx_keyboard_|keys[6][3]~q ))) # (!\ula_|zx_keyboard_|keys[6][3]~137_combout & -// (!\ula_|zx_keyboard_|Selector13~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|zx_keyboard_|keys[6][3]~q )))) +// \ula_|zx_keyboard_|keys[6][3]~133_combout = (\ula_|zx_keyboard_|keys[6][3]~132_combout & (((\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[6][3]~132_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & +// ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[6][3]~q )))) - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|Selector13~0_combout ), + .dataa(\ula_|zx_keyboard_|keys[6][3]~132_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), .datac(\ula_|zx_keyboard_|keys[6][3]~q ), - .datad(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .datad(\ula_|zx_keyboard_|Selector13~0_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~133_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~138 .lut_mask = 16'hF072; -defparam \ula_|zx_keyboard_|keys[6][3]~138 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~133 .lut_mask = 16'hB0F4; +defparam \ula_|zx_keyboard_|keys[6][3]~133 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y21_N29 +// Location: FF_X23_Y8_N5 dffeas \ula_|zx_keyboard_|keys[6][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .d(\ula_|zx_keyboard_|keys[6][3]~133_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52409,115 +44953,220 @@ defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( +// Location: LCCOMB_X23_Y8_N30 +cycloneive_lcell_comb \D[3]~75 ( // Equation(s): -// \ula_|zx_keyboard_|key_row~2_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # ((!\ula_|zx_keyboard_|keys[6][3]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) +// \D[3]~75_combout = (\ula_|zx_keyboard_|keys[7][3]~q & (\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[7][3]~q & +// ((\z80_|address_pins_|abus[14]~22_combout ) # ((!\ula_|zx_keyboard_|keys[6][3]~q )))) - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [14]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|zx_keyboard_|keys[6][3]~q ), + .dataa(\ula_|zx_keyboard_|keys[7][3]~q ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ula_|zx_keyboard_|keys[6][3]~q ), + .datad(\z80_|address_pins_|abus[15]~21_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~2_combout ), + .combout(\D[3]~75_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hCFFF; -defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; +defparam \D[3]~75 .lut_mask = 16'hCF45; +defparam \D[3]~75 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N8 -cycloneive_lcell_comb \D[3]~68 ( +// Location: LCCOMB_X23_Y8_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~94 ( // Equation(s): -// \D[3]~68_combout = (\D[3]~67_combout & (\ula_|zx_keyboard_|key_row~2_combout & ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) +// \ula_|zx_keyboard_|keys[0][3]~94_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\D[3]~67_combout ), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|key_row~2_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\D[3]~68_combout ), + .combout(\ula_|zx_keyboard_|keys[0][3]~94_combout ), .cout()); // synopsys translate_off -defparam \D[3]~68 .lut_mask = 16'h8C00; -defparam \D[3]~68 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[0][3]~94 .lut_mask = 16'h2004; +defparam \ula_|zx_keyboard_|keys[0][3]~94 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N30 -cycloneive_lcell_comb \D[3]~69 ( +// Location: LCCOMB_X23_Y8_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~93 ( // Equation(s): -// \D[3]~69_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[3]~65_combout & (\D[3]~66_combout & \D[3]~68_combout ))) +// \ula_|zx_keyboard_|keys[2][4]~93_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|shifted~q )) - .dataa(\D[3]~65_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[3]~66_combout ), - .datad(\D[3]~68_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), .cin(gnd), - .combout(\D[3]~69_combout ), + .combout(\ula_|zx_keyboard_|keys[2][4]~93_combout ), .cout()); // synopsys translate_off -defparam \D[3]~69 .lut_mask = 16'hECCC; -defparam \D[3]~69 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[2][4]~93 .lut_mask = 16'hF0FA; +defparam \ula_|zx_keyboard_|keys[2][4]~93 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y11_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: LCCOMB_X23_Y7_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~95 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~95_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~95 .lut_mask = 16'h0060; +defparam \ula_|zx_keyboard_|keys[0][4]~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|zx_keyboard_|keys[0][3]~94_combout & ((\ula_|zx_keyboard_|keys[0][4]~95_combout & (!\ula_|zx_keyboard_|keys[2][4]~93_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & +// ((\ula_|zx_keyboard_|keys[0][3]~q ))))) # (!\ula_|zx_keyboard_|keys[0][3]~94_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][3]~94_combout ), + .datab(\ula_|zx_keyboard_|keys[2][4]~93_combout ), + .datac(\ula_|zx_keyboard_|keys[0][3]~q ), + .datad(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y8_N3 +dffeas \ula_|zx_keyboard_|keys[0][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), - .portbdataout()); + .q(\ula_|zx_keyboard_|keys[0][3]~q ), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; // synopsys translate_on -// Location: M9K_X22_Y15_N0 +// Location: LCCOMB_X19_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~91 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~91_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][4]~15_combout & \ula_|zx_keyboard_|keys[6][4]~43_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[7][4]~15_combout ), + .datad(\ula_|zx_keyboard_|keys[6][4]~43_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~91_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~91 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[1][3]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~92 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~92_combout = (\ula_|zx_keyboard_|keys[1][3]~91_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # +// (!\ula_|zx_keyboard_|keys[1][3]~91_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][3]~91_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~92 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[1][3]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y9_N5 +dffeas \ula_|zx_keyboard_|keys[1][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N8 +cycloneive_lcell_comb \D[3]~72 ( +// Equation(s): +// \D[3]~72_combout = (\z80_|address_pins_|abus[9]~17_combout & (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][3]~q ))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][3]~q & +// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\z80_|address_pins_|abus[9]~17_combout ), + .datab(\ula_|zx_keyboard_|keys[0][3]~q ), + .datac(\z80_|address_pins_|abus[8]~18_combout ), + .datad(\ula_|zx_keyboard_|keys[1][3]~q ), + .cin(gnd), + .combout(\D[3]~72_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~72 .lut_mask = 16'hA2F3; +defparam \D[3]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N10 +cycloneive_lcell_comb \D[3]~76 ( +// Equation(s): +// \D[3]~76_combout = (\D[3]~74_combout & (\D[3]~73_combout & (\D[3]~75_combout & \D[3]~72_combout ))) + + .dataa(\D[3]~74_combout ), + .datab(\D[3]~73_combout ), + .datac(\D[3]~75_combout ), + .datad(\D[3]~72_combout ), + .cin(gnd), + .combout(\D[3]~76_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~76 .lut_mask = 16'h8000; +defparam \D[3]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N2 +cycloneive_lcell_comb \D[3]~122 ( +// Equation(s): +// \D[3]~122_combout = (\Equal2~0_combout & ((\D[3]~76_combout ) # ((\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) + + .dataa(\D[3]~76_combout ), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\Equal2~0_combout ), + .cin(gnd), + .combout(\D[3]~122_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~122 .lut_mask = 16'hEF00; +defparam \D[3]~122 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y14_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .portare(vcc), @@ -52533,8 +45182,8 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52574,7 +45223,24 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; // synopsys translate_on -// Location: M9K_X22_Y18_N0 +// Location: LCCOMB_X25_Y15_N28 +cycloneive_lcell_comb \D[3]~79 ( +// Equation(s): +// \D[3]~79_combout = (!\Equal2~0_combout & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\Equal2~0_combout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\D[3]~79_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~79 .lut_mask = 16'h3332; +defparam \D[3]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), @@ -52590,8 +45256,8 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52631,25 +45297,7 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N14 -cycloneive_lcell_comb \D[3]~73 ( -// Equation(s): -// \D[3]~73_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .cin(gnd), - .combout(\D[3]~73_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~73 .lut_mask = 16'hCCE2; -defparam \D[3]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y5_N0 +// Location: M9K_X22_Y15_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), .portare(vcc), @@ -52665,8 +45313,8 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52706,42 +45354,24 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N16 -cycloneive_lcell_comb \D[3]~74 ( -// Equation(s): -// \D[3]~74_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\D[3]~73_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ))) # (!\D[3]~73_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[3]~73_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datac(\D[3]~73_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), - .cin(gnd), - .combout(\D[3]~74_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~74 .lut_mask = 16'hF858; -defparam \D[3]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y19_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(vcc), +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52750,39 +45380,238 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X22_Y23_N0 +// Location: M9K_X33_Y12_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N20 +cycloneive_lcell_comb \D[3]~77 ( +// Equation(s): +// \D[3]~77_combout = (\z80_|address_pins_|abus[15]~21_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) # (!\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # +// ((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\D[3]~77_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~77 .lut_mask = 16'hF5E4; +defparam \D[3]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N22 +cycloneive_lcell_comb \D[3]~80 ( +// Equation(s): +// \D[3]~80_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~77_combout ))) + + .dataa(gnd), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\D[3]~77_combout ), + .cin(gnd), + .combout(\D[3]~80_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~80 .lut_mask = 16'hCFC0; +defparam \D[3]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N4 +cycloneive_lcell_comb \D[3]~81 ( +// Equation(s): +// \D[3]~81_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[3]~80_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout +// )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datac(\D[3]~80_combout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\D[3]~81_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~81 .lut_mask = 16'hF0DD; +defparam \D[3]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N30 +cycloneive_lcell_comb \D[3]~124 ( +// Equation(s): +// \D[3]~124_combout = (\D[3]~77_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ) # ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [14])))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datad(\D[3]~77_combout ), + .cin(gnd), + .combout(\D[3]~124_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~124 .lut_mask = 16'hF200; +defparam \D[3]~124 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y23_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), .portare(vcc), @@ -52792,14 +45621,14 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), .ena1(gnd), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portadatain({\D[3]~109_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52855,26 +45684,8 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N24 -cycloneive_lcell_comb \D[3]~70 ( -// Equation(s): -// \D[3]~70_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~23_combout )) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\z80_|address_pins_|abus[14]~23_combout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .cin(gnd), - .combout(\D[3]~70_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~70 .lut_mask = 16'hEC64; -defparam \D[3]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y21_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( +// Location: M9K_X22_Y32_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( .portawe(vcc), .portare(vcc), .portaaddrstall(gnd), @@ -52883,14 +45694,14 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), .portabyteenamasks(1'b1), @@ -52899,217 +45710,143 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N22 -cycloneive_lcell_comb \D[3]~71 ( +// Location: LCCOMB_X25_Y15_N0 +cycloneive_lcell_comb \D[3]~123 ( // Equation(s): -// \D[3]~71_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout $ (((\D[3]~70_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout & !\D[3]~70_combout )))) +// \D[3]~123_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & (\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # (!\z80_|address_pins_|DFFE_apin_latch [14] & +// ((\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datad(\D[3]~70_combout ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), .cin(gnd), - .combout(\D[3]~71_combout ), + .combout(\D[3]~123_combout ), .cout()); // synopsys translate_off -defparam \D[3]~71 .lut_mask = 16'h22D8; -defparam \D[3]~71 .sum_lutc_input = "datac"; +defparam \D[3]~123 .lut_mask = 16'hF2D0; +defparam \D[3]~123 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X22_Y31_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N20 -cycloneive_lcell_comb \D[3]~72 ( +// Location: LCCOMB_X25_Y15_N10 +cycloneive_lcell_comb \D[3]~78 ( // Equation(s): -// \D[3]~72_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\D[3]~70_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~70_combout & (!\D[3]~71_combout & -// \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout )) # (!\D[3]~70_combout & (\D[3]~71_combout )))) +// \D[3]~78_combout = (!\Equal2~0_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~123_combout ))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\D[3]~124_combout )))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\D[3]~70_combout ), - .datac(\D[3]~71_combout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .dataa(\Equal2~0_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[3]~124_combout ), + .datad(\D[3]~123_combout ), .cin(gnd), - .combout(\D[3]~72_combout ), + .combout(\D[3]~78_combout ), .cout()); // synopsys translate_off -defparam \D[3]~72 .lut_mask = 16'h9C98; -defparam \D[3]~72 .sum_lutc_input = "datac"; +defparam \D[3]~78 .lut_mask = 16'h5410; +defparam \D[3]~78 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N28 +// Location: LCCOMB_X25_Y15_N6 +cycloneive_lcell_comb \D[3]~82 ( +// Equation(s): +// \D[3]~82_combout = (\z80_|address_pins_|abus[15]~21_combout & (\D[3]~79_combout & (\D[3]~81_combout ))) # (!\z80_|address_pins_|abus[15]~21_combout & (((\D[3]~78_combout )))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\D[3]~79_combout ), + .datac(\D[3]~81_combout ), + .datad(\D[3]~78_combout ), + .cin(gnd), + .combout(\D[3]~82_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~82 .lut_mask = 16'hD580; +defparam \D[3]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N26 cycloneive_lcell_comb \D[3]~108 ( // Equation(s): -// \D[3]~108_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[3]~74_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[3]~72_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[3]~74_combout )))) +// \D[3]~108_combout = ((\D[3]~122_combout ) # (\D[3]~82_combout )) # (!\Equal2~1_combout ) - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\D[3]~74_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[3]~72_combout ), + .dataa(\Equal2~1_combout ), + .datab(\D[3]~122_combout ), + .datac(gnd), + .datad(\D[3]~82_combout ), .cin(gnd), .combout(\D[3]~108_combout ), .cout()); // synopsys translate_off -defparam \D[3]~108 .lut_mask = 16'hDC8C; +defparam \D[3]~108 .lut_mask = 16'hFFDD; defparam \D[3]~108 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N4 -cycloneive_lcell_comb \D[3]~95 ( +// Location: LCCOMB_X25_Y15_N8 +cycloneive_lcell_comb \D[3]~109 ( // Equation(s): -// \D[3]~95_combout = ((\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout )))) # (!\Equal2~1_combout ) +// \D[3]~109_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [3] & (\D[3]~108_combout ))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[3]~108_combout ) # (!\Equal2~1_combout )))) - .dataa(\D[3]~69_combout ), - .datab(\Equal2~1_combout ), - .datac(\Equal2~0_combout ), - .datad(\D[3]~108_combout ), + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|data_pins_|dout [3]), + .datac(\D[3]~108_combout ), + .datad(\Equal2~1_combout ), .cin(gnd), - .combout(\D[3]~95_combout ), + .combout(\D[3]~109_combout ), .cout()); // synopsys translate_off -defparam \D[3]~95 .lut_mask = 16'hBFB3; -defparam \D[3]~95 .sum_lutc_input = "datac"; +defparam \D[3]~109 .lut_mask = 16'hD0D5; +defparam \D[3]~109 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N26 -cycloneive_lcell_comb \D[3]~96 ( -// Equation(s): -// \D[3]~96_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [3] & \D[3]~95_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[3]~95_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [3]), - .datad(\D[3]~95_combout ), - .cin(gnd), - .combout(\D[3]~96_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~96 .lut_mask = 16'hF511; -defparam \D[3]~96 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N6 +// Location: LCCOMB_X28_Y12_N4 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[3]~21_combout ) # ((\D[3]~96_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[3]~96_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[3]~109_combout ) # ((\z80_|bus_control_|db[3]~21_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & +// (((\z80_|bus_control_|db[3]~21_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[3]~96_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), + .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), + .datab(\D[3]~109_combout ), + .datac(\z80_|bus_control_|db[3]~21_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hF888; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N7 +// Location: FF_X28_Y12_N5 dffeas \z80_|data_pins_|dout[3] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), @@ -53128,41 +45865,41 @@ defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N4 +// Location: LCCOMB_X28_Y12_N22 cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( // Equation(s): // \z80_|bus_control_|db[3]~20_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(\z80_|data_pins_|dout [3]), - .datac(gnd), + .dataa(gnd), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|data_pins_|dout [3]), .datad(\z80_|bus_control_|db[0]~4_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[3]~20_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hDD00; +defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hF300; defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N0 +// Location: LCCOMB_X27_Y12_N28 cycloneive_lcell_comb \z80_|bus_control_|db[3]~21 ( // Equation(s): -// \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~36_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|bus_control_|db[0]~6_combout ), + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), .datab(\z80_|bus_control_|db[3]~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|alu_control_|db[3]~36_combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[3]~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hDD5D; +defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hC4FF; defparam \z80_|bus_control_|db[3]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y10_N1 +// Location: FF_X27_Y12_N29 dffeas \z80_|ir_|opcode[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|bus_control_|db[3]~21_combout ), @@ -53181,41 +45918,7772 @@ defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( +// Location: LCCOMB_X39_Y8_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~4_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) +// \z80_|pla_decode_|Equal33~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4])) .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal52~0_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~4_combout ), + .combout(\z80_|pla_decode_|Equal33~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N20 +// Location: LCCOMB_X36_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N4 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( +// Equation(s): +// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hCECF; +defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N6 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( +// Equation(s): +// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~37_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|bus_control_|db[0]~4_combout ), + .datab(\z80_|alu_control_|db[7]~37_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'h88AA; +defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y4_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y1_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 .lut_mask = 16'hCFA0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N2 +cycloneive_lcell_comb \D[5]~97 ( +// Equation(s): +// \D[5]~97_combout = (\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|control_pins_|pin_nIORQ~1_combout ))) + + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|control_pins_|pin_nIORQ~1_combout ), + .cin(gnd), + .combout(\D[5]~97_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~97 .lut_mask = 16'h2000; +defparam \D[5]~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y21_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y3_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: M9K_X33_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~117_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y27_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N6 +cycloneive_lcell_comb \Mux0~0 ( +// Equation(s): +// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) # (!\z80_|address_pins_|abus[14]~22_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~0 .lut_mask = 16'hB9A8; +defparam \Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N4 +cycloneive_lcell_comb \Mux0~1 ( +// Equation(s): +// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datad(\Mux0~0_combout ), + .cin(gnd), + .combout(\Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~1 .lut_mask = 16'hDDA0; +defparam \Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N20 +cycloneive_lcell_comb \D[7]~116 ( +// Equation(s): +// \D[7]~116_combout = ((\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )) # (!\z80_|address_pins_|abus[15]~21_combout & ((\Mux0~1_combout )))) # (!\D[5]~97_combout ) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .datab(\D[5]~97_combout ), + .datac(\z80_|address_pins_|abus[15]~21_combout ), + .datad(\Mux0~1_combout ), + .cin(gnd), + .combout(\D[7]~116_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~116 .lut_mask = 16'hBFB3; +defparam \D[7]~116 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N26 +cycloneive_lcell_comb \D[7]~117 ( +// Equation(s): +// \D[7]~117_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\z80_|data_pins_|dout [7] & \D[7]~116_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[7]~116_combout )) # (!\Equal2~1_combout ))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [7]), + .datad(\D[7]~116_combout ), + .cin(gnd), + .combout(\D[7]~117_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~117 .lut_mask = 16'hF311; +defparam \D[7]~117 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N0 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\z80_|bus_control_|db[7]~7_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[7]~117_combout )))) # (!\z80_|bus_control_|db[7]~7_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[7]~117_combout ))) + + .dataa(\z80_|bus_control_|db[7]~7_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\D[7]~117_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N1 +dffeas \z80_|data_pins_|dout[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N20 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( +// Equation(s): +// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[7]~5_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|bus_control_|db[0]~6_combout ), + .datad(\z80_|data_pins_|dout [7]), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hAF2F; +defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N13 +dffeas \z80_|ir_|opcode[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[7]~7_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hF000; +defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~2_combout = (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~0_combout & \z80_|pla_decode_|Equal41~1_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datad(\z80_|pla_decode_|Equal41~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|pla_decode_|Equal36~0_combout & (((\z80_|pla_decode_|Equal41~2_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # +// (!\z80_|pla_decode_|Equal36~0_combout & (\z80_|pla_decode_|Equal41~2_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal36~0_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hC0EA; +defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h3222; +defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y7_N9 +dffeas \z80_|decode_state_|DFFE_instCB ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instCB~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal52~0_combout ), + .datab(\z80_|execute_|comb~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N29 +dffeas \z80_|interrupts_|im1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_im_we~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|im1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|interrupts_|im1~q ), + .datad(\z80_|interrupts_|im2~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hC4C0; +defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & +// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h4F0A; +defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_ff_oe~1_combout & (!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datac(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0203; +defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_bus_db_oe~5_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; +defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (\z80_|execute_|ctl_bus_db_oe~4_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hAAA2; +defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~88 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~88_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~88_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~88 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[6][0]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~1_combout = (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~89 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~89_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (\ula_|zx_keyboard_|keys[6][0]~88_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|shifted~1_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .datab(\ula_|zx_keyboard_|keys[6][0]~88_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|shifted~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~89 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[6][0]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|zx_keyboard_|keys[6][0]~89_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][0]~89_combout & ((\ula_|zx_keyboard_|keys[6][0]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[6][0]~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h7272; +defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y10_N23 +dffeas \ula_|zx_keyboard_|keys[6][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~84 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~84_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~84_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~84 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[7][0]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~78 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~78_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~78 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[5][0]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~85 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~85_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[5][0]~78_combout ) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[5][0]~78_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~85_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~85 .lut_mask = 16'h3300; +defparam \ula_|zx_keyboard_|keys[7][0]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~86 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~86_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[3][0]~73_combout & (\ula_|zx_keyboard_|keys[5][4]~20_combout ))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|keys[7][0]~85_combout +// )))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~73_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~20_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|keys[7][0]~85_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~86 .lut_mask = 16'h8F80; +defparam \ula_|zx_keyboard_|keys[7][0]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[7][0]~84_combout & ((\ula_|zx_keyboard_|keys[7][0]~86_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][0]~86_combout & ((\ula_|zx_keyboard_|keys[7][0]~q +// ))))) # (!\ula_|zx_keyboard_|keys[7][0]~84_combout & (((\ula_|zx_keyboard_|keys[7][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][0]~84_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[7][0]~q ), + .datad(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y10_N1 +dffeas \ula_|zx_keyboard_|keys[7][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N28 +cycloneive_lcell_comb \D[0]~57 ( +// Equation(s): +// \D[0]~57_combout = (\ula_|zx_keyboard_|keys[6][0]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\ula_|zx_keyboard_|keys[6][0]~q & +// (((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][0]~q ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[15]~21_combout ), + .datad(\ula_|zx_keyboard_|keys[7][0]~q ), + .cin(gnd), + .combout(\D[0]~57_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~57 .lut_mask = 16'hD0DD; +defparam \D[0]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~81 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~81_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [5]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & +// (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [5])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~81_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~81 .lut_mask = 16'h1024; +defparam \ula_|zx_keyboard_|keys[4][0]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~82 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~82_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~82_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~82 .lut_mask = 16'hF0FA; +defparam \ula_|zx_keyboard_|keys[4][0]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y7_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~40 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~40_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][1]~39_combout & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~40 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[5][1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~83 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~83_combout = (\ula_|zx_keyboard_|keys[4][0]~81_combout & ((\ula_|zx_keyboard_|keys[5][1]~40_combout & (!\ula_|zx_keyboard_|keys[4][0]~82_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~40_combout & +// ((\ula_|zx_keyboard_|keys[4][0]~q ))))) # (!\ula_|zx_keyboard_|keys[4][0]~81_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][0]~81_combout ), + .datab(\ula_|zx_keyboard_|keys[4][0]~82_combout ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~40_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~83_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~83 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][0]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y8_N23 +dffeas \ula_|zx_keyboard_|keys[4][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][0]~83_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~79 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~79_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (((!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[5][0]~78_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & +// ((\ula_|zx_keyboard_|keys[3][0]~73_combout ) # (\ula_|zx_keyboard_|keys[5][0]~78_combout )))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~73_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|zx_keyboard_|keys[5][0]~78_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~79_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~79 .lut_mask = 16'h3C20; +defparam \ula_|zx_keyboard_|keys[5][0]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~80 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~80_combout = (\ula_|zx_keyboard_|keys[6][1]~32_combout & ((\ula_|zx_keyboard_|keys[5][0]~79_combout & (!\ula_|zx_keyboard_|keys[5][0]~62_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~79_combout & +// ((\ula_|zx_keyboard_|keys[5][0]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~32_combout & (((\ula_|zx_keyboard_|keys[5][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~62_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~32_combout ), + .datac(\ula_|zx_keyboard_|keys[5][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][0]~79_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~80 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[5][0]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y9_N15 +dffeas \ula_|zx_keyboard_|keys[5][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N2 +cycloneive_lcell_comb \D[0]~56 ( +// Equation(s): +// \D[0]~56_combout = (\z80_|address_pins_|abus[13]~23_combout & ((\z80_|address_pins_|abus[12]~24_combout ) # ((!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\z80_|address_pins_|abus[13]~23_combout & (!\ula_|zx_keyboard_|keys[5][0]~q & +// ((\z80_|address_pins_|abus[12]~24_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~23_combout ), + .datab(\z80_|address_pins_|abus[12]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][0]~q ), + .cin(gnd), + .combout(\D[0]~56_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~56 .lut_mask = 16'h8ACF; +defparam \D[0]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~76 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~76_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~21_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~76_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~76 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[1][0]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~77 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~77_combout = (\ula_|zx_keyboard_|keys[1][0]~76_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][0]~76_combout & ((\ula_|zx_keyboard_|keys[1][0]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[1][0]~q ), + .datad(\ula_|zx_keyboard_|keys[1][0]~76_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~77_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~77 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[1][0]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N23 +dffeas \ula_|zx_keyboard_|keys[1][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][0]~77_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~68 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~68_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~68_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~68 .lut_mask = 16'hC0C0; +defparam \ula_|zx_keyboard_|keys[4][3]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [2] & ((!\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & +// \ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0130; +defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~69 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~69_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|zx_keyboard_|WideOr0~0_combout )) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|keys[6][4]~43_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[6][4]~43_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~69_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~69 .lut_mask = 16'h2777; +defparam \ula_|zx_keyboard_|keys~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~70 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~70_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][3]~68_combout & !\ula_|zx_keyboard_|keys~69_combout )) # (!\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .datab(\ula_|zx_keyboard_|keys[4][3]~68_combout ), + .datac(\ula_|zx_keyboard_|keys~69_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~70_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~70 .lut_mask = 16'h08AA; +defparam \ula_|zx_keyboard_|keys[0][0]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~27 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~27_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~27 .lut_mask = 16'h3030; +defparam \ula_|zx_keyboard_|keys[4][1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & +// (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'hC002; +defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~71 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~71_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|WideOr4~0_combout )) # (!\ula_|zx_keyboard_|keys[4][1]~27_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[4][1]~27_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|WideOr4~0_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~71_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~71 .lut_mask = 16'h3313; +defparam \ula_|zx_keyboard_|keys~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~72 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~72_combout = (\ula_|zx_keyboard_|keys[0][0]~70_combout & ((\ula_|zx_keyboard_|keys~71_combout & ((\ula_|zx_keyboard_|keys[0][0]~q ))) # (!\ula_|zx_keyboard_|keys~71_combout & (!\ula_|zx_keyboard_|released~q )))) # +// (!\ula_|zx_keyboard_|keys[0][0]~70_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~70_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[0][0]~q ), + .datad(\ula_|zx_keyboard_|keys~71_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~72_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~72 .lut_mask = 16'hF072; +defparam \ula_|zx_keyboard_|keys[0][0]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y8_N11 +dffeas \ula_|zx_keyboard_|keys[0][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][0]~72_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~2_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # ((!\ula_|zx_keyboard_|keys[0][0]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [8]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hAFFF; +defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~22 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~22_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~21_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~22 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|keys[2][1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~75 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][0]~75_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~22_combout & (!\ula_|zx_keyboard_|released~q )) # +// (!\ula_|zx_keyboard_|keys[2][1]~22_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~22_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][0]~75_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0]~75 .lut_mask = 16'hD1F0; +defparam \ula_|zx_keyboard_|keys[2][0]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N15 +dffeas \ula_|zx_keyboard_|keys[2][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][0]~75_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~24 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~24_combout = (\ula_|zx_keyboard_|keys[7][1]~19_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~20_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~19_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|zx_keyboard_|keys[5][4]~20_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~24 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[3][1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~74 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~74_combout = (\ula_|zx_keyboard_|keys[3][0]~73_combout & ((\ula_|zx_keyboard_|keys[3][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~24_combout & ((\ula_|zx_keyboard_|keys[3][0]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][0]~73_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][0]~73_combout ), + .datac(\ula_|zx_keyboard_|keys[3][0]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~24_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~74_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~74 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][0]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N17 +dffeas \ula_|zx_keyboard_|keys[3][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][0]~74_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N0 +cycloneive_lcell_comb \D[0]~54 ( +// Equation(s): +// \D[0]~54_combout = (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][0]~q )))) # (!\z80_|address_pins_|abus[10]~20_combout & (!\ula_|zx_keyboard_|keys[2][0]~q & +// ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][0]~q )))) + + .dataa(\z80_|address_pins_|abus[10]~20_combout ), + .datab(\z80_|address_pins_|abus[11]~19_combout ), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|keys[3][0]~q ), + .cin(gnd), + .combout(\D[0]~54_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~54 .lut_mask = 16'h8CAF; +defparam \D[0]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N12 +cycloneive_lcell_comb \D[0]~55 ( +// Equation(s): +// \D[0]~55_combout = (\ula_|zx_keyboard_|key_row~2_combout & (\D[0]~54_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][0]~q ), + .datab(\z80_|address_pins_|abus[9]~17_combout ), + .datac(\ula_|zx_keyboard_|key_row~2_combout ), + .datad(\D[0]~54_combout ), + .cin(gnd), + .combout(\D[0]~55_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~55 .lut_mask = 16'hD000; +defparam \D[0]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N0 +cycloneive_lcell_comb \D[0]~58 ( +// Equation(s): +// \D[0]~58_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~57_combout & (\D[0]~56_combout & \D[0]~55_combout ))) + + .dataa(\D[0]~57_combout ), + .datab(\D[0]~56_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[0]~55_combout ), + .cin(gnd), + .combout(\D[0]~58_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~58 .lut_mask = 16'hF8F0; +defparam \D[0]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N12 +cycloneive_lcell_comb \D[0]~62 ( +// Equation(s): +// \D[0]~62_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .cin(gnd), + .combout(\D[0]~62_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~62 .lut_mask = 16'hEC64; +defparam \D[0]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N8 +cycloneive_lcell_comb \D[0]~63 ( +// Equation(s): +// \D[0]~63_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~62_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~62_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # (!\D[0]~62_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[0]~62_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\D[0]~63_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~63 .lut_mask = 16'hE3E0; +defparam \D[0]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y29_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y4_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N6 +cycloneive_lcell_comb \D[0]~59 ( +// Equation(s): +// \D[0]~59_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout & +// (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .cin(gnd), + .combout(\D[0]~59_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~59 .lut_mask = 16'hE6A2; +defparam \D[0]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y29_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~65_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y11_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N28 +cycloneive_lcell_comb \D[0]~60 ( +// Equation(s): +// \D[0]~60_combout = (\z80_|address_pins_|abus[15]~21_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout $ (\D[0]~59_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & +// (\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout & ((!\D[0]~59_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datac(\z80_|address_pins_|abus[15]~21_combout ), + .datad(\D[0]~59_combout ), + .cin(gnd), + .combout(\D[0]~60_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~60 .lut_mask = 16'h30CA; +defparam \D[0]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N10 +cycloneive_lcell_comb \D[0]~61 ( +// Equation(s): +// \D[0]~61_combout = (\D[0]~59_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & !\D[0]~60_combout )))) # (!\D[0]~59_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~60_combout )))) + + .dataa(\D[0]~59_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datad(\D[0]~60_combout ), + .cin(gnd), + .combout(\D[0]~61_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~61 .lut_mask = 16'h99A8; +defparam \D[0]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N18 +cycloneive_lcell_comb \D[0]~120 ( +// Equation(s): +// \D[0]~120_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[0]~63_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[0]~61_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[0]~63_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\D[0]~63_combout ), + .datad(\D[0]~61_combout ), + .cin(gnd), + .combout(\D[0]~120_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~120 .lut_mask = 16'hF4B0; +defparam \D[0]~120 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N26 +cycloneive_lcell_comb \D[0]~64 ( +// Equation(s): +// \D[0]~64_combout = ((\Equal2~0_combout & (\D[0]~58_combout )) # (!\Equal2~0_combout & ((\D[0]~120_combout )))) # (!\Equal2~1_combout ) + + .dataa(\D[0]~58_combout ), + .datab(\Equal2~0_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[0]~120_combout ), + .cin(gnd), + .combout(\D[0]~64_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~64 .lut_mask = 16'hBF8F; +defparam \D[0]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N16 +cycloneive_lcell_comb \D[0]~65 ( +// Equation(s): +// \D[0]~65_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [0] & (\D[0]~64_combout ))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[0]~64_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [0]), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\D[0]~64_combout ), + .datad(\Equal2~1_combout ), + .cin(gnd), + .combout(\D[0]~65_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~65 .lut_mask = 16'hB0B3; +defparam \D[0]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N26 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\D[0]~65_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[0]~17_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[0]~65_combout & +// (((\z80_|bus_control_|db[0]~17_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) + + .dataa(\D[0]~65_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|bus_control_|db[0]~17_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N27 +dffeas \z80_|data_pins_|dout[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N30 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( +// Equation(s): +// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|bus_control_|db[0]~4_combout ), + .datad(\z80_|data_pins_|dout [0]), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'hF030; +defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N12 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( +// Equation(s): +// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~14_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~16_combout ), + .datab(\z80_|alu_control_|db[0]~14_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'h8AFF; +defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N19 +dffeas \z80_|ir_|opcode[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[0]~17_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal3~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal3~2_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pla_decode_|Equal3~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y7_N31 +dffeas \z80_|decode_state_|DFFE_instIY1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_iy_set~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instIY1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N16 +cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( +// Equation(s): +// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|decode_state_|DFFE_instIY1~q ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|decode_state_|use_ixiy~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFFF0; +defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( +// Equation(s): +// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~9_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~8_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; +defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( +// Equation(s): +// \z80_|execute_|ixy_d~13_combout = (\z80_|execute_|ixy_d~16_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|pla_decode_|Equal41~2_combout )) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ixy_d~10_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( +// Equation(s): +// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~5_combout & (((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )))) # (!\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ixy_d~12_combout ) # +// ((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ixy_d~12_combout ), + .datac(\z80_|execute_|ixy_d~13_combout ), + .datad(\z80_|execute_|ixy_d~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h4F44; +defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( +// Equation(s): +// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|sequencer_|DFFE_T5_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hAA8A; +defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( +// Equation(s): +// \z80_|execute_|ixy_d~15_combout = ((\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal49~0_combout & \z80_|execute_|ixy_d~11_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|ixy_d~14_combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|execute_|ixy_d~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'hB333; +defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~9_combout = (\z80_|execute_|ctl_flags_xy_we~8_combout & (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h0070; +defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~12_combout = ((\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_ir_we~12_combout ) # (\z80_|execute_|ctl_ir_we~11_combout )))) # (!\z80_|execute_|ctl_alu_oe~6_combout ) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hBBB3; +defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_alu_oe~11_combout ) # ((\z80_|execute_|ctl_alu_oe~12_combout ) # (!\z80_|execute_|ctl_alu_oe~8_combout ))) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~11_combout ), + .datac(\z80_|execute_|ctl_alu_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~14_combout = ((\z80_|execute_|ctl_alu_oe~13_combout ) # ((!\z80_|execute_|ctl_alu_oe~10_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~9_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~13_combout ), + .datac(\z80_|execute_|ctl_flags_alu~14_combout ), + .datad(\z80_|execute_|ctl_alu_oe~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N6 +cycloneive_lcell_comb \z80_|alu_|db[7]~9 ( +// Equation(s): +// \z80_|alu_|db[7]~9_combout = (\z80_|execute_|ctl_alu_oe~14_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (\z80_|execute_|ctl_reg_out_hi~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~9 .lut_mask = 16'hFFFC; +defparam \z80_|alu_|db[7]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N0 +cycloneive_lcell_comb \z80_|alu_|db[1]~15 ( +// Equation(s): +// \z80_|alu_|db[1]~15_combout = (\z80_|alu_control_|db[1]~27_combout & (((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[1]~27_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[1]~21_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) + + .dataa(\z80_|alu_control_|db[1]~27_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~15 .lut_mask = 16'hB0BB; +defparam \z80_|alu_|db[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N14 +cycloneive_lcell_comb \z80_|alu_|db[1]~16 ( +// Equation(s): +// \z80_|alu_|db[1]~16_combout = ((\z80_|alu_|db[1]~15_combout & ((\z80_|alu_|db_low[1]~20_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[7]~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~14_combout ), + .datac(\z80_|alu_|db_low[1]~20_combout ), + .datad(\z80_|alu_|db[1]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~16 .lut_mask = 16'hF755; +defparam \z80_|alu_|db[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( +// Equation(s): +// \z80_|alu_control_|db[1]~25_combout = (\z80_|alu_|db[1]~16_combout & (\z80_|execute_|ctl_flags_oe~2_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) # (!\z80_|alu_|db[1]~16_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((\z80_|execute_|ctl_flags_oe~2_combout & !\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) + + .dataa(\z80_|alu_|db[1]~16_combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h50DC; +defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( +// Equation(s): +// \z80_|alu_control_|db[1]~26_combout = (!\z80_|alu_control_|db[1]~25_combout & (\z80_|alu_control_|db[2]~24_combout & ((\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|alu_control_|db[1]~25_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .datad(\z80_|alu_control_|db[2]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h5100; +defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N6 +cycloneive_lcell_comb \z80_|sw1_|db_down[1]~2 ( +// Equation(s): +// \z80_|sw1_|db_down[1]~2_combout = ((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) + + .dataa(\z80_|bus_control_|db[1]~11_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datad(\z80_|execute_|ctl_sw_1d~7_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[1]~2 .lut_mask = 16'h0AFF; +defparam \z80_|sw1_|db_down[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~27 ( +// Equation(s): +// \z80_|alu_control_|db[1]~27_combout = ((\z80_|alu_control_|db[1]~26_combout & \z80_|sw1_|db_down[1]~2_combout )) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(gnd), + .datab(\z80_|alu_control_|db[1]~26_combout ), + .datac(\z80_|alu_control_|db[6]~13_combout ), + .datad(\z80_|sw1_|db_down[1]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~27 .lut_mask = 16'hCF0F; +defparam \z80_|alu_control_|db[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N12 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( +// Equation(s): +// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~27_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|alu_control_|db[1]~27_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[0]~4_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hBB00; +defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~38_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'hFAF0; +defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~41 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~41_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~41 .lut_mask = 16'h0005; +defparam \ula_|zx_keyboard_|keys[5][1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~42 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~42_combout = (\ula_|zx_keyboard_|keys[5][1]~41_combout & ((\ula_|zx_keyboard_|keys[5][1]~40_combout & (!\ula_|zx_keyboard_|keys[5][1]~38_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~40_combout & +// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~41_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~38_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~41_combout ), + .datac(\ula_|zx_keyboard_|keys[5][1]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~40_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~42 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[5][1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y8_N9 +dffeas \ula_|zx_keyboard_|keys[5][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][1]~42_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y10_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~30 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~30_combout = (\ula_|zx_keyboard_|keys[5][2]~29_combout & ((\ula_|zx_keyboard_|keys[4][1]~27_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][1]~27_combout & ((\ula_|zx_keyboard_|keys[4][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~29_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~29_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][1]~q ), + .datad(\ula_|zx_keyboard_|keys[4][1]~27_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~30 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y10_N9 +dffeas \ula_|zx_keyboard_|keys[4][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][1]~30_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~0_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # ((!\ula_|zx_keyboard_|keys[4][1]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [12]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|zx_keyboard_|keys[4][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hCFFF; +defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y10_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~36 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~36_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|scan_code_ready~q & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~36 .lut_mask = 16'h0010; +defparam \ula_|zx_keyboard_|keys[7][1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~3_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & +// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h444A; +defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [0] & +// (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~0 .lut_mask = 16'h0120; +defparam \ula_|zx_keyboard_|WideOr16~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~2_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~1_combout & (!\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|zx_keyboard_|WideOr16~1_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|WideOr16~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'hF202; +defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~4_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~2_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~3_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|WideOr16~3_combout ), + .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'hEA40; +defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~37 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~37_combout = (\ula_|zx_keyboard_|keys[7][1]~36_combout & ((\ula_|zx_keyboard_|WideOr16~4_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~4_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # +// (!\ula_|zx_keyboard_|keys[7][1]~36_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[7][1]~36_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~q ), + .datad(\ula_|zx_keyboard_|WideOr16~4_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~37 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[7][1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y10_N25 +dffeas \ula_|zx_keyboard_|keys[7][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][1]~37_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~33 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~33_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & +// (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~33 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[6][1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~34 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~34_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|zx_keyboard_|keys[6][1]~33_combout & \ula_|zx_keyboard_|keys[6][1]~32_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|zx_keyboard_|keys[6][1]~33_combout ), + .datad(\ula_|zx_keyboard_|keys[6][1]~32_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~34 .lut_mask = 16'hC000; +defparam \ula_|zx_keyboard_|keys[6][1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~31 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~31_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|shifted~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~31 .lut_mask = 16'hFCF0; +defparam \ula_|zx_keyboard_|keys[6][1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~35 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~35_combout = (\ula_|zx_keyboard_|keys[6][1]~34_combout & ((!\ula_|zx_keyboard_|keys[6][1]~31_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~34_combout & (\ula_|zx_keyboard_|keys[6][1]~q )) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~34_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[6][1]~q ), + .datad(\ula_|zx_keyboard_|keys[6][1]~31_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~35 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[6][1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y9_N31 +dffeas \ula_|zx_keyboard_|keys[6][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][1]~35_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N28 +cycloneive_lcell_comb \D[1]~32 ( +// Equation(s): +// \D[1]~32_combout = (\ula_|zx_keyboard_|keys[7][1]~q & (\z80_|address_pins_|abus[15]~21_combout & ((\z80_|address_pins_|abus[14]~22_combout ) # (!\ula_|zx_keyboard_|keys[6][1]~q )))) # (!\ula_|zx_keyboard_|keys[7][1]~q & +// ((\z80_|address_pins_|abus[14]~22_combout ) # ((!\ula_|zx_keyboard_|keys[6][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~q ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\ula_|zx_keyboard_|keys[6][1]~q ), + .datad(\z80_|address_pins_|abus[15]~21_combout ), + .cin(gnd), + .combout(\D[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~32 .lut_mask = 16'hCF45; +defparam \D[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N12 +cycloneive_lcell_comb \D[1]~33 ( +// Equation(s): +// \D[1]~33_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~32_combout & ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~q ), + .datac(\ula_|zx_keyboard_|key_row~0_combout ), + .datad(\D[1]~32_combout ), + .cin(gnd), + .combout(\D[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~33 .lut_mask = 16'hB000; +defparam \D[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~16 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~16_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~16 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[6][4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~17 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~17_combout = (\ula_|zx_keyboard_|keys[6][4]~16_combout & (\ula_|zx_keyboard_|keys[7][4]~15_combout & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~16_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~15_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~17 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[1][1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~18 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~18_combout = (\ula_|zx_keyboard_|keys[1][1]~17_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][1]~17_combout & ((\ula_|zx_keyboard_|keys[1][1]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[1][1]~17_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[1][1]~q ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~18 .lut_mask = 16'h7272; +defparam \ula_|zx_keyboard_|keys[1][1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y9_N9 +dffeas \ula_|zx_keyboard_|keys[1][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][1]~18_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~12 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~12_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~12 .lut_mask = 16'h0048; +defparam \ula_|zx_keyboard_|keys[0][1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~13 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~13_combout = (\ula_|zx_keyboard_|keys[0][1]~12_combout & ((\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [4] & +// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~13 .lut_mask = 16'h2400; +defparam \ula_|zx_keyboard_|keys[0][1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~10 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~10_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|shifted~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~10 .lut_mask = 16'hF0F3; +defparam \ula_|zx_keyboard_|keys[0][1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~13_combout & ((!\ula_|zx_keyboard_|keys[0][1]~10_combout ))) # (!\ula_|zx_keyboard_|keys[0][1]~13_combout & +// (\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~0_combout ), + .datab(\ula_|zx_keyboard_|keys[0][1]~13_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\ula_|zx_keyboard_|keys[0][1]~10_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y9_N21 +dffeas \ula_|zx_keyboard_|keys[0][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N16 +cycloneive_lcell_comb \D[1]~30 ( +// Equation(s): +// \D[1]~30_combout = (\ula_|zx_keyboard_|keys[1][1]~q & (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|keys[1][1]~q & +// (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[1][1]~q ), + .datab(\ula_|zx_keyboard_|keys[0][1]~q ), + .datac(\z80_|address_pins_|abus[9]~17_combout ), + .datad(\z80_|address_pins_|abus[8]~18_combout ), + .cin(gnd), + .combout(\D[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~30 .lut_mask = 16'hF531; +defparam \D[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~25 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~25 .lut_mask = 16'h3000; +defparam \ula_|zx_keyboard_|keys[3][1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~26 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~26_combout = (\ula_|zx_keyboard_|keys[3][1]~25_combout & ((\ula_|zx_keyboard_|keys[3][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~24_combout & ((\ula_|zx_keyboard_|keys[3][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~25_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][1]~25_combout ), + .datac(\ula_|zx_keyboard_|keys[3][1]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~24_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~26 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N31 +dffeas \ula_|zx_keyboard_|keys[3][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~23 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~23_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~22_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~22_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # +// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[2][1]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~22_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~23 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[2][1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N21 +dffeas \ula_|zx_keyboard_|keys[2][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][1]~23_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N8 +cycloneive_lcell_comb \D[1]~31 ( +// Equation(s): +// \D[1]~31_combout = (\z80_|address_pins_|abus[10]~20_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # ((!\ula_|zx_keyboard_|keys[3][1]~q )))) # (!\z80_|address_pins_|abus[10]~20_combout & (!\ula_|zx_keyboard_|keys[2][1]~q & +// ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\z80_|address_pins_|abus[10]~20_combout ), + .datab(\z80_|address_pins_|abus[11]~19_combout ), + .datac(\ula_|zx_keyboard_|keys[3][1]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~q ), + .cin(gnd), + .combout(\D[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~31 .lut_mask = 16'h8ACF; +defparam \D[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y9_N6 +cycloneive_lcell_comb \D[1]~34 ( +// Equation(s): +// \D[1]~34_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~33_combout & (\D[1]~30_combout & \D[1]~31_combout ))) + + .dataa(\D[1]~33_combout ), + .datab(\D[1]~30_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[1]~31_combout ), + .cin(gnd), + .combout(\D[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~34 .lut_mask = 16'hF8F0; +defparam \D[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N22 +cycloneive_lcell_comb \D[1]~38 ( +// Equation(s): +// \D[1]~38_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .cin(gnd), + .combout(\D[1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~38 .lut_mask = 16'hE6A2; +defparam \D[1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N4 +cycloneive_lcell_comb \D[1]~39 ( +// Equation(s): +// \D[1]~39_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[1]~38_combout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\D[1]~38_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\D[1]~38_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datac(\D[1]~38_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .cin(gnd), + .combout(\D[1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~39 .lut_mask = 16'hE5E0; +defparam \D[1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y2_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +// synopsys translate_on + +// Location: M9K_X22_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +// synopsys translate_on + +// Location: M9K_X22_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~41_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N24 +cycloneive_lcell_comb \D[1]~35 ( +// Equation(s): +// \D[1]~35_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout & +// (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .cin(gnd), + .combout(\D[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~35 .lut_mask = 16'hEA62; +defparam \D[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N14 +cycloneive_lcell_comb \D[1]~36 ( +// Equation(s): +// \D[1]~36_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout $ (((\D[1]~35_combout ))))) # (!\z80_|address_pins_|abus[15]~21_combout & +// (((\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout & !\D[1]~35_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datad(\D[1]~35_combout ), + .cin(gnd), + .combout(\D[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~36 .lut_mask = 16'h44B8; +defparam \D[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N0 +cycloneive_lcell_comb \D[1]~37 ( +// Equation(s): +// \D[1]~37_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[1]~35_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[1]~36_combout & ((!\D[1]~35_combout ))) # (!\D[1]~36_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout & \D[1]~35_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datac(\D[1]~36_combout ), + .datad(\D[1]~35_combout ), + .cin(gnd), + .combout(\D[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~37 .lut_mask = 16'hAE50; +defparam \D[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N20 +cycloneive_lcell_comb \D[1]~118 ( +// Equation(s): +// \D[1]~118_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[1]~39_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[1]~37_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (\D[1]~39_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\D[1]~39_combout ), + .datad(\D[1]~37_combout ), + .cin(gnd), + .combout(\D[1]~118_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~118 .lut_mask = 16'hF4B0; +defparam \D[1]~118 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N2 +cycloneive_lcell_comb \D[1]~40 ( +// Equation(s): +// \D[1]~40_combout = ((\Equal2~0_combout & (\D[1]~34_combout )) # (!\Equal2~0_combout & ((\D[1]~118_combout )))) # (!\Equal2~1_combout ) + + .dataa(\D[1]~34_combout ), + .datab(\Equal2~0_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[1]~118_combout ), + .cin(gnd), + .combout(\D[1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~40 .lut_mask = 16'hBF8F; +defparam \D[1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N12 +cycloneive_lcell_comb \D[1]~41 ( +// Equation(s): +// \D[1]~41_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~40_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[1]~40_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [1]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[1]~40_combout ), + .cin(gnd), + .combout(\D[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~41 .lut_mask = 16'hAF03; +defparam \D[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N28 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\D[1]~41_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[1]~11_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[1]~41_combout & +// (((\z80_|bus_control_|db[1]~11_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) + + .dataa(\D[1]~41_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|bus_control_|db[1]~11_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N29 +dffeas \z80_|data_pins_|dout[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N8 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~11 ( +// Equation(s): +// \z80_|bus_control_|db[1]~11_combout = ((\z80_|bus_control_|db[1]~10_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[1]~10_combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\z80_|bus_control_|db[0]~6_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'h8FAF; +defparam \z80_|bus_control_|db[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N9 +dffeas \z80_|ir_|opcode[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[1]~11_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_ed_set~combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|pla_decode_|Equal2~1_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y7_N29 +dffeas \z80_|decode_state_|DFFE_instED ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instED~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y6_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; +defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~8_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal9~0_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~8_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y7_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal8~0_combout & \z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_iorw~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFAEA; +defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~8_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h00C8; +defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~6_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC888; +defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~6_combout = (\z80_|execute_|ctl_bus_db_we~4_combout ) # (((!\z80_|execute_|ctl_sw_2u~3_combout ) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) + + .dataa(\z80_|execute_|ctl_bus_db_we~4_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|execute_|ctl_sw_2u~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~2_combout ) # ((\z80_|execute_|ctl_bus_db_we~3_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # (\z80_|execute_|ctl_bus_db_we~6_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~2_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~3_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~126 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~126_combout = (\ula_|zx_keyboard_|keys[6][4]~16_combout & ((\ula_|zx_keyboard_|keys[6][4]~44_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~44_combout & ((\ula_|zx_keyboard_|keys[6][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~16_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~16_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~44_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~126_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~126 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[6][4]~126 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y9_N1 +dffeas \ula_|zx_keyboard_|keys[6][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][4]~126_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~125 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~125_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~48_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~48_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) +// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|shifted~1_combout ), + .datac(\ula_|zx_keyboard_|keys[7][4]~q ), + .datad(\ula_|zx_keyboard_|keys[7][4]~48_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~125_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~125 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[7][4]~125 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N11 +dffeas \ula_|zx_keyboard_|keys[7][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][4]~125_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N16 +cycloneive_lcell_comb \D[4]~88 ( +// Equation(s): +// \D[4]~88_combout = (\ula_|zx_keyboard_|keys[6][4]~q & (\z80_|address_pins_|abus[14]~22_combout & ((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][4]~q )))) # (!\ula_|zx_keyboard_|keys[6][4]~q & +// (((\z80_|address_pins_|abus[15]~21_combout ) # (!\ula_|zx_keyboard_|keys[7][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~q ), + .datab(\z80_|address_pins_|abus[14]~22_combout ), + .datac(\z80_|address_pins_|abus[15]~21_combout ), + .datad(\ula_|zx_keyboard_|keys[7][4]~q ), + .cin(gnd), + .combout(\D[4]~88_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~88 .lut_mask = 16'hD0DD; +defparam \D[4]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~120 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~120_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~120_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~120 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[5][4]~120 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~121 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~121_combout = (\ula_|zx_keyboard_|keys[6][4]~44_combout & ((\ula_|zx_keyboard_|keys[5][4]~120_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~120_combout & (\ula_|zx_keyboard_|keys[5][4]~q +// )))) # (!\ula_|zx_keyboard_|keys[6][4]~44_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~44_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~120_combout ), + .datac(\ula_|zx_keyboard_|keys[5][4]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~121_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~121 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][4]~121 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y9_N31 +dffeas \ula_|zx_keyboard_|keys[5][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][4]~121_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~122 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q )) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & +// \ula_|zx_keyboard_|extended~q )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~122_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~122 .lut_mask = 16'h300C; +defparam \ula_|zx_keyboard_|keys[4][4]~122 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~123 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~123_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[4][4]~122_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[4][4]~122_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~123_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~123 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][4]~123 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|zx_keyboard_|keys[0][0]~11_combout & ((\ula_|zx_keyboard_|keys[4][4]~123_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~123_combout & ((\ula_|zx_keyboard_|keys[4][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~11_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[0][0]~11_combout ), + .datac(\ula_|zx_keyboard_|keys[4][4]~q ), + .datad(\ula_|zx_keyboard_|keys[4][4]~123_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y9_N9 +dffeas \ula_|zx_keyboard_|keys[4][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N28 +cycloneive_lcell_comb \D[4]~87 ( +// Equation(s): +// \D[4]~87_combout = (\z80_|address_pins_|abus[12]~24_combout & ((\z80_|address_pins_|abus[13]~23_combout ) # ((!\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\z80_|address_pins_|abus[12]~24_combout & (!\ula_|zx_keyboard_|keys[4][4]~q & +// ((\z80_|address_pins_|abus[13]~23_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\z80_|address_pins_|abus[12]~24_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[5][4]~q ), + .datad(\ula_|zx_keyboard_|keys[4][4]~q ), + .cin(gnd), + .combout(\D[4]~87_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~87 .lut_mask = 16'h8ACF; +defparam \D[4]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~115 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~115_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [5] & +// (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~115_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~115 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[2][4]~115 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~116 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~116_combout = (\ula_|zx_keyboard_|keys[5][1]~39_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[2][4]~115_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~39_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|keys[2][4]~115_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~116_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~116 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[2][4]~116 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~117 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~117_combout = (\ula_|zx_keyboard_|keys[2][4]~116_combout & (!\ula_|zx_keyboard_|keys[2][4]~93_combout )) # (!\ula_|zx_keyboard_|keys[2][4]~116_combout & ((\ula_|zx_keyboard_|keys[2][4]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[2][4]~93_combout ), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~116_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~117_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~117 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[2][4]~117 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y8_N25 +dffeas \ula_|zx_keyboard_|keys[2][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][4]~117_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][4]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [10]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[2][4]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hDDFF; +defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~118 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~118_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~118_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~118 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|keys[3][4]~118 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~131 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~131_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[3][4]~118_combout & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[3][4]~118_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~131_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~131 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[3][4]~131 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~119 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~119_combout = (\ula_|zx_keyboard_|keys[3][4]~127_combout & ((\ula_|zx_keyboard_|keys[3][4]~131_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~131_combout & ((\ula_|zx_keyboard_|keys[3][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~127_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][4]~127_combout ), + .datac(\ula_|zx_keyboard_|keys[3][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~131_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~119_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~119 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][4]~119 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y9_N21 +dffeas \ula_|zx_keyboard_|keys[3][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][4]~119_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~114 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~114_combout = (\ula_|zx_keyboard_|keys[0][4]~95_combout & ((\ula_|zx_keyboard_|keys[3][1]~25_combout & (!\ula_|zx_keyboard_|keys[0][4]~108_combout )) # (!\ula_|zx_keyboard_|keys[3][1]~25_combout & +// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[0][4]~95_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~108_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~95_combout ), + .datac(\ula_|zx_keyboard_|keys[0][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~25_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~114_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~114 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[0][4]~114 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y8_N21 +dffeas \ula_|zx_keyboard_|keys[0][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][4]~114_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y8_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~113 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~113_combout = (\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~21_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][4]~21_combout & ((\ula_|zx_keyboard_|keys[1][4]~q ))))) # +// (!\ula_|zx_keyboard_|Equal0~2_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|Equal0~2_combout ), + .datac(\ula_|zx_keyboard_|keys[1][4]~q ), + .datad(\ula_|zx_keyboard_|keys[1][4]~21_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~113_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~113 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[1][4]~113 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y8_N15 +dffeas \ula_|zx_keyboard_|keys[1][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][4]~113_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y8_N6 +cycloneive_lcell_comb \D[4]~85 ( +// Equation(s): +// \D[4]~85_combout = (\z80_|address_pins_|abus[9]~17_combout & (((\z80_|address_pins_|abus[8]~18_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~q ))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][4]~q & +// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\z80_|address_pins_|abus[9]~17_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~q ), + .datac(\z80_|address_pins_|abus[8]~18_combout ), + .datad(\ula_|zx_keyboard_|keys[1][4]~q ), + .cin(gnd), + .combout(\D[4]~85_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~85 .lut_mask = 16'hA2F3; +defparam \D[4]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y11_N20 +cycloneive_lcell_comb \D[4]~86 ( +// Equation(s): +// \D[4]~86_combout = (\ula_|zx_keyboard_|key_row~3_combout & (\D[4]~85_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][4]~q )))) + + .dataa(\ula_|zx_keyboard_|key_row~3_combout ), + .datab(\z80_|address_pins_|abus[11]~19_combout ), + .datac(\ula_|zx_keyboard_|keys[3][4]~q ), + .datad(\D[4]~85_combout ), + .cin(gnd), + .combout(\D[4]~86_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~86 .lut_mask = 16'h8A00; +defparam \D[4]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N24 +cycloneive_lcell_comb \D[4]~89 ( +// Equation(s): +// \D[4]~89_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~88_combout & (\D[4]~87_combout & \D[4]~86_combout ))) + + .dataa(\D[4]~88_combout ), + .datab(\D[4]~87_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[4]~86_combout ), + .cin(gnd), + .combout(\D[4]~89_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~89 .lut_mask = 16'hF8F0; +defparam \D[4]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N18 +cycloneive_lcell_comb \D[4]~93 ( +// Equation(s): +// \D[4]~93_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), + .cin(gnd), + .combout(\D[4]~93_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~93 .lut_mask = 16'hF838; +defparam \D[4]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N4 +cycloneive_lcell_comb \D[4]~94 ( +// Equation(s): +// \D[4]~94_combout = (\D[4]~93_combout & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )))) # (!\D[4]~93_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datab(\D[4]~93_combout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), + .cin(gnd), + .combout(\D[4]~94_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~94 .lut_mask = 16'hCEC2; +defparam \D[4]~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y22_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X22_Y21_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~111_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y33_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N8 +cycloneive_lcell_comb \D[4]~90 ( +// Equation(s): +// \D[4]~90_combout = (\z80_|address_pins_|abus[14]~22_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~22_combout +// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .cin(gnd), + .combout(\D[4]~90_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~90 .lut_mask = 16'hE6A2; +defparam \D[4]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y30_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N22 +cycloneive_lcell_comb \D[4]~91 ( +// Equation(s): +// \D[4]~91_combout = (\z80_|address_pins_|abus[15]~21_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout $ ((\D[4]~90_combout )))) # (!\z80_|address_pins_|abus[15]~21_combout & (((!\D[4]~90_combout & +// \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\D[4]~90_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .cin(gnd), + .combout(\D[4]~91_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~91 .lut_mask = 16'h4B48; +defparam \D[4]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N28 +cycloneive_lcell_comb \D[4]~92 ( +// Equation(s): +// \D[4]~92_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[4]~90_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[4]~90_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout & !\D[4]~91_combout )) # (!\D[4]~90_combout & ((\D[4]~91_combout ))))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\D[4]~90_combout ), + .datad(\D[4]~91_combout ), + .cin(gnd), + .combout(\D[4]~92_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~92 .lut_mask = 16'hC3E0; +defparam \D[4]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N8 +cycloneive_lcell_comb \D[4]~125 ( +// Equation(s): +// \D[4]~125_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\D[4]~94_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\D[4]~92_combout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & +// (((\D[4]~94_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\D[4]~94_combout ), + .datad(\D[4]~92_combout ), + .cin(gnd), + .combout(\D[4]~125_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~125 .lut_mask = 16'hF2D0; +defparam \D[4]~125 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N30 +cycloneive_lcell_comb \D[4]~110 ( +// Equation(s): +// \D[4]~110_combout = ((\Equal2~0_combout & (\D[4]~89_combout )) # (!\Equal2~0_combout & ((\D[4]~125_combout )))) # (!\Equal2~1_combout ) + + .dataa(\D[4]~89_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[4]~125_combout ), + .datad(\Equal2~1_combout ), + .cin(gnd), + .combout(\D[4]~110_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~110 .lut_mask = 16'hB8FF; +defparam \D[4]~110 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N4 +cycloneive_lcell_comb \D[4]~111 ( +// Equation(s): +// \D[4]~111_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[4]~110_combout & \z80_|data_pins_|dout [4])))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[4]~110_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[4]~110_combout ), + .datad(\z80_|data_pins_|dout [4]), + .cin(gnd), + .combout(\D[4]~111_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~111 .lut_mask = 16'hF151; +defparam \D[4]~111 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N10 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\D[4]~111_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[4]~19_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[4]~111_combout & +// (((\z80_|bus_control_|db[4]~19_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) + + .dataa(\D[4]~111_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|bus_control_|db[4]~19_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N11 +dffeas \z80_|data_pins_|dout[4] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N18 +cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( +// Equation(s): +// \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|data_pins_|dout [4]), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(gnd), + .datad(\z80_|bus_control_|db[0]~4_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'hBB00; +defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N6 +cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( +// Equation(s): +// \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~33_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[4]~18_combout ), + .datac(\z80_|alu_control_|db[4]~33_combout ), + .datad(\z80_|bus_control_|db[0]~6_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[4]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hC4FF; +defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N23 +dffeas \z80_|ir_|opcode[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[4]~19_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal32~0_combout = (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal32~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal2~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal2~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y7_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y7_N26 +cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( +// Equation(s): +// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal36~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal43~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal36~0_combout ), + .datab(\z80_|pla_decode_|Equal3~2_combout ), + .datac(\z80_|pla_decode_|Equal79~0_combout ), + .datad(\z80_|pla_decode_|Equal43~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|test1~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; +defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N30 +cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( +// Equation(s): +// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~53_combout & (((\z80_|interrupts_|test1~2_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|interrupts_|test1~2_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|setM1~53_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|test1~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h00FD; +defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N7 +dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|interrupts_|nmi_armed~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|interrupts_|test1~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y11_N16 +cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( +// Equation(s): +// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hF8FC; +defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_flags_alu~19_combout ) # ((\z80_|alu_control_|db[5]~17_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_high[1]~19_combout & +// (((\z80_|alu_control_|db[5]~17_combout & \z80_|execute_|ctl_flags_bus~combout )))) + + .dataa(\z80_|alu_|db_high[1]~19_combout ), + .datab(\z80_|execute_|ctl_flags_alu~19_combout ), + .datac(\z80_|alu_control_|db[5]~17_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N3 +dffeas \z80_|alu_flags_|flags_yf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_yf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_yf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N18 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( +// Equation(s): +// \z80_|alu_control_|db[5]~15_combout = (\z80_|alu_control_|out[6]~2_combout & (((\z80_|alu_flags_|flags_yf~q )) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_control_|out[6]~2_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & +// ((\z80_|alu_flags_|flags_yf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_control_|out[6]~2_combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_flags_|flags_yf~q ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hF3A2; +defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N12 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~16 ( +// Equation(s): +// \z80_|alu_control_|db[5]~16_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~15_combout & ((\z80_|reg_file_|gdfx_temp0[5]~71_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|sw1_|db_down[5]~0_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .datad(\z80_|alu_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~16 .lut_mask = 16'hA200; +defparam \z80_|alu_control_|db[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~17 ( +// Equation(s): +// \z80_|alu_control_|db[5]~17_combout = ((\z80_|alu_control_|db[5]~16_combout & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~13_combout ) + + .dataa(\z80_|alu_control_|db[5]~16_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_control_|db[6]~13_combout ), + .datad(\z80_|alu_|db[5]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~17 .lut_mask = 16'hAF2F; +defparam \z80_|alu_control_|db[5]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y33_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; +// synopsys translate_on + +// Location: M9K_X33_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80000001C000000160F000FF70C0007F78C00000F05001007870010010000000000800000038000000F000000070000000300000006000000000000040000000F00000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000001D108000BEDA9FA9698A000000000000000000000000FFFFFFFF408102048004188297E014DA9FA9E9CA00000000000000000000000000000000FFFFFFFC800400CA972208DA9FA9CD8E00000000000000000000000000000000FFFFFFFC8004046A97A289FA9FA9CDC20000000000000000000000007FFFFFFC8000000280040E2A97A2997A9DA9CFC20000000000000000000000007FFFFFFE8000000280042EB28002BE369DA9274200000000000000000000000040810206BFFFFFFE9FE430A29D82AC3E8009E34A000000000000000000000000000000023FFFFFFC9FE4B1829FA2800E8009436A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h9FE8334E88F827C697F88D1600A80A44809E8FC2B86999C2B85B3A82B1D32A869FE8336A88F807CA97F88F96A0A80EC2838E8D42B9E98FC2B86B3B82B0D7B2D2800832E288F827CA97F88B82A0080EC683869542B939B8C2B1AB0F8290B730C2800826EA8878078297F88AD2A0280EC283E694C2B83A3BC2A3AB3E8291A316AA800826EE881807C69DE8ABD6A0280BC282209CD2BA2A3D42A2737F82918314E2800806E6981805C69D48AED6A1E80BCA82709FC2BB223DC2A07B7F8295DF11C2800886E6980805869848AAC6A1E42DC281789DC2BBAA3DC6A02B7582955F00928008A6EE98082D9618088AC8A0F40FC289E89DC2BBCA3DC2A18B7782154F02F0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y6_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~23_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'hE10F8B8C100323720BEBBDEBB81DF13FF97B252E2CB4F27BA091FBD0002D1A611E1EDBBC716D44D2912B80041C44558060CFCF15955C0D780DD5E71393920844F25E16C87C5D0308EEC52C011514BBC13AFA1028924D0C7CE738105BD47A10AA5B5C1D9D4193E4339F492B0E1A64E13AE35BE6B67AC8057BDACC155F14E906A017A1841358335450D4B26CD2A21B3D8F2211080B81EC040D7FA0B51CD48008112508062020A02490900092D2040259108806A328F4006D2AA514B42FB006ECCCCB9A360865678449975A8AE72B5C0F7BA800C1B5DC55D7D6FE2EF4EED85D00AB111821321BA426A4FE4956B43595832C271E83E060341AE5F2023FC808177383; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h1A2955372D510AC266A5445146E27000020C320FAE1557E37154040A13202DC6F40B840FB9A59B6DBB296562CB6220EFBE99D2776A202044D9101006FD221D305519198C859000004012AFF4FB060307C92BB732203BFDFEFFFFFFDFFF87FCFFFBFFEFF03FFE0FFFBFAFE0FF80787FFF7FFF83F7F87003FFBFFFFBFFFBFF0FFC0FF81FFF7FFBFFDFFFBFFFE1FF0086F3141AAB6005810A0621595A893F9D85983B9254954341968BAC8C141C90938C05B2C9CD267E11650407375FEDD6A2FEB346AAF6CFDC0791AA97B741995A3B3981E06D1A44D3711955197BB9910FCA20744915C84D6C24BAF53929814CA8A4697E8F4201145AE7415DC122A5F010436107; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h02E84F969E3C800AC610D276182020227809001A50DDDBA3487BB6AE802BA06509312DA0E620656EAF24D57C08FFB14D289613DC32083803B84DC6415FD5EDC000300A8D128FA20030ACCBAFA237B7024504D36A4BA26081137F059E78991154FE2AC2A884A8CC7FBBB21C851CC92B12E15593C0C020FFEE066558590E882D5B67459F1A8C3240FE4E6A8D028C0C088FCF471D400A19B38211004DD122212288B111114514CB11840E04828849C621392041163C00808C67223422F00110201DD18FCFFFF3FFE7F9FFFFFFF82C0B422D214711E08904524A069491774E663F48F665955B4E2C63DAC0078652D10120900298F7EE380092442AFD400BEC43C003; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N2 +cycloneive_lcell_comb \Mux2~0 ( +// Equation(s): +// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~22_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~22_combout & +// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .cin(gnd), + .combout(\Mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux2~0 .lut_mask = 16'hB9A8; +defparam \Mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N24 +cycloneive_lcell_comb \Mux2~1 ( +// Equation(s): +// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datad(\Mux2~0_combout ), + .cin(gnd), + .combout(\Mux2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Mux2~1 .lut_mask = 16'hBBC0; +defparam \Mux2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y2_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # +// (\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout & +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 .lut_mask = 16'hCEC2; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~113_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~24_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~20_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 .lut_mask = 16'hBCB0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N30 +cycloneive_lcell_comb \D[5]~112 ( +// Equation(s): +// \D[5]~112_combout = ((\z80_|address_pins_|abus[15]~21_combout & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ))) # (!\z80_|address_pins_|abus[15]~21_combout & (\Mux2~1_combout ))) # (!\D[5]~97_combout ) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\D[5]~97_combout ), + .datac(\Mux2~1_combout ), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .cin(gnd), + .combout(\D[5]~112_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~112 .lut_mask = 16'hFB73; +defparam \D[5]~112 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N8 +cycloneive_lcell_comb \D[5]~113 ( +// Equation(s): +// \D[5]~113_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[5]~112_combout & \z80_|data_pins_|dout [5])))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[5]~112_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[5]~112_combout ), + .datad(\z80_|data_pins_|dout [5]), + .cin(gnd), + .combout(\D[5]~113_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~113 .lut_mask = 16'hF151; +defparam \D[5]~113 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N24 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|bus_control_|db[5]~15_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[5]~113_combout )))) # (!\z80_|bus_control_|db[5]~15_combout & +// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[5]~113_combout )))) + + .dataa(\z80_|bus_control_|db[5]~15_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datac(\z80_|pin_control_|bus_db_pin_re~combout ), + .datad(\D[5]~113_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y12_N25 +dffeas \z80_|data_pins_|dout[5] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N20 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( +// Equation(s): +// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(gnd), + .datab(\z80_|data_pins_|dout [5]), + .datac(\z80_|bus_control_|db[0]~4_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hC0F0; +defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( +// Equation(s): +// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~17_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|alu_control_|db[5]~17_combout ), + .datab(\z80_|bus_control_|db[0]~6_combout ), + .datac(\z80_|bus_control_|db[5]~14_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hB3F3; +defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N25 +dffeas \z80_|ir_|opcode[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[5]~15_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y9_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~11_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~46 ( +// Equation(s): +// \z80_|execute_|setM1~46_combout = (!\z80_|execute_|ctl_mRead~11_combout & (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_iorw~10_combout & \z80_|execute_|ctl_mRead~17_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~11_combout ), + .datab(\z80_|execute_|ctl_iorw~11_combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|execute_|ctl_mRead~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~46 .lut_mask = 16'h0100; +defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~40 ( +// Equation(s): +// \z80_|execute_|setM1~40_combout = (!\z80_|execute_|ctl_mWrite~7_combout & \z80_|execute_|setM1~39_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|setM1~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~40 .lut_mask = 16'h0F00; +defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|nextM~5 ( +// Equation(s): +// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|setM1~40_combout )) # (!\z80_|execute_|setM1~46_combout ))) + + .dataa(\z80_|execute_|setM1~46_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|setM1~40_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~5 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|nextM~6 ( +// Equation(s): +// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|nextM~3_combout ) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|nextM~3_combout ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|execute_|ixy_d~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~6 .lut_mask = 16'hB3FF; +defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|nextM~7 ( +// Equation(s): +// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~8_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|nextM~6_combout ), + .datac(\z80_|execute_|ixy_d~8_combout ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~7 .lut_mask = 16'hC8FF; +defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y9_N10 +cycloneive_lcell_comb \z80_|execute_|nextM~9 ( +// Equation(s): +// \z80_|execute_|nextM~9_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~9 .lut_mask = 16'hE000; +defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|nextM~10 ( +// Equation(s): +// \z80_|execute_|nextM~10_combout = (\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|ctl_mRead~34_combout ))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|nextM~9_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~8 ( +// Equation(s): +// \z80_|execute_|nextM~8_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ixy_d~8_combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ixy_d~8_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~8 .lut_mask = 16'h2F22; +defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|nextM~12 ( +// Equation(s): +// \z80_|execute_|nextM~12_combout = (\z80_|execute_|ctl_alu_op_low~21_combout ) # (((\z80_|execute_|nextM~10_combout ) # (\z80_|execute_|nextM~8_combout )) # (!\z80_|execute_|nextM~11_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~21_combout ), + .datab(\z80_|execute_|nextM~11_combout ), + .datac(\z80_|execute_|nextM~10_combout ), + .datad(\z80_|execute_|nextM~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|nextM~15 ( +// Equation(s): +// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|fMRead~12_combout )))) + + .dataa(\z80_|execute_|fMRead~12_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~15 .lut_mask = 16'hC040; +defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|nextM~13 ( +// Equation(s): +// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~7_combout ) # ((\z80_|execute_|nextM~12_combout ) # (\z80_|execute_|nextM~15_combout )) + + .dataa(\z80_|execute_|nextM~7_combout ), + .datab(\z80_|execute_|nextM~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~14 ( +// Equation(s): +// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~5_combout ) # ((\z80_|execute_|nextM~13_combout ) # ((!\z80_|execute_|ctl_mWrite~14_combout ) # (!\z80_|execute_|ctl_mRead~28_combout ))) + + .dataa(\z80_|execute_|nextM~5_combout ), + .datab(\z80_|execute_|nextM~13_combout ), + .datac(\z80_|execute_|ctl_mRead~28_combout ), + .datad(\z80_|execute_|ctl_mWrite~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~14 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N22 +cycloneive_lcell_comb \z80_|sequencer_|ena_M ( +// Equation(s): +// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|ena_M~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; +defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N23 +dffeas \z80_|sequencer_|DFFE_T1_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|ena_M~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T1_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N26 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0050; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N27 +dffeas \z80_|sequencer_|DFFE_T2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T2_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N30 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N31 +dffeas \z80_|sequencer_|DFFE_T3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T3_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N20 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N21 +dffeas \z80_|sequencer_|DFFE_T4_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T4_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y9_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~9_combout & (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|execute_|ctl_mWrite~9_combout & (((!\z80_|execute_|ctl_mWrite~5_combout ) # +// (!\z80_|execute_|ctl_ir_we~12_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0757; +defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~54 ( +// Equation(s): +// \z80_|execute_|setM1~54_combout = ((\z80_|execute_|ctl_iorw~11_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_iorw~11_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~54 .lut_mask = 16'hD555; +defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~25 ( +// Equation(s): +// \z80_|execute_|setM1~25_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_mRead~10_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~25 .lut_mask = 16'h2F22; +defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~26 ( +// Equation(s): +// \z80_|execute_|setM1~26_combout = (\z80_|execute_|ctl_mRead~11_combout ) # (((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) + + .dataa(\z80_|alu_control_|flags_cond_true~q ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~26 .lut_mask = 16'hDCFF; +defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~27 ( +// Equation(s): +// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~26_combout ) # (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|execute_|setM1~26_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~27 .lut_mask = 16'hECFF; +defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~22 ( +// Equation(s): +// \z80_|execute_|setM1~22_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|decode_state_|DFFE_instNonRep~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~22 .lut_mask = 16'hFF04; +defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~55 ( +// Equation(s): +// \z80_|execute_|setM1~55_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|execute_|setM1~22_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|setM1~22_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~55 .lut_mask = 16'hF080; +defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~23 ( +// Equation(s): +// \z80_|execute_|setM1~23_combout = (\z80_|execute_|fMWrite~0_combout & (!\z80_|execute_|ctl_mRead~8_combout & (\z80_|execute_|fMWrite~6_combout & !\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|fMWrite~0_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|fMWrite~6_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~23 .lut_mask = 16'h0020; +defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~24 ( +// Equation(s): +// \z80_|execute_|setM1~24_combout = (\z80_|execute_|setM1~55_combout & (((\z80_|execute_|ctl_reg_in_hi~2_combout & !\z80_|execute_|setM1~23_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) # (!\z80_|execute_|setM1~55_combout & +// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|execute_|setM1~23_combout )))) + + .dataa(\z80_|execute_|setM1~55_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_flags_bus~5_combout ), + .datad(\z80_|execute_|setM1~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~24 .lut_mask = 16'h0ACE; +defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~28 ( +// Equation(s): +// \z80_|execute_|setM1~28_combout = (\z80_|execute_|setM1~25_combout ) # ((\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|setM1~27_combout & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|setM1~25_combout ), + .datab(\z80_|execute_|setM1~27_combout ), + .datac(\z80_|execute_|setM1~24_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~11 ( +// Equation(s): +// \z80_|execute_|setM1~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [2]))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~11 .lut_mask = 16'hFF04; +defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~33 ( +// Equation(s): +// \z80_|execute_|setM1~33_combout = (\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mRead~2_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|setM1~11_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|setM1~11_combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~29 ( +// Equation(s): +// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~5_combout ) # (((\z80_|execute_|ctl_mRead~13_combout ) # (\z80_|execute_|ctl_mRead~7_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~29 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~31 ( +// Equation(s): +// \z80_|execute_|setM1~31_combout = (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~30_combout )) # (!\z80_|execute_|setM1~56_combout ) + + .dataa(\z80_|execute_|setM1~56_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|setM1~29_combout ), + .datad(\z80_|execute_|setM1~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~31 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~32 ( +// Equation(s): +// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~16_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & +// (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~16_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~32 .lut_mask = 16'hECA0; +defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~34 ( +// Equation(s): +// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~32_combout ) # ((\z80_|execute_|setM1~33_combout & \z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|setM1~33_combout ), + .datab(\z80_|execute_|setM1~31_combout ), + .datac(\z80_|execute_|setM1~32_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~20 ( +// Equation(s): +// \z80_|execute_|setM1~20_combout = (\z80_|execute_|ctl_mRead~9_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_flags_bus~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~20 .lut_mask = 16'h20F0; +defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~21 ( +// Equation(s): +// \z80_|execute_|setM1~21_combout = (\z80_|execute_|setM1~20_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & (\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|ixy_d~8_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|execute_|setM1~20_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~21 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~35 ( +// Equation(s): +// \z80_|execute_|setM1~35_combout = (\z80_|execute_|setM1~54_combout ) # ((\z80_|execute_|setM1~28_combout ) # ((\z80_|execute_|setM1~34_combout ) # (\z80_|execute_|setM1~21_combout ))) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(\z80_|execute_|setM1~28_combout ), + .datac(\z80_|execute_|setM1~34_combout ), + .datad(\z80_|execute_|setM1~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~35 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~15 ( +// Equation(s): +// \z80_|execute_|setM1~15_combout = (\z80_|pla_decode_|Equal21~2_combout & (!\z80_|pla_decode_|Equal32~0_combout & ((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )))) # (!\z80_|pla_decode_|Equal21~2_combout & +// (((!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~2_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~15 .lut_mask = 16'h153F; +defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~14 ( +// Equation(s): +// \z80_|execute_|setM1~14_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|execute_|ctl_alu_oe~3_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal77~1_combout ), + .datac(\z80_|pla_decode_|Equal1~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~14 .lut_mask = 16'h0003; +defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~16 ( +// Equation(s): +// \z80_|execute_|setM1~16_combout = (\z80_|interrupts_|test1~2_combout & (\z80_|execute_|setM1~15_combout & (\z80_|execute_|setM1~14_combout & !\z80_|pla_decode_|Equal2~2_combout ))) + + .dataa(\z80_|interrupts_|test1~2_combout ), + .datab(\z80_|execute_|setM1~15_combout ), + .datac(\z80_|execute_|setM1~14_combout ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0080; +defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~10 ( +// Equation(s): +// \z80_|execute_|setM1~10_combout = (\z80_|pla_decode_|Equal6~1_combout ) # (((\z80_|execute_|ctl_mWrite~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|fMWrite~0_combout )) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|fMWrite~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~12 ( +// Equation(s): +// \z80_|execute_|setM1~12_combout = ((\z80_|execute_|setM1~10_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout & \z80_|execute_|setM1~11_combout ))) # (!\z80_|execute_|nextM~2_combout ) + + .dataa(\z80_|execute_|nextM~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|setM1~11_combout ), + .datad(\z80_|execute_|setM1~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~12 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~8 ( +// Equation(s): +// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_al_we~13_combout & (((\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & +// \z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~8 .lut_mask = 16'hF444; +defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~9 ( +// Equation(s): +// \z80_|execute_|setM1~9_combout = ((\z80_|execute_|setM1~8_combout & \z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|execute_|ctl_flags_xy_we~17_combout ) + + .dataa(\z80_|execute_|setM1~8_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~9 .lut_mask = 16'hA0FF; +defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~13 ( +// Equation(s): +// \z80_|execute_|setM1~13_combout = ((\z80_|execute_|setM1~9_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|setM1~12_combout ))) # (!\z80_|reg_control_|reg_sel_pc~3_combout ) + + .dataa(\z80_|reg_control_|reg_sel_pc~3_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|setM1~12_combout ), + .datad(\z80_|execute_|setM1~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~13 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y8_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~18 ( +// Equation(s): +// \z80_|execute_|setM1~18_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|execute_|setM1~17_combout & (\z80_|execute_|ctl_alu_op_low~38_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|setM1~17_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~18 .lut_mask = 16'h0040; +defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~19 ( +// Equation(s): +// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~13_combout ) # (((!\z80_|execute_|setM1~16_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|setM1~18_combout )) + + .dataa(\z80_|execute_|setM1~16_combout ), + .datab(\z80_|execute_|setM1~13_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|setM1~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~19 .lut_mask = 16'hDCFF; +defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y9_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~43 ( +// Equation(s): +// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|pla_decode_|Equal37~0_combout & !\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal38~2_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0004; +defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~42 ( +// Equation(s): +// \z80_|execute_|setM1~42_combout = (!\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout )) + + .dataa(\z80_|execute_|ctl_mWrite~6_combout ), + .datab(\z80_|execute_|ctl_ir_we~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|setM1~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0101; +defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y8_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~44 ( +// Equation(s): +// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~42_combout & !\z80_|pla_decode_|Equal48~0_combout ))) + + .dataa(\z80_|execute_|setM1~43_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|setM1~42_combout ), + .datad(\z80_|pla_decode_|Equal48~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~44 .lut_mask = 16'h0020; +defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~45 ( +// Equation(s): +// \z80_|execute_|setM1~45_combout = (\z80_|execute_|setM1~41_combout & (\z80_|execute_|setM1~44_combout & ((!\z80_|pla_decode_|Equal1~4_combout ) # (!\z80_|pla_decode_|Equal2~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal2~1_combout ), + .datab(\z80_|execute_|setM1~41_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|execute_|setM1~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~45 .lut_mask = 16'h4C00; +defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~51 ( +// Equation(s): +// \z80_|execute_|setM1~51_combout = (\z80_|execute_|setM1~45_combout & (\z80_|execute_|setM1~47_combout & (\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~16_combout ))) + + .dataa(\z80_|execute_|setM1~45_combout ), + .datab(\z80_|execute_|setM1~47_combout ), + .datac(\z80_|execute_|setM1~50_combout ), + .datad(\z80_|execute_|setM1~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~51 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N18 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~53_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|execute_|setM1~53_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N19 +dffeas \z80_|sequencer_|T6 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|T6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|T6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~52 ( +// Equation(s): +// \z80_|execute_|setM1~52_combout = (\z80_|execute_|setM1~51_combout & ((\z80_|execute_|setM1~40_combout ) # ((\z80_|sequencer_|T6~q & !\z80_|execute_|setM1~41_combout )))) # (!\z80_|execute_|setM1~51_combout & (\z80_|sequencer_|T6~q & +// (!\z80_|execute_|setM1~41_combout ))) + + .dataa(\z80_|execute_|setM1~51_combout ), + .datab(\z80_|sequencer_|T6~q ), + .datac(\z80_|execute_|setM1~41_combout ), + .datad(\z80_|execute_|setM1~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~52 .lut_mask = 16'hAE0C; +defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~53 ( +// Equation(s): +// \z80_|execute_|setM1~53_combout = (!\z80_|execute_|setM1~35_combout & (!\z80_|execute_|setM1~19_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~52_combout )))) + + .dataa(\z80_|execute_|setM1~35_combout ), + .datab(\z80_|execute_|setM1~19_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|setM1~52_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~53 .lut_mask = 16'h1011; +defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N14 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hCCC0; +defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N15 +dffeas \z80_|sequencer_|DFFE_M1_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M1_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N28 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h44C0; +defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y13_N29 +dffeas \z80_|sequencer_|DFFE_M2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M2_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h0F0C; +defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N28 cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( // Equation(s): -// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_apin_mux~1_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) +// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_apin_mux~1_combout ), - .datac(\z80_|execute_|ctl_inc_dec~6_combout ), - .datad(gnd), + .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_dec~6_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_apin_mux~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'h8F8F; +defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'h88FF; defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y16_N18 +// Location: LCCOMB_X28_Y16_N20 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[0]~0 ( // Equation(s): // \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [0]))) @@ -53232,7 +53700,7 @@ defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hDD88; defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y16_N19 +// Location: FF_X28_Y16_N21 dffeas \z80_|address_pins_|DFFE_apin_latch[0] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), @@ -53251,228 +53719,332 @@ defparam \z80_|address_pins_|DFFE_apin_latch[0] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N12 -cycloneive_lcell_comb \D[0]~59 ( +// Location: LCCOMB_X24_Y15_N30 +cycloneive_lcell_comb \D[0]~66 ( // Equation(s): -// \D[0]~59_combout = (\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout ))) - - .dataa(\Equal2~0_combout ), - .datab(\D[0]~51_combout ), - .datac(\D[0]~106_combout ), - .datad(gnd), - .cin(gnd), - .combout(\D[0]~59_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~59 .lut_mask = 16'hD8D8; -defparam \D[0]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N8 -cycloneive_lcell_comb \D[0]~60 ( -// Equation(s): -// \D[0]~60_combout = (\Equal2~1_combout & (\D[0]~59_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [0]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [0]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[0]~59_combout ), - .cin(gnd), - .combout(\D[0]~60_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~60 .lut_mask = 16'hCF45; -defparam \D[0]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y18_N20 -cycloneive_lcell_comb \D[1]~61 ( -// Equation(s): -// \D[1]~61_combout = (\Equal2~0_combout & (\D[1]~32_combout )) # (!\Equal2~0_combout & ((\D[1]~103_combout ))) - - .dataa(\Equal2~0_combout ), - .datab(gnd), - .datac(\D[1]~32_combout ), - .datad(\D[1]~103_combout ), - .cin(gnd), - .combout(\D[1]~61_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~61 .lut_mask = 16'hF5A0; -defparam \D[1]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y18_N22 -cycloneive_lcell_comb \D[1]~62 ( -// Equation(s): -// \D[1]~62_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~61_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~61_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [1]), - .datad(\D[1]~61_combout ), - .cin(gnd), - .combout(\D[1]~62_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~62 .lut_mask = 16'hF531; -defparam \D[1]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N12 -cycloneive_lcell_comb \D[2]~63 ( -// Equation(s): -// \D[2]~63_combout = (\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout ))) - - .dataa(\Equal2~0_combout ), - .datab(gnd), - .datac(\D[2]~104_combout ), - .datad(\D[2]~105_combout ), - .cin(gnd), - .combout(\D[2]~63_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~63 .lut_mask = 16'hF5A0; -defparam \D[2]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N26 -cycloneive_lcell_comb \D[2]~64 ( -// Equation(s): -// \D[2]~64_combout = (\z80_|data_pins_|dout [2] & (((\D[2]~63_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [2] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[2]~63_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [2]), - .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[2]~63_combout ), - .cin(gnd), - .combout(\D[2]~64_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~64 .lut_mask = 16'hAF23; -defparam \D[2]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N2 -cycloneive_lcell_comb \D[3]~75 ( -// Equation(s): -// \D[3]~75_combout = (\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout ))) - - .dataa(\D[3]~69_combout ), - .datab(gnd), - .datac(\Equal2~0_combout ), - .datad(\D[3]~108_combout ), - .cin(gnd), - .combout(\D[3]~75_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~75 .lut_mask = 16'hAFA0; -defparam \D[3]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N20 -cycloneive_lcell_comb \D[3]~76 ( -// Equation(s): -// \D[3]~76_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~75_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[3]~75_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [3]), - .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[3]~75_combout ), - .cin(gnd), - .combout(\D[3]~76_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~76 .lut_mask = 16'hAF23; -defparam \D[3]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N24 -cycloneive_lcell_comb \D[4]~82 ( -// Equation(s): -// \D[4]~82_combout = (\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout ))) - - .dataa(\Equal2~0_combout ), - .datab(\D[4]~81_combout ), - .datac(gnd), - .datad(\D[4]~109_combout ), - .cin(gnd), - .combout(\D[4]~82_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~82 .lut_mask = 16'hDD88; -defparam \D[4]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N26 -cycloneive_lcell_comb \D[4]~83 ( -// Equation(s): -// \D[4]~83_combout = (\Equal2~1_combout & (\D[4]~82_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [4]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [4]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[4]~82_combout ), - .cin(gnd), - .combout(\D[4]~83_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~83 .lut_mask = 16'hCF45; -defparam \D[4]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N24 -cycloneive_lcell_comb \D[6]~92 ( -// Equation(s): -// \D[6]~92_combout = (\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout )) +// \D[0]~66_combout = (\Equal2~0_combout & (\D[0]~58_combout )) # (!\Equal2~0_combout & ((\D[0]~120_combout ))) .dataa(gnd), .datab(\Equal2~0_combout ), - .datac(\D[6]~111_combout ), - .datad(\D[6]~86_combout ), + .datac(\D[0]~58_combout ), + .datad(\D[0]~120_combout ), .cin(gnd), - .combout(\D[6]~92_combout ), + .combout(\D[0]~66_combout ), .cout()); // synopsys translate_off -defparam \D[6]~92 .lut_mask = 16'hFC30; -defparam \D[6]~92 .sum_lutc_input = "datac"; +defparam \D[0]~66 .lut_mask = 16'hF3C0; +defparam \D[0]~66 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N10 -cycloneive_lcell_comb \D[6]~93 ( +// Location: LCCOMB_X25_Y15_N18 +cycloneive_lcell_comb \D[0]~67 ( // Equation(s): -// \D[6]~93_combout = (\Equal2~1_combout & (\D[6]~92_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [6]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) +// \D[0]~67_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [0] & ((\D[0]~66_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[0]~66_combout ) # (!\Equal2~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[6]~92_combout ), + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|data_pins_|dout [0]), + .datac(\Equal2~1_combout ), + .datad(\D[0]~66_combout ), .cin(gnd), - .combout(\D[6]~93_combout ), + .combout(\D[0]~67_combout ), .cout()); // synopsys translate_off -defparam \D[6]~93 .lut_mask = 16'hCF45; -defparam \D[6]~93 .sum_lutc_input = "datac"; +defparam \D[0]~67 .lut_mask = 16'hDD0D; +defparam \D[0]~67 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N0 -cycloneive_lcell_comb \z80_|nM1_int~3 ( +// Location: LCCOMB_X25_Y17_N24 +cycloneive_lcell_comb \D[0]~121 ( // Equation(s): -// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) +// \D[0]~121_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout ) # ((\z80_|memory_ifc_|nRD_out~2_combout & (!\z80_|memory_ifc_|nWR_out~0_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .cin(gnd), + .combout(\D[0]~121_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~121 .lut_mask = 16'hFF20; +defparam \D[0]~121 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N16 +cycloneive_lcell_comb \D[1]~68 ( +// Equation(s): +// \D[1]~68_combout = (\Equal2~0_combout & (\D[1]~34_combout )) # (!\Equal2~0_combout & ((\D[1]~118_combout ))) .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|setM1~52_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[1]~34_combout ), + .datad(\D[1]~118_combout ), + .cin(gnd), + .combout(\D[1]~68_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~68 .lut_mask = 16'hF3C0; +defparam \D[1]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N14 +cycloneive_lcell_comb \D[1]~69 ( +// Equation(s): +// \D[1]~69_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~68_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[1]~68_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\Equal2~1_combout ), + .datad(\D[1]~68_combout ), + .cin(gnd), + .combout(\D[1]~69_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~69 .lut_mask = 16'hDD0D; +defparam \D[1]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N16 +cycloneive_lcell_comb \D[2]~70 ( +// Equation(s): +// \D[2]~70_combout = (\Equal2~0_combout & (\D[2]~46_combout )) # (!\Equal2~0_combout & ((\D[2]~119_combout ))) + + .dataa(gnd), + .datab(\D[2]~46_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[2]~119_combout ), + .cin(gnd), + .combout(\D[2]~70_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~70 .lut_mask = 16'hCFC0; +defparam \D[2]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N14 +cycloneive_lcell_comb \D[2]~71 ( +// Equation(s): +// \D[2]~71_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|data_pins_|dout [2] & ((\D[2]~70_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout & (((\D[2]~70_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\Equal2~1_combout ), + .datac(\z80_|data_pins_|dout [2]), + .datad(\D[2]~70_combout ), + .cin(gnd), + .combout(\D[2]~71_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~71 .lut_mask = 16'hF531; +defparam \D[2]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N24 +cycloneive_lcell_comb \D[3]~83 ( +// Equation(s): +// \D[3]~83_combout = (\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(gnd), + .datac(\z80_|data_pins_|dout [3]), + .datad(gnd), + .cin(gnd), + .combout(\D[3]~83_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~83 .lut_mask = 16'hF5F5; +defparam \D[3]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N6 +cycloneive_lcell_comb \D[3]~84 ( +// Equation(s): +// \D[3]~84_combout = (\D[3]~83_combout & ((\D[3]~122_combout ) # ((\D[3]~82_combout ) # (!\Equal2~1_combout )))) + + .dataa(\D[3]~122_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[3]~82_combout ), + .datad(\D[3]~83_combout ), + .cin(gnd), + .combout(\D[3]~84_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~84 .lut_mask = 16'hFB00; +defparam \D[3]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N20 +cycloneive_lcell_comb \D[4]~95 ( +// Equation(s): +// \D[4]~95_combout = (\Equal2~0_combout & (\D[4]~89_combout )) # (!\Equal2~0_combout & ((\D[4]~125_combout ))) + + .dataa(\D[4]~89_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[4]~125_combout ), + .datad(gnd), + .cin(gnd), + .combout(\D[4]~95_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~95 .lut_mask = 16'hB8B8; +defparam \D[4]~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N6 +cycloneive_lcell_comb \D[4]~96 ( +// Equation(s): +// \D[4]~96_combout = (\z80_|data_pins_|dout [4] & (((\D[4]~95_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [4] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[4]~95_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [4]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[4]~95_combout ), + .cin(gnd), + .combout(\D[4]~96_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~96 .lut_mask = 16'hAF23; +defparam \D[4]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N18 +cycloneive_lcell_comb \D[5]~126 ( +// Equation(s): +// \D[5]~126_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\Mux2~1_combout )) # +// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ))))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\Mux2~1_combout ), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1_combout ), + .cin(gnd), + .combout(\D[5]~126_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~126 .lut_mask = 16'hFB40; +defparam \D[5]~126 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N0 +cycloneive_lcell_comb \D[5]~98 ( +// Equation(s): +// \D[5]~98_combout = (\z80_|data_pins_|dout [5] & (((\D[5]~126_combout )) # (!\D[5]~97_combout ))) # (!\z80_|data_pins_|dout [5] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[5]~126_combout ) # (!\D[5]~97_combout )))) + + .dataa(\z80_|data_pins_|dout [5]), + .datab(\D[5]~97_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[5]~126_combout ), + .cin(gnd), + .combout(\D[5]~98_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~98 .lut_mask = 16'hAF23; +defparam \D[5]~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N18 +cycloneive_lcell_comb \D[6]~105 ( +// Equation(s): +// \D[6]~105_combout = (\Equal2~0_combout & ((\D[6]~99_combout ))) # (!\Equal2~0_combout & (\D[6]~127_combout )) + + .dataa(gnd), + .datab(\Equal2~0_combout ), + .datac(\D[6]~127_combout ), + .datad(\D[6]~99_combout ), + .cin(gnd), + .combout(\D[6]~105_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~105 .lut_mask = 16'hFC30; +defparam \D[6]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N0 +cycloneive_lcell_comb \D[6]~106 ( +// Equation(s): +// \D[6]~106_combout = (\z80_|data_pins_|dout [6] & (((\D[6]~105_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [6] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[6]~105_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [6]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[6]~105_combout ), + .cin(gnd), + .combout(\D[6]~106_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~106 .lut_mask = 16'hAF23; +defparam \D[6]~106 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N10 +cycloneive_lcell_comb \D[7]~128 ( +// Equation(s): +// \D[7]~128_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux0~1_combout ))))) # +// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3_combout ), + .datad(\Mux0~1_combout ), + .cin(gnd), + .combout(\D[7]~128_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~128 .lut_mask = 16'hF2D0; +defparam \D[7]~128 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N16 +cycloneive_lcell_comb \D[7]~107 ( +// Equation(s): +// \D[7]~107_combout = (\z80_|data_pins_|dout [7] & (((\D[7]~128_combout ) # (!\D[5]~97_combout )))) # (!\z80_|data_pins_|dout [7] & (!\z80_|pin_control_|bus_db_pin_oe~16_combout & ((\D[7]~128_combout ) # (!\D[5]~97_combout )))) + + .dataa(\z80_|data_pins_|dout [7]), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\D[5]~97_combout ), + .datad(\D[7]~128_combout ), + .cin(gnd), + .combout(\D[7]~107_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~107 .lut_mask = 16'hBB0B; +defparam \D[7]~107 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y14_N6 +cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nIORQ_out~0_combout = (!\z80_|memory_ifc_|DFFE_intr_ff3~q & (!\z80_|memory_ifc_|iorq~0_combout & !\z80_|memory_ifc_|wait_iorqinta~q )) + + .dataa(gnd), + .datab(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .datac(\z80_|memory_ifc_|iorq~0_combout ), + .datad(\z80_|memory_ifc_|wait_iorqinta~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'h0003; +defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y13_N12 +cycloneive_lcell_comb \z80_|nM1_int~3 ( +// Equation(s): +// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~53_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~53_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), .combout(\z80_|nM1_int~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|nM1_int~3 .lut_mask = 16'hFC00; +defparam \z80_|nM1_int~3 .lut_mask = 16'hCCC0; defparam \z80_|nM1_int~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N1 +// Location: FF_X40_Y13_N13 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|nM1_int~3_combout ), @@ -53491,7 +54063,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N30 +// Location: LCCOMB_X40_Y11_N4 cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder ( // Equation(s): // \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -53508,7 +54080,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N31 +// Location: FF_X40_Y11_N5 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ), @@ -53527,7 +54099,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .power_up = "low"; // synopsys translate_on -// Location: FF_X43_Y17_N25 +// Location: FF_X40_Y11_N27 dffeas \z80_|memory_ifc_|DFFE_mreq_ff2 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -53546,31 +54118,31 @@ defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N24 +// Location: LCCOMB_X40_Y11_N26 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~0 ( // Equation(s): // \z80_|memory_ifc_|nMREQ_out~0_combout = (\z80_|memory_ifc_|wait_mwr~q ) # ((\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q & !\z80_|memory_ifc_|DFFE_mreq_ff2~q ))) - .dataa(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), - .datab(\z80_|memory_ifc_|wait_mwr~q ), + .dataa(\z80_|memory_ifc_|wait_mwr~q ), + .datab(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), .datac(\z80_|memory_ifc_|DFFE_mreq_ff2~q ), .datad(\z80_|memory_ifc_|mwr_wr~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFCE; +defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFAE; defparam \z80_|memory_ifc_|nMREQ_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N2 +// Location: LCCOMB_X40_Y11_N2 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~1 ( // Equation(s): -// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nMREQ_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|nRD_out~0_combout ))) +// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nMREQ_out~0_combout & !\z80_|memory_ifc_|nRD_out~0_combout ))) - .dataa(\z80_|memory_ifc_|wait_mrd~q ), - .datab(\z80_|memory_ifc_|nMREQ_out~0_combout ), - .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .dataa(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .datab(\z80_|memory_ifc_|wait_mrd~q ), + .datac(\z80_|memory_ifc_|nMREQ_out~0_combout ), .datad(\z80_|memory_ifc_|nRD_out~0_combout ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~1_combout ), @@ -53593,24 +54165,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( -// Equation(s): -// \ula_|i2c_loader_|state.Idle~feeder_combout = VCC - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Idle~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; -defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y24_N0 +// Location: LCCOMB_X1_Y24_N18 cycloneive_lcell_comb \ula_|i2c_loader_|divider[0]~15 ( // Equation(s): // \ula_|i2c_loader_|divider[0]~15_combout = !\ula_|i2c_loader_|divider [0] @@ -53627,7 +54182,7 @@ defparam \ula_|i2c_loader_|divider[0]~15 .lut_mask = 16'h0F0F; defparam \ula_|i2c_loader_|divider[0]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X4_Y24_N1 +// Location: FF_X1_Y24_N19 dffeas \ula_|i2c_loader_|divider[0] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[0]~15_combout ), @@ -53646,14 +54201,14 @@ defparam \ula_|i2c_loader_|divider[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N10 +// Location: LCCOMB_X1_Y24_N8 cycloneive_lcell_comb \ula_|i2c_loader_|divider[1]~5 ( // Equation(s): -// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] $ (VCC))) # (!\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] & VCC)) -// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [1] & \ula_|i2c_loader_|divider [0])) +// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] $ (VCC))) # (!\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] & VCC)) +// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [0] & \ula_|i2c_loader_|divider [1])) - .dataa(\ula_|i2c_loader_|divider [1]), - .datab(\ula_|i2c_loader_|divider [0]), + .dataa(\ula_|i2c_loader_|divider [0]), + .datab(\ula_|i2c_loader_|divider [1]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -53664,7 +54219,7 @@ defparam \ula_|i2c_loader_|divider[1]~5 .lut_mask = 16'h6688; defparam \ula_|i2c_loader_|divider[1]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X4_Y24_N11 +// Location: FF_X1_Y24_N9 dffeas \ula_|i2c_loader_|divider[1] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[1]~5_combout ), @@ -53683,7 +54238,7 @@ defparam \ula_|i2c_loader_|divider[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N12 +// Location: LCCOMB_X1_Y24_N10 cycloneive_lcell_comb \ula_|i2c_loader_|divider[2]~7 ( // Equation(s): // \ula_|i2c_loader_|divider[2]~7_combout = (\ula_|i2c_loader_|divider [2] & (!\ula_|i2c_loader_|divider[1]~6 )) # (!\ula_|i2c_loader_|divider [2] & ((\ula_|i2c_loader_|divider[1]~6 ) # (GND))) @@ -53701,7 +54256,7 @@ defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|divider[2]~7 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N13 +// Location: FF_X1_Y24_N11 dffeas \ula_|i2c_loader_|divider[2] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[2]~7_combout ), @@ -53720,25 +54275,25 @@ defparam \ula_|i2c_loader_|divider[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N14 +// Location: LCCOMB_X1_Y24_N12 cycloneive_lcell_comb \ula_|i2c_loader_|divider[3]~9 ( // Equation(s): // \ula_|i2c_loader_|divider[3]~9_combout = (\ula_|i2c_loader_|divider [3] & (\ula_|i2c_loader_|divider[2]~8 $ (GND))) # (!\ula_|i2c_loader_|divider [3] & (!\ula_|i2c_loader_|divider[2]~8 & VCC)) // \ula_|i2c_loader_|divider[3]~10 = CARRY((\ula_|i2c_loader_|divider [3] & !\ula_|i2c_loader_|divider[2]~8 )) - .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [3]), + .dataa(\ula_|i2c_loader_|divider [3]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|divider[2]~8 ), .combout(\ula_|i2c_loader_|divider[3]~9_combout ), .cout(\ula_|i2c_loader_|divider[3]~10 )); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[3]~9 .lut_mask = 16'hC30C; +defparam \ula_|i2c_loader_|divider[3]~9 .lut_mask = 16'hA50A; defparam \ula_|i2c_loader_|divider[3]~9 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N15 +// Location: FF_X1_Y24_N13 dffeas \ula_|i2c_loader_|divider[3] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[3]~9_combout ), @@ -53757,7 +54312,24 @@ defparam \ula_|i2c_loader_|divider[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N16 +// Location: LCCOMB_X1_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( +// Equation(s): +// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [1])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [3]) + + .dataa(\ula_|i2c_loader_|divider [3]), + .datab(\ula_|i2c_loader_|divider [0]), + .datac(\ula_|i2c_loader_|divider [1]), + .datad(\ula_|i2c_loader_|divider [2]), + .cin(gnd), + .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; +defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N14 cycloneive_lcell_comb \ula_|i2c_loader_|divider[4]~11 ( // Equation(s): // \ula_|i2c_loader_|divider[4]~11_combout = (\ula_|i2c_loader_|divider [4] & (!\ula_|i2c_loader_|divider[3]~10 )) # (!\ula_|i2c_loader_|divider [4] & ((\ula_|i2c_loader_|divider[3]~10 ) # (GND))) @@ -53775,7 +54347,7 @@ defparam \ula_|i2c_loader_|divider[4]~11 .lut_mask = 16'h3C3F; defparam \ula_|i2c_loader_|divider[4]~11 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N17 +// Location: FF_X1_Y24_N15 dffeas \ula_|i2c_loader_|divider[4] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[4]~11_combout ), @@ -53794,7 +54366,7 @@ defparam \ula_|i2c_loader_|divider[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N18 +// Location: LCCOMB_X1_Y24_N16 cycloneive_lcell_comb \ula_|i2c_loader_|divider[5]~13 ( // Equation(s): // \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider[4]~12 $ (!\ula_|i2c_loader_|divider [5]) @@ -53811,7 +54383,7 @@ defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hF00F; defparam \ula_|i2c_loader_|divider[5]~13 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N19 +// Location: FF_X1_Y24_N17 dffeas \ula_|i2c_loader_|divider[5] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[5]~13_combout ), @@ -53830,1115 +54402,23 @@ defparam \ula_|i2c_loader_|divider[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( -// Equation(s): -// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [3])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [1]) - - .dataa(\ula_|i2c_loader_|divider [1]), - .datab(\ula_|i2c_loader_|divider [0]), - .datac(\ula_|i2c_loader_|divider [3]), - .datad(\ula_|i2c_loader_|divider [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; -defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y24_N8 +// Location: LCCOMB_X1_Y24_N30 cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0 ( // Equation(s): -// \ula_|i2c_loader_|WideAnd0~combout = ((\ula_|i2c_loader_|WideAnd0~0_combout ) # (!\ula_|i2c_loader_|divider [4])) # (!\ula_|i2c_loader_|divider [5]) +// \ula_|i2c_loader_|WideAnd0~combout = (\ula_|i2c_loader_|WideAnd0~0_combout ) # ((!\ula_|i2c_loader_|divider [5]) # (!\ula_|i2c_loader_|divider [4])) .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [5]), - .datac(\ula_|i2c_loader_|WideAnd0~0_combout ), - .datad(\ula_|i2c_loader_|divider [4]), + .datab(\ula_|i2c_loader_|WideAnd0~0_combout ), + .datac(\ula_|i2c_loader_|divider [4]), + .datad(\ula_|i2c_loader_|divider [5]), .cin(gnd), .combout(\ula_|i2c_loader_|WideAnd0~combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hF3FF; +defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hCFFF; defparam \ula_|i2c_loader_|WideAnd0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N1 -dffeas \ula_|i2c_loader_|state.Idle ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Idle~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Idle~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Idle .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Idle .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|phase~0 ( -// Equation(s): -// \ula_|i2c_loader_|phase~0_combout = (!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|phase~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|phase~0 .lut_mask = 16'h0F00; -defparam \ula_|i2c_loader_|phase~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N5 -dffeas \ula_|i2c_loader_|phase[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|phase~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|phase [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|phase[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|phase[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|phase~1 ( -// Equation(s): -// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [0] $ (\ula_|i2c_loader_|phase [1]))) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|phase~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h3C00; -defparam \ula_|i2c_loader_|phase~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N15 -dffeas \ula_|i2c_loader_|phase[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|phase~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|phase [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|phase[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|phase[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~5_combout = (!\ula_|i2c_loader_|nbit [0]) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbit [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h5F5F; -defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) -// \ula_|i2c_loader_|thisbyte[0]~9 = CARRY(\ula_|i2c_loader_|thisbyte [0]) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~8_combout ), - .cout(\ula_|i2c_loader_|thisbyte[0]~9 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; -defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( -// Equation(s): -// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Mux42~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hF000; -defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [0] $ (!\ula_|i2c_loader_|nbyte [1])))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Start~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hFF84; -defparam \ula_|i2c_loader_|nbyte~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state.Ack~q ) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hC0C0; -defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X0_Y23_N1 -cycloneive_io_ibuf \I2C_SDAT~input ( - .i(I2C_SDAT), - .ibar(gnd), - .o(\I2C_SDAT~input_o )); -// synopsys translate_off -defparam \I2C_SDAT~input .bus_hold = "false"; -defparam \I2C_SDAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hEFE0; -defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|thisbyte[0]~7_combout & \ula_|i2c_loader_|nbyte[0]~1_combout )))) - - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|thisbyte[0]~7_combout ), - .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hD888; -defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[0]~3_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|nbyte[0]~2_combout )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), - .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h3000; -defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N29 -dffeas \ula_|i2c_loader_|nbyte[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbyte~4_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbyte [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbyte[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Stop~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h1010; -defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Stop~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))) # -// (!\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Stop~q )))) - - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Stop~q ), - .datad(\ula_|i2c_loader_|state.Stop~0_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Stop~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF4B0; -defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N3 -dffeas \ula_|i2c_loader_|state.Stop ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Stop~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Stop~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Ack~q ))) - - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Ack~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Idle~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; -defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])))) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|nbit [0]), - .datac(\ula_|i2c_loader_|nbit [2]), - .datad(\ula_|i2c_loader_|nbit [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; -defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N1 -dffeas \ula_|i2c_loader_|nbit[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~0_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [0]))) - - .dataa(\ula_|i2c_loader_|nbit [1]), - .datab(\ula_|i2c_loader_|nbit [2]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|nbit [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~0 .lut_mask = 16'h0010; -defparam \ula_|i2c_loader_|state.Done~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Done~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|state.Idle~0_combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), - .datad(\ula_|i2c_loader_|state.Done~0_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hAF2F; -defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Data~q ))))) # -// (!\ula_|i2c_loader_|state.Ack~0_combout & (((\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|state.Ack~0_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF2D0; -defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N31 -dffeas \ula_|i2c_loader_|state.Ack ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Ack~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Ack~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hEFE0; -defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[1]~5_combout ))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h0800; -defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y23_N15 -dffeas \ula_|i2c_loader_|thisbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), - .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; -defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N17 -dffeas \ula_|i2c_loader_|thisbyte[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) -// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), - .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hC30C; -defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N19 -dffeas \ula_|i2c_loader_|thisbyte[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), - .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; -defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N21 -dffeas \ula_|i2c_loader_|thisbyte[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( -// Equation(s): -// \ula_|i2c_loader_|Equal2~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0002; -defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~0_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]))) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Stop~q )))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h5FCC; -defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) - - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), - .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; -defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N23 -dffeas \ula_|i2c_loader_|thisbyte[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~1_combout = (\ula_|i2c_loader_|state.Pause~0_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|Equal2~0_combout ), - .datac(\ula_|i2c_loader_|state.Pause~0_combout ), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h30F0; -defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~2_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Done~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & -// (\ula_|i2c_loader_|state.Data~q & ((!\ula_|i2c_loader_|state.Done~1_combout )))) - - .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Done~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~2 .lut_mask = 16'h0ACE; -defparam \ula_|i2c_loader_|state.Done~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~2_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Done~2_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Done~2_combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'hC4FF; -defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Pause~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~2_combout & (\ula_|i2c_loader_|state.Pause~1_combout )) # -// (!\ula_|i2c_loader_|state.Pause~2_combout & ((\ula_|i2c_loader_|state.Pause~q ))))) - - .dataa(\ula_|i2c_loader_|state.Pause~1_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Pause~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'hE2F0; -defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N23 -dffeas \ula_|i2c_loader_|state.Pause ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Pause~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Pause~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( -// Equation(s): -// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # -// (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Pause~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h38FF; -defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N31 -dffeas \ula_|i2c_loader_|state.Start ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state~25_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Start~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Start .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Start~q )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [0]), - .datad(\ula_|i2c_loader_|state.Start~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h000C; -defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N11 -dffeas \ula_|i2c_loader_|nbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbyte~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & !\ula_|i2c_loader_|state.Data~q )) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0005; -defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h47CF; -defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # ((\ula_|i2c_loader_|nbit[0]~2_combout ) # (\ula_|i2c_loader_|state.Done~0_combout )))) - - .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), - .datab(\ula_|i2c_loader_|nbit[0]~2_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Done~0_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h0F0E; -defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~4 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~4_combout = (!\ula_|i2c_loader_|nbit[0]~3_combout & (\ula_|i2c_loader_|Mux42~0_combout & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q ))) - - .dataa(\ula_|i2c_loader_|nbit[0]~3_combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~4 .lut_mask = 16'h0400; -defparam \ula_|i2c_loader_|nbit[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N3 -dffeas \ula_|i2c_loader_|nbit[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~5_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbit [1]), - .datad(\ula_|i2c_loader_|nbit [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hF55F; -defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N13 -dffeas \ula_|i2c_loader_|nbit[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~6_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~1_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & !\ula_|i2c_loader_|nbit [0])) - - .dataa(\ula_|i2c_loader_|nbit [1]), - .datab(\ula_|i2c_loader_|nbit [2]), - .datac(gnd), - .datad(\ula_|i2c_loader_|nbit [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~1 .lut_mask = 16'h0011; -defparam \ula_|i2c_loader_|state.Done~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( -// Equation(s): -// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Done~1_combout ) # (!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Done~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h5FFF; -defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( -// Equation(s): -// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hE0E0; -defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( -// Equation(s): -// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state~24_combout )) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state~24_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hA000; -defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~27_combout )) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~26_combout ))) - - .dataa(\ula_|i2c_loader_|state~27_combout ), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state~26_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Data~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hAFA0; -defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N29 -dffeas \ula_|i2c_loader_|state.Data ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Data~0_combout ), - .asdata(\ula_|i2c_loader_|Mux42~0_combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2c_loader_|state.Start~q ), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Data~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Data .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( -// Equation(s): -// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Stop~q )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Stop~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|scl_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0003; -defparam \ula_|i2c_loader_|scl_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - // Location: FF_X1_Y23_N13 dffeas \ula_|i2c_loader_|scl_out~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), @@ -54958,38 +54438,1113 @@ defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~1 ( +// Location: LCCOMB_X2_Y24_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( // Equation(s): -// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Start~q $ (((!\ula_|i2c_loader_|scl_out~_Duplicate_1_q ))))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # -// ((\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|scl_out~_Duplicate_1_q )))) +// \ula_|i2c_loader_|state.Idle~feeder_combout = VCC - .dataa(\ula_|i2c_loader_|state.Start~q ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Idle~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; +defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N23 +dffeas \ula_|i2c_loader_|state.Idle ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Idle~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Idle~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Idle .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Idle .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|phase~0 ( +// Equation(s): +// \ula_|i2c_loader_|phase~0_combout = (!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|phase~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|phase~0 .lut_mask = 16'h0F00; +defparam \ula_|i2c_loader_|phase~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N9 +dffeas \ula_|i2c_loader_|phase[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|phase~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|phase [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|phase[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|phase[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|phase~1 ( +// Equation(s): +// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [0] $ (\ula_|i2c_loader_|phase [1]))) + + .dataa(gnd), .datab(\ula_|i2c_loader_|phase [0]), .datac(\ula_|i2c_loader_|phase [1]), - .datad(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|phase~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h3C00; +defparam \ula_|i2c_loader_|phase~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y24_N29 +dffeas \ula_|i2c_loader_|phase[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|phase~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|phase [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|phase[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|phase[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( +// Equation(s): +// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|phase [0]) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2c_loader_|Mux42~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hC0C0; +defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|phase [0])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|phase [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y25_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~4_combout = (!\ula_|i2c_loader_|state.Data~q ) # (!\ula_|i2c_loader_|nbit [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|nbit [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~4 .lut_mask = 16'h0FFF; +defparam \ula_|i2c_loader_|nbit~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [0] $ (!\ula_|i2c_loader_|nbyte [1])))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|phase [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hEDCC; +defparam \ula_|i2c_loader_|nbyte~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y23_N31 +dffeas \ula_|i2c_loader_|nbyte[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbyte~4_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbyte [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbyte[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~1_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'hFC00; +defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Start~q ) # ((!\ula_|i2c_loader_|state.Pause~0_combout & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # (\ula_|i2c_loader_|state.Data~q )))) + + .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Pause~0_combout ), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'hCFCE; +defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~3_combout = (\ula_|i2c_loader_|Mux42~0_combout & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|nbit[0]~2_combout ))) + + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Idle~q ), + .datad(\ula_|i2c_loader_|nbit[0]~2_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h2000; +defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y25_N27 +dffeas \ula_|i2c_loader_|nbit[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~4_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y25_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~5_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(gnd), + .datac(\ula_|i2c_loader_|nbit [1]), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'hF55F; +defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y25_N1 +dffeas \ula_|i2c_loader_|nbit[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~5_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y25_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~1_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [1] & !\ula_|i2c_loader_|nbit [0])) + + .dataa(\ula_|i2c_loader_|nbit [2]), + .datab(\ula_|i2c_loader_|nbit [1]), + .datac(gnd), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h0011; +defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( +// Equation(s): +// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Pause~1_combout ) # (!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Pause~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h3FFF; +defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( +// Equation(s): +// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hFC00; +defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( +// Equation(s): +// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state~24_combout )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state~24_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hC000; +defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~27_combout )) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~26_combout ))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state~27_combout ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|state~26_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Data~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hCFC0; +defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N5 +dffeas \ula_|i2c_loader_|state.Data ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Data~0_combout ), + .asdata(\ula_|i2c_loader_|Mux42~0_combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2c_loader_|state.Start~q ), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Data~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Data .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y25_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [1] & !\ula_|i2c_loader_|nbit [0])))) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|nbit [1]), + .datac(\ula_|i2c_loader_|nbit [2]), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; +defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y25_N13 +dffeas \ula_|i2c_loader_|nbit[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y25_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~0_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [0] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [1]))) + + .dataa(\ula_|i2c_loader_|nbit [2]), + .datab(\ula_|i2c_loader_|nbit [0]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|nbit [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h0010; +defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Pause~q ))) + + .dataa(\ula_|i2c_loader_|state.Stop~q ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Pause~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Idle~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; +defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Pause~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|state.Pause~0_combout ), + .datad(\ula_|i2c_loader_|state.Idle~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hB3BB; +defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|state.Data~q ))) # +// (!\ula_|i2c_loader_|state.Ack~0_combout & (\ula_|i2c_loader_|state.Ack~q )))) + + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|state.Ack~0_combout ), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF4B0; +defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N25 +dffeas \ula_|i2c_loader_|state.Ack ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Ack~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Ack~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state.Ack~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hF000; +defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y23_N1 +cycloneive_io_ibuf \I2C_SDAT~input ( + .i(I2C_SDAT), + .ibar(gnd), + .o(\I2C_SDAT~input_o )); +// synopsys translate_off +defparam \I2C_SDAT~input .bus_hold = "false"; +defparam \I2C_SDAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hFBC8; +defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|Mux42~0_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|thisbyte[0]~7_combout & ((\ula_|i2c_loader_|nbyte[0]~1_combout )))) + + .dataa(\ula_|i2c_loader_|thisbyte[0]~7_combout ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|nbyte[0]~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hCAC0; +defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[0]~3_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[0]~2_combout )) + + .dataa(\ula_|i2c_loader_|state.Idle~q ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(gnd), + .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h2200; +defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y23_N21 +dffeas \ula_|i2c_loader_|nbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|i2c_loader_|nbyte~0_combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Stop~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Stop~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))))) # +// (!\ula_|i2c_loader_|Mux42~0_combout & (((\ula_|i2c_loader_|state.Stop~q )))) + + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Stop~q ), + .datad(\ula_|i2c_loader_|state.Stop~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Stop~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF2D0; +defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N7 +dffeas \ula_|i2c_loader_|state.Stop ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Stop~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Stop~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0]) # (!\ula_|i2c_loader_|phase [1])))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state.Stop~q )) + + .dataa(\ula_|i2c_loader_|state.Stop~q ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|phase [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'h2EEE; +defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) +// \ula_|i2c_loader_|thisbyte[0]~9 = CARRY(\ula_|i2c_loader_|thisbyte [0]) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~8_combout ), + .cout(\ula_|i2c_loader_|thisbyte[0]~9 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; +defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) + + .dataa(\ula_|i2c_loader_|nbyte [0]), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hFBC8; +defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~18_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q & (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|nbyte[1]~5_combout ))) + + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [1]), + .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h4000; +defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y23_N19 +dffeas \ula_|i2c_loader_|thisbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), + .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y23_N21 +dffeas \ula_|i2c_loader_|thisbyte[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) +// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) + + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), + .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hA50A; +defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y23_N23 +dffeas \ula_|i2c_loader_|thisbyte[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), + .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y23_N25 +dffeas \ula_|i2c_loader_|thisbyte[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( +// Equation(s): +// \ula_|i2c_loader_|Equal2~0_combout = (!\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte [3]))) + + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0010; +defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) + + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), + .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; +defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y23_N27 +dffeas \ula_|i2c_loader_|thisbyte[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|state.Pause~2_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Pause~2_combout ), + .datac(\ula_|i2c_loader_|Equal2~0_combout ), + .datad(\ula_|i2c_loader_|thisbyte [4]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'h0CCC; +defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( +// Equation(s): +// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Data~q )) + + .dataa(\ula_|i2c_loader_|state.Stop~q ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|scl_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0011; +defparam \ula_|i2c_loader_|scl_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~4 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~4_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Pause~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & +// (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Pause~1_combout )))) + + .dataa(\ula_|i2c_loader_|scl_out~0_combout ), + .datab(\ula_|i2c_loader_|state.Pause~q ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|state.Pause~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~4 .lut_mask = 16'h22F2; +defparam \ula_|i2c_loader_|state.Pause~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~5 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~5_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Pause~4_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Pause~4_combout ), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|Mux42~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~5 .lut_mask = 16'hF733; +defparam \ula_|i2c_loader_|state.Pause~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~6 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~6_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Pause~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~5_combout & (\ula_|i2c_loader_|state.Pause~3_combout )) # +// (!\ula_|i2c_loader_|state.Pause~5_combout & ((\ula_|i2c_loader_|state.Pause~q ))))) + + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|state.Pause~3_combout ), + .datac(\ula_|i2c_loader_|state.Pause~q ), + .datad(\ula_|i2c_loader_|state.Pause~5_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~6 .lut_mask = 16'hE4F0; +defparam \ula_|i2c_loader_|state.Pause~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N21 +dffeas \ula_|i2c_loader_|state.Pause ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Pause~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Pause~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( +// Equation(s): +// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # +// (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|state.Pause~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h58FF; +defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N31 +dffeas \ula_|i2c_loader_|state.Start ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state~25_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Start~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Start .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~1 ( +// Equation(s): +// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|scl_out~_Duplicate_1_q $ (((!\ula_|i2c_loader_|state.Start~q ))))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # +// ((\ula_|i2c_loader_|scl_out~_Duplicate_1_q & \ula_|i2c_loader_|state.Start~q )))) + + .dataa(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|phase [0]), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hBA74; +defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hA5EC; defparam \ula_|i2c_loader_|scl_out~1 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X1_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~2 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|scl_out~1_combout & ((\ula_|i2c_loader_|state.Start~q ))) # (!\ula_|i2c_loader_|scl_out~1_combout & (!\ula_|i2c_loader_|scl_out~0_combout & !\ula_|i2c_loader_|state.Start~q )) +// \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|scl_out~1_combout & (\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|scl_out~1_combout & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|scl_out~0_combout )) - .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(\ula_|i2c_loader_|scl_out~1_combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|state.Start~q ), + .dataa(\ula_|i2c_loader_|scl_out~1_combout ), + .datab(gnd), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|scl_out~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hCC11; +defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hA0A5; defparam \ula_|i2c_loader_|scl_out~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -55031,15 +55586,32 @@ defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N10 +// Location: LCCOMB_X3_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( +// Equation(s): +// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [3]) # (!\ula_|i2c_loader_|thisbyte [1])))) + + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Mux35~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h20A0; +defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~4 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Start~q ) +// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Data~q ) .dataa(gnd), .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~4_combout ), .cout()); @@ -55048,146 +55620,146 @@ defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h000F; defparam \ula_|i2c_loader_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( +// Location: LCCOMB_X3_Y23_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( // Equation(s): -// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [1]) # (!\ula_|i2c_loader_|thisbyte [3])))) +// \ula_|i2c_loader_|shiftreg~19_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1])) # (!\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [3]))))) .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [1]), - .datad(\ula_|i2c_loader_|thisbyte [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Mux35~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h2A00; -defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) - - .dataa(\ula_|i2c_loader_|thisbyte [4]), .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h001A; -defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~14_combout = (\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2]) - - .dataa(gnd), - .datab(gnd), .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [3]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~14_combout ), + .combout(\ula_|i2c_loader_|shiftreg~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h00F0; -defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h202A; +defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( +// Location: LCCOMB_X3_Y23_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|shiftreg~13_combout ) # ((!\ula_|i2c_loader_|thisbyte [3] & (\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|shiftreg~14_combout ))) +// \ula_|i2c_loader_|shiftreg~20_combout = ((\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|shiftreg~19_combout ))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) - .dataa(\ula_|i2c_loader_|shiftreg~13_combout ), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|shiftreg~14_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'hAABA; -defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~24 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~24_combout = (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|thisbyte [0])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|shiftreg~4_combout ), + .datac(\ula_|i2c_loader_|shiftreg~19_combout ), .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~24_combout ), + .combout(\ula_|i2c_loader_|shiftreg~20_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~24 .lut_mask = 16'h0300; -defparam \ula_|i2c_loader_|shiftreg[0]~24 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'h73FB; +defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N14 +// Location: LCCOMB_X3_Y23_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [3]))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [3])))) + + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [0]), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h8804; +defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~23 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~23_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~22_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) + + .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|shiftreg~22_combout ), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hA0A8; +defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~25 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[0]~25_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|thisbyte [3] & \ula_|i2c_loader_|thisbyte [0])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|thisbyte [3]), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg[0]~25 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|shiftreg[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N12 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~6 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~6_combout = (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|shiftreg[0]~6_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|phase [0] & !\ula_|i2c_loader_|phase [1])) - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|phase [1]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h5000; +defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h00C0; defparam \ula_|i2c_loader_|shiftreg[0]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N0 +// Location: LCCOMB_X2_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~7 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|state~24_combout )))) +// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state~24_combout ) # (\ula_|i2c_loader_|state.Start~q )))) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|shiftreg[0]~6_combout ), - .datad(\ula_|i2c_loader_|state~24_combout ), + .dataa(\ula_|i2c_loader_|shiftreg[0]~6_combout ), + .datab(\ula_|i2c_loader_|state~24_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|Mux42~0_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFCF8; +defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFEAA; defparam \ula_|i2c_loader_|shiftreg[0]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N10 +// Location: LCCOMB_X2_Y24_N0 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~8 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~8_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|shiftreg[0]~7_combout )) +// \ula_|i2c_loader_|shiftreg[0]~8_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|shiftreg[0]~7_combout & \ula_|i2c_loader_|state.Idle~q )) - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Idle~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|shiftreg[0]~7_combout ), + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|shiftreg[0]~7_combout ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Idle~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h0C00; +defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h4400; defparam \ula_|i2c_loader_|shiftreg[0]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N13 +// Location: FF_X3_Y24_N21 dffeas \ula_|i2c_loader_|shiftreg[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg[0]~24_combout ), + .d(\ula_|i2c_loader_|shiftreg[0]~25_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -55203,102 +55775,85 @@ defparam \ula_|i2c_loader_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( +// Location: LCCOMB_X3_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~24 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte [2]))) # (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2])))) +// \ula_|i2c_loader_|shiftreg~24_combout = (\ula_|i2c_loader_|shiftreg~23_combout ) # ((\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [0])) - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~21_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hC010; -defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~21_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) - - .dataa(\ula_|i2c_loader_|shiftreg~21_combout ), - .datab(\ula_|i2c_loader_|shiftreg~4_combout ), - .datac(\ula_|i2c_loader_|thisbyte [1]), - .datad(\ula_|i2c_loader_|thisbyte [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h88C8; -defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~23 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~23_combout = (\ula_|i2c_loader_|shiftreg~22_combout ) # ((\ula_|i2c_loader_|shiftreg [0] & \ula_|i2c_loader_|state.Data~q )) - - .dataa(\ula_|i2c_loader_|shiftreg [0]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|shiftreg~23_combout ), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~22_combout ), + .datad(\ula_|i2c_loader_|shiftreg [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~23_combout ), + .combout(\ula_|i2c_loader_|shiftreg~24_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hFFA0; -defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~24 .lut_mask = 16'hFCCC; +defparam \ula_|i2c_loader_|shiftreg~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N10 +// Location: LCCOMB_X2_Y24_N6 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~10 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state.Start~q ) # ((!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|state~24_combout )))) # (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Data~q -// & (!\ula_|i2c_loader_|state.Start~q ))) +// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|phase [1]) # (!\ula_|i2c_loader_|phase [0])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state~24_combout )) - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state~24_combout ), + .dataa(\ula_|i2c_loader_|state.Data~q ), + .datab(\ula_|i2c_loader_|state~24_combout ), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|phase [1]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hA6A4; +defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hBB1B; defparam \ula_|i2c_loader_|shiftreg[6]~10 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X2_Y24_N24 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~11 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|shiftreg[6]~10_combout ))) +// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg[6]~10_combout ) # ((!\ula_|i2c_loader_|Mux42~0_combout & +// !\ula_|i2c_loader_|state.Data~q )))) - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), + .dataa(\ula_|i2c_loader_|Mux42~0_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), .datad(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~11_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~11 .lut_mask = 16'h2000; +defparam \ula_|i2c_loader_|shiftreg[6]~11 .lut_mask = 16'h5F51; defparam \ula_|i2c_loader_|shiftreg[6]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N23 +// Location: LCCOMB_X2_Y24_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~12 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[6]~12_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (!\ula_|i2c_loader_|shiftreg[6]~11_combout & \ula_|i2c_loader_|state.Idle~q )) + + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg[6]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg[6]~12 .lut_mask = 16'h1100; +defparam \ula_|i2c_loader_|shiftreg[6]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N13 dffeas \ula_|i2c_loader_|shiftreg[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~23_combout ), + .d(\ula_|i2c_loader_|shiftreg~24_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [1]), @@ -55308,67 +55863,33 @@ defparam \ula_|i2c_loader_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( +// Location: LCCOMB_X3_Y24_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [1]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [3])))) +// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|shiftreg~20_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h10B0; -defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~19_combout = ((\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [0])) # (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|shiftreg~18_combout )))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(\ula_|i2c_loader_|shiftreg~18_combout ), - .datad(\ula_|i2c_loader_|shiftreg~4_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h74FF; -defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~20_combout = (\ula_|i2c_loader_|shiftreg~19_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) - - .dataa(\ula_|i2c_loader_|shiftreg [1]), + .dataa(\ula_|i2c_loader_|shiftreg~20_combout ), .datab(gnd), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~19_combout ), + .datad(\ula_|i2c_loader_|shiftreg [1]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~20_combout ), + .combout(\ula_|i2c_loader_|shiftreg~21_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'hAF00; -defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hAA0A; +defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N3 +// Location: FF_X3_Y24_N11 dffeas \ula_|i2c_loader_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~20_combout ), + .d(\ula_|i2c_loader_|shiftreg~21_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [2]), @@ -55378,67 +55899,84 @@ defparam \ula_|i2c_loader_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( +// Location: LCCOMB_X3_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) +// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) .dataa(\ula_|i2c_loader_|thisbyte [2]), .datab(\ula_|i2c_loader_|thisbyte [1]), .datac(\ula_|i2c_loader_|thisbyte [4]), .datad(\ula_|i2c_loader_|thisbyte [3]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'h10BA; -defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~16_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [3] & ((!\ula_|i2c_loader_|shiftreg~14_combout )))) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|shiftreg~16_combout ), - .datad(\ula_|i2c_loader_|shiftreg~14_combout ), - .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'hA0E4; +defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'h10BA; defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( +// Location: LCCOMB_X3_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [2])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg~17_combout )))) +// \ula_|i2c_loader_|shiftreg~15_combout = (!\ula_|i2c_loader_|thisbyte [2] & \ula_|i2c_loader_|thisbyte [4]) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|shiftreg [2]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~17_combout ), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(gnd), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(gnd), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~26_combout ), + .combout(\ula_|i2c_loader_|shiftreg~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hC5C0; -defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'h5050; +defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N7 +// Location: LCCOMB_X3_Y24_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|shiftreg~17_combout )) # (!\ula_|i2c_loader_|thisbyte [0] & (((!\ula_|i2c_loader_|shiftreg~15_combout & \ula_|i2c_loader_|thisbyte [3])))) + + .dataa(\ula_|i2c_loader_|shiftreg~17_combout ), + .datab(\ula_|i2c_loader_|shiftreg~15_combout ), + .datac(\ula_|i2c_loader_|thisbyte [3]), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'hAA30; +defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~27 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~27_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [2])) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|shiftreg~18_combout )))) + + .dataa(\ula_|i2c_loader_|shiftreg [2]), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg~18_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~27 .lut_mask = 16'hA3A0; +defparam \ula_|i2c_loader_|shiftreg~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N23 dffeas \ula_|i2c_loader_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~26_combout ), + .d(\ula_|i2c_loader_|shiftreg~27_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [3]), @@ -55448,33 +55986,67 @@ defparam \ula_|i2c_loader_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~25 ( +// Location: LCCOMB_X3_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg~15_combout ) # ((\ula_|i2c_loader_|state.Start~q )))) +// \ula_|i2c_loader_|shiftreg~14_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) - .dataa(\ula_|i2c_loader_|shiftreg~15_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|shiftreg [3]), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~25_combout ), + .combout(\ula_|i2c_loader_|shiftreg~14_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hFE32; -defparam \ula_|i2c_loader_|shiftreg~25 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h0150; +defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N1 +// Location: LCCOMB_X3_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|shiftreg~14_combout ) # ((\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|thisbyte [3] & !\ula_|i2c_loader_|shiftreg~15_combout ))) + + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|shiftreg~14_combout ), + .datac(\ula_|i2c_loader_|thisbyte [3]), + .datad(\ula_|i2c_loader_|shiftreg~15_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'hCCCE; +defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y24_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [3])) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|shiftreg~16_combout )))) + + .dataa(\ula_|i2c_loader_|shiftreg [3]), + .datab(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg~16_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hAFAC; +defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y24_N15 dffeas \ula_|i2c_loader_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~25_combout ), + .d(\ula_|i2c_loader_|shiftreg~26_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [4]), @@ -55484,33 +56056,33 @@ defparam \ula_|i2c_loader_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~12 ( +// Location: LCCOMB_X4_Y24_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~12_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) +// \ula_|i2c_loader_|shiftreg~13_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) .dataa(\ula_|i2c_loader_|Mux35~0_combout ), .datab(\ula_|i2c_loader_|state.Data~q ), .datac(gnd), .datad(\ula_|i2c_loader_|shiftreg [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~12_combout ), + .combout(\ula_|i2c_loader_|shiftreg~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~12 .lut_mask = 16'hEE22; -defparam \ula_|i2c_loader_|shiftreg~12 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'hEE22; +defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N5 +// Location: FF_X4_Y24_N5 dffeas \ula_|i2c_loader_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~12_combout ), + .d(\ula_|i2c_loader_|shiftreg~13_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(\ula_|i2c_loader_|state.Start~q ), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [5]), @@ -55520,24 +56092,24 @@ defparam \ula_|i2c_loader_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N18 +// Location: LCCOMB_X3_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~9 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~9_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [5])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) +// \ula_|i2c_loader_|shiftreg~9_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [5]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) .dataa(gnd), - .datab(\ula_|i2c_loader_|shiftreg [5]), + .datab(\ula_|i2c_loader_|Mux35~0_combout ), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|Mux35~0_combout ), + .datad(\ula_|i2c_loader_|shiftreg [5]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hCFC0; +defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hFC0C; defparam \ula_|i2c_loader_|shiftreg~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N19 +// Location: FF_X3_Y24_N3 dffeas \ula_|i2c_loader_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg~9_combout ), @@ -55546,7 +56118,7 @@ dffeas \ula_|i2c_loader_|shiftreg[6] ( .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~12_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [6]), @@ -55556,7 +56128,7 @@ defparam \ula_|i2c_loader_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N4 +// Location: LCCOMB_X3_Y24_N28 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[7]~5 ( // Equation(s): // \ula_|i2c_loader_|shiftreg[7]~5_combout = (\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [6]) @@ -55573,7 +56145,7 @@ defparam \ula_|i2c_loader_|shiftreg[7]~5 .lut_mask = 16'hF000; defparam \ula_|i2c_loader_|shiftreg[7]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N5 +// Location: FF_X3_Y24_N29 dffeas \ula_|i2c_loader_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg[7]~5_combout ), @@ -55592,42 +56164,42 @@ defparam \ula_|i2c_loader_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N12 +// Location: LCCOMB_X2_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~0 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|shiftreg [7]))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|state.Data~q & +// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|shiftreg [7])) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|state.Ack~q ))))) # (!\ula_|i2c_loader_|state.Data~q & // (((\ula_|i2c_loader_|state.Ack~q )))) - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|phase [0]), + .dataa(\ula_|i2c_loader_|shiftreg [7]), + .datab(\ula_|i2c_loader_|state.Data~q ), .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|shiftreg [7]), + .datad(\ula_|i2c_loader_|phase [0]), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hF870; +defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hB8F0; defparam \ula_|i2c_loader_|sda_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N6 +// Location: LCCOMB_X1_Y23_N18 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~1 ( // Equation(s): // \ula_|i2c_loader_|sda_out~1_combout = (\ula_|i2c_loader_|sda_out~0_combout & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|shiftreg~4_combout & !\I2C_SDAT~input_o )))) - .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), + .dataa(\ula_|i2c_loader_|sda_out~0_combout ), .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|sda_out~0_combout ), + .datac(\ula_|i2c_loader_|shiftreg~4_combout ), .datad(\I2C_SDAT~input_o ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'hC0E0; +defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'h88A8; defparam \ula_|i2c_loader_|sda_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N8 +// Location: LCCOMB_X1_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~2 ( // Equation(s): // \ula_|i2c_loader_|sda_out~2_combout = (!\ula_|i2c_loader_|sda_out~_Duplicate_1_q & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|phase [1] & !\ula_|i2c_loader_|sda_out~1_combout )))) @@ -55644,7 +56216,7 @@ defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h4454; defparam \ula_|i2c_loader_|sda_out~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N2 +// Location: LCCOMB_X1_Y23_N6 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~3 ( // Equation(s): // \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )) # (!\ula_|i2c_loader_|phase [1] & ((!\ula_|i2c_loader_|sda_out~1_combout ))))) # (!\ula_|i2c_loader_|phase @@ -55698,7 +56270,2727 @@ defparam \ula_|i2c_loader_|sda_out .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out .power_up = "high"; // synopsys translate_on -// Location: LCCOMB_X27_Y23_N16 +// Location: PLL_1 +cycloneive_pll \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 ( + .areset(gnd), + .pfdena(vcc), + .fbin(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\CLOCK_50~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(), + .vcooverrange(), + .vcounderrange(), + .fbout(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c0_high = 3; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c0_initial = 2; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c0_low = 2; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c0_mode = "odd"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c0_ph = 4; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_high = 3; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_initial = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_low = 2; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_mode = "odd"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk0_counter = "c1"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk0_divide_by = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk0_multiply_by = 2; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk1_counter = "c0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk1_divide_by = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk1_multiply_by = 2; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk1_phase_shift = "3000"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .m = 10; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .n = 1; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .pll_compensation_delay = 3323; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 250; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N14 +cycloneive_lcell_comb \sdram_|Mux38~0 ( +// Equation(s): +// \sdram_|Mux38~0_combout = (\sdram_|r.rd_pending~q & (((\sdram_|Mux39~1_combout )))) # (!\sdram_|r.rd_pending~q & (\z80_|control_pins_|pin_nIORQ~1_combout & (\Equal2~1_combout ))) + + .dataa(\z80_|control_pins_|pin_nIORQ~1_combout ), + .datab(\Equal2~1_combout ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Mux39~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux38~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux38~0 .lut_mask = 16'hF808; +defparam \sdram_|Mux38~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y12_N15 +dffeas \sdram_|r.rd_pending ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux38~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rd_pending~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rd_pending .is_wysiwyg = "true"; +defparam \sdram_|r.rd_pending .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N0 +cycloneive_lcell_comb \sdram_|r.rf_counter[0]~12 ( +// Equation(s): +// \sdram_|r.rf_counter[0]~12_combout = \sdram_|r.rf_counter [0] $ (VCC) +// \sdram_|r.rf_counter[0]~13 = CARRY(\sdram_|r.rf_counter [0]) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_|r.rf_counter[0]~12_combout ), + .cout(\sdram_|r.rf_counter[0]~13 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[0]~12 .lut_mask = 16'h33CC; +defparam \sdram_|r.rf_counter[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N26 +cycloneive_lcell_comb \sdram_|r.rf_counter[3]~32 ( +// Equation(s): +// \sdram_|r.rf_counter[3]~32_combout = ((!\sdram_|r.state [5] & (\sdram_|r.address[3]~6_combout & !\sdram_|r.state [4]))) # (!\sdram_|Equal0~2_combout ) + + .dataa(\sdram_|Equal0~2_combout ), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.address[3]~6_combout ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|r.rf_counter[3]~32_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.rf_counter[3]~32 .lut_mask = 16'h5575; +defparam \sdram_|r.rf_counter[3]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y13_N1 +dffeas \sdram_|r.rf_counter[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[0]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[0] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N2 +cycloneive_lcell_comb \sdram_|r.rf_counter[1]~14 ( +// Equation(s): +// \sdram_|r.rf_counter[1]~14_combout = (\sdram_|r.rf_counter [1] & (!\sdram_|r.rf_counter[0]~13 )) # (!\sdram_|r.rf_counter [1] & ((\sdram_|r.rf_counter[0]~13 ) # (GND))) +// \sdram_|r.rf_counter[1]~15 = CARRY((!\sdram_|r.rf_counter[0]~13 ) # (!\sdram_|r.rf_counter [1])) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[0]~13 ), + .combout(\sdram_|r.rf_counter[1]~14_combout ), + .cout(\sdram_|r.rf_counter[1]~15 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[1]~14 .lut_mask = 16'h3C3F; +defparam \sdram_|r.rf_counter[1]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N3 +dffeas \sdram_|r.rf_counter[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[1]~14_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[1] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N4 +cycloneive_lcell_comb \sdram_|r.rf_counter[2]~16 ( +// Equation(s): +// \sdram_|r.rf_counter[2]~16_combout = (\sdram_|r.rf_counter [2] & (\sdram_|r.rf_counter[1]~15 $ (GND))) # (!\sdram_|r.rf_counter [2] & (!\sdram_|r.rf_counter[1]~15 & VCC)) +// \sdram_|r.rf_counter[2]~17 = CARRY((\sdram_|r.rf_counter [2] & !\sdram_|r.rf_counter[1]~15 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[1]~15 ), + .combout(\sdram_|r.rf_counter[2]~16_combout ), + .cout(\sdram_|r.rf_counter[2]~17 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[2]~16 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[2]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N5 +dffeas \sdram_|r.rf_counter[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[2]~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[2] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N6 +cycloneive_lcell_comb \sdram_|r.rf_counter[3]~18 ( +// Equation(s): +// \sdram_|r.rf_counter[3]~18_combout = (\sdram_|r.rf_counter [3] & (!\sdram_|r.rf_counter[2]~17 )) # (!\sdram_|r.rf_counter [3] & ((\sdram_|r.rf_counter[2]~17 ) # (GND))) +// \sdram_|r.rf_counter[3]~19 = CARRY((!\sdram_|r.rf_counter[2]~17 ) # (!\sdram_|r.rf_counter [3])) + + .dataa(\sdram_|r.rf_counter [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[2]~17 ), + .combout(\sdram_|r.rf_counter[3]~18_combout ), + .cout(\sdram_|r.rf_counter[3]~19 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[3]~18 .lut_mask = 16'h5A5F; +defparam \sdram_|r.rf_counter[3]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N7 +dffeas \sdram_|r.rf_counter[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[3]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[3] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N8 +cycloneive_lcell_comb \sdram_|r.rf_counter[4]~20 ( +// Equation(s): +// \sdram_|r.rf_counter[4]~20_combout = (\sdram_|r.rf_counter [4] & (\sdram_|r.rf_counter[3]~19 $ (GND))) # (!\sdram_|r.rf_counter [4] & (!\sdram_|r.rf_counter[3]~19 & VCC)) +// \sdram_|r.rf_counter[4]~21 = CARRY((\sdram_|r.rf_counter [4] & !\sdram_|r.rf_counter[3]~19 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[3]~19 ), + .combout(\sdram_|r.rf_counter[4]~20_combout ), + .cout(\sdram_|r.rf_counter[4]~21 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[4]~20 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[4]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N9 +dffeas \sdram_|r.rf_counter[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[4]~20_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[4] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N10 +cycloneive_lcell_comb \sdram_|r.rf_counter[5]~22 ( +// Equation(s): +// \sdram_|r.rf_counter[5]~22_combout = (\sdram_|r.rf_counter [5] & (!\sdram_|r.rf_counter[4]~21 )) # (!\sdram_|r.rf_counter [5] & ((\sdram_|r.rf_counter[4]~21 ) # (GND))) +// \sdram_|r.rf_counter[5]~23 = CARRY((!\sdram_|r.rf_counter[4]~21 ) # (!\sdram_|r.rf_counter [5])) + + .dataa(\sdram_|r.rf_counter [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[4]~21 ), + .combout(\sdram_|r.rf_counter[5]~22_combout ), + .cout(\sdram_|r.rf_counter[5]~23 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[5]~22 .lut_mask = 16'h5A5F; +defparam \sdram_|r.rf_counter[5]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N11 +dffeas \sdram_|r.rf_counter[5] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[5]~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[5] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N12 +cycloneive_lcell_comb \sdram_|r.rf_counter[6]~24 ( +// Equation(s): +// \sdram_|r.rf_counter[6]~24_combout = (\sdram_|r.rf_counter [6] & (\sdram_|r.rf_counter[5]~23 $ (GND))) # (!\sdram_|r.rf_counter [6] & (!\sdram_|r.rf_counter[5]~23 & VCC)) +// \sdram_|r.rf_counter[6]~25 = CARRY((\sdram_|r.rf_counter [6] & !\sdram_|r.rf_counter[5]~23 )) + + .dataa(\sdram_|r.rf_counter [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[5]~23 ), + .combout(\sdram_|r.rf_counter[6]~24_combout ), + .cout(\sdram_|r.rf_counter[6]~25 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[6]~24 .lut_mask = 16'hA50A; +defparam \sdram_|r.rf_counter[6]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N13 +dffeas \sdram_|r.rf_counter[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[6]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[6] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N14 +cycloneive_lcell_comb \sdram_|r.rf_counter[7]~26 ( +// Equation(s): +// \sdram_|r.rf_counter[7]~26_combout = (\sdram_|r.rf_counter [7] & (!\sdram_|r.rf_counter[6]~25 )) # (!\sdram_|r.rf_counter [7] & ((\sdram_|r.rf_counter[6]~25 ) # (GND))) +// \sdram_|r.rf_counter[7]~27 = CARRY((!\sdram_|r.rf_counter[6]~25 ) # (!\sdram_|r.rf_counter [7])) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[6]~25 ), + .combout(\sdram_|r.rf_counter[7]~26_combout ), + .cout(\sdram_|r.rf_counter[7]~27 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[7]~26 .lut_mask = 16'h3C3F; +defparam \sdram_|r.rf_counter[7]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N15 +dffeas \sdram_|r.rf_counter[7] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[7]~26_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[7] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N24 +cycloneive_lcell_comb \sdram_|Equal0~1 ( +// Equation(s): +// \sdram_|Equal0~1_combout = (\sdram_|r.rf_counter [5]) # ((\sdram_|r.rf_counter [7]) # ((\sdram_|r.rf_counter [4]) # (\sdram_|r.rf_counter [6]))) + + .dataa(\sdram_|r.rf_counter [5]), + .datab(\sdram_|r.rf_counter [7]), + .datac(\sdram_|r.rf_counter [4]), + .datad(\sdram_|r.rf_counter [6]), + .cin(gnd), + .combout(\sdram_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~1 .lut_mask = 16'hFFFE; +defparam \sdram_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N16 +cycloneive_lcell_comb \sdram_|r.rf_counter[8]~28 ( +// Equation(s): +// \sdram_|r.rf_counter[8]~28_combout = (\sdram_|r.rf_counter [8] & (\sdram_|r.rf_counter[7]~27 $ (GND))) # (!\sdram_|r.rf_counter [8] & (!\sdram_|r.rf_counter[7]~27 & VCC)) +// \sdram_|r.rf_counter[8]~29 = CARRY((\sdram_|r.rf_counter [8] & !\sdram_|r.rf_counter[7]~27 )) + + .dataa(gnd), + .datab(\sdram_|r.rf_counter [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|r.rf_counter[7]~27 ), + .combout(\sdram_|r.rf_counter[8]~28_combout ), + .cout(\sdram_|r.rf_counter[8]~29 )); +// synopsys translate_off +defparam \sdram_|r.rf_counter[8]~28 .lut_mask = 16'hC30C; +defparam \sdram_|r.rf_counter[8]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N17 +dffeas \sdram_|r.rf_counter[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[8]~28_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[8] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N30 +cycloneive_lcell_comb \sdram_|Equal0~0 ( +// Equation(s): +// \sdram_|Equal0~0_combout = (\sdram_|r.rf_counter [3]) # ((\sdram_|r.rf_counter [0]) # ((\sdram_|r.rf_counter [2]) # (!\sdram_|r.rf_counter [1]))) + + .dataa(\sdram_|r.rf_counter [3]), + .datab(\sdram_|r.rf_counter [0]), + .datac(\sdram_|r.rf_counter [2]), + .datad(\sdram_|r.rf_counter [1]), + .cin(gnd), + .combout(\sdram_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~0 .lut_mask = 16'hFEFF; +defparam \sdram_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N18 +cycloneive_lcell_comb \sdram_|r.rf_counter[9]~30 ( +// Equation(s): +// \sdram_|r.rf_counter[9]~30_combout = \sdram_|r.rf_counter[8]~29 $ (\sdram_|r.rf_counter [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_|r.rf_counter [9]), + .cin(\sdram_|r.rf_counter[8]~29 ), + .combout(\sdram_|r.rf_counter[9]~30_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.rf_counter[9]~30 .lut_mask = 16'h0FF0; +defparam \sdram_|r.rf_counter[9]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X20_Y13_N19 +dffeas \sdram_|r.rf_counter[9] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.rf_counter[9]~30_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\sdram_|r.rf_counter[3]~32_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_counter [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_counter[9] .is_wysiwyg = "true"; +defparam \sdram_|r.rf_counter[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N22 +cycloneive_lcell_comb \sdram_|Equal0~2 ( +// Equation(s): +// \sdram_|Equal0~2_combout = (\sdram_|Equal0~1_combout ) # (((\sdram_|Equal0~0_combout ) # (!\sdram_|r.rf_counter [9])) # (!\sdram_|r.rf_counter [8])) + + .dataa(\sdram_|Equal0~1_combout ), + .datab(\sdram_|r.rf_counter [8]), + .datac(\sdram_|Equal0~0_combout ), + .datad(\sdram_|r.rf_counter [9]), + .cin(gnd), + .combout(\sdram_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal0~2 .lut_mask = 16'hFBFF; +defparam \sdram_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N28 +cycloneive_lcell_comb \sdram_|Mux13~8 ( +// Equation(s): +// \sdram_|Mux13~8_combout = (\sdram_|r.state [4] & !\sdram_|r.state [5]) + + .dataa(gnd), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [5]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|Mux13~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~8 .lut_mask = 16'h0C0C; +defparam \sdram_|Mux13~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N20 +cycloneive_lcell_comb \sdram_|Mux37~0 ( +// Equation(s): +// \sdram_|Mux37~0_combout = (\sdram_|r.rf_pending~q & (((!\sdram_|Mux13~8_combout ) # (!\sdram_|r.address[3]~6_combout )))) # (!\sdram_|r.rf_pending~q & (!\sdram_|Equal0~2_combout )) + + .dataa(\sdram_|Equal0~2_combout ), + .datab(\sdram_|r.address[3]~6_combout ), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Mux13~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux37~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux37~0 .lut_mask = 16'h35F5; +defparam \sdram_|Mux37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y13_N21 +dffeas \sdram_|r.rf_pending ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux37~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.rf_pending~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.rf_pending .is_wysiwyg = "true"; +defparam \sdram_|r.rf_pending .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N14 +cycloneive_lcell_comb \sdram_|Mux4~0 ( +// Equation(s): +// \sdram_|Mux4~0_combout = (!\sdram_|r.wr_pending~q & (\sdram_|r.rd_pending~q & (!\sdram_|r.rf_pending~q & \sdram_|Equal7~2_combout ))) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~0 .lut_mask = 16'h0400; +defparam \sdram_|Mux4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N0 +cycloneive_lcell_comb \sdram_|Mux4~1 ( +// Equation(s): +// \sdram_|Mux4~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [5] $ ((!\sdram_|r.state [4])))) # (!\sdram_|r.state [6] & (\sdram_|r.state [5] & ((!\sdram_|Mux4~0_combout ) # (!\sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|Mux4~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~1 .lut_mask = 16'h86C6; +defparam \sdram_|Mux4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N2 +cycloneive_lcell_comb \sdram_|Mux4~2 ( +// Equation(s): +// \sdram_|Mux4~2_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [5]) # ((\sdram_|r.state [4])))) # (!\sdram_|r.state [6] & ((\sdram_|Mux4~0_combout ) # ((!\sdram_|r.state [5] & \sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|Mux4~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~2 .lut_mask = 16'hFDB8; +defparam \sdram_|Mux4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N30 +cycloneive_lcell_comb \sdram_|Mux4~3 ( +// Equation(s): +// \sdram_|Mux4~3_combout = (\sdram_|Mux4~2_combout & (\sdram_|r.state [8] $ (((\sdram_|Mux4~1_combout & \sdram_|r.state [7]))))) # (!\sdram_|Mux4~2_combout & (\sdram_|r.state [8] & (\sdram_|Mux4~1_combout $ (\sdram_|r.state [7])))) + + .dataa(\sdram_|Mux4~1_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux4~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux4~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux4~3 .lut_mask = 16'h7860; +defparam \sdram_|Mux4~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y15_N31 +dffeas \sdram_|r.state[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux4~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[8] .is_wysiwyg = "true"; +defparam \sdram_|r.state[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N6 +cycloneive_lcell_comb \sdram_|r.act_row[1]~0 ( +// Equation(s): +// \sdram_|r.act_row[1]~0_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [6] & (\sdram_|r.state [5] & \sdram_|r.state [8])) # (!\sdram_|r.state [6] & (!\sdram_|r.state [5] & !\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.act_row[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.act_row[1]~0 .lut_mask = 16'h8004; +defparam \sdram_|r.act_row[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N18 +cycloneive_lcell_comb \sdram_|process_0~2 ( +// Equation(s): +// \sdram_|process_0~2_combout = (\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|process_0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~2 .lut_mask = 16'hFFF0; +defparam \sdram_|process_0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N0 +cycloneive_lcell_comb \sdram_|r.act_row[1]~1 ( +// Equation(s): +// \sdram_|r.act_row[1]~1_combout = (\sdram_|r.act_row[1]~0_combout & (\sdram_|process_0~2_combout & (\sdram_|r.state [7] $ (!\sdram_|r.state [8])))) + + .dataa(\sdram_|r.act_row[1]~0_combout ), + .datab(\sdram_|process_0~2_combout ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.act_row[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.act_row[1]~1 .lut_mask = 16'h8008; +defparam \sdram_|r.act_row[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y13_N9 +dffeas \sdram_|r.act_row[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\z80_|address_pins_|abus[15]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.act_row[1]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[4] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y13_N23 +dffeas \sdram_|r.act_row[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[1]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[3] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N20 +cycloneive_lcell_comb \sdram_|r.act_row[2]~feeder ( +// Equation(s): +// \sdram_|r.act_row[2]~feeder_combout = \z80_|address_pins_|abus[13]~23_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~23_combout ), + .cin(gnd), + .combout(\sdram_|r.act_row[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.act_row[2]~feeder .lut_mask = 16'hFF00; +defparam \sdram_|r.act_row[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y13_N21 +dffeas \sdram_|r.act_row[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.act_row[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.act_row[1]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[2] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N22 +cycloneive_lcell_comb \sdram_|Equal7~1 ( +// Equation(s): +// \sdram_|Equal7~1_combout = (\z80_|address_pins_|abus[14]~22_combout & (\sdram_|r.act_row [3] & (\z80_|address_pins_|abus[13]~23_combout $ (!\sdram_|r.act_row [2])))) # (!\z80_|address_pins_|abus[14]~22_combout & (!\sdram_|r.act_row [3] & +// (\z80_|address_pins_|abus[13]~23_combout $ (!\sdram_|r.act_row [2])))) + + .dataa(\z80_|address_pins_|abus[14]~22_combout ), + .datab(\z80_|address_pins_|abus[13]~23_combout ), + .datac(\sdram_|r.act_row [3]), + .datad(\sdram_|r.act_row [2]), + .cin(gnd), + .combout(\sdram_|Equal7~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal7~1 .lut_mask = 16'h8421; +defparam \sdram_|Equal7~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y13_N3 +dffeas \sdram_|r.act_row[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[12]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[1]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[1] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y13_N13 +dffeas \sdram_|r.act_row[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[11]~19_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_|r.act_row[1]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.act_row [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.act_row[0] .is_wysiwyg = "true"; +defparam \sdram_|r.act_row[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N2 +cycloneive_lcell_comb \sdram_|Equal7~0 ( +// Equation(s): +// \sdram_|Equal7~0_combout = (\z80_|address_pins_|abus[11]~19_combout & (\sdram_|r.act_row [0] & (\z80_|address_pins_|abus[12]~24_combout $ (!\sdram_|r.act_row [1])))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\sdram_|r.act_row [0] & +// (\z80_|address_pins_|abus[12]~24_combout $ (!\sdram_|r.act_row [1])))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\z80_|address_pins_|abus[12]~24_combout ), + .datac(\sdram_|r.act_row [1]), + .datad(\sdram_|r.act_row [0]), + .cin(gnd), + .combout(\sdram_|Equal7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal7~0 .lut_mask = 16'h8241; +defparam \sdram_|Equal7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N30 +cycloneive_lcell_comb \sdram_|Equal7~2 ( +// Equation(s): +// \sdram_|Equal7~2_combout = (\sdram_|Equal7~1_combout & (\sdram_|Equal7~0_combout & (\z80_|address_pins_|abus[15]~21_combout $ (!\sdram_|r.act_row [4])))) + + .dataa(\z80_|address_pins_|abus[15]~21_combout ), + .datab(\sdram_|r.act_row [4]), + .datac(\sdram_|Equal7~1_combout ), + .datad(\sdram_|Equal7~0_combout ), + .cin(gnd), + .combout(\sdram_|Equal7~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal7~2 .lut_mask = 16'h9000; +defparam \sdram_|Equal7~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N4 +cycloneive_lcell_comb \sdram_|Mux39~0 ( +// Equation(s): +// \sdram_|Mux39~0_combout = (\sdram_|r.state [5] & (\sdram_|r.state [7] & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & (\sdram_|r.state [8] & (!\sdram_|r.state [7] & !\sdram_|r.state [4]))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux39~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux39~0 .lut_mask = 16'h8024; +defparam \sdram_|Mux39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N12 +cycloneive_lcell_comb \sdram_|Mux39~1 ( +// Equation(s): +// \sdram_|Mux39~1_combout = (\sdram_|r.state [6]) # ((!\sdram_|Mux39~0_combout ) # (!\sdram_|Equal7~2_combout )) + + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|Mux39~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux39~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux39~1 .lut_mask = 16'hAFFF; +defparam \sdram_|Mux39~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N24 +cycloneive_lcell_comb \sdram_|Mux39~2 ( +// Equation(s): +// \sdram_|Mux39~2_combout = (\sdram_|r.wr_pending~q & (\sdram_|Mux39~1_combout )) # (!\sdram_|r.wr_pending~q & (((\z80_|address_pins_|abus[15]~21_combout & \ExtRamWE~0_combout )))) + + .dataa(\sdram_|Mux39~1_combout ), + .datab(\z80_|address_pins_|abus[15]~21_combout ), + .datac(\sdram_|r.wr_pending~q ), + .datad(\ExtRamWE~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux39~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux39~2 .lut_mask = 16'hACA0; +defparam \sdram_|Mux39~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y12_N25 +dffeas \sdram_|r.wr_pending ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux39~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.wr_pending~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.wr_pending .is_wysiwyg = "true"; +defparam \sdram_|r.wr_pending .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N8 +cycloneive_lcell_comb \sdram_|Mux9~8 ( +// Equation(s): +// \sdram_|Mux9~8_combout = (\sdram_|r.state [8] & !\sdram_|r.state [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux9~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~8 .lut_mask = 16'h00F0; +defparam \sdram_|Mux9~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N20 +cycloneive_lcell_comb \sdram_|Mux9~9 ( +// Equation(s): +// \sdram_|Mux9~9_combout = (!\sdram_|r.rd_pending~q & (!\sdram_|r.rf_pending~q & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.wr_pending~q )))) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux9~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~9 .lut_mask = 16'h0405; +defparam \sdram_|Mux9~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N26 +cycloneive_lcell_comb \sdram_|Mux6~3 ( +// Equation(s): +// \sdram_|Mux6~3_combout = (\sdram_|r.state [6] & (((!\sdram_|Mux9~9_combout ) # (!\sdram_|Mux9~8_combout )))) # (!\sdram_|r.state [6] & (\sdram_|r.wr_pending~q & (\sdram_|Mux9~8_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|Mux9~8_combout ), + .datad(\sdram_|Mux9~9_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~3 .lut_mask = 16'h4AEA; +defparam \sdram_|Mux6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N0 +cycloneive_lcell_comb \sdram_|Mux6~4 ( +// Equation(s): +// \sdram_|Mux6~4_combout = (\sdram_|r.state [6]) # ((!\sdram_|r.rf_pending~q & \sdram_|Equal7~2_combout )) + + .dataa(gnd), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux6~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~4 .lut_mask = 16'hFF30; +defparam \sdram_|Mux6~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N6 +cycloneive_lcell_comb \sdram_|Mux6~2 ( +// Equation(s): +// \sdram_|Mux6~2_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [8]) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & ((\sdram_|r.state [4]))) + + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~2 .lut_mask = 16'hF5AA; +defparam \sdram_|Mux6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N10 +cycloneive_lcell_comb \sdram_|Mux6~5 ( +// Equation(s): +// \sdram_|Mux6~5_combout = (\sdram_|r.state [5] & (((\sdram_|Mux6~2_combout )))) # (!\sdram_|r.state [5] & (\sdram_|Mux6~3_combout & (\sdram_|Mux6~4_combout ))) + + .dataa(\sdram_|Mux6~3_combout ), + .datab(\sdram_|Mux6~4_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|Mux6~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~5 .lut_mask = 16'hF808; +defparam \sdram_|Mux6~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N8 +cycloneive_lcell_comb \sdram_|process_0~3 ( +// Equation(s): +// \sdram_|process_0~3_combout = (\sdram_|r.wr_pending~q & \sdram_|Equal7~2_combout ) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(gnd), + .datac(\sdram_|Equal7~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|process_0~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~3 .lut_mask = 16'hA0A0; +defparam \sdram_|process_0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N14 +cycloneive_lcell_comb \sdram_|Mux6~0 ( +// Equation(s): +// \sdram_|Mux6~0_combout = (\sdram_|r.state [8] & (\sdram_|r.state [4] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|process_0~3_combout )))) # (!\sdram_|r.state [8] & (!\sdram_|r.rf_pending~q & (\sdram_|process_0~3_combout & !\sdram_|r.state [4]))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|process_0~3_combout ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~0 .lut_mask = 16'h8A10; +defparam \sdram_|Mux6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N16 +cycloneive_lcell_comb \sdram_|Mux6~1 ( +// Equation(s): +// \sdram_|Mux6~1_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] $ (((\sdram_|r.state [6]) # (\sdram_|Mux6~0_combout ))))) # (!\sdram_|r.state [5] & (\sdram_|r.state [6] & ((\sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|Mux6~0_combout ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~1 .lut_mask = 16'h46A8; +defparam \sdram_|Mux6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N24 +cycloneive_lcell_comb \sdram_|Mux6~6 ( +// Equation(s): +// \sdram_|Mux6~6_combout = (\sdram_|r.state [7] & ((\sdram_|Mux6~1_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux6~5_combout )) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux6~5_combout ), + .datad(\sdram_|Mux6~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux6~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux6~6 .lut_mask = 16'hFC30; +defparam \sdram_|Mux6~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y15_N25 +dffeas \sdram_|r.state[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux6~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[6] .is_wysiwyg = "true"; +defparam \sdram_|r.state[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N12 +cycloneive_lcell_comb \sdram_|r.address[3]~6 ( +// Equation(s): +// \sdram_|r.address[3]~6_combout = (!\sdram_|r.state [6] & (!\sdram_|r.state [7] & !\sdram_|r.state [8])) + + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.address[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~6 .lut_mask = 16'h0005; +defparam \sdram_|r.address[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N22 +cycloneive_lcell_comb \sdram_|Mux7~2 ( +// Equation(s): +// \sdram_|Mux7~2_combout = (!\sdram_|r.state [5] & (\sdram_|r.state [4] & ((\sdram_|r.rf_pending~q ) # (!\sdram_|r.address[3]~6_combout )))) + + .dataa(\sdram_|r.address[3]~6_combout ), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux7~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~2 .lut_mask = 16'h3100; +defparam \sdram_|Mux7~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N12 +cycloneive_lcell_comb \sdram_|n~3 ( +// Equation(s): +// \sdram_|n~3_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q ))) + + .dataa(gnd), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|n~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|n~3 .lut_mask = 16'hFC00; +defparam \sdram_|n~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N6 +cycloneive_lcell_comb \sdram_|Mux7~3 ( +// Equation(s): +// \sdram_|Mux7~3_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [6]) # (!\sdram_|r.rd_pending~q ))) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|r.state [6]), + .datac(gnd), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux7~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~3 .lut_mask = 16'h7700; +defparam \sdram_|Mux7~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N28 +cycloneive_lcell_comb \sdram_|Mux7~4 ( +// Equation(s): +// \sdram_|Mux7~4_combout = (\sdram_|r.state [6] & (\sdram_|Mux7~3_combout & (!\sdram_|r.wr_pending~q & \sdram_|r.state [7]))) # (!\sdram_|r.state [6] & (\sdram_|Mux7~3_combout $ (((\sdram_|r.state [7]))))) + + .dataa(\sdram_|Mux7~3_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux7~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~4 .lut_mask = 16'h1922; +defparam \sdram_|Mux7~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N10 +cycloneive_lcell_comb \sdram_|Mux7~5 ( +// Equation(s): +// \sdram_|Mux7~5_combout = (\sdram_|r.state [6] & (((\sdram_|r.rf_pending~q & \sdram_|Mux7~4_combout )))) # (!\sdram_|r.state [6] & (!\sdram_|Mux7~4_combout & ((\sdram_|r.rf_pending~q ) # (!\sdram_|n~3_combout )))) + + .dataa(\sdram_|n~3_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Mux7~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux7~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~5 .lut_mask = 16'hC031; +defparam \sdram_|Mux7~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N0 +cycloneive_lcell_comb \sdram_|Mux23~0 ( +// Equation(s): +// \sdram_|Mux23~0_combout = (\sdram_|r.state [8] & \sdram_|r.state [6]) + + .dataa(gnd), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [6]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|Mux23~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~0 .lut_mask = 16'hC0C0; +defparam \sdram_|Mux23~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N24 +cycloneive_lcell_comb \sdram_|Mux13~7 ( +// Equation(s): +// \sdram_|Mux13~7_combout = (!\sdram_|r.state [4] & \sdram_|r.state [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [5]), + .cin(gnd), + .combout(\sdram_|Mux13~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~7 .lut_mask = 16'h0F00; +defparam \sdram_|Mux13~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N20 +cycloneive_lcell_comb \sdram_|Mux10~10 ( +// Equation(s): +// \sdram_|Mux10~10_combout = (!\sdram_|r.state [8] & (((\sdram_|r.state [6]) # (\sdram_|r.rf_pending~q )) # (!\sdram_|n~3_combout ))) + + .dataa(\sdram_|n~3_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.rf_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux10~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~10 .lut_mask = 16'h3331; +defparam \sdram_|Mux10~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N18 +cycloneive_lcell_comb \sdram_|Mux7~1 ( +// Equation(s): +// \sdram_|Mux7~1_combout = (\sdram_|Mux13~7_combout & ((\sdram_|Mux23~0_combout ) # ((\sdram_|Mux10~10_combout ) # (!\sdram_|r.state [7])))) + + .dataa(\sdram_|Mux23~0_combout ), + .datab(\sdram_|Mux13~7_combout ), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|Mux10~10_combout ), + .cin(gnd), + .combout(\sdram_|Mux7~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~1 .lut_mask = 16'hCC8C; +defparam \sdram_|Mux7~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N22 +cycloneive_lcell_comb \sdram_|Mux7~6 ( +// Equation(s): +// \sdram_|Mux7~6_combout = (\sdram_|Mux7~2_combout ) # ((\sdram_|Mux7~1_combout ) # ((\sdram_|Mux7~5_combout & \sdram_|r.state [8]))) + + .dataa(\sdram_|Mux7~2_combout ), + .datab(\sdram_|Mux7~5_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux7~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux7~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~6 .lut_mask = 16'hFFEA; +defparam \sdram_|Mux7~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y15_N23 +dffeas \sdram_|r.state[5] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux7~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[5] .is_wysiwyg = "true"; +defparam \sdram_|r.state[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N6 +cycloneive_lcell_comb \sdram_|Mux5~2 ( +// Equation(s): +// \sdram_|Mux5~2_combout = (\sdram_|Mux13~7_combout & ((\sdram_|r.state [6]) # ((!\sdram_|Mux4~0_combout & !\sdram_|r.state [8])))) + + .dataa(\sdram_|Mux4~0_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux13~7_combout ), + .cin(gnd), + .combout(\sdram_|Mux5~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~2 .lut_mask = 16'hCD00; +defparam \sdram_|Mux5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N18 +cycloneive_lcell_comb \sdram_|Mux5~10 ( +// Equation(s): +// \sdram_|Mux5~10_combout = (\sdram_|r.state [6] & (\sdram_|r.state [8] & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q )))) # (!\sdram_|r.state [6] & (((!\sdram_|r.state [8])))) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux5~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~10 .lut_mask = 16'hE00F; +defparam \sdram_|Mux5~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N16 +cycloneive_lcell_comb \sdram_|Mux5~3 ( +// Equation(s): +// \sdram_|Mux5~3_combout = ((\sdram_|Mux5~10_combout ) # ((!\sdram_|r.state [6] & !\sdram_|Mux4~0_combout ))) # (!\sdram_|r.state [5]) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|Mux4~0_combout ), + .datad(\sdram_|Mux5~10_combout ), + .cin(gnd), + .combout(\sdram_|Mux5~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~3 .lut_mask = 16'hFF37; +defparam \sdram_|Mux5~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N30 +cycloneive_lcell_comb \sdram_|Mux5~4 ( +// Equation(s): +// \sdram_|Mux5~4_combout = (\sdram_|r.state [7] & ((\sdram_|Mux5~2_combout ) # ((\sdram_|Mux5~3_combout & \sdram_|r.state [4])))) + + .dataa(\sdram_|Mux5~2_combout ), + .datab(\sdram_|Mux5~3_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux5~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~4 .lut_mask = 16'hEA00; +defparam \sdram_|Mux5~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N18 +cycloneive_lcell_comb \sdram_|Mux5~7 ( +// Equation(s): +// \sdram_|Mux5~7_combout = (!\sdram_|r.state [8] & (\sdram_|r.state [4] & ((\sdram_|r.wr_pending~q ) # (\sdram_|r.rd_pending~q )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.wr_pending~q ), + .datad(\sdram_|r.rd_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux5~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~7 .lut_mask = 16'h4440; +defparam \sdram_|Mux5~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N4 +cycloneive_lcell_comb \sdram_|Mux5~8 ( +// Equation(s): +// \sdram_|Mux5~8_combout = (!\sdram_|r.state [6] & ((\sdram_|r.state [7]) # ((\sdram_|Mux5~7_combout & !\sdram_|r.rf_pending~q )))) + + .dataa(\sdram_|Mux5~7_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux5~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~8 .lut_mask = 16'h3302; +defparam \sdram_|Mux5~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N26 +cycloneive_lcell_comb \sdram_|Mux5~5 ( +// Equation(s): +// \sdram_|Mux5~5_combout = (!\sdram_|r.state [7] & (((\sdram_|r.rf_pending~q ) # (!\sdram_|Equal7~2_combout )) # (!\sdram_|r.rd_pending~q ))) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux5~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~5 .lut_mask = 16'h00DF; +defparam \sdram_|Mux5~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N12 +cycloneive_lcell_comb \sdram_|Mux5~6 ( +// Equation(s): +// \sdram_|Mux5~6_combout = (\sdram_|Mux9~8_combout & ((\sdram_|Mux5~5_combout ) # ((!\sdram_|r.state [6] & \sdram_|process_0~3_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|process_0~3_combout ), + .datac(\sdram_|Mux9~8_combout ), + .datad(\sdram_|Mux5~5_combout ), + .cin(gnd), + .combout(\sdram_|Mux5~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~6 .lut_mask = 16'hF040; +defparam \sdram_|Mux5~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N20 +cycloneive_lcell_comb \sdram_|Mux5~9 ( +// Equation(s): +// \sdram_|Mux5~9_combout = (\sdram_|Mux5~4_combout ) # ((!\sdram_|r.state [5] & ((\sdram_|Mux5~8_combout ) # (\sdram_|Mux5~6_combout )))) + + .dataa(\sdram_|r.state [5]), + .datab(\sdram_|Mux5~4_combout ), + .datac(\sdram_|Mux5~8_combout ), + .datad(\sdram_|Mux5~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux5~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux5~9 .lut_mask = 16'hDDDC; +defparam \sdram_|Mux5~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y15_N21 +dffeas \sdram_|r.state[7] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux5~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[7] .is_wysiwyg = "true"; +defparam \sdram_|r.state[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N8 +cycloneive_lcell_comb \sdram_|n~2 ( +// Equation(s): +// \sdram_|n~2_combout = (\sdram_|r.rd_pending~q ) # ((\sdram_|r.rf_pending~q ) # (\sdram_|r.wr_pending~q )) + + .dataa(gnd), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|n~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|n~2 .lut_mask = 16'hFFFC; +defparam \sdram_|n~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N8 +cycloneive_lcell_comb \sdram_|Mux8~3 ( +// Equation(s): +// \sdram_|Mux8~3_combout = (\sdram_|r.state [5] & (\sdram_|n~2_combout & (\sdram_|r.state [8] $ (!\sdram_|r.state [4])))) # (!\sdram_|r.state [5] & (((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) + + .dataa(\sdram_|n~2_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux8~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~3 .lut_mask = 16'h8C2F; +defparam \sdram_|Mux8~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N6 +cycloneive_lcell_comb \sdram_|Mux8~4 ( +// Equation(s): +// \sdram_|Mux8~4_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [6] $ (\sdram_|Mux8~3_combout )))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [4] & ((\sdram_|r.state [6]) # (\sdram_|Mux8~3_combout )))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|Mux8~3_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux8~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~4 .lut_mask = 16'h3C54; +defparam \sdram_|Mux8~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N4 +cycloneive_lcell_comb \sdram_|Mux9~10 ( +// Equation(s): +// \sdram_|Mux9~10_combout = (!\sdram_|r.state [4] & ((!\sdram_|r.state [8]) # (!\sdram_|Mux9~9_combout ))) + + .dataa(gnd), + .datab(\sdram_|Mux9~9_combout ), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux9~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~10 .lut_mask = 16'h003F; +defparam \sdram_|Mux9~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N28 +cycloneive_lcell_comb \sdram_|r.init_counter[0]~0 ( +// Equation(s): +// \sdram_|r.init_counter[0]~0_combout = !\sdram_|r.init_counter [0] + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.init_counter [0]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.init_counter[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.init_counter[0]~0 .lut_mask = 16'h0F0F; +defparam \sdram_|r.init_counter[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y7_N29 +dffeas \sdram_|r.init_counter[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.init_counter[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[0] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N2 +cycloneive_lcell_comb \sdram_|Add1~1 ( +// Equation(s): +// \sdram_|Add1~1_cout = CARRY(\sdram_|r.init_counter [0]) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\sdram_|Add1~1_cout )); +// synopsys translate_off +defparam \sdram_|Add1~1 .lut_mask = 16'h00CC; +defparam \sdram_|Add1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N4 +cycloneive_lcell_comb \sdram_|Add1~2 ( +// Equation(s): +// \sdram_|Add1~2_combout = (\sdram_|r.init_counter [1] & (\sdram_|Add1~1_cout & VCC)) # (!\sdram_|r.init_counter [1] & (!\sdram_|Add1~1_cout )) +// \sdram_|Add1~3 = CARRY((!\sdram_|r.init_counter [1] & !\sdram_|Add1~1_cout )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~1_cout ), + .combout(\sdram_|Add1~2_combout ), + .cout(\sdram_|Add1~3 )); +// synopsys translate_off +defparam \sdram_|Add1~2 .lut_mask = 16'hC303; +defparam \sdram_|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N5 +dffeas \sdram_|r.init_counter[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[1] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N6 +cycloneive_lcell_comb \sdram_|Add1~4 ( +// Equation(s): +// \sdram_|Add1~4_combout = (\sdram_|r.init_counter [2] & ((GND) # (!\sdram_|Add1~3 ))) # (!\sdram_|r.init_counter [2] & (\sdram_|Add1~3 $ (GND))) +// \sdram_|Add1~5 = CARRY((\sdram_|r.init_counter [2]) # (!\sdram_|Add1~3 )) + + .dataa(\sdram_|r.init_counter [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~3 ), + .combout(\sdram_|Add1~4_combout ), + .cout(\sdram_|Add1~5 )); +// synopsys translate_off +defparam \sdram_|Add1~4 .lut_mask = 16'h5AAF; +defparam \sdram_|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N7 +dffeas \sdram_|r.init_counter[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[2] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N8 +cycloneive_lcell_comb \sdram_|Add1~6 ( +// Equation(s): +// \sdram_|Add1~6_combout = (\sdram_|r.init_counter [3] & (!\sdram_|Add1~5 )) # (!\sdram_|r.init_counter [3] & (\sdram_|Add1~5 & VCC)) +// \sdram_|Add1~7 = CARRY((\sdram_|r.init_counter [3] & !\sdram_|Add1~5 )) + + .dataa(\sdram_|r.init_counter [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~5 ), + .combout(\sdram_|Add1~6_combout ), + .cout(\sdram_|Add1~7 )); +// synopsys translate_off +defparam \sdram_|Add1~6 .lut_mask = 16'h5A0A; +defparam \sdram_|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N2 +cycloneive_lcell_comb \sdram_|r.init_counter[3]~1 ( +// Equation(s): +// \sdram_|r.init_counter[3]~1_combout = !\sdram_|Add1~6_combout + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|Add1~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.init_counter[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.init_counter[3]~1 .lut_mask = 16'h0F0F; +defparam \sdram_|r.init_counter[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y3_N3 +dffeas \sdram_|r.init_counter[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.init_counter[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[3] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N10 +cycloneive_lcell_comb \sdram_|Add1~8 ( +// Equation(s): +// \sdram_|Add1~8_combout = (\sdram_|r.init_counter [4] & ((GND) # (!\sdram_|Add1~7 ))) # (!\sdram_|r.init_counter [4] & (\sdram_|Add1~7 $ (GND))) +// \sdram_|Add1~9 = CARRY((\sdram_|r.init_counter [4]) # (!\sdram_|Add1~7 )) + + .dataa(\sdram_|r.init_counter [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~7 ), + .combout(\sdram_|Add1~8_combout ), + .cout(\sdram_|Add1~9 )); +// synopsys translate_off +defparam \sdram_|Add1~8 .lut_mask = 16'h5AAF; +defparam \sdram_|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N11 +dffeas \sdram_|r.init_counter[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[4] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N12 +cycloneive_lcell_comb \sdram_|Add1~10 ( +// Equation(s): +// \sdram_|Add1~10_combout = (\sdram_|r.init_counter [5] & (\sdram_|Add1~9 & VCC)) # (!\sdram_|r.init_counter [5] & (!\sdram_|Add1~9 )) +// \sdram_|Add1~11 = CARRY((!\sdram_|r.init_counter [5] & !\sdram_|Add1~9 )) + + .dataa(\sdram_|r.init_counter [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~9 ), + .combout(\sdram_|Add1~10_combout ), + .cout(\sdram_|Add1~11 )); +// synopsys translate_off +defparam \sdram_|Add1~10 .lut_mask = 16'hA505; +defparam \sdram_|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N13 +dffeas \sdram_|r.init_counter[5] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[5] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N14 +cycloneive_lcell_comb \sdram_|Add1~12 ( +// Equation(s): +// \sdram_|Add1~12_combout = (\sdram_|r.init_counter [6] & ((GND) # (!\sdram_|Add1~11 ))) # (!\sdram_|r.init_counter [6] & (\sdram_|Add1~11 $ (GND))) +// \sdram_|Add1~13 = CARRY((\sdram_|r.init_counter [6]) # (!\sdram_|Add1~11 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~11 ), + .combout(\sdram_|Add1~12_combout ), + .cout(\sdram_|Add1~13 )); +// synopsys translate_off +defparam \sdram_|Add1~12 .lut_mask = 16'h3CCF; +defparam \sdram_|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N15 +dffeas \sdram_|r.init_counter[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[6] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N16 +cycloneive_lcell_comb \sdram_|Add1~14 ( +// Equation(s): +// \sdram_|Add1~14_combout = (\sdram_|r.init_counter [7] & (\sdram_|Add1~13 & VCC)) # (!\sdram_|r.init_counter [7] & (!\sdram_|Add1~13 )) +// \sdram_|Add1~15 = CARRY((!\sdram_|r.init_counter [7] & !\sdram_|Add1~13 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~13 ), + .combout(\sdram_|Add1~14_combout ), + .cout(\sdram_|Add1~15 )); +// synopsys translate_off +defparam \sdram_|Add1~14 .lut_mask = 16'hC303; +defparam \sdram_|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N17 +dffeas \sdram_|r.init_counter[7] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~14_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[7] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N18 +cycloneive_lcell_comb \sdram_|Add1~16 ( +// Equation(s): +// \sdram_|Add1~16_combout = (\sdram_|r.init_counter [8] & ((GND) # (!\sdram_|Add1~15 ))) # (!\sdram_|r.init_counter [8] & (\sdram_|Add1~15 $ (GND))) +// \sdram_|Add1~17 = CARRY((\sdram_|r.init_counter [8]) # (!\sdram_|Add1~15 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~15 ), + .combout(\sdram_|Add1~16_combout ), + .cout(\sdram_|Add1~17 )); +// synopsys translate_off +defparam \sdram_|Add1~16 .lut_mask = 16'h3CCF; +defparam \sdram_|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N19 +dffeas \sdram_|r.init_counter[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[8] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N20 +cycloneive_lcell_comb \sdram_|Add1~18 ( +// Equation(s): +// \sdram_|Add1~18_combout = (\sdram_|r.init_counter [9] & (\sdram_|Add1~17 & VCC)) # (!\sdram_|r.init_counter [9] & (!\sdram_|Add1~17 )) +// \sdram_|Add1~19 = CARRY((!\sdram_|r.init_counter [9] & !\sdram_|Add1~17 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [9]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~17 ), + .combout(\sdram_|Add1~18_combout ), + .cout(\sdram_|Add1~19 )); +// synopsys translate_off +defparam \sdram_|Add1~18 .lut_mask = 16'hC303; +defparam \sdram_|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N21 +dffeas \sdram_|r.init_counter[9] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[9] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N22 +cycloneive_lcell_comb \sdram_|Add1~20 ( +// Equation(s): +// \sdram_|Add1~20_combout = (\sdram_|r.init_counter [10] & ((GND) # (!\sdram_|Add1~19 ))) # (!\sdram_|r.init_counter [10] & (\sdram_|Add1~19 $ (GND))) +// \sdram_|Add1~21 = CARRY((\sdram_|r.init_counter [10]) # (!\sdram_|Add1~19 )) + + .dataa(\sdram_|r.init_counter [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~19 ), + .combout(\sdram_|Add1~20_combout ), + .cout(\sdram_|Add1~21 )); +// synopsys translate_off +defparam \sdram_|Add1~20 .lut_mask = 16'h5AAF; +defparam \sdram_|Add1~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N23 +dffeas \sdram_|r.init_counter[10] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~20_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[10] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N22 +cycloneive_lcell_comb \sdram_|Equal2~0 ( +// Equation(s): +// \sdram_|Equal2~0_combout = (!\sdram_|r.init_counter [9] & (!\sdram_|r.init_counter [8] & (!\sdram_|r.init_counter [4] & !\sdram_|r.init_counter [10]))) + + .dataa(\sdram_|r.init_counter [9]), + .datab(\sdram_|r.init_counter [8]), + .datac(\sdram_|r.init_counter [4]), + .datad(\sdram_|r.init_counter [10]), + .cin(gnd), + .combout(\sdram_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~0 .lut_mask = 16'h0001; +defparam \sdram_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N0 +cycloneive_lcell_comb \sdram_|Equal2~1 ( +// Equation(s): +// \sdram_|Equal2~1_combout = (!\sdram_|r.init_counter [6] & (!\sdram_|r.init_counter [5] & \sdram_|r.init_counter [3])) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [6]), + .datac(\sdram_|r.init_counter [5]), + .datad(\sdram_|r.init_counter [3]), + .cin(gnd), + .combout(\sdram_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~1 .lut_mask = 16'h0300; +defparam \sdram_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N24 +cycloneive_lcell_comb \sdram_|Add1~22 ( +// Equation(s): +// \sdram_|Add1~22_combout = (\sdram_|r.init_counter [11] & (\sdram_|Add1~21 & VCC)) # (!\sdram_|r.init_counter [11] & (!\sdram_|Add1~21 )) +// \sdram_|Add1~23 = CARRY((!\sdram_|r.init_counter [11] & !\sdram_|Add1~21 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [11]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~21 ), + .combout(\sdram_|Add1~22_combout ), + .cout(\sdram_|Add1~23 )); +// synopsys translate_off +defparam \sdram_|Add1~22 .lut_mask = 16'hC303; +defparam \sdram_|Add1~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N25 +dffeas \sdram_|r.init_counter[11] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[11] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N26 +cycloneive_lcell_comb \sdram_|Add1~24 ( +// Equation(s): +// \sdram_|Add1~24_combout = (\sdram_|r.init_counter [12] & ((GND) # (!\sdram_|Add1~23 ))) # (!\sdram_|r.init_counter [12] & (\sdram_|Add1~23 $ (GND))) +// \sdram_|Add1~25 = CARRY((\sdram_|r.init_counter [12]) # (!\sdram_|Add1~23 )) + + .dataa(\sdram_|r.init_counter [12]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~23 ), + .combout(\sdram_|Add1~24_combout ), + .cout(\sdram_|Add1~25 )); +// synopsys translate_off +defparam \sdram_|Add1~24 .lut_mask = 16'h5AAF; +defparam \sdram_|Add1~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N27 +dffeas \sdram_|r.init_counter[12] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[12] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N28 +cycloneive_lcell_comb \sdram_|Add1~26 ( +// Equation(s): +// \sdram_|Add1~26_combout = (\sdram_|r.init_counter [13] & (\sdram_|Add1~25 & VCC)) # (!\sdram_|r.init_counter [13] & (!\sdram_|Add1~25 )) +// \sdram_|Add1~27 = CARRY((!\sdram_|r.init_counter [13] & !\sdram_|Add1~25 )) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [13]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_|Add1~25 ), + .combout(\sdram_|Add1~26_combout ), + .cout(\sdram_|Add1~27 )); +// synopsys translate_off +defparam \sdram_|Add1~26 .lut_mask = 16'hC303; +defparam \sdram_|Add1~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N29 +dffeas \sdram_|r.init_counter[13] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~26_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[13] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N30 +cycloneive_lcell_comb \sdram_|Add1~28 ( +// Equation(s): +// \sdram_|Add1~28_combout = \sdram_|r.init_counter [14] $ (\sdram_|Add1~27 ) + + .dataa(\sdram_|r.init_counter [14]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sdram_|Add1~27 ), + .combout(\sdram_|Add1~28_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Add1~28 .lut_mask = 16'h5A5A; +defparam \sdram_|Add1~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y3_N31 +dffeas \sdram_|r.init_counter[14] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Add1~28_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.init_counter [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.init_counter[14] .is_wysiwyg = "true"; +defparam \sdram_|r.init_counter[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y3_N0 +cycloneive_lcell_comb \sdram_|process_0~5 ( +// Equation(s): +// \sdram_|process_0~5_combout = (!\sdram_|r.init_counter [14] & (!\sdram_|r.init_counter [11] & (!\sdram_|r.init_counter [12] & !\sdram_|r.init_counter [13]))) + + .dataa(\sdram_|r.init_counter [14]), + .datab(\sdram_|r.init_counter [11]), + .datac(\sdram_|r.init_counter [12]), + .datad(\sdram_|r.init_counter [13]), + .cin(gnd), + .combout(\sdram_|process_0~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~5 .lut_mask = 16'h0001; +defparam \sdram_|process_0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N6 +cycloneive_lcell_comb \sdram_|Equal2~2 ( +// Equation(s): +// \sdram_|Equal2~2_combout = (\sdram_|Equal2~0_combout & (\sdram_|Equal2~1_combout & (\sdram_|process_0~5_combout & !\sdram_|r.init_counter [2]))) + + .dataa(\sdram_|Equal2~0_combout ), + .datab(\sdram_|Equal2~1_combout ), + .datac(\sdram_|process_0~5_combout ), + .datad(\sdram_|r.init_counter [2]), + .cin(gnd), + .combout(\sdram_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~2 .lut_mask = 16'h0080; +defparam \sdram_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N10 +cycloneive_lcell_comb \sdram_|Mux9~11 ( +// Equation(s): +// \sdram_|Mux9~11_combout = (!\sdram_|r.init_counter [1] & (\sdram_|r.init_counter [0] & !\sdram_|r.init_counter [7])) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [0]), + .datac(gnd), + .datad(\sdram_|r.init_counter [7]), + .cin(gnd), + .combout(\sdram_|Mux9~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~11 .lut_mask = 16'h0044; +defparam \sdram_|Mux9~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N24 +cycloneive_lcell_comb \sdram_|Mux9~12 ( +// Equation(s): +// \sdram_|Mux9~12_combout = (\sdram_|r.state [4] & (!\sdram_|n~2_combout )) # (!\sdram_|r.state [4] & (((\sdram_|Equal2~2_combout & \sdram_|Mux9~11_combout )))) + + .dataa(\sdram_|n~2_combout ), + .datab(\sdram_|Equal2~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|Mux9~11_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~12 .lut_mask = 16'h5C50; +defparam \sdram_|Mux9~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N0 +cycloneive_lcell_comb \sdram_|Mux9~13 ( +// Equation(s): +// \sdram_|Mux9~13_combout = (\sdram_|r.state [8] & (!\sdram_|r.state [4] & (\sdram_|n~2_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux9~12_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|n~2_combout ), + .datad(\sdram_|Mux9~12_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~13_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~13 .lut_mask = 16'h7520; +defparam \sdram_|Mux9~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N2 +cycloneive_lcell_comb \sdram_|Mux8~0 ( +// Equation(s): +// \sdram_|Mux8~0_combout = (\sdram_|r.state [6] & ((\sdram_|r.state [5]) # ((\sdram_|Mux9~10_combout )))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [5] & ((\sdram_|Mux9~13_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|Mux9~10_combout ), + .datad(\sdram_|Mux9~13_combout ), + .cin(gnd), + .combout(\sdram_|Mux8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~0 .lut_mask = 16'hB9A8; +defparam \sdram_|Mux8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N16 +cycloneive_lcell_comb \sdram_|Mux8~1 ( +// Equation(s): +// \sdram_|Mux8~1_combout = (\sdram_|r.state [5] & (((!\sdram_|r.state [8] & \sdram_|Mux8~0_combout )) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [5] & (((\sdram_|Mux8~0_combout )))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|Mux8~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux8~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~1 .lut_mask = 16'h7F50; +defparam \sdram_|Mux8~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N20 +cycloneive_lcell_comb \sdram_|Mux8~2 ( +// Equation(s): +// \sdram_|Mux8~2_combout = (\sdram_|r.state [7] & (\sdram_|Mux8~4_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux8~1_combout ))) + + .dataa(\sdram_|r.state [7]), + .datab(gnd), + .datac(\sdram_|Mux8~4_combout ), + .datad(\sdram_|Mux8~1_combout ), + .cin(gnd), + .combout(\sdram_|Mux8~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux8~2 .lut_mask = 16'hF5A0; +defparam \sdram_|Mux8~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y15_N21 +dffeas \sdram_|r.state[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux8~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[4] .is_wysiwyg = "true"; +defparam \sdram_|r.state[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N4 +cycloneive_lcell_comb \sdram_|Mux72~0 ( +// Equation(s): +// \sdram_|Mux72~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [0]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux72~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux72~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux72~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N2 +cycloneive_lcell_comb \sdram_|Mux72~1 ( +// Equation(s): +// \sdram_|Mux72~1_combout = (\sdram_|Mux72~0_combout & ((\D[0]~64_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\sdram_|Mux72~0_combout ), + .datad(\D[0]~64_combout ), + .cin(gnd), + .combout(\sdram_|Mux72~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux72~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux72~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N0 +cycloneive_lcell_comb \sdram_|Mux84~0 ( +// Equation(s): +// \sdram_|Mux84~0_combout = (\sdram_|r.state [5]) # (\sdram_|r.state [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux84~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux84~0 .lut_mask = 16'hFFF0; +defparam \sdram_|Mux84~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N2 +cycloneive_lcell_comb \sdram_|Mux84~1 ( +// Equation(s): +// \sdram_|Mux84~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [7] & (!\sdram_|r.state [8] & \sdram_|Mux84~0_combout ))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [7] & (\sdram_|r.state [8] & !\sdram_|Mux84~0_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [8]), + .datad(\sdram_|Mux84~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux84~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux84~1 .lut_mask = 16'h0810; +defparam \sdram_|Mux84~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N16 +cycloneive_lcell_comb \sdram_|Mux3~0 ( +// Equation(s): +// \sdram_|Mux3~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [1]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux3~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N18 +cycloneive_lcell_comb \sdram_|Mux3~1 ( +// Equation(s): +// \sdram_|Mux3~1_combout = (\sdram_|Mux3~0_combout & ((\D[1]~40_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\sdram_|Mux3~0_combout ), + .datad(\D[1]~40_combout ), + .cin(gnd), + .combout(\sdram_|Mux3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux3~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N0 +cycloneive_lcell_comb \sdram_|Mux2~0 ( +// Equation(s): +// \sdram_|Mux2~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [2]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [2]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux2~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N30 +cycloneive_lcell_comb \sdram_|Mux2~1 ( +// Equation(s): +// \sdram_|Mux2~1_combout = (\sdram_|Mux2~0_combout & ((\D[2]~52_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\sdram_|Mux2~0_combout ), + .datad(\D[2]~52_combout ), + .cin(gnd), + .combout(\sdram_|Mux2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux2~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N28 +cycloneive_lcell_comb \sdram_|Mux1~0 ( +// Equation(s): +// \sdram_|Mux1~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [3]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [3]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux1~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N10 +cycloneive_lcell_comb \sdram_|Mux1~1 ( +// Equation(s): +// \sdram_|Mux1~1_combout = (\sdram_|Mux1~0_combout & ((\D[3]~108_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\D[3]~108_combout ), + .datad(\sdram_|Mux1~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux1~1 .lut_mask = 16'hF100; +defparam \sdram_|Mux1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N12 +cycloneive_lcell_comb \sdram_|Mux0~0 ( +// Equation(s): +// \sdram_|Mux0~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [4]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux0~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N26 +cycloneive_lcell_comb \sdram_|Mux0~1 ( +// Equation(s): +// \sdram_|Mux0~1_combout = (\sdram_|Mux0~0_combout & ((\D[4]~110_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\sdram_|Mux0~0_combout ), + .datad(\D[4]~110_combout ), + .cin(gnd), + .combout(\sdram_|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux0~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N8 +cycloneive_lcell_comb \sdram_|Mux73~0 ( +// Equation(s): +// \sdram_|Mux73~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [5]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux73~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux73~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux73~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N14 +cycloneive_lcell_comb \sdram_|Mux73~1 ( +// Equation(s): +// \sdram_|Mux73~1_combout = (\sdram_|Mux73~0_combout & ((\D[5]~112_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\sdram_|Mux73~0_combout ), + .datad(\D[5]~112_combout ), + .cin(gnd), + .combout(\sdram_|Mux73~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux73~1 .lut_mask = 16'hF010; +defparam \sdram_|Mux73~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N24 +cycloneive_lcell_comb \sdram_|Mux74~0 ( +// Equation(s): +// \sdram_|Mux74~0_combout = (\sdram_|r.state [4] & ((\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~16_combout ))) + + .dataa(gnd), + .datab(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datac(\z80_|data_pins_|dout [6]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux74~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux74~0 .lut_mask = 16'hF300; +defparam \sdram_|Mux74~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N6 +cycloneive_lcell_comb \sdram_|Mux74~1 ( +// Equation(s): +// \sdram_|Mux74~1_combout = (\sdram_|Mux74~0_combout & ((\D[6]~114_combout ) # ((!\Equal2~1_combout & !\z80_|pin_control_|bus_db_pin_oe~16_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\sdram_|Mux74~0_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datad(\D[6]~114_combout ), + .cin(gnd), + .combout(\sdram_|Mux74~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux74~1 .lut_mask = 16'hCC04; +defparam \sdram_|Mux74~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y4_N28 +cycloneive_lcell_comb \sdram_|Mux75~0 ( +// Equation(s): +// \sdram_|Mux75~0_combout = (\sdram_|r.state [4] & \D[7]~117_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [4]), + .datad(\D[7]~117_combout ), + .cin(gnd), + .combout(\sdram_|Mux75~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux75~0 .lut_mask = 16'hF000; +defparam \sdram_|Mux75~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y32_N8 cycloneive_lcell_comb \ula_|i2s_intf_|mclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|mclk_r~0_combout = !\ula_|i2s_intf_|mclk_r~_Duplicate_1_q @@ -55715,7 +59007,7 @@ defparam \ula_|i2s_intf_|mclk_r~0 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|mclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y23_N17 +// Location: FF_X20_Y32_N9 dffeas \ula_|i2s_intf_|mclk_r~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|mclk_r~0_combout ), @@ -55753,24 +59045,24 @@ defparam \ula_|i2s_intf_|mclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|mclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N6 +// Location: LCCOMB_X20_Y31_N12 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~1 ( // Equation(s): // \ula_|i2s_intf_|Add0~1_cout = CARRY(!\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ) - .dataa(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), .datac(gnd), .datad(vcc), .cin(gnd), .combout(), .cout(\ula_|i2s_intf_|Add0~1_cout )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0033; defparam \ula_|i2s_intf_|Add0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N8 +// Location: LCCOMB_X20_Y31_N14 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~2 ( // Equation(s): // \ula_|i2s_intf_|Add0~2_combout = (\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Add0~1_cout & VCC)) # (!\ula_|i2s_intf_|lrdivider [1] & (!\ula_|i2s_intf_|Add0~1_cout )) @@ -55788,24 +59080,24 @@ defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hC303; defparam \ula_|i2s_intf_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N28 +// Location: LCCOMB_X20_Y31_N0 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~2 ( // Equation(s): -// \ula_|i2s_intf_|lrdivider~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~2_combout ) +// \ula_|i2s_intf_|lrdivider~2_combout = (\ula_|i2s_intf_|Add0~2_combout & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(gnd), .datab(gnd), .datac(\ula_|i2s_intf_|Add0~2_combout ), - .datad(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h5050; +defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h00F0; defparam \ula_|i2s_intf_|lrdivider~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N29 +// Location: FF_X20_Y31_N1 dffeas \ula_|i2s_intf_|lrdivider[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~2_combout ), @@ -55824,7 +59116,7 @@ defparam \ula_|i2s_intf_|lrdivider[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N10 +// Location: LCCOMB_X20_Y31_N16 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~4 ( // Equation(s): // \ula_|i2s_intf_|Add0~4_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|Add0~3 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add0~3 ))) @@ -55842,24 +59134,24 @@ defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hA55F; defparam \ula_|i2s_intf_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X30_Y23_N6 +// Location: LCCOMB_X21_Y31_N6 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[2]~8 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[2]~8_combout = !\ula_|i2s_intf_|Add0~4_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~4_combout ), + .datac(\ula_|i2s_intf_|Add0~4_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[2]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[2]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y23_N7 +// Location: FF_X21_Y31_N7 dffeas \ula_|i2s_intf_|lrdivider[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[2]~8_combout ), @@ -55878,42 +59170,42 @@ defparam \ula_|i2s_intf_|lrdivider[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N12 +// Location: LCCOMB_X20_Y31_N18 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~6 ( // Equation(s): // \ula_|i2s_intf_|Add0~6_combout = (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|Add0~5 )) # (!\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|Add0~5 & VCC)) // \ula_|i2s_intf_|Add0~7 = CARRY((\ula_|i2s_intf_|lrdivider [3] & !\ula_|i2s_intf_|Add0~5 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [3]), + .dataa(\ula_|i2s_intf_|lrdivider [3]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~5 ), .combout(\ula_|i2s_intf_|Add0~6_combout ), .cout(\ula_|i2s_intf_|Add0~7 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h3C0C; +defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h5A0A; defparam \ula_|i2s_intf_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N6 +// Location: LCCOMB_X20_Y32_N30 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[3]~7 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[3]~7_combout = !\ula_|i2s_intf_|Add0~6_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~6_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~6_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[3]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[3]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N7 +// Location: FF_X20_Y32_N31 dffeas \ula_|i2s_intf_|lrdivider[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[3]~7_combout ), @@ -55932,7 +59224,7 @@ defparam \ula_|i2s_intf_|lrdivider[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N14 +// Location: LCCOMB_X20_Y31_N20 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~8 ( // Equation(s): // \ula_|i2s_intf_|Add0~8_combout = (\ula_|i2s_intf_|lrdivider [4] & ((GND) # (!\ula_|i2s_intf_|Add0~7 ))) # (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|Add0~7 $ (GND))) @@ -55950,24 +59242,24 @@ defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N4 +// Location: LCCOMB_X20_Y31_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~1 ( // Equation(s): -// \ula_|i2s_intf_|lrdivider~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~8_combout ) +// \ula_|i2s_intf_|lrdivider~1_combout = (\ula_|i2s_intf_|Add0~8_combout & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~8_combout ), - .datad(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|Add0~8_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h5050; +defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h00CC; defparam \ula_|i2s_intf_|lrdivider~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N5 +// Location: FF_X20_Y31_N5 dffeas \ula_|i2s_intf_|lrdivider[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~1_combout ), @@ -55986,25 +59278,25 @@ defparam \ula_|i2s_intf_|lrdivider[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N16 +// Location: LCCOMB_X20_Y31_N22 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~10 ( // Equation(s): // \ula_|i2s_intf_|Add0~10_combout = (\ula_|i2s_intf_|lrdivider [5] & (!\ula_|i2s_intf_|Add0~9 )) # (!\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|Add0~9 & VCC)) // \ula_|i2s_intf_|Add0~11 = CARRY((\ula_|i2s_intf_|lrdivider [5] & !\ula_|i2s_intf_|Add0~9 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [5]), + .dataa(\ula_|i2s_intf_|lrdivider [5]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~9 ), .combout(\ula_|i2s_intf_|Add0~10_combout ), .cout(\ula_|i2s_intf_|Add0~11 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h3C0C; +defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h5A0A; defparam \ula_|i2s_intf_|Add0~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N2 +// Location: LCCOMB_X21_Y31_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[5]~6 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[5]~6_combout = !\ula_|i2s_intf_|Add0~10_combout @@ -56021,7 +59313,7 @@ defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[5]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N3 +// Location: FF_X21_Y31_N5 dffeas \ula_|i2s_intf_|lrdivider[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[5]~6_combout ), @@ -56040,7 +59332,7 @@ defparam \ula_|i2s_intf_|lrdivider[5] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N26 +// Location: LCCOMB_X20_Y31_N10 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~1 ( // Equation(s): // \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [2] & (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|lrdivider [3] & \ula_|i2s_intf_|lrdivider [5]))) @@ -56057,25 +59349,25 @@ defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h2000; defparam \ula_|i2s_intf_|Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N18 +// Location: LCCOMB_X20_Y31_N24 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~12 ( // Equation(s): // \ula_|i2s_intf_|Add0~12_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|Add0~11 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [6] & ((GND) # (!\ula_|i2s_intf_|Add0~11 ))) // \ula_|i2s_intf_|Add0~13 = CARRY((!\ula_|i2s_intf_|Add0~11 ) # (!\ula_|i2s_intf_|lrdivider [6])) - .dataa(\ula_|i2s_intf_|lrdivider [6]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [6]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~11 ), .combout(\ula_|i2s_intf_|Add0~12_combout ), .cout(\ula_|i2s_intf_|Add0~13 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hC33F; defparam \ula_|i2s_intf_|Add0~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N26 +// Location: LCCOMB_X21_Y31_N22 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[6]~5 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[6]~5_combout = !\ula_|i2s_intf_|Add0~12_combout @@ -56092,7 +59384,7 @@ defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[6]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N27 +// Location: FF_X21_Y31_N23 dffeas \ula_|i2s_intf_|lrdivider[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[6]~5_combout ), @@ -56111,7 +59403,7 @@ defparam \ula_|i2s_intf_|lrdivider[6] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N20 +// Location: LCCOMB_X20_Y31_N26 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~14 ( // Equation(s): // \ula_|i2s_intf_|Add0~14_combout = (\ula_|i2s_intf_|lrdivider [7] & (!\ula_|i2s_intf_|Add0~13 )) # (!\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|Add0~13 & VCC)) @@ -56129,24 +59421,24 @@ defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h5A0A; defparam \ula_|i2s_intf_|Add0~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X30_Y23_N4 +// Location: LCCOMB_X21_Y31_N20 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[7]~4 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[7]~4_combout = !\ula_|i2s_intf_|Add0~14_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~14_combout ), + .datac(\ula_|i2s_intf_|Add0~14_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[7]~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[7]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y23_N5 +// Location: FF_X21_Y31_N21 dffeas \ula_|i2s_intf_|lrdivider[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[7]~4_combout ), @@ -56165,42 +59457,42 @@ defparam \ula_|i2s_intf_|lrdivider[7] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N22 +// Location: LCCOMB_X20_Y31_N28 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~16 ( // Equation(s): // \ula_|i2s_intf_|Add0~16_combout = (\ula_|i2s_intf_|lrdivider [8] & ((GND) # (!\ula_|i2s_intf_|Add0~15 ))) # (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|Add0~15 $ (GND))) // \ula_|i2s_intf_|Add0~17 = CARRY((\ula_|i2s_intf_|lrdivider [8]) # (!\ula_|i2s_intf_|Add0~15 )) - .dataa(\ula_|i2s_intf_|lrdivider [8]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [8]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~15 ), .combout(\ula_|i2s_intf_|Add0~16_combout ), .cout(\ula_|i2s_intf_|Add0~17 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h5AAF; +defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|Add0~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N16 +// Location: LCCOMB_X20_Y31_N8 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~0 ( // Equation(s): // \ula_|i2s_intf_|lrdivider~0_combout = (\ula_|i2s_intf_|Add0~16_combout & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), .datab(\ula_|i2s_intf_|Add0~16_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Equal0~2_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h0C0C; +defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h00CC; defparam \ula_|i2s_intf_|lrdivider~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N17 +// Location: FF_X20_Y31_N9 dffeas \ula_|i2s_intf_|lrdivider[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~0_combout ), @@ -56219,7 +59511,7 @@ defparam \ula_|i2s_intf_|lrdivider[8] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N24 +// Location: LCCOMB_X20_Y31_N30 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~18 ( // Equation(s): // \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|Add0~17 $ (\ula_|i2s_intf_|lrdivider [9]) @@ -56236,24 +59528,24 @@ defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h0FF0; defparam \ula_|i2s_intf_|Add0~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N24 +// Location: LCCOMB_X19_Y31_N24 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[9]~3 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[9]~3_combout = !\ula_|i2s_intf_|Add0~18_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~18_combout ), + .datac(\ula_|i2s_intf_|Add0~18_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[9]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[9]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N25 +// Location: FF_X19_Y31_N25 dffeas \ula_|i2s_intf_|lrdivider[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[9]~3_combout ), @@ -56272,32 +59564,32 @@ defparam \ula_|i2s_intf_|lrdivider[9] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N0 +// Location: LCCOMB_X20_Y31_N6 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~0 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~0_combout = (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|lrdivider [9] & (\ula_|i2s_intf_|lrdivider [6] & \ula_|i2s_intf_|lrdivider [7]))) +// \ula_|i2s_intf_|Equal0~0_combout = (\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|lrdivider [9] & (!\ula_|i2s_intf_|lrdivider [8] & \ula_|i2s_intf_|lrdivider [6]))) - .dataa(\ula_|i2s_intf_|lrdivider [8]), + .dataa(\ula_|i2s_intf_|lrdivider [7]), .datab(\ula_|i2s_intf_|lrdivider [9]), - .datac(\ula_|i2s_intf_|lrdivider [6]), - .datad(\ula_|i2s_intf_|lrdivider [7]), + .datac(\ula_|i2s_intf_|lrdivider [8]), + .datad(\ula_|i2s_intf_|lrdivider [6]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h4000; +defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h0800; defparam \ula_|i2s_intf_|Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N30 +// Location: LCCOMB_X20_Y31_N2 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~2 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & \ula_|i2s_intf_|Equal0~0_combout ))) +// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Equal0~0_combout & \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ))) .dataa(\ula_|i2s_intf_|Equal0~1_combout ), .datab(\ula_|i2s_intf_|lrdivider [1]), - .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|Equal0~0_combout ), + .datac(\ula_|i2s_intf_|Equal0~0_combout ), + .datad(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~2_combout ), .cout()); @@ -56306,32 +59598,15 @@ defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h2000; defparam \ula_|i2s_intf_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder ( -// Equation(s): -// \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout = \ula_|i2s_intf_|lrclk_r~0_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .lut_mask = 16'hFF00; -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N25 +// Location: FF_X23_Y32_N29 dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|i2s_intf_|lrclk_r~0_combout ), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -56342,7 +59617,7 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N0 +// Location: LCCOMB_X23_Y32_N30 cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|Equal0~2_combout $ (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ) @@ -56397,516 +59672,13 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N0 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] -// \ula_|i2s_intf_|bitcount[0]~6 = CARRY(!\ula_|i2s_intf_|bitcount [0]) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [0]), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2s_intf_|bitcount[0]~5_combout ), - .cout(\ula_|i2s_intf_|bitcount[0]~6 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; -defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N11 -dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bclk_r~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N28 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & !\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .cin(gnd), - .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hF0FC; -defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N1 -dffeas \ula_|i2s_intf_|bitcount[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) -// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[0]~6 ), - .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .cout(\ula_|i2s_intf_|bitcount[1]~8 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y22_N3 -dffeas \ula_|i2s_intf_|bitcount[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N4 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) -// \ula_|i2s_intf_|bitcount[2]~10 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[1]~8 ), - .combout(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .cout(\ula_|i2s_intf_|bitcount[2]~10 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; -defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y22_N5 -dffeas \ula_|i2s_intf_|bitcount[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N6 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) -// \ula_|i2s_intf_|bitcount[3]~12 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~10 )) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|bitcount[2]~10 ), - .combout(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .cout(\ula_|i2s_intf_|bitcount[3]~12 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hA505; -defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y22_N7 -dffeas \ula_|i2s_intf_|bitcount[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( -// Equation(s): -// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # (((\ula_|i2s_intf_|bitcount [2]) # (\ula_|i2s_intf_|bitcount [1])) # (!\ula_|i2s_intf_|bitcount [0])) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(\ula_|i2s_intf_|bitcount [0]), - .datac(\ula_|i2s_intf_|bitcount [2]), - .datad(\ula_|i2s_intf_|bitcount [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFFB; -defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N8 -cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( -// Equation(s): -// \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [4]), - .datac(gnd), - .datad(gnd), - .cin(\ula_|i2s_intf_|bitcount[3]~12 ), - .combout(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h3C3C; -defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X31_Y22_N9 -dffeas \ula_|i2s_intf_|bitcount[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(\ula_|i2s_intf_|Equal0~2_combout ), - .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bitcount [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(), - .cout(\ula_|i2s_intf_|Add2~7_cout )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; -defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) -// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) - - .dataa(\ula_|i2s_intf_|bdivider [1]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~7_cout ), - .combout(\ula_|i2s_intf_|Add2~8_combout ), - .cout(\ula_|i2s_intf_|Add2~9 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hA505; -defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Equal1~0_combout ), - .datad(\ula_|i2s_intf_|Add2~8_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h1300; -defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N13 -dffeas \ula_|i2s_intf_|bdivider[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~20_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) -// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) - - .dataa(\ula_|i2s_intf_|bdivider [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~9 ), - .combout(\ula_|i2s_intf_|Add2~10_combout ), - .cout(\ula_|i2s_intf_|Add2~11 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hA55F; -defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add2~10_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h0203; -defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N17 -dffeas \ula_|i2s_intf_|bdivider[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~17_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) -// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~11 ), - .combout(\ula_|i2s_intf_|Add2~12_combout ), - .cout(\ula_|i2s_intf_|Add2~13 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~19_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~12_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Equal1~0_combout ), - .datad(\ula_|i2s_intf_|Add2~12_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h1300; -defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N3 -dffeas \ula_|i2s_intf_|bdivider[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~19_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|bdivider [4]), - .cin(\ula_|i2s_intf_|Add2~13 ), - .combout(\ula_|i2s_intf_|Add2~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; -defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add2~14_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0203; -defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N19 -dffeas \ula_|i2s_intf_|bdivider[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( -// Equation(s): -// \ula_|i2s_intf_|Equal1~0_combout = (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|bdivider [2] & \ula_|i2s_intf_|bdivider [4]))) - - .dataa(\ula_|i2s_intf_|bdivider [1]), - .datab(\ula_|i2s_intf_|bdivider [3]), - .datac(\ula_|i2s_intf_|bdivider [2]), - .datad(\ula_|i2s_intf_|bdivider [4]), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h1000; -defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~1 ( -// Equation(s): -// \ula_|i2s_intf_|shiftreg[4]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|LessThan0~0_combout ), - .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4]~1 .lut_mask = 16'h8A00; -defparam \ula_|i2s_intf_|shiftreg[4]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N12 +// Location: LCCOMB_X23_Y32_N8 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( // Equation(s): -// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[4]~1_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) +// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(\ula_|i2s_intf_|bdivider [0]), .datad(\ula_|i2s_intf_|Equal1~0_combout ), .cin(gnd), @@ -56917,7 +59689,7 @@ defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1101; defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y22_N13 +// Location: FF_X23_Y32_N9 dffeas \ula_|i2s_intf_|bdivider[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~18_combout ), @@ -56936,54 +59708,574 @@ defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( +// Location: LCCOMB_X24_Y32_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( // Equation(s): -// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|bdivider [0] & \ula_|i2s_intf_|Equal1~0_combout ) +// \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] +// \ula_|i2s_intf_|bitcount[0]~6 = CARRY(!\ula_|i2s_intf_|bitcount [0]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [0]), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|bitcount[0]~5_combout ), + .cout(\ula_|i2s_intf_|bitcount[0]~6 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; +defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder ( +// Equation(s): +// \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout = \ula_|i2s_intf_|bclk_r~1_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|bdivider [0]), + .datac(\ula_|i2s_intf_|bclk_r~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .lut_mask = 16'hF0F0; +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y32_N25 +dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[1]~1_combout )) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datac(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hBABA; +defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y32_N15 +dffeas \ula_|i2s_intf_|bitcount[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) +// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[0]~6 ), + .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .cout(\ula_|i2s_intf_|bitcount[1]~8 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y32_N17 +dffeas \ula_|i2s_intf_|bitcount[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) +// \ula_|i2s_intf_|bitcount[2]~10 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[1]~8 ), + .combout(\ula_|i2s_intf_|bitcount[2]~9_combout ), + .cout(\ula_|i2s_intf_|bitcount[2]~10 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; +defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y32_N19 +dffeas \ula_|i2s_intf_|bitcount[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) +// \ula_|i2s_intf_|bitcount[3]~12 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~10 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bitcount [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|bitcount[2]~10 ), + .combout(\ula_|i2s_intf_|bitcount[3]~11_combout ), + .cout(\ula_|i2s_intf_|bitcount[3]~12 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y32_N21 +dffeas \ula_|i2s_intf_|bitcount[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( +// Equation(s): +// \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) + + .dataa(\ula_|i2s_intf_|bitcount [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2s_intf_|bitcount[3]~12 ), + .combout(\ula_|i2s_intf_|bitcount[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h5A5A; +defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y32_N23 +dffeas \ula_|i2s_intf_|bitcount[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\ula_|i2s_intf_|Equal0~2_combout ), + .ena(\ula_|i2s_intf_|bitcount[4]~15_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bitcount [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( +// Equation(s): +// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # ((\ula_|i2s_intf_|bitcount [2]) # ((\ula_|i2s_intf_|bitcount [1]) # (!\ula_|i2s_intf_|bitcount [0]))) + + .dataa(\ula_|i2s_intf_|bitcount [3]), + .datab(\ula_|i2s_intf_|bitcount [2]), + .datac(\ula_|i2s_intf_|bitcount [0]), + .datad(\ula_|i2s_intf_|bitcount [1]), + .cin(gnd), + .combout(\ula_|i2s_intf_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFEF; +defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y32_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[1]~1 ( +// Equation(s): +// \ula_|i2s_intf_|shiftreg[1]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Equal1~0_combout ), + .datac(\ula_|i2s_intf_|bitcount [4]), + .datad(\ula_|i2s_intf_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|shiftreg[1]~1 .lut_mask = 16'h8808; +defparam \ula_|i2s_intf_|shiftreg[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N18 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\ula_|i2s_intf_|Add2~7_cout )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) +// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~7_cout ), + .combout(\ula_|i2s_intf_|Add2~8_combout ), + .cout(\ula_|i2s_intf_|Add2~9 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Add2~8_combout ), .datad(\ula_|i2s_intf_|Equal1~0_combout ), .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h1030; +defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y32_N5 +dffeas \ula_|i2s_intf_|bdivider[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) +// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~9 ), + .combout(\ula_|i2s_intf_|Add2~10_combout ), + .cout(\ula_|i2s_intf_|Add2~11 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hC33F; +defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) + + .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Add2~10_combout ), + .datad(\ula_|i2s_intf_|Equal1~1_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h1101; +defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y32_N17 +dffeas \ula_|i2s_intf_|bdivider[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~17_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N24 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) +// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~11 ), + .combout(\ula_|i2s_intf_|Add2~12_combout ), + .cout(\ula_|i2s_intf_|Add2~13 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~19_combout = (\ula_|i2s_intf_|Add2~12_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Add2~12_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h040C; +defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y32_N15 +dffeas \ula_|i2s_intf_|bdivider[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~19_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|bdivider [4]), + .cin(\ula_|i2s_intf_|Add2~13 ), + .combout(\ula_|i2s_intf_|Add2~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; +defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|shiftreg[1]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) + + .dataa(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Add2~14_combout ), + .datad(\ula_|i2s_intf_|Equal1~1_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h1101; +defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y32_N7 +dffeas \ula_|i2s_intf_|bdivider[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~0_combout = (\ula_|i2s_intf_|bdivider [4] & (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & \ula_|i2s_intf_|bdivider [2]))) + + .dataa(\ula_|i2s_intf_|bdivider [4]), + .datab(\ula_|i2s_intf_|bdivider [1]), + .datac(\ula_|i2s_intf_|bdivider [3]), + .datad(\ula_|i2s_intf_|bdivider [2]), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h0200; +defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y32_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|Equal1~0_combout & \ula_|i2s_intf_|bdivider [0]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal1~0_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|bdivider [0]), + .cin(gnd), .combout(\ula_|i2s_intf_|Equal1~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hF000; +defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hCC00; defparam \ula_|i2s_intf_|Equal1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N14 +// Location: LCCOMB_X24_Y32_N12 cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|bclk_r~0_combout = \ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]))) - .dataa(gnd), - .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .dataa(\ula_|i2s_intf_|LessThan0~0_combout ), + .datab(gnd), .datac(\ula_|i2s_intf_|bitcount [4]), .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), .cin(gnd), .combout(\ula_|i2s_intf_|bclk_r~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h30CF; +defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h50AF; defparam \ula_|i2s_intf_|bclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N10 +// Location: LCCOMB_X24_Y32_N26 cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~1 ( // Equation(s): -// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~0_combout )) # (!\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))))) +// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~0_combout ))) # (!\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )))) .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|bclk_r~0_combout ), - .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|bclk_r~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|bclk_r~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h00D8; +defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h0E04; defparam \ula_|i2s_intf_|bclk_r~1 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57006,15 +60298,15 @@ defparam \ula_|i2s_intf_|bclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N24 +// Location: LCCOMB_X23_Y19_N16 cycloneive_lcell_comb \ula_|pcm_outl[13]~feeder ( // Equation(s): -// \ula_|pcm_outl[13]~feeder_combout = \D[3]~96_combout +// \ula_|pcm_outl[13]~feeder_combout = \D[3]~109_combout .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(\D[3]~96_combout ), + .datad(\D[3]~109_combout ), .cin(gnd), .combout(\ula_|pcm_outl[13]~feeder_combout ), .cout()); @@ -57023,41 +60315,41 @@ defparam \ula_|pcm_outl[13]~feeder .lut_mask = 16'hFF00; defparam \ula_|pcm_outl[13]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N2 +// Location: LCCOMB_X24_Y19_N30 cycloneive_lcell_comb \ula_|always0~2 ( // Equation(s): -// \ula_|always0~2_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) +// \ula_|always0~2_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nRD_out~2_combout )) - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), + .dataa(gnd), + .datab(\z80_|memory_ifc_|nWR_out~0_combout ), .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), + .datad(\z80_|memory_ifc_|nRD_out~2_combout ), .cin(gnd), .combout(\ula_|always0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~2 .lut_mask = 16'h2020; +defparam \ula_|always0~2 .lut_mask = 16'h00C0; defparam \ula_|always0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N20 +// Location: LCCOMB_X23_Y19_N2 cycloneive_lcell_comb \ula_|always0~3 ( // Equation(s): -// \ula_|always0~3_combout = (!\z80_|address_pins_|DFFE_apin_latch [0] & (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~2_combout ))) +// \ula_|always0~3_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [0] & (!\z80_|control_pins_|pin_nIORQ~1_combout & \ula_|always0~2_combout ))) - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|control_pins_|pin_nIORQ~1_combout ), .datad(\ula_|always0~2_combout ), .cin(gnd), .combout(\ula_|always0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~3 .lut_mask = 16'h4000; +defparam \ula_|always0~3 .lut_mask = 16'h0200; defparam \ula_|always0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y19_N25 +// Location: FF_X23_Y19_N17 dffeas \ula_|pcm_outl[13] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|pcm_outl[13]~feeder_combout ), @@ -57076,20 +60368,20 @@ defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N26 +// Location: LCCOMB_X24_Y32_N0 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( // Equation(s): // \ula_|i2s_intf_|shiftreg[0]~19_combout = (\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|LessThan0~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h008A; +defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h2202; defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57103,25 +60395,25 @@ defparam \AUD_ADCDAT~input .bus_hold = "false"; defparam \AUD_ADCDAT~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N20 +// Location: LCCOMB_X23_Y33_N6 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~20 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [0])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\AUD_ADCDAT~input_o ))))) # -// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (((\ula_|i2s_intf_|shiftreg [0])))) +// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|shiftreg [0])))) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\AUD_ADCDAT~input_o ))) # +// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (\ula_|i2s_intf_|shiftreg [0])))) - .dataa(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|shiftreg[0]~19_combout ), .datac(\ula_|i2s_intf_|shiftreg [0]), .datad(\AUD_ADCDAT~input_o ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[0]~20_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF2D0; +defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF4B0; defparam \ula_|i2s_intf_|shiftreg[0]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N21 +// Location: FF_X23_Y33_N7 dffeas \ula_|i2s_intf_|shiftreg[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg[0]~20_combout ), @@ -57140,41 +60432,41 @@ defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N26 +// Location: LCCOMB_X23_Y33_N28 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~18 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~18_combout = (\ula_|i2s_intf_|shiftreg [0] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [0]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [0]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [0]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~2 ( +// Location: LCCOMB_X24_Y32_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[1]~2 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg[4]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & \ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) +// \ula_|i2s_intf_|shiftreg[1]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[1]~1_combout )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datac(\ula_|i2s_intf_|shiftreg[1]~1_combout ), + .datad(gnd), .cin(gnd), - .combout(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .combout(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4]~2 .lut_mask = 16'hFCF0; -defparam \ula_|i2s_intf_|shiftreg[4]~2 .sum_lutc_input = "datac"; +defparam \ula_|i2s_intf_|shiftreg[1]~2 .lut_mask = 16'hEAEA; +defparam \ula_|i2s_intf_|shiftreg[1]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N27 +// Location: FF_X23_Y33_N29 dffeas \ula_|i2s_intf_|shiftreg[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~18_combout ), @@ -57183,7 +60475,7 @@ dffeas \ula_|i2s_intf_|shiftreg[1] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [1]), @@ -57193,24 +60485,24 @@ defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N24 +// Location: LCCOMB_X23_Y33_N14 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~17_combout = (\ula_|i2s_intf_|shiftreg [1] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [1]) .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|shiftreg [1]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [1]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N25 +// Location: FF_X23_Y33_N15 dffeas \ula_|i2s_intf_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~17_combout ), @@ -57219,7 +60511,7 @@ dffeas \ula_|i2s_intf_|shiftreg[2] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [2]), @@ -57229,24 +60521,24 @@ defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N18 +// Location: LCCOMB_X23_Y33_N16 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~16_combout = (\ula_|i2s_intf_|shiftreg [2] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), .datab(\ula_|i2s_intf_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N19 +// Location: FF_X23_Y33_N17 dffeas \ula_|i2s_intf_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~16_combout ), @@ -57255,7 +60547,7 @@ dffeas \ula_|i2s_intf_|shiftreg[3] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [3]), @@ -57265,24 +60557,24 @@ defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N0 +// Location: LCCOMB_X23_Y33_N22 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~15_combout = (\ula_|i2s_intf_|shiftreg [3] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~15_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [3]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [3]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [3]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N1 +// Location: FF_X23_Y33_N23 dffeas \ula_|i2s_intf_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~15_combout ), @@ -57291,7 +60583,7 @@ dffeas \ula_|i2s_intf_|shiftreg[4] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [4]), @@ -57301,24 +60593,24 @@ defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N10 +// Location: LCCOMB_X23_Y33_N12 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~14_combout = (\ula_|i2s_intf_|shiftreg [4] & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [4]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|shiftreg [4]), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~14_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h0A0A; defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N11 +// Location: FF_X23_Y33_N13 dffeas \ula_|i2s_intf_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~14_combout ), @@ -57327,7 +60619,7 @@ dffeas \ula_|i2s_intf_|shiftreg[5] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [5]), @@ -57337,24 +60629,24 @@ defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N16 +// Location: LCCOMB_X23_Y33_N18 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~13_combout = (\ula_|i2s_intf_|shiftreg [5] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~13_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [5]) - .dataa(\ula_|i2s_intf_|shiftreg [5]), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [5]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N17 +// Location: FF_X23_Y33_N19 dffeas \ula_|i2s_intf_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~13_combout ), @@ -57363,7 +60655,7 @@ dffeas \ula_|i2s_intf_|shiftreg[6] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [6]), @@ -57373,24 +60665,24 @@ defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N30 +// Location: LCCOMB_X23_Y33_N8 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~12_combout = (\ula_|i2s_intf_|shiftreg [6] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~12_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [6]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [6]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [6]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N31 +// Location: FF_X23_Y33_N9 dffeas \ula_|i2s_intf_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~12_combout ), @@ -57399,7 +60691,7 @@ dffeas \ula_|i2s_intf_|shiftreg[7] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [7]), @@ -57409,24 +60701,24 @@ defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N28 +// Location: LCCOMB_X23_Y33_N2 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~11_combout = (\ula_|i2s_intf_|shiftreg [7] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|shiftreg [7]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|shiftreg [7]), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~11_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N29 +// Location: FF_X23_Y33_N3 dffeas \ula_|i2s_intf_|shiftreg[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~11_combout ), @@ -57435,7 +60727,7 @@ dffeas \ula_|i2s_intf_|shiftreg[8] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [8]), @@ -57445,24 +60737,24 @@ defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N22 +// Location: LCCOMB_X23_Y33_N4 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~10_combout = (\ula_|i2s_intf_|shiftreg [8] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~10_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [8]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [8]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [8]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N23 +// Location: FF_X23_Y33_N5 dffeas \ula_|i2s_intf_|shiftreg[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~10_combout ), @@ -57471,7 +60763,7 @@ dffeas \ula_|i2s_intf_|shiftreg[9] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [9]), @@ -57481,24 +60773,24 @@ defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N12 +// Location: LCCOMB_X23_Y33_N10 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [9] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|shiftreg [9]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|shiftreg [9]), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N13 +// Location: FF_X23_Y33_N11 dffeas \ula_|i2s_intf_|shiftreg[10] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~9_combout ), @@ -57507,7 +60799,7 @@ dffeas \ula_|i2s_intf_|shiftreg[10] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [10]), @@ -57517,24 +60809,24 @@ defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N2 +// Location: LCCOMB_X23_Y33_N0 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~8_combout = (\ula_|i2s_intf_|shiftreg [10] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~8_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [10]) - .dataa(\ula_|i2s_intf_|shiftreg [10]), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [10]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N3 +// Location: FF_X23_Y33_N1 dffeas \ula_|i2s_intf_|shiftreg[11] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~8_combout ), @@ -57543,7 +60835,7 @@ dffeas \ula_|i2s_intf_|shiftreg[11] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [11]), @@ -57553,24 +60845,24 @@ defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N8 +// Location: LCCOMB_X23_Y33_N26 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~7_combout = (\ula_|i2s_intf_|shiftreg [11] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~7_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [11]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [11]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [11]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N9 +// Location: FF_X23_Y33_N27 dffeas \ula_|i2s_intf_|shiftreg[12] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~7_combout ), @@ -57579,7 +60871,7 @@ dffeas \ula_|i2s_intf_|shiftreg[12] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [12]), @@ -57589,7 +60881,7 @@ defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N30 +// Location: LCCOMB_X23_Y32_N10 cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( // Equation(s): // \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INR [14]))))) # @@ -57607,7 +60899,7 @@ defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hB8F0; defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N31 +// Location: FF_X23_Y32_N11 dffeas \ula_|i2s_intf_|PCM_INR[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), @@ -57626,7 +60918,7 @@ defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N28 +// Location: LCCOMB_X23_Y32_N12 cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INL[14]~0 ( // Equation(s): // \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INL [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])))) # @@ -57644,7 +60936,7 @@ defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF0B8; defparam \ula_|i2s_intf_|PCM_INL[14]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N29 +// Location: FF_X23_Y32_N13 dffeas \ula_|i2s_intf_|PCM_INL[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), @@ -57663,24 +60955,24 @@ defparam \ula_|i2s_intf_|PCM_INL[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|PCM_INL[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N6 +// Location: LCCOMB_X23_Y32_N0 cycloneive_lcell_comb \ula_|pcm_outr~0 ( // Equation(s): // \ula_|pcm_outr~0_combout = (\ula_|i2s_intf_|PCM_INR [14]) # (\ula_|i2s_intf_|PCM_INL [14]) - .dataa(gnd), + .dataa(\ula_|i2s_intf_|PCM_INR [14]), .datab(gnd), - .datac(\ula_|i2s_intf_|PCM_INR [14]), + .datac(gnd), .datad(\ula_|i2s_intf_|PCM_INL [14]), .cin(gnd), .combout(\ula_|pcm_outr~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFF0; +defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFAA; defparam \ula_|pcm_outr~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N7 +// Location: FF_X23_Y32_N1 dffeas \ula_|pcm_outl[12] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|pcm_outr~0_combout ), @@ -57699,24 +60991,24 @@ defparam \ula_|pcm_outl[12] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N14 +// Location: LCCOMB_X23_Y33_N20 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~6 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [12]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [12])) - .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg [12]), + .dataa(\ula_|i2s_intf_|shiftreg [12]), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), .datad(\ula_|pcm_outl [12]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFC30; +defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFA0A; defparam \ula_|i2s_intf_|shiftreg~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N15 +// Location: FF_X23_Y33_N21 dffeas \ula_|i2s_intf_|shiftreg[13] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~6_combout ), @@ -57725,7 +61017,7 @@ dffeas \ula_|i2s_intf_|shiftreg[13] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [13]), @@ -57735,24 +61027,24 @@ defparam \ula_|i2s_intf_|shiftreg[13] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N4 +// Location: LCCOMB_X23_Y33_N30 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) .dataa(gnd), .datab(\ula_|pcm_outl [13]), - .datac(\ula_|i2s_intf_|shiftreg [13]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [13]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hCCF0; +defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hCFC0; defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N5 +// Location: FF_X23_Y33_N31 dffeas \ula_|i2s_intf_|shiftreg[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~5_combout ), @@ -57761,7 +61053,7 @@ dffeas \ula_|i2s_intf_|shiftreg[14] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [14]), @@ -57771,10 +61063,27 @@ defparam \ula_|i2s_intf_|shiftreg[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[14] .power_up = "low"; // synopsys translate_on -// Location: FF_X29_Y14_N31 +// Location: LCCOMB_X23_Y19_N22 +cycloneive_lcell_comb \ula_|pcm_outl[14]~feeder ( +// Equation(s): +// \ula_|pcm_outl[14]~feeder_combout = \D[4]~111_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\D[4]~111_combout ), + .cin(gnd), + .combout(\ula_|pcm_outl[14]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|pcm_outl[14]~feeder .lut_mask = 16'hFF00; +defparam \ula_|pcm_outl[14]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N23 dffeas \ula_|pcm_outl[14] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\D[4]~98_combout ), + .d(\ula_|pcm_outl[14]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -57790,24 +61099,24 @@ defparam \ula_|pcm_outl[14] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y22_N4 +// Location: LCCOMB_X23_Y33_N24 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~4 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) .dataa(\ula_|i2s_intf_|shiftreg [14]), .datab(gnd), - .datac(\ula_|pcm_outl [14]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|pcm_outl [14]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hF0AA; +defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hFA0A; defparam \ula_|i2s_intf_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y22_N5 +// Location: FF_X23_Y33_N25 dffeas \ula_|i2s_intf_|shiftreg[15] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~4_combout ), @@ -57816,7 +61125,7 @@ dffeas \ula_|i2s_intf_|shiftreg[15] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [15]), @@ -57826,24 +61135,24 @@ defparam \ula_|i2s_intf_|shiftreg[15] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y22_N0 +// Location: LCCOMB_X20_Y33_N0 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~3 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~3_combout = (\ula_|i2s_intf_|shiftreg [15] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~3_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [15]) .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2s_intf_|shiftreg [15]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|shiftreg [15]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h3300; defparam \ula_|i2s_intf_|shiftreg~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y22_N1 +// Location: FF_X20_Y33_N1 dffeas \ula_|i2s_intf_|shiftreg[16] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~3_combout ), @@ -57852,7 +61161,7 @@ dffeas \ula_|i2s_intf_|shiftreg[16] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [16]), @@ -57862,20 +61171,20 @@ defparam \ula_|i2s_intf_|shiftreg[16] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y22_N10 +// Location: LCCOMB_X20_Y33_N14 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~0 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~0_combout = (\ula_|i2s_intf_|shiftreg [16] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~0_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [16]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [16]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [16]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h3300; defparam \ula_|i2s_intf_|shiftreg~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57888,7 +61197,7 @@ dffeas \ula_|i2s_intf_|shiftreg[17] ( .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ), + .ena(\ula_|i2s_intf_|shiftreg[1]~2_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2s_intf_|shiftreg [17]), @@ -57898,135 +61207,32 @@ defparam \ula_|i2s_intf_|shiftreg[17] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N8 -cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Location: LCCOMB_X27_Y18_N12 +cycloneive_lcell_comb \ula_|border[1]~feeder ( // Equation(s): -// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [6]))) +// \ula_|border[1]~feeder_combout = \D[1]~41_combout - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|vga_vc [8]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [6]), - .cin(gnd), - .combout(\ula_|video_|LessThan2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N4 -cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( -// Equation(s): -// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) - - .dataa(\ula_|video_|vga_vc [2]), - .datab(\ula_|video_|vga_vc [3]), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|LessThan6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0111; -defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N30 -cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( -// Equation(s): -// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(\ula_|video_|vga_vc [4]), - .datac(\ula_|video_|LessThan2~0_combout ), - .datad(\ula_|video_|LessThan6~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan2~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7050; -defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N16 -cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( -// Equation(s): -// \ula_|video_|LessThan3~0_combout = ((\ula_|video_|LessThan6~0_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) # (!\ula_|video_|vga_vc [9]) - - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|LessThan6~0_combout ), - .datac(\ula_|video_|vga_vc [5]), - .datad(\ula_|video_|Equal2~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h5D55; -defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N22 -cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( -// Equation(s): -// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [6] & !\ula_|video_|vga_hc [5])) - - .dataa(\ula_|video_|vga_hc [4]), - .datab(\ula_|video_|vga_hc [6]), + .dataa(gnd), + .datab(gnd), .datac(gnd), - .datad(\ula_|video_|vga_hc [5]), + .datad(\D[1]~41_combout ), .cin(gnd), - .combout(\ula_|video_|LessThan0~0_combout ), + .combout(\ula_|border[1]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0011; -defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; +defparam \ula_|border[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|border[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N24 -cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( -// Equation(s): -// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((\ula_|video_|LessThan0~0_combout & !\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # -// ((!\ula_|video_|LessThan0~0_combout & \ula_|video_|vga_hc [7])))) - - .dataa(\ula_|video_|LessThan0~0_combout ), - .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|vga_hc [7]), - .datad(\ula_|video_|vga_hc [9]), - .cin(gnd), - .combout(\ula_|video_|disp_enable~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h3BDC; -defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N2 -cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( -// Equation(s): -// \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) - - .dataa(\ula_|video_|LessThan2~1_combout ), - .datab(\ula_|video_|LessThan3~0_combout ), - .datac(gnd), - .datad(\ula_|video_|disp_enable~0_combout ), - .cin(gnd), - .combout(\ula_|video_|disp_enable~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h4400; -defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N11 +// Location: FF_X27_Y18_N13 dffeas \ula_|border[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\D[1]~34_combout ), + .d(\ula_|border[1]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58037,58 +61243,75 @@ defparam \ula_|border[1] .is_wysiwyg = "true"; defparam \ula_|border[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N8 +// Location: LCCOMB_X32_Y30_N28 +cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( +// Equation(s): +// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) + + .dataa(\ula_|video_|vga_vc [1]), + .datab(\ula_|video_|vga_vc [2]), + .datac(\ula_|video_|vga_vc [3]), + .datad(\ula_|video_|vga_vc [0]), + .cin(gnd), + .combout(\ula_|video_|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0103; +defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y30_N14 cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( // Equation(s): // \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) - .dataa(\ula_|video_|vga_vc [6]), + .dataa(\ula_|video_|vga_vc [4]), .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|vga_vc [4]), + .datac(\ula_|video_|vga_vc [6]), .datad(\ula_|video_|LessThan6~0_combout ), .cin(gnd), .combout(\ula_|video_|LessThan6~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h7757; +defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h3F1F; defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N28 +// Location: LCCOMB_X29_Y30_N6 cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( // Equation(s): -// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) +// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [5] & !\ula_|video_|vga_hc [4])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) - .dataa(\ula_|video_|vga_hc [4]), - .datab(\ula_|video_|vga_hc [5]), - .datac(\ula_|video_|vga_hc [6]), + .dataa(\ula_|video_|vga_hc [5]), + .datab(\ula_|video_|vga_hc [6]), + .datac(\ula_|video_|vga_hc [4]), .datad(\ula_|video_|vga_hc [7]), .cin(gnd), .combout(\ula_|video_|LessThan4~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h1FFF; +defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h37FF; defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N10 +// Location: LCCOMB_X31_Y30_N10 cycloneive_lcell_comb \ula_|video_|screen_en~0 ( // Equation(s): // \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) - .dataa(\ula_|video_|vga_hc [9]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|LessThan4~0_combout ), - .datad(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|vga_hc [9]), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|LessThan4~0_combout ), .cin(gnd), .combout(\ula_|video_|screen_en~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1121; +defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1411; defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N22 +// Location: LCCOMB_X31_Y30_N24 cycloneive_lcell_comb \ula_|video_|screen_en~1 ( // Equation(s): // \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # @@ -58106,151 +61329,7 @@ defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE700; defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N28 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N10 -cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( -// Equation(s): -// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h0080; -defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N29 -dffeas \ula_|video_|attr_prefetch[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N12 -cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( -// Equation(s): -// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & \ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; -defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y33_N27 -dffeas \ula_|video_|attr[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N10 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N11 -dffeas \ula_|video_|attr_prefetch[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y33_N13 -dffeas \ula_|video_|attr[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N24 +// Location: LCCOMB_X30_Y28_N0 cycloneive_lcell_comb \ula_|video_|attr_prefetch[7]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 @@ -58267,7 +61346,24 @@ defparam \ula_|video_|attr_prefetch[7]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N25 +// Location: LCCOMB_X30_Y29_N20 +cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( +// Equation(s): +// \ula_|video_|Decoder0~1_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & \ula_|video_|vga_hc [1]))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h4000; +defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N1 dffeas \ula_|video_|attr_prefetch[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[7]~feeder_combout ), @@ -58286,7 +61382,24 @@ defparam \ula_|video_|attr_prefetch[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[7] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N5 +// Location: LCCOMB_X30_Y29_N10 +cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( +// Equation(s): +// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & \ula_|video_|vga_hc [1]))) + + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; +defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y30_N7 dffeas \ula_|video_|attr[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58305,32 +61418,32 @@ defparam \ula_|video_|attr[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y33_N22 +// Location: LCCOMB_X34_Y30_N4 cycloneive_lcell_comb \ula_|video_|frame[0]~12 ( // Equation(s): // \ula_|video_|frame[0]~12_combout = \ula_|video_|Equal3~1_combout $ (\ula_|video_|frame [0]) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(gnd), - .datac(\ula_|video_|frame [0]), - .datad(gnd), + .dataa(gnd), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(gnd), + .datad(\ula_|video_|frame [0]), .cin(gnd), .combout(\ula_|video_|frame[0]~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h5A5A; +defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h33CC; defparam \ula_|video_|frame[0]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y33_N23 +// Location: FF_X34_Y30_N21 dffeas \ula_|video_|frame[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[0]~12_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|frame[0]~12_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(vcc), .devclrn(devclrn), .devpor(devpor), @@ -58341,14 +61454,14 @@ defparam \ula_|video_|frame[0] .is_wysiwyg = "true"; defparam \ula_|video_|frame[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N24 +// Location: LCCOMB_X34_Y30_N14 cycloneive_lcell_comb \ula_|video_|frame[1]~4 ( // Equation(s): -// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [0] & (\ula_|video_|frame [1] $ (VCC))) # (!\ula_|video_|frame [0] & (\ula_|video_|frame [1] & VCC)) -// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [0] & \ula_|video_|frame [1])) +// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [1] & (\ula_|video_|frame [0] $ (VCC))) # (!\ula_|video_|frame [1] & (\ula_|video_|frame [0] & VCC)) +// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [1] & \ula_|video_|frame [0])) - .dataa(\ula_|video_|frame [0]), - .datab(\ula_|video_|frame [1]), + .dataa(\ula_|video_|frame [1]), + .datab(\ula_|video_|frame [0]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -58359,7 +61472,7 @@ defparam \ula_|video_|frame[1]~4 .lut_mask = 16'h6688; defparam \ula_|video_|frame[1]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y33_N25 +// Location: FF_X34_Y30_N15 dffeas \ula_|video_|frame[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[1]~4_combout ), @@ -58378,25 +61491,25 @@ defparam \ula_|video_|frame[1] .is_wysiwyg = "true"; defparam \ula_|video_|frame[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N26 +// Location: LCCOMB_X34_Y30_N16 cycloneive_lcell_comb \ula_|video_|frame[2]~6 ( // Equation(s): // \ula_|video_|frame[2]~6_combout = (\ula_|video_|frame [2] & (!\ula_|video_|frame[1]~5 )) # (!\ula_|video_|frame [2] & ((\ula_|video_|frame[1]~5 ) # (GND))) // \ula_|video_|frame[2]~7 = CARRY((!\ula_|video_|frame[1]~5 ) # (!\ula_|video_|frame [2])) - .dataa(\ula_|video_|frame [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|frame [2]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|frame[1]~5 ), .combout(\ula_|video_|frame[2]~6_combout ), .cout(\ula_|video_|frame[2]~7 )); // synopsys translate_off -defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h3C3F; defparam \ula_|video_|frame[2]~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N27 +// Location: FF_X34_Y30_N17 dffeas \ula_|video_|frame[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[2]~6_combout ), @@ -58415,7 +61528,7 @@ defparam \ula_|video_|frame[2] .is_wysiwyg = "true"; defparam \ula_|video_|frame[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N28 +// Location: LCCOMB_X34_Y30_N18 cycloneive_lcell_comb \ula_|video_|frame[3]~8 ( // Equation(s): // \ula_|video_|frame[3]~8_combout = (\ula_|video_|frame [3] & (\ula_|video_|frame[2]~7 $ (GND))) # (!\ula_|video_|frame [3] & (!\ula_|video_|frame[2]~7 & VCC)) @@ -58433,7 +61546,7 @@ defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hC30C; defparam \ula_|video_|frame[3]~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N29 +// Location: FF_X34_Y30_N19 dffeas \ula_|video_|frame[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[3]~8_combout ), @@ -58452,32 +61565,32 @@ defparam \ula_|video_|frame[3] .is_wysiwyg = "true"; defparam \ula_|video_|frame[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N30 +// Location: LCCOMB_X34_Y30_N20 cycloneive_lcell_comb \ula_|video_|frame[4]~10 ( // Equation(s): -// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame [4] $ (\ula_|video_|frame[3]~9 ) +// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame[3]~9 $ (\ula_|video_|frame [4]) - .dataa(\ula_|video_|frame [4]), + .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|video_|frame [4]), .cin(\ula_|video_|frame[3]~9 ), .combout(\ula_|video_|frame[4]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h5A5A; +defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h0FF0; defparam \ula_|video_|frame[4]~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N31 +// Location: FF_X34_Y30_N5 dffeas \ula_|video_|frame[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[4]~10_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|frame[4]~10_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|video_|Equal3~1_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58488,7 +61601,7 @@ defparam \ula_|video_|frame[4] .is_wysiwyg = "true"; defparam \ula_|video_|frame[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N4 +// Location: LCCOMB_X30_Y30_N6 cycloneive_lcell_comb \ula_|video_|inverted ( // Equation(s): // \ula_|video_|inverted~combout = (\ula_|video_|attr [7] & \ula_|video_|frame [4]) @@ -58505,7 +61618,7 @@ defparam \ula_|video_|inverted .lut_mask = 16'hF000; defparam \ula_|video_|inverted .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N12 +// Location: LCCOMB_X30_Y28_N28 cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 @@ -58522,24 +61635,24 @@ defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N8 +// Location: LCCOMB_X30_Y29_N14 cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( // Equation(s): -// \ula_|video_|Decoder0~2_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) +// \ula_|video_|Decoder0~2_combout = (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & !\ula_|video_|vga_hc [1]))) - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), + .dataa(\ula_|video_|vga_hc [0]), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|vga_hc [3]), + .datad(\ula_|video_|vga_hc [1]), .cin(gnd), .combout(\ula_|video_|Decoder0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0008; +defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0040; defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N13 +// Location: FF_X30_Y28_N29 dffeas \ula_|video_|bits_prefetch[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), @@ -58558,32 +61671,15 @@ defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N6 -cycloneive_lcell_comb \ula_|video_|bits[6]~feeder ( -// Equation(s): -// \ula_|video_|bits[6]~feeder_combout = \ula_|video_|bits_prefetch [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|bits_prefetch [6]), - .cin(gnd), - .combout(\ula_|video_|bits[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y33_N7 +// Location: FF_X30_Y30_N5 dffeas \ula_|video_|bits[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits[6]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [6]), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58594,7 +61690,7 @@ defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; defparam \ula_|video_|bits[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N22 +// Location: LCCOMB_X30_Y28_N26 cycloneive_lcell_comb \ula_|video_|bits_prefetch[4]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 @@ -58611,7 +61707,7 @@ defparam \ula_|video_|bits_prefetch[4]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[4]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N23 +// Location: FF_X30_Y28_N27 dffeas \ula_|video_|bits_prefetch[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[4]~feeder_combout ), @@ -58630,7 +61726,7 @@ defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N23 +// Location: FF_X30_Y30_N29 dffeas \ula_|video_|bits[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58649,7 +61745,7 @@ defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; defparam \ula_|video_|bits[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N18 +// Location: LCCOMB_X30_Y28_N14 cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 @@ -58666,7 +61762,7 @@ defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N19 +// Location: FF_X30_Y28_N15 dffeas \ula_|video_|bits_prefetch[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), @@ -58685,7 +61781,7 @@ defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N18 +// Location: LCCOMB_X30_Y30_N24 cycloneive_lcell_comb \ula_|video_|bits[5]~feeder ( // Equation(s): // \ula_|video_|bits[5]~feeder_combout = \ula_|video_|bits_prefetch [5] @@ -58702,7 +61798,7 @@ defparam \ula_|video_|bits[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N19 +// Location: FF_X30_Y30_N25 dffeas \ula_|video_|bits[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[5]~feeder_combout ), @@ -58721,7 +61817,7 @@ defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; defparam \ula_|video_|bits[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N0 +// Location: LCCOMB_X30_Y28_N12 cycloneive_lcell_comb \ula_|video_|bits_prefetch[7]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 @@ -58738,7 +61834,7 @@ defparam \ula_|video_|bits_prefetch[7]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N1 +// Location: FF_X30_Y28_N13 dffeas \ula_|video_|bits_prefetch[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[7]~feeder_combout ), @@ -58757,7 +61853,7 @@ defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N1 +// Location: FF_X30_Y30_N19 dffeas \ula_|video_|bits[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58776,41 +61872,41 @@ defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; defparam \ula_|video_|bits[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N0 +// Location: LCCOMB_X30_Y30_N18 cycloneive_lcell_comb \ula_|video_|Mux0~0 ( // Equation(s): // \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [5])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [7]))))) - .dataa(\ula_|video_|bits [5]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [5]), .datac(\ula_|video_|bits [7]), .datad(\ula_|video_|vga_hc [2]), .cin(gnd), .combout(\ula_|video_|Mux0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE30; +defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE50; defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N22 +// Location: LCCOMB_X30_Y30_N28 cycloneive_lcell_comb \ula_|video_|Mux0~1 ( // Equation(s): // \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) - .dataa(\ula_|video_|bits [6]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [6]), .datac(\ula_|video_|bits [4]), .datad(\ula_|video_|Mux0~0_combout ), .cin(gnd), .combout(\ula_|video_|Mux0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF388; +defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF588; defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N16 +// Location: LCCOMB_X30_Y28_N20 cycloneive_lcell_comb \ula_|video_|bits_prefetch[2]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 @@ -58827,7 +61923,7 @@ defparam \ula_|video_|bits_prefetch[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N17 +// Location: FF_X30_Y28_N21 dffeas \ula_|video_|bits_prefetch[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[2]~feeder_combout ), @@ -58846,7 +61942,7 @@ defparam \ula_|video_|bits_prefetch[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N12 +// Location: LCCOMB_X30_Y30_N14 cycloneive_lcell_comb \ula_|video_|bits[2]~feeder ( // Equation(s): // \ula_|video_|bits[2]~feeder_combout = \ula_|video_|bits_prefetch [2] @@ -58863,7 +61959,7 @@ defparam \ula_|video_|bits[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N13 +// Location: FF_X30_Y30_N15 dffeas \ula_|video_|bits[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[2]~feeder_combout ), @@ -58882,7 +61978,7 @@ defparam \ula_|video_|bits[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N14 +// Location: LCCOMB_X30_Y28_N18 cycloneive_lcell_comb \ula_|video_|bits_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -58899,7 +61995,7 @@ defparam \ula_|video_|bits_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N15 +// Location: FF_X30_Y28_N19 dffeas \ula_|video_|bits_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[0]~feeder_combout ), @@ -58918,7 +62014,7 @@ defparam \ula_|video_|bits_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N3 +// Location: FF_X30_Y30_N1 dffeas \ula_|video_|bits[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58937,7 +62033,7 @@ defparam \ula_|video_|bits[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N6 +// Location: LCCOMB_X30_Y28_N6 cycloneive_lcell_comb \ula_|video_|bits_prefetch[1]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 @@ -58954,7 +62050,7 @@ defparam \ula_|video_|bits_prefetch[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N7 +// Location: FF_X30_Y28_N7 dffeas \ula_|video_|bits_prefetch[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[1]~feeder_combout ), @@ -58973,7 +62069,7 @@ defparam \ula_|video_|bits_prefetch[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N26 +// Location: LCCOMB_X30_Y30_N20 cycloneive_lcell_comb \ula_|video_|bits[1]~feeder ( // Equation(s): // \ula_|video_|bits[1]~feeder_combout = \ula_|video_|bits_prefetch [1] @@ -58990,7 +62086,7 @@ defparam \ula_|video_|bits[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N27 +// Location: FF_X30_Y30_N21 dffeas \ula_|video_|bits[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[1]~feeder_combout ), @@ -59009,7 +62105,7 @@ defparam \ula_|video_|bits[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N4 +// Location: LCCOMB_X30_Y28_N24 cycloneive_lcell_comb \ula_|video_|bits_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 @@ -59026,7 +62122,7 @@ defparam \ula_|video_|bits_prefetch[3]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N5 +// Location: FF_X30_Y28_N25 dffeas \ula_|video_|bits_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[3]~feeder_combout ), @@ -59045,7 +62141,7 @@ defparam \ula_|video_|bits_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N25 +// Location: FF_X30_Y30_N3 dffeas \ula_|video_|bits[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59064,92 +62160,305 @@ defparam \ula_|video_|bits[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N24 +// Location: LCCOMB_X30_Y30_N2 cycloneive_lcell_comb \ula_|video_|Mux0~2 ( // Equation(s): // \ula_|video_|Mux0~2_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [1])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [3]))))) - .dataa(\ula_|video_|bits [1]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [1]), .datac(\ula_|video_|bits [3]), .datad(\ula_|video_|vga_hc [2]), .cin(gnd), .combout(\ula_|video_|Mux0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE30; +defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE50; defparam \ula_|video_|Mux0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N2 +// Location: LCCOMB_X30_Y30_N0 cycloneive_lcell_comb \ula_|video_|Mux0~3 ( // Equation(s): // \ula_|video_|Mux0~3_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~2_combout & ((\ula_|video_|bits [0]))) # (!\ula_|video_|Mux0~2_combout & (\ula_|video_|bits [2])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~2_combout )))) - .dataa(\ula_|video_|bits [2]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [2]), .datac(\ula_|video_|bits [0]), .datad(\ula_|video_|Mux0~2_combout ), .cin(gnd), .combout(\ula_|video_|Mux0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF388; +defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF588; defparam \ula_|video_|Mux0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N10 -cycloneive_lcell_comb \ula_|video_|cindex[1]~0 ( +// Location: LCCOMB_X30_Y30_N10 +cycloneive_lcell_comb \ula_|video_|cindex[2]~0 ( // Equation(s): -// \ula_|video_|cindex[1]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~3_combout ))) # (!\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~1_combout )))) +// \ula_|video_|cindex[2]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~3_combout ))) # (!\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~1_combout )))) - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|inverted~combout ), - .datac(\ula_|video_|Mux0~1_combout ), + .dataa(\ula_|video_|inverted~combout ), + .datab(\ula_|video_|Mux0~1_combout ), + .datac(\ula_|video_|vga_hc [3]), .datad(\ula_|video_|Mux0~3_combout ), .cin(gnd), - .combout(\ula_|video_|cindex[1]~0_combout ), + .combout(\ula_|video_|cindex[2]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h369C; -defparam \ula_|video_|cindex[1]~0 .sum_lutc_input = "datac"; +defparam \ula_|video_|cindex[2]~0 .lut_mask = 16'h56A6; +defparam \ula_|video_|cindex[2]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N12 +// Location: LCCOMB_X30_Y28_N10 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N11 +dffeas \ula_|video_|attr_prefetch[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y30_N17 +dffeas \ula_|video_|attr[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y28_N4 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N5 +dffeas \ula_|video_|attr_prefetch[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y30_N19 +dffeas \ula_|video_|attr[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y30_N16 cycloneive_lcell_comb \ula_|video_|cindex[1]~1 ( // Equation(s): -// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [1])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [4]))) +// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [1]))) # (!\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [4])) - .dataa(\ula_|video_|attr [1]), + .dataa(\ula_|video_|cindex[2]~0_combout ), .datab(gnd), .datac(\ula_|video_|attr [4]), - .datad(\ula_|video_|cindex[1]~0_combout ), + .datad(\ula_|video_|attr [1]), .cin(gnd), .combout(\ula_|video_|cindex[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hAAF0; +defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hFA50; defparam \ula_|video_|cindex[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N24 +// Location: LCCOMB_X31_Y30_N4 +cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Equation(s): +// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) + + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|vga_vc [6]), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|vga_vc [8]), + .cin(gnd), + .combout(\ula_|video_|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N2 +cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( +// Equation(s): +// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|vga_vc [5]), + .datac(\ula_|video_|LessThan2~0_combout ), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7030; +defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N14 +cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( +// Equation(s): +// \ula_|video_|LessThan3~0_combout = ((!\ula_|video_|vga_vc [5] & (\ula_|video_|Equal2~0_combout & \ula_|video_|LessThan6~0_combout ))) # (!\ula_|video_|vga_vc [9]) + + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|vga_vc [5]), + .datac(\ula_|video_|Equal2~0_combout ), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h7555; +defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N0 +cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( +// Equation(s): +// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [5] & !\ula_|video_|vga_hc [6])) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(gnd), + .datac(\ula_|video_|vga_hc [5]), + .datad(\ula_|video_|vga_hc [6]), + .cin(gnd), + .combout(\ula_|video_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0005; +defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y30_N4 +cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( +// Equation(s): +// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((!\ula_|video_|vga_hc [7] & \ula_|video_|LessThan0~0_combout )) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # ((\ula_|video_|vga_hc [7] & +// !\ula_|video_|LessThan0~0_combout )))) + + .dataa(\ula_|video_|vga_hc [7]), + .datab(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [9]), + .datad(\ula_|video_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|video_|disp_enable~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h7C3E; +defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N12 +cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( +// Equation(s): +// \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) + + .dataa(gnd), + .datab(\ula_|video_|LessThan2~1_combout ), + .datac(\ula_|video_|LessThan3~0_combout ), + .datad(\ula_|video_|disp_enable~0_combout ), + .cin(gnd), + .combout(\ula_|video_|disp_enable~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h3000; +defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y30_N26 cycloneive_lcell_comb \ula_|video_|VGA_R[0]~0 ( // Equation(s): // \ula_|video_|VGA_R[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[1]~1_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [1])))) - .dataa(\ula_|video_|disp_enable~1_combout ), - .datab(\ula_|border [1]), - .datac(\ula_|video_|screen_en~1_combout ), - .datad(\ula_|video_|cindex[1]~1_combout ), + .dataa(\ula_|border [1]), + .datab(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|cindex[1]~1_combout ), + .datad(\ula_|video_|disp_enable~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hA808; +defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hE200; defparam \ula_|video_|VGA_R[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N26 +// Location: LCCOMB_X30_Y28_N22 cycloneive_lcell_comb \ula_|video_|attr_prefetch[6]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 @@ -59166,7 +62475,7 @@ defparam \ula_|video_|attr_prefetch[6]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N27 +// Location: FF_X30_Y28_N23 dffeas \ula_|video_|attr_prefetch[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[6]~feeder_combout ), @@ -59185,7 +62494,7 @@ defparam \ula_|video_|attr_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X38_Y33_N1 +// Location: FF_X31_Y30_N29 dffeas \ula_|video_|attr[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59204,49 +62513,66 @@ defparam \ula_|video_|attr[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N0 +// Location: LCCOMB_X31_Y30_N28 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~0 ( // Equation(s): -// \ula_|video_|VGA_B[1]~0_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & (\ula_|video_|attr [6] & \ula_|video_|disp_enable~0_combout ))) +// \ula_|video_|VGA_B[1]~0_combout = (\ula_|video_|LessThan3~0_combout & (\ula_|video_|disp_enable~0_combout & (\ula_|video_|attr [6] & !\ula_|video_|LessThan2~1_combout ))) - .dataa(\ula_|video_|LessThan2~1_combout ), - .datab(\ula_|video_|LessThan3~0_combout ), + .dataa(\ula_|video_|LessThan3~0_combout ), + .datab(\ula_|video_|disp_enable~0_combout ), .datac(\ula_|video_|attr [6]), - .datad(\ula_|video_|disp_enable~0_combout ), + .datad(\ula_|video_|LessThan2~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h4000; +defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h0080; defparam \ula_|video_|VGA_B[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N2 +// Location: LCCOMB_X31_Y30_N6 cycloneive_lcell_comb \ula_|video_|VGA_R[1]~1 ( // Equation(s): -// \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[1]~1_combout )) +// \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[1]~1_combout )) - .dataa(\ula_|video_|screen_en~1_combout ), - .datab(gnd), - .datac(\ula_|video_|VGA_B[1]~0_combout ), - .datad(\ula_|video_|cindex[1]~1_combout ), + .dataa(\ula_|video_|VGA_B[1]~0_combout ), + .datab(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|cindex[1]~1_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|VGA_R[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'hA000; +defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'h8080; defparam \ula_|video_|VGA_R[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y12_N17 +// Location: LCCOMB_X30_Y27_N20 +cycloneive_lcell_comb \ula_|border[2]~feeder ( +// Equation(s): +// \ula_|border[2]~feeder_combout = \D[2]~53_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\D[2]~53_combout ), + .cin(gnd), + .combout(\ula_|border[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|border[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|border[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y27_N21 dffeas \ula_|border[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\D[2]~46_combout ), + .d(\ula_|border[2]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -59257,62 +62583,7 @@ defparam \ula_|border[2] .is_wysiwyg = "true"; defparam \ula_|border[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N8 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N9 -dffeas \ula_|video_|attr_prefetch[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y33_N21 -dffeas \ula_|video_|attr[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N30 +// Location: LCCOMB_X30_Y28_N30 cycloneive_lcell_comb \ula_|video_|attr_prefetch[5]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 @@ -59329,7 +62600,7 @@ defparam \ula_|video_|attr_prefetch[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N31 +// Location: FF_X30_Y28_N31 dffeas \ula_|video_|attr_prefetch[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[5]~feeder_combout ), @@ -59348,7 +62619,7 @@ defparam \ula_|video_|attr_prefetch[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[5] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N15 +// Location: FF_X30_Y30_N31 dffeas \ula_|video_|attr[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59367,66 +62638,138 @@ defparam \ula_|video_|attr[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N14 -cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( +// Location: LCCOMB_X30_Y28_N16 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( // Equation(s): -// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [2])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [5]))) +// \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 .dataa(gnd), - .datab(\ula_|video_|attr [2]), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N17 +dffeas \ula_|video_|attr_prefetch[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y30_N13 +dffeas \ula_|video_|attr[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y30_N30 +cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( +// Equation(s): +// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [2]))) # (!\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [5])) + + .dataa(\ula_|video_|cindex[2]~0_combout ), + .datab(gnd), .datac(\ula_|video_|attr [5]), - .datad(\ula_|video_|cindex[1]~0_combout ), + .datad(\ula_|video_|attr [2]), .cin(gnd), .combout(\ula_|video_|cindex[2]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hCCF0; +defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hFA50; defparam \ula_|video_|cindex[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N26 +// Location: LCCOMB_X31_Y30_N0 cycloneive_lcell_comb \ula_|video_|VGA_G[0]~0 ( // Equation(s): // \ula_|video_|VGA_G[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[2]~2_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [2])))) - .dataa(\ula_|border [2]), + .dataa(\ula_|video_|disp_enable~1_combout ), .datab(\ula_|video_|screen_en~1_combout ), - .datac(\ula_|video_|disp_enable~1_combout ), + .datac(\ula_|border [2]), .datad(\ula_|video_|cindex[2]~2_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hE020; +defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hA820; defparam \ula_|video_|VGA_G[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N20 +// Location: LCCOMB_X31_Y30_N18 cycloneive_lcell_comb \ula_|video_|VGA_G[1]~1 ( // Equation(s): -// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|cindex[2]~2_combout & \ula_|video_|screen_en~1_combout )) +// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[2]~2_combout )) .dataa(\ula_|video_|VGA_B[1]~0_combout ), - .datab(\ula_|video_|cindex[2]~2_combout ), - .datac(gnd), - .datad(\ula_|video_|screen_en~1_combout ), + .datab(gnd), + .datac(\ula_|video_|screen_en~1_combout ), + .datad(\ula_|video_|cindex[2]~2_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_G[1]~1 .lut_mask = 16'h8800; +defparam \ula_|video_|VGA_G[1]~1 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_G[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N1 +// Location: LCCOMB_X26_Y15_N4 +cycloneive_lcell_comb \ula_|border[0]~feeder ( +// Equation(s): +// \ula_|border[0]~feeder_combout = \D[0]~65_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\D[0]~65_combout ), + .cin(gnd), + .combout(\ula_|border[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|border[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|border[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y15_N5 dffeas \ula_|border[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\D[0]~58_combout ), + .d(\ula_|border[0]~feeder_combout ), + .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -59437,7 +62780,7 @@ defparam \ula_|border[0] .is_wysiwyg = "true"; defparam \ula_|border[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N20 +// Location: LCCOMB_X30_Y28_N8 cycloneive_lcell_comb \ula_|video_|attr_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -59454,7 +62797,7 @@ defparam \ula_|video_|attr_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N21 +// Location: FF_X30_Y28_N9 dffeas \ula_|video_|attr_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[0]~feeder_combout ), @@ -59473,32 +62816,15 @@ defparam \ula_|video_|attr_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N28 -cycloneive_lcell_comb \ula_|video_|attr[0]~feeder ( -// Equation(s): -// \ula_|video_|attr[0]~feeder_combout = \ula_|video_|attr_prefetch [0] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|attr_prefetch [0]), - .cin(gnd), - .combout(\ula_|video_|attr[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y33_N29 +// Location: FF_X29_Y30_N23 dffeas \ula_|video_|attr[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr[0]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [0]), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -59509,7 +62835,7 @@ defparam \ula_|video_|attr[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N2 +// Location: LCCOMB_X30_Y28_N2 cycloneive_lcell_comb \ula_|video_|attr_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 @@ -59526,7 +62852,7 @@ defparam \ula_|video_|attr_prefetch[3]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N3 +// Location: FF_X30_Y28_N3 dffeas \ula_|video_|attr_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[3]~feeder_combout ), @@ -59545,7 +62871,7 @@ defparam \ula_|video_|attr_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N29 +// Location: FF_X30_Y30_N9 dffeas \ula_|video_|attr[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59564,15 +62890,15 @@ defparam \ula_|video_|attr[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N28 +// Location: LCCOMB_X30_Y30_N8 cycloneive_lcell_comb \ula_|video_|cindex[0]~3 ( // Equation(s): -// \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [3]))) +// \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[2]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[2]~0_combout & ((\ula_|video_|attr [3]))) .dataa(gnd), .datab(\ula_|video_|attr [0]), .datac(\ula_|video_|attr [3]), - .datad(\ula_|video_|cindex[1]~0_combout ), + .datad(\ula_|video_|cindex[2]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[0]~3_combout ), .cout()); @@ -59581,58 +62907,58 @@ defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hCCF0; defparam \ula_|video_|cindex[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N30 +// Location: LCCOMB_X30_Y30_N26 cycloneive_lcell_comb \ula_|video_|VGA_B[0]~1 ( // Equation(s): // \ula_|video_|VGA_B[0]~1_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[0]~3_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [0])))) - .dataa(\ula_|video_|disp_enable~1_combout ), - .datab(\ula_|border [0]), - .datac(\ula_|video_|screen_en~1_combout ), - .datad(\ula_|video_|cindex[0]~3_combout ), + .dataa(\ula_|border [0]), + .datab(\ula_|video_|cindex[0]~3_combout ), + .datac(\ula_|video_|disp_enable~1_combout ), + .datad(\ula_|video_|screen_en~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[0]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hA808; +defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hC0A0; defparam \ula_|video_|VGA_B[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N0 +// Location: LCCOMB_X30_Y30_N12 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~2 ( // Equation(s): -// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[0]~3_combout )) +// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|cindex[0]~3_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|screen_en~1_combout )) - .dataa(\ula_|video_|screen_en~1_combout ), - .datab(gnd), - .datac(\ula_|video_|VGA_B[1]~0_combout ), - .datad(\ula_|video_|cindex[0]~3_combout ), + .dataa(\ula_|video_|cindex[0]~3_combout ), + .datab(\ula_|video_|VGA_B[1]~0_combout ), + .datac(gnd), + .datad(\ula_|video_|screen_en~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[1]~2 .lut_mask = 16'hA000; +defparam \ula_|video_|VGA_B[1]~2 .lut_mask = 16'h8800; defparam \ula_|video_|VGA_B[1]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N26 +// Location: LCCOMB_X29_Y29_N12 cycloneive_lcell_comb \ula_|video_|Equal0~2 ( // Equation(s): -// \ula_|video_|Equal0~2_combout = (\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [9] & !\ula_|video_|vga_hc [8])) +// \ula_|video_|Equal0~2_combout = (!\ula_|video_|vga_hc [9] & (!\ula_|video_|vga_hc [8] & \ula_|video_|vga_hc [6])) - .dataa(\ula_|video_|vga_hc [6]), - .datab(\ula_|video_|vga_hc [9]), - .datac(gnd), - .datad(\ula_|video_|vga_hc [8]), + .dataa(\ula_|video_|vga_hc [9]), + .datab(gnd), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|vga_hc [6]), .cin(gnd), .combout(\ula_|video_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0022; +defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0500; defparam \ula_|video_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y33_N7 +// Location: FF_X29_Y29_N1 dffeas \ula_|video_|VGA_HS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector0~0_combout ), @@ -59651,7 +62977,7 @@ defparam \ula_|video_|VGA_HS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N6 +// Location: LCCOMB_X29_Y29_N0 cycloneive_lcell_comb \ula_|video_|Selector0~0 ( // Equation(s): // \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|Equal1~0_combout & \ula_|video_|VGA_HS~_Duplicate_1_q )))) # (!\ula_|video_|Equal0~2_combout & (\ula_|video_|Equal1~0_combout & @@ -59688,7 +63014,7 @@ defparam \ula_|video_|VGA_HS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS .power_up = "low"; // synopsys translate_on -// Location: FF_X34_Y33_N25 +// Location: FF_X32_Y30_N1 dffeas \ula_|video_|VGA_VS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector1~0_combout ), @@ -59707,21 +63033,21 @@ defparam \ula_|video_|VGA_VS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y33_N24 +// Location: LCCOMB_X32_Y30_N0 cycloneive_lcell_comb \ula_|video_|Selector1~0 ( // Equation(s): -// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal3~1_combout & (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1])))) # (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|VGA_VS~_Duplicate_1_q ) # ((\ula_|video_|Equal2~2_combout & -// \ula_|video_|vga_vc [1])))) +// \ula_|video_|Selector1~0_combout = (\ula_|video_|vga_vc [1] & ((\ula_|video_|Equal2~2_combout ) # ((\ula_|video_|VGA_VS~_Duplicate_1_q & !\ula_|video_|Equal3~1_combout )))) # (!\ula_|video_|vga_vc [1] & (((\ula_|video_|VGA_VS~_Duplicate_1_q & +// !\ula_|video_|Equal3~1_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), + .dataa(\ula_|video_|vga_vc [1]), .datab(\ula_|video_|Equal2~2_combout ), .datac(\ula_|video_|VGA_VS~_Duplicate_1_q ), - .datad(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector1~0 .lut_mask = 16'hDC50; +defparam \ula_|video_|Selector1~0 .lut_mask = 16'h88F8; defparam \ula_|video_|Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59744,7 +63070,7 @@ defparam \ula_|video_|VGA_VS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N4 +// Location: LCCOMB_X40_Y13_N4 cycloneive_lcell_comb \z80_|memory_ifc_|q1~feeder ( // Equation(s): // \z80_|memory_ifc_|q1~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -59761,7 +63087,7 @@ defparam \z80_|memory_ifc_|q1~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|q1~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X47_Y17_N5 +// Location: FF_X40_Y13_N5 dffeas \z80_|memory_ifc_|q1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|q1~feeder_combout ), @@ -59780,7 +63106,7 @@ defparam \z80_|memory_ifc_|q1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q1 .power_up = "low"; // synopsys translate_on -// Location: FF_X47_Y17_N25 +// Location: FF_X40_Y13_N3 dffeas \z80_|memory_ifc_|q2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -59799,7 +63125,7 @@ defparam \z80_|memory_ifc_|q2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N24 +// Location: LCCOMB_X40_Y13_N2 cycloneive_lcell_comb \z80_|memory_ifc_|nRFSH_out~0 ( // Equation(s): // \z80_|memory_ifc_|nRFSH_out~0_combout = (!\z80_|memory_ifc_|q2~q & \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) @@ -59816,7 +63142,7 @@ defparam \z80_|memory_ifc_|nRFSH_out~0 .lut_mask = 16'h0F00; defparam \z80_|memory_ifc_|nRFSH_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N26 +// Location: LCCOMB_X40_Y13_N24 cycloneive_lcell_comb \z80_|memory_ifc_|nM1_out ( // Equation(s): // \z80_|memory_ifc_|nM1_out~combout = (\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) @@ -59833,24 +63159,24 @@ defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF0F; defparam \z80_|memory_ifc_|nM1_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y26_N0 +// Location: LCCOMB_X23_Y19_N24 cycloneive_lcell_comb \ula_|beep~0 ( // Equation(s): -// \ula_|beep~0_combout = \D[4]~98_combout $ (\raw_loader_in~input_o $ (\D[3]~96_combout )) +// \ula_|beep~0_combout = \D[3]~109_combout $ (\raw_loader_in~input_o $ (\D[4]~111_combout )) - .dataa(gnd), - .datab(\D[4]~98_combout ), + .dataa(\D[3]~109_combout ), + .datab(gnd), .datac(\raw_loader_in~input_o ), - .datad(\D[3]~96_combout ), + .datad(\D[4]~111_combout ), .cin(gnd), .combout(\ula_|beep~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|beep~0 .lut_mask = 16'hC33C; +defparam \ula_|beep~0 .lut_mask = 16'hA55A; defparam \ula_|beep~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y26_N1 +// Location: FF_X23_Y19_N25 dffeas \ula_|beep ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|beep~0_combout ), @@ -59869,6 +63195,2526 @@ defparam \ula_|beep .is_wysiwyg = "true"; defparam \ula_|beep .power_up = "low"; // synopsys translate_on +// Location: LCCOMB_X23_Y10_N4 +cycloneive_lcell_comb \sdram_|Mux26~4 ( +// Equation(s): +// \sdram_|Mux26~4_combout = (!\sdram_|r.address[3]~6_combout & ((\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\sdram_|r.address[3]~6_combout ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [9]), + .cin(gnd), + .combout(\sdram_|Mux26~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux26~4 .lut_mask = 16'h3311; +defparam \sdram_|Mux26~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N10 +cycloneive_lcell_comb \sdram_|r.bank[0]~7 ( +// Equation(s): +// \sdram_|r.bank[0]~7_combout = (\sdram_|r.state [6] & \sdram_|r.state [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|r.bank[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~7 .lut_mask = 16'hF000; +defparam \sdram_|r.bank[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N8 +cycloneive_lcell_comb \sdram_|r.bank[0]~11 ( +// Equation(s): +// \sdram_|r.bank[0]~11_combout = (\sdram_|r.rd_pending~q & ((\sdram_|Equal7~2_combout ) # ((\sdram_|r.bank[0]~7_combout )))) # (!\sdram_|r.rd_pending~q & (((\sdram_|r.wr_pending~q & \sdram_|r.bank[0]~7_combout )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.bank[0]~7_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~11 .lut_mask = 16'hFCA0; +defparam \sdram_|r.bank[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N28 +cycloneive_lcell_comb \sdram_|r.bank[0]~4 ( +// Equation(s): +// \sdram_|r.bank[0]~4_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.rd_pending~q ) # (\sdram_|r.wr_pending~q ))) + + .dataa(gnd), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~4 .lut_mask = 16'hF0C0; +defparam \sdram_|r.bank[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N28 +cycloneive_lcell_comb \sdram_|r.bank[0]~5 ( +// Equation(s): +// \sdram_|r.bank[0]~5_combout = (\sdram_|r.state [5] & (!\sdram_|r.state [4] & ((!\sdram_|r.bank[0]~4_combout ) # (!\sdram_|r.state [7])))) # (!\sdram_|r.state [5] & (((\sdram_|r.state [7])))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.bank[0]~4_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~5 .lut_mask = 16'h3474; +defparam \sdram_|r.bank[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N4 +cycloneive_lcell_comb \sdram_|r.bank[0]~6 ( +// Equation(s): +// \sdram_|r.bank[0]~6_combout = (\sdram_|r.state [8] & (((\sdram_|r.state [6])))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & ((!\sdram_|r.bank[0]~5_combout ) # (!\sdram_|r.state [6]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [6]) # +// (\sdram_|r.bank[0]~5_combout ))))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.bank[0]~5_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~6 .lut_mask = 16'hB5F4; +defparam \sdram_|r.bank[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N28 +cycloneive_lcell_comb \sdram_|r.bank[0]~8 ( +// Equation(s): +// \sdram_|r.bank[0]~8_combout = (\sdram_|r.state [5] & (\sdram_|r.state [4] & \sdram_|r.state [7])) # (!\sdram_|r.state [5] & (!\sdram_|r.state [4] & !\sdram_|r.state [7])) + + .dataa(gnd), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.bank[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~8 .lut_mask = 16'hC003; +defparam \sdram_|r.bank[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N18 +cycloneive_lcell_comb \sdram_|r.bank[0]~12 ( +// Equation(s): +// \sdram_|r.bank[0]~12_combout = (\sdram_|r.bank[0]~8_combout & ((\sdram_|r.bank[0]~11_combout ) # ((\sdram_|Equal7~2_combout & \sdram_|r.wr_pending~q )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.bank[0]~11_combout ), + .datad(\sdram_|r.bank[0]~8_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~12 .lut_mask = 16'hF800; +defparam \sdram_|r.bank[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N2 +cycloneive_lcell_comb \sdram_|r.bank[0]~9 ( +// Equation(s): +// \sdram_|r.bank[0]~9_combout = (\sdram_|r.state [8] & (\sdram_|r.bank[0]~12_combout & ((\sdram_|r.bank[0]~11_combout ) # (!\sdram_|r.bank[0]~6_combout )))) # (!\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~6_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.bank[0]~11_combout ), + .datac(\sdram_|r.bank[0]~6_combout ), + .datad(\sdram_|r.bank[0]~12_combout ), + .cin(gnd), + .combout(\sdram_|r.bank[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~9 .lut_mask = 16'h8F05; +defparam \sdram_|r.bank[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X11_Y0_N18 +dffeas \sdram_|r.bank[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux26~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.bank[0]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.bank [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.bank[0] .is_wysiwyg = "true"; +defparam \sdram_|r.bank[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N2 +cycloneive_lcell_comb \sdram_|Mux25~4 ( +// Equation(s): +// \sdram_|Mux25~4_combout = (!\sdram_|r.address[3]~6_combout & ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [10]), + .datac(gnd), + .datad(\sdram_|r.address[3]~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux25~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux25~4 .lut_mask = 16'h00DD; +defparam \sdram_|Mux25~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X7_Y0_N11 +dffeas \sdram_|r.bank[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux25~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.bank[0]~9_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.bank [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.bank[1] .is_wysiwyg = "true"; +defparam \sdram_|r.bank[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N6 +cycloneive_lcell_comb \sdram_|Mux24~5 ( +// Equation(s): +// \sdram_|Mux24~5_combout = (!\sdram_|r.state [6] & (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|Equal7~2_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux24~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~5 .lut_mask = 16'h0515; +defparam \sdram_|Mux24~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N24 +cycloneive_lcell_comb \sdram_|Mux71~0 ( +// Equation(s): +// \sdram_|Mux71~0_combout = (!\sdram_|r.state [4] & !\sdram_|r.state [5]) + + .dataa(gnd), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [5]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|Mux71~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~0 .lut_mask = 16'h0303; +defparam \sdram_|Mux71~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N4 +cycloneive_lcell_comb \sdram_|process_0~7 ( +// Equation(s): +// \sdram_|process_0~7_combout = \sdram_|r.act_row [4] $ (((\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\sdram_|r.act_row [4]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\sdram_|process_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~7 .lut_mask = 16'h3C0F; +defparam \sdram_|process_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N28 +cycloneive_lcell_comb \sdram_|process_0~4 ( +// Equation(s): +// \sdram_|process_0~4_combout = ((\sdram_|process_0~7_combout ) # ((!\sdram_|Equal7~0_combout ) # (!\sdram_|Equal7~1_combout ))) # (!\sdram_|r.rd_pending~q ) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|process_0~7_combout ), + .datac(\sdram_|Equal7~1_combout ), + .datad(\sdram_|Equal7~0_combout ), + .cin(gnd), + .combout(\sdram_|process_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~4 .lut_mask = 16'hDFFF; +defparam \sdram_|process_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N30 +cycloneive_lcell_comb \sdram_|Mux71~1 ( +// Equation(s): +// \sdram_|Mux71~1_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [6]) # ((!\sdram_|r.state [4]) # (!\sdram_|r.state [5])))) # (!\sdram_|r.state [8] & (!\sdram_|r.state [6] & ((\sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux71~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~1 .lut_mask = 16'h9BAA; +defparam \sdram_|Mux71~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N28 +cycloneive_lcell_comb \sdram_|Mux71~2 ( +// Equation(s): +// \sdram_|Mux71~2_combout = (\sdram_|r.state [7] & ((\sdram_|Mux71~1_combout ) # ((!\sdram_|r.state [8] & \sdram_|Mux71~0_combout )))) # (!\sdram_|r.state [7] & (!\sdram_|r.state [8])) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux71~1_combout ), + .datad(\sdram_|Mux71~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux71~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~2 .lut_mask = 16'hD5D1; +defparam \sdram_|Mux71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N14 +cycloneive_lcell_comb \sdram_|Mux71~3 ( +// Equation(s): +// \sdram_|Mux71~3_combout = (\sdram_|Mux71~2_combout ) # ((\sdram_|process_0~4_combout & (\sdram_|Mux71~0_combout & \sdram_|r.state [6]))) + + .dataa(\sdram_|process_0~4_combout ), + .datab(\sdram_|Mux71~0_combout ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux71~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux71~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~3 .lut_mask = 16'hFF80; +defparam \sdram_|Mux71~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N4 +cycloneive_lcell_comb \sdram_|Mux71~4 ( +// Equation(s): +// \sdram_|Mux71~4_combout = (\sdram_|Mux71~3_combout ) # ((\sdram_|Mux24~5_combout & ((\sdram_|Mux71~0_combout ) # (\sdram_|r.state [7])))) + + .dataa(\sdram_|Mux24~5_combout ), + .datab(\sdram_|Mux71~0_combout ), + .datac(\sdram_|Mux71~3_combout ), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|Mux71~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux71~4 .lut_mask = 16'hFAF8; +defparam \sdram_|Mux71~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X14_Y0_N11 +dffeas \sdram_|r.dq_masks[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux71~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.dq_masks [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.dq_masks[0] .is_wysiwyg = "true"; +defparam \sdram_|r.dq_masks[0] .power_up = "low"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X14_Y0_N18 +dffeas \sdram_|r.dq_masks[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux71~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.dq_masks [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.dq_masks[1] .is_wysiwyg = "true"; +defparam \sdram_|r.dq_masks[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N2 +cycloneive_lcell_comb \sdram_|r.bank[0]~10 ( +// Equation(s): +// \sdram_|r.bank[0]~10_combout = \sdram_|r.state [5] $ (\sdram_|r.state [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.bank[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.bank[0]~10 .lut_mask = 16'h0FF0; +defparam \sdram_|r.bank[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N18 +cycloneive_lcell_comb \sdram_|Mux9~3 ( +// Equation(s): +// \sdram_|Mux9~3_combout = (\sdram_|r.bank[0]~10_combout ) # ((!\sdram_|n~2_combout & (\sdram_|r.state [6] & \sdram_|r.state [4]))) + + .dataa(\sdram_|n~2_combout ), + .datab(\sdram_|r.state [6]), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.bank[0]~10_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~3 .lut_mask = 16'hFF40; +defparam \sdram_|Mux9~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y12_N30 +cycloneive_lcell_comb \sdram_|n~5 ( +// Equation(s): +// \sdram_|n~5_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|Equal7~2_combout ) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) + + .dataa(\sdram_|r.rd_pending~q ), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|n~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|n~5 .lut_mask = 16'h3031; +defparam \sdram_|n~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N12 +cycloneive_lcell_comb \sdram_|Mux9~4 ( +// Equation(s): +// \sdram_|Mux9~4_combout = (\sdram_|Mux9~3_combout ) # ((\sdram_|r.state [7] & (\sdram_|n~5_combout & !\sdram_|r.state [6]))) + + .dataa(\sdram_|Mux9~3_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|n~5_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux9~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~4 .lut_mask = 16'hAAEA; +defparam \sdram_|Mux9~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N4 +cycloneive_lcell_comb \sdram_|Mux9~2 ( +// Equation(s): +// \sdram_|Mux9~2_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [4] & (!\sdram_|r.state [7])) # (!\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (\sdram_|n~5_combout ))))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|n~5_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux9~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~2 .lut_mask = 16'h7600; +defparam \sdram_|Mux9~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N30 +cycloneive_lcell_comb \sdram_|Equal2~3 ( +// Equation(s): +// \sdram_|Equal2~3_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [0] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [7]))) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [0]), + .datac(\sdram_|Equal2~2_combout ), + .datad(\sdram_|r.init_counter [7]), + .cin(gnd), + .combout(\sdram_|Equal2~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal2~3 .lut_mask = 16'h2000; +defparam \sdram_|Equal2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N8 +cycloneive_lcell_comb \sdram_|Mux10~2 ( +// Equation(s): +// \sdram_|Mux10~2_combout = (\sdram_|r.init_counter [6]) # ((\sdram_|r.init_counter [5]) # (\sdram_|r.init_counter [4])) + + .dataa(gnd), + .datab(\sdram_|r.init_counter [6]), + .datac(\sdram_|r.init_counter [5]), + .datad(\sdram_|r.init_counter [4]), + .cin(gnd), + .combout(\sdram_|Mux10~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~2 .lut_mask = 16'hFFFC; +defparam \sdram_|Mux10~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N26 +cycloneive_lcell_comb \sdram_|Mux10~3 ( +// Equation(s): +// \sdram_|Mux10~3_combout = (\sdram_|r.init_counter [1] & ((\sdram_|r.init_counter [2] & (!\sdram_|r.init_counter [3])) # (!\sdram_|r.init_counter [2] & (\sdram_|r.init_counter [3] & !\sdram_|Mux10~2_combout )))) + + .dataa(\sdram_|r.init_counter [2]), + .datab(\sdram_|r.init_counter [3]), + .datac(\sdram_|Mux10~2_combout ), + .datad(\sdram_|r.init_counter [1]), + .cin(gnd), + .combout(\sdram_|Mux10~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~3 .lut_mask = 16'h2600; +defparam \sdram_|Mux10~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N4 +cycloneive_lcell_comb \sdram_|process_0~6 ( +// Equation(s): +// \sdram_|process_0~6_combout = (!\sdram_|r.init_counter [9] & (!\sdram_|r.init_counter [8] & (\sdram_|process_0~5_combout & !\sdram_|r.init_counter [10]))) + + .dataa(\sdram_|r.init_counter [9]), + .datab(\sdram_|r.init_counter [8]), + .datac(\sdram_|process_0~5_combout ), + .datad(\sdram_|r.init_counter [10]), + .cin(gnd), + .combout(\sdram_|process_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|process_0~6 .lut_mask = 16'h0010; +defparam \sdram_|process_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y3_N24 +cycloneive_lcell_comb \sdram_|Mux10~4 ( +// Equation(s): +// \sdram_|Mux10~4_combout = ((\sdram_|r.init_counter [7]) # ((!\sdram_|r.init_counter [0]) # (!\sdram_|process_0~6_combout ))) # (!\sdram_|Mux10~3_combout ) + + .dataa(\sdram_|Mux10~3_combout ), + .datab(\sdram_|r.init_counter [7]), + .datac(\sdram_|process_0~6_combout ), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Mux10~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~4 .lut_mask = 16'hDFFF; +defparam \sdram_|Mux10~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N22 +cycloneive_lcell_comb \sdram_|Mux9~5 ( +// Equation(s): +// \sdram_|Mux9~5_combout = (\sdram_|r.state [6]) # ((\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|n~2_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|n~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~5 .lut_mask = 16'hEAEE; +defparam \sdram_|Mux9~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N20 +cycloneive_lcell_comb \sdram_|Mux7~0 ( +// Equation(s): +// \sdram_|Mux7~0_combout = (!\sdram_|r.state [7] & !\sdram_|r.state [4]) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(gnd), + .datad(\sdram_|r.state [4]), + .cin(gnd), + .combout(\sdram_|Mux7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux7~0 .lut_mask = 16'h0033; +defparam \sdram_|Mux7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N10 +cycloneive_lcell_comb \sdram_|Mux9~6 ( +// Equation(s): +// \sdram_|Mux9~6_combout = (\sdram_|Mux9~5_combout ) # ((!\sdram_|Equal2~3_combout & (\sdram_|Mux10~4_combout & \sdram_|Mux7~0_combout ))) + + .dataa(\sdram_|Equal2~3_combout ), + .datab(\sdram_|Mux10~4_combout ), + .datac(\sdram_|Mux9~5_combout ), + .datad(\sdram_|Mux7~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~6 .lut_mask = 16'hF4F0; +defparam \sdram_|Mux9~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N24 +cycloneive_lcell_comb \sdram_|Mux9~7 ( +// Equation(s): +// \sdram_|Mux9~7_combout = (\sdram_|Mux9~4_combout ) # ((\sdram_|Mux9~2_combout ) # ((!\sdram_|r.state [8] & \sdram_|Mux9~6_combout ))) + + .dataa(\sdram_|Mux9~4_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|Mux9~2_combout ), + .datad(\sdram_|Mux9~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux9~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux9~7 .lut_mask = 16'hFBFA; +defparam \sdram_|Mux9~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y11_N4 +dffeas \sdram_|r.state[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux9~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[2] .is_wysiwyg = "true"; +defparam \sdram_|r.state[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N16 +cycloneive_lcell_comb \sdram_|Mux10~11 ( +// Equation(s): +// \sdram_|Mux10~11_combout = (\sdram_|r.rf_pending~q & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q )))) # (!\sdram_|r.rf_pending~q & (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|Equal7~2_combout ))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|Mux10~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~11 .lut_mask = 16'hAF9D; +defparam \sdram_|Mux10~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N12 +cycloneive_lcell_comb \sdram_|Mux10~6 ( +// Equation(s): +// \sdram_|Mux10~6_combout = (\sdram_|r.state [6] & (((\sdram_|process_0~4_combout ) # (!\sdram_|r.state [8])))) # (!\sdram_|r.state [6] & (\sdram_|Mux10~11_combout & ((\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Mux10~11_combout ), + .datac(\sdram_|process_0~4_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux10~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~6 .lut_mask = 16'hE4AA; +defparam \sdram_|Mux10~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N26 +cycloneive_lcell_comb \sdram_|Mux10~5 ( +// Equation(s): +// \sdram_|Mux10~5_combout = (\sdram_|r.state [8] & ((\sdram_|r.state [4]) # ((\sdram_|r.rf_pending~q )))) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & (!\sdram_|r.rf_pending~q )) # (!\sdram_|r.state [4] & ((\sdram_|Mux10~4_combout ))))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|Mux10~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~5 .lut_mask = 16'hBDAC; +defparam \sdram_|Mux10~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N10 +cycloneive_lcell_comb \sdram_|Mux10~7 ( +// Equation(s): +// \sdram_|Mux10~7_combout = (\sdram_|r.state [6] & (((!\sdram_|r.state [8]) # (!\sdram_|r.rf_pending~q )) # (!\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & ((\sdram_|r.rf_pending~q ) # (\sdram_|r.state [4] $ (\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.rf_pending~q ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux10~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~7 .lut_mask = 16'h7BFE; +defparam \sdram_|Mux10~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N20 +cycloneive_lcell_comb \sdram_|Mux10~8 ( +// Equation(s): +// \sdram_|Mux10~8_combout = (\sdram_|r.state [7] & ((\sdram_|Mux10~7_combout ) # ((\sdram_|Mux10~11_combout )))) # (!\sdram_|r.state [7] & (((\sdram_|Mux10~5_combout )))) + + .dataa(\sdram_|Mux10~7_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux10~5_combout ), + .datad(\sdram_|Mux10~11_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~8 .lut_mask = 16'hFCB8; +defparam \sdram_|Mux10~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N22 +cycloneive_lcell_comb \sdram_|Mux10~9 ( +// Equation(s): +// \sdram_|Mux10~9_combout = (\sdram_|r.bank[0]~10_combout ) # ((\sdram_|Mux10~8_combout ) # ((\sdram_|Mux10~6_combout & !\sdram_|Mux10~5_combout ))) + + .dataa(\sdram_|Mux10~6_combout ), + .datab(\sdram_|r.bank[0]~10_combout ), + .datac(\sdram_|Mux10~5_combout ), + .datad(\sdram_|Mux10~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux10~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux10~9 .lut_mask = 16'hFFCE; +defparam \sdram_|Mux10~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y11_N11 +dffeas \sdram_|r.state[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux10~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[1] .is_wysiwyg = "true"; +defparam \sdram_|r.state[1] .power_up = "low"; +// synopsys translate_on + +// Location: CLKCTRL_PLL1E0 +cycloneive_clkctrl \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk [1]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK_outclk )); +// synopsys translate_off +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK .clock_type = "external clock output"; +defparam \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK .ena_register_mode = "double register"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N8 +cycloneive_lcell_comb \sdram_|Mux11~2 ( +// Equation(s): +// \sdram_|Mux11~2_combout = (\sdram_|r.init_counter [7] $ (!\sdram_|r.init_counter [0])) # (!\sdram_|r.init_counter [1]) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [7]), + .datac(gnd), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Mux11~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~2 .lut_mask = 16'hDD77; +defparam \sdram_|Mux11~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N6 +cycloneive_lcell_comb \sdram_|Mux11~3 ( +// Equation(s): +// \sdram_|Mux11~3_combout = (!\sdram_|r.state [8] & (!\sdram_|r.state [6] & ((\sdram_|Mux11~2_combout ) # (!\sdram_|Equal2~2_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Equal2~2_combout ), + .datac(\sdram_|Mux11~2_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux11~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~3 .lut_mask = 16'h0051; +defparam \sdram_|Mux11~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N26 +cycloneive_lcell_comb \sdram_|Mux11~4 ( +// Equation(s): +// \sdram_|Mux11~4_combout = (!\sdram_|r.state [7] & ((\sdram_|Mux11~3_combout ) # ((\sdram_|r.state [4] & !\sdram_|Mux23~0_combout )))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux23~0_combout ), + .datad(\sdram_|Mux11~3_combout ), + .cin(gnd), + .combout(\sdram_|Mux11~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~4 .lut_mask = 16'h3302; +defparam \sdram_|Mux11~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N28 +cycloneive_lcell_comb \sdram_|Mux11~5 ( +// Equation(s): +// \sdram_|Mux11~5_combout = (\sdram_|r.state [7] & ((\sdram_|r.state [4] $ (\sdram_|r.state [8])) # (!\sdram_|r.state [5]))) # (!\sdram_|r.state [7] & (((\sdram_|r.state [5])))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux11~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~5 .lut_mask = 16'h7CBC; +defparam \sdram_|Mux11~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y7_N0 +cycloneive_lcell_comb \sdram_|Mux11~6 ( +// Equation(s): +// \sdram_|Mux11~6_combout = (!\sdram_|r.rf_pending~q & ((\sdram_|r.state [7]) # ((!\sdram_|r.state [6] & \sdram_|r.state [8])))) + + .dataa(\sdram_|r.rf_pending~q ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux11~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~6 .lut_mask = 16'h4544; +defparam \sdram_|Mux11~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N30 +cycloneive_lcell_comb \sdram_|Mux11~7 ( +// Equation(s): +// \sdram_|Mux11~7_combout = (!\sdram_|r.wr_pending~q & (\sdram_|Mux11~6_combout & ((\sdram_|Equal7~2_combout ) # (!\sdram_|r.rd_pending~q )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.wr_pending~q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|Mux11~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux11~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~7 .lut_mask = 16'h2300; +defparam \sdram_|Mux11~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N16 +cycloneive_lcell_comb \sdram_|Mux11~9 ( +// Equation(s): +// \sdram_|Mux11~9_combout = (\sdram_|r.state [6] & (((\sdram_|n~5_combout ) # (!\sdram_|Mux7~0_combout )) # (!\sdram_|r.state [8]))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|n~5_combout ), + .datad(\sdram_|Mux7~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux11~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~9 .lut_mask = 16'hA2AA; +defparam \sdram_|Mux11~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N14 +cycloneive_lcell_comb \sdram_|Mux11~8 ( +// Equation(s): +// \sdram_|Mux11~8_combout = (\sdram_|Mux11~4_combout ) # ((\sdram_|Mux11~5_combout ) # ((\sdram_|Mux11~7_combout ) # (\sdram_|Mux11~9_combout ))) + + .dataa(\sdram_|Mux11~4_combout ), + .datab(\sdram_|Mux11~5_combout ), + .datac(\sdram_|Mux11~7_combout ), + .datad(\sdram_|Mux11~9_combout ), + .cin(gnd), + .combout(\sdram_|Mux11~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux11~8 .lut_mask = 16'hFFFE; +defparam \sdram_|Mux11~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y27_N4 +dffeas \sdram_|r.state[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux11~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.state [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.state[0] .is_wysiwyg = "true"; +defparam \sdram_|r.state[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N20 +cycloneive_lcell_comb \sdram_|Mux24~2 ( +// Equation(s): +// \sdram_|Mux24~2_combout = (\sdram_|Equal7~2_combout & ((\sdram_|r.rd_pending~q ) # ((\sdram_|r.wr_pending~q & !\sdram_|r.state [6])))) + + .dataa(\sdram_|r.wr_pending~q ), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Equal7~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux24~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~2 .lut_mask = 16'hCE00; +defparam \sdram_|Mux24~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N2 +cycloneive_lcell_comb \sdram_|r.address[0]~7 ( +// Equation(s): +// \sdram_|r.address[0]~7_combout = (\sdram_|r.state [4] & ((\sdram_|process_0~2_combout & (\z80_|address_pins_|abus[11]~19_combout )) # (!\sdram_|process_0~2_combout & ((\sdram_|r.address[0]~_Duplicate_1_q ))))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\sdram_|r.address[0]~_Duplicate_1_q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|r.address[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[0]~7 .lut_mask = 16'hA0C0; +defparam \sdram_|r.address[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N12 +cycloneive_lcell_comb \sdram_|r.address[0]~0 ( +// Equation(s): +// \sdram_|r.address[0]~0_combout = (\sdram_|r.state [8] & (!\sdram_|Mux24~2_combout & (\sdram_|r.address[0]~_Duplicate_1_q ))) # (!\sdram_|r.state [8] & (((\sdram_|r.address[0]~7_combout )))) + + .dataa(\sdram_|Mux24~2_combout ), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.address[0]~_Duplicate_1_q ), + .datad(\sdram_|r.address[0]~7_combout ), + .cin(gnd), + .combout(\sdram_|r.address[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[0]~0 .lut_mask = 16'h7340; +defparam \sdram_|r.address[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N30 +cycloneive_lcell_comb \sdram_|Mux13~9 ( +// Equation(s): +// \sdram_|Mux13~9_combout = (!\sdram_|r.state [5] & ((\sdram_|r.state [8] & (!\sdram_|r.state [4])) # (!\sdram_|r.state [8] & ((!\sdram_|r.state [6]))))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux13~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~9 .lut_mask = 16'h0407; +defparam \sdram_|Mux13~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N0 +cycloneive_lcell_comb \sdram_|Mux13~4 ( +// Equation(s): +// \sdram_|Mux13~4_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] & (\sdram_|r.state [8] $ (!\sdram_|r.state [5])))) # (!\sdram_|r.state [6] & (\sdram_|r.state [5] & (\sdram_|r.state [4] $ (!\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [8]), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux13~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~4 .lut_mask = 16'h8290; +defparam \sdram_|Mux13~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y7_N2 +cycloneive_lcell_comb \sdram_|Mux13~5 ( +// Equation(s): +// \sdram_|Mux13~5_combout = (\sdram_|r.state [7] & ((\sdram_|Mux13~4_combout ))) # (!\sdram_|r.state [7] & (\sdram_|Mux13~9_combout )) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux13~9_combout ), + .datad(\sdram_|Mux13~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux13~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~5 .lut_mask = 16'hFC30; +defparam \sdram_|Mux13~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y11_N13 +dffeas \sdram_|r.address[0]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[0]~0_combout ), + .asdata(\sdram_|Mux24~4_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\sdram_|r.state [7]), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[0]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[0]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[0]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N4 +cycloneive_lcell_comb \sdram_|Mux24~3 ( +// Equation(s): +// \sdram_|Mux24~3_combout = (\sdram_|Mux23~0_combout & ((\sdram_|process_0~2_combout & (\z80_|address_pins_|abus[11]~19_combout )) # (!\sdram_|process_0~2_combout & ((\sdram_|r.address[0]~_Duplicate_1_q ))))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\sdram_|r.address[0]~_Duplicate_1_q ), + .datac(\sdram_|Mux23~0_combout ), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux24~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~3 .lut_mask = 16'hA0C0; +defparam \sdram_|Mux24~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N14 +cycloneive_lcell_comb \sdram_|Mux24~4 ( +// Equation(s): +// \sdram_|Mux24~4_combout = (\sdram_|Mux24~3_combout ) # ((!\sdram_|n~3_combout & (\sdram_|r.address[0]~_Duplicate_1_q & !\sdram_|r.state [6]))) + + .dataa(\sdram_|n~3_combout ), + .datab(\sdram_|r.address[0]~_Duplicate_1_q ), + .datac(\sdram_|Mux24~3_combout ), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|Mux24~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux24~4 .lut_mask = 16'hF0F4; +defparam \sdram_|Mux24~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N24 +cycloneive_lcell_comb \sdram_|r.address[0]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[0]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux24~4_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[0]~0_combout ))) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux24~4_combout ), + .datad(\sdram_|r.address[0]~0_combout ), + .cin(gnd), + .combout(\sdram_|r.address[0]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[0]~SLOAD_MUX .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[0]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y4_N18 +dffeas \sdram_|r.address[0] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[0]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[0] .is_wysiwyg = "true"; +defparam \sdram_|r.address[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N16 +cycloneive_lcell_comb \sdram_|r.address[1]~_Duplicate_1feeder ( +// Equation(s): +// \sdram_|r.address[1]~_Duplicate_1feeder_combout = \sdram_|r.address[1]~1_combout + + .dataa(\sdram_|r.address[1]~1_combout ), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[1]~_Duplicate_1feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~_Duplicate_1feeder .lut_mask = 16'hAAAA; +defparam \sdram_|r.address[1]~_Duplicate_1feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N20 +cycloneive_lcell_comb \sdram_|Mux23~4 ( +// Equation(s): +// \sdram_|Mux23~4_combout = (\sdram_|r.state [8] & (\sdram_|r.address[1]~_Duplicate_1_q )) # (!\sdram_|r.state [8] & ((\sdram_|process_0~2_combout & ((\z80_|address_pins_|abus[12]~24_combout ))) # (!\sdram_|process_0~2_combout & +// (\sdram_|r.address[1]~_Duplicate_1_q )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.address[1]~_Duplicate_1_q ), + .datac(\z80_|address_pins_|abus[12]~24_combout ), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux23~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~4 .lut_mask = 16'hD8CC; +defparam \sdram_|Mux23~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N16 +cycloneive_lcell_comb \sdram_|Equal5~0 ( +// Equation(s): +// \sdram_|Equal5~0_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [0]))) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [7]), + .datac(\sdram_|Equal2~2_combout ), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Equal5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Equal5~0 .lut_mask = 16'h2000; +defparam \sdram_|Equal5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N14 +cycloneive_lcell_comb \sdram_|Mux23~5 ( +// Equation(s): +// \sdram_|Mux23~5_combout = (\sdram_|r.state [8] & (\sdram_|Mux23~4_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.state [4] & (\sdram_|Mux23~4_combout )) # (!\sdram_|r.state [4] & ((\sdram_|Equal5~0_combout ))))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux23~4_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|Equal5~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux23~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~5 .lut_mask = 16'hCDC8; +defparam \sdram_|Mux23~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N8 +cycloneive_lcell_comb \sdram_|Mux23~6 ( +// Equation(s): +// \sdram_|Mux23~6_combout = (\sdram_|Mux23~5_combout & (((\sdram_|r.state [4]) # (!\sdram_|Mux24~2_combout )) # (!\sdram_|r.state [8]))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|Mux23~5_combout ), + .datad(\sdram_|Mux24~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux23~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~6 .lut_mask = 16'hD0F0; +defparam \sdram_|Mux23~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N2 +cycloneive_lcell_comb \sdram_|Mux19~0 ( +// Equation(s): +// \sdram_|Mux19~0_combout = (\sdram_|r.state [7] & (\sdram_|r.state [5] $ (((!\sdram_|r.state [8] & \sdram_|r.state [6]))))) # (!\sdram_|r.state [7] & (!\sdram_|r.state [5] & ((\sdram_|r.state [8]) # (!\sdram_|r.state [6])))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [5]), + .cin(gnd), + .combout(\sdram_|Mux19~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~0 .lut_mask = 16'h8C63; +defparam \sdram_|Mux19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y12_N17 +dffeas \sdram_|r.address[1]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[1]~_Duplicate_1feeder_combout ), + .asdata(\sdram_|Mux23~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(!\sdram_|r.state [7]), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[1]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[1]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[1]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N28 +cycloneive_lcell_comb \sdram_|Mux23~2 ( +// Equation(s): +// \sdram_|Mux23~2_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] & ((\sdram_|process_0~2_combout ) # (!\sdram_|r.state [8])))) # (!\sdram_|r.state [6] & (\sdram_|process_0~2_combout & (\sdram_|r.state [4] $ (!\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|process_0~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux23~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~2 .lut_mask = 16'hC0A4; +defparam \sdram_|Mux23~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N30 +cycloneive_lcell_comb \sdram_|Mux23~3 ( +// Equation(s): +// \sdram_|Mux23~3_combout = (\sdram_|Mux23~2_combout & ((\sdram_|r.state [6]) # (\sdram_|Equal7~2_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(gnd), + .datac(\sdram_|Equal7~2_combout ), + .datad(\sdram_|Mux23~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux23~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~3 .lut_mask = 16'hFA00; +defparam \sdram_|Mux23~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N18 +cycloneive_lcell_comb \sdram_|Mux23~1 ( +// Equation(s): +// \sdram_|Mux23~1_combout = (\sdram_|r.state [6] & (\sdram_|r.state [8] & ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) + + .dataa(\sdram_|r.state [6]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [12]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux23~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~1 .lut_mask = 16'hA200; +defparam \sdram_|Mux23~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N22 +cycloneive_lcell_comb \sdram_|r.address[1]~1 ( +// Equation(s): +// \sdram_|r.address[1]~1_combout = (\sdram_|Mux23~3_combout & ((\sdram_|Mux23~1_combout ))) # (!\sdram_|Mux23~3_combout & (\sdram_|r.address[1]~_Duplicate_1_q )) + + .dataa(gnd), + .datab(\sdram_|r.address[1]~_Duplicate_1_q ), + .datac(\sdram_|Mux23~3_combout ), + .datad(\sdram_|Mux23~1_combout ), + .cin(gnd), + .combout(\sdram_|r.address[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~1 .lut_mask = 16'hFC0C; +defparam \sdram_|r.address[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N2 +cycloneive_lcell_comb \sdram_|r.address[1]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[1]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|r.address[1]~1_combout )) # (!\sdram_|r.state [7] & ((\sdram_|Mux23~6_combout ))) + + .dataa(\sdram_|r.address[1]~1_combout ), + .datab(\sdram_|Mux23~6_combout ), + .datac(\sdram_|r.state [7]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[1]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[1]~SLOAD_MUX .lut_mask = 16'hACAC; +defparam \sdram_|r.address[1]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X5_Y0_N11 +dffeas \sdram_|r.address[1] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[1]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[1] .is_wysiwyg = "true"; +defparam \sdram_|r.address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N10 +cycloneive_lcell_comb \sdram_|r.address[3]~8 ( +// Equation(s): +// \sdram_|r.address[3]~8_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [5])) # (!\sdram_|r.state [6] & (((\sdram_|r.state [7]) # (\sdram_|r.state [8])))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|r.state [5]), + .datac(\sdram_|r.state [7]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.address[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~8 .lut_mask = 16'h7772; +defparam \sdram_|r.address[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N24 +cycloneive_lcell_comb \sdram_|r.address[3]~9 ( +// Equation(s): +// \sdram_|r.address[3]~9_combout = (\sdram_|r.state [5] & \sdram_|r.state [6]) + + .dataa(gnd), + .datab(\sdram_|r.state [5]), + .datac(gnd), + .datad(\sdram_|r.state [6]), + .cin(gnd), + .combout(\sdram_|r.address[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~9 .lut_mask = 16'hCC00; +defparam \sdram_|r.address[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N26 +cycloneive_lcell_comb \sdram_|Mux21~0 ( +// Equation(s): +// \sdram_|Mux21~0_combout = (!\sdram_|r.address[3]~8_combout & ((\sdram_|r.address[3]~9_combout ) # ((\sdram_|r.address[3]~6_combout & \sdram_|r.state [4])))) + + .dataa(\sdram_|r.address[3]~6_combout ), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.address[3]~9_combout ), + .datad(\sdram_|r.address[3]~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux21~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux21~0 .lut_mask = 16'h00F8; +defparam \sdram_|Mux21~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N18 +cycloneive_lcell_comb \sdram_|Mux22~0 ( +// Equation(s): +// \sdram_|Mux22~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|abus[1]~25_combout ) # ((\z80_|address_pins_|abus[13]~23_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~8_combout & +// (((\z80_|address_pins_|abus[13]~23_combout & \sdram_|Mux21~0_combout )))) + + .dataa(\sdram_|r.address[3]~8_combout ), + .datab(\z80_|address_pins_|abus[1]~25_combout ), + .datac(\z80_|address_pins_|abus[13]~23_combout ), + .datad(\sdram_|Mux21~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux22~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux22~0 .lut_mask = 16'hF888; +defparam \sdram_|Mux22~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N20 +cycloneive_lcell_comb \sdram_|r.address[3]~10 ( +// Equation(s): +// \sdram_|r.address[3]~10_combout = (((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )) # (!\sdram_|r.state [7])) # (!\sdram_|r.state [4]) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|r.address[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~10 .lut_mask = 16'h777F; +defparam \sdram_|r.address[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N14 +cycloneive_lcell_comb \sdram_|r.address[3]~11 ( +// Equation(s): +// \sdram_|r.address[3]~11_combout = (\sdram_|r.state [4] & ((!\sdram_|r.state [7]))) # (!\sdram_|r.state [4] & ((\sdram_|r.state [7]) # (!\sdram_|r.rd_pending~q ))) + + .dataa(gnd), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.address[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~11 .lut_mask = 16'h0FF3; +defparam \sdram_|r.address[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N0 +cycloneive_lcell_comb \sdram_|r.address[3]~12 ( +// Equation(s): +// \sdram_|r.address[3]~12_combout = (\sdram_|r.address[3]~11_combout ) # ((\sdram_|r.state [4] & ((\sdram_|r.state [8]))) # (!\sdram_|r.state [4] & ((!\sdram_|r.state [8]) # (!\sdram_|Equal7~2_combout )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.address[3]~11_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.address[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~12 .lut_mask = 16'hFDCF; +defparam \sdram_|r.address[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N6 +cycloneive_lcell_comb \sdram_|r.address[3]~13 ( +// Equation(s): +// \sdram_|r.address[3]~13_combout = (\sdram_|r.state [5] & (((\sdram_|r.address[3]~10_combout )) # (!\sdram_|r.state [8]))) # (!\sdram_|r.state [5] & (((\sdram_|r.address[3]~12_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.address[3]~10_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.address[3]~12_combout ), + .cin(gnd), + .combout(\sdram_|r.address[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~13 .lut_mask = 16'hDFD0; +defparam \sdram_|r.address[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N16 +cycloneive_lcell_comb \sdram_|r.address[3]~14 ( +// Equation(s): +// \sdram_|r.address[3]~14_combout = (\sdram_|r.state [4] & ((\sdram_|r.state [7]) # ((!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q )))) # (!\sdram_|r.state [4] & (\sdram_|r.state [7] & (!\sdram_|r.rd_pending~q & !\sdram_|r.wr_pending~q ))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|r.address[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~14 .lut_mask = 16'h888E; +defparam \sdram_|r.address[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N22 +cycloneive_lcell_comb \sdram_|r.address[3]~15 ( +// Equation(s): +// \sdram_|r.address[3]~15_combout = (\sdram_|r.address[3]~14_combout ) # ((\sdram_|r.state [5] & ((!\sdram_|r.state [7]) # (!\sdram_|Equal7~2_combout ))) # (!\sdram_|r.state [5] & ((\sdram_|r.state [7])))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.address[3]~14_combout ), + .datac(\sdram_|r.state [5]), + .datad(\sdram_|r.state [7]), + .cin(gnd), + .combout(\sdram_|r.address[3]~15_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~15 .lut_mask = 16'hDFFC; +defparam \sdram_|r.address[3]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N24 +cycloneive_lcell_comb \sdram_|r.address[3]~16 ( +// Equation(s): +// \sdram_|r.address[3]~16_combout = (\sdram_|r.state [8] & (((!\sdram_|r.bank[0]~8_combout )) # (!\sdram_|n~3_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|r.address[3]~15_combout )))) + + .dataa(\sdram_|n~3_combout ), + .datab(\sdram_|r.bank[0]~8_combout ), + .datac(\sdram_|r.address[3]~15_combout ), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|r.address[3]~16_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~16 .lut_mask = 16'h77F0; +defparam \sdram_|r.address[3]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y8_N26 +cycloneive_lcell_comb \sdram_|r.address[3]~17 ( +// Equation(s): +// \sdram_|r.address[3]~17_combout = (\sdram_|r.state [6] & (!\sdram_|r.address[3]~13_combout )) # (!\sdram_|r.state [6] & ((!\sdram_|r.address[3]~16_combout ))) + + .dataa(\sdram_|r.address[3]~13_combout ), + .datab(gnd), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.address[3]~16_combout ), + .cin(gnd), + .combout(\sdram_|r.address[3]~17_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[3]~17 .lut_mask = 16'h505F; +defparam \sdram_|r.address[3]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X5_Y0_N4 +dffeas \sdram_|r.address[2] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux22~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[2] .is_wysiwyg = "true"; +defparam \sdram_|r.address[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N2 +cycloneive_lcell_comb \sdram_|Mux21~1 ( +// Equation(s): +// \sdram_|Mux21~1_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|abus[2]~26_combout ) # ((\z80_|address_pins_|abus[14]~22_combout & \sdram_|Mux21~0_combout )))) # (!\sdram_|r.address[3]~8_combout & +// (((\z80_|address_pins_|abus[14]~22_combout & \sdram_|Mux21~0_combout )))) + + .dataa(\sdram_|r.address[3]~8_combout ), + .datab(\z80_|address_pins_|abus[2]~26_combout ), + .datac(\z80_|address_pins_|abus[14]~22_combout ), + .datad(\sdram_|Mux21~0_combout ), + .cin(gnd), + .combout(\sdram_|Mux21~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux21~1 .lut_mask = 16'hF888; +defparam \sdram_|Mux21~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X20_Y0_N11 +dffeas \sdram_|r.address[3] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux21~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[3] .is_wysiwyg = "true"; +defparam \sdram_|r.address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N22 +cycloneive_lcell_comb \sdram_|Mux20~4 ( +// Equation(s): +// \sdram_|Mux20~4_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & \sdram_|r.init_counter [0])) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [7]), + .datac(gnd), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Mux20~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~4 .lut_mask = 16'h2200; +defparam \sdram_|Mux20~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N26 +cycloneive_lcell_comb \sdram_|Mux20~7 ( +// Equation(s): +// \sdram_|Mux20~7_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\sdram_|r.state [6] & (!\z80_|address_pins_|DFFE_apin_latch [15])) # (!\sdram_|r.state [6] & ((!\z80_|address_pins_|DFFE_apin_latch [3]))))) + + .dataa(\sdram_|r.state [6]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\z80_|address_pins_|DFFE_apin_latch [3]), + .cin(gnd), + .combout(\sdram_|Mux20~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~7 .lut_mask = 16'h084C; +defparam \sdram_|Mux20~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N10 +cycloneive_lcell_comb \sdram_|Mux23~7 ( +// Equation(s): +// \sdram_|Mux23~7_combout = (\sdram_|r.state [4] & (\sdram_|process_0~2_combout & ((\sdram_|r.state [6]) # (\sdram_|Equal7~2_combout )))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux23~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux23~7 .lut_mask = 16'hE000; +defparam \sdram_|Mux23~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N10 +cycloneive_lcell_comb \sdram_|Mux20~8 ( +// Equation(s): +// \sdram_|Mux20~8_combout = (\sdram_|r.state [6] & (\sdram_|r.state [4] $ (((\sdram_|r.state [8]))))) # (!\sdram_|r.state [6] & (!\sdram_|r.state [4] & (\sdram_|n~3_combout & !\sdram_|r.state [8]))) + + .dataa(\sdram_|r.state [4]), + .datab(\sdram_|n~3_combout ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux20~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~8 .lut_mask = 16'h50A4; +defparam \sdram_|Mux20~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N18 +cycloneive_lcell_comb \sdram_|Mux20~10 ( +// Equation(s): +// \sdram_|Mux20~10_combout = (\sdram_|r.state [8] & (\sdram_|Mux20~7_combout & (\sdram_|Mux23~7_combout & !\sdram_|Mux20~8_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux20~8_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux20~7_combout ), + .datac(\sdram_|Mux23~7_combout ), + .datad(\sdram_|Mux20~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~10 .lut_mask = 16'h5580; +defparam \sdram_|Mux20~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N0 +cycloneive_lcell_comb \sdram_|Mux20~9 ( +// Equation(s): +// \sdram_|Mux20~9_combout = (\sdram_|r.state [8] & (!\sdram_|Mux20~7_combout & (\sdram_|Mux23~7_combout ))) # (!\sdram_|r.state [8] & (((\sdram_|Mux20~8_combout )))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux20~7_combout ), + .datac(\sdram_|Mux23~7_combout ), + .datad(\sdram_|Mux20~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~9 .lut_mask = 16'h7520; +defparam \sdram_|Mux20~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N24 +cycloneive_lcell_comb \sdram_|Mux20~11 ( +// Equation(s): +// \sdram_|Mux20~11_combout = (\sdram_|Mux20~10_combout & (((\z80_|address_pins_|abus[3]~27_combout & \sdram_|Mux20~9_combout )))) # (!\sdram_|Mux20~10_combout & ((\sdram_|r.address[4]~_Duplicate_1_q ) # ((\sdram_|Mux20~9_combout )))) + + .dataa(\sdram_|r.address[4]~_Duplicate_1_q ), + .datab(\z80_|address_pins_|abus[3]~27_combout ), + .datac(\sdram_|Mux20~10_combout ), + .datad(\sdram_|Mux20~9_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~11 .lut_mask = 16'hCF0A; +defparam \sdram_|Mux20~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y11_N5 +dffeas \sdram_|r.address[4]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[4]~2_combout ), + .asdata(\sdram_|Mux20~11_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\sdram_|r.state [7]), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[4]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[4]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[4]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N2 +cycloneive_lcell_comb \sdram_|Mux20~12 ( +// Equation(s): +// \sdram_|Mux20~12_combout = (\sdram_|process_0~2_combout & (((\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )))) # (!\sdram_|process_0~2_combout & (\sdram_|r.address[4]~_Duplicate_1_q )) + + .dataa(\sdram_|r.address[4]~_Duplicate_1_q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~12 .lut_mask = 16'hCFAA; +defparam \sdram_|Mux20~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N4 +cycloneive_lcell_comb \sdram_|Mux20~5 ( +// Equation(s): +// \sdram_|Mux20~5_combout = (\sdram_|r.state [4] & (((\sdram_|Mux20~12_combout )))) # (!\sdram_|r.state [4] & (\sdram_|Mux20~4_combout & (\sdram_|Equal2~2_combout ))) + + .dataa(\sdram_|Mux20~4_combout ), + .datab(\sdram_|Equal2~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|Mux20~12_combout ), + .cin(gnd), + .combout(\sdram_|Mux20~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~5 .lut_mask = 16'hF808; +defparam \sdram_|Mux20~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N16 +cycloneive_lcell_comb \sdram_|Mux20~6 ( +// Equation(s): +// \sdram_|Mux20~6_combout = (\sdram_|Mux24~2_combout & ((\sdram_|r.state [4] & ((\sdram_|r.address[4]~_Duplicate_1_q ))) # (!\sdram_|r.state [4] & (\z80_|address_pins_|abus[3]~27_combout )))) # (!\sdram_|Mux24~2_combout & +// (((\sdram_|r.address[4]~_Duplicate_1_q )))) + + .dataa(\sdram_|Mux24~2_combout ), + .datab(\z80_|address_pins_|abus[3]~27_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.address[4]~_Duplicate_1_q ), + .cin(gnd), + .combout(\sdram_|Mux20~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux20~6 .lut_mask = 16'hFD08; +defparam \sdram_|Mux20~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N4 +cycloneive_lcell_comb \sdram_|r.address[4]~2 ( +// Equation(s): +// \sdram_|r.address[4]~2_combout = (\sdram_|r.state [8] & ((\sdram_|Mux20~6_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux20~5_combout )) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux20~5_combout ), + .datac(gnd), + .datad(\sdram_|Mux20~6_combout ), + .cin(gnd), + .combout(\sdram_|r.address[4]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[4]~2 .lut_mask = 16'hEE44; +defparam \sdram_|r.address[4]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N8 +cycloneive_lcell_comb \sdram_|r.address[4]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[4]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux20~11_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[4]~2_combout )) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.address[4]~2_combout ), + .datad(\sdram_|Mux20~11_combout ), + .cin(gnd), + .combout(\sdram_|r.address[4]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[4]~SLOAD_MUX .lut_mask = 16'hFC30; +defparam \sdram_|r.address[4]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X25_Y0_N18 +dffeas \sdram_|r.address[4] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[4]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[4] .is_wysiwyg = "true"; +defparam \sdram_|r.address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N26 +cycloneive_lcell_comb \sdram_|Mux19~1 ( +// Equation(s): +// \sdram_|Mux19~1_combout = (\sdram_|r.init_counter [1] & (!\sdram_|r.init_counter [7] & (\sdram_|Equal2~2_combout & \sdram_|r.init_counter [0]))) + + .dataa(\sdram_|r.init_counter [1]), + .datab(\sdram_|r.init_counter [7]), + .datac(\sdram_|Equal2~2_combout ), + .datad(\sdram_|r.init_counter [0]), + .cin(gnd), + .combout(\sdram_|Mux19~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~1 .lut_mask = 16'h2000; +defparam \sdram_|Mux19~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N12 +cycloneive_lcell_comb \sdram_|Mux19~4 ( +// Equation(s): +// \sdram_|Mux19~4_combout = (\sdram_|r.state [8] & (\sdram_|Mux23~7_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.bank[0]~4_combout ))) + + .dataa(\sdram_|r.state [8]), + .datab(gnd), + .datac(\sdram_|Mux23~7_combout ), + .datad(\sdram_|r.bank[0]~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux19~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~4 .lut_mask = 16'hF5A0; +defparam \sdram_|Mux19~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N22 +cycloneive_lcell_comb \sdram_|Mux19~5 ( +// Equation(s): +// \sdram_|Mux19~5_combout = (\sdram_|r.state [6] & (!\sdram_|r.state [8] & (\sdram_|r.state [4]))) # (!\sdram_|r.state [6] & (\sdram_|Mux19~4_combout & ((\sdram_|r.state [8]) # (!\sdram_|r.state [4])))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux19~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux19~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~5 .lut_mask = 16'h4B40; +defparam \sdram_|Mux19~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N20 +cycloneive_lcell_comb \sdram_|Mux19~6 ( +// Equation(s): +// \sdram_|Mux19~6_combout = (\sdram_|r.state [8] & (\sdram_|r.state [4] & (\sdram_|r.state [6] & \sdram_|Mux19~4_combout ))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|r.state [4]), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|Mux19~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux19~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~6 .lut_mask = 16'h8000; +defparam \sdram_|Mux19~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N14 +cycloneive_lcell_comb \sdram_|Mux19~7 ( +// Equation(s): +// \sdram_|Mux19~7_combout = (\sdram_|Mux19~5_combout & ((\sdram_|Mux19~6_combout & ((\sdram_|r.address[5]~_Duplicate_1_q ))) # (!\sdram_|Mux19~6_combout & (\z80_|address_pins_|abus[4]~28_combout )))) # (!\sdram_|Mux19~5_combout & +// (((\sdram_|r.address[5]~_Duplicate_1_q & !\sdram_|Mux19~6_combout )))) + + .dataa(\z80_|address_pins_|abus[4]~28_combout ), + .datab(\sdram_|r.address[5]~_Duplicate_1_q ), + .datac(\sdram_|Mux19~5_combout ), + .datad(\sdram_|Mux19~6_combout ), + .cin(gnd), + .combout(\sdram_|Mux19~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~7 .lut_mask = 16'hC0AC; +defparam \sdram_|Mux19~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y11_N31 +dffeas \sdram_|r.address[5]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[5]~3_combout ), + .asdata(\sdram_|Mux19~7_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\sdram_|r.state [7]), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[5]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[5]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[5]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y7_N20 +cycloneive_lcell_comb \sdram_|Mux19~2 ( +// Equation(s): +// \sdram_|Mux19~2_combout = (\sdram_|r.state [4] & (((!\sdram_|process_0~2_combout & \sdram_|r.address[5]~_Duplicate_1_q )))) # (!\sdram_|r.state [4] & (\sdram_|Mux19~1_combout )) + + .dataa(\sdram_|Mux19~1_combout ), + .datab(\sdram_|process_0~2_combout ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.address[5]~_Duplicate_1_q ), + .cin(gnd), + .combout(\sdram_|Mux19~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~2 .lut_mask = 16'h3A0A; +defparam \sdram_|Mux19~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N6 +cycloneive_lcell_comb \sdram_|Mux19~3 ( +// Equation(s): +// \sdram_|Mux19~3_combout = (\sdram_|Mux24~2_combout & ((\sdram_|r.state [4] & ((\sdram_|r.address[5]~_Duplicate_1_q ))) # (!\sdram_|r.state [4] & (\z80_|address_pins_|abus[4]~28_combout )))) # (!\sdram_|Mux24~2_combout & +// (((\sdram_|r.address[5]~_Duplicate_1_q )))) + + .dataa(\sdram_|Mux24~2_combout ), + .datab(\sdram_|r.state [4]), + .datac(\z80_|address_pins_|abus[4]~28_combout ), + .datad(\sdram_|r.address[5]~_Duplicate_1_q ), + .cin(gnd), + .combout(\sdram_|Mux19~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux19~3 .lut_mask = 16'hFD20; +defparam \sdram_|Mux19~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N30 +cycloneive_lcell_comb \sdram_|r.address[5]~3 ( +// Equation(s): +// \sdram_|r.address[5]~3_combout = (\sdram_|r.state [8] & ((\sdram_|Mux19~3_combout ))) # (!\sdram_|r.state [8] & (\sdram_|Mux19~2_combout )) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux19~2_combout ), + .datac(gnd), + .datad(\sdram_|Mux19~3_combout ), + .cin(gnd), + .combout(\sdram_|r.address[5]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[5]~3 .lut_mask = 16'hEE44; +defparam \sdram_|r.address[5]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y11_N26 +cycloneive_lcell_comb \sdram_|r.address[5]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[5]~SLOAD_MUX_combout = (\sdram_|r.state [7] & ((\sdram_|Mux19~7_combout ))) # (!\sdram_|r.state [7] & (\sdram_|r.address[5]~3_combout )) + + .dataa(\sdram_|r.address[5]~3_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux19~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[5]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[5]~SLOAD_MUX .lut_mask = 16'hE2E2; +defparam \sdram_|r.address[5]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X18_Y0_N25 +dffeas \sdram_|r.address[5] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[5]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux19~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[5] .is_wysiwyg = "true"; +defparam \sdram_|r.address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N6 +cycloneive_lcell_comb \sdram_|Mux18~0 ( +// Equation(s): +// \sdram_|Mux18~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [5]), + .datad(\sdram_|r.address[3]~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux18~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux18~0 .lut_mask = 16'hF500; +defparam \sdram_|Mux18~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X20_Y0_N4 +dffeas \sdram_|r.address[6] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux18~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[6] .is_wysiwyg = "true"; +defparam \sdram_|r.address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N4 +cycloneive_lcell_comb \sdram_|Mux17~0 ( +// Equation(s): +// \sdram_|Mux17~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [6]), + .datad(\sdram_|r.address[3]~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux17~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux17~0 .lut_mask = 16'hF500; +defparam \sdram_|Mux17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X14_Y0_N4 +dffeas \sdram_|r.address[7] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux17~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[7] .is_wysiwyg = "true"; +defparam \sdram_|r.address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N22 +cycloneive_lcell_comb \sdram_|Mux16~0 ( +// Equation(s): +// \sdram_|Mux16~0_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(\z80_|address_pins_|DFFE_apin_latch [7]), + .datad(\sdram_|r.address[3]~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux16~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux16~0 .lut_mask = 16'hF500; +defparam \sdram_|Mux16~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y5_N25 +dffeas \sdram_|r.address[8] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux16~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[8] .is_wysiwyg = "true"; +defparam \sdram_|r.address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N30 +cycloneive_lcell_comb \sdram_|Mux15~2 ( +// Equation(s): +// \sdram_|Mux15~2_combout = (\sdram_|r.address[3]~8_combout & ((\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [8]), + .datac(gnd), + .datad(\sdram_|r.address[3]~8_combout ), + .cin(gnd), + .combout(\sdram_|Mux15~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux15~2 .lut_mask = 16'hDD00; +defparam \sdram_|Mux15~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y4_N25 +dffeas \sdram_|r.address[9] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|Mux15~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|r.address[3]~17_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[9] .is_wysiwyg = "true"; +defparam \sdram_|r.address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N22 +cycloneive_lcell_comb \sdram_|Mux14~0 ( +// Equation(s): +// \sdram_|Mux14~0_combout = (\sdram_|r.rf_pending~q ) # ((\sdram_|n~4_combout & ((\sdram_|r.state [6]) # (!\sdram_|process_0~3_combout )))) + + .dataa(\sdram_|process_0~3_combout ), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|n~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux14~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~0 .lut_mask = 16'hFDCC; +defparam \sdram_|Mux14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N28 +cycloneive_lcell_comb \sdram_|Mux14~1 ( +// Equation(s): +// \sdram_|Mux14~1_combout = (\sdram_|r.state [4] & (((\sdram_|r.address[10]~_Duplicate_1_q & !\sdram_|process_0~2_combout )))) # (!\sdram_|r.state [4] & (\sdram_|Equal2~3_combout )) + + .dataa(\sdram_|Equal2~3_combout ), + .datab(\sdram_|r.address[10]~_Duplicate_1_q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux14~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~1 .lut_mask = 16'h0ACA; +defparam \sdram_|Mux14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N10 +cycloneive_lcell_comb \sdram_|r.address[10]~4 ( +// Equation(s): +// \sdram_|r.address[10]~4_combout = (\sdram_|r.state [8] & (\sdram_|Mux14~0_combout )) # (!\sdram_|r.state [8] & ((\sdram_|Mux14~1_combout ))) + + .dataa(\sdram_|Mux14~0_combout ), + .datab(\sdram_|r.state [8]), + .datac(gnd), + .datad(\sdram_|Mux14~1_combout ), + .cin(gnd), + .combout(\sdram_|r.address[10]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[10]~4 .lut_mask = 16'hBB88; +defparam \sdram_|r.address[10]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X20_Y11_N11 +dffeas \sdram_|r.address[10]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[10]~4_combout ), + .asdata(\sdram_|Mux14~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\sdram_|r.state [7]), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[10]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[10]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[10]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N16 +cycloneive_lcell_comb \sdram_|n~4 ( +// Equation(s): +// \sdram_|n~4_combout = (\sdram_|r.rd_pending~q & (!\sdram_|Equal7~2_combout )) # (!\sdram_|r.rd_pending~q & (((\sdram_|r.address[10]~_Duplicate_1_q ) # (\sdram_|r.wr_pending~q )))) + + .dataa(\sdram_|Equal7~2_combout ), + .datab(\sdram_|r.address[10]~_Duplicate_1_q ), + .datac(\sdram_|r.rd_pending~q ), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|n~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|n~4 .lut_mask = 16'h5F5C; +defparam \sdram_|n~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N30 +cycloneive_lcell_comb \sdram_|Mux14~2 ( +// Equation(s): +// \sdram_|Mux14~2_combout = (!\sdram_|r.state [6] & ((\sdram_|r.rf_pending~q ) # ((!\sdram_|process_0~3_combout & \sdram_|n~4_combout )))) + + .dataa(\sdram_|process_0~3_combout ), + .datab(\sdram_|r.rf_pending~q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|n~4_combout ), + .cin(gnd), + .combout(\sdram_|Mux14~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~2 .lut_mask = 16'h0D0C; +defparam \sdram_|Mux14~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N8 +cycloneive_lcell_comb \sdram_|Mux14~3 ( +// Equation(s): +// \sdram_|Mux14~3_combout = (\sdram_|Mux14~2_combout ) # ((\sdram_|r.address[10]~_Duplicate_1_q & (\sdram_|Mux23~0_combout & !\sdram_|process_0~2_combout ))) + + .dataa(\sdram_|Mux14~2_combout ), + .datab(\sdram_|r.address[10]~_Duplicate_1_q ), + .datac(\sdram_|Mux23~0_combout ), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux14~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux14~3 .lut_mask = 16'hAAEA; +defparam \sdram_|Mux14~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y11_N26 +cycloneive_lcell_comb \sdram_|r.address[10]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[10]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux14~3_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[10]~4_combout ))) + + .dataa(gnd), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|Mux14~3_combout ), + .datad(\sdram_|r.address[10]~4_combout ), + .cin(gnd), + .combout(\sdram_|r.address[10]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[10]~SLOAD_MUX .lut_mask = 16'hF3C0; +defparam \sdram_|r.address[10]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y8_N25 +dffeas \sdram_|r.address[10] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[10]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[10] .is_wysiwyg = "true"; +defparam \sdram_|r.address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N28 +cycloneive_lcell_comb \sdram_|r.address[11]~18 ( +// Equation(s): +// \sdram_|r.address[11]~18_combout = (!\sdram_|r.rd_pending~q & (\sdram_|r.state [4] & !\sdram_|r.wr_pending~q )) + + .dataa(gnd), + .datab(\sdram_|r.rd_pending~q ), + .datac(\sdram_|r.state [4]), + .datad(\sdram_|r.wr_pending~q ), + .cin(gnd), + .combout(\sdram_|r.address[11]~18_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~18 .lut_mask = 16'h0030; +defparam \sdram_|r.address[11]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N26 +cycloneive_lcell_comb \sdram_|r.address[11]~5 ( +// Equation(s): +// \sdram_|r.address[11]~5_combout = (\sdram_|r.address[11]~_Duplicate_2_q & ((\sdram_|r.state [8] & (!\sdram_|Mux24~2_combout )) # (!\sdram_|r.state [8] & ((\sdram_|r.address[11]~18_combout ))))) + + .dataa(\sdram_|r.state [8]), + .datab(\sdram_|Mux24~2_combout ), + .datac(\sdram_|r.address[11]~_Duplicate_2_q ), + .datad(\sdram_|r.address[11]~18_combout ), + .cin(gnd), + .combout(\sdram_|r.address[11]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~5 .lut_mask = 16'h7020; +defparam \sdram_|r.address[11]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N4 +cycloneive_lcell_comb \sdram_|r.address[11]~_Duplicate_2feeder ( +// Equation(s): +// \sdram_|r.address[11]~_Duplicate_2feeder_combout = \sdram_|r.address[11]~5_combout + + .dataa(\sdram_|r.address[11]~5_combout ), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[11]~_Duplicate_2feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~_Duplicate_2feeder .lut_mask = 16'hAAAA; +defparam \sdram_|r.address[11]~_Duplicate_2feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y11_N5 +dffeas \sdram_|r.address[11]~_Duplicate_2 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[11]~_Duplicate_2feeder_combout ), + .asdata(\sdram_|Mux13~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\sdram_|r.state [7]), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[11]~_Duplicate_2_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[11]~_Duplicate_2 .is_wysiwyg = "true"; +defparam \sdram_|r.address[11]~_Duplicate_2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N8 +cycloneive_lcell_comb \sdram_|Mux13~10 ( +// Equation(s): +// \sdram_|Mux13~10_combout = (\sdram_|r.address[11]~_Duplicate_2_q & ((\sdram_|r.state [8]) # (!\sdram_|r.state [6]))) + + .dataa(gnd), + .datab(\sdram_|r.address[11]~_Duplicate_2_q ), + .datac(\sdram_|r.state [6]), + .datad(\sdram_|r.state [8]), + .cin(gnd), + .combout(\sdram_|Mux13~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~10 .lut_mask = 16'hCC0C; +defparam \sdram_|Mux13~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N22 +cycloneive_lcell_comb \sdram_|Mux13~6 ( +// Equation(s): +// \sdram_|Mux13~6_combout = (\sdram_|Mux13~10_combout & (((!\sdram_|r.state [6] & !\sdram_|Equal7~2_combout )) # (!\sdram_|process_0~2_combout ))) + + .dataa(\sdram_|r.state [6]), + .datab(\sdram_|Equal7~2_combout ), + .datac(\sdram_|Mux13~10_combout ), + .datad(\sdram_|process_0~2_combout ), + .cin(gnd), + .combout(\sdram_|Mux13~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|Mux13~6 .lut_mask = 16'h10F0; +defparam \sdram_|Mux13~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N12 +cycloneive_lcell_comb \sdram_|r.address[11]~SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[11]~SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux13~6_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[11]~5_combout ))) + + .dataa(\sdram_|Mux13~6_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.address[11]~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[11]~SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~SLOAD_MUX .lut_mask = 16'hB8B8; +defparam \sdram_|r.address[11]~SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y7_N4 +dffeas \sdram_|r.address[11] ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[11]~SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[11] .is_wysiwyg = "true"; +defparam \sdram_|r.address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y11_N6 +cycloneive_lcell_comb \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX ( +// Equation(s): +// \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout = (\sdram_|r.state [7] & (\sdram_|Mux13~6_combout )) # (!\sdram_|r.state [7] & ((\sdram_|r.address[11]~5_combout ))) + + .dataa(\sdram_|Mux13~6_combout ), + .datab(\sdram_|r.state [7]), + .datac(\sdram_|r.address[11]~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX .lut_mask = 16'hB8B8; +defparam \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X0_Y6_N18 +dffeas \sdram_|r.address[11]~_Duplicate_1 ( + .clk(\sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_|r.address[11]~_Duplicate_1SLOAD_MUX_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_|Mux13~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_|r.address[11]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_|r.address[11]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \sdram_|r.address[11]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + // Location: IOIBUF_X0_Y16_N22 cycloneive_io_ibuf \SW[0]~input ( .i(SW[0]), @@ -59899,4 +65745,164 @@ defparam \I2C_SCLK~input .bus_hold = "false"; defparam \I2C_SCLK~input .simulate_z_as = "z"; // synopsys translate_on +// Location: IOIBUF_X0_Y23_N15 +cycloneive_io_ibuf \DRAM_DQ[0]~input ( + .i(DRAM_DQ[0]), + .ibar(gnd), + .o(\DRAM_DQ[0]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[0]~input .bus_hold = "false"; +defparam \DRAM_DQ[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y23_N22 +cycloneive_io_ibuf \DRAM_DQ[1]~input ( + .i(DRAM_DQ[1]), + .ibar(gnd), + .o(\DRAM_DQ[1]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[1]~input .bus_hold = "false"; +defparam \DRAM_DQ[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N8 +cycloneive_io_ibuf \DRAM_DQ[2]~input ( + .i(DRAM_DQ[2]), + .ibar(gnd), + .o(\DRAM_DQ[2]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[2]~input .bus_hold = "false"; +defparam \DRAM_DQ[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y7_N8 +cycloneive_io_ibuf \DRAM_DQ[3]~input ( + .i(DRAM_DQ[3]), + .ibar(gnd), + .o(\DRAM_DQ[3]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[3]~input .bus_hold = "false"; +defparam \DRAM_DQ[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y12_N1 +cycloneive_io_ibuf \DRAM_DQ[4]~input ( + .i(DRAM_DQ[4]), + .ibar(gnd), + .o(\DRAM_DQ[4]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[4]~input .bus_hold = "false"; +defparam \DRAM_DQ[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y15_N1 +cycloneive_io_ibuf \DRAM_DQ[5]~input ( + .i(DRAM_DQ[5]), + .ibar(gnd), + .o(\DRAM_DQ[5]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[5]~input .bus_hold = "false"; +defparam \DRAM_DQ[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y15_N8 +cycloneive_io_ibuf \DRAM_DQ[6]~input ( + .i(DRAM_DQ[6]), + .ibar(gnd), + .o(\DRAM_DQ[6]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[6]~input .bus_hold = "false"; +defparam \DRAM_DQ[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y0_N15 +cycloneive_io_ibuf \DRAM_DQ[7]~input ( + .i(DRAM_DQ[7]), + .ibar(gnd), + .o(\DRAM_DQ[7]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[7]~input .bus_hold = "false"; +defparam \DRAM_DQ[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y0_N15 +cycloneive_io_ibuf \DRAM_DQ[8]~input ( + .i(DRAM_DQ[8]), + .ibar(gnd), + .o(\DRAM_DQ[8]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[8]~input .bus_hold = "false"; +defparam \DRAM_DQ[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y0_N1 +cycloneive_io_ibuf \DRAM_DQ[9]~input ( + .i(DRAM_DQ[9]), + .ibar(gnd), + .o(\DRAM_DQ[9]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[9]~input .bus_hold = "false"; +defparam \DRAM_DQ[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X1_Y0_N1 +cycloneive_io_ibuf \DRAM_DQ[10]~input ( + .i(DRAM_DQ[10]), + .ibar(gnd), + .o(\DRAM_DQ[10]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[10]~input .bus_hold = "false"; +defparam \DRAM_DQ[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X1_Y0_N8 +cycloneive_io_ibuf \DRAM_DQ[11]~input ( + .i(DRAM_DQ[11]), + .ibar(gnd), + .o(\DRAM_DQ[11]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[11]~input .bus_hold = "false"; +defparam \DRAM_DQ[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y0_N22 +cycloneive_io_ibuf \DRAM_DQ[12]~input ( + .i(DRAM_DQ[12]), + .ibar(gnd), + .o(\DRAM_DQ[12]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[12]~input .bus_hold = "false"; +defparam \DRAM_DQ[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X1_Y0_N15 +cycloneive_io_ibuf \DRAM_DQ[13]~input ( + .i(DRAM_DQ[13]), + .ibar(gnd), + .o(\DRAM_DQ[13]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[13]~input .bus_hold = "false"; +defparam \DRAM_DQ[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X1_Y0_N22 +cycloneive_io_ibuf \DRAM_DQ[14]~input ( + .i(DRAM_DQ[14]), + .ibar(gnd), + .o(\DRAM_DQ[14]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[14]~input .bus_hold = "false"; +defparam \DRAM_DQ[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y12_N8 +cycloneive_io_ibuf \DRAM_DQ[15]~input ( + .i(DRAM_DQ[15]), + .ibar(gnd), + .o(\DRAM_DQ[15]~input_o )); +// synopsys translate_off +defparam \DRAM_DQ[15]~input .bus_hold = "false"; +defparam \DRAM_DQ[15]~input .simulate_z_as = "z"; +// synopsys translate_on + endmodule diff --git a/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo b/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo index ef4ecfb..bf15cbf 100644 --- a/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo +++ b/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "04/01/2022 18:55:52") + (DATE "04/02/2022 14:51:22") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,8 +41,8 @@ (INSTANCE GPIO_1\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1174:1174:1174) (1317:1317:1317)) - (PORT oe (934:934:934) (1057:1057:1057)) + (PORT i (851:851:851) (986:986:986)) + (PORT oe (952:952:952) (1082:1082:1082)) (IOPATH i o (1586:1586:1586) (1541:1541:1541)) (IOPATH oe o (1579:1579:1579) (1514:1514:1514)) ) @@ -53,8 +53,8 @@ (INSTANCE GPIO_1\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1180:1180:1180) (1340:1340:1340)) - (PORT oe (1037:1037:1037) (1174:1174:1174)) + (PORT i (1146:1146:1146) (1288:1288:1288)) + (PORT oe (925:925:925) (1058:1058:1058)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -65,8 +65,8 @@ (INSTANCE GPIO_1\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1119:1119:1119) (1291:1291:1291)) - (PORT oe (1037:1037:1037) (1174:1174:1174)) + (PORT i (1254:1254:1254) (1396:1396:1396)) + (PORT oe (925:925:925) (1058:1058:1058)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -77,8 +77,8 @@ (INSTANCE GPIO_1\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1254:1254:1254) (1427:1427:1427)) - (PORT oe (1198:1198:1198) (1376:1376:1376)) + (PORT i (1003:1003:1003) (1126:1126:1126)) + (PORT oe (1151:1151:1151) (1314:1314:1314)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -89,8 +89,8 @@ (INSTANCE GPIO_1\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (1312:1312:1312) (1495:1495:1495)) - (PORT oe (1198:1198:1198) (1376:1376:1376)) + (PORT i (1052:1052:1052) (1196:1196:1196)) + (PORT oe (1151:1151:1151) (1314:1314:1314)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -101,8 +101,8 @@ (INSTANCE GPIO_1\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1099:1099:1099) (1242:1242:1242)) - (PORT oe (1064:1064:1064) (1222:1222:1222)) + (PORT i (867:867:867) (1013:1013:1013)) + (PORT oe (1288:1288:1288) (1473:1473:1473)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -113,8 +113,8 @@ (INSTANCE GPIO_1\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (918:918:918) (1050:1050:1050)) - (PORT oe (1064:1064:1064) (1222:1222:1222)) + (PORT i (903:903:903) (1032:1032:1032)) + (PORT oe (1288:1288:1288) (1473:1473:1473)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -125,8 +125,8 @@ (INSTANCE GPIO_1\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (1143:1143:1143) (1334:1334:1334)) - (PORT oe (1064:1064:1064) (1222:1222:1222)) + (PORT i (915:915:915) (1053:1053:1053)) + (PORT oe (1288:1288:1288) (1473:1473:1473)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -137,8 +137,8 @@ (INSTANCE GPIO_1\[8\]\~output) (DELAY (ABSOLUTE - (PORT i (543:543:543) (634:634:634)) - (PORT oe (1215:1215:1215) (1393:1393:1393)) + (PORT i (806:806:806) (927:927:927)) + (PORT oe (1431:1431:1431) (1637:1637:1637)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -149,8 +149,8 @@ (INSTANCE GPIO_1\[9\]\~output) (DELAY (ABSOLUTE - (PORT i (970:970:970) (1109:1109:1109)) - (PORT oe (1215:1215:1215) (1393:1393:1393)) + (PORT i (888:888:888) (1012:1012:1012)) + (PORT oe (1431:1431:1431) (1637:1637:1637)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -161,8 +161,8 @@ (INSTANCE GPIO_1\[10\]\~output) (DELAY (ABSOLUTE - (PORT i (1061:1061:1061) (1219:1219:1219)) - (PORT oe (1375:1375:1375) (1593:1593:1593)) + (PORT i (969:969:969) (1122:1122:1122)) + (PORT oe (1283:1283:1283) (1469:1469:1469)) (IOPATH i o (3177:3177:3177) (2883:2883:2883)) (IOPATH oe o (3164:3164:3164) (2848:2848:2848)) ) @@ -173,8 +173,8 @@ (INSTANCE GPIO_1\[11\]\~output) (DELAY (ABSOLUTE - (PORT i (775:775:775) (876:876:876)) - (PORT oe (1215:1215:1215) (1393:1393:1393)) + (PORT i (845:845:845) (958:958:958)) + (PORT oe (1431:1431:1431) (1637:1637:1637)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -185,8 +185,8 @@ (INSTANCE GPIO_1\[12\]\~output) (DELAY (ABSOLUTE - (PORT i (1194:1194:1194) (1336:1336:1336)) - (PORT oe (933:933:933) (1055:1055:1055)) + (PORT i (907:907:907) (1029:1029:1029)) + (PORT oe (934:934:934) (1068:1068:1068)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -197,8 +197,8 @@ (INSTANCE GPIO_1\[13\]\~output) (DELAY (ABSOLUTE - (PORT i (1275:1275:1275) (1459:1459:1459)) - (PORT oe (1375:1375:1375) (1593:1593:1593)) + (PORT i (913:913:913) (1049:1049:1049)) + (PORT oe (1283:1283:1283) (1469:1469:1469)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -209,8 +209,8 @@ (INSTANCE GPIO_1\[14\]\~output) (DELAY (ABSOLUTE - (PORT i (934:934:934) (1057:1057:1057)) - (PORT oe (1212:1212:1212) (1388:1388:1388)) + (PORT i (834:834:834) (953:953:953)) + (PORT oe (1202:1202:1202) (1384:1384:1384)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -221,8 +221,8 @@ (INSTANCE GPIO_1\[15\]\~output) (DELAY (ABSOLUTE - (PORT i (987:987:987) (1146:1146:1146)) - (PORT oe (1050:1050:1050) (1190:1190:1190)) + (PORT i (996:996:996) (1130:1130:1130)) + (PORT oe (1037:1037:1037) (1186:1186:1186)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -233,8 +233,8 @@ (INSTANCE GPIO_1\[16\]\~output) (DELAY (ABSOLUTE - (PORT i (673:673:673) (772:772:772)) - (PORT oe (1396:1396:1396) (1566:1566:1566)) + (PORT i (665:665:665) (771:771:771)) + (PORT oe (779:779:779) (899:899:899)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -245,8 +245,8 @@ (INSTANCE GPIO_1\[17\]\~output) (DELAY (ABSOLUTE - (PORT i (694:694:694) (791:791:791)) - (PORT oe (1396:1396:1396) (1567:1567:1567)) + (PORT i (699:699:699) (800:800:800)) + (PORT oe (952:952:952) (1085:1085:1085)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -257,8 +257,8 @@ (INSTANCE GPIO_1\[18\]\~output) (DELAY (ABSOLUTE - (PORT i (620:620:620) (700:700:700)) - (PORT oe (1211:1211:1211) (1355:1355:1355)) + (PORT i (821:821:821) (941:941:941)) + (PORT oe (924:924:924) (1056:1056:1056)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -269,8 +269,8 @@ (INSTANCE GPIO_1\[19\]\~output) (DELAY (ABSOLUTE - (PORT i (663:663:663) (769:769:769)) - (PORT oe (1396:1396:1396) (1566:1566:1566)) + (PORT i (780:780:780) (878:878:878)) + (PORT oe (779:779:779) (899:899:899)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -281,8 +281,8 @@ (INSTANCE GPIO_1\[20\]\~output) (DELAY (ABSOLUTE - (PORT i (826:826:826) (944:944:944)) - (PORT oe (1184:1184:1184) (1331:1331:1331)) + (PORT i (910:910:910) (1026:1026:1026)) + (PORT oe (793:793:793) (914:914:914)) (IOPATH i o (1586:1586:1586) (1541:1541:1541)) (IOPATH oe o (1579:1579:1579) (1514:1514:1514)) ) @@ -293,8 +293,8 @@ (INSTANCE GPIO_1\[21\]\~output) (DELAY (ABSOLUTE - (PORT i (736:736:736) (825:825:825)) - (PORT oe (1210:1210:1210) (1354:1354:1354)) + (PORT i (817:817:817) (938:938:938)) + (PORT oe (955:955:955) (1093:1093:1093)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -305,8 +305,8 @@ (INSTANCE GPIO_1\[22\]\~output) (DELAY (ABSOLUTE - (PORT i (678:678:678) (773:773:773)) - (PORT oe (1148:1148:1148) (1280:1280:1280)) + (PORT i (943:943:943) (1090:1090:1090)) + (PORT oe (908:908:908) (1044:1044:1044)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -317,8 +317,8 @@ (INSTANCE GPIO_1\[23\]\~output) (DELAY (ABSOLUTE - (PORT i (622:622:622) (691:691:691)) - (PORT oe (1364:1364:1364) (1526:1526:1526)) + (PORT i (776:776:776) (890:890:890)) + (PORT oe (782:782:782) (897:897:897)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -329,8 +329,8 @@ (INSTANCE GPIO_1\[27\]\~output) (DELAY (ABSOLUTE - (PORT i (846:846:846) (761:761:761)) - (PORT oe (926:926:926) (1046:1046:1046)) + (PORT i (887:887:887) (799:799:799)) + (PORT oe (839:839:839) (969:969:969)) (IOPATH i o (1541:1541:1541) (1586:1586:1586)) (IOPATH oe o (1579:1579:1579) (1514:1514:1514)) ) @@ -341,8 +341,8 @@ (INSTANCE GPIO_1\[28\]\~output) (DELAY (ABSOLUTE - (PORT i (1098:1098:1098) (954:954:954)) - (PORT oe (1050:1050:1050) (1190:1190:1190)) + (PORT i (773:773:773) (700:700:700)) + (PORT oe (1037:1037:1037) (1186:1186:1186)) (IOPATH i o (1588:1588:1588) (1643:1643:1643)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -353,9 +353,9 @@ (INSTANCE GPIO_1\[29\]\~output) (DELAY (ABSOLUTE - (PORT i (934:934:934) (837:837:837)) - (PORT oe (757:757:757) (859:859:859)) - (IOPATH i o (1600:1600:1600) (1666:1666:1666)) + (PORT i (646:646:646) (707:707:707)) + (PORT oe (1025:1025:1025) (1173:1173:1173)) + (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) ) @@ -365,8 +365,8 @@ (INSTANCE GPIO_1\[30\]\~output) (DELAY (ABSOLUTE - (PORT i (571:571:571) (628:628:628)) - (PORT oe (731:731:731) (836:836:836)) + (PORT i (637:637:637) (702:702:702)) + (PORT oe (544:544:544) (628:628:628)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -377,7 +377,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1022:1022:1022) (889:889:889)) + (PORT i (1023:1023:1023) (889:889:889)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -387,7 +387,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (641:641:641) (574:574:574)) + (PORT i (642:642:642) (575:575:575)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -397,7 +397,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (741:741:741) (831:831:831)) + (PORT i (860:860:860) (990:990:990)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -452,7 +452,7 @@ (INSTANCE VGA_R\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (638:638:638) (733:733:733)) + (PORT i (623:623:623) (717:717:717)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -462,7 +462,7 @@ (INSTANCE VGA_R\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (601:601:601) (687:687:687)) + (PORT i (632:632:632) (726:726:726)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -472,7 +472,7 @@ (INSTANCE VGA_R\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (397:397:397) (437:437:437)) + (PORT i (480:480:480) (539:539:539)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -482,7 +482,7 @@ (INSTANCE VGA_R\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (527:527:527) (586:586:586)) + (PORT i (445:445:445) (499:499:499)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -492,7 +492,7 @@ (INSTANCE VGA_G\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (524:524:524) (579:579:579)) + (PORT i (313:313:313) (353:353:353)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -502,7 +502,7 @@ (INSTANCE VGA_G\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (382:382:382) (418:418:418)) + (PORT i (307:307:307) (345:345:345)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -512,7 +512,7 @@ (INSTANCE VGA_G\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (444:444:444) (480:480:480)) + (PORT i (706:706:706) (787:787:787)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -522,7 +522,7 @@ (INSTANCE VGA_G\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (444:444:444) (480:480:480)) + (PORT i (706:706:706) (787:787:787)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -532,7 +532,7 @@ (INSTANCE VGA_B\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (384:384:384) (417:417:417)) + (PORT i (618:618:618) (708:708:708)) (IOPATH i o (3177:3177:3177) (2883:2883:2883)) ) ) @@ -542,7 +542,7 @@ (INSTANCE VGA_B\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (373:373:373) (405:405:405)) + (PORT i (694:694:694) (759:759:759)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -552,7 +552,7 @@ (INSTANCE VGA_B\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (511:511:511) (561:561:561)) + (PORT i (638:638:638) (732:732:732)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -562,7 +562,7 @@ (INSTANCE VGA_B\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (738:738:738) (808:808:808)) + (PORT i (639:639:639) (733:733:733)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -590,7 +590,7 @@ (INSTANCE GPIO_1\[25\]\~output) (DELAY (ABSOLUTE - (PORT i (1282:1282:1282) (1120:1120:1120)) + (PORT i (1044:1044:1044) (916:916:916)) (IOPATH i o (1588:1588:1588) (1643:1643:1643)) ) ) @@ -600,7 +600,7 @@ (INSTANCE GPIO_1\[26\]\~output) (DELAY (ABSOLUTE - (PORT i (792:792:792) (715:715:715)) + (PORT i (696:696:696) (629:629:629)) (IOPATH i o (2841:2841:2841) (3106:3106:3106)) ) ) @@ -610,7 +610,7 @@ (INSTANCE GPIO_1\[31\]\~output) (DELAY (ABSOLUTE - (PORT i (506:506:506) (553:553:553)) + (PORT i (472:472:472) (516:516:516)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) ) ) @@ -620,11 +620,201 @@ (INSTANCE buzzer_out\~output) (DELAY (ABSOLUTE - (PORT i (749:749:749) (860:860:860)) + (PORT i (917:917:917) (1047:1047:1047)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_BA\[0\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1375:1375:1375) (1320:1320:1320)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_BA\[1\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1375:1375:1375) (1320:1320:1320)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQM\[0\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1375:1375:1375) (1320:1320:1320)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQM\[1\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1375:1375:1375) (1320:1320:1320)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_RAS_N\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1429:1429:1429) (1363:1363:1363)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_CAS_N\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1429:1429:1429) (1363:1363:1363)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_CLK\~output) + (DELAY + (ABSOLUTE + (PORT i (1062:1062:1062) (1064:1064:1064)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_WE_N\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1429:1429:1429) (1363:1363:1363)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[0\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1429:1429:1429) (1363:1363:1363)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[1\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1375:1375:1375) (1320:1320:1320)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[2\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1375:1375:1375) (1320:1320:1320)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[3\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1375:1375:1375) (1320:1320:1320)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[4\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1375:1375:1375) (1320:1320:1320)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[5\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1375:1375:1375) (1320:1320:1320)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[6\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1375:1375:1375) (1320:1320:1320)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[7\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1375:1375:1375) (1320:1320:1320)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[8\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1349:1349:1349) (1304:1304:1304)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[9\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1429:1429:1429) (1363:1363:1363)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[10\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1429:1429:1429) (1363:1363:1363)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[11\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1429:1429:1429) (1363:1363:1363)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[12\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1349:1349:1349) (1304:1304:1304)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_obuf") (INSTANCE I2C_SCLK\~output) @@ -643,6 +833,182 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (701:701:701) (808:808:808)) + (PORT oe (956:956:956) (1100:1100:1100)) + (IOPATH i o (1666:1666:1666) (1600:1600:1600)) + (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (766:766:766) (870:870:870)) + (PORT oe (956:956:956) (1100:1100:1100)) + (IOPATH i o (1666:1666:1666) (1600:1600:1600)) + (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (613:613:613) (699:699:699)) + (PORT oe (793:793:793) (885:885:885)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (673:673:673) (774:774:774)) + (PORT oe (845:845:845) (968:968:968)) + (IOPATH i o (1586:1586:1586) (1541:1541:1541)) + (IOPATH oe o (1579:1579:1579) (1514:1514:1514)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (662:662:662) (753:753:753)) + (PORT oe (669:669:669) (766:766:766)) + (IOPATH i o (1666:1666:1666) (1600:1600:1600)) + (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (811:811:811) (939:939:939)) + (PORT oe (732:732:732) (811:811:811)) + (IOPATH i o (1666:1666:1666) (1600:1600:1600)) + (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (646:646:646) (745:745:745)) + (PORT oe (732:732:732) (811:811:811)) + (IOPATH i o (1666:1666:1666) (1600:1600:1600)) + (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (303:303:303) (338:338:338)) + (PORT oe (759:759:759) (864:864:864)) + (IOPATH i o (1643:1643:1643) (1588:1588:1588)) + (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1031:1031:1031) (902:902:902)) + (IOPATH i o (1588:1588:1588) (1643:1643:1643)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (900:900:900) (791:791:791)) + (IOPATH i o (1588:1588:1588) (1643:1643:1643)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (890:890:890) (782:782:782)) + (IOPATH i o (1588:1588:1588) (1643:1643:1643)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (890:890:890) (782:782:782)) + (IOPATH i o (1588:1588:1588) (1643:1643:1643)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1021:1021:1021) (899:899:899)) + (IOPATH i o (1588:1588:1588) (1643:1643:1643)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1022:1022:1022) (894:894:894)) + (IOPATH i o (1588:1588:1588) (1643:1643:1643)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[14\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1022:1022:1022) (894:894:894)) + (IOPATH i o (1588:1588:1588) (1643:1643:1643)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[15\]\~output) + (DELAY + (ABSOLUTE + (PORT i (766:766:766) (669:669:669)) + (IOPATH i o (1600:1600:1600) (1666:1666:1666)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE CLOCK_50\~input) @@ -707,8 +1073,8 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~0) (DELAY (ABSOLUTE - (PORT datab (131:131:131) (179:179:179)) - (PORT datad (340:340:340) (316:316:316)) + (PORT datab (130:130:130) (178:178:178)) + (PORT datad (341:341:341) (316:316:316)) (IOPATH datab combout (188:188:188) (193:193:193)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -734,32 +1100,7 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (388:388:388) (421:421:421)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (714:714:714)) - (PORT datad (612:612:612) (707:707:707)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|ena_M) - (DELAY - (ABSOLUTE - (PORT datac (596:596:596) (692:692:692)) - (PORT datad (608:608:608) (702:702:702)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT inclk[0] (391:391:391) (423:423:423)) ) ) ) @@ -772,10573 +1113,6 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (280:280:280)) - (PORT datad (1132:1132:1132) (1310:1310:1310)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|nmi_armed) - (DELAY - (ABSOLUTE - (PORT clk (830:830:830) (891:891:891)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (694:694:694) (742:742:742)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (425:425:425) (491:491:491)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) - (DELAY - (ABSOLUTE - (PORT datac (133:133:133) (175:175:175)) - (PORT datad (136:136:136) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1371:1371:1371) (1593:1593:1593)) - (PORT datab (1375:1375:1375) (1595:1595:1595)) - (PORT datad (904:904:904) (1067:1067:1067)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M3_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (709:709:709)) - (PORT datab (214:214:214) (274:274:274)) - (PORT datad (615:615:615) (711:711:711)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M3_ff) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (927:927:927) (908:908:908)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (743:743:743) (846:846:846)) - (PORT datab (854:854:854) (1004:1004:1004)) - (PORT datac (752:752:752) (882:882:882)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M4_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (724:724:724)) - (PORT datab (218:218:218) (276:276:276)) - (PORT datad (605:605:605) (699:699:699)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M4_ff) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (927:927:927) (908:908:908)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal32\~0) - (DELAY - (ABSOLUTE - (PORT datab (206:206:206) (265:265:265)) - (PORT datad (363:363:363) (441:441:441)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) - (DELAY - (ABSOLUTE - (PORT datab (1456:1456:1456) (1687:1687:1687)) - (PORT datad (880:880:880) (1039:1039:1039)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|table_xx\~0) - (DELAY - (ABSOLUTE - (PORT dataa (781:781:781) (936:936:936)) - (PORT datad (666:666:666) (794:794:794)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~7) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (1066:1066:1066)) - (PORT datab (519:519:519) (601:601:601)) - (PORT datac (1240:1240:1240) (1447:1447:1447)) - (PORT datad (652:652:652) (756:756:756)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT datac (811:811:811) (946:946:946)) - (PORT datad (1277:1277:1277) (1473:1473:1473)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal36\~0) - (DELAY - (ABSOLUTE - (PORT dataa (704:704:704) (826:826:826)) - (PORT datab (932:932:932) (1116:1116:1116)) - (PORT datac (516:516:516) (599:599:599)) - (PORT datad (519:519:519) (609:609:609)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) - (DELAY - (ABSOLUTE - (PORT dataa (975:975:975) (1124:1124:1124)) - (PORT datab (801:801:801) (910:910:910)) - (PORT datac (461:461:461) (539:539:539)) - (PORT datad (425:425:425) (474:474:474)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (795:795:795)) - (PORT datab (1485:1485:1485) (1716:1716:1716)) - (PORT datac (459:459:459) (536:536:536)) - (PORT datad (543:543:543) (638:638:638)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instCB) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (920:920:920)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (902:902:902)) - (PORT ena (407:407:407) (424:424:424)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~0) - (DELAY - (ABSOLUTE - (PORT dataa (392:392:392) (481:481:481)) - (PORT datab (680:680:680) (814:814:814)) - (PORT datac (543:543:543) (642:642:642)) - (PORT datad (760:760:760) (909:909:909)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1347:1347:1347) (1572:1572:1572)) - (PORT datab (931:931:931) (1114:1114:1114)) - (PORT datac (515:515:515) (597:597:597)) - (PORT datad (376:376:376) (440:440:440)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) - (DELAY - (ABSOLUTE - (PORT dataa (987:987:987) (1141:1141:1141)) - (PORT datab (447:447:447) (515:515:515)) - (PORT datac (784:784:784) (887:887:887)) - (PORT datad (1145:1145:1145) (1327:1327:1327)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instED) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (920:920:920)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (902:902:902)) - (PORT ena (407:407:407) (424:424:424)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (485:485:485)) - (PORT datac (535:535:535) (633:633:633)) - (PORT datad (756:756:756) (905:905:905)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1256:1256:1256) (1471:1471:1471)) - (PORT datac (811:811:811) (946:946:946)) - (PORT datad (1277:1277:1277) (1474:1474:1474)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_im_we) - (DELAY - (ABSOLUTE - (PORT dataa (316:316:316) (366:366:366)) - (PORT datab (591:591:591) (702:702:702)) - (PORT datac (752:752:752) (890:890:890)) - (PORT datad (510:510:510) (595:595:595)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal49\~0) - (DELAY - (ABSOLUTE - (PORT datab (553:553:553) (662:662:662)) - (PORT datac (372:372:372) (439:439:439)) - (PORT datad (715:715:715) (832:832:832)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~1) - (DELAY - (ABSOLUTE - (PORT dataa (793:793:793) (929:929:929)) - (PORT datab (843:843:843) (988:988:988)) - (PORT datac (813:813:813) (946:946:946)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (392:392:392) (481:481:481)) - (PORT datab (680:680:680) (814:814:814)) - (PORT datac (544:544:544) (643:643:643)) - (PORT datad (760:760:760) (910:910:910)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (670:670:670) (794:794:794)) - (PORT datab (731:731:731) (859:859:859)) - (PORT datad (401:401:401) (483:483:483)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1529:1529:1529) (1775:1775:1775)) - (PORT datab (476:476:476) (565:565:565)) - (PORT datac (615:615:615) (717:717:717)) - (PORT datad (630:630:630) (728:728:728)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (522:522:522) (627:627:627)) - (PORT datab (882:882:882) (1046:1046:1046)) - (PORT datac (771:771:771) (895:895:895)) - (PORT datad (107:107:107) (132:132:132)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|nM1_int\~2) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (758:758:758)) - (PORT datad (1171:1171:1171) (1359:1359:1359)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (731:731:731)) - (PORT datab (606:606:606) (688:688:688)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (387:387:387) (458:458:458)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT datac (814:814:814) (955:955:955)) - (PORT datad (835:835:835) (972:972:972)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~4) - (DELAY - (ABSOLUTE - (PORT dataa (700:700:700) (821:821:821)) - (PORT datab (929:929:929) (1113:1113:1113)) - (PORT datac (957:957:957) (1095:1095:1095)) - (PORT datad (521:521:521) (611:611:611)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~7) - (DELAY - (ABSOLUTE - (PORT datac (1149:1149:1149) (1365:1365:1365)) - (PORT datad (685:685:685) (796:796:796)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1088:1088:1088) (1274:1274:1274)) - (PORT datac (1441:1441:1441) (1671:1671:1671)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (488:488:488) (571:571:571)) - (PORT datab (589:589:589) (696:696:696)) - (PORT datac (481:481:481) (579:579:579)) - (PORT datad (501:501:501) (587:587:587)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~1) - (DELAY - (ABSOLUTE - (PORT dataa (490:490:490) (571:571:571)) - (PORT datab (485:485:485) (562:562:562)) - (PORT datac (500:500:500) (609:609:609)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (490:490:490) (571:571:571)) - (PORT datab (485:485:485) (562:562:562)) - (PORT datac (499:499:499) (609:609:609)) - (PORT datad (652:652:652) (747:747:747)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (472:472:472) (546:546:546)) - (PORT datac (544:544:544) (643:643:643)) - (PORT datad (626:626:626) (718:718:718)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1255:1255:1255) (1470:1470:1470)) - (PORT datac (811:811:811) (947:947:947)) - (PORT datad (1276:1276:1276) (1472:1472:1472)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~2) - (DELAY - (ABSOLUTE - (PORT dataa (482:482:482) (579:579:579)) - (PORT datab (961:961:961) (1119:1119:1119)) - (PORT datac (623:623:623) (709:709:709)) - (PORT datad (350:350:350) (413:413:413)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (508:508:508) (595:595:595)) - (PORT datab (1337:1337:1337) (1560:1560:1560)) - (PORT datac (959:959:959) (1097:1097:1097)) - (PORT datad (370:370:370) (434:434:434)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) - (DELAY - (ABSOLUTE - (PORT dataa (681:681:681) (814:814:814)) - (PORT datab (1179:1179:1179) (1400:1400:1400)) - (PORT datac (470:470:470) (534:534:534)) - (PORT datad (824:824:824) (972:972:972)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~8) - (DELAY - (ABSOLUTE - (PORT datab (780:780:780) (902:902:902)) - (PORT datac (872:872:872) (1009:1009:1009)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~6) - (DELAY - (ABSOLUTE - (PORT datac (897:897:897) (1030:1030:1030)) - (PORT datad (1066:1066:1066) (1247:1247:1247)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~9) - (DELAY - (ABSOLUTE - (PORT datac (572:572:572) (683:683:683)) - (PORT datad (542:542:542) (632:632:632)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (559:559:559) (651:651:651)) - (PORT datab (547:547:547) (647:647:647)) - (PORT datac (486:486:486) (568:568:568)) - (PORT datad (1183:1183:1183) (1350:1350:1350)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (214:214:214) (265:265:265)) - (PORT datab (642:642:642) (740:740:740)) - (PORT datac (352:352:352) (411:411:411)) - (PORT datad (619:619:619) (708:708:708)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal44\~0) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (484:484:484)) - (PORT datab (686:686:686) (821:821:821)) - (PORT datac (535:535:535) (634:634:634)) - (PORT datad (756:756:756) (905:905:905)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~16) - (DELAY - (ABSOLUTE - (PORT dataa (556:556:556) (660:660:660)) - (PORT datab (737:737:737) (838:838:838)) - (PORT datac (528:528:528) (622:622:622)) - (PORT datad (598:598:598) (682:682:682)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~13) - (DELAY - (ABSOLUTE - (PORT datab (461:461:461) (539:539:539)) - (PORT datac (346:346:346) (409:409:409)) - (PORT datad (114:114:114) (136:136:136)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal50\~0) - (DELAY - (ABSOLUTE - (PORT datab (554:554:554) (662:662:662)) - (PORT datac (372:372:372) (439:439:439)) - (PORT datad (648:648:648) (765:765:765)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~2) - (DELAY - (ABSOLUTE - (PORT dataa (670:670:670) (794:794:794)) - (PORT datab (731:731:731) (860:860:860)) - (PORT datad (402:402:402) (483:483:483)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~17) - (DELAY - (ABSOLUTE - (PORT dataa (546:546:546) (648:648:648)) - (PORT datab (601:601:601) (680:680:680)) - (PORT datac (526:526:526) (619:619:619)) - (PORT datad (581:581:581) (663:663:663)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~5) - (DELAY - (ABSOLUTE - (PORT datac (894:894:894) (1057:1057:1057)) - (PORT datad (540:540:540) (631:631:631)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (409:409:409)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (105:105:105) (129:129:129)) - (PORT datad (589:589:589) (682:682:682)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (1033:1033:1033)) - (PORT datab (781:781:781) (903:903:903)) - (PORT datac (191:191:191) (228:228:228)) - (PORT datad (1020:1020:1020) (1182:1182:1182)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~15) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (674:674:674)) - (PORT datab (124:124:124) (156:156:156)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (706:706:706) (832:832:832)) - (PORT datab (845:845:845) (1000:1000:1000)) - (PORT datac (837:837:837) (976:976:976)) - (PORT datad (1172:1172:1172) (1384:1384:1384)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instIY1) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (473:473:473) (571:571:571)) - (PORT datac (350:350:350) (421:421:421)) - (PORT datad (781:781:781) (925:925:925)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (701:701:701) (832:832:832)) - (PORT datab (253:253:253) (308:308:308)) - (PORT datac (938:938:938) (1081:1081:1081)) - (PORT datad (145:145:145) (182:182:182)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (393:393:393) (481:481:481)) - (PORT datab (559:559:559) (663:663:663)) - (PORT datac (375:375:375) (457:457:457)) - (PORT datad (759:759:759) (909:909:909)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~16) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (1090:1090:1090)) - (PORT datab (862:862:862) (993:993:993)) - (PORT datac (979:979:979) (1128:1128:1128)) - (PORT datad (857:857:857) (1004:1004:1004)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (859:859:859)) - (PORT datab (696:696:696) (819:819:819)) - (PORT datac (580:580:580) (688:688:688)) - (PORT datad (936:936:936) (1067:1067:1067)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~26) - (DELAY - (ABSOLUTE - (PORT datac (375:375:375) (436:436:436)) - (PORT datad (979:979:979) (1143:1143:1143)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (333:333:333) (387:387:387)) - (PORT datac (606:606:606) (703:703:703)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (109:109:109) (141:141:141)) - (PORT datab (132:132:132) (167:167:167)) - (PORT datac (358:358:358) (422:422:422)) - (PORT datad (1181:1181:1181) (1348:1348:1348)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (651:651:651)) - (PORT datab (682:682:682) (795:795:795)) - (PORT datac (379:379:379) (441:441:441)) - (PORT datad (93:93:93) (112:112:112)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (520:520:520) (625:625:625)) - (PORT datab (880:880:880) (1044:1044:1044)) - (PORT datac (766:766:766) (890:890:890)) - (PORT datad (106:106:106) (130:130:130)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal55\~0) - (DELAY - (ABSOLUTE - (PORT dataa (159:159:159) (217:217:217)) - (PORT datac (500:500:500) (585:585:585)) - (PORT datad (507:507:507) (594:594:594)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~1) - (DELAY - (ABSOLUTE - (PORT dataa (985:985:985) (1160:1160:1160)) - (PORT datac (638:638:638) (752:752:752)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (388:388:388)) - (PORT datab (637:637:637) (747:747:747)) - (PORT datac (521:521:521) (627:627:627)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (414:414:414)) - (PORT datab (347:347:347) (398:398:398)) - (PORT datac (523:523:523) (630:630:630)) - (PORT datad (494:494:494) (570:570:570)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (499:499:499) (584:584:584)) - (PORT datab (638:638:638) (743:743:743)) - (PORT datac (1023:1023:1023) (1194:1194:1194)) - (PORT datad (484:484:484) (556:556:556)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (945:945:945) (1085:1085:1085)) - (PORT datac (898:898:898) (1044:1044:1044)) - (PORT datad (656:656:656) (761:761:761)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~0) - (DELAY - (ABSOLUTE - (PORT datac (448:448:448) (528:528:528)) - (PORT datad (490:490:490) (584:584:584)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (945:945:945) (1085:1085:1085)) - (PORT datab (915:915:915) (1066:1066:1066)) - (PORT datac (835:835:835) (984:984:984)) - (PORT datad (668:668:668) (776:776:776)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (835:835:835) (968:968:968)) - (PORT datab (691:691:691) (816:816:816)) - (PORT datac (804:804:804) (935:935:935)) - (PORT datad (446:446:446) (503:503:503)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (551:551:551)) - (PORT datab (694:694:694) (803:803:803)) - (PORT datac (752:752:752) (855:855:855)) - (PORT datad (715:715:715) (832:832:832)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~1) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (384:384:384)) - (PORT datab (534:534:534) (640:640:640)) - (PORT datad (627:627:627) (727:727:727)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~1) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (1011:1011:1011)) - (PORT datab (539:539:539) (636:636:636)) - (PORT datac (912:912:912) (1095:1095:1095)) - (PORT datad (688:688:688) (798:798:798)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal25\~0) - (DELAY - (ABSOLUTE - (PORT dataa (828:828:828) (976:976:976)) - (PORT datab (865:865:865) (1032:1032:1032)) - (PORT datac (748:748:748) (868:868:868)) - (PORT datad (877:877:877) (994:994:994)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (474:474:474) (548:548:548)) - (PORT datab (1013:1013:1013) (1170:1170:1170)) - (PORT datac (462:462:462) (531:531:531)) - (PORT datad (841:841:841) (969:969:969)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (782:782:782)) - (PORT datac (526:526:526) (615:615:615)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~0) - (DELAY - (ABSOLUTE - (PORT dataa (503:503:503) (588:588:588)) - (PORT datab (532:532:532) (619:619:619)) - (PORT datac (912:912:912) (1095:1095:1095)) - (PORT datad (688:688:688) (798:798:798)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~4) - (DELAY - (ABSOLUTE - (PORT datac (963:963:963) (1115:1115:1115)) - (PORT datad (1142:1142:1142) (1323:1323:1323)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal29\~0) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datab (632:632:632) (729:729:729)) - (PORT datac (877:877:877) (995:995:995)) - (PORT datad (817:817:817) (953:953:953)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~1) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (1009:1009:1009)) - (PORT datab (537:537:537) (633:633:633)) - (PORT datac (915:915:915) (1098:1098:1098)) - (PORT datad (693:693:693) (804:804:804)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal34\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1256:1256:1256) (1471:1471:1471)) - (PORT datab (521:521:521) (603:603:603)) - (PORT datac (102:102:102) (123:123:123)) - (PORT datad (232:232:232) (271:271:271)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (292:292:292)) - (PORT datab (518:518:518) (600:600:600)) - (PORT datac (1240:1240:1240) (1447:1447:1447)) - (PORT datad (622:622:622) (714:714:714)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal35\~0) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (294:294:294)) - (PORT datab (520:520:520) (602:602:602)) - (PORT datac (1240:1240:1240) (1447:1447:1447)) - (PORT datad (102:102:102) (120:120:120)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal38\~2) - (DELAY - (ABSOLUTE - (PORT dataa (924:924:924) (1089:1089:1089)) - (PORT datab (876:876:876) (1032:1032:1032)) - (PORT datac (978:978:978) (1128:1128:1128)) - (PORT datad (815:815:815) (930:930:930)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (708:708:708)) - (PORT datab (616:616:616) (736:736:736)) - (PORT datac (315:315:315) (370:370:370)) - (PORT datad (487:487:487) (571:571:571)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (468:468:468) (551:551:551)) - (PORT datab (784:784:784) (923:923:923)) - (PORT datac (325:325:325) (381:381:381)) - (PORT datad (316:316:316) (360:360:360)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~0) - (DELAY - (ABSOLUTE - (PORT datab (1101:1101:1101) (1266:1266:1266)) - (PORT datac (656:656:656) (766:766:766)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (299:299:299)) - (PORT datab (524:524:524) (606:606:606)) - (PORT datac (1238:1238:1238) (1444:1444:1444)) - (PORT datad (188:188:188) (219:219:219)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (724:724:724) (850:850:850)) - (PORT datab (657:657:657) (761:761:761)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (717:717:717) (845:845:845)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (430:430:430)) - (PORT datab (336:336:336) (396:396:396)) - (PORT datac (95:95:95) (119:119:119)) - (PORT datad (638:638:638) (735:735:735)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (496:496:496) (581:581:581)) - (PORT datab (122:122:122) (157:157:157)) - (PORT datac (335:335:335) (390:390:390)) - (PORT datad (361:361:361) (420:420:420)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (800:800:800) (920:920:920)) - (PORT datab (687:687:687) (811:811:811)) - (PORT datac (373:373:373) (443:443:443)) - (PORT datad (633:633:633) (722:722:722)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (454:454:454)) - (PORT datab (621:621:621) (717:717:717)) - (PORT datac (1030:1030:1030) (1202:1202:1202)) - (PORT datad (307:307:307) (363:363:363)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (824:824:824) (963:963:963)) - (PORT datab (633:633:633) (730:730:730)) - (PORT datac (670:670:670) (792:792:792)) - (PORT datad (359:359:359) (425:425:425)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (831:831:831) (971:971:971)) - (PORT datab (377:377:377) (452:452:452)) - (PORT datac (666:666:666) (788:788:788)) - (PORT datad (778:778:778) (892:892:892)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|M5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (716:716:716)) - (PORT datab (144:144:144) (193:193:193)) - (PORT datad (611:611:611) (705:705:705)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|M5) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (927:927:927) (908:908:908)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) - (DELAY - (ABSOLUTE - (PORT datab (908:908:908) (1071:1071:1071)) - (PORT datac (1462:1462:1462) (1689:1689:1689)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~29) - (DELAY - (ABSOLUTE - (PORT dataa (333:333:333) (389:389:389)) - (PORT datab (516:516:516) (605:605:605)) - (PORT datac (563:563:563) (665:665:665)) - (PORT datad (364:364:364) (430:430:430)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1104:1104:1104) (1300:1300:1300)) - (PORT datab (377:377:377) (453:453:453)) - (PORT datac (376:376:376) (440:440:440)) - (PORT datad (309:309:309) (358:358:358)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1059:1059:1059) (1216:1216:1216)) - (PORT datab (516:516:516) (618:618:618)) - (PORT datac (102:102:102) (124:124:124)) - (PORT datad (97:97:97) (118:118:118)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (702:702:702) (833:833:833)) - (PORT datab (252:252:252) (307:307:307)) - (PORT datac (936:936:936) (1080:1080:1080)) - (PORT datad (146:146:146) (182:182:182)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~1) - (DELAY - (ABSOLUTE - (PORT dataa (780:780:780) (935:935:935)) - (PORT datab (522:522:522) (616:616:616)) - (PORT datac (526:526:526) (613:613:613)) - (PORT datad (668:668:668) (796:796:796)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~14) - (DELAY - (ABSOLUTE - (PORT dataa (552:552:552) (655:655:655)) - (PORT datab (738:738:738) (839:839:839)) - (PORT datac (527:527:527) (621:621:621)) - (PORT datad (596:596:596) (679:679:679)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (333:333:333) (396:396:396)) - (PORT datab (703:703:703) (820:820:820)) - (PORT datac (306:306:306) (350:350:350)) - (PORT datad (911:911:911) (1051:1051:1051)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~0) - (DELAY - (ABSOLUTE - (PORT dataa (393:393:393) (481:481:481)) - (PORT datab (114:114:114) (143:143:143)) - (PORT datac (142:142:142) (190:190:190)) - (PORT datad (494:494:494) (571:571:571)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (488:488:488) (582:582:582)) - (PORT datab (619:619:619) (740:740:740)) - (PORT datac (607:607:607) (691:691:691)) - (PORT datad (370:370:370) (429:429:429)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) - (DELAY - (ABSOLUTE - (PORT dataa (240:240:240) (291:291:291)) - (PORT datab (1132:1132:1132) (1336:1336:1336)) - (PORT datac (579:579:579) (676:676:676)) - (PORT datad (891:891:891) (1034:1034:1034)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (505:505:505) (599:599:599)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (487:487:487) (571:571:571)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (396:396:396)) - (PORT datab (661:661:661) (762:762:762)) - (PORT datac (109:109:109) (134:134:134)) - (PORT datad (338:338:338) (397:397:397)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (212:212:212) (261:261:261)) - (PORT datab (647:647:647) (745:745:745)) - (PORT datac (350:350:350) (409:409:409)) - (PORT datad (620:620:620) (709:709:709)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (924:924:924) (1088:1088:1088)) - (PORT datab (861:861:861) (993:993:993)) - (PORT datac (978:978:978) (1128:1128:1128)) - (PORT datad (855:855:855) (1002:1002:1002)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (1090:1090:1090)) - (PORT datab (862:862:862) (994:994:994)) - (PORT datac (979:979:979) (1129:1129:1129)) - (PORT datad (858:858:858) (1005:1005:1005)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (949:949:949) (1095:1095:1095)) - (PORT datab (826:826:826) (967:967:967)) - (PORT datac (1442:1442:1442) (1672:1672:1672)) - (PORT datad (1066:1066:1066) (1247:1247:1247)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (397:397:397)) - (PORT datab (702:702:702) (819:819:819)) - (PORT datac (608:608:608) (702:702:702)) - (PORT datad (290:290:290) (330:330:330)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (701:701:701) (833:833:833)) - (PORT datab (252:252:252) (307:307:307)) - (PORT datac (937:937:937) (1081:1081:1081)) - (PORT datad (146:146:146) (182:182:182)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (729:729:729)) - (PORT datab (639:639:639) (740:740:740)) - (PORT datac (294:294:294) (332:332:332)) - (PORT datad (319:319:319) (370:370:370)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (158:158:158) (205:205:205)) - (PORT datab (253:253:253) (308:308:308)) - (PORT datac (101:101:101) (121:121:121)) - (PORT datad (782:782:782) (926:926:926)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal46\~0) - (DELAY - (ABSOLUTE - (PORT dataa (156:156:156) (213:213:213)) - (PORT datab (517:517:517) (613:613:613)) - (PORT datac (501:501:501) (586:586:586)) - (PORT datad (662:662:662) (789:789:789)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (829:829:829)) - (PORT datab (475:475:475) (551:551:551)) - (PORT datac (942:942:942) (1086:1086:1086)) - (PORT datad (144:144:144) (178:178:178)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1196:1196:1196) (1388:1388:1388)) - (PORT datab (1137:1137:1137) (1323:1323:1323)) - (PORT datac (552:552:552) (649:649:649)) - (PORT datad (663:663:663) (762:762:762)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (770:770:770) (890:890:890)) - (PORT datab (613:613:613) (728:728:728)) - (PORT datac (402:402:402) (458:458:458)) - (PORT datad (679:679:679) (797:797:797)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (547:547:547) (645:645:645)) - (PORT datac (625:625:625) (720:720:720)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (162:162:162) (210:210:210)) - (PORT datab (252:252:252) (307:307:307)) - (PORT datac (666:666:666) (779:779:779)) - (PORT datad (777:777:777) (921:921:921)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (794:794:794)) - (PORT datab (1230:1230:1230) (1413:1413:1413)) - (PORT datac (749:749:749) (886:886:886)) - (PORT datad (534:534:534) (628:628:628)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1009:1009:1009) (1176:1176:1176)) - (PORT datab (728:728:728) (854:854:854)) - (PORT datac (751:751:751) (855:855:855)) - (PORT datad (477:477:477) (546:546:546)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (374:374:374)) - (PORT datac (295:295:295) (337:337:337)) - (PORT datad (703:703:703) (813:813:813)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (104:104:104) (121:121:121)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datac (455:455:455) (527:527:527)) - (PORT datad (472:472:472) (544:544:544)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) - (DELAY - (ABSOLUTE - (PORT datac (1152:1152:1152) (1344:1344:1344)) - (PORT datad (536:536:536) (632:632:632)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~36) - (DELAY - (ABSOLUTE - (PORT dataa (922:922:922) (1087:1087:1087)) - (PORT datab (861:861:861) (992:992:992)) - (PORT datac (978:978:978) (1128:1128:1128)) - (PORT datad (854:854:854) (1001:1001:1001)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~9) - (DELAY - (ABSOLUTE - (PORT dataa (375:375:375) (446:446:446)) - (PORT datab (844:844:844) (979:979:979)) - (PORT datac (635:635:635) (741:741:741)) - (PORT datad (782:782:782) (889:889:889)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1213:1213:1213) (1420:1420:1420)) - (PORT datab (379:379:379) (463:463:463)) - (PORT datac (930:930:930) (1068:1068:1068)) - (PORT datad (110:110:110) (130:130:130)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (705:705:705) (831:831:831)) - (PORT datad (1162:1162:1162) (1373:1373:1373)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (504:504:504) (599:599:599)) - (PORT datab (241:241:241) (281:281:281)) - (PORT datac (213:213:213) (262:262:262)) - (PORT datad (880:880:880) (1017:1017:1017)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (393:393:393)) - (PORT datab (640:640:640) (745:745:745)) - (PORT datac (805:805:805) (935:935:935)) - (PORT datad (173:173:173) (205:205:205)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~7) - (DELAY - (ABSOLUTE - (PORT datac (845:845:845) (986:986:986)) - (PORT datad (630:630:630) (726:726:726)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (703:703:703) (836:836:836)) - (PORT datab (473:473:473) (549:549:549)) - (PORT datac (934:934:934) (1077:1077:1077)) - (PORT datad (148:148:148) (184:184:184)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (702:702:702) (834:834:834)) - (PORT datab (252:252:252) (307:307:307)) - (PORT datac (936:936:936) (1079:1079:1079)) - (PORT datad (147:147:147) (183:183:183)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (793:793:793) (907:907:907)) - (PORT datab (596:596:596) (688:688:688)) - (PORT datac (582:582:582) (663:663:663)) - (PORT datad (527:527:527) (618:618:618)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (447:447:447)) - (PORT datab (650:650:650) (762:762:762)) - (PORT datac (811:811:811) (941:941:941)) - (PORT datad (831:831:831) (957:957:957)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (241:241:241)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (344:344:344) (400:400:400)) - (PORT datad (99:99:99) (120:120:120)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (298:298:298) (349:349:349)) - (PORT datab (466:466:466) (534:534:534)) - (PORT datac (467:467:467) (542:542:542)) - (PORT datad (428:428:428) (494:494:494)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (721:721:721)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datac (101:101:101) (128:128:128)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (276:276:276)) - (PORT datab (685:685:685) (797:797:797)) - (PORT datac (360:360:360) (430:430:430)) - (PORT datad (725:725:725) (861:861:861)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~8) - (DELAY - (ABSOLUTE - (PORT datab (1663:1663:1663) (1925:1925:1925)) - (PORT datac (1123:1123:1123) (1307:1307:1307)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1045:1045:1045) (1187:1187:1187)) - (PORT datab (1192:1192:1192) (1397:1397:1397)) - (PORT datac (618:618:618) (703:703:703)) - (PORT datad (109:109:109) (130:130:130)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) - (DELAY - (ABSOLUTE - (PORT datac (670:670:670) (795:795:795)) - (PORT datad (335:335:335) (398:398:398)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (758:758:758)) - (PORT datab (516:516:516) (598:598:598)) - (PORT datac (1136:1136:1136) (1290:1290:1290)) - (PORT datad (826:826:826) (963:963:963)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (701:701:701)) - (PORT datab (1350:1350:1350) (1567:1567:1567)) - (PORT datad (1175:1175:1175) (1364:1364:1364)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (847:847:847) (974:974:974)) - (PORT datab (563:563:563) (662:662:662)) - (PORT datac (491:491:491) (576:576:576)) - (PORT datad (627:627:627) (719:719:719)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (804:804:804) (914:914:914)) - (PORT datab (633:633:633) (730:730:730)) - (PORT datac (174:174:174) (207:207:207)) - (PORT datad (629:629:629) (717:717:717)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (195:195:195) (235:235:235)) - (PORT datab (588:588:588) (678:678:678)) - (PORT datac (874:874:874) (992:992:992)) - (PORT datad (439:439:439) (505:505:505)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (734:734:734)) - (PORT datab (643:643:643) (735:735:735)) - (PORT datac (464:464:464) (527:527:527)) - (PORT datad (440:440:440) (503:503:503)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (755:755:755)) - (PORT datab (153:153:153) (197:197:197)) - (PORT datac (138:138:138) (178:178:178)) - (PORT datad (136:136:136) (167:167:167)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) - (DELAY - (ABSOLUTE - (PORT datac (527:527:527) (616:616:616)) - (PORT datad (1139:1139:1139) (1332:1332:1332)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (472:472:472) (546:546:546)) - (PORT datab (563:563:563) (662:662:662)) - (PORT datac (682:682:682) (798:798:798)) - (PORT datad (626:626:626) (718:718:718)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) - (DELAY - (ABSOLUTE - (PORT datab (114:114:114) (142:142:142)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (755:755:755)) - (PORT datab (562:562:562) (662:662:662)) - (PORT datac (1135:1135:1135) (1289:1289:1289)) - (PORT datad (827:827:827) (964:964:964)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (741:741:741) (866:866:866)) - (PORT datab (650:650:650) (759:759:759)) - (PORT datac (469:469:469) (538:538:538)) - (PORT datad (755:755:755) (896:896:896)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (516:516:516) (608:608:608)) - (PORT datab (533:533:533) (618:618:618)) - (PORT datac (671:671:671) (792:792:792)) - (PORT datad (361:361:361) (422:422:422)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (768:768:768) (921:921:921)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (201:201:201) (232:232:232)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal69\~0) - (DELAY - (ABSOLUTE - (PORT dataa (480:480:480) (577:577:577)) - (PORT datab (956:956:956) (1113:1113:1113)) - (PORT datac (618:618:618) (701:701:701)) - (PORT datad (356:356:356) (419:419:419)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~5) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (791:791:791)) - (PORT datad (648:648:648) (770:770:770)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) - (DELAY - (ABSOLUTE - (PORT dataa (561:561:561) (653:653:653)) - (PORT datab (1135:1135:1135) (1296:1296:1296)) - (PORT datac (623:623:623) (708:708:708)) - (PORT datad (351:351:351) (414:414:414)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~12) - (DELAY - (ABSOLUTE - (PORT dataa (991:991:991) (1166:1166:1166)) - (PORT datab (511:511:511) (594:594:594)) - (PORT datad (117:117:117) (134:134:134)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal56\~0) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (415:415:415)) - (PORT datab (638:638:638) (748:748:748)) - (PORT datac (520:520:520) (626:626:626)) - (PORT datad (500:500:500) (583:583:583)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~11) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (970:970:970)) - (PORT datab (687:687:687) (811:811:811)) - (PORT datac (812:812:812) (944:944:944)) - (PORT datad (441:441:441) (498:498:498)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~2) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (515:515:515)) - (PORT datab (465:465:465) (538:538:538)) - (PORT datad (364:364:364) (427:427:427)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1108:1108:1108) (1300:1300:1300)) - (PORT datab (1182:1182:1182) (1366:1366:1366)) - (PORT datac (284:284:284) (330:330:330)) - (PORT datad (971:971:971) (1107:1107:1107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (463:463:463) (539:539:539)) - (PORT datab (533:533:533) (615:615:615)) - (PORT datac (93:93:93) (117:117:117)) - (PORT datad (816:816:816) (946:946:946)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~5) - (DELAY - (ABSOLUTE - (PORT datac (627:627:627) (734:734:734)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (798:798:798)) - (PORT datab (551:551:551) (659:659:659)) - (PORT datac (371:371:371) (438:438:438)) - (PORT datad (713:713:713) (830:830:830)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) - (DELAY - (ABSOLUTE - (PORT datab (611:611:611) (734:734:734)) - (PORT datac (830:830:830) (972:972:972)) - (PORT datad (1305:1305:1305) (1526:1526:1526)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (440:440:440)) - (PORT datab (997:997:997) (1144:1144:1144)) - (PORT datac (553:553:553) (652:652:652)) - (PORT datad (665:665:665) (764:764:764)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (673:673:673)) - (PORT datab (683:683:683) (789:789:789)) - (PORT datac (613:613:613) (700:700:700)) - (PORT datad (97:97:97) (117:117:117)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) - (DELAY - (ABSOLUTE - (PORT dataa (525:525:525) (605:605:605)) - (PORT datab (616:616:616) (732:732:732)) - (PORT datac (561:561:561) (661:661:661)) - (PORT datad (639:639:639) (736:736:736)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (683:683:683)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (701:701:701) (826:826:826)) - (PORT datad (598:598:598) (707:707:707)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) - (DELAY - (ABSOLUTE - (PORT datab (842:842:842) (985:985:985)) - (PORT datac (831:831:831) (968:968:968)) - (PORT datad (727:727:727) (823:823:823)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (432:432:432) (499:499:499)) - (PORT datab (457:457:457) (527:527:527)) - (PORT datac (680:680:680) (759:759:759)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (906:906:906)) - (PORT datab (1159:1159:1159) (1325:1325:1325)) - (PORT datac (457:457:457) (530:530:530)) - (PORT datad (425:425:425) (487:487:487)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal48\~0) - (DELAY - (ABSOLUTE - (PORT dataa (479:479:479) (576:576:576)) - (PORT datab (955:955:955) (1113:1113:1113)) - (PORT datac (618:618:618) (701:701:701)) - (PORT datad (357:357:357) (420:420:420)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) - (DELAY - (ABSOLUTE - (PORT dataa (517:517:517) (604:604:604)) - (PORT datab (491:491:491) (589:589:589)) - (PORT datac (524:524:524) (617:617:617)) - (PORT datad (714:714:714) (820:820:820)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (701:701:701) (837:837:837)) - (PORT datab (547:547:547) (646:646:646)) - (PORT datac (112:112:112) (138:138:138)) - (PORT datad (688:688:688) (791:791:791)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1010:1010:1010) (1177:1177:1177)) - (PORT datab (733:733:733) (860:860:860)) - (PORT datac (1145:1145:1145) (1334:1334:1334)) - (PORT datad (450:450:450) (514:514:514)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) - (DELAY - (ABSOLUTE - (PORT dataa (664:664:664) (771:771:771)) - (PORT datab (562:562:562) (662:662:662)) - (PORT datac (344:344:344) (398:398:398)) - (PORT datad (631:631:631) (724:724:724)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) - (DELAY - (ABSOLUTE - (PORT dataa (487:487:487) (573:573:573)) - (PORT datab (600:600:600) (713:713:713)) - (PORT datac (310:310:310) (364:364:364)) - (PORT datad (595:595:595) (683:683:683)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~10) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (1086:1086:1086)) - (PORT datab (872:872:872) (1027:1027:1027)) - (PORT datac (978:978:978) (1128:1128:1128)) - (PORT datad (820:820:820) (936:936:936)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (1064:1064:1064)) - (PORT datab (853:853:853) (1005:1005:1005)) - (PORT datac (524:524:524) (616:616:616)) - (PORT datad (657:657:657) (760:760:760)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) - (DELAY - (ABSOLUTE - (PORT dataa (307:307:307) (366:366:366)) - (PORT datab (496:496:496) (581:581:581)) - (PORT datac (528:528:528) (621:621:621)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (1079:1079:1079)) - (PORT datab (630:630:630) (743:743:743)) - (PORT datac (1001:1001:1001) (1169:1169:1169)) - (PORT datad (529:529:529) (621:621:621)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (797:797:797)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (542:542:542) (622:622:622)) - (PORT datad (515:515:515) (597:597:597)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (754:754:754) (879:879:879)) - (PORT datab (544:544:544) (643:643:643)) - (PORT datac (304:304:304) (357:357:357)) - (PORT datad (349:349:349) (410:410:410)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal20\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1134:1134:1134) (1319:1319:1319)) - (PORT datab (852:852:852) (1008:1008:1008)) - (PORT datac (123:123:123) (151:151:151)) - (PORT datad (617:617:617) (712:712:712)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal68\~2) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (1086:1086:1086)) - (PORT datab (873:873:873) (1028:1028:1028)) - (PORT datac (978:978:978) (1128:1128:1128)) - (PORT datad (819:819:819) (935:935:935)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (516:516:516) (605:605:605)) - (PORT datab (792:792:792) (918:918:918)) - (PORT datac (749:749:749) (887:887:887)) - (PORT datad (855:855:855) (1000:1000:1000)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~13) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (433:433:433)) - (PORT datab (883:883:883) (1009:1009:1009)) - (PORT datac (709:709:709) (807:807:807)) - (PORT datad (820:820:820) (956:956:956)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (1028:1028:1028)) - (PORT datab (766:766:766) (906:906:906)) - (PORT datac (624:624:624) (718:718:718)) - (PORT datad (436:436:436) (498:498:498)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (441:441:441)) - (PORT datab (550:550:550) (651:651:651)) - (PORT datac (631:631:631) (756:756:756)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1268:1268:1268) (1469:1469:1469)) - (PORT datab (459:459:459) (530:530:530)) - (PORT datac (1182:1182:1182) (1375:1375:1375)) - (PORT datad (362:362:362) (424:424:424)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (515:515:515) (602:602:602)) - (PORT datab (548:548:548) (647:647:647)) - (PORT datac (815:815:815) (942:942:942)) - (PORT datad (843:843:843) (988:988:988)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (407:407:407)) - (PORT datab (232:232:232) (277:277:277)) - (PORT datac (107:107:107) (130:130:130)) - (PORT datad (776:776:776) (892:892:892)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (333:333:333) (390:390:390)) - (PORT datab (544:544:544) (642:642:642)) - (PORT datac (479:479:479) (551:551:551)) - (PORT datad (450:450:450) (513:513:513)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (225:225:225)) - (PORT datab (169:169:169) (206:206:206)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (147:147:147)) - (PORT datab (119:119:119) (149:149:149)) - (PORT datac (106:106:106) (129:129:129)) - (PORT datad (106:106:106) (124:124:124)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (395:395:395)) - (PORT datab (810:810:810) (932:932:932)) - (PORT datac (336:336:336) (400:400:400)) - (PORT datad (917:917:917) (1055:1055:1055)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (427:427:427)) - (PORT datab (549:549:549) (650:650:650)) - (PORT datac (631:631:631) (755:755:755)) - (PORT datad (1285:1285:1285) (1467:1467:1467)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (515:515:515) (604:604:604)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (175:175:175) (210:210:210)) - (PORT datad (1286:1286:1286) (1469:1469:1469)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~4) - (DELAY - (ABSOLUTE - (PORT datab (589:589:589) (720:720:720)) - (PORT datac (812:812:812) (935:935:935)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (774:774:774) (900:900:900)) - (PORT datab (535:535:535) (623:623:623)) - (PORT datac (614:614:614) (721:721:721)) - (PORT datad (788:788:788) (903:903:903)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (547:547:547) (635:635:635)) - (PORT datab (798:798:798) (921:921:921)) - (PORT datac (544:544:544) (624:624:624)) - (PORT datad (103:103:103) (121:121:121)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (687:687:687)) - (PORT datab (653:653:653) (762:762:762)) - (PORT datac (371:371:371) (437:437:437)) - (PORT datad (483:483:483) (565:565:565)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) - (DELAY - (ABSOLUTE - (PORT dataa (318:318:318) (371:371:371)) - (PORT datac (294:294:294) (345:345:345)) - (PORT datad (285:285:285) (323:323:323)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (133:133:133) (171:171:171)) - (PORT datab (689:689:689) (799:799:799)) - (PORT datac (642:642:642) (742:742:742)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (487:487:487) (571:571:571)) - (PORT datab (459:459:459) (531:531:531)) - (PORT datac (173:173:173) (208:208:208)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1136:1136:1136) (1321:1321:1321)) - (PORT datab (503:503:503) (587:587:587)) - (PORT datac (120:120:120) (149:149:149)) - (PORT datad (788:788:788) (906:906:906)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) - (DELAY - (ABSOLUTE - (PORT dataa (1018:1018:1018) (1199:1199:1199)) - (PORT datab (890:890:890) (1045:1045:1045)) - (PORT datad (790:790:790) (920:920:920)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1154:1154:1154) (1317:1317:1317)) - (PORT datab (529:529:529) (620:620:620)) - (PORT datac (591:591:591) (687:687:687)) - (PORT datad (502:502:502) (603:603:603)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) - (DELAY - (ABSOLUTE - (PORT dataa (731:731:731) (831:831:831)) - (PORT datab (648:648:648) (761:761:761)) - (PORT datac (824:824:824) (943:943:943)) - (PORT datad (832:832:832) (958:958:958)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (722:722:722)) - (PORT datab (118:118:118) (153:153:153)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (459:459:459) (527:527:527)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT datab (532:532:532) (631:631:631)) - (PORT datac (308:308:308) (355:355:355)) - (PORT datad (372:372:372) (443:443:443)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) - (DELAY - (ABSOLUTE - (PORT datac (509:509:509) (606:606:606)) - (PORT datad (376:376:376) (447:447:447)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (653:653:653)) - (PORT datab (394:394:394) (463:463:463)) - (PORT datac (485:485:485) (568:568:568)) - (PORT datad (984:984:984) (1149:1149:1149)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~10) - (DELAY - (ABSOLUTE - (PORT dataa (849:849:849) (998:998:998)) - (PORT datab (833:833:833) (979:979:979)) - (PORT datac (1038:1038:1038) (1201:1201:1201)) - (PORT datad (215:215:215) (255:255:255)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~11) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (781:781:781)) - (PORT datac (522:522:522) (609:609:609)) - (PORT datad (685:685:685) (795:795:795)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) - (DELAY - (ABSOLUTE - (PORT dataa (687:687:687) (790:790:790)) - (PORT datab (795:795:795) (904:904:904)) - (PORT datac (597:597:597) (680:680:680)) - (PORT datad (723:723:723) (824:824:824)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) - (DELAY - (ABSOLUTE - (PORT datab (511:511:511) (594:594:594)) - (PORT datac (279:279:279) (321:321:321)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) - (DELAY - (ABSOLUTE - (PORT dataa (559:559:559) (651:651:651)) - (PORT datab (394:394:394) (463:463:463)) - (PORT datac (484:484:484) (566:566:566)) - (PORT datad (983:983:983) (1148:1148:1148)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) - (DELAY - (ABSOLUTE - (PORT dataa (752:752:752) (866:866:866)) - (PORT datab (509:509:509) (593:593:593)) - (PORT datad (334:334:334) (391:391:391)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (469:469:469) (544:544:544)) - (PORT datab (840:840:840) (975:975:975)) - (PORT datac (739:739:739) (871:871:871)) - (PORT datad (1222:1222:1222) (1416:1416:1416)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1293:1293:1293) (1503:1503:1503)) - (PORT datab (499:499:499) (582:582:582)) - (PORT datac (192:192:192) (228:228:228)) - (PORT datad (821:821:821) (954:954:954)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (111:111:111) (145:145:145)) - (PORT datab (128:128:128) (160:160:160)) - (PORT datac (456:456:456) (522:522:522)) - (PORT datad (291:291:291) (331:331:331)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~5) - (DELAY - (ABSOLUTE - (PORT datac (1434:1434:1434) (1701:1701:1701)) - (PORT datad (1109:1109:1109) (1285:1285:1285)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) - (DELAY - (ABSOLUTE - (PORT dataa (823:823:823) (951:951:951)) - (PORT datab (458:458:458) (530:530:530)) - (PORT datac (530:530:530) (608:608:608)) - (PORT datad (362:362:362) (424:424:424)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) - (DELAY - (ABSOLUTE - (PORT dataa (790:790:790) (902:902:902)) - (PORT datab (730:730:730) (837:837:837)) - (PORT datac (453:453:453) (531:531:531)) - (PORT datad (428:428:428) (489:489:489)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) - (DELAY - (ABSOLUTE - (PORT dataa (599:599:599) (690:690:690)) - (PORT datab (1442:1442:1442) (1669:1669:1669)) - (PORT datac (871:871:871) (1031:1031:1031)) - (PORT datad (948:948:948) (1102:1102:1102)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) - (DELAY - (ABSOLUTE - (PORT datac (112:112:112) (138:138:138)) - (PORT datad (112:112:112) (132:132:132)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) - (DELAY - (ABSOLUTE - (PORT dataa (681:681:681) (799:799:799)) - (PORT datab (727:727:727) (862:862:862)) - (PORT datac (985:985:985) (1124:1124:1124)) - (PORT datad (446:446:446) (511:511:511)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (242:242:242)) - (PORT datab (204:204:204) (243:243:243)) - (PORT datac (189:189:189) (225:225:225)) - (PORT datad (110:110:110) (134:134:134)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) - (DELAY - (ABSOLUTE - (PORT dataa (848:848:848) (975:975:975)) - (PORT datab (729:729:729) (862:862:862)) - (PORT datac (491:491:491) (575:575:575)) - (PORT datad (630:630:630) (722:722:722)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (454:454:454)) - (PORT datab (1530:1530:1530) (1769:1769:1769)) - (PORT datac (725:725:725) (854:854:854)) - (PORT datad (307:307:307) (354:354:354)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low) - (DELAY - (ABSOLUTE - (PORT dataa (480:480:480) (556:556:556)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datac (104:104:104) (132:132:132)) - (PORT datad (96:96:96) (116:116:116)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (414:414:414)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (306:306:306) (350:350:350)) - (PORT datad (816:816:816) (927:927:927)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (773:773:773) (897:897:897)) - (PORT datab (1023:1023:1023) (1165:1165:1165)) - (PORT datac (627:627:627) (722:722:722)) - (PORT datad (986:986:986) (1115:1115:1115)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1049:1049:1049) (1198:1198:1198)) - (PORT datab (102:102:102) (129:129:129)) - (PORT datac (657:657:657) (749:749:749)) - (PORT datad (325:325:325) (380:380:380)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (338:338:338) (395:395:395)) - (PORT datab (578:578:578) (690:690:690)) - (PORT datac (482:482:482) (550:550:550)) - (PORT datad (893:893:893) (1048:1048:1048)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (188:188:188) (226:226:226)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (562:562:562) (628:628:628)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (911:911:911)) - (PORT datab (797:797:797) (920:920:920)) - (PORT datac (330:330:330) (380:380:380)) - (PORT datad (512:512:512) (593:593:593)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (1079:1079:1079)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (1001:1001:1001) (1169:1169:1169)) - (PORT datad (519:519:519) (601:601:601)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (911:911:911)) - (PORT datab (797:797:797) (921:921:921)) - (PORT datac (617:617:617) (724:724:724)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1016:1016:1016) (1164:1164:1164)) - (PORT datab (173:173:173) (209:209:209)) - (PORT datac (614:614:614) (721:721:721)) - (PORT datad (657:657:657) (768:768:768)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (905:905:905)) - (PORT datab (796:796:796) (920:920:920)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (526:526:526) (617:617:617)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (547:547:547) (644:644:644)) - (PORT datac (585:585:585) (667:667:667)) - (PORT datad (656:656:656) (767:767:767)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1100:1100:1100) (1268:1268:1268)) - (PORT datab (1019:1019:1019) (1160:1160:1160)) - (PORT datac (624:624:624) (719:719:719)) - (PORT datad (1134:1134:1134) (1315:1315:1315)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (232:232:232)) - (PORT datab (1020:1020:1020) (1161:1161:1161)) - (PORT datac (877:877:877) (996:996:996)) - (PORT datad (98:98:98) (121:121:121)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (409:409:409)) - (PORT datab (570:570:570) (660:660:660)) - (PORT datac (708:708:708) (805:805:805)) - (PORT datad (439:439:439) (498:498:498)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (405:405:405)) - (PORT datac (580:580:580) (650:650:650)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (547:547:547) (636:636:636)) - (PORT datab (795:795:795) (919:919:919)) - (PORT datac (546:546:546) (626:626:626)) - (PORT datad (661:661:661) (773:773:773)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (197:197:197) (236:236:236)) - (PORT datab (111:111:111) (144:144:144)) - (PORT datac (182:182:182) (221:221:221)) - (PORT datad (178:178:178) (207:207:207)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) - (DELAY - (ABSOLUTE - (PORT datab (349:349:349) (409:409:409)) - (PORT datac (485:485:485) (563:563:563)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (304:304:304) (355:355:355)) - (PORT datab (483:483:483) (559:559:559)) - (PORT datac (102:102:102) (123:123:123)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) - (DELAY - (ABSOLUTE - (PORT dataa (444:444:444) (511:511:511)) - (PORT datab (376:376:376) (447:447:447)) - (PORT datac (530:530:530) (609:609:609)) - (PORT datad (443:443:443) (505:505:505)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) - (DELAY - (ABSOLUTE - (PORT datab (460:460:460) (537:537:537)) - (PORT datad (436:436:436) (495:495:495)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) - (DELAY - (ABSOLUTE - (PORT datab (113:113:113) (146:146:146)) - (PORT datac (182:182:182) (221:221:221)) - (PORT datad (179:179:179) (208:208:208)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (1079:1079:1079)) - (PORT datab (1019:1019:1019) (1194:1194:1194)) - (PORT datac (1001:1001:1001) (1169:1169:1169)) - (PORT datad (533:533:533) (609:609:609)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (911:911:911)) - (PORT datab (796:796:796) (919:919:919)) - (PORT datac (545:545:545) (626:626:626)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1017:1017:1017) (1164:1164:1164)) - (PORT datab (560:560:560) (645:645:645)) - (PORT datac (161:161:161) (190:190:190)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (420:420:420)) - (PORT datab (325:325:325) (375:375:375)) - (PORT datac (441:441:441) (508:508:508)) - (PORT datad (171:171:171) (202:202:202)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (720:720:720) (841:841:841)) - (PORT datab (551:551:551) (651:651:651)) - (PORT datac (608:608:608) (730:730:730)) - (PORT datad (550:550:550) (651:651:651)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (913:913:913)) - (PORT datab (733:733:733) (835:835:835)) - (PORT datac (878:878:878) (998:998:998)) - (PORT datad (718:718:718) (838:838:838)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (760:760:760)) - (PORT datab (583:583:583) (702:702:702)) - (PORT datad (763:763:763) (910:910:910)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (448:448:448)) - (PORT datab (535:535:535) (630:630:630)) - (PORT datac (291:291:291) (336:336:336)) - (PORT datad (119:119:119) (137:137:137)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (491:491:491)) - (PORT datab (531:531:531) (621:621:621)) - (PORT datac (591:591:591) (686:686:686)) - (PORT datad (497:497:497) (597:597:597)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (689:689:689) (810:810:810)) - (PORT datab (119:119:119) (153:153:153)) - (PORT datac (1335:1335:1335) (1559:1559:1559)) - (PORT datad (88:88:88) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal8\~0) - (DELAY - (ABSOLUTE - (PORT datab (1162:1162:1162) (1349:1349:1349)) - (PORT datac (963:963:963) (1116:1116:1116)) - (PORT datad (644:644:644) (755:755:755)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (803:803:803) (934:934:934)) - (PORT datab (791:791:791) (908:908:908)) - (PORT datac (457:457:457) (519:519:519)) - (PORT datad (205:205:205) (245:245:245)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) - (DELAY - (ABSOLUTE - (PORT dataa (472:472:472) (546:546:546)) - (PORT datab (639:639:639) (740:740:740)) - (PORT datac (544:544:544) (643:643:643)) - (PORT datad (551:551:551) (647:647:647)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1150:1150:1150) (1360:1360:1360)) - (PORT datab (237:237:237) (277:277:277)) - (PORT datac (560:560:560) (651:651:651)) - (PORT datad (490:490:490) (579:579:579)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~1) - (DELAY - (ABSOLUTE - (PORT datac (908:908:908) (1064:1064:1064)) - (PORT datad (858:858:858) (1006:1006:1006)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) - (DELAY - (ABSOLUTE - (PORT dataa (543:543:543) (631:631:631)) - (PORT datab (650:650:650) (745:745:745)) - (PORT datac (1107:1107:1107) (1270:1270:1270)) - (PORT datad (361:361:361) (419:419:419)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (331:331:331) (396:396:396)) - (PORT datac (990:990:990) (1152:1152:1152)) - (PORT datad (339:339:339) (397:397:397)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (848:848:848) (992:992:992)) - (PORT datab (187:187:187) (227:227:227)) - (PORT datac (1177:1177:1177) (1366:1366:1366)) - (PORT datad (306:306:306) (360:360:360)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (491:491:491)) - (PORT datab (530:530:530) (620:620:620)) - (PORT datac (591:591:591) (686:686:686)) - (PORT datad (499:499:499) (600:600:600)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) - (DELAY - (ABSOLUTE - (PORT dataa (836:836:836) (969:969:969)) - (PORT datab (689:689:689) (813:813:813)) - (PORT datac (812:812:812) (946:946:946)) - (PORT datad (630:630:630) (718:718:718)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1014:1014:1014) (1193:1193:1193)) - (PORT datab (1143:1143:1143) (1332:1332:1332)) - (PORT datac (720:720:720) (823:823:823)) - (PORT datad (1122:1122:1122) (1302:1302:1302)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (753:753:753)) - (PORT datab (348:348:348) (399:399:399)) - (PORT datac (674:674:674) (787:787:787)) - (PORT datad (322:322:322) (364:364:364)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (711:711:711)) - (PORT datab (455:455:455) (523:523:523)) - (PORT datad (296:296:296) (342:342:342)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) - (DELAY - (ABSOLUTE - (PORT datac (989:989:989) (1149:1149:1149)) - (PORT datad (879:879:879) (1038:1038:1038)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~25) - (DELAY - (ABSOLUTE - (PORT dataa (563:563:563) (657:657:657)) - (PORT datab (587:587:587) (695:695:695)) - (PORT datac (594:594:594) (709:709:709)) - (PORT datad (341:341:341) (395:395:395)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (890:890:890) (1056:1056:1056)) - (PORT datab (106:106:106) (135:135:135)) - (PORT datac (595:595:595) (710:710:710)) - (PORT datad (1013:1013:1013) (1180:1180:1180)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (663:663:663) (770:770:770)) - (PORT datab (362:362:362) (426:426:426)) - (PORT datac (716:716:716) (846:846:846)) - (PORT datad (886:886:886) (1036:1036:1036)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (111:111:111) (142:142:142)) - (PORT datac (714:714:714) (844:844:844)) - (PORT datad (888:888:888) (1038:1038:1038)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (689:689:689) (789:789:789)) - (PORT datab (900:900:900) (1019:1019:1019)) - (PORT datac (423:423:423) (478:478:478)) - (PORT datad (317:317:317) (366:366:366)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (327:327:327) (387:387:387)) - (PORT datab (361:361:361) (425:425:425)) - (PORT datac (382:382:382) (448:448:448)) - (PORT datad (467:467:467) (555:555:555)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) - (DELAY - (ABSOLUTE - (PORT dataa (547:547:547) (652:652:652)) - (PORT datab (912:912:912) (1061:1061:1061)) - (PORT datac (886:886:886) (1038:1038:1038)) - (PORT datad (539:539:539) (626:626:626)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) - (DELAY - (ABSOLUTE - (PORT dataa (718:718:718) (837:837:837)) - (PORT datab (509:509:509) (594:594:594)) - (PORT datac (543:543:543) (642:642:642)) - (PORT datad (632:632:632) (725:725:725)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (223:223:223)) - (PORT datab (807:807:807) (925:925:925)) - (PORT datac (598:598:598) (678:678:678)) - (PORT datad (743:743:743) (846:846:846)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (225:225:225)) - (PORT datab (126:126:126) (154:154:154)) - (PORT datac (581:581:581) (690:690:690)) - (PORT datad (768:768:768) (885:885:885)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (474:474:474) (543:543:543)) - (PORT datab (190:190:190) (228:228:228)) - (PORT datac (365:365:365) (419:419:419)) - (PORT datad (449:449:449) (521:521:521)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (485:485:485)) - (PORT datab (522:522:522) (616:616:616)) - (PORT datac (534:534:534) (632:632:632)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (959:959:959)) - (PORT datab (327:327:327) (388:388:388)) - (PORT datac (677:677:677) (785:785:785)) - (PORT datad (447:447:447) (511:511:511)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (152:152:152)) - (PORT datab (110:110:110) (141:141:141)) - (PORT datac (309:309:309) (352:352:352)) - (PORT datad (464:464:464) (538:538:538)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (774:774:774)) - (PORT datab (537:537:537) (628:628:628)) - (PORT datac (608:608:608) (716:716:716)) - (PORT datad (810:810:810) (922:922:922)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (741:741:741)) - (PORT datab (543:543:543) (635:635:635)) - (PORT datac (158:158:158) (190:190:190)) - (PORT datad (346:346:346) (400:400:400)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (674:674:674)) - (PORT datab (761:761:761) (862:862:862)) - (PORT datac (650:650:650) (750:750:750)) - (PORT datad (664:664:664) (763:763:763)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (142:142:142)) - (PORT datab (684:684:684) (790:790:790)) - (PORT datac (553:553:553) (651:651:651)) - (PORT datad (344:344:344) (398:398:398)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (546:546:546)) - (PORT datab (793:793:793) (910:910:910)) - (PORT datac (931:931:931) (1064:1064:1064)) - (PORT datad (1156:1156:1156) (1339:1339:1339)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (333:333:333) (390:390:390)) - (PORT datab (111:111:111) (142:142:142)) - (PORT datac (802:802:802) (918:918:918)) - (PORT datad (792:792:792) (911:911:911)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1014:1014:1014) (1189:1189:1189)) - (PORT datab (452:452:452) (517:517:517)) - (PORT datac (459:459:459) (521:521:521)) - (PORT datad (1156:1156:1156) (1340:1340:1340)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (439:439:439) (511:511:511)) - (PORT datab (419:419:419) (486:486:486)) - (PORT datac (88:88:88) (110:110:110)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (178:178:178) (218:218:218)) - (PORT datab (115:115:115) (144:144:144)) - (PORT datac (103:103:103) (125:125:125)) - (PORT datad (287:287:287) (330:330:330)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (530:530:530) (618:618:618)) - (PORT datab (463:463:463) (527:527:527)) - (PORT datac (958:958:958) (1116:1116:1116)) - (PORT datad (640:640:640) (747:747:747)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (831:831:831)) - (PORT datab (658:658:658) (760:760:760)) - (PORT datac (619:619:619) (706:706:706)) - (PORT datad (370:370:370) (438:438:438)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (763:763:763)) - (PORT datac (314:314:314) (366:366:366)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (757:757:757)) - (PORT datab (349:349:349) (411:411:411)) - (PORT datac (103:103:103) (133:133:133)) - (PORT datad (329:329:329) (379:379:379)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (153:153:153)) - (PORT datac (1178:1178:1178) (1367:1367:1367)) - (PORT datad (827:827:827) (965:965:965)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (266:266:266)) - (PORT datab (640:640:640) (738:738:738)) - (PORT datac (814:814:814) (949:949:949)) - (PORT datad (618:618:618) (707:707:707)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (623:623:623) (739:739:739)) - (PORT datab (588:588:588) (702:702:702)) - (PORT datac (650:650:650) (750:750:750)) - (PORT datad (663:663:663) (763:763:763)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (476:476:476) (540:540:540)) - (PORT datab (362:362:362) (423:423:423)) - (PORT datac (598:598:598) (686:686:686)) - (PORT datad (410:410:410) (473:473:473)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (704:704:704)) - (PORT datab (881:881:881) (1027:1027:1027)) - (PORT datac (339:339:339) (403:403:403)) - (PORT datad (97:97:97) (117:117:117)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (404:404:404) (469:469:469)) - (PORT datab (459:459:459) (531:531:531)) - (PORT datac (429:429:429) (487:487:487)) - (PORT datad (362:362:362) (424:424:424)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~9) - (DELAY - (ABSOLUTE - (PORT dataa (577:577:577) (675:675:675)) - (PORT datab (541:541:541) (634:634:634)) - (PORT datac (101:101:101) (122:122:122)) - (PORT datad (810:810:810) (922:922:922)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (859:859:859)) - (PORT datab (541:541:541) (633:633:633)) - (PORT datac (608:608:608) (717:717:717)) - (PORT datad (875:875:875) (1029:1029:1029)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (859:859:859)) - (PORT datab (684:684:684) (790:790:790)) - (PORT datac (553:553:553) (651:651:651)) - (PORT datad (875:875:875) (1030:1030:1030)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datac (92:92:92) (115:115:115)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (295:295:295) (341:341:341)) - (PORT datab (127:127:127) (161:161:161)) - (PORT datac (282:282:282) (323:323:323)) - (PORT datad (801:801:801) (933:933:933)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (735:735:735) (853:853:853)) - (PORT datac (296:296:296) (342:342:342)) - (PORT datad (313:313:313) (366:366:366)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (448:448:448)) - (PORT datab (608:608:608) (701:701:701)) - (PORT datac (519:519:519) (611:611:611)) - (PORT datad (647:647:647) (744:744:744)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (516:516:516) (609:609:609)) - (PORT datab (533:533:533) (618:618:618)) - (PORT datac (671:671:671) (792:792:792)) - (PORT datad (199:199:199) (230:230:230)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) - (DELAY - (ABSOLUTE - (PORT dataa (971:971:971) (1110:1110:1110)) - (PORT datab (896:896:896) (1028:1028:1028)) - (PORT datac (730:730:730) (858:858:858)) - (PORT datad (881:881:881) (1044:1044:1044)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (704:704:704)) - (PORT datab (597:597:597) (694:694:694)) - (PORT datac (528:528:528) (615:615:615)) - (PORT datad (438:438:438) (504:504:504)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (543:543:543) (639:639:639)) - (PORT datab (374:374:374) (440:440:440)) - (PORT datac (115:115:115) (143:143:143)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (463:463:463) (536:536:536)) - (PORT datab (349:349:349) (410:410:410)) - (PORT datac (485:485:485) (557:557:557)) - (PORT datad (444:444:444) (508:508:508)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (186:186:186) (226:226:226)) - (PORT datac (556:556:556) (646:646:646)) - (PORT datad (305:305:305) (359:359:359)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (147:147:147)) - (PORT datac (952:952:952) (1085:1085:1085)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (129:129:129) (165:165:165)) - (PORT datab (654:654:654) (759:759:759)) - (PORT datac (672:672:672) (775:775:775)) - (PORT datad (283:283:283) (329:329:329)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (705:705:705)) - (PORT datab (132:132:132) (166:166:166)) - (PORT datac (484:484:484) (566:566:566)) - (PORT datad (1090:1090:1090) (1242:1242:1242)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (440:440:440) (509:509:509)) - (PORT datab (459:459:459) (533:533:533)) - (PORT datac (305:305:305) (363:363:363)) - (PORT datad (437:437:437) (496:496:496)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1198:1198:1198) (1392:1392:1392)) - (PORT datab (994:994:994) (1150:1150:1150)) - (PORT datac (474:474:474) (554:554:554)) - (PORT datad (1331:1331:1331) (1541:1541:1541)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (536:536:536) (632:632:632)) - (PORT datab (1179:1179:1179) (1363:1363:1363)) - (PORT datac (287:287:287) (333:333:333)) - (PORT datad (1092:1092:1092) (1271:1271:1271)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~54) - (DELAY - (ABSOLUTE - (PORT dataa (988:988:988) (1156:1156:1156)) - (PORT datab (631:631:631) (745:745:745)) - (PORT datac (542:542:542) (622:622:622)) - (PORT datad (1123:1123:1123) (1309:1309:1309)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (789:789:789)) - (PORT datab (648:648:648) (756:756:756)) - (PORT datac (320:320:320) (378:378:378)) - (PORT datad (1286:1286:1286) (1469:1469:1469)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (541:541:541) (627:627:627)) - (PORT datab (626:626:626) (720:720:720)) - (PORT datac (181:181:181) (222:222:222)) - (PORT datad (341:341:341) (406:406:406)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (465:465:465) (548:548:548)) - (PORT datac (464:464:464) (528:528:528)) - (PORT datad (279:279:279) (316:316:316)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (129:129:129) (165:165:165)) - (PORT datab (133:133:133) (168:168:168)) - (PORT datac (1121:1121:1121) (1299:1299:1299)) - (PORT datad (107:107:107) (132:132:132)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (188:188:188) (193:193:193)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) - (DELAY - (ABSOLUTE - (PORT dataa (767:767:767) (919:919:919)) - (PORT datab (731:731:731) (841:841:841)) - (PORT datac (471:471:471) (548:548:548)) - (PORT datad (816:816:816) (944:944:944)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (753:753:753)) - (PORT datab (386:386:386) (461:461:461)) - (PORT datac (538:538:538) (632:632:632)) - (PORT datad (327:327:327) (376:376:376)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (336:336:336) (390:390:390)) - (PORT datab (545:545:545) (654:654:654)) - (PORT datac (970:970:970) (1135:1135:1135)) - (PORT datad (621:621:621) (720:720:720)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1098:1098:1098) (1260:1260:1260)) - (PORT datab (471:471:471) (556:556:556)) - (PORT datac (765:765:765) (900:900:900)) - (PORT datad (784:784:784) (899:899:899)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (321:321:321) (381:381:381)) - (PORT datab (594:594:594) (706:706:706)) - (PORT datac (109:109:109) (135:135:135)) - (PORT datad (488:488:488) (568:568:568)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) - (DELAY - (ABSOLUTE - (PORT dataa (319:319:319) (374:374:374)) - (PORT datab (105:105:105) (135:135:135)) - (PORT datac (482:482:482) (557:557:557)) - (PORT datad (463:463:463) (533:533:533)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (967:967:967) (1114:1114:1114)) - (PORT datab (591:591:591) (723:723:723)) - (PORT datac (676:676:676) (794:794:794)) - (PORT datad (467:467:467) (542:542:542)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (450:450:450)) - (PORT datab (648:648:648) (760:760:760)) - (PORT datac (824:824:824) (943:943:943)) - (PORT datad (832:832:832) (958:958:958)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (463:463:463) (539:539:539)) - (PORT datab (747:747:747) (852:852:852)) - (PORT datac (415:415:415) (480:480:480)) - (PORT datad (970:970:970) (1105:1105:1105)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel3) - (DELAY - (ABSOLUTE - (PORT dataa (770:770:770) (910:910:910)) - (PORT datab (1305:1305:1305) (1522:1522:1522)) - (PORT datac (615:615:615) (716:716:716)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (531:531:531) (624:624:624)) - (PORT datab (567:567:567) (659:659:659)) - (PORT datac (96:96:96) (120:120:120)) - (PORT datad (354:354:354) (414:414:414)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (310:310:310) (369:369:369)) - (PORT datab (369:369:369) (432:432:432)) - (PORT datac (264:264:264) (301:301:301)) - (PORT datad (463:463:463) (533:533:533)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (144:144:144)) - (PORT datab (486:486:486) (561:561:561)) - (PORT datac (485:485:485) (559:559:559)) - (PORT datad (96:96:96) (116:116:116)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel0) - (DELAY - (ABSOLUTE - (PORT dataa (1255:1255:1255) (1469:1469:1469)) - (PORT datac (812:812:812) (947:947:947)) - (PORT datad (1276:1276:1276) (1472:1472:1472)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) - (DELAY - (ABSOLUTE - (PORT datab (530:530:530) (627:627:627)) - (PORT datac (861:861:861) (1011:1011:1011)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (380:380:380) (446:446:446)) - (PORT datab (460:460:460) (536:536:536)) - (PORT datac (734:734:734) (872:872:872)) - (PORT datad (483:483:483) (564:564:564)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (835:835:835) (964:964:964)) - (PORT datab (107:107:107) (136:136:136)) - (PORT datac (572:572:572) (655:655:655)) - (PORT datad (573:573:573) (670:670:670)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (124:124:124) (160:160:160)) - (PORT datab (190:190:190) (227:227:227)) - (PORT datac (331:331:331) (387:387:387)) - (PORT datad (106:106:106) (129:129:129)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~11) - (DELAY - (ABSOLUTE - (PORT dataa (923:923:923) (1088:1088:1088)) - (PORT datab (874:874:874) (1029:1029:1029)) - (PORT datac (978:978:978) (1128:1128:1128)) - (PORT datad (817:817:817) (933:933:933)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (992:992:992) (1133:1133:1133)) - (PORT datab (370:370:370) (439:439:439)) - (PORT datac (287:287:287) (334:334:334)) - (PORT datad (622:622:622) (722:722:722)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (389:389:389) (463:463:463)) - (PORT datab (555:555:555) (664:664:664)) - (PORT datac (101:101:101) (121:121:121)) - (PORT datad (716:716:716) (833:833:833)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (313:313:313) (368:368:368)) - (PORT datab (477:477:477) (554:554:554)) - (PORT datac (175:175:175) (209:209:209)) - (PORT datad (384:384:384) (454:454:454)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (422:422:422)) - (PORT datab (530:530:530) (611:611:611)) - (PORT datac (315:315:315) (365:365:365)) - (PORT datad (356:356:356) (417:417:417)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (705:705:705)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (298:298:298) (348:348:348)) - (PORT datad (94:94:94) (114:114:114)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe) - (DELAY - (ABSOLUTE - (PORT dataa (205:205:205) (283:283:283)) - (PORT datab (723:723:723) (852:852:852)) - (PORT datac (383:383:383) (464:464:464)) - (PORT datad (731:731:731) (868:868:868)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) - (DELAY - (ABSOLUTE - (PORT dataa (886:886:886) (1020:1020:1020)) - (PORT datab (492:492:492) (582:582:582)) - (PORT datac (706:706:706) (818:818:818)) - (PORT datad (917:917:917) (1048:1048:1048)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (229:229:229)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datac (366:366:366) (437:437:437)) - (PORT datad (918:918:918) (1050:1050:1050)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (741:741:741) (866:866:866)) - (PORT datab (663:663:663) (763:763:763)) - (PORT datac (634:634:634) (740:740:740)) - (PORT datad (752:752:752) (892:892:892)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (561:561:561)) - (PORT datab (193:193:193) (235:235:235)) - (PORT datac (360:360:360) (431:431:431)) - (PORT datad (661:661:661) (765:765:765)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (672:672:672)) - (PORT datab (482:482:482) (567:567:567)) - (PORT datac (579:579:579) (678:678:678)) - (PORT datad (481:481:481) (566:566:566)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (138:138:138)) - (PORT datab (534:534:534) (641:641:641)) - (PORT datac (469:469:469) (537:537:537)) - (PORT datad (501:501:501) (584:584:584)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) - (DELAY - (ABSOLUTE - (PORT dataa (544:544:544) (649:649:649)) - (PORT datab (658:658:658) (766:766:766)) - (PORT datac (883:883:883) (1035:1035:1035)) - (PORT datad (636:636:636) (741:741:741)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (405:405:405)) - (PORT datab (1177:1177:1177) (1396:1396:1396)) - (PORT datac (470:470:470) (542:542:542)) - (PORT datad (682:682:682) (803:803:803)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) - (DELAY - (ABSOLUTE - (PORT dataa (492:492:492) (578:578:578)) - (PORT datab (477:477:477) (561:561:561)) - (PORT datac (603:603:603) (695:695:695)) - (PORT datad (482:482:482) (568:568:568)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~92) - (DELAY - (ABSOLUTE - (PORT dataa (573:573:573) (682:682:682)) - (PORT datab (908:908:908) (1071:1071:1071)) - (PORT datac (341:341:341) (391:391:391)) - (PORT datad (959:959:959) (1118:1118:1118)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1348:1348:1348) (1572:1572:1572)) - (PORT datab (930:930:930) (1114:1114:1114)) - (PORT datac (515:515:515) (597:597:597)) - (PORT datad (376:376:376) (440:440:440)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (568:568:568) (676:676:676)) - (PORT datad (880:880:880) (1030:1030:1030)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) - (DELAY - (ABSOLUTE - (PORT dataa (742:742:742) (866:866:866)) - (PORT datab (360:360:360) (425:425:425)) - (PORT datac (754:754:754) (862:862:862)) - (PORT datad (479:479:479) (556:556:556)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~93) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (720:720:720)) - (PORT datab (973:973:973) (1143:1143:1143)) - (PORT datac (891:891:891) (1050:1050:1050)) - (PORT datad (559:559:559) (657:657:657)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) - (DELAY - (ABSOLUTE - (PORT dataa (772:772:772) (924:924:924)) - (PORT datab (455:455:455) (530:530:530)) - (PORT datac (609:609:609) (694:694:694)) - (PORT datad (355:355:355) (422:422:422)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~24) - (DELAY - (ABSOLUTE - (PORT datab (653:653:653) (759:759:759)) - (PORT datac (103:103:103) (124:124:124)) - (PORT datad (97:97:97) (117:117:117)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (466:466:466) (543:543:543)) - (PORT datac (103:103:103) (131:131:131)) - (PORT datad (372:372:372) (448:448:448)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) - (DELAY - (ABSOLUTE - (PORT dataa (541:541:541) (637:637:637)) - (PORT datab (518:518:518) (603:603:603)) - (PORT datac (782:782:782) (906:906:906)) - (PORT datad (285:285:285) (323:323:323)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (317:317:317) (373:373:373)) - (PORT datab (472:472:472) (548:548:548)) - (PORT datac (768:768:768) (902:902:902)) - (PORT datad (837:837:837) (992:992:992)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (510:510:510) (605:605:605)) - (PORT datab (478:478:478) (562:562:562)) - (PORT datac (502:502:502) (594:594:594)) - (PORT datad (861:861:861) (1018:1018:1018)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (735:735:735)) - (PORT datab (345:345:345) (419:419:419)) - (PORT datac (496:496:496) (578:578:578)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) - (DELAY - (ABSOLUTE - (PORT datab (841:841:841) (988:988:988)) - (PORT datac (974:974:974) (1125:1125:1125)) - (PORT datad (587:587:587) (666:666:666)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (441:441:441)) - (PORT datab (657:657:657) (752:752:752)) - (PORT datac (468:468:468) (540:540:540)) - (PORT datad (660:660:660) (773:773:773)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (504:504:504) (595:595:595)) - (PORT datab (520:520:520) (613:613:613)) - (PORT datac (345:345:345) (409:409:409)) - (PORT datad (629:629:629) (732:732:732)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) - (DELAY - (ABSOLUTE - (PORT datab (476:476:476) (555:555:555)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (465:465:465) (535:535:535)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (558:558:558) (633:633:633)) - (PORT datab (811:811:811) (939:939:939)) - (PORT datac (711:711:711) (816:816:816)) - (PORT datad (463:463:463) (532:532:532)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (943:943:943) (1083:1083:1083)) - (PORT datab (919:919:919) (1069:1069:1069)) - (PORT datac (837:837:837) (986:986:986)) - (PORT datad (465:465:465) (533:533:533)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (936:936:936)) - (PORT datab (920:920:920) (1071:1071:1071)) - (PORT datac (925:925:925) (1058:1058:1058)) - (PORT datad (655:655:655) (760:760:760)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (576:576:576)) - (PORT datab (318:318:318) (370:370:370)) - (PORT datac (836:836:836) (966:966:966)) - (PORT datad (306:306:306) (350:350:350)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (516:516:516) (597:597:597)) - (PORT datab (500:500:500) (584:584:584)) - (PORT datac (481:481:481) (564:564:564)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~94) - (DELAY - (ABSOLUTE - (PORT dataa (1015:1015:1015) (1177:1177:1177)) - (PORT datab (971:971:971) (1140:1140:1140)) - (PORT datac (892:892:892) (1051:1051:1051)) - (PORT datad (561:561:561) (658:658:658)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (1090:1090:1090)) - (PORT datac (1406:1406:1406) (1623:1623:1623)) - (PORT datad (835:835:835) (990:990:990)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (733:733:733)) - (PORT datab (652:652:652) (753:753:753)) - (PORT datac (103:103:103) (124:124:124)) - (PORT datad (469:469:469) (539:539:539)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT datab (365:365:365) (434:434:434)) - (PORT datac (201:201:201) (241:241:241)) - (PORT datad (107:107:107) (127:127:127)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) - (DELAY - (ABSOLUTE - (PORT dataa (239:239:239) (285:285:285)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (432:432:432) (496:496:496)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (236:236:236)) - (PORT datab (480:480:480) (553:553:553)) - (PORT datac (336:336:336) (397:397:397)) - (PORT datad (667:667:667) (771:771:771)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (709:709:709) (831:831:831)) - (PORT datab (935:935:935) (1119:1119:1119)) - (PORT datac (518:518:518) (601:601:601)) - (PORT datad (517:517:517) (606:606:606)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~6) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (960:960:960)) - (PORT datab (959:959:959) (1114:1114:1114)) - (PORT datac (446:446:446) (515:515:515)) - (PORT datad (358:358:358) (424:424:424)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_exx\~2) - (DELAY - (ABSOLUTE - (PORT dataa (787:787:787) (943:943:943)) - (PORT datab (491:491:491) (569:569:569)) - (PORT datad (1310:1310:1310) (1532:1532:1532)) - (IOPATH dataa combout (159:159:159) (173:173:173)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_exx) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (914:914:914) (898:898:898)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (739:739:739)) - (PORT datab (660:660:660) (759:759:759)) - (PORT datad (671:671:671) (796:796:796)) - (IOPATH dataa combout (192:192:192) (184:184:184)) - (IOPATH datab combout (182:182:182) (193:193:193)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de1) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (929:929:929) (911:911:911)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (514:514:514) (597:597:597)) - (PORT datab (1135:1135:1135) (1296:1296:1296)) - (PORT datac (427:427:427) (493:493:493)) - (PORT datad (177:177:177) (207:207:207)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (503:503:503) (593:593:593)) - (PORT datab (953:953:953) (1084:1084:1084)) - (PORT datac (698:698:698) (818:818:818)) - (PORT datad (630:630:630) (733:733:733)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (472:472:472)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (698:698:698) (819:819:819)) - (PORT datad (863:863:863) (1020:1020:1020)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (793:793:793)) - (PORT datab (732:732:732) (861:861:861)) - (PORT datac (629:629:629) (733:733:733)) - (PORT datad (403:403:403) (485:485:485)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (395:395:395)) - (PORT datab (308:308:308) (356:356:356)) - (PORT datac (494:494:494) (576:576:576)) - (PORT datad (981:981:981) (1128:1128:1128)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (514:514:514) (597:597:597)) - (PORT datab (186:186:186) (222:222:222)) - (PORT datac (645:645:645) (746:746:746)) - (PORT datad (1145:1145:1145) (1339:1339:1339)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (175:175:175) (212:212:212)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (489:489:489) (568:568:568)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (549:549:549) (652:652:652)) - (PORT datab (518:518:518) (615:615:615)) - (PORT datac (584:584:584) (657:657:657)) - (PORT datad (581:581:581) (648:648:648)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (762:762:762) (897:897:897)) - (PORT datab (498:498:498) (585:585:585)) - (PORT datac (356:356:356) (420:420:420)) - (PORT datad (635:635:635) (739:739:739)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1149:1149:1149) (1325:1325:1325)) - (PORT datac (919:919:919) (1039:1039:1039)) - (PORT datad (967:967:967) (1114:1114:1114)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~2) - (DELAY - (ABSOLUTE - (PORT dataa (565:565:565) (657:657:657)) - (PORT datab (729:729:729) (840:840:840)) - (PORT datac (765:765:765) (881:881:881)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~19) - (DELAY - (ABSOLUTE - (PORT datab (355:355:355) (410:410:410)) - (PORT datac (347:347:347) (408:408:408)) - (PORT datad (506:506:506) (589:589:589)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (418:418:418)) - (PORT datab (384:384:384) (447:447:447)) - (PORT datac (369:369:369) (448:448:448)) - (PORT datad (440:440:440) (506:506:506)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (458:458:458) (541:541:541)) - (PORT datac (1089:1089:1089) (1248:1248:1248)) - (PORT datad (106:106:106) (130:130:130)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (408:408:408)) - (PORT datab (484:484:484) (566:566:566)) - (PORT datac (603:603:603) (690:690:690)) - (PORT datad (450:450:450) (521:521:521)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (734:734:734)) - (PORT datab (567:567:567) (668:668:668)) - (PORT datac (770:770:770) (894:894:894)) - (PORT datad (106:106:106) (131:131:131)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (736:736:736)) - (PORT datab (1101:1101:1101) (1277:1277:1277)) - (PORT datac (627:627:627) (722:722:722)) - (PORT datad (523:523:523) (615:615:615)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (104:104:104) (134:134:134)) - (PORT datac (1507:1507:1507) (1752:1752:1752)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (522:522:522) (627:627:627)) - (PORT datac (614:614:614) (716:716:716)) - (PORT datad (629:629:629) (727:727:727)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) - (DELAY - (ABSOLUTE - (PORT dataa (545:545:545) (627:627:627)) - (PORT datab (449:449:449) (517:517:517)) - (PORT datac (1117:1117:1117) (1276:1276:1276)) - (PORT datad (774:774:774) (885:885:885)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (902:902:902) (1057:1057:1057)) - (PORT datab (498:498:498) (586:586:586)) - (PORT datac (510:510:510) (598:598:598)) - (PORT datad (857:857:857) (1010:1010:1010)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (407:407:407)) - (PORT datab (461:461:461) (537:537:537)) - (PORT datac (338:338:338) (398:398:398)) - (PORT datad (435:435:435) (494:494:494)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (758:758:758)) - (PORT datac (784:784:784) (900:900:900)) - (PORT datad (1170:1170:1170) (1359:1359:1359)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (506:506:506) (599:599:599)) - (PORT datab (901:901:901) (1063:1063:1063)) - (PORT datac (114:114:114) (141:141:141)) - (PORT datad (334:334:334) (384:384:384)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (761:761:761) (889:889:889)) - (PORT datab (330:330:330) (387:387:387)) - (PORT datac (415:415:415) (481:481:481)) - (PORT datad (318:318:318) (369:369:369)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (1074:1074:1074)) - (PORT datab (609:609:609) (691:691:691)) - (PORT datac (596:596:596) (705:705:705)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (743:743:743) (891:891:891)) - (PORT datab (106:106:106) (136:136:136)) - (PORT datac (325:325:325) (376:376:376)) - (PORT datad (819:819:819) (947:947:947)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (305:305:305) (357:357:357)) - (PORT datab (344:344:344) (408:408:408)) - (PORT datac (325:325:325) (383:383:383)) - (PORT datad (304:304:304) (348:348:348)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1261:1261:1261) (1461:1461:1461)) - (PORT datab (140:140:140) (187:187:187)) - (PORT datac (637:637:637) (730:730:730)) - (PORT datad (128:128:128) (165:165:165)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (92:92:92) (116:116:116)) - (PORT datad (480:480:480) (556:556:556)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT datab (110:110:110) (140:140:140)) - (PORT datad (361:361:361) (422:422:422)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (152:152:152)) - (PORT datab (565:565:565) (667:667:667)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (387:387:387) (457:457:457)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (794:794:794)) - (PORT datac (495:495:495) (585:585:585)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~14) - (DELAY - (ABSOLUTE - (PORT datac (369:369:369) (448:448:448)) - (PORT datad (488:488:488) (560:560:560)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (803:803:803) (928:928:928)) - (PORT datab (331:331:331) (393:393:393)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (624:624:624) (709:709:709)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~47) - (DELAY - (ABSOLUTE - (PORT dataa (318:318:318) (371:371:371)) - (PORT datab (340:340:340) (397:397:397)) - (PORT datac (479:479:479) (553:553:553)) - (PORT datad (482:482:482) (556:556:556)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~48) - (DELAY - (ABSOLUTE - (PORT dataa (176:176:176) (219:219:219)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datac (335:335:335) (395:395:395)) - (PORT datad (573:573:573) (656:656:656)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1150:1150:1150) (1326:1326:1326)) - (PORT datac (919:919:919) (1039:1039:1039)) - (PORT datad (967:967:967) (1114:1114:1114)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (765:765:765) (907:907:907)) - (PORT datab (604:604:604) (690:690:690)) - (PORT datac (516:516:516) (599:599:599)) - (PORT datad (293:293:293) (334:334:334)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (122:122:122) (156:156:156)) - (PORT datab (120:120:120) (150:150:150)) - (PORT datac (654:654:654) (762:762:762)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (515:515:515)) - (PORT datab (712:712:712) (832:832:832)) - (PORT datac (1031:1031:1031) (1187:1187:1187)) - (PORT datad (1174:1174:1174) (1364:1364:1364)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (328:328:328) (385:385:385)) - (PORT datac (305:305:305) (362:362:362)) - (PORT datad (463:463:463) (529:529:529)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) - (DELAY - (ABSOLUTE - (PORT dataa (771:771:771) (923:923:923)) - (PORT datab (414:414:414) (500:500:500)) - (PORT datac (475:475:475) (552:552:552)) - (PORT datad (502:502:502) (582:582:582)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) - (DELAY - (ABSOLUTE - (PORT dataa (471:471:471) (542:542:542)) - (PORT datab (383:383:383) (458:458:458)) - (PORT datac (538:538:538) (636:636:636)) - (PORT datad (996:996:996) (1148:1148:1148)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) - (DELAY - (ABSOLUTE - (PORT dataa (704:704:704) (836:836:836)) - (PORT datab (488:488:488) (567:567:567)) - (PORT datac (342:342:342) (392:392:392)) - (PORT datad (963:963:963) (1107:1107:1107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) - (DELAY - (ABSOLUTE - (PORT dataa (773:773:773) (926:926:926)) - (PORT datab (366:366:366) (431:431:431)) - (PORT datac (477:477:477) (555:555:555)) - (PORT datad (199:199:199) (229:229:229)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) - (DELAY - (ABSOLUTE - (PORT dataa (500:500:500) (582:582:582)) - (PORT datab (386:386:386) (461:461:461)) - (PORT datac (547:547:547) (642:642:642)) - (PORT datad (335:335:335) (387:387:387)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (823:823:823) (941:941:941)) - (PORT datab (505:505:505) (589:589:589)) - (PORT datac (100:100:100) (122:122:122)) - (PORT datad (789:789:789) (906:906:906)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (1060:1060:1060)) - (PORT datab (872:872:872) (999:999:999)) - (PORT datac (560:560:560) (651:651:651)) - (PORT datad (878:878:878) (1014:1014:1014)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (954:954:954)) - (PORT datab (516:516:516) (618:618:618)) - (PORT datac (467:467:467) (556:556:556)) - (PORT datad (307:307:307) (356:356:356)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (818:818:818) (950:950:950)) - (PORT datab (517:517:517) (619:619:619)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (505:505:505) (591:591:591)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (309:309:309) (359:359:359)) - (PORT datab (475:475:475) (554:554:554)) - (PORT datac (449:449:449) (536:536:536)) - (PORT datad (442:442:442) (526:526:526)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (406:406:406)) - (PORT datab (127:127:127) (160:160:160)) - (PORT datac (739:739:739) (871:871:871)) - (PORT datad (1224:1224:1224) (1419:1419:1419)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1024:1024:1024) (1204:1204:1204)) - (PORT datab (900:900:900) (1065:1065:1065)) - (PORT datac (729:729:729) (864:864:864)) - (PORT datad (1439:1439:1439) (1664:1664:1664)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (825:825:825)) - (PORT datab (461:461:461) (536:536:536)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (313:313:313) (365:365:365)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (958:958:958)) - (PORT datab (143:143:143) (176:176:176)) - (PORT datac (676:676:676) (784:784:784)) - (PORT datad (447:447:447) (511:511:511)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~2) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (573:573:573)) - (PORT datab (480:480:480) (559:559:559)) - (PORT datac (464:464:464) (541:541:541)) - (PORT datad (488:488:488) (587:587:587)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (465:465:465) (554:554:554)) - (PORT datab (510:510:510) (610:610:610)) - (PORT datac (102:102:102) (128:128:128)) - (PORT datad (653:653:653) (748:748:748)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (920:920:920)) - (PORT datab (842:842:842) (981:981:981)) - (PORT datac (610:610:610) (703:703:703)) - (PORT datad (212:212:212) (252:252:252)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (483:483:483) (570:570:570)) - (PORT datab (482:482:482) (561:561:561)) - (PORT datac (467:467:467) (545:545:545)) - (PORT datad (490:490:490) (589:589:589)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (398:398:398) (489:489:489)) - (PORT datab (437:437:437) (539:539:539)) - (PORT datad (641:641:641) (743:743:743)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (316:316:316) (369:369:369)) - (PORT datab (640:640:640) (739:739:739)) - (PORT datac (472:472:472) (550:550:550)) - (PORT datad (504:504:504) (582:582:582)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~15) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (958:958:958)) - (PORT datab (461:461:461) (536:536:536)) - (PORT datac (714:714:714) (822:822:822)) - (PORT datad (879:879:879) (1038:1038:1038)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (849:849:849) (998:998:998)) - (PORT datab (789:789:789) (902:902:902)) - (PORT datac (816:816:816) (958:958:958)) - (PORT datad (214:214:214) (254:254:254)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (564:564:564) (655:655:655)) - (PORT datac (425:425:425) (486:486:486)) - (PORT datad (548:548:548) (625:625:625)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (132:132:132)) - (PORT datab (214:214:214) (257:257:257)) - (PORT datac (547:547:547) (625:625:625)) - (PORT datad (96:96:96) (116:116:116)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (175:175:175) (212:212:212)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (320:320:320) (367:367:367)) - (PORT datad (862:862:862) (1021:1021:1021)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (687:687:687) (788:788:788)) - (PORT datab (680:680:680) (797:797:797)) - (PORT datac (492:492:492) (568:568:568)) - (PORT datad (877:877:877) (1018:1018:1018)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (459:459:459) (542:542:542)) - (PORT datab (119:119:119) (152:152:152)) - (PORT datac (654:654:654) (764:764:764)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (1081:1081:1081)) - (PORT datab (921:921:921) (1072:1072:1072)) - (PORT datac (838:838:838) (987:987:987)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (523:523:523) (628:628:628)) - (PORT datab (108:108:108) (138:138:138)) - (PORT datac (666:666:666) (777:777:777)) - (PORT datad (496:496:496) (567:567:567)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) - (DELAY - (ABSOLUTE - (PORT datab (660:660:660) (761:761:761)) - (PORT datac (678:678:678) (804:804:804)) - (PORT datad (424:424:424) (481:481:481)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) - (DELAY - (ABSOLUTE - (PORT dataa (483:483:483) (580:580:580)) - (PORT datab (502:502:502) (601:601:601)) - (PORT datac (628:628:628) (727:727:727)) - (PORT datad (200:200:200) (241:241:241)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (823:823:823)) - (PORT datab (657:657:657) (758:758:758)) - (PORT datac (626:626:626) (725:725:725)) - (PORT datad (423:423:423) (480:480:480)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) - (DELAY - (ABSOLUTE - (PORT dataa (138:138:138) (190:190:190)) - (PORT datab (119:119:119) (153:153:153)) - (PORT datac (178:178:178) (212:212:212)) - (PORT datad (681:681:681) (806:806:806)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (742:742:742)) - (PORT datab (658:658:658) (758:758:758)) - (PORT datad (677:677:677) (802:802:802)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (161:161:161) (174:174:174)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de2) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (929:929:929) (911:911:911)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (188:188:188) (231:231:231)) - (PORT datab (117:117:117) (151:151:151)) - (PORT datac (121:121:121) (164:164:164)) - (PORT datad (668:668:668) (791:791:791)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (297:297:297) (339:339:339)) - (PORT datab (567:567:567) (669:669:669)) - (PORT datac (175:175:175) (209:209:209)) - (PORT datad (384:384:384) (454:454:454)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (423:423:423)) - (PORT datab (975:975:975) (1126:1126:1126)) - (PORT datad (469:469:469) (536:536:536)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (1477:1477:1477) (1704:1704:1704)) - (PORT datab (970:970:970) (1139:1139:1139)) - (PORT datac (568:568:568) (656:656:656)) - (PORT datad (861:861:861) (996:996:996)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (153:153:153)) - (PORT datab (464:464:464) (548:548:548)) - (PORT datac (841:841:841) (978:978:978)) - (PORT datad (687:687:687) (788:788:788)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) - (DELAY - (ABSOLUTE - (PORT dataa (543:543:543) (626:626:626)) - (PORT datab (106:106:106) (137:137:137)) - (PORT datac (527:527:527) (615:615:615)) - (PORT datad (111:111:111) (132:132:132)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla30npla13M5T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (520:520:520) (613:613:613)) - (PORT datab (120:120:120) (154:154:154)) - (PORT datac (770:770:770) (895:895:895)) - (PORT datad (844:844:844) (974:974:974)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (737:737:737)) - (PORT datab (849:849:849) (985:985:985)) - (PORT datac (329:329:329) (386:386:386)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (224:224:224)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (89:89:89) (109:109:109)) - (PORT datad (93:93:93) (112:112:112)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (491:491:491) (573:573:573)) - (PORT datab (355:355:355) (418:418:418)) - (PORT datac (598:598:598) (686:686:686)) - (PORT datad (410:410:410) (473:473:473)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (923:923:923) (1088:1088:1088)) - (PORT datab (861:861:861) (993:993:993)) - (PORT datac (978:978:978) (1128:1128:1128)) - (PORT datad (577:577:577) (656:656:656)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1388:1388:1388)) - (PORT datab (845:845:845) (992:992:992)) - (PORT datac (835:835:835) (979:979:979)) - (PORT datad (1090:1090:1090) (1237:1237:1237)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (503:503:503) (596:596:596)) - (PORT datab (481:481:481) (558:558:558)) - (PORT datac (472:472:472) (562:562:562)) - (PORT datad (885:885:885) (1041:1041:1041)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (399:399:399)) - (PORT datab (369:369:369) (437:437:437)) - (PORT datac (514:514:514) (596:596:596)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (377:377:377) (447:447:447)) - (PORT datab (678:678:678) (781:781:781)) - (PORT datac (357:357:357) (421:421:421)) - (PORT datad (741:741:741) (871:871:871)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (767:767:767) (892:892:892)) - (PORT datab (350:350:350) (409:409:409)) - (PORT datac (717:717:717) (828:828:828)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (755:755:755)) - (PORT datab (1014:1014:1014) (1171:1171:1171)) - (PORT datad (550:550:550) (651:651:651)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (476:476:476) (561:561:561)) - (PORT datab (376:376:376) (446:446:446)) - (PORT datac (107:107:107) (130:130:130)) - (PORT datad (1233:1233:1233) (1400:1400:1400)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (687:687:687) (805:805:805)) - (PORT datab (841:841:841) (994:994:994)) - (PORT datac (668:668:668) (785:785:785)) - (PORT datad (675:675:675) (774:774:774)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1061:1061:1061) (1218:1218:1218)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (500:500:500) (596:596:596)) - (PORT datad (99:99:99) (120:120:120)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (324:324:324) (375:375:375)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (497:497:497) (568:568:568)) - (PORT datad (464:464:464) (555:555:555)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (469:469:469) (560:560:560)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datac (289:289:289) (340:340:340)) - (PORT datad (344:344:344) (402:402:402)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (458:458:458) (540:540:540)) - (PORT datac (112:112:112) (139:139:139)) - (PORT datad (106:106:106) (130:130:130)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (726:726:726) (837:837:837)) - (PORT datab (324:324:324) (381:381:381)) - (PORT datac (455:455:455) (526:526:526)) - (PORT datad (318:318:318) (373:373:373)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (791:791:791) (923:923:923)) - (PORT datab (495:495:495) (579:579:579)) - (PORT datac (643:643:643) (731:731:731)) - (PORT datad (660:660:660) (773:773:773)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (986:986:986) (1138:1138:1138)) - (PORT datab (445:445:445) (512:512:512)) - (PORT datac (1117:1117:1117) (1277:1277:1277)) - (PORT datad (1145:1145:1145) (1327:1327:1327)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~40) - (DELAY - (ABSOLUTE - (PORT dataa (514:514:514) (597:597:597)) - (PORT datab (619:619:619) (713:713:713)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (278:278:278) (330:330:330)) - (PORT datab (364:364:364) (430:430:430)) - (PORT datac (1103:1103:1103) (1260:1260:1260)) - (PORT datad (281:281:281) (320:320:320)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (498:498:498) (594:594:594)) - (PORT datac (94:94:94) (117:117:117)) - (PORT datad (103:103:103) (121:121:121)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (465:465:465) (539:539:539)) - (PORT datac (299:299:299) (348:348:348)) - (PORT datad (96:96:96) (116:116:116)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~93) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (774:774:774)) - (PORT datab (555:555:555) (630:630:630)) - (PORT datac (642:642:642) (731:731:731)) - (PORT datad (735:735:735) (845:845:845)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) - (DELAY - (ABSOLUTE - (PORT dataa (133:133:133) (185:185:185)) - (PORT datab (117:117:117) (150:150:150)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (668:668:668) (792:792:792)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) - (DELAY - (ABSOLUTE - (PORT datab (758:758:758) (873:873:873)) - (PORT datac (634:634:634) (722:722:722)) - (PORT datad (325:325:325) (377:377:377)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) - (DELAY - (ABSOLUTE - (PORT datac (504:504:504) (580:580:580)) - (PORT datad (733:733:733) (840:840:840)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (758:758:758)) - (PORT datab (118:118:118) (152:152:152)) - (PORT datac (631:631:631) (727:727:727)) - (PORT datad (374:374:374) (434:434:434)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (466:466:466)) - (PORT datab (817:817:817) (959:959:959)) - (PORT datac (634:634:634) (731:731:731)) - (PORT datad (107:107:107) (132:132:132)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (461:461:461)) - (PORT datab (821:821:821) (964:964:964)) - (PORT datac (628:628:628) (724:724:724)) - (PORT datad (103:103:103) (128:128:128)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) - (DELAY - (ABSOLUTE - (PORT dataa (743:743:743) (872:872:872)) - (PORT datab (472:472:472) (548:548:548)) - (PORT datac (1037:1037:1037) (1204:1204:1204)) - (PORT datad (878:878:878) (1011:1011:1011)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datad (467:467:467) (543:543:543)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) - (DELAY - (ABSOLUTE - (PORT dataa (547:547:547) (653:653:653)) - (PORT datab (349:349:349) (411:411:411)) - (PORT datac (514:514:514) (595:595:595)) - (PORT datad (833:833:833) (968:968:968)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (713:713:713)) - (PORT datab (399:399:399) (482:482:482)) - (PORT datac (817:817:817) (959:959:959)) - (PORT datad (835:835:835) (972:972:972)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (310:310:310) (366:366:366)) - (PORT datab (106:106:106) (137:137:137)) - (PORT datac (337:337:337) (397:397:397)) - (PORT datad (591:591:591) (668:668:668)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (241:241:241)) - (PORT datab (643:643:643) (746:746:746)) - (PORT datac (179:179:179) (217:217:217)) - (PORT datad (593:593:593) (677:677:677)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) - (DELAY - (ABSOLUTE - (PORT dataa (691:691:691) (814:814:814)) - (PORT datab (882:882:882) (1040:1040:1040)) - (PORT datac (1221:1221:1221) (1398:1398:1398)) - (PORT datad (597:597:597) (722:722:722)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) - (DELAY - (ABSOLUTE - (PORT dataa (521:521:521) (615:615:615)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (686:686:686) (808:808:808)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (398:398:398)) - (PORT datac (352:352:352) (414:414:414)) - (PORT datad (292:292:292) (332:332:332)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (736:736:736)) - (PORT datab (113:113:113) (146:146:146)) - (PORT datac (625:625:625) (721:721:721)) - (PORT datad (369:369:369) (429:429:429)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~2) - (DELAY - (ABSOLUTE - (PORT dataa (489:489:489) (571:571:571)) - (PORT datab (486:486:486) (563:563:563)) - (PORT datac (499:499:499) (608:608:608)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (447:447:447)) - (PORT datab (643:643:643) (742:742:742)) - (PORT datad (509:509:509) (596:596:596)) - (IOPATH dataa combout (159:159:159) (173:173:173)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_af) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (902:902:902)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (633:633:633) (736:736:736)) - (PORT datab (133:133:133) (182:182:182)) - (PORT datac (634:634:634) (730:730:730)) - (PORT datad (376:376:376) (436:436:436)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (432:432:432)) - (PORT datab (745:745:745) (856:856:856)) - (PORT datad (516:516:516) (594:594:594)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (736:736:736)) - (PORT datab (134:134:134) (183:183:183)) - (PORT datac (627:627:627) (723:723:723)) - (PORT datad (371:371:371) (431:431:431)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) - (DELAY - (ABSOLUTE - (PORT dataa (971:971:971) (1123:1123:1123)) - (PORT datab (648:648:648) (745:745:745)) - (PORT datad (431:431:431) (486:486:486)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (455:455:455)) - (PORT datab (502:502:502) (588:588:588)) - (PORT datac (1028:1028:1028) (1200:1200:1200)) - (PORT datad (612:612:612) (705:705:705)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (830:830:830) (978:978:978)) - (PORT datac (587:587:587) (665:665:665)) - (PORT datad (166:166:166) (198:198:198)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (904:904:904)) - (PORT datab (654:654:654) (760:760:760)) - (PORT datac (1151:1151:1151) (1341:1341:1341)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (747:747:747)) - (PORT datab (1147:1147:1147) (1325:1325:1325)) - (PORT datac (527:527:527) (620:620:620)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (484:484:484) (575:575:575)) - (PORT datab (853:853:853) (990:990:990)) - (PORT datac (714:714:714) (819:819:819)) - (PORT datad (469:469:469) (539:539:539)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) - (DELAY - (ABSOLUTE - (PORT datab (119:119:119) (149:149:149)) - (PORT datac (106:106:106) (129:129:129)) - (PORT datad (107:107:107) (125:125:125)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (914:914:914) (1068:1068:1068)) - (PORT datac (108:108:108) (134:134:134)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) - (DELAY - (ABSOLUTE - (PORT dataa (308:308:308) (364:364:364)) - (PORT datab (477:477:477) (553:553:553)) - (PORT datac (753:753:753) (873:873:873)) - (PORT datad (1084:1084:1084) (1240:1240:1240)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (117:117:117) (149:149:149)) - (PORT datab (1128:1128:1128) (1305:1305:1305)) - (PORT datac (431:431:431) (494:494:494)) - (PORT datad (102:102:102) (120:120:120)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (454:454:454)) - (PORT datab (808:808:808) (935:935:935)) - (PORT datac (188:188:188) (222:222:222)) - (PORT datad (640:640:640) (734:734:734)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (153:153:153)) - (PORT datab (293:293:293) (340:340:340)) - (PORT datac (435:435:435) (496:496:496)) - (PORT datad (315:315:315) (366:366:366)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (772:772:772)) - (PORT datab (310:310:310) (361:361:361)) - (PORT datac (359:359:359) (431:431:431)) - (PORT datad (462:462:462) (531:531:531)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (454:454:454)) - (PORT datab (649:649:649) (751:751:751)) - (PORT datac (659:659:659) (753:753:753)) - (PORT datad (314:314:314) (361:361:361)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) - (DELAY - (ABSOLUTE - (PORT dataa (482:482:482) (556:556:556)) - (PORT datab (677:677:677) (783:783:783)) - (PORT datac (489:489:489) (563:563:563)) - (PORT datad (354:354:354) (417:417:417)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) - (DELAY - (ABSOLUTE - (PORT dataa (310:310:310) (360:360:360)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) - (DELAY - (ABSOLUTE - (PORT dataa (498:498:498) (577:577:577)) - (PORT datab (676:676:676) (782:782:782)) - (PORT datac (191:191:191) (226:226:226)) - (PORT datad (639:639:639) (733:733:733)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (771:771:771)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (660:660:660) (754:754:754)) - (PORT datad (460:460:460) (530:530:530)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (141:141:141)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (360:360:360) (431:431:431)) - (PORT datad (467:467:467) (543:543:543)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (312:312:312) (370:370:370)) - (PORT datab (366:366:366) (434:434:434)) - (PORT datac (201:201:201) (241:241:241)) - (PORT datad (108:108:108) (128:128:128)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (322:322:322) (373:373:373)) - (PORT datac (272:272:272) (312:312:312)) - (PORT datad (473:473:473) (544:544:544)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (510:510:510) (595:595:595)) - (PORT datab (880:880:880) (1044:1044:1044)) - (PORT datac (767:767:767) (891:891:891)) - (PORT datad (106:106:106) (129:129:129)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (385:385:385)) - (PORT datab (535:535:535) (642:642:642)) - (PORT datac (970:970:970) (1136:1136:1136)) - (PORT datad (626:626:626) (726:726:726)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~49) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (712:712:712)) - (PORT datab (832:832:832) (978:978:978)) - (PORT datac (904:904:904) (1039:1039:1039)) - (PORT datad (643:643:643) (748:748:748)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (763:763:763) (875:875:875)) - (PORT datab (693:693:693) (802:802:802)) - (PORT datac (688:688:688) (789:789:789)) - (PORT datad (713:713:713) (830:830:830)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (717:717:717)) - (PORT datac (326:326:326) (385:385:385)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~28) - (DELAY - (ABSOLUTE - (PORT dataa (126:126:126) (161:161:161)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (623:623:623) (726:726:726)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~35) - (DELAY - (ABSOLUTE - (PORT datab (1124:1124:1124) (1293:1293:1293)) - (PORT datac (736:736:736) (840:840:840)) - (PORT datad (461:461:461) (530:530:530)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~36) - (DELAY - (ABSOLUTE - (PORT dataa (113:113:113) (147:147:147)) - (PORT datab (490:490:490) (568:568:568)) - (PORT datac (331:331:331) (391:391:391)) - (PORT datad (516:516:516) (598:598:598)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~5) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (973:973:973)) - (PORT datab (646:646:646) (742:742:742)) - (PORT datac (620:620:620) (707:707:707)) - (PORT datad (288:288:288) (330:330:330)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (392:392:392)) - (PORT datab (123:123:123) (154:154:154)) - (PORT datac (619:619:619) (716:716:716)) - (PORT datad (104:104:104) (121:121:121)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~29) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (1082:1082:1082)) - (PORT datab (563:563:563) (663:663:663)) - (PORT datac (574:574:574) (685:685:685)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (756:756:756)) - (PORT datab (861:861:861) (1015:1015:1015)) - (PORT datad (106:106:106) (124:124:124)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (481:481:481) (562:562:562)) - (PORT datab (304:304:304) (350:350:350)) - (PORT datac (309:309:309) (367:367:367)) - (PORT datad (316:316:316) (362:362:362)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~3) - (DELAY - (ABSOLUTE - (PORT dataa (671:671:671) (795:795:795)) - (PORT datab (730:730:730) (859:859:859)) - (PORT datac (626:626:626) (729:729:729)) - (PORT datad (399:399:399) (481:481:481)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (448:448:448)) - (PORT datab (713:713:713) (821:821:821)) - (PORT datac (662:662:662) (773:773:773)) - (PORT datad (928:928:928) (1065:1065:1065)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (585:585:585) (692:692:692)) - (PORT datab (490:490:490) (570:570:570)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (119:119:119) (137:137:137)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (581:581:581) (703:703:703)) - (PORT datac (1206:1206:1206) (1387:1387:1387)) - (PORT datad (371:371:371) (437:437:437)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (400:400:400) (473:473:473)) - (PORT datab (615:615:615) (712:712:712)) - (PORT datac (89:89:89) (109:109:109)) - (PORT datad (620:620:620) (713:713:713)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (566:566:566) (672:672:672)) - (PORT datab (349:349:349) (415:415:415)) - (PORT datac (559:559:559) (671:671:671)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (141:141:141)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (94:94:94) (118:118:118)) - (PORT datad (515:515:515) (599:599:599)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) - (DELAY - (ABSOLUTE - (PORT datab (152:152:152) (203:203:203)) - (PORT datac (130:130:130) (173:173:173)) - (PORT datad (135:135:135) (175:175:175)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) - (DELAY - (ABSOLUTE - (PORT dataa (522:522:522) (612:612:612)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (605:605:605) (688:688:688)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (755:755:755)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (368:368:368) (439:439:439)) - (PORT datad (550:550:550) (651:651:651)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1417:1417:1417) (1651:1651:1651)) - (PORT datab (891:891:891) (1048:1048:1048)) - (PORT datac (102:102:102) (124:124:124)) - (PORT datad (117:117:117) (141:141:141)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (579:579:579) (682:682:682)) - (PORT datab (106:106:106) (136:136:136)) - (PORT datac (481:481:481) (555:555:555)) - (PORT datad (452:452:452) (517:517:517)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) - (DELAY - (ABSOLUTE - (PORT datab (512:512:512) (597:597:597)) - (PORT datad (334:334:334) (397:397:397)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (412:412:412)) - (PORT datab (516:516:516) (605:605:605)) - (PORT datac (600:600:600) (684:684:684)) - (PORT datad (105:105:105) (124:124:124)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~4) - (DELAY - (ABSOLUTE - (PORT dataa (491:491:491) (577:577:577)) - (PORT datab (490:490:490) (573:573:573)) - (PORT datac (345:345:345) (403:403:403)) - (PORT datad (480:480:480) (557:557:557)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (1138:1138:1138) (1322:1322:1322)) - (PORT datab (506:506:506) (590:590:590)) - (PORT datac (117:117:117) (145:145:145)) - (PORT datad (619:619:619) (717:717:717)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~5) - (DELAY - (ABSOLUTE - (PORT dataa (513:513:513) (593:593:593)) - (PORT datab (498:498:498) (586:586:586)) - (PORT datac (476:476:476) (560:560:560)) - (PORT datad (326:326:326) (381:381:381)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) - (DELAY - (ABSOLUTE - (PORT dataa (492:492:492) (585:585:585)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) - (DELAY - (ABSOLUTE - (PORT dataa (582:582:582) (673:673:673)) - (PORT datab (494:494:494) (579:579:579)) - (PORT datac (340:340:340) (402:402:402)) - (PORT datad (481:481:481) (557:557:557)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1373:1373:1373) (1595:1595:1595)) - (PORT datab (1019:1019:1019) (1196:1196:1196)) - (PORT datac (581:581:581) (652:652:652)) - (PORT datad (902:902:902) (1065:1065:1065)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) - (DELAY - (ABSOLUTE - (PORT dataa (446:446:446) (511:511:511)) - (PORT datab (476:476:476) (564:564:564)) - (PORT datac (443:443:443) (521:521:521)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1375:1375:1375) (1597:1597:1597)) - (PORT datab (1373:1373:1373) (1593:1593:1593)) - (PORT datac (780:780:780) (900:900:900)) - (PORT datad (901:901:901) (1063:1063:1063)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (121:121:121) (151:151:151)) - (PORT datac (109:109:109) (133:133:133)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) - (DELAY - (ABSOLUTE - (PORT dataa (718:718:718) (827:827:827)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (436:436:436) (498:498:498)) - (PORT datad (475:475:475) (552:552:552)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (473:473:473) (549:549:549)) - (PORT datab (126:126:126) (158:158:158)) - (PORT datac (347:347:347) (409:409:409)) - (PORT datad (752:752:752) (857:857:857)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (690:690:690) (814:814:814)) - (PORT datab (773:773:773) (932:932:932)) - (PORT datac (486:486:486) (570:570:570)) - (PORT datad (444:444:444) (510:510:510)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1145:1145:1145) (1330:1330:1330)) - (PORT datab (1472:1472:1472) (1749:1749:1749)) - (PORT datac (1647:1647:1647) (1903:1903:1903)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (458:458:458) (537:537:537)) - (PORT datac (551:551:551) (649:649:649)) - (PORT datad (778:778:778) (883:883:883)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (114:114:114) (150:150:150)) - (PORT datac (354:354:354) (417:417:417)) - (PORT datad (595:595:595) (705:705:705)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) - (DELAY - (ABSOLUTE - (PORT dataa (754:754:754) (904:904:904)) - (PORT datac (642:642:642) (743:743:743)) - (PORT datad (1138:1138:1138) (1332:1332:1332)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (697:697:697)) - (PORT datab (117:117:117) (147:147:147)) - (PORT datac (321:321:321) (376:376:376)) - (PORT datad (646:646:646) (746:746:746)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (780:780:780)) - (PORT datac (631:631:631) (719:719:719)) - (PORT datad (529:529:529) (623:623:623)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) - (DELAY - (ABSOLUTE - (PORT datab (1181:1181:1181) (1364:1364:1364)) - (PORT datac (512:512:512) (606:606:606)) - (PORT datad (1094:1094:1094) (1273:1273:1273)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (766:766:766)) - (PORT datab (306:306:306) (356:356:356)) - (PORT datac (495:495:495) (571:571:571)) - (PORT datad (625:625:625) (719:719:719)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (717:717:717)) - (PORT datab (303:303:303) (352:352:352)) - (PORT datac (624:624:624) (716:716:716)) - (PORT datad (468:468:468) (543:543:543)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1011:1011:1011) (1173:1173:1173)) - (PORT datab (882:882:882) (1025:1025:1025)) - (PORT datad (553:553:553) (642:642:642)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (502:502:502) (586:586:586)) - (PORT datab (643:643:643) (754:754:754)) - (PORT datac (834:834:834) (971:971:971)) - (PORT datad (609:609:609) (698:698:698)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (441:441:441)) - (PORT datab (491:491:491) (569:569:569)) - (PORT datac (328:328:328) (388:388:388)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (857:857:857) (971:971:971)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (502:502:502) (586:586:586)) - (PORT datab (505:505:505) (595:595:595)) - (PORT datac (97:97:97) (123:123:123)) - (PORT datad (476:476:476) (545:545:545)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (976:976:976) (1116:1116:1116)) - (PORT datad (173:173:173) (202:202:202)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (750:750:750)) - (PORT datab (436:436:436) (510:510:510)) - (PORT datac (453:453:453) (529:529:529)) - (PORT datad (92:92:92) (111:111:111)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) - (DELAY - (ABSOLUTE - (PORT dataa (867:867:867) (1021:1021:1021)) - (PORT datab (977:977:977) (1131:1131:1131)) - (PORT datac (1461:1461:1461) (1688:1688:1688)) - (PORT datad (636:636:636) (733:733:733)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1480:1480:1480) (1707:1707:1707)) - (PORT datab (909:909:909) (1072:1072:1072)) - (PORT datac (343:343:343) (393:393:393)) - (PORT datad (108:108:108) (128:128:128)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (311:311:311) (362:362:362)) - (PORT datab (354:354:354) (417:417:417)) - (PORT datac (357:357:357) (412:412:412)) - (PORT datad (484:484:484) (555:555:555)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) - (DELAY - (ABSOLUTE - (PORT datab (377:377:377) (446:446:446)) - (PORT datac (568:568:568) (654:654:654)) - (PORT datad (503:503:503) (584:584:584)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (231:231:231)) - (PORT datab (610:610:610) (698:698:698)) - (PORT datac (569:569:569) (645:645:645)) - (PORT datad (455:455:455) (523:523:523)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (966:966:966) (1113:1113:1113)) - (PORT datab (482:482:482) (562:562:562)) - (PORT datac (866:866:866) (1010:1010:1010)) - (PORT datad (630:630:630) (738:738:738)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (716:716:716)) - (PORT datab (911:911:911) (1046:1046:1046)) - (PORT datac (623:623:623) (725:725:725)) - (PORT datad (114:114:114) (137:137:137)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (423:423:423)) - (PORT datab (628:628:628) (731:731:731)) - (PORT datac (641:641:641) (735:735:735)) - (PORT datad (539:539:539) (628:628:628)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~1) - (DELAY - (ABSOLUTE - (PORT dataa (159:159:159) (204:204:204)) - (PORT datac (940:940:940) (1084:1084:1084)) - (PORT datad (238:238:238) (284:284:284)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (422:422:422)) - (PORT datab (636:636:636) (742:742:742)) - (PORT datac (850:850:850) (970:970:970)) - (PORT datad (715:715:715) (832:832:832)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (914:914:914)) - (PORT datab (496:496:496) (583:583:583)) - (PORT datac (475:475:475) (562:562:562)) - (PORT datad (530:530:530) (618:618:618)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) - (DELAY - (ABSOLUTE - (PORT dataa (471:471:471) (546:546:546)) - (PORT datac (568:568:568) (667:667:667)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (713:713:713)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (593:593:593) (674:674:674)) - (PORT datad (93:93:93) (113:113:113)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (177:177:177) (214:214:214)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datac (182:182:182) (222:222:222)) - (PORT datad (467:467:467) (538:538:538)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (755:755:755) (871:871:871)) - (PORT datab (439:439:439) (502:502:502)) - (PORT datac (946:946:946) (1093:1093:1093)) - (PORT datad (508:508:508) (588:588:588)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (693:693:693)) - (PORT datab (347:347:347) (408:408:408)) - (PORT datac (462:462:462) (532:532:532)) - (PORT datad (481:481:481) (559:559:559)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (153:153:153)) - (PORT datab (345:345:345) (407:407:407)) - (PORT datac (773:773:773) (892:892:892)) - (PORT datad (627:627:627) (723:723:723)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (1084:1084:1084)) - (PORT datab (563:563:563) (663:663:663)) - (PORT datac (1072:1072:1072) (1218:1218:1218)) - (PORT datad (906:906:906) (1050:1050:1050)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (364:364:364) (431:431:431)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (117:117:117) (154:154:154)) - (PORT datab (342:342:342) (402:402:402)) - (PORT datac (106:106:106) (128:128:128)) - (PORT datad (657:657:657) (748:748:748)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (580:580:580) (687:687:687)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (331:331:331) (385:385:385)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) - (DELAY - (ABSOLUTE - (PORT dataa (509:509:509) (599:599:599)) - (PORT datab (622:622:622) (721:721:721)) - (PORT datac (480:480:480) (563:563:563)) - (PORT datad (634:634:634) (736:736:736)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) - (DELAY - (ABSOLUTE - (PORT datab (114:114:114) (141:141:141)) - (PORT datac (335:335:335) (393:393:393)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) - (DELAY - (ABSOLUTE - (PORT dataa (111:111:111) (147:147:147)) - (PORT datac (286:286:286) (335:335:335)) - (PORT datad (478:478:478) (567:567:567)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (745:745:745) (873:873:873)) - (PORT datab (362:362:362) (420:420:420)) - (PORT datac (104:104:104) (125:125:125)) - (PORT datad (634:634:634) (743:743:743)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) - (DELAY - (ABSOLUTE - (PORT dataa (290:290:290) (338:338:338)) - (PORT datac (450:450:450) (537:537:537)) - (PORT datad (442:442:442) (526:526:526)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (495:495:495) (570:570:570)) - (PORT datab (363:363:363) (428:428:428)) - (PORT datac (196:196:196) (235:235:235)) - (PORT datad (335:335:335) (388:388:388)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~45) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (416:416:416)) - (PORT datab (456:456:456) (527:527:527)) - (PORT datac (482:482:482) (553:553:553)) - (PORT datad (351:351:351) (418:418:418)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~46) - (DELAY - (ABSOLUTE - (PORT datab (438:438:438) (503:503:503)) - (PORT datac (105:105:105) (127:127:127)) - (PORT datad (821:821:821) (939:939:939)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) - (DELAY - (ABSOLUTE - (PORT dataa (311:311:311) (357:357:357)) - (PORT datab (496:496:496) (585:585:585)) - (PORT datac (306:306:306) (346:346:346)) - (PORT datad (311:311:311) (363:363:363)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) - (DELAY - (ABSOLUTE - (PORT dataa (524:524:524) (599:599:599)) - (PORT datab (904:904:904) (1066:1066:1066)) - (PORT datac (466:466:466) (536:536:536)) - (PORT datad (198:198:198) (231:231:231)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (139:139:139)) - (PORT datab (177:177:177) (214:214:214)) - (PORT datac (114:114:114) (140:140:140)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~4) - (DELAY - (ABSOLUTE - (PORT dataa (502:502:502) (586:586:586)) - (PORT datac (488:488:488) (572:572:572)) - (PORT datad (442:442:442) (507:507:507)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (411:411:411)) - (PORT datab (835:835:835) (969:969:969)) - (PORT datac (450:450:450) (512:512:512)) - (PORT datad (458:458:458) (527:527:527)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (295:295:295)) - (PORT datab (520:520:520) (602:602:602)) - (PORT datac (201:201:201) (234:234:234)) - (PORT datad (1100:1100:1100) (1292:1292:1292)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1449:1449:1449) (1724:1724:1724)) - (PORT datab (289:289:289) (333:333:333)) - (PORT datac (486:486:486) (560:560:560)) - (PORT datad (633:633:633) (727:727:727)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (419:419:419)) - (PORT datab (306:306:306) (354:354:354)) - (PORT datac (444:444:444) (524:524:524)) - (PORT datad (108:108:108) (126:126:126)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) - (DELAY - (ABSOLUTE - (PORT dataa (308:308:308) (363:363:363)) - (PORT datab (477:477:477) (554:554:554)) - (PORT datac (1115:1115:1115) (1290:1290:1290)) - (PORT datad (318:318:318) (364:364:364)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (715:715:715)) - (PORT datab (900:900:900) (1058:1058:1058)) - (PORT datac (353:353:353) (417:417:417)) - (PORT datad (336:336:336) (386:386:386)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) - (DELAY - (ABSOLUTE - (PORT dataa (481:481:481) (561:561:561)) - (PORT datab (298:298:298) (343:343:343)) - (PORT datac (338:338:338) (390:390:390)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (413:413:413)) - (PORT datab (515:515:515) (604:604:604)) - (PORT datac (273:273:273) (312:312:312)) - (PORT datad (477:477:477) (558:558:558)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc) - (DELAY - (ABSOLUTE - (PORT dataa (121:121:121) (153:153:153)) - (PORT datab (351:351:351) (414:414:414)) - (PORT datac (452:452:452) (520:520:520)) - (PORT datad (175:175:175) (207:207:207)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) - (DELAY - (ABSOLUTE - (PORT datab (803:803:803) (941:941:941)) - (PORT datac (498:498:498) (577:577:577)) - (PORT datad (435:435:435) (504:504:504)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (121:121:121) (154:154:154)) - (PORT datab (714:714:714) (816:816:816)) - (PORT datac (757:757:757) (868:868:868)) - (PORT datad (162:162:162) (189:189:189)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) - (DELAY - (ABSOLUTE - (PORT datab (518:518:518) (608:608:608)) - (PORT datac (803:803:803) (934:934:934)) - (PORT datad (358:358:358) (423:423:423)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (529:529:529) (593:593:593)) - (PORT ena (636:636:636) (682:682:682)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1037:1037:1037) (1192:1192:1192)) - (PORT datab (385:385:385) (456:456:456)) - (PORT datad (662:662:662) (772:772:772)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) - (DELAY - (ABSOLUTE - (PORT datab (377:377:377) (447:447:447)) - (PORT datac (570:570:570) (655:655:655)) - (PORT datad (503:503:503) (584:584:584)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (746:746:746)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (404:404:404) (479:479:479)) - (PORT datac (339:339:339) (398:398:398)) - (PORT datad (118:118:118) (155:155:155)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT datac (1107:1107:1107) (1285:1285:1285)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) - (DELAY - (ABSOLUTE - (PORT clk (932:932:932) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT clk (932:932:932) (916:916:916)) - (PORT asdata (300:300:300) (342:342:342)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (932:932:932) (916:916:916)) - (PORT asdata (301:301:301) (343:343:343)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE KEY\[0\]\~input) @@ -11353,8 +1127,8 @@ (INSTANCE reset) (DELAY (ABSOLUTE - (PORT datac (981:981:981) (856:856:856)) - (PORT datad (284:284:284) (306:306:306)) + (PORT datac (979:979:979) (855:855:855)) + (PORT datad (283:283:283) (305:305:305)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -11365,7 +1139,7 @@ (INSTANCE z80_\|resets_\|x1\~0) (DELAY (ABSOLUTE - (PORT datad (827:827:827) (963:963:963)) + (PORT datad (104:104:104) (121:121:121)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -11375,7 +1149,7 @@ (INSTANCE z80_\|fpga_reset) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (919:919:919)) + (PORT clk (912:912:912) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -11389,7 +1163,7 @@ (INSTANCE z80_\|fpga_reset\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (391:391:391) (424:424:424)) + (PORT inclk[0] (411:411:411) (447:447:447)) ) ) ) @@ -11398,9 +1172,9 @@ (INSTANCE z80_\|resets_\|x1) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (899:899:899)) + (PORT clk (924:924:924) (908:908:908)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (1092:1092:1092) (1064:1064:1064)) + (PORT clrn (913:913:913) (896:896:896)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -11411,27 +1185,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc_int\~0) + (INSTANCE z80_\|resets_\|x3) (DELAY (ABSOLUTE - (PORT dataa (341:341:341) (418:418:418)) - (PORT datab (321:321:321) (386:386:386)) - (PORT datad (642:642:642) (749:749:749)) - (IOPATH dataa combout (181:181:181) (193:193:193)) - (IOPATH datab combout (191:191:191) (188:188:188)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT dataa (1093:1093:1093) (1296:1296:1296)) + (PORT datac (797:797:797) (942:942:942)) + (PORT datad (636:636:636) (763:763:763)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|clrpc_int) + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) (DELAY (ABSOLUTE - (PORT clk (932:932:932) (916:916:916)) + (PORT clk (914:914:914) (922:922:922)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (928:928:928) (909:909:909)) + (PORT clrn (915:915:915) (898:898:898)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -11442,1393 +1215,49 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc\~0) + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) (DELAY (ABSOLUTE - (PORT dataa (134:134:134) (187:187:187)) - (PORT datab (138:138:138) (189:189:189)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[7\]) - (DELAY - (ABSOLUTE - (PORT datac (362:362:362) (425:425:425)) - (PORT datad (330:330:330) (387:387:387)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1449:1449:1449) (1725:1725:1725)) - (PORT datac (486:486:486) (561:561:561)) - (PORT datad (1109:1109:1109) (1285:1285:1285)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (188:188:188) (224:224:224)) - (PORT datab (294:294:294) (338:338:338)) - (PORT datac (468:468:468) (539:539:539)) - (PORT datad (632:632:632) (726:726:726)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT datac (410:410:410) (494:494:494)) + (PORT datad (178:178:178) (236:236:236)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (701:701:701)) - (PORT datab (633:633:633) (735:735:735)) - (PORT datac (425:425:425) (483:483:483)) - (PORT datad (341:341:341) (396:396:396)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (549:549:549) (652:652:652)) - (PORT datab (908:908:908) (1030:1030:1030)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (638:638:638) (733:733:733)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (671:671:671) (796:796:796)) - (PORT datab (556:556:556) (665:665:665)) - (PORT datac (373:373:373) (440:440:440)) - (PORT datad (717:717:717) (834:834:834)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (417:417:417) (476:476:476)) - (PORT datab (346:346:346) (408:408:408)) - (PORT datac (473:473:473) (541:541:541)) - (PORT datad (592:592:592) (693:693:693)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (387:387:387) (450:450:450)) - (PORT datac (106:106:106) (129:129:129)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datac (96:96:96) (120:120:120)) - (PORT datad (287:287:287) (329:329:329)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (718:718:718) (827:827:827)) - (PORT datab (440:440:440) (506:506:506)) - (PORT datac (439:439:439) (501:501:501)) - (PORT datad (477:477:477) (554:554:554)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[7\]) + (INSTANCE z80_\|interrupts_\|nmi_armed) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) + (PORT clk (1233:1233:1233) (1373:1373:1373)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (904:904:904)) - (PORT ena (1159:1159:1159) (1318:1318:1318)) + (PORT clrn (780:780:780) (846:846:846)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1264:1264:1264) (1415:1415:1415)) + ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (248:248:248)) - (PORT datab (1010:1010:1010) (1167:1167:1167)) - (PORT datac (107:107:107) (131:131:131)) - (PORT datad (358:358:358) (422:422:422)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datab (808:808:808) (953:953:953)) + (PORT datad (951:951:951) (1131:1131:1131)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~0) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (781:781:781)) - (PORT datab (1128:1128:1128) (1312:1312:1312)) - (PORT datac (739:739:739) (880:880:880)) - (PORT datad (1144:1144:1144) (1338:1338:1338)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) - (DELAY - (ABSOLUTE - (PORT dataa (195:195:195) (234:234:234)) - (PORT datab (114:114:114) (146:146:146)) - (PORT datac (607:607:607) (700:700:700)) - (PORT datad (666:666:666) (759:759:759)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (144:144:144)) - (PORT datab (957:957:957) (1115:1115:1115)) - (PORT datac (290:290:290) (329:329:329)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) - (DELAY - (ABSOLUTE - (PORT datab (548:548:548) (641:641:641)) - (PORT datac (607:607:607) (700:700:700)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) - (DELAY - (ABSOLUTE - (PORT dataa (566:566:566) (659:659:659)) - (PORT datad (620:620:620) (707:707:707)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (746:746:746)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) - (DELAY - (ABSOLUTE - (PORT datab (865:865:865) (1006:1006:1006)) - (PORT datac (667:667:667) (775:775:775)) - (PORT datad (578:578:578) (662:662:662)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) - (DELAY - (ABSOLUTE - (PORT datab (863:863:863) (1004:1004:1004)) - (PORT datac (675:675:675) (784:784:784)) - (PORT datad (548:548:548) (645:645:645)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) - (DELAY - (ABSOLUTE - (PORT datab (862:862:862) (1004:1004:1004)) - (PORT datac (677:677:677) (786:786:786)) - (PORT datad (577:577:577) (661:661:661)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (761:761:761) (846:846:846)) - (PORT ena (915:915:915) (1002:1002:1002)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) - (DELAY - (ABSOLUTE - (PORT datab (866:866:866) (1008:1008:1008)) - (PORT datac (664:664:664) (771:771:771)) - (PORT datad (552:552:552) (650:650:650)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (760:760:760) (845:845:845)) - (PORT ena (756:756:756) (816:816:816)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (482:482:482) (566:566:566)) - (PORT datab (545:545:545) (641:641:641)) - (PORT datad (116:116:116) (152:152:152)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) - (DELAY - (ABSOLUTE - (PORT datab (754:754:754) (870:870:870)) - (PORT datac (642:642:642) (731:731:731)) - (PORT datad (320:320:320) (371:371:371)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (377:377:377) (413:413:413)) - (PORT ena (419:419:419) (435:435:435)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (234:234:234)) - (PORT datab (117:117:117) (151:151:151)) - (PORT datac (119:119:119) (161:161:161)) - (PORT datad (676:676:676) (801:801:801)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) - (DELAY - (ABSOLUTE - (PORT datab (650:650:650) (745:745:745)) - (PORT datac (346:346:346) (410:410:410)) - (PORT datad (739:739:739) (849:849:849)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT datab (653:653:653) (749:749:749)) - (PORT datac (346:346:346) (410:410:410)) - (PORT datad (738:738:738) (848:848:848)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (375:375:375) (411:411:411)) - (PORT ena (432:432:432) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (130:130:130) (181:181:181)) - (PORT datab (141:141:141) (179:179:179)) - (PORT datad (126:126:126) (150:150:150)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) - (DELAY - (ABSOLUTE - (PORT datac (503:503:503) (580:580:580)) - (PORT datad (731:731:731) (838:838:838)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (462:462:462)) - (PORT datab (646:646:646) (750:750:750)) - (PORT datac (104:104:104) (134:134:134)) - (PORT datad (804:804:804) (942:942:942)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (643:643:643) (714:714:714)) - (PORT ena (660:660:660) (723:723:723)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (386:386:386) (461:461:461)) - (PORT datab (645:645:645) (748:748:748)) - (PORT datac (105:105:105) (135:135:135)) - (PORT datad (805:805:805) (943:943:943)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (643:643:643) (714:714:714)) - (PORT ena (631:631:631) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (294:294:294)) - (PORT datab (130:130:130) (178:178:178)) - (PORT datad (344:344:344) (402:402:402)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (397:397:397)) - (PORT datab (517:517:517) (608:608:608)) - (PORT datad (358:358:358) (423:423:423)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (915:915:915) (1012:1012:1012)) - (PORT ena (812:812:812) (885:885:885)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (404:404:404)) - (PORT datab (766:766:766) (882:882:882)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) - (DELAY - (ABSOLUTE - (PORT dataa (633:633:633) (737:737:737)) - (PORT datab (644:644:644) (748:748:748)) - (PORT datac (105:105:105) (135:135:135)) - (PORT datad (371:371:371) (430:430:430)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (661:661:661) (736:736:736)) - (PORT ena (644:644:644) (698:698:698)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (492:492:492) (581:581:581)) - (PORT datab (214:214:214) (269:269:269)) - (PORT datac (508:508:508) (591:591:591)) - (PORT datad (333:333:333) (387:387:387)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) - (DELAY - (ABSOLUTE - (PORT dataa (483:483:483) (580:580:580)) - (PORT datab (502:502:502) (600:600:600)) - (PORT datac (627:627:627) (726:726:726)) - (PORT datad (200:200:200) (242:242:242)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) - (DELAY - (ABSOLUTE - (PORT datab (527:527:527) (614:614:614)) - (PORT datac (733:733:733) (838:838:838)) - (PORT datad (497:497:497) (573:573:573)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (761:761:761)) - (PORT datab (648:648:648) (752:752:752)) - (PORT datac (103:103:103) (132:132:132)) - (PORT datad (374:374:374) (434:434:434)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (915:915:915) (1012:1012:1012)) - (PORT ena (649:649:649) (703:703:703)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) - (DELAY - (ABSOLUTE - (PORT dataa (972:972:972) (1102:1102:1102)) - (PORT datab (510:510:510) (597:597:597)) - (PORT datad (515:515:515) (592:592:592)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (662:662:662) (738:738:738)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (264:264:264)) - (PORT datab (344:344:344) (406:406:406)) - (PORT datad (187:187:187) (230:230:230)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1122:1122:1122)) - (PORT datab (650:650:650) (747:747:747)) - (PORT datad (431:431:431) (486:486:486)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (762:762:762) (844:844:844)) - (PORT ena (422:422:422) (454:454:454)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (465:465:465) (528:528:528)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT datab (562:562:562) (646:646:646)) - (PORT datac (491:491:491) (581:581:581)) - (PORT datad (481:481:481) (559:559:559)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (669:669:669) (725:725:725)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (274:274:274)) - (PORT datab (313:313:313) (371:371:371)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (275:275:275) (313:313:313)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (415:415:415)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datad (426:426:426) (485:485:485)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (228:228:228)) - (PORT datab (323:323:323) (376:376:376)) - (PORT datac (748:748:748) (865:865:865)) - (PORT datad (346:346:346) (405:405:405)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (762:762:762) (847:847:847)) - (PORT ena (636:636:636) (682:682:682)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (147:147:147)) - (PORT datab (675:675:675) (791:791:791)) - (PORT datad (362:362:362) (425:425:425)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (368:368:368) (431:431:431)) - (PORT datac (622:622:622) (719:719:719)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (746:746:746)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (769:769:769) (850:850:850)) - (PORT ena (419:419:419) (435:435:435)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (769:769:769) (849:849:849)) - (PORT ena (432:432:432) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (130:130:130) (181:181:181)) - (PORT datab (141:141:141) (179:179:179)) - (PORT datad (126:126:126) (151:151:151)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (907:907:907)) - (PORT asdata (645:645:645) (709:709:709)) - (PORT ena (421:421:421) (441:441:441)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|db\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (749:749:749)) - (PORT datab (862:862:862) (1003:1003:1003)) - (PORT datad (577:577:577) (660:660:660)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (810:810:810) (910:910:910)) - (PORT ena (756:756:756) (816:816:816)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (415:415:415)) - (PORT datab (610:610:610) (699:699:699)) - (PORT datad (528:528:528) (614:614:614)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (648:648:648) (715:715:715)) - (PORT ena (644:644:644) (698:698:698)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (649:649:649) (715:715:715)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (427:427:427)) - (PORT datab (129:129:129) (176:176:176)) - (PORT datad (191:191:191) (225:225:225)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (809:809:809) (908:908:908)) - (PORT ena (794:794:794) (880:880:880)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (180:180:180) (214:214:214)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (660:660:660) (723:723:723)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (806:806:806) (905:905:905)) - (PORT ena (736:736:736) (793:793:793)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (283:283:283)) - (PORT datab (346:346:346) (408:408:408)) - (PORT datad (436:436:436) (508:508:508)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (794:794:794)) - (PORT datab (493:493:493) (580:580:580)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (486:486:486) (535:535:535)) - (PORT ena (631:631:631) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (283:283:283)) - (PORT datab (624:624:624) (718:718:718)) - (PORT datad (283:283:283) (328:328:328)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (927:927:927) (1045:1045:1045)) - (PORT ena (422:422:422) (454:454:454)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (927:927:927) (1045:1045:1045)) - (PORT ena (669:669:669) (725:725:725)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (277:277:277)) - (PORT datab (306:306:306) (363:363:363)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (329:329:329) (390:390:390)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (173:173:173) (208:208:208)) - (PORT datad (317:317:317) (368:368:368)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (761:761:761)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (621:621:621) (707:707:707)) - (PORT datad (446:446:446) (510:510:510)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (867:867:867) (954:954:954)) - (PORT ena (636:636:636) (682:682:682)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (715:715:715)) - (PORT datab (381:381:381) (451:451:451)) - (PORT datad (654:654:654) (763:763:763)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT datab (131:131:131) (180:180:180)) - (PORT datac (386:386:386) (461:461:461)) - (PORT datad (455:455:455) (520:520:520)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) - (DELAY - (ABSOLUTE - (PORT dataa (501:501:501) (593:593:593)) - (PORT datab (516:516:516) (603:603:603)) - (PORT datac (843:843:843) (964:964:964)) - (PORT datad (375:375:375) (446:446:446)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -12842,105 +1271,14 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~14) - (DELAY - (ABSOLUTE - (PORT datab (773:773:773) (898:898:898)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (143:143:143) (194:194:194)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~2) - (DELAY - (ABSOLUTE - (PORT datac (457:457:457) (527:527:527)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~18) - (DELAY - (ABSOLUTE - (PORT datad (363:363:363) (425:425:425)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~1) - (DELAY - (ABSOLUTE - (PORT datab (120:120:120) (149:149:149)) - (PORT datad (295:295:295) (343:343:343)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (921:921:921)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~0) (DELAY (ABSOLUTE - (PORT datab (571:571:571) (658:658:658)) - (IOPATH datab combout (192:192:192) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (357:357:357) (445:445:445)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -12950,8 +1288,8 @@ (INSTANCE ula_\|video_\|vga_hc\~3) (DELAY (ABSOLUTE - (PORT datac (457:457:457) (535:535:535)) - (PORT datad (505:505:505) (580:580:580)) + (PORT datac (191:191:191) (233:233:233)) + (PORT datad (332:332:332) (389:389:389)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -12962,7 +1300,7 @@ (INSTANCE ula_\|video_\|vga_hc\[0\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (923:923:923)) + (PORT clk (920:920:920) (923:923:923)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -12976,7 +1314,7 @@ (INSTANCE ula_\|video_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (360:360:360) (430:430:430)) + (PORT datab (240:240:240) (295:295:295)) (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -12990,7 +1328,7 @@ (INSTANCE ula_\|video_\|vga_hc\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (307:307:307) (358:358:358)) + (PORT datad (168:168:168) (197:197:197)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -13000,7 +1338,7 @@ (INSTANCE ula_\|video_\|vga_hc\[1\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) + (PORT clk (921:921:921) (925:925:925)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -13028,8 +1366,8 @@ (INSTANCE ula_\|video_\|vga_hc\[2\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (340:340:340) (367:367:367)) + (PORT clk (921:921:921) (926:926:926)) + (PORT asdata (445:445:445) (482:482:482)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -13042,37 +1380,27 @@ (INSTANCE ula_\|video_\|Add0\~6) (DELAY (ABSOLUTE - (PORT datab (366:366:366) (441:441:441)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (330:330:330) (400:400:400)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (295:295:295) (339:339:339)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|vga_hc\[3\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) + (PORT clk (921:921:921) (925:925:925)) + (PORT asdata (450:450:450) (489:489:489)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) ) ) (CELL @@ -13080,7 +1408,7 @@ (INSTANCE ula_\|video_\|Add0\~8) (DELAY (ABSOLUTE - (PORT dataa (561:561:561) (647:647:647)) + (PORT dataa (330:330:330) (404:404:404)) (IOPATH dataa combout (186:186:186) (175:175:175)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -13094,8 +1422,104 @@ (INSTANCE ula_\|video_\|vga_hc\[4\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (340:340:340) (367:367:367)) + (PORT clk (921:921:921) (926:926:926)) + (PORT asdata (449:449:449) (486:486:486)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT datab (431:431:431) (504:504:504)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\~0) + (DELAY + (ABSOLUTE + (PORT datab (104:104:104) (132:132:132)) + (PORT datad (336:336:336) (394:394:394)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (921:921:921) (926:926:926)) + (PORT asdata (270:270:270) (291:291:291)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (746:746:746) (859:859:859)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (921:921:921) (926:926:926)) + (PORT asdata (338:338:338) (363:363:363)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (416:416:416)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (921:921:921) (926:926:926)) + (PORT asdata (781:781:781) (871:871:871)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -13108,10 +1532,10 @@ (INSTANCE ula_\|video_\|Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (680:680:680) (808:808:808)) - (PORT datab (530:530:530) (634:634:634)) - (PORT datac (534:534:534) (639:639:639)) - (PORT datad (156:156:156) (204:204:204)) + (PORT dataa (239:239:239) (309:309:309)) + (PORT datab (521:521:521) (622:622:622)) + (PORT datac (381:381:381) (463:463:463)) + (PORT datad (397:397:397) (476:476:476)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -13124,39 +1548,24 @@ (INSTANCE ula_\|video_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (350:350:350) (423:423:423)) - (PORT datab (774:774:774) (900:900:900)) - (PORT datad (508:508:508) (565:565:565)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (236:236:236) (295:295:295)) - (PORT datab (366:366:366) (440:440:440)) - (PORT datac (343:343:343) (414:414:414)) - (PORT datad (299:299:299) (344:344:344)) + (PORT dataa (675:675:675) (799:799:799)) + (PORT datab (486:486:486) (567:567:567)) + (PORT datac (353:353:353) (419:419:419)) + (PORT datad (91:91:91) (109:109:109)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~10) + (INSTANCE ula_\|video_\|Add0\~16) (DELAY (ABSOLUTE - (PORT dataa (346:346:346) (418:418:418)) - (IOPATH dataa combout (165:165:165) (173:173:173)) + (PORT dataa (565:565:565) (661:661:661)) + (IOPATH dataa combout (186:186:186) (175:175:175)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) @@ -13166,22 +1575,130 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~0) + (INSTANCE ula_\|video_\|vga_hc\~2) (DELAY (ABSOLUTE - (PORT datac (460:460:460) (530:530:530)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datad (336:336:336) (394:394:394)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[5\]) + (INSTANCE ula_\|video_\|vga_hc\[8\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) + (PORT clk (921:921:921) (926:926:926)) + (PORT asdata (444:444:444) (481:481:481)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datab (144:144:144) (193:193:193)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\~1) + (DELAY + (ABSOLUTE + (PORT datab (177:177:177) (218:218:218)) + (PORT datad (337:337:337) (395:395:395)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (921:921:921) (926:926:926)) + (PORT asdata (764:764:764) (846:846:846)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (119:119:119) (151:151:151)) + (PORT datab (683:683:683) (799:799:799)) + (PORT datac (480:480:480) (572:572:572)) + (PORT datad (470:470:470) (548:548:548)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (688:688:688) (802:802:802)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (379:379:379) (456:456:456)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (415:415:415)) + (PORT datab (832:832:832) (954:954:954)) + (PORT datad (317:317:317) (366:366:366)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (921:921:921) (925:925:925)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -13190,82 +1707,14 @@ (HOLD d (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~12) - (DELAY - (ABSOLUTE - (PORT dataa (326:326:326) (394:394:394)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (268:268:268) (288:288:288)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (446:446:446) (483:483:483)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~0) - (DELAY - (ABSOLUTE - (PORT datab (393:393:393) (474:474:474)) - (IOPATH datab combout (192:192:192) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~2) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (464:464:464)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~4) (DELAY (ABSOLUTE - (PORT dataa (362:362:362) (437:437:437)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (365:365:365) (439:439:439)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -13277,9 +1726,9 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (332:332:332)) - (PORT datab (313:313:313) (364:364:364)) - (PORT datad (476:476:476) (552:552:552)) + (PORT dataa (354:354:354) (417:417:417)) + (PORT datab (339:339:339) (404:404:404)) + (PORT datad (813:813:813) (929:929:929)) (IOPATH dataa combout (188:188:188) (179:179:179)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -13292,7 +1741,7 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) + (PORT clk (921:921:921) (925:925:925)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -13306,9 +1755,9 @@ (INSTANCE ula_\|video_\|Add1\~6) (DELAY (ABSOLUTE - (PORT dataa (376:376:376) (456:456:456)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (376:376:376) (452:452:452)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -13320,13 +1769,12 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (322:322:322) (377:377:377)) - (PORT datab (354:354:354) (417:417:417)) - (PORT datac (358:358:358) (437:437:437)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (353:353:353) (416:416:416)) + (PORT datab (832:832:832) (954:954:954)) + (PORT datad (318:318:318) (369:369:369)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -13336,13 +1784,13 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT asdata (707:707:707) (780:780:780)) + (PORT clk (921:921:921) (925:925:925)) + (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) + (HOLD d (posedge clk) (84:84:84)) ) ) (CELL @@ -13350,9 +1798,9 @@ (INSTANCE ula_\|video_\|Add1\~8) (DELAY (ABSOLUTE - (PORT datab (373:373:373) (454:454:454)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (506:506:506) (598:598:598)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -13364,9 +1812,9 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]\~5) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (332:332:332)) - (PORT datab (327:327:327) (381:381:381)) - (PORT datad (474:474:474) (549:549:549)) + (PORT dataa (354:354:354) (417:417:417)) + (PORT datab (351:351:351) (415:415:415)) + (PORT datad (813:813:813) (928:928:928)) (IOPATH dataa combout (188:188:188) (179:179:179)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -13379,7 +1827,7 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) + (PORT clk (921:921:921) (925:925:925)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -13393,9 +1841,9 @@ (INSTANCE ula_\|video_\|Add1\~10) (DELAY (ABSOLUTE - (PORT dataa (382:382:382) (469:469:469)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (396:396:396) (481:481:481)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -13407,13 +1855,12 @@ (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) (DELAY (ABSOLUTE - (PORT dataa (322:322:322) (377:377:377)) - (PORT datab (354:354:354) (417:417:417)) - (PORT datac (384:384:384) (465:465:465)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (357:357:357) (421:421:421)) + (PORT datab (836:836:836) (958:958:958)) + (PORT datad (314:314:314) (362:362:362)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -13423,13 +1870,13 @@ (INSTANCE ula_\|video_\|vga_vc\[5\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT asdata (467:467:467) (503:503:503)) + (PORT clk (921:921:921) (925:925:925)) + (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) + (HOLD d (posedge clk) (84:84:84)) ) ) (CELL @@ -13437,9 +1884,9 @@ (INSTANCE ula_\|video_\|Add1\~12) (DELAY (ABSOLUTE - (PORT datab (389:389:389) (469:469:469)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (514:514:514) (596:596:596)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -13451,11 +1898,11 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]\~4) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (332:332:332)) - (PORT datab (310:310:310) (365:365:365)) - (PORT datad (477:477:477) (553:553:553)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (355:355:355) (424:424:424)) + (PORT datab (303:303:303) (357:357:357)) + (PORT datad (415:415:415) (470:470:470)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -13466,7 +1913,7 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) + (PORT clk (921:921:921) (925:925:925)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -13480,7 +1927,7 @@ (INSTANCE ula_\|video_\|Add1\~14) (DELAY (ABSOLUTE - (PORT datab (376:376:376) (449:449:449)) + (PORT datab (530:530:530) (630:630:630)) (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -13494,9 +1941,9 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]\~6) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (332:332:332)) - (PORT datab (639:639:639) (726:726:726)) - (PORT datad (476:476:476) (551:551:551)) + (PORT dataa (354:354:354) (423:423:423)) + (PORT datab (570:570:570) (653:653:653)) + (PORT datad (289:289:289) (333:333:333)) (IOPATH dataa combout (188:188:188) (179:179:179)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -13509,7 +1956,7 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) + (PORT clk (921:921:921) (925:925:925)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -13523,7 +1970,7 @@ (INSTANCE ula_\|video_\|Add1\~16) (DELAY (ABSOLUTE - (PORT datab (399:399:399) (484:484:484)) + (PORT datab (505:505:505) (596:596:596)) (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -13537,9 +1984,9 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]\~7) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (332:332:332)) - (PORT datab (521:521:521) (599:599:599)) - (PORT datad (473:473:473) (548:548:548)) + (PORT dataa (354:354:354) (423:423:423)) + (PORT datab (603:603:603) (696:696:696)) + (PORT datad (289:289:289) (333:333:333)) (IOPATH dataa combout (188:188:188) (179:179:179)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -13552,7 +1999,7 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) + (PORT clk (921:921:921) (925:925:925)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -13566,7 +2013,7 @@ (INSTANCE ula_\|video_\|Add1\~18) (DELAY (ABSOLUTE - (PORT datad (351:351:351) (415:415:415)) + (PORT datad (347:347:347) (419:419:419)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) ) @@ -13577,11 +2024,11 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]\~9) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (332:332:332)) - (PORT datab (537:537:537) (608:608:608)) - (PORT datad (477:477:477) (552:552:552)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (357:357:357) (426:426:426)) + (PORT datab (304:304:304) (358:358:358)) + (PORT datad (418:418:418) (477:477:477)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -13592,7 +2039,7 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) + (PORT clk (921:921:921) (925:925:925)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -13601,47 +2048,15 @@ (HOLD d (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (147:147:147) (200:200:200)) - (PORT datab (146:146:146) (195:195:195)) - (PORT datac (144:144:144) (186:186:186)) - (PORT datad (133:133:133) (172:172:172)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Equal3\~0) (DELAY (ABSOLUTE - (PORT dataa (650:650:650) (772:772:772)) - (PORT datab (457:457:457) (535:535:535)) - (PORT datac (339:339:339) (397:397:397)) - (PORT datad (370:370:370) (443:443:443)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (409:409:409)) - (PORT datab (359:359:359) (427:427:427)) - (PORT datac (300:300:300) (343:343:343)) - (PORT datad (156:156:156) (182:182:182)) + (PORT dataa (156:156:156) (213:213:213)) + (PORT datab (365:365:365) (440:440:440)) + (PORT datac (337:337:337) (404:404:404)) + (PORT datad (641:641:641) (743:743:743)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -13649,16 +2064,48 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (277:277:277)) + (PORT datab (158:158:158) (207:207:207)) + (PORT datac (136:136:136) (182:182:182)) + (PORT datad (222:222:222) (270:270:270)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (275:275:275)) + (PORT datab (479:479:479) (550:550:550)) + (PORT datac (326:326:326) (387:387:387)) + (PORT datad (308:308:308) (347:347:347)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (265:265:265) (331:331:331)) - (PORT datab (295:295:295) (339:339:339)) - (PORT datad (472:472:472) (547:547:547)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (354:354:354) (417:417:417)) + (PORT datab (833:833:833) (955:955:955)) + (PORT datad (161:161:161) (188:188:188)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -13669,7 +2116,7 @@ (INSTANCE ula_\|video_\|vga_vc\[0\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) + (PORT clk (921:921:921) (925:925:925)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -13680,32 +2127,33 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (INSTANCE ula_\|video_\|Equal2\~1) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (332:332:332)) - (PORT datab (301:301:301) (348:348:348)) - (PORT datad (474:474:474) (549:549:549)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT dataa (217:217:217) (274:274:274)) + (PORT datab (365:365:365) (441:441:441)) + (PORT datac (335:335:335) (402:402:402)) + (PORT datad (198:198:198) (250:250:250)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[1\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal2\~2) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (PORT dataa (177:177:177) (220:220:220)) + (PORT datac (325:325:325) (386:386:386)) + (PORT datad (309:309:309) (349:349:349)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) ) (CELL (CELLTYPE "cycloneive_io_ibuf") @@ -13721,10 +2169,10 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13\~0) (DELAY (ABSOLUTE - (PORT dataa (784:784:784) (902:902:902)) - (PORT datab (396:396:396) (475:475:475)) - (PORT datac (1149:1149:1149) (995:995:995)) - (PORT datad (359:359:359) (424:424:424)) + (PORT dataa (503:503:503) (588:588:588)) + (PORT datab (508:508:508) (603:603:603)) + (PORT datac (495:495:495) (577:577:577)) + (PORT datad (816:816:816) (701:701:701)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -13734,13 +2182,731 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal79\~0) + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) (DELAY (ABSOLUTE - (PORT dataa (712:712:712) (834:834:834)) - (PORT datab (535:535:535) (631:631:631)) - (PORT datac (917:917:917) (1101:1101:1101)) - (PORT datad (676:676:676) (800:800:800)) + (PORT datac (781:781:781) (898:898:898)) + (PORT datad (1070:1070:1070) (1244:1244:1244)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (408:408:408) (505:505:505)) + (PORT datab (804:804:804) (961:961:961)) + (PORT datac (1061:1061:1061) (1240:1240:1240)) + (PORT datad (939:939:939) (1085:1085:1085)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (990:990:990) (1153:1153:1153)) + (PORT datad (172:172:172) (204:204:204)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M3_ff\~0) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (275:275:275)) + (PORT datab (388:388:388) (467:467:467)) + (PORT datad (492:492:492) (569:569:569)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M3_ff) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (918:918:918) (901:901:901)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (796:796:796) (974:974:974)) + (PORT datad (520:520:520) (619:619:619)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla12M3T3_3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1062:1062:1062) (1225:1225:1225)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (350:350:350) (408:408:408)) + (PORT datad (922:922:922) (1096:1096:1096)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~0) + (DELAY + (ABSOLUTE + (PORT dataa (989:989:989) (1152:1152:1152)) + (PORT datab (940:940:940) (1122:1122:1122)) + (PORT datad (1048:1048:1048) (1199:1199:1199)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~5) + (DELAY + (ABSOLUTE + (PORT dataa (896:896:896) (1044:1044:1044)) + (PORT datab (143:143:143) (176:176:176)) + (PORT datac (806:806:806) (925:925:925)) + (PORT datad (662:662:662) (766:766:766)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal77\~0) + (DELAY + (ABSOLUTE + (PORT dataa (411:411:411) (510:510:510)) + (PORT datab (411:411:411) (504:504:504)) + (PORT datac (1058:1058:1058) (1236:1236:1236)) + (PORT datad (935:935:935) (1080:1080:1080)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal50\~0) + (DELAY + (ABSOLUTE + (PORT dataa (672:672:672) (774:774:774)) + (PORT datac (519:519:519) (602:602:602)) + (PORT datad (662:662:662) (767:767:767)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (410:410:410)) + (PORT datac (373:373:373) (445:445:445)) + (PORT datad (488:488:488) (565:565:565)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) + (DELAY + (ABSOLUTE + (PORT dataa (762:762:762) (924:924:924)) + (PORT datab (1245:1245:1245) (1493:1493:1493)) + (PORT datac (203:203:203) (251:251:251)) + (PORT datad (175:175:175) (233:233:233)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (925:925:925) (906:906:906)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|DFF_inst5\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (663:663:663) (764:764:764)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|DFF_inst5) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (919:919:919) (901:901:901)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (194:194:194)) + (PORT datad (661:661:661) (762:762:762)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (918:918:918) (901:901:901)) + (PORT ena (646:646:646) (704:704:704)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) + (DELAY + (ABSOLUTE + (PORT datab (843:843:843) (990:990:990)) + (PORT datac (655:655:655) (765:765:765)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (764:764:764)) + (PORT datab (663:663:663) (753:753:753)) + (PORT datac (1275:1275:1275) (1482:1482:1482)) + (PORT datad (196:196:196) (232:232:232)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1280:1280:1280) (1486:1486:1486)) + (PORT datab (1233:1233:1233) (1453:1453:1453)) + (PORT datac (686:686:686) (799:799:799)) + (PORT datad (499:499:499) (573:573:573)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_inst4) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (890:890:890)) + (PORT ena (420:420:420) (448:448:448)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~3) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (256:256:256)) + (PORT datab (120:120:120) (154:154:154)) + (PORT datac (556:556:556) (656:656:656)) + (PORT datad (837:837:837) (971:971:971)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M4_ff\~0) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (283:283:283)) + (PORT datab (386:386:386) (465:465:465)) + (PORT datad (494:494:494) (572:572:572)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M4_ff) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (918:918:918) (901:901:901)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1402:1402:1402) (1642:1642:1642)) + (PORT datab (866:866:866) (1015:1015:1015)) + (PORT datac (659:659:659) (783:783:783)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1434:1434:1434) (1652:1652:1652)) + (PORT datac (1408:1408:1408) (1660:1660:1660)) + (PORT datad (1036:1036:1036) (1194:1194:1194)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1092:1092:1092) (1258:1258:1258)) + (PORT datab (1172:1172:1172) (1380:1380:1380)) + (PORT datac (836:836:836) (990:990:990)) + (PORT datad (111:111:111) (136:136:136)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~4) + (DELAY + (ABSOLUTE + (PORT datab (1400:1400:1400) (1645:1645:1645)) + (PORT datac (1217:1217:1217) (1400:1400:1400)) + (PORT datad (823:823:823) (960:960:960)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (421:421:421)) + (PORT datac (834:834:834) (966:966:966)) + (PORT datad (352:352:352) (425:425:425)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~5) + (DELAY + (ABSOLUTE + (PORT datac (312:312:312) (377:377:377)) + (PORT datad (355:355:355) (428:428:428)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~2) + (DELAY + (ABSOLUTE + (PORT datab (647:647:647) (759:759:759)) + (PORT datac (832:832:832) (977:977:977)) + (PORT datad (661:661:661) (784:784:784)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~2) + (DELAY + (ABSOLUTE + (PORT datab (935:935:935) (1113:1113:1113)) + (PORT datad (926:926:926) (1075:1075:1075)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1433:1433:1433) (1651:1651:1651)) + (PORT datab (1434:1434:1434) (1688:1688:1688)) + (PORT datac (840:840:840) (995:995:995)) + (PORT datad (1038:1038:1038) (1195:1195:1195)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (173:173:173)) + (PORT datab (483:483:483) (557:557:557)) + (PORT datac (722:722:722) (838:838:838)) + (PORT datad (450:450:450) (533:533:533)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT datab (955:955:955) (1140:1140:1140)) + (PORT datad (1016:1016:1016) (1186:1186:1186)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|table_xx\~0) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (285:285:285)) + (PORT datad (136:136:136) (176:176:176)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~7) + (DELAY + (ABSOLUTE + (PORT dataa (955:955:955) (1108:1108:1108)) + (PORT datab (626:626:626) (727:727:727)) + (PORT datac (501:501:501) (587:587:587)) + (PORT datad (1095:1095:1095) (1255:1255:1255)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~0) + (DELAY + (ABSOLUTE + (PORT datac (588:588:588) (701:701:701)) + (PORT datad (694:694:694) (826:826:826)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (651:651:651)) + (PORT datab (822:822:822) (952:952:952)) + (PORT datac (584:584:584) (674:674:674)) + (PORT datad (106:106:106) (125:125:125)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~3) + (DELAY + (ABSOLUTE + (PORT dataa (543:543:543) (648:648:648)) + (PORT datab (413:413:413) (503:503:503)) + (PORT datac (498:498:498) (589:589:589)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~5) + (DELAY + (ABSOLUTE + (PORT datac (393:393:393) (480:480:480)) + (PORT datad (392:392:392) (472:472:472)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (407:407:407)) + (PORT datab (345:345:345) (406:406:406)) + (PORT datac (173:173:173) (205:205:205)) + (PORT datad (329:329:329) (374:374:374)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (144:144:144)) + (PORT datab (101:101:101) (130:130:130)) + (PORT datac (910:910:910) (1031:1031:1031)) + (PORT datad (335:335:335) (392:392:392)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (487:487:487) (585:585:585)) + (PORT datab (116:116:116) (145:145:145)) + (PORT datac (583:583:583) (685:685:685)) + (PORT datad (724:724:724) (856:856:856)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~3) + (DELAY + (ABSOLUTE + (PORT datab (409:409:409) (506:506:506)) + (PORT datac (525:525:525) (621:621:621)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT datab (927:927:927) (1099:1099:1099)) + (PORT datad (1056:1056:1056) (1230:1230:1230)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (124:124:124) (159:159:159)) + (PORT datab (747:747:747) (857:857:857)) + (PORT datac (929:929:929) (1075:1075:1075)) + (PORT datad (956:956:956) (1092:1092:1092)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~4) + (DELAY + (ABSOLUTE + (PORT datac (348:348:348) (431:431:431)) + (PORT datad (366:366:366) (441:441:441)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~0) + (DELAY + (ABSOLUTE + (PORT datac (589:589:589) (701:701:701)) + (PORT datad (696:696:696) (828:828:828)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1192:1192:1192) (1419:1419:1419)) + (PORT datab (801:801:801) (908:908:908)) + (PORT datac (615:615:615) (693:693:693)) + (PORT datad (338:338:338) (395:395:395)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -13750,85 +2916,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) + (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) (DELAY (ABSOLUTE - (PORT dataa (833:833:833) (979:979:979)) - (PORT datab (187:187:187) (223:223:223)) - (PORT datad (365:365:365) (435:435:435)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (286:286:286)) - (PORT datab (1139:1139:1139) (1327:1327:1327)) - (PORT datad (152:152:152) (195:195:195)) + (PORT dataa (638:638:638) (741:741:741)) + (PORT datab (498:498:498) (585:585:585)) + (PORT datac (769:769:769) (885:885:885)) + (PORT datad (344:344:344) (410:410:410)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (890:890:890) (988:988:988)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (890:890:890) (894:894:894)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (463:463:463)) - (PORT datab (144:144:144) (193:193:193)) - (PORT datac (109:109:109) (134:134:134)) - (PORT datad (808:808:808) (948:948:948)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (723:723:723) (832:832:832)) - (PORT datab (142:142:142) (191:191:191)) - (PORT datac (481:481:481) (565:565:565)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (172:172:172) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -13836,26 +2932,179 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) + (INSTANCE z80_\|pla_decode_\|Equal11\~0) (DELAY (ABSOLUTE - (PORT datab (781:781:781) (906:906:906)) - (PORT datac (840:840:840) (975:975:975)) - (PORT datad (711:711:711) (827:827:827)) + (PORT dataa (1039:1039:1039) (1218:1218:1218)) + (PORT datab (952:952:952) (1136:1136:1136)) + (PORT datac (962:962:962) (1114:1114:1114)) + (PORT datad (471:471:471) (545:545:545)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) + (DELAY + (ABSOLUTE + (PORT datab (893:893:893) (1057:1057:1057)) + (PORT datac (982:982:982) (1155:1155:1155)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) + (DELAY + (ABSOLUTE + (PORT dataa (791:791:791) (918:918:918)) + (PORT datab (847:847:847) (969:969:969)) + (PORT datac (687:687:687) (795:795:795)) + (PORT datad (682:682:682) (781:781:781)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (141:141:141)) + (PORT datab (596:596:596) (688:688:688)) + (PORT datac (936:936:936) (1068:1068:1068)) + (PORT datad (549:549:549) (637:637:637)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (493:493:493) (575:575:575)) + (PORT datab (355:355:355) (417:417:417)) + (PORT datac (1159:1159:1159) (1382:1382:1382)) + (PORT datad (497:497:497) (574:574:574)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal34\~0) + (DELAY + (ABSOLUTE + (PORT dataa (954:954:954) (1107:1107:1107)) + (PORT datab (134:134:134) (169:169:169)) + (PORT datac (500:500:500) (586:586:586)) + (PORT datad (517:517:517) (599:599:599)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~0) + (DELAY + (ABSOLUTE + (PORT datab (956:956:956) (1142:1142:1142)) + (PORT datad (1016:1016:1016) (1186:1186:1186)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (956:956:956) (1109:1109:1109)) + (PORT datab (134:134:134) (168:168:168)) + (PORT datac (501:501:501) (587:587:587)) + (PORT datad (643:643:643) (744:744:744)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (1071:1071:1071)) + (PORT datab (748:748:748) (856:856:856)) + (PORT datac (1414:1414:1414) (1606:1606:1606)) + (PORT datad (618:618:618) (710:710:710)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (494:494:494) (570:570:570)) + (PORT datab (106:106:106) (137:137:137)) + (PORT datac (614:614:614) (723:723:723)) + (PORT datad (521:521:521) (622:622:622)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|M5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (287:287:287)) + (PORT datab (389:389:389) (468:468:468)) + (PORT datad (491:491:491) (569:569:569)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|iff1) + (INSTANCE z80_\|sequencer_\|M5) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (923:923:923)) + (PORT clk (906:906:906) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (739:739:739) (803:803:803)) + (PORT clrn (918:918:918) (901:901:901)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -13866,13 +3115,147 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal2\~1) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) (DELAY (ABSOLUTE - (PORT dataa (872:872:872) (1011:1011:1011)) - (PORT datab (456:456:456) (534:534:534)) - (PORT datac (342:342:342) (402:402:402)) - (PORT datad (233:233:233) (287:287:287)) + (PORT dataa (543:543:543) (647:647:647)) + (PORT datac (378:378:378) (464:464:464)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1312:1312:1312) (1557:1557:1557)) + (PORT datad (685:685:685) (808:808:808)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (407:407:407)) + (PORT datab (746:746:746) (854:854:854)) + (PORT datac (916:916:916) (1049:1049:1049)) + (PORT datad (493:493:493) (572:572:572)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) + (DELAY + (ABSOLUTE + (PORT dataa (494:494:494) (570:570:570)) + (PORT datab (177:177:177) (215:215:215)) + (PORT datac (332:332:332) (384:384:384)) + (PORT datad (107:107:107) (125:125:125)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (743:743:743) (868:868:868)) + (PORT datab (523:523:523) (603:603:603)) + (PORT datac (829:829:829) (980:980:980)) + (PORT datad (662:662:662) (767:767:767)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~5) + (DELAY + (ABSOLUTE + (PORT datab (140:140:140) (187:187:187)) + (PORT datac (127:127:127) (168:168:168)) + (PORT datad (208:208:208) (261:261:261)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (239:239:239) (290:290:290)) + (PORT datab (938:938:938) (1087:1087:1087)) + (PORT datac (1058:1058:1058) (1236:1236:1236)) + (PORT datad (443:443:443) (531:531:531)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (290:290:290)) + (PORT datab (938:938:938) (1087:1087:1087)) + (PORT datac (1057:1057:1057) (1235:1235:1235)) + (PORT datad (443:443:443) (530:530:530)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (240:240:240) (293:293:293)) + (PORT datab (942:942:942) (1092:1092:1092)) + (PORT datac (1063:1063:1063) (1242:1242:1242)) + (PORT datad (449:449:449) (537:537:537)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~0) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (925:925:925)) + (PORT datab (345:345:345) (410:410:410)) + (PORT datac (354:354:354) (419:419:419)) + (PORT datad (347:347:347) (408:408:408)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -13882,12 +3265,92 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal2\~2) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~97) (DELAY (ABSOLUTE - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (301:301:301) (343:343:343)) - (PORT datad (239:239:239) (295:295:295)) + (PORT dataa (366:366:366) (451:451:451)) + (PORT datab (798:798:798) (958:958:958)) + (PORT datac (781:781:781) (935:935:935)) + (PORT datad (378:378:378) (457:457:457)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~96) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (771:771:771)) + (PORT datab (524:524:524) (612:612:612)) + (PORT datac (378:378:378) (464:464:464)) + (PORT datad (388:388:388) (468:468:468)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~98) + (DELAY + (ABSOLUTE + (PORT dataa (758:758:758) (874:874:874)) + (PORT datab (645:645:645) (762:762:762)) + (PORT datac (378:378:378) (464:464:464)) + (PORT datad (388:388:388) (468:468:468)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) + (DELAY + (ABSOLUTE + (PORT dataa (1420:1420:1420) (1646:1646:1646)) + (PORT datab (127:127:127) (154:154:154)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (913:913:913) (1027:1027:1027)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (498:498:498) (593:593:593)) + (PORT datab (177:177:177) (217:217:217)) + (PORT datad (175:175:175) (207:207:207)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (1107:1107:1107)) + (PORT datab (861:861:861) (1009:1009:1009)) + (PORT datac (927:927:927) (1072:1072:1072)) + (PORT datad (993:993:993) (1182:1182:1182)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -13896,13 +3359,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) (DELAY (ABSOLUTE - (PORT dataa (636:636:636) (749:749:749)) - (PORT datab (338:338:338) (394:394:394)) - (PORT datac (873:873:873) (1017:1017:1017)) - (PORT datad (456:456:456) (527:527:527)) + (PORT dataa (637:637:637) (728:728:728)) + (PORT datab (835:835:835) (959:959:959)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (443:443:443) (528:528:528)) + (PORT datac (549:549:549) (647:647:647)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1008:1008:1008) (1168:1168:1168)) + (PORT datab (608:608:608) (719:719:719)) + (PORT datac (965:965:965) (1116:1116:1116)) + (PORT datad (116:116:116) (141:141:141)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -13911,30 +3404,878 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|int_armed) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT dataa (767:767:767) (918:918:918)) + (PORT datad (1121:1121:1121) (1297:1297:1297)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (773:773:773) (890:890:890)) + (PORT datab (460:460:460) (537:537:537)) + (PORT datac (507:507:507) (599:599:599)) + (PORT datad (328:328:328) (382:382:382)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~7) + (DELAY + (ABSOLUTE + (PORT dataa (672:672:672) (774:774:774)) + (PORT datab (142:142:142) (174:174:174)) + (PORT datac (523:523:523) (606:606:606)) + (PORT datad (664:664:664) (769:769:769)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (298:298:298) (344:344:344)) + (PORT datab (771:771:771) (925:925:925)) + (PORT datac (432:432:432) (495:495:495)) + (PORT datad (486:486:486) (585:585:585)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1039:1039:1039) (1217:1217:1217)) + (PORT datab (955:955:955) (1139:1139:1139)) + (PORT datac (966:966:966) (1118:1118:1118)) + (PORT datad (473:473:473) (548:548:548)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~4) + (DELAY + (ABSOLUTE + (PORT datab (902:902:902) (1067:1067:1067)) + (PORT datac (778:778:778) (895:895:895)) + (PORT datad (749:749:749) (871:871:871)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~4) + (DELAY + (ABSOLUTE + (PORT datab (1197:1197:1197) (1407:1407:1407)) + (PORT datad (519:519:519) (618:618:618)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) + (DELAY + (ABSOLUTE + (PORT dataa (509:509:509) (602:602:602)) + (PORT datab (746:746:746) (854:854:854)) + (PORT datac (916:916:916) (1049:1049:1049)) + (PORT datad (656:656:656) (754:754:754)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) + (DELAY + (ABSOLUTE + (PORT dataa (493:493:493) (572:572:572)) + (PORT datab (384:384:384) (460:460:460)) + (PORT datac (510:510:510) (587:587:587)) + (PORT datad (367:367:367) (443:443:443)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (735:735:735)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (483:483:483) (565:565:565)) + (PORT datad (98:98:98) (118:118:118)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (654:654:654)) + (PORT datab (1122:1122:1122) (1279:1279:1279)) + (PORT datac (553:553:553) (639:639:639)) + (PORT datad (617:617:617) (711:711:711)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1371:1371:1371) (1614:1614:1614)) + (PORT datab (676:676:676) (799:799:799)) + (PORT datac (800:800:800) (961:961:961)) + (PORT datad (295:295:295) (336:336:336)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (240:240:240) (292:292:292)) + (PORT datab (409:409:409) (501:501:501)) + (PORT datac (574:574:574) (652:652:652)) + (PORT datad (448:448:448) (536:536:536)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1251:1251:1251) (1482:1482:1482)) + (PORT datab (362:362:362) (428:428:428)) + (PORT datac (461:461:461) (534:534:534)) + (PORT datad (1073:1073:1073) (1267:1267:1267)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal46\~0) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1151:1151:1151)) + (PORT datab (390:390:390) (479:479:479)) + (PORT datac (1026:1026:1026) (1170:1170:1170)) + (PORT datad (923:923:923) (1097:1097:1097)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (462:462:462) (561:561:561)) + (PORT datab (1080:1080:1080) (1265:1265:1265)) + (PORT datac (168:168:168) (199:199:199)) + (PORT datad (940:940:940) (1086:1086:1086)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) + (DELAY + (ABSOLUTE + (PORT dataa (523:523:523) (620:620:620)) + (PORT datab (1084:1084:1084) (1288:1288:1288)) + (PORT datac (1236:1236:1236) (1458:1458:1458)) + (PORT datad (515:515:515) (608:608:608)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~6) + (DELAY + (ABSOLUTE + (PORT datab (938:938:938) (1079:1079:1079)) + (PORT datad (1215:1215:1215) (1390:1390:1390)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (732:732:732) (864:864:864)) + (PORT datab (340:340:340) (412:412:412)) + (PORT datac (460:460:460) (528:528:528)) + (PORT datad (461:461:461) (526:526:526)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (807:807:807) (927:927:927)) + (PORT datab (851:851:851) (977:977:977)) + (PORT datac (688:688:688) (796:796:796)) + (PORT datad (518:518:518) (603:603:603)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (509:509:509) (585:585:585)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal55\~0) + (DELAY + (ABSOLUTE + (PORT dataa (985:985:985) (1147:1147:1147)) + (PORT datab (956:956:956) (1140:1140:1140)) + (PORT datad (1016:1016:1016) (1186:1186:1186)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~7) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (652:652:652)) + (PORT datac (765:765:765) (898:898:898)) + (PORT datad (508:508:508) (587:587:587)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1509:1509:1509) (1731:1731:1731)) + (PORT datab (404:404:404) (477:477:477)) + (PORT datac (554:554:554) (652:652:652)) + (PORT datad (488:488:488) (561:561:561)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (561:561:561) (661:661:661)) + (PORT datac (597:597:597) (676:676:676)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) + (DELAY + (ABSOLUTE + (PORT datab (858:858:858) (1006:1006:1006)) + (PORT datac (663:663:663) (787:787:787)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (551:551:551) (654:654:654)) + (PORT datab (810:810:810) (934:934:934)) + (PORT datac (766:766:766) (899:899:899)) + (PORT datad (509:509:509) (587:587:587)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~17) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (788:788:788)) + (PORT datab (346:346:346) (406:406:406)) + (PORT datac (651:651:651) (742:742:742)) + (PORT datad (1096:1096:1096) (1266:1266:1266)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~0) + (DELAY + (ABSOLUTE + (PORT dataa (686:686:686) (800:800:800)) + (PORT datab (795:795:795) (949:949:949)) + (PORT datac (1257:1257:1257) (1462:1462:1462)) + (PORT datad (1356:1356:1356) (1586:1586:1586)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (457:457:457) (555:555:555)) + (PORT datab (1075:1075:1075) (1260:1260:1260)) + (PORT datac (165:165:165) (196:196:196)) + (PORT datad (933:933:933) (1078:1078:1078)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (754:754:754) (883:883:883)) + (PORT datab (352:352:352) (420:420:420)) + (PORT datac (1251:1251:1251) (1430:1430:1430)) + (PORT datad (1107:1107:1107) (1296:1296:1296)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (685:685:685) (799:799:799)) + (PORT datab (818:818:818) (980:980:980)) + (PORT datac (1255:1255:1255) (1459:1459:1459)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (146:146:146)) + (PORT datab (189:189:189) (226:226:226)) + (PORT datac (442:442:442) (505:505:505)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (1077:1077:1077)) + (PORT datac (497:497:497) (569:569:569)) + (PORT datad (788:788:788) (929:929:929)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (1027:1027:1027)) + (PORT datab (1123:1123:1123) (1280:1280:1280)) + (PORT datac (633:633:633) (721:721:721)) + (PORT datad (105:105:105) (123:123:123)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1510:1510:1510) (1732:1732:1732)) + (PORT datab (569:569:569) (661:661:661)) + (PORT datac (471:471:471) (565:565:565)) + (PORT datad (386:386:386) (452:452:452)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (310:310:310) (365:365:365)) + (PORT datab (442:442:442) (524:524:524)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (527:527:527) (618:618:618)) + (PORT datab (661:661:661) (772:772:772)) + (PORT datac (1052:1052:1052) (1208:1208:1208)) + (PORT datad (342:342:342) (394:394:394)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (1084:1084:1084)) + (PORT datab (297:297:297) (338:338:338)) + (PORT datac (102:102:102) (124:124:124)) + (PORT datad (182:182:182) (216:216:216)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (239:239:239)) + (PORT datab (506:506:506) (599:599:599)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (598:598:598) (680:680:680)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) + (DELAY + (ABSOLUTE + (PORT datab (778:778:778) (933:933:933)) + (PORT datad (527:527:527) (633:633:633)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (400:400:400)) + (PORT datab (460:460:460) (558:558:558)) + (PORT datac (980:980:980) (1134:1134:1134)) + (PORT datad (109:109:109) (129:129:129)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~7) + (DELAY + (ABSOLUTE + (PORT dataa (672:672:672) (783:783:783)) + (PORT datab (474:474:474) (571:571:571)) + (PORT datac (472:472:472) (566:566:566)) + (PORT datad (486:486:486) (560:560:560)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (679:679:679) (788:788:788)) + (PORT datac (549:549:549) (630:630:630)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (482:482:482) (560:560:560)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (104:104:104) (126:126:126)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (401:401:401)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (189:189:189) (223:223:223)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) + (DELAY + (ABSOLUTE + (PORT datab (860:860:860) (1008:1008:1008)) + (PORT datac (927:927:927) (1072:1072:1072)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~16) + (DELAY + (ABSOLUTE + (PORT dataa (768:768:768) (919:919:919)) + (PORT datab (115:115:115) (143:143:143)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (721:721:721) (852:852:852)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1091:1091:1091) (1300:1300:1300)) + (PORT datac (644:644:644) (752:752:752)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~0) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (167:167:167)) + (PORT datab (855:855:855) (1020:1020:1020)) + (PORT datac (963:963:963) (1115:1115:1115)) + (PORT datad (719:719:719) (817:817:817)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~4) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (949:949:949)) + (PORT datab (667:667:667) (775:775:775)) + (PORT datac (347:347:347) (412:412:412)) + (PORT datad (353:353:353) (414:414:414)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT datac (590:590:590) (701:701:701)) + (PORT datad (697:697:697) (829:829:829)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1277:1277:1277) (1502:1502:1502)) + (PORT datac (784:784:784) (944:944:944)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1069:1069:1069) (1255:1255:1255)) + (PORT datab (929:929:929) (1102:1102:1102)) + (PORT datac (822:822:822) (943:943:943)) + (PORT datad (584:584:584) (694:694:694)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~8) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (391:391:391)) + (PORT datab (747:747:747) (848:848:848)) + (PORT datac (342:342:342) (389:389:389)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~9) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (750:750:750)) + (PORT datab (364:364:364) (430:430:430)) + (PORT datac (102:102:102) (122:122:122)) + (PORT datad (326:326:326) (377:377:377)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (911:911:911)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (900:900:900) (904:904:904)) + (PORT clrn (916:916:916) (897:897:897)) + (PORT ena (658:658:658) (719:719:719)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|DFFE_inst44) + (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT asdata (1177:1177:1177) (1361:1361:1361)) - (PORT clrn (928:928:928) (910:910:910)) - (PORT ena (890:890:890) (972:972:972)) + (PORT clk (902:902:902) (909:909:909)) + (PORT asdata (365:365:365) (415:415:415)) + (PORT clrn (915:915:915) (897:897:897)) + (PORT ena (764:764:764) (833:833:833)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -13946,13 +4287,72 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~38) + (INSTANCE z80_\|memory_ifc_\|wait_iorq\~feeder) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (275:275:275)) - (PORT datac (655:655:655) (768:768:768)) - (PORT datad (147:147:147) (189:189:189)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datad (361:361:361) (429:429:429)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorq) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (917:917:917) (898:898:898)) + (PORT ena (667:667:667) (723:723:723)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (900:900:900)) + (PORT asdata (299:299:299) (340:340:340)) + (PORT clrn (917:917:917) (898:898:898)) + (PORT ena (667:667:667) (723:723:723)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|iorq\~0) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (184:184:184)) + (PORT datad (360:360:360) (427:427:427)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~2) + (DELAY + (ABSOLUTE + (PORT dataa (896:896:896) (1044:1044:1044)) + (PORT datac (806:806:806) (925:925:925)) + (PORT datad (662:662:662) (766:766:766)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -13960,77 +4360,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~91) + (INSTANCE z80_\|execute_\|ixy_d\~17) (DELAY (ABSOLUTE - (PORT dataa (942:942:942) (1111:1111:1111)) - (PORT datab (680:680:680) (788:788:788)) - (PORT datac (543:543:543) (644:644:644)) - (PORT datad (466:466:466) (541:541:541)) + (PORT dataa (120:120:120) (153:153:153)) + (PORT datab (115:115:115) (149:149:149)) + (PORT datac (553:553:553) (651:651:651)) + (PORT datad (831:831:831) (963:963:963)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~45) + (INSTANCE z80_\|execute_\|ctl_mWrite\~15) (DELAY (ABSOLUTE - (PORT dataa (584:584:584) (679:679:679)) - (PORT datab (394:394:394) (470:470:470)) - (PORT datac (663:663:663) (783:783:783)) - (PORT datad (349:349:349) (403:403:403)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~44) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (679:679:679)) - (PORT datab (514:514:514) (601:601:601)) - (PORT datac (474:474:474) (540:540:540)) - (PORT datad (588:588:588) (671:671:671)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~46) - (DELAY - (ABSOLUTE - (PORT dataa (172:172:172) (212:212:212)) - (PORT datab (395:395:395) (471:471:471)) - (PORT datac (92:92:92) (114:114:114)) - (PORT datad (592:592:592) (676:676:676)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~37) - (DELAY - (ABSOLUTE - (PORT dataa (643:643:643) (753:753:753)) - (PORT datab (502:502:502) (579:579:579)) - (PORT datac (578:578:578) (652:652:652)) - (PORT datad (106:106:106) (124:124:124)) + (PORT dataa (670:670:670) (779:779:779)) + (PORT datab (1054:1054:1054) (1212:1212:1212)) + (PORT datac (584:584:584) (688:688:688)) + (PORT datad (580:580:580) (682:682:682)) (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -14040,16 +4392,1051 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~50) + (INSTANCE z80_\|execute_\|ctl_mWrite\~18) (DELAY (ABSOLUTE - (PORT dataa (442:442:442) (518:518:518)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (892:892:892) (1053:1053:1053)) - (PORT datad (1280:1280:1280) (1481:1481:1481)) - (IOPATH dataa combout (166:166:166) (157:157:157)) + (PORT dataa (984:984:984) (1154:1154:1154)) + (PORT datab (348:348:348) (408:408:408)) + (PORT datad (921:921:921) (1090:1090:1090)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~12) + (DELAY + (ABSOLUTE + (PORT dataa (497:497:497) (578:578:578)) + (PORT datab (687:687:687) (795:795:795)) + (PORT datac (446:446:446) (516:516:516)) + (PORT datad (98:98:98) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~21) + (DELAY + (ABSOLUTE + (PORT dataa (525:525:525) (622:622:622)) + (PORT datab (536:536:536) (635:635:635)) + (PORT datac (1128:1128:1128) (1307:1307:1307)) + (PORT datad (843:843:843) (988:988:988)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~20) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (420:420:420)) + (PORT datab (840:840:840) (984:984:984)) + (PORT datac (967:967:967) (1130:1130:1130)) + (PORT datad (342:342:342) (399:399:399)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (400:400:400)) + (PORT datab (998:998:998) (1153:1153:1153)) + (PORT datac (492:492:492) (573:573:573)) + (PORT datad (311:311:311) (345:345:345)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (316:316:316) (371:371:371)) + (PORT datab (350:350:350) (417:417:417)) + (PORT datac (786:786:786) (916:916:916)) + (PORT datad (996:996:996) (1163:1163:1163)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~10) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (395:395:395)) + (PORT datab (642:642:642) (742:742:742)) + (PORT datac (502:502:502) (584:584:584)) + (PORT datad (100:100:100) (121:121:121)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~13) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (389:389:389)) + (PORT datab (1000:1000:1000) (1149:1149:1149)) + (PORT datac (463:463:463) (538:538:538)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~9) + (DELAY + (ABSOLUTE + (PORT datab (1489:1489:1489) (1764:1764:1764)) + (PORT datac (1107:1107:1107) (1306:1306:1306)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) + (DELAY + (ABSOLUTE + (PORT dataa (933:933:933) (1075:1075:1075)) + (PORT datab (940:940:940) (1062:1062:1062)) + (PORT datac (726:726:726) (832:832:832)) + (PORT datad (618:618:618) (716:716:716)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (590:590:590)) + (PORT datab (672:672:672) (794:794:794)) + (PORT datac (363:363:363) (442:442:442)) + (PORT datad (370:370:370) (436:436:436)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (469:469:469)) + (PORT datab (106:106:106) (137:137:137)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (651:651:651) (737:737:737)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (819:819:819)) + (PORT datab (603:603:603) (694:694:694)) + (PORT datac (779:779:779) (896:896:896)) + (PORT datad (102:102:102) (118:118:118)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (951:951:951)) + (PORT datab (839:839:839) (992:992:992)) + (PORT datac (796:796:796) (927:927:927)) + (PORT datad (777:777:777) (894:894:894)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~11) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (147:147:147)) + (PORT datab (344:344:344) (409:409:409)) + (PORT datac (1005:1005:1005) (1145:1145:1145)) + (PORT datad (348:348:348) (409:409:409)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~25) + (DELAY + (ABSOLUTE + (PORT datac (664:664:664) (784:784:784)) + (PORT datad (658:658:658) (754:754:754)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~22) + (DELAY + (ABSOLUTE + (PORT dataa (807:807:807) (956:956:956)) + (PORT datab (620:620:620) (711:711:711)) + (PORT datac (356:356:356) (421:421:421)) + (PORT datad (824:824:824) (967:967:967)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~24) + (DELAY + (ABSOLUTE + (PORT datac (669:669:669) (789:789:789)) + (PORT datad (663:663:663) (760:760:760)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (418:418:418)) + (PORT datab (132:132:132) (161:161:161)) + (PORT datac (513:513:513) (594:594:594)) + (PORT datad (449:449:449) (515:515:515)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~14) + (DELAY + (ABSOLUTE + (PORT dataa (512:512:512) (592:592:592)) + (PORT datab (501:501:501) (582:582:582)) + (PORT datac (491:491:491) (567:567:567)) + (PORT datad (316:316:316) (367:367:367)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (793:793:793) (971:971:971)) + (PORT datad (675:675:675) (789:789:789)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~16) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (400:400:400)) + (PORT datab (445:445:445) (519:519:519)) + (PORT datac (604:604:604) (685:685:685)) + (PORT datad (1336:1336:1336) (1531:1531:1531)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (922:922:922) (903:903:903)) + (PORT ena (623:623:623) (673:673:673)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (118:118:118) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mwr) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (922:922:922) (903:903:903)) + (PORT ena (609:609:609) (652:652:652)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|mwr_wr\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (493:493:493) (578:578:578)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|mwr_wr) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (917:917:917) (898:898:898)) + (PORT ena (667:667:667) (723:723:723)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (152:152:152)) + (PORT datab (133:133:133) (182:182:182)) + (PORT datac (582:582:582) (688:688:688)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff1) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (917:917:917) (898:898:898)) + (PORT ena (667:667:667) (723:723:723)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1\~0) + (DELAY + (ABSOLUTE + (PORT datad (118:118:118) (155:155:155)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (917:917:917) (898:898:898)) + (PORT ena (667:667:667) (723:723:723)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff3) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (911:911:911)) + (PORT asdata (298:298:298) (339:339:339)) + (PORT clrn (917:917:917) (898:898:898)) + (PORT ena (681:681:681) (744:744:744)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (707:707:707)) + (PORT datab (134:134:134) (183:183:183)) + (PORT datad (754:754:754) (862:862:862)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (650:650:650)) + (PORT datab (124:124:124) (156:156:156)) + (PORT datac (585:585:585) (674:674:674)) + (PORT datad (806:806:806) (929:929:929)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~0) + (DELAY + (ABSOLUTE + (PORT dataa (736:736:736) (860:860:860)) + (PORT datab (531:531:531) (627:627:627)) + (PORT datac (659:659:659) (757:757:757)) + (PORT datad (810:810:810) (914:914:914)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~10) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1143:1143:1143)) + (PORT datab (952:952:952) (1137:1137:1137)) + (PORT datac (592:592:592) (699:699:699)) + (PORT datad (1016:1016:1016) (1187:1187:1187)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~4) + (DELAY + (ABSOLUTE + (PORT datab (926:926:926) (1099:1099:1099)) + (PORT datad (1056:1056:1056) (1230:1230:1230)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) + (DELAY + (ABSOLUTE + (PORT dataa (141:141:141) (176:176:176)) + (PORT datab (1011:1011:1011) (1204:1204:1204)) + (PORT datac (769:769:769) (909:909:909)) + (PORT datad (1617:1617:1617) (1861:1861:1861)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~1) + (DELAY + (ABSOLUTE + (PORT dataa (140:140:140) (175:175:175)) + (PORT datab (531:531:531) (627:627:627)) + (PORT datac (659:659:659) (757:757:757)) + (PORT datad (974:974:974) (1127:1127:1127)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (720:720:720)) + (PORT datab (116:116:116) (145:145:145)) + (PORT datac (771:771:771) (873:873:873)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (1019:1019:1019)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (95:95:95) (120:120:120)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (304:304:304)) + (PORT datad (315:315:315) (372:372:372)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_im_we) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (947:947:947)) + (PORT datab (801:801:801) (917:917:917)) + (PORT datac (784:784:784) (945:945:945)) + (PORT datad (1424:1424:1424) (1645:1645:1645)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im2) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (524:524:524) (568:568:568)) + (PORT clrn (917:917:917) (902:902:902)) + (PORT ena (498:498:498) (538:538:538)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (253:253:253)) + (PORT datab (459:459:459) (544:544:544)) + (PORT datad (148:148:148) (192:192:192)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~3) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (1041:1041:1041)) + (PORT datab (142:142:142) (175:175:175)) + (PORT datac (803:803:803) (922:922:922)) + (PORT datad (665:665:665) (769:769:769)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (946:946:946) (1099:1099:1099)) + (PORT datab (125:125:125) (159:159:159)) + (PORT datac (989:989:989) (1138:1138:1138)) + (PORT datad (457:457:457) (549:549:549)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (285:285:285)) + (PORT datab (712:712:712) (831:831:831)) + (PORT datac (747:747:747) (859:859:859)) + (PORT datad (349:349:349) (408:408:408)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~31) + (DELAY + (ABSOLUTE + (PORT datab (351:351:351) (401:401:401)) + (PORT datac (456:456:456) (532:532:532)) + (PORT datad (458:458:458) (519:519:519)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (293:293:293)) + (PORT datab (943:943:943) (1093:1093:1093)) + (PORT datac (1064:1064:1064) (1243:1243:1243)) + (PORT datad (450:450:450) (538:538:538)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) + (DELAY + (ABSOLUTE + (PORT datab (804:804:804) (934:934:934)) + (PORT datac (654:654:654) (752:752:752)) + (PORT datad (799:799:799) (923:923:923)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal44\~0) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (507:507:507)) + (PORT datab (410:410:410) (503:503:503)) + (PORT datac (1060:1060:1060) (1238:1238:1238)) + (PORT datad (938:938:938) (1083:1083:1083)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~6) + (DELAY + (ABSOLUTE + (PORT dataa (493:493:493) (575:575:575)) + (PORT datab (572:572:572) (675:675:675)) + (PORT datac (803:803:803) (922:922:922)) + (PORT datad (835:835:835) (969:969:969)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~5) + (DELAY + (ABSOLUTE + (PORT dataa (502:502:502) (576:576:576)) + (PORT datab (510:510:510) (622:622:622)) + (PORT datac (585:585:585) (687:687:687)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~17) + (DELAY + (ABSOLUTE + (PORT datab (355:355:355) (421:421:421)) + (PORT datac (442:442:442) (500:500:500)) + (PORT datad (455:455:455) (517:517:517)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (1042:1042:1042)) + (PORT datac (804:804:804) (923:923:923)) + (PORT datad (664:664:664) (768:768:768)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal49\~0) + (DELAY + (ABSOLUTE + (PORT dataa (820:820:820) (946:946:946)) + (PORT datab (539:539:539) (629:629:629)) + (PORT datac (656:656:656) (749:749:749)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~57) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (758:758:758)) + (PORT datab (357:357:357) (421:421:421)) + (PORT datac (912:912:912) (1043:1043:1043)) + (PORT datad (492:492:492) (577:577:577)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1008:1008:1008) (1168:1168:1168)) + (PORT datab (608:608:608) (720:720:720)) + (PORT datac (964:964:964) (1116:1116:1116)) + (PORT datad (117:117:117) (141:141:141)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal25\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1190:1190:1190) (1417:1417:1417)) + (PORT datab (1476:1476:1476) (1702:1702:1702)) + (PORT datac (782:782:782) (932:932:932)) + (PORT datad (473:473:473) (552:552:552)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1271:1271:1271) (1460:1460:1460)) + (PORT datab (121:121:121) (151:151:151)) + (PORT datac (338:338:338) (398:398:398)) + (PORT datad (568:568:568) (663:663:663)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) + (DELAY + (ABSOLUTE + (PORT datab (897:897:897) (1044:1044:1044)) + (PORT datac (686:686:686) (796:796:796)) + (PORT datad (617:617:617) (704:704:704)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (736:736:736) (859:859:859)) + (PORT datab (526:526:526) (606:606:606)) + (PORT datac (819:819:819) (969:969:969)) + (PORT datad (667:667:667) (773:773:773)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~16) + (DELAY + (ABSOLUTE + (PORT dataa (493:493:493) (574:574:574)) + (PORT datab (568:568:568) (671:671:671)) + (PORT datac (807:807:807) (926:926:926)) + (PORT datad (828:828:828) (960:960:960)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (434:434:434) (499:499:499)) + (PORT datab (319:319:319) (371:371:371)) + (PORT datac (911:911:911) (1033:1033:1033)) + (PORT datad (881:881:881) (996:996:996)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (423:423:423)) + (PORT datac (612:612:612) (704:704:704)) + (PORT datad (462:462:462) (553:553:553)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal29\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1193:1193:1193) (1420:1420:1420)) + (PORT datab (358:358:358) (420:420:420)) + (PORT datac (601:601:601) (709:709:709)) + (PORT datad (478:478:478) (548:548:548)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~38) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (233:233:233)) + (PORT datab (202:202:202) (239:239:239)) + (PORT datac (352:352:352) (430:430:430)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal35\~0) + (DELAY + (ABSOLUTE + (PORT dataa (764:764:764) (868:868:868)) + (PORT datab (1070:1070:1070) (1233:1233:1233)) + (PORT datac (501:501:501) (587:587:587)) + (PORT datad (120:120:120) (145:145:145)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -14059,124 +5446,12 @@ (INSTANCE z80_\|execute_\|pc_inc_hold\~33) (DELAY (ABSOLUTE - (PORT dataa (121:121:121) (155:155:155)) - (PORT datab (650:650:650) (755:755:755)) - (PORT datac (592:592:592) (674:674:674)) - (PORT datad (314:314:314) (365:365:365)) + (PORT dataa (1742:1742:1742) (2009:2009:2009)) + (PORT datab (462:462:462) (540:540:540)) + (PORT datac (842:842:842) (990:990:990)) + (PORT datad (1111:1111:1111) (1269:1269:1269)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (943:943:943) (1083:1083:1083)) - (PORT datab (328:328:328) (388:388:388)) - (PORT datac (902:902:902) (1048:1048:1048)) - (PORT datad (656:656:656) (761:761:761)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (481:481:481)) - (PORT datab (368:368:368) (440:440:440)) - (PORT datac (623:623:623) (726:726:726)) - (PORT datad (114:114:114) (137:137:137)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~31) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (697:697:697)) - (PORT datab (455:455:455) (525:525:525)) - (PORT datac (683:683:683) (777:777:777)) - (PORT datad (442:442:442) (508:508:508)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~32) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (697:697:697)) - (PORT datab (329:329:329) (389:389:389)) - (PORT datac (110:110:110) (135:135:135)) - (PORT datad (915:915:915) (1056:1056:1056)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~34) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (103:103:103) (132:132:132)) - (PORT datad (93:93:93) (113:113:113)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~51) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (744:744:744)) - (PORT datab (786:786:786) (922:922:922)) - (PORT datac (1403:1403:1403) (1620:1620:1620)) - (PORT datad (839:839:839) (994:994:994)) - (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~30) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (454:454:454)) - (PORT datab (652:652:652) (755:755:755)) - (PORT datac (193:193:193) (227:227:227)) - (PORT datad (461:461:461) (529:529:529)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -14184,156 +5459,56 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~52) + (INSTANCE z80_\|execute_\|comb\~1) (DELAY (ABSOLUTE - (PORT dataa (846:846:846) (1011:1011:1011)) - (PORT datab (783:783:783) (918:918:918)) - (PORT datac (1408:1408:1408) (1626:1626:1626)) - (PORT datad (595:595:595) (700:700:700)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datab (991:991:991) (1168:1168:1168)) + (PORT datad (1314:1314:1314) (1503:1503:1503)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~35) + (INSTANCE z80_\|execute_\|ctl_mRead\~13) (DELAY (ABSOLUTE - (PORT dataa (192:192:192) (236:236:236)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (324:324:324) (385:385:385)) - (PORT datad (94:94:94) (112:112:112)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~36) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (697:697:697)) - (PORT datab (345:345:345) (407:407:407)) - (PORT datac (335:335:335) (384:384:384)) - (PORT datad (773:773:773) (885:885:885)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1139:1139:1139) (1333:1333:1333)) - (PORT datab (514:514:514) (601:601:601)) - (PORT datac (788:788:788) (904:904:904)) - (PORT datad (352:352:352) (421:421:421)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (749:749:749) (876:876:876)) - (PORT datab (989:989:989) (1158:1158:1158)) - (PORT datad (354:354:354) (418:418:418)) + (PORT dataa (478:478:478) (574:574:574)) + (PORT datab (200:200:200) (244:244:244)) + (PORT datac (991:991:991) (1140:1140:1140)) + (PORT datad (95:95:95) (114:114:114)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) (DELAY (ABSOLUTE - (PORT dataa (114:114:114) (148:148:148)) - (PORT datab (115:115:115) (147:147:147)) - (PORT datac (366:366:366) (431:431:431)) - (PORT datad (302:302:302) (349:349:349)) + (PORT dataa (658:658:658) (763:763:763)) + (PORT datab (999:999:999) (1153:1153:1153)) + (PORT datac (319:319:319) (370:370:370)) + (PORT datad (336:336:336) (388:388:388)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~43) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) (DELAY (ABSOLUTE - (PORT dataa (791:791:791) (908:908:908)) - (PORT datab (369:369:369) (428:428:428)) - (PORT datac (1100:1100:1100) (1281:1281:1281)) - (PORT datad (710:710:710) (816:816:816)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) - (DELAY - (ABSOLUTE - (PORT dataa (109:109:109) (142:142:142)) - (PORT datab (117:117:117) (145:145:145)) - (PORT datac (346:346:346) (410:410:410)) - (PORT datad (101:101:101) (123:123:123)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (241:241:241)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (341:341:341) (395:395:395)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (433:433:433)) - (PORT datab (393:393:393) (469:469:469)) - (PORT datac (344:344:344) (398:398:398)) - (PORT datad (642:642:642) (741:741:741)) - (IOPATH dataa combout (159:159:159) (163:163:163)) + (PORT datab (486:486:486) (566:566:566)) + (PORT datac (505:505:505) (592:592:592)) + (PORT datad (311:311:311) (360:360:360)) (IOPATH datab combout (166:166:166) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -14342,29 +5517,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~53) + (INSTANCE z80_\|pla_decode_\|Equal40\~2) (DELAY (ABSOLUTE - (PORT dataa (920:920:920) (1083:1083:1083)) - (PORT datab (591:591:591) (704:704:704)) - (PORT datac (328:328:328) (388:388:388)) - (PORT datad (545:545:545) (639:639:639)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~39) - (DELAY - (ABSOLUTE - (PORT dataa (113:113:113) (147:147:147)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (334:334:334) (383:383:383)) - (PORT datad (297:297:297) (344:344:344)) + (PORT dataa (1060:1060:1060) (1223:1223:1223)) + (PORT datab (944:944:944) (1126:1126:1126)) + (PORT datac (332:332:332) (390:390:390)) + (PORT datad (974:974:974) (1126:1126:1126)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -14374,45 +5533,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~47) + (INSTANCE z80_\|execute_\|setM1\~36) (DELAY (ABSOLUTE - (PORT dataa (203:203:203) (238:238:238)) - (PORT datab (110:110:110) (143:143:143)) - (PORT datac (346:346:346) (409:409:409)) - (PORT datad (104:104:104) (121:121:121)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) - (DELAY - (ABSOLUTE - (PORT dataa (117:117:117) (149:149:149)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (472:472:472) (539:539:539)) - (PORT datad (102:102:102) (120:120:120)) + (PORT dataa (469:469:469) (554:554:554)) + (PORT datab (179:179:179) (218:218:218)) + (PORT datac (1105:1105:1105) (1295:1295:1295)) + (PORT datad (600:600:600) (673:673:673)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) - (DELAY - (ABSOLUTE - (PORT datab (108:108:108) (139:139:139)) - (PORT datac (353:353:353) (411:411:411)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -14420,29 +5549,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) + (INSTANCE z80_\|execute_\|pc_inc_hold\~14) (DELAY (ABSOLUTE - (PORT dataa (109:109:109) (143:143:143)) - (PORT datab (174:174:174) (214:214:214)) - (PORT datac (343:343:343) (397:397:397)) - (PORT datad (96:96:96) (117:117:117)) + (PORT dataa (120:120:120) (153:153:153)) + (PORT datab (142:142:142) (176:176:176)) + (PORT datac (175:175:175) (209:209:209)) + (PORT datad (102:102:102) (126:126:126)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) + (INSTANCE z80_\|execute_\|setM1\~37) (DELAY (ABSOLUTE - (PORT dataa (369:369:369) (435:435:435)) - (PORT datab (517:517:517) (604:604:604)) - (PORT datac (663:663:663) (782:782:782)) - (PORT datad (99:99:99) (121:121:121)) + (PORT dataa (640:640:640) (740:740:740)) + (PORT datab (346:346:346) (409:409:409)) + (PORT datac (520:520:520) (609:609:609)) + (PORT datad (643:643:643) (736:736:736)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -14452,29 +5581,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) + (INSTANCE z80_\|execute_\|ctl_mRead\~14) (DELAY (ABSOLUTE - (PORT dataa (483:483:483) (566:566:566)) - (PORT datab (377:377:377) (447:447:447)) - (PORT datac (546:546:546) (641:641:641)) - (PORT datad (345:345:345) (406:406:406)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (948:948:948) (1101:1101:1101)) + (PORT datab (744:744:744) (855:855:855)) + (PORT datac (991:991:991) (1140:1140:1140)) + (PORT datad (117:117:117) (142:142:142)) + (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) + (INSTANCE z80_\|execute_\|setM1\~39) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (383:383:383) (458:458:458)) - (PORT datac (538:538:538) (636:636:636)) - (PORT datad (919:919:919) (1050:1050:1050)) + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (342:342:342) (393:393:393)) + (PORT datad (460:460:460) (521:521:521)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -14484,42 +5613,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) + (INSTANCE z80_\|execute_\|ctl_mRead\~32) (DELAY (ABSOLUTE - (PORT dataa (108:108:108) (142:142:142)) - (PORT datab (173:173:173) (210:210:210)) - (PORT datac (343:343:343) (396:396:396)) - (PORT datad (183:183:183) (213:213:213)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) - (DELAY - (ABSOLUTE - (PORT datab (106:106:106) (136:136:136)) - (PORT datac (93:93:93) (117:117:117)) - (PORT datad (93:93:93) (112:112:112)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~42) - (DELAY - (ABSOLUTE - (PORT datab (341:341:341) (404:404:404)) - (PORT datac (176:176:176) (211:211:211)) - (PORT datad (94:94:94) (113:113:113)) + (PORT dataa (679:679:679) (777:777:777)) + (PORT datab (190:190:190) (230:230:230)) + (PORT datac (1034:1034:1034) (1191:1191:1191)) + (PORT datad (318:318:318) (372:372:372)) + (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -14528,13 +5629,265 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~90) + (INSTANCE z80_\|pla_decode_\|Equal40\~0) (DELAY (ABSOLUTE - (PORT dataa (563:563:563) (668:668:668)) - (PORT datab (610:610:610) (722:722:722)) - (PORT datac (648:648:648) (744:744:744)) - (PORT datad (838:838:838) (993:993:993)) + (PORT dataa (1433:1433:1433) (1652:1652:1652)) + (PORT datab (1432:1432:1432) (1685:1685:1685)) + (PORT datad (1037:1037:1037) (1195:1195:1195)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1063:1063:1063) (1225:1225:1225)) + (PORT datab (487:487:487) (565:565:565)) + (PORT datac (931:931:931) (1095:1095:1095)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (955:955:955) (1109:1109:1109)) + (PORT datab (622:622:622) (733:733:733)) + (PORT datac (501:501:501) (587:587:587)) + (PORT datad (120:120:120) (145:145:145)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (519:519:519) (597:597:597)) + (PORT datab (774:774:774) (869:869:869)) + (PORT datac (325:325:325) (388:388:388)) + (PORT datad (441:441:441) (506:506:506)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1060:1060:1060) (1223:1223:1223)) + (PORT datab (944:944:944) (1125:1125:1125)) + (PORT datac (332:332:332) (390:390:390)) + (PORT datad (974:974:974) (1126:1126:1126)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1263:1263:1263) (1450:1450:1450)) + (PORT datab (484:484:484) (560:560:560)) + (PORT datac (885:885:885) (1057:1057:1057)) + (PORT datad (949:949:949) (1083:1083:1083)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (496:496:496) (585:585:585)) + (PORT datab (886:886:886) (1031:1031:1031)) + (PORT datac (662:662:662) (769:769:769)) + (PORT datad (940:940:940) (1066:1066:1066)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (492:492:492)) + (PORT datab (897:897:897) (1044:1044:1044)) + (PORT datac (687:687:687) (797:797:797)) + (PORT datad (617:617:617) (705:705:705)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1187:1187:1187) (1413:1413:1413)) + (PORT datab (801:801:801) (907:907:907)) + (PORT datac (614:614:614) (693:693:693)) + (PORT datad (337:337:337) (393:393:393)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~0) + (DELAY + (ABSOLUTE + (PORT dataa (500:500:500) (599:599:599)) + (PORT datab (292:292:292) (343:343:343)) + (PORT datac (296:296:296) (337:337:337)) + (PORT datad (298:298:298) (342:342:342)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~1) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (114:114:114) (143:143:143)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (119:119:119) (138:138:138)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (496:496:496) (574:574:574)) + (PORT datab (384:384:384) (458:458:458)) + (PORT datac (720:720:720) (818:818:818)) + (PORT datad (654:654:654) (750:750:750)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (592:592:592)) + (PORT datab (821:821:821) (954:954:954)) + (PORT datac (485:485:485) (558:558:558)) + (PORT datad (114:114:114) (135:135:135)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (481:481:481) (563:563:563)) + (PORT datab (381:381:381) (463:463:463)) + (PORT datac (164:164:164) (194:194:194)) + (PORT datad (456:456:456) (533:533:533)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (420:420:420)) + (PORT datab (495:495:495) (576:576:576)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (470:470:470) (541:541:541)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~1) + (DELAY + (ABSOLUTE + (PORT dataa (239:239:239) (291:291:291)) + (PORT datab (590:590:590) (670:670:670)) + (PORT datac (387:387:387) (484:484:484)) + (PORT datad (391:391:391) (478:478:478)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (389:389:389)) + (PORT datab (349:349:349) (410:410:410)) + (PORT datac (310:310:310) (359:359:359)) + (PORT datad (361:361:361) (421:421:421)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -14544,124 +5897,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~41) + (INSTANCE z80_\|execute_\|ctl_mRead\~27) (DELAY (ABSOLUTE - (PORT dataa (122:122:122) (161:161:161)) - (PORT datab (330:330:330) (390:390:390)) - (PORT datac (110:110:110) (135:135:135)) - (PORT datad (93:93:93) (112:112:112)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (281:281:281)) - (PORT datab (508:508:508) (586:586:586)) - (PORT datac (652:652:652) (766:766:766)) - (PORT datad (149:149:149) (193:193:193)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (698:698:698)) - (PORT datab (122:122:122) (152:152:152)) - (PORT datac (106:106:106) (136:136:136)) - (PORT datad (491:491:491) (559:559:559)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) - (DELAY - (ABSOLUTE - (PORT dataa (808:808:808) (935:935:935)) - (PORT datab (101:101:101) (129:129:129)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (916:916:916) (1058:1058:1058)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (698:698:698)) - (PORT datab (124:124:124) (156:156:156)) - (PORT datac (106:106:106) (136:136:136)) - (PORT datad (315:315:315) (367:367:367)) + (PORT dataa (466:466:466) (537:537:537)) + (PORT datab (324:324:324) (384:384:384)) + (PORT datac (842:842:842) (968:968:968)) + (PORT datad (102:102:102) (125:125:125)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) + (INSTANCE z80_\|execute_\|ctl_mRead\~28) (DELAY (ABSOLUTE - (PORT dataa (458:458:458) (529:529:529)) - (PORT datab (627:627:627) (716:716:716)) - (PORT datac (177:177:177) (212:212:212)) - (PORT datad (470:470:470) (537:537:537)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (741:741:741)) - (PORT datab (191:191:191) (229:229:229)) - (PORT datac (157:157:157) (183:183:183)) - (PORT datad (88:88:88) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (166:166:166) (197:197:197)) + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (494:494:494) (571:571:571)) + (PORT datac (314:314:314) (368:368:368)) (PORT datad (90:90:90) (108:108:108)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) @@ -14672,14 +5929,146 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) + (INSTANCE z80_\|execute_\|nextM\~3) (DELAY (ABSOLUTE - (PORT dataa (360:360:360) (432:432:432)) - (PORT datab (211:211:211) (252:252:252)) - (PORT datac (603:603:603) (696:696:696)) - (PORT datad (467:467:467) (541:541:541)) - (IOPATH dataa combout (166:166:166) (157:157:157)) + (PORT dataa (340:340:340) (405:405:405)) + (PORT datab (674:674:674) (788:788:788)) + (PORT datad (486:486:486) (558:558:558)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (758:758:758)) + (PORT datab (347:347:347) (411:411:411)) + (PORT datac (105:105:105) (128:128:128)) + (PORT datad (1337:1337:1337) (1531:1531:1531)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (430:430:430) (496:496:496)) + (PORT datab (313:313:313) (363:363:363)) + (PORT datac (464:464:464) (536:536:536)) + (PORT datad (572:572:572) (673:673:673)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (917:917:917) (898:898:898)) + (PORT ena (681:681:681) (744:744:744)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (118:118:118) (155:155:155)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mrd) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (917:917:917) (898:898:898)) + (PORT ena (667:667:667) (723:723:723)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (128:128:128) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (917:917:917) (898:898:898)) + (PORT ena (667:667:667) (723:723:723)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (PORT datad (129:129:129) (172:172:172)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (140:140:140)) + (PORT datab (443:443:443) (512:512:512)) + (PORT datac (107:107:107) (131:131:131)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -14688,14 +6077,337 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) + (INSTANCE Equal2\~1) (DELAY (ABSOLUTE - (PORT dataa (362:362:362) (434:434:434)) - (PORT datab (519:519:519) (612:612:612)) - (PORT datac (622:622:622) (717:717:717)) - (PORT datad (972:972:972) (1106:1106:1106)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datab (1080:1080:1080) (1284:1284:1284)) + (PORT datac (1739:1739:1739) (2035:2035:2035)) + (PORT datad (1448:1448:1448) (1664:1664:1664)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_DAT\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (153:153:153) (704:704:704)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (478:478:478) (503:503:503)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) + (DELAY + (ABSOLUTE + (PORT dataa (148:148:148) (204:204:204)) + (PORT datab (158:158:158) (213:213:213)) + (PORT datad (137:137:137) (182:182:182)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_CLK\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (153:153:153) (704:704:704)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1926:1926:1926) (2185:2185:2185)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (893:893:893) (896:896:896)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (124:124:124) (164:164:164)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (893:893:893) (896:896:896)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (122:122:122) (161:161:161)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (893:893:893) (896:896:896)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (123:123:123) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (893:893:893) (896:896:896)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (130:130:130) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (893:893:893) (896:896:896)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (PORT datab (134:134:134) (184:184:184)) + (PORT datac (198:198:198) (247:247:247)) + (PORT datad (124:124:124) (163:163:163)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (122:122:122) (161:161:161)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (893:893:893) (896:896:896)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (124:124:124) (164:164:164)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (893:893:893) (896:896:896)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (190:190:190)) + (PORT datab (104:104:104) (132:132:132)) + (PORT datac (122:122:122) (164:164:164)) + (PORT datad (125:125:125) (165:165:165)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (122:122:122) (164:164:164)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (893:893:893) (896:896:896)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (193:193:193)) + (PORT datad (98:98:98) (118:118:118)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) + (DELAY + (ABSOLUTE + (PORT clk (899:899:899) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (893:893:893) (896:896:896)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) + (DELAY + (ABSOLUTE + (PORT datab (109:109:109) (140:140:140)) + (PORT datac (122:122:122) (166:166:166)) + (PORT datad (118:118:118) (156:156:156)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -14703,16 +6415,417 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge) (DELAY (ABSOLUTE - (PORT dataa (189:189:189) (225:225:225)) - (PORT datab (622:622:622) (722:722:722)) - (PORT datac (564:564:564) (638:638:638)) - (PORT datad (665:665:665) (757:757:757)) + (PORT clk (899:899:899) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (893:893:893) (896:896:896)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (901:901:901)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (890:890:890) (893:893:893)) + (PORT ena (1192:1192:1192) (1344:1344:1344)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) + (DELAY + (ABSOLUTE + (PORT dataa (146:146:146) (203:203:203)) + (PORT datab (148:148:148) (203:203:203)) + (PORT datad (138:138:138) (183:183:183)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (901:901:901)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (890:890:890) (893:893:893)) + (PORT ena (1192:1192:1192) (1344:1344:1344)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) + (DELAY + (ABSOLUTE + (PORT dataa (149:149:149) (207:207:207)) + (PORT datab (160:160:160) (216:216:216)) + (PORT datad (135:135:135) (181:181:181)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (901:901:901)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (890:890:890) (893:893:893)) + (PORT ena (1192:1192:1192) (1344:1344:1344)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) + (DELAY + (ABSOLUTE + (PORT dataa (152:152:152) (211:211:211)) + (PORT datab (156:156:156) (211:211:211)) + (PORT datad (134:134:134) (178:178:178)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (901:901:901)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (890:890:890) (893:893:893)) + (PORT ena (1192:1192:1192) (1344:1344:1344)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (150:150:150) (208:208:208)) + (PORT datab (161:161:161) (217:217:217)) + (PORT datad (137:137:137) (182:182:182)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (150:150:150) (208:208:208)) + (PORT datab (150:150:150) (205:205:205)) + (PORT datac (202:202:202) (249:249:249)) + (PORT datad (1930:1930:1930) (2186:2186:2186)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (149:149:149) (208:208:208)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (858:858:858) (1002:1002:1002)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (894:894:894) (899:899:899)) + (PORT asdata (2099:2099:2099) (2358:2358:2358)) + (PORT clrn (887:887:887) (891:891:891)) + (PORT ena (865:865:865) (948:948:948)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (894:894:894) (899:899:899)) + (PORT asdata (366:366:366) (414:414:414)) + (PORT clrn (887:887:887) (891:891:891)) + (PORT ena (865:865:865) (948:948:948)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (894:894:894) (899:899:899)) + (PORT asdata (331:331:331) (390:390:390)) + (PORT clrn (887:887:887) (891:891:891)) + (PORT ena (865:865:865) (948:948:948)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (902:902:902)) + (PORT asdata (708:708:708) (799:799:799)) + (PORT clrn (883:883:883) (888:888:888)) + (PORT ena (907:907:907) (992:992:992)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (894:894:894) (899:899:899)) + (PORT asdata (673:673:673) (771:771:771)) + (PORT clrn (887:887:887) (891:891:891)) + (PORT ena (865:865:865) (948:948:948)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (901:901:901)) + (PORT asdata (714:714:714) (822:822:822)) + (PORT clrn (883:883:883) (887:887:887)) + (PORT ena (763:763:763) (839:839:839)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (901:901:901)) + (PORT asdata (620:620:620) (688:688:688)) + (PORT clrn (883:883:883) (887:887:887)) + (PORT ena (763:763:763) (839:839:839)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (901:901:901)) + (PORT asdata (324:324:324) (372:372:372)) + (PORT clrn (883:883:883) (887:887:887)) + (PORT ena (763:763:763) (839:839:839)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (894:894:894) (899:899:899)) + (PORT asdata (683:683:683) (774:774:774)) + (PORT clrn (887:887:887) (891:891:891)) + (PORT ena (865:865:865) (948:948:948)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (166:166:166) (231:231:231)) + (PORT datab (511:511:511) (614:614:614)) + (PORT datac (137:137:137) (181:181:181)) + (PORT datad (518:518:518) (618:618:618)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (431:431:431) (534:534:534)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (502:502:502) (594:594:594)) + (PORT datad (145:145:145) (188:188:188)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (173:173:173) (240:240:240)) + (PORT datab (539:539:539) (645:645:645)) + (PORT datad (145:145:145) (189:189:189)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (502:502:502) (598:598:598)) + (PORT datab (521:521:521) (620:620:620)) + (PORT datad (419:419:419) (512:512:512)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) + (DELAY + (ABSOLUTE + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (128:128:128) (170:170:170)) + (PORT datad (160:160:160) (186:186:186)) + (IOPATH datab combout (196:196:196) (205:205:205)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -14720,14 +6833,303 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) (DELAY (ABSOLUTE - (PORT dataa (364:364:364) (433:433:433)) - (PORT datab (484:484:484) (569:569:569)) - (PORT datac (501:501:501) (593:593:593)) - (PORT datad (161:161:161) (189:189:189)) + (PORT dataa (356:356:356) (421:421:421)) + (PORT datab (1945:1945:1945) (2207:2207:2207)) + (PORT datac (858:858:858) (1002:1002:1002)) + (PORT datad (98:98:98) (118:118:118)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (901:901:901)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (890:890:890) (893:893:893)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|released\~0) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (430:430:430)) + (PORT datab (478:478:478) (562:562:562)) + (PORT datad (381:381:381) (454:454:454)) (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|released) + (DELAY + (ABSOLUTE + (PORT clk (893:893:893) (898:898:898)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (885:885:885) (890:890:890)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (460:460:460)) + (PORT datab (440:440:440) (536:536:536)) + (PORT datac (395:395:395) (484:484:484)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (473:473:473)) + (PORT datad (406:406:406) (499:499:499)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|extended\~0) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (432:432:432)) + (PORT datad (373:373:373) (445:445:445)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|extended) + (DELAY + (ABSOLUTE + (PORT clk (893:893:893) (898:898:898)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (885:885:885) (890:890:890)) + (PORT ena (794:794:794) (881:881:881)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (163:163:163) (229:229:229)) + (PORT datab (353:353:353) (426:426:426)) + (PORT datac (485:485:485) (576:576:576)) + (PORT datad (146:146:146) (191:191:191)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (417:417:417)) + (PORT datab (421:421:421) (513:513:513)) + (PORT datac (95:95:95) (119:119:119)) + (PORT datad (618:618:618) (700:700:700)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (243:243:243)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (893:893:893) (898:898:898)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (885:885:885) (890:890:890)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|clrpc_int\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1093:1093:1093) (1296:1296:1296)) + (PORT datab (814:814:814) (961:961:961)) + (PORT datad (635:635:635) (762:762:762)) + (IOPATH dataa combout (181:181:181) (193:193:193)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|clrpc_int) + (DELAY + (ABSOLUTE + (PORT clk (926:926:926) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (1129:1129:1129) (1094:1094:1094)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT datac (516:516:516) (604:604:604)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (902:902:902)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (122:122:122) (162:162:162)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (902:902:902)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (902:902:902)) + (PORT asdata (300:300:300) (341:341:341)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|clrpc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (443:443:443)) + (PORT datab (136:136:136) (186:186:186)) + (PORT datad (124:124:124) (163:163:163)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (846:846:846)) + (PORT datab (535:535:535) (643:643:643)) + (PORT datac (347:347:347) (410:410:410)) + (PORT datad (481:481:481) (557:557:557)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -14736,13 +7138,427 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) + (INSTANCE z80_\|pla_decode_\|Equal21\~1) (DELAY (ABSOLUTE - (PORT dataa (514:514:514) (605:605:605)) - (PORT datab (488:488:488) (571:571:571)) - (PORT datac (760:760:760) (876:876:876)) - (PORT datad (474:474:474) (551:551:551)) + (PORT dataa (1063:1063:1063) (1225:1225:1225)) + (PORT datab (638:638:638) (731:731:731)) + (PORT datac (933:933:933) (1097:1097:1097)) + (PORT datad (467:467:467) (541:541:541)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1063:1063:1063) (1225:1225:1225)) + (PORT datab (486:486:486) (564:564:564)) + (PORT datac (933:933:933) (1097:1097:1097)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1063:1063:1063) (1225:1225:1225)) + (PORT datab (966:966:966) (1102:1102:1102)) + (PORT datac (929:929:929) (1093:1093:1093)) + (PORT datad (468:468:468) (542:542:542)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) + (DELAY + (ABSOLUTE + (PORT datab (136:136:136) (171:171:171)) + (PORT datac (140:140:140) (180:180:180)) + (PORT datad (135:135:135) (166:166:166)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (391:391:391)) + (PORT datac (918:918:918) (1055:1055:1055)) + (PORT datad (627:627:627) (728:728:728)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (418:418:418)) + (PORT datac (332:332:332) (385:385:385)) + (PORT datad (683:683:683) (791:791:791)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (423:423:423)) + (PORT datab (787:787:787) (906:906:906)) + (PORT datac (313:313:313) (355:355:355)) + (PORT datad (626:626:626) (717:717:717)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (413:413:413)) + (PORT datab (508:508:508) (593:593:593)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (484:484:484) (549:549:549)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) + (DELAY + (ABSOLUTE + (PORT datab (849:849:849) (975:975:975)) + (PORT datac (686:686:686) (793:793:793)) + (PORT datad (804:804:804) (917:917:917)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) + (DELAY + (ABSOLUTE + (PORT dataa (754:754:754) (884:884:884)) + (PORT datab (899:899:899) (1072:1072:1072)) + (PORT datac (338:338:338) (399:399:399)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1112:1112:1112) (1326:1326:1326)) + (PORT datab (1482:1482:1482) (1751:1751:1751)) + (PORT datad (961:961:961) (1121:1121:1121)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (815:815:815) (930:930:930)) + (PORT datab (522:522:522) (605:605:605)) + (PORT datac (492:492:492) (559:559:559)) + (PORT datad (511:511:511) (592:592:592)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) + (DELAY + (ABSOLUTE + (PORT dataa (1330:1330:1330) (1548:1548:1548)) + (PORT datac (1025:1025:1025) (1163:1163:1163)) + (PORT datad (988:988:988) (1156:1156:1156)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (526:526:526) (621:621:621)) + (PORT datab (110:110:110) (141:141:141)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (753:753:753)) + (PORT datab (326:326:326) (381:381:381)) + (PORT datac (504:504:504) (578:578:578)) + (PORT datad (466:466:466) (544:544:544)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (492:492:492) (570:570:570)) + (PORT datac (343:343:343) (397:397:397)) + (PORT datad (345:345:345) (391:391:391)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (462:462:462) (541:541:541)) + (PORT datab (877:877:877) (1025:1025:1025)) + (PORT datac (346:346:346) (409:409:409)) + (PORT datad (682:682:682) (790:790:790)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (101:101:101) (130:130:130)) + (PORT datac (97:97:97) (122:122:122)) + (PORT datad (690:690:690) (802:802:802)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~13) + (DELAY + (ABSOLUTE + (PORT datab (1578:1578:1578) (1849:1849:1849)) + (PORT datac (959:959:959) (1116:1116:1116)) + (PORT datad (450:450:450) (517:517:517)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (1051:1051:1051)) + (PORT datab (1134:1134:1134) (1320:1320:1320)) + (PORT datac (1242:1242:1242) (1423:1423:1423)) + (PORT datad (985:985:985) (1151:1151:1151)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (989:989:989) (1152:1152:1152)) + (PORT datab (184:184:184) (226:226:226)) + (PORT datac (1029:1029:1029) (1174:1174:1174)) + (PORT datad (914:914:914) (1087:1087:1087)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1344:1344:1344) (1571:1571:1571)) + (PORT datab (627:627:627) (720:720:720)) + (PORT datac (873:873:873) (1030:1030:1030)) + (PORT datad (1124:1124:1124) (1302:1302:1302)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) + (DELAY + (ABSOLUTE + (PORT dataa (470:470:470) (557:557:557)) + (PORT datab (433:433:433) (504:504:504)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (919:919:919) (1054:1054:1054)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) + (DELAY + (ABSOLUTE + (PORT dataa (125:125:125) (159:159:159)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (367:367:367) (425:425:425)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (754:754:754)) + (PORT datab (461:461:461) (539:539:539)) + (PORT datac (661:661:661) (763:763:763)) + (PORT datad (497:497:497) (576:576:576)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (996:996:996)) + (PORT datab (607:607:607) (697:697:697)) + (PORT datac (966:966:966) (1116:1116:1116)) + (PORT datad (651:651:651) (752:752:752)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (991:991:991)) + (PORT datab (115:115:115) (147:147:147)) + (PORT datac (692:692:692) (818:818:818)) + (PORT datad (656:656:656) (756:756:756)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~2) + (DELAY + (ABSOLUTE + (PORT dataa (154:154:154) (198:198:198)) + (PORT datab (132:132:132) (167:167:167)) + (PORT datac (135:135:135) (174:174:174)) + (PORT datad (788:788:788) (901:901:901)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -14752,12 +7568,1912 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) (DELAY (ABSOLUTE - (PORT dataa (779:779:779) (905:905:905)) - (PORT datab (509:509:509) (608:608:608)) - (PORT datac (166:166:166) (201:201:201)) + (PORT dataa (314:314:314) (369:369:369)) + (PORT datab (436:436:436) (506:506:506)) + (PORT datac (192:192:192) (222:222:222)) + (PORT datad (492:492:492) (576:576:576)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (308:308:308) (360:360:360)) + (PORT datab (119:119:119) (148:148:148)) + (PORT datac (613:613:613) (697:697:697)) + (PORT datad (483:483:483) (564:564:564)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (701:701:701)) + (PORT datab (121:121:121) (151:151:151)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal56\~0) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (738:738:738)) + (PORT datab (1131:1131:1131) (1301:1301:1301)) + (PORT datac (789:789:789) (941:941:941)) + (PORT datad (1048:1048:1048) (1201:1201:1201)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (1100:1100:1100)) + (PORT datab (336:336:336) (393:393:393)) + (PORT datac (990:990:990) (1139:1139:1139)) + (PORT datad (587:587:587) (696:696:696)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (1101:1101:1101)) + (PORT datab (335:335:335) (392:392:392)) + (PORT datac (991:991:991) (1140:1140:1140)) + (PORT datad (585:585:585) (695:695:695)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (769:769:769)) + (PORT datab (478:478:478) (561:561:561)) + (PORT datac (524:524:524) (610:610:610)) + (PORT datad (518:518:518) (607:607:607)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (251:251:251)) + (PORT datab (516:516:516) (600:600:600)) + (PORT datac (326:326:326) (377:377:377)) + (PORT datad (120:120:120) (139:139:139)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (593:593:593)) + (PORT datab (517:517:517) (598:598:598)) + (PORT datac (353:353:353) (410:410:410)) + (PORT datad (663:663:663) (765:765:765)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) + (DELAY + (ABSOLUTE + (PORT dataa (546:546:546) (641:641:641)) + (PORT datab (539:539:539) (633:633:633)) + (PORT datac (659:659:659) (754:754:754)) + (PORT datad (551:551:551) (642:642:642)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (407:407:407)) + (PORT datab (818:818:818) (946:946:946)) + (PORT datac (481:481:481) (582:582:582)) + (PORT datad (1089:1089:1089) (1263:1263:1263)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|nM1_int\~2) + (DELAY + (ABSOLUTE + (PORT datac (745:745:745) (897:897:897)) + (PORT datad (1230:1230:1230) (1468:1468:1468)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (449:449:449) (525:525:525)) + (PORT datab (114:114:114) (149:149:149)) + (PORT datac (635:635:635) (724:724:724)) + (PORT datad (343:343:343) (405:405:405)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~94) + (DELAY + (ABSOLUTE + (PORT dataa (493:493:493) (592:592:592)) + (PORT datab (829:829:829) (949:949:949)) + (PORT datac (798:798:798) (946:946:946)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (385:385:385)) + (PORT datab (120:120:120) (151:151:151)) + (PORT datac (440:440:440) (506:506:506)) + (PORT datad (447:447:447) (536:536:536)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1145:1145:1145) (1332:1332:1332)) + (PORT datab (326:326:326) (381:381:381)) + (PORT datac (462:462:462) (526:526:526)) + (PORT datad (381:381:381) (447:447:447)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (1098:1098:1098)) + (PORT datab (999:999:999) (1154:1154:1154)) + (PORT datac (486:486:486) (567:567:567)) + (PORT datad (380:380:380) (446:446:446)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) + (DELAY + (ABSOLUTE + (PORT dataa (485:485:485) (572:572:572)) + (PORT datab (1141:1141:1141) (1317:1317:1317)) + (PORT datac (993:993:993) (1128:1128:1128)) + (PORT datad (783:783:783) (882:882:882)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (388:388:388)) + (PORT datab (399:399:399) (470:470:470)) + (PORT datac (636:636:636) (740:740:740)) + (PORT datad (432:432:432) (496:496:496)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (397:397:397)) + (PORT datab (400:400:400) (471:471:471)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (329:329:329) (375:375:375)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) + (DELAY + (ABSOLUTE + (PORT dataa (173:173:173) (215:215:215)) + (PORT datab (103:103:103) (133:133:133)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) + (DELAY + (ABSOLUTE + (PORT dataa (916:916:916) (1046:1046:1046)) + (PORT datab (446:446:446) (520:520:520)) + (PORT datac (471:471:471) (549:549:549)) + (PORT datad (317:317:317) (359:359:359)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (1093:1093:1093)) + (PORT datab (325:325:325) (379:379:379)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (1122:1122:1122) (1303:1303:1303)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) + (DELAY + (ABSOLUTE + (PORT dataa (461:461:461) (555:555:555)) + (PORT datab (611:611:611) (725:725:725)) + (PORT datac (448:448:448) (519:519:519)) + (PORT datad (346:346:346) (405:405:405)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~99) + (DELAY + (ABSOLUTE + (PORT dataa (396:396:396) (482:482:482)) + (PORT datab (1347:1347:1347) (1571:1571:1571)) + (PORT datac (421:421:421) (511:511:511)) + (PORT datad (1038:1038:1038) (1202:1202:1202)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (152:152:152)) + (PORT datab (338:338:338) (401:401:401)) + (PORT datac (188:188:188) (222:222:222)) + (PORT datad (449:449:449) (516:516:516)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) + (DELAY + (ABSOLUTE + (PORT datac (1186:1186:1186) (1389:1389:1389)) + (PORT datad (952:952:952) (1132:1132:1132)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (147:147:147)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (487:487:487) (554:554:554)) + (PORT datad (188:188:188) (219:219:219)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (179:179:179) (223:223:223)) + (PORT datab (315:315:315) (367:367:367)) + (PORT datac (314:314:314) (357:357:357)) + (PORT datad (428:428:428) (489:489:489)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (151:151:151) (195:195:195)) + (PORT datab (990:990:990) (1129:1129:1129)) + (PORT datac (137:137:137) (174:174:174)) + (PORT datad (121:121:121) (146:146:146)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (526:526:526) (618:618:618)) + (PORT datab (535:535:535) (622:622:622)) + (PORT datac (1052:1052:1052) (1208:1208:1208)) + (PORT datad (342:342:342) (395:395:395)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (526:526:526) (635:635:635)) + (PORT datab (799:799:799) (966:966:966)) + (PORT datac (518:518:518) (621:621:621)) + (PORT datad (420:420:420) (484:484:484)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (426:426:426)) + (PORT datab (891:891:891) (1037:1037:1037)) + (PORT datac (725:725:725) (841:841:841)) + (PORT datad (629:629:629) (720:720:720)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~5) + (DELAY + (ABSOLUTE + (PORT datac (1065:1065:1065) (1230:1230:1230)) + (PORT datad (1150:1150:1150) (1352:1352:1352)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (153:153:153)) + (PORT datab (851:851:851) (1010:1010:1010)) + (PORT datac (1107:1107:1107) (1253:1253:1253)) + (PORT datad (109:109:109) (133:133:133)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal48\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1089:1089:1089) (1254:1254:1254)) + (PORT datab (1170:1170:1170) (1377:1377:1377)) + (PORT datac (839:839:839) (994:994:994)) + (PORT datad (114:114:114) (138:138:138)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1101:1101:1101) (1285:1285:1285)) + (PORT datab (659:659:659) (763:763:763)) + (PORT datac (962:962:962) (1102:1102:1102)) + (PORT datad (522:522:522) (611:611:611)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (819:819:819) (939:939:939)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (750:750:750) (869:869:869)) + (PORT datad (334:334:334) (391:391:391)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (728:728:728)) + (PORT datab (892:892:892) (1038:1038:1038)) + (PORT datac (489:489:489) (571:571:571)) + (PORT datad (498:498:498) (569:569:569)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (142:142:142)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (112:112:112) (134:134:134)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) + (DELAY + (ABSOLUTE + (PORT datab (1173:1173:1173) (1380:1380:1380)) + (PORT datac (835:835:835) (989:989:989)) + (PORT datad (109:109:109) (134:134:134)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) + (DELAY + (ABSOLUTE + (PORT datab (811:811:811) (956:956:956)) + (PORT datac (1189:1189:1189) (1392:1392:1392)) + (PORT datad (954:954:954) (1134:1134:1134)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) + (DELAY + (ABSOLUTE + (PORT dataa (516:516:516) (611:611:611)) + (PORT datab (599:599:599) (689:689:689)) + (PORT datac (348:348:348) (410:410:410)) + (PORT datad (330:330:330) (388:388:388)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~7) + (DELAY + (ABSOLUTE + (PORT dataa (311:311:311) (365:365:365)) + (PORT datab (489:489:489) (566:566:566)) + (PORT datac (306:306:306) (350:350:350)) + (PORT datad (901:901:901) (1007:1007:1007)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1259:1259:1259) (1446:1446:1446)) + (PORT datab (908:908:908) (1082:1082:1082)) + (PORT datac (467:467:467) (543:543:543)) + (PORT datad (481:481:481) (546:546:546)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (419:419:419)) + (PORT datab (475:475:475) (557:557:557)) + (PORT datac (952:952:952) (1085:1085:1085)) + (PORT datad (836:836:836) (967:967:967)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (755:755:755)) + (PORT datab (336:336:336) (391:391:391)) + (PORT datac (355:355:355) (421:421:421)) + (PORT datad (650:650:650) (741:741:741)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (808:808:808)) + (PORT datab (538:538:538) (632:632:632)) + (PORT datac (934:934:934) (1079:1079:1079)) + (PORT datad (777:777:777) (885:885:885)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (143:143:143)) + (PORT datab (563:563:563) (663:663:663)) + (PORT datac (993:993:993) (1149:1149:1149)) + (PORT datad (776:776:776) (884:884:884)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (585:585:585)) + (PORT datab (522:522:522) (612:612:612)) + (PORT datad (483:483:483) (569:569:569)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (153:153:153)) + (PORT datab (543:543:543) (638:638:638)) + (PORT datac (435:435:435) (498:498:498)) + (PORT datad (763:763:763) (865:865:865)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (989:989:989) (1152:1152:1152)) + (PORT datab (935:935:935) (1116:1116:1116)) + (PORT datad (1050:1050:1050) (1202:1202:1202)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~0) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (725:725:725)) + (PORT datac (974:974:974) (1145:1145:1145)) + (PORT datad (352:352:352) (415:415:415)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~1) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (735:735:735)) + (PORT datab (513:513:513) (603:603:603)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (301:301:301) (348:348:348)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1064:1064:1064) (1227:1227:1227)) + (PORT datab (854:854:854) (980:980:980)) + (PORT datac (931:931:931) (1095:1095:1095)) + (PORT datad (469:469:469) (543:543:543)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~7) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (911:911:911)) + (PORT datab (683:683:683) (792:792:792)) + (PORT datac (529:529:529) (624:624:624)) + (PORT datad (453:453:453) (513:513:513)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (129:129:129) (165:165:165)) + (PORT datab (1089:1089:1089) (1273:1273:1273)) + (PORT datac (760:760:760) (887:887:887)) + (PORT datad (850:850:850) (1006:1006:1006)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~9) + (DELAY + (ABSOLUTE + (PORT dataa (767:767:767) (917:917:917)) + (PORT datab (865:865:865) (1013:1013:1013)) + (PORT datac (1380:1380:1380) (1618:1618:1618)) + (PORT datad (697:697:697) (833:833:833)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~5) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (1074:1074:1074)) + (PORT datab (512:512:512) (591:591:591)) + (PORT datac (1420:1420:1420) (1615:1615:1615)) + (PORT datad (436:436:436) (520:520:520)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (790:790:790) (920:920:920)) + (PORT datab (310:310:310) (359:359:359)) + (PORT datac (614:614:614) (711:711:711)) + (PORT datad (309:309:309) (354:354:354)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~8) + (DELAY + (ABSOLUTE + (PORT dataa (785:785:785) (914:914:914)) + (PORT datab (798:798:798) (902:902:902)) + (PORT datac (528:528:528) (622:622:622)) + (PORT datad (777:777:777) (891:891:891)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~2) + (DELAY + (ABSOLUTE + (PORT dataa (984:984:984) (1167:1167:1167)) + (PORT datab (113:113:113) (141:141:141)) + (PORT datac (96:96:96) (121:121:121)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (490:490:490)) + (PORT datab (662:662:662) (757:757:757)) + (PORT datac (669:669:669) (769:769:769)) + (PORT datad (479:479:479) (562:562:562)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (464:464:464) (563:563:563)) + (PORT datab (1082:1082:1082) (1267:1267:1267)) + (PORT datac (169:169:169) (200:200:200)) + (PORT datad (943:943:943) (1089:1089:1089)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1255:1255:1255) (1479:1479:1479)) + (PORT datab (780:780:780) (895:895:895)) + (PORT datac (779:779:779) (897:897:897)) + (PORT datad (1272:1272:1272) (1474:1474:1474)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (713:713:713) (840:840:840)) + (PORT datab (665:665:665) (772:772:772)) + (PORT datac (367:367:367) (433:433:433)) + (PORT datad (644:644:644) (737:737:737)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (798:798:798) (928:928:928)) + (PORT datab (667:667:667) (774:774:774)) + (PORT datac (369:369:369) (436:436:436)) + (PORT datad (100:100:100) (122:122:122)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1204:1204:1204) (1413:1413:1413)) + (PORT datab (972:972:972) (1159:1159:1159)) + (PORT datac (655:655:655) (755:755:755)) + (PORT datad (1072:1072:1072) (1229:1229:1229)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (473:473:473) (562:562:562)) + (PORT datab (511:511:511) (590:590:590)) + (PORT datac (296:296:296) (339:339:339)) + (PORT datad (598:598:598) (681:681:681)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (552:552:552)) + (PORT datab (581:581:581) (682:682:682)) + (PORT datac (640:640:640) (727:727:727)) + (PORT datad (347:347:347) (394:394:394)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (414:414:414)) + (PORT datab (363:363:363) (428:428:428)) + (PORT datac (347:347:347) (412:412:412)) + (PORT datad (635:635:635) (715:715:715)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (408:408:408)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (639:639:639) (726:726:726)) + (PORT datad (296:296:296) (342:342:342)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) + (DELAY + (ABSOLUTE + (PORT dataa (744:744:744) (868:868:868)) + (PORT datab (847:847:847) (970:970:970)) + (PORT datac (829:829:829) (981:981:981)) + (PORT datad (1417:1417:1417) (1647:1647:1647)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (811:811:811) (952:952:952)) + (PORT datab (840:840:840) (984:984:984)) + (PORT datac (901:901:901) (1032:1032:1032)) + (PORT datad (833:833:833) (985:985:985)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (796:796:796)) + (PORT datab (359:359:359) (427:427:427)) + (PORT datac (90:90:90) (113:113:113)) + (PORT datad (366:366:366) (428:428:428)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1306:1306:1306) (1526:1526:1526)) + (PORT datab (1252:1252:1252) (1442:1442:1442)) + (PORT datac (828:828:828) (979:979:979)) + (PORT datad (651:651:651) (751:751:751)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal68\~2) + (DELAY + (ABSOLUTE + (PORT dataa (986:986:986) (1148:1148:1148)) + (PORT datab (957:957:957) (1143:1143:1143)) + (PORT datac (586:586:586) (693:693:693)) + (PORT datad (1016:1016:1016) (1186:1186:1186)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (793:793:793) (931:931:931)) + (PORT datab (628:628:628) (733:733:733)) + (PORT datac (438:438:438) (502:502:502)) + (PORT datad (839:839:839) (991:991:991)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal63\~0) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (712:712:712)) + (PORT datab (117:117:117) (146:146:146)) + (PORT datac (962:962:962) (1113:1113:1113)) + (PORT datad (842:842:842) (997:997:997)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal76\~2) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (423:423:423)) + (PORT datac (1249:1249:1249) (1427:1427:1427)) + (PORT datad (947:947:947) (1081:1081:1081)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (405:405:405)) + (PORT datab (832:832:832) (956:956:956)) + (PORT datac (669:669:669) (773:773:773)) + (PORT datad (296:296:296) (340:340:340)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1039:1039:1039) (1218:1218:1218)) + (PORT datab (486:486:486) (551:551:551)) + (PORT datac (470:470:470) (547:547:547)) + (PORT datad (848:848:848) (957:957:957)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (702:702:702)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (670:670:670) (774:774:774)) + (PORT datad (508:508:508) (586:586:586)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (421:421:421)) + (PORT datab (196:196:196) (236:236:236)) + (PORT datac (627:627:627) (724:724:724)) + (PORT datad (517:517:517) (603:603:603)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) + (DELAY + (ABSOLUTE + (PORT dataa (690:690:690) (805:805:805)) + (PORT datab (531:531:531) (633:633:633)) + (PORT datac (450:450:450) (523:523:523)) + (PORT datad (765:765:765) (915:915:915)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) + (DELAY + (ABSOLUTE + (PORT dataa (488:488:488) (562:562:562)) + (PORT datab (670:670:670) (781:781:781)) + (PORT datac (668:668:668) (780:780:780)) + (PORT datad (380:380:380) (446:446:446)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1382:1382:1382)) + (PORT datab (858:858:858) (995:995:995)) + (PORT datac (324:324:324) (381:381:381)) + (PORT datad (1179:1179:1179) (1377:1377:1377)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~7) + (DELAY + (ABSOLUTE + (PORT dataa (524:524:524) (611:611:611)) + (PORT datab (134:134:134) (169:169:169)) + (PORT datac (659:659:659) (763:763:763)) + (PORT datad (983:983:983) (1125:1125:1125)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (166:166:166)) + (PORT datab (342:342:342) (401:401:401)) + (PORT datac (95:95:95) (120:120:120)) + (PORT datad (94:94:94) (112:112:112)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~3) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (650:650:650)) + (PORT datab (478:478:478) (553:553:553)) + (PORT datac (589:589:589) (702:702:702)) + (PORT datad (694:694:694) (826:826:826)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (464:464:464) (555:555:555)) + (PORT datab (345:345:345) (406:406:406)) + (PORT datac (949:949:949) (1115:1115:1115)) + (PORT datad (628:628:628) (717:717:717)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (404:404:404) (489:489:489)) + (PORT datab (682:682:682) (788:788:788)) + (PORT datac (738:738:738) (877:877:877)) + (PORT datad (481:481:481) (564:564:564)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (243:243:243)) + (PORT datab (677:677:677) (782:782:782)) + (PORT datac (519:519:519) (630:630:630)) + (PORT datad (1108:1108:1108) (1303:1303:1303)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) + (DELAY + (ABSOLUTE + (PORT dataa (736:736:736) (860:860:860)) + (PORT datab (912:912:912) (1075:1075:1075)) + (PORT datac (1238:1238:1238) (1424:1424:1424)) + (PORT datad (514:514:514) (595:595:595)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1471:1471:1471) (1746:1746:1746)) + (PORT datab (686:686:686) (803:803:803)) + (PORT datac (480:480:480) (561:561:561)) + (PORT datad (1222:1222:1222) (1442:1442:1442)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (818:818:818)) + (PORT datac (776:776:776) (885:885:885)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (404:404:404)) + (PORT datab (694:694:694) (803:803:803)) + (PORT datac (1062:1062:1062) (1260:1260:1260)) + (PORT datad (954:954:954) (1134:1134:1134)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (775:775:775)) + (PORT datab (292:292:292) (340:340:340)) + (PORT datac (1165:1165:1165) (1358:1358:1358)) + (PORT datad (729:729:729) (880:880:880)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (122:122:122) (156:156:156)) + (PORT datab (363:363:363) (422:422:422)) + (PORT datac (494:494:494) (570:570:570)) + (PORT datad (159:159:159) (186:186:186)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (1031:1031:1031)) + (PORT datab (858:858:858) (996:996:996)) + (PORT datac (94:94:94) (117:117:117)) + (PORT datad (390:390:390) (463:463:463)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal10\~1) + (DELAY + (ABSOLUTE + (PORT datac (1191:1191:1191) (1360:1360:1360)) + (PORT datad (784:784:784) (907:907:907)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (773:773:773)) + (PORT datab (781:781:781) (901:901:901)) + (PORT datac (93:93:93) (117:117:117)) + (PORT datad (799:799:799) (923:923:923)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal69\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1090:1090:1090) (1255:1255:1255)) + (PORT datab (1170:1170:1170) (1378:1378:1378)) + (PORT datac (839:839:839) (993:993:993)) + (PORT datad (113:113:113) (138:138:138)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1020:1020:1020) (1170:1170:1170)) + (PORT datab (747:747:747) (904:904:904)) + (PORT datac (1165:1165:1165) (1358:1358:1358)) + (PORT datad (1180:1180:1180) (1379:1379:1379)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (971:971:971) (1130:1130:1130)) + (PORT datab (508:508:508) (586:586:586)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (337:337:337) (397:397:397)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (142:142:142)) + (PORT datab (349:349:349) (408:408:408)) + (PORT datac (319:319:319) (376:376:376)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (648:648:648)) + (PORT datab (477:477:477) (552:552:552)) + (PORT datac (935:935:935) (1125:1125:1125)) + (PORT datad (1197:1197:1197) (1425:1425:1425)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (704:704:704)) + (PORT datab (113:113:113) (146:146:146)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (473:473:473) (546:546:546)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (154:154:154) (198:198:198)) + (PORT datab (134:134:134) (168:168:168)) + (PORT datac (648:648:648) (745:745:745)) + (PORT datad (137:137:137) (171:171:171)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (1038:1038:1038)) + (PORT datab (1113:1113:1113) (1275:1275:1275)) + (PORT datac (474:474:474) (557:557:557)) + (PORT datad (961:961:961) (1121:1121:1121)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (809:809:809)) + (PORT datab (336:336:336) (392:392:392)) + (PORT datac (340:340:340) (402:402:402)) + (PORT datad (479:479:479) (552:552:552)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1030:1030:1030) (1212:1212:1212)) + (PORT datab (500:500:500) (593:593:593)) + (PORT datad (348:348:348) (394:394:394)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (144:144:144)) + (PORT datab (610:610:610) (705:705:705)) + (PORT datac (164:164:164) (194:194:194)) + (PORT datad (369:369:369) (440:440:440)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (119:119:119) (149:149:149)) + (PORT datac (333:333:333) (391:391:391)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1030:1030:1030) (1211:1211:1211)) + (PORT datab (366:366:366) (418:418:418)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (488:488:488) (571:571:571)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~20) + (DELAY + (ABSOLUTE + (PORT dataa (533:533:533) (650:650:650)) + (PORT datab (1030:1030:1030) (1209:1209:1209)) + (PORT datac (541:541:541) (643:643:643)) + (PORT datad (694:694:694) (800:800:800)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1297:1297:1297) (1548:1548:1548)) + (PORT datab (1031:1031:1031) (1210:1210:1210)) + (PORT datac (476:476:476) (555:555:555)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (468:468:468) (537:537:537)) + (PORT datab (798:798:798) (954:954:954)) + (PORT datac (364:364:364) (427:427:427)) + (PORT datad (368:368:368) (443:443:443)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (154:154:154) (198:198:198)) + (PORT datab (133:133:133) (167:167:167)) + (PORT datac (136:136:136) (174:174:174)) + (PORT datad (667:667:667) (766:766:766)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (453:453:453) (544:544:544)) + (PORT datab (338:338:338) (410:410:410)) + (PORT datac (474:474:474) (561:561:561)) + (PORT datad (356:356:356) (427:427:427)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (140:140:140)) + (PORT datab (870:870:870) (1013:1013:1013)) + (PORT datac (1557:1557:1557) (1772:1772:1772)) (PORT datad (91:91:91) (109:109:109)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) @@ -14768,29 +9484,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~29) (DELAY (ABSOLUTE - (PORT dataa (122:122:122) (159:159:159)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (315:315:315) (360:360:360)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (777:777:777)) - (PORT datab (652:652:652) (755:755:755)) - (PORT datac (192:192:192) (227:227:227)) - (PORT datad (645:645:645) (746:746:746)) + (PORT dataa (360:360:360) (429:429:429)) + (PORT datab (190:190:190) (229:229:229)) + (PORT datac (94:94:94) (119:119:119)) + (PORT datad (489:489:489) (566:566:566)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -14800,28 +9500,74 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) (DELAY (ABSOLUTE - (PORT dataa (605:605:605) (700:700:700)) - (PORT datab (652:652:652) (754:754:754)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (158:158:158)) + (PORT dataa (721:721:721) (853:853:853)) + (PORT datab (555:555:555) (654:654:654)) + (PORT datac (531:531:531) (631:631:631)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (640:640:640) (702:702:702)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) + (DELAY + (ABSOLUTE + (PORT dataa (721:721:721) (852:852:852)) + (PORT datab (556:556:556) (655:655:655)) + (PORT datac (531:531:531) (630:630:630)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (813:813:813) (948:948:948)) + (PORT datab (607:607:607) (718:718:718)) + (PORT datac (653:653:653) (752:752:752)) + (PORT datad (786:786:786) (910:910:910)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) + (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) (DELAY (ABSOLUTE - (PORT dataa (513:513:513) (609:609:609)) - (PORT datab (483:483:483) (568:568:568)) - (PORT datac (347:347:347) (408:408:408)) - (PORT datad (864:864:864) (1021:1021:1021)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (338:338:338) (400:400:400)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datac (755:755:755) (854:854:854)) + (PORT datad (695:695:695) (808:808:808)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -14830,13 +9576,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) (DELAY (ABSOLUTE - (PORT dataa (241:241:241) (288:288:288)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datac (430:430:430) (494:494:494)) - (PORT datad (102:102:102) (119:119:119)) + (PORT dataa (844:844:844) (978:978:978)) + (PORT datab (987:987:987) (1134:1134:1134)) + (PORT datac (316:316:316) (360:360:360)) + (PORT datad (326:326:326) (381:381:381)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~47) + (DELAY + (ABSOLUTE + (PORT datab (375:375:375) (440:440:440)) + (PORT datac (196:196:196) (235:235:235)) + (PORT datad (468:468:468) (542:542:542)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) + (DELAY + (ABSOLUTE + (PORT dataa (498:498:498) (581:581:581)) + (PORT datab (667:667:667) (769:769:769)) + (PORT datac (97:97:97) (123:123:123)) + (PORT datad (788:788:788) (915:915:915)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -14846,47 +9622,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~89) + (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) (DELAY (ABSOLUTE - (PORT dataa (749:749:749) (876:876:876)) - (PORT datab (624:624:624) (715:715:715)) - (PORT datac (785:785:785) (899:899:899)) - (PORT datad (466:466:466) (543:543:543)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (480:480:480) (550:550:550)) + (PORT datab (366:366:366) (449:449:449)) + (PORT datac (475:475:475) (557:557:557)) + (PORT datad (815:815:815) (934:934:934)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) + (INSTANCE z80_\|execute_\|fMRead\~8) (DELAY (ABSOLUTE - (PORT dataa (109:109:109) (142:142:142)) - (PORT datab (456:456:456) (518:518:518)) - (PORT datac (160:160:160) (188:188:188)) - (PORT datad (89:89:89) (106:106:106)) + (PORT dataa (327:327:327) (392:392:392)) + (PORT datab (366:366:366) (450:450:450)) + (PORT datac (919:919:919) (1060:1060:1060)) + (PORT datad (192:192:192) (219:219:219)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) + (INSTANCE z80_\|execute_\|fMRead\~9) (DELAY (ABSOLUTE - (PORT dataa (485:485:485) (560:560:560)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (317:317:317) (362:362:362)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (328:328:328) (393:393:393)) + (PORT datab (935:935:935) (1083:1083:1083)) + (PORT datac (445:445:445) (510:510:510)) + (PORT datad (460:460:460) (522:522:522)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -14894,13 +9670,165 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) + (INSTANCE z80_\|execute_\|fMRead\~10) (DELAY (ABSOLUTE - (PORT dataa (642:642:642) (741:741:741)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (291:291:291) (331:331:331)) - (PORT datad (295:295:295) (341:341:341)) + (PORT dataa (325:325:325) (391:391:391)) + (PORT datab (493:493:493) (578:578:578)) + (PORT datac (918:918:918) (1059:1059:1059)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) + (DELAY + (ABSOLUTE + (PORT datab (336:336:336) (396:396:396)) + (PORT datac (93:93:93) (115:115:115)) + (PORT datad (94:94:94) (114:114:114)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (751:751:751) (905:905:905)) + (PORT datac (1123:1123:1123) (1343:1343:1343)) + (PORT datad (643:643:643) (740:740:740)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1009:1009:1009) (1164:1164:1164)) + (PORT datab (133:133:133) (167:167:167)) + (PORT datac (489:489:489) (565:565:565)) + (PORT datad (96:96:96) (115:115:115)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~41) + (DELAY + (ABSOLUTE + (PORT datab (516:516:516) (605:605:605)) + (PORT datac (602:602:602) (704:704:704)) + (PORT datad (333:333:333) (383:383:383)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (1100:1100:1100)) + (PORT datab (991:991:991) (1168:1168:1168)) + (PORT datac (730:730:730) (835:835:835)) + (PORT datad (354:354:354) (415:415:415)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (489:489:489) (586:586:586)) + (PORT datab (572:572:572) (667:667:667)) + (PORT datac (847:847:847) (975:975:975)) + (PORT datad (674:674:674) (780:780:780)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (863:863:863) (992:992:992)) + (PORT datac (595:595:595) (683:683:683)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (501:501:501) (582:582:582)) + (PORT datab (928:928:928) (1051:1051:1051)) + (PORT datac (722:722:722) (837:837:837)) + (PORT datad (877:877:877) (991:991:991)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (395:395:395)) + (PORT datac (676:676:676) (779:779:779)) + (PORT datad (490:490:490) (569:569:569)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) + (DELAY + (ABSOLUTE + (PORT dataa (804:804:804) (924:924:924)) + (PORT datab (346:346:346) (405:405:405)) + (PORT datac (91:91:91) (115:115:115)) + (PORT datad (512:512:512) (595:595:595)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -14910,13 +9838,87 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) (DELAY (ABSOLUTE - (PORT dataa (593:593:593) (693:693:693)) - (PORT datab (110:110:110) (142:142:142)) - (PORT datac (579:579:579) (653:653:653)) - (PORT datad (100:100:100) (122:122:122)) + (PORT datac (315:315:315) (359:359:359)) + (PORT datad (473:473:473) (540:540:540)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (115:115:115) (143:143:143)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (444:444:444) (505:505:505)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) + (DELAY + (ABSOLUTE + (PORT datab (184:184:184) (220:220:220)) + (PORT datac (314:314:314) (367:367:367)) + (PORT datad (333:333:333) (387:387:387)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~4) + (DELAY + (ABSOLUTE + (PORT dataa (741:741:741) (865:865:865)) + (PORT datab (885:885:885) (1031:1031:1031)) + (PORT datac (533:533:533) (631:631:631)) + (PORT datad (1192:1192:1192) (1344:1344:1344)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) + (DELAY + (ABSOLUTE + (PORT dataa (454:454:454) (541:541:541)) + (PORT datab (115:115:115) (143:143:143)) + (PORT datac (530:530:530) (625:625:625)) + (PORT datad (625:625:625) (715:715:715)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (728:728:728)) + (PORT datab (482:482:482) (561:561:561)) + (PORT datac (526:526:526) (619:619:619)) + (PORT datad (103:103:103) (127:127:127)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -14926,45 +9928,416 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) (DELAY (ABSOLUTE - (PORT dataa (920:920:920) (1089:1089:1089)) - (PORT datab (473:473:473) (548:548:548)) - (PORT datac (1407:1407:1407) (1624:1624:1624)) - (PORT datad (834:834:834) (989:989:989)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (702:702:702) (846:846:846)) + (PORT datab (329:329:329) (380:380:380)) + (PORT datac (99:99:99) (125:125:125)) + (PORT datad (519:519:519) (624:624:624)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) (DELAY (ABSOLUTE - (PORT dataa (304:304:304) (356:356:356)) - (PORT datab (298:298:298) (346:346:346)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (631:631:631) (718:718:718)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~40) - (DELAY - (ABSOLUTE - (PORT datab (342:342:342) (404:404:404)) - (PORT datac (175:175:175) (210:210:210)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datab (671:671:671) (781:781:781)) + (PORT datac (520:520:520) (594:594:594)) + (PORT datad (513:513:513) (592:592:592)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (754:754:754)) + (PORT datab (486:486:486) (563:563:563)) + (PORT datac (619:619:619) (708:708:708)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) + (DELAY + (ABSOLUTE + (PORT datab (733:733:733) (832:832:832)) + (PORT datad (629:629:629) (721:721:721)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (410:410:410)) + (PORT datab (102:102:102) (129:129:129)) + (PORT datac (441:441:441) (498:498:498)) + (PORT datad (453:453:453) (521:521:521)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (408:408:408)) + (PORT datab (540:540:540) (652:652:652)) + (PORT datac (584:584:584) (660:660:660)) + (PORT datad (1008:1008:1008) (1185:1185:1185)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (404:404:404)) + (PORT datab (515:515:515) (599:599:599)) + (PORT datac (192:192:192) (232:232:232)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (133:133:133)) + (PORT datab (320:320:320) (373:373:373)) + (PORT datac (482:482:482) (545:545:545)) + (PORT datad (298:298:298) (343:343:343)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) + (DELAY + (ABSOLUTE + (PORT dataa (723:723:723) (854:854:854)) + (PORT datab (538:538:538) (627:627:627)) + (PORT datac (534:534:534) (632:632:632)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (842:842:842)) + (PORT datab (535:535:535) (624:624:624)) + (PORT datac (541:541:541) (639:639:639)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (278:278:278) (297:297:297)) + (PORT ena (650:650:650) (698:698:698)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (515:515:515) (618:618:618)) + (PORT datab (1462:1462:1462) (1681:1681:1681)) + (PORT datac (102:102:102) (130:130:130)) + (PORT datad (769:769:769) (880:880:880)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_exx\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1096:1096:1096) (1299:1299:1299)) + (PORT datab (816:816:816) (963:963:963)) + (PORT datad (633:633:633) (732:732:732)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_exx) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (1129:1129:1129) (1094:1094:1094)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (1027:1027:1027)) + (PORT datab (956:956:956) (1091:1091:1091)) + (PORT datac (660:660:660) (762:762:762)) + (PORT datad (684:684:684) (790:790:790)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (768:768:768)) + (PORT datab (680:680:680) (785:785:785)) + (PORT datac (924:924:924) (1056:1056:1056)) + (PORT datad (309:309:309) (353:353:353)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (947:947:947)) + (PORT datab (538:538:538) (628:628:628)) + (PORT datac (656:656:656) (749:749:749)) + (PORT datad (664:664:664) (769:769:769)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (394:394:394)) + (PORT datab (1052:1052:1052) (1211:1211:1211)) + (PORT datac (583:583:583) (687:687:687)) + (PORT datad (1479:1479:1479) (1682:1682:1682)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~56) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (786:786:786)) + (PORT datab (702:702:702) (815:815:815)) + (PORT datac (464:464:464) (552:552:552)) + (PORT datad (469:469:469) (559:559:559)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) + (DELAY + (ABSOLUTE + (PORT datab (500:500:500) (575:575:575)) + (PORT datac (338:338:338) (400:400:400)) + (PORT datad (103:103:103) (121:121:121)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (121:121:121) (156:156:156)) + (PORT datac (1563:1563:1563) (1836:1836:1836)) + (PORT datad (115:115:115) (138:138:138)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (1002:1002:1002)) + (PORT datab (833:833:833) (963:963:963)) + (PORT datac (832:832:832) (947:947:947)) + (PORT datad (612:612:612) (699:699:699)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (690:690:690) (804:804:804)) + (PORT datab (530:530:530) (632:632:632)) + (PORT datac (1107:1107:1107) (1253:1253:1253)) + (PORT datad (767:767:767) (917:917:917)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (788:788:788) (917:917:917)) + (PORT datab (730:730:730) (864:864:864)) + (PORT datac (526:526:526) (621:621:621)) + (PORT datad (847:847:847) (1002:1002:1002)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (521:521:521) (617:617:617)) + (PORT datab (114:114:114) (146:146:146)) + (PORT datac (326:326:326) (383:383:383)) + (PORT datad (686:686:686) (801:801:801)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (852:852:852) (991:991:991)) + (PORT datab (478:478:478) (551:551:551)) + (PORT datac (792:792:792) (917:917:917)) + (PORT datad (378:378:378) (444:444:444)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (524:524:524) (608:608:608)) + (PORT datac (334:334:334) (390:390:390)) + (PORT datad (315:315:315) (356:356:356)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -14973,370 +10346,13 @@ (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) (DELAY (ABSOLUTE - (PORT dataa (121:121:121) (154:154:154)) - (PORT datab (112:112:112) (145:145:145)) - (PORT datac (579:579:579) (652:652:652)) - (PORT datad (628:628:628) (724:724:724)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (744:744:744)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (285:285:285) (332:332:332)) - (PORT datad (212:212:212) (249:249:249)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (710:710:710)) - (PORT datab (608:608:608) (701:701:701)) - (PORT datac (590:590:590) (677:677:677)) - (PORT datad (648:648:648) (752:752:752)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) - (DELAY - (ABSOLUTE - (PORT datac (386:386:386) (469:469:469)) - (PORT datad (189:189:189) (220:220:220)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (527:527:527) (619:619:619)) - (PORT datac (375:375:375) (447:447:447)) - (PORT datad (174:174:174) (206:206:206)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[0\]) - (DELAY - (ABSOLUTE - (PORT datac (541:541:541) (617:617:617)) - (PORT datad (498:498:498) (573:573:573)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (93:93:93) (113:113:113)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (904:904:904)) - (PORT ena (1125:1125:1125) (1271:1271:1271)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (725:725:725)) - (PORT datab (549:549:549) (642:642:642)) - (PORT datac (382:382:382) (465:465:465)) - (PORT datad (107:107:107) (126:126:126)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (746:746:746)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (535:535:535) (593:593:593)) - (PORT ena (636:636:636) (682:682:682)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (228:228:228)) - (PORT datab (381:381:381) (451:451:451)) - (PORT datad (655:655:655) (764:764:764)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (405:405:405) (481:481:481)) - (PORT datac (119:119:119) (160:160:160)) - (PORT datad (339:339:339) (396:396:396)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (441:441:441) (521:521:521)) - (PORT datab (207:207:207) (245:245:245)) - (PORT datac (103:103:103) (125:125:125)) - (IOPATH dataa combout (195:195:195) (203:203:203)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (527:527:527) (618:618:618)) - (PORT datac (376:376:376) (448:448:448)) - (PORT datad (174:174:174) (205:205:205)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[1\]) - (DELAY - (ABSOLUTE - (PORT datab (204:204:204) (241:241:241)) - (PORT datad (176:176:176) (210:210:210)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (928:928:928)) - (PORT asdata (279:279:279) (298:298:298)) - (PORT clrn (927:927:927) (909:909:909)) - (PORT ena (1168:1168:1168) (1321:1321:1321)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~4) - (DELAY - (ABSOLUTE - (PORT dataa (570:570:570) (664:664:664)) - (PORT datab (635:635:635) (731:731:731)) - (PORT datac (426:426:426) (498:498:498)) - (PORT datad (187:187:187) (218:218:218)) - (IOPATH dataa combout (181:181:181) (193:193:193)) - (IOPATH datab combout (182:182:182) (193:193:193)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (211:211:211) (253:253:253)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (128:128:128) (169:169:169)) - (PORT datad (167:167:167) (198:198:198)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (469:469:469)) - (PORT datab (528:528:528) (619:619:619)) - (PORT datac (344:344:344) (405:405:405)) - (PORT datad (277:277:277) (315:315:315)) + (PORT dataa (367:367:367) (439:439:439)) + (PORT datab (597:597:597) (690:690:690)) + (PORT datac (1111:1111:1111) (1284:1284:1284)) + (PORT datad (452:452:452) (516:516:516)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (288:288:288) (342:342:342)) - (PORT datad (114:114:114) (137:137:137)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (102:102:102) (119:119:119)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (928:928:928)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (928:928:928) (909:909:909)) - (PORT ena (1169:1169:1169) (1320:1320:1320)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (635:635:635) (730:730:730)) - (PORT datac (548:548:548) (641:641:641)) - (PORT datad (207:207:207) (252:252:252)) - (IOPATH dataa combout (181:181:181) (180:180:180)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -15346,10 +10362,520 @@ (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) (DELAY (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (94:94:94) (113:113:113)) + (PORT dataa (501:501:501) (600:600:600)) + (PORT datab (291:291:291) (342:342:342)) + (PORT datac (521:521:521) (610:610:610)) + (PORT datad (513:513:513) (589:589:589)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) + (DELAY + (ABSOLUTE + (PORT dataa (174:174:174) (216:216:216)) + (PORT datab (134:134:134) (164:164:164)) + (PORT datac (521:521:521) (610:610:610)) + (PORT datad (512:512:512) (589:589:589)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~52) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (652:652:652)) + (PORT datab (431:431:431) (534:534:534)) + (PORT datac (409:409:409) (501:501:501)) + (PORT datad (347:347:347) (410:410:410)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~49) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (777:777:777)) + (PORT datab (177:177:177) (215:215:215)) + (PORT datac (1069:1069:1069) (1278:1278:1278)) + (PORT datad (333:333:333) (383:383:383)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (121:121:121) (154:154:154)) + (PORT datab (211:211:211) (254:254:254)) + (PORT datac (534:534:534) (624:624:624)) + (PORT datad (440:440:440) (504:504:504)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (141:141:141)) + (PORT datab (106:106:106) (137:137:137)) + (PORT datac (676:676:676) (779:779:779)) + (PORT datad (167:167:167) (197:197:197)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (1029:1029:1029)) + (PORT datab (656:656:656) (763:763:763)) + (PORT datac (739:739:739) (878:878:878)) + (PORT datad (389:389:389) (462:462:462)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (119:119:119) (152:152:152)) + (PORT datab (328:328:328) (383:383:383)) + (PORT datac (623:623:623) (714:714:714)) + (PORT datad (389:389:389) (462:462:462)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (404:404:404) (489:489:489)) + (PORT datab (365:365:365) (435:435:435)) + (PORT datac (351:351:351) (409:409:409)) + (PORT datad (88:88:88) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (115:115:115) (143:143:143)) + (PORT datac (632:632:632) (722:722:722)) + (PORT datad (93:93:93) (113:113:113)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (317:317:317) (378:378:378)) + (PORT datab (635:635:635) (734:734:734)) + (PORT datac (780:780:780) (901:901:901)) + (PORT datad (462:462:462) (529:529:529)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (128:128:128) (164:164:164)) + (PORT datab (539:539:539) (632:632:632)) + (PORT datac (362:362:362) (420:420:420)) + (PORT datad (162:162:162) (187:187:187)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) + (DELAY + (ABSOLUTE + (PORT datab (2033:2033:2033) (2335:2335:2335)) + (PORT datad (842:842:842) (984:984:984)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~8) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (379:379:379)) + (PORT datab (638:638:638) (734:734:734)) + (PORT datac (335:335:335) (389:389:389)) + (PORT datad (449:449:449) (517:517:517)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~48) + (DELAY + (ABSOLUTE + (PORT dataa (1038:1038:1038) (1217:1217:1217)) + (PORT datab (505:505:505) (592:592:592)) + (PORT datac (492:492:492) (551:551:551)) + (PORT datad (471:471:471) (544:544:544)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) + (DELAY + (ABSOLUTE + (PORT datab (354:354:354) (423:423:423)) + (PORT datad (609:609:609) (704:704:704)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~2) + (DELAY + (ABSOLUTE + (PORT datab (473:473:473) (553:553:553)) + (PORT datac (599:599:599) (710:710:710)) + (PORT datad (824:824:824) (965:965:965)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~49) + (DELAY + (ABSOLUTE + (PORT dataa (187:187:187) (223:223:223)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (284:284:284) (327:327:327)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (1125:1125:1125)) + (PORT datab (681:681:681) (810:810:810)) + (PORT datac (743:743:743) (849:849:849)) + (PORT datad (315:315:315) (366:366:366)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1260:1260:1260) (1447:1447:1447)) + (PORT datab (485:485:485) (562:562:562)) + (PORT datac (888:888:888) (1060:1060:1060)) + (PORT datad (951:951:951) (1086:1086:1086)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (499:499:499) (586:586:586)) + (PORT datab (733:733:733) (840:840:840)) + (PORT datac (486:486:486) (566:566:566)) + (PORT datad (780:780:780) (900:900:900)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (436:436:436)) + (PORT datab (812:812:812) (932:932:932)) + (PORT datac (465:465:465) (530:530:530)) + (PORT datad (372:372:372) (437:437:437)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (705:705:705) (828:828:828)) + (PORT datab (505:505:505) (589:589:589)) + (PORT datac (770:770:770) (887:887:887)) + (PORT datad (997:997:997) (1134:1134:1134)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT datac (472:472:472) (537:537:537)) + (PORT datad (171:171:171) (202:202:202)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (140:140:140)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (351:351:351) (406:406:406)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (517:517:517) (600:600:600)) + (PORT datab (553:553:553) (640:640:640)) + (PORT datac (500:500:500) (572:572:572)) + (PORT datad (489:489:489) (563:563:563)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1002:1002:1002) (1151:1151:1151)) + (PORT datab (838:838:838) (984:984:984)) + (PORT datac (598:598:598) (710:710:710)) + (PORT datad (459:459:459) (529:529:529)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (750:750:750)) + (PORT datab (472:472:472) (551:551:551)) + (PORT datac (598:598:598) (710:710:710)) + (PORT datad (819:819:819) (959:959:959)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) + (DELAY + (ABSOLUTE + (PORT dataa (985:985:985) (1126:1126:1126)) + (PORT datab (1067:1067:1067) (1220:1220:1220)) + (PORT datac (845:845:845) (962:962:962)) + (PORT datad (596:596:596) (698:698:698)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) + (DELAY + (ABSOLUTE + (PORT dataa (127:127:127) (163:163:163)) + (PORT datab (127:127:127) (161:161:161)) + (PORT datac (571:571:571) (667:667:667)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (933:933:933) (1127:1127:1127)) + (PORT datac (695:695:695) (833:833:833)) + (PORT datad (615:615:615) (705:705:705)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (767:767:767) (891:891:891)) + (PORT datab (116:116:116) (145:145:145)) + (PORT datac (436:436:436) (495:495:495)) + (PORT datad (464:464:464) (540:540:540)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (760:760:760)) + (PORT datac (497:497:497) (580:580:580)) + (PORT datad (474:474:474) (546:546:546)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (741:741:741) (865:865:865)) + (PORT datab (509:509:509) (586:586:586)) + (PORT datac (826:826:826) (977:977:977)) + (PORT datad (663:663:663) (769:769:769)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -15359,13 +10885,155 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (249:249:249)) - (PORT datab (605:605:605) (698:698:698)) - (PORT datac (589:589:589) (671:671:671)) - (PORT datad (652:652:652) (757:757:757)) + (PORT dataa (511:511:511) (592:592:592)) + (PORT datab (913:913:913) (1076:1076:1076)) + (PORT datac (1237:1237:1237) (1423:1423:1423)) + (PORT datad (904:904:904) (1057:1057:1057)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (152:152:152)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (102:102:102) (123:123:123)) + (PORT datad (665:665:665) (771:771:771)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (1123:1123:1123)) + (PORT datab (184:184:184) (223:223:223)) + (PORT datac (690:690:690) (828:828:828)) + (PORT datad (330:330:330) (383:383:383)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~30) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (381:381:381)) + (PORT datab (526:526:526) (621:621:621)) + (PORT datac (361:361:361) (426:426:426)) + (PORT datad (309:309:309) (362:362:362)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (471:471:471) (556:556:556)) + (PORT datab (109:109:109) (141:141:141)) + (PORT datac (101:101:101) (122:122:122)) + (PORT datad (895:895:895) (1043:1043:1043)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (382:382:382)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (96:96:96) (121:121:121)) + (PORT datad (345:345:345) (404:404:404)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (147:147:147)) + (PORT datab (345:345:345) (413:413:413)) + (PORT datac (450:450:450) (514:514:514)) + (PORT datad (950:950:950) (1084:1084:1084)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (225:225:225)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (676:676:676) (780:780:780)) + (PORT datad (583:583:583) (664:664:664)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) + (DELAY + (ABSOLUTE + (PORT dataa (763:763:763) (911:911:911)) + (PORT datab (631:631:631) (732:732:732)) + (PORT datad (914:914:914) (1081:1081:1081)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (1003:1003:1003)) + (PORT datab (903:903:903) (1068:1068:1068)) + (PORT datac (482:482:482) (564:564:564)) + (PORT datad (750:750:750) (871:871:871)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -15375,13 +11043,752 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) (DELAY (ABSOLUTE - (PORT dataa (619:619:619) (720:720:720)) - (PORT datab (545:545:545) (637:637:637)) - (PORT datac (540:540:540) (631:631:631)) - (PORT datad (619:619:619) (706:706:706)) + (PORT dataa (209:209:209) (255:255:255)) + (PORT datab (131:131:131) (166:166:166)) + (PORT datac (820:820:820) (941:941:941)) + (PORT datad (102:102:102) (120:120:120)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (776:776:776) (891:891:891)) + (PORT datab (579:579:579) (661:661:661)) + (PORT datac (838:838:838) (963:963:963)) + (PORT datad (336:336:336) (388:388:388)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (383:383:383)) + (PORT datab (105:105:105) (135:135:135)) + (PORT datac (326:326:326) (388:388:388)) + (PORT datad (329:329:329) (380:380:380)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (804:804:804)) + (PORT datab (1376:1376:1376) (1582:1582:1582)) + (PORT datac (933:933:933) (1078:1078:1078)) + (PORT datad (551:551:551) (642:642:642)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (655:655:655)) + (PORT datab (425:425:425) (519:519:519)) + (PORT datac (328:328:328) (388:388:388)) + (PORT datad (491:491:491) (558:558:558)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (732:732:732)) + (PORT datab (188:188:188) (225:225:225)) + (PORT datac (517:517:517) (601:601:601)) + (PORT datad (460:460:460) (526:526:526)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (127:127:127) (159:159:159)) + (PORT datac (106:106:106) (137:137:137)) + (PORT datad (471:471:471) (548:548:548)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (855:855:855) (992:992:992)) + (PORT datab (570:570:570) (673:673:673)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (103:103:103) (128:128:128)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (769:769:769) (890:890:890)) + (PORT datab (597:597:597) (681:681:681)) + (PORT datac (755:755:755) (873:873:873)) + (PORT datad (175:175:175) (206:206:206)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (503:503:503) (583:583:583)) + (PORT datab (378:378:378) (461:461:461)) + (PORT datac (362:362:362) (441:441:441)) + (PORT datad (314:314:314) (362:362:362)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (285:285:285)) + (PORT datab (148:148:148) (198:198:198)) + (PORT datac (798:798:798) (958:958:958)) + (PORT datad (661:661:661) (777:777:777)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (1081:1081:1081)) + (PORT datab (1092:1092:1092) (1283:1283:1283)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (1458:1458:1458) (1677:1677:1677)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1235:1235:1235) (1415:1415:1415)) + (PORT datab (1414:1414:1414) (1657:1657:1657)) + (PORT datac (1250:1250:1250) (1429:1429:1429)) + (PORT datad (921:921:921) (1056:1056:1056)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (788:788:788)) + (PORT datab (482:482:482) (558:558:558)) + (PORT datac (1253:1253:1253) (1431:1431:1431)) + (PORT datad (1397:1397:1397) (1634:1634:1634)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (1151:1151:1151) (1305:1305:1305)) + (PORT datad (106:106:106) (125:125:125)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (455:455:455) (528:528:528)) + (PORT datab (454:454:454) (525:525:525)) + (PORT datac (875:875:875) (1046:1046:1046)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (229:229:229)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (671:671:671) (775:775:775)) + (PORT datad (478:478:478) (552:552:552)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~2) + (DELAY + (ABSOLUTE + (PORT datac (455:455:455) (532:532:532)) + (PORT datad (753:753:753) (862:862:862)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (786:786:786) (936:936:936)) + (PORT datab (657:657:657) (768:768:768)) + (PORT datac (985:985:985) (1153:1153:1153)) + (PORT datad (811:811:811) (940:940:940)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (493:493:493) (575:575:575)) + (PORT datab (355:355:355) (416:416:416)) + (PORT datac (1157:1157:1157) (1380:1380:1380)) + (PORT datad (781:781:781) (882:882:882)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (507:507:507)) + (PORT datab (484:484:484) (559:559:559)) + (PORT datad (654:654:654) (755:755:755)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de1) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (926:926:926) (909:909:909)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (408:408:408) (509:509:509)) + (PORT datab (120:120:120) (155:155:155)) + (PORT datac (419:419:419) (479:479:479)) + (PORT datad (122:122:122) (160:160:160)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (726:726:726)) + (PORT datab (511:511:511) (600:600:600)) + (PORT datac (1068:1068:1068) (1277:1277:1277)) + (PORT datad (661:661:661) (773:773:773)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~50) + (DELAY + (ABSOLUTE + (PORT dataa (494:494:494) (578:578:578)) + (PORT datab (238:238:238) (299:299:299)) + (PORT datac (220:220:220) (277:277:277)) + (PORT datad (550:550:550) (641:641:641)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1019:1019:1019) (1189:1189:1189)) + (PORT datab (110:110:110) (141:141:141)) + (PORT datac (380:380:380) (441:441:441)) + (PORT datad (103:103:103) (121:121:121)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (712:712:712)) + (PORT datab (690:690:690) (785:785:785)) + (PORT datac (678:678:678) (782:782:782)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (463:463:463)) + (PORT datab (833:833:833) (958:958:958)) + (PORT datac (1099:1099:1099) (1263:1263:1263)) + (PORT datad (817:817:817) (923:923:923)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (489:489:489) (564:564:564)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (161:161:161) (189:189:189)) + (PORT datad (325:325:325) (370:370:370)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1628:1628:1628) (1913:1913:1913)) + (PORT datab (576:576:576) (658:658:658)) + (PORT datac (841:841:841) (966:966:966)) + (PORT datad (715:715:715) (841:841:841)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (467:467:467) (551:551:551)) + (PORT datab (114:114:114) (146:146:146)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (892:892:892) (1040:1040:1040)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (792:792:792)) + (PORT datab (772:772:772) (887:887:887)) + (PORT datac (674:674:674) (768:768:768)) + (PORT datad (802:802:802) (912:912:912)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (806:806:806)) + (PORT datab (486:486:486) (585:585:585)) + (PORT datac (966:966:966) (1120:1120:1120)) + (PORT datad (466:466:466) (565:565:565)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (400:400:400) (484:484:484)) + (PORT datac (781:781:781) (935:935:935)) + (PORT datad (368:368:368) (444:444:444)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (711:711:711)) + (PORT datab (120:120:120) (151:151:151)) + (PORT datac (770:770:770) (887:887:887)) + (PORT datad (107:107:107) (126:126:126)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (450:450:450)) + (PORT datab (354:354:354) (425:425:425)) + (PORT datac (682:682:682) (791:791:791)) + (PORT datad (613:613:613) (700:700:700)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (721:721:721)) + (PORT datab (101:101:101) (130:130:130)) + (PORT datac (95:95:95) (118:118:118)) + (PORT datad (92:92:92) (111:111:111)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel3) + (DELAY + (ABSOLUTE + (PORT dataa (1264:1264:1264) (1452:1452:1452)) + (PORT datac (883:883:883) (1055:1055:1055)) + (PORT datad (948:948:948) (1082:1082:1082)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (922:922:922)) + (PORT datab (593:593:593) (683:683:683)) + (PORT datac (164:164:164) (197:197:197)) + (PORT datad (332:332:332) (386:386:386)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (703:703:703) (847:847:847)) + (PORT datab (536:536:536) (645:645:645)) + (PORT datac (476:476:476) (554:554:554)) + (PORT datad (341:341:341) (387:387:387)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (401:401:401)) + (PORT datab (818:818:818) (954:954:954)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (696:696:696) (810:810:810)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (669:669:669)) + (PORT datab (478:478:478) (556:556:556)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (495:495:495) (569:569:569)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (123:123:123) (159:159:159)) + (PORT datac (463:463:463) (529:529:529)) + (PORT datad (114:114:114) (136:136:136)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel0) + (DELAY + (ABSOLUTE + (PORT dataa (1311:1311:1311) (1503:1503:1503)) + (PORT datab (1579:1579:1579) (1859:1859:1859)) + (PORT datad (473:473:473) (551:551:551)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (407:407:407)) + (PORT datab (344:344:344) (405:405:405)) + (PORT datac (340:340:340) (383:383:383)) + (PORT datad (626:626:626) (725:725:725)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (403:403:403)) + (PORT datab (338:338:338) (397:397:397)) + (PORT datac (348:348:348) (412:412:412)) + (PORT datad (92:92:92) (111:111:111)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (1002:1002:1002)) + (PORT datab (527:527:527) (613:613:613)) + (PORT datac (724:724:724) (841:841:841)) + (PORT datad (663:663:663) (769:769:769)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (499:499:499) (585:585:585)) + (PORT datab (733:733:733) (841:841:841)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (781:781:781) (900:900:900)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -15391,14 +11798,684 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|carry_borrow_out\~0) + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) (DELAY (ABSOLUTE - (PORT dataa (442:442:442) (522:522:522)) - (PORT datab (758:758:758) (874:874:874)) - (PORT datac (381:381:381) (464:464:464)) - (PORT datad (192:192:192) (224:224:224)) + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (350:350:350) (409:409:409)) + (PORT datac (509:509:509) (586:586:586)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (475:475:475) (562:562:562)) + (PORT datab (800:800:800) (967:967:967)) + (PORT datac (290:290:290) (332:332:332)) + (PORT datad (521:521:521) (621:621:621)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) + (DELAY + (ABSOLUTE + (PORT dataa (735:735:735) (847:847:847)) + (PORT datab (1053:1053:1053) (1256:1256:1256)) + (PORT datac (1069:1069:1069) (1269:1269:1269)) + (PORT datad (582:582:582) (662:662:662)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (128:128:128) (163:163:163)) + (PORT datab (487:487:487) (572:572:572)) + (PORT datac (967:967:967) (1120:1120:1120)) + (PORT datad (346:346:346) (398:398:398)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (611:611:611)) + (PORT datab (793:793:793) (916:916:916)) + (PORT datac (1014:1014:1014) (1146:1146:1146)) + (PORT datad (482:482:482) (562:562:562)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) + (DELAY + (ABSOLUTE + (PORT datab (513:513:513) (592:592:592)) + (PORT datac (737:737:737) (857:857:857)) + (PORT datad (441:441:441) (496:496:496)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (536:536:536) (623:623:623)) + (PORT datab (912:912:912) (1075:1075:1075)) + (PORT datac (1238:1238:1238) (1424:1424:1424)) + (PORT datad (902:902:902) (1055:1055:1055)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (630:630:630)) + (PORT datab (673:673:673) (787:787:787)) + (PORT datac (438:438:438) (504:504:504)) + (PORT datad (319:319:319) (361:361:361)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (661:661:661) (758:758:758)) + (PORT datac (293:293:293) (338:338:338)) + (PORT datad (343:343:343) (401:401:401)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (705:705:705)) + (PORT datab (831:831:831) (943:943:943)) + (PORT datac (560:560:560) (645:645:645)) + (PORT datad (803:803:803) (920:920:920)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) + (DELAY + (ABSOLUTE + (PORT datab (180:180:180) (220:220:220)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (466:466:466) (535:535:535)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (248:248:248)) + (PORT datab (122:122:122) (157:157:157)) + (PORT datac (665:665:665) (759:759:759)) + (PORT datad (345:345:345) (408:408:408)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) + (DELAY + (ABSOLUTE + (PORT dataa (465:465:465) (541:541:541)) + (PORT datab (964:964:964) (1116:1116:1116)) + (PORT datad (1036:1036:1036) (1215:1215:1215)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (408:408:408) (509:509:509)) + (PORT datab (483:483:483) (558:558:558)) + (PORT datad (653:653:653) (754:754:754)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (161:161:161) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de2) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (926:926:926) (909:909:909)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (507:507:507)) + (PORT datab (134:134:134) (183:183:183)) + (PORT datac (417:417:417) (477:477:477)) + (PORT datad (106:106:106) (129:129:129)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) + (DELAY + (ABSOLUTE + (PORT dataa (128:128:128) (163:163:163)) + (PORT datac (760:760:760) (874:874:874)) + (PORT datad (1044:1044:1044) (1189:1189:1189)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) + (DELAY + (ABSOLUTE + (PORT dataa (125:125:125) (158:158:158)) + (PORT datac (756:756:756) (870:870:870)) + (PORT datad (1046:1046:1046) (1191:1191:1191)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (528:528:528) (590:590:590)) + (PORT ena (754:754:754) (814:814:814)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) + (DELAY + (ABSOLUTE + (PORT datab (965:965:965) (1118:1118:1118)) + (PORT datac (454:454:454) (522:522:522)) + (PORT datad (1033:1033:1033) (1212:1212:1212)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (533:533:533) (595:595:595)) + (PORT ena (434:434:434) (466:466:466)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (184:184:184)) + (PORT datab (589:589:589) (679:679:679)) + (PORT datad (189:189:189) (236:236:236)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (791:791:791) (922:922:922)) + (PORT datab (607:607:607) (700:700:700)) + (PORT datac (524:524:524) (617:617:617)) + (PORT datad (310:310:310) (354:354:354)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (251:251:251)) + (PORT datab (118:118:118) (147:147:147)) + (PORT datac (109:109:109) (138:138:138)) + (PORT datad (714:714:714) (802:802:802)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37npla28M3T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (1158:1158:1158) (1388:1388:1388)) + (PORT datab (764:764:764) (927:927:927)) + (PORT datac (613:613:613) (706:706:706)) + (PORT datad (475:475:475) (540:540:540)) (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) + (DELAY + (ABSOLUTE + (PORT dataa (528:528:528) (614:614:614)) + (PORT datab (599:599:599) (688:688:688)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (477:477:477) (545:545:545)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (732:732:732)) + (PORT datab (536:536:536) (635:635:635)) + (PORT datac (668:668:668) (789:789:789)) + (PORT datad (1614:1614:1614) (1855:1855:1855)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (756:756:756) (870:870:870)) + (PORT datad (347:347:347) (399:399:399)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1312:1312:1312) (1556:1556:1556)) + (PORT datab (969:969:969) (1134:1134:1134)) + (PORT datac (799:799:799) (924:924:924)) + (PORT datad (605:605:605) (689:689:689)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (702:702:702)) + (PORT datab (671:671:671) (774:774:774)) + (PORT datac (663:663:663) (757:757:757)) + (PORT datad (1231:1231:1231) (1401:1401:1401)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (731:731:731)) + (PORT datab (104:104:104) (132:132:132)) + (PORT datac (461:461:461) (537:537:537)) + (PORT datad (1107:1107:1107) (1244:1244:1244)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (690:690:690) (801:801:801)) + (PORT datab (749:749:749) (853:853:853)) + (PORT datac (496:496:496) (569:569:569)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) + (DELAY + (ABSOLUTE + (PORT dataa (698:698:698) (821:821:821)) + (PORT datad (483:483:483) (561:561:561)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (597:597:597)) + (PORT datab (350:350:350) (410:410:410)) + (PORT datac (1078:1078:1078) (1250:1250:1250)) + (PORT datad (923:923:923) (1093:1093:1093)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (500:500:500) (580:580:580)) + (PORT datab (527:527:527) (618:618:618)) + (PORT datac (759:759:759) (862:862:862)) + (PORT datad (319:319:319) (369:369:369)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (760:760:760)) + (PORT datab (351:351:351) (418:418:418)) + (PORT datac (483:483:483) (561:561:561)) + (PORT datad (471:471:471) (543:543:543)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (169:169:169)) + (PORT datab (512:512:512) (602:602:602)) + (PORT datac (821:821:821) (939:939:939)) + (PORT datad (454:454:454) (514:514:514)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (142:142:142)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (311:311:311) (357:357:357)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (431:431:431)) + (PORT datab (886:886:886) (1032:1032:1032)) + (PORT datac (725:725:725) (841:841:841)) + (PORT datad (497:497:497) (568:568:568)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (393:393:393)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (327:327:327) (385:385:385)) + (PORT datad (512:512:512) (588:588:588)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (178:178:178) (223:223:223)) + (PORT datab (673:673:673) (780:780:780)) + (PORT datac (871:871:871) (993:993:993)) + (PORT datad (532:532:532) (625:625:625)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (340:340:340) (400:400:400)) + (PORT datad (468:468:468) (538:538:538)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (802:802:802)) + (PORT datab (805:805:805) (933:933:933)) + (PORT datac (617:617:617) (718:718:718)) + (PORT datad (672:672:672) (774:774:774)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (179:179:179) (218:218:218)) + (PORT datab (750:750:750) (862:862:862)) + (PORT datac (599:599:599) (680:680:680)) + (PORT datad (735:735:735) (843:843:843)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -15407,220 +12484,437 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) + (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) (DELAY (ABSOLUTE - (PORT datab (107:107:107) (138:138:138)) - (PORT datac (169:169:169) (201:201:201)) - (PORT datad (132:132:132) (170:170:170)) - (IOPATH datab combout (188:188:188) (181:181:181)) + (PORT dataa (355:355:355) (431:431:431)) + (PORT datab (494:494:494) (575:575:575)) + (PORT datad (652:652:652) (757:757:757)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1242:1242:1242) (1468:1468:1468)) + (PORT datab (895:895:895) (1059:1059:1059)) + (PORT datac (823:823:823) (976:976:976)) + (PORT datad (465:465:465) (538:538:538)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (747:747:747) (829:829:829)) - (PORT ena (422:422:422) (454:454:454)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (PORT dataa (1003:1003:1003) (1151:1151:1151)) + (PORT datab (661:661:661) (772:772:772)) + (PORT datac (1052:1052:1052) (1208:1208:1208)) + (PORT datad (606:606:606) (693:693:693)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (748:748:748) (829:829:829)) - (PORT ena (669:669:669) (725:725:725)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (279:279:279)) - (PORT datab (311:311:311) (370:370:370)) - (PORT datad (118:118:118) (155:155:155)) + (PORT dataa (187:187:187) (228:228:228)) + (PORT datab (340:340:340) (407:407:407)) + (PORT datac (331:331:331) (393:393:393)) + (PORT datad (318:318:318) (370:370:370)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (733:733:733)) + (PORT datab (472:472:472) (551:551:551)) + (PORT datac (988:988:988) (1127:1127:1127)) + (PORT datad (623:623:623) (721:721:721)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (543:543:543) (626:626:626)) + (PORT datab (474:474:474) (547:547:547)) + (PORT datac (510:510:510) (593:593:593)) + (PORT datad (777:777:777) (893:893:893)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]\~feeder) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) (DELAY (ABSOLUTE - (PORT datad (443:443:443) (510:510:510)) + (PORT dataa (115:115:115) (151:151:151)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (647:647:647) (744:744:744)) + (PORT datad (337:337:337) (395:395:395)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (736:736:736) (793:793:793)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (PORT dataa (655:655:655) (774:774:774)) + (PORT datab (538:538:538) (631:631:631)) + (PORT datac (477:477:477) (558:558:558)) + (PORT datad (670:670:670) (782:782:782)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (621:621:621) (686:686:686)) - (PORT ena (660:660:660) (723:723:723)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) (DELAY (ABSOLUTE - (PORT dataa (322:322:322) (387:387:387)) - (PORT datab (444:444:444) (522:522:522)) - (PORT datad (348:348:348) (407:407:407)) + (PORT datab (120:120:120) (150:150:150)) + (PORT datac (327:327:327) (382:382:382)) + (PORT datad (117:117:117) (134:134:134)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) + (DELAY + (ABSOLUTE + (PORT dataa (689:689:689) (804:804:804)) + (PORT datab (528:528:528) (630:630:630)) + (PORT datac (348:348:348) (410:410:410)) + (PORT datad (770:770:770) (920:920:920)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) + (DELAY + (ABSOLUTE + (PORT dataa (494:494:494) (579:579:579)) + (PORT datab (791:791:791) (948:948:948)) + (PORT datac (350:350:350) (412:412:412)) + (PORT datad (187:187:187) (223:223:223)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal61\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1063:1063:1063) (1225:1225:1225)) + (PORT datab (938:938:938) (1119:1119:1119)) + (PORT datac (329:329:329) (387:387:387)) + (PORT datad (975:975:975) (1127:1127:1127)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (697:697:697)) + (PORT datab (488:488:488) (574:574:574)) + (PORT datac (1249:1249:1249) (1432:1432:1432)) + (PORT datad (925:925:925) (1095:1095:1095)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (644:644:644) (719:719:719)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (PORT dataa (740:740:740) (864:864:864)) + (PORT datab (508:508:508) (586:586:586)) + (PORT datac (1236:1236:1236) (1422:1422:1422)) + (PORT datad (896:896:896) (1053:1053:1053)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (644:644:644) (719:719:719)) - (PORT ena (644:644:644) (698:698:698)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~12) (DELAY (ABSOLUTE - (PORT dataa (360:360:360) (433:433:433)) - (PORT datab (131:131:131) (179:179:179)) - (PORT datad (195:195:195) (229:229:229)) + (PORT dataa (537:537:537) (647:647:647)) + (PORT datab (477:477:477) (551:551:551)) + (PORT datac (113:113:113) (138:138:138)) + (PORT datad (106:106:106) (124:124:124)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (419:419:419)) + (PORT datab (684:684:684) (797:797:797)) + (PORT datac (696:696:696) (813:813:813)) + (PORT datad (304:304:304) (351:351:351)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (641:641:641)) + (PORT datab (630:630:630) (728:728:728)) + (PORT datac (746:746:746) (861:861:861)) + (PORT datad (489:489:489) (572:572:572)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]\~feeder) + (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) (DELAY (ABSOLUTE - (PORT datad (440:440:440) (507:507:507)) + (PORT dataa (346:346:346) (406:406:406)) + (PORT datab (508:508:508) (597:597:597)) + (PORT datac (838:838:838) (963:963:963)) + (PORT datad (637:637:637) (731:731:731)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (794:794:794) (880:880:880)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (PORT dataa (493:493:493) (572:572:572)) + (PORT datab (619:619:619) (720:720:720)) + (PORT datac (187:187:187) (227:227:227)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (625:625:625) (689:689:689)) - (PORT ena (631:631:631) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) + (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) (DELAY (ABSOLUTE - (PORT dataa (493:493:493) (580:580:580)) - (PORT datab (322:322:322) (376:376:376)) - (PORT datac (285:285:285) (331:331:331)) - (PORT datad (877:877:877) (1019:1019:1019)) + (PORT dataa (667:667:667) (786:786:786)) + (PORT datab (110:110:110) (140:140:140)) + (PORT datac (97:97:97) (123:123:123)) + (PORT datad (1150:1150:1150) (1334:1334:1334)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) + (DELAY + (ABSOLUTE + (PORT datab (127:127:127) (161:161:161)) + (PORT datac (113:113:113) (139:139:139)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) + (DELAY + (ABSOLUTE + (PORT dataa (2065:2065:2065) (2371:2371:2371)) + (PORT datab (526:526:526) (637:637:637)) + (PORT datac (690:690:690) (812:812:812)) + (PORT datad (373:373:373) (438:438:438)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1109:1109:1109) (1309:1309:1309)) + (PORT datab (813:813:813) (933:933:933)) + (PORT datac (94:94:94) (118:118:118)) + (PORT datad (752:752:752) (914:914:914)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (491:491:491)) + (PORT datab (116:116:116) (145:145:145)) + (PORT datac (886:886:886) (1008:1008:1008)) + (PORT datad (847:847:847) (975:975:975)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (546:546:546) (660:660:660)) + (PORT datab (436:436:436) (540:540:540)) + (PORT datac (839:839:839) (964:964:964)) + (PORT datad (352:352:352) (415:415:415)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1145:1145:1145) (1327:1327:1327)) + (PORT datab (608:608:608) (694:694:694)) + (PORT datac (463:463:463) (540:540:540)) + (PORT datad (369:369:369) (434:434:434)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~39) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (654:654:654)) + (PORT datab (426:426:426) (519:519:519)) + (PORT datac (838:838:838) (963:963:963)) + (PORT datad (495:495:495) (575:575:575)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (147:147:147)) + (PORT datab (814:814:814) (934:934:934)) + (PORT datac (553:553:553) (627:627:627)) + (PORT datad (337:337:337) (397:397:397)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -15628,18 +12922,1526 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) + (DELAY + (ABSOLUTE + (PORT dataa (530:530:530) (604:604:604)) + (PORT datab (699:699:699) (798:798:798)) + (PORT datac (92:92:92) (116:116:116)) + (PORT datad (487:487:487) (554:554:554)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (1114:1114:1114)) + (PORT datac (769:769:769) (879:879:879)) + (PORT datad (960:960:960) (1116:1116:1116)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (395:395:395)) + (PORT datab (104:104:104) (134:134:134)) + (PORT datac (582:582:582) (657:657:657)) + (PORT datad (465:465:465) (541:541:541)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (395:395:395)) + (PORT datab (642:642:642) (742:742:742)) + (PORT datac (262:262:262) (298:298:298)) + (PORT datad (101:101:101) (123:123:123)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) + (DELAY + (ABSOLUTE + (PORT dataa (523:523:523) (637:637:637)) + (PORT datab (850:850:850) (1008:1008:1008)) + (PORT datac (102:102:102) (131:131:131)) + (PORT datad (106:106:106) (130:130:130)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~2) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (955:955:955)) + (PORT datac (671:671:671) (784:784:784)) + (PORT datad (750:750:750) (911:911:911)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) + (DELAY + (ABSOLUTE + (PORT dataa (782:782:782) (955:955:955)) + (PORT datab (944:944:944) (1105:1105:1105)) + (PORT datac (964:964:964) (1133:1133:1133)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~23) + (DELAY + (ABSOLUTE + (PORT dataa (780:780:780) (952:952:952)) + (PORT datab (1483:1483:1483) (1754:1754:1754)) + (PORT datac (679:679:679) (784:784:784)) + (PORT datad (478:478:478) (551:551:551)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (680:680:680) (790:790:790)) + (PORT datab (338:338:338) (395:395:395)) + (PORT datac (113:113:113) (140:140:140)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (956:956:956) (1099:1099:1099)) + (PORT datab (1487:1487:1487) (1762:1762:1762)) + (PORT datac (930:930:930) (1124:1124:1124)) + (PORT datad (861:861:861) (977:977:977)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (819:819:819)) + (PORT datab (603:603:603) (694:694:694)) + (PORT datac (885:885:885) (1044:1044:1044)) + (PORT datad (814:814:814) (943:943:943)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~17) + (DELAY + (ABSOLUTE + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (602:602:602) (688:688:688)) + (PORT datad (118:118:118) (143:143:143)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (951:951:951)) + (PORT datab (854:854:854) (990:990:990)) + (PORT datac (844:844:844) (971:971:971)) + (PORT datad (1114:1114:1114) (1266:1266:1266)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (588:588:588)) + (PORT datab (361:361:361) (428:428:428)) + (PORT datac (333:333:333) (391:391:391)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (144:144:144)) + (PORT datab (346:346:346) (407:407:407)) + (PORT datac (497:497:497) (580:580:580)) + (PORT datad (518:518:518) (601:601:601)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) + (DELAY + (ABSOLUTE + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (721:721:721) (830:830:830)) + (PORT datad (448:448:448) (517:517:517)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~19) + (DELAY + (ABSOLUTE + (PORT dataa (468:468:468) (542:542:542)) + (PORT datab (600:600:600) (690:690:690)) + (PORT datac (267:267:267) (307:307:307)) + (PORT datad (273:273:273) (314:314:314)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) + (DELAY + (ABSOLUTE + (PORT dataa (738:738:738) (862:862:862)) + (PORT datab (1254:1254:1254) (1445:1445:1445)) + (PORT datac (822:822:822) (972:972:972)) + (PORT datad (494:494:494) (562:562:562)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (749:749:749)) + (PORT datab (668:668:668) (777:777:777)) + (PORT datac (482:482:482) (564:564:564)) + (PORT datad (667:667:667) (778:778:778)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (597:597:597)) + (PORT datab (491:491:491) (577:577:577)) + (PORT datac (681:681:681) (780:780:780)) + (PORT datad (317:317:317) (358:358:358)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (736:736:736) (860:860:860)) + (PORT datab (996:996:996) (1143:1143:1143)) + (PORT datac (446:446:446) (527:527:527)) + (PORT datad (1180:1180:1180) (1322:1322:1322)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (719:719:719)) + (PORT datab (672:672:672) (783:783:783)) + (PORT datad (514:514:514) (593:593:593)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (518:518:518) (614:614:614)) + (PORT datab (360:360:360) (415:415:415)) + (PORT datac (452:452:452) (525:525:525)) + (PORT datad (474:474:474) (543:543:543)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) + (DELAY + (ABSOLUTE + (PORT datab (631:631:631) (729:729:729)) + (PORT datac (109:109:109) (132:132:132)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (423:423:423)) + (PORT datab (176:176:176) (214:214:214)) + (PORT datac (629:629:629) (726:726:726)) + (PORT datad (518:518:518) (604:604:604)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (708:708:708)) + (PORT datab (361:361:361) (433:433:433)) + (PORT datac (494:494:494) (574:574:574)) + (PORT datad (445:445:445) (514:514:514)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (113:113:113) (148:148:148)) + (PORT datab (129:129:129) (163:163:163)) + (PORT datac (114:114:114) (141:141:141)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (717:717:717) (825:825:825)) + (PORT datab (1104:1104:1104) (1305:1305:1305)) + (PORT datac (1091:1091:1091) (1266:1266:1266)) + (PORT datad (750:750:750) (873:873:873)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (784:784:784)) + (PORT datab (670:670:670) (777:777:777)) + (PORT datac (557:557:557) (633:633:633)) + (PORT datad (161:161:161) (188:188:188)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1204:1204:1204) (1413:1413:1413)) + (PORT datab (972:972:972) (1160:1160:1160)) + (PORT datac (309:309:309) (359:359:359)) + (PORT datad (1129:1129:1129) (1295:1295:1295)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1174:1174:1174) (1350:1350:1350)) + (PORT datab (662:662:662) (768:768:768)) + (PORT datac (799:799:799) (924:924:924)) + (PORT datad (761:761:761) (873:873:873)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (471:471:471) (555:555:555)) + (PORT datab (368:368:368) (433:433:433)) + (PORT datac (1005:1005:1005) (1146:1146:1146)) + (PORT datad (986:986:986) (1124:1124:1124)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (794:794:794) (911:911:911)) + (PORT datab (492:492:492) (579:579:579)) + (PORT datac (818:818:818) (936:936:936)) + (PORT datad (468:468:468) (533:533:533)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (503:503:503) (593:593:593)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (344:344:344) (405:405:405)) + (PORT datad (337:337:337) (391:391:391)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (481:481:481) (559:559:559)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (95:95:95) (118:118:118)) + (PORT datad (444:444:444) (507:507:507)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (414:414:414)) + (PORT datab (358:358:358) (424:424:424)) + (PORT datac (356:356:356) (408:408:408)) + (PORT datad (178:178:178) (211:211:211)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (810:810:810)) + (PORT datab (673:673:673) (781:781:781)) + (PORT datac (342:342:342) (402:402:402)) + (PORT datad (660:660:660) (757:757:757)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (133:133:133)) + (PORT datab (501:501:501) (574:574:574)) + (PORT datad (331:331:331) (390:390:390)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1328:1328:1328) (1546:1546:1546)) + (PORT datab (533:533:533) (621:621:621)) + (PORT datac (581:581:581) (656:656:656)) + (PORT datad (990:990:990) (1157:1157:1157)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (142:142:142)) + (PORT datab (477:477:477) (544:544:544)) + (PORT datac (664:664:664) (767:767:767)) + (PORT datad (797:797:797) (917:917:917)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datac (939:939:939) (1073:1073:1073)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (391:391:391)) + (PORT datab (298:298:298) (348:348:348)) + (PORT datac (846:846:846) (972:972:972)) + (PORT datad (913:913:913) (1042:1042:1042)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (821:821:821)) + (PORT datab (632:632:632) (734:734:734)) + (PORT datac (504:504:504) (599:599:599)) + (PORT datad (161:161:161) (189:189:189)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (141:141:141)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (555:555:555) (635:635:635)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (989:989:989) (1154:1154:1154)) + (PORT datab (508:508:508) (595:595:595)) + (PORT datac (666:666:666) (769:769:769)) + (PORT datad (1383:1383:1383) (1621:1621:1621)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) + (DELAY + (ABSOLUTE + (PORT datab (356:356:356) (418:418:418)) + (PORT datac (95:95:95) (121:121:121)) + (PORT datad (101:101:101) (123:123:123)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (794:794:794)) + (PORT datab (903:903:903) (1078:1078:1078)) + (PORT datac (854:854:854) (1008:1008:1008)) + (PORT datad (995:995:995) (1153:1153:1153)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1174:1174:1174) (1349:1349:1349)) + (PORT datab (699:699:699) (819:819:819)) + (PORT datac (839:839:839) (965:965:965)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (241:241:241)) + (PORT datab (700:700:700) (820:820:820)) + (PORT datac (637:637:637) (728:728:728)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (113:113:113) (149:149:149)) + (PORT datab (325:325:325) (377:377:377)) + (PORT datac (748:748:748) (855:855:855)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (436:436:436)) + (PORT datab (528:528:528) (616:616:616)) + (PORT datac (840:840:840) (967:967:967)) + (PORT datad (664:664:664) (770:770:770)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) + (DELAY + (ABSOLUTE + (PORT datab (115:115:115) (143:143:143)) + (PORT datac (799:799:799) (921:921:921)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (716:716:716) (844:844:844)) + (PORT datab (667:667:667) (775:775:775)) + (PORT datac (845:845:845) (971:971:971)) + (PORT datad (358:358:358) (415:415:415)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (681:681:681) (788:788:788)) + (PORT datac (845:845:845) (972:972:972)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (903:903:903)) + (PORT datab (958:958:958) (1152:1152:1152)) + (PORT datac (519:519:519) (589:589:589)) + (PORT datad (106:106:106) (124:124:124)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (729:729:729)) + (PORT datab (365:365:365) (432:432:432)) + (PORT datac (346:346:346) (410:410:410)) + (PORT datad (349:349:349) (400:400:400)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (1058:1058:1058)) + (PORT datab (744:744:744) (851:851:851)) + (PORT datac (629:629:629) (723:723:723)) + (PORT datad (332:332:332) (389:389:389)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (750:750:750)) + (PORT datab (750:750:750) (858:858:858)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (142:142:142)) + (PORT datab (357:357:357) (418:418:418)) + (PORT datac (99:99:99) (126:126:126)) + (PORT datad (97:97:97) (118:118:118)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (177:177:177) (220:220:220)) + (PORT datab (431:431:431) (491:491:491)) + (PORT datac (781:781:781) (909:909:909)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (1039:1039:1039)) + (PORT datab (705:705:705) (829:829:829)) + (PORT datac (838:838:838) (965:965:965)) + (PORT datad (1161:1161:1161) (1324:1324:1324)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1008:1008:1008) (1178:1178:1178)) + (PORT datab (901:901:901) (1076:1076:1076)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (894:894:894) (1013:1013:1013)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (993:993:993)) + (PORT datab (985:985:985) (1137:1137:1137)) + (PORT datac (847:847:847) (980:980:980)) + (PORT datad (170:170:170) (201:201:201)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (459:459:459)) + (PORT datab (513:513:513) (593:593:593)) + (PORT datac (968:968:968) (1117:1117:1117)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (991:991:991)) + (PORT datab (609:609:609) (699:699:699)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (1057:1057:1057) (1212:1212:1212)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (458:458:458)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (594:594:594) (678:678:678)) + (PORT datad (939:939:939) (1073:1073:1073)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) + (DELAY + (ABSOLUTE + (PORT dataa (798:798:798) (928:928:928)) + (PORT datab (104:104:104) (132:132:132)) + (PORT datac (339:339:339) (399:399:399)) + (PORT datad (1062:1062:1062) (1217:1217:1217)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (412:412:412)) + (PORT datab (328:328:328) (385:385:385)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (795:795:795) (912:912:912)) + (PORT datab (529:529:529) (622:622:622)) + (PORT datac (673:673:673) (777:777:777)) + (PORT datad (642:642:642) (744:744:744)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (724:724:724)) + (PORT datab (629:629:629) (721:721:721)) + (PORT datac (94:94:94) (118:118:118)) + (PORT datad (104:104:104) (121:121:121)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1132:1132:1132)) + (PORT datab (771:771:771) (887:887:887)) + (PORT datac (666:666:666) (777:777:777)) + (PORT datad (854:854:854) (976:976:976)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (1130:1130:1130)) + (PORT datab (774:774:774) (891:891:891)) + (PORT datac (818:818:818) (940:940:940)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (815:815:815)) + (PORT datab (878:878:878) (1008:1008:1008)) + (PORT datac (515:515:515) (605:605:605)) + (PORT datad (521:521:521) (615:615:615)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (759:759:759)) + (PORT datab (537:537:537) (636:636:636)) + (PORT datac (510:510:510) (599:599:599)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (499:499:499) (585:585:585)) + (PORT datab (1087:1087:1087) (1289:1289:1289)) + (PORT datac (1068:1068:1068) (1268:1268:1268)) + (PORT datad (583:583:583) (662:662:662)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (802:802:802)) + (PORT datab (662:662:662) (772:772:772)) + (PORT datac (455:455:455) (521:521:521)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (146:146:146)) + (PORT datab (329:329:329) (391:391:391)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (500:500:500) (577:577:577)) + (PORT datab (491:491:491) (570:570:570)) + (PORT datac (349:349:349) (405:405:405)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1636:1636:1636) (1867:1867:1867)) + (PORT datab (580:580:580) (692:692:692)) + (PORT datac (100:100:100) (121:121:121)) + (PORT datad (1443:1443:1443) (1656:1656:1656)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (672:672:672) (790:790:790)) + (PORT datab (599:599:599) (687:687:687)) + (PORT datac (755:755:755) (868:868:868)) + (PORT datad (657:657:657) (753:753:753)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (785:785:785) (904:904:904)) + (PORT datab (341:341:341) (405:405:405)) + (PORT datac (332:332:332) (384:384:384)) + (PORT datad (390:390:390) (463:463:463)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (460:460:460) (549:549:549)) + (PORT datab (483:483:483) (563:563:563)) + (PORT datac (1127:1127:1127) (1311:1311:1311)) + (PORT datad (453:453:453) (518:518:518)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1327:1327:1327) (1544:1544:1544)) + (PORT datab (534:534:534) (622:622:622)) + (PORT datac (1025:1025:1025) (1163:1163:1163)) + (PORT datad (990:990:990) (1158:1158:1158)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) + (DELAY + (ABSOLUTE + (PORT datac (653:653:653) (763:763:763)) + (PORT datad (952:952:952) (1106:1106:1106)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1144:1144:1144) (1326:1326:1326)) + (PORT datab (351:351:351) (408:408:408)) + (PORT datac (465:465:465) (542:542:542)) + (PORT datad (372:372:372) (437:437:437)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (148:148:148)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (470:470:470) (537:537:537)) + (PORT datad (174:174:174) (206:206:206)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1084:1084:1084) (1286:1286:1286)) + (PORT datab (854:854:854) (981:981:981)) + (PORT datac (655:655:655) (772:772:772)) + (PORT datad (337:337:337) (392:392:392)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (140:140:140)) + (PORT datab (117:117:117) (146:146:146)) + (PORT datac (316:316:316) (359:359:359)) + (PORT datad (466:466:466) (537:537:537)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (1048:1048:1048)) + (PORT datab (561:561:561) (675:675:675)) + (PORT datac (1281:1281:1281) (1512:1512:1512)) + (PORT datad (337:337:337) (397:397:397)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (229:229:229)) + (PORT datab (475:475:475) (556:556:556)) + (PORT datac (1234:1234:1234) (1420:1420:1420)) + (PORT datad (650:650:650) (751:751:751)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (391:391:391)) + (PORT datab (327:327:327) (387:387:387)) + (PORT datac (582:582:582) (656:656:656)) + (PORT datad (794:794:794) (914:914:914)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (630:630:630)) + (PORT datab (727:727:727) (824:824:824)) + (PORT datac (783:783:783) (897:897:897)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (740:740:740)) + (PORT datab (494:494:494) (577:577:577)) + (PORT datac (329:329:329) (385:385:385)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (830:830:830) (954:954:954)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (102:102:102) (123:123:123)) + (PORT datad (163:163:163) (190:190:190)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (494:494:494) (569:569:569)) + (PORT datab (112:112:112) (144:144:144)) + (PORT datac (321:321:321) (379:379:379)) + (PORT datad (788:788:788) (914:914:914)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (500:500:500) (576:576:576)) + (PORT datab (520:520:520) (613:613:613)) + (PORT datac (393:393:393) (448:448:448)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~42) (DELAY (ABSOLUTE - (PORT dataa (532:532:532) (626:626:626)) - (PORT datab (313:313:313) (361:361:361)) - (PORT datac (549:549:549) (639:639:639)) - (PORT datad (490:490:490) (559:559:559)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (338:338:338) (400:400:400)) + (PORT datab (1032:1032:1032) (1177:1177:1177)) + (PORT datac (522:522:522) (608:608:608)) + (PORT datad (694:694:694) (807:807:807)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -15649,12 +14451,12 @@ (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~43) (DELAY (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (371:371:371) (440:440:440)) - (PORT datac (91:91:91) (112:112:112)) - (PORT datad (89:89:89) (106:106:106)) + (PORT dataa (110:110:110) (144:144:144)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (317:317:317) (370:370:370)) + (PORT datad (574:574:574) (658:658:658)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -15665,10 +14467,10 @@ (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~44) (DELAY (ABSOLUTE - (PORT dataa (281:281:281) (326:326:326)) - (PORT datab (322:322:322) (378:378:378)) - (PORT datac (466:466:466) (543:543:543)) - (PORT datad (317:317:317) (372:372:372)) + (PORT dataa (183:183:183) (229:229:229)) + (PORT datab (346:346:346) (407:407:407)) + (PORT datac (327:327:327) (378:378:378)) + (PORT datad (333:333:333) (389:389:389)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -15676,31 +14478,15 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (412:412:412)) - (PORT datab (350:350:350) (409:409:409)) - (PORT datac (661:661:661) (758:758:758)) - (PORT datad (311:311:311) (362:362:362)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~46) (DELAY (ABSOLUTE - (PORT dataa (108:108:108) (142:142:142)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (327:327:327) (384:384:384)) - (PORT datad (96:96:96) (115:115:115)) + (PORT dataa (507:507:507) (580:580:580)) + (PORT datab (102:102:102) (129:129:129)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (631:631:631) (716:716:716)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -15710,13 +14496,92 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) (DELAY (ABSOLUTE - (PORT datab (790:790:790) (915:915:915)) - (PORT datac (670:670:670) (778:778:778)) - (PORT datad (466:466:466) (542:542:542)) - (IOPATH datab combout (166:166:166) (167:167:167)) + (PORT dataa (470:470:470) (554:554:554)) + (PORT datab (1259:1259:1259) (1482:1482:1482)) + (PORT datac (704:704:704) (843:843:843)) + (PORT datad (1613:1613:1613) (1886:1886:1886)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (382:382:382)) + (PORT datab (373:373:373) (443:443:443)) + (PORT datac (509:509:509) (602:602:602)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (382:382:382)) + (PORT datac (474:474:474) (539:539:539)) + (PORT datad (446:446:446) (511:511:511)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1130:1130:1130) (1277:1277:1277)) + (PORT datab (188:188:188) (226:226:226)) + (PORT datad (476:476:476) (557:557:557)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_af) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (924:924:924) (906:906:906)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (782:782:782) (907:907:907)) + (PORT datab (656:656:656) (766:766:766)) + (PORT datac (461:461:461) (543:543:543)) + (PORT datad (737:737:737) (855:855:855)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -15724,27 +14589,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) (DELAY (ABSOLUTE - (PORT datab (791:791:791) (916:916:916)) - (PORT datac (674:674:674) (783:783:783)) - (PORT datad (465:465:465) (533:533:533)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) - (DELAY - (ABSOLUTE - (PORT datab (789:789:789) (914:914:914)) - (PORT datac (665:665:665) (773:773:773)) - (PORT datad (465:465:465) (533:533:533)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (PORT dataa (983:983:983) (1166:1166:1166)) + (PORT datac (343:343:343) (400:400:400)) + (PORT datad (783:783:783) (926:926:926)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -15752,12 +14603,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (548:548:548) (616:616:616)) - (PORT ena (515:515:515) (556:556:556)) + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (664:664:664) (764:764:764)) + (PORT ena (422:422:422) (450:450:450)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -15768,42 +14619,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~12) (DELAY (ABSOLUTE - (PORT datab (789:789:789) (914:914:914)) - (PORT datac (666:666:666) (774:774:774)) - (PORT datad (468:468:468) (544:544:544)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (551:551:551) (620:620:620)) - (PORT ena (506:506:506) (537:537:537)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (256:256:256) (309:309:309)) - (PORT datab (268:268:268) (320:320:320)) - (PORT datad (118:118:118) (155:155:155)) + (PORT dataa (804:804:804) (955:955:955)) + (PORT datab (352:352:352) (413:413:413)) + (PORT datad (949:949:949) (1123:1123:1123)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -15816,12 +14637,12 @@ (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) (DELAY (ABSOLUTE - (PORT datab (790:790:790) (915:915:915)) - (PORT datac (669:669:669) (777:777:777)) - (PORT datad (578:578:578) (662:662:662)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT dataa (697:697:697) (839:839:839)) + (PORT datab (492:492:492) (570:570:570)) + (PORT datac (811:811:811) (941:941:941)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) ) ) ) @@ -15830,9 +14651,9 @@ (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) (DELAY (ABSOLUTE - (PORT datab (791:791:791) (916:916:916)) - (PORT datac (673:673:673) (782:782:782)) - (PORT datad (549:549:549) (646:646:646)) + (PORT datab (832:832:832) (963:963:963)) + (PORT datac (487:487:487) (568:568:568)) + (PORT datad (677:677:677) (811:811:811)) (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -15844,9 +14665,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (623:623:623) (692:692:692)) - (PORT ena (759:759:759) (842:842:842)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (537:537:537) (608:608:608)) + (PORT ena (797:797:797) (873:873:873)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -15860,12 +14681,12 @@ (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) (DELAY (ABSOLUTE - (PORT datab (791:791:791) (916:916:916)) - (PORT datac (672:672:672) (781:781:781)) - (PORT datad (578:578:578) (661:661:661)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (PORT dataa (707:707:707) (853:853:853)) + (PORT datab (488:488:488) (566:566:566)) + (PORT datac (813:813:813) (942:942:942)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -15874,9 +14695,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (625:625:625) (694:694:694)) - (PORT ena (753:753:753) (845:845:845)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (540:540:540) (612:612:612)) + (PORT ena (782:782:782) (860:860:860)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -15890,23 +14711,23 @@ (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) (DELAY (ABSOLUTE - (PORT datab (793:793:793) (918:918:918)) - (PORT datac (678:678:678) (788:788:788)) - (PORT datad (547:547:547) (644:644:644)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datab (831:831:831) (962:962:962)) + (PORT datac (489:489:489) (571:571:571)) + (PORT datad (672:672:672) (805:805:805)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~41) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~32) (DELAY (ABSOLUTE - (PORT dataa (510:510:510) (624:624:624)) - (PORT datab (130:130:130) (178:178:178)) - (PORT datad (498:498:498) (596:596:596)) + (PORT dataa (512:512:512) (599:599:599)) + (PORT datab (132:132:132) (180:180:180)) + (PORT datad (490:490:490) (569:569:569)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -15916,12 +14737,72 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~3) (DELAY (ABSOLUTE - (PORT datab (669:669:669) (791:791:791)) - (PORT datac (488:488:488) (577:577:577)) - (PORT datad (488:488:488) (567:567:567)) + (PORT dataa (408:408:408) (508:508:508)) + (PORT datab (134:134:134) (183:183:183)) + (PORT datac (419:419:419) (478:478:478)) + (PORT datad (107:107:107) (130:130:130)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (182:182:182) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT datab (831:831:831) (962:962:962)) + (PORT datac (470:470:470) (546:546:546)) + (PORT datad (676:676:676) (810:810:810)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (506:506:506)) + (PORT datab (118:118:118) (153:153:153)) + (PORT datac (416:416:416) (476:476:476)) + (PORT datad (120:120:120) (159:159:159)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) + (DELAY + (ABSOLUTE + (PORT datab (831:831:831) (962:962:962)) + (PORT datac (463:463:463) (537:537:537)) + (PORT datad (673:673:673) (807:807:807)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) + (DELAY + (ABSOLUTE + (PORT datab (832:832:832) (963:963:963)) + (PORT datac (467:467:467) (543:543:543)) + (PORT datad (681:681:681) (818:818:818)) (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -15930,12 +14811,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (638:638:638) (715:715:715)) - (PORT ena (408:408:408) (429:429:429)) + (PORT clk (903:903:903) (907:907:907)) + (PORT asdata (793:793:793) (902:902:902)) + (PORT ena (820:820:820) (910:910:910)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -15946,60 +14827,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~18) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) (DELAY (ABSOLUTE - (PORT dataa (510:510:510) (609:609:609)) - (PORT datab (669:669:669) (792:792:792)) - (PORT datad (480:480:480) (558:558:558)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (730:730:730)) - (PORT datab (106:106:106) (136:136:136)) - (PORT datac (1031:1031:1031) (1204:1204:1204)) - (PORT datad (110:110:110) (135:135:135)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (539:539:539)) - (PORT datab (108:108:108) (138:138:138)) - (PORT datac (339:339:339) (401:401:401)) - (PORT datad (482:482:482) (558:558:558)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) - (DELAY - (ABSOLUTE - (PORT dataa (816:816:816) (949:949:949)) - (PORT datac (442:442:442) (513:513:513)) - (PORT datad (617:617:617) (712:712:712)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT datab (832:832:832) (963:963:963)) + (PORT datac (463:463:463) (537:537:537)) + (PORT datad (675:675:675) (809:809:809)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -16007,12 +14841,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (537:537:537) (596:596:596)) - (PORT ena (405:405:405) (422:422:422)) + (PORT clk (903:903:903) (907:907:907)) + (PORT asdata (790:790:790) (899:899:899)) + (PORT ena (778:778:778) (844:844:844)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -16023,27 +14857,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~31) (DELAY (ABSOLUTE - (PORT dataa (818:818:818) (952:952:952)) - (PORT datac (443:443:443) (515:515:515)) - (PORT datad (619:619:619) (714:714:714)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (683:683:683)) - (PORT datab (650:650:650) (752:752:752)) - (PORT datad (129:129:129) (157:157:157)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (540:540:540) (644:644:644)) + (PORT datab (539:539:539) (625:625:625)) + (PORT datad (186:186:186) (232:232:232)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -16055,7 +14875,23 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (370:370:370) (434:434:434)) + (PORT datad (486:486:486) (585:585:585)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) + (DELAY + (ABSOLUTE + (PORT dataa (793:793:793) (947:947:947)) + (PORT datab (661:661:661) (772:772:772)) + (PORT datac (979:979:979) (1147:1147:1147)) + (PORT datad (813:813:813) (942:942:942)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -16065,9 +14901,9 @@ (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) (DELAY (ABSOLUTE - (PORT datab (613:613:613) (713:713:713)) - (PORT datac (756:756:756) (883:883:883)) - (PORT datad (454:454:454) (522:522:522)) + (PORT datab (939:939:939) (1108:1108:1108)) + (PORT datac (611:611:611) (705:705:705)) + (PORT datad (179:179:179) (214:214:214)) (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -16079,9 +14915,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) + (PORT clk (914:914:914) (922:922:922)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (405:405:405) (422:422:422)) + (PORT ena (408:408:408) (429:429:429)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -16092,27 +14928,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) (DELAY (ABSOLUTE - (PORT dataa (506:506:506) (605:605:605)) - (PORT datab (669:669:669) (791:791:791)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (211:211:211) (264:264:264)) - (PORT datab (506:506:506) (605:605:605)) - (PORT datac (635:635:635) (735:735:735)) - (PORT datad (354:354:354) (415:415:415)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (PORT datab (936:936:936) (1104:1104:1104)) + (PORT datac (609:609:609) (704:704:704)) + (PORT datad (177:177:177) (212:212:212)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -16123,9 +14945,9 @@ (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) (DELAY (ABSOLUTE - (PORT datac (795:795:795) (928:928:928)) - (PORT datad (618:618:618) (713:713:713)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datab (935:935:935) (1103:1103:1103)) + (PORT datad (967:967:967) (1123:1123:1123)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -16135,12 +14957,12 @@ (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) (DELAY (ABSOLUTE - (PORT dataa (653:653:653) (764:764:764)) - (PORT datab (431:431:431) (504:504:504)) - (PORT datac (626:626:626) (722:722:722)) - (PORT datad (370:370:370) (430:430:430)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (796:796:796) (951:951:951)) + (PORT datab (998:998:998) (1166:1166:1166)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (642:642:642) (746:746:746)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -16151,9 +14973,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (810:810:810) (913:913:913)) - (PORT ena (582:582:582) (618:618:618)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (783:783:783) (891:891:891)) + (PORT ena (619:619:619) (665:665:665)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -16164,27 +14986,41 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) (DELAY (ABSOLUTE - (PORT datab (613:613:613) (713:713:713)) - (PORT datac (756:756:756) (883:883:883)) - (PORT datad (453:453:453) (522:522:522)) + (PORT datab (934:934:934) (1102:1102:1102)) + (PORT datac (609:609:609) (703:703:703)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (785:785:785) (934:934:934)) + (PORT datab (196:196:196) (237:237:237)) + (PORT datac (987:987:987) (1155:1155:1155)) + (PORT datad (636:636:636) (739:739:739)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~43) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~34) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (257:257:257)) - (PORT datab (483:483:483) (564:564:564)) - (PORT datad (193:193:193) (221:221:221)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (252:252:252) (318:318:318)) + (PORT datab (269:269:269) (326:326:326)) + (PORT datad (339:339:339) (394:394:394)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -16193,16 +15029,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (215:215:215) (268:268:268)) - (PORT datab (779:779:779) (899:899:899)) - (PORT datac (628:628:628) (727:727:727)) - (PORT datad (351:351:351) (412:412:412)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datad (330:330:330) (385:385:385)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -16212,10 +15042,10 @@ (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) (DELAY (ABSOLUTE - (PORT dataa (633:633:633) (737:737:737)) - (PORT datab (432:432:432) (506:506:506)) - (PORT datac (632:632:632) (729:729:729)) - (PORT datad (375:375:375) (435:435:435)) + (PORT dataa (782:782:782) (908:908:908)) + (PORT datab (657:657:657) (768:768:768)) + (PORT datac (176:176:176) (210:210:210)) + (PORT datad (738:738:738) (855:855:855)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -16228,9 +15058,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) + (PORT clk (903:903:903) (908:908:908)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (776:776:776) (851:851:851)) + (PORT ena (787:787:787) (866:866:866)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -16241,15 +15071,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) (DELAY (ABSOLUTE - (PORT dataa (1009:1009:1009) (1180:1180:1180)) - (PORT datab (530:530:530) (614:614:614)) - (PORT datac (805:805:805) (923:923:923)) - (PORT datad (1092:1092:1092) (1244:1244:1244)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) + (PORT dataa (795:795:795) (949:949:949)) + (PORT datab (191:191:191) (230:230:230)) + (PORT datac (769:769:769) (886:886:886)) + (PORT datad (642:642:642) (745:745:745)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -16257,31 +15087,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) (DELAY (ABSOLUTE - (PORT dataa (329:329:329) (391:391:391)) - (PORT datab (688:688:688) (797:797:797)) - (PORT datac (1033:1033:1033) (1205:1205:1205)) - (PORT datad (605:605:605) (696:696:696)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (360:360:360) (423:423:423)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (94:94:94) (118:118:118)) + (PORT datad (110:110:110) (131:131:131)) + (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) + (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) (DELAY (ABSOLUTE - (PORT dataa (354:354:354) (421:421:421)) - (PORT datab (500:500:500) (585:585:585)) - (PORT datac (474:474:474) (552:552:552)) - (PORT datad (89:89:89) (106:106:106)) + (PORT dataa (1144:1144:1144) (1304:1304:1304)) + (PORT datab (802:802:802) (954:954:954)) + (PORT datac (1164:1164:1164) (1388:1388:1388)) + (PORT datad (474:474:474) (553:553:553)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (677:677:677)) + (PORT datab (710:710:710) (829:829:829)) + (PORT datac (1069:1069:1069) (1218:1218:1218)) + (PORT datad (187:187:187) (218:218:218)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (121:121:121) (154:154:154)) + (PORT datac (326:326:326) (382:382:382)) + (PORT datad (451:451:451) (517:517:517)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -16289,13 +15149,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) (DELAY (ABSOLUTE - (PORT dataa (108:108:108) (142:142:142)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (646:646:646) (737:737:737)) - (PORT datad (109:109:109) (133:133:133)) + (PORT dataa (364:364:364) (431:431:431)) + (PORT datab (116:116:116) (150:150:150)) + (PORT datac (91:91:91) (112:112:112)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) + (DELAY + (ABSOLUTE + (PORT dataa (114:114:114) (145:145:145)) + (PORT datab (104:104:104) (132:132:132)) + (PORT datac (462:462:462) (538:538:538)) + (PORT datad (346:346:346) (402:402:402)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -16303,44 +15179,14 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (461:461:461)) - (PORT datab (107:107:107) (136:136:136)) - (PORT datac (177:177:177) (213:213:213)) - (PORT datad (627:627:627) (725:725:725)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) - (DELAY - (ABSOLUTE - (PORT datab (502:502:502) (587:587:587)) - (PORT datac (301:301:301) (353:353:353)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) (DELAY (ABSOLUTE - (PORT dataa (464:464:464) (547:547:547)) - (PORT datac (614:614:614) (717:717:717)) - (PORT datad (449:449:449) (516:516:516)) + (PORT dataa (539:539:539) (635:635:635)) + (PORT datac (507:507:507) (593:593:593)) + (PORT datad (686:686:686) (796:796:796)) (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -16352,9 +15198,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (810:810:810) (913:913:913)) - (PORT ena (673:673:673) (745:745:745)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (508:508:508) (563:563:563)) + (PORT ena (619:619:619) (666:666:666)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -16368,9 +15214,9 @@ (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) (DELAY (ABSOLUTE - (PORT dataa (462:462:462) (545:545:545)) - (PORT datac (610:610:610) (713:713:713)) - (PORT datad (450:450:450) (517:517:517)) + (PORT dataa (538:538:538) (633:633:633)) + (PORT datac (508:508:508) (593:593:593)) + (PORT datad (685:685:685) (795:795:795)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -16379,31 +15225,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~45) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~36) (DELAY (ABSOLUTE - (PORT dataa (591:591:591) (685:685:685)) - (PORT datab (736:736:736) (875:875:875)) - (PORT datad (454:454:454) (523:523:523)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (129:129:129) (180:180:180)) + (PORT datab (523:523:523) (617:617:617)) + (PORT datad (468:468:468) (549:549:549)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (945:945:945)) + (PORT datab (660:660:660) (771:771:771)) + (PORT datac (176:176:176) (209:209:209)) + (PORT datad (310:310:310) (374:374:374)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) (DELAY (ABSOLUTE - (PORT dataa (347:347:347) (415:415:415)) - (PORT datab (700:700:700) (833:833:833)) - (PORT datac (634:634:634) (734:734:734)) - (PORT datad (197:197:197) (238:238:238)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (792:792:792) (945:945:945)) + (PORT datab (325:325:325) (400:400:400)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (640:640:640) (743:743:743)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -16413,9 +15275,41 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (539:539:539) (600:600:600)) - (PORT ena (627:627:627) (675:675:675)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (795:795:795) (910:910:910)) + (PORT ena (606:606:606) (646:646:646)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (789:789:789) (940:940:940)) + (PORT datab (324:324:324) (398:398:398)) + (PORT datac (175:175:175) (209:209:209)) + (PORT datad (639:639:639) (741:741:741)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (800:800:800) (915:915:915)) + (PORT ena (631:631:631) (686:686:686)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -16429,41 +15323,116 @@ (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) (DELAY (ABSOLUTE - (PORT dataa (212:212:212) (265:265:265)) - (PORT datab (697:697:697) (830:830:830)) - (PORT datac (633:633:633) (732:732:732)) - (PORT datad (353:353:353) (414:414:414)) + (PORT dataa (793:793:793) (946:946:946)) + (PORT datab (660:660:660) (772:772:772)) + (PORT datac (175:175:175) (209:209:209)) + (PORT datad (310:310:310) (375:375:375)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~33) (DELAY (ABSOLUTE - (PORT dataa (349:349:349) (417:417:417)) - (PORT datab (695:695:695) (827:827:827)) - (PORT datac (630:630:630) (729:729:729)) - (PORT datad (200:200:200) (241:241:241)) + (PORT dataa (356:356:356) (420:420:420)) + (PORT datab (132:132:132) (181:181:181)) + (PORT datad (339:339:339) (397:397:397)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (910:910:910)) + (PORT datab (661:661:661) (772:772:772)) + (PORT datac (464:464:464) (546:546:546)) + (PORT datad (741:741:741) (859:859:859)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (958:958:958)) + (PORT datab (475:475:475) (556:556:556)) + (PORT datad (956:956:956) (1130:1130:1130)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (147:147:147)) + (PORT datab (890:890:890) (1036:1036:1036)) + (PORT datac (490:490:490) (573:573:573)) + (PORT datad (112:112:112) (133:133:133)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (1081:1081:1081)) + (PORT datab (200:200:200) (238:238:238)) + (PORT datac (94:94:94) (118:118:118)) + (PORT datad (485:485:485) (558:558:558)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (538:538:538) (599:599:599)) - (PORT ena (670:670:670) (742:742:742)) + (PORT dataa (803:803:803) (955:955:955)) + (PORT datab (480:480:480) (562:562:562)) + (PORT datad (948:948:948) (1122:1122:1122)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (787:787:787) (896:896:896)) + (PORT ena (655:655:655) (718:718:718)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -16474,30 +15443,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~35) (DELAY (ABSOLUTE - (PORT dataa (211:211:211) (264:264:264)) - (PORT datab (700:700:700) (832:832:832)) - (PORT datac (635:635:635) (734:734:734)) - (PORT datad (354:354:354) (415:415:415)) + (PORT dataa (540:540:540) (637:637:637)) + (PORT datab (718:718:718) (840:840:840)) + (PORT datad (471:471:471) (544:544:544)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (272:272:272)) - (PORT datab (898:898:898) (1047:1047:1047)) - (PORT datad (644:644:644) (749:749:749)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -16505,13 +15458,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~46) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~37) (DELAY (ABSOLUTE - (PORT dataa (322:322:322) (386:386:386)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (415:415:415) (471:471:471)) + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (699:699:699) (804:804:804)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (90:90:90) (106:106:106)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -16521,13 +15474,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~47) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~38) (DELAY (ABSOLUTE - (PORT dataa (328:328:328) (393:393:393)) - (PORT datab (172:172:172) (210:210:210)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (334:334:334) (392:392:392)) + (PORT dataa (349:349:349) (409:409:409)) + (PORT datab (290:290:290) (336:336:336)) + (PORT datac (434:434:434) (503:503:503)) + (PORT datad (580:580:580) (687:687:687)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -16535,15 +15488,47 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (749:749:749) (858:858:858)) + (PORT datac (635:635:635) (729:729:729)) + (PORT datad (330:330:330) (387:387:387)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (440:440:440)) + (PORT datab (486:486:486) (570:570:570)) + (PORT datac (670:670:670) (789:789:789)) + (PORT datad (295:295:295) (342:342:342)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) (DELAY (ABSOLUTE - (PORT dataa (504:504:504) (599:599:599)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (346:346:346) (396:396:396)) - (PORT datad (416:416:416) (473:473:473)) + (PORT dataa (115:115:115) (146:146:146)) + (PORT datab (469:469:469) (545:545:545)) + (PORT datac (178:178:178) (212:212:212)) + (PORT datad (625:625:625) (706:706:706)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -16556,9 +15541,9 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) (DELAY (ABSOLUTE - (PORT dataa (594:594:594) (699:699:699)) - (PORT datab (459:459:459) (531:531:531)) - (PORT datac (116:116:116) (144:144:144)) + (PORT dataa (116:116:116) (147:147:147)) + (PORT datab (115:115:115) (144:144:144)) + (PORT datac (337:337:337) (382:382:382)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -16570,10 +15555,10 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) (DELAY (ABSOLUTE - (PORT dataa (350:350:350) (410:410:410)) - (PORT datab (458:458:458) (536:536:536)) - (PORT datac (92:92:92) (114:114:114)) - (PORT datad (470:470:470) (548:548:548)) + (PORT dataa (294:294:294) (343:343:343)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (103:103:103) (120:120:120)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -16586,10 +15571,10 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) (DELAY (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (103:103:103) (125:125:125)) - (PORT datad (103:103:103) (120:120:120)) + (PORT dataa (117:117:117) (148:148:148)) + (PORT datab (118:118:118) (147:147:147)) + (PORT datac (104:104:104) (125:125:125)) + (PORT datad (105:105:105) (123:123:123)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -16602,10 +15587,10 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) (DELAY (ABSOLUTE - (PORT dataa (839:839:839) (955:955:955)) - (PORT datab (475:475:475) (575:575:575)) - (PORT datac (623:623:623) (711:711:711)) - (PORT datad (91:91:91) (109:109:109)) + (PORT dataa (500:500:500) (585:585:585)) + (PORT datab (757:757:757) (870:870:870)) + (PORT datac (754:754:754) (864:864:864)) + (PORT datad (458:458:458) (542:542:542)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -16615,271 +15600,308 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~39) (DELAY (ABSOLUTE - (PORT dataa (729:729:729) (872:872:872)) - (PORT datac (613:613:613) (716:716:716)) - (PORT datad (449:449:449) (516:516:516)) + (PORT dataa (335:335:335) (393:393:393)) + (PORT datab (759:759:759) (873:873:873)) + (PORT datac (219:219:219) (261:261:261)) + (PORT datad (113:113:113) (135:135:135)) (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (747:747:747)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (659:659:659) (734:734:734)) - (PORT ena (515:515:515) (556:556:556)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (658:658:658) (734:734:734)) - (PORT ena (506:506:506) (537:537:537)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) + (INSTANCE z80_\|alu_\|db\[3\]\~13) (DELAY (ABSOLUTE - (PORT dataa (256:256:256) (310:310:310)) - (PORT datab (267:267:267) (319:319:319)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (1077:1077:1077) (1197:1197:1197)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (510:510:510) (609:609:609)) - (PORT datab (669:669:669) (792:792:792)) - (PORT datad (479:479:479) (557:557:557)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT asdata (286:286:286) (308:308:308)) - (PORT ena (776:776:776) (851:851:851)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (937:937:937) (1041:1041:1041)) - (PORT ena (673:673:673) (745:745:745)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (685:685:685)) - (PORT datab (357:357:357) (432:432:432)) - (PORT datad (459:459:459) (529:529:529)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (1203:1203:1203) (1346:1346:1346)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (450:450:450) (528:528:528)) - (PORT datab (650:650:650) (752:752:752)) - (PORT datad (130:130:130) (158:158:158)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (1082:1082:1082) (1206:1206:1206)) - (PORT ena (627:627:627) (675:675:675)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (1084:1084:1084) (1208:1208:1208)) - (PORT ena (670:670:670) (742:742:742)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (266:266:266)) - (PORT datab (890:890:890) (1038:1038:1038)) - (PORT datad (642:642:642) (746:746:746)) + (PORT dataa (847:847:847) (991:991:991)) + (PORT datab (437:437:437) (509:509:509)) + (PORT datac (478:478:478) (573:573:573)) + (PORT datad (465:465:465) (540:540:540)) (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (935:935:935) (1038:1038:1038)) - (PORT ena (582:582:582) (618:618:618)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]\~feeder) + (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) (DELAY (ABSOLUTE - (PORT datad (879:879:879) (1000:1000:1000)) + (PORT dataa (534:534:534) (612:612:612)) + (PORT datab (767:767:767) (880:880:880)) + (PORT datac (613:613:613) (718:718:718)) + (PORT datad (108:108:108) (128:128:128)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (691:691:691)) + (PORT datab (1053:1053:1053) (1212:1212:1212)) + (PORT datac (469:469:469) (545:545:545)) + (PORT datad (341:341:341) (399:399:399)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (739:739:739)) + (PORT datab (806:806:806) (934:934:934)) + (PORT datac (588:588:588) (673:673:673)) + (PORT datad (663:663:663) (767:767:767)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (802:802:802)) + (PORT datab (632:632:632) (735:735:735)) + (PORT datac (508:508:508) (590:590:590)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) + (DELAY + (ABSOLUTE + (PORT dataa (458:458:458) (537:537:537)) + (PORT datab (434:434:434) (500:500:500)) + (PORT datac (876:876:876) (1003:1003:1003)) + (PORT datad (595:595:595) (681:681:681)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (548:548:548) (641:641:641)) + (PORT datab (349:349:349) (410:410:410)) + (PORT datac (490:490:490) (565:565:565)) + (PORT datad (105:105:105) (122:122:122)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (952:952:952)) + (PORT datab (350:350:350) (407:407:407)) + (PORT datac (507:507:507) (592:592:592)) + (PORT datad (657:657:657) (754:754:754)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (114:114:114) (145:145:145)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (757:757:757) (870:870:870)) + (PORT datad (328:328:328) (381:381:381)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) + (DELAY + (ABSOLUTE + (PORT dataa (786:786:786) (905:905:905)) + (PORT datab (192:192:192) (231:231:231)) + (PORT datac (347:347:347) (401:401:401)) + (PORT datad (390:390:390) (463:463:463)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (626:626:626)) + (PORT datab (458:458:458) (537:537:537)) + (PORT datac (281:281:281) (325:325:325)) + (PORT datad (601:601:601) (692:692:692)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (623:623:623) (721:721:721)) + (PORT datab (497:497:497) (576:576:576)) + (PORT datac (681:681:681) (786:786:786)) + (PORT datad (681:681:681) (793:793:793)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) + (DELAY + (ABSOLUTE + (PORT datab (106:106:106) (136:136:136)) + (PORT datac (92:92:92) (115:115:115)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (691:691:691)) + (PORT datab (337:337:337) (392:392:392)) + (PORT datac (100:100:100) (126:126:126)) + (PORT datad (449:449:449) (507:507:507)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) + (DELAY + (ABSOLUTE + (PORT datab (1105:1105:1105) (1307:1307:1307)) + (PORT datac (1092:1092:1092) (1268:1268:1268)) + (PORT datad (926:926:926) (1105:1105:1105)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (774:774:774) (903:903:903)) + (PORT datab (676:676:676) (789:789:789)) + (PORT datac (645:645:645) (750:750:750)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) + (DELAY + (ABSOLUTE + (PORT datac (451:451:451) (525:525:525)) + (PORT datad (338:338:338) (391:391:391)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) + (DELAY + (ABSOLUTE + (PORT dataa (298:298:298) (346:346:346)) + (PORT datab (196:196:196) (237:237:237)) + (PORT datac (600:600:600) (690:690:690)) + (PORT datad (448:448:448) (506:506:506)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) + (INSTANCE z80_\|alu_flags_\|flags_xf) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) + (PORT clk (904:904:904) (909:909:909)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (405:405:405) (422:422:422)) + (PORT ena (421:421:421) (448:448:448)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -16890,28 +15912,145 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) + (INSTANCE z80_\|execute_\|setM1\~50) (DELAY (ABSOLUTE - (PORT dataa (207:207:207) (248:248:248)) - (PORT datab (482:482:482) (562:562:562)) - (PORT datad (462:462:462) (542:542:542)) + (PORT dataa (891:891:891) (1043:1043:1043)) + (PORT datab (910:910:910) (1035:1035:1035)) + (PORT datac (917:917:917) (1055:1055:1055)) + (PORT datad (625:625:625) (724:724:724)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) + (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (334:334:334) (392:392:392)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (91:91:91) (109:109:109)) + (PORT dataa (364:364:364) (434:434:434)) + (PORT datab (800:800:800) (904:904:904)) + (PORT datac (524:524:524) (618:618:618)) + (PORT datad (165:165:165) (193:193:193)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (260:260:260)) + (PORT datab (199:199:199) (236:236:236)) + (PORT datac (520:520:520) (610:610:610)) + (PORT datad (476:476:476) (554:554:554)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (456:456:456) (543:543:543)) + (PORT datab (644:644:644) (744:744:744)) + (PORT datad (310:310:310) (362:362:362)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (389:389:389)) + (PORT datab (215:215:215) (269:269:269)) + (PORT datac (483:483:483) (571:571:571)) + (PORT datad (645:645:645) (743:743:743)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (717:717:717)) + (PORT datad (1041:1041:1041) (1186:1186:1186)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (747:747:747)) + (PORT datab (632:632:632) (732:732:732)) + (PORT datac (763:763:763) (872:872:872)) + (PORT datad (606:606:606) (693:693:693)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (237:237:237)) + (PORT datab (966:966:966) (1114:1114:1114)) + (PORT datac (919:919:919) (1083:1083:1083)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) + (DELAY + (ABSOLUTE + (PORT datac (761:761:761) (875:875:875)) + (PORT datad (1044:1044:1044) (1189:1189:1189)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (748:748:748)) + (PORT datab (633:633:633) (733:733:733)) + (PORT datac (763:763:763) (873:873:873)) + (PORT datad (447:447:447) (511:511:511)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -16921,28 +16060,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) (DELAY (ABSOLUTE (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (1313:1313:1313) (1470:1470:1470)) - (PORT ena (753:753:753) (845:845:845)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (1313:1313:1313) (1469:1469:1469)) - (PORT ena (759:759:759) (842:842:842)) + (PORT asdata (352:352:352) (384:384:384)) + (PORT ena (409:409:409) (429:429:429)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -16953,11 +16076,154 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) (DELAY (ABSOLUTE - (PORT dataa (508:508:508) (621:621:621)) - (PORT datab (514:514:514) (622:622:622)) + (PORT dataa (189:189:189) (236:236:236)) + (PORT datab (966:966:966) (1113:1113:1113)) + (PORT datac (917:917:917) (1081:1081:1081)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (931:931:931) (1043:1043:1043)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (184:184:184)) + (PORT datab (819:819:819) (974:974:974)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) + (DELAY + (ABSOLUTE + (PORT dataa (703:703:703) (848:848:848)) + (PORT datac (571:571:571) (660:660:660)) + (PORT datad (770:770:770) (876:876:876)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (718:718:718)) + (PORT datab (193:193:193) (230:230:230)) + (PORT datad (1042:1042:1042) (1188:1188:1188)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (841:841:841)) + (PORT datac (569:569:569) (659:659:659)) + (PORT datad (768:768:768) (873:873:873)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (896:896:896) (995:995:995)) + (PORT ena (594:594:594) (642:642:642)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (491:491:491) (569:569:569)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (718:718:718)) + (PORT datab (192:192:192) (229:229:229)) + (PORT datad (1043:1043:1043) (1189:1189:1189)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (665:665:665) (725:725:725)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (393:393:393)) + (PORT datab (517:517:517) (607:607:607)) (PORT datad (116:116:116) (153:153:153)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) @@ -16968,72 +16234,58 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) (DELAY (ABSOLUTE - (PORT dataa (344:344:344) (405:405:405)) - (PORT datab (101:101:101) (129:129:129)) - (PORT datac (321:321:321) (375:375:375)) - (PORT datad (160:160:160) (183:183:183)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (504:504:504) (602:602:602)) - (PORT datab (284:284:284) (333:333:333)) - (PORT datac (591:591:591) (692:692:692)) - (PORT datad (731:731:731) (840:840:840)) + (PORT dataa (717:717:717) (846:846:846)) + (PORT datab (558:558:558) (657:657:657)) + (PORT datac (507:507:507) (593:593:593)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) (DELAY (ABSOLUTE - (PORT dataa (465:465:465) (542:542:542)) - (PORT datac (609:609:609) (712:712:712)) - (PORT datad (459:459:459) (536:536:536)) + (PORT dataa (739:739:739) (860:860:860)) + (PORT datab (120:120:120) (150:150:150)) + (PORT datac (603:603:603) (699:699:699)) + (PORT datad (312:312:312) (377:377:377)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) (DELAY (ABSOLUTE - (PORT dataa (464:464:464) (542:542:542)) - (PORT datac (612:612:612) (714:714:714)) - (PORT datad (460:460:460) (536:536:536)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (403:403:403) (504:504:504)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (455:455:455) (531:531:531)) + (PORT datad (752:752:752) (862:862:862)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT asdata (768:768:768) (868:868:868)) - (PORT ena (480:480:480) (509:509:509)) + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (515:515:515) (574:574:574)) + (PORT ena (666:666:666) (729:729:729)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -17044,29 +16296,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) (DELAY (ABSOLUTE - (PORT dataa (640:640:640) (739:739:739)) - (PORT datab (446:446:446) (520:520:520)) - (PORT datac (613:613:613) (716:716:716)) - (PORT datad (460:460:460) (536:536:536)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (153:153:153)) - (PORT datab (213:213:213) (257:257:257)) - (PORT datad (203:203:203) (241:241:241)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (669:669:669) (782:782:782)) + (PORT datab (372:372:372) (441:441:441)) + (PORT datad (532:532:532) (613:613:613)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -17075,13 +16311,90 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) (DELAY (ABSOLUTE - (PORT dataa (729:729:729) (871:871:871)) - (PORT datac (613:613:613) (715:715:715)) - (PORT datad (449:449:449) (516:516:516)) + (PORT dataa (715:715:715) (843:843:843)) + (PORT datab (560:560:560) (660:660:660)) + (PORT datac (509:509:509) (596:596:596)) (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (516:516:516) (575:575:575)) + (PORT ena (603:603:603) (650:650:650)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (267:267:267)) + (PORT datab (102:102:102) (131:131:131)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) + (DELAY + (ABSOLUTE + (PORT dataa (791:791:791) (944:944:944)) + (PORT datab (660:660:660) (771:771:771)) + (PORT datac (983:983:983) (1151:1151:1151)) + (PORT datad (286:286:286) (326:326:326)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT asdata (602:602:602) (664:664:664)) + (PORT ena (495:495:495) (537:537:537)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) + (DELAY + (ABSOLUTE + (PORT dataa (975:975:975) (1134:1134:1134)) + (PORT datab (739:739:739) (856:856:856)) + (PORT datac (603:603:603) (700:700:700)) + (PORT datad (602:602:602) (693:693:693)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -17089,12 +16402,119 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) (DELAY (ABSOLUTE - (PORT dataa (130:130:130) (180:180:180)) - (PORT datac (428:428:428) (511:511:511)) - (PORT datad (343:343:343) (399:399:399)) + (PORT dataa (624:624:624) (721:721:721)) + (PORT datab (325:325:325) (400:400:400)) + (PORT datac (721:721:721) (833:833:833)) + (PORT datad (434:434:434) (496:496:496)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT asdata (600:600:600) (661:661:661)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) + (DELAY + (ABSOLUTE + (PORT dataa (742:742:742) (863:863:863)) + (PORT datab (119:119:119) (148:148:148)) + (PORT datac (604:604:604) (700:700:700)) + (PORT datad (313:313:313) (378:378:378)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (181:181:181)) + (PORT datab (133:133:133) (167:167:167)) + (PORT datad (113:113:113) (135:135:135)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (421:421:421)) + (PORT datab (344:344:344) (407:407:407)) + (PORT datac (411:411:411) (468:468:468)) + (PORT datad (337:337:337) (393:393:393)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (845:845:845)) + (PORT datac (462:462:462) (536:536:536)) + (PORT datad (769:769:769) (875:875:875)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) + (DELAY + (ABSOLUTE + (PORT dataa (708:708:708) (854:854:854)) + (PORT datac (466:466:466) (542:542:542)) + (PORT datad (773:773:773) (879:879:879)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT dataa (706:706:706) (852:852:852)) + (PORT datac (467:467:467) (543:543:543)) + (PORT datad (772:772:772) (878:878:878)) (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -17102,14 +16522,162 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT dataa (128:128:128) (164:164:164)) - (PORT datab (122:122:122) (153:153:153)) - (PORT datac (589:589:589) (685:685:685)) - (PORT datad (115:115:115) (137:137:137)) + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (641:641:641) (717:717:717)) + (PORT ena (503:503:503) (543:543:543)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (372:372:372) (442:442:442)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) + (DELAY + (ABSOLUTE + (PORT dataa (704:704:704) (849:849:849)) + (PORT datac (461:461:461) (535:535:535)) + (PORT datad (771:771:771) (877:877:877)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (473:473:473) (498:498:498)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (269:269:269)) + (PORT datab (234:234:234) (280:280:280)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (579:579:579) (634:634:634)) + (PORT ena (754:754:754) (814:814:814)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (578:578:578) (632:632:632)) + (PORT ena (434:434:434) (466:466:466)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (180:180:180)) + (PORT datab (590:590:590) (680:680:680)) + (PORT datad (188:188:188) (231:231:231)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (417:417:417)) + (PORT datab (350:350:350) (420:420:420)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~91) + (DELAY + (ABSOLUTE + (PORT dataa (1058:1058:1058) (1215:1215:1215)) + (PORT datab (1046:1046:1046) (1222:1222:1222)) + (PORT datac (112:112:112) (139:139:139)) + (PORT datad (104:104:104) (122:122:122)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (470:470:470) (547:547:547)) + (PORT datab (478:478:478) (555:555:555)) + (PORT datac (278:278:278) (314:314:314)) + (PORT datad (337:337:337) (389:389:389)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -17119,28 +16687,60 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (288:288:288)) - (PORT datab (150:150:150) (202:202:202)) - (PORT datac (723:723:723) (827:827:827)) - (PORT datad (95:95:95) (116:116:116)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (653:653:653) (759:759:759)) + (PORT datab (567:567:567) (657:657:657)) + (PORT datac (381:381:381) (454:454:454)) + (PORT datad (616:616:616) (712:712:712)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (806:806:806)) + (PORT datab (380:380:380) (446:446:446)) + (PORT datac (282:282:282) (328:328:328)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (273:273:273) (318:318:318)) + (PORT datab (352:352:352) (421:421:421)) + (PORT datac (345:345:345) (397:397:397)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) + (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (434:434:434) (466:466:466)) + (PORT ena (640:640:640) (702:702:702)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -17151,28 +16751,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) (DELAY (ABSOLUTE (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (504:504:504) (554:554:554)) - (PORT ena (753:753:753) (845:845:845)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (504:504:504) (554:554:554)) - (PORT ena (759:759:759) (842:842:842)) + (PORT asdata (280:280:280) (300:300:300)) + (PORT ena (650:650:650) (698:698:698)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -17183,12 +16767,1365 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) (DELAY (ABSOLUTE - (PORT dataa (504:504:504) (616:616:616)) - (PORT datab (516:516:516) (624:624:624)) - (PORT datad (115:115:115) (152:152:152)) + (PORT dataa (809:809:809) (944:944:944)) + (PORT datab (301:301:301) (351:351:351)) + (PORT datad (349:349:349) (404:404:404)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (260:260:260)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (328:328:328) (383:383:383)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (545:545:545) (640:640:640)) + (PORT datab (228:228:228) (290:290:290)) + (PORT datac (660:660:660) (754:754:754)) + (PORT datad (223:223:223) (278:278:278)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (1015:1015:1015) (1166:1166:1166)) + (PORT datab (689:689:689) (783:783:783)) + (PORT datac (675:675:675) (779:779:779)) + (PORT datad (551:551:551) (642:642:642)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (501:501:501) (583:583:583)) + (PORT datad (97:97:97) (118:118:118)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (1064:1064:1064)) + (PORT datab (661:661:661) (772:772:772)) + (PORT datac (339:339:339) (396:396:396)) + (PORT datad (466:466:466) (559:559:559)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (407:407:407)) + (PORT datab (336:336:336) (395:395:395)) + (PORT datad (486:486:486) (558:558:558)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (503:503:503) (584:584:584)) + (PORT datab (621:621:621) (716:716:716)) + (PORT datac (911:911:911) (1032:1032:1032)) + (PORT datad (488:488:488) (556:556:556)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (212:212:212)) + (PORT datab (505:505:505) (579:579:579)) + (PORT datac (586:586:586) (667:667:667)) + (PORT datad (604:604:604) (688:688:688)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (744:744:744)) + (PORT datab (485:485:485) (584:584:584)) + (PORT datac (629:629:629) (725:725:725)) + (PORT datad (465:465:465) (533:533:533)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (715:715:715)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (549:549:549) (634:634:634)) + (PORT datad (497:497:497) (576:576:576)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (546:546:546) (655:655:655)) + (PORT datab (522:522:522) (625:625:625)) + (PORT datac (582:582:582) (666:666:666)) + (PORT datad (102:102:102) (126:126:126)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) + (DELAY + (ABSOLUTE + (PORT dataa (499:499:499) (579:579:579)) + (PORT datab (450:450:450) (515:515:515)) + (PORT datac (216:216:216) (277:277:277)) + (PORT datad (345:345:345) (416:416:416)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (717:717:717)) + (PORT datab (205:205:205) (266:266:266)) + (PORT datac (597:597:597) (683:683:683)) + (PORT datad (347:347:347) (418:418:418)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (110:110:110) (142:142:142)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (316:316:316) (365:365:365)) + (PORT datab (872:872:872) (1007:1007:1007)) + (PORT datac (95:95:95) (120:120:120)) + (PORT datad (469:469:469) (546:546:546)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) + (DELAY + (ABSOLUTE + (PORT dataa (404:404:404) (488:488:488)) + (PORT datab (119:119:119) (147:147:147)) + (PORT datac (107:107:107) (130:130:130)) + (PORT datad (543:543:543) (640:640:640)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (810:810:810) (945:945:945)) + (PORT datab (342:342:342) (406:406:406)) + (PORT datac (667:667:667) (776:776:776)) + (PORT datad (355:355:355) (411:411:411)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~25) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (256:256:256)) + (PORT datab (160:160:160) (215:215:215)) + (PORT datad (135:135:135) (176:176:176)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (422:422:422)) + (PORT datab (556:556:556) (634:634:634)) + (PORT datac (691:691:691) (805:805:805)) + (PORT datad (1118:1118:1118) (1256:1256:1256)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla20M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (542:542:542) (655:655:655)) + (PORT datab (433:433:433) (536:536:536)) + (PORT datac (838:838:838) (963:963:963)) + (PORT datad (496:496:496) (576:576:576)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) + (DELAY + (ABSOLUTE + (PORT dataa (399:399:399) (495:495:495)) + (PORT datab (1406:1406:1406) (1621:1621:1621)) + (PORT datac (741:741:741) (851:851:851)) + (PORT datad (396:396:396) (481:481:481)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) + (DELAY + (ABSOLUTE + (PORT dataa (455:455:455) (527:527:527)) + (PORT datab (351:351:351) (413:413:413)) + (PORT datac (463:463:463) (529:529:529)) + (PORT datad (459:459:459) (528:528:528)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) + (DELAY + (ABSOLUTE + (PORT dataa (546:546:546) (656:656:656)) + (PORT datab (487:487:487) (564:564:564)) + (PORT datac (505:505:505) (602:602:602)) + (PORT datad (102:102:102) (124:124:124)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (709:709:709)) + (PORT datab (101:101:101) (130:130:130)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (783:783:783)) + (PORT datab (1123:1123:1123) (1302:1302:1302)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (312:312:312) (354:354:354)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (924:924:924)) + (PORT datab (833:833:833) (963:963:963)) + (PORT datac (474:474:474) (555:555:555)) + (PORT datad (654:654:654) (740:740:740)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (744:744:744)) + (PORT datab (472:472:472) (541:541:541)) + (PORT datac (368:368:368) (447:447:447)) + (PORT datad (595:595:595) (681:681:681)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) + (DELAY + (ABSOLUTE + (PORT dataa (950:950:950) (1091:1091:1091)) + (PORT datab (1125:1125:1125) (1305:1305:1305)) + (PORT datac (342:342:342) (397:397:397)) + (PORT datad (447:447:447) (513:513:513)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (755:755:755)) + (PORT datab (387:387:387) (456:456:456)) + (PORT datac (101:101:101) (121:121:121)) + (PORT datad (379:379:379) (458:458:458)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) + (DELAY + (ABSOLUTE + (PORT dataa (123:123:123) (157:157:157)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (333:333:333) (385:385:385)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1252:1252:1252) (1454:1454:1454)) + (PORT datab (820:820:820) (953:953:953)) + (PORT datac (403:403:403) (472:472:472)) + (PORT datad (114:114:114) (136:136:136)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (545:545:545) (654:654:654)) + (PORT datab (524:524:524) (627:627:627)) + (PORT datac (326:326:326) (374:374:374)) + (PORT datad (652:652:652) (743:743:743)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~17) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (376:376:376)) + (PORT datab (305:305:305) (357:357:357)) + (PORT datac (1235:1235:1235) (1429:1429:1429)) + (PORT datad (285:285:285) (325:325:325)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~19) + (DELAY + (ABSOLUTE + (PORT dataa (770:770:770) (886:886:886)) + (PORT datab (417:417:417) (491:491:491)) + (PORT datac (1236:1236:1236) (1430:1430:1430)) + (PORT datad (712:712:712) (831:831:831)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (545:545:545) (646:646:646)) + (PORT datab (780:780:780) (914:914:914)) + (PORT datac (401:401:401) (469:469:469)) + (PORT datad (507:507:507) (586:586:586)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~20) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (144:144:144)) + (PORT datab (123:123:123) (155:155:155)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (94:94:94) (114:114:114)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~36) + (DELAY + (ABSOLUTE + (PORT dataa (435:435:435) (531:531:531)) + (PORT datab (428:428:428) (530:530:530)) + (PORT datac (344:344:344) (401:401:401)) + (PORT datad (396:396:396) (481:481:481)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~15) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (384:384:384)) + (PORT datab (402:402:402) (473:473:473)) + (PORT datac (1124:1124:1124) (1294:1294:1294)) + (PORT datad (435:435:435) (499:499:499)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~16) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (507:507:507)) + (PORT datab (431:431:431) (533:533:533)) + (PORT datac (424:424:424) (514:514:514)) + (PORT datad (1037:1037:1037) (1201:1201:1201)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~21) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (430:430:430)) + (PORT datab (107:107:107) (136:136:136)) + (PORT datac (273:273:273) (311:311:311)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (713:713:713)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (440:440:440) (499:499:499)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (1045:1045:1045)) + (PORT datab (1139:1139:1139) (1315:1315:1315)) + (PORT datac (472:472:472) (550:550:550)) + (PORT datad (789:789:789) (889:889:889)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) + (DELAY + (ABSOLUTE + (PORT datab (427:427:427) (528:528:528)) + (PORT datac (415:415:415) (504:504:504)) + (PORT datad (563:563:563) (631:631:631)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~34) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (494:494:494)) + (PORT datab (1344:1344:1344) (1567:1567:1567)) + (PORT datac (417:417:417) (506:506:506)) + (PORT datad (354:354:354) (415:415:415)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~22) + (DELAY + (ABSOLUTE + (PORT datab (643:643:643) (760:760:760)) + (PORT datac (497:497:497) (588:588:588)) + (PORT datad (390:390:390) (470:470:470)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1419:1419:1419) (1644:1644:1644)) + (PORT datab (511:511:511) (599:599:599)) + (PORT datac (612:612:612) (696:696:696)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~35) + (DELAY + (ABSOLUTE + (PORT dataa (489:489:489) (575:575:575)) + (PORT datab (428:428:428) (529:529:529)) + (PORT datac (417:417:417) (506:506:506)) + (PORT datad (302:302:302) (347:347:347)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~24) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (133:133:133)) + (PORT datab (110:110:110) (142:142:142)) + (PORT datac (92:92:92) (115:115:115)) + (PORT datad (108:108:108) (129:129:129)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) + (DELAY + (ABSOLUTE + (PORT datab (207:207:207) (251:251:251)) + (PORT datad (467:467:467) (546:546:546)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (698:698:698)) + (PORT datab (235:235:235) (281:281:281)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (1100:1100:1100) (1235:1235:1235)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (651:651:651)) + (PORT datab (783:783:783) (917:917:917)) + (PORT datac (1235:1235:1235) (1429:1429:1429)) + (PORT datad (508:508:508) (587:587:587)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (220:220:220)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (886:886:886) (1003:1003:1003)) + (PORT datad (94:94:94) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (433:433:433)) + (PORT datab (115:115:115) (143:143:143)) + (PORT datac (490:490:490) (563:563:563)) + (PORT datad (796:796:796) (916:916:916)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (811:811:811) (935:935:935)) + (PORT datac (175:175:175) (210:210:210)) + (PORT datad (114:114:114) (135:135:135)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~95) + (DELAY + (ABSOLUTE + (PORT dataa (438:438:438) (534:534:534)) + (PORT datab (1347:1347:1347) (1571:1571:1571)) + (PORT datac (343:343:343) (400:400:400)) + (PORT datad (374:374:374) (455:455:455)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (430:430:430)) + (PORT datab (107:107:107) (136:136:136)) + (PORT datac (271:271:271) (309:309:309)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~27) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (145:145:145)) + (PORT datab (124:124:124) (156:156:156)) + (PORT datac (402:402:402) (470:470:470)) + (PORT datad (115:115:115) (137:137:137)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (250:250:250)) + (PORT datab (163:163:163) (218:218:218)) + (PORT datac (617:617:617) (718:718:718)) + (PORT datad (136:136:136) (176:176:176)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) + (DELAY + (ABSOLUTE + (PORT dataa (1250:1250:1250) (1454:1454:1454)) + (PORT datab (124:124:124) (155:155:155)) + (PORT datac (340:340:340) (395:395:395)) + (PORT datad (564:564:564) (630:630:630)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (814:814:814) (938:938:938)) + (PORT datac (807:807:807) (935:935:935)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) + (DELAY + (ABSOLUTE + (PORT dataa (299:299:299) (347:347:347)) + (PORT datab (282:282:282) (326:326:326)) + (PORT datac (747:747:747) (846:846:846)) + (PORT datad (354:354:354) (404:404:404)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) + (DELAY + (ABSOLUTE + (PORT dataa (286:286:286) (336:336:336)) + (PORT datab (114:114:114) (147:147:147)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (113:113:113) (134:134:134)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (343:343:343) (408:408:408)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (331:331:331) (385:385:385)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (573:573:573)) + (PORT datab (1113:1113:1113) (1259:1259:1259)) + (PORT datac (427:427:427) (495:495:495)) + (PORT datad (468:468:468) (547:547:547)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~26) + (DELAY + (ABSOLUTE + (PORT datab (115:115:115) (148:148:148)) + (PORT datac (95:95:95) (119:119:119)) + (PORT datad (114:114:114) (135:135:135)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (1128:1128:1128) (1300:1300:1300)) + (PORT datac (471:471:471) (569:569:569)) + (PORT datad (283:283:283) (324:324:324)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (327:327:327) (384:384:384)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) + (DELAY + (ABSOLUTE + (PORT dataa (119:119:119) (152:152:152)) + (PORT datab (115:115:115) (144:144:144)) + (PORT datac (101:101:101) (122:122:122)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~89) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (396:396:396)) + (PORT datab (114:114:114) (141:141:141)) + (PORT datad (174:174:174) (206:206:206)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~90) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (756:756:756)) + (PORT datab (235:235:235) (281:281:281)) + (PORT datac (423:423:423) (502:502:502)) + (PORT datad (1107:1107:1107) (1276:1276:1276)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~91) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (675:675:675) (771:771:771)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (1099:1099:1099) (1234:1234:1234)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) + (DELAY + (ABSOLUTE + (PORT dataa (493:493:493) (570:570:570)) + (PORT datab (522:522:522) (603:603:603)) + (PORT datac (524:524:524) (634:634:634)) + (PORT datad (682:682:682) (804:804:804)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (555:555:555)) + (PORT datab (298:298:298) (345:345:345)) + (PORT datac (1504:1504:1504) (1707:1707:1707)) + (PORT datad (166:166:166) (196:196:196)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~100) + (DELAY + (ABSOLUTE + (PORT dataa (548:548:548) (662:662:662)) + (PORT datab (438:438:438) (541:541:541)) + (PORT datac (403:403:403) (495:495:495)) + (PORT datad (895:895:895) (1024:1024:1024)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~92) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (133:133:133)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (280:280:280) (320:320:320)) + (PORT datad (1099:1099:1099) (1234:1234:1234)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~28) + (DELAY + (ABSOLUTE + (PORT dataa (723:723:723) (858:858:858)) + (PORT datab (841:841:841) (967:967:967)) + (PORT datac (343:343:343) (408:408:408)) + (PORT datad (468:468:468) (562:562:562)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) + (DELAY + (ABSOLUTE + (PORT dataa (465:465:465) (553:553:553)) + (PORT datab (110:110:110) (141:141:141)) + (PORT datac (593:593:593) (677:677:677)) + (PORT datad (195:195:195) (229:229:229)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1418:1418:1418) (1643:1643:1643)) + (PORT datab (522:522:522) (610:610:610)) + (PORT datac (723:723:723) (813:813:813)) + (PORT datad (474:474:474) (545:545:545)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~30) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (276:276:276)) + (PORT datab (523:523:523) (611:611:611)) + (PORT datac (744:744:744) (850:850:850)) + (PORT datad (93:93:93) (112:112:112)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~31) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (274:274:274)) + (PORT datab (490:490:490) (570:570:570)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~32) + (DELAY + (ABSOLUTE + (PORT dataa (179:179:179) (223:223:223)) + (PORT datab (208:208:208) (252:252:252)) + (PORT datac (96:96:96) (120:120:120)) + (PORT datad (467:467:467) (546:546:546)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~93) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (1100:1100:1100) (1235:1235:1235)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) + (DELAY + (ABSOLUTE + (PORT datab (779:779:779) (897:897:897)) + (PORT datac (763:763:763) (873:873:873)) + (PORT datad (575:575:575) (662:662:662)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (532:532:532) (591:591:591)) + (PORT ena (594:594:594) (642:642:642)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (533:533:533) (591:591:591)) + (PORT ena (665:665:665) (725:725:725)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (391:391:391)) + (PORT datab (516:516:516) (605:605:605)) + (PORT datad (116:116:116) (153:153:153)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -17196,14 +18133,62 @@ ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (350:350:350) (375:375:375)) + (PORT ena (666:666:666) (729:729:729)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (253:253:253)) + (PORT datab (497:497:497) (582:582:582)) + (PORT datac (525:525:525) (616:616:616)) + (PORT datad (102:102:102) (118:118:118)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (477:477:477) (554:554:554)) + (PORT datab (476:476:476) (557:557:557)) + (PORT datac (430:430:430) (494:494:494)) + (PORT datad (298:298:298) (337:337:337)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (753:753:753) (853:853:853)) - (PORT ena (515:515:515) (556:556:556)) + (PORT clk (903:903:903) (907:907:907)) + (PORT asdata (696:696:696) (773:773:773)) + (PORT ena (820:820:820) (910:910:910)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -17217,9 +18202,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (749:749:749) (850:850:850)) - (PORT ena (506:506:506) (537:537:537)) + (PORT clk (903:903:903) (907:907:907)) + (PORT asdata (699:699:699) (777:777:777)) + (PORT ena (778:778:778) (844:844:844)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -17233,8 +18218,8 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) (DELAY (ABSOLUTE - (PORT dataa (255:255:255) (309:309:309)) - (PORT datab (269:269:269) (321:321:321)) + (PORT dataa (538:538:538) (642:642:642)) + (PORT datab (536:536:536) (622:622:622)) (PORT datad (119:119:119) (156:156:156)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) @@ -17245,28 +18230,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (691:691:691) (767:767:767)) - (PORT ena (670:670:670) (742:742:742)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (691:691:691) (768:768:768)) - (PORT ena (627:627:627) (675:675:675)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (532:532:532) (588:588:588)) + (PORT ena (782:782:782) (860:860:860)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -17277,68 +18246,94 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (258:258:258)) - (PORT datab (897:897:897) (1046:1046:1046)) - (PORT datad (644:644:644) (749:749:749)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT datad (354:354:354) (412:412:412)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (682:682:682) (746:746:746)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (565:565:565) (645:645:645)) - (PORT datab (649:649:649) (751:751:751)) - (PORT datad (127:127:127) (156:156:156)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (463:463:463) (542:542:542)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) + (PORT clk (903:903:903) (908:908:908)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (622:622:622) (680:680:680)) + (PORT ena (797:797:797) (873:873:873)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (600:600:600)) + (PORT datab (513:513:513) (599:599:599)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (645:645:645) (735:735:735)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (807:807:807) (960:960:960)) + (PORT datab (361:361:361) (424:424:424)) + (PORT datad (958:958:958) (1134:1134:1134)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (350:350:350) (407:407:407)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (619:619:619) (666:666:666)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -17347,14 +18342,61 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (540:540:540) (606:606:606)) + (PORT ena (787:787:787) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (129:129:129) (180:180:180)) + (PORT datab (519:519:519) (612:612:612)) + (PORT datad (472:472:472) (553:553:553)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (638:638:638) (719:719:719)) + (PORT ena (629:629:629) (679:679:679)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (688:688:688) (764:764:764)) - (PORT ena (405:405:405) (422:422:422)) + (PORT clk (914:914:914) (922:922:922)) + (PORT asdata (828:828:828) (921:921:921)) + (PORT ena (408:408:408) (429:429:429)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -17368,9 +18410,9 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) (DELAY (ABSOLUTE - (PORT dataa (132:132:132) (184:184:184)) - (PORT datab (130:130:130) (163:163:163)) - (PORT datad (471:471:471) (549:549:549)) + (PORT dataa (366:366:366) (444:444:444)) + (PORT datab (115:115:115) (143:143:143)) + (PORT datad (302:302:302) (347:347:347)) (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -17380,12 +18422,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) (DELAY (ABSOLUTE (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (356:356:356) (383:383:383)) - (PORT ena (747:747:747) (810:810:810)) + (PORT asdata (691:691:691) (768:768:768)) + (PORT ena (631:631:631) (686:686:686)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -17396,29 +18438,60 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) (DELAY (ABSOLUTE (PORT clk (903:903:903) (908:908:908)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (778:778:778) (855:855:855)) + (PORT asdata (691:691:691) (768:768:768)) + (PORT ena (606:606:606) (646:646:646)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) (DELAY (ABSOLUTE - (PORT dataa (563:563:563) (644:644:644)) - (PORT datab (720:720:720) (850:850:850)) - (PORT datad (117:117:117) (153:153:153)) + (PORT dataa (357:357:357) (420:420:420)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datad (337:337:337) (394:394:394)) (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (894:894:894) (1025:1025:1025)) + (PORT ena (656:656:656) (724:724:724)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (477:477:477) (574:574:574)) + (PORT datab (693:693:693) (815:815:815)) + (PORT datad (335:335:335) (393:393:393)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -17430,10 +18503,10 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) (DELAY (ABSOLUTE - (PORT dataa (453:453:453) (524:524:524)) - (PORT datab (568:568:568) (676:676:676)) - (PORT datac (457:457:457) (544:544:544)) - (PORT datad (90:90:90) (106:106:106)) + (PORT dataa (350:350:350) (413:413:413)) + (PORT datab (459:459:459) (549:549:549)) + (PORT datac (323:323:323) (372:372:372)) + (PORT datad (92:92:92) (110:110:110)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -17441,13 +18514,980 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (454:454:454) (523:523:523)) + (PORT datab (580:580:580) (678:678:678)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (740:740:740)) + (PORT datab (761:761:761) (868:868:868)) + (PORT datac (522:522:522) (614:614:614)) + (PORT datad (767:767:767) (863:863:863)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1457:1457:1457) (1668:1668:1668)) + (PORT datab (105:105:105) (135:135:135)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) + (DELAY + (ABSOLUTE + (PORT datac (608:608:608) (706:706:706)) + (PORT datad (797:797:797) (918:918:918)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (409:409:409)) + (PORT datab (508:508:508) (590:590:590)) + (PORT datac (617:617:617) (715:715:715)) + (PORT datad (93:93:93) (113:113:113)) + (IOPATH dataa combout (181:181:181) (193:193:193)) + (IOPATH datab combout (182:182:182) (188:188:188)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (739:739:739)) + (PORT datac (494:494:494) (570:570:570)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (736:736:736)) + (PORT datab (512:512:512) (595:595:595)) + (PORT datac (602:602:602) (699:699:699)) + (PORT datad (792:792:792) (912:912:912)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (281:281:281)) + (PORT datac (303:303:303) (353:353:353)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (360:360:360) (391:391:391)) + (PORT ena (594:594:594) (642:642:642)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (360:360:360) (391:391:391)) + (PORT ena (665:665:665) (725:725:725)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (394:394:394)) + (PORT datab (517:517:517) (607:607:607)) + (PORT datad (116:116:116) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) (DELAY (ABSOLUTE (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (512:512:512) (563:563:563)) + (PORT asdata (681:681:681) (761:761:761)) + (PORT ena (754:754:754) (814:814:814)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (682:682:682) (761:761:761)) + (PORT ena (434:434:434) (466:466:466)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (133:133:133) (177:177:177)) + (PORT datab (591:591:591) (681:681:681)) + (PORT datad (187:187:187) (235:235:235)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (480:480:480) (524:524:524)) + (PORT ena (473:473:473) (498:498:498)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (480:480:480) (524:524:524)) + (PORT ena (503:503:503) (543:543:543)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (267:267:267)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datad (221:221:221) (260:260:260)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (751:751:751) (832:832:832)) + (PORT ena (434:434:434) (462:462:462)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (724:724:724) (856:856:856)) + (PORT datab (553:553:553) (652:652:652)) + (PORT datad (495:495:495) (575:575:575)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (785:785:785) (874:874:874)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (973:973:973)) + (PORT datab (851:851:851) (1009:1009:1009)) + (PORT datac (1145:1145:1145) (1307:1307:1307)) + (PORT datad (341:341:341) (397:397:397)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) + (DELAY + (ABSOLUTE + (PORT dataa (129:129:129) (159:159:159)) + (PORT datab (389:389:389) (477:477:477)) + (PORT datac (485:485:485) (561:561:561)) + (PORT datad (657:657:657) (748:748:748)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (582:582:582)) + (PORT datab (346:346:346) (406:406:406)) + (PORT datac (722:722:722) (847:847:847)) + (PORT datad (170:170:170) (201:201:201)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT datab (474:474:474) (565:565:565)) + (PORT datac (388:388:388) (477:477:477)) + (PORT datad (349:349:349) (407:407:407)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (478:478:478) (564:564:564)) + (PORT datab (775:775:775) (889:889:889)) + (PORT datac (109:109:109) (134:134:134)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (110:110:110) (135:135:135)) + (PORT datad (704:704:704) (806:806:806)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (777:777:777)) + (PORT datac (1159:1159:1159) (1351:1351:1351)) + (PORT datad (724:724:724) (874:874:874)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~10) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (419:419:419)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (282:282:282) (325:325:325)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1104:1104:1104) (1312:1312:1312)) + (PORT datab (818:818:818) (946:946:946)) + (PORT datac (598:598:598) (684:684:684)) + (PORT datad (892:892:892) (1058:1058:1058)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~18) + (DELAY + (ABSOLUTE + (PORT dataa (987:987:987) (1162:1162:1162)) + (PORT datab (904:904:904) (1080:1080:1080)) + (PORT datac (1763:1763:1763) (2032:2032:2032)) + (PORT datad (1082:1082:1082) (1285:1285:1285)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~38) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (950:950:950)) + (PORT datab (1113:1113:1113) (1288:1288:1288)) + (PORT datac (837:837:837) (972:972:972)) + (PORT datad (994:994:994) (1152:1152:1152)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~11) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (871:871:871) (1019:1019:1019)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~12) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (377:377:377)) + (PORT datab (330:330:330) (392:392:392)) + (PORT datac (333:333:333) (390:390:390)) + (PORT datad (174:174:174) (207:207:207)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) + (DELAY + (ABSOLUTE + (PORT dataa (126:126:126) (162:162:162)) + (PORT datab (363:363:363) (422:422:422)) + (PORT datac (549:549:549) (617:617:617)) + (PORT datad (325:325:325) (376:376:376)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) + (DELAY + (ABSOLUTE + (PORT dataa (501:501:501) (581:581:581)) + (PORT datab (354:354:354) (421:421:421)) + (PORT datac (986:986:986) (1128:1128:1128)) + (PORT datad (293:293:293) (336:336:336)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) + (DELAY + (ABSOLUTE + (PORT dataa (314:314:314) (369:369:369)) + (PORT datab (353:353:353) (421:421:421)) + (PORT datac (93:93:93) (117:117:117)) + (PORT datad (511:511:511) (595:595:595)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) + (DELAY + (ABSOLUTE + (PORT datac (296:296:296) (348:348:348)) + (PORT datad (594:594:594) (683:683:683)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1109:1109:1109) (1309:1309:1309)) + (PORT datab (793:793:793) (912:912:912)) + (PORT datad (755:755:755) (916:916:916)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (529:529:529) (626:626:626)) + (PORT datab (539:539:539) (638:638:638)) + (PORT datac (822:822:822) (942:942:942)) + (PORT datad (702:702:702) (816:816:816)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (140:140:140)) + (PORT datab (544:544:544) (630:630:630)) + (PORT datac (513:513:513) (603:603:603)) + (PORT datad (520:520:520) (614:614:614)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1030:1030:1030) (1169:1169:1169)) + (PORT datab (107:107:107) (138:138:138)) + (PORT datac (326:326:326) (382:382:382)) + (PORT datad (857:857:857) (975:975:975)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) + (DELAY + (ABSOLUTE + (PORT dataa (775:775:775) (899:899:899)) + (PORT datab (765:765:765) (935:935:935)) + (PORT datac (608:608:608) (695:695:695)) + (PORT datad (755:755:755) (921:921:921)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (150:150:150)) + (PORT datab (348:348:348) (416:416:416)) + (PORT datad (172:172:172) (204:204:204)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (688:688:688)) + (PORT datab (441:441:441) (509:509:509)) + (PORT datac (298:298:298) (350:350:350)) + (PORT datad (280:280:280) (323:323:323)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal73\~2) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (652:652:652)) + (PORT datab (479:479:479) (554:554:554)) + (PORT datac (590:590:590) (701:701:701)) + (PORT datad (698:698:698) (830:830:830)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (440:440:440)) + (PORT datab (514:514:514) (604:604:604)) + (PORT datac (839:839:839) (964:964:964)) + (PORT datad (639:639:639) (733:733:733)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (707:707:707)) + (PORT datab (185:185:185) (226:226:226)) + (PORT datac (295:295:295) (347:347:347)) + (PORT datad (571:571:571) (653:653:653)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) + (DELAY + (ABSOLUTE + (PORT datab (118:118:118) (148:148:148)) + (PORT datac (323:323:323) (377:377:377)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) + (DELAY + (ABSOLUTE + (PORT dataa (112:112:112) (147:147:147)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (464:464:464) (541:541:541)) + (PORT datad (318:318:318) (364:364:364)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (407:407:407)) + (PORT datab (858:858:858) (984:984:984)) + (PORT datac (530:530:530) (602:602:602)) + (PORT datad (755:755:755) (865:865:865)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) + (DELAY + (ABSOLUTE + (PORT dataa (464:464:464) (541:541:541)) + (PORT datab (290:290:290) (336:336:336)) + (PORT datac (434:434:434) (499:499:499)) + (PORT datad (451:451:451) (520:520:520)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) + (DELAY + (ABSOLUTE + (PORT dataa (149:149:149) (192:192:192)) + (PORT datab (994:994:994) (1134:1134:1134)) + (PORT datac (141:141:141) (181:181:181)) + (PORT datad (664:664:664) (763:763:763)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~40) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (1114:1114:1114)) + (PORT datab (469:469:469) (546:546:546)) + (PORT datac (471:471:471) (550:550:550)) + (PORT datad (1037:1037:1037) (1237:1237:1237)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (1113:1113:1113)) + (PORT datab (972:972:972) (1138:1138:1138)) + (PORT datac (471:471:471) (550:550:550)) + (PORT datad (1216:1216:1216) (1455:1455:1455)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (119:119:119) (154:154:154)) + (PORT datac (96:96:96) (121:121:121)) + (PORT datad (107:107:107) (126:126:126)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (372:372:372) (408:408:408)) + (PORT ena (782:782:782) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (372:372:372) (408:408:408)) + (PORT ena (797:797:797) (873:873:873)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (600:600:600)) + (PORT datab (518:518:518) (605:605:605)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (907:907:907)) + (PORT asdata (676:676:676) (752:752:752)) + (PORT ena (820:820:820) (910:910:910)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (907:907:907)) + (PORT asdata (677:677:677) (753:753:753)) + (PORT ena (778:778:778) (844:844:844)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (644:644:644)) + (PORT datab (540:540:540) (626:626:626)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (544:544:544) (600:600:600)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (804:804:804) (956:956:956)) + (PORT datab (353:353:353) (415:415:415)) + (PORT datad (951:951:951) (1124:1124:1124)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT asdata (989:989:989) (1104:1104:1104)) (PORT ena (408:408:408) (429:429:429)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -17457,61 +19497,14 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (505:505:505) (604:604:604)) - (PORT datab (669:669:669) (791:791:791)) - (PORT datad (488:488:488) (568:568:568)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (249:249:249)) - (PORT datab (466:466:466) (557:557:557)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (295:295:295) (341:341:341)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (452:452:452) (524:524:524)) - (PORT datab (476:476:476) (550:550:550)) - (PORT datac (455:455:455) (546:546:546)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT asdata (451:451:451) (491:491:491)) - (PORT ena (482:482:482) (509:509:509)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (1072:1072:1072) (1210:1210:1210)) + (PORT ena (619:619:619) (665:665:665)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -17522,12 +19515,137 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~61) (DELAY (ABSOLUTE - (PORT dataa (126:126:126) (160:160:160)) - (PORT datab (505:505:505) (574:574:574)) - (PORT datad (112:112:112) (133:133:133)) + (PORT dataa (338:338:338) (411:411:411)) + (PORT datab (268:268:268) (325:325:325)) + (PORT datad (340:340:340) (394:394:394)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (808:808:808) (899:899:899)) + (PORT ena (656:656:656) (724:724:724)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (581:581:581)) + (PORT datab (353:353:353) (417:417:417)) + (PORT datad (675:675:675) (791:791:791)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (787:787:787) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (472:472:472) (509:509:509)) + (PORT ena (619:619:619) (666:666:666)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (495:495:495) (583:583:583)) + (PORT datab (129:129:129) (176:176:176)) + (PORT datad (500:500:500) (586:586:586)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (541:541:541) (608:608:608)) + (PORT ena (606:606:606) (646:646:646)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (540:540:540) (606:606:606)) + (PORT ena (631:631:631) (686:686:686)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (420:420:420)) + (PORT datab (130:130:130) (177:177:177)) + (PORT datad (338:338:338) (395:395:395)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -17537,13 +19655,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~64) (DELAY (ABSOLUTE - (PORT dataa (127:127:127) (163:163:163)) - (PORT datac (116:116:116) (156:156:156)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (340:340:340) (399:399:399)) + (PORT datab (483:483:483) (574:574:574)) + (PORT datac (308:308:308) (356:356:356)) + (PORT datad (313:313:313) (364:364:364)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -17551,16 +19671,541 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~65) (DELAY (ABSOLUTE - (PORT dataa (611:611:611) (709:709:709)) - (PORT datab (442:442:442) (512:512:512)) - (PORT datac (104:104:104) (128:128:128)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (437:437:437) (504:504:504)) + (PORT datab (567:567:567) (664:664:664)) + (PORT datac (465:465:465) (554:554:554)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (637:637:637)) + (PORT datac (531:531:531) (630:630:630)) + (PORT datad (688:688:688) (798:798:798)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (613:613:613) (681:681:681)) + (PORT ena (599:599:599) (646:646:646)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (635:635:635)) + (PORT datab (549:549:549) (649:649:649)) + (PORT datac (700:700:700) (828:828:828)) + (PORT datad (608:608:608) (701:701:701)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (977:977:977)) + (PORT datab (311:311:311) (365:365:365)) + (PORT datad (300:300:300) (350:350:350)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (DELAY + (ABSOLUTE + (PORT datab (539:539:539) (628:628:628)) + (PORT datac (523:523:523) (613:613:613)) + (PORT datad (688:688:688) (798:798:798)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (611:611:611) (658:658:658)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) + (DELAY + (ABSOLUTE + (PORT datab (535:535:535) (624:624:624)) + (PORT datac (521:521:521) (610:610:610)) + (PORT datad (685:685:685) (795:795:795)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (130:130:130) (177:177:177)) + (PORT datad (297:297:297) (342:342:342)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (611:611:611) (658:658:658)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (907:907:907)) + (PORT asdata (545:545:545) (615:615:615)) + (PORT ena (820:820:820) (910:910:910)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (907:907:907)) + (PORT asdata (545:545:545) (615:615:615)) + (PORT ena (778:778:778) (844:844:844)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (641:641:641)) + (PORT datab (535:535:535) (621:621:621)) + (PORT datad (116:116:116) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (469:469:469) (514:514:514)) + (PORT ena (782:782:782) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (469:469:469) (514:514:514)) + (PORT ena (797:797:797) (873:873:873)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (600:600:600)) + (PORT datab (512:512:512) (598:598:598)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (653:653:653) (724:724:724)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (955:955:955)) + (PORT datab (350:350:350) (412:412:412)) + (PORT datad (948:948:948) (1121:1121:1121)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (652:652:652) (723:723:723)) + (PORT ena (606:606:606) (646:646:646)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (649:649:649) (720:720:720)) + (PORT ena (631:631:631) (686:686:686)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (421:421:421)) + (PORT datab (131:131:131) (180:180:180)) + (PORT datad (335:335:335) (392:392:392)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (358:358:358) (392:392:392)) + (PORT ena (619:619:619) (666:666:666)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (787:787:787) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (493:493:493) (581:581:581)) + (PORT datab (522:522:522) (616:616:616)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT asdata (663:663:663) (734:734:734)) + (PORT ena (408:408:408) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (655:655:655) (727:727:727)) + (PORT ena (619:619:619) (665:665:665)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (300:300:300)) + (PORT datab (269:269:269) (326:326:326)) + (PORT datad (339:339:339) (393:393:393)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (657:657:657) (729:729:729)) + (PORT ena (655:655:655) (718:718:718)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (637:637:637)) + (PORT datab (716:716:716) (838:838:838)) + (PORT datad (852:852:852) (996:996:996)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (174:174:174) (210:210:210)) + (PORT datab (347:347:347) (409:409:409)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (217:217:217)) + (PORT datab (334:334:334) (395:395:395)) + (PORT datac (336:336:336) (395:395:395)) + (PORT datad (329:329:329) (384:384:384)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (443:443:443) (518:518:518)) + (PORT datab (214:214:214) (257:257:257)) + (PORT datac (748:748:748) (857:857:857)) + (PORT datad (309:309:309) (363:363:363)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (458:458:458) (505:505:505)) + (PORT ena (599:599:599) (646:646:646)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (377:377:377)) + (PORT datab (700:700:700) (817:817:817)) + (PORT datad (298:298:298) (343:343:343)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (129:129:129) (179:179:179)) + (PORT datab (309:309:309) (364:364:364)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -17570,10 +20215,122 @@ (INSTANCE z80_\|address_latch_\|abusz\[8\]) (DELAY (ABSOLUTE - (PORT dataa (377:377:377) (449:449:449)) - (PORT datac (424:424:424) (492:492:492)) + (PORT dataa (194:194:194) (233:233:233)) + (PORT datac (487:487:487) (571:571:571)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (400:400:400)) + (PORT datab (113:113:113) (146:146:146)) + (PORT datac (95:95:95) (120:120:120)) + (PORT datad (313:313:313) (358:358:358)) (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (126:126:126) (160:160:160)) + (PORT datab (383:383:383) (447:447:447)) + (PORT datac (658:658:658) (761:761:761)) + (PORT datad (1002:1002:1002) (1140:1140:1140)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (449:449:449) (516:516:516)) + (PORT datab (614:614:614) (723:723:723)) + (PORT datac (565:565:565) (664:664:664)) + (PORT datad (462:462:462) (517:517:517)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (499:499:499) (582:582:582)) + (PORT datab (487:487:487) (569:569:569)) + (PORT datac (174:174:174) (201:201:201)) + (PORT datad (469:469:469) (543:543:543)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (262:262:262)) + (PORT datab (808:808:808) (941:941:941)) + (PORT datac (573:573:573) (682:682:682)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (176:176:176) (214:214:214)) + (PORT datab (346:346:346) (409:409:409)) + (PORT datac (281:281:281) (327:327:327)) + (PORT datad (336:336:336) (390:390:390)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (756:756:756)) + (PORT datab (675:675:675) (783:783:783)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (451:451:451) (519:519:519)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -17585,7 +20342,604 @@ (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) (PORT clrn (920:920:920) (904:904:904)) - (PORT ena (1159:1159:1159) (1318:1318:1318)) + (PORT ena (953:953:953) (1066:1066:1066)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (640:640:640) (702:702:702)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (470:470:470) (511:511:511)) + (PORT ena (754:754:754) (814:814:814)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (471:471:471) (512:512:512)) + (PORT ena (434:434:434) (466:466:466)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (140:140:140) (186:186:186)) + (PORT datab (588:588:588) (678:678:678)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (653:653:653) (730:730:730)) + (PORT ena (503:503:503) (543:543:543)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (653:653:653) (731:731:731)) + (PORT ena (473:473:473) (498:498:498)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (269:269:269)) + (PORT datab (236:236:236) (282:282:282)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (324:324:324) (382:382:382)) + (PORT datac (712:712:712) (815:815:815)) + (PORT datad (625:625:625) (714:714:714)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (345:345:345)) + (PORT datab (619:619:619) (718:718:718)) + (PORT datac (578:578:578) (658:658:658)) + (PORT datad (445:445:445) (514:514:514)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (440:440:440) (508:508:508)) + (PORT datab (199:199:199) (240:240:240)) + (PORT datac (570:570:570) (651:651:651)) + (PORT datad (593:593:593) (675:675:675)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (407:407:407) (424:424:424)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (411:411:411)) + (PORT datab (723:723:723) (830:830:830)) + (PORT datac (351:351:351) (427:427:427)) + (PORT datad (630:630:630) (719:719:719)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (497:497:497) (576:576:576)) + (PORT datab (469:469:469) (549:549:549)) + (PORT datac (607:607:607) (719:719:719)) + (PORT datad (450:450:450) (522:522:522)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (475:475:475) (551:551:551)) + (PORT datab (315:315:315) (373:373:373)) + (PORT datac (427:427:427) (490:490:490)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (497:497:497) (576:576:576)) + (PORT datab (483:483:483) (564:564:564)) + (PORT datac (432:432:432) (496:496:496)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (497:497:497) (574:574:574)) + (PORT datab (477:477:477) (548:548:548)) + (PORT datac (476:476:476) (559:559:559)) + (PORT datad (572:572:572) (659:659:659)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT asdata (926:926:926) (1039:1039:1039)) + (PORT ena (495:495:495) (537:537:537)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (564:564:564) (658:658:658)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (435:435:435) (462:462:462)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (423:423:423)) + (PORT datab (127:127:127) (161:161:161)) + (PORT datad (288:288:288) (341:341:341)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (915:915:915) (1026:1026:1026)) + (PORT ena (603:603:603) (650:650:650)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT asdata (927:927:927) (1039:1039:1039)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (911:911:911) (1021:1021:1021)) + (PORT ena (666:666:666) (729:729:729)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (457:457:457)) + (PORT datab (372:372:372) (441:441:441)) + (PORT datad (348:348:348) (405:405:405)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (265:265:265)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (769:769:769) (855:855:855)) + (PORT ena (594:594:594) (642:642:642)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (770:770:770) (856:856:856)) + (PORT ena (665:665:665) (725:725:725)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (390:390:390)) + (PORT datab (515:515:515) (605:605:605)) + (PORT datad (116:116:116) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (319:319:319) (367:367:367)) + (PORT datab (427:427:427) (491:491:491)) + (PORT datac (350:350:350) (414:414:414)) + (PORT datad (453:453:453) (526:526:526)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (431:431:431)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datad (343:343:343) (401:401:401)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (468:468:468) (540:540:540)) + (PORT datab (182:182:182) (226:226:226)) + (PORT datac (625:625:625) (730:730:730)) + (PORT datad (375:375:375) (439:439:439)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (346:346:346) (376:376:376)) + (PORT ena (650:650:650) (698:698:698)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (810:810:810) (945:945:945)) + (PORT datab (424:424:424) (489:489:489)) + (PORT datad (356:356:356) (411:411:411)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (180:180:180)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datad (327:327:327) (383:383:383)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) + (DELAY + (ABSOLUTE + (PORT datab (379:379:379) (464:464:464)) + (PORT datad (424:424:424) (487:487:487)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (115:115:115) (143:143:143)) + (PORT datac (669:669:669) (777:777:777)) + (PORT datad (115:115:115) (138:138:138)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (681:681:681)) + (PORT datad (335:335:335) (394:394:394)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (928:928:928) (910:910:910)) + (PORT ena (1097:1097:1097) (1218:1218:1218)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -17600,13 +20954,13 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) (DELAY (ABSOLUTE - (PORT dataa (225:225:225) (293:293:293)) - (PORT datab (152:152:152) (204:204:204)) - (PORT datac (720:720:720) (824:824:824)) - (PORT datad (100:100:100) (121:121:121)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (668:668:668) (761:761:761)) + (PORT datab (492:492:492) (579:579:579)) + (PORT datac (199:199:199) (252:252:252)) + (PORT datad (499:499:499) (590:590:590)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -17616,8 +20970,8 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) (DELAY (ABSOLUTE - (PORT datac (136:136:136) (185:185:185)) - (PORT datad (166:166:166) (195:195:195)) + (PORT datac (206:206:206) (264:264:264)) + (PORT datad (100:100:100) (122:122:122)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -17628,13 +20982,13 @@ (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~3) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (389:389:389) (459:459:459)) - (PORT datac (438:438:438) (508:508:508)) - (PORT datad (303:303:303) (347:347:347)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT dataa (853:853:853) (1002:1002:1002)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (233:233:233) (288:288:288)) + (PORT datad (164:164:164) (194:194:194)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -17644,19 +20998,9 @@ (INSTANCE z80_\|address_latch_\|abusz\[9\]) (DELAY (ABSOLUTE - (PORT datab (185:185:185) (222:222:222)) - (PORT datac (481:481:481) (555:555:555)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[9\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (286:286:286) (329:329:329)) + (PORT datac (482:482:482) (565:565:565)) + (PORT datad (162:162:162) (189:189:189)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -17666,10 +21010,10 @@ (INSTANCE z80_\|address_latch_\|Q\[9\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) + (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) (PORT clrn (920:920:920) (904:904:904)) - (PORT ena (1125:1125:1125) (1271:1271:1271)) + (PORT ena (953:953:953) (1066:1066:1066)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -17679,30 +21023,14 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (144:144:144) (201:201:201)) - (PORT datab (154:154:154) (211:211:211)) - (PORT datac (729:729:729) (840:840:840)) - (PORT datad (166:166:166) (195:195:195)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (166:166:166) (174:174:174)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (612:612:612) (684:684:684)) - (PORT ena (753:753:753) (845:845:845)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (472:472:472) (512:512:512)) + (PORT ena (619:619:619) (673:673:673)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -17711,45 +21039,14 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (612:612:612) (684:684:684)) - (PORT ena (759:759:759) (842:842:842)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (505:505:505) (617:617:617)) - (PORT datab (516:516:516) (623:623:623)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (1078:1078:1078) (1235:1235:1235)) - (PORT ena (405:405:405) (422:422:422)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (736:736:736) (809:809:809)) + (PORT ena (655:655:655) (718:718:718)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -17760,69 +21057,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~35) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~44) (DELAY (ABSOLUTE - (PORT dataa (434:434:434) (502:502:502)) - (PORT datab (651:651:651) (753:753:753)) - (PORT datad (130:130:130) (159:159:159)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (806:806:806) (926:926:926)) - (PORT ena (582:582:582) (618:618:618)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (456:456:456) (544:544:544)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (248:248:248)) - (PORT datab (481:481:481) (561:561:561)) - (PORT datad (183:183:183) (228:228:228)) + (PORT dataa (541:541:541) (638:638:638)) + (PORT datab (713:713:713) (834:834:834)) + (PORT datad (489:489:489) (576:576:576)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -17830,71 +21070,14 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (573:573:573) (673:673:673)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (627:627:627) (675:675:675)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (1123:1123:1123) (1280:1280:1280)) - (PORT ena (670:670:670) (742:742:742)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (297:297:297) (365:365:365)) - (PORT datab (895:895:895) (1044:1044:1044)) - (PORT datad (643:643:643) (748:748:748)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) + (PORT clk (903:903:903) (908:908:908)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (776:776:776) (851:851:851)) + (PORT ena (787:787:787) (866:866:866)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -17908,9 +21091,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (805:805:805) (926:926:926)) - (PORT ena (673:673:673) (745:745:745)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (634:634:634) (701:701:701)) + (PORT ena (619:619:619) (666:666:666)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -17921,43 +21104,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~36) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~45) (DELAY (ABSOLUTE - (PORT dataa (592:592:592) (685:685:685)) - (PORT datab (371:371:371) (448:448:448)) - (PORT datad (462:462:462) (533:533:533)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (131:131:131) (182:182:182)) + (PORT datab (520:520:520) (614:614:614)) + (PORT datad (470:470:470) (552:552:552)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (333:333:333) (391:391:391)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (317:317:317) (374:374:374)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (1225:1225:1225) (1404:1404:1404)) - (PORT ena (506:506:506) (537:537:537)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (658:658:658) (736:736:736)) + (PORT ena (606:606:606) (646:646:646)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -17968,12 +21135,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (1227:1227:1227) (1407:1407:1407)) - (PORT ena (515:515:515) (556:556:556)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (658:658:658) (736:736:736)) + (PORT ena (631:631:631) (686:686:686)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -17984,12 +21151,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~31) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~42) (DELAY (ABSOLUTE - (PORT dataa (257:257:257) (311:311:311)) - (PORT datab (132:132:132) (181:181:181)) - (PORT datad (245:245:245) (290:290:290)) + (PORT dataa (358:358:358) (421:421:421)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datad (332:332:332) (389:389:389)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -17999,11 +21166,11 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (1237:1237:1237) (1417:1417:1417)) + (PORT clk (914:914:914) (922:922:922)) + (PORT asdata (649:649:649) (717:717:717)) (PORT ena (408:408:408) (429:429:429)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -18013,61 +21180,14 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (506:506:506) (605:605:605)) - (PORT datab (669:669:669) (791:791:791)) - (PORT datad (486:486:486) (565:565:565)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (440:440:440) (531:531:531)) - (PORT datab (297:297:297) (349:349:349)) - (PORT datac (292:292:292) (336:336:336)) - (PORT datad (462:462:462) (537:537:537)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (488:488:488) (579:579:579)) - (PORT datab (202:202:202) (239:239:239)) - (PORT datac (489:489:489) (580:580:580)) - (PORT datad (730:730:730) (840:840:840)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT asdata (284:284:284) (306:306:306)) - (PORT ena (482:482:482) (509:509:509)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (736:736:736) (808:808:808)) + (PORT ena (619:619:619) (665:665:665)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -18078,13 +21198,211 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~7) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~43) (DELAY (ABSOLUTE - (PORT dataa (1080:1080:1080) (1264:1264:1264)) - (PORT datab (125:125:125) (156:156:156)) - (PORT datad (113:113:113) (135:135:135)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (228:228:228) (295:295:295)) + (PORT datab (269:269:269) (326:326:326)) + (PORT datad (338:338:338) (391:391:391)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (407:407:407)) + (PORT datab (458:458:458) (530:530:530)) + (PORT datac (298:298:298) (341:341:341)) + (PORT datad (298:298:298) (343:343:343)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (907:907:907)) + (PORT asdata (756:756:756) (831:831:831)) + (PORT ena (820:820:820) (910:910:910)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (575:575:575) (652:652:652)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (778:778:778) (844:844:844)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (643:643:643)) + (PORT datab (537:537:537) (623:623:623)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (649:649:649) (713:713:713)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (804:804:804) (956:956:956)) + (PORT datab (352:352:352) (414:414:414)) + (PORT datad (950:950:950) (1123:1123:1123)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (367:367:367) (407:407:407)) + (PORT ena (797:797:797) (873:873:873)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (367:367:367) (406:406:406)) + (PORT ena (782:782:782) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (601:601:601)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datad (497:497:497) (577:577:577)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (411:411:411)) + (PORT datab (358:358:358) (425:425:425)) + (PORT datac (487:487:487) (558:558:558)) + (PORT datad (164:164:164) (193:193:193)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (293:293:293) (336:336:336)) + (PORT datab (206:206:206) (249:249:249)) + (PORT datac (745:745:745) (856:856:856)) + (PORT datad (303:303:303) (349:349:349)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (409:409:409)) + (PORT datab (332:332:332) (390:390:390)) + (PORT datad (296:296:296) (340:340:340)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -18096,9 +21414,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) + (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (434:434:434) (466:466:466)) + (PORT ena (611:611:611) (658:658:658)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -18109,29 +21427,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~8) + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~11) (DELAY (ABSOLUTE - (PORT dataa (126:126:126) (160:160:160)) (PORT datab (103:103:103) (132:132:132)) - (PORT datad (185:185:185) (232:232:232)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT datac (218:218:218) (276:276:276)) + (PORT datad (313:313:313) (358:358:358)) (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~9) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) (DELAY (ABSOLUTE - (PORT dataa (615:615:615) (713:713:713)) - (PORT datab (283:283:283) (325:325:325)) - (PORT datac (108:108:108) (132:132:132)) - (PORT datad (89:89:89) (107:107:107)) + (PORT dataa (223:223:223) (292:292:292)) + (PORT datab (491:491:491) (578:578:578)) + (PORT datac (217:217:217) (279:279:279)) + (PORT datad (99:99:99) (121:121:121)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (850:850:850) (998:998:998)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (235:235:235) (289:289:289)) + (PORT datad (184:184:184) (214:214:214)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -18142,19 +21476,9 @@ (INSTANCE z80_\|address_latch_\|abusz\[10\]) (DELAY (ABSOLUTE - (PORT datac (105:105:105) (128:128:128)) - (PORT datad (479:479:479) (549:549:549)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[10\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (276:276:276) (318:318:318)) + (PORT datac (489:489:489) (573:573:573)) + (PORT datad (170:170:170) (199:199:199)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -18164,10 +21488,10 @@ (INSTANCE z80_\|address_latch_\|Q\[10\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) + (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) (PORT clrn (920:920:920) (904:904:904)) - (PORT ena (1125:1125:1125) (1271:1271:1271)) + (PORT ena (953:953:953) (1066:1066:1066)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -18182,2797 +21506,25 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) (DELAY (ABSOLUTE - (PORT dataa (148:148:148) (206:206:206)) - (PORT datab (149:149:149) (204:204:204)) - (PORT datac (732:732:732) (843:843:843)) - (PORT datad (167:167:167) (196:196:196)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[11\]) - (DELAY - (ABSOLUTE - (PORT datab (328:328:328) (387:387:387)) - (PORT datad (499:499:499) (574:574:574)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (904:904:904)) - (PORT ena (1125:1125:1125) (1271:1271:1271)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datac (300:300:300) (361:361:361)) - (IOPATH dataa combout (195:195:195) (203:203:203)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (747:747:747)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT asdata (389:389:389) (432:432:432)) - (PORT ena (480:480:480) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datab (210:210:210) (253:253:253)) - (PORT datad (206:206:206) (244:244:244)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (134:134:134) (186:186:186)) - (PORT datac (465:465:465) (547:547:547)) - (PORT datad (340:340:340) (396:396:396)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (293:293:293) (339:339:339)) - (PORT datab (461:461:461) (536:536:536)) - (PORT datac (372:372:372) (442:442:442)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (325:325:325) (389:389:389)) - (PORT datab (469:469:469) (565:565:565)) - (PORT datac (209:209:209) (254:254:254)) - (PORT datad (731:731:731) (840:840:840)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (484:484:484) (570:570:570)) - (PORT datab (118:118:118) (152:152:152)) - (PORT datac (628:628:628) (734:734:734)) - (PORT datad (329:329:329) (379:379:379)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (652:652:652)) - (PORT datab (1201:1201:1201) (1376:1376:1376)) - (PORT datac (377:377:377) (439:439:439)) - (PORT datad (981:981:981) (1147:1147:1147)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT datab (530:530:530) (628:628:628)) - (PORT datac (626:626:626) (726:726:726)) - (PORT datad (375:375:375) (446:446:446)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT datab (347:347:347) (419:419:419)) - (PORT datac (345:345:345) (409:409:409)) - (PORT datad (344:344:344) (397:397:397)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (419:419:419)) - (PORT datab (344:344:344) (416:416:416)) - (PORT datac (101:101:101) (122:122:122)) - (PORT datad (301:301:301) (348:348:348)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (719:719:719)) - (PORT datab (730:730:730) (864:864:864)) - (PORT datac (331:331:331) (378:378:378)) - (PORT datad (608:608:608) (689:689:689)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1163:1163:1163) (1387:1387:1387)) - (PORT datab (701:701:701) (819:819:819)) - (PORT datac (545:545:545) (643:643:643)) - (PORT datad (828:828:828) (966:966:966)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) - (DELAY - (ABSOLUTE - (PORT dataa (565:565:565) (657:657:657)) - (PORT datab (893:893:893) (1051:1051:1051)) - (PORT datac (617:617:617) (699:699:699)) - (PORT datad (358:358:358) (422:422:422)) + (PORT dataa (221:221:221) (289:289:289)) + (PORT datab (490:490:490) (576:576:576)) + (PORT datac (217:217:217) (278:278:278)) + (PORT datad (100:100:100) (121:121:121)) (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1416:1416:1416) (1651:1651:1651)) - (PORT datab (887:887:887) (1038:1038:1038)) - (PORT datac (470:470:470) (547:547:547)) - (PORT datad (101:101:101) (124:124:124)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (195:195:195) (235:235:235)) - (PORT datab (457:457:457) (533:533:533)) - (PORT datac (446:446:446) (511:511:511)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (385:385:385)) - (PORT datab (672:672:672) (771:771:771)) - (PORT datac (289:289:289) (323:323:323)) - (PORT datad (323:323:323) (372:372:372)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (314:314:314) (368:368:368)) - (PORT datab (621:621:621) (741:741:741)) - (PORT datac (290:290:290) (338:338:338)) - (PORT datad (504:504:504) (590:590:590)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (143:143:143) (190:190:190)) - (PORT datac (88:88:88) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) - (DELAY - (ABSOLUTE - (PORT dataa (145:145:145) (193:193:193)) - (PORT datac (605:605:605) (725:725:725)) - (PORT datad (499:499:499) (585:585:585)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (420:420:420) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT datab (533:533:533) (632:632:632)) - (PORT datac (191:191:191) (233:233:233)) - (PORT datad (371:371:371) (441:441:441)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (422:422:422)) - (PORT datab (627:627:627) (749:749:749)) - (PORT datac (315:315:315) (362:362:362)) - (PORT datad (201:201:201) (247:247:247)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (146:146:146) (194:194:194)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (297:297:297) (342:342:342)) - (PORT datad (498:498:498) (583:583:583)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (420:420:420) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (920:920:920)) - (PORT datab (843:843:843) (982:982:982)) - (PORT datac (1035:1035:1035) (1198:1198:1198)) - (PORT datad (212:212:212) (252:252:252)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~20) - (DELAY - (ABSOLUTE - (PORT dataa (800:800:800) (925:925:925)) - (PORT datab (897:897:897) (1061:1061:1061)) - (PORT datac (580:580:580) (670:670:670)) - (PORT datad (732:732:732) (861:861:861)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (551:551:551)) - (PORT datab (527:527:527) (606:606:606)) - (PORT datac (462:462:462) (539:539:539)) - (PORT datad (351:351:351) (409:409:409)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (301:301:301)) - (PORT datab (660:660:660) (765:765:765)) - (PORT datac (501:501:501) (611:611:611)) - (PORT datad (786:786:786) (923:923:923)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal61\~2) - (DELAY - (ABSOLUTE - (PORT dataa (997:997:997) (1156:1156:1156)) - (PORT datab (779:779:779) (892:892:892)) - (PORT datac (909:909:909) (1065:1065:1065)) - (PORT datad (859:859:859) (1007:1007:1007)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) - (DELAY - (ABSOLUTE - (PORT datab (1021:1021:1021) (1197:1197:1197)) - (PORT datac (945:945:945) (1094:1094:1094)) - (PORT datad (520:520:520) (608:608:608)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1015:1015:1015) (1160:1160:1160)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (471:471:471) (535:535:535)) - (PORT datad (427:427:427) (493:493:493)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~21) - (DELAY - (ABSOLUTE - (PORT dataa (752:752:752) (888:888:888)) - (PORT datab (980:980:980) (1147:1147:1147)) - (PORT datac (812:812:812) (935:935:935)) - (PORT datad (102:102:102) (118:118:118)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) - (DELAY - (ABSOLUTE - (PORT dataa (849:849:849) (987:987:987)) - (PORT datab (517:517:517) (606:606:606)) - (PORT datac (100:100:100) (121:121:121)) - (PORT datad (108:108:108) (127:127:127)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) - (DELAY - (ABSOLUTE - (PORT dataa (114:114:114) (145:145:145)) - (PORT datab (109:109:109) (139:139:139)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (97:97:97) (117:117:117)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~22) - (DELAY - (ABSOLUTE - (PORT dataa (971:971:971) (1110:1110:1110)) - (PORT datab (448:448:448) (525:525:525)) - (PORT datac (731:731:731) (858:858:858)) - (PORT datad (1411:1411:1411) (1636:1636:1636)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) - (DELAY - (ABSOLUTE - (PORT dataa (314:314:314) (372:372:372)) - (PORT datab (132:132:132) (161:161:161)) - (PORT datac (120:120:120) (143:143:143)) - (PORT datad (490:490:490) (589:589:589)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (559:559:559) (641:641:641)) - (PORT datab (892:892:892) (1024:1024:1024)) - (PORT datac (662:662:662) (770:770:770)) - (PORT datad (960:960:960) (1087:1087:1087)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal71\~2) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (555:555:555)) - (PORT datab (511:511:511) (611:611:611)) - (PORT datac (117:117:117) (139:139:139)) - (PORT datad (487:487:487) (585:585:585)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (144:144:144)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datac (106:106:106) (130:130:130)) - (PORT datad (96:96:96) (116:116:116)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) - (DELAY - (ABSOLUTE - (PORT dataa (663:663:663) (770:770:770)) - (PORT datab (121:121:121) (151:151:151)) - (PORT datac (1168:1168:1168) (1352:1352:1352)) - (PORT datad (796:796:796) (914:914:914)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (431:431:431)) - (PORT datab (826:826:826) (963:963:963)) - (PORT datac (824:824:824) (944:944:944)) - (PORT datad (340:340:340) (393:393:393)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla25M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (516:516:516)) - (PORT datab (828:828:828) (965:965:965)) - (PORT datac (869:869:869) (992:992:992)) - (PORT datad (821:821:821) (957:957:957)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (111:111:111) (142:142:142)) - (PORT datac (449:449:449) (518:518:518)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) - (DELAY - (ABSOLUTE - (PORT dataa (117:117:117) (148:148:148)) - (PORT datab (116:116:116) (145:145:145)) - (PORT datac (586:586:586) (666:666:666)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal72\~2) - (DELAY - (ABSOLUTE - (PORT dataa (768:768:768) (908:908:908)) - (PORT datab (1306:1306:1306) (1524:1524:1524)) - (PORT datac (614:614:614) (714:714:714)) - (PORT datad (453:453:453) (513:513:513)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal73\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1306:1306:1306)) - (PORT datab (619:619:619) (727:727:727)) - (PORT datac (752:752:752) (871:871:871)) - (PORT datad (463:463:463) (523:523:523)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (552:552:552) (647:647:647)) - (PORT datab (549:549:549) (651:651:651)) - (PORT datac (1000:1000:1000) (1140:1140:1140)) - (PORT datad (819:819:819) (951:951:951)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (573:573:573) (657:657:657)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (329:329:329) (388:388:388)) - (PORT datad (318:318:318) (372:372:372)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (838:838:838) (980:980:980)) - (PORT datab (1112:1112:1112) (1276:1276:1276)) - (PORT datac (715:715:715) (835:835:835)) - (PORT datad (526:526:526) (615:615:615)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) - (DELAY - (ABSOLUTE - (PORT datab (467:467:467) (539:539:539)) - (PORT datac (445:445:445) (513:513:513)) - (PORT datad (444:444:444) (508:508:508)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1417:1417:1417) (1652:1652:1652)) - (PORT datac (871:871:871) (1016:1016:1016)) - (PORT datad (878:878:878) (1033:1033:1033)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (135:135:135) (172:172:172)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (644:644:644) (743:743:743)) - (PORT datad (102:102:102) (125:125:125)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (454:454:454) (539:539:539)) - (PORT datab (337:337:337) (399:399:399)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (470:470:470) (559:559:559)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~15) - (DELAY - (ABSOLUTE - (PORT dataa (509:509:509) (588:588:588)) - (PORT datac (457:457:457) (527:527:527)) - (PORT datad (352:352:352) (408:408:408)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~16) - (DELAY - (ABSOLUTE - (PORT dataa (513:513:513) (593:593:593)) - (PORT datab (187:187:187) (226:226:226)) - (PORT datac (320:320:320) (372:372:372)) - (PORT datad (175:175:175) (203:203:203)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) - (DELAY - (ABSOLUTE - (PORT datac (486:486:486) (564:564:564)) - (PORT datad (448:448:448) (512:512:512)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (325:325:325) (384:384:384)) - (PORT datab (609:609:609) (696:696:696)) - (PORT datac (403:403:403) (461:461:461)) - (PORT datad (333:333:333) (388:388:388)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (565:565:565)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1286:1286:1286)) - (PORT datab (121:121:121) (151:151:151)) - (PORT datac (978:978:978) (1128:1128:1128)) - (PORT datad (846:846:846) (969:969:969)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (738:738:738)) - (PORT datab (894:894:894) (1056:1056:1056)) - (PORT datac (1399:1399:1399) (1627:1627:1627)) - (PORT datad (100:100:100) (122:122:122)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (652:652:652)) - (PORT datab (739:739:739) (866:866:866)) - (PORT datac (485:485:485) (560:560:560)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (397:397:397)) - (PORT datab (1270:1270:1270) (1476:1476:1476)) - (PORT datac (1157:1157:1157) (1345:1345:1345)) - (PORT datad (635:635:635) (733:733:733)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (325:325:325) (378:378:378)) - (PORT datab (324:324:324) (384:384:384)) - (PORT datac (292:292:292) (335:335:335)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) - (DELAY - (ABSOLUTE - (PORT dataa (563:563:563) (664:664:664)) - (PORT datab (1124:1124:1124) (1307:1307:1307)) - (PORT datac (436:436:436) (501:501:501)) - (PORT datad (1392:1392:1392) (1610:1610:1610)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (853:853:853) (1001:1001:1001)) - (PORT datab (524:524:524) (626:626:626)) - (PORT datac (338:338:338) (398:398:398)) - (PORT datad (302:302:302) (342:342:342)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (494:494:494) (583:583:583)) - (PORT datab (115:115:115) (142:142:142)) - (PORT datac (359:359:359) (422:422:422)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (409:409:409)) - (PORT datab (644:644:644) (748:748:748)) - (PORT datac (354:354:354) (418:418:418)) - (PORT datad (157:157:157) (184:184:184)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (416:416:416)) - (PORT datab (464:464:464) (557:557:557)) - (PORT datac (613:613:613) (698:698:698)) - (PORT datad (329:329:329) (376:376:376)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (390:390:390)) - (PORT datab (347:347:347) (398:398:398)) - (PORT datac (523:523:523) (629:629:629)) - (PORT datad (452:452:452) (514:514:514)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (839:839:839) (981:981:981)) - (PORT datab (577:577:577) (656:656:656)) - (PORT datac (716:716:716) (836:836:836)) - (PORT datad (524:524:524) (612:612:612)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~19) - (DELAY - (ABSOLUTE - (PORT dataa (806:806:806) (917:917:917)) - (PORT datab (635:635:635) (733:733:733)) - (PORT datac (669:669:669) (792:792:792)) - (PORT datad (632:632:632) (721:721:721)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (384:384:384)) - (PORT datab (578:578:578) (678:678:678)) - (PORT datac (408:408:408) (468:468:468)) - (PORT datad (331:331:331) (381:381:381)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (152:152:152)) - (PORT datab (581:581:581) (678:678:678)) - (PORT datac (463:463:463) (533:533:533)) - (PORT datad (324:324:324) (374:374:374)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (315:315:315) (373:373:373)) - (PORT datab (117:117:117) (152:152:152)) - (PORT datac (447:447:447) (523:523:523)) - (PORT datad (800:800:800) (932:932:932)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~9) - (DELAY - (ABSOLUTE - (PORT dataa (439:439:439) (533:533:533)) - (PORT datab (452:452:452) (524:524:524)) - (PORT datac (445:445:445) (535:535:535)) - (PORT datad (431:431:431) (511:511:511)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~10) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) - (DELAY - (ABSOLUTE - (PORT clk (896:896:896) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) - (DELAY - (ABSOLUTE - (PORT dataa (688:688:688) (789:789:789)) - (PORT datab (382:382:382) (457:457:457)) - (PORT datac (505:505:505) (595:595:595)) - (PORT datad (585:585:585) (669:669:669)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (389:389:389)) - (PORT datab (347:347:347) (397:397:397)) - (PORT datac (522:522:522) (629:629:629)) - (PORT datad (200:200:200) (232:232:232)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) - (DELAY - (ABSOLUTE - (PORT dataa (546:546:546) (639:639:639)) - (PORT datab (1012:1012:1012) (1158:1158:1158)) - (PORT datac (715:715:715) (835:835:835)) - (PORT datad (582:582:582) (657:657:657)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1121:1121:1121) (1298:1298:1298)) - (PORT datab (1374:1374:1374) (1594:1594:1594)) - (PORT datac (763:763:763) (873:873:873)) - (PORT datad (903:903:903) (1066:1066:1066)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) - (DELAY - (ABSOLUTE - (PORT dataa (836:836:836) (977:977:977)) - (PORT datab (196:196:196) (231:231:231)) - (PORT datac (714:714:714) (833:833:833)) - (PORT datad (489:489:489) (565:565:565)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) - (DELAY - (ABSOLUTE - (PORT dataa (679:679:679) (778:778:778)) - (PORT datab (174:174:174) (213:213:213)) - (PORT datac (584:584:584) (667:667:667)) - (PORT datad (171:171:171) (202:202:202)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (343:343:343) (403:403:403)) - (PORT datac (87:87:87) (109:109:109)) - (PORT datad (335:335:335) (382:382:382)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~18) - (DELAY - (ABSOLUTE - (PORT dataa (456:456:456) (533:533:533)) - (PORT datab (629:629:629) (726:726:726)) - (PORT datac (466:466:466) (540:540:540)) - (PORT datad (191:191:191) (239:239:239)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) - (DELAY - (ABSOLUTE - (PORT dataa (1417:1417:1417) (1651:1651:1651)) - (PORT datab (116:116:116) (145:145:145)) - (PORT datac (775:775:775) (886:886:886)) - (PORT datad (1053:1053:1053) (1215:1215:1215)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (303:303:303)) - (PORT datab (240:240:240) (302:302:302)) - (PORT datac (469:469:469) (547:547:547)) - (PORT datad (356:356:356) (422:422:422)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH datab combout (196:196:196) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (285:285:285) (335:335:335)) - (PORT datab (346:346:346) (413:413:413)) - (PORT datac (335:335:335) (386:386:386)) - (PORT datad (346:346:346) (404:404:404)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) - (DELAY - (ABSOLUTE - (PORT dataa (443:443:443) (511:511:511)) - (PORT datab (319:319:319) (379:379:379)) - (PORT datac (103:103:103) (125:125:125)) - (PORT datad (97:97:97) (117:117:117)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (483:483:483)) - (PORT datab (325:325:325) (379:379:379)) - (PORT datac (607:607:607) (727:727:727)) - (PORT datad (498:498:498) (582:582:582)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (129:129:129) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (420:420:420) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (235:235:235) (302:302:302)) - (PORT datab (358:358:358) (435:435:435)) - (PORT datac (469:469:469) (547:547:547)) - (PORT datad (357:357:357) (423:423:423)) - (IOPATH dataa combout (195:195:195) (203:203:203)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~12) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (556:556:556)) - (PORT datab (117:117:117) (151:151:151)) - (PORT datac (451:451:451) (526:526:526)) - (PORT datad (493:493:493) (588:588:588)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) - (DELAY - (ABSOLUTE - (PORT dataa (441:441:441) (526:526:526)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (986:986:986) (1116:1116:1116)) - (PORT datad (432:432:432) (495:495:495)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (423:423:423)) - (PORT datab (977:977:977) (1099:1099:1099)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (443:443:443) (508:508:508)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1328:1328:1328) (1554:1554:1554)) - (PORT datab (847:847:847) (991:991:991)) - (PORT datac (471:471:471) (546:546:546)) - (PORT datad (574:574:574) (679:679:679)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) - (DELAY - (ABSOLUTE - (PORT dataa (310:310:310) (357:357:357)) - (PORT datab (556:556:556) (654:654:654)) - (PORT datac (365:365:365) (433:433:433)) - (PORT datad (450:450:450) (510:510:510)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) - (DELAY - (ABSOLUTE - (PORT dataa (544:544:544) (627:627:627)) - (PORT datab (227:227:227) (274:274:274)) - (PORT datac (528:528:528) (616:616:616)) - (PORT datad (642:642:642) (749:749:749)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) - (DELAY - (ABSOLUTE - (PORT dataa (124:124:124) (158:158:158)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datac (103:103:103) (125:125:125)) - (PORT datad (109:109:109) (129:129:129)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) - (DELAY - (ABSOLUTE - (PORT datab (123:123:123) (158:158:158)) - (PORT datac (102:102:102) (129:129:129)) - (PORT datad (196:196:196) (226:226:226)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (343:343:343) (402:402:402)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) - (DELAY - (ABSOLUTE - (PORT datab (730:730:730) (863:863:863)) - (PORT datac (490:490:490) (574:574:574)) - (PORT datad (634:634:634) (727:727:727)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (833:833:833)) - (PORT datab (568:568:568) (671:671:671)) - (PORT datac (830:830:830) (949:949:949)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1153:1153:1153) (1315:1315:1315)) - (PORT datab (528:528:528) (618:618:618)) - (PORT datac (659:659:659) (762:762:762)) - (PORT datad (597:597:597) (687:687:687)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) - (DELAY - (ABSOLUTE - (PORT dataa (506:506:506) (584:584:584)) - (PORT datab (581:581:581) (661:661:661)) - (PORT datac (499:499:499) (576:576:576)) - (PORT datad (301:301:301) (346:346:346)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) - (DELAY - (ABSOLUTE - (PORT dataa (846:846:846) (994:994:994)) - (PORT datab (228:228:228) (276:276:276)) - (PORT datac (520:520:520) (602:602:602)) - (PORT datad (643:643:643) (751:751:751)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) - (DELAY - (ABSOLUTE - (PORT dataa (848:848:848) (996:996:996)) - (PORT datab (122:122:122) (153:153:153)) - (PORT datac (1117:1117:1117) (1275:1275:1275)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (115:115:115) (144:144:144)) - (PORT datac (334:334:334) (392:392:392)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (144:144:144)) - (PORT datab (113:113:113) (142:142:142)) - (PORT datac (464:464:464) (541:541:541)) - (PORT datad (291:291:291) (331:331:331)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) - (DELAY - (ABSOLUTE - (PORT dataa (823:823:823) (952:952:952)) - (PORT datab (777:777:777) (887:887:887)) - (PORT datac (874:874:874) (993:993:993)) - (PORT datad (576:576:576) (656:656:656)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) - (DELAY - (ABSOLUTE - (PORT dataa (403:403:403) (468:468:468)) - (PORT datab (378:378:378) (450:450:450)) - (PORT datac (865:865:865) (979:979:979)) - (PORT datad (810:810:810) (926:926:926)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~43) - (DELAY - (ABSOLUTE - (PORT dataa (753:753:753) (894:894:894)) - (PORT datab (587:587:587) (675:675:675)) - (PORT datac (873:873:873) (991:991:991)) - (PORT datad (1006:1006:1006) (1178:1178:1178)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (458:458:458) (529:529:529)) - (PORT datac (869:869:869) (983:983:983)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~42) - (DELAY - (ABSOLUTE - (PORT dataa (449:449:449) (528:528:528)) - (PORT datab (591:591:591) (680:680:680)) - (PORT datac (1181:1181:1181) (1374:1374:1374)) - (PORT datad (1001:1001:1001) (1172:1172:1172)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (543:543:543) (616:616:616)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~41) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (427:427:427)) - (PORT datab (1124:1124:1124) (1291:1291:1291)) - (PORT datac (822:822:822) (957:957:957)) - (PORT datad (767:767:767) (909:909:909)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) - (DELAY - (ABSOLUTE - (PORT dataa (838:838:838) (981:981:981)) - (PORT datab (1110:1110:1110) (1274:1274:1274)) - (PORT datac (715:715:715) (835:835:835)) - (PORT datad (487:487:487) (562:562:562)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~10) - (DELAY - (ABSOLUTE - (PORT dataa (997:997:997) (1156:1156:1156)) - (PORT datab (578:578:578) (684:684:684)) - (PORT datac (104:104:104) (127:127:127)) - (PORT datad (847:847:847) (970:970:970)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (717:717:717)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (756:756:756) (863:863:863)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~44) - (DELAY - (ABSOLUTE - (PORT dataa (444:444:444) (511:511:511)) - (PORT datab (1029:1029:1029) (1201:1201:1201)) - (PORT datac (731:731:731) (871:871:871)) - (PORT datad (1007:1007:1007) (1179:1179:1179)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (378:378:378) (449:449:449)) - (PORT datac (465:465:465) (531:531:531)) - (PORT datad (381:381:381) (441:441:441)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) - (DELAY - (ABSOLUTE - (PORT dataa (276:276:276) (319:319:319)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (342:342:342) (406:406:406)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~39) - (DELAY - (ABSOLUTE - (PORT dataa (317:317:317) (376:376:376)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (325:325:325) (381:381:381)) - (PORT datad (177:177:177) (203:203:203)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~40) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (519:519:519) (594:594:594)) - (PORT datac (102:102:102) (123:123:123)) - (PORT datad (162:162:162) (191:191:191)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (940:940:940) (1084:1084:1084)) - (PORT datab (810:810:810) (933:933:933)) - (PORT datac (337:337:337) (400:400:400)) - (PORT datad (468:468:468) (534:534:534)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) - (DELAY - (ABSOLUTE - (PORT dataa (804:804:804) (935:935:935)) - (PORT datab (454:454:454) (519:519:519)) - (PORT datac (456:456:456) (518:518:518)) - (PORT datad (773:773:773) (884:884:884)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R) - (DELAY - (ABSOLUTE - (PORT dataa (448:448:448) (518:518:518)) - (PORT datab (977:977:977) (1099:1099:1099)) - (PORT datac (330:330:330) (389:389:389)) - (PORT datad (442:442:442) (508:508:508)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (763:763:763)) - (PORT datab (116:116:116) (150:150:150)) - (PORT datac (495:495:495) (580:580:580)) - (PORT datad (328:328:328) (378:378:378)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (144:144:144) (189:189:189)) - (PORT datab (523:523:523) (615:615:615)) - (PORT datac (272:272:272) (314:314:314)) - (PORT datad (614:614:614) (701:701:701)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (420:420:420) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (315:315:315) (389:389:389)) - (PORT datab (620:620:620) (740:740:740)) - (PORT datac (310:310:310) (357:357:357)) - (PORT datad (205:205:205) (248:248:248)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (145:145:145) (193:193:193)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (290:290:290) (339:339:339)) - (PORT datad (499:499:499) (584:584:584)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (420:420:420) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (295:295:295)) - (PORT datab (226:226:226) (289:289:289)) - (PORT datac (471:471:471) (549:549:549)) - (PORT datad (352:352:352) (418:418:418)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH datab combout (196:196:196) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (141:141:141)) - (PORT datab (341:341:341) (395:395:395)) - (PORT datac (181:181:181) (220:220:220)) - (PORT datad (439:439:439) (506:506:506)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (240:240:240)) - (PORT datab (348:348:348) (420:420:420)) - (PORT datac (346:346:346) (410:410:410)) - (PORT datad (344:344:344) (397:397:397)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (213:213:213) (254:254:254)) - (PORT datab (128:128:128) (161:161:161)) - (PORT datac (96:96:96) (120:120:120)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (453:453:453)) - (PORT datab (646:646:646) (772:772:772)) - (PORT datac (468:468:468) (546:546:546)) - (PORT datad (360:360:360) (420:420:420)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (739:739:739) (860:860:860)) - (PORT datab (1112:1112:1112) (1276:1276:1276)) - (PORT datac (821:821:821) (956:956:956)) - (PORT datad (848:848:848) (984:984:984)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (723:723:723)) - (PORT datab (334:334:334) (392:392:392)) - (PORT datac (447:447:447) (512:512:512)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (111:111:111) (146:146:146)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datad (423:423:423) (484:484:484)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) - (DELAY - (ABSOLUTE - (PORT clk (900:900:900) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (727:727:727)) - (PORT datac (306:306:306) (350:350:350)) - (PORT datad (911:911:911) (1051:1051:1051)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) - (DELAY - (ABSOLUTE - (PORT dataa (492:492:492) (567:567:567)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (1037:1037:1037) (1212:1212:1212)) - (PORT datad (302:302:302) (345:345:345)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~13) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (1171:1171:1171) (1361:1361:1361)) - (PORT datac (739:739:739) (871:871:871)) - (PORT datad (497:497:497) (586:586:586)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (260:260:260)) - (PORT datab (314:314:314) (364:364:364)) - (PORT datac (654:654:654) (765:765:765)) - (PORT datad (449:449:449) (520:520:520)) - (IOPATH dataa combout (192:192:192) (184:184:184)) - (IOPATH datab combout (182:182:182) (188:188:188)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) - (DELAY - (ABSOLUTE - (PORT dataa (302:302:302) (353:353:353)) - (PORT datab (319:319:319) (370:370:370)) - (PORT datad (288:288:288) (330:330:330)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (411:411:411)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (428:428:428) (490:490:490)) - (PORT datad (107:107:107) (125:125:125)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (934:934:934) (1091:1091:1091)) - (PORT datab (499:499:499) (574:574:574)) - (PORT datac (486:486:486) (558:558:558)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[12\]) - (DELAY - (ABSOLUTE - (PORT datab (217:217:217) (260:260:260)) - (PORT datac (484:484:484) (559:559:559)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[12\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (162:162:162) (189:189:189)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (905:905:905)) - (PORT ena (1106:1106:1106) (1248:1248:1248)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (323:323:323) (376:376:376)) - (PORT datab (479:479:479) (565:565:565)) - (PORT datac (132:132:132) (179:179:179)) - (PORT datad (309:309:309) (369:369:369)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (747:747:747)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT asdata (694:694:694) (776:776:776)) - (PORT ena (480:480:480) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (263:263:263)) - (PORT datab (217:217:217) (260:260:260)) - (PORT datad (102:102:102) (118:118:118)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (428:428:428)) - (PORT datac (117:117:117) (158:158:158)) - (PORT datad (441:441:441) (509:509:509)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (241:241:241)) - (PORT datab (452:452:452) (526:526:526)) - (PORT datac (369:369:369) (438:438:438)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (1107:1107:1107) (1234:1234:1234)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (248:248:248)) - (PORT datab (648:648:648) (750:750:750)) - (PORT datad (384:384:384) (437:437:437)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (776:776:776) (851:851:851)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (1105:1105:1105) (1232:1232:1232)) - (PORT ena (663:663:663) (731:731:731)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (381:381:381) (461:461:461)) - (PORT datab (470:470:470) (545:545:545)) - (PORT datad (480:480:480) (550:550:550)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (775:775:775) (861:861:861)) - (PORT ena (622:622:622) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (774:774:774) (861:861:861)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (488:488:488) (578:578:578)) - (PORT datab (130:130:130) (164:164:164)) - (PORT datad (117:117:117) (152:152:152)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (764:764:764) (865:865:865)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (627:627:627) (675:675:675)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (933:933:933) (1030:1030:1030)) - (PORT ena (670:670:670) (742:742:742)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (262:262:262)) - (PORT datab (892:892:892) (1040:1040:1040)) - (PORT datad (642:642:642) (747:747:747)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (101:101:101) (129:129:129)) - (PORT datac (422:422:422) (489:489:489)) - (PORT datad (328:328:328) (384:384:384)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (1062:1062:1062) (1195:1195:1195)) - (PORT ena (753:753:753) (845:845:845)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (1201:1201:1201) (1360:1360:1360)) + (PORT ena (782:782:782) (860:860:860)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -20986,9 +21538,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (1061:1061:1061) (1195:1195:1195)) - (PORT ena (759:759:759) (842:842:842)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (1202:1202:1202) (1362:1362:1362)) + (PORT ena (797:797:797) (873:873:873)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -20999,58 +21551,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~59) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~50) (DELAY (ABSOLUTE - (PORT dataa (513:513:513) (629:629:629)) - (PORT datab (511:511:511) (618:618:618)) - (PORT datad (115:115:115) (152:152:152)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (1044:1044:1044) (1156:1156:1156)) - (PORT ena (515:515:515) (556:556:556)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (1043:1043:1043) (1155:1155:1155)) - (PORT ena (506:506:506) (537:537:537)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (257:257:257) (310:310:310)) - (PORT datab (266:266:266) (318:318:318)) + (PORT dataa (513:513:513) (600:600:600)) + (PORT datab (516:516:516) (603:603:603)) (PORT datad (117:117:117) (154:154:154)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) @@ -21064,603 +21569,12 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (1059:1059:1059) (1190:1190:1190)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (507:507:507) (606:606:606)) - (PORT datab (669:669:669) (791:791:791)) - (PORT datad (485:485:485) (564:564:564)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (415:415:415)) - (PORT datab (168:168:168) (205:205:205)) - (PORT datac (310:310:310) (357:357:357)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (508:508:508) (606:606:606)) - (PORT datab (479:479:479) (577:577:577)) - (PORT datac (439:439:439) (509:509:509)) - (PORT datad (730:730:730) (839:839:839)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (715:715:715) (846:846:846)) - (PORT datab (537:537:537) (630:630:630)) - (PORT datac (464:464:464) (539:539:539)) - (PORT datad (804:804:804) (906:906:906)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (704:704:704) (830:830:830)) - (PORT datab (666:666:666) (773:773:773)) - (PORT datac (507:507:507) (583:583:583)) - (PORT datad (522:522:522) (608:608:608)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (140:140:140)) - (PORT datab (129:129:129) (168:168:168)) - (PORT datac (562:562:562) (636:636:636)) - (PORT datad (527:527:527) (614:614:614)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) - (DELAY - (ABSOLUTE - (PORT dataa (718:718:718) (845:845:845)) - (PORT datab (522:522:522) (615:615:615)) - (PORT datac (192:192:192) (229:229:229)) - (PORT datad (665:665:665) (793:793:793)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (781:781:781)) - (PORT datab (1031:1031:1031) (1199:1199:1199)) - (PORT datac (487:487:487) (576:576:576)) - (PORT datad (858:858:858) (1004:1004:1004)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) - (DELAY - (ABSOLUTE - (PORT dataa (519:519:519) (610:610:610)) - (PORT datab (346:346:346) (403:403:403)) - (PORT datac (799:799:799) (940:940:940)) - (PORT datad (320:320:320) (371:371:371)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datac (504:504:504) (590:590:590)) - (PORT datad (127:127:127) (156:156:156)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (756:756:756)) - (PORT datab (158:158:158) (203:203:203)) - (PORT datac (141:141:141) (181:181:181)) - (PORT datad (131:131:131) (162:162:162)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT datab (185:185:185) (226:226:226)) - (PORT datac (513:513:513) (610:610:610)) - (PORT datad (371:371:371) (441:441:441)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (1068:1068:1068) (1190:1190:1190)) (PORT ena (422:422:422) (450:450:450)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (407:407:407)) - (PORT datab (656:656:656) (758:758:758)) - (PORT datac (341:341:341) (416:416:416)) - (PORT datad (370:370:370) (437:437:437)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (318:318:318) (379:379:379)) - (PORT datab (168:168:168) (204:204:204)) - (PORT datac (632:632:632) (738:738:738)) - (PORT datad (281:281:281) (324:324:324)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (336:336:336) (396:396:396)) - (PORT datab (546:546:546) (645:645:645)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (119:119:119) (149:149:149)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (317:317:317) (372:372:372)) - (PORT datab (529:529:529) (627:627:627)) - (PORT datac (478:478:478) (551:551:551)) - (PORT datad (175:175:175) (205:205:205)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (369:369:369) (439:439:439)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) - (DELAY - (ABSOLUTE - (PORT dataa (502:502:502) (585:585:585)) - (PORT datab (394:394:394) (473:473:473)) - (PORT datac (511:511:511) (608:608:608)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (409:409:409)) - (PORT datab (342:342:342) (411:411:411)) - (PORT datac (331:331:331) (386:386:386)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (329:329:329) (379:379:379)) - (PORT datab (515:515:515) (607:607:607)) - (PORT datac (609:609:609) (729:729:729)) - (PORT datad (307:307:307) (355:355:355)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (144:144:144) (192:192:192)) - (PORT datac (90:90:90) (112:112:112)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (420:420:420) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (235:235:235) (302:302:302)) - (PORT datac (341:341:341) (416:416:416)) - (PORT datad (355:355:355) (421:421:421)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (300:300:300) (345:345:345)) - (PORT datab (451:451:451) (516:516:516)) - (PORT datac (426:426:426) (488:488:488)) - (PORT datad (106:106:106) (125:125:125)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (429:429:429)) - (PORT datab (108:108:108) (138:138:138)) - (PORT datac (109:109:109) (133:133:133)) - (PORT datad (438:438:438) (502:502:502)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (409:409:409)) - (PORT datab (345:345:345) (412:412:412)) - (PORT datad (346:346:346) (404:404:404)) - (IOPATH dataa combout (172:172:172) (165:165:165)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (423:423:423)) - (PORT datab (462:462:462) (533:533:533)) - (PORT datac (96:96:96) (120:120:120)) - (PORT datad (267:267:267) (304:304:304)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (141:141:141)) - (PORT datab (111:111:111) (144:144:144)) - (PORT datac (108:108:108) (132:132:132)) - (PORT datad (97:97:97) (116:116:116)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (414:414:414)) - (PORT datab (358:358:358) (421:421:421)) - (PORT datad (326:326:326) (386:386:386)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (194:194:194) (233:233:233)) - (PORT datab (341:341:341) (396:396:396)) - (PORT datac (95:95:95) (120:120:120)) - (PORT datad (439:439:439) (506:506:506)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (196:196:196) (237:237:237)) - (PORT datab (203:203:203) (245:245:245)) - (PORT datac (93:93:93) (117:117:117)) - (PORT datad (186:186:186) (220:220:220)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) - (DELAY - (ABSOLUTE - (PORT datac (960:960:960) (1080:1080:1080)) - (PORT datad (442:442:442) (507:507:507)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (234:234:234)) - (PORT datab (123:123:123) (155:155:155)) - (PORT datac (92:92:92) (116:116:116)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (142:142:142)) - (PORT datab (125:125:125) (158:158:158)) - (PORT datac (179:179:179) (218:218:218)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (614:614:614) (710:710:710)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (627:627:627) (675:675:675)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (803:803:803) (911:911:911)) - (PORT ena (670:670:670) (742:742:742)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) (TIMINGCHECK (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) @@ -21668,59 +21582,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~69) + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~16) (DELAY (ABSOLUTE - (PORT dataa (130:130:130) (181:181:181)) - (PORT datab (893:893:893) (1041:1041:1041)) - (PORT datad (643:643:643) (748:748:748)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (920:920:920) (1042:1042:1042)) - (PORT ena (622:622:622) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (918:918:918) (1040:1040:1040)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (484:484:484) (573:573:573)) - (PORT datab (130:130:130) (163:163:163)) - (PORT datad (119:119:119) (156:156:156)) + (PORT dataa (805:805:805) (958:958:958)) + (PORT datab (357:357:357) (420:420:420)) + (PORT datad (955:955:955) (1130:1130:1130)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -21730,106 +21597,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (776:776:776) (851:851:851)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (798:798:798) (895:895:895)) - (PORT ena (663:663:663) (731:731:731)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (386:386:386) (470:470:470)) - (PORT datab (470:470:470) (545:545:545)) - (PORT datad (480:480:480) (550:550:550)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (798:798:798) (895:895:895)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (761:761:761) (870:870:870)) - (PORT datab (650:650:650) (752:752:752)) - (PORT datad (129:129:129) (157:157:157)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (439:439:439) (513:513:513)) - (PORT datab (600:600:600) (712:712:712)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (803:803:803) (913:913:913)) - (PORT ena (515:515:515) (556:556:556)) + (PORT clk (903:903:903) (907:907:907)) + (PORT asdata (511:511:511) (570:570:570)) + (PORT ena (820:820:820) (910:910:910)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -21840,12 +21613,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (803:803:803) (913:913:913)) - (PORT ena (506:506:506) (537:537:537)) + (PORT clk (903:903:903) (907:907:907)) + (PORT asdata (513:513:513) (571:571:571)) + (PORT ena (778:778:778) (844:844:844)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -21856,12 +21629,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~67) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~49) (DELAY (ABSOLUTE - (PORT dataa (257:257:257) (311:311:311)) - (PORT datab (266:266:266) (317:317:317)) - (PORT datad (117:117:117) (153:153:153)) + (PORT dataa (538:538:538) (642:642:642)) + (PORT datab (537:537:537) (622:622:622)) + (PORT datad (184:184:184) (231:231:231)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -21871,11 +21644,58 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (765:765:765) (858:858:858)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (970:970:970) (1085:1085:1085)) + (PORT ena (606:606:606) (646:646:646)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (972:972:972) (1087:1087:1087)) + (PORT ena (631:631:631) (686:686:686)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (421:421:421)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datad (333:333:333) (390:390:390)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT asdata (1050:1050:1050) (1181:1181:1181)) (PORT ena (408:408:408) (429:429:429)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -21886,14 +21706,30 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~20) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT dataa (508:508:508) (607:607:607)) - (PORT datab (669:669:669) (791:791:791)) - (PORT datad (483:483:483) (561:561:561)) - (IOPATH dataa combout (158:158:158) (163:163:163)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (1083:1083:1083) (1207:1207:1207)) + (PORT ena (619:619:619) (665:665:665)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (297:297:297)) + (PORT datab (269:269:269) (326:326:326)) + (PORT datad (331:331:331) (384:384:384)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -21902,28 +21738,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (664:664:664) (748:748:748)) - (PORT ena (753:753:753) (845:845:845)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (663:663:663) (747:747:747)) - (PORT ena (759:759:759) (842:842:842)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (1084:1084:1084) (1208:1208:1208)) + (PORT ena (655:655:655) (718:718:718)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -21934,12 +21754,44 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~68) + (INSTANCE z80_\|alu_\|db\[4\]\~8) (DELAY (ABSOLUTE - (PORT dataa (506:506:506) (619:619:619)) - (PORT datab (515:515:515) (623:623:623)) - (PORT datad (117:117:117) (154:154:154)) + (PORT dataa (591:591:591) (683:683:683)) + (PORT datab (478:478:478) (554:554:554)) + (PORT datac (435:435:435) (499:499:499)) + (PORT datad (632:632:632) (721:721:721)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (439:439:439)) + (PORT datab (579:579:579) (667:667:667)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (528:528:528) (611:611:611)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (637:637:637)) + (PORT datab (714:714:714) (835:835:835)) + (PORT datad (493:493:493) (577:577:577)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -21948,29 +21800,29 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~74) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT dataa (194:194:194) (234:234:234)) - (PORT datab (339:339:339) (406:406:406)) - (PORT datac (342:342:342) (405:405:405)) - (PORT datad (462:462:462) (547:547:547)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (787:787:787) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT asdata (632:632:632) (700:700:700)) - (PORT ena (480:480:480) (509:509:509)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (1189:1189:1189) (1340:1340:1340)) + (PORT ena (619:619:619) (666:666:666)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -21981,12 +21833,91 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~19) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~54) (DELAY (ABSOLUTE - (PORT dataa (117:117:117) (148:148:148)) - (PORT datab (210:210:210) (253:253:253)) - (PORT datad (206:206:206) (243:243:243)) + (PORT dataa (129:129:129) (178:178:178)) + (PORT datab (519:519:519) (612:612:612)) + (PORT datad (471:471:471) (553:553:553)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (424:424:424)) + (PORT datab (357:357:357) (426:426:426)) + (PORT datac (337:337:337) (397:397:397)) + (PORT datad (335:335:335) (395:395:395)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (387:387:387)) + (PORT datab (364:364:364) (428:428:428)) + (PORT datac (458:458:458) (533:533:533)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (761:761:761) (881:881:881)) + (PORT datab (347:347:347) (417:417:417)) + (PORT datac (289:289:289) (330:330:330)) + (PORT datad (194:194:194) (226:226:226)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (602:602:602) (658:658:658)) + (PORT ena (599:599:599) (646:646:646)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (1058:1058:1058)) + (PORT datab (311:311:311) (365:365:365)) + (PORT datad (299:299:299) (350:350:350)) (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -21996,12 +21927,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) (DELAY (ABSOLUTE (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (747:747:747)) + (PORT ena (611:611:611) (658:658:658)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -22012,27 +21943,89 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~20) + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~14) (DELAY (ABSOLUTE - (PORT dataa (451:451:451) (544:544:544)) - (PORT datac (115:115:115) (156:156:156)) - (PORT datad (349:349:349) (406:406:406)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (116:116:116) (158:158:158)) + (PORT datad (297:297:297) (342:342:342)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (297:297:297) (345:345:345)) + (PORT datab (387:387:387) (461:461:461)) + (PORT datac (202:202:202) (259:259:259)) + (PORT datad (333:333:333) (395:395:395)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (257:257:257) (313:313:313)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (277:277:277) (318:318:318)) + (PORT datad (832:832:832) (975:975:975)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[12\]) + (DELAY + (ABSOLUTE + (PORT datab (492:492:492) (571:571:571)) + (PORT datac (433:433:433) (495:495:495)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (919:919:919) (904:904:904)) + (PORT ena (937:937:937) (1043:1043:1043)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) (DELAY (ABSOLUTE - (PORT dataa (321:321:321) (374:374:374)) - (PORT datab (486:486:486) (573:573:573)) - (PORT datac (129:129:129) (176:176:176)) - (PORT datad (306:306:306) (366:366:366)) + (PORT dataa (299:299:299) (347:347:347)) + (PORT datab (388:388:388) (462:462:462)) + (PORT datac (199:199:199) (256:256:256)) + (PORT datad (333:333:333) (395:395:395)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (190:190:190) (181:181:181)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -22045,395 +22038,9 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) (DELAY (ABSOLUTE - (PORT datac (144:144:144) (192:192:192)) + (PORT dataa (227:227:227) (291:291:291)) (PORT datad (98:98:98) (120:120:120)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (796:796:796) (899:899:899)) - (PORT ena (673:673:673) (745:745:745)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (776:776:776) (851:851:851)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (685:685:685)) - (PORT datab (478:478:478) (553:553:553)) - (PORT datad (361:361:361) (437:437:437)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (1146:1146:1146) (1300:1300:1300)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (913:913:913) (1038:1038:1038)) - (PORT datab (647:647:647) (748:748:748)) - (PORT datad (121:121:121) (149:149:149)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (628:628:628) (736:736:736)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (627:627:627) (675:675:675)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (795:795:795) (894:894:894)) - (PORT ena (670:670:670) (742:742:742)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (259:259:259)) - (PORT datab (896:896:896) (1045:1045:1045)) - (PORT datad (644:644:644) (749:749:749)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (1005:1005:1005) (1137:1137:1137)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (796:796:796) (899:899:899)) - (PORT ena (582:582:582) (618:618:618)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (214:214:214) (270:270:270)) - (PORT datab (477:477:477) (557:557:557)) - (PORT datad (191:191:191) (219:219:219)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (172:172:172) (209:209:209)) - (PORT datac (421:421:421) (477:477:477)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (805:805:805) (908:908:908)) - (PORT ena (506:506:506) (537:537:537)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (805:805:805) (908:908:908)) - (PORT ena (515:515:515) (556:556:556)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (255:255:255) (308:308:308)) - (PORT datab (129:129:129) (176:176:176)) - (PORT datad (249:249:249) (295:295:295)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (958:958:958) (1085:1085:1085)) - (PORT ena (759:759:759) (842:842:842)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (959:959:959) (1086:1086:1086)) - (PORT ena (753:753:753) (845:845:845)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (512:512:512) (627:627:627)) - (PORT datab (132:132:132) (180:180:180)) - (PORT datad (497:497:497) (594:594:594)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (979:979:979) (1116:1116:1116)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (507:507:507) (606:606:606)) - (PORT datab (669:669:669) (791:791:791)) - (PORT datad (486:486:486) (565:565:565)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (417:417:417)) - (PORT datab (473:473:473) (555:555:555)) - (PORT datac (323:323:323) (380:380:380)) - (PORT datad (438:438:438) (504:504:504)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (509:509:509) (607:607:607)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (463:463:463) (547:547:547)) - (PORT datad (729:729:729) (839:839:839)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT asdata (641:641:641) (723:723:723)) - (PORT ena (480:480:480) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (214:214:214) (262:262:262)) - (PORT datab (113:113:113) (141:141:141)) - (PORT datad (204:204:204) (240:240:240)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -22445,7 +22052,280 @@ (ABSOLUTE (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (747:747:747)) + (PORT ena (611:611:611) (658:658:658)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (907:907:907)) + (PORT asdata (522:522:522) (585:585:585)) + (PORT ena (820:820:820) (910:910:910)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (907:907:907)) + (PORT asdata (522:522:522) (585:585:585)) + (PORT ena (778:778:778) (844:844:844)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (645:645:645)) + (PORT datab (540:540:540) (627:627:627)) + (PORT datad (116:116:116) (152:152:152)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (351:351:351) (388:388:388)) + (PORT ena (782:782:782) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (351:351:351) (388:388:388)) + (PORT ena (797:797:797) (873:873:873)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (600:600:600)) + (PORT datab (515:515:515) (601:601:601)) + (PORT datad (116:116:116) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (493:493:493) (573:573:573)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (408:408:408) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (930:930:930) (1043:1043:1043)) + (PORT ena (619:619:619) (665:665:665)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (409:409:409)) + (PORT datab (269:269:269) (326:326:326)) + (PORT datad (332:332:332) (384:384:384)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (929:929:929) (1041:1041:1041)) + (PORT ena (655:655:655) (718:718:718)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (704:704:704)) + (PORT datab (389:389:389) (460:460:460)) + (PORT datac (601:601:601) (681:681:681)) + (PORT datad (102:102:102) (125:125:125)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (799:799:799)) + (PORT datab (441:441:441) (511:511:511)) + (PORT datac (451:451:451) (523:523:523)) + (PORT datad (426:426:426) (487:487:487)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) + (DELAY + (ABSOLUTE + (PORT dataa (690:690:690) (805:805:805)) + (PORT datab (529:529:529) (631:631:631)) + (PORT datac (350:350:350) (413:413:413)) + (PORT datad (771:771:771) (922:922:922)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) + (DELAY + (ABSOLUTE + (PORT dataa (179:179:179) (222:222:222)) + (PORT datab (498:498:498) (583:583:583)) + (PORT datac (341:341:341) (395:395:395)) + (PORT datad (521:521:521) (607:607:607)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (521:521:521) (605:605:605)) + (PORT datab (155:155:155) (200:200:200)) + (PORT datad (459:459:459) (527:527:527)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) + (DELAY + (ABSOLUTE + (PORT datab (156:156:156) (200:200:200)) + (PORT datad (458:458:458) (527:527:527)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (450:450:450)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -22456,28 +22336,72 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~14) + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) (DELAY (ABSOLUTE - (PORT dataa (360:360:360) (428:428:428)) - (PORT datab (202:202:202) (245:245:245)) - (PORT datac (116:116:116) (156:156:156)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (1110:1110:1110) (1311:1311:1311)) + (PORT datac (590:590:590) (673:673:673)) + (PORT datad (754:754:754) (917:917:917)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~15) + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) (DELAY (ABSOLUTE - (PORT dataa (288:288:288) (336:336:336)) - (PORT datab (459:459:459) (533:533:533)) - (PORT datac (372:372:372) (441:441:441)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) + (PORT dataa (494:494:494) (572:572:572)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (491:491:491) (574:574:574)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (149:149:149)) + (PORT datac (375:375:375) (459:459:459)) + (PORT datad (486:486:486) (579:579:579)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (116:116:116) (145:145:145)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (753:753:753) (857:857:857)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (1015:1015:1015)) + (PORT datab (893:893:893) (1054:1054:1054)) + (PORT datac (473:473:473) (551:551:551)) + (PORT datad (217:217:217) (270:270:270)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -22486,37 +22410,134 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[13\]) + (INSTANCE z80_\|alu_\|db_low\[1\]\~15) (DELAY (ABSOLUTE - (PORT datab (204:204:204) (251:251:251)) - (PORT datac (486:486:486) (561:561:561)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (241:241:241) (301:301:301)) + (PORT datab (309:309:309) (361:361:361)) + (PORT datac (476:476:476) (562:562:562)) + (PORT datad (128:128:128) (156:156:156)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[13\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (172:172:172) (202:202:202)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[13\]) + (INSTANCE z80_\|alu_\|result_lo\[1\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (905:905:905)) - (PORT ena (1106:1106:1106) (1248:1248:1248)) + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (341:341:341) (368:368:368)) + (PORT ena (779:779:779) (853:853:853)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (395:395:395)) + (PORT datab (614:614:614) (705:705:705)) + (PORT datad (450:450:450) (521:521:521)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (396:396:396)) + (PORT datab (724:724:724) (832:832:832)) + (PORT datac (111:111:111) (136:136:136)) + (PORT datad (446:446:446) (519:519:519)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datac (136:136:136) (173:173:173)) + (PORT datad (179:179:179) (211:211:211)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (239:239:239)) + (PORT datab (552:552:552) (652:652:652)) + (PORT datac (924:924:924) (1078:1078:1078)) + (PORT datad (662:662:662) (759:759:759)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (308:308:308) (361:361:361)) + (PORT datac (499:499:499) (582:582:582)) + (PORT datad (459:459:459) (528:528:528)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) + (DELAY + (ABSOLUTE + (PORT datab (315:315:315) (370:370:370)) + (PORT datac (137:137:137) (176:176:176)) + (PORT datad (461:461:461) (530:530:530)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (407:407:407) (424:424:424)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK @@ -22526,11 +22547,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) (DELAY (ABSOLUTE - (PORT datac (144:144:144) (193:193:193)) - (PORT datad (467:467:467) (548:548:548)) + (PORT dataa (481:481:481) (557:557:557)) + (PORT datab (547:547:547) (646:646:646)) + (PORT datac (928:928:928) (1083:1083:1083)) + (PORT datad (654:654:654) (751:751:751)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -22538,11 +22563,389 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[15\]) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) (DELAY (ABSOLUTE - (PORT datac (183:183:183) (215:215:215)) - (PORT datad (471:471:471) (541:541:541)) + (PORT dataa (517:517:517) (614:614:614)) + (PORT datab (610:610:610) (732:732:732)) + (PORT datac (474:474:474) (556:556:556)) + (PORT datad (346:346:346) (402:402:402)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (431:431:431)) + (PORT datab (355:355:355) (421:421:421)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (507:507:507) (592:592:592)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (427:427:427)) + (PORT datab (354:354:354) (418:418:418)) + (PORT datac (337:337:337) (402:402:402)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (893:893:893)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (454:454:454)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (812:812:812) (964:964:964)) + (PORT datab (511:511:511) (591:591:591)) + (PORT datac (303:303:303) (350:350:350)) + (PORT datad (876:876:876) (1035:1035:1035)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) + (DELAY + (ABSOLUTE + (PORT dataa (476:476:476) (564:564:564)) + (PORT datab (548:548:548) (636:636:636)) + (PORT datac (765:765:765) (869:869:869)) + (PORT datad (353:353:353) (410:410:410)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) + (DELAY + (ABSOLUTE + (PORT dataa (690:690:690) (815:815:815)) + (PORT datab (337:337:337) (396:396:396)) + (PORT datac (822:822:822) (942:942:942)) + (PORT datad (335:335:335) (384:384:384)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nop3pla68M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (777:777:777)) + (PORT datab (682:682:682) (798:798:798)) + (PORT datac (484:484:484) (566:566:566)) + (PORT datad (101:101:101) (118:118:118)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) + (DELAY + (ABSOLUTE + (PORT dataa (690:690:690) (815:815:815)) + (PORT datab (720:720:720) (841:841:841)) + (PORT datac (1206:1206:1206) (1403:1403:1403)) + (PORT datad (815:815:815) (940:940:940)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (231:231:231)) + (PORT datab (348:348:348) (404:404:404)) + (PORT datac (183:183:183) (213:213:213)) + (PORT datad (161:161:161) (189:189:189)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (142:142:142)) + (PORT datab (114:114:114) (141:141:141)) + (PORT datac (93:93:93) (117:117:117)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (224:224:224)) + (PORT datab (172:172:172) (210:210:210)) + (PORT datac (461:461:461) (531:531:531)) + (PORT datad (322:322:322) (378:378:378)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (163:163:163)) + (PORT datab (464:464:464) (531:531:531)) + (PORT datac (186:186:186) (225:225:225)) + (PORT datad (104:104:104) (122:122:122)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (502:502:502) (599:599:599)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (330:330:330) (386:386:386)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (733:733:733) (843:843:843)) + (PORT datab (360:360:360) (425:425:425)) + (PORT datac (344:344:344) (406:406:406)) + (PORT datad (507:507:507) (592:592:592)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~7) + (DELAY + (ABSOLUTE + (PORT datac (336:336:336) (400:400:400)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (893:893:893)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (454:454:454)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (420:420:420)) + (PORT datab (131:131:131) (160:160:160)) + (PORT datac (443:443:443) (514:514:514)) + (PORT datad (447:447:447) (513:513:513)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (293:293:293)) + (PORT datab (468:468:468) (544:544:544)) + (PORT datac (326:326:326) (379:379:379)) + (PORT datad (291:291:291) (339:339:339)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (758:758:758)) + (PORT datab (296:296:296) (343:343:343)) + (PORT datac (463:463:463) (537:537:537)) + (PORT datad (1005:1005:1005) (1179:1179:1179)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (760:760:760)) + (PORT datab (295:295:295) (341:341:341)) + (PORT datac (461:461:461) (534:534:534)) + (PORT datad (1006:1006:1006) (1180:1180:1180)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (168:168:168)) + (PORT datab (288:288:288) (331:331:331)) + (PORT datac (123:123:123) (148:148:148)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (147:147:147)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (113:113:113) (142:142:142)) + (PORT datad (110:110:110) (130:130:130)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (153:153:153)) + (PORT datab (106:106:106) (136:136:136)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT datab (437:437:437) (506:506:506)) + (PORT datac (290:290:290) (336:336:336)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -22550,13 +22953,516 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[15\]) + (INSTANCE z80_\|alu_\|op1_high\[2\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) + (PORT clk (913:913:913) (900:900:900)) + (PORT asdata (353:353:353) (386:386:386)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (671:671:671)) + (PORT datab (352:352:352) (416:416:416)) + (PORT datac (339:339:339) (401:401:401)) + (PORT datad (311:311:311) (356:356:356)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datac (335:335:335) (399:399:399)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (893:893:893)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (905:905:905)) - (PORT ena (1106:1106:1106) (1248:1248:1248)) + (PORT ena (422:422:422) (454:454:454)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (551:551:551) (668:668:668)) + (PORT datab (894:894:894) (1055:1055:1055)) + (PORT datac (472:472:472) (550:550:550)) + (PORT datad (225:225:225) (283:283:283)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (114:114:114) (141:141:141)) + (PORT datac (389:389:389) (477:477:477)) + (PORT datad (483:483:483) (569:569:569)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (479:479:479) (565:565:565)) + (PORT datab (777:777:777) (891:891:891)) + (PORT datac (108:108:108) (132:132:132)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (306:306:306)) + (PORT datab (145:145:145) (184:184:184)) + (PORT datad (317:317:317) (375:375:375)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (464:464:464) (553:553:553)) + (PORT datab (459:459:459) (554:554:554)) + (PORT datac (324:324:324) (380:380:380)) + (PORT datad (332:332:332) (388:388:388)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (121:121:121) (151:151:151)) + (PORT datac (465:465:465) (545:545:545)) + (PORT datad (348:348:348) (402:402:402)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (989:989:989) (1119:1119:1119)) + (PORT ena (782:782:782) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (989:989:989) (1119:1119:1119)) + (PORT ena (797:797:797) (873:873:873)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (512:512:512) (599:599:599)) + (PORT datab (510:510:510) (596:596:596)) + (PORT datad (115:115:115) (152:152:152)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (907:907:907)) + (PORT asdata (957:957:957) (1082:1082:1082)) + (PORT ena (820:820:820) (910:910:910)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (627:627:627) (733:733:733)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (778:778:778) (844:844:844)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (644:644:644)) + (PORT datab (539:539:539) (625:625:625)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (803:803:803) (907:907:907)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (958:958:958)) + (PORT datab (359:359:359) (421:421:421)) + (PORT datad (956:956:956) (1131:1131:1131)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (513:513:513) (563:563:563)) + (PORT ena (619:619:619) (666:666:666)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (511:511:511) (561:561:561)) + (PORT ena (787:787:787) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (493:493:493) (581:581:581)) + (PORT datab (521:521:521) (614:614:614)) + (PORT datad (116:116:116) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT asdata (670:670:670) (762:762:762)) + (PORT ena (408:408:408) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (806:806:806) (913:913:913)) + (PORT ena (619:619:619) (665:665:665)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (409:409:409)) + (PORT datab (242:242:242) (306:306:306)) + (PORT datad (341:341:341) (395:395:395)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (808:808:808) (916:916:916)) + (PORT ena (606:606:606) (646:646:646)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (808:808:808) (915:915:915)) + (PORT ena (631:631:631) (686:686:686)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (419:419:419)) + (PORT datab (128:128:128) (175:175:175)) + (PORT datad (340:340:340) (398:398:398)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (803:803:803) (910:910:910)) + (PORT ena (655:655:655) (718:718:718)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (637:637:637)) + (PORT datab (715:715:715) (837:837:837)) + (PORT datad (477:477:477) (558:558:558)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (193:193:193) (231:231:231)) + (PORT datab (486:486:486) (585:585:585)) + (PORT datac (318:318:318) (373:373:373)) + (PORT datad (436:436:436) (502:502:502)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (305:305:305) (355:355:355)) + (PORT datab (459:459:459) (526:526:526)) + (PORT datac (343:343:343) (395:395:395)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[14\]) + (DELAY + (ABSOLUTE + (PORT datab (488:488:488) (566:566:566)) + (PORT datad (477:477:477) (534:534:534)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (919:919:919) (904:904:904)) + (PORT ena (937:937:937) (1043:1043:1043)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -22571,10 +23477,10 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) (DELAY (ABSOLUTE - (PORT dataa (157:157:157) (212:212:212)) - (PORT datab (113:113:113) (146:146:146)) - (PORT datac (134:134:134) (178:178:178)) - (PORT datad (463:463:463) (544:544:544)) + (PORT dataa (224:224:224) (288:288:288)) + (PORT datab (111:111:111) (143:143:143)) + (PORT datac (305:305:305) (364:364:364)) + (PORT datad (369:369:369) (437:437:437)) (IOPATH dataa combout (188:188:188) (203:203:203)) (IOPATH datab combout (190:190:190) (205:205:205)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -22582,14 +23488,278 @@ ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (401:401:401) (443:443:443)) + (PORT ena (619:619:619) (673:673:673)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (147:147:147)) + (PORT datab (330:330:330) (388:388:388)) + (PORT datad (302:302:302) (346:346:346)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) (DELAY (ABSOLUTE (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (281:281:281) (300:300:300)) + (PORT ena (611:611:611) (658:658:658)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (323:323:323) (379:379:379)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (213:213:213) (266:266:266)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (997:997:997)) + (PORT datab (280:280:280) (327:327:327)) + (PORT datac (234:234:234) (289:289:289)) + (PORT datad (184:184:184) (215:215:215)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (758:758:758) (871:871:871)) + (PORT datac (225:225:225) (269:269:269)) + (PORT datad (110:110:110) (131:131:131)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (664:664:664)) + (PORT datab (476:476:476) (552:552:552)) + (PORT datac (762:762:762) (883:883:883)) + (PORT datad (569:569:569) (656:656:656)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (445:445:445)) + (PORT datab (575:575:575) (663:663:663)) + (PORT datac (545:545:545) (642:642:642)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (407:407:407) (496:496:496)) + (PORT datac (104:104:104) (127:127:127)) + (PORT datad (123:123:123) (142:142:142)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (500:500:500) (593:593:593)) + (PORT datac (764:764:764) (877:877:877)) + (PORT datad (88:88:88) (106:106:106)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (404:404:404)) + (PORT datab (222:222:222) (276:276:276)) + (PORT datac (477:477:477) (564:564:564)) + (PORT datad (133:133:133) (162:162:162)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (422:422:422)) + (PORT datab (471:471:471) (543:543:543)) + (PORT datac (1125:1125:1125) (1310:1310:1310)) + (PORT datad (476:476:476) (574:574:574)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (257:257:257)) + (PORT datab (725:725:725) (832:832:832)) + (PORT datac (328:328:328) (384:384:384)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (469:469:469) (556:556:556)) + (PORT datab (182:182:182) (224:224:224)) + (PORT datac (319:319:319) (376:376:376)) + (PORT datad (338:338:338) (393:393:393)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (591:591:591)) + (PORT datab (316:316:316) (370:370:370)) + (PORT datac (104:104:104) (126:126:126)) + (PORT datad (425:425:425) (492:492:492)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (449:449:449)) + (PORT datab (486:486:486) (567:567:567)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (115:115:115) (139:139:139)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (638:638:638)) + (PORT datab (709:709:709) (830:830:830)) + (PORT datad (772:772:772) (906:906:906)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (747:747:747)) + (PORT ena (787:787:787) (866:866:866)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -22600,28 +23770,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (1314:1314:1314) (1518:1518:1518)) - (PORT ena (515:515:515) (556:556:556)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (1314:1314:1314) (1517:1517:1517)) - (PORT ena (506:506:506) (537:537:537)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (470:470:470) (517:517:517)) + (PORT ena (619:619:619) (666:666:666)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -22632,43 +23786,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~76) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~81) (DELAY (ABSOLUTE - (PORT dataa (255:255:255) (309:309:309)) - (PORT datab (268:268:268) (320:320:320)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (1077:1077:1077) (1239:1239:1239)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (441:441:441) (511:511:511)) - (PORT datab (651:651:651) (753:753:753)) - (PORT datad (130:130:130) (158:158:158)) + (PORT dataa (129:129:129) (179:179:179)) + (PORT datab (522:522:522) (616:616:616)) + (PORT datad (468:468:468) (549:549:549)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -22678,12 +23801,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (676:676:676) (761:761:761)) - (PORT ena (405:405:405) (422:422:422)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (522:522:522) (582:582:582)) + (PORT ena (606:606:606) (646:646:646)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -22694,12 +23817,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (1217:1217:1217) (1390:1390:1390)) - (PORT ena (582:582:582) (618:618:618)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (523:523:523) (583:583:583)) + (PORT ena (631:631:631) (686:686:686)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -22710,43 +23833,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~79) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~78) (DELAY (ABSOLUTE - (PORT dataa (203:203:203) (261:261:261)) - (PORT datab (478:478:478) (558:558:558)) - (PORT datad (192:192:192) (220:220:220)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (357:357:357) (421:421:421)) + (PORT datab (197:197:197) (255:255:255)) + (PORT datad (331:331:331) (388:388:388)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~82) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (808:808:808) (912:912:912)) - (PORT ena (670:670:670) (742:742:742)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (PORT dataa (102:102:102) (133:133:133)) + (PORT datab (105:105:105) (135:135:135)) + (PORT datac (583:583:583) (662:662:662)) + (PORT datad (168:168:168) (197:197:197)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (808:808:808) (913:913:913)) - (PORT ena (627:627:627) (675:675:675)) + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (655:655:655) (727:727:727)) + (PORT ena (422:422:422) (450:450:450)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -22757,12 +23880,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~78) + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~19) (DELAY (ABSOLUTE - (PORT dataa (714:714:714) (841:841:841)) - (PORT datab (662:662:662) (774:774:774)) - (PORT datad (116:116:116) (153:153:153)) + (PORT dataa (805:805:805) (957:957:957)) + (PORT datab (357:357:357) (419:419:419)) + (PORT datad (954:954:954) (1129:1129:1129)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -22771,270 +23894,162 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~83) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (776:776:776) (851:851:851)) + (PORT dataa (424:424:424) (498:498:498)) + (PORT datab (488:488:488) (569:569:569)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (319:319:319) (375:375:375)) + (PORT datab (351:351:351) (420:420:420)) + (PORT datac (747:747:747) (856:856:856)) + (PORT datad (198:198:198) (230:230:230)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (444:444:444) (486:486:486)) + (PORT ena (599:599:599) (646:646:646)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (302:302:302) (352:352:352)) + (PORT datab (330:330:330) (387:387:387)) + (PORT datac (227:227:227) (287:287:287)) + (PORT datad (303:303:303) (347:347:347)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (300:300:300)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datad (312:312:312) (357:357:357)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (995:995:995)) + (PORT datab (304:304:304) (350:350:350)) + (PORT datac (235:235:235) (290:290:290)) + (PORT datad (187:187:187) (218:218:218)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[13\]) + (DELAY + (ABSOLUTE + (PORT datab (490:490:490) (568:568:568)) + (PORT datac (401:401:401) (453:453:453)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (919:919:919) (904:904:904)) + (PORT ena (937:937:937) (1043:1043:1043)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) (TIMINGCHECK (HOLD d (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (1217:1217:1217) (1391:1391:1391)) - (PORT ena (673:673:673) (745:745:745)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~81) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) (DELAY (ABSOLUTE - (PORT dataa (592:592:592) (685:685:685)) - (PORT datab (372:372:372) (450:450:450)) - (PORT datad (461:461:461) (531:531:531)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datab (384:384:384) (458:458:458)) + (PORT datac (206:206:206) (261:261:261)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~82) + (INSTANCE z80_\|address_latch_\|abusz\[15\]) (DELAY (ABSOLUTE - (PORT dataa (321:321:321) (376:376:376)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (317:317:317) (369:369:369)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (454:454:454) (534:534:534)) + (PORT datad (474:474:474) (548:548:548)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) + (INSTANCE z80_\|address_latch_\|Q\[15\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (666:666:666) (766:766:766)) - (PORT ena (753:753:753) (845:845:845)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (666:666:666) (766:766:766)) - (PORT ena (759:759:759) (842:842:842)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (511:511:511) (625:625:625)) - (PORT datab (512:512:512) (620:620:620)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (1196:1196:1196) (1350:1350:1350)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (509:509:509) (608:608:608)) - (PORT datab (669:669:669) (792:792:792)) - (PORT datad (482:482:482) (561:561:561)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (390:390:390)) - (PORT datab (338:338:338) (404:404:404)) - (PORT datac (254:254:254) (292:292:292)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (505:505:505) (602:602:602)) - (PORT datab (349:349:349) (415:415:415)) - (PORT datac (440:440:440) (529:529:529)) - (PORT datad (731:731:731) (840:840:840)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT asdata (618:618:618) (706:706:706)) - (PORT ena (480:480:480) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (266:266:266)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datad (199:199:199) (234:234:234)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (132:132:132) (183:183:183)) - (PORT datab (348:348:348) (415:415:415)) - (PORT datad (347:347:347) (404:404:404)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (230:230:230)) - (PORT datab (388:388:388) (458:458:458)) - (PORT datac (436:436:436) (506:506:506)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[14\]) - (DELAY - (ABSOLUTE - (PORT dataa (499:499:499) (583:583:583)) - (PORT datac (191:191:191) (227:227:227)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[14\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (163:163:163) (188:188:188)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) + (PORT clk (909:909:909) (913:913:913)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (905:905:905)) - (PORT ena (1106:1106:1106) (1248:1248:1248)) + (PORT clrn (919:919:919) (904:904:904)) + (PORT ena (937:937:937) (1043:1043:1043)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -23049,13 +24064,13 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_16) (DELAY (ABSOLUTE - (PORT dataa (627:627:627) (727:727:727)) - (PORT datab (213:213:213) (269:269:269)) - (PORT datac (602:602:602) (688:688:688)) - (PORT datad (345:345:345) (400:400:400)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT dataa (638:638:638) (738:738:738)) + (PORT datab (208:208:208) (269:269:269)) + (PORT datac (360:360:360) (424:424:424)) + (PORT datad (637:637:637) (734:734:734)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -23065,10 +24080,10 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (112:112:112) (144:144:144)) - (PORT datac (127:127:127) (173:173:173)) - (PORT datad (171:171:171) (203:203:203)) + (PORT dataa (105:105:105) (138:138:138)) + (PORT datab (111:111:111) (143:143:143)) + (PORT datac (288:288:288) (347:347:347)) + (PORT datad (92:92:92) (110:110:110)) (IOPATH dataa combout (158:158:158) (173:173:173)) (IOPATH datab combout (160:160:160) (176:176:176)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -23078,13 +24093,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~21) + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~18) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (391:391:391) (461:461:461)) - (PORT datac (443:443:443) (513:513:513)) - (PORT datad (288:288:288) (331:331:331)) + (PORT dataa (852:852:852) (1001:1001:1001)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (234:234:234) (289:289:289)) + (PORT datad (276:276:276) (314:314:314)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (383:383:383)) + (PORT datab (211:211:211) (253:253:253)) + (PORT datac (747:747:747) (856:856:856)) + (PORT datad (295:295:295) (332:332:332)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -23094,15 +24125,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~75) + (INSTANCE z80_\|alu_\|db\[7\]\~19) (DELAY (ABSOLUTE - (PORT dataa (508:508:508) (606:606:606)) - (PORT datab (356:356:356) (422:422:422)) - (PORT datac (452:452:452) (521:521:521)) - (PORT datad (729:729:729) (839:839:839)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (675:675:675) (779:779:779)) + (PORT datab (478:478:478) (554:554:554)) + (PORT datac (305:305:305) (346:346:346)) + (PORT datad (569:569:569) (654:654:654)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -23113,10 +24144,10 @@ (INSTANCE z80_\|alu_\|db\[7\]\~20) (DELAY (ABSOLUTE - (PORT dataa (708:708:708) (836:836:836)) - (PORT datab (543:543:543) (638:638:638)) - (PORT datac (1055:1055:1055) (1229:1229:1229)) - (PORT datad (441:441:441) (512:512:512)) + (PORT dataa (371:371:371) (443:443:443)) + (PORT datab (577:577:577) (664:664:664)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (463:463:463) (544:544:544)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -23124,47 +24155,351 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (139:139:139)) - (PORT datab (138:138:138) (178:178:178)) - (PORT datac (648:648:648) (749:749:749)) - (PORT datad (521:521:521) (607:607:607)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) (DELAY (ABSOLUTE - (PORT dataa (505:505:505) (584:584:584)) - (PORT datab (661:661:661) (793:793:793)) - (PORT datac (497:497:497) (566:566:566)) - (PORT datad (768:768:768) (892:892:892)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (176:176:176)) + (PORT dataa (238:238:238) (284:284:284)) + (PORT datab (1036:1036:1036) (1196:1196:1196)) + (PORT datac (593:593:593) (688:688:688)) + (PORT datad (134:134:134) (174:174:174)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (443:443:443) (515:515:515)) + (PORT datab (196:196:196) (231:231:231)) + (PORT datac (139:139:139) (178:178:178)) + (PORT datad (179:179:179) (202:202:202)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (248:248:248)) + (PORT datab (314:314:314) (369:369:369)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (461:461:461) (529:529:529)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (407:407:407) (424:424:424)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (248:248:248)) + (PORT datab (153:153:153) (196:196:196)) + (PORT datad (460:460:460) (529:529:529)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (459:459:459) (549:549:549)) + (PORT datab (378:378:378) (464:464:464)) + (PORT datad (471:471:471) (548:548:548)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (425:425:425)) + (PORT datab (308:308:308) (360:360:360)) + (PORT datac (137:137:137) (175:175:175)) + (PORT datad (295:295:295) (344:344:344)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (475:475:475) (553:553:553)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (407:407:407) (424:424:424)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (304:304:304) (356:356:356)) + (PORT datab (385:385:385) (472:472:472)) + (PORT datac (540:540:540) (649:649:649)) + (PORT datad (569:569:569) (671:671:671)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (425:425:425)) + (PORT datab (328:328:328) (380:380:380)) + (PORT datac (338:338:338) (403:403:403)) + (PORT datad (191:191:191) (226:226:226)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (893:893:893)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (454:454:454)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (304:304:304)) + (PORT datab (473:473:473) (549:549:549)) + (PORT datac (270:270:270) (309:309:309)) + (PORT datad (217:217:217) (269:269:269)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (281:281:281)) + (PORT datab (591:591:591) (689:689:689)) + (PORT datac (420:420:420) (500:500:500)) + (PORT datad (329:329:329) (386:386:386)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (227:227:227)) + (PORT datab (670:670:670) (793:793:793)) + (PORT datac (370:370:370) (448:448:448)) + (PORT datad (473:473:473) (550:550:550)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT datac (194:194:194) (235:235:235)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (384:384:384)) + (PORT datab (112:112:112) (145:145:145)) + (PORT datac (311:311:311) (362:362:362)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (260:260:260)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datac (105:105:105) (128:128:128)) + (PORT datad (171:171:171) (198:198:198)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) (DELAY (ABSOLUTE - (PORT dataa (490:490:490) (569:569:569)) - (PORT datab (353:353:353) (410:410:410)) - (PORT datac (359:359:359) (429:429:429)) - (PORT datad (361:361:361) (420:420:420)) + (PORT datab (356:356:356) (415:415:415)) + (PORT datac (436:436:436) (502:502:502)) + (PORT datad (355:355:355) (411:411:411)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (518:518:518)) + (PORT datab (116:116:116) (144:144:144)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (152:152:152)) + (PORT datab (363:363:363) (418:418:418)) + (PORT datac (451:451:451) (524:524:524)) + (PORT datad (506:506:506) (590:590:590)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (522:522:522) (618:618:618)) + (PORT datab (115:115:115) (148:148:148)) + (PORT datac (284:284:284) (326:326:326)) + (PORT datad (687:687:687) (802:802:802)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -23177,12 +24512,12 @@ (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) (DELAY (ABSOLUTE - (PORT dataa (874:874:874) (1031:1031:1031)) - (PORT datab (803:803:803) (960:960:960)) - (PORT datac (791:791:791) (910:910:910)) - (PORT datad (459:459:459) (527:527:527)) + (PORT dataa (723:723:723) (826:826:826)) + (PORT datab (1281:1281:1281) (1480:1480:1480)) + (PORT datac (672:672:672) (779:779:779)) + (PORT datad (738:738:738) (836:836:836)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -23193,26 +24528,10 @@ (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) (DELAY (ABSOLUTE - (PORT dataa (312:312:312) (371:371:371)) + (PORT dataa (314:314:314) (361:361:361)) (PORT datab (102:102:102) (130:130:130)) - (PORT datac (102:102:102) (123:123:123)) - (PORT datad (596:596:596) (686:686:686)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (747:747:747)) - (PORT datab (550:550:550) (650:650:650)) - (PORT datac (114:114:114) (141:141:141)) - (PORT datad (1129:1129:1129) (1300:1300:1300)) + (PORT datac (698:698:698) (816:816:816)) + (PORT datad (528:528:528) (611:611:611)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -23225,27 +24544,13 @@ (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) (DELAY (ABSOLUTE - (PORT dataa (112:112:112) (147:147:147)) - (PORT datab (334:334:334) (391:391:391)) - (PORT datac (318:318:318) (373:373:373)) - (PORT datad (335:335:335) (384:384:384)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~2) - (DELAY - (ABSOLUTE - (PORT datab (385:385:385) (461:461:461)) - (PORT datac (738:738:738) (842:842:842)) - (PORT datad (620:620:620) (724:724:724)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (274:274:274) (321:321:321)) + (PORT datab (460:460:460) (531:531:531)) + (PORT datac (282:282:282) (331:331:331)) + (PORT datad (334:334:334) (387:387:387)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -23255,12 +24560,10 @@ (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~4) (DELAY (ABSOLUTE - (PORT dataa (952:952:952) (1100:1100:1100)) - (PORT datab (830:830:830) (971:971:971)) - (PORT datac (1441:1441:1441) (1671:1671:1671)) - (PORT datad (1064:1064:1064) (1245:1245:1245)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (PORT datab (455:455:455) (532:532:532)) + (PORT datac (437:437:437) (490:490:490)) + (PORT datad (659:659:659) (761:761:761)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -23268,13 +24571,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~3) + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~6) (DELAY (ABSOLUTE - (PORT dataa (1091:1091:1091) (1278:1278:1278)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (514:514:514) (598:598:598)) - (PORT datad (91:91:91) (109:109:109)) + (PORT dataa (1008:1008:1008) (1179:1179:1179)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (1055:1055:1055) (1237:1237:1237)) + (PORT datad (916:916:916) (1089:1089:1089)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -23284,12 +24587,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~5) (DELAY (ABSOLUTE - (PORT dataa (340:340:340) (409:409:409)) - (PORT datab (344:344:344) (403:403:403)) - (PORT datad (484:484:484) (562:562:562)) + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (946:946:946) (1091:1091:1091)) + (PORT datac (777:777:777) (894:894:894)) + (PORT datad (1279:1279:1279) (1482:1482:1482)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datad (95:95:95) (115:115:115)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (190:190:190) (188:188:188)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -23302,7 +24621,7 @@ (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) (DELAY (ABSOLUTE - (PORT clk (896:896:896) (902:902:902)) + (PORT clk (911:911:911) (919:919:919)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -23316,13 +24635,13 @@ (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) (DELAY (ABSOLUTE - (PORT dataa (656:656:656) (786:786:786)) - (PORT datab (135:135:135) (186:186:186)) - (PORT datac (749:749:749) (866:866:866)) - (PORT datad (649:649:649) (771:771:771)) + (PORT dataa (148:148:148) (201:201:201)) + (PORT datab (1036:1036:1036) (1196:1196:1196)) + (PORT datac (580:580:580) (677:677:677)) + (PORT datad (135:135:135) (175:175:175)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -23332,23 +24651,226 @@ (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) (DELAY (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datad (643:643:643) (762:762:762)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (145:145:145) (198:198:198)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~5) + (INSTANCE z80_\|alu_\|db_low\[0\]\~21) (DELAY (ABSOLUTE - (PORT datab (115:115:115) (143:143:143)) - (PORT datac (487:487:487) (552:552:552)) - (PORT datad (768:768:768) (891:891:891)) + (PORT datab (507:507:507) (603:603:603)) + (PORT datac (613:613:613) (710:710:710)) + (PORT datad (339:339:339) (392:392:392)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (1014:1014:1014)) + (PORT datab (523:523:523) (610:610:610)) + (PORT datac (555:555:555) (636:636:636)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (415:415:415)) + (PORT datab (154:154:154) (199:199:199)) + (PORT datac (106:106:106) (130:130:130)) + (PORT datad (289:289:289) (338:338:338)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (473:473:473) (551:551:551)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (913:913:913) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (407:407:407) (424:424:424)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (306:306:306)) + (PORT datab (893:893:893) (1054:1054:1054)) + (PORT datac (474:474:474) (552:552:552)) + (PORT datad (314:314:314) (381:381:381)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (346:346:346) (377:377:377)) + (PORT ena (805:805:805) (893:893:893)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (303:303:303)) + (PORT datab (308:308:308) (360:360:360)) + (PORT datac (475:475:475) (562:562:562)) + (PORT datad (130:130:130) (159:159:159)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (468:468:468) (555:555:555)) + (PORT datab (185:185:185) (221:221:221)) + (PORT datad (328:328:328) (378:378:378)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (443:443:443) (514:514:514)) + (PORT datab (350:350:350) (415:415:415)) + (PORT datac (306:306:306) (352:352:352)) + (PORT datad (178:178:178) (201:201:201)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (595:595:595)) + (PORT datab (607:607:607) (728:728:728)) + (PORT datac (311:311:311) (375:375:375)) + (PORT datad (340:340:340) (396:396:396)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (429:429:429)) + (PORT datab (555:555:555) (653:653:653)) + (PORT datac (336:336:336) (401:401:401)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (893:893:893)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (454:454:454)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (425:425:425)) + (PORT datab (352:352:352) (415:415:415)) + (PORT datac (310:310:310) (351:351:351)) + (PORT datad (540:540:540) (628:628:628)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -23357,27 +24879,639 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~6) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~5) (DELAY (ABSOLUTE - (PORT dataa (213:213:213) (254:254:254)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (483:483:483) (561:561:561)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datac (337:337:337) (401:401:401)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (893:893:893)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (454:454:454)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (305:305:305)) + (PORT datab (306:306:306) (363:363:363)) + (PORT datac (233:233:233) (296:296:296)) + (PORT datad (451:451:451) (522:522:522)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~4) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (295:295:295)) - (PORT datab (647:647:647) (748:748:748)) - (PORT datac (321:321:321) (379:379:379)) - (PORT datad (368:368:368) (435:435:435)) + (PORT dataa (135:135:135) (174:174:174)) + (PORT datab (286:286:286) (329:329:329)) + (PORT datac (293:293:293) (345:345:345)) + (PORT datad (590:590:590) (679:679:679)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) + (DELAY + (ABSOLUTE + (PORT dataa (464:464:464) (541:541:541)) + (PORT datab (586:586:586) (668:668:668)) + (PORT datac (434:434:434) (500:500:500)) + (PORT datad (419:419:419) (477:477:477)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~36) + (DELAY + (ABSOLUTE + (PORT datab (118:118:118) (153:153:153)) + (PORT datac (114:114:114) (141:141:141)) + (PORT datad (451:451:451) (520:520:520)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~35) + (DELAY + (ABSOLUTE + (PORT dataa (112:112:112) (146:146:146)) + (PORT datab (120:120:120) (155:155:155)) + (PORT datac (116:116:116) (143:143:143)) + (PORT datad (451:451:451) (520:520:520)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~13) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (955:955:955)) + (PORT datab (795:795:795) (918:918:918)) + (PORT datac (1012:1012:1012) (1144:1144:1144)) + (PORT datad (735:735:735) (832:832:832)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~14) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (697:697:697)) + (PORT datab (756:756:756) (881:881:881)) + (PORT datac (430:430:430) (491:491:491)) + (PORT datad (727:727:727) (829:829:829)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1083:1083:1083) (1265:1265:1265)) + (PORT datab (110:110:110) (142:142:142)) + (PORT datac (1090:1090:1090) (1265:1265:1265)) + (PORT datad (914:914:914) (1045:1045:1045)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~16) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (704:704:704)) + (PORT datab (187:187:187) (226:226:226)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (456:456:456) (522:522:522)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~17) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (116:116:116) (144:144:144)) + (PORT datac (269:269:269) (308:308:308)) + (PORT datad (310:310:310) (358:358:358)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) + (DELAY + (ABSOLUTE + (PORT datab (993:993:993) (1133:1133:1133)) + (PORT datac (651:651:651) (747:747:747)) + (PORT datad (791:791:791) (905:905:905)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) + (DELAY + (ABSOLUTE + (PORT dataa (149:149:149) (192:192:192)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (141:141:141) (181:181:181)) + (PORT datad (664:664:664) (763:763:763)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1240:1240:1240) (1467:1467:1467)) + (PORT datab (893:893:893) (1057:1057:1057)) + (PORT datac (981:981:981) (1155:1155:1155)) + (PORT datad (462:462:462) (535:535:535)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (133:133:133)) + (PORT datab (1060:1060:1060) (1233:1233:1233)) + (PORT datac (328:328:328) (384:384:384)) + (PORT datad (517:517:517) (606:606:606)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1008:1008:1008) (1180:1180:1180)) + (PORT datab (785:785:785) (892:892:892)) + (PORT datac (782:782:782) (903:903:903)) + (PORT datad (1334:1334:1334) (1550:1550:1550)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (1007:1007:1007)) + (PORT datab (672:672:672) (775:775:775)) + (PORT datac (780:780:780) (900:900:900)) + (PORT datad (918:918:918) (1053:1053:1053)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) + (DELAY + (ABSOLUTE + (PORT dataa (800:800:800) (922:922:922)) + (PORT datab (374:374:374) (448:448:448)) + (PORT datac (653:653:653) (755:755:755)) + (PORT datad (932:932:932) (1070:1070:1070)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (404:404:404)) + (PORT datab (1134:1134:1134) (1320:1320:1320)) + (PORT datac (871:871:871) (1027:1027:1027)) + (PORT datad (1334:1334:1334) (1550:1550:1550)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (1010:1010:1010)) + (PORT datab (368:368:368) (442:442:442)) + (PORT datac (879:879:879) (1020:1020:1020)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (373:373:373) (447:447:447)) + (PORT datac (1129:1129:1129) (1286:1286:1286)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) + (DELAY + (ABSOLUTE + (PORT dataa (174:174:174) (215:215:215)) + (PORT datab (189:189:189) (228:228:228)) + (PORT datac (163:163:163) (197:197:197)) + (PORT datad (491:491:491) (564:564:564)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~37) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (419:419:419)) + (PORT datab (341:341:341) (408:408:408)) + (PORT datac (646:646:646) (743:743:743)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) + (DELAY + (ABSOLUTE + (PORT dataa (503:503:503) (597:597:597)) + (PORT datab (114:114:114) (143:143:143)) + (PORT datac (746:746:746) (862:862:862)) + (PORT datad (332:332:332) (387:387:387)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (421:421:421)) + (PORT datab (112:112:112) (144:144:144)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (642:642:642) (738:738:738)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (397:397:397)) + (PORT datab (102:102:102) (129:129:129)) + (PORT datac (314:314:314) (361:361:361)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (955:955:955)) + (PORT datab (795:795:795) (918:918:918)) + (PORT datac (564:564:564) (650:650:650)) + (PORT datad (734:734:734) (832:832:832)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (500:500:500) (586:586:586)) + (PORT datac (514:514:514) (596:596:596)) + (PORT datad (1268:1268:1268) (1457:1457:1457)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) + (DELAY + (ABSOLUTE + (PORT dataa (739:739:739) (875:875:875)) + (PORT datab (713:713:713) (832:832:832)) + (PORT datac (515:515:515) (598:598:598)) + (PORT datad (644:644:644) (745:745:745)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) + (DELAY + (ABSOLUTE + (PORT dataa (790:790:790) (895:895:895)) + (PORT datab (551:551:551) (639:639:639)) + (PORT datac (196:196:196) (229:229:229)) + (PORT datad (88:88:88) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (228:228:228)) + (PORT datab (101:101:101) (130:130:130)) + (PORT datac (271:271:271) (304:304:304)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) + (DELAY + (ABSOLUTE + (PORT dataa (466:466:466) (540:540:540)) + (PORT datab (347:347:347) (406:406:406)) + (PORT datac (173:173:173) (208:208:208)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) + (DELAY + (ABSOLUTE + (PORT dataa (458:458:458) (528:528:528)) + (PORT datab (348:348:348) (408:408:408)) + (PORT datac (441:441:441) (496:496:496)) + (PORT datad (704:704:704) (823:823:823)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (421:421:421)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (288:288:288) (334:334:334)) + (PORT datac (96:96:96) (120:120:120)) + (PORT datad (316:316:316) (366:366:366)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (318:318:318)) + (PORT datab (894:894:894) (1054:1054:1054)) + (PORT datac (556:556:556) (666:666:666)) + (PORT datad (463:463:463) (540:540:540)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (480:480:480)) + (PORT datac (108:108:108) (132:132:132)) + (PORT datad (106:106:106) (125:125:125)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (435:435:435)) + (PORT datab (768:768:768) (882:882:882)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (404:404:404)) + (PORT datab (222:222:222) (276:276:276)) + (PORT datac (477:477:477) (564:564:564)) + (PORT datad (132:132:132) (162:162:162)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (467:467:467) (553:553:553)) + (PORT datab (722:722:722) (829:829:829)) + (PORT datac (453:453:453) (538:538:538)) + (PORT datad (430:430:430) (496:496:496)) (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -23387,45 +25521,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~27) + (INSTANCE z80_\|alu_\|db_high\[0\]\~25) (DELAY (ABSOLUTE - (PORT dataa (647:647:647) (752:752:752)) - (PORT datab (152:152:152) (195:195:195)) - (PORT datac (135:135:135) (174:174:174)) - (PORT datad (140:140:140) (171:171:171)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (175:175:175) (216:216:216)) - (PORT datab (433:433:433) (505:505:505)) - (PORT datac (258:258:258) (289:289:289)) - (PORT datad (604:604:604) (695:695:695)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (316:316:316) (378:378:378)) - (PORT datab (549:549:549) (648:648:648)) - (PORT datac (311:311:311) (363:363:363)) - (PORT datad (121:121:121) (151:151:151)) + (PORT dataa (468:468:468) (554:554:554)) + (PORT datab (183:183:183) (221:221:221)) + (PORT datac (305:305:305) (350:350:350)) + (PORT datad (340:340:340) (394:394:394)) (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -23435,28 +25537,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~4) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) (DELAY (ABSOLUTE - (PORT dataa (192:192:192) (230:230:230)) - (PORT datab (493:493:493) (573:573:573)) - (PORT datac (627:627:627) (727:727:727)) - (PORT datad (373:373:373) (444:444:444)) + (PORT dataa (356:356:356) (415:415:415)) + (PORT datab (155:155:155) (199:199:199)) + (PORT datad (459:459:459) (527:527:527)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[3\]) + (INSTANCE z80_\|alu_\|op1_high\[0\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (901:901:901)) + (PORT clk (913:913:913) (900:900:900)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (405:405:405) (422:422:422)) + (PORT ena (422:422:422) (450:450:450)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -23467,13 +25567,57 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~9) + (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (367:367:367) (440:440:440)) - (PORT datab (659:659:659) (762:762:762)) - (PORT datac (332:332:332) (403:403:403)) - (PORT datad (370:370:370) (438:438:438)) + (PORT datab (583:583:583) (691:691:691)) + (PORT datac (556:556:556) (666:666:666)) + (PORT datad (314:314:314) (381:381:381)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (304:304:304)) + (PORT datab (306:306:306) (364:364:364)) + (PORT datac (233:233:233) (296:296:296)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (141:141:141)) + (PORT datab (468:468:468) (543:543:543)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (319:319:319) (368:368:368)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (134:134:134) (172:172:172)) + (PORT datab (136:136:136) (167:167:167)) + (PORT datac (272:272:272) (309:309:309)) + (PORT datad (95:95:95) (114:114:114)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -23483,211 +25627,75 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) (DELAY (ABSOLUTE - (PORT datab (154:154:154) (199:199:199)) - (PORT datad (134:134:134) (165:165:165)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (PORT dataa (219:219:219) (263:263:263)) + (PORT datab (201:201:201) (238:238:238)) + (PORT datac (195:195:195) (229:229:229)) + (PORT datad (173:173:173) (201:201:201)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~10) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) (DELAY (ABSOLUTE - (PORT dataa (153:153:153) (198:198:198)) - (PORT datab (321:321:321) (379:379:379)) - (PORT datac (630:630:630) (728:728:728)) - (PORT datad (91:91:91) (108:108:108)) + (PORT dataa (191:191:191) (233:233:233)) + (PORT datab (114:114:114) (146:146:146)) + (PORT datac (314:314:314) (365:365:365)) + (PORT datad (93:93:93) (111:111:111)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (324:324:324) (381:381:381)) + (PORT datac (96:96:96) (122:122:122)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[3\]) + (INSTANCE z80_\|alu_\|result_lo\[2\]) (DELAY (ABSOLUTE - (PORT clk (901:901:901) (909:909:909)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (676:676:676) (740:740:740)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (293:293:293) (312:312:312)) + (PORT ena (805:805:805) (893:893:893)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~7) + (INSTANCE z80_\|alu_\|db_low\[2\]\~11) (DELAY (ABSOLUTE - (PORT dataa (523:523:523) (609:609:609)) - (PORT datac (914:914:914) (1063:1063:1063)) - (PORT datad (777:777:777) (877:877:877)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (693:693:693)) - (PORT datab (615:615:615) (716:716:716)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (131:131:131) (159:159:159)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (270:270:270) (311:311:311)) - (PORT datab (466:466:466) (560:560:560)) - (PORT datac (520:520:520) (618:618:618)) - (PORT datad (316:316:316) (367:367:367)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (761:761:761)) - (PORT datab (328:328:328) (388:388:388)) - (PORT datac (102:102:102) (129:129:129)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (417:417:417)) - (PORT datab (503:503:503) (584:584:584)) - (PORT datac (459:459:459) (534:534:534)) - (PORT datad (647:647:647) (738:738:738)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (405:405:405)) - (PORT datab (539:539:539) (632:632:632)) - (PORT datac (635:635:635) (724:724:724)) - (PORT datad (120:120:120) (151:151:151)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) - (DELAY - (ABSOLUTE - (PORT dataa (122:122:122) (155:155:155)) - (PORT datab (817:817:817) (945:945:945)) - (PORT datac (620:620:620) (709:709:709)) - (PORT datad (92:92:92) (111:111:111)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~49) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (763:763:763)) - (PORT datab (510:510:510) (590:590:590)) - (PORT datac (275:275:275) (319:319:319)) - (PORT datad (447:447:447) (511:511:511)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (820:820:820) (957:957:957)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (127:127:127) (154:154:154)) - (PORT datad (782:782:782) (893:893:893)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (402:402:402)) - (PORT datab (337:337:337) (394:394:394)) - (PORT datac (351:351:351) (419:419:419)) - (PORT datad (369:369:369) (431:431:431)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) - (DELAY - (ABSOLUTE - (PORT datab (334:334:334) (395:395:395)) - (PORT datad (467:467:467) (556:556:556)) + (PORT datab (199:199:199) (255:255:255)) + (PORT datad (447:447:447) (518:518:518)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -23695,91 +25703,181 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla69M2T2_3) + (INSTANCE z80_\|alu_\|db_low\[2\]\~12) (DELAY (ABSOLUTE - (PORT dataa (341:341:341) (398:398:398)) - (PORT datab (1272:1272:1272) (1479:1479:1479)) - (PORT datac (1155:1155:1155) (1344:1344:1344)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (491:491:491) (580:580:580)) + (PORT datab (383:383:383) (469:469:469)) + (PORT datac (872:872:872) (1028:1028:1028)) + (PORT datad (217:217:217) (269:269:269)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (247:247:247)) - (PORT datab (922:922:922) (1054:1054:1054)) - (PORT datac (453:453:453) (515:515:515)) - (PORT datad (94:94:94) (114:114:114)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (559:559:559)) - (PORT datab (185:185:185) (226:226:226)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (97:97:97) (117:117:117)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (517:517:517) (607:607:607)) - (PORT datab (369:369:369) (432:432:432)) - (PORT datac (302:302:302) (347:347:347)) - (PORT datad (332:332:332) (387:387:387)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_xf) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) (DELAY (ABSOLUTE - (PORT clk (900:900:900) (905:905:905)) + (PORT dataa (238:238:238) (298:298:298)) + (PORT datad (317:317:317) (374:374:374)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (435:435:435) (514:514:514)) + (PORT datab (613:613:613) (714:714:714)) + (PORT datac (201:201:201) (240:240:240)) + (PORT datad (497:497:497) (568:568:568)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (422:422:422) (488:488:488)) + (PORT datab (357:357:357) (417:417:417)) + (PORT datac (175:175:175) (211:211:211)) + (PORT datad (166:166:166) (195:195:195)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (687:687:687)) + (PORT datab (477:477:477) (554:554:554)) + (PORT datac (583:583:583) (682:682:682)) + (PORT datad (549:549:549) (643:643:643)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (420:420:420)) + (PORT datab (576:576:576) (664:664:664)) + (PORT datac (269:269:269) (308:308:308)) + (PORT datad (358:358:358) (416:416:416)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (398:398:398)) + (PORT datab (357:357:357) (435:435:435)) + (PORT datac (706:706:706) (808:808:808)) + (PORT datad (631:631:631) (721:721:721)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (618:618:618)) + (PORT datab (616:616:616) (708:708:708)) + (PORT datad (576:576:576) (651:651:651)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_hf2) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (448:448:448)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~33) + (INSTANCE z80_\|alu_control_\|out\[6\]\~0) (DELAY (ABSOLUTE - (PORT datab (515:515:515) (602:602:602)) - (PORT datac (354:354:354) (422:422:422)) - (PORT datad (355:355:355) (423:423:423)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT datab (201:201:201) (259:259:259)) + (PORT datac (199:199:199) (244:244:244)) + (PORT datad (201:201:201) (251:251:251)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (639:639:639)) + (PORT datab (1280:1280:1280) (1486:1486:1486)) + (PORT datad (1231:1231:1231) (1469:1469:1469)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (180:180:180)) + (PORT datab (333:333:333) (394:394:394)) + (PORT datac (430:430:430) (492:492:492)) + (PORT datad (784:784:784) (883:883:883)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -23790,12 +25888,12 @@ (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) (DELAY (ABSOLUTE - (PORT dataa (178:178:178) (215:215:215)) - (PORT datab (110:110:110) (142:142:142)) - (PORT datac (92:92:92) (115:115:115)) - (PORT datad (354:354:354) (414:414:414)) + (PORT dataa (108:108:108) (141:141:141)) + (PORT datab (106:106:106) (136:136:136)) + (PORT datac (781:781:781) (895:895:895)) + (PORT datad (96:96:96) (116:116:116)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -23806,13 +25904,13 @@ (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) (DELAY (ABSOLUTE - (PORT dataa (471:471:471) (542:542:542)) - (PORT datab (561:561:561) (649:649:649)) - (PORT datac (813:813:813) (945:945:945)) - (PORT datad (636:636:636) (725:725:725)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (651:651:651) (764:764:764)) + (PORT datab (513:513:513) (599:599:599)) + (PORT datac (668:668:668) (771:771:771)) + (PORT datad (655:655:655) (753:753:753)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -23822,10 +25920,10 @@ (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) (DELAY (ABSOLUTE - (PORT dataa (348:348:348) (419:419:419)) - (PORT datab (510:510:510) (596:596:596)) - (PORT datac (831:831:831) (950:950:950)) - (PORT datad (625:625:625) (717:717:717)) + (PORT dataa (153:153:153) (197:197:197)) + (PORT datab (988:988:988) (1126:1126:1126)) + (PORT datac (136:136:136) (174:174:174)) + (PORT datad (92:92:92) (111:111:111)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -23838,10 +25936,10 @@ (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) (DELAY (ABSOLUTE - (PORT dataa (326:326:326) (384:384:384)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datac (479:479:479) (558:558:558)) - (PORT datad (102:102:102) (119:119:119)) + (PORT dataa (335:335:335) (395:395:395)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (597:597:597) (676:676:676)) + (PORT datad (96:96:96) (116:116:116)) (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -23851,45 +25949,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) + (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~1) (DELAY (ABSOLUTE - (PORT datab (926:926:926) (1053:1053:1053)) - (PORT datac (804:804:804) (935:935:935)) - (PORT datad (645:645:645) (743:743:743)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (205:205:205) (284:284:284)) - (PORT datab (687:687:687) (799:799:799)) - (PORT datac (631:631:631) (721:721:721)) - (PORT datad (503:503:503) (574:574:574)) + (PORT dataa (461:461:461) (539:539:539)) + (PORT datab (501:501:501) (581:581:581)) + (PORT datac (444:444:444) (515:515:515)) + (PORT datad (445:445:445) (505:505:505)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~34) + (INSTANCE z80_\|alu_control_\|db\[2\]\~29) (DELAY (ABSOLUTE - (PORT dataa (468:468:468) (552:552:552)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (476:476:476) (549:549:549)) - (PORT datad (342:342:342) (397:397:397)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) + (PORT dataa (475:475:475) (558:558:558)) + (PORT datab (104:104:104) (132:132:132)) + (PORT datac (345:345:345) (408:408:408)) + (PORT datad (332:332:332) (384:384:384)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -23897,28 +25981,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~35) + (INSTANCE z80_\|alu_control_\|db\[2\]\~30) (DELAY (ABSOLUTE - (PORT dataa (331:331:331) (391:391:391)) - (PORT datab (133:133:133) (168:168:168)) - (PORT datac (627:627:627) (722:722:722)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (453:453:453) (521:521:521)) + (PORT datab (105:105:105) (135:135:135)) + (PORT datac (480:480:480) (562:562:562)) + (PORT datad (93:93:93) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) (DELAY (ABSOLUTE - (PORT dataa (235:235:235) (299:299:299)) - (PORT datab (630:630:630) (725:725:725)) - (PORT datad (805:805:805) (920:920:920)) + (PORT dataa (146:146:146) (188:188:188)) + (PORT datab (633:633:633) (738:738:738)) + (PORT datad (687:687:687) (797:797:797)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -23926,58 +26010,14 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (274:274:274)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (881:881:881) (999:999:999)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) - (DELAY - (ABSOLUTE - (PORT datab (182:182:182) (224:224:224)) - (PORT datac (419:419:419) (476:476:476)) - (PORT datad (164:164:164) (193:193:193)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (527:527:527) (588:588:588)) - (PORT ena (756:756:756) (816:816:816)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (527:527:527) (588:588:588)) - (PORT ena (915:915:915) (1002:1002:1002)) + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (287:287:287) (310:310:310)) + (PORT ena (662:662:662) (720:720:720)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -23988,137 +26028,22 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (134:134:134) (187:187:187)) - (PORT datab (546:546:546) (643:643:643)) - (PORT datad (470:470:470) (544:544:544)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT datad (505:505:505) (591:591:591)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (451:451:451) (486:486:486)) - (PORT ena (419:419:419) (435:435:435)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (451:451:451) (486:486:486)) - (PORT ena (432:432:432) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (131:131:131) (182:182:182)) - (PORT datab (137:137:137) (176:176:176)) - (PORT datad (121:121:121) (146:146:146)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (451:451:451) (520:520:520)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (327:327:327) (382:382:382)) - (PORT datad (335:335:335) (393:393:393)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (464:464:464) (542:542:542)) - (PORT datab (328:328:328) (383:383:383)) - (PORT datac (172:172:172) (202:202:202)) - (PORT datad (603:603:603) (692:692:692)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (515:515:515) (573:573:573)) - (PORT ena (636:636:636) (682:682:682)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (724:724:724) (825:825:825)) - (PORT datab (383:383:383) (454:454:454)) - (PORT datad (659:659:659) (768:768:768)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) + (PORT clk (914:914:914) (922:922:922)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (746:746:746)) + (PORT ena (435:435:435) (462:462:462)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -24129,13 +26054,180 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) (DELAY (ABSOLUTE - (PORT dataa (336:336:336) (401:401:401)) - (PORT datac (386:386:386) (461:461:461)) - (PORT datad (119:119:119) (157:157:157)) + (PORT dataa (669:669:669) (809:809:809)) + (PORT datab (385:385:385) (452:452:452)) + (PORT datad (477:477:477) (564:564:564)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (355:355:355) (410:410:410)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (287:287:287) (309:309:309)) + (PORT ena (684:684:684) (755:755:755)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (469:469:469)) + (PORT datab (402:402:402) (476:476:476)) + (PORT datad (553:553:553) (633:633:633)) (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (412:412:412)) + (PORT datab (336:336:336) (393:393:393)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (193:193:193) (233:233:233)) + (PORT datab (337:337:337) (395:395:395)) + (PORT datac (157:157:157) (184:184:184)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (145:145:145)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (441:441:441) (511:511:511)) + (PORT datad (618:618:618) (714:714:714)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (642:642:642) (715:715:715)) + (PORT ena (421:421:421) (441:441:441)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (678:678:678)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datad (608:608:608) (701:701:701)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (652:652:652) (711:711:711)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (331:331:331) (386:386:386)) + (PORT datac (352:352:352) (425:425:425)) + (PORT datad (118:118:118) (156:156:156)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -24143,29 +26235,59 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) (DELAY (ABSOLUTE - (PORT dataa (193:193:193) (230:230:230)) - (PORT datab (526:526:526) (617:617:617)) - (PORT datac (376:376:376) (448:448:448)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT dataa (216:216:216) (259:259:259)) + (PORT datab (337:337:337) (397:397:397)) + (PORT datac (664:664:664) (774:774:774)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (689:689:689)) + (PORT datad (482:482:482) (555:555:555)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (928:928:928) (910:910:910)) + (PORT ena (1097:1097:1097) (1218:1218:1218)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|address_latch_\|abusz\[3\]) (DELAY (ABSOLUTE - (PORT datab (129:129:129) (162:162:162)) - (PORT datac (283:283:283) (331:331:331)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (721:721:721) (837:837:837)) + (PORT datad (191:191:191) (224:224:224)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -24174,10 +26296,10 @@ (INSTANCE z80_\|address_latch_\|Q\[3\]) (DELAY (ABSOLUTE - (PORT clk (920:920:920) (928:928:928)) - (PORT asdata (447:447:447) (488:488:488)) - (PORT clrn (927:927:927) (909:909:909)) - (PORT ena (1168:1168:1168) (1321:1321:1321)) + (PORT clk (913:913:913) (922:922:922)) + (PORT asdata (500:500:500) (549:549:549)) + (PORT clrn (926:926:926) (909:909:909)) + (PORT ena (1097:1097:1097) (1218:1218:1218)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -24187,540 +26309,62 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~4) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (245:245:245)) - (PORT datab (634:634:634) (730:730:730)) - (PORT datac (543:543:543) (635:635:635)) - (PORT datad (132:132:132) (170:170:170)) - (IOPATH dataa combout (181:181:181) (180:180:180)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) (DELAY (ABSOLUTE - (PORT dataa (179:179:179) (223:223:223)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (177:177:177) (209:209:209)) - (PORT datad (165:165:165) (195:195:195)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (143:143:143) (194:194:194)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (659:659:659) (731:731:731)) - (PORT ena (419:419:419) (435:435:435)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (655:655:655) (727:727:727)) - (PORT ena (432:432:432) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (132:132:132) (183:183:183)) - (PORT datab (137:137:137) (175:175:175)) - (PORT datad (122:122:122) (147:147:147)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (326:326:326) (387:387:387)) - (PORT datab (627:627:627) (721:721:721)) - (PORT datad (336:336:336) (393:393:393)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (634:634:634) (705:705:705)) - (PORT ena (422:422:422) (454:454:454)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (638:638:638) (710:710:710)) - (PORT ena (669:669:669) (725:725:725)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (273:273:273)) - (PORT datab (314:314:314) (372:372:372)) - (PORT datad (119:119:119) (157:157:157)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (794:794:794) (880:880:880)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (492:492:492) (533:533:533)) - (PORT ena (631:631:631) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (493:493:493) (533:533:533)) - (PORT ena (660:660:660) (723:723:723)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (294:294:294)) - (PORT datab (359:359:359) (425:425:425)) - (PORT datad (117:117:117) (152:152:152)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (403:403:403)) - (PORT datab (493:493:493) (580:580:580)) - (PORT datac (114:114:114) (155:155:155)) - (PORT datad (170:170:170) (201:201:201)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (531:531:531) (590:590:590)) - (PORT ena (915:915:915) (1002:1002:1002)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (534:534:534) (593:593:593)) - (PORT ena (756:756:756) (816:816:816)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (487:487:487) (572:572:572)) - (PORT datab (537:537:537) (632:632:632)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (523:523:523) (580:580:580)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (523:523:523) (579:579:579)) - (PORT ena (644:644:644) (698:698:698)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (431:431:431)) - (PORT datab (209:209:209) (253:253:253)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (453:453:453) (485:485:485)) - (PORT ena (736:736:736) (793:793:793)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (273:273:273) (317:317:317)) - (PORT datad (433:433:433) (505:505:505)) + (PORT dataa (344:344:344) (407:407:407)) + (PORT datab (315:315:315) (370:370:370)) + (PORT datac (313:313:313) (380:380:380)) + (PORT datad (358:358:358) (433:433:433)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (174:174:174) (215:215:215)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (544:544:544) (619:619:619)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (463:463:463) (533:533:533)) - (PORT datac (614:614:614) (701:701:701)) - (PORT datad (635:635:635) (735:735:735)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (729:729:729) (807:807:807)) - (PORT ena (636:636:636) (682:682:682)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (479:479:479) (546:546:546)) - (PORT datab (681:681:681) (797:797:797)) - (PORT datad (365:365:365) (428:428:428)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (746:746:746)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (349:349:349) (408:408:408)) - (PORT datac (385:385:385) (459:459:459)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (190:190:190) (181:181:181)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (230:230:230)) - (PORT datab (527:527:527) (619:619:619)) - (PORT datac (375:375:375) (448:448:448)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[4\]) - (DELAY - (ABSOLUTE - (PORT datab (126:126:126) (159:159:159)) - (PORT datad (272:272:272) (314:314:314)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (928:928:928)) - (PORT asdata (441:441:441) (473:473:473)) - (PORT clrn (927:927:927) (909:909:909)) - (PORT ena (1168:1168:1168) (1321:1321:1321)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (721:721:721)) - (PORT datab (546:546:546) (639:639:639)) - (PORT datad (106:106:106) (124:124:124)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) (DELAY (ABSOLUTE - (PORT dataa (362:362:362) (439:439:439)) - (PORT datab (642:642:642) (741:741:741)) - (PORT datac (338:338:338) (393:393:393)) - (IOPATH dataa combout (195:195:195) (203:203:203)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT dataa (224:224:224) (293:293:293)) + (PORT datab (317:317:317) (372:372:372)) + (PORT datac (316:316:316) (375:375:375)) + (PORT datad (107:107:107) (125:125:125)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (458:458:458) (495:495:495)) - (PORT ena (756:756:756) (816:816:816)) + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (640:640:640) (702:702:702)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (279:279:279) (298:298:298)) + (PORT ena (650:650:650) (698:698:698)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -24734,40 +26378,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (458:458:458) (495:495:495)) - (PORT ena (915:915:915) (1002:1002:1002)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (131:131:131) (182:182:182)) - (PORT datab (541:541:541) (636:636:636)) - (PORT datad (470:470:470) (544:544:544)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (359:359:359) (387:387:387)) - (PORT ena (781:781:781) (840:840:840)) + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (490:490:490) (547:547:547)) + (PORT ena (754:754:754) (814:814:814)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -24778,12 +26391,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (359:359:359) (387:387:387)) - (PORT ena (662:662:662) (720:720:720)) + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (491:491:491) (547:547:547)) + (PORT ena (434:434:434) (466:466:466)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -24797,56 +26410,9 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) (DELAY (ABSOLUTE - (PORT dataa (613:613:613) (704:704:704)) - (PORT datab (129:129:129) (176:176:176)) - (PORT datad (358:358:358) (416:416:416)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (764:764:764) (851:851:851)) - (PORT ena (794:794:794) (880:880:880)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (774:774:774) (864:864:864)) - (PORT ena (631:631:631) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (284:284:284)) - (PORT datab (625:625:625) (718:718:718)) - (PORT datad (334:334:334) (382:382:382)) + (PORT dataa (137:137:137) (181:181:181)) + (PORT datab (590:590:590) (680:680:680)) + (PORT datad (186:186:186) (231:231:231)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -24854,13 +26420,47 @@ ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT asdata (999:999:999) (1123:1123:1123)) + (PORT ena (495:495:495) (537:537:537)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT asdata (999:999:999) (1122:1122:1122)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) (DELAY (ABSOLUTE - (PORT datab (492:492:492) (579:579:579)) - (PORT datad (171:171:171) (203:203:203)) + (PORT dataa (132:132:132) (183:183:183)) + (PORT datab (132:132:132) (167:167:167)) + (PORT datad (113:113:113) (134:134:134)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -24869,28 +26469,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (638:638:638) (711:711:711)) - (PORT ena (422:422:422) (454:454:454)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (637:637:637) (710:710:710)) - (PORT ena (669:669:669) (725:725:725)) + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (990:990:990) (1113:1113:1113)) + (PORT ena (666:666:666) (729:729:729)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -24904,9 +26488,9 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) (DELAY (ABSOLUTE - (PORT dataa (217:217:217) (273:273:273)) - (PORT datab (315:315:315) (374:374:374)) - (PORT datad (117:117:117) (154:154:154)) + (PORT dataa (663:663:663) (776:776:776)) + (PORT datab (373:373:373) (442:442:442)) + (PORT datad (454:454:454) (512:512:512)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -24916,12 +26500,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (789:789:789) (871:871:871)) - (PORT ena (644:644:644) (698:698:698)) + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (990:990:990) (1112:1112:1112)) + (PORT ena (603:603:603) (650:650:650)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -24932,11 +26516,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]\~feeder) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) (DELAY (ABSOLUTE - (PORT datad (329:329:329) (377:377:377)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT dataa (217:217:217) (265:265:265)) + (PORT datab (101:101:101) (129:129:129)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) ) ) ) @@ -24945,50 +26532,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) + (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (426:426:426)) - (PORT datab (202:202:202) (245:245:245)) - (PORT datad (115:115:115) (152:152:152)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (461:461:461) (525:525:525)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (736:736:736) (793:793:793)) + (PORT ena (931:931:931) (1043:1043:1043)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -24999,12 +26545,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (774:774:774) (864:864:864)) - (PORT ena (660:660:660) (723:723:723)) + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (575:575:575) (635:635:635)) + (PORT ena (409:409:409) (429:429:429)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -25018,70 +26564,40 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) (DELAY (ABSOLUTE - (PORT dataa (300:300:300) (366:366:366)) - (PORT datab (441:441:441) (518:518:518)) - (PORT datad (347:347:347) (405:405:405)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (142:142:142) (182:182:182)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datad (805:805:805) (949:949:949)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT dataa (343:343:343) (401:401:401)) - (PORT datab (609:609:609) (697:697:697)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (320:320:320) (370:370:370)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (520:520:520) (576:576:576)) + (PORT ena (594:594:594) (642:642:642)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (226:226:226)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (419:419:419)) - (PORT datab (522:522:522) (603:603:603)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (878:878:878) (998:998:998)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (650:650:650) (724:724:724)) - (PORT ena (636:636:636) (682:682:682)) + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (520:520:520) (575:575:575)) + (PORT ena (665:665:665) (725:725:725)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -25092,13 +26608,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) (DELAY (ABSOLUTE - (PORT dataa (649:649:649) (740:740:740)) - (PORT datab (681:681:681) (798:798:798)) - (PORT datad (365:365:365) (428:428:428)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (329:329:329) (389:389:389)) + (PORT datab (514:514:514) (604:604:604)) + (PORT datad (116:116:116) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -25106,31 +26622,123 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (419:419:419) (435:435:435)) + (PORT dataa (442:442:442) (509:509:509)) + (PORT datab (351:351:351) (411:411:411)) + (PORT datac (334:334:334) (388:388:388)) + (PORT datad (326:326:326) (382:382:382)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (654:654:654) (728:728:728)) + (PORT ena (473:473:473) (498:498:498)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (653:653:653) (728:728:728)) + (PORT ena (503:503:503) (543:543:543)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (267:267:267)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datad (222:222:222) (262:262:262)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (429:429:429)) + (PORT datab (454:454:454) (530:530:530)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (467:467:467) (540:540:540)) + (PORT datab (205:205:205) (245:245:245)) + (PORT datac (627:627:627) (732:732:732)) + (PORT datad (372:372:372) (436:436:436)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (944:944:944)) + (PORT datab (363:363:363) (428:428:428)) + (PORT datad (169:169:169) (195:195:195)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~17) (DELAY (ABSOLUTE - (PORT dataa (120:120:120) (153:153:153)) - (PORT datac (333:333:333) (385:385:385)) - (PORT datad (119:119:119) (157:157:157)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (298:298:298) (364:364:364)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datad (327:327:327) (382:382:382)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -25140,13 +26748,13 @@ (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~18) (DELAY (ABSOLUTE - (PORT dataa (348:348:348) (404:404:404)) - (PORT datab (715:715:715) (816:816:816)) - (PORT datac (101:101:101) (121:121:121)) - (PORT datad (92:92:92) (110:110:110)) + (PORT dataa (465:465:465) (528:528:528)) + (PORT datab (101:101:101) (130:130:130)) + (PORT datac (669:669:669) (778:778:778)) + (PORT datad (116:116:116) (139:139:139)) (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -25156,9 +26764,9 @@ (INSTANCE z80_\|address_latch_\|abusz\[5\]) (DELAY (ABSOLUTE - (PORT datac (358:358:358) (420:420:420)) - (PORT datad (437:437:437) (498:498:498)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (594:594:594) (691:691:691)) + (PORT datad (335:335:335) (387:387:387)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -25168,10 +26776,10 @@ (INSTANCE z80_\|address_latch_\|Q\[5\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) + (PORT clk (914:914:914) (922:922:922)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (904:904:904)) - (PORT ena (1159:1159:1159) (1318:1318:1318)) + (PORT clrn (928:928:928) (910:910:910)) + (PORT ena (1097:1097:1097) (1218:1218:1218)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -25183,16 +26791,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~4) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~0) (DELAY (ABSOLUTE - (PORT dataa (493:493:493) (588:588:588)) - (PORT datab (633:633:633) (729:729:729)) - (PORT datac (541:541:541) (633:633:633)) - (PORT datad (190:190:190) (221:221:221)) - (IOPATH dataa combout (181:181:181) (193:193:193)) - (IOPATH datab combout (182:182:182) (188:188:188)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT dataa (629:629:629) (728:728:728)) + (PORT datab (815:815:815) (941:941:941)) + (PORT datac (638:638:638) (747:747:747)) + (PORT datad (107:107:107) (126:126:126)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -25202,10 +26810,10 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) (DELAY (ABSOLUTE - (PORT dataa (354:354:354) (419:419:419)) - (PORT datab (640:640:640) (739:739:739)) - (PORT datac (422:422:422) (496:496:496)) - (PORT datad (332:332:332) (388:388:388)) + (PORT dataa (315:315:315) (363:363:363)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (328:328:328) (385:385:385)) + (PORT datad (95:95:95) (115:115:115)) (IOPATH dataa combout (158:158:158) (173:173:173)) (IOPATH datab combout (160:160:160) (176:176:176)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -25213,30 +26821,14 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (746:746:746)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (903:903:903) (1009:1009:1009)) - (PORT ena (915:915:915) (1002:1002:1002)) + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (780:780:780) (877:877:877)) + (PORT ena (754:754:754) (814:814:814)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -25245,71 +26837,14 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (724:724:724) (832:832:832)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (756:756:756) (816:816:816)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (571:571:571)) - (PORT datab (538:538:538) (634:634:634)) - (PORT datad (118:118:118) (154:154:154)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (1013:1013:1013) (1123:1123:1123)) - (PORT ena (781:781:781) (840:840:840)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (1011:1011:1011) (1120:1120:1120)) - (PORT ena (662:662:662) (720:720:720)) + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (776:776:776) (873:873:873)) + (PORT ena (434:434:434) (466:466:466)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -25323,11 +26858,11 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) (DELAY (ABSOLUTE - (PORT dataa (611:611:611) (701:701:701)) - (PORT datab (130:130:130) (178:178:178)) - (PORT datad (354:354:354) (412:412:412)) + (PORT dataa (131:131:131) (174:174:174)) + (PORT datab (591:591:591) (682:682:682)) + (PORT datad (119:119:119) (156:156:156)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -25335,12 +26870,28 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (1171:1171:1171) (1302:1302:1302)) - (PORT ena (649:649:649) (703:703:703)) + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (661:661:661) (744:744:744)) + (PORT ena (503:503:503) (543:543:543)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (658:658:658) (741:741:741)) + (PORT ena (473:473:473) (498:498:498)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -25351,39 +26902,44 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]\~feeder) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~72) (DELAY (ABSOLUTE - (PORT datad (571:571:571) (650:650:650)) + (PORT dataa (218:218:218) (270:270:270)) + (PORT datab (232:232:232) (277:277:277)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (449:449:449)) + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (631:631:631) (696:696:696)) + (PORT ena (434:434:434) (462:462:462)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[6\]\~1) (DELAY (ABSOLUTE - (PORT dataa (220:220:220) (266:266:266)) - (PORT datab (346:346:346) (409:409:409)) - (PORT datad (194:194:194) (242:242:242)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (715:715:715) (844:844:844)) + (PORT datab (559:559:559) (659:659:659)) + (PORT datad (498:498:498) (578:578:578)) + (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -25395,41 +26951,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (764:764:764) (834:834:834)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (456:456:456)) - (PORT datab (525:525:525) (610:610:610)) - (PORT datac (479:479:479) (549:549:549)) - (PORT datad (332:332:332) (386:386:386)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (1171:1171:1171) (1301:1301:1301)) - (PORT ena (812:812:812) (885:885:885)) + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (1051:1051:1051) (1201:1201:1201)) + (PORT ena (409:409:409) (429:429:429)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -25440,10 +26964,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]\~feeder) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) (DELAY (ABSOLUTE - (PORT datad (703:703:703) (802:802:802)) + (PORT dataa (141:141:141) (182:182:182)) + (PORT datab (635:635:635) (741:741:741)) + (PORT datad (459:459:459) (530:530:530)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -25453,14 +26982,14 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (660:660:660) (723:723:723)) + (PORT clk (914:914:914) (922:922:922)) + (PORT asdata (513:513:513) (574:574:574)) + (PORT ena (409:409:409) (429:429:429)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) @@ -25469,83 +26998,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (875:875:875) (968:968:968)) - (PORT ena (631:631:631) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (292:292:292)) - (PORT datab (129:129:129) (176:176:176)) - (PORT datad (345:345:345) (403:403:403)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) - (DELAY - (ABSOLUTE - (PORT datab (767:767:767) (883:883:883)) - (PORT datad (302:302:302) (347:347:347)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) - (DELAY - (ABSOLUTE - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (724:724:724) (793:793:793)) - (PORT ena (422:422:422) (454:454:454)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (788:788:788) (871:871:871)) - (PORT ena (433:433:433) (461:461:461)) + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (521:521:521) (583:583:583)) + (PORT ena (684:684:684) (755:755:755)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -25559,9 +27014,56 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (277:277:277)) - (PORT datab (305:305:305) (362:362:362)) - (PORT datad (454:454:454) (533:533:533)) + (PORT dataa (630:630:630) (746:746:746)) + (PORT datab (396:396:396) (469:469:469)) + (PORT datad (554:554:554) (635:635:635)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (521:521:521) (584:584:584)) + (PORT ena (662:662:662) (720:720:720)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (931:931:931) (1043:1043:1043)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (806:806:806)) + (PORT datab (378:378:378) (444:444:444)) + (PORT datad (361:361:361) (434:434:434)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -25571,13 +27073,86 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) (DELAY (ABSOLUTE - (PORT dataa (190:190:190) (227:227:227)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (422:422:422) (480:480:480)) - (PORT datad (410:410:410) (465:465:465)) + (PORT dataa (358:358:358) (431:431:431)) + (PORT datab (356:356:356) (417:417:417)) + (PORT datac (304:304:304) (350:350:350)) + (PORT datad (159:159:159) (186:186:186)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (667:667:667) (749:749:749)) + (PORT ena (594:594:594) (642:642:642)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (357:357:357) (422:422:422)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (665:665:665) (725:725:725)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (390:390:390)) + (PORT datab (515:515:515) (604:604:604)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (402:402:402)) + (PORT datab (166:166:166) (202:202:202)) + (PORT datac (174:174:174) (207:207:207)) + (PORT datad (170:170:170) (201:201:201)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -25587,16 +27162,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) (DELAY (ABSOLUTE - (PORT dataa (326:326:326) (386:386:386)) - (PORT datab (367:367:367) (432:432:432)) - (PORT datac (747:747:747) (864:864:864)) - (PORT datad (309:309:309) (352:352:352)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (359:359:359) (422:422:422)) + (PORT datab (387:387:387) (456:456:456)) + (PORT datac (628:628:628) (734:734:734)) + (PORT datad (276:276:276) (318:318:318)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -25606,9 +27181,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (527:527:527) (588:588:588)) - (PORT ena (636:636:636) (682:682:682)) + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (440:440:440) (477:477:477)) + (PORT ena (650:650:650) (698:698:698)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -25622,26 +27197,42 @@ (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) (DELAY (ABSOLUTE - (PORT dataa (736:736:736) (841:841:841)) - (PORT datab (676:676:676) (792:792:792)) - (PORT datad (362:362:362) (425:425:425)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (809:809:809) (944:944:944)) + (PORT datab (197:197:197) (239:239:239)) + (PORT datad (346:346:346) (401:401:401)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (652:652:652) (711:711:711)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) (DELAY (ABSOLUTE - (PORT datab (369:369:369) (432:432:432)) - (PORT datac (372:372:372) (446:446:446)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (375:375:375) (448:448:448)) + (PORT datab (171:171:171) (208:208:208)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -25651,12 +27242,12 @@ (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) (DELAY (ABSOLUTE - (PORT dataa (392:392:392) (472:472:472)) - (PORT datab (352:352:352) (417:417:417)) - (PORT datac (511:511:511) (598:598:598)) - (PORT datad (335:335:335) (391:391:391)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT dataa (455:455:455) (528:528:528)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (663:663:663) (772:772:772)) + (PORT datad (192:192:192) (230:230:230)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -25667,9 +27258,9 @@ (INSTANCE z80_\|address_latch_\|abusz\[6\]) (DELAY (ABSOLUTE - (PORT datac (359:359:359) (421:421:421)) - (PORT datad (442:442:442) (510:510:510)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT datab (431:431:431) (498:498:498)) + (PORT datad (566:566:566) (657:657:657)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -25679,10 +27270,10 @@ (INSTANCE z80_\|address_latch_\|Q\[6\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) + (PORT clk (914:914:914) (922:922:922)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (904:904:904)) - (PORT ena (1159:1159:1159) (1318:1318:1318)) + (PORT clrn (928:928:928) (910:910:910)) + (PORT ena (1097:1097:1097) (1218:1218:1218)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -25697,13 +27288,13 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) (DELAY (ABSOLUTE - (PORT dataa (344:344:344) (407:407:407)) - (PORT datab (346:346:346) (408:408:408)) - (PORT datac (422:422:422) (497:497:497)) - (PORT datad (625:625:625) (721:721:721)) + (PORT dataa (120:120:120) (152:152:152)) + (PORT datab (474:474:474) (544:544:544)) + (PORT datac (327:327:327) (384:384:384)) + (PORT datad (97:97:97) (116:116:116)) (IOPATH dataa combout (192:192:192) (184:184:184)) - (IOPATH datab combout (191:191:191) (188:188:188)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -25713,10 +27304,10 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) (DELAY (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (636:636:636) (735:735:735)) - (PORT datac (341:341:341) (397:397:397)) - (PORT datad (333:333:333) (389:389:389)) + (PORT dataa (107:107:107) (138:138:138)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (302:302:302) (341:341:341)) + (PORT datad (93:93:93) (113:113:113)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -25726,331 +27317,122 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (295:295:295)) - (PORT datad (101:101:101) (122:122:122)) - (IOPATH dataa combout (186:186:186) (180:180:180)) + (PORT dataa (668:668:668) (761:761:761)) + (PORT datab (494:494:494) (581:581:581)) + (PORT datac (199:199:199) (252:252:252)) + (PORT datad (501:501:501) (593:593:593)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (470:470:470) (515:515:515)) + (PORT ena (619:619:619) (673:673:673)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (410:410:410)) + (PORT datab (331:331:331) (389:389:389)) + (PORT datad (102:102:102) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (611:611:611) (658:658:658)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (324:324:324) (380:380:380)) + (PORT datad (224:224:224) (280:280:280)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) (DELAY (ABSOLUTE - (PORT dataa (388:388:388) (467:467:467)) - (PORT datab (529:529:529) (620:620:620)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (337:337:337) (390:390:390)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (191:191:191) (232:232:232)) + (PORT datab (211:211:211) (253:253:253)) + (PORT datac (233:233:233) (288:288:288)) + (PORT datad (831:831:831) (974:974:974)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (393:393:393)) + (PORT datab (123:123:123) (155:155:155)) + (PORT datac (291:291:291) (336:336:336)) + (PORT datad (740:740:740) (848:848:848)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (644:644:644) (723:723:723)) - (PORT ena (781:781:781) (840:840:840)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (643:643:643) (722:722:722)) - (PORT ena (662:662:662) (720:720:720)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) + (INSTANCE z80_\|alu_\|db\[0\]\~17) (DELAY (ABSOLUTE - (PORT dataa (612:612:612) (702:702:702)) - (PORT datab (130:130:130) (179:179:179)) - (PORT datad (355:355:355) (414:414:414)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (761:761:761) (847:847:847)) - (PORT ena (915:915:915) (1002:1002:1002)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (762:762:762) (848:848:848)) - (PORT ena (756:756:756) (816:816:816)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (489:489:489) (574:574:574)) - (PORT datab (534:534:534) (629:629:629)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (1049:1049:1049) (1178:1178:1178)) - (PORT ena (649:649:649) (703:703:703)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (880:880:880) (1011:1011:1011)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (268:268:268)) - (PORT datab (348:348:348) (411:411:411)) - (PORT datad (193:193:193) (240:240:240)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (1047:1047:1047) (1177:1177:1177)) - (PORT ena (812:812:812) (885:885:885)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (1058:1058:1058) (1183:1183:1183)) - (PORT ena (660:660:660) (723:723:723)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (1057:1057:1057) (1183:1183:1183)) - (PORT ena (631:631:631) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (285:285:285)) - (PORT datab (129:129:129) (176:176:176)) - (PORT datad (347:347:347) (405:405:405)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) - (DELAY - (ABSOLUTE - (PORT datab (768:768:768) (884:884:884)) - (PORT datad (312:312:312) (360:360:360)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (942:942:942) (1061:1061:1061)) - (PORT ena (422:422:422) (454:454:454)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (941:941:941) (1060:1060:1060)) - (PORT ena (669:669:669) (725:725:725)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (274:274:274)) - (PORT datab (313:313:313) (371:371:371)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (764:764:764) (834:834:834)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (437:437:437)) - (PORT datab (525:525:525) (610:610:610)) - (PORT datac (444:444:444) (513:513:513)) - (PORT datad (330:330:330) (383:383:383)) + (PORT dataa (489:489:489) (580:580:580)) + (PORT datab (485:485:485) (565:565:565)) + (PORT datac (345:345:345) (404:404:404)) + (PORT datad (420:420:420) (486:486:486)) (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -26060,43 +27442,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) + (INSTANCE z80_\|alu_\|db\[0\]\~18) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (260:260:260) (292:292:292)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (183:183:183) (219:219:219)) - (PORT datad (306:306:306) (353:353:353)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~92) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (437:437:437)) - (PORT datab (358:358:358) (423:423:423)) - (PORT datac (746:746:746) (863:863:863)) - (PORT datad (310:310:310) (353:353:353)) + (PORT dataa (1015:1015:1015) (1160:1160:1160)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (303:303:303) (350:350:350)) + (PORT datad (120:120:120) (144:144:144)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (166:166:166) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -26106,15 +27458,325 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[7\]\~0) + (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (830:830:830) (963:963:963)) - (PORT datab (929:929:929) (1057:1057:1057)) - (PORT datac (467:467:467) (549:549:549)) - (PORT datad (646:646:646) (745:745:745)) + (PORT dataa (476:476:476) (573:573:573)) + (PORT datad (434:434:434) (501:501:501)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (671:671:671) (778:778:778)) + (PORT datac (484:484:484) (555:555:555)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (472:472:472) (546:546:546)) + (PORT datab (640:640:640) (738:738:738)) + (PORT datac (633:633:633) (732:732:732)) + (PORT datad (340:340:340) (396:396:396)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (783:783:783)) + (PORT datab (372:372:372) (441:441:441)) + (PORT datad (600:600:600) (678:678:678)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (749:749:749) (846:846:846)) + (PORT ena (667:667:667) (727:727:727)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|db\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (705:705:705) (850:850:850)) + (PORT datab (496:496:496) (576:576:576)) + (PORT datad (771:771:771) (877:877:877)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (632:632:632) (701:701:701)) + (PORT ena (754:754:754) (814:814:814)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (636:636:636) (701:701:701)) + (PORT ena (503:503:503) (543:543:543)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (637:637:637) (702:702:702)) + (PORT ena (473:473:473) (498:498:498)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (268:268:268)) + (PORT datab (239:239:239) (286:286:286)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (441:441:441) (511:511:511)) + (PORT datab (345:345:345) (412:412:412)) + (PORT datad (340:340:340) (397:397:397)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (603:603:603) (650:650:650)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT asdata (537:537:537) (597:597:597)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT asdata (536:536:536) (597:597:597)) + (PORT ena (495:495:495) (537:537:537)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (258:258:258)) + (PORT datab (129:129:129) (163:163:163)) + (PORT datad (110:110:110) (131:131:131)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (625:625:625) (690:690:690)) + (PORT ena (931:931:931) (1043:1043:1043)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (622:622:622) (686:686:686)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (148:148:148) (190:190:190)) + (PORT datab (825:825:825) (980:980:980)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (183:183:183)) + (PORT datab (334:334:334) (396:396:396)) + (PORT datac (201:201:201) (242:242:242)) + (PORT datad (160:160:160) (186:186:186)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (407:407:407)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (270:270:270) (309:309:309)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (647:647:647)) + (PORT datab (645:645:645) (752:752:752)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (357:357:357) (418:418:418)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -26122,13 +27784,102 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im2) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (595:595:595) (649:649:649)) + (PORT ena (650:650:650) (698:698:698)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (810:810:810) (945:945:945)) + (PORT datab (652:652:652) (753:753:753)) + (PORT datad (353:353:353) (409:409:409)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (913:913:913)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (895:895:895)) - (PORT ena (667:667:667) (732:732:732)) + (PORT ena (652:652:652) (711:711:711)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (173:173:173) (212:212:212)) + (PORT datac (351:351:351) (423:423:423)) + (PORT datad (118:118:118) (156:156:156)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (253:253:253)) + (PORT datab (115:115:115) (142:142:142)) + (PORT datac (660:660:660) (768:768:768)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[0\]) + (DELAY + (ABSOLUTE + (PORT datac (483:483:483) (566:566:566)) + (PORT datad (426:426:426) (481:481:481)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (920:920:920) (904:904:904)) + (PORT ena (953:953:953) (1066:1066:1066)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -26140,122 +27891,302 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~12) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) (DELAY (ABSOLUTE - (PORT dataa (206:206:206) (284:284:284)) - (PORT datac (681:681:681) (805:805:805)) - (PORT datad (150:150:150) (194:194:194)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (801:801:801) (921:921:921)) + (PORT datab (586:586:586) (683:683:683)) + (PORT datac (353:353:353) (418:418:418)) + (PORT datad (613:613:613) (706:706:706)) + (IOPATH dataa combout (188:188:188) (196:196:196)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (286:286:286)) - (PORT datab (382:382:382) (455:455:455)) - (PORT datac (100:100:100) (121:121:121)) - (PORT datad (733:733:733) (870:870:870)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (473:473:473) (545:545:545)) - (PORT datab (493:493:493) (571:571:571)) - (PORT datac (347:347:347) (410:410:410)) - (PORT datad (343:343:343) (394:394:394)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (365:365:365) (442:442:442)) + (PORT datab (782:782:782) (900:900:900)) + (PORT datac (92:92:92) (117:117:117)) + (PORT datad (756:756:756) (862:862:862)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datab combout (188:188:188) (177:177:177)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (449:449:449) (521:521:521)) - (PORT datab (460:460:460) (533:533:533)) - (PORT datac (491:491:491) (567:567:567)) - (PORT datad (352:352:352) (423:423:423)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (131:131:131) (166:166:166)) - (PORT datac (354:354:354) (422:422:422)) - (PORT datad (328:328:328) (381:381:381)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (444:444:444)) - (PORT datab (499:499:499) (575:575:575)) - (PORT datac (461:461:461) (530:530:530)) - (PORT datad (107:107:107) (125:125:125)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (739:739:739) (872:872:872)) - (PORT datab (486:486:486) (575:575:575)) - (PORT datac (333:333:333) (392:392:392)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (896:896:896) (901:901:901)) + (PORT clk (909:909:909) (913:913:913)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (435:435:435) (466:466:466)) + (PORT ena (652:652:652) (711:711:711)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (797:797:797) (892:892:892)) + (PORT ena (503:503:503) (543:543:543)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (798:798:798) (894:894:894)) + (PORT ena (473:473:473) (498:498:498)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (269:269:269)) + (PORT datab (233:233:233) (279:279:279)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (537:537:537) (605:605:605)) + (PORT ena (662:662:662) (720:720:720)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT asdata (754:754:754) (861:861:861)) + (PORT ena (435:435:435) (462:462:462)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (807:807:807)) + (PORT datab (381:381:381) (448:448:448)) + (PORT datad (477:477:477) (559:559:559)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT asdata (796:796:796) (889:889:889)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (775:775:775) (865:865:865)) + (PORT ena (666:666:666) (729:729:729)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (467:467:467)) + (PORT datab (372:372:372) (441:441:441)) + (PORT datad (349:349:349) (406:406:406)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (775:775:775) (865:865:865)) + (PORT ena (603:603:603) (650:650:650)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (268:268:268)) + (PORT datab (101:101:101) (129:129:129)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (470:470:470) (514:514:514)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (501:501:501) (583:583:583)) + (PORT datab (740:740:740) (859:859:859)) + (PORT datac (457:457:457) (525:525:525)) + (PORT datad (461:461:461) (541:541:541)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (177:177:177) (215:215:215)) + (PORT datab (333:333:333) (397:397:397)) + (PORT datad (163:163:163) (192:192:192)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (488:488:488) (540:540:540)) + (PORT ena (754:754:754) (814:814:814)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (309:309:309) (364:364:364)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (434:434:434) (466:466:466)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -26266,13 +28197,85 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~3) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) (DELAY (ABSOLUTE - (PORT dataa (830:830:830) (973:973:973)) - (PORT datab (820:820:820) (963:963:963)) - (PORT datac (607:607:607) (704:704:704)) - (PORT datad (358:358:358) (409:409:409)) + (PORT dataa (140:140:140) (185:185:185)) + (PORT datab (589:589:589) (679:679:679)) + (PORT datad (116:116:116) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (652:652:652) (729:729:729)) + (PORT ena (594:594:594) (642:642:642)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (354:354:354) (423:423:423)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (665:665:665) (725:725:725)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (392:392:392)) + (PORT datab (516:516:516) (606:606:606)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (317:317:317)) + (PORT datab (187:187:187) (224:224:224)) + (PORT datac (450:450:450) (511:511:511)) + (PORT datad (160:160:160) (183:183:183)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -26282,78 +28285,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) (DELAY (ABSOLUTE - (PORT dataa (614:614:614) (712:712:712)) - (PORT datab (401:401:401) (473:473:473)) - (PORT datac (779:779:779) (893:893:893)) - (PORT datad (669:669:669) (779:779:779)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (502:502:502) (599:599:599)) - (PORT datab (647:647:647) (748:748:748)) - (PORT datac (404:404:404) (501:501:501)) - (PORT datad (1079:1079:1079) (1263:1263:1263)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (411:411:411) (492:492:492)) - (PORT datab (803:803:803) (961:961:961)) - (PORT datac (614:614:614) (693:693:693)) - (PORT datad (105:105:105) (130:130:130)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (400:400:400)) - (PORT datab (440:440:440) (497:497:497)) - (PORT datac (617:617:617) (699:699:699)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (418:418:418)) - (PORT datab (579:579:579) (679:679:679)) - (PORT datac (302:302:302) (347:347:347)) - (PORT datad (502:502:502) (580:580:580)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (443:443:443) (519:519:519)) + (PORT datab (298:298:298) (346:346:346)) + (PORT datac (629:629:629) (735:735:735)) + (PORT datad (368:368:368) (431:431:431)) + (IOPATH dataa combout (165:165:165) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -26361,93 +28300,29 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT dataa (380:380:380) (450:450:450)) - (PORT datab (315:315:315) (366:366:366)) - (PORT datac (128:128:128) (169:169:169)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (440:440:440) (475:475:475)) + (PORT ena (650:650:650) (698:698:698)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (615:615:615) (714:714:714)) - (PORT datab (399:399:399) (471:471:471)) - (PORT datac (509:509:509) (590:590:590)) - (PORT datad (650:650:650) (742:742:742)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) - (DELAY - (ABSOLUTE - (PORT dataa (805:805:805) (926:926:926)) - (PORT datab (360:360:360) (432:432:432)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (791:791:791) (904:904:904)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) - (DELAY - (ABSOLUTE - (PORT dataa (786:786:786) (906:906:906)) - (PORT datab (399:399:399) (470:470:470)) - (PORT datac (636:636:636) (731:731:731)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (282:282:282)) - (PORT datab (146:146:146) (201:201:201)) - (PORT datac (124:124:124) (170:170:170)) - (PORT datad (313:313:313) (370:370:370)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) - (DELAY - (ABSOLUTE - (PORT dataa (442:442:442) (522:522:522)) - (PORT datab (403:403:403) (487:487:487)) - (PORT datad (208:208:208) (253:253:253)) + (PORT dataa (809:809:809) (944:944:944)) + (PORT datab (196:196:196) (237:237:237)) + (PORT datad (347:347:347) (402:402:402)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -26455,15 +28330,1946 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (449:449:449)) + (PORT datac (119:119:119) (160:160:160)) + (PORT datad (171:171:171) (202:202:202)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (259:259:259)) + (PORT datab (680:680:680) (795:795:795)) + (PORT datac (94:94:94) (117:117:117)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (719:719:719) (835:835:835)) + (PORT datad (279:279:279) (320:320:320)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (304:304:304) (349:349:349)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (928:928:928) (910:910:910)) + (PORT ena (1097:1097:1097) (1218:1218:1218)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (443:443:443)) + (PORT datab (631:631:631) (730:730:730)) + (PORT datac (352:352:352) (416:416:416)) + (PORT datad (777:777:777) (892:892:892)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (142:142:142)) + (PORT datab (780:780:780) (897:897:897)) + (PORT datac (762:762:762) (871:871:871)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (408:408:408)) + (PORT datab (315:315:315) (370:370:370)) + (PORT datac (313:313:313) (381:381:381)) + (PORT datad (358:358:358) (434:434:434)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (133:133:133)) + (PORT datab (684:684:684) (799:799:799)) + (PORT datac (492:492:492) (565:565:565)) + (PORT datad (113:113:113) (136:136:136)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (174:174:174) (211:211:211)) + (PORT datab (394:394:394) (462:462:462)) + (PORT datac (625:625:625) (730:730:730)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (386:386:386)) + (PORT datab (213:213:213) (254:254:254)) + (PORT datac (290:290:290) (329:329:329)) + (PORT datad (335:335:335) (391:391:391)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (119:119:119) (151:151:151)) + (PORT datab (605:605:605) (698:698:698)) + (PORT datac (461:461:461) (530:530:530)) + (PORT datad (173:173:173) (206:206:206)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (169:169:169)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (303:303:303) (350:350:350)) + (PORT datad (101:101:101) (118:118:118)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (405:405:405) (494:494:494)) + (PORT datac (110:110:110) (135:135:135)) + (PORT datad (117:117:117) (135:135:135)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (479:479:479) (565:565:565)) + (PORT datab (364:364:364) (434:434:434)) + (PORT datac (758:758:758) (871:871:871)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (463:463:463) (500:500:500)) + (PORT ena (894:894:894) (985:985:985)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (582:582:582)) + (PORT datab (891:891:891) (1052:1052:1052)) + (PORT datac (475:475:475) (553:553:553)) + (PORT datad (224:224:224) (281:281:281)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (460:460:460) (553:553:553)) + (PORT datab (141:141:141) (177:177:177)) + (PORT datac (476:476:476) (562:562:562)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (464:464:464) (551:551:551)) + (PORT datab (485:485:485) (566:566:566)) + (PORT datad (422:422:422) (496:496:496)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (719:719:719) (826:826:826)) + (PORT datac (110:110:110) (136:136:136)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (502:502:502) (599:599:599)) + (PORT datab (611:611:611) (733:733:733)) + (PORT datac (484:484:484) (579:579:579)) + (PORT datad (347:347:347) (403:403:403)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (430:430:430)) + (PORT datab (456:456:456) (527:527:527)) + (PORT datac (336:336:336) (400:400:400)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (893:893:893)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (454:454:454)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (426:426:426)) + (PORT datab (481:481:481) (568:568:568)) + (PORT datac (444:444:444) (509:509:509)) + (PORT datad (338:338:338) (393:393:393)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (337:337:337) (402:402:402)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (893:893:893)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (454:454:454)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (246:246:246) (308:308:308)) + (PORT datab (306:306:306) (363:363:363)) + (PORT datac (350:350:350) (419:419:419)) + (PORT datad (450:450:450) (521:521:521)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (223:223:223)) + (PORT datac (105:105:105) (128:128:128)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~1) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (224:224:224)) + (PORT datab (116:116:116) (144:144:144)) + (PORT datac (179:179:179) (212:212:212)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (415:415:415)) + (PORT datab (469:469:469) (540:540:540)) + (PORT datac (1130:1130:1130) (1315:1315:1315)) + (PORT datad (471:471:471) (574:574:574)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (508:508:508) (604:604:604)) + (PORT datac (356:356:356) (412:412:412)) + (PORT datad (339:339:339) (391:391:391)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (1013:1013:1013)) + (PORT datab (393:393:393) (458:458:458)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (531:531:531) (600:600:600)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (304:304:304)) + (PORT datab (144:144:144) (181:181:181)) + (PORT datad (318:318:318) (376:376:376)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (398:398:398)) + (PORT datab (305:305:305) (354:354:354)) + (PORT datac (475:475:475) (561:561:561)) + (PORT datad (93:93:93) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (302:302:302) (350:350:350)) + (PORT datab (120:120:120) (150:150:150)) + (PORT datac (464:464:464) (544:544:544)) + (PORT datad (446:446:446) (526:526:526)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (436:436:436)) + (PORT datab (620:620:620) (719:719:719)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (283:283:283) (319:319:319)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1029:1029:1029) (1169:1169:1169)) + (PORT datab (105:105:105) (135:135:135)) + (PORT datac (488:488:488) (570:570:570)) + (PORT datad (168:168:168) (200:200:200)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (695:695:695)) + (PORT datab (761:761:761) (887:887:887)) + (PORT datac (428:428:428) (489:489:489)) + (PORT datad (300:300:300) (348:348:348)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (432:432:432) (500:500:500)) + (PORT datab (188:188:188) (229:229:229)) + (PORT datac (584:584:584) (664:664:664)) + (PORT datad (570:570:570) (651:651:651)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (152:152:152)) + (PORT datab (112:112:112) (144:144:144)) + (PORT datac (320:320:320) (375:375:375)) + (PORT datad (315:315:315) (361:361:361)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (599:599:599)) + (PORT datab (487:487:487) (573:573:573)) + (PORT datac (679:679:679) (778:778:778)) + (PORT datad (331:331:331) (387:387:387)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (120:120:120) (149:149:149)) + (PORT datac (466:466:466) (538:538:538)) + (PORT datad (341:341:341) (396:396:396)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~14) + (DELAY + (ABSOLUTE + (PORT dataa (128:128:128) (165:165:165)) + (PORT datab (835:835:835) (969:969:969)) + (PORT datac (681:681:681) (786:786:786)) + (PORT datad (381:381:381) (448:448:448)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~13) + (DELAY + (ABSOLUTE + (PORT datac (97:97:97) (124:124:124)) + (PORT datad (102:102:102) (124:124:124)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~15) + (DELAY + (ABSOLUTE + (PORT dataa (432:432:432) (500:500:500)) + (PORT datab (187:187:187) (229:229:229)) + (PORT datac (269:269:269) (311:311:311)) + (PORT datad (431:431:431) (491:491:491)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~16) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (400:400:400)) + (PORT datab (348:348:348) (412:412:412)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (381:381:381)) + (PORT datab (799:799:799) (903:903:903)) + (PORT datac (800:800:800) (932:932:932)) + (PORT datad (102:102:102) (118:118:118)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (767:767:767)) + (PORT datab (797:797:797) (901:901:901)) + (PORT datac (91:91:91) (112:112:112)) + (PORT datad (451:451:451) (518:518:518)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (623:623:623)) + (PORT datab (668:668:668) (766:766:766)) + (PORT datac (330:330:330) (390:390:390)) + (PORT datad (753:753:753) (862:862:862)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_set\~0) + (DELAY + (ABSOLUTE + (PORT dataa (443:443:443) (513:513:513)) + (PORT datab (760:760:760) (886:886:886)) + (PORT datac (587:587:587) (672:672:672)) + (PORT datad (948:948:948) (1073:1073:1073)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M2T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (1008:1008:1008) (1169:1169:1169)) + (PORT datab (363:363:363) (431:431:431)) + (PORT datac (594:594:594) (701:701:701)) + (PORT datad (174:174:174) (205:205:205)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) + (DELAY + (ABSOLUTE + (PORT dataa (461:461:461) (533:533:533)) + (PORT datab (339:339:339) (400:400:400)) + (PORT datac (103:103:103) (125:125:125)) + (PORT datad (344:344:344) (401:401:401)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) + (DELAY + (ABSOLUTE + (PORT dataa (283:283:283) (330:330:330)) + (PORT datab (342:342:342) (398:398:398)) + (PORT datac (305:305:305) (354:354:354)) + (PORT datad (165:165:165) (194:194:194)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (476:476:476) (562:562:562)) + (PORT datab (582:582:582) (677:677:677)) + (PORT datac (439:439:439) (520:520:520)) + (PORT datad (313:313:313) (363:363:363)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (473:473:473) (556:556:556)) + (PORT datab (228:228:228) (283:283:283)) + (PORT datac (165:165:165) (195:195:195)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) + (DELAY + (ABSOLUTE + (PORT datab (509:509:509) (605:605:605)) + (PORT datac (373:373:373) (436:436:436)) + (PORT datad (510:510:510) (586:586:586)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (434:434:434)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (339:339:339) (391:391:391)) + (PORT datad (863:863:863) (988:988:988)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (452:452:452) (514:514:514)) + (PORT datab (106:106:106) (136:136:136)) + (PORT datac (120:120:120) (164:164:164)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (452:452:452) (514:514:514)) + (PORT datab (181:181:181) (221:221:221)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (866:866:866) (992:992:992)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (782:782:782) (954:954:954)) + (PORT datab (1484:1484:1484) (1755:1755:1755)) + (PORT datac (671:671:671) (783:783:783)) + (PORT datad (750:750:750) (911:911:911)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (249:249:249)) + (PORT datab (358:358:358) (421:421:421)) + (PORT datac (959:959:959) (1109:1109:1109)) + (PORT datad (469:469:469) (526:526:526)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (419:419:419)) + (PORT datab (358:358:358) (426:426:426)) + (PORT datad (613:613:613) (707:707:707)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1039:1039:1039) (1218:1218:1218)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (442:442:442) (493:493:493)) + (PORT datad (643:643:643) (732:732:732)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (711:711:711)) + (PORT datab (460:460:460) (542:542:542)) + (PORT datac (647:647:647) (740:740:740)) + (PORT datad (606:606:606) (697:697:697)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (187:187:187)) + (PORT datab (140:140:140) (187:187:187)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (453:453:453) (518:518:518)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (650:650:650)) + (PORT datab (478:478:478) (553:553:553)) + (PORT datac (589:589:589) (701:701:701)) + (PORT datad (695:695:695) (827:827:827)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) + (DELAY + (ABSOLUTE + (PORT dataa (128:128:128) (158:158:158)) + (PORT datab (791:791:791) (949:949:949)) + (PORT datac (1108:1108:1108) (1254:1254:1254)) + (PORT datad (489:489:489) (556:556:556)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (143:143:143)) + (PORT datab (550:550:550) (653:653:653)) + (PORT datac (653:653:653) (751:751:751)) + (PORT datad (799:799:799) (923:923:923)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (717:717:717)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (340:340:340) (397:397:397)) + (PORT datad (487:487:487) (561:561:561)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (416:416:416)) + (PORT datab (691:691:691) (802:802:802)) + (PORT datac (96:96:96) (122:122:122)) + (PORT datad (341:341:341) (400:400:400)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (398:398:398)) + (PORT datab (316:316:316) (365:365:365)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (165:165:165) (193:193:193)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal64\~0) + (DELAY + (ABSOLUTE + (PORT datac (519:519:519) (622:622:622)) + (PORT datad (458:458:458) (527:527:527)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~1) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (318:318:318) (367:367:367)) + (PORT datac (109:109:109) (135:135:135)) + (PORT datad (102:102:102) (118:118:118)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (573:573:573)) + (PORT datab (1102:1102:1102) (1281:1281:1281)) + (PORT datac (744:744:744) (851:851:851)) + (PORT datad (1216:1216:1216) (1455:1455:1455)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (475:475:475) (549:549:549)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (116:116:116) (143:143:143)) + (PORT datad (101:101:101) (125:125:125)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (465:465:465) (537:537:537)) + (PORT datab (111:111:111) (143:143:143)) + (PORT datac (679:679:679) (777:777:777)) + (PORT datad (473:473:473) (548:548:548)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (143:143:143)) + (PORT datab (656:656:656) (759:759:759)) + (PORT datad (95:95:95) (116:116:116)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (805:805:805)) + (PORT datab (374:374:374) (448:448:448)) + (PORT datac (420:420:420) (484:484:484)) + (PORT datad (932:932:932) (1070:1070:1070)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (309:309:309) (357:357:357)) + (PORT datab (444:444:444) (512:512:512)) + (PORT datac (318:318:318) (367:367:367)) + (PORT datad (352:352:352) (408:408:408)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (352:352:352) (417:417:417)) + (PORT datac (175:175:175) (212:212:212)) + (PORT datad (331:331:331) (378:378:378)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (750:750:750) (860:860:860)) + (PORT datab (499:499:499) (585:585:585)) + (PORT datac (566:566:566) (652:652:652)) + (PORT datad (776:776:776) (893:893:893)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (229:229:229)) + (PORT datab (334:334:334) (394:394:394)) + (PORT datac (100:100:100) (121:121:121)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (451:451:451)) + (PORT datab (543:543:543) (622:622:622)) + (PORT datac (1106:1106:1106) (1296:1296:1296)) + (PORT datad (168:168:168) (197:197:197)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) + (DELAY + (ABSOLUTE + (PORT datab (431:431:431) (498:498:498)) + (PORT datac (115:115:115) (141:141:141)) + (PORT datad (451:451:451) (520:520:520)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (177:177:177) (217:217:217)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (330:330:330) (386:386:386)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_cf) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (392:392:392)) + (PORT datab (104:104:104) (132:132:132)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (306:306:306) (348:348:348)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (711:711:711)) + (PORT datab (650:650:650) (753:753:753)) + (PORT datac (643:643:643) (748:748:748)) + (PORT datad (750:750:750) (859:859:859)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (701:701:701)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (106:106:106) (129:129:129)) + (PORT datad (274:274:274) (316:316:316)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) + (DELAY + (ABSOLUTE + (PORT datab (449:449:449) (517:517:517)) + (PORT datac (604:604:604) (690:690:690)) + (PORT datad (435:435:435) (506:506:506)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (443:443:443) (512:512:512)) + (PORT datab (494:494:494) (570:570:570)) + (PORT datad (88:88:88) (106:106:106)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~9) + (DELAY + (ABSOLUTE + (PORT dataa (506:506:506) (595:595:595)) + (PORT datab (496:496:496) (568:568:568)) + (PORT datac (798:798:798) (907:907:907)) + (PORT datad (481:481:481) (543:543:543)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (780:780:780)) + (PORT datab (485:485:485) (562:562:562)) + (PORT datac (633:633:633) (720:720:720)) + (PORT datad (534:534:534) (619:619:619)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (767:767:767)) + (PORT datab (798:798:798) (902:902:902)) + (PORT datac (101:101:101) (121:121:121)) + (PORT datad (282:282:282) (324:324:324)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (418:418:418)) + (PORT datab (361:361:361) (443:443:443)) + (PORT datac (590:590:590) (672:672:672)) + (PORT datad (280:280:280) (325:325:325)) + (IOPATH dataa combout (158:158:158) (165:165:165)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (456:456:456)) + (PORT datab (725:725:725) (832:832:832)) + (PORT datac (537:537:537) (625:625:625)) + (PORT datad (194:194:194) (222:222:222)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (647:647:647) (746:746:746)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (312:312:312) (364:364:364)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (309:309:309) (359:359:359)) + (PORT datab (450:450:450) (514:514:514)) + (PORT datac (297:297:297) (343:343:343)) + (PORT datad (288:288:288) (332:332:332)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (542:542:542) (608:608:608)) + (PORT ena (503:503:503) (543:543:543)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (542:542:542) (609:609:609)) + (PORT ena (473:473:473) (498:498:498)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (268:268:268)) + (PORT datab (238:238:238) (284:284:284)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (779:779:779)) + (PORT datab (463:463:463) (539:539:539)) + (PORT datad (322:322:322) (375:375:375)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (634:634:634) (701:701:701)) + (PORT ena (662:662:662) (720:720:720)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (535:535:535) (600:600:600)) + (PORT ena (931:931:931) (1043:1043:1043)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (537:537:537) (601:601:601)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (147:147:147) (190:190:190)) + (PORT datab (824:824:824) (979:979:979)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (383:383:383) (450:450:450)) + (PORT datad (335:335:335) (391:391:391)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT asdata (526:526:526) (580:580:580)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (633:633:633) (700:700:700)) + (PORT ena (684:684:684) (755:755:755)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (470:470:470)) + (PORT datab (396:396:396) (470:470:470)) + (PORT datad (554:554:554) (635:635:635)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (638:638:638) (707:707:707)) + (PORT ena (594:594:594) (642:642:642)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT asdata (638:638:638) (707:707:707)) + (PORT ena (665:665:665) (725:725:725)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (395:395:395)) + (PORT datab (518:518:518) (608:608:608)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (603:603:603) (650:650:650)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (419:419:419)) + (PORT datab (341:341:341) (403:403:403)) + (PORT datac (201:201:201) (242:242:242)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (433:433:433) (498:498:498)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (342:342:342) (407:407:407)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (644:644:644) (750:750:750)) + (PORT datac (575:575:575) (649:649:649)) + (PORT datad (355:355:355) (417:417:417)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (944:944:944)) + (PORT datab (362:362:362) (426:426:426)) + (PORT datad (442:442:442) (496:496:496)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (272:272:272)) + (PORT datac (352:352:352) (425:425:425)) + (PORT datad (168:168:168) (198:198:198)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (294:294:294)) + (PORT datad (106:106:106) (124:124:124)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (345:345:345)) + (PORT datab (131:131:131) (164:164:164)) + (PORT datac (672:672:672) (781:781:781)) + (PORT datad (333:333:333) (383:383:383)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[4\]) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (682:682:682)) + (PORT datad (455:455:455) (513:513:513)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (928:928:928) (910:910:910)) + (PORT ena (1097:1097:1097) (1218:1218:1218)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) (DELAY (ABSOLUTE - (PORT dataa (224:224:224) (293:293:293)) - (PORT datab (205:205:205) (263:263:263)) - (PORT datac (345:345:345) (421:421:421)) - (PORT datad (374:374:374) (448:448:448)) + (PORT dataa (221:221:221) (290:290:290)) + (PORT datab (207:207:207) (265:265:265)) + (PORT datac (133:133:133) (175:175:175)) + (PORT datad (129:129:129) (166:166:166)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -26476,10 +30282,42 @@ (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) (DELAY (ABSOLUTE - (PORT dataa (150:150:150) (208:208:208)) - (PORT datab (315:315:315) (383:383:383)) - (PORT datac (134:134:134) (182:182:182)) - (PORT datad (196:196:196) (239:239:239)) + (PORT dataa (243:243:243) (305:305:305)) + (PORT datab (220:220:220) (280:280:280)) + (PORT datac (207:207:207) (265:265:265)) + (PORT datad (131:131:131) (168:168:168)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) + (DELAY + (ABSOLUTE + (PORT dataa (705:705:705) (816:816:816)) + (PORT datab (378:378:378) (460:460:460)) + (PORT datac (315:315:315) (383:383:383)) + (PORT datad (131:131:131) (169:169:169)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (289:289:289)) + (PORT datab (218:218:218) (282:282:282)) + (PORT datac (290:290:290) (350:350:350)) + (PORT datad (198:198:198) (248:248:248)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -26492,10 +30330,10 @@ (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) (DELAY (ABSOLUTE - (PORT dataa (302:302:302) (349:349:349)) - (PORT datab (486:486:486) (556:556:556)) - (PORT datac (301:301:301) (340:340:340)) - (PORT datad (158:158:158) (184:184:184)) + (PORT dataa (462:462:462) (532:532:532)) + (PORT datab (446:446:446) (513:513:513)) + (PORT datac (330:330:330) (387:387:387)) + (PORT datad (339:339:339) (397:397:397)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -26508,9 +30346,9 @@ (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) (DELAY (ABSOLUTE - (PORT dataa (788:788:788) (908:908:908)) - (PORT datab (874:874:874) (1011:1011:1011)) - (PORT datad (90:90:90) (108:108:108)) + (PORT dataa (555:555:555) (650:650:650)) + (PORT datab (367:367:367) (428:428:428)) + (PORT datad (334:334:334) (389:389:389)) (IOPATH dataa combout (181:181:181) (175:175:175)) (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -26523,9 +30361,9 @@ (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) + (PORT clk (904:904:904) (909:909:909)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (919:919:919) (904:904:904)) + (PORT clrn (914:914:914) (898:898:898)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -26539,28 +30377,98 @@ (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) (DELAY (ABSOLUTE - (PORT dataa (615:615:615) (713:713:713)) - (PORT datab (358:358:358) (430:430:430)) - (PORT datac (510:510:510) (591:591:591)) - (PORT datad (648:648:648) (740:740:740)) + (PORT dataa (537:537:537) (627:627:627)) + (PORT datab (347:347:347) (409:409:409)) + (PORT datac (453:453:453) (521:521:521)) + (PORT datad (346:346:346) (408:408:408)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal79\~0) + (DELAY + (ABSOLUTE + (PORT dataa (317:317:317) (370:370:370)) + (PORT datab (1477:1477:1477) (1703:1703:1703)) + (PORT datac (1166:1166:1166) (1392:1392:1392)) + (PORT datad (783:783:783) (884:884:884)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (307:307:307) (358:358:358)) + (PORT datab (322:322:322) (390:390:390)) + (PORT datad (623:623:623) (719:719:719)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (253:253:253)) + (PORT datac (402:402:402) (485:485:485)) + (PORT datad (150:150:150) (194:194:194)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (697:697:697) (760:760:760)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (898:898:898)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) (DELAY (ABSOLUTE - (PORT dataa (535:535:535) (630:630:630)) - (PORT datab (146:146:146) (195:195:195)) - (PORT datac (633:633:633) (728:728:728)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (102:102:102) (133:133:133)) + (PORT datab (744:744:744) (861:861:861)) + (PORT datac (459:459:459) (543:543:543)) + (PORT datad (127:127:127) (168:168:168)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -26571,13 +30479,109 @@ (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) (DELAY (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (399:399:399) (470:470:470)) - (PORT datac (771:771:771) (882:882:882)) - (PORT datad (133:133:133) (172:172:172)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (139:139:139) (191:191:191)) + (PORT datab (104:104:104) (134:134:134)) + (PORT datac (532:532:532) (627:627:627)) + (PORT datad (451:451:451) (529:529:529)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) + (DELAY + (ABSOLUTE + (PORT dataa (554:554:554) (649:649:649)) + (PORT datab (740:740:740) (857:857:857)) + (PORT datac (330:330:330) (385:385:385)) + (PORT datad (512:512:512) (596:596:596)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) + (DELAY + (ABSOLUTE + (PORT dataa (467:467:467) (557:557:557)) + (PORT datab (349:349:349) (425:425:425)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (346:346:346) (408:408:408)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (551:551:551) (645:645:645)) + (PORT datab (1225:1225:1225) (1465:1465:1465)) + (PORT datac (727:727:727) (838:838:838)) + (PORT datad (754:754:754) (914:914:914)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (653:653:653)) + (PORT datab (517:517:517) (608:608:608)) + (PORT datac (329:329:329) (384:384:384)) + (PORT datad (450:450:450) (528:528:528)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (467:467:467) (545:545:545)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (346:346:346) (408:408:408)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (222:222:222)) + (PORT datab (138:138:138) (169:169:169)) + (PORT datac (188:188:188) (223:223:223)) + (PORT datad (309:309:309) (356:356:356)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -26587,9 +30591,9 @@ (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) (DELAY (ABSOLUTE - (PORT clk (901:901:901) (909:909:909)) + (PORT clk (904:904:904) (909:909:909)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (676:676:676) (740:740:740)) + (PORT ena (1037:1037:1037) (1155:1155:1155)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -26598,47 +30602,17 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (147:147:147)) - (PORT datab (113:113:113) (145:145:145)) - (PORT datac (94:94:94) (119:119:119)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (284:284:284) (333:333:333)) - (PORT datab (112:112:112) (144:144:144)) - (PORT datac (92:92:92) (116:116:116)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|alu_parity_out\~0) (DELAY (ABSOLUTE - (PORT dataa (415:415:415) (479:479:479)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (104:104:104) (121:121:121)) - (IOPATH dataa combout (195:195:195) (203:203:203)) + (PORT dataa (197:197:197) (236:236:236)) + (PORT datab (183:183:183) (225:225:225)) + (PORT datac (164:164:164) (196:196:196)) + (PORT datad (101:101:101) (118:118:118)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -26649,43 +30623,41 @@ (INSTANCE z80_\|alu_\|alu_parity_out) (DELAY (ABSOLUTE - (PORT dataa (179:179:179) (217:217:217)) - (PORT datab (358:358:358) (421:421:421)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (196:196:196) (192:192:192)) + (PORT datab (719:719:719) (838:838:838)) + (PORT datad (419:419:419) (477:477:477)) + (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (714:714:714)) - (PORT datab (650:650:650) (752:752:752)) - (PORT datac (772:772:772) (883:883:883)) - (PORT datad (649:649:649) (742:742:742)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) (DELAY (ABSOLUTE - (PORT dataa (527:527:527) (616:616:616)) - (PORT datab (401:401:401) (473:473:473)) - (PORT datac (342:342:342) (408:408:408)) - (PORT datad (92:92:92) (109:109:109)) + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (262:262:262) (296:296:296)) + (PORT datad (90:90:90) (107:107:107)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (268:268:268)) + (PORT datab (540:540:540) (641:641:641)) + (PORT datac (539:539:539) (633:633:633)) + (PORT datad (523:523:523) (610:610:610)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -26696,10 +30668,10 @@ (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) (DELAY (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (778:778:778) (888:888:888)) - (PORT datad (89:89:89) (107:107:107)) + (PORT dataa (540:540:540) (640:640:640)) + (PORT datab (424:424:424) (493:493:493)) + (PORT datac (454:454:454) (526:526:526)) + (PORT datad (92:92:92) (110:110:110)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -26707,22 +30679,6 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~10) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (140:140:140)) - (PORT datab (173:173:173) (208:208:208)) - (PORT datac (680:680:680) (776:776:776)) - (PORT datad (364:364:364) (424:424:424)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) @@ -26739,13 +30695,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) (DELAY (ABSOLUTE - (PORT dataa (491:491:491) (574:574:574)) - (PORT datab (1125:1125:1125) (1288:1288:1288)) - (PORT datac (502:502:502) (612:612:612)) - (PORT datad (466:466:466) (538:538:538)) + (PORT dataa (672:672:672) (782:782:782)) + (PORT datab (550:550:550) (650:650:650)) + (PORT datac (623:623:623) (722:722:722)) + (PORT datad (631:631:631) (726:726:726)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -26755,13 +30711,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~2) + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) (DELAY (ABSOLUTE - (PORT dataa (213:213:213) (257:257:257)) - (PORT datab (642:642:642) (749:749:749)) - (PORT datac (309:309:309) (355:355:355)) - (PORT datad (173:173:173) (203:203:203)) + (PORT dataa (360:360:360) (423:423:423)) + (PORT datab (120:120:120) (151:151:151)) + (PORT datac (277:277:277) (321:321:321)) + (PORT datad (180:180:180) (213:213:213)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -26769,61 +30725,31 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (518:518:518)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (121:121:121) (160:160:160)) - (PORT datab (117:117:117) (152:152:152)) - (PORT datac (330:330:330) (391:391:391)) - (PORT datad (116:116:116) (146:146:146)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) (DELAY (ABSOLUTE - (PORT dataa (316:316:316) (370:370:370)) - (PORT datab (358:358:358) (422:422:422)) - (PORT datac (302:302:302) (348:348:348)) - (PORT datad (160:160:160) (183:183:183)) + (PORT dataa (447:447:447) (522:522:522)) + (PORT datab (336:336:336) (389:389:389)) + (PORT datac (289:289:289) (335:335:335)) + (PORT datad (285:285:285) (322:322:322)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11) (DELAY (ABSOLUTE - (PORT dataa (331:331:331) (385:385:385)) - (PORT datab (345:345:345) (395:395:395)) - (PORT datac (131:131:131) (173:173:173)) - (PORT datad (198:198:198) (230:230:230)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT datab (613:613:613) (711:711:711)) + (PORT datac (159:159:159) (187:187:187)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -26834,12 +30760,12 @@ (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) (DELAY (ABSOLUTE - (PORT dataa (355:355:355) (417:417:417)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (334:334:334) (392:392:392)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (PORT dataa (334:334:334) (402:402:402)) + (PORT datab (729:729:729) (856:856:856)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (444:444:444) (512:512:512)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -26850,9 +30776,9 @@ (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) (DELAY (ABSOLUTE - (PORT clk (902:902:902) (907:907:907)) + (PORT clk (904:904:904) (909:909:909)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (661:661:661) (712:712:712)) + (PORT ena (407:407:407) (424:424:424)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -26866,12 +30792,12 @@ (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) (DELAY (ABSOLUTE - (PORT dataa (891:891:891) (1048:1048:1048)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datac (95:95:95) (119:119:119)) - (PORT datad (479:479:479) (570:570:570)) + (PORT dataa (347:347:347) (416:416:416)) + (PORT datab (496:496:496) (600:600:600)) + (PORT datac (639:639:639) (740:740:740)) + (PORT datad (407:407:407) (466:466:466)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -26882,13 +30808,13 @@ (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) (DELAY (ABSOLUTE - (PORT dataa (367:367:367) (451:451:451)) - (PORT datab (347:347:347) (416:416:416)) - (PORT datac (94:94:94) (118:118:118)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (430:430:430) (495:495:495)) + (PORT datab (356:356:356) (434:434:434)) + (PORT datac (353:353:353) (431:431:431)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (186:186:186) (175:175:175)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -26898,11 +30824,11 @@ (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) (DELAY (ABSOLUTE - (PORT dataa (1019:1019:1019) (1203:1203:1203)) - (PORT datab (1126:1126:1126) (1289:1289:1289)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (159:159:159) (173:173:173)) - (IOPATH datab combout (196:196:196) (192:192:192)) + (PORT dataa (367:367:367) (436:436:436)) + (PORT datab (531:531:531) (633:633:633)) + (PORT datad (262:262:262) (293:293:293)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (161:161:161) (176:176:176)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -26913,7 +30839,7 @@ (INSTANCE z80_\|alu_control_\|flags_cond_true) (DELAY (ABSOLUTE - (PORT clk (899:899:899) (904:904:904)) + (PORT clk (911:911:911) (919:919:919)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -26922,49 +30848,17 @@ (HOLD d (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (392:392:392)) - (PORT datab (985:985:985) (1144:1144:1144)) - (PORT datac (1024:1024:1024) (1196:1196:1196)) - (PORT datad (302:302:302) (349:349:349)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) (DELAY (ABSOLUTE - (PORT dataa (108:108:108) (142:142:142)) - (PORT datab (121:121:121) (155:155:155)) - (PORT datac (301:301:301) (349:349:349)) - (PORT datad (94:94:94) (113:113:113)) + (PORT dataa (740:740:740) (865:865:865)) + (PORT datab (547:547:547) (651:651:651)) + (PORT datac (598:598:598) (689:689:689)) + (PORT datad (868:868:868) (1007:1007:1007)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (550:550:550)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datac (337:337:337) (398:398:398)) - (PORT datad (670:670:670) (775:775:775)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -26972,289 +30866,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) (DELAY (ABSOLUTE - (PORT dataa (340:340:340) (398:398:398)) - (PORT datab (517:517:517) (608:608:608)) - (PORT datad (358:358:358) (423:423:423)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (429:429:429)) - (PORT datab (268:268:268) (309:309:309)) - (PORT datac (384:384:384) (430:430:430)) - (PORT datad (604:604:604) (691:691:691)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (282:282:282) (331:331:331)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (316:316:316) (370:370:370)) - (PORT datad (341:341:341) (393:393:393)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (139:139:139) (175:175:175)) - (PORT datac (322:322:322) (372:372:372)) - (PORT datad (128:128:128) (157:157:157)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (1007:1007:1007) (1124:1124:1124)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (989:989:989) (1095:1095:1095)) - (PORT ena (649:649:649) (703:703:703)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (265:265:265)) - (PORT datab (198:198:198) (255:255:255)) - (PORT datad (331:331:331) (384:384:384)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (988:988:988) (1095:1095:1095)) - (PORT ena (812:812:812) (885:885:885)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (1163:1163:1163) (1294:1294:1294)) - (PORT ena (631:631:631) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (911:911:911)) - (PORT asdata (1168:1168:1168) (1299:1299:1299)) - (PORT ena (432:432:432) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (227:227:227) (288:288:288)) - (PORT datab (360:360:360) (427:427:427)) - (PORT datad (338:338:338) (407:407:407)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (768:768:768) (884:884:884)) - (PORT datad (311:311:311) (359:359:359)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (1006:1006:1006) (1123:1123:1123)) - (PORT ena (644:644:644) (698:698:698)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (336:336:336) (403:403:403)) - (PORT datab (525:525:525) (610:610:610)) - (PORT datac (488:488:488) (565:565:565)) - (PORT datad (333:333:333) (386:386:386)) + (PORT dataa (815:815:815) (939:939:939)) + (PORT datab (611:611:611) (706:706:706)) + (PORT datac (585:585:585) (660:660:660)) + (PORT datad (328:328:328) (376:376:376)) (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (875:875:875) (973:973:973)) - (PORT ena (422:422:422) (454:454:454)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (450:450:450) (519:519:519)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (669:669:669) (725:725:725)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (278:278:278)) - (PORT datab (305:305:305) (362:362:362)) - (PORT datad (300:300:300) (360:360:360)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (137:137:137)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (282:282:282) (322:322:322)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -27262,289 +30882,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]\~feeder) + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) (DELAY (ABSOLUTE - (PORT datad (833:833:833) (949:949:949)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (756:756:756) (816:816:816)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (1002:1002:1002) (1110:1110:1110)) - (PORT ena (915:915:915) (1002:1002:1002)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (130:130:130) (180:180:180)) - (PORT datab (536:536:536) (631:631:631)) - (PORT datad (474:474:474) (547:547:547)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (368:368:368) (408:408:408)) - (PORT ena (419:419:419) (435:435:435)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (368:368:368) (408:408:408)) - (PORT ena (432:432:432) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (130:130:130) (180:180:180)) - (PORT datab (142:142:142) (180:180:180)) - (PORT datad (127:127:127) (152:152:152)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (434:434:434)) - (PORT datab (346:346:346) (405:405:405)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (727:727:727) (836:836:836)) - (PORT datab (323:323:323) (375:375:375)) - (PORT datac (356:356:356) (416:416:416)) - (PORT datad (158:158:158) (184:184:184)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (828:828:828) (961:961:961)) - (PORT datab (928:928:928) (1056:1056:1056)) - (PORT datac (831:831:831) (943:943:943)) - (PORT datad (647:647:647) (747:747:747)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (527:527:527) (608:608:608)) - (PORT datab (489:489:489) (559:559:559)) - (PORT datac (506:506:506) (591:591:591)) - (PORT datad (488:488:488) (556:556:556)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (434:434:434)) - (PORT datab (612:612:612) (709:709:709)) - (PORT datac (491:491:491) (582:582:582)) - (PORT datad (652:652:652) (747:747:747)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (498:498:498) (583:583:583)) - (PORT datac (342:342:342) (402:402:402)) + (PORT dataa (341:341:341) (393:393:393)) + (PORT datab (119:119:119) (148:148:148)) + (PORT datac (332:332:332) (390:390:390)) (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (634:634:634)) + (PORT datac (531:531:531) (630:630:630)) + (PORT datad (686:686:686) (795:795:795)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (409:409:409)) + (PORT datab (809:809:809) (930:930:930)) + (PORT datac (315:315:315) (368:368:368)) + (PORT datad (311:311:311) (356:356:356)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (844:844:844)) - (PORT datab (508:508:508) (596:596:596)) - (PORT datac (805:805:805) (914:914:914)) - (PORT datad (517:517:517) (603:603:603)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (545:545:545) (638:638:638)) - (PORT datac (484:484:484) (567:567:567)) - (PORT datad (118:118:118) (149:149:149)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (1087:1087:1087)) - (PORT datac (492:492:492) (566:566:566)) - (PORT datad (186:186:186) (217:217:217)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (104:104:104) (132:132:132)) - (PORT datac (503:503:503) (580:580:580)) - (PORT datad (122:122:122) (149:149:149)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (754:754:754)) - (PORT datab (152:152:152) (196:196:196)) - (PORT datac (137:137:137) (175:175:175)) - (PORT datad (138:138:138) (168:168:168)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (235:235:235) (302:302:302)) - (PORT datab (650:650:650) (752:752:752)) - (PORT datac (635:635:635) (744:744:744)) - (PORT datad (368:368:368) (436:436:436)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -27552,12 +30928,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[0\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (901:901:901) (909:909:909)) - (PORT asdata (348:348:348) (380:380:380)) - (PORT ena (676:676:676) (740:740:740)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (396:396:396) (436:436:436)) + (PORT ena (619:619:619) (673:673:673)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -27568,210 +30944,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~20) + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~7) (DELAY (ABSOLUTE - (PORT dataa (334:334:334) (387:387:387)) - (PORT datab (186:186:186) (223:223:223)) - (PORT datad (630:630:630) (723:723:723)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (339:339:339) (408:408:408)) + (PORT datab (333:333:333) (391:391:391)) + (PORT datad (326:326:326) (381:381:381)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (307:307:307) (358:358:358)) - (PORT datab (116:116:116) (145:145:145)) - (PORT datac (610:610:610) (705:705:705)) - (PORT datad (170:170:170) (200:200:200)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (834:834:834)) - (PORT datab (489:489:489) (568:568:568)) - (PORT datac (627:627:627) (702:702:702)) - (PORT datad (525:525:525) (611:611:611)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (537:537:537) (630:630:630)) - (PORT datac (430:430:430) (491:491:491)) - (PORT datad (122:122:122) (153:153:153)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (531:531:531) (611:611:611)) - (PORT datac (914:914:914) (1063:1063:1063)) - (PORT datad (777:777:777) (876:876:876)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datac (494:494:494) (569:569:569)) - (PORT datad (129:129:129) (157:157:157)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (756:756:756)) - (PORT datab (155:155:155) (200:200:200)) - (PORT datac (141:141:141) (181:181:181)) - (PORT datad (132:132:132) (163:163:163)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (433:433:433)) - (PORT datab (651:651:651) (752:752:752)) - (PORT datac (328:328:328) (390:390:390)) - (PORT datad (368:368:368) (436:436:436)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[1\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (901:901:901) (909:909:909)) - (PORT asdata (579:579:579) (631:631:631)) - (PORT ena (676:676:676) (740:740:740)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (294:294:294) (344:344:344)) - (PORT datab (170:170:170) (207:207:207)) - (PORT datad (629:629:629) (722:722:722)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (363:363:363) (430:430:430)) - (PORT datab (187:187:187) (223:223:223)) - (PORT datac (433:433:433) (492:492:492)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (313:313:313) (367:367:367)) - (PORT datab (534:534:534) (632:632:632)) - (PORT datac (190:190:190) (233:233:233)) - (PORT datad (481:481:481) (558:558:558)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (376:376:376) (447:447:447)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (901:901:901)) + (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (405:405:405) (422:422:422)) + (PORT ena (611:611:611) (658:658:658)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -27782,888 +30975,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~0) + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~8) (DELAY (ABSOLUTE - (PORT datab (144:144:144) (192:192:192)) - (PORT datac (128:128:128) (169:169:169)) - (PORT datad (128:128:128) (164:164:164)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) - (DELAY - (ABSOLUTE - (PORT datac (464:464:464) (542:542:542)) - (PORT datad (365:365:365) (428:428:428)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (429:429:429)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datad (330:330:330) (381:381:381)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_hf2) - (DELAY - (ABSOLUTE - (PORT clk (900:900:900) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (662:662:662) (755:755:755)) - (PORT datab (357:357:357) (420:420:420)) - (PORT datac (641:641:641) (735:735:735)) - (PORT datad (358:358:358) (432:432:432)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (777:777:777)) - (PORT datab (925:925:925) (1052:1052:1052)) - (PORT datac (801:801:801) (932:932:932)) - (PORT datad (471:471:471) (543:543:543)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (410:410:410)) - (PORT datab (492:492:492) (569:569:569)) - (PORT datac (349:349:349) (411:411:411)) - (PORT datad (457:457:457) (516:516:516)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (444:444:444) (515:515:515)) - (PORT datab (500:500:500) (573:573:573)) - (PORT datac (215:215:215) (270:270:270)) - (PORT datad (452:452:452) (516:516:516)) + (PORT dataa (295:295:295) (343:343:343)) + (PORT datab (311:311:311) (366:366:366)) + (PORT datad (117:117:117) (154:154:154)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~29) + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~9) (DELAY (ABSOLUTE - (PORT dataa (363:363:363) (425:425:425)) - (PORT datab (498:498:498) (583:583:583)) - (PORT datac (310:310:310) (358:358:358)) - (PORT datad (163:163:163) (191:191:191)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (716:716:716) (847:847:847)) - (PORT datab (535:535:535) (629:629:629)) - (PORT datac (498:498:498) (575:575:575)) - (PORT datad (889:889:889) (1031:1031:1031)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (332:332:332) (389:389:389)) - (PORT datab (546:546:546) (639:639:639)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (117:117:117) (147:147:147)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (1087:1087:1087)) - (PORT datab (497:497:497) (571:571:571)) - (PORT datac (496:496:496) (571:571:571)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (791:791:791) (903:903:903)) - (PORT datab (617:617:617) (717:717:717)) + (PORT dataa (258:258:258) (315:315:315)) + (PORT datab (115:115:115) (144:144:144)) (PORT datac (88:88:88) (109:109:109)) - (PORT datad (125:125:125) (153:153:153)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (158:158:158)) - (PORT datab (133:133:133) (171:171:171)) - (PORT datac (331:331:331) (392:392:392)) - (PORT datad (471:471:471) (545:545:545)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (285:285:285) (330:330:330)) - (PORT datab (390:390:390) (468:468:468)) - (PORT datac (310:310:310) (356:356:356)) - (PORT datad (481:481:481) (558:558:558)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (415:415:415)) - (PORT datab (626:626:626) (748:748:748)) - (PORT datac (314:314:314) (362:362:362)) - (PORT datad (210:210:210) (258:258:258)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (144:144:144) (189:189:189)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (288:288:288) (335:335:335)) - (PORT datad (502:502:502) (587:587:587)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (420:420:420) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (310:310:310)) - (PORT datab (342:342:342) (414:414:414)) - (PORT datac (609:609:609) (701:701:701)) - (PORT datad (367:367:367) (435:435:435)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (901:901:901) (909:909:909)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (676:676:676) (740:740:740)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (174:174:174) (211:211:211)) - (PORT datab (324:324:324) (381:381:381)) - (PORT datac (530:530:530) (629:629:629)) - (PORT datad (317:317:317) (378:378:378)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (118:118:118) (156:156:156)) - (PORT datab (350:350:350) (411:411:411)) - (PORT datac (497:497:497) (583:583:583)) - (PORT datad (120:120:120) (150:150:150)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (147:147:147) (195:195:195)) - (PORT datab (306:306:306) (357:357:357)) - (PORT datac (305:305:305) (346:346:346)) - (PORT datad (496:496:496) (581:581:581)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (420:420:420) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (307:307:307)) - (PORT datab (373:373:373) (444:444:444)) - (PORT datac (470:470:470) (548:548:548)) - (PORT datad (223:223:223) (280:280:280)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (196:196:196) (237:237:237)) - (PORT datab (203:203:203) (246:246:246)) - (PORT datac (93:93:93) (117:117:117)) - (PORT datad (179:179:179) (209:209:209)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (194:194:194) (233:233:233)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (95:95:95) (119:119:119)) - (PORT datad (183:183:183) (219:219:219)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (752:752:752)) - (PORT datab (152:152:152) (194:194:194)) - (PORT datac (136:136:136) (173:173:173)) - (PORT datad (140:140:140) (170:170:170)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (1087:1087:1087)) - (PORT datac (486:486:486) (558:558:558)) - (PORT datad (479:479:479) (548:548:548)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT datab (102:102:102) (129:129:129)) - (PORT datac (499:499:499) (575:575:575)) - (PORT datad (130:130:130) (158:158:158)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (419:419:419)) - (PORT datab (649:649:649) (750:750:750)) - (PORT datac (222:222:222) (282:282:282)) - (PORT datad (368:368:368) (436:436:436)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (606:606:606) (705:705:705)) - (PORT datac (320:320:320) (375:375:375)) - (PORT datad (335:335:335) (389:389:389)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (689:689:689) (813:813:813)) - (PORT datab (128:128:128) (167:167:167)) - (PORT datac (521:521:521) (619:619:619)) - (PORT datad (167:167:167) (197:197:197)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (839:839:839)) - (PORT datab (536:536:536) (629:629:629)) - (PORT datac (915:915:915) (1056:1056:1056)) - (PORT datad (471:471:471) (544:544:544)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (401:401:401)) - (PORT datab (542:542:542) (634:634:634)) - (PORT datac (161:161:161) (194:194:194)) - (PORT datad (123:123:123) (154:154:154)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (261:261:261)) - (PORT datab (141:141:141) (189:189:189)) - (PORT datac (128:128:128) (169:169:169)) - (PORT datad (104:104:104) (122:122:122)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (752:752:752)) - (PORT datab (344:344:344) (406:406:406)) - (PORT datac (338:338:338) (413:413:413)) - (PORT datad (128:128:128) (170:170:170)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (716:716:716)) - (PORT datab (499:499:499) (574:574:574)) - (PORT datac (348:348:348) (415:415:415)) - (PORT datad (470:470:470) (539:539:539)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (503:503:503) (574:574:574)) - (PORT datac (597:597:597) (687:687:687)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (527:527:527) (617:617:617)) - (PORT datab (520:520:520) (607:607:607)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (487:487:487) (555:555:555)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (430:430:430)) - (PORT datab (104:104:104) (132:132:132)) - (PORT datac (881:881:881) (1001:1001:1001)) - (PORT datad (480:480:480) (538:538:538)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (381:381:381)) - (PORT datab (696:696:696) (795:795:795)) - (PORT datac (627:627:627) (732:732:732)) - (PORT datad (174:174:174) (208:208:208)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) - (DELAY - (ABSOLUTE - (PORT datab (155:155:155) (199:199:199)) - (PORT datad (133:133:133) (164:164:164)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im1) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (895:895:895)) - (PORT ena (667:667:667) (732:732:732)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (769:769:769)) - (PORT datab (669:669:669) (790:790:790)) - (PORT datac (676:676:676) (800:800:800)) - (PORT datad (147:147:147) (190:190:190)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (276:276:276)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datac (631:631:631) (720:720:720)) - (PORT datad (644:644:644) (741:741:741)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (537:537:537) (643:643:643)) - (PORT datab (644:644:644) (740:740:740)) - (PORT datac (366:366:366) (427:427:427)) - (PORT datad (345:345:345) (403:403:403)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (471:471:471) (544:544:544)) - (PORT datac (520:520:520) (612:612:612)) - (PORT datad (113:113:113) (136:136:136)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~37) - (DELAY - (ABSOLUTE - (PORT dataa (705:705:705) (831:831:831)) - (PORT datab (1183:1183:1183) (1403:1403:1403)) - (PORT datac (467:467:467) (556:556:556)) - (PORT datad (515:515:515) (607:607:607)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (694:694:694) (800:800:800)) - (PORT datac (778:778:778) (887:887:887)) - (PORT datad (504:504:504) (590:590:590)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (130:130:130) (159:159:159)) - (PORT datac (1120:1120:1120) (1313:1313:1313)) - (PORT datad (99:99:99) (120:120:120)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (480:480:480) (563:563:563)) - (PORT datab (119:119:119) (154:154:154)) - (PORT datac (337:337:337) (393:393:393)) - (PORT datad (523:523:523) (610:610:610)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~37) - (DELAY - (ABSOLUTE - (PORT dataa (580:580:580) (677:677:677)) - (PORT datab (604:604:604) (708:708:708)) - (PORT datac (553:553:553) (632:632:632)) - (PORT datad (335:335:335) (389:389:389)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~55) - (DELAY - (ABSOLUTE - (PORT dataa (543:543:543) (646:646:646)) - (PORT datab (608:608:608) (690:690:690)) - (PORT datac (536:536:536) (633:633:633)) - (PORT datad (581:581:581) (648:648:648)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~38) - (DELAY - (ABSOLUTE - (PORT dataa (485:485:485) (562:562:562)) - (PORT datab (106:106:106) (135:135:135)) - (PORT datac (280:280:280) (321:321:321)) - (PORT datad (285:285:285) (327:327:327)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (427:427:427)) - (PORT datab (500:500:500) (578:578:578)) - (PORT datac (1097:1097:1097) (1249:1249:1249)) - (PORT datad (437:437:437) (502:502:502)) + (PORT datad (826:826:826) (968:968:968)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -28673,89 +31005,25 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~3) + (INSTANCE z80_\|address_latch_\|abusz\[11\]) (DELAY (ABSOLUTE - (PORT datab (457:457:457) (536:536:536)) - (PORT datac (349:349:349) (411:411:411)) - (PORT datad (108:108:108) (130:130:130)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~31) - (DELAY - (ABSOLUTE - (PORT dataa (122:122:122) (156:156:156)) - (PORT datab (127:127:127) (160:160:160)) - (PORT datac (183:183:183) (220:220:220)) - (PORT datad (582:582:582) (649:649:649)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (403:403:403) (485:485:485)) - (PORT datab (879:879:879) (1005:1005:1005)) - (PORT datac (332:332:332) (392:392:392)) - (PORT datad (288:288:288) (334:334:334)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~33) - (DELAY - (ABSOLUTE - (PORT datab (287:287:287) (334:334:334)) - (PORT datac (729:729:729) (812:812:812)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~35) - (DELAY - (ABSOLUTE - (PORT dataa (576:576:576) (661:661:661)) - (PORT datab (300:300:300) (349:349:349)) - (PORT datac (420:420:420) (472:472:472)) - (PORT datad (417:417:417) (464:464:464)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datac (485:485:485) (569:569:569)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) + (INSTANCE z80_\|address_latch_\|Q\[11\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (923:923:923)) + (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (689:689:689) (767:767:767)) + (PORT clrn (920:920:920) (904:904:904)) + (PORT ena (953:953:953) (1066:1066:1066)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -28767,415 +31035,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) (DELAY (ABSOLUTE - (PORT datad (453:453:453) (528:528:528)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mrd) - (DELAY - (ABSOLUTE - (PORT clk (923:923:923) (907:907:907)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (925:925:925) (908:908:908)) - (PORT ena (602:602:602) (646:646:646)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) - (PORT asdata (661:661:661) (755:755:755)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (704:704:704) (789:789:789)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (497:497:497) (601:601:601)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~4) - (DELAY - (ABSOLUTE - (PORT dataa (125:125:125) (159:159:159)) - (PORT datab (399:399:399) (483:483:483)) - (PORT datac (471:471:471) (548:548:548)) - (PORT datad (606:606:606) (687:687:687)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1064:1064:1064) (1229:1229:1229)) - (PORT datab (829:829:829) (953:953:953)) - (PORT datac (830:830:830) (962:962:962)) - (PORT datad (1098:1098:1098) (1256:1256:1256)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~8) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (713:713:713)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (105:105:105) (128:128:128)) - (PORT datad (388:388:388) (461:461:461)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~9) - (DELAY - (ABSOLUTE - (PORT dataa (467:467:467) (537:537:537)) - (PORT datab (648:648:648) (746:746:746)) - (PORT datac (457:457:457) (517:517:517)) - (PORT datad (435:435:435) (495:495:495)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (689:689:689) (767:767:767)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (120:120:120) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (689:689:689) (767:767:767)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorq) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) - (PORT asdata (307:307:307) (347:347:347)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (704:704:704) (789:789:789)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) - (PORT asdata (298:298:298) (339:339:339)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (704:704:704) (789:789:789)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|iorq\~0) - (DELAY - (ABSOLUTE - (PORT datab (134:134:134) (183:183:183)) - (PORT datad (316:316:316) (377:377:377)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~1) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (146:146:146)) - (PORT datab (542:542:542) (637:637:637)) - (PORT datac (192:192:192) (230:230:230)) - (PORT datad (118:118:118) (135:135:135)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~2) - (DELAY - (ABSOLUTE - (PORT dataa (476:476:476) (554:554:554)) - (PORT datab (112:112:112) (144:144:144)) - (PORT datac (659:659:659) (755:755:755)) - (PORT datad (604:604:604) (693:693:693)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1045:1045:1045) (1187:1187:1187)) - (PORT datab (859:859:859) (999:999:999)) - (PORT datac (1202:1202:1202) (1386:1386:1386)) - (PORT datad (113:113:113) (135:135:135)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datab (173:173:173) (211:211:211)) - (PORT datac (305:305:305) (347:347:347)) - (PORT datad (188:188:188) (222:222:222)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff1) - (DELAY - (ABSOLUTE - (PORT clk (924:924:924) (910:910:910)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (902:902:902)) - (PORT ena (983:983:983) (1112:1112:1112)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1\~0) - (DELAY - (ABSOLUTE - (PORT datad (309:309:309) (371:371:371)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (704:704:704) (789:789:789)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff3) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (923:923:923)) - (PORT asdata (298:298:298) (340:340:340)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (689:689:689) (767:767:767)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (805:805:805) (940:940:940)) - (PORT datab (134:134:134) (184:184:184)) - (PORT datad (824:824:824) (959:959:959)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (174:174:174) (214:214:214)) - (PORT datab (183:183:183) (225:225:225)) - (PORT datac (557:557:557) (634:634:634)) - (PORT datad (94:94:94) (112:112:112)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (975:975:975) (1134:1134:1134)) - (PORT datab (898:898:898) (1064:1064:1064)) - (PORT datac (659:659:659) (776:776:776)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1334:1334:1334) (1561:1561:1561)) - (PORT datad (572:572:572) (677:677:677)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~5) - (DELAY - (ABSOLUTE - (PORT datab (745:745:745) (882:882:882)) - (PORT datac (1646:1646:1646) (1901:1901:1901)) - (PORT datad (1457:1457:1457) (1728:1728:1728)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT datac (217:217:217) (272:272:272)) + (PORT datad (174:174:174) (206:206:206)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -29183,455 +31047,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~6) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) (DELAY (ABSOLUTE - (PORT dataa (193:193:193) (230:230:230)) - (PORT datab (470:470:470) (547:547:547)) - (PORT datac (546:546:546) (629:629:629)) - (PORT datad (576:576:576) (646:646:646)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (516:516:516) (617:617:617)) - (PORT datac (650:650:650) (757:757:757)) - (PORT datad (1146:1146:1146) (1341:1341:1341)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (781:781:781) (907:907:907)) - (PORT datab (509:509:509) (601:601:601)) - (PORT datac (185:185:185) (217:217:217)) - (PORT datad (101:101:101) (118:118:118)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (446:446:446)) - (PORT datab (450:450:450) (528:528:528)) - (PORT datac (462:462:462) (539:539:539)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (719:719:719) (828:828:828)) - (PORT datab (468:468:468) (534:534:534)) - (PORT datac (714:714:714) (810:810:810)) - (PORT datad (352:352:352) (411:411:411)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (134:134:134)) - (PORT datab (590:590:590) (677:677:677)) - (PORT datac (191:191:191) (226:226:226)) - (PORT datad (1006:1006:1006) (1174:1174:1174)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~7) - (DELAY - (ABSOLUTE - (PORT datab (500:500:500) (588:588:588)) - (PORT datac (481:481:481) (557:557:557)) - (PORT datad (407:407:407) (466:466:466)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (866:866:866) (995:995:995)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (940:940:940) (1095:1095:1095)) - (PORT datad (482:482:482) (558:558:558)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (787:787:787) (919:919:919)) - (PORT datab (636:636:636) (729:729:729)) - (PORT datac (472:472:472) (558:558:558)) - (PORT datad (407:407:407) (465:465:465)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (994:994:994)) - (PORT datab (632:632:632) (739:739:739)) - (PORT datac (605:605:605) (693:693:693)) - (PORT datad (332:332:332) (389:389:389)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~9) - (DELAY - (ABSOLUTE - (PORT dataa (696:696:696) (827:827:827)) - (PORT datab (475:475:475) (551:551:551)) - (PORT datac (943:943:943) (1088:1088:1088)) - (PORT datad (143:143:143) (178:178:178)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (726:726:726)) - (PORT datab (112:112:112) (143:143:143)) - (PORT datac (101:101:101) (123:123:123)) - (PORT datad (343:343:343) (401:401:401)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (118:118:118) (147:147:147)) - (PORT datac (574:574:574) (650:650:650)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (673:673:673)) - (PORT datab (466:466:466) (542:542:542)) - (PORT datac (326:326:326) (377:377:377)) - (PORT datad (657:657:657) (763:763:763)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (491:491:491) (584:584:584)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datac (314:314:314) (362:362:362)) - (PORT datad (105:105:105) (123:123:123)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (168:168:168) (200:200:200)) - (PORT datad (439:439:439) (509:509:509)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~10) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (549:549:549)) - (PORT datab (578:578:578) (685:685:685)) - (PORT datac (604:604:604) (692:692:692)) - (PORT datad (616:616:616) (702:702:702)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (139:139:139)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (96:96:96) (115:115:115)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (302:302:302) (352:352:352)) - (PORT datab (606:606:606) (708:708:708)) - (PORT datac (940:940:940) (1096:1096:1096)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (440:440:440)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (327:327:327) (385:385:385)) - (PORT datad (103:103:103) (121:121:121)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (498:498:498) (581:581:581)) - (PORT datac (597:597:597) (720:720:720)) - (PORT datad (637:637:637) (733:733:733)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|DFF_inst5\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (120:120:120) (159:159:159)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|DFF_inst5) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (924:924:924) (906:906:906)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_iorqinta\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (124:124:124) (164:164:164)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) - (DELAY - (ABSOLUTE - (PORT clk (921:921:921) (906:906:906)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (924:924:924) (906:906:906)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (299:299:299) (342:342:342)) - (PORT clrn (924:924:924) (906:906:906)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (136:136:136) (189:189:189)) - (PORT datad (334:334:334) (390:390:390)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (977:977:977) (1136:1136:1136)) - (PORT datab (898:898:898) (1063:1063:1063)) - (PORT datac (658:658:658) (774:774:774)) - (PORT datad (680:680:680) (795:795:795)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ExtRamWE\~0) - (DELAY - (ABSOLUTE - (PORT dataa (976:976:976) (1134:1134:1134)) - (PORT datab (898:898:898) (1064:1064:1064)) - (PORT datac (659:659:659) (775:775:775)) - (PORT datad (679:679:679) (794:794:794)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (964:964:964) (1095:1095:1095)) - (PORT datab (451:451:451) (522:522:522)) - (PORT datad (171:171:171) (201:201:201)) + (PORT dataa (656:656:656) (771:771:771)) + (PORT datab (199:199:199) (235:235:235)) + (PORT datad (279:279:279) (320:320:320)) (IOPATH dataa combout (172:172:172) (165:165:165)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -29643,12 +31064,12 @@ (INSTANCE z80_\|execute_\|ctl_apin_mux2\~0) (DELAY (ABSOLUTE - (PORT dataa (514:514:514) (616:616:616)) - (PORT datab (539:539:539) (651:651:651)) - (PORT datac (1077:1077:1077) (1266:1266:1266)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT dataa (803:803:803) (973:973:973)) + (PORT datac (739:739:739) (898:898:898)) + (PORT datad (1422:1422:1422) (1644:1644:1644)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -29657,11 +31078,11 @@ (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~2) (DELAY (ABSOLUTE - (PORT dataa (941:941:941) (1117:1117:1117)) - (PORT datab (543:543:543) (633:633:633)) - (PORT datac (535:535:535) (624:624:624)) - (PORT datad (683:683:683) (785:785:785)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (619:619:619) (717:717:717)) + (PORT datab (523:523:523) (603:603:603)) + (PORT datac (450:450:450) (516:516:516)) + (PORT datad (955:955:955) (1136:1136:1136)) + (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -29673,653 +31094,13 @@ (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~3) (DELAY (ABSOLUTE - (PORT dataa (513:513:513) (615:615:615)) - (PORT datab (540:540:540) (651:651:651)) - (PORT datac (1077:1077:1077) (1266:1266:1266)) - (PORT datad (341:341:341) (400:400:400)) + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (1080:1080:1080) (1282:1282:1282)) + (PORT datac (1189:1189:1189) (1393:1393:1393)) + (PORT datad (955:955:955) (1136:1136:1136)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (319:319:319) (365:365:365)) - (PORT sload (583:583:583) (639:639:639)) - (PORT ena (599:599:599) (635:635:635)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[13\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (755:755:755)) - (PORT datad (1152:1152:1152) (1332:1332:1332)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (963:963:963) (1094:1094:1094)) - (PORT datab (115:115:115) (142:142:142)) - (PORT datad (164:164:164) (189:189:189)) - (IOPATH dataa combout (172:172:172) (165:165:165)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (313:313:313) (356:356:356)) - (PORT sload (583:583:583) (639:639:639)) - (PORT ena (599:599:599) (635:635:635)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[14\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (1165:1165:1165) (1354:1354:1354)) - (PORT datad (628:628:628) (735:735:735)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (966:966:966) (1097:1097:1097)) - (PORT datab (173:173:173) (212:212:212)) - (PORT datad (282:282:282) (323:323:323)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (305:305:305) (349:349:349)) - (PORT sload (583:583:583) (639:639:639)) - (PORT ena (599:599:599) (635:635:635)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[15\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (915:915:915) (1073:1073:1073)) - (PORT datac (840:840:840) (974:974:974)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (445:445:445)) - (PORT datab (139:139:139) (177:177:177)) - (PORT datac (191:191:191) (232:232:232)) - (PORT datad (702:702:702) (789:789:789)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (1159:1159:1159) (1347:1347:1347)) - (PORT datac (617:617:617) (726:726:726)) - (PORT datad (626:626:626) (733:733:733)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (499:499:499) (592:592:592)) - (PORT datad (1119:1119:1119) (1292:1292:1292)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (459:459:459) (534:534:534)) - (PORT datab (189:189:189) (226:226:226)) - (PORT datad (173:173:173) (195:195:195)) - (IOPATH dataa combout (172:172:172) (165:165:165)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (931:931:931) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (586:586:586) (648:648:648)) - (PORT sload (640:640:640) (715:715:715)) - (PORT ena (763:763:763) (829:829:829)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1006:1006:1006) (1180:1180:1180)) - (PORT datad (359:359:359) (438:438:438)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (536:536:536)) - (PORT datab (316:316:316) (363:363:363)) - (PORT datad (277:277:277) (315:315:315)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (931:931:931) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (518:518:518) (582:582:582)) - (PORT sload (640:640:640) (715:715:715)) - (PORT ena (763:763:763) (829:829:829)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) - (DELAY - (ABSOLUTE - (PORT datac (980:980:980) (1153:1153:1153)) - (PORT datad (345:345:345) (415:415:415)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (465:465:465) (541:541:541)) - (PORT datab (276:276:276) (318:318:318)) - (PORT datad (171:171:171) (203:203:203)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (931:931:931) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (390:390:390) (439:439:439)) - (PORT sload (640:640:640) (715:715:715)) - (PORT ena (763:763:763) (829:829:829)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) - (DELAY - (ABSOLUTE - (PORT datac (986:986:986) (1159:1159:1159)) - (PORT datad (193:193:193) (241:241:241)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (459:459:459) (533:533:533)) - (PORT datab (278:278:278) (323:323:323)) - (PORT datad (172:172:172) (204:204:204)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (931:931:931) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (516:516:516) (572:572:572)) - (PORT sload (640:640:640) (715:715:715)) - (PORT ena (763:763:763) (829:829:829)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) - (DELAY - (ABSOLUTE - (PORT datac (989:989:989) (1163:1163:1163)) - (PORT datad (350:350:350) (423:423:423)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (737:737:737) (848:848:848)) - (PORT datab (173:173:173) (212:212:212)) - (PORT datad (104:104:104) (122:122:122)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (522:522:522) (598:598:598)) - (PORT sload (591:591:591) (660:660:660)) - (PORT ena (606:606:606) (650:650:650)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) - (DELAY - (ABSOLUTE - (PORT datab (1121:1121:1121) (1302:1302:1302)) - (PORT datac (365:365:365) (442:442:442)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datad (723:723:723) (822:822:822)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (601:601:601) (673:673:673)) - (PORT sload (591:591:591) (660:660:660)) - (PORT ena (606:606:606) (650:650:650)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) - (DELAY - (ABSOLUTE - (PORT datab (385:385:385) (466:466:466)) - (PORT datac (980:980:980) (1152:1152:1152)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (740:740:740) (852:852:852)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (866:866:866) (977:977:977)) - (PORT sload (591:591:591) (660:660:660)) - (PORT ena (606:606:606) (650:650:650)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) - (DELAY - (ABSOLUTE - (PORT datac (981:981:981) (1154:1154:1154)) - (PORT datad (513:513:513) (600:600:600)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (176:176:176) (217:217:217)) - (PORT datab (737:737:737) (840:840:840)) - (PORT datad (104:104:104) (122:122:122)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (316:316:316) (360:360:360)) - (PORT sload (591:591:591) (660:660:660)) - (PORT ena (606:606:606) (650:650:650)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) - (DELAY - (ABSOLUTE - (PORT datab (508:508:508) (604:604:604)) - (PORT datad (1141:1141:1141) (1320:1320:1320)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (757:757:757) (876:876:876)) - (PORT datab (115:115:115) (142:142:142)) - (PORT datad (284:284:284) (327:327:327)) - (IOPATH dataa combout (172:172:172) (165:165:165)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (314:314:314) (361:361:361)) - (PORT sload (575:575:575) (630:630:630)) - (PORT ena (419:419:419) (435:435:435)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) - (DELAY - (ABSOLUTE - (PORT datac (988:988:988) (1162:1162:1162)) - (PORT datad (372:372:372) (453:453:453)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (294:294:294) (342:342:342)) - (PORT datad (745:745:745) (852:852:852)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (307:307:307) (354:354:354)) - (PORT sload (575:575:575) (630:630:630)) - (PORT ena (419:419:419) (435:435:435)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[10\]\~24) - (DELAY - (ABSOLUTE - (PORT datac (495:495:495) (592:592:592)) - (PORT datad (829:829:829) (968:968:968)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datad (741:741:741) (848:848:848)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -30329,11 +31110,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (905:905:905)) + (PORT clk (918:918:918) (905:905:905)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (477:477:477) (537:537:537)) - (PORT sload (575:575:575) (630:630:630)) - (PORT ena (419:419:419) (435:435:435)) + (PORT asdata (615:615:615) (685:685:685)) + (PORT sload (758:758:758) (851:851:851)) + (PORT ena (778:778:778) (852:852:852)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -30349,37 +31130,37 @@ (INSTANCE z80_\|address_pins_\|abus\[11\]\~19) (DELAY (ABSOLUTE - (PORT dataa (513:513:513) (606:606:606)) - (PORT datad (831:831:831) (970:970:970)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT datac (767:767:767) (892:892:892)) + (PORT datad (1116:1116:1116) (1308:1308:1308)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) (DELAY (ABSOLUTE - (PORT dataa (175:175:175) (215:215:215)) - (PORT datab (435:435:435) (497:497:497)) - (PORT datad (841:841:841) (952:952:952)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (PORT dataa (657:657:657) (772:772:772)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datad (291:291:291) (332:332:332)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) (DELAY (ABSOLUTE (PORT clk (918:918:918) (905:905:905)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (307:307:307) (353:353:353)) - (PORT sload (583:583:583) (639:639:639)) - (PORT ena (599:599:599) (635:635:635)) + (PORT asdata (389:389:389) (447:447:447)) + (PORT sload (758:758:758) (851:851:851)) + (PORT ena (778:778:778) (852:852:852)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -30392,206 +31173,205 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[12\]\~21) + (INSTANCE z80_\|address_pins_\|abus\[10\]\~20) (DELAY (ABSOLUTE - (PORT dataa (1003:1003:1003) (1176:1176:1176)) - (PORT datad (472:472:472) (553:553:553)) + (PORT dataa (1315:1315:1315) (1554:1554:1554)) + (PORT datad (789:789:789) (921:921:921)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~19) (DELAY (ABSOLUTE - (PORT d[0] (565:565:565) (645:645:645)) - (PORT clk (1094:1094:1094) (1111:1111:1111)) + (PORT dataa (171:171:171) (239:239:239)) + (PORT datac (491:491:491) (582:582:582)) + (PORT datad (340:340:340) (408:408:408)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (568:568:568) (645:645:645)) - (PORT d[1] (1218:1218:1218) (1443:1443:1443)) - (PORT d[2] (828:828:828) (946:946:946)) - (PORT d[3] (1657:1657:1657) (1939:1939:1939)) - (PORT d[4] (1525:1525:1525) (1792:1792:1792)) - (PORT d[5] (1840:1840:1840) (2134:2134:2134)) - (PORT d[6] (790:790:790) (920:920:920)) - (PORT d[7] (1703:1703:1703) (1928:1928:1928)) - (PORT d[8] (558:558:558) (640:640:640)) - (PORT d[9] (903:903:903) (1044:1044:1044)) - (PORT d[10] (932:932:932) (1066:1066:1066)) - (PORT d[11] (1275:1275:1275) (1489:1489:1489)) - (PORT d[12] (927:927:927) (1071:1071:1071)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (528:528:528) (555:555:555)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (PORT d[0] (804:804:804) (836:836:836)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1074:1074:1074) (1090:1090:1090)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (614:614:614) (622:622:622)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (623:623:623)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (623:623:623)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (623:623:623)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1110:1110:1110) (1139:1139:1139)) - (PORT asdata (1127:1127:1127) (1272:1272:1272)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (917:917:917)) - (PORT asdata (755:755:755) (842:842:842)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~48) (DELAY (ABSOLUTE - (PORT dataa (369:369:369) (445:445:445)) - (PORT datab (140:140:140) (179:179:179)) - (PORT datac (192:192:192) (233:233:233)) - (PORT datad (702:702:702) (789:789:789)) + (PORT dataa (331:331:331) (389:389:389)) + (PORT datab (710:710:710) (832:832:832)) + (PORT datac (399:399:399) (491:491:491)) + (PORT datad (328:328:328) (385:385:385)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (249:249:249)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datad (98:98:98) (119:119:119)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (893:893:893) (898:898:898)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (885:885:885) (890:890:890)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (417:417:417)) + (PORT datab (1610:1610:1610) (1880:1880:1880)) + (PORT datac (353:353:353) (411:411:411)) + (PORT datad (348:348:348) (411:411:411)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (151:151:151) (205:205:205)) + (PORT datab (515:515:515) (610:610:610)) + (PORT datac (547:547:547) (648:648:648)) + (PORT datad (144:144:144) (187:187:187)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~2) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (670:670:670)) + (PORT datac (153:153:153) (206:206:206)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (170:170:170) (237:237:237)) + (PORT datac (489:489:489) (580:580:580)) + (PORT datad (107:107:107) (126:126:126)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~0) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (765:765:765)) + (PORT datac (375:375:375) (458:458:458)) + (PORT datad (327:327:327) (399:399:399)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~3) + (DELAY + (ABSOLUTE + (PORT dataa (428:428:428) (521:521:521)) + (PORT datab (174:174:174) (211:211:211)) + (PORT datad (105:105:105) (122:122:122)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|shifted) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (902:902:902)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (883:883:883) (888:888:888)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~62) + (DELAY + (ABSOLUTE + (PORT datab (420:420:420) (503:503:503)) + (PORT datac (243:243:243) (305:305:305)) + (PORT datad (495:495:495) (582:582:582)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (652:652:652)) + (PORT datab (350:350:350) (427:427:427)) + (PORT datac (377:377:377) (460:460:460)) + (PORT datad (637:637:637) (736:736:736)) (IOPATH dataa combout (165:165:165) (159:159:159)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -30601,208 +31381,909 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~63) (DELAY (ABSOLUTE - (PORT datab (1160:1160:1160) (1348:1348:1348)) - (PORT datac (618:618:618) (727:727:727)) - (PORT datad (626:626:626) (733:733:733)) + (PORT dataa (539:539:539) (638:638:638)) + (PORT datab (417:417:417) (499:499:499)) + (PORT datac (383:383:383) (464:464:464)) + (PORT datad (525:525:525) (619:619:619)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (508:508:508)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (112:112:112) (147:147:147)) + (PORT datab (294:294:294) (341:341:341)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (893:893:893) (899:899:899)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (886:886:886) (890:890:890)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (115:115:115) (144:144:144)) + (PORT datad (620:620:620) (720:720:720)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (468:468:468) (526:526:526)) + (PORT sload (642:642:642) (710:710:710)) + (PORT ena (769:769:769) (838:838:838)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[15\]\~21) + (DELAY + (ABSOLUTE + (PORT datac (960:960:960) (1139:1139:1139)) + (PORT datad (1486:1486:1486) (1743:1743:1743)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (179:179:179) (215:215:215)) + (PORT datad (620:620:620) (720:720:720)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (481:481:481) (539:539:539)) + (PORT sload (642:642:642) (710:710:710)) + (PORT ena (769:769:769) (838:838:838)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[14\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1374:1374:1374) (1626:1626:1626)) + (PORT datad (943:943:943) (1097:1097:1097)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (715:715:715) (839:839:839)) + (PORT datac (394:394:394) (483:483:483)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (438:438:438) (533:533:533)) + (PORT datab (369:369:369) (441:441:441)) + (PORT datac (373:373:373) (447:447:447)) + (PORT datad (97:97:97) (117:117:117)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT datac (363:363:363) (433:433:433)) + (PORT datad (414:414:414) (504:504:504)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (479:479:479)) + (PORT datab (713:713:713) (837:837:837)) + (PORT datac (393:393:393) (482:482:482)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (110:110:110) (142:142:142)) + (PORT datac (423:423:423) (515:515:515)) + (PORT datad (110:110:110) (130:130:130)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (161:161:161) (221:221:221)) + (PORT datac (458:458:458) (526:526:526)) + (PORT datad (384:384:384) (469:469:469)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (449:449:449)) + (PORT datac (540:540:540) (637:637:637)) + (PORT datad (357:357:357) (424:424:424)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (497:497:497) (570:570:570)) + (PORT datab (330:330:330) (384:384:384)) + (PORT datad (99:99:99) (119:119:119)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (886:886:886) (891:891:891)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (420:420:420)) + (PORT datab (810:810:810) (927:927:927)) + (PORT datac (488:488:488) (569:569:569)) + (PORT datad (190:190:190) (236:236:236)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (115:115:115) (143:143:143)) + (PORT datad (620:620:620) (719:719:719)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (381:381:381) (437:437:437)) + (PORT sload (642:642:642) (710:710:710)) + (PORT ena (769:769:769) (838:838:838)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[12\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (990:990:990) (1163:1163:1163)) + (PORT datac (1285:1285:1285) (1512:1512:1512)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (187:187:187) (227:227:227)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datad (623:623:623) (723:723:723)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (389:389:389) (445:445:445)) + (PORT sload (642:642:642) (710:710:710)) + (PORT ena (769:769:769) (838:838:838)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (250:250:250)) + (PORT datab (424:424:424) (517:517:517)) + (PORT datac (390:390:390) (475:475:475)) + (PORT datad (180:180:180) (210:210:210)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~54) + (DELAY + (ABSOLUTE + (PORT datab (225:225:225) (286:286:286)) + (PORT datac (413:413:413) (499:499:499)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (145:145:145)) + (PORT datab (419:419:419) (507:507:507)) + (PORT datad (93:93:93) (112:112:112)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (895:895:895) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (887:887:887) (891:891:891)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~1) + (DELAY + (ABSOLUTE + (PORT datab (1112:1112:1112) (1315:1315:1315)) + (PORT datac (1286:1286:1286) (1512:1512:1512)) + (PORT datad (355:355:355) (426:426:426)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~127) + (DELAY + (ABSOLUTE + (PORT dataa (503:503:503) (600:600:600)) + (PORT datab (536:536:536) (642:642:642)) + (PORT datad (109:109:109) (128:128:128)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (561:561:561) (668:668:668)) + (PORT datab (155:155:155) (208:208:208)) + (PORT datac (134:134:134) (179:179:179)) + (PORT datad (388:388:388) (473:473:473)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~128) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (670:670:670)) + (PORT datab (519:519:519) (614:614:614)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (243:243:243)) + (PORT datab (334:334:334) (398:398:398)) + (PORT datad (424:424:424) (487:487:487)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (893:893:893) (898:898:898)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (885:885:885) (890:890:890)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (121:121:121) (151:151:151)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (345:345:345) (410:410:410)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT datac (1429:1429:1429) (1677:1677:1677)) + (PORT datad (653:653:653) (774:774:774)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~43) (DELAY (ABSOLUTE - (PORT d[0] (555:555:555) (632:632:632)) - (PORT clk (1092:1092:1092) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (569:569:569) (646:646:646)) - (PORT d[1] (1219:1219:1219) (1447:1447:1447)) - (PORT d[2] (1946:1946:1946) (2222:2222:2222)) - (PORT d[3] (1649:1649:1649) (1930:1930:1930)) - (PORT d[4] (1489:1489:1489) (1749:1749:1749)) - (PORT d[5] (1847:1847:1847) (2145:2145:2145)) - (PORT d[6] (933:933:933) (1077:1077:1077)) - (PORT d[7] (1691:1691:1691) (1915:1915:1915)) - (PORT d[8] (572:572:572) (660:660:660)) - (PORT d[9] (1843:1843:1843) (2130:2130:2130)) - (PORT d[10] (955:955:955) (1096:1096:1096)) - (PORT d[11] (1109:1109:1109) (1291:1291:1291)) - (PORT d[12] (1075:1075:1075) (1236:1236:1236)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (523:523:523) (545:545:545)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (PORT d[0] (928:928:928) (968:968:968)) + (PORT dataa (402:402:402) (495:495:495)) + (PORT datab (507:507:507) (609:609:609)) + (PORT datac (410:410:410) (504:504:504)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~44) (DELAY (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + (PORT dataa (503:503:503) (603:603:603)) + (PORT datab (390:390:390) (465:465:465)) + (PORT datac (390:390:390) (475:475:475)) + (PORT datad (190:190:190) (226:226:226)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~45) (DELAY (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + (PORT datab (115:115:115) (148:148:148)) + (PORT datac (239:239:239) (312:312:312)) + (PORT datad (337:337:337) (392:392:392)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~46) (DELAY (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1072:1072:1072) (1089:1089:1089)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + (PORT datab (262:262:262) (327:327:327)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (801:801:801) (910:910:910)) + (PORT clk (892:892:892) (898:898:898)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (885:885:885) (889:889:889)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (472:472:472)) + (PORT datad (407:407:407) (499:499:499)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (249:249:249)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datad (99:99:99) (121:121:121)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (893:893:893) (898:898:898)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (885:885:885) (890:890:890)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (772:772:772)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datad (165:165:165) (193:193:193)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (918:918:918) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (386:386:386) (442:442:442)) + (PORT sload (758:758:758) (851:851:851)) + (PORT ena (778:778:778) (852:852:852)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1311:1311:1311) (1550:1550:1550)) + (PORT datad (799:799:799) (933:933:933)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (769:769:769)) + (PORT datab (117:117:117) (146:146:146)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (367:367:367) (416:416:416)) + (PORT clk (918:918:918) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (381:381:381) (433:433:433)) + (PORT sload (758:758:758) (851:851:851)) + (PORT ena (778:778:778) (852:852:852)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (515:515:515) (617:617:617)) + (PORT datad (1362:1362:1362) (1600:1600:1600)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (456:456:456)) + (PORT datab (366:366:366) (441:441:441)) + (PORT datac (369:369:369) (430:430:430)) + (PORT datad (856:856:856) (988:988:988)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (1375:1375:1375) (1624:1624:1624)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) + (DELAY + (ABSOLUTE + (PORT clk (918:918:918) (902:902:902)) + (PORT asdata (302:302:302) (345:345:345)) + (PORT clrn (919:919:919) (901:901:901)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) (TIMINGCHECK (HOLD asdata (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (124:124:124) (164:164:164)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (919:919:919) (901:901:901)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|control_pins_\|pin_nIORQ\~1) + (DELAY + (ABSOLUTE + (PORT dataa (476:476:476) (549:549:549)) + (PORT datab (134:134:134) (184:184:184)) + (PORT datac (539:539:539) (626:626:626)) + (PORT datad (125:125:125) (165:165:165)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1462:1462:1462) (1695:1695:1695)) + (PORT datab (1122:1122:1122) (1325:1325:1325)) + (PORT datac (1570:1570:1570) (1835:1835:1835)) + (PORT datad (1216:1216:1216) (1397:1397:1397)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[13\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (1115:1115:1115) (1319:1319:1319)) + (PORT datac (1283:1283:1283) (1509:1509:1509)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ExtRamWE\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1463:1463:1463) (1696:1696:1696)) + (PORT datab (1119:1119:1119) (1322:1322:1322)) + (PORT datac (1569:1569:1569) (1834:1834:1834)) + (PORT datad (1219:1219:1219) (1399:1399:1399)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (370:370:370) (447:447:447)) - (PORT datab (144:144:144) (182:182:182)) - (PORT datac (195:195:195) (237:237:237)) - (PORT datad (702:702:702) (789:789:789)) + (PORT dataa (218:218:218) (267:267:267)) + (PORT datab (688:688:688) (798:798:798)) + (PORT datac (694:694:694) (797:797:797)) + (PORT datad (768:768:768) (886:886:886)) (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -30815,21 +32296,2740 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) (DELAY (ABSOLUTE - (PORT datab (1157:1157:1157) (1345:1345:1345)) - (PORT datac (616:616:616) (725:725:725)) - (PORT datad (625:625:625) (732:732:732)) - (IOPATH datab combout (166:166:166) (167:167:167)) + (PORT dataa (1089:1089:1089) (1298:1298:1298)) + (PORT datac (1131:1131:1131) (1334:1334:1334)) + (PORT datad (800:800:800) (938:938:938)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (140:140:140)) + (PORT datab (319:319:319) (369:369:369)) + (PORT datad (500:500:500) (580:580:580)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (905:905:905)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (527:527:527) (594:594:594)) + (PORT sload (641:641:641) (709:709:709)) + (PORT ena (649:649:649) (704:704:704)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1375:1375:1375) (1628:1628:1628)) + (PORT datac (591:591:591) (688:688:688)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (936:936:936) (1084:1084:1084)) + (PORT datad (167:167:167) (199:199:199)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (926:926:926) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (494:494:494) (561:561:561)) + (PORT sload (861:861:861) (960:960:960)) + (PORT ena (764:764:764) (831:831:831)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (732:732:732)) + (PORT datad (1361:1361:1361) (1599:1599:1599)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (466:466:466) (544:544:544)) + (PORT datab (952:952:952) (1107:1107:1107)) + (PORT datad (484:484:484) (544:544:544)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (897:897:897)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (677:677:677) (775:775:775)) + (PORT sload (709:709:709) (784:784:784)) + (PORT ena (743:743:743) (803:803:803)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (143:143:143) (192:192:192)) + (PORT datad (1357:1357:1357) (1594:1594:1594)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (147:147:147)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datad (918:918:918) (1059:1059:1059)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (926:926:926) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (472:472:472) (528:528:528)) + (PORT sload (861:861:861) (960:960:960)) + (PORT ena (764:764:764) (831:831:831)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (153:153:153) (201:201:201)) + (PORT datad (197:197:197) (246:246:246)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (937:937:937) (1084:1084:1084)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (926:926:926) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (496:496:496) (554:554:554)) + (PORT sload (861:861:861) (960:960:960)) + (PORT ena (764:764:764) (831:831:831)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) + (DELAY + (ABSOLUTE + (PORT datac (698:698:698) (834:834:834)) + (PORT datad (1354:1354:1354) (1591:1591:1591)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (329:329:329)) + (PORT datab (935:935:935) (1082:1082:1082)) + (PORT datad (161:161:161) (185:185:185)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (926:926:926) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (310:310:310) (352:352:352)) + (PORT sload (861:861:861) (960:960:960)) + (PORT ena (764:764:764) (831:831:831)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) + (DELAY + (ABSOLUTE + (PORT datac (834:834:834) (976:976:976)) + (PORT datad (1358:1358:1358) (1595:1595:1595)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (665:665:665)) + (PORT datab (495:495:495) (568:568:568)) + (PORT datad (940:940:940) (1085:1085:1085)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (897:897:897)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (685:685:685) (785:785:785)) + (PORT sload (709:709:709) (784:784:784)) + (PORT ena (743:743:743) (803:803:803)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1373:1373:1373) (1625:1625:1625)) + (PORT datac (134:134:134) (177:177:177)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (726:726:726) (845:845:845)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1375:1375:1375) (1629:1629:1629)) + (PORT d[1] (1485:1485:1485) (1680:1680:1680)) + (PORT d[2] (1090:1090:1090) (1255:1255:1255)) + (PORT d[3] (723:723:723) (834:834:834)) + (PORT d[4] (1271:1271:1271) (1447:1447:1447)) + (PORT d[5] (731:731:731) (849:849:849)) + (PORT d[6] (806:806:806) (920:920:920)) + (PORT d[7] (1360:1360:1360) (1562:1562:1562)) + (PORT d[8] (1271:1271:1271) (1499:1499:1499)) + (PORT d[9] (596:596:596) (690:690:690)) + (PORT d[10] (577:577:577) (670:670:670)) + (PORT d[11] (814:814:814) (927:927:927)) + (PORT d[12] (427:427:427) (501:501:501)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1008:1008:1008) (1096:1096:1096)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (1000:1000:1000) (1066:1066:1066)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1069:1069:1069) (1085:1085:1085)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (609:609:609) (617:617:617)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1133:1133:1133)) + (PORT asdata (1105:1105:1105) (1235:1235:1235)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (948:948:948) (1074:1074:1074)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (627:627:627)) + (PORT datab (488:488:488) (565:565:565)) + (PORT datac (632:632:632) (729:729:729)) + (PORT datad (545:545:545) (632:632:632)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1088:1088:1088) (1296:1296:1296)) + (PORT datac (1131:1131:1131) (1335:1335:1335)) + (PORT datad (798:798:798) (935:935:935)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (844:844:844) (957:957:957)) + (PORT clk (1087:1087:1087) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1132:1132:1132) (1327:1327:1327)) + (PORT d[1] (1413:1413:1413) (1585:1585:1585)) + (PORT d[2] (1512:1512:1512) (1758:1758:1758)) + (PORT d[3] (641:641:641) (732:732:732)) + (PORT d[4] (1385:1385:1385) (1601:1601:1601)) + (PORT d[5] (1798:1798:1798) (2049:2049:2049)) + (PORT d[6] (1232:1232:1232) (1397:1397:1397)) + (PORT d[7] (1025:1025:1025) (1147:1147:1147)) + (PORT d[8] (1409:1409:1409) (1643:1643:1643)) + (PORT d[9] (953:953:953) (1074:1074:1074)) + (PORT d[10] (1443:1443:1443) (1625:1625:1625)) + (PORT d[11] (2339:2339:2339) (2720:2720:2720)) + (PORT d[12] (1426:1426:1426) (1614:1614:1614)) + (PORT clk (1085:1085:1085) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1115:1115:1115) (1203:1203:1203)) + (PORT clk (1085:1085:1085) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1106:1106:1106)) + (PORT d[0] (1200:1200:1200) (1274:1274:1274)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1067:1067:1067) (1085:1085:1085)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (607:607:607) (617:617:617)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (266:266:266)) + (PORT datab (690:690:690) (800:800:800)) + (PORT datac (694:694:694) (798:798:798)) + (PORT datad (770:770:770) (887:887:887)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1088:1088:1088) (1297:1297:1297)) + (PORT datac (1131:1131:1131) (1334:1334:1334)) + (PORT datad (799:799:799) (936:936:936)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (464:464:464) (519:519:519)) + (PORT clk (1096:1096:1096) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1720:1720:1720) (2007:2007:2007)) + (PORT d[1] (1938:1938:1938) (2220:2220:2220)) + (PORT d[2] (859:859:859) (991:991:991)) + (PORT d[3] (2305:2305:2305) (2612:2612:2612)) + (PORT d[4] (1680:1680:1680) (1971:1971:1971)) + (PORT d[5] (2530:2530:2530) (2887:2887:2887)) + (PORT d[6] (1261:1261:1261) (1431:1431:1431)) + (PORT d[7] (2287:2287:2287) (2600:2600:2600)) + (PORT d[8] (864:864:864) (986:986:986)) + (PORT d[9] (1228:1228:1228) (1402:1402:1402)) + (PORT d[10] (1305:1305:1305) (1482:1482:1482)) + (PORT d[11] (1796:1796:1796) (2105:2105:2105)) + (PORT d[12] (2451:2451:2451) (2782:2782:2782)) + (PORT clk (1094:1094:1094) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1083:1083:1083) (1166:1166:1166)) + (PORT clk (1094:1094:1094) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1114:1114:1114)) + (PORT d[0] (1535:1535:1535) (1652:1652:1652)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1076:1076:1076) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (819:819:819) (914:914:914)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (491:491:491) (554:554:554)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (269:269:269)) + (PORT datab (686:686:686) (796:796:796)) + (PORT datac (693:693:693) (797:797:797)) + (PORT datad (767:767:767) (884:884:884)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1085:1085:1085) (1293:1293:1293)) + (PORT datac (1132:1132:1132) (1335:1335:1335)) + (PORT datad (795:795:795) (931:931:931)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (720:720:720) (836:836:836)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1235:1235:1235) (1473:1473:1473)) + (PORT d[1] (1304:1304:1304) (1475:1475:1475)) + (PORT d[2] (925:925:925) (1064:1064:1064)) + (PORT d[3] (1424:1424:1424) (1622:1622:1622)) + (PORT d[4] (1291:1291:1291) (1472:1472:1472)) + (PORT d[5] (895:895:895) (1031:1031:1031)) + (PORT d[6] (964:964:964) (1094:1094:1094)) + (PORT d[7] (1247:1247:1247) (1418:1418:1418)) + (PORT d[8] (1400:1400:1400) (1648:1648:1648)) + (PORT d[9] (616:616:616) (713:713:713)) + (PORT d[10] (977:977:977) (1120:1120:1120)) + (PORT d[11] (795:795:795) (908:908:908)) + (PORT d[12] (584:584:584) (674:674:674)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (859:859:859) (926:926:926)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (1107:1107:1107) (1184:1184:1184)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (668:668:668)) + (PORT datab (829:829:829) (972:972:972)) + (PORT datac (760:760:760) (888:888:888)) + (PORT datad (838:838:838) (961:961:961)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (735:735:735) (846:846:846)) + (PORT datab (1036:1036:1036) (1217:1217:1217)) + (PORT datac (945:945:945) (1071:1071:1071)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (271:271:271)) + (PORT datab (682:682:682) (791:791:791)) + (PORT datac (693:693:693) (796:796:796)) + (PORT datad (764:764:764) (881:881:881)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE CLOCK_50\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (91:91:91) (78:78:78)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\~0) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (311:311:311)) + (PORT datab (521:521:521) (622:622:622)) + (PORT datac (383:383:383) (466:466:466)) + (PORT datad (397:397:397) (476:476:476)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (923:923:923)) + (PORT asdata (531:531:531) (596:596:596)) + (PORT ena (421:421:421) (441:441:441)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (469:469:469) (543:543:543)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (441:441:441)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT datac (482:482:482) (575:575:575)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (441:441:441)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~0) + (DELAY + (ABSOLUTE + (PORT datac (487:487:487) (580:580:580)) + (PORT datad (473:473:473) (556:556:556)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (441:441:441)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (508:508:508) (602:602:602)) + (PORT datab (487:487:487) (581:581:581)) + (PORT datad (473:473:473) (552:552:552)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (161:161:161) (176:176:176)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (441:441:441)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (815:815:815)) + (PORT datab (328:328:328) (394:394:394)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (479:479:479)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~4) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (449:449:449)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~6) + (DELAY + (ABSOLUTE + (PORT datab (497:497:497) (585:585:585)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (487:487:487) (511:511:511)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~8) + (DELAY + (ABSOLUTE + (PORT dataa (507:507:507) (601:601:601)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (487:487:487) (511:511:511)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~10) + (DELAY + (ABSOLUTE + (PORT datab (508:508:508) (597:597:597)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (487:487:487) (511:511:511)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~12) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (468:468:468)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (611:611:611)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[8\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (240:240:240) (311:311:311)) + (PORT datab (519:519:519) (619:619:619)) + (PORT datac (383:383:383) (467:467:467)) + (PORT datad (396:396:396) (475:475:475)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (501:501:501) (544:544:544)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~14) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (690:690:690)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (508:508:508) (603:603:603)) + (PORT datac (96:96:96) (121:121:121)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (501:501:501) (544:544:544)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (311:311:311)) + (PORT datab (529:529:529) (630:630:630)) + (PORT datac (378:378:378) (461:461:461)) + (PORT datad (402:402:402) (481:481:481)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (176:176:176) (214:214:214)) + (PORT datab (191:191:191) (230:230:230)) + (PORT datad (400:400:400) (479:479:479)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT datac (490:490:490) (586:586:586)) + (PORT datad (95:95:95) (113:113:113)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (501:501:501) (544:544:544)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (507:507:507) (602:602:602)) + (PORT datac (97:97:97) (121:121:121)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (923:923:923)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (501:501:501) (544:544:544)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (735:735:735) (829:829:829)) + (PORT clk (1094:1094:1094) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1608:1608:1608) (1867:1867:1867)) + (PORT d[1] (1744:1744:1744) (1971:1971:1971)) + (PORT d[2] (1135:1135:1135) (1322:1322:1322)) + (PORT d[3] (1254:1254:1254) (1442:1442:1442)) + (PORT d[4] (1170:1170:1170) (1365:1365:1365)) + (PORT d[5] (1078:1078:1078) (1241:1241:1241)) + (PORT d[6] (1331:1331:1331) (1531:1531:1531)) + (PORT d[7] (1089:1089:1089) (1253:1253:1253)) + (PORT d[8] (1806:1806:1806) (2077:2077:2077)) + (PORT d[9] (1197:1197:1197) (1383:1383:1383)) + (PORT d[10] (2072:2072:2072) (2375:2375:2375)) + (PORT d[11] (1367:1367:1367) (1575:1575:1575)) + (PORT d[12] (1169:1169:1169) (1350:1350:1350)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1028:1028:1028) (1112:1112:1112)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1112:1112:1112)) + (PORT d[0] (1982:1982:1982) (1835:1835:1835)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1069:1069:1069)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1042:1042:1042) (1187:1187:1187)) + (PORT clk (1054:1054:1054) (1072:1072:1072)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2529:2529:2529) (2874:2874:2874)) + (PORT d[1] (2502:2502:2502) (2849:2849:2849)) + (PORT d[2] (2529:2529:2529) (2862:2862:2862)) + (PORT d[3] (2417:2417:2417) (2749:2749:2749)) + (PORT d[4] (2461:2461:2461) (2781:2781:2781)) + (PORT d[5] (2504:2504:2504) (2838:2838:2838)) + (PORT d[6] (2487:2487:2487) (2825:2825:2825)) + (PORT d[7] (2498:2498:2498) (2836:2836:2836)) + (PORT d[8] (2604:2604:2604) (2962:2962:2962)) + (PORT d[9] (2455:2455:2455) (2815:2815:2815)) + (PORT d[10] (2483:2483:2483) (2787:2787:2787)) + (PORT d[11] (2491:2491:2491) (2833:2833:2833)) + (PORT d[12] (2454:2454:2454) (2779:2779:2779)) + (PORT clk (1051:1051:1051) (1071:1071:1071)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1054:1054:1054) (1072:1072:1072)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1073:1073:1073)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1073:1073:1073)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1073:1073:1073)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1073:1073:1073)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1070:1070:1070)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (822:822:822) (935:935:935)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (118:118:118) (155:155:155)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (760:760:760)) + (PORT datab (718:718:718) (826:826:826)) + (PORT datac (810:810:810) (926:926:926)) + (PORT datad (645:645:645) (739:739:739)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (673:673:673) (757:757:757)) + (PORT clk (1086:1086:1086) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1787:1787:1787) (2069:2069:2069)) + (PORT d[1] (1219:1219:1219) (1392:1392:1392)) + (PORT d[2] (948:948:948) (1104:1104:1104)) + (PORT d[3] (898:898:898) (1029:1029:1029)) + (PORT d[4] (1523:1523:1523) (1770:1770:1770)) + (PORT d[5] (900:900:900) (1036:1036:1036)) + (PORT d[6] (1152:1152:1152) (1324:1324:1324)) + (PORT d[7] (1063:1063:1063) (1230:1230:1230)) + (PORT d[8] (1977:1977:1977) (2270:2270:2270)) + (PORT d[9] (1004:1004:1004) (1160:1160:1160)) + (PORT d[10] (963:963:963) (1117:1117:1117)) + (PORT d[11] (909:909:909) (1063:1063:1063)) + (PORT d[12] (986:986:986) (1141:1141:1141)) + (PORT clk (1084:1084:1084) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (786:786:786) (847:847:847)) + (PORT clk (1084:1084:1084) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1086:1086:1086) (1104:1104:1104)) + (PORT d[0] (1631:1631:1631) (1777:1777:1777)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1041:1041:1041) (1061:1061:1061)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (847:847:847) (964:964:964)) + (PORT clk (1046:1046:1046) (1064:1064:1064)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2496:2496:2496) (2834:2834:2834)) + (PORT d[1] (2448:2448:2448) (2754:2754:2754)) + (PORT d[2] (2471:2471:2471) (2795:2795:2795)) + (PORT d[3] (2427:2427:2427) (2753:2753:2753)) + (PORT d[4] (2452:2452:2452) (2797:2797:2797)) + (PORT d[5] (2475:2475:2475) (2817:2817:2817)) + (PORT d[6] (2455:2455:2455) (2758:2758:2758)) + (PORT d[7] (2458:2458:2458) (2799:2799:2799)) + (PORT d[8] (2517:2517:2517) (2872:2872:2872)) + (PORT d[9] (2509:2509:2509) (2856:2856:2856)) + (PORT d[10] (2527:2527:2527) (2866:2866:2866)) + (PORT d[11] (2535:2535:2535) (2877:2877:2877)) + (PORT d[12] (2446:2446:2446) (2777:2777:2777)) + (PORT clk (1043:1043:1043) (1063:1063:1063)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1046:1046:1046) (1064:1064:1064)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1065:1065:1065)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1065:1065:1065)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1065:1065:1065)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1065:1065:1065)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1881:1881:1881) (2187:2187:2187)) + (PORT d[1] (1935:1935:1935) (2211:2211:2211)) + (PORT d[2] (826:826:826) (944:944:944)) + (PORT d[3] (2281:2281:2281) (2583:2583:2583)) + (PORT d[4] (1690:1690:1690) (1986:1986:1986)) + (PORT d[5] (2522:2522:2522) (2878:2878:2878)) + (PORT d[6] (1589:1589:1589) (1811:1811:1811)) + (PORT d[7] (981:981:981) (1113:1113:1113)) + (PORT d[8] (1117:1117:1117) (1267:1267:1267)) + (PORT d[9] (1234:1234:1234) (1409:1409:1409)) + (PORT d[10] (1319:1319:1319) (1498:1498:1498)) + (PORT d[11] (1776:1776:1776) (2078:2078:2078)) + (PORT d[12] (2525:2525:2525) (2857:2857:2857)) + (PORT clk (1094:1094:1094) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1110:1110:1110)) + (PORT d[0] (1113:1113:1113) (1229:1229:1229)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1076:1076:1076) (1091:1091:1091)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (623:623:623)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (624:624:624)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (624:624:624)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (624:624:624)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (533:533:533) (624:624:624)) + (PORT datab (167:167:167) (219:219:219)) + (PORT datac (509:509:509) (571:571:571)) + (PORT datad (576:576:576) (655:655:655)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1111:1111:1111) (1295:1295:1295)) + (PORT d[1] (1500:1500:1500) (1693:1693:1693)) + (PORT d[2] (1390:1390:1390) (1602:1602:1602)) + (PORT d[3] (1723:1723:1723) (1945:1945:1945)) + (PORT d[4] (1283:1283:1283) (1479:1479:1479)) + (PORT d[5] (1752:1752:1752) (1994:1994:1994)) + (PORT d[6] (1635:1635:1635) (1858:1858:1858)) + (PORT d[7] (1803:1803:1803) (2055:2055:2055)) + (PORT d[8] (1353:1353:1353) (1548:1548:1548)) + (PORT d[9] (1781:1781:1781) (2030:2030:2030)) + (PORT d[10] (1287:1287:1287) (1461:1461:1461)) + (PORT d[11] (1418:1418:1418) (1651:1651:1651)) + (PORT d[12] (1894:1894:1894) (2151:2151:2151)) + (PORT clk (1105:1105:1105) (1122:1122:1122)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1122:1122:1122)) + (PORT d[0] (1878:1878:1878) (1681:1681:1681)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1123:1123:1123)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1103:1103:1103)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (627:627:627) (635:635:635)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (628:628:628) (636:636:636)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (628:628:628) (636:636:636)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (628:628:628) (636:636:636)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (668:668:668)) + (PORT datab (826:826:826) (960:960:960)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (942:942:942) (1075:1075:1075)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (759:759:759)) + (PORT datab (168:168:168) (220:220:220)) + (PORT datac (94:94:94) (117:117:117)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~119) + (DELAY + (ABSOLUTE + (PORT dataa (762:762:762) (890:890:890)) + (PORT datab (1311:1311:1311) (1547:1547:1547)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (181:181:181) (175:175:175)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (703:703:703) (816:816:816)) + (PORT datab (331:331:331) (384:384:384)) + (PORT datac (456:456:456) (529:529:529)) + (PORT datad (167:167:167) (198:198:198)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1235:1235:1235) (1412:1412:1412)) + (PORT datab (332:332:332) (385:385:385)) + (PORT datac (947:947:947) (1099:1099:1099)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (146:146:146)) + (PORT datab (789:789:789) (897:897:897)) + (PORT datac (600:600:600) (692:692:692)) + (PORT datad (179:179:179) (202:202:202)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (715:715:715)) + (PORT datab (811:811:811) (957:957:957)) + (PORT datac (1187:1187:1187) (1391:1391:1391)) + (PORT datad (953:953:953) (1134:1134:1134)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (1078:1078:1078)) + (PORT datab (281:281:281) (328:328:328)) + (PORT datac (544:544:544) (614:614:614)) + (PORT datad (620:620:620) (710:710:710)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (598:598:598) (635:635:635)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (718:718:718)) + (PORT datab (127:127:127) (161:161:161)) + (PORT datac (442:442:442) (513:513:513)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (141:141:141)) + (PORT datac (599:599:599) (690:690:690)) + (PORT datad (120:120:120) (144:144:144)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (264:264:264)) + (PORT datab (134:134:134) (169:169:169)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (116:116:116) (140:140:140)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|ir_\|opcode\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (329:329:329) (380:380:380)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (726:726:726)) + (PORT datab (1638:1638:1638) (1881:1881:1881)) + (PORT datac (782:782:782) (920:920:920)) + (PORT datad (451:451:451) (535:535:535)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (927:927:927) (910:910:910)) + (PORT ena (1203:1203:1203) (1324:1324:1324)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1038:1038:1038) (1217:1217:1217)) + (PORT datab (957:957:957) (1143:1143:1143)) + (PORT datac (969:969:969) (1121:1121:1121)) + (PORT datad (475:475:475) (551:551:551)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (417:417:417)) + (PORT datab (439:439:439) (510:510:510)) + (PORT datac (180:180:180) (210:210:210)) + (PORT datad (328:328:328) (376:376:376)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (594:594:594)) + (PORT datab (663:663:663) (758:758:758)) + (PORT datac (641:641:641) (735:735:735)) + (PORT datad (646:646:646) (739:739:739)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (174:174:174) (216:216:216)) + (PORT datab (115:115:115) (143:143:143)) + (PORT datac (464:464:464) (530:530:530)) + (PORT datad (114:114:114) (136:136:136)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (457:457:457) (535:535:535)) + (PORT datac (442:442:442) (510:510:510)) + (PORT datad (444:444:444) (504:504:504)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (498:498:498) (576:576:576)) + (PORT datab (482:482:482) (564:564:564)) + (PORT datac (431:431:431) (494:494:494)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (313:313:313) (372:372:372)) + (PORT datab (641:641:641) (739:739:739)) + (PORT datac (479:479:479) (569:569:569)) + (PORT datad (307:307:307) (359:359:359)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (728:728:728) (835:835:835)) + (PORT datac (339:339:339) (392:392:392)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[6\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (460:460:460) (538:538:538)) + (PORT datab (364:364:364) (432:432:432)) + (PORT datac (444:444:444) (514:514:514)) + (PORT datad (445:445:445) (506:506:506)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (452:452:452) (524:524:524)) + (PORT datac (180:180:180) (218:218:218)) + (PORT datad (452:452:452) (523:523:523)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (493:493:493) (584:584:584)) + (PORT datab (343:343:343) (402:402:402)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (314:314:314) (365:365:365)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (714:714:714)) + (PORT datab (133:133:133) (168:168:168)) + (PORT datad (659:659:659) (767:767:767)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (659:659:659) (756:756:756)) + (PORT d[0] (721:721:721) (836:836:836)) (PORT clk (1087:1087:1087) (1104:1104:1104)) ) ) @@ -30842,19 +35042,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2260:2260:2260) (2618:2618:2618)) - (PORT d[1] (967:967:967) (1145:1145:1145)) - (PORT d[2] (1935:1935:1935) (2216:2216:2216)) - (PORT d[3] (1210:1210:1210) (1410:1410:1410)) - (PORT d[4] (1232:1232:1232) (1428:1428:1428)) - (PORT d[5] (955:955:955) (1125:1125:1125)) - (PORT d[6] (1005:1005:1005) (1163:1163:1163)) - (PORT d[7] (1786:1786:1786) (2020:2020:2020)) - (PORT d[8] (1927:1927:1927) (2239:2239:2239)) - (PORT d[9] (1000:1000:1000) (1155:1155:1155)) - (PORT d[10] (1873:1873:1873) (2157:2157:2157)) - (PORT d[11] (1185:1185:1185) (1369:1369:1369)) - (PORT d[12] (1018:1018:1018) (1175:1175:1175)) + (PORT d[0] (1394:1394:1394) (1654:1654:1654)) + (PORT d[1] (1497:1497:1497) (1696:1696:1696)) + (PORT d[2] (714:714:714) (817:817:817)) + (PORT d[3] (719:719:719) (824:824:824)) + (PORT d[4] (1134:1134:1134) (1301:1301:1301)) + (PORT d[5] (710:710:710) (820:820:820)) + (PORT d[6] (819:819:819) (938:938:938)) + (PORT d[7] (1361:1361:1361) (1563:1563:1563)) + (PORT d[8] (1402:1402:1402) (1657:1657:1657)) + (PORT d[9] (440:440:440) (517:517:517)) + (PORT d[10] (994:994:994) (1138:1138:1138)) + (PORT d[11] (649:649:649) (747:747:747)) + (PORT d[12] (413:413:413) (480:480:480)) (PORT clk (1085:1085:1085) (1102:1102:1102)) ) ) @@ -30867,7 +35067,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1271:1271:1271) (1396:1396:1396)) + (PORT d[0] (1010:1010:1010) (1099:1099:1099)) (PORT clk (1085:1085:1085) (1102:1102:1102)) ) ) @@ -30881,7 +35081,7 @@ (DELAY (ABSOLUTE (PORT clk (1087:1087:1087) (1104:1104:1104)) - (PORT d[0] (1658:1658:1658) (1820:1820:1820)) + (PORT d[0] (999:999:999) (1065:1065:1065)) ) ) ) @@ -30978,48 +35178,308 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~90) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (319:319:319) (368:368:368)) - (PORT datab (518:518:518) (618:618:618)) - (PORT datac (460:460:460) (513:513:513)) - (PORT datad (632:632:632) (741:741:741)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT d[0] (536:536:536) (602:602:602)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1429:1429:1429) (1672:1672:1672)) + (PORT d[1] (704:704:704) (809:809:809)) + (PORT d[2] (954:954:954) (1113:1113:1113)) + (PORT d[3] (922:922:922) (1066:1066:1066)) + (PORT d[4] (1719:1719:1719) (1992:1992:1992)) + (PORT d[5] (707:707:707) (817:817:817)) + (PORT d[6] (884:884:884) (1026:1026:1026)) + (PORT d[7] (723:723:723) (837:837:837)) + (PORT d[8] (701:701:701) (818:818:818)) + (PORT d[9] (634:634:634) (737:737:737)) + (PORT d[10] (622:622:622) (725:725:725)) + (PORT d[11] (1272:1272:1272) (1486:1486:1486)) + (PORT d[12] (635:635:635) (743:743:743)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (674:674:674) (711:711:711)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (1298:1298:1298) (1395:1395:1395)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) (DELAY (ABSOLUTE - (PORT dataa (370:370:370) (447:447:447)) - (PORT datab (143:143:143) (181:181:181)) - (PORT datac (194:194:194) (236:236:236)) - (PORT datad (702:702:702) (789:789:789)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) (DELAY (ABSOLUTE - (PORT datab (1165:1165:1165) (1354:1354:1354)) - (PORT datac (622:622:622) (731:731:731)) - (PORT datad (628:628:628) (735:735:735)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (714:714:714) (831:831:831)) + (PORT clk (1082:1082:1082) (1100:1100:1100)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1565:1565:1565) (1849:1849:1849)) + (PORT d[1] (1665:1665:1665) (1885:1885:1885)) + (PORT d[2] (698:698:698) (799:799:799)) + (PORT d[3] (547:547:547) (641:641:641)) + (PORT d[4] (1165:1165:1165) (1328:1328:1328)) + (PORT d[5] (530:530:530) (613:613:613)) + (PORT d[6] (787:787:787) (900:900:900)) + (PORT d[7] (1536:1536:1536) (1760:1760:1760)) + (PORT d[8] (1422:1422:1422) (1679:1679:1679)) + (PORT d[9] (419:419:419) (488:488:488)) + (PORT d[10] (421:421:421) (496:496:496)) + (PORT d[11] (1641:1641:1641) (1917:1917:1917)) + (PORT d[12] (392:392:392) (458:458:458)) + (PORT clk (1080:1080:1080) (1098:1098:1098)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (687:687:687) (733:733:733)) + (PORT clk (1080:1080:1080) (1098:1098:1098)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1082:1082:1082) (1100:1100:1100)) + (PORT d[0] (783:783:783) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1083:1083:1083) (1101:1101:1101)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1083:1083:1083) (1101:1101:1101)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1083:1083:1083) (1101:1101:1101)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1083:1083:1083) (1101:1101:1101)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1062:1062:1062) (1079:1079:1079)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (602:602:602) (611:611:611)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (603:603:603) (612:612:612)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (603:603:603) (612:612:612)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (603:603:603) (612:612:612)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) @@ -31028,8 +35488,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (679:679:679) (760:760:760)) - (PORT clk (1092:1092:1092) (1110:1110:1110)) + (PORT d[0] (366:366:366) (419:419:419)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) ) ) (TIMINGCHECK @@ -31041,20 +35501,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2377:2377:2377) (2744:2744:2744)) - (PORT d[1] (1350:1350:1350) (1590:1590:1590)) - (PORT d[2] (1850:1850:1850) (2107:2107:2107)) - (PORT d[3] (1476:1476:1476) (1736:1736:1736)) - (PORT d[4] (1493:1493:1493) (1748:1748:1748)) - (PORT d[5] (1642:1642:1642) (1906:1906:1906)) - (PORT d[6] (1107:1107:1107) (1279:1279:1279)) - (PORT d[7] (1510:1510:1510) (1712:1712:1712)) - (PORT d[8] (1945:1945:1945) (2280:2280:2280)) - (PORT d[9] (1660:1660:1660) (1922:1922:1922)) - (PORT d[10] (2963:2963:2963) (3389:3389:3389)) - (PORT d[11] (1075:1075:1075) (1261:1261:1261)) - (PORT d[12] (1256:1256:1256) (1442:1442:1442)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT d[0] (1562:1562:1562) (1830:1830:1830)) + (PORT d[1] (738:738:738) (848:848:848)) + (PORT d[2] (946:946:946) (1107:1107:1107)) + (PORT d[3] (892:892:892) (1029:1029:1029)) + (PORT d[4] (1710:1710:1710) (1975:1975:1975)) + (PORT d[5] (716:716:716) (826:826:826)) + (PORT d[6] (858:858:858) (995:995:995)) + (PORT d[7] (903:903:903) (1049:1049:1049)) + (PORT d[8] (879:879:879) (1017:1017:1017)) + (PORT d[9] (808:808:808) (935:935:935)) + (PORT d[10] (773:773:773) (895:895:895)) + (PORT d[11] (1077:1077:1077) (1257:1257:1257)) + (PORT d[12] (807:807:807) (938:938:938)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) ) ) (TIMINGCHECK @@ -31066,8 +35526,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1116:1116:1116) (1216:1216:1216)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT d[0] (695:695:695) (741:741:741)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) ) ) (TIMINGCHECK @@ -31079,8 +35539,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (PORT d[0] (1226:1226:1226) (1303:1303:1303)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (1481:1481:1481) (1627:1627:1627)) ) ) ) @@ -31089,7 +35549,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) @@ -31099,7 +35559,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -31109,7 +35569,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -31119,7 +35579,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -31129,7 +35589,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1072:1072:1072) (1089:1089:1089)) + (PORT clk (1071:1071:1071) (1087:1087:1087)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -31143,7 +35603,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) + (PORT clk (611:611:611) (619:619:619)) ) ) ) @@ -31152,7 +35612,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) + (PORT clk (612:612:612) (620:620:620)) ) ) ) @@ -31161,7 +35621,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) + (PORT clk (612:612:612) (620:620:620)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -31171,536 +35631,49 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) + (PORT clk (612:612:612) (620:620:620)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~91) + (INSTANCE D\[6\]\~103) (DELAY (ABSOLUTE - (PORT dataa (456:456:456) (524:524:524)) - (PORT datab (782:782:782) (914:914:914)) - (PORT datac (163:163:163) (191:191:191)) - (PORT datad (617:617:617) (704:704:704)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (444:444:444)) - (PORT datab (136:136:136) (174:174:174)) - (PORT datac (189:189:189) (231:231:231)) - (PORT datad (702:702:702) (789:789:789)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE CLOCK_50\~inputclkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (91:91:91) (78:78:78)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (558:558:558) (639:639:639)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\~0) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (811:811:811)) - (PORT datab (535:535:535) (640:640:640)) - (PORT datac (530:530:530) (634:634:634)) - (PORT datad (151:151:151) (199:199:199)) - (IOPATH dataa combout (188:188:188) (203:203:203)) + (PORT dataa (783:783:783) (913:913:913)) + (PORT datab (686:686:686) (788:788:788)) + (PORT datad (783:783:783) (893:893:893)) + (IOPATH dataa combout (195:195:195) (203:203:203)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (629:629:629) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) - (PORT asdata (643:643:643) (725:725:725)) - (PORT ena (629:629:629) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT datac (479:479:479) (568:568:568)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (629:629:629) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~0) - (DELAY - (ABSOLUTE - (PORT datac (475:475:475) (562:562:562)) - (PORT datad (789:789:789) (916:916:916)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (629:629:629) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (497:497:497) (586:586:586)) - (PORT datac (762:762:762) (879:879:879)) - (PORT datad (789:789:789) (916:916:916)) - (IOPATH dataa combout (166:166:166) (173:173:173)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (629:629:629) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (465:465:465)) - (PORT datab (398:398:398) (477:477:477)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~2) - (DELAY - (ABSOLUTE - (PORT datab (347:347:347) (425:425:425)) - (IOPATH datab combout (167:167:167) (174:174:174)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~4) - (DELAY - (ABSOLUTE - (PORT datab (372:372:372) (452:452:452)) - (IOPATH datab combout (188:188:188) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~6) - (DELAY - (ABSOLUTE - (PORT datab (376:376:376) (457:457:457)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (629:629:629) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~8) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (470:470:470)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (629:629:629) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~10) - (DELAY - (ABSOLUTE - (PORT dataa (520:520:520) (618:618:618)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (629:629:629) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~12) - (DELAY - (ABSOLUTE - (PORT datab (379:379:379) (452:452:452)) - (IOPATH datab combout (188:188:188) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector6\~0) - (DELAY - (ABSOLUTE - (PORT datab (331:331:331) (390:390:390)) - (PORT datac (306:306:306) (357:357:357)) - (PORT datad (526:526:526) (625:625:625)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[9\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (811:811:811)) - (PORT datab (533:533:533) (638:638:638)) - (PORT datac (533:533:533) (638:638:638)) - (PORT datad (155:155:155) (204:204:204)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~14) - (DELAY - (ABSOLUTE - (PORT datad (384:384:384) (462:462:462)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (413:413:413)) - (PORT datac (429:429:429) (491:491:491)) - (PORT datad (526:526:526) (625:625:625)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (809:809:809)) - (PORT datab (529:529:529) (634:634:634)) - (PORT datac (538:538:538) (643:643:643)) - (PORT datad (158:158:158) (207:207:207)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (392:392:392)) - (PORT datab (557:557:557) (667:667:667)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector3\~0) + (INSTANCE D\[6\]\~104) (DELAY (ABSOLUTE - (PORT datab (332:332:332) (391:391:391)) - (PORT datad (526:526:526) (625:625:625)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector2\~0) - (DELAY - (ABSOLUTE - (PORT datac (333:333:333) (392:392:392)) - (PORT datad (525:525:525) (625:625:625)) + (PORT dataa (848:848:848) (982:982:982)) + (PORT datab (1036:1036:1036) (1216:1216:1216)) + (PORT datac (805:805:805) (919:919:919)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (875:875:875) (1007:1007:1007)) - (PORT clk (1099:1099:1099) (1117:1117:1117)) + (PORT d[0] (711:711:711) (800:800:800)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) ) ) (TIMINGCHECK @@ -31712,20 +35685,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1463:1463:1463) (1667:1667:1667)) - (PORT d[1] (1368:1368:1368) (1613:1613:1613)) - (PORT d[2] (1329:1329:1329) (1557:1557:1557)) - (PORT d[3] (1137:1137:1137) (1317:1317:1317)) - (PORT d[4] (1716:1716:1716) (2014:2014:2014)) - (PORT d[5] (1231:1231:1231) (1458:1458:1458)) - (PORT d[6] (908:908:908) (1038:1038:1038)) - (PORT d[7] (933:933:933) (1073:1073:1073)) - (PORT d[8] (1605:1605:1605) (1884:1884:1884)) - (PORT d[9] (1200:1200:1200) (1368:1368:1368)) - (PORT d[10] (1231:1231:1231) (1400:1400:1400)) - (PORT d[11] (1813:1813:1813) (2074:2074:2074)) - (PORT d[12] (1246:1246:1246) (1439:1439:1439)) - (PORT clk (1097:1097:1097) (1115:1115:1115)) + (PORT d[0] (1615:1615:1615) (1876:1876:1876)) + (PORT d[1] (1067:1067:1067) (1221:1221:1221)) + (PORT d[2] (1116:1116:1116) (1300:1300:1300)) + (PORT d[3] (1254:1254:1254) (1439:1439:1439)) + (PORT d[4] (1344:1344:1344) (1567:1567:1567)) + (PORT d[5] (1077:1077:1077) (1240:1240:1240)) + (PORT d[6] (1333:1333:1333) (1537:1537:1537)) + (PORT d[7] (1260:1260:1260) (1457:1457:1457)) + (PORT d[8] (1796:1796:1796) (2065:2065:2065)) + (PORT d[9] (1038:1038:1038) (1201:1201:1201)) + (PORT d[10] (964:964:964) (1114:1114:1114)) + (PORT d[11] (1379:1379:1379) (1587:1587:1587)) + (PORT d[12] (1429:1429:1429) (1641:1641:1641)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) ) ) (TIMINGCHECK @@ -31737,8 +35710,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1536:1536:1536) (1684:1684:1684)) - (PORT clk (1097:1097:1097) (1115:1115:1115)) + (PORT d[0] (1017:1017:1017) (1099:1099:1099)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) ) ) (TIMINGCHECK @@ -31750,8 +35723,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1099:1099:1099) (1117:1117:1117)) - (PORT d[0] (1721:1721:1721) (1605:1605:1605)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (1978:1978:1978) (1828:1828:1828)) ) ) ) @@ -31760,7 +35733,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1100:1100:1100) (1118:1118:1118)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) @@ -31770,7 +35743,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1100:1100:1100) (1118:1118:1118)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -31780,7 +35753,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1100:1100:1100) (1118:1118:1118)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -31790,7 +35763,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1100:1100:1100) (1118:1118:1118)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -31800,7 +35773,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1054:1054:1054) (1074:1074:1074)) + (PORT clk (1046:1046:1046) (1065:1065:1065)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -31814,8 +35787,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1208:1208:1208) (1358:1358:1358)) - (PORT clk (1059:1059:1059) (1077:1077:1077)) + (PORT d[0] (1053:1053:1053) (1202:1202:1202)) + (PORT clk (1051:1051:1051) (1068:1068:1068)) ) ) (TIMINGCHECK @@ -31827,20 +35800,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2557:2557:2557) (2902:2902:2902)) - (PORT d[1] (2446:2446:2446) (2755:2755:2755)) - (PORT d[2] (2547:2547:2547) (2893:2893:2893)) - (PORT d[3] (2605:2605:2605) (2960:2960:2960)) - (PORT d[4] (2353:2353:2353) (2651:2651:2651)) - (PORT d[5] (2406:2406:2406) (2710:2710:2710)) - (PORT d[6] (2575:2575:2575) (2938:2938:2938)) - (PORT d[7] (2406:2406:2406) (2709:2709:2709)) - (PORT d[8] (2610:2610:2610) (2940:2940:2940)) - (PORT d[9] (2605:2605:2605) (2984:2984:2984)) - (PORT d[10] (2474:2474:2474) (2781:2781:2781)) - (PORT d[11] (2556:2556:2556) (2881:2881:2881)) - (PORT d[12] (2476:2476:2476) (2788:2788:2788)) - (PORT clk (1056:1056:1056) (1076:1076:1076)) + (PORT d[0] (2502:2502:2502) (2839:2839:2839)) + (PORT d[1] (2506:2506:2506) (2855:2855:2855)) + (PORT d[2] (2541:2541:2541) (2875:2875:2875)) + (PORT d[3] (2395:2395:2395) (2721:2721:2721)) + (PORT d[4] (2433:2433:2433) (2757:2757:2757)) + (PORT d[5] (2494:2494:2494) (2837:2837:2837)) + (PORT d[6] (2451:2451:2451) (2781:2781:2781)) + (PORT d[7] (2498:2498:2498) (2835:2835:2835)) + (PORT d[8] (2605:2605:2605) (2960:2960:2960)) + (PORT d[9] (2461:2461:2461) (2814:2814:2814)) + (PORT d[10] (2482:2482:2482) (2811:2811:2811)) + (PORT d[11] (2504:2504:2504) (2853:2853:2853)) + (PORT d[12] (2464:2464:2464) (2791:2791:2791)) + (PORT clk (1048:1048:1048) (1067:1067:1067)) ) ) (TIMINGCHECK @@ -31852,7 +35825,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1059:1059:1059) (1077:1077:1077)) + (PORT clk (1051:1051:1051) (1068:1068:1068)) ) ) ) @@ -31861,7 +35834,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1060:1060:1060) (1078:1078:1078)) + (PORT clk (1052:1052:1052) (1069:1069:1069)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) @@ -31871,7 +35844,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1060:1060:1060) (1078:1078:1078)) + (PORT clk (1052:1052:1052) (1069:1069:1069)) (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) ) ) @@ -31881,7 +35854,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1060:1060:1060) (1078:1078:1078)) + (PORT clk (1052:1052:1052) (1069:1069:1069)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -31891,7 +35864,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1060:1060:1060) (1078:1078:1078)) + (PORT clk (1052:1052:1052) (1069:1069:1069)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -31901,7 +35874,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) (DELAY (ABSOLUTE - (PORT clk (1055:1055:1055) (1075:1075:1075)) + (PORT clk (1047:1047:1047) (1066:1066:1066)) (IOPATH (posedge clk) q (164:164:164) (166:166:166)) ) ) @@ -31910,67 +35883,13 @@ (HOLD d (posedge clk) (90:90:90)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (682:682:682) (804:804:804)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1122:1122:1122) (1154:1154:1154)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (927:927:927) (1048:1048:1048)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (369:369:369) (445:445:445)) - (PORT datab (139:139:139) (178:178:178)) - (PORT datac (191:191:191) (233:233:233)) - (PORT datad (702:702:702) (789:789:789)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (857:857:857) (982:982:982)) - (PORT clk (1094:1094:1094) (1111:1111:1111)) + (PORT d[0] (669:669:669) (765:765:765)) + (PORT clk (1088:1088:1088) (1106:1106:1106)) ) ) (TIMINGCHECK @@ -31982,20 +35901,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1642:1642:1642) (1871:1871:1871)) - (PORT d[1] (1395:1395:1395) (1637:1637:1637)) - (PORT d[2] (688:688:688) (789:789:789)) - (PORT d[3] (1143:1143:1143) (1331:1331:1331)) - (PORT d[4] (1700:1700:1700) (1997:1997:1997)) - (PORT d[5] (1414:1414:1414) (1670:1670:1670)) - (PORT d[6] (879:879:879) (1002:1002:1002)) - (PORT d[7] (737:737:737) (847:847:847)) - (PORT d[8] (979:979:979) (1123:1123:1123)) - (PORT d[9] (882:882:882) (1016:1016:1016)) - (PORT d[10] (1266:1266:1266) (1445:1445:1445)) - (PORT d[11] (1830:1830:1830) (2093:2093:2093)) - (PORT d[12] (1100:1100:1100) (1269:1269:1269)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) + (PORT d[0] (1616:1616:1616) (1877:1877:1877)) + (PORT d[1] (1062:1062:1062) (1215:1215:1215)) + (PORT d[2] (1317:1317:1317) (1534:1534:1534)) + (PORT d[3] (1261:1261:1261) (1445:1445:1445)) + (PORT d[4] (1345:1345:1345) (1566:1566:1566)) + (PORT d[5] (1070:1070:1070) (1232:1232:1232)) + (PORT d[6] (1065:1065:1065) (1235:1235:1235)) + (PORT d[7] (1070:1070:1070) (1230:1230:1230)) + (PORT d[8] (1789:1789:1789) (2052:2052:2052)) + (PORT d[9] (1027:1027:1027) (1187:1187:1187)) + (PORT d[10] (2260:2260:2260) (2590:2590:2590)) + (PORT d[11] (1385:1385:1385) (1593:1593:1593)) + (PORT d[12] (995:995:995) (1154:1154:1154)) + (PORT clk (1086:1086:1086) (1104:1104:1104)) ) ) (TIMINGCHECK @@ -32007,8 +35926,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1509:1509:1509) (1656:1656:1656)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) + (PORT d[0] (946:946:946) (1018:1018:1018)) + (PORT clk (1086:1086:1086) (1104:1104:1104)) ) ) (TIMINGCHECK @@ -32020,8 +35939,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (PORT d[0] (1739:1739:1739) (1900:1900:1900)) + (PORT clk (1088:1088:1088) (1106:1106:1106)) + (PORT d[0] (1654:1654:1654) (1809:1809:1809)) ) ) ) @@ -32030,7 +35949,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT clk (1089:1089:1089) (1107:1107:1107)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) @@ -32040,7 +35959,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT clk (1089:1089:1089) (1107:1107:1107)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -32050,7 +35969,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT clk (1089:1089:1089) (1107:1107:1107)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -32060,7 +35979,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT clk (1089:1089:1089) (1107:1107:1107)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) @@ -32070,7 +35989,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1049:1049:1049) (1068:1068:1068)) + (PORT clk (1043:1043:1043) (1063:1063:1063)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -32084,8 +36003,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1204:1204:1204) (1366:1366:1366)) - (PORT clk (1054:1054:1054) (1071:1071:1071)) + (PORT d[0] (1034:1034:1034) (1178:1178:1178)) + (PORT clk (1048:1048:1048) (1066:1066:1066)) ) ) (TIMINGCHECK @@ -32097,20 +36016,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2539:2539:2539) (2882:2882:2882)) - (PORT d[1] (2319:2319:2319) (2617:2617:2617)) - (PORT d[2] (2377:2377:2377) (2701:2701:2701)) - (PORT d[3] (2488:2488:2488) (2836:2836:2836)) - (PORT d[4] (2376:2376:2376) (2699:2699:2699)) - (PORT d[5] (2409:2409:2409) (2733:2733:2733)) - (PORT d[6] (2476:2476:2476) (2830:2830:2830)) - (PORT d[7] (2266:2266:2266) (2556:2556:2556)) - (PORT d[8] (2430:2430:2430) (2726:2726:2726)) - (PORT d[9] (2585:2585:2585) (2963:2963:2963)) - (PORT d[10] (2471:2471:2471) (2777:2777:2777)) - (PORT d[11] (2523:2523:2523) (2853:2853:2853)) - (PORT d[12] (2469:2469:2469) (2781:2781:2781)) - (PORT clk (1051:1051:1051) (1070:1070:1070)) + (PORT d[0] (2498:2498:2498) (2836:2836:2836)) + (PORT d[1] (2472:2472:2472) (2812:2812:2812)) + (PORT d[2] (2474:2474:2474) (2809:2809:2809)) + (PORT d[3] (2399:2399:2399) (2725:2725:2725)) + (PORT d[4] (2442:2442:2442) (2759:2759:2759)) + (PORT d[5] (2503:2503:2503) (2850:2850:2850)) + (PORT d[6] (2484:2484:2484) (2825:2825:2825)) + (PORT d[7] (2478:2478:2478) (2809:2809:2809)) + (PORT d[8] (2621:2621:2621) (2980:2980:2980)) + (PORT d[9] (2503:2503:2503) (2852:2852:2852)) + (PORT d[10] (2504:2504:2504) (2845:2845:2845)) + (PORT d[11] (2543:2543:2543) (2885:2885:2885)) + (PORT d[12] (2459:2459:2459) (2789:2789:2789)) + (PORT clk (1045:1045:1045) (1065:1065:1065)) ) ) (TIMINGCHECK @@ -32122,7 +36041,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1054:1054:1054) (1071:1071:1071)) + (PORT clk (1048:1048:1048) (1066:1066:1066)) ) ) ) @@ -32131,7 +36050,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1055:1055:1055) (1072:1072:1072)) + (PORT clk (1049:1049:1049) (1067:1067:1067)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) @@ -32141,7 +36060,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1055:1055:1055) (1072:1072:1072)) + (PORT clk (1049:1049:1049) (1067:1067:1067)) ) ) ) @@ -32150,7 +36069,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1055:1055:1055) (1072:1072:1072)) + (PORT clk (1049:1049:1049) (1067:1067:1067)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -32160,7 +36079,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1055:1055:1055) (1072:1072:1072)) + (PORT clk (1049:1049:1049) (1067:1067:1067)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -32170,20 +36089,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1426:1426:1426) (1615:1615:1615)) - (PORT d[1] (1269:1269:1269) (1482:1482:1482)) - (PORT d[2] (1336:1336:1336) (1564:1564:1564)) - (PORT d[3] (1228:1228:1228) (1448:1448:1448)) - (PORT d[4] (1698:1698:1698) (1990:1990:1990)) - (PORT d[5] (1326:1326:1326) (1565:1565:1565)) - (PORT d[6] (1094:1094:1094) (1247:1247:1247)) - (PORT d[7] (1243:1243:1243) (1418:1418:1418)) - (PORT d[8] (1582:1582:1582) (1856:1856:1856)) - (PORT d[9] (1014:1014:1014) (1157:1157:1157)) - (PORT d[10] (1002:1002:1002) (1126:1126:1126)) - (PORT d[11] (1757:1757:1757) (2009:2009:2009)) - (PORT d[12] (728:728:728) (843:843:843)) - (PORT clk (1106:1106:1106) (1123:1123:1123)) + (PORT d[0] (1431:1431:1431) (1666:1666:1666)) + (PORT d[1] (1553:1553:1553) (1763:1763:1763)) + (PORT d[2] (1311:1311:1311) (1527:1527:1527)) + (PORT d[3] (1232:1232:1232) (1407:1407:1407)) + (PORT d[4] (983:983:983) (1152:1152:1152)) + (PORT d[5] (1245:1245:1245) (1430:1430:1430)) + (PORT d[6] (1395:1395:1395) (1604:1604:1604)) + (PORT d[7] (1964:1964:1964) (2241:2241:2241)) + (PORT d[8] (1625:1625:1625) (1868:1868:1868)) + (PORT d[9] (1231:1231:1231) (1423:1423:1423)) + (PORT d[10] (1136:1136:1136) (1305:1305:1305)) + (PORT d[11] (1204:1204:1204) (1396:1396:1396)) + (PORT d[12] (1338:1338:1338) (1537:1537:1537)) + (PORT clk (1097:1097:1097) (1115:1115:1115)) ) ) (TIMINGCHECK @@ -32195,8 +36114,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1106:1106:1106) (1123:1123:1123)) - (PORT d[0] (1273:1273:1273) (1427:1427:1427)) + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (PORT d[0] (1502:1502:1502) (1694:1694:1694)) ) ) ) @@ -32205,7 +36124,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1107:1107:1107) (1124:1124:1124)) + (PORT clk (1098:1098:1098) (1116:1116:1116)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -32215,7 +36134,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1088:1088:1088) (1104:1104:1104)) + (PORT clk (1079:1079:1079) (1096:1096:1096)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -32229,7 +36148,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (628:628:628) (636:636:636)) + (PORT clk (619:619:619) (628:628:628)) ) ) ) @@ -32238,7 +36157,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (629:629:629) (637:637:637)) + (PORT clk (620:620:620) (629:629:629)) ) ) ) @@ -32247,7 +36166,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (629:629:629) (637:637:637)) + (PORT clk (620:620:620) (629:629:629)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -32257,23 +36176,23 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (629:629:629) (637:637:637)) + (PORT clk (620:620:620) (629:629:629)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~87) + (INSTANCE D\[6\]\~100) (DELAY (ABSOLUTE - (PORT dataa (740:740:740) (855:855:855)) - (PORT datab (148:148:148) (201:201:201)) - (PORT datac (794:794:794) (897:897:897)) - (PORT datad (908:908:908) (1038:1038:1038)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (648:648:648) (746:746:746)) + (PORT datab (168:168:168) (222:222:222)) + (PORT datac (641:641:641) (738:738:738)) + (PORT datad (835:835:835) (939:939:939)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -32283,20 +36202,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2075:2075:2075) (2400:2400:2400)) - (PORT d[1] (1515:1515:1515) (1769:1769:1769)) - (PORT d[2] (1420:1420:1420) (1623:1623:1623)) - (PORT d[3] (1217:1217:1217) (1428:1428:1428)) - (PORT d[4] (1287:1287:1287) (1509:1509:1509)) - (PORT d[5] (1213:1213:1213) (1425:1425:1425)) - (PORT d[6] (1122:1122:1122) (1294:1294:1294)) - (PORT d[7] (1157:1157:1157) (1309:1309:1309)) - (PORT d[8] (1735:1735:1735) (2028:2028:2028)) - (PORT d[9] (1494:1494:1494) (1731:1731:1731)) - (PORT d[10] (2747:2747:2747) (3134:3134:3134)) - (PORT d[11] (1194:1194:1194) (1379:1379:1379)) - (PORT d[12] (1423:1423:1423) (1629:1629:1629)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) + (PORT d[0] (1119:1119:1119) (1314:1314:1314)) + (PORT d[1] (1753:1753:1753) (2005:2005:2005)) + (PORT d[2] (1295:1295:1295) (1486:1486:1486)) + (PORT d[3] (2116:2116:2116) (2394:2394:2394)) + (PORT d[4] (1504:1504:1504) (1765:1765:1765)) + (PORT d[5] (2354:2354:2354) (2691:2691:2691)) + (PORT d[6] (1569:1569:1569) (1784:1784:1784)) + (PORT d[7] (2124:2124:2124) (2421:2421:2421)) + (PORT d[8] (1150:1150:1150) (1308:1308:1308)) + (PORT d[9] (1244:1244:1244) (1420:1420:1420)) + (PORT d[10] (1352:1352:1352) (1542:1542:1542)) + (PORT d[11] (1599:1599:1599) (1874:1874:1874)) + (PORT d[12] (2275:2275:2275) (2585:2585:2585)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) ) ) (TIMINGCHECK @@ -32308,8 +36227,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (PORT d[0] (1992:1992:1992) (1801:1801:1801)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (1424:1424:1424) (1283:1283:1283)) ) ) ) @@ -32318,7 +36237,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -32328,7 +36247,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1078:1078:1078) (1094:1094:1094)) + (PORT clk (1073:1073:1073) (1089:1089:1089)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -32342,7 +36261,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) + (PORT clk (613:613:613) (621:621:621)) ) ) ) @@ -32351,7 +36270,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) + (PORT clk (614:614:614) (622:622:622)) ) ) ) @@ -32360,7 +36279,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) + (PORT clk (614:614:614) (622:622:622)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -32370,38 +36289,38 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) + (PORT clk (614:614:614) (622:622:622)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~88) + (INSTANCE D\[6\]\~101) (DELAY (ABSOLUTE - (PORT dataa (698:698:698) (786:786:786)) - (PORT datab (637:637:637) (730:730:730)) - (PORT datac (884:884:884) (1011:1011:1011)) - (PORT datad (93:93:93) (113:113:113)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (734:734:734) (849:849:849)) + (PORT datab (687:687:687) (790:790:790)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (584:584:584) (662:662:662)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~89) + (INSTANCE D\[6\]\~102) (DELAY (ABSOLUTE - (PORT dataa (790:790:790) (926:926:926)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datac (326:326:326) (394:394:394)) - (PORT datad (91:91:91) (109:109:109)) + (PORT dataa (668:668:668) (765:765:765)) + (PORT datab (171:171:171) (224:224:224)) + (PORT datac (94:94:94) (118:118:118)) + (PORT datad (90:90:90) (107:107:107)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datab combout (188:188:188) (177:177:177)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -32409,16 +36328,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~111) + (INSTANCE D\[6\]\~127) (DELAY (ABSOLUTE - (PORT dataa (349:349:349) (409:409:409)) - (PORT datab (1129:1129:1129) (1312:1312:1312)) - (PORT datac (494:494:494) (589:589:589)) + (PORT dataa (761:761:761) (889:889:889)) + (PORT datab (1311:1311:1311) (1546:1546:1546)) + (PORT datac (91:91:91) (114:114:114)) (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH dataa combout (181:181:181) (175:175:175)) (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -32434,13 +36353,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~86) + (INSTANCE D\[6\]\~99) (DELAY (ABSOLUTE - (PORT dataa (496:496:496) (588:588:588)) - (PORT datac (913:913:913) (1067:1067:1067)) - (PORT datad (1114:1114:1114) (1287:1287:1287)) - (IOPATH dataa combout (165:165:165) (163:163:163)) + (PORT datab (671:671:671) (798:798:798)) + (PORT datac (1429:1429:1429) (1677:1677:1677)) + (PORT datad (847:847:847) (982:982:982)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~114) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (1010:1010:1010)) + (PORT datab (227:227:227) (273:273:273)) + (PORT datac (308:308:308) (351:351:351)) + (PORT datad (104:104:104) (122:122:122)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -32448,77 +36383,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~100) + (INSTANCE D\[6\]\~115) (DELAY (ABSOLUTE - (PORT dataa (509:509:509) (602:602:602)) - (PORT datab (728:728:728) (836:836:836)) - (PORT datac (95:95:95) (119:119:119)) - (PORT datad (95:95:95) (114:114:114)) + (PORT dataa (1257:1257:1257) (1443:1443:1443)) + (PORT datab (228:228:228) (273:273:273)) + (PORT datac (680:680:680) (804:804:804)) + (PORT datad (102:102:102) (119:119:119)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (504:504:504) (596:596:596)) - (PORT datab (479:479:479) (578:578:578)) - (PORT datac (902:902:902) (1028:1028:1028)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) (DELAY (ABSOLUTE - (PORT dataa (149:149:149) (194:194:194)) - (PORT datab (772:772:772) (880:880:880)) - (PORT datac (525:525:525) (620:620:620)) - (PORT datad (443:443:443) (498:498:498)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) - (DELAY - (ABSOLUTE - (PORT dataa (940:940:940) (1115:1115:1115)) - (PORT datab (426:426:426) (518:518:518)) - (PORT datac (519:519:519) (605:605:605)) - (PORT datad (686:686:686) (789:789:789)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) - (DELAY - (ABSOLUTE - (PORT dataa (541:541:541) (643:643:643)) - (PORT datab (549:549:549) (639:639:639)) - (PORT datac (520:520:520) (608:608:608)) - (PORT datad (94:94:94) (114:114:114)) + (PORT dataa (1016:1016:1016) (1165:1165:1165)) + (PORT datab (226:226:226) (266:266:266)) + (PORT datac (178:178:178) (216:216:216)) + (PORT datad (621:621:621) (711:711:711)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -32547,38 +36434,12 @@ (INSTANCE z80_\|bus_control_\|db\[6\]\~9) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (635:635:635) (752:752:752)) - (PORT datac (121:121:121) (151:151:151)) - (PORT datad (112:112:112) (133:133:133)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|ir_\|opcode\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (102:102:102) (119:119:119)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (754:754:754)) - (PORT datab (501:501:501) (593:593:593)) - (PORT datac (369:369:369) (435:435:435)) - (PORT datad (198:198:198) (225:225:225)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (133:133:133) (168:168:168)) + (PORT datac (303:303:303) (360:360:360)) + (PORT datad (115:115:115) (139:139:139)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -32589,1717 +36450,10 @@ (INSTANCE z80_\|ir_\|opcode\[6\]) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (356:356:356) (392:392:392)) (PORT clrn (917:917:917) (902:902:902)) - (PORT ena (645:645:645) (697:697:697)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~0) - (DELAY - (ABSOLUTE - (PORT datac (941:941:941) (1085:1085:1085)) - (PORT datad (683:683:683) (800:800:800)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~1) - (DELAY - (ABSOLUTE - (PORT dataa (835:835:835) (970:970:970)) - (PORT datab (1296:1296:1296) (1497:1497:1497)) - (PORT datac (1238:1238:1238) (1445:1445:1445)) - (PORT datad (817:817:817) (953:953:953)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~2) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (297:297:297)) - (PORT datab (895:895:895) (1020:1020:1020)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (609:609:609) (701:701:701)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) - (DELAY - (ABSOLUTE - (PORT dataa (1100:1100:1100) (1268:1268:1268)) - (PORT datab (611:611:611) (701:701:701)) - (PORT datac (1150:1150:1150) (1342:1342:1342)) - (PORT datad (93:93:93) (112:112:112)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (757:757:757)) - (PORT datab (159:159:159) (204:204:204)) - (PORT datac (143:143:143) (184:184:184)) - (PORT datad (130:130:130) (160:160:160)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (714:714:714)) - (PORT datab (655:655:655) (757:757:757)) - (PORT datac (221:221:221) (280:280:280)) - (PORT datad (369:369:369) (437:437:437)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (522:522:522) (599:599:599)) - (PORT datac (916:916:916) (1066:1066:1066)) - (PORT datad (490:490:490) (565:565:565)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT datab (104:104:104) (132:132:132)) - (PORT datac (489:489:489) (561:561:561)) - (PORT datad (132:132:132) (161:161:161)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (222:222:222)) - (PORT datab (336:336:336) (392:392:392)) - (PORT datac (630:630:630) (736:736:736)) - (PORT datad (322:322:322) (376:376:376)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (547:547:547) (647:647:647)) - (PORT datac (309:309:309) (360:360:360)) - (PORT datad (120:120:120) (150:150:150)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (711:711:711) (839:839:839)) - (PORT datab (504:504:504) (587:587:587)) - (PORT datac (1033:1033:1033) (1182:1182:1182)) - (PORT datad (520:520:520) (607:607:607)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (406:406:406)) - (PORT datab (139:139:139) (179:179:179)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (520:520:520) (605:605:605)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (283:283:283)) - (PORT datab (747:747:747) (871:871:871)) - (PORT datac (632:632:632) (721:721:721)) - (PORT datad (674:674:674) (776:776:776)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) - (DELAY - (ABSOLUTE - (PORT dataa (290:290:290) (338:338:338)) - (PORT datab (337:337:337) (396:396:396)) - (PORT datac (353:353:353) (422:422:422)) - (PORT datad (366:366:366) (429:429:429)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_yf) - (DELAY - (ABSOLUTE - (PORT clk (900:900:900) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (338:338:338) (409:409:409)) - (PORT datab (502:502:502) (579:579:579)) - (PORT datac (352:352:352) (420:420:420)) - (PORT datad (473:473:473) (542:542:542)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (533:533:533) (611:611:611)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (522:522:522) (600:600:600)) - (PORT datad (482:482:482) (540:540:540)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (429:429:429)) - (PORT datab (658:658:658) (756:756:756)) - (PORT datac (594:594:594) (684:684:684)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~107) - (DELAY - (ABSOLUTE - (PORT dataa (980:980:980) (1140:1140:1140)) - (PORT datab (673:673:673) (794:794:794)) - (PORT datac (879:879:879) (1043:1043:1043)) - (PORT datad (607:607:607) (694:694:694)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (659:659:659) (755:755:755)) - (PORT clk (1087:1087:1087) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2092:2092:2092) (2427:2427:2427)) - (PORT d[1] (1003:1003:1003) (1187:1187:1187)) - (PORT d[2] (1762:1762:1762) (2022:2022:2022)) - (PORT d[3] (1066:1066:1066) (1248:1248:1248)) - (PORT d[4] (1270:1270:1270) (1482:1482:1482)) - (PORT d[5] (1549:1549:1549) (1816:1816:1816)) - (PORT d[6] (1190:1190:1190) (1376:1376:1376)) - (PORT d[7] (1606:1606:1606) (1818:1818:1818)) - (PORT d[8] (1757:1757:1757) (2045:2045:2045)) - (PORT d[9] (1602:1602:1602) (1842:1842:1842)) - (PORT d[10] (2054:2054:2054) (2366:2366:2366)) - (PORT d[11] (1012:1012:1012) (1176:1176:1176)) - (PORT d[12] (1207:1207:1207) (1391:1391:1391)) - (PORT clk (1085:1085:1085) (1102:1102:1102)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1093:1093:1093) (1194:1194:1194)) - (PORT clk (1085:1085:1085) (1102:1102:1102)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1104:1104:1104)) - (PORT d[0] (1481:1481:1481) (1623:1623:1623)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1067:1067:1067) (1083:1083:1083)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (607:607:607) (615:615:615)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (616:616:616)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (616:616:616)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (616:616:616)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (643:643:643) (736:736:736)) - (PORT clk (1084:1084:1084) (1102:1102:1102)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2264:2264:2264) (2626:2626:2626)) - (PORT d[1] (976:976:976) (1155:1155:1155)) - (PORT d[2] (1924:1924:1924) (2200:2200:2200)) - (PORT d[3] (1054:1054:1054) (1231:1231:1231)) - (PORT d[4] (1073:1073:1073) (1242:1242:1242)) - (PORT d[5] (954:954:954) (1119:1119:1119)) - (PORT d[6] (1009:1009:1009) (1167:1167:1167)) - (PORT d[7] (1774:1774:1774) (2007:2007:2007)) - (PORT d[8] (1932:1932:1932) (2243:2243:2243)) - (PORT d[9] (1635:1635:1635) (1882:1882:1882)) - (PORT d[10] (2007:2007:2007) (2303:2303:2303)) - (PORT d[11] (861:861:861) (1003:1003:1003)) - (PORT d[12] (1003:1003:1003) (1150:1150:1150)) - (PORT clk (1082:1082:1082) (1100:1100:1100)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1068:1068:1068) (1159:1159:1159)) - (PORT clk (1082:1082:1082) (1100:1100:1100)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1084:1084:1084) (1102:1102:1102)) - (PORT d[0] (1327:1327:1327) (1422:1422:1422)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1064:1064:1064) (1081:1081:1081)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (604:604:604) (613:613:613)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (605:605:605) (614:614:614)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (605:605:605) (614:614:614)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (605:605:605) (614:614:614)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (673:673:673) (772:772:772)) - (PORT clk (1084:1084:1084) (1102:1102:1102)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2093:2093:2093) (2428:2428:2428)) - (PORT d[1] (983:983:983) (1158:1158:1158)) - (PORT d[2] (1742:1742:1742) (1993:1993:1993)) - (PORT d[3] (1189:1189:1189) (1381:1381:1381)) - (PORT d[4] (1286:1286:1286) (1504:1504:1504)) - (PORT d[5] (1557:1557:1557) (1827:1827:1827)) - (PORT d[6] (1042:1042:1042) (1211:1211:1211)) - (PORT d[7] (1613:1613:1613) (1825:1825:1825)) - (PORT d[8] (1938:1938:1938) (2254:2254:2254)) - (PORT d[9] (1639:1639:1639) (1892:1892:1892)) - (PORT d[10] (2034:2034:2034) (2338:2338:2338)) - (PORT d[11] (1022:1022:1022) (1190:1190:1190)) - (PORT d[12] (1170:1170:1170) (1342:1342:1342)) - (PORT clk (1082:1082:1082) (1100:1100:1100)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1059:1059:1059) (1151:1151:1151)) - (PORT clk (1082:1082:1082) (1100:1100:1100)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1084:1084:1084) (1102:1102:1102)) - (PORT d[0] (1375:1375:1375) (1493:1493:1493)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1064:1064:1064) (1081:1081:1081)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (604:604:604) (613:613:613)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (605:605:605) (614:614:614)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (605:605:605) (614:614:614)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (605:605:605) (614:614:614)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (782:782:782) (913:913:913)) - (PORT datab (781:781:781) (913:913:913)) - (PORT datac (638:638:638) (717:717:717)) - (PORT datad (631:631:631) (709:709:709)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (707:707:707) (817:817:817)) - (PORT clk (1091:1091:1091) (1109:1109:1109)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1636:1636:1636) (1864:1864:1864)) - (PORT d[1] (1552:1552:1552) (1823:1823:1823)) - (PORT d[2] (682:682:682) (782:782:782)) - (PORT d[3] (962:962:962) (1117:1117:1117)) - (PORT d[4] (1687:1687:1687) (1968:1968:1968)) - (PORT d[5] (1407:1407:1407) (1658:1658:1658)) - (PORT d[6] (722:722:722) (827:827:827)) - (PORT d[7] (750:750:750) (869:869:869)) - (PORT d[8] (995:995:995) (1153:1153:1153)) - (PORT d[9] (708:708:708) (820:820:820)) - (PORT d[10] (1411:1411:1411) (1604:1604:1604)) - (PORT d[11] (1846:1846:1846) (2146:2146:2146)) - (PORT d[12] (1264:1264:1264) (1454:1454:1454)) - (PORT clk (1089:1089:1089) (1107:1107:1107)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (854:854:854) (919:919:919)) - (PORT clk (1089:1089:1089) (1107:1107:1107)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (PORT d[0] (1185:1185:1185) (1273:1273:1273)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1071:1071:1071) (1088:1088:1088)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (729:729:729)) - (PORT datab (935:935:935) (1086:1086:1086)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (785:785:785) (911:911:911)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (898:898:898) (1053:1053:1053)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1785:1785:1785) (2045:2045:2045)) - (PORT d[1] (1164:1164:1164) (1373:1373:1373)) - (PORT d[2] (1221:1221:1221) (1417:1417:1417)) - (PORT d[3] (1049:1049:1049) (1230:1230:1230)) - (PORT d[4] (1442:1442:1442) (1668:1668:1668)) - (PORT d[5] (1305:1305:1305) (1532:1532:1532)) - (PORT d[6] (976:976:976) (1119:1119:1119)) - (PORT d[7] (940:940:940) (1092:1092:1092)) - (PORT d[8] (1488:1488:1488) (1732:1732:1732)) - (PORT d[9] (1134:1134:1134) (1301:1301:1301)) - (PORT d[10] (1133:1133:1133) (1307:1307:1307)) - (PORT d[11] (1381:1381:1381) (1598:1598:1598)) - (PORT d[12] (1446:1446:1446) (1655:1655:1655)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1438:1438:1438) (1584:1584:1584)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (PORT d[0] (2262:2262:2262) (2502:2502:2502)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1046:1046:1046) (1065:1065:1065)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (946:946:946) (1050:1050:1050)) - (PORT clk (1051:1051:1051) (1068:1068:1068)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2446:2446:2446) (2778:2778:2778)) - (PORT d[1] (2362:2362:2362) (2678:2678:2678)) - (PORT d[2] (2423:2423:2423) (2755:2755:2755)) - (PORT d[3] (2615:2615:2615) (2968:2968:2968)) - (PORT d[4] (2392:2392:2392) (2714:2714:2714)) - (PORT d[5] (2550:2550:2550) (2906:2906:2906)) - (PORT d[6] (2637:2637:2637) (3014:3014:3014)) - (PORT d[7] (2422:2422:2422) (2758:2758:2758)) - (PORT d[8] (2414:2414:2414) (2749:2749:2749)) - (PORT d[9] (2559:2559:2559) (2937:2937:2937)) - (PORT d[10] (2575:2575:2575) (2895:2895:2895)) - (PORT d[11] (2424:2424:2424) (2742:2742:2742)) - (PORT d[12] (2554:2554:2554) (2908:2908:2908)) - (PORT clk (1048:1048:1048) (1067:1067:1067)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1051:1051:1051) (1068:1068:1068)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1069:1069:1069)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1069:1069:1069)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1069:1069:1069)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1069:1069:1069)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1599:1599:1599) (1833:1833:1833)) - (PORT d[1] (989:989:989) (1178:1178:1178)) - (PORT d[2] (1107:1107:1107) (1292:1292:1292)) - (PORT d[3] (1072:1072:1072) (1258:1258:1258)) - (PORT d[4] (1602:1602:1602) (1841:1841:1841)) - (PORT d[5] (1316:1316:1316) (1540:1540:1540)) - (PORT d[6] (1129:1129:1129) (1293:1293:1293)) - (PORT d[7] (1227:1227:1227) (1432:1432:1432)) - (PORT d[8] (1367:1367:1367) (1595:1595:1595)) - (PORT d[9] (1129:1129:1129) (1298:1298:1298)) - (PORT d[10] (959:959:959) (1096:1096:1096)) - (PORT d[11] (1135:1135:1135) (1299:1299:1299)) - (PORT d[12] (1423:1423:1423) (1625:1625:1625)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (PORT d[0] (1578:1578:1578) (1775:1775:1775)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1078:1078:1078) (1094:1094:1094)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2216:2216:2216) (2563:2563:2563)) - (PORT d[1] (1659:1659:1659) (1935:1935:1935)) - (PORT d[2] (1569:1569:1569) (1794:1794:1794)) - (PORT d[3] (1294:1294:1294) (1526:1526:1526)) - (PORT d[4] (1452:1452:1452) (1691:1691:1691)) - (PORT d[5] (1461:1461:1461) (1699:1699:1699)) - (PORT d[6] (1104:1104:1104) (1269:1269:1269)) - (PORT d[7] (1321:1321:1321) (1494:1494:1494)) - (PORT d[8] (1792:1792:1792) (2113:2113:2113)) - (PORT d[9] (1529:1529:1529) (1780:1780:1780)) - (PORT d[10] (2637:2637:2637) (3017:3017:3017)) - (PORT d[11] (1109:1109:1109) (1296:1296:1296)) - (PORT d[12] (1409:1409:1409) (1611:1611:1611)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (PORT d[0] (2281:2281:2281) (2058:2058:2058)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1077:1077:1077) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (839:839:839) (963:963:963)) - (PORT clk (1104:1104:1104) (1120:1120:1120)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1582:1582:1582) (1791:1791:1791)) - (PORT d[1] (1211:1211:1211) (1427:1427:1427)) - (PORT d[2] (1254:1254:1254) (1474:1474:1474)) - (PORT d[3] (1306:1306:1306) (1512:1512:1512)) - (PORT d[4] (1722:1722:1722) (2020:2020:2020)) - (PORT d[5] (1375:1375:1375) (1614:1614:1614)) - (PORT d[6] (917:917:917) (1047:1047:1047)) - (PORT d[7] (907:907:907) (1040:1040:1040)) - (PORT d[8] (1585:1585:1585) (1863:1863:1863)) - (PORT d[9] (1205:1205:1205) (1379:1379:1379)) - (PORT d[10] (1085:1085:1085) (1238:1238:1238)) - (PORT d[11] (1643:1643:1643) (1882:1882:1882)) - (PORT d[12] (905:905:905) (1047:1047:1047)) - (PORT clk (1102:1102:1102) (1118:1118:1118)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1389:1389:1389) (1525:1525:1525)) - (PORT clk (1102:1102:1102) (1118:1118:1118)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1104:1104:1104) (1120:1120:1120)) - (PORT d[0] (1751:1751:1751) (1627:1627:1627)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1105:1105:1105) (1121:1121:1121)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1105:1105:1105) (1121:1121:1121)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1105:1105:1105) (1121:1121:1121)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1105:1105:1105) (1121:1121:1121)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1059:1059:1059) (1077:1077:1077)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1400:1400:1400) (1590:1590:1590)) - (PORT clk (1064:1064:1064) (1080:1080:1080)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2480:2480:2480) (2801:2801:2801)) - (PORT d[1] (2279:2279:2279) (2566:2566:2566)) - (PORT d[2] (2448:2448:2448) (2750:2750:2750)) - (PORT d[3] (2483:2483:2483) (2821:2821:2821)) - (PORT d[4] (2520:2520:2520) (2837:2837:2837)) - (PORT d[5] (2430:2430:2430) (2762:2762:2762)) - (PORT d[6] (2545:2545:2545) (2901:2901:2901)) - (PORT d[7] (2265:2265:2265) (2556:2556:2556)) - (PORT d[8] (2566:2566:2566) (2898:2898:2898)) - (PORT d[9] (2550:2550:2550) (2915:2915:2915)) - (PORT d[10] (2580:2580:2580) (2904:2904:2904)) - (PORT d[11] (2430:2430:2430) (2736:2736:2736)) - (PORT d[12] (2483:2483:2483) (2802:2802:2802)) - (PORT clk (1061:1061:1061) (1079:1079:1079)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1064:1064:1064) (1080:1080:1080)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1065:1065:1065) (1081:1081:1081)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1065:1065:1065) (1081:1081:1081)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1065:1065:1065) (1081:1081:1081)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1065:1065:1065) (1081:1081:1081)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1060:1060:1060) (1078:1078:1078)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (802:802:802) (931:931:931)) - (PORT datab (528:528:528) (629:629:629)) - (PORT datac (650:650:650) (748:748:748)) - (PORT datad (918:918:918) (1051:1051:1051)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (1000:1000:1000)) - (PORT datab (528:528:528) (629:629:629)) - (PORT datac (963:963:963) (1090:1090:1090)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (666:666:666) (787:787:787)) - (PORT datac (899:899:899) (1036:1036:1036)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (745:745:745) (854:854:854)) - (PORT datab (747:747:747) (855:855:855)) - (PORT datac (467:467:467) (550:550:550)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~99) - (DELAY - (ABSOLUTE - (PORT dataa (442:442:442) (512:512:512)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) - (DELAY - (ABSOLUTE - (PORT dataa (542:542:542) (645:645:645)) - (PORT datab (566:566:566) (642:642:642)) - (PORT datac (132:132:132) (169:169:169)) - (PORT datad (527:527:527) (607:607:607)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (432:432:432) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (374:374:374) (442:442:442)) - (PORT datac (127:127:127) (168:168:168)) - (PORT datad (186:186:186) (216:216:216)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (539:539:539) (623:623:623)) - (PORT datab (519:519:519) (599:599:599)) - (PORT datac (435:435:435) (493:493:493)) - (PORT datad (491:491:491) (558:558:558)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) - (PORT asdata (317:317:317) (356:356:356)) - (PORT clrn (911:911:911) (895:895:895)) - (PORT ena (780:780:780) (849:849:849)) + (PORT ena (1045:1045:1045) (1140:1140:1140)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -34311,203 +36465,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) + (INSTANCE z80_\|pla_decode_\|Equal13\~0) (DELAY (ABSOLUTE - (PORT dataa (681:681:681) (814:814:814)) - (PORT datab (474:474:474) (551:551:551)) - (PORT datac (470:470:470) (534:534:534)) - (PORT datad (1077:1077:1077) (1218:1218:1218)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_inst4) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|use_ixiy) - (DELAY - (ABSOLUTE - (PORT dataa (555:555:555) (659:659:659)) - (PORT datac (528:528:528) (621:621:621)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (752:752:752)) - (PORT datab (554:554:554) (663:663:663)) - (PORT datac (372:372:372) (440:440:440)) - (PORT datad (715:715:715) (832:832:832)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (479:479:479) (563:563:563)) - (PORT datab (353:353:353) (408:408:408)) - (PORT datac (506:506:506) (589:589:589)) - (PORT datad (187:187:187) (217:217:217)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~31) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (745:745:745)) - (PORT datab (877:877:877) (1003:1003:1003)) - (PORT datac (330:330:330) (389:389:389)) - (PORT datad (608:608:608) (690:690:690)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (828:828:828)) - (PORT datab (254:254:254) (310:310:310)) - (PORT datac (945:945:945) (1090:1090:1090)) - (PORT datad (144:144:144) (179:179:179)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (258:258:258)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (602:602:602) (684:684:684)) - (PORT datad (107:107:107) (126:126:126)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (747:747:747)) - (PORT datab (301:301:301) (357:357:357)) - (PORT datac (600:600:600) (688:688:688)) - (PORT datad (164:164:164) (193:193:193)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (542:542:542)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (311:311:311) (362:362:362)) - (PORT datad (92:92:92) (111:111:111)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (121:121:121) (153:153:153)) - (PORT datab (342:342:342) (402:402:402)) - (PORT datac (101:101:101) (130:130:130)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (479:479:479) (563:563:563)) - (PORT datab (611:611:611) (699:699:699)) - (PORT datac (785:785:785) (905:905:905)) - (PORT datad (506:506:506) (590:590:590)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (473:473:473) (549:549:549)) - (PORT datab (512:512:512) (603:603:603)) - (PORT datac (547:547:547) (631:631:631)) - (PORT datad (615:615:615) (700:700:700)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (405:405:405) (501:501:501)) + (PORT datac (1064:1064:1064) (1243:1243:1243)) + (PORT datad (944:944:944) (1091:1091:1091)) + (IOPATH dataa combout (165:165:165) (163:163:163)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -34515,14 +36479,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~9) + (INSTANCE z80_\|pla_decode_\|Equal38\~2) (DELAY (ABSOLUTE - (PORT dataa (480:480:480) (564:564:564)) - (PORT datab (472:472:472) (554:554:554)) - (PORT datac (616:616:616) (700:700:700)) - (PORT datad (169:169:169) (200:200:200)) - (IOPATH dataa combout (158:158:158) (163:163:163)) + (PORT dataa (984:984:984) (1146:1146:1146)) + (PORT datab (955:955:955) (1140:1140:1140)) + (PORT datac (589:589:589) (696:696:696)) + (PORT datad (1016:1016:1016) (1186:1186:1186)) + (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -34531,93 +36495,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~11) + (INSTANCE z80_\|interrupts_\|iff1\~0) (DELAY (ABSOLUTE - (PORT dataa (882:882:882) (1032:1032:1032)) - (PORT datab (107:107:107) (136:136:136)) - (PORT datac (1068:1068:1068) (1218:1218:1218)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (793:793:793)) - (PORT datab (553:553:553) (655:655:655)) - (PORT datac (934:934:934) (1076:1076:1076)) - (PORT datad (653:653:653) (755:755:755)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (780:780:780) (888:888:888)) - (PORT datab (611:611:611) (699:699:699)) - (PORT datac (570:570:570) (646:646:646)) - (PORT datad (171:171:171) (202:202:202)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (322:322:322) (366:366:366)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (325:325:325) (374:374:374)) - (PORT datab (578:578:578) (680:680:680)) - (PORT datac (294:294:294) (344:344:344)) - (PORT datad (337:337:337) (390:390:390)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~48) - (DELAY - (ABSOLUTE - (PORT dataa (489:489:489) (583:583:583)) - (PORT datab (644:644:644) (749:749:749)) - (PORT datac (834:834:834) (982:982:982)) - (PORT datad (370:370:370) (429:429:429)) + (PORT dataa (311:311:311) (363:363:363)) + (PORT datab (142:142:142) (190:190:190)) + (PORT datac (326:326:326) (392:392:392)) + (PORT datad (625:625:625) (722:722:722)) (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -34627,14 +36511,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~22) + (INSTANCE z80_\|interrupts_\|iff1\~1) (DELAY (ABSOLUTE - (PORT dataa (743:743:743) (842:842:842)) - (PORT datab (463:463:463) (538:538:538)) - (PORT datac (592:592:592) (674:674:674)) - (PORT datad (103:103:103) (119:119:119)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (917:917:917) (1068:1068:1068)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (192:192:192) (245:245:245)) + (PORT datad (104:104:104) (122:122:122)) + (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -34643,30 +36527,234 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~21) + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT dataa (507:507:507) (600:600:600)) - (PORT datab (525:525:525) (628:628:628)) - (PORT datac (856:856:856) (976:976:976)) - (PORT datad (675:675:675) (763:763:763)) + (PORT datab (426:426:426) (512:512:512)) + (PORT datad (176:176:176) (234:234:234)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|iff1) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (632:632:632) (690:690:690)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) + (DELAY + (ABSOLUTE + (PORT dataa (460:460:460) (529:529:529)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (630:630:630) (727:727:727)) + (PORT datad (872:872:872) (1017:1017:1017)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|int_armed) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (915:915:915)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (898:898:898) (902:902:902)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|DFFE_inst44) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (1053:1053:1053) (1195:1195:1195)) + (PORT clrn (925:925:925) (906:906:906)) + (PORT ena (508:508:508) (552:552:552)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|in_halt\~0) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (262:262:262)) + (PORT datab (160:160:160) (213:213:213)) + (PORT datad (138:138:138) (178:178:178)) (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal77\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1298:1298:1298) (1516:1516:1516)) + (PORT datab (676:676:676) (786:786:786)) + (PORT datac (637:637:637) (738:738:738)) + (PORT datad (668:668:668) (759:759:759)) + (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|in_halt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (138:138:138)) + (PORT datab (373:373:373) (438:438:438)) + (PORT datad (480:480:480) (559:559:559)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|in_halt) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (925:925:925) (906:906:906)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (980:980:980)) + (PORT datab (332:332:332) (383:383:383)) + (PORT datac (687:687:687) (790:790:790)) + (PORT datad (328:328:328) (383:383:383)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~35) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (153:153:153)) + (PORT datab (113:113:113) (141:141:141)) + (PORT datac (311:311:311) (360:360:360)) + (PORT datad (105:105:105) (122:122:122)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|fMRead\~23) (DELAY (ABSOLUTE - (PORT dataa (469:469:469) (543:543:543)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (427:427:427) (493:493:493)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (498:498:498) (581:581:581)) + (PORT datab (347:347:347) (402:402:402)) + (PORT datac (450:450:450) (520:520:520)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (573:573:573)) + (PORT datab (851:851:851) (990:990:990)) + (PORT datac (309:309:309) (374:374:374)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (434:434:434)) + (PORT datab (460:460:460) (535:535:535)) + (PORT datac (480:480:480) (555:555:555)) + (PORT datad (578:578:578) (669:669:669)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (729:729:729)) + (PORT datab (674:674:674) (784:784:784)) + (PORT datac (732:732:732) (858:858:858)) + (PORT datad (1097:1097:1097) (1257:1257:1257)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -34675,13 +36763,93 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~26) + (INSTANCE z80_\|execute_\|fMRead\~30) (DELAY (ABSOLUTE - (PORT dataa (1167:1167:1167) (1359:1359:1359)) - (PORT datab (657:657:657) (756:756:756)) - (PORT datac (636:636:636) (734:734:734)) - (PORT datad (649:649:649) (747:747:747)) + (PORT dataa (498:498:498) (601:601:601)) + (PORT datab (1041:1041:1041) (1194:1194:1194)) + (PORT datac (653:653:653) (750:750:750)) + (PORT datad (460:460:460) (526:526:526)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~31) + (DELAY + (ABSOLUTE + (PORT dataa (239:239:239) (286:286:286)) + (PORT datab (591:591:591) (692:692:692)) + (PORT datac (748:748:748) (860:860:860)) + (PORT datad (595:595:595) (703:703:703)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (93:93:93) (113:113:113)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~37) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (408:408:408)) + (PORT datab (818:818:818) (946:946:946)) + (PORT datac (815:815:815) (964:964:964)) + (PORT datad (908:908:908) (1052:1052:1052)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (398:398:398)) + (PORT datab (116:116:116) (150:150:150)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1670:1670:1670) (1917:1917:1917)) + (PORT datab (353:353:353) (423:423:423)) + (PORT datac (331:331:331) (381:381:381)) + (PORT datad (115:115:115) (132:132:132)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -34694,42 +36862,26 @@ (INSTANCE z80_\|execute_\|fMRead\~25) (DELAY (ABSOLUTE - (PORT dataa (1406:1406:1406) (1620:1620:1620)) - (PORT datab (297:297:297) (343:343:343)) - (PORT datac (101:101:101) (121:121:121)) - (PORT datad (557:557:557) (639:639:639)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (899:899:899) (1026:1026:1026)) - (PORT datab (477:477:477) (571:571:571)) - (PORT datac (582:582:582) (688:688:688)) - (PORT datad (438:438:438) (519:519:519)) + (PORT dataa (228:228:228) (276:276:276)) + (PORT datab (489:489:489) (569:569:569)) + (PORT datac (617:617:617) (709:709:709)) + (PORT datad (91:91:91) (108:108:108)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~33) + (INSTANCE z80_\|execute_\|fMRead\~16) (DELAY (ABSOLUTE - (PORT dataa (555:555:555) (640:640:640)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (470:470:470) (561:561:561)) - (PORT datad (90:90:90) (107:107:107)) + (PORT dataa (324:324:324) (381:381:381)) + (PORT datab (349:349:349) (417:417:417)) + (PORT datac (100:100:100) (127:127:127)) + (PORT datad (615:615:615) (709:709:709)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -34739,13 +36891,141 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~35) + (INSTANCE z80_\|execute_\|fMRead\~11) (DELAY (ABSOLUTE - (PORT dataa (463:463:463) (536:536:536)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (463:463:463) (549:549:549)) - (PORT datad (102:102:102) (119:119:119)) + (PORT dataa (647:647:647) (747:747:747)) + (PORT datab (489:489:489) (566:566:566)) + (PORT datac (99:99:99) (127:127:127)) + (PORT datad (636:636:636) (731:731:731)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (481:481:481) (557:557:557)) + (PORT datab (896:896:896) (1019:1019:1019)) + (PORT datac (633:633:633) (732:732:732)) + (PORT datad (783:783:783) (891:891:891)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (470:470:470) (543:543:543)) + (PORT datac (356:356:356) (421:421:421)) + (PORT datad (647:647:647) (746:746:746)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (473:473:473) (558:558:558)) + (PORT datab (704:704:704) (809:809:809)) + (PORT datac (353:353:353) (418:418:418)) + (PORT datad (766:766:766) (874:874:874)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (801:801:801) (923:923:923)) + (PORT datab (608:608:608) (711:711:711)) + (PORT datac (349:349:349) (416:416:416)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (529:529:529) (613:613:613)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (144:144:144)) + (PORT datab (357:357:357) (420:420:420)) + (PORT datac (334:334:334) (393:393:393)) + (PORT datad (323:323:323) (371:371:371)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (732:732:732)) + (PORT datab (521:521:521) (609:609:609)) + (PORT datac (313:313:313) (370:370:370)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~36) + (DELAY + (ABSOLUTE + (PORT dataa (500:500:500) (593:593:593)) + (PORT datab (355:355:355) (420:420:420)) + (PORT datac (519:519:519) (604:604:604)) + (PORT datad (594:594:594) (679:679:679)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -34758,1800 +37038,9 @@ (INSTANCE z80_\|pin_control_\|bus_db_pin_re) (DELAY (ABSOLUTE - (PORT datab (553:553:553) (643:643:643)) - (PORT datac (523:523:523) (610:610:610)) - (PORT datad (96:96:96) (116:116:116)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (581:581:581) (665:665:665)) - (PORT clk (1098:1098:1098) (1115:1115:1115)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (648:648:648) (731:731:731)) - (PORT d[1] (1411:1411:1411) (1666:1666:1666)) - (PORT d[2] (993:993:993) (1127:1127:1127)) - (PORT d[3] (570:570:570) (662:662:662)) - (PORT d[4] (1533:1533:1533) (1796:1796:1796)) - (PORT d[5] (2036:2036:2036) (2359:2359:2359)) - (PORT d[6] (588:588:588) (683:683:683)) - (PORT d[7] (1881:1881:1881) (2126:2126:2126)) - (PORT d[8] (688:688:688) (792:792:792)) - (PORT d[9] (574:574:574) (672:672:672)) - (PORT d[10] (753:753:753) (864:864:864)) - (PORT d[11] (1435:1435:1435) (1666:1666:1666)) - (PORT d[12] (744:744:744) (861:861:861)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (508:508:508) (530:530:530)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (PORT d[0] (920:920:920) (961:961:961)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1078:1078:1078) (1094:1094:1094)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (397:397:397) (457:457:457)) - (PORT clk (1097:1097:1097) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (546:546:546) (622:622:622)) - (PORT d[1] (1745:1745:1745) (2043:2043:2043)) - (PORT d[2] (693:693:693) (795:795:795)) - (PORT d[3] (737:737:737) (857:857:857)) - (PORT d[4] (1511:1511:1511) (1768:1768:1768)) - (PORT d[5] (1749:1749:1749) (2050:2050:2050)) - (PORT d[6] (379:379:379) (434:434:434)) - (PORT d[7] (386:386:386) (446:446:446)) - (PORT d[8] (571:571:571) (657:657:657)) - (PORT d[9] (390:390:390) (452:452:452)) - (PORT d[10] (585:585:585) (673:673:673)) - (PORT d[11] (1495:1495:1495) (1741:1741:1741)) - (PORT d[12] (704:704:704) (811:811:811)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (536:536:536) (563:563:563)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (PORT d[0] (1141:1141:1141) (1215:1215:1215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1077:1077:1077) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (439:439:439)) - (PORT datab (358:358:358) (429:429:429)) - (PORT datac (429:429:429) (482:482:482)) - (PORT datad (479:479:479) (551:551:551)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (392:392:392) (449:449:449)) - (PORT clk (1096:1096:1096) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1810:1810:1810) (2056:2056:2056)) - (PORT d[1] (1721:1721:1721) (2012:2012:2012)) - (PORT d[2] (533:533:533) (613:613:613)) - (PORT d[3] (755:755:755) (880:880:880)) - (PORT d[4] (1533:1533:1533) (1796:1796:1796)) - (PORT d[5] (1573:1573:1573) (1841:1841:1841)) - (PORT d[6] (533:533:533) (609:609:609)) - (PORT d[7] (720:720:720) (823:823:823)) - (PORT d[8] (819:819:819) (944:944:944)) - (PORT d[9] (535:535:535) (619:619:619)) - (PORT d[10] (565:565:565) (652:652:652)) - (PORT d[11] (1679:1679:1679) (1958:1958:1958)) - (PORT d[12] (537:537:537) (624:624:624)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (691:691:691) (739:739:739)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1114:1114:1114)) - (PORT d[0] (1110:1110:1110) (1180:1180:1180)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1076:1076:1076) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (408:408:408) (473:473:473)) - (PORT clk (1096:1096:1096) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1820:1820:1820) (2069:2069:2069)) - (PORT d[1] (1574:1574:1574) (1849:1849:1849)) - (PORT d[2] (717:717:717) (831:831:831)) - (PORT d[3] (756:756:756) (884:884:884)) - (PORT d[4] (1541:1541:1541) (1805:1805:1805)) - (PORT d[5] (1574:1574:1574) (1853:1853:1853)) - (PORT d[6] (692:692:692) (791:791:791)) - (PORT d[7] (625:625:625) (715:715:715)) - (PORT d[8] (837:837:837) (967:967:967)) - (PORT d[9] (877:877:877) (1007:1007:1007)) - (PORT d[10] (398:398:398) (459:459:459)) - (PORT d[11] (1680:1680:1680) (1954:1954:1954)) - (PORT d[12] (548:548:548) (636:636:636)) - (PORT clk (1094:1094:1094) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (690:690:690) (738:738:738)) - (PORT clk (1094:1094:1094) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1112:1112:1112)) - (PORT d[0] (1009:1009:1009) (1075:1075:1075)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1076:1076:1076) (1091:1091:1091)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (623:623:623)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (624:624:624)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (624:624:624)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (624:624:624)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (687:687:687) (803:803:803)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (547:547:547) (632:632:632)) - (PORT datad (621:621:621) (701:701:701)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (411:411:411) (475:475:475)) - (PORT clk (1089:1089:1089) (1107:1107:1107)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1643:1643:1643) (1872:1872:1872)) - (PORT d[1] (1390:1390:1390) (1638:1638:1638)) - (PORT d[2] (876:876:876) (1010:1010:1010)) - (PORT d[3] (1125:1125:1125) (1310:1310:1310)) - (PORT d[4] (1706:1706:1706) (2004:2004:2004)) - (PORT d[5] (1570:1570:1570) (1848:1848:1848)) - (PORT d[6] (730:730:730) (836:836:836)) - (PORT d[7] (750:750:750) (866:866:866)) - (PORT d[8] (999:999:999) (1150:1150:1150)) - (PORT d[9] (872:872:872) (1005:1005:1005)) - (PORT d[10] (1264:1264:1264) (1440:1440:1440)) - (PORT d[11] (1844:1844:1844) (2112:2112:2112)) - (PORT d[12] (729:729:729) (841:841:841)) - (PORT clk (1087:1087:1087) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1646:1646:1646) (1803:1803:1803)) - (PORT clk (1087:1087:1087) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1107:1107:1107)) - (PORT d[0] (1744:1744:1744) (1905:1905:1905)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1044:1044:1044) (1064:1064:1064)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1177:1177:1177) (1330:1330:1330)) - (PORT clk (1049:1049:1049) (1067:1067:1067)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2414:2414:2414) (2742:2742:2742)) - (PORT d[1] (2309:2309:2309) (2604:2604:2604)) - (PORT d[2] (2377:2377:2377) (2705:2705:2705)) - (PORT d[3] (2410:2410:2410) (2738:2738:2738)) - (PORT d[4] (2388:2388:2388) (2717:2717:2717)) - (PORT d[5] (2415:2415:2415) (2707:2707:2707)) - (PORT d[6] (2588:2588:2588) (2951:2951:2951)) - (PORT d[7] (2446:2446:2446) (2756:2756:2756)) - (PORT d[8] (2454:2454:2454) (2760:2760:2760)) - (PORT d[9] (2548:2548:2548) (2918:2918:2918)) - (PORT d[10] (2469:2469:2469) (2774:2774:2774)) - (PORT d[11] (2511:2511:2511) (2836:2836:2836)) - (PORT d[12] (2491:2491:2491) (2835:2835:2835)) - (PORT clk (1046:1046:1046) (1066:1066:1066)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1049:1049:1049) (1067:1067:1067)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1050:1050:1050) (1068:1068:1068)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1050:1050:1050) (1068:1068:1068)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1050:1050:1050) (1068:1068:1068)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1050:1050:1050) (1068:1068:1068)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1438:1438:1438) (1631:1631:1631)) - (PORT d[1] (1172:1172:1172) (1379:1379:1379)) - (PORT d[2] (1335:1335:1335) (1563:1563:1563)) - (PORT d[3] (1428:1428:1428) (1670:1670:1670)) - (PORT d[4] (1729:1729:1729) (2027:2027:2027)) - (PORT d[5] (1311:1311:1311) (1534:1534:1534)) - (PORT d[6] (1094:1094:1094) (1246:1246:1246)) - (PORT d[7] (1420:1420:1420) (1623:1623:1623)) - (PORT d[8] (1591:1591:1591) (1868:1868:1868)) - (PORT d[9] (1016:1016:1016) (1161:1161:1161)) - (PORT d[10] (873:873:873) (992:992:992)) - (PORT d[11] (1938:1938:1938) (2221:2221:2221)) - (PORT d[12] (889:889:889) (1021:1021:1021)) - (PORT clk (1105:1105:1105) (1122:1122:1122)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1105:1105:1105) (1122:1122:1122)) - (PORT d[0] (1274:1274:1274) (1426:1426:1426)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1123:1123:1123)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1103:1103:1103)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (627:627:627) (635:635:635)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (628:628:628) (636:636:636)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (628:628:628) (636:636:636)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (628:628:628) (636:636:636)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (847:847:847) (954:954:954)) - (PORT d[1] (1579:1579:1579) (1848:1848:1848)) - (PORT d[2] (553:553:553) (640:640:640)) - (PORT d[3] (947:947:947) (1108:1108:1108)) - (PORT d[4] (1531:1531:1531) (1791:1791:1791)) - (PORT d[5] (1588:1588:1588) (1867:1867:1867)) - (PORT d[6] (553:553:553) (632:632:632)) - (PORT d[7] (541:541:541) (622:622:622)) - (PORT d[8] (817:817:817) (941:941:941)) - (PORT d[9] (884:884:884) (1019:1019:1019)) - (PORT d[10] (1446:1446:1446) (1649:1649:1649)) - (PORT d[11] (1701:1701:1701) (1982:1982:1982)) - (PORT d[12] (715:715:715) (824:824:824)) - (PORT clk (1093:1093:1093) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) - (PORT d[0] (546:546:546) (501:501:501)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1075:1075:1075) (1091:1091:1091)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (623:623:623)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (624:624:624)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (624:624:624)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (624:624:624)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (494:494:494) (554:554:554)) - (PORT clk (1093:1093:1093) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1800:1800:1800) (2048:2048:2048)) - (PORT d[1] (1566:1566:1566) (1841:1841:1841)) - (PORT d[2] (873:873:873) (1009:1009:1009)) - (PORT d[3] (961:961:961) (1116:1116:1116)) - (PORT d[4] (1712:1712:1712) (2007:2007:2007)) - (PORT d[5] (1587:1587:1587) (1867:1867:1867)) - (PORT d[6] (553:553:553) (633:633:633)) - (PORT d[7] (863:863:863) (998:998:998)) - (PORT d[8] (1771:1771:1771) (2072:2072:2072)) - (PORT d[9] (557:557:557) (646:646:646)) - (PORT d[10] (1448:1448:1448) (1654:1654:1654)) - (PORT d[11] (1688:1688:1688) (1963:1963:1963)) - (PORT d[12] (1278:1278:1278) (1473:1473:1473)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1724:1724:1724) (1898:1898:1898)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) - (PORT d[0] (1046:1046:1046) (1015:1015:1015)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1048:1048:1048) (1067:1067:1067)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1342:1342:1342) (1511:1511:1511)) - (PORT clk (1053:1053:1053) (1070:1070:1070)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2545:2545:2545) (2890:2890:2890)) - (PORT d[1] (2355:2355:2355) (2682:2682:2682)) - (PORT d[2] (2365:2365:2365) (2686:2686:2686)) - (PORT d[3] (2422:2422:2422) (2765:2765:2765)) - (PORT d[4] (2372:2372:2372) (2696:2696:2696)) - (PORT d[5] (2509:2509:2509) (2830:2830:2830)) - (PORT d[6] (2634:2634:2634) (3005:3005:3005)) - (PORT d[7] (2483:2483:2483) (2824:2824:2824)) - (PORT d[8] (2457:2457:2457) (2761:2761:2761)) - (PORT d[9] (2566:2566:2566) (2937:2937:2937)) - (PORT d[10] (2510:2510:2510) (2831:2831:2831)) - (PORT d[11] (2433:2433:2433) (2735:2735:2735)) - (PORT d[12] (2433:2433:2433) (2739:2739:2739)) - (PORT clk (1050:1050:1050) (1069:1069:1069)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1053:1053:1053) (1070:1070:1070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1054:1054:1054) (1071:1071:1071)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1054:1054:1054) (1071:1071:1071)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1054:1054:1054) (1071:1071:1071)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1054:1054:1054) (1071:1071:1071)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1049:1049:1049) (1068:1068:1068)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (440:440:440)) - (PORT datab (638:638:638) (739:739:739)) - (PORT datac (453:453:453) (513:513:513)) - (PORT datad (481:481:481) (546:546:546)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (653:653:653) (748:748:748)) - (PORT datab (638:638:638) (740:740:740)) - (PORT datac (870:870:870) (992:992:992)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~103) - (DELAY - (ABSOLUTE - (PORT dataa (978:978:978) (1137:1137:1137)) - (PORT datab (787:787:787) (919:919:919)) - (PORT datac (358:358:358) (424:424:424)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (182:182:182) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_DAT\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (153:153:153) (704:704:704)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE reset\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (477:477:477) (502:502:502)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) - (DELAY - (ABSOLUTE - (PORT dataa (157:157:157) (218:218:218)) - (PORT datab (159:159:159) (214:214:214)) - (PORT datad (131:131:131) (175:175:175)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_CLK\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (153:153:153) (704:704:704)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1960:1960:1960) (2226:2226:2226)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (899:899:899) (904:904:904)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (901:901:901) (907:907:907)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (121:121:121) (161:161:161)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (899:899:899) (904:904:904)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (901:901:901) (907:907:907)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (124:124:124) (164:164:164)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (899:899:899) (904:904:904)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (901:901:901) (907:907:907)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (129:129:129) (166:166:166)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (899:899:899) (904:904:904)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (901:901:901) (907:907:907)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (136:136:136) (188:188:188)) - (PORT datab (135:135:135) (186:186:186)) - (PORT datac (200:200:200) (245:245:245)) - (PORT datad (122:122:122) (161:161:161)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (123:123:123) (162:162:162)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (899:899:899) (904:904:904)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (901:901:901) (907:907:907)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (125:125:125) (164:164:164)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (899:899:899) (904:904:904)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (901:901:901) (907:907:907)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (122:122:122) (161:161:161)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (899:899:899) (904:904:904)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (901:901:901) (907:907:907)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (136:136:136) (186:186:186)) - (PORT datac (122:122:122) (164:164:164)) - (PORT datad (123:123:123) (162:162:162)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (123:123:123) (166:166:166)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (899:899:899) (904:904:904)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (901:901:901) (907:907:907)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) - (DELAY - (ABSOLUTE - (PORT datab (108:108:108) (139:139:139)) - (PORT datad (123:123:123) (162:162:162)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) - (DELAY - (ABSOLUTE - (PORT clk (899:899:899) (904:904:904)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (901:901:901) (907:907:907)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) - (DELAY - (ABSOLUTE - (PORT datab (109:109:109) (140:140:140)) - (PORT datac (119:119:119) (161:161:161)) - (PORT datad (121:121:121) (159:159:159)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge) - (DELAY - (ABSOLUTE - (PORT clk (899:899:899) (904:904:904)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (901:901:901) (907:907:907)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (903:903:903) (908:908:908)) - (PORT ena (1092:1092:1092) (1217:1217:1217)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) - (DELAY - (ABSOLUTE - (PORT dataa (158:158:158) (218:218:218)) - (PORT datab (160:160:160) (214:214:214)) - (PORT datad (128:128:128) (170:170:170)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (903:903:903) (908:908:908)) - (PORT ena (1092:1092:1092) (1217:1217:1217)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) - (DELAY - (ABSOLUTE - (PORT dataa (153:153:153) (213:213:213)) - (PORT datab (152:152:152) (207:207:207)) - (PORT datad (132:132:132) (175:175:175)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (903:903:903) (908:908:908)) - (PORT ena (1092:1092:1092) (1217:1217:1217)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) - (DELAY - (ABSOLUTE - (PORT dataa (214:214:214) (269:269:269)) - (PORT datab (153:153:153) (209:209:209)) - (PORT datad (133:133:133) (177:177:177)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (903:903:903) (908:908:908)) - (PORT ena (1092:1092:1092) (1217:1217:1217)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|always1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (151:151:151) (210:210:210)) - (PORT datab (156:156:156) (210:210:210)) - (PORT datac (2001:2001:2001) (2280:2280:2280)) - (PORT datad (138:138:138) (182:182:182)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT datab (157:157:157) (212:212:212)) - (PORT datac (139:139:139) (189:189:189)) - (PORT datad (135:135:135) (179:179:179)) + (PORT datab (808:808:808) (954:954:954)) + (PORT datac (544:544:544) (614:614:614)) + (PORT datad (268:268:268) (304:304:304)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -36560,433 +37049,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~103) (DELAY (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (143:143:143) (196:196:196)) - (PORT datac (760:760:760) (876:876:876)) - (PORT datad (96:96:96) (115:115:115)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (2292:2292:2292) (2579:2579:2579)) - (PORT clrn (909:909:909) (914:914:914)) - (PORT ena (638:638:638) (688:688:688)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (294:294:294) (333:333:333)) - (PORT clrn (909:909:909) (914:914:914)) - (PORT ena (638:638:638) (688:688:688)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (320:320:320) (365:365:365)) - (PORT clrn (909:909:909) (914:914:914)) - (PORT ena (638:638:638) (688:688:688)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (310:310:310) (352:352:352)) - (PORT clrn (909:909:909) (914:914:914)) - (PORT ena (638:638:638) (688:688:688)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (499:499:499) (556:556:556)) - (PORT clrn (908:908:908) (914:914:914)) - (PORT ena (632:632:632) (688:688:688)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (506:506:506) (568:568:568)) - (PORT clrn (909:909:909) (914:914:914)) - (PORT ena (638:638:638) (688:688:688)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (499:499:499) (563:563:563)) - (PORT clrn (908:908:908) (914:914:914)) - (PORT ena (632:632:632) (688:688:688)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (402:402:402) (464:464:464)) - (PORT clrn (908:908:908) (914:914:914)) - (PORT ena (632:632:632) (688:688:688)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (405:405:405) (477:477:477)) - (PORT clrn (908:908:908) (914:914:914)) - (PORT ena (632:632:632) (688:688:688)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (532:532:532) (640:640:640)) - (PORT datab (370:370:370) (447:447:447)) - (PORT datac (426:426:426) (527:527:527)) - (PORT datad (425:425:425) (531:531:531)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (791:791:791) (953:953:953)) - (PORT datab (514:514:514) (619:619:619)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (422:422:422) (528:528:528)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|extended\~0) - (DELAY - (ABSOLUTE - (PORT datab (592:592:592) (716:716:716)) - (PORT datad (423:423:423) (484:484:484)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (413:413:413)) - (PORT datab (157:157:157) (211:211:211)) - (PORT datad (440:440:440) (513:513:513)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (196:196:196) (193:193:193)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (492:492:492)) - (PORT datab (357:357:357) (432:432:432)) - (PORT datac (340:340:340) (413:413:413)) - (PORT datad (234:234:234) (292:292:292)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (196:196:196) (193:193:193)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) - (DELAY - (ABSOLUTE - (PORT datab (358:358:358) (433:433:433)) - (PORT datac (174:174:174) (210:210:210)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH datab combout (196:196:196) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) - (DELAY - (ABSOLUTE - (PORT dataa (109:109:109) (141:141:141)) - (PORT datab (2011:2011:2011) (2305:2305:2305)) - (PORT datac (760:760:760) (876:876:876)) - (PORT datad (192:192:192) (226:226:226)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (903:903:903) (908:908:908)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|extended) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) - (PORT ena (933:933:933) (1038:1038:1038)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (363:363:363) (447:447:447)) - (PORT datab (359:359:359) (424:424:424)) - (PORT datac (142:142:142) (190:190:190)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (257:257:257) (316:316:316)) - (PORT datac (759:759:759) (914:914:914)) - (PORT datad (448:448:448) (517:517:517)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (652:652:652) (771:771:771)) - (PORT datac (346:346:346) (412:412:412)) - (PORT datad (492:492:492) (585:585:585)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~0) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (246:246:246)) - (PORT datac (322:322:322) (381:381:381)) - (PORT datad (403:403:403) (480:480:480)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|released\~0) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (427:427:427)) - (PORT datab (359:359:359) (423:423:423)) - (PORT datad (730:730:730) (836:836:836)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|released) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (328:328:328)) - (PORT datab (352:352:352) (427:427:427)) - (PORT datac (322:322:322) (387:387:387)) - (PORT datad (141:141:141) (183:183:183)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~2) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datac (221:221:221) (285:285:285)) - (PORT datad (347:347:347) (422:422:422)) + (PORT dataa (258:258:258) (329:329:329)) + (PORT datac (537:537:537) (637:637:637)) + (PORT datad (324:324:324) (396:396:396)) (IOPATH dataa combout (165:165:165) (163:163:163)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -36995,14 +37063,42 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~3) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~20) (DELAY (ABSOLUTE - (PORT dataa (302:302:302) (352:352:352)) - (PORT datab (227:227:227) (289:289:289)) - (PORT datad (91:91:91) (108:108:108)) + (PORT datab (427:427:427) (519:519:519)) + (PORT datac (357:357:357) (422:422:422)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (249:249:249)) + (PORT datab (423:423:423) (515:515:515)) + (PORT datac (370:370:370) (438:438:438)) + (PORT datad (101:101:101) (124:124:124)) (IOPATH dataa combout (165:165:165) (159:159:159)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) + (DELAY + (ABSOLUTE + (PORT dataa (429:429:429) (521:521:521)) + (PORT datab (104:104:104) (132:132:132)) + (PORT datad (326:326:326) (372:372:372)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -37010,12 +37106,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|shifted) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (897:897:897) (902:902:902)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (914:914:914)) + (PORT clrn (883:883:883) (888:888:888)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -37026,28 +37122,169 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~73) (DELAY (ABSOLUTE - (PORT dataa (409:409:409) (504:504:504)) - (PORT datab (538:538:538) (642:642:642)) - (PORT datad (526:526:526) (622:622:622)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (399:399:399) (491:491:491)) + (PORT datac (511:511:511) (618:618:618)) + (PORT datad (493:493:493) (584:584:584)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) + (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) (DELAY (ABSOLUTE - (PORT datab (419:419:419) (519:519:519)) - (PORT datac (410:410:410) (505:505:505)) - (PORT datad (414:414:414) (506:506:506)) + (PORT dataa (430:430:430) (534:534:534)) + (PORT datab (347:347:347) (418:418:418)) + (PORT datac (498:498:498) (598:598:598)) + (PORT datad (145:145:145) (189:189:189)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (154:154:154) (209:209:209)) + (PORT datab (512:512:512) (615:615:615)) + (PORT datac (503:503:503) (595:595:595)) + (PORT datad (418:418:418) (510:510:510)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~129) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (622:622:622)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~1) + (DELAY + (ABSOLUTE + (PORT datab (438:438:438) (533:533:533)) + (PORT datac (366:366:366) (436:436:436)) + (PORT datad (411:411:411) (500:500:500)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~105) + (DELAY + (ABSOLUTE + (PORT dataa (194:194:194) (237:237:237)) + (PORT datab (393:393:393) (468:468:468)) + (PORT datac (487:487:487) (579:579:579)) + (PORT datad (106:106:106) (130:130:130)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (228:228:228)) + (PORT datab (326:326:326) (392:392:392)) + (PORT datac (355:355:355) (420:420:420)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~130) + (DELAY + (ABSOLUTE + (PORT dataa (429:429:429) (522:522:522)) + (PORT datab (218:218:218) (280:280:280)) + (PORT datad (525:525:525) (617:617:617)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (764:764:764)) + (PORT datab (340:340:340) (397:397:397)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (902:902:902)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (883:883:883) (888:888:888)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (720:720:720) (835:835:835)) + (PORT datab (130:130:130) (178:178:178)) + (PORT datac (485:485:485) (553:553:553)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -37057,83 +37294,10 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~39) (DELAY (ABSOLUTE - (PORT dataa (181:181:181) (225:225:225)) - (PORT datab (106:106:106) (135:135:135)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT datab (516:516:516) (623:623:623)) - (PORT datad (412:412:412) (504:504:504)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (492:492:492)) - (PORT datab (157:157:157) (211:211:211)) - (PORT datac (351:351:351) (426:426:426)) + (PORT dataa (559:559:559) (670:670:670)) + (PORT datac (458:458:458) (525:525:525)) + (PORT datad (384:384:384) (468:468:468)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~32) - (DELAY - (ABSOLUTE - (PORT datab (348:348:348) (421:421:421)) - (PORT datac (210:210:210) (264:264:264)) - (PORT datad (342:342:342) (420:420:420)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (196:196:196) (240:240:240)) - (PORT datab (117:117:117) (150:150:150)) - (PORT datac (345:345:345) (419:419:419)) - (PORT datad (229:229:229) (286:286:286)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -37141,12 +37305,56 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~34) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~100) (DELAY (ABSOLUTE - (PORT dataa (119:119:119) (151:151:151)) - (PORT datab (343:343:343) (405:405:405)) - (PORT datad (525:525:525) (621:621:621)) + (PORT datab (412:412:412) (502:502:502)) + (PORT datac (698:698:698) (815:815:815)) + (PORT datad (529:529:529) (626:626:626)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (574:574:574) (687:687:687)) + (PORT datac (421:421:421) (512:512:512)) + (PORT datad (102:102:102) (124:124:124)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (161:161:161) (174:174:174)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~99) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (501:501:501)) + (PORT datac (544:544:544) (636:636:636)) + (PORT datad (354:354:354) (420:420:420)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) + (DELAY + (ABSOLUTE + (PORT dataa (503:503:503) (582:582:582)) + (PORT datab (494:494:494) (566:566:566)) + (PORT datad (92:92:92) (109:109:109)) (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH datab combout (190:190:190) (181:181:181)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -37156,12 +37364,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) + (PORT clk (902:902:902) (907:907:907)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (916:916:916)) + (PORT clrn (889:889:889) (893:893:893)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -37172,43 +37380,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~30) + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~97) (DELAY (ABSOLUTE - (PORT dataa (630:630:630) (743:743:743)) - (PORT datab (129:129:129) (177:177:177)) - (PORT datac (117:117:117) (158:158:158)) - (PORT datad (289:289:289) (337:337:337)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (528:528:528) (633:633:633)) - (PORT datac (493:493:493) (593:593:593)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (789:789:789) (950:950:950)) - (PORT datab (379:379:379) (444:444:444)) - (PORT datac (518:518:518) (616:616:616)) - (PORT datad (100:100:100) (122:122:122)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) + (PORT dataa (189:189:189) (226:226:226)) + (PORT datab (575:575:575) (687:687:687)) + (PORT datac (380:380:380) (455:455:455)) + (PORT datad (101:101:101) (124:124:124)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -37216,13 +37396,58 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~29) + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~98) (DELAY (ABSOLUTE - (PORT datab (536:536:536) (640:640:640)) - (PORT datac (405:405:405) (503:503:503)) - (PORT datad (413:413:413) (506:506:506)) + (PORT dataa (557:557:557) (658:658:658)) + (PORT datab (509:509:509) (586:586:586)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (889:889:889) (893:893:893)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (739:739:739)) + (PORT datab (397:397:397) (469:469:469)) + (PORT datac (116:116:116) (155:155:155)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (165:165:165) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~108) + (DELAY + (ABSOLUTE + (PORT dataa (680:680:680) (792:792:792)) + (PORT datac (541:541:541) (637:637:637)) + (PORT datad (357:357:357) (424:424:424)) + (IOPATH dataa combout (165:165:165) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -37230,12 +37455,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~30) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~109) (DELAY (ABSOLUTE - (PORT dataa (446:446:446) (547:547:547)) - (PORT datab (349:349:349) (412:412:412)) - (PORT datad (259:259:259) (295:295:295)) + (PORT dataa (108:108:108) (141:141:141)) + (PORT datab (120:120:120) (151:151:151)) + (PORT datac (379:379:379) (453:453:453)) + (PORT datad (108:108:108) (129:129:129)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~110) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (143:143:143)) + (PORT datab (508:508:508) (587:587:587)) + (PORT datad (312:312:312) (355:355:355)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -37245,12 +37486,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) + (PORT clk (900:900:900) (904:904:904)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) + (PORT clrn (886:886:886) (891:891:891)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -37261,43 +37502,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~25) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~111) (DELAY (ABSOLUTE - (PORT dataa (787:787:787) (948:948:948)) - (PORT datab (111:111:111) (143:143:143)) - (PORT datac (364:364:364) (422:422:422)) - (PORT datad (426:426:426) (532:532:532)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (559:559:559) (670:670:670)) + (PORT datab (223:223:223) (284:284:284)) + (PORT datac (538:538:538) (638:638:638)) + (PORT datad (316:316:316) (384:384:384)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~26) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~112) (DELAY (ABSOLUTE - (PORT dataa (398:398:398) (490:490:490)) - (PORT datab (187:187:187) (226:226:226)) - (PORT datac (396:396:396) (487:487:487)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (169:169:169) (229:229:229)) + (PORT datab (105:105:105) (135:135:135)) + (PORT datac (370:370:370) (441:441:441)) + (PORT datad (344:344:344) (400:400:400)) + (IOPATH dataa combout (165:165:165) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~27) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~132) (DELAY (ABSOLUTE - (PORT dataa (872:872:872) (1025:1025:1025)) - (PORT datab (521:521:521) (620:620:620)) - (PORT datad (268:268:268) (306:306:306)) - (IOPATH dataa combout (165:165:165) (159:159:159)) + (PORT dataa (475:475:475) (551:551:551)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datad (387:387:387) (472:472:472)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -37305,13 +37548,28 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~133) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) + (PORT dataa (339:339:339) (392:392:392)) + (PORT datab (415:415:415) (495:495:495)) + (PORT datad (98:98:98) (119:119:119)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (904:904:904)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) + (PORT clrn (886:886:886) (891:891:891)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -37322,27 +37580,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~0) + (INSTANCE D\[3\]\~75) (DELAY (ABSOLUTE - (PORT datab (844:844:844) (993:993:993)) - (PORT datac (497:497:497) (594:594:594)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (130:130:130) (180:180:180)) + (PORT datab (489:489:489) (566:566:566)) + (PORT datac (119:119:119) (160:160:160)) + (PORT datad (781:781:781) (884:884:884)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~94) (DELAY (ABSOLUTE - (PORT datab (227:227:227) (288:288:288)) - (PORT datac (605:605:605) (707:707:707)) - (PORT datad (347:347:347) (421:421:421)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (679:679:679) (791:791:791)) + (PORT datab (709:709:709) (835:835:835)) + (PORT datac (380:380:380) (457:457:457)) + (PORT datad (395:395:395) (469:469:469)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (191:191:191) (181:181:181)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -37350,13 +37612,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~16) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~93) (DELAY (ABSOLUTE - (PORT dataa (372:372:372) (451:451:451)) - (PORT datab (217:217:217) (280:280:280)) - (PORT datac (322:322:322) (387:387:387)) - (PORT datad (141:141:141) (183:183:183)) + (PORT dataa (679:679:679) (791:791:791)) + (PORT datac (543:543:543) (640:640:640)) + (PORT datad (359:359:359) (427:427:427)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~95) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (683:683:683)) + (PORT datab (518:518:518) (619:619:619)) + (PORT datac (488:488:488) (561:561:561)) + (PORT datad (390:390:390) (471:471:471)) (IOPATH dataa combout (188:188:188) (179:179:179)) (IOPATH datab combout (188:188:188) (177:177:177)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -37366,28 +37642,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~17) + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) (DELAY (ABSOLUTE - (PORT dataa (254:254:254) (329:329:329)) - (PORT datab (353:353:353) (428:428:428)) - (PORT datac (259:259:259) (297:297:297)) - (PORT datad (349:349:349) (423:423:423)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (302:302:302) (353:353:353)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datad (92:92:92) (110:110:110)) + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datad (325:325:325) (383:383:383)) (IOPATH dataa combout (165:165:165) (159:159:159)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -37397,12 +37657,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (900:900:900) (904:904:904)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (914:914:914)) + (PORT clrn (886:886:886) (891:891:891)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -37413,646 +37673,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~19) + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~91) (DELAY (ABSOLUTE - (PORT dataa (378:378:378) (457:457:457)) - (PORT datab (668:668:668) (791:791:791)) - (PORT datac (229:229:229) (287:287:287)) - (PORT datad (580:580:580) (661:661:661)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (407:407:407) (502:502:502)) - (PORT datab (777:777:777) (933:933:933)) - (PORT datac (489:489:489) (592:592:592)) - (PORT datad (461:461:461) (545:545:545)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (119:119:119) (156:156:156)) - (PORT datab (117:117:117) (145:145:145)) - (PORT datac (403:403:403) (499:499:499)) - (PORT datad (864:864:864) (1017:1017:1017)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (269:269:269) (309:309:309)) - (PORT datad (503:503:503) (596:596:596)) - (IOPATH datab combout (191:191:191) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (434:434:434)) - (PORT datab (636:636:636) (744:744:744)) - (PORT datac (347:347:347) (415:415:415)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (450:450:450)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (103:103:103) (125:125:125)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (254:254:254) (313:313:313)) - (PORT datab (666:666:666) (789:789:789)) - (PORT datac (407:407:407) (504:504:504)) - (PORT datad (448:448:448) (518:518:518)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (413:413:413) (523:523:523)) - (PORT datab (491:491:491) (586:586:586)) - (PORT datac (597:597:597) (701:701:701)) - (PORT datad (385:385:385) (471:471:471)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (226:226:226)) - (PORT datac (383:383:383) (467:467:467)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (425:425:425) (518:518:518)) - (PORT datab (489:489:489) (584:584:584)) - (PORT datac (360:360:360) (437:437:437)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (419:419:419)) - (PORT datab (272:272:272) (339:339:339)) - (PORT datac (209:209:209) (264:264:264)) - (PORT datad (312:312:312) (367:367:367)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) - (DELAY - (ABSOLUTE - (PORT dataa (450:450:450) (562:562:562)) - (PORT datab (516:516:516) (621:621:621)) - (PORT datac (428:428:428) (529:529:529)) - (PORT datad (421:421:421) (528:528:528)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) - (DELAY - (ABSOLUTE - (PORT dataa (445:445:445) (555:555:555)) - (PORT datab (439:439:439) (541:541:541)) - (PORT datad (424:424:424) (530:530:530)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (558:558:558)) - (PORT datab (514:514:514) (619:619:619)) - (PORT datac (424:424:424) (525:525:525)) - (PORT datad (423:423:423) (529:529:529)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~7) - (DELAY - (ABSOLUTE - (PORT dataa (123:123:123) (155:155:155)) - (PORT datab (516:516:516) (622:622:622)) - (PORT datac (159:159:159) (192:192:192)) - (PORT datad (779:779:779) (929:929:929)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~6) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (954:954:954)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (508:508:508) (604:604:604)) - (PORT datad (264:264:264) (302:302:302)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (229:229:229)) - (PORT datab (147:147:147) (198:198:198)) - (PORT datad (328:328:328) (379:379:379)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (780:780:780) (899:899:899)) - (PORT datab (211:211:211) (266:266:266)) - (PORT datac (770:770:770) (877:877:877)) - (PORT datad (305:305:305) (361:361:361)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (422:422:422) (485:485:485)) - (PORT datab (1903:1903:1903) (2161:2161:2161)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (1064:1064:1064)) - (PORT datab (709:709:709) (818:818:818)) - (PORT datac (348:348:348) (407:407:407)) - (PORT datad (638:638:638) (725:725:725)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (997:997:997)) - (PORT datab (709:709:709) (819:819:819)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (721:721:721) (842:842:842)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (541:541:541) (643:643:643)) - (PORT datab (346:346:346) (408:408:408)) - (PORT datac (129:129:129) (165:165:165)) - (PORT datad (944:944:944) (1074:1074:1074)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (432:432:432) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT datab (500:500:500) (577:577:577)) - (PORT datac (517:517:517) (610:610:610)) - (PORT datad (119:119:119) (142:142:142)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (136:136:136) (173:173:173)) - (PORT datab (378:378:378) (461:461:461)) - (PORT datac (88:88:88) (110:110:110)) - (PORT datad (110:110:110) (131:131:131)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|ir_\|opcode\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (103:103:103) (120:120:120)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (917:917:917) (902:902:902)) - (PORT ena (645:645:645) (697:697:697)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (157:157:157) (214:214:214)) - (PORT datac (501:501:501) (586:586:586)) - (PORT datad (505:505:505) (592:592:592)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~1) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (947:947:947)) - (PORT datab (481:481:481) (557:557:557)) - (PORT datac (501:501:501) (610:610:610)) - (PORT datad (468:468:468) (544:544:544)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) - (DELAY - (ABSOLUTE - (PORT dataa (874:874:874) (1034:1034:1034)) - (PORT datab (1302:1302:1302) (1480:1480:1480)) - (PORT datac (364:364:364) (432:432:432)) - (PORT datad (1513:1513:1513) (1746:1746:1746)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (122:122:122) (157:157:157)) - (PORT datac (101:101:101) (128:128:128)) - (PORT datad (195:195:195) (226:226:226)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) - (DELAY - (ABSOLUTE - (PORT dataa (329:329:329) (383:383:383)) - (PORT datab (230:230:230) (273:273:273)) - (PORT datac (290:290:290) (331:331:331)) - (PORT datad (651:651:651) (746:746:746)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (994:994:994)) - (PORT datab (229:229:229) (277:277:277)) - (PORT datac (519:519:519) (601:601:601)) - (PORT datad (112:112:112) (133:133:133)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) - (DELAY - (ABSOLUTE - (PORT dataa (550:550:550) (643:643:643)) - (PORT datab (627:627:627) (714:714:714)) - (PORT datac (714:714:714) (833:833:833)) - (PORT datad (756:756:756) (864:864:864)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (683:683:683)) - (PORT datab (552:552:552) (654:654:654)) - (PORT datac (716:716:716) (835:835:835)) - (PORT datad (697:697:697) (795:795:795)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) - (DELAY - (ABSOLUTE - (PORT dataa (814:814:814) (919:919:919)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (461:461:461) (519:519:519)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (1001:1001:1001)) - (PORT datab (450:450:450) (525:525:525)) - (PORT datad (557:557:557) (632:632:632)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (1003:1003:1003)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (348:348:348) (413:413:413)) - (PORT datad (295:295:295) (338:338:338)) + (PORT dataa (262:262:262) (335:335:335)) + (PORT datab (481:481:481) (574:574:574)) + (PORT datac (326:326:326) (385:385:385)) + (PORT datad (102:102:102) (126:126:126)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -38062,246 +37689,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~92) (DELAY (ABSOLUTE - (PORT dataa (332:332:332) (399:399:399)) - (PORT datab (288:288:288) (333:333:333)) - (PORT datac (102:102:102) (123:123:123)) - (PORT datad (193:193:193) (226:226:226)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1233:1233:1233) (1408:1408:1408)) - (PORT datab (883:883:883) (1032:1032:1032)) - (PORT datac (492:492:492) (577:577:577)) - (PORT datad (622:622:622) (713:713:713)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) - (DELAY - (ABSOLUTE - (PORT datab (120:120:120) (155:155:155)) - (PORT datac (176:176:176) (209:209:209)) - (PORT datad (191:191:191) (224:224:224)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) - (DELAY - (ABSOLUTE - (PORT dataa (704:704:704) (829:829:829)) - (PORT datab (511:511:511) (600:600:600)) - (PORT datac (1119:1119:1119) (1312:1312:1312)) - (PORT datad (1169:1169:1169) (1381:1381:1381)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (553:553:553)) - (PORT datab (120:120:120) (155:155:155)) - (PORT datac (104:104:104) (132:132:132)) - (PORT datad (191:191:191) (223:223:223)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (721:721:721)) - (PORT datab (104:104:104) (132:132:132)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (144:144:144)) - (PORT datab (117:117:117) (151:151:151)) - (PORT datac (105:105:105) (128:128:128)) - (PORT datad (120:120:120) (138:138:138)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1087:1087:1087) (1273:1273:1273)) - (PORT datab (1458:1458:1458) (1689:1689:1689)) - (PORT datad (811:811:811) (945:945:945)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (434:434:434)) - (PORT datab (383:383:383) (458:458:458)) - (PORT datac (593:593:593) (676:676:676)) - (PORT datad (358:358:358) (416:416:416)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (140:140:140)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (325:325:325) (382:382:382)) - (PORT datad (424:424:424) (480:480:480)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) - (DELAY - (ABSOLUTE - (PORT dataa (464:464:464) (539:539:539)) - (PORT datab (171:171:171) (208:208:208)) - (PORT datac (191:191:191) (228:228:228)) - (PORT datad (330:330:330) (383:383:383)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1014:1014:1014) (1196:1196:1196)) - (PORT datab (498:498:498) (595:595:595)) - (PORT datac (499:499:499) (608:608:608)) - (PORT datad (227:227:227) (269:269:269)) - (IOPATH dataa combout (159:159:159) (173:173:173)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (505:505:505) (583:583:583)) - (PORT datac (494:494:494) (563:563:563)) - (PORT datad (768:768:768) (891:891:891)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (257:257:257)) - (PORT datac (101:101:101) (122:122:122)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (759:759:759)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (310:310:310) (366:366:366)) - (PORT datad (190:190:190) (226:226:226)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (759:759:759)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datad (480:480:480) (559:559:559)) - (IOPATH dataa combout (172:172:172) (165:165:165)) - (IOPATH datab combout (169:169:169) (167:167:167)) + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (530:530:530) (637:637:637)) + (PORT datad (246:246:246) (305:305:305)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -38309,12 +37704,14 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) (DELAY (ABSOLUTE - (PORT clk (896:896:896) (902:902:902)) + (PORT clk (892:892:892) (898:898:898)) (PORT d (37:37:37) (50:50:50)) + (PORT clrn (885:885:885) (889:889:889)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK @@ -38323,809 +37720,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) + (INSTANCE D\[3\]\~72) (DELAY (ABSOLUTE - (PORT dataa (1338:1338:1338) (1530:1530:1530)) - (PORT datab (891:891:891) (1046:1046:1046)) - (PORT datac (1005:1005:1005) (1176:1176:1176)) - (PORT datad (938:938:938) (1076:1076:1076)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) - (DELAY - (ABSOLUTE - (PORT dataa (801:801:801) (942:942:942)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (585:585:585) (679:679:679)) - (PORT datad (727:727:727) (829:829:829)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (786:786:786)) - (PORT datac (490:490:490) (579:579:579)) - (PORT datad (531:531:531) (625:625:625)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) - (DELAY - (ABSOLUTE - (PORT dataa (495:495:495) (570:570:570)) - (PORT datab (528:528:528) (618:618:618)) - (PORT datac (310:310:310) (355:355:355)) - (PORT datad (282:282:282) (315:315:315)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (452:452:452) (520:520:520)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (100:100:100) (124:124:124)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (769:769:769)) - (PORT datab (139:139:139) (191:191:191)) - (PORT datac (116:116:116) (157:157:157)) - (PORT datad (318:318:318) (367:367:367)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~20) - (DELAY - (ABSOLUTE - (PORT dataa (303:303:303) (355:355:355)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (326:326:326) (377:377:377)) - (PORT datad (318:318:318) (359:359:359)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (1057:1057:1057)) - (PORT datab (1441:1441:1441) (1668:1668:1668)) - (PORT datac (584:584:584) (667:667:667)) - (PORT datad (486:486:486) (557:557:557)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) - (DELAY - (ABSOLUTE - (PORT dataa (598:598:598) (690:690:690)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (662:662:662) (752:752:752)) - (PORT datad (292:292:292) (331:331:331)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) - (DELAY - (ABSOLUTE - (PORT dataa (474:474:474) (552:552:552)) - (PORT datab (115:115:115) (144:144:144)) - (PORT datac (128:128:128) (154:154:154)) - (PORT datad (319:319:319) (372:372:372)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) - (DELAY - (ABSOLUTE - (PORT dataa (522:522:522) (620:620:620)) - (PORT datab (143:143:143) (176:176:176)) - (PORT datac (778:778:778) (901:901:901)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) - (DELAY - (ABSOLUTE - (PORT dataa (506:506:506) (585:585:585)) - (PORT datab (613:613:613) (718:718:718)) - (PORT datac (497:497:497) (574:574:574)) - (PORT datad (550:550:550) (616:616:616)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_set\~0) - (DELAY - (ABSOLUTE - (PORT dataa (250:250:250) (297:297:297)) - (PORT datab (484:484:484) (559:559:559)) - (PORT datac (499:499:499) (608:608:608)) - (PORT datad (218:218:218) (252:252:252)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) - (DELAY - (ABSOLUTE - (PORT datab (582:582:582) (662:662:662)) - (PORT datac (110:110:110) (135:135:135)) - (PORT datad (110:110:110) (130:130:130)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~9) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (279:279:279) (322:322:322)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_cf) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (309:309:309) (361:361:361)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (299:299:299) (346:346:346)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (380:380:380) (448:448:448)) - (PORT datab (362:362:362) (431:431:431)) - (PORT datac (481:481:481) (550:550:550)) - (PORT datad (477:477:477) (548:548:548)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (629:629:629) (724:724:724)) - (PORT datad (336:336:336) (387:387:387)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (230:230:230)) - (PORT datab (344:344:344) (402:402:402)) - (PORT datac (476:476:476) (549:549:549)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (436:436:436)) - (PORT datab (513:513:513) (599:599:599)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (113:113:113) (137:137:137)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (460:460:460)) - (PORT datac (596:596:596) (699:699:699)) - (PORT datad (408:408:408) (499:499:499)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (414:414:414) (524:524:524)) - (PORT datab (394:394:394) (484:484:484)) - (PORT datac (598:598:598) (701:701:701)) - (PORT datad (385:385:385) (471:471:471)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (493:493:493) (588:588:588)) - (PORT datac (597:597:597) (700:700:700)) - (PORT datad (172:172:172) (200:200:200)) + (PORT dataa (390:390:390) (457:457:457)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datac (1371:1371:1371) (1616:1616:1616)) + (PORT datad (486:486:486) (563:563:563)) (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~83) + (INSTANCE D\[3\]\~76) (DELAY (ABSOLUTE - (PORT dataa (112:112:112) (148:148:148)) + (PORT dataa (484:484:484) (559:559:559)) (PORT datab (103:103:103) (132:132:132)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (190:190:190) (195:195:195)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (401:401:401) (482:482:482)) - (PORT datab (535:535:535) (638:638:638)) - (PORT datac (408:408:408) (506:506:506)) - (PORT datad (413:413:413) (505:505:505)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (445:445:445) (545:545:545)) - (PORT datab (410:410:410) (500:500:500)) - (PORT datac (400:400:400) (487:487:487)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (224:224:224)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datad (171:171:171) (202:202:202)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (742:742:742)) - (PORT datab (392:392:392) (480:480:480)) - (PORT datac (116:116:116) (156:156:156)) - (PORT datad (290:290:290) (338:338:338)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (504:504:504) (614:614:614)) - (PORT datab (430:430:430) (528:528:528)) - (PORT datac (758:758:758) (914:914:914)) - (PORT datad (644:644:644) (761:761:761)) - (IOPATH dataa combout (159:159:159) (173:173:173)) - (IOPATH datab combout (161:161:161) (176:176:176)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~76) - (DELAY - (ABSOLUTE - (PORT dataa (177:177:177) (219:219:219)) - (PORT datab (153:153:153) (201:201:201)) - (PORT datac (517:517:517) (597:597:597)) - (PORT datad (839:839:839) (979:979:979)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~73) - (DELAY - (ABSOLUTE - (PORT datac (406:406:406) (503:503:503)) - (PORT datad (647:647:647) (765:765:765)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (519:519:519)) - (PORT datab (397:397:397) (487:487:487)) - (PORT datac (477:477:477) (565:565:565)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (406:406:406) (499:499:499)) - (PORT datab (846:846:846) (997:997:997)) - (PORT datac (491:491:491) (594:594:594)) - (PORT datad (459:459:459) (543:543:543)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~74) - (DELAY - (ABSOLUTE - (PORT dataa (308:308:308) (361:361:361)) - (PORT datab (174:174:174) (210:210:210)) - (PORT datac (756:756:756) (911:911:911)) - (PORT datad (864:864:864) (1017:1017:1017)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (105:105:105) (135:135:135)) - (PORT datac (234:234:234) (293:293:293)) - (PORT datad (448:448:448) (518:518:518)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (287:287:287) (330:330:330)) - (PORT datab (171:171:171) (209:209:209)) - (PORT datad (404:404:404) (493:493:493)) - (IOPATH dataa combout (159:159:159) (173:173:173)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (513:513:513)) - (PORT datab (404:404:404) (495:495:495)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (610:610:610) (712:712:712)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~72) - (DELAY - (ABSOLUTE - (PORT datab (103:103:103) (132:132:132)) - (PORT datad (403:403:403) (484:484:484)) - (IOPATH datab combout (191:191:191) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (257:257:257)) - (PORT datab (639:639:639) (748:748:748)) - (PORT datac (350:350:350) (419:419:419)) - (PORT datad (337:337:337) (404:404:404)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (1025:1025:1025)) - (PORT datab (520:520:520) (619:619:619)) - (PORT datad (267:267:267) (305:305:305)) - (IOPATH dataa combout (159:159:159) (165:165:165)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (255:255:255) (330:330:330)) - (PORT datac (321:321:321) (387:387:387)) - (PORT datad (142:142:142) (184:184:184)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (243:243:243)) - (PORT datab (443:443:443) (515:515:515)) - (PORT datad (401:401:401) (491:491:491)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~1) - (DELAY - (ABSOLUTE - (PORT datab (845:845:845) (994:994:994)) - (PORT datac (181:181:181) (230:230:230)) - (PORT datad (489:489:489) (577:577:577)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datac (117:117:117) (158:158:158)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~1) - (DELAY - (ABSOLUTE - (PORT datac (598:598:598) (727:727:727)) - (PORT datad (577:577:577) (691:691:691)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (788:788:788) (949:949:949)) - (PORT datab (437:437:437) (539:539:539)) - (PORT datac (518:518:518) (616:616:616)) - (PORT datad (420:420:420) (525:525:525)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (142:142:142)) - (PORT datab (359:359:359) (429:429:429)) - (PORT datac (321:321:321) (376:376:376)) - (PORT datad (487:487:487) (584:584:584)) + (PORT datac (175:175:175) (207:207:207)) + (PORT datad (323:323:323) (378:378:378)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -39135,324 +37752,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~92) + (INSTANCE D\[3\]\~122) (DELAY (ABSOLUTE - (PORT datab (525:525:525) (630:630:630)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~63) - (DELAY - (ABSOLUTE - (PORT datac (341:341:341) (415:415:415)) - (PORT datad (342:342:342) (406:406:406)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) - (DELAY - (ABSOLUTE - (PORT datab (346:346:346) (418:418:418)) - (PORT datac (361:361:361) (461:461:461)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (144:144:144)) - (PORT datab (249:249:249) (312:312:312)) - (PORT datac (343:343:343) (412:412:412)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~132) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (153:153:153)) - (PORT datab (354:354:354) (429:429:429)) - (PORT datad (348:348:348) (423:423:423)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (455:455:455) (541:541:541)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (280:280:280) (323:323:323)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (430:430:430) (494:494:494)) - (PORT datad (503:503:503) (597:597:597)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (780:780:780) (900:900:900)) - (PORT datab (311:311:311) (377:377:377)) - (PORT datac (770:770:770) (877:877:877)) - (PORT datad (119:119:119) (156:156:156)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (488:488:488)) - (PORT datab (1905:1905:1905) (2163:2163:2163)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (92:92:92) (110:110:110)) + (PORT dataa (607:607:607) (692:692:692)) + (PORT datab (713:713:713) (845:845:845)) + (PORT datac (1471:1471:1471) (1729:1729:1729)) + (PORT datad (353:353:353) (414:414:414)) (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (489:489:489) (554:554:554)) - (PORT clk (1098:1098:1098) (1115:1115:1115)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (692:692:692) (785:785:785)) - (PORT d[1] (555:555:555) (645:645:645)) - (PORT d[2] (539:539:539) (612:612:612)) - (PORT d[3] (570:570:570) (664:664:664)) - (PORT d[4] (1524:1524:1524) (1787:1787:1787)) - (PORT d[5] (567:567:567) (665:665:665)) - (PORT d[6] (566:566:566) (652:652:652)) - (PORT d[7] (538:538:538) (620:620:620)) - (PORT d[8] (582:582:582) (677:677:677)) - (PORT d[9] (556:556:556) (651:651:651)) - (PORT d[10] (600:600:600) (694:694:694)) - (PORT d[11] (1498:1498:1498) (1745:1745:1745)) - (PORT d[12] (743:743:743) (860:860:860)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (519:519:519) (547:547:547)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (PORT d[0] (809:809:809) (845:845:845)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1078:1078:1078) (1094:1094:1094)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (528:528:528) (606:606:606)) + (PORT d[0] (618:618:618) (690:690:690)) (PORT clk (1097:1097:1097) (1114:1114:1114)) ) ) @@ -39462,22 +37781,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (388:388:388) (446:446:446)) - (PORT d[1] (1400:1400:1400) (1651:1651:1651)) - (PORT d[2] (850:850:850) (968:968:968)) - (PORT d[3] (558:558:558) (641:641:641)) - (PORT d[4] (1510:1510:1510) (1771:1771:1771)) - (PORT d[5] (2023:2023:2023) (2340:2340:2340)) - (PORT d[6] (729:729:729) (838:838:838)) - (PORT d[7] (1869:1869:1869) (2113:2113:2113)) - (PORT d[8] (377:377:377) (441:441:441)) - (PORT d[9] (912:912:912) (1053:1053:1053)) - (PORT d[10] (777:777:777) (894:894:894)) - (PORT d[11] (1301:1301:1301) (1515:1515:1515)) - (PORT d[12] (893:893:893) (1028:1028:1028)) + (PORT d[0] (1496:1496:1496) (1741:1741:1741)) + (PORT d[1] (2126:2126:2126) (2427:2427:2427)) + (PORT d[2] (1357:1357:1357) (1560:1560:1560)) + (PORT d[3] (2512:2512:2512) (2851:2851:2851)) + (PORT d[4] (1870:1870:1870) (2188:2188:2188)) + (PORT d[5] (2727:2727:2727) (3117:3117:3117)) + (PORT d[6] (1467:1467:1467) (1669:1669:1669)) + (PORT d[7] (784:784:784) (887:887:887)) + (PORT d[8] (1612:1612:1612) (1880:1880:1880)) + (PORT d[9] (1015:1015:1015) (1153:1153:1153)) + (PORT d[10] (959:959:959) (1086:1086:1086)) + (PORT d[11] (1981:1981:1981) (2318:2318:2318)) + (PORT d[12] (2725:2725:2725) (3085:3085:3085)) (PORT clk (1095:1095:1095) (1112:1112:1112)) ) ) @@ -39487,10 +37806,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (355:355:355) (356:356:356)) + (PORT d[0] (912:912:912) (975:975:975)) (PORT clk (1095:1095:1095) (1112:1112:1112)) ) ) @@ -39500,17 +37819,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1097:1097:1097) (1114:1114:1114)) - (PORT d[0] (800:800:800) (826:826:826)) + (PORT d[0] (1242:1242:1242) (1328:1328:1328)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1098:1098:1098) (1115:1115:1115)) @@ -39520,7 +37839,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1098:1098:1098) (1115:1115:1115)) @@ -39530,7 +37849,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1098:1098:1098) (1115:1115:1115)) @@ -39540,7 +37859,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1098:1098:1098) (1115:1115:1115)) @@ -39550,7 +37869,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1077:1077:1077) (1093:1093:1093)) @@ -39564,7 +37883,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (617:617:617) (625:625:625)) @@ -39573,7 +37892,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) (DELAY (ABSOLUTE (PORT clk (618:618:618) (626:626:626)) @@ -39582,7 +37901,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (618:618:618) (626:626:626)) @@ -39592,7 +37911,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (618:618:618) (626:626:626)) @@ -39601,11 +37920,27 @@ ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~79) (DELAY (ABSOLUTE - (PORT d[0] (593:593:593) (668:668:668)) + (PORT dataa (641:641:641) (759:759:759)) + (PORT datab (366:366:366) (433:433:433)) + (PORT datac (771:771:771) (884:884:884)) + (PORT datad (602:602:602) (688:688:688)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (632:632:632) (706:706:706)) (PORT clk (1097:1097:1097) (1114:1114:1114)) ) ) @@ -39615,22 +37950,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (539:539:539) (619:619:619)) - (PORT d[1] (2026:2026:2026) (2346:2346:2346)) - (PORT d[2] (705:705:705) (808:808:808)) - (PORT d[3] (715:715:715) (826:826:826)) - (PORT d[4] (1504:1504:1504) (1764:1764:1764)) - (PORT d[5] (2029:2029:2029) (2352:2352:2352)) - (PORT d[6] (754:754:754) (872:872:872)) - (PORT d[7] (692:692:692) (792:792:792)) - (PORT d[8] (552:552:552) (638:638:638)) - (PORT d[9] (891:891:891) (1024:1024:1024)) - (PORT d[10] (788:788:788) (909:909:909)) - (PORT d[11] (1310:1310:1310) (1527:1527:1527)) - (PORT d[12] (919:919:919) (1062:1062:1062)) + (PORT d[0] (965:965:965) (1149:1149:1149)) + (PORT d[1] (1619:1619:1619) (1828:1828:1828)) + (PORT d[2] (1371:1371:1371) (1567:1567:1567)) + (PORT d[3] (2502:2502:2502) (2839:2839:2839)) + (PORT d[4] (544:544:544) (629:629:629)) + (PORT d[5] (1237:1237:1237) (1403:1403:1403)) + (PORT d[6] (1468:1468:1468) (1670:1670:1670)) + (PORT d[7] (758:758:758) (852:852:852)) + (PORT d[8] (1599:1599:1599) (1859:1859:1859)) + (PORT d[9] (840:840:840) (949:949:949)) + (PORT d[10] (1112:1112:1112) (1256:1256:1256)) + (PORT d[11] (1982:1982:1982) (2319:2319:2319)) + (PORT d[12] (2790:2790:2790) (3157:3157:3157)) (PORT clk (1095:1095:1095) (1112:1112:1112)) ) ) @@ -39640,10 +37975,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (518:518:518) (544:544:544)) + (PORT d[0] (1456:1456:1456) (1585:1585:1585)) (PORT clk (1095:1095:1095) (1112:1112:1112)) ) ) @@ -39653,17 +37988,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1097:1097:1097) (1114:1114:1114)) - (PORT d[0] (912:912:912) (949:949:949)) + (PORT d[0] (1228:1228:1228) (1312:1312:1312)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1098:1098:1098) (1115:1115:1115)) @@ -39673,7 +38008,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1098:1098:1098) (1115:1115:1115)) @@ -39683,7 +38018,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1098:1098:1098) (1115:1115:1115)) @@ -39693,7 +38028,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1098:1098:1098) (1115:1115:1115)) @@ -39703,7 +38038,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1077:1077:1077) (1093:1093:1093)) @@ -39717,7 +38052,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (617:617:617) (625:625:625)) @@ -39726,7 +38061,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) (DELAY (ABSOLUTE (PORT clk (618:618:618) (626:626:626)) @@ -39735,7 +38070,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (618:618:618) (626:626:626)) @@ -39745,7 +38080,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (618:618:618) (626:626:626)) @@ -39753,29 +38088,13 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (246:246:246)) - (PORT datab (355:355:355) (426:426:426)) - (PORT datac (352:352:352) (416:416:416)) - (PORT datad (349:349:349) (402:402:402)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (652:652:652) (746:746:746)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (409:409:409) (468:468:468)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) ) ) (TIMINGCHECK @@ -39784,23 +38103,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2062:2062:2062) (2392:2392:2392)) - (PORT d[1] (795:795:795) (938:938:938)) - (PORT d[2] (1144:1144:1144) (1312:1312:1312)) - (PORT d[3] (1386:1386:1386) (1609:1609:1609)) - (PORT d[4] (1274:1274:1274) (1480:1480:1480)) - (PORT d[5] (775:775:775) (917:917:917)) - (PORT d[6] (824:824:824) (954:954:954)) - (PORT d[7] (1952:1952:1952) (2204:2204:2204)) - (PORT d[8] (2104:2104:2104) (2435:2435:2435)) - (PORT d[9] (1815:1815:1815) (2090:2090:2090)) - (PORT d[10] (1826:1826:1826) (2094:2094:2094)) - (PORT d[11] (1007:1007:1007) (1167:1167:1167)) - (PORT d[12] (814:814:814) (935:935:935)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (1800:1800:1800) (2127:2127:2127)) + (PORT d[1] (925:925:925) (1072:1072:1072)) + (PORT d[2] (567:567:567) (658:658:658)) + (PORT d[3] (540:540:540) (624:624:624)) + (PORT d[4] (1894:1894:1894) (2181:2181:2181)) + (PORT d[5] (530:530:530) (613:613:613)) + (PORT d[6] (915:915:915) (1062:1062:1062)) + (PORT d[7] (539:539:539) (628:628:628)) + (PORT d[8] (709:709:709) (828:828:828)) + (PORT d[9] (604:604:604) (702:702:702)) + (PORT d[10] (580:580:580) (673:673:673)) + (PORT d[11] (1268:1268:1268) (1485:1485:1485)) + (PORT d[12] (620:620:620) (723:723:723)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) ) ) (TIMINGCHECK @@ -39809,11 +38128,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (890:890:890) (960:960:960)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (523:523:523) (550:550:550)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) ) ) (TIMINGCHECK @@ -39822,17 +38141,170 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (PORT d[0] (1554:1554:1554) (1684:1684:1684)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (PORT d[0] (1662:1662:1662) (1834:1834:1834)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (561:561:561) (633:633:633)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1769:1769:1769) (2086:2086:2086)) + (PORT d[1] (923:923:923) (1067:1067:1067)) + (PORT d[2] (541:541:541) (628:628:628)) + (PORT d[3] (528:528:528) (614:614:614)) + (PORT d[4] (792:792:792) (905:905:905)) + (PORT d[5] (510:510:510) (589:589:589)) + (PORT d[6] (1081:1081:1081) (1253:1253:1253)) + (PORT d[7] (508:508:508) (588:588:588)) + (PORT d[8] (720:720:720) (838:838:838)) + (PORT d[9] (429:429:429) (500:500:500)) + (PORT d[10] (426:426:426) (500:500:500)) + (PORT d[11] (1459:1459:1459) (1705:1705:1705)) + (PORT d[12] (439:439:439) (517:517:517)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (360:360:360) (353:353:353)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (981:981:981) (1037:1037:1037)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1092:1092:1092) (1109:1109:1109)) @@ -39842,7 +38314,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1092:1092:1092) (1109:1109:1109)) @@ -39852,7 +38324,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1092:1092:1092) (1109:1109:1109)) @@ -39862,7 +38334,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1092:1092:1092) (1109:1109:1109)) @@ -39872,7 +38344,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1071:1071:1071) (1087:1087:1087)) @@ -39886,7 +38358,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (611:611:611) (619:619:619)) @@ -39895,7 +38367,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) (DELAY (ABSOLUTE (PORT clk (612:612:612) (620:620:620)) @@ -39904,7 +38376,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (612:612:612) (620:620:620)) @@ -39914,7 +38386,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (612:612:612) (620:620:620)) @@ -39922,29 +38394,25 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (571:571:571) (652:652:652)) - (PORT datab (785:785:785) (918:918:918)) - (PORT datac (276:276:276) (323:323:323)) - (PORT datad (654:654:654) (746:746:746)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (914:914:914) (1070:1070:1070)) - (PORT clk (1096:1096:1096) (1114:1114:1114)) + (PORT d[0] (1330:1330:1330) (1554:1554:1554)) + (PORT d[1] (1603:1603:1603) (1809:1809:1809)) + (PORT d[2] (1366:1366:1366) (1568:1568:1568)) + (PORT d[3] (2665:2665:2665) (3022:3022:3022)) + (PORT d[4] (556:556:556) (645:645:645)) + (PORT d[5] (1214:1214:1214) (1374:1374:1374)) + (PORT d[6] (513:513:513) (581:581:581)) + (PORT d[7] (734:734:734) (823:823:823)) + (PORT d[8] (1603:1603:1603) (1869:1869:1869)) + (PORT d[9] (832:832:832) (940:940:940)) + (PORT d[10] (1125:1125:1125) (1270:1270:1270)) + (PORT d[11] (2158:2158:2158) (2516:2516:2516)) + (PORT d[12] (2804:2804:2804) (3176:3176:3176)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) ) ) (TIMINGCHECK @@ -39953,98 +38421,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) (DELAY (ABSOLUTE - (PORT d[0] (1612:1612:1612) (1843:1843:1843)) - (PORT d[1] (1155:1155:1155) (1367:1367:1367)) - (PORT d[2] (1117:1117:1117) (1292:1292:1292)) - (PORT d[3] (1070:1070:1070) (1255:1255:1255)) - (PORT d[4] (1763:1763:1763) (2023:2023:2023)) - (PORT d[5] (1312:1312:1312) (1534:1534:1534)) - (PORT d[6] (982:982:982) (1126:1126:1126)) - (PORT d[7] (1219:1219:1219) (1414:1414:1414)) - (PORT d[8] (1382:1382:1382) (1622:1622:1622)) - (PORT d[9] (965:965:965) (1112:1112:1112)) - (PORT d[10] (820:820:820) (943:943:943)) - (PORT d[11] (960:960:960) (1098:1098:1098)) - (PORT d[12] (1308:1308:1308) (1499:1499:1499)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1425:1425:1425) (1591:1591:1591)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1114:1114:1114)) - (PORT d[0] (2282:2282:2282) (2098:2098:2098)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (PORT d[0] (809:809:809) (745:745:745)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1051:1051:1051) (1071:1071:1071)) + (PORT clk (1076:1076:1076) (1092:1092:1092)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -40055,97 +38455,296 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (1117:1117:1117) (1240:1240:1240)) - (PORT clk (1056:1056:1056) (1074:1074:1074)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2452:2452:2452) (2784:2784:2784)) - (PORT d[1] (2314:2314:2314) (2623:2623:2623)) - (PORT d[2] (2389:2389:2389) (2699:2699:2699)) - (PORT d[3] (2550:2550:2550) (2907:2907:2907)) - (PORT d[4] (2364:2364:2364) (2679:2679:2679)) - (PORT d[5] (2568:2568:2568) (2916:2916:2916)) - (PORT d[6] (2462:2462:2462) (2816:2816:2816)) - (PORT d[7] (2364:2364:2364) (2657:2657:2657)) - (PORT d[8] (2551:2551:2551) (2900:2900:2900)) - (PORT d[9] (2545:2545:2545) (2918:2918:2918)) - (PORT d[10] (2631:2631:2631) (2982:2982:2982)) - (PORT d[11] (2413:2413:2413) (2724:2724:2724)) - (PORT d[12] (2561:2561:2561) (2915:2915:2915)) - (PORT clk (1053:1053:1053) (1073:1073:1073)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1056:1056:1056) (1074:1074:1074)) + (PORT clk (616:616:616) (624:624:624)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1057:1057:1057) (1075:1075:1075)) + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (1102:1102:1102) (1267:1267:1267)) + (PORT datab (851:851:851) (984:984:984)) + (PORT datac (500:500:500) (563:563:563)) + (PORT datad (591:591:591) (675:675:675)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~80) + (DELAY + (ABSOLUTE + (PORT datab (486:486:486) (556:556:556)) + (PORT datac (771:771:771) (884:884:884)) + (PORT datad (94:94:94) (112:112:112)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (983:983:983)) + (PORT datab (628:628:628) (717:717:717)) + (PORT datac (91:91:91) (112:112:112)) + (PORT datad (1017:1017:1017) (1172:1172:1172)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (796:796:796) (904:904:904)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1418:1418:1418) (1643:1643:1643)) + (PORT d[1] (1567:1567:1567) (1789:1789:1789)) + (PORT d[2] (1482:1482:1482) (1705:1705:1705)) + (PORT d[3] (1939:1939:1939) (2194:2194:2194)) + (PORT d[4] (1324:1324:1324) (1555:1555:1555)) + (PORT d[5] (2153:2153:2153) (2452:2452:2452)) + (PORT d[6] (1462:1462:1462) (1666:1666:1666)) + (PORT d[7] (1936:1936:1936) (2205:2205:2205)) + (PORT d[8] (1666:1666:1666) (1901:1901:1901)) + (PORT d[9] (1585:1585:1585) (1810:1810:1810)) + (PORT d[10] (1499:1499:1499) (1705:1705:1705)) + (PORT d[11] (1426:1426:1426) (1677:1677:1677)) + (PORT d[12] (2085:2085:2085) (2366:2366:2366)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1641:1641:1641) (1792:1792:1792)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT d[0] (2145:2145:2145) (1989:1989:1989)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1057:1057:1057) (1075:1075:1075)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1071:1071:1071)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1350:1350:1350) (1504:1504:1504)) + (PORT clk (1057:1057:1057) (1074:1074:1074)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2471:2471:2471) (2783:2783:2783)) + (PORT d[1] (2502:2502:2502) (2825:2825:2825)) + (PORT d[2] (2515:2515:2515) (2832:2832:2832)) + (PORT d[3] (2434:2434:2434) (2750:2750:2750)) + (PORT d[4] (2424:2424:2424) (2763:2763:2763)) + (PORT d[5] (2474:2474:2474) (2805:2805:2805)) + (PORT d[6] (2470:2470:2470) (2777:2777:2777)) + (PORT d[7] (2424:2424:2424) (2719:2719:2719)) + (PORT d[8] (2462:2462:2462) (2784:2784:2784)) + (PORT d[9] (2452:2452:2452) (2796:2796:2796)) + (PORT d[10] (2383:2383:2383) (2682:2682:2682)) + (PORT d[11] (2452:2452:2452) (2792:2792:2792)) + (PORT d[12] (2340:2340:2340) (2638:2638:2638)) + (PORT clk (1054:1054:1054) (1073:1073:1073)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1074:1074:1074)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1058:1058:1058) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1058:1058:1058) (1075:1075:1075)) (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1057:1057:1057) (1075:1075:1075)) + (PORT clk (1058:1058:1058) (1075:1075:1075)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1057:1057:1057) (1075:1075:1075)) + (PORT clk (1058:1058:1058) (1075:1075:1075)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) (DELAY (ABSOLUTE - (PORT clk (1052:1052:1052) (1072:1072:1072)) + (PORT clk (1053:1053:1053) (1072:1072:1072)) (IOPATH (posedge clk) q (164:164:164) (166:166:166)) ) ) @@ -40154,338 +38753,569 @@ (HOLD d (posedge clk) (90:90:90)) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1588:1588:1588) (1816:1816:1816)) - (PORT d[1] (992:992:992) (1179:1179:1179)) - (PORT d[2] (1103:1103:1103) (1283:1283:1283)) - (PORT d[3] (1062:1062:1062) (1246:1246:1246)) - (PORT d[4] (1617:1617:1617) (1864:1864:1864)) - (PORT d[5] (1317:1317:1317) (1540:1540:1540)) - (PORT d[6] (1154:1154:1154) (1319:1319:1319)) - (PORT d[7] (1225:1225:1225) (1427:1427:1427)) - (PORT d[8] (1375:1375:1375) (1606:1606:1606)) - (PORT d[9] (1130:1130:1130) (1297:1297:1297)) - (PORT d[10] (1111:1111:1111) (1274:1274:1274)) - (PORT d[11] (1134:1134:1134) (1293:1293:1293)) - (PORT d[12] (1458:1458:1458) (1670:1670:1670)) - (PORT clk (1097:1097:1097) (1115:1115:1115)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (PORT d[0] (1576:1576:1576) (1776:1776:1776)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1079:1079:1079) (1096:1096:1096)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (628:628:628)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (620:620:620) (629:629:629)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (620:620:620) (629:629:629)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (620:620:620) (629:629:629)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (906:906:906) (1058:1058:1058)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1607:1607:1607) (1841:1841:1841)) - (PORT d[1] (1178:1178:1178) (1395:1395:1395)) - (PORT d[2] (1073:1073:1073) (1246:1246:1246)) - (PORT d[3] (1061:1061:1061) (1246:1246:1246)) - (PORT d[4] (1778:1778:1778) (2032:2032:2032)) - (PORT d[5] (1152:1152:1152) (1354:1354:1354)) - (PORT d[6] (984:984:984) (1132:1132:1132)) - (PORT d[7] (1029:1029:1029) (1190:1190:1190)) - (PORT d[8] (1394:1394:1394) (1627:1627:1627)) - (PORT d[9] (1130:1130:1130) (1298:1298:1298)) - (PORT d[10] (1118:1118:1118) (1290:1290:1290)) - (PORT d[11] (1424:1424:1424) (1619:1619:1619)) - (PORT d[12] (1271:1271:1271) (1457:1457:1457)) - (PORT clk (1092:1092:1092) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1419:1419:1419) (1556:1556:1556)) - (PORT clk (1092:1092:1092) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1112:1112:1112)) - (PORT d[0] (2096:2096:2096) (2313:2313:2313)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1049:1049:1049) (1069:1069:1069)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1117:1117:1117) (1241:1241:1241)) - (PORT clk (1054:1054:1054) (1072:1072:1072)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2473:2473:2473) (2812:2812:2812)) - (PORT d[1] (2361:2361:2361) (2677:2677:2677)) - (PORT d[2] (2402:2402:2402) (2727:2727:2727)) - (PORT d[3] (2543:2543:2543) (2900:2900:2900)) - (PORT d[4] (2378:2378:2378) (2698:2698:2698)) - (PORT d[5] (2560:2560:2560) (2905:2905:2905)) - (PORT d[6] (2623:2623:2623) (2996:2996:2996)) - (PORT d[7] (2364:2364:2364) (2664:2664:2664)) - (PORT d[8] (2457:2457:2457) (2789:2789:2789)) - (PORT d[9] (2540:2540:2540) (2926:2926:2926)) - (PORT d[10] (2593:2593:2593) (2922:2922:2922)) - (PORT d[11] (2412:2412:2412) (2719:2719:2719)) - (PORT d[12] (2561:2561:2561) (2914:2914:2914)) - (PORT clk (1051:1051:1051) (1071:1071:1071)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1054:1054:1054) (1072:1072:1072)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1073:1073:1073)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1073:1073:1073)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1073:1073:1073)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1073:1073:1073)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~52) + (INSTANCE D\[3\]\~124) (DELAY (ABSOLUTE - (PORT dataa (667:667:667) (789:789:789)) - (PORT datab (803:803:803) (920:920:920)) - (PORT datac (624:624:624) (734:734:734)) - (PORT datad (798:798:798) (908:908:908)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT dataa (1498:1498:1498) (1759:1759:1759)) + (PORT datab (1390:1390:1390) (1610:1610:1610)) + (PORT datac (901:901:901) (1043:1043:1043)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2050:2050:2050) (2378:2378:2378)) - (PORT d[1] (1539:1539:1539) (1803:1803:1803)) - (PORT d[2] (930:930:930) (1089:1089:1089)) - (PORT d[3] (1196:1196:1196) (1398:1398:1398)) - (PORT d[4] (1249:1249:1249) (1444:1444:1444)) - (PORT d[5] (957:957:957) (1133:1133:1133)) - (PORT d[6] (636:636:636) (734:734:734)) - (PORT d[7] (650:650:650) (750:750:750)) - (PORT d[8] (1254:1254:1254) (1478:1478:1478)) - (PORT d[9] (1328:1328:1328) (1519:1519:1519)) - (PORT d[10] (1463:1463:1463) (1678:1678:1678)) - (PORT d[11] (502:502:502) (579:579:579)) - (PORT d[12] (986:986:986) (1140:1140:1140)) + (PORT d[0] (791:791:791) (890:890:890)) + (PORT clk (1091:1091:1091) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1114:1114:1114) (1308:1308:1308)) + (PORT d[1] (1755:1755:1755) (2009:2009:2009)) + (PORT d[2] (1046:1046:1046) (1206:1206:1206)) + (PORT d[3] (2118:2118:2118) (2399:2399:2399)) + (PORT d[4] (1509:1509:1509) (1776:1776:1776)) + (PORT d[5] (2340:2340:2340) (2670:2670:2670)) + (PORT d[6] (1547:1547:1547) (1757:1757:1757)) + (PORT d[7] (1139:1139:1139) (1288:1288:1288)) + (PORT d[8] (1138:1138:1138) (1289:1289:1289)) + (PORT d[9] (1415:1415:1415) (1616:1616:1616)) + (PORT d[10] (1512:1512:1512) (1723:1723:1723)) + (PORT d[11] (1592:1592:1592) (1869:1869:1869)) + (PORT d[12] (2685:2685:2685) (3043:3043:3043)) + (PORT clk (1089:1089:1089) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (857:857:857) (914:914:914)) + (PORT clk (1089:1089:1089) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (PORT d[0] (1808:1808:1808) (1970:1970:1970)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1046:1046:1046) (1066:1066:1066)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1205:1205:1205) (1342:1342:1342)) + (PORT clk (1051:1051:1051) (1069:1069:1069)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2531:2531:2531) (2860:2860:2860)) + (PORT d[1] (2492:2492:2492) (2813:2813:2813)) + (PORT d[2] (2475:2475:2475) (2783:2783:2783)) + (PORT d[3] (2451:2451:2451) (2772:2772:2772)) + (PORT d[4] (2449:2449:2449) (2806:2806:2806)) + (PORT d[5] (2451:2451:2451) (2771:2771:2771)) + (PORT d[6] (2479:2479:2479) (2782:2782:2782)) + (PORT d[7] (2447:2447:2447) (2787:2787:2787)) + (PORT d[8] (2504:2504:2504) (2820:2820:2820)) + (PORT d[9] (2535:2535:2535) (2871:2871:2871)) + (PORT d[10] (2420:2420:2420) (2729:2729:2729)) + (PORT d[11] (2509:2509:2509) (2845:2845:2845)) + (PORT d[12] (2348:2348:2348) (2648:2648:2648)) + (PORT clk (1048:1048:1048) (1068:1068:1068)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1051:1051:1051) (1069:1069:1069)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1070:1070:1070)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1070:1070:1070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1070:1070:1070)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1070:1070:1070)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1411:1411:1411) (1643:1643:1643)) + (PORT d[1] (1391:1391:1391) (1581:1581:1581)) + (PORT d[2] (1332:1332:1332) (1552:1552:1552)) + (PORT d[3] (1272:1272:1272) (1464:1464:1464)) + (PORT d[4] (1165:1165:1165) (1361:1361:1361)) + (PORT d[5] (1406:1406:1406) (1606:1606:1606)) + (PORT d[6] (1424:1424:1424) (1638:1638:1638)) + (PORT d[7] (1799:1799:1799) (2059:2059:2059)) + (PORT d[8] (1604:1604:1604) (1846:1846:1846)) + (PORT d[9] (1413:1413:1413) (1632:1632:1632)) + (PORT d[10] (1880:1880:1880) (2160:2160:2160)) + (PORT d[11] (1187:1187:1187) (1372:1372:1372)) + (PORT d[12] (1360:1360:1360) (1566:1566:1566)) + (PORT clk (1099:1099:1099) (1117:1117:1117)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1117:1117:1117)) + (PORT d[0] (1510:1510:1510) (1695:1695:1695)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1081:1081:1081) (1098:1098:1098)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (621:621:621) (630:630:630)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (622:622:622) (631:631:631)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (622:622:622) (631:631:631)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (622:622:622) (631:631:631)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~123) + (DELAY + (ABSOLUTE + (PORT dataa (1492:1492:1492) (1751:1751:1751)) + (PORT datab (1391:1391:1391) (1611:1611:1611)) + (PORT datac (748:748:748) (848:848:848)) + (PORT datad (931:931:931) (1053:1053:1053)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (182:182:182) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (809:809:809)) + (PORT datab (415:415:415) (507:507:507)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (1100:1100:1100) (1265:1265:1265)) + (PORT datab (104:104:104) (134:134:134)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (181:181:181) (175:175:175)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~108) + (DELAY + (ABSOLUTE + (PORT dataa (852:852:852) (976:976:976)) + (PORT datab (117:117:117) (146:146:146)) + (PORT datad (104:104:104) (122:122:122)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~109) + (DELAY + (ABSOLUTE + (PORT dataa (1554:1554:1554) (1786:1786:1786)) + (PORT datab (518:518:518) (620:620:620)) + (PORT datac (103:103:103) (125:125:125)) + (PORT datad (826:826:826) (943:943:943)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (170:170:170)) + (PORT datab (479:479:479) (545:545:545)) + (PORT datac (337:337:337) (396:396:396)) + (PORT datad (622:622:622) (712:712:712)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (432:432:432) (460:460:460)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (217:217:217) (259:259:259)) + (PORT datac (191:191:191) (242:242:242)) + (PORT datad (199:199:199) (238:238:238)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (700:700:700) (802:802:802)) + (PORT datab (188:188:188) (226:226:226)) + (PORT datac (470:470:470) (557:557:557)) + (PORT datad (301:301:301) (343:343:343)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (917:917:917) (902:902:902)) + (PORT ena (1057:1057:1057) (1164:1164:1164)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1261:1261:1261) (1448:1448:1448)) + (PORT datac (887:887:887) (1059:1059:1059)) + (PORT datad (951:951:951) (1085:1085:1085)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (465:465:465) (543:543:543)) + (PORT datab (1055:1055:1055) (1214:1214:1214)) + (PORT datac (616:616:616) (711:711:711)) + (PORT datad (340:340:340) (398:398:398)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (406:406:406)) + (PORT datab (105:105:105) (136:136:136)) + (PORT datac (633:633:633) (736:736:736)) + (PORT datad (455:455:455) (534:534:534)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (262:262:262)) + (PORT datab (322:322:322) (370:370:370)) + (PORT datad (622:622:622) (712:712:712)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (837:837:837) (945:945:945)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1371:1371:1371) (1627:1627:1627)) + (PORT d[1] (1470:1470:1470) (1662:1662:1662)) + (PORT d[2] (897:897:897) (1029:1029:1029)) + (PORT d[3] (721:721:721) (835:835:835)) + (PORT d[4] (1130:1130:1130) (1291:1291:1291)) + (PORT d[5] (719:719:719) (830:830:830)) + (PORT d[6] (952:952:952) (1082:1082:1082)) + (PORT d[7] (1353:1353:1353) (1554:1554:1554)) + (PORT d[8] (1388:1388:1388) (1636:1636:1636)) + (PORT d[9] (597:597:597) (688:688:688)) + (PORT d[10] (988:988:988) (1132:1132:1132)) + (PORT d[11] (820:820:820) (939:939:939)) + (PORT d[12] (572:572:572) (661:661:661)) (PORT clk (1088:1088:1088) (1105:1105:1105)) ) ) @@ -40495,27 +39325,70 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) (DELAY (ABSOLUTE + (PORT d[0] (1008:1008:1008) (1096:1096:1096)) (PORT clk (1088:1088:1088) (1105:1105:1105)) - (PORT d[0] (2202:2202:2202) (1954:1954:1954)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (PORT d[0] (1161:1161:1161) (1245:1245:1245)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1070:1070:1070) (1086:1086:1086)) @@ -40529,7 +39402,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (610:610:610) (618:618:618)) @@ -40538,7 +39411,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) (DELAY (ABSOLUTE (PORT clk (611:611:611) (619:619:619)) @@ -40547,7 +39420,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (611:611:611) (619:619:619)) @@ -40557,7 +39430,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (611:611:611) (619:619:619)) @@ -40566,30 +39439,473 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~53) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (668:668:668) (763:763:763)) - (PORT datab (588:588:588) (669:669:669)) - (PORT datac (96:96:96) (121:121:121)) - (PORT datad (788:788:788) (884:884:884)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT d[0] (824:824:824) (928:928:928)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1351:1351:1351) (1598:1598:1598)) + (PORT d[1] (1140:1140:1140) (1291:1291:1291)) + (PORT d[2] (1063:1063:1063) (1222:1222:1222)) + (PORT d[3] (1259:1259:1259) (1438:1438:1438)) + (PORT d[4] (1143:1143:1143) (1304:1304:1304)) + (PORT d[5] (913:913:913) (1051:1051:1051)) + (PORT d[6] (971:971:971) (1102:1102:1102)) + (PORT d[7] (1298:1298:1298) (1482:1482:1482)) + (PORT d[8] (1407:1407:1407) (1655:1655:1655)) + (PORT d[9] (674:674:674) (764:764:764)) + (PORT d[10] (925:925:925) (1050:1050:1050)) + (PORT d[11] (668:668:668) (767:767:767)) + (PORT d[12] (604:604:604) (700:700:700)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (878:878:878) (949:949:949)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (PORT d[0] (1105:1105:1105) (1172:1172:1172)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (506:506:506) (567:567:567)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1711:1711:1711) (1997:1997:1997)) + (PORT d[1] (2087:2087:2087) (2382:2382:2382)) + (PORT d[2] (1116:1116:1116) (1274:1274:1274)) + (PORT d[3] (2313:2313:2313) (2621:2621:2621)) + (PORT d[4] (1841:1841:1841) (2153:2153:2153)) + (PORT d[5] (2688:2688:2688) (3070:3070:3070)) + (PORT d[6] (1269:1269:1269) (1440:1440:1440)) + (PORT d[7] (949:949:949) (1071:1071:1071)) + (PORT d[8] (1789:1789:1789) (2077:2077:2077)) + (PORT d[9] (1048:1048:1048) (1193:1193:1193)) + (PORT d[10] (1152:1152:1152) (1305:1305:1305)) + (PORT d[11] (1771:1771:1771) (2069:2069:2069)) + (PORT d[12] (2703:2703:2703) (3061:3061:3061)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1292:1292:1292) (1403:1403:1403)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT d[0] (1413:1413:1413) (1518:1518:1518)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (653:653:653) (753:753:753)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1515:1515:1515) (1766:1766:1766)) + (PORT d[1] (2121:2121:2121) (2428:2428:2428)) + (PORT d[2] (1203:1203:1203) (1382:1382:1382)) + (PORT d[3] (2480:2480:2480) (2814:2814:2814)) + (PORT d[4] (1872:1872:1872) (2192:2192:2192)) + (PORT d[5] (2696:2696:2696) (3075:3075:3075)) + (PORT d[6] (1469:1469:1469) (1677:1677:1677)) + (PORT d[7] (792:792:792) (896:896:896)) + (PORT d[8] (1791:1791:1791) (2085:2085:2085)) + (PORT d[9] (1044:1044:1044) (1190:1190:1190)) + (PORT d[10] (1129:1129:1129) (1278:1278:1278)) + (PORT d[11] (1957:1957:1957) (2290:2290:2290)) + (PORT d[12] (2706:2706:2706) (3060:3060:3060)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (862:862:862) (913:913:913)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (PORT d[0] (1379:1379:1379) (1480:1480:1480)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1078:1078:1078) (1094:1094:1094)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~54) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~2) (DELAY (ABSOLUTE - (PORT dataa (836:836:836) (986:986:986)) - (PORT datab (506:506:506) (601:601:601)) - (PORT datac (95:95:95) (119:119:119)) - (PORT datad (91:91:91) (108:108:108)) + (PORT dataa (449:449:449) (511:511:511)) + (PORT datab (634:634:634) (755:755:755)) + (PORT datac (648:648:648) (764:764:764)) + (PORT datad (605:605:605) (691:691:691)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (188:188:188) (177:177:177)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -40599,29 +39915,1657 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~106) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~3) (DELAY (ABSOLUTE - (PORT dataa (378:378:378) (465:465:465)) - (PORT datab (646:646:646) (769:769:769)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (181:181:181) (175:175:175)) - (IOPATH datab combout (166:166:166) (158:158:158)) + (PORT dataa (688:688:688) (794:794:794)) + (PORT datab (729:729:729) (840:840:840)) + (PORT datac (964:964:964) (1117:1117:1117)) + (PORT datad (161:161:161) (187:187:187)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~97) + (DELAY + (ABSOLUTE + (PORT dataa (1462:1462:1462) (1694:1694:1694)) + (PORT datab (1124:1124:1124) (1327:1327:1327)) + (PORT datac (1571:1571:1571) (1835:1835:1835)) + (PORT datad (1215:1215:1215) (1396:1396:1396)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (908:908:908) (1036:1036:1036)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1882:1882:1882) (2187:2187:2187)) + (PORT d[1] (1941:1941:1941) (2211:2211:2211)) + (PORT d[2] (1295:1295:1295) (1481:1481:1481)) + (PORT d[3] (2117:2117:2117) (2395:2395:2395)) + (PORT d[4] (1693:1693:1693) (1991:1991:1991)) + (PORT d[5] (2497:2497:2497) (2848:2848:2848)) + (PORT d[6] (1018:1018:1018) (1166:1166:1166)) + (PORT d[7] (1122:1122:1122) (1269:1269:1269)) + (PORT d[8] (1140:1140:1140) (1294:1294:1294)) + (PORT d[9] (1231:1231:1231) (1400:1400:1400)) + (PORT d[10] (1338:1338:1338) (1522:1522:1522)) + (PORT d[11] (1601:1601:1601) (1879:1879:1879)) + (PORT d[12] (2526:2526:2526) (2864:2864:2864)) + (PORT clk (1093:1093:1093) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (913:913:913) (980:980:980)) + (PORT clk (1093:1093:1093) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT d[0] (1612:1612:1612) (1743:1743:1743)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1069:1069:1069)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1200:1200:1200) (1335:1335:1335)) + (PORT clk (1055:1055:1055) (1072:1072:1072)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2524:2524:2524) (2849:2849:2849)) + (PORT d[1] (2509:2509:2509) (2833:2833:2833)) + (PORT d[2] (2510:2510:2510) (2827:2827:2827)) + (PORT d[3] (2459:2459:2459) (2780:2780:2780)) + (PORT d[4] (2474:2474:2474) (2834:2834:2834)) + (PORT d[5] (2437:2437:2437) (2753:2753:2753)) + (PORT d[6] (2452:2452:2452) (2755:2755:2755)) + (PORT d[7] (2473:2473:2473) (2784:2784:2784)) + (PORT d[8] (2542:2542:2542) (2871:2871:2871)) + (PORT d[9] (2539:2539:2539) (2878:2878:2878)) + (PORT d[10] (2570:2570:2570) (2897:2897:2897)) + (PORT d[11] (2498:2498:2498) (2845:2845:2845)) + (PORT d[12] (2367:2367:2367) (2670:2670:2670)) + (PORT clk (1052:1052:1052) (1071:1071:1071)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1072:1072:1072)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1056:1056:1056) (1073:1073:1073)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1056:1056:1056) (1073:1073:1073)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1056:1056:1056) (1073:1073:1073)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1056:1056:1056) (1073:1073:1073)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (976:976:976) (1157:1157:1157)) + (PORT d[1] (943:943:943) (1059:1059:1059)) + (PORT d[2] (1312:1312:1312) (1530:1530:1530)) + (PORT d[3] (1053:1053:1053) (1188:1188:1188)) + (PORT d[4] (1348:1348:1348) (1556:1556:1556)) + (PORT d[5] (1449:1449:1449) (1643:1643:1643)) + (PORT d[6] (1107:1107:1107) (1264:1264:1264)) + (PORT d[7] (1147:1147:1147) (1306:1306:1306)) + (PORT d[8] (1176:1176:1176) (1369:1369:1369)) + (PORT d[9] (1141:1141:1141) (1286:1286:1286)) + (PORT d[10] (945:945:945) (1063:1063:1063)) + (PORT d[11] (2540:2540:2540) (2952:2952:2952)) + (PORT d[12] (1217:1217:1217) (1369:1369:1369)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT d[0] (1170:1170:1170) (1282:1282:1282)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (877:877:877) (1008:1008:1008)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (928:928:928) (1096:1096:1096)) + (PORT d[1] (1731:1731:1731) (1979:1979:1979)) + (PORT d[2] (1482:1482:1482) (1700:1700:1700)) + (PORT d[3] (1930:1930:1930) (2182:2182:2182)) + (PORT d[4] (1501:1501:1501) (1768:1768:1768)) + (PORT d[5] (2167:2167:2167) (2473:2473:2473)) + (PORT d[6] (1282:1282:1282) (1459:1459:1459)) + (PORT d[7] (1930:1930:1930) (2196:2196:2196)) + (PORT d[8] (1666:1666:1666) (1902:1902:1902)) + (PORT d[9] (1436:1436:1436) (1645:1645:1645)) + (PORT d[10] (1509:1509:1509) (1717:1717:1717)) + (PORT d[11] (1417:1417:1417) (1665:1665:1665)) + (PORT d[12] (2715:2715:2715) (3081:3081:3081)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1641:1641:1641) (1793:1793:1793)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (PORT d[0] (1951:1951:1951) (1820:1820:1820)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1068:1068:1068)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1071:1071:1071) (1195:1195:1195)) + (PORT clk (1054:1054:1054) (1071:1071:1071)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2476:2476:2476) (2793:2793:2793)) + (PORT d[1] (2474:2474:2474) (2790:2790:2790)) + (PORT d[2] (2491:2491:2491) (2810:2810:2810)) + (PORT d[3] (2356:2356:2356) (2668:2668:2668)) + (PORT d[4] (2441:2441:2441) (2785:2785:2785)) + (PORT d[5] (2460:2460:2460) (2779:2779:2779)) + (PORT d[6] (2451:2451:2451) (2753:2753:2753)) + (PORT d[7] (2323:2323:2323) (2607:2607:2607)) + (PORT d[8] (2452:2452:2452) (2765:2765:2765)) + (PORT d[9] (2430:2430:2430) (2768:2768:2768)) + (PORT d[10] (2382:2382:2382) (2679:2679:2679)) + (PORT d[11] (2528:2528:2528) (2870:2870:2870)) + (PORT d[12] (2437:2437:2437) (2729:2729:2729)) + (PORT clk (1051:1051:1051) (1070:1070:1070)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1054:1054:1054) (1071:1071:1071)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1072:1072:1072)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1072:1072:1072)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1072:1072:1072)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1072:1072:1072)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1069:1069:1069)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (946:946:946) (1118:1118:1118)) + (PORT d[1] (1572:1572:1572) (1788:1788:1788)) + (PORT d[2] (1233:1233:1233) (1425:1425:1425)) + (PORT d[3] (1921:1921:1921) (2172:2172:2172)) + (PORT d[4] (1323:1323:1323) (1554:1554:1554)) + (PORT d[5] (2135:2135:2135) (2430:2430:2430)) + (PORT d[6] (1452:1452:1452) (1652:1652:1652)) + (PORT d[7] (1937:1937:1937) (2211:2211:2211)) + (PORT d[8] (1659:1659:1659) (1893:1893:1893)) + (PORT d[9] (1608:1608:1608) (1837:1837:1837)) + (PORT d[10] (1310:1310:1310) (1495:1495:1495)) + (PORT d[11] (1404:1404:1404) (1647:1647:1647)) + (PORT d[12] (2083:2083:2083) (2363:2363:2363)) + (PORT clk (1097:1097:1097) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (PORT d[0] (1679:1679:1679) (1502:1502:1502)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1079:1079:1079) (1096:1096:1096)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (628:628:628)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (620:620:620) (629:629:629)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (620:620:620) (629:629:629)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (620:620:620) (629:629:629)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (672:672:672) (780:780:780)) + (PORT datab (383:383:383) (454:454:454)) + (PORT datac (746:746:746) (855:855:855)) + (PORT datad (779:779:779) (902:902:902)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (169:169:169) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (438:438:438)) + (PORT datab (602:602:602) (688:688:688)) + (PORT datac (871:871:871) (1020:1020:1020)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~116) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (140:140:140)) + (PORT datab (116:116:116) (145:145:145)) + (PORT datac (544:544:544) (627:627:627)) + (PORT datad (336:336:336) (394:394:394)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~117) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (754:754:754)) + (PORT datab (1406:1406:1406) (1606:1606:1606)) + (PORT datac (664:664:664) (777:777:777)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (228:228:228)) + (PORT datab (230:230:230) (271:271:271)) + (PORT datac (653:653:653) (758:758:758)) + (PORT datad (623:623:623) (713:713:713)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (432:432:432) (460:460:460)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (218:218:218) (259:259:259)) + (PORT datac (307:307:307) (352:352:352)) + (PORT datad (132:132:132) (169:169:169)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (350:350:350) (379:379:379)) + (PORT clrn (917:917:917) (902:902:902)) + (PORT ena (1045:1045:1045) (1140:1140:1140)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~0) + (DELAY + (ABSOLUTE + (PORT datac (612:612:612) (706:706:706)) + (PORT datad (1095:1095:1095) (1255:1255:1255)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1433:1433:1433) (1651:1651:1651)) + (PORT datab (1169:1169:1169) (1377:1377:1377)) + (PORT datac (1417:1417:1417) (1670:1670:1670)) + (PORT datad (1038:1038:1038) (1195:1195:1195)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~2) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (1056:1056:1056)) + (PORT datab (289:289:289) (338:338:338)) + (PORT datac (458:458:458) (522:522:522)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (425:425:425)) + (PORT datab (494:494:494) (593:593:593)) + (PORT datac (802:802:802) (905:905:905)) + (PORT datad (645:645:645) (733:733:733)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1279:1279:1279) (1484:1484:1484)) + (PORT datab (1233:1233:1233) (1454:1454:1454)) + (PORT datac (671:671:671) (778:778:778)) + (PORT datad (476:476:476) (568:568:568)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instCB) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (890:890:890)) + (PORT ena (405:405:405) (422:422:422)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~0) + (DELAY + (ABSOLUTE + (PORT dataa (411:411:411) (509:509:509)) + (PORT datab (411:411:411) (504:504:504)) + (PORT datac (1059:1059:1059) (1237:1237:1237)) + (PORT datad (935:935:935) (1081:1081:1081)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (530:530:530) (621:621:621)) + (PORT datab (656:656:656) (766:766:766)) + (PORT datac (1054:1054:1054) (1210:1210:1210)) + (PORT datad (787:787:787) (902:902:902)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im1) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (499:499:499) (542:542:542)) + (PORT clrn (917:917:917) (902:902:902)) + (PORT ena (498:498:498) (538:538:538)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (396:396:396)) + (PORT datab (510:510:510) (600:600:600)) + (PORT datad (190:190:190) (237:237:237)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (483:483:483) (571:571:571)) + (PORT datab (552:552:552) (646:646:646)) + (PORT datac (319:319:319) (384:384:384)) + (PORT datad (92:92:92) (111:111:111)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (396:396:396)) + (PORT datab (110:110:110) (140:140:140)) + (PORT datac (635:635:635) (739:739:739)) + (PORT datad (451:451:451) (530:530:530)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (1000:1000:1000)) + (PORT datab (695:695:695) (804:804:804)) + (PORT datac (640:640:640) (731:731:731)) + (PORT datad (835:835:835) (954:954:954)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (404:404:404)) + (PORT datab (789:789:789) (910:910:910)) + (PORT datac (265:265:265) (302:302:302)) + (PORT datad (533:533:533) (621:621:621)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) + (DELAY + (ABSOLUTE + (PORT datac (497:497:497) (580:580:580)) + (PORT datad (334:334:334) (393:393:393)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (142:142:142)) + (PORT datab (194:194:194) (234:234:234)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (275:275:275) (315:315:315)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (512:512:512) (621:621:621)) + (PORT datab (512:512:512) (615:615:615)) + (PORT datac (138:138:138) (183:183:183)) + (PORT datad (145:145:145) (190:190:190)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~1) + (DELAY + (ABSOLUTE + (PORT datac (400:400:400) (477:477:477)) + (PORT datad (550:550:550) (657:657:657)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (253:253:253)) + (PORT datab (173:173:173) (211:211:211)) + (PORT datac (408:408:408) (499:499:499)) + (PORT datad (312:312:312) (361:361:361)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (420:420:420) (508:508:508)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (895:895:895) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (887:887:887) (891:891:891)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (169:169:169) (235:235:235)) + (PORT datab (357:357:357) (430:430:430)) + (PORT datac (489:489:489) (580:580:580)) + (PORT datad (519:519:519) (620:620:620)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (509:509:509)) + (PORT datab (419:419:419) (501:501:501)) + (PORT datac (383:383:383) (465:465:465)) + (PORT datad (523:523:523) (617:617:617)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~85) + (DELAY + (ABSOLUTE + (PORT datab (572:572:572) (684:684:684)) + (PORT datad (98:98:98) (118:118:118)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (413:413:413)) + (PORT datab (119:119:119) (153:153:153)) + (PORT datac (376:376:376) (444:444:444)) + (PORT datad (270:270:270) (309:309:309)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (177:177:177) (215:215:215)) + (PORT datab (423:423:423) (512:512:512)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (895:895:895) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (887:887:887) (891:891:891)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE D\[0\]\~57) (DELAY (ABSOLUTE - (PORT dataa (1112:1112:1112) (1282:1282:1282)) - (PORT datab (639:639:639) (743:743:743)) - (PORT datac (94:94:94) (118:118:118)) - (PORT datad (454:454:454) (532:532:532)) + (PORT dataa (130:130:130) (180:180:180)) + (PORT datab (522:522:522) (613:613:613)) + (PORT datac (432:432:432) (489:489:489)) + (PORT datad (120:120:120) (157:157:157)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (258:258:258) (330:330:330)) + (PORT datab (551:551:551) (658:658:658)) + (PORT datac (348:348:348) (410:410:410)) + (PORT datad (329:329:329) (401:401:401)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (258:258:258) (330:330:330)) + (PORT datac (415:415:415) (501:501:501)) + (PORT datad (208:208:208) (260:260:260)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (683:683:683)) + (PORT datac (488:488:488) (561:561:561)) + (PORT datad (390:390:390) (471:471:471)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datad (309:309:309) (355:355:355)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (902:902:902)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (883:883:883) (888:888:888)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (311:311:311) (364:364:364)) + (PORT datab (572:572:572) (684:684:684)) + (PORT datac (394:394:394) (470:470:470)) + (PORT datad (98:98:98) (118:118:118)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (146:146:146)) + (PORT datab (292:292:292) (338:338:338)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (893:893:893) (899:899:899)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (886:886:886) (890:890:890)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (125:125:125) (159:159:159)) + (PORT datab (119:119:119) (149:149:149)) + (PORT datac (507:507:507) (595:595:595)) + (PORT datad (334:334:334) (390:390:390)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (478:478:478)) + (PORT datab (562:562:562) (660:660:660)) + (PORT datac (535:535:535) (633:633:633)) + (PORT datad (311:311:311) (355:355:355)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (736:736:736) (862:862:862)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (891:891:891) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~68) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (412:412:412)) + (PORT datac (543:543:543) (643:643:643)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (400:400:400) (493:493:493)) + (PORT datab (531:531:531) (638:638:638)) + (PORT datac (410:410:410) (505:505:505)) + (PORT datad (493:493:493) (584:584:584)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~69) + (DELAY + (ABSOLUTE + (PORT dataa (260:260:260) (332:332:332)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (510:510:510) (616:616:616)) + (PORT datad (103:103:103) (126:126:126)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (476:476:476) (552:552:552)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (318:318:318) (374:374:374)) + (PORT datad (390:390:390) (474:474:474)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (224:224:224) (285:285:285)) + (PORT datac (413:413:413) (498:498:498)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (670:670:670)) + (PORT datab (316:316:316) (382:382:382)) + (PORT datac (545:545:545) (645:645:645)) + (PORT datad (321:321:321) (389:389:389)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~71) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (418:418:418)) + (PORT datab (406:406:406) (497:497:497)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (141:141:141) (184:184:184)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (404:404:404) (488:488:488)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (901:901:901)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (883:883:883) (887:887:887)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~2) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (940:940:940)) + (PORT datac (1294:1294:1294) (1527:1527:1527)) + (PORT datad (488:488:488) (570:570:570)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (478:478:478)) + (PORT datac (536:536:536) (634:634:634)) + (PORT datad (312:312:312) (356:356:356)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (738:738:738) (864:864:864)) + (PORT datab (562:562:562) (660:660:660)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (891:891:891) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (252:252:252)) + (PORT datab (391:391:391) (467:467:467)) + (PORT datac (488:488:488) (579:579:579)) + (PORT datad (105:105:105) (129:129:129)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (737:737:737) (863:863:863)) + (PORT datab (520:520:520) (605:605:605)) + (PORT datad (322:322:322) (360:360:360)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (891:891:891) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (153:153:153)) + (PORT datab (1621:1621:1621) (1900:1900:1900)) + (PORT datac (116:116:116) (157:157:157)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (182:182:182)) + (PORT datab (116:116:116) (145:145:145)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (90:90:90) (108:108:108)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -40634,12 +41578,1363 @@ (INSTANCE D\[0\]\~58) (DELAY (ABSOLUTE - (PORT dataa (1114:1114:1114) (1284:1284:1284)) - (PORT datab (341:341:341) (410:410:410)) + (PORT dataa (493:493:493) (569:569:569)) + (PORT datab (101:101:101) (130:130:130)) + (PORT datac (1372:1372:1372) (1621:1621:1621)) + (PORT datad (327:327:327) (383:383:383)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (679:679:679) (775:775:775)) + (PORT clk (1084:1084:1084) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1569:1569:1569) (1852:1852:1852)) + (PORT d[1] (1661:1661:1661) (1877:1877:1877)) + (PORT d[2] (572:572:572) (661:661:661)) + (PORT d[3] (547:547:547) (638:638:638)) + (PORT d[4] (1167:1167:1167) (1338:1338:1338)) + (PORT d[5] (539:539:539) (625:625:625)) + (PORT d[6] (956:956:956) (1085:1085:1085)) + (PORT d[7] (1543:1543:1543) (1768:1768:1768)) + (PORT d[8] (1410:1410:1410) (1661:1661:1661)) + (PORT d[9] (415:415:415) (485:485:485)) + (PORT d[10] (408:408:408) (481:481:481)) + (PORT d[11] (1641:1641:1641) (1916:1916:1916)) + (PORT d[12] (232:232:232) (273:273:273)) + (PORT clk (1082:1082:1082) (1100:1100:1100)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (850:850:850) (918:918:918)) + (PORT clk (1082:1082:1082) (1100:1100:1100)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1084:1084:1084) (1102:1102:1102)) + (PORT d[0] (794:794:794) (826:826:826)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1064:1064:1064) (1081:1081:1081)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (604:604:604) (613:613:613)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (520:520:520) (594:594:594)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1789:1789:1789) (2110:2110:2110)) + (PORT d[1] (922:922:922) (1066:1066:1066)) + (PORT d[2] (557:557:557) (647:647:647)) + (PORT d[3] (529:529:529) (616:616:616)) + (PORT d[4] (636:636:636) (733:733:733)) + (PORT d[5] (523:523:523) (605:605:605)) + (PORT d[6] (906:906:906) (1049:1049:1049)) + (PORT d[7] (533:533:533) (620:620:620)) + (PORT d[8] (725:725:725) (849:849:849)) + (PORT d[9] (441:441:441) (514:514:514)) + (PORT d[10] (414:414:414) (481:481:481)) + (PORT d[11] (1438:1438:1438) (1677:1677:1677)) + (PORT d[12] (604:604:604) (705:705:705)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (505:505:505) (528:528:528)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (PORT d[0] (1133:1133:1133) (1212:1212:1212)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1088:1088:1088)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (621:621:621)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (621:621:621)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (556:556:556) (638:638:638)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1763:1763:1763) (2080:2080:2080)) + (PORT d[1] (1091:1091:1091) (1257:1257:1257)) + (PORT d[2] (720:720:720) (825:825:825)) + (PORT d[3] (711:711:711) (823:823:823)) + (PORT d[4] (825:825:825) (948:948:948)) + (PORT d[5] (363:363:363) (421:421:421)) + (PORT d[6] (1069:1069:1069) (1235:1235:1235)) + (PORT d[7] (1705:1705:1705) (1949:1949:1949)) + (PORT d[8] (720:720:720) (839:839:839)) + (PORT d[9] (566:566:566) (657:657:657)) + (PORT d[10] (405:405:405) (472:472:472)) + (PORT d[11] (1460:1460:1460) (1706:1706:1706)) + (PORT d[12] (438:438:438) (516:516:516)) + (PORT clk (1088:1088:1088) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (508:508:508) (531:531:531)) + (PORT clk (1088:1088:1088) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (PORT d[0] (991:991:991) (1055:1055:1055)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1070:1070:1070) (1086:1086:1086)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (697:697:697)) + (PORT datab (519:519:519) (617:617:617)) + (PORT datac (493:493:493) (556:556:556)) + (PORT datad (527:527:527) (600:600:600)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (789:789:789) (888:888:888)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1438:1438:1438) (1666:1666:1666)) + (PORT d[1] (1430:1430:1430) (1615:1615:1615)) + (PORT d[2] (1502:1502:1502) (1743:1743:1743)) + (PORT d[3] (2695:2695:2695) (3058:3058:3058)) + (PORT d[4] (1651:1651:1651) (1897:1897:1897)) + (PORT d[5] (1788:1788:1788) (2036:2036:2036)) + (PORT d[6] (813:813:813) (919:919:919)) + (PORT d[7] (781:781:781) (878:878:878)) + (PORT d[8] (1405:1405:1405) (1633:1633:1633)) + (PORT d[9] (939:939:939) (1059:1059:1059)) + (PORT d[10] (1457:1457:1457) (1645:1645:1645)) + (PORT d[11] (2158:2158:2158) (2516:2516:2516)) + (PORT d[12] (1423:1423:1423) (1606:1606:1606)) + (PORT clk (1088:1088:1088) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1107:1107:1107) (1194:1194:1194)) + (PORT clk (1088:1088:1088) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT d[0] (1065:1065:1065) (1125:1125:1125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1070:1070:1070) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (775:775:775)) + (PORT datab (865:865:865) (1022:1022:1022)) + (PORT datac (177:177:177) (214:214:214)) + (PORT datad (749:749:749) (848:848:848)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (870:870:870) (1008:1008:1008)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1432:1432:1432) (1667:1667:1667)) + (PORT d[1] (1238:1238:1238) (1414:1414:1414)) + (PORT d[2] (1398:1398:1398) (1616:1616:1616)) + (PORT d[3] (1224:1224:1224) (1399:1399:1399)) + (PORT d[4] (1159:1159:1159) (1354:1354:1354)) + (PORT d[5] (1331:1331:1331) (1523:1523:1523)) + (PORT d[6] (1337:1337:1337) (1536:1536:1536)) + (PORT d[7] (1984:1984:1984) (2268:2268:2268)) + (PORT d[8] (1616:1616:1616) (1855:1855:1855)) + (PORT d[9] (1220:1220:1220) (1409:1409:1409)) + (PORT d[10] (2067:2067:2067) (2374:2374:2374)) + (PORT d[11] (1226:1226:1226) (1423:1423:1423)) + (PORT d[12] (1176:1176:1176) (1359:1359:1359)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1108:1108:1108) (1198:1198:1198)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (PORT d[0] (1832:1832:1832) (2014:2014:2014)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1053:1053:1053) (1072:1072:1072)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1210:1210:1210) (1374:1374:1374)) + (PORT clk (1058:1058:1058) (1075:1075:1075)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2428:2428:2428) (2747:2747:2747)) + (PORT d[1] (2529:2529:2529) (2872:2872:2872)) + (PORT d[2] (2532:2532:2532) (2867:2867:2867)) + (PORT d[3] (2436:2436:2436) (2773:2773:2773)) + (PORT d[4] (2480:2480:2480) (2803:2803:2803)) + (PORT d[5] (2512:2512:2512) (2846:2846:2846)) + (PORT d[6] (2583:2583:2583) (2909:2909:2909)) + (PORT d[7] (2411:2411:2411) (2705:2705:2705)) + (PORT d[8] (2497:2497:2497) (2839:2839:2839)) + (PORT d[9] (2499:2499:2499) (2822:2822:2822)) + (PORT d[10] (2475:2475:2475) (2812:2812:2812)) + (PORT d[11] (2485:2485:2485) (2832:2832:2832)) + (PORT d[12] (2403:2403:2403) (2691:2691:2691)) + (PORT clk (1055:1055:1055) (1074:1074:1074)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1058:1058:1058) (1075:1075:1075)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1059:1059:1059) (1076:1076:1076)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1059:1059:1059) (1076:1076:1076)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1059:1059:1059) (1076:1076:1076)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1059:1059:1059) (1076:1076:1076)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1143:1143:1143) (1345:1345:1345)) + (PORT d[1] (1231:1231:1231) (1379:1379:1379)) + (PORT d[2] (1305:1305:1305) (1517:1517:1517)) + (PORT d[3] (963:963:963) (1098:1098:1098)) + (PORT d[4] (1296:1296:1296) (1502:1502:1502)) + (PORT d[5] (1585:1585:1585) (1801:1801:1801)) + (PORT d[6] (971:971:971) (1110:1110:1110)) + (PORT d[7] (1117:1117:1117) (1259:1259:1259)) + (PORT d[8] (1214:1214:1214) (1419:1419:1419)) + (PORT d[9] (1135:1135:1135) (1279:1279:1279)) + (PORT d[10] (1424:1424:1424) (1605:1605:1605)) + (PORT d[11] (2521:2521:2521) (2926:2926:2926)) + (PORT d[12] (1230:1230:1230) (1385:1385:1385)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (PORT d[0] (1193:1193:1193) (1312:1312:1312)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1076:1076:1076) (1092:1092:1092)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (624:624:624)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (499:499:499) (581:581:581)) + (PORT datab (434:434:434) (524:524:524)) + (PORT datac (672:672:672) (762:762:762)) + (PORT datad (937:937:937) (1068:1068:1068)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (824:824:824) (935:935:935)) + (PORT clk (1104:1104:1104) (1120:1120:1120)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1246:1246:1246) (1453:1453:1453)) + (PORT d[1] (1533:1533:1533) (1747:1747:1747)) + (PORT d[2] (1382:1382:1382) (1587:1587:1587)) + (PORT d[3] (1754:1754:1754) (1982:1982:1982)) + (PORT d[4] (1292:1292:1292) (1525:1525:1525)) + (PORT d[5] (1953:1953:1953) (2224:2224:2224)) + (PORT d[6] (1460:1460:1460) (1664:1664:1664)) + (PORT d[7] (1682:1682:1682) (1928:1928:1928)) + (PORT d[8] (1491:1491:1491) (1707:1707:1707)) + (PORT d[9] (1734:1734:1734) (1973:1973:1973)) + (PORT d[10] (1297:1297:1297) (1480:1480:1480)) + (PORT d[11] (1261:1261:1261) (1482:1482:1482)) + (PORT d[12] (2080:2080:2080) (2363:2363:2363)) + (PORT clk (1102:1102:1102) (1118:1118:1118)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1479:1479:1479) (1610:1610:1610)) + (PORT clk (1102:1102:1102) (1118:1118:1118)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1104:1104:1104) (1120:1120:1120)) + (PORT d[0] (2172:2172:2172) (2012:2012:2012)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1121:1121:1121)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1059:1059:1059) (1077:1077:1077)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1208:1208:1208) (1346:1346:1346)) + (PORT clk (1064:1064:1064) (1080:1080:1080)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2496:2496:2496) (2811:2811:2811)) + (PORT d[1] (2480:2480:2480) (2802:2802:2802)) + (PORT d[2] (2465:2465:2465) (2778:2778:2778)) + (PORT d[3] (2451:2451:2451) (2772:2772:2772)) + (PORT d[4] (2409:2409:2409) (2745:2745:2745)) + (PORT d[5] (2500:2500:2500) (2815:2815:2815)) + (PORT d[6] (2408:2408:2408) (2701:2701:2701)) + (PORT d[7] (2474:2474:2474) (2784:2784:2784)) + (PORT d[8] (2466:2466:2466) (2800:2800:2800)) + (PORT d[9] (2430:2430:2430) (2745:2745:2745)) + (PORT d[10] (2378:2378:2378) (2673:2673:2673)) + (PORT d[11] (2490:2490:2490) (2812:2812:2812)) + (PORT d[12] (2371:2371:2371) (2676:2676:2676)) + (PORT clk (1061:1061:1061) (1079:1079:1079)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1064:1064:1064) (1080:1080:1080)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1065:1065:1065) (1081:1081:1081)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1065:1065:1065) (1081:1081:1081)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1065:1065:1065) (1081:1081:1081)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1065:1065:1065) (1081:1081:1081)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1060:1060:1060) (1078:1078:1078)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1318:1318:1318) (1537:1537:1537)) + (PORT d[1] (608:608:608) (684:684:684)) + (PORT d[2] (1510:1510:1510) (1728:1728:1728)) + (PORT d[3] (2694:2694:2694) (3050:3050:3050)) + (PORT d[4] (563:563:563) (652:652:652)) + (PORT d[5] (1213:1213:1213) (1370:1370:1370)) + (PORT d[6] (1644:1644:1644) (1873:1873:1873)) + (PORT d[7] (776:776:776) (875:875:875)) + (PORT d[8] (1565:1565:1565) (1818:1818:1818)) + (PORT d[9] (829:829:829) (936:936:936)) + (PORT d[10] (1144:1144:1144) (1293:1293:1293)) + (PORT d[11] (2167:2167:2167) (2529:2529:2529)) + (PORT d[12] (956:956:956) (1078:1078:1078)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (PORT d[0] (817:817:817) (748:748:748)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1074:1074:1074) (1090:1090:1090)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (614:614:614) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (623:623:623)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (623:623:623)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (623:623:623)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (734:734:734)) + (PORT datab (518:518:518) (592:592:592)) + (PORT datac (556:556:556) (650:650:650)) + (PORT datad (97:97:97) (117:117:117)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (181:181:181)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (434:434:434) (524:524:524)) + (PORT datac (1049:1049:1049) (1206:1206:1206)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~120) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (1088:1088:1088)) + (PORT datab (1718:1718:1718) (2022:2022:2022)) (PORT datac (90:90:90) (111:111:111)) - (PORT datad (884:884:884) (1007:1007:1007)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (181:181:181) (175:175:175)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (511:511:511) (590:590:590)) + (PORT datab (489:489:489) (566:566:566)) + (PORT datac (905:905:905) (1026:1026:1026)) + (PORT datad (95:95:95) (113:113:113)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (664:664:664) (788:788:788)) + (PORT datab (1681:1681:1681) (1921:1921:1921)) + (PORT datac (102:102:102) (123:123:123)) + (PORT datad (792:792:792) (907:907:907)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -40650,10 +42945,10 @@ (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) (DELAY (ABSOLUTE - (PORT dataa (545:545:545) (648:648:648)) - (PORT datab (512:512:512) (593:593:593)) - (PORT datac (135:135:135) (172:172:172)) - (PORT datad (877:877:877) (993:993:993)) + (PORT dataa (648:648:648) (741:741:741)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (192:192:192) (229:229:229)) + (PORT datad (619:619:619) (708:708:708)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -40682,10 +42977,10 @@ (INSTANCE z80_\|bus_control_\|db\[0\]\~16) (DELAY (ABSOLUTE - (PORT datab (206:206:206) (246:246:246)) - (PORT datac (211:211:211) (262:262:262)) - (PORT datad (359:359:359) (422:422:422)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datab (134:134:134) (168:168:168)) + (PORT datac (119:119:119) (148:148:148)) + (PORT datad (1184:1184:1184) (1351:1351:1351)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -40696,11 +42991,11 @@ (INSTANCE z80_\|bus_control_\|db\[0\]\~17) (DELAY (ABSOLUTE - (PORT dataa (539:539:539) (622:622:622)) - (PORT datab (735:735:735) (841:841:841)) - (PORT datac (505:505:505) (580:580:580)) - (PORT datad (489:489:489) (557:557:557)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (796:796:796) (905:905:905)) + (PORT datac (601:601:601) (693:693:693)) + (PORT datad (116:116:116) (139:139:139)) + (IOPATH dataa combout (165:165:165) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -40712,10 +43007,10 @@ (INSTANCE z80_\|ir_\|opcode\[0\]) (DELAY (ABSOLUTE - (PORT clk (904:904:904) (909:909:909)) - (PORT asdata (833:833:833) (925:925:925)) - (PORT clrn (915:915:915) (899:899:899)) - (PORT ena (784:784:784) (855:855:855)) + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (369:369:369) (404:404:404)) + (PORT clrn (917:917:917) (902:902:902)) + (PORT ena (1045:1045:1045) (1140:1140:1140)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -40727,13 +43022,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal63\~0) + (INSTANCE z80_\|pla_decode_\|Equal3\~2) (DELAY (ABSOLUTE - (PORT dataa (1134:1134:1134) (1318:1318:1318)) - (PORT datab (852:852:852) (1008:1008:1008)) - (PORT datac (123:123:123) (152:152:152)) - (PORT datad (617:617:617) (712:712:712)) + (PORT dataa (947:947:947) (1100:1100:1100)) + (PORT datab (745:745:745) (856:856:856)) + (PORT datac (111:111:111) (137:137:137)) + (PORT datad (730:730:730) (821:821:821)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -40743,396 +43038,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) + (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) (DELAY (ABSOLUTE - (PORT dataa (849:849:849) (998:998:998)) - (PORT datab (837:837:837) (983:983:983)) - (PORT datac (1033:1033:1033) (1196:1196:1196)) - (PORT datad (211:211:211) (250:250:250)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (282:282:282)) - (PORT datab (380:380:380) (452:452:452)) - (PORT datac (820:820:820) (948:948:948)) - (PORT datad (730:730:730) (867:867:867)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (443:443:443)) - (PORT datac (629:629:629) (724:724:724)) - (PORT datad (495:495:495) (576:576:576)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (366:366:366) (433:433:433)) - (PORT datac (477:477:477) (551:551:551)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (274:274:274) (322:322:322)) - (PORT datab (495:495:495) (569:569:569)) - (PORT datac (306:306:306) (352:352:352)) - (PORT datad (626:626:626) (722:722:722)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (406:406:406)) - (PORT datab (513:513:513) (599:599:599)) - (PORT datac (353:353:353) (420:420:420)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (494:494:494) (571:571:571)) - (PORT datab (132:132:132) (167:167:167)) - (PORT datac (344:344:344) (405:405:405)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~119) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (518:518:518)) - (PORT datab (404:404:404) (495:495:495)) - (PORT datac (636:636:636) (744:744:744)) - (PORT datad (495:495:495) (588:588:588)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~120) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (432:432:432)) - (PORT datab (175:175:175) (210:210:210)) - (PORT datac (403:403:403) (491:491:491)) - (PORT datad (406:406:406) (506:506:506)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~95) - (DELAY - (ABSOLUTE - (PORT dataa (445:445:445) (545:545:545)) - (PORT datac (395:395:395) (479:479:479)) - (PORT datad (640:640:640) (745:745:745)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~121) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datad (94:94:94) (114:114:114)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~117) - (DELAY - (ABSOLUTE - (PORT dataa (235:235:235) (305:305:305)) - (PORT datab (349:349:349) (423:423:423)) - (PORT datad (400:400:400) (477:477:477)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~136) - (DELAY - (ABSOLUTE - (PORT dataa (288:288:288) (338:338:338)) - (PORT datab (237:237:237) (296:296:296)) - (PORT datad (346:346:346) (420:420:420)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~130) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (450:450:450)) - (PORT datab (358:358:358) (422:422:422)) - (PORT datad (440:440:440) (514:514:514)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~118) - (DELAY - (ABSOLUTE - (PORT dataa (448:448:448) (548:548:548)) - (PORT datab (340:340:340) (399:399:399)) - (PORT datad (335:335:335) (383:383:383)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (469:469:469) (542:542:542)) - (PORT datab (466:466:466) (538:538:538)) - (PORT datac (329:329:329) (399:399:399)) - (PORT datad (347:347:347) (419:419:419)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~126) - (DELAY - (ABSOLUTE - (PORT dataa (446:446:446) (557:557:557)) - (PORT datab (380:380:380) (445:445:445)) - (PORT datac (517:517:517) (616:616:616)) - (PORT datad (775:775:775) (924:924:924)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~128) - (DELAY - (ABSOLUTE - (PORT dataa (529:529:529) (634:634:634)) - (PORT datab (435:435:435) (537:537:537)) - (PORT datac (493:493:493) (594:594:594)) - (PORT datad (427:427:427) (533:533:533)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~129) - (DELAY - (ABSOLUTE - (PORT dataa (180:180:180) (220:220:220)) - (PORT datab (103:103:103) (133:133:133)) - (PORT datad (493:493:493) (582:582:582)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~127) - (DELAY - (ABSOLUTE - (PORT dataa (321:321:321) (383:383:383)) - (PORT datab (519:519:519) (623:623:623)) - (PORT datad (295:295:295) (337:337:337)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (1047:1047:1047)) - (PORT datac (414:414:414) (511:511:511)) - (PORT datad (387:387:387) (476:476:476)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (441:441:441)) - (PORT datab (669:669:669) (792:792:792)) - (PORT datac (493:493:493) (597:597:597)) - (PORT datad (172:172:172) (201:201:201)) + (PORT dataa (1288:1288:1288) (1505:1505:1505)) + (PORT datab (1235:1235:1235) (1455:1455:1455)) + (PORT datac (1253:1253:1253) (1457:1457:1457)) + (PORT datad (196:196:196) (232:232:232)) (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -41140,48 +43052,311 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~125) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (142:142:142)) - (PORT datab (521:521:521) (625:625:625)) - (PORT datad (179:179:179) (219:219:219)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) + (INSTANCE z80_\|decode_state_\|DFFE_instIY1) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) + (PORT clk (901:901:901) (906:906:906)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) + (PORT clrn (906:906:906) (890:890:890)) + (PORT ena (420:420:420) (448:448:448)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~79) + (INSTANCE z80_\|decode_state_\|use_ixiy) (DELAY (ABSOLUTE - (PORT dataa (753:753:753) (856:856:856)) - (PORT datab (674:674:674) (793:793:793)) - (PORT datac (118:118:118) (160:160:160)) - (PORT datad (119:119:119) (156:156:156)) - (IOPATH dataa combout (165:165:165) (163:163:163)) + (PORT datac (554:554:554) (653:653:653)) + (PORT datad (833:833:833) (966:966:966)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~12) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (565:565:565)) + (PORT datab (945:945:945) (1070:1070:1070)) + (PORT datac (592:592:592) (698:698:698)) + (PORT datad (464:464:464) (546:546:546)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~13) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (405:405:405)) + (PORT datab (671:671:671) (784:784:784)) + (PORT datad (483:483:483) (555:555:555)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (721:721:721)) + (PORT datab (337:337:337) (393:393:393)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (325:325:325) (376:376:376)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (419:419:419)) + (PORT datab (374:374:374) (453:453:453)) + (PORT datac (831:831:831) (962:962:962)) + (PORT datad (320:320:320) (380:380:380)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~15) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (757:757:757)) + (PORT datab (102:102:102) (129:129:129)) + (PORT datac (334:334:334) (392:392:392)) + (PORT datad (435:435:435) (515:515:515)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (805:805:805)) + (PORT datab (200:200:200) (242:242:242)) + (PORT datac (517:517:517) (615:615:615)) + (PORT datad (763:763:763) (912:912:912)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (787:787:787)) + (PORT datab (846:846:846) (993:993:993)) + (PORT datac (309:309:309) (356:356:356)) + (PORT datad (468:468:468) (540:540:540)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (903:903:903)) + (PORT datab (1243:1243:1243) (1465:1465:1465)) + (PORT datac (889:889:889) (1019:1019:1019)) + (PORT datad (389:389:389) (462:462:462)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (490:490:490)) + (PORT datab (346:346:346) (406:406:406)) + (PORT datac (886:886:886) (1007:1007:1007)) + (PORT datad (844:844:844) (973:973:973)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (739:739:739)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (96:96:96) (115:115:115)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (113:113:113) (147:147:147)) + (PORT datab (340:340:340) (404:404:404)) + (PORT datac (94:94:94) (118:118:118)) + (PORT datad (178:178:178) (206:206:206)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~9) + (DELAY + (ABSOLUTE + (PORT datab (486:486:486) (567:567:567)) + (PORT datac (301:301:301) (347:347:347)) + (PORT datad (424:424:424) (492:492:492)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (313:313:313) (371:371:371)) + (PORT datab (316:316:316) (370:370:370)) + (PORT datac (499:499:499) (581:581:581)) + (PORT datad (426:426:426) (494:494:494)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (129:129:129) (166:166:166)) + (PORT datab (485:485:485) (566:566:566)) + (PORT datac (351:351:351) (416:416:416)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (719:719:719)) + (PORT datab (645:645:645) (745:745:745)) + (PORT datac (706:706:706) (809:809:809)) + (PORT datad (745:745:745) (865:865:865)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (406:406:406)) + (PORT datab (116:116:116) (145:145:145)) + (PORT datac (459:459:459) (532:532:532)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (392:392:392)) + (PORT datac (345:345:345) (407:407:407)) + (PORT datad (459:459:459) (529:529:529)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (477:477:477) (560:560:560)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -41189,29 +43364,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~122) + (INSTANCE z80_\|bus_control_\|db\[1\]\~10) (DELAY (ABSOLUTE - (PORT dataa (237:237:237) (307:307:307)) - (PORT datab (348:348:348) (422:422:422)) - (PORT datad (401:401:401) (478:478:478)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (167:167:167) (158:158:158)) + (PORT dataa (476:476:476) (553:553:553)) + (PORT datab (636:636:636) (736:736:736)) + (PORT datad (197:197:197) (235:235:235)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~123) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) (DELAY (ABSOLUTE - (PORT dataa (300:300:300) (351:351:351)) - (PORT datab (402:402:402) (496:496:496)) - (PORT datac (860:860:860) (1023:1023:1023)) - (PORT datad (317:317:317) (366:366:366)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT dataa (257:257:257) (328:328:328)) + (PORT datac (411:411:411) (497:497:497)) + (PORT datad (203:203:203) (255:255:255)) + (IOPATH dataa combout (165:165:165) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -41219,14 +43392,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~124) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~41) (DELAY (ABSOLUTE - (PORT dataa (357:357:357) (422:422:422)) - (PORT datab (416:416:416) (509:509:509)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (362:362:362) (434:434:434)) + (PORT datac (537:537:537) (637:637:637)) + (PORT datad (325:325:325) (397:397:397)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (139:139:139)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datad (311:311:311) (356:356:356)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -41234,12 +43421,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) + (PORT clk (897:897:897) (902:902:902)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) + (PORT clrn (883:883:883) (888:888:888)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -41250,12 +43437,59 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~3) + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~30) (DELAY (ABSOLUTE - (PORT datab (848:848:848) (999:999:999)) - (PORT datac (477:477:477) (571:571:571)) - (PORT datad (119:119:119) (156:156:156)) + (PORT dataa (109:109:109) (142:142:142)) + (PORT datab (422:422:422) (511:511:511)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (895:895:895) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (887:887:887) (891:891:891)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~0) + (DELAY + (ABSOLUTE + (PORT datab (991:991:991) (1165:1165:1165)) + (PORT datac (1285:1285:1285) (1511:1511:1511)) + (PORT datad (500:500:500) (582:582:582)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (174:174:174) (242:242:242)) + (PORT datab (361:361:361) (435:435:435)) + (PORT datac (494:494:494) (586:586:586)) + (PORT datad (521:521:521) (622:622:622)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -41264,14 +43498,123 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~80) + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) (DELAY (ABSOLUTE - (PORT dataa (198:198:198) (256:256:256)) - (PORT datab (339:339:339) (392:392:392)) - (PORT datac (744:744:744) (860:860:860)) - (PORT datad (90:90:90) (107:107:107)) + (PORT dataa (381:381:381) (460:460:460)) + (PORT datab (440:440:440) (536:536:536)) + (PORT datac (562:562:562) (667:667:667)) + (PORT datad (414:414:414) (504:504:504)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~0) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (463:463:463)) + (PORT datab (438:438:438) (533:533:533)) + (PORT datac (558:558:558) (663:663:663)) + (PORT datad (411:411:411) (500:500:500)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) + (DELAY + (ABSOLUTE + (PORT dataa (122:122:122) (155:155:155)) + (PORT datab (577:577:577) (690:690:690)) + (PORT datac (700:700:700) (818:818:818)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) + (DELAY + (ABSOLUTE + (PORT dataa (394:394:394) (475:475:475)) + (PORT datab (718:718:718) (842:842:842)) + (PORT datac (90:90:90) (110:110:110)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (484:484:484)) + (PORT datab (312:312:312) (357:357:357)) + (PORT datad (91:91:91) (107:107:107)) (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (895:895:895) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (888:888:888) (892:892:892)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (509:509:509)) + (PORT datab (398:398:398) (486:486:486)) + (PORT datac (401:401:401) (479:479:479)) + (PORT datad (550:550:550) (657:657:657)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (540:540:540) (644:644:644)) + (PORT datac (90:90:90) (113:113:113)) + (PORT datad (274:274:274) (315:315:315)) (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -41280,13 +43623,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~111) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~31) (DELAY (ABSOLUTE - (PORT dataa (448:448:448) (548:548:548)) - (PORT datac (389:389:389) (472:472:472)) - (PORT datad (633:633:633) (736:736:736)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datab (569:569:569) (682:682:682)) + (PORT datac (242:242:242) (305:305:305)) + (PORT datad (496:496:496) (583:583:583)) + (IOPATH datab combout (166:166:166) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -41294,30 +43637,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~97) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~35) (DELAY (ABSOLUTE - (PORT dataa (653:653:653) (772:772:772)) - (PORT datab (407:407:407) (498:498:498)) - (PORT datac (347:347:347) (413:413:413)) - (PORT datad (491:491:491) (584:584:584)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~116) - (DELAY - (ABSOLUTE - (PORT dataa (195:195:195) (235:235:235)) - (PORT datab (116:116:116) (145:145:145)) - (PORT datad (96:96:96) (117:117:117)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (105:105:105) (137:137:137)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -41325,12 +43650,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) + (PORT clk (893:893:893) (899:899:899)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) + (PORT clrn (886:886:886) (890:890:890)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -41341,12 +43666,151 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~115) + (INSTANCE D\[1\]\~32) (DELAY (ABSOLUTE - (PORT dataa (300:300:300) (351:351:351)) - (PORT datab (188:188:188) (227:227:227)) - (PORT datad (403:403:403) (484:484:484)) + (PORT dataa (504:504:504) (603:603:603)) + (PORT datab (505:505:505) (589:589:589)) + (PORT datac (343:343:343) (410:410:410)) + (PORT datad (790:790:790) (900:900:900)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (123:123:123) (158:158:158)) + (PORT datab (499:499:499) (586:586:586)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (91:91:91) (110:110:110)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (336:336:336)) + (PORT datab (508:508:508) (610:610:610)) + (PORT datac (411:411:411) (506:506:506)) + (PORT datad (383:383:383) (464:464:464)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (144:144:144)) + (PORT datab (347:347:347) (409:409:409)) + (PORT datac (513:513:513) (619:619:619)) + (PORT datad (479:479:479) (561:561:561)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (264:264:264) (329:329:329)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (892:892:892) (898:898:898)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (885:885:885) (889:889:889)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (265:265:265) (339:339:339)) + (PORT datab (531:531:531) (638:638:638)) + (PORT datac (411:411:411) (505:505:505)) + (PORT datad (385:385:385) (466:466:466)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (396:396:396) (481:481:481)) + (PORT datab (713:713:713) (835:835:835)) + (PORT datac (404:404:404) (496:496:496)) + (PORT datad (160:160:160) (188:188:188)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (414:414:414) (496:496:496)) + (PORT datac (246:246:246) (309:309:309)) + (PORT datad (491:491:491) (578:578:578)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (405:405:405)) + (PORT datab (171:171:171) (209:209:209)) + (PORT datad (92:92:92) (109:109:109)) (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH datab combout (190:190:190) (181:181:181)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -41356,12 +43820,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) + (PORT clk (893:893:893) (899:899:899)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) + (PORT clrn (886:886:886) (890:890:890)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -41372,13 +43836,105 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~77) + (INSTANCE D\[1\]\~30) (DELAY (ABSOLUTE - (PORT dataa (593:593:593) (687:687:687)) - (PORT datab (643:643:643) (753:753:753)) - (PORT datac (342:342:342) (417:417:417)) - (PORT datad (119:119:119) (156:156:156)) + (PORT dataa (352:352:352) (424:424:424)) + (PORT datab (361:361:361) (430:430:430)) + (PORT datac (368:368:368) (429:429:429)) + (PORT datad (856:856:856) (989:989:989)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (709:709:709) (835:835:835)) + (PORT datac (380:380:380) (457:457:457)) + (PORT datad (395:395:395) (469:469:469)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (735:735:735) (861:861:861)) + (PORT datab (356:356:356) (421:421:421)) + (PORT datad (322:322:322) (361:361:361)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (891:891:891) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (737:737:737) (862:862:862)) + (PORT datab (563:563:563) (661:661:661)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (891:891:891) (894:894:894)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (121:121:121) (154:154:154)) + (PORT datab (1619:1619:1619) (1898:1898:1898)) + (PORT datac (118:118:118) (159:159:159)) + (PORT datad (118:118:118) (155:155:155)) (IOPATH dataa combout (165:165:165) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -41388,15 +43944,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~81) + (INSTANCE D\[1\]\~34) (DELAY (ABSOLUTE - (PORT dataa (889:889:889) (1015:1015:1015)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (91:91:91) (112:112:112)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (1372:1372:1372) (1622:1622:1622)) + (PORT datad (306:306:306) (353:353:353)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -41404,22 +43960,485 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1903:1903:1903) (2207:2207:2207)) - (PORT d[1] (924:924:924) (1081:1081:1081)) - (PORT d[2] (1394:1394:1394) (1602:1602:1602)) - (PORT d[3] (1060:1060:1060) (1235:1235:1235)) - (PORT d[4] (1100:1100:1100) (1278:1278:1278)) - (PORT d[5] (1202:1202:1202) (1421:1421:1421)) - (PORT d[6] (1313:1313:1313) (1508:1508:1508)) - (PORT d[7] (1246:1246:1246) (1411:1411:1411)) - (PORT d[8] (1678:1678:1678) (1943:1943:1943)) - (PORT d[9] (1275:1275:1275) (1470:1470:1470)) - (PORT d[10] (2344:2344:2344) (2687:2687:2687)) - (PORT d[11] (1008:1008:1008) (1166:1166:1166)) - (PORT d[12] (1364:1364:1364) (1560:1560:1560)) + (PORT d[0] (724:724:724) (824:824:824)) + (PORT clk (1084:1084:1084) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1405:1405:1405) (1668:1668:1668)) + (PORT d[1] (1480:1480:1480) (1671:1671:1671)) + (PORT d[2] (720:720:720) (825:825:825)) + (PORT d[3] (707:707:707) (809:809:809)) + (PORT d[4] (1146:1146:1146) (1313:1313:1313)) + (PORT d[5] (707:707:707) (818:818:818)) + (PORT d[6] (799:799:799) (912:912:912)) + (PORT d[7] (1536:1536:1536) (1765:1765:1765)) + (PORT d[8] (1402:1402:1402) (1652:1652:1652)) + (PORT d[9] (440:440:440) (516:516:516)) + (PORT d[10] (415:415:415) (485:485:485)) + (PORT d[11] (676:676:676) (777:777:777)) + (PORT d[12] (405:405:405) (472:472:472)) + (PORT clk (1082:1082:1082) (1100:1100:1100)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (697:697:697) (745:745:745)) + (PORT clk (1082:1082:1082) (1100:1100:1100)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1084:1084:1084) (1102:1102:1102)) + (PORT d[0] (932:932:932) (979:979:979)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1064:1064:1064) (1081:1081:1081)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (604:604:604) (613:613:613)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (555:555:555) (637:637:637)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1599:1599:1599) (1892:1892:1892)) + (PORT d[1] (1108:1108:1108) (1278:1278:1278)) + (PORT d[2] (545:545:545) (633:633:633)) + (PORT d[3] (531:531:531) (614:614:614)) + (PORT d[4] (799:799:799) (913:913:913)) + (PORT d[5] (517:517:517) (599:599:599)) + (PORT d[6] (626:626:626) (718:718:718)) + (PORT d[7] (1708:1708:1708) (1955:1955:1955)) + (PORT d[8] (901:901:901) (1048:1048:1048)) + (PORT d[9] (406:406:406) (473:473:473)) + (PORT d[10] (392:392:392) (457:457:457)) + (PORT d[11] (1449:1449:1449) (1693:1693:1693)) + (PORT d[12] (425:425:425) (499:499:499)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (517:517:517) (543:543:543)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (1842:1842:1842) (2033:2033:2033)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1069:1069:1069) (1085:1085:1085)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (609:609:609) (617:617:617)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (649:649:649) (722:722:722)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1504:1504:1504) (1750:1750:1750)) + (PORT d[1] (2131:2131:2131) (2426:2426:2426)) + (PORT d[2] (1343:1343:1343) (1541:1541:1541)) + (PORT d[3] (2503:2503:2503) (2842:2842:2842)) + (PORT d[4] (1858:1858:1858) (2171:2171:2171)) + (PORT d[5] (2713:2713:2713) (3096:3096:3096)) + (PORT d[6] (1458:1458:1458) (1658:1658:1658)) + (PORT d[7] (778:778:778) (875:875:875)) + (PORT d[8] (1780:1780:1780) (2069:2069:2069)) + (PORT d[9] (1017:1017:1017) (1155:1155:1155)) + (PORT d[10] (1114:1114:1114) (1260:1260:1260)) + (PORT d[11] (1969:1969:1969) (2299:2299:2299)) + (PORT d[12] (2785:2785:2785) (3155:3155:3155)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1068:1068:1068) (1183:1183:1183)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (PORT d[0] (1350:1350:1350) (1439:1439:1439)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1078:1078:1078) (1094:1094:1094)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (640:640:640)) + (PORT datab (665:665:665) (790:790:790)) + (PORT datac (510:510:510) (584:584:584)) + (PORT datad (578:578:578) (664:664:664)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (781:781:781) (873:873:873)) (PORT clk (1090:1090:1090) (1108:1108:1108)) ) ) @@ -41429,17 +44448,65 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1432:1432:1432) (1660:1660:1660)) + (PORT d[1] (1402:1402:1402) (1577:1577:1577)) + (PORT d[2] (1505:1505:1505) (1749:1749:1749)) + (PORT d[3] (942:942:942) (1074:1074:1074)) + (PORT d[4] (1384:1384:1384) (1600:1600:1600)) + (PORT d[5] (1802:1802:1802) (2059:2059:2059)) + (PORT d[6] (1244:1244:1244) (1415:1415:1415)) + (PORT d[7] (959:959:959) (1087:1087:1087)) + (PORT d[8] (1370:1370:1370) (1592:1592:1592)) + (PORT d[9] (960:960:960) (1083:1083:1083)) + (PORT d[10] (1447:1447:1447) (1631:1631:1631)) + (PORT d[11] (2349:2349:2349) (2735:2735:2735)) + (PORT d[12] (1407:1407:1407) (1591:1591:1591)) + (PORT clk (1088:1088:1088) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1115:1115:1115) (1203:1203:1203)) + (PORT clk (1088:1088:1088) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1090:1090:1090) (1108:1108:1108)) - (PORT d[0] (1428:1428:1428) (1591:1591:1591)) + (PORT d[0] (1209:1209:1209) (1285:1285:1285)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1091:1091:1091) (1109:1109:1109)) @@ -41448,11 +44515,31 @@ ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1072:1072:1072) (1089:1089:1089)) + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1070:1070:1070) (1087:1087:1087)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -41463,49 +44550,65 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) + (PORT clk (610:610:610) (619:619:619)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) + (PORT clk (611:611:611) (620:620:620)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) + (PORT clk (611:611:611) (620:620:620)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) + (PORT clk (611:611:611) (620:620:620)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~39) (DELAY (ABSOLUTE - (PORT d[0] (858:858:858) (978:978:978)) - (PORT clk (1087:1087:1087) (1105:1105:1105)) + (PORT dataa (844:844:844) (989:989:989)) + (PORT datab (679:679:679) (770:770:770)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (776:776:776) (880:880:880)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (835:835:835) (945:945:945)) + (PORT clk (1102:1102:1102) (1119:1119:1119)) ) ) (TIMINGCHECK @@ -41514,23 +44617,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1958:1958:1958) (2237:2237:2237)) - (PORT d[1] (952:952:952) (1135:1135:1135)) - (PORT d[2] (1019:1019:1019) (1175:1175:1175)) - (PORT d[3] (1176:1176:1176) (1375:1375:1375)) - (PORT d[4] (1274:1274:1274) (1480:1480:1480)) - (PORT d[5] (965:965:965) (1137:1137:1137)) - (PORT d[6] (813:813:813) (936:936:936)) - (PORT d[7] (825:825:825) (950:950:950)) - (PORT d[8] (1671:1671:1671) (1934:1934:1934)) - (PORT d[9] (1320:1320:1320) (1511:1511:1511)) - (PORT d[10] (1313:1313:1313) (1512:1512:1512)) - (PORT d[11] (1209:1209:1209) (1403:1403:1403)) - (PORT d[12] (1130:1130:1130) (1305:1305:1305)) - (PORT clk (1085:1085:1085) (1103:1103:1103)) + (PORT d[0] (1413:1413:1413) (1641:1641:1641)) + (PORT d[1] (1315:1315:1315) (1490:1490:1490)) + (PORT d[2] (1212:1212:1212) (1393:1393:1393)) + (PORT d[3] (1908:1908:1908) (2156:2156:2156)) + (PORT d[4] (1318:1318:1318) (1559:1559:1559)) + (PORT d[5] (2134:2134:2134) (2433:2433:2433)) + (PORT d[6] (1449:1449:1449) (1648:1648:1648)) + (PORT d[7] (1420:1420:1420) (1603:1603:1603)) + (PORT d[8] (1666:1666:1666) (1906:1906:1906)) + (PORT d[9] (1604:1604:1604) (1831:1831:1831)) + (PORT d[10] (1684:1684:1684) (1914:1914:1914)) + (PORT d[11] (1564:1564:1564) (1815:1815:1815)) + (PORT d[12] (2068:2068:2068) (2347:2347:2347)) + (PORT clk (1100:1100:1100) (1117:1117:1117)) ) ) (TIMINGCHECK @@ -41539,11 +44642,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1619:1619:1619) (1787:1787:1787)) - (PORT clk (1085:1085:1085) (1103:1103:1103)) + (PORT d[0] (1621:1621:1621) (1770:1770:1770)) + (PORT clk (1100:1100:1100) (1117:1117:1117)) ) ) (TIMINGCHECK @@ -41552,60 +44655,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1087:1087:1087) (1105:1105:1105)) - (PORT d[0] (2447:2447:2447) (2710:2710:2710)) + (PORT clk (1102:1102:1102) (1119:1119:1119)) + (PORT d[0] (2171:2171:2171) (2012:2012:2012)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) + (PORT clk (1103:1103:1103) (1120:1120:1120)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) + (PORT clk (1103:1103:1103) (1120:1120:1120)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) + (PORT clk (1103:1103:1103) (1120:1120:1120)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) + (PORT clk (1103:1103:1103) (1120:1120:1120)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1042:1042:1042) (1062:1062:1062)) + (PORT clk (1057:1057:1057) (1076:1076:1076)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -41616,11 +44719,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (941:941:941) (1043:1043:1043)) - (PORT clk (1047:1047:1047) (1065:1065:1065)) + (PORT d[0] (1208:1208:1208) (1345:1345:1345)) + (PORT clk (1062:1062:1062) (1079:1079:1079)) ) ) (TIMINGCHECK @@ -41629,23 +44732,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2450:2450:2450) (2777:2777:2777)) - (PORT d[1] (2392:2392:2392) (2704:2704:2704)) - (PORT d[2] (2394:2394:2394) (2721:2721:2721)) - (PORT d[3] (2491:2491:2491) (2861:2861:2861)) - (PORT d[4] (2566:2566:2566) (2910:2910:2910)) - (PORT d[5] (2373:2373:2373) (2706:2706:2706)) - (PORT d[6] (2612:2612:2612) (2990:2990:2990)) - (PORT d[7] (2373:2373:2373) (2714:2714:2714)) - (PORT d[8] (2476:2476:2476) (2808:2808:2808)) - (PORT d[9] (2554:2554:2554) (2935:2935:2935)) - (PORT d[10] (2444:2444:2444) (2765:2765:2765)) - (PORT d[11] (2421:2421:2421) (2728:2728:2728)) - (PORT d[12] (2407:2407:2407) (2712:2712:2712)) - (PORT clk (1044:1044:1044) (1064:1064:1064)) + (PORT d[0] (2497:2497:2497) (2815:2815:2815)) + (PORT d[1] (2496:2496:2496) (2815:2815:2815)) + (PORT d[2] (2504:2504:2504) (2835:2835:2835)) + (PORT d[3] (2441:2441:2441) (2755:2755:2755)) + (PORT d[4] (2407:2407:2407) (2744:2744:2744)) + (PORT d[5] (2478:2478:2478) (2782:2782:2782)) + (PORT d[6] (2412:2412:2412) (2708:2708:2708)) + (PORT d[7] (2486:2486:2486) (2802:2802:2802)) + (PORT d[8] (2535:2535:2535) (2891:2891:2891)) + (PORT d[9] (2436:2436:2436) (2771:2771:2771)) + (PORT d[10] (2354:2354:2354) (2645:2645:2645)) + (PORT d[11] (2472:2472:2472) (2820:2820:2820)) + (PORT d[12] (2358:2358:2358) (2657:2657:2657)) + (PORT clk (1059:1059:1059) (1078:1078:1078)) ) ) (TIMINGCHECK @@ -41654,70 +44757,85 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1047:1047:1047) (1065:1065:1065)) + (PORT clk (1062:1062:1062) (1079:1079:1079)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1048:1048:1048) (1066:1066:1066)) + (PORT clk (1063:1063:1063) (1080:1080:1080)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1048:1048:1048) (1066:1066:1066)) + (PORT clk (1063:1063:1063) (1080:1080:1080)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1048:1048:1048) (1066:1066:1066)) + (PORT clk (1063:1063:1063) (1080:1080:1080)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1048:1048:1048) (1066:1066:1066)) + (PORT clk (1063:1063:1063) (1080:1080:1080)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2356:2356:2356) (2720:2720:2720)) - (PORT d[1] (1675:1675:1675) (1954:1954:1954)) - (PORT d[2] (1571:1571:1571) (1793:1793:1793)) - (PORT d[3] (1306:1306:1306) (1539:1539:1539)) - (PORT d[4] (1463:1463:1463) (1705:1705:1705)) - (PORT d[5] (1474:1474:1474) (1713:1713:1713)) - (PORT d[6] (1093:1093:1093) (1258:1258:1258)) - (PORT d[7] (1344:1344:1344) (1523:1523:1523)) - (PORT d[8] (1807:1807:1807) (2124:2124:2124)) - (PORT d[9] (1492:1492:1492) (1734:1734:1734)) - (PORT d[10] (2804:2804:2804) (3207:3207:3207)) - (PORT d[11] (1095:1095:1095) (1275:1275:1275)) - (PORT d[12] (1289:1289:1289) (1483:1483:1483)) + (PORT clk (1058:1058:1058) (1077:1077:1077)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1101:1101:1101) (1289:1289:1289)) + (PORT d[1] (954:954:954) (1077:1077:1077)) + (PORT d[2] (1145:1145:1145) (1339:1339:1339)) + (PORT d[3] (1079:1079:1079) (1223:1223:1223)) + (PORT d[4] (1511:1511:1511) (1740:1740:1740)) + (PORT d[5] (1307:1307:1307) (1487:1487:1487)) + (PORT d[6] (960:960:960) (1100:1100:1100)) + (PORT d[7] (1149:1149:1149) (1302:1302:1302)) + (PORT d[8] (1036:1036:1036) (1208:1208:1208)) + (PORT d[9] (1155:1155:1155) (1306:1306:1306)) + (PORT d[10] (957:957:957) (1081:1081:1081)) + (PORT d[11] (2528:2528:2528) (2934:2934:2934)) + (PORT d[12] (945:945:945) (1060:1060:1060)) (PORT clk (1095:1095:1095) (1112:1112:1112)) ) ) @@ -41727,17 +44845,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1095:1095:1095) (1112:1112:1112)) - (PORT d[0] (2275:2275:2275) (2058:2058:2058)) + (PORT d[0] (1118:1118:1118) (1024:1024:1024)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1096:1096:1096) (1113:1113:1113)) @@ -41747,7 +44865,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1077:1077:1077) (1093:1093:1093)) @@ -41761,7 +44879,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (617:617:617) (625:625:625)) @@ -41770,7 +44888,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) (DELAY (ABSOLUTE (PORT clk (618:618:618) (626:626:626)) @@ -41779,7 +44897,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (618:618:618) (626:626:626)) @@ -41789,7 +44907,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (618:618:618) (626:626:626)) @@ -41799,11 +44917,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (876:876:876) (1020:1020:1020)) - (PORT clk (1088:1088:1088) (1106:1106:1106)) + (PORT d[0] (1424:1424:1424) (1658:1658:1658)) + (PORT d[1] (1552:1552:1552) (1763:1763:1763)) + (PORT d[2] (1311:1311:1311) (1525:1525:1525)) + (PORT d[3] (1246:1246:1246) (1423:1423:1423)) + (PORT d[4] (1155:1155:1155) (1350:1350:1350)) + (PORT d[5] (1408:1408:1408) (1611:1611:1611)) + (PORT d[6] (1420:1420:1420) (1636:1636:1636)) + (PORT d[7] (1961:1961:1961) (2241:2241:2241)) + (PORT d[8] (1605:1605:1605) (1843:1843:1843)) + (PORT d[9] (1388:1388:1388) (1599:1599:1599)) + (PORT d[10] (1890:1890:1890) (2172:2172:2172)) + (PORT d[11] (1205:1205:1205) (1400:1400:1400)) + (PORT d[12] (1350:1350:1350) (1552:1552:1552)) + (PORT clk (1099:1099:1099) (1116:1116:1116)) ) ) (TIMINGCHECK @@ -41812,98 +44942,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE - (PORT d[0] (1688:1688:1688) (1964:1964:1964)) - (PORT d[1] (1334:1334:1334) (1569:1569:1569)) - (PORT d[2] (1223:1223:1223) (1416:1416:1416)) - (PORT d[3] (1064:1064:1064) (1252:1252:1252)) - (PORT d[4] (1419:1419:1419) (1629:1629:1629)) - (PORT d[5] (1143:1143:1143) (1344:1344:1344)) - (PORT d[6] (986:986:986) (1130:1130:1130)) - (PORT d[7] (1372:1372:1372) (1582:1582:1582)) - (PORT d[8] (1652:1652:1652) (1914:1914:1914)) - (PORT d[9] (1153:1153:1153) (1324:1324:1324)) - (PORT d[10] (1141:1141:1141) (1317:1317:1317)) - (PORT d[11] (1383:1383:1383) (1601:1601:1601)) - (PORT d[12] (1451:1451:1451) (1660:1660:1660)) - (PORT clk (1086:1086:1086) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1453:1453:1453) (1609:1609:1609)) - (PORT clk (1086:1086:1086) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) - (PORT d[0] (2488:2488:2488) (2278:2278:2278)) + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (PORT d[0] (1509:1509:1509) (1696:1696:1696)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1089:1089:1089) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1107:1107:1107)) + (PORT clk (1100:1100:1100) (1117:1117:1117)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1043:1043:1043) (1063:1063:1063)) + (PORT clk (1081:1081:1081) (1097:1097:1097)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -41914,98 +44976,150 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (1108:1108:1108) (1228:1228:1228)) - (PORT clk (1048:1048:1048) (1066:1066:1066)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2443:2443:2443) (2777:2777:2777)) - (PORT d[1] (2372:2372:2372) (2684:2684:2684)) - (PORT d[2] (2405:2405:2405) (2732:2732:2732)) - (PORT d[3] (2484:2484:2484) (2833:2833:2833)) - (PORT d[4] (2401:2401:2401) (2725:2725:2725)) - (PORT d[5] (2571:2571:2571) (2915:2915:2915)) - (PORT d[6] (2478:2478:2478) (2831:2831:2831)) - (PORT d[7] (2422:2422:2422) (2757:2757:2757)) - (PORT d[8] (2472:2472:2472) (2808:2808:2808)) - (PORT d[9] (2555:2555:2555) (2931:2931:2931)) - (PORT d[10] (2414:2414:2414) (2717:2717:2717)) - (PORT d[11] (2582:2582:2582) (2920:2920:2920)) - (PORT d[12] (2506:2506:2506) (2850:2850:2850)) - (PORT clk (1045:1045:1045) (1065:1065:1065)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1048:1048:1048) (1066:1066:1066)) + (PORT clk (621:621:621) (629:629:629)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1049:1049:1049) (1067:1067:1067)) + (PORT clk (622:622:622) (630:630:630)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (622:622:622) (630:630:630)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (622:622:622) (630:630:630)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (924:924:924) (1071:1071:1071)) + (PORT clk (1096:1096:1096) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1596:1596:1596) (1854:1854:1854)) + (PORT d[1] (1730:1730:1730) (1961:1961:1961)) + (PORT d[2] (1153:1153:1153) (1345:1345:1345)) + (PORT d[3] (1086:1086:1086) (1250:1250:1250)) + (PORT d[4] (1184:1184:1184) (1386:1386:1386)) + (PORT d[5] (1489:1489:1489) (1701:1701:1701)) + (PORT d[6] (1244:1244:1244) (1438:1438:1438)) + (PORT d[7] (1972:1972:1972) (2249:2249:2249)) + (PORT d[8] (1785:1785:1785) (2050:2050:2050)) + (PORT d[9] (1354:1354:1354) (1564:1564:1564)) + (PORT d[10] (1130:1130:1130) (1298:1298:1298)) + (PORT d[11] (1209:1209:1209) (1397:1397:1397)) + (PORT d[12] (1411:1411:1411) (1617:1617:1617)) + (PORT clk (1094:1094:1094) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1131:1131:1131) (1240:1240:1240)) + (PORT clk (1094:1094:1094) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1114:1114:1114)) + (PORT d[0] (1825:1825:1825) (1999:1999:1999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1049:1049:1049) (1067:1067:1067)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1049:1049:1049) (1067:1067:1067)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1049:1049:1049) (1067:1067:1067)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1044:1044:1044) (1064:1064:1064)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + (PORT clk (1051:1051:1051) (1071:1071:1071)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) (TIMINGCHECK @@ -42014,15 +45128,117 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~0) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) (DELAY (ABSOLUTE - (PORT dataa (646:646:646) (757:757:757)) - (PORT datab (501:501:501) (596:596:596)) - (PORT datac (785:785:785) (890:890:890)) - (PORT datad (804:804:804) (913:913:913)) - (IOPATH dataa combout (188:188:188) (184:184:184)) + (PORT d[0] (1189:1189:1189) (1350:1350:1350)) + (PORT clk (1056:1056:1056) (1074:1074:1074)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2519:2519:2519) (2860:2860:2860)) + (PORT d[1] (2502:2502:2502) (2847:2847:2847)) + (PORT d[2] (2482:2482:2482) (2816:2816:2816)) + (PORT d[3] (2424:2424:2424) (2757:2757:2757)) + (PORT d[4] (2473:2473:2473) (2795:2795:2795)) + (PORT d[5] (2522:2522:2522) (2859:2859:2859)) + (PORT d[6] (2458:2458:2458) (2788:2788:2788)) + (PORT d[7] (2433:2433:2433) (2727:2727:2727)) + (PORT d[8] (2590:2590:2590) (2953:2953:2953)) + (PORT d[9] (2489:2489:2489) (2808:2808:2808)) + (PORT d[10] (2451:2451:2451) (2781:2781:2781)) + (PORT d[11] (2462:2462:2462) (2806:2806:2806)) + (PORT d[12] (2406:2406:2406) (2697:2697:2697)) + (PORT clk (1053:1053:1053) (1073:1073:1073)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1056:1056:1056) (1074:1074:1074)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1075:1075:1075)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (500:500:500) (582:582:582)) + (PORT datab (432:432:432) (522:522:522)) + (PORT datac (820:820:820) (939:939:939)) + (PORT datad (648:648:648) (741:741:741)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (649:649:649)) + (PORT datab (569:569:569) (665:665:665)) + (PORT datac (910:910:910) (1049:1049:1049)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH datab combout (190:190:190) (188:188:188)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -42031,15 +45247,756 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~1) + (INSTANCE D\[1\]\~37) (DELAY (ABSOLUTE - (PORT dataa (735:735:735) (849:849:849)) - (PORT datab (508:508:508) (603:603:603)) - (PORT datac (801:801:801) (924:924:924)) + (PORT dataa (416:416:416) (510:510:510)) + (PORT datab (993:993:993) (1154:1154:1154)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (97:97:97) (117:117:117)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~118) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (1087:1087:1087)) + (PORT datab (1718:1718:1718) (2021:2021:2021)) + (PORT datac (91:91:91) (112:112:112)) (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (181:181:181) (175:175:175)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (521:521:521) (598:598:598)) + (PORT datab (490:490:490) (568:568:568)) + (PORT datac (901:901:901) (1022:1022:1022)) + (PORT datad (104:104:104) (121:121:121)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (747:747:747)) + (PORT datab (806:806:806) (931:931:931)) + (PORT datac (1794:1794:1794) (2045:2045:2045)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (516:516:516) (606:606:606)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datac (103:103:103) (124:124:124)) + (PORT datad (619:619:619) (708:708:708)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (432:432:432) (460:460:460)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (145:145:145) (194:194:194)) + (PORT datac (309:309:309) (354:354:354)) + (PORT datad (200:200:200) (236:236:236)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (917:917:917) (902:902:902)) + (PORT ena (1045:1045:1045) (1140:1140:1140)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (1084:1084:1084)) + (PORT datab (1095:1095:1095) (1287:1287:1287)) + (PORT datac (195:195:195) (237:237:237)) + (PORT datad (647:647:647) (736:736:736)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instED) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (906:906:906) (890:890:890)) + (PORT ena (405:405:405) (422:422:422)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (504:504:504)) + (PORT datab (408:408:408) (501:501:501)) + (PORT datac (1062:1062:1062) (1241:1241:1241)) + (PORT datad (941:941:941) (1087:1087:1087)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1402:1402:1402)) + (PORT datab (808:808:808) (961:961:961)) + (PORT datac (613:613:613) (692:692:692)) + (PORT datad (479:479:479) (558:558:558)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (1049:1049:1049)) + (PORT datab (343:343:343) (401:401:401)) + (PORT datac (584:584:584) (688:688:688)) + (PORT datad (1478:1478:1478) (1681:1681:1681)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (1008:1008:1008) (1169:1169:1169)) + (PORT datab (609:609:609) (721:721:721)) + (PORT datac (453:453:453) (522:522:522)) + (PORT datad (1457:1457:1457) (1656:1656:1656)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (478:478:478) (562:562:562)) + (PORT datab (600:600:600) (709:709:709)) + (PORT datac (1035:1035:1035) (1193:1193:1193)) + (PORT datad (341:341:341) (399:399:399)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (1049:1049:1049)) + (PORT datab (1296:1296:1296) (1534:1534:1534)) + (PORT datac (345:345:345) (412:412:412)) + (PORT datad (548:548:548) (653:653:653)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (472:472:472)) + (PORT datab (513:513:513) (598:598:598)) + (PORT datac (816:816:816) (927:927:927)) + (PORT datad (357:357:357) (418:418:418)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (380:380:380)) + (PORT datab (628:628:628) (715:715:715)) + (PORT datac (293:293:293) (337:337:337)) + (PORT datad (336:336:336) (396:396:396)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~126) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (143:143:143)) + (PORT datab (266:266:266) (332:332:332)) + (PORT datad (336:336:336) (390:390:390)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (892:892:892) (898:898:898)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (885:885:885) (889:889:889)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~125) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (249:249:249)) + (PORT datab (196:196:196) (236:236:236)) + (PORT datad (99:99:99) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (893:893:893) (898:898:898)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (885:885:885) (890:890:890)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (269:269:269)) + (PORT datab (530:530:530) (615:615:615)) + (PORT datac (459:459:459) (521:521:521)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~120) + (DELAY + (ABSOLUTE + (PORT dataa (267:267:267) (341:341:341)) + (PORT datab (508:508:508) (610:610:610)) + (PORT datac (411:411:411) (506:506:506)) + (PORT datad (387:387:387) (469:469:469)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~121) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (424:424:424)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datad (239:239:239) (296:296:296)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (892:892:892) (898:898:898)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (885:885:885) (889:889:889)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~122) + (DELAY + (ABSOLUTE + (PORT datab (422:422:422) (521:521:521)) + (PORT datac (695:695:695) (815:815:815)) + (PORT datad (133:133:133) (170:170:170)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~123) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (476:476:476)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (401:401:401) (493:493:493)) + (PORT datad (330:330:330) (387:387:387)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~124) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (333:333:333)) + (PORT datab (744:744:744) (846:846:846)) + (PORT datad (163:163:163) (186:186:186)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (893:893:893) (899:899:899)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (886:886:886) (890:890:890)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (721:721:721) (837:837:837)) + (PORT datab (501:501:501) (576:576:576)) + (PORT datac (322:322:322) (381:381:381)) + (PORT datad (347:347:347) (417:417:417)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~115) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (448:448:448)) + (PORT datab (394:394:394) (472:472:472)) + (PORT datac (680:680:680) (786:786:786)) + (PORT datad (665:665:665) (763:763:763)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~116) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (381:381:381)) + (PORT datab (414:414:414) (493:493:493)) + (PORT datac (379:379:379) (456:456:456)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~117) + (DELAY + (ABSOLUTE + (PORT datab (108:108:108) (139:139:139)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (886:886:886) (891:891:891)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1315:1315:1315) (1554:1554:1554)) + (PORT datab (802:802:802) (943:943:943)) + (PORT datad (357:357:357) (433:433:433)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~118) + (DELAY + (ABSOLUTE + (PORT dataa (164:164:164) (224:224:224)) + (PORT datab (517:517:517) (612:612:612)) + (PORT datac (540:540:540) (640:640:640)) + (PORT datad (386:386:386) (471:471:471)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~131) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (670:670:670)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datad (142:142:142) (184:184:184)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~119) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (244:244:244)) + (PORT datab (334:334:334) (398:398:398)) + (PORT datad (438:438:438) (495:495:495)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (893:893:893) (898:898:898)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (885:885:885) (890:890:890)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~114) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (143:143:143)) + (PORT datab (341:341:341) (405:405:405)) + (PORT datad (104:104:104) (121:121:121)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (900:900:900) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (886:886:886) (891:891:891)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~113) + (DELAY + (ABSOLUTE + (PORT dataa (431:431:431) (524:524:524)) + (PORT datab (335:335:335) (391:391:391)) + (PORT datad (325:325:325) (372:372:372)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (902:902:902)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (883:883:883) (888:888:888)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (456:456:456)) + (PORT datab (130:130:130) (178:178:178)) + (PORT datac (1371:1371:1371) (1616:1616:1616)) + (PORT datad (341:341:341) (404:404:404)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (316:316:316) (375:375:375)) + (PORT datab (1426:1426:1426) (1673:1673:1673)) + (PORT datac (508:508:508) (597:597:597)) + (PORT datad (327:327:327) (379:379:379)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (746:746:746)) + (PORT datab (673:673:673) (768:768:768)) + (PORT datac (1910:1910:1910) (2251:2251:2251)) + (PORT datad (326:326:326) (378:378:378)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -42047,316 +46004,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (496:496:496) (569:569:569)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1898:1898:1898) (2205:2205:2205)) - (PORT d[1] (1002:1002:1002) (1185:1185:1185)) - (PORT d[2] (1140:1140:1140) (1304:1304:1304)) - (PORT d[3] (1203:1203:1203) (1403:1403:1403)) - (PORT d[4] (1057:1057:1057) (1219:1219:1219)) - (PORT d[5] (774:774:774) (921:921:921)) - (PORT d[6] (820:820:820) (948:948:948)) - (PORT d[7] (1963:1963:1963) (2216:2216:2216)) - (PORT d[8] (1431:1431:1431) (1674:1674:1674)) - (PORT d[9] (2015:2015:2015) (2327:2327:2327)) - (PORT d[10] (1692:1692:1692) (1948:1948:1948)) - (PORT d[11] (827:827:827) (959:959:959)) - (PORT d[12] (830:830:830) (960:960:960)) - (PORT clk (1090:1090:1090) (1107:1107:1107)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1893:1893:1893) (2093:2093:2093)) - (PORT clk (1090:1090:1090) (1107:1107:1107)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (PORT d[0] (1046:1046:1046) (1116:1116:1116)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1072:1072:1072) (1088:1088:1088)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (621:621:621)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (621:621:621)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (621:621:621)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (828:828:828) (944:944:944)) - (PORT clk (1082:1082:1082) (1100:1100:1100)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2082:2082:2082) (2419:2419:2419)) - (PORT d[1] (977:977:977) (1152:1152:1152)) - (PORT d[2] (1908:1908:1908) (2182:2182:2182)) - (PORT d[3] (1200:1200:1200) (1400:1400:1400)) - (PORT d[4] (1473:1473:1473) (1710:1710:1710)) - (PORT d[5] (973:973:973) (1145:1145:1145)) - (PORT d[6] (1035:1035:1035) (1202:1202:1202)) - (PORT d[7] (970:970:970) (1112:1112:1112)) - (PORT d[8] (1931:1931:1931) (2242:2242:2242)) - (PORT d[9] (1624:1624:1624) (1868:1868:1868)) - (PORT d[10] (2021:2021:2021) (2323:2323:2323)) - (PORT d[11] (1010:1010:1010) (1172:1172:1172)) - (PORT d[12] (1004:1004:1004) (1151:1151:1151)) - (PORT clk (1080:1080:1080) (1098:1098:1098)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1078:1078:1078) (1178:1178:1178)) - (PORT clk (1080:1080:1080) (1098:1098:1098)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1082:1082:1082) (1100:1100:1100)) - (PORT d[0] (1538:1538:1538) (1677:1677:1677)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1083:1083:1083) (1101:1101:1101)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1083:1083:1083) (1101:1101:1101)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1083:1083:1083) (1101:1101:1101)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1083:1083:1083) (1101:1101:1101)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1062:1062:1062) (1079:1079:1079)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (602:602:602) (611:611:611)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (603:603:603) (612:612:612)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (603:603:603) (612:612:612)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (603:603:603) (612:612:612)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (696:696:696) (802:802:802)) + (PORT d[0] (568:568:568) (653:653:653)) (PORT clk (1092:1092:1092) (1110:1110:1110)) ) ) @@ -42366,22 +46017,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1891:1891:1891) (2200:2200:2200)) - (PORT d[1] (764:764:764) (903:903:903)) - (PORT d[2] (1115:1115:1115) (1298:1298:1298)) - (PORT d[3] (861:861:861) (1007:1007:1007)) - (PORT d[4] (1071:1071:1071) (1242:1242:1242)) - (PORT d[5] (927:927:927) (1087:1087:1087)) - (PORT d[6] (665:665:665) (775:775:775)) - (PORT d[7] (836:836:836) (960:960:960)) - (PORT d[8] (1455:1455:1455) (1707:1707:1707)) - (PORT d[9] (2011:2011:2011) (2318:2318:2318)) - (PORT d[10] (1658:1658:1658) (1903:1903:1903)) - (PORT d[11] (696:696:696) (800:800:800)) - (PORT d[12] (623:623:623) (719:719:719)) + (PORT d[0] (1956:1956:1956) (2300:2300:2300)) + (PORT d[1] (901:901:901) (1036:1036:1036)) + (PORT d[2] (579:579:579) (672:672:672)) + (PORT d[3] (926:926:926) (1070:1070:1070)) + (PORT d[4] (1718:1718:1718) (1988:1988:1988)) + (PORT d[5] (531:531:531) (614:614:614)) + (PORT d[6] (909:909:909) (1060:1060:1060)) + (PORT d[7] (703:703:703) (813:813:813)) + (PORT d[8] (676:676:676) (792:792:792)) + (PORT d[9] (635:635:635) (743:743:743)) + (PORT d[10] (596:596:596) (691:691:691)) + (PORT d[11] (1276:1276:1276) (1491:1491:1491)) + (PORT d[12] (631:631:631) (738:738:738)) (PORT clk (1090:1090:1090) (1108:1108:1108)) ) ) @@ -42391,10 +46042,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1641:1641:1641) (1814:1814:1814)) + (PORT d[0] (648:648:648) (688:688:688)) (PORT clk (1090:1090:1090) (1108:1108:1108)) ) ) @@ -42404,17 +46055,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1092:1092:1092) (1110:1110:1110)) - (PORT d[0] (1828:1828:1828) (2013:2013:2013)) + (PORT d[0] (1303:1303:1303) (1405:1405:1405)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1093:1093:1093) (1111:1111:1111)) @@ -42424,7 +46075,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1093:1093:1093) (1111:1111:1111)) @@ -42434,7 +46085,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1093:1093:1093) (1111:1111:1111)) @@ -42444,7 +46095,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1093:1093:1093) (1111:1111:1111)) @@ -42454,7 +46105,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1072:1072:1072) (1089:1089:1089)) @@ -42468,7 +46119,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (612:612:612) (621:621:621)) @@ -42477,7 +46128,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) (DELAY (ABSOLUTE (PORT clk (613:613:613) (622:622:622)) @@ -42486,7 +46137,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (613:613:613) (622:622:622)) @@ -42496,7 +46147,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (613:613:613) (622:622:622)) @@ -42506,10 +46157,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1002:1002:1002) (1135:1135:1135)) + (PORT d[0] (544:544:544) (625:625:625)) (PORT clk (1091:1091:1091) (1108:1108:1108)) ) ) @@ -42519,22 +46170,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1907:1907:1907) (2218:2218:2218)) - (PORT d[1] (982:982:982) (1157:1157:1157)) - (PORT d[2] (1569:1569:1569) (1801:1801:1801)) - (PORT d[3] (1205:1205:1205) (1398:1398:1398)) - (PORT d[4] (1266:1266:1266) (1475:1475:1475)) - (PORT d[5] (1387:1387:1387) (1637:1637:1637)) - (PORT d[6] (1227:1227:1227) (1424:1424:1424)) - (PORT d[7] (1427:1427:1427) (1617:1617:1617)) - (PORT d[8] (1747:1747:1747) (2037:2037:2037)) - (PORT d[9] (1449:1449:1449) (1675:1675:1675)) - (PORT d[10] (2215:2215:2215) (2545:2545:2545)) - (PORT d[11] (992:992:992) (1149:1149:1149)) - (PORT d[12] (1348:1348:1348) (1543:1543:1543)) + (PORT d[0] (1972:1972:1972) (2319:2319:2319)) + (PORT d[1] (739:739:739) (857:857:857)) + (PORT d[2] (970:970:970) (1137:1137:1137)) + (PORT d[3] (916:916:916) (1059:1059:1059)) + (PORT d[4] (1706:1706:1706) (1978:1978:1978)) + (PORT d[5] (715:715:715) (825:825:825)) + (PORT d[6] (742:742:742) (865:865:865)) + (PORT d[7] (744:744:744) (867:867:867)) + (PORT d[8] (870:870:870) (1008:1008:1008)) + (PORT d[9] (645:645:645) (751:751:751)) + (PORT d[10] (609:609:609) (705:705:705)) + (PORT d[11] (1252:1252:1252) (1459:1459:1459)) + (PORT d[12] (794:794:794) (923:923:923)) (PORT clk (1089:1089:1089) (1106:1106:1106)) ) ) @@ -42544,10 +46195,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1269:1269:1269) (1391:1391:1391)) + (PORT d[0] (681:681:681) (725:725:725)) (PORT clk (1089:1089:1089) (1106:1106:1106)) ) ) @@ -42557,17 +46208,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1091:1091:1091) (1108:1108:1108)) - (PORT d[0] (1504:1504:1504) (1616:1616:1616)) + (PORT d[0] (1317:1317:1317) (1421:1421:1421)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1092:1092:1092) (1109:1109:1109)) @@ -42577,7 +46228,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1092:1092:1092) (1109:1109:1109)) @@ -42587,7 +46238,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1092:1092:1092) (1109:1109:1109)) @@ -42597,7 +46248,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1092:1092:1092) (1109:1109:1109)) @@ -42607,7 +46258,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1071:1071:1071) (1087:1087:1087)) @@ -42621,7 +46272,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (611:611:611) (619:619:619)) @@ -42630,7 +46281,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) (DELAY (ABSOLUTE (PORT clk (612:612:612) (620:620:620)) @@ -42639,7 +46290,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (612:612:612) (620:620:620)) @@ -42649,7 +46300,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (612:612:612) (620:620:620)) @@ -42657,63 +46308,980 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (511:511:511) (584:584:584)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1568:1568:1568) (1836:1836:1836)) + (PORT d[1] (878:878:878) (1007:1007:1007)) + (PORT d[2] (774:774:774) (904:904:904)) + (PORT d[3] (752:752:752) (876:876:876)) + (PORT d[4] (1529:1529:1529) (1777:1777:1777)) + (PORT d[5] (892:892:892) (1032:1032:1032)) + (PORT d[6] (871:871:871) (1009:1009:1009)) + (PORT d[7] (887:887:887) (1025:1025:1025)) + (PORT d[8] (876:876:876) (1011:1011:1011)) + (PORT d[9] (966:966:966) (1116:1116:1116)) + (PORT d[10] (786:786:786) (911:911:911)) + (PORT d[11] (1079:1079:1079) (1263:1263:1263)) + (PORT d[12] (817:817:817) (952:952:952)) + (PORT clk (1088:1088:1088) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (712:712:712) (763:763:763)) + (PORT clk (1088:1088:1088) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (PORT d[0] (1305:1305:1305) (1425:1425:1425)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1070:1070:1070) (1086:1086:1086)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~2) + (INSTANCE D\[4\]\~93) (DELAY (ABSOLUTE - (PORT dataa (962:962:962) (1111:1111:1111)) - (PORT datab (660:660:660) (745:745:745)) - (PORT datad (964:964:964) (1091:1091:1091)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (499:499:499) (572:572:572)) + (PORT datab (684:684:684) (804:804:804)) + (PORT datad (506:506:506) (572:572:572)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (205:205:205)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~3) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (847:847:847) (962:962:962)) - (PORT datab (834:834:834) (948:948:948)) - (PORT datac (1159:1159:1159) (1329:1329:1329)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT d[0] (770:770:770) (901:901:901)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1737:1737:1737) (2036:2036:2036)) + (PORT d[1] (1672:1672:1672) (1893:1893:1893)) + (PORT d[2] (558:558:558) (646:646:646)) + (PORT d[3] (727:727:727) (845:845:845)) + (PORT d[4] (1178:1178:1178) (1352:1352:1352)) + (PORT d[5] (521:521:521) (603:603:603)) + (PORT d[6] (646:646:646) (743:743:743)) + (PORT d[7] (1544:1544:1544) (1769:1769:1769)) + (PORT d[8] (895:895:895) (1036:1036:1036)) + (PORT d[9] (237:237:237) (279:279:279)) + (PORT d[10] (230:230:230) (272:272:272)) + (PORT d[11] (1620:1620:1620) (1888:1888:1888)) + (PORT d[12] (410:410:410) (481:481:481)) + (PORT clk (1085:1085:1085) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (695:695:695) (740:740:740)) + (PORT clk (1085:1085:1085) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1104:1104:1104)) + (PORT d[0] (952:952:952) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1067:1067:1067) (1083:1083:1083)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (607:607:607) (615:615:615)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~109) + (INSTANCE D\[4\]\~94) (DELAY (ABSOLUTE - (PORT dataa (378:378:378) (465:465:465)) - (PORT datab (646:646:646) (769:769:769)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (535:535:535) (610:610:610)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (666:666:666) (783:783:783)) + (PORT datad (830:830:830) (931:931:931)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (653:653:653) (730:730:730)) + (PORT clk (1087:1087:1087) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1794:1794:1794) (2076:2076:2076)) + (PORT d[1] (1219:1219:1219) (1388:1388:1388)) + (PORT d[2] (937:937:937) (1091:1091:1091)) + (PORT d[3] (881:881:881) (1012:1012:1012)) + (PORT d[4] (1544:1544:1544) (1795:1795:1795)) + (PORT d[5] (899:899:899) (1035:1035:1035)) + (PORT d[6] (867:867:867) (999:999:999)) + (PORT d[7] (1087:1087:1087) (1259:1259:1259)) + (PORT d[8] (1991:1991:1991) (2288:2288:2288)) + (PORT d[9] (846:846:846) (983:983:983)) + (PORT d[10] (968:968:968) (1123:1123:1123)) + (PORT d[11] (1052:1052:1052) (1228:1228:1228)) + (PORT d[12] (974:974:974) (1128:1128:1128)) + (PORT clk (1085:1085:1085) (1103:1103:1103)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (843:843:843) (906:906:906)) + (PORT clk (1085:1085:1085) (1103:1103:1103)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1105:1105:1105)) + (PORT d[0] (1758:1758:1758) (1639:1639:1639)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1106:1106:1106)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1106:1106:1106)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1106:1106:1106)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1106:1106:1106)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1042:1042:1042) (1062:1062:1062)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1013:1013:1013) (1151:1151:1151)) + (PORT clk (1047:1047:1047) (1065:1065:1065)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2513:2513:2513) (2845:2845:2845)) + (PORT d[1] (2464:2464:2464) (2777:2777:2777)) + (PORT d[2] (2478:2478:2478) (2811:2811:2811)) + (PORT d[3] (2418:2418:2418) (2748:2748:2748)) + (PORT d[4] (2440:2440:2440) (2745:2745:2745)) + (PORT d[5] (2489:2489:2489) (2844:2844:2844)) + (PORT d[6] (2482:2482:2482) (2797:2797:2797)) + (PORT d[7] (2475:2475:2475) (2809:2809:2809)) + (PORT d[8] (2516:2516:2516) (2871:2871:2871)) + (PORT d[9] (2535:2535:2535) (2906:2906:2906)) + (PORT d[10] (2539:2539:2539) (2877:2877:2877)) + (PORT d[11] (2523:2523:2523) (2865:2865:2865)) + (PORT d[12] (2439:2439:2439) (2762:2762:2762)) + (PORT clk (1044:1044:1044) (1064:1064:1064)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1065:1065:1065)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1048:1048:1048) (1066:1066:1066)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1048:1048:1048) (1066:1066:1066)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1048:1048:1048) (1066:1066:1066)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1048:1048:1048) (1066:1066:1066)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1043:1043:1043) (1063:1063:1063)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (664:664:664) (753:753:753)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1794:1794:1794) (2077:2077:2077)) + (PORT d[1] (887:887:887) (1017:1017:1017)) + (PORT d[2] (932:932:932) (1085:1085:1085)) + (PORT d[3] (874:874:874) (1005:1005:1005)) + (PORT d[4] (1528:1528:1528) (1772:1772:1772)) + (PORT d[5] (892:892:892) (1027:1027:1027)) + (PORT d[6] (888:888:888) (1030:1030:1030)) + (PORT d[7] (937:937:937) (1093:1093:1093)) + (PORT d[8] (877:877:877) (1011:1011:1011)) + (PORT d[9] (832:832:832) (962:962:962)) + (PORT d[10] (806:806:806) (939:939:939)) + (PORT d[11] (1057:1057:1057) (1232:1232:1232)) + (PORT d[12] (818:818:818) (953:953:953)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (777:777:777) (837:837:837)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (1455:1455:1455) (1578:1578:1578)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1044:1044:1044) (1063:1063:1063)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1024:1024:1024) (1162:1162:1162)) + (PORT clk (1049:1049:1049) (1066:1066:1066)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2513:2513:2513) (2852:2852:2852)) + (PORT d[1] (2455:2455:2455) (2753:2753:2753)) + (PORT d[2] (2498:2498:2498) (2840:2840:2840)) + (PORT d[3] (2429:2429:2429) (2762:2762:2762)) + (PORT d[4] (2454:2454:2454) (2786:2786:2786)) + (PORT d[5] (2473:2473:2473) (2815:2815:2815)) + (PORT d[6] (2464:2464:2464) (2767:2767:2767)) + (PORT d[7] (2472:2472:2472) (2802:2802:2802)) + (PORT d[8] (2496:2496:2496) (2844:2844:2844)) + (PORT d[9] (2502:2502:2502) (2852:2852:2852)) + (PORT d[10] (2558:2558:2558) (2903:2903:2903)) + (PORT d[11] (2528:2528:2528) (2880:2880:2880)) + (PORT d[12] (2434:2434:2434) (2756:2756:2756)) + (PORT clk (1046:1046:1046) (1065:1065:1065)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1066:1066:1066)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1067:1067:1067)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1067:1067:1067)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1067:1067:1067)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1067:1067:1067)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1228:1228:1228) (1431:1431:1431)) + (PORT d[1] (1385:1385:1385) (1574:1574:1574)) + (PORT d[2] (1425:1425:1425) (1650:1650:1650)) + (PORT d[3] (1351:1351:1351) (1538:1538:1538)) + (PORT d[4] (1149:1149:1149) (1336:1336:1336)) + (PORT d[5] (1410:1410:1410) (1611:1611:1611)) + (PORT d[6] (1438:1438:1438) (1657:1657:1657)) + (PORT d[7] (1453:1453:1453) (1675:1675:1675)) + (PORT d[8] (1418:1418:1418) (1627:1627:1627)) + (PORT d[9] (1406:1406:1406) (1619:1619:1619)) + (PORT d[10] (1723:1723:1723) (1984:1984:1984)) + (PORT d[11] (1177:1177:1177) (1361:1361:1361)) + (PORT d[12] (1361:1361:1361) (1566:1566:1566)) + (PORT clk (1100:1100:1100) (1117:1117:1117)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1117:1117:1117)) + (PORT d[0] (1530:1530:1530) (1728:1728:1728)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1101:1101:1101) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1082:1082:1082) (1098:1098:1098)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (622:622:622) (630:630:630)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (623:623:623) (631:631:631)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (623:623:623) (631:631:631)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (623:623:623) (631:631:631)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (672:672:672) (780:780:780)) + (PORT datab (383:383:383) (454:454:454)) + (PORT datac (516:516:516) (584:584:584)) + (PORT datad (667:667:667) (757:757:757)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~97) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) (DELAY (ABSOLUTE - (PORT dataa (478:478:478) (562:562:562)) - (PORT datab (877:877:877) (1025:1025:1025)) - (PORT datac (833:833:833) (962:962:962)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (172:172:172) (163:163:163)) + (PORT d[0] (1239:1239:1239) (1446:1446:1446)) + (PORT d[1] (1395:1395:1395) (1590:1590:1590)) + (PORT d[2] (1493:1493:1493) (1706:1706:1706)) + (PORT d[3] (1743:1743:1743) (1968:1968:1968)) + (PORT d[4] (1109:1109:1109) (1313:1313:1313)) + (PORT d[5] (1957:1957:1957) (2231:2231:2231)) + (PORT d[6] (1605:1605:1605) (1824:1824:1824)) + (PORT d[7] (1907:1907:1907) (2171:2171:2171)) + (PORT d[8] (1191:1191:1191) (1365:1365:1365)) + (PORT d[9] (1773:1773:1773) (2025:2025:2025)) + (PORT d[10] (1307:1307:1307) (1492:1492:1492)) + (PORT d[11] (1405:1405:1405) (1638:1638:1638)) + (PORT d[12] (1913:1913:1913) (2172:2172:2172)) + (PORT clk (1103:1103:1103) (1121:1121:1121)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1121:1121:1121)) + (PORT d[0] (1857:1857:1857) (1662:1662:1662)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1104:1104:1104) (1122:1122:1122)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1102:1102:1102)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (625:625:625) (634:634:634)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (626:626:626) (635:635:635)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (626:626:626) (635:635:635)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (626:626:626) (635:635:635)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~91) + (DELAY + (ABSOLUTE + (PORT dataa (497:497:497) (576:576:576)) + (PORT datab (737:737:737) (854:854:854)) + (PORT datac (95:95:95) (119:119:119)) + (PORT datad (890:890:890) (1007:1007:1007)) + (IOPATH dataa combout (188:188:188) (203:203:203)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -42722,16 +47290,64 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~98) + (INSTANCE D\[4\]\~92) (DELAY (ABSOLUTE - (PORT dataa (642:642:642) (768:768:768)) - (PORT datab (898:898:898) (1028:1028:1028)) - (PORT datac (834:834:834) (963:963:963)) - (PORT datad (90:90:90) (108:108:108)) + (PORT dataa (541:541:541) (619:619:619)) + (PORT datab (380:380:380) (451:451:451)) + (PORT datac (96:96:96) (120:120:120)) + (PORT datad (161:161:161) (187:187:187)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~125) + (DELAY + (ABSOLUTE + (PORT dataa (1450:1450:1450) (1707:1707:1707)) + (PORT datab (756:756:756) (883:883:883)) + (PORT datac (294:294:294) (342:342:342)) + (PORT datad (163:163:163) (192:192:192)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (182:182:182) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~110) + (DELAY + (ABSOLUTE + (PORT dataa (515:515:515) (599:599:599)) + (PORT datab (498:498:498) (576:576:576)) + (PORT datac (96:96:96) (121:121:121)) + (PORT datad (326:326:326) (379:379:379)) (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~111) + (DELAY + (ABSOLUTE + (PORT dataa (1259:1259:1259) (1445:1445:1445)) + (PORT datab (227:227:227) (273:273:273)) + (PORT datac (104:104:104) (126:126:126)) + (PORT datad (702:702:702) (825:825:825)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -42741,11 +47357,11 @@ (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) (DELAY (ABSOLUTE - (PORT dataa (539:539:539) (641:641:641)) - (PORT datab (817:817:817) (925:925:925)) - (PORT datac (126:126:126) (162:162:162)) - (PORT datad (642:642:642) (729:729:729)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (995:995:995) (1153:1153:1153)) + (PORT datab (227:227:227) (268:268:268)) + (PORT datac (280:280:280) (320:320:320)) + (PORT datad (621:621:621) (711:711:711)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -42773,11 +47389,11 @@ (INSTANCE z80_\|bus_control_\|db\[4\]\~18) (DELAY (ABSOLUTE - (PORT dataa (205:205:205) (265:265:265)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datad (356:356:356) (418:418:418)) + (PORT dataa (142:142:142) (193:193:193)) + (PORT datab (218:218:218) (259:259:259)) + (PORT datad (198:198:198) (237:237:237)) (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -42787,13 +47403,13 @@ (INSTANCE z80_\|bus_control_\|db\[4\]\~19) (DELAY (ABSOLUTE - (PORT dataa (540:540:540) (624:624:624)) - (PORT datab (504:504:504) (580:580:580)) - (PORT datac (503:503:503) (577:577:577)) - (PORT datad (492:492:492) (560:560:560)) + (PORT dataa (619:619:619) (717:717:717)) + (PORT datab (172:172:172) (210:210:210)) + (PORT datac (273:273:273) (312:312:312)) + (PORT datad (116:116:116) (140:140:140)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -42803,244 +47419,10 @@ (INSTANCE z80_\|ir_\|opcode\[4\]) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (895:895:895)) - (PORT ena (780:780:780) (849:849:849)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~0) - (DELAY - (ABSOLUTE - (PORT datac (814:814:814) (956:956:956)) - (PORT datad (835:835:835) (972:972:972)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~5) - (DELAY - (ABSOLUTE - (PORT dataa (756:756:756) (873:873:873)) - (PORT datab (538:538:538) (635:635:635)) - (PORT datac (913:913:913) (1096:1096:1096)) - (PORT datad (690:690:690) (800:800:800)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (731:731:731) (854:854:854)) - (PORT datab (861:861:861) (1001:1001:1001)) - (PORT datac (440:440:440) (506:506:506)) - (PORT datad (106:106:106) (124:124:124)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~3) - (DELAY - (ABSOLUTE - (PORT datab (853:853:853) (1003:1003:1003)) - (PORT datac (752:752:752) (882:882:882)) - (PORT datad (1442:1442:1442) (1705:1705:1705)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (465:465:465) (551:551:551)) - (PORT datab (488:488:488) (576:576:576)) - (PORT datac (944:944:944) (1100:1100:1100)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (265:265:265)) - (PORT datab (667:667:667) (778:778:778)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (189:189:189) (221:221:221)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~11) - (DELAY - (ABSOLUTE - (PORT dataa (513:513:513) (594:594:594)) - (PORT datab (340:340:340) (405:405:405)) - (PORT datac (484:484:484) (567:567:567)) - (PORT datad (482:482:482) (551:551:551)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1103:1103:1103) (1266:1266:1266)) - (PORT datab (609:609:609) (706:706:706)) - (PORT datac (460:460:460) (531:531:531)) - (PORT datad (349:349:349) (411:411:411)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~13) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (315:315:315) (367:367:367)) - (PORT datac (278:278:278) (323:323:323)) - (PORT datad (94:94:94) (112:112:112)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~14) - (DELAY - (ABSOLUTE - (PORT dataa (882:882:882) (1032:1032:1032)) - (PORT datab (468:468:468) (544:544:544)) - (PORT datac (835:835:835) (945:945:945)) - (PORT datad (577:577:577) (648:648:648)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~15) - (DELAY - (ABSOLUTE - (PORT dataa (332:332:332) (384:384:384)) - (PORT datab (478:478:478) (556:556:556)) - (PORT datac (459:459:459) (532:532:532)) - (PORT datad (670:670:670) (781:781:781)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (689:689:689) (767:767:767)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (120:120:120) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mwr) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (704:704:704) (789:789:789)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|mwr_wr) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) - (PORT asdata (299:299:299) (341:341:341)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (704:704:704) (789:789:789)) + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (473:473:473) (516:516:516)) + (PORT clrn (917:917:917) (902:902:902)) + (PORT ena (1057:1057:1057) (1164:1164:1164)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -43052,26 +47434,73 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) + (INSTANCE z80_\|pla_decode_\|Equal32\~0) (DELAY (ABSOLUTE - (PORT dataa (459:459:459) (532:532:532)) - (PORT datab (182:182:182) (225:225:225)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT datac (1072:1072:1072) (1238:1238:1238)) + (PORT datad (1443:1443:1443) (1657:1657:1657)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~84) + (INSTANCE z80_\|pla_decode_\|Equal36\~0) (DELAY (ABSOLUTE - (PORT dataa (982:982:982) (1142:1142:1142)) - (PORT datab (897:897:897) (1062:1062:1062)) - (PORT datac (653:653:653) (769:769:769)) - (PORT datad (683:683:683) (799:799:799)) + (PORT dataa (494:494:494) (576:576:576)) + (PORT datab (354:354:354) (415:415:415)) + (PORT datac (1153:1153:1153) (1375:1375:1375)) + (PORT datad (780:780:780) (882:882:882)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (128:128:128) (164:164:164)) + (PORT datab (505:505:505) (584:584:584)) + (PORT datac (962:962:962) (1127:1127:1127)) + (PORT datad (351:351:351) (412:412:412)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (425:425:425)) + (PORT datab (208:208:208) (253:253:253)) + (PORT datac (812:812:812) (950:950:950)) + (PORT datad (188:188:188) (222:222:222)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1281:1281:1281) (1507:1507:1507)) + (PORT datab (900:900:900) (1024:1024:1024)) + (PORT datac (784:784:784) (945:945:945)) + (PORT datad (700:700:700) (796:796:796)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -43080,655 +47509,125 @@ ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) (DELAY (ABSOLUTE - (PORT d[0] (657:657:657) (743:743:743)) - (PORT clk (1094:1094:1094) (1111:1111:1111)) + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (639:639:639) (720:720:720)) + (PORT clrn (925:925:925) (906:906:906)) + (PORT ena (508:508:508) (552:552:552)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2376:2376:2376) (2743:2743:2743)) - (PORT d[1] (1673:1673:1673) (1949:1949:1949)) - (PORT d[2] (1859:1859:1859) (2120:2120:2120)) - (PORT d[3] (1457:1457:1457) (1704:1704:1704)) - (PORT d[4] (1308:1308:1308) (1532:1532:1532)) - (PORT d[5] (1495:1495:1495) (1741:1741:1741)) - (PORT d[6] (1079:1079:1079) (1242:1242:1242)) - (PORT d[7] (1355:1355:1355) (1538:1538:1538)) - (PORT d[8] (1818:1818:1818) (2136:2136:2136)) - (PORT d[9] (1647:1647:1647) (1909:1909:1909)) - (PORT d[10] (2810:2810:2810) (3210:3210:3210)) - (PORT d[11] (1259:1259:1259) (1464:1464:1464)) - (PORT d[12] (1279:1279:1279) (1469:1469:1469)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1104:1104:1104) (1196:1196:1196)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (PORT d[0] (1283:1283:1283) (1376:1376:1376)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1074:1074:1074) (1090:1090:1090)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (614:614:614) (622:622:622)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (623:623:623)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (623:623:623)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (623:623:623)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (667:667:667) (755:755:755)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2370:2370:2370) (2737:2737:2737)) - (PORT d[1] (1682:1682:1682) (1961:1961:1961)) - (PORT d[2] (1599:1599:1599) (1830:1830:1830)) - (PORT d[3] (1456:1456:1456) (1704:1704:1704)) - (PORT d[4] (1317:1317:1317) (1545:1545:1545)) - (PORT d[5] (1481:1481:1481) (1721:1721:1721)) - (PORT d[6] (1111:1111:1111) (1275:1275:1275)) - (PORT d[7] (1341:1341:1341) (1517:1517:1517)) - (PORT d[8] (1821:1821:1821) (2141:2141:2141)) - (PORT d[9] (1479:1479:1479) (1716:1716:1716)) - (PORT d[10] (2803:2803:2803) (3202:3202:3202)) - (PORT d[11] (1087:1087:1087) (1266:1266:1266)) - (PORT d[12] (1288:1288:1288) (1482:1482:1482)) - (PORT clk (1094:1094:1094) (1111:1111:1111)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1335:1335:1335) (1450:1450:1450)) - (PORT clk (1094:1094:1094) (1111:1111:1111)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (PORT d[0] (1595:1595:1595) (1711:1711:1711)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1076:1076:1076) (1092:1092:1092)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (624:624:624)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (490:490:490) (554:554:554)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (756:756:756) (870:870:870)) - (PORT d[1] (1184:1184:1184) (1400:1400:1400)) - (PORT d[2] (1753:1753:1753) (2001:2001:2001)) - (PORT d[3] (1487:1487:1487) (1749:1749:1749)) - (PORT d[4] (1499:1499:1499) (1753:1753:1753)) - (PORT d[5] (1655:1655:1655) (1919:1919:1919)) - (PORT d[6] (1127:1127:1127) (1303:1303:1303)) - (PORT d[7] (1522:1522:1522) (1724:1724:1724)) - (PORT d[8] (1982:1982:1982) (2322:2322:2322)) - (PORT d[9] (1666:1666:1666) (1930:1930:1930)) - (PORT d[10] (2976:2976:2976) (3402:3402:3402)) - (PORT d[11] (1099:1099:1099) (1284:1284:1284)) - (PORT d[12] (1108:1108:1108) (1277:1277:1277)) - (PORT clk (1088:1088:1088) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (692:692:692) (734:734:734)) - (PORT clk (1088:1088:1088) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (PORT d[0] (1395:1395:1395) (1506:1506:1506)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1070:1070:1070) (1087:1087:1087)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~6) + (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) (DELAY (ABSOLUTE - (PORT dataa (785:785:785) (912:912:912)) - (PORT datab (518:518:518) (617:617:617)) - (PORT datac (611:611:611) (694:694:694)) - (PORT datad (462:462:462) (525:525:525)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (190:190:190) (188:188:188)) + (PORT dataa (357:357:357) (435:435:435)) + (PORT datab (497:497:497) (579:579:579)) + (PORT datac (585:585:585) (682:682:682)) + (PORT datad (653:653:653) (759:759:759)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) (DELAY (ABSOLUTE - (PORT d[0] (657:657:657) (752:752:752)) - (PORT clk (1090:1090:1090) (1107:1107:1107)) + (PORT dataa (449:449:449) (525:525:525)) + (PORT datab (621:621:621) (720:720:720)) + (PORT datac (555:555:555) (624:624:624)) + (PORT datad (445:445:445) (514:514:514)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_yf) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (448:448:448)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~15) (DELAY (ABSOLUTE - (PORT d[0] (1900:1900:1900) (2210:2210:2210)) - (PORT d[1] (990:990:990) (1167:1167:1167)) - (PORT d[2] (1735:1735:1735) (1988:1988:1988)) - (PORT d[3] (1232:1232:1232) (1433:1433:1433)) - (PORT d[4] (1437:1437:1437) (1671:1671:1671)) - (PORT d[5] (1395:1395:1395) (1645:1645:1645)) - (PORT d[6] (1220:1220:1220) (1416:1416:1416)) - (PORT d[7] (1434:1434:1434) (1624:1624:1624)) - (PORT d[8] (1748:1748:1748) (2034:2034:2034)) - (PORT d[9] (1434:1434:1434) (1651:1651:1651)) - (PORT d[10] (2203:2203:2203) (2532:2532:2532)) - (PORT d[11] (965:965:965) (1112:1112:1112)) - (PORT d[12] (1353:1353:1353) (1550:1550:1550)) - (PORT clk (1088:1088:1088) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1241:1241:1241) (1352:1352:1352)) - (PORT clk (1088:1088:1088) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (PORT d[0] (1519:1519:1519) (1646:1646:1646)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1070:1070:1070) (1086:1086:1086)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + (PORT dataa (314:314:314) (375:375:375)) + (PORT datab (644:644:644) (744:744:744)) + (PORT datac (351:351:351) (426:426:426)) + (PORT datad (310:310:310) (362:362:362)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) + (INSTANCE z80_\|alu_control_\|db\[5\]\~16) (DELAY (ABSOLUTE - (PORT dataa (782:782:782) (914:914:914)) - (PORT datab (635:635:635) (736:736:736)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (807:807:807) (907:907:907)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT dataa (471:471:471) (566:566:566)) + (PORT datab (323:323:323) (380:380:380)) + (PORT datac (804:804:804) (920:920:920)) + (PORT datad (330:330:330) (385:385:385)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (605:605:605) (698:698:698)) + (PORT datac (460:460:460) (529:529:529)) + (PORT datad (107:107:107) (126:126:126)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (969:969:969) (1123:1123:1123)) + (PORT d[0] (830:830:830) (926:926:926)) (PORT clk (1083:1083:1083) (1102:1102:1102)) ) ) @@ -43738,22 +47637,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1865:1865:1865) (2172:2172:2172)) - (PORT d[1] (1358:1358:1358) (1599:1599:1599)) - (PORT d[2] (1247:1247:1247) (1438:1438:1438)) - (PORT d[3] (1075:1075:1075) (1261:1261:1261)) - (PORT d[4] (1421:1421:1421) (1634:1634:1634)) - (PORT d[5] (1142:1142:1142) (1347:1347:1347)) - (PORT d[6] (807:807:807) (930:930:930)) - (PORT d[7] (834:834:834) (959:959:959)) - (PORT d[8] (1664:1664:1664) (1927:1927:1927)) - (PORT d[9] (1154:1154:1154) (1325:1325:1325)) - (PORT d[10] (1129:1129:1129) (1298:1298:1298)) - (PORT d[11] (789:789:789) (907:907:907)) - (PORT d[12] (1148:1148:1148) (1322:1322:1322)) + (PORT d[0] (1776:1776:1776) (2058:2058:2058)) + (PORT d[1] (1062:1062:1062) (1215:1215:1215)) + (PORT d[2] (960:960:960) (1119:1119:1119)) + (PORT d[3] (1261:1261:1261) (1446:1446:1446)) + (PORT d[4] (1353:1353:1353) (1575:1575:1575)) + (PORT d[5] (1163:1163:1163) (1337:1337:1337)) + (PORT d[6] (1074:1074:1074) (1247:1247:1247)) + (PORT d[7] (1114:1114:1114) (1293:1293:1293)) + (PORT d[8] (1960:1960:1960) (2249:2249:2249)) + (PORT d[9] (1032:1032:1032) (1197:1197:1197)) + (PORT d[10] (2242:2242:2242) (2565:2565:2565)) + (PORT d[11] (1534:1534:1534) (1760:1760:1760)) + (PORT d[12] (1444:1444:1444) (1655:1655:1655)) (PORT clk (1081:1081:1081) (1100:1100:1100)) ) ) @@ -43763,10 +47662,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1601:1601:1601) (1763:1763:1763)) + (PORT d[0] (1307:1307:1307) (1441:1441:1441)) (PORT clk (1081:1081:1081) (1100:1100:1100)) ) ) @@ -43776,17 +47675,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1083:1083:1083) (1102:1102:1102)) - (PORT d[0] (2271:2271:2271) (2510:2510:2510)) + (PORT d[0] (1633:1633:1633) (1777:1777:1777)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1084:1084:1084) (1103:1103:1103)) @@ -43796,7 +47695,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1084:1084:1084) (1103:1103:1103)) @@ -43806,7 +47705,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1084:1084:1084) (1103:1103:1103)) @@ -43816,7 +47715,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1084:1084:1084) (1103:1103:1103)) @@ -43826,7 +47725,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1038:1038:1038) (1059:1059:1059)) @@ -43840,10 +47739,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (654:654:654) (722:722:722)) + (PORT d[0] (1011:1011:1011) (1149:1149:1149)) (PORT clk (1043:1043:1043) (1062:1062:1062)) ) ) @@ -43853,22 +47752,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2436:2436:2436) (2780:2780:2780)) - (PORT d[1] (2375:2375:2375) (2685:2685:2685)) - (PORT d[2] (2392:2392:2392) (2718:2718:2718)) - (PORT d[3] (2528:2528:2528) (2881:2881:2881)) - (PORT d[4] (2391:2391:2391) (2711:2711:2711)) - (PORT d[5] (2412:2412:2412) (2738:2738:2738)) - (PORT d[6] (2618:2618:2618) (2985:2985:2985)) - (PORT d[7] (2437:2437:2437) (2782:2782:2782)) - (PORT d[8] (2483:2483:2483) (2820:2820:2820)) - (PORT d[9] (2692:2692:2692) (3085:3085:3085)) - (PORT d[10] (2446:2446:2446) (2770:2770:2770)) - (PORT d[11] (2402:2402:2402) (2710:2710:2710)) - (PORT d[12] (2596:2596:2596) (2931:2931:2931)) + (PORT d[0] (2450:2450:2450) (2773:2773:2773)) + (PORT d[1] (2425:2425:2425) (2759:2759:2759)) + (PORT d[2] (2450:2450:2450) (2792:2792:2792)) + (PORT d[3] (2397:2397:2397) (2725:2725:2725)) + (PORT d[4] (2481:2481:2481) (2811:2811:2811)) + (PORT d[5] (2487:2487:2487) (2829:2829:2829)) + (PORT d[6] (2432:2432:2432) (2730:2730:2730)) + (PORT d[7] (2467:2467:2467) (2797:2797:2797)) + (PORT d[8] (2458:2458:2458) (2776:2776:2776)) + (PORT d[9] (2504:2504:2504) (2850:2850:2850)) + (PORT d[10] (2495:2495:2495) (2826:2826:2826)) + (PORT d[11] (2542:2542:2542) (2884:2884:2884)) + (PORT d[12] (2379:2379:2379) (2691:2691:2691)) (PORT clk (1040:1040:1040) (1061:1061:1061)) ) ) @@ -43878,7 +47777,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1043:1043:1043) (1062:1062:1062)) @@ -43887,7 +47786,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) (DELAY (ABSOLUTE (PORT clk (1044:1044:1044) (1063:1063:1063)) @@ -43897,7 +47796,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1044:1044:1044) (1063:1063:1063)) @@ -43906,7 +47805,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1044:1044:1044) (1063:1063:1063)) @@ -43916,7 +47815,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1044:1044:1044) (1063:1063:1063)) @@ -43926,23 +47825,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1451:1451:1451) (1655:1655:1655)) - (PORT d[1] (1198:1198:1198) (1420:1420:1420)) - (PORT d[2] (1305:1305:1305) (1527:1527:1527)) - (PORT d[3] (1317:1317:1317) (1517:1517:1517)) - (PORT d[4] (1725:1725:1725) (2024:2024:2024)) - (PORT d[5] (1210:1210:1210) (1433:1433:1433)) - (PORT d[6] (1075:1075:1075) (1227:1227:1227)) - (PORT d[7] (1440:1440:1440) (1645:1645:1645)) - (PORT d[8] (1584:1584:1584) (1869:1869:1869)) - (PORT d[9] (893:893:893) (1030:1030:1030)) - (PORT d[10] (1067:1067:1067) (1215:1215:1215)) - (PORT d[11] (1632:1632:1632) (1870:1870:1870)) - (PORT d[12] (881:881:881) (1013:1013:1013)) - (PORT clk (1103:1103:1103) (1121:1121:1121)) + (PORT d[0] (953:953:953) (1121:1121:1121)) + (PORT d[1] (1588:1588:1588) (1781:1781:1781)) + (PORT d[2] (1506:1506:1506) (1725:1725:1725)) + (PORT d[3] (1439:1439:1439) (1627:1627:1627)) + (PORT d[4] (1363:1363:1363) (1567:1567:1567)) + (PORT d[5] (1649:1649:1649) (1884:1884:1884)) + (PORT d[6] (1613:1613:1613) (1832:1832:1832)) + (PORT d[7] (1832:1832:1832) (2090:2090:2090)) + (PORT d[8] (1309:1309:1309) (1495:1495:1495)) + (PORT d[9] (1795:1795:1795) (2050:2050:2050)) + (PORT d[10] (1317:1317:1317) (1500:1500:1500)) + (PORT d[11] (1431:1431:1431) (1669:1669:1669)) + (PORT d[12] (1737:1737:1737) (1972:1972:1972)) + (PORT clk (1106:1106:1106) (1123:1123:1123)) ) ) (TIMINGCHECK @@ -43951,30 +47850,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1103:1103:1103) (1121:1121:1121)) - (PORT d[0] (1263:1263:1263) (1416:1416:1416)) + (PORT clk (1106:1106:1106) (1123:1123:1123)) + (PORT d[0] (1682:1682:1682) (1879:1879:1879)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1104:1104:1104) (1122:1122:1122)) + (PORT clk (1107:1107:1107) (1124:1124:1124)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1085:1085:1085) (1102:1102:1102)) + (PORT clk (1088:1088:1088) (1104:1104:1104)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -43985,60 +47884,418 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (625:625:625) (634:634:634)) + (PORT clk (628:628:628) (636:636:636)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (626:626:626) (635:635:635)) + (PORT clk (629:629:629) (637:637:637)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (626:626:626) (635:635:635)) + (PORT clk (629:629:629) (637:637:637)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (626:626:626) (635:635:635)) + (PORT clk (629:629:629) (637:637:637)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2011:2011:2011) (2313:2313:2313)) - (PORT d[1] (987:987:987) (1165:1165:1165)) - (PORT d[2] (1558:1558:1558) (1787:1787:1787)) - (PORT d[3] (1194:1194:1194) (1385:1385:1385)) - (PORT d[4] (1098:1098:1098) (1286:1286:1286)) - (PORT d[5] (1372:1372:1372) (1616:1616:1616)) - (PORT d[6] (1346:1346:1346) (1556:1556:1556)) - (PORT d[7] (1416:1416:1416) (1605:1605:1605)) - (PORT d[8] (1556:1556:1556) (1811:1811:1811)) - (PORT d[9] (1412:1412:1412) (1625:1625:1625)) - (PORT d[10] (2235:2235:2235) (2571:2571:2571)) - (PORT d[11] (1016:1016:1016) (1179:1179:1179)) - (PORT d[12] (1382:1382:1382) (1587:1587:1587)) + (PORT d[0] (785:785:785) (881:881:881)) + (PORT clk (1089:1089:1089) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1103:1103:1103) (1297:1297:1297)) + (PORT d[1] (1760:1760:1760) (2007:2007:2007)) + (PORT d[2] (1018:1018:1018) (1168:1168:1168)) + (PORT d[3] (2095:2095:2095) (2370:2370:2370)) + (PORT d[4] (1509:1509:1509) (1776:1776:1776)) + (PORT d[5] (2332:2332:2332) (2661:2661:2661)) + (PORT d[6] (1309:1309:1309) (1494:1494:1494)) + (PORT d[7] (2117:2117:2117) (2413:2413:2413)) + (PORT d[8] (1064:1064:1064) (1252:1252:1252)) + (PORT d[9] (1422:1422:1422) (1624:1624:1624)) + (PORT d[10] (1515:1515:1515) (1727:1727:1727)) + (PORT d[11] (1593:1593:1593) (1867:1867:1867)) + (PORT d[12] (2530:2530:2530) (2863:2863:2863)) + (PORT clk (1087:1087:1087) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1802:1802:1802) (1970:1970:1970)) + (PORT clk (1087:1087:1087) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1107:1107:1107)) + (PORT d[0] (1950:1950:1950) (1820:1820:1820)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1044:1044:1044) (1064:1064:1064)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1194:1194:1194) (1331:1331:1331)) + (PORT clk (1049:1049:1049) (1067:1067:1067)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2452:2452:2452) (2779:2779:2779)) + (PORT d[1] (2493:2493:2493) (2817:2817:2817)) + (PORT d[2] (2441:2441:2441) (2771:2771:2771)) + (PORT d[3] (2429:2429:2429) (2742:2742:2742)) + (PORT d[4] (2401:2401:2401) (2731:2731:2731)) + (PORT d[5] (2450:2450:2450) (2769:2769:2769)) + (PORT d[6] (2440:2440:2440) (2740:2740:2740)) + (PORT d[7] (2336:2336:2336) (2624:2624:2624)) + (PORT d[8] (2481:2481:2481) (2800:2800:2800)) + (PORT d[9] (2543:2543:2543) (2882:2882:2882)) + (PORT d[10] (2375:2375:2375) (2669:2669:2669)) + (PORT d[11] (2459:2459:2459) (2799:2799:2799)) + (PORT d[12] (2337:2337:2337) (2636:2636:2636)) + (PORT clk (1046:1046:1046) (1066:1066:1066)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1067:1067:1067)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1068:1068:1068)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1068:1068:1068)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1068:1068:1068)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1068:1068:1068)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1045:1045:1045) (1065:1065:1065)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (986:986:986) (1169:1169:1169)) + (PORT d[1] (787:787:787) (890:890:890)) + (PORT d[2] (1313:1313:1313) (1526:1526:1526)) + (PORT d[3] (956:956:956) (1091:1091:1091)) + (PORT d[4] (1386:1386:1386) (1605:1605:1605)) + (PORT d[5] (1595:1595:1595) (1812:1812:1812)) + (PORT d[6] (1115:1115:1115) (1271:1271:1271)) + (PORT d[7] (957:957:957) (1081:1081:1081)) + (PORT d[8] (1223:1223:1223) (1429:1429:1429)) + (PORT d[9] (974:974:974) (1103:1103:1103)) + (PORT d[10] (1434:1434:1434) (1618:1618:1618)) + (PORT d[11] (2347:2347:2347) (2730:2730:2730)) + (PORT d[12] (777:777:777) (874:874:874)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT d[0] (1305:1305:1305) (1190:1190:1190)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (672:672:672) (780:780:780)) + (PORT datab (384:384:384) (455:455:455)) + (PORT datac (761:761:761) (868:868:868)) + (PORT datad (917:917:917) (1057:1057:1057)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (773:773:773)) + (PORT datab (381:381:381) (451:451:451)) + (PORT datac (1038:1038:1038) (1187:1187:1187)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (714:714:714) (826:826:826)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1332:1332:1332) (1566:1566:1566)) + (PORT d[1] (1292:1292:1292) (1461:1461:1461)) + (PORT d[2] (1060:1060:1060) (1218:1218:1218)) + (PORT d[3] (1424:1424:1424) (1625:1625:1625)) + (PORT d[4] (1157:1157:1157) (1327:1327:1327)) + (PORT d[5] (897:897:897) (1031:1031:1031)) + (PORT d[6] (983:983:983) (1120:1120:1120)) + (PORT d[7] (1347:1347:1347) (1557:1557:1557)) + (PORT d[8] (1406:1406:1406) (1654:1654:1654)) + (PORT d[9] (708:708:708) (811:811:811)) + (PORT d[10] (927:927:927) (1052:1052:1052)) + (PORT d[11] (653:653:653) (747:747:747)) + (PORT d[12] (591:591:591) (680:680:680)) (PORT clk (1090:1090:1090) (1107:1107:1107)) ) ) @@ -44048,27 +48305,70 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) (DELAY (ABSOLUTE + (PORT d[0] (877:877:877) (948:948:948)) (PORT clk (1090:1090:1090) (1107:1107:1107)) - (PORT d[0] (1590:1590:1590) (1427:1427:1427)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (PORT d[0] (1122:1122:1122) (1200:1200:1200)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1072:1072:1072) (1088:1088:1088)) @@ -44082,7 +48382,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (612:612:612) (620:620:620)) @@ -44091,7 +48391,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) (DELAY (ABSOLUTE (PORT clk (613:613:613) (621:621:621)) @@ -44100,7 +48400,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (613:613:613) (621:621:621)) @@ -44110,7 +48410,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (613:613:613) (621:621:621)) @@ -44120,10 +48420,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (936:936:936) (1083:1083:1083)) + (PORT d[0] (639:639:639) (714:714:714)) (PORT clk (1097:1097:1097) (1114:1114:1114)) ) ) @@ -44133,22 +48433,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1645:1645:1645) (1877:1877:1877)) - (PORT d[1] (1382:1382:1382) (1630:1630:1630)) - (PORT d[2] (1485:1485:1485) (1730:1730:1730)) - (PORT d[3] (1144:1144:1144) (1334:1334:1334)) - (PORT d[4] (1707:1707:1707) (2004:2004:2004)) - (PORT d[5] (1389:1389:1389) (1638:1638:1638)) - (PORT d[6] (1065:1065:1065) (1219:1219:1219)) - (PORT d[7] (939:939:939) (1085:1085:1085)) - (PORT d[8] (1741:1741:1741) (2030:2030:2030)) - (PORT d[9] (699:699:699) (802:802:802)) - (PORT d[10] (1255:1255:1255) (1430:1430:1430)) - (PORT d[11] (2096:2096:2096) (2391:2391:2391)) - (PORT d[12] (1086:1086:1086) (1248:1248:1248)) + (PORT d[0] (1708:1708:1708) (1990:1990:1990)) + (PORT d[1] (1930:1930:1930) (2206:2206:2206)) + (PORT d[2] (1111:1111:1111) (1275:1275:1275)) + (PORT d[3] (2312:2312:2312) (2621:2621:2621)) + (PORT d[4] (1679:1679:1679) (1964:1964:1964)) + (PORT d[5] (2543:2543:2543) (2907:2907:2907)) + (PORT d[6] (1268:1268:1268) (1439:1439:1439)) + (PORT d[7] (973:973:973) (1104:1104:1104)) + (PORT d[8] (1803:1803:1803) (2097:2097:2097)) + (PORT d[9] (1062:1062:1062) (1215:1215:1215)) + (PORT d[10] (1165:1165:1165) (1326:1326:1326)) + (PORT d[11] (1786:1786:1786) (2092:2092:2092)) + (PORT d[12] (2544:2544:2544) (2884:2884:2884)) (PORT clk (1095:1095:1095) (1112:1112:1112)) ) ) @@ -44158,10 +48458,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1554:1554:1554) (1710:1710:1710)) + (PORT d[0] (895:895:895) (956:956:956)) (PORT clk (1095:1095:1095) (1112:1112:1112)) ) ) @@ -44171,17 +48471,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1097:1097:1097) (1114:1114:1114)) - (PORT d[0] (1889:1889:1889) (1754:1754:1754)) + (PORT d[0] (1405:1405:1405) (1513:1513:1513)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1098:1098:1098) (1115:1115:1115)) @@ -44191,7 +48491,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1098:1098:1098) (1115:1115:1115)) @@ -44201,7 +48501,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1098:1098:1098) (1115:1115:1115)) @@ -44211,7 +48511,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1098:1098:1098) (1115:1115:1115)) @@ -44221,10 +48521,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1052:1052:1052) (1071:1071:1071)) + (PORT clk (1077:1077:1077) (1093:1093:1093)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -44235,98 +48535,150 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (1217:1217:1217) (1382:1382:1382)) - (PORT clk (1057:1057:1057) (1074:1074:1074)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2540:2540:2540) (2882:2882:2882)) - (PORT d[1] (2318:2318:2318) (2609:2609:2609)) - (PORT d[2] (2339:2339:2339) (2654:2654:2654)) - (PORT d[3] (2599:2599:2599) (2954:2954:2954)) - (PORT d[4] (2392:2392:2392) (2719:2719:2719)) - (PORT d[5] (2428:2428:2428) (2730:2730:2730)) - (PORT d[6] (2583:2583:2583) (2943:2943:2943)) - (PORT d[7] (2268:2268:2268) (2562:2562:2562)) - (PORT d[8] (2620:2620:2620) (2939:2939:2939)) - (PORT d[9] (2601:2601:2601) (2982:2982:2982)) - (PORT d[10] (2462:2462:2462) (2771:2771:2771)) - (PORT d[11] (2504:2504:2504) (2828:2828:2828)) - (PORT d[12] (2488:2488:2488) (2807:2807:2807)) - (PORT clk (1054:1054:1054) (1073:1073:1073)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1074:1074:1074)) + (PORT clk (617:617:617) (625:625:625)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (797:797:797) (892:892:892)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1310:1310:1310) (1528:1528:1528)) + (PORT d[1] (627:627:627) (710:710:710)) + (PORT d[2] (1532:1532:1532) (1755:1755:1755)) + (PORT d[3] (2695:2695:2695) (3058:3058:3058)) + (PORT d[4] (546:546:546) (625:625:625)) + (PORT d[5] (917:917:917) (1038:1038:1038)) + (PORT d[6] (801:801:801) (916:916:916)) + (PORT d[7] (785:785:785) (884:884:884)) + (PORT d[8] (1419:1419:1419) (1654:1654:1654)) + (PORT d[9] (639:639:639) (718:718:718)) + (PORT d[10] (1157:1157:1157) (1313:1313:1313)) + (PORT d[11] (2168:2168:2168) (2530:2530:2530)) + (PORT d[12] (1410:1410:1410) (1588:1588:1588)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1619:1619:1619) (1765:1765:1765)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (PORT d[0] (1045:1045:1045) (1103:1103:1103)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1053:1053:1053) (1072:1072:1072)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + (PORT clk (1072:1072:1072) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) (TIMINGCHECK @@ -44335,92 +48687,271 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~0) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) (DELAY (ABSOLUTE - (PORT dataa (798:798:798) (926:926:926)) - (PORT datab (532:532:532) (633:633:633)) - (PORT datac (791:791:791) (901:901:901)) - (PORT datad (781:781:781) (900:900:900)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT clk (612:612:612) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~1) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~0) (DELAY (ABSOLUTE - (PORT dataa (841:841:841) (994:994:994)) - (PORT datab (530:530:530) (632:632:632)) - (PORT datac (833:833:833) (959:959:959)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~112) - (DELAY - (ABSOLUTE - (PORT dataa (826:826:826) (971:971:971)) - (PORT datab (666:666:666) (787:787:787)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (181:181:181) (175:175:175)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~94) - (DELAY - (ABSOLUTE - (PORT dataa (745:745:745) (854:854:854)) - (PORT datab (484:484:484) (576:576:576)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (729:729:729) (831:831:831)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~102) - (DELAY - (ABSOLUTE - (PORT datac (100:100:100) (121:121:121)) - (PORT datad (430:430:430) (487:487:487)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) - (DELAY - (ABSOLUTE - (PORT dataa (532:532:532) (616:616:616)) - (PORT datab (121:121:121) (152:152:152)) - (PORT datac (125:125:125) (161:161:161)) - (PORT datad (480:480:480) (551:551:551)) + (PORT dataa (460:460:460) (529:529:529)) + (PORT datab (683:683:683) (805:805:805)) + (PORT datac (807:807:807) (934:934:934)) + (PORT datad (797:797:797) (914:914:914)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (804:804:804) (912:912:912)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (971:971:971) (1147:1147:1147)) + (PORT d[1] (1250:1250:1250) (1411:1411:1411)) + (PORT d[2] (1323:1323:1323) (1541:1541:1541)) + (PORT d[3] (969:969:969) (1096:1096:1096)) + (PORT d[4] (1373:1373:1373) (1590:1590:1590)) + (PORT d[5] (1604:1604:1604) (1824:1824:1824)) + (PORT d[6] (1139:1139:1139) (1301:1301:1301)) + (PORT d[7] (976:976:976) (1105:1105:1105)) + (PORT d[8] (1209:1209:1209) (1408:1408:1408)) + (PORT d[9] (1122:1122:1122) (1267:1267:1267)) + (PORT d[10] (1260:1260:1260) (1423:1423:1423)) + (PORT d[11] (2508:2508:2508) (2913:2913:2913)) + (PORT d[12] (1250:1250:1250) (1413:1413:1413)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1074:1074:1074) (1193:1193:1193)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (PORT d[0] (1045:1045:1045) (1097:1097:1097)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1074:1074:1074) (1090:1090:1090)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (614:614:614) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (623:623:623)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (623:623:623)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (623:623:623)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (769:769:769)) + (PORT datab (948:948:948) (1103:1103:1103)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (968:968:968) (1109:1109:1109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~112) + (DELAY + (ABSOLUTE + (PORT dataa (964:964:964) (1108:1108:1108)) + (PORT datab (355:355:355) (414:414:414)) + (PORT datac (333:333:333) (386:386:386)) + (PORT datad (162:162:162) (192:192:192)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~113) + (DELAY + (ABSOLUTE + (PORT dataa (1401:1401:1401) (1599:1599:1599)) + (PORT datab (369:369:369) (434:434:434)) + (PORT datac (103:103:103) (125:125:125)) + (PORT datad (668:668:668) (770:770:770)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (414:414:414)) + (PORT datab (634:634:634) (733:733:733)) + (PORT datac (118:118:118) (141:141:141)) + (PORT datad (857:857:857) (964:964:964)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -44428,7 +48959,7 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[7\]) + (INSTANCE z80_\|data_pins_\|dout\[5\]) (DELAY (ABSOLUTE (PORT clk (916:916:916) (903:903:903)) @@ -44444,2157 +48975,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~5) + (INSTANCE z80_\|bus_control_\|db\[5\]\~14) (DELAY (ABSOLUTE - (PORT datab (638:638:638) (735:735:735)) - (PORT datac (527:527:527) (622:622:622)) - (PORT datad (193:193:193) (224:224:224)) + (PORT datab (222:222:222) (275:275:275)) + (PORT datac (117:117:117) (145:145:145)) + (PORT datad (120:120:120) (144:144:144)) (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~7) + (INSTANCE z80_\|bus_control_\|db\[5\]\~15) (DELAY (ABSOLUTE - (PORT dataa (145:145:145) (197:197:197)) - (PORT datab (377:377:377) (445:445:445)) - (PORT datac (457:457:457) (523:523:523)) - (PORT datad (89:89:89) (107:107:107)) + (PORT dataa (461:461:461) (528:528:528)) + (PORT datab (313:313:313) (365:365:365)) + (PORT datac (277:277:277) (316:316:316)) + (PORT datad (599:599:599) (688:688:688)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[7\]) + (INSTANCE z80_\|ir_\|opcode\[5\]) (DELAY (ABSOLUTE (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (285:285:285) (306:306:306)) - (PORT clrn (918:918:918) (903:903:903)) - (PORT ena (800:800:800) (873:873:873)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~0) - (DELAY - (ABSOLUTE - (PORT dataa (394:394:394) (483:483:483)) - (PORT datab (684:684:684) (818:818:818)) - (PORT datac (539:539:539) (638:638:638)) - (PORT datad (758:758:758) (907:907:907)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (389:389:389) (463:463:463)) - (PORT datab (553:553:553) (661:661:661)) - (PORT datac (624:624:624) (727:727:727)) - (PORT datad (648:648:648) (766:766:766)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (398:398:398) (470:470:470)) - (PORT datab (197:197:197) (244:244:244)) - (PORT datac (595:595:595) (689:689:689)) - (PORT datad (962:962:962) (1116:1116:1116)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (542:542:542) (628:628:628)) - (PORT datab (625:625:625) (719:719:719)) - (PORT datac (611:611:611) (714:714:714)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (965:965:965) (1112:1112:1112)) - (PORT datab (590:590:590) (722:722:722)) - (PORT datac (677:677:677) (795:795:795)) - (PORT datad (620:620:620) (714:714:714)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (962:962:962) (1108:1108:1108)) - (PORT datab (197:197:197) (244:244:244)) - (PORT datac (865:865:865) (1010:1010:1010)) - (PORT datad (607:607:607) (695:695:695)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (124:124:124) (158:158:158)) - (PORT datab (585:585:585) (684:684:684)) - (PORT datac (601:601:601) (700:700:700)) - (PORT datad (605:605:605) (686:686:686)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (476:476:476) (551:551:551)) - (PORT datab (821:821:821) (960:960:960)) - (PORT datac (435:435:435) (510:510:510)) - (PORT datad (467:467:467) (542:542:542)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (102:102:102) (129:129:129)) - (PORT datac (88:88:88) (110:110:110)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~50) - (DELAY - (ABSOLUTE - (PORT datac (600:600:600) (730:730:730)) - (PORT datad (576:576:576) (691:691:691)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (250:250:250)) - (PORT datab (524:524:524) (628:628:628)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (158:158:158)) - (PORT datab (424:424:424) (522:522:522)) - (PORT datac (757:757:757) (913:913:913)) - (PORT datad (864:864:864) (1018:1018:1018)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (178:178:178) (219:219:219)) - (PORT datab (116:116:116) (144:144:144)) - (PORT datad (406:406:406) (496:496:496)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1321:1321:1321) (1555:1555:1555)) - (PORT datab (129:129:129) (177:177:177)) - (PORT datac (303:303:303) (362:362:362)) - (PORT datad (707:707:707) (810:810:810)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~57) - (DELAY - (ABSOLUTE - (PORT datab (521:521:521) (629:629:629)) - (PORT datad (414:414:414) (506:506:506)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (342:342:342) (405:405:405)) - (PORT datad (525:525:525) (620:620:620)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (329:329:329)) - (PORT datab (353:353:353) (428:428:428)) - (PORT datac (321:321:321) (387:387:387)) - (PORT datad (398:398:398) (474:474:474)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~131) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (308:308:308)) - (PORT datab (176:176:176) (216:216:216)) - (PORT datad (141:141:141) (183:183:183)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (548:548:548)) - (PORT datab (575:575:575) (662:662:662)) - (PORT datad (336:336:336) (383:383:383)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (737:737:737)) - (PORT datab (129:129:129) (177:177:177)) - (PORT datac (298:298:298) (357:357:357)) - (PORT datad (293:293:293) (342:342:342)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~53) - (DELAY - (ABSOLUTE - (PORT datac (601:601:601) (730:730:730)) - (PORT datad (575:575:575) (689:689:689)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (122:122:122) (161:161:161)) - (PORT datab (199:199:199) (234:234:234)) - (PORT datac (489:489:489) (592:592:592)) - (PORT datad (169:169:169) (198:198:198)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~56) - (DELAY - (ABSOLUTE - (PORT datab (527:527:527) (632:632:632)) - (PORT datad (172:172:172) (203:203:203)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (252:252:252)) - (PORT datab (528:528:528) (632:632:632)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (132:132:132) (183:183:183)) - (PORT datab (131:131:131) (180:180:180)) - (PORT datac (296:296:296) (342:342:342)) - (PORT datad (291:291:291) (332:332:332)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (523:523:523) (627:627:627)) - (PORT datab (445:445:445) (548:548:548)) - (PORT datac (498:498:498) (598:598:598)) - (PORT datad (422:422:422) (528:528:528)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (226:226:226)) - (PORT datab (397:397:397) (494:494:494)) - (PORT datad (311:311:311) (362:362:362)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (114:114:114) (150:150:150)) - (PORT datab (106:106:106) (135:135:135)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (190:190:190) (195:195:195)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) - (DELAY - (ABSOLUTE - (PORT datac (134:134:134) (177:177:177)) - (PORT datad (440:440:440) (513:513:513)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (450:450:450)) - (PORT datab (179:179:179) (219:219:219)) - (PORT datac (346:346:346) (420:420:420)) - (PORT datad (340:340:340) (404:404:404)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (111:111:111) (145:145:145)) - (PORT datab (248:248:248) (310:310:310)) - (PORT datac (188:188:188) (220:220:220)) - (PORT datad (104:104:104) (127:127:127)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (486:486:486)) - (PORT datab (269:269:269) (336:336:336)) - (PORT datac (300:300:300) (353:353:353)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (411:411:411) (507:507:507)) - (PORT datab (428:428:428) (525:525:525)) - (PORT datad (523:523:523) (618:618:618)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (174:174:174) (211:211:211)) - (PORT datad (344:344:344) (402:402:402)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (1056:1056:1056)) - (PORT datab (322:322:322) (390:390:390)) - (PORT datac (601:601:601) (690:690:690)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (339:339:339) (397:397:397)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (312:312:312) (363:363:363)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~104) - (DELAY - (ABSOLUTE - (PORT datab (674:674:674) (795:795:795)) - (PORT datac (364:364:364) (433:433:433)) - (PORT datad (776:776:776) (881:881:881)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (515:515:515) (582:582:582)) - (PORT clk (1087:1087:1087) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (756:756:756) (869:869:869)) - (PORT d[1] (1131:1131:1131) (1346:1346:1346)) - (PORT d[2] (1781:1781:1781) (2038:2038:2038)) - (PORT d[3] (1638:1638:1638) (1913:1913:1913)) - (PORT d[4] (1489:1489:1489) (1740:1740:1740)) - (PORT d[5] (1662:1662:1662) (1928:1928:1928)) - (PORT d[6] (1114:1114:1114) (1285:1285:1285)) - (PORT d[7] (1518:1518:1518) (1718:1718:1718)) - (PORT d[8] (1996:1996:1996) (2341:2341:2341)) - (PORT d[9] (919:919:919) (1060:1060:1060)) - (PORT d[10] (2974:2974:2974) (3396:3396:3396)) - (PORT d[11] (1099:1099:1099) (1281:1281:1281)) - (PORT d[12] (1107:1107:1107) (1276:1276:1276)) - (PORT clk (1085:1085:1085) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (686:686:686) (730:730:730)) - (PORT clk (1085:1085:1085) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1106:1106:1106)) - (PORT d[0] (1382:1382:1382) (1484:1484:1484)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1067:1067:1067) (1085:1085:1085)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (607:607:607) (617:617:617)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (618:618:618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (618:618:618)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (618:618:618)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (383:383:383) (431:431:431)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (701:701:701) (805:805:805)) - (PORT d[1] (1229:1229:1229) (1458:1458:1458)) - (PORT d[2] (713:713:713) (805:805:805)) - (PORT d[3] (726:726:726) (840:840:840)) - (PORT d[4] (1534:1534:1534) (1791:1791:1791)) - (PORT d[5] (2015:2015:2015) (2334:2334:2334)) - (PORT d[6] (770:770:770) (891:891:891)) - (PORT d[7] (1699:1699:1699) (1922:1922:1922)) - (PORT d[8] (552:552:552) (633:633:633)) - (PORT d[9] (736:736:736) (855:855:855)) - (PORT d[10] (789:789:789) (910:910:910)) - (PORT d[11] (1418:1418:1418) (1644:1644:1644)) - (PORT d[12] (926:926:926) (1070:1070:1070)) - (PORT clk (1094:1094:1094) (1111:1111:1111)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (534:534:534) (564:564:564)) - (PORT clk (1094:1094:1094) (1111:1111:1111)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (PORT d[0] (811:811:811) (848:848:848)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1076:1076:1076) (1092:1092:1092)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (624:624:624)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (515:515:515) (584:584:584)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (758:758:758) (875:875:875)) - (PORT d[1] (1852:1852:1852) (2153:2153:2153)) - (PORT d[2] (2023:2023:2023) (2302:2302:2302)) - (PORT d[3] (1638:1638:1638) (1914:1914:1914)) - (PORT d[4] (1483:1483:1483) (1743:1743:1743)) - (PORT d[5] (1676:1676:1676) (1948:1948:1948)) - (PORT d[6] (967:967:967) (1121:1121:1121)) - (PORT d[7] (864:864:864) (987:987:987)) - (PORT d[8] (2007:2007:2007) (2356:2356:2356)) - (PORT d[9] (1837:1837:1837) (2124:2124:2124)) - (PORT d[10] (2979:2979:2979) (3401:3401:3401)) - (PORT d[11] (1122:1122:1122) (1311:1311:1311)) - (PORT d[12] (1098:1098:1098) (1263:1263:1263)) - (PORT clk (1088:1088:1088) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (944:944:944) (1020:1020:1020)) - (PORT clk (1088:1088:1088) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (PORT d[0] (1118:1118:1118) (1193:1193:1193)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1070:1070:1070) (1087:1087:1087)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (619:619:619) (707:707:707)) - (PORT clk (1090:1090:1090) (1107:1107:1107)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2084:2084:2084) (2418:2418:2418)) - (PORT d[1] (974:974:974) (1149:1149:1149)) - (PORT d[2] (1121:1121:1121) (1283:1283:1283)) - (PORT d[3] (1195:1195:1195) (1397:1397:1397)) - (PORT d[4] (1263:1263:1263) (1466:1466:1466)) - (PORT d[5] (793:793:793) (940:940:940)) - (PORT d[6] (850:850:850) (989:989:989)) - (PORT d[7] (1005:1005:1005) (1152:1152:1152)) - (PORT d[8] (2103:2103:2103) (2435:2435:2435)) - (PORT d[9] (1804:1804:1804) (2075:2075:2075)) - (PORT d[10] (1840:1840:1840) (2114:2114:2114)) - (PORT d[11] (1182:1182:1182) (1363:1363:1363)) - (PORT d[12] (815:815:815) (935:935:935)) - (PORT clk (1088:1088:1088) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (914:914:914) (988:988:988)) - (PORT clk (1088:1088:1088) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (PORT d[0] (1497:1497:1497) (1612:1612:1612)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1070:1070:1070) (1086:1086:1086)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (531:531:531) (623:623:623)) - (PORT datab (629:629:629) (737:737:737)) - (PORT datac (452:452:452) (516:516:516)) - (PORT datad (577:577:577) (637:637:637)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (711:711:711)) - (PORT datab (899:899:899) (1055:1055:1055)) - (PORT datac (625:625:625) (722:722:722)) - (PORT datad (160:160:160) (186:186:186)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1711:1711:1711) (1985:1985:1985)) - (PORT d[1] (1692:1692:1692) (1969:1969:1969)) - (PORT d[2] (951:951:951) (1114:1114:1114)) - (PORT d[3] (838:838:838) (978:978:978)) - (PORT d[4] (1077:1077:1077) (1247:1247:1247)) - (PORT d[5] (774:774:774) (919:919:919)) - (PORT d[6] (631:631:631) (730:730:730)) - (PORT d[7] (846:846:846) (976:976:976)) - (PORT d[8] (1434:1434:1434) (1682:1682:1682)) - (PORT d[9] (2200:2200:2200) (2538:2538:2538)) - (PORT d[10] (1484:1484:1484) (1701:1701:1701)) - (PORT d[11] (1006:1006:1006) (1165:1165:1165)) - (PORT d[12] (1141:1141:1141) (1316:1316:1316)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1106:1106:1106)) - (PORT d[0] (720:720:720) (792:792:792)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1071:1071:1071) (1087:1087:1087)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (908:908:908) (1039:1039:1039)) - (PORT clk (1102:1102:1102) (1119:1119:1119)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1462:1462:1462) (1666:1666:1666)) - (PORT d[1] (1206:1206:1206) (1428:1428:1428)) - (PORT d[2] (1461:1461:1461) (1705:1705:1705)) - (PORT d[3] (1294:1294:1294) (1499:1499:1499)) - (PORT d[4] (1739:1739:1739) (2032:2032:2032)) - (PORT d[5] (1231:1231:1231) (1457:1457:1457)) - (PORT d[6] (916:916:916) (1046:1046:1046)) - (PORT d[7] (1592:1592:1592) (1814:1814:1814)) - (PORT d[8] (1611:1611:1611) (1895:1895:1895)) - (PORT d[9] (1199:1199:1199) (1367:1367:1367)) - (PORT d[10] (1075:1075:1075) (1225:1225:1225)) - (PORT d[11] (2079:2079:2079) (2374:2374:2374)) - (PORT d[12] (1066:1066:1066) (1228:1228:1228)) - (PORT clk (1100:1100:1100) (1117:1117:1117)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1776:1776:1776) (1945:1945:1945)) - (PORT clk (1100:1100:1100) (1117:1117:1117)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1102:1102:1102) (1119:1119:1119)) - (PORT d[0] (1621:1621:1621) (1764:1764:1764)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1103:1103:1103) (1120:1120:1120)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1103:1103:1103) (1120:1120:1120)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1103:1103:1103) (1120:1120:1120)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1103:1103:1103) (1120:1120:1120)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1076:1076:1076)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1215:1215:1215) (1378:1378:1378)) - (PORT clk (1062:1062:1062) (1079:1079:1079)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2485:2485:2485) (2804:2804:2804)) - (PORT d[1] (2412:2412:2412) (2731:2731:2731)) - (PORT d[2] (2546:2546:2546) (2889:2889:2889)) - (PORT d[3] (2481:2481:2481) (2823:2823:2823)) - (PORT d[4] (2356:2356:2356) (2667:2667:2667)) - (PORT d[5] (2416:2416:2416) (2742:2742:2742)) - (PORT d[6] (2567:2567:2567) (2926:2926:2926)) - (PORT d[7] (2254:2254:2254) (2544:2544:2544)) - (PORT d[8] (2452:2452:2452) (2774:2774:2774)) - (PORT d[9] (2619:2619:2619) (3004:3004:3004)) - (PORT d[10] (2502:2502:2502) (2822:2822:2822)) - (PORT d[11] (2565:2565:2565) (2889:2889:2889)) - (PORT d[12] (2495:2495:2495) (2818:2818:2818)) - (PORT clk (1059:1059:1059) (1078:1078:1078)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1062:1062:1062) (1079:1079:1079)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1063:1063:1063) (1080:1080:1080)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1063:1063:1063) (1080:1080:1080)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1063:1063:1063) (1080:1080:1080)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1063:1063:1063) (1080:1080:1080)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (738:738:738) (852:852:852)) - (PORT datab (151:151:151) (204:204:204)) - (PORT datac (754:754:754) (847:847:847)) - (PORT datad (835:835:835) (953:953:953)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (892:892:892) (1016:1016:1016)) - (PORT clk (1106:1106:1106) (1124:1124:1124)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1300:1300:1300) (1471:1471:1471)) - (PORT d[1] (1184:1184:1184) (1402:1402:1402)) - (PORT d[2] (1329:1329:1329) (1558:1558:1558)) - (PORT d[3] (1296:1296:1296) (1525:1525:1525)) - (PORT d[4] (1717:1717:1717) (2015:2015:2015)) - (PORT d[5] (1375:1375:1375) (1630:1630:1630)) - (PORT d[6] (1087:1087:1087) (1239:1239:1239)) - (PORT d[7] (1420:1420:1420) (1618:1618:1618)) - (PORT d[8] (1816:1816:1816) (2139:2139:2139)) - (PORT d[9] (1026:1026:1026) (1177:1177:1177)) - (PORT d[10] (1040:1040:1040) (1180:1180:1180)) - (PORT d[11] (1650:1650:1650) (1901:1901:1901)) - (PORT d[12] (1068:1068:1068) (1234:1234:1234)) - (PORT clk (1104:1104:1104) (1122:1122:1122)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1222:1222:1222) (1331:1331:1331)) - (PORT clk (1104:1104:1104) (1122:1122:1122)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1124:1124:1124)) - (PORT d[0] (1921:1921:1921) (1784:1784:1784)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1107:1107:1107) (1125:1125:1125)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1107:1107:1107) (1125:1125:1125)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1107:1107:1107) (1125:1125:1125)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1107:1107:1107) (1125:1125:1125)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1061:1061:1061) (1081:1081:1081)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1396:1396:1396) (1583:1583:1583)) - (PORT clk (1066:1066:1066) (1084:1084:1084)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2485:2485:2485) (2802:2802:2802)) - (PORT d[1] (2296:2296:2296) (2585:2585:2585)) - (PORT d[2] (2499:2499:2499) (2826:2826:2826)) - (PORT d[3] (2489:2489:2489) (2856:2856:2856)) - (PORT d[4] (2486:2486:2486) (2819:2819:2819)) - (PORT d[5] (2590:2590:2590) (2938:2938:2938)) - (PORT d[6] (2582:2582:2582) (2952:2952:2952)) - (PORT d[7] (2284:2284:2284) (2579:2579:2579)) - (PORT d[8] (2592:2592:2592) (2930:2930:2930)) - (PORT d[9] (2569:2569:2569) (2938:2938:2938)) - (PORT d[10] (2524:2524:2524) (2834:2834:2834)) - (PORT d[11] (2504:2504:2504) (2829:2829:2829)) - (PORT d[12] (2553:2553:2553) (2895:2895:2895)) - (PORT clk (1063:1063:1063) (1083:1083:1083)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1066:1066:1066) (1084:1084:1084)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1067:1067:1067) (1085:1085:1085)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1067:1067:1067) (1085:1085:1085)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1067:1067:1067) (1085:1085:1085)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1067:1067:1067) (1085:1085:1085)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1062:1062:1062) (1082:1082:1082)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (556:556:556) (637:637:637)) - (PORT d[1] (542:542:542) (629:629:629)) - (PORT d[2] (685:685:685) (787:787:787)) - (PORT d[3] (734:734:734) (855:855:855)) - (PORT d[4] (1524:1524:1524) (1788:1788:1788)) - (PORT d[5] (1750:1750:1750) (2051:2051:2051)) - (PORT d[6] (544:544:544) (626:626:626)) - (PORT d[7] (730:730:730) (835:835:835)) - (PORT d[8] (580:580:580) (669:669:669)) - (PORT d[9] (534:534:534) (619:619:619)) - (PORT d[10] (745:745:745) (856:856:856)) - (PORT d[11] (1492:1492:1492) (1736:1736:1736)) - (PORT d[12] (729:729:729) (842:842:842)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (PORT d[0] (356:356:356) (332:332:332)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1077:1077:1077) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (786:786:786)) - (PORT datab (482:482:482) (556:556:556)) - (PORT datac (468:468:468) (545:545:545)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (109:109:109) (142:142:142)) - (PORT datab (155:155:155) (208:208:208)) - (PORT datac (901:901:901) (1024:1024:1024)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (172:172:172) (165:165:165)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~105) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (503:503:503) (592:592:592)) - (PORT datac (652:652:652) (768:768:768)) - (PORT datad (311:311:311) (358:358:358)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (237:237:237)) - (PORT datab (125:125:125) (156:156:156)) - (PORT datac (94:94:94) (118:118:118)) - (PORT datad (97:97:97) (117:117:117)) - (IOPATH dataa combout (181:181:181) (175:175:175)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (288:288:288)) - (PORT datab (125:125:125) (156:156:156)) - (PORT datac (613:613:613) (702:702:702)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (535:535:535) (638:638:638)) - (PORT datab (345:345:345) (406:406:406)) - (PORT datac (317:317:317) (356:356:356)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (902:902:902)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (652:652:652) (703:703:703)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT datab (493:493:493) (580:580:580)) - (PORT datac (518:518:518) (611:611:611)) - (PORT datad (117:117:117) (140:140:140)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (227:227:227) (286:286:286)) - (PORT datab (125:125:125) (158:158:158)) - (PORT datac (122:122:122) (151:151:151)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) (PORT d (37:37:37) (50:50:50)) (PORT clrn (917:917:917) (902:902:902)) - (PORT ena (645:645:645) (697:697:697)) + (PORT ena (1057:1057:1057) (1164:1164:1164)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -46606,11 +49023,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~1) + (INSTANCE z80_\|execute_\|ctl_mRead\~11) (DELAY (ABSOLUTE - (PORT datac (811:811:811) (946:946:946)) - (PORT datad (1279:1279:1279) (1475:1475:1475)) + (PORT dataa (1181:1181:1181) (1407:1407:1407)) + (PORT datab (1130:1130:1130) (1300:1300:1300)) + (PORT datac (787:787:787) (939:939:939)) + (PORT datad (477:477:477) (556:556:556)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -46618,79 +49039,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal43\~0) + (INSTANCE z80_\|execute_\|setM1\~46) (DELAY (ABSOLUTE - (PORT dataa (507:507:507) (594:594:594)) - (PORT datab (535:535:535) (622:622:622)) - (PORT datac (916:916:916) (1100:1100:1100)) - (PORT datad (695:695:695) (806:806:806)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~2) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (104:104:104) (128:128:128)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~3) - (DELAY - (ABSOLUTE - (PORT dataa (455:455:455) (525:525:525)) - (PORT datab (1139:1139:1139) (1322:1322:1322)) - (PORT datac (717:717:717) (840:840:840)) - (PORT datad (595:595:595) (674:674:674)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (928:928:928) (910:910:910)) - (PORT ena (890:890:890) (972:972:972)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (786:786:786)) - (PORT datab (1137:1137:1137) (1320:1320:1320)) - (PORT datac (723:723:723) (853:853:853)) - (PORT datad (1052:1052:1052) (1203:1203:1203)) + (PORT dataa (679:679:679) (777:777:777)) + (PORT datab (358:358:358) (422:422:422)) + (PORT datac (803:803:803) (912:912:912)) + (PORT datad (170:170:170) (200:200:200)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -46699,29 +49054,183 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~40) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (924:924:924) (906:906:906)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + (PORT datac (582:582:582) (686:686:686)) + (PORT datad (318:318:318) (371:371:371)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) + (INSTANCE z80_\|execute_\|nextM\~5) (DELAY (ABSOLUTE - (PORT datab (136:136:136) (186:186:186)) - (PORT datad (124:124:124) (163:163:163)) + (PORT dataa (115:115:115) (146:146:146)) + (PORT datab (1056:1056:1056) (1215:1215:1215)) + (PORT datac (104:104:104) (125:125:125)) + (PORT datad (578:578:578) (666:666:666)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~6) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (759:759:759)) + (PORT datab (121:121:121) (152:152:152)) + (PORT datac (334:334:334) (392:392:392)) + (PORT datad (325:325:325) (376:376:376)) + (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~7) + (DELAY + (ABSOLUTE + (PORT dataa (705:705:705) (823:823:823)) + (PORT datab (428:428:428) (514:514:514)) + (PORT datac (1064:1064:1064) (1205:1205:1205)) + (PORT datad (454:454:454) (515:515:515)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~9) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (409:409:409)) + (PORT datab (115:115:115) (142:142:142)) + (PORT datac (840:840:840) (965:965:965)) + (PORT datad (352:352:352) (416:416:416)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~10) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (1063:1063:1063)) + (PORT datab (493:493:493) (577:577:577)) + (PORT datac (772:772:772) (892:892:892)) + (PORT datad (461:461:461) (523:523:523)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~8) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (424:424:424)) + (PORT datab (723:723:723) (847:847:847)) + (PORT datac (113:113:113) (134:134:134)) + (PORT datad (939:939:939) (1070:1070:1070)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~12) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (148:148:148)) + (PORT datab (362:362:362) (423:423:423)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~15) + (DELAY + (ABSOLUTE + (PORT dataa (454:454:454) (529:529:529)) + (PORT datab (1306:1306:1306) (1527:1527:1527)) + (PORT datac (817:817:817) (959:959:959)) + (PORT datad (588:588:588) (692:692:692)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~13) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (569:569:569)) + (PORT datab (101:101:101) (130:130:130)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~14) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (301:301:301) (351:351:351)) + (PORT datac (329:329:329) (389:389:389)) + (PORT datad (770:770:770) (877:877:877)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|ena_M) + (DELAY + (ABSOLUTE + (PORT datac (375:375:375) (447:447:447)) + (PORT datad (486:486:486) (563:563:563)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -46731,10 +49240,10 @@ (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) (DELAY (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) + (PORT clk (906:906:906) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (927:927:927) (908:908:908)) - (PORT ena (1086:1086:1086) (1232:1232:1232)) + (PORT clrn (918:918:918) (901:901:901)) + (PORT ena (646:646:646) (704:704:704)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -46749,9 +49258,9 @@ (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) (DELAY (ABSOLUTE - (PORT dataa (143:143:143) (194:194:194)) - (PORT datac (600:600:600) (695:695:695)) - (PORT datad (605:605:605) (699:699:699)) + (PORT dataa (365:365:365) (448:448:448)) + (PORT datac (376:376:376) (448:448:448)) + (PORT datad (485:485:485) (562:562:562)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -46763,10 +49272,10 @@ (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) (DELAY (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) + (PORT clk (906:906:906) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (927:927:927) (908:908:908)) - (PORT ena (1086:1086:1086) (1232:1232:1232)) + (PORT clrn (918:918:918) (901:901:901)) + (PORT ena (646:646:646) (704:704:704)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -46778,12 +49287,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|x3) + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) (DELAY (ABSOLUTE - (PORT dataa (1330:1330:1330) (1557:1557:1557)) - (PORT datac (130:130:130) (172:172:172)) - (PORT datad (763:763:763) (913:913:913)) + (PORT dataa (142:142:142) (194:194:194)) + (PORT datac (377:377:377) (449:449:449)) + (PORT datad (484:484:484) (560:560:560)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -46792,26 +49301,678 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) + (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) (DELAY (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) + (PORT clk (906:906:906) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (1092:1092:1092) (1064:1064:1064)) + (PORT clrn (918:918:918) (901:901:901)) + (PORT ena (646:646:646) (704:704:704)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT inclk[0] (903:903:903) (996:996:996)) + (PORT dataa (143:143:143) (195:195:195)) + (PORT datac (374:374:374) (447:447:447)) + (PORT datad (487:487:487) (564:564:564)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (918:918:918) (901:901:901)) + (PORT ena (646:646:646) (704:704:704)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~9) + (DELAY + (ABSOLUTE + (PORT datac (384:384:384) (472:472:472)) + (PORT datad (1329:1329:1329) (1548:1548:1548)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (789:789:789)) + (PORT datab (857:857:857) (994:994:994)) + (PORT datac (886:886:886) (1007:1007:1007)) + (PORT datad (521:521:521) (597:597:597)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~54) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (709:709:709)) + (PORT datab (347:347:347) (410:410:410)) + (PORT datac (643:643:643) (754:754:754)) + (PORT datad (493:493:493) (583:583:583)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~25) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (422:422:422)) + (PORT datab (722:722:722) (845:845:845)) + (PORT datac (336:336:336) (378:378:378)) + (PORT datad (458:458:458) (519:519:519)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~26) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (754:754:754)) + (PORT datab (534:534:534) (623:623:623)) + (PORT datac (139:139:139) (179:179:179)) + (PORT datad (628:628:628) (724:724:724)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~27) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (753:753:753)) + (PORT datab (331:331:331) (383:383:383)) + (PORT datac (466:466:466) (531:531:531)) + (PORT datad (458:458:458) (546:546:546)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~22) + (DELAY + (ABSOLUTE + (PORT dataa (495:495:495) (597:597:597)) + (PORT datab (811:811:811) (935:935:935)) + (PORT datac (1616:1616:1616) (1860:1860:1860)) + (PORT datad (125:125:125) (165:165:165)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~55) + (DELAY + (ABSOLUTE + (PORT dataa (798:798:798) (976:976:976)) + (PORT datab (587:587:587) (672:672:672)) + (PORT datac (682:682:682) (803:803:803)) + (PORT datad (1183:1183:1183) (1384:1384:1384)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~23) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (700:700:700)) + (PORT datab (195:195:195) (235:235:235)) + (PORT datac (477:477:477) (569:569:569)) + (PORT datad (931:931:931) (1060:1060:1060)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~24) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (508:508:508) (601:601:601)) + (PORT datac (472:472:472) (531:531:531)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~28) + (DELAY + (ABSOLUTE + (PORT dataa (283:283:283) (332:332:332)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (330:330:330) (386:386:386)) + (PORT datad (487:487:487) (553:553:553)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~11) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (723:723:723)) + (PORT datab (1081:1081:1081) (1237:1237:1237)) + (PORT datac (518:518:518) (616:616:616)) + (PORT datad (646:646:646) (755:755:755)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~33) + (DELAY + (ABSOLUTE + (PORT dataa (952:952:952) (1107:1107:1107)) + (PORT datab (1126:1126:1126) (1264:1264:1264)) + (PORT datac (912:912:912) (1034:1034:1034)) + (PORT datad (882:882:882) (998:998:998)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~29) + (DELAY + (ABSOLUTE + (PORT dataa (468:468:468) (560:560:560)) + (PORT datab (470:470:470) (568:568:568)) + (PORT datac (496:496:496) (579:579:579)) + (PORT datad (737:737:737) (854:854:854)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~31) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (714:714:714)) + (PORT datab (479:479:479) (555:555:555)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (724:724:724) (844:844:844)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~32) + (DELAY + (ABSOLUTE + (PORT dataa (496:496:496) (586:586:586)) + (PORT datab (846:846:846) (985:985:985)) + (PORT datac (607:607:607) (708:708:708)) + (PORT datad (869:869:869) (1008:1008:1008)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~34) + (DELAY + (ABSOLUTE + (PORT dataa (470:470:470) (557:557:557)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (449:449:449) (513:513:513)) + (PORT datad (926:926:926) (1044:1044:1044)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~20) + (DELAY + (ABSOLUTE + (PORT dataa (524:524:524) (609:609:609)) + (PORT datab (140:140:140) (188:188:188)) + (PORT datac (920:920:920) (1048:1048:1048)) + (PORT datad (503:503:503) (586:586:586)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~21) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (752:752:752)) + (PORT datab (731:731:731) (853:853:853)) + (PORT datac (478:478:478) (546:546:546)) + (PORT datad (464:464:464) (546:546:546)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~35) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~15) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (394:394:394)) + (PORT datab (677:677:677) (787:787:787)) + (PORT datac (836:836:836) (978:978:978)) + (PORT datad (322:322:322) (377:377:377)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~14) + (DELAY + (ABSOLUTE + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (317:317:317) (376:376:376)) + (PORT datad (1081:1081:1081) (1226:1226:1226)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (744:744:744)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (730:730:730) (827:827:827)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (754:754:754)) + (PORT datab (632:632:632) (720:720:720)) + (PORT datac (776:776:776) (893:893:893)) + (PORT datad (749:749:749) (871:871:871)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (692:692:692)) + (PORT datab (899:899:899) (1063:1063:1063)) + (PORT datac (750:750:750) (842:842:842)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (575:575:575)) + (PORT datab (639:639:639) (755:755:755)) + (PORT datac (374:374:374) (460:460:460)) + (PORT datad (474:474:474) (551:551:551)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~9) + (DELAY + (ABSOLUTE + (PORT dataa (488:488:488) (574:574:574)) + (PORT datac (823:823:823) (969:969:969)) + (PORT datad (449:449:449) (507:507:507)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~13) + (DELAY + (ABSOLUTE + (PORT dataa (114:114:114) (145:145:145)) + (PORT datab (652:652:652) (761:761:761)) + (PORT datac (661:661:661) (768:768:768)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~18) + (DELAY + (ABSOLUTE + (PORT dataa (509:509:509) (587:587:587)) + (PORT datab (362:362:362) (429:429:429)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (1114:1114:1114) (1266:1266:1266)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~19) + (DELAY + (ABSOLUTE + (PORT dataa (508:508:508) (592:592:592)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (847:847:847) (975:975:975)) + (PORT datad (338:338:338) (395:395:395)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~43) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (702:702:702)) + (PORT datab (631:631:631) (761:761:761)) + (PORT datac (294:294:294) (338:338:338)) + (PORT datad (419:419:419) (484:484:484)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~42) + (DELAY + (ABSOLUTE + (PORT dataa (984:984:984) (1137:1137:1137)) + (PORT datab (1122:1122:1122) (1281:1281:1281)) + (PORT datac (515:515:515) (606:606:606)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~44) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (657:657:657)) + (PORT datab (555:555:555) (638:638:638)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (524:524:524) (612:612:612)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~45) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (958:958:958)) + (PORT datab (772:772:772) (879:879:879)) + (PORT datac (867:867:867) (1018:1018:1018)) + (PORT datad (323:323:323) (373:373:373)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~51) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (132:132:132)) + (PORT datab (111:111:111) (142:142:142)) + (PORT datac (101:101:101) (122:122:122)) + (PORT datad (178:178:178) (205:205:205)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (191:191:191)) + (PORT datac (374:374:374) (446:446:446)) + (PORT datad (487:487:487) (565:565:565)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|T6) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (918:918:918) (901:901:901)) + (PORT ena (646:646:646) (704:704:704)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~52) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (500:500:500) (600:600:600)) + (PORT datac (759:759:759) (859:859:859)) + (PORT datad (185:185:185) (215:215:215)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~53) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (386:386:386)) + (PORT datab (610:610:610) (700:700:700)) + (PORT datac (493:493:493) (595:595:595)) + (PORT datad (290:290:290) (331:331:331)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) + (DELAY + (ABSOLUTE + (PORT datab (390:390:390) (469:469:469)) + (PORT datad (490:490:490) (567:567:567)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -46820,9 +49981,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M1_ff) (DELAY (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) + (PORT clk (906:906:906) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (927:927:927) (908:908:908)) + (PORT clrn (918:918:918) (901:901:901)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -46836,11 +49997,11 @@ (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (615:615:615) (720:720:720)) - (PORT datab (152:152:152) (205:205:205)) - (PORT datad (607:607:607) (702:702:702)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (343:343:343) (418:418:418)) + (PORT datab (394:394:394) (474:474:474)) + (PORT datad (484:484:484) (561:561:561)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -46849,3104 +50010,29 @@ (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (927:927:927) (908:908:908)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~3) - (DELAY - (ABSOLUTE - (PORT datac (595:595:595) (716:716:716)) - (PORT datad (1126:1126:1126) (1302:1302:1302)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~11) - (DELAY - (ABSOLUTE - (PORT dataa (823:823:823) (951:951:951)) - (PORT datab (464:464:464) (536:536:536)) - (PORT datac (431:431:431) (489:489:489)) - (PORT datad (364:364:364) (427:427:427)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~8) - (DELAY - (ABSOLUTE - (PORT dataa (554:554:554) (656:656:656)) - (PORT datab (359:359:359) (422:422:422)) - (PORT datac (531:531:531) (627:627:627)) - (PORT datad (1266:1266:1266) (1455:1455:1455)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~9) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (547:547:547)) - (PORT datab (452:452:452) (517:517:517)) - (PORT datac (520:520:520) (602:602:602)) - (PORT datad (212:212:212) (253:253:253)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~10) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (435:435:435)) - (PORT datab (171:171:171) (208:208:208)) - (PORT datac (833:833:833) (964:964:964)) - (PORT datad (1187:1187:1187) (1363:1363:1363)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~12) - (DELAY - (ABSOLUTE - (PORT dataa (205:205:205) (243:243:243)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1106:1106:1106) (1287:1287:1287)) - (PORT datab (467:467:467) (544:544:544)) - (PORT datac (786:786:786) (909:909:909)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~6) - (DELAY - (ABSOLUTE - (PORT dataa (123:123:123) (157:157:157)) - (PORT datab (125:125:125) (157:157:157)) - (PORT datac (180:180:180) (218:218:218)) - (PORT datad (582:582:582) (648:648:648)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~7) - (DELAY - (ABSOLUTE - (PORT dataa (124:124:124) (158:158:158)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (554:554:554) (656:656:656)) - (PORT datad (428:428:428) (489:489:489)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~13) - (DELAY - (ABSOLUTE - (PORT datab (602:602:602) (697:697:697)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (161:161:161) (190:190:190)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~39) - (DELAY - (ABSOLUTE - (PORT datac (411:411:411) (470:470:470)) - (PORT datad (333:333:333) (382:382:382)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~5) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (139:139:139)) - (PORT datab (1136:1136:1136) (1298:1298:1298)) - (PORT datac (345:345:345) (408:408:408)) - (PORT datad (173:173:173) (194:194:194)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~14) - (DELAY - (ABSOLUTE - (PORT dataa (446:446:446) (508:508:508)) - (PORT datab (478:478:478) (557:557:557)) - (PORT datac (564:564:564) (640:640:640)) - (PORT datad (281:281:281) (321:321:321)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT datab (147:147:147) (198:198:198)) - (PORT datac (596:596:596) (691:691:691)) - (PORT datad (609:609:609) (703:703:703)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (927:927:927) (908:908:908)) - (PORT ena (1086:1086:1086) (1232:1232:1232)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (715:715:715)) - (PORT datac (133:133:133) (177:177:177)) - (PORT datad (611:611:611) (706:706:706)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (927:927:927) (908:908:908)) - (PORT ena (1086:1086:1086) (1232:1232:1232)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) - (DELAY - (ABSOLUTE - (PORT datab (143:143:143) (191:191:191)) - (PORT datac (589:589:589) (684:684:684)) - (PORT datad (614:614:614) (709:709:709)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|T6) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (927:927:927) (908:908:908)) - (PORT ena (1086:1086:1086) (1232:1232:1232)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~13) - (DELAY - (ABSOLUTE - (PORT dataa (316:316:316) (367:367:367)) - (PORT datab (483:483:483) (558:558:558)) - (PORT datac (325:325:325) (377:377:377)) - (PORT datad (510:510:510) (594:594:594)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~1) - (DELAY - (ABSOLUTE - (PORT dataa (572:572:572) (695:695:695)) - (PORT datab (658:658:658) (767:767:767)) - (PORT datac (372:372:372) (439:439:439)) - (PORT datad (717:717:717) (834:834:834)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~12) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (431:431:431)) - (PORT datab (915:915:915) (1053:1053:1053)) - (PORT datac (469:469:469) (544:544:544)) - (PORT datad (464:464:464) (535:535:535)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~14) - (DELAY - (ABSOLUTE - (PORT datab (102:102:102) (129:129:129)) - (PORT datac (352:352:352) (408:408:408)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~41) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (260:260:260)) - (PORT datac (576:576:576) (672:672:672)) - (PORT datad (108:108:108) (127:127:127)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~42) - (DELAY - (ABSOLUTE - (PORT dataa (510:510:510) (599:599:599)) - (PORT datab (614:614:614) (734:734:734)) - (PORT datac (216:216:216) (266:266:266)) - (PORT datad (1392:1392:1392) (1611:1611:1611)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1149:1149:1149) (1358:1358:1358)) - (PORT datab (437:437:437) (524:524:524)) - (PORT datac (526:526:526) (610:610:610)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~44) - (DELAY - (ABSOLUTE - (PORT dataa (481:481:481) (557:557:557)) - (PORT datab (184:184:184) (223:223:223)) - (PORT datac (108:108:108) (131:131:131)) - (PORT datad (406:406:406) (458:458:458)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~50) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (230:230:230)) - (PORT datab (586:586:586) (660:660:660)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (729:729:729) (821:821:821)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~51) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (707:707:707)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (105:105:105) (128:128:128)) - (PORT datad (95:95:95) (113:113:113)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~6) - (DELAY - (ABSOLUTE - (PORT dataa (453:453:453) (522:522:522)) - (PORT datab (908:908:908) (1071:1071:1071)) - (PORT datac (339:339:339) (389:389:389)) - (PORT datad (960:960:960) (1120:1120:1120)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~7) - (DELAY - (ABSOLUTE - (PORT datab (495:495:495) (584:584:584)) - (PORT datac (492:492:492) (563:563:563)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~8) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (928:928:928)) - (PORT datab (471:471:471) (548:548:548)) - (PORT datac (484:484:484) (562:562:562)) - (PORT datad (338:338:338) (387:387:387)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~9) - (DELAY - (ABSOLUTE - (PORT dataa (849:849:849) (998:998:998)) - (PORT datab (1114:1114:1114) (1277:1277:1277)) - (PORT datac (759:759:759) (892:892:892)) - (PORT datad (616:616:616) (699:699:699)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~10) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (144:144:144)) - (PORT datab (622:622:622) (714:714:714)) - (PORT datac (266:266:266) (299:299:299)) - (PORT datad (351:351:351) (408:408:408)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~11) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (652:652:652) (767:767:767)) - (PORT datac (562:562:562) (667:667:667)) - (PORT datad (174:174:174) (206:206:206)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~17) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (405:405:405)) - (PORT datab (585:585:585) (659:659:659)) - (PORT datac (1117:1117:1117) (1277:1277:1277)) - (PORT datad (333:333:333) (385:385:385)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~31) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (391:391:391)) - (PORT datab (500:500:500) (587:587:587)) - (PORT datac (1026:1026:1026) (1197:1197:1197)) - (PORT datad (475:475:475) (555:555:555)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~28) - (DELAY - (ABSOLUTE - (PORT dataa (187:187:187) (232:232:232)) - (PORT datab (670:670:670) (786:786:786)) - (PORT datac (786:786:786) (906:906:906)) - (PORT datad (457:457:457) (524:524:524)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~30) - (DELAY - (ABSOLUTE - (PORT dataa (463:463:463) (545:545:545)) - (PORT datab (503:503:503) (579:579:579)) - (PORT datac (500:500:500) (569:569:569)) - (PORT datad (453:453:453) (528:528:528)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~32) - (DELAY - (ABSOLUTE - (PORT dataa (507:507:507) (592:592:592)) - (PORT datab (186:186:186) (224:224:224)) - (PORT datac (481:481:481) (558:558:558)) - (PORT datad (610:610:610) (697:697:697)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~33) - (DELAY - (ABSOLUTE - (PORT dataa (313:313:313) (364:364:364)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (496:496:496) (577:577:577)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~25) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (731:731:731)) - (PORT datac (331:331:331) (393:393:393)) - (PORT datad (900:900:900) (1053:1053:1053)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~26) - (DELAY - (ABSOLUTE - (PORT dataa (487:487:487) (564:564:564)) - (PORT datab (864:864:864) (1009:1009:1009)) - (PORT datac (485:485:485) (555:555:555)) - (PORT datad (638:638:638) (731:731:731)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~24) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (433:433:433)) - (PORT datab (359:359:359) (421:421:421)) - (PORT datac (1113:1113:1113) (1238:1238:1238)) - (PORT datad (530:530:530) (626:626:626)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~27) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (354:354:354) (420:420:420)) - (PORT datad (380:380:380) (450:450:450)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~22) - (DELAY - (ABSOLUTE - (PORT dataa (515:515:515) (596:596:596)) - (PORT datab (485:485:485) (566:566:566)) - (PORT datac (482:482:482) (565:565:565)) - (PORT datad (329:329:329) (379:379:379)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~21) - (DELAY - (ABSOLUTE - (PORT dataa (996:996:996) (1155:1155:1155)) - (PORT datab (875:875:875) (1044:1044:1044)) - (PORT datac (680:680:680) (794:794:794)) - (PORT datad (846:846:846) (968:968:968)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~53) - (DELAY - (ABSOLUTE - (PORT dataa (531:531:531) (620:620:620)) - (PORT datab (519:519:519) (605:605:605)) - (PORT datac (347:347:347) (411:411:411)) - (PORT datad (711:711:711) (805:805:805)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~23) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (190:190:190) (228:228:228)) - (PORT datac (866:866:866) (1002:1002:1002)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~18) - (DELAY - (ABSOLUTE - (PORT dataa (194:194:194) (236:236:236)) - (PORT datab (533:533:533) (619:619:619)) - (PORT datac (844:844:844) (991:991:991)) - (PORT datad (101:101:101) (119:119:119)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~19) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (387:387:387)) - (PORT datab (388:388:388) (463:463:463)) - (PORT datac (364:364:364) (431:431:431)) - (PORT datad (744:744:744) (877:877:877)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~20) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (414:414:414)) - (PORT datab (645:645:645) (743:743:743)) - (PORT datac (495:495:495) (574:574:574)) - (PORT datad (332:332:332) (388:388:388)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~34) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (394:394:394)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (160:160:160) (190:190:190)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~52) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (159:159:159) (187:187:187)) - (PORT datad (542:542:542) (636:636:636)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (712:712:712)) - (PORT datac (135:135:135) (179:179:179)) - (PORT datad (613:613:613) (708:708:708)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (927:927:927) (908:908:908)) - (PORT ena (1086:1086:1086) (1232:1232:1232)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) - (DELAY - (ABSOLUTE - (PORT datac (551:551:551) (648:648:648)) - (PORT datad (763:763:763) (910:910:910)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~0) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (285:285:285)) - (PORT datac (652:652:652) (766:766:766)) - (PORT datad (151:151:151) (195:195:195)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~1) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (422:422:422)) - (PORT datab (878:878:878) (991:991:991)) - (PORT datad (347:347:347) (409:409:409)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|in_halt) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (914:914:914) (898:898:898)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (536:536:536) (641:641:641)) - (PORT datab (645:645:645) (740:740:740)) - (PORT datac (367:367:367) (429:429:429)) - (PORT datad (349:349:349) (407:407:407)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (785:785:785)) - (PORT datab (550:550:550) (651:651:651)) - (PORT datac (635:635:635) (737:737:737)) - (PORT datad (485:485:485) (566:566:566)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (249:249:249)) - (PORT datab (382:382:382) (454:454:454)) - (PORT datac (493:493:493) (572:572:572)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) - (DELAY - (ABSOLUTE - (PORT datac (576:576:576) (667:667:667)) - (PORT datad (344:344:344) (397:397:397)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datab (516:516:516) (610:610:610)) - (PORT datac (335:335:335) (396:396:396)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (135:135:135) (173:173:173)) - (PORT datac (517:517:517) (609:609:609)) - (PORT datad (174:174:174) (202:202:202)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~93) - (DELAY - (ABSOLUTE - (PORT dataa (123:123:123) (161:161:161)) - (PORT datab (432:432:432) (531:531:531)) - (PORT datac (759:759:759) (915:915:915)) - (PORT datad (296:296:296) (336:336:336)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~94) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (398:398:398)) - (PORT datab (408:408:408) (499:499:499)) - (PORT datad (402:402:402) (484:484:484)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (511:511:511)) - (PORT datab (657:657:657) (772:772:772)) - (PORT datac (407:407:407) (493:493:493)) - (PORT datad (410:410:410) (510:510:510)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~98) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (140:140:140)) - (PORT datab (110:110:110) (141:141:141)) - (PORT datad (98:98:98) (118:118:118)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (688:688:688)) - (PORT datab (644:644:644) (754:754:754)) - (PORT datac (118:118:118) (160:160:160)) - (PORT datad (189:189:189) (235:235:235)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~99) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (521:521:521)) - (PORT datab (397:397:397) (488:488:488)) - (PORT datac (478:478:478) (565:565:565)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~100) - (DELAY - (ABSOLUTE - (PORT dataa (177:177:177) (217:217:217)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datad (402:402:402) (492:492:492)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (505:505:505)) - (PORT datab (538:538:538) (645:645:645)) - (PORT datad (507:507:507) (606:606:606)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) - (DELAY - (ABSOLUTE - (PORT dataa (417:417:417) (513:513:513)) - (PORT datab (406:406:406) (497:497:497)) - (PORT datac (639:639:639) (748:748:748)) - (PORT datad (492:492:492) (585:585:585)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~133) - (DELAY - (ABSOLUTE - (PORT dataa (363:363:363) (429:429:429)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (409:409:409) (495:495:495)) - (PORT datad (404:404:404) (504:504:504)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~103) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datad (165:165:165) (195:195:195)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (314:314:314) (364:364:364)) - (PORT datab (217:217:217) (275:275:275)) - (PORT datac (294:294:294) (339:339:339)) - (PORT datad (338:338:338) (406:406:406)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) - (DELAY - (ABSOLUTE - (PORT dataa (397:397:397) (488:488:488)) - (PORT datab (404:404:404) (494:494:494)) - (PORT datac (399:399:399) (489:489:489)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~105) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (191:191:191) (231:231:231)) - (PORT datad (402:402:402) (484:484:484)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) - (DELAY - (ABSOLUTE - (PORT dataa (791:791:791) (952:952:952)) - (PORT datab (114:114:114) (147:147:147)) - (PORT datac (517:517:517) (615:615:615)) - (PORT datad (108:108:108) (128:128:128)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (479:479:479)) - (PORT datab (355:355:355) (429:429:429)) - (PORT datac (345:345:345) (419:419:419)) - (PORT datad (228:228:228) (285:285:285)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (122:122:122) (156:156:156)) - (PORT datab (217:217:217) (280:280:280)) - (PORT datac (333:333:333) (402:402:402)) - (PORT datad (214:214:214) (265:265:265)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~134) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (229:229:229)) - (PORT datab (193:193:193) (232:232:232)) - (PORT datad (440:440:440) (513:513:513)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (492:492:492)) - (PORT datab (327:327:327) (387:387:387)) - (PORT datac (328:328:328) (391:391:391)) - (PORT datad (271:271:271) (307:307:307)) - (IOPATH dataa combout (172:172:172) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~135) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (491:491:491)) - (PORT datab (148:148:148) (198:198:198)) - (PORT datad (595:595:595) (692:692:692)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~108) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (190:190:190) (235:235:235)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (130:130:130) (179:179:179)) - (PORT datab (663:663:663) (779:779:779)) - (PORT datac (342:342:342) (408:408:408)) - (PORT datad (418:418:418) (478:478:478)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~112) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (535:535:535)) - (PORT datab (119:119:119) (153:153:153)) - (PORT datac (342:342:342) (411:411:411)) - (PORT datad (167:167:167) (196:196:196)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~113) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (478:478:478)) - (PORT datab (106:106:106) (135:135:135)) - (PORT datac (297:297:297) (351:351:351)) - (PORT datad (251:251:251) (308:308:308)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~114) - (DELAY - (ABSOLUTE - (PORT datab (296:296:296) (344:344:344)) - (PORT datad (470:470:470) (539:539:539)) - (IOPATH datab combout (191:191:191) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (903:903:903) (908:908:908)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~109) - (DELAY - (ABSOLUTE - (PORT dataa (386:386:386) (488:488:488)) - (PORT datab (345:345:345) (418:418:418)) - (PORT datac (343:343:343) (411:411:411)) - (PORT datad (424:424:424) (495:495:495)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (483:483:483)) - (PORT datab (117:117:117) (150:150:150)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (341:341:341) (406:406:406)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~137) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (485:485:485)) - (PORT datab (171:171:171) (209:209:209)) - (PORT datad (177:177:177) (212:212:212)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~138) - (DELAY - (ABSOLUTE - (PORT dataa (581:581:581) (714:714:714)) - (PORT datab (361:361:361) (425:425:425)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~2) - (DELAY - (ABSOLUTE - (PORT datab (749:749:749) (881:881:881)) - (PORT datac (902:902:902) (1053:1053:1053)) - (PORT datad (669:669:669) (791:791:791)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (121:121:121) (152:152:152)) - (PORT datab (639:639:639) (743:743:743)) - (PORT datac (660:660:660) (773:773:773)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (721:721:721)) - (PORT datab (1854:1854:1854) (2144:2144:2144)) - (PORT datac (639:639:639) (741:741:741)) - (PORT datad (285:285:285) (326:326:326)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (583:583:583) (669:669:669)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2271:2271:2271) (2633:2633:2633)) - (PORT d[1] (973:973:973) (1149:1149:1149)) - (PORT d[2] (959:959:959) (1102:1102:1102)) - (PORT d[3] (1046:1046:1046) (1227:1227:1227)) - (PORT d[4] (1245:1245:1245) (1443:1443:1443)) - (PORT d[5] (784:784:784) (927:927:927)) - (PORT d[6] (857:857:857) (998:998:998)) - (PORT d[7] (1954:1954:1954) (2213:2213:2213)) - (PORT d[8] (2109:2109:2109) (2446:2446:2446)) - (PORT d[9] (838:838:838) (972:972:972)) - (PORT d[10] (1853:1853:1853) (2129:2129:2129)) - (PORT d[11] (1194:1194:1194) (1380:1380:1380)) - (PORT d[12] (992:992:992) (1139:1139:1139)) - (PORT clk (1087:1087:1087) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1463:1463:1463) (1618:1618:1618)) - (PORT clk (1087:1087:1087) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1106:1106:1106)) - (PORT d[0] (1670:1670:1670) (1837:1837:1837)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1069:1069:1069) (1085:1085:1085)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (609:609:609) (617:617:617)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (364:364:364) (418:418:418)) - (PORT clk (1092:1092:1092) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1714:1714:1714) (1988:1988:1988)) - (PORT d[1] (791:791:791) (936:936:936)) - (PORT d[2] (1150:1150:1150) (1318:1318:1318)) - (PORT d[3] (1214:1214:1214) (1418:1418:1418)) - (PORT d[4] (898:898:898) (1045:1045:1045)) - (PORT d[5] (787:787:787) (936:936:936)) - (PORT d[6] (673:673:673) (784:784:784)) - (PORT d[7] (1969:1969:1969) (2223:2223:2223)) - (PORT d[8] (1446:1446:1446) (1694:1694:1694)) - (PORT d[9] (2000:2000:2000) (2303:2303:2303)) - (PORT d[10] (1670:1670:1670) (1918:1918:1918)) - (PORT d[11] (977:977:977) (1132:1132:1132)) - (PORT d[12] (803:803:803) (924:924:924)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1087:1087:1087) (1186:1186:1186)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (PORT d[0] (1674:1674:1674) (1813:1813:1813)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1072:1072:1072) (1089:1089:1089)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (556:556:556) (636:636:636)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1698:1698:1698) (1965:1965:1965)) - (PORT d[1] (791:791:791) (935:935:935)) - (PORT d[2] (940:940:940) (1098:1098:1098)) - (PORT d[3] (839:839:839) (978:978:978)) - (PORT d[4] (1094:1094:1094) (1277:1277:1277)) - (PORT d[5] (937:937:937) (1106:1106:1106)) - (PORT d[6] (760:760:760) (866:866:866)) - (PORT d[7] (824:824:824) (946:946:946)) - (PORT d[8] (1251:1251:1251) (1469:1469:1469)) - (PORT d[9] (2197:2197:2197) (2532:2532:2532)) - (PORT d[10] (1497:1497:1497) (1720:1720:1720)) - (PORT d[11] (1017:1017:1017) (1179:1179:1179)) - (PORT d[12] (1136:1136:1136) (1310:1310:1310)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (919:919:919) (997:997:997)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (PORT d[0] (1219:1219:1219) (1309:1309:1309)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1071:1071:1071) (1087:1087:1087)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (400:400:400)) - (PORT datab (718:718:718) (841:841:841)) - (PORT datac (507:507:507) (574:574:574)) - (PORT datad (630:630:630) (739:739:739)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (717:717:717) (828:828:828)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2086:2086:2086) (2416:2416:2416)) - (PORT d[1] (989:989:989) (1166:1166:1166)) - (PORT d[2] (1751:1751:1751) (2006:2006:2006)) - (PORT d[3] (1216:1216:1216) (1416:1416:1416)) - (PORT d[4] (1303:1303:1303) (1522:1522:1522)) - (PORT d[5] (1396:1396:1396) (1646:1646:1646)) - (PORT d[6] (1194:1194:1194) (1381:1381:1381)) - (PORT d[7] (1595:1595:1595) (1805:1805:1805)) - (PORT d[8] (1756:1756:1756) (2044:2044:2044)) - (PORT d[9] (1448:1448:1448) (1671:1671:1671)) - (PORT d[10] (2188:2188:2188) (2512:2512:2512)) - (PORT d[11] (1010:1010:1010) (1170:1170:1170)) - (PORT d[12] (1191:1191:1191) (1366:1366:1366)) - (PORT clk (1087:1087:1087) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1555:1555:1555) (1720:1720:1720)) - (PORT clk (1087:1087:1087) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1106:1106:1106)) - (PORT d[0] (1507:1507:1507) (1632:1632:1632)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1069:1069:1069) (1085:1085:1085)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (609:609:609) (617:617:617)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (652:652:652) (759:759:759)) - (PORT datab (522:522:522) (603:603:603)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (825:825:825) (930:930:930)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2056:2056:2056) (2379:2379:2379)) - (PORT d[1] (1524:1524:1524) (1781:1781:1781)) - (PORT d[2] (942:942:942) (1103:1103:1103)) - (PORT d[3] (1197:1197:1197) (1399:1399:1399)) - (PORT d[4] (1073:1073:1073) (1250:1250:1250)) - (PORT d[5] (783:783:783) (928:928:928)) - (PORT d[6] (636:636:636) (739:739:739)) - (PORT d[7] (818:818:818) (941:941:941)) - (PORT d[8] (1260:1260:1260) (1481:1481:1481)) - (PORT d[9] (2208:2208:2208) (2547:2547:2547)) - (PORT d[10] (1476:1476:1476) (1692:1692:1692)) - (PORT d[11] (1175:1175:1175) (1361:1361:1361)) - (PORT d[12] (1122:1122:1122) (1295:1295:1295)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1106:1106:1106)) - (PORT d[0] (1966:1966:1966) (2218:2218:2218)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1071:1071:1071) (1087:1087:1087)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (822:822:822) (936:936:936)) - (PORT clk (1086:1086:1086) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1883:1883:1883) (2185:2185:2185)) - (PORT d[1] (1343:1343:1343) (1577:1577:1577)) - (PORT d[2] (1232:1232:1232) (1425:1425:1425)) - (PORT d[3] (1027:1027:1027) (1201:1201:1201)) - (PORT d[4] (1250:1250:1250) (1450:1450:1450)) - (PORT d[5] (965:965:965) (1138:1138:1138)) - (PORT d[6] (836:836:836) (965:965:965)) - (PORT d[7] (843:843:843) (972:972:972)) - (PORT d[8] (1670:1670:1670) (1933:1933:1933)) - (PORT d[9] (1320:1320:1320) (1516:1516:1516)) - (PORT d[10] (1292:1292:1292) (1485:1485:1485)) - (PORT d[11] (1399:1399:1399) (1626:1626:1626)) - (PORT d[12] (1114:1114:1114) (1279:1279:1279)) - (PORT clk (1084:1084:1084) (1102:1102:1102)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1608:1608:1608) (1771:1771:1771)) - (PORT clk (1084:1084:1084) (1102:1102:1102)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1086:1086:1086) (1104:1104:1104)) - (PORT d[0] (2283:2283:2283) (2527:2527:2527)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1041:1041:1041) (1061:1061:1061)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1252:1252:1252) (1392:1392:1392)) - (PORT clk (1046:1046:1046) (1064:1064:1064)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2408:2408:2408) (2741:2741:2741)) - (PORT d[1] (2392:2392:2392) (2698:2698:2698)) - (PORT d[2] (2372:2372:2372) (2705:2705:2705)) - (PORT d[3] (2539:2539:2539) (2894:2894:2894)) - (PORT d[4] (2352:2352:2352) (2674:2674:2674)) - (PORT d[5] (2403:2403:2403) (2727:2727:2727)) - (PORT d[6] (2496:2496:2496) (2860:2860:2860)) - (PORT d[7] (2413:2413:2413) (2753:2753:2753)) - (PORT d[8] (2542:2542:2542) (2856:2856:2856)) - (PORT d[9] (2555:2555:2555) (2936:2936:2936)) - (PORT d[10] (2442:2442:2442) (2755:2755:2755)) - (PORT d[11] (2400:2400:2400) (2708:2708:2708)) - (PORT d[12] (2571:2571:2571) (2895:2895:2895)) - (PORT clk (1043:1043:1043) (1063:1063:1063)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1046:1046:1046) (1064:1064:1064)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1047:1047:1047) (1065:1065:1065)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1047:1047:1047) (1065:1065:1065)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1047:1047:1047) (1065:1065:1065)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1047:1047:1047) (1065:1065:1065)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (472:472:472) (563:563:563)) - (PORT datab (938:938:938) (1094:1094:1094)) - (PORT datac (517:517:517) (591:591:591)) - (PORT datad (685:685:685) (776:776:776)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2029:2029:2029) (2354:2354:2354)) - (PORT d[1] (1516:1516:1516) (1773:1773:1773)) - (PORT d[2] (872:872:872) (1012:1012:1012)) - (PORT d[3] (1178:1178:1178) (1374:1374:1374)) - (PORT d[4] (1252:1252:1252) (1447:1447:1447)) - (PORT d[5] (957:957:957) (1129:1129:1129)) - (PORT d[6] (783:783:783) (903:903:903)) - (PORT d[7] (825:825:825) (954:954:954)) - (PORT d[8] (1234:1234:1234) (1452:1452:1452)) - (PORT d[9] (1340:1340:1340) (1538:1538:1538)) - (PORT d[10] (1301:1301:1301) (1494:1494:1494)) - (PORT d[11] (1198:1198:1198) (1388:1388:1388)) - (PORT d[12] (1288:1288:1288) (1479:1479:1479)) - (PORT clk (1087:1087:1087) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1104:1104:1104)) - (PORT d[0] (2195:2195:2195) (1948:1948:1948)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1069:1069:1069) (1085:1085:1085)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (609:609:609) (617:617:617)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (121:121:121) (154:154:154)) - (PORT datab (513:513:513) (583:583:583)) - (PORT datac (627:627:627) (715:715:715)) - (PORT datad (95:95:95) (113:113:113)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (860:860:860) (991:991:991)) - (PORT clk (1101:1101:1101) (1118:1118:1118)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1412:1412:1412) (1614:1614:1614)) - (PORT d[1] (1124:1124:1124) (1322:1322:1322)) - (PORT d[2] (1114:1114:1114) (1299:1299:1299)) - (PORT d[3] (1054:1054:1054) (1236:1236:1236)) - (PORT d[4] (1594:1594:1594) (1834:1834:1834)) - (PORT d[5] (1318:1318:1318) (1541:1541:1541)) - (PORT d[6] (1175:1175:1175) (1347:1347:1347)) - (PORT d[7] (1389:1389:1389) (1610:1610:1610)) - (PORT d[8] (1374:1374:1374) (1604:1604:1604)) - (PORT d[9] (1149:1149:1149) (1321:1321:1321)) - (PORT d[10] (975:975:975) (1114:1114:1114)) - (PORT d[11] (1153:1153:1153) (1319:1319:1319)) - (PORT d[12] (1441:1441:1441) (1644:1644:1644)) - (PORT clk (1099:1099:1099) (1116:1116:1116)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1465:1465:1465) (1612:1612:1612)) - (PORT clk (1099:1099:1099) (1116:1116:1116)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1101:1101:1101) (1118:1118:1118)) - (PORT d[0] (2068:2068:2068) (1911:1911:1911)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1102:1102:1102) (1119:1119:1119)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1102:1102:1102) (1119:1119:1119)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1102:1102:1102) (1119:1119:1119)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1102:1102:1102) (1119:1119:1119)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1056:1056:1056) (1075:1075:1075)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1143:1143:1143) (1275:1275:1275)) - (PORT clk (1061:1061:1061) (1078:1078:1078)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2565:2565:2565) (2902:2902:2902)) - (PORT d[1] (2379:2379:2379) (2698:2698:2698)) - (PORT d[2] (2538:2538:2538) (2875:2875:2875)) - (PORT d[3] (2480:2480:2480) (2809:2809:2809)) - (PORT d[4] (2379:2379:2379) (2694:2694:2694)) - (PORT d[5] (2552:2552:2552) (2893:2893:2893)) - (PORT d[6] (2642:2642:2642) (3020:3020:3020)) - (PORT d[7] (2531:2531:2531) (2886:2886:2886)) - (PORT d[8] (2543:2543:2543) (2891:2891:2891)) - (PORT d[9] (2572:2572:2572) (2952:2952:2952)) - (PORT d[10] (2438:2438:2438) (2753:2753:2753)) - (PORT d[11] (2584:2584:2584) (2914:2914:2914)) - (PORT d[12] (2592:2592:2592) (2978:2978:2978)) - (PORT clk (1058:1058:1058) (1077:1077:1077)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1061:1061:1061) (1078:1078:1078)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1062:1062:1062) (1079:1079:1079)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1062:1062:1062) (1079:1079:1079)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1062:1062:1062) (1079:1079:1079)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1062:1062:1062) (1079:1079:1079)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1076:1076:1076)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (472:472:472) (563:563:563)) - (PORT datab (107:107:107) (136:136:136)) - (PORT datac (89:89:89) (109:109:109)) - (PORT datad (831:831:831) (945:945:945)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~108) - (DELAY - (ABSOLUTE - (PORT dataa (852:852:852) (995:995:995)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (904:904:904) (1055:1055:1055)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (172:172:172) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~95) - (DELAY - (ABSOLUTE - (PORT dataa (112:112:112) (148:148:148)) - (PORT datab (765:765:765) (879:879:879)) - (PORT datac (730:730:730) (844:844:844)) - (PORT datad (179:179:179) (205:205:205)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~96) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (1024:1024:1024)) - (PORT datab (761:761:761) (876:876:876)) - (PORT datac (610:610:610) (720:720:720)) - (PORT datad (161:161:161) (189:189:189)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) - (DELAY - (ABSOLUTE - (PORT dataa (544:544:544) (647:647:647)) - (PORT datab (926:926:926) (1052:1052:1052)) - (PORT datac (134:134:134) (171:171:171)) - (PORT datad (486:486:486) (557:557:557)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (432:432:432) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (138:138:138) (177:177:177)) - (PORT datab (356:356:356) (436:436:436)) - (PORT datad (112:112:112) (135:135:135)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (545:545:545) (629:629:629)) - (PORT datab (498:498:498) (571:571:571)) - (PORT datac (499:499:499) (573:573:573)) - (PORT datad (501:501:501) (577:577:577)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[3\]) (DELAY (ABSOLUTE (PORT clk (906:906:906) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (895:895:895)) - (PORT ena (780:780:780) (849:849:849)) + (PORT clrn (918:918:918) (901:901:901)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~4) + (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) (DELAY (ABSOLUTE - (PORT dataa (829:829:829) (969:969:969)) - (PORT datab (649:649:649) (747:747:747)) - (PORT datac (667:667:667) (790:790:790)) - (PORT datad (778:778:778) (892:892:892)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datab (537:537:537) (647:647:647)) + (PORT datac (681:681:681) (825:825:825)) + (PORT datad (522:522:522) (627:627:627)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -49956,12 +50042,12 @@ (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) (DELAY (ABSOLUTE - (PORT dataa (505:505:505) (598:598:598)) - (PORT datab (115:115:115) (144:144:144)) - (PORT datac (488:488:488) (553:553:553)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT dataa (107:107:107) (141:141:141)) + (PORT datab (819:819:819) (955:955:955)) + (PORT datad (646:646:646) (743:743:743)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -49970,9 +50056,9 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (757:757:757) (876:876:876)) - (PORT datab (339:339:339) (406:406:406)) - (PORT datad (94:94:94) (113:113:113)) + (PORT dataa (655:655:655) (770:770:770)) + (PORT datab (446:446:446) (514:514:514)) + (PORT datad (90:90:90) (107:107:107)) (IOPATH dataa combout (172:172:172) (165:165:165)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -49984,11 +50070,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (905:905:905)) + (PORT clk (918:918:918) (905:905:905)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (306:306:306) (344:344:344)) - (PORT sload (575:575:575) (630:630:630)) - (PORT ena (419:419:419) (435:435:435)) + (PORT asdata (368:368:368) (414:414:414)) + (PORT sload (758:758:758) (851:851:851)) + (PORT ena (778:778:778) (852:852:852)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -50001,43 +50087,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~59) + (INSTANCE D\[0\]\~66) (DELAY (ABSOLUTE - (PORT dataa (476:476:476) (559:559:559)) - (PORT datab (639:639:639) (743:743:743)) - (PORT datac (94:94:94) (117:117:117)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datab (488:488:488) (566:566:566)) + (PORT datac (490:490:490) (568:568:568)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH datab combout (188:188:188) (177:177:177)) (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~60) + (INSTANCE D\[0\]\~67) (DELAY (ABSOLUTE - (PORT dataa (504:504:504) (597:597:597)) - (PORT datab (337:337:337) (405:405:405)) - (PORT datac (901:901:901) (1028:1028:1028)) - (PORT datad (168:168:168) (197:197:197)) + (PORT dataa (1552:1552:1552) (1783:1783:1783)) + (PORT datab (808:808:808) (947:947:947)) + (PORT datac (840:840:840) (960:960:960)) + (PORT datad (157:157:157) (183:183:183)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~61) + (INSTANCE D\[0\]\~121) (DELAY (ABSOLUTE - (PORT dataa (778:778:778) (898:898:898)) - (PORT datac (455:455:455) (518:518:518)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (186:186:186) (175:175:175)) + (PORT dataa (1464:1464:1464) (1696:1696:1696)) + (PORT datab (1118:1118:1118) (1320:1320:1320)) + (PORT datac (1569:1569:1569) (1833:1833:1833)) + (PORT datad (1388:1388:1388) (1582:1582:1582)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -50045,13 +50133,57 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~62) + (INSTANCE D\[1\]\~68) (DELAY (ABSOLUTE - (PORT dataa (781:781:781) (899:899:899)) - (PORT datab (539:539:539) (634:634:634)) - (PORT datac (551:551:551) (659:659:659)) - (PORT datad (90:90:90) (106:106:106)) + (PORT datab (368:368:368) (435:435:435)) + (PORT datac (606:606:606) (688:688:688)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (1553:1553:1553) (1785:1785:1785)) + (PORT datab (529:529:529) (624:624:624)) + (PORT datac (839:839:839) (959:959:959)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~70) + (DELAY + (ABSOLUTE + (PORT datab (665:665:665) (766:766:766)) + (PORT datac (456:456:456) (528:528:528)) + (PORT datad (167:167:167) (198:198:198)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (1238:1238:1238) (1415:1415:1415)) + (PORT datab (330:330:330) (383:383:383)) + (PORT datac (947:947:947) (1099:1099:1099)) + (PORT datad (90:90:90) (107:107:107)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -50061,13 +50193,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~63) + (INSTANCE D\[3\]\~83) (DELAY (ABSOLUTE - (PORT dataa (191:191:191) (238:238:238)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (94:94:94) (114:114:114)) - (IOPATH dataa combout (186:186:186) (175:175:175)) + (PORT dataa (1551:1551:1551) (1782:1782:1782)) + (PORT datac (507:507:507) (601:601:601)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (233:233:233)) + (PORT datab (514:514:514) (594:594:594)) + (PORT datac (171:171:171) (197:197:197)) + (PORT datad (170:170:170) (200:200:200)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -50075,12 +50221,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~64) + (INSTANCE D\[4\]\~95) (DELAY (ABSOLUTE - (PORT dataa (219:219:219) (286:286:286)) - (PORT datab (125:125:125) (156:156:156)) - (PORT datac (613:613:613) (702:702:702)) + (PORT dataa (515:515:515) (600:600:600)) + (PORT datab (497:497:497) (575:575:575)) + (PORT datac (95:95:95) (119:119:119)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~96) + (DELAY + (ABSOLUTE + (PORT dataa (715:715:715) (850:850:850)) + (PORT datab (227:227:227) (273:273:273)) + (PORT datac (1237:1237:1237) (1422:1422:1422)) (PORT datad (91:91:91) (109:109:109)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) @@ -50091,27 +50251,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~75) + (INSTANCE D\[5\]\~126) (DELAY (ABSOLUTE - (PORT dataa (113:113:113) (148:148:148)) - (PORT datac (730:730:730) (844:844:844)) - (PORT datad (105:105:105) (123:123:123)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (996:996:996) (1155:1155:1155)) + (PORT datab (1740:1740:1740) (2035:2035:2035)) + (PORT datac (331:331:331) (383:383:383)) + (PORT datad (164:164:164) (194:194:194)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~76) + (INSTANCE D\[5\]\~98) (DELAY (ABSOLUTE - (PORT dataa (617:617:617) (736:736:736)) - (PORT datab (634:634:634) (729:729:729)) - (PORT datac (838:838:838) (949:949:949)) - (PORT datad (167:167:167) (195:195:195)) + (PORT dataa (680:680:680) (795:795:795)) + (PORT datab (360:360:360) (420:420:420)) + (PORT datac (1380:1380:1380) (1577:1577:1577)) + (PORT datad (92:92:92) (109:109:109)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -50121,42 +50283,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~82) + (INSTANCE D\[6\]\~105) (DELAY (ABSOLUTE - (PORT dataa (479:479:479) (563:563:563)) - (PORT datab (877:877:877) (1024:1024:1024)) - (PORT datad (96:96:96) (115:115:115)) - (IOPATH dataa combout (172:172:172) (165:165:165)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (508:508:508) (602:602:602)) - (PORT datab (788:788:788) (926:926:926)) - (PORT datac (898:898:898) (1025:1025:1025)) - (PORT datad (168:168:168) (198:198:198)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~92) - (DELAY - (ABSOLUTE - (PORT datab (728:728:728) (837:837:837)) - (PORT datac (95:95:95) (118:118:118)) - (PORT datad (94:94:94) (113:113:113)) + (PORT datab (471:471:471) (550:550:550)) + (PORT datac (186:186:186) (221:221:221)) + (PORT datad (179:179:179) (206:206:206)) (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -50165,29 +50297,75 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~93) + (INSTANCE D\[6\]\~106) (DELAY (ABSOLUTE - (PORT dataa (505:505:505) (597:597:597)) - (PORT datab (479:479:479) (578:578:578)) - (PORT datac (901:901:901) (1028:1028:1028)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (687:687:687) (806:806:806)) + (PORT datab (329:329:329) (382:382:382)) + (PORT datac (1226:1226:1226) (1395:1395:1395)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~128) + (DELAY + (ABSOLUTE + (PORT dataa (1586:1586:1586) (1861:1861:1861)) + (PORT datab (1112:1112:1112) (1291:1291:1291)) + (PORT datac (95:95:95) (119:119:119)) + (PORT datad (337:337:337) (394:394:394)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (182:182:182) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~107) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (794:794:794)) + (PORT datab (1407:1407:1407) (1607:1607:1607)) + (PORT datac (179:179:179) (208:208:208)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (PORT datac (463:463:463) (526:526:526)) + (PORT datad (124:124:124) (165:165:165)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|nM1_int\~3) (DELAY (ABSOLUTE - (PORT datab (789:789:789) (939:939:939)) - (PORT datac (1301:1301:1301) (1509:1509:1509)) - (PORT datad (288:288:288) (332:332:332)) - (IOPATH datab combout (166:166:166) (167:167:167)) + (PORT datab (389:389:389) (469:469:469)) + (PORT datac (352:352:352) (426:426:426)) + (PORT datad (318:318:318) (387:387:387)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -50198,10 +50376,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_16) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (923:923:923)) + (PORT clk (906:906:906) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (689:689:689) (767:767:767)) + (PORT clrn (918:918:918) (901:901:901)) + (PORT ena (646:646:646) (704:704:704)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50216,7 +50394,7 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17\~feeder) (DELAY (ABSOLUTE - (PORT datad (133:133:133) (171:171:171)) + (PORT datad (367:367:367) (438:438:438)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -50226,10 +50404,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17) (DELAY (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) + (PORT clk (915:915:915) (900:900:900)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (704:704:704) (789:789:789)) + (PORT clrn (917:917:917) (898:898:898)) + (PORT ena (667:667:667) (723:723:723)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50244,10 +50422,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_mreq_ff2) (DELAY (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) - (PORT asdata (298:298:298) (340:340:340)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (704:704:704) (789:789:789)) + (PORT clk (915:915:915) (900:900:900)) + (PORT asdata (301:301:301) (343:343:343)) + (PORT clrn (917:917:917) (898:898:898)) + (PORT ena (667:667:667) (723:723:723)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50262,9 +50440,9 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~0) (DELAY (ABSOLUTE - (PORT dataa (135:135:135) (188:188:188)) - (PORT datab (137:137:137) (187:187:187)) - (PORT datad (117:117:117) (153:153:153)) + (PORT dataa (508:508:508) (602:602:602)) + (PORT datab (138:138:138) (188:188:188)) + (PORT datad (122:122:122) (160:160:160)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -50277,12 +50455,13 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~1) (DELAY (ABSOLUTE - (PORT dataa (498:498:498) (603:603:603)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datad (96:96:96) (115:115:115)) + (PORT dataa (136:136:136) (189:189:189)) + (PORT datab (142:142:142) (195:195:195)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (94:94:94) (114:114:114)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -50310,9 +50489,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[0\]) (DELAY (ABSOLUTE - (PORT clk (1140:1140:1140) (1102:1102:1102)) + (PORT clk (1141:1141:1141) (1103:1103:1103)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (913:913:913)) + (PORT clrn (898:898:898) (902:902:902)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50326,8 +50505,8 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (136:136:136) (188:188:188)) - (PORT datab (135:135:135) (186:186:186)) + (PORT dataa (214:214:214) (273:273:273)) + (PORT datab (136:136:136) (186:186:186)) (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datab combout (190:190:190) (181:181:181)) @@ -50341,9 +50520,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1140:1140:1140) (1102:1102:1102)) + (PORT clk (1141:1141:1141) (1103:1103:1103)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (913:913:913)) + (PORT clrn (898:898:898) (902:902:902)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50357,7 +50536,7 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]\~7) (DELAY (ABSOLUTE - (PORT dataa (135:135:135) (187:187:187)) + (PORT dataa (136:136:136) (187:187:187)) (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -50371,9 +50550,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1140:1140:1140) (1102:1102:1102)) + (PORT clk (1141:1141:1141) (1103:1103:1103)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (913:913:913)) + (PORT clrn (898:898:898) (902:902:902)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50387,9 +50566,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[3\]\~9) (DELAY (ABSOLUTE - (PORT datab (135:135:135) (185:185:185)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (137:137:137) (188:188:188)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -50401,66 +50580,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1140:1140:1140) (1102:1102:1102)) + (PORT clk (1141:1141:1141) (1103:1103:1103)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) - (DELAY - (ABSOLUTE - (PORT datab (134:134:134) (184:184:184)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1140:1140:1140) (1102:1102:1102)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT datad (122:122:122) (161:161:161)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1140:1140:1140) (1102:1102:1102)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (913:913:913)) + (PORT clrn (898:898:898) (902:902:902)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50474,10 +50596,10 @@ (INSTANCE ula_\|i2c_loader_\|WideAnd0\~0) (DELAY (ABSOLUTE - (PORT dataa (137:137:137) (190:190:190)) - (PORT datab (137:137:137) (188:188:188)) - (PORT datac (121:121:121) (164:164:164)) - (PORT datad (123:123:123) (162:162:162)) + (PORT dataa (136:136:136) (189:189:189)) + (PORT datab (143:143:143) (192:192:192)) + (PORT datac (121:121:121) (163:163:163)) + (PORT datad (122:122:122) (161:161:161)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -50485,29 +50607,104 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (186:186:186)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1141:1141:1141) (1103:1103:1103)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (898:898:898) (902:902:902)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) + (DELAY + (ABSOLUTE + (PORT datad (121:121:121) (160:160:160)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1141:1141:1141) (1103:1103:1103)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (898:898:898) (902:902:902)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|WideAnd0) (DELAY (ABSOLUTE - (PORT datab (135:135:135) (185:185:185)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (122:122:122) (161:161:161)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datab (107:107:107) (136:136:136)) + (PORT datac (122:122:122) (165:165:165)) + (PORT datad (122:122:122) (160:160:160)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|scl_out\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT ena (546:546:546) (522:522:522)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2c_loader_\|state\.Idle) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) + (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT ena (810:810:810) (754:754:754)) + (PORT clrn (898:898:898) (902:902:902)) + (PORT ena (851:851:851) (793:793:793)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50522,7 +50719,7 @@ (INSTANCE ula_\|i2c_loader_\|phase\~0) (DELAY (ABSOLUTE - (PORT datad (132:132:132) (171:171:171)) + (PORT datad (217:217:217) (270:270:270)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -50533,10 +50730,10 @@ (INSTANCE ula_\|i2c_loader_\|phase\[0\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) + (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT ena (810:810:810) (754:754:754)) + (PORT clrn (898:898:898) (902:902:902)) + (PORT ena (851:851:851) (793:793:793)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50551,8 +50748,8 @@ (INSTANCE ula_\|i2c_loader_\|phase\~1) (DELAY (ABSOLUTE - (PORT datab (183:183:183) (249:249:249)) - (PORT datad (135:135:135) (174:174:174)) + (PORT datab (235:235:235) (295:295:295)) + (PORT datad (206:206:206) (261:261:261)) (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -50562,12 +50759,146 @@ (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2c_loader_\|phase\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (898:898:898) (902:902:902)) + (PORT ena (463:463:463) (442:442:442)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|Mux42\~0) + (DELAY + (ABSOLUTE + (PORT datab (241:241:241) (306:306:306)) + (PORT datac (147:147:147) (196:196:196)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbyte\~0) + (DELAY + (ABSOLUTE + (PORT datab (248:248:248) (308:308:308)) + (PORT datac (298:298:298) (359:359:359)) + (PORT datad (467:467:467) (552:552:552)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~4) + (DELAY + (ABSOLUTE + (PORT datad (377:377:377) (457:457:457)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbyte\~4) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (276:276:276)) + (PORT datab (341:341:341) (413:413:413)) + (PORT datad (380:380:380) (463:463:463)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) (DELAY (ABSOLUTE (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT ena (810:810:810) (754:754:754)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (248:248:248) (308:308:308)) + (PORT datac (314:314:314) (371:371:371)) + (PORT datad (156:156:156) (200:200:200)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (315:315:315) (382:382:382)) + (PORT datac (342:342:342) (413:413:413)) + (PORT datad (455:455:455) (539:539:539)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (414:414:414)) + (PORT datab (336:336:336) (387:387:387)) + (PORT datac (338:338:338) (415:415:415)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1112:1112:1112) (1141:1141:1141)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (903:903:903) (906:906:906)) + (PORT ena (637:637:637) (687:687:687)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50582,31 +50913,69 @@ (INSTANCE ula_\|i2c_loader_\|nbit\~5) (DELAY (ABSOLUTE - (PORT dataa (338:338:338) (412:412:412)) + (PORT dataa (395:395:395) (480:480:480)) + (PORT datad (205:205:205) (257:257:257)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) (DELAY (ABSOLUTE - (PORT datab (166:166:166) (225:225:225)) - (IOPATH datab combout (192:192:192) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT clk (914:914:914) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (903:903:903) (906:906:906)) + (PORT ena (654:654:654) (717:717:717)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (192:192:192)) + (PORT datab (144:144:144) (197:197:197)) + (PORT datad (198:198:198) (249:249:249)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|Mux42\~0) + (INSTANCE ula_\|i2c_loader_\|state\~27) (DELAY (ABSOLUTE - (PORT datac (381:381:381) (465:465:465)) - (PORT datad (369:369:369) (445:445:445)) + (PORT datab (239:239:239) (303:303:303)) + (PORT datac (148:148:148) (197:197:197)) + (PORT datad (347:347:347) (421:421:421)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~24) + (DELAY + (ABSOLUTE + (PORT datab (249:249:249) (309:309:309)) + (PORT datac (316:316:316) (373:373:373)) + (PORT datad (158:158:158) (201:201:201)) + (IOPATH datab combout (166:166:166) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -50614,28 +50983,174 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\~4) + (INSTANCE ula_\|i2c_loader_\|state\~26) (DELAY (ABSOLUTE - (PORT dataa (157:157:157) (214:214:214)) - (PORT datab (187:187:187) (253:253:253)) - (PORT datad (340:340:340) (406:406:406)) - (IOPATH dataa combout (181:181:181) (193:193:193)) + (PORT datab (240:240:240) (304:304:304)) + (PORT datac (148:148:148) (197:197:197)) + (PORT datad (172:172:172) (203:203:203)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) + (DELAY + (ABSOLUTE + (PORT datab (105:105:105) (134:134:134)) + (PORT datad (92:92:92) (109:109:109)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Data) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (356:356:356) (384:384:384)) + (PORT clrn (898:898:898) (902:902:902)) + (PORT sload (460:460:460) (529:529:529)) + (PORT ena (851:851:851) (793:793:793)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~0) + (DELAY + (ABSOLUTE + (PORT dataa (397:397:397) (482:482:482)) + (PORT datab (140:140:140) (194:194:194)) + (PORT datad (202:202:202) (254:254:254)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (903:903:903) (906:906:906)) + (PORT ena (654:654:654) (717:717:717)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (193:193:193)) + (PORT datab (211:211:211) (273:273:273)) + (PORT datac (473:473:473) (554:554:554)) + (PORT datad (131:131:131) (174:174:174)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) + (DELAY + (ABSOLUTE + (PORT dataa (148:148:148) (202:202:202)) + (PORT datab (171:171:171) (225:225:225)) + (PORT datac (297:297:297) (357:357:357)) + (PORT datad (330:330:330) (393:393:393)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (415:415:415)) + (PORT datab (351:351:351) (435:435:435)) + (PORT datac (341:341:341) (412:412:412)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (392:392:392)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datad (456:456:456) (540:540:540)) + (IOPATH dataa combout (181:181:181) (175:175:175)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Ack) + (DELAY + (ABSOLUTE + (PORT clk (1121:1121:1121) (1153:1153:1153)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (900:900:900) (904:904:904)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~7) (DELAY (ABSOLUTE - (PORT datab (158:158:158) (213:213:213)) - (PORT datac (299:299:299) (354:354:354)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datac (353:353:353) (439:439:439)) + (PORT datad (230:230:230) (282:282:282)) (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -50653,13 +51168,13 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (155:155:155) (212:212:212)) - (PORT datab (148:148:148) (198:198:198)) - (PORT datac (168:168:168) (228:228:228)) - (PORT datad (278:278:278) (297:297:297)) + (PORT dataa (220:220:220) (277:277:277)) + (PORT datab (404:404:404) (492:492:492)) + (PORT datac (131:131:131) (173:173:173)) + (PORT datad (274:274:274) (291:291:291)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -50669,13 +51184,13 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~2) (DELAY (ABSOLUTE - (PORT dataa (352:352:352) (429:429:429)) - (PORT datab (341:341:341) (398:398:398)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (172:172:172) (163:163:163)) + (PORT dataa (176:176:176) (214:214:214)) + (PORT datab (344:344:344) (402:402:402)) + (PORT datac (321:321:321) (386:386:386)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (165:165:165) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -50685,30 +51200,30 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~3) (DELAY (ABSOLUTE - (PORT datab (445:445:445) (522:522:522)) - (PORT datac (222:222:222) (278:278:278)) - (PORT datad (91:91:91) (108:108:108)) + (PORT dataa (339:339:339) (423:423:423)) + (PORT datab (325:325:325) (375:375:375)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (166:166:166) (159:159:159)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) + (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]) (DELAY (ABSOLUTE (PORT clk (911:911:911) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT ena (422:422:422) (449:449:449)) + (PORT asdata (353:353:353) (387:387:387)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT ena (421:421:421) (449:449:449)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) @@ -50717,12 +51232,12 @@ (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) (DELAY (ABSOLUTE - (PORT dataa (369:369:369) (449:449:449)) - (PORT datab (381:381:381) (459:459:459)) - (PORT datac (138:138:138) (185:185:185)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT datab (247:247:247) (307:307:307)) + (PORT datac (312:312:312) (368:368:368)) + (PORT datad (154:154:154) (196:196:196)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -50731,11 +51246,11 @@ (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) (DELAY (ABSOLUTE - (PORT dataa (310:310:310) (366:366:366)) - (PORT datab (140:140:140) (177:177:177)) - (PORT datad (174:174:174) (205:205:205)) - (IOPATH dataa combout (181:181:181) (175:175:175)) - (IOPATH datab combout (166:166:166) (158:158:158)) + (PORT dataa (354:354:354) (416:416:416)) + (PORT datab (332:332:332) (383:383:383)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (182:182:182) (177:177:177)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -50746,9 +51261,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Stop) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) + (PORT clk (1121:1121:1121) (1153:1153:1153)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) + (PORT clrn (900:900:900) (904:904:904)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50759,128 +51274,44 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) (DELAY (ABSOLUTE - (PORT dataa (159:159:159) (218:218:218)) - (PORT datab (142:142:142) (195:195:195)) - (PORT datac (127:127:127) (171:171:171)) - (PORT datad (295:295:295) (350:350:350)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~0) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (413:413:413)) - (PORT datab (142:142:142) (194:194:194)) - (PORT datad (128:128:128) (170:170:170)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (182:182:182) (193:193:193)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (913:913:913)) - (PORT ena (612:612:612) (664:664:664)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~0) - (DELAY - (ABSOLUTE - (PORT dataa (141:141:141) (194:194:194)) - (PORT datab (134:134:134) (185:185:185)) - (PORT datac (320:320:320) (383:383:383)) - (PORT datad (129:129:129) (172:172:172)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (228:228:228)) - (PORT datab (187:187:187) (224:224:224)) - (PORT datac (490:490:490) (579:579:579)) - (PORT datad (167:167:167) (198:198:198)) + (PORT dataa (148:148:148) (201:201:201)) + (PORT datab (474:474:474) (568:568:568)) + (PORT datac (424:424:424) (499:499:499)) + (PORT datad (467:467:467) (552:552:552)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) + (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) (DELAY (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (297:297:297) (354:354:354)) - (PORT datad (232:232:232) (290:290:290)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (182:182:182) (177:177:177)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT datab (160:160:160) (215:215:215)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Ack) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (158:158:158) (214:214:214)) - (PORT datab (146:146:146) (196:196:196)) - (PORT datac (170:170:170) (230:230:230)) - (PORT datad (278:278:278) (297:297:297)) + (PORT dataa (312:312:312) (376:376:376)) + (PORT datab (490:490:490) (585:585:585)) + (PORT datac (324:324:324) (388:388:388)) + (PORT datad (379:379:379) (406:406:406)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -50890,13 +51321,13 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~18) (DELAY (ABSOLUTE - (PORT dataa (218:218:218) (276:276:276)) - (PORT datab (304:304:304) (366:366:366)) - (PORT datac (448:448:448) (524:524:524)) - (PORT datad (159:159:159) (185:185:185)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (320:320:320) (376:376:376)) + (PORT datab (239:239:239) (292:292:292)) + (PORT datac (419:419:419) (490:490:490)) + (PORT datad (93:93:93) (112:112:112)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -50906,12 +51337,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) + (PORT clk (1106:1106:1106) (1131:1131:1131)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (593:593:593) (659:659:659)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT sload (571:571:571) (535:535:535)) - (PORT ena (408:408:408) (429:429:429)) + (PORT asdata (1454:1454:1454) (1619:1619:1619)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT sload (865:865:865) (791:791:791)) + (PORT ena (422:422:422) (450:450:450)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50928,7 +51359,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]\~10) (DELAY (ABSOLUTE - (PORT datab (161:161:161) (217:217:217)) + (PORT datab (160:160:160) (217:217:217)) (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -50942,12 +51373,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) + (PORT clk (1106:1106:1106) (1131:1131:1131)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (594:594:594) (660:660:660)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT sload (571:571:571) (535:535:535)) - (PORT ena (408:408:408) (429:429:429)) + (PORT asdata (1455:1455:1455) (1620:1620:1620)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT sload (865:865:865) (791:791:791)) + (PORT ena (422:422:422) (450:450:450)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50964,9 +51395,9 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]\~12) (DELAY (ABSOLUTE - (PORT datab (156:156:156) (208:208:208)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (166:166:166) (229:229:229)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -50978,11 +51409,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) + (PORT clk (1106:1106:1106) (1131:1131:1131)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT sload (571:571:571) (535:535:535)) - (PORT ena (408:408:408) (429:429:429)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT sload (865:865:865) (791:791:791)) + (PORT ena (422:422:422) (450:450:450)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50999,7 +51430,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]\~14) (DELAY (ABSOLUTE - (PORT datab (165:165:165) (221:221:221)) + (PORT datab (163:163:163) (217:217:217)) (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -51013,12 +51444,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) + (PORT clk (1106:1106:1106) (1131:1131:1131)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (595:595:595) (661:661:661)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT sload (571:571:571) (535:535:535)) - (PORT ena (408:408:408) (429:429:429)) + (PORT asdata (1455:1455:1455) (1620:1620:1620)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT sload (865:865:865) (791:791:791)) + (PORT ena (422:422:422) (450:450:450)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51035,29 +51466,13 @@ (INSTANCE ula_\|i2c_loader_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (225:225:225) (289:289:289)) - (PORT datab (163:163:163) (218:218:218)) - (PORT datac (151:151:151) (201:201:201)) - (PORT datad (154:154:154) (202:202:202)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) - (DELAY - (ABSOLUTE - (PORT dataa (389:389:389) (476:476:476)) - (PORT datab (143:143:143) (196:196:196)) - (PORT datac (384:384:384) (469:469:469)) - (PORT datad (141:141:141) (185:185:185)) + (PORT dataa (229:229:229) (295:295:295)) + (PORT datab (161:161:161) (221:221:221)) + (PORT datac (152:152:152) (212:212:212)) + (PORT datad (152:152:152) (197:197:197)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -51067,7 +51482,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]\~16) (DELAY (ABSOLUTE - (PORT dataa (170:170:170) (228:228:228)) + (PORT dataa (165:165:165) (226:226:226)) (IOPATH dataa combout (188:188:188) (193:193:193)) (IOPATH cin combout (187:187:187) (204:204:204)) ) @@ -51078,11 +51493,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) + (PORT clk (1106:1106:1106) (1131:1131:1131)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT sload (571:571:571) (535:535:535)) - (PORT ena (408:408:408) (429:429:429)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT sload (865:865:865) (791:791:791)) + (PORT ena (422:422:422) (450:450:450)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51096,12 +51511,42 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~3) (DELAY (ABSOLUTE - (PORT datab (329:329:329) (385:385:385)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (353:353:353) (421:421:421)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (177:177:177) (214:214:214)) + (PORT datad (210:210:210) (259:259:259)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|scl_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (273:273:273)) + (PORT datab (252:252:252) (312:312:312)) + (PORT datad (463:463:463) (547:547:547)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~4) + (DELAY + (ABSOLUTE + (PORT dataa (286:286:286) (330:330:330)) + (PORT datab (148:148:148) (198:198:198)) + (PORT datac (141:141:141) (187:187:187)) + (PORT datad (347:347:347) (421:421:421)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -51110,31 +51555,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~2) + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~5) (DELAY (ABSOLUTE - (PORT dataa (117:117:117) (149:149:149)) - (PORT datab (155:155:155) (209:209:209)) - (PORT datac (127:127:127) (171:171:171)) - (PORT datad (250:250:250) (281:281:281)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) - (DELAY - (ABSOLUTE - (PORT dataa (175:175:175) (212:212:212)) - (PORT datab (142:142:142) (181:181:181)) - (PORT datac (144:144:144) (194:194:194)) - (PORT datad (222:222:222) (275:275:275)) + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (229:229:229) (292:292:292)) + (PORT datac (140:140:140) (189:189:189)) + (PORT datad (120:120:120) (145:145:145)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -51142,14 +51571,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~3) + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~6) (DELAY (ABSOLUTE - (PORT dataa (176:176:176) (218:218:218)) - (PORT datab (310:310:310) (366:366:366)) - (PORT datad (91:91:91) (107:107:107)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (PORT dataa (488:488:488) (569:569:569)) + (PORT datab (332:332:332) (390:390:390)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -51162,7 +51591,7 @@ (ABSOLUTE (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) + (PORT clrn (898:898:898) (902:902:902)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51176,11 +51605,11 @@ (INSTANCE ula_\|i2c_loader_\|state\~25) (DELAY (ABSOLUTE - (PORT dataa (142:142:142) (196:196:196)) - (PORT datab (144:144:144) (183:183:183)) - (PORT datad (219:219:219) (272:272:272)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (176:176:176)) + (PORT dataa (135:135:135) (172:172:172)) + (PORT datab (148:148:148) (198:198:198)) + (PORT datad (214:214:214) (267:267:267)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -51193,273 +51622,8 @@ (ABSOLUTE (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) - (PORT ena (654:654:654) (617:617:617)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\~0) - (DELAY - (ABSOLUTE - (PORT datab (181:181:181) (247:247:247)) - (PORT datad (333:333:333) (398:398:398)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT ena (422:422:422) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (369:369:369) (449:449:449)) - (PORT datac (366:366:366) (437:437:437)) - (PORT datad (233:233:233) (292:292:292)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (549:549:549) (642:642:642)) - (PORT datab (260:260:260) (324:324:324)) - (PORT datac (142:142:142) (188:188:188)) - (PORT datad (359:359:359) (431:431:431)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (314:314:314) (372:372:372)) - (PORT datad (167:167:167) (197:197:197)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (178:178:178) (221:221:221)) - (PORT datab (139:139:139) (177:177:177)) - (PORT datac (292:292:292) (341:341:341)) - (PORT datad (226:226:226) (279:279:279)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1137:1137:1137)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (913:913:913)) - (PORT ena (595:595:595) (634:634:634)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~6) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (408:408:408)) - (PORT datad (131:131:131) (174:174:174)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (913:913:913)) - (PORT ena (612:612:612) (664:664:664)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~1) - (DELAY - (ABSOLUTE - (PORT dataa (140:140:140) (196:196:196)) - (PORT datab (137:137:137) (187:187:187)) - (PORT datad (132:132:132) (175:175:175)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~27) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (471:471:471)) - (PORT datac (381:381:381) (465:465:465)) - (PORT datad (249:249:249) (280:280:280)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~24) - (DELAY - (ABSOLUTE - (PORT dataa (369:369:369) (450:450:450)) - (PORT datab (382:382:382) (459:459:459)) - (PORT datac (135:135:135) (181:181:181)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~26) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (475:475:475)) - (PORT datac (384:384:384) (468:468:468)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (139:139:139)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Data) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (305:305:305) (334:334:334)) - (PORT clrn (907:907:907) (913:913:913)) - (PORT sload (461:461:461) (529:529:529)) - (PORT ena (654:654:654) (617:617:617)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|scl_out\~0) - (DELAY - (ABSOLUTE - (PORT datab (158:158:158) (212:212:212)) - (PORT datac (311:311:311) (375:375:375)) - (PORT datad (126:126:126) (169:169:169)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|scl_out\~_Duplicate_1) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT ena (810:810:810) (754:754:754)) + (PORT clrn (898:898:898) (902:902:902)) + (PORT ena (851:851:851) (793:793:793)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51474,13 +51638,13 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~1) (DELAY (ABSOLUTE - (PORT dataa (351:351:351) (427:427:427)) - (PORT datab (184:184:184) (250:250:250)) - (PORT datac (141:141:141) (190:190:190)) - (PORT datad (117:117:117) (155:155:155)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (132:132:132) (183:183:183)) + (PORT datab (371:371:371) (458:458:458)) + (PORT datac (323:323:323) (388:388:388)) + (PORT datad (380:380:380) (463:463:463)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -51490,11 +51654,11 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~2) (DELAY (ABSOLUTE - (PORT dataa (345:345:345) (403:403:403)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datad (334:334:334) (399:399:399)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (176:176:176)) + (PORT dataa (105:105:105) (138:138:138)) + (PORT datac (320:320:320) (384:384:384)) + (PORT datad (108:108:108) (128:128:128)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -51505,9 +51669,9 @@ (DELAY (ABSOLUTE (PORT clk (868:868:868) (887:887:887)) - (PORT d (555:555:555) (509:509:509)) - (PORT aload (1017:1017:1017) (1062:1062:1062)) - (PORT ena (487:487:487) (454:454:454)) + (PORT d (556:556:556) (509:509:509)) + (PORT aload (1008:1008:1008) (1051:1051:1051)) + (PORT ena (382:382:382) (363:363:363)) (IOPATH (posedge clk) q (345:345:345) (339:339:339)) (IOPATH (posedge aload) q (286:286:286) (280:280:280)) ) @@ -51526,8 +51690,8 @@ (ABSOLUTE (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT ena (810:810:810) (754:754:754)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT ena (546:546:546) (522:522:522)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51537,71 +51701,15 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) - (DELAY - (ABSOLUTE - (PORT datac (473:473:473) (559:559:559)) - (PORT datad (326:326:326) (387:387:387)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|Mux35\~0) (DELAY (ABSOLUTE - (PORT dataa (234:234:234) (295:295:295)) - (PORT datab (239:239:239) (296:296:296)) - (PORT datac (205:205:205) (252:252:252)) - (PORT datad (209:209:209) (257:257:257)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) - (DELAY - (ABSOLUTE - (PORT dataa (170:170:170) (230:230:230)) - (PORT datab (162:162:162) (218:218:218)) - (PORT datac (153:153:153) (206:206:206)) - (PORT datad (143:143:143) (186:186:186)) - (IOPATH dataa combout (192:192:192) (184:184:184)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) - (DELAY - (ABSOLUTE - (PORT datac (153:153:153) (206:206:206)) - (PORT datad (143:143:143) (185:185:185)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (139:139:139)) - (PORT datab (167:167:167) (225:225:225)) - (PORT datac (151:151:151) (200:200:200)) - (PORT datad (105:105:105) (122:122:122)) + (PORT dataa (228:228:228) (294:294:294)) + (PORT datab (158:158:158) (217:217:217)) + (PORT datac (147:147:147) (205:205:205)) + (PORT datad (147:147:147) (191:191:191)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -51611,12 +51719,88 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~24) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) (DELAY (ABSOLUTE - (PORT datab (238:238:238) (295:295:295)) - (PORT datac (474:474:474) (560:560:560)) - (PORT datad (220:220:220) (268:268:268)) + (PORT datac (318:318:318) (383:383:383)) + (PORT datad (461:461:461) (545:545:545)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (296:296:296)) + (PORT datab (162:162:162) (222:222:222)) + (PORT datac (156:156:156) (211:211:211)) + (PORT datad (153:153:153) (198:198:198)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) + (DELAY + (ABSOLUTE + (PORT dataa (169:169:169) (235:235:235)) + (PORT datab (302:302:302) (344:344:344)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (147:147:147) (192:192:192)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) + (DELAY + (ABSOLUTE + (PORT dataa (170:170:170) (237:237:237)) + (PORT datab (161:161:161) (217:217:217)) + (PORT datac (155:155:155) (210:210:210)) + (PORT datad (152:152:152) (198:198:198)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) + (DELAY + (ABSOLUTE + (PORT dataa (291:291:291) (340:340:340)) + (PORT datab (160:160:160) (218:218:218)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (146:146:146) (191:191:191)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (264:264:264) (335:335:335)) + (PORT datac (368:368:368) (444:444:444)) + (PORT datad (359:359:359) (430:430:430)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -51628,10 +51812,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~6) (DELAY (ABSOLUTE - (PORT dataa (385:385:385) (472:472:472)) - (PORT datac (382:382:382) (467:467:467)) - (PORT datad (144:144:144) (189:189:189)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT datab (152:152:152) (205:205:205)) + (PORT datac (147:147:147) (197:197:197)) + (PORT datad (221:221:221) (280:280:280)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -51642,12 +51826,12 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~7) (DELAY (ABSOLUTE - (PORT dataa (164:164:164) (223:223:223)) - (PORT datab (139:139:139) (177:177:177)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (183:183:183) (212:212:212)) + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (190:190:190) (232:232:232)) + (PORT datac (147:147:147) (197:197:197)) + (PORT datad (116:116:116) (139:139:139)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -51658,11 +51842,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~8) (DELAY (ABSOLUTE - (PORT datab (239:239:239) (301:301:301)) - (PORT datac (293:293:293) (342:342:342)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (486:486:486) (566:566:566)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datad (218:218:218) (271:271:271)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -51672,11 +51856,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) + (PORT clk (908:908:908) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT sclr (554:554:554) (649:649:649)) - (PORT ena (724:724:724) (781:781:781)) + (PORT clrn (897:897:897) (902:902:902)) + (PORT sclr (643:643:643) (746:746:746)) + (PORT ena (485:485:485) (516:516:516)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51689,62 +51873,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~24) (DELAY (ABSOLUTE - (PORT dataa (170:170:170) (229:229:229)) - (PORT datab (164:164:164) (221:221:221)) - (PORT datac (152:152:152) (206:206:206)) - (PORT datad (143:143:143) (185:185:185)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (174:174:174)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (227:227:227)) - (PORT datab (194:194:194) (230:230:230)) - (PORT datac (204:204:204) (251:251:251)) - (PORT datad (221:221:221) (269:269:269)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datab (332:332:332) (398:398:398)) + (PORT datac (244:244:244) (309:309:309)) + (PORT datad (118:118:118) (155:155:155)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) - (DELAY - (ABSOLUTE - (PORT dataa (132:132:132) (183:183:183)) - (PORT datac (477:477:477) (564:564:564)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~10) (DELAY (ABSOLUTE - (PORT dataa (383:383:383) (461:461:461)) - (PORT datab (258:258:258) (321:321:321)) - (PORT datac (313:313:313) (371:371:371)) - (PORT datad (105:105:105) (123:123:123)) - (IOPATH dataa combout (188:188:188) (193:193:193)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT dataa (227:227:227) (294:294:294)) + (PORT datab (189:189:189) (230:230:230)) + (PORT datac (146:146:146) (196:196:196)) + (PORT datad (222:222:222) (282:282:282)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -51754,13 +51906,27 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~11) (DELAY (ABSOLUTE - (PORT dataa (548:548:548) (641:641:641)) - (PORT datab (296:296:296) (352:352:352)) - (PORT datac (492:492:492) (580:580:580)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (166:166:166) (157:157:157)) + (PORT dataa (133:133:133) (170:170:170)) + (PORT datab (155:155:155) (209:209:209)) + (PORT datac (142:142:142) (191:191:191)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (487:487:487) (567:567:567)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datad (216:216:216) (269:269:269)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -51770,10 +51936,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) + (PORT clk (908:908:908) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT ena (629:629:629) (676:676:676)) + (PORT clrn (897:897:897) (902:902:902)) + (PORT ena (496:496:496) (536:536:536)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51785,46 +51951,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) (DELAY (ABSOLUTE - (PORT dataa (172:172:172) (232:232:232)) - (PORT datab (167:167:167) (225:225:225)) - (PORT datac (151:151:151) (201:201:201)) - (PORT datad (149:149:149) (193:193:193)) - (IOPATH dataa combout (172:172:172) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) - (DELAY - (ABSOLUTE - (PORT dataa (235:235:235) (297:297:297)) - (PORT datab (221:221:221) (279:279:279)) - (PORT datac (159:159:159) (189:189:189)) - (PORT datad (104:104:104) (122:122:122)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) - (DELAY - (ABSOLUTE - (PORT dataa (133:133:133) (185:185:185)) - (PORT datac (472:472:472) (558:558:558)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (333:333:333) (389:389:389)) + (PORT datac (243:243:243) (308:308:308)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -51834,10 +51968,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[2\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) + (PORT clk (908:908:908) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT ena (629:629:629) (676:676:676)) + (PORT clrn (897:897:897) (902:902:902)) + (PORT ena (496:496:496) (536:536:536)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51849,13 +51983,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) (DELAY (ABSOLUTE - (PORT dataa (223:223:223) (287:287:287)) - (PORT datab (162:162:162) (218:218:218)) - (PORT datac (153:153:153) (207:207:207)) - (PORT datad (151:151:151) (196:196:196)) + (PORT dataa (171:171:171) (238:238:238)) + (PORT datab (162:162:162) (222:222:222)) + (PORT datac (155:155:155) (211:211:211)) + (PORT datad (153:153:153) (198:198:198)) (IOPATH dataa combout (172:172:172) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -51865,15 +51999,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) (DELAY (ABSOLUTE - (PORT dataa (235:235:235) (297:297:297)) - (PORT datab (237:237:237) (293:293:293)) - (PORT datac (259:259:259) (293:293:293)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (173:173:173) (239:239:239)) + (PORT datac (157:157:157) (212:212:212)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (378:378:378)) + (PORT datab (179:179:179) (218:218:218)) + (PORT datac (368:368:368) (444:444:444)) + (PORT datad (360:360:360) (431:431:431)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -51881,15 +52027,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~27) (DELAY (ABSOLUTE - (PORT dataa (339:339:339) (413:413:413)) - (PORT datab (130:130:130) (179:179:179)) - (PORT datac (473:473:473) (559:559:559)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (132:132:132) (184:184:184)) + (PORT datab (429:429:429) (509:509:509)) + (PORT datac (247:247:247) (313:313:313)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -51900,10 +52046,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) + (PORT clk (908:908:908) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT ena (629:629:629) (676:676:676)) + (PORT clrn (897:897:897) (902:902:902)) + (PORT ena (496:496:496) (536:536:536)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51915,16 +52061,48 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~25) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) (DELAY (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (359:359:359) (435:435:435)) - (PORT datac (323:323:323) (379:379:379)) - (PORT datad (189:189:189) (236:236:236)) + (PORT dataa (170:170:170) (237:237:237)) + (PORT datab (161:161:161) (221:221:221)) + (PORT datac (154:154:154) (210:210:210)) + (PORT datad (147:147:147) (193:193:193)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (453:453:453)) + (PORT datab (343:343:343) (405:405:405)) + (PORT datac (367:367:367) (444:444:444)) + (PORT datad (171:171:171) (200:200:200)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (183:183:183)) + (PORT datab (431:431:431) (510:510:510)) + (PORT datac (245:245:245) (310:310:310)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -51934,10 +52112,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[4\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) + (PORT clk (908:908:908) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT ena (728:728:728) (796:796:796)) + (PORT clrn (897:897:897) (902:902:902)) + (PORT ena (496:496:496) (536:536:536)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51949,12 +52127,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~12) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) (DELAY (ABSOLUTE - (PORT dataa (286:286:286) (330:330:330)) - (PORT datab (260:260:260) (324:324:324)) - (PORT datad (191:191:191) (237:237:237)) + (PORT dataa (339:339:339) (398:398:398)) + (PORT datab (329:329:329) (395:395:395)) + (PORT datad (188:188:188) (231:231:231)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -51966,11 +52144,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) + (PORT clk (908:908:908) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) - (PORT sload (627:627:627) (704:704:704)) - (PORT ena (419:419:419) (435:435:435)) + (PORT clrn (897:897:897) (902:902:902)) + (PORT sload (630:630:630) (715:715:715)) + (PORT ena (609:609:609) (659:659:659)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51987,11 +52165,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~9) (DELAY (ABSOLUTE - (PORT datab (342:342:342) (418:418:418)) - (PORT datac (476:476:476) (563:563:563)) - (PORT datad (105:105:105) (123:123:123)) + (PORT datab (337:337:337) (397:397:397)) + (PORT datac (241:241:241) (306:306:306)) + (PORT datad (198:198:198) (249:249:249)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -52001,11 +52179,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) + (PORT clk (908:908:908) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT sclr (554:554:554) (649:649:649)) - (PORT ena (629:629:629) (676:676:676)) + (PORT clrn (897:897:897) (902:902:902)) + (PORT sclr (643:643:643) (746:746:746)) + (PORT ena (496:496:496) (536:536:536)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52021,8 +52199,8 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]\~5) (DELAY (ABSOLUTE - (PORT datac (472:472:472) (558:558:558)) - (PORT datad (119:119:119) (156:156:156)) + (PORT datac (249:249:249) (315:315:315)) + (PORT datad (120:120:120) (158:158:158)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -52033,11 +52211,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) + (PORT clk (908:908:908) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT sclr (554:554:554) (649:649:649)) - (PORT ena (724:724:724) (781:781:781)) + (PORT clrn (897:897:897) (902:902:902)) + (PORT sclr (643:643:643) (746:746:746)) + (PORT ena (485:485:485) (516:516:516)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52053,12 +52231,12 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~0) (DELAY (ABSOLUTE - (PORT dataa (364:364:364) (440:440:440)) - (PORT datab (220:220:220) (277:277:277)) - (PORT datac (290:290:290) (344:344:344)) - (PORT datad (198:198:198) (249:249:249)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) + (PORT dataa (351:351:351) (430:430:430)) + (PORT datab (470:470:470) (564:564:564)) + (PORT datac (215:215:215) (261:261:261)) + (PORT datad (465:465:465) (550:550:550)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -52069,10 +52247,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~1) (DELAY (ABSOLUTE - (PORT dataa (279:279:279) (324:324:324)) - (PORT datab (180:180:180) (245:245:245)) - (PORT datac (174:174:174) (211:211:211)) - (PORT datad (279:279:279) (297:297:297)) + (PORT dataa (176:176:176) (217:217:217)) + (PORT datab (402:402:402) (490:490:490)) + (PORT datac (103:103:103) (124:124:124)) + (PORT datad (273:273:273) (291:291:291)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -52086,9 +52264,9 @@ (DELAY (ABSOLUTE (PORT dataa (139:139:139) (193:193:193)) - (PORT datab (181:181:181) (246:246:246)) - (PORT datac (142:142:142) (189:189:189)) - (PORT datad (95:95:95) (114:114:114)) + (PORT datab (405:405:405) (493:493:493)) + (PORT datac (352:352:352) (438:438:438)) + (PORT datad (96:96:96) (116:116:116)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -52101,10 +52279,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~3) (DELAY (ABSOLUTE - (PORT dataa (139:139:139) (194:194:194)) - (PORT datab (178:178:178) (243:243:243)) - (PORT datac (143:143:143) (190:190:190)) - (PORT datad (94:94:94) (113:113:113)) + (PORT dataa (139:139:139) (193:193:193)) + (PORT datab (404:404:404) (493:493:493)) + (PORT datac (353:353:353) (438:438:438)) + (PORT datad (96:96:96) (115:115:115)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -52117,8 +52295,8 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~4) (DELAY (ABSOLUTE - (PORT dataa (353:353:353) (430:430:430)) - (PORT datab (430:430:430) (496:496:496)) + (PORT dataa (439:439:439) (528:528:528)) + (PORT datab (123:123:123) (154:154:154)) (PORT datac (91:91:91) (113:113:113)) (PORT datad (92:92:92) (110:110:110)) (IOPATH dataa combout (172:172:172) (163:163:163)) @@ -52135,8 +52313,8 @@ (ABSOLUTE (PORT clk (871:871:871) (889:889:889)) (PORT d (381:381:381) (356:356:356)) - (PORT aload (1028:1028:1028) (1070:1070:1070)) - (PORT ena (725:725:725) (672:672:672)) + (PORT aload (1011:1011:1011) (1052:1052:1052)) + (PORT ena (518:518:518) (488:488:488)) (IOPATH (posedge clk) q (345:345:345) (339:339:339)) (IOPATH (posedge aload) q (286:286:286) (280:280:280)) ) @@ -52148,6 +52326,2173 @@ (HOLD ena (posedge clk) (58:58:58)) ) ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1400:1400:1400) (1400:1400:1400)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1137:1137:1137) (1133:1133:1133)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux38\~0) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (1012:1012:1012)) + (PORT datab (726:726:726) (840:840:840)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rd_pending) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (133:133:133) (183:183:183)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[3\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (143:143:143)) + (PORT datab (522:522:522) (621:621:621)) + (PORT datac (353:353:353) (412:412:412)) + (PORT datad (757:757:757) (898:898:898)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (321:321:321) (375:375:375)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (133:133:133) (183:183:183)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (321:321:321) (375:375:375)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[2\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (321:321:321) (375:375:375)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[3\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (321:321:321) (375:375:375)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[4\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (321:321:321) (375:375:375)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[5\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (321:321:321) (375:375:375)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[6\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (187:187:187)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (321:321:321) (375:375:375)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[7\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (321:321:321) (375:375:375)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (191:191:191)) + (PORT datab (136:136:136) (186:186:186)) + (PORT datac (122:122:122) (166:166:166)) + (PORT datad (123:123:123) (163:163:163)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[8\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (186:186:186)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (321:321:321) (375:375:375)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (193:193:193)) + (PORT datab (139:139:139) (190:190:190)) + (PORT datac (124:124:124) (168:168:168)) + (PORT datad (125:125:125) (165:165:165)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[9\]\~30) + (DELAY + (ABSOLUTE + (PORT datad (121:121:121) (160:160:160)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (321:321:321) (375:375:375)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (213:213:213)) + (PORT datab (136:136:136) (185:185:185)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (122:122:122) (160:160:160)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~8) + (DELAY + (ABSOLUTE + (PORT datab (774:774:774) (923:923:923)) + (PORT datac (508:508:508) (600:600:600)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (143:143:143)) + (PORT datab (367:367:367) (433:433:433)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_pending) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (416:416:416) (510:510:510)) + (PORT datab (411:411:411) (505:505:505)) + (PORT datac (359:359:359) (440:440:440)) + (PORT datad (460:460:460) (536:536:536)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (456:456:456) (560:560:560)) + (PORT datab (557:557:557) (664:664:664)) + (PORT datac (718:718:718) (858:858:858)) + (PORT datad (297:297:297) (341:341:341)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (455:455:455) (560:560:560)) + (PORT datab (556:556:556) (663:663:663)) + (PORT datac (718:718:718) (857:857:857)) + (PORT datad (297:297:297) (340:340:340)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux4\~3) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (412:412:412)) + (PORT datab (166:166:166) (221:221:221)) + (PORT datad (329:329:329) (384:384:384)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.act_row\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (730:730:730) (872:872:872)) + (PORT datab (610:610:610) (729:729:729)) + (PORT datac (759:759:759) (874:874:874)) + (PORT datad (549:549:549) (652:652:652)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~2) + (DELAY + (ABSOLUTE + (PORT datac (144:144:144) (187:187:187)) + (PORT datad (158:158:158) (201:201:201)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.act_row\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (189:189:189) (231:231:231)) + (PORT datac (569:569:569) (683:683:683)) + (PORT datad (551:551:551) (655:655:655)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (495:495:495) (532:532:532)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (919:919:919)) + (PORT asdata (870:870:870) (972:972:972)) + (PORT ena (495:495:495) (532:532:532)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.act_row\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (664:664:664) (768:768:768)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (495:495:495) (532:532:532)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal7\~1) + (DELAY + (ABSOLUTE + (PORT dataa (709:709:709) (819:819:819)) + (PORT datab (682:682:682) (791:791:791)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (919:919:919)) + (PORT asdata (730:730:730) (824:824:824)) + (PORT ena (495:495:495) (532:532:532)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (919:919:919)) + (PORT asdata (1745:1745:1745) (1998:1998:1998)) + (PORT ena (495:495:495) (532:532:532)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1584:1584:1584) (1848:1848:1848)) + (PORT datab (566:566:566) (669:669:669)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal7\~2) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (272:272:272)) + (PORT datab (137:137:137) (187:187:187)) + (PORT datac (94:94:94) (117:117:117)) + (PORT datad (98:98:98) (118:118:118)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (774:774:774) (897:897:897)) + (PORT datab (570:570:570) (680:680:680)) + (PORT datac (568:568:568) (682:682:682)) + (PORT datad (591:591:591) (705:705:705)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~1) + (DELAY + (ABSOLUTE + (PORT dataa (708:708:708) (841:841:841)) + (PORT datac (300:300:300) (351:351:351)) + (PORT datad (172:172:172) (204:204:204)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~2) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (141:141:141)) + (PORT datab (351:351:351) (409:409:409)) + (PORT datad (753:753:753) (863:863:863)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.wr_pending) + (DELAY + (ABSOLUTE + (PORT clk (910:910:910) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~8) + (DELAY + (ABSOLUTE + (PORT datac (636:636:636) (750:750:750)) + (PORT datad (600:600:600) (722:722:722)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~9) + (DELAY + (ABSOLUTE + (PORT dataa (235:235:235) (295:295:295)) + (PORT datab (318:318:318) (377:377:377)) + (PORT datac (365:365:365) (447:447:447)) + (PORT datad (158:158:158) (201:201:201)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (710:710:710) (844:844:844)) + (PORT datab (171:171:171) (225:225:225)) + (PORT datac (104:104:104) (125:125:125)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~4) + (DELAY + (ABSOLUTE + (PORT datab (375:375:375) (462:462:462)) + (PORT datac (297:297:297) (349:349:349)) + (PORT datad (690:690:690) (811:811:811)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (706:706:706) (839:839:839)) + (PORT datac (637:637:637) (751:751:751)) + (PORT datad (601:601:601) (722:722:722)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~5) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (525:525:525) (624:624:624)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (495:495:495) (586:586:586)) + (PORT datac (435:435:435) (497:497:497)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (161:161:161) (220:220:220)) + (PORT datab (401:401:401) (490:490:490)) + (PORT datac (106:106:106) (130:130:130)) + (PORT datad (399:399:399) (485:485:485)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (161:161:161) (174:174:174)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (154:154:154) (209:209:209)) + (PORT datab (163:163:163) (218:218:218)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (399:399:399) (485:485:485)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~6) + (DELAY + (ABSOLUTE + (PORT datab (166:166:166) (220:220:220)) + (PORT datac (329:329:329) (385:385:385)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (732:732:732) (873:873:873)) + (PORT datac (567:567:567) (681:681:681)) + (PORT datad (546:546:546) (649:649:649)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~2) + (DELAY + (ABSOLUTE + (PORT dataa (315:315:315) (363:363:363)) + (PORT datab (774:774:774) (905:905:905)) + (PORT datac (366:366:366) (449:449:449)) + (PORT datad (597:597:597) (718:718:718)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~3) + (DELAY + (ABSOLUTE + (PORT datab (456:456:456) (558:558:558)) + (PORT datac (436:436:436) (536:536:536)) + (PORT datad (478:478:478) (557:557:557)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~3) + (DELAY + (ABSOLUTE + (PORT dataa (509:509:509) (600:600:600)) + (PORT datab (165:165:165) (221:221:221)) + (PORT datad (400:400:400) (486:486:486)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~4) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (160:160:160) (215:215:215)) + (PORT datac (479:479:479) (561:561:561)) + (PORT datad (151:151:151) (195:195:195)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~5) + (DELAY + (ABSOLUTE + (PORT dataa (503:503:503) (583:583:583)) + (PORT datab (165:165:165) (221:221:221)) + (PORT datac (382:382:382) (469:469:469)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~0) + (DELAY + (ABSOLUTE + (PORT datab (537:537:537) (639:639:639)) + (PORT datac (697:697:697) (823:823:823)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~7) + (DELAY + (ABSOLUTE + (PORT datac (711:711:711) (850:850:850)) + (PORT datad (535:535:535) (635:635:635)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~10) + (DELAY + (ABSOLUTE + (PORT dataa (491:491:491) (572:572:572)) + (PORT datab (541:541:541) (644:644:644)) + (PORT datac (700:700:700) (829:829:829)) + (PORT datad (378:378:378) (463:463:463)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~1) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (258:258:258)) + (PORT datab (194:194:194) (234:234:234)) + (PORT datac (558:558:558) (666:666:666)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~6) + (DELAY + (ABSOLUTE + (PORT dataa (434:434:434) (502:502:502)) + (PORT datab (175:175:175) (210:210:210)) + (PORT datac (142:142:142) (192:192:192)) + (PORT datad (444:444:444) (511:511:511)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (231:231:231)) + (PORT datab (715:715:715) (847:847:847)) + (PORT datac (521:521:521) (618:618:618)) + (PORT datad (178:178:178) (211:211:211)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~10) + (DELAY + (ABSOLUTE + (PORT dataa (418:418:418) (512:512:512)) + (PORT datab (411:411:411) (506:506:506)) + (PORT datac (432:432:432) (527:527:527)) + (PORT datad (381:381:381) (459:459:459)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~3) + (DELAY + (ABSOLUTE + (PORT dataa (450:450:450) (553:553:553)) + (PORT datab (554:554:554) (661:661:661)) + (PORT datac (101:101:101) (122:122:122)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~4) + (DELAY + (ABSOLUTE + (PORT dataa (179:179:179) (223:223:223)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (710:710:710) (849:849:849)) + (PORT datad (395:395:395) (477:477:477)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~7) + (DELAY + (ABSOLUTE + (PORT dataa (159:159:159) (218:218:218)) + (PORT datab (417:417:417) (509:509:509)) + (PORT datac (480:480:480) (562:562:562)) + (PORT datad (488:488:488) (573:573:573)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~8) + (DELAY + (ABSOLUTE + (PORT dataa (176:176:176) (219:219:219)) + (PORT datab (166:166:166) (222:222:222)) + (PORT datac (381:381:381) (468:468:468)) + (PORT datad (153:153:153) (198:198:198)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~5) + (DELAY + (ABSOLUTE + (PORT dataa (511:511:511) (602:602:602)) + (PORT datab (404:404:404) (493:493:493)) + (PORT datac (438:438:438) (500:500:500)) + (PORT datad (151:151:151) (195:195:195)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~6) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (289:289:289)) + (PORT datab (120:120:120) (150:150:150)) + (PORT datac (343:343:343) (401:401:401)) + (PORT datad (501:501:501) (580:580:580)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~9) + (DELAY + (ABSOLUTE + (PORT dataa (153:153:153) (207:207:207)) + (PORT datab (359:359:359) (423:423:423)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~2) + (DELAY + (ABSOLUTE + (PORT datab (568:568:568) (678:678:678)) + (PORT datac (544:544:544) (653:653:653)) + (PORT datad (556:556:556) (655:655:655)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~3) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (228:228:228)) + (PORT datab (697:697:697) (819:819:819)) + (PORT datac (871:871:871) (1024:1024:1024)) + (PORT datad (894:894:894) (1047:1047:1047)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~4) + (DELAY + (ABSOLUTE + (PORT dataa (790:790:790) (942:942:942)) + (PORT datab (831:831:831) (970:970:970)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (694:694:694) (811:811:811)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~10) + (DELAY + (ABSOLUTE + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (637:637:637) (752:752:752)) + (PORT datad (601:601:601) (723:723:723)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.init_counter\[0\]\~0) + (DELAY + (ABSOLUTE + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (918:918:918) (928:928:928)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~1) + (DELAY + (ABSOLUTE + (PORT datab (403:403:403) (488:488:488)) + (IOPATH datab cout (227:227:227) (175:175:175)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (153:153:153) (201:201:201)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (925:925:925)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (193:193:193)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (925:925:925)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (279:279:279)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.init_counter\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (174:174:174) (210:210:210)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (918:918:918) (925:925:925)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (925:925:925)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (925:925:925)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~12) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (188:188:188) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (925:925:925)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~14) + (DELAY + (ABSOLUTE + (PORT datab (154:154:154) (202:202:202)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (925:925:925)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~16) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (188:188:188) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (925:925:925)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~18) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (925:925:925)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~20) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (925:925:925)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (279:279:279)) + (PORT datab (232:232:232) (290:290:290)) + (PORT datac (204:204:204) (256:256:256)) + (PORT datad (213:213:213) (264:264:264)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT datab (233:233:233) (291:291:291)) + (PORT datac (217:217:217) (272:272:272)) + (PORT datad (131:131:131) (170:170:170)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~22) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (184:184:184)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (925:925:925)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~24) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (188:188:188)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (925:925:925)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~26) + (DELAY + (ABSOLUTE + (PORT datab (133:133:133) (183:183:183)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (925:925:925)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~28) + (DELAY + (ABSOLUTE + (PORT dataa (134:134:134) (187:187:187)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (925:925:925)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (193:193:193)) + (PORT datab (137:137:137) (187:187:187)) + (PORT datac (124:124:124) (168:168:168)) + (PORT datad (125:125:125) (164:164:164)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (204:204:204) (252:252:252)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~11) + (DELAY + (ABSOLUTE + (PORT dataa (420:420:420) (511:511:511)) + (PORT datab (166:166:166) (223:223:223)) + (PORT datad (416:416:416) (498:498:498)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~12) + (DELAY + (ABSOLUTE + (PORT dataa (307:307:307) (356:356:356)) + (PORT datab (367:367:367) (433:433:433)) + (PORT datac (893:893:893) (1043:1043:1043)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~13) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (1002:1002:1002)) + (PORT datab (774:774:774) (919:919:919)) + (PORT datac (295:295:295) (335:335:335)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (186:186:186) (179:179:179)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (705:705:705) (838:838:838)) + (PORT datab (775:775:775) (905:905:905)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (481:481:481) (552:552:552)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~1) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (813:813:813)) + (PORT datab (523:523:523) (620:620:620)) + (PORT datac (525:525:525) (624:624:624)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~2) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (472:472:472)) + (PORT datac (637:637:637) (718:718:718)) + (PORT datad (484:484:484) (550:550:550)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux72\~0) + (DELAY + (ABSOLUTE + (PORT datab (1733:1733:1733) (1978:1978:1978)) + (PORT datac (506:506:506) (604:604:604)) + (PORT datad (155:155:155) (203:203:203)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux72\~1) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (650:650:650)) + (PORT datab (1732:1732:1732) (1978:1978:1978)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (186:186:186) (216:216:216)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux84\~0) + (DELAY + (ABSOLUTE + (PORT datac (140:140:140) (187:187:187)) + (PORT datad (400:400:400) (486:486:486)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux84\~1) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (289:289:289)) + (PORT datab (166:166:166) (222:222:222)) + (PORT datac (146:146:146) (196:196:196)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux3\~0) + (DELAY + (ABSOLUTE + (PORT datab (1735:1735:1735) (1980:1980:1980)) + (PORT datac (631:631:631) (730:730:730)) + (PORT datad (152:152:152) (199:199:199)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (653:653:653)) + (PORT datab (1735:1735:1735) (1981:1981:1981)) + (PORT datac (159:159:159) (186:186:186)) + (PORT datad (178:178:178) (207:207:207)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux2\~0) + (DELAY + (ABSOLUTE + (PORT datab (1732:1732:1732) (1978:1978:1978)) + (PORT datac (619:619:619) (722:722:722)) + (PORT datad (156:156:156) (204:204:204)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (551:551:551) (655:655:655)) + (PORT datab (1736:1736:1736) (1983:1983:1983)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (351:351:351) (405:405:405)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux1\~0) + (DELAY + (ABSOLUTE + (PORT datab (1736:1736:1736) (1982:1982:1982)) + (PORT datac (618:618:618) (725:725:725)) + (PORT datad (151:151:151) (198:198:198)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (548:548:548) (652:652:652)) + (PORT datab (1733:1733:1733) (1979:1979:1979)) + (PORT datac (318:318:318) (362:362:362)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT datab (1734:1734:1734) (1979:1979:1979)) + (PORT datac (529:529:529) (632:632:632)) + (PORT datad (153:153:153) (202:202:202)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (655:655:655)) + (PORT datab (1736:1736:1736) (1982:1982:1982)) + (PORT datac (161:161:161) (194:194:194)) + (PORT datad (344:344:344) (394:394:394)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux73\~0) + (DELAY + (ABSOLUTE + (PORT datab (1733:1733:1733) (1979:1979:1979)) + (PORT datac (849:849:849) (989:989:989)) + (PORT datad (154:154:154) (202:202:202)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux73\~1) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (652:652:652)) + (PORT datab (1734:1734:1734) (1980:1980:1980)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (345:345:345) (397:397:397)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux74\~0) + (DELAY + (ABSOLUTE + (PORT datab (1736:1736:1736) (1982:1982:1982)) + (PORT datac (506:506:506) (607:607:607)) + (PORT datad (152:152:152) (198:198:198)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux74\~1) + (DELAY + (ABSOLUTE + (PORT dataa (548:548:548) (651:651:651)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (1712:1712:1712) (1956:1956:1956)) + (PORT datad (357:357:357) (412:412:412)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux75\~0) + (DELAY + (ABSOLUTE + (PORT datac (850:850:850) (999:999:999)) + (PORT datad (745:745:745) (858:858:858)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|mclk_r\~0) @@ -52162,9 +54507,9 @@ (INSTANCE ula_\|i2s_intf_\|mclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1134:1134:1134)) + (PORT clk (1122:1122:1122) (1155:1155:1155)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (911:911:911)) + (PORT clrn (902:902:902) (906:906:906)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52179,8 +54524,8 @@ (DELAY (ABSOLUTE (PORT clk (891:891:891) (913:913:913)) - (PORT d (1491:1491:1491) (1301:1301:1301)) - (PORT clrn (1029:1029:1029) (1076:1076:1076)) + (PORT d (549:549:549) (502:502:502)) + (PORT clrn (1020:1020:1020) (1065:1065:1065)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) ) @@ -52195,8 +54540,8 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~1) (DELAY (ABSOLUTE - (PORT dataa (379:379:379) (460:460:460)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (367:367:367) (448:448:448)) + (IOPATH datab cout (227:227:227) (175:175:175)) ) ) ) @@ -52205,7 +54550,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (137:137:137) (187:187:187)) + (PORT datab (136:136:136) (186:186:186)) (IOPATH datab combout (167:167:167) (174:174:174)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -52219,10 +54564,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~2) (DELAY (ABSOLUTE - (PORT dataa (120:120:120) (154:154:154)) - (PORT datac (92:92:92) (114:114:114)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT datac (91:91:91) (112:112:112)) + (PORT datad (110:110:110) (131:131:131)) (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -52231,9 +54576,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1134:1134:1134)) + (PORT clk (1110:1110:1110) (1140:1140:1140)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (911:911:911)) + (PORT clrn (902:902:902) (905:905:905)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52247,7 +54592,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~4) (DELAY (ABSOLUTE - (PORT dataa (207:207:207) (271:271:271)) + (PORT dataa (209:209:209) (272:272:272)) (IOPATH dataa combout (166:166:166) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -52261,8 +54606,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]\~8) (DELAY (ABSOLUTE - (PORT datad (167:167:167) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datac (161:161:161) (190:190:190)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -52271,9 +54616,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1134:1134:1134)) + (PORT clk (1110:1110:1110) (1140:1140:1140)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (911:911:911)) + (PORT clrn (902:902:902) (906:906:906)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52287,9 +54632,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~6) (DELAY (ABSOLUTE - (PORT datab (203:203:203) (259:259:259)) - (IOPATH datab combout (191:191:191) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (227:227:227) (284:284:284)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -52301,8 +54646,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]\~7) (DELAY (ABSOLUTE - (PORT datac (174:174:174) (211:211:211)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT datad (293:293:293) (340:340:340)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -52311,9 +54656,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1134:1134:1134)) + (PORT clk (1122:1122:1122) (1155:1155:1155)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (911:911:911)) + (PORT clrn (902:902:902) (906:906:906)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52327,7 +54672,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~8) (DELAY (ABSOLUTE - (PORT datab (135:135:135) (186:186:186)) + (PORT datab (137:137:137) (187:187:187)) (IOPATH datab combout (188:188:188) (181:181:181)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -52341,10 +54686,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~1) (DELAY (ABSOLUTE - (PORT dataa (125:125:125) (160:160:160)) - (PORT datac (90:90:90) (111:111:111)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datad (111:111:111) (132:132:132)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -52353,9 +54698,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1134:1134:1134)) + (PORT clk (1110:1110:1110) (1140:1140:1140)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (911:911:911)) + (PORT clrn (902:902:902) (905:905:905)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52369,9 +54714,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~10) (DELAY (ABSOLUTE - (PORT datab (136:136:136) (186:186:186)) - (IOPATH datab combout (191:191:191) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (227:227:227) (287:287:287)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -52383,7 +54728,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]\~6) (DELAY (ABSOLUTE - (PORT datad (92:92:92) (109:109:109)) + (PORT datad (162:162:162) (189:189:189)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -52393,9 +54738,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1134:1134:1134)) + (PORT clk (1110:1110:1110) (1140:1140:1140)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (911:911:911)) + (PORT clrn (902:902:902) (906:906:906)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52409,10 +54754,10 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (210:210:210) (273:273:273)) - (PORT datab (137:137:137) (187:187:187)) - (PORT datac (191:191:191) (240:240:240)) - (PORT datad (124:124:124) (164:164:164)) + (PORT dataa (207:207:207) (271:271:271)) + (PORT datab (134:134:134) (184:184:184)) + (PORT datac (202:202:202) (258:258:258)) + (PORT datad (201:201:201) (255:255:255)) (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -52425,9 +54770,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~12) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (278:278:278)) - (IOPATH dataa combout (166:166:166) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (220:220:220) (280:280:280)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -52439,7 +54784,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]\~5) (DELAY (ABSOLUTE - (PORT datad (172:172:172) (203:203:203)) + (PORT datad (168:168:168) (197:197:197)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -52449,9 +54794,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1134:1134:1134)) + (PORT clk (1110:1110:1110) (1140:1140:1140)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (911:911:911)) + (PORT clrn (902:902:902) (906:906:906)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52465,7 +54810,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~14) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (287:287:287)) + (PORT dataa (207:207:207) (270:270:270)) (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -52479,8 +54824,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]\~4) (DELAY (ABSOLUTE - (PORT datad (169:169:169) (199:199:199)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datac (169:169:169) (203:203:203)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -52489,9 +54834,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1134:1134:1134)) + (PORT clk (1110:1110:1110) (1140:1140:1140)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (911:911:911)) + (PORT clrn (902:902:902) (906:906:906)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52505,9 +54850,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~16) (DELAY (ABSOLUTE - (PORT dataa (207:207:207) (265:265:265)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (137:137:137) (187:187:187)) + (IOPATH datab combout (188:188:188) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -52519,10 +54864,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~0) (DELAY (ABSOLUTE - (PORT datab (190:190:190) (229:229:229)) - (PORT datac (197:197:197) (236:236:236)) + (PORT datab (105:105:105) (135:135:135)) + (PORT datad (112:112:112) (132:132:132)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -52531,9 +54876,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[8\]) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1134:1134:1134)) + (PORT clk (1110:1110:1110) (1140:1140:1140)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (911:911:911)) + (PORT clrn (902:902:902) (905:905:905)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52547,7 +54892,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~18) (DELAY (ABSOLUTE - (PORT datad (199:199:199) (249:249:249)) + (PORT datad (199:199:199) (248:248:248)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) ) @@ -52558,8 +54903,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]\~3) (DELAY (ABSOLUTE - (PORT datad (171:171:171) (202:202:202)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datac (174:174:174) (209:209:209)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -52568,9 +54913,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1134:1134:1134)) + (PORT clk (1109:1109:1109) (1139:1139:1139)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (911:911:911)) + (PORT clrn (901:901:901) (905:905:905)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52584,13 +54929,13 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (207:207:207) (266:266:266)) - (PORT datab (220:220:220) (276:276:276)) - (PORT datac (202:202:202) (259:259:259)) - (PORT datad (201:201:201) (254:254:254)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (208:208:208) (271:271:271)) + (PORT datab (219:219:219) (275:275:275)) + (PORT datac (120:120:120) (162:162:162)) + (PORT datad (204:204:204) (257:257:257)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -52600,10 +54945,10 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (132:132:132) (182:182:182)) - (PORT datac (360:360:360) (431:431:431)) - (PORT datad (94:94:94) (112:112:112)) + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (133:133:133) (183:183:183)) + (PORT datac (160:160:160) (189:189:189)) + (PORT datad (351:351:351) (425:425:425)) (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -52611,30 +54956,20 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2feeder) - (DELAY - (ABSOLUTE - (PORT datad (105:105:105) (123:123:123)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (912:912:912)) + (PORT clk (916:916:916) (921:921:921)) + (PORT asdata (278:278:278) (297:297:297)) + (PORT clrn (905:905:905) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) ) ) (CELL @@ -52642,8 +54977,8 @@ (INSTANCE ula_\|i2s_intf_\|lrclk_r\~0) (DELAY (ABSOLUTE - (PORT datab (492:492:492) (573:573:573)) - (PORT datad (128:128:128) (168:168:168)) + (PORT datab (521:521:521) (608:608:608)) + (PORT datad (123:123:123) (163:163:163)) (IOPATH datab combout (192:192:192) (181:181:181)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -52655,8 +54990,8 @@ (DELAY (ABSOLUTE (PORT clk (889:889:889) (911:911:911)) - (PORT d (1273:1273:1273) (1412:1412:1412)) - (PORT clrn (1027:1027:1027) (1074:1074:1074)) + (PORT d (751:751:751) (802:802:802)) + (PORT clrn (1018:1018:1018) (1063:1063:1063)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) ) @@ -52672,8 +55007,8 @@ (DELAY (ABSOLUTE (PORT clk (891:891:891) (912:912:912)) - (PORT d (1390:1390:1390) (1547:1547:1547)) - (PORT clrn (1029:1029:1029) (1075:1075:1075)) + (PORT d (747:747:747) (799:799:799)) + (PORT clrn (1020:1020:1020) (1064:1064:1064)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) ) @@ -52683,25 +55018,66 @@ (HOLD d (posedge clk) (56:56:56)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~18) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (260:260:260)) + (PORT datab (525:525:525) (613:613:613)) + (PORT datad (115:115:115) (139:139:139)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (921:921:921)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (905:905:905) (909:909:909)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]\~5) (DELAY (ABSOLUTE - (PORT datab (133:133:133) (183:183:183)) + (PORT datab (135:135:135) (185:185:185)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datab cout (227:227:227) (175:175:175)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1feeder) + (DELAY + (ABSOLUTE + (PORT datac (102:102:102) (123:123:123)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) + (PORT clk (917:917:917) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (912:912:912)) + (PORT clrn (906:906:906) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52715,12 +55091,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~15) (DELAY (ABSOLUTE - (PORT datab (124:124:124) (159:159:159)) - (PORT datac (471:471:471) (543:543:543)) - (PORT datad (132:132:132) (176:176:176)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (497:497:497) (576:576:576)) + (PORT datab (148:148:148) (203:203:203)) + (PORT datac (109:109:109) (133:133:133)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -52729,11 +55105,11 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) + (PORT clk (917:917:917) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (1507:1507:1507) (1683:1683:1683)) - (PORT clrn (907:907:907) (912:912:912)) - (PORT sload (777:777:777) (867:867:867)) + (PORT asdata (301:301:301) (329:329:329)) + (PORT clrn (906:906:906) (909:909:909)) + (PORT sload (797:797:797) (886:886:886)) (PORT ena (407:407:407) (424:424:424)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) @@ -52751,7 +55127,7 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]\~7) (DELAY (ABSOLUTE - (PORT datab (133:133:133) (183:183:183)) + (PORT datab (134:134:134) (184:184:184)) (IOPATH datab combout (167:167:167) (174:174:174)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -52765,11 +55141,11 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) + (PORT clk (917:917:917) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (1507:1507:1507) (1683:1683:1683)) - (PORT clrn (907:907:907) (912:912:912)) - (PORT sload (777:777:777) (867:867:867)) + (PORT asdata (300:300:300) (327:327:327)) + (PORT clrn (906:906:906) (909:909:909)) + (PORT sload (797:797:797) (886:886:886)) (PORT ena (407:407:407) (424:424:424)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) @@ -52787,7 +55163,7 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]\~9) (DELAY (ABSOLUTE - (PORT datab (134:134:134) (185:185:185)) + (PORT datab (135:135:135) (185:185:185)) (IOPATH datab combout (188:188:188) (181:181:181)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -52801,11 +55177,11 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) + (PORT clk (917:917:917) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (1506:1506:1506) (1683:1683:1683)) - (PORT clrn (907:907:907) (912:912:912)) - (PORT sload (777:777:777) (867:867:867)) + (PORT asdata (299:299:299) (327:327:327)) + (PORT clrn (906:906:906) (909:909:909)) + (PORT sload (797:797:797) (886:886:886)) (PORT ena (407:407:407) (424:424:424)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) @@ -52823,9 +55199,9 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]\~11) (DELAY (ABSOLUTE - (PORT dataa (136:136:136) (189:189:189)) - (IOPATH dataa combout (166:166:166) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -52837,11 +55213,44 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) + (PORT clk (917:917:917) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (1506:1506:1506) (1682:1682:1682)) - (PORT clrn (907:907:907) (912:912:912)) - (PORT sload (777:777:777) (867:867:867)) + (PORT asdata (298:298:298) (326:326:326)) + (PORT clrn (906:906:906) (909:909:909)) + (PORT sload (797:797:797) (886:886:886)) + (PORT ena (407:407:407) (424:424:424)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (146:146:146) (201:201:201)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (921:921:921)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (298:298:298) (326:326:326)) + (PORT clrn (906:906:906) (909:909:909)) + (PORT sload (797:797:797) (886:886:886)) (PORT ena (407:407:407) (424:424:424)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) @@ -52859,56 +55268,39 @@ (INSTANCE ula_\|i2s_intf_\|LessThan0\~0) (DELAY (ABSOLUTE - (PORT dataa (137:137:137) (191:191:191)) - (PORT datab (137:137:137) (188:188:188)) - (PORT datac (122:122:122) (166:166:166)) - (PORT datad (124:124:124) (163:163:163)) + (PORT dataa (214:214:214) (269:269:269)) + (PORT datab (136:136:136) (186:186:186)) + (PORT datac (121:121:121) (163:163:163)) + (PORT datad (122:122:122) (162:162:162)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]\~1) (DELAY (ABSOLUTE - (PORT datab (145:145:145) (199:199:199)) - (IOPATH datab combout (196:196:196) (205:205:205)) - (IOPATH cin combout (187:187:187) (204:204:204)) + (PORT dataa (201:201:201) (262:262:262)) + (PORT datab (285:285:285) (326:326:326)) + (PORT datac (133:133:133) (182:182:182)) + (PORT datad (99:99:99) (121:121:121)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (1506:1506:1506) (1682:1682:1682)) - (PORT clrn (907:907:907) (912:912:912)) - (PORT sload (777:777:777) (867:867:867)) - (PORT ena (407:407:407) (424:424:424)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|Add2\~7) (DELAY (ABSOLUTE - (PORT dataa (241:241:241) (304:304:304)) + (PORT dataa (221:221:221) (289:289:289)) (IOPATH dataa cout (226:226:226) (171:171:171)) ) ) @@ -52918,9 +55310,9 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~8) (DELAY (ABSOLUTE - (PORT dataa (136:136:136) (190:190:190)) - (IOPATH dataa combout (166:166:166) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (137:137:137) (187:187:187)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -52932,13 +55324,13 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~20) (DELAY (ABSOLUTE - (PORT dataa (241:241:241) (305:305:305)) - (PORT datab (491:491:491) (572:572:572)) - (PORT datac (109:109:109) (134:134:134)) - (PORT datad (91:91:91) (108:108:108)) + (PORT dataa (219:219:219) (287:287:287)) + (PORT datab (526:526:526) (613:613:613)) + (PORT datac (162:162:162) (190:190:190)) + (PORT datad (114:114:114) (137:137:137)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -52948,9 +55340,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) + (PORT clk (916:916:916) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (912:912:912)) + (PORT clrn (905:905:905) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52964,9 +55356,9 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~10) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (267:267:267)) - (IOPATH dataa combout (166:166:166) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (302:302:302) (367:367:367)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -52978,13 +55370,13 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~17) (DELAY (ABSOLUTE - (PORT dataa (121:121:121) (158:158:158)) - (PORT datab (124:124:124) (160:160:160)) - (PORT datac (472:472:472) (545:545:545)) - (PORT datad (172:172:172) (203:203:203)) - (IOPATH dataa combout (165:165:165) (159:159:159)) + (PORT dataa (216:216:216) (262:262:262)) + (PORT datab (524:524:524) (611:611:611)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (171:171:171) (200:200:200)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -52994,9 +55386,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) + (PORT clk (916:916:916) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (912:912:912)) + (PORT clrn (905:905:905) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53010,7 +55402,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~12) (DELAY (ABSOLUTE - (PORT datab (138:138:138) (189:189:189)) + (PORT datab (135:135:135) (186:186:186)) (IOPATH datab combout (167:167:167) (174:174:174)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -53024,13 +55416,13 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~19) (DELAY (ABSOLUTE - (PORT dataa (241:241:241) (305:305:305)) - (PORT datab (492:492:492) (574:574:574)) - (PORT datac (110:110:110) (135:135:135)) - (PORT datad (92:92:92) (110:110:110)) + (PORT dataa (221:221:221) (289:289:289)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (474:474:474) (539:539:539)) + (PORT datad (117:117:117) (141:141:141)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53040,9 +55432,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) + (PORT clk (916:916:916) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (912:912:912)) + (PORT clrn (905:905:905) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53056,7 +55448,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~14) (DELAY (ABSOLUTE - (PORT datad (189:189:189) (236:236:236)) + (PORT datad (124:124:124) (164:164:164)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) ) @@ -53067,13 +55459,13 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~16) (DELAY (ABSOLUTE - (PORT dataa (121:121:121) (158:158:158)) - (PORT datab (124:124:124) (159:159:159)) - (PORT datac (472:472:472) (545:545:545)) - (PORT datad (172:172:172) (203:203:203)) - (IOPATH dataa combout (165:165:165) (159:159:159)) + (PORT dataa (215:215:215) (260:260:260)) + (PORT datab (526:526:526) (613:613:613)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (174:174:174) (203:203:203)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53083,9 +55475,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) + (PORT clk (916:916:916) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (912:912:912)) + (PORT clrn (905:905:905) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53099,72 +55491,25 @@ (INSTANCE ula_\|i2s_intf_\|Equal1\~0) (DELAY (ABSOLUTE - (PORT dataa (137:137:137) (190:190:190)) - (PORT datab (138:138:138) (189:189:189)) - (PORT datac (193:193:193) (243:243:243)) - (PORT datad (189:189:189) (235:235:235)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (134:134:134) (186:186:186)) + (PORT datab (133:133:133) (183:183:183)) + (PORT datac (121:121:121) (163:163:163)) + (PORT datad (289:289:289) (344:344:344)) + (IOPATH dataa combout (165:165:165) (159:159:159)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (143:143:143) (194:194:194)) - (PORT datab (113:113:113) (145:145:145)) - (PORT datac (131:131:131) (180:180:180)) - (PORT datad (193:193:193) (226:226:226)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~18) - (DELAY - (ABSOLUTE - (PORT dataa (489:489:489) (573:573:573)) - (PORT datab (124:124:124) (160:160:160)) - (PORT datad (195:195:195) (229:229:229)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (912:912:912)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|Equal1\~1) (DELAY (ABSOLUTE - (PORT datac (201:201:201) (253:253:253)) - (PORT datad (193:193:193) (226:226:226)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datab (132:132:132) (165:165:165)) + (PORT datad (209:209:209) (263:263:263)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53174,10 +55519,10 @@ (INSTANCE ula_\|i2s_intf_\|bclk_r\~0) (DELAY (ABSOLUTE - (PORT datab (114:114:114) (146:146:146)) - (PORT datac (130:130:130) (178:178:178)) - (PORT datad (128:128:128) (172:172:172)) - (IOPATH datab combout (188:188:188) (181:181:181)) + (PORT dataa (113:113:113) (147:147:147)) + (PORT datac (132:132:132) (181:181:181)) + (PORT datad (137:137:137) (182:182:182)) + (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -53188,12 +55533,13 @@ (INSTANCE ula_\|i2s_intf_\|bclk_r\~1) (DELAY (ABSOLUTE - (PORT dataa (121:121:121) (160:160:160)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datad (466:466:466) (535:535:535)) - (IOPATH dataa combout (188:188:188) (184:184:184)) + (PORT dataa (283:283:283) (330:330:330)) + (PORT datab (148:148:148) (202:202:202)) + (PORT datac (481:481:481) (551:551:551)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (165:165:165) (159:159:159)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53204,8 +55550,8 @@ (DELAY (ABSOLUTE (PORT clk (888:888:888) (910:910:910)) - (PORT d (1273:1273:1273) (1428:1428:1428)) - (PORT clrn (1026:1026:1026) (1073:1073:1073)) + (PORT d (814:814:814) (884:884:884)) + (PORT clrn (1017:1017:1017) (1062:1062:1062)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) ) @@ -53220,7 +55566,7 @@ (INSTANCE ula_\|pcm_outl\[13\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (471:471:471) (541:541:541)) + (PORT datad (521:521:521) (595:595:595)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53230,12 +55576,12 @@ (INSTANCE ula_\|always0\~2) (DELAY (ABSOLUTE - (PORT dataa (983:983:983) (1142:1142:1142)) - (PORT datab (897:897:897) (1062:1062:1062)) - (PORT datac (653:653:653) (769:769:769)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT datab (1084:1084:1084) (1288:1288:1288)) + (PORT datac (1740:1740:1740) (2036:2036:2036)) + (PORT datad (1447:1447:1447) (1663:1663:1663)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -53244,13 +55590,13 @@ (INSTANCE ula_\|always0\~3) (DELAY (ABSOLUTE - (PORT dataa (379:379:379) (457:457:457)) - (PORT datab (693:693:693) (818:818:818)) - (PORT datac (659:659:659) (775:775:775)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (1451:1451:1451) (1709:1709:1709)) + (PORT datab (675:675:675) (802:802:802)) + (PORT datac (1190:1190:1190) (1383:1383:1383)) + (PORT datad (590:590:590) (658:658:658)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53262,7 +55608,7 @@ (ABSOLUTE (PORT clk (908:908:908) (913:913:913)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (1089:1089:1089) (1200:1200:1200)) + (PORT ena (510:510:510) (556:556:556)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -53276,12 +55622,12 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~19) (DELAY (ABSOLUTE - (PORT dataa (119:119:119) (156:156:156)) - (PORT datab (112:112:112) (144:144:144)) - (PORT datac (132:132:132) (181:181:181)) - (PORT datad (132:132:132) (175:175:175)) + (PORT dataa (288:288:288) (336:336:336)) + (PORT datab (154:154:154) (209:209:209)) + (PORT datac (135:135:135) (184:184:184)) + (PORT datad (99:99:99) (121:121:121)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -53301,11 +55647,11 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~20) (DELAY (ABSOLUTE - (PORT dataa (751:751:751) (865:865:865)) - (PORT datab (734:734:734) (861:861:861)) - (PORT datad (433:433:433) (467:467:467)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (182:182:182) (177:177:177)) + (PORT dataa (545:545:545) (640:640:640)) + (PORT datab (293:293:293) (341:341:341)) + (PORT datad (422:422:422) (452:452:452)) + (IOPATH dataa combout (181:181:181) (175:175:175)) + (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -53316,9 +55662,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (1102:1102:1102) (1123:1123:1123)) + (PORT clk (1117:1117:1117) (1144:1144:1144)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) + (PORT clrn (908:908:908) (911:911:911)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53332,24 +55678,24 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~18) (DELAY (ABSOLUTE - (PORT datab (131:131:131) (178:178:178)) - (PORT datad (711:711:711) (829:829:829)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datac (512:512:512) (595:595:595)) + (PORT datad (120:120:120) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~2) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]\~2) (DELAY (ABSOLUTE - (PORT datab (123:123:123) (159:159:159)) - (PORT datac (470:470:470) (543:543:543)) - (PORT datad (133:133:133) (176:176:176)) - (IOPATH datab combout (166:166:166) (167:167:167)) + (PORT dataa (497:497:497) (576:576:576)) + (PORT datab (152:152:152) (208:208:208)) + (PORT datac (106:106:106) (130:130:130)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -53358,10 +55704,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (923:923:923) (931:931:931)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (908:908:908) (911:911:911)) + (PORT ena (711:711:711) (764:764:764)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53376,9 +55722,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~17) (DELAY (ABSOLUTE - (PORT datac (117:117:117) (157:157:157)) - (PORT datad (712:712:712) (830:830:830)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datac (521:521:521) (606:606:606)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53388,10 +55734,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[2\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (923:923:923) (931:931:931)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (908:908:908) (911:911:911)) + (PORT ena (711:711:711) (764:764:764)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53406,10 +55752,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~16) (DELAY (ABSOLUTE - (PORT datab (131:131:131) (179:179:179)) - (PORT datad (714:714:714) (833:833:833)) + (PORT datab (130:130:130) (179:179:179)) + (PORT datac (518:518:518) (603:603:603)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -53418,10 +55764,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[3\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (923:923:923) (931:931:931)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (908:908:908) (911:911:911)) + (PORT ena (711:711:711) (764:764:764)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53436,9 +55782,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~15) (DELAY (ABSOLUTE - (PORT datab (132:132:132) (181:181:181)) - (PORT datad (723:723:723) (843:843:843)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datac (515:515:515) (599:599:599)) + (PORT datad (118:118:118) (154:154:154)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53448,10 +55794,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (923:923:923) (931:931:931)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (908:908:908) (911:911:911)) + (PORT ena (711:711:711) (764:764:764)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53466,10 +55812,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~14) (DELAY (ABSOLUTE - (PORT datab (131:131:131) (180:180:180)) - (PORT datad (719:719:719) (838:838:838)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT dataa (132:132:132) (184:184:184)) + (PORT datac (522:522:522) (608:608:608)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -53478,10 +55824,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (923:923:923) (931:931:931)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (908:908:908) (911:911:911)) + (PORT ena (711:711:711) (764:764:764)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53496,9 +55842,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~13) (DELAY (ABSOLUTE - (PORT dataa (132:132:132) (183:183:183)) - (PORT datad (715:715:715) (834:834:834)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datac (517:517:517) (602:602:602)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53508,10 +55854,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (923:923:923) (931:931:931)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (908:908:908) (911:911:911)) + (PORT ena (711:711:711) (764:764:764)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53526,9 +55872,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~12) (DELAY (ABSOLUTE - (PORT datab (131:131:131) (180:180:180)) - (PORT datad (709:709:709) (827:827:827)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datac (525:525:525) (610:610:610)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53538,10 +55884,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (923:923:923) (931:931:931)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (908:908:908) (911:911:911)) + (PORT ena (711:711:711) (764:764:764)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53556,10 +55902,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~11) (DELAY (ABSOLUTE - (PORT datac (116:116:116) (157:157:157)) - (PORT datad (710:710:710) (828:828:828)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datab (130:130:130) (178:178:178)) + (PORT datac (528:528:528) (614:614:614)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -53568,10 +55914,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (923:923:923) (931:931:931)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (908:908:908) (911:911:911)) + (PORT ena (711:711:711) (764:764:764)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53586,9 +55932,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~10) (DELAY (ABSOLUTE - (PORT datab (131:131:131) (179:179:179)) - (PORT datad (713:713:713) (831:831:831)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datac (527:527:527) (613:613:613)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53598,10 +55944,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[9\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (923:923:923) (931:931:931)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (908:908:908) (911:911:911)) + (PORT ena (711:711:711) (764:764:764)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53616,10 +55962,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~9) (DELAY (ABSOLUTE - (PORT datac (118:118:118) (159:159:159)) - (PORT datad (718:718:718) (837:837:837)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datab (131:131:131) (179:179:179)) + (PORT datac (523:523:523) (609:609:609)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -53628,10 +55974,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[10\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (923:923:923) (931:931:931)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (908:908:908) (911:911:911)) + (PORT ena (711:711:711) (764:764:764)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53646,9 +55992,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~8) (DELAY (ABSOLUTE - (PORT dataa (132:132:132) (182:182:182)) - (PORT datad (722:722:722) (842:842:842)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datac (529:529:529) (615:615:615)) + (PORT datad (118:118:118) (154:154:154)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53658,10 +56004,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[11\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (923:923:923) (931:931:931)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (908:908:908) (911:911:911)) + (PORT ena (711:711:711) (764:764:764)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53676,9 +56022,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~7) (DELAY (ABSOLUTE - (PORT datab (130:130:130) (179:179:179)) - (PORT datad (720:720:720) (839:839:839)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datac (513:513:513) (597:597:597)) + (PORT datad (120:120:120) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53688,10 +56034,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[12\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (923:923:923) (931:931:931)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (908:908:908) (911:911:911)) + (PORT ena (711:711:711) (764:764:764)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53706,9 +56052,9 @@ (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) (DELAY (ABSOLUTE - (PORT dataa (783:783:783) (903:903:903)) - (PORT datab (487:487:487) (568:568:568)) - (PORT datad (124:124:124) (165:165:165)) + (PORT dataa (238:238:238) (296:296:296)) + (PORT datab (525:525:525) (612:612:612)) + (PORT datad (128:128:128) (169:169:169)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -53721,9 +56067,9 @@ (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) + (PORT clk (916:916:916) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (912:912:912)) + (PORT clrn (905:905:905) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53737,9 +56083,9 @@ (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) (DELAY (ABSOLUTE - (PORT dataa (783:783:783) (903:903:903)) - (PORT datab (487:487:487) (568:568:568)) - (PORT datad (125:125:125) (165:165:165)) + (PORT dataa (238:238:238) (296:296:296)) + (PORT datab (525:525:525) (612:612:612)) + (PORT datad (127:127:127) (169:169:169)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (190:190:190) (188:188:188)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -53752,9 +56098,9 @@ (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) + (PORT clk (916:916:916) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (912:912:912)) + (PORT clrn (905:905:905) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53768,9 +56114,9 @@ (INSTANCE ula_\|pcm_outr\~0) (DELAY (ABSOLUTE - (PORT datac (119:119:119) (161:161:161)) - (PORT datad (120:120:120) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (132:132:132) (182:182:182)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53780,9 +56126,9 @@ (INSTANCE ula_\|pcm_outl\[12\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (915:915:915)) + (PORT clk (912:912:912) (917:917:917)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (1148:1148:1148) (1270:1270:1270)) + (PORT ena (1630:1630:1630) (1808:1808:1808)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -53796,11 +56142,11 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~6) (DELAY (ABSOLUTE - (PORT datab (738:738:738) (865:865:865)) - (PORT datac (117:117:117) (158:158:158)) - (PORT datad (720:720:720) (842:842:842)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (132:132:132) (182:182:182)) + (PORT datac (516:516:516) (601:601:601)) + (PORT datad (192:192:192) (239:239:239)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53810,10 +56156,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[13\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (923:923:923) (931:931:931)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (908:908:908) (911:911:911)) + (PORT ena (711:711:711) (764:764:764)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53828,11 +56174,11 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~5) (DELAY (ABSOLUTE - (PORT datab (698:698:698) (823:823:823)) - (PORT datac (117:117:117) (158:158:158)) - (PORT datad (722:722:722) (841:841:841)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datab (786:786:786) (914:914:914)) + (PORT datac (510:510:510) (594:594:594)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53842,10 +56188,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[14\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (923:923:923) (931:931:931)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (908:908:908) (911:911:911)) + (PORT ena (711:711:711) (764:764:764)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53855,14 +56201,24 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|pcm_outl\[14\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (349:349:349)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|pcm_outl\[14\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) + (PORT clk (908:908:908) (913:913:913)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (1213:1213:1213) (1335:1335:1335)) + (PORT ena (510:510:510) (556:556:556)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -53876,11 +56232,11 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~4) (DELAY (ABSOLUTE - (PORT dataa (683:683:683) (796:796:796)) - (PORT datac (555:555:555) (662:662:662)) - (PORT datad (356:356:356) (415:415:415)) + (PORT dataa (143:143:143) (194:194:194)) + (PORT datac (514:514:514) (598:598:598)) + (PORT datad (850:850:850) (990:990:990)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53890,10 +56246,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[15\]) (DELAY (ABSOLUTE - (PORT clk (1108:1108:1108) (1141:1141:1141)) + (PORT clk (923:923:923) (931:931:931)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) - (PORT ena (599:599:599) (641:641:641)) + (PORT clrn (908:908:908) (911:911:911)) + (PORT ena (711:711:711) (764:764:764)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53908,9 +56264,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~3) (DELAY (ABSOLUTE - (PORT datac (116:116:116) (157:157:157)) - (PORT datad (357:357:357) (416:416:416)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datab (328:328:328) (384:384:384)) + (PORT datad (354:354:354) (428:428:428)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53920,10 +56276,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[16\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) + (PORT clk (1117:1117:1117) (1149:1149:1149)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) - (PORT ena (617:617:617) (670:670:670)) + (PORT clrn (904:904:904) (907:907:907)) + (PORT ena (756:756:756) (822:822:822)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53938,9 +56294,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~0) (DELAY (ABSOLUTE - (PORT datab (131:131:131) (179:179:179)) - (PORT datad (354:354:354) (413:413:413)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datab (327:327:327) (382:382:382)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53951,9 +56307,9 @@ (DELAY (ABSOLUTE (PORT clk (893:893:893) (915:915:915)) - (PORT d (827:827:827) (902:902:902)) - (PORT clrn (1031:1031:1031) (1077:1077:1077)) - (PORT ena (946:946:946) (1053:1053:1053)) + (PORT d (609:609:609) (642:642:642)) + (PORT clrn (1022:1022:1022) (1066:1066:1066)) + (PORT ena (447:447:447) (471:471:471)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) ) @@ -53967,106 +56323,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan2\~0) + (INSTANCE ula_\|border\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (159:159:159) (210:210:210)) - (PORT datab (147:147:147) (197:197:197)) - (PORT datac (144:144:144) (185:185:185)) - (PORT datad (133:133:133) (172:172:172)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (142:142:142) (192:192:192)) - (PORT datab (140:140:140) (188:188:188)) - (PORT datac (141:141:141) (182:182:182)) - (PORT datad (131:131:131) (168:168:168)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (310:310:310)) - (PORT datab (146:146:146) (196:196:196)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (188:188:188) (214:214:214)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (159:159:159) (212:212:212)) - (PORT datab (129:129:129) (157:157:157)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (147:147:147) (201:201:201)) - (PORT datab (141:141:141) (189:189:189)) - (PORT datad (136:136:136) (176:176:176)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|disp_enable\~0) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (215:215:215) (273:273:273)) - (PORT datad (361:361:361) (423:423:423)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (191:191:191) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|disp_enable\~1) - (DELAY - (ABSOLUTE - (PORT dataa (113:113:113) (148:148:148)) - (PORT datab (109:109:109) (140:140:140)) - (PORT datad (179:179:179) (213:213:213)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (158:158:158)) + (PORT datad (636:636:636) (725:725:725)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54076,29 +56336,45 @@ (INSTANCE ula_\|border\[1\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (915:915:915)) - (PORT asdata (279:279:279) (298:298:298)) - (PORT ena (1148:1148:1148) (1270:1270:1270)) + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (961:961:961) (1066:1066:1066)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) + (HOLD d (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (149:149:149) (205:205:205)) + (PORT datab (141:141:141) (188:188:188)) + (PORT datac (127:127:127) (167:167:167)) + (PORT datad (128:128:128) (164:164:164)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|LessThan6\~1) (DELAY (ABSOLUTE - (PORT dataa (245:245:245) (312:312:312)) - (PORT datab (252:252:252) (318:318:318)) - (PORT datac (232:232:232) (290:290:290)) - (PORT datad (220:220:220) (255:255:255)) + (PORT dataa (154:154:154) (204:204:204)) + (PORT datab (153:153:153) (201:201:201)) + (PORT datac (209:209:209) (253:253:253)) + (PORT datad (104:104:104) (121:121:121)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54108,9 +56384,9 @@ (INSTANCE ula_\|video_\|LessThan4\~0) (DELAY (ABSOLUTE - (PORT dataa (146:146:146) (199:199:199)) - (PORT datab (149:149:149) (200:200:200)) - (PORT datad (128:128:128) (164:164:164)) + (PORT dataa (231:231:231) (286:286:286)) + (PORT datab (148:148:148) (199:199:199)) + (PORT datad (128:128:128) (165:165:165)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -54123,13 +56399,13 @@ (INSTANCE ula_\|video_\|screen_en\~0) (DELAY (ABSOLUTE - (PORT dataa (236:236:236) (294:294:294)) - (PORT datab (249:249:249) (311:311:311)) - (PORT datac (288:288:288) (330:330:330)) - (PORT datad (348:348:348) (416:416:416)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT dataa (218:218:218) (287:287:287)) + (PORT datab (353:353:353) (421:421:421)) + (PORT datac (321:321:321) (382:382:382)) + (PORT datad (269:269:269) (304:304:304)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54139,9 +56415,9 @@ (INSTANCE ula_\|video_\|screen_en\~1) (DELAY (ABSOLUTE - (PORT dataa (365:365:365) (435:435:435)) - (PORT datab (258:258:258) (322:322:322)) - (PORT datac (90:90:90) (112:112:112)) + (PORT dataa (151:151:151) (205:205:205)) + (PORT datab (157:157:157) (204:204:204)) + (PORT datac (174:174:174) (209:209:209)) (PORT datad (91:91:91) (109:109:109)) (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (167:167:167) (156:156:156)) @@ -54152,10 +56428,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) + (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (823:823:823) (939:939:939)) + (PORT datad (508:508:508) (580:580:580)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54165,12 +56441,12 @@ (INSTANCE ula_\|video_\|Decoder0\~1) (DELAY (ABSOLUTE - (PORT dataa (682:682:682) (811:811:811)) - (PORT datab (533:533:533) (638:638:638)) - (PORT datac (532:532:532) (636:636:636)) - (PORT datad (153:153:153) (202:202:202)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (241:241:241) (311:311:311)) + (PORT datab (526:526:526) (627:627:627)) + (PORT datac (380:380:380) (462:462:462)) + (PORT datad (400:400:400) (479:479:479)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -54178,12 +56454,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]) + (INSTANCE ula_\|video_\|attr_prefetch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1138:1138:1138) (1170:1170:1170)) + (PORT clk (1120:1120:1120) (1150:1150:1150)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (772:772:772) (840:840:840)) + (PORT ena (635:635:635) (688:688:688)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54197,10 +56473,10 @@ (INSTANCE ula_\|video_\|Decoder0\~0) (DELAY (ABSOLUTE - (PORT dataa (682:682:682) (810:810:810)) - (PORT datab (533:533:533) (638:638:638)) - (PORT datac (532:532:532) (637:637:637)) - (PORT datad (154:154:154) (203:203:203)) + (PORT dataa (240:240:240) (311:311:311)) + (PORT datab (522:522:522) (622:622:622)) + (PORT datac (382:382:382) (465:465:465)) + (PORT datad (397:397:397) (476:476:476)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -54208,98 +56484,14 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (921:921:921)) - (PORT asdata (974:974:974) (1094:1094:1094)) - (PORT ena (745:745:745) (812:812:812)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (859:859:859) (961:961:961)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1138:1138:1138) (1170:1170:1170)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (772:772:772) (840:840:840)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (921:921:921)) - (PORT asdata (538:538:538) (609:609:609)) - (PORT ena (745:745:745) (812:812:812)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (684:684:684) (780:780:780)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1138:1138:1138) (1170:1170:1170)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (772:772:772) (840:840:840)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|attr\[7\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) - (PORT asdata (535:535:535) (606:606:606)) - (PORT ena (747:747:747) (817:817:817)) + (PORT clk (921:921:921) (925:925:925)) + (PORT asdata (614:614:614) (686:686:686)) + (PORT ena (642:642:642) (689:689:689)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54313,9 +56505,10 @@ (INSTANCE ula_\|video_\|frame\[0\]\~12) (DELAY (ABSOLUTE - (PORT dataa (326:326:326) (380:380:380)) - (IOPATH dataa combout (195:195:195) (203:203:203)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT datab (647:647:647) (744:744:744)) + (PORT datad (124:124:124) (163:163:163)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -54324,13 +56517,13 @@ (INSTANCE ula_\|video_\|frame\[0\]) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) + (PORT clk (1102:1102:1102) (1123:1123:1123)) + (PORT asdata (268:268:268) (288:288:288)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) ) ) (CELL @@ -54338,8 +56531,8 @@ (INSTANCE ula_\|video_\|frame\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (319:319:319) (383:383:383)) - (PORT datab (130:130:130) (178:178:178)) + (PORT dataa (202:202:202) (258:258:258)) + (PORT datab (135:135:135) (185:185:185)) (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datab combout (190:190:190) (181:181:181)) @@ -54353,9 +56546,9 @@ (INSTANCE ula_\|video_\|frame\[1\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (923:923:923)) + (PORT clk (917:917:917) (922:922:922)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (642:642:642) (697:697:697)) + (PORT ena (946:946:946) (1033:1033:1033)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54369,9 +56562,9 @@ (INSTANCE ula_\|video_\|frame\[2\]\~6) (DELAY (ABSOLUTE - (PORT dataa (131:131:131) (182:182:182)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (130:130:130) (178:178:178)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -54383,9 +56576,9 @@ (INSTANCE ula_\|video_\|frame\[2\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (923:923:923)) + (PORT clk (917:917:917) (922:922:922)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (642:642:642) (697:697:697)) + (PORT ena (946:946:946) (1033:1033:1033)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54413,9 +56606,9 @@ (INSTANCE ula_\|video_\|frame\[3\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (923:923:923)) + (PORT clk (917:917:917) (922:922:922)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (642:642:642) (697:697:697)) + (PORT ena (946:946:946) (1033:1033:1033)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54429,8 +56622,8 @@ (INSTANCE ula_\|video_\|frame\[4\]\~10) (DELAY (ABSOLUTE - (PORT dataa (142:142:142) (193:193:193)) - (IOPATH dataa combout (195:195:195) (203:203:203)) + (PORT datad (200:200:200) (246:246:246)) + (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) ) ) @@ -54440,14 +56633,14 @@ (INSTANCE ula_\|video_\|frame\[4\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (642:642:642) (697:697:697)) + (PORT clk (917:917:917) (922:922:922)) + (PORT asdata (340:340:340) (365:365:365)) + (PORT ena (946:946:946) (1033:1033:1033)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) @@ -54456,7 +56649,7 @@ (INSTANCE ula_\|video_\|inverted) (DELAY (ABSOLUTE - (PORT datad (196:196:196) (239:239:239)) + (PORT datad (358:358:358) (427:427:427)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -54467,7 +56660,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (646:646:646) (734:734:734)) + (PORT datad (595:595:595) (672:672:672)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54477,13 +56670,13 @@ (INSTANCE ula_\|video_\|Decoder0\~2) (DELAY (ABSOLUTE - (PORT dataa (682:682:682) (811:811:811)) - (PORT datab (534:534:534) (639:639:639)) - (PORT datac (531:531:531) (635:635:635)) - (PORT datad (152:152:152) (201:201:201)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (241:241:241) (311:311:311)) + (PORT datab (523:523:523) (624:624:624)) + (PORT datac (381:381:381) (464:464:464)) + (PORT datad (398:398:398) (478:478:478)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54493,9 +56686,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1123:1123:1123) (1148:1148:1148)) + (PORT clk (1105:1105:1105) (1124:1124:1124)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (773:773:773) (844:844:844)) + (PORT ena (638:638:638) (699:699:699)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54504,29 +56697,19 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (335:335:335) (394:394:394)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits\[6\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (747:747:747) (817:817:817)) + (PORT clk (921:921:921) (925:925:925)) + (PORT asdata (716:716:716) (820:820:820)) + (PORT ena (642:642:642) (689:689:689)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) @@ -54535,7 +56718,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (858:858:858) (960:960:960)) + (PORT datad (793:793:793) (898:898:898)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54545,9 +56728,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1123:1123:1123) (1148:1148:1148)) + (PORT clk (1105:1105:1105) (1124:1124:1124)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (773:773:773) (844:844:844)) + (PORT ena (638:638:638) (699:699:699)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54561,9 +56744,9 @@ (INSTANCE ula_\|video_\|bits\[4\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) - (PORT asdata (535:535:535) (601:601:601)) - (PORT ena (747:747:747) (817:817:817)) + (PORT clk (921:921:921) (925:925:925)) + (PORT asdata (523:523:523) (594:594:594)) + (PORT ena (642:642:642) (689:689:689)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54577,7 +56760,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (522:522:522) (600:600:600)) + (PORT datad (524:524:524) (604:604:604)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54587,9 +56770,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1123:1123:1123) (1148:1148:1148)) + (PORT clk (1105:1105:1105) (1124:1124:1124)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (773:773:773) (844:844:844)) + (PORT ena (638:638:638) (699:699:699)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54603,7 +56786,7 @@ (INSTANCE ula_\|video_\|bits\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (356:356:356) (420:420:420)) + (PORT datad (352:352:352) (426:426:426)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54613,9 +56796,9 @@ (INSTANCE ula_\|video_\|bits\[5\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) + (PORT clk (921:921:921) (925:925:925)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (747:747:747) (817:817:817)) + (PORT ena (642:642:642) (689:689:689)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54629,7 +56812,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (688:688:688) (785:785:785)) + (PORT datad (506:506:506) (577:577:577)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54639,9 +56822,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1123:1123:1123) (1148:1148:1148)) + (PORT clk (1105:1105:1105) (1124:1124:1124)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (773:773:773) (844:844:844)) + (PORT ena (638:638:638) (699:699:699)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54655,9 +56838,9 @@ (INSTANCE ula_\|video_\|bits\[7\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) - (PORT asdata (648:648:648) (729:729:729)) - (PORT ena (747:747:747) (817:817:817)) + (PORT clk (921:921:921) (925:925:925)) + (PORT asdata (529:529:529) (602:602:602)) + (PORT ena (642:642:642) (689:689:689)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54671,9 +56854,9 @@ (INSTANCE ula_\|video_\|Mux0\~0) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (262:262:262)) - (PORT datab (158:158:158) (212:212:212)) - (PORT datad (338:338:338) (401:401:401)) + (PORT dataa (170:170:170) (225:225:225)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datad (198:198:198) (241:241:241)) (IOPATH dataa combout (166:166:166) (159:159:159)) (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -54686,11 +56869,11 @@ (INSTANCE ula_\|video_\|Mux0\~1) (DELAY (ABSOLUTE - (PORT dataa (131:131:131) (182:182:182)) - (PORT datab (155:155:155) (209:209:209)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (177:177:177)) + (PORT dataa (168:168:168) (225:225:225)) + (PORT datab (132:132:132) (180:180:180)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -54701,7 +56884,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (485:485:485) (555:555:555)) + (PORT datad (573:573:573) (644:644:644)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54711,9 +56894,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1123:1123:1123) (1148:1148:1148)) + (PORT clk (1105:1105:1105) (1124:1124:1124)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (773:773:773) (844:844:844)) + (PORT ena (638:638:638) (699:699:699)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54727,7 +56910,7 @@ (INSTANCE ula_\|video_\|bits\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (350:350:350) (413:413:413)) + (PORT datad (351:351:351) (422:422:422)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54737,9 +56920,9 @@ (INSTANCE ula_\|video_\|bits\[2\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) + (PORT clk (921:921:921) (925:925:925)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (747:747:747) (817:817:817)) + (PORT ena (642:642:642) (689:689:689)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54753,7 +56936,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (800:800:800) (885:885:885)) + (PORT datad (503:503:503) (574:574:574)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54763,9 +56946,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1123:1123:1123) (1148:1148:1148)) + (PORT clk (1105:1105:1105) (1124:1124:1124)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (773:773:773) (844:844:844)) + (PORT ena (638:638:638) (699:699:699)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54779,9 +56962,9 @@ (INSTANCE ula_\|video_\|bits\[0\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) - (PORT asdata (526:526:526) (585:585:585)) - (PORT ena (747:747:747) (817:817:817)) + (PORT clk (921:921:921) (925:925:925)) + (PORT asdata (810:810:810) (921:921:921)) + (PORT ena (642:642:642) (689:689:689)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54795,7 +56978,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (821:821:821) (936:936:936)) + (PORT datad (351:351:351) (404:404:404)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54805,9 +56988,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1123:1123:1123) (1148:1148:1148)) + (PORT clk (1105:1105:1105) (1124:1124:1124)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (773:773:773) (844:844:844)) + (PORT ena (638:638:638) (699:699:699)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54821,7 +57004,7 @@ (INSTANCE ula_\|video_\|bits\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (347:347:347) (411:411:411)) + (PORT datad (350:350:350) (422:422:422)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54831,9 +57014,9 @@ (INSTANCE ula_\|video_\|bits\[1\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) + (PORT clk (921:921:921) (925:925:925)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (747:747:747) (817:817:817)) + (PORT ena (642:642:642) (689:689:689)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54847,7 +57030,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (687:687:687) (771:771:771)) + (PORT datad (515:515:515) (592:592:592)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54857,9 +57040,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1123:1123:1123) (1148:1148:1148)) + (PORT clk (1105:1105:1105) (1124:1124:1124)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (773:773:773) (844:844:844)) + (PORT ena (638:638:638) (699:699:699)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54873,9 +57056,9 @@ (INSTANCE ula_\|video_\|bits\[3\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) - (PORT asdata (762:762:762) (848:848:848)) - (PORT ena (747:747:747) (817:817:817)) + (PORT clk (921:921:921) (925:925:925)) + (PORT asdata (618:618:618) (692:692:692)) + (PORT ena (642:642:642) (689:689:689)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54889,9 +57072,9 @@ (INSTANCE ula_\|video_\|Mux0\~2) (DELAY (ABSOLUTE - (PORT dataa (130:130:130) (180:180:180)) - (PORT datab (155:155:155) (209:209:209)) - (PORT datad (335:335:335) (398:398:398)) + (PORT dataa (173:173:173) (231:231:231)) + (PORT datab (131:131:131) (179:179:179)) + (PORT datad (201:201:201) (245:245:245)) (IOPATH dataa combout (166:166:166) (159:159:159)) (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -54904,11 +57087,11 @@ (INSTANCE ula_\|video_\|Mux0\~3) (DELAY (ABSOLUTE - (PORT dataa (130:130:130) (180:180:180)) - (PORT datab (157:157:157) (211:211:211)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (177:177:177)) + (PORT dataa (174:174:174) (231:231:231)) + (PORT datab (130:130:130) (177:177:177)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -54916,45 +57099,218 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|cindex\[1\]\~0) + (INSTANCE ula_\|video_\|cindex\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (210:210:210) (268:268:268)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (90:90:90) (112:112:112)) + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (104:104:104) (133:133:133)) (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (181:181:181) (184:184:184)) - (IOPATH datab combout (192:192:192) (188:188:188)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (792:792:792) (897:897:897)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1120:1120:1120) (1150:1150:1150)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (635:635:635) (688:688:688)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (921:921:921) (925:925:925)) + (PORT asdata (532:532:532) (610:610:610)) + (PORT ena (642:642:642) (689:689:689)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (351:351:351) (404:404:404)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1120:1120:1120) (1150:1150:1150)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (635:635:635) (688:688:688)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (921:921:921) (926:926:926)) + (PORT asdata (532:532:532) (606:606:606)) + (PORT ena (766:766:766) (838:838:838)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|cindex\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (131:131:131) (183:183:183)) - (PORT datad (179:179:179) (206:206:206)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (113:113:113) (149:149:149)) + (PORT datad (184:184:184) (228:228:228)) + (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (286:286:286)) + (PORT datab (158:158:158) (208:208:208)) + (PORT datac (139:139:139) (185:185:185)) + (PORT datad (146:146:146) (185:185:185)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (408:408:408)) + (PORT datab (243:243:243) (300:300:300)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (184:184:184) (213:213:213)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (287:287:287)) + (PORT datab (244:244:244) (301:301:301)) + (PORT datac (103:103:103) (125:125:125)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (141:141:141) (192:192:192)) + (PORT datad (137:137:137) (177:177:177)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|disp_enable\~0) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (411:411:411)) + (PORT datab (141:141:141) (190:190:190)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|disp_enable\~1) + (DELAY + (ABSOLUTE + (PORT datab (107:107:107) (138:138:138)) + (PORT datac (101:101:101) (121:121:121)) + (PORT datad (268:268:268) (305:305:305)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|VGA_R\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (214:214:214) (266:266:266)) - (PORT datab (820:820:820) (958:958:958)) - (PORT datac (128:128:128) (155:155:155)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT dataa (811:811:811) (938:938:938)) + (PORT datab (123:123:123) (155:155:155)) + (PORT datac (166:166:166) (197:197:197)) + (PORT datad (109:109:109) (128:128:128)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54964,7 +57320,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (648:648:648) (736:736:736)) + (PORT datad (593:593:593) (671:671:671)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54974,9 +57330,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1138:1138:1138) (1170:1170:1170)) + (PORT clk (1120:1120:1120) (1150:1150:1150)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (772:772:772) (840:840:840)) + (PORT ena (635:635:635) (688:688:688)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54990,9 +57346,9 @@ (INSTANCE ula_\|video_\|attr\[6\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT asdata (655:655:655) (731:731:731)) - (PORT ena (858:858:858) (937:937:937)) + (PORT clk (921:921:921) (925:925:925)) + (PORT asdata (520:520:520) (585:585:585)) + (PORT ena (671:671:671) (738:738:738)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -55006,11 +57362,11 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (114:114:114) (149:149:149)) - (PORT datab (110:110:110) (141:141:141)) - (PORT datad (179:179:179) (214:214:214)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (PORT dataa (188:188:188) (224:224:224)) + (PORT datab (606:606:606) (691:691:691)) + (PORT datad (98:98:98) (118:118:118)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -55021,11 +57377,21 @@ (INSTANCE ula_\|video_\|VGA_R\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (147:147:147) (185:185:185)) - (PORT datac (207:207:207) (250:250:250)) - (PORT datad (94:94:94) (112:112:112)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (187:187:187) (228:228:228)) + (PORT datab (127:127:127) (160:160:160)) + (PORT datac (167:167:167) (197:197:197)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|border\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (738:738:738) (826:826:826)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55035,35 +57401,9 @@ (INSTANCE ula_\|border\[2\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (911:911:911)) - (PORT asdata (495:495:495) (538:538:538)) - (PORT ena (418:418:418) (434:434:434)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (486:486:486) (555:555:555)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1138:1138:1138) (1170:1170:1170)) + (PORT clk (911:911:911) (915:915:915)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (772:772:772) (840:840:840)) + (PORT ena (1059:1059:1059) (1163:1163:1163)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -55072,28 +57412,12 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) - (PORT asdata (641:641:641) (711:711:711)) - (PORT ena (747:747:747) (817:817:817)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|attr_prefetch\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (521:521:521) (599:599:599)) + (PORT datad (522:522:522) (602:602:602)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55103,9 +57427,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1138:1138:1138) (1170:1170:1170)) + (PORT clk (1120:1120:1120) (1150:1150:1150)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (772:772:772) (840:840:840)) + (PORT ena (635:635:635) (688:688:688)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -55119,9 +57443,51 @@ (INSTANCE ula_\|video_\|attr\[5\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) - (PORT asdata (528:528:528) (588:588:588)) - (PORT ena (747:747:747) (817:817:817)) + (PORT clk (921:921:921) (925:925:925)) + (PORT asdata (543:543:543) (613:613:613)) + (PORT ena (642:642:642) (689:689:689)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (573:573:573) (645:645:645)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1120:1120:1120) (1150:1150:1150)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (635:635:635) (688:688:688)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (921:921:921) (925:925:925)) + (PORT asdata (758:758:758) (855:855:855)) + (PORT ena (642:642:642) (689:689:689)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -55135,9 +57501,9 @@ (INSTANCE ula_\|video_\|cindex\[2\]\~2) (DELAY (ABSOLUTE - (PORT datab (130:130:130) (177:177:177)) - (PORT datad (106:106:106) (126:126:126)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (PORT dataa (115:115:115) (151:151:151)) + (PORT datad (119:119:119) (155:155:155)) + (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -55148,12 +57514,12 @@ (INSTANCE ula_\|video_\|VGA_G\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1315:1315:1315) (1534:1534:1534)) - (PORT datab (221:221:221) (262:262:262)) - (PORT datac (203:203:203) (246:246:246)) - (PORT datad (294:294:294) (329:329:329)) + (PORT dataa (120:120:120) (152:152:152)) + (PORT datab (128:128:128) (161:161:161)) + (PORT datac (467:467:467) (548:548:548)) + (PORT datad (164:164:164) (192:192:192)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datab combout (160:160:160) (176:176:176)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -55164,11 +57530,21 @@ (INSTANCE ula_\|video_\|VGA_G\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (340:340:340) (400:400:400)) - (PORT datab (115:115:115) (144:144:144)) - (PORT datad (195:195:195) (224:224:224)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT dataa (184:184:184) (225:225:225)) + (PORT datac (308:308:308) (352:352:352)) + (PORT datad (160:160:160) (188:188:188)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|border\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (308:308:308) (350:350:350)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55178,9 +57554,51 @@ (INSTANCE ula_\|border\[0\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (915:915:915)) - (PORT asdata (823:823:823) (908:908:908)) - (PORT ena (1148:1148:1148) (1270:1270:1270)) + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (908:908:908) (996:996:996)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (505:505:505) (576:576:576)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1120:1120:1120) (1150:1150:1150)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (635:635:635) (688:688:688)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (921:921:921) (926:926:926)) + (PORT asdata (521:521:521) (592:592:592)) + (PORT ena (766:766:766) (838:838:838)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -55189,64 +57607,12 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (799:799:799) (884:884:884)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1138:1138:1138) (1170:1170:1170)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (772:772:772) (840:840:840)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (455:455:455) (523:523:523)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (921:921:921)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (745:745:745) (812:812:812)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|attr_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (687:687:687) (770:770:770)) + (PORT datad (518:518:518) (596:596:596)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55256,9 +57622,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1138:1138:1138) (1170:1170:1170)) + (PORT clk (1120:1120:1120) (1150:1150:1150)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (772:772:772) (840:840:840)) + (PORT ena (635:635:635) (688:688:688)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -55272,9 +57638,9 @@ (INSTANCE ula_\|video_\|attr\[3\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) - (PORT asdata (520:520:520) (583:583:583)) - (PORT ena (747:747:747) (817:817:817)) + (PORT clk (921:921:921) (925:925:925)) + (PORT asdata (525:525:525) (591:591:591)) + (PORT ena (642:642:642) (689:689:689)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -55288,8 +57654,8 @@ (INSTANCE ula_\|video_\|cindex\[0\]\~3) (DELAY (ABSOLUTE - (PORT datab (200:200:200) (258:258:258)) - (PORT datad (108:108:108) (127:127:127)) + (PORT datab (197:197:197) (253:253:253)) + (PORT datad (99:99:99) (121:121:121)) (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -55301,13 +57667,13 @@ (INSTANCE ula_\|video_\|VGA_B\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (215:215:215) (267:267:267)) - (PORT datab (933:933:933) (1067:1067:1067)) - (PORT datac (128:128:128) (155:155:155)) - (PORT datad (170:170:170) (200:200:200)) + (PORT dataa (991:991:991) (1148:1148:1148)) + (PORT datab (117:117:117) (145:145:145)) + (PORT datac (187:187:187) (222:222:222)) + (PORT datad (191:191:191) (223:223:223)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55317,11 +57683,11 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~2) (DELAY (ABSOLUTE - (PORT dataa (148:148:148) (185:185:185)) - (PORT datac (207:207:207) (250:250:250)) - (PORT datad (175:175:175) (206:206:206)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (185:185:185) (224:224:224)) + (PORT datab (180:180:180) (220:220:220)) + (PORT datad (193:193:193) (226:226:226)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55331,11 +57697,11 @@ (INSTANCE ula_\|video_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (364:364:364) (435:435:435)) - (PORT datab (154:154:154) (201:201:201)) - (PORT datad (346:346:346) (414:414:414)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (477:477:477) (566:566:566)) + (PORT datac (455:455:455) (529:529:529)) + (PORT datad (617:617:617) (713:713:713)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55345,7 +57711,7 @@ (INSTANCE ula_\|video_\|VGA_HS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (921:921:921)) + (PORT clk (920:920:920) (923:923:923)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -55359,9 +57725,9 @@ (INSTANCE ula_\|video_\|Selector0\~0) (DELAY (ABSOLUTE - (PORT dataa (540:540:540) (616:616:616)) - (PORT datab (120:120:120) (151:151:151)) - (PORT datad (300:300:300) (346:346:346)) + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (205:205:205) (250:250:250)) + (PORT datad (187:187:187) (217:217:217)) (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -55375,7 +57741,7 @@ (DELAY (ABSOLUTE (PORT clk (893:893:893) (915:915:915)) - (PORT d (917:917:917) (975:975:975)) + (PORT d (1277:1277:1277) (1374:1374:1374)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) ) ) @@ -55389,7 +57755,7 @@ (INSTANCE ula_\|video_\|VGA_VS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) + (PORT clk (921:921:921) (925:925:925)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -55403,11 +57769,11 @@ (INSTANCE ula_\|video_\|Selector1\~0) (DELAY (ABSOLUTE - (PORT dataa (325:325:325) (380:380:380)) - (PORT datab (627:627:627) (727:727:727)) - (PORT datad (383:383:383) (452:452:452)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (167:167:167)) + (PORT dataa (158:158:158) (215:215:215)) + (PORT datab (275:275:275) (318:318:318)) + (PORT datad (817:817:817) (933:933:933)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -55419,7 +57785,7 @@ (DELAY (ABSOLUTE (PORT clk (892:892:892) (914:914:914)) - (PORT d (979:979:979) (1050:1050:1050)) + (PORT d (867:867:867) (946:946:946)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) ) ) @@ -55433,7 +57799,7 @@ (INSTANCE z80_\|memory_ifc_\|q1\~feeder) (DELAY (ABSOLUTE - (PORT datad (323:323:323) (383:383:383)) + (PORT datad (137:137:137) (177:177:177)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55443,10 +57809,10 @@ (INSTANCE z80_\|memory_ifc_\|q1) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) + (PORT clk (906:906:906) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (924:924:924) (906:906:906)) - (PORT ena (783:783:783) (862:862:862)) + (PORT clrn (918:918:918) (901:901:901)) + (PORT ena (646:646:646) (704:704:704)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -55461,10 +57827,10 @@ (INSTANCE z80_\|memory_ifc_\|q2) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) - (PORT asdata (296:296:296) (335:335:335)) - (PORT clrn (924:924:924) (906:906:906)) - (PORT ena (783:783:783) (862:862:862)) + (PORT clk (906:906:906) (914:914:914)) + (PORT asdata (293:293:293) (332:332:332)) + (PORT clrn (918:918:918) (901:901:901)) + (PORT ena (646:646:646) (704:704:704)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -55479,7 +57845,7 @@ (INSTANCE z80_\|memory_ifc_\|nRFSH_out\~0) (DELAY (ABSOLUTE - (PORT datad (326:326:326) (386:386:386)) + (PORT datad (136:136:136) (176:176:176)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -55490,8 +57856,8 @@ (INSTANCE z80_\|memory_ifc_\|nM1_out) (DELAY (ABSOLUTE - (PORT datac (730:730:730) (833:833:833)) - (PORT datad (326:326:326) (387:387:387)) + (PORT datac (798:798:798) (916:916:916)) + (PORT datad (137:137:137) (178:178:178)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -55502,10 +57868,10 @@ (INSTANCE ula_\|beep\~0) (DELAY (ABSOLUTE - (PORT datab (972:972:972) (1130:1130:1130)) - (PORT datac (1872:1872:1872) (2097:2097:2097)) - (PORT datad (705:705:705) (818:818:818)) - (IOPATH datab combout (196:196:196) (205:205:205)) + (PORT dataa (545:545:545) (624:624:624)) + (PORT datac (2038:2038:2038) (2329:2329:2329)) + (PORT datad (304:304:304) (349:349:349)) + (IOPATH dataa combout (195:195:195) (203:203:203)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -55516,9 +57882,9 @@ (INSTANCE ula_\|beep) (DELAY (ABSOLUTE - (PORT clk (902:902:902) (907:907:907)) + (PORT clk (908:908:908) (913:913:913)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (1416:1416:1416) (1569:1569:1569)) + (PORT ena (510:510:510) (556:556:556)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -55527,4 +57893,2294 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux26\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1316:1316:1316) (1556:1556:1556)) + (PORT datab (520:520:520) (599:599:599)) + (PORT datad (798:798:798) (932:932:932)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT datac (572:572:572) (676:676:676)) + (PORT datad (1014:1014:1014) (1180:1180:1180)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (491:491:491) (582:582:582)) + (PORT datab (457:457:457) (559:559:559)) + (PORT datac (436:436:436) (536:536:536)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (160:160:160) (209:209:209)) + (PORT datac (303:303:303) (356:356:356)) + (PORT datad (157:157:157) (201:201:201)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (681:681:681)) + (PORT datab (556:556:556) (656:656:656)) + (PORT datac (578:578:578) (690:690:690)) + (PORT datad (317:317:317) (369:369:369)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (726:726:726) (865:865:865)) + (PORT datab (1052:1052:1052) (1235:1235:1235)) + (PORT datac (573:573:573) (677:677:677)) + (PORT datad (426:426:426) (487:487:487)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (707:707:707) (837:837:837)) + (PORT datac (1035:1035:1035) (1217:1217:1217)) + (PORT datad (561:561:561) (661:661:661)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (494:494:494) (585:585:585)) + (PORT datab (456:456:456) (557:557:557)) + (PORT datac (94:94:94) (118:118:118)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (727:727:727) (865:865:865)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.bank\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (895:895:895) (920:920:920)) + (PORT d (980:980:980) (1073:1073:1073)) + (PORT ena (941:941:941) (1026:1026:1026)) + (IOPATH (posedge clk) q (329:329:329) (329:329:329)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (41:41:41)) + (SETUP ena (posedge clk) (41:41:41)) + (HOLD d (posedge clk) (56:56:56)) + (HOLD ena (posedge clk) (56:56:56)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux25\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1316:1316:1316) (1556:1556:1556)) + (PORT datab (804:804:804) (945:945:945)) + (PORT datad (508:508:508) (576:576:576)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.bank\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (921:921:921)) + (PORT d (1315:1315:1315) (1459:1459:1459)) + (PORT ena (852:852:852) (930:930:930)) + (IOPATH (posedge clk) q (329:329:329) (329:329:329)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (41:41:41)) + (SETUP ena (posedge clk) (41:41:41)) + (HOLD d (posedge clk) (56:56:56)) + (HOLD ena (posedge clk) (56:56:56)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~5) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (733:733:733)) + (PORT datab (568:568:568) (679:679:679)) + (PORT datac (632:632:632) (733:733:733)) + (PORT datad (556:556:556) (655:655:655)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~0) + (DELAY + (ABSOLUTE + (PORT datab (793:793:793) (945:945:945)) + (PORT datac (870:870:870) (1025:1025:1025)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~7) + (DELAY + (ABSOLUTE + (PORT datab (975:975:975) (1160:1160:1160)) + (PORT datac (120:120:120) (162:162:162)) + (PORT datad (1486:1486:1486) (1744:1744:1744)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (460:460:460)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (94:94:94) (117:117:117)) + (PORT datad (98:98:98) (118:118:118)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~1) + (DELAY + (ABSOLUTE + (PORT dataa (738:738:738) (871:871:871)) + (PORT datab (816:816:816) (951:951:951)) + (PORT datac (872:872:872) (1027:1027:1027)) + (PORT datad (774:774:774) (921:921:921)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~2) + (DELAY + (ABSOLUTE + (PORT dataa (737:737:737) (870:870:870)) + (PORT datab (576:576:576) (687:687:687)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (97:97:97) (119:119:119)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~3) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (694:694:694)) + (PORT datab (113:113:113) (145:145:145)) + (PORT datac (594:594:594) (707:707:707)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~4) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (114:114:114) (147:147:147)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (565:565:565) (666:666:666)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.dq_masks\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (894:894:894) (918:918:918)) + (PORT d (815:815:815) (883:883:883)) + (IOPATH (posedge clk) q (329:329:329) (329:329:329)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (41:41:41)) + (HOLD d (posedge clk) (56:56:56)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.dq_masks\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (894:894:894) (918:918:918)) + (PORT d (808:808:808) (875:875:875)) + (IOPATH (posedge clk) q (329:329:329) (329:329:329)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (41:41:41)) + (HOLD d (posedge clk) (56:56:56)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT datac (864:864:864) (1018:1018:1018)) + (PORT datad (564:564:564) (666:666:666)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~3) + (DELAY + (ABSOLUTE + (PORT dataa (187:187:187) (230:230:230)) + (PORT datab (830:830:830) (968:968:968)) + (PORT datac (769:769:769) (913:913:913)) + (PORT datad (182:182:182) (209:209:209)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~5) + (DELAY + (ABSOLUTE + (PORT dataa (236:236:236) (296:296:296)) + (PORT datab (383:383:383) (471:471:471)) + (PORT datac (304:304:304) (356:356:356)) + (PORT datad (157:157:157) (201:201:201)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~4) + (DELAY + (ABSOLUTE + (PORT dataa (174:174:174) (216:216:216)) + (PORT datab (757:757:757) (892:892:892)) + (PORT datac (467:467:467) (531:531:531)) + (PORT datad (812:812:812) (945:945:945)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~2) + (DELAY + (ABSOLUTE + (PORT dataa (791:791:791) (942:942:942)) + (PORT datab (757:757:757) (891:891:891)) + (PORT datac (465:465:465) (530:530:530)) + (PORT datad (693:693:693) (810:810:810)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (428:428:428) (521:521:521)) + (PORT datab (161:161:161) (216:216:216)) + (PORT datac (352:352:352) (414:414:414)) + (PORT datad (415:415:415) (498:498:498)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~2) + (DELAY + (ABSOLUTE + (PORT datab (233:233:233) (291:291:291)) + (PORT datac (218:218:218) (272:272:272)) + (PORT datad (310:310:310) (366:366:366)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~3) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (281:281:281)) + (PORT datab (148:148:148) (198:198:198)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (224:224:224) (272:272:272)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (282:282:282)) + (PORT datab (234:234:234) (292:292:292)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (216:216:216) (266:266:266)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~4) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (224:224:224) (279:279:279)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (376:376:376) (452:452:452)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~5) + (DELAY + (ABSOLUTE + (PORT dataa (801:801:801) (932:932:932)) + (PORT datab (910:910:910) (1069:1069:1069)) + (PORT datac (739:739:739) (873:873:873)) + (PORT datad (174:174:174) (204:204:204)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~0) + (DELAY + (ABSOLUTE + (PORT datab (758:758:758) (892:892:892)) + (PORT datad (892:892:892) (1045:1045:1045)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~6) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (350:350:350) (409:409:409)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~7) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (702:702:702) (824:824:824)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (911:911:911)) + (PORT d (814:814:814) (895:895:895)) + (IOPATH (posedge clk) q (345:345:345) (339:339:339)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (40:40:40)) + (HOLD d (posedge clk) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~11) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (675:675:675)) + (PORT datab (567:567:567) (678:678:678)) + (PORT datac (632:632:632) (734:734:734)) + (PORT datad (558:558:558) (657:657:657)) + (IOPATH dataa combout (181:181:181) (193:193:193)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~6) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (731:731:731)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (590:590:590) (671:671:671)) + (PORT datad (555:555:555) (657:657:657)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~5) + (DELAY + (ABSOLUTE + (PORT dataa (737:737:737) (870:870:870)) + (PORT datab (793:793:793) (945:945:945)) + (PORT datac (542:542:542) (650:650:650)) + (PORT datad (342:342:342) (402:402:402)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~7) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (732:732:732)) + (PORT datab (794:794:794) (947:947:947)) + (PORT datac (544:544:544) (653:653:653)) + (PORT datad (556:556:556) (657:657:657)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~8) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (577:577:577) (688:688:688)) + (PORT datac (94:94:94) (118:118:118)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~9) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (117:117:117) (146:146:146)) + (PORT datac (94:94:94) (117:117:117)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (911:911:911)) + (PORT d (700:700:700) (771:771:771)) + (IOPATH (posedge clk) q (345:345:345) (339:339:339)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (40:40:40)) + (HOLD d (posedge clk) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ena_reg") + (INSTANCE sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl_e_DRAM_CLK.extena0_reg) + (DELAY + (ABSOLUTE + (PORT d (145:145:145) (118:118:118)) + (PORT clk (0:0:0) (0:0:0)) + (IOPATH (posedge clk) q (107:107:107) (107:107:107)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (52:52:52)) + (HOLD d (posedge clk) (57:57:57)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ena_reg") + (INSTANCE sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl_e_DRAM_CLK.extena1_reg) + (DELAY + (ABSOLUTE + (PORT d (0:0:0) (0:0:0)) + (PORT clk (0:0:0) (0:0:0)) + (IOPATH (posedge clk) q (175:175:175) (159:159:159)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (52:52:52)) + (HOLD d (posedge clk) (57:57:57)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~2) + (DELAY + (ABSOLUTE + (PORT dataa (420:420:420) (511:511:511)) + (PORT datab (430:430:430) (521:521:521)) + (PORT datad (153:153:153) (198:198:198)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (176:176:176)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~3) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (1002:1002:1002)) + (PORT datab (362:362:362) (427:427:427)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (793:793:793) (918:918:918)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~4) + (DELAY + (ABSOLUTE + (PORT dataa (785:785:785) (936:936:936)) + (PORT datab (758:758:758) (893:893:893)) + (PORT datac (344:344:344) (400:400:400)) + (PORT datad (166:166:166) (196:196:196)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~5) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (935:935:935)) + (PORT datab (758:758:758) (893:893:893)) + (PORT datac (877:877:877) (1031:1031:1031)) + (PORT datad (698:698:698) (815:815:815)) + (IOPATH dataa combout (181:181:181) (180:180:180)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~6) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (678:678:678)) + (PORT datab (579:579:579) (691:691:691)) + (PORT datac (597:597:597) (711:711:711)) + (PORT datad (558:558:558) (660:660:660)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~7) + (DELAY + (ABSOLUTE + (PORT dataa (497:497:497) (588:588:588)) + (PORT datab (454:454:454) (556:556:556)) + (PORT datac (437:437:437) (538:538:538)) + (PORT datad (160:160:160) (186:186:186)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~9) + (DELAY + (ABSOLUTE + (PORT dataa (801:801:801) (932:932:932)) + (PORT datab (700:700:700) (822:822:822)) + (PORT datac (468:468:468) (533:533:533)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~8) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (315:315:315) (363:363:363)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (907:907:907)) + (PORT d (1006:1006:1006) (1123:1123:1123)) + (IOPATH (posedge clk) q (345:345:345) (339:339:339)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (40:40:40)) + (HOLD d (posedge clk) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~2) + (DELAY + (ABSOLUTE + (PORT dataa (418:418:418) (512:512:512)) + (PORT datab (410:410:410) (505:505:505)) + (PORT datac (431:431:431) (526:526:526)) + (PORT datad (458:458:458) (534:534:534)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1761:1761:1761) (2049:2049:2049)) + (PORT datab (318:318:318) (383:383:383)) + (PORT datac (588:588:588) (703:703:703)) + (PORT datad (341:341:341) (404:404:404)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (369:369:369)) + (PORT datab (539:539:539) (641:641:641)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~9) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (935:935:935)) + (PORT datab (703:703:703) (826:826:826)) + (PORT datac (878:878:878) (1032:1032:1032)) + (PORT datad (810:810:810) (943:943:943)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~4) + (DELAY + (ABSOLUTE + (PORT dataa (791:791:791) (943:943:943)) + (PORT datab (696:696:696) (817:817:817)) + (PORT datac (868:868:868) (1022:1022:1022)) + (PORT datad (813:813:813) (946:946:946)) + (IOPATH dataa combout (181:181:181) (184:184:184)) + (IOPATH datab combout (182:182:182) (188:188:188)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~5) + (DELAY + (ABSOLUTE + (PORT datab (757:757:757) (891:891:891)) + (PORT datac (92:92:92) (115:115:115)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[0\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (925:925:925)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (271:271:271) (292:292:292)) + (PORT sload (872:872:872) (996:996:996)) + (PORT ena (663:663:663) (715:715:715)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1761:1761:1761) (2049:2049:2049)) + (PORT datab (318:318:318) (384:384:384)) + (PORT datac (193:193:193) (231:231:231)) + (PORT datad (341:341:341) (403:403:403)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~4) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (571:571:571)) + (PORT datab (320:320:320) (385:385:385)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (603:603:603) (700:700:700)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[0\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT datab (576:576:576) (685:685:685)) + (PORT datac (94:94:94) (117:117:117)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (890:890:890) (910:910:910)) + (PORT d (1122:1122:1122) (1241:1241:1241)) + (PORT ena (905:905:905) (1003:1003:1003)) + (IOPATH (posedge clk) q (345:345:345) (339:339:339)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (40:40:40)) + (SETUP ena (posedge clk) (40:40:40)) + (HOLD d (posedge clk) (58:58:58)) + (HOLD ena (posedge clk) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~_Duplicate_1feeder) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (142:142:142)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~4) + (DELAY + (ABSOLUTE + (PORT dataa (562:562:562) (676:676:676)) + (PORT datab (135:135:135) (184:184:184)) + (PORT datac (716:716:716) (840:840:840)) + (PORT datad (173:173:173) (205:205:205)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (423:423:423) (515:515:515)) + (PORT datab (430:430:430) (521:521:521)) + (PORT datac (348:348:348) (409:409:409)) + (PORT datad (151:151:151) (196:196:196)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~5) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (678:678:678)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (539:539:539) (633:633:633)) + (PORT datad (482:482:482) (551:551:551)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~6) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (680:680:680)) + (PORT datab (609:609:609) (728:728:728)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (471:471:471) (531:531:531)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (823:823:823)) + (PORT datab (596:596:596) (708:708:708)) + (PORT datac (709:709:709) (838:838:838)) + (PORT datad (540:540:540) (634:634:634)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[1\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (918:918:918)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (272:272:272) (294:294:294)) + (PORT sload (997:997:997) (899:899:899)) + (PORT ena (676:676:676) (745:745:745)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~2) + (DELAY + (ABSOLUTE + (PORT dataa (739:739:739) (881:881:881)) + (PORT datab (186:186:186) (228:228:228)) + (PORT datac (538:538:538) (632:632:632)) + (PORT datad (540:540:540) (641:641:641)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~3) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (882:882:882)) + (PORT datac (269:269:269) (311:311:311)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~1) + (DELAY + (ABSOLUTE + (PORT dataa (735:735:735) (877:877:877)) + (PORT datab (1478:1478:1478) (1732:1732:1732)) + (PORT datac (939:939:939) (1097:1097:1097)) + (PORT datad (543:543:543) (645:645:645)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (145:145:145)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (568:568:568) (682:682:682)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (921:921:921)) + (PORT d (820:820:820) (903:903:903)) + (PORT ena (1041:1041:1041) (1145:1145:1145)) + (IOPATH (posedge clk) q (329:329:329) (329:329:329)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (41:41:41)) + (SETUP ena (posedge clk) (41:41:41)) + (HOLD d (posedge clk) (56:56:56)) + (HOLD ena (posedge clk) (56:56:56)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (731:731:731) (872:872:872)) + (PORT datab (557:557:557) (657:657:657)) + (PORT datac (568:568:568) (681:681:681)) + (PORT datad (547:547:547) (649:649:649)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT datab (556:556:556) (656:656:656)) + (PORT datad (722:722:722) (853:853:853)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux21\~0) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (161:161:161)) + (PORT datab (605:605:605) (723:723:723)) + (PORT datac (160:160:160) (187:187:187)) + (PORT datad (104:104:104) (121:121:121)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux22\~0) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (439:439:439)) + (PORT datab (115:115:115) (143:143:143)) + (PORT datac (475:475:475) (537:537:537)) + (PORT datad (336:336:336) (391:391:391)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1027:1027:1027) (1206:1206:1206)) + (PORT datab (574:574:574) (686:686:686)) + (PORT datac (437:437:437) (537:537:537)) + (PORT datad (435:435:435) (532:532:532)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (455:455:455) (557:557:557)) + (PORT datac (1035:1035:1035) (1216:1216:1216)) + (PORT datad (561:561:561) (662:662:662)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (580:580:580)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (1034:1034:1034) (1216:1216:1216)) + (PORT datad (677:677:677) (792:792:792)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (725:725:725) (864:864:864)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (768:768:768) (886:886:886)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1027:1027:1027) (1205:1205:1205)) + (PORT datab (575:575:575) (686:686:686)) + (PORT datac (436:436:436) (537:537:537)) + (PORT datad (436:436:436) (532:532:532)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (495:495:495) (586:586:586)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (768:768:768) (885:885:885)) + (PORT datad (561:561:561) (662:662:662)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (148:148:148)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (672:672:672) (787:787:787)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datac (569:569:569) (673:673:673)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (897:897:897) (921:921:921)) + (PORT d (1029:1029:1029) (1142:1142:1142)) + (PORT ena (998:998:998) (1091:1091:1091)) + (IOPATH (posedge clk) q (329:329:329) (329:329:329)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (41:41:41)) + (SETUP ena (posedge clk) (41:41:41)) + (HOLD d (posedge clk) (56:56:56)) + (HOLD ena (posedge clk) (56:56:56)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux21\~1) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (439:439:439)) + (PORT datab (117:117:117) (146:146:146)) + (PORT datac (102:102:102) (123:123:123)) + (PORT datad (339:339:339) (395:395:395)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (921:921:921)) + (PORT d (863:863:863) (948:948:948)) + (PORT ena (873:873:873) (946:946:946)) + (IOPATH (posedge clk) q (329:329:329) (329:329:329)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (41:41:41)) + (SETUP ena (posedge clk) (41:41:41)) + (HOLD d (posedge clk) (56:56:56)) + (HOLD ena (posedge clk) (56:56:56)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~4) + (DELAY + (ABSOLUTE + (PORT dataa (425:425:425) (517:517:517)) + (PORT datab (430:430:430) (521:521:521)) + (PORT datad (149:149:149) (194:194:194)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~7) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (665:665:665)) + (PORT datab (1501:1501:1501) (1765:1765:1765)) + (PORT datac (963:963:963) (1143:1143:1143)) + (PORT datad (513:513:513) (599:599:599)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~7) + (DELAY + (ABSOLUTE + (PORT dataa (452:452:452) (556:556:556)) + (PORT datab (479:479:479) (561:561:561)) + (PORT datac (715:715:715) (855:855:855)) + (PORT datad (436:436:436) (506:506:506)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~8) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (684:684:684)) + (PORT datab (518:518:518) (601:601:601)) + (PORT datac (710:710:710) (839:839:839)) + (PORT datad (680:680:680) (795:795:795)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~10) + (DELAY + (ABSOLUTE + (PORT dataa (698:698:698) (827:827:827)) + (PORT datab (353:353:353) (423:423:423)) + (PORT datac (304:304:304) (347:347:347)) + (PORT datad (94:94:94) (114:114:114)) + (IOPATH dataa combout (181:181:181) (180:180:180)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~9) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (823:823:823)) + (PORT datab (357:357:357) (428:428:428)) + (PORT datac (302:302:302) (344:344:344)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (186:186:186) (179:179:179)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~11) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (280:280:280)) + (PORT datab (494:494:494) (580:580:580)) + (PORT datac (160:160:160) (193:193:193)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[4\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (926:926:926)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (354:354:354) (379:379:379)) + (PORT sload (893:893:893) (1021:1021:1021)) + (PORT ena (503:503:503) (534:534:534)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~12) + (DELAY + (ABSOLUTE + (PORT dataa (397:397:397) (483:483:483)) + (PORT datab (1165:1165:1165) (1369:1369:1369)) + (PORT datac (1285:1285:1285) (1515:1515:1515)) + (PORT datad (488:488:488) (560:560:560)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~5) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (361:361:361) (426:426:426)) + (PORT datac (896:896:896) (1047:1047:1047)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~6) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (387:387:387)) + (PORT datab (495:495:495) (580:580:580)) + (PORT datac (553:553:553) (660:660:660)) + (PORT datad (200:200:200) (253:253:253)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[4\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (824:824:824)) + (PORT datab (339:339:339) (400:400:400)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[4\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT datab (596:596:596) (709:709:709)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (104:104:104) (121:121:121)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (922:922:922)) + (PORT d (933:933:933) (1008:1008:1008)) + (PORT ena (1262:1262:1262) (1417:1417:1417)) + (IOPATH (posedge clk) q (329:329:329) (329:329:329)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (41:41:41)) + (SETUP ena (posedge clk) (41:41:41)) + (HOLD d (posedge clk) (56:56:56)) + (HOLD ena (posedge clk) (56:56:56)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~1) + (DELAY + (ABSOLUTE + (PORT dataa (427:427:427) (519:519:519)) + (PORT datab (430:430:430) (521:521:521)) + (PORT datac (351:351:351) (412:412:412)) + (PORT datad (148:148:148) (193:193:193)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~4) + (DELAY + (ABSOLUTE + (PORT dataa (696:696:696) (825:825:825)) + (PORT datac (303:303:303) (346:346:346)) + (PORT datad (316:316:316) (369:369:369)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~5) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (828:828:828)) + (PORT datab (584:584:584) (699:699:699)) + (PORT datac (711:711:711) (840:840:840)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~6) + (DELAY + (ABSOLUTE + (PORT dataa (698:698:698) (828:828:828)) + (PORT datab (584:584:584) (700:700:700)) + (PORT datac (711:711:711) (840:840:840)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~7) + (DELAY + (ABSOLUTE + (PORT dataa (770:770:770) (881:881:881)) + (PORT datab (213:213:213) (274:274:274)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[5\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (926:926:926)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (273:273:273) (295:295:295)) + (PORT sload (893:893:893) (1021:1021:1021)) + (PORT ena (503:503:503) (534:534:534)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~2) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (500:500:500) (582:582:582)) + (PORT datac (893:893:893) (1044:1044:1044)) + (PORT datad (352:352:352) (422:422:422)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~3) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (386:386:386)) + (PORT datab (587:587:587) (703:703:703)) + (PORT datac (755:755:755) (858:858:858)) + (PORT datad (201:201:201) (253:253:253)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[5\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (700:700:700) (830:830:830)) + (PORT datab (350:350:350) (411:411:411)) + (PORT datad (93:93:93) (110:110:110)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[5\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (134:134:134)) + (PORT datab (597:597:597) (710:710:710)) + (PORT datac (95:95:95) (119:119:119)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (920:920:920)) + (PORT d (788:788:788) (858:858:858)) + (PORT ena (1184:1184:1184) (1305:1305:1305)) + (IOPATH (posedge clk) q (329:329:329) (329:329:329)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (41:41:41)) + (SETUP ena (posedge clk) (41:41:41)) + (HOLD d (posedge clk) (56:56:56)) + (HOLD ena (posedge clk) (56:56:56)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux18\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1372:1372:1372) (1624:1624:1624)) + (PORT datac (699:699:699) (835:835:835)) + (PORT datad (361:361:361) (414:414:414)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (896:896:896) (921:921:921)) + (PORT d (852:852:852) (930:930:930)) + (PORT ena (873:873:873) (946:946:946)) + (IOPATH (posedge clk) q (329:329:329) (329:329:329)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (41:41:41)) + (SETUP ena (posedge clk) (41:41:41)) + (HOLD d (posedge clk) (56:56:56)) + (HOLD ena (posedge clk) (56:56:56)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1371:1371:1371) (1623:1623:1623)) + (PORT datac (834:834:834) (976:976:976)) + (PORT datad (361:361:361) (414:414:414)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (894:894:894) (918:918:918)) + (PORT d (1086:1086:1086) (1203:1203:1203)) + (PORT ena (903:903:903) (1016:1016:1016)) + (IOPATH (posedge clk) q (329:329:329) (329:329:329)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (41:41:41)) + (SETUP ena (posedge clk) (41:41:41)) + (HOLD d (posedge clk) (56:56:56)) + (HOLD ena (posedge clk) (56:56:56)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux16\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1377:1377:1377) (1630:1630:1630)) + (PORT datac (132:132:132) (175:175:175)) + (PORT datad (362:362:362) (414:414:414)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (908:908:908)) + (PORT d (1203:1203:1203) (1344:1344:1344)) + (PORT ena (761:761:761) (844:844:844)) + (IOPATH (posedge clk) q (345:345:345) (339:339:339)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (40:40:40)) + (SETUP ena (posedge clk) (40:40:40)) + (HOLD d (posedge clk) (58:58:58)) + (HOLD ena (posedge clk) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux15\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1380:1380:1380) (1633:1633:1633)) + (PORT datab (515:515:515) (618:618:618)) + (PORT datad (362:362:362) (415:415:415)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (890:890:890) (910:910:910)) + (PORT d (1210:1210:1210) (1359:1359:1359)) + (PORT ena (779:779:779) (872:872:872)) + (IOPATH (posedge clk) q (345:345:345) (339:339:339)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (40:40:40)) + (SETUP ena (posedge clk) (40:40:40)) + (HOLD d (posedge clk) (58:58:58)) + (HOLD ena (posedge clk) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (440:440:440)) + (PORT datab (391:391:391) (486:486:486)) + (PORT datac (700:700:700) (829:829:829)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~1) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (436:436:436)) + (PORT datab (213:213:213) (271:271:271)) + (PORT datac (584:584:584) (699:699:699)) + (PORT datad (335:335:335) (397:397:397)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[10\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (539:539:539) (641:641:641)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[10\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (925:925:925)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (271:271:271) (292:292:292)) + (PORT sload (872:872:872) (996:996:996)) + (PORT ena (663:663:663) (715:715:715)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~4) + (DELAY + (ABSOLUTE + (PORT dataa (473:473:473) (554:554:554)) + (PORT datab (212:212:212) (269:269:269)) + (PORT datac (370:370:370) (442:442:442)) + (PORT datad (364:364:364) (431:431:431)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~2) + (DELAY + (ABSOLUTE + (PORT dataa (375:375:375) (441:441:441)) + (PORT datab (391:391:391) (486:486:486)) + (PORT datac (701:701:701) (830:830:830)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~3) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (211:211:211) (268:268:268)) + (PORT datac (194:194:194) (232:232:232)) + (PORT datad (340:340:340) (403:403:403)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[10\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT datab (576:576:576) (686:686:686)) + (PORT datac (95:95:95) (119:119:119)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (902:902:902)) + (PORT d (804:804:804) (883:883:883)) + (PORT ena (891:891:891) (989:989:989)) + (IOPATH (posedge clk) q (345:345:345) (339:339:339)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (40:40:40)) + (SETUP ena (posedge clk) (40:40:40)) + (HOLD d (posedge clk) (58:58:58)) + (HOLD ena (posedge clk) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (411:411:411) (505:505:505)) + (PORT datac (710:710:710) (849:849:849)) + (PORT datad (397:397:397) (486:486:486)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (661:661:661)) + (PORT datab (115:115:115) (142:142:142)) + (PORT datac (123:123:123) (166:166:166)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (186:186:186) (179:179:179)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_2feeder) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (153:153:153)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_2) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (924:924:924)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (279:279:279) (304:304:304)) + (PORT sload (708:708:708) (811:811:811)) + (PORT ena (683:683:683) (755:755:755)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~10) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (PORT datac (435:435:435) (532:532:532)) + (PORT datad (384:384:384) (462:462:462)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~6) + (DELAY + (ABSOLUTE + (PORT dataa (448:448:448) (551:551:551)) + (PORT datab (476:476:476) (558:558:558)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (435:435:435) (504:504:504)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (151:151:151)) + (PORT datab (410:410:410) (502:502:502)) + (PORT datac (100:100:100) (128:128:128)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (891:891:891) (913:913:913)) + (PORT d (701:701:701) (770:770:770)) + (PORT ena (736:736:736) (803:803:803)) + (IOPATH (posedge clk) q (345:345:345) (339:339:339)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (40:40:40)) + (SETUP ena (posedge clk) (40:40:40)) + (HOLD d (posedge clk) (58:58:58)) + (HOLD ena (posedge clk) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_1SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (152:152:152)) + (PORT datab (410:410:410) (502:502:502)) + (PORT datac (101:101:101) (129:129:129)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (907:907:907)) + (PORT d (951:951:951) (1044:1044:1044)) + (PORT ena (909:909:909) (1008:1008:1008)) + (IOPATH (posedge clk) q (345:345:345) (339:339:339)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (40:40:40)) + (SETUP ena (posedge clk) (40:40:40)) + (HOLD d (posedge clk) (58:58:58)) + (HOLD ena (posedge clk) (58:58:58)) + ) + ) ) diff --git a/simulation/modelsim/spectrum_modelsim.xrf b/simulation/modelsim/spectrum_modelsim.xrf index a3e8bc9..ae6cb77 100644 --- a/simulation/modelsim/spectrum_modelsim.xrf +++ b/simulation/modelsim/spectrum_modelsim.xrf @@ -62,6 +62,9 @@ source_file = 1, /home/benny/work/fpga/spectrum/pll_video.v source_file = 1, /home/benny/work/fpga/spectrum/spectrum.sdc source_file = 1, /home/benny/work/fpga/spectrum/ram_video.qip source_file = 1, /home/benny/work/fpga/spectrum/ram_video.v +source_file = 1, /home/benny/work/fpga/spectrum/sdram.vhdl +source_file = 1, /home/benny/work/fpga/spectrum/sdram_clk_gen.qip +source_file = 1, /home/benny/work/fpga/spectrum/sdram_clk_gen.v source_file = 1, /home/benny/work/fpga/spectrum/db/spectrum.cbx.xml source_file = 1, /home/benny/work/fpga/spectrum/cpu/toplevel/globals.vh source_file = 1, /home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh @@ -99,6 +102,7 @@ source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/altpll. source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/stratix_pll.inc source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/stratixii_pll.inc source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/cycloneii_pll.inc +source_file = 1, /home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v source_file = 1, /home/benny/work/fpga/spectrum/db/pll_altpll.v design_name = spectrum instance = comp, \GPIO_1[0]~output , GPIO_1[0]~output, spectrum, 1 @@ -163,8 +167,47 @@ instance = comp, \GPIO_1[31]~output , GPIO_1[31]~output, spectrum, 1 instance = comp, \GPIO_1[32]~output , GPIO_1[32]~output, spectrum, 1 instance = comp, \GPIO_1[33]~output , GPIO_1[33]~output, spectrum, 1 instance = comp, \buzzer_out~output , buzzer_out~output, spectrum, 1 +instance = comp, \DRAM_BA[0]~output , DRAM_BA[0]~output, spectrum, 1 +instance = comp, \DRAM_BA[1]~output , DRAM_BA[1]~output, spectrum, 1 +instance = comp, \DRAM_DQM[0]~output , DRAM_DQM[0]~output, spectrum, 1 +instance = comp, \DRAM_DQM[1]~output , DRAM_DQM[1]~output, spectrum, 1 +instance = comp, \DRAM_RAS_N~output , DRAM_RAS_N~output, spectrum, 1 +instance = comp, \DRAM_CAS_N~output , DRAM_CAS_N~output, spectrum, 1 +instance = comp, \DRAM_CKE~output , DRAM_CKE~output, spectrum, 1 +instance = comp, \DRAM_CLK~output , DRAM_CLK~output, spectrum, 1 +instance = comp, \DRAM_WE_N~output , DRAM_WE_N~output, spectrum, 1 +instance = comp, \DRAM_CS_N~output , DRAM_CS_N~output, spectrum, 1 +instance = comp, \DRAM_ADDR[0]~output , DRAM_ADDR[0]~output, spectrum, 1 +instance = comp, \DRAM_ADDR[1]~output , DRAM_ADDR[1]~output, spectrum, 1 +instance = comp, \DRAM_ADDR[2]~output , DRAM_ADDR[2]~output, spectrum, 1 +instance = comp, \DRAM_ADDR[3]~output , DRAM_ADDR[3]~output, spectrum, 1 +instance = comp, \DRAM_ADDR[4]~output , DRAM_ADDR[4]~output, spectrum, 1 +instance = comp, \DRAM_ADDR[5]~output , DRAM_ADDR[5]~output, spectrum, 1 +instance = comp, \DRAM_ADDR[6]~output , DRAM_ADDR[6]~output, spectrum, 1 +instance = comp, \DRAM_ADDR[7]~output , DRAM_ADDR[7]~output, spectrum, 1 +instance = comp, \DRAM_ADDR[8]~output , DRAM_ADDR[8]~output, spectrum, 1 +instance = comp, \DRAM_ADDR[9]~output , DRAM_ADDR[9]~output, spectrum, 1 +instance = comp, \DRAM_ADDR[10]~output , DRAM_ADDR[10]~output, spectrum, 1 +instance = comp, \DRAM_ADDR[11]~output , DRAM_ADDR[11]~output, spectrum, 1 +instance = comp, \DRAM_ADDR[12]~output , DRAM_ADDR[12]~output, spectrum, 1 instance = comp, \I2C_SCLK~output , I2C_SCLK~output, spectrum, 1 instance = comp, \I2C_SDAT~output , I2C_SDAT~output, spectrum, 1 +instance = comp, \DRAM_DQ[0]~output , DRAM_DQ[0]~output, spectrum, 1 +instance = comp, \DRAM_DQ[1]~output , DRAM_DQ[1]~output, spectrum, 1 +instance = comp, \DRAM_DQ[2]~output , DRAM_DQ[2]~output, spectrum, 1 +instance = comp, \DRAM_DQ[3]~output , DRAM_DQ[3]~output, spectrum, 1 +instance = comp, \DRAM_DQ[4]~output , DRAM_DQ[4]~output, spectrum, 1 +instance = comp, \DRAM_DQ[5]~output , DRAM_DQ[5]~output, spectrum, 1 +instance = comp, \DRAM_DQ[6]~output , DRAM_DQ[6]~output, spectrum, 1 +instance = comp, \DRAM_DQ[7]~output , DRAM_DQ[7]~output, spectrum, 1 +instance = comp, \DRAM_DQ[8]~output , DRAM_DQ[8]~output, spectrum, 1 +instance = comp, \DRAM_DQ[9]~output , DRAM_DQ[9]~output, spectrum, 1 +instance = comp, \DRAM_DQ[10]~output , DRAM_DQ[10]~output, spectrum, 1 +instance = comp, \DRAM_DQ[11]~output , DRAM_DQ[11]~output, spectrum, 1 +instance = comp, \DRAM_DQ[12]~output , DRAM_DQ[12]~output, spectrum, 1 +instance = comp, \DRAM_DQ[13]~output , DRAM_DQ[13]~output, spectrum, 1 +instance = comp, \DRAM_DQ[14]~output , DRAM_DQ[14]~output, spectrum, 1 +instance = comp, \DRAM_DQ[15]~output , DRAM_DQ[15]~output, spectrum, 1 instance = comp, \CLOCK_50~input , CLOCK_50~input, spectrum, 1 instance = comp, \ula_|pll_|altpll_component|auto_generated|pll1 , ula_|pll_|altpll_component|auto_generated|pll1, spectrum, 1 instance = comp, \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl , ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl, spectrum, 1 @@ -174,804 +217,21 @@ instance = comp, \SW[2]~input , SW[2]~input, spectrum, 1 instance = comp, \ula_|clocks_|clk_cpu~0 , ula_|clocks_|clk_cpu~0, spectrum, 1 instance = comp, \ula_|clocks_|clk_cpu , ula_|clocks_|clk_cpu, spectrum, 1 instance = comp, \ula_|clocks_|clk_cpu~clkctrl , ula_|clocks_|clk_cpu~clkctrl, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_M1_ff~0 , z80_|sequencer_|DFFE_M1_ff~0, spectrum, 1 -instance = comp, \z80_|sequencer_|ena_M , z80_|sequencer_|ena_M, spectrum, 1 instance = comp, \KEY[1]~input , KEY[1]~input, spectrum, 1 instance = comp, \z80_|interrupts_|nmi_armed~feeder , z80_|interrupts_|nmi_armed~feeder, spectrum, 1 -instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_9 , z80_|interrupts_|SYNTHESIZED_WIRE_9, spectrum, 1 -instance = comp, \z80_|interrupts_|nmi_armed , z80_|interrupts_|nmi_armed, spectrum, 1 -instance = comp, \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder , z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder, spectrum, 1 -instance = comp, \z80_|execute_|ctl_eval_cond~0 , z80_|execute_|ctl_eval_cond~0, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~4 , z80_|execute_|ixy_d~4, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_M3_ff~0 , z80_|sequencer_|DFFE_M3_ff~0, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_M3_ff , z80_|sequencer_|DFFE_M3_ff, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~1 , z80_|execute_|fIOWrite~1, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_M4_ff~0 , z80_|sequencer_|DFFE_M4_ff~0, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_M4_ff , z80_|sequencer_|DFFE_M4_ff, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal32~0 , z80_|pla_decode_|Equal32~0, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_11 , z80_|resets_|SYNTHESIZED_WIRE_11, spectrum, 1 -instance = comp, \z80_|decode_state_|table_xx~0 , z80_|decode_state_|table_xx~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal1~7 , z80_|pla_decode_|Equal1~7, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal2~0 , z80_|pla_decode_|Equal2~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal36~0 , z80_|pla_decode_|Equal36~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_tbl_cb_set , z80_|execute_|ctl_state_tbl_cb_set, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_tbl_we~8 , z80_|execute_|ctl_state_tbl_we~8, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instCB , z80_|decode_state_|DFFE_instCB, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal52~0 , z80_|pla_decode_|Equal52~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal2~1 , z80_|pla_decode_|Equal2~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_tbl_ed_set , z80_|execute_|ctl_state_tbl_ed_set, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instED , z80_|decode_state_|DFFE_instED, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal13~0 , z80_|pla_decode_|Equal13~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal33~0 , z80_|pla_decode_|Equal33~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_im_we , z80_|execute_|ctl_im_we, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal49~0 , z80_|pla_decode_|Equal49~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal33~1 , z80_|pla_decode_|Equal33~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal6~0 , z80_|pla_decode_|Equal6~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~14 , z80_|execute_|ctl_mRead~14, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal12~0 , z80_|pla_decode_|Equal12~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~8 , z80_|execute_|ctl_sw_1d~8, spectrum, 1 -instance = comp, \z80_|nM1_int~2 , z80_|nM1_int~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~5 , z80_|execute_|ctl_sw_1d~5, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal3~0 , z80_|pla_decode_|Equal3~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~4 , z80_|execute_|ctl_mRead~4, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~7 , z80_|execute_|ixy_d~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~4 , z80_|execute_|ctl_state_alu~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~4 , z80_|execute_|ctl_sw_1d~4, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal40~1 , z80_|pla_decode_|Equal40~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal39~0 , z80_|pla_decode_|Equal39~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~1 , z80_|execute_|ctl_bus_db_oe~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal13~1 , z80_|pla_decode_|Equal13~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal13~2 , z80_|pla_decode_|Equal13~2, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal3~2 , z80_|pla_decode_|Equal3~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_iy_set~2 , z80_|execute_|ctl_state_iy_set~2, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~8 , z80_|execute_|ixy_d~8, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~6 , z80_|execute_|ixy_d~6, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~9 , z80_|execute_|ixy_d~9, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~12 , z80_|execute_|ixy_d~12, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~10 , z80_|execute_|ixy_d~10, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal44~0 , z80_|pla_decode_|Equal44~0, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~16 , z80_|execute_|ixy_d~16, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~13 , z80_|execute_|ixy_d~13, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal50~0 , z80_|pla_decode_|Equal50~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal33~2 , z80_|pla_decode_|Equal33~2, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~17 , z80_|execute_|ixy_d~17, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~5 , z80_|execute_|ixy_d~5, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~14 , z80_|execute_|ixy_d~14, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~11 , z80_|execute_|ixy_d~11, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~15 , z80_|execute_|ixy_d~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_ixiy_we~2 , z80_|execute_|ctl_state_ixiy_we~2, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instIY1 , z80_|decode_state_|DFFE_instIY1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~5 , z80_|execute_|ctl_ir_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~14 , z80_|execute_|ctl_ir_we~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~2 , z80_|execute_|ctl_mWrite~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~16 , z80_|execute_|ctl_mWrite~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~18 , z80_|execute_|ctl_flags_alu~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~26 , z80_|execute_|ctl_mRead~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~27 , z80_|execute_|ctl_mRead~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~7 , z80_|execute_|ctl_bus_db_oe~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~5 , z80_|execute_|ctl_sw_2d~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~18 , z80_|execute_|ctl_mRead~18, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal55~0 , z80_|pla_decode_|Equal55~0, spectrum, 1 -instance = comp, \z80_|execute_|comb~1 , z80_|execute_|comb~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~15 , z80_|execute_|ctl_mRead~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~17 , z80_|execute_|ctl_mRead~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~5 , z80_|execute_|ctl_reg_in_hi~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~9 , z80_|execute_|ctl_mRead~9, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal9~0 , z80_|pla_decode_|Equal9~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~10 , z80_|execute_|ctl_mRead~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~8 , z80_|execute_|ctl_mRead~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~20 , z80_|execute_|ctl_mRead~20, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal12~1 , z80_|pla_decode_|Equal12~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal9~1 , z80_|pla_decode_|Equal9~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal25~0 , z80_|pla_decode_|Equal25~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~21 , z80_|execute_|ctl_mRead~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~6 , z80_|execute_|ctl_state_alu~6, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal19~0 , z80_|pla_decode_|Equal19~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal1~4 , z80_|pla_decode_|Equal1~4, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal29~0 , z80_|pla_decode_|Equal29~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal24~1 , z80_|pla_decode_|Equal24~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal34~0 , z80_|pla_decode_|Equal34~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal37~0 , z80_|pla_decode_|Equal37~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal35~0 , z80_|pla_decode_|Equal35~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal38~2 , z80_|pla_decode_|Equal38~2, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~2 , z80_|reg_control_|reg_sys_we_lo~2, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~3 , z80_|reg_control_|reg_sys_we_lo~3, spectrum, 1 -instance = comp, \z80_|execute_|comb~0 , z80_|execute_|comb~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal47~0 , z80_|pla_decode_|Equal47~0, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~4 , z80_|reg_control_|reg_sys_we_lo~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~22 , z80_|execute_|ctl_mRead~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~24 , z80_|execute_|ctl_mRead~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 , z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~6 , z80_|execute_|ctl_reg_in_hi~6, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal6~1 , z80_|pla_decode_|Equal6~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~16 , z80_|execute_|ctl_mRead~16, spectrum, 1 -instance = comp, \z80_|sequencer_|M5~0 , z80_|sequencer_|M5~0, spectrum, 1 -instance = comp, \z80_|sequencer_|M5 , z80_|sequencer_|M5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~2 , z80_|execute_|ctl_reg_in_hi~2, spectrum, 1 -instance = comp, \z80_|execute_|setM1~29 , z80_|execute_|setM1~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~25 , z80_|execute_|ctl_mRead~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~6 , z80_|execute_|ctl_reg_gp_sel[0]~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~7 , z80_|execute_|ctl_ir_we~7, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal52~1 , z80_|pla_decode_|Equal52~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~14 , z80_|execute_|ctl_state_alu~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~8 , z80_|execute_|ctl_state_alu~8, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal24~0 , z80_|pla_decode_|Equal24~0, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_pc~0 , z80_|reg_control_|reg_sel_pc~0, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_pc~1 , z80_|reg_control_|reg_sel_pc~1, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_pc~2 , z80_|reg_control_|reg_sel_pc~2, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~17 , z80_|execute_|fMRead~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~6 , z80_|execute_|ctl_mRead~6, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal11~0 , z80_|pla_decode_|Equal11~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal10~0 , z80_|pla_decode_|Equal10~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~9 , z80_|execute_|ctl_alu_op2_sel_bus~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~4 , z80_|execute_|ctl_sw_2d~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~15 , z80_|execute_|ctl_ir_we~15, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~16 , z80_|execute_|fMRead~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~9 , z80_|execute_|ctl_ir_we~9, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal46~0 , z80_|pla_decode_|Equal46~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~10 , z80_|execute_|ctl_ir_we~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~17 , z80_|execute_|ctl_flags_alu~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~6 , z80_|execute_|ctl_flags_alu~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~6 , z80_|execute_|ctl_ir_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~8 , z80_|execute_|ctl_ir_we~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~16 , z80_|execute_|ctl_flags_alu~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~3 , z80_|execute_|ctl_reg_in_hi~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~8 , z80_|execute_|ctl_mWrite~8, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~18 , z80_|execute_|fMRead~18, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~19 , z80_|execute_|fMRead~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~16 , z80_|execute_|ctl_alu_shift_oe~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~36 , z80_|execute_|ctl_mRead~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~9 , z80_|execute_|ctl_alu_op_low~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~44 , z80_|execute_|ctl_alu_shift_oe~44, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~11 , z80_|execute_|ctl_mRead~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~6 , z80_|execute_|ctl_sw_2d~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~7 , z80_|execute_|ctl_sw_2d~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~7 , z80_|execute_|ctl_mWrite~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~11 , z80_|execute_|ctl_ir_we~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~12 , z80_|execute_|ctl_ir_we~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~0 , z80_|execute_|ctl_flags_sz_we~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 , z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~8 , z80_|execute_|ctl_sw_2d~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~9 , z80_|execute_|ctl_sw_2d~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~6 , z80_|execute_|ctl_sw_1d~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~7 , z80_|execute_|ctl_sw_1d~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~8 , z80_|execute_|ctl_alu_op_low~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 , z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 , z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~39 , z80_|execute_|ctl_reg_gp_hilo[1]~39, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 , z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_hi~4 , z80_|execute_|ctl_reg_out_hi~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~15 , z80_|execute_|ctl_alu_shift_oe~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~38 , z80_|execute_|ctl_alu_shift_oe~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_zero , z80_|execute_|ctl_alu_op2_sel_zero, spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~4 , z80_|alu_|db_low[2]~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~14 , z80_|execute_|ctl_alu_shift_oe~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~11 , z80_|execute_|ctl_reg_sys_hilo[0]~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~1 , z80_|execute_|ctl_sw_4u~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~5 , z80_|execute_|ctl_alu_sel_op2_neg~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~30 , z80_|execute_|ctl_alu_shift_oe~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~29 , z80_|execute_|ctl_alu_shift_oe~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~31 , z80_|execute_|ctl_alu_shift_oe~31, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal69~0 , z80_|pla_decode_|Equal69~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal1~5 , z80_|pla_decode_|Equal1~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~14 , z80_|execute_|ctl_alu_op_low~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~12 , z80_|execute_|ctl_alu_op_low~12, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal56~0 , z80_|pla_decode_|Equal56~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~11 , z80_|execute_|ctl_alu_op_low~11, spectrum, 1 -instance = comp, \z80_|execute_|nextM~2 , z80_|execute_|nextM~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~16 , z80_|execute_|ctl_alu_op1_sel_bus~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~4 , z80_|execute_|ctl_alu_op1_sel_bus~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~5 , z80_|execute_|ctl_alu_op1_sel_bus~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~3 , z80_|execute_|ctl_alu_oe~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~15 , z80_|execute_|ctl_alu_op_low~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~8 , z80_|execute_|ctl_alu_op1_sel_bus~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~9 , z80_|execute_|ctl_alu_op1_sel_bus~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~3 , z80_|execute_|ctl_alu_core_R~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~4 , z80_|execute_|ctl_alu_core_R~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 , z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~10 , z80_|execute_|ctl_alu_op1_sel_bus~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~11 , z80_|execute_|ctl_alu_op1_sel_bus~11, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal48~0 , z80_|pla_decode_|Equal48~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf2_we , z80_|execute_|ctl_flags_hf2_we, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~41 , z80_|execute_|ctl_alu_shift_oe~41, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~18 , z80_|execute_|ctl_flags_xy_we~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~17 , z80_|execute_|ctl_alu_shift_oe~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~19 , z80_|execute_|ctl_alu_shift_oe~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_iorw~10 , z80_|execute_|ctl_iorw~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~18 , z80_|execute_|ctl_alu_shift_oe~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~20 , z80_|execute_|ctl_alu_shift_oe~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~13 , z80_|execute_|ctl_alu_bs_oe~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~9 , z80_|execute_|ctl_alu_bs_oe~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~3 , z80_|execute_|ctl_bus_db_oe~3, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal20~0 , z80_|pla_decode_|Equal20~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal68~2 , z80_|pla_decode_|Equal68~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~14 , z80_|execute_|ctl_flags_bus~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~13 , z80_|execute_|ctl_alu_op_low~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~15 , z80_|execute_|ctl_flags_bus~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~11 , z80_|execute_|ctl_flags_bus~11, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~11 , z80_|alu_flags_|DFFE_inst_latch_nf~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~10 , z80_|execute_|ctl_flags_bus~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~8 , z80_|execute_|ctl_flags_bus~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~9 , z80_|execute_|ctl_flags_bus~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~12 , z80_|execute_|ctl_flags_bus~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~11 , z80_|execute_|ctl_flags_xy_we~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~12 , z80_|execute_|ctl_flags_xy_we~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~6 , z80_|execute_|ctl_alu_op1_sel_bus~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~7 , z80_|execute_|ctl_alu_op1_sel_bus~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~4 , z80_|execute_|ctl_ir_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~8 , z80_|execute_|ctl_alu_bs_oe~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~0 , z80_|execute_|ctl_bus_db_oe~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~12 , z80_|execute_|ctl_alu_op1_sel_bus~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~13 , z80_|execute_|ctl_alu_op1_sel_bus~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~14 , z80_|execute_|ctl_alu_op1_sel_bus~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~15 , z80_|execute_|ctl_alu_op1_sel_bus~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_66_oe~2 , z80_|execute_|ctl_66_oe~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel_pla11M1T1_11 , z80_|execute_|ctl_pf_sel_pla11M1T1_11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero~5 , z80_|execute_|ctl_alu_op1_sel_zero~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero~4 , z80_|execute_|ctl_alu_op1_sel_zero~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero , z80_|execute_|ctl_alu_op1_sel_zero, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[2] , z80_|alu_|b2v_op1_latch_mux_high|Q[2], spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|ena~0 , z80_|alu_|b2v_op1_latch_mux_high|ena~0, spectrum, 1 -instance = comp, \z80_|alu_|op1_high[2] , z80_|alu_|op1_high[2], spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_lq , z80_|execute_|ctl_alu_op2_sel_lq, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~10 , z80_|execute_|ctl_alu_op_low~10, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~11 , z80_|execute_|fMWrite~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~21 , z80_|execute_|ctl_alu_op_low~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~22 , z80_|execute_|ctl_alu_op_low~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~16 , z80_|execute_|ctl_alu_op_low~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~17 , z80_|execute_|ctl_alu_op_low~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 , z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel~36 , z80_|execute_|ctl_reg_gp_sel~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~4 , z80_|execute_|ctl_alu_op2_sel_bus~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~5 , z80_|execute_|ctl_state_alu~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~18 , z80_|execute_|ctl_alu_op_low~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~19 , z80_|execute_|ctl_alu_op_low~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~33 , z80_|execute_|ctl_alu_op_low~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~20 , z80_|execute_|ctl_alu_op_low~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~23 , z80_|execute_|ctl_alu_op_low~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~24 , z80_|execute_|ctl_alu_op_low~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~25 , z80_|execute_|ctl_alu_op_low~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~34 , z80_|execute_|ctl_alu_op_low~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low , z80_|execute_|ctl_alu_op_low, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~40 , z80_|execute_|ctl_alu_shift_oe~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~37 , z80_|execute_|ctl_alu_shift_oe~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~39 , z80_|execute_|ctl_alu_shift_oe~39, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~46 , z80_|execute_|ctl_alu_shift_oe~46, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~42 , z80_|execute_|ctl_alu_shift_oe~42, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~21 , z80_|execute_|ctl_alu_shift_oe~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~45 , z80_|execute_|ctl_alu_shift_oe~45, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~22 , z80_|execute_|ctl_alu_shift_oe~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~23 , z80_|execute_|ctl_alu_shift_oe~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~24 , z80_|execute_|ctl_alu_shift_oe~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~25 , z80_|execute_|ctl_alu_shift_oe~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~14 , z80_|execute_|ctl_alu_bs_oe~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~26 , z80_|execute_|ctl_alu_shift_oe~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~27 , z80_|execute_|ctl_alu_shift_oe~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~28 , z80_|execute_|ctl_alu_shift_oe~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~10 , z80_|execute_|ctl_alu_bs_oe~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~11 , z80_|execute_|ctl_alu_bs_oe~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~32 , z80_|execute_|ctl_alu_shift_oe~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~33 , z80_|execute_|ctl_alu_shift_oe~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~0 , z80_|execute_|ctl_reg_use_sp~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~1 , z80_|execute_|ctl_reg_use_sp~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~12 , z80_|execute_|ctl_alu_bs_oe~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~47 , z80_|execute_|ctl_alu_shift_oe~47, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~34 , z80_|execute_|ctl_alu_shift_oe~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~35 , z80_|execute_|ctl_alu_shift_oe~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~36 , z80_|execute_|ctl_alu_shift_oe~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~43 , z80_|execute_|ctl_alu_shift_oe~43, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_lo~9 , z80_|execute_|ctl_reg_in_lo~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_oe~0 , z80_|execute_|ctl_alu_op1_oe~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 , z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_oe~1 , z80_|execute_|ctl_alu_op1_oe~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~8 , z80_|execute_|ctl_flags_xy_we~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~9 , z80_|execute_|ctl_flags_xy_we~9, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal8~0 , z80_|pla_decode_|Equal8~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~9 , z80_|execute_|ctl_flags_alu~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~4 , z80_|execute_|ctl_alu_sel_op2_neg~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~3 , z80_|execute_|ctl_flags_sz_we~3, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal11~1 , z80_|pla_decode_|Equal11~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 , z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~10 , z80_|execute_|ctl_flags_alu~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~11 , z80_|execute_|ctl_flags_alu~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 , z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel_pla82M1T1_16 , z80_|execute_|ctl_pf_sel_pla82M1T1_16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~13 , z80_|execute_|ctl_flags_use_cf2~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_we~7 , z80_|execute_|ctl_flags_cf_we~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel[0]~2 , z80_|execute_|ctl_pf_sel[0]~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~2 , z80_|execute_|ctl_alu_oe~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~25 , z80_|execute_|ctl_bus_inc_oe~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_we~5 , z80_|execute_|ctl_flags_hf_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~10 , z80_|execute_|ctl_flags_pf_we~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~48 , z80_|execute_|ctl_reg_gp_hilo[1]~48, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~2 , z80_|execute_|ctl_flags_pf_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~3 , z80_|execute_|ctl_flags_pf_we~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~17 , z80_|execute_|ctl_flags_xy_we~17, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~5 , z80_|reg_control_|reg_sys_we_lo~5, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~6 , z80_|reg_control_|reg_sys_we_lo~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~10 , z80_|execute_|ctl_flags_xy_we~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 , z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~7 , z80_|execute_|ctl_state_alu~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~1 , z80_|execute_|ctl_flags_sz_we~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_we~2 , z80_|execute_|ctl_flags_cf_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~6 , z80_|execute_|ctl_alu_core_S~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~7 , z80_|execute_|ctl_alu_core_S~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~4 , z80_|execute_|ctl_alu_core_S~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~5 , z80_|execute_|ctl_alu_core_S~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 , z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_res_oe~0 , z80_|execute_|ctl_alu_res_oe~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~15 , z80_|execute_|ctl_alu_oe~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_res_oe~1 , z80_|execute_|ctl_alu_res_oe~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_res_oe~2 , z80_|execute_|ctl_alu_res_oe~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_oe~0 , z80_|execute_|ctl_alu_op2_oe~0, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~2 , z80_|alu_|db_high[3]~2, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~3 , z80_|alu_|db_high[3]~3, spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~24 , z80_|alu_|db_low[2]~24, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~7 , z80_|reg_control_|reg_sys_we_lo~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 , z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~19 , z80_|execute_|ctl_reg_gp_hilo[1]~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~8 , z80_|execute_|ctl_reg_in_hi~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~8 , z80_|execute_|ctl_alu_oe~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~4 , z80_|execute_|ctl_alu_oe~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~9 , z80_|execute_|ctl_mWrite~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~10 , z80_|execute_|ctl_alu_core_S~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~43 , z80_|execute_|ctl_bus_inc_oe~43, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~26 , z80_|execute_|ctl_bus_inc_oe~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~5 , z80_|execute_|ctl_bus_db_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~9 , z80_|execute_|ctl_alu_oe~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~11 , z80_|execute_|ctl_alu_oe~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~5 , z80_|execute_|ctl_alu_oe~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~11 , z80_|execute_|ctl_alu_core_S~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~6 , z80_|execute_|ctl_alu_oe~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~7 , z80_|execute_|ctl_alu_oe~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~12 , z80_|execute_|ctl_alu_oe~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~13 , z80_|execute_|ctl_alu_oe~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~14 , z80_|execute_|ctl_alu_oe~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~24 , z80_|execute_|ctl_reg_gp_sel[0]~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~27 , z80_|execute_|ctl_reg_gp_sel[0]~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~40 , z80_|execute_|ctl_reg_gp_hilo[1]~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~53 , z80_|execute_|ctl_reg_gp_hilo[1]~53, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_hi~8 , z80_|execute_|ctl_reg_out_hi~8, spectrum, 1 -instance = comp, \z80_|execute_|setM1~54 , z80_|execute_|setM1~54, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~1 , z80_|execute_|ctl_sw_2u~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~4 , z80_|execute_|ctl_sw_2u~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~5 , z80_|execute_|ctl_sw_2u~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~6 , z80_|execute_|ctl_sw_2u~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~35 , z80_|execute_|ctl_inc_cy~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~35 , z80_|execute_|ctl_reg_sys_hilo[1]~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~6 , z80_|execute_|ctl_mWrite~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~2 , z80_|execute_|ctl_sw_2u~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~0 , z80_|execute_|ctl_sw_2u~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~3 , z80_|execute_|ctl_sw_2u~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~52 , z80_|execute_|ctl_reg_gp_hilo[1]~52, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 , z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~2 , z80_|execute_|ctl_reg_out_lo~2, spectrum, 1 -instance = comp, \z80_|execute_|rsel3 , z80_|execute_|rsel3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_hi~5 , z80_|execute_|ctl_reg_out_hi~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_hi~6 , z80_|execute_|ctl_reg_out_hi~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_hi~7 , z80_|execute_|ctl_reg_out_hi~7, spectrum, 1 -instance = comp, \z80_|execute_|rsel0 , z80_|execute_|rsel0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 , z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~33 , z80_|execute_|ctl_reg_gp_hilo[0]~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~6 , z80_|execute_|ctl_reg_out_lo~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~7 , z80_|execute_|ctl_reg_out_lo~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_iorw~11 , z80_|execute_|ctl_iorw~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~10 , z80_|execute_|ctl_sw_2d~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~14 , z80_|execute_|ctl_sw_2d~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~11 , z80_|execute_|ctl_sw_2d~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~12 , z80_|execute_|ctl_sw_2d~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~13 , z80_|execute_|ctl_sw_2d~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_66_oe , z80_|execute_|ctl_66_oe, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~34 , z80_|execute_|ctl_inc_cy~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_apin_mux~0 , z80_|execute_|ctl_apin_mux~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~5 , z80_|execute_|ctl_sw_4u~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~75 , z80_|execute_|ctl_inc_cy~75, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~76 , z80_|execute_|ctl_inc_cy~76, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal4~0 , z80_|pla_decode_|Equal4~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~48 , z80_|execute_|ctl_bus_inc_oe~48, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~46 , z80_|execute_|ctl_bus_inc_oe~46, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~53 , z80_|execute_|ctl_inc_cy~53, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~92 , z80_|execute_|ctl_inc_cy~92, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal19~1 , z80_|pla_decode_|Equal19~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~0 , z80_|execute_|ctl_sw_4u~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~38 , z80_|execute_|ctl_inc_cy~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~93 , z80_|execute_|ctl_inc_cy~93, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~39 , z80_|execute_|ctl_inc_cy~39, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~24 , z80_|execute_|ctl_bus_inc_oe~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~1 , z80_|execute_|ctl_reg_gp_we~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 , z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~44 , z80_|execute_|ctl_bus_inc_oe~44, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~5 , z80_|execute_|ctl_reg_gp_sel[1]~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~0 , z80_|execute_|ctl_reg_gp_we~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 , z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~35 , z80_|execute_|ctl_reg_gp_hilo[1]~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~2 , z80_|execute_|ctl_sw_4u~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~3 , z80_|execute_|ctl_sw_4u~3, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~3 , z80_|execute_|fMRead~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~4 , z80_|execute_|ctl_sw_4u~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 , z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~15 , z80_|execute_|ctl_reg_sel_wz~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~8 , z80_|execute_|ctl_reg_sys_hilo[1]~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~94 , z80_|execute_|ctl_inc_cy~94, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~87 , z80_|execute_|ctl_inc_cy~87, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~42 , z80_|execute_|ctl_inc_cy~42, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~34 , z80_|execute_|ctl_reg_sys_hilo[1]~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~16 , z80_|execute_|ctl_reg_sel_wz~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~6 , z80_|execute_|ctl_sw_4u~6, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal2~2 , z80_|pla_decode_|Equal2~2, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal1~6 , z80_|pla_decode_|Equal1~6, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_exx~2 , z80_|reg_control_|bank_exx~2, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_exx , z80_|reg_control_|bank_exx, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_hl_de1~0 , z80_|reg_control_|bank_hl_de1~0, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_hl_de1 , z80_|reg_control_|bank_hl_de1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~10 , z80_|execute_|ctl_reg_gp_sel[1]~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~11 , z80_|execute_|ctl_reg_gp_sel[1]~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~12 , z80_|execute_|ctl_reg_gp_sel[1]~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~7 , z80_|execute_|ctl_mRead~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~9 , z80_|execute_|ctl_reg_gp_sel[1]~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~37 , z80_|execute_|ctl_reg_gp_sel[1]~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~13 , z80_|execute_|ctl_reg_gp_sel[1]~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~47 , z80_|execute_|ctl_reg_gp_hilo[1]~47, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~3 , z80_|execute_|fMWrite~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~5 , z80_|execute_|ctl_flags_bus~5, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~2 , z80_|execute_|fMRead~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~19 , z80_|execute_|ctl_mRead~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~7 , z80_|execute_|ctl_reg_gp_sel[1]~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~8 , z80_|execute_|ctl_reg_gp_sel[1]~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~14 , z80_|execute_|ctl_reg_gp_sel[1]~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~16 , z80_|execute_|ctl_reg_gp_sel[1]~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~15 , z80_|execute_|ctl_reg_gp_sel[1]~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~17 , z80_|execute_|ctl_reg_gp_sel[1]~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~19 , z80_|execute_|ctl_reg_gp_sel[1]~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~2 , z80_|execute_|ctl_reg_use_sp~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~47 , z80_|execute_|ctl_bus_inc_oe~47, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~3 , z80_|execute_|ctl_reg_use_sp~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~9 , z80_|execute_|ctl_sw_1d~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~21 , z80_|execute_|ctl_reg_gp_sel[0]~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~20 , z80_|execute_|ctl_reg_gp_hilo[1]~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~20 , z80_|execute_|ctl_reg_gp_sel[0]~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~49 , z80_|execute_|ctl_reg_gp_hilo[1]~49, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~22 , z80_|execute_|ctl_reg_gp_sel[0]~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~18 , z80_|execute_|ctl_reg_gp_sel[1]~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~23 , z80_|execute_|ctl_reg_gp_sel[1]~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~28 , z80_|execute_|ctl_reg_gp_sel[0]~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~23 , z80_|execute_|ctl_reg_gp_hilo[1]~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~2 , z80_|execute_|ctl_flags_cf2_sel_shift~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_cpl~14 , z80_|execute_|ctl_flags_hf_cpl~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_cpl~10 , z80_|execute_|ctl_flags_hf_cpl~10, spectrum, 1 -instance = comp, \z80_|execute_|setM1~47 , z80_|execute_|setM1~47, spectrum, 1 -instance = comp, \z80_|execute_|setM1~48 , z80_|execute_|setM1~48, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~13 , z80_|execute_|ctl_al_we~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_oe~0 , z80_|execute_|ctl_flags_oe~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_oe~1 , z80_|execute_|ctl_flags_oe~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~13 , z80_|execute_|ctl_reg_in_hi~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~29 , z80_|execute_|ctl_reg_gp_sel[0]~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~40 , z80_|execute_|ctl_inc_cy~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~2 , z80_|execute_|ctl_inc_dec~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~12 , z80_|execute_|ctl_inc_dec~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~43 , z80_|execute_|ctl_inc_cy~43, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~5 , z80_|execute_|ctl_inc_dec~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~4 , z80_|execute_|ctl_reg_gp_sel[1]~4, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~6 , z80_|execute_|fMRead~6, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~7 , z80_|execute_|fMRead~7, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~8 , z80_|execute_|fMRead~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~26 , z80_|execute_|ctl_reg_gp_sel[1]~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~13 , z80_|execute_|ctl_state_alu~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~10 , z80_|execute_|ctl_state_alu~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~11 , z80_|execute_|ctl_state_alu~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~9 , z80_|execute_|ctl_state_alu~9, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal62~2 , z80_|pla_decode_|Equal62~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~4 , z80_|execute_|ctl_flags_pf_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~21 , z80_|execute_|ctl_reg_gp_hilo[1]~21, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal64~0 , z80_|pla_decode_|Equal64~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel[0]~3 , z80_|execute_|ctl_pf_sel[0]~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~22 , z80_|execute_|ctl_reg_gp_hilo[1]~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~15 , z80_|execute_|ctl_state_alu~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 , z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~25 , z80_|execute_|ctl_reg_gp_sel[0]~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~30 , z80_|execute_|ctl_reg_gp_sel[0]~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~31 , z80_|execute_|ctl_reg_gp_sel[1]~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~33 , z80_|execute_|ctl_reg_gp_sel[0]~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~34 , z80_|execute_|ctl_reg_gp_sel[0]~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo~20 , z80_|execute_|ctl_reg_sys_hilo~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~32 , z80_|execute_|ctl_reg_gp_sel[0]~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~35 , z80_|execute_|ctl_reg_gp_sel[0]~35, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_de2~5 , z80_|reg_control_|reg_sel_de2~5, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_de2~6 , z80_|reg_control_|reg_sel_de2~6, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_hl~0 , z80_|reg_control_|reg_sel_hl~0, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_hl_de2~0 , z80_|reg_control_|bank_hl_de2~0, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_hl_de2 , z80_|reg_control_|bank_hl_de2, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_hl2~0 , z80_|reg_control_|reg_sel_hl2~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~7 , z80_|execute_|ctl_reg_in_hi~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~4 , z80_|execute_|ctl_reg_gp_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 , z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~3 , z80_|execute_|ctl_reg_gp_we~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~13 , z80_|execute_|ctl_alu_sel_op2_neg~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 , z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~2 , z80_|execute_|ctl_reg_gp_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~5 , z80_|execute_|ctl_reg_gp_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~6 , z80_|execute_|ctl_reg_gp_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~14 , z80_|execute_|ctl_al_we~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~50 , z80_|execute_|ctl_reg_gp_hilo[0]~50, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~26 , z80_|execute_|ctl_reg_gp_hilo[0]~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~27 , z80_|execute_|ctl_reg_gp_hilo[0]~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~28 , z80_|execute_|ctl_reg_gp_hilo[0]~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~29 , z80_|execute_|ctl_reg_gp_hilo[0]~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 , z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~31 , z80_|execute_|ctl_reg_gp_hilo[0]~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~51 , z80_|execute_|ctl_reg_gp_hilo[0]~51, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~30 , z80_|execute_|ctl_reg_gp_hilo[0]~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~32 , z80_|execute_|ctl_reg_gp_hilo[0]~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~34 , z80_|execute_|ctl_reg_gp_hilo[0]~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~24 , z80_|execute_|ctl_reg_gp_hilo[1]~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~25 , z80_|execute_|ctl_reg_gp_hilo[0]~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~36 , z80_|execute_|ctl_reg_gp_hilo[1]~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 , z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4, spectrum, 1 -instance = comp, \z80_|execute_|setM1~40 , z80_|execute_|setM1~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~18 , z80_|execute_|ctl_reg_gp_hilo[1]~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~37 , z80_|execute_|ctl_reg_gp_hilo[1]~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~38 , z80_|execute_|ctl_reg_gp_hilo[0]~38, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~93 , z80_|reg_file_|gdfx_temp0[0]~93, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_de~0 , z80_|reg_control_|reg_sel_de~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_50 , z80_|reg_file_|SYNTHESIZED_WIRE_50, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 , z80_|reg_file_|SYNTHESIZED_WIRE_70~2, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 , z80_|reg_file_|SYNTHESIZED_WIRE_66~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 , z80_|reg_file_|SYNTHESIZED_WIRE_38~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 , z80_|reg_file_|SYNTHESIZED_WIRE_42~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~9 , z80_|execute_|ctl_reg_in_hi~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~10 , z80_|execute_|ctl_reg_in_hi~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~19 , z80_|execute_|ctl_reg_sel_wz~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 , z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_lo~8 , z80_|execute_|ctl_reg_in_lo~8, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~19 , z80_|reg_file_|gdfx_temp0[0]~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~4 , z80_|execute_|ctl_reg_use_sp~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~5 , z80_|execute_|ctl_reg_use_sp~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~6 , z80_|execute_|ctl_reg_use_sp~6, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 , z80_|reg_file_|SYNTHESIZED_WIRE_78~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal21~2 , z80_|pla_decode_|Equal21~2, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_af~0 , z80_|reg_control_|bank_af~0, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_af , z80_|reg_control_|bank_af, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_af~0 , z80_|reg_control_|reg_sel_af~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_34 , z80_|reg_file_|SYNTHESIZED_WIRE_34, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_af2~0 , z80_|reg_control_|reg_sel_af2~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_30 , z80_|reg_file_|SYNTHESIZED_WIRE_30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~12 , z80_|execute_|ctl_reg_sel_wz~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~4 , z80_|execute_|ctl_flags_bus~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~6 , z80_|execute_|ctl_flags_bus~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~7 , z80_|execute_|ctl_flags_bus~7, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~24 , z80_|execute_|fMRead~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~13 , z80_|execute_|ctl_flags_bus~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus , z80_|execute_|ctl_flags_bus, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~3 , z80_|execute_|ctl_inc_dec~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~14 , z80_|execute_|ctl_reg_sys_hilo[1]~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~2 , z80_|execute_|ctl_reg_sel_pc~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~3 , z80_|execute_|ctl_reg_sel_pc~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~6 , z80_|execute_|ctl_reg_sel_pc~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~5 , z80_|execute_|ctl_reg_sel_pc~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~4 , z80_|execute_|ctl_reg_sel_pc~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~7 , z80_|execute_|ctl_reg_sel_pc~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~8 , z80_|execute_|ctl_reg_sel_pc~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~9 , z80_|execute_|ctl_reg_sel_pc~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~10 , z80_|execute_|ctl_reg_sel_pc~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~13 , z80_|execute_|ctl_reg_sys_hilo[1]~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~15 , z80_|execute_|ctl_reg_sys_hilo[1]~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~29 , z80_|execute_|ctl_bus_inc_oe~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~13 , z80_|execute_|ctl_mRead~13, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~49 , z80_|execute_|pc_inc_hold~49, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~9 , z80_|execute_|ctl_reg_sys_hilo[1]~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~10 , z80_|execute_|ctl_reg_sys_hilo[1]~10, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~28 , z80_|execute_|pc_inc_hold~28, spectrum, 1 -instance = comp, \z80_|execute_|setM1~35 , z80_|execute_|setM1~35, spectrum, 1 -instance = comp, \z80_|execute_|setM1~36 , z80_|execute_|setM1~36, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~5 , z80_|execute_|fMRead~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~31 , z80_|execute_|ctl_bus_inc_oe~31, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~29 , z80_|execute_|pc_inc_hold~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we~1 , z80_|execute_|ctl_reg_sys_we~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we~2 , z80_|execute_|ctl_reg_sys_we~2, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal33~3 , z80_|pla_decode_|Equal33~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we~0 , z80_|execute_|ctl_reg_sys_we~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we~3 , z80_|execute_|ctl_reg_sys_we~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we_lo~2 , z80_|execute_|ctl_reg_sys_we_lo~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we_lo~3 , z80_|execute_|ctl_reg_sys_we_lo~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we_lo~4 , z80_|execute_|ctl_reg_sys_we_lo~4, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo , z80_|reg_control_|reg_sys_we_lo, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_ir~0 , z80_|execute_|ctl_reg_sel_ir~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_ir~1 , z80_|execute_|ctl_reg_sel_ir~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~9 , z80_|execute_|ctl_reg_out_lo~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~36 , z80_|execute_|ctl_reg_sys_hilo[1]~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~12 , z80_|execute_|ctl_reg_sys_hilo[0]~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 , z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~4 , z80_|execute_|ctl_reg_in_hi~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~4 , z80_|execute_|ctl_reg_sel_wz~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 , z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~5 , z80_|execute_|ctl_reg_sel_wz~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~6 , z80_|execute_|ctl_reg_sel_wz~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~7 , z80_|execute_|ctl_reg_sel_wz~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo~16 , z80_|execute_|ctl_reg_sys_hilo~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~11 , z80_|execute_|ctl_reg_sel_pc~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~17 , z80_|execute_|ctl_reg_sys_hilo[1]~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~12 , z80_|execute_|ctl_reg_sel_pc~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~13 , z80_|execute_|ctl_reg_sel_pc~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~4 , z80_|execute_|ctl_al_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~38 , z80_|execute_|ctl_reg_sys_hilo[1]~38, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~0 , z80_|execute_|fMRead~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~24 , z80_|execute_|ctl_reg_sys_hilo[1]~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~25 , z80_|execute_|ctl_reg_sys_hilo[1]~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~4 , z80_|execute_|ctl_inc_dec~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~21 , z80_|execute_|ctl_reg_sys_hilo[1]~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~9 , z80_|execute_|ctl_reg_sel_wz~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 , z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~22 , z80_|execute_|ctl_reg_sys_hilo[1]~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~23 , z80_|execute_|ctl_reg_sys_hilo[1]~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~8 , z80_|execute_|ctl_reg_sel_wz~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~18 , z80_|execute_|ctl_reg_sys_hilo[1]~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~19 , z80_|execute_|ctl_reg_sys_hilo[1]~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~26 , z80_|execute_|ctl_reg_sys_hilo[1]~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~5 , z80_|execute_|ctl_al_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~27 , z80_|execute_|ctl_reg_sys_hilo[1]~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~28 , z80_|execute_|ctl_reg_sys_hilo[1]~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~18 , z80_|execute_|ctl_reg_sel_wz~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~37 , z80_|execute_|ctl_reg_sys_hilo[0]~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~29 , z80_|execute_|ctl_reg_sys_hilo[0]~29, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_62 , z80_|reg_file_|SYNTHESIZED_WIRE_62, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~38 , z80_|execute_|ctl_bus_inc_oe~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~39 , z80_|execute_|ctl_bus_inc_oe~39, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~30 , z80_|execute_|ctl_bus_inc_oe~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~45 , z80_|execute_|ctl_bus_inc_oe~45, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~1 , z80_|execute_|fMRead~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~36 , z80_|execute_|ctl_bus_inc_oe~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~27 , z80_|execute_|ctl_bus_inc_oe~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~28 , z80_|execute_|ctl_bus_inc_oe~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~37 , z80_|execute_|ctl_bus_inc_oe~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~40 , z80_|execute_|ctl_bus_inc_oe~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~35 , z80_|execute_|ctl_bus_inc_oe~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~77 , z80_|execute_|ctl_inc_cy~77, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~32 , z80_|execute_|ctl_bus_inc_oe~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 , z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~33 , z80_|execute_|ctl_bus_inc_oe~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~34 , z80_|execute_|ctl_bus_inc_oe~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~41 , z80_|execute_|ctl_bus_inc_oe~41, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~10 , z80_|execute_|ctl_reg_sel_wz~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~11 , z80_|execute_|ctl_reg_sel_wz~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~3 , z80_|execute_|ctl_sw_4d~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~4 , z80_|execute_|ctl_sw_4d~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~2 , z80_|execute_|ctl_sw_4d~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~5 , z80_|execute_|ctl_sw_4d~5, spectrum, 1 -instance = comp, \z80_|execute_|setM1~45 , z80_|execute_|setM1~45, spectrum, 1 -instance = comp, \z80_|execute_|setM1~46 , z80_|execute_|setM1~46, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~1 , z80_|execute_|ctl_sw_4d~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~0 , z80_|execute_|ctl_sw_4d~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~6 , z80_|execute_|ctl_sw_4d~6, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~4 , z80_|execute_|fMRead~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~16 , z80_|execute_|ctl_reg_sel_pc~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~14 , z80_|execute_|ctl_reg_sel_pc~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~20 , z80_|execute_|ctl_reg_sel_pc~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~15 , z80_|execute_|ctl_reg_sel_pc~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~17 , z80_|execute_|ctl_reg_sel_pc~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~18 , z80_|execute_|ctl_reg_sel_pc~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~19 , z80_|execute_|ctl_reg_sel_pc~19, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_pc~3 , z80_|reg_control_|reg_sel_pc~3, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_pc , z80_|reg_control_|reg_sel_pc, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_74 , z80_|reg_file_|SYNTHESIZED_WIRE_74, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[0]~2 , z80_|reg_file_|db_lo_as[0]~2, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_75 , z80_|reg_file_|SYNTHESIZED_WIRE_75, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[7] , z80_|reg_file_|b2v_latch_pc_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[7]~22 , z80_|reg_file_|db_lo_as[7]~22, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_63 , z80_|reg_file_|SYNTHESIZED_WIRE_63, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[7] , z80_|reg_file_|b2v_latch_ir_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[7]~23 , z80_|reg_file_|db_lo_as[7]~23, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_10~0 , z80_|resets_|SYNTHESIZED_WIRE_10~0, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_10 , z80_|resets_|SYNTHESIZED_WIRE_10, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_9 , z80_|resets_|SYNTHESIZED_WIRE_9, spectrum, 1 -instance = comp, \z80_|resets_|DFFE_intr_ff3 , z80_|resets_|DFFE_intr_ff3, spectrum, 1 instance = comp, \KEY[0]~input , KEY[0]~input, spectrum, 1 instance = comp, \z80_|resets_|x1~0 , z80_|resets_|x1~0, spectrum, 1 instance = comp, \z80_|fpga_reset~feeder , z80_|fpga_reset~feeder, spectrum, 1 instance = comp, \z80_|fpga_reset , z80_|fpga_reset, spectrum, 1 instance = comp, \z80_|fpga_reset~clkctrl , z80_|fpga_reset~clkctrl, spectrum, 1 instance = comp, \z80_|resets_|x1 , z80_|resets_|x1, spectrum, 1 -instance = comp, \z80_|resets_|clrpc_int~0 , z80_|resets_|clrpc_int~0, spectrum, 1 -instance = comp, \z80_|resets_|clrpc_int , z80_|resets_|clrpc_int, spectrum, 1 -instance = comp, \z80_|resets_|clrpc~0 , z80_|resets_|clrpc~0, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[7] , z80_|address_latch_|abusz[7], spectrum, 1 -instance = comp, \z80_|execute_|ctl_apin_mux~1 , z80_|execute_|ctl_apin_mux~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~6 , z80_|execute_|ctl_al_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~7 , z80_|execute_|ctl_al_we~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~8 , z80_|execute_|ctl_al_we~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~10 , z80_|execute_|ctl_alu_oe~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~9 , z80_|execute_|ctl_al_we~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~10 , z80_|execute_|ctl_al_we~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~11 , z80_|execute_|ctl_al_we~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~12 , z80_|execute_|ctl_al_we~12, spectrum, 1 -instance = comp, \z80_|address_latch_|Q[7] , z80_|address_latch_|Q[7], spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~6 , z80_|execute_|ctl_inc_dec~6, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~0 , z80_|execute_|fIOWrite~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~8 , z80_|execute_|ctl_inc_dec~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~9 , z80_|execute_|ctl_inc_dec~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~10 , z80_|execute_|ctl_inc_dec~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~7 , z80_|execute_|ctl_inc_dec~7, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[2] , z80_|reg_file_|b2v_latch_ir_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_54 , z80_|reg_file_|SYNTHESIZED_WIRE_54, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_58 , z80_|reg_file_|SYNTHESIZED_WIRE_58, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_55 , z80_|reg_file_|SYNTHESIZED_WIRE_55, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] , z80_|reg_file_|b2v_latch_hl2_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_59 , z80_|reg_file_|SYNTHESIZED_WIRE_59, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[2] , z80_|reg_file_|b2v_latch_hl_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~34 , z80_|reg_file_|gdfx_temp0[2]~34, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_51 , z80_|reg_file_|SYNTHESIZED_WIRE_51, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[2] , z80_|reg_file_|b2v_latch_de_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_de2~4 , z80_|reg_control_|reg_sel_de2~4, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_46 , z80_|reg_file_|SYNTHESIZED_WIRE_46, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_47 , z80_|reg_file_|SYNTHESIZED_WIRE_47, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[2] , z80_|reg_file_|b2v_latch_de2_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~33 , z80_|reg_file_|gdfx_temp0[2]~33, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 , z80_|reg_file_|SYNTHESIZED_WIRE_71~2, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 , z80_|reg_file_|SYNTHESIZED_WIRE_43~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[2] , z80_|reg_file_|b2v_latch_bc_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 , z80_|reg_file_|SYNTHESIZED_WIRE_39~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] , z80_|reg_file_|b2v_latch_bc2_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~36 , z80_|reg_file_|gdfx_temp0[2]~36, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_83 , z80_|reg_file_|SYNTHESIZED_WIRE_83, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[2] , z80_|reg_file_|b2v_latch_wz_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~37 , z80_|reg_file_|gdfx_temp0[2]~37, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 , z80_|reg_file_|SYNTHESIZED_WIRE_79~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[2] , z80_|reg_file_|b2v_latch_sp_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~39 , z80_|reg_file_|gdfx_temp0[2]~39, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_iy~2 , z80_|reg_control_|reg_sel_iy~2, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_70 , z80_|reg_file_|SYNTHESIZED_WIRE_70, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 , z80_|reg_file_|SYNTHESIZED_WIRE_67~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[2] , z80_|reg_file_|b2v_latch_ix_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_71 , z80_|reg_file_|SYNTHESIZED_WIRE_71, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[2] , z80_|reg_file_|b2v_latch_iy_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~38 , z80_|reg_file_|gdfx_temp0[2]~38, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_31 , z80_|reg_file_|SYNTHESIZED_WIRE_31, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[2] , z80_|reg_file_|b2v_latch_af2_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder , z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_35 , z80_|reg_file_|SYNTHESIZED_WIRE_35, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[2] , z80_|reg_file_|b2v_latch_af_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~35 , z80_|reg_file_|gdfx_temp0[2]~35, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~40 , z80_|reg_file_|gdfx_temp0[2]~40, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~41 , z80_|reg_file_|gdfx_temp0[2]~41, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~42 , z80_|reg_file_|gdfx_temp0[2]~42, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[2] , z80_|reg_file_|b2v_latch_pc_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[2]~7 , z80_|reg_file_|db_lo_as[2]~7, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[2]~8 , z80_|reg_file_|db_lo_as[2]~8, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[0] , z80_|reg_file_|b2v_latch_ir_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[0] , z80_|reg_file_|b2v_latch_de_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[0] , z80_|reg_file_|b2v_latch_de2_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~10 , z80_|reg_file_|gdfx_temp0[0]~10, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] , z80_|reg_file_|b2v_latch_hl2_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 , z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[0] , z80_|reg_file_|b2v_latch_hl_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~11 , z80_|reg_file_|gdfx_temp0[0]~11, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[0] , z80_|reg_file_|b2v_latch_sp_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[0] , z80_|reg_file_|b2v_latch_iy_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~15 , z80_|reg_file_|gdfx_temp0[0]~15, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[0] , z80_|reg_file_|b2v_latch_wz_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder , z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[0] , z80_|reg_file_|b2v_latch_bc_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[0] , z80_|reg_file_|b2v_latch_ix_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~14 , z80_|reg_file_|gdfx_temp0[0]~14, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~16 , z80_|reg_file_|gdfx_temp0[0]~16, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] , z80_|reg_file_|b2v_latch_bc2_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~12 , z80_|reg_file_|gdfx_temp0[0]~12, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[0] , z80_|reg_file_|b2v_latch_af2_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[0] , z80_|reg_file_|b2v_latch_af_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~13 , z80_|reg_file_|gdfx_temp0[0]~13, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~17 , z80_|reg_file_|gdfx_temp0[0]~17, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~22 , z80_|reg_file_|gdfx_temp0[0]~22, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[0] , z80_|reg_file_|b2v_latch_pc_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[0]~0 , z80_|reg_file_|db_lo_as[0]~0, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[0]~1 , z80_|reg_file_|db_lo_as[0]~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~72 , z80_|execute_|ctl_inc_cy~72, spectrum, 1 +instance = comp, \z80_|resets_|x3 , z80_|resets_|x3, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_12 , z80_|resets_|SYNTHESIZED_WIRE_12, spectrum, 1 +instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_9 , z80_|interrupts_|SYNTHESIZED_WIRE_9, spectrum, 1 +instance = comp, \z80_|interrupts_|nmi_armed , z80_|interrupts_|nmi_armed, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl , z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_11 , z80_|resets_|SYNTHESIZED_WIRE_11, spectrum, 1 instance = comp, \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl , ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl, spectrum, 1 -instance = comp, \ula_|video_|Add0~14 , ula_|video_|Add0~14, spectrum, 1 -instance = comp, \ula_|video_|Add0~16 , ula_|video_|Add0~16, spectrum, 1 -instance = comp, \ula_|video_|vga_hc~2 , ula_|video_|vga_hc~2, spectrum, 1 -instance = comp, \ula_|video_|vga_hc[8] , ula_|video_|vga_hc[8], spectrum, 1 -instance = comp, \ula_|video_|Add0~18 , ula_|video_|Add0~18, spectrum, 1 -instance = comp, \ula_|video_|vga_hc~1 , ula_|video_|vga_hc~1, spectrum, 1 -instance = comp, \ula_|video_|vga_hc[9] , ula_|video_|vga_hc[9], spectrum, 1 instance = comp, \ula_|video_|Add0~0 , ula_|video_|Add0~0, spectrum, 1 instance = comp, \ula_|video_|vga_hc~3 , ula_|video_|vga_hc~3, spectrum, 1 instance = comp, \ula_|video_|vga_hc[0] , ula_|video_|vga_hc[0], spectrum, 1 @@ -981,21 +241,29 @@ instance = comp, \ula_|video_|vga_hc[1] , ula_|video_|vga_hc[1], spectrum, 1 instance = comp, \ula_|video_|Add0~4 , ula_|video_|Add0~4, spectrum, 1 instance = comp, \ula_|video_|vga_hc[2] , ula_|video_|vga_hc[2], spectrum, 1 instance = comp, \ula_|video_|Add0~6 , ula_|video_|Add0~6, spectrum, 1 -instance = comp, \ula_|video_|vga_hc[3]~feeder , ula_|video_|vga_hc[3]~feeder, spectrum, 1 instance = comp, \ula_|video_|vga_hc[3] , ula_|video_|vga_hc[3], spectrum, 1 instance = comp, \ula_|video_|Add0~8 , ula_|video_|Add0~8, spectrum, 1 instance = comp, \ula_|video_|vga_hc[4] , ula_|video_|vga_hc[4], spectrum, 1 -instance = comp, \ula_|video_|Equal0~0 , ula_|video_|Equal0~0, spectrum, 1 -instance = comp, \ula_|video_|Equal0~1 , ula_|video_|Equal0~1, spectrum, 1 -instance = comp, \ula_|video_|Equal1~0 , ula_|video_|Equal1~0, spectrum, 1 instance = comp, \ula_|video_|Add0~10 , ula_|video_|Add0~10, spectrum, 1 instance = comp, \ula_|video_|vga_hc~0 , ula_|video_|vga_hc~0, spectrum, 1 instance = comp, \ula_|video_|vga_hc[5] , ula_|video_|vga_hc[5], spectrum, 1 instance = comp, \ula_|video_|Add0~12 , ula_|video_|Add0~12, spectrum, 1 instance = comp, \ula_|video_|vga_hc[6] , ula_|video_|vga_hc[6], spectrum, 1 +instance = comp, \ula_|video_|Add0~14 , ula_|video_|Add0~14, spectrum, 1 instance = comp, \ula_|video_|vga_hc[7] , ula_|video_|vga_hc[7], spectrum, 1 +instance = comp, \ula_|video_|Equal0~0 , ula_|video_|Equal0~0, spectrum, 1 +instance = comp, \ula_|video_|Equal0~1 , ula_|video_|Equal0~1, spectrum, 1 +instance = comp, \ula_|video_|Add0~16 , ula_|video_|Add0~16, spectrum, 1 +instance = comp, \ula_|video_|vga_hc~2 , ula_|video_|vga_hc~2, spectrum, 1 +instance = comp, \ula_|video_|vga_hc[8] , ula_|video_|vga_hc[8], spectrum, 1 +instance = comp, \ula_|video_|Add0~18 , ula_|video_|Add0~18, spectrum, 1 +instance = comp, \ula_|video_|vga_hc~1 , ula_|video_|vga_hc~1, spectrum, 1 +instance = comp, \ula_|video_|vga_hc[9] , ula_|video_|vga_hc[9], spectrum, 1 +instance = comp, \ula_|video_|Equal1~0 , ula_|video_|Equal1~0, spectrum, 1 instance = comp, \ula_|video_|Add1~0 , ula_|video_|Add1~0, spectrum, 1 instance = comp, \ula_|video_|Add1~2 , ula_|video_|Add1~2, spectrum, 1 +instance = comp, \ula_|video_|vga_vc[1]~1 , ula_|video_|vga_vc[1]~1, spectrum, 1 +instance = comp, \ula_|video_|vga_vc[1] , ula_|video_|vga_vc[1], spectrum, 1 instance = comp, \ula_|video_|Add1~4 , ula_|video_|Add1~4, spectrum, 1 instance = comp, \ula_|video_|vga_vc[2]~2 , ula_|video_|vga_vc[2]~2, spectrum, 1 instance = comp, \ula_|video_|vga_vc[2] , ula_|video_|vga_vc[2], spectrum, 1 @@ -1020,1063 +288,1975 @@ instance = comp, \ula_|video_|vga_vc[8] , ula_|video_|vga_vc[8], spectrum, 1 instance = comp, \ula_|video_|Add1~18 , ula_|video_|Add1~18, spectrum, 1 instance = comp, \ula_|video_|vga_vc[9]~9 , ula_|video_|vga_vc[9]~9, spectrum, 1 instance = comp, \ula_|video_|vga_vc[9] , ula_|video_|vga_vc[9], spectrum, 1 -instance = comp, \ula_|video_|Equal2~0 , ula_|video_|Equal2~0, spectrum, 1 instance = comp, \ula_|video_|Equal3~0 , ula_|video_|Equal3~0, spectrum, 1 +instance = comp, \ula_|video_|Equal2~0 , ula_|video_|Equal2~0, spectrum, 1 instance = comp, \ula_|video_|Equal3~1 , ula_|video_|Equal3~1, spectrum, 1 instance = comp, \ula_|video_|vga_vc[0]~0 , ula_|video_|vga_vc[0]~0, spectrum, 1 instance = comp, \ula_|video_|vga_vc[0] , ula_|video_|vga_vc[0], spectrum, 1 -instance = comp, \ula_|video_|vga_vc[1]~1 , ula_|video_|vga_vc[1]~1, spectrum, 1 -instance = comp, \ula_|video_|vga_vc[1] , ula_|video_|vga_vc[1], spectrum, 1 -instance = comp, \SW[1]~input , SW[1]~input, spectrum, 1 -instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 , z80_|interrupts_|SYNTHESIZED_WIRE_13~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal79~0 , z80_|pla_decode_|Equal79~0, spectrum, 1 -instance = comp, \z80_|interrupts_|DFFE_instIFF2~0 , z80_|interrupts_|DFFE_instIFF2~0, spectrum, 1 -instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_12 , z80_|interrupts_|SYNTHESIZED_WIRE_12, spectrum, 1 -instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl , z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl, spectrum, 1 -instance = comp, \z80_|interrupts_|DFFE_instIFF2 , z80_|interrupts_|DFFE_instIFF2, spectrum, 1 -instance = comp, \z80_|interrupts_|iff1~0 , z80_|interrupts_|iff1~0, spectrum, 1 -instance = comp, \z80_|interrupts_|iff1~1 , z80_|interrupts_|iff1~1, spectrum, 1 -instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_15 , z80_|interrupts_|SYNTHESIZED_WIRE_15, spectrum, 1 -instance = comp, \z80_|interrupts_|iff1 , z80_|interrupts_|iff1, spectrum, 1 instance = comp, \ula_|video_|Equal2~1 , ula_|video_|Equal2~1, spectrum, 1 instance = comp, \ula_|video_|Equal2~2 , ula_|video_|Equal2~2, spectrum, 1 -instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_13 , z80_|interrupts_|SYNTHESIZED_WIRE_13, spectrum, 1 -instance = comp, \z80_|interrupts_|int_armed , z80_|interrupts_|int_armed, spectrum, 1 -instance = comp, \z80_|interrupts_|DFFE_inst44 , z80_|interrupts_|DFFE_inst44, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~38 , z80_|execute_|pc_inc_hold~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~91 , z80_|execute_|ctl_inc_cy~91, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~45 , z80_|execute_|pc_inc_hold~45, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~44 , z80_|execute_|pc_inc_hold~44, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~46 , z80_|execute_|pc_inc_hold~46, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~37 , z80_|execute_|pc_inc_hold~37, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~50 , z80_|execute_|pc_inc_hold~50, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~33 , z80_|execute_|pc_inc_hold~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 , z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 , z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~31 , z80_|execute_|pc_inc_hold~31, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~32 , z80_|execute_|pc_inc_hold~32, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~34 , z80_|execute_|pc_inc_hold~34, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~51 , z80_|execute_|pc_inc_hold~51, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~30 , z80_|execute_|pc_inc_hold~30, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~52 , z80_|execute_|pc_inc_hold~52, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~35 , z80_|execute_|pc_inc_hold~35, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~36 , z80_|execute_|pc_inc_hold~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~44 , z80_|execute_|ctl_inc_cy~44, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 , z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~45 , z80_|execute_|ctl_inc_cy~45, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~43 , z80_|execute_|pc_inc_hold~43, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~71 , z80_|execute_|ctl_inc_cy~71, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~73 , z80_|execute_|ctl_inc_cy~73, spectrum, 1 +instance = comp, \SW[1]~input , SW[1]~input, spectrum, 1 +instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 , z80_|interrupts_|SYNTHESIZED_WIRE_13~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 , z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~4 , z80_|execute_|ctl_mWrite~4, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal0~0 , z80_|pla_decode_|Equal0~0, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_M3_ff~0 , z80_|sequencer_|DFFE_M3_ff~0, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_M3_ff , z80_|sequencer_|DFFE_M3_ff, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~6 , z80_|execute_|ixy_d~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0 , z80_|execute_|ctl_reg_gp_hilo_pla12M3T3_3~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal33~0 , z80_|pla_decode_|Equal33~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~5 , z80_|execute_|ctl_mRead~5, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal77~0 , z80_|pla_decode_|Equal77~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal50~0 , z80_|pla_decode_|Equal50~0, spectrum, 1 +instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_16 , z80_|sequencer_|SYNTHESIZED_WIRE_16, spectrum, 1 +instance = comp, \z80_|clk_delay_|SYNTHESIZED_WIRE_4 , z80_|clk_delay_|SYNTHESIZED_WIRE_4, spectrum, 1 +instance = comp, \z80_|clk_delay_|SYNTHESIZED_WIRE_7 , z80_|clk_delay_|SYNTHESIZED_WIRE_7, spectrum, 1 +instance = comp, \z80_|clk_delay_|DFF_inst5~feeder , z80_|clk_delay_|DFF_inst5~feeder, spectrum, 1 +instance = comp, \z80_|clk_delay_|DFF_inst5 , z80_|clk_delay_|DFF_inst5, spectrum, 1 +instance = comp, \z80_|clk_delay_|hold_clk_iorq , z80_|clk_delay_|hold_clk_iorq, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_T5_ff , z80_|sequencer_|DFFE_T5_ff, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 , z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7, spectrum, 1 +instance = comp, \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 , z80_|decode_state_|SYNTHESIZED_WIRE_0~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_ixiy_we~2 , z80_|execute_|ctl_state_ixiy_we~2, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_inst4 , z80_|decode_state_|DFFE_inst4, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~3 , z80_|execute_|fMWrite~3, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_M4_ff~0 , z80_|sequencer_|DFFE_M4_ff~0, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_M4_ff , z80_|sequencer_|DFFE_M4_ff, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~2 , z80_|execute_|fMWrite~2, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal13~1 , z80_|pla_decode_|Equal13~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal13~2 , z80_|pla_decode_|Equal13~2, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~4 , z80_|execute_|ixy_d~4, spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~1 , z80_|execute_|fIOWrite~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~5 , z80_|execute_|ctl_mWrite~5, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~2 , z80_|execute_|fMRead~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~2 , z80_|execute_|ctl_state_alu~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_iorw~11 , z80_|execute_|ctl_iorw~11, spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~2 , z80_|execute_|fIOWrite~2, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal2~0 , z80_|pla_decode_|Equal2~0, spectrum, 1 +instance = comp, \z80_|decode_state_|table_xx~0 , z80_|decode_state_|table_xx~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal1~7 , z80_|pla_decode_|Equal1~7, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal21~0 , z80_|pla_decode_|Equal21~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~3 , z80_|execute_|ctl_mRead~3, spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~3 , z80_|execute_|fIOWrite~3, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~5 , z80_|execute_|ixy_d~5, spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~4 , z80_|execute_|fIOWrite~4, spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~5 , z80_|execute_|fIOWrite~5, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~4 , z80_|pin_control_|bus_db_pin_oe~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~3 , z80_|execute_|ctl_state_alu~3, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal3~1 , z80_|pla_decode_|Equal3~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~6 , z80_|execute_|ctl_mWrite~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~4 , z80_|execute_|ctl_ir_we~4, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal9~0 , z80_|pla_decode_|Equal9~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal9~1 , z80_|pla_decode_|Equal9~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~0 , z80_|execute_|ctl_sw_2u~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal11~0 , z80_|pla_decode_|Equal11~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~14 , z80_|execute_|ctl_alu_op_low~14, spectrum, 1 instance = comp, \z80_|execute_|ctl_inc_cy~46 , z80_|execute_|ctl_inc_cy~46, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~53 , z80_|execute_|pc_inc_hold~53, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~39 , z80_|execute_|pc_inc_hold~39, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~47 , z80_|execute_|pc_inc_hold~47, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~74 , z80_|execute_|ctl_inc_cy~74, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~78 , z80_|execute_|ctl_inc_cy~78, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~79 , z80_|execute_|ctl_inc_cy~79, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~80 , z80_|execute_|ctl_inc_cy~80, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~81 , z80_|execute_|ctl_inc_cy~81, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~82 , z80_|execute_|ctl_inc_cy~82, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~83 , z80_|execute_|ctl_inc_cy~83, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~84 , z80_|execute_|ctl_inc_cy~84, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~42 , z80_|execute_|pc_inc_hold~42, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~90 , z80_|execute_|ctl_inc_cy~90, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~41 , z80_|execute_|pc_inc_hold~41, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~66 , z80_|execute_|ctl_inc_cy~66, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~67 , z80_|execute_|ctl_inc_cy~67, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~68 , z80_|execute_|ctl_inc_cy~68, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~64 , z80_|execute_|ctl_inc_cy~64, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~63 , z80_|execute_|ctl_inc_cy~63, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~65 , z80_|execute_|ctl_inc_cy~65, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~69 , z80_|execute_|ctl_inc_cy~69, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~49 , z80_|execute_|ctl_inc_cy~49, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~50 , z80_|execute_|ctl_inc_cy~50, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~51 , z80_|execute_|ctl_inc_cy~51, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~52 , z80_|execute_|ctl_inc_cy~52, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~36 , z80_|execute_|ctl_inc_cy~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~37 , z80_|execute_|ctl_inc_cy~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~54 , z80_|execute_|ctl_inc_cy~54, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~41 , z80_|execute_|ctl_inc_cy~41, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~58 , z80_|execute_|ctl_inc_cy~58, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~55 , z80_|execute_|ctl_inc_cy~55, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~56 , z80_|execute_|ctl_inc_cy~56, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~89 , z80_|execute_|ctl_inc_cy~89, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~57 , z80_|execute_|ctl_inc_cy~57, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~59 , z80_|execute_|ctl_inc_cy~59, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~60 , z80_|execute_|ctl_inc_cy~60, spectrum, 1 instance = comp, \z80_|execute_|ctl_inc_cy~47 , z80_|execute_|ctl_inc_cy~47, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~88 , z80_|execute_|ctl_inc_cy~88, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal19~0 , z80_|pla_decode_|Equal19~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal34~0 , z80_|pla_decode_|Equal34~0, spectrum, 1 +instance = comp, \z80_|execute_|comb~0 , z80_|execute_|comb~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal47~0 , z80_|pla_decode_|Equal47~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~45 , z80_|execute_|ctl_inc_cy~45, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~35 , z80_|execute_|ctl_reg_sys_hilo[1]~35, spectrum, 1 +instance = comp, \z80_|sequencer_|M5~0 , z80_|sequencer_|M5~0, spectrum, 1 +instance = comp, \z80_|sequencer_|M5 , z80_|sequencer_|M5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~2 , z80_|execute_|ctl_alu_oe~2, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~7 , z80_|execute_|ixy_d~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~44 , z80_|execute_|ctl_inc_cy~44, spectrum, 1 +instance = comp, \z80_|execute_|ctl_apin_mux~0 , z80_|execute_|ctl_apin_mux~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~4 , z80_|execute_|ctl_mRead~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~5 , z80_|execute_|ctl_ir_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~15 , z80_|execute_|ctl_ir_we~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~14 , z80_|execute_|ctl_ir_we~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~7 , z80_|execute_|ctl_ir_we~7, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~0 , z80_|execute_|fMWrite~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~97 , z80_|execute_|ctl_inc_cy~97, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~96 , z80_|execute_|ctl_inc_cy~96, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~98 , z80_|execute_|ctl_inc_cy~98, spectrum, 1 instance = comp, \z80_|execute_|ctl_inc_cy~48 , z80_|execute_|ctl_inc_cy~48, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~40 , z80_|execute_|pc_inc_hold~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~28 , z80_|execute_|ctl_bus_inc_oe~28, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~1 , z80_|execute_|fMWrite~1, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~3 , z80_|pin_control_|bus_db_pin_oe~3, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~5 , z80_|pin_control_|bus_db_pin_oe~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~6 , z80_|execute_|ctl_mRead~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~2 , z80_|execute_|ctl_reg_in_hi~2, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~6 , z80_|pin_control_|bus_db_pin_oe~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~7 , z80_|execute_|ctl_mWrite~7, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~7 , z80_|pin_control_|bus_db_pin_oe~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~17 , z80_|execute_|ctl_mWrite~17, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~4 , z80_|execute_|fMWrite~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~4 , z80_|execute_|ctl_state_alu~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~49 , z80_|execute_|ctl_inc_cy~49, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~2 , z80_|execute_|ctl_inc_dec~2, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~8 , z80_|pin_control_|bus_db_pin_oe~8, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~8 , z80_|execute_|fMWrite~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~51 , z80_|execute_|ctl_bus_inc_oe~51, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~9 , z80_|execute_|ctl_ir_we~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~10 , z80_|execute_|ctl_alu_core_S~10, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal46~0 , z80_|pla_decode_|Equal46~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~10 , z80_|execute_|ctl_ir_we~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~45 , z80_|execute_|ctl_bus_inc_oe~45, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~6 , z80_|execute_|ctl_ir_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~8 , z80_|execute_|ctl_ir_we~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~29 , z80_|execute_|ctl_bus_inc_oe~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~30 , z80_|execute_|ctl_bus_inc_oe~30, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal55~0 , z80_|pla_decode_|Equal55~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~7 , z80_|execute_|ctl_mRead~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~31 , z80_|execute_|ctl_bus_inc_oe~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~32 , z80_|execute_|ctl_bus_inc_oe~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~14 , z80_|execute_|ctl_alu_shift_oe~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 , z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~17 , z80_|pin_control_|bus_db_pin_oe~17, spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~0 , z80_|execute_|fIOWrite~0, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~6 , z80_|execute_|fMWrite~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~8 , z80_|execute_|ctl_mWrite~8, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~5 , z80_|execute_|fMWrite~5, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~11 , z80_|pin_control_|bus_db_pin_oe~11, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~3 , z80_|execute_|fMRead~3, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~9 , z80_|pin_control_|bus_db_pin_oe~9, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~10 , z80_|pin_control_|bus_db_pin_oe~10, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~12 , z80_|pin_control_|bus_db_pin_oe~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 , z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~6 , z80_|execute_|ctl_reg_sel_wz~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~7 , z80_|execute_|ctl_reg_sel_wz~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~0 , z80_|execute_|ctl_sw_4u~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~8 , z80_|execute_|ctl_reg_sys_hilo[1]~8, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~7 , z80_|execute_|fMWrite~7, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~13 , z80_|pin_control_|bus_db_pin_oe~13, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~14 , z80_|pin_control_|bus_db_pin_oe~14, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~15 , z80_|pin_control_|bus_db_pin_oe~15, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~2 , z80_|pin_control_|bus_db_pin_oe~2, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~16 , z80_|pin_control_|bus_db_pin_oe~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~9 , z80_|execute_|ctl_mRead~9, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal24~0 , z80_|pla_decode_|Equal24~0, spectrum, 1 +instance = comp, \z80_|execute_|nextM~4 , z80_|execute_|nextM~4, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal3~0 , z80_|pla_decode_|Equal3~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_eval_cond~0 , z80_|execute_|ctl_eval_cond~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_iorw~12 , z80_|execute_|ctl_iorw~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_iorw~8 , z80_|execute_|ctl_iorw~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_iorw~9 , z80_|execute_|ctl_iorw~9, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_iorq_ff1 , z80_|memory_ifc_|DFFE_iorq_ff1, spectrum, 1 +instance = comp, \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 , z80_|memory_ifc_|SYNTHESIZED_WIRE_15, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_iorq~feeder , z80_|memory_ifc_|wait_iorq~feeder, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_iorq , z80_|memory_ifc_|wait_iorq, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_iorq_ff4 , z80_|memory_ifc_|DFFE_iorq_ff4, spectrum, 1 +instance = comp, \z80_|memory_ifc_|iorq~0 , z80_|memory_ifc_|iorq~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal33~2 , z80_|pla_decode_|Equal33~2, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~17 , z80_|execute_|ixy_d~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~15 , z80_|execute_|ctl_mWrite~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~18 , z80_|execute_|ctl_mWrite~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~12 , z80_|execute_|ctl_mWrite~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~21 , z80_|execute_|ctl_flags_alu~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~20 , z80_|execute_|ctl_flags_alu~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~3 , z80_|execute_|ctl_reg_in_hi~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~10 , z80_|execute_|ctl_flags_alu~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~10 , z80_|execute_|ctl_mWrite~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~13 , z80_|execute_|ctl_mWrite~13, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~9 , z80_|execute_|ixy_d~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~51 , z80_|execute_|ctl_inc_cy~51, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~12 , z80_|execute_|ctl_inc_dec~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~5 , z80_|execute_|ctl_inc_dec~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~4 , z80_|execute_|ctl_reg_gp_sel[1]~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~13 , z80_|execute_|ctl_flags_use_cf2~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~11 , z80_|execute_|ctl_mWrite~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~25 , z80_|execute_|ctl_mRead~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~22 , z80_|execute_|ctl_flags_alu~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~24 , z80_|execute_|ctl_mRead~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~7 , z80_|execute_|ctl_bus_db_oe~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~14 , z80_|execute_|ctl_mWrite~14, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~8 , z80_|execute_|ixy_d~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~16 , z80_|execute_|ctl_mWrite~16, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_mwr_ff1 , z80_|memory_ifc_|DFFE_mwr_ff1, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_mwr~feeder , z80_|memory_ifc_|wait_mwr~feeder, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_mwr , z80_|memory_ifc_|wait_mwr, spectrum, 1 +instance = comp, \z80_|memory_ifc_|mwr_wr~feeder , z80_|memory_ifc_|mwr_wr~feeder, spectrum, 1 +instance = comp, \z80_|memory_ifc_|mwr_wr , z80_|memory_ifc_|mwr_wr, spectrum, 1 +instance = comp, \z80_|memory_ifc_|nWR_out~0 , z80_|memory_ifc_|nWR_out~0, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_m1_ff1 , z80_|memory_ifc_|DFFE_m1_ff1, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 , z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 , z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_m1_ff3 , z80_|memory_ifc_|DFFE_m1_ff3, spectrum, 1 +instance = comp, \z80_|memory_ifc_|nRD_out~0 , z80_|memory_ifc_|nRD_out~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~2 , z80_|execute_|ctl_mRead~2, spectrum, 1 +instance = comp, \z80_|execute_|fIORead~0 , z80_|execute_|fIORead~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_iorw~10 , z80_|execute_|ctl_iorw~10, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal1~4 , z80_|pla_decode_|Equal1~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~15 , z80_|execute_|ctl_alu_op_low~15, spectrum, 1 +instance = comp, \z80_|execute_|fIORead~1 , z80_|execute_|fIORead~1, spectrum, 1 +instance = comp, \z80_|execute_|fIORead~2 , z80_|execute_|fIORead~2, spectrum, 1 +instance = comp, \z80_|execute_|fIORead~3 , z80_|execute_|fIORead~3, spectrum, 1 +instance = comp, \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 , z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_im_we , z80_|execute_|ctl_im_we, spectrum, 1 +instance = comp, \z80_|interrupts_|im2 , z80_|interrupts_|im2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~10 , z80_|execute_|ctl_mRead~10, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal33~3 , z80_|pla_decode_|Equal33~3, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal6~1 , z80_|pla_decode_|Equal6~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~30 , z80_|execute_|ctl_mRead~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~31 , z80_|execute_|ctl_mRead~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~12 , z80_|execute_|ctl_ir_we~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~5 , z80_|execute_|ctl_flags_bus~5, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal44~0 , z80_|pla_decode_|Equal44~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~6 , z80_|execute_|ctl_state_alu~6, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~5 , z80_|execute_|fMRead~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~17 , z80_|execute_|ctl_mRead~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~12 , z80_|execute_|ctl_mRead~12, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal49~0 , z80_|pla_decode_|Equal49~0, spectrum, 1 +instance = comp, \z80_|execute_|setM1~57 , z80_|execute_|setM1~57, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~15 , z80_|execute_|ctl_mRead~15, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal25~0 , z80_|pla_decode_|Equal25~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal12~1 , z80_|pla_decode_|Equal12~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~8 , z80_|execute_|ctl_reg_sel_wz~8, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~10 , z80_|execute_|ixy_d~10, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~16 , z80_|execute_|ixy_d~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~4 , z80_|execute_|ctl_al_we~4, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~4 , z80_|execute_|fMRead~4, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal29~0 , z80_|pla_decode_|Equal29~0, spectrum, 1 +instance = comp, \z80_|execute_|setM1~38 , z80_|execute_|setM1~38, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal35~0 , z80_|pla_decode_|Equal35~0, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~33 , z80_|execute_|pc_inc_hold~33, spectrum, 1 +instance = comp, \z80_|execute_|comb~1 , z80_|execute_|comb~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~13 , z80_|execute_|ctl_mRead~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~9 , z80_|execute_|ctl_reg_sys_hilo[1]~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~10 , z80_|execute_|ctl_reg_sys_hilo[1]~10, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal40~2 , z80_|pla_decode_|Equal40~2, spectrum, 1 +instance = comp, \z80_|execute_|setM1~36 , z80_|execute_|setM1~36, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~14 , z80_|execute_|pc_inc_hold~14, spectrum, 1 +instance = comp, \z80_|execute_|setM1~37 , z80_|execute_|setM1~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~14 , z80_|execute_|ctl_mRead~14, spectrum, 1 +instance = comp, \z80_|execute_|setM1~39 , z80_|execute_|setM1~39, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~32 , z80_|execute_|ctl_mRead~32, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal40~0 , z80_|pla_decode_|Equal40~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal21~2 , z80_|pla_decode_|Equal21~2, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal37~0 , z80_|pla_decode_|Equal37~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~26 , z80_|execute_|ctl_mRead~26, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal12~0 , z80_|pla_decode_|Equal12~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~16 , z80_|execute_|ctl_mRead~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~5 , z80_|execute_|ctl_reg_in_hi~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~19 , z80_|execute_|ctl_mRead~19, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal24~1 , z80_|pla_decode_|Equal24~1, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~0 , z80_|reg_control_|reg_sys_we_lo~0, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~1 , z80_|reg_control_|reg_sys_we_lo~1, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~2 , z80_|reg_control_|reg_sys_we_lo~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~18 , z80_|execute_|ctl_mRead~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~20 , z80_|execute_|ctl_mRead~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~22 , z80_|execute_|ctl_mRead~22, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal52~1 , z80_|pla_decode_|Equal52~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~23 , z80_|execute_|ctl_mRead~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~27 , z80_|execute_|ctl_mRead~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~28 , z80_|execute_|ctl_mRead~28, spectrum, 1 +instance = comp, \z80_|execute_|nextM~3 , z80_|execute_|nextM~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~29 , z80_|execute_|ctl_mRead~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~33 , z80_|execute_|ctl_mRead~33, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_mrd_ff1 , z80_|memory_ifc_|DFFE_mrd_ff1, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_mrd~feeder , z80_|memory_ifc_|wait_mrd~feeder, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_mrd , z80_|memory_ifc_|wait_mrd, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_mrd_ff3~feeder , z80_|memory_ifc_|DFFE_mrd_ff3~feeder, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_mrd_ff3 , z80_|memory_ifc_|DFFE_mrd_ff3, spectrum, 1 +instance = comp, \z80_|memory_ifc_|nRD_out~1 , z80_|memory_ifc_|nRD_out~1, spectrum, 1 +instance = comp, \z80_|memory_ifc_|nRD_out~2 , z80_|memory_ifc_|nRD_out~2, spectrum, 1 +instance = comp, \Equal2~1 , Equal2~1, spectrum, 1 +instance = comp, \PS2_DAT~input , PS2_DAT~input, spectrum, 1 +instance = comp, \reset~clkctrl , reset~clkctrl, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count~2 , ula_|ps2_keyboard_|bit_count~2, spectrum, 1 +instance = comp, \PS2_CLK~input , PS2_CLK~input, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[7]~feeder , ula_|ps2_keyboard_|clk_filter[7]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[7] , ula_|ps2_keyboard_|clk_filter[7], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[6]~feeder , ula_|ps2_keyboard_|clk_filter[6]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[6] , ula_|ps2_keyboard_|clk_filter[6], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[5]~feeder , ula_|ps2_keyboard_|clk_filter[5]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[5] , ula_|ps2_keyboard_|clk_filter[5], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[4]~feeder , ula_|ps2_keyboard_|clk_filter[4]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[4] , ula_|ps2_keyboard_|clk_filter[4], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[3]~feeder , ula_|ps2_keyboard_|clk_filter[3]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[3] , ula_|ps2_keyboard_|clk_filter[3], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|Equal0~0 , ula_|ps2_keyboard_|Equal0~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[2]~feeder , ula_|ps2_keyboard_|clk_filter[2]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[2] , ula_|ps2_keyboard_|clk_filter[2], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[1]~feeder , ula_|ps2_keyboard_|clk_filter[1]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[1] , ula_|ps2_keyboard_|clk_filter[1], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|Equal0~1 , ula_|ps2_keyboard_|Equal0~1, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[0]~0 , ula_|ps2_keyboard_|clk_filter[0]~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[0] , ula_|ps2_keyboard_|clk_filter[0], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|ps2_clk_in~0 , ula_|ps2_keyboard_|ps2_clk_in~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|ps2_clk_in , ula_|ps2_keyboard_|ps2_clk_in, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_edge~0 , ula_|ps2_keyboard_|clk_edge~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_edge , ula_|ps2_keyboard_|clk_edge, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count[1] , ula_|ps2_keyboard_|bit_count[1], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count~3 , ula_|ps2_keyboard_|bit_count~3, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count[3] , ula_|ps2_keyboard_|bit_count[3], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count~1 , ula_|ps2_keyboard_|bit_count~1, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count[2] , ula_|ps2_keyboard_|bit_count[2], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count~0 , ula_|ps2_keyboard_|bit_count~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count[0] , ula_|ps2_keyboard_|bit_count[0], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|LessThan0~0 , ula_|ps2_keyboard_|LessThan0~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|always1~0 , ula_|ps2_keyboard_|always1~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[0]~0 , ula_|ps2_keyboard_|shiftreg[0]~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[8] , ula_|ps2_keyboard_|shiftreg[8], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[7] , ula_|ps2_keyboard_|shiftreg[7], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[6] , ula_|ps2_keyboard_|shiftreg[6], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[5] , ula_|ps2_keyboard_|shiftreg[5], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[4] , ula_|ps2_keyboard_|shiftreg[4], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[3] , ula_|ps2_keyboard_|shiftreg[3], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[2] , ula_|ps2_keyboard_|shiftreg[2], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[1] , ula_|ps2_keyboard_|shiftreg[1], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[0] , ula_|ps2_keyboard_|shiftreg[0], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|Equal0~0 , ula_|zx_keyboard_|Equal0~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|Equal0~1 , ula_|zx_keyboard_|Equal0~1, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|WideXor0~1 , ula_|ps2_keyboard_|WideXor0~1, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|WideXor0~0 , ula_|ps2_keyboard_|WideXor0~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|WideXor0~2 , ula_|ps2_keyboard_|WideXor0~2, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|scan_code_ready~0 , ula_|ps2_keyboard_|scan_code_ready~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|scan_code_ready , ula_|ps2_keyboard_|scan_code_ready, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|released~0 , ula_|zx_keyboard_|released~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|released , ula_|zx_keyboard_|released, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|Equal0~2 , ula_|zx_keyboard_|Equal0~2, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][2]~50 , ula_|zx_keyboard_|keys[3][2]~50, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|extended~0 , ula_|zx_keyboard_|extended~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|extended , ula_|zx_keyboard_|extended, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][4]~15 , ula_|zx_keyboard_|keys[7][4]~15, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][2]~52 , ula_|zx_keyboard_|keys[2][2]~52, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][2]~53 , ula_|zx_keyboard_|keys[2][2]~53, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][2] , ula_|zx_keyboard_|keys[2][2], spectrum, 1 +instance = comp, \z80_|resets_|clrpc_int~0 , z80_|resets_|clrpc_int~0, spectrum, 1 +instance = comp, \z80_|resets_|clrpc_int , z80_|resets_|clrpc_int, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_10~0 , z80_|resets_|SYNTHESIZED_WIRE_10~0, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_10 , z80_|resets_|SYNTHESIZED_WIRE_10, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_9~feeder , z80_|resets_|SYNTHESIZED_WIRE_9~feeder, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_9 , z80_|resets_|SYNTHESIZED_WIRE_9, spectrum, 1 +instance = comp, \z80_|resets_|DFFE_intr_ff3 , z80_|resets_|DFFE_intr_ff3, spectrum, 1 +instance = comp, \z80_|resets_|clrpc~0 , z80_|resets_|clrpc~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~38 , z80_|execute_|ctl_reg_sys_hilo[1]~38, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal21~1 , z80_|pla_decode_|Equal21~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal40~1 , z80_|pla_decode_|Equal40~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal39~0 , z80_|pla_decode_|Equal39~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~1 , z80_|execute_|ctl_bus_db_oe~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~24 , z80_|execute_|ctl_reg_sys_hilo[1]~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~25 , z80_|execute_|ctl_reg_sys_hilo[1]~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~18 , z80_|execute_|ctl_reg_sys_hilo[1]~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~19 , z80_|execute_|ctl_reg_sys_hilo[1]~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~10 , z80_|execute_|ctl_reg_sel_wz~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo~20 , z80_|execute_|ctl_reg_sys_hilo~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~4 , z80_|execute_|ctl_inc_dec~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~21 , z80_|execute_|ctl_reg_sys_hilo[1]~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 , z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~22 , z80_|execute_|ctl_reg_sys_hilo[1]~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~23 , z80_|execute_|ctl_reg_sys_hilo[1]~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~26 , z80_|execute_|ctl_reg_sys_hilo[1]~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~5 , z80_|execute_|ctl_al_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~27 , z80_|execute_|ctl_reg_sys_hilo[1]~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~13 , z80_|execute_|ctl_al_we~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~17 , z80_|execute_|ctl_reg_sys_hilo[1]~17, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal10~0 , z80_|pla_decode_|Equal10~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo~16 , z80_|execute_|ctl_reg_sys_hilo~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~11 , z80_|execute_|ctl_reg_sel_pc~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~12 , z80_|execute_|ctl_reg_sel_pc~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~13 , z80_|execute_|ctl_reg_sel_pc~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~6 , z80_|execute_|ctl_alu_bs_oe~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~0 , z80_|execute_|ctl_bus_db_oe~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~2 , z80_|execute_|ctl_alu_sel_op2_neg~2, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_pc~1 , z80_|reg_control_|reg_sel_pc~1, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_pc~0 , z80_|reg_control_|reg_sel_pc~0, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_pc~2 , z80_|reg_control_|reg_sel_pc~2, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal56~0 , z80_|pla_decode_|Equal56~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~18 , z80_|execute_|ctl_alu_op_low~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~17 , z80_|execute_|ctl_alu_op_low~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~4 , z80_|execute_|ctl_alu_oe~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~4 , z80_|execute_|ctl_reg_in_hi~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~9 , z80_|execute_|ctl_reg_sel_wz~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~3 , z80_|execute_|ctl_inc_dec~3, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~6 , z80_|execute_|fMRead~6, spectrum, 1 +instance = comp, \z80_|nM1_int~2 , z80_|nM1_int~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~14 , z80_|execute_|ctl_reg_sys_hilo[1]~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~94 , z80_|execute_|ctl_inc_cy~94, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~50 , z80_|execute_|ctl_inc_cy~50, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~6 , z80_|execute_|ctl_reg_sel_pc~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~5 , z80_|execute_|ctl_reg_sel_pc~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~4 , z80_|execute_|ctl_reg_sel_pc~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~2 , z80_|execute_|ctl_reg_sel_pc~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~3 , z80_|execute_|ctl_reg_sel_pc~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~7 , z80_|execute_|ctl_reg_sel_pc~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~8 , z80_|execute_|ctl_reg_sel_pc~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~9 , z80_|execute_|ctl_reg_sel_pc~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~10 , z80_|execute_|ctl_reg_sel_pc~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~99 , z80_|execute_|ctl_inc_cy~99, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~13 , z80_|execute_|ctl_reg_sys_hilo[1]~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 , z80_|execute_|ctl_reg_sys_hilo_1M1T3_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~15 , z80_|execute_|ctl_reg_sys_hilo[1]~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~28 , z80_|execute_|ctl_reg_sys_hilo[1]~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_hi~4 , z80_|execute_|ctl_reg_out_hi~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 , z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_lo~9 , z80_|execute_|ctl_reg_in_lo~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~30 , z80_|execute_|ctl_reg_sys_hilo[1]~30, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal1~5 , z80_|pla_decode_|Equal1~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~20 , z80_|execute_|ctl_alu_op_low~20, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal48~0 , z80_|pla_decode_|Equal48~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~31 , z80_|execute_|ctl_reg_sys_hilo[1]~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~32 , z80_|execute_|ctl_reg_sys_hilo[1]~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~13 , z80_|execute_|ctl_reg_sel_wz~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~33 , z80_|execute_|ctl_reg_sys_hilo[1]~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~4 , z80_|execute_|ctl_flags_bus~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_ir~0 , z80_|execute_|ctl_reg_sel_ir~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_ir~1 , z80_|execute_|ctl_reg_sel_ir~1, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~7 , z80_|execute_|fMRead~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~33 , z80_|execute_|ctl_bus_inc_oe~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~35 , z80_|execute_|ctl_bus_inc_oe~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~34 , z80_|execute_|ctl_bus_inc_oe~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we~0 , z80_|execute_|ctl_reg_sys_we~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we~1 , z80_|execute_|ctl_reg_sys_we~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 , z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we~2 , z80_|execute_|ctl_reg_sys_we~2, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal8~0 , z80_|pla_decode_|Equal8~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we_lo~0 , z80_|execute_|ctl_reg_sys_we_lo~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we_lo~1 , z80_|execute_|ctl_reg_sys_we_lo~1, spectrum, 1 +instance = comp, \z80_|alu_control_|sel[1]~0 , z80_|alu_control_|sel[1]~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~7 , z80_|execute_|ctl_state_alu~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~11 , z80_|execute_|ctl_state_alu~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~9 , z80_|execute_|ctl_state_alu~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~5 , z80_|execute_|ctl_state_alu~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~10 , z80_|execute_|ctl_state_alu~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~8 , z80_|execute_|ctl_state_alu~8, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal62~2 , z80_|pla_decode_|Equal62~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~5 , z80_|execute_|ctl_flags_pf_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~11 , z80_|execute_|ctl_ir_we~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~11 , z80_|execute_|ctl_alu_bs_oe~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~7 , z80_|execute_|ctl_alu_bs_oe~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~3 , z80_|execute_|ctl_bus_db_oe~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~19 , z80_|execute_|ctl_flags_xy_we~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~27 , z80_|execute_|ctl_alu_shift_oe~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~25 , z80_|execute_|ctl_alu_shift_oe~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~26 , z80_|execute_|ctl_alu_shift_oe~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~28 , z80_|execute_|ctl_alu_shift_oe~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~19 , z80_|execute_|ctl_alu_op_low~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~15 , z80_|execute_|ctl_flags_bus~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~9 , z80_|execute_|ctl_flags_bus~9, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal20~0 , z80_|pla_decode_|Equal20~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal68~2 , z80_|pla_decode_|Equal68~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~14 , z80_|execute_|ctl_flags_bus~14, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal63~0 , z80_|pla_decode_|Equal63~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal76~2 , z80_|pla_decode_|Equal76~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~8 , z80_|execute_|ctl_flags_bus~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~6 , z80_|execute_|ctl_flags_bus~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~7 , z80_|execute_|ctl_flags_bus~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~10 , z80_|execute_|ctl_flags_bus~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~11 , z80_|execute_|ctl_flags_xy_we~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf2_we , z80_|execute_|ctl_flags_hf2_we, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~41 , z80_|execute_|ctl_alu_shift_oe~41, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~46 , z80_|execute_|ctl_alu_shift_oe~46, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel~7 , z80_|execute_|ctl_reg_gp_sel~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~12 , z80_|execute_|ctl_state_alu~12, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal62~3 , z80_|pla_decode_|Equal62~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~6 , z80_|execute_|ctl_flags_pf_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 , z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~48 , z80_|execute_|ctl_reg_gp_hilo[1]~48, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel_pla82M1T1_16 , z80_|execute_|ctl_pf_sel_pla82M1T1_16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_we~7 , z80_|execute_|ctl_flags_cf_we~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel[0]~10 , z80_|execute_|ctl_pf_sel[0]~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_we~5 , z80_|execute_|ctl_flags_hf_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~11 , z80_|execute_|ctl_flags_pf_we~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~2 , z80_|execute_|ctl_flags_pf_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~3 , z80_|execute_|ctl_flags_pf_we~3, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal10~1 , z80_|pla_decode_|Equal10~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel_pla11M1T1_11 , z80_|execute_|ctl_pf_sel_pla11M1T1_11, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal69~0 , z80_|pla_decode_|Equal69~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~7 , z80_|execute_|ctl_flags_pf_we~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~8 , z80_|execute_|ctl_flags_pf_we~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~9 , z80_|execute_|ctl_flags_pf_we~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel[0]~13 , z80_|execute_|ctl_pf_sel[0]~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~10 , z80_|execute_|ctl_flags_pf_we~10, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~3 , z80_|reg_control_|reg_sys_we_lo~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~18 , z80_|execute_|ctl_flags_xy_we~18, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~4 , z80_|reg_control_|reg_sys_we_lo~4, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~5 , z80_|reg_control_|reg_sys_we_lo~5, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~6 , z80_|reg_control_|reg_sys_we_lo~6, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo , z80_|reg_control_|reg_sys_we_lo, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~21 , z80_|execute_|ctl_reg_sel_wz~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~20 , z80_|execute_|ctl_reg_sel_wz~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~37 , z80_|execute_|ctl_reg_sys_hilo[0]~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~9 , z80_|execute_|ctl_reg_out_lo~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~11 , z80_|execute_|ctl_reg_sys_hilo[0]~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~36 , z80_|execute_|ctl_reg_sys_hilo[1]~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~12 , z80_|execute_|ctl_reg_sys_hilo[0]~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~29 , z80_|execute_|ctl_reg_sys_hilo[0]~29, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_63 , z80_|reg_file_|SYNTHESIZED_WIRE_63, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[4] , z80_|reg_file_|b2v_latch_ir_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_62 , z80_|reg_file_|SYNTHESIZED_WIRE_62, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~14 , z80_|execute_|ctl_al_we~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~1 , z80_|execute_|ctl_sw_4d~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~5 , z80_|execute_|ctl_alu_oe~5, spectrum, 1 +instance = comp, \z80_|execute_|setM1~47 , z80_|execute_|setM1~47, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~0 , z80_|execute_|ctl_sw_4d~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~4 , z80_|execute_|ctl_sw_4d~4, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~8 , z80_|execute_|fMRead~8, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~9 , z80_|execute_|fMRead~9, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~10 , z80_|execute_|fMRead~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~2 , z80_|execute_|ctl_sw_4d~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 , z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal4~0 , z80_|pla_decode_|Equal4~0, spectrum, 1 +instance = comp, \z80_|execute_|setM1~41 , z80_|execute_|setM1~41, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal2~1 , z80_|pla_decode_|Equal2~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 , z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~18 , z80_|execute_|ctl_reg_gp_hilo[1]~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~4 , z80_|execute_|ctl_sw_1d~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~3 , z80_|execute_|ctl_sw_4d~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~11 , z80_|execute_|ctl_reg_sel_wz~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~12 , z80_|execute_|ctl_reg_sel_wz~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~5 , z80_|execute_|ctl_sw_4d~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~6 , z80_|execute_|ctl_sw_4d~6, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_pc~4 , z80_|reg_control_|reg_sel_pc~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~16 , z80_|execute_|ctl_reg_sel_pc~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~17 , z80_|execute_|ctl_reg_sel_pc~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~19 , z80_|execute_|ctl_reg_sel_pc~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~14 , z80_|execute_|ctl_reg_sel_pc~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~15 , z80_|execute_|ctl_reg_sel_pc~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~1 , z80_|execute_|ctl_sw_4u~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~18 , z80_|execute_|ctl_reg_sel_pc~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~19 , z80_|execute_|ctl_reg_sel_wz~19, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_pc~3 , z80_|reg_control_|reg_sel_pc~3, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_pc , z80_|reg_control_|reg_sel_pc, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_74 , z80_|reg_file_|SYNTHESIZED_WIRE_74, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_75 , z80_|reg_file_|SYNTHESIZED_WIRE_75, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[4] , z80_|reg_file_|b2v_latch_pc_lo|latch[4], spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal1~6 , z80_|pla_decode_|Equal1~6, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_exx~2 , z80_|reg_control_|bank_exx~2, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_exx , z80_|reg_control_|bank_exx, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~20 , z80_|execute_|ctl_reg_gp_hilo[1]~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~1 , z80_|execute_|ctl_sw_2u~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~3 , z80_|execute_|ctl_alu_oe~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~4 , z80_|execute_|ctl_sw_2u~4, spectrum, 1 +instance = comp, \z80_|execute_|setM1~56 , z80_|execute_|setM1~56, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~5 , z80_|execute_|ctl_sw_2u~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~33 , z80_|execute_|ctl_reg_gp_sel[0]~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~34 , z80_|execute_|ctl_reg_gp_sel[0]~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 , z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~13 , z80_|execute_|ctl_state_alu~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~12 , z80_|execute_|ctl_flags_xy_we~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~24 , z80_|execute_|ctl_reg_gp_sel[0]~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~25 , z80_|execute_|ctl_reg_gp_sel[0]~25, spectrum, 1 instance = comp, \z80_|execute_|ctl_inc_cy~61 , z80_|execute_|ctl_inc_cy~61, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~62 , z80_|execute_|ctl_inc_cy~62, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~70 , z80_|execute_|ctl_inc_cy~70, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~85 , z80_|execute_|ctl_inc_cy~85, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[0]~3 , z80_|reg_file_|db_lo_as[0]~3, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[0] , z80_|address_latch_|abusz[0], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[0]~feeder , z80_|address_latch_|Q[0]~feeder, spectrum, 1 -instance = comp, \z80_|address_latch_|Q[0] , z80_|address_latch_|Q[0], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[1] , z80_|reg_file_|b2v_latch_ir_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[1] , z80_|reg_file_|b2v_latch_pc_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[1]~4 , z80_|reg_file_|db_lo_as[1]~4, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[1]~5 , z80_|reg_file_|db_lo_as[1]~5, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[1]~6 , z80_|reg_file_|db_lo_as[1]~6, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[1] , z80_|address_latch_|abusz[1], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[1] , z80_|address_latch_|Q[1], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[2]~9 , z80_|reg_file_|db_lo_as[2]~9, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[2] , z80_|address_latch_|abusz[2], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[2]~feeder , z80_|address_latch_|Q[2]~feeder, spectrum, 1 -instance = comp, \z80_|address_latch_|Q[2] , z80_|address_latch_|Q[2], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42, spectrum, 1 instance = comp, \z80_|execute_|ctl_inc_cy~86 , z80_|execute_|ctl_inc_cy~86, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~11 , z80_|execute_|ctl_inc_dec~11, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[3] , z80_|reg_file_|b2v_latch_af2_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[3] , z80_|reg_file_|b2v_latch_af_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~45 , z80_|reg_file_|gdfx_temp0[3]~45, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder , z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[3] , z80_|reg_file_|b2v_latch_ix_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[3] , z80_|reg_file_|b2v_latch_bc_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~48 , z80_|reg_file_|gdfx_temp0[3]~48, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[3] , z80_|reg_file_|b2v_latch_iy_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[3] , z80_|reg_file_|b2v_latch_sp_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~49 , z80_|reg_file_|gdfx_temp0[3]~49, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder , z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[3] , z80_|reg_file_|b2v_latch_wz_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] , z80_|reg_file_|b2v_latch_bc2_lo|latch[3], spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~87 , z80_|execute_|ctl_inc_cy~87, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~52 , z80_|execute_|ctl_bus_inc_oe~52, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~49 , z80_|execute_|ctl_bus_inc_oe~49, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~3 , z80_|execute_|ctl_reg_gp_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~26 , z80_|execute_|ctl_reg_gp_sel[1]~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~21 , z80_|execute_|ctl_reg_gp_hilo[1]~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~7 , z80_|execute_|ctl_alu_oe~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~8 , z80_|execute_|ctl_alu_oe~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~22 , z80_|execute_|ctl_reg_gp_hilo[1]~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_oe~0 , z80_|execute_|ctl_flags_oe~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_oe~1 , z80_|execute_|ctl_flags_oe~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_cpl~12 , z80_|execute_|ctl_flags_hf_cpl~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_cpl~8 , z80_|execute_|ctl_flags_hf_cpl~8, spectrum, 1 +instance = comp, \z80_|execute_|setM1~48 , z80_|execute_|setM1~48, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~2 , z80_|execute_|ctl_flags_cf2_sel_shift~2, spectrum, 1 +instance = comp, \z80_|execute_|nextM~2 , z80_|execute_|nextM~2, spectrum, 1 +instance = comp, \z80_|execute_|setM1~49 , z80_|execute_|setM1~49, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~12 , z80_|execute_|ctl_reg_in_hi~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~8 , z80_|execute_|ctl_sw_1d~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~23 , z80_|execute_|ctl_reg_gp_hilo[1]~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~27 , z80_|execute_|ctl_reg_gp_sel[0]~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~2 , z80_|execute_|ctl_sw_2u~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~28 , z80_|execute_|ctl_reg_gp_sel[0]~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~29 , z80_|execute_|ctl_reg_gp_sel[0]~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~30 , z80_|execute_|ctl_reg_gp_sel[0]~30, spectrum, 1 +instance = comp, \z80_|execute_|nextM~11 , z80_|execute_|nextM~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~0 , z80_|execute_|ctl_reg_use_sp~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~2 , z80_|execute_|ctl_reg_use_sp~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~3 , z80_|execute_|ctl_reg_use_sp~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~9 , z80_|execute_|ctl_sw_1d~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~13 , z80_|execute_|ctl_reg_gp_sel[0]~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~12 , z80_|execute_|ctl_reg_gp_sel[0]~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~15 , z80_|execute_|ctl_alu_shift_oe~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 , z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~19 , z80_|execute_|ctl_reg_gp_hilo[1]~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~49 , z80_|execute_|ctl_reg_gp_hilo[1]~49, spectrum, 1 +instance = comp, \z80_|execute_|setM1~30 , z80_|execute_|setM1~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~6 , z80_|execute_|ctl_reg_gp_sel[0]~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~14 , z80_|execute_|ctl_reg_gp_sel[0]~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~32 , z80_|execute_|ctl_reg_gp_sel[0]~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~35 , z80_|execute_|ctl_reg_gp_sel[0]~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 , z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~18 , z80_|execute_|ctl_reg_gp_sel[1]~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~19 , z80_|execute_|ctl_reg_gp_sel[1]~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~20 , z80_|execute_|ctl_reg_gp_sel[1]~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~21 , z80_|execute_|ctl_reg_gp_sel[1]~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~5 , z80_|execute_|ctl_reg_gp_sel[1]~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~37 , z80_|execute_|ctl_reg_gp_sel[1]~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~22 , z80_|execute_|ctl_reg_gp_sel[1]~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~23 , z80_|execute_|ctl_reg_gp_sel[1]~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~47 , z80_|execute_|ctl_reg_gp_hilo[1]~47, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~16 , z80_|execute_|ctl_reg_gp_sel[1]~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~17 , z80_|execute_|ctl_reg_gp_sel[1]~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~11 , z80_|execute_|ctl_reg_gp_sel[1]~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~36 , z80_|execute_|ctl_reg_gp_sel[1]~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~8 , z80_|execute_|ctl_reg_gp_sel[1]~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~9 , z80_|execute_|ctl_reg_gp_sel[1]~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~10 , z80_|execute_|ctl_reg_gp_sel[1]~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~15 , z80_|execute_|ctl_reg_gp_sel[1]~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~31 , z80_|execute_|ctl_reg_gp_sel[1]~31, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_de2~2 , z80_|reg_control_|reg_sel_de2~2, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_de2~4 , z80_|reg_control_|reg_sel_de2~4, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal2~2 , z80_|pla_decode_|Equal2~2, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_hl_de1~0 , z80_|reg_control_|bank_hl_de1~0, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_hl_de1 , z80_|reg_control_|bank_hl_de1, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_hl~0 , z80_|reg_control_|reg_sel_hl~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 , z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~50 , z80_|execute_|ctl_bus_inc_oe~50, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~2 , z80_|execute_|ctl_reg_gp_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~35 , z80_|execute_|ctl_reg_gp_hilo[1]~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~36 , z80_|execute_|ctl_reg_gp_hilo[1]~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~37 , z80_|execute_|ctl_reg_gp_hilo[1]~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~51 , z80_|execute_|ctl_reg_gp_hilo[0]~51, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~30 , z80_|execute_|ctl_reg_gp_hilo[0]~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~28 , z80_|execute_|ctl_reg_gp_hilo[0]~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~29 , z80_|execute_|ctl_reg_gp_hilo[0]~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 , z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~31 , z80_|execute_|ctl_reg_gp_hilo[0]~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 , z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~32 , z80_|execute_|ctl_reg_gp_hilo[0]~32, spectrum, 1 +instance = comp, \z80_|execute_|rsel3 , z80_|execute_|rsel3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~27 , z80_|execute_|ctl_reg_gp_hilo[0]~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~50 , z80_|execute_|ctl_reg_gp_hilo[0]~50, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~26 , z80_|execute_|ctl_reg_gp_hilo[0]~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~34 , z80_|execute_|ctl_reg_gp_hilo[0]~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~24 , z80_|execute_|ctl_reg_gp_hilo[1]~24, spectrum, 1 +instance = comp, \z80_|execute_|rsel0 , z80_|execute_|rsel0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~25 , z80_|execute_|ctl_reg_gp_hilo[0]~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~38 , z80_|execute_|ctl_reg_gp_hilo[0]~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 , z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~7 , z80_|execute_|ctl_reg_in_hi~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~6 , z80_|execute_|ctl_reg_gp_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~9 , z80_|execute_|ctl_reg_gp_we~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 , z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 , z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~10 , z80_|execute_|ctl_alu_sel_op2_neg~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~4 , z80_|execute_|ctl_reg_gp_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 , z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~5 , z80_|execute_|ctl_reg_gp_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~7 , z80_|execute_|ctl_reg_gp_we~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~2 , z80_|execute_|ctl_sw_4u~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~3 , z80_|execute_|ctl_sw_4u~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~8 , z80_|execute_|ctl_reg_gp_we~8, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_58 , z80_|reg_file_|SYNTHESIZED_WIRE_58, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_hl_de2~0 , z80_|reg_control_|bank_hl_de2~0, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_hl_de2 , z80_|reg_control_|bank_hl_de2, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_hl2~0 , z80_|reg_control_|reg_sel_hl2~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_54 , z80_|reg_file_|SYNTHESIZED_WIRE_54, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_55 , z80_|reg_file_|SYNTHESIZED_WIRE_55, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] , z80_|reg_file_|b2v_latch_hl2_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_59 , z80_|reg_file_|SYNTHESIZED_WIRE_59, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[4] , z80_|reg_file_|b2v_latch_hl_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~56 , z80_|reg_file_|gdfx_temp0[4]~56, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~1 , z80_|execute_|ctl_flags_sz_we~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~8 , z80_|execute_|ctl_reg_in_hi~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2 , z80_|execute_|ctl_reg_gp_sel_pla37npla28M3T1_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~9 , z80_|execute_|ctl_reg_in_hi~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 , z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_lo~8 , z80_|execute_|ctl_reg_in_lo~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~44 , z80_|execute_|ctl_alu_shift_oe~44, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~6 , z80_|execute_|ctl_sw_2d~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~7 , z80_|execute_|ctl_sw_2d~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~8 , z80_|execute_|ctl_sw_2d~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~16 , z80_|execute_|ctl_alu_shift_oe~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~10 , z80_|execute_|ctl_alu_op2_sel_bus~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~4 , z80_|execute_|ctl_sw_2d~4, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~18 , z80_|execute_|fMRead~18, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~19 , z80_|execute_|fMRead~19, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~20 , z80_|execute_|fMRead~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~6 , z80_|execute_|ctl_reg_in_hi~6, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~21 , z80_|execute_|fMRead~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~5 , z80_|execute_|ctl_sw_2d~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~9 , z80_|execute_|ctl_sw_2d~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~5 , z80_|execute_|ctl_sw_1d~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~6 , z80_|execute_|ctl_sw_1d~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~7 , z80_|execute_|ctl_sw_1d~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~41 , z80_|execute_|ctl_alu_op_low~41, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 , z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~6 , z80_|execute_|ctl_alu_op2_sel_bus~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~26 , z80_|execute_|ctl_alu_op_low~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~38 , z80_|execute_|ctl_alu_shift_oe~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~27 , z80_|execute_|ctl_alu_op_low~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 , z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~2 , z80_|execute_|ctl_flags_cf_cpl~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_sel_daa , z80_|execute_|ctl_flags_cf2_sel_daa, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~4 , z80_|execute_|ctl_alu_sel_op2_neg~4, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal61~2 , z80_|pla_decode_|Equal61~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~13 , z80_|execute_|ctl_alu_sel_op2_neg~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero~4 , z80_|execute_|ctl_alu_op1_sel_zero~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~12 , z80_|execute_|ctl_alu_core_hf~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~14 , z80_|execute_|ctl_alu_sel_op2_neg~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~3 , z80_|execute_|ctl_flags_sz_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~13 , z80_|execute_|ctl_flags_alu~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~14 , z80_|execute_|ctl_flags_alu~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~15 , z80_|execute_|ctl_flags_alu~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~1 , z80_|execute_|ctl_reg_use_sp~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~16 , z80_|execute_|ctl_alu_op_low~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~17 , z80_|execute_|ctl_flags_xy_we~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~4 , z80_|execute_|ctl_flags_sz_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 , z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~3 , z80_|execute_|ctl_alu_sel_op2_neg~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~39 , z80_|execute_|ctl_alu_op_low~39, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~16 , z80_|execute_|ctl_flags_alu~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~17 , z80_|execute_|ctl_flags_alu~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~23 , z80_|execute_|ctl_alu_op_low~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~18 , z80_|execute_|ctl_flags_alu~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~11 , z80_|execute_|ctl_flags_alu~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~0 , z80_|execute_|ctl_alu_core_R~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 , z80_|execute_|ctl_pf_sel_pla12M1T1_12~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~1 , z80_|execute_|ctl_alu_core_R~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~23 , z80_|execute_|ctl_flags_alu~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~12 , z80_|execute_|ctl_flags_alu~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~11 , z80_|execute_|ctl_alu_op2_sel_bus~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~6 , z80_|execute_|ctl_alu_oe~6, spectrum, 1 +instance = comp, \z80_|execute_|setM1~17 , z80_|execute_|setM1~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~22 , z80_|execute_|ctl_alu_op_low~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~6 , z80_|execute_|ctl_flags_xy_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~7 , z80_|execute_|ctl_flags_xy_we~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~2 , z80_|execute_|ctl_flags_sz_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~19 , z80_|execute_|ctl_flags_alu~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~16 , z80_|execute_|ctl_alu_sel_op2_neg~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 , z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~0, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~26 , z80_|execute_|fMRead~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~11 , z80_|execute_|ctl_flags_bus~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~12 , z80_|execute_|ctl_flags_bus~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~13 , z80_|execute_|ctl_flags_bus~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus , z80_|execute_|ctl_flags_bus, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~12 , z80_|execute_|ctl_alu_op2_sel_bus~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~7 , z80_|execute_|ctl_alu_op2_sel_bus~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~8 , z80_|execute_|ctl_alu_op2_sel_bus~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~18 , z80_|execute_|ctl_alu_op1_sel_bus~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~14 , z80_|execute_|ctl_alu_op1_sel_bus~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~8 , z80_|execute_|ctl_alu_op1_sel_bus~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~9 , z80_|execute_|ctl_alu_op1_sel_bus~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~15 , z80_|execute_|ctl_alu_op1_sel_bus~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~9 , z80_|execute_|ctl_alu_op2_sel_bus~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~40 , z80_|execute_|ctl_alu_shift_oe~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~24 , z80_|execute_|ctl_alu_op_low~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~25 , z80_|execute_|ctl_alu_op_low~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~17 , z80_|execute_|ctl_alu_op1_sel_bus~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~6 , z80_|execute_|ctl_alu_op1_sel_bus~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~7 , z80_|execute_|ctl_alu_op1_sel_bus~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~37 , z80_|execute_|ctl_alu_shift_oe~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~39 , z80_|execute_|ctl_alu_shift_oe~39, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~42 , z80_|execute_|ctl_alu_shift_oe~42, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~12 , z80_|execute_|ctl_alu_bs_oe~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~8 , z80_|execute_|ctl_alu_bs_oe~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~47 , z80_|execute_|ctl_alu_shift_oe~47, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~34 , z80_|execute_|ctl_alu_shift_oe~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~35 , z80_|execute_|ctl_alu_shift_oe~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~36 , z80_|execute_|ctl_alu_shift_oe~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~24 , z80_|execute_|ctl_alu_shift_oe~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~29 , z80_|execute_|ctl_alu_shift_oe~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~9 , z80_|execute_|ctl_alu_bs_oe~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe , z80_|execute_|ctl_alu_bs_oe, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~23 , z80_|execute_|ctl_alu_shift_oe~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~30 , z80_|execute_|ctl_alu_shift_oe~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~31 , z80_|execute_|ctl_alu_shift_oe~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~32 , z80_|execute_|ctl_alu_shift_oe~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~10 , z80_|execute_|ctl_alu_bs_oe~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~33 , z80_|execute_|ctl_alu_shift_oe~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~17 , z80_|execute_|ctl_alu_shift_oe~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~45 , z80_|execute_|ctl_alu_shift_oe~45, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~18 , z80_|execute_|ctl_alu_shift_oe~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~19 , z80_|execute_|ctl_alu_shift_oe~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~20 , z80_|execute_|ctl_alu_shift_oe~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~21 , z80_|execute_|ctl_alu_shift_oe~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~22 , z80_|execute_|ctl_alu_shift_oe~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~43 , z80_|execute_|ctl_alu_shift_oe~43, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~10 , z80_|execute_|ctl_flags_xy_we~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_we~2 , z80_|execute_|ctl_flags_cf_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~6 , z80_|execute_|ctl_alu_core_S~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~7 , z80_|execute_|ctl_alu_core_S~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~4 , z80_|execute_|ctl_alu_core_S~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~5 , z80_|execute_|ctl_alu_core_S~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~15 , z80_|execute_|ctl_alu_oe~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_res_oe~0 , z80_|execute_|ctl_alu_res_oe~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_res_oe~1 , z80_|execute_|ctl_alu_res_oe~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_res_oe~2 , z80_|execute_|ctl_alu_res_oe~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_oe~0 , z80_|execute_|ctl_alu_op2_oe~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_oe~0 , z80_|execute_|ctl_alu_op1_oe~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_oe~1 , z80_|execute_|ctl_alu_op1_oe~1, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~0 , z80_|alu_|db_high[3]~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_hi~8 , z80_|execute_|ctl_reg_out_hi~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 , z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~39 , z80_|execute_|ctl_reg_gp_hilo[1]~39, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~40 , z80_|execute_|ctl_reg_gp_hilo[1]~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~53 , z80_|execute_|ctl_reg_gp_hilo[1]~53, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~3 , z80_|execute_|ctl_sw_2u~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~52 , z80_|execute_|ctl_reg_gp_hilo[1]~52, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~6 , z80_|execute_|ctl_sw_2u~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~2 , z80_|execute_|ctl_reg_out_lo~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_hi~5 , z80_|execute_|ctl_reg_out_hi~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_hi~6 , z80_|execute_|ctl_reg_out_hi~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_hi~7 , z80_|execute_|ctl_reg_out_hi~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~45 , z80_|execute_|ctl_reg_gp_hilo[1]~45, spectrum, 1 instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~41 , z80_|execute_|ctl_reg_gp_hilo[1]~41, spectrum, 1 instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~42 , z80_|execute_|ctl_reg_gp_hilo[1]~42, spectrum, 1 instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~43 , z80_|execute_|ctl_reg_gp_hilo[1]~43, spectrum, 1 instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~44 , z80_|execute_|ctl_reg_gp_hilo[1]~44, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~45 , z80_|execute_|ctl_reg_gp_hilo[1]~45, spectrum, 1 instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~46 , z80_|execute_|ctl_reg_gp_hilo[1]~46, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_48 , z80_|reg_file_|SYNTHESIZED_WIRE_48, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_44 , z80_|reg_file_|SYNTHESIZED_WIRE_44, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_45 , z80_|reg_file_|SYNTHESIZED_WIRE_45, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[3] , z80_|reg_file_|b2v_latch_de2_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_49 , z80_|reg_file_|SYNTHESIZED_WIRE_49, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[3] , z80_|reg_file_|b2v_latch_de_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~40 , z80_|reg_file_|gdfx_temp1[3]~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~4 , z80_|execute_|ctl_reg_use_sp~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~5 , z80_|execute_|ctl_reg_use_sp~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~6 , z80_|execute_|ctl_reg_use_sp~6, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_af~0 , z80_|reg_control_|bank_af~0, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_af , z80_|reg_control_|bank_af, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_af~0 , z80_|reg_control_|reg_sel_af~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_33 , z80_|reg_file_|SYNTHESIZED_WIRE_33, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[3] , z80_|reg_file_|b2v_latch_af_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[3]~12 , z80_|reg_file_|b2v_latch_af_hi|db[3]~12, spectrum, 1 instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_52 , z80_|reg_file_|SYNTHESIZED_WIRE_52, spectrum, 1 instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_57 , z80_|reg_file_|SYNTHESIZED_WIRE_57, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[3] , z80_|reg_file_|b2v_latch_hl_hi|latch[3], spectrum, 1 instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_53 , z80_|reg_file_|SYNTHESIZED_WIRE_53, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] , z80_|reg_file_|b2v_latch_hl2_hi|latch[3], spectrum, 1 instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_56 , z80_|reg_file_|SYNTHESIZED_WIRE_56, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~41 , z80_|reg_file_|gdfx_temp1[3]~41, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_33 , z80_|reg_file_|SYNTHESIZED_WIRE_33, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[3] , z80_|reg_file_|b2v_latch_af_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 , z80_|reg_file_|b2v_latch_af_hi|db[3]~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~11 , z80_|execute_|ctl_reg_in_hi~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~12 , z80_|execute_|ctl_reg_in_hi~12, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_29 , z80_|reg_file_|SYNTHESIZED_WIRE_29, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[3] , z80_|reg_file_|b2v_latch_af2_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_28 , z80_|reg_file_|SYNTHESIZED_WIRE_28, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~44 , z80_|reg_file_|gdfx_temp1[3]~44, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~32 , z80_|reg_file_|gdfx_temp1[3]~32, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_de2~3 , z80_|reg_control_|reg_sel_de2~3, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_44 , z80_|reg_file_|SYNTHESIZED_WIRE_44, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_de~0 , z80_|reg_control_|reg_sel_de~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_48 , z80_|reg_file_|SYNTHESIZED_WIRE_48, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_45 , z80_|reg_file_|SYNTHESIZED_WIRE_45, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[3] , z80_|reg_file_|b2v_latch_de2_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_49 , z80_|reg_file_|SYNTHESIZED_WIRE_49, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[3] , z80_|reg_file_|b2v_latch_de_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~31 , z80_|reg_file_|gdfx_temp1[3]~31, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder , z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_iy~2 , z80_|reg_control_|reg_sel_iy~2, spectrum, 1 instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_69 , z80_|reg_file_|SYNTHESIZED_WIRE_69, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[3] , z80_|reg_file_|b2v_latch_iy_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 , z80_|reg_file_|SYNTHESIZED_WIRE_68~2, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 , z80_|reg_file_|SYNTHESIZED_WIRE_64~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_68 , z80_|reg_file_|SYNTHESIZED_WIRE_68, spectrum, 1 instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 , z80_|reg_file_|SYNTHESIZED_WIRE_69~2, spectrum, 1 instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 , z80_|reg_file_|SYNTHESIZED_WIRE_65~0, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[3] , z80_|reg_file_|b2v_latch_ix_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_68 , z80_|reg_file_|SYNTHESIZED_WIRE_68, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~43 , z80_|reg_file_|gdfx_temp1[3]~43, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 , z80_|reg_file_|SYNTHESIZED_WIRE_76~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 , z80_|reg_file_|SYNTHESIZED_WIRE_68~2, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 , z80_|reg_file_|SYNTHESIZED_WIRE_64~0, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~34 , z80_|reg_file_|gdfx_temp1[3]~34, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder , z80_|reg_file_|b2v_latch_sp_hi|latch[3]~feeder, spectrum, 1 instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 , z80_|reg_file_|SYNTHESIZED_WIRE_77~0, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[3] , z80_|reg_file_|b2v_latch_sp_hi|latch[3], spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~31 , z80_|execute_|ctl_reg_sys_hilo[1]~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~30 , z80_|execute_|ctl_reg_sys_hilo[1]~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~32 , z80_|execute_|ctl_reg_sys_hilo[1]~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~33 , z80_|execute_|ctl_reg_sys_hilo[1]~33, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_hi~0 , z80_|reg_control_|reg_sys_we_hi~0, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_hi , z80_|reg_control_|reg_sys_we_hi, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 , z80_|reg_file_|SYNTHESIZED_WIRE_76~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~15 , z80_|execute_|ctl_reg_sel_wz~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~4 , z80_|execute_|ctl_sw_4u~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~16 , z80_|execute_|ctl_reg_sel_wz~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~34 , z80_|execute_|ctl_reg_sys_hilo[1]~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~17 , z80_|execute_|ctl_reg_sel_wz~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~18 , z80_|execute_|ctl_reg_sel_wz~18, spectrum, 1 instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_81 , z80_|reg_file_|SYNTHESIZED_WIRE_81, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[3] , z80_|reg_file_|b2v_latch_wz_hi|latch[3], spectrum, 1 instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_80 , z80_|reg_file_|SYNTHESIZED_WIRE_80, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~45 , z80_|reg_file_|gdfx_temp1[3]~45, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~36 , z80_|reg_file_|gdfx_temp1[3]~36, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 , z80_|reg_file_|SYNTHESIZED_WIRE_40~0, spectrum, 1 instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 , z80_|reg_file_|SYNTHESIZED_WIRE_41~0, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[3] , z80_|reg_file_|b2v_latch_bc_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 , z80_|reg_file_|SYNTHESIZED_WIRE_36~0, spectrum, 1 instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 , z80_|reg_file_|SYNTHESIZED_WIRE_37~0, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] , z80_|reg_file_|b2v_latch_bc2_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 , z80_|reg_file_|SYNTHESIZED_WIRE_40~0, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~42 , z80_|reg_file_|gdfx_temp1[3]~42, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~46 , z80_|reg_file_|gdfx_temp1[3]~46, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~47 , z80_|reg_file_|gdfx_temp1[3]~47, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 , z80_|reg_file_|SYNTHESIZED_WIRE_36~0, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~33 , z80_|reg_file_|gdfx_temp1[3]~33, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_af2~0 , z80_|reg_control_|reg_sel_af2~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_28 , z80_|reg_file_|SYNTHESIZED_WIRE_28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~10 , z80_|execute_|ctl_reg_in_hi~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~11 , z80_|execute_|ctl_reg_in_hi~11, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_29 , z80_|reg_file_|SYNTHESIZED_WIRE_29, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[3] , z80_|reg_file_|b2v_latch_af2_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~35 , z80_|reg_file_|gdfx_temp1[3]~35, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~37 , z80_|reg_file_|gdfx_temp1[3]~37, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~38 , z80_|reg_file_|gdfx_temp1[3]~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~5 , z80_|execute_|ctl_sw_4u~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~6 , z80_|execute_|ctl_sw_4u~6, spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp1[0]~17 , z80_|reg_file_|gdfx_temp1[0]~17, spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp1[0]~18 , z80_|reg_file_|gdfx_temp1[0]~18, spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp1[0]~19 , z80_|reg_file_|gdfx_temp1[0]~19, spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp1[0]~16 , z80_|reg_file_|gdfx_temp1[0]~16, spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp1[0]~20 , z80_|reg_file_|gdfx_temp1[0]~20, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_73 , z80_|reg_file_|SYNTHESIZED_WIRE_73, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[1] , z80_|reg_file_|b2v_latch_pc_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[1] , z80_|reg_file_|b2v_latch_de2_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[1] , z80_|reg_file_|b2v_latch_de_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~8 , z80_|reg_file_|gdfx_temp1[1]~8, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[1] , z80_|reg_file_|b2v_latch_af_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 , z80_|reg_file_|b2v_latch_af_hi|db[1]~15, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[1] , z80_|reg_file_|b2v_latch_sp_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[1] , z80_|reg_file_|b2v_latch_wz_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~13 , z80_|reg_file_|gdfx_temp1[1]~13, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[1] , z80_|reg_file_|b2v_latch_af2_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~12 , z80_|reg_file_|gdfx_temp1[1]~12, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[1] , z80_|reg_file_|b2v_latch_bc_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] , z80_|reg_file_|b2v_latch_bc2_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~10 , z80_|reg_file_|gdfx_temp1[1]~10, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[1] , z80_|reg_file_|b2v_latch_ix_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder , z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[1] , z80_|reg_file_|b2v_latch_iy_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~11 , z80_|reg_file_|gdfx_temp1[1]~11, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~14 , z80_|reg_file_|gdfx_temp1[1]~14, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] , z80_|reg_file_|b2v_latch_hl2_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[1] , z80_|reg_file_|b2v_latch_hl_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~9 , z80_|reg_file_|gdfx_temp1[1]~9, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~15 , z80_|reg_file_|gdfx_temp1[1]~15, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~21 , z80_|reg_file_|gdfx_temp1[1]~21, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_60 , z80_|reg_file_|SYNTHESIZED_WIRE_60, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_61 , z80_|reg_file_|SYNTHESIZED_WIRE_61, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[1] , z80_|reg_file_|b2v_latch_ir_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sw_4d_hi~0 , z80_|reg_control_|reg_sw_4d_hi~0, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[1]~0 , z80_|reg_file_|db_hi_as[1]~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_72 , z80_|reg_file_|SYNTHESIZED_WIRE_72, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[1]~1 , z80_|reg_file_|db_hi_as[1]~1, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[0]~2 , z80_|reg_file_|db_hi_as[0]~2, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[0] , z80_|reg_file_|b2v_latch_pc_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] , z80_|reg_file_|b2v_latch_hl2_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[0] , z80_|reg_file_|b2v_latch_hl_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~23 , z80_|reg_file_|gdfx_temp1[0]~23, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~39 , z80_|reg_file_|gdfx_temp1[3]~39, spectrum, 1 +instance = comp, \z80_|alu_|db[3]~13 , z80_|alu_|db[3]~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~12 , z80_|execute_|ctl_sw_2d~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~10 , z80_|execute_|ctl_sw_2d~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~14 , z80_|execute_|ctl_sw_2d~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~11 , z80_|execute_|ctl_sw_2d~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~13 , z80_|execute_|ctl_sw_2d~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~5 , z80_|execute_|ctl_bus_db_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~9 , z80_|execute_|ctl_alu_oe~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~10 , z80_|execute_|ctl_alu_oe~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~7 , z80_|execute_|ctl_sw_2u~7, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_35 , z80_|alu_flags_|SYNTHESIZED_WIRE_35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~13 , z80_|execute_|ctl_flags_xy_we~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~14 , z80_|execute_|ctl_flags_xy_we~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~15 , z80_|execute_|ctl_flags_xy_we~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~5 , z80_|execute_|ctl_flags_sz_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~6 , z80_|execute_|ctl_flags_sz_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~7 , z80_|execute_|ctl_flags_sz_we~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~16 , z80_|execute_|ctl_flags_xy_we~16, spectrum, 1 +instance = comp, \z80_|alu_flags_|flags_xf , z80_|alu_flags_|flags_xf, spectrum, 1 +instance = comp, \z80_|execute_|setM1~50 , z80_|execute_|setM1~50, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_oe~2 , z80_|execute_|ctl_flags_oe~2, spectrum, 1 +instance = comp, \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 , z80_|alu_control_|SYNTHESIZED_WIRE_2~0, spectrum, 1 +instance = comp, \z80_|alu_control_|db[3]~34 , z80_|alu_control_|db[3]~34, spectrum, 1 +instance = comp, \z80_|sw1_|db_down[3]~3 , z80_|sw1_|db_down[3]~3, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 , z80_|reg_file_|SYNTHESIZED_WIRE_70~2, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 , z80_|reg_file_|SYNTHESIZED_WIRE_78~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_70 , z80_|reg_file_|SYNTHESIZED_WIRE_70, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 , z80_|reg_file_|SYNTHESIZED_WIRE_71~2, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 , z80_|reg_file_|SYNTHESIZED_WIRE_79~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[3] , z80_|reg_file_|b2v_latch_sp_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_71 , z80_|reg_file_|SYNTHESIZED_WIRE_71, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[3] , z80_|reg_file_|b2v_latch_iy_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~48 , z80_|reg_file_|gdfx_temp0[3]~48, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_30 , z80_|reg_file_|SYNTHESIZED_WIRE_30, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_34 , z80_|reg_file_|SYNTHESIZED_WIRE_34, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_31 , z80_|reg_file_|SYNTHESIZED_WIRE_31, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[3] , z80_|reg_file_|b2v_latch_af2_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder , z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_35 , z80_|reg_file_|SYNTHESIZED_WIRE_35, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[3] , z80_|reg_file_|b2v_latch_af_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~44 , z80_|reg_file_|gdfx_temp0[3]~44, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_82 , z80_|reg_file_|SYNTHESIZED_WIRE_82, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 , z80_|reg_file_|SYNTHESIZED_WIRE_38~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 , z80_|reg_file_|SYNTHESIZED_WIRE_39~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] , z80_|reg_file_|b2v_latch_bc2_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~45 , z80_|reg_file_|gdfx_temp0[3]~45, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_83 , z80_|reg_file_|SYNTHESIZED_WIRE_83, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[3] , z80_|reg_file_|b2v_latch_wz_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~46 , z80_|reg_file_|gdfx_temp0[3]~46, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 , z80_|reg_file_|SYNTHESIZED_WIRE_67~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[3] , z80_|reg_file_|b2v_latch_ix_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 , z80_|reg_file_|SYNTHESIZED_WIRE_66~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 , z80_|reg_file_|SYNTHESIZED_WIRE_43~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[3] , z80_|reg_file_|b2v_latch_bc_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 , z80_|reg_file_|SYNTHESIZED_WIRE_42~0, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~47 , z80_|reg_file_|gdfx_temp0[3]~47, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~49 , z80_|reg_file_|gdfx_temp0[3]~49, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_50 , z80_|reg_file_|SYNTHESIZED_WIRE_50, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_46 , z80_|reg_file_|SYNTHESIZED_WIRE_46, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_47 , z80_|reg_file_|SYNTHESIZED_WIRE_47, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[3] , z80_|reg_file_|b2v_latch_de2_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder , z80_|reg_file_|b2v_latch_de_lo|latch[3]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_51 , z80_|reg_file_|SYNTHESIZED_WIRE_51, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[3] , z80_|reg_file_|b2v_latch_de_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~42 , z80_|reg_file_|gdfx_temp0[3]~42, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] , z80_|reg_file_|b2v_latch_hl2_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[3] , z80_|reg_file_|b2v_latch_hl_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~43 , z80_|reg_file_|gdfx_temp0[3]~43, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~50 , z80_|reg_file_|gdfx_temp0[3]~50, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~91 , z80_|reg_file_|gdfx_temp0[0]~91, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~18 , z80_|reg_file_|gdfx_temp0[0]~18, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~19 , z80_|reg_file_|gdfx_temp0[0]~19, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~20 , z80_|reg_file_|gdfx_temp0[0]~20, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~21 , z80_|reg_file_|gdfx_temp0[0]~21, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[3] , z80_|reg_file_|b2v_latch_ir_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[3] , z80_|reg_file_|b2v_latch_pc_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[3]~10 , z80_|reg_file_|db_lo_as[3]~10, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[3]~11 , z80_|reg_file_|db_lo_as[3]~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 , z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~42 , z80_|execute_|ctl_bus_inc_oe~42, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~43 , z80_|execute_|ctl_bus_inc_oe~43, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~88 , z80_|execute_|ctl_inc_cy~88, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~41 , z80_|execute_|ctl_bus_inc_oe~41, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~38 , z80_|execute_|ctl_bus_inc_oe~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~39 , z80_|execute_|ctl_bus_inc_oe~39, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~36 , z80_|execute_|ctl_bus_inc_oe~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~37 , z80_|execute_|ctl_bus_inc_oe~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~47 , z80_|execute_|ctl_bus_inc_oe~47, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~48 , z80_|execute_|ctl_bus_inc_oe~48, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~46 , z80_|execute_|ctl_bus_inc_oe~46, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~40 , z80_|execute_|ctl_bus_inc_oe~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~44 , z80_|execute_|ctl_bus_inc_oe~44, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~6 , z80_|execute_|ctl_inc_dec~6, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[0]~2 , z80_|reg_file_|db_lo_as[0]~2, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~25 , z80_|execute_|pc_inc_hold~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~67 , z80_|execute_|ctl_inc_cy~67, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 , z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~64 , z80_|execute_|ctl_inc_cy~64, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~65 , z80_|execute_|ctl_inc_cy~65, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~63 , z80_|execute_|ctl_inc_cy~63, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~66 , z80_|execute_|ctl_inc_cy~66, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~68 , z80_|execute_|ctl_inc_cy~68, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~58 , z80_|execute_|ctl_inc_cy~58, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~59 , z80_|execute_|ctl_inc_cy~59, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~60 , z80_|execute_|ctl_inc_cy~60, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~57 , z80_|execute_|ctl_inc_cy~57, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~62 , z80_|execute_|ctl_inc_cy~62, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~18 , z80_|execute_|pc_inc_hold~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 , z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~17 , z80_|execute_|pc_inc_hold~17, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~19 , z80_|execute_|pc_inc_hold~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 , z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~20 , z80_|execute_|pc_inc_hold~20, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~36 , z80_|execute_|pc_inc_hold~36, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~15 , z80_|execute_|pc_inc_hold~15, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~16 , z80_|execute_|pc_inc_hold~16, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~21 , z80_|execute_|pc_inc_hold~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~69 , z80_|execute_|ctl_inc_cy~69, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~52 , z80_|execute_|ctl_inc_cy~52, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 , z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~34 , z80_|execute_|pc_inc_hold~34, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~22 , z80_|execute_|pc_inc_hold~22, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~23 , z80_|execute_|pc_inc_hold~23, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~35 , z80_|execute_|pc_inc_hold~35, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~24 , z80_|execute_|pc_inc_hold~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~53 , z80_|execute_|ctl_inc_cy~53, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~54 , z80_|execute_|ctl_inc_cy~54, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~74 , z80_|execute_|ctl_inc_cy~74, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~75 , z80_|execute_|ctl_inc_cy~75, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~73 , z80_|execute_|ctl_inc_cy~73, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~76 , z80_|execute_|ctl_inc_cy~76, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~95 , z80_|execute_|ctl_inc_cy~95, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~72 , z80_|execute_|ctl_inc_cy~72, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~27 , z80_|execute_|pc_inc_hold~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~77 , z80_|execute_|ctl_inc_cy~77, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~78 , z80_|execute_|ctl_inc_cy~78, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~79 , z80_|execute_|ctl_inc_cy~79, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~70 , z80_|execute_|ctl_inc_cy~70, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~71 , z80_|execute_|ctl_inc_cy~71, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~80 , z80_|execute_|ctl_inc_cy~80, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~55 , z80_|execute_|ctl_inc_cy~55, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~26 , z80_|execute_|pc_inc_hold~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~56 , z80_|execute_|ctl_inc_cy~56, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~81 , z80_|execute_|ctl_inc_cy~81, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~85 , z80_|execute_|ctl_inc_cy~85, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~89 , z80_|execute_|ctl_inc_cy~89, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~90 , z80_|execute_|ctl_inc_cy~90, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~91 , z80_|execute_|ctl_inc_cy~91, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~83 , z80_|execute_|ctl_inc_cy~83, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~84 , z80_|execute_|ctl_inc_cy~84, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~100 , z80_|execute_|ctl_inc_cy~100, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~92 , z80_|execute_|ctl_inc_cy~92, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~28 , z80_|execute_|pc_inc_hold~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~82 , z80_|execute_|ctl_inc_cy~82, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~29 , z80_|execute_|pc_inc_hold~29, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~30 , z80_|execute_|pc_inc_hold~30, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~31 , z80_|execute_|pc_inc_hold~31, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~32 , z80_|execute_|pc_inc_hold~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~93 , z80_|execute_|ctl_inc_cy~93, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[0] , z80_|reg_file_|b2v_latch_af2_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[0] , z80_|reg_file_|b2v_latch_af_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~13 , z80_|reg_file_|gdfx_temp0[0]~13, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] , z80_|reg_file_|b2v_latch_bc2_lo|latch[0], spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_mask543_en~0 , z80_|execute_|ctl_sw_mask543_en~0, spectrum, 1 +instance = comp, \z80_|alu_control_|db[0]~10 , z80_|alu_control_|db[0]~10, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[0] , z80_|reg_file_|b2v_latch_de2_hi|latch[0], spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[0] , z80_|reg_file_|b2v_latch_de_hi|latch[0], spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp1[0]~22 , z80_|reg_file_|gdfx_temp1[0]~22, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] , z80_|reg_file_|b2v_latch_hl2_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder , z80_|reg_file_|b2v_latch_hl_hi|latch[0]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[0] , z80_|reg_file_|b2v_latch_hl_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~23 , z80_|reg_file_|gdfx_temp1[0]~23, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[0] , z80_|reg_file_|b2v_latch_af_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[0]~15 , z80_|reg_file_|b2v_latch_af_hi|db[0]~15, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder , z80_|reg_file_|b2v_latch_wz_hi|latch[0]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[0] , z80_|reg_file_|b2v_latch_wz_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[0] , z80_|reg_file_|b2v_latch_sp_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~27 , z80_|reg_file_|gdfx_temp1[0]~27, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[0] , z80_|reg_file_|b2v_latch_ix_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[0] , z80_|reg_file_|b2v_latch_iy_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~25 , z80_|reg_file_|gdfx_temp1[0]~25, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] , z80_|reg_file_|b2v_latch_bc2_hi|latch[0], spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[0] , z80_|reg_file_|b2v_latch_bc_hi|latch[0], spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp1[0]~24 , z80_|reg_file_|gdfx_temp1[0]~24, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[0] , z80_|reg_file_|b2v_latch_af2_hi|latch[0], spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp1[0]~26 , z80_|reg_file_|gdfx_temp1[0]~26, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder , z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[0] , z80_|reg_file_|b2v_latch_ix_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[0] , z80_|reg_file_|b2v_latch_iy_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~25 , z80_|reg_file_|gdfx_temp1[0]~25, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[0] , z80_|reg_file_|b2v_latch_sp_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[0] , z80_|reg_file_|b2v_latch_wz_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~27 , z80_|reg_file_|gdfx_temp1[0]~27, spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp1[0]~28 , z80_|reg_file_|gdfx_temp1[0]~28, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[0] , z80_|reg_file_|b2v_latch_af_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 , z80_|reg_file_|b2v_latch_af_hi|db[0]~16, spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp1[0]~29 , z80_|reg_file_|gdfx_temp1[0]~29, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~30 , z80_|reg_file_|gdfx_temp1[0]~30, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[0] , z80_|reg_file_|b2v_latch_ir_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[0]~4 , z80_|reg_file_|db_hi_as[0]~4, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[0]~5 , z80_|reg_file_|db_hi_as[0]~5, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[0]~6 , z80_|reg_file_|db_hi_as[0]~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~8 , z80_|execute_|ctl_inc_dec~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~9 , z80_|execute_|ctl_inc_dec~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~10 , z80_|execute_|ctl_inc_dec~10, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~7 , z80_|execute_|ctl_inc_dec~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~11 , z80_|execute_|ctl_inc_dec~11, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[2] , z80_|reg_file_|b2v_latch_af2_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[2] , z80_|reg_file_|b2v_latch_af_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~35 , z80_|reg_file_|gdfx_temp0[2]~35, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] , z80_|reg_file_|b2v_latch_hl2_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[2] , z80_|reg_file_|b2v_latch_hl_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~34 , z80_|reg_file_|gdfx_temp0[2]~34, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[2] , z80_|reg_file_|b2v_latch_de_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[2] , z80_|reg_file_|b2v_latch_de2_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~33 , z80_|reg_file_|gdfx_temp0[2]~33, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[2] , z80_|reg_file_|b2v_latch_wz_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|db[2]~0 , z80_|reg_file_|b2v_latch_wz_lo|db[2]~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[2] , z80_|reg_file_|b2v_latch_sp_lo|latch[2], spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~5 , z80_|execute_|ctl_flags_cf2_sel_shift~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~3 , z80_|execute_|ctl_flags_cf2_sel_shift~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~4 , z80_|execute_|ctl_flags_cf2_sel_shift~4, spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~9 , z80_|alu_|db_low[2]~9, spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~10 , z80_|alu_|db_low[2]~10, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~1 , z80_|alu_|db_high[3]~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~4 , z80_|execute_|ctl_flags_pf_we~4, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~10 , z80_|alu_flags_|DFFE_inst_latch_nf~10, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~17 , z80_|alu_flags_|DFFE_inst_latch_nf~17, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~18 , z80_|alu_flags_|DFFE_inst_latch_nf~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~38 , z80_|execute_|ctl_alu_op_low~38, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~11 , z80_|alu_flags_|DFFE_inst_latch_nf~11, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~12 , z80_|alu_flags_|DFFE_inst_latch_nf~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~8 , z80_|execute_|ctl_alu_core_S~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~2 , z80_|execute_|ctl_alu_core_R~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~3 , z80_|execute_|ctl_alu_core_R~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~4 , z80_|execute_|ctl_alu_core_R~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 , z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~10 , z80_|execute_|ctl_alu_op1_sel_bus~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~11 , z80_|execute_|ctl_alu_op1_sel_bus~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~12 , z80_|execute_|ctl_alu_op1_sel_bus~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~11 , z80_|execute_|ctl_alu_core_S~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~9 , z80_|execute_|ctl_alu_core_S~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S , z80_|execute_|ctl_alu_core_S, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal73~2 , z80_|pla_decode_|Equal73~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~5 , z80_|execute_|ctl_alu_core_R~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R , z80_|execute_|ctl_alu_core_R, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~28 , z80_|execute_|ctl_alu_op_low~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~29 , z80_|execute_|ctl_alu_op_low~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~30 , z80_|execute_|ctl_alu_op_low~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~31 , z80_|execute_|ctl_alu_op_low~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~32 , z80_|execute_|ctl_alu_op_low~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~40 , z80_|execute_|ctl_alu_op_low~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~33 , z80_|execute_|ctl_alu_op_low~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low , z80_|execute_|ctl_alu_op_low, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] , z80_|reg_file_|b2v_latch_hl2_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[7] , z80_|reg_file_|b2v_latch_hl_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~59 , z80_|reg_file_|gdfx_temp1[7]~59, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[7] , z80_|reg_file_|b2v_latch_de2_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[7] , z80_|reg_file_|b2v_latch_de_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~58 , z80_|reg_file_|gdfx_temp1[7]~58, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[7] , z80_|reg_file_|b2v_latch_af_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[7]~17 , z80_|reg_file_|b2v_latch_af_hi|db[7]~17, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[7] , z80_|reg_file_|b2v_latch_iy_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[7] , z80_|reg_file_|b2v_latch_ix_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~61 , z80_|reg_file_|gdfx_temp1[7]~61, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[7] , z80_|reg_file_|b2v_latch_af2_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~62 , z80_|reg_file_|gdfx_temp1[7]~62, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[7] , z80_|reg_file_|b2v_latch_sp_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[7] , z80_|reg_file_|b2v_latch_wz_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~63 , z80_|reg_file_|gdfx_temp1[7]~63, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[7] , z80_|reg_file_|b2v_latch_bc_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] , z80_|reg_file_|b2v_latch_bc2_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~60 , z80_|reg_file_|gdfx_temp1[7]~60, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~64 , z80_|reg_file_|gdfx_temp1[7]~64, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~65 , z80_|reg_file_|gdfx_temp1[7]~65, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_61 , z80_|reg_file_|SYNTHESIZED_WIRE_61, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[7] , z80_|reg_file_|b2v_latch_ir_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sw_4d_hi~0 , z80_|reg_control_|reg_sw_4d_hi~0, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[7]~16 , z80_|reg_file_|db_hi_as[7]~16, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_73 , z80_|reg_file_|SYNTHESIZED_WIRE_73, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[7] , z80_|reg_file_|b2v_latch_pc_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_72 , z80_|reg_file_|SYNTHESIZED_WIRE_72, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[7]~17 , z80_|reg_file_|db_hi_as[7]~17, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[1] , z80_|reg_file_|b2v_latch_pc_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[1] , z80_|reg_file_|b2v_latch_de2_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[1] , z80_|reg_file_|b2v_latch_de_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~8 , z80_|reg_file_|gdfx_temp1[1]~8, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] , z80_|reg_file_|b2v_latch_hl2_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[1] , z80_|reg_file_|b2v_latch_hl_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~9 , z80_|reg_file_|gdfx_temp1[1]~9, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[1] , z80_|reg_file_|b2v_latch_af_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[1]~14 , z80_|reg_file_|b2v_latch_af_hi|db[1]~14, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[1] , z80_|reg_file_|b2v_latch_bc_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] , z80_|reg_file_|b2v_latch_bc2_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~10 , z80_|reg_file_|gdfx_temp1[1]~10, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[1] , z80_|reg_file_|b2v_latch_wz_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[1] , z80_|reg_file_|b2v_latch_sp_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~13 , z80_|reg_file_|gdfx_temp1[1]~13, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[1] , z80_|reg_file_|b2v_latch_iy_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[1] , z80_|reg_file_|b2v_latch_ix_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~11 , z80_|reg_file_|gdfx_temp1[1]~11, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[1] , z80_|reg_file_|b2v_latch_af2_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~12 , z80_|reg_file_|gdfx_temp1[1]~12, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~14 , z80_|reg_file_|gdfx_temp1[1]~14, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~15 , z80_|reg_file_|gdfx_temp1[1]~15, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~21 , z80_|reg_file_|gdfx_temp1[1]~21, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[1] , z80_|reg_file_|b2v_latch_ir_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[1]~0 , z80_|reg_file_|db_hi_as[1]~0, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[1]~1 , z80_|reg_file_|db_hi_as[1]~1, spectrum, 1 instance = comp, \z80_|address_latch_|abusz[8] , z80_|address_latch_|abusz[8], spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~6 , z80_|execute_|ctl_al_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~9 , z80_|execute_|ctl_al_we~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~10 , z80_|execute_|ctl_al_we~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~7 , z80_|execute_|ctl_al_we~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~8 , z80_|execute_|ctl_al_we~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~11 , z80_|execute_|ctl_al_we~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~12 , z80_|execute_|ctl_al_we~12, spectrum, 1 instance = comp, \z80_|address_latch_|Q[8] , z80_|address_latch_|Q[8], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[7] , z80_|reg_file_|b2v_latch_ir_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] , z80_|reg_file_|b2v_latch_hl2_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[7] , z80_|reg_file_|b2v_latch_hl_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~82 , z80_|reg_file_|gdfx_temp0[7]~82, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[7] , z80_|reg_file_|b2v_latch_de2_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[7] , z80_|reg_file_|b2v_latch_de_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~81 , z80_|reg_file_|gdfx_temp0[7]~81, spectrum, 1 +instance = comp, \z80_|alu_control_|db[6]~12 , z80_|alu_control_|db[6]~12, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_34 , z80_|alu_flags_|SYNTHESIZED_WIRE_34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~8 , z80_|execute_|ctl_flags_sz_we~8, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_sf , z80_|alu_flags_|DFFE_inst_latch_sf, spectrum, 1 +instance = comp, \z80_|alu_control_|db[7]~18 , z80_|alu_control_|db[7]~18, spectrum, 1 +instance = comp, \z80_|alu_control_|db[7]~19 , z80_|alu_control_|db[7]~19, spectrum, 1 +instance = comp, \z80_|alu_control_|db[7]~20 , z80_|alu_control_|db[7]~20, spectrum, 1 +instance = comp, \z80_|alu_control_|db[7]~37 , z80_|alu_control_|db[7]~37, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[7] , z80_|reg_file_|b2v_latch_sp_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~87 , z80_|reg_file_|gdfx_temp0[7]~87, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[7] , z80_|reg_file_|b2v_latch_ix_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder , z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[7] , z80_|reg_file_|b2v_latch_iy_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~86 , z80_|reg_file_|gdfx_temp0[7]~86, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[7] , z80_|reg_file_|b2v_latch_wz_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[7] , z80_|reg_file_|b2v_latch_bc_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] , z80_|reg_file_|b2v_latch_bc2_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~84 , z80_|reg_file_|gdfx_temp0[7]~84, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~85 , z80_|reg_file_|gdfx_temp0[7]~85, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[7] , z80_|reg_file_|b2v_latch_af2_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[7] , z80_|reg_file_|b2v_latch_af_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~83 , z80_|reg_file_|gdfx_temp0[7]~83, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~88 , z80_|reg_file_|gdfx_temp0[7]~88, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~89 , z80_|reg_file_|gdfx_temp0[7]~89, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~90 , z80_|reg_file_|gdfx_temp0[7]~90, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[7] , z80_|reg_file_|b2v_latch_pc_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[7]~22 , z80_|reg_file_|db_lo_as[7]~22, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[7]~23 , z80_|reg_file_|db_lo_as[7]~23, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[7]~24 , z80_|reg_file_|db_lo_as[7]~24, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[7] , z80_|address_latch_|abusz[7], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[7] , z80_|address_latch_|Q[7], spectrum, 1 instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0, spectrum, 1 instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out, spectrum, 1 instance = comp, \z80_|reg_file_|db_hi_as[1]~3 , z80_|reg_file_|db_hi_as[1]~3, spectrum, 1 instance = comp, \z80_|address_latch_|abusz[9] , z80_|address_latch_|abusz[9], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[9]~feeder , z80_|address_latch_|Q[9]~feeder, spectrum, 1 instance = comp, \z80_|address_latch_|Q[9] , z80_|address_latch_|Q[9], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] , z80_|reg_file_|b2v_latch_hl2_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[2] , z80_|reg_file_|b2v_latch_hl_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~32 , z80_|reg_file_|gdfx_temp1[2]~32, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[2] , z80_|reg_file_|b2v_latch_ir_hi|latch[2], spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[2] , z80_|reg_file_|b2v_latch_af2_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~35 , z80_|reg_file_|gdfx_temp1[2]~35, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[2] , z80_|reg_file_|b2v_latch_ix_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder , z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[2] , z80_|reg_file_|b2v_latch_iy_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~34 , z80_|reg_file_|gdfx_temp1[2]~34, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder , z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[2] , z80_|reg_file_|b2v_latch_bc_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] , z80_|reg_file_|b2v_latch_bc2_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~33 , z80_|reg_file_|gdfx_temp1[2]~33, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~44 , z80_|reg_file_|gdfx_temp1[2]~44, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[2] , z80_|reg_file_|b2v_latch_sp_hi|latch[2], spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[2] , z80_|reg_file_|b2v_latch_wz_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~36 , z80_|reg_file_|gdfx_temp1[2]~36, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~37 , z80_|reg_file_|gdfx_temp1[2]~37, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[2] , z80_|reg_file_|b2v_latch_de_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~45 , z80_|reg_file_|gdfx_temp1[2]~45, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[2] , z80_|reg_file_|b2v_latch_bc_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] , z80_|reg_file_|b2v_latch_bc2_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~42 , z80_|reg_file_|gdfx_temp1[2]~42, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[2] , z80_|reg_file_|b2v_latch_iy_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[2] , z80_|reg_file_|b2v_latch_ix_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~43 , z80_|reg_file_|gdfx_temp1[2]~43, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~46 , z80_|reg_file_|gdfx_temp1[2]~46, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[2] , z80_|reg_file_|b2v_latch_de2_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~31 , z80_|reg_file_|gdfx_temp1[2]~31, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder , z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[2] , z80_|reg_file_|b2v_latch_de_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~40 , z80_|reg_file_|gdfx_temp1[2]~40, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[2] , z80_|reg_file_|b2v_latch_af_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 , z80_|reg_file_|b2v_latch_af_hi|db[2]~17, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~38 , z80_|reg_file_|gdfx_temp1[2]~38, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~39 , z80_|reg_file_|gdfx_temp1[2]~39, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[2] , z80_|reg_file_|b2v_latch_ir_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[2]~7 , z80_|reg_file_|db_hi_as[2]~7, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[2]~13 , z80_|reg_file_|b2v_latch_af_hi|db[2]~13, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[2] , z80_|reg_file_|b2v_latch_hl_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] , z80_|reg_file_|b2v_latch_hl2_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~41 , z80_|reg_file_|gdfx_temp1[2]~41, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~47 , z80_|reg_file_|gdfx_temp1[2]~47, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~48 , z80_|reg_file_|gdfx_temp1[2]~48, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[2]~10 , z80_|reg_file_|db_hi_as[2]~10, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[2] , z80_|reg_file_|b2v_latch_pc_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[2]~8 , z80_|reg_file_|db_hi_as[2]~8, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[2]~9 , z80_|reg_file_|db_hi_as[2]~9, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[2]~11 , z80_|reg_file_|db_hi_as[2]~11, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[2]~12 , z80_|reg_file_|db_hi_as[2]~12, spectrum, 1 instance = comp, \z80_|address_latch_|abusz[10] , z80_|address_latch_|abusz[10], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[10]~feeder , z80_|address_latch_|Q[10]~feeder, spectrum, 1 instance = comp, \z80_|address_latch_|Q[10] , z80_|address_latch_|Q[10], spectrum, 1 instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[11] , z80_|address_latch_|abusz[11], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[11] , z80_|address_latch_|Q[11], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[11] , z80_|address_latch_|b2v_inst_inc_dec|address[11], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[3] , z80_|reg_file_|b2v_latch_pc_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[3] , z80_|reg_file_|b2v_latch_ir_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[3]~10 , z80_|reg_file_|db_hi_as[3]~10, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[3]~11 , z80_|reg_file_|db_hi_as[3]~11, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[3]~12 , z80_|reg_file_|db_hi_as[3]~12, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~48 , z80_|reg_file_|gdfx_temp1[3]~48, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 , z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_low , z80_|execute_|ctl_alu_op1_sel_low, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[3] , z80_|alu_|b2v_op1_latch_mux_high|Q[3], spectrum, 1 -instance = comp, \z80_|alu_|op1_high[3] , z80_|alu_|op1_high[3], spectrum, 1 -instance = comp, \z80_|alu_|alu_op1[3]~3 , z80_|alu_|alu_op1[3]~3, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~6 , z80_|execute_|ctl_alu_op2_sel_bus~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~10 , z80_|execute_|ctl_alu_op2_sel_bus~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~0 , z80_|execute_|ctl_alu_core_R~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~5 , z80_|execute_|ctl_alu_op2_sel_bus~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~7 , z80_|execute_|ctl_alu_op2_sel_bus~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~8 , z80_|execute_|ctl_alu_op2_sel_bus~8, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 , z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 , z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|ena , z80_|alu_|b2v_op2_latch_mux_high|ena, spectrum, 1 -instance = comp, \z80_|alu_|op2_high[1] , z80_|alu_|op2_high[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] , z80_|reg_file_|b2v_latch_hl2_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[4] , z80_|reg_file_|b2v_latch_hl_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~50 , z80_|reg_file_|gdfx_temp1[4]~50, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[4] , z80_|reg_file_|b2v_latch_af_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[4]~16 , z80_|reg_file_|b2v_latch_af_hi|db[4]~16, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[4] , z80_|reg_file_|b2v_latch_de2_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[4] , z80_|reg_file_|b2v_latch_de_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~49 , z80_|reg_file_|gdfx_temp1[4]~49, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[4] , z80_|reg_file_|b2v_latch_bc_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] , z80_|reg_file_|b2v_latch_bc2_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~51 , z80_|reg_file_|gdfx_temp1[4]~51, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[4] , z80_|reg_file_|b2v_latch_iy_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[4] , z80_|reg_file_|b2v_latch_ix_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~52 , z80_|reg_file_|gdfx_temp1[4]~52, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[4] , z80_|reg_file_|b2v_latch_af2_hi|latch[4], spectrum, 1 +instance = comp, \z80_|alu_|db[4]~8 , z80_|alu_|db[4]~8, spectrum, 1 +instance = comp, \z80_|alu_|db[4]~10 , z80_|alu_|db[4]~10, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~53 , z80_|reg_file_|gdfx_temp1[4]~53, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[4] , z80_|reg_file_|b2v_latch_sp_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[4] , z80_|reg_file_|b2v_latch_wz_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~54 , z80_|reg_file_|gdfx_temp1[4]~54, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~55 , z80_|reg_file_|gdfx_temp1[4]~55, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~56 , z80_|reg_file_|gdfx_temp1[4]~56, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~57 , z80_|reg_file_|gdfx_temp1[4]~57, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[4] , z80_|reg_file_|b2v_latch_ir_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[4]~13 , z80_|reg_file_|db_hi_as[4]~13, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[4] , z80_|reg_file_|b2v_latch_pc_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[4]~14 , z80_|reg_file_|db_hi_as[4]~14, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[4]~15 , z80_|reg_file_|db_hi_as[4]~15, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[12] , z80_|address_latch_|abusz[12], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[12] , z80_|address_latch_|Q[12], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[5] , z80_|reg_file_|b2v_latch_pc_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[5] , z80_|reg_file_|b2v_latch_de2_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[5] , z80_|reg_file_|b2v_latch_de_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~76 , z80_|reg_file_|gdfx_temp1[5]~76, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] , z80_|reg_file_|b2v_latch_hl2_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[5] , z80_|reg_file_|b2v_latch_hl_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~77 , z80_|reg_file_|gdfx_temp1[5]~77, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder , z80_|reg_file_|b2v_latch_iy_hi|latch[5]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[5] , z80_|reg_file_|b2v_latch_iy_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[5] , z80_|reg_file_|b2v_latch_ix_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~79 , z80_|reg_file_|gdfx_temp1[5]~79, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[5] , z80_|reg_file_|b2v_latch_af2_hi|latch[5], spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~13 , z80_|execute_|ctl_alu_op1_sel_bus~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~16 , z80_|execute_|ctl_alu_op1_sel_bus~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero~5 , z80_|execute_|ctl_alu_op1_sel_zero~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero , z80_|execute_|ctl_alu_op1_sel_zero, spectrum, 1 instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[1] , z80_|alu_|b2v_op1_latch_mux_high|Q[1], spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|ena~0 , z80_|alu_|b2v_op1_latch_mux_high|ena~0, spectrum, 1 instance = comp, \z80_|alu_|op1_high[1] , z80_|alu_|op1_high[1], spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 , z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_zero , z80_|execute_|ctl_alu_op2_sel_zero, spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~18 , z80_|alu_|db_low[1]~18, spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~19 , z80_|alu_|db_low[1]~19, spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~16 , z80_|alu_|db_low[1]~16, spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~15 , z80_|alu_|db_low[1]~15, spectrum, 1 +instance = comp, \z80_|alu_|result_lo[1] , z80_|alu_|result_lo[1], spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~17 , z80_|alu_|db_low[1]~17, spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~20 , z80_|alu_|db_low[1]~20, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 , z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_low , z80_|execute_|ctl_alu_op1_sel_low, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 , z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|ena , z80_|alu_|b2v_op1_latch_mux_low|ena, spectrum, 1 +instance = comp, \z80_|alu_|op1_low[1] , z80_|alu_|op1_low[1], spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_lq , z80_|execute_|ctl_alu_op2_sel_lq, spectrum, 1 instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 , z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4, spectrum, 1 instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 , z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|ena , z80_|alu_|b2v_op2_latch_mux_high|ena, spectrum, 1 instance = comp, \z80_|alu_|op2_low[1] , z80_|alu_|op2_low[1], spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~6 , z80_|execute_|ctl_alu_sel_op2_neg~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~20 , z80_|execute_|ctl_alu_sel_op2_neg~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~12 , z80_|execute_|ctl_state_alu~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~18 , z80_|execute_|ctl_alu_core_hf~18, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal61~2 , z80_|pla_decode_|Equal61~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~16 , z80_|execute_|ctl_alu_sel_op2_neg~16, spectrum, 1 instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~17 , z80_|execute_|ctl_alu_sel_op2_neg~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~21 , z80_|execute_|ctl_alu_sel_op2_neg~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~15 , z80_|execute_|ctl_alu_sel_op2_neg~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~12 , z80_|execute_|ctl_alu_sel_op2_neg~12, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~20 , z80_|execute_|ctl_alu_core_hf~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~4 , z80_|execute_|ctl_flags_sz_we~4, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal71~2 , z80_|pla_decode_|Equal71~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~8 , z80_|alu_flags_|DFFE_inst_latch_nf~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~31 , z80_|execute_|ctl_alu_op_low~31, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~4 , z80_|alu_flags_|DFFE_inst_latch_nf~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 , z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~5 , z80_|alu_flags_|DFFE_inst_latch_nf~5, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~6 , z80_|alu_flags_|DFFE_inst_latch_nf~6, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal72~2 , z80_|pla_decode_|Equal72~2, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal73~2 , z80_|pla_decode_|Equal73~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_nf_we~0 , z80_|execute_|ctl_flags_nf_we~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_nf_we~1 , z80_|execute_|ctl_flags_nf_we~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_nf_we~2 , z80_|execute_|ctl_flags_nf_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_nf_we~3 , z80_|execute_|ctl_flags_nf_we~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~5 , z80_|execute_|ctl_flags_sz_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~6 , z80_|execute_|ctl_flags_sz_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_nf_we~4 , z80_|execute_|ctl_flags_nf_we~4, spectrum, 1 -instance = comp, \z80_|execute_|setM1~15 , z80_|execute_|setM1~15, spectrum, 1 -instance = comp, \z80_|execute_|setM1~16 , z80_|execute_|setM1~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~6 , z80_|execute_|ctl_flags_xy_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~7 , z80_|execute_|ctl_flags_xy_we~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~2 , z80_|execute_|ctl_flags_sz_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 , z80_|execute_|ctl_pf_sel_pla12M1T1_12~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~1 , z80_|execute_|ctl_alu_core_R~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~7 , z80_|execute_|ctl_flags_alu~7, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~8 , z80_|reg_control_|reg_sys_we_lo~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~8 , z80_|execute_|ctl_flags_alu~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~16 , z80_|execute_|ctl_flags_xy_we~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~12 , z80_|execute_|ctl_flags_alu~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~13 , z80_|execute_|ctl_flags_alu~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~14 , z80_|execute_|ctl_flags_alu~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~15 , z80_|execute_|ctl_flags_alu~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 , z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~19 , z80_|execute_|ctl_alu_sel_op2_neg~19, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~1, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~7 , z80_|alu_flags_|DFFE_inst_latch_nf~7, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~9 , z80_|alu_flags_|DFFE_inst_latch_nf~9, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~10 , z80_|alu_flags_|DFFE_inst_latch_nf~10, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf , z80_|alu_flags_|DFFE_inst_latch_nf, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~5 , z80_|execute_|ctl_alu_sel_op2_neg~5, spectrum, 1 instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~7 , z80_|execute_|ctl_alu_sel_op2_neg~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 , z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~10 , z80_|execute_|ctl_alu_sel_op2_neg~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 , z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~6 , z80_|execute_|ctl_alu_sel_op2_neg~6, spectrum, 1 instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~8 , z80_|execute_|ctl_alu_sel_op2_neg~8, spectrum, 1 instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~9 , z80_|execute_|ctl_alu_sel_op2_neg~9, spectrum, 1 instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~11 , z80_|execute_|ctl_alu_sel_op2_neg~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~14 , z80_|execute_|ctl_alu_sel_op2_neg~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~18 , z80_|execute_|ctl_alu_sel_op2_neg~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~12 , z80_|execute_|ctl_alu_sel_op2_neg~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~15 , z80_|execute_|ctl_alu_sel_op2_neg~15, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 , z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7 , z80_|alu_|b2v_op2_latch_mux_high|Q[1]~7, spectrum, 1 +instance = comp, \z80_|alu_|op2_high[1] , z80_|alu_|op2_high[1], spectrum, 1 instance = comp, \z80_|execute_|ctl_alu_sel_op2_high , z80_|execute_|ctl_alu_sel_op2_high, spectrum, 1 -instance = comp, \z80_|alu_|alu_op2[1]~1 , z80_|alu_|alu_op2[1]~1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~9 , z80_|execute_|ctl_alu_core_S~9, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 , z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 , z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8, spectrum, 1 -instance = comp, \z80_|alu_|op2_high[0] , z80_|alu_|op2_high[0], spectrum, 1 -instance = comp, \z80_|alu_|alu_op2[0]~3 , z80_|alu_|alu_op2[0]~3, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~12 , z80_|alu_flags_|DFFE_inst_latch_nf~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~8 , z80_|execute_|ctl_alu_core_S~8, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~21 , z80_|execute_|ctl_alu_core_hf~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~22 , z80_|execute_|ctl_alu_core_hf~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~19 , z80_|execute_|ctl_alu_core_hf~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~27 , z80_|execute_|ctl_alu_op_low~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~29 , z80_|execute_|ctl_alu_op_low~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~23 , z80_|execute_|ctl_alu_core_hf~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~37 , z80_|execute_|ctl_alu_core_hf~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~38 , z80_|execute_|ctl_alu_core_hf~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~24 , z80_|execute_|ctl_alu_core_hf~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~25 , z80_|execute_|ctl_alu_core_hf~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~26 , z80_|execute_|ctl_alu_core_hf~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~27 , z80_|execute_|ctl_alu_core_hf~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~28 , z80_|execute_|ctl_alu_core_hf~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~30 , z80_|execute_|ctl_alu_op_low~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~34 , z80_|execute_|ctl_alu_core_hf~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~32 , z80_|execute_|ctl_alu_core_hf~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~43 , z80_|execute_|ctl_alu_core_hf~43, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~33 , z80_|execute_|ctl_alu_core_hf~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~42 , z80_|execute_|ctl_alu_core_hf~42, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~35 , z80_|execute_|ctl_alu_core_hf~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~41 , z80_|execute_|ctl_alu_core_hf~41, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~30 , z80_|execute_|ctl_alu_core_hf~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~10 , z80_|execute_|ctl_mWrite~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~31 , z80_|execute_|ctl_alu_core_hf~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~44 , z80_|execute_|ctl_alu_core_hf~44, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~29 , z80_|execute_|ctl_alu_core_hf~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~36 , z80_|execute_|ctl_alu_core_hf~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~39 , z80_|execute_|ctl_alu_core_hf~39, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~40 , z80_|execute_|ctl_alu_core_hf~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_we~2 , z80_|execute_|ctl_flags_hf_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~2 , z80_|execute_|ctl_alu_core_R~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R , z80_|execute_|ctl_alu_core_R, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 , z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 , z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2, spectrum, 1 -instance = comp, \z80_|alu_|op2_high[3] , z80_|alu_|op2_high[3], spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 , z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 , z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3, spectrum, 1 -instance = comp, \z80_|alu_|op2_low[3] , z80_|alu_|op2_low[3], spectrum, 1 -instance = comp, \z80_|alu_|alu_op2[3]~2 , z80_|alu_|alu_op2[3]~2, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_hf~0 , z80_|alu_flags_|DFFE_inst_latch_hf~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_we~3 , z80_|execute_|ctl_flags_hf_we~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_we~4 , z80_|execute_|ctl_flags_hf_we~4, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_hf~1 , z80_|alu_flags_|DFFE_inst_latch_hf~1, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_hf , z80_|alu_flags_|DFFE_inst_latch_hf, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_cpl~11 , z80_|execute_|ctl_flags_hf_cpl~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_cpl~12 , z80_|execute_|ctl_flags_hf_cpl~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_cpl~13 , z80_|execute_|ctl_flags_hf_cpl~13, spectrum, 1 -instance = comp, \z80_|alu_flags_|flags_hf , z80_|alu_flags_|flags_hf, spectrum, 1 -instance = comp, \z80_|alu_control_|alu_core_cf_in~0 , z80_|alu_control_|alu_core_cf_in~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0, spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~23 , z80_|alu_|db_high[0]~23, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[12] , z80_|address_latch_|abusz[12], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[12]~feeder , z80_|address_latch_|Q[12]~feeder, spectrum, 1 -instance = comp, \z80_|address_latch_|Q[12] , z80_|address_latch_|Q[12], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[4] , z80_|reg_file_|b2v_latch_pc_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[4] , z80_|reg_file_|b2v_latch_ir_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[4]~16 , z80_|reg_file_|db_hi_as[4]~16, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[4]~17 , z80_|reg_file_|db_hi_as[4]~17, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[4]~18 , z80_|reg_file_|db_hi_as[4]~18, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[4] , z80_|reg_file_|b2v_latch_af2_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~62 , z80_|reg_file_|gdfx_temp1[4]~62, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[4] , z80_|reg_file_|b2v_latch_sp_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[4] , z80_|reg_file_|b2v_latch_wz_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~63 , z80_|reg_file_|gdfx_temp1[4]~63, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[4] , z80_|reg_file_|b2v_latch_ix_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[4] , z80_|reg_file_|b2v_latch_iy_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~61 , z80_|reg_file_|gdfx_temp1[4]~61, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder , z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[4] , z80_|reg_file_|b2v_latch_bc_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] , z80_|reg_file_|b2v_latch_bc2_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~60 , z80_|reg_file_|gdfx_temp1[4]~60, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~64 , z80_|reg_file_|gdfx_temp1[4]~64, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] , z80_|reg_file_|b2v_latch_hl2_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[4] , z80_|reg_file_|b2v_latch_hl_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~59 , z80_|reg_file_|gdfx_temp1[4]~59, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[4] , z80_|reg_file_|b2v_latch_de2_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[4] , z80_|reg_file_|b2v_latch_de_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~58 , z80_|reg_file_|gdfx_temp1[4]~58, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[4] , z80_|reg_file_|b2v_latch_af_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 , z80_|reg_file_|b2v_latch_af_hi|db[4]~19, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~65 , z80_|reg_file_|gdfx_temp1[4]~65, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~66 , z80_|reg_file_|gdfx_temp1[4]~66, spectrum, 1 -instance = comp, \z80_|alu_|db[4]~16 , z80_|alu_|db[4]~16, spectrum, 1 -instance = comp, \z80_|alu_|db[7]~26 , z80_|alu_|db[7]~26, spectrum, 1 -instance = comp, \z80_|alu_|db[4]~17 , z80_|alu_|db[4]~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~3 , z80_|execute_|ctl_flags_cf2_sel_shift~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~5 , z80_|execute_|ctl_flags_cf2_sel_shift~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~4 , z80_|execute_|ctl_flags_cf2_sel_shift~4, spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~24 , z80_|alu_|db_high[0]~24, spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~21 , z80_|alu_|db_high[0]~21, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[0] , z80_|alu_|b2v_op1_latch_mux_high|Q[0], spectrum, 1 -instance = comp, \z80_|alu_|op1_high[0] , z80_|alu_|op1_high[0], spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~22 , z80_|alu_|db_high[0]~22, spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~25 , z80_|alu_|db_high[0]~25, spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~26 , z80_|alu_|db_high[0]~26, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 , z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 , z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|ena , z80_|alu_|b2v_op1_latch_mux_low|ena, spectrum, 1 -instance = comp, \z80_|alu_|op1_low[0] , z80_|alu_|op1_low[0], spectrum, 1 -instance = comp, \z80_|alu_|alu_op1[0]~1 , z80_|alu_|alu_op1[0]~1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 , z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 , z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7, spectrum, 1 -instance = comp, \z80_|alu_|op2_low[0] , z80_|alu_|op2_low[0], spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0, spectrum, 1 -instance = comp, \z80_|alu_|alu_op1[1]~0 , z80_|alu_|alu_op1[1]~0, spectrum, 1 +instance = comp, \z80_|alu_|alu_op2[1]~2 , z80_|alu_|alu_op2[1]~2, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0, spectrum, 1 instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0, spectrum, 1 -instance = comp, \z80_|alu_|alu_op1[2]~2 , z80_|alu_|alu_op1[2]~2, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~5 , z80_|execute_|ctl_alu_core_R~5, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder , z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[7] , z80_|reg_file_|b2v_latch_bc_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] , z80_|reg_file_|b2v_latch_bc2_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~69 , z80_|reg_file_|gdfx_temp1[7]~69, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[7] , z80_|reg_file_|b2v_latch_ix_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[7] , z80_|reg_file_|b2v_latch_iy_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~70 , z80_|reg_file_|gdfx_temp1[7]~70, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[7] , z80_|reg_file_|b2v_latch_sp_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[7] , z80_|reg_file_|b2v_latch_wz_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~72 , z80_|reg_file_|gdfx_temp1[7]~72, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[7] , z80_|reg_file_|b2v_latch_af2_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~71 , z80_|reg_file_|gdfx_temp1[7]~71, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~73 , z80_|reg_file_|gdfx_temp1[7]~73, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[7] , z80_|reg_file_|b2v_latch_de2_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[7] , z80_|reg_file_|b2v_latch_de_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~67 , z80_|reg_file_|gdfx_temp1[7]~67, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[7] , z80_|reg_file_|b2v_latch_af_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 , z80_|reg_file_|b2v_latch_af_hi|db[7]~20, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] , z80_|reg_file_|b2v_latch_hl2_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[7] , z80_|reg_file_|b2v_latch_hl_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~68 , z80_|reg_file_|gdfx_temp1[7]~68, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~74 , z80_|reg_file_|gdfx_temp1[7]~74, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[7] , z80_|reg_file_|b2v_latch_ir_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[7]~19 , z80_|reg_file_|db_hi_as[7]~19, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[7] , z80_|reg_file_|b2v_latch_pc_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[7]~20 , z80_|reg_file_|db_hi_as[7]~20, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[5] , z80_|reg_file_|b2v_latch_wz_hi|latch[5], spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[2] , z80_|alu_|b2v_op1_latch_mux_high|Q[2], spectrum, 1 +instance = comp, \z80_|alu_|op1_high[2] , z80_|alu_|op1_high[2], spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 , z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 , z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3, spectrum, 1 +instance = comp, \z80_|alu_|op2_high[2] , z80_|alu_|op2_high[2], spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~10 , z80_|alu_|db_high[2]~10, spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~8 , z80_|alu_|db_high[2]~8, spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~9 , z80_|alu_|db_high[2]~9, spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~11 , z80_|alu_|db_high[2]~11, spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~12 , z80_|alu_|db_high[2]~12, spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~13 , z80_|alu_|db_high[2]~13, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] , z80_|reg_file_|b2v_latch_hl2_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[6] , z80_|reg_file_|b2v_latch_hl_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~68 , z80_|reg_file_|gdfx_temp1[6]~68, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[6] , z80_|reg_file_|b2v_latch_de2_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder , z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[6] , z80_|reg_file_|b2v_latch_de_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~67 , z80_|reg_file_|gdfx_temp1[6]~67, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[6] , z80_|reg_file_|b2v_latch_af_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[6]~18 , z80_|reg_file_|b2v_latch_af_hi|db[6]~18, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[6] , z80_|reg_file_|b2v_latch_wz_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[6] , z80_|reg_file_|b2v_latch_sp_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~72 , z80_|reg_file_|gdfx_temp1[6]~72, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[6] , z80_|reg_file_|b2v_latch_iy_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[6] , z80_|reg_file_|b2v_latch_ix_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~70 , z80_|reg_file_|gdfx_temp1[6]~70, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[6] , z80_|reg_file_|b2v_latch_bc_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] , z80_|reg_file_|b2v_latch_bc2_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~69 , z80_|reg_file_|gdfx_temp1[6]~69, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[6] , z80_|reg_file_|b2v_latch_af2_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~71 , z80_|reg_file_|gdfx_temp1[6]~71, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~73 , z80_|reg_file_|gdfx_temp1[6]~73, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~74 , z80_|reg_file_|gdfx_temp1[6]~74, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[14] , z80_|address_latch_|abusz[14], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[14] , z80_|address_latch_|Q[14], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[14] , z80_|address_latch_|b2v_inst_inc_dec|address[14], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[6] , z80_|reg_file_|b2v_latch_ir_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[6]~19 , z80_|reg_file_|db_hi_as[6]~19, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[6] , z80_|reg_file_|b2v_latch_pc_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[6]~20 , z80_|reg_file_|db_hi_as[6]~20, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[6]~21 , z80_|reg_file_|db_hi_as[6]~21, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~75 , z80_|reg_file_|gdfx_temp1[6]~75, spectrum, 1 +instance = comp, \z80_|alu_|db[6]~21 , z80_|alu_|db[6]~21, spectrum, 1 +instance = comp, \z80_|alu_|db[6]~22 , z80_|alu_|db[6]~22, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~16 , z80_|alu_|db_high[1]~16, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~17 , z80_|alu_|db_high[1]~17, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~14 , z80_|alu_|db_high[1]~14, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~15 , z80_|alu_|db_high[1]~15, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~18 , z80_|alu_|db_high[1]~18, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~19 , z80_|alu_|db_high[1]~19, spectrum, 1 +instance = comp, \z80_|alu_|db[5]~23 , z80_|alu_|db[5]~23, spectrum, 1 +instance = comp, \z80_|alu_|db[5]~24 , z80_|alu_|db[5]~24, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~80 , z80_|reg_file_|gdfx_temp1[5]~80, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[5] , z80_|reg_file_|b2v_latch_sp_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~54 , z80_|reg_file_|gdfx_temp1[5]~54, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[5] , z80_|reg_file_|b2v_latch_af2_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~53 , z80_|reg_file_|gdfx_temp1[5]~53, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder , z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[5] , z80_|reg_file_|b2v_latch_wz_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~81 , z80_|reg_file_|gdfx_temp1[5]~81, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[5] , z80_|reg_file_|b2v_latch_bc_hi|latch[5], spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] , z80_|reg_file_|b2v_latch_bc2_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~51 , z80_|reg_file_|gdfx_temp1[5]~51, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[5] , z80_|reg_file_|b2v_latch_iy_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[5] , z80_|reg_file_|b2v_latch_ix_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~52 , z80_|reg_file_|gdfx_temp1[5]~52, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~55 , z80_|reg_file_|gdfx_temp1[5]~55, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[5] , z80_|reg_file_|b2v_latch_de_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[5] , z80_|reg_file_|b2v_latch_de2_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~49 , z80_|reg_file_|gdfx_temp1[5]~49, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[5] , z80_|reg_file_|b2v_latch_hl_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] , z80_|reg_file_|b2v_latch_hl2_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~50 , z80_|reg_file_|gdfx_temp1[5]~50, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~78 , z80_|reg_file_|gdfx_temp1[5]~78, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~82 , z80_|reg_file_|gdfx_temp1[5]~82, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[5] , z80_|reg_file_|b2v_latch_af_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 , z80_|reg_file_|b2v_latch_af_hi|db[5]~14, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~56 , z80_|reg_file_|gdfx_temp1[5]~56, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~57 , z80_|reg_file_|gdfx_temp1[5]~57, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[5]~19 , z80_|reg_file_|b2v_latch_af_hi|db[5]~19, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~83 , z80_|reg_file_|gdfx_temp1[5]~83, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~84 , z80_|reg_file_|gdfx_temp1[5]~84, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[5] , z80_|reg_file_|b2v_latch_ir_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[5]~13 , z80_|reg_file_|db_hi_as[5]~13, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[5] , z80_|reg_file_|b2v_latch_pc_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[5]~14 , z80_|reg_file_|db_hi_as[5]~14, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[5]~15 , z80_|reg_file_|db_hi_as[5]~15, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[5]~22 , z80_|reg_file_|db_hi_as[5]~22, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[5]~23 , z80_|reg_file_|db_hi_as[5]~23, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[5]~24 , z80_|reg_file_|db_hi_as[5]~24, spectrum, 1 instance = comp, \z80_|address_latch_|abusz[13] , z80_|address_latch_|abusz[13], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[13]~feeder , z80_|address_latch_|Q[13]~feeder, spectrum, 1 instance = comp, \z80_|address_latch_|Q[13] , z80_|address_latch_|Q[13], spectrum, 1 instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0, spectrum, 1 instance = comp, \z80_|address_latch_|abusz[15] , z80_|address_latch_|abusz[15], spectrum, 1 instance = comp, \z80_|address_latch_|Q[15] , z80_|address_latch_|Q[15], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[14] , z80_|address_latch_|b2v_inst_inc_dec|address[14], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[6] , z80_|reg_file_|b2v_latch_pc_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[6] , z80_|reg_file_|b2v_latch_de2_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[6] , z80_|reg_file_|b2v_latch_de_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~76 , z80_|reg_file_|gdfx_temp1[6]~76, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[6] , z80_|reg_file_|b2v_latch_af2_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~80 , z80_|reg_file_|gdfx_temp1[6]~80, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[6] , z80_|reg_file_|b2v_latch_iy_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[6] , z80_|reg_file_|b2v_latch_ix_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~79 , z80_|reg_file_|gdfx_temp1[6]~79, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] , z80_|reg_file_|b2v_latch_bc2_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[6] , z80_|reg_file_|b2v_latch_bc_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~78 , z80_|reg_file_|gdfx_temp1[6]~78, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[6] , z80_|reg_file_|b2v_latch_sp_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[6] , z80_|reg_file_|b2v_latch_wz_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~81 , z80_|reg_file_|gdfx_temp1[6]~81, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~82 , z80_|reg_file_|gdfx_temp1[6]~82, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] , z80_|reg_file_|b2v_latch_hl2_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[6] , z80_|reg_file_|b2v_latch_hl_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~77 , z80_|reg_file_|gdfx_temp1[6]~77, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[6] , z80_|reg_file_|b2v_latch_af_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 , z80_|reg_file_|b2v_latch_af_hi|db[6]~21, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~83 , z80_|reg_file_|gdfx_temp1[6]~83, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~84 , z80_|reg_file_|gdfx_temp1[6]~84, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[6] , z80_|reg_file_|b2v_latch_ir_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[6]~22 , z80_|reg_file_|db_hi_as[6]~22, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[6]~23 , z80_|reg_file_|db_hi_as[6]~23, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[6]~24 , z80_|reg_file_|db_hi_as[6]~24, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[14] , z80_|address_latch_|abusz[14], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[14]~feeder , z80_|address_latch_|Q[14]~feeder, spectrum, 1 -instance = comp, \z80_|address_latch_|Q[14] , z80_|address_latch_|Q[14], spectrum, 1 instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16, spectrum, 1 instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[15] , z80_|address_latch_|b2v_inst_inc_dec|address[15], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[7]~21 , z80_|reg_file_|db_hi_as[7]~21, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~75 , z80_|reg_file_|gdfx_temp1[7]~75, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[7]~18 , z80_|reg_file_|db_hi_as[7]~18, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~66 , z80_|reg_file_|gdfx_temp1[7]~66, spectrum, 1 +instance = comp, \z80_|alu_|db[7]~19 , z80_|alu_|db[7]~19, spectrum, 1 instance = comp, \z80_|alu_|db[7]~20 , z80_|alu_|db[7]~20, spectrum, 1 -instance = comp, \z80_|alu_|db[7]~21 , z80_|alu_|db[7]~21, spectrum, 1 instance = comp, \z80_|alu_control_|b2v_inst_shift_mux|out~1 , z80_|alu_control_|b2v_inst_shift_mux|out~1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 , z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2 , z80_|alu_|b2v_op1_latch_mux_low|Q[3]~2, spectrum, 1 +instance = comp, \z80_|alu_|op1_low[3] , z80_|alu_|op1_low[3], spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[3] , z80_|alu_|b2v_op1_latch_mux_high|Q[3], spectrum, 1 +instance = comp, \z80_|alu_|op1_high[3] , z80_|alu_|op1_high[3], spectrum, 1 +instance = comp, \z80_|alu_|alu_op1[3]~0 , z80_|alu_|alu_op1[3]~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 , z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4 , z80_|alu_|b2v_op1_latch_mux_low|Q[2]~4, spectrum, 1 +instance = comp, \z80_|alu_|op1_low[2] , z80_|alu_|op1_low[2], spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2 , z80_|alu_|b2v_op2_latch_mux_low|Q[2]~2, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3 , z80_|alu_|b2v_op2_latch_mux_low|Q[2]~3, spectrum, 1 +instance = comp, \z80_|alu_|op2_low[2] , z80_|alu_|op2_low[2], spectrum, 1 +instance = comp, \z80_|alu_|alu_op2[2]~1 , z80_|alu_|alu_op2[2]~1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_8~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf~0 , z80_|alu_flags_|DFFE_inst_latch_cf~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf~1 , z80_|alu_flags_|DFFE_inst_latch_cf~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_we~3 , z80_|execute_|ctl_flags_cf_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_we~2 , z80_|execute_|ctl_flags_hf_we~2, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_cf_we~4 , z80_|execute_|ctl_flags_cf_we~4, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_cf_we~5 , z80_|execute_|ctl_flags_cf_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_we~3 , z80_|execute_|ctl_flags_cf_we~3, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_cf_we~6 , z80_|execute_|ctl_flags_cf_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_we~2 , z80_|execute_|ctl_flags_cf2_we~2, spectrum, 1 instance = comp, \z80_|execute_|ctl_flags_cf2_we~4 , z80_|execute_|ctl_flags_cf2_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_we~3 , z80_|execute_|ctl_flags_cf2_we~3, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf~1 , z80_|alu_flags_|DFFE_inst_latch_cf~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_we~6 , z80_|execute_|ctl_flags_cf2_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_we~5 , z80_|execute_|ctl_flags_cf2_we~5, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf~2 , z80_|alu_flags_|DFFE_inst_latch_cf~2, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf , z80_|alu_flags_|DFFE_inst_latch_cf, spectrum, 1 instance = comp, \z80_|alu_control_|b2v_inst_shift_mux|out~0 , z80_|alu_control_|b2v_inst_shift_mux|out~0, spectrum, 1 instance = comp, \z80_|alu_control_|b2v_inst_shift_mux|out~2 , z80_|alu_control_|b2v_inst_shift_mux|out~2, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~5 , z80_|alu_|db_high[3]~5, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~6 , z80_|alu_|db_high[3]~6, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~4 , z80_|alu_|db_high[3]~4, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~27 , z80_|alu_|db_high[3]~27, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~7 , z80_|alu_|db_high[3]~7, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~8 , z80_|alu_|db_high[3]~8, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 , z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4, spectrum, 1 -instance = comp, \z80_|alu_|op1_low[3] , z80_|alu_|op1_low[3], spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~9 , z80_|alu_|db_low[3]~9, spectrum, 1 -instance = comp, \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 , z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2, spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~10 , z80_|alu_|db_low[3]~10, spectrum, 1 -instance = comp, \z80_|alu_|result_lo[3] , z80_|alu_|result_lo[3], spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~7 , z80_|alu_|db_low[3]~7, spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~8 , z80_|alu_|db_low[3]~8, spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~11 , z80_|alu_|db_low[3]~11, spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~25 , z80_|alu_|db_low[3]~25, spectrum, 1 -instance = comp, \z80_|alu_|db[3]~10 , z80_|alu_|db[3]~10, spectrum, 1 -instance = comp, \z80_|alu_|db[3]~11 , z80_|alu_|db[3]~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~7 , z80_|execute_|ctl_sw_2u~7, spectrum, 1 -instance = comp, \z80_|execute_|setM1~49 , z80_|execute_|setM1~49, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_oe~2 , z80_|execute_|ctl_flags_oe~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_35 , z80_|alu_flags_|SYNTHESIZED_WIRE_35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~7 , z80_|execute_|ctl_flags_sz_we~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 , z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~13 , z80_|execute_|ctl_flags_xy_we~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~14 , z80_|execute_|ctl_flags_xy_we~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~15 , z80_|execute_|ctl_flags_xy_we~15, spectrum, 1 -instance = comp, \z80_|alu_flags_|flags_xf , z80_|alu_flags_|flags_xf, spectrum, 1 -instance = comp, \z80_|alu_control_|db[3]~33 , z80_|alu_control_|db[3]~33, spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~21 , z80_|alu_|db_low[0]~21, spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~22 , z80_|alu_|db_low[0]~22, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 , z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 , z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8, spectrum, 1 +instance = comp, \z80_|alu_|op1_low[0] , z80_|alu_|op1_low[0], spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~24 , z80_|alu_|db_low[0]~24, spectrum, 1 +instance = comp, \z80_|alu_|result_lo[0] , z80_|alu_|result_lo[0], spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~23 , z80_|alu_|db_low[0]~23, spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~25 , z80_|alu_|db_low[0]~25, spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~27 , z80_|alu_|db_low[0]~27, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 , z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 , z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7, spectrum, 1 +instance = comp, \z80_|alu_|op2_low[0] , z80_|alu_|op2_low[0], spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4 , z80_|alu_|b2v_op2_latch_mux_high|Q[0]~4, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5 , z80_|alu_|b2v_op2_latch_mux_high|Q[0]~5, spectrum, 1 +instance = comp, \z80_|alu_|op2_high[0] , z80_|alu_|op2_high[0], spectrum, 1 +instance = comp, \z80_|alu_|alu_op2[0]~3 , z80_|alu_|alu_op2[0]~3, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~34 , z80_|execute_|ctl_alu_op_low~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~36 , z80_|execute_|ctl_alu_op_low~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~35 , z80_|execute_|ctl_alu_op_low~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~13 , z80_|execute_|ctl_alu_core_hf~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~14 , z80_|execute_|ctl_alu_core_hf~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~15 , z80_|execute_|ctl_alu_core_hf~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~16 , z80_|execute_|ctl_alu_core_hf~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~17 , z80_|execute_|ctl_alu_core_hf~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~37 , z80_|execute_|ctl_alu_core_hf~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~38 , z80_|execute_|ctl_alu_core_hf~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~36 , z80_|execute_|ctl_alu_core_hf~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~23 , z80_|execute_|ctl_alu_core_hf~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~34 , z80_|execute_|ctl_alu_core_hf~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~29 , z80_|execute_|ctl_alu_core_hf~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~26 , z80_|execute_|ctl_alu_core_hf~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~35 , z80_|execute_|ctl_alu_core_hf~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~27 , z80_|execute_|ctl_alu_core_hf~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~28 , z80_|execute_|ctl_alu_core_hf~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~30 , z80_|execute_|ctl_alu_core_hf~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~37 , z80_|execute_|ctl_alu_op_low~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~24 , z80_|execute_|ctl_alu_core_hf~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~25 , z80_|execute_|ctl_alu_core_hf~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~31 , z80_|execute_|ctl_alu_core_hf~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~20 , z80_|execute_|ctl_alu_core_hf~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~21 , z80_|execute_|ctl_alu_core_hf~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~18 , z80_|execute_|ctl_alu_core_hf~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~19 , z80_|execute_|ctl_alu_core_hf~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~22 , z80_|execute_|ctl_alu_core_hf~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~32 , z80_|execute_|ctl_alu_core_hf~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~33 , z80_|execute_|ctl_alu_core_hf~33, spectrum, 1 +instance = comp, \z80_|alu_control_|alu_core_cf_in~0 , z80_|alu_control_|alu_core_cf_in~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0, spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~21 , z80_|alu_|db_high[0]~21, spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~22 , z80_|alu_|db_high[0]~22, spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~23 , z80_|alu_|db_high[0]~23, spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~20 , z80_|alu_|db_high[0]~20, spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~24 , z80_|alu_|db_high[0]~24, spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~25 , z80_|alu_|db_high[0]~25, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[0] , z80_|alu_|b2v_op1_latch_mux_high|Q[0], spectrum, 1 +instance = comp, \z80_|alu_|op1_high[0] , z80_|alu_|op1_high[0], spectrum, 1 +instance = comp, \z80_|alu_|alu_op1[0]~1 , z80_|alu_|alu_op1[0]~1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0, spectrum, 1 +instance = comp, \z80_|alu_|result_lo[2] , z80_|alu_|result_lo[2], spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~11 , z80_|alu_|db_low[2]~11, spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~12 , z80_|alu_|db_low[2]~12, spectrum, 1 +instance = comp, \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 , z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3, spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~13 , z80_|alu_|db_low[2]~13, spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~14 , z80_|alu_|db_low[2]~14, spectrum, 1 +instance = comp, \z80_|alu_|db[2]~11 , z80_|alu_|db[2]~11, spectrum, 1 +instance = comp, \z80_|alu_|db[2]~12 , z80_|alu_|db[2]~12, spectrum, 1 +instance = comp, \z80_|alu_control_|db[2]~28 , z80_|alu_control_|db[2]~28, spectrum, 1 +instance = comp, \z80_|alu_flags_|flags_hf2~0 , z80_|alu_flags_|flags_hf2~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|flags_hf2 , z80_|alu_flags_|flags_hf2, spectrum, 1 +instance = comp, \z80_|alu_control_|out[6]~0 , z80_|alu_control_|out[6]~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_66_oe , z80_|execute_|ctl_66_oe, spectrum, 1 +instance = comp, \z80_|alu_control_|db[2]~24 , z80_|alu_control_|db[2]~24, spectrum, 1 instance = comp, \z80_|execute_|ctl_reg_out_lo~3 , z80_|execute_|ctl_reg_out_lo~3, spectrum, 1 instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 , z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0, spectrum, 1 instance = comp, \z80_|execute_|ctl_reg_out_lo~4 , z80_|execute_|ctl_reg_out_lo~4, spectrum, 1 instance = comp, \z80_|execute_|ctl_reg_out_lo~5 , z80_|execute_|ctl_reg_out_lo~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~8 , z80_|execute_|ctl_reg_out_lo~8, spectrum, 1 -instance = comp, \z80_|sw1_|db_down[3]~1 , z80_|sw1_|db_down[3]~1, spectrum, 1 -instance = comp, \z80_|alu_control_|db[3]~34 , z80_|alu_control_|db[3]~34, spectrum, 1 -instance = comp, \z80_|alu_control_|db[3]~35 , z80_|alu_control_|db[3]~35, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~46 , z80_|reg_file_|gdfx_temp0[3]~46, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~47 , z80_|reg_file_|gdfx_temp0[3]~47, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~50 , z80_|reg_file_|gdfx_temp0[3]~50, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[3] , z80_|reg_file_|b2v_latch_hl_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] , z80_|reg_file_|b2v_latch_hl2_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~44 , z80_|reg_file_|gdfx_temp0[3]~44, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[3] , z80_|reg_file_|b2v_latch_de_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[3] , z80_|reg_file_|b2v_latch_de2_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~43 , z80_|reg_file_|gdfx_temp0[3]~43, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~51 , z80_|reg_file_|gdfx_temp0[3]~51, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~52 , z80_|reg_file_|gdfx_temp0[3]~52, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[3] , z80_|reg_file_|b2v_latch_pc_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[3]~10 , z80_|reg_file_|db_lo_as[3]~10, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[3] , z80_|reg_file_|b2v_latch_ir_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[3]~11 , z80_|reg_file_|db_lo_as[3]~11, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[3]~12 , z80_|reg_file_|db_lo_as[3]~12, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_ds[2]~1 , z80_|reg_file_|db_lo_ds[2]~1, spectrum, 1 +instance = comp, \z80_|alu_control_|db[2]~29 , z80_|alu_control_|db[2]~29, spectrum, 1 +instance = comp, \z80_|alu_control_|db[2]~30 , z80_|alu_control_|db[2]~30, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~38 , z80_|reg_file_|gdfx_temp0[2]~38, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[2] , z80_|reg_file_|b2v_latch_ix_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder , z80_|reg_file_|b2v_latch_iy_lo|latch[2]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[2] , z80_|reg_file_|b2v_latch_iy_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~37 , z80_|reg_file_|gdfx_temp0[2]~37, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder , z80_|reg_file_|b2v_latch_bc_lo|latch[2]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[2] , z80_|reg_file_|b2v_latch_bc_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] , z80_|reg_file_|b2v_latch_bc2_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~36 , z80_|reg_file_|gdfx_temp0[2]~36, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~39 , z80_|reg_file_|gdfx_temp0[2]~39, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~40 , z80_|reg_file_|gdfx_temp0[2]~40, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~41 , z80_|reg_file_|gdfx_temp0[2]~41, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[2] , z80_|reg_file_|b2v_latch_pc_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[2]~7 , z80_|reg_file_|db_lo_as[2]~7, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[2] , z80_|reg_file_|b2v_latch_ir_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[2]~8 , z80_|reg_file_|db_lo_as[2]~8, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[2]~9 , z80_|reg_file_|db_lo_as[2]~9, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[2] , z80_|address_latch_|abusz[2], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[2] , z80_|address_latch_|Q[2], spectrum, 1 instance = comp, \z80_|address_latch_|abusz[3] , z80_|address_latch_|abusz[3], spectrum, 1 instance = comp, \z80_|address_latch_|Q[3] , z80_|address_latch_|Q[3], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4, spectrum, 1 instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[4] , z80_|reg_file_|b2v_latch_de_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[4] , z80_|reg_file_|b2v_latch_de2_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~53 , z80_|reg_file_|gdfx_temp0[4]~53, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~54 , z80_|reg_file_|gdfx_temp0[4]~54, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[4] , z80_|reg_file_|b2v_latch_af2_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[4] , z80_|reg_file_|b2v_latch_af_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~58 , z80_|reg_file_|gdfx_temp0[4]~58, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[4] , z80_|reg_file_|b2v_latch_wz_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] , z80_|reg_file_|b2v_latch_bc2_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[4] , z80_|reg_file_|b2v_latch_bc_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~59 , z80_|reg_file_|gdfx_temp0[4]~59, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~60 , z80_|reg_file_|gdfx_temp0[4]~60, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] , z80_|reg_file_|b2v_latch_hl2_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[4] , z80_|reg_file_|b2v_latch_hl_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~57 , z80_|reg_file_|gdfx_temp0[4]~57, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[4] , z80_|reg_file_|b2v_latch_iy_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[4] , z80_|reg_file_|b2v_latch_sp_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~55 , z80_|reg_file_|gdfx_temp0[4]~55, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[4] , z80_|reg_file_|b2v_latch_ix_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~56 , z80_|reg_file_|gdfx_temp0[4]~56, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~61 , z80_|reg_file_|gdfx_temp0[4]~61, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~62 , z80_|reg_file_|gdfx_temp0[4]~62, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[4] , z80_|reg_file_|b2v_latch_pc_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[4]~13 , z80_|reg_file_|db_lo_as[4]~13, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[4] , z80_|reg_file_|b2v_latch_ir_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[4]~14 , z80_|reg_file_|db_lo_as[4]~14, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[4]~15 , z80_|reg_file_|db_lo_as[4]~15, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[4] , z80_|address_latch_|abusz[4], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[4] , z80_|address_latch_|Q[4], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44, spectrum, 1 instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[5] , z80_|reg_file_|b2v_latch_hl_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[5] , z80_|reg_file_|b2v_latch_ir_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[5] , z80_|reg_file_|b2v_latch_pc_lo|latch[5], spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] , z80_|reg_file_|b2v_latch_hl2_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~64 , z80_|reg_file_|gdfx_temp0[5]~64, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[5] , z80_|reg_file_|b2v_latch_de_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[5] , z80_|reg_file_|b2v_latch_de2_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[5] , z80_|reg_file_|b2v_latch_hl_lo|latch[5], spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp0[5]~63 , z80_|reg_file_|gdfx_temp0[5]~63, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[5] , z80_|reg_file_|b2v_latch_wz_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] , z80_|reg_file_|b2v_latch_bc2_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~66 , z80_|reg_file_|gdfx_temp0[5]~66, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~67 , z80_|reg_file_|gdfx_temp0[5]~67, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[5] , z80_|reg_file_|b2v_latch_af2_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[5] , z80_|reg_file_|b2v_latch_af_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~65 , z80_|reg_file_|gdfx_temp0[5]~65, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[5] , z80_|reg_file_|b2v_latch_sp_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder , z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[5] , z80_|reg_file_|b2v_latch_iy_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~69 , z80_|reg_file_|gdfx_temp0[5]~69, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder , z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[5] , z80_|reg_file_|b2v_latch_ix_lo|latch[5], spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[5] , z80_|reg_file_|b2v_latch_bc_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~67 , z80_|reg_file_|gdfx_temp0[5]~67, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] , z80_|reg_file_|b2v_latch_bc2_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~65 , z80_|reg_file_|gdfx_temp0[5]~65, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[5] , z80_|reg_file_|b2v_latch_wz_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~66 , z80_|reg_file_|gdfx_temp0[5]~66, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[5] , z80_|reg_file_|b2v_latch_iy_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[5] , z80_|reg_file_|b2v_latch_sp_lo|latch[5], spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp0[5]~68 , z80_|reg_file_|gdfx_temp0[5]~68, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[5] , z80_|reg_file_|b2v_latch_af2_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[5] , z80_|reg_file_|b2v_latch_af_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~64 , z80_|reg_file_|gdfx_temp0[5]~64, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~69 , z80_|reg_file_|gdfx_temp0[5]~69, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[5] , z80_|reg_file_|b2v_latch_de_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[5] , z80_|reg_file_|b2v_latch_de2_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~62 , z80_|reg_file_|gdfx_temp0[5]~62, spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp0[5]~70 , z80_|reg_file_|gdfx_temp0[5]~70, spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp0[5]~71 , z80_|reg_file_|gdfx_temp0[5]~71, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~72 , z80_|reg_file_|gdfx_temp0[5]~72, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[5] , z80_|reg_file_|b2v_latch_pc_lo|latch[5], spectrum, 1 instance = comp, \z80_|reg_file_|db_lo_as[5]~16 , z80_|reg_file_|db_lo_as[5]~16, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[5] , z80_|reg_file_|b2v_latch_ir_lo|latch[5], spectrum, 1 instance = comp, \z80_|reg_file_|db_lo_as[5]~17 , z80_|reg_file_|db_lo_as[5]~17, spectrum, 1 instance = comp, \z80_|reg_file_|db_lo_as[5]~18 , z80_|reg_file_|db_lo_as[5]~18, spectrum, 1 instance = comp, \z80_|address_latch_|abusz[5] , z80_|address_latch_|abusz[5], spectrum, 1 instance = comp, \z80_|address_latch_|Q[5] , z80_|address_latch_|Q[5], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~0, spectrum, 1 instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[6] , z80_|address_latch_|b2v_inst_inc_dec|address[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[6] , z80_|reg_file_|b2v_latch_ir_lo|latch[6], spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] , z80_|reg_file_|b2v_latch_hl2_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder , z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[6] , z80_|reg_file_|b2v_latch_hl_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~74 , z80_|reg_file_|gdfx_temp0[6]~74, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[6] , z80_|reg_file_|b2v_latch_de_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[6] , z80_|reg_file_|b2v_latch_de2_lo|latch[6], spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp0[6]~73 , z80_|reg_file_|gdfx_temp0[6]~73, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[6] , z80_|reg_file_|b2v_latch_ix_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder , z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[6] , z80_|reg_file_|b2v_latch_iy_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~78 , z80_|reg_file_|gdfx_temp0[6]~78, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[6] , z80_|reg_file_|b2v_latch_sp_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~79 , z80_|reg_file_|gdfx_temp0[6]~79, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[6] , z80_|reg_file_|b2v_latch_de2_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[6] , z80_|reg_file_|b2v_latch_de_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~72 , z80_|reg_file_|gdfx_temp0[6]~72, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[6] , z80_|reg_file_|b2v_latch_wz_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder , z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|db[6]~1 , z80_|reg_file_|b2v_latch_wz_lo|db[6]~1, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[6] , z80_|reg_file_|b2v_latch_sp_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~77 , z80_|reg_file_|gdfx_temp0[6]~77, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[6] , z80_|reg_file_|b2v_latch_bc_lo|latch[6], spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] , z80_|reg_file_|b2v_latch_bc2_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~76 , z80_|reg_file_|gdfx_temp0[6]~76, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~77 , z80_|reg_file_|gdfx_temp0[6]~77, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~80 , z80_|reg_file_|gdfx_temp0[6]~80, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[6] , z80_|reg_file_|b2v_latch_af2_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[6] , z80_|reg_file_|b2v_latch_af_lo|latch[6], spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp0[6]~75 , z80_|reg_file_|gdfx_temp0[6]~75, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~81 , z80_|reg_file_|gdfx_temp0[6]~81, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~82 , z80_|reg_file_|gdfx_temp0[6]~82, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[6] , z80_|reg_file_|b2v_latch_ix_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[6] , z80_|reg_file_|b2v_latch_iy_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~76 , z80_|reg_file_|gdfx_temp0[6]~76, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~78 , z80_|reg_file_|gdfx_temp0[6]~78, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[6] , z80_|reg_file_|b2v_latch_af2_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder , z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[6] , z80_|reg_file_|b2v_latch_af_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~74 , z80_|reg_file_|gdfx_temp0[6]~74, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~79 , z80_|reg_file_|gdfx_temp0[6]~79, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~80 , z80_|reg_file_|gdfx_temp0[6]~80, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[6] , z80_|reg_file_|b2v_latch_pc_lo|latch[6], spectrum, 1 instance = comp, \z80_|reg_file_|db_lo_as[6]~19 , z80_|reg_file_|db_lo_as[6]~19, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[6] , z80_|reg_file_|b2v_latch_ir_lo|latch[6], spectrum, 1 instance = comp, \z80_|reg_file_|db_lo_as[6]~20 , z80_|reg_file_|db_lo_as[6]~20, spectrum, 1 instance = comp, \z80_|reg_file_|db_lo_as[6]~21 , z80_|reg_file_|db_lo_as[6]~21, spectrum, 1 instance = comp, \z80_|address_latch_|abusz[6] , z80_|address_latch_|abusz[6], spectrum, 1 instance = comp, \z80_|address_latch_|Q[6] , z80_|address_latch_|Q[6], spectrum, 1 instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0, spectrum, 1 instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[7]~24 , z80_|reg_file_|db_lo_as[7]~24, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[7] , z80_|reg_file_|b2v_latch_de_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[7] , z80_|reg_file_|b2v_latch_de2_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~83 , z80_|reg_file_|gdfx_temp0[7]~83, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] , z80_|reg_file_|b2v_latch_hl2_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[7] , z80_|reg_file_|b2v_latch_hl_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~84 , z80_|reg_file_|gdfx_temp0[7]~84, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[7] , z80_|reg_file_|b2v_latch_ix_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder , z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[7] , z80_|reg_file_|b2v_latch_iy_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~88 , z80_|reg_file_|gdfx_temp0[7]~88, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[7] , z80_|reg_file_|b2v_latch_wz_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[7] , z80_|reg_file_|b2v_latch_bc_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] , z80_|reg_file_|b2v_latch_bc2_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~86 , z80_|reg_file_|gdfx_temp0[7]~86, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~87 , z80_|reg_file_|gdfx_temp0[7]~87, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[7] , z80_|reg_file_|b2v_latch_af2_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[7] , z80_|reg_file_|b2v_latch_af_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~85 , z80_|reg_file_|gdfx_temp0[7]~85, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[7] , z80_|reg_file_|b2v_latch_sp_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~89 , z80_|reg_file_|gdfx_temp0[7]~89, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~90 , z80_|reg_file_|gdfx_temp0[7]~90, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~91 , z80_|reg_file_|gdfx_temp0[7]~91, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~92 , z80_|reg_file_|gdfx_temp0[7]~92, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_ds[7]~0 , z80_|reg_file_|db_lo_ds[7]~0, spectrum, 1 -instance = comp, \z80_|interrupts_|im2 , z80_|interrupts_|im2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~12 , z80_|execute_|ctl_mRead~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_mask543_en~0 , z80_|execute_|ctl_sw_mask543_en~0, spectrum, 1 -instance = comp, \z80_|alu_control_|db[7]~17 , z80_|alu_control_|db[7]~17, spectrum, 1 -instance = comp, \z80_|alu_control_|db[7]~16 , z80_|alu_control_|db[7]~16, spectrum, 1 -instance = comp, \z80_|alu_control_|db[7]~18 , z80_|alu_control_|db[7]~18, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_34 , z80_|alu_flags_|SYNTHESIZED_WIRE_34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~8 , z80_|execute_|ctl_flags_sz_we~8, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_sf , z80_|alu_flags_|DFFE_inst_latch_sf, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal62~3 , z80_|pla_decode_|Equal62~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~5 , z80_|execute_|ctl_flags_pf_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~6 , z80_|execute_|ctl_flags_pf_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~7 , z80_|execute_|ctl_flags_pf_we~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~8 , z80_|execute_|ctl_flags_pf_we~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~9 , z80_|execute_|ctl_flags_pf_we~9, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~0 , z80_|alu_flags_|DFFE_inst_latch_pf~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~4 , z80_|alu_flags_|DFFE_inst_latch_pf~4, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~5 , z80_|alu_flags_|DFFE_inst_latch_pf~5, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~6 , z80_|alu_flags_|DFFE_inst_latch_pf~6, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instNonRep~0 , z80_|decode_state_|DFFE_instNonRep~0, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instNonRep~3 , z80_|decode_state_|DFFE_instNonRep~3, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[0] , z80_|reg_file_|b2v_latch_ir_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[0]~4 , z80_|reg_file_|db_hi_as[0]~4, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[0] , z80_|reg_file_|b2v_latch_pc_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[0]~5 , z80_|reg_file_|db_hi_as[0]~5, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[0]~6 , z80_|reg_file_|db_hi_as[0]~6, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~30 , z80_|reg_file_|gdfx_temp1[0]~30, spectrum, 1 +instance = comp, \z80_|alu_|db[0]~17 , z80_|alu_|db[0]~17, spectrum, 1 +instance = comp, \z80_|alu_|db[0]~18 , z80_|alu_|db[0]~18, spectrum, 1 +instance = comp, \z80_|sw2_|db_up[0]~0 , z80_|sw2_|db_up[0]~0, spectrum, 1 +instance = comp, \z80_|alu_control_|db[0]~11 , z80_|alu_control_|db[0]~11, spectrum, 1 +instance = comp, \z80_|alu_control_|db[0]~14 , z80_|alu_control_|db[0]~14, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~12 , z80_|reg_file_|gdfx_temp0[0]~12, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[0] , z80_|reg_file_|b2v_latch_hl_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|db[0]~2 , z80_|reg_file_|b2v_latch_hl_lo|db[0]~2, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] , z80_|reg_file_|b2v_latch_hl2_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[0] , z80_|reg_file_|b2v_latch_de2_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[0] , z80_|reg_file_|b2v_latch_de_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~10 , z80_|reg_file_|gdfx_temp0[0]~10, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~11 , z80_|reg_file_|gdfx_temp0[0]~11, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[0] , z80_|reg_file_|b2v_latch_wz_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[0] , z80_|reg_file_|b2v_latch_bc_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[0] , z80_|reg_file_|b2v_latch_ix_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~14 , z80_|reg_file_|gdfx_temp0[0]~14, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[0] , z80_|reg_file_|b2v_latch_iy_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[0] , z80_|reg_file_|b2v_latch_sp_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~15 , z80_|reg_file_|gdfx_temp0[0]~15, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~16 , z80_|reg_file_|gdfx_temp0[0]~16, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~17 , z80_|reg_file_|gdfx_temp0[0]~17, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~22 , z80_|reg_file_|gdfx_temp0[0]~22, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[0] , z80_|reg_file_|b2v_latch_pc_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[0]~0 , z80_|reg_file_|db_lo_as[0]~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[0] , z80_|reg_file_|b2v_latch_ir_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[0]~1 , z80_|reg_file_|db_lo_as[0]~1, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[0]~3 , z80_|reg_file_|db_lo_as[0]~3, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[0] , z80_|address_latch_|abusz[0], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[0] , z80_|address_latch_|Q[0], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[1] , z80_|reg_file_|b2v_latch_ir_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[1] , z80_|reg_file_|b2v_latch_de2_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[1] , z80_|reg_file_|b2v_latch_de_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~23 , z80_|reg_file_|gdfx_temp0[1]~23, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[1] , z80_|reg_file_|b2v_latch_ix_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[1] , z80_|reg_file_|b2v_latch_iy_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~28 , z80_|reg_file_|gdfx_temp0[1]~28, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[1] , z80_|reg_file_|b2v_latch_bc_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] , z80_|reg_file_|b2v_latch_bc2_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~26 , z80_|reg_file_|gdfx_temp0[1]~26, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[1] , z80_|reg_file_|b2v_latch_wz_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~27 , z80_|reg_file_|gdfx_temp0[1]~27, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[1] , z80_|reg_file_|b2v_latch_sp_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~29 , z80_|reg_file_|gdfx_temp0[1]~29, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~30 , z80_|reg_file_|gdfx_temp0[1]~30, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] , z80_|reg_file_|b2v_latch_hl2_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder , z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[1] , z80_|reg_file_|b2v_latch_hl_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~24 , z80_|reg_file_|gdfx_temp0[1]~24, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[1] , z80_|reg_file_|b2v_latch_af2_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder , z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[1] , z80_|reg_file_|b2v_latch_af_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~25 , z80_|reg_file_|gdfx_temp0[1]~25, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~31 , z80_|reg_file_|gdfx_temp0[1]~31, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~32 , z80_|reg_file_|gdfx_temp0[1]~32, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[1] , z80_|reg_file_|b2v_latch_pc_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[1]~4 , z80_|reg_file_|db_lo_as[1]~4, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[1]~5 , z80_|reg_file_|db_lo_as[1]~5, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[1]~6 , z80_|reg_file_|db_lo_as[1]~6, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[1] , z80_|address_latch_|abusz[1], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[1]~feeder , z80_|address_latch_|Q[1]~feeder, spectrum, 1 +instance = comp, \z80_|address_latch_|Q[1] , z80_|address_latch_|Q[1], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[3]~12 , z80_|reg_file_|db_lo_as[3]~12, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~51 , z80_|reg_file_|gdfx_temp0[3]~51, spectrum, 1 +instance = comp, \z80_|alu_control_|db[3]~35 , z80_|alu_control_|db[3]~35, spectrum, 1 +instance = comp, \z80_|alu_control_|db[3]~36 , z80_|alu_control_|db[3]~36, spectrum, 1 +instance = comp, \z80_|alu_|db[3]~14 , z80_|alu_|db[3]~14, spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~4 , z80_|alu_|db_low[3]~4, spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~5 , z80_|alu_|db_low[3]~5, spectrum, 1 +instance = comp, \z80_|alu_|result_lo[3] , z80_|alu_|result_lo[3], spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~6 , z80_|alu_|db_low[3]~6, spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~7 , z80_|alu_|db_low[3]~7, spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~8 , z80_|alu_|db_low[3]~8, spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~26 , z80_|alu_|db_low[3]~26, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0 , z80_|alu_|b2v_op2_latch_mux_low|Q[3]~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1 , z80_|alu_|b2v_op2_latch_mux_low|Q[3]~1, spectrum, 1 +instance = comp, \z80_|alu_|op2_low[3] , z80_|alu_|op2_low[3], spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 , z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 , z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1, spectrum, 1 +instance = comp, \z80_|alu_|op2_high[3] , z80_|alu_|op2_high[3], spectrum, 1 +instance = comp, \z80_|alu_|alu_op2[3]~0 , z80_|alu_|alu_op2[3]~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~1, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~4 , z80_|alu_|db_high[3]~4, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~2 , z80_|alu_|db_high[3]~2, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~3 , z80_|alu_|db_high[3]~3, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~5 , z80_|alu_|db_high[3]~5, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~6 , z80_|alu_|db_high[3]~6, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~7 , z80_|alu_|db_high[3]~7, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~14, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_nf_we~0 , z80_|execute_|ctl_flags_nf_we~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_nf_we~1 , z80_|execute_|ctl_flags_nf_we~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_nf_we~2 , z80_|execute_|ctl_flags_nf_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_nf_we~3 , z80_|execute_|ctl_flags_nf_we~3, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~14 , z80_|alu_flags_|DFFE_inst_latch_nf~14, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~13 , z80_|alu_flags_|DFFE_inst_latch_nf~13, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~15 , z80_|alu_flags_|DFFE_inst_latch_nf~15, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~16 , z80_|alu_flags_|DFFE_inst_latch_nf~16, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf , z80_|alu_flags_|DFFE_inst_latch_nf, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~3 , z80_|execute_|ctl_flags_cf_cpl~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~4 , z80_|execute_|ctl_flags_cf_cpl~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~5 , z80_|execute_|ctl_flags_cf_cpl~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_set~0 , z80_|execute_|ctl_flags_cf_set~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2 , z80_|execute_|ctl_reg_gp_hilo_nop3pla68M2T1_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~6 , z80_|execute_|ctl_flags_cf_cpl~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~7 , z80_|execute_|ctl_flags_cf_cpl~7, spectrum, 1 +instance = comp, \z80_|alu_control_|out[6]~1 , z80_|alu_control_|out[6]~1, spectrum, 1 +instance = comp, \z80_|alu_control_|out[6]~2 , z80_|alu_control_|out[6]~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~0 , z80_|alu_flags_|DFFE_inst_latch_cf2~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~1 , z80_|alu_flags_|DFFE_inst_latch_cf2~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~2 , z80_|alu_flags_|DFFE_inst_latch_cf2~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~3 , z80_|alu_flags_|DFFE_inst_latch_cf2~3, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2 , z80_|alu_flags_|DFFE_inst_latch_cf2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~10 , z80_|execute_|ctl_flags_use_cf2~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~11 , z80_|execute_|ctl_flags_use_cf2~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~8 , z80_|execute_|ctl_flags_use_cf2~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~9 , z80_|execute_|ctl_flags_use_cf2~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~12 , z80_|execute_|ctl_flags_use_cf2~12, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~11, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~17, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~21 , z80_|execute_|ctl_alu_op_low~21, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~13, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~16, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~18, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal64~0 , z80_|pla_decode_|Equal64~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~1 , z80_|execute_|ctl_flags_cf_cpl~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~6, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~7, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~3, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~0 , z80_|execute_|ctl_flags_cf_cpl~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~5, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~8, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~9, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~10, spectrum, 1 +instance = comp, \z80_|alu_flags_|flags_cf , z80_|alu_flags_|flags_cf, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_we~3 , z80_|execute_|ctl_flags_hf_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_we~4 , z80_|execute_|ctl_flags_hf_we~4, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_hf~0 , z80_|alu_flags_|DFFE_inst_latch_hf~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_hf~1 , z80_|alu_flags_|DFFE_inst_latch_hf~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_hf , z80_|alu_flags_|DFFE_inst_latch_hf, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_cpl~9 , z80_|execute_|ctl_flags_hf_cpl~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_cpl~10 , z80_|execute_|ctl_flags_hf_cpl~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_cpl~11 , z80_|execute_|ctl_flags_hf_cpl~11, spectrum, 1 +instance = comp, \z80_|alu_flags_|flags_hf , z80_|alu_flags_|flags_hf, spectrum, 1 +instance = comp, \z80_|alu_control_|db[4]~31 , z80_|alu_control_|db[4]~31, spectrum, 1 +instance = comp, \z80_|alu_control_|db[4]~32 , z80_|alu_control_|db[4]~32, spectrum, 1 +instance = comp, \z80_|alu_control_|db[4]~33 , z80_|alu_control_|db[4]~33, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[4] , z80_|reg_file_|b2v_latch_de2_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[4] , z80_|reg_file_|b2v_latch_de_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~52 , z80_|reg_file_|gdfx_temp0[4]~52, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~53 , z80_|reg_file_|gdfx_temp0[4]~53, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[4] , z80_|reg_file_|b2v_latch_ix_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[4] , z80_|reg_file_|b2v_latch_iy_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[4] , z80_|reg_file_|b2v_latch_sp_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~54 , z80_|reg_file_|gdfx_temp0[4]~54, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~55 , z80_|reg_file_|gdfx_temp0[4]~55, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[4] , z80_|reg_file_|b2v_latch_bc_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] , z80_|reg_file_|b2v_latch_bc2_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~58 , z80_|reg_file_|gdfx_temp0[4]~58, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[4] , z80_|reg_file_|b2v_latch_af2_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[4] , z80_|reg_file_|b2v_latch_af_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~57 , z80_|reg_file_|gdfx_temp0[4]~57, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[4] , z80_|reg_file_|b2v_latch_wz_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~59 , z80_|reg_file_|gdfx_temp0[4]~59, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~60 , z80_|reg_file_|gdfx_temp0[4]~60, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~61 , z80_|reg_file_|gdfx_temp0[4]~61, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[4]~13 , z80_|reg_file_|db_lo_as[4]~13, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[4]~14 , z80_|reg_file_|db_lo_as[4]~14, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[4]~15 , z80_|reg_file_|db_lo_as[4]~15, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[4] , z80_|address_latch_|abusz[4], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[4] , z80_|address_latch_|Q[4], spectrum, 1 instance = comp, \z80_|decode_state_|DFFE_instNonRep~2 , z80_|decode_state_|DFFE_instNonRep~2, spectrum, 1 instance = comp, \z80_|decode_state_|DFFE_instNonRep~1 , z80_|decode_state_|DFFE_instNonRep~1, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instNonRep~3 , z80_|decode_state_|DFFE_instNonRep~3, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instNonRep~0 , z80_|decode_state_|DFFE_instNonRep~0, spectrum, 1 instance = comp, \z80_|decode_state_|DFFE_instNonRep~4 , z80_|decode_state_|DFFE_instNonRep~4, spectrum, 1 instance = comp, \z80_|decode_state_|DFFE_instNonRep~5 , z80_|decode_state_|DFFE_instNonRep~5, spectrum, 1 instance = comp, \z80_|decode_state_|DFFE_instNonRep , z80_|decode_state_|DFFE_instNonRep, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~1 , z80_|alu_flags_|DFFE_inst_latch_pf~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal79~0 , z80_|pla_decode_|Equal79~0, spectrum, 1 +instance = comp, \z80_|interrupts_|DFFE_instIFF2~0 , z80_|interrupts_|DFFE_instIFF2~0, spectrum, 1 +instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_12 , z80_|interrupts_|SYNTHESIZED_WIRE_12, spectrum, 1 +instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl , z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl, spectrum, 1 +instance = comp, \z80_|interrupts_|DFFE_instIFF2 , z80_|interrupts_|DFFE_instIFF2, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~2 , z80_|alu_flags_|DFFE_inst_latch_pf~2, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~3 , z80_|alu_flags_|DFFE_inst_latch_pf~3, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~6 , z80_|alu_flags_|DFFE_inst_latch_pf~6, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~7 , z80_|alu_flags_|DFFE_inst_latch_pf~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel[1]~12 , z80_|execute_|ctl_pf_sel[1]~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel[0]~11 , z80_|execute_|ctl_pf_sel[0]~11, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~4 , z80_|alu_flags_|DFFE_inst_latch_pf~4, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~5 , z80_|alu_flags_|DFFE_inst_latch_pf~5, spectrum, 1 instance = comp, \z80_|alu_control_|DFFE_latch_pf_tmp , z80_|alu_control_|DFFE_latch_pf_tmp, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0, spectrum, 1 instance = comp, \z80_|alu_|alu_parity_out~0 , z80_|alu_|alu_parity_out~0, spectrum, 1 instance = comp, \z80_|alu_|alu_parity_out , z80_|alu_|alu_parity_out, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~7 , z80_|alu_flags_|DFFE_inst_latch_pf~7, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~8 , z80_|alu_flags_|DFFE_inst_latch_pf~8, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~0 , z80_|alu_flags_|DFFE_inst_latch_pf~0, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~9 , z80_|alu_flags_|DFFE_inst_latch_pf~9, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~10 , z80_|alu_flags_|DFFE_inst_latch_pf~10, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf , z80_|alu_flags_|DFFE_inst_latch_pf, spectrum, 1 -instance = comp, \z80_|alu_control_|sel[1]~0 , z80_|alu_control_|sel[1]~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 , z80_|alu_flags_|SYNTHESIZED_WIRE_11~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_12 , z80_|alu_flags_|SYNTHESIZED_WIRE_12, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_37~0, spectrum, 1 instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_11~0, spectrum, 1 instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_11~1, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_37~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_11 , z80_|alu_flags_|SYNTHESIZED_WIRE_11, spectrum, 1 instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_37~1, spectrum, 1 instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_39 , z80_|alu_flags_|SYNTHESIZED_WIRE_39, spectrum, 1 instance = comp, \z80_|alu_control_|b2v_inst_cond_mux|out~0 , z80_|alu_control_|b2v_inst_cond_mux|out~0, spectrum, 1 instance = comp, \z80_|alu_control_|b2v_inst_cond_mux|out~1 , z80_|alu_control_|b2v_inst_cond_mux|out~1, spectrum, 1 instance = comp, \z80_|alu_control_|flags_cond_true~0 , z80_|alu_control_|flags_cond_true~0, spectrum, 1 instance = comp, \z80_|alu_control_|flags_cond_true , z80_|alu_control_|flags_cond_true, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~13 , z80_|execute_|ctl_reg_sel_wz~13, spectrum, 1 instance = comp, \z80_|execute_|ctl_reg_sel_wz~14 , z80_|execute_|ctl_reg_sel_wz~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~17 , z80_|execute_|ctl_reg_sel_wz~17, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_82 , z80_|reg_file_|SYNTHESIZED_WIRE_82, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~18 , z80_|reg_file_|gdfx_temp0[0]~18, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~20 , z80_|reg_file_|gdfx_temp0[0]~20, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~21 , z80_|reg_file_|gdfx_temp0[0]~21, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[1] , z80_|reg_file_|b2v_latch_iy_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[1] , z80_|reg_file_|b2v_latch_ix_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~28 , z80_|reg_file_|gdfx_temp0[1]~28, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[1] , z80_|reg_file_|b2v_latch_wz_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] , z80_|reg_file_|b2v_latch_bc2_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[1] , z80_|reg_file_|b2v_latch_bc_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~26 , z80_|reg_file_|gdfx_temp0[1]~26, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~27 , z80_|reg_file_|gdfx_temp0[1]~27, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[1] , z80_|reg_file_|b2v_latch_sp_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~29 , z80_|reg_file_|gdfx_temp0[1]~29, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[1] , z80_|reg_file_|b2v_latch_af2_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder , z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[1] , z80_|reg_file_|b2v_latch_af_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~25 , z80_|reg_file_|gdfx_temp0[1]~25, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~30 , z80_|reg_file_|gdfx_temp0[1]~30, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder , z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[1] , z80_|reg_file_|b2v_latch_hl_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] , z80_|reg_file_|b2v_latch_hl2_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~24 , z80_|reg_file_|gdfx_temp0[1]~24, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[1] , z80_|reg_file_|b2v_latch_de_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[1] , z80_|reg_file_|b2v_latch_de2_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~23 , z80_|reg_file_|gdfx_temp0[1]~23, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~31 , z80_|reg_file_|gdfx_temp0[1]~31, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~32 , z80_|reg_file_|gdfx_temp0[1]~32, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_ds[1]~1 , z80_|reg_file_|db_lo_ds[1]~1, spectrum, 1 -instance = comp, \z80_|alu_control_|db[1]~25 , z80_|alu_control_|db[1]~25, spectrum, 1 -instance = comp, \z80_|alu_control_|db[1]~24 , z80_|alu_control_|db[1]~24, spectrum, 1 -instance = comp, \z80_|alu_control_|db[1]~26 , z80_|alu_control_|db[1]~26, spectrum, 1 -instance = comp, \z80_|alu_|db[1]~12 , z80_|alu_|db[1]~12, spectrum, 1 -instance = comp, \z80_|alu_|db[1]~13 , z80_|alu_|db[1]~13, spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~21 , z80_|alu_|db_low[0]~21, spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~22 , z80_|alu_|db_low[0]~22, spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~18 , z80_|alu_|db_low[0]~18, spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~19 , z80_|alu_|db_low[0]~19, spectrum, 1 -instance = comp, \z80_|alu_|result_lo[0] , z80_|alu_|result_lo[0], spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~20 , z80_|alu_|db_low[0]~20, spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~23 , z80_|alu_|db_low[0]~23, spectrum, 1 -instance = comp, \z80_|alu_|db[0]~18 , z80_|alu_|db[0]~18, spectrum, 1 -instance = comp, \z80_|alu_|db[0]~19 , z80_|alu_|db[0]~19, spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~15 , z80_|alu_|db_low[1]~15, spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~16 , z80_|alu_|db_low[1]~16, spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~12 , z80_|alu_|db_low[1]~12, spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~13 , z80_|alu_|db_low[1]~13, spectrum, 1 -instance = comp, \z80_|alu_|result_lo[1] , z80_|alu_|result_lo[1], spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~14 , z80_|alu_|db_low[1]~14, spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~17 , z80_|alu_|db_low[1]~17, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 , z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 , z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6, spectrum, 1 -instance = comp, \z80_|alu_|op1_low[1] , z80_|alu_|op1_low[1], spectrum, 1 -instance = comp, \z80_|alu_control_|out[6]~0 , z80_|alu_control_|out[6]~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf~2 , z80_|alu_flags_|DFFE_inst_latch_cf~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|flags_hf2~0 , z80_|alu_flags_|flags_hf2~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|flags_hf2 , z80_|alu_flags_|flags_hf2, spectrum, 1 -instance = comp, \z80_|alu_control_|db[2]~23 , z80_|alu_control_|db[2]~23, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_ds[2]~2 , z80_|reg_file_|db_lo_ds[2]~2, spectrum, 1 -instance = comp, \z80_|alu_control_|db[2]~28 , z80_|alu_control_|db[2]~28, spectrum, 1 -instance = comp, \z80_|alu_control_|db[2]~27 , z80_|alu_control_|db[2]~27, spectrum, 1 -instance = comp, \z80_|alu_control_|db[2]~29 , z80_|alu_control_|db[2]~29, spectrum, 1 -instance = comp, \z80_|alu_|db[2]~14 , z80_|alu_|db[2]~14, spectrum, 1 -instance = comp, \z80_|alu_|db[2]~15 , z80_|alu_|db[2]~15, spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~2 , z80_|alu_|db_low[2]~2, spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~3 , z80_|alu_|db_low[2]~3, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 , z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 , z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3, spectrum, 1 -instance = comp, \z80_|alu_|op1_low[2] , z80_|alu_|op1_low[2], spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 , z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 , z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1, spectrum, 1 -instance = comp, \z80_|alu_|op2_low[2] , z80_|alu_|op2_low[2], spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~5 , z80_|alu_|db_low[2]~5, spectrum, 1 -instance = comp, \z80_|alu_|result_lo[2] , z80_|alu_|result_lo[2], spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~6 , z80_|alu_|db_low[2]~6, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 , z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 , z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4, spectrum, 1 -instance = comp, \z80_|alu_|op2_high[2] , z80_|alu_|op2_high[2], spectrum, 1 -instance = comp, \z80_|alu_|alu_op2[2]~0 , z80_|alu_|alu_op2[2]~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0, spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~9 , z80_|alu_|db_high[2]~9, spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~11 , z80_|alu_|db_high[2]~11, spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~12 , z80_|alu_|db_high[2]~12, spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~10 , z80_|alu_|db_high[2]~10, spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~13 , z80_|alu_|db_high[2]~13, spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~14 , z80_|alu_|db_high[2]~14, spectrum, 1 -instance = comp, \z80_|alu_|db[6]~22 , z80_|alu_|db[6]~22, spectrum, 1 -instance = comp, \z80_|alu_|db[6]~23 , z80_|alu_|db[6]~23, spectrum, 1 -instance = comp, \z80_|alu_control_|out[6]~1 , z80_|alu_control_|out[6]~1, spectrum, 1 -instance = comp, \z80_|alu_control_|out[6]~2 , z80_|alu_control_|out[6]~2, spectrum, 1 -instance = comp, \z80_|alu_control_|db[6]~19 , z80_|alu_control_|db[6]~19, spectrum, 1 -instance = comp, \z80_|alu_control_|db[6]~20 , z80_|alu_control_|db[6]~20, spectrum, 1 -instance = comp, \z80_|alu_control_|db[6]~21 , z80_|alu_control_|db[6]~21, spectrum, 1 -instance = comp, \z80_|alu_control_|db[6]~22 , z80_|alu_control_|db[6]~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_zero_oe~0 , z80_|execute_|ctl_bus_zero_oe~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 , z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3, spectrum, 1 -instance = comp, \z80_|interrupts_|im1 , z80_|interrupts_|im1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_ff_oe~0 , z80_|execute_|ctl_bus_ff_oe~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_ff_oe~1 , z80_|execute_|ctl_bus_ff_oe~1, spectrum, 1 -instance = comp, \z80_|bus_control_|db[0]~4 , z80_|bus_control_|db[0]~4, spectrum, 1 -instance = comp, \z80_|bus_control_|db[6]~8 , z80_|bus_control_|db[6]~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~37 , z80_|execute_|ctl_mRead~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~28 , z80_|execute_|ctl_mRead~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~29 , z80_|execute_|ctl_mRead~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~30 , z80_|execute_|ctl_mRead~30, spectrum, 1 -instance = comp, \z80_|execute_|setM1~37 , z80_|execute_|setM1~37, spectrum, 1 -instance = comp, \z80_|execute_|setM1~55 , z80_|execute_|setM1~55, spectrum, 1 -instance = comp, \z80_|execute_|setM1~38 , z80_|execute_|setM1~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~34 , z80_|execute_|ctl_mRead~34, spectrum, 1 -instance = comp, \z80_|execute_|nextM~3 , z80_|execute_|nextM~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~31 , z80_|execute_|ctl_mRead~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~32 , z80_|execute_|ctl_mRead~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~33 , z80_|execute_|ctl_mRead~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~35 , z80_|execute_|ctl_mRead~35, spectrum, 1 -instance = comp, \z80_|memory_ifc_|DFFE_mrd_ff1 , z80_|memory_ifc_|DFFE_mrd_ff1, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_mrd~feeder , z80_|memory_ifc_|wait_mrd~feeder, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_mrd , z80_|memory_ifc_|wait_mrd, spectrum, 1 -instance = comp, \z80_|memory_ifc_|DFFE_mrd_ff3 , z80_|memory_ifc_|DFFE_mrd_ff3, spectrum, 1 -instance = comp, \z80_|memory_ifc_|nRD_out~1 , z80_|memory_ifc_|nRD_out~1, spectrum, 1 -instance = comp, \z80_|execute_|nextM~4 , z80_|execute_|nextM~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_iorw~12 , z80_|execute_|ctl_iorw~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_iorw~8 , z80_|execute_|ctl_iorw~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_iorw~9 , z80_|execute_|ctl_iorw~9, spectrum, 1 -instance = comp, \z80_|memory_ifc_|DFFE_iorq_ff1 , z80_|memory_ifc_|DFFE_iorq_ff1, spectrum, 1 -instance = comp, \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder , z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder, spectrum, 1 -instance = comp, \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 , z80_|memory_ifc_|SYNTHESIZED_WIRE_15, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_iorq , z80_|memory_ifc_|wait_iorq, spectrum, 1 -instance = comp, \z80_|memory_ifc_|DFFE_iorq_ff4 , z80_|memory_ifc_|DFFE_iorq_ff4, spectrum, 1 -instance = comp, \z80_|memory_ifc_|iorq~0 , z80_|memory_ifc_|iorq~0, spectrum, 1 -instance = comp, \z80_|execute_|fIORead~1 , z80_|execute_|fIORead~1, spectrum, 1 -instance = comp, \z80_|execute_|fIORead~2 , z80_|execute_|fIORead~2, spectrum, 1 -instance = comp, \z80_|execute_|fIORead~0 , z80_|execute_|fIORead~0, spectrum, 1 -instance = comp, \z80_|execute_|fIORead~3 , z80_|execute_|fIORead~3, spectrum, 1 -instance = comp, \z80_|memory_ifc_|DFFE_m1_ff1 , z80_|memory_ifc_|DFFE_m1_ff1, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 , z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 , z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1, spectrum, 1 -instance = comp, \z80_|memory_ifc_|DFFE_m1_ff3 , z80_|memory_ifc_|DFFE_m1_ff3, spectrum, 1 -instance = comp, \z80_|memory_ifc_|nRD_out~0 , z80_|memory_ifc_|nRD_out~0, spectrum, 1 -instance = comp, \z80_|memory_ifc_|nRD_out~2 , z80_|memory_ifc_|nRD_out~2, spectrum, 1 -instance = comp, \Equal2~1 , Equal2~1, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~0 , z80_|pin_control_|bus_db_pin_oe~0, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~5 , z80_|execute_|fMWrite~5, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~6 , z80_|execute_|fMWrite~6, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~2 , z80_|execute_|fMWrite~2, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~4 , z80_|execute_|fMWrite~4, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~1 , z80_|pin_control_|bus_db_pin_oe~1, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~2 , z80_|pin_control_|bus_db_pin_oe~2, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~3 , z80_|pin_control_|bus_db_pin_oe~3, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~7 , z80_|execute_|fMWrite~7, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~4 , z80_|pin_control_|bus_db_pin_oe~4, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~7 , z80_|pin_control_|bus_db_pin_oe~7, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~6 , z80_|pin_control_|bus_db_pin_oe~6, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~9 , z80_|execute_|fMWrite~9, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~8 , z80_|pin_control_|bus_db_pin_oe~8, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~9 , z80_|pin_control_|bus_db_pin_oe~9, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~8 , z80_|execute_|fMWrite~8, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~5 , z80_|pin_control_|bus_db_pin_oe~5, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~10 , z80_|pin_control_|bus_db_pin_oe~10, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~10 , z80_|execute_|fMWrite~10, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~11 , z80_|pin_control_|bus_db_pin_oe~11, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~12 , z80_|pin_control_|bus_db_pin_oe~12, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~13 , z80_|pin_control_|bus_db_pin_oe~13, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~14 , z80_|pin_control_|bus_db_pin_oe~14, spectrum, 1 -instance = comp, \z80_|clk_delay_|DFF_inst5~feeder , z80_|clk_delay_|DFF_inst5~feeder, spectrum, 1 -instance = comp, \z80_|clk_delay_|DFF_inst5 , z80_|clk_delay_|DFF_inst5, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_iorqinta~feeder , z80_|memory_ifc_|wait_iorqinta~feeder, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_iorqinta , z80_|memory_ifc_|wait_iorqinta, spectrum, 1 -instance = comp, \z80_|memory_ifc_|DFFE_intr_ff3 , z80_|memory_ifc_|DFFE_intr_ff3, spectrum, 1 -instance = comp, \z80_|memory_ifc_|nIORQ_out~0 , z80_|memory_ifc_|nIORQ_out~0, spectrum, 1 -instance = comp, \Equal2~0 , Equal2~0, spectrum, 1 -instance = comp, \ExtRamWE~0 , ExtRamWE~0, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[13]~13 , z80_|address_pins_|DFFE_apin_latch[13]~13, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_hi~0 , z80_|reg_control_|reg_sys_we_hi~0, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_hi , z80_|reg_control_|reg_sys_we_hi, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_60 , z80_|reg_file_|SYNTHESIZED_WIRE_60, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[0]~2 , z80_|reg_file_|db_hi_as[0]~2, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[3] , z80_|reg_file_|b2v_latch_ir_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[3]~7 , z80_|reg_file_|db_hi_as[3]~7, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[3] , z80_|reg_file_|b2v_latch_pc_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[3]~8 , z80_|reg_file_|db_hi_as[3]~8, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[3]~9 , z80_|reg_file_|db_hi_as[3]~9, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[11] , z80_|address_latch_|abusz[11], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[11] , z80_|address_latch_|Q[11], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[11] , z80_|address_latch_|b2v_inst_inc_dec|address[11], spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[11]~11 , z80_|address_pins_|DFFE_apin_latch[11]~11, spectrum, 1 instance = comp, \z80_|execute_|ctl_apin_mux2~0 , z80_|execute_|ctl_apin_mux2~0, spectrum, 1 instance = comp, \z80_|pin_control_|bus_ab_pin_we~2 , z80_|pin_control_|bus_ab_pin_we~2, spectrum, 1 instance = comp, \z80_|pin_control_|bus_ab_pin_we~3 , z80_|pin_control_|bus_ab_pin_we~3, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[13] , z80_|address_pins_|DFFE_apin_latch[13], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[13]~20 , z80_|address_pins_|abus[13]~20, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[14]~14 , z80_|address_pins_|DFFE_apin_latch[14]~14, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[14] , z80_|address_pins_|DFFE_apin_latch[14], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[14]~23 , z80_|address_pins_|abus[14]~23, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[11] , z80_|address_pins_|DFFE_apin_latch[11], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[11]~19 , z80_|address_pins_|abus[11]~19, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[10]~10 , z80_|address_pins_|DFFE_apin_latch[10]~10, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[10] , z80_|address_pins_|DFFE_apin_latch[10], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[10]~20 , z80_|address_pins_|abus[10]~20, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][1]~19 , ula_|zx_keyboard_|keys[7][1]~19, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][4]~48 , ula_|zx_keyboard_|keys[7][4]~48, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][2]~51 , ula_|zx_keyboard_|keys[3][2]~51, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][2] , ula_|zx_keyboard_|keys[3][2], spectrum, 1 +instance = comp, \D[2]~43 , D[2]~43, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr17~0 , ula_|zx_keyboard_|WideOr17~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|shifted~2 , ula_|zx_keyboard_|shifted~2, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][0]~11 , ula_|zx_keyboard_|keys[0][0]~11, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|shifted~0 , ula_|zx_keyboard_|shifted~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|shifted~3 , ula_|zx_keyboard_|shifted~3, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|shifted , ula_|zx_keyboard_|shifted, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][0]~62 , ula_|zx_keyboard_|keys[5][0]~62, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1]~32 , ula_|zx_keyboard_|keys[6][1]~32, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][2]~63 , ula_|zx_keyboard_|keys[6][2]~63, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][2]~64 , ula_|zx_keyboard_|keys[6][2]~64, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][2]~65 , ula_|zx_keyboard_|keys[6][2]~65, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][2] , ula_|zx_keyboard_|keys[6][2], spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[15]~15 , z80_|address_pins_|DFFE_apin_latch[15]~15, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[15] , z80_|address_pins_|DFFE_apin_latch[15], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[15]~22 , z80_|address_pins_|abus[15]~22, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] , ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2], spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 , ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0, spectrum, 1 +instance = comp, \z80_|address_pins_|abus[15]~21 , z80_|address_pins_|abus[15]~21, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[14]~14 , z80_|address_pins_|DFFE_apin_latch[14]~14, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[14] , z80_|address_pins_|DFFE_apin_latch[14], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[14]~22 , z80_|address_pins_|abus[14]~22, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2]~57 , ula_|zx_keyboard_|keys[7][2]~57, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2]~58 , ula_|zx_keyboard_|keys[7][2]~58, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][4]~59 , ula_|zx_keyboard_|keys[5][4]~59, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2]~28 , ula_|zx_keyboard_|keys[7][2]~28, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2]~60 , ula_|zx_keyboard_|keys[7][2]~60, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2]~56 , ula_|zx_keyboard_|keys[7][2]~56, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|Selector13~0 , ula_|zx_keyboard_|Selector13~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2]~61 , ula_|zx_keyboard_|keys[7][2]~61, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2] , ula_|zx_keyboard_|keys[7][2], spectrum, 1 +instance = comp, \D[2]~44 , D[2]~44, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[12]~12 , z80_|address_pins_|DFFE_apin_latch[12]~12, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[12] , z80_|address_pins_|DFFE_apin_latch[12], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[12]~24 , z80_|address_pins_|abus[12]~24, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[13]~13 , z80_|address_pins_|DFFE_apin_latch[13]~13, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[13] , z80_|address_pins_|DFFE_apin_latch[13], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][2]~29 , ula_|zx_keyboard_|keys[5][2]~29, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][2]~54 , ula_|zx_keyboard_|keys[5][2]~54, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][2]~55 , ula_|zx_keyboard_|keys[5][2]~55, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][2] , ula_|zx_keyboard_|keys[5][2], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row~1 , ula_|zx_keyboard_|key_row~1, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][4]~127 , ula_|zx_keyboard_|keys[3][4]~127, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][2]~66 , ula_|zx_keyboard_|keys[4][2]~66, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][2]~128 , ula_|zx_keyboard_|keys[4][2]~128, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][2]~67 , ula_|zx_keyboard_|keys[4][2]~67, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][2] , ula_|zx_keyboard_|keys[4][2], spectrum, 1 +instance = comp, \D[2]~45 , D[2]~45, spectrum, 1 instance = comp, \z80_|address_pins_|abus[0]~16 , z80_|address_pins_|abus[0]~16, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][4]~43 , ula_|zx_keyboard_|keys[6][4]~43, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][4]~44 , ula_|zx_keyboard_|keys[6][4]~44, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][2]~45 , ula_|zx_keyboard_|keys[1][2]~45, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][2]~46 , ula_|zx_keyboard_|keys[1][2]~46, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][2] , ula_|zx_keyboard_|keys[1][2], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][2]~47 , ula_|zx_keyboard_|keys[0][2]~47, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][2]~49 , ula_|zx_keyboard_|keys[0][2]~49, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][2] , ula_|zx_keyboard_|keys[0][2], spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[9]~9 , z80_|address_pins_|DFFE_apin_latch[9]~9, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[9] , z80_|address_pins_|DFFE_apin_latch[9], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[9]~17 , z80_|address_pins_|abus[9]~17, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[8]~8 , z80_|address_pins_|DFFE_apin_latch[8]~8, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[8] , z80_|address_pins_|DFFE_apin_latch[8], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[8]~18 , z80_|address_pins_|abus[8]~18, spectrum, 1 +instance = comp, \D[2]~42 , D[2]~42, spectrum, 1 +instance = comp, \D[2]~46 , D[2]~46, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_iorqinta , z80_|memory_ifc_|wait_iorqinta, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_intr_ff3~feeder , z80_|memory_ifc_|DFFE_intr_ff3~feeder, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_intr_ff3 , z80_|memory_ifc_|DFFE_intr_ff3, spectrum, 1 +instance = comp, \z80_|control_pins_|pin_nIORQ~1 , z80_|control_pins_|pin_nIORQ~1, spectrum, 1 +instance = comp, \Equal2~0 , Equal2~0, spectrum, 1 +instance = comp, \z80_|address_pins_|abus[13]~23 , z80_|address_pins_|abus[13]~23, spectrum, 1 +instance = comp, \ExtRamWE~0 , ExtRamWE~0, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] , ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2], spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 , ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[1]~1 , z80_|address_pins_|DFFE_apin_latch[1]~1, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[1] , z80_|address_pins_|DFFE_apin_latch[1], spectrum, 1 instance = comp, \z80_|address_pins_|abus[1]~25 , z80_|address_pins_|abus[1]~25, spectrum, 1 @@ -2098,43 +2278,28 @@ instance = comp, \z80_|address_pins_|abus[6]~30 , z80_|address_pins_|abus[6]~30, instance = comp, \z80_|address_pins_|DFFE_apin_latch[7]~7 , z80_|address_pins_|DFFE_apin_latch[7]~7, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[7] , z80_|address_pins_|DFFE_apin_latch[7], spectrum, 1 instance = comp, \z80_|address_pins_|abus[7]~31 , z80_|address_pins_|abus[7]~31, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[8]~8 , z80_|address_pins_|DFFE_apin_latch[8]~8, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[8] , z80_|address_pins_|DFFE_apin_latch[8], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[8]~18 , z80_|address_pins_|abus[8]~18, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[9]~9 , z80_|address_pins_|DFFE_apin_latch[9]~9, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[9] , z80_|address_pins_|DFFE_apin_latch[9], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[9]~17 , z80_|address_pins_|abus[9]~17, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[10]~10 , z80_|address_pins_|DFFE_apin_latch[10]~10, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[10] , z80_|address_pins_|DFFE_apin_latch[10], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[10]~24 , z80_|address_pins_|abus[10]~24, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[11]~11 , z80_|address_pins_|DFFE_apin_latch[11]~11, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[11] , z80_|address_pins_|DFFE_apin_latch[11], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[11]~19 , z80_|address_pins_|abus[11]~19, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[12]~12 , z80_|address_pins_|DFFE_apin_latch[12]~12, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[12] , z80_|address_pins_|DFFE_apin_latch[12], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[12]~21 , z80_|address_pins_|abus[12]~21, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a14 , ram1|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a18 , ram1|altsyncram_component|auto_generated|ram_block1a18, spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|address_reg_a[0] , ram1|altsyncram_component|auto_generated|address_reg_a[0], spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] , ram1|altsyncram_component|auto_generated|out_address_reg_a[0], spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] , ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2], spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 , ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a6 , ram1|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a2 , ram1|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] , ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2], spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 , ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a10 , ram1|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|address_reg_a[1] , ram1|altsyncram_component|auto_generated|address_reg_a[1], spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] , ram1|altsyncram_component|auto_generated|out_address_reg_a[1], spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] , ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2], spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 , ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a22 , ram1|altsyncram_component|auto_generated|ram_block1a22, spectrum, 1 -instance = comp, \D[6]~90 , D[6]~90, spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] , ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2], spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 , ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a30 , ram1|altsyncram_component|auto_generated|ram_block1a30, spectrum, 1 -instance = comp, \D[6]~91 , D[6]~91, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a26 , ram1|altsyncram_component|auto_generated|ram_block1a26, spectrum, 1 +instance = comp, \D[2]~50 , D[2]~50, spectrum, 1 +instance = comp, \D[2]~51 , D[2]~51, spectrum, 1 instance = comp, \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 , ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0, spectrum, 1 instance = comp, \CLOCK_50~inputclkctrl , CLOCK_50~inputclkctrl, spectrum, 1 instance = comp, \~GND , ~GND, spectrum, 1 -instance = comp, \ula_|video_|vram_address[0]~feeder , ula_|video_|vram_address[0]~feeder, spectrum, 1 instance = comp, \ula_|video_|vram_address~0 , ula_|video_|vram_address~0, spectrum, 1 instance = comp, \ula_|video_|vram_address[0] , ula_|video_|vram_address[0], spectrum, 1 +instance = comp, \ula_|video_|vram_address[1]~feeder , ula_|video_|vram_address[1]~feeder, spectrum, 1 instance = comp, \ula_|video_|vram_address[1] , ula_|video_|vram_address[1], spectrum, 1 instance = comp, \ula_|video_|vram_address[2]~4 , ula_|video_|vram_address[2]~4, spectrum, 1 instance = comp, \ula_|video_|vram_address[2] , ula_|video_|vram_address[2], spectrum, 1 @@ -2153,7 +2318,7 @@ instance = comp, \ula_|video_|Add4~10 , ula_|video_|Add4~10, spectrum, 1 instance = comp, \ula_|video_|vram_address[7] , ula_|video_|vram_address[7], spectrum, 1 instance = comp, \ula_|video_|Add4~12 , ula_|video_|Add4~12, spectrum, 1 instance = comp, \ula_|video_|Selector6~0 , ula_|video_|Selector6~0, spectrum, 1 -instance = comp, \ula_|video_|vram_address[9]~1 , ula_|video_|vram_address[9]~1, spectrum, 1 +instance = comp, \ula_|video_|vram_address[8]~1 , ula_|video_|vram_address[8]~1, spectrum, 1 instance = comp, \ula_|video_|vram_address[8] , ula_|video_|vram_address[8], spectrum, 1 instance = comp, \ula_|video_|Add4~14 , ula_|video_|Add4~14, spectrum, 1 instance = comp, \ula_|video_|Selector5~0 , ula_|video_|Selector5~0, spectrum, 1 @@ -2165,672 +2330,534 @@ instance = comp, \ula_|video_|Selector3~0 , ula_|video_|Selector3~0, spectrum, 1 instance = comp, \ula_|video_|vram_address[11] , ula_|video_|vram_address[11], spectrum, 1 instance = comp, \ula_|video_|Selector2~0 , ula_|video_|Selector2~0, spectrum, 1 instance = comp, \ula_|video_|vram_address[12] , ula_|video_|vram_address[12], spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a6 , ram0|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a2 , ram0|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 instance = comp, \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder , ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder, spectrum, 1 instance = comp, \ram0|altsyncram_component|auto_generated|address_reg_a[0] , ram0|altsyncram_component|auto_generated|address_reg_a[0], spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder , ram0|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder, spectrum, 1 instance = comp, \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] , ram0|altsyncram_component|auto_generated|out_address_reg_a[0], spectrum, 1 instance = comp, \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 , ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a14 , ram0|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a14 , rom|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 -instance = comp, \D[6]~87 , D[6]~87, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a6 , rom|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 -instance = comp, \D[6]~88 , D[6]~88, spectrum, 1 -instance = comp, \D[6]~89 , D[6]~89, spectrum, 1 -instance = comp, \D[6]~111 , D[6]~111, spectrum, 1 -instance = comp, \raw_loader_in~input , raw_loader_in~input, spectrum, 1 -instance = comp, \D[6]~86 , D[6]~86, spectrum, 1 -instance = comp, \D[6]~100 , D[6]~100, spectrum, 1 -instance = comp, \D[6]~101 , D[6]~101, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] , z80_|data_pins_|SYNTHESIZED_WIRE_0[6], spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a10 , ram0|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a10 , rom|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 +instance = comp, \D[2]~47 , D[2]~47, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a2 , rom|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 +instance = comp, \D[2]~48 , D[2]~48, spectrum, 1 +instance = comp, \D[2]~49 , D[2]~49, spectrum, 1 +instance = comp, \D[2]~119 , D[2]~119, spectrum, 1 +instance = comp, \D[2]~52 , D[2]~52, spectrum, 1 +instance = comp, \D[2]~53 , D[2]~53, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] , z80_|data_pins_|SYNTHESIZED_WIRE_0[2], spectrum, 1 instance = comp, \z80_|pin_control_|bus_db_pin_re~2 , z80_|pin_control_|bus_db_pin_re~2, spectrum, 1 instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_2 , z80_|data_pins_|SYNTHESIZED_WIRE_2, spectrum, 1 +instance = comp, \z80_|data_pins_|dout[2] , z80_|data_pins_|dout[2], spectrum, 1 +instance = comp, \z80_|bus_control_|db[2]~12 , z80_|bus_control_|db[2]~12, spectrum, 1 +instance = comp, \z80_|bus_control_|db[0]~6 , z80_|bus_control_|db[0]~6, spectrum, 1 +instance = comp, \z80_|bus_control_|db[2]~13 , z80_|bus_control_|db[2]~13, spectrum, 1 +instance = comp, \z80_|ir_|opcode[2]~feeder , z80_|ir_|opcode[2]~feeder, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~13 , z80_|execute_|ctl_ir_we~13, spectrum, 1 +instance = comp, \z80_|ir_|opcode[2] , z80_|ir_|opcode[2], spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~34 , z80_|execute_|ctl_mRead~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~33 , z80_|execute_|ctl_reg_gp_hilo[0]~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~6 , z80_|execute_|ctl_reg_out_lo~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~7 , z80_|execute_|ctl_reg_out_lo~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~8 , z80_|execute_|ctl_reg_out_lo~8, spectrum, 1 +instance = comp, \z80_|alu_control_|db[6]~13 , z80_|alu_control_|db[6]~13, spectrum, 1 +instance = comp, \z80_|alu_control_|db[6]~21 , z80_|alu_control_|db[6]~21, spectrum, 1 +instance = comp, \z80_|alu_control_|db[6]~22 , z80_|alu_control_|db[6]~22, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_ds[6]~0 , z80_|reg_file_|db_lo_ds[6]~0, spectrum, 1 +instance = comp, \z80_|sw1_|db_down[6]~1 , z80_|sw1_|db_down[6]~1, spectrum, 1 +instance = comp, \z80_|alu_control_|db[6]~23 , z80_|alu_control_|db[6]~23, spectrum, 1 +instance = comp, \z80_|bus_control_|db[6]~8 , z80_|bus_control_|db[6]~8, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a22 , ram1|altsyncram_component|auto_generated|ram_block1a22, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a6 , ram1|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a14 , ram1|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a30 , ram1|altsyncram_component|auto_generated|ram_block1a30, spectrum, 1 +instance = comp, \D[6]~103 , D[6]~103, spectrum, 1 +instance = comp, \D[6]~104 , D[6]~104, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a6 , ram0|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a14 , ram0|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a14 , rom|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 +instance = comp, \D[6]~100 , D[6]~100, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a6 , rom|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 +instance = comp, \D[6]~101 , D[6]~101, spectrum, 1 +instance = comp, \D[6]~102 , D[6]~102, spectrum, 1 +instance = comp, \D[6]~127 , D[6]~127, spectrum, 1 +instance = comp, \raw_loader_in~input , raw_loader_in~input, spectrum, 1 +instance = comp, \D[6]~99 , D[6]~99, spectrum, 1 +instance = comp, \D[6]~114 , D[6]~114, spectrum, 1 +instance = comp, \D[6]~115 , D[6]~115, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] , z80_|data_pins_|SYNTHESIZED_WIRE_0[6], spectrum, 1 instance = comp, \z80_|data_pins_|dout[6] , z80_|data_pins_|dout[6], spectrum, 1 instance = comp, \z80_|bus_control_|db[6]~9 , z80_|bus_control_|db[6]~9, spectrum, 1 -instance = comp, \z80_|ir_|opcode[6]~feeder , z80_|ir_|opcode[6]~feeder, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~13 , z80_|execute_|ctl_ir_we~13, spectrum, 1 instance = comp, \z80_|ir_|opcode[6] , z80_|ir_|opcode[6], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal41~0 , z80_|pla_decode_|Equal41~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal41~1 , z80_|pla_decode_|Equal41~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal41~2 , z80_|pla_decode_|Equal41~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe , z80_|execute_|ctl_alu_bs_oe, spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~15 , z80_|alu_|db_high[1]~15, spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~16 , z80_|alu_|db_high[1]~16, spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~17 , z80_|alu_|db_high[1]~17, spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~18 , z80_|alu_|db_high[1]~18, spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~19 , z80_|alu_|db_high[1]~19, spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~20 , z80_|alu_|db_high[1]~20, spectrum, 1 -instance = comp, \z80_|alu_|db[5]~24 , z80_|alu_|db[5]~24, spectrum, 1 -instance = comp, \z80_|alu_|db[5]~25 , z80_|alu_|db[5]~25, spectrum, 1 -instance = comp, \z80_|sw1_|db_down[5]~0 , z80_|sw1_|db_down[5]~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_36 , z80_|alu_flags_|SYNTHESIZED_WIRE_36, spectrum, 1 -instance = comp, \z80_|alu_flags_|flags_yf , z80_|alu_flags_|flags_yf, spectrum, 1 -instance = comp, \z80_|alu_control_|db[5]~13 , z80_|alu_control_|db[5]~13, spectrum, 1 -instance = comp, \z80_|alu_control_|db[5]~14 , z80_|alu_control_|db[5]~14, spectrum, 1 -instance = comp, \z80_|alu_control_|db[5]~15 , z80_|alu_control_|db[5]~15, spectrum, 1 -instance = comp, \D[0]~107 , D[0]~107, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a21 , ram1|altsyncram_component|auto_generated|ram_block1a21, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a5 , ram1|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a13 , ram1|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 , ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a29 , ram1|altsyncram_component|auto_generated|ram_block1a29, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 , ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a13 , ram0|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a13 , rom|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a5 , rom|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a5 , ram0|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 -instance = comp, \Mux2~0 , Mux2~0, spectrum, 1 -instance = comp, \Mux2~1 , Mux2~1, spectrum, 1 -instance = comp, \D[5]~110 , D[5]~110, spectrum, 1 -instance = comp, \D[5]~85 , D[5]~85, spectrum, 1 -instance = comp, \D[5]~99 , D[5]~99, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] , z80_|data_pins_|SYNTHESIZED_WIRE_0[5], spectrum, 1 -instance = comp, \z80_|data_pins_|dout[5] , z80_|data_pins_|dout[5], spectrum, 1 -instance = comp, \z80_|bus_control_|db[5]~14 , z80_|bus_control_|db[5]~14, spectrum, 1 -instance = comp, \z80_|bus_control_|db[5]~15 , z80_|bus_control_|db[5]~15, spectrum, 1 -instance = comp, \z80_|ir_|opcode[5] , z80_|ir_|opcode[5], spectrum, 1 -instance = comp, \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 , z80_|decode_state_|SYNTHESIZED_WIRE_0~0, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_inst4 , z80_|decode_state_|DFFE_inst4, spectrum, 1 -instance = comp, \z80_|decode_state_|use_ixiy , z80_|decode_state_|use_ixiy, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~23 , z80_|execute_|ctl_mRead~23, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~34 , z80_|execute_|fMRead~34, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~31 , z80_|execute_|fMRead~31, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal13~0 , z80_|pla_decode_|Equal13~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal38~2 , z80_|pla_decode_|Equal38~2, spectrum, 1 +instance = comp, \z80_|interrupts_|iff1~0 , z80_|interrupts_|iff1~0, spectrum, 1 +instance = comp, \z80_|interrupts_|iff1~1 , z80_|interrupts_|iff1~1, spectrum, 1 +instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_15 , z80_|interrupts_|SYNTHESIZED_WIRE_15, spectrum, 1 +instance = comp, \z80_|interrupts_|iff1 , z80_|interrupts_|iff1, spectrum, 1 +instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_13 , z80_|interrupts_|SYNTHESIZED_WIRE_13, spectrum, 1 +instance = comp, \z80_|interrupts_|int_armed , z80_|interrupts_|int_armed, spectrum, 1 +instance = comp, \z80_|interrupts_|DFFE_inst44 , z80_|interrupts_|DFFE_inst44, spectrum, 1 +instance = comp, \z80_|decode_state_|in_halt~0 , z80_|decode_state_|in_halt~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal77~1 , z80_|pla_decode_|Equal77~1, spectrum, 1 +instance = comp, \z80_|decode_state_|in_halt~1 , z80_|decode_state_|in_halt~1, spectrum, 1 +instance = comp, \z80_|decode_state_|in_halt , z80_|decode_state_|in_halt, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~21 , z80_|execute_|ctl_mRead~21, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~35 , z80_|execute_|fMRead~35, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~23 , z80_|execute_|fMRead~23, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~27 , z80_|execute_|fMRead~27, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~28 , z80_|execute_|fMRead~28, spectrum, 1 instance = comp, \z80_|execute_|fMRead~29 , z80_|execute_|fMRead~29, spectrum, 1 instance = comp, \z80_|execute_|fMRead~30 , z80_|execute_|fMRead~30, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~28 , z80_|execute_|fMRead~28, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~31 , z80_|execute_|fMRead~31, spectrum, 1 instance = comp, \z80_|execute_|fMRead~32 , z80_|execute_|fMRead~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~42 , z80_|execute_|ctl_bus_inc_oe~42, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~14 , z80_|execute_|fMRead~14, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~10 , z80_|execute_|fMRead~10, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~9 , z80_|execute_|fMRead~9, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~37 , z80_|execute_|fMRead~37, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~33 , z80_|execute_|fMRead~33, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~24 , z80_|execute_|fMRead~24, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~25 , z80_|execute_|fMRead~25, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~16 , z80_|execute_|fMRead~16, spectrum, 1 instance = comp, \z80_|execute_|fMRead~11 , z80_|execute_|fMRead~11, spectrum, 1 instance = comp, \z80_|execute_|fMRead~12 , z80_|execute_|fMRead~12, spectrum, 1 instance = comp, \z80_|execute_|fMRead~13 , z80_|execute_|fMRead~13, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~14 , z80_|execute_|fMRead~14, spectrum, 1 instance = comp, \z80_|execute_|fMRead~15 , z80_|execute_|fMRead~15, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~20 , z80_|execute_|fMRead~20, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~48 , z80_|execute_|pc_inc_hold~48, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~17 , z80_|execute_|fMRead~17, spectrum, 1 instance = comp, \z80_|execute_|fMRead~22 , z80_|execute_|fMRead~22, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~21 , z80_|execute_|fMRead~21, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~23 , z80_|execute_|fMRead~23, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~26 , z80_|execute_|fMRead~26, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~25 , z80_|execute_|fMRead~25, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~27 , z80_|execute_|fMRead~27, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~33 , z80_|execute_|fMRead~33, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~35 , z80_|execute_|fMRead~35, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~34 , z80_|execute_|fMRead~34, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~36 , z80_|execute_|fMRead~36, spectrum, 1 instance = comp, \z80_|pin_control_|bus_db_pin_re , z80_|pin_control_|bus_db_pin_re, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a1 , ram1|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a9 , ram1|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 , ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a17 , ram1|altsyncram_component|auto_generated|ram_block1a17, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a25 , ram1|altsyncram_component|auto_generated|ram_block1a25, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 , ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a9 , ram0|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a9 , rom|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a1 , rom|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a1 , ram0|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 -instance = comp, \Selector1~0 , Selector1~0, spectrum, 1 -instance = comp, \Selector1~1 , Selector1~1, spectrum, 1 -instance = comp, \D[1]~103 , D[1]~103, spectrum, 1 -instance = comp, \PS2_DAT~input , PS2_DAT~input, spectrum, 1 -instance = comp, \reset~clkctrl , reset~clkctrl, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count~0 , ula_|ps2_keyboard_|bit_count~0, spectrum, 1 -instance = comp, \PS2_CLK~input , PS2_CLK~input, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[7]~feeder , ula_|ps2_keyboard_|clk_filter[7]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[7] , ula_|ps2_keyboard_|clk_filter[7], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[6]~feeder , ula_|ps2_keyboard_|clk_filter[6]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[6] , ula_|ps2_keyboard_|clk_filter[6], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[5]~feeder , ula_|ps2_keyboard_|clk_filter[5]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[5] , ula_|ps2_keyboard_|clk_filter[5], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[4]~feeder , ula_|ps2_keyboard_|clk_filter[4]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[4] , ula_|ps2_keyboard_|clk_filter[4], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|Equal0~0 , ula_|ps2_keyboard_|Equal0~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[3]~feeder , ula_|ps2_keyboard_|clk_filter[3]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[3] , ula_|ps2_keyboard_|clk_filter[3], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[2]~feeder , ula_|ps2_keyboard_|clk_filter[2]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[2] , ula_|ps2_keyboard_|clk_filter[2], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[1]~feeder , ula_|ps2_keyboard_|clk_filter[1]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[1] , ula_|ps2_keyboard_|clk_filter[1], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|Equal0~1 , ula_|ps2_keyboard_|Equal0~1, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[0]~0 , ula_|ps2_keyboard_|clk_filter[0]~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[0] , ula_|ps2_keyboard_|clk_filter[0], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|ps2_clk_in~0 , ula_|ps2_keyboard_|ps2_clk_in~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|ps2_clk_in , ula_|ps2_keyboard_|ps2_clk_in, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_edge~0 , ula_|ps2_keyboard_|clk_edge~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_edge , ula_|ps2_keyboard_|clk_edge, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count[0] , ula_|ps2_keyboard_|bit_count[0], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count~1 , ula_|ps2_keyboard_|bit_count~1, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count[2] , ula_|ps2_keyboard_|bit_count[2], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count~3 , ula_|ps2_keyboard_|bit_count~3, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count[3] , ula_|ps2_keyboard_|bit_count[3], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count~2 , ula_|ps2_keyboard_|bit_count~2, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count[1] , ula_|ps2_keyboard_|bit_count[1], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|always1~0 , ula_|ps2_keyboard_|always1~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|LessThan0~0 , ula_|ps2_keyboard_|LessThan0~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[0]~0 , ula_|ps2_keyboard_|shiftreg[0]~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[8] , ula_|ps2_keyboard_|shiftreg[8], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[7] , ula_|ps2_keyboard_|shiftreg[7], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[6] , ula_|ps2_keyboard_|shiftreg[6], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[5] , ula_|ps2_keyboard_|shiftreg[5], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[4] , ula_|ps2_keyboard_|shiftreg[4], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[3] , ula_|ps2_keyboard_|shiftreg[3], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[2] , ula_|ps2_keyboard_|shiftreg[2], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[1] , ula_|ps2_keyboard_|shiftreg[1], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[0] , ula_|ps2_keyboard_|shiftreg[0], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|Equal0~0 , ula_|zx_keyboard_|Equal0~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|Equal0~1 , ula_|zx_keyboard_|Equal0~1, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|extended~0 , ula_|zx_keyboard_|extended~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|WideXor0~1 , ula_|ps2_keyboard_|WideXor0~1, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|WideXor0~0 , ula_|ps2_keyboard_|WideXor0~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|WideXor0~2 , ula_|ps2_keyboard_|WideXor0~2, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|scan_code_ready~0 , ula_|ps2_keyboard_|scan_code_ready~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|scan_code_ready , ula_|ps2_keyboard_|scan_code_ready, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|extended , ula_|zx_keyboard_|extended, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][0]~15 , ula_|zx_keyboard_|keys[0][0]~15, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1]~36 , ula_|zx_keyboard_|keys[5][1]~36, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1]~37 , ula_|zx_keyboard_|keys[5][1]~37, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|shifted~0 , ula_|zx_keyboard_|shifted~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|released~0 , ula_|zx_keyboard_|released~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|released , ula_|zx_keyboard_|released, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr17~0 , ula_|zx_keyboard_|WideOr17~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|shifted~2 , ula_|zx_keyboard_|shifted~2, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|shifted~3 , ula_|zx_keyboard_|shifted~3, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|shifted , ula_|zx_keyboard_|shifted, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1]~35 , ula_|zx_keyboard_|keys[5][1]~35, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1]~38 , ula_|zx_keyboard_|keys[5][1]~38, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1]~39 , ula_|zx_keyboard_|keys[5][1]~39, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1] , ula_|zx_keyboard_|keys[5][1], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][1]~31 , ula_|zx_keyboard_|keys[4][1]~31, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][1]~23 , ula_|zx_keyboard_|keys[7][1]~23, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2]~32 , ula_|zx_keyboard_|keys[7][2]~32, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][2]~33 , ula_|zx_keyboard_|keys[5][2]~33, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][1]~34 , ula_|zx_keyboard_|keys[4][1]~34, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][1] , ula_|zx_keyboard_|keys[4][1], spectrum, 1 -instance = comp, \D[1]~30 , D[1]~30, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][4]~24 , ula_|zx_keyboard_|keys[5][4]~24, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][1]~28 , ula_|zx_keyboard_|keys[3][1]~28, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][1]~29 , ula_|zx_keyboard_|keys[3][1]~29, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][1]~30 , ula_|zx_keyboard_|keys[3][1]~30, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][1] , ula_|zx_keyboard_|keys[3][1], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][4]~25 , ula_|zx_keyboard_|keys[1][4]~25, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][1]~26 , ula_|zx_keyboard_|keys[2][1]~26, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][1]~27 , ula_|zx_keyboard_|keys[2][1]~27, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][1] , ula_|zx_keyboard_|keys[2][1], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|key_row~0 , ula_|zx_keyboard_|key_row~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][1]~14 , ula_|zx_keyboard_|keys[0][1]~14, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][1]~16 , ula_|zx_keyboard_|keys[0][1]~16, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][1]~17 , ula_|zx_keyboard_|keys[0][1]~17, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][1]~18 , ula_|zx_keyboard_|keys[0][1]~18, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][1] , ula_|zx_keyboard_|keys[0][1], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][4]~19 , ula_|zx_keyboard_|keys[7][4]~19, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][4]~20 , ula_|zx_keyboard_|keys[6][4]~20, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][1]~21 , ula_|zx_keyboard_|keys[1][1]~21, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][1]~22 , ula_|zx_keyboard_|keys[1][1]~22, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][1] , ula_|zx_keyboard_|keys[1][1], spectrum, 1 -instance = comp, \D[1]~28 , D[1]~28, spectrum, 1 -instance = comp, \D[1]~29 , D[1]~29, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1]~41 , ula_|zx_keyboard_|keys[6][1]~41, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1]~42 , ula_|zx_keyboard_|keys[6][1]~42, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1]~43 , ula_|zx_keyboard_|keys[6][1]~43, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1]~40 , ula_|zx_keyboard_|keys[6][1]~40, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1]~44 , ula_|zx_keyboard_|keys[6][1]~44, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1] , ula_|zx_keyboard_|keys[6][1], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][1]~45 , ula_|zx_keyboard_|keys[7][1]~45, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr16~5 , ula_|zx_keyboard_|WideOr16~5, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr16~2 , ula_|zx_keyboard_|WideOr16~2, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr16~4 , ula_|zx_keyboard_|WideOr16~4, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr16~7 , ula_|zx_keyboard_|WideOr16~7, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr16~6 , ula_|zx_keyboard_|WideOr16~6, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][1]~46 , ula_|zx_keyboard_|keys[7][1]~46, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][1] , ula_|zx_keyboard_|keys[7][1], spectrum, 1 -instance = comp, \D[1]~31 , D[1]~31, spectrum, 1 -instance = comp, \D[1]~32 , D[1]~32, spectrum, 1 -instance = comp, \D[1]~33 , D[1]~33, spectrum, 1 -instance = comp, \D[1]~34 , D[1]~34, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] , z80_|data_pins_|SYNTHESIZED_WIRE_0[1], spectrum, 1 -instance = comp, \z80_|data_pins_|dout[1] , z80_|data_pins_|dout[1], spectrum, 1 -instance = comp, \z80_|bus_control_|db[1]~10 , z80_|bus_control_|db[1]~10, spectrum, 1 -instance = comp, \z80_|bus_control_|db[1]~11 , z80_|bus_control_|db[1]~11, spectrum, 1 -instance = comp, \z80_|ir_|opcode[1]~feeder , z80_|ir_|opcode[1]~feeder, spectrum, 1 -instance = comp, \z80_|ir_|opcode[1] , z80_|ir_|opcode[1], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal40~0 , z80_|pla_decode_|Equal40~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal21~1 , z80_|pla_decode_|Equal21~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~26 , z80_|execute_|ctl_alu_op_low~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~28 , z80_|execute_|ctl_alu_op_low~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~3 , z80_|execute_|ctl_flags_cf_cpl~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~2 , z80_|execute_|ctl_flags_cf_cpl~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~5, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~6, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~7, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~4, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~8, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~9, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~21, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~12, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~10, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~11, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~13, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~32 , z80_|execute_|ctl_alu_op_low~32, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~15, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~16, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~18, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~19, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~0 , z80_|alu_flags_|DFFE_inst_latch_cf2~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~1 , z80_|alu_flags_|DFFE_inst_latch_cf2~1, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~2 , z80_|alu_flags_|DFFE_inst_latch_cf2~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~3 , z80_|alu_flags_|DFFE_inst_latch_cf2~3, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2 , z80_|alu_flags_|DFFE_inst_latch_cf2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~10 , z80_|execute_|ctl_flags_use_cf2~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~11 , z80_|execute_|ctl_flags_use_cf2~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~8 , z80_|execute_|ctl_flags_use_cf2~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~9 , z80_|execute_|ctl_flags_use_cf2~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~12 , z80_|execute_|ctl_flags_use_cf2~12, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~14, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~10 , z80_|execute_|ctl_flags_cf_cpl~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~8 , z80_|execute_|ctl_flags_cf_cpl~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~5 , z80_|execute_|ctl_flags_cf_cpl~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~6 , z80_|execute_|ctl_flags_cf_cpl~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~7 , z80_|execute_|ctl_flags_cf_cpl~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_set~0 , z80_|execute_|ctl_flags_cf_set~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~4 , z80_|execute_|ctl_flags_cf_cpl~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~9 , z80_|execute_|ctl_flags_cf_cpl~9, spectrum, 1 -instance = comp, \z80_|alu_flags_|flags_cf , z80_|alu_flags_|flags_cf, spectrum, 1 -instance = comp, \z80_|alu_control_|db[0]~8 , z80_|alu_control_|db[0]~8, spectrum, 1 -instance = comp, \z80_|sw2_|db_up[0]~0 , z80_|sw2_|db_up[0]~0, spectrum, 1 -instance = comp, \z80_|alu_control_|db[0]~9 , z80_|alu_control_|db[0]~9, spectrum, 1 -instance = comp, \z80_|alu_control_|db[0]~12 , z80_|alu_control_|db[0]~12, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][0]~67 , ula_|zx_keyboard_|keys[5][0]~67, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][0]~81 , ula_|zx_keyboard_|keys[5][0]~81, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][0]~82 , ula_|zx_keyboard_|keys[5][0]~82, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][0]~83 , ula_|zx_keyboard_|keys[5][0]~83, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][0] , ula_|zx_keyboard_|keys[5][0], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][0]~84 , ula_|zx_keyboard_|keys[4][0]~84, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][0]~85 , ula_|zx_keyboard_|keys[4][0]~85, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][0]~86 , ula_|zx_keyboard_|keys[4][0]~86, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][0] , ula_|zx_keyboard_|keys[4][0], spectrum, 1 -instance = comp, \D[0]~49 , D[0]~49, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr4~0 , ula_|zx_keyboard_|WideOr4~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys~76 , ula_|zx_keyboard_|keys~76, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3]~73 , ula_|zx_keyboard_|keys[4][3]~73, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][4]~47 , ula_|zx_keyboard_|keys[6][4]~47, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr0~0 , ula_|zx_keyboard_|WideOr0~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys~74 , ula_|zx_keyboard_|keys~74, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][0]~75 , ula_|zx_keyboard_|keys[0][0]~75, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][0]~77 , ula_|zx_keyboard_|keys[0][0]~77, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][0] , ula_|zx_keyboard_|keys[0][0], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][0]~71 , ula_|zx_keyboard_|keys[1][0]~71, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][0]~72 , ula_|zx_keyboard_|keys[1][0]~72, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][0] , ula_|zx_keyboard_|keys[1][0], spectrum, 1 -instance = comp, \D[0]~47 , D[0]~47, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][0]~80 , ula_|zx_keyboard_|keys[2][0]~80, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][0] , ula_|zx_keyboard_|keys[2][0], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][0]~78 , ula_|zx_keyboard_|keys[3][0]~78, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][0]~79 , ula_|zx_keyboard_|keys[3][0]~79, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][0] , ula_|zx_keyboard_|keys[3][0], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|key_row~1 , ula_|zx_keyboard_|key_row~1, spectrum, 1 -instance = comp, \D[0]~48 , D[0]~48, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|shifted~1 , ula_|zx_keyboard_|shifted~1, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][0]~90 , ula_|zx_keyboard_|keys[6][0]~90, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][0]~91 , ula_|zx_keyboard_|keys[6][0]~91, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][0]~92 , ula_|zx_keyboard_|keys[6][0]~92, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][0] , ula_|zx_keyboard_|keys[6][0], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][4]~63 , ula_|zx_keyboard_|keys[5][4]~63, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr16~3 , ula_|zx_keyboard_|WideOr16~3, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][0]~87 , ula_|zx_keyboard_|keys[7][0]~87, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][0]~132 , ula_|zx_keyboard_|keys[7][0]~132, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][0]~88 , ula_|zx_keyboard_|keys[7][0]~88, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][0]~89 , ula_|zx_keyboard_|keys[7][0]~89, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][0] , ula_|zx_keyboard_|keys[7][0], spectrum, 1 -instance = comp, \D[0]~50 , D[0]~50, spectrum, 1 -instance = comp, \D[0]~51 , D[0]~51, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a24 , ram1|altsyncram_component|auto_generated|ram_block1a24, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a16 , ram1|altsyncram_component|auto_generated|ram_block1a16, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a0 , ram1|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 -instance = comp, \D[0]~55 , D[0]~55, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a8 , ram1|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 -instance = comp, \D[0]~56 , D[0]~56, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a0 , ram0|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a8 , rom|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a8 , ram0|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 -instance = comp, \D[0]~52 , D[0]~52, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a0 , rom|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 -instance = comp, \D[0]~53 , D[0]~53, spectrum, 1 -instance = comp, \D[0]~54 , D[0]~54, spectrum, 1 -instance = comp, \D[0]~106 , D[0]~106, spectrum, 1 -instance = comp, \D[0]~57 , D[0]~57, spectrum, 1 -instance = comp, \D[0]~58 , D[0]~58, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] , z80_|data_pins_|SYNTHESIZED_WIRE_0[0], spectrum, 1 -instance = comp, \z80_|data_pins_|dout[0] , z80_|data_pins_|dout[0], spectrum, 1 -instance = comp, \z80_|bus_control_|db[0]~16 , z80_|bus_control_|db[0]~16, spectrum, 1 -instance = comp, \z80_|bus_control_|db[0]~17 , z80_|bus_control_|db[0]~17, spectrum, 1 -instance = comp, \z80_|ir_|opcode[0] , z80_|ir_|opcode[0], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal63~0 , z80_|pla_decode_|Equal63~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_sel_daa , z80_|execute_|ctl_flags_cf2_sel_daa, spectrum, 1 -instance = comp, \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 , z80_|alu_control_|SYNTHESIZED_WIRE_2~0, spectrum, 1 -instance = comp, \z80_|alu_control_|db[6]~10 , z80_|alu_control_|db[6]~10, spectrum, 1 -instance = comp, \z80_|alu_control_|db[6]~11 , z80_|alu_control_|db[6]~11, spectrum, 1 -instance = comp, \z80_|alu_control_|db[4]~30 , z80_|alu_control_|db[4]~30, spectrum, 1 -instance = comp, \z80_|alu_control_|db[4]~31 , z80_|alu_control_|db[4]~31, spectrum, 1 -instance = comp, \z80_|alu_control_|db[4]~32 , z80_|alu_control_|db[4]~32, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][4]~119 , ula_|zx_keyboard_|keys[2][4]~119, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][4]~120 , ula_|zx_keyboard_|keys[2][4]~120, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][4]~95 , ula_|zx_keyboard_|keys[2][4]~95, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][4]~121 , ula_|zx_keyboard_|keys[2][4]~121, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][4] , ula_|zx_keyboard_|keys[2][4], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][4]~117 , ula_|zx_keyboard_|keys[3][4]~117, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][4]~136 , ula_|zx_keyboard_|keys[3][4]~136, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][4]~130 , ula_|zx_keyboard_|keys[3][4]~130, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][4]~118 , ula_|zx_keyboard_|keys[3][4]~118, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][4] , ula_|zx_keyboard_|keys[3][4], spectrum, 1 -instance = comp, \D[4]~78 , D[4]~78, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][4]~126 , ula_|zx_keyboard_|keys[6][4]~126, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][4]~128 , ula_|zx_keyboard_|keys[5][4]~128, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][4]~129 , ula_|zx_keyboard_|keys[5][4]~129, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][4] , ula_|zx_keyboard_|keys[5][4], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][4]~127 , ula_|zx_keyboard_|keys[6][4]~127, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][4] , ula_|zx_keyboard_|keys[6][4], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|Equal0~2 , ula_|zx_keyboard_|Equal0~2, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][4]~51 , ula_|zx_keyboard_|keys[7][4]~51, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][4]~125 , ula_|zx_keyboard_|keys[7][4]~125, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][4] , ula_|zx_keyboard_|keys[7][4], spectrum, 1 -instance = comp, \D[4]~79 , D[4]~79, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][4]~122 , ula_|zx_keyboard_|keys[4][4]~122, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][4]~123 , ula_|zx_keyboard_|keys[4][4]~123, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][4]~124 , ula_|zx_keyboard_|keys[4][4]~124, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][4] , ula_|zx_keyboard_|keys[4][4], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|key_row~3 , ula_|zx_keyboard_|key_row~3, spectrum, 1 -instance = comp, \D[4]~80 , D[4]~80, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][4]~111 , ula_|zx_keyboard_|keys[0][4]~111, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][4]~97 , ula_|zx_keyboard_|keys[0][4]~97, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][4]~116 , ula_|zx_keyboard_|keys[0][4]~116, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][4] , ula_|zx_keyboard_|keys[0][4], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][4]~115 , ula_|zx_keyboard_|keys[1][4]~115, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][4] , ula_|zx_keyboard_|keys[1][4], spectrum, 1 -instance = comp, \D[4]~77 , D[4]~77, spectrum, 1 -instance = comp, \D[4]~81 , D[4]~81, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a12 , rom|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a12 , ram0|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a4 , rom|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a4 , ram0|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 -instance = comp, \Selector4~0 , Selector4~0, spectrum, 1 -instance = comp, \Selector4~1 , Selector4~1, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a28 , ram1|altsyncram_component|auto_generated|ram_block1a28, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a12 , ram1|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a20 , ram1|altsyncram_component|auto_generated|ram_block1a20, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a4 , ram1|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 , ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 , ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3, spectrum, 1 -instance = comp, \D[4]~109 , D[4]~109, spectrum, 1 -instance = comp, \D[4]~97 , D[4]~97, spectrum, 1 -instance = comp, \D[4]~98 , D[4]~98, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] , z80_|data_pins_|SYNTHESIZED_WIRE_0[4], spectrum, 1 -instance = comp, \z80_|data_pins_|dout[4] , z80_|data_pins_|dout[4], spectrum, 1 -instance = comp, \z80_|bus_control_|db[4]~18 , z80_|bus_control_|db[4]~18, spectrum, 1 -instance = comp, \z80_|bus_control_|db[4]~19 , z80_|bus_control_|db[4]~19, spectrum, 1 -instance = comp, \z80_|ir_|opcode[4] , z80_|ir_|opcode[4], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal21~0 , z80_|pla_decode_|Equal21~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~5 , z80_|execute_|ctl_mRead~5, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~2 , z80_|execute_|fIOWrite~2, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~3 , z80_|execute_|fIOWrite~3, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~4 , z80_|execute_|fIOWrite~4, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~5 , z80_|execute_|fIOWrite~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~11 , z80_|execute_|ctl_mWrite~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~12 , z80_|execute_|ctl_mWrite~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~13 , z80_|execute_|ctl_mWrite~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~14 , z80_|execute_|ctl_mWrite~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~15 , z80_|execute_|ctl_mWrite~15, spectrum, 1 -instance = comp, \z80_|memory_ifc_|DFFE_mwr_ff1 , z80_|memory_ifc_|DFFE_mwr_ff1, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_mwr~feeder , z80_|memory_ifc_|wait_mwr~feeder, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_mwr , z80_|memory_ifc_|wait_mwr, spectrum, 1 -instance = comp, \z80_|memory_ifc_|mwr_wr , z80_|memory_ifc_|mwr_wr, spectrum, 1 -instance = comp, \z80_|memory_ifc_|nWR_out~0 , z80_|memory_ifc_|nWR_out~0, spectrum, 1 -instance = comp, \D[5]~84 , D[5]~84, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a23 , ram1|altsyncram_component|auto_generated|ram_block1a23, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a7 , ram1|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a15 , ram1|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 , ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a31 , ram1|altsyncram_component|auto_generated|ram_block1a31, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 , ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a15 , ram0|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a15 , rom|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a7 , rom|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a7 , ram0|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 -instance = comp, \Mux0~0 , Mux0~0, spectrum, 1 -instance = comp, \Mux0~1 , Mux0~1, spectrum, 1 -instance = comp, \D[7]~112 , D[7]~112, spectrum, 1 -instance = comp, \D[7]~94 , D[7]~94, spectrum, 1 -instance = comp, \D[7]~102 , D[7]~102, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] , z80_|data_pins_|SYNTHESIZED_WIRE_0[7], spectrum, 1 -instance = comp, \z80_|data_pins_|dout[7] , z80_|data_pins_|dout[7], spectrum, 1 -instance = comp, \z80_|bus_control_|db[7]~5 , z80_|bus_control_|db[7]~5, spectrum, 1 -instance = comp, \z80_|bus_control_|db[7]~7 , z80_|bus_control_|db[7]~7, spectrum, 1 -instance = comp, \z80_|ir_|opcode[7] , z80_|ir_|opcode[7], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal77~0 , z80_|pla_decode_|Equal77~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~5 , z80_|execute_|ctl_mWrite~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 , z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~3 , z80_|execute_|ctl_bus_db_we~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~8 , z80_|execute_|ctl_bus_db_we~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~2 , z80_|execute_|ctl_bus_db_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~4 , z80_|execute_|ctl_bus_db_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~6 , z80_|execute_|ctl_bus_db_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~7 , z80_|execute_|ctl_bus_db_we~7, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][2]~50 , ula_|zx_keyboard_|keys[0][2]~50, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][2]~52 , ula_|zx_keyboard_|keys[0][2]~52, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][2] , ula_|zx_keyboard_|keys[0][2], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][3]~48 , ula_|zx_keyboard_|keys[3][3]~48, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][2]~49 , ula_|zx_keyboard_|keys[1][2]~49, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][2] , ula_|zx_keyboard_|keys[1][2], spectrum, 1 -instance = comp, \D[2]~35 , D[2]~35, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][2]~57 , ula_|zx_keyboard_|keys[5][2]~57, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][2]~58 , ula_|zx_keyboard_|keys[5][2]~58, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][2] , ula_|zx_keyboard_|keys[5][2], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][2]~59 , ula_|zx_keyboard_|keys[4][2]~59, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][2]~131 , ula_|zx_keyboard_|keys[4][2]~131, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][2]~60 , ula_|zx_keyboard_|keys[4][2]~60, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][2] , ula_|zx_keyboard_|keys[4][2], spectrum, 1 -instance = comp, \D[2]~37 , D[2]~37, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][2]~53 , ula_|zx_keyboard_|keys[3][2]~53, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][2]~55 , ula_|zx_keyboard_|keys[2][2]~55, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][2]~56 , ula_|zx_keyboard_|keys[2][2]~56, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][2] , ula_|zx_keyboard_|keys[2][2], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][2]~54 , ula_|zx_keyboard_|keys[3][2]~54, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][2] , ula_|zx_keyboard_|keys[3][2], spectrum, 1 -instance = comp, \D[2]~36 , D[2]~36, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][2]~68 , ula_|zx_keyboard_|keys[6][2]~68, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][2]~69 , ula_|zx_keyboard_|keys[6][2]~69, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][2]~70 , ula_|zx_keyboard_|keys[6][2]~70, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][2] , ula_|zx_keyboard_|keys[6][2], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2]~61 , ula_|zx_keyboard_|keys[7][2]~61, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2]~62 , ula_|zx_keyboard_|keys[7][2]~62, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2]~64 , ula_|zx_keyboard_|keys[7][2]~64, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2]~65 , ula_|zx_keyboard_|keys[7][2]~65, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|Selector13~0 , ula_|zx_keyboard_|Selector13~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2]~66 , ula_|zx_keyboard_|keys[7][2]~66, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2] , ula_|zx_keyboard_|keys[7][2], spectrum, 1 -instance = comp, \D[2]~38 , D[2]~38, spectrum, 1 -instance = comp, \D[2]~39 , D[2]~39, spectrum, 1 -instance = comp, \D[2]~104 , D[2]~104, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a26 , ram1|altsyncram_component|auto_generated|ram_block1a26, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a10 , ram1|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a18 , ram1|altsyncram_component|auto_generated|ram_block1a18, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a2 , ram1|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 -instance = comp, \D[2]~43 , D[2]~43, spectrum, 1 -instance = comp, \D[2]~44 , D[2]~44, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a10 , rom|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a10 , ram0|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 -instance = comp, \D[2]~40 , D[2]~40, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a2 , ram0|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a2 , rom|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 -instance = comp, \D[2]~41 , D[2]~41, spectrum, 1 -instance = comp, \D[2]~42 , D[2]~42, spectrum, 1 -instance = comp, \D[2]~105 , D[2]~105, spectrum, 1 -instance = comp, \D[2]~45 , D[2]~45, spectrum, 1 -instance = comp, \D[2]~46 , D[2]~46, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] , z80_|data_pins_|SYNTHESIZED_WIRE_0[2], spectrum, 1 -instance = comp, \z80_|data_pins_|dout[2] , z80_|data_pins_|dout[2], spectrum, 1 -instance = comp, \z80_|bus_control_|db[2]~12 , z80_|bus_control_|db[2]~12, spectrum, 1 -instance = comp, \z80_|bus_control_|db[2]~13 , z80_|bus_control_|db[2]~13, spectrum, 1 -instance = comp, \z80_|ir_|opcode[2] , z80_|ir_|opcode[2], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal3~1 , z80_|pla_decode_|Equal3~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal43~0 , z80_|pla_decode_|Equal43~0, spectrum, 1 -instance = comp, \z80_|interrupts_|test1~2 , z80_|interrupts_|test1~2, spectrum, 1 -instance = comp, \z80_|interrupts_|test1~3 , z80_|interrupts_|test1~3, spectrum, 1 -instance = comp, \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED , z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED, spectrum, 1 -instance = comp, \z80_|clk_delay_|SYNTHESIZED_WIRE_4 , z80_|clk_delay_|SYNTHESIZED_WIRE_4, spectrum, 1 -instance = comp, \z80_|clk_delay_|SYNTHESIZED_WIRE_7 , z80_|clk_delay_|SYNTHESIZED_WIRE_7, spectrum, 1 -instance = comp, \z80_|clk_delay_|hold_clk_iorq , z80_|clk_delay_|hold_clk_iorq, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_T1_ff , z80_|sequencer_|DFFE_T1_ff, spectrum, 1 -instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_13 , z80_|sequencer_|SYNTHESIZED_WIRE_13, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_T2_ff , z80_|sequencer_|DFFE_T2_ff, spectrum, 1 -instance = comp, \z80_|resets_|x3 , z80_|resets_|x3, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_12 , z80_|resets_|SYNTHESIZED_WIRE_12, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl , z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_M1_ff , z80_|sequencer_|DFFE_M1_ff, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_M2_ff~0 , z80_|sequencer_|DFFE_M2_ff~0, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_M2_ff , z80_|sequencer_|DFFE_M2_ff, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~3 , z80_|execute_|ctl_mWrite~3, spectrum, 1 -instance = comp, \z80_|execute_|nextM~11 , z80_|execute_|nextM~11, spectrum, 1 -instance = comp, \z80_|execute_|nextM~8 , z80_|execute_|nextM~8, spectrum, 1 -instance = comp, \z80_|execute_|nextM~9 , z80_|execute_|nextM~9, spectrum, 1 -instance = comp, \z80_|execute_|nextM~10 , z80_|execute_|nextM~10, spectrum, 1 -instance = comp, \z80_|execute_|nextM~12 , z80_|execute_|nextM~12, spectrum, 1 -instance = comp, \z80_|execute_|nextM~15 , z80_|execute_|nextM~15, spectrum, 1 -instance = comp, \z80_|execute_|nextM~6 , z80_|execute_|nextM~6, spectrum, 1 -instance = comp, \z80_|execute_|nextM~7 , z80_|execute_|nextM~7, spectrum, 1 -instance = comp, \z80_|execute_|nextM~13 , z80_|execute_|nextM~13, spectrum, 1 -instance = comp, \z80_|execute_|setM1~39 , z80_|execute_|setM1~39, spectrum, 1 -instance = comp, \z80_|execute_|nextM~5 , z80_|execute_|nextM~5, spectrum, 1 -instance = comp, \z80_|execute_|nextM~14 , z80_|execute_|nextM~14, spectrum, 1 -instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_15 , z80_|sequencer_|SYNTHESIZED_WIRE_15, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_T4_ff , z80_|sequencer_|DFFE_T4_ff, spectrum, 1 -instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_16 , z80_|sequencer_|SYNTHESIZED_WIRE_16, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_T5_ff , z80_|sequencer_|DFFE_T5_ff, spectrum, 1 -instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_17 , z80_|sequencer_|SYNTHESIZED_WIRE_17, spectrum, 1 -instance = comp, \z80_|sequencer_|T6 , z80_|sequencer_|T6, spectrum, 1 -instance = comp, \z80_|execute_|setM1~13 , z80_|execute_|setM1~13, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal77~1 , z80_|pla_decode_|Equal77~1, spectrum, 1 -instance = comp, \z80_|execute_|setM1~12 , z80_|execute_|setM1~12, spectrum, 1 -instance = comp, \z80_|execute_|setM1~14 , z80_|execute_|setM1~14, spectrum, 1 -instance = comp, \z80_|execute_|setM1~41 , z80_|execute_|setM1~41, spectrum, 1 -instance = comp, \z80_|execute_|setM1~42 , z80_|execute_|setM1~42, spectrum, 1 -instance = comp, \z80_|execute_|setM1~43 , z80_|execute_|setM1~43, spectrum, 1 -instance = comp, \z80_|execute_|setM1~44 , z80_|execute_|setM1~44, spectrum, 1 -instance = comp, \z80_|execute_|setM1~50 , z80_|execute_|setM1~50, spectrum, 1 -instance = comp, \z80_|execute_|setM1~51 , z80_|execute_|setM1~51, spectrum, 1 -instance = comp, \z80_|execute_|setM1~6 , z80_|execute_|setM1~6, spectrum, 1 -instance = comp, \z80_|execute_|setM1~7 , z80_|execute_|setM1~7, spectrum, 1 -instance = comp, \z80_|execute_|setM1~8 , z80_|execute_|setM1~8, spectrum, 1 -instance = comp, \z80_|execute_|setM1~9 , z80_|execute_|setM1~9, spectrum, 1 -instance = comp, \z80_|execute_|setM1~10 , z80_|execute_|setM1~10, spectrum, 1 -instance = comp, \z80_|execute_|setM1~11 , z80_|execute_|setM1~11, spectrum, 1 -instance = comp, \z80_|execute_|setM1~17 , z80_|execute_|setM1~17, spectrum, 1 -instance = comp, \z80_|execute_|setM1~31 , z80_|execute_|setM1~31, spectrum, 1 -instance = comp, \z80_|execute_|setM1~28 , z80_|execute_|setM1~28, spectrum, 1 -instance = comp, \z80_|execute_|setM1~30 , z80_|execute_|setM1~30, spectrum, 1 -instance = comp, \z80_|execute_|setM1~32 , z80_|execute_|setM1~32, spectrum, 1 -instance = comp, \z80_|execute_|setM1~33 , z80_|execute_|setM1~33, spectrum, 1 -instance = comp, \z80_|execute_|setM1~25 , z80_|execute_|setM1~25, spectrum, 1 -instance = comp, \z80_|execute_|setM1~26 , z80_|execute_|setM1~26, spectrum, 1 -instance = comp, \z80_|execute_|setM1~24 , z80_|execute_|setM1~24, spectrum, 1 -instance = comp, \z80_|execute_|setM1~27 , z80_|execute_|setM1~27, spectrum, 1 -instance = comp, \z80_|execute_|setM1~22 , z80_|execute_|setM1~22, spectrum, 1 -instance = comp, \z80_|execute_|setM1~21 , z80_|execute_|setM1~21, spectrum, 1 -instance = comp, \z80_|execute_|setM1~53 , z80_|execute_|setM1~53, spectrum, 1 -instance = comp, \z80_|execute_|setM1~23 , z80_|execute_|setM1~23, spectrum, 1 -instance = comp, \z80_|execute_|setM1~18 , z80_|execute_|setM1~18, spectrum, 1 -instance = comp, \z80_|execute_|setM1~19 , z80_|execute_|setM1~19, spectrum, 1 -instance = comp, \z80_|execute_|setM1~20 , z80_|execute_|setM1~20, spectrum, 1 -instance = comp, \z80_|execute_|setM1~34 , z80_|execute_|setM1~34, spectrum, 1 -instance = comp, \z80_|execute_|setM1~52 , z80_|execute_|setM1~52, spectrum, 1 -instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_14 , z80_|sequencer_|SYNTHESIZED_WIRE_14, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_T3_ff , z80_|sequencer_|DFFE_T3_ff, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 , z80_|execute_|ctl_reg_sys_hilo_1M1T3_3, spectrum, 1 -instance = comp, \z80_|decode_state_|in_halt~0 , z80_|decode_state_|in_halt~0, spectrum, 1 -instance = comp, \z80_|decode_state_|in_halt~1 , z80_|decode_state_|in_halt~1, spectrum, 1 -instance = comp, \z80_|decode_state_|in_halt , z80_|decode_state_|in_halt, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~2 , z80_|execute_|ctl_bus_db_oe~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~5 , z80_|execute_|ctl_bus_db_oe~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~6 , z80_|execute_|ctl_bus_db_oe~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~4 , z80_|execute_|ctl_bus_db_oe~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe , z80_|execute_|ctl_bus_db_oe, spectrum, 1 -instance = comp, \z80_|bus_control_|db[0]~6 , z80_|bus_control_|db[0]~6, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][3]~93 , ula_|zx_keyboard_|keys[1][3]~93, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][3]~94 , ula_|zx_keyboard_|keys[1][3]~94, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][3] , ula_|zx_keyboard_|keys[1][3], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][3]~96 , ula_|zx_keyboard_|keys[0][3]~96, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][3]~98 , ula_|zx_keyboard_|keys[0][3]~98, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][3] , ula_|zx_keyboard_|keys[0][3], spectrum, 1 -instance = comp, \D[3]~65 , D[3]~65, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][3]~99 , ula_|zx_keyboard_|keys[3][3]~99, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][3]~100 , ula_|zx_keyboard_|keys[3][3]~100, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][3] , ula_|zx_keyboard_|keys[3][3], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][3]~101 , ula_|zx_keyboard_|keys[2][3]~101, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][3]~102 , ula_|zx_keyboard_|keys[2][3]~102, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][3]~133 , ula_|zx_keyboard_|keys[2][3]~133, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][3]~103 , ula_|zx_keyboard_|keys[2][3]~103, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][3] , ula_|zx_keyboard_|keys[2][3], spectrum, 1 -instance = comp, \D[3]~66 , D[3]~66, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][3]~103 , ula_|zx_keyboard_|keys[5][3]~103, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][4]~20 , ula_|zx_keyboard_|keys[5][4]~20, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][4]~21 , ula_|zx_keyboard_|keys[1][4]~21, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[5][3]~104 , ula_|zx_keyboard_|keys[5][3]~104, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][3]~105 , ula_|zx_keyboard_|keys[5][3]~105, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[5][3] , ula_|zx_keyboard_|keys[5][3], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3]~106 , ula_|zx_keyboard_|keys[4][3]~106, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|Selector5~1 , ula_|zx_keyboard_|Selector5~1, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][0]~73 , ula_|zx_keyboard_|keys[3][0]~73, spectrum, 1 instance = comp, \ula_|zx_keyboard_|Selector5~0 , ula_|zx_keyboard_|Selector5~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3]~134 , ula_|zx_keyboard_|keys[4][3]~134, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|Selector5~1 , ula_|zx_keyboard_|Selector5~1, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3]~129 , ula_|zx_keyboard_|keys[4][3]~129, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr16~1 , ula_|zx_keyboard_|WideOr16~1, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3]~105 , ula_|zx_keyboard_|keys[4][3]~105, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3]~106 , ula_|zx_keyboard_|keys[4][3]~106, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3]~130 , ula_|zx_keyboard_|keys[4][3]~130, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[4][3]~107 , ula_|zx_keyboard_|keys[4][3]~107, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3]~135 , ula_|zx_keyboard_|keys[4][3]~135, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3]~108 , ula_|zx_keyboard_|keys[4][3]~108, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[4][3] , ula_|zx_keyboard_|keys[4][3], spectrum, 1 -instance = comp, \D[3]~67 , D[3]~67, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][3]~112 , ula_|zx_keyboard_|keys[7][3]~112, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][3]~113 , ula_|zx_keyboard_|keys[7][3]~113, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][3]~114 , ula_|zx_keyboard_|keys[7][3]~114, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][3] , ula_|zx_keyboard_|keys[7][3], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][3]~109 , ula_|zx_keyboard_|keys[6][3]~109, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][3]~110 , ula_|zx_keyboard_|keys[6][3]~110, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][3]~137 , ula_|zx_keyboard_|keys[6][3]~137, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][3]~138 , ula_|zx_keyboard_|keys[6][3]~138, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][3] , ula_|zx_keyboard_|keys[6][3], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|key_row~2 , ula_|zx_keyboard_|key_row~2, spectrum, 1 -instance = comp, \D[3]~68 , D[3]~68, spectrum, 1 -instance = comp, \D[3]~69 , D[3]~69, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a19 , ram1|altsyncram_component|auto_generated|ram_block1a19, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a3 , ram1|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a11 , ram1|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 -instance = comp, \D[3]~73 , D[3]~73, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a27 , ram1|altsyncram_component|auto_generated|ram_block1a27, spectrum, 1 instance = comp, \D[3]~74 , D[3]~74, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a11 , rom|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a11 , ram0|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 -instance = comp, \D[3]~70 , D[3]~70, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a3 , rom|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 -instance = comp, \D[3]~71 , D[3]~71, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a3 , ram0|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1]~39 , ula_|zx_keyboard_|keys[5][1]~39, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][3]~100 , ula_|zx_keyboard_|keys[2][3]~100, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][3]~101 , ula_|zx_keyboard_|keys[2][3]~101, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][3]~99 , ula_|zx_keyboard_|keys[2][3]~99, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][3]~102 , ula_|zx_keyboard_|keys[2][3]~102, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][3] , ula_|zx_keyboard_|keys[2][3], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][3]~97 , ula_|zx_keyboard_|keys[3][3]~97, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][3]~98 , ula_|zx_keyboard_|keys[3][3]~98, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][3] , ula_|zx_keyboard_|keys[3][3], spectrum, 1 +instance = comp, \D[3]~73 , D[3]~73, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][4]~108 , ula_|zx_keyboard_|keys[0][4]~108, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][3]~109 , ula_|zx_keyboard_|keys[7][3]~109, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][3]~110 , ula_|zx_keyboard_|keys[7][3]~110, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][3] , ula_|zx_keyboard_|keys[7][3], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][3]~111 , ula_|zx_keyboard_|keys[6][3]~111, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][3]~112 , ula_|zx_keyboard_|keys[6][3]~112, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][3]~132 , ula_|zx_keyboard_|keys[6][3]~132, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][3]~133 , ula_|zx_keyboard_|keys[6][3]~133, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][3] , ula_|zx_keyboard_|keys[6][3], spectrum, 1 +instance = comp, \D[3]~75 , D[3]~75, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][3]~94 , ula_|zx_keyboard_|keys[0][3]~94, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][4]~93 , ula_|zx_keyboard_|keys[2][4]~93, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][4]~95 , ula_|zx_keyboard_|keys[0][4]~95, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][3]~96 , ula_|zx_keyboard_|keys[0][3]~96, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][3] , ula_|zx_keyboard_|keys[0][3], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][3]~91 , ula_|zx_keyboard_|keys[1][3]~91, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][3]~92 , ula_|zx_keyboard_|keys[1][3]~92, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][3] , ula_|zx_keyboard_|keys[1][3], spectrum, 1 instance = comp, \D[3]~72 , D[3]~72, spectrum, 1 +instance = comp, \D[3]~76 , D[3]~76, spectrum, 1 +instance = comp, \D[3]~122 , D[3]~122, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a3 , ram1|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 +instance = comp, \D[3]~79 , D[3]~79, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a11 , ram1|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a27 , ram1|altsyncram_component|auto_generated|ram_block1a27, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a19 , ram1|altsyncram_component|auto_generated|ram_block1a19, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a3 , rom|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 +instance = comp, \D[3]~77 , D[3]~77, spectrum, 1 +instance = comp, \D[3]~80 , D[3]~80, spectrum, 1 +instance = comp, \D[3]~81 , D[3]~81, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a3 , ram0|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 +instance = comp, \D[3]~124 , D[3]~124, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a11 , ram0|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a11 , rom|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 +instance = comp, \D[3]~123 , D[3]~123, spectrum, 1 +instance = comp, \D[3]~78 , D[3]~78, spectrum, 1 +instance = comp, \D[3]~82 , D[3]~82, spectrum, 1 instance = comp, \D[3]~108 , D[3]~108, spectrum, 1 -instance = comp, \D[3]~95 , D[3]~95, spectrum, 1 -instance = comp, \D[3]~96 , D[3]~96, spectrum, 1 +instance = comp, \D[3]~109 , D[3]~109, spectrum, 1 instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] , z80_|data_pins_|SYNTHESIZED_WIRE_0[3], spectrum, 1 instance = comp, \z80_|data_pins_|dout[3] , z80_|data_pins_|dout[3], spectrum, 1 instance = comp, \z80_|bus_control_|db[3]~20 , z80_|bus_control_|db[3]~20, spectrum, 1 instance = comp, \z80_|bus_control_|db[3]~21 , z80_|bus_control_|db[3]~21, spectrum, 1 instance = comp, \z80_|ir_|opcode[3] , z80_|ir_|opcode[3], spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~4 , z80_|execute_|ctl_mWrite~4, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal33~1 , z80_|pla_decode_|Equal33~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_zero_oe~0 , z80_|execute_|ctl_bus_zero_oe~0, spectrum, 1 +instance = comp, \z80_|bus_control_|db[0]~4 , z80_|bus_control_|db[0]~4, spectrum, 1 +instance = comp, \z80_|bus_control_|db[7]~5 , z80_|bus_control_|db[7]~5, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a23 , ram1|altsyncram_component|auto_generated|ram_block1a23, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a31 , ram1|altsyncram_component|auto_generated|ram_block1a31, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a15 , ram1|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a7 , ram1|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2 , ram1|altsyncram_component|auto_generated|mux2|result_node[7]~2, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3 , ram1|altsyncram_component|auto_generated|mux2|result_node[7]~3, spectrum, 1 +instance = comp, \D[5]~97 , D[5]~97, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a15 , ram0|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a15 , rom|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a7 , ram0|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a7 , rom|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 +instance = comp, \Mux0~0 , Mux0~0, spectrum, 1 +instance = comp, \Mux0~1 , Mux0~1, spectrum, 1 +instance = comp, \D[7]~116 , D[7]~116, spectrum, 1 +instance = comp, \D[7]~117 , D[7]~117, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] , z80_|data_pins_|SYNTHESIZED_WIRE_0[7], spectrum, 1 +instance = comp, \z80_|data_pins_|dout[7] , z80_|data_pins_|dout[7], spectrum, 1 +instance = comp, \z80_|bus_control_|db[7]~7 , z80_|bus_control_|db[7]~7, spectrum, 1 +instance = comp, \z80_|ir_|opcode[7] , z80_|ir_|opcode[7], spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal41~0 , z80_|pla_decode_|Equal41~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal41~1 , z80_|pla_decode_|Equal41~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal41~2 , z80_|pla_decode_|Equal41~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_tbl_cb_set , z80_|execute_|ctl_state_tbl_cb_set, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_tbl_we~8 , z80_|execute_|ctl_state_tbl_we~8, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instCB , z80_|decode_state_|DFFE_instCB, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal52~0 , z80_|pla_decode_|Equal52~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_66_oe~2 , z80_|execute_|ctl_66_oe~2, spectrum, 1 +instance = comp, \z80_|interrupts_|im1 , z80_|interrupts_|im1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_ff_oe~0 , z80_|execute_|ctl_bus_ff_oe~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_ff_oe~1 , z80_|execute_|ctl_bus_ff_oe~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~2 , z80_|execute_|ctl_bus_db_oe~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~5 , z80_|execute_|ctl_bus_db_oe~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~6 , z80_|execute_|ctl_bus_db_oe~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~4 , z80_|execute_|ctl_bus_db_oe~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe , z80_|execute_|ctl_bus_db_oe, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][0]~88 , ula_|zx_keyboard_|keys[6][0]~88, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|shifted~1 , ula_|zx_keyboard_|shifted~1, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][0]~89 , ula_|zx_keyboard_|keys[6][0]~89, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][0]~90 , ula_|zx_keyboard_|keys[6][0]~90, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][0] , ula_|zx_keyboard_|keys[6][0], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][0]~84 , ula_|zx_keyboard_|keys[7][0]~84, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][0]~78 , ula_|zx_keyboard_|keys[5][0]~78, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][0]~85 , ula_|zx_keyboard_|keys[7][0]~85, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][0]~86 , ula_|zx_keyboard_|keys[7][0]~86, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][0]~87 , ula_|zx_keyboard_|keys[7][0]~87, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][0] , ula_|zx_keyboard_|keys[7][0], spectrum, 1 +instance = comp, \D[0]~57 , D[0]~57, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][0]~81 , ula_|zx_keyboard_|keys[4][0]~81, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][0]~82 , ula_|zx_keyboard_|keys[4][0]~82, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1]~40 , ula_|zx_keyboard_|keys[5][1]~40, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][0]~83 , ula_|zx_keyboard_|keys[4][0]~83, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][0] , ula_|zx_keyboard_|keys[4][0], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][0]~79 , ula_|zx_keyboard_|keys[5][0]~79, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][0]~80 , ula_|zx_keyboard_|keys[5][0]~80, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][0] , ula_|zx_keyboard_|keys[5][0], spectrum, 1 +instance = comp, \D[0]~56 , D[0]~56, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][0]~76 , ula_|zx_keyboard_|keys[1][0]~76, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][0]~77 , ula_|zx_keyboard_|keys[1][0]~77, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][0] , ula_|zx_keyboard_|keys[1][0], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3]~68 , ula_|zx_keyboard_|keys[4][3]~68, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr0~0 , ula_|zx_keyboard_|WideOr0~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys~69 , ula_|zx_keyboard_|keys~69, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][0]~70 , ula_|zx_keyboard_|keys[0][0]~70, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][1]~27 , ula_|zx_keyboard_|keys[4][1]~27, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr4~0 , ula_|zx_keyboard_|WideOr4~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys~71 , ula_|zx_keyboard_|keys~71, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][0]~72 , ula_|zx_keyboard_|keys[0][0]~72, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][0] , ula_|zx_keyboard_|keys[0][0], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row~2 , ula_|zx_keyboard_|key_row~2, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][1]~22 , ula_|zx_keyboard_|keys[2][1]~22, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][0]~75 , ula_|zx_keyboard_|keys[2][0]~75, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][0] , ula_|zx_keyboard_|keys[2][0], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][1]~24 , ula_|zx_keyboard_|keys[3][1]~24, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][0]~74 , ula_|zx_keyboard_|keys[3][0]~74, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][0] , ula_|zx_keyboard_|keys[3][0], spectrum, 1 +instance = comp, \D[0]~54 , D[0]~54, spectrum, 1 +instance = comp, \D[0]~55 , D[0]~55, spectrum, 1 +instance = comp, \D[0]~58 , D[0]~58, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a16 , ram1|altsyncram_component|auto_generated|ram_block1a16, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a8 , ram1|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a24 , ram1|altsyncram_component|auto_generated|ram_block1a24, spectrum, 1 +instance = comp, \D[0]~62 , D[0]~62, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a0 , ram1|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 +instance = comp, \D[0]~63 , D[0]~63, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a8 , ram0|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a8 , rom|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 +instance = comp, \D[0]~59 , D[0]~59, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a0 , ram0|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a0 , rom|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 +instance = comp, \D[0]~60 , D[0]~60, spectrum, 1 +instance = comp, \D[0]~61 , D[0]~61, spectrum, 1 +instance = comp, \D[0]~120 , D[0]~120, spectrum, 1 +instance = comp, \D[0]~64 , D[0]~64, spectrum, 1 +instance = comp, \D[0]~65 , D[0]~65, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] , z80_|data_pins_|SYNTHESIZED_WIRE_0[0], spectrum, 1 +instance = comp, \z80_|data_pins_|dout[0] , z80_|data_pins_|dout[0], spectrum, 1 +instance = comp, \z80_|bus_control_|db[0]~16 , z80_|bus_control_|db[0]~16, spectrum, 1 +instance = comp, \z80_|bus_control_|db[0]~17 , z80_|bus_control_|db[0]~17, spectrum, 1 +instance = comp, \z80_|ir_|opcode[0] , z80_|ir_|opcode[0], spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal3~2 , z80_|pla_decode_|Equal3~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_iy_set~2 , z80_|execute_|ctl_state_iy_set~2, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instIY1 , z80_|decode_state_|DFFE_instIY1, spectrum, 1 +instance = comp, \z80_|decode_state_|use_ixiy , z80_|decode_state_|use_ixiy, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~12 , z80_|execute_|ixy_d~12, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~13 , z80_|execute_|ixy_d~13, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~14 , z80_|execute_|ixy_d~14, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~11 , z80_|execute_|ixy_d~11, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~15 , z80_|execute_|ixy_d~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~8 , z80_|execute_|ctl_flags_xy_we~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~9 , z80_|execute_|ctl_flags_xy_we~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~11 , z80_|execute_|ctl_alu_oe~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~12 , z80_|execute_|ctl_alu_oe~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~13 , z80_|execute_|ctl_alu_oe~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~14 , z80_|execute_|ctl_alu_oe~14, spectrum, 1 +instance = comp, \z80_|alu_|db[7]~9 , z80_|alu_|db[7]~9, spectrum, 1 +instance = comp, \z80_|alu_|db[1]~15 , z80_|alu_|db[1]~15, spectrum, 1 +instance = comp, \z80_|alu_|db[1]~16 , z80_|alu_|db[1]~16, spectrum, 1 +instance = comp, \z80_|alu_control_|db[1]~25 , z80_|alu_control_|db[1]~25, spectrum, 1 +instance = comp, \z80_|alu_control_|db[1]~26 , z80_|alu_control_|db[1]~26, spectrum, 1 +instance = comp, \z80_|sw1_|db_down[1]~2 , z80_|sw1_|db_down[1]~2, spectrum, 1 +instance = comp, \z80_|alu_control_|db[1]~27 , z80_|alu_control_|db[1]~27, spectrum, 1 +instance = comp, \z80_|bus_control_|db[1]~10 , z80_|bus_control_|db[1]~10, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1]~38 , ula_|zx_keyboard_|keys[5][1]~38, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1]~41 , ula_|zx_keyboard_|keys[5][1]~41, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1]~42 , ula_|zx_keyboard_|keys[5][1]~42, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1] , ula_|zx_keyboard_|keys[5][1], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][1]~30 , ula_|zx_keyboard_|keys[4][1]~30, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][1] , ula_|zx_keyboard_|keys[4][1], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row~0 , ula_|zx_keyboard_|key_row~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][1]~36 , ula_|zx_keyboard_|keys[7][1]~36, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr16~3 , ula_|zx_keyboard_|WideOr16~3, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr16~0 , ula_|zx_keyboard_|WideOr16~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr16~2 , ula_|zx_keyboard_|WideOr16~2, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr16~4 , ula_|zx_keyboard_|WideOr16~4, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][1]~37 , ula_|zx_keyboard_|keys[7][1]~37, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][1] , ula_|zx_keyboard_|keys[7][1], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1]~33 , ula_|zx_keyboard_|keys[6][1]~33, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1]~34 , ula_|zx_keyboard_|keys[6][1]~34, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1]~31 , ula_|zx_keyboard_|keys[6][1]~31, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1]~35 , ula_|zx_keyboard_|keys[6][1]~35, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1] , ula_|zx_keyboard_|keys[6][1], spectrum, 1 +instance = comp, \D[1]~32 , D[1]~32, spectrum, 1 +instance = comp, \D[1]~33 , D[1]~33, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][4]~16 , ula_|zx_keyboard_|keys[6][4]~16, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][1]~17 , ula_|zx_keyboard_|keys[1][1]~17, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][1]~18 , ula_|zx_keyboard_|keys[1][1]~18, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][1] , ula_|zx_keyboard_|keys[1][1], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][1]~12 , ula_|zx_keyboard_|keys[0][1]~12, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][1]~13 , ula_|zx_keyboard_|keys[0][1]~13, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][1]~10 , ula_|zx_keyboard_|keys[0][1]~10, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][1]~14 , ula_|zx_keyboard_|keys[0][1]~14, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][1] , ula_|zx_keyboard_|keys[0][1], spectrum, 1 +instance = comp, \D[1]~30 , D[1]~30, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][1]~25 , ula_|zx_keyboard_|keys[3][1]~25, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][1]~26 , ula_|zx_keyboard_|keys[3][1]~26, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][1] , ula_|zx_keyboard_|keys[3][1], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][1]~23 , ula_|zx_keyboard_|keys[2][1]~23, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][1] , ula_|zx_keyboard_|keys[2][1], spectrum, 1 +instance = comp, \D[1]~31 , D[1]~31, spectrum, 1 +instance = comp, \D[1]~34 , D[1]~34, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a9 , ram1|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a25 , ram1|altsyncram_component|auto_generated|ram_block1a25, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a17 , ram1|altsyncram_component|auto_generated|ram_block1a17, spectrum, 1 +instance = comp, \D[1]~38 , D[1]~38, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a1 , ram1|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 +instance = comp, \D[1]~39 , D[1]~39, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a1 , ram0|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a1 , rom|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a9 , rom|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a9 , ram0|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 +instance = comp, \D[1]~35 , D[1]~35, spectrum, 1 +instance = comp, \D[1]~36 , D[1]~36, spectrum, 1 +instance = comp, \D[1]~37 , D[1]~37, spectrum, 1 +instance = comp, \D[1]~118 , D[1]~118, spectrum, 1 +instance = comp, \D[1]~40 , D[1]~40, spectrum, 1 +instance = comp, \D[1]~41 , D[1]~41, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] , z80_|data_pins_|SYNTHESIZED_WIRE_0[1], spectrum, 1 +instance = comp, \z80_|data_pins_|dout[1] , z80_|data_pins_|dout[1], spectrum, 1 +instance = comp, \z80_|bus_control_|db[1]~11 , z80_|bus_control_|db[1]~11, spectrum, 1 +instance = comp, \z80_|ir_|opcode[1] , z80_|ir_|opcode[1], spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_tbl_ed_set , z80_|execute_|ctl_state_tbl_ed_set, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instED , z80_|decode_state_|DFFE_instED, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal6~0 , z80_|pla_decode_|Equal6~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~8 , z80_|execute_|ctl_mRead~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~2 , z80_|execute_|ctl_bus_db_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 , z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~3 , z80_|execute_|ctl_bus_db_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~8 , z80_|execute_|ctl_bus_db_we~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~4 , z80_|execute_|ctl_bus_db_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~6 , z80_|execute_|ctl_bus_db_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~7 , z80_|execute_|ctl_bus_db_we~7, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][4]~126 , ula_|zx_keyboard_|keys[6][4]~126, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][4] , ula_|zx_keyboard_|keys[6][4], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][4]~125 , ula_|zx_keyboard_|keys[7][4]~125, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][4] , ula_|zx_keyboard_|keys[7][4], spectrum, 1 +instance = comp, \D[4]~88 , D[4]~88, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][4]~120 , ula_|zx_keyboard_|keys[5][4]~120, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][4]~121 , ula_|zx_keyboard_|keys[5][4]~121, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][4] , ula_|zx_keyboard_|keys[5][4], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][4]~122 , ula_|zx_keyboard_|keys[4][4]~122, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][4]~123 , ula_|zx_keyboard_|keys[4][4]~123, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][4]~124 , ula_|zx_keyboard_|keys[4][4]~124, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][4] , ula_|zx_keyboard_|keys[4][4], spectrum, 1 +instance = comp, \D[4]~87 , D[4]~87, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][4]~115 , ula_|zx_keyboard_|keys[2][4]~115, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][4]~116 , ula_|zx_keyboard_|keys[2][4]~116, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][4]~117 , ula_|zx_keyboard_|keys[2][4]~117, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][4] , ula_|zx_keyboard_|keys[2][4], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row~3 , ula_|zx_keyboard_|key_row~3, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][4]~118 , ula_|zx_keyboard_|keys[3][4]~118, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][4]~131 , ula_|zx_keyboard_|keys[3][4]~131, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][4]~119 , ula_|zx_keyboard_|keys[3][4]~119, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][4] , ula_|zx_keyboard_|keys[3][4], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][4]~114 , ula_|zx_keyboard_|keys[0][4]~114, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][4] , ula_|zx_keyboard_|keys[0][4], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][4]~113 , ula_|zx_keyboard_|keys[1][4]~113, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][4] , ula_|zx_keyboard_|keys[1][4], spectrum, 1 +instance = comp, \D[4]~85 , D[4]~85, spectrum, 1 +instance = comp, \D[4]~86 , D[4]~86, spectrum, 1 +instance = comp, \D[4]~89 , D[4]~89, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a4 , ram1|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a12 , ram1|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a28 , ram1|altsyncram_component|auto_generated|ram_block1a28, spectrum, 1 +instance = comp, \D[4]~93 , D[4]~93, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a20 , ram1|altsyncram_component|auto_generated|ram_block1a20, spectrum, 1 +instance = comp, \D[4]~94 , D[4]~94, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a4 , ram0|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a12 , ram0|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a12 , rom|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 +instance = comp, \D[4]~90 , D[4]~90, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a4 , rom|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 +instance = comp, \D[4]~91 , D[4]~91, spectrum, 1 +instance = comp, \D[4]~92 , D[4]~92, spectrum, 1 +instance = comp, \D[4]~125 , D[4]~125, spectrum, 1 +instance = comp, \D[4]~110 , D[4]~110, spectrum, 1 +instance = comp, \D[4]~111 , D[4]~111, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] , z80_|data_pins_|SYNTHESIZED_WIRE_0[4], spectrum, 1 +instance = comp, \z80_|data_pins_|dout[4] , z80_|data_pins_|dout[4], spectrum, 1 +instance = comp, \z80_|bus_control_|db[4]~18 , z80_|bus_control_|db[4]~18, spectrum, 1 +instance = comp, \z80_|bus_control_|db[4]~19 , z80_|bus_control_|db[4]~19, spectrum, 1 +instance = comp, \z80_|ir_|opcode[4] , z80_|ir_|opcode[4], spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal32~0 , z80_|pla_decode_|Equal32~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal36~0 , z80_|pla_decode_|Equal36~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal43~0 , z80_|pla_decode_|Equal43~0, spectrum, 1 +instance = comp, \z80_|interrupts_|test1~2 , z80_|interrupts_|test1~2, spectrum, 1 +instance = comp, \z80_|interrupts_|test1~3 , z80_|interrupts_|test1~3, spectrum, 1 +instance = comp, \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED , z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED, spectrum, 1 +instance = comp, \z80_|sw1_|db_down[5]~0 , z80_|sw1_|db_down[5]~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_36 , z80_|alu_flags_|SYNTHESIZED_WIRE_36, spectrum, 1 +instance = comp, \z80_|alu_flags_|flags_yf , z80_|alu_flags_|flags_yf, spectrum, 1 +instance = comp, \z80_|alu_control_|db[5]~15 , z80_|alu_control_|db[5]~15, spectrum, 1 +instance = comp, \z80_|alu_control_|db[5]~16 , z80_|alu_control_|db[5]~16, spectrum, 1 +instance = comp, \z80_|alu_control_|db[5]~17 , z80_|alu_control_|db[5]~17, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a13 , ram0|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a13 , rom|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a5 , ram0|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a5 , rom|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 +instance = comp, \Mux2~0 , Mux2~0, spectrum, 1 +instance = comp, \Mux2~1 , Mux2~1, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a29 , ram1|altsyncram_component|auto_generated|ram_block1a29, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a5 , ram1|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a13 , ram1|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0 , ram1|altsyncram_component|auto_generated|mux2|result_node[5]~0, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a21 , ram1|altsyncram_component|auto_generated|ram_block1a21, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1 , ram1|altsyncram_component|auto_generated|mux2|result_node[5]~1, spectrum, 1 +instance = comp, \D[5]~112 , D[5]~112, spectrum, 1 +instance = comp, \D[5]~113 , D[5]~113, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] , z80_|data_pins_|SYNTHESIZED_WIRE_0[5], spectrum, 1 +instance = comp, \z80_|data_pins_|dout[5] , z80_|data_pins_|dout[5], spectrum, 1 +instance = comp, \z80_|bus_control_|db[5]~14 , z80_|bus_control_|db[5]~14, spectrum, 1 +instance = comp, \z80_|bus_control_|db[5]~15 , z80_|bus_control_|db[5]~15, spectrum, 1 +instance = comp, \z80_|ir_|opcode[5] , z80_|ir_|opcode[5], spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~11 , z80_|execute_|ctl_mRead~11, spectrum, 1 +instance = comp, \z80_|execute_|setM1~46 , z80_|execute_|setM1~46, spectrum, 1 +instance = comp, \z80_|execute_|setM1~40 , z80_|execute_|setM1~40, spectrum, 1 +instance = comp, \z80_|execute_|nextM~5 , z80_|execute_|nextM~5, spectrum, 1 +instance = comp, \z80_|execute_|nextM~6 , z80_|execute_|nextM~6, spectrum, 1 +instance = comp, \z80_|execute_|nextM~7 , z80_|execute_|nextM~7, spectrum, 1 +instance = comp, \z80_|execute_|nextM~9 , z80_|execute_|nextM~9, spectrum, 1 +instance = comp, \z80_|execute_|nextM~10 , z80_|execute_|nextM~10, spectrum, 1 +instance = comp, \z80_|execute_|nextM~8 , z80_|execute_|nextM~8, spectrum, 1 +instance = comp, \z80_|execute_|nextM~12 , z80_|execute_|nextM~12, spectrum, 1 +instance = comp, \z80_|execute_|nextM~15 , z80_|execute_|nextM~15, spectrum, 1 +instance = comp, \z80_|execute_|nextM~13 , z80_|execute_|nextM~13, spectrum, 1 +instance = comp, \z80_|execute_|nextM~14 , z80_|execute_|nextM~14, spectrum, 1 +instance = comp, \z80_|sequencer_|ena_M , z80_|sequencer_|ena_M, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_T1_ff , z80_|sequencer_|DFFE_T1_ff, spectrum, 1 +instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_13 , z80_|sequencer_|SYNTHESIZED_WIRE_13, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_T2_ff , z80_|sequencer_|DFFE_T2_ff, spectrum, 1 +instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_14 , z80_|sequencer_|SYNTHESIZED_WIRE_14, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_T3_ff , z80_|sequencer_|DFFE_T3_ff, spectrum, 1 +instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_15 , z80_|sequencer_|SYNTHESIZED_WIRE_15, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_T4_ff , z80_|sequencer_|DFFE_T4_ff, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~9 , z80_|execute_|ctl_mWrite~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~0 , z80_|execute_|ctl_flags_sz_we~0, spectrum, 1 +instance = comp, \z80_|execute_|setM1~54 , z80_|execute_|setM1~54, spectrum, 1 +instance = comp, \z80_|execute_|setM1~25 , z80_|execute_|setM1~25, spectrum, 1 +instance = comp, \z80_|execute_|setM1~26 , z80_|execute_|setM1~26, spectrum, 1 +instance = comp, \z80_|execute_|setM1~27 , z80_|execute_|setM1~27, spectrum, 1 +instance = comp, \z80_|execute_|setM1~22 , z80_|execute_|setM1~22, spectrum, 1 +instance = comp, \z80_|execute_|setM1~55 , z80_|execute_|setM1~55, spectrum, 1 +instance = comp, \z80_|execute_|setM1~23 , z80_|execute_|setM1~23, spectrum, 1 +instance = comp, \z80_|execute_|setM1~24 , z80_|execute_|setM1~24, spectrum, 1 +instance = comp, \z80_|execute_|setM1~28 , z80_|execute_|setM1~28, spectrum, 1 +instance = comp, \z80_|execute_|setM1~11 , z80_|execute_|setM1~11, spectrum, 1 +instance = comp, \z80_|execute_|setM1~33 , z80_|execute_|setM1~33, spectrum, 1 +instance = comp, \z80_|execute_|setM1~29 , z80_|execute_|setM1~29, spectrum, 1 +instance = comp, \z80_|execute_|setM1~31 , z80_|execute_|setM1~31, spectrum, 1 +instance = comp, \z80_|execute_|setM1~32 , z80_|execute_|setM1~32, spectrum, 1 +instance = comp, \z80_|execute_|setM1~34 , z80_|execute_|setM1~34, spectrum, 1 +instance = comp, \z80_|execute_|setM1~20 , z80_|execute_|setM1~20, spectrum, 1 +instance = comp, \z80_|execute_|setM1~21 , z80_|execute_|setM1~21, spectrum, 1 +instance = comp, \z80_|execute_|setM1~35 , z80_|execute_|setM1~35, spectrum, 1 +instance = comp, \z80_|execute_|setM1~15 , z80_|execute_|setM1~15, spectrum, 1 +instance = comp, \z80_|execute_|setM1~14 , z80_|execute_|setM1~14, spectrum, 1 +instance = comp, \z80_|execute_|setM1~16 , z80_|execute_|setM1~16, spectrum, 1 +instance = comp, \z80_|execute_|setM1~10 , z80_|execute_|setM1~10, spectrum, 1 +instance = comp, \z80_|execute_|setM1~12 , z80_|execute_|setM1~12, spectrum, 1 +instance = comp, \z80_|execute_|setM1~8 , z80_|execute_|setM1~8, spectrum, 1 +instance = comp, \z80_|execute_|setM1~9 , z80_|execute_|setM1~9, spectrum, 1 +instance = comp, \z80_|execute_|setM1~13 , z80_|execute_|setM1~13, spectrum, 1 +instance = comp, \z80_|execute_|setM1~18 , z80_|execute_|setM1~18, spectrum, 1 +instance = comp, \z80_|execute_|setM1~19 , z80_|execute_|setM1~19, spectrum, 1 +instance = comp, \z80_|execute_|setM1~43 , z80_|execute_|setM1~43, spectrum, 1 +instance = comp, \z80_|execute_|setM1~42 , z80_|execute_|setM1~42, spectrum, 1 +instance = comp, \z80_|execute_|setM1~44 , z80_|execute_|setM1~44, spectrum, 1 +instance = comp, \z80_|execute_|setM1~45 , z80_|execute_|setM1~45, spectrum, 1 +instance = comp, \z80_|execute_|setM1~51 , z80_|execute_|setM1~51, spectrum, 1 +instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_17 , z80_|sequencer_|SYNTHESIZED_WIRE_17, spectrum, 1 +instance = comp, \z80_|sequencer_|T6 , z80_|sequencer_|T6, spectrum, 1 +instance = comp, \z80_|execute_|setM1~52 , z80_|execute_|setM1~52, spectrum, 1 +instance = comp, \z80_|execute_|setM1~53 , z80_|execute_|setM1~53, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_M1_ff~0 , z80_|sequencer_|DFFE_M1_ff~0, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_M1_ff , z80_|sequencer_|DFFE_M1_ff, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_M2_ff~0 , z80_|sequencer_|DFFE_M2_ff~0, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_M2_ff , z80_|sequencer_|DFFE_M2_ff, spectrum, 1 +instance = comp, \z80_|execute_|ctl_apin_mux~1 , z80_|execute_|ctl_apin_mux~1, spectrum, 1 instance = comp, \z80_|execute_|ctl_apin_mux~2 , z80_|execute_|ctl_apin_mux~2, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[0]~0 , z80_|address_pins_|DFFE_apin_latch[0]~0, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[0] , z80_|address_pins_|DFFE_apin_latch[0], spectrum, 1 -instance = comp, \D[0]~59 , D[0]~59, spectrum, 1 -instance = comp, \D[0]~60 , D[0]~60, spectrum, 1 -instance = comp, \D[1]~61 , D[1]~61, spectrum, 1 -instance = comp, \D[1]~62 , D[1]~62, spectrum, 1 -instance = comp, \D[2]~63 , D[2]~63, spectrum, 1 -instance = comp, \D[2]~64 , D[2]~64, spectrum, 1 -instance = comp, \D[3]~75 , D[3]~75, spectrum, 1 -instance = comp, \D[3]~76 , D[3]~76, spectrum, 1 -instance = comp, \D[4]~82 , D[4]~82, spectrum, 1 -instance = comp, \D[4]~83 , D[4]~83, spectrum, 1 -instance = comp, \D[6]~92 , D[6]~92, spectrum, 1 -instance = comp, \D[6]~93 , D[6]~93, spectrum, 1 +instance = comp, \D[0]~66 , D[0]~66, spectrum, 1 +instance = comp, \D[0]~67 , D[0]~67, spectrum, 1 +instance = comp, \D[0]~121 , D[0]~121, spectrum, 1 +instance = comp, \D[1]~68 , D[1]~68, spectrum, 1 +instance = comp, \D[1]~69 , D[1]~69, spectrum, 1 +instance = comp, \D[2]~70 , D[2]~70, spectrum, 1 +instance = comp, \D[2]~71 , D[2]~71, spectrum, 1 +instance = comp, \D[3]~83 , D[3]~83, spectrum, 1 +instance = comp, \D[3]~84 , D[3]~84, spectrum, 1 +instance = comp, \D[4]~95 , D[4]~95, spectrum, 1 +instance = comp, \D[4]~96 , D[4]~96, spectrum, 1 +instance = comp, \D[5]~126 , D[5]~126, spectrum, 1 +instance = comp, \D[5]~98 , D[5]~98, spectrum, 1 +instance = comp, \D[6]~105 , D[6]~105, spectrum, 1 +instance = comp, \D[6]~106 , D[6]~106, spectrum, 1 +instance = comp, \D[7]~128 , D[7]~128, spectrum, 1 +instance = comp, \D[7]~107 , D[7]~107, spectrum, 1 +instance = comp, \z80_|memory_ifc_|nIORQ_out~0 , z80_|memory_ifc_|nIORQ_out~0, spectrum, 1 instance = comp, \z80_|nM1_int~3 , z80_|nM1_int~3, spectrum, 1 instance = comp, \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 , z80_|memory_ifc_|SYNTHESIZED_WIRE_16, spectrum, 1 instance = comp, \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder , z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder, spectrum, 1 @@ -2839,7 +2866,6 @@ instance = comp, \z80_|memory_ifc_|DFFE_mreq_ff2 , z80_|memory_ifc_|DFFE_mreq_ff instance = comp, \z80_|memory_ifc_|nMREQ_out~0 , z80_|memory_ifc_|nMREQ_out~0, spectrum, 1 instance = comp, \z80_|memory_ifc_|nMREQ_out~1 , z80_|memory_ifc_|nMREQ_out~1, spectrum, 1 instance = comp, \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl , ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Idle~feeder , ula_|i2c_loader_|state.Idle~feeder, spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[0]~15 , ula_|i2c_loader_|divider[0]~15, spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[0] , ula_|i2c_loader_|divider[0], spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[1]~5 , ula_|i2c_loader_|divider[1]~5, spectrum, 1 @@ -2848,37 +2874,54 @@ instance = comp, \ula_|i2c_loader_|divider[2]~7 , ula_|i2c_loader_|divider[2]~7, instance = comp, \ula_|i2c_loader_|divider[2] , ula_|i2c_loader_|divider[2], spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[3]~9 , ula_|i2c_loader_|divider[3]~9, spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[3] , ula_|i2c_loader_|divider[3], spectrum, 1 +instance = comp, \ula_|i2c_loader_|WideAnd0~0 , ula_|i2c_loader_|WideAnd0~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[4]~11 , ula_|i2c_loader_|divider[4]~11, spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[4] , ula_|i2c_loader_|divider[4], spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[5]~13 , ula_|i2c_loader_|divider[5]~13, spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[5] , ula_|i2c_loader_|divider[5], spectrum, 1 -instance = comp, \ula_|i2c_loader_|WideAnd0~0 , ula_|i2c_loader_|WideAnd0~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|WideAnd0 , ula_|i2c_loader_|WideAnd0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|scl_out~_Duplicate_1 , ula_|i2c_loader_|scl_out~_Duplicate_1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Idle~feeder , ula_|i2c_loader_|state.Idle~feeder, spectrum, 1 instance = comp, \ula_|i2c_loader_|state.Idle , ula_|i2c_loader_|state.Idle, spectrum, 1 instance = comp, \ula_|i2c_loader_|phase~0 , ula_|i2c_loader_|phase~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|phase[0] , ula_|i2c_loader_|phase[0], spectrum, 1 instance = comp, \ula_|i2c_loader_|phase~1 , ula_|i2c_loader_|phase~1, spectrum, 1 instance = comp, \ula_|i2c_loader_|phase[1] , ula_|i2c_loader_|phase[1], spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit~5 , ula_|i2c_loader_|nbit~5, spectrum, 1 -instance = comp, \ula_|i2c_loader_|thisbyte[0]~8 , ula_|i2c_loader_|thisbyte[0]~8, spectrum, 1 instance = comp, \ula_|i2c_loader_|Mux42~0 , ula_|i2c_loader_|Mux42~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbyte~0 , ula_|i2c_loader_|nbyte~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit~4 , ula_|i2c_loader_|nbit~4, spectrum, 1 instance = comp, \ula_|i2c_loader_|nbyte~4 , ula_|i2c_loader_|nbyte~4, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbyte[1] , ula_|i2c_loader_|nbyte[1], spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[0]~1 , ula_|i2c_loader_|nbit[0]~1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[0]~2 , ula_|i2c_loader_|nbit[0]~2, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[0]~3 , ula_|i2c_loader_|nbit[0]~3, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[0] , ula_|i2c_loader_|nbit[0], spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit~5 , ula_|i2c_loader_|nbit~5, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[1] , ula_|i2c_loader_|nbit[1], spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Pause~1 , ula_|i2c_loader_|state.Pause~1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state~27 , ula_|i2c_loader_|state~27, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state~24 , ula_|i2c_loader_|state~24, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state~26 , ula_|i2c_loader_|state~26, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Data~0 , ula_|i2c_loader_|state.Data~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Data , ula_|i2c_loader_|state.Data, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit~0 , ula_|i2c_loader_|nbit~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[2] , ula_|i2c_loader_|nbit[2], spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Pause~0 , ula_|i2c_loader_|state.Pause~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Idle~0 , ula_|i2c_loader_|state.Idle~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Ack~0 , ula_|i2c_loader_|state.Ack~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Ack~1 , ula_|i2c_loader_|state.Ack~1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Ack , ula_|i2c_loader_|state.Ack, spectrum, 1 instance = comp, \ula_|i2c_loader_|thisbyte[0]~7 , ula_|i2c_loader_|thisbyte[0]~7, spectrum, 1 instance = comp, \I2C_SDAT~input , I2C_SDAT~input, spectrum, 1 instance = comp, \ula_|i2c_loader_|nbyte[0]~1 , ula_|i2c_loader_|nbyte[0]~1, spectrum, 1 instance = comp, \ula_|i2c_loader_|nbyte[0]~2 , ula_|i2c_loader_|nbyte[0]~2, spectrum, 1 instance = comp, \ula_|i2c_loader_|nbyte[0]~3 , ula_|i2c_loader_|nbyte[0]~3, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbyte[1] , ula_|i2c_loader_|nbyte[1], spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbyte[0] , ula_|i2c_loader_|nbyte[0], spectrum, 1 instance = comp, \ula_|i2c_loader_|state.Stop~0 , ula_|i2c_loader_|state.Stop~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|state.Stop~1 , ula_|i2c_loader_|state.Stop~1, spectrum, 1 instance = comp, \ula_|i2c_loader_|state.Stop , ula_|i2c_loader_|state.Stop, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Idle~0 , ula_|i2c_loader_|state.Idle~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit~0 , ula_|i2c_loader_|nbit~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[2] , ula_|i2c_loader_|nbit[2], spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Done~0 , ula_|i2c_loader_|state.Done~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Ack~0 , ula_|i2c_loader_|state.Ack~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Ack~1 , ula_|i2c_loader_|state.Ack~1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Ack , ula_|i2c_loader_|state.Ack, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Pause~2 , ula_|i2c_loader_|state.Pause~2, spectrum, 1 +instance = comp, \ula_|i2c_loader_|thisbyte[0]~8 , ula_|i2c_loader_|thisbyte[0]~8, spectrum, 1 instance = comp, \ula_|i2c_loader_|nbyte[1]~5 , ula_|i2c_loader_|nbyte[1]~5, spectrum, 1 instance = comp, \ula_|i2c_loader_|thisbyte[0]~18 , ula_|i2c_loader_|thisbyte[0]~18, spectrum, 1 instance = comp, \ula_|i2c_loader_|thisbyte[0] , ula_|i2c_loader_|thisbyte[0], spectrum, 1 @@ -2889,64 +2932,48 @@ instance = comp, \ula_|i2c_loader_|thisbyte[2] , ula_|i2c_loader_|thisbyte[2], s instance = comp, \ula_|i2c_loader_|thisbyte[3]~14 , ula_|i2c_loader_|thisbyte[3]~14, spectrum, 1 instance = comp, \ula_|i2c_loader_|thisbyte[3] , ula_|i2c_loader_|thisbyte[3], spectrum, 1 instance = comp, \ula_|i2c_loader_|Equal2~0 , ula_|i2c_loader_|Equal2~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Pause~0 , ula_|i2c_loader_|state.Pause~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|thisbyte[4]~16 , ula_|i2c_loader_|thisbyte[4]~16, spectrum, 1 instance = comp, \ula_|i2c_loader_|thisbyte[4] , ula_|i2c_loader_|thisbyte[4], spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Pause~1 , ula_|i2c_loader_|state.Pause~1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Done~2 , ula_|i2c_loader_|state.Done~2, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Pause~2 , ula_|i2c_loader_|state.Pause~2, spectrum, 1 instance = comp, \ula_|i2c_loader_|state.Pause~3 , ula_|i2c_loader_|state.Pause~3, spectrum, 1 +instance = comp, \ula_|i2c_loader_|scl_out~0 , ula_|i2c_loader_|scl_out~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Pause~4 , ula_|i2c_loader_|state.Pause~4, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Pause~5 , ula_|i2c_loader_|state.Pause~5, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Pause~6 , ula_|i2c_loader_|state.Pause~6, spectrum, 1 instance = comp, \ula_|i2c_loader_|state.Pause , ula_|i2c_loader_|state.Pause, spectrum, 1 instance = comp, \ula_|i2c_loader_|state~25 , ula_|i2c_loader_|state~25, spectrum, 1 instance = comp, \ula_|i2c_loader_|state.Start , ula_|i2c_loader_|state.Start, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbyte~0 , ula_|i2c_loader_|nbyte~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbyte[0] , ula_|i2c_loader_|nbyte[0], spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[0]~1 , ula_|i2c_loader_|nbit[0]~1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[0]~2 , ula_|i2c_loader_|nbit[0]~2, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[0]~3 , ula_|i2c_loader_|nbit[0]~3, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[0]~4 , ula_|i2c_loader_|nbit[0]~4, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[0] , ula_|i2c_loader_|nbit[0], spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit~6 , ula_|i2c_loader_|nbit~6, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[1] , ula_|i2c_loader_|nbit[1], spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Done~1 , ula_|i2c_loader_|state.Done~1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state~27 , ula_|i2c_loader_|state~27, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state~24 , ula_|i2c_loader_|state~24, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state~26 , ula_|i2c_loader_|state~26, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Data~0 , ula_|i2c_loader_|state.Data~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Data , ula_|i2c_loader_|state.Data, spectrum, 1 -instance = comp, \ula_|i2c_loader_|scl_out~0 , ula_|i2c_loader_|scl_out~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|scl_out~_Duplicate_1 , ula_|i2c_loader_|scl_out~_Duplicate_1, spectrum, 1 instance = comp, \ula_|i2c_loader_|scl_out~1 , ula_|i2c_loader_|scl_out~1, spectrum, 1 instance = comp, \ula_|i2c_loader_|scl_out~2 , ula_|i2c_loader_|scl_out~2, spectrum, 1 instance = comp, \ula_|i2c_loader_|scl_out , ula_|i2c_loader_|scl_out, spectrum, 1 instance = comp, \ula_|i2c_loader_|sda_out~_Duplicate_1 , ula_|i2c_loader_|sda_out~_Duplicate_1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~4 , ula_|i2c_loader_|shiftreg~4, spectrum, 1 instance = comp, \ula_|i2c_loader_|Mux35~0 , ula_|i2c_loader_|Mux35~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~13 , ula_|i2c_loader_|shiftreg~13, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~14 , ula_|i2c_loader_|shiftreg~14, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~15 , ula_|i2c_loader_|shiftreg~15, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[0]~24 , ula_|i2c_loader_|shiftreg[0]~24, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~4 , ula_|i2c_loader_|shiftreg~4, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~19 , ula_|i2c_loader_|shiftreg~19, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~20 , ula_|i2c_loader_|shiftreg~20, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~22 , ula_|i2c_loader_|shiftreg~22, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~23 , ula_|i2c_loader_|shiftreg~23, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[0]~25 , ula_|i2c_loader_|shiftreg[0]~25, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg[0]~6 , ula_|i2c_loader_|shiftreg[0]~6, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg[0]~7 , ula_|i2c_loader_|shiftreg[0]~7, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg[0]~8 , ula_|i2c_loader_|shiftreg[0]~8, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg[0] , ula_|i2c_loader_|shiftreg[0], spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~21 , ula_|i2c_loader_|shiftreg~21, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~22 , ula_|i2c_loader_|shiftreg~22, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~23 , ula_|i2c_loader_|shiftreg~23, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~24 , ula_|i2c_loader_|shiftreg~24, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg[6]~10 , ula_|i2c_loader_|shiftreg[6]~10, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg[6]~11 , ula_|i2c_loader_|shiftreg[6]~11, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[6]~12 , ula_|i2c_loader_|shiftreg[6]~12, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg[1] , ula_|i2c_loader_|shiftreg[1], spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~18 , ula_|i2c_loader_|shiftreg~18, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~19 , ula_|i2c_loader_|shiftreg~19, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~20 , ula_|i2c_loader_|shiftreg~20, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~21 , ula_|i2c_loader_|shiftreg~21, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg[2] , ula_|i2c_loader_|shiftreg[2], spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~16 , ula_|i2c_loader_|shiftreg~16, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg~17 , ula_|i2c_loader_|shiftreg~17, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~26 , ula_|i2c_loader_|shiftreg~26, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~15 , ula_|i2c_loader_|shiftreg~15, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~18 , ula_|i2c_loader_|shiftreg~18, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~27 , ula_|i2c_loader_|shiftreg~27, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg[3] , ula_|i2c_loader_|shiftreg[3], spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~25 , ula_|i2c_loader_|shiftreg~25, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~14 , ula_|i2c_loader_|shiftreg~14, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~16 , ula_|i2c_loader_|shiftreg~16, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~26 , ula_|i2c_loader_|shiftreg~26, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg[4] , ula_|i2c_loader_|shiftreg[4], spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~12 , ula_|i2c_loader_|shiftreg~12, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~13 , ula_|i2c_loader_|shiftreg~13, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg[5] , ula_|i2c_loader_|shiftreg[5], spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg~9 , ula_|i2c_loader_|shiftreg~9, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg[6] , ula_|i2c_loader_|shiftreg[6], spectrum, 1 @@ -2958,6 +2985,155 @@ instance = comp, \ula_|i2c_loader_|sda_out~2 , ula_|i2c_loader_|sda_out~2, spect instance = comp, \ula_|i2c_loader_|sda_out~3 , ula_|i2c_loader_|sda_out~3, spectrum, 1 instance = comp, \ula_|i2c_loader_|sda_out~4 , ula_|i2c_loader_|sda_out~4, spectrum, 1 instance = comp, \ula_|i2c_loader_|sda_out , ula_|i2c_loader_|sda_out, spectrum, 1 +instance = comp, \sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1 , sdram_|sdram_clk_pll|altpll_component|auto_generated|pll1, spectrum, 1 +instance = comp, \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl , sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl, spectrum, 1 +instance = comp, \sdram_|Mux38~0 , sdram_|Mux38~0, spectrum, 1 +instance = comp, \sdram_|r.rd_pending , sdram_|r.rd_pending, spectrum, 1 +instance = comp, \sdram_|r.rf_counter[0]~12 , sdram_|r.rf_counter[0]~12, spectrum, 1 +instance = comp, \sdram_|r.rf_counter[3]~32 , sdram_|r.rf_counter[3]~32, spectrum, 1 +instance = comp, \sdram_|r.rf_counter[0] , sdram_|r.rf_counter[0], spectrum, 1 +instance = comp, \sdram_|r.rf_counter[1]~14 , sdram_|r.rf_counter[1]~14, spectrum, 1 +instance = comp, \sdram_|r.rf_counter[1] , sdram_|r.rf_counter[1], spectrum, 1 +instance = comp, \sdram_|r.rf_counter[2]~16 , sdram_|r.rf_counter[2]~16, spectrum, 1 +instance = comp, \sdram_|r.rf_counter[2] , sdram_|r.rf_counter[2], spectrum, 1 +instance = comp, \sdram_|r.rf_counter[3]~18 , sdram_|r.rf_counter[3]~18, spectrum, 1 +instance = comp, \sdram_|r.rf_counter[3] , sdram_|r.rf_counter[3], spectrum, 1 +instance = comp, \sdram_|r.rf_counter[4]~20 , sdram_|r.rf_counter[4]~20, spectrum, 1 +instance = comp, \sdram_|r.rf_counter[4] , sdram_|r.rf_counter[4], spectrum, 1 +instance = comp, \sdram_|r.rf_counter[5]~22 , sdram_|r.rf_counter[5]~22, spectrum, 1 +instance = comp, \sdram_|r.rf_counter[5] , sdram_|r.rf_counter[5], spectrum, 1 +instance = comp, \sdram_|r.rf_counter[6]~24 , sdram_|r.rf_counter[6]~24, spectrum, 1 +instance = comp, \sdram_|r.rf_counter[6] , sdram_|r.rf_counter[6], spectrum, 1 +instance = comp, \sdram_|r.rf_counter[7]~26 , sdram_|r.rf_counter[7]~26, spectrum, 1 +instance = comp, \sdram_|r.rf_counter[7] , sdram_|r.rf_counter[7], spectrum, 1 +instance = comp, \sdram_|Equal0~1 , sdram_|Equal0~1, spectrum, 1 +instance = comp, \sdram_|r.rf_counter[8]~28 , sdram_|r.rf_counter[8]~28, spectrum, 1 +instance = comp, \sdram_|r.rf_counter[8] , sdram_|r.rf_counter[8], spectrum, 1 +instance = comp, \sdram_|Equal0~0 , sdram_|Equal0~0, spectrum, 1 +instance = comp, \sdram_|r.rf_counter[9]~30 , sdram_|r.rf_counter[9]~30, spectrum, 1 +instance = comp, \sdram_|r.rf_counter[9] , sdram_|r.rf_counter[9], spectrum, 1 +instance = comp, \sdram_|Equal0~2 , sdram_|Equal0~2, spectrum, 1 +instance = comp, \sdram_|Mux13~8 , sdram_|Mux13~8, spectrum, 1 +instance = comp, \sdram_|Mux37~0 , sdram_|Mux37~0, spectrum, 1 +instance = comp, \sdram_|r.rf_pending , sdram_|r.rf_pending, spectrum, 1 +instance = comp, \sdram_|Mux4~0 , sdram_|Mux4~0, spectrum, 1 +instance = comp, \sdram_|Mux4~1 , sdram_|Mux4~1, spectrum, 1 +instance = comp, \sdram_|Mux4~2 , sdram_|Mux4~2, spectrum, 1 +instance = comp, \sdram_|Mux4~3 , sdram_|Mux4~3, spectrum, 1 +instance = comp, \sdram_|r.state[8] , sdram_|r.state[8], spectrum, 1 +instance = comp, \sdram_|r.act_row[1]~0 , sdram_|r.act_row[1]~0, spectrum, 1 +instance = comp, \sdram_|process_0~2 , sdram_|process_0~2, spectrum, 1 +instance = comp, \sdram_|r.act_row[1]~1 , sdram_|r.act_row[1]~1, spectrum, 1 +instance = comp, \sdram_|r.act_row[4] , sdram_|r.act_row[4], spectrum, 1 +instance = comp, \sdram_|r.act_row[3] , sdram_|r.act_row[3], spectrum, 1 +instance = comp, \sdram_|r.act_row[2]~feeder , sdram_|r.act_row[2]~feeder, spectrum, 1 +instance = comp, \sdram_|r.act_row[2] , sdram_|r.act_row[2], spectrum, 1 +instance = comp, \sdram_|Equal7~1 , sdram_|Equal7~1, spectrum, 1 +instance = comp, \sdram_|r.act_row[1] , sdram_|r.act_row[1], spectrum, 1 +instance = comp, \sdram_|r.act_row[0] , sdram_|r.act_row[0], spectrum, 1 +instance = comp, \sdram_|Equal7~0 , sdram_|Equal7~0, spectrum, 1 +instance = comp, \sdram_|Equal7~2 , sdram_|Equal7~2, spectrum, 1 +instance = comp, \sdram_|Mux39~0 , sdram_|Mux39~0, spectrum, 1 +instance = comp, \sdram_|Mux39~1 , sdram_|Mux39~1, spectrum, 1 +instance = comp, \sdram_|Mux39~2 , sdram_|Mux39~2, spectrum, 1 +instance = comp, \sdram_|r.wr_pending , sdram_|r.wr_pending, spectrum, 1 +instance = comp, \sdram_|Mux9~8 , sdram_|Mux9~8, spectrum, 1 +instance = comp, \sdram_|Mux9~9 , sdram_|Mux9~9, spectrum, 1 +instance = comp, \sdram_|Mux6~3 , sdram_|Mux6~3, spectrum, 1 +instance = comp, \sdram_|Mux6~4 , sdram_|Mux6~4, spectrum, 1 +instance = comp, \sdram_|Mux6~2 , sdram_|Mux6~2, spectrum, 1 +instance = comp, \sdram_|Mux6~5 , sdram_|Mux6~5, spectrum, 1 +instance = comp, \sdram_|process_0~3 , sdram_|process_0~3, spectrum, 1 +instance = comp, \sdram_|Mux6~0 , sdram_|Mux6~0, spectrum, 1 +instance = comp, \sdram_|Mux6~1 , sdram_|Mux6~1, spectrum, 1 +instance = comp, \sdram_|Mux6~6 , sdram_|Mux6~6, spectrum, 1 +instance = comp, \sdram_|r.state[6] , sdram_|r.state[6], spectrum, 1 +instance = comp, \sdram_|r.address[3]~6 , sdram_|r.address[3]~6, spectrum, 1 +instance = comp, \sdram_|Mux7~2 , sdram_|Mux7~2, spectrum, 1 +instance = comp, \sdram_|n~3 , sdram_|n~3, spectrum, 1 +instance = comp, \sdram_|Mux7~3 , sdram_|Mux7~3, spectrum, 1 +instance = comp, \sdram_|Mux7~4 , sdram_|Mux7~4, spectrum, 1 +instance = comp, \sdram_|Mux7~5 , sdram_|Mux7~5, spectrum, 1 +instance = comp, \sdram_|Mux23~0 , sdram_|Mux23~0, spectrum, 1 +instance = comp, \sdram_|Mux13~7 , sdram_|Mux13~7, spectrum, 1 +instance = comp, \sdram_|Mux10~10 , sdram_|Mux10~10, spectrum, 1 +instance = comp, \sdram_|Mux7~1 , sdram_|Mux7~1, spectrum, 1 +instance = comp, \sdram_|Mux7~6 , sdram_|Mux7~6, spectrum, 1 +instance = comp, \sdram_|r.state[5] , sdram_|r.state[5], spectrum, 1 +instance = comp, \sdram_|Mux5~2 , sdram_|Mux5~2, spectrum, 1 +instance = comp, \sdram_|Mux5~10 , sdram_|Mux5~10, spectrum, 1 +instance = comp, \sdram_|Mux5~3 , sdram_|Mux5~3, spectrum, 1 +instance = comp, \sdram_|Mux5~4 , sdram_|Mux5~4, spectrum, 1 +instance = comp, \sdram_|Mux5~7 , sdram_|Mux5~7, spectrum, 1 +instance = comp, \sdram_|Mux5~8 , sdram_|Mux5~8, spectrum, 1 +instance = comp, \sdram_|Mux5~5 , sdram_|Mux5~5, spectrum, 1 +instance = comp, \sdram_|Mux5~6 , sdram_|Mux5~6, spectrum, 1 +instance = comp, \sdram_|Mux5~9 , sdram_|Mux5~9, spectrum, 1 +instance = comp, \sdram_|r.state[7] , sdram_|r.state[7], spectrum, 1 +instance = comp, \sdram_|n~2 , sdram_|n~2, spectrum, 1 +instance = comp, \sdram_|Mux8~3 , sdram_|Mux8~3, spectrum, 1 +instance = comp, \sdram_|Mux8~4 , sdram_|Mux8~4, spectrum, 1 +instance = comp, \sdram_|Mux9~10 , sdram_|Mux9~10, spectrum, 1 +instance = comp, \sdram_|r.init_counter[0]~0 , sdram_|r.init_counter[0]~0, spectrum, 1 +instance = comp, \sdram_|r.init_counter[0] , sdram_|r.init_counter[0], spectrum, 1 +instance = comp, \sdram_|Add1~1 , sdram_|Add1~1, spectrum, 1 +instance = comp, \sdram_|Add1~2 , sdram_|Add1~2, spectrum, 1 +instance = comp, \sdram_|r.init_counter[1] , sdram_|r.init_counter[1], spectrum, 1 +instance = comp, \sdram_|Add1~4 , sdram_|Add1~4, spectrum, 1 +instance = comp, \sdram_|r.init_counter[2] , sdram_|r.init_counter[2], spectrum, 1 +instance = comp, \sdram_|Add1~6 , sdram_|Add1~6, spectrum, 1 +instance = comp, \sdram_|r.init_counter[3]~1 , sdram_|r.init_counter[3]~1, spectrum, 1 +instance = comp, \sdram_|r.init_counter[3] , sdram_|r.init_counter[3], spectrum, 1 +instance = comp, \sdram_|Add1~8 , sdram_|Add1~8, spectrum, 1 +instance = comp, \sdram_|r.init_counter[4] , sdram_|r.init_counter[4], spectrum, 1 +instance = comp, \sdram_|Add1~10 , sdram_|Add1~10, spectrum, 1 +instance = comp, \sdram_|r.init_counter[5] , sdram_|r.init_counter[5], spectrum, 1 +instance = comp, \sdram_|Add1~12 , sdram_|Add1~12, spectrum, 1 +instance = comp, \sdram_|r.init_counter[6] , sdram_|r.init_counter[6], spectrum, 1 +instance = comp, \sdram_|Add1~14 , sdram_|Add1~14, spectrum, 1 +instance = comp, \sdram_|r.init_counter[7] , sdram_|r.init_counter[7], spectrum, 1 +instance = comp, \sdram_|Add1~16 , sdram_|Add1~16, spectrum, 1 +instance = comp, \sdram_|r.init_counter[8] , sdram_|r.init_counter[8], spectrum, 1 +instance = comp, \sdram_|Add1~18 , sdram_|Add1~18, spectrum, 1 +instance = comp, \sdram_|r.init_counter[9] , sdram_|r.init_counter[9], spectrum, 1 +instance = comp, \sdram_|Add1~20 , sdram_|Add1~20, spectrum, 1 +instance = comp, \sdram_|r.init_counter[10] , sdram_|r.init_counter[10], spectrum, 1 +instance = comp, \sdram_|Equal2~0 , sdram_|Equal2~0, spectrum, 1 +instance = comp, \sdram_|Equal2~1 , sdram_|Equal2~1, spectrum, 1 +instance = comp, \sdram_|Add1~22 , sdram_|Add1~22, spectrum, 1 +instance = comp, \sdram_|r.init_counter[11] , sdram_|r.init_counter[11], spectrum, 1 +instance = comp, \sdram_|Add1~24 , sdram_|Add1~24, spectrum, 1 +instance = comp, \sdram_|r.init_counter[12] , sdram_|r.init_counter[12], spectrum, 1 +instance = comp, \sdram_|Add1~26 , sdram_|Add1~26, spectrum, 1 +instance = comp, \sdram_|r.init_counter[13] , sdram_|r.init_counter[13], spectrum, 1 +instance = comp, \sdram_|Add1~28 , sdram_|Add1~28, spectrum, 1 +instance = comp, \sdram_|r.init_counter[14] , sdram_|r.init_counter[14], spectrum, 1 +instance = comp, \sdram_|process_0~5 , sdram_|process_0~5, spectrum, 1 +instance = comp, \sdram_|Equal2~2 , sdram_|Equal2~2, spectrum, 1 +instance = comp, \sdram_|Mux9~11 , sdram_|Mux9~11, spectrum, 1 +instance = comp, \sdram_|Mux9~12 , sdram_|Mux9~12, spectrum, 1 +instance = comp, \sdram_|Mux9~13 , sdram_|Mux9~13, spectrum, 1 +instance = comp, \sdram_|Mux8~0 , sdram_|Mux8~0, spectrum, 1 +instance = comp, \sdram_|Mux8~1 , sdram_|Mux8~1, spectrum, 1 +instance = comp, \sdram_|Mux8~2 , sdram_|Mux8~2, spectrum, 1 +instance = comp, \sdram_|r.state[4] , sdram_|r.state[4], spectrum, 1 +instance = comp, \sdram_|Mux72~0 , sdram_|Mux72~0, spectrum, 1 +instance = comp, \sdram_|Mux72~1 , sdram_|Mux72~1, spectrum, 1 +instance = comp, \sdram_|Mux84~0 , sdram_|Mux84~0, spectrum, 1 +instance = comp, \sdram_|Mux84~1 , sdram_|Mux84~1, spectrum, 1 +instance = comp, \sdram_|Mux3~0 , sdram_|Mux3~0, spectrum, 1 +instance = comp, \sdram_|Mux3~1 , sdram_|Mux3~1, spectrum, 1 +instance = comp, \sdram_|Mux2~0 , sdram_|Mux2~0, spectrum, 1 +instance = comp, \sdram_|Mux2~1 , sdram_|Mux2~1, spectrum, 1 +instance = comp, \sdram_|Mux1~0 , sdram_|Mux1~0, spectrum, 1 +instance = comp, \sdram_|Mux1~1 , sdram_|Mux1~1, spectrum, 1 +instance = comp, \sdram_|Mux0~0 , sdram_|Mux0~0, spectrum, 1 +instance = comp, \sdram_|Mux0~1 , sdram_|Mux0~1, spectrum, 1 +instance = comp, \sdram_|Mux73~0 , sdram_|Mux73~0, spectrum, 1 +instance = comp, \sdram_|Mux73~1 , sdram_|Mux73~1, spectrum, 1 +instance = comp, \sdram_|Mux74~0 , sdram_|Mux74~0, spectrum, 1 +instance = comp, \sdram_|Mux74~1 , sdram_|Mux74~1, spectrum, 1 +instance = comp, \sdram_|Mux75~0 , sdram_|Mux75~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|mclk_r~0 , ula_|i2s_intf_|mclk_r~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|mclk_r~_Duplicate_1 , ula_|i2s_intf_|mclk_r~_Duplicate_1, spectrum, 1 instance = comp, \ula_|i2s_intf_|mclk_r , ula_|i2s_intf_|mclk_r, spectrum, 1 @@ -2992,12 +3168,14 @@ instance = comp, \ula_|i2s_intf_|lrdivider[9]~3 , ula_|i2s_intf_|lrdivider[9]~3, instance = comp, \ula_|i2s_intf_|lrdivider[9] , ula_|i2s_intf_|lrdivider[9], spectrum, 1 instance = comp, \ula_|i2s_intf_|Equal0~0 , ula_|i2s_intf_|Equal0~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|Equal0~2 , ula_|i2s_intf_|Equal0~2, spectrum, 1 -instance = comp, \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder , ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder, spectrum, 1 instance = comp, \ula_|i2s_intf_|lrclk_r~_Duplicate_2 , ula_|i2s_intf_|lrclk_r~_Duplicate_2, spectrum, 1 instance = comp, \ula_|i2s_intf_|lrclk_r~0 , ula_|i2s_intf_|lrclk_r~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|lrclk_r , ula_|i2s_intf_|lrclk_r, spectrum, 1 instance = comp, \ula_|i2s_intf_|lrclk_r~_Duplicate_1 , ula_|i2s_intf_|lrclk_r~_Duplicate_1, spectrum, 1 +instance = comp, \ula_|i2s_intf_|Add2~18 , ula_|i2s_intf_|Add2~18, spectrum, 1 +instance = comp, \ula_|i2s_intf_|bdivider[0] , ula_|i2s_intf_|bdivider[0], spectrum, 1 instance = comp, \ula_|i2s_intf_|bitcount[0]~5 , ula_|i2s_intf_|bitcount[0]~5, spectrum, 1 +instance = comp, \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder , ula_|i2s_intf_|bclk_r~_Duplicate_1feeder, spectrum, 1 instance = comp, \ula_|i2s_intf_|bclk_r~_Duplicate_1 , ula_|i2s_intf_|bclk_r~_Duplicate_1, spectrum, 1 instance = comp, \ula_|i2s_intf_|bitcount[4]~15 , ula_|i2s_intf_|bitcount[4]~15, spectrum, 1 instance = comp, \ula_|i2s_intf_|bitcount[0] , ula_|i2s_intf_|bitcount[0], spectrum, 1 @@ -3007,9 +3185,10 @@ instance = comp, \ula_|i2s_intf_|bitcount[2]~9 , ula_|i2s_intf_|bitcount[2]~9, s instance = comp, \ula_|i2s_intf_|bitcount[2] , ula_|i2s_intf_|bitcount[2], spectrum, 1 instance = comp, \ula_|i2s_intf_|bitcount[3]~11 , ula_|i2s_intf_|bitcount[3]~11, spectrum, 1 instance = comp, \ula_|i2s_intf_|bitcount[3] , ula_|i2s_intf_|bitcount[3], spectrum, 1 -instance = comp, \ula_|i2s_intf_|LessThan0~0 , ula_|i2s_intf_|LessThan0~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|bitcount[4]~13 , ula_|i2s_intf_|bitcount[4]~13, spectrum, 1 instance = comp, \ula_|i2s_intf_|bitcount[4] , ula_|i2s_intf_|bitcount[4], spectrum, 1 +instance = comp, \ula_|i2s_intf_|LessThan0~0 , ula_|i2s_intf_|LessThan0~0, spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[1]~1 , ula_|i2s_intf_|shiftreg[1]~1, spectrum, 1 instance = comp, \ula_|i2s_intf_|Add2~7 , ula_|i2s_intf_|Add2~7, spectrum, 1 instance = comp, \ula_|i2s_intf_|Add2~8 , ula_|i2s_intf_|Add2~8, spectrum, 1 instance = comp, \ula_|i2s_intf_|Add2~20 , ula_|i2s_intf_|Add2~20, spectrum, 1 @@ -3024,9 +3203,6 @@ instance = comp, \ula_|i2s_intf_|Add2~14 , ula_|i2s_intf_|Add2~14, spectrum, 1 instance = comp, \ula_|i2s_intf_|Add2~16 , ula_|i2s_intf_|Add2~16, spectrum, 1 instance = comp, \ula_|i2s_intf_|bdivider[4] , ula_|i2s_intf_|bdivider[4], spectrum, 1 instance = comp, \ula_|i2s_intf_|Equal1~0 , ula_|i2s_intf_|Equal1~0, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[4]~1 , ula_|i2s_intf_|shiftreg[4]~1, spectrum, 1 -instance = comp, \ula_|i2s_intf_|Add2~18 , ula_|i2s_intf_|Add2~18, spectrum, 1 -instance = comp, \ula_|i2s_intf_|bdivider[0] , ula_|i2s_intf_|bdivider[0], spectrum, 1 instance = comp, \ula_|i2s_intf_|Equal1~1 , ula_|i2s_intf_|Equal1~1, spectrum, 1 instance = comp, \ula_|i2s_intf_|bclk_r~0 , ula_|i2s_intf_|bclk_r~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|bclk_r~1 , ula_|i2s_intf_|bclk_r~1, spectrum, 1 @@ -3040,7 +3216,7 @@ instance = comp, \AUD_ADCDAT~input , AUD_ADCDAT~input, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[0]~20 , ula_|i2s_intf_|shiftreg[0]~20, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[0] , ula_|i2s_intf_|shiftreg[0], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg~18 , ula_|i2s_intf_|shiftreg~18, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[4]~2 , ula_|i2s_intf_|shiftreg[4]~2, spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[1]~2 , ula_|i2s_intf_|shiftreg[1]~2, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[1] , ula_|i2s_intf_|shiftreg[1], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg~17 , ula_|i2s_intf_|shiftreg~17, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[2] , ula_|i2s_intf_|shiftreg[2], spectrum, 1 @@ -3074,6 +3250,7 @@ instance = comp, \ula_|i2s_intf_|shiftreg~6 , ula_|i2s_intf_|shiftreg~6, spectru instance = comp, \ula_|i2s_intf_|shiftreg[13] , ula_|i2s_intf_|shiftreg[13], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg~5 , ula_|i2s_intf_|shiftreg~5, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[14] , ula_|i2s_intf_|shiftreg[14], spectrum, 1 +instance = comp, \ula_|pcm_outl[14]~feeder , ula_|pcm_outl[14]~feeder, spectrum, 1 instance = comp, \ula_|pcm_outl[14] , ula_|pcm_outl[14], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg~4 , ula_|i2s_intf_|shiftreg~4, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[15] , ula_|i2s_intf_|shiftreg[15], spectrum, 1 @@ -3081,28 +3258,17 @@ instance = comp, \ula_|i2s_intf_|shiftreg~3 , ula_|i2s_intf_|shiftreg~3, spectru instance = comp, \ula_|i2s_intf_|shiftreg[16] , ula_|i2s_intf_|shiftreg[16], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg~0 , ula_|i2s_intf_|shiftreg~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[17] , ula_|i2s_intf_|shiftreg[17], spectrum, 1 -instance = comp, \ula_|video_|LessThan2~0 , ula_|video_|LessThan2~0, spectrum, 1 -instance = comp, \ula_|video_|LessThan6~0 , ula_|video_|LessThan6~0, spectrum, 1 -instance = comp, \ula_|video_|LessThan2~1 , ula_|video_|LessThan2~1, spectrum, 1 -instance = comp, \ula_|video_|LessThan3~0 , ula_|video_|LessThan3~0, spectrum, 1 -instance = comp, \ula_|video_|LessThan0~0 , ula_|video_|LessThan0~0, spectrum, 1 -instance = comp, \ula_|video_|disp_enable~0 , ula_|video_|disp_enable~0, spectrum, 1 -instance = comp, \ula_|video_|disp_enable~1 , ula_|video_|disp_enable~1, spectrum, 1 +instance = comp, \ula_|border[1]~feeder , ula_|border[1]~feeder, spectrum, 1 instance = comp, \ula_|border[1] , ula_|border[1], spectrum, 1 +instance = comp, \ula_|video_|LessThan6~0 , ula_|video_|LessThan6~0, spectrum, 1 instance = comp, \ula_|video_|LessThan6~1 , ula_|video_|LessThan6~1, spectrum, 1 instance = comp, \ula_|video_|LessThan4~0 , ula_|video_|LessThan4~0, spectrum, 1 instance = comp, \ula_|video_|screen_en~0 , ula_|video_|screen_en~0, spectrum, 1 instance = comp, \ula_|video_|screen_en~1 , ula_|video_|screen_en~1, spectrum, 1 -instance = comp, \ula_|video_|attr_prefetch[1]~feeder , ula_|video_|attr_prefetch[1]~feeder, spectrum, 1 -instance = comp, \ula_|video_|Decoder0~1 , ula_|video_|Decoder0~1, spectrum, 1 -instance = comp, \ula_|video_|attr_prefetch[1] , ula_|video_|attr_prefetch[1], spectrum, 1 -instance = comp, \ula_|video_|Decoder0~0 , ula_|video_|Decoder0~0, spectrum, 1 -instance = comp, \ula_|video_|attr[1] , ula_|video_|attr[1], spectrum, 1 -instance = comp, \ula_|video_|attr_prefetch[4]~feeder , ula_|video_|attr_prefetch[4]~feeder, spectrum, 1 -instance = comp, \ula_|video_|attr_prefetch[4] , ula_|video_|attr_prefetch[4], spectrum, 1 -instance = comp, \ula_|video_|attr[4] , ula_|video_|attr[4], spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[7]~feeder , ula_|video_|attr_prefetch[7]~feeder, spectrum, 1 +instance = comp, \ula_|video_|Decoder0~1 , ula_|video_|Decoder0~1, spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[7] , ula_|video_|attr_prefetch[7], spectrum, 1 +instance = comp, \ula_|video_|Decoder0~0 , ula_|video_|Decoder0~0, spectrum, 1 instance = comp, \ula_|video_|attr[7] , ula_|video_|attr[7], spectrum, 1 instance = comp, \ula_|video_|frame[0]~12 , ula_|video_|frame[0]~12, spectrum, 1 instance = comp, \ula_|video_|frame[0] , ula_|video_|frame[0], spectrum, 1 @@ -3118,7 +3284,6 @@ instance = comp, \ula_|video_|inverted , ula_|video_|inverted, spectrum, 1 instance = comp, \ula_|video_|bits_prefetch[6]~feeder , ula_|video_|bits_prefetch[6]~feeder, spectrum, 1 instance = comp, \ula_|video_|Decoder0~2 , ula_|video_|Decoder0~2, spectrum, 1 instance = comp, \ula_|video_|bits_prefetch[6] , ula_|video_|bits_prefetch[6], spectrum, 1 -instance = comp, \ula_|video_|bits[6]~feeder , ula_|video_|bits[6]~feeder, spectrum, 1 instance = comp, \ula_|video_|bits[6] , ula_|video_|bits[6], spectrum, 1 instance = comp, \ula_|video_|bits_prefetch[4]~feeder , ula_|video_|bits_prefetch[4]~feeder, spectrum, 1 instance = comp, \ula_|video_|bits_prefetch[4] , ula_|video_|bits_prefetch[4], spectrum, 1 @@ -3148,28 +3313,41 @@ instance = comp, \ula_|video_|bits_prefetch[3] , ula_|video_|bits_prefetch[3], s instance = comp, \ula_|video_|bits[3] , ula_|video_|bits[3], spectrum, 1 instance = comp, \ula_|video_|Mux0~2 , ula_|video_|Mux0~2, spectrum, 1 instance = comp, \ula_|video_|Mux0~3 , ula_|video_|Mux0~3, spectrum, 1 -instance = comp, \ula_|video_|cindex[1]~0 , ula_|video_|cindex[1]~0, spectrum, 1 +instance = comp, \ula_|video_|cindex[2]~0 , ula_|video_|cindex[2]~0, spectrum, 1 +instance = comp, \ula_|video_|attr_prefetch[4]~feeder , ula_|video_|attr_prefetch[4]~feeder, spectrum, 1 +instance = comp, \ula_|video_|attr_prefetch[4] , ula_|video_|attr_prefetch[4], spectrum, 1 +instance = comp, \ula_|video_|attr[4] , ula_|video_|attr[4], spectrum, 1 +instance = comp, \ula_|video_|attr_prefetch[1]~feeder , ula_|video_|attr_prefetch[1]~feeder, spectrum, 1 +instance = comp, \ula_|video_|attr_prefetch[1] , ula_|video_|attr_prefetch[1], spectrum, 1 +instance = comp, \ula_|video_|attr[1] , ula_|video_|attr[1], spectrum, 1 instance = comp, \ula_|video_|cindex[1]~1 , ula_|video_|cindex[1]~1, spectrum, 1 +instance = comp, \ula_|video_|LessThan2~0 , ula_|video_|LessThan2~0, spectrum, 1 +instance = comp, \ula_|video_|LessThan2~1 , ula_|video_|LessThan2~1, spectrum, 1 +instance = comp, \ula_|video_|LessThan3~0 , ula_|video_|LessThan3~0, spectrum, 1 +instance = comp, \ula_|video_|LessThan0~0 , ula_|video_|LessThan0~0, spectrum, 1 +instance = comp, \ula_|video_|disp_enable~0 , ula_|video_|disp_enable~0, spectrum, 1 +instance = comp, \ula_|video_|disp_enable~1 , ula_|video_|disp_enable~1, spectrum, 1 instance = comp, \ula_|video_|VGA_R[0]~0 , ula_|video_|VGA_R[0]~0, spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[6]~feeder , ula_|video_|attr_prefetch[6]~feeder, spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[6] , ula_|video_|attr_prefetch[6], spectrum, 1 instance = comp, \ula_|video_|attr[6] , ula_|video_|attr[6], spectrum, 1 instance = comp, \ula_|video_|VGA_B[1]~0 , ula_|video_|VGA_B[1]~0, spectrum, 1 instance = comp, \ula_|video_|VGA_R[1]~1 , ula_|video_|VGA_R[1]~1, spectrum, 1 +instance = comp, \ula_|border[2]~feeder , ula_|border[2]~feeder, spectrum, 1 instance = comp, \ula_|border[2] , ula_|border[2], spectrum, 1 -instance = comp, \ula_|video_|attr_prefetch[2]~feeder , ula_|video_|attr_prefetch[2]~feeder, spectrum, 1 -instance = comp, \ula_|video_|attr_prefetch[2] , ula_|video_|attr_prefetch[2], spectrum, 1 -instance = comp, \ula_|video_|attr[2] , ula_|video_|attr[2], spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[5]~feeder , ula_|video_|attr_prefetch[5]~feeder, spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[5] , ula_|video_|attr_prefetch[5], spectrum, 1 instance = comp, \ula_|video_|attr[5] , ula_|video_|attr[5], spectrum, 1 +instance = comp, \ula_|video_|attr_prefetch[2]~feeder , ula_|video_|attr_prefetch[2]~feeder, spectrum, 1 +instance = comp, \ula_|video_|attr_prefetch[2] , ula_|video_|attr_prefetch[2], spectrum, 1 +instance = comp, \ula_|video_|attr[2] , ula_|video_|attr[2], spectrum, 1 instance = comp, \ula_|video_|cindex[2]~2 , ula_|video_|cindex[2]~2, spectrum, 1 instance = comp, \ula_|video_|VGA_G[0]~0 , ula_|video_|VGA_G[0]~0, spectrum, 1 instance = comp, \ula_|video_|VGA_G[1]~1 , ula_|video_|VGA_G[1]~1, spectrum, 1 +instance = comp, \ula_|border[0]~feeder , ula_|border[0]~feeder, spectrum, 1 instance = comp, \ula_|border[0] , ula_|border[0], spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[0]~feeder , ula_|video_|attr_prefetch[0]~feeder, spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[0] , ula_|video_|attr_prefetch[0], spectrum, 1 -instance = comp, \ula_|video_|attr[0]~feeder , ula_|video_|attr[0]~feeder, spectrum, 1 instance = comp, \ula_|video_|attr[0] , ula_|video_|attr[0], spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[3]~feeder , ula_|video_|attr_prefetch[3]~feeder, spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[3] , ula_|video_|attr_prefetch[3], spectrum, 1 @@ -3191,6 +3369,167 @@ instance = comp, \z80_|memory_ifc_|nRFSH_out~0 , z80_|memory_ifc_|nRFSH_out~0, s instance = comp, \z80_|memory_ifc_|nM1_out , z80_|memory_ifc_|nM1_out, spectrum, 1 instance = comp, \ula_|beep~0 , ula_|beep~0, spectrum, 1 instance = comp, \ula_|beep , ula_|beep, spectrum, 1 +instance = comp, \sdram_|Mux26~4 , sdram_|Mux26~4, spectrum, 1 +instance = comp, \sdram_|r.bank[0]~7 , sdram_|r.bank[0]~7, spectrum, 1 +instance = comp, \sdram_|r.bank[0]~11 , sdram_|r.bank[0]~11, spectrum, 1 +instance = comp, \sdram_|r.bank[0]~4 , sdram_|r.bank[0]~4, spectrum, 1 +instance = comp, \sdram_|r.bank[0]~5 , sdram_|r.bank[0]~5, spectrum, 1 +instance = comp, \sdram_|r.bank[0]~6 , sdram_|r.bank[0]~6, spectrum, 1 +instance = comp, \sdram_|r.bank[0]~8 , sdram_|r.bank[0]~8, spectrum, 1 +instance = comp, \sdram_|r.bank[0]~12 , sdram_|r.bank[0]~12, spectrum, 1 +instance = comp, \sdram_|r.bank[0]~9 , sdram_|r.bank[0]~9, spectrum, 1 +instance = comp, \sdram_|r.bank[0] , sdram_|r.bank[0], spectrum, 1 +instance = comp, \sdram_|Mux25~4 , sdram_|Mux25~4, spectrum, 1 +instance = comp, \sdram_|r.bank[1] , sdram_|r.bank[1], spectrum, 1 +instance = comp, \sdram_|Mux24~5 , sdram_|Mux24~5, spectrum, 1 +instance = comp, \sdram_|Mux71~0 , sdram_|Mux71~0, spectrum, 1 +instance = comp, \sdram_|process_0~7 , sdram_|process_0~7, spectrum, 1 +instance = comp, \sdram_|process_0~4 , sdram_|process_0~4, spectrum, 1 +instance = comp, \sdram_|Mux71~1 , sdram_|Mux71~1, spectrum, 1 +instance = comp, \sdram_|Mux71~2 , sdram_|Mux71~2, spectrum, 1 +instance = comp, \sdram_|Mux71~3 , sdram_|Mux71~3, spectrum, 1 +instance = comp, \sdram_|Mux71~4 , sdram_|Mux71~4, spectrum, 1 +instance = comp, \sdram_|r.dq_masks[0] , sdram_|r.dq_masks[0], spectrum, 1 +instance = comp, \sdram_|r.dq_masks[1] , sdram_|r.dq_masks[1], spectrum, 1 +instance = comp, \sdram_|r.bank[0]~10 , sdram_|r.bank[0]~10, spectrum, 1 +instance = comp, \sdram_|Mux9~3 , sdram_|Mux9~3, spectrum, 1 +instance = comp, \sdram_|n~5 , sdram_|n~5, spectrum, 1 +instance = comp, \sdram_|Mux9~4 , sdram_|Mux9~4, spectrum, 1 +instance = comp, \sdram_|Mux9~2 , sdram_|Mux9~2, spectrum, 1 +instance = comp, \sdram_|Equal2~3 , sdram_|Equal2~3, spectrum, 1 +instance = comp, \sdram_|Mux10~2 , sdram_|Mux10~2, spectrum, 1 +instance = comp, \sdram_|Mux10~3 , sdram_|Mux10~3, spectrum, 1 +instance = comp, \sdram_|process_0~6 , sdram_|process_0~6, spectrum, 1 +instance = comp, \sdram_|Mux10~4 , sdram_|Mux10~4, spectrum, 1 +instance = comp, \sdram_|Mux9~5 , sdram_|Mux9~5, spectrum, 1 +instance = comp, \sdram_|Mux7~0 , sdram_|Mux7~0, spectrum, 1 +instance = comp, \sdram_|Mux9~6 , sdram_|Mux9~6, spectrum, 1 +instance = comp, \sdram_|Mux9~7 , sdram_|Mux9~7, spectrum, 1 +instance = comp, \sdram_|r.state[2] , sdram_|r.state[2], spectrum, 1 +instance = comp, \sdram_|Mux10~11 , sdram_|Mux10~11, spectrum, 1 +instance = comp, \sdram_|Mux10~6 , sdram_|Mux10~6, spectrum, 1 +instance = comp, \sdram_|Mux10~5 , sdram_|Mux10~5, spectrum, 1 +instance = comp, \sdram_|Mux10~7 , sdram_|Mux10~7, spectrum, 1 +instance = comp, \sdram_|Mux10~8 , sdram_|Mux10~8, spectrum, 1 +instance = comp, \sdram_|Mux10~9 , sdram_|Mux10~9, spectrum, 1 +instance = comp, \sdram_|r.state[1] , sdram_|r.state[1], spectrum, 1 +instance = comp, \sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK , sdram_|sdram_clk_pll|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_e_DRAM_CLK, spectrum, 1 +instance = comp, \sdram_|Mux11~2 , sdram_|Mux11~2, spectrum, 1 +instance = comp, \sdram_|Mux11~3 , sdram_|Mux11~3, spectrum, 1 +instance = comp, \sdram_|Mux11~4 , sdram_|Mux11~4, spectrum, 1 +instance = comp, \sdram_|Mux11~5 , sdram_|Mux11~5, spectrum, 1 +instance = comp, \sdram_|Mux11~6 , sdram_|Mux11~6, spectrum, 1 +instance = comp, \sdram_|Mux11~7 , sdram_|Mux11~7, spectrum, 1 +instance = comp, \sdram_|Mux11~9 , sdram_|Mux11~9, spectrum, 1 +instance = comp, \sdram_|Mux11~8 , sdram_|Mux11~8, spectrum, 1 +instance = comp, \sdram_|r.state[0] , sdram_|r.state[0], spectrum, 1 +instance = comp, \sdram_|Mux24~2 , sdram_|Mux24~2, spectrum, 1 +instance = comp, \sdram_|r.address[0]~7 , sdram_|r.address[0]~7, spectrum, 1 +instance = comp, \sdram_|r.address[0]~0 , sdram_|r.address[0]~0, spectrum, 1 +instance = comp, \sdram_|Mux13~9 , sdram_|Mux13~9, spectrum, 1 +instance = comp, \sdram_|Mux13~4 , sdram_|Mux13~4, spectrum, 1 +instance = comp, \sdram_|Mux13~5 , sdram_|Mux13~5, spectrum, 1 +instance = comp, \sdram_|r.address[0]~_Duplicate_1 , sdram_|r.address[0]~_Duplicate_1, spectrum, 1 +instance = comp, \sdram_|Mux24~3 , sdram_|Mux24~3, spectrum, 1 +instance = comp, \sdram_|Mux24~4 , sdram_|Mux24~4, spectrum, 1 +instance = comp, \sdram_|r.address[0]~SLOAD_MUX , sdram_|r.address[0]~SLOAD_MUX, spectrum, 1 +instance = comp, \sdram_|r.address[0] , sdram_|r.address[0], spectrum, 1 +instance = comp, \sdram_|r.address[1]~_Duplicate_1feeder , sdram_|r.address[1]~_Duplicate_1feeder, spectrum, 1 +instance = comp, \sdram_|Mux23~4 , sdram_|Mux23~4, spectrum, 1 +instance = comp, \sdram_|Equal5~0 , sdram_|Equal5~0, spectrum, 1 +instance = comp, \sdram_|Mux23~5 , sdram_|Mux23~5, spectrum, 1 +instance = comp, \sdram_|Mux23~6 , sdram_|Mux23~6, spectrum, 1 +instance = comp, \sdram_|Mux19~0 , sdram_|Mux19~0, spectrum, 1 +instance = comp, \sdram_|r.address[1]~_Duplicate_1 , sdram_|r.address[1]~_Duplicate_1, spectrum, 1 +instance = comp, \sdram_|Mux23~2 , sdram_|Mux23~2, spectrum, 1 +instance = comp, \sdram_|Mux23~3 , sdram_|Mux23~3, spectrum, 1 +instance = comp, \sdram_|Mux23~1 , sdram_|Mux23~1, spectrum, 1 +instance = comp, \sdram_|r.address[1]~1 , sdram_|r.address[1]~1, spectrum, 1 +instance = comp, \sdram_|r.address[1]~SLOAD_MUX , sdram_|r.address[1]~SLOAD_MUX, spectrum, 1 +instance = comp, \sdram_|r.address[1] , sdram_|r.address[1], spectrum, 1 +instance = comp, \sdram_|r.address[3]~8 , sdram_|r.address[3]~8, spectrum, 1 +instance = comp, \sdram_|r.address[3]~9 , sdram_|r.address[3]~9, spectrum, 1 +instance = comp, \sdram_|Mux21~0 , sdram_|Mux21~0, spectrum, 1 +instance = comp, \sdram_|Mux22~0 , sdram_|Mux22~0, spectrum, 1 +instance = comp, \sdram_|r.address[3]~10 , sdram_|r.address[3]~10, spectrum, 1 +instance = comp, \sdram_|r.address[3]~11 , sdram_|r.address[3]~11, spectrum, 1 +instance = comp, \sdram_|r.address[3]~12 , sdram_|r.address[3]~12, spectrum, 1 +instance = comp, \sdram_|r.address[3]~13 , sdram_|r.address[3]~13, spectrum, 1 +instance = comp, \sdram_|r.address[3]~14 , sdram_|r.address[3]~14, spectrum, 1 +instance = comp, \sdram_|r.address[3]~15 , sdram_|r.address[3]~15, spectrum, 1 +instance = comp, \sdram_|r.address[3]~16 , sdram_|r.address[3]~16, spectrum, 1 +instance = comp, \sdram_|r.address[3]~17 , sdram_|r.address[3]~17, spectrum, 1 +instance = comp, \sdram_|r.address[2] , sdram_|r.address[2], spectrum, 1 +instance = comp, \sdram_|Mux21~1 , sdram_|Mux21~1, spectrum, 1 +instance = comp, \sdram_|r.address[3] , sdram_|r.address[3], spectrum, 1 +instance = comp, \sdram_|Mux20~4 , sdram_|Mux20~4, spectrum, 1 +instance = comp, \sdram_|Mux20~7 , sdram_|Mux20~7, spectrum, 1 +instance = comp, \sdram_|Mux23~7 , sdram_|Mux23~7, spectrum, 1 +instance = comp, \sdram_|Mux20~8 , sdram_|Mux20~8, spectrum, 1 +instance = comp, \sdram_|Mux20~10 , sdram_|Mux20~10, spectrum, 1 +instance = comp, \sdram_|Mux20~9 , sdram_|Mux20~9, spectrum, 1 +instance = comp, \sdram_|Mux20~11 , sdram_|Mux20~11, spectrum, 1 +instance = comp, \sdram_|r.address[4]~_Duplicate_1 , sdram_|r.address[4]~_Duplicate_1, spectrum, 1 +instance = comp, \sdram_|Mux20~12 , sdram_|Mux20~12, spectrum, 1 +instance = comp, \sdram_|Mux20~5 , sdram_|Mux20~5, spectrum, 1 +instance = comp, \sdram_|Mux20~6 , sdram_|Mux20~6, spectrum, 1 +instance = comp, \sdram_|r.address[4]~2 , sdram_|r.address[4]~2, spectrum, 1 +instance = comp, \sdram_|r.address[4]~SLOAD_MUX , sdram_|r.address[4]~SLOAD_MUX, spectrum, 1 +instance = comp, \sdram_|r.address[4] , sdram_|r.address[4], spectrum, 1 +instance = comp, \sdram_|Mux19~1 , sdram_|Mux19~1, spectrum, 1 +instance = comp, \sdram_|Mux19~4 , sdram_|Mux19~4, spectrum, 1 +instance = comp, \sdram_|Mux19~5 , sdram_|Mux19~5, spectrum, 1 +instance = comp, \sdram_|Mux19~6 , sdram_|Mux19~6, spectrum, 1 +instance = comp, \sdram_|Mux19~7 , sdram_|Mux19~7, spectrum, 1 +instance = comp, \sdram_|r.address[5]~_Duplicate_1 , sdram_|r.address[5]~_Duplicate_1, spectrum, 1 +instance = comp, \sdram_|Mux19~2 , sdram_|Mux19~2, spectrum, 1 +instance = comp, \sdram_|Mux19~3 , sdram_|Mux19~3, spectrum, 1 +instance = comp, \sdram_|r.address[5]~3 , sdram_|r.address[5]~3, spectrum, 1 +instance = comp, \sdram_|r.address[5]~SLOAD_MUX , sdram_|r.address[5]~SLOAD_MUX, spectrum, 1 +instance = comp, \sdram_|r.address[5] , sdram_|r.address[5], spectrum, 1 +instance = comp, \sdram_|Mux18~0 , sdram_|Mux18~0, spectrum, 1 +instance = comp, \sdram_|r.address[6] , sdram_|r.address[6], spectrum, 1 +instance = comp, \sdram_|Mux17~0 , sdram_|Mux17~0, spectrum, 1 +instance = comp, \sdram_|r.address[7] , sdram_|r.address[7], spectrum, 1 +instance = comp, \sdram_|Mux16~0 , sdram_|Mux16~0, spectrum, 1 +instance = comp, \sdram_|r.address[8] , sdram_|r.address[8], spectrum, 1 +instance = comp, \sdram_|Mux15~2 , sdram_|Mux15~2, spectrum, 1 +instance = comp, \sdram_|r.address[9] , sdram_|r.address[9], spectrum, 1 +instance = comp, \sdram_|Mux14~0 , sdram_|Mux14~0, spectrum, 1 +instance = comp, \sdram_|Mux14~1 , sdram_|Mux14~1, spectrum, 1 +instance = comp, \sdram_|r.address[10]~4 , sdram_|r.address[10]~4, spectrum, 1 +instance = comp, \sdram_|r.address[10]~_Duplicate_1 , sdram_|r.address[10]~_Duplicate_1, spectrum, 1 +instance = comp, \sdram_|n~4 , sdram_|n~4, spectrum, 1 +instance = comp, \sdram_|Mux14~2 , sdram_|Mux14~2, spectrum, 1 +instance = comp, \sdram_|Mux14~3 , sdram_|Mux14~3, spectrum, 1 +instance = comp, \sdram_|r.address[10]~SLOAD_MUX , sdram_|r.address[10]~SLOAD_MUX, spectrum, 1 +instance = comp, \sdram_|r.address[10] , sdram_|r.address[10], spectrum, 1 +instance = comp, \sdram_|r.address[11]~18 , sdram_|r.address[11]~18, spectrum, 1 +instance = comp, \sdram_|r.address[11]~5 , sdram_|r.address[11]~5, spectrum, 1 +instance = comp, \sdram_|r.address[11]~_Duplicate_2feeder , sdram_|r.address[11]~_Duplicate_2feeder, spectrum, 1 +instance = comp, \sdram_|r.address[11]~_Duplicate_2 , sdram_|r.address[11]~_Duplicate_2, spectrum, 1 +instance = comp, \sdram_|Mux13~10 , sdram_|Mux13~10, spectrum, 1 +instance = comp, \sdram_|Mux13~6 , sdram_|Mux13~6, spectrum, 1 +instance = comp, \sdram_|r.address[11]~SLOAD_MUX , sdram_|r.address[11]~SLOAD_MUX, spectrum, 1 +instance = comp, \sdram_|r.address[11] , sdram_|r.address[11], spectrum, 1 +instance = comp, \sdram_|r.address[11]~_Duplicate_1SLOAD_MUX , sdram_|r.address[11]~_Duplicate_1SLOAD_MUX, spectrum, 1 +instance = comp, \sdram_|r.address[11]~_Duplicate_1 , sdram_|r.address[11]~_Duplicate_1, spectrum, 1 instance = comp, \SW[0]~input , SW[0]~input, spectrum, 1 instance = comp, \SW[3]~input , SW[3]~input, spectrum, 1 instance = comp, \I2C_SCLK~input , I2C_SCLK~input, spectrum, 1 +instance = comp, \DRAM_DQ[0]~input , DRAM_DQ[0]~input, spectrum, 1 +instance = comp, \DRAM_DQ[1]~input , DRAM_DQ[1]~input, spectrum, 1 +instance = comp, \DRAM_DQ[2]~input , DRAM_DQ[2]~input, spectrum, 1 +instance = comp, \DRAM_DQ[3]~input , DRAM_DQ[3]~input, spectrum, 1 +instance = comp, \DRAM_DQ[4]~input , DRAM_DQ[4]~input, spectrum, 1 +instance = comp, \DRAM_DQ[5]~input , DRAM_DQ[5]~input, spectrum, 1 +instance = comp, \DRAM_DQ[6]~input , DRAM_DQ[6]~input, spectrum, 1 +instance = comp, \DRAM_DQ[7]~input , DRAM_DQ[7]~input, spectrum, 1 +instance = comp, \DRAM_DQ[8]~input , DRAM_DQ[8]~input, spectrum, 1 +instance = comp, \DRAM_DQ[9]~input , DRAM_DQ[9]~input, spectrum, 1 +instance = comp, \DRAM_DQ[10]~input , DRAM_DQ[10]~input, spectrum, 1 +instance = comp, \DRAM_DQ[11]~input , DRAM_DQ[11]~input, spectrum, 1 +instance = comp, \DRAM_DQ[12]~input , DRAM_DQ[12]~input, spectrum, 1 +instance = comp, \DRAM_DQ[13]~input , DRAM_DQ[13]~input, spectrum, 1 +instance = comp, \DRAM_DQ[14]~input , DRAM_DQ[14]~input, spectrum, 1 +instance = comp, \DRAM_DQ[15]~input , DRAM_DQ[15]~input, spectrum, 1 diff --git a/simulation/modelsim/spectrum_v.sdo b/simulation/modelsim/spectrum_v.sdo index 8f29861..ce14b52 100644 --- a/simulation/modelsim/spectrum_v.sdo +++ b/simulation/modelsim/spectrum_v.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "04/01/2022 18:55:53") + (DATE "04/02/2022 14:51:22") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,8 +41,8 @@ (INSTANCE GPIO_1\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (2109:2109:2109) (2123:2123:2123)) - (PORT oe (1638:1638:1638) (1708:1708:1708)) + (PORT i (1504:1504:1504) (1598:1598:1598)) + (PORT oe (1712:1712:1712) (1779:1779:1779)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -53,8 +53,8 @@ (INSTANCE GPIO_1\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (2133:2133:2133) (2174:2174:2174)) - (PORT oe (1897:1897:1897) (1931:1931:1931)) + (PORT i (2050:2050:2050) (2110:2110:2110)) + (PORT oe (1688:1688:1688) (1781:1781:1781)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -65,8 +65,8 @@ (INSTANCE GPIO_1\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1984:1984:1984) (2083:2083:2083)) - (PORT oe (1897:1897:1897) (1931:1931:1931)) + (PORT i (2228:2228:2228) (2262:2262:2262)) + (PORT oe (1688:1688:1688) (1781:1781:1781)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -77,8 +77,8 @@ (INSTANCE GPIO_1\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (2218:2218:2218) (2284:2284:2284)) - (PORT oe (2147:2147:2147) (2236:2236:2236)) + (PORT i (1814:1814:1814) (1854:1854:1854)) + (PORT oe (2105:2105:2105) (2195:2195:2195)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -89,8 +89,8 @@ (INSTANCE GPIO_1\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (2271:2271:2271) (2432:2432:2432)) - (PORT oe (2147:2147:2147) (2236:2236:2236)) + (PORT i (1890:1890:1890) (1931:1931:1931)) + (PORT oe (2105:2105:2105) (2195:2195:2195)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -101,8 +101,8 @@ (INSTANCE GPIO_1\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1973:1973:1973) (2011:2011:2011)) - (PORT oe (1910:1910:1910) (2005:2005:2005)) + (PORT i (1532:1532:1532) (1676:1676:1676)) + (PORT oe (2346:2346:2346) (2450:2450:2450)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -113,8 +113,8 @@ (INSTANCE GPIO_1\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1640:1640:1640) (1716:1716:1716)) - (PORT oe (1910:1910:1910) (2005:2005:2005)) + (PORT i (1646:1646:1646) (1694:1694:1694)) + (PORT oe (2346:2346:2346) (2450:2450:2450)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -125,8 +125,8 @@ (INSTANCE GPIO_1\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (1960:1960:1960) (2148:2148:2148)) - (PORT oe (1910:1910:1910) (2005:2005:2005)) + (PORT i (1651:1651:1651) (1747:1747:1747)) + (PORT oe (2346:2346:2346) (2450:2450:2450)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -137,8 +137,8 @@ (INSTANCE GPIO_1\[8\]\~output) (DELAY (ABSOLUTE - (PORT i (976:976:976) (1064:1064:1064)) - (PORT oe (2161:2161:2161) (2266:2266:2266)) + (PORT i (1458:1458:1458) (1517:1517:1517)) + (PORT oe (2627:2627:2627) (2741:2741:2741)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -149,8 +149,8 @@ (INSTANCE GPIO_1\[9\]\~output) (DELAY (ABSOLUTE - (PORT i (1717:1717:1717) (1803:1803:1803)) - (PORT oe (2161:2161:2161) (2266:2266:2266)) + (PORT i (1614:1614:1614) (1659:1659:1659)) + (PORT oe (2627:2627:2627) (2741:2741:2741)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -161,8 +161,8 @@ (INSTANCE GPIO_1\[10\]\~output) (DELAY (ABSOLUTE - (PORT i (1939:1939:1939) (1996:1996:1996)) - (PORT oe (2404:2404:2404) (2537:2537:2537)) + (PORT i (1699:1699:1699) (1833:1833:1833)) + (PORT oe (2364:2364:2364) (2456:2456:2456)) (IOPATH i o (4557:4557:4557) (4190:4190:4190)) (IOPATH oe o (4578:4578:4578) (4159:4159:4159)) ) @@ -173,8 +173,8 @@ (INSTANCE GPIO_1\[11\]\~output) (DELAY (ABSOLUTE - (PORT i (1417:1417:1417) (1462:1462:1462)) - (PORT oe (2161:2161:2161) (2266:2266:2266)) + (PORT i (1560:1560:1560) (1602:1602:1602)) + (PORT oe (2627:2627:2627) (2741:2741:2741)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -185,8 +185,8 @@ (INSTANCE GPIO_1\[12\]\~output) (DELAY (ABSOLUTE - (PORT i (2181:2181:2181) (2209:2209:2209)) - (PORT oe (1700:1700:1700) (1736:1736:1736)) + (PORT i (1639:1639:1639) (1709:1709:1709)) + (PORT oe (1712:1712:1712) (1796:1796:1796)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -197,8 +197,8 @@ (INSTANCE GPIO_1\[13\]\~output) (DELAY (ABSOLUTE - (PORT i (2231:2231:2231) (2361:2361:2361)) - (PORT oe (2404:2404:2404) (2537:2537:2537)) + (PORT i (1649:1649:1649) (1732:1732:1732)) + (PORT oe (2364:2364:2364) (2456:2456:2456)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -209,8 +209,8 @@ (INSTANCE GPIO_1\[14\]\~output) (DELAY (ABSOLUTE - (PORT i (1625:1625:1625) (1715:1715:1715)) - (PORT oe (2140:2140:2140) (2250:2250:2250)) + (PORT i (1435:1435:1435) (1557:1557:1557)) + (PORT oe (2114:2114:2114) (2280:2280:2280)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -221,8 +221,8 @@ (INSTANCE GPIO_1\[15\]\~output) (DELAY (ABSOLUTE - (PORT i (1724:1724:1724) (1854:1854:1854)) - (PORT oe (1916:1916:1916) (1948:1948:1948)) + (PORT i (1807:1807:1807) (1861:1861:1861)) + (PORT oe (1901:1901:1901) (1995:1995:1995)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -233,8 +233,8 @@ (INSTANCE GPIO_1\[16\]\~output) (DELAY (ABSOLUTE - (PORT i (1202:1202:1202) (1265:1265:1265)) - (PORT oe (2441:2441:2441) (2523:2523:2523)) + (PORT i (1165:1165:1165) (1241:1241:1241)) + (PORT oe (1397:1397:1397) (1462:1462:1462)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -245,8 +245,8 @@ (INSTANCE GPIO_1\[17\]\~output) (DELAY (ABSOLUTE - (PORT i (1216:1216:1216) (1287:1287:1287)) - (PORT oe (2442:2442:2442) (2524:2524:2524)) + (PORT i (1217:1217:1217) (1281:1281:1281)) + (PORT oe (1676:1676:1676) (1756:1756:1756)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -257,8 +257,8 @@ (INSTANCE GPIO_1\[18\]\~output) (DELAY (ABSOLUTE - (PORT i (1118:1118:1118) (1163:1163:1163)) - (PORT oe (2137:2137:2137) (2196:2196:2196)) + (PORT i (1447:1447:1447) (1518:1518:1518)) + (PORT oe (1644:1644:1644) (1702:1702:1702)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -269,8 +269,8 @@ (INSTANCE GPIO_1\[19\]\~output) (DELAY (ABSOLUTE - (PORT i (1161:1161:1161) (1237:1237:1237)) - (PORT oe (2441:2441:2441) (2523:2523:2523)) + (PORT i (1400:1400:1400) (1428:1428:1428)) + (PORT oe (1397:1397:1397) (1462:1462:1462)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -281,8 +281,8 @@ (INSTANCE GPIO_1\[20\]\~output) (DELAY (ABSOLUTE - (PORT i (1455:1455:1455) (1530:1530:1530)) - (PORT oe (2096:2096:2096) (2158:2158:2158)) + (PORT i (1625:1625:1625) (1682:1682:1682)) + (PORT oe (1412:1412:1412) (1478:1478:1478)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -293,8 +293,8 @@ (INSTANCE GPIO_1\[21\]\~output) (DELAY (ABSOLUTE - (PORT i (1343:1343:1343) (1352:1352:1352)) - (PORT oe (2136:2136:2136) (2195:2195:2195)) + (PORT i (1455:1455:1455) (1530:1530:1530)) + (PORT oe (1701:1701:1701) (1755:1755:1755)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -305,8 +305,8 @@ (INSTANCE GPIO_1\[22\]\~output) (DELAY (ABSOLUTE - (PORT i (1213:1213:1213) (1275:1275:1275)) - (PORT oe (2035:2035:2035) (2069:2069:2069)) + (PORT i (1615:1615:1615) (1704:1704:1704)) + (PORT oe (1627:1627:1627) (1676:1676:1676)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -317,8 +317,8 @@ (INSTANCE GPIO_1\[23\]\~output) (DELAY (ABSOLUTE - (PORT i (1131:1131:1131) (1146:1146:1146)) - (PORT oe (2405:2405:2405) (2466:2466:2466)) + (PORT i (1389:1389:1389) (1468:1468:1468)) + (PORT oe (1392:1392:1392) (1455:1455:1455)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -329,8 +329,8 @@ (INSTANCE GPIO_1\[27\]\~output) (DELAY (ABSOLUTE - (PORT i (1412:1412:1412) (1417:1417:1417)) - (PORT oe (1643:1643:1643) (1693:1693:1693)) + (PORT i (1446:1446:1446) (1447:1447:1447)) + (PORT oe (1534:1534:1534) (1631:1631:1631)) (IOPATH i o (2378:2378:2378) (2455:2455:2455)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -341,8 +341,8 @@ (INSTANCE GPIO_1\[28\]\~output) (DELAY (ABSOLUTE - (PORT i (1794:1794:1794) (1688:1688:1688)) - (PORT oe (1916:1916:1916) (1948:1948:1948)) + (PORT i (1260:1260:1260) (1241:1241:1241)) + (PORT oe (1901:1901:1901) (1995:1995:1995)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -353,9 +353,9 @@ (INSTANCE GPIO_1\[29\]\~output) (DELAY (ABSOLUTE - (PORT i (1533:1533:1533) (1531:1531:1531)) - (PORT oe (1352:1352:1352) (1405:1405:1405)) - (IOPATH i o (2502:2502:2502) (2582:2582:2582)) + (PORT i (1183:1183:1183) (1166:1166:1166)) + (PORT oe (1856:1856:1856) (1947:1947:1947)) + (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) ) @@ -365,8 +365,8 @@ (INSTANCE GPIO_1\[30\]\~output) (DELAY (ABSOLUTE - (PORT i (1050:1050:1050) (1062:1062:1062)) - (PORT oe (1327:1327:1327) (1369:1369:1369)) + (PORT i (1167:1167:1167) (1158:1158:1158)) + (PORT oe (1000:1000:1000) (1069:1069:1069)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -387,7 +387,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1030:1030:1030) (1018:1018:1018)) + (PORT i (1031:1031:1031) (1018:1018:1018)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -397,7 +397,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1304:1304:1304) (1340:1340:1340)) + (PORT i (1473:1473:1473) (1574:1574:1574)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -452,7 +452,7 @@ (INSTANCE VGA_R\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1164:1164:1164) (1204:1204:1204)) + (PORT i (1116:1116:1116) (1178:1178:1178)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -462,7 +462,7 @@ (INSTANCE VGA_R\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1073:1073:1073) (1104:1104:1104)) + (PORT i (1137:1137:1137) (1173:1173:1173)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -472,7 +472,7 @@ (INSTANCE VGA_R\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (774:774:774) (751:751:751)) + (PORT i (869:869:869) (884:884:884)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -482,7 +482,7 @@ (INSTANCE VGA_R\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (986:986:986) (968:968:968)) + (PORT i (820:820:820) (820:820:820)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -492,7 +492,7 @@ (INSTANCE VGA_G\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (972:972:972) (958:958:958)) + (PORT i (576:576:576) (580:580:580)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -502,7 +502,7 @@ (INSTANCE VGA_G\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (721:721:721) (699:699:699)) + (PORT i (555:555:555) (581:581:581)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -512,7 +512,7 @@ (INSTANCE VGA_G\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (843:843:843) (812:812:812)) + (PORT i (1282:1282:1282) (1290:1290:1290)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -522,7 +522,7 @@ (INSTANCE VGA_G\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (843:843:843) (812:812:812)) + (PORT i (1282:1282:1282) (1290:1290:1290)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -532,7 +532,7 @@ (INSTANCE VGA_B\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (717:717:717) (702:702:702)) + (PORT i (1111:1111:1111) (1161:1161:1161)) (IOPATH i o (4557:4557:4557) (4190:4190:4190)) ) ) @@ -542,7 +542,7 @@ (INSTANCE VGA_B\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (692:692:692) (667:667:667)) + (PORT i (1244:1244:1244) (1229:1229:1229)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -552,7 +552,7 @@ (INSTANCE VGA_B\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (952:952:952) (940:940:940)) + (PORT i (1131:1131:1131) (1197:1197:1197)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -562,7 +562,7 @@ (INSTANCE VGA_B\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1378:1378:1378) (1350:1350:1350)) + (PORT i (1135:1135:1135) (1193:1193:1193)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -590,7 +590,7 @@ (INSTANCE GPIO_1\[25\]\~output) (DELAY (ABSOLUTE - (PORT i (2048:2048:2048) (1957:1957:1957)) + (PORT i (1748:1748:1748) (1663:1663:1663)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) ) ) @@ -600,7 +600,7 @@ (INSTANCE GPIO_1\[26\]\~output) (DELAY (ABSOLUTE - (PORT i (1307:1307:1307) (1281:1281:1281)) + (PORT i (1132:1132:1132) (1158:1158:1158)) (IOPATH i o (4127:4127:4127) (4477:4477:4477)) ) ) @@ -610,7 +610,7 @@ (INSTANCE GPIO_1\[31\]\~output) (DELAY (ABSOLUTE - (PORT i (927:927:927) (923:923:923)) + (PORT i (888:888:888) (865:865:865)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) ) ) @@ -620,11 +620,201 @@ (INSTANCE buzzer_out\~output) (DELAY (ABSOLUTE - (PORT i (1348:1348:1348) (1373:1373:1373)) + (PORT i (1643:1643:1643) (1721:1721:1721)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_BA\[0\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2051:2051:2051) (1961:1961:1961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_BA\[1\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2051:2051:2051) (1961:1961:1961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQM\[0\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2051:2051:2051) (1961:1961:1961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQM\[1\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2051:2051:2051) (1961:1961:1961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_RAS_N\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2144:2144:2144) (2064:2064:2064)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_CAS_N\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2144:2144:2144) (2064:2064:2064)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_CLK\~output) + (DELAY + (ABSOLUTE + (PORT i (1764:1764:1764) (1783:1783:1783)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_WE_N\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2144:2144:2144) (2064:2064:2064)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[0\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2144:2144:2144) (2064:2064:2064)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[1\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2051:2051:2051) (1961:1961:1961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[2\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2051:2051:2051) (1961:1961:1961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[3\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2051:2051:2051) (1961:1961:1961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[4\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2051:2051:2051) (1961:1961:1961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[5\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2051:2051:2051) (1961:1961:1961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[6\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2051:2051:2051) (1961:1961:1961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[7\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2051:2051:2051) (1961:1961:1961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[8\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2017:2017:2017) (1940:1940:1940)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[9\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2144:2144:2144) (2064:2064:2064)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[10\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2144:2144:2144) (2064:2064:2064)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[11\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2144:2144:2144) (2064:2064:2064)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_ADDR\[12\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2017:2017:2017) (1940:1940:1940)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_obuf") (INSTANCE I2C_SCLK\~output) @@ -643,6 +833,182 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1255:1255:1255) (1335:1335:1335)) + (PORT oe (1717:1717:1717) (1786:1786:1786)) + (IOPATH i o (2582:2582:2582) (2502:2502:2502)) + (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1398:1398:1398) (1454:1454:1454)) + (PORT oe (1717:1717:1717) (1786:1786:1786)) + (IOPATH i o (2582:2582:2582) (2502:2502:2502)) + (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1113:1113:1113) (1148:1148:1148)) + (PORT oe (1376:1376:1376) (1434:1434:1434)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1206:1206:1206) (1278:1278:1278)) + (PORT oe (1471:1471:1471) (1583:1583:1583)) + (IOPATH i o (2455:2455:2455) (2378:2378:2378)) + (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1183:1183:1183) (1228:1228:1228)) + (PORT oe (1200:1200:1200) (1240:1240:1240)) + (IOPATH i o (2582:2582:2582) (2502:2502:2502)) + (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1419:1419:1419) (1515:1515:1515)) + (PORT oe (1364:1364:1364) (1339:1339:1339)) + (IOPATH i o (2582:2582:2582) (2502:2502:2502)) + (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1148:1148:1148) (1200:1200:1200)) + (PORT oe (1364:1364:1364) (1339:1339:1339)) + (IOPATH i o (2582:2582:2582) (2502:2502:2502)) + (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (558:558:558) (558:558:558)) + (PORT oe (1367:1367:1367) (1406:1406:1406)) + (IOPATH i o (2535:2535:2535) (2445:2445:2445)) + (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1686:1686:1686) (1628:1628:1628)) + (IOPATH i o (2445:2445:2445) (2535:2535:2535)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1476:1476:1476) (1402:1402:1402)) + (IOPATH i o (2445:2445:2445) (2535:2535:2535)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1459:1459:1459) (1382:1382:1382)) + (IOPATH i o (2445:2445:2445) (2535:2535:2535)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1459:1459:1459) (1382:1382:1382)) + (IOPATH i o (2445:2445:2445) (2535:2535:2535)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1653:1653:1653) (1629:1629:1629)) + (IOPATH i o (2445:2445:2445) (2535:2535:2535)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1679:1679:1679) (1615:1615:1615)) + (IOPATH i o (2445:2445:2445) (2535:2535:2535)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[14\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1679:1679:1679) (1615:1615:1615)) + (IOPATH i o (2445:2445:2445) (2535:2535:2535)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE DRAM_DQ\[15\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1240:1240:1240) (1200:1200:1200)) + (IOPATH i o (2502:2502:2502) (2582:2582:2582)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE CLOCK_50\~input) @@ -707,8 +1073,8 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~0) (DELAY (ABSOLUTE - (PORT datab (245:245:245) (328:328:328)) - (PORT datad (552:552:552) (573:573:573)) + (PORT datab (243:243:243) (326:326:326)) + (PORT datad (551:551:551) (574:574:574)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -734,32 +1100,7 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (716:716:716) (747:747:747)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1158:1158:1158)) - (PORT datad (1110:1110:1110) (1159:1159:1159)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|ena_M) - (DELAY - (ABSOLUTE - (PORT datac (1094:1094:1094) (1132:1132:1132)) - (PORT datad (1106:1106:1106) (1160:1160:1160)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT inclk[0] (720:720:720) (751:751:751)) ) ) ) @@ -772,10573 +1113,6 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (490:490:490)) - (PORT datad (1994:1994:1994) (2109:2109:2109)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|nmi_armed) - (DELAY - (ABSOLUTE - (PORT clk (1476:1476:1476) (1490:1490:1490)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1325:1325:1325) (1320:1320:1320)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (790:790:790) (826:826:826)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) - (DELAY - (ABSOLUTE - (PORT datac (243:243:243) (323:323:323)) - (PORT datad (252:252:252) (325:325:325)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (2418:2418:2418) (2567:2567:2567)) - (PORT datab (2411:2411:2411) (2541:2541:2541)) - (PORT datad (1577:1577:1577) (1737:1737:1737)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M3_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1115:1115:1115) (1160:1160:1160)) - (PORT datab (408:408:408) (481:481:481)) - (PORT datad (1111:1111:1111) (1161:1161:1161)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M3_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1355:1355:1355) (1381:1381:1381)) - (PORT datab (1537:1537:1537) (1647:1647:1647)) - (PORT datac (1348:1348:1348) (1441:1441:1441)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M4_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1178:1178:1178)) - (PORT datab (413:413:413) (488:488:488)) - (PORT datad (1104:1104:1104) (1156:1156:1156)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M4_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal32\~0) - (DELAY - (ABSOLUTE - (PORT datab (393:393:393) (466:466:466)) - (PORT datad (667:667:667) (742:742:742)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) - (DELAY - (ABSOLUTE - (PORT datab (2598:2598:2598) (2742:2742:2742)) - (PORT datad (1607:1607:1607) (1729:1729:1729)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|table_xx\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1365:1365:1365) (1484:1484:1484)) - (PORT datad (1197:1197:1197) (1317:1317:1317)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1675:1675:1675) (1712:1712:1712)) - (PORT datab (945:945:945) (983:983:983)) - (PORT datac (2134:2134:2134) (2287:2287:2287)) - (PORT datad (1162:1162:1162) (1232:1232:1232)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT datac (1459:1459:1459) (1537:1537:1537)) - (PORT datad (2262:2262:2262) (2332:2332:2332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal36\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1246:1246:1246) (1343:1343:1343)) - (PORT datab (1671:1671:1671) (1786:1786:1786)) - (PORT datac (906:906:906) (959:959:959)) - (PORT datad (943:943:943) (998:998:998)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) - (DELAY - (ABSOLUTE - (PORT dataa (1739:1739:1739) (1786:1786:1786)) - (PORT datab (1426:1426:1426) (1455:1455:1455)) - (PORT datac (846:846:846) (882:882:882)) - (PORT datad (789:789:789) (792:792:792)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1224:1224:1224) (1329:1329:1329)) - (PORT datab (2644:2644:2644) (2764:2764:2764)) - (PORT datac (844:844:844) (879:879:879)) - (PORT datad (972:972:972) (1035:1035:1035)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instCB) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1588:1588:1588) (1563:1563:1563)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~0) - (DELAY - (ABSOLUTE - (PORT dataa (711:711:711) (808:808:808)) - (PORT datab (1233:1233:1233) (1347:1347:1347)) - (PORT datac (988:988:988) (1067:1067:1067)) - (PORT datad (1323:1323:1323) (1441:1441:1441)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2337:2337:2337) (2490:2490:2490)) - (PORT datab (1667:1667:1667) (1786:1786:1786)) - (PORT datac (905:905:905) (957:957:957)) - (PORT datad (672:672:672) (720:720:720)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) - (DELAY - (ABSOLUTE - (PORT dataa (1761:1761:1761) (1838:1838:1838)) - (PORT datab (839:839:839) (854:854:854)) - (PORT datac (1396:1396:1396) (1420:1420:1420)) - (PORT datad (2042:2042:2042) (2106:2106:2106)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instED) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1588:1588:1588) (1563:1563:1563)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (810:810:810)) - (PORT datac (981:981:981) (1058:1058:1058)) - (PORT datad (1323:1323:1323) (1434:1434:1434)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2169:2169:2169) (2327:2327:2327)) - (PORT datac (1460:1460:1460) (1537:1537:1537)) - (PORT datad (2263:2263:2263) (2329:2329:2329)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_im_we) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (636:636:636)) - (PORT datab (1050:1050:1050) (1169:1169:1169)) - (PORT datac (1337:1337:1337) (1469:1469:1469)) - (PORT datad (915:915:915) (959:959:959)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal49\~0) - (DELAY - (ABSOLUTE - (PORT datab (997:997:997) (1105:1105:1105)) - (PORT datac (656:656:656) (719:719:719)) - (PORT datad (1244:1244:1244) (1328:1328:1328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1410:1410:1410) (1499:1499:1499)) - (PORT datab (1489:1489:1489) (1614:1614:1614)) - (PORT datac (1433:1433:1433) (1524:1524:1524)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (711:711:711) (809:809:809)) - (PORT datab (1233:1233:1233) (1347:1347:1347)) - (PORT datac (989:989:989) (1067:1067:1067)) - (PORT datad (1323:1323:1323) (1441:1441:1441)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1232:1232:1232) (1301:1301:1301)) - (PORT datab (1273:1273:1273) (1368:1368:1368)) - (PORT datad (711:711:711) (773:773:773)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2639:2639:2639) (2814:2814:2814)) - (PORT datab (899:899:899) (934:934:934)) - (PORT datac (1110:1110:1110) (1167:1167:1167)) - (PORT datad (1150:1150:1150) (1194:1194:1194)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (933:933:933) (1033:1033:1033)) - (PORT datab (1561:1561:1561) (1662:1662:1662)) - (PORT datac (1411:1411:1411) (1476:1476:1476)) - (PORT datad (201:201:201) (238:238:238)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|nM1_int\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1239:1239:1239)) - (PORT datad (2109:2109:2109) (2254:2254:2254)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1086:1086:1086) (1149:1149:1149)) - (PORT datab (1113:1113:1113) (1123:1123:1123)) - (PORT datac (333:333:333) (359:359:359)) - (PORT datad (689:689:689) (743:743:743)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT datac (1439:1439:1439) (1545:1545:1545)) - (PORT datad (1464:1464:1464) (1551:1551:1551)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1247:1247:1247) (1335:1335:1335)) - (PORT datab (1669:1669:1669) (1782:1782:1782)) - (PORT datac (1700:1700:1700) (1785:1785:1785)) - (PORT datad (944:944:944) (1001:1001:1001)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~7) - (DELAY - (ABSOLUTE - (PORT datac (1974:1974:1974) (2154:2154:2154)) - (PORT datad (1235:1235:1235) (1306:1306:1306)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1939:1939:1939) (2060:2060:2060)) - (PORT datac (2560:2560:2560) (2661:2661:2661)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (937:937:937)) - (PORT datab (1029:1029:1029) (1093:1093:1093)) - (PORT datac (849:849:849) (913:913:913)) - (PORT datad (929:929:929) (973:973:973)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~1) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (941:941:941)) - (PORT datab (898:898:898) (917:917:917)) - (PORT datac (919:919:919) (1011:1011:1011)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (940:940:940)) - (PORT datab (901:901:901) (913:913:913)) - (PORT datac (920:920:920) (1009:1009:1009)) - (PORT datad (1166:1166:1166) (1216:1216:1216)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (896:896:896)) - (PORT datac (977:977:977) (1048:1048:1048)) - (PORT datad (1170:1170:1170) (1184:1184:1184)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2169:2169:2169) (2322:2322:2322)) - (PORT datac (1461:1461:1461) (1534:1534:1534)) - (PORT datad (2261:2261:2261) (2326:2326:2326)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~2) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (972:972:972)) - (PORT datab (1721:1721:1721) (1812:1812:1812)) - (PORT datac (1148:1148:1148) (1153:1153:1153)) - (PORT datad (650:650:650) (690:690:690)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (944:944:944) (975:975:975)) - (PORT datab (2317:2317:2317) (2471:2471:2471)) - (PORT datac (1702:1702:1702) (1788:1788:1788)) - (PORT datad (669:669:669) (716:716:716)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1211:1211:1211) (1331:1331:1331)) - (PORT datab (2075:2075:2075) (2256:2256:2256)) - (PORT datac (862:862:862) (881:881:881)) - (PORT datad (1458:1458:1458) (1561:1561:1561)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~8) - (DELAY - (ABSOLUTE - (PORT datab (1418:1418:1418) (1489:1489:1489)) - (PORT datac (1562:1562:1562) (1631:1631:1631)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~6) - (DELAY - (ABSOLUTE - (PORT datac (1595:1595:1595) (1686:1686:1686)) - (PORT datad (1897:1897:1897) (2018:2018:2018)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~9) - (DELAY - (ABSOLUTE - (PORT datac (1033:1033:1033) (1103:1103:1103)) - (PORT datad (985:985:985) (1046:1046:1046)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1003:1003:1003) (1060:1060:1060)) - (PORT datab (989:989:989) (1052:1052:1052)) - (PORT datac (903:903:903) (941:941:941)) - (PORT datad (2055:2055:2055) (2108:2108:2108)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (461:461:461)) - (PORT datab (1160:1160:1160) (1195:1195:1195)) - (PORT datac (623:623:623) (685:685:685)) - (PORT datad (1108:1108:1108) (1138:1138:1138)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal44\~0) - (DELAY - (ABSOLUTE - (PORT dataa (711:711:711) (810:810:810)) - (PORT datab (1238:1238:1238) (1352:1352:1352)) - (PORT datac (982:982:982) (1059:1059:1059)) - (PORT datad (1323:1323:1323) (1435:1435:1435)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~16) - (DELAY - (ABSOLUTE - (PORT dataa (976:976:976) (1074:1074:1074)) - (PORT datab (1336:1336:1336) (1358:1358:1358)) - (PORT datac (931:931:931) (1016:1016:1016)) - (PORT datad (1108:1108:1108) (1132:1132:1132)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~13) - (DELAY - (ABSOLUTE - (PORT datab (836:836:836) (897:897:897)) - (PORT datac (619:619:619) (671:671:671)) - (PORT datad (213:213:213) (245:245:245)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal50\~0) - (DELAY - (ABSOLUTE - (PORT datab (998:998:998) (1107:1107:1107)) - (PORT datac (656:656:656) (717:717:717)) - (PORT datad (1193:1193:1193) (1255:1255:1255)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1233:1233:1233) (1300:1300:1300)) - (PORT datab (1273:1273:1273) (1368:1368:1368)) - (PORT datad (711:711:711) (773:773:773)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~17) - (DELAY - (ABSOLUTE - (PORT dataa (967:967:967) (1063:1063:1063)) - (PORT datab (1112:1112:1112) (1107:1107:1107)) - (PORT datac (928:928:928) (1011:1011:1011)) - (PORT datad (1085:1085:1085) (1082:1082:1082)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~5) - (DELAY - (ABSOLUTE - (PORT datac (1607:1607:1607) (1722:1722:1722)) - (PORT datad (984:984:984) (1047:1047:1047)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (674:674:674)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (199:199:199) (237:237:237)) - (PORT datad (1103:1103:1103) (1112:1112:1112)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1593:1593:1593) (1671:1671:1671)) - (PORT datab (1420:1420:1420) (1492:1492:1492)) - (PORT datac (372:372:372) (399:399:399)) - (PORT datad (1786:1786:1786) (1904:1904:1904)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1089:1089:1089) (1107:1107:1107)) - (PORT datab (236:236:236) (282:282:282)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1302:1302:1302) (1399:1399:1399)) - (PORT datab (1499:1499:1499) (1604:1604:1604)) - (PORT datac (1460:1460:1460) (1551:1551:1551)) - (PORT datad (2054:2054:2054) (2222:2222:2222)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instIY1) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1586:1586:1586) (1563:1563:1563)) - (PORT ena (820:820:820) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (960:960:960)) - (PORT datac (643:643:643) (708:708:708)) - (PORT datad (1365:1365:1365) (1481:1481:1481)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1259:1259:1259) (1368:1368:1368)) - (PORT datab (463:463:463) (524:524:524)) - (PORT datac (1699:1699:1699) (1754:1754:1754)) - (PORT datad (267:267:267) (321:321:321)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (709:709:709) (805:805:805)) - (PORT datab (1019:1019:1019) (1101:1101:1101)) - (PORT datac (676:676:676) (769:769:769)) - (PORT datad (1322:1322:1322) (1435:1435:1435)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1624:1624:1624) (1717:1717:1717)) - (PORT datab (1533:1533:1533) (1585:1585:1585)) - (PORT datac (1709:1709:1709) (1830:1830:1830)) - (PORT datad (1494:1494:1494) (1626:1626:1626)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1299:1299:1299) (1388:1388:1388)) - (PORT datab (1243:1243:1243) (1323:1323:1323)) - (PORT datac (1034:1034:1034) (1082:1082:1082)) - (PORT datad (1678:1678:1678) (1738:1738:1738)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~26) - (DELAY - (ABSOLUTE - (PORT datac (685:685:685) (734:734:734)) - (PORT datad (1734:1734:1734) (1851:1851:1851)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (666:666:666)) - (PORT datac (1102:1102:1102) (1151:1151:1151)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (252:252:252)) - (PORT datab (244:244:244) (291:291:291)) - (PORT datac (669:669:669) (688:688:688)) - (PORT datad (2054:2054:2054) (2107:2107:2107)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1002:1002:1002) (1065:1065:1065)) - (PORT datab (1219:1219:1219) (1281:1281:1281)) - (PORT datac (688:688:688) (740:740:740)) - (PORT datad (179:179:179) (206:206:206)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (1031:1031:1031)) - (PORT datab (1557:1557:1557) (1661:1661:1661)) - (PORT datac (1407:1407:1407) (1474:1474:1474)) - (PORT datad (203:203:203) (238:238:238)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal55\~0) - (DELAY - (ABSOLUTE - (PORT dataa (288:288:288) (386:386:386)) - (PORT datac (902:902:902) (964:964:964)) - (PORT datad (928:928:928) (984:984:984)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1762:1762:1762) (1872:1872:1872)) - (PORT datac (1146:1146:1146) (1226:1226:1226)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (664:664:664)) - (PORT datab (1178:1178:1178) (1215:1215:1215)) - (PORT datac (934:934:934) (1030:1030:1030)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (723:723:723)) - (PORT datab (653:653:653) (674:674:674)) - (PORT datac (936:936:936) (1036:1036:1036)) - (PORT datad (898:898:898) (943:943:943)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (958:958:958)) - (PORT datab (1199:1199:1199) (1222:1222:1222)) - (PORT datac (1813:1813:1813) (1890:1890:1890)) - (PORT datad (871:871:871) (910:910:910)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1687:1687:1687) (1746:1746:1746)) - (PORT datac (1659:1659:1659) (1737:1737:1737)) - (PORT datad (1165:1165:1165) (1209:1209:1209)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~0) - (DELAY - (ABSOLUTE - (PORT datac (826:826:826) (880:880:880)) - (PORT datad (900:900:900) (971:971:971)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1685:1685:1685) (1750:1750:1750)) - (PORT datab (1691:1691:1691) (1776:1776:1776)) - (PORT datac (1479:1479:1479) (1575:1575:1575)) - (PORT datad (1244:1244:1244) (1311:1311:1311)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1465:1465:1465) (1537:1537:1537)) - (PORT datab (1233:1233:1233) (1318:1318:1318)) - (PORT datac (1424:1424:1424) (1514:1514:1514)) - (PORT datad (825:825:825) (838:838:838)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (914:914:914)) - (PORT datab (1241:1241:1241) (1279:1279:1279)) - (PORT datac (1377:1377:1377) (1384:1384:1384)) - (PORT datad (1263:1263:1263) (1301:1301:1301)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~1) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (657:657:657)) - (PORT datab (963:963:963) (1059:1059:1059)) - (PORT datad (1154:1154:1154) (1176:1176:1176)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1565:1565:1565) (1659:1659:1659)) - (PORT datab (982:982:982) (1039:1039:1039)) - (PORT datac (1634:1634:1634) (1749:1749:1749)) - (PORT datad (1216:1216:1216) (1293:1293:1293)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal25\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1460:1460:1460) (1559:1559:1559)) - (PORT datab (1540:1540:1540) (1676:1676:1676)) - (PORT datac (1379:1379:1379) (1439:1439:1439)) - (PORT datad (1566:1566:1566) (1596:1596:1596)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (894:894:894) (913:913:913)) - (PORT datab (1819:1819:1819) (1900:1900:1900)) - (PORT datac (867:867:867) (883:883:883)) - (PORT datad (1475:1475:1475) (1552:1552:1552)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1220:1220:1220) (1307:1307:1307)) - (PORT datac (948:948:948) (1024:1024:1024)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~0) - (DELAY - (ABSOLUTE - (PORT dataa (940:940:940) (969:969:969)) - (PORT datab (936:936:936) (992:992:992)) - (PORT datac (1633:1633:1633) (1753:1753:1753)) - (PORT datad (1215:1215:1215) (1294:1294:1294)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~4) - (DELAY - (ABSOLUTE - (PORT datac (1720:1720:1720) (1792:1792:1792)) - (PORT datad (2039:2039:2039) (2100:2100:2100)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal29\~0) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (1158:1158:1158) (1201:1201:1201)) - (PORT datac (1618:1618:1618) (1607:1607:1607)) - (PORT datad (1454:1454:1454) (1538:1538:1538)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1564:1564:1564) (1657:1657:1657)) - (PORT datab (978:978:978) (1038:1038:1038)) - (PORT datac (1634:1634:1634) (1759:1759:1759)) - (PORT datad (1220:1220:1220) (1302:1302:1302)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal34\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2169:2169:2169) (2326:2326:2326)) - (PORT datab (948:948:948) (988:988:988)) - (PORT datac (193:193:193) (227:227:227)) - (PORT datad (416:416:416) (461:461:461)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (445:445:445) (500:500:500)) - (PORT datab (942:942:942) (982:982:982)) - (PORT datac (2138:2138:2138) (2282:2282:2282)) - (PORT datad (1141:1141:1141) (1176:1176:1176)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal35\~0) - (DELAY - (ABSOLUTE - (PORT dataa (446:446:446) (504:504:504)) - (PORT datab (946:946:946) (982:982:982)) - (PORT datac (2134:2134:2134) (2284:2284:2284)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal38\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1627:1627:1627) (1717:1717:1717)) - (PORT datab (1533:1533:1533) (1663:1663:1663)) - (PORT datac (1709:1709:1709) (1827:1827:1827)) - (PORT datad (1445:1445:1445) (1492:1492:1492)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1114:1114:1114) (1137:1137:1137)) - (PORT datab (1107:1107:1107) (1172:1172:1172)) - (PORT datac (580:580:580) (611:611:611)) - (PORT datad (895:895:895) (945:945:945)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (867:867:867) (927:927:927)) - (PORT datab (1362:1362:1362) (1426:1426:1426)) - (PORT datac (584:584:584) (617:617:617)) - (PORT datad (583:583:583) (602:602:602)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~0) - (DELAY - (ABSOLUTE - (PORT datab (1940:1940:1940) (2011:2011:2011)) - (PORT datac (1163:1163:1163) (1222:1222:1222)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (450:450:450) (507:507:507)) - (PORT datab (949:949:949) (988:988:988)) - (PORT datac (2135:2135:2135) (2282:2282:2282)) - (PORT datad (364:364:364) (385:385:385)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1290:1290:1290) (1360:1360:1360)) - (PORT datab (1193:1193:1193) (1242:1242:1242)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (1264:1264:1264) (1365:1365:1365)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (717:717:717)) - (PORT datab (639:639:639) (661:661:661)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (1158:1158:1158) (1203:1203:1203)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (939:939:939) (959:959:959)) - (PORT datab (231:231:231) (282:282:282)) - (PORT datac (629:629:629) (651:651:651)) - (PORT datad (649:649:649) (681:681:681)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (1447:1447:1447) (1493:1493:1493)) - (PORT datab (1229:1229:1229) (1315:1315:1315)) - (PORT datac (680:680:680) (717:717:717)) - (PORT datad (1141:1141:1141) (1161:1161:1161)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (708:708:708) (759:759:759)) - (PORT datab (1141:1141:1141) (1169:1169:1169)) - (PORT datac (1819:1819:1819) (1896:1896:1896)) - (PORT datad (588:588:588) (613:613:613)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1461:1461:1461) (1560:1560:1560)) - (PORT datab (1137:1137:1137) (1179:1179:1179)) - (PORT datac (1192:1192:1192) (1287:1287:1287)) - (PORT datad (655:655:655) (686:686:686)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1468:1468:1468) (1566:1566:1566)) - (PORT datab (683:683:683) (725:725:725)) - (PORT datac (1193:1193:1193) (1278:1278:1278)) - (PORT datad (1406:1406:1406) (1445:1445:1445)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|M5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1173:1173:1173)) - (PORT datab (267:267:267) (350:350:350)) - (PORT datad (1104:1104:1104) (1160:1160:1160)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|M5) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) - (DELAY - (ABSOLUTE - (PORT datab (1589:1589:1589) (1719:1719:1719)) - (PORT datac (2606:2606:2606) (2704:2704:2704)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~29) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (665:665:665)) - (PORT datab (931:931:931) (978:978:978)) - (PORT datac (1004:1004:1004) (1061:1061:1061)) - (PORT datad (662:662:662) (691:691:691)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1946:1946:1946) (2050:2050:2050)) - (PORT datab (687:687:687) (729:729:729)) - (PORT datac (658:658:658) (709:709:709)) - (PORT datad (585:585:585) (615:615:615)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1904:1904:1904) (1999:1999:1999)) - (PORT datab (898:898:898) (961:961:961)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (187:187:187) (219:219:219)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1259:1259:1259) (1371:1371:1371)) - (PORT datab (464:464:464) (522:522:522)) - (PORT datac (1696:1696:1696) (1755:1755:1755)) - (PORT datad (268:268:268) (323:323:323)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1366:1366:1366) (1481:1481:1481)) - (PORT datab (934:934:934) (992:992:992)) - (PORT datac (958:958:958) (990:990:990)) - (PORT datad (1201:1201:1201) (1318:1318:1318)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~14) - (DELAY - (ABSOLUTE - (PORT dataa (972:972:972) (1071:1071:1071)) - (PORT datab (1335:1335:1335) (1360:1360:1360)) - (PORT datac (927:927:927) (1015:1015:1015)) - (PORT datad (1107:1107:1107) (1130:1130:1130)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (679:679:679)) - (PORT datab (1262:1262:1262) (1301:1301:1301)) - (PORT datac (566:566:566) (573:573:573)) - (PORT datad (1626:1626:1626) (1701:1701:1701)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~0) - (DELAY - (ABSOLUTE - (PORT dataa (708:708:708) (808:808:808)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (255:255:255) (343:343:343)) - (PORT datad (881:881:881) (941:941:941)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (933:933:933)) - (PORT datab (1109:1109:1109) (1175:1175:1175)) - (PORT datac (1089:1089:1089) (1121:1121:1121)) - (PORT datad (673:673:673) (713:713:713)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) - (DELAY - (ABSOLUTE - (PORT dataa (449:449:449) (492:492:492)) - (PORT datab (1938:1938:1938) (2051:2051:2051)) - (PORT datac (1035:1035:1035) (1084:1084:1084)) - (PORT datad (1561:1561:1561) (1612:1612:1612)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (1000:1000:1000)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (895:895:895) (945:945:945)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (683:683:683)) - (PORT datab (1196:1196:1196) (1213:1213:1213)) - (PORT datac (208:208:208) (248:248:248)) - (PORT datad (624:624:624) (642:642:642)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (458:458:458)) - (PORT datab (1170:1170:1170) (1201:1201:1201)) - (PORT datac (620:620:620) (684:684:684)) - (PORT datad (1113:1113:1113) (1142:1142:1142)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1626:1626:1626) (1717:1717:1717)) - (PORT datab (1533:1533:1533) (1584:1584:1584)) - (PORT datac (1703:1703:1703) (1827:1827:1827)) - (PORT datad (1490:1490:1490) (1625:1625:1625)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1624:1624:1624) (1719:1719:1719)) - (PORT datab (1534:1534:1534) (1581:1581:1581)) - (PORT datac (1711:1711:1711) (1826:1826:1826)) - (PORT datad (1494:1494:1494) (1620:1620:1620)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1688:1688:1688) (1727:1727:1727)) - (PORT datab (1470:1470:1470) (1564:1564:1564)) - (PORT datac (2563:2563:2563) (2660:2660:2660)) - (PORT datad (1901:1901:1901) (2013:2013:2013)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (682:682:682)) - (PORT datab (1262:1262:1262) (1302:1302:1302)) - (PORT datac (1116:1116:1116) (1135:1135:1135)) - (PORT datad (553:553:553) (571:571:571)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1260:1260:1260) (1370:1370:1370)) - (PORT datab (464:464:464) (521:521:521)) - (PORT datac (1697:1697:1697) (1755:1755:1755)) - (PORT datad (267:267:267) (323:323:323)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1107:1107:1107) (1153:1153:1153)) - (PORT datab (1145:1145:1145) (1184:1184:1184)) - (PORT datac (548:548:548) (563:563:563)) - (PORT datad (609:609:609) (634:634:634)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (291:291:291) (358:358:358)) - (PORT datab (465:465:465) (519:519:519)) - (PORT datac (191:191:191) (223:223:223)) - (PORT datad (1368:1368:1368) (1479:1479:1479)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal46\~0) - (DELAY - (ABSOLUTE - (PORT dataa (286:286:286) (382:382:382)) - (PORT datab (952:952:952) (1018:1018:1018)) - (PORT datac (903:903:903) (963:963:963)) - (PORT datad (1192:1192:1192) (1312:1312:1312)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1252:1252:1252) (1367:1367:1367)) - (PORT datab (866:866:866) (891:891:891)) - (PORT datac (1704:1704:1704) (1755:1755:1755)) - (PORT datad (263:263:263) (316:316:316)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) - (DELAY - (ABSOLUTE - (PORT dataa (2111:2111:2111) (2254:2254:2254)) - (PORT datab (2048:2048:2048) (2161:2161:2161)) - (PORT datac (986:986:986) (1043:1043:1043)) - (PORT datad (1210:1210:1210) (1253:1253:1253)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1380:1380:1380) (1424:1424:1424)) - (PORT datab (1059:1059:1059) (1143:1143:1143)) - (PORT datac (754:754:754) (762:762:762)) - (PORT datad (1235:1235:1235) (1269:1269:1269)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (982:982:982) (1061:1061:1061)) - (PORT datac (1148:1148:1148) (1203:1203:1203)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (296:296:296) (369:369:369)) - (PORT datab (465:465:465) (518:518:518)) - (PORT datac (1197:1197:1197) (1289:1289:1289)) - (PORT datad (1363:1363:1363) (1476:1476:1476)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1248:1248:1248)) - (PORT datab (2197:2197:2197) (2296:2296:2296)) - (PORT datac (1334:1334:1334) (1445:1445:1445)) - (PORT datad (959:959:959) (1022:1022:1022)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1792:1792:1792) (1883:1883:1883)) - (PORT datab (1288:1288:1288) (1337:1337:1337)) - (PORT datac (1377:1377:1377) (1384:1384:1384)) - (PORT datad (883:883:883) (905:905:905)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (635:635:635)) - (PORT datac (550:550:550) (559:559:559)) - (PORT datad (1232:1232:1232) (1290:1290:1290)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (861:861:861) (876:876:876)) - (PORT datad (848:848:848) (889:889:889)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) - (DELAY - (ABSOLUTE - (PORT datac (2061:2061:2061) (2184:2184:2184)) - (PORT datad (959:959:959) (1014:1014:1014)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1615:1615:1615) (1714:1714:1714)) - (PORT datab (1532:1532:1532) (1580:1580:1580)) - (PORT datac (1706:1706:1706) (1825:1825:1825)) - (PORT datad (1489:1489:1489) (1621:1621:1621)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~9) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (717:717:717)) - (PORT datab (1494:1494:1494) (1553:1553:1553)) - (PORT datac (1138:1138:1138) (1205:1205:1205)) - (PORT datad (1383:1383:1383) (1432:1432:1432)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (2148:2148:2148) (2325:2325:2325)) - (PORT datab (675:675:675) (746:746:746)) - (PORT datac (1715:1715:1715) (1794:1794:1794)) - (PORT datad (205:205:205) (235:235:235)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1299:1299:1299) (1399:1399:1399)) - (PORT datad (2046:2046:2046) (2211:2211:2211)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (999:999:999)) - (PORT datab (454:454:454) (482:482:482)) - (PORT datac (408:408:408) (448:448:448)) - (PORT datad (1564:1564:1564) (1622:1622:1622)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (651:651:651)) - (PORT datab (1155:1155:1155) (1200:1200:1200)) - (PORT datac (1451:1451:1451) (1502:1502:1502)) - (PORT datad (337:337:337) (358:358:358)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~7) - (DELAY - (ABSOLUTE - (PORT datac (1520:1520:1520) (1613:1613:1613)) - (PORT datad (1159:1159:1159) (1225:1225:1225)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1261:1261:1261) (1371:1371:1371)) - (PORT datab (865:865:865) (889:889:889)) - (PORT datac (1688:1688:1688) (1749:1749:1749)) - (PORT datad (267:267:267) (323:323:323)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1260:1260:1260) (1371:1371:1371)) - (PORT datab (465:465:465) (519:519:519)) - (PORT datac (1689:1689:1689) (1752:1752:1752)) - (PORT datad (268:268:268) (320:320:320)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1420:1420:1420) (1451:1451:1451)) - (PORT datab (1101:1101:1101) (1122:1122:1122)) - (PORT datac (1072:1072:1072) (1084:1084:1084)) - (PORT datad (939:939:939) (973:973:973)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (719:719:719)) - (PORT datab (1167:1167:1167) (1240:1240:1240)) - (PORT datac (1455:1455:1455) (1509:1509:1509)) - (PORT datad (1468:1468:1468) (1520:1520:1520)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (420:420:420)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (623:623:623) (666:666:666)) - (PORT datad (189:189:189) (220:220:220)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (566:566:566) (593:593:593)) - (PORT datab (860:860:860) (886:886:886)) - (PORT datac (854:854:854) (889:889:889)) - (PORT datad (805:805:805) (822:822:822)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1150:1150:1150) (1163:1163:1163)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (186:186:186) (228:228:228)) - (PORT datad (179:179:179) (206:206:206)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (483:483:483)) - (PORT datab (1218:1218:1218) (1272:1272:1272)) - (PORT datac (679:679:679) (709:709:709)) - (PORT datad (1295:1295:1295) (1387:1387:1387)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~8) - (DELAY - (ABSOLUTE - (PORT datab (2915:2915:2915) (3094:3094:3094)) - (PORT datac (2028:2028:2028) (2098:2098:2098)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1889:1889:1889) (1934:1934:1934)) - (PORT datab (2084:2084:2084) (2215:2215:2215)) - (PORT datac (1111:1111:1111) (1144:1144:1144)) - (PORT datad (208:208:208) (238:238:238)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) - (DELAY - (ABSOLUTE - (PORT datac (1234:1234:1234) (1326:1326:1326)) - (PORT datad (625:625:625) (665:665:665)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1232:1232:1232)) - (PORT datab (906:906:906) (961:961:961)) - (PORT datac (2032:2032:2032) (2056:2056:2056)) - (PORT datad (1479:1479:1479) (1541:1541:1541)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) - (DELAY - (ABSOLUTE - (PORT dataa (1057:1057:1057) (1151:1151:1151)) - (PORT datab (2381:2381:2381) (2493:2493:2493)) - (PORT datad (2113:2113:2113) (2257:2257:2257)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1487:1487:1487) (1536:1536:1536)) - (PORT datab (1011:1011:1011) (1078:1078:1078)) - (PORT datac (900:900:900) (921:921:921)) - (PORT datad (1172:1172:1172) (1187:1187:1187)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1450:1450:1450) (1479:1479:1479)) - (PORT datab (1137:1137:1137) (1178:1178:1178)) - (PORT datac (337:337:337) (365:365:365)) - (PORT datad (1137:1137:1137) (1159:1159:1159)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (412:412:412)) - (PORT datab (1088:1088:1088) (1114:1114:1114)) - (PORT datac (1575:1575:1575) (1617:1617:1617)) - (PORT datad (811:811:811) (828:828:828)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (1142:1142:1142) (1206:1206:1206)) - (PORT datab (1169:1169:1169) (1204:1204:1204)) - (PORT datac (835:835:835) (863:863:863)) - (PORT datad (800:800:800) (827:827:827)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1212:1212:1212)) - (PORT datab (286:286:286) (351:351:351)) - (PORT datac (253:253:253) (312:312:312)) - (PORT datad (252:252:252) (297:297:297)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) - (DELAY - (ABSOLUTE - (PORT datac (948:948:948) (1024:1024:1024)) - (PORT datad (2023:2023:2023) (2146:2146:2146)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (897:897:897)) - (PORT datab (1012:1012:1012) (1081:1081:1081)) - (PORT datac (1223:1223:1223) (1284:1284:1284)) - (PORT datad (1171:1171:1171) (1183:1183:1183)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) - (DELAY - (ABSOLUTE - (PORT datab (219:219:219) (257:257:257)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1230:1230:1230)) - (PORT datab (1013:1013:1013) (1082:1082:1082)) - (PORT datac (2030:2030:2030) (2056:2056:2056)) - (PORT datad (1479:1479:1479) (1543:1543:1543)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1303:1303:1303) (1377:1377:1377)) - (PORT datab (1170:1170:1170) (1231:1231:1231)) - (PORT datac (840:840:840) (887:887:887)) - (PORT datad (1322:1322:1322) (1434:1434:1434)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (984:984:984)) - (PORT datab (941:941:941) (1009:1009:1009)) - (PORT datac (1210:1210:1210) (1289:1289:1289)) - (PORT datad (658:658:658) (688:688:688)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1353:1353:1353) (1482:1482:1482)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (382:382:382) (410:410:410)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal69\~0) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (968:968:968)) - (PORT datab (1718:1718:1718) (1808:1808:1808)) - (PORT datac (1144:1144:1144) (1148:1148:1148)) - (PORT datad (653:653:653) (693:693:693)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1201:1201:1201) (1290:1290:1290)) - (PORT datad (1198:1198:1198) (1259:1259:1259)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1009:1009:1009) (1044:1044:1044)) - (PORT datab (2023:2023:2023) (2060:2060:2060)) - (PORT datac (1148:1148:1148) (1153:1153:1153)) - (PORT datad (650:650:650) (690:690:690)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1758:1758:1758) (1876:1876:1876)) - (PORT datab (915:915:915) (977:977:977)) - (PORT datad (216:216:216) (242:242:242)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal56\~0) - (DELAY - (ABSOLUTE - (PORT dataa (670:670:670) (725:725:725)) - (PORT datab (1178:1178:1178) (1215:1215:1215)) - (PORT datac (934:934:934) (1029:1029:1029)) - (PORT datad (903:903:903) (950:950:950)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1467:1467:1467) (1537:1537:1537)) - (PORT datab (1228:1228:1228) (1312:1312:1312)) - (PORT datac (1432:1432:1432) (1520:1520:1520)) - (PORT datad (820:820:820) (833:833:833)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~2) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (845:845:845)) - (PORT datab (854:854:854) (887:887:887)) - (PORT datad (673:673:673) (693:693:693)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) - (DELAY - (ABSOLUTE - (PORT dataa (2011:2011:2011) (2114:2114:2114)) - (PORT datab (2111:2111:2111) (2221:2221:2221)) - (PORT datac (547:547:547) (569:569:569)) - (PORT datad (1739:1739:1739) (1782:1782:1782)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (882:882:882)) - (PORT datab (952:952:952) (1011:1011:1011)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (1472:1472:1472) (1533:1533:1533)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~5) - (DELAY - (ABSOLUTE - (PORT datac (1162:1162:1162) (1174:1174:1174)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1237:1237:1237) (1303:1303:1303)) - (PORT datab (992:992:992) (1101:1101:1101)) - (PORT datac (657:657:657) (716:716:716)) - (PORT datad (1239:1239:1239) (1323:1323:1323)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) - (DELAY - (ABSOLUTE - (PORT datab (1082:1082:1082) (1193:1193:1193)) - (PORT datac (1465:1465:1465) (1548:1548:1548)) - (PORT datad (2348:2348:2348) (2497:2497:2497)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (726:726:726)) - (PORT datab (1800:1800:1800) (1830:1830:1830)) - (PORT datac (988:988:988) (1048:1048:1048)) - (PORT datad (1210:1210:1210) (1257:1257:1257)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1026:1026:1026) (1084:1084:1084)) - (PORT datab (1248:1248:1248) (1292:1292:1292)) - (PORT datac (1097:1097:1097) (1128:1128:1128)) - (PORT datad (183:183:183) (212:212:212)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) - (DELAY - (ABSOLUTE - (PORT dataa (942:942:942) (983:983:983)) - (PORT datab (1091:1091:1091) (1163:1163:1163)) - (PORT datac (985:985:985) (1050:1050:1050)) - (PORT datad (1157:1157:1157) (1206:1206:1206)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1013:1013:1013) (1086:1086:1086)) - (PORT datab (197:197:197) (234:234:234)) - (PORT datac (1253:1253:1253) (1320:1320:1320)) - (PORT datad (1054:1054:1054) (1123:1123:1123)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) - (DELAY - (ABSOLUTE - (PORT datab (1514:1514:1514) (1650:1650:1650)) - (PORT datac (1504:1504:1504) (1617:1617:1617)) - (PORT datad (1306:1306:1306) (1325:1325:1325)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (831:831:831)) - (PORT datab (860:860:860) (870:870:870)) - (PORT datac (1242:1242:1242) (1262:1262:1262)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1415:1415:1415) (1454:1454:1454)) - (PORT datab (2084:2084:2084) (2114:2114:2114)) - (PORT datac (835:835:835) (859:859:859)) - (PORT datad (788:788:788) (798:798:798)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal48\~0) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (968:968:968)) - (PORT datab (1718:1718:1718) (1807:1807:1807)) - (PORT datac (1144:1144:1144) (1148:1148:1148)) - (PORT datad (654:654:654) (693:693:693)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) - (DELAY - (ABSOLUTE - (PORT dataa (922:922:922) (998:998:998)) - (PORT datab (900:900:900) (985:985:985)) - (PORT datac (966:966:966) (1015:1015:1015)) - (PORT datad (1295:1295:1295) (1365:1365:1365)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (1246:1246:1246) (1336:1336:1336)) - (PORT datab (1005:1005:1005) (1056:1056:1056)) - (PORT datac (209:209:209) (248:248:248)) - (PORT datad (1195:1195:1195) (1244:1244:1244)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1847:1847:1847) (1960:1960:1960)) - (PORT datab (1294:1294:1294) (1397:1397:1397)) - (PORT datac (2030:2030:2030) (2118:2118:2118)) - (PORT datad (836:836:836) (843:843:843)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1215:1215:1215) (1251:1251:1251)) - (PORT datab (1013:1013:1013) (1076:1076:1076)) - (PORT datac (621:621:621) (659:659:659)) - (PORT datad (1176:1176:1176) (1188:1188:1188)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) - (DELAY - (ABSOLUTE - (PORT dataa (886:886:886) (945:945:945)) - (PORT datab (1062:1062:1062) (1128:1128:1128)) - (PORT datac (579:579:579) (602:602:602)) - (PORT datad (1089:1089:1089) (1104:1104:1104)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1618:1618:1618) (1711:1711:1711)) - (PORT datab (1527:1527:1527) (1658:1658:1658)) - (PORT datac (1710:1710:1710) (1825:1825:1825)) - (PORT datad (1448:1448:1448) (1496:1496:1496)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1670:1670:1670) (1753:1753:1753)) - (PORT datab (1528:1528:1528) (1617:1617:1617)) - (PORT datac (966:966:966) (1014:1014:1014)) - (PORT datad (1159:1159:1159) (1218:1218:1218)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (622:622:622)) - (PORT datab (923:923:923) (944:944:944)) - (PORT datac (969:969:969) (1018:1018:1018)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1638:1638:1638) (1764:1764:1764)) - (PORT datab (1075:1075:1075) (1149:1149:1149)) - (PORT datac (1806:1806:1806) (1948:1948:1948)) - (PORT datad (942:942:942) (974:974:974)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1241:1241:1241) (1294:1294:1294)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (972:972:972) (992:992:992)) - (PORT datad (902:902:902) (955:955:955)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1348:1348:1348) (1398:1398:1398)) - (PORT datab (1002:1002:1002) (1057:1057:1057)) - (PORT datac (575:575:575) (596:596:596)) - (PORT datad (637:637:637) (681:681:681)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal20\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1988:1988:1988) (2128:2128:2128)) - (PORT datab (1534:1534:1534) (1632:1632:1632)) - (PORT datac (227:227:227) (272:272:272)) - (PORT datad (1108:1108:1108) (1149:1149:1149)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal68\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1617:1617:1617) (1711:1711:1711)) - (PORT datab (1528:1528:1528) (1657:1657:1657)) - (PORT datac (1709:1709:1709) (1824:1824:1824)) - (PORT datad (1448:1448:1448) (1496:1496:1496)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (922:922:922) (983:983:983)) - (PORT datab (1427:1427:1427) (1510:1510:1510)) - (PORT datac (1333:1333:1333) (1448:1448:1448)) - (PORT datad (1550:1550:1550) (1659:1659:1659)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~13) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (721:721:721)) - (PORT datab (1637:1637:1637) (1642:1642:1642)) - (PORT datac (1298:1298:1298) (1314:1314:1314)) - (PORT datad (1443:1443:1443) (1563:1563:1563)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1580:1580:1580) (1703:1703:1703)) - (PORT datab (1365:1365:1365) (1479:1479:1479)) - (PORT datac (1152:1152:1152) (1186:1186:1186)) - (PORT datad (832:832:832) (834:834:834)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (672:672:672) (729:729:729)) - (PORT datab (995:995:995) (1057:1057:1057)) - (PORT datac (1074:1074:1074) (1196:1196:1196)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~11) - (DELAY - (ABSOLUTE - (PORT dataa (2265:2265:2265) (2414:2414:2414)) - (PORT datab (848:848:848) (886:886:886)) - (PORT datac (2113:2113:2113) (2221:2221:2221)) - (PORT datad (669:669:669) (694:694:694)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (996:996:996)) - (PORT datab (1005:1005:1005) (1060:1060:1060)) - (PORT datac (1413:1413:1413) (1487:1487:1487)) - (PORT datad (1522:1522:1522) (1622:1622:1622)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (684:684:684)) - (PORT datab (440:440:440) (477:477:477)) - (PORT datac (202:202:202) (238:238:238)) - (PORT datad (1428:1428:1428) (1432:1432:1432)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (662:662:662)) - (PORT datab (1001:1001:1001) (1053:1053:1053)) - (PORT datac (870:870:870) (914:914:914)) - (PORT datad (809:809:809) (854:854:854)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (392:392:392)) - (PORT datab (331:331:331) (360:360:360)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (228:228:228) (271:271:271)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (657:657:657)) - (PORT datab (1415:1415:1415) (1491:1491:1491)) - (PORT datac (638:638:638) (658:658:658)) - (PORT datad (1624:1624:1624) (1706:1706:1706)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (702:702:702)) - (PORT datab (995:995:995) (1056:1056:1056)) - (PORT datac (1075:1075:1075) (1194:1194:1194)) - (PORT datad (2306:2306:2306) (2342:2342:2342)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (980:980:980)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (346:346:346) (371:371:371)) - (PORT datad (2307:2307:2307) (2344:2344:2344)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~4) - (DELAY - (ABSOLUTE - (PORT datab (1060:1060:1060) (1178:1178:1178)) - (PORT datac (1452:1452:1452) (1530:1530:1530)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1391:1391:1391) (1453:1453:1453)) - (PORT datab (942:942:942) (993:993:993)) - (PORT datac (1045:1045:1045) (1115:1115:1115)) - (PORT datad (1421:1421:1421) (1470:1470:1470)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (969:969:969) (1009:1009:1009)) - (PORT datab (1445:1445:1445) (1500:1500:1500)) - (PORT datac (972:972:972) (995:995:995)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1123:1123:1123)) - (PORT datab (1196:1196:1196) (1246:1246:1246)) - (PORT datac (663:663:663) (712:712:712)) - (PORT datad (879:879:879) (931:931:931)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (616:616:616)) - (PORT datac (573:573:573) (593:593:593)) - (PORT datad (531:531:531) (543:543:543)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (303:303:303)) - (PORT datab (1244:1244:1244) (1269:1269:1269)) - (PORT datac (1174:1174:1174) (1214:1214:1214)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (925:925:925)) - (PORT datab (852:852:852) (865:865:865)) - (PORT datac (342:342:342) (367:367:367)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1987:1987:1987) (2132:2132:2132)) - (PORT datab (903:903:903) (955:955:955)) - (PORT datac (224:224:224) (269:269:269)) - (PORT datad (1402:1402:1402) (1466:1466:1466)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) - (DELAY - (ABSOLUTE - (PORT dataa (1798:1798:1798) (1933:1933:1933)) - (PORT datab (1613:1613:1613) (1726:1726:1726)) - (PORT datad (1409:1409:1409) (1475:1475:1475)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) - (DELAY - (ABSOLUTE - (PORT dataa (2050:2050:2050) (2089:2089:2089)) - (PORT datab (946:946:946) (1023:1023:1023)) - (PORT datac (1099:1099:1099) (1158:1158:1158)) - (PORT datad (914:914:914) (1002:1002:1002)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1335:1335:1335) (1354:1354:1354)) - (PORT datab (1166:1166:1166) (1239:1239:1239)) - (PORT datac (1485:1485:1485) (1514:1514:1514)) - (PORT datad (1468:1468:1468) (1520:1520:1520)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (1144:1144:1144) (1189:1189:1189)) - (PORT datab (222:222:222) (269:269:269)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (836:836:836) (868:868:868)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT datab (963:963:963) (1010:1010:1010)) - (PORT datac (601:601:601) (607:607:607)) - (PORT datad (676:676:676) (718:718:718)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) - (DELAY - (ABSOLUTE - (PORT datac (928:928:928) (973:973:973)) - (PORT datad (680:680:680) (720:720:720)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) - (DELAY - (ABSOLUTE - (PORT dataa (1003:1003:1003) (1064:1064:1064)) - (PORT datab (717:717:717) (774:774:774)) - (PORT datac (903:903:903) (944:944:944)) - (PORT datad (1740:1740:1740) (1858:1858:1858)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1494:1494:1494) (1600:1600:1600)) - (PORT datab (1475:1475:1475) (1582:1582:1582)) - (PORT datac (1847:1847:1847) (1916:1916:1916)) - (PORT datad (402:402:402) (439:439:439)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1219:1219:1219) (1306:1306:1306)) - (PORT datac (943:943:943) (1021:1021:1021)) - (PORT datad (1208:1208:1208) (1293:1293:1293)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1221:1221:1221) (1285:1285:1285)) - (PORT datab (1430:1430:1430) (1456:1456:1456)) - (PORT datac (1096:1096:1096) (1116:1116:1116)) - (PORT datad (1325:1325:1325) (1332:1332:1332)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) - (DELAY - (ABSOLUTE - (PORT datab (934:934:934) (968:968:968)) - (PORT datac (531:531:531) (544:544:544)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1001:1001:1001) (1063:1063:1063)) - (PORT datab (717:717:717) (773:773:773)) - (PORT datac (901:901:901) (942:942:942)) - (PORT datad (1738:1738:1738) (1857:1857:1857)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1357:1357:1357) (1397:1397:1397)) - (PORT datab (917:917:917) (962:962:962)) - (PORT datad (619:619:619) (654:654:654)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (864:864:864) (915:915:915)) - (PORT datab (1463:1463:1463) (1548:1548:1548)) - (PORT datac (1313:1313:1313) (1405:1405:1405)) - (PORT datad (2215:2215:2215) (2336:2336:2336)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~36) - (DELAY - (ABSOLUTE - (PORT dataa (2340:2340:2340) (2463:2463:2463)) - (PORT datab (901:901:901) (951:951:951)) - (PORT datac (370:370:370) (398:398:398)) - (PORT datad (1461:1461:1461) (1558:1558:1558)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (258:258:258)) - (PORT datab (239:239:239) (284:284:284)) - (PORT datac (839:839:839) (874:874:874)) - (PORT datad (554:554:554) (572:572:572)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~5) - (DELAY - (ABSOLUTE - (PORT datac (2441:2441:2441) (2623:2623:2623)) - (PORT datad (1996:1996:1996) (2085:2085:2085)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1464:1464:1464) (1521:1521:1521)) - (PORT datab (843:843:843) (881:881:881)) - (PORT datac (916:916:916) (966:966:966)) - (PORT datad (669:669:669) (689:689:689)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1438:1438:1438) (1467:1467:1467)) - (PORT datab (1349:1349:1349) (1381:1381:1381)) - (PORT datac (855:855:855) (867:867:867)) - (PORT datad (805:805:805) (815:815:815)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1088:1088:1088) (1119:1119:1119)) - (PORT datab (2571:2571:2571) (2668:2668:2668)) - (PORT datac (1529:1529:1529) (1666:1666:1666)) - (PORT datad (1710:1710:1710) (1831:1831:1831)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) - (DELAY - (ABSOLUTE - (PORT datac (207:207:207) (248:248:248)) - (PORT datad (209:209:209) (239:239:239)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1221:1221:1221) (1290:1290:1290)) - (PORT datab (1275:1275:1275) (1382:1382:1382)) - (PORT datac (1752:1752:1752) (1793:1793:1793)) - (PORT datad (851:851:851) (865:865:865)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) - (DELAY - (ABSOLUTE - (PORT dataa (401:401:401) (427:427:427)) - (PORT datab (401:401:401) (428:428:428)) - (PORT datac (370:370:370) (396:396:396)) - (PORT datad (207:207:207) (244:244:244)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1486:1486:1486) (1538:1538:1538)) - (PORT datab (1265:1265:1265) (1379:1379:1379)) - (PORT datac (900:900:900) (922:922:922)) - (PORT datad (1168:1168:1168) (1190:1190:1190)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) - (DELAY - (ABSOLUTE - (PORT dataa (708:708:708) (754:754:754)) - (PORT datab (2783:2783:2783) (2910:2910:2910)) - (PORT datac (1297:1297:1297) (1413:1413:1413)) - (PORT datad (574:574:574) (587:587:587)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low) - (DELAY - (ABSOLUTE - (PORT dataa (886:886:886) (898:898:898)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datac (196:196:196) (240:240:240)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE 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z80_\|execute_\|ctl_alu_shift_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1639:1639:1639) (1766:1766:1766)) - (PORT datab (1825:1825:1825) (1925:1925:1925)) - (PORT datac (1804:1804:1804) (1951:1951:1951)) - (PORT datad (941:941:941) (965:965:965)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1437:1437:1437) (1451:1451:1451)) - (PORT datab (1439:1439:1439) (1497:1497:1497)) - (PORT datac (974:974:974) (995:995:995)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - 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(242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1463:1463:1463) (1478:1478:1478)) - (PORT datab (1379:1379:1379) (1398:1398:1398)) - (PORT datac (1618:1618:1618) (1662:1662:1662)) - (PORT datad (1263:1263:1263) (1327:1327:1327)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1202:1202:1202) (1231:1231:1231)) - (PORT datab (1048:1048:1048) (1149:1149:1149)) - (PORT datad (1348:1348:1348) (1490:1490:1490)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (681:681:681) (736:736:736)) - (PORT datab (1001:1001:1001) (1033:1033:1033)) - (PORT datac (553:553:553) (568:568:568)) - (PORT datad (222:222:222) (249:249:249)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (737:737:737) (798:798:798)) - (PORT datab (948:948:948) (1025:1025:1025)) - (PORT datac (1099:1099:1099) (1159:1159:1159)) - (PORT datad (909:909:909) (998:998:998)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1225:1225:1225) (1294:1294:1294)) - (PORT datab (224:224:224) (271:271:271)) - (PORT datac (2351:2351:2351) (2449:2449:2449)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal8\~0) - (DELAY - (ABSOLUTE - (PORT datab (2076:2076:2076) (2143:2143:2143)) - (PORT datac (1719:1719:1719) (1796:1796:1796)) - (PORT datad (1155:1155:1155) (1236:1236:1236)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1450:1450:1450) (1501:1501:1501)) - (PORT datab (1425:1425:1425) (1462:1462:1462)) - (PORT datac (836:836:836) (865:865:865)) - (PORT datad (394:394:394) (429:429:429)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (894:894:894)) - (PORT datab (1197:1197:1197) (1223:1223:1223)) - (PORT datac (981:981:981) (1043:1043:1043)) - (PORT datad (972:972:972) (1036:1036:1036)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (2006:2006:2006) (2147:2147:2147)) - (PORT datab (450:450:450) (480:480:480)) - (PORT datac (1000:1000:1000) (1045:1045:1045)) - (PORT datad (900:900:900) (950:950:950)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~1) - (DELAY - (ABSOLUTE - (PORT datac (1589:1589:1589) (1676:1676:1676)) - (PORT datad (1494:1494:1494) (1621:1621:1621)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) - (DELAY - (ABSOLUTE - (PORT dataa (959:959:959) (1016:1016:1016)) - (PORT datab (1194:1194:1194) (1223:1223:1223)) - (PORT datac (1942:1942:1942) (2000:2000:2000)) - (PORT datad (641:641:641) (693:693:693)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (627:627:627) (662:662:662)) - (PORT datac (1683:1683:1683) (1789:1789:1789)) - (PORT datad (633:633:633) (651:651:651)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1500:1500:1500) (1575:1575:1575)) - (PORT datab (362:362:362) (397:397:397)) - (PORT datac (2091:2091:2091) (2220:2220:2220)) - (PORT datad (590:590:590) (607:607:607)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (736:736:736) (800:800:800)) - (PORT datab (947:947:947) (1025:1025:1025)) - (PORT datac (1098:1098:1098) (1158:1158:1158)) - (PORT datad (911:911:911) (1001:1001:1001)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) - (DELAY - (ABSOLUTE - (PORT dataa (1465:1465:1465) (1539:1539:1539)) - (PORT datab (1227:1227:1227) (1318:1318:1318)) - (PORT datac (1459:1459:1459) (1517:1517:1517)) - (PORT datad (1138:1138:1138) (1159:1159:1159)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1840:1840:1840) (1939:1939:1939)) - (PORT datab (2068:2068:2068) (2187:2187:2187)) - (PORT datac (1327:1327:1327) (1336:1336:1336)) - (PORT datad (2013:2013:2013) (2125:2125:2125)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1215:1215:1215)) - (PORT datab (653:653:653) (674:674:674)) - (PORT datac (1214:1214:1214) (1294:1294:1294)) - (PORT datad (596:596:596) (619:619:619)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1170:1170:1170)) - (PORT datab (841:841:841) (864:864:864)) - (PORT datad (579:579:579) (590:590:590)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) - (DELAY - (ABSOLUTE - (PORT datac (1753:1753:1753) (1873:1873:1873)) - (PORT datad (1571:1571:1571) (1694:1694:1694)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1025:1025:1025) (1056:1056:1056)) - (PORT datab (1039:1039:1039) (1096:1096:1096)) - (PORT datac (1052:1052:1052) (1117:1117:1117)) - (PORT datad (625:625:625) (651:651:651)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1581:1581:1581) (1726:1726:1726)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (1053:1053:1053) (1117:1117:1117)) - (PORT datad (1795:1795:1795) (1930:1930:1930)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1219:1219:1219) (1272:1272:1272)) - (PORT datab (689:689:689) (706:706:706)) - (PORT datac (1267:1267:1267) (1395:1395:1395)) - (PORT datad (1570:1570:1570) (1720:1720:1720)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (1265:1265:1265) (1395:1395:1395)) - (PORT datad (1573:1573:1573) (1723:1723:1723)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1230:1230:1230) (1277:1277:1277)) - (PORT datab (1647:1647:1647) (1673:1673:1673)) - (PORT datac (777:777:777) (786:786:786)) - (PORT datad (581:581:581) (600:600:600)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (652:652:652)) - (PORT datab (656:656:656) (711:711:711)) - (PORT datac (680:680:680) (730:730:730)) - (PORT datad (800:800:800) (871:871:871)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1001:1001:1001) (1087:1087:1087)) - (PORT datab (1683:1683:1683) (1741:1741:1741)) - (PORT datac (1582:1582:1582) (1690:1690:1690)) - (PORT datad (964:964:964) (1004:1004:1004)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1288:1288:1288) (1342:1342:1342)) - (PORT datab (935:935:935) (949:949:949)) - (PORT datac (978:978:978) (1043:1043:1043)) - (PORT datad (1176:1176:1176) (1188:1188:1188)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (390:390:390)) - (PORT datab (1476:1476:1476) (1506:1506:1506)) - (PORT datac (1080:1080:1080) (1084:1084:1084)) - (PORT datad (1360:1360:1360) (1375:1375:1375)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (392:392:392)) - (PORT datab (238:238:238) (276:276:276)) - (PORT datac (1044:1044:1044) (1080:1080:1080)) - (PORT datad (1386:1386:1386) (1428:1428:1428)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (869:869:869) (907:907:907)) - (PORT datab (364:364:364) (400:400:400)) - (PORT datac (656:656:656) (701:701:701)) - (PORT datad (837:837:837) (878:878:878)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (810:810:810)) - (PORT datab (933:933:933) (988:988:988)) - (PORT datac (981:981:981) (1058:1058:1058)) - (PORT datad (194:194:194) (218:218:218)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1441:1441:1441) (1552:1552:1552)) - (PORT datab (614:614:614) (644:644:644)) - (PORT datac (1197:1197:1197) (1258:1258:1258)) - (PORT datad (844:844:844) (855:855:855)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (275:275:275)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (588:588:588) (608:608:608)) - (PORT datad (876:876:876) (896:896:896)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1212:1212:1212) (1250:1250:1250)) - (PORT datab (965:965:965) (1013:1013:1013)) - (PORT datac (1049:1049:1049) (1111:1111:1111)) - (PORT datad (1444:1444:1444) (1477:1477:1477)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1082:1082:1082) (1153:1153:1153)) - (PORT datab (970:970:970) (1019:1019:1019)) - (PORT datac (308:308:308) (334:334:334)) - (PORT datad (628:628:628) (654:654:654)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1024:1024:1024) (1085:1085:1085)) - (PORT datab (1386:1386:1386) (1414:1414:1414)) - (PORT datac (1180:1180:1180) (1211:1211:1211)) - (PORT datad (1209:1209:1209) (1252:1252:1252)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (1246:1246:1246) (1296:1296:1296)) - (PORT datac (984:984:984) (1048:1048:1048)) - (PORT datad (625:625:625) (654:654:654)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (910:910:910)) - (PORT datab (1428:1428:1428) (1466:1466:1466)) - (PORT datac (1688:1688:1688) (1726:1726:1726)) - (PORT datad (2057:2057:2057) (2190:2190:2190)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (642:642:642)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (1398:1398:1398) (1422:1422:1422)) - (PORT datad (1424:1424:1424) (1462:1462:1462)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1803:1803:1803) (1945:1945:1945)) - (PORT datab (847:847:847) (858:858:858)) - (PORT datac (838:838:838) (869:869:869)) - (PORT datad (2056:2056:2056) (2191:2191:2191)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (847:847:847)) - (PORT datab (783:783:783) (809:809:809)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (382:382:382)) - (PORT datab (220:220:220) (258:258:258)) - (PORT datac (193:193:193) (227:227:227)) - (PORT datad (539:539:539) (561:561:561)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (952:952:952) (1004:1004:1004)) - (PORT datab (876:876:876) (893:893:893)) - (PORT datac (1689:1689:1689) (1781:1781:1781)) - (PORT datad (1175:1175:1175) (1232:1232:1232)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1346:1346:1346) (1340:1340:1340)) - (PORT datab (1176:1176:1176) (1219:1219:1219)) - (PORT datac (1123:1123:1123) (1137:1137:1137)) - (PORT datad (665:665:665) (719:719:719)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1197:1197:1197) (1247:1247:1247)) - (PORT datac (582:582:582) (614:614:614)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1190:1190:1190) (1242:1242:1242)) - (PORT datab (650:650:650) (679:679:679)) - (PORT datac (191:191:191) (237:237:237)) - (PORT datad (607:607:607) (635:635:635)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (274:274:274)) - (PORT datac (2094:2094:2094) (2219:2219:2219)) - (PORT datad (1462:1462:1462) (1527:1527:1527)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (461:461:461)) - (PORT datab (1161:1161:1161) (1190:1190:1190)) - (PORT datac (1460:1460:1460) (1518:1518:1518)) - (PORT datad (1106:1106:1106) (1136:1136:1136)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1080:1080:1080) (1147:1147:1147)) - (PORT datab (1037:1037:1037) (1105:1105:1105)) - (PORT datac (1180:1180:1180) (1210:1210:1210)) - (PORT datad (1210:1210:1210) (1252:1252:1252)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (919:919:919)) - (PORT datab (661:661:661) (705:705:705)) - (PORT datac (1104:1104:1104) (1117:1117:1117)) - (PORT datad (766:766:766) (786:786:786)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1156:1156:1156)) - (PORT datab (1528:1528:1528) (1657:1657:1657)) - (PORT datac (609:609:609) (665:665:665)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (734:734:734) (762:762:762)) - (PORT datab (849:849:849) (885:885:885)) - (PORT datac (787:787:787) (804:804:804)) - (PORT datad (670:670:670) (694:694:694)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1025:1025:1025) (1084:1084:1084)) - (PORT datab (969:969:969) (1019:1019:1019)) - (PORT datac (192:192:192) (223:223:223)) - (PORT datad (1444:1444:1444) (1475:1475:1475)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1298:1298:1298) (1390:1390:1390)) - (PORT datab (968:968:968) (1017:1017:1017)) - (PORT datac (1050:1050:1050) (1110:1110:1110)) - (PORT datad (1553:1553:1553) (1682:1682:1682)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1298:1298:1298) (1391:1391:1391)) - (PORT datab (1247:1247:1247) (1291:1291:1291)) - (PORT datac (985:985:985) (1043:1043:1043)) - (PORT datad (1553:1553:1553) (1682:1682:1682)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (564:564:564) (579:579:579)) - (PORT datab (244:244:244) (288:288:288)) - (PORT datac (543:543:543) (551:551:551)) - (PORT datad (1454:1454:1454) (1511:1511:1511)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (1400:1400:1400) (1422:1422:1422)) - (PORT datac (572:572:572) (596:596:596)) - (PORT datad (602:602:602) (630:630:630)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (681:681:681) (737:737:737)) - (PORT datab (1115:1115:1115) (1164:1164:1164)) - (PORT datac (969:969:969) (1001:1001:1001)) - (PORT datad (1160:1160:1160) (1223:1223:1223)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (984:984:984)) - (PORT datab (941:941:941) (1009:1009:1009)) - (PORT datac (1210:1210:1210) (1289:1289:1289)) - (PORT datad (381:381:381) (406:406:406)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1765:1765:1765) (1808:1808:1808)) - (PORT datab (1620:1620:1620) (1658:1658:1658)) - (PORT datac (1305:1305:1305) (1421:1421:1421)) - (PORT datad (1541:1541:1541) (1677:1677:1677)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1103:1103:1103) (1119:1119:1119)) - (PORT datab (1046:1046:1046) (1094:1094:1094)) - (PORT datac (952:952:952) (984:984:984)) - (PORT datad (819:819:819) (844:844:844)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (982:982:982) (1023:1023:1023)) - (PORT datab (700:700:700) (721:721:721)) - (PORT datac (216:216:216) (260:260:260)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (874:874:874)) - (PORT datab (648:648:648) (669:669:669)) - (PORT datac (877:877:877) (899:899:899)) - (PORT datad (813:813:813) (834:834:834)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (363:363:363) (397:397:397)) - (PORT datac (964:964:964) (1033:1033:1033)) - (PORT datad (590:590:590) (607:607:607)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datac (1711:1711:1711) (1773:1773:1773)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (296:296:296)) - (PORT datab (1200:1200:1200) (1240:1240:1240)) - (PORT datac (1213:1213:1213) (1232:1232:1232)) - (PORT datad (559:559:559) (571:571:571)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1102:1102:1102) (1121:1121:1121)) - (PORT datab (246:246:246) (294:294:294)) - (PORT datac (901:901:901) (943:943:943)) - (PORT datad (1975:1975:1975) (2012:2012:2012)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (823:823:823) (840:840:840)) - (PORT datab (850:850:850) (877:877:877)) - (PORT datac (595:595:595) (617:617:617)) - (PORT datad (811:811:811) (824:824:824)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (2154:2154:2154) (2304:2304:2304)) - (PORT datab (1756:1756:1756) (1875:1875:1875)) - (PORT datac (868:868:868) (905:905:905)) - (PORT datad (2343:2343:2343) (2450:2450:2450)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (963:963:963) (1025:1025:1025)) - (PORT datab (2108:2108:2108) (2222:2222:2222)) - (PORT datac (548:548:548) (573:573:573)) - (PORT datad (1982:1982:1982) (2069:2069:2069)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~54) - (DELAY - (ABSOLUTE - (PORT dataa (1779:1779:1779) (1888:1888:1888)) - (PORT datab (1077:1077:1077) (1152:1152:1152)) - (PORT datac (971:971:971) (991:991:991)) - (PORT datad (2049:2049:2049) (2156:2156:2156)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1244:1244:1244)) - (PORT datab (1192:1192:1192) (1241:1241:1241)) - (PORT datac (610:610:610) (626:626:626)) - (PORT datad (2306:2306:2306) (2345:2345:2345)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (998:998:998) (1033:1033:1033)) - (PORT datab (1150:1150:1150) (1177:1177:1177)) - (PORT datac (346:346:346) (385:385:385)) - (PORT datad (630:630:630) (669:669:669)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (890:890:890)) - (PORT datac (839:839:839) (858:858:858)) - (PORT datad (520:520:520) (531:531:531)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (288:288:288)) - (PORT datab (250:250:250) (300:300:300)) - (PORT datac (1960:1960:1960) (2089:2089:2089)) - (PORT datad (202:202:202) (238:238:238)) - (IOPATH dataa combout (303:303:303) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1352:1352:1352) (1478:1478:1478)) - (PORT datab (1346:1346:1346) (1363:1363:1363)) - (PORT datac (870:870:870) (896:896:896)) - (PORT datad (1449:1449:1449) (1511:1511:1511)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1104:1104:1104) (1189:1189:1189)) - (PORT datab (685:685:685) (754:754:754)) - (PORT datac (958:958:958) (1039:1039:1039)) - (PORT datad (613:613:613) (629:629:629)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (664:664:664)) - (PORT datab (973:973:973) (1069:1069:1069)) - (PORT datac (1733:1733:1733) (1832:1832:1832)) - (PORT datad (1149:1149:1149) (1173:1173:1173)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1999:1999:1999) (2036:2036:2036)) - (PORT datab (872:872:872) (899:899:899)) - (PORT datac (1356:1356:1356) (1432:1432:1432)) - (PORT datad (1348:1348:1348) (1396:1396:1396)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (650:650:650)) - (PORT datab (1061:1061:1061) (1123:1123:1123)) - (PORT datac (208:208:208) (247:247:247)) - (PORT datad (864:864:864) (923:923:923)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (632:632:632)) - (PORT datab (203:203:203) (245:245:245)) - (PORT datac (877:877:877) (914:914:914)) - (PORT datad (853:853:853) (874:874:874)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1749:1749:1749) (1769:1769:1769)) - (PORT datab (1064:1064:1064) (1181:1181:1181)) - (PORT datac (1204:1204:1204) (1273:1273:1273)) - (PORT datad (860:860:860) (875:875:875)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (686:686:686) (719:719:719)) - (PORT datab (1166:1166:1166) (1236:1236:1236)) - (PORT datac (1485:1485:1485) (1511:1511:1511)) - (PORT datad (1469:1469:1469) (1516:1516:1516)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (880:880:880)) - (PORT datab (1385:1385:1385) (1395:1395:1395)) - (PORT datac (777:777:777) (796:796:796)) - (PORT datad (1739:1739:1739) (1779:1779:1779)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel3) - (DELAY - (ABSOLUTE - (PORT dataa (1404:1404:1404) (1480:1480:1480)) - (PORT datab (2358:2358:2358) (2492:2492:2492)) - (PORT datac (1133:1133:1133) (1174:1174:1174)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (966:966:966) (1016:1016:1016)) - (PORT datab (1031:1031:1031) (1053:1053:1053)) - (PORT datac (181:181:181) (219:219:219)) - (PORT datad (652:652:652) (692:692:692)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (616:616:616)) - (PORT datab (672:672:672) (701:701:701)) - (PORT datac (510:510:510) (522:522:522)) - (PORT datad (840:840:840) (853:853:853)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (256:256:256)) - (PORT datab (884:884:884) (911:911:911)) - (PORT datac (866:866:866) (930:930:930)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel0) - (DELAY - (ABSOLUTE - (PORT dataa (2169:2169:2169) (2322:2322:2322)) - (PORT datac (1461:1461:1461) (1534:1534:1534)) - (PORT datad (2260:2260:2260) (2326:2326:2326)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) - (DELAY - (ABSOLUTE - (PORT datab (924:924:924) (1011:1011:1011)) - (PORT datac (1545:1545:1545) (1672:1672:1672)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (705:705:705) (747:747:747)) - (PORT datab (868:868:868) (890:890:890)) - (PORT datac (1285:1285:1285) (1378:1378:1378)) - (PORT datad (896:896:896) (936:936:936)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1484:1484:1484) (1547:1547:1547)) - (PORT datab (205:205:205) (245:245:245)) - (PORT datac (988:988:988) (1034:1034:1034)) - (PORT datad (1031:1031:1031) (1081:1081:1081)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (236:236:236) (286:286:286)) - (PORT datab (373:373:373) (398:398:398)) - (PORT datac (599:599:599) (641:641:641)) - (PORT datad (200:200:200) (235:235:235)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1623:1623:1623) (1713:1713:1713)) - (PORT datab (1529:1529:1529) (1662:1662:1662)) - (PORT datac (1705:1705:1705) (1826:1826:1826)) - (PORT datad (1447:1447:1447) (1495:1495:1495)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1779:1779:1779) (1826:1826:1826)) - (PORT datab (681:681:681) (732:732:732)) - (PORT datac (551:551:551) (571:571:571)) - (PORT datad (1134:1134:1134) (1177:1177:1177)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (688:688:688) (759:759:759)) - (PORT datab (1001:1001:1001) (1109:1109:1109)) - (PORT datac (192:192:192) (226:226:226)) - (PORT datad (1242:1242:1242) (1328:1328:1328)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (598:598:598) (630:630:630)) - (PORT datab (875:875:875) (920:920:920)) - (PORT datac (338:338:338) (364:364:364)) - (PORT datad (685:685:685) (739:739:739)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (707:707:707)) - (PORT datab (950:950:950) (1008:1008:1008)) - (PORT datac (590:590:590) (605:605:605)) - (PORT datad (654:654:654) (692:692:692)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1138:1138:1138) (1171:1171:1171)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (566:566:566) (595:595:595)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (494:494:494)) - (PORT datab (1299:1299:1299) (1396:1396:1396)) - (PORT datac (680:680:680) (764:764:764)) - (PORT datad (1300:1300:1300) (1391:1391:1391)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1581:1581:1581) (1626:1626:1626)) - (PORT datab (906:906:906) (950:950:950)) - (PORT datac (1263:1263:1263) (1320:1320:1320)) - (PORT datad (1666:1666:1666) (1688:1688:1688)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (401:401:401)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (653:653:653) (714:714:714)) - (PORT datad (1668:1668:1668) (1689:1689:1689)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1304:1304:1304) (1373:1373:1373)) - (PORT datab (1184:1184:1184) (1235:1235:1235)) - (PORT datac (1139:1139:1139) (1197:1197:1197)) - (PORT datad (1323:1323:1323) (1433:1433:1433)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) - (DELAY - (ABSOLUTE - (PORT dataa (908:908:908) (940:940:940)) - (PORT datab (380:380:380) (410:410:410)) - (PORT datac (654:654:654) (698:698:698)) - (PORT datad (1204:1204:1204) (1277:1277:1277)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1116:1116:1116)) - (PORT datab (917:917:917) (963:963:963)) - (PORT datac (1010:1010:1010) (1060:1060:1060)) - (PORT datad (924:924:924) (954:954:954)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (251:251:251)) - (PORT datab (964:964:964) (1061:1061:1061)) - (PORT datac (844:844:844) (886:886:886)) - (PORT datad (905:905:905) (950:950:950)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) - (DELAY - (ABSOLUTE - (PORT dataa (998:998:998) (1084:1084:1084)) - (PORT datab (1205:1205:1205) (1272:1272:1272)) - (PORT datac (1579:1579:1579) (1687:1687:1687)) - (PORT datad (1138:1138:1138) (1195:1195:1195)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (653:653:653)) - (PORT datab (2073:2073:2073) (2252:2252:2252)) - (PORT datac (861:861:861) (894:894:894)) - (PORT datad (1257:1257:1257) (1349:1349:1349)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (961:961:961)) - (PORT datab (916:916:916) (955:955:955)) - (PORT datac (1131:1131:1131) (1156:1156:1156)) - (PORT datad (926:926:926) (955:955:955)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~92) - (DELAY - (ABSOLUTE - (PORT dataa (1028:1028:1028) (1147:1147:1147)) - (PORT datab (1588:1588:1588) (1723:1723:1723)) - (PORT datac (637:637:637) (656:656:656)) - (PORT datad (1691:1691:1691) (1790:1790:1790)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2337:2337:2337) (2490:2490:2490)) - (PORT datab (1668:1668:1668) (1785:1785:1785)) - (PORT datac (905:905:905) (956:956:956)) - (PORT datad (672:672:672) (720:720:720)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1009:1009:1009) (1130:1130:1130)) - (PORT datad (1542:1542:1542) (1657:1657:1657)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1306:1306:1306) (1373:1373:1373)) - (PORT datab (656:656:656) (703:703:703)) - (PORT datac (1351:1351:1351) (1409:1409:1409)) - (PORT datad (881:881:881) (908:908:908)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~93) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1148:1148:1148)) - (PORT datab (1720:1720:1720) (1825:1825:1825)) - (PORT datac (1557:1557:1557) (1685:1685:1685)) - (PORT datad (1001:1001:1001) (1102:1102:1102)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1356:1356:1356) (1478:1478:1478)) - (PORT datab (827:827:827) (854:854:854)) - (PORT datac (1113:1113:1113) (1149:1149:1149)) - (PORT datad (635:635:635) (687:687:687)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~24) - (DELAY - (ABSOLUTE - (PORT datab (1169:1169:1169) (1230:1230:1230)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (183:183:183) (212:212:212)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (851:851:851) (919:919:919)) - (PORT datac (194:194:194) (241:241:241)) - (PORT datad (673:673:673) (732:732:732)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) - (DELAY - (ABSOLUTE - (PORT dataa (968:968:968) (1052:1052:1052)) - (PORT datab (936:936:936) (1006:1006:1006)) - (PORT datac (1407:1407:1407) (1449:1449:1449)) - (PORT datad (537:537:537) (548:548:548)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (620:620:620)) - (PORT datab (867:867:867) (902:902:902)) - (PORT datac (1366:1366:1366) (1470:1470:1470)) - (PORT datad (1496:1496:1496) (1606:1606:1606)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (951:951:951) (985:985:985)) - (PORT datab (916:916:916) (957:957:957)) - (PORT datac (915:915:915) (950:950:950)) - (PORT datad (1540:1540:1540) (1625:1625:1625)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1174:1174:1174) (1214:1214:1214)) - (PORT datab (649:649:649) (694:694:694)) - (PORT datac (902:902:902) (950:950:950)) - (PORT datad (338:338:338) (355:355:355)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) - (DELAY - (ABSOLUTE - (PORT datab (1511:1511:1511) (1618:1618:1618)) - (PORT datac (1726:1726:1726) (1837:1837:1837)) - (PORT datad (1072:1072:1072) (1082:1082:1082)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (734:734:734)) - (PORT datab (1163:1163:1163) (1210:1210:1210)) - (PORT datac (852:852:852) (881:881:881)) - (PORT datad (1173:1173:1173) (1254:1254:1254)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (966:966:966) (1001:1001:1001)) - (PORT datab (946:946:946) (986:986:986)) - (PORT datac (632:632:632) (678:678:678)) - (PORT datad (1150:1150:1150) (1195:1195:1195)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) - (DELAY - (ABSOLUTE - (PORT datab (865:865:865) (918:918:918)) - (PORT datac (179:179:179) (213:213:213)) - (PORT datad (851:851:851) (896:896:896)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1052:1052:1052) (1077:1077:1077)) - (PORT datab (1450:1450:1450) (1521:1521:1521)) - (PORT datac (1291:1291:1291) (1321:1321:1321)) - (PORT datad (856:856:856) (875:875:875)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1685:1685:1685) (1750:1750:1750)) - (PORT datab (1695:1695:1695) (1779:1779:1779)) - (PORT datac (1479:1479:1479) (1576:1576:1576)) - (PORT datad (855:855:855) (874:874:874)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (1444:1444:1444) (1505:1505:1505)) - (PORT datab (1695:1695:1695) (1774:1774:1774)) - (PORT datac (1653:1653:1653) (1704:1704:1704)) - (PORT datad (1165:1165:1165) (1208:1208:1208)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) - (DELAY - (ABSOLUTE - (PORT dataa (829:829:829) (902:902:902)) - (PORT datab (612:612:612) (626:626:626)) - (PORT datac (1486:1486:1486) (1525:1525:1525)) - (PORT datad (572:572:572) (587:587:587)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (953:953:953)) - (PORT datab (920:920:920) (939:939:939)) - (PORT datac (888:888:888) (933:933:933)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~94) - (DELAY - (ABSOLUTE - (PORT dataa (1805:1805:1805) (1846:1846:1846)) - (PORT datab (1718:1718:1718) (1824:1824:1824)) - (PORT datac (1560:1560:1560) (1684:1684:1684)) - (PORT datad (1003:1003:1003) (1103:1103:1103)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) - (DELAY - (ABSOLUTE - (PORT dataa (1617:1617:1617) (1736:1736:1736)) - (PORT datac (2516:2516:2516) (2621:2621:2621)) - (PORT datad (1496:1496:1496) (1610:1610:1610)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1204:1204:1204)) - (PORT datab (1153:1153:1153) (1208:1208:1208)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (861:861:861) (880:880:880)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT datab (684:684:684) (709:709:709)) - (PORT datac (378:378:378) (413:413:413)) - (PORT datad (203:203:203) (232:232:232)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) - (DELAY - (ABSOLUTE - (PORT dataa (454:454:454) (494:494:494)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (807:807:807) (827:827:827)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (413:413:413)) - (PORT datab (907:907:907) (914:914:914)) - (PORT datac (619:619:619) (656:656:656)) - (PORT datad (1190:1190:1190) (1243:1243:1243)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1250:1250:1250) (1344:1344:1344)) - (PORT datab (1673:1673:1673) (1790:1790:1790)) - (PORT datac (909:909:909) (958:958:958)) - (PORT datad (940:940:940) (995:995:995)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1458:1458:1458) (1556:1556:1556)) - (PORT datab (1664:1664:1664) (1735:1735:1735)) - (PORT datac (847:847:847) (861:861:861)) - (PORT datad (654:654:654) (683:683:683)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_exx\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1407:1407:1407) (1552:1552:1552)) - (PORT datab (901:901:901) (929:929:929)) - (PORT datad (2354:2354:2354) (2501:2501:2501)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_exx) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1532:1532:1532)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1555:1555:1555)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1165:1165:1165) (1200:1200:1200)) - (PORT datab (1193:1193:1193) (1243:1243:1243)) - (PORT datad (1206:1206:1206) (1288:1288:1288)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de1) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1593:1593:1593) (1569:1569:1569)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (961:961:961)) - (PORT datab (2051:2051:2051) (2083:2083:2083)) - (PORT datac (805:805:805) (817:817:817)) - (PORT datad (336:336:336) (360:360:360)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (965:965:965) (998:998:998)) - (PORT datab (1733:1733:1733) (1770:1770:1770)) - (PORT datac (1229:1229:1229) (1327:1327:1327)) - (PORT datad (1151:1151:1151) (1194:1194:1194)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (766:766:766) (785:785:785)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1230:1230:1230) (1329:1329:1329)) - (PORT datad (1542:1542:1542) (1627:1627:1627)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1235:1235:1235) (1298:1298:1298)) - (PORT datab (1276:1276:1276) (1367:1367:1367)) - (PORT datac (1156:1156:1156) (1195:1195:1195)) - (PORT datad (711:711:711) (777:777:777)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (656:656:656)) - (PORT datab (603:603:603) (615:615:615)) - (PORT datac (902:902:902) (950:950:950)) - (PORT datad (1750:1750:1750) (1806:1806:1806)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (937:937:937) (985:985:985)) - (PORT datab (359:359:359) (388:388:388)) - (PORT datac (1182:1182:1182) (1242:1242:1242)) - (PORT datad (2028:2028:2028) (2153:2153:2153)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (372:372:372)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (878:878:878) (913:913:913)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1069:1069:1069)) - (PORT datab (913:913:913) (1002:1002:1002)) - (PORT datac (1084:1084:1084) (1074:1074:1074)) - (PORT datad (1060:1060:1060) (1062:1062:1062)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1344:1344:1344) (1441:1441:1441)) - (PORT datab (898:898:898) (946:946:946)) - (PORT datac (669:669:669) (692:692:692)) - (PORT datad (1162:1162:1162) (1228:1228:1228)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) - (DELAY - (ABSOLUTE - (PORT dataa (2046:2046:2046) (2143:2143:2143)) - (PORT datac (1652:1652:1652) (1690:1690:1690)) - (PORT datad (1726:1726:1726) (1766:1766:1766)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~2) - (DELAY - (ABSOLUTE - (PORT dataa (985:985:985) (1068:1068:1068)) - (PORT datab (1320:1320:1320) (1358:1358:1358)) - (PORT datac (1320:1320:1320) (1375:1375:1375)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~19) - (DELAY - (ABSOLUTE - (PORT datab (667:667:667) (677:677:677)) - (PORT datac (650:650:650) (674:674:674)) - (PORT datad (899:899:899) (937:937:937)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (691:691:691)) - (PORT datab (711:711:711) (745:745:745)) - (PORT datac (675:675:675) (730:730:730)) - (PORT datad (832:832:832) (843:843:843)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (889:889:889)) - (PORT datac (1915:1915:1915) (1982:1982:1982)) - (PORT datad (200:200:200) (239:239:239)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (677:677:677)) - (PORT datab (864:864:864) (932:932:932)) - (PORT datac (1099:1099:1099) (1123:1123:1123)) - (PORT datad (830:830:830) (852:852:852)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1058:1058:1058) (1166:1166:1166)) - (PORT datab (1000:1000:1000) (1115:1115:1115)) - (PORT datac (1411:1411:1411) (1477:1477:1477)) - (PORT datad (203:203:203) (239:239:239)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1061:1061:1061) (1166:1166:1166)) - (PORT datab (1976:1976:1976) (2065:2065:2065)) - (PORT datac (1151:1151:1151) (1205:1205:1205)) - (PORT datad (941:941:941) (1012:1012:1012)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (2603:2603:2603) (2772:2772:2772)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (1032:1032:1032)) - (PORT datac (1109:1109:1109) (1164:1164:1164)) - (PORT datad (1148:1148:1148) (1191:1191:1191)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) - (DELAY - (ABSOLUTE - (PORT dataa (988:988:988) (1040:1040:1040)) - (PORT datab (845:845:845) (850:850:850)) - (PORT datac (2021:2021:2021) (2050:2050:2050)) - (PORT datad (1388:1388:1388) (1426:1426:1426)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1582:1582:1582) (1703:1703:1703)) - (PORT datab (917:917:917) (971:971:971)) - (PORT datac (929:929:929) (1008:1008:1008)) - (PORT datad (1530:1530:1530) (1630:1630:1630)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (674:674:674)) - (PORT datab (871:871:871) (890:890:890)) - (PORT datac (598:598:598) (661:661:661)) - (PORT datad (809:809:809) (825:825:825)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1239:1239:1239)) - (PORT datac (1383:1383:1383) (1458:1458:1458)) - (PORT datad (2108:2108:2108) (2253:2253:2253)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (896:896:896) (968:968:968)) - (PORT datab (1559:1559:1559) (1655:1655:1655)) - (PORT datac (211:211:211) (252:252:252)) - (PORT datad (618:618:618) (634:634:634)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1375:1375:1375) (1445:1445:1445)) - (PORT datab (619:619:619) (640:640:640)) - (PORT datac (776:776:776) (799:799:799)) - (PORT datad (597:597:597) (614:614:614)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1683:1683:1683) (1739:1739:1739)) - (PORT datab (1115:1115:1115) (1125:1125:1125)) - (PORT datac (1054:1054:1054) (1110:1110:1110)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1324:1324:1324) (1411:1411:1411)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (592:592:592) (627:627:627)) - (PORT datad (1466:1466:1466) (1538:1538:1538)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (576:576:576) (604:604:604)) - (PORT datab (614:614:614) (675:675:675)) - (PORT datac (611:611:611) (636:636:636)) - (PORT datad (573:573:573) (586:586:586)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (2248:2248:2248) (2386:2386:2386)) - (PORT datab (260:260:260) (341:341:341)) - (PORT datac (1161:1161:1161) (1218:1218:1218)) - (PORT datad (235:235:235) (303:303:303)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (874:874:874) (909:909:909)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT datab (208:208:208) (250:250:250)) - (PORT datad (663:663:663) (707:707:707)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (266:266:266)) - (PORT datab (1027:1027:1027) (1068:1068:1068)) - (PORT datac (332:332:332) (358:358:358)) - (PORT datad (688:688:688) (740:740:740)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1247:1247:1247)) - (PORT datac (887:887:887) (944:944:944)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~14) - (DELAY - (ABSOLUTE - (PORT datac (663:663:663) (747:747:747)) - (PORT datad (890:890:890) (915:915:915)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1435:1435:1435) (1516:1516:1516)) - (PORT datab (619:619:619) (646:646:646)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (1126:1126:1126) (1172:1172:1172)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~47) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (640:640:640)) - (PORT datab (648:648:648) (672:672:672)) - (PORT datac (891:891:891) (929:929:929)) - (PORT datad (873:873:873) (908:908:908)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~48) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (385:385:385)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (616:616:616) (658:658:658)) - (PORT datad (1046:1046:1046) (1069:1069:1069)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (2048:2048:2048) (2143:2143:2143)) - (PORT datac (1652:1652:1652) (1688:1688:1688)) - (PORT datad (1726:1726:1726) (1766:1766:1766)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1331:1331:1331) (1424:1424:1424)) - (PORT datab (1098:1098:1098) (1141:1141:1141)) - (PORT datac (923:923:923) (945:945:945)) - (PORT datad (569:569:569) (578:578:578)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (278:278:278)) - (PORT datab (229:229:229) (272:272:272)) - (PORT datac (1186:1186:1186) (1234:1234:1234)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) - (DELAY - (ABSOLUTE - (PORT dataa (816:816:816) (855:855:855)) - (PORT datab (1257:1257:1257) (1326:1326:1326)) - (PORT datac (1798:1798:1798) (1932:1932:1932)) - (PORT datad (2112:2112:2112) (2257:2257:2257)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (632:632:632) (652:652:652)) - (PORT datac (595:595:595) (618:618:618)) - (PORT datad (847:847:847) (860:860:860)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1357:1357:1357) (1484:1484:1484)) - (PORT datab (742:742:742) (806:806:806)) - (PORT datac (873:873:873) (902:902:902)) - (PORT datad (887:887:887) (943:943:943)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (916:916:916)) - (PORT datab (683:683:683) (749:749:749)) - (PORT datac (971:971:971) (1032:1032:1032)) - (PORT datad (1783:1783:1783) (1858:1858:1858)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1298:1298:1298) (1401:1401:1401)) - (PORT datab (881:881:881) (925:925:925)) - (PORT datac (637:637:637) (657:657:657)) - (PORT datad (1737:1737:1737) (1788:1788:1788)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1357:1357:1357) (1486:1486:1486)) - (PORT datab (643:643:643) (709:709:709)) - (PORT datac (874:874:874) (901:901:901)) - (PORT datad (380:380:380) (406:406:406)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (953:953:953)) - (PORT datab (685:685:685) (750:750:750)) - (PORT datac (967:967:967) (1028:1028:1028)) - (PORT datad (629:629:629) (639:639:639)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1456:1456:1456) (1534:1534:1534)) - (PORT datab (926:926:926) (971:971:971)) - (PORT datac (191:191:191) (224:224:224)) - (PORT datad (1396:1396:1396) (1442:1442:1442)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1587:1587:1587) (1654:1654:1654)) - (PORT datab (1578:1578:1578) (1625:1625:1625)) - (PORT datac (1000:1000:1000) (1045:1045:1045)) - (PORT datad (1562:1562:1562) (1620:1620:1620)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1452:1452:1452) (1526:1526:1526)) - (PORT datab (898:898:898) (959:959:959)) - (PORT datac (823:823:823) (876:876:876)) - (PORT datad (584:584:584) (613:613:613)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1449:1449:1449) (1523:1523:1523)) - (PORT datab (899:899:899) (962:962:962)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (914:914:914) (977:977:977)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (613:613:613)) - (PORT datab (864:864:864) (919:919:919)) - (PORT datac (792:792:792) (849:849:849)) - (PORT datad (781:781:781) (835:835:835)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (652:652:652) (665:665:665)) - (PORT datab (238:238:238) (284:284:284)) - (PORT datac (1314:1314:1314) (1404:1404:1404)) - (PORT datad (2218:2218:2218) (2338:2338:2338)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1788:1788:1788) (1938:1938:1938)) - (PORT datab (1645:1645:1645) (1766:1766:1766)) - (PORT datac (1304:1304:1304) (1398:1398:1398)) - (PORT datad (2565:2565:2565) (2702:2702:2702)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1255:1255:1255) (1317:1317:1317)) - (PORT datab (870:870:870) (893:893:893)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (588:588:588) (606:606:606)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1443:1443:1443) (1548:1548:1548)) - (PORT datab (263:263:263) (309:309:309)) - (PORT datac (1197:1197:1197) (1255:1255:1255)) - (PORT datad (842:842:842) (854:854:854)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~2) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (910:910:910)) - (PORT datab (891:891:891) (912:912:912)) - (PORT datac (859:859:859) (877:877:877)) - (PORT datad (902:902:902) (978:978:978)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (921:921:921)) - (PORT datab (937:937:937) (1012:1012:1012)) - (PORT datac (195:195:195) (239:239:239)) - (PORT datad (1152:1152:1152) (1199:1199:1199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1470:1470:1470) (1476:1476:1476)) - (PORT datab (1497:1497:1497) (1569:1569:1569)) - (PORT datac (1102:1102:1102) (1120:1120:1120)) - (PORT datad (400:400:400) (436:436:436)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (854:854:854) (906:906:906)) - (PORT datab (893:893:893) (913:913:913)) - (PORT datac (861:861:861) (879:879:879)) - (PORT datad (904:904:904) (979:979:979)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (805:805:805)) - (PORT datab (775:775:775) (880:880:880)) - (PORT datad (1178:1178:1178) (1197:1197:1197)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (619:619:619)) - (PORT datab (1166:1166:1166) (1207:1207:1207)) - (PORT datac (854:854:854) (905:905:905)) - (PORT datad (902:902:902) (956:956:956)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1440:1440:1440) (1550:1550:1550)) - (PORT datab (866:866:866) (895:895:895)) - (PORT datac (1284:1284:1284) (1336:1336:1336)) - (PORT datad (1607:1607:1607) (1729:1729:1729)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1494:1494:1494) (1601:1601:1601)) - (PORT datab (1439:1439:1439) (1451:1451:1451)) - (PORT datac (1444:1444:1444) (1551:1551:1551)) - (PORT datad (402:402:402) (439:439:439)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1017:1017:1017) (1057:1057:1057)) - (PORT datac (793:793:793) (802:802:802)) - (PORT datad (1022:1022:1022) (1048:1048:1048)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (397:397:397) (440:440:440)) - (PORT datac (980:980:980) (992:992:992)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (373:373:373)) - (PORT datab (198:198:198) (235:235:235)) - (PORT datac (586:586:586) (613:613:613)) - (PORT datad (1522:1522:1522) (1622:1622:1622)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1222:1222:1222) (1272:1272:1272)) - (PORT datab (1222:1222:1222) (1263:1263:1263)) - (PORT datac (892:892:892) (922:922:922)) - (PORT datad (1507:1507:1507) (1624:1624:1624)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (886:886:886)) - (PORT datab (227:227:227) (274:274:274)) - (PORT datac (1160:1160:1160) (1222:1222:1222)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1685:1685:1685) (1744:1744:1744)) - (PORT datab (1695:1695:1695) (1779:1779:1779)) - (PORT datac (1482:1482:1482) (1577:1577:1577)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (934:934:934) (1034:1034:1034)) - (PORT datab (206:206:206) (246:246:246)) - (PORT datac (1192:1192:1192) (1254:1254:1254)) - (PORT datad (882:882:882) (917:917:917)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) - (DELAY - (ABSOLUTE - (PORT datab (1193:1193:1193) (1230:1230:1230)) - (PORT datac (1251:1251:1251) (1308:1308:1308)) - (PORT datad (780:780:780) (799:799:799)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) - (DELAY - (ABSOLUTE - (PORT dataa (896:896:896) (976:976:976)) - (PORT datab (940:940:940) (1022:1022:1022)) - (PORT datac (1140:1140:1140) (1178:1178:1178)) - (PORT datad (375:375:375) (417:417:417)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1284:1284:1284) (1345:1345:1345)) - (PORT datab (1189:1189:1189) (1228:1228:1228)) - (PORT datac (1135:1135:1135) (1177:1177:1177)) - (PORT datad (780:780:780) (799:799:799)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (343:343:343)) - (PORT datab (224:224:224) (272:272:272)) - (PORT datac (342:342:342) (371:371:371)) - (PORT datad (1219:1219:1219) (1301:1301:1301)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1167:1167:1167) (1203:1203:1203)) - (PORT datab (1191:1191:1191) (1242:1242:1242)) - (PORT datad (1220:1220:1220) (1299:1299:1299)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de2) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1593:1593:1593) (1569:1569:1569)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (405:405:405)) - (PORT datab (224:224:224) (269:269:269)) - (PORT datac (222:222:222) (302:302:302)) - (PORT datad (1202:1202:1202) (1285:1285:1285)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (568:568:568) (586:586:586)) - (PORT datab (1028:1028:1028) (1073:1073:1073)) - (PORT datac (338:338:338) (364:364:364)) - (PORT datad (686:686:686) (739:739:739)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (687:687:687)) - (PORT datab (1720:1720:1720) (1802:1802:1802)) - (PORT datad (879:879:879) (876:876:876)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (2640:2640:2640) (2740:2740:2740)) - (PORT datab (1718:1718:1718) (1823:1823:1823)) - (PORT datac (1017:1017:1017) (1049:1049:1049)) - (PORT datad (1534:1534:1534) (1564:1564:1564)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (277:277:277)) - (PORT datab (894:894:894) (923:923:923)) - (PORT datac (1486:1486:1486) (1564:1564:1564)) - (PORT datad (1217:1217:1217) (1256:1256:1256)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) - (DELAY - (ABSOLUTE - (PORT dataa (985:985:985) (1038:1038:1038)) - (PORT datab (204:204:204) (246:246:246)) - (PORT datac (946:946:946) (1014:1014:1014)) - (PORT datad (209:209:209) (240:240:240)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla30npla13M5T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (1011:1011:1011)) - (PORT datab (229:229:229) (278:278:278)) - (PORT datac (1408:1408:1408) (1479:1479:1479)) - (PORT datad (1499:1499:1499) (1550:1550:1550)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1150:1150:1150) (1181:1181:1181)) - (PORT datab (1549:1549:1549) (1573:1573:1573)) - (PORT datac (592:592:592) (626:626:626)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (391:391:391)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (178:178:178) (207:207:207)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (910:910:910) (934:934:934)) - (PORT datab (654:654:654) (689:689:689)) - (PORT datac (1104:1104:1104) (1117:1117:1117)) - (PORT datad (766:766:766) (786:786:786)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1624:1624:1624) (1711:1711:1711)) - (PORT datab (1531:1531:1531) (1582:1582:1582)) - (PORT datac (1704:1704:1704) (1824:1824:1824)) - (PORT datad (1073:1073:1073) (1075:1075:1075)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (2002:2002:2002) (2195:2195:2195)) - (PORT datab (1455:1455:1455) (1549:1549:1549)) - (PORT datac (1508:1508:1508) (1592:1592:1592)) - (PORT datad (1918:1918:1918) (1978:1978:1978)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (965:965:965)) - (PORT datab (871:871:871) (909:909:909)) - (PORT datac (803:803:803) (870:870:870)) - (PORT datad (1526:1526:1526) (1620:1620:1620)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (664:664:664)) - (PORT datab (678:678:678) (735:735:735)) - (PORT datac (919:919:919) (966:966:966)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (728:728:728)) - (PORT datab (1191:1191:1191) (1244:1244:1244)) - (PORT datac (669:669:669) (694:694:694)) - (PORT datad (1304:1304:1304) (1397:1397:1397)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1369:1369:1369) (1431:1431:1431)) - (PORT datab (643:643:643) (680:680:680)) - (PORT datac (1322:1322:1322) (1362:1362:1362)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1105:1105:1105) (1190:1190:1190)) - (PORT datab (1820:1820:1820) (1897:1897:1897)) - (PORT datad (966:966:966) (1074:1074:1074)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (932:932:932)) - (PORT datab (680:680:680) (741:741:741)) - (PORT datac (202:202:202) (239:239:239)) - (PORT datad (2206:2206:2206) (2251:2251:2251)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1252:1252:1252) (1348:1348:1348)) - (PORT datab (1492:1492:1492) (1598:1598:1598)) - (PORT datac (1226:1226:1226) (1277:1277:1277)) - (PORT datad (1231:1231:1231) (1263:1263:1263)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1906:1906:1906) (2000:2000:2000)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (869:869:869) (926:926:926)) - (PORT datad (188:188:188) (220:220:220)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (635:635:635)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (898:898:898) (931:931:931)) - (PORT datad (816:816:816) (860:860:860)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (810:810:810) (881:881:881)) - (PORT datab (206:206:206) (246:246:246)) - (PORT datac (561:561:561) (575:575:575)) - (PORT datad (613:613:613) (668:668:668)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (889:889:889)) - (PORT datac (208:208:208) (251:251:251)) - (PORT datad (202:202:202) (238:238:238)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1311:1311:1311) (1368:1368:1368)) - (PORT datab (614:614:614) (640:640:640)) - (PORT datac (842:842:842) (872:872:872)) - (PORT datad (607:607:607) (635:635:635)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1417:1417:1417) (1464:1464:1464)) - (PORT datab (910:910:910) (954:954:954)) - (PORT datac (1136:1136:1136) (1177:1177:1177)) - (PORT datad (1173:1173:1173) (1255:1255:1255)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1757:1757:1757) (1831:1831:1831)) - (PORT datab (836:836:836) (849:849:849)) - (PORT datac (2018:2018:2018) (2050:2050:2050)) - (PORT datad (2040:2040:2040) (2102:2102:2102)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~40) - (DELAY - (ABSOLUTE - (PORT dataa (927:927:927) (961:961:961)) - (PORT datab (1098:1098:1098) (1150:1150:1150)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (535:535:535) (566:566:566)) - (PORT datab (662:662:662) (694:694:694)) - (PORT datac (2000:2000:2000) (2031:2031:2031)) - (PORT datad (538:538:538) (549:549:549)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (852:852:852) (924:924:924)) - (PORT datac (179:179:179) (214:214:214)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (855:855:855) (863:863:863)) - (PORT datac (568:568:568) (591:591:591)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~93) - (DELAY - (ABSOLUTE - (PORT dataa (1191:1191:1191) (1227:1227:1227)) - (PORT datab (1050:1050:1050) (1057:1057:1057)) - (PORT datac (1185:1185:1185) (1207:1207:1207)) - (PORT datad (1343:1343:1343) (1388:1388:1388)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) - (DELAY - (ABSOLUTE - (PORT dataa (249:249:249) (338:338:338)) - (PORT datab (223:223:223) (268:268:268)) - (PORT datac (337:337:337) (367:367:367)) - (PORT datad (1203:1203:1203) (1285:1285:1285)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) - (DELAY - (ABSOLUTE - (PORT datab (1384:1384:1384) (1432:1432:1432)) - (PORT datac (1179:1179:1179) (1200:1200:1200)) - (PORT datad (594:594:594) (610:610:610)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) - (DELAY - (ABSOLUTE - (PORT datac (900:900:900) (943:943:943)) - (PORT datad (1328:1328:1328) (1383:1383:1383)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1165:1165:1165) (1261:1261:1261)) - (PORT datab (223:223:223) (270:270:270)) - (PORT datac (1141:1141:1141) (1178:1178:1178)) - (PORT datad (671:671:671) (721:721:721)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) - (DELAY - (ABSOLUTE - (PORT dataa (704:704:704) (769:769:769)) - (PORT datab (1469:1469:1469) (1552:1552:1552)) - (PORT datac (1145:1145:1145) (1180:1180:1180)) - (PORT datad (199:199:199) (235:235:235)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (766:766:766)) - (PORT datab (1471:1471:1471) (1557:1557:1557)) - (PORT datac (1138:1138:1138) (1176:1176:1176)) - (PORT datad (196:196:196) (232:232:232)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1346:1346:1346) (1411:1411:1411)) - (PORT datab (869:869:869) (903:903:903)) - (PORT datac (1807:1807:1807) (1896:1896:1896)) - (PORT datad (1570:1570:1570) (1608:1608:1608)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datad (868:868:868) (885:885:885)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) - (DELAY - (ABSOLUTE - (PORT dataa (981:981:981) (1092:1092:1092)) - (PORT datab (657:657:657) (681:681:681)) - (PORT datac (908:908:908) (975:975:975)) - (PORT datad (1438:1438:1438) (1536:1536:1536)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (1101:1101:1101) (1154:1154:1154)) - (PORT datab (701:701:701) (782:782:782)) - (PORT datac (1444:1444:1444) (1551:1551:1551)) - (PORT datad (1465:1465:1465) (1554:1554:1554)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (634:634:634)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (622:622:622) (651:651:651)) - (PORT datad (1082:1082:1082) (1107:1107:1107)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (419:419:419)) - (PORT datab (1179:1179:1179) (1229:1229:1229)) - (PORT datac (351:351:351) (380:380:380)) - (PORT datad (1087:1087:1087) (1108:1108:1108)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1246:1246:1246) (1335:1335:1335)) - (PORT datab (1577:1577:1577) (1714:1714:1714)) - (PORT datac (2188:2188:2188) (2312:2312:2312)) - (PORT datad (1069:1069:1069) (1164:1164:1164)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) - (DELAY - (ABSOLUTE - (PORT dataa (942:942:942) (1012:1012:1012)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1253:1253:1253) (1293:1293:1293)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (660:660:660)) - (PORT datac (659:659:659) (688:688:688)) - (PORT datad (550:550:550) (559:559:559)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1144:1144:1144) (1180:1180:1180)) - (PORT datab (218:218:218) (265:265:265)) - (PORT datac (1135:1135:1135) (1168:1168:1168)) - (PORT datad (665:665:665) (712:712:712)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~2) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (938:938:938)) - (PORT datab (900:900:900) (913:913:913)) - (PORT datac (920:920:920) (1008:1008:1008)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (700:700:700) (751:751:751)) - (PORT datab (1166:1166:1166) (1198:1198:1198)) - (PORT datad (948:948:948) (968:968:968)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_af) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1142:1142:1142) (1184:1184:1184)) - (PORT datab (248:248:248) (332:332:332)) - (PORT datac (1144:1144:1144) (1179:1179:1179)) - (PORT datad (672:672:672) (720:720:720)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (703:703:703)) - (PORT datab (1351:1351:1351) (1386:1386:1386)) - (PORT datad (908:908:908) (958:958:958)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1142:1142:1142) (1183:1183:1183)) - (PORT datab (250:250:250) (335:335:335)) - (PORT datac (1137:1137:1137) (1173:1173:1173)) - (PORT datad (664:664:664) (718:718:718)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) - (DELAY - (ABSOLUTE - (PORT dataa (1721:1721:1721) (1780:1780:1780)) - (PORT datab (1170:1170:1170) (1223:1223:1223)) - (PORT datad (792:792:792) (797:797:797)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) - (DELAY - (ABSOLUTE - (PORT dataa (709:709:709) (761:761:761)) - (PORT datab (914:914:914) (975:975:975)) - (PORT datac (1817:1817:1817) (1896:1896:1896)) - (PORT datad (1153:1153:1153) (1178:1178:1178)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1482:1482:1482) (1581:1581:1581)) - (PORT datac (1016:1016:1016) (1055:1055:1055)) - (PORT datad (321:321:321) (344:344:344)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1428:1428:1428) (1487:1487:1487)) - (PORT datab (1168:1168:1168) (1215:1215:1215)) - (PORT datac (2035:2035:2035) (2124:2124:2124)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1158:1158:1158) (1200:1200:1200)) - (PORT datab (2031:2031:2031) (2127:2127:2127)) - (PORT datac (969:969:969) (1020:1020:1020)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (826:826:826) (902:902:902)) - (PORT datab (1517:1517:1517) (1560:1560:1560)) - (PORT datac (1294:1294:1294) (1324:1324:1324)) - (PORT datad (862:862:862) (880:880:880)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) - (DELAY - (ABSOLUTE - (PORT datab (229:229:229) (272:272:272)) - (PORT datac (202:202:202) (239:239:239)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (1544:1544:1544) (1653:1653:1653)) - (PORT datac (208:208:208) (246:246:246)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (620:620:620)) - (PORT datab (876:876:876) (893:893:893)) - (PORT datac (1384:1384:1384) (1444:1444:1444)) - (PORT datad (1947:1947:1947) (1977:1977:1977)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (266:266:266)) - (PORT datab (2017:2017:2017) (2075:2075:2075)) - (PORT datac (804:804:804) (827:827:827)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (740:740:740)) - (PORT datab (1445:1445:1445) (1514:1514:1514)) - (PORT datac (360:360:360) (389:389:389)) - (PORT datad (1121:1121:1121) (1177:1177:1177)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (277:277:277)) - (PORT datab (558:558:558) (578:578:578)) - (PORT datac (804:804:804) (818:818:818)) - (PORT datad (595:595:595) (633:633:633)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1170:1170:1170) (1229:1229:1229)) - (PORT datab (599:599:599) (614:614:614)) - (PORT datac (654:654:654) (698:698:698)) - (PORT datad (866:866:866) (893:893:893)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) - (DELAY - (ABSOLUTE - (PORT dataa (692:692:692) (737:737:737)) - (PORT datab (1195:1195:1195) (1210:1210:1210)) - (PORT datac (1157:1157:1157) (1193:1193:1193)) - (PORT datad (590:590:590) (602:602:602)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (936:936:936)) - (PORT datab (1199:1199:1199) (1253:1253:1253)) - (PORT datac (889:889:889) (931:931:931)) - (PORT datad (630:630:630) (687:687:687)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (601:601:601)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (951:951:951)) - (PORT datab (1199:1199:1199) (1252:1252:1252)) - (PORT datac (361:361:361) (394:394:394)) - (PORT datad (1118:1118:1118) (1176:1176:1176)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1169:1169:1169) (1230:1230:1230)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1158:1158:1158) (1196:1196:1196)) - (PORT datad (863:863:863) (892:892:892)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (252:252:252)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (652:652:652) (697:697:697)) - (PORT datad (845:845:845) (894:894:894)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (637:637:637)) - (PORT datab (686:686:686) (707:707:707)) - (PORT datac (378:378:378) (410:410:410)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (607:607:607) (625:625:625)) - (PORT datac (530:530:530) (542:542:542)) - (PORT datad (838:838:838) (876:876:876)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (962:962:962)) - (PORT datab (1558:1558:1558) (1661:1661:1661)) - (PORT datac (1407:1407:1407) (1474:1474:1474)) - (PORT datad (200:200:200) (235:235:235)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (660:660:660)) - (PORT datab (965:965:965) (1060:1060:1060)) - (PORT datac (1732:1732:1732) (1835:1835:1835)) - (PORT datad (1150:1150:1150) (1179:1179:1179)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1102:1102:1102) (1150:1150:1150)) - (PORT datab (1473:1473:1473) (1583:1583:1583)) - (PORT datac (1614:1614:1614) (1681:1681:1681)) - (PORT datad (1173:1173:1173) (1219:1219:1219)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1405:1405:1405) (1418:1418:1418)) - (PORT datab (1241:1241:1241) (1276:1276:1276)) - (PORT datac (1251:1251:1251) (1275:1275:1275)) - (PORT datad (1260:1260:1260) (1298:1298:1298)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1121:1121:1121) (1151:1151:1151)) - (PORT datac (613:613:613) (636:636:636)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~28) - (DELAY - (ABSOLUTE - (PORT dataa (236:236:236) (284:284:284)) - (PORT datab (219:219:219) (256:256:256)) - (PORT datac (1148:1148:1148) (1190:1190:1190)) - (PORT datad (194:194:194) (218:218:218)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~35) - (DELAY - (ABSOLUTE - (PORT datab (2004:2004:2004) (2134:2134:2134)) - (PORT datac (1351:1351:1351) (1365:1365:1365)) - (PORT datad (859:859:859) (872:872:872)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~36) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (267:267:267)) - (PORT datab (910:910:910) (941:941:941)) - (PORT datac (621:621:621) (645:645:645)) - (PORT datad (924:924:924) (962:962:962)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1513:1513:1513) (1596:1596:1596)) - (PORT datab (1166:1166:1166) (1202:1202:1202)) - (PORT datac (1104:1104:1104) (1142:1142:1142)) - (PORT datad (548:548:548) (560:560:560)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (650:650:650)) - (PORT datab (234:234:234) (278:278:278)) - (PORT datac (1132:1132:1132) (1164:1164:1164)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1646:1646:1646) (1763:1763:1763)) - (PORT datab (1008:1008:1008) (1101:1101:1101)) - (PORT datac (1033:1033:1033) (1107:1107:1107)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1208:1208:1208)) - (PORT datab (1537:1537:1537) (1621:1621:1621)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (923:923:923)) - (PORT datab (570:570:570) (590:590:590)) - (PORT datac (603:603:603) (628:628:628)) - (PORT datad (595:595:595) (619:619:619)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1229:1229:1229) (1305:1305:1305)) - (PORT datab (1275:1275:1275) (1372:1372:1372)) - (PORT datac (1155:1155:1155) (1192:1192:1192)) - (PORT datad (709:709:709) (772:772:772)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (690:690:690) (719:719:719)) - (PORT datab (1344:1344:1344) (1367:1367:1367)) - (PORT datac (1222:1222:1222) (1269:1269:1269)) - (PORT datad (1654:1654:1654) (1748:1748:1748)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1005:1005:1005) (1089:1089:1089)) - (PORT datab (887:887:887) (923:923:923)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (221:221:221) (249:249:249)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1035:1035:1035) (1133:1133:1133)) - (PORT datac (2185:2185:2185) (2272:2272:2272)) - (PORT datad (654:654:654) (711:711:711)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (718:718:718) (782:782:782)) - (PORT datab (1135:1135:1135) (1159:1159:1159)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1153:1153:1153) (1186:1186:1186)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1016:1016:1016) (1112:1112:1112)) - (PORT datab (668:668:668) (685:685:685)) - (PORT datac (1012:1012:1012) (1113:1113:1113)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (933:933:933) (975:975:975)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) - (DELAY - (ABSOLUTE - (PORT datab (278:278:278) (366:366:366)) - (PORT datac (241:241:241) (319:319:319)) - (PORT datad (246:246:246) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (971:971:971)) - (PORT datab (218:218:218) (257:257:257)) - (PORT datac (1095:1095:1095) (1116:1116:1116)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1104:1104:1104) (1192:1192:1192)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (650:650:650) (716:716:716)) - (PORT datad (966:966:966) (1077:1077:1077)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (2563:2563:2563) (2705:2705:2705)) - (PORT datab (1595:1595:1595) (1711:1711:1711)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (218:218:218) (258:258:258)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1067:1067:1067) (1148:1148:1148)) - (PORT datab (204:204:204) (245:245:245)) - (PORT datac (880:880:880) (911:911:911)) - (PORT datad (824:824:824) (834:834:834)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) - (DELAY - (ABSOLUTE - (PORT datab (931:931:931) (1002:1002:1002)) - (PORT datad (625:625:625) (662:662:662)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (663:663:663)) - (PORT datab (924:924:924) (986:986:986)) - (PORT datac (1079:1079:1079) (1113:1113:1113)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~4) - (DELAY - (ABSOLUTE - (PORT dataa (882:882:882) (951:951:951)) - (PORT datab (902:902:902) (933:933:933)) - (PORT datac (628:628:628) (672:672:672)) - (PORT datad (883:883:883) (909:909:909)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (1992:1992:1992) (2133:2133:2133)) - (PORT datab (907:907:907) (958:958:958)) - (PORT datac (224:224:224) (265:265:265)) - (PORT datad (1139:1139:1139) (1178:1178:1178)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~5) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (951:951:951)) - (PORT datab (917:917:917) (970:970:970)) - (PORT datac (879:879:879) (911:911:911)) - (PORT datad (593:593:593) (627:627:627)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (926:926:926)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1074:1074:1074) (1121:1121:1121)) - (PORT datab (894:894:894) (950:950:950)) - (PORT datac (601:601:601) (665:665:665)) - (PORT datad (855:855:855) (908:908:908)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~16) - (DELAY - (ABSOLUTE - (PORT dataa (2419:2419:2419) (2569:2569:2569)) - (PORT datab (1823:1823:1823) (1925:1925:1925)) - (PORT datac (1074:1074:1074) (1067:1067:1067)) - (PORT datad (1576:1576:1576) (1735:1735:1735)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) - (DELAY - (ABSOLUTE - (PORT dataa (827:827:827) (849:849:849)) - (PORT datab (912:912:912) (944:944:944)) - (PORT datac (835:835:835) (868:868:868)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (2421:2421:2421) (2571:2571:2571)) - (PORT datab (2408:2408:2408) (2540:2540:2540)) - (PORT datac (1413:1413:1413) (1473:1473:1473)) - (PORT datad (1573:1573:1573) (1734:1734:1734)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (229:229:229) (272:272:272)) - (PORT datac (202:202:202) (241:241:241)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1252:1252:1252) (1310:1310:1310)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (832:832:832) (831:831:831)) - (PORT datad (872:872:872) (917:917:917)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (882:882:882) (898:898:898)) - (PORT datab (237:237:237) (281:281:281)) - (PORT datac (619:619:619) (671:671:671)) - (PORT datad (1350:1350:1350) (1391:1391:1391)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1228:1228:1228) (1318:1318:1318)) - (PORT datab (1384:1384:1384) (1497:1497:1497)) - (PORT datac (857:857:857) (917:917:917)) - (PORT datad (831:831:831) (860:860:860)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2065:2065:2065) (2136:2136:2136)) - (PORT datab (2504:2504:2504) (2706:2706:2706)) - (PORT datac (2886:2886:2886) (3058:3058:3058)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (845:845:845) (894:894:894)) - (PORT datac (990:990:990) (1030:1030:1030)) - (PORT datad (1379:1379:1379) (1425:1425:1425)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (268:268:268)) - (PORT datac (663:663:663) (700:700:700)) - (PORT datad (1031:1031:1031) (1094:1094:1094)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1328:1328:1328) (1447:1447:1447)) - (PORT datac (1179:1179:1179) (1239:1239:1239)) - (PORT datad (2024:2024:2024) (2146:2146:2146)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1166:1166:1166)) - (PORT datab (226:226:226) (266:266:266)) - (PORT datac (604:604:604) (622:622:622)) - (PORT datad (1151:1151:1151) (1191:1191:1191)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1230:1230:1230)) - (PORT datac (1131:1131:1131) (1168:1168:1168)) - (PORT datad (957:957:957) (1017:1017:1017)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) - (DELAY - (ABSOLUTE - (PORT datab (2109:2109:2109) (2224:2224:2224)) - (PORT datac (925:925:925) (983:983:983)) - (PORT datad (1982:1982:1982) (2072:2072:2072)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1189:1189:1189) (1250:1250:1250)) - (PORT datab (599:599:599) (617:617:617)) - (PORT datac (871:871:871) (913:913:913)) - (PORT datad (1143:1143:1143) (1193:1193:1193)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1120:1120:1120) (1154:1154:1154)) - (PORT datab (595:595:595) (609:609:609)) - (PORT datac (1115:1115:1115) (1174:1174:1174)) - (PORT datad (878:878:878) (910:910:910)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1801:1801:1801) (1843:1843:1843)) - (PORT datab (1573:1573:1573) (1608:1608:1608)) - (PORT datad (985:985:985) (1020:1020:1020)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (957:957:957)) - (PORT datab (1162:1162:1162) (1232:1232:1232)) - (PORT datac (1480:1480:1480) (1554:1554:1554)) - (PORT datad (1102:1102:1102) (1119:1119:1119)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (702:702:702) (740:740:740)) - (PORT datab (913:913:913) (942:942:942)) - (PORT datac (618:618:618) (642:642:642)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (1512:1512:1512) (1540:1540:1540)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (926:926:926) (959:959:959)) - (PORT datab (887:887:887) (953:953:953)) - (PORT datac (185:185:185) (226:226:226)) - (PORT datad (885:885:885) (902:902:902)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (1725:1725:1725) (1783:1783:1783)) - (PORT datad (330:330:330) (351:351:351)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1198:1198:1198) (1240:1240:1240)) - (PORT datab (835:835:835) (861:861:861)) - (PORT datac (841:841:841) (865:865:865)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1551:1551:1551) (1610:1610:1610)) - (PORT datab (1763:1763:1763) (1826:1826:1826)) - (PORT datac (2606:2606:2606) (2704:2704:2704)) - (PORT datad (1157:1157:1157) (1177:1177:1177)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (2641:2641:2641) (2744:2744:2744)) - (PORT datab (1587:1587:1587) (1722:1722:1722)) - (PORT datac (639:639:639) (659:659:659)) - (PORT datad (202:202:202) (233:233:233)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (638:638:638)) - (PORT datab (653:653:653) (683:683:683)) - (PORT datac (637:637:637) (684:684:684)) - (PORT datad (847:847:847) (906:906:906)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) - (DELAY - (ABSOLUTE - (PORT datab (707:707:707) (739:739:739)) - (PORT datac (1055:1055:1055) (1068:1068:1068)) - (PORT datad (921:921:921) (956:956:956)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (401:401:401)) - (PORT datab (1114:1114:1114) (1146:1146:1146)) - (PORT datac (1038:1038:1038) (1080:1080:1080)) - (PORT datad (853:853:853) (854:854:854)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1748:1748:1748) (1768:1768:1768)) - (PORT datab (881:881:881) (907:907:907)) - (PORT datac (1501:1501:1501) (1630:1630:1630)) - (PORT datad (1129:1129:1129) (1199:1199:1199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1137:1137:1137) (1170:1170:1170)) - (PORT datab (1651:1651:1651) (1721:1721:1721)) - (PORT datac (1148:1148:1148) (1186:1186:1186)) - (PORT datad (212:212:212) (247:247:247)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (671:671:671) (702:702:702)) - (PORT datab (1148:1148:1148) (1207:1207:1207)) - (PORT datac (1182:1182:1182) (1237:1237:1237)) - (PORT datad (969:969:969) (1043:1043:1043)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~1) - (DELAY - (ABSOLUTE - (PORT dataa (294:294:294) (365:365:365)) - (PORT datac (1702:1702:1702) (1757:1757:1757)) - (PORT datad (437:437:437) (482:482:482)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (685:685:685)) - (PORT datab (1154:1154:1154) (1208:1208:1208)) - (PORT datac (1484:1484:1484) (1544:1544:1544)) - (PORT datad (1270:1270:1270) (1331:1331:1331)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1443:1443:1443) (1501:1501:1501)) - (PORT datab (912:912:912) (961:961:961)) - (PORT datac (896:896:896) (925:925:925)) - (PORT datad (962:962:962) (988:988:988)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) - (DELAY - (ABSOLUTE - (PORT dataa (874:874:874) (897:897:897)) - (PORT datac (992:992:992) (1045:1045:1045)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1066:1066:1066) (1139:1139:1139)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1089:1089:1089) (1116:1116:1116)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (374:374:374)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (345:345:345) (385:385:385)) - (PORT datad (858:858:858) (866:866:866)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1408:1408:1408) (1444:1444:1444)) - (PORT datab (814:814:814) (844:844:844)) - (PORT datac (1711:1711:1711) (1730:1730:1730)) - (PORT datad (911:911:911) (949:949:949)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) - (DELAY - (ABSOLUTE - (PORT dataa (1097:1097:1097) (1124:1124:1124)) - (PORT datab (662:662:662) (693:693:693)) - (PORT datac (868:868:868) (892:892:892)) - (PORT datad (871:871:871) (914:914:914)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (275:275:275)) - (PORT datab (642:642:642) (663:663:663)) - (PORT datac (1367:1367:1367) (1431:1431:1431)) - (PORT datad (1132:1132:1132) (1158:1158:1158)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1647:1647:1647) (1764:1764:1764)) - (PORT datab (1009:1009:1009) (1098:1098:1098)) - (PORT datac (1939:1939:1939) (1965:1965:1965)) - (PORT datad (1664:1664:1664) (1726:1726:1726)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (264:264:264)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (646:646:646) (703:703:703)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (275:275:275)) - (PORT datab (645:645:645) (669:669:669)) - (PORT datac (199:199:199) (236:236:236)) - (PORT datad (1191:1191:1191) (1215:1215:1215)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (1028:1028:1028) (1084:1084:1084)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (593:593:593) (617:617:617)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) - (DELAY - (ABSOLUTE - (PORT dataa (896:896:896) (960:960:960)) - (PORT datab (1128:1128:1128) (1156:1156:1156)) - (PORT datac (886:886:886) (918:918:918)) - (PORT datad (1142:1142:1142) (1198:1198:1198)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) - (DELAY - (ABSOLUTE - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (593:593:593) (653:653:653)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) - (DELAY - (ABSOLUTE - (PORT dataa (214:214:214) (264:264:264)) - (PORT datac (557:557:557) (571:571:571)) - (PORT datad (812:812:812) (882:882:882)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1301:1301:1301) (1363:1363:1363)) - (PORT datab (670:670:670) (695:695:695)) - (PORT datac (195:195:195) (228:228:228)) - (PORT datad (1179:1179:1179) (1216:1216:1216)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) - (DELAY - (ABSOLUTE - (PORT dataa (565:565:565) (585:585:585)) - (PORT datac (793:793:793) (849:849:849)) - (PORT datad (781:781:781) (835:835:835)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (914:914:914) (932:932:932)) - (PORT datab (670:670:670) (713:713:713)) - (PORT datac (371:371:371) (406:406:406)) - (PORT datad (595:595:595) (643:643:643)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~45) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (677:677:677)) - (PORT datab (867:867:867) (880:880:880)) - (PORT datac (866:866:866) (892:892:892)) - (PORT datad (646:646:646) (680:680:680)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~46) - (DELAY - (ABSOLUTE - (PORT datab (821:821:821) (842:842:842)) - (PORT datac (201:201:201) (237:237:237)) - (PORT datad (1425:1425:1425) (1509:1509:1509)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) - (DELAY - (ABSOLUTE - (PORT dataa (599:599:599) (610:610:610)) - (PORT datab (926:926:926) (956:956:956)) - (PORT datac (586:586:586) (596:596:596)) - (PORT datad (582:582:582) (613:613:613)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1011:1011:1011)) - (PORT datab (1561:1561:1561) (1659:1659:1659)) - (PORT datac (842:842:842) (876:876:876)) - (PORT datad (371:371:371) (400:400:400)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (251:251:251)) - (PORT datab (340:340:340) (371:371:371)) - (PORT datac (211:211:211) (252:252:252)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~4) - (DELAY - (ABSOLUTE - (PORT dataa (926:926:926) (963:963:963)) - (PORT datac (857:857:857) (921:921:921)) - (PORT datad (828:828:828) (859:859:859)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (681:681:681)) - (PORT datab (1486:1486:1486) (1550:1550:1550)) - (PORT datac (820:820:820) (856:856:856)) - (PORT datad (815:815:815) (871:871:871)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) - (DELAY - (ABSOLUTE - (PORT dataa (446:446:446) (504:504:504)) - (PORT datab (946:946:946) (986:986:986)) - (PORT datac (374:374:374) (405:405:405)) - (PORT datad (1915:1915:1915) (2040:2040:2040)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~20) - (DELAY - (ABSOLUTE - (PORT dataa (2472:2472:2472) (2661:2661:2661)) - (PORT datab (554:554:554) (575:575:575)) - (PORT datac (892:892:892) (956:956:956)) - (PORT datad (1125:1125:1125) (1142:1142:1142)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (677:677:677)) - (PORT datab (581:581:581) (596:596:596)) - (PORT datac (785:785:785) (834:834:834)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (619:619:619)) - (PORT datab (876:876:876) (893:893:893)) - (PORT datac (1988:1988:1988) (2046:2046:2046)) - (PORT datad (596:596:596) (620:620:620)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1153:1153:1153) (1167:1167:1167)) - (PORT datab (1567:1567:1567) (1688:1688:1688)) - (PORT datac (635:635:635) (692:692:692)) - (PORT datad (604:604:604) (642:642:642)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (914:914:914)) - (PORT datab (562:562:562) (571:571:571)) - (PORT datac (611:611:611) (649:649:649)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (663:663:663)) - (PORT datab (925:925:925) (986:986:986)) - (PORT datac (532:532:532) (538:538:538)) - (PORT datad (873:873:873) (880:880:880)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (276:276:276)) - (PORT datab (643:643:643) (675:675:675)) - (PORT datac (842:842:842) (864:864:864)) - (PORT datad (344:344:344) (366:366:366)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) - (DELAY - (ABSOLUTE - (PORT datab (1438:1438:1438) (1508:1508:1508)) - (PORT datac (915:915:915) (945:945:945)) - (PORT datad (819:819:819) (835:835:835)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (275:275:275)) - (PORT datab (1330:1330:1330) (1334:1334:1334)) - (PORT datac (1375:1375:1375) (1393:1393:1393)) - (PORT datad (312:312:312) (330:330:330)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) - (DELAY - (ABSOLUTE - (PORT datab (949:949:949) (999:999:999)) - (PORT datac (1439:1439:1439) (1498:1498:1498)) - (PORT datad (671:671:671) (702:702:702)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (974:974:974) (1028:1028:1028)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1880:1880:1880) (1905:1905:1905)) - (PORT datab (702:702:702) (730:730:730)) - (PORT datad (1198:1198:1198) (1238:1238:1238)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) - (DELAY - (ABSOLUTE - (PORT datab (709:709:709) (737:737:737)) - (PORT datac (1057:1057:1057) (1070:1070:1070)) - (PORT datad (923:923:923) (954:954:954)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (738:738:738) (772:772:772)) - (PORT datac (609:609:609) (659:659:659)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT datac (1990:1990:1990) (2095:2095:2095)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT asdata (567:567:567) (646:646:646)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT asdata (569:569:569) (648:648:648)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE KEY\[0\]\~input) @@ -11353,8 +1127,8 @@ (INSTANCE reset) (DELAY (ABSOLUTE - (PORT datac (1566:1566:1566) (1527:1527:1527)) - (PORT datad (531:531:531) (524:524:524)) + (PORT datac (1565:1565:1565) (1526:1526:1526)) + (PORT datad (529:529:529) (525:525:525)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -11365,7 +1139,7 @@ (INSTANCE z80_\|resets_\|x1\~0) (DELAY (ABSOLUTE - (PORT datad (1474:1474:1474) (1549:1549:1549)) + (PORT datad (198:198:198) (224:224:224)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -11375,7 +1149,7 @@ (INSTANCE z80_\|fpga_reset) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1542:1542:1542)) + (PORT clk (1527:1527:1527) (1539:1539:1539)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -11389,7 +1163,7 @@ (INSTANCE z80_\|fpga_reset\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (727:727:727) (752:752:752)) + (PORT inclk[0] (753:753:753) (788:788:788)) ) ) ) @@ -11398,9 +1172,9 @@ (INSTANCE z80_\|resets_\|x1) (DELAY (ABSOLUTE - (PORT clk (1523:1523:1523) (1527:1527:1527)) + (PORT clk (1539:1539:1539) (1540:1540:1540)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1883:1883:1883) (1869:1869:1869)) + (PORT clrn (1574:1574:1574) (1552:1552:1552)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -11411,27 +1185,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc_int\~0) + (INSTANCE z80_\|resets_\|x3) (DELAY (ABSOLUTE - (PORT dataa (649:649:649) (728:728:728)) - (PORT datab (605:605:605) (665:665:665)) - (PORT datad (1168:1168:1168) (1217:1217:1217)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (1901:1901:1901) (2085:2085:2085)) + (PORT datac (1463:1463:1463) (1532:1532:1532)) + (PORT datad (1153:1153:1153) (1264:1264:1264)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|clrpc_int) + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) (DELAY (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) + (PORT clk (1533:1533:1533) (1551:1551:1551)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1597:1597:1597) (1572:1572:1572)) + (PORT clrn (1577:1577:1577) (1554:1554:1554)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -11442,166 +1215,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc\~0) + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) (DELAY (ABSOLUTE - (PORT dataa (251:251:251) (340:340:340)) - (PORT datab (253:253:253) (339:339:339)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[7\]) - (DELAY - (ABSOLUTE - (PORT datac (657:657:657) (695:695:695)) - (PORT datad (609:609:609) (638:638:638)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2470:2470:2470) (2664:2664:2664)) - (PORT datac (891:891:891) (959:959:959)) - (PORT datad (1997:1997:1997) (2087:2087:2087)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (394:394:394)) - (PORT datab (558:558:558) (580:580:580)) - (PORT datac (844:844:844) (879:879:879)) - (PORT datad (1124:1124:1124) (1141:1141:1141)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1113:1113:1113) (1149:1149:1149)) - (PORT datab (1162:1162:1162) (1184:1184:1184)) - (PORT datac (794:794:794) (810:810:810)) - (PORT datad (642:642:642) (654:654:654)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (985:985:985) (1053:1053:1053)) - (PORT datab (1645:1645:1645) (1657:1657:1657)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (1141:1141:1141) (1167:1167:1167)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1232:1232:1232) (1303:1303:1303)) - (PORT datab (1001:1001:1001) (1111:1111:1111)) - (PORT datac (655:655:655) (722:722:722)) - (PORT datad (1242:1242:1242) (1330:1330:1330)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (789:789:789) (798:798:798)) - (PORT datab (653:653:653) (676:676:676)) - (PORT datac (834:834:834) (870:870:870)) - (PORT datad (1032:1032:1032) (1091:1091:1091)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (714:714:714) (749:749:749)) - (PORT datac (201:201:201) (236:236:236)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datac (180:180:180) (218:218:218)) - (PORT datad (538:538:538) (562:562:562)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1254:1254:1254) (1307:1307:1307)) - (PORT datab (845:845:845) (854:854:854)) - (PORT datac (835:835:835) (832:832:832)) - (PORT datad (874:874:874) (917:917:917)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT datac (727:727:727) (823:823:823)) + (PORT datad (308:308:308) (411:411:411)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -11609,1226 +1227,37 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[7\]) + (INSTANCE z80_\|interrupts_\|nmi_armed) (DELAY (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT clk (2148:2148:2148) (2241:2241:2241)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2152:2152:2152) (2220:2220:2220)) + (PORT clrn (1481:1481:1481) (1494:1494:1494)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) (DELAY (ABSOLUTE - (PORT dataa (407:407:407) (434:434:434)) - (PORT datab (1814:1814:1814) (1895:1895:1895)) - (PORT datac (201:201:201) (236:236:236)) - (PORT datad (644:644:644) (699:699:699)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT inclk[0] (2234:2234:2234) (2331:2331:2331)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~0) + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) (DELAY (ABSOLUTE - (PORT dataa (1218:1218:1218) (1307:1307:1307)) - (PORT datab (2009:2009:2009) (2129:2129:2129)) - (PORT datac (1296:1296:1296) (1407:1407:1407)) - (PORT datad (2028:2028:2028) (2149:2149:2149)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT datab (1470:1470:1470) (1557:1557:1557)) + (PORT datad (1650:1650:1650) (1825:1825:1825)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (412:412:412)) - (PORT datab (213:213:213) (258:258:258)) - (PORT datac (1100:1100:1100) (1149:1149:1149)) - (PORT datad (1205:1205:1205) (1229:1229:1229)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (1709:1709:1709) (1797:1797:1797)) - (PORT datac (549:549:549) (562:562:562)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) - (DELAY - (ABSOLUTE - (PORT datab (988:988:988) (1021:1021:1021)) - (PORT datac (1126:1126:1126) (1145:1145:1145)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1002:1002:1002) (1072:1072:1072)) - (PORT datad (1126:1126:1126) (1143:1143:1143)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) - (DELAY - (ABSOLUTE - (PORT datab (1546:1546:1546) (1602:1602:1602)) - (PORT datac (1206:1206:1206) (1268:1268:1268)) - (PORT datad (1073:1073:1073) (1099:1099:1099)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) - (DELAY - (ABSOLUTE - (PORT datab (1543:1543:1543) (1602:1602:1602)) - (PORT datac (1215:1215:1215) (1279:1279:1279)) - (PORT datad (985:985:985) (1033:1033:1033)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) - (DELAY - (ABSOLUTE - (PORT datab (1542:1542:1542) (1602:1602:1602)) - (PORT datac (1217:1217:1217) (1279:1279:1279)) - (PORT datad (1074:1074:1074) (1100:1100:1100)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1413:1413:1413) (1448:1448:1448)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) - (DELAY - (ABSOLUTE - (PORT datab (1547:1547:1547) (1607:1607:1607)) - (PORT datac (1199:1199:1199) (1261:1261:1261)) - (PORT datad (990:990:990) (1037:1037:1037)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1413:1413:1413) (1447:1447:1447)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (916:916:916)) - (PORT datab (971:971:971) (1024:1024:1024)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) - (DELAY - (ABSOLUTE - (PORT datab (1381:1381:1381) (1428:1428:1428)) - (PORT datac (1185:1185:1185) (1207:1207:1207)) - (PORT datad (589:589:589) (605:605:605)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (726:726:726) (753:753:753)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (407:407:407)) - (PORT datab (224:224:224) (272:272:272)) - (PORT datac (222:222:222) (301:301:301)) - (PORT datad (1218:1218:1218) (1299:1299:1299)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) - (DELAY - (ABSOLUTE - (PORT datab (1209:1209:1209) (1234:1234:1234)) - (PORT datac (637:637:637) (665:665:665)) - (PORT datad (1346:1346:1346) (1393:1393:1393)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT datab (1212:1212:1212) (1239:1239:1239)) - (PORT datac (637:637:637) (665:665:665)) - (PORT datad (1342:1342:1342) (1391:1391:1391)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (725:725:725) (752:752:752)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (261:261:261) (314:314:314)) - (PORT datad (232:232:232) (270:270:270)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) - (DELAY - (ABSOLUTE - (PORT datac (898:898:898) (941:941:941)) - (PORT datad (1326:1326:1326) (1381:1381:1381)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (770:770:770)) - (PORT datab (1175:1175:1175) (1215:1215:1215)) - (PORT datac (195:195:195) (238:238:238)) - (PORT datad (1436:1436:1436) (1519:1519:1519)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1192:1192:1192) (1227:1227:1227)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (765:765:765)) - (PORT datab (1172:1172:1172) (1214:1214:1214)) - (PORT datac (195:195:195) (237:237:237)) - (PORT datad (1438:1438:1438) (1518:1518:1518)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1193:1193:1193) (1225:1225:1225)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (467:467:467) (505:505:505)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (640:640:640) (663:663:663)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (658:658:658)) - (PORT datab (950:950:950) (994:994:994)) - (PORT datad (672:672:672) (698:698:698)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1673:1673:1673) (1678:1678:1678)) - (PORT ena (1499:1499:1499) (1507:1507:1507)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (674:674:674)) - (PORT datab (1409:1409:1409) (1424:1424:1424)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1144:1144:1144) (1180:1180:1180)) - (PORT datab (1171:1171:1171) (1213:1213:1213)) - (PORT datac (195:195:195) (238:238:238)) - (PORT datad (664:664:664) (715:715:715)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1225:1225:1225) (1263:1263:1263)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (962:962:962)) - (PORT datab (414:414:414) (473:473:473)) - (PORT datac (913:913:913) (963:963:963)) - (PORT datad (609:609:609) (629:629:629)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) - (DELAY - (ABSOLUTE - (PORT dataa (896:896:896) (973:973:973)) - (PORT datab (938:938:938) (1019:1019:1019)) - (PORT datac (1135:1135:1135) (1179:1179:1179)) - (PORT datad (378:378:378) (412:412:412)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) - (DELAY - (ABSOLUTE - (PORT datab (929:929:929) (993:993:993)) - (PORT datac (1324:1324:1324) (1357:1357:1357)) - (PORT datad (891:891:891) (947:947:947)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1168:1168:1168) (1265:1265:1265)) - (PORT datab (1178:1178:1178) (1216:1216:1216)) - (PORT datac (195:195:195) (239:239:239)) - (PORT datad (671:671:671) (719:719:719)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1674:1674:1674) (1676:1676:1676)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) - (DELAY - (ABSOLUTE - (PORT dataa (1791:1791:1791) (1805:1805:1805)) - (PORT datab (916:916:916) (986:986:986)) - (PORT datad (905:905:905) (958:958:958)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1226:1226:1226) (1265:1265:1265)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (433:433:433) (465:465:465)) - (PORT datab (634:634:634) (665:665:665)) - (PORT datad (357:357:357) (410:410:410)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) - (DELAY - (ABSOLUTE - (PORT dataa (1721:1721:1721) (1780:1780:1780)) - (PORT datab (1171:1171:1171) (1225:1225:1225)) - (PORT datad (792:792:792) (797:797:797)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1407:1407:1407) (1434:1434:1434)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (841:841:841) (868:868:868)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT datab (1032:1032:1032) (1065:1065:1065)) - (PORT datac (905:905:905) (951:951:951)) - (PORT datad (876:876:876) (937:937:937)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (407:407:407) (468:468:468)) - (PORT datab (590:590:590) (630:630:630)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (530:530:530) (540:540:540)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (699:699:699)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datad (780:780:780) (810:810:810)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (397:397:397)) - (PORT datab (625:625:625) (654:654:654)) - (PORT datac (1393:1393:1393) (1416:1416:1416)) - (PORT datad (618:618:618) (673:673:673)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1402:1402:1402) (1441:1441:1441)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (264:264:264)) - (PORT datab (1232:1232:1232) (1270:1270:1270)) - (PORT datad (658:658:658) (688:688:688)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (671:671:671) (703:703:703)) - (PORT datac (1147:1147:1147) (1188:1188:1188)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1460:1460:1460) (1492:1492:1492)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1460:1460:1460) (1491:1491:1491)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (262:262:262) (315:315:315)) - (PORT datad (233:233:233) (271:271:271)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT asdata (1185:1185:1185) (1213:1213:1213)) - (PORT ena (816:816:816) (813:813:813)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|db\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1227:1227:1227)) - (PORT datab (1541:1541:1541) (1602:1602:1602)) - (PORT datad (1074:1074:1074) (1100:1100:1100)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1483:1483:1483) (1519:1519:1519)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (688:688:688)) - (PORT datab (1088:1088:1088) (1097:1097:1097)) - (PORT datad (940:940:940) (980:980:980)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1236:1236:1236) (1247:1247:1247)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1237:1237:1237) (1246:1246:1246)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (696:696:696)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (367:367:367) (395:395:395)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1461:1461:1461) (1534:1534:1534)) - (PORT ena (1505:1505:1505) (1518:1518:1518)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (347:347:347) (372:372:372)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1458:1458:1458) (1530:1530:1530)) - (PORT ena (1407:1407:1407) (1382:1382:1382)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (430:430:430) (499:499:499)) - (PORT datab (652:652:652) (676:676:676)) - (PORT datad (827:827:827) (837:837:837)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1212:1212:1212) (1256:1256:1256)) - (PORT datab (919:919:919) (944:944:944)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (939:939:939) (964:964:964)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (455:455:455) (491:491:491)) - (PORT datab (1133:1133:1133) (1178:1178:1178)) - (PORT datad (539:539:539) (559:559:559)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1719:1719:1719) (1765:1765:1765)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1719:1719:1719) (1768:1768:1768)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (470:470:470)) - (PORT datab (585:585:585) (623:623:623)) - (PORT datad (216:216:216) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (635:635:635)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (344:344:344) (368:368:368)) - (PORT datad (597:597:597) (607:607:607)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1201:1201:1201) (1235:1235:1235)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (1104:1104:1104) (1151:1151:1151)) - (PORT datad (820:820:820) (839:839:839)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1589:1589:1589) (1608:1608:1608)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1178:1178:1178) (1198:1198:1198)) - (PORT datab (697:697:697) (724:724:724)) - (PORT datad (1194:1194:1194) (1230:1230:1230)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT datab (243:243:243) (325:325:325)) - (PORT datac (706:706:706) (737:737:737)) - (PORT datad (842:842:842) (876:876:876)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) - (DELAY - (ABSOLUTE - (PORT dataa (938:938:938) (985:985:985)) - (PORT datab (912:912:912) (985:985:985)) - (PORT datac (1500:1500:1500) (1547:1547:1547)) - (PORT datad (662:662:662) (730:730:730)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -12842,105 +1271,14 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~14) - (DELAY - (ABSOLUTE - (PORT datab (1393:1393:1393) (1462:1462:1462)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (265:265:265) (352:352:352)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~2) - (DELAY - (ABSOLUTE - (PORT datac (830:830:830) (872:872:872)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~18) - (DELAY - (ABSOLUTE - (PORT datad (660:660:660) (722:722:722)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~1) - (DELAY - (ABSOLUTE - (PORT datab (230:230:230) (272:272:272)) - (PORT datad (560:560:560) (588:588:588)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~0) (DELAY (ABSOLUTE - (PORT datab (1071:1071:1071) (1110:1110:1110)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (670:670:670) (741:741:741)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -12950,8 +1288,8 @@ (INSTANCE ula_\|video_\|vga_hc\~3) (DELAY (ABSOLUTE - (PORT datac (830:830:830) (865:865:865)) - (PORT datad (903:903:903) (941:941:941)) + (PORT datac (372:372:372) (407:407:407)) + (PORT datad (630:630:630) (642:642:642)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -12962,7 +1300,7 @@ (INSTANCE ula_\|video_\|vga_hc\[0\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) + (PORT clk (1540:1540:1540) (1552:1552:1552)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -12976,7 +1314,7 @@ (INSTANCE ula_\|video_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (672:672:672) (727:727:727)) + (PORT datab (460:460:460) (524:524:524)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -12990,7 +1328,7 @@ (INSTANCE ula_\|video_\|vga_hc\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (590:590:590) (612:612:612)) + (PORT datad (330:330:330) (344:344:344)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13000,7 +1338,7 @@ (INSTANCE ula_\|video_\|vga_hc\[1\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13014,7 +1352,7 @@ (INSTANCE ula_\|video_\|Add0\~4) (DELAY (ABSOLUTE - (PORT datab (410:410:410) (485:485:485)) + (PORT datab (411:411:411) (488:488:488)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13028,8 +1366,8 @@ (INSTANCE ula_\|video_\|vga_hc\[2\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) - (PORT asdata (663:663:663) (679:679:679)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (865:865:865) (873:873:873)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13042,37 +1380,27 @@ (INSTANCE ula_\|video_\|Add0\~6) (DELAY (ABSOLUTE - (PORT datab (693:693:693) (745:745:745)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (643:643:643) (698:698:698)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (558:558:558) (581:581:581)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|vga_hc\[3\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (870:870:870) (883:883:883)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL @@ -13080,7 +1408,7 @@ (INSTANCE ula_\|video_\|Add0\~8) (DELAY (ABSOLUTE - (PORT dataa (1094:1094:1094) (1127:1127:1127)) + (PORT dataa (642:642:642) (711:711:711)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13094,8 +1422,104 @@ (INSTANCE ula_\|video_\|vga_hc\[4\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) - (PORT asdata (662:662:662) (678:678:678)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (876:876:876) (877:877:877)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT datab (827:827:827) (881:881:881)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\~0) + (DELAY + (ABSOLUTE + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (626:626:626) (651:651:651)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (518:518:518) (549:549:549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (1373:1373:1373) (1418:1418:1418)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (658:658:658) (673:673:673)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (731:731:731)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (1457:1457:1457) (1474:1474:1474)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13108,10 +1532,10 @@ (INSTANCE ula_\|video_\|Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (1251:1251:1251) (1340:1340:1340)) - (PORT datab (983:983:983) (1062:1062:1062)) - (PORT datac (978:978:978) (1050:1050:1050)) - (PORT datad (282:282:282) (366:366:366)) + (PORT dataa (442:442:442) (542:542:542)) + (PORT datab (973:973:973) (1044:1044:1044)) + (PORT datac (708:708:708) (773:773:773)) + (PORT datad (740:740:740) (794:794:794)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -13124,39 +1548,24 @@ (INSTANCE ula_\|video_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (687:687:687) (737:737:737)) - (PORT datab (1394:1394:1394) (1464:1464:1464)) - (PORT datad (941:941:941) (937:937:937)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (523:523:523)) - (PORT datab (684:684:684) (758:758:758)) - (PORT datac (646:646:646) (716:716:716)) - (PORT datad (570:570:570) (576:576:576)) + (PORT dataa (1238:1238:1238) (1307:1307:1307)) + (PORT datab (920:920:920) (963:963:963)) + (PORT datac (651:651:651) (705:705:705)) + (PORT datad (174:174:174) (200:200:200)) (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~10) + (INSTANCE ula_\|video_\|Add0\~16) (DELAY (ABSOLUTE - (PORT dataa (684:684:684) (734:734:734)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (1079:1079:1079) (1140:1140:1140)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -13166,22 +1575,130 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~0) + (INSTANCE ula_\|video_\|vga_hc\~2) (DELAY (ABSOLUTE - (PORT datac (833:833:833) (875:875:875)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datad (626:626:626) (651:651:651)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[5\]) + (INSTANCE ula_\|video_\|vga_hc\[8\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (868:868:868) (876:876:876)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datab (265:265:265) (348:348:348)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\~1) + (DELAY + (ABSOLUTE + (PORT datab (344:344:344) (377:377:377)) + (PORT datad (627:627:627) (653:653:653)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (1429:1429:1429) (1430:1430:1430)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (269:269:269)) + (PORT datab (1253:1253:1253) (1334:1334:1334)) + (PORT datac (909:909:909) (963:963:963)) + (PORT datad (873:873:873) (928:928:928)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1244:1244:1244) (1316:1316:1316)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (711:711:711) (769:769:769)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (703:703:703)) + (PORT datab (1503:1503:1503) (1521:1521:1521)) + (PORT datad (594:594:594) (607:607:607)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1552:1552:1552)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13190,82 +1707,14 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~12) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (686:686:686)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) - (PORT asdata (516:516:516) (547:547:547)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) - (PORT asdata (869:869:869) (872:872:872)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~0) - (DELAY - (ABSOLUTE - (PORT datab (720:720:720) (795:795:795)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~2) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (782:782:782)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~4) (DELAY (ABSOLUTE - (PORT dataa (679:679:679) (747:747:747)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (678:678:678) (738:738:738)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -13277,9 +1726,9 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (517:517:517) (564:564:564)) - (PORT datab (595:595:595) (609:609:609)) - (PORT datad (899:899:899) (922:922:922)) + (PORT dataa (657:657:657) (705:705:705)) + (PORT datab (638:638:638) (664:664:664)) + (PORT datad (1466:1466:1466) (1485:1485:1485)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -13292,7 +1741,7 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1541:1541:1541) (1552:1552:1552)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13306,9 +1755,9 @@ (INSTANCE ula_\|video_\|Add1\~6) (DELAY (ABSOLUTE - (PORT dataa (712:712:712) (782:782:782)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (704:704:704) (764:764:764)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -13320,13 +1769,12 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (616:616:616) (648:648:648)) - (PORT datab (645:645:645) (692:692:692)) - (PORT datac (679:679:679) (747:747:747)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (654:654:654) (701:701:701)) + (PORT datab (1504:1504:1504) (1520:1520:1520)) + (PORT datad (597:597:597) (611:611:611)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13336,13 +1784,13 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1361:1361:1361) (1352:1352:1352)) + (PORT clk (1541:1541:1541) (1552:1552:1552)) + (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) ) ) (CELL @@ -13350,9 +1798,9 @@ (INSTANCE ula_\|video_\|Add1\~8) (DELAY (ABSOLUTE - (PORT datab (680:680:680) (762:762:762)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (965:965:965) (1008:1008:1008)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -13364,9 +1812,9 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]\~5) (DELAY (ABSOLUTE - (PORT dataa (516:516:516) (565:565:565)) - (PORT datab (625:625:625) (643:643:643)) - (PORT datad (899:899:899) (921:921:921)) + (PORT dataa (653:653:653) (704:704:704)) + (PORT datab (669:669:669) (683:683:683)) + (PORT datad (1464:1464:1464) (1484:1484:1484)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -13379,7 +1827,7 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1541:1541:1541) (1552:1552:1552)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13393,9 +1841,9 @@ (INSTANCE ula_\|video_\|Add1\~10) (DELAY (ABSOLUTE - (PORT dataa (690:690:690) (785:785:785)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (735:735:735) (804:804:804)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -13407,13 +1855,12 @@ (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) (DELAY (ABSOLUTE - (PORT dataa (616:616:616) (645:645:645)) - (PORT datab (645:645:645) (689:689:689)) - (PORT datac (698:698:698) (778:778:778)) - (PORT datad (175:175:175) (199:199:199)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (660:660:660) (706:706:706)) + (PORT datab (1508:1508:1508) (1524:1524:1524)) + (PORT datad (585:585:585) (600:600:600)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13423,13 +1870,13 @@ (INSTANCE ula_\|video_\|vga_vc\[5\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (884:884:884) (883:883:883)) + (PORT clk (1541:1541:1541) (1552:1552:1552)) + (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) ) ) (CELL @@ -13437,9 +1884,9 @@ (INSTANCE ula_\|video_\|Add1\~12) (DELAY (ABSOLUTE - (PORT datab (720:720:720) (789:789:789)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (966:966:966) (1010:1010:1010)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -13451,11 +1898,11 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]\~4) (DELAY (ABSOLUTE - (PORT dataa (519:519:519) (562:562:562)) - (PORT datab (588:588:588) (607:607:607)) - (PORT datad (902:902:902) (917:917:917)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (701:701:701) (726:726:726)) + (PORT datab (586:586:586) (616:616:616)) + (PORT datad (775:775:775) (772:772:772)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13466,7 +1913,7 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13480,7 +1927,7 @@ (INSTANCE ula_\|video_\|Add1\~14) (DELAY (ABSOLUTE - (PORT datab (691:691:691) (762:762:762)) + (PORT datab (965:965:965) (1025:1025:1025)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13494,9 +1941,9 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]\~6) (DELAY (ABSOLUTE - (PORT dataa (517:517:517) (566:566:566)) - (PORT datab (1177:1177:1177) (1178:1178:1178)) - (PORT datad (900:900:900) (920:920:920)) + (PORT dataa (699:699:699) (723:723:723)) + (PORT datab (1070:1070:1070) (1068:1068:1068)) + (PORT datad (558:558:558) (576:576:576)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -13509,7 +1956,7 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13523,7 +1970,7 @@ (INSTANCE ula_\|video_\|Add1\~16) (DELAY (ABSOLUTE - (PORT datab (743:743:743) (817:817:817)) + (PORT datab (954:954:954) (1004:1004:1004)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13537,9 +1984,9 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]\~7) (DELAY (ABSOLUTE - (PORT dataa (517:517:517) (558:558:558)) - (PORT datab (998:998:998) (1000:1000:1000)) - (PORT datad (899:899:899) (916:916:916)) + (PORT dataa (700:700:700) (726:726:726)) + (PORT datab (1128:1128:1128) (1126:1126:1126)) + (PORT datad (558:558:558) (578:578:578)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -13552,7 +1999,7 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13566,7 +2013,7 @@ (INSTANCE ula_\|video_\|Add1\~18) (DELAY (ABSOLUTE - (PORT datad (650:650:650) (707:707:707)) + (PORT datad (644:644:644) (702:702:702)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -13577,11 +2024,11 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]\~9) (DELAY (ABSOLUTE - (PORT dataa (518:518:518) (565:565:565)) - (PORT datab (1005:1005:1005) (1007:1007:1007)) - (PORT datad (899:899:899) (922:922:922)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (702:702:702) (724:724:724)) + (PORT datab (586:586:586) (613:613:613)) + (PORT datad (781:781:781) (782:782:782)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13592,7 +2039,7 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13603,31 +2050,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal2\~0) + (INSTANCE ula_\|video_\|Equal3\~0) (DELAY (ABSOLUTE - (PORT dataa (272:272:272) (361:361:361)) - (PORT datab (270:270:270) (356:356:356)) - (PORT datac (263:263:263) (343:343:343)) - (PORT datad (244:244:244) (317:317:317)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (282:282:282) (378:378:378)) + (PORT datab (715:715:715) (775:775:775)) + (PORT datac (648:648:648) (714:714:714)) + (PORT datad (1179:1179:1179) (1245:1245:1245)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal3\~0) + (INSTANCE ula_\|video_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (1173:1173:1173) (1262:1262:1262)) - (PORT datab (846:846:846) (922:922:922)) - (PORT datac (628:628:628) (679:679:679)) - (PORT datad (673:673:673) (746:746:746)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (426:426:426) (493:493:493)) + (PORT datab (290:290:290) (374:374:374)) + (PORT datac (250:250:250) (333:333:333)) + (PORT datad (421:421:421) (482:482:482)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13638,13 +2085,13 @@ (INSTANCE ula_\|video_\|Equal3\~1) (DELAY (ABSOLUTE - (PORT dataa (635:635:635) (701:701:701)) - (PORT datab (664:664:664) (725:725:725)) - (PORT datac (564:564:564) (582:582:582)) - (PORT datad (306:306:306) (321:321:321)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (400:400:400) (484:484:484)) + (PORT datab (873:873:873) (896:896:896)) + (PORT datac (620:620:620) (674:674:674)) + (PORT datad (590:590:590) (603:603:603)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13654,11 +2101,11 @@ (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (518:518:518) (561:561:561)) - (PORT datab (553:553:553) (567:567:567)) - (PORT datad (900:900:900) (915:915:915)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (653:653:653) (704:704:704)) + (PORT datab (1503:1503:1503) (1523:1523:1523)) + (PORT datad (313:313:313) (333:333:333)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13669,7 +2116,7 @@ (INSTANCE ula_\|video_\|vga_vc\[0\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1541:1541:1541) (1552:1552:1552)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13680,32 +2127,33 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (INSTANCE ula_\|video_\|Equal2\~1) (DELAY (ABSOLUTE - (PORT dataa (516:516:516) (560:560:560)) - (PORT datab (566:566:566) (575:575:575)) - (PORT datad (899:899:899) (916:916:916)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (414:414:414) (488:488:488)) + (PORT datab (715:715:715) (775:775:775)) + (PORT datac (648:648:648) (712:712:712)) + (PORT datad (372:372:372) (442:442:442)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[1\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal2\~2) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT dataa (345:345:345) (385:385:385)) + (PORT datac (620:620:620) (674:674:674)) + (PORT datad (591:591:591) (604:604:604)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_io_ibuf") @@ -13721,10 +2169,10 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13\~0) (DELAY (ABSOLUTE - (PORT dataa (1420:1420:1420) (1497:1497:1497)) - (PORT datab (716:716:716) (801:801:801)) - (PORT datac (1844:1844:1844) (1733:1733:1733)) - (PORT datad (677:677:677) (732:732:732)) + (PORT dataa (919:919:919) (997:997:997)) + (PORT datab (946:946:946) (1004:1004:1004)) + (PORT datac (905:905:905) (970:970:970)) + (PORT datad (1292:1292:1292) (1213:1213:1213)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -13734,15 +2182,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal79\~0) + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) (DELAY (ABSOLUTE - (PORT dataa (1251:1251:1251) (1348:1348:1348)) - (PORT datab (976:976:976) (1034:1034:1034)) - (PORT datac (1637:1637:1637) (1758:1758:1758)) - (PORT datad (1191:1191:1191) (1306:1306:1306)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT datac (1393:1393:1393) (1460:1460:1460)) + (PORT datad (1899:1899:1899) (2006:2006:2006)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13750,50 +2194,55 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) + (INSTANCE z80_\|execute_\|ctl_mWrite\~4) (DELAY (ABSOLUTE - (PORT dataa (1500:1500:1500) (1602:1602:1602)) - (PORT datab (361:361:361) (391:391:391)) - (PORT datad (665:665:665) (720:720:720)) + (PORT dataa (784:784:784) (852:852:852)) + (PORT datab (1496:1496:1496) (1609:1609:1609)) + (PORT datac (1839:1839:1839) (1973:1973:1973)) + (PORT datad (1690:1690:1690) (1763:1763:1763)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1772:1772:1772) (1878:1878:1878)) + (PORT datad (331:331:331) (359:359:359)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M3_ff\~0) + (DELAY + (ABSOLUTE + (PORT dataa (408:408:408) (485:485:485)) + (PORT datab (707:707:707) (759:759:759)) + (PORT datad (898:898:898) (912:912:912)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (495:495:495)) - (PORT datab (2014:2014:2014) (2140:2140:2140)) - (PORT datad (275:275:275) (358:358:358)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (1586:1586:1586) (1625:1625:1625)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) + (INSTANCE z80_\|sequencer_\|DFFE_M3_ff) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1553:1553:1553)) + (PORT clk (1525:1525:1525) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1552:1552:1552) (1543:1543:1543)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -13804,31 +2253,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~0) + (INSTANCE z80_\|execute_\|ixy_d\~6) (DELAY (ABSOLUTE - (PORT dataa (706:706:706) (765:765:765)) - (PORT datab (266:266:266) (349:349:349)) - (PORT datac (204:204:204) (241:241:241)) - (PORT datad (1456:1456:1456) (1550:1550:1550)) + (PORT dataa (1418:1418:1418) (1546:1546:1546)) + (PORT datad (934:934:934) (1041:1041:1041)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla12M3T3_3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1912:1912:1912) (2001:2001:2001)) + (PORT datab (207:207:207) (250:250:250)) + (PORT datac (622:622:622) (681:681:681)) + (PORT datad (1605:1605:1605) (1758:1758:1758)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1287:1287:1287) (1330:1330:1330)) - (PORT datab (266:266:266) (349:349:349)) - (PORT datac (888:888:888) (913:913:913)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13836,631 +2281,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) + (INSTANCE z80_\|pla_decode_\|Equal33\~0) (DELAY (ABSOLUTE - (PORT datab (1431:1431:1431) (1492:1492:1492)) - (PORT datac (1518:1518:1518) (1551:1551:1551)) - (PORT datad (1267:1267:1267) (1335:1335:1335)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|iff1) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1403:1403:1403) (1412:1412:1412)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1600:1600:1600) (1657:1657:1657)) - (PORT datab (843:843:843) (917:917:917)) - (PORT datac (633:633:633) (688:688:688)) - (PORT datad (427:427:427) (498:498:498)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (565:565:565) (583:583:583)) - (PORT datad (436:436:436) (516:516:516)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) - (DELAY - (ABSOLUTE - (PORT dataa (1175:1175:1175) (1240:1240:1240)) - (PORT datab (630:630:630) (645:645:645)) - (PORT datac (1541:1541:1541) (1636:1636:1636)) - (PORT datad (848:848:848) (861:861:861)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|int_armed) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1542:1542:1542)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1562:1562:1562) (1552:1552:1552)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|DFFE_inst44) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1552:1552:1552)) - (PORT asdata (2158:2158:2158) (2284:2284:2284)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (1669:1669:1669) (1678:1678:1678)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~38) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (487:487:487)) - (PORT datac (1180:1180:1180) (1261:1261:1261)) - (PORT datad (269:269:269) (350:350:350)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~91) - (DELAY - (ABSOLUTE - (PORT dataa (1671:1671:1671) (1790:1790:1790)) - (PORT datab (1251:1251:1251) (1347:1347:1347)) - (PORT datac (971:971:971) (1065:1065:1065)) - (PORT datad (862:862:862) (887:887:887)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1089:1089:1089) (1139:1139:1139)) - (PORT datab (699:699:699) (765:765:765)) - (PORT datac (1191:1191:1191) (1271:1271:1271)) - (PORT datad (626:626:626) (668:668:668)) + (PORT dataa (1771:1771:1771) (1874:1874:1874)) + (PORT datab (1642:1642:1642) (1796:1796:1796)) + (PORT datad (1883:1883:1883) (1955:1955:1955)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~44) + (INSTANCE z80_\|execute_\|ctl_mRead\~5) (DELAY (ABSOLUTE - (PORT dataa (1090:1090:1090) (1140:1140:1140)) - (PORT datab (909:909:909) (981:981:981)) - (PORT datac (856:856:856) (898:898:898)) - (PORT datad (1096:1096:1096) (1107:1107:1107)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~46) - (DELAY - (ABSOLUTE - (PORT dataa (338:338:338) (372:372:372)) - (PORT datab (702:702:702) (770:770:770)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (1101:1101:1101) (1112:1112:1112)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1161:1161:1161) (1207:1207:1207)) - (PORT datab (884:884:884) (933:933:933)) - (PORT datac (1058:1058:1058) (1098:1098:1098)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~50) - (DELAY - (ABSOLUTE - (PORT dataa (830:830:830) (863:863:863)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1604:1604:1604) (1719:1719:1719)) - (PORT datad (2285:2285:2285) (2389:2389:2389)) + (PORT dataa (1549:1549:1549) (1644:1644:1644)) + (PORT datab (263:263:263) (310:310:310)) + (PORT datac (1465:1465:1465) (1503:1503:1503)) + (PORT datad (1184:1184:1184) (1237:1237:1237)) (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~33) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (276:276:276)) - (PORT datab (1151:1151:1151) (1219:1219:1219)) - (PORT datac (1080:1080:1080) (1126:1126:1126)) - (PORT datad (596:596:596) (629:629:629)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (1685:1685:1685) (1750:1750:1750)) - (PORT datab (623:623:623) (672:672:672)) - (PORT datac (1663:1663:1663) (1743:1743:1743)) - (PORT datad (1164:1164:1164) (1212:1212:1212)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (825:825:825)) - (PORT datab (672:672:672) (761:761:761)) - (PORT datac (1148:1148:1148) (1186:1186:1186)) - (PORT datad (212:212:212) (247:247:247)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1165:1165:1165)) - (PORT datab (850:850:850) (866:866:866)) - (PORT datac (1208:1208:1208) (1236:1236:1236)) - (PORT datad (822:822:822) (834:834:834)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1110:1110:1110) (1168:1168:1168)) - (PORT datab (622:622:622) (673:673:673)) - (PORT datac (209:209:209) (250:250:250)) - (PORT datad (1641:1641:1641) (1711:1711:1711)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~34) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (193:193:193) (238:238:238)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1149:1149:1149) (1191:1191:1191)) - (PORT datab (1399:1399:1399) (1505:1505:1505)) - (PORT datac (2514:2514:2514) (2618:2618:2618)) - (PORT datad (1497:1497:1497) (1611:1611:1611)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~30) - (DELAY - (ABSOLUTE - (PORT dataa (691:691:691) (738:738:738)) - (PORT datab (1144:1144:1144) (1210:1210:1210)) - (PORT datac (365:365:365) (393:393:393)) - (PORT datad (865:865:865) (890:890:890)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1521:1521:1521) (1648:1648:1648)) - (PORT datab (1395:1395:1395) (1501:1501:1501)) - (PORT datac (2518:2518:2518) (2621:2621:2621)) - (PORT datad (1054:1054:1054) (1086:1086:1086)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~35) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (406:406:406)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (619:619:619) (652:652:652)) - (PORT datad (179:179:179) (207:207:207)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1104:1104:1104) (1123:1123:1123)) - (PORT datab (643:643:643) (662:662:662)) - (PORT datac (625:625:625) (646:646:646)) - (PORT datad (1379:1379:1379) (1419:1419:1419)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) - (DELAY - (ABSOLUTE - (PORT dataa (2071:2071:2071) (2185:2185:2185)) - (PORT datab (910:910:910) (981:981:981)) - (PORT datac (1397:1397:1397) (1483:1483:1483)) - (PORT datad (646:646:646) (677:677:677)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (1333:1333:1333) (1437:1437:1437)) - (PORT datab (1764:1764:1764) (1881:1881:1881)) - (PORT datad (630:630:630) (685:685:685)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (266:266:266)) - (PORT datab (216:216:216) (261:261:261)) - (PORT datac (670:670:670) (716:716:716)) - (PORT datad (570:570:570) (590:590:590)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1409:1409:1409) (1454:1454:1454)) - (PORT datab (666:666:666) (697:697:697)) - (PORT datac (1989:1989:1989) (2085:2085:2085)) - (PORT datad (1246:1246:1246) (1294:1294:1294)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (635:635:635) (682:682:682)) - (PORT datad (190:190:190) (223:223:223)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (421:421:421)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (637:637:637) (672:672:672)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (722:722:722)) - (PORT datab (699:699:699) (766:766:766)) - (PORT datac (639:639:639) (671:671:671)) - (PORT datad (1153:1153:1153) (1224:1224:1224)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1647:1647:1647) (1764:1764:1764)) - (PORT datab (1067:1067:1067) (1136:1136:1136)) - (PORT datac (612:612:612) (631:631:631)) - (PORT datad (973:973:973) (1058:1058:1058)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~39) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (264:264:264)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (623:623:623) (647:647:647)) - (PORT datad (565:565:565) (585:585:585)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~47) - (DELAY - (ABSOLUTE - (PORT dataa (399:399:399) (422:422:422)) - (PORT datab (212:212:212) (257:257:257)) - (PORT datac (620:620:620) (677:677:677)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (881:881:881) (895:895:895)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) - (DELAY - (ABSOLUTE - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (636:636:636) (661:661:661)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (257:257:257)) - (PORT datab (341:341:341) (376:376:376)) - (PORT datac (639:639:639) (674:674:674)) - (PORT datad (182:182:182) (213:213:213)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (725:725:725)) - (PORT datab (911:911:911) (985:985:985)) - (PORT datac (1190:1190:1190) (1272:1272:1272)) - (PORT datad (188:188:188) (220:220:220)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) - (DELAY - (ABSOLUTE - (PORT dataa (868:868:868) (915:915:915)) - (PORT datab (682:682:682) (741:741:741)) - (PORT datac (965:965:965) (1027:1027:1027)) - (PORT datad (621:621:621) (668:668:668)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14468,281 +2311,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) + (INSTANCE z80_\|pla_decode_\|Equal77\~0) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (684:684:684) (749:749:749)) - (PORT datac (972:972:972) (1033:1033:1033)) - (PORT datad (1668:1668:1668) (1690:1690:1690)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (255:255:255)) - (PORT datab (340:340:340) (370:370:370)) - (PORT datac (638:638:638) (672:672:672)) - (PORT datad (357:357:357) (377:377:377)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) - (DELAY - (ABSOLUTE - (PORT datab (205:205:205) (245:245:245)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (180:180:180) (207:207:207)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~42) - (DELAY - (ABSOLUTE - (PORT datab (652:652:652) (687:687:687)) - (PORT datac (339:339:339) (370:370:370)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~90) - (DELAY - (ABSOLUTE - (PORT dataa (1017:1017:1017) (1099:1099:1099)) - (PORT datab (1086:1086:1086) (1123:1123:1123)) - (PORT datac (1171:1171:1171) (1232:1232:1232)) - (PORT datad (1497:1497:1497) (1611:1611:1611)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~41) - (DELAY - (ABSOLUTE - (PORT dataa (227:227:227) (279:279:279)) - (PORT datab (627:627:627) (674:674:674)) - (PORT datac (208:208:208) (246:246:246)) - (PORT datad (180:180:180) (207:207:207)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (494:494:494)) - (PORT datab (902:902:902) (935:935:935)) - (PORT datac (1178:1178:1178) (1261:1261:1261)) - (PORT datad (273:273:273) (355:355:355)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1166:1166:1166)) - (PORT datab (227:227:227) (270:270:270)) - (PORT datac (194:194:194) (242:242:242)) - (PORT datad (872:872:872) (923:923:923)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) - (DELAY - (ABSOLUTE - (PORT dataa (1443:1443:1443) (1505:1505:1505)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (1642:1642:1642) (1712:1712:1712)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) - (DELAY - (ABSOLUTE - (PORT dataa (1110:1110:1110) (1166:1166:1166)) - (PORT datab (235:235:235) (278:278:278)) - (PORT datac (195:195:195) (241:241:241)) - (PORT datad (596:596:596) (630:630:630)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (888:888:888)) - (PORT datab (1133:1133:1133) (1145:1145:1145)) - (PORT datac (343:343:343) (372:372:372)) - (PORT datad (854:854:854) (886:886:886)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) - (DELAY - (ABSOLUTE - (PORT dataa (1157:1157:1157) (1221:1221:1221)) - (PORT datab (375:375:375) (398:398:398)) - (PORT datac (308:308:308) (325:325:325)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (330:330:330) (348:348:348)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) - (DELAY - (ABSOLUTE - (PORT dataa (663:663:663) (715:715:715)) - (PORT datab (410:410:410) (440:440:440)) - (PORT datac (1131:1131:1131) (1156:1156:1156)) - (PORT datad (854:854:854) (887:887:887)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) - (DELAY - (ABSOLUTE - (PORT dataa (663:663:663) (719:719:719)) - (PORT datab (946:946:946) (985:985:985)) - (PORT datac (1123:1123:1123) (1165:1165:1165)) - (PORT datad (1721:1721:1721) (1778:1778:1778)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (395:395:395)) - (PORT datab (1129:1129:1129) (1184:1184:1184)) - (PORT datac (1040:1040:1040) (1054:1054:1054)) - (PORT datad (1204:1204:1204) (1229:1229:1229)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (717:717:717)) - (PORT datab (921:921:921) (959:959:959)) - (PORT datac (913:913:913) (949:949:949)) - (PORT datad (313:313:313) (331:331:331)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) - (DELAY - (ABSOLUTE - (PORT dataa (902:902:902) (981:981:981)) - (PORT datab (893:893:893) (932:932:932)) - (PORT datac (1434:1434:1434) (1470:1470:1470)) - (PORT datad (843:843:843) (890:890:890)) + (PORT dataa (787:787:787) (855:855:855)) + (PORT datab (770:770:770) (837:837:837)) + (PORT datac (1831:1831:1831) (1966:1966:1966)) + (PORT datad (1685:1685:1685) (1757:1757:1757)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -14752,15 +2327,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) + (INSTANCE z80_\|pla_decode_\|Equal50\~0) (DELAY (ABSOLUTE - (PORT dataa (1466:1466:1466) (1512:1512:1512)) - (PORT datab (915:915:915) (968:968:968)) - (PORT datac (321:321:321) (356:356:356)) - (PORT datad (174:174:174) (200:200:200)) + (PORT dataa (1231:1231:1231) (1295:1295:1295)) + (PORT datac (924:924:924) (977:977:977)) + (PORT datad (1184:1184:1184) (1237:1237:1237)) (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14768,109 +2341,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (280:280:280)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (588:588:588) (601:601:601)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) - (DELAY - (ABSOLUTE - (PORT dataa (1188:1188:1188) (1234:1234:1234)) - (PORT datab (1144:1144:1144) (1214:1214:1214)) - (PORT datac (364:364:364) (396:396:396)) - (PORT datad (1141:1141:1141) (1188:1188:1188)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1132:1132:1132)) - (PORT datab (1153:1153:1153) (1193:1193:1193)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) - (DELAY - (ABSOLUTE - (PORT dataa (956:956:956) (987:987:987)) - (PORT datab (921:921:921) (959:959:959)) - (PORT datac (635:635:635) (676:676:676)) - (PORT datad (1543:1543:1543) (1626:1626:1626)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) - (DELAY - (ABSOLUTE - (PORT dataa (457:457:457) (498:498:498)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (805:805:805) (826:826:826)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~89) - (DELAY - (ABSOLUTE - (PORT dataa (1333:1333:1333) (1437:1437:1437)) - (PORT datab (1163:1163:1163) (1169:1169:1169)) - (PORT datac (1430:1430:1430) (1469:1469:1469)) - (PORT datad (844:844:844) (894:894:894)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (254:254:254)) - (PORT datab (828:828:828) (830:830:830)) - (PORT datac (314:314:314) (333:333:333)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (642:642:642) (713:713:713)) + (PORT datac (679:679:679) (726:726:726)) + (PORT datad (895:895:895) (912:912:912)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14878,15 +2355,115 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) (DELAY (ABSOLUTE - (PORT dataa (907:907:907) (937:937:937)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (590:590:590) (602:602:602)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (1354:1354:1354) (1515:1515:1515)) + (PORT datab (2217:2217:2217) (2404:2404:2404)) + (PORT datac (387:387:387) (452:452:452)) + (PORT datad (308:308:308) (411:411:411)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1590:1590:1590) (1567:1567:1567)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|DFF_inst5\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1182:1182:1182) (1247:1247:1247)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|DFF_inst5) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (344:344:344)) + (PORT datad (1180:1180:1180) (1243:1243:1243)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT ena (1243:1243:1243) (1234:1234:1234)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) + (DELAY + (ABSOLUTE + (PORT datab (1537:1537:1537) (1637:1637:1637)) + (PORT datac (1180:1180:1180) (1248:1248:1248)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1204:1204:1204) (1263:1263:1263)) + (PORT datab (1222:1222:1222) (1236:1236:1236)) + (PORT datac (2271:2271:2271) (2399:2399:2399)) + (PORT datad (364:364:364) (396:396:396)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14894,16 +2471,505 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) + (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) (DELAY (ABSOLUTE - (PORT dataa (1157:1157:1157) (1220:1220:1220)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (563:563:563) (566:566:566)) - (PORT datad (559:559:559) (582:582:582)) - (IOPATH dataa combout (337:337:337) (338:338:338)) + (PORT dataa (2287:2287:2287) (2396:2396:2396)) + (PORT datab (2178:2178:2178) (2359:2359:2359)) + (PORT datac (1216:1216:1216) (1300:1300:1300)) + (PORT datad (874:874:874) (939:939:939)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_inst4) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1565:1565:1565) (1545:1545:1545)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~3) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (434:434:434)) + (PORT datab (224:224:224) (271:271:271)) + (PORT datac (1000:1000:1000) (1080:1080:1080)) + (PORT datad (1503:1503:1503) (1556:1556:1556)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M4_ff\~0) + (DELAY + (ABSOLUTE + (PORT dataa (420:420:420) (502:502:502)) + (PORT datab (708:708:708) (757:757:757)) + (PORT datad (899:899:899) (915:915:915)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M4_ff) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2484:2484:2484) (2682:2682:2682)) + (PORT datab (1562:1562:1562) (1651:1651:1651)) + (PORT datac (1193:1193:1193) (1280:1280:1280)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2561:2561:2561) (2633:2633:2633)) + (PORT datac (2429:2429:2429) (2625:2625:2625)) + (PORT datad (1838:1838:1838) (1929:1929:1929)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1982:1982:1982) (2048:2048:2048)) + (PORT datab (2103:2103:2103) (2239:2239:2239)) + (PORT datac (1465:1465:1465) (1540:1540:1540)) + (PORT datad (209:209:209) (246:246:246)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~4) + (DELAY + (ABSOLUTE + (PORT datab (2490:2490:2490) (2690:2690:2690)) + (PORT datac (2152:2152:2152) (2252:2252:2252)) + (PORT datad (1470:1470:1470) (1560:1560:1560)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (722:722:722)) + (PORT datac (1428:1428:1428) (1511:1511:1511)) + (PORT datad (659:659:659) (735:735:735)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~5) + (DELAY + (ABSOLUTE + (PORT datac (590:590:590) (659:659:659)) + (PORT datad (661:661:661) (738:738:738)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~2) + (DELAY + (ABSOLUTE + (PORT datab (1181:1181:1181) (1258:1258:1258)) + (PORT datac (1491:1491:1491) (1604:1604:1604)) + (PORT datad (1204:1204:1204) (1275:1275:1275)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~2) + (DELAY + (ABSOLUTE + (PORT datab (1624:1624:1624) (1780:1780:1780)) + (PORT datad (1680:1680:1680) (1802:1802:1802)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~11) + (DELAY + (ABSOLUTE + (PORT dataa (2561:2561:2561) (2630:2630:2630)) + (PORT datab (2468:2468:2468) (2666:2666:2666)) + (PORT datac (1469:1469:1469) (1544:1544:1544)) + (PORT datad (1838:1838:1838) (1932:1932:1932)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (258:258:258) (308:308:308)) + (PORT datab (897:897:897) (907:907:907)) + (PORT datac (1280:1280:1280) (1332:1332:1332)) + (PORT datad (793:793:793) (839:839:839)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT datab (1654:1654:1654) (1808:1808:1808)) + (PORT datad (1815:1815:1815) (1894:1894:1894)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|table_xx\~0) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (501:501:501)) + (PORT datad (247:247:247) (319:319:319)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1699:1699:1699) (1795:1795:1795)) + (PORT datab (1125:1125:1125) (1202:1202:1202)) + (PORT datac (896:896:896) (937:937:937)) + (PORT datad (1966:1966:1966) (2037:2037:2037)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~0) + (DELAY + (ABSOLUTE + (PORT datac (1044:1044:1044) (1135:1135:1135)) + (PORT datad (1269:1269:1269) (1357:1357:1357)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1067:1067:1067)) + (PORT datab (1506:1506:1506) (1576:1576:1576)) + (PORT datac (1078:1078:1078) (1094:1094:1094)) + (PORT datad (201:201:201) (229:229:229)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~3) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1081:1081:1081)) + (PORT datab (741:741:741) (845:845:845)) + (PORT datac (909:909:909) (983:983:983)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~5) + (DELAY + (ABSOLUTE + (PORT datac (705:705:705) (809:809:809)) + (PORT datad (697:697:697) (796:796:796)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (681:681:681)) + (PORT datab (640:640:640) (663:663:663)) + (PORT datac (341:341:341) (362:362:362)) + (PORT datad (609:609:609) (621:621:621)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (1625:1625:1625) (1667:1667:1667)) + (PORT datad (616:616:616) (648:648:648)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (922:922:922)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datac (1049:1049:1049) (1089:1089:1089)) + (PORT datad (1211:1211:1211) (1321:1321:1321)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~3) + (DELAY + (ABSOLUTE + (PORT datab (745:745:745) (845:845:845)) + (PORT datac (970:970:970) (1032:1032:1032)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT datab (1607:1607:1607) (1747:1747:1747)) + (PORT datad (1859:1859:1859) (1958:1958:1958)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (236:236:236) (286:286:286)) + (PORT datab (1368:1368:1368) (1395:1395:1395)) + (PORT datac (1649:1649:1649) (1746:1746:1746)) + (PORT datad (1692:1692:1692) (1750:1750:1750)) + (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~4) + (DELAY + (ABSOLUTE + (PORT datac (667:667:667) (737:737:737)) + (PORT datad (669:669:669) (753:753:753)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~0) + (DELAY + (ABSOLUTE + (PORT datac (1044:1044:1044) (1136:1136:1136)) + (PORT datad (1269:1269:1269) (1359:1359:1359)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2136:2136:2136) (2306:2306:2306)) + (PORT datab (1472:1472:1472) (1496:1496:1496)) + (PORT datac (1120:1120:1120) (1150:1150:1150)) + (PORT datad (648:648:648) (671:671:671)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1142:1142:1142) (1181:1181:1181)) + (PORT datab (899:899:899) (952:952:952)) + (PORT datac (1409:1409:1409) (1473:1473:1473)) + (PORT datad (637:637:637) (678:678:678)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1859:1859:1859) (1941:1941:1941)) + (PORT datab (1653:1653:1653) (1803:1803:1803)) + (PORT datac (1713:1713:1713) (1796:1796:1796)) + (PORT datad (879:879:879) (896:896:896)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) + (DELAY + (ABSOLUTE + (PORT datab (1578:1578:1578) (1721:1721:1721)) + (PORT datac (1756:1756:1756) (1850:1850:1850)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1417:1417:1417) (1491:1491:1491)) + (PORT datab (1499:1499:1499) (1601:1601:1601)) + (PORT datac (1236:1236:1236) (1278:1278:1278)) + (PORT datad (1212:1212:1212) (1250:1250:1250)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -14911,1393 +2977,14 @@ (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1096:1096:1096) (1139:1139:1139)) - (PORT datab (213:213:213) (256:256:256)) - (PORT datac (1061:1061:1061) (1099:1099:1099)) - (PORT datad (189:189:189) (222:222:222)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) - (DELAY - (ABSOLUTE - (PORT dataa (1618:1618:1618) (1736:1736:1736)) - (PORT datab (867:867:867) (905:905:905)) - (PORT datac (2517:2517:2517) (2622:2622:2622)) - (PORT datad (1493:1493:1493) (1607:1607:1607)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (611:611:611)) - (PORT datab (580:580:580) (593:593:593)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1133:1133:1133) (1184:1184:1184)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~40) - (DELAY - (ABSOLUTE - (PORT datab (652:652:652) (686:686:686)) - (PORT datac (338:338:338) (369:369:369)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (277:277:277)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (1058:1058:1058) (1099:1099:1099)) - (PORT datad (1134:1134:1134) (1161:1161:1161)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) - (DELAY - (ABSOLUTE - (PORT dataa (1157:1157:1157) (1225:1225:1225)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (551:551:551) (564:564:564)) - (PORT datad (399:399:399) (430:430:430)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (169:169:169) (201:201:201)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1138:1138:1138)) - (PORT datab (1105:1105:1105) (1122:1122:1122)) - (PORT datac (1065:1065:1065) (1088:1088:1088)) - (PORT datad (1172:1172:1172) (1217:1217:1217)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) - (DELAY - (ABSOLUTE - (PORT datac (700:700:700) (784:784:784)) - (PORT datad (365:365:365) (386:386:386)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (958:958:958) (1001:1001:1001)) - (PORT datac (681:681:681) (720:720:720)) - (PORT datad (339:339:339) (361:361:361)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[0\]) - (DELAY - (ABSOLUTE - (PORT datac (1006:1006:1006) (1012:1012:1012)) - (PORT datad (924:924:924) (943:943:943)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (179:179:179) (207:207:207)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2096:2096:2096) (2133:2133:2133)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) - (DELAY - (ABSOLUTE - (PORT dataa (1158:1158:1158) (1184:1184:1184)) - (PORT datab (989:989:989) (1022:1022:1022)) - (PORT datac (696:696:696) (778:778:778)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (985:985:985) (1033:1033:1033)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (396:396:396)) - (PORT datab (697:697:697) (726:726:726)) - (PORT datad (1194:1194:1194) (1231:1231:1231)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (740:740:740) (774:774:774)) - (PORT datac (217:217:217) (294:294:294)) - (PORT datad (608:608:608) (657:657:657)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (905:905:905)) - (PORT datab (402:402:402) (425:425:425)) - (PORT datac (194:194:194) (227:227:227)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (244:244:244)) - (PORT datab (959:959:959) (1000:1000:1000)) - (PORT datac (683:683:683) (721:721:721)) - (PORT datad (341:341:341) (359:359:359)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[1\]) - (DELAY - (ABSOLUTE - (PORT datab (396:396:396) (421:421:421)) - (PORT datad (345:345:345) (371:371:371)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT asdata (537:537:537) (568:568:568)) - (PORT clrn (1597:1597:1597) (1572:1572:1572)) - (PORT ena (2143:2143:2143) (2210:2210:2210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1005:1005:1005) (1069:1069:1069)) - (PORT datab (1154:1154:1154) (1178:1178:1178)) - (PORT datac (812:812:812) (866:866:866)) - (PORT datad (359:359:359) (383:383:383)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (443:443:443)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (236:236:236) (311:311:311)) - (PORT datad (327:327:327) (348:348:348)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (716:716:716) (758:758:758)) - (PORT datab (962:962:962) (1001:1001:1001)) - (PORT datac (617:617:617) (670:670:670)) - (PORT datad (532:532:532) (544:544:544)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (553:553:553) (579:579:579)) - (PORT datad (214:214:214) (247:247:247)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (195:195:195) (220:220:220)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1597:1597:1597) (1572:1572:1572)) - (PORT ena (2146:2146:2146) (2210:2210:2210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) - (DELAY - (ABSOLUTE - (PORT dataa (386:386:386) (424:424:424)) - (PORT datab (1154:1154:1154) (1182:1182:1182)) - (PORT datac (966:966:966) (1033:1033:1033)) - (PORT datad (394:394:394) (449:449:449)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (179:179:179) (208:208:208)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (441:441:441)) - (PORT datab (1103:1103:1103) (1121:1121:1121)) - (PORT datac (1068:1068:1068) (1079:1079:1079)) - (PORT datad (1177:1177:1177) (1222:1222:1222)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1182:1182:1182)) - (PORT datab (983:983:983) (1021:1021:1021)) - (PORT datac (960:960:960) (1025:1025:1025)) - (PORT datad (1127:1127:1127) (1138:1138:1138)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (846:846:846) (907:907:907)) - (PORT datab (1376:1376:1376) (1400:1400:1400)) - (PORT datac (695:695:695) (778:778:778)) - (PORT datad (369:369:369) (389:389:389)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) - (DELAY - (ABSOLUTE - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (331:331:331) (357:357:357)) - (PORT datad (244:244:244) (316:316:316)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1394:1394:1394) (1425:1425:1425)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1396:1396:1396) (1427:1427:1427)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (413:413:413) (478:478:478)) - (PORT datab (593:593:593) (633:633:633)) - (PORT datad (219:219:219) (288:288:288)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (815:815:815) (857:857:857)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1407:1407:1407) (1382:1382:1382)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1165:1165:1165) (1197:1197:1197)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (678:678:678)) - (PORT datab (842:842:842) (870:870:870)) - (PORT datad (643:643:643) (672:672:672)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1201:1201:1201) (1243:1243:1243)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1200:1200:1200) (1247:1247:1247)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (705:705:705)) - (PORT datab (245:245:245) (328:328:328)) - (PORT datad (369:369:369) (400:400:400)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (812:812:812) (855:855:855)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1505:1505:1505) (1518:1518:1518)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1168:1168:1168) (1200:1200:1200)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (934:934:934) (963:963:963)) - (PORT datab (606:606:606) (617:617:617)) - (PORT datac (548:548:548) (570:570:570)) - (PORT datad (1519:1519:1519) (1633:1633:1633)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (968:968:968) (1020:1020:1020)) - (PORT datab (580:580:580) (595:595:595)) - (PORT datac (1000:1000:1000) (1021:1021:1021)) - (PORT datad (861:861:861) (896:896:896)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (681:681:681) (737:737:737)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (542:542:542) (562:562:562)) - (PORT datab (612:612:612) (638:638:638)) - (PORT datac (854:854:854) (888:888:888)) - (PORT datad (607:607:607) (635:635:635)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (687:687:687)) - (PORT datab (643:643:643) (681:681:681)) - (PORT datac (1161:1161:1161) (1210:1210:1210)) - (PORT datad (581:581:581) (616:616:616)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (255:255:255)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (603:603:603) (634:634:634)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) - (DELAY - (ABSOLUTE - (PORT datab (1437:1437:1437) (1505:1505:1505)) - (PORT datac (1211:1211:1211) (1273:1273:1273)) - (PORT datad (849:849:849) (886:886:886)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT datab (1435:1435:1435) (1506:1506:1506)) - (PORT datac (1214:1214:1214) (1277:1277:1277)) - (PORT datad (841:841:841) (870:870:870)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) - (DELAY - (ABSOLUTE - (PORT datab (1431:1431:1431) (1499:1499:1499)) - (PORT datac (1202:1202:1202) (1265:1265:1265)) - (PORT datad (842:842:842) (868:868:868)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1009:1009:1009) (1065:1065:1065)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) - (DELAY - (ABSOLUTE - (PORT datab (1431:1431:1431) (1500:1500:1500)) - (PORT datac (1204:1204:1204) (1267:1267:1267)) - (PORT datad (851:851:851) (887:887:887)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1012:1012:1012) (1067:1067:1067)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (523:523:523)) - (PORT datab (490:490:490) (541:541:541)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) - (DELAY - (ABSOLUTE - (PORT datab (1436:1436:1436) (1501:1501:1501)) - (PORT datac (1209:1209:1209) (1271:1271:1271)) - (PORT datad (1072:1072:1072) (1103:1103:1103)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) - (DELAY - (ABSOLUTE - (PORT datab (1436:1436:1436) (1506:1506:1506)) - (PORT datac (1213:1213:1213) (1276:1276:1276)) - (PORT datad (987:987:987) (1036:1036:1036)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1181:1181:1181) (1200:1200:1200)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) - (DELAY - (ABSOLUTE - (PORT datab (1437:1437:1437) (1502:1502:1502)) - (PORT datac (1212:1212:1212) (1275:1275:1275)) - (PORT datad (1074:1074:1074) (1101:1101:1101)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1183:1183:1183) (1203:1203:1203)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) - (DELAY - (ABSOLUTE - (PORT datab (1438:1438:1438) (1503:1503:1503)) - (PORT datac (1218:1218:1218) (1279:1279:1279)) - (PORT datad (985:985:985) (1032:1032:1032)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (988:988:988)) - (PORT datab (242:242:242) (325:325:325)) - (PORT datad (882:882:882) (948:948:948)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) - (DELAY - (ABSOLUTE - (PORT datab (1221:1221:1221) (1292:1292:1292)) - (PORT datac (894:894:894) (941:941:941)) - (PORT datad (886:886:886) (945:945:945)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1204:1204:1204) (1243:1243:1243)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (936:936:936) (997:997:997)) - (PORT datab (1221:1221:1221) (1285:1285:1285)) - (PORT datad (879:879:879) (935:935:935)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1180:1180:1180) (1217:1217:1217)) - (PORT datab (204:204:204) (246:246:246)) - (PORT datac (1821:1821:1821) (1898:1898:1898)) - (PORT datad (203:203:203) (239:239:239)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (899:899:899)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (601:601:601) (662:662:662)) - (PORT datad (870:870:870) (912:912:912)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) - (DELAY - (ABSOLUTE - (PORT dataa (1473:1473:1473) (1527:1527:1527)) - (PORT datac (833:833:833) (838:838:838)) - (PORT datad (1122:1122:1122) (1157:1157:1157)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (981:981:981) (1026:1026:1026)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) - (DELAY - (ABSOLUTE - (PORT dataa (1475:1475:1475) (1527:1527:1527)) - (PORT datac (835:835:835) (838:838:838)) - (PORT datad (1125:1125:1125) (1158:1158:1158)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1083:1083:1083) (1099:1099:1099)) - (PORT datab (1166:1166:1166) (1217:1217:1217)) - (PORT datad (239:239:239) (279:279:279)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (656:656:656) (709:709:709)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) - (DELAY - (ABSOLUTE - (PORT datab (1122:1122:1122) (1149:1149:1149)) - (PORT datac (1397:1397:1397) (1448:1448:1448)) - (PORT datad (822:822:822) (857:857:857)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (987:987:987)) - (PORT datab (1220:1220:1220) (1288:1288:1288)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (403:403:403) (454:454:454)) - (PORT datab (944:944:944) (1025:1025:1025)) - (PORT datac (1146:1146:1146) (1186:1186:1186)) - (PORT datad (666:666:666) (686:686:686)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) - (DELAY - (ABSOLUTE - (PORT datac (1438:1438:1438) (1484:1484:1484)) - (PORT datad (1123:1123:1123) (1155:1155:1155)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1170:1170:1170) (1265:1265:1265)) - (PORT datab (813:813:813) (832:832:832)) - (PORT datac (1134:1134:1134) (1171:1171:1171)) - (PORT datad (664:664:664) (713:713:713)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1504:1504:1504) (1545:1545:1545)) - (PORT ena (1131:1131:1131) (1098:1098:1098)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) - (DELAY - (ABSOLUTE - (PORT datab (1121:1121:1121) (1148:1148:1148)) - (PORT datac (1398:1398:1398) (1447:1447:1447)) - (PORT datad (821:821:821) (856:856:856)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (453:453:453)) - (PORT datab (887:887:887) (923:923:923)) - (PORT datad (364:364:364) (388:388:388)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) - (DELAY - (ABSOLUTE - (PORT dataa (408:408:408) (464:464:464)) - (PORT datab (1404:1404:1404) (1437:1437:1437)) - (PORT datac (1139:1139:1139) (1179:1179:1179)) - (PORT datad (663:663:663) (683:683:683)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1146:1146:1146) (1180:1180:1180)) - (PORT datab (815:815:815) (833:833:833)) - (PORT datac (1143:1143:1143) (1180:1180:1180)) - (PORT datad (671:671:671) (721:721:721)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1782:1782:1782) (1906:1906:1906)) - (PORT datab (973:973:973) (1022:1022:1022)) - (PORT datac (1471:1471:1471) (1489:1489:1489)) - (PORT datad (1978:1978:1978) (2013:2013:2013)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (660:660:660)) - (PORT datab (1249:1249:1249) (1275:1275:1275)) - (PORT datac (1822:1822:1822) (1900:1900:1900)) - (PORT datad (1106:1106:1106) (1134:1134:1134)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (687:687:687)) - (PORT datab (905:905:905) (971:971:971)) - (PORT datac (861:861:861) (888:888:888)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) (DELAY (ABSOLUTE (PORT dataa (208:208:208) (256:256:256)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1153:1153:1153) (1178:1178:1178)) - (PORT datad (204:204:204) (241:241:241)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT datab (1120:1120:1120) (1175:1175:1175)) + (PORT datac (1695:1695:1695) (1735:1735:1735)) + (PORT datad (989:989:989) (1018:1018:1018)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16305,134 +2992,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) + (INSTANCE z80_\|pla_decode_\|Equal19\~0) (DELAY (ABSOLUTE - (PORT dataa (713:713:713) (766:766:766)) - (PORT datab (205:205:205) (245:245:245)) - (PORT datac (346:346:346) (370:370:370)) - (PORT datad (1145:1145:1145) (1176:1176:1176)) + (PORT dataa (889:889:889) (948:948:948)) + (PORT datab (683:683:683) (708:708:708)) + (PORT datac (2084:2084:2084) (2256:2256:2256)) + (PORT datad (909:909:909) (931:931:931)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) - (DELAY - (ABSOLUTE - (PORT datab (922:922:922) (944:944:944)) - (PORT datac (595:595:595) (615:615:615)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (900:900:900)) - (PORT datac (1144:1144:1144) (1163:1163:1163)) - (PORT datad (832:832:832) (861:861:861)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1506:1506:1506) (1545:1545:1545)) - (PORT ena (1261:1261:1261) (1299:1299:1299)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) - (DELAY - (ABSOLUTE - (PORT dataa (874:874:874) (899:899:899)) - (PORT datac (1138:1138:1138) (1159:1159:1159)) - (PORT datad (835:835:835) (861:861:861)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1100:1100:1100) (1149:1149:1149)) - (PORT datab (1280:1280:1280) (1386:1386:1386)) - (PORT datad (842:842:842) (869:869:869)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (693:693:693)) - (PORT datab (1259:1259:1259) (1346:1346:1346)) - (PORT datac (1146:1146:1146) (1187:1187:1187)) - (PORT datad (374:374:374) (412:412:412)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (990:990:990) (1035:1035:1035)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) + (INSTANCE z80_\|pla_decode_\|Equal34\~0) (DELAY (ABSOLUTE - (PORT dataa (404:404:404) (462:462:462)) - (PORT datab (1258:1258:1258) (1341:1341:1341)) - (PORT datac (1142:1142:1142) (1186:1186:1186)) - (PORT datad (664:664:664) (686:686:686)) + (PORT dataa (1700:1700:1700) (1791:1791:1791)) + (PORT datab (250:250:250) (300:300:300)) + (PORT datac (899:899:899) (937:937:937)) + (PORT datad (928:928:928) (989:989:989)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -16442,1198 +3024,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) + (INSTANCE z80_\|execute_\|comb\~0) (DELAY (ABSOLUTE - (PORT dataa (639:639:639) (696:696:696)) - (PORT datab (1255:1255:1255) (1339:1339:1339)) - (PORT datac (1141:1141:1141) (1184:1184:1184)) - (PORT datad (375:375:375) (413:413:413)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (989:989:989) (1035:1035:1035)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (402:402:402) (457:457:457)) - (PORT datab (1258:1258:1258) (1344:1344:1344)) - (PORT datac (1146:1146:1146) (1187:1187:1187)) - (PORT datad (666:666:666) (682:682:682)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (1659:1659:1659) (1811:1811:1811)) + (PORT datad (1814:1814:1814) (1891:1891:1891)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~42) + (INSTANCE z80_\|pla_decode_\|Equal47\~0) (DELAY (ABSOLUTE - (PORT dataa (423:423:423) (485:485:485)) - (PORT datab (1600:1600:1600) (1653:1653:1653)) - (PORT datad (1181:1181:1181) (1221:1221:1221)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (634:634:634)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (787:787:787) (785:785:785)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (623:623:623) (653:653:653)) - (PORT datab (336:336:336) (368:368:368)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (626:626:626) (642:642:642)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (988:988:988)) - (PORT datab (218:218:218) (257:257:257)) - (PORT datac (618:618:618) (661:661:661)) - (PORT datad (787:787:787) (791:791:791)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1064:1064:1064) (1103:1103:1103)) - (PORT datab (836:836:836) (868:868:868)) - (PORT datac (218:218:218) (261:261:261)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (671:671:671)) - (PORT datab (834:834:834) (892:892:892)) - (PORT datac (174:174:174) (207:207:207)) - (PORT datad (874:874:874) (899:899:899)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1547:1547:1547) (1564:1564:1564)) - (PORT datab (851:851:851) (910:910:910)) - (PORT datac (1130:1130:1130) (1151:1151:1151)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) - (DELAY - (ABSOLUTE - (PORT dataa (1308:1308:1308) (1399:1399:1399)) - (PORT datac (1141:1141:1141) (1164:1164:1164)) - (PORT datad (832:832:832) (866:866:866)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1187:1187:1187) (1229:1229:1229)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1186:1186:1186) (1227:1227:1227)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (460:460:460) (523:523:523)) - (PORT datab (492:492:492) (541:541:541)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1950:1950:1950) (1996:1996:1996)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (937:937:937) (991:991:991)) - (PORT datab (1222:1222:1222) (1291:1291:1291)) - (PORT datad (879:879:879) (935:935:935)) + (PORT dataa (1700:1700:1700) (1795:1795:1795)) + (PORT datab (250:250:250) (298:298:298)) + (PORT datac (898:898:898) (934:934:934)) + (PORT datad (1153:1153:1153) (1208:1208:1208)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (545:545:545) (579:579:579)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1716:1716:1716) (1767:1767:1767)) - (PORT ena (1261:1261:1261) (1299:1299:1299)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1098:1098:1098) (1151:1151:1151)) - (PORT datab (648:648:648) (728:728:728)) - (PORT datad (845:845:845) (876:876:876)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (2219:2219:2219) (2260:2260:2260)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (881:881:881)) - (PORT datab (1166:1166:1166) (1218:1218:1218)) - (PORT datad (240:240:240) (280:280:280)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1976:1976:1976) (2020:2020:2020)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1977:1977:1977) (2023:2023:2023)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (466:466:466)) - (PORT datab (1593:1593:1593) (1643:1643:1643)) - (PORT datad (1180:1180:1180) (1216:1216:1216)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1715:1715:1715) (1766:1766:1766)) - (PORT ena (1131:1131:1131) (1098:1098:1098)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1611:1611:1611) (1650:1650:1650)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (433:433:433)) - (PORT datab (886:886:886) (923:923:923)) - (PORT datad (859:859:859) (925:925:925)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (632:632:632) (649:649:649)) - (PORT datac (338:338:338) (358:358:358)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (2372:2372:2372) (2423:2423:2423)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (2371:2371:2371) (2423:2423:2423)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (926:926:926) (986:986:986)) - (PORT datab (911:911:911) (986:986:986)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (672:672:672)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (596:596:596) (613:613:613)) - (PORT datad (313:313:313) (323:323:323)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (944:944:944)) - (PORT datab (543:543:543) (563:563:563)) - (PORT datac (1049:1049:1049) (1102:1102:1102)) - (PORT datad (1297:1297:1297) (1338:1338:1338)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (911:911:911)) - (PORT datac (1138:1138:1138) (1159:1159:1159)) - (PORT datad (844:844:844) (869:869:869)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (909:909:909)) - (PORT datac (1140:1140:1140) (1164:1164:1164)) - (PORT datad (844:844:844) (871:871:871)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (1391:1391:1391) (1443:1443:1443)) - (PORT ena (935:935:935) (924:924:924)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1171:1171:1171) (1195:1195:1195)) - (PORT datab (835:835:835) (855:855:855)) - (PORT datac (1143:1143:1143) (1163:1163:1163)) - (PORT datad (844:844:844) (868:868:868)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (276:276:276)) - (PORT datab (409:409:409) (450:450:450)) - (PORT datad (382:382:382) (419:419:419)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) - (DELAY - (ABSOLUTE - (PORT dataa (1308:1308:1308) (1398:1398:1398)) - (PORT datac (1141:1141:1141) (1165:1165:1165)) - (PORT datad (832:832:832) (866:866:866)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datac (762:762:762) (815:815:815)) - (PORT datad (642:642:642) (666:666:666)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (239:239:239) (292:292:292)) - (PORT datab (235:235:235) (277:277:277)) - (PORT datac (1097:1097:1097) (1113:1113:1113)) - (PORT datad (212:212:212) (246:246:246)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (418:418:418) (508:508:508)) - (PORT datab (279:279:279) (364:364:364)) - (PORT datac (1332:1332:1332) (1337:1337:1337)) - (PORT datad (184:184:184) (216:216:216)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (842:842:842) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (951:951:951) (975:975:975)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (951:951:951) (974:974:974)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (978:978:978)) - (PORT datab (914:914:914) (989:989:989)) - (PORT datad (214:214:214) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1393:1393:1393) (1432:1432:1432)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1390:1390:1390) (1429:1429:1429)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (517:517:517)) - (PORT datab (496:496:496) (537:537:537)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1278:1278:1278) (1308:1308:1308)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1278:1278:1278) (1306:1306:1306)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (458:458:458)) - (PORT datab (1599:1599:1599) (1646:1646:1646)) - (PORT datad (1181:1181:1181) (1215:1215:1215)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1228:1228:1228) (1277:1277:1277)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1058:1058:1058) (1070:1070:1070)) - (PORT datab (1167:1167:1167) (1216:1216:1216)) - (PORT datad (237:237:237) (277:277:277)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (810:810:810) (862:862:862)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1214:1214:1214) (1210:1210:1210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1259:1259:1259) (1290:1290:1290)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (243:243:243) (289:289:289)) - (PORT datad (875:875:875) (901:901:901)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (689:689:689) (709:709:709)) - (PORT ena (1404:1404:1404) (1382:1382:1382)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1474:1474:1474) (1488:1488:1488)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1058:1058:1058) (1072:1072:1072)) - (PORT datab (1270:1270:1270) (1360:1360:1360)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (838:838:838) (872:872:872)) - (PORT datab (1030:1030:1030) (1072:1072:1072)) - (PORT datac (803:803:803) (856:856:856)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (969:969:969) (986:986:986)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (986:986:986)) - (PORT datab (1221:1221:1221) (1292:1292:1292)) - (PORT datad (887:887:887) (945:945:945)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (380:380:380) (429:429:429)) - (PORT datab (829:829:829) (880:880:880)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (558:558:558) (582:582:582)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (834:834:834) (864:864:864)) - (PORT datab (867:867:867) (903:903:903)) - (PORT datac (808:808:808) (862:862:862)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT asdata (881:881:881) (888:888:888)) - (PORT ena (940:940:940) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (288:288:288)) - (PORT datab (905:905:905) (941:941:941)) - (PORT datad (211:211:211) (245:245:245)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (288:288:288)) - (PORT datac (214:214:214) (290:290:290)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1135:1135:1135) (1153:1153:1153)) - (PORT datab (827:827:827) (837:837:837)) - (PORT datac (199:199:199) (234:234:234)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[8\]) - (DELAY - (ABSOLUTE - (PORT dataa (688:688:688) (733:733:733)) - (PORT datac (799:799:799) (817:817:817)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2152:2152:2152) (2220:2220:2220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (422:422:422) (513:513:513)) - (PORT datab (280:280:280) (369:369:369)) - (PORT datac (1329:1329:1329) (1334:1334:1334)) - (PORT datad (189:189:189) (221:221:221)) - (IOPATH dataa combout (301:301:301) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) - (DELAY - (ABSOLUTE - (PORT datac (248:248:248) (337:337:337)) - (PORT datad (324:324:324) (346:346:346)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (712:712:712) (756:756:756)) - (PORT datac (810:810:810) (842:842:842)) - (PORT datad (578:578:578) (586:586:586)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -17641,672 +3052,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[9\]) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) (DELAY (ABSOLUTE - (PORT datab (355:355:355) (385:385:385)) - (PORT datac (880:880:880) (911:911:911)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[9\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (554:554:554) (561:561:561)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2096:2096:2096) (2133:2133:2133)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (268:268:268) (364:364:364)) - (PORT datab (279:279:279) (374:374:374)) - (PORT datac (1335:1335:1335) (1349:1349:1349)) - (PORT datad (325:325:325) (343:343:343)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (1678:1678:1678) (1695:1695:1695)) + (PORT datab (1374:1374:1374) (1396:1396:1396)) + (PORT datac (2514:2514:2514) (2557:2557:2557)) + (PORT datad (1128:1128:1128) (1145:1145:1145)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1106:1106:1106) (1145:1145:1145)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1107:1107:1107) (1146:1146:1146)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~32) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) (DELAY (ABSOLUTE - (PORT dataa (921:921:921) (980:980:980)) - (PORT datab (914:914:914) (982:982:982)) - (PORT datad (216:216:216) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1947:1947:1947) (2004:2004:2004)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (812:812:812) (827:827:827)) - (PORT datab (1168:1168:1168) (1216:1216:1216)) - (PORT datad (240:240:240) (281:281:281)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1439:1439:1439) (1508:1508:1508)) - (PORT ena (1131:1131:1131) (1098:1098:1098)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (778:778:778) (850:850:850)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (433:433:433)) - (PORT datab (886:886:886) (923:923:923)) - (PORT datad (350:350:350) (406:406:406)) + (PORT dataa (889:889:889) (940:940:940)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datac (1113:1113:1113) (1189:1189:1189)) + (PORT datad (961:961:961) (1053:1053:1053)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1005:1005:1005) (1055:1055:1055)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1994:1994:1994) (2075:2075:2075)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (568:568:568) (641:641:641)) - (PORT datab (1599:1599:1599) (1649:1649:1649)) - (PORT datad (1179:1179:1179) (1219:1219:1219)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1439:1439:1439) (1506:1506:1506)) - (PORT ena (1261:1261:1261) (1299:1299:1299)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1100:1100:1100) (1147:1147:1147)) - (PORT datab (678:678:678) (753:753:753)) - (PORT datad (849:849:849) (878:878:878)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (653:653:653)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (599:599:599) (617:617:617)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (2176:2176:2176) (2269:2269:2269)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (2177:2177:2177) (2273:2273:2273)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (524:524:524)) - (PORT datab (243:243:243) (326:326:326)) - (PORT datad (454:454:454) (497:497:497)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (2201:2201:2201) (2285:2285:2285)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (990:990:990)) - (PORT datab (1220:1220:1220) (1290:1290:1290)) - (PORT datad (884:884:884) (941:941:941)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (773:773:773) (837:837:837)) - (PORT datab (560:560:560) (597:597:597)) - (PORT datac (558:558:558) (555:555:555)) - (PORT datad (850:850:850) (877:877:877)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (909:909:909)) - (PORT datab (396:396:396) (421:421:421)) - (PORT datac (848:848:848) (907:907:907)) - (PORT datad (1297:1297:1297) (1337:1337:1337)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT asdata (545:545:545) (579:579:579)) - (PORT ena (940:940:940) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1897:1897:1897) (1987:1987:1987)) - (PORT datab (235:235:235) (281:281:281)) - (PORT datad (211:211:211) (246:246:246)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (842:842:842) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (287:287:287)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datad (354:354:354) (413:413:413)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1139:1139:1139) (1156:1156:1156)) - (PORT datab (545:545:545) (561:561:561)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[10\]) - (DELAY - (ABSOLUTE - (PORT datac (200:200:200) (235:235:235)) - (PORT datad (869:869:869) (899:899:899)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[10\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (531:531:531) (546:546:546)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2096:2096:2096) (2133:2133:2133)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (270:270:270) (368:368:368)) - (PORT datab (276:276:276) (370:370:370)) - (PORT datac (1338:1338:1338) (1352:1352:1352)) - (PORT datad (324:324:324) (345:345:345)) - (IOPATH dataa combout (301:301:301) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[11\]) - (DELAY - (ABSOLUTE - (PORT datab (602:602:602) (632:632:632)) - (PORT datad (924:924:924) (945:945:945)) (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2096:2096:2096) (2133:2133:2133)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datac (568:568:568) (632:632:632)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (738:738:738) (772:772:772)) - (PORT ena (935:935:935) (924:924:924)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (407:407:407) (446:446:446)) - (PORT datad (388:388:388) (422:422:422)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (335:335:335)) - (PORT datac (823:823:823) (870:870:870)) - (PORT datad (639:639:639) (664:664:664)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (565:565:565) (577:577:577)) - (PORT datab (846:846:846) (883:883:883)) - (PORT datac (679:679:679) (728:728:728)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18314,106 +3084,69 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~48) + (INSTANCE z80_\|sequencer_\|M5\~0) (DELAY (ABSOLUTE - (PORT dataa (612:612:612) (644:644:644)) - (PORT datab (820:820:820) (880:880:880)) - (PORT datac (393:393:393) (430:430:430)) - (PORT datad (1301:1301:1301) (1333:1333:1333)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (872:872:872) (916:916:916)) - (PORT datab (223:223:223) (272:272:272)) - (PORT datac (1159:1159:1159) (1203:1203:1203)) - (PORT datad (607:607:607) (634:634:634)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) - (DELAY - (ABSOLUTE - (PORT dataa (1004:1004:1004) (1068:1068:1068)) - (PORT datab (2092:2092:2092) (2152:2152:2152)) - (PORT datac (686:686:686) (739:739:739)) - (PORT datad (1737:1737:1737) (1857:1857:1857)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT datab (964:964:964) (1009:1009:1009)) - (PORT datac (1166:1166:1166) (1163:1163:1163)) - (PORT datad (680:680:680) (717:717:717)) + (PORT dataa (442:442:442) (510:510:510)) + (PORT datab (706:706:706) (761:761:761)) + (PORT datad (892:892:892) (915:915:915)) + (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[3\]) + (INSTANCE z80_\|sequencer_\|M5) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) + (PORT clk (1525:1525:1525) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[3\]\~3) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) (DELAY (ABSOLUTE - (PORT datab (652:652:652) (711:711:711)) - (PORT datac (647:647:647) (707:707:707)) - (PORT datad (634:634:634) (661:661:661)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (980:980:980) (1079:1079:1079)) + (PORT datac (670:670:670) (776:776:776)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (2272:2272:2272) (2458:2458:2458)) + (PORT datad (1247:1247:1247) (1340:1340:1340)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) (DELAY (ABSOLUTE - (PORT dataa (638:638:638) (713:713:713)) - (PORT datab (641:641:641) (708:708:708)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (575:575:575) (599:599:599)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (643:643:643) (677:677:677)) + (PORT datab (1376:1376:1376) (1393:1393:1393)) + (PORT datac (1649:1649:1649) (1659:1659:1659)) + (PORT datad (908:908:908) (928:928:928)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -18422,15 +3155,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) + (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) (DELAY (ABSOLUTE - (PORT dataa (1127:1127:1127) (1169:1169:1169)) - (PORT datab (1268:1268:1268) (1379:1379:1379)) - (PORT datac (613:613:613) (634:634:634)) - (PORT datad (1131:1131:1131) (1134:1134:1134)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (890:890:890) (938:938:938)) + (PORT datab (348:348:348) (377:377:377)) + (PORT datac (614:614:614) (637:637:637)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18438,29 +3171,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) + (INSTANCE z80_\|execute_\|ctl_mRead\~4) (DELAY (ABSOLUTE - (PORT dataa (2003:2003:2003) (2192:2192:2192)) - (PORT datab (1271:1271:1271) (1346:1346:1346)) - (PORT datac (994:994:994) (1035:1035:1035)) - (PORT datad (1461:1461:1461) (1531:1531:1531)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1013:1013:1013) (1048:1048:1048)) - (PORT datab (1598:1598:1598) (1713:1713:1713)) - (PORT datac (1145:1145:1145) (1147:1147:1147)) - (PORT datad (654:654:654) (698:698:698)) + (PORT dataa (1325:1325:1325) (1382:1382:1382)) + (PORT datab (967:967:967) (991:991:991)) + (PORT datac (1402:1402:1402) (1542:1542:1542)) + (PORT datad (1180:1180:1180) (1240:1240:1240)) (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -18470,31 +3187,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~5) + (INSTANCE z80_\|execute_\|ctl_ir_we\~5) (DELAY (ABSOLUTE - (PORT dataa (2564:2564:2564) (2702:2702:2702)) - (PORT datab (1558:1558:1558) (1680:1680:1680)) - (PORT datac (866:866:866) (908:908:908)) - (PORT datad (191:191:191) (224:224:224)) + (PORT datab (260:260:260) (343:343:343)) + (PORT datac (234:234:234) (310:310:310)) + (PORT datad (391:391:391) (462:462:462)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (475:475:475) (503:503:503)) + (PORT datab (1696:1696:1696) (1768:1768:1768)) + (PORT datac (1831:1831:1831) (1963:1963:1963)) + (PORT datad (780:780:780) (842:842:842)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (475:475:475) (504:504:504)) + (PORT datab (1697:1697:1697) (1767:1767:1767)) + (PORT datac (1832:1832:1832) (1964:1964:1964)) + (PORT datad (781:781:781) (840:840:840)) (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (411:411:411)) - (PORT datab (804:804:804) (851:851:851)) - (PORT datac (829:829:829) (862:862:862)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18502,15 +3233,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) + (INSTANCE z80_\|execute_\|ctl_ir_we\~7) (DELAY (ABSOLUTE - (PORT dataa (647:647:647) (668:668:668)) - (PORT datab (1164:1164:1164) (1226:1226:1226)) - (PORT datac (562:562:562) (562:562:562)) - (PORT datad (595:595:595) (626:626:626)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (479:479:479) (505:505:505)) + (PORT datab (1700:1700:1700) (1770:1770:1770)) + (PORT datac (1842:1842:1842) (1975:1975:1975)) + (PORT datad (787:787:787) (845:845:845)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1450:1450:1450) (1501:1501:1501)) + (PORT datab (641:641:641) (679:679:679)) + (PORT datac (647:647:647) (693:693:693)) + (PORT datad (648:648:648) (679:679:679)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18518,149 +3265,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~5) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~97) (DELAY (ABSOLUTE - (PORT dataa (588:588:588) (616:616:616)) - (PORT datab (1125:1125:1125) (1173:1173:1173)) - (PORT datac (561:561:561) (579:579:579)) - (PORT datad (905:905:905) (952:952:952)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (702:702:702) (774:774:774)) + (PORT datab (1409:1409:1409) (1519:1519:1519)) + (PORT datac (1370:1370:1370) (1480:1480:1480)) + (PORT datad (682:682:682) (744:744:744)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~6) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~96) (DELAY (ABSOLUTE - (PORT dataa (258:258:258) (332:332:332)) - (PORT datac (170:170:170) (202:202:202)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) - (DELAY - (ABSOLUTE - (PORT dataa (263:263:263) (339:339:339)) - (PORT datac (1090:1090:1090) (1144:1144:1144)) - (PORT datad (902:902:902) (951:951:951)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT datab (968:968:968) (1010:1010:1010)) - (PORT datac (370:370:370) (404:404:404)) - (PORT datad (675:675:675) (715:715:715)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (733:733:733)) - (PORT datab (1128:1128:1128) (1182:1182:1182)) - (PORT datac (588:588:588) (620:620:620)) - (PORT datad (380:380:380) (439:439:439)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1172:1172:1172) (1272:1272:1272)) + (PORT datab (969:969:969) (1014:1014:1014)) + (PORT datac (672:672:672) (779:779:779)) + (PORT datad (693:693:693) (794:794:794)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~98) (DELAY (ABSOLUTE - (PORT dataa (264:264:264) (340:340:340)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (556:556:556) (578:578:578)) - (PORT datad (900:900:900) (949:949:949)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1468:1468:1468) (1479:1479:1479)) - (PORT datab (1497:1497:1497) (1572:1572:1572)) - (PORT datac (1847:1847:1847) (1915:1915:1915)) - (PORT datad (402:402:402) (438:438:438)) + (PORT dataa (1401:1401:1401) (1407:1407:1407)) + (PORT datab (1154:1154:1154) (1254:1254:1254)) + (PORT datac (671:671:671) (779:779:779)) + (PORT datad (693:693:693) (794:794:794)) (IOPATH dataa combout (325:325:325) (328:328:328)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -18670,251 +3313,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~20) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) (DELAY (ABSOLUTE - (PORT dataa (1433:1433:1433) (1518:1518:1518)) - (PORT datab (1643:1643:1643) (1769:1769:1769)) - (PORT datac (1052:1052:1052) (1102:1102:1102)) - (PORT datad (1294:1294:1294) (1385:1385:1385)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (2512:2512:2512) (2579:2579:2579)) + (PORT datab (239:239:239) (277:277:277)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (1711:1711:1711) (1689:1689:1689)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~12) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) (DELAY (ABSOLUTE - (PORT dataa (885:885:885) (898:898:898)) - (PORT datab (943:943:943) (983:983:983)) - (PORT datac (858:858:858) (877:877:877)) - (PORT datad (654:654:654) (664:664:664)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) - (DELAY - (ABSOLUTE - (PORT dataa (480:480:480) (518:518:518)) - (PORT datab (1187:1187:1187) (1249:1249:1249)) - (PORT datac (925:925:925) (1011:1011:1011)) - (PORT datad (1383:1383:1383) (1482:1482:1482)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal61\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1746:1746:1746) (1869:1869:1869)) - (PORT datab (1375:1375:1375) (1426:1426:1426)) - (PORT datac (1591:1591:1591) (1672:1672:1672)) - (PORT datad (1495:1495:1495) (1627:1627:1627)) + (PORT dataa (861:861:861) (935:935:935)) + (PORT datab (348:348:348) (381:381:381)) + (PORT datad (336:336:336) (362:362:362)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) + (INSTANCE z80_\|execute_\|fMWrite\~1) (DELAY (ABSOLUTE - (PORT datab (1828:1828:1828) (1926:1926:1926)) - (PORT datac (1699:1699:1699) (1792:1792:1792)) - (PORT datad (926:926:926) (994:994:994)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1872:1872:1872) (1889:1889:1889)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (880:880:880) (886:886:886)) - (PORT datad (803:803:803) (814:814:814)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1342:1342:1342) (1440:1440:1440)) - (PORT datab (1765:1765:1765) (1873:1873:1873)) - (PORT datac (1447:1447:1447) (1536:1536:1536)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1520:1520:1520) (1609:1609:1609)) - (PORT datab (925:925:925) (988:988:988)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (203:203:203) (232:232:232)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (262:262:262)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (177:177:177) (214:214:214)) - (PORT datad (182:182:182) (212:212:212)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1766:1766:1766) (1808:1808:1808)) - (PORT datab (836:836:836) (862:862:862)) - (PORT datac (1306:1306:1306) (1421:1421:1421)) - (PORT datad (2555:2555:2555) (2677:2677:2677)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) - (DELAY - (ABSOLUTE - (PORT dataa (582:582:582) (614:614:614)) - (PORT datab (246:246:246) (286:286:286)) - (PORT datac (221:221:221) (257:257:257)) - (PORT datad (904:904:904) (976:976:976)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1051:1051:1051) (1075:1075:1075)) - (PORT datab (1615:1615:1615) (1655:1655:1655)) - (PORT datac (1187:1187:1187) (1227:1227:1227)) - (PORT datad (1742:1742:1742) (1769:1769:1769)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal71\~2) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (921:921:921)) - (PORT datab (941:941:941) (1014:1014:1014)) - (PORT datac (219:219:219) (254:254:254)) - (PORT datad (903:903:903) (974:974:974)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (258:258:258)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1219:1219:1219) (1272:1272:1272)) - (PORT datab (227:227:227) (268:268:268)) - (PORT datac (2061:2061:2061) (2171:2171:2171)) - (PORT datad (1409:1409:1409) (1503:1503:1503)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (718:718:718)) - (PORT datab (1484:1484:1484) (1542:1542:1542)) - (PORT datac (1486:1486:1486) (1511:1511:1511)) - (PORT datad (640:640:640) (654:654:654)) + (PORT dataa (1633:1633:1633) (1765:1765:1765)) + (PORT datab (1559:1559:1559) (1648:1648:1648)) + (PORT datac (1677:1677:1677) (1756:1756:1756)) + (PORT datad (1743:1743:1743) (1852:1852:1852)) (IOPATH dataa combout (341:341:341) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -18924,384 +3359,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla25M1T1_3) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) (DELAY (ABSOLUTE - (PORT dataa (837:837:837) (857:857:857)) - (PORT datab (1485:1485:1485) (1542:1542:1542)) - (PORT datac (1608:1608:1608) (1613:1613:1613)) - (PORT datad (1444:1444:1444) (1563:1563:1563)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (213:213:213) (257:257:257)) - (PORT datac (838:838:838) (870:870:870)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (341:341:341) (319:319:319)) + (PORT dataa (1155:1155:1155) (1190:1190:1190)) + (PORT datab (1492:1492:1492) (1531:1531:1531)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (1070:1070:1070) (1092:1092:1092)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal72\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1402:1402:1402) (1477:1477:1477)) - (PORT datab (2359:2359:2359) (2492:2492:2492)) - (PORT datac (1132:1132:1132) (1171:1171:1171)) - (PORT datad (855:855:855) (857:857:857)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal73\~2) - (DELAY - (ABSOLUTE - (PORT dataa (2002:2002:2002) (2149:2149:2149)) - (PORT datab (1120:1120:1120) (1189:1189:1189)) - (PORT datac (1350:1350:1350) (1403:1403:1403)) - (PORT datad (855:855:855) (872:872:872)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (975:975:975) (1049:1049:1049)) - (PORT datab (960:960:960) (1047:1047:1047)) - (PORT datac (1782:1782:1782) (1803:1803:1803)) - (PORT datad (1450:1450:1450) (1533:1533:1533)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1044:1044:1044) (1059:1059:1059)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (616:616:616) (640:640:640)) - (PORT datad (601:601:601) (613:613:613)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1518:1518:1518) (1586:1586:1586)) - (PORT datab (1962:1962:1962) (1991:1991:1991)) - (PORT datac (1263:1263:1263) (1313:1313:1313)) - (PORT datad (933:933:933) (1002:1002:1002)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) - (DELAY - (ABSOLUTE - (PORT datab (864:864:864) (893:893:893)) - (PORT datac (819:819:819) (853:853:853)) - (PORT datad (811:811:811) (845:845:845)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (2565:2565:2565) (2704:2704:2704)) - (PORT datac (1529:1529:1529) (1648:1648:1648)) - (PORT datad (1533:1533:1533) (1667:1667:1667)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (304:304:304)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datac (1176:1176:1176) (1212:1212:1212)) - (PORT datad (191:191:191) (224:224:224)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (808:808:808) (859:859:859)) - (PORT datab (618:618:618) (647:647:647)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (802:802:802) (881:881:881)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~15) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (957:957:957)) - (PORT datac (824:824:824) (856:856:856)) - (PORT datad (647:647:647) (680:680:680)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~16) - (DELAY - (ABSOLUTE - (PORT dataa (912:912:912) (960:960:960)) - (PORT datab (362:362:362) (394:394:394)) - (PORT datac (591:591:591) (619:619:619)) - (PORT datad (338:338:338) (357:357:357)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) - (DELAY - (ABSOLUTE - (PORT datac (891:891:891) (933:933:933)) - (PORT datad (831:831:831) (843:843:843)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (649:649:649)) - (PORT datab (1105:1105:1105) (1114:1114:1114)) - (PORT datac (753:753:753) (781:781:781)) - (PORT datad (613:613:613) (631:631:631)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (917:917:917) (942:942:942)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2002:2002:2002) (2062:2062:2062)) - (PORT datab (228:228:228) (270:270:270)) - (PORT datac (1707:1707:1707) (1823:1823:1823)) - (PORT datad (1505:1505:1505) (1539:1539:1539)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1137:1137:1137) (1211:1211:1211)) - (PORT datab (1568:1568:1568) (1705:1705:1705)) - (PORT datac (2532:2532:2532) (2663:2663:2663)) - (PORT datad (189:189:189) (222:222:222)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1005:1005:1005) (1063:1063:1063)) - (PORT datab (1299:1299:1299) (1349:1349:1349)) - (PORT datac (890:890:890) (914:914:914)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (665:665:665)) - (PORT datab (2303:2303:2303) (2383:2383:2383)) - (PORT datac (2057:2057:2057) (2199:2199:2199)) - (PORT datad (1163:1163:1163) (1186:1186:1186)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (640:640:640)) - (PORT datab (608:608:608) (638:638:638)) - (PORT datac (549:549:549) (557:557:557)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1025:1025:1025) (1068:1068:1068)) - (PORT datab (2030:2030:2030) (2166:2166:2166)) - (PORT datac (821:821:821) (831:831:831)) - (PORT datad (2503:2503:2503) (2629:2629:2629)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1546:1546:1546) (1624:1624:1624)) - (PORT datab (938:938:938) (1017:1017:1017)) - (PORT datac (601:601:601) (662:662:662)) - (PORT datad (580:580:580) (585:585:585)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (920:920:920)) - (PORT datab (220:220:220) (258:258:258)) - (PORT datac (666:666:666) (685:685:685)) + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (781:781:781) (835:835:835)) + (PORT datac (973:973:973) (1029:1029:1029)) (PORT datad (173:173:173) (198:198:198)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) @@ -19312,187 +3389,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) + (INSTANCE z80_\|execute_\|ctl_mRead\~6) (DELAY (ABSOLUTE - (PORT dataa (658:658:658) (680:680:680)) - (PORT datab (1172:1172:1172) (1198:1198:1198)) - (PORT datac (636:636:636) (693:693:693)) - (PORT datad (307:307:307) (324:324:324)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (694:694:694)) - (PORT datab (806:806:806) (876:876:876)) - (PORT datac (1101:1101:1101) (1130:1130:1130)) - (PORT datad (589:589:589) (627:627:627)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (667:667:667)) - (PORT datab (654:654:654) (679:679:679)) - (PORT datac (936:936:936) (1033:1033:1033)) - (PORT datad (830:830:830) (861:861:861)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1518:1518:1518) (1588:1588:1588)) - (PORT datab (1051:1051:1051) (1075:1075:1075)) - (PORT datac (1263:1263:1263) (1316:1316:1316)) - (PORT datad (930:930:930) (999:999:999)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1452:1452:1452) (1482:1482:1482)) - (PORT datab (1142:1142:1142) (1181:1181:1181)) - (PORT datac (1196:1196:1196) (1287:1287:1287)) - (PORT datad (1139:1139:1139) (1160:1160:1160)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (646:646:646)) - (PORT datab (1014:1014:1014) (1076:1076:1076)) - (PORT datac (798:798:798) (807:807:807)) - (PORT datad (619:619:619) (632:632:632)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (276:276:276)) - (PORT datab (1030:1030:1030) (1067:1067:1067)) - (PORT datac (871:871:871) (866:866:866)) - (PORT datad (599:599:599) (614:614:614)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (619:619:619)) - (PORT datab (225:225:225) (273:273:273)) - (PORT datac (824:824:824) (846:846:846)) - (PORT datad (1377:1377:1377) (1491:1491:1491)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~9) - (DELAY - (ABSOLUTE - (PORT dataa (780:780:780) (837:837:837)) - (PORT datab (827:827:827) (864:864:864)) - (PORT datac (762:762:762) (835:835:835)) - (PORT datad (767:767:767) (810:810:810)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~10) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1230:1230:1230) (1277:1277:1277)) - (PORT datab (699:699:699) (755:755:755)) - (PORT datac (917:917:917) (964:964:964)) - (PORT datad (1070:1070:1070) (1101:1101:1101)) - (IOPATH dataa combout (304:304:304) (299:299:299)) + (PORT dataa (1813:1813:1813) (1882:1882:1882)) + (PORT datab (1074:1074:1074) (1139:1139:1139)) + (PORT datac (1722:1722:1722) (1803:1803:1803)) + (PORT datad (217:217:217) (256:256:256)) + (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -19501,406 +3405,74 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) (DELAY (ABSOLUTE - (PORT dataa (625:625:625) (667:667:667)) - (PORT datab (653:653:653) (673:673:673)) - (PORT datac (935:935:935) (1036:1036:1036)) - (PORT datad (387:387:387) (408:408:408)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) - (DELAY - (ABSOLUTE - (PORT dataa (971:971:971) (1042:1042:1042)) - (PORT datab (1807:1807:1807) (1835:1835:1835)) - (PORT datac (1262:1262:1262) (1315:1315:1315)) - (PORT datad (1069:1069:1069) (1081:1081:1081)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) - (DELAY - (ABSOLUTE - (PORT dataa (2018:2018:2018) (2105:2105:2105)) - (PORT datab (2408:2408:2408) (2537:2537:2537)) - (PORT datac (1381:1381:1381) (1441:1441:1441)) - (PORT datad (1576:1576:1576) (1733:1733:1733)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1517:1517:1517) (1579:1579:1579)) - (PORT datab (385:385:385) (404:404:404)) - (PORT datac (1263:1263:1263) (1308:1308:1308)) - (PORT datad (871:871:871) (923:923:923)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1215:1215:1215) (1269:1269:1269)) - (PORT datab (340:340:340) (375:375:375)) - (PORT datac (1057:1057:1057) (1084:1084:1084)) - (PORT datad (337:337:337) (358:358:358)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (385:385:385)) - (PORT datab (643:643:643) (665:665:665)) - (PORT datac (169:169:169) (201:201:201)) - (PORT datad (616:616:616) (624:624:624)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~18) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (887:887:887)) - (PORT datab (1118:1118:1118) (1197:1197:1197)) - (PORT datac (848:848:848) (898:898:898)) - (PORT datad (364:364:364) (426:426:426)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) - (DELAY - (ABSOLUTE - (PORT dataa (2563:2563:2563) (2705:2705:2705)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (1385:1385:1385) (1391:1391:1391)) - (PORT datad (1888:1888:1888) (1980:1980:1980)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (455:455:455) (529:529:529)) - (PORT datab (452:452:452) (522:522:522)) - (PORT datac (877:877:877) (897:897:897)) - (PORT datad (660:660:660) (680:680:680)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (546:546:546) (573:573:573)) - (PORT datab (633:633:633) (685:685:685)) - (PORT datac (619:619:619) (639:639:639)) - (PORT datad (630:630:630) (672:672:672)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) - (DELAY - (ABSOLUTE - (PORT dataa (815:815:815) (850:850:850)) - (PORT datab (621:621:621) (640:640:640)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (182:182:182) (212:212:212)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (811:811:811) (823:823:823)) - (PORT datab (610:610:610) (633:633:633)) - (PORT datac (1092:1092:1092) (1142:1142:1142)) - (PORT datad (895:895:895) (948:948:948)) + (PORT dataa (1366:1366:1366) (1474:1474:1474)) + (PORT datad (1994:1994:1994) (2071:2071:2071)) (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~8) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) (DELAY (ABSOLUTE - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (232:232:232) (287:287:287)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (432:432:432) (521:521:521)) - (PORT datab (682:682:682) (739:739:739)) - (PORT datac (877:877:877) (897:897:897)) - (PORT datad (660:660:660) (685:685:685)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~12) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (922:922:922)) - (PORT datab (224:224:224) (269:269:269)) - (PORT datac (826:826:826) (848:848:848)) - (PORT datad (904:904:904) (974:974:974)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) - (DELAY - (ABSOLUTE - (PORT dataa (786:786:786) (842:842:842)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (1821:1821:1821) (1815:1815:1815)) - (PORT datad (790:790:790) (826:826:826)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (684:684:684) (706:706:706)) - (PORT datab (1772:1772:1772) (1798:1798:1798)) - (PORT datac (179:179:179) (214:214:214)) - (PORT datad (823:823:823) (837:837:837)) + (PORT dataa (1446:1446:1446) (1484:1484:1484)) + (PORT datab (854:854:854) (902:902:902)) + (PORT datac (909:909:909) (971:971:971)) + (PORT datad (616:616:616) (647:647:647)) (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) - (DELAY - (ABSOLUTE - (PORT dataa (2390:2390:2390) (2544:2544:2544)) - (PORT datab (1497:1497:1497) (1581:1581:1581)) - (PORT datac (874:874:874) (897:897:897)) - (PORT datad (1014:1014:1014) (1128:1128:1128)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) - (DELAY - (ABSOLUTE - (PORT dataa (578:578:578) (605:605:605)) - (PORT datab (974:974:974) (1056:1056:1056)) - (PORT datac (672:672:672) (715:715:715)) - (PORT datad (819:819:819) (820:820:820)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) - (DELAY - (ABSOLUTE - (PORT dataa (987:987:987) (1039:1039:1039)) - (PORT datab (434:434:434) (474:474:474)) - (PORT datac (947:947:947) (1015:1015:1015)) - (PORT datad (1175:1175:1175) (1235:1235:1235)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (285:285:285)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (208:208:208) (238:238:238)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) - (DELAY - (ABSOLUTE - (PORT datab (229:229:229) (278:278:278)) - (PORT datac (193:193:193) (235:235:235)) - (PORT datad (374:374:374) (396:396:396)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (639:639:639) (661:661:661)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) - (DELAY - (ABSOLUTE - (PORT datab (1269:1269:1269) (1380:1380:1380)) - (PORT datac (901:901:901) (917:917:917)) - (PORT datad (1177:1177:1177) (1191:1191:1191)) (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) + (INSTANCE z80_\|execute_\|ctl_mWrite\~7) (DELAY (ABSOLUTE - (PORT dataa (1285:1285:1285) (1340:1340:1340)) - (PORT datab (1007:1007:1007) (1075:1075:1075)) - (PORT datac (1456:1456:1456) (1496:1496:1496)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (304:304:304) (307:307:307)) + (PORT dataa (1230:1230:1230) (1296:1296:1296)) + (PORT datab (266:266:266) (314:314:314)) + (PORT datac (928:928:928) (983:983:983)) + (PORT datad (1184:1184:1184) (1243:1243:1243)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (591:591:591)) + (PORT datab (1349:1349:1349) (1470:1470:1470)) + (PORT datac (808:808:808) (820:820:820)) + (PORT datad (834:834:834) (910:910:910)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1860:1860:1860) (1945:1945:1945)) + (PORT datab (1656:1656:1656) (1813:1813:1813)) + (PORT datac (1723:1723:1723) (1804:1804:1804)) + (PORT datad (880:880:880) (899:899:899)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -19909,15 +3481,213 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) + (INSTANCE z80_\|execute_\|fMWrite\~4) (DELAY (ABSOLUTE - (PORT dataa (2050:2050:2050) (2087:2087:2087)) - (PORT datab (943:943:943) (1022:1022:1022)) - (PORT datac (1211:1211:1211) (1239:1239:1239)) - (PORT datad (1083:1083:1083) (1126:1126:1126)) + (PORT datab (1616:1616:1616) (1771:1771:1771)) + (PORT datac (1389:1389:1389) (1456:1456:1456)) + (PORT datad (1311:1311:1311) (1374:1374:1374)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~4) + (DELAY + (ABSOLUTE + (PORT datab (2076:2076:2076) (2209:2209:2209)) + (PORT datad (933:933:933) (1039:1039:1039)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) + (DELAY + (ABSOLUTE + (PORT dataa (934:934:934) (985:985:985)) + (PORT datab (1376:1376:1376) (1394:1394:1394)) + (PORT datac (1649:1649:1649) (1659:1659:1659)) + (PORT datad (1168:1168:1168) (1213:1213:1213)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (935:935:935)) + (PORT datab (698:698:698) (760:760:760)) + (PORT datac (915:915:915) (959:959:959)) + (PORT datad (661:661:661) (719:719:719)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1181:1181:1181) (1224:1224:1224)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (873:873:873) (934:934:934)) + (PORT datad (183:183:183) (213:213:213)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1020:1020:1020) (1059:1059:1059)) + (PORT datab (1999:1999:1999) (2042:2042:2042)) + (PORT datac (1001:1001:1001) (1029:1029:1029)) + (PORT datad (1097:1097:1097) (1148:1148:1148)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~51) + (DELAY + (ABSOLUTE + (PORT dataa (2428:2428:2428) (2599:2599:2599)) + (PORT datab (1208:1208:1208) (1296:1296:1296)) + (PORT datac (1399:1399:1399) (1508:1508:1508)) + (PORT datad (555:555:555) (574:574:574)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (474:474:474) (509:509:509)) + (PORT datab (767:767:767) (841:841:841)) + (PORT datac (1069:1069:1069) (1085:1085:1085)) + (PORT datad (787:787:787) (850:850:850)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) + (DELAY + (ABSOLUTE + (PORT dataa (2204:2204:2204) (2398:2398:2398)) + (PORT datab (686:686:686) (707:707:707)) + (PORT datac (835:835:835) (875:875:875)) + (PORT datad (1872:1872:1872) (2005:2005:2005)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal46\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1772:1772:1772) (1872:1872:1872)) + (PORT datab (739:739:739) (800:800:800)) + (PORT datac (1861:1861:1861) (1915:1915:1915)) + (PORT datad (1607:1607:1607) (1753:1753:1753)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (812:812:812) (894:894:894)) + (PORT datab (1876:1876:1876) (2012:2012:2012)) + (PORT datac (328:328:328) (351:351:351)) + (PORT datad (1690:1690:1690) (1763:1763:1763)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (1013:1013:1013)) + (PORT datab (1893:1893:1893) (2038:2038:2038)) + (PORT datac (2174:2174:2174) (2358:2358:2358)) + (PORT datad (955:955:955) (995:995:995)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~6) + (DELAY + (ABSOLUTE + (PORT datab (1677:1677:1677) (1729:1729:1729)) + (PORT datad (2190:2190:2190) (2227:2227:2227)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1285:1285:1285) (1356:1356:1356)) + (PORT datab (662:662:662) (720:720:720)) + (PORT datac (856:856:856) (884:884:884)) + (PORT datad (846:846:846) (874:874:874)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19925,159 +3695,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) (DELAY (ABSOLUTE - (PORT dataa (923:923:923) (949:949:949)) - (PORT datab (1060:1060:1060) (1085:1085:1085)) - (PORT datac (892:892:892) (934:934:934)) - (PORT datad (568:568:568) (571:571:571)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1490:1490:1490) (1592:1592:1592)) - (PORT datab (438:438:438) (472:472:472)) - (PORT datac (945:945:945) (997:997:997)) - (PORT datad (1178:1178:1178) (1233:1233:1233)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1493:1493:1493) (1597:1597:1597)) - (PORT datab (234:234:234) (278:278:278)) - (PORT datac (2021:2021:2021) (2050:2050:2050)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (609:609:609) (638:638:638)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (258:258:258)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (817:817:817) (862:862:862)) - (PORT datad (554:554:554) (572:572:572)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1462:1462:1462) (1525:1525:1525)) - (PORT datab (1404:1404:1404) (1424:1424:1424)) - (PORT datac (1574:1574:1574) (1618:1618:1618)) - (PORT datad (1065:1065:1065) (1079:1079:1079)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) - (DELAY - (ABSOLUTE - (PORT dataa (734:734:734) (759:759:759)) - (PORT datab (699:699:699) (730:730:730)) - (PORT datac (1599:1599:1599) (1604:1604:1604)) - (PORT datad (1436:1436:1436) (1479:1479:1479)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1343:1343:1343) (1425:1425:1425)) - (PORT datab (1086:1086:1086) (1110:1110:1110)) - (PORT datac (1574:1574:1574) (1614:1614:1614)) - (PORT datad (1794:1794:1794) (1911:1911:1911)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (843:843:843) (880:880:880)) - (PORT datac (1602:1602:1602) (1608:1608:1608)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~42) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (867:867:867)) - (PORT datab (1092:1092:1092) (1116:1116:1116)) - (PORT datac (2113:2113:2113) (2219:2219:2219)) - (PORT datad (1789:1789:1789) (1904:1904:1904)) + (PORT dataa (1444:1444:1444) (1482:1482:1482)) + (PORT datab (1494:1494:1494) (1558:1558:1558)) + (PORT datac (1227:1227:1227) (1257:1257:1257)) + (PORT datad (932:932:932) (1002:1002:1002)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20085,63 +3711,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) (DELAY (ABSOLUTE (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1016:1016:1016) (1027:1027:1027)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~41) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (702:702:702)) - (PORT datab (2051:2051:2051) (2134:2134:2134)) - (PORT datac (1486:1486:1486) (1540:1540:1540)) - (PORT datad (1327:1327:1327) (1454:1454:1454)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1519:1519:1519) (1580:1580:1580)) - (PORT datab (1960:1960:1960) (1986:1986:1986)) - (PORT datac (1263:1263:1263) (1313:1313:1313)) - (PORT datad (869:869:869) (922:922:922)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1748:1748:1748) (1872:1872:1872)) - (PORT datab (1028:1028:1028) (1083:1083:1083)) - (PORT datac (199:199:199) (235:235:235)) - (PORT datad (1506:1506:1506) (1541:1541:1541)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (897:897:897) (961:961:961)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20149,31 +3725,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) + (INSTANCE z80_\|pla_decode_\|Equal55\~0) (DELAY (ABSOLUTE - (PORT dataa (1165:1165:1165) (1194:1194:1194)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1359:1359:1359) (1382:1382:1382)) + (PORT dataa (1756:1756:1756) (1851:1851:1851)) + (PORT datab (1657:1657:1657) (1809:1809:1809)) + (PORT datad (1812:1812:1812) (1893:1893:1893)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~44) + (INSTANCE z80_\|execute_\|ctl_mRead\~7) (DELAY (ABSOLUTE - (PORT dataa (819:819:819) (841:841:841)) - (PORT datab (1818:1818:1818) (1968:1968:1968)) - (PORT datac (1306:1306:1306) (1386:1386:1386)) - (PORT datad (1794:1794:1794) (1911:1911:1911)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (994:994:994) (1075:1075:1075)) + (PORT datac (1310:1310:1310) (1404:1404:1404)) + (PORT datad (914:914:914) (958:958:958)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20181,255 +3753,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (699:699:699) (733:733:733)) - (PORT datac (862:862:862) (901:901:901)) - (PORT datad (693:693:693) (717:717:717)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) - (DELAY - (ABSOLUTE - (PORT dataa (532:532:532) (551:551:551)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (641:641:641) (659:659:659)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~39) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (620:620:620)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (603:603:603) (622:622:622)) - (PORT datad (345:345:345) (359:359:359)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~40) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (917:917:917) (956:956:956)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (317:317:317) (337:337:337)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1666:1666:1666) (1754:1754:1754)) - (PORT datab (1416:1416:1416) (1493:1493:1493)) - (PORT datac (639:639:639) (659:659:659)) - (PORT datad (847:847:847) (875:875:875)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1450:1450:1450) (1506:1506:1506)) - (PORT datab (849:849:849) (859:859:859)) - (PORT datac (836:836:836) (864:864:864)) - (PORT datad (1389:1389:1389) (1423:1423:1423)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R) - (DELAY - (ABSOLUTE - (PORT dataa (831:831:831) (869:869:869)) - (PORT datab (1772:1772:1772) (1798:1798:1798)) - (PORT datac (618:618:618) (638:638:638)) - (PORT datad (822:822:822) (837:837:837)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1198:1198:1198) (1248:1248:1248)) - (PORT datab (223:223:223) (268:268:268)) - (PORT datac (914:914:914) (947:947:947)) - (PORT datad (607:607:607) (631:631:631)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (263:263:263) (334:334:334)) - (PORT datab (944:944:944) (991:991:991)) - (PORT datac (535:535:535) (545:545:545)) - (PORT datad (1139:1139:1139) (1125:1125:1125)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (673:673:673)) - (PORT datab (1125:1125:1125) (1173:1173:1173)) - (PORT datac (583:583:583) (615:615:615)) - (PORT datad (389:389:389) (443:443:443)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (263:263:263) (340:340:340)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (559:559:559) (583:583:583)) - (PORT datad (901:901:901) (948:948:948)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (511:511:511)) - (PORT datab (419:419:419) (499:499:499)) - (PORT datac (878:878:878) (901:901:901)) - (PORT datad (657:657:657) (678:678:678)) - (IOPATH dataa combout (324:324:324) (328:328:328)) + (PORT dataa (2680:2680:2680) (2765:2765:2765)) + (PORT datab (751:751:751) (781:781:781)) + (PORT datac (998:998:998) (1052:1052:1052)) + (PORT datad (890:890:890) (939:939:939)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (638:638:638) (659:659:659)) - (PORT datac (355:355:355) (378:378:378)) - (PORT datad (830:830:830) (837:837:837)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (419:419:419)) - (PORT datab (653:653:653) (711:711:711)) - (PORT datac (647:647:647) (707:707:707)) - (PORT datad (635:635:635) (659:659:659)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20437,670 +3769,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) (DELAY (ABSOLUTE - (PORT dataa (413:413:413) (443:443:443)) - (PORT datab (239:239:239) (284:284:284)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (709:709:709) (742:742:742)) - (PORT datab (1178:1178:1178) (1274:1274:1274)) - (PORT datac (855:855:855) (865:865:865)) - (PORT datad (674:674:674) (693:693:693)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1304:1304:1304) (1358:1358:1358)) - (PORT datab (1962:1962:1962) (1990:1990:1990)) - (PORT datac (1486:1486:1486) (1545:1545:1545)) - (PORT datad (1495:1495:1495) (1557:1557:1557)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1144:1144:1144) (1179:1179:1179)) - (PORT datab (609:609:609) (638:638:638)) - (PORT datac (820:820:820) (842:842:842)) + (PORT dataa (1003:1003:1003) (1052:1052:1052)) + (PORT datac (1080:1080:1080) (1095:1095:1095)) (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (257:257:257)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datad (798:798:798) (805:805:805)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1152:1152:1152) (1175:1175:1175)) - (PORT datac (567:567:567) (576:576:576)) - (PORT datad (1627:1627:1627) (1703:1703:1703)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (927:927:927)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1829:1829:1829) (1911:1911:1911)) - (PORT datad (562:562:562) (570:570:570)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~13) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (415:415:415)) - (PORT datab (2086:2086:2086) (2229:2229:2229)) - (PORT datac (1314:1314:1314) (1402:1402:1402)) - (PORT datad (902:902:902) (968:968:968)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (462:462:462)) - (PORT datab (612:612:612) (633:633:633)) - (PORT datac (1175:1175:1175) (1235:1235:1235)) - (PORT datad (822:822:822) (844:844:844)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) - (DELAY - (ABSOLUTE - (PORT dataa (572:572:572) (597:597:597)) - (PORT datab (615:615:615) (638:638:638)) - (PORT datad (567:567:567) (574:574:574)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (685:685:685)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (807:807:807) (808:808:808)) - (PORT datad (203:203:203) (232:232:232)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1698:1698:1698) (1789:1789:1789)) - (PORT datab (919:919:919) (952:952:952)) - (PORT datac (888:888:888) (909:909:909)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[12\]) - (DELAY - (ABSOLUTE - (PORT datab (403:403:403) (448:448:448)) - (PORT datac (885:885:885) (915:915:915)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[12\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (314:314:314) (333:333:333)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1561:1561:1561)) - (PORT ena (2058:2058:2058) (2109:2109:2109)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (638:638:638)) - (PORT datab (903:903:903) (926:926:926)) - (PORT datac (240:240:240) (327:327:327)) - (PORT datad (577:577:577) (639:639:639)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (1270:1270:1270) (1318:1318:1318)) - (PORT ena (935:935:935) (924:924:924)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (460:460:460)) - (PORT datab (412:412:412) (448:448:448)) - (PORT datad (194:194:194) (218:218:218)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (717:717:717)) - (PORT datac (216:216:216) (293:293:293)) - (PORT datad (775:775:775) (807:807:807)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (418:418:418)) - (PORT datab (838:838:838) (875:875:875)) - (PORT datac (679:679:679) (721:721:721)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (2041:2041:2041) (2053:2053:2053)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (437:437:437)) - (PORT datab (1165:1165:1165) (1216:1216:1216)) - (PORT datad (739:739:739) (751:751:751)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (2041:2041:2041) (2050:2050:2050)) - (PORT ena (1236:1236:1236) (1273:1273:1273)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (692:692:692) (780:780:780)) - (PORT datab (884:884:884) (909:909:909)) - (PORT datad (866:866:866) (902:902:902)) (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1376:1376:1376) (1427:1427:1427)) - (PORT ena (1214:1214:1214) (1210:1210:1210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1376:1376:1376) (1429:1429:1429)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (905:905:905) (945:945:945)) - (PORT datab (244:244:244) (290:290:290)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1394:1394:1394) (1418:1418:1418)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1721:1721:1721) (1742:1742:1742)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (392:392:392) (467:467:467)) - (PORT datab (1593:1593:1593) (1645:1645:1645)) - (PORT datad (1180:1180:1180) (1215:1215:1215)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (809:809:809) (810:810:810)) - (PORT datad (610:610:610) (622:622:622)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1872:1872:1872) (1943:1943:1943)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1872:1872:1872) (1942:1942:1942)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (991:991:991)) - (PORT datab (912:912:912) (981:981:981)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1938:1938:1938) (1952:1952:1952)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1936:1936:1936) (1952:1952:1952)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (519:519:519)) - (PORT datab (492:492:492) (537:537:537)) - (PORT datad (217:217:217) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1867:1867:1867) (1935:1935:1935)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (988:988:988)) - (PORT datab (1221:1221:1221) (1295:1295:1295)) - (PORT datad (887:887:887) (943:943:943)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (697:697:697)) - (PORT datab (331:331:331) (360:360:360)) - (PORT datac (577:577:577) (594:594:594)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -21108,2955 +3783,25 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~66) + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) (DELAY (ABSOLUTE - (PORT dataa (883:883:883) (947:947:947)) - (PORT datab (844:844:844) (916:916:916)) - (PORT datac (840:840:840) (851:851:851)) - (PORT datad (1298:1298:1298) (1335:1335:1335)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1304:1304:1304) (1356:1356:1356)) - (PORT datab (968:968:968) (1024:1024:1024)) - (PORT datac (891:891:891) (908:908:908)) - (PORT datad (1445:1445:1445) (1454:1454:1454)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1289:1289:1289) (1337:1337:1337)) - (PORT datab (1225:1225:1225) (1251:1251:1251)) - (PORT datac (904:904:904) (947:947:947)) - (PORT datad (928:928:928) (986:986:986)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (251:251:251)) - (PORT datab (249:249:249) (305:305:305)) - (PORT datac (1067:1067:1067) (1064:1064:1064)) - (PORT datad (949:949:949) (996:996:996)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1286:1286:1286) (1354:1354:1354)) - (PORT datab (933:933:933) (990:990:990)) - (PORT datac (372:372:372) (402:402:402)) - (PORT datad (1200:1200:1200) (1314:1314:1314)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1230:1230:1230)) - (PORT datab (1831:1831:1831) (1921:1921:1921)) - (PORT datac (881:881:881) (935:935:935)) - (PORT datad (1554:1554:1554) (1661:1661:1661)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) - (DELAY - (ABSOLUTE - (PORT dataa (923:923:923) (987:987:987)) - (PORT datab (637:637:637) (672:672:672)) - (PORT datac (1395:1395:1395) (1470:1470:1470)) - (PORT datad (580:580:580) (617:617:617)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datac (935:935:935) (965:965:965)) - (PORT datad (241:241:241) (282:282:282)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1212:1212:1212)) - (PORT datab (290:290:290) (355:355:355)) - (PORT datac (254:254:254) (314:314:314)) - (PORT datad (246:246:246) (292:292:292)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT datab (359:359:359) (395:395:395)) - (PORT datac (927:927:927) (982:982:982)) - (PORT datad (676:676:676) (714:714:714)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (695:695:695)) - (PORT datab (1175:1175:1175) (1218:1218:1218)) - (PORT datac (649:649:649) (707:707:707)) - (PORT datad (660:660:660) (719:719:719)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (598:598:598) (629:629:629)) - (PORT datab (329:329:329) (356:356:356)) - (PORT datac (1163:1163:1163) (1203:1203:1203)) - (PORT datad (530:530:530) (548:548:548)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (679:679:679)) - (PORT datab (998:998:998) (1032:1032:1032)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (220:220:220) (263:263:263)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (621:621:621)) - (PORT datab (963:963:963) (1009:1009:1009)) - (PORT datac (864:864:864) (907:907:907)) - (PORT datad (337:337:337) (357:357:357)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (674:674:674) (713:713:713)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (963:963:963)) - (PORT datab (719:719:719) (762:762:762)) - (PORT datac (929:929:929) (980:980:980)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (678:678:678)) - (PORT datab (640:640:640) (697:697:697)) - (PORT datac (608:608:608) (646:646:646)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (648:648:648)) - (PORT datab (935:935:935) (984:984:984)) - (PORT datac (1093:1093:1093) (1149:1149:1149)) - (PORT datad (575:575:575) (595:595:595)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (263:263:263) (339:339:339)) - (PORT datac (171:171:171) (204:204:204)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (431:431:431) (524:524:524)) - (PORT datac (650:650:650) (711:711:711)) - (PORT datad (658:658:658) (684:684:684)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (600:600:600)) - (PORT datab (826:826:826) (830:830:830)) - (PORT datac (805:805:805) (806:806:806)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (688:688:688) (712:712:712)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datac (203:203:203) (240:240:240)) - (PORT datad (818:818:818) (831:831:831)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (676:676:676)) - (PORT datab (632:632:632) (684:684:684)) - (PORT datad (630:630:630) (672:672:672)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (704:704:704)) - (PORT datab (860:860:860) (876:876:876)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (515:515:515) (526:526:526)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (252:252:252)) - (PORT datab (213:213:213) (257:257:257)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (182:182:182) (212:212:212)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (690:690:690)) - (PORT datab (662:662:662) (696:696:696)) - (PORT datad (604:604:604) (655:655:655)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (369:369:369) (405:405:405)) - (PORT datab (638:638:638) (659:659:659)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (830:830:830) (837:837:837)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (410:410:410)) - (PORT datab (394:394:394) (423:423:423)) - (PORT datac (177:177:177) (214:214:214)) - (PORT datad (368:368:368) (390:390:390)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) - (DELAY - (ABSOLUTE - (PORT datac (1740:1740:1740) (1766:1766:1766)) - (PORT datad (822:822:822) (836:836:836)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (410:410:410)) - (PORT datab (234:234:234) (279:279:279)) - (PORT datac (177:177:177) (213:213:213)) - (PORT datad (179:179:179) (207:207:207)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (236:236:236) (281:281:281)) - (PORT datac (354:354:354) (379:379:379)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1068:1068:1068) (1102:1102:1102)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1435:1435:1435) (1482:1482:1482)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (1596:1596:1596) (1648:1648:1648)) - (PORT datad (1179:1179:1179) (1221:1221:1221)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1647:1647:1647) (1718:1718:1718)) - (PORT ena (1214:1214:1214) (1210:1210:1210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1644:1644:1644) (1714:1714:1714)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (902:902:902) (942:942:942)) - (PORT datab (245:245:245) (290:290:290)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1405:1405:1405) (1471:1471:1471)) - (PORT ena (1236:1236:1236) (1273:1273:1273)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (798:798:798)) - (PORT datab (884:884:884) (909:909:909)) - (PORT datad (866:866:866) (902:902:902)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1404:1404:1404) (1472:1472:1472)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (1391:1391:1391) (1418:1418:1418)) - (PORT datab (1167:1167:1167) (1217:1217:1217)) - (PORT datad (238:238:238) (279:279:279)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (820:820:820) (843:843:843)) - (PORT datab (1070:1070:1070) (1130:1130:1130)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1442:1442:1442) (1490:1490:1490)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1439:1439:1439) (1490:1490:1490)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (523:523:523)) - (PORT datab (492:492:492) (536:536:536)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1377:1377:1377) (1423:1423:1423)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (938:938:938) (994:994:994)) - (PORT datab (1222:1222:1222) (1294:1294:1294)) - (PORT datad (881:881:881) (941:941:941)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1195:1195:1195) (1249:1249:1249)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1195:1195:1195) (1248:1248:1248)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (924:924:924) (985:985:985)) - (PORT datab (910:910:910) (988:988:988)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (410:410:410)) - (PORT datab (634:634:634) (661:661:661)) - (PORT datac (637:637:637) (673:673:673)) - (PORT datad (789:789:789) (853:853:853)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (1138:1138:1138) (1178:1178:1178)) - (PORT ena (935:935:935) (924:924:924)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (407:407:407) (446:446:446)) - (PORT datad (387:387:387) (422:422:422)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (860:860:860)) - (PORT datac (214:214:214) (289:289:289)) - (PORT datad (646:646:646) (672:672:672)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (623:623:623) (634:634:634)) - (PORT datab (906:906:906) (933:933:933)) - (PORT datac (239:239:239) (322:322:322)) - (PORT datad (576:576:576) (636:636:636)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) - (DELAY - (ABSOLUTE - (PORT datac (258:258:258) (345:345:345)) - (PORT datad (187:187:187) (220:220:220)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1405:1405:1405) (1477:1477:1477)) - (PORT ena (1261:1261:1261) (1299:1299:1299)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (1099:1099:1099) (1151:1151:1151)) - (PORT datab (881:881:881) (915:915:915)) - (PORT datad (665:665:665) (744:744:744)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (2052:2052:2052) (2111:2111:2111)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1647:1647:1647) (1654:1654:1654)) - (PORT datab (1164:1164:1164) (1211:1211:1211)) - (PORT datad (231:231:231) (271:271:271)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1101:1101:1101) (1166:1166:1166)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1418:1418:1418) (1481:1481:1481)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (380:380:380) (459:459:459)) - (PORT datab (1594:1594:1594) (1651:1651:1651)) - (PORT datad (1178:1178:1178) (1221:1221:1221)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1799:1799:1799) (1855:1855:1855)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1406:1406:1406) (1476:1476:1476)) - (PORT ena (1131:1131:1131) (1098:1098:1098)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (478:478:478)) - (PORT datab (881:881:881) (916:916:916)) - (PORT datad (364:364:364) (384:384:384)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (338:338:338) (368:368:368)) - (PORT datac (804:804:804) (808:808:808)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1448:1448:1448) (1498:1498:1498)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1448:1448:1448) (1501:1501:1501)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (518:518:518)) - (PORT datab (240:240:240) (322:322:322)) - (PORT datad (458:458:458) (504:504:504)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1721:1721:1721) (1779:1779:1779)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1723:1723:1723) (1782:1782:1782)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (989:989:989)) - (PORT datab (243:243:243) (326:326:326)) - (PORT datad (883:883:883) (941:941:941)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1771:1771:1771) (1829:1829:1829)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (989:989:989)) - (PORT datab (1220:1220:1220) (1296:1296:1296)) - (PORT datad (884:884:884) (944:944:944)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (699:699:699)) - (PORT datab (825:825:825) (869:869:869)) - (PORT datac (606:606:606) (632:632:632)) - (PORT datad (842:842:842) (848:848:848)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (884:884:884) (946:946:946)) - (PORT datab (197:197:197) (234:234:234)) - (PORT datac (817:817:817) (863:863:863)) - (PORT datad (1298:1298:1298) (1332:1332:1332)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (1159:1159:1159) (1205:1205:1205)) - (PORT ena (935:935:935) (924:924:924)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (459:459:459)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datad (386:386:386) (413:413:413)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (716:716:716)) - (PORT datab (379:379:379) (421:421:421)) - (PORT datac (215:215:215) (292:292:292)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (567:567:567) (582:582:582)) - (PORT datab (844:844:844) (883:883:883)) - (PORT datac (682:682:682) (722:722:722)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[13\]) - (DELAY - (ABSOLUTE - (PORT datab (383:383:383) (425:425:425)) - (PORT datac (886:886:886) (918:918:918)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[13\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (335:335:335) (352:352:352)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1561:1561:1561)) - (PORT ena (2058:2058:2058) (2109:2109:2109)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) - (DELAY - (ABSOLUTE - (PORT datac (258:258:258) (345:345:345)) - (PORT datad (869:869:869) (891:891:891)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[15\]) - (DELAY - (ABSOLUTE - (PORT datac (356:356:356) (377:377:377)) - (PORT datad (867:867:867) (889:889:889)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1561:1561:1561)) - (PORT ena (2058:2058:2058) (2109:2109:2109)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) - (DELAY - (ABSOLUTE - (PORT dataa (290:290:290) (385:385:385)) - (PORT datab (215:215:215) (260:260:260)) - (PORT datac (245:245:245) (326:326:326)) - (PORT datad (866:866:866) (891:891:891)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (2284:2284:2284) (2422:2422:2422)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (2284:2284:2284) (2422:2422:2422)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (524:524:524)) - (PORT datab (491:491:491) (541:541:541)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1879:1879:1879) (1975:1975:1975)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (818:818:818) (835:835:835)) - (PORT datab (1168:1168:1168) (1216:1216:1216)) - (PORT datad (239:239:239) (281:281:281)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1192:1192:1192) (1258:1258:1258)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (2131:2131:2131) (2211:2211:2211)) - (PORT ena (1131:1131:1131) (1098:1098:1098)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (460:460:460)) - (PORT datab (883:883:883) (917:917:917)) - (PORT datad (364:364:364) (384:384:384)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1453:1453:1453) (1497:1497:1497)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1453:1453:1453) (1497:1497:1497)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (1297:1297:1297) (1353:1353:1353)) - (PORT datab (1218:1218:1218) (1255:1255:1255)) - (PORT datad (214:214:214) (282:282:282)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (2133:2133:2133) (2211:2211:2211)) - (PORT ena (1261:1261:1261) (1299:1299:1299)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (1100:1100:1100) (1146:1146:1146)) - (PORT datab (681:681:681) (756:756:756)) - (PORT datad (848:848:848) (874:874:874)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (624:624:624)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (595:595:595) (612:612:612)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1205:1205:1205) (1270:1270:1270)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1205:1205:1205) (1270:1270:1270)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (985:985:985)) - (PORT datab (912:912:912) (982:982:982)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (2162:2162:2162) (2212:2212:2212)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (939:939:939) (997:997:997)) - (PORT datab (1220:1220:1220) (1296:1296:1296)) - (PORT datad (879:879:879) (940:940:940)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (650:650:650)) - (PORT datab (632:632:632) (657:657:657)) - (PORT datac (489:489:489) (507:507:507)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (944:944:944)) - (PORT datab (672:672:672) (688:688:688)) - (PORT datac (786:786:786) (839:839:839)) - (PORT datad (1301:1301:1301) (1333:1333:1333)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (1132:1132:1132) (1183:1183:1183)) - (PORT ena (935:935:935) (924:924:924)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (466:466:466)) - (PORT datab (218:218:218) (258:258:258)) - (PORT datad (382:382:382) (412:412:412)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (332:332:332)) - (PORT datab (670:670:670) (688:688:688)) - (PORT datad (645:645:645) (672:672:672)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (401:401:401)) - (PORT datab (712:712:712) (754:754:754)) - (PORT datac (808:808:808) (840:840:840)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[14\]) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (955:955:955)) - (PORT datac (361:361:361) (395:395:395)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[14\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (320:320:320) (331:331:331)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1561:1561:1561)) - (PORT ena (2058:2058:2058) (2109:2109:2109)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (1141:1141:1141) (1169:1169:1169)) - (PORT datab (404:404:404) (477:477:477)) - (PORT datac (1110:1110:1110) (1117:1117:1117)) - (PORT datad (632:632:632) (663:663:663)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (214:214:214) (258:258:258)) - (PORT datac (232:232:232) (316:316:316)) - (PORT datad (339:339:339) (360:360:360)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (417:417:417)) - (PORT datab (712:712:712) (760:760:760)) - (PORT datac (814:814:814) (847:847:847)) - (PORT datad (550:550:550) (569:569:569)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (880:880:880) (950:950:950)) - (PORT datab (664:664:664) (704:704:704)) - (PORT datac (792:792:792) (834:834:834)) - (PORT datad (1297:1297:1297) (1337:1337:1337)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1297:1297:1297) (1347:1347:1347)) - (PORT datab (973:973:973) (1026:1026:1026)) - (PORT datac (1877:1877:1877) (1946:1946:1946)) - (PORT datad (831:831:831) (844:844:844)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datab (256:256:256) (314:314:314)) - (PORT datac (1193:1193:1193) (1204:1204:1204)) - (PORT datad (945:945:945) (989:989:989)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (933:933:933) (970:970:970)) - (PORT datab (1223:1223:1223) (1296:1296:1296)) - (PORT datac (905:905:905) (924:924:924)) - (PORT datad (1385:1385:1385) (1451:1451:1451)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (893:893:893) (902:902:902)) - (PORT datab (661:661:661) (697:697:697)) - (PORT datac (670:670:670) (697:697:697)) - (PORT datad (675:675:675) (694:694:694)) - (IOPATH dataa combout (325:325:325) (320:320:320)) + (PORT datab (1557:1557:1557) (1643:1643:1643)) + (PORT datac (1196:1196:1196) (1284:1284:1284)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) (DELAY (ABSOLUTE - (PORT dataa (1512:1512:1512) (1612:1612:1612)) - (PORT datab (1393:1393:1393) (1508:1508:1508)) - (PORT datac (1411:1411:1411) (1459:1459:1459)) - (PORT datad (835:835:835) (870:870:870)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (635:635:635)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (1083:1083:1083) (1127:1127:1127)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1159:1159:1159) (1199:1199:1199)) - (PORT datab (1007:1007:1007) (1063:1063:1063)) - (PORT datac (212:212:212) (252:252:252)) - (PORT datad (1995:1995:1995) (2085:2085:2085)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (211:211:211) (260:260:260)) - (PORT datab (634:634:634) (650:650:650)) - (PORT datac (599:599:599) (616:616:616)) - (PORT datad (610:610:610) (626:626:626)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~2) - (DELAY - (ABSOLUTE - (PORT datab (701:701:701) (761:761:761)) - (PORT datac (1331:1331:1331) (1352:1352:1352)) - (PORT datad (1148:1148:1148) (1179:1179:1179)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1693:1693:1693) (1732:1732:1732)) - (PORT datab (1474:1474:1474) (1569:1569:1569)) - (PORT datac (2562:2562:2562) (2664:2664:2664)) - (PORT datad (1898:1898:1898) (2017:2017:2017)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1942:1942:1942) (2062:2062:2062)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (918:918:918) (965:965:965)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (664:664:664)) - (PORT datab (640:640:640) (658:658:658)) - (PORT datad (880:880:880) (936:936:936)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1199:1199:1199) (1286:1286:1286)) - (PORT datab (255:255:255) (340:340:340)) - (PORT datac (1353:1353:1353) (1415:1415:1415)) - (PORT datad (1199:1199:1199) (1262:1262:1262)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datad (1171:1171:1171) (1244:1244:1244)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (219:219:219) (259:259:259)) - (PORT datac (882:882:882) (919:919:919)) - (PORT datad (1382:1382:1382) (1453:1453:1453)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (442:442:442)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (896:896:896) (932:932:932)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (511:511:511)) - (PORT datab (1166:1166:1166) (1210:1210:1210)) - (PORT datac (593:593:593) (646:646:646)) - (PORT datad (662:662:662) (719:719:719)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1177:1177:1177) (1208:1208:1208)) - (PORT datab (281:281:281) (344:344:344)) - (PORT datac (245:245:245) (304:304:304)) - (PORT datad (256:256:256) (301:301:301)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (378:378:378)) - (PORT datab (802:802:802) (831:831:831)) - (PORT datac (498:498:498) (504:504:504)) - (PORT datad (1104:1104:1104) (1147:1147:1147)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (639:639:639)) - (PORT datab (999:999:999) (1033:1033:1033)) - (PORT datac (589:589:589) (604:604:604)) - (PORT datad (221:221:221) (264:264:264)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (404:404:404)) - (PORT datab (893:893:893) (942:942:942)) - (PORT datac (1167:1167:1167) (1166:1166:1166)) - (PORT datad (680:680:680) (715:715:715)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (756:756:756)) - (PORT datab (1177:1177:1177) (1222:1222:1222)) - (PORT datac (613:613:613) (678:678:678)) - (PORT datad (666:666:666) (725:725:725)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) - (DELAY - (ABSOLUTE - (PORT datab (288:288:288) (350:350:350)) - (PORT datad (251:251:251) (296:296:296)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (285:285:285) (347:347:347)) - (PORT datab (620:620:620) (638:638:638)) - (PORT datac (1141:1141:1141) (1167:1167:1167)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1287:1287:1287)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (968:968:968) (996:996:996)) - (PORT datac (1660:1660:1660) (1742:1742:1742)) - (PORT datad (1418:1418:1418) (1445:1445:1445)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1138:1138:1138) (1168:1168:1168)) - (PORT datab (1129:1129:1129) (1182:1182:1182)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (241:241:241) (282:282:282)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (522:522:522) (538:538:538)) - (PORT datab (879:879:879) (956:956:956)) - (PORT datac (959:959:959) (990:990:990)) - (PORT datad (594:594:594) (608:608:608)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1196:1196:1196) (1243:1243:1243)) - (PORT datab (609:609:609) (645:645:645)) - (PORT datac (193:193:193) (235:235:235)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (695:695:695)) - (PORT datab (912:912:912) (959:959:959)) - (PORT datac (854:854:854) (883:883:883)) - (PORT datad (1144:1144:1144) (1179:1179:1179)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (678:678:678)) - (PORT datab (961:961:961) (1023:1023:1023)) - (PORT datac (1152:1152:1152) (1178:1178:1178)) - (PORT datad (225:225:225) (270:270:270)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (279:279:279)) - (PORT datab (1448:1448:1448) (1517:1517:1517)) - (PORT datac (1115:1115:1115) (1163:1163:1163)) - (PORT datad (178:178:178) (206:206:206)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1187:1187:1187) (1261:1261:1261)) - (PORT datab (930:930:930) (959:959:959)) - (PORT datac (533:533:533) (553:553:553)) - (PORT datad (844:844:844) (856:856:856)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1441:1441:1441) (1548:1548:1548)) - (PORT datab (218:218:218) (257:257:257)) - (PORT datac (235:235:235) (277:277:277)) - (PORT datad (1401:1401:1401) (1453:1453:1453)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (663:663:663)) - (PORT datab (615:615:615) (664:664:664)) - (PORT datac (664:664:664) (693:693:693)) - (PORT datad (680:680:680) (701:701:701)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) - (DELAY - (ABSOLUTE - (PORT datab (614:614:614) (644:644:644)) - (PORT datad (801:801:801) (877:877:877)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla69M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (665:665:665)) - (PORT datab (2306:2306:2306) (2385:2385:2385)) - (PORT datac (2054:2054:2054) (2198:2198:2198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (377:377:377) (426:426:426)) - (PORT datab (1624:1624:1624) (1701:1701:1701)) - (PORT datac (829:829:829) (848:848:848)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (816:816:816) (877:877:877)) - (PORT datab (360:360:360) (396:396:396)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (1002:1002:1002)) - (PORT datab (692:692:692) (710:710:710)) - (PORT datac (563:563:563) (586:586:586)) - (PORT datad (616:616:616) (630:630:630)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_xf) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~33) - (DELAY - (ABSOLUTE - (PORT datab (957:957:957) (981:981:981)) - (PORT datac (645:645:645) (694:694:694)) - (PORT datad (656:656:656) (712:712:712)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (378:378:378)) - (PORT datab (209:209:209) (251:251:251)) - (PORT datac (177:177:177) (213:213:213)) - (PORT datad (652:652:652) (692:692:692)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (904:904:904)) - (PORT datab (994:994:994) (1026:1026:1026)) - (PORT datac (1433:1433:1433) (1520:1520:1520)) - (PORT datad (1142:1142:1142) (1160:1160:1160)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (697:697:697)) - (PORT datab (936:936:936) (950:950:950)) - (PORT datac (1455:1455:1455) (1497:1497:1497)) - (PORT datad (1163:1163:1163) (1183:1183:1183)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (638:638:638)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datac (881:881:881) (909:909:909)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) - (DELAY - (ABSOLUTE - (PORT datab (1639:1639:1639) (1704:1704:1704)) - (PORT datac (1440:1440:1440) (1481:1481:1481)) - (PORT datad (1160:1160:1160) (1199:1199:1199)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (500:500:500)) - (PORT datab (1223:1223:1223) (1282:1282:1282)) - (PORT datac (1145:1145:1145) (1179:1179:1179)) - (PORT datad (899:899:899) (938:938:938)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (868:868:868) (917:917:917)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (870:870:870) (900:900:900)) - (PORT datad (616:616:616) (665:665:665)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (647:647:647)) - (PORT datab (247:247:247) (295:295:295)) - (PORT datac (1154:1154:1154) (1184:1184:1184)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (474:474:474) (512:512:512)) - (PORT datab (1141:1141:1141) (1188:1188:1188)) - (PORT datad (1463:1463:1463) (1479:1479:1479)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (486:486:486)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (1618:1618:1618) (1617:1617:1617)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) - (DELAY - (ABSOLUTE - (PORT datab (353:353:353) (390:390:390)) - (PORT datac (784:784:784) (794:794:794)) - (PORT datad (320:320:320) (341:341:341)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (970:970:970) (1022:1022:1022)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (970:970:970) (1022:1022:1022)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (336:336:336)) - (PORT datab (975:975:975) (1029:1029:1029)) - (PORT datad (845:845:845) (875:875:875)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (868:868:868) (877:877:877)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (869:869:869) (877:877:877)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (246:246:246) (333:333:333)) - (PORT datab (260:260:260) (314:314:314)) - (PORT datad (229:229:229) (267:267:267)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (870:870:870)) - (PORT datab (202:202:202) (242:242:242)) - (PORT datac (607:607:607) (626:626:626)) - (PORT datad (625:625:625) (639:639:639)) + (PORT dataa (994:994:994) (1076:1076:1076)) + (PORT datab (1450:1450:1450) (1484:1484:1484)) + (PORT datac (1313:1313:1313) (1404:1404:1404)) + (PORT datad (917:917:917) (957:957:957)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -24066,2295 +3811,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~52) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~17) (DELAY (ABSOLUTE - (PORT dataa (858:858:858) (895:895:895)) - (PORT datab (609:609:609) (627:627:627)) - (PORT datac (332:332:332) (359:359:359)) - (PORT datad (1115:1115:1115) (1138:1138:1138)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (957:957:957) (1002:1002:1002)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1331:1331:1331) (1374:1374:1374)) - (PORT datab (697:697:697) (731:731:731)) - (PORT datad (1194:1194:1194) (1238:1238:1238)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (669:669:669)) - (PORT datac (704:704:704) (742:742:742)) - (PORT datad (220:220:220) (290:290:290)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (401:401:401)) - (PORT datab (960:960:960) (999:999:999)) - (PORT datac (683:683:683) (718:718:718)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[3\]) - (DELAY - (ABSOLUTE - (PORT datab (240:240:240) (286:286:286)) - (PORT datac (548:548:548) (560:560:560)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT asdata (870:870:870) (882:882:882)) - (PORT clrn (1597:1597:1597) (1572:1572:1572)) - (PORT ena (2143:2143:2143) (2210:2210:2210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~4) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (429:429:429)) - (PORT datab (1153:1153:1153) (1183:1183:1183)) - (PORT datac (963:963:963) (1032:1032:1032)) - (PORT datad (244:244:244) (316:316:316)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (392:392:392)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (340:340:340) (367:367:367)) - (PORT datad (324:324:324) (346:346:346)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (265:265:265) (352:352:352)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (332:332:332) (358:358:358)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1239:1239:1239) (1260:1260:1260)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1236:1236:1236) (1256:1256:1256)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (258:258:258) (310:310:310)) - (PORT datad (228:228:228) (266:266:266)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (663:663:663)) - (PORT datab (1133:1133:1133) (1182:1182:1182)) - (PORT datad (630:630:630) (644:644:644)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1202:1202:1202) (1222:1222:1222)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1206:1206:1206) (1227:1227:1227)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (408:408:408) (466:466:466)) - (PORT datab (591:591:591) (631:631:631)) - (PORT datad (218:218:218) (288:288:288)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1505:1505:1505) (1518:1518:1518)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (958:958:958) (967:967:967)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (960:960:960) (969:969:969)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (467:467:467) (505:505:505)) - (PORT datab (668:668:668) (703:703:703)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (665:665:665)) - (PORT datab (920:920:920) (943:943:943)) - (PORT datac (213:213:213) (288:288:288)) - (PORT datad (335:335:335) (356:356:356)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (993:993:993) (1020:1020:1020)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (995:995:995) (1022:1022:1022)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (875:875:875) (922:922:922)) - (PORT datab (965:965:965) (1021:1021:1021)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (984:984:984) (1006:1006:1006)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (982:982:982) (1003:1003:1003)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (700:700:700)) - (PORT datab (396:396:396) (436:436:436)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (875:875:875) (882:882:882)) - (PORT ena (1407:1407:1407) (1382:1382:1382)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (527:527:527) (547:547:547)) - (PORT datad (825:825:825) (835:835:835)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (377:377:377)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1018:1018:1018) (1019:1019:1019)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (856:856:856) (875:875:875)) - (PORT datac (1094:1094:1094) (1126:1126:1126)) - (PORT datad (1162:1162:1162) (1190:1190:1190)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1359:1359:1359) (1370:1370:1370)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (911:911:911)) - (PORT datab (1236:1236:1236) (1275:1275:1275)) - (PORT datad (664:664:664) (688:688:688)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (624:624:624) (675:675:675)) - (PORT datac (704:704:704) (739:739:739)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (401:401:401)) - (PORT datab (959:959:959) (1001:1001:1001)) - (PORT datac (682:682:682) (721:721:721)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[4\]) - (DELAY - (ABSOLUTE - (PORT datab (238:238:238) (283:283:283)) - (PORT datad (529:529:529) (540:540:540)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT asdata (852:852:852) (858:858:858)) - (PORT clrn (1597:1597:1597) (1572:1572:1572)) - (PORT ena (2143:2143:2143) (2210:2210:2210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1182:1182:1182)) - (PORT datab (985:985:985) (1022:1022:1022)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (770:770:770)) - (PORT datab (1162:1162:1162) (1199:1199:1199)) - (PORT datac (626:626:626) (647:647:647)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (879:879:879) (891:891:891)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (878:878:878) (893:893:893)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (966:966:966) (1022:1022:1022)) - (PORT datad (843:843:843) (873:873:873)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (692:692:692) (715:715:715)) - (PORT ena (1477:1477:1477) (1472:1472:1472)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (692:692:692) (713:713:713)) - (PORT ena (1247:1247:1247) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1134:1134:1134)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (658:658:658) (679:679:679)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1437:1437:1437) (1460:1460:1460)) - (PORT ena (1505:1505:1505) (1518:1518:1518)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1457:1457:1457) (1472:1472:1472)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (458:458:458) (494:494:494)) - (PORT datab (1132:1132:1132) (1177:1177:1177)) - (PORT datad (626:626:626) (636:636:636)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) - (DELAY - (ABSOLUTE - (PORT datab (918:918:918) (940:940:940)) - (PORT datad (338:338:338) (359:359:359)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1214:1214:1214) (1217:1217:1217)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1214:1214:1214) (1215:1215:1215)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (467:467:467)) - (PORT datab (592:592:592) (632:632:632)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1471:1471:1471) (1477:1477:1477)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (607:607:607) (622:622:622)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (693:693:693)) - (PORT datab (390:390:390) (429:429:429)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (853:853:853) (859:859:859)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1407:1407:1407) (1382:1382:1382)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1457:1457:1457) (1474:1474:1474)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (574:574:574) (638:638:638)) - (PORT datab (836:836:836) (860:860:860)) - (PORT datad (645:645:645) (669:669:669)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (656:656:656)) - (PORT datab (1118:1118:1118) (1148:1148:1148)) - (PORT datac (339:339:339) (359:359:359)) - (PORT datad (587:587:587) (601:601:601)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (394:394:394)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (175:175:175) (202:202:202)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (699:699:699)) - (PORT datab (929:929:929) (992:992:992)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1608:1608:1608) (1611:1611:1611)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1227:1227:1227) (1243:1243:1243)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1190:1190:1190) (1197:1197:1197)) - (PORT datab (1236:1236:1236) (1275:1275:1275)) - (PORT datad (664:664:664) (688:688:688)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (275:275:275)) - (PORT datac (613:613:613) (632:632:632)) - (PORT datad (219:219:219) (288:288:288)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (670:670:670)) - (PORT datab (1331:1331:1331) (1335:1335:1335)) - (PORT datac (192:192:192) (224:224:224)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[5\]) - (DELAY - (ABSOLUTE - (PORT datac (653:653:653) (693:693:693)) - (PORT datad (834:834:834) (843:843:843)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2152:2152:2152) (2220:2220:2220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~4) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (994:994:994)) - (PORT datab (1154:1154:1154) (1178:1178:1178)) - (PORT datac (960:960:960) (1026:1026:1026)) - (PORT datad (362:362:362) (387:387:387)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (687:687:687)) - (PORT datab (1161:1161:1161) (1198:1198:1198)) - (PORT datac (811:811:811) (865:865:865)) - (PORT datad (615:615:615) (643:643:643)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1676:1676:1676) (1684:1684:1684)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1342:1342:1342) (1345:1345:1345)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (918:918:918)) - (PORT datab (966:966:966) (1020:1020:1020)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (1896:1896:1896) (1881:1881:1881)) - (PORT ena (1477:1477:1477) (1472:1472:1472)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (1893:1893:1893) (1878:1878:1878)) - (PORT ena (1247:1247:1247) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (1092:1092:1092) (1133:1133:1133)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (654:654:654) (676:676:676)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (2168:2168:2168) (2154:2154:2154)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1053:1053:1053) (1073:1073:1073)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (435:435:435) (470:470:470)) - (PORT datab (637:637:637) (669:669:669)) - (PORT datad (374:374:374) (432:432:432)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1463:1463:1463) (1454:1454:1454)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (689:689:689) (771:771:771)) - (PORT datab (945:945:945) (995:995:995)) - (PORT datac (878:878:878) (894:894:894)) - (PORT datad (606:606:606) (625:625:625)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (2168:2168:2168) (2153:2153:2153)) - (PORT ena (1499:1499:1499) (1507:1507:1507)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1302:1302:1302) (1310:1310:1310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1608:1608:1608) (1628:1628:1628)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (503:503:503)) - (PORT datab (242:242:242) (324:324:324)) - (PORT datad (640:640:640) (666:666:666)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) - (DELAY - (ABSOLUTE - (PORT datab (1410:1410:1410) (1425:1425:1425)) - (PORT datad (563:563:563) (574:574:574)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) - (DELAY - (ABSOLUTE - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1342:1342:1342) (1366:1366:1366)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1430:1430:1430) (1466:1466:1466)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (471:471:471)) - (PORT datab (584:584:584) (622:622:622)) - (PORT datad (835:835:835) (900:900:900)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (399:399:399)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (794:794:794) (791:791:791)) - (PORT datad (776:776:776) (774:774:774)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (625:625:625)) - (PORT datab (658:658:658) (716:716:716)) - (PORT datac (1393:1393:1393) (1416:1416:1416)) - (PORT datad (599:599:599) (618:618:618)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (967:967:967) (1025:1025:1025)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1322:1322:1322) (1350:1350:1350)) - (PORT datab (1232:1232:1232) (1270:1270:1270)) - (PORT datad (660:660:660) (687:687:687)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (673:673:673) (705:705:705)) - (PORT datac (668:668:668) (749:749:749)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (760:760:760)) - (PORT datab (648:648:648) (689:689:689)) - (PORT datac (926:926:926) (965:965:965)) - (PORT datad (593:593:593) (644:644:644)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[6\]) - (DELAY - (ABSOLUTE - (PORT datac (652:652:652) (694:694:694)) - (PORT datad (819:819:819) (838:838:838)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2152:2152:2152) (2220:2220:2220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (670:670:670)) - (PORT datab (632:632:632) (673:673:673)) - (PORT datac (811:811:811) (863:863:863)) - (PORT datad (1165:1165:1165) (1193:1193:1193)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (1158:1158:1158) (1194:1194:1194)) - (PORT datac (628:628:628) (651:651:651)) - (PORT datad (616:616:616) (644:644:644)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (515:515:515)) - (PORT datad (190:190:190) (222:222:222)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (708:708:708) (752:752:752)) - (PORT datab (962:962:962) (1002:1002:1002)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (619:619:619) (645:645:645)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (1212:1212:1212) (1251:1251:1251)) - (PORT ena (1477:1477:1477) (1472:1472:1472)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (1211:1211:1211) (1254:1254:1254)) - (PORT ena (1247:1247:1247) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (1092:1092:1092) (1137:1137:1137)) - (PORT datab (243:243:243) (325:325:325)) - (PORT datad (656:656:656) (679:679:679)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1408:1408:1408) (1437:1437:1437)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1410:1410:1410) (1439:1439:1439)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (876:876:876) (924:924:924)) - (PORT datab (963:963:963) (1013:1013:1013)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1934:1934:1934) (1968:1968:1968)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1624:1624:1624) (1645:1645:1645)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (435:435:435) (469:469:469)) - (PORT datab (636:636:636) (669:669:669)) - (PORT datad (370:370:370) (429:429:429)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1932:1932:1932) (1967:1967:1967)) - (PORT ena (1499:1499:1499) (1507:1507:1507)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1954:1954:1954) (1989:1989:1989)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1954:1954:1954) (1989:1989:1989)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (459:459:459) (495:495:495)) - (PORT datab (241:241:241) (322:322:322)) - (PORT datad (640:640:640) (664:664:664)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) - (DELAY - (ABSOLUTE - (PORT datab (1411:1411:1411) (1427:1427:1427)) - (PORT datad (587:587:587) (598:598:598)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1731:1731:1731) (1772:1772:1772)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1730:1730:1730) (1774:1774:1774)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (407:407:407) (467:467:467)) - (PORT datab (591:591:591) (631:631:631)) - (PORT datad (216:216:216) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1463:1463:1463) (1454:1454:1454)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (738:738:738)) - (PORT datab (944:944:944) (996:996:996)) - (PORT datac (844:844:844) (845:845:845)) - (PORT datad (606:606:606) (623:623:623)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (496:496:496) (503:503:503)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (364:364:364) (385:385:385)) - (PORT datad (573:573:573) (586:586:586)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~92) - (DELAY - (ABSOLUTE - (PORT dataa (667:667:667) (723:723:723)) - (PORT datab (660:660:660) (704:704:704)) - (PORT datac (1391:1391:1391) (1414:1414:1414)) - (PORT datad (597:597:597) (618:618:618)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[7\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1484:1484:1484) (1528:1528:1528)) - (PORT datab (1645:1645:1645) (1711:1711:1711)) - (PORT datac (872:872:872) (914:914:914)) - (PORT datad (1163:1163:1163) (1203:1203:1203)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im2) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1550:1550:1550)) - (PORT ena (1258:1258:1258) (1280:1280:1280)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (492:492:492)) - (PORT datac (1227:1227:1227) (1295:1295:1295)) - (PORT datad (274:274:274) (356:356:356)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (494:494:494)) - (PORT datab (716:716:716) (747:747:747)) - (PORT datac (192:192:192) (224:224:224)) - (PORT datad (1301:1301:1301) (1395:1395:1395)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (881:881:881) (903:903:903)) - (PORT datab (928:928:928) (957:957:957)) - (PORT datac (631:631:631) (687:687:687)) - (PORT datad (632:632:632) (647:647:647)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (841:841:841) (861:861:861)) - (PORT datab (852:852:852) (879:879:879)) - (PORT datac (900:900:900) (940:940:940)) - (PORT datad (639:639:639) (700:700:700)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datab (244:244:244) (291:291:291)) - (PORT datac (645:645:645) (698:698:698)) - (PORT datad (617:617:617) (628:628:628)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (693:693:693) (738:738:738)) - (PORT datab (889:889:889) (932:932:932)) - (PORT datac (869:869:869) (862:862:862)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1252:1252:1252) (1344:1344:1344)) - (PORT datab (857:857:857) (911:911:911)) - (PORT datac (614:614:614) (652:652:652)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (843:843:843) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1466:1466:1466) (1594:1594:1594)) - (PORT datab (1469:1469:1469) (1553:1553:1553)) - (PORT datac (1102:1102:1102) (1148:1148:1148)) - (PORT datad (647:647:647) (684:684:684)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1119:1119:1119) (1156:1156:1156)) - (PORT datab (747:747:747) (772:772:772)) - (PORT datac (1394:1394:1394) (1464:1464:1464)) - (PORT datad (1189:1189:1189) (1225:1225:1225)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (1006:1006:1006)) - (PORT datab (1150:1150:1150) (1220:1220:1220)) - (PORT datac (733:733:733) (829:829:829)) - (PORT datad (1883:1883:1883) (2044:2044:2044)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (737:737:737) (802:802:802)) - (PORT datab (1392:1392:1392) (1509:1509:1509)) - (PORT datac (1112:1112:1112) (1157:1157:1157)) - (PORT datad (198:198:198) (235:235:235)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (653:653:653) (668:668:668)) - (PORT datab (819:819:819) (840:840:840)) - (PORT datac (1123:1123:1123) (1137:1137:1137)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (696:696:696)) - (PORT datab (1031:1031:1031) (1083:1083:1083)) - (PORT datac (562:562:562) (584:584:584)) - (PORT datad (901:901:901) (957:957:957)) + (PORT dataa (1212:1212:1212) (1288:1288:1288)) + (PORT datab (627:627:627) (676:676:676)) + (PORT datac (1171:1171:1171) (1187:1187:1187)) + (PORT datad (1954:1954:1954) (2068:2068:2068)) (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -26362,47 +3827,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (INSTANCE z80_\|execute_\|fIOWrite\~0) (DELAY (ABSOLUTE - (PORT dataa (704:704:704) (741:741:741)) - (PORT datab (618:618:618) (633:633:633)) - (PORT datac (237:237:237) (315:315:315)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1120:1120:1120) (1156:1156:1156)) - (PORT datab (746:746:746) (770:770:770)) - (PORT datac (899:899:899) (956:956:956)) - (PORT datad (1169:1169:1169) (1206:1206:1206)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1433:1433:1433) (1488:1488:1488)) - (PORT datab (677:677:677) (711:711:711)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1402:1402:1402) (1440:1440:1440)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (1205:1205:1205) (1328:1328:1328)) + (PORT datab (1374:1374:1374) (1512:1512:1512)) + (PORT datac (2247:2247:2247) (2354:2354:2354)) + (PORT datad (2399:2399:2399) (2556:2556:2556)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -26410,157 +3843,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) + (INSTANCE z80_\|execute_\|fMWrite\~6) (DELAY (ABSOLUTE - (PORT dataa (1422:1422:1422) (1463:1463:1463)) - (PORT datab (746:746:746) (770:770:770)) - (PORT datac (1125:1125:1125) (1193:1193:1193)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (496:496:496)) - (PORT datab (268:268:268) (357:357:357)) - (PORT datac (230:230:230) (313:313:313)) - (PORT datad (609:609:609) (655:655:655)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (908:908:908)) - (PORT datab (730:730:730) (816:816:816)) - (PORT datad (395:395:395) (453:453:453)) + (PORT dataa (810:810:810) (885:885:885)) + (PORT datab (1869:1869:1869) (2005:2005:2005)) + (PORT datac (325:325:325) (347:347:347)) + (PORT datad (1684:1684:1684) (1756:1756:1756)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) - (DELAY - (ABSOLUTE - (PORT dataa (422:422:422) (513:513:513)) - (PORT datab (390:390:390) (465:465:465)) - (PORT datac (675:675:675) (735:735:735)) - (PORT datad (679:679:679) (752:752:752)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) - (DELAY - (ABSOLUTE - (PORT dataa (269:269:269) (367:367:367)) - (PORT datab (598:598:598) (665:665:665)) - (PORT datac (245:245:245) (334:334:334)) - (PORT datad (371:371:371) (425:425:425)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (599:599:599)) - (PORT datab (914:914:914) (923:923:923)) - (PORT datac (565:565:565) (580:580:580)) - (PORT datad (307:307:307) (323:323:323)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1424:1424:1424) (1466:1466:1466)) - (PORT datab (1535:1535:1535) (1597:1597:1597)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1559:1559:1559)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1118:1118:1118) (1158:1158:1158)) - (PORT datab (675:675:675) (710:710:710)) - (PORT datac (900:900:900) (960:960:960)) - (PORT datad (1167:1167:1167) (1206:1206:1206)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) - (DELAY - (ABSOLUTE - (PORT dataa (979:979:979) (1040:1040:1040)) - (PORT datab (271:271:271) (356:356:356)) - (PORT datac (1122:1122:1122) (1190:1190:1190)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -26568,202 +3859,59 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) + (INSTANCE z80_\|execute_\|ctl_mWrite\~8) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (746:746:746) (769:769:769)) - (PORT datac (1390:1390:1390) (1425:1425:1425)) - (PORT datad (245:245:245) (316:316:316)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1349:1349:1349) (1393:1393:1393)) + (PORT datab (650:650:650) (695:695:695)) + (PORT datac (2228:2228:2228) (2301:2301:2301)) + (PORT datad (2014:2014:2014) (2108:2108:2108)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~5) (DELAY (ABSOLUTE - (PORT clk (1518:1518:1518) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1287:1287:1287)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT dataa (1206:1206:1206) (1327:1327:1327)) + (PORT datab (1429:1429:1429) (1544:1544:1544)) + (PORT datac (2248:2248:2248) (2352:2352:2352)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) (DELAY (ABSOLUTE (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (545:545:545) (570:570:570)) - (PORT datab (213:213:213) (257:257:257)) - (PORT datac (177:177:177) (214:214:214)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (813:813:813) (826:826:826)) - (PORT datac (328:328:328) (358:358:358)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (381:381:381)) - (PORT datab (662:662:662) (697:697:697)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1118:1118:1118) (1161:1161:1161)) - (PORT datab (1154:1154:1154) (1224:1224:1224)) - (PORT datac (1392:1392:1392) (1427:1427:1427)) - (PORT datad (1169:1169:1169) (1209:1209:1209)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) - (DELAY - (ABSOLUTE - (PORT dataa (933:933:933) (998:998:998)) - (PORT datab (748:748:748) (772:772:772)) - (PORT datac (646:646:646) (675:675:675)) + (PORT datab (363:363:363) (394:394:394)) + (PORT datac (810:810:810) (838:838:838)) (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (1374:1374:1374) (1429:1429:1429)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~10) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (341:341:341) (367:367:367)) - (PORT datac (1214:1214:1214) (1255:1255:1255)) - (PORT datad (677:677:677) (698:698:698)) - (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) + (INSTANCE z80_\|execute_\|fMRead\~3) (DELAY (ABSOLUTE - (PORT dataa (922:922:922) (946:946:946)) - (PORT datab (2012:2012:2012) (2066:2066:2066)) - (PORT datac (919:919:919) (1015:1015:1015)) - (PORT datad (863:863:863) (877:877:877)) + (PORT dataa (1654:1654:1654) (1725:1725:1725)) + (PORT datac (907:907:907) (930:930:930)) + (PORT datad (1391:1391:1391) (1460:1460:1460)) (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~2) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (447:447:447)) - (PORT datab (1195:1195:1195) (1198:1198:1198)) - (PORT datac (601:601:601) (607:607:607)) - (PORT datad (334:334:334) (359:359:359)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -26771,1773 +3919,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_12) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) (DELAY (ABSOLUTE - (PORT dataa (825:825:825) (855:855:855)) - (PORT datad (337:337:337) (354:354:354)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (278:278:278)) - (PORT datab (223:223:223) (271:271:271)) - (PORT datac (616:616:616) (645:645:645)) - (PORT datad (216:216:216) (258:258:258)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (621:621:621)) - (PORT datab (686:686:686) (701:701:701)) - (PORT datac (562:562:562) (583:583:583)) - (PORT datad (312:312:312) (322:322:322)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (661:661:661)) - (PORT datab (654:654:654) (674:674:674)) - (PORT datac (240:240:240) (317:317:317)) - (PORT datad (385:385:385) (407:407:407)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (692:692:692)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (610:610:610) (651:651:651)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1530:1530:1530)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1244:1244:1244) (1250:1250:1250)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1638:1638:1638) (1703:1703:1703)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (884:884:884) (949:949:949)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (747:747:747)) - (PORT datab (659:659:659) (717:717:717)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1816:1816:1816) (1911:1911:1911)) - (PORT datab (2014:2014:2014) (2068:2068:2068)) - (PORT datad (173:173:173) (199:199:199)) + (PORT dataa (1571:1571:1571) (1642:1642:1642)) + (PORT datab (2001:2001:2001) (2042:2042:2042)) + (PORT datac (1133:1133:1133) (1159:1159:1159)) + (PORT datad (197:197:197) (223:223:223)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|flags_cond_true) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1527:1527:1527)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (663:663:663)) - (PORT datab (1772:1772:1772) (1863:1863:1863)) - (PORT datac (1815:1815:1815) (1893:1893:1893)) - (PORT datad (552:552:552) (570:570:570)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (256:256:256)) - (PORT datab (230:230:230) (280:280:280)) - (PORT datac (563:563:563) (592:592:592)) - (PORT datad (181:181:181) (211:211:211)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (905:905:905)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datac (623:623:623) (650:650:650)) - (PORT datad (1193:1193:1193) (1247:1247:1247)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (658:658:658)) - (PORT datab (949:949:949) (994:994:994)) - (PORT datad (671:671:671) (699:699:699)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (694:694:694)) - (PORT datab (517:517:517) (537:537:537)) - (PORT datac (742:742:742) (744:744:744)) - (PORT datad (1107:1107:1107) (1107:1107:1107)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (545:545:545) (573:573:573)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (580:580:580) (606:606:606)) - (PORT datad (621:621:621) (643:643:643)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (242:242:242)) - (PORT datab (259:259:259) (310:310:310)) - (PORT datac (607:607:607) (617:617:617)) - (PORT datad (236:236:236) (276:276:276)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1881:1881:1881) (1885:1885:1885)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1836:1836:1836) (1841:1841:1841)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (434:434:434) (465:465:465)) - (PORT datab (378:378:378) (448:448:448)) - (PORT datad (608:608:608) (629:629:629)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1836:1836:1836) (1841:1841:1841)) - (PORT ena (1499:1499:1499) (1507:1507:1507)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (2122:2122:2122) (2138:2138:2138)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT asdata (2124:2124:2124) (2160:2160:2160)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (498:498:498)) - (PORT datab (667:667:667) (706:706:706)) - (PORT datad (632:632:632) (685:685:685)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (1411:1411:1411) (1423:1423:1423)) - (PORT datad (585:585:585) (594:594:594)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1880:1880:1880) (1884:1884:1884)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (709:709:709)) - (PORT datab (945:945:945) (994:994:994)) - (PORT datac (888:888:888) (910:910:910)) - (PORT datad (609:609:609) (625:625:625)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1630:1630:1630) (1644:1644:1644)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (823:823:823) (864:864:864)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (473:473:473)) - (PORT datab (583:583:583) (621:621:621)) - (PORT datad (584:584:584) (628:628:628)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (551:551:551) (556:556:556)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1532:1532:1532) (1549:1549:1549)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1857:1857:1857) (1863:1863:1863)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (328:328:328)) - (PORT datab (962:962:962) (1016:1016:1016)) - (PORT datad (847:847:847) (873:873:873)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (712:712:712) (740:740:740)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (712:712:712) (740:740:740)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (329:329:329)) - (PORT datab (263:263:263) (316:316:316)) - (PORT datad (234:234:234) (273:273:273)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (684:684:684) (726:726:726)) - (PORT datab (635:635:635) (674:674:674)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1349:1349:1349) (1373:1373:1373)) - (PORT datab (623:623:623) (653:653:653)) - (PORT datac (643:643:643) (694:694:694)) - (PORT datad (308:308:308) (323:323:323)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1481:1481:1481) (1531:1531:1531)) - (PORT datab (1644:1644:1644) (1715:1715:1715)) - (PORT datac (1522:1522:1522) (1538:1538:1538)) - (PORT datad (1165:1165:1165) (1205:1205:1205)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (978:978:978) (996:996:996)) - (PORT datab (878:878:878) (913:913:913)) - (PORT datac (923:923:923) (978:978:978)) - (PORT datad (879:879:879) (914:914:914)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (696:696:696) (721:721:721)) - (PORT datab (1150:1150:1150) (1186:1186:1186)) - (PORT datac (887:887:887) (975:975:975)) - (PORT datad (1184:1184:1184) (1219:1219:1219)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (248:248:248)) - (PORT datab (943:943:943) (996:996:996)) - (PORT datac (648:648:648) (674:674:674)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1303:1303:1303) (1352:1352:1352)) - (PORT datab (933:933:933) (975:975:975)) - (PORT datac (1446:1446:1446) (1491:1491:1491)) - (PORT datad (926:926:926) (983:983:983)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (248:248:248)) - (PORT datab (986:986:986) (1033:1033:1033)) - (PORT datac (900:900:900) (933:933:933)) - (PORT datad (222:222:222) (267:267:267)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1695:1695:1695) (1783:1783:1783)) - (PORT datac (897:897:897) (925:925:925)) - (PORT datad (364:364:364) (385:385:385)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (926:926:926) (952:952:952)) - (PORT datad (237:237:237) (274:274:274)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1212:1212:1212)) - (PORT datab (286:286:286) (347:347:347)) - (PORT datac (254:254:254) (311:311:311)) - (PORT datad (254:254:254) (300:300:300)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (432:432:432) (525:525:525)) - (PORT datab (1170:1170:1170) (1217:1217:1217)) - (PORT datac (1156:1156:1156) (1212:1212:1212)) - (PORT datad (661:661:661) (724:724:724)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1535:1535:1535)) - (PORT asdata (672:672:672) (698:698:698)) - (PORT ena (1283:1283:1283) (1287:1287:1287)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (638:638:638)) - (PORT datab (368:368:368) (389:389:389)) - (PORT datad (1139:1139:1139) (1146:1146:1146)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (597:597:597)) - (PORT datab (220:220:220) (258:258:258)) - (PORT datac (1124:1124:1124) (1146:1146:1146)) - (PORT datad (335:335:335) (355:355:355)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1292:1292:1292) (1345:1345:1345)) - (PORT datab (915:915:915) (937:937:937)) - (PORT datac (1123:1123:1123) (1144:1144:1144)) - (PORT datad (945:945:945) (995:995:995)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (964:964:964) (1020:1020:1020)) - (PORT datac (806:806:806) (813:813:813)) - (PORT datad (227:227:227) (273:273:273)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (999:999:999)) - (PORT datac (1663:1663:1663) (1739:1739:1739)) - (PORT datad (1415:1415:1415) (1442:1442:1442)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datac (902:902:902) (931:931:931)) - (PORT datad (239:239:239) (281:281:281)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1211:1211:1211)) - (PORT datab (286:286:286) (349:349:349)) - (PORT datac (255:255:255) (313:313:313)) - (PORT datad (248:248:248) (293:293:293)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (671:671:671) (728:728:728)) - (PORT datab (1171:1171:1171) (1217:1217:1217)) - (PORT datac (615:615:615) (673:673:673)) - (PORT datad (661:661:661) (723:723:723)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1535:1535:1535)) - (PORT asdata (1127:1127:1127) (1132:1132:1132)) - (PORT ena (1283:1283:1283) (1287:1287:1287)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (549:549:549) (578:578:578)) - (PORT datab (331:331:331) (362:362:362)) - (PORT datad (1138:1138:1138) (1145:1145:1145)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (703:703:703)) - (PORT datab (359:359:359) (389:389:389)) - (PORT datac (797:797:797) (800:800:800)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (588:588:588) (619:619:619)) - (PORT datab (968:968:968) (1015:1015:1015)) - (PORT datac (371:371:371) (403:403:403)) - (PORT datad (863:863:863) (917:917:917)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (681:681:681) (721:721:721)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (264:264:264) (346:346:346)) - (PORT datac (235:235:235) (311:311:311)) - (PORT datad (235:235:235) (303:303:303)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) - (DELAY - (ABSOLUTE - (PORT datac (852:852:852) (861:861:861)) - (PORT datad (679:679:679) (700:700:700)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (690:690:690) (732:732:732)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datad (621:621:621) (632:632:632)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_hf2) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1183:1183:1183) (1231:1231:1231)) - (PORT datab (681:681:681) (697:697:697)) - (PORT datac (1123:1123:1123) (1203:1203:1203)) - (PORT datad (667:667:667) (721:721:721)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1196:1196:1196) (1252:1252:1252)) - (PORT datab (1640:1640:1640) (1708:1708:1708)) - (PORT datac (1440:1440:1440) (1482:1482:1482)) - (PORT datad (844:844:844) (890:890:890)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (686:686:686)) - (PORT datab (928:928:928) (956:956:956)) - (PORT datac (630:630:630) (688:688:688)) - (PORT datad (848:848:848) (847:847:847)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (856:856:856)) - (PORT datab (904:904:904) (946:946:946)) - (PORT datac (412:412:412) (479:479:479)) - (PORT datad (832:832:832) (862:862:862)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (712:712:712)) - (PORT datab (943:943:943) (996:996:996)) - (PORT datac (576:576:576) (598:598:598)) - (PORT datad (316:316:316) (337:337:337)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1305:1305:1305) (1357:1357:1357)) - (PORT datab (967:967:967) (1024:1024:1024)) - (PORT datac (922:922:922) (952:952:952)) - (PORT datad (1557:1557:1557) (1610:1610:1610)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (642:642:642)) - (PORT datab (987:987:987) (1034:1034:1034)) - (PORT datac (175:175:175) (210:210:210)) - (PORT datad (221:221:221) (266:266:266)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1693:1693:1693) (1778:1778:1778)) - (PORT datab (916:916:916) (942:942:942)) - (PORT datac (904:904:904) (929:929:929)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1446:1446:1446) (1487:1487:1487)) - (PORT datab (1129:1129:1129) (1183:1183:1183)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (234:234:234) (275:275:275)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (274:274:274)) - (PORT datab (246:246:246) (301:301:301)) - (PORT datac (617:617:617) (647:647:647)) - (PORT datad (845:845:845) (875:875:875)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (549:549:549) (580:580:580)) - (PORT datab (714:714:714) (753:753:753)) - (PORT datac (601:601:601) (608:608:608)) - (PORT datad (865:865:865) (915:915:915)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (718:718:718)) - (PORT datab (1128:1128:1128) (1175:1175:1175)) - (PORT datac (587:587:587) (617:617:617)) - (PORT datad (401:401:401) (459:459:459)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (261:261:261) (336:336:336)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (559:559:559) (578:578:578)) - (PORT datad (903:903:903) (954:954:954)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (460:460:460) (538:538:538)) - (PORT datab (638:638:638) (705:705:705)) - (PORT datac (1102:1102:1102) (1133:1133:1133)) - (PORT datad (662:662:662) (719:719:719)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1287:1287:1287)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (368:368:368)) - (PORT datab (597:597:597) (636:636:636)) - (PORT datac (965:965:965) (999:999:999)) - (PORT datad (590:590:590) (645:645:645)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (276:276:276)) - (PORT datab (653:653:653) (675:675:675)) - (PORT datac (916:916:916) (949:949:949)) - (PORT datad (220:220:220) (264:264:264)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (263:263:263) (337:337:337)) - (PORT datab (596:596:596) (614:614:614)) - (PORT datac (585:585:585) (589:589:589)) - (PORT datad (896:896:896) (944:944:944)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (534:534:534)) - (PORT datab (695:695:695) (720:720:720)) - (PORT datac (877:877:877) (900:900:900)) - (PORT datad (417:417:417) (490:490:490)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (411:411:411)) - (PORT datab (395:395:395) (424:424:424)) - (PORT datac (177:177:177) (214:214:214)) - (PORT datad (345:345:345) (368:368:368)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (407:407:407)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (354:354:354) (383:383:383)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1176:1176:1176) (1207:1207:1207)) - (PORT datab (281:281:281) (344:344:344)) - (PORT datac (244:244:244) (303:303:303)) - (PORT datad (255:255:255) (301:301:301)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1695:1695:1695) (1779:1779:1779)) - (PORT datac (887:887:887) (904:904:904)) - (PORT datad (883:883:883) (900:900:900)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (911:911:911) (960:960:960)) - (PORT datad (237:237:237) (277:277:277)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (711:711:711)) - (PORT datab (1166:1166:1166) (1213:1213:1213)) - (PORT datac (421:421:421) (493:493:493)) - (PORT datad (662:662:662) (719:719:719)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (1116:1116:1116) (1164:1164:1164)) - (PORT datac (603:603:603) (622:622:622)) - (PORT datad (629:629:629) (654:654:654)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1253:1253:1253) (1347:1347:1347)) - (PORT datab (239:239:239) (295:295:295)) - (PORT datac (959:959:959) (993:993:993)) - (PORT datad (329:329:329) (348:348:348)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1295:1295:1295) (1347:1347:1347)) - (PORT datab (963:963:963) (1021:1021:1021)) - (PORT datac (1621:1621:1621) (1653:1653:1653)) - (PORT datad (867:867:867) (886:886:886)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (667:667:667)) - (PORT datab (983:983:983) (1034:1034:1034)) - (PORT datac (313:313:313) (343:343:343)) - (PORT datad (228:228:228) (273:273:273)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (465:465:465)) - (PORT datab (263:263:263) (345:345:345)) - (PORT datac (236:236:236) (312:312:312)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1227:1227:1227)) - (PORT datab (658:658:658) (671:671:671)) - (PORT datac (632:632:632) (691:691:691)) - (PORT datad (234:234:234) (310:310:310)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1213:1213:1213)) - (PORT datab (894:894:894) (942:942:942)) - (PORT datac (660:660:660) (687:687:687)) - (PORT datad (883:883:883) (901:901:901)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (924:924:924) (933:933:933)) - (PORT datac (1121:1121:1121) (1153:1153:1153)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1018:1018:1018)) - (PORT datab (950:950:950) (1001:1001:1001)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (876:876:876) (911:911:911)) - (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (689:689:689) (714:714:714)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (1597:1597:1597) (1627:1627:1627)) - (PORT datad (861:861:861) (875:875:875)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (655:655:655)) - (PORT datab (1245:1245:1245) (1272:1272:1272)) - (PORT datac (1147:1147:1147) (1195:1195:1195)) - (PORT datad (336:336:336) (365:365:365)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) - (DELAY - (ABSOLUTE - (PORT datab (287:287:287) (348:348:348)) - (PORT datad (249:249:249) (295:295:295)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im1) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1550:1550:1550)) - (PORT ena (1258:1258:1258) (1280:1280:1280)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1215:1215:1215) (1260:1260:1260)) - (PORT datab (1208:1208:1208) (1291:1291:1291)) - (PORT datac (1222:1222:1222) (1290:1290:1290)) - (PORT datad (272:272:272) (349:349:349)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (485:485:485)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (1143:1143:1143) (1174:1174:1174)) - (PORT datad (1174:1174:1174) (1212:1212:1212)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (993:993:993) (1051:1051:1051)) - (PORT datab (1152:1152:1152) (1212:1212:1212)) - (PORT datac (671:671:671) (716:716:716)) - (PORT datad (621:621:621) (670:670:670)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (864:864:864) (885:885:885)) - (PORT datac (946:946:946) (986:986:986)) - (PORT datad (214:214:214) (249:249:249)) - (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28545,127 +3935,79 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~37) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) (DELAY (ABSOLUTE - (PORT dataa (1300:1300:1300) (1399:1399:1399)) - (PORT datab (2075:2075:2075) (2259:2259:2259)) - (PORT datac (822:822:822) (879:879:879)) - (PORT datad (913:913:913) (964:964:964)) + (PORT dataa (2683:2683:2683) (2764:2764:2764)) + (PORT datab (1030:1030:1030) (1061:1061:1061)) + (PORT datac (798:798:798) (876:876:876)) + (PORT datad (715:715:715) (740:740:740)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (624:624:624)) + (PORT datab (789:789:789) (834:834:834)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (1008:1008:1008)) + (PORT datab (1184:1184:1184) (1250:1250:1250)) + (PORT datac (1904:1904:1904) (1966:1966:1966)) + (PORT datad (644:644:644) (669:669:669)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1681:1681:1681) (1756:1756:1756)) + (PORT datab (574:574:574) (580:580:580)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (352:352:352) (375:375:375)) (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1269:1269:1269) (1304:1304:1304)) - (PORT datac (1404:1404:1404) (1456:1456:1456)) - (PORT datad (913:913:913) (977:977:977)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (241:241:241) (281:281:281)) - (PORT datac (1941:1941:1941) (2072:2072:2072)) - (PORT datad (187:187:187) (218:218:218)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (875:875:875) (914:914:914)) - (PORT datab (230:230:230) (277:277:277)) - (PORT datac (631:631:631) (653:653:653)) - (PORT datad (955:955:955) (999:999:999)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1051:1051:1051) (1095:1095:1095)) - (PORT datab (1067:1067:1067) (1105:1105:1105)) - (PORT datac (1033:1033:1033) (1064:1064:1064)) - (PORT datad (634:634:634) (644:644:644)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~55) - (DELAY - (ABSOLUTE - (PORT dataa (960:960:960) (1056:1056:1056)) - (PORT datab (1130:1130:1130) (1132:1132:1132)) - (PORT datac (939:939:939) (1031:1031:1031)) - (PORT datad (1060:1060:1060) (1062:1062:1062)) - (IOPATH dataa combout (303:303:303) (299:299:299)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~38) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) (DELAY (ABSOLUTE - (PORT dataa (888:888:888) (940:940:940)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (539:539:539) (555:555:555)) - (PORT datad (545:545:545) (556:556:556)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (715:715:715)) - (PORT datab (898:898:898) (929:929:929)) - (PORT datac (1980:1980:1980) (2019:2019:2019)) - (PORT datad (830:830:830) (842:842:842)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (379:379:379) (418:418:418)) + (PORT datab (925:925:925) (988:988:988)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1103:1103:1103) (1103:1103:1103)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28673,12 +4015,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~3) + (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) (DELAY (ABSOLUTE - (PORT datab (833:833:833) (894:894:894)) - (PORT datac (622:622:622) (675:675:675)) - (PORT datad (207:207:207) (239:239:239)) + (PORT datab (1374:1374:1374) (1494:1494:1494)) + (PORT datad (976:976:976) (1058:1058:1058)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (657:657:657)) + (PORT datab (814:814:814) (879:879:879)) + (PORT datac (1743:1743:1743) (1807:1807:1807)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -28687,29 +4043,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~31) + (INSTANCE z80_\|execute_\|fMWrite\~7) (DELAY (ABSOLUTE - (PORT dataa (231:231:231) (279:279:279)) - (PORT datab (238:238:238) (284:284:284)) - (PORT datac (356:356:356) (385:385:385)) - (PORT datad (1060:1060:1060) (1062:1062:1062)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (719:719:719) (787:787:787)) - (PORT datab (1609:1609:1609) (1627:1627:1627)) - (PORT datac (617:617:617) (649:649:649)) - (PORT datad (544:544:544) (562:562:562)) + (PORT dataa (1202:1202:1202) (1255:1255:1255)) + (PORT datab (805:805:805) (887:887:887)) + (PORT datac (798:798:798) (880:880:880)) + (PORT datad (889:889:889) (937:937:937)) (IOPATH dataa combout (341:341:341) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -28719,13 +4059,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~33) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) (DELAY (ABSOLUTE - (PORT datab (553:553:553) (575:575:575)) - (PORT datac (1318:1318:1318) (1317:1317:1317)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1253:1253:1253) (1284:1284:1284)) + (PORT datac (1036:1036:1036) (1054:1054:1054)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28733,92 +4075,88 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~35) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) (DELAY (ABSOLUTE - (PORT dataa (1048:1048:1048) (1070:1070:1070)) - (PORT datab (577:577:577) (591:591:591)) - (PORT datac (783:783:783) (785:785:785)) - (PORT datad (770:770:770) (770:770:770)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (872:872:872) (909:909:909)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (195:195:195) (229:229:229)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~15) (DELAY (ABSOLUTE - (PORT datad (815:815:815) (866:866:866)) + (PORT dataa (638:638:638) (656:656:656)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (353:353:353) (384:384:384)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mrd) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1588:1588:1588) (1565:1565:1565)) - (PORT ena (1172:1172:1172) (1151:1151:1151)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + (PORT datab (1558:1558:1558) (1645:1645:1645)) + (PORT datac (1678:1678:1678) (1754:1754:1754)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT asdata (1226:1226:1226) (1290:1290:1290)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~16) (DELAY (ABSOLUTE - (PORT dataa (909:909:909) (983:983:983)) - (PORT datad (215:215:215) (284:284:284)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (1366:1366:1366) (1468:1468:1468)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (1209:1209:1209) (1317:1317:1317)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1935:1935:1935) (2103:2103:2103)) + (PORT datac (1169:1169:1169) (1247:1247:1247)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~0) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (295:295:295)) + (PORT datab (1549:1549:1549) (1663:1663:1663)) + (PORT datac (1712:1712:1712) (1799:1799:1799)) + (PORT datad (1313:1313:1313) (1326:1326:1326)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -28828,10 +4166,10 @@ (INSTANCE z80_\|execute_\|nextM\~4) (DELAY (ABSOLUTE - (PORT dataa (233:233:233) (281:281:281)) - (PORT datab (702:702:702) (781:781:781)) - (PORT datac (856:856:856) (898:898:898)) - (PORT datad (1074:1074:1074) (1111:1111:1111)) + (PORT dataa (1524:1524:1524) (1519:1519:1519)) + (PORT datab (1191:1191:1191) (1249:1249:1249)) + (PORT datac (630:630:630) (682:682:682)) + (PORT datad (632:632:632) (687:687:687)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -28839,18 +4177,42 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT datac (1044:1044:1044) (1133:1133:1133)) + (PORT datad (1271:1271:1271) (1354:1354:1354)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2306:2306:2306) (2424:2424:2424)) + (PORT datac (1346:1346:1346) (1529:1529:1529)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_iorw\~12) (DELAY (ABSOLUTE - (PORT dataa (1890:1890:1890) (1960:1960:1960)) - (PORT datab (1472:1472:1472) (1522:1522:1522)) - (PORT datac (1489:1489:1489) (1536:1536:1536)) - (PORT datad (1919:1919:1919) (1985:1985:1985)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1886:1886:1886) (2000:2000:2000)) + (PORT datab (1612:1612:1612) (1752:1752:1752)) + (PORT datac (1469:1469:1469) (1530:1530:1530)) + (PORT datad (1053:1053:1053) (1100:1100:1100)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -28860,13 +4222,13 @@ (INSTANCE z80_\|execute_\|ctl_iorw\~8) (DELAY (ABSOLUTE - (PORT dataa (1104:1104:1104) (1152:1152:1152)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (201:201:201) (236:236:236)) - (PORT datad (679:679:679) (747:747:747)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (640:640:640) (658:658:658)) + (PORT datab (1360:1360:1360) (1377:1377:1377)) + (PORT datac (631:631:631) (639:639:639)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -28876,13 +4238,13 @@ (INSTANCE z80_\|execute_\|ctl_iorw\~9) (DELAY (ABSOLUTE - (PORT dataa (876:876:876) (891:891:891)) - (PORT datab (1170:1170:1170) (1227:1227:1227)) - (PORT datac (822:822:822) (840:840:840)) - (PORT datad (805:805:805) (814:814:814)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (1185:1185:1185) (1212:1212:1212)) + (PORT datab (661:661:661) (716:716:716)) + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (595:595:595) (628:628:628)) + (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -28892,10 +4254,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) + (PORT clk (1520:1520:1520) (1540:1540:1540)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) + (PORT clrn (1580:1580:1580) (1557:1557:1557)) + (PORT ena (1244:1244:1244) (1252:1252:1252)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -28905,43 +4267,15 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (220:220:220) (290:290:290)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorq) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT asdata (581:581:581) (655:655:655)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) + (PORT clk (1520:1520:1520) (1539:1539:1539)) + (PORT asdata (702:702:702) (770:770:770)) + (PORT clrn (1579:1579:1579) (1556:1556:1556)) + (PORT ena (1442:1442:1442) (1450:1450:1450)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -28951,15 +4285,43 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_iorq\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (655:655:655) (727:727:727)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorq) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1581:1581:1581) (1557:1557:1557)) + (PORT ena (1253:1253:1253) (1263:1263:1263)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) (DELAY (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT asdata (567:567:567) (645:645:645)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) + (PORT clk (1532:1532:1532) (1530:1530:1530)) + (PORT asdata (567:567:567) (643:643:643)) + (PORT clrn (1581:1581:1581) (1557:1557:1557)) + (PORT ena (1253:1253:1253) (1263:1263:1263)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -28974,8 +4336,8 @@ (INSTANCE z80_\|memory_ifc_\|iorq\~0) (DELAY (ABSOLUTE - (PORT datab (250:250:250) (335:335:335)) - (PORT datad (613:613:613) (663:663:663)) + (PORT datab (250:250:250) (333:333:333)) + (PORT datad (655:655:655) (722:722:722)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -28984,15 +4346,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~1) + (INSTANCE z80_\|pla_decode_\|Equal33\~2) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (941:941:941) (1024:1024:1024)) - (PORT datac (374:374:374) (401:401:401)) - (PORT datad (217:217:217) (243:243:243)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (1548:1548:1548) (1644:1644:1644)) + (PORT datac (1464:1464:1464) (1503:1503:1503)) + (PORT datad (1184:1184:1184) (1237:1237:1237)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29000,31 +4360,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~2) + (INSTANCE z80_\|execute_\|ixy_d\~17) (DELAY (ABSOLUTE - (PORT dataa (888:888:888) (913:913:913)) - (PORT datab (215:215:215) (260:260:260)) - (PORT datac (1187:1187:1187) (1208:1208:1208)) - (PORT datad (1091:1091:1091) (1137:1137:1137)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (229:229:229) (278:278:278)) + (PORT datab (221:221:221) (268:268:268)) + (PORT datac (996:996:996) (1082:1082:1082)) + (PORT datad (1499:1499:1499) (1549:1549:1549)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~0) + (INSTANCE z80_\|execute_\|ctl_mWrite\~15) (DELAY (ABSOLUTE - (PORT dataa (1889:1889:1889) (1932:1932:1932)) - (PORT datab (1525:1525:1525) (1597:1597:1597)) - (PORT datac (2202:2202:2202) (2248:2248:2248)) - (PORT datad (210:210:210) (242:242:242)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (1218:1218:1218) (1276:1276:1276)) + (PORT datab (1869:1869:1869) (1945:1945:1945)) + (PORT datac (1029:1029:1029) (1095:1095:1095)) + (PORT datad (1021:1021:1021) (1078:1078:1078)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29032,17 +4392,423 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~3) + (INSTANCE z80_\|execute_\|ctl_mWrite\~18) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (263:263:263)) - (PORT datab (336:336:336) (366:366:366)) - (PORT datac (586:586:586) (589:589:589)) - (PORT datad (351:351:351) (382:382:382)) + (PORT dataa (1764:1764:1764) (1856:1856:1856)) + (PORT datab (654:654:654) (690:690:690)) + (PORT datad (1598:1598:1598) (1743:1743:1743)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~12) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (958:958:958)) + (PORT datab (1244:1244:1244) (1298:1298:1298)) + (PORT datac (827:827:827) (870:870:870)) + (PORT datad (189:189:189) (219:219:219)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~21) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (1017:1017:1017)) + (PORT datab (993:993:993) (1040:1040:1040)) + (PORT datac (2018:2018:2018) (2124:2124:2124)) + (PORT datad (1484:1484:1484) (1600:1600:1600)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~20) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (687:687:687)) + (PORT datab (1506:1506:1506) (1597:1597:1597)) + (PORT datac (1719:1719:1719) (1859:1859:1859)) + (PORT datad (646:646:646) (663:663:663)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (658:658:658)) + (PORT datab (1777:1777:1777) (1839:1839:1839)) + (PORT datac (901:901:901) (951:951:951)) + (PORT datad (577:577:577) (582:582:582)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (640:640:640)) + (PORT datab (656:656:656) (693:693:693)) + (PORT datac (1397:1397:1397) (1513:1513:1513)) + (PORT datad (1771:1771:1771) (1867:1867:1867)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~10) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (674:674:674)) + (PORT datab (1187:1187:1187) (1225:1225:1225)) + (PORT datac (905:905:905) (945:945:945)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~13) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (647:647:647)) + (PORT datab (1785:1785:1785) (1851:1851:1851)) + (PORT datac (843:843:843) (884:884:884)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~9) + (DELAY + (ABSOLUTE + (PORT datab (2599:2599:2599) (2784:2784:2784)) + (PORT datac (2013:2013:2013) (2151:2151:2151)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1681:1681:1681) (1696:1696:1696)) + (PORT datab (1665:1665:1665) (1691:1691:1691)) + (PORT datac (1340:1340:1340) (1357:1357:1357)) + (PORT datad (1137:1137:1137) (1157:1157:1157)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) + (DELAY + (ABSOLUTE + (PORT dataa (934:934:934) (966:966:966)) + (PORT datab (1226:1226:1226) (1311:1311:1311)) + (PORT datac (667:667:667) (748:748:748)) + (PORT datad (672:672:672) (721:721:721)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) + (DELAY + (ABSOLUTE + (PORT dataa (689:689:689) (763:763:763)) + (PORT datab (205:205:205) (246:246:246)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1172:1172:1172) (1211:1211:1211)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1266:1266:1266) (1320:1320:1320)) + (PORT datab (1090:1090:1090) (1146:1146:1146)) + (PORT datac (1387:1387:1387) (1457:1457:1457)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1449:1449:1449) (1553:1553:1553)) + (PORT datab (1507:1507:1507) (1626:1626:1626)) + (PORT datac (1410:1410:1410) (1520:1520:1520)) + (PORT datad (1406:1406:1406) (1453:1453:1453)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~11) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (265:265:265)) + (PORT datab (640:640:640) (681:681:681)) + (PORT datac (1761:1761:1761) (1841:1841:1841)) + (PORT datad (650:650:650) (681:681:681)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~25) + (DELAY + (ABSOLUTE + (PORT datac (1195:1195:1195) (1279:1279:1279)) + (PORT datad (1192:1192:1192) (1245:1245:1245)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1453:1453:1453) (1558:1558:1558)) + (PORT datab (1151:1151:1151) (1192:1192:1192)) + (PORT datac (647:647:647) (693:693:693)) + (PORT datad (1478:1478:1478) (1588:1588:1588)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~24) + (DELAY + (ABSOLUTE + (PORT datac (1200:1200:1200) (1285:1285:1285)) + (PORT datad (1195:1195:1195) (1248:1248:1248)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (698:698:698)) + (PORT datab (247:247:247) (290:290:290)) + (PORT datac (913:913:913) (969:969:969)) + (PORT datad (845:845:845) (863:863:863)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~14) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (966:966:966)) + (PORT datab (897:897:897) (948:948:948)) + (PORT datac (882:882:882) (919:919:919)) + (PORT datad (593:593:593) (606:606:606)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1415:1415:1415) (1541:1541:1541)) + (PORT datad (1222:1222:1222) (1311:1311:1311)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~16) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (655:655:655)) + (PORT datab (821:821:821) (865:865:865)) + (PORT datac (1104:1104:1104) (1130:1130:1130)) + (PORT datad (2384:2384:2384) (2430:2430:2430)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1585:1585:1585) (1562:1562:1562)) + (PORT ena (1197:1197:1197) (1197:1197:1197)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (218:218:218) (288:288:288)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mwr) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1585:1585:1585) (1562:1562:1562)) + (PORT ena (1171:1171:1171) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|mwr_wr\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (882:882:882) (959:959:959)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|mwr_wr) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1581:1581:1581) (1557:1557:1557)) + (PORT ena (1253:1253:1253) (1263:1263:1263)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (275:275:275)) + (PORT datab (248:248:248) (331:331:331)) + (PORT datac (1026:1026:1026) (1073:1073:1073)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -29051,10 +4817,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff1) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1541:1541:1541)) + (PORT clk (1532:1532:1532) (1530:1530:1530)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1588:1588:1588) (1563:1563:1563)) - (PORT ena (1810:1810:1810) (1851:1851:1851)) + (PORT clrn (1581:1581:1581) (1557:1557:1557)) + (PORT ena (1253:1253:1253) (1263:1263:1263)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -29069,7 +4835,7 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1\~0) (DELAY (ABSOLUTE - (PORT datad (586:586:586) (642:642:642)) + (PORT datad (219:219:219) (287:287:287)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -29079,10 +4845,10 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1) (DELAY (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1530:1530:1530)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) + (PORT clrn (1581:1581:1581) (1557:1557:1557)) + (PORT ena (1253:1253:1253) (1263:1263:1263)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -29097,10 +4863,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff3) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) - (PORT asdata (568:568:568) (646:646:646)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) + (PORT clk (1521:1521:1521) (1541:1541:1541)) + (PORT asdata (566:566:566) (642:642:642)) + (PORT clrn (1581:1581:1581) (1557:1557:1557)) + (PORT ena (1280:1280:1280) (1296:1296:1296)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -29115,478 +4881,11 @@ (INSTANCE z80_\|memory_ifc_\|nRD_out\~0) (DELAY (ABSOLUTE - (PORT dataa (1456:1456:1456) (1520:1520:1520)) - (PORT datab (251:251:251) (336:336:336)) - (PORT datad (1485:1485:1485) (1574:1574:1574)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (376:376:376)) - (PORT datab (352:352:352) (391:391:391)) - (PORT datac (1027:1027:1027) (1030:1030:1030)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1747:1747:1747) (1852:1852:1852)) - (PORT datab (1597:1597:1597) (1730:1730:1730)) - (PORT datac (1200:1200:1200) (1265:1265:1265)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2395:2395:2395) (2551:2551:2551)) - (PORT datad (1014:1014:1014) (1128:1128:1128)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~5) - (DELAY - (ABSOLUTE - (PORT datab (1342:1342:1342) (1445:1445:1445)) - (PORT datac (2885:2885:2885) (3060:3060:3060)) - (PORT datad (2470:2470:2470) (2672:2672:2672)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (401:401:401)) - (PORT datab (883:883:883) (892:892:892)) - (PORT datac (957:957:957) (1029:1029:1029)) - (PORT datad (1073:1073:1073) (1058:1058:1058)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (1027:1027:1027)) - (PORT datac (1189:1189:1189) (1270:1270:1270)) - (PORT datad (2029:2029:2029) (2154:2154:2154)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1470:1470:1470) (1514:1514:1514)) - (PORT datab (897:897:897) (976:976:976)) - (PORT datac (362:362:362) (383:383:383)) - (PORT datad (193:193:193) (218:218:218)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (736:736:736)) - (PORT datab (837:837:837) (873:873:873)) - (PORT datac (876:876:876) (891:891:891)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1253:1253:1253) (1311:1311:1311)) - (PORT datab (870:870:870) (881:881:881)) - (PORT datac (1299:1299:1299) (1298:1298:1298)) - (PORT datad (625:625:625) (681:681:681)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (242:242:242)) - (PORT datab (1100:1100:1100) (1104:1104:1104)) - (PORT datac (369:369:369) (395:395:395)) - (PORT datad (1798:1798:1798) (1887:1887:1887)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~7) - (DELAY - (ABSOLUTE - (PORT datab (916:916:916) (964:964:964)) - (PORT datac (850:850:850) (896:896:896)) - (PORT datad (781:781:781) (791:791:791)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1515:1515:1515) (1583:1583:1583)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (1714:1714:1714) (1760:1760:1760)) - (PORT datad (881:881:881) (920:920:920)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1447:1447:1447) (1506:1506:1506)) - (PORT datab (1169:1169:1169) (1174:1174:1174)) - (PORT datac (894:894:894) (923:923:923)) - (PORT datad (781:781:781) (794:794:794)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1513:1513:1513) (1581:1581:1581)) - (PORT datab (1150:1150:1150) (1204:1204:1204)) - (PORT datac (1094:1094:1094) (1111:1111:1111)) - (PORT datad (616:616:616) (634:634:634)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1253:1253:1253) (1361:1361:1361)) - (PORT datab (869:869:869) (894:894:894)) - (PORT datac (1706:1706:1706) (1761:1761:1761)) - (PORT datad (263:263:263) (315:315:315)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1146:1146:1146) (1188:1188:1188)) - (PORT datab (214:214:214) (258:258:258)) - (PORT datac (192:192:192) (225:225:225)) - (PORT datad (621:621:621) (651:651:651)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (1051:1051:1051) (1068:1068:1068)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1101:1101:1101) (1104:1104:1104)) - (PORT datab (879:879:879) (888:888:888)) - (PORT datac (609:609:609) (624:624:624)) - (PORT datad (1198:1198:1198) (1221:1221:1221)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (927:927:927)) - (PORT datab (206:206:206) (246:246:246)) - (PORT datac (583:583:583) (601:601:601)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (332:332:332) (351:351:351)) - (PORT datad (813:813:813) (840:840:840)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~10) - (DELAY - (ABSOLUTE - (PORT dataa (881:881:881) (906:906:906)) - (PORT datab (1043:1043:1043) (1098:1098:1098)) - (PORT datac (1093:1093:1093) (1111:1111:1111)) - (PORT datad (1130:1130:1130) (1132:1132:1132)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (247:247:247)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (572:572:572) (605:605:605)) - (PORT datab (1113:1113:1113) (1136:1136:1136)) - (PORT datac (1714:1714:1714) (1760:1760:1760)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (1120:1120:1120) (1187:1187:1187)) + (PORT datab (249:249:249) (332:332:332)) + (PORT datad (1382:1382:1382) (1442:1442:1442)) (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (726:726:726)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (612:612:612) (639:639:639)) - (PORT datad (196:196:196) (220:220:220)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (930:930:930) (979:979:979)) - (PORT datac (1054:1054:1054) (1167:1167:1167)) - (PORT datad (1137:1137:1137) (1183:1183:1183)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|DFF_inst5\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (225:225:225) (296:296:296)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|DFF_inst5) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1587:1587:1587) (1563:1563:1563)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_iorqinta\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (228:228:228) (301:301:301)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1587:1587:1587) (1563:1563:1563)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1547:1547:1547)) - (PORT asdata (568:568:568) (647:647:647)) - (PORT clrn (1587:1587:1587) (1563:1563:1563)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (342:342:342)) - (PORT datad (605:605:605) (631:631:631)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29594,13 +4893,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal2\~0) + (INSTANCE z80_\|execute_\|ctl_mRead\~2) (DELAY (ABSOLUTE - (PORT dataa (1750:1750:1750) (1853:1853:1853)) - (PORT datab (1593:1593:1593) (1734:1734:1734)) - (PORT datac (1199:1199:1199) (1264:1264:1264)) - (PORT datad (1222:1222:1222) (1307:1307:1307)) + (PORT dataa (993:993:993) (1073:1073:1073)) + (PORT datab (236:236:236) (281:281:281)) + (PORT datac (1079:1079:1079) (1095:1095:1095)) + (PORT datad (1469:1469:1469) (1538:1538:1538)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -29610,13 +4909,289 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ExtRamWE\~0) + (INSTANCE z80_\|execute_\|fIORead\~0) (DELAY (ABSOLUTE - (PORT dataa (1747:1747:1747) (1852:1852:1852)) - (PORT datab (1597:1597:1597) (1730:1730:1730)) - (PORT datac (1200:1200:1200) (1265:1265:1265)) - (PORT datad (1220:1220:1220) (1307:1307:1307)) + (PORT dataa (1309:1309:1309) (1371:1371:1371)) + (PORT datab (927:927:927) (1024:1024:1024)) + (PORT datac (1164:1164:1164) (1225:1225:1225)) + (PORT datad (1430:1430:1430) (1462:1462:1462)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1747:1747:1747) (1845:1845:1845)) + (PORT datab (1652:1652:1652) (1803:1803:1803)) + (PORT datac (1044:1044:1044) (1103:1103:1103)) + (PORT datad (1815:1815:1815) (1893:1893:1893)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~4) + (DELAY + (ABSOLUTE + (PORT datab (1607:1607:1607) (1746:1746:1746)) + (PORT datad (1856:1856:1856) (1958:1958:1958)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) + (DELAY + (ABSOLUTE + (PORT dataa (259:259:259) (311:311:311)) + (PORT datab (1677:1677:1677) (1826:1826:1826)) + (PORT datac (1288:1288:1288) (1378:1378:1378)) + (PORT datad (2871:2871:2871) (2927:2927:2927)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~1) + (DELAY + (ABSOLUTE + (PORT dataa (259:259:259) (312:312:312)) + (PORT datab (927:927:927) (1024:1024:1024)) + (PORT datac (1164:1164:1164) (1225:1225:1225)) + (PORT datad (1753:1753:1753) (1784:1784:1784)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1132:1132:1132) (1179:1179:1179)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (1409:1409:1409) (1398:1398:1398)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1622:1622:1622) (1658:1658:1658)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) + (DELAY + (ABSOLUTE + (PORT dataa (448:448:448) (509:509:509)) + (PORT datad (602:602:602) (624:624:624)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_im_we) + (DELAY + (ABSOLUTE + (PORT dataa (1454:1454:1454) (1538:1538:1538)) + (PORT datab (1435:1435:1435) (1471:1471:1471)) + (PORT datac (1347:1347:1347) (1529:1529:1529)) + (PORT datad (2534:2534:2534) (2622:2622:2622)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im2) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (980:980:980) (1001:1001:1001)) + (PORT clrn (1577:1577:1577) (1557:1557:1557)) + (PORT ena (968:968:968) (972:972:972)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (447:447:447)) + (PORT datab (862:862:862) (915:915:915)) + (PORT datad (269:269:269) (350:350:350)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1545:1545:1545) (1642:1642:1642)) + (PORT datab (265:265:265) (310:310:310)) + (PORT datac (1461:1461:1461) (1499:1499:1499)) + (PORT datad (1184:1184:1184) (1243:1243:1243)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1684:1684:1684) (1788:1788:1788)) + (PORT datab (243:243:243) (287:287:287)) + (PORT datac (1764:1764:1764) (1827:1827:1827)) + (PORT datad (810:810:810) (866:866:866)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (451:451:451) (489:489:489)) + (PORT datab (1270:1270:1270) (1351:1351:1351)) + (PORT datac (1326:1326:1326) (1377:1377:1377)) + (PORT datad (651:651:651) (674:674:674)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~31) + (DELAY + (ABSOLUTE + (PORT datab (654:654:654) (678:678:678)) + (PORT datac (852:852:852) (873:873:873)) + (PORT datad (866:866:866) (881:881:881)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (474:474:474) (510:510:510)) + (PORT datab (1700:1700:1700) (1774:1774:1774)) + (PORT datac (1844:1844:1844) (1971:1971:1971)) + (PORT datad (788:788:788) (851:851:851)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) + (DELAY + (ABSOLUTE + (PORT datab (1461:1461:1461) (1510:1510:1510)) + (PORT datac (1183:1183:1183) (1237:1237:1237)) + (PORT datad (1434:1434:1434) (1514:1514:1514)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal44\~0) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (855:855:855)) + (PORT datab (768:768:768) (840:840:840)) + (PORT datac (1827:1827:1827) (1972:1972:1972)) + (PORT datad (1687:1687:1687) (1760:1760:1760)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~6) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (928:928:928)) + (PORT datab (1029:1029:1029) (1113:1113:1113)) + (PORT datac (1460:1460:1460) (1500:1500:1500)) + (PORT datad (1502:1502:1502) (1555:1555:1555)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -29626,12 +5201,25858 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) + (INSTANCE z80_\|execute_\|fMRead\~5) (DELAY (ABSOLUTE - (PORT dataa (1796:1796:1796) (1810:1810:1810)) - (PORT datab (849:849:849) (873:873:873)) - (PORT datad (335:335:335) (353:353:353)) + (PORT dataa (916:916:916) (960:960:960)) + (PORT datab (880:880:880) (969:969:969)) + (PORT datac (1051:1051:1051) (1088:1088:1088)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~17) + (DELAY + (ABSOLUTE + (PORT datab (631:631:631) (694:694:694)) + (PORT datac (802:802:802) (833:833:833)) + (PORT datad (852:852:852) (894:894:894)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1545:1545:1545) (1645:1645:1645)) + (PORT datac (1461:1461:1461) (1503:1503:1503)) + (PORT datad (1184:1184:1184) (1243:1243:1243)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal49\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1495:1495:1495) (1540:1540:1540)) + (PORT datab (958:958:958) (1015:1015:1015)) + (PORT datac (1200:1200:1200) (1255:1255:1255)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1231:1231:1231) (1240:1240:1240)) + (PORT datab (660:660:660) (687:687:687)) + (PORT datac (1667:1667:1667) (1700:1700:1700)) + (PORT datad (907:907:907) (984:984:984)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1812:1812:1812) (1880:1880:1880)) + (PORT datab (1075:1075:1075) (1143:1143:1143)) + (PORT datac (1721:1721:1721) (1798:1798:1798)) + (PORT datad (218:218:218) (257:257:257)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal25\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2132:2132:2132) (2307:2307:2307)) + (PORT datab (2626:2626:2626) (2718:2718:2718)) + (PORT datac (1370:1370:1370) (1475:1475:1475)) + (PORT datad (874:874:874) (899:899:899)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2265:2265:2265) (2343:2343:2343)) + (PORT datab (228:228:228) (270:270:270)) + (PORT datac (623:623:623) (663:663:663)) + (PORT datad (1014:1014:1014) (1053:1053:1053)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) + (DELAY + (ABSOLUTE + (PORT datab (1599:1599:1599) (1667:1667:1667)) + (PORT datac (1208:1208:1208) (1265:1265:1265)) + (PORT datad (1110:1110:1110) (1156:1156:1156)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1318:1318:1318) (1375:1375:1375)) + (PORT datab (970:970:970) (996:996:996)) + (PORT datac (1388:1388:1388) (1527:1527:1527)) + (PORT datad (1184:1184:1184) (1246:1246:1246)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~16) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (928:928:928)) + (PORT datab (1028:1028:1028) (1113:1113:1113)) + (PORT datac (1466:1466:1466) (1505:1505:1505)) + (PORT datad (1497:1497:1497) (1547:1547:1547)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (829:829:829) (834:834:834)) + (PORT datab (606:606:606) (630:630:630)) + (PORT datac (1624:1624:1624) (1671:1671:1671)) + (PORT datad (1597:1597:1597) (1618:1618:1618)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (703:703:703)) + (PORT datac (1119:1119:1119) (1126:1126:1126)) + (PORT datad (794:794:794) (865:865:865)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal29\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2137:2137:2137) (2307:2307:2307)) + (PORT datab (686:686:686) (711:711:711)) + (PORT datac (1044:1044:1044) (1121:1121:1121)) + (PORT datad (863:863:863) (904:904:904)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~38) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (407:407:407)) + (PORT datab (389:389:389) (421:421:421)) + (PORT datac (657:657:657) (706:706:706)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal35\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1421:1421:1421) (1449:1449:1449)) + (PORT datab (1932:1932:1932) (2005:2005:2005)) + (PORT datac (896:896:896) (938:938:938)) + (PORT datad (226:226:226) (261:261:261)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~33) + (DELAY + (ABSOLUTE + (PORT dataa (3083:3083:3083) (3178:3178:3178)) + (PORT datab (849:849:849) (890:890:890)) + (PORT datac (1445:1445:1445) (1544:1544:1544)) + (PORT datad (1991:1991:1991) (2046:2046:2046)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~1) + (DELAY + (ABSOLUTE + (PORT datab (1812:1812:1812) (1916:1916:1916)) + (PORT datad (2317:2317:2317) (2381:2381:2381)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (910:910:910)) + (PORT datab (393:393:393) (426:426:426)) + (PORT datac (1765:1765:1765) (1827:1827:1827)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1189:1189:1189) (1249:1249:1249)) + (PORT datab (1776:1776:1776) (1843:1843:1843)) + (PORT datac (593:593:593) (619:619:619)) + (PORT datad (613:613:613) (635:635:635)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (894:894:894) (917:917:917)) + (PORT datac (935:935:935) (977:977:977)) + (PORT datad (586:586:586) (595:595:595)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1910:1910:1910) (1994:1994:1994)) + (PORT datab (1648:1648:1648) (1797:1797:1797)) + (PORT datac (611:611:611) (649:649:649)) + (PORT datad (1744:1744:1744) (1826:1826:1826)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~36) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (901:901:901)) + (PORT datab (349:349:349) (382:382:382)) + (PORT datac (2016:2016:2016) (2128:2128:2128)) + (PORT datad (1098:1098:1098) (1111:1111:1111)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~14) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (275:275:275)) + (PORT datab (264:264:264) (310:310:310)) + (PORT datac (339:339:339) (366:366:366)) + (PORT datad (194:194:194) (230:230:230)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1164:1164:1164) (1218:1218:1218)) + (PORT datab (662:662:662) (682:682:682)) + (PORT datac (928:928:928) (996:996:996)) + (PORT datad (1139:1139:1139) (1210:1210:1210)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1684:1684:1684) (1791:1791:1791)) + (PORT datab (1366:1366:1366) (1397:1397:1397)) + (PORT datac (1763:1763:1763) (1830:1830:1830)) + (PORT datad (219:219:219) (255:255:255)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~39) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (624:624:624) (657:657:657)) + (PORT datad (827:827:827) (857:857:857)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1250:1250:1250)) + (PORT datab (366:366:366) (399:399:399)) + (PORT datac (1834:1834:1834) (1907:1907:1907)) + (PORT datad (603:603:603) (616:616:616)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2560:2560:2560) (2631:2631:2631)) + (PORT datab (2467:2467:2467) (2664:2664:2664)) + (PORT datad (1837:1837:1837) (1931:1931:1931)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1916:1916:1916) (2018:2018:2018)) + (PORT datab (894:894:894) (927:927:927)) + (PORT datac (1604:1604:1604) (1723:1723:1723)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1703:1703:1703) (1792:1792:1792)) + (PORT datab (1079:1079:1079) (1158:1158:1158)) + (PORT datac (897:897:897) (935:935:935)) + (PORT datad (225:225:225) (260:260:260)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (978:978:978)) + (PORT datab (1423:1423:1423) (1444:1444:1444)) + (PORT datac (618:618:618) (657:657:657)) + (PORT datad (823:823:823) (839:839:839)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1910:1910:1910) (1993:1993:1993)) + (PORT datab (1647:1647:1647) (1796:1796:1796)) + (PORT datac (610:610:610) (648:648:648)) + (PORT datad (1744:1744:1744) (1826:1826:1826)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (2257:2257:2257) (2334:2334:2334)) + (PORT datab (879:879:879) (911:911:911)) + (PORT datac (1573:1573:1573) (1705:1705:1705)) + (PORT datad (1688:1688:1688) (1747:1747:1747)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (940:940:940)) + (PORT datab (1609:1609:1609) (1651:1651:1651)) + (PORT datac (1191:1191:1191) (1251:1251:1251)) + (PORT datad (1658:1658:1658) (1714:1714:1714)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (728:728:728) (796:796:796)) + (PORT datab (1599:1599:1599) (1668:1668:1668)) + (PORT datac (1208:1208:1208) (1265:1265:1265)) + (PORT datad (1111:1111:1111) (1156:1156:1156)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2134:2134:2134) (2303:2303:2303)) + (PORT datab (1470:1470:1470) (1496:1496:1496)) + (PORT datac (1118:1118:1118) (1150:1150:1150)) + (PORT datad (645:645:645) (670:670:670)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~0) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (988:988:988)) + (PORT datab (557:557:557) (587:587:587)) + (PORT datac (569:569:569) (575:575:575)) + (PORT datad (573:573:573) (586:586:586)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~1) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (171:171:171) (202:202:202)) + (PORT datad (221:221:221) (250:250:250)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (956:956:956)) + (PORT datab (691:691:691) (757:757:757)) + (PORT datac (1338:1338:1338) (1342:1342:1342)) + (PORT datad (1183:1183:1183) (1212:1212:1212)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (954:954:954)) + (PORT datab (1459:1459:1459) (1512:1512:1512)) + (PORT datac (877:877:877) (900:900:900)) + (PORT datad (215:215:215) (248:248:248)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (919:919:919)) + (PORT datab (689:689:689) (761:761:761)) + (PORT datac (320:320:320) (344:344:344)) + (PORT datad (842:842:842) (871:871:871)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (686:686:686)) + (PORT datab (895:895:895) (931:931:931)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (882:882:882) (910:910:910)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~1) + (DELAY + (ABSOLUTE + (PORT dataa (474:474:474) (506:506:506)) + (PORT datab (1099:1099:1099) (1115:1115:1115)) + (PORT datac (742:742:742) (814:814:814)) + (PORT datad (730:730:730) (803:803:803)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (659:659:659)) + (PORT datab (660:660:660) (693:693:693)) + (PORT datac (576:576:576) (604:604:604)) + (PORT datad (663:663:663) (683:683:683)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (891:891:891)) + (PORT datab (616:616:616) (645:645:645)) + (PORT datac (1506:1506:1506) (1571:1571:1571)) + (PORT datad (192:192:192) (225:225:225)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (899:899:899) (928:928:928)) + (PORT datac (570:570:570) (592:592:592)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~3) + (DELAY + (ABSOLUTE + (PORT dataa (623:623:623) (660:660:660)) + (PORT datab (1247:1247:1247) (1277:1277:1277)) + (PORT datad (874:874:874) (919:919:919)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1203:1203:1203) (1236:1236:1236)) + (PORT datab (638:638:638) (670:670:670)) + (PORT datac (200:200:200) (236:236:236)) + (PORT datad (2384:2384:2384) (2430:2430:2430)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (835:835:835)) + (PORT datab (590:590:590) (599:599:599)) + (PORT datac (836:836:836) (870:870:870)) + (PORT datad (988:988:988) (1049:1049:1049)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1581:1581:1581) (1557:1557:1557)) + (PORT ena (1280:1280:1280) (1296:1296:1296)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (218:218:218) (287:287:287)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mrd) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1581:1581:1581) (1557:1557:1557)) + (PORT ena (1253:1253:1253) (1263:1263:1263)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (235:235:235) (312:312:312)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1581:1581:1581) (1557:1557:1557)) + (PORT ena (1253:1253:1253) (1263:1263:1263)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (249:249:249) (340:340:340)) + (PORT datad (234:234:234) (311:311:311)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (824:824:824) (842:842:842)) + (PORT datac (202:202:202) (240:240:240)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~1) + (DELAY + (ABSOLUTE + (PORT datab (1866:1866:1866) (2020:2020:2020)) + (PORT datac (3074:3074:3074) (3300:3300:3300)) + (PORT datad (2568:2568:2568) (2680:2680:2680)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_DAT\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (843:843:843) (859:859:859)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (373:373:373)) + (PORT datab (291:291:291) (383:383:383)) + (PORT datad (249:249:249) (334:334:334)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE PS2_CLK\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3310:3310:3310) (3637:3637:3637)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (228:228:228) (301:301:301)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (225:225:225) (298:298:298)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (227:227:227) (302:302:302)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (240:240:240) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (344:344:344)) + (PORT datab (250:250:250) (336:336:336)) + (PORT datac (375:375:375) (441:441:441)) + (PORT datad (226:226:226) (299:299:299)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (226:226:226) (298:298:298)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (228:228:228) (301:301:301)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (344:344:344)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (224:224:224) (304:304:304)) + (PORT datad (228:228:228) (301:301:301)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (225:225:225) (304:304:304)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) + (DELAY + (ABSOLUTE + (PORT dataa (256:256:256) (346:346:346)) + (PORT datad (183:183:183) (212:212:212)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) + (DELAY + (ABSOLUTE + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (225:225:225) (308:308:308)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|clk_edge) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1548:1548:1548) (1540:1540:1540)) + (PORT ena (2142:2142:2142) (2242:2242:2242)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (368:368:368)) + (PORT datab (277:277:277) (367:367:367)) + (PORT datad (249:249:249) (333:333:333)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1548:1548:1548) (1540:1540:1540)) + (PORT ena (2142:2142:2142) (2242:2242:2242)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (374:374:374)) + (PORT datab (293:293:293) (386:386:386)) + (PORT datad (250:250:250) (330:330:330)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1548:1548:1548) (1540:1540:1540)) + (PORT ena (2142:2142:2142) (2242:2242:2242)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (377:377:377)) + (PORT datab (289:289:289) (381:381:381)) + (PORT datad (247:247:247) (326:326:326)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1548:1548:1548) (1540:1540:1540)) + (PORT ena (2142:2142:2142) (2242:2242:2242)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (275:275:275) (373:373:373)) + (PORT datab (292:292:292) (384:384:384)) + (PORT datad (250:250:250) (329:329:329)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (373:373:373)) + (PORT datab (276:276:276) (369:369:369)) + (PORT datac (384:384:384) (445:445:445)) + (PORT datad (3313:3313:3313) (3645:3645:3645)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (368:368:368)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (1497:1497:1497) (1608:1608:1608)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT asdata (3641:3641:3641) (3987:3987:3987)) + (PORT clrn (1545:1545:1545) (1538:1538:1538)) + (PORT ena (1641:1641:1641) (1638:1638:1638)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT asdata (703:703:703) (765:765:765)) + (PORT clrn (1545:1545:1545) (1538:1538:1538)) + (PORT ena (1641:1641:1641) (1638:1638:1638)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT asdata (613:613:613) (718:718:718)) + (PORT clrn (1545:1545:1545) (1538:1538:1538)) + (PORT ena (1641:1641:1641) (1638:1638:1638)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT asdata (1312:1312:1312) (1370:1370:1370)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) + (PORT ena (1685:1685:1685) (1687:1687:1687)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT asdata (1237:1237:1237) (1318:1318:1318)) + (PORT clrn (1545:1545:1545) (1538:1538:1538)) + (PORT ena (1641:1641:1641) (1638:1638:1638)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT asdata (1368:1368:1368) (1443:1443:1443)) + (PORT clrn (1542:1542:1542) (1535:1535:1535)) + (PORT ena (1425:1425:1425) (1453:1453:1453)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT asdata (1184:1184:1184) (1233:1233:1233)) + (PORT clrn (1542:1542:1542) (1535:1535:1535)) + (PORT ena (1425:1425:1425) (1453:1453:1453)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT asdata (608:608:608) (699:699:699)) + (PORT clrn (1542:1542:1542) (1535:1535:1535)) + (PORT ena (1425:1425:1425) (1453:1453:1453)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT asdata (1274:1274:1274) (1331:1331:1331)) + (PORT clrn (1545:1545:1545) (1538:1538:1538)) + (PORT ena (1641:1641:1641) (1638:1638:1638)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (416:416:416)) + (PORT datab (930:930:930) (1010:1010:1010)) + (PORT datac (251:251:251) (336:336:336)) + (PORT datad (944:944:944) (1019:1019:1019)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (780:780:780) (879:879:879)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (927:927:927) (986:986:986)) + (PORT datad (264:264:264) (344:344:344)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (301:301:301) (422:422:422)) + (PORT datab (985:985:985) (1056:1056:1056)) + (PORT datad (264:264:264) (344:344:344)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (916:916:916) (985:985:985)) + (PORT datab (960:960:960) (1023:1023:1023)) + (PORT datad (755:755:755) (838:838:838)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) + (DELAY + (ABSOLUTE + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (236:236:236) (312:312:312)) + (PORT datad (311:311:311) (327:327:327)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) + (DELAY + (ABSOLUTE + (PORT dataa (672:672:672) (692:692:692)) + (PORT datab (3347:3347:3347) (3682:3682:3682)) + (PORT datac (1498:1498:1498) (1609:1609:1609)) + (PORT datad (185:185:185) (215:215:215)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1548:1548:1548) (1540:1540:1540)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|released\~0) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (714:714:714)) + (PORT datab (877:877:877) (947:947:947)) + (PORT datad (704:704:704) (775:775:775)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|released) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (795:795:795)) + (PORT datab (791:791:791) (877:877:877)) + (PORT datac (707:707:707) (797:797:797)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (729:729:729) (814:814:814)) + (PORT datad (750:750:750) (828:828:828)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|extended\~0) + (DELAY + (ABSOLUTE + (PORT dataa (698:698:698) (717:717:717)) + (PORT datad (699:699:699) (766:766:766)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|extended) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (PORT ena (1489:1489:1489) (1540:1540:1540)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (291:291:291) (409:409:409)) + (PORT datab (677:677:677) (741:741:741)) + (PORT datac (912:912:912) (970:970:970)) + (PORT datad (268:268:268) (348:348:348)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (690:690:690)) + (PORT datab (762:762:762) (850:850:850)) + (PORT datac (182:182:182) (219:219:219)) + (PORT datad (1129:1129:1129) (1155:1155:1155)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (436:436:436)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|clrpc_int\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1901:1901:1901) (2085:2085:2085)) + (PORT datab (1495:1495:1495) (1563:1563:1563)) + (PORT datad (1153:1153:1153) (1262:1262:1262)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|clrpc_int) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1542:1542:1542)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1931:1931:1931) (1907:1907:1907)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT datac (949:949:949) (997:997:997)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (225:225:225) (298:298:298)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1530:1530:1530)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1530:1530:1530)) + (PORT asdata (568:568:568) (646:646:646)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|clrpc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (728:728:728)) + (PORT datab (252:252:252) (337:337:337)) + (PORT datad (226:226:226) (299:299:299)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1278:1278:1278) (1382:1382:1382)) + (PORT datab (977:977:977) (1078:1078:1078)) + (PORT datac (624:624:624) (676:676:676)) + (PORT datad (886:886:886) (918:918:918)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1916:1916:1916) (2016:2016:2016)) + (PORT datab (1192:1192:1192) (1204:1204:1204)) + (PORT datac (1608:1608:1608) (1722:1722:1722)) + (PORT datad (856:856:856) (886:886:886)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1916:1916:1916) (2016:2016:2016)) + (PORT datab (893:893:893) (925:925:925)) + (PORT datac (1608:1608:1608) (1721:1721:1721)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1915:1915:1915) (2019:2019:2019)) + (PORT datab (1746:1746:1746) (1780:1780:1780)) + (PORT datac (1605:1605:1605) (1722:1722:1722)) + (PORT datad (856:856:856) (890:890:890)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (300:300:300)) + (PORT datac (256:256:256) (311:311:311)) + (PORT datad (245:245:245) (296:296:296)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (667:667:667)) + (PORT datac (1675:1675:1675) (1746:1746:1746)) + (PORT datad (1137:1137:1137) (1176:1176:1176)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (683:683:683)) + (PORT datac (621:621:621) (640:640:640)) + (PORT datad (1221:1221:1221) (1279:1279:1279)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (700:700:700)) + (PORT datab (1445:1445:1445) (1504:1504:1504)) + (PORT datac (586:586:586) (606:606:606)) + (PORT datad (1117:1117:1117) (1138:1138:1138)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (686:686:686)) + (PORT datab (939:939:939) (980:980:980)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (887:887:887) (909:909:909)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) + (DELAY + (ABSOLUTE + (PORT datab (1493:1493:1493) (1554:1554:1554)) + (PORT datac (1223:1223:1223) (1253:1253:1253)) + (PORT datad (1403:1403:1403) (1470:1470:1470)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1350:1350:1350) (1394:1394:1394)) + (PORT datab (1605:1605:1605) (1734:1734:1734)) + (PORT datac (622:622:622) (664:664:664)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1978:1978:1978) (2137:2137:2137)) + (PORT datab (2591:2591:2591) (2768:2768:2768)) + (PORT datad (1697:1697:1697) (1792:1792:1792)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1450:1450:1450) (1523:1523:1523)) + (PORT datab (976:976:976) (983:983:983)) + (PORT datac (868:868:868) (907:907:907)) + (PORT datad (918:918:918) (955:955:955)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) + (DELAY + (ABSOLUTE + (PORT dataa (2356:2356:2356) (2462:2462:2462)) + (PORT datac (1864:1864:1864) (1892:1892:1892)) + (PORT datad (1772:1772:1772) (1886:1886:1886)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (966:966:966) (1020:1020:1020)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1187:1187:1187) (1271:1271:1271)) + (PORT datab (627:627:627) (649:649:649)) + (PORT datac (902:902:902) (931:931:931)) + (PORT datad (859:859:859) (879:879:879)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (891:891:891) (925:925:925)) + (PORT datac (619:619:619) (660:660:660)) + (PORT datad (620:620:620) (668:668:668)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (907:907:907)) + (PORT datab (1517:1517:1517) (1628:1628:1628)) + (PORT datac (622:622:622) (674:674:674)) + (PORT datad (1219:1219:1219) (1277:1277:1277)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (185:185:185) (224:224:224)) + (PORT datad (1252:1252:1252) (1309:1309:1309)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~13) + (DELAY + (ABSOLUTE + (PORT datab (2733:2733:2733) (2908:2908:2908)) + (PORT datac (1737:1737:1737) (1813:1813:1813)) + (PORT datad (839:839:839) (867:867:867)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1578:1578:1578) (1687:1687:1687)) + (PORT datab (2007:2007:2007) (2122:2122:2122)) + (PORT datac (2198:2198:2198) (2304:2304:2304)) + (PORT datad (1762:1762:1762) (1853:1853:1853)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1771:1771:1771) (1876:1876:1876)) + (PORT datab (356:356:356) (392:392:392)) + (PORT datac (1865:1865:1865) (1919:1919:1919)) + (PORT datad (1599:1599:1599) (1746:1746:1746)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~16) + (DELAY + (ABSOLUTE + (PORT dataa (2343:2343:2343) (2509:2509:2509)) + (PORT datab (1128:1128:1128) (1167:1167:1167)) + (PORT datac (1549:1549:1549) (1649:1649:1649)) + (PORT datad (1983:1983:1983) (2085:2085:2085)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (931:931:931)) + (PORT datab (822:822:822) (869:869:869)) + (PORT datac (169:169:169) (202:202:202)) + (PORT datad (1639:1639:1639) (1711:1711:1711)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (287:287:287)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (650:650:650) (707:707:707)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1143:1143:1143) (1214:1214:1214)) + (PORT datab (849:849:849) (876:876:876)) + (PORT datac (1180:1180:1180) (1245:1245:1245)) + (PORT datad (894:894:894) (941:941:941)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1536:1536:1536) (1600:1600:1600)) + (PORT datab (1096:1096:1096) (1128:1128:1128)) + (PORT datac (1717:1717:1717) (1793:1793:1793)) + (PORT datad (1165:1165:1165) (1203:1203:1203)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1531:1531:1531) (1599:1599:1599)) + (PORT datab (216:216:216) (261:261:261)) + (PORT datac (1264:1264:1264) (1333:1333:1333)) + (PORT datad (1159:1159:1159) (1219:1219:1219)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~2) + (DELAY + (ABSOLUTE + (PORT dataa (277:277:277) (348:348:348)) + (PORT datab (250:250:250) (300:300:300)) + (PORT datac (248:248:248) (306:306:306)) + (PORT datad (1436:1436:1436) (1458:1458:1458)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (632:632:632)) + (PORT datab (853:853:853) (859:859:859)) + (PORT datac (371:371:371) (388:388:388)) + (PORT datad (899:899:899) (949:949:949)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (615:615:615)) + (PORT datab (226:226:226) (267:267:267)) + (PORT datac (1119:1119:1119) (1151:1151:1151)) + (PORT datad (880:880:880) (918:918:918)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1108:1108:1108) (1164:1164:1164)) + (PORT datab (229:229:229) (271:271:271)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal56\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1086:1086:1086) (1166:1166:1166)) + (PORT datab (2009:2009:2009) (2098:2098:2098)) + (PORT datac (1374:1374:1374) (1482:1482:1482)) + (PORT datad (1892:1892:1892) (1950:1950:1950)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1682:1682:1682) (1789:1789:1789)) + (PORT datab (654:654:654) (672:672:672)) + (PORT datac (1764:1764:1764) (1827:1827:1827)) + (PORT datad (1054:1054:1054) (1101:1101:1101)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1684:1684:1684) (1793:1793:1793)) + (PORT datab (653:653:653) (674:674:674)) + (PORT datac (1763:1763:1763) (1832:1832:1832)) + (PORT datad (1052:1052:1052) (1102:1102:1102)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1222:1222:1222) (1238:1238:1238)) + (PORT datab (886:886:886) (929:929:929)) + (PORT datac (942:942:942) (998:998:998)) + (PORT datad (944:944:944) (995:995:995)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (436:436:436)) + (PORT datab (948:948:948) (982:982:982)) + (PORT datac (584:584:584) (628:628:628)) + (PORT datad (223:223:223) (253:253:253)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (962:962:962)) + (PORT datab (942:942:942) (963:963:963)) + (PORT datac (638:638:638) (669:669:669)) + (PORT datad (1172:1172:1172) (1244:1244:1244)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (1052:1052:1052)) + (PORT datab (987:987:987) (1030:1030:1030)) + (PORT datac (1171:1171:1171) (1219:1219:1219)) + (PORT datad (986:986:986) (1036:1036:1036)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (673:673:673)) + (PORT datab (1462:1462:1462) (1514:1514:1514)) + (PORT datac (830:830:830) (908:908:908)) + (PORT datad (1914:1914:1914) (1984:1984:1984)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|nM1_int\~2) + (DELAY + (ABSOLUTE + (PORT datac (1322:1322:1322) (1471:1471:1471)) + (PORT datad (2189:2189:2189) (2361:2361:2361)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (881:881:881)) + (PORT datab (217:217:217) (263:263:263)) + (PORT datac (1159:1159:1159) (1177:1177:1177)) + (PORT datad (639:639:639) (677:677:677)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~94) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (999:999:999)) + (PORT datab (1472:1472:1472) (1516:1516:1516)) + (PORT datac (1410:1410:1410) (1502:1502:1502)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (645:645:645)) + (PORT datab (228:228:228) (270:270:270)) + (PORT datac (826:826:826) (838:838:838)) + (PORT datad (789:789:789) (845:845:845)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) + (DELAY + (ABSOLUTE + (PORT dataa (2006:2006:2006) (2078:2078:2078)) + (PORT datab (611:611:611) (626:626:626)) + (PORT datac (831:831:831) (870:870:870)) + (PORT datad (705:705:705) (742:742:742)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1665:1665:1665) (1731:1731:1731)) + (PORT datab (1778:1778:1778) (1843:1843:1843)) + (PORT datac (897:897:897) (948:948:948)) + (PORT datad (703:703:703) (737:737:737)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (936:936:936)) + (PORT datab (1991:1991:1991) (2053:2053:2053)) + (PORT datac (1786:1786:1786) (1813:1813:1813)) + (PORT datad (1444:1444:1444) (1438:1438:1438)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (644:644:644)) + (PORT datab (740:740:740) (777:777:777)) + (PORT datac (1151:1151:1151) (1208:1208:1208)) + (PORT datad (804:804:804) (817:817:817)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (658:658:658)) + (PORT datab (742:742:742) (780:780:780)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (607:607:607) (632:632:632)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (376:376:376)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1656:1656:1656) (1674:1674:1674)) + (PORT datab (832:832:832) (856:856:856)) + (PORT datac (874:874:874) (900:900:900)) + (PORT datad (583:583:583) (602:602:602)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1662:1662:1662) (1727:1727:1727)) + (PORT datab (609:609:609) (623:623:623)) + (PORT datac (171:171:171) (202:202:202)) + (PORT datad (1964:1964:1964) (2030:2030:2030)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (874:874:874)) + (PORT datab (1111:1111:1111) (1163:1163:1163)) + (PORT datac (760:760:760) (817:817:817)) + (PORT datad (648:648:648) (669:669:669)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~99) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (816:816:816)) + (PORT datab (2351:2351:2351) (2480:2480:2480)) + (PORT datac (750:750:750) (859:859:859)) + (PORT datad (1843:1843:1843) (1894:1894:1894)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (275:275:275)) + (PORT datab (615:615:615) (668:668:668)) + (PORT datac (355:355:355) (385:385:385)) + (PORT datad (820:820:820) (847:847:847)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) + (DELAY + (ABSOLUTE + (PORT datac (2110:2110:2110) (2222:2222:2222)) + (PORT datad (1649:1649:1649) (1827:1827:1827)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (265:265:265)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (886:886:886) (924:924:924)) + (PORT datad (364:364:364) (387:387:387)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (389:389:389)) + (PORT datab (613:613:613) (635:635:635)) + (PORT datac (585:585:585) (595:595:595)) + (PORT datad (816:816:816) (824:824:824)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (276:276:276) (346:346:346)) + (PORT datab (1766:1766:1766) (1810:1810:1810)) + (PORT datac (251:251:251) (310:310:310)) + (PORT datad (225:225:225) (265:265:265)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (1008:1008:1008)) + (PORT datab (964:964:964) (1028:1028:1028)) + (PORT datac (1904:1904:1904) (1967:1967:1967)) + (PORT datad (644:644:644) (671:671:671)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (1056:1056:1056)) + (PORT datab (1415:1415:1415) (1547:1547:1547)) + (PORT datac (943:943:943) (1040:1040:1040)) + (PORT datad (818:818:818) (824:824:824)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (717:717:717)) + (PORT datab (1612:1612:1612) (1652:1652:1652)) + (PORT datac (1279:1279:1279) (1317:1317:1317)) + (PORT datad (1153:1153:1153) (1159:1159:1159)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~5) + (DELAY + (ABSOLUTE + (PORT datac (1943:1943:1943) (2004:2004:2004)) + (PORT datad (2062:2062:2062) (2197:2197:2197)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (266:266:266)) + (PORT datab (1497:1497:1497) (1573:1573:1573)) + (PORT datac (1953:1953:1953) (2008:2008:2008)) + (PORT datad (206:206:206) (244:244:244)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal48\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1982:1982:1982) (2045:2045:2045)) + (PORT datab (2098:2098:2098) (2238:2238:2238)) + (PORT datac (1468:1468:1468) (1539:1539:1539)) + (PORT datad (211:211:211) (249:249:249)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1990:1990:1990) (2089:2089:2089)) + (PORT datab (1214:1214:1214) (1264:1264:1264)) + (PORT datac (1724:1724:1724) (1792:1792:1792)) + (PORT datad (935:935:935) (979:979:979)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1491:1491:1491) (1544:1544:1544)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (1386:1386:1386) (1421:1421:1421)) + (PORT datad (614:614:614) (649:649:649)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1176:1176:1176) (1199:1199:1199)) + (PORT datab (1612:1612:1612) (1652:1652:1652)) + (PORT datac (885:885:885) (930:930:930)) + (PORT datad (893:893:893) (940:940:940)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (256:256:256)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (178:178:178) (215:215:215)) + (PORT datad (211:211:211) (242:242:242)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) + (DELAY + (ABSOLUTE + (PORT datab (2102:2102:2102) (2242:2242:2242)) + (PORT datac (1464:1464:1464) (1539:1539:1539)) + (PORT datad (208:208:208) (246:246:246)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) + (DELAY + (ABSOLUTE + (PORT datab (1474:1474:1474) (1558:1558:1558)) + (PORT datac (2114:2114:2114) (2223:2223:2223)) + (PORT datad (1649:1649:1649) (1828:1828:1828)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) + (DELAY + (ABSOLUTE + (PORT dataa (955:955:955) (1004:1004:1004)) + (PORT datab (1085:1085:1085) (1111:1111:1111)) + (PORT datac (644:644:644) (684:684:684)) + (PORT datad (629:629:629) (644:644:644)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~7) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (629:629:629)) + (PORT datab (917:917:917) (949:949:949)) + (PORT datac (586:586:586) (598:598:598)) + (PORT datad (1627:1627:1627) (1648:1648:1648)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (2251:2251:2251) (2329:2329:2329)) + (PORT datab (1611:1611:1611) (1741:1741:1741)) + (PORT datac (847:847:847) (879:879:879)) + (PORT datad (871:871:871) (887:887:887)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (686:686:686)) + (PORT datab (874:874:874) (906:906:906)) + (PORT datac (1698:1698:1698) (1732:1732:1732)) + (PORT datad (1500:1500:1500) (1556:1556:1556)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1145:1145:1145) (1213:1213:1213)) + (PORT datab (624:624:624) (655:655:655)) + (PORT datac (657:657:657) (701:701:701)) + (PORT datad (1183:1183:1183) (1213:1213:1213)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1234:1234:1234) (1292:1292:1292)) + (PORT datab (986:986:986) (1027:1027:1027)) + (PORT datac (1677:1677:1677) (1709:1709:1709)) + (PORT datad (1375:1375:1375) (1426:1426:1426)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (255:255:255)) + (PORT datab (1011:1011:1011) (1072:1072:1072)) + (PORT datac (1770:1770:1770) (1905:1905:1905)) + (PORT datad (1375:1375:1375) (1425:1425:1425)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (1014:1014:1014)) + (PORT datab (946:946:946) (992:992:992)) + (PORT datad (890:890:890) (963:963:963)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (271:271:271)) + (PORT datab (989:989:989) (1051:1051:1051)) + (PORT datac (804:804:804) (824:824:824)) + (PORT datad (1395:1395:1395) (1406:1406:1406)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1775:1775:1775) (1871:1871:1871)) + (PORT datab (1638:1638:1638) (1787:1787:1787)) + (PORT datad (1885:1885:1885) (1952:1952:1952)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1063:1063:1063) (1146:1146:1146)) + (PORT datac (1745:1745:1745) (1882:1882:1882)) + (PORT datad (635:635:635) (694:694:694)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1074:1074:1074) (1159:1159:1159)) + (PORT datab (921:921:921) (984:984:984)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (566:566:566) (581:581:581)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1917:1917:1917) (2022:2022:2022)) + (PORT datab (1506:1506:1506) (1587:1587:1587)) + (PORT datac (1606:1606:1606) (1725:1725:1725)) + (PORT datad (857:857:857) (891:891:891)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1474:1474:1474) (1533:1533:1533)) + (PORT datab (1245:1245:1245) (1280:1280:1280)) + (PORT datac (931:931:931) (1004:1004:1004)) + (PORT datad (845:845:845) (854:854:854)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (296:296:296)) + (PORT datab (1965:1965:1965) (2057:2057:2057)) + (PORT datac (1434:1434:1434) (1491:1491:1491)) + (PORT datad (1510:1510:1510) (1653:1653:1653)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1364:1364:1364) (1466:1466:1466)) + (PORT datab (1561:1561:1561) (1650:1650:1650)) + (PORT datac (2446:2446:2446) (2642:2642:2642)) + (PORT datad (1222:1222:1222) (1355:1355:1355)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1651:1651:1651) (1723:1723:1723)) + (PORT datab (935:935:935) (964:964:964)) + (PORT datac (2570:2570:2570) (2619:2619:2619)) + (PORT datad (771:771:771) (818:818:818)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1479:1479:1479) (1540:1540:1540)) + (PORT datab (603:603:603) (620:620:620)) + (PORT datac (1131:1131:1131) (1166:1166:1166)) + (PORT datad (578:578:578) (596:596:596)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1475:1475:1475) (1536:1536:1536)) + (PORT datab (1418:1418:1418) (1464:1464:1464)) + (PORT datac (928:928:928) (1006:1006:1006)) + (PORT datad (1413:1413:1413) (1432:1432:1432)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1777:1777:1777) (1900:1900:1900)) + (PORT datab (217:217:217) (256:256:256)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (723:723:723) (797:797:797)) + (PORT datab (1182:1182:1182) (1233:1233:1233)) + (PORT datac (1221:1221:1221) (1278:1278:1278)) + (PORT datad (894:894:894) (946:946:946)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (896:896:896)) + (PORT datab (1880:1880:1880) (2010:2010:2010)) + (PORT datac (329:329:329) (351:351:351)) + (PORT datad (1691:1691:1691) (1766:1766:1766)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (2180:2180:2180) (2359:2359:2359)) + (PORT datab (1395:1395:1395) (1458:1458:1458)) + (PORT datac (1425:1425:1425) (1436:1436:1436)) + (PORT datad (2268:2268:2268) (2359:2359:2359)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1302:1302:1302) (1373:1373:1373)) + (PORT datab (1199:1199:1199) (1239:1239:1239)) + (PORT datac (650:650:650) (720:720:720)) + (PORT datad (1152:1152:1152) (1181:1181:1181)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1459:1459:1459) (1482:1482:1482)) + (PORT datab (1177:1177:1177) (1245:1245:1245)) + (PORT datac (653:653:653) (721:721:721)) + (PORT datad (187:187:187) (219:219:219)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~19) + (DELAY + (ABSOLUTE + (PORT dataa (2144:2144:2144) (2265:2265:2265)) + (PORT datab (1689:1689:1689) (1868:1868:1868)) + (PORT datac (1147:1147:1147) (1206:1206:1206)) + (PORT datad (1953:1953:1953) (2015:2015:2015)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (894:894:894)) + (PORT datab (919:919:919) (952:952:952)) + (PORT datac (564:564:564) (581:581:581)) + (PORT datad (1104:1104:1104) (1103:1103:1103)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (938:938:938)) + (PORT datab (1034:1034:1034) (1098:1098:1098)) + (PORT datac (1178:1178:1178) (1210:1210:1210)) + (PORT datad (634:634:634) (667:667:667)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (687:687:687)) + (PORT datab (662:662:662) (710:710:710)) + (PORT datac (629:629:629) (681:681:681)) + (PORT datad (1142:1142:1142) (1152:1152:1152)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (670:670:670)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1177:1177:1177) (1212:1212:1212)) + (PORT datad (560:560:560) (587:587:587)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1325:1325:1325) (1384:1384:1384)) + (PORT datab (1536:1536:1536) (1559:1559:1559)) + (PORT datac (1403:1403:1403) (1539:1539:1539)) + (PORT datad (2538:2538:2538) (2656:2656:2656)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1484:1484:1484) (1532:1532:1532)) + (PORT datab (1506:1506:1506) (1597:1597:1597)) + (PORT datac (1663:1663:1663) (1679:1679:1679)) + (PORT datad (1485:1485:1485) (1617:1617:1617)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1250:1250:1250) (1306:1306:1306)) + (PORT datab (672:672:672) (706:706:706)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (678:678:678) (701:701:701)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2311:2311:2311) (2479:2479:2479)) + (PORT datab (2245:2245:2245) (2328:2328:2328)) + (PORT datac (1401:1401:1401) (1542:1542:1542)) + (PORT datad (1158:1158:1158) (1220:1220:1220)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal68\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1759:1759:1759) (1850:1850:1850)) + (PORT datab (1660:1660:1660) (1809:1809:1809)) + (PORT datac (1036:1036:1036) (1100:1100:1100)) + (PORT datad (1815:1815:1815) (1892:1892:1892)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1443:1443:1443) (1550:1550:1550)) + (PORT datab (1149:1149:1149) (1188:1188:1188)) + (PORT datac (809:809:809) (820:820:820)) + (PORT datad (1490:1490:1490) (1622:1622:1622)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal63\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1059:1059:1059) (1127:1127:1127)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datac (1714:1714:1714) (1797:1797:1797)) + (PORT datad (1525:1525:1525) (1626:1626:1626)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal76\~2) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (691:691:691)) + (PORT datac (2229:2229:2229) (2297:2297:2297)) + (PORT datad (1684:1684:1684) (1744:1744:1744)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (670:670:670)) + (PORT datab (1492:1492:1492) (1549:1549:1549)) + (PORT datac (1215:1215:1215) (1263:1263:1263)) + (PORT datad (558:558:558) (582:582:582)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1853:1853:1853) (1956:1956:1956)) + (PORT datab (895:895:895) (912:912:912)) + (PORT datac (850:850:850) (899:899:899)) + (PORT datad (1512:1512:1512) (1544:1544:1544)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1106:1106:1106) (1144:1144:1144)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1215:1215:1215) (1263:1263:1263)) + (PORT datad (914:914:914) (954:954:954)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (705:705:705)) + (PORT datab (384:384:384) (412:412:412)) + (PORT datac (1156:1156:1156) (1181:1181:1181)) + (PORT datad (941:941:941) (985:985:985)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) + (DELAY + (ABSOLUTE + (PORT dataa (1248:1248:1248) (1328:1328:1328)) + (PORT datab (986:986:986) (1055:1055:1055)) + (PORT datac (840:840:840) (878:878:878)) + (PORT datad (1355:1355:1355) (1447:1447:1447)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (936:936:936)) + (PORT datab (1220:1220:1220) (1268:1268:1268)) + (PORT datac (1208:1208:1208) (1289:1289:1289)) + (PORT datad (683:683:683) (740:740:740)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (2075:2075:2075) (2210:2210:2210)) + (PORT datab (1511:1511:1511) (1577:1577:1577)) + (PORT datac (590:590:590) (639:639:639)) + (PORT datad (2101:2101:2101) (2201:2201:2201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~7) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (976:976:976)) + (PORT datab (251:251:251) (299:299:299)) + (PORT datac (1219:1219:1219) (1264:1264:1264)) + (PORT datad (1755:1755:1755) (1827:1827:1827)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (296:296:296)) + (PORT datab (645:645:645) (664:664:664)) + (PORT datac (180:180:180) (215:215:215)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~3) + (DELAY + (ABSOLUTE + (PORT dataa (997:997:997) (1069:1069:1069)) + (PORT datab (877:877:877) (902:902:902)) + (PORT datac (1046:1046:1046) (1134:1134:1134)) + (PORT datad (1269:1269:1269) (1355:1355:1355)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (913:913:913)) + (PORT datab (636:636:636) (660:660:660)) + (PORT datac (1654:1654:1654) (1746:1746:1746)) + (PORT datad (1116:1116:1116) (1186:1186:1186)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (724:724:724) (791:791:791)) + (PORT datab (1248:1248:1248) (1307:1307:1307)) + (PORT datac (1288:1288:1288) (1402:1402:1402)) + (PORT datad (896:896:896) (946:946:946)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (397:397:397) (427:427:427)) + (PORT datab (1208:1208:1208) (1268:1268:1268)) + (PORT datac (959:959:959) (1038:1038:1038)) + (PORT datad (1924:1924:1924) (2082:2082:2082)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) + (DELAY + (ABSOLUTE + (PORT dataa (1318:1318:1318) (1375:1375:1375)) + (PORT datab (1540:1540:1540) (1661:1661:1661)) + (PORT datac (2217:2217:2217) (2299:2299:2299)) + (PORT datad (919:919:919) (967:967:967)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (2563:2563:2563) (2766:2766:2766)) + (PORT datab (1244:1244:1244) (1298:1298:1298)) + (PORT datac (873:873:873) (937:937:937)) + (PORT datad (2161:2161:2161) (2331:2331:2331)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1265:1265:1265) (1296:1296:1296)) + (PORT datac (1421:1421:1421) (1419:1419:1419)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (671:671:671)) + (PORT datab (1250:1250:1250) (1279:1279:1279)) + (PORT datac (1879:1879:1879) (2050:2050:2050)) + (PORT datad (1649:1649:1649) (1832:1832:1832)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1274:1274:1274)) + (PORT datab (571:571:571) (582:582:582)) + (PORT datac (2046:2046:2046) (2173:2173:2173)) + (PORT datad (1308:1308:1308) (1448:1448:1448)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (278:278:278)) + (PORT datab (686:686:686) (703:703:703)) + (PORT datac (878:878:878) (936:936:936)) + (PORT datad (312:312:312) (329:329:329)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1624:1624:1624) (1672:1672:1672)) + (PORT datab (1493:1493:1493) (1610:1610:1610)) + (PORT datac (178:178:178) (216:216:216)) + (PORT datad (694:694:694) (748:748:748)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal10\~1) + (DELAY + (ABSOLUTE + (PORT datac (2148:2148:2148) (2195:2195:2195)) + (PORT datad (1421:1421:1421) (1470:1470:1470)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) + (DELAY + (ABSOLUTE + (PORT dataa (1212:1212:1212) (1275:1275:1275)) + (PORT datab (1443:1443:1443) (1483:1483:1483)) + (PORT datac (178:178:178) (216:216:216)) + (PORT datad (1433:1433:1433) (1518:1518:1518)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal69\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1981:1981:1981) (2045:2045:2045)) + (PORT datab (2097:2097:2097) (2238:2238:2238)) + (PORT datac (1468:1468:1468) (1539:1539:1539)) + (PORT datad (211:211:211) (249:249:249)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1873:1873:1873) (1941:1941:1941)) + (PORT datab (1345:1345:1345) (1486:1486:1486)) + (PORT datac (2046:2046:2046) (2172:2172:2172)) + (PORT datad (2102:2102:2102) (2203:2203:2203)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1755:1755:1755) (1823:1823:1823)) + (PORT datab (924:924:924) (949:949:949)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (621:621:621) (652:652:652)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (641:641:641) (662:662:662)) + (PORT datac (603:603:603) (623:623:623)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (995:995:995) (1066:1066:1066)) + (PORT datab (876:876:876) (900:900:900)) + (PORT datac (1640:1640:1640) (1827:1827:1827)) + (PORT datad (2138:2138:2138) (2305:2305:2305)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1112:1112:1112) (1152:1152:1152)) + (PORT datab (216:216:216) (259:259:259)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (863:863:863) (899:899:899)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (285:285:285) (352:352:352)) + (PORT datab (251:251:251) (304:304:304)) + (PORT datac (1170:1170:1170) (1219:1219:1219)) + (PORT datad (248:248:248) (302:302:302)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1554:1554:1554) (1689:1689:1689)) + (PORT datab (1993:1993:1993) (2047:2047:2047)) + (PORT datac (873:873:873) (939:939:939)) + (PORT datad (1697:1697:1697) (1792:1792:1792)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1238:1238:1238) (1290:1290:1290)) + (PORT datab (616:616:616) (641:641:641)) + (PORT datac (619:619:619) (670:670:670)) + (PORT datad (890:890:890) (915:915:915)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1847:1847:1847) (1963:1963:1963)) + (PORT datab (926:926:926) (986:986:986)) + (PORT datad (638:638:638) (671:671:671)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (1154:1154:1154) (1181:1181:1181)) + (PORT datac (320:320:320) (344:344:344)) + (PORT datad (663:663:663) (726:726:726)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (227:227:227) (267:267:267)) + (PORT datac (613:613:613) (637:637:637)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1847:1847:1847) (1960:1960:1960)) + (PORT datab (674:674:674) (708:708:708)) + (PORT datac (179:179:179) (213:213:213)) + (PORT datad (903:903:903) (947:947:947)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~20) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1091:1091:1091)) + (PORT datab (1843:1843:1843) (1936:1936:1936)) + (PORT datac (990:990:990) (1056:1056:1056)) + (PORT datad (1223:1223:1223) (1265:1265:1265)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (2284:2284:2284) (2463:2463:2463)) + (PORT datab (1844:1844:1844) (1935:1935:1935)) + (PORT datac (867:867:867) (913:913:913)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (852:852:852) (886:886:886)) + (PORT datab (1403:1403:1403) (1513:1513:1513)) + (PORT datac (650:650:650) (711:711:711)) + (PORT datad (671:671:671) (755:755:755)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (277:277:277) (348:348:348)) + (PORT datab (250:250:250) (300:300:300)) + (PORT datac (247:247:247) (306:306:306)) + (PORT datad (1203:1203:1203) (1275:1275:1275)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (793:793:793) (857:857:857)) + (PORT datab (630:630:630) (708:708:708)) + (PORT datac (832:832:832) (885:885:885)) + (PORT datad (661:661:661) (724:724:724)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (1562:1562:1562) (1606:1606:1606)) + (PORT datac (2770:2770:2770) (2816:2816:2816)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (703:703:703)) + (PORT datab (377:377:377) (403:403:403)) + (PORT datac (180:180:180) (218:218:218)) + (PORT datad (896:896:896) (921:921:921)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) + (DELAY + (ABSOLUTE + (PORT dataa (1286:1286:1286) (1375:1375:1375)) + (PORT datab (1004:1004:1004) (1054:1054:1054)) + (PORT datac (959:959:959) (1026:1026:1026)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1222:1222:1222) (1224:1224:1224)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) + (DELAY + (ABSOLUTE + (PORT dataa (1286:1286:1286) (1372:1372:1372)) + (PORT datab (1005:1005:1005) (1052:1052:1052)) + (PORT datac (959:959:959) (1023:1023:1023)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1461:1461:1461) (1557:1557:1557)) + (PORT datab (1071:1071:1071) (1131:1131:1131)) + (PORT datac (1183:1183:1183) (1237:1237:1237)) + (PORT datad (1422:1422:1422) (1471:1471:1471)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (656:656:656)) + (PORT datab (204:204:204) (244:244:244)) + (PORT datac (1380:1380:1380) (1388:1388:1388)) + (PORT datad (1256:1256:1256) (1311:1311:1311)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1542:1542:1542) (1647:1647:1647)) + (PORT datab (1761:1761:1761) (1804:1804:1804)) + (PORT datac (605:605:605) (628:628:628)) + (PORT datad (631:631:631) (654:654:654)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~47) + (DELAY + (ABSOLUTE + (PORT datab (688:688:688) (737:737:737)) + (PORT datac (381:381:381) (410:410:410)) + (PORT datad (853:853:853) (891:891:891)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (939:939:939)) + (PORT datab (1244:1244:1244) (1260:1260:1260)) + (PORT datac (187:187:187) (227:227:227)) + (PORT datad (1433:1433:1433) (1449:1449:1449)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (925:925:925)) + (PORT datab (684:684:684) (737:737:737)) + (PORT datac (875:875:875) (914:914:914)) + (PORT datad (1472:1472:1472) (1513:1513:1513)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (671:671:671)) + (PORT datab (684:684:684) (737:737:737)) + (PORT datac (1663:1663:1663) (1676:1676:1676)) + (PORT datad (367:367:367) (388:388:388)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (673:673:673)) + (PORT datab (1692:1692:1692) (1710:1710:1710)) + (PORT datac (836:836:836) (839:839:839)) + (PORT datad (827:827:827) (859:859:859)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (669:669:669)) + (PORT datab (901:901:901) (931:931:931)) + (PORT datac (1661:1661:1661) (1674:1674:1674)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) + (DELAY + (ABSOLUTE + (PORT datab (637:637:637) (657:657:657)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (1340:1340:1340) (1496:1496:1496)) + (PORT datac (1960:1960:1960) (2130:2130:2130)) + (PORT datad (1151:1151:1151) (1205:1205:1205)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1798:1798:1798) (1873:1873:1873)) + (PORT datab (247:247:247) (295:295:295)) + (PORT datac (880:880:880) (894:894:894)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~41) + (DELAY + (ABSOLUTE + (PORT datab (924:924:924) (979:979:979)) + (PORT datac (1035:1035:1035) (1109:1109:1109)) + (PORT datad (617:617:617) (626:626:626)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1681:1681:1681) (1791:1791:1791)) + (PORT datab (1812:1812:1812) (1917:1917:1917)) + (PORT datac (1337:1337:1337) (1365:1365:1365)) + (PORT datad (637:637:637) (687:687:687)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (974:974:974)) + (PORT datab (1062:1062:1062) (1114:1114:1114)) + (PORT datac (1488:1488:1488) (1575:1575:1575)) + (PORT datad (1194:1194:1194) (1262:1262:1262)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (250:250:250)) + (PORT datab (1520:1520:1520) (1602:1602:1602)) + (PORT datac (1087:1087:1087) (1105:1105:1105)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (960:960:960)) + (PORT datab (1658:1658:1658) (1699:1699:1699)) + (PORT datac (1280:1280:1280) (1331:1331:1331)) + (PORT datad (1594:1594:1594) (1614:1614:1614)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (668:668:668)) + (PORT datac (1213:1213:1213) (1256:1256:1256)) + (PORT datad (886:886:886) (936:936:936)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1441:1441:1441) (1479:1479:1479)) + (PORT datab (646:646:646) (667:667:667)) + (PORT datac (177:177:177) (213:213:213)) + (PORT datad (939:939:939) (976:976:976)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) + (DELAY + (ABSOLUTE + (PORT datac (588:588:588) (596:596:596)) + (PORT datad (863:863:863) (883:883:883)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (830:830:830) (842:842:842)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) + (DELAY + (ABSOLUTE + (PORT datab (366:366:366) (387:387:387)) + (PORT datac (593:593:593) (608:608:608)) + (PORT datad (614:614:614) (631:631:631)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1311:1311:1311) (1357:1357:1357)) + (PORT datab (1610:1610:1610) (1651:1651:1651)) + (PORT datac (968:968:968) (1039:1039:1039)) + (PORT datad (2195:2195:2195) (2176:2176:2176)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (859:859:859)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (965:965:965) (1009:1009:1009)) + (PORT datad (1114:1114:1114) (1140:1140:1140)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1155:1155:1155) (1199:1199:1199)) + (PORT datab (902:902:902) (932:932:932)) + (PORT datac (956:956:956) (1022:1022:1022)) + (PORT datad (196:196:196) (233:233:233)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1279:1279:1279) (1383:1383:1383)) + (PORT datab (637:637:637) (659:659:659)) + (PORT datac (187:187:187) (227:227:227)) + (PORT datad (955:955:955) (1046:1046:1046)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) + (DELAY + (ABSOLUTE + (PORT datab (1245:1245:1245) (1295:1295:1295)) + (PORT datac (935:935:935) (984:984:984)) + (PORT datad (898:898:898) (966:966:966)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1175:1175:1175) (1219:1219:1219)) + (PORT datab (911:911:911) (944:944:944)) + (PORT datac (1136:1136:1136) (1156:1156:1156)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) + (DELAY + (ABSOLUTE + (PORT datab (1342:1342:1342) (1372:1372:1372)) + (PORT datad (1144:1144:1144) (1175:1175:1175)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (670:670:670)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (817:817:817) (835:835:835)) + (PORT datad (822:822:822) (842:842:842)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (675:675:675)) + (PORT datab (983:983:983) (1074:1074:1074)) + (PORT datac (1087:1087:1087) (1097:1097:1097)) + (PORT datad (1806:1806:1806) (1916:1916:1916)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (674:674:674)) + (PORT datab (947:947:947) (979:979:979)) + (PORT datac (371:371:371) (399:399:399)) + (PORT datad (179:179:179) (206:206:206)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (618:618:618) (631:631:631)) + (PORT datac (871:871:871) (877:877:877)) + (PORT datad (577:577:577) (595:595:595)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) + (DELAY + (ABSOLUTE + (PORT dataa (1287:1287:1287) (1376:1376:1376)) + (PORT datab (978:978:978) (1026:1026:1026)) + (PORT datac (966:966:966) (1015:1015:1015)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) + (DELAY + (ABSOLUTE + (PORT dataa (1276:1276:1276) (1362:1362:1362)) + (PORT datab (973:973:973) (1025:1025:1025)) + (PORT datac (974:974:974) (1023:1023:1023)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (536:536:536) (565:565:565)) + (PORT ena (1237:1237:1237) (1220:1220:1220)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (969:969:969)) + (PORT datab (2629:2629:2629) (2685:2685:2685)) + (PORT datac (187:187:187) (228:228:228)) + (PORT datad (1382:1382:1382) (1417:1417:1417)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_exx\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1904:1904:1904) (2087:2087:2087)) + (PORT datab (1498:1498:1498) (1565:1565:1565)) + (PORT datad (1153:1153:1153) (1185:1185:1185)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_exx) + (DELAY + (ABSOLUTE + (PORT clk (1533:1533:1533) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1931:1931:1931) (1907:1907:1907)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1652:1652:1652) (1684:1684:1684)) + (PORT datab (1728:1728:1728) (1737:1737:1737)) + (PORT datac (1191:1191:1191) (1239:1239:1239)) + (PORT datad (1223:1223:1223) (1265:1265:1265)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1220:1220:1220) (1242:1242:1242)) + (PORT datab (1206:1206:1206) (1263:1263:1263)) + (PORT datac (1663:1663:1663) (1680:1680:1680)) + (PORT datad (577:577:577) (596:596:596)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1493:1493:1493) (1541:1541:1541)) + (PORT datab (957:957:957) (1012:1012:1012)) + (PORT datac (1200:1200:1200) (1254:1254:1254)) + (PORT datad (1188:1188:1188) (1238:1238:1238)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (653:653:653)) + (PORT datab (1866:1866:1866) (1943:1943:1943)) + (PORT datac (1028:1028:1028) (1092:1092:1092)) + (PORT datad (2619:2619:2619) (2697:2697:2697)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~56) + (DELAY + (ABSOLUTE + (PORT dataa (1223:1223:1223) (1275:1275:1275)) + (PORT datab (1259:1259:1259) (1303:1303:1303)) + (PORT datac (863:863:863) (935:935:935)) + (PORT datad (890:890:890) (967:967:967)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) + (DELAY + (ABSOLUTE + (PORT datab (908:908:908) (944:944:944)) + (PORT datac (636:636:636) (655:655:655)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (232:232:232) (283:283:283)) + (PORT datac (2706:2706:2706) (2903:2903:2903)) + (PORT datad (218:218:218) (253:253:253)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1596:1596:1596) (1646:1646:1646)) + (PORT datab (1499:1499:1499) (1573:1573:1573)) + (PORT datac (1471:1471:1471) (1570:1570:1570)) + (PORT datad (1124:1124:1124) (1141:1141:1141)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1244:1244:1244) (1329:1329:1329)) + (PORT datab (984:984:984) (1057:1057:1057)) + (PORT datac (1948:1948:1948) (2028:2028:2028)) + (PORT datad (1356:1356:1356) (1450:1450:1450)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1478:1478:1478) (1539:1539:1539)) + (PORT datab (1303:1303:1303) (1403:1403:1403)) + (PORT datac (929:929:929) (1005:1005:1005)) + (PORT datad (1508:1508:1508) (1652:1652:1652)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (1003:1003:1003)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (592:592:592) (642:642:642)) + (PORT datad (1235:1235:1235) (1275:1275:1275)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1525:1525:1525) (1588:1588:1588)) + (PORT datab (901:901:901) (934:934:934)) + (PORT datac (1455:1455:1455) (1495:1495:1495)) + (PORT datad (682:682:682) (736:736:736)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (956:956:956) (974:974:974)) + (PORT datac (625:625:625) (647:647:647)) + (PORT datad (575:575:575) (606:606:606)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) + (DELAY + (ABSOLUTE + (PORT dataa (679:679:679) (725:725:725)) + (PORT datab (1120:1120:1120) (1176:1176:1176)) + (PORT datac (1928:1928:1928) (1998:1998:1998)) + (PORT datad (809:809:809) (845:845:845)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (989:989:989)) + (PORT datab (556:556:556) (587:587:587)) + (PORT datac (963:963:963) (1008:1008:1008)) + (PORT datad (929:929:929) (951:951:951)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (376:376:376)) + (PORT datab (249:249:249) (290:290:290)) + (PORT datac (963:963:963) (1005:1005:1005)) + (PORT datad (929:929:929) (948:948:948)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~52) + (DELAY + (ABSOLUTE + (PORT dataa (983:983:983) (1101:1101:1101)) + (PORT datab (783:783:783) (890:890:890)) + (PORT datac (726:726:726) (838:838:838)) + (PORT datad (626:626:626) (675:675:675)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1200:1200:1200) (1286:1286:1286)) + (PORT datab (342:342:342) (372:372:372)) + (PORT datac (1901:1901:1901) (2064:2064:2064)) + (PORT datad (617:617:617) (629:629:629)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (278:278:278)) + (PORT datab (397:397:397) (437:437:437)) + (PORT datac (975:975:975) (1014:1014:1014)) + (PORT datad (812:812:812) (837:837:837)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (1213:1213:1213) (1257:1257:1257)) + (PORT datad (323:323:323) (347:347:347)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1627:1627:1627) (1675:1675:1675)) + (PORT datab (1195:1195:1195) (1246:1246:1246)) + (PORT datac (1289:1289:1289) (1403:1403:1403)) + (PORT datad (691:691:691) (746:746:746)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (274:274:274)) + (PORT datab (614:614:614) (638:638:638)) + (PORT datac (1132:1132:1132) (1151:1151:1151)) + (PORT datad (696:696:696) (744:744:744)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (726:726:726) (791:791:791)) + (PORT datab (668:668:668) (719:719:719)) + (PORT datac (639:639:639) (684:684:684)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (220:220:220) (258:258:258)) + (PORT datac (1154:1154:1154) (1175:1175:1175)) + (PORT datad (179:179:179) (207:207:207)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (639:639:639)) + (PORT datab (1176:1176:1176) (1220:1220:1220)) + (PORT datac (1428:1428:1428) (1462:1462:1462)) + (PORT datad (862:862:862) (888:888:888)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (239:239:239) (291:291:291)) + (PORT datab (986:986:986) (1028:1028:1028)) + (PORT datac (645:645:645) (702:702:702)) + (PORT datad (319:319:319) (331:331:331)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) + (DELAY + (ABSOLUTE + (PORT datab (3601:3601:3601) (3704:3704:3704)) + (PORT datad (1514:1514:1514) (1586:1586:1586)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~8) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (641:641:641)) + (PORT datab (1172:1172:1172) (1203:1203:1203)) + (PORT datac (626:626:626) (659:659:659)) + (PORT datad (828:828:828) (846:846:846)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~48) + (DELAY + (ABSOLUTE + (PORT dataa (1853:1853:1853) (1955:1955:1955)) + (PORT datab (899:899:899) (946:946:946)) + (PORT datac (894:894:894) (920:920:920)) + (PORT datad (854:854:854) (879:879:879)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) + (DELAY + (ABSOLUTE + (PORT datab (672:672:672) (700:700:700)) + (PORT datad (1120:1120:1120) (1145:1145:1145)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~2) + (DELAY + (ABSOLUTE + (PORT datab (885:885:885) (918:918:918)) + (PORT datac (1069:1069:1069) (1130:1130:1130)) + (PORT datad (1496:1496:1496) (1538:1538:1538)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~49) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (390:390:390)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (552:552:552) (564:564:564)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1647:1647:1647) (1826:1826:1826)) + (PORT datab (1263:1263:1263) (1332:1332:1332)) + (PORT datac (1375:1375:1375) (1403:1403:1403)) + (PORT datad (588:588:588) (608:608:608)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2251:2251:2251) (2328:2328:2328)) + (PORT datab (879:879:879) (911:911:911)) + (PORT datac (1575:1575:1575) (1707:1707:1707)) + (PORT datad (1688:1688:1688) (1747:1747:1747)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (972:972:972)) + (PORT datab (1342:1342:1342) (1395:1395:1395)) + (PORT datac (866:866:866) (929:929:929)) + (PORT datad (1427:1427:1427) (1449:1449:1449)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (725:725:725)) + (PORT datab (1471:1471:1471) (1517:1517:1517)) + (PORT datac (849:849:849) (874:874:874)) + (PORT datad (669:669:669) (723:723:723)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1233:1233:1233) (1315:1315:1315)) + (PORT datab (936:936:936) (978:978:978)) + (PORT datac (1411:1411:1411) (1475:1475:1475)) + (PORT datad (1767:1767:1767) (1823:1823:1823)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT datac (859:859:859) (876:876:876)) + (PORT datad (327:327:327) (351:351:351)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (655:655:655) (688:688:688)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (975:975:975)) + (PORT datab (986:986:986) (1041:1041:1041)) + (PORT datac (871:871:871) (933:933:933)) + (PORT datad (885:885:885) (915:915:915)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1793:1793:1793) (1875:1875:1875)) + (PORT datab (1527:1527:1527) (1572:1572:1572)) + (PORT datac (1068:1068:1068) (1127:1127:1127)) + (PORT datad (856:856:856) (879:879:879)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1174:1174:1174) (1222:1222:1222)) + (PORT datab (882:882:882) (915:915:915)) + (PORT datac (1069:1069:1069) (1128:1128:1128)) + (PORT datad (1492:1492:1492) (1533:1533:1533)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1761:1761:1761) (1832:1832:1832)) + (PORT datab (1926:1926:1926) (1967:1967:1967)) + (PORT datac (1557:1557:1557) (1584:1584:1584)) + (PORT datad (1049:1049:1049) (1102:1102:1102)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) + (DELAY + (ABSOLUTE + (PORT dataa (239:239:239) (287:287:287)) + (PORT datab (237:237:237) (282:282:282)) + (PORT datac (1015:1015:1015) (1061:1061:1061)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1650:1650:1650) (1827:1827:1827)) + (PORT datac (1232:1232:1232) (1346:1346:1346)) + (PORT datad (1116:1116:1116) (1144:1144:1144)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1406:1406:1406) (1446:1446:1446)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (825:825:825) (841:841:841)) + (PORT datad (838:838:838) (886:886:886)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1230:1230:1230)) + (PORT datac (917:917:917) (956:956:956)) + (PORT datad (859:859:859) (899:899:899)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1321:1321:1321) (1383:1383:1383)) + (PORT datab (933:933:933) (971:971:971)) + (PORT datac (1396:1396:1396) (1536:1536:1536)) + (PORT datad (1181:1181:1181) (1244:1244:1244)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (978:978:978)) + (PORT datab (1540:1540:1540) (1664:1664:1664)) + (PORT datac (2216:2216:2216) (2296:2296:2296)) + (PORT datad (1530:1530:1530) (1622:1622:1622)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (276:276:276)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (1184:1184:1184) (1245:1245:1245)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1647:1647:1647) (1822:1822:1822)) + (PORT datab (355:355:355) (385:385:385)) + (PORT datac (1228:1228:1228) (1341:1341:1341)) + (PORT datad (604:604:604) (639:639:639)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~30) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (641:641:641)) + (PORT datab (966:966:966) (999:999:999)) + (PORT datac (663:663:663) (694:694:694)) + (PORT datad (594:594:594) (614:614:614)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (901:901:901)) + (PORT datab (211:211:211) (255:255:255)) + (PORT datac (192:192:192) (223:223:223)) + (PORT datad (1560:1560:1560) (1654:1654:1654)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (631:631:631)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (628:628:628) (658:658:658)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (643:643:643) (669:669:669)) + (PORT datac (823:823:823) (829:829:829)) + (PORT datad (1688:1688:1688) (1742:1742:1742)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (393:393:393)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (1204:1204:1204) (1257:1257:1257)) + (PORT datad (1048:1048:1048) (1082:1082:1082)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) + (DELAY + (ABSOLUTE + (PORT dataa (1360:1360:1360) (1460:1460:1460)) + (PORT datab (1167:1167:1167) (1197:1197:1197)) + (PORT datad (1607:1607:1607) (1719:1719:1719)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1598:1598:1598) (1645:1645:1645)) + (PORT datab (1618:1618:1618) (1773:1773:1773)) + (PORT datac (872:872:872) (933:933:933)) + (PORT datad (1311:1311:1311) (1374:1374:1374)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (440:440:440)) + (PORT datab (246:246:246) (294:294:294)) + (PORT datac (1467:1467:1467) (1528:1528:1528)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1424:1424:1424) (1502:1502:1502)) + (PORT datab (1104:1104:1104) (1116:1116:1116)) + (PORT datac (1503:1503:1503) (1564:1564:1564)) + (PORT datad (635:635:635) (657:657:657)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (647:647:647)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (617:617:617) (656:656:656)) + (PORT datad (631:631:631) (650:650:650)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1232:1232:1232) (1293:1293:1293)) + (PORT datab (2419:2419:2419) (2477:2477:2477)) + (PORT datac (1675:1675:1675) (1710:1710:1710)) + (PORT datad (985:985:985) (1038:1038:1038)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (982:982:982) (1100:1100:1100)) + (PORT datab (759:759:759) (866:866:866)) + (PORT datac (608:608:608) (629:629:629)) + (PORT datad (884:884:884) (917:917:917)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1159:1159:1159) (1204:1204:1204)) + (PORT datab (372:372:372) (397:397:397)) + (PORT datac (920:920:920) (973:973:973)) + (PORT datad (818:818:818) (865:865:865)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (242:242:242) (289:289:289)) + (PORT datac (202:202:202) (247:247:247)) + (PORT datad (868:868:868) (925:925:925)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1541:1541:1541) (1598:1598:1598)) + (PORT datab (1027:1027:1027) (1116:1116:1116)) + (PORT datac (337:337:337) (366:366:366)) + (PORT datad (196:196:196) (232:232:232)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1398:1398:1398) (1425:1425:1425)) + (PORT datab (1123:1123:1123) (1145:1145:1145)) + (PORT datac (1387:1387:1387) (1417:1417:1417)) + (PORT datad (337:337:337) (362:362:362)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (955:955:955)) + (PORT datab (705:705:705) (772:772:772)) + (PORT datac (665:665:665) (748:748:748)) + (PORT datad (575:575:575) (591:591:591)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (500:500:500)) + (PORT datab (269:269:269) (353:353:353)) + (PORT datac (1395:1395:1395) (1507:1507:1507)) + (PORT datad (1175:1175:1175) (1258:1258:1258)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1596:1596:1596) (1729:1729:1729)) + (PORT datab (1938:1938:1938) (2043:2043:2043)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (2588:2588:2588) (2666:2666:2666)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2229:2229:2229) (2274:2274:2274)) + (PORT datab (2486:2486:2486) (2693:2693:2693)) + (PORT datac (2230:2230:2230) (2299:2299:2299)) + (PORT datad (1642:1642:1642) (1694:1694:1694)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1211:1211:1211) (1286:1286:1286)) + (PORT datab (879:879:879) (905:905:905)) + (PORT datac (2230:2230:2230) (2302:2302:2302)) + (PORT datad (2452:2452:2452) (2652:2652:2652)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (2068:2068:2068) (2112:2112:2112)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (865:865:865)) + (PORT datab (828:828:828) (846:846:846)) + (PORT datac (1565:1565:1565) (1694:1694:1694)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (400:400:400)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (1200:1200:1200) (1252:1252:1252)) + (PORT datad (861:861:861) (911:911:911)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~2) + (DELAY + (ABSOLUTE + (PORT datac (858:858:858) (869:869:869)) + (PORT datad (1351:1351:1351) (1366:1366:1366)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1499:1499:1499) (1515:1515:1515)) + (PORT datab (1191:1191:1191) (1239:1239:1239)) + (PORT datac (1752:1752:1752) (1874:1874:1874)) + (PORT datad (1446:1446:1446) (1521:1521:1521)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (947:947:947)) + (PORT datab (683:683:683) (705:705:705)) + (PORT datac (2071:2071:2071) (2251:2251:2251)) + (PORT datad (1432:1432:1432) (1451:1451:1451)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (752:752:752) (844:844:844)) + (PORT datab (887:887:887) (909:909:909)) + (PORT datad (1197:1197:1197) (1224:1224:1224)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (306:306:306) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de1) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1591:1591:1591) (1568:1568:1568)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (751:751:751) (842:842:842)) + (PORT datab (225:225:225) (273:273:273)) + (PORT datac (788:788:788) (792:792:792)) + (PORT datad (224:224:224) (296:296:296)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) + (DELAY + (ABSOLUTE + (PORT dataa (1063:1063:1063) (1149:1149:1149)) + (PORT datab (922:922:922) (983:983:983)) + (PORT datac (1898:1898:1898) (2064:2064:2064)) + (PORT datad (1207:1207:1207) (1289:1289:1289)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~50) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (939:939:939)) + (PORT datab (457:457:457) (532:532:532)) + (PORT datac (420:420:420) (489:489:489)) + (PORT datad (984:984:984) (1034:1034:1034)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1830:1830:1830) (1974:1974:1974)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (678:678:678) (727:727:727)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1113:1113:1113) (1151:1151:1151)) + (PORT datab (1237:1237:1237) (1272:1272:1272)) + (PORT datac (1201:1201:1201) (1255:1255:1255)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (700:700:700) (759:759:759)) + (PORT datab (1508:1508:1508) (1551:1551:1551)) + (PORT datac (1985:1985:1985) (2041:2041:2041)) + (PORT datad (1440:1440:1440) (1501:1501:1501)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (933:933:933)) + (PORT datab (219:219:219) (256:256:256)) + (PORT datac (316:316:316) (335:335:335)) + (PORT datad (590:590:590) (623:623:623)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (2828:2828:2828) (3036:3036:3036)) + (PORT datab (1101:1101:1101) (1114:1114:1114)) + (PORT datac (1504:1504:1504) (1566:1566:1566)) + (PORT datad (1269:1269:1269) (1342:1342:1342)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (900:900:900)) + (PORT datab (215:215:215) (260:260:260)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1558:1558:1558) (1654:1654:1654)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1205:1205:1205) (1284:1284:1284)) + (PORT datab (1396:1396:1396) (1445:1445:1445)) + (PORT datac (1194:1194:1194) (1232:1232:1232)) + (PORT datad (1411:1411:1411) (1507:1507:1507)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1245:1245:1245) (1304:1304:1304)) + (PORT datab (865:865:865) (920:920:920)) + (PORT datac (1734:1734:1734) (1769:1769:1769)) + (PORT datad (823:823:823) (888:888:888)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (723:723:723) (790:790:790)) + (PORT datac (1371:1371:1371) (1479:1479:1479)) + (PORT datad (672:672:672) (752:752:752)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1087:1087:1087) (1120:1120:1120)) + (PORT datab (228:228:228) (269:269:269)) + (PORT datac (1374:1374:1374) (1452:1452:1452)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (773:773:773)) + (PORT datab (666:666:666) (735:735:735)) + (PORT datac (1203:1203:1203) (1259:1259:1259)) + (PORT datad (1108:1108:1108) (1151:1151:1151)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1122:1122:1122) (1172:1172:1172)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel3) + (DELAY + (ABSOLUTE + (PORT dataa (2260:2260:2260) (2337:2337:2337)) + (PORT datac (1572:1572:1572) (1704:1704:1704)) + (PORT datad (1683:1683:1683) (1743:1743:1743)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1463:1463:1463) (1491:1491:1491)) + (PORT datab (1113:1113:1113) (1143:1143:1143)) + (PORT datac (321:321:321) (347:347:347)) + (PORT datad (606:606:606) (641:641:641)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (1280:1280:1280) (1380:1380:1380)) + (PORT datab (980:980:980) (1076:1076:1076)) + (PORT datac (892:892:892) (917:917:917)) + (PORT datad (615:615:615) (665:665:665)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (661:661:661)) + (PORT datab (1481:1481:1481) (1539:1539:1539)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (1257:1257:1257) (1315:1315:1315)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1002:1002:1002) (1063:1063:1063)) + (PORT datab (906:906:906) (923:923:923)) + (PORT datac (174:174:174) (207:207:207)) + (PORT datad (890:890:890) (926:926:926)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (233:233:233) (284:284:284)) + (PORT datac (865:865:865) (890:890:890)) + (PORT datad (217:217:217) (249:249:249)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel0) + (DELAY + (ABSOLUTE + (PORT dataa (2362:2362:2362) (2435:2435:2435)) + (PORT datab (2736:2736:2736) (2936:2936:2936)) + (PORT datad (869:869:869) (926:926:926)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (668:668:668)) + (PORT datab (632:632:632) (661:661:661)) + (PORT datac (624:624:624) (652:652:652)) + (PORT datad (1153:1153:1153) (1193:1193:1193)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (664:664:664)) + (PORT datab (641:641:641) (658:658:658)) + (PORT datac (649:649:649) (669:669:669)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) + (DELAY + (ABSOLUTE + (PORT dataa (1429:1429:1429) (1578:1578:1578)) + (PORT datab (948:948:948) (1000:1000:1000)) + (PORT datac (1287:1287:1287) (1342:1342:1342)) + (PORT datad (1181:1181:1181) (1244:1244:1244)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (920:920:920) (973:973:973)) + (PORT datab (1342:1342:1342) (1392:1392:1392)) + (PORT datac (326:326:326) (353:353:353)) + (PORT datad (1427:1427:1427) (1449:1449:1449)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (656:656:656) (678:678:678)) + (PORT datac (928:928:928) (941:941:941)) + (PORT datad (180:180:180) (211:211:211)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (914:914:914)) + (PORT datab (1416:1416:1416) (1546:1546:1546)) + (PORT datac (565:565:565) (575:575:575)) + (PORT datad (936:936:936) (1040:1040:1040)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) + (DELAY + (ABSOLUTE + (PORT dataa (1341:1341:1341) (1375:1375:1375)) + (PORT datab (1855:1855:1855) (2010:2010:2010)) + (PORT datac (1899:1899:1899) (2062:2062:2062)) + (PORT datad (1056:1056:1056) (1088:1088:1088)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (294:294:294)) + (PORT datab (908:908:908) (935:935:935)) + (PORT datac (1721:1721:1721) (1807:1807:1807)) + (PORT datad (644:644:644) (655:655:655)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1030:1030:1030) (1022:1022:1022)) + (PORT datab (1458:1458:1458) (1479:1479:1479)) + (PORT datac (1863:1863:1863) (1883:1883:1883)) + (PORT datad (891:891:891) (942:942:942)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) + (DELAY + (ABSOLUTE + (PORT datab (899:899:899) (963:963:963)) + (PORT datac (1275:1275:1275) (1353:1353:1353)) + (PORT datad (819:819:819) (820:820:820)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (961:961:961) (1011:1011:1011)) + (PORT datab (1539:1539:1539) (1661:1661:1661)) + (PORT datac (2217:2217:2217) (2294:2294:2294)) + (PORT datad (1527:1527:1527) (1620:1620:1620)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (950:950:950) (1002:1002:1002)) + (PORT datab (1222:1222:1222) (1268:1268:1268)) + (PORT datac (825:825:825) (834:834:834)) + (PORT datad (586:586:586) (604:604:604)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (1191:1191:1191) (1202:1202:1202)) + (PORT datac (550:550:550) (570:570:570)) + (PORT datad (623:623:623) (657:657:657)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1148:1148:1148) (1198:1198:1198)) + (PORT datab (1473:1473:1473) (1535:1535:1535)) + (PORT datac (1063:1063:1063) (1084:1084:1084)) + (PORT datad (1433:1433:1433) (1485:1485:1485)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) + (DELAY + (ABSOLUTE + (PORT datab (349:349:349) (382:382:382)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (842:842:842) (885:885:885)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (404:404:404) (433:433:433)) + (PORT datab (229:229:229) (278:278:278)) + (PORT datac (1189:1189:1189) (1253:1253:1253)) + (PORT datad (646:646:646) (683:683:683)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (875:875:875)) + (PORT datab (1717:1717:1717) (1789:1789:1789)) + (PORT datad (1811:1811:1811) (1901:1901:1901)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (753:753:753) (846:846:846)) + (PORT datab (887:887:887) (908:908:908)) + (PORT datad (1196:1196:1196) (1223:1223:1223)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de2) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1591:1591:1591) (1568:1568:1568)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (750:750:750) (841:841:841)) + (PORT datab (248:248:248) (331:331:331)) + (PORT datac (787:787:787) (792:792:792)) + (PORT datad (197:197:197) (232:232:232)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (288:288:288)) + (PORT datac (1412:1412:1412) (1417:1417:1417)) + (PORT datad (1852:1852:1852) (1892:1892:1892)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) + (DELAY + (ABSOLUTE + (PORT dataa (236:236:236) (287:287:287)) + (PORT datac (1407:1407:1407) (1415:1415:1415)) + (PORT datad (1854:1854:1854) (1894:1894:1894)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (991:991:991) (1026:1026:1026)) + (PORT ena (1426:1426:1426) (1409:1409:1409)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) + (DELAY + (ABSOLUTE + (PORT datab (1717:1717:1717) (1793:1793:1793)) + (PORT datac (821:821:821) (841:841:841)) + (PORT datad (1809:1809:1809) (1899:1899:1899)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (994:994:994) (1029:1029:1029)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (319:319:319)) + (PORT datab (1080:1080:1080) (1115:1115:1115)) + (PORT datad (360:360:360) (421:421:421)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1479:1479:1479) (1540:1540:1540)) + (PORT datab (1114:1114:1114) (1149:1149:1149)) + (PORT datac (926:926:926) (1002:1002:1002)) + (PORT datad (579:579:579) (597:597:597)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (404:404:404) (437:437:437)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (204:204:204) (249:249:249)) + (PORT datad (1311:1311:1311) (1345:1345:1345)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37npla28M3T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (2034:2034:2034) (2206:2206:2206)) + (PORT datab (1368:1368:1368) (1522:1522:1522)) + (PORT datac (1094:1094:1094) (1159:1159:1159)) + (PORT datad (902:902:902) (911:911:911)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) + (DELAY + (ABSOLUTE + (PORT dataa (959:959:959) (1003:1003:1003)) + (PORT datab (1101:1101:1101) (1135:1135:1135)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (876:876:876) (901:901:901)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1199:1199:1199)) + (PORT datab (961:961:961) (1031:1031:1031)) + (PORT datac (1199:1199:1199) (1282:1282:1282)) + (PORT datad (2867:2867:2867) (2961:2961:2961)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (1363:1363:1363) (1378:1378:1378)) + (PORT datad (644:644:644) (658:658:658)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (2294:2294:2294) (2473:2473:2473)) + (PORT datab (1742:1742:1742) (1828:1828:1828)) + (PORT datac (1441:1441:1441) (1490:1490:1490)) + (PORT datad (1101:1101:1101) (1143:1143:1143)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1106:1106:1106) (1146:1146:1146)) + (PORT datab (1219:1219:1219) (1250:1250:1250)) + (PORT datac (1199:1199:1199) (1241:1241:1241)) + (PORT datad (2219:2219:2219) (2243:2243:2243)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1166:1166:1166) (1207:1207:1207)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (838:838:838) (886:886:886)) + (PORT datad (2017:2017:2017) (2045:2045:2045)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1213:1213:1213) (1272:1272:1272)) + (PORT datab (1362:1362:1362) (1402:1402:1402)) + (PORT datac (892:892:892) (931:931:931)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1263:1263:1263) (1355:1355:1355)) + (PORT datad (870:870:870) (922:922:922)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (986:986:986)) + (PORT datab (653:653:653) (692:692:692)) + (PORT datac (1951:1951:1951) (2031:2031:2031)) + (PORT datad (1598:1598:1598) (1743:1743:1743)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (975:975:975)) + (PORT datab (978:978:978) (1029:1029:1029)) + (PORT datac (1362:1362:1362) (1399:1399:1399)) + (PORT datad (597:597:597) (611:611:611)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1152:1152:1152) (1210:1210:1210)) + (PORT datab (654:654:654) (692:692:692)) + (PORT datac (923:923:923) (937:937:937)) + (PORT datad (855:855:855) (865:865:865)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (246:246:246) (301:301:301)) + (PORT datab (928:928:928) (974:974:974)) + (PORT datac (1453:1453:1453) (1529:1529:1529)) + (PORT datad (845:845:845) (857:857:857)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (574:574:574) (585:585:585)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (672:672:672) (720:720:720)) + (PORT datab (1610:1610:1610) (1651:1651:1651)) + (PORT datac (1280:1280:1280) (1319:1319:1319)) + (PORT datad (891:891:891) (939:939:939)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (634:634:634)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (614:614:614) (636:636:636)) + (PORT datad (913:913:913) (950:950:950)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (386:386:386)) + (PORT datab (1199:1199:1199) (1267:1267:1267)) + (PORT datac (1595:1595:1595) (1618:1618:1618)) + (PORT datad (972:972:972) (1026:1026:1026)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (622:622:622) (668:668:668)) + (PORT datad (869:869:869) (889:889:889)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1237:1237:1237) (1286:1286:1286)) + (PORT datab (1475:1475:1475) (1512:1512:1512)) + (PORT datac (1132:1132:1132) (1166:1166:1166)) + (PORT datad (1185:1185:1185) (1228:1228:1228)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (381:381:381)) + (PORT datab (1367:1367:1367) (1378:1378:1378)) + (PORT datac (1077:1077:1077) (1101:1101:1101)) + (PORT datad (1342:1342:1342) (1364:1364:1364)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (680:680:680) (741:741:741)) + (PORT datab (919:919:919) (951:951:951)) + (PORT datad (1175:1175:1175) (1224:1224:1224)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~41) + (DELAY + (ABSOLUTE + (PORT dataa (2212:2212:2212) (2402:2402:2402)) + (PORT datab (1581:1581:1581) (1722:1722:1722)) + (PORT datac (1487:1487:1487) (1611:1611:1611)) + (PORT datad (861:861:861) (890:890:890)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1794:1794:1794) (1871:1871:1871)) + (PORT datab (1184:1184:1184) (1250:1250:1250)) + (PORT datac (1904:1904:1904) (1967:1967:1967)) + (PORT datad (1103:1103:1103) (1118:1118:1118)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (401:401:401)) + (PORT datab (641:641:641) (670:670:670)) + (PORT datac (635:635:635) (656:656:656)) + (PORT datad (592:592:592) (611:611:611)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1106:1106:1106) (1171:1171:1171)) + (PORT datab (882:882:882) (919:919:919)) + (PORT datac (1764:1764:1764) (1841:1841:1841)) + (PORT datad (1133:1133:1133) (1176:1176:1176)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (957:957:957) (1028:1028:1028)) + (PORT datab (890:890:890) (914:914:914)) + (PORT datac (933:933:933) (977:977:977)) + (PORT datad (1405:1405:1405) (1453:1453:1453)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (269:269:269)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1187:1187:1187) (1232:1232:1232)) + (PORT datad (616:616:616) (660:660:660)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) + (DELAY + (ABSOLUTE + (PORT dataa (1180:1180:1180) (1278:1278:1278)) + (PORT datab (971:971:971) (1028:1028:1028)) + (PORT datac (871:871:871) (935:935:935)) + (PORT datad (1211:1211:1211) (1261:1261:1261)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) + (DELAY + (ABSOLUTE + (PORT datab (229:229:229) (271:271:271)) + (PORT datac (605:605:605) (631:631:631)) + (PORT datad (216:216:216) (242:242:242)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) + (DELAY + (ABSOLUTE + (PORT dataa (1244:1244:1244) (1332:1332:1332)) + (PORT datab (983:983:983) (1057:1057:1057)) + (PORT datac (644:644:644) (684:684:684)) + (PORT datad (1355:1355:1355) (1453:1453:1453)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (971:971:971)) + (PORT datab (1396:1396:1396) (1491:1491:1491)) + (PORT datac (646:646:646) (684:684:684)) + (PORT datad (359:359:359) (387:387:387)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal61\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1912:1912:1912) (1997:1997:1997)) + (PORT datab (1642:1642:1642) (1792:1792:1792)) + (PORT datac (607:607:607) (647:647:647)) + (PORT datad (1742:1742:1742) (1827:1827:1827)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1111:1111:1111) (1149:1149:1149)) + (PORT datab (933:933:933) (967:967:967)) + (PORT datac (2220:2220:2220) (2323:2323:2323)) + (PORT datad (1600:1600:1600) (1743:1743:1743)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1322:1322:1322) (1383:1383:1383)) + (PORT datab (934:934:934) (970:970:970)) + (PORT datac (2216:2216:2216) (2296:2296:2296)) + (PORT datad (1503:1503:1503) (1626:1626:1626)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~12) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1067:1067:1067)) + (PORT datab (877:877:877) (898:898:898)) + (PORT datac (210:210:210) (250:250:250)) + (PORT datad (202:202:202) (229:229:229)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (699:699:699)) + (PORT datab (1206:1206:1206) (1268:1268:1268)) + (PORT datac (1250:1250:1250) (1284:1284:1284)) + (PORT datad (568:568:568) (578:578:578)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1003:1003:1003) (1039:1039:1039)) + (PORT datab (1167:1167:1167) (1188:1188:1188)) + (PORT datac (1404:1404:1404) (1438:1438:1438)) + (PORT datad (912:912:912) (940:940:940)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (677:677:677)) + (PORT datab (921:921:921) (977:977:977)) + (PORT datac (1473:1473:1473) (1537:1537:1537)) + (PORT datad (1145:1145:1145) (1179:1179:1179)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (933:933:933)) + (PORT datab (1131:1131:1131) (1170:1170:1170)) + (PORT datac (367:367:367) (395:395:395)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1210:1210:1210) (1285:1285:1285)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (186:186:186) (225:225:225)) + (PORT datad (2031:2031:2031) (2148:2148:2148)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) + (DELAY + (ABSOLUTE + (PORT datab (237:237:237) (281:281:281)) + (PORT datac (208:208:208) (249:249:249)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) + (DELAY + (ABSOLUTE + (PORT dataa (3682:3682:3682) (3765:3765:3765)) + (PORT datab (960:960:960) (1060:1060:1060)) + (PORT datac (1232:1232:1232) (1308:1308:1308)) + (PORT datad (669:669:669) (723:723:723)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1998:1998:1998) (2157:2157:2157)) + (PORT datab (1471:1471:1471) (1519:1519:1519)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (1320:1320:1320) (1494:1494:1494)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (722:722:722) (790:790:790)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (1592:1592:1592) (1634:1634:1634)) + (PORT datad (1467:1467:1467) (1572:1572:1572)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1102:1102:1102)) + (PORT datab (786:786:786) (892:892:892)) + (PORT datac (1471:1471:1471) (1536:1536:1536)) + (PORT datad (633:633:633) (692:692:692)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2044:2044:2044) (2134:2134:2134)) + (PORT datab (1124:1124:1124) (1155:1155:1155)) + (PORT datac (860:860:860) (892:892:892)) + (PORT datad (666:666:666) (722:722:722)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~39) + (DELAY + (ABSOLUTE + (PORT dataa (983:983:983) (1100:1100:1100)) + (PORT datab (759:759:759) (866:866:866)) + (PORT datac (1473:1473:1473) (1536:1536:1536)) + (PORT datad (893:893:893) (939:939:939)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (1473:1473:1473) (1522:1522:1522)) + (PORT datac (1014:1014:1014) (1048:1048:1048)) + (PORT datad (607:607:607) (642:642:642)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) + (DELAY + (ABSOLUTE + (PORT dataa (963:963:963) (997:997:997)) + (PORT datab (1257:1257:1257) (1285:1285:1285)) + (PORT datac (177:177:177) (214:214:214)) + (PORT datad (867:867:867) (902:902:902)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1728:1728:1728) (1837:1837:1837)) + (PORT datac (1359:1359:1359) (1427:1427:1427)) + (PORT datad (1691:1691:1691) (1791:1791:1791)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) + (DELAY + (ABSOLUTE + (PORT dataa (625:625:625) (649:649:649)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (1066:1066:1066) (1088:1088:1088)) + (PORT datad (841:841:841) (877:877:877)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (672:672:672)) + (PORT datab (1188:1188:1188) (1223:1223:1223)) + (PORT datac (506:506:506) (518:518:518)) + (PORT datad (190:190:190) (222:222:222)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) + (DELAY + (ABSOLUTE + (PORT dataa (957:957:957) (1055:1055:1055)) + (PORT datab (1495:1495:1495) (1572:1572:1572)) + (PORT datac (190:190:190) (232:232:232)) + (PORT datad (205:205:205) (242:242:242)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1404:1404:1404) (1572:1572:1572)) + (PORT datac (1211:1211:1211) (1292:1292:1292)) + (PORT datad (1320:1320:1320) (1484:1484:1484)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1404:1404:1404) (1567:1567:1567)) + (PORT datab (1663:1663:1663) (1731:1731:1731)) + (PORT datac (1737:1737:1737) (1850:1850:1850)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1403:1403:1403) (1571:1571:1571)) + (PORT datab (2575:2575:2575) (2767:2767:2767)) + (PORT datac (1204:1204:1204) (1249:1249:1249)) + (PORT datad (887:887:887) (915:915:915)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1241:1241:1241) (1265:1265:1265)) + (PORT datab (618:618:618) (643:643:643)) + (PORT datac (209:209:209) (250:250:250)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1682:1682:1682) (1783:1783:1783)) + (PORT datab (2598:2598:2598) (2784:2784:2784)) + (PORT datac (1652:1652:1652) (1819:1819:1819)) + (PORT datad (1573:1573:1573) (1595:1595:1595)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1265:1265:1265) (1319:1319:1319)) + (PORT datab (1090:1090:1090) (1145:1145:1145)) + (PORT datac (1586:1586:1586) (1738:1738:1738)) + (PORT datad (1474:1474:1474) (1508:1508:1508)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~17) + (DELAY + (ABSOLUTE + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (1089:1089:1089) (1133:1133:1133)) + (PORT datad (218:218:218) (256:256:256)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1475:1475:1475) (1530:1530:1530)) + (PORT datab (1552:1552:1552) (1583:1583:1583)) + (PORT datac (1503:1503:1503) (1583:1583:1583)) + (PORT datad (1969:1969:1969) (2022:2022:2022)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (982:982:982)) + (PORT datab (685:685:685) (707:707:707)) + (PORT datac (623:623:623) (648:648:648)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (256:256:256)) + (PORT datab (648:648:648) (674:674:674)) + (PORT datac (902:902:902) (952:952:952)) + (PORT datad (923:923:923) (972:972:972)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) + (DELAY + (ABSOLUTE + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (1346:1346:1346) (1374:1374:1374)) + (PORT datad (825:825:825) (853:853:853)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~19) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (907:907:907)) + (PORT datab (1078:1078:1078) (1132:1132:1132)) + (PORT datac (515:515:515) (534:534:534)) + (PORT datad (522:522:522) (533:533:533)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1320:1320:1320) (1381:1381:1381)) + (PORT datab (2246:2246:2246) (2335:2335:2335)) + (PORT datac (1395:1395:1395) (1531:1531:1531)) + (PORT datad (908:908:908) (933:933:933)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1222:1222:1222)) + (PORT datab (1197:1197:1197) (1273:1273:1273)) + (PORT datac (877:877:877) (942:942:942)) + (PORT datad (1209:1209:1209) (1259:1259:1259)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (986:986:986)) + (PORT datab (935:935:935) (974:974:974)) + (PORT datac (1208:1208:1208) (1267:1267:1267)) + (PORT datad (580:580:580) (609:609:609)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1309:1309:1309) (1367:1367:1367)) + (PORT datab (1760:1760:1760) (1823:1823:1823)) + (PORT datac (780:780:780) (832:832:832)) + (PORT datad (2119:2119:2119) (2113:2113:2113)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1130:1130:1130) (1164:1164:1164)) + (PORT datab (1248:1248:1248) (1297:1297:1297)) + (PORT datad (900:900:900) (967:967:967)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (957:957:957) (1008:1008:1008)) + (PORT datab (667:667:667) (689:689:689)) + (PORT datac (844:844:844) (882:882:882)) + (PORT datad (865:865:865) (875:875:875)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) + (DELAY + (ABSOLUTE + (PORT datab (1146:1146:1146) (1171:1171:1171)) + (PORT datac (202:202:202) (240:240:240)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (705:705:705)) + (PORT datab (344:344:344) (376:376:376)) + (PORT datac (1158:1158:1158) (1183:1183:1183)) + (PORT datad (942:942:942) (987:987:987)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1122:1122:1122) (1155:1155:1155)) + (PORT datab (660:660:660) (713:713:713)) + (PORT datac (904:904:904) (922:922:922)) + (PORT datad (820:820:820) (840:840:840)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (266:266:266)) + (PORT datab (240:240:240) (286:286:286)) + (PORT datac (211:211:211) (254:254:254)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1301:1301:1301) (1320:1320:1320)) + (PORT datab (2020:2020:2020) (2143:2143:2143)) + (PORT datac (1955:1955:1955) (2058:2058:2058)) + (PORT datad (1295:1295:1295) (1376:1376:1376)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1214:1214:1214) (1262:1262:1262)) + (PORT datab (1197:1197:1197) (1269:1269:1269)) + (PORT datac (1021:1021:1021) (1050:1050:1050)) + (PORT datad (315:315:315) (333:333:333)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~18) + (DELAY + (ABSOLUTE + (PORT dataa (2144:2144:2144) (2265:2265:2265)) + (PORT datab (1690:1690:1690) (1867:1867:1867)) + (PORT datac (604:604:604) (619:619:619)) + (PORT datad (2025:2025:2025) (2071:2071:2071)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (2076:2076:2076) (2173:2173:2173)) + (PORT datab (1169:1169:1169) (1260:1260:1260)) + (PORT datac (1442:1442:1442) (1488:1488:1488)) + (PORT datad (1368:1368:1368) (1396:1396:1396)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (942:942:942)) + (PORT datab (677:677:677) (721:721:721)) + (PORT datac (1761:1761:1761) (1841:1841:1841)) + (PORT datad (1762:1762:1762) (1819:1819:1819)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1433:1433:1433) (1482:1482:1482)) + (PORT datab (910:910:910) (937:937:937)) + (PORT datac (1440:1440:1440) (1519:1519:1519)) + (PORT datad (838:838:838) (870:870:870)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (961:961:961)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (619:619:619) (672:672:672)) + (PORT datad (598:598:598) (648:648:648)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (911:911:911)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (812:812:812) (847:847:847)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (693:693:693)) + (PORT datab (661:661:661) (693:693:693)) + (PORT datac (634:634:634) (677:677:677)) + (PORT datad (348:348:348) (370:370:370)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1228:1228:1228) (1319:1319:1319)) + (PORT datab (1236:1236:1236) (1274:1274:1274)) + (PORT datac (625:625:625) (679:679:679)) + (PORT datad (1191:1191:1191) (1247:1247:1247)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (950:950:950) (979:979:979)) + (PORT datad (624:624:624) (649:649:649)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~17) + (DELAY + (ABSOLUTE + (PORT dataa (2353:2353:2353) (2461:2461:2461)) + (PORT datab (976:976:976) (1005:1005:1005)) + (PORT datac (1088:1088:1088) (1104:1104:1104)) + (PORT datad (1772:1772:1772) (1890:1890:1890)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (907:907:907) (918:918:918)) + (PORT datac (1188:1188:1188) (1230:1230:1230)) + (PORT datad (1430:1430:1430) (1500:1500:1500)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datac (1693:1693:1693) (1727:1727:1727)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (672:672:672)) + (PORT datab (578:578:578) (605:605:605)) + (PORT datac (1476:1476:1476) (1572:1572:1572)) + (PORT datad (1639:1639:1639) (1701:1701:1701)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1271:1271:1271) (1315:1315:1315)) + (PORT datab (1165:1165:1165) (1196:1196:1196)) + (PORT datac (912:912:912) (969:969:969)) + (PORT datad (314:314:314) (333:333:333)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (256:256:256)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (1047:1047:1047) (1053:1053:1053)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1758:1758:1758) (1900:1900:1900)) + (PORT datab (902:902:902) (950:950:950)) + (PORT datac (1212:1212:1212) (1261:1261:1261)) + (PORT datad (2454:2454:2454) (2652:2652:2652)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) + (DELAY + (ABSOLUTE + (PORT datab (664:664:664) (686:686:686)) + (PORT datac (185:185:185) (223:223:223)) + (PORT datad (190:190:190) (222:222:222)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1193:1193:1193) (1290:1290:1290)) + (PORT datab (1597:1597:1597) (1747:1747:1747)) + (PORT datac (1512:1512:1512) (1646:1646:1646)) + (PORT datad (1772:1772:1772) (1860:1860:1860)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (2076:2076:2076) (2171:2171:2171)) + (PORT datab (1273:1273:1273) (1341:1341:1341)) + (PORT datac (1497:1497:1497) (1578:1578:1578)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (332:332:332)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (420:420:420)) + (PORT datab (1273:1273:1273) (1342:1342:1342)) + (PORT datac (1152:1152:1152) (1193:1193:1193)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (269:269:269)) + (PORT datab (601:601:601) (645:645:645)) + (PORT datac (1369:1369:1369) (1405:1405:1405)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (725:725:725)) + (PORT datab (952:952:952) (1009:1009:1009)) + (PORT datac (1500:1500:1500) (1582:1582:1582)) + (PORT datad (1167:1167:1167) (1248:1248:1248)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) + (DELAY + (ABSOLUTE + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (1458:1458:1458) (1477:1477:1477)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1302:1302:1302) (1377:1377:1377)) + (PORT datab (1178:1178:1178) (1247:1247:1247)) + (PORT datac (1503:1503:1503) (1562:1562:1562)) + (PORT datad (642:642:642) (693:693:693)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (255:255:255)) + (PORT datab (1217:1217:1217) (1266:1266:1266)) + (PORT datac (1500:1500:1500) (1564:1564:1564)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1389:1389:1389) (1465:1465:1465)) + (PORT datab (1685:1685:1685) (1852:1852:1852)) + (PORT datac (982:982:982) (980:980:980)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1140:1140:1140) (1183:1183:1183)) + (PORT datab (662:662:662) (713:713:713)) + (PORT datac (627:627:627) (681:681:681)) + (PORT datad (640:640:640) (676:676:676)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1655:1655:1655) (1726:1726:1726)) + (PORT datab (1375:1375:1375) (1391:1391:1391)) + (PORT datac (1118:1118:1118) (1174:1174:1174)) + (PORT datad (624:624:624) (643:643:643)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1183:1183:1183) (1210:1210:1210)) + (PORT datab (1380:1380:1380) (1398:1398:1398)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (257:257:257)) + (PORT datab (663:663:663) (690:690:690)) + (PORT datac (188:188:188) (229:229:229)) + (PORT datad (187:187:187) (218:218:218)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (384:384:384)) + (PORT datab (811:811:811) (819:819:819)) + (PORT datac (1421:1421:1421) (1484:1484:1484)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1645:1645:1645) (1680:1680:1680)) + (PORT datab (1246:1246:1246) (1316:1316:1316)) + (PORT datac (1499:1499:1499) (1579:1579:1579)) + (PORT datad (2049:2049:2049) (2131:2131:2131)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1799:1799:1799) (1901:1901:1901)) + (PORT datab (1594:1594:1594) (1745:1745:1745)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1620:1620:1620) (1635:1635:1635)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1533:1533:1533) (1601:1601:1601)) + (PORT datab (1750:1750:1750) (1829:1829:1829)) + (PORT datac (1522:1522:1522) (1600:1600:1600)) + (PORT datad (337:337:337) (356:356:356)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (332:332:332)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) + (DELAY + (ABSOLUTE + (PORT dataa (680:680:680) (761:761:761)) + (PORT datab (915:915:915) (968:968:968)) + (PORT datac (1718:1718:1718) (1796:1796:1796)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1531:1531:1531) (1599:1599:1599)) + (PORT datab (1097:1097:1097) (1130:1130:1130)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1896:1896:1896) (1969:1969:1969)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (761:761:761)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1068:1068:1068) (1100:1100:1100)) + (PORT datad (1691:1691:1691) (1730:1730:1730)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1460:1460:1460) (1483:1483:1483)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (631:631:631) (655:655:655)) + (PORT datad (1901:1901:1901) (1974:1974:1974)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (690:690:690)) + (PORT datab (610:610:610) (635:635:635)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1434:1434:1434) (1482:1482:1482)) + (PORT datab (979:979:979) (1023:1023:1023)) + (PORT datac (1196:1196:1196) (1241:1241:1241)) + (PORT datad (1188:1188:1188) (1214:1214:1214)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1171:1171:1171) (1204:1204:1204)) + (PORT datab (1148:1148:1148) (1184:1184:1184)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1749:1749:1749) (1821:1821:1821)) + (PORT datab (1396:1396:1396) (1445:1445:1445)) + (PORT datac (1206:1206:1206) (1248:1248:1248)) + (PORT datad (1501:1501:1501) (1578:1578:1578)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1747:1747:1747) (1821:1821:1821)) + (PORT datab (1398:1398:1398) (1449:1449:1449)) + (PORT datac (1474:1474:1474) (1513:1513:1513)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1260:1260:1260) (1306:1306:1306)) + (PORT datab (1543:1543:1543) (1626:1626:1626)) + (PORT datac (912:912:912) (982:982:982)) + (PORT datad (959:959:959) (1003:1003:1003)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1181:1181:1181) (1240:1240:1240)) + (PORT datab (994:994:994) (1040:1040:1040)) + (PORT datac (909:909:909) (977:977:977)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (984:984:984)) + (PORT datab (1911:1911:1911) (2074:2074:2074)) + (PORT datac (1899:1899:1899) (2060:2060:2060)) + (PORT datad (1058:1058:1058) (1086:1086:1086)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1235:1235:1235) (1286:1286:1286)) + (PORT datab (1215:1215:1215) (1233:1233:1233)) + (PORT datac (833:833:833) (881:881:881)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (624:624:624) (649:649:649)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (926:926:926)) + (PORT datab (875:875:875) (918:918:918)) + (PORT datac (635:635:635) (664:664:664)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2896:2896:2896) (2954:2954:2954)) + (PORT datab (1052:1052:1052) (1116:1116:1116)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (2591:2591:2591) (2649:2649:2649)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1270:1270:1270)) + (PORT datab (1101:1101:1101) (1135:1135:1135)) + (PORT datac (1363:1363:1363) (1380:1380:1380)) + (PORT datad (1191:1191:1191) (1245:1245:1245)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1384:1384:1384) (1464:1464:1464)) + (PORT datab (628:628:628) (673:673:673)) + (PORT datac (611:611:611) (637:637:637)) + (PORT datad (697:697:697) (744:744:744)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (853:853:853) (883:883:883)) + (PORT datab (877:877:877) (946:946:946)) + (PORT datac (2034:2034:2034) (2072:2072:2072)) + (PORT datad (821:821:821) (867:867:867)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2352:2352:2352) (2460:2460:2460)) + (PORT datab (979:979:979) (1005:1005:1005)) + (PORT datac (1863:1863:1863) (1892:1892:1892)) + (PORT datad (1775:1775:1775) (1890:1890:1890)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) + (DELAY + (ABSOLUTE + (PORT datac (1179:1179:1179) (1246:1246:1246)) + (PORT datad (1693:1693:1693) (1817:1817:1817)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (2042:2042:2042) (2132:2132:2132)) + (PORT datab (661:661:661) (679:679:679)) + (PORT datac (861:861:861) (893:893:893)) + (PORT datad (666:666:666) (723:723:723)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (265:265:265)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (859:859:859) (874:874:874)) + (PORT datad (340:340:340) (363:363:363)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1882:1882:1882) (2069:2069:2069)) + (PORT datab (1503:1503:1503) (1598:1598:1598)) + (PORT datac (1200:1200:1200) (1277:1277:1277)) + (PORT datad (613:613:613) (652:652:652)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (591:591:591) (609:609:609)) + (PORT datad (832:832:832) (884:884:884)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1622:1622:1622) (1656:1656:1656)) + (PORT datab (1011:1011:1011) (1122:1122:1122)) + (PORT datac (2246:2246:2246) (2401:2401:2401)) + (PORT datad (640:640:640) (657:657:657)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (399:399:399)) + (PORT datab (886:886:886) (926:926:926)) + (PORT datac (2213:2213:2213) (2293:2293:2293)) + (PORT datad (1158:1158:1158) (1220:1220:1220)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (649:649:649)) + (PORT datab (610:610:610) (643:643:643)) + (PORT datac (1089:1089:1089) (1103:1103:1103)) + (PORT datad (1426:1426:1426) (1497:1497:1497)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (1047:1047:1047)) + (PORT datab (1328:1328:1328) (1357:1357:1357)) + (PORT datac (1395:1395:1395) (1452:1452:1452)) + (PORT datad (180:180:180) (211:211:211)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1158:1158:1158) (1195:1195:1195)) + (PORT datab (908:908:908) (926:926:926)) + (PORT datac (616:616:616) (647:647:647)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1485:1485:1485) (1546:1546:1546)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (316:316:316) (335:335:335)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (953:953:953)) + (PORT datab (214:214:214) (257:257:257)) + (PORT datac (606:606:606) (625:625:625)) + (PORT datad (1433:1433:1433) (1446:1446:1446)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (955:955:955)) + (PORT datab (968:968:968) (1012:1012:1012)) + (PORT datac (766:766:766) (778:778:778)) + (PORT datad (180:180:180) (210:210:210)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (661:661:661)) + (PORT datab (1887:1887:1887) (1914:1914:1914)) + (PORT datac (951:951:951) (996:996:996)) + (PORT datad (1256:1256:1256) (1314:1314:1314)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (198:198:198) (235:235:235)) + (PORT datac (574:574:574) (617:617:617)) + (PORT datad (1077:1077:1077) (1104:1104:1104)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (396:396:396)) + (PORT datab (632:632:632) (663:663:663)) + (PORT datac (612:612:612) (624:624:624)) + (PORT datad (624:624:624) (639:639:639)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (950:950:950)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (1118:1118:1118) (1174:1174:1174)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (904:904:904)) + (PORT datab (2215:2215:2215) (2381:2381:2381)) + (PORT datac (1232:1232:1232) (1373:1373:1373)) + (PORT datad (2798:2798:2798) (2994:2994:2994)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (638:638:638)) + (PORT datab (687:687:687) (717:717:717)) + (PORT datac (934:934:934) (966:966:966)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (631:631:631)) + (PORT datac (895:895:895) (905:905:905)) + (PORT datad (841:841:841) (853:853:853)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1988:1988:1988) (2068:2068:2068)) + (PORT datab (363:363:363) (394:394:394)) + (PORT datad (869:869:869) (931:931:931)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_af) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1589:1589:1589) (1566:1566:1566)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1426:1426:1426) (1475:1475:1475)) + (PORT datab (1193:1193:1193) (1241:1241:1241)) + (PORT datac (846:846:846) (891:891:891)) + (PORT datad (1379:1379:1379) (1380:1380:1380)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) + (DELAY + (ABSOLUTE + (PORT dataa (1682:1682:1682) (1803:1803:1803)) + (PORT datac (632:632:632) (678:678:678)) + (PORT datad (1446:1446:1446) (1513:1513:1513)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1183:1183:1183) (1262:1262:1262)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1485:1485:1485) (1554:1554:1554)) + (PORT datab (656:656:656) (705:705:705)) + (PORT datad (1630:1630:1630) (1739:1739:1739)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) + (DELAY + (ABSOLUTE + (PORT dataa (1285:1285:1285) (1362:1362:1362)) + (PORT datab (897:897:897) (934:934:934)) + (PORT datac (1431:1431:1431) (1496:1496:1496)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) + (DELAY + (ABSOLUTE + (PORT datab (1464:1464:1464) (1531:1531:1531)) + (PORT datac (876:876:876) (924:924:924)) + (PORT datad (1249:1249:1249) (1317:1317:1317)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1014:1014:1014) (1056:1056:1056)) + (PORT ena (1485:1485:1485) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) + (DELAY + (ABSOLUTE + (PORT dataa (1300:1300:1300) (1381:1381:1381)) + (PORT datab (894:894:894) (929:929:929)) + (PORT datac (1433:1433:1433) (1499:1499:1499)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1016:1016:1016) (1059:1059:1059)) + (PORT ena (1475:1475:1475) (1479:1479:1479)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) + (DELAY + (ABSOLUTE + (PORT datab (1468:1468:1468) (1530:1530:1530)) + (PORT datac (879:879:879) (925:925:925)) + (PORT datad (1241:1241:1241) (1311:1311:1311)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (977:977:977)) + (PORT datab (243:243:243) (326:326:326)) + (PORT datad (893:893:893) (937:937:937)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (751:751:751) (842:842:842)) + (PORT datab (249:249:249) (332:332:332)) + (PORT datac (787:787:787) (792:792:792)) + (PORT datad (199:199:199) (237:237:237)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT datab (1462:1462:1462) (1531:1531:1531)) + (PORT datac (860:860:860) (902:902:902)) + (PORT datad (1246:1246:1246) (1318:1318:1318)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) + (DELAY + (ABSOLUTE + (PORT dataa (747:747:747) (841:841:841)) + (PORT datab (223:223:223) (271:271:271)) + (PORT datac (787:787:787) (791:791:791)) + (PORT datad (224:224:224) (296:296:296)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) + (DELAY + (ABSOLUTE + (PORT datab (1466:1466:1466) (1528:1528:1528)) + (PORT datac (844:844:844) (888:888:888)) + (PORT datad (1241:1241:1241) (1313:1313:1313)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) + (DELAY + (ABSOLUTE + (PORT datab (1468:1468:1468) (1532:1532:1532)) + (PORT datac (861:861:861) (900:900:900)) + (PORT datad (1254:1254:1254) (1327:1327:1327)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1423:1423:1423) (1482:1482:1482)) + (PORT ena (1546:1546:1546) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) + (DELAY + (ABSOLUTE + (PORT datab (1465:1465:1465) (1532:1532:1532)) + (PORT datac (841:841:841) (888:888:888)) + (PORT datad (1245:1245:1245) (1318:1318:1318)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1421:1421:1421) (1478:1478:1478)) + (PORT ena (1446:1446:1446) (1455:1455:1455)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (999:999:999) (1057:1057:1057)) + (PORT datab (966:966:966) (1013:1013:1013)) + (PORT datad (357:357:357) (414:414:414)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (854:854:854) (911:911:911)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1512:1512:1512) (1527:1527:1527)) + (PORT datab (1198:1198:1198) (1246:1246:1246)) + (PORT datac (1748:1748:1748) (1867:1867:1867)) + (PORT datad (1449:1449:1449) (1522:1522:1522)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) + (DELAY + (ABSOLUTE + (PORT datab (1615:1615:1615) (1723:1723:1723)) + (PORT datac (1085:1085:1085) (1141:1141:1141)) + (PORT datad (346:346:346) (373:373:373)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) + (DELAY + (ABSOLUTE + (PORT datab (1612:1612:1612) (1721:1721:1721)) + (PORT datac (1083:1083:1083) (1140:1140:1140)) + (PORT datad (343:343:343) (371:371:371)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) + (DELAY + (ABSOLUTE + (PORT datab (1611:1611:1611) (1718:1718:1718)) + (PORT datad (1731:1731:1731) (1794:1794:1794)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1515:1515:1515) (1529:1529:1529)) + (PORT datab (1784:1784:1784) (1902:1902:1902)) + (PORT datac (337:337:337) (362:362:362)) + (PORT datad (1160:1160:1160) (1205:1205:1205)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1411:1411:1411) (1470:1470:1470)) + (PORT ena (1196:1196:1196) (1165:1165:1165)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) + (DELAY + (ABSOLUTE + (PORT datab (1610:1610:1610) (1716:1716:1716)) + (PORT datac (1084:1084:1084) (1136:1136:1136)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1497:1497:1497) (1513:1513:1513)) + (PORT datab (376:376:376) (408:408:408)) + (PORT datac (1753:1753:1753) (1874:1874:1874)) + (PORT datad (1153:1153:1153) (1198:1198:1198)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (473:473:473) (552:552:552)) + (PORT datab (498:498:498) (554:554:554)) + (PORT datad (627:627:627) (659:659:659)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (599:599:599) (636:636:636)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1426:1426:1426) (1476:1476:1476)) + (PORT datab (1193:1193:1193) (1241:1241:1241)) + (PORT datac (341:341:341) (367:367:367)) + (PORT datad (1380:1380:1380) (1380:1380:1380)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1476:1476:1476) (1478:1478:1478)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1514:1514:1514) (1527:1527:1527)) + (PORT datab (371:371:371) (402:402:402)) + (PORT datac (1398:1398:1398) (1441:1441:1441)) + (PORT datad (1158:1158:1158) (1204:1204:1204)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (706:706:706)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (180:180:180) (216:216:216)) + (PORT datad (208:208:208) (240:240:240)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (2055:2055:2055) (2081:2081:2081)) + (PORT datab (1404:1404:1404) (1511:1511:1511)) + (PORT datac (2090:2090:2090) (2260:2260:2260)) + (PORT datad (875:875:875) (901:901:901)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1051:1051:1051) (1073:1073:1073)) + (PORT datab (1268:1268:1268) (1350:1350:1350)) + (PORT datac (1926:1926:1926) (1930:1930:1930)) + (PORT datad (363:363:363) (385:385:385)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (276:276:276)) + (PORT datac (588:588:588) (636:636:636)) + (PORT datad (822:822:822) (847:847:847)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) + (DELAY + (ABSOLUTE + (PORT dataa (679:679:679) (721:721:721)) + (PORT datab (218:218:218) (264:264:264)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (263:263:263)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (860:860:860) (875:875:875)) + (PORT datad (642:642:642) (659:659:659)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) + (DELAY + (ABSOLUTE + (PORT dataa (964:964:964) (1041:1041:1041)) + (PORT datac (916:916:916) (968:968:968)) + (PORT datad (1214:1214:1214) (1282:1282:1282)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (950:950:950) (983:983:983)) + (PORT ena (1186:1186:1186) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) + (DELAY + (ABSOLUTE + (PORT dataa (963:963:963) (1034:1034:1034)) + (PORT datac (915:915:915) (966:966:966)) + (PORT datad (1213:1213:1213) (1277:1277:1277)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (328:328:328)) + (PORT datab (959:959:959) (999:999:999)) + (PORT datad (880:880:880) (921:921:921)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1509:1509:1509) (1526:1526:1526)) + (PORT datab (1196:1196:1196) (1249:1249:1249)) + (PORT datac (341:341:341) (369:369:369)) + (PORT datad (582:582:582) (643:643:643)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1509:1509:1509) (1526:1526:1526)) + (PORT datab (611:611:611) (683:683:683)) + (PORT datac (338:338:338) (364:364:364)) + (PORT datad (1156:1156:1156) (1205:1205:1205)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1439:1439:1439) (1498:1498:1498)) + (PORT ena (1163:1163:1163) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1506:1506:1506) (1523:1523:1523)) + (PORT datab (609:609:609) (680:680:680)) + (PORT datac (340:340:340) (366:366:366)) + (PORT datad (1150:1150:1150) (1203:1203:1203)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1444:1444:1444) (1503:1503:1503)) + (PORT ena (1213:1213:1213) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1511:1511:1511) (1527:1527:1527)) + (PORT datab (1197:1197:1197) (1246:1246:1246)) + (PORT datac (341:341:341) (368:368:368)) + (PORT datad (582:582:582) (639:639:639)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (705:705:705)) + (PORT datab (243:243:243) (326:326:326)) + (PORT datad (626:626:626) (663:663:663)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1429:1429:1429) (1476:1476:1476)) + (PORT datab (1197:1197:1197) (1247:1247:1247)) + (PORT datac (850:850:850) (893:893:893)) + (PORT datad (1383:1383:1383) (1381:1381:1381)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) + (DELAY + (ABSOLUTE + (PORT dataa (1488:1488:1488) (1561:1561:1561)) + (PORT datab (902:902:902) (929:929:929)) + (PORT datad (1637:1637:1637) (1751:1751:1751)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (1609:1609:1609) (1656:1656:1656)) + (PORT datac (887:887:887) (932:932:932)) + (PORT datad (209:209:209) (241:241:241)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1674:1674:1674) (1748:1748:1748)) + (PORT datab (392:392:392) (418:418:418)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (886:886:886) (902:902:902)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) + (DELAY + (ABSOLUTE + (PORT dataa (1486:1486:1486) (1558:1558:1558)) + (PORT datab (908:908:908) (935:935:935)) + (PORT datad (1629:1629:1629) (1743:1743:1743)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1414:1414:1414) (1474:1474:1474)) + (PORT ena (1256:1256:1256) (1255:1255:1255)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (984:984:984) (1031:1031:1031)) + (PORT datab (1291:1291:1291) (1331:1331:1331)) + (PORT datad (874:874:874) (906:906:906)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (1320:1320:1320) (1335:1335:1335)) + (PORT datac (335:335:335) (358:358:358)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (672:672:672)) + (PORT datab (555:555:555) (576:576:576)) + (PORT datac (825:825:825) (840:840:840)) + (PORT datad (1032:1032:1032) (1101:1101:1101)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (385:385:385)) + (PORT datab (1380:1380:1380) (1398:1398:1398)) + (PORT datac (1123:1123:1123) (1180:1180:1180)) + (PORT datad (622:622:622) (640:640:640)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (690:690:690) (732:732:732)) + (PORT datab (891:891:891) (930:930:930)) + (PORT datac (1215:1215:1215) (1263:1263:1263)) + (PORT datad (560:560:560) (577:577:577)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (264:264:264)) + (PORT datab (875:875:875) (893:893:893)) + (PORT datac (344:344:344) (372:372:372)) + (PORT datad (1110:1110:1110) (1122:1122:1122)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (220:220:220) (258:258:258)) + (PORT datac (615:615:615) (641:641:641)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (581:581:581) (593:593:593)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datac (195:195:195) (228:228:228)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (962:962:962)) + (PORT datab (1357:1357:1357) (1408:1408:1408)) + (PORT datac (1375:1375:1375) (1378:1378:1378)) + (PORT datad (793:793:793) (845:845:845)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (658:658:658)) + (PORT datab (1361:1361:1361) (1409:1409:1409)) + (PORT datac (412:412:412) (449:449:449)) + (PORT datad (209:209:209) (242:242:242)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1495:1495:1495) (1563:1563:1563)) + (PORT datab (841:841:841) (869:869:869)) + (PORT datac (809:809:809) (891:891:891)) + (PORT datad (837:837:837) (886:886:886)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) + (DELAY + (ABSOLUTE + (PORT dataa (964:964:964) (994:994:994)) + (PORT datab (1403:1403:1403) (1460:1460:1460)) + (PORT datac (1085:1085:1085) (1138:1138:1138)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1124:1124:1124) (1165:1165:1165)) + (PORT datab (1867:1867:1867) (1942:1942:1942)) + (PORT datac (842:842:842) (905:905:905)) + (PORT datad (626:626:626) (662:662:662)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1190:1190:1190) (1209:1209:1209)) + (PORT datab (1474:1474:1474) (1514:1514:1514)) + (PORT datac (1094:1094:1094) (1102:1102:1102)) + (PORT datad (1208:1208:1208) (1297:1297:1297)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1236:1236:1236) (1289:1289:1289)) + (PORT datab (1163:1163:1163) (1196:1196:1196)) + (PORT datac (917:917:917) (959:959:959)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) + (DELAY + (ABSOLUTE + (PORT dataa (854:854:854) (896:896:896)) + (PORT datab (814:814:814) (835:835:835)) + (PORT datac (1604:1604:1604) (1624:1624:1624)) + (PORT datad (1091:1091:1091) (1104:1104:1104)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1005:1005:1005) (1081:1081:1081)) + (PORT datab (643:643:643) (686:686:686)) + (PORT datac (880:880:880) (916:916:916)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1506:1506:1506) (1583:1583:1583)) + (PORT datab (645:645:645) (676:676:676)) + (PORT datac (924:924:924) (965:965:965)) + (PORT datad (1191:1191:1191) (1244:1244:1244)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (263:263:263)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1363:1363:1363) (1381:1381:1381)) + (PORT datad (584:584:584) (632:632:632)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1381:1381:1381) (1468:1468:1468)) + (PORT datab (376:376:376) (404:404:404)) + (PORT datac (631:631:631) (672:672:672)) + (PORT datad (695:695:695) (746:746:746)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (972:972:972) (1011:1011:1011)) + (PORT datab (845:845:845) (882:882:882)) + (PORT datac (544:544:544) (563:563:563)) + (PORT datad (1121:1121:1121) (1121:1121:1121)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1134:1134:1134) (1168:1168:1168)) + (PORT datab (927:927:927) (955:955:955)) + (PORT datac (1207:1207:1207) (1250:1250:1250)) + (PORT datad (1220:1220:1220) (1269:1269:1269)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) + (DELAY + (ABSOLUTE + (PORT datab (205:205:205) (246:246:246)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (175:175:175) (202:202:202)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1125:1125:1125) (1132:1132:1132)) + (PORT datab (613:613:613) (653:653:653)) + (PORT datac (186:186:186) (227:227:227)) + (PORT datad (836:836:836) (844:844:844)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) + (DELAY + (ABSOLUTE + (PORT datab (2020:2020:2020) (2146:2146:2146)) + (PORT datac (1954:1954:1954) (2061:2061:2061)) + (PORT datad (1620:1620:1620) (1793:1793:1793)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1338:1338:1338) (1426:1426:1426)) + (PORT datab (1201:1201:1201) (1270:1270:1270)) + (PORT datac (1175:1175:1175) (1230:1230:1230)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) + (DELAY + (ABSOLUTE + (PORT datac (842:842:842) (866:866:866)) + (PORT datad (625:625:625) (636:636:636)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (592:592:592)) + (PORT datab (387:387:387) (415:415:415)) + (PORT datac (1088:1088:1088) (1123:1123:1123)) + (PORT datad (809:809:809) (841:841:841)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_xf) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~50) + (DELAY + (ABSOLUTE + (PORT dataa (1561:1561:1561) (1660:1660:1660)) + (PORT datab (1645:1645:1645) (1688:1688:1688)) + (PORT datac (1674:1674:1674) (1745:1745:1745)) + (PORT datad (1153:1153:1153) (1190:1190:1190)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (717:717:717)) + (PORT datab (1418:1418:1418) (1466:1466:1466)) + (PORT datac (927:927:927) (1002:1002:1002)) + (PORT datad (320:320:320) (342:342:342)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (453:453:453)) + (PORT datab (381:381:381) (414:414:414)) + (PORT datac (948:948:948) (997:997:997)) + (PORT datad (902:902:902) (929:929:929)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (924:924:924)) + (PORT datab (1172:1172:1172) (1217:1217:1217)) + (PORT datad (586:586:586) (617:617:617)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (665:665:665)) + (PORT datab (400:400:400) (448:448:448)) + (PORT datac (903:903:903) (950:950:950)) + (PORT datad (1154:1154:1154) (1178:1178:1178)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1138:1138:1138) (1171:1171:1171)) + (PORT datad (1850:1850:1850) (1892:1892:1892)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1156:1156:1156) (1190:1190:1190)) + (PORT datab (1154:1154:1154) (1186:1186:1186)) + (PORT datac (1365:1365:1365) (1404:1404:1404)) + (PORT datad (1108:1108:1108) (1127:1127:1127)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (413:413:413)) + (PORT datab (1708:1708:1708) (1765:1765:1765)) + (PORT datac (1580:1580:1580) (1686:1686:1686)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) + (DELAY + (ABSOLUTE + (PORT datac (1414:1414:1414) (1421:1421:1421)) + (PORT datad (1852:1852:1852) (1893:1893:1893)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1157:1157:1157) (1191:1191:1191)) + (PORT datab (1155:1155:1155) (1186:1186:1186)) + (PORT datac (1366:1366:1366) (1405:1405:1405)) + (PORT datad (826:826:826) (842:842:842)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (681:681:681) (708:708:708)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (413:413:413)) + (PORT datab (1709:1709:1709) (1766:1766:1766)) + (PORT datac (1579:1579:1579) (1681:1681:1681)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1712:1712:1712) (1752:1752:1752)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (261:261:261) (325:325:325)) + (PORT datab (1404:1404:1404) (1519:1519:1519)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) + (DELAY + (ABSOLUTE + (PORT dataa (1297:1297:1297) (1374:1374:1374)) + (PORT datac (1019:1019:1019) (1043:1043:1043)) + (PORT datad (1368:1368:1368) (1412:1412:1412)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (1138:1138:1138) (1174:1174:1174)) + (PORT datab (371:371:371) (403:403:403)) + (PORT datad (1851:1851:1851) (1894:1894:1894)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) + (DELAY + (ABSOLUTE + (PORT dataa (1290:1290:1290) (1369:1369:1369)) + (PORT datac (1018:1018:1018) (1041:1041:1041)) + (PORT datad (1364:1364:1364) (1407:1407:1407)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1699:1699:1699) (1727:1727:1727)) + (PORT ena (1147:1147:1147) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (905:905:905) (954:954:954)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (1141:1141:1141) (1172:1172:1172)) + (PORT datab (368:368:368) (402:402:402)) + (PORT datad (1853:1853:1853) (1893:1893:1893)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1248:1248:1248) (1262:1262:1262)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (663:663:663)) + (PORT datab (940:940:940) (1000:1000:1000)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) + (DELAY + (ABSOLUTE + (PORT dataa (1281:1281:1281) (1368:1368:1368)) + (PORT datab (1005:1005:1005) (1055:1055:1055)) + (PORT datac (915:915:915) (968:968:968)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1377:1377:1377) (1394:1394:1394)) + (PORT datab (228:228:228) (270:270:270)) + (PORT datac (1112:1112:1112) (1132:1132:1132)) + (PORT datad (596:596:596) (654:654:654)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (838:838:838)) + (PORT datab (218:218:218) (257:257:257)) + (PORT datac (859:859:859) (867:867:867)) + (PORT datad (1351:1351:1351) (1364:1364:1364)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (970:970:970) (999:999:999)) + (PORT ena (1243:1243:1243) (1273:1273:1273)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1199:1199:1199) (1256:1256:1256)) + (PORT datab (676:676:676) (714:714:714)) + (PORT datad (959:959:959) (992:992:992)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) + (DELAY + (ABSOLUTE + (PORT dataa (1275:1275:1275) (1362:1362:1362)) + (PORT datab (1010:1010:1010) (1056:1056:1056)) + (PORT datac (916:916:916) (969:969:969)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (969:969:969) (1001:1001:1001)) + (PORT ena (1168:1168:1168) (1161:1161:1161)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (459:459:459)) + (PORT datab (197:197:197) (236:236:236)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1509:1509:1509) (1527:1527:1527)) + (PORT datab (1196:1196:1196) (1250:1250:1250)) + (PORT datac (1752:1752:1752) (1873:1873:1873)) + (PORT datad (543:543:543) (551:551:551)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT asdata (1136:1136:1136) (1158:1158:1158)) + (PORT ena (961:961:961) (970:970:970)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1742:1742:1742) (1856:1856:1856)) + (PORT datab (1391:1391:1391) (1393:1393:1393)) + (PORT datac (1113:1113:1113) (1130:1130:1130)) + (PORT datad (1127:1127:1127) (1128:1128:1128)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1151:1151:1151) (1170:1170:1170)) + (PORT datab (624:624:624) (692:692:692)) + (PORT datac (1345:1345:1345) (1352:1352:1352)) + (PORT datad (823:823:823) (830:830:830)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT asdata (1134:1134:1134) (1155:1155:1155)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1380:1380:1380) (1395:1395:1395)) + (PORT datab (227:227:227) (268:268:268)) + (PORT datac (1113:1113:1113) (1134:1134:1134)) + (PORT datad (597:597:597) (655:655:655)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (330:330:330)) + (PORT datab (247:247:247) (295:295:295)) + (PORT datad (211:211:211) (244:244:244)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (696:696:696)) + (PORT datab (660:660:660) (673:673:673)) + (PORT datac (762:762:762) (771:771:771)) + (PORT datad (596:596:596) (645:645:645)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) + (DELAY + (ABSOLUTE + (PORT dataa (1296:1296:1296) (1377:1377:1377)) + (PORT datac (840:840:840) (891:891:891)) + (PORT datad (1367:1367:1367) (1411:1411:1411)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) + (DELAY + (ABSOLUTE + (PORT dataa (1300:1300:1300) (1381:1381:1381)) + (PORT datac (861:861:861) (899:899:899)) + (PORT datad (1371:1371:1371) (1413:1413:1413)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT dataa (1300:1300:1300) (1380:1380:1380)) + (PORT datac (861:861:861) (899:899:899)) + (PORT datad (1371:1371:1371) (1413:1413:1413)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1201:1201:1201) (1221:1221:1221)) + (PORT ena (984:984:984) (983:983:983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (676:676:676) (712:712:712)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) + (DELAY + (ABSOLUTE + (PORT dataa (1299:1299:1299) (1381:1381:1381)) + (PORT datac (841:841:841) (888:888:888)) + (PORT datad (1369:1369:1369) (1414:1414:1414)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (923:923:923) (907:907:907)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (459:459:459)) + (PORT datab (449:449:449) (481:481:481)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1109:1109:1109) (1118:1118:1118)) + (PORT ena (1426:1426:1426) (1409:1409:1409)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1107:1107:1107) (1116:1116:1116)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (248:248:248) (312:312:312)) + (PORT datab (1080:1080:1080) (1119:1119:1119)) + (PORT datad (362:362:362) (415:415:415)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (701:701:701)) + (PORT datab (642:642:642) (676:676:676)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~91) + (DELAY + (ABSOLUTE + (PORT dataa (1879:1879:1879) (1937:1937:1937)) + (PORT datab (1816:1816:1816) (1903:1903:1903)) + (PORT datac (209:209:209) (252:252:252)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (892:892:892)) + (PORT datab (878:878:878) (922:922:922)) + (PORT datac (538:538:538) (540:540:540)) + (PORT datad (617:617:617) (645:645:645)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1174:1174:1174) (1222:1222:1222)) + (PORT datab (1045:1045:1045) (1100:1100:1100)) + (PORT datac (695:695:695) (747:747:747)) + (PORT datad (1116:1116:1116) (1134:1134:1134)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1256:1256:1256)) + (PORT datab (677:677:677) (742:742:742)) + (PORT datac (546:546:546) (556:556:556)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (528:528:528) (548:548:548)) + (PORT datab (646:646:646) (698:698:698)) + (PORT datac (641:641:641) (670:670:670)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1222:1222:1222) (1224:1224:1224)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (537:537:537) (568:568:568)) + (PORT ena (1237:1237:1237) (1220:1220:1220)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1466:1466:1466) (1518:1518:1518)) + (PORT datab (576:576:576) (596:596:596)) + (PORT datad (642:642:642) (669:669:669)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (460:460:460)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (607:607:607) (629:629:629)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (1052:1052:1052)) + (PORT datab (442:442:442) (513:513:513)) + (PORT datac (1170:1170:1170) (1219:1219:1219)) + (PORT datad (423:423:423) (496:496:496)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (1794:1794:1794) (1867:1867:1867)) + (PORT datab (1235:1235:1235) (1271:1271:1271)) + (PORT datac (1201:1201:1201) (1255:1255:1255)) + (PORT datad (985:985:985) (1038:1038:1038)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (910:910:910) (962:962:962)) + (PORT datad (182:182:182) (214:214:214)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) + (DELAY + (ABSOLUTE + (PORT dataa (1762:1762:1762) (1747:1747:1747)) + (PORT datab (1212:1212:1212) (1248:1248:1248)) + (PORT datac (634:634:634) (657:657:657)) + (PORT datad (825:825:825) (876:876:876)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (685:685:685)) + (PORT datab (647:647:647) (666:666:666)) + (PORT datad (880:880:880) (928:928:928)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (963:963:963)) + (PORT datab (1141:1141:1141) (1159:1159:1159)) + (PORT datac (1626:1626:1626) (1670:1670:1670)) + (PORT datad (878:878:878) (910:910:910)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (371:371:371)) + (PORT datab (915:915:915) (950:950:950)) + (PORT datac (1075:1075:1075) (1082:1082:1082)) + (PORT datad (1088:1088:1088) (1108:1108:1108)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1162:1162:1162) (1199:1199:1199)) + (PORT datab (826:826:826) (911:911:911)) + (PORT datac (1135:1135:1135) (1158:1158:1158)) + (PORT datad (788:788:788) (836:836:836)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1099:1099:1099) (1136:1136:1136)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (997:997:997) (1023:1023:1023)) + (PORT datad (886:886:886) (940:940:940)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1004:1004:1004) (1084:1084:1084)) + (PORT datab (954:954:954) (1049:1049:1049)) + (PORT datac (1094:1094:1094) (1101:1101:1101)) + (PORT datad (195:195:195) (232:232:232)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (947:947:947)) + (PORT datab (837:837:837) (839:839:839)) + (PORT datac (413:413:413) (484:484:484)) + (PORT datad (636:636:636) (716:716:716)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1143:1143:1143) (1162:1162:1162)) + (PORT datab (392:392:392) (471:471:471)) + (PORT datac (1098:1098:1098) (1115:1115:1115)) + (PORT datad (640:640:640) (718:718:718)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (636:636:636)) + (PORT datab (1622:1622:1622) (1684:1684:1684)) + (PORT datac (180:180:180) (218:218:218)) + (PORT datad (862:862:862) (899:899:899)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) + (DELAY + (ABSOLUTE + (PORT dataa (728:728:728) (795:795:795)) + (PORT datab (227:227:227) (268:268:268)) + (PORT datac (201:201:201) (238:238:238)) + (PORT datad (983:983:983) (1020:1020:1020)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1469:1469:1469) (1520:1520:1520)) + (PORT datab (636:636:636) (670:670:670)) + (PORT datac (1209:1209:1209) (1261:1261:1261)) + (PORT datad (653:653:653) (675:675:675)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~25) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (453:453:453)) + (PORT datab (293:293:293) (385:385:385)) + (PORT datad (251:251:251) (325:325:325)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (700:700:700)) + (PORT datab (1035:1035:1035) (1050:1050:1050)) + (PORT datac (1203:1203:1203) (1278:1278:1278)) + (PORT datad (2028:2028:2028) (2053:2053:2053)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla20M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (985:985:985) (1105:1105:1105)) + (PORT datab (783:783:783) (893:893:893)) + (PORT datac (1472:1472:1472) (1539:1539:1539)) + (PORT datad (893:893:893) (943:943:943)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) + (DELAY + (ABSOLUTE + (PORT dataa (725:725:725) (830:830:830)) + (PORT datab (2475:2475:2475) (2536:2536:2536)) + (PORT datac (1334:1334:1334) (1380:1380:1380)) + (PORT datad (707:707:707) (810:810:810)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (867:867:867)) + (PORT datab (655:655:655) (692:692:692)) + (PORT datac (845:845:845) (859:859:859)) + (PORT datad (831:831:831) (863:863:863)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) + (DELAY + (ABSOLUTE + (PORT dataa (1008:1008:1008) (1085:1085:1085)) + (PORT datab (899:899:899) (926:926:926)) + (PORT datac (925:925:925) (1014:1014:1014)) + (PORT datad (194:194:194) (228:228:228)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) + (DELAY + (ABSOLUTE + (PORT dataa (1046:1046:1046) (1122:1122:1122)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) + (DELAY + (ABSOLUTE + (PORT dataa (1231:1231:1231) (1258:1258:1258)) + (PORT datab (1956:1956:1956) (2026:2026:2026)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (575:575:575) (577:577:577)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) + (DELAY + (ABSOLUTE + (PORT dataa (1423:1423:1423) (1498:1498:1498)) + (PORT datab (1500:1500:1500) (1572:1572:1572)) + (PORT datac (866:866:866) (926:926:926)) + (PORT datad (1174:1174:1174) (1212:1212:1212)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1205:1205:1205)) + (PORT datab (873:873:873) (884:884:884)) + (PORT datac (670:670:670) (726:726:726)) + (PORT datad (1092:1092:1092) (1114:1114:1114)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) + (DELAY + (ABSOLUTE + (PORT dataa (1724:1724:1724) (1770:1770:1770)) + (PORT datab (1956:1956:1956) (2027:2027:2027)) + (PORT datac (609:609:609) (664:664:664)) + (PORT datad (828:828:828) (846:846:846)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1195:1195:1195) (1241:1241:1241)) + (PORT datab (704:704:704) (759:759:759)) + (PORT datac (192:192:192) (226:226:226)) + (PORT datad (683:683:683) (746:746:746)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (277:277:277)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (614:614:614) (645:645:645)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~18) + (DELAY + (ABSOLUTE + (PORT dataa (2201:2201:2201) (2281:2281:2281)) + (PORT datab (1459:1459:1459) (1512:1512:1512)) + (PORT datac (730:730:730) (781:781:781)) + (PORT datad (216:216:216) (249:249:249)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1006:1006:1006) (1082:1082:1082)) + (PORT datab (957:957:957) (1052:1052:1052)) + (PORT datac (599:599:599) (626:626:626)) + (PORT datad (1185:1185:1185) (1214:1214:1214)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~17) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (636:636:636)) + (PORT datab (580:580:580) (603:603:603)) + (PORT datac (2168:2168:2168) (2243:2243:2243)) + (PORT datad (533:533:533) (549:549:549)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1375:1375:1375) (1410:1410:1410)) + (PORT datab (757:757:757) (812:812:812)) + (PORT datac (2169:2169:2169) (2240:2240:2240)) + (PORT datad (1276:1276:1276) (1310:1310:1310)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (989:989:989) (1068:1068:1068)) + (PORT datab (1342:1342:1342) (1431:1431:1431)) + (PORT datac (728:728:728) (781:781:781)) + (PORT datad (915:915:915) (953:953:953)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~20) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (255:255:255)) + (PORT datab (236:236:236) (281:281:281)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~36) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (899:899:899)) + (PORT datab (777:777:777) (885:885:885)) + (PORT datac (628:628:628) (674:674:674)) + (PORT datad (707:707:707) (811:811:811)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~15) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (642:642:642)) + (PORT datab (744:744:744) (781:781:781)) + (PORT datac (1960:1960:1960) (2018:2018:2018)) + (PORT datad (808:808:808) (821:821:821)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~16) + (DELAY + (ABSOLUTE + (PORT dataa (748:748:748) (853:853:853)) + (PORT datab (779:779:779) (885:885:885)) + (PORT datac (754:754:754) (860:860:860)) + (PORT datad (1842:1842:1842) (1891:1891:1891)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~21) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (720:720:720)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (525:525:525) (536:536:536)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) + (DELAY + (ABSOLUTE + (PORT dataa (1156:1156:1156) (1178:1178:1178)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (809:809:809) (833:833:833)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1655:1655:1655) (1672:1672:1672)) + (PORT datab (1989:1989:1989) (2051:2051:2051)) + (PORT datac (877:877:877) (900:900:900)) + (PORT datad (1449:1449:1449) (1444:1444:1444)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) + (DELAY + (ABSOLUTE + (PORT datab (777:777:777) (881:881:881)) + (PORT datac (751:751:751) (853:853:853)) + (PORT datad (1014:1014:1014) (1034:1034:1034)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~34) + (DELAY + (ABSOLUTE + (PORT dataa (725:725:725) (827:827:827)) + (PORT datab (2350:2350:2350) (2475:2475:2475)) + (PORT datac (751:751:751) (853:853:853)) + (PORT datad (649:649:649) (694:694:694)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~22) + (DELAY + (ABSOLUTE + (PORT datab (1154:1154:1154) (1254:1254:1254)) + (PORT datac (908:908:908) (984:984:984)) + (PORT datad (695:695:695) (796:796:796)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~23) + (DELAY + (ABSOLUTE + (PORT dataa (2509:2509:2509) (2581:2581:2581)) + (PORT datab (930:930:930) (981:981:981)) + (PORT datac (1138:1138:1138) (1158:1158:1158)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~35) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (935:935:935)) + (PORT datab (776:776:776) (881:881:881)) + (PORT datac (751:751:751) (854:854:854)) + (PORT datad (563:563:563) (572:572:572)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~24) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (240:240:240)) + (PORT datab (213:213:213) (256:256:256)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (207:207:207) (237:237:237)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) + (DELAY + (ABSOLUTE + (PORT datab (390:390:390) (430:430:430)) + (PORT datad (887:887:887) (895:895:895)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) + (DELAY + (ABSOLUTE + (PORT dataa (1066:1066:1066) (1104:1104:1104)) + (PORT datab (452:452:452) (487:487:487)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (1994:1994:1994) (2001:2001:2001)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) + (DELAY + (ABSOLUTE + (PORT dataa (993:993:993) (1075:1075:1075)) + (PORT datab (1343:1343:1343) (1437:1437:1437)) + (PORT datac (2168:2168:2168) (2246:2246:2246)) + (PORT datad (914:914:914) (958:958:958)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (389:389:389)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1584:1584:1584) (1620:1620:1620)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (726:726:726)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (882:882:882) (905:905:905)) + (PORT datad (1416:1416:1416) (1450:1450:1450)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (1449:1449:1449) (1484:1484:1484)) + (PORT datac (344:344:344) (368:368:368)) + (PORT datad (215:215:215) (248:248:248)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~95) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (899:899:899)) + (PORT datab (2351:2351:2351) (2480:2480:2480)) + (PORT datac (628:628:628) (672:672:672)) + (PORT datad (671:671:671) (769:769:769)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (718:718:718)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (524:524:524) (535:535:535)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~27) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (257:257:257)) + (PORT datab (237:237:237) (282:282:282)) + (PORT datac (727:727:727) (782:782:782)) + (PORT datad (217:217:217) (251:251:251)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (439:439:439)) + (PORT datab (296:296:296) (390:390:390)) + (PORT datac (1137:1137:1137) (1168:1168:1168)) + (PORT datad (250:250:250) (323:323:323)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) + (DELAY + (ABSOLUTE + (PORT dataa (2200:2200:2200) (2281:2281:2281)) + (PORT datab (236:236:236) (278:278:278)) + (PORT datac (602:602:602) (659:659:659)) + (PORT datad (1039:1039:1039) (1034:1034:1034)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (1452:1452:1452) (1485:1485:1485)) + (PORT datac (1451:1451:1451) (1488:1488:1488)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) + (DELAY + (ABSOLUTE + (PORT dataa (580:580:580) (594:594:594)) + (PORT datab (550:550:550) (563:563:563)) + (PORT datac (1357:1357:1357) (1370:1370:1370)) + (PORT datad (647:647:647) (674:674:674)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (584:584:584)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (209:209:209) (241:241:241)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (634:634:634) (678:678:678)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (607:607:607) (648:648:648)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (902:902:902)) + (PORT datab (2019:2019:2019) (2038:2038:2038)) + (PORT datac (811:811:811) (824:824:824)) + (PORT datad (887:887:887) (895:895:895)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~26) + (DELAY + (ABSOLUTE + (PORT datab (217:217:217) (262:262:262)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (212:212:212) (244:244:244)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1970:1970:1970) (2029:2029:2029)) + (PORT datac (826:826:826) (890:890:890)) + (PORT datad (544:544:544) (549:549:549)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (415:415:415)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (608:608:608) (631:631:631)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (275:275:275)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~89) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (658:658:658)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datad (336:336:336) (360:360:360)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~90) + (DELAY + (ABSOLUTE + (PORT dataa (1211:1211:1211) (1241:1241:1241)) + (PORT datab (451:451:451) (487:487:487)) + (PORT datac (746:746:746) (800:800:800)) + (PORT datad (1929:1929:1929) (1986:1986:1986)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~91) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1218:1218:1218) (1238:1238:1238)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1992:1992:1992) (2003:2003:2003)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (957:957:957)) + (PORT datab (948:948:948) (988:988:988)) + (PORT datac (952:952:952) (1040:1040:1040)) + (PORT datad (1244:1244:1244) (1337:1337:1337)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (920:920:920)) + (PORT datab (555:555:555) (584:584:584)) + (PORT datac (2651:2651:2651) (2699:2699:2699)) + (PORT datad (325:325:325) (347:347:347)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~100) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1107:1107:1107)) + (PORT datab (787:787:787) (896:896:896)) + (PORT datac (722:722:722) (831:831:831)) + (PORT datad (1631:1631:1631) (1626:1626:1626)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~92) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (546:546:546) (547:547:547)) + (PORT datad (1991:1991:1991) (2002:2002:2002)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1291:1291:1291) (1360:1360:1360)) + (PORT datab (1487:1487:1487) (1548:1548:1548)) + (PORT datac (611:611:611) (675:675:675)) + (PORT datad (827:827:827) (876:876:876)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (906:906:906)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (1102:1102:1102) (1091:1091:1091)) + (PORT datad (362:362:362) (397:397:397)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~29) + (DELAY + (ABSOLUTE + (PORT dataa (2510:2510:2510) (2578:2578:2578)) + (PORT datab (968:968:968) (1013:1013:1013)) + (PORT datac (1329:1329:1329) (1335:1335:1335)) + (PORT datad (869:869:869) (880:880:880)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~30) + (DELAY + (ABSOLUTE + (PORT dataa (426:426:426) (476:476:476)) + (PORT datab (968:968:968) (1011:1011:1011)) + (PORT datac (1340:1340:1340) (1390:1390:1390)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~31) + (DELAY + (ABSOLUTE + (PORT dataa (426:426:426) (475:475:475)) + (PORT datab (896:896:896) (921:921:921)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~32) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (389:389:389)) + (PORT datab (388:388:388) (429:429:429)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (886:886:886) (895:895:895)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~93) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (1994:1994:1994) (2001:2001:2001)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) + (DELAY + (ABSOLUTE + (PORT datab (1398:1398:1398) (1449:1449:1449)) + (PORT datac (1373:1373:1373) (1416:1416:1416)) + (PORT datad (1070:1070:1070) (1118:1118:1118)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (990:990:990) (1026:1026:1026)) + (PORT ena (1147:1147:1147) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (990:990:990) (1026:1026:1026)) + (PORT ena (1248:1248:1248) (1262:1262:1262)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (664:664:664)) + (PORT datab (941:941:941) (1002:1002:1002)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (679:679:679) (694:694:694)) + (PORT ena (1243:1243:1243) (1273:1273:1273)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (448:448:448)) + (PORT datab (941:941:941) (971:971:971)) + (PORT datac (952:952:952) (1001:1001:1001)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (920:920:920)) + (PORT datab (889:889:889) (924:924:924)) + (PORT datac (807:807:807) (828:828:828)) + (PORT datad (558:558:558) (581:581:581)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1257:1257:1257) (1295:1295:1295)) + (PORT ena (1546:1546:1546) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1260:1260:1260) (1299:1299:1299)) + (PORT ena (1446:1446:1446) (1455:1455:1455)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1050:1050:1050)) + (PORT datab (965:965:965) (1007:1007:1007)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (978:978:978) (1023:1023:1023)) + (PORT ena (1475:1475:1475) (1479:1479:1479)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (637:637:637) (678:678:678)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1485:1485:1485) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (920:920:920) (979:979:979)) + (PORT datab (934:934:934) (981:981:981)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1132:1132:1132) (1209:1209:1209)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1492:1492:1492) (1562:1562:1562)) + (PORT datab (665:665:665) (715:715:715)) + (PORT datad (1640:1640:1640) (1755:1755:1755)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (631:631:631) (671:671:671)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1186:1186:1186) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1005:1005:1005) (1051:1051:1051)) + (PORT ena (1476:1476:1476) (1478:1478:1478)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (328:328:328)) + (PORT datab (957:957:957) (994:994:994)) + (PORT datad (880:880:880) (927:927:927)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1153:1153:1153) (1205:1205:1205)) + (PORT ena (1204:1204:1204) (1190:1190:1190)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT asdata (1497:1497:1497) (1521:1521:1521)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (686:686:686) (744:744:744)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datad (587:587:587) (604:604:604)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1256:1256:1256) (1290:1290:1290)) + (PORT ena (1213:1213:1213) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1257:1257:1257) (1292:1292:1292)) + (PORT ena (1163:1163:1163) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (708:708:708)) + (PORT datab (242:242:242) (324:324:324)) + (PORT datad (625:625:625) (661:661:661)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT asdata (1551:1551:1551) (1646:1646:1646)) + (PORT ena (1256:1256:1256) (1263:1263:1263)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (912:912:912)) + (PORT datab (1255:1255:1255) (1305:1305:1305)) + (PORT datad (635:635:635) (652:652:652)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (685:685:685)) + (PORT datab (803:803:803) (863:863:863)) + (PORT datac (602:602:602) (611:611:611)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (867:867:867)) + (PORT datab (1027:1027:1027) (1075:1075:1075)) + (PORT datac (339:339:339) (360:360:360)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1158:1158:1158) (1174:1174:1174)) + (PORT datab (1389:1389:1389) (1427:1427:1427)) + (PORT datac (932:932:932) (1001:1001:1001)) + (PORT datad (1353:1353:1353) (1389:1389:1389)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) + (DELAY + (ABSOLUTE + (PORT dataa (2598:2598:2598) (2655:2655:2655)) + (PORT datab (203:203:203) (244:244:244)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) + (DELAY + (ABSOLUTE + (PORT datac (1110:1110:1110) (1142:1142:1142)) + (PORT datad (1438:1438:1438) (1486:1486:1486)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (710:710:710)) + (PORT datab (940:940:940) (967:967:967)) + (PORT datac (1128:1128:1128) (1173:1173:1173)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1160:1160:1160) (1209:1209:1209)) + (PORT datac (912:912:912) (935:935:935)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1157:1157:1157) (1206:1206:1206)) + (PORT datab (943:943:943) (970:970:970)) + (PORT datac (1105:1105:1105) (1135:1135:1135)) + (PORT datad (1434:1434:1434) (1479:1479:1479)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (430:430:430) (493:493:493)) + (PORT datac (568:568:568) (586:586:586)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (690:690:690) (717:717:717)) + (PORT ena (1147:1147:1147) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (690:690:690) (717:717:717)) + (PORT ena (1248:1248:1248) (1262:1262:1262)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (665:665:665)) + (PORT datab (946:946:946) (1002:1002:1002)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1265:1265:1265) (1314:1314:1314)) + (PORT ena (1426:1426:1426) (1409:1409:1409)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1265:1265:1265) (1316:1316:1316)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (312:312:312)) + (PORT datab (1085:1085:1085) (1113:1113:1113)) + (PORT datad (357:357:357) (417:417:417)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (919:919:919) (943:943:943)) + (PORT ena (923:923:923) (907:907:907)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (919:919:919) (943:943:943)) + (PORT ena (984:984:984) (983:983:983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (457:457:457)) + (PORT datab (240:240:240) (322:322:322)) + (PORT datad (417:417:417) (444:444:444)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1412:1412:1412) (1427:1427:1427)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1288:1288:1288) (1376:1376:1376)) + (PORT datab (1003:1003:1003) (1047:1047:1047)) + (PORT datad (892:892:892) (942:942:942)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1471:1471:1471) (1507:1507:1507)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1489:1489:1489) (1614:1614:1614)) + (PORT datab (1521:1521:1521) (1656:1656:1656)) + (PORT datac (2142:2142:2142) (2142:2142:2142)) + (PORT datad (646:646:646) (662:662:662)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (284:284:284)) + (PORT datab (736:736:736) (799:799:799)) + (PORT datac (897:897:897) (948:948:948)) + (PORT datad (1169:1169:1169) (1226:1226:1226)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (952:952:952)) + (PORT datab (644:644:644) (665:665:665)) + (PORT datac (1286:1286:1286) (1331:1331:1331)) + (PORT datad (335:335:335) (355:355:355)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT datab (829:829:829) (884:884:884)) + (PORT datac (710:710:710) (803:803:803)) + (PORT datad (644:644:644) (666:666:666)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (942:942:942)) + (PORT datab (1388:1388:1388) (1430:1430:1430)) + (PORT datac (205:205:205) (241:241:241)) + (PORT datad (172:172:172) (196:196:196)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (207:207:207) (245:245:245)) + (PORT datad (1277:1277:1277) (1328:1328:1328)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1277:1277:1277)) + (PORT datac (2040:2040:2040) (2164:2164:2164)) + (PORT datad (1304:1304:1304) (1444:1444:1444)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~10) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (693:693:693)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (546:546:546) (555:555:555)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1942:1942:1942) (2136:2136:2136)) + (PORT datab (1507:1507:1507) (1522:1522:1522)) + (PORT datac (1089:1089:1089) (1120:1120:1120)) + (PORT datad (1570:1570:1570) (1713:1713:1713)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1803:1803:1803) (1900:1900:1900)) + (PORT datab (1596:1596:1596) (1748:1748:1748)) + (PORT datac (3144:3144:3144) (3233:3233:3233)) + (PORT datad (1902:1902:1902) (2090:2090:2090)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1474:1474:1474) (1525:1525:1525)) + (PORT datab (1976:1976:1976) (2075:2075:2075)) + (PORT datac (1520:1520:1520) (1551:1551:1551)) + (PORT datad (1771:1771:1771) (1858:1858:1858)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~11) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (197:197:197) (234:234:234)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (1561:1561:1561) (1627:1627:1627)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~12) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (643:643:643)) + (PORT datab (602:602:602) (655:655:655)) + (PORT datac (616:616:616) (660:660:660)) + (PORT datad (343:343:343) (363:363:363)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (288:288:288)) + (PORT datab (665:665:665) (693:693:693)) + (PORT datac (1025:1025:1025) (1030:1030:1030)) + (PORT datad (584:584:584) (607:607:607)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) + (DELAY + (ABSOLUTE + (PORT dataa (957:957:957) (975:975:975)) + (PORT datab (657:657:657) (694:694:694)) + (PORT datac (1759:1759:1759) (1816:1816:1816)) + (PORT datad (562:562:562) (580:580:580)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (638:638:638)) + (PORT datab (656:656:656) (696:696:696)) + (PORT datac (178:178:178) (217:217:217)) + (PORT datad (943:943:943) (992:992:992)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) + (DELAY + (ABSOLUTE + (PORT datac (555:555:555) (591:591:591)) + (PORT datad (1085:1085:1085) (1092:1092:1092)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (2000:2000:2000) (2156:2156:2156)) + (PORT datab (1422:1422:1422) (1488:1488:1488)) + (PORT datad (1323:1323:1323) (1495:1495:1495)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (1021:1021:1021)) + (PORT datab (993:993:993) (1042:1042:1042)) + (PORT datac (1464:1464:1464) (1524:1524:1524)) + (PORT datad (1227:1227:1227) (1313:1313:1313)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (253:253:253)) + (PORT datab (965:965:965) (1025:1025:1025)) + (PORT datac (912:912:912) (977:977:977)) + (PORT datad (958:958:958) (998:998:998)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1856:1856:1856) (1890:1890:1890)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (584:584:584) (639:639:639)) + (PORT datad (1583:1583:1583) (1570:1570:1570)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1386:1386:1386) (1474:1474:1474)) + (PORT datab (1349:1349:1349) (1521:1521:1521)) + (PORT datac (1103:1103:1103) (1126:1126:1126)) + (PORT datad (1358:1358:1358) (1519:1519:1519)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (268:268:268)) + (PORT datab (642:642:642) (688:688:688)) + (PORT datad (333:333:333) (358:358:358)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S) + (DELAY + (ABSOLUTE + (PORT dataa (1090:1090:1090) (1128:1128:1128)) + (PORT datab (820:820:820) (850:850:850)) + (PORT datac (558:558:558) (591:591:591)) + (PORT datad (546:546:546) (551:551:551)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal73\~2) + (DELAY + (ABSOLUTE + (PORT dataa (997:997:997) (1074:1074:1074)) + (PORT datab (881:881:881) (904:904:904)) + (PORT datac (1049:1049:1049) (1138:1138:1138)) + (PORT datad (1271:1271:1271) (1360:1360:1360)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (734:734:734)) + (PORT datab (924:924:924) (980:980:980)) + (PORT datac (1471:1471:1471) (1536:1536:1536)) + (PORT datad (1149:1149:1149) (1181:1181:1181)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R) + (DELAY + (ABSOLUTE + (PORT dataa (1111:1111:1111) (1132:1132:1132)) + (PORT datab (360:360:360) (393:393:393)) + (PORT datac (555:555:555) (590:590:590)) + (PORT datad (1061:1061:1061) (1074:1074:1074)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) + (DELAY + (ABSOLUTE + (PORT datab (226:226:226) (267:267:267)) + (PORT datac (601:601:601) (626:626:626)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (266:266:266)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (861:861:861) (894:894:894)) + (PORT datad (593:593:593) (607:607:607)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (694:694:694)) + (PORT datab (1536:1536:1536) (1599:1599:1599)) + (PORT datac (961:961:961) (990:990:990)) + (PORT datad (1384:1384:1384) (1458:1458:1458)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (893:893:893)) + (PORT datab (563:563:563) (581:581:581)) + (PORT datac (801:801:801) (807:807:807)) + (PORT datad (831:831:831) (859:859:859)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (340:340:340)) + (PORT datab (1770:1770:1770) (1810:1810:1810)) + (PORT datac (255:255:255) (312:312:312)) + (PORT datad (1200:1200:1200) (1271:1271:1271)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1728:1728:1728) (1834:1834:1834)) + (PORT datab (887:887:887) (890:890:890)) + (PORT datac (859:859:859) (902:902:902)) + (PORT datad (1842:1842:1842) (2007:2007:2007)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1729:1729:1729) (1835:1835:1835)) + (PORT datab (1714:1714:1714) (1825:1825:1825)) + (PORT datac (859:859:859) (903:903:903)) + (PORT datad (2100:2100:2100) (2296:2296:2296)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (250:250:250)) + (PORT datab (221:221:221) (269:269:269)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (201:201:201) (229:229:229)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (719:719:719) (745:745:745)) + (PORT ena (1475:1475:1475) (1479:1479:1479)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (718:718:718) (747:747:747)) + (PORT ena (1485:1485:1485) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (982:982:982)) + (PORT datab (937:937:937) (984:984:984)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1270:1270:1270) (1302:1302:1302)) + (PORT ena (1546:1546:1546) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1271:1271:1271) (1304:1304:1304)) + (PORT ena (1446:1446:1446) (1455:1455:1455)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (998:998:998) (1056:1056:1056)) + (PORT datab (968:968:968) (1014:1014:1014)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (999:999:999) (1040:1040:1040)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1487:1487:1487) (1562:1562:1562)) + (PORT datab (657:657:657) (709:709:709)) + (PORT datad (1632:1632:1632) (1751:1751:1751)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT asdata (1772:1772:1772) (1847:1847:1847)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1916:1916:1916) (1967:1967:1967)) + (PORT ena (1196:1196:1196) (1165:1165:1165)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (700:700:700)) + (PORT datab (498:498:498) (553:553:553)) + (PORT datad (627:627:627) (659:659:659)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT asdata (1475:1475:1475) (1524:1524:1524)) + (PORT ena (1256:1256:1256) (1263:1263:1263)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (921:921:921)) + (PORT datab (672:672:672) (692:692:692)) + (PORT datad (1219:1219:1219) (1269:1269:1269)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1476:1476:1476) (1478:1478:1478)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (913:913:913) (927:927:927)) + (PORT ena (1186:1186:1186) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (972:972:972)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (917:917:917) (961:961:961)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1003:1003:1003) (1054:1054:1054)) + (PORT ena (1163:1163:1163) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1001:1001:1001) (1054:1054:1054)) + (PORT ena (1213:1213:1213) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (706:706:706)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datad (625:625:625) (656:656:656)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (666:666:666)) + (PORT datab (831:831:831) (898:898:898)) + (PORT datac (578:578:578) (588:588:588)) + (PORT datad (591:591:591) (603:603:603)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (843:843:843)) + (PORT datab (1032:1032:1032) (1063:1063:1063)) + (PORT datac (813:813:813) (859:859:859)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (1040:1040:1040)) + (PORT datac (960:960:960) (1021:1021:1021)) + (PORT datad (1216:1216:1216) (1283:1283:1283)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1164:1164:1164) (1183:1183:1183)) + (PORT ena (1164:1164:1164) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (965:965:965) (1036:1036:1036)) + (PORT datab (992:992:992) (1052:1052:1052)) + (PORT datac (1247:1247:1247) (1332:1332:1332)) + (PORT datad (1118:1118:1118) (1138:1138:1138)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1491:1491:1491) (1578:1578:1578)) + (PORT datab (588:588:588) (620:620:620)) + (PORT datad (574:574:574) (600:600:600)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (DELAY + (ABSOLUTE + (PORT datab (979:979:979) (1030:1030:1030)) + (PORT datac (935:935:935) (999:999:999)) + (PORT datad (1216:1216:1216) (1283:1283:1283)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1185:1185:1185) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) + (DELAY + (ABSOLUTE + (PORT datab (973:973:973) (1024:1024:1024)) + (PORT datac (931:931:931) (993:993:993)) + (PORT datad (1213:1213:1213) (1277:1277:1277)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (243:243:243) (325:325:325)) + (PORT datad (565:565:565) (592:592:592)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1185:1185:1185) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1019:1019:1019) (1071:1071:1071)) + (PORT ena (1546:1546:1546) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1018:1018:1018) (1071:1071:1071)) + (PORT ena (1446:1446:1446) (1455:1455:1455)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (997:997:997) (1051:1051:1051)) + (PORT datab (965:965:965) (1008:1008:1008)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (914:914:914) (930:930:930)) + (PORT ena (1475:1475:1475) (1479:1479:1479)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (914:914:914) (930:930:930)) + (PORT ena (1485:1485:1485) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (978:978:978)) + (PORT datab (931:931:931) (977:977:977)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1218:1218:1218) (1256:1256:1256)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1486:1486:1486) (1558:1558:1558)) + (PORT datab (659:659:659) (703:703:703)) + (PORT datad (1630:1630:1630) (1743:1743:1743)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1214:1214:1214) (1253:1253:1253)) + (PORT ena (1163:1163:1163) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1211:1211:1211) (1250:1250:1250)) + (PORT ena (1213:1213:1213) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (712:712:712)) + (PORT datab (242:242:242) (325:325:325)) + (PORT datad (623:623:623) (658:658:658)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (697:697:697) (721:721:721)) + (PORT ena (1186:1186:1186) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1476:1476:1476) (1478:1478:1478)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (968:968:968)) + (PORT datab (959:959:959) (996:996:996)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT asdata (1223:1223:1223) (1248:1248:1248)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1227:1227:1227) (1258:1258:1258)) + (PORT ena (1196:1196:1196) (1165:1165:1165)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (431:431:431) (520:520:520)) + (PORT datab (498:498:498) (554:554:554)) + (PORT datad (627:627:627) (659:659:659)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1229:1229:1229) (1261:1261:1261)) + (PORT ena (1256:1256:1256) (1255:1255:1255)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (984:984:984) (1035:1035:1035)) + (PORT datab (1291:1291:1291) (1330:1330:1330)) + (PORT datad (1490:1490:1490) (1545:1545:1545)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (369:369:369)) + (PORT datab (654:654:654) (670:670:670)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (382:382:382)) + (PORT datab (615:615:615) (642:642:642)) + (PORT datac (632:632:632) (658:658:658)) + (PORT datad (613:613:613) (637:637:637)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (847:847:847)) + (PORT datab (405:405:405) (445:445:445)) + (PORT datac (1349:1349:1349) (1373:1373:1373)) + (PORT datad (593:593:593) (611:611:611)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (895:895:895) (905:905:905)) + (PORT ena (1164:1164:1164) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (645:645:645)) + (PORT datab (1250:1250:1250) (1323:1323:1323)) + (PORT datad (563:563:563) (584:584:584)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (327:327:327)) + (PORT datab (589:589:589) (623:623:623)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[8\]) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (405:405:405)) + (PORT datac (883:883:883) (935:935:935)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (658:658:658)) + (PORT datab (215:215:215) (260:260:260)) + (PORT datac (179:179:179) (218:218:218)) + (PORT datad (603:603:603) (621:621:621)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (236:236:236) (288:288:288)) + (PORT datab (680:680:680) (738:738:738)) + (PORT datac (1196:1196:1196) (1238:1238:1238)) + (PORT datad (1772:1772:1772) (1834:1834:1834)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (860:860:860)) + (PORT datab (1104:1104:1104) (1147:1147:1147)) + (PORT datac (1002:1002:1002) (1071:1071:1071)) + (PORT datad (847:847:847) (873:873:873)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (941:941:941)) + (PORT datab (916:916:916) (948:948:948)) + (PORT datac (338:338:338) (357:357:357)) + (PORT datad (854:854:854) (893:893:893)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (422:422:422) (453:453:453)) + (PORT datab (1472:1472:1472) (1490:1490:1490)) + (PORT datac (1016:1016:1016) (1077:1077:1077)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (374:374:374)) + (PORT datab (663:663:663) (676:676:676)) + (PORT datac (551:551:551) (566:566:566)) + (PORT datad (616:616:616) (633:633:633)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1147:1147:1147) (1215:1215:1215)) + (PORT datab (1209:1209:1209) (1278:1278:1278)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (827:827:827) (839:839:839)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (1783:1783:1783) (1814:1814:1814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1222:1222:1222) (1224:1224:1224)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (900:900:900) (908:908:908)) + (PORT ena (1426:1426:1426) (1409:1409:1409)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (900:900:900) (911:911:911)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (246:246:246) (318:318:318)) + (PORT datab (1081:1081:1081) (1113:1113:1113)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1215:1215:1215) (1256:1256:1256)) + (PORT ena (984:984:984) (983:983:983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1217:1217:1217) (1254:1254:1254)) + (PORT ena (923:923:923) (907:907:907)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (462:462:462)) + (PORT datab (452:452:452) (481:481:481)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (621:621:621) (651:651:651)) + (PORT datac (1318:1318:1318) (1334:1334:1334)) + (PORT datad (1133:1133:1133) (1166:1166:1166)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (596:596:596)) + (PORT datab (1148:1148:1148) (1164:1164:1164)) + (PORT datac (1083:1083:1083) (1082:1082:1082)) + (PORT datad (819:819:819) (843:843:843)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (835:835:835)) + (PORT datab (390:390:390) (417:417:417)) + (PORT datac (1069:1069:1069) (1074:1074:1074)) + (PORT datad (1075:1075:1075) (1109:1109:1109)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (685:685:685)) + (PORT datab (1345:1345:1345) (1363:1363:1363)) + (PORT datac (653:653:653) (717:717:717)) + (PORT datad (1140:1140:1140) (1170:1170:1170)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (952:952:952)) + (PORT datab (882:882:882) (913:913:913)) + (PORT datac (1082:1082:1082) (1120:1120:1120)) + (PORT datad (836:836:836) (859:859:859)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (911:911:911)) + (PORT datab (599:599:599) (619:619:619)) + (PORT datac (802:802:802) (820:820:820)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (952:952:952)) + (PORT datab (903:903:903) (934:934:934)) + (PORT datac (806:806:806) (826:826:826)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (954:954:954)) + (PORT datab (891:891:891) (915:915:915)) + (PORT datac (862:862:862) (932:932:932)) + (PORT datad (1058:1058:1058) (1077:1077:1077)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT asdata (1695:1695:1695) (1745:1745:1745)) + (PORT ena (961:961:961) (970:970:970)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1005:1005:1005) (1047:1047:1047)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (841:841:841) (847:847:847)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (710:710:710)) + (PORT datab (244:244:244) (289:289:289)) + (PORT datad (547:547:547) (596:596:596)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1690:1690:1690) (1722:1722:1722)) + (PORT ena (1168:1168:1168) (1161:1161:1161)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT asdata (1694:1694:1694) (1745:1745:1745)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1687:1687:1687) (1719:1719:1719)) + (PORT ena (1243:1243:1243) (1273:1273:1273)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (759:759:759)) + (PORT datab (676:676:676) (718:718:718)) + (PORT datad (629:629:629) (658:658:658)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (411:411:411) (458:458:458)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1445:1445:1445) (1462:1462:1462)) + (PORT ena (1147:1147:1147) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1445:1445:1445) (1465:1465:1465)) + (PORT ena (1248:1248:1248) (1262:1262:1262)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (661:661:661)) + (PORT datab (941:941:941) (1000:1000:1000)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (622:622:622)) + (PORT datab (801:801:801) (823:823:823)) + (PORT datac (647:647:647) (685:685:685)) + (PORT datad (828:828:828) (870:870:870)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (704:704:704)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datad (622:622:622) (661:661:661)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (899:899:899)) + (PORT datab (353:353:353) (392:392:392)) + (PORT datac (1132:1132:1132) (1184:1184:1184)) + (PORT datad (670:670:670) (701:701:701)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (672:672:672) (695:695:695)) + (PORT ena (1237:1237:1237) (1220:1220:1220)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1469:1469:1469) (1520:1520:1520)) + (PORT datab (820:820:820) (835:835:835)) + (PORT datad (653:653:653) (675:675:675)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datad (607:607:607) (630:630:630)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) + (DELAY + (ABSOLUTE + (PORT datab (704:704:704) (782:782:782)) + (PORT datad (796:796:796) (798:798:798)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (1209:1209:1209) (1265:1265:1265)) + (PORT datad (217:217:217) (253:253:253)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (1104:1104:1104) (1132:1132:1132)) + (PORT datad (634:634:634) (652:652:652)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1592:1592:1592) (1568:1568:1568)) + (PORT ena (2023:2023:2023) (2039:2039:2039)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1245:1245:1245) (1250:1250:1250)) + (PORT datab (904:904:904) (935:935:935)) + (PORT datac (384:384:384) (452:452:452)) + (PORT datad (911:911:911) (971:971:971)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) + (DELAY + (ABSOLUTE + (PORT datac (390:390:390) (464:464:464)) + (PORT datad (189:189:189) (222:222:222)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1543:1543:1543) (1611:1611:1611)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (432:432:432) (479:479:479)) + (PORT datad (319:319:319) (341:341:341)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[9\]) + (DELAY + (ABSOLUTE + (PORT datac (880:880:880) (934:934:934)) + (PORT datad (313:313:313) (333:333:333)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (1783:1783:1783) (1814:1814:1814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (892:892:892) (909:909:909)) + (PORT ena (1203:1203:1203) (1189:1189:1189)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1387:1387:1387) (1394:1394:1394)) + (PORT ena (1256:1256:1256) (1255:1255:1255)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (983:983:983) (1035:1035:1035)) + (PORT datab (1288:1288:1288) (1327:1327:1327)) + (PORT datad (831:831:831) (901:901:901)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1476:1476:1476) (1478:1478:1478)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1200:1200:1200) (1214:1214:1214)) + (PORT ena (1186:1186:1186) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (330:330:330)) + (PORT datab (957:957:957) (998:998:998)) + (PORT datad (879:879:879) (924:924:924)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1245:1245:1245) (1259:1259:1259)) + (PORT ena (1163:1163:1163) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1245:1245:1245) (1259:1259:1259)) + (PORT ena (1213:1213:1213) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (706:706:706)) + (PORT datab (240:240:240) (322:322:322)) + (PORT datad (621:621:621) (655:655:655)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT asdata (1206:1206:1206) (1211:1211:1211)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1386:1386:1386) (1392:1392:1392)) + (PORT ena (1196:1196:1196) (1165:1165:1165)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (423:423:423) (513:513:513)) + (PORT datab (498:498:498) (557:557:557)) + (PORT datad (622:622:622) (662:662:662)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (674:674:674)) + (PORT datab (845:845:845) (862:862:862)) + (PORT datac (584:584:584) (597:597:597)) + (PORT datad (575:575:575) (585:585:585)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1426:1426:1426) (1436:1436:1436)) + (PORT ena (1546:1546:1546) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1076:1076:1076) (1088:1088:1088)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1446:1446:1446) (1455:1455:1455)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (998:998:998) (1056:1056:1056)) + (PORT datab (964:964:964) (1012:1012:1012)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1210:1210:1210) (1217:1217:1217)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1484:1484:1484) (1556:1556:1556)) + (PORT datab (656:656:656) (706:706:706)) + (PORT datad (1631:1631:1631) (1740:1740:1740)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (709:709:709) (736:736:736)) + (PORT ena (1485:1485:1485) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (709:709:709) (736:736:736)) + (PORT ena (1475:1475:1475) (1479:1479:1479)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (977:977:977)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datad (899:899:899) (938:938:938)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (672:672:672)) + (PORT datab (674:674:674) (694:694:694)) + (PORT datac (855:855:855) (905:905:905)) + (PORT datad (319:319:319) (339:339:339)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (579:579:579)) + (PORT datab (400:400:400) (438:438:438)) + (PORT datac (1346:1346:1346) (1369:1369:1369)) + (PORT datad (569:569:569) (587:587:587)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (694:694:694)) + (PORT datab (621:621:621) (667:667:667)) + (PORT datad (582:582:582) (592:592:592)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1185:1185:1185) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (403:403:403) (482:482:482)) + (PORT datad (585:585:585) (610:610:610)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (423:423:423) (508:508:508)) + (PORT datab (905:905:905) (932:932:932)) + (PORT datac (415:415:415) (484:484:484)) + (PORT datad (188:188:188) (218:218:218)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1540:1540:1540) (1609:1609:1609)) + (PORT datab (380:380:380) (414:414:414)) + (PORT datac (435:435:435) (484:484:484)) + (PORT datad (359:359:359) (378:378:378)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[10\]) + (DELAY + (ABSOLUTE + (PORT datac (883:883:883) (940:940:940)) + (PORT datad (333:333:333) (350:350:350)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (1783:1783:1783) (1814:1814:1814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (421:421:421) (503:503:503)) + (PORT datab (904:904:904) (930:930:930)) + (PORT datac (414:414:414) (483:483:483)) + (PORT datad (189:189:189) (222:222:222)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (2165:2165:2165) (2195:2195:2195)) + (PORT ena (1475:1475:1475) (1479:1479:1479)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (2167:2167:2167) (2197:2197:2197)) + (PORT ena (1485:1485:1485) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (982:982:982)) + (PORT datab (932:932:932) (982:982:982)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1965:1965:1965) (2001:2001:2001)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1487:1487:1487) (1563:1563:1563)) + (PORT datab (662:662:662) (714:714:714)) + (PORT datad (1637:1637:1637) (1748:1748:1748)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (959:959:959) (984:984:984)) + (PORT ena (1546:1546:1546) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (961:961:961) (982:982:982)) + (PORT ena (1446:1446:1446) (1455:1455:1455)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1058:1058:1058)) + (PORT datab (964:964:964) (1012:1012:1012)) + (PORT datad (353:353:353) (413:413:413)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1767:1767:1767) (1800:1800:1800)) + (PORT ena (1163:1163:1163) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1768:1768:1768) (1802:1802:1802)) + (PORT ena (1213:1213:1213) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (711:711:711)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (622:622:622) (656:656:656)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT asdata (1910:1910:1910) (1926:1926:1926)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1990:1990:1990) (2006:2006:2006)) + (PORT ena (1196:1196:1196) (1165:1165:1165)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (426:426:426) (514:514:514)) + (PORT datab (497:497:497) (558:558:558)) + (PORT datad (621:621:621) (655:655:655)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1990:1990:1990) (2008:2008:2008)) + (PORT ena (1256:1256:1256) (1255:1255:1255)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1099:1099:1099) (1111:1111:1111)) + (PORT datab (882:882:882) (895:895:895)) + (PORT datac (824:824:824) (834:834:834)) + (PORT datad (1128:1128:1128) (1146:1146:1146)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (715:715:715)) + (PORT datab (1096:1096:1096) (1104:1104:1104)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (950:950:950) (981:981:981)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (982:982:982) (1034:1034:1034)) + (PORT datab (1288:1288:1288) (1327:1327:1327)) + (PORT datad (844:844:844) (907:907:907)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1476:1476:1476) (1478:1478:1478)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (2137:2137:2137) (2157:2157:2157)) + (PORT ena (1186:1186:1186) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (327:327:327)) + (PORT datab (957:957:957) (993:993:993)) + (PORT datad (879:879:879) (921:921:921)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (701:701:701)) + (PORT datab (651:651:651) (704:704:704)) + (PORT datac (614:614:614) (661:661:661)) + (PORT datad (632:632:632) (653:653:653)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (636:636:636)) + (PORT datab (654:654:654) (706:706:706)) + (PORT datac (844:844:844) (895:895:895)) + (PORT datad (172:172:172) (196:196:196)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1377:1377:1377) (1408:1408:1408)) + (PORT datab (643:643:643) (692:692:692)) + (PORT datac (543:543:543) (567:567:567)) + (PORT datad (373:373:373) (401:401:401)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1137:1137:1137) (1157:1157:1157)) + (PORT ena (1164:1164:1164) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1624:1624:1624) (1648:1648:1648)) + (PORT datab (588:588:588) (621:621:621)) + (PORT datad (575:575:575) (600:600:600)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1185:1185:1185) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (215:215:215) (292:292:292)) + (PORT datad (565:565:565) (592:592:592)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (589:589:589)) + (PORT datab (711:711:711) (747:747:747)) + (PORT datac (381:381:381) (458:458:458)) + (PORT datad (623:623:623) (682:682:682)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (475:475:475) (521:521:521)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (519:519:519) (550:550:550)) + (PORT datad (1502:1502:1502) (1569:1569:1569)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[12\]) + (DELAY + (ABSOLUTE + (PORT datab (903:903:903) (949:949:949)) + (PORT datac (795:795:795) (815:815:815)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1559:1559:1559)) + (PORT ena (1762:1762:1762) (1780:1780:1780)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (591:591:591)) + (PORT datab (712:712:712) (749:749:749)) + (PORT datac (380:380:380) (454:454:454)) + (PORT datad (624:624:624) (682:682:682)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (427:427:427) (508:508:508)) + (PORT datad (187:187:187) (219:219:219)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1185:1185:1185) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (963:963:963) (1022:1022:1022)) + (PORT ena (1546:1546:1546) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (962:962:962) (1021:1021:1021)) + (PORT ena (1446:1446:1446) (1455:1455:1455)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (1000:1000:1000) (1057:1057:1057)) + (PORT datab (969:969:969) (1008:1008:1008)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (678:678:678) (714:714:714)) + (PORT ena (1475:1475:1475) (1479:1479:1479)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (678:678:678) (714:714:714)) + (PORT ena (1485:1485:1485) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (982:982:982)) + (PORT datab (937:937:937) (981:981:981)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (893:893:893) (927:927:927)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1710:1710:1710) (1763:1763:1763)) + (PORT ena (1196:1196:1196) (1165:1165:1165)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (700:700:700)) + (PORT datab (501:501:501) (558:558:558)) + (PORT datad (620:620:620) (655:655:655)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1710:1710:1710) (1761:1761:1761)) + (PORT ena (1256:1256:1256) (1255:1255:1255)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1133:1133:1133) (1144:1144:1144)) + (PORT datab (705:705:705) (763:763:763)) + (PORT datac (1078:1078:1078) (1114:1114:1114)) + (PORT datad (188:188:188) (223:223:223)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1291:1291:1291)) + (PORT datab (808:808:808) (845:845:845)) + (PORT datac (818:818:818) (868:868:868)) + (PORT datad (804:804:804) (813:813:813)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1247:1247:1247) (1330:1330:1330)) + (PORT datab (985:985:985) (1056:1056:1056)) + (PORT datac (647:647:647) (686:686:686)) + (PORT datad (1360:1360:1360) (1453:1453:1453)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (388:388:388)) + (PORT datab (889:889:889) (946:946:946)) + (PORT datac (612:612:612) (646:646:646)) + (PORT datad (933:933:933) (987:987:987)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (955:955:955) (970:970:970)) + (PORT datab (287:287:287) (346:346:346)) + (PORT datad (853:853:853) (856:856:856)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) + (DELAY + (ABSOLUTE + (PORT datab (285:285:285) (345:345:345)) + (PORT datad (854:854:854) (856:856:856)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) + (DELAY + (ABSOLUTE + (PORT dataa (2000:2000:2000) (2162:2162:2162)) + (PORT datac (1090:1090:1090) (1122:1122:1122)) + (PORT datad (1323:1323:1323) (1497:1497:1497)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (967:967:967)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (888:888:888) (937:937:937)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datac (698:698:698) (765:765:765)) + (PORT datad (855:855:855) (908:908:908)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (224:224:224) (265:265:265)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1323:1323:1323) (1378:1378:1378)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1541:1541:1541) (1629:1629:1629)) + (PORT datab (1591:1591:1591) (1670:1670:1670)) + (PORT datac (857:857:857) (918:918:918)) + (PORT datad (398:398:398) (467:467:467)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (445:445:445) (507:507:507)) + (PORT datab (587:587:587) (606:606:606)) + (PORT datac (849:849:849) (909:909:909)) + (PORT datad (239:239:239) (282:282:282)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (662:662:662) (679:679:679)) + (PORT ena (1474:1474:1474) (1475:1475:1475)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (663:663:663)) + (PORT datab (1117:1117:1117) (1151:1151:1151)) + (PORT datad (847:847:847) (870:870:870)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (662:662:662)) + (PORT datab (1316:1316:1316) (1369:1369:1369)) + (PORT datac (209:209:209) (247:247:247)) + (PORT datad (841:841:841) (848:848:848)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datac (252:252:252) (311:311:311)) + (PORT datad (347:347:347) (371:371:371)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (419:419:419)) + (PORT datab (1011:1011:1011) (1072:1072:1072)) + (PORT datac (1687:1687:1687) (1750:1750:1750)) + (PORT datad (1175:1175:1175) (1233:1233:1233)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (586:586:586) (607:607:607)) + (PORT datac (918:918:918) (934:934:934)) + (PORT datad (852:852:852) (859:859:859)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) + (DELAY + (ABSOLUTE + (PORT datab (593:593:593) (612:612:612)) + (PORT datac (250:250:250) (307:307:307)) + (PORT datad (858:858:858) (860:860:860)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (921:921:921)) + (PORT datab (1005:1005:1005) (1064:1064:1064)) + (PORT datac (1691:1691:1691) (1755:1755:1755)) + (PORT datad (1168:1168:1168) (1225:1225:1225)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (957:957:957) (1024:1024:1024)) + (PORT datab (1075:1075:1075) (1139:1139:1139)) + (PORT datac (867:867:867) (925:925:925)) + (PORT datad (646:646:646) (678:678:678)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (731:731:731)) + (PORT datab (660:660:660) (692:692:692)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (913:913:913) (955:955:955)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (725:725:725)) + (PORT datab (663:663:663) (713:713:713)) + (PORT datac (627:627:627) (659:659:659)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1454:1454:1454) (1593:1593:1593)) + (PORT datab (927:927:927) (972:972:972)) + (PORT datac (587:587:587) (604:604:604)) + (PORT datad (1544:1544:1544) (1686:1686:1686)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (951:951:951)) + (PORT datab (989:989:989) (1033:1033:1033)) + (PORT datac (1425:1425:1425) (1436:1436:1436)) + (PORT datad (651:651:651) (670:670:670)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1259:1259:1259) (1306:1306:1306)) + (PORT datab (621:621:621) (668:668:668)) + (PORT datac (1465:1465:1465) (1520:1520:1520)) + (PORT datad (628:628:628) (636:636:636)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nop3pla68M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1184:1184:1184) (1281:1281:1281)) + (PORT datab (1244:1244:1244) (1294:1294:1294)) + (PORT datac (877:877:877) (941:941:941)) + (PORT datad (194:194:194) (218:218:218)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1260:1260:1260) (1306:1306:1306)) + (PORT datab (1263:1263:1263) (1349:1349:1349)) + (PORT datac (2128:2128:2128) (2214:2214:2214)) + (PORT datad (1440:1440:1440) (1511:1511:1511)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (408:408:408)) + (PORT datab (654:654:654) (669:669:669)) + (PORT datac (357:357:357) (377:377:377)) + (PORT datad (316:316:316) (335:335:335)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (178:178:178) (216:216:216)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (392:392:392)) + (PORT datab (337:337:337) (369:369:369)) + (PORT datac (870:870:870) (876:876:876)) + (PORT datad (609:609:609) (634:634:634)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (248:248:248) (293:293:293)) + (PORT datab (893:893:893) (901:901:901)) + (PORT datac (366:366:366) (393:393:393)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (998:998:998)) + (PORT datab (218:218:218) (255:255:255)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (610:610:610) (646:646:646)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1366:1366:1366) (1381:1381:1381)) + (PORT datab (674:674:674) (719:719:719)) + (PORT datac (640:640:640) (688:688:688)) + (PORT datad (913:913:913) (955:955:955)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~7) + (DELAY + (ABSOLUTE + (PORT datac (625:625:625) (661:661:661)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (699:699:699)) + (PORT datab (247:247:247) (288:288:288)) + (PORT datac (828:828:828) (858:858:858)) + (PORT datad (843:843:843) (860:860:860)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (421:421:421) (508:508:508)) + (PORT datab (867:867:867) (892:892:892)) + (PORT datac (604:604:604) (651:651:651)) + (PORT datad (566:566:566) (585:585:585)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1180:1180:1180) (1252:1252:1252)) + (PORT datab (574:574:574) (587:587:587)) + (PORT datac (861:861:861) (886:886:886)) + (PORT datad (1797:1797:1797) (1884:1884:1884)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1183:1183:1183) (1255:1255:1255)) + (PORT datab (572:572:572) (588:588:588)) + (PORT datac (858:858:858) (886:886:886)) + (PORT datad (1798:1798:1798) (1887:1887:1887)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (298:298:298)) + (PORT datab (554:554:554) (571:571:571)) + (PORT datac (228:228:228) (266:266:266)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (265:265:265)) + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (214:214:214) (259:259:259)) + (PORT datad (204:204:204) (235:235:235)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (274:274:274)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT datab (825:825:825) (834:834:834)) + (PORT datac (556:556:556) (572:572:572)) + (PORT datad (330:330:330) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT asdata (690:690:690) (711:711:711)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1043:1043:1043) (1079:1079:1079)) + (PORT datab (664:664:664) (707:707:707)) + (PORT datac (633:633:633) (680:680:680)) + (PORT datad (584:584:584) (611:611:611)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datac (625:625:625) (657:657:657)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (992:992:992) (1100:1100:1100)) + (PORT datab (1591:1591:1591) (1671:1671:1671)) + (PORT datac (857:857:857) (917:917:917)) + (PORT datad (421:421:421) (491:491:491)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (710:710:710) (805:805:805)) + (PORT datad (847:847:847) (895:895:895)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (943:943:943)) + (PORT datab (1389:1389:1389) (1433:1433:1433)) + (PORT datac (204:204:204) (242:242:242)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (452:452:452) (514:514:514)) + (PORT datab (270:270:270) (325:325:325)) + (PORT datad (605:605:605) (628:628:628)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (886:886:886)) + (PORT datab (812:812:812) (875:875:875)) + (PORT datac (607:607:607) (626:626:626)) + (PORT datad (617:617:617) (630:630:630)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (227:227:227) (270:270:270)) + (PORT datac (843:843:843) (913:913:913)) + (PORT datad (662:662:662) (672:672:672)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1717:1717:1717) (1813:1813:1813)) + (PORT ena (1475:1475:1475) (1479:1479:1479)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1717:1717:1717) (1813:1813:1813)) + (PORT ena (1485:1485:1485) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (920:920:920) (976:976:976)) + (PORT datab (932:932:932) (975:975:975)) + (PORT datad (214:214:214) (282:282:282)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1677:1677:1677) (1751:1751:1751)) + (PORT ena (1546:1546:1546) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1074:1074:1074) (1150:1150:1150)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1446:1446:1446) (1455:1455:1455)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (997:997:997) (1053:1053:1053)) + (PORT datab (967:967:967) (1008:1008:1008)) + (PORT datad (216:216:216) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1419:1419:1419) (1492:1492:1492)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1488:1488:1488) (1562:1562:1562)) + (PORT datab (663:663:663) (712:712:712)) + (PORT datad (1638:1638:1638) (1752:1752:1752)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (957:957:957) (989:989:989)) + (PORT ena (1186:1186:1186) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (956:956:956) (987:987:987)) + (PORT ena (1476:1476:1476) (1478:1478:1478)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (970:970:970)) + (PORT datab (956:956:956) (998:998:998)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT asdata (1182:1182:1182) (1255:1255:1255)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1429:1429:1429) (1502:1502:1502)) + (PORT ena (1196:1196:1196) (1165:1165:1165)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (689:689:689)) + (PORT datab (456:456:456) (531:531:531)) + (PORT datad (627:627:627) (664:664:664)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1431:1431:1431) (1502:1502:1502)) + (PORT ena (1163:1163:1163) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (1431:1431:1431) (1503:1503:1503)) + (PORT ena (1213:1213:1213) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (706:706:706)) + (PORT datab (239:239:239) (320:320:320)) + (PORT datad (626:626:626) (662:662:662)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (1427:1427:1427) (1500:1500:1500)) + (PORT ena (1256:1256:1256) (1255:1255:1255)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (983:983:983) (1033:1033:1033)) + (PORT datab (1290:1290:1290) (1329:1329:1329)) + (PORT datad (808:808:808) (878:878:878)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (403:403:403)) + (PORT datab (862:862:862) (914:914:914)) + (PORT datac (576:576:576) (606:606:606)) + (PORT datad (807:807:807) (828:828:828)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (614:614:614)) + (PORT datab (839:839:839) (859:859:859)) + (PORT datac (619:619:619) (659:659:659)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[14\]) + (DELAY + (ABSOLUTE + (PORT datab (902:902:902) (944:944:944)) + (PORT datad (877:877:877) (887:887:887)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1559:1559:1559)) + (PORT ena (1762:1762:1762) (1780:1780:1780)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (510:510:510)) + (PORT datab (213:213:213) (259:259:259)) + (PORT datac (584:584:584) (636:636:636)) + (PORT datad (673:673:673) (710:710:710)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (761:761:761) (801:801:801)) + (PORT ena (1203:1203:1203) (1189:1189:1189)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (621:621:621) (663:663:663)) + (PORT datad (560:560:560) (586:586:586)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (538:538:538) (569:569:569)) + (PORT ena (1185:1185:1185) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (606:606:606) (648:648:648)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (395:395:395) (466:466:466)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1539:1539:1539) (1609:1609:1609)) + (PORT datab (534:534:534) (553:553:553)) + (PORT datac (434:434:434) (481:481:481)) + (PORT datad (345:345:345) (369:369:369)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (1357:1357:1357) (1408:1408:1408)) + (PORT datac (420:420:420) (460:460:460)) + (PORT datad (208:208:208) (240:240:240)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1018:1018:1018) (1067:1067:1067)) + (PORT datab (879:879:879) (898:898:898)) + (PORT datac (1268:1268:1268) (1345:1345:1345)) + (PORT datad (1057:1057:1057) (1068:1068:1068)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (685:685:685) (721:721:721)) + (PORT datab (1094:1094:1094) (1099:1099:1099)) + (PORT datac (994:994:994) (1030:1030:1030)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (743:743:743) (837:837:837)) + (PORT datac (199:199:199) (234:234:234)) + (PORT datad (227:227:227) (256:256:256)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (882:882:882) (933:933:933)) + (PORT datac (1359:1359:1359) (1403:1403:1403)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (674:674:674)) + (PORT datab (413:413:413) (463:463:463)) + (PORT datac (855:855:855) (912:912:912)) + (PORT datad (242:242:242) (285:285:285)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (728:728:728)) + (PORT datab (860:860:860) (903:903:903)) + (PORT datac (2033:2033:2033) (2070:2070:2070)) + (PORT datad (836:836:836) (928:928:928)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (445:445:445)) + (PORT datab (1316:1316:1316) (1370:1370:1370)) + (PORT datac (609:609:609) (627:627:627)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (915:915:915)) + (PORT datab (354:354:354) (389:389:389)) + (PORT datac (610:610:610) (623:623:623)) + (PORT datad (640:640:640) (654:654:654)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (949:949:949)) + (PORT datab (600:600:600) (621:621:621)) + (PORT datac (196:196:196) (230:230:230)) + (PORT datad (809:809:809) (832:832:832)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (744:744:744)) + (PORT datab (874:874:874) (931:931:931)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (217:217:217) (255:255:255)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1036:1036:1036)) + (PORT datab (1285:1285:1285) (1323:1323:1323)) + (PORT datad (1367:1367:1367) (1447:1447:1447)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1476:1476:1476) (1478:1478:1478)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (905:905:905) (935:935:935)) + (PORT ena (1186:1186:1186) (1184:1184:1184)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (326:326:326)) + (PORT datab (959:959:959) (996:996:996)) + (PORT datad (880:880:880) (920:920:920)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (966:966:966) (1015:1015:1015)) + (PORT ena (1163:1163:1163) (1152:1152:1152)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (969:969:969) (1017:1017:1017)) + (PORT ena (1213:1213:1213) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (711:711:711)) + (PORT datab (378:378:378) (450:450:450)) + (PORT datad (620:620:620) (653:653:653)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (1052:1052:1052) (1055:1055:1055)) + (PORT datad (328:328:328) (344:344:344)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT asdata (1215:1215:1215) (1257:1257:1257)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1488:1488:1488) (1562:1562:1562)) + (PORT datab (662:662:662) (713:713:713)) + (PORT datad (1636:1636:1636) (1747:1747:1747)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (846:846:846)) + (PORT datab (915:915:915) (949:949:949)) + (PORT datac (338:338:338) (359:359:359)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (644:644:644)) + (PORT datab (645:645:645) (697:697:697)) + (PORT datac (1345:1345:1345) (1373:1373:1373)) + (PORT datad (375:375:375) (406:406:406)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (866:866:866) (878:878:878)) + (PORT ena (1164:1164:1164) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (608:608:608)) + (PORT datab (622:622:622) (664:664:664)) + (PORT datac (425:425:425) (498:498:498)) + (PORT datad (563:563:563) (590:590:590)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (432:432:432) (520:520:520)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datad (584:584:584) (613:613:613)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1538:1538:1538) (1606:1606:1606)) + (PORT datab (586:586:586) (605:605:605)) + (PORT datac (435:435:435) (481:481:481)) + (PORT datad (348:348:348) (372:372:372)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[13\]) + (DELAY + (ABSOLUTE + (PORT datab (902:902:902) (948:948:948)) + (PORT datac (775:775:775) (783:783:783)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1559:1559:1559)) + (PORT ena (1762:1762:1762) (1780:1780:1780)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) + (DELAY + (ABSOLUTE + (PORT datab (711:711:711) (744:744:744)) + (PORT datac (392:392:392) (466:466:466)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[15\]) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (887:887:887)) + (PORT datad (867:867:867) (907:907:907)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1579:1579:1579) (1559:1559:1559)) + (PORT ena (1762:1762:1762) (1780:1780:1780)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_16) + (DELAY + (ABSOLUTE + (PORT dataa (1143:1143:1143) (1199:1199:1199)) + (PORT datab (399:399:399) (474:474:474)) + (PORT datac (670:670:670) (691:691:691)) + (PORT datad (1153:1153:1153) (1200:1200:1200)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (213:213:213) (257:257:257)) + (PORT datac (548:548:548) (605:605:605)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1542:1542:1542) (1611:1611:1611)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (431:431:431) (485:485:485)) + (PORT datad (526:526:526) (542:542:542)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (638:638:638)) + (PORT datab (400:400:400) (442:442:442)) + (PORT datac (1344:1344:1344) (1372:1372:1372)) + (PORT datad (551:551:551) (569:569:569)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1203:1203:1203) (1249:1249:1249)) + (PORT datab (882:882:882) (895:895:895)) + (PORT datac (567:567:567) (583:583:583)) + (PORT datad (1058:1058:1058) (1064:1064:1064)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (721:721:721)) + (PORT datab (1094:1094:1094) (1103:1103:1103)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (813:813:813) (871:871:871)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (450:450:450) (491:491:491)) + (PORT datab (1860:1860:1860) (1955:1955:1955)) + (PORT datac (1054:1054:1054) (1101:1101:1101)) + (PORT datad (244:244:244) (315:315:315)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (807:807:807) (861:861:861)) + (PORT datab (385:385:385) (404:404:404)) + (PORT datac (252:252:252) (308:308:308)) + (PORT datad (343:343:343) (357:357:357)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (408:408:408) (431:431:431)) + (PORT datab (591:591:591) (610:610:610)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (857:857:857) (859:859:859)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (436:436:436)) + (PORT datab (285:285:285) (345:345:345)) + (PORT datad (856:856:856) (862:862:862)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (926:926:926)) + (PORT datab (716:716:716) (777:777:777)) + (PORT datad (886:886:886) (910:910:910)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (703:703:703)) + (PORT datab (606:606:606) (624:624:624)) + (PORT datac (249:249:249) (307:307:307)) + (PORT datad (554:554:554) (572:572:572)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (885:885:885) (899:899:899)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (581:581:581) (608:608:608)) + (PORT datab (718:718:718) (786:786:786)) + (PORT datac (966:966:966) (1066:1066:1066)) + (PORT datad (995:995:995) (1046:1046:1046)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (723:723:723)) + (PORT datab (618:618:618) (649:649:649)) + (PORT datac (628:628:628) (663:663:663)) + (PORT datad (356:356:356) (387:387:387)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (457:457:457) (532:532:532)) + (PORT datab (870:870:870) (896:896:896)) + (PORT datac (519:519:519) (536:536:536)) + (PORT datad (399:399:399) (466:466:466)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (415:415:415) (497:497:497)) + (PORT datab (1023:1023:1023) (1072:1072:1072)) + (PORT datac (819:819:819) (866:866:866)) + (PORT datad (625:625:625) (636:636:636)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (375:375:375) (399:399:399)) + (PORT datab (1228:1228:1228) (1318:1318:1318)) + (PORT datac (696:696:696) (757:757:757)) + (PORT datad (886:886:886) (912:912:912)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT datac (383:383:383) (414:414:414)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (663:663:663)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (585:585:585) (600:600:600)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (456:456:456)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (200:200:200) (237:237:237)) + (PORT datad (328:328:328) (349:349:349)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) + (DELAY + (ABSOLUTE + (PORT datab (646:646:646) (675:675:675)) + (PORT datac (810:810:810) (825:825:825)) + (PORT datad (655:655:655) (668:668:668)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (861:861:861)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datad (350:350:350) (366:366:366)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (275:275:275)) + (PORT datab (668:668:668) (691:691:691)) + (PORT datac (842:842:842) (879:879:879)) + (PORT datad (931:931:931) (964:964:964)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (946:946:946) (1005:1005:1005)) + (PORT datab (216:216:216) (260:260:260)) + (PORT datac (547:547:547) (557:557:557)) + (PORT datad (1236:1236:1236) (1277:1277:1277)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1336:1336:1336) (1342:1342:1342)) + (PORT datab (2282:2282:2282) (2366:2366:2366)) + (PORT datac (1180:1180:1180) (1239:1239:1239)) + (PORT datad (1331:1331:1331) (1363:1363:1363)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (622:622:622)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (1252:1252:1252) (1287:1287:1287)) + (PORT datad (952:952:952) (991:991:991)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (531:531:531) (556:556:556)) + (PORT datab (854:854:854) (864:864:864)) + (PORT datac (547:547:547) (558:558:558)) + (PORT datad (610:610:610) (649:649:649)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~4) + (DELAY + (ABSOLUTE + (PORT datab (844:844:844) (872:872:872)) + (PORT datac (829:829:829) (842:842:842)) + (PORT datad (1173:1173:1173) (1229:1229:1229)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1798:1798:1798) (1899:1899:1899)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datac (1834:1834:1834) (1965:1965:1965)) + (PORT datad (1601:1601:1601) (1748:1748:1748)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (1649:1649:1649) (1760:1760:1760)) + (PORT datac (1397:1397:1397) (1433:1433:1433)) + (PORT datad (2275:2275:2275) (2370:2370:2370)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datad (181:181:181) (211:211:211)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (362:362:362)) + (PORT datab (1863:1863:1863) (1958:1958:1958)) + (PORT datac (1087:1087:1087) (1133:1133:1133)) + (PORT datad (246:246:246) (318:318:318)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (359:359:359)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT datab (952:952:952) (1016:1016:1016)) + (PORT datac (1076:1076:1076) (1122:1122:1122)) + (PORT datad (632:632:632) (661:661:661)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1608:1608:1608) (1639:1639:1639)) + (PORT datab (964:964:964) (1002:1002:1002)) + (PORT datac (1030:1030:1030) (1064:1064:1064)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (694:694:694)) + (PORT datab (286:286:286) (344:344:344)) + (PORT datac (201:201:201) (239:239:239)) + (PORT datad (549:549:549) (567:567:567)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (884:884:884) (897:897:897)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (436:436:436) (530:530:530)) + (PORT datab (1590:1590:1590) (1672:1672:1672)) + (PORT datac (858:858:858) (922:922:922)) + (PORT datad (599:599:599) (660:660:660)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (669:669:669) (691:691:691)) + (PORT ena (1535:1535:1535) (1542:1542:1542)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (447:447:447) (510:510:510)) + (PORT datab (586:586:586) (606:606:606)) + (PORT datac (850:850:850) (911:911:911)) + (PORT datad (240:240:240) (284:284:284)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (912:912:912)) + (PORT datab (367:367:367) (387:387:387)) + (PORT datad (598:598:598) (630:630:630)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (859:859:859)) + (PORT datab (669:669:669) (685:685:685)) + (PORT datac (574:574:574) (583:583:583)) + (PORT datad (342:342:342) (354:354:354)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (991:991:991)) + (PORT datab (1072:1072:1072) (1137:1137:1137)) + (PORT datac (580:580:580) (650:650:650)) + (PORT datad (642:642:642) (673:673:673)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (726:726:726)) + (PORT datab (999:999:999) (1052:1052:1052)) + (PORT datac (627:627:627) (664:664:664)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (723:723:723)) + (PORT datab (665:665:665) (708:708:708)) + (PORT datac (575:575:575) (604:604:604)) + (PORT datad (972:972:972) (1013:1013:1013)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT datac (628:628:628) (662:662:662)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (434:434:434) (528:528:528)) + (PORT datab (591:591:591) (625:625:625)) + (PORT datac (435:435:435) (513:513:513)) + (PORT datad (830:830:830) (856:856:856)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (249:249:249) (304:304:304)) + (PORT datab (554:554:554) (570:570:570)) + (PORT datac (554:554:554) (586:586:586)) + (PORT datad (1081:1081:1081) (1087:1087:1087)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (892:892:892)) + (PORT datab (1082:1082:1082) (1083:1083:1083)) + (PORT datac (801:801:801) (808:808:808)) + (PORT datad (782:782:782) (795:795:795)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~36) + (DELAY + (ABSOLUTE + (PORT datab (224:224:224) (272:272:272)) + (PORT datac (217:217:217) (261:261:261)) + (PORT datad (831:831:831) (859:859:859)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~35) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (257:257:257)) + (PORT datab (225:225:225) (273:273:273)) + (PORT datac (217:217:217) (258:258:258)) + (PORT datad (832:832:832) (857:857:857)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1505:1505:1505) (1591:1591:1591)) + (PORT datab (1459:1459:1459) (1480:1480:1480)) + (PORT datac (1862:1862:1862) (1880:1880:1880)) + (PORT datad (1327:1327:1327) (1360:1360:1360)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1108:1108:1108) (1137:1137:1137)) + (PORT datab (1392:1392:1392) (1450:1450:1450)) + (PORT datac (798:798:798) (814:814:814)) + (PORT datad (1298:1298:1298) (1369:1369:1369)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1937:1937:1937) (2026:2026:2026)) + (PORT datab (212:212:212) (256:256:256)) + (PORT datac (1953:1953:1953) (2056:2056:2056)) + (PORT datad (1615:1615:1615) (1688:1688:1688)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1125:1125:1125) (1152:1152:1152)) + (PORT datab (370:370:370) (396:396:396)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (824:824:824) (863:863:863)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~17) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (528:528:528) (540:540:540)) + (PORT datad (580:580:580) (593:593:593)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) + (DELAY + (ABSOLUTE + (PORT datab (1770:1770:1770) (1810:1810:1810)) + (PORT datac (1173:1173:1173) (1220:1220:1220)) + (PORT datad (1440:1440:1440) (1461:1461:1461)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (340:340:340)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (254:254:254) (313:313:313)) + (PORT datad (1200:1200:1200) (1271:1271:1271)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) + (DELAY + (ABSOLUTE + (PORT dataa (2211:2211:2211) (2401:2401:2401)) + (PORT datab (1578:1578:1578) (1721:1721:1721)) + (PORT datac (1756:1756:1756) (1850:1850:1850)) + (PORT datad (857:857:857) (888:888:888)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (1859:1859:1859) (1955:1955:1955)) + (PORT datac (605:605:605) (631:631:631)) + (PORT datad (944:944:944) (992:992:992)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1804:1804:1804) (1902:1902:1902)) + (PORT datab (1429:1429:1429) (1461:1461:1461)) + (PORT datac (1430:1430:1430) (1464:1464:1464)) + (PORT datad (2319:2319:2319) (2472:2472:2472)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1547:1547:1547) (1642:1642:1642)) + (PORT datab (1225:1225:1225) (1267:1267:1267)) + (PORT datac (1428:1428:1428) (1462:1462:1462)) + (PORT datad (1636:1636:1636) (1711:1711:1711)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1464:1464:1464) (1499:1499:1499)) + (PORT datab (684:684:684) (724:724:724)) + (PORT datac (1191:1191:1191) (1233:1233:1233)) + (PORT datad (1662:1662:1662) (1693:1693:1693)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (671:671:671)) + (PORT datab (2007:2007:2007) (2122:2122:2122)) + (PORT datac (1547:1547:1547) (1649:1649:1649)) + (PORT datad (2319:2319:2319) (2472:2472:2472)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1548:1548:1548) (1643:1643:1643)) + (PORT datab (680:680:680) (721:721:721)) + (PORT datac (1534:1534:1534) (1622:1622:1622)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (332:332:332)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (681:681:681) (728:728:728)) + (PORT datac (2002:2002:2002) (2034:2034:2034)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (378:378:378)) + (PORT datab (375:375:375) (401:401:401)) + (PORT datac (317:317:317) (348:348:348)) + (PORT datad (875:875:875) (912:912:912)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~37) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (698:698:698)) + (PORT datab (643:643:643) (669:669:669)) + (PORT datac (1186:1186:1186) (1232:1232:1232)) + (PORT datad (366:366:366) (388:388:388)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (986:986:986)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (1404:1404:1404) (1439:1439:1439)) + (PORT datad (619:619:619) (649:649:649)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (704:704:704)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1184:1184:1184) (1224:1224:1224)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (680:680:680)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (581:581:581) (598:598:598)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1504:1504:1504) (1590:1590:1590)) + (PORT datab (1459:1459:1459) (1480:1480:1480)) + (PORT datac (1045:1045:1045) (1092:1092:1092)) + (PORT datad (1326:1326:1326) (1360:1360:1360)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (927:927:927) (983:983:983)) + (PORT datac (900:900:900) (967:967:967)) + (PORT datad (2255:2255:2255) (2330:2330:2330)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1308:1308:1308) (1389:1389:1389)) + (PORT datab (1282:1282:1282) (1317:1317:1317)) + (PORT datac (903:903:903) (968:968:968)) + (PORT datad (1147:1147:1147) (1224:1224:1224)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1465:1465:1465) (1478:1478:1478)) + (PORT datab (991:991:991) (1033:1033:1033)) + (PORT datac (382:382:382) (406:406:406)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (399:399:399)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (523:523:523) (528:528:528)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (896:896:896)) + (PORT datab (650:650:650) (675:675:675)) + (PORT datac (342:342:342) (365:365:365)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (882:882:882)) + (PORT datab (639:639:639) (683:683:683)) + (PORT datac (811:811:811) (813:813:813)) + (PORT datad (1234:1234:1234) (1284:1284:1284)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (704:704:704)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (181:181:181) (212:212:212)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (554:554:554) (564:564:564)) + (PORT datac (178:178:178) (216:216:216)) + (PORT datad (584:584:584) (600:600:600)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (473:473:473) (549:549:549)) + (PORT datab (1591:1591:1591) (1671:1671:1671)) + (PORT datac (998:998:998) (1082:1082:1082)) + (PORT datad (844:844:844) (897:897:897)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (726:726:726) (802:802:802)) + (PORT datac (204:204:204) (242:242:242)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (712:712:712)) + (PORT datab (1350:1350:1350) (1417:1417:1417)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (674:674:674)) + (PORT datab (413:413:413) (463:463:463)) + (PORT datac (854:854:854) (913:913:913)) + (PORT datad (244:244:244) (285:285:285)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (878:878:878)) + (PORT datab (1313:1313:1313) (1370:1370:1370)) + (PORT datac (768:768:768) (840:840:840)) + (PORT datad (753:753:753) (788:788:788)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (915:915:915)) + (PORT datab (354:354:354) (384:384:384)) + (PORT datac (570:570:570) (580:580:580)) + (PORT datad (640:640:640) (657:657:657)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (692:692:692)) + (PORT datab (288:288:288) (346:346:346)) + (PORT datad (853:853:853) (857:857:857)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (1027:1027:1027) (1080:1080:1080)) + (PORT datac (998:998:998) (1082:1082:1082)) + (PORT datad (598:598:598) (658:658:658)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (435:435:435) (524:524:524)) + (PORT datab (593:593:593) (621:621:621)) + (PORT datac (435:435:435) (509:509:509)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (867:867:867) (892:892:892)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (587:587:587) (604:604:604)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (302:302:302)) + (PORT datab (256:256:256) (302:302:302)) + (PORT datac (525:525:525) (539:539:539)) + (PORT datad (181:181:181) (211:211:211)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (426:426:426) (455:455:455)) + (PORT datab (394:394:394) (418:418:418)) + (PORT datac (381:381:381) (403:403:403)) + (PORT datad (335:335:335) (355:355:355)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (407:407:407)) + (PORT datab (215:215:215) (260:260:260)) + (PORT datac (587:587:587) (602:602:602)) + (PORT datad (179:179:179) (206:206:206)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (612:612:612) (629:629:629)) + (PORT datac (184:184:184) (224:224:224)) + (PORT datad (178:178:178) (206:206:206)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (558:558:558) (589:589:589)) + (PORT ena (1535:1535:1535) (1542:1542:1542)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (379:379:379) (448:448:448)) + (PORT datad (845:845:845) (867:867:867)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (961:961:961)) + (PORT datab (715:715:715) (786:786:786)) + (PORT datac (1555:1555:1555) (1630:1630:1630)) + (PORT datad (399:399:399) (466:466:466)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) + (DELAY + (ABSOLUTE + (PORT dataa (440:440:440) (500:500:500)) + (PORT datad (602:602:602) (625:625:625)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (810:810:810) (836:836:836)) + (PORT datab (1100:1100:1100) (1140:1140:1140)) + (PORT datac (379:379:379) (412:412:412)) + (PORT datad (895:895:895) (920:920:920)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (785:785:785) (808:808:808)) + (PORT datab (676:676:676) (693:693:693)) + (PORT datac (345:345:345) (369:369:369)) + (PORT datad (327:327:327) (345:345:345)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1107:1107:1107) (1118:1118:1118)) + (PORT datab (884:884:884) (901:901:901)) + (PORT datac (1027:1027:1027) (1078:1078:1078)) + (PORT datad (981:981:981) (1014:1014:1014)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (683:683:683)) + (PORT datab (1094:1094:1094) (1101:1101:1101)) + (PORT datac (530:530:530) (542:542:542)) + (PORT datad (658:658:658) (677:677:677)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (662:662:662)) + (PORT datab (676:676:676) (735:735:735)) + (PORT datac (1314:1314:1314) (1328:1328:1328)) + (PORT datad (1142:1142:1142) (1172:1172:1172)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1027:1027:1027) (1032:1032:1032)) + (PORT datab (1108:1108:1108) (1163:1163:1163)) + (PORT datad (1085:1085:1085) (1076:1076:1076)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_hf2) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (384:384:384) (458:458:458)) + (PORT datac (379:379:379) (440:440:440)) + (PORT datad (386:386:386) (446:446:446)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe) + (DELAY + (ABSOLUTE + (PORT dataa (990:990:990) (1041:1041:1041)) + (PORT datab (2280:2280:2280) (2375:2375:2375)) + (PORT datad (2190:2190:2190) (2361:2361:2361)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (329:329:329)) + (PORT datab (605:605:605) (655:655:655)) + (PORT datac (802:802:802) (820:820:820)) + (PORT datad (1419:1419:1419) (1423:1423:1423)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (1395:1395:1395) (1451:1451:1451)) + (PORT datad (182:182:182) (213:213:213)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1230:1230:1230) (1286:1286:1286)) + (PORT datab (947:947:947) (992:992:992)) + (PORT datac (1206:1206:1206) (1235:1235:1235)) + (PORT datad (1186:1186:1186) (1199:1199:1199)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (276:276:276) (346:346:346)) + (PORT datab (1765:1765:1765) (1806:1806:1806)) + (PORT datac (247:247:247) (305:305:305)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (671:671:671)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datac (1094:1094:1094) (1107:1107:1107)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (885:885:885)) + (PORT datab (910:910:910) (959:959:959)) + (PORT datac (827:827:827) (862:862:862)) + (PORT datad (816:816:816) (839:839:839)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (906:906:906)) + (PORT datab (202:202:202) (242:242:242)) + (PORT datac (630:630:630) (665:665:665)) + (PORT datad (625:625:625) (641:641:641)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (864:864:864)) + (PORT datab (205:205:205) (246:246:246)) + (PORT datac (885:885:885) (913:913:913)) + (PORT datad (176:176:176) (203:203:203)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (328:328:328)) + (PORT datab (1135:1135:1135) (1215:1215:1215)) + (PORT datad (1221:1221:1221) (1258:1258:1258)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (547:547:547) (582:582:582)) + (PORT ena (1248:1248:1248) (1256:1256:1256)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (923:923:923) (953:953:953)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (841:841:841) (847:847:847)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1256:1256:1256)) + (PORT datab (682:682:682) (747:747:747)) + (PORT datad (875:875:875) (945:945:945)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (625:625:625) (679:679:679)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (547:547:547) (582:582:582)) + (PORT ena (1275:1275:1275) (1314:1314:1314)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (787:787:787)) + (PORT datab (729:729:729) (781:781:781)) + (PORT datad (1021:1021:1021) (1061:1061:1061)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (680:680:680)) + (PORT datab (611:611:611) (638:638:638)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (412:412:412)) + (PORT datab (612:612:612) (639:639:639)) + (PORT datac (309:309:309) (325:325:325)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (262:262:262)) + (PORT datab (195:195:195) (234:234:234)) + (PORT datac (816:816:816) (831:831:831)) + (PORT datad (1118:1118:1118) (1134:1134:1134)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1241:1241:1241) (1251:1251:1251)) + (PORT ena (816:816:816) (813:813:813)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1096:1096:1096) (1126:1126:1126)) + (PORT datab (219:219:219) (259:259:259)) + (PORT datad (1117:1117:1117) (1141:1141:1141)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1252:1252:1252) (1240:1240:1240)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (624:624:624) (639:639:639)) + (PORT datac (666:666:666) (695:695:695)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (450:450:450)) + (PORT datab (626:626:626) (654:654:654)) + (PORT datac (1197:1197:1197) (1250:1250:1250)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (1110:1110:1110) (1140:1140:1140)) + (PORT datad (880:880:880) (895:895:895)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1592:1592:1592) (1568:1568:1568)) + (PORT ena (2023:2023:2023) (2039:2039:2039)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (1341:1341:1341) (1362:1362:1362)) + (PORT datad (370:370:370) (394:394:394)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1550:1550:1550)) + (PORT asdata (934:934:934) (951:951:951)) + (PORT clrn (1591:1591:1591) (1568:1568:1568)) + (PORT ena (2020:2020:2020) (2056:2056:2056)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (673:673:673)) + (PORT datab (614:614:614) (636:636:636)) + (PORT datac (590:590:590) (657:657:657)) + (PORT datad (665:665:665) (729:729:729)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (422:422:422) (513:513:513)) + (PORT datab (617:617:617) (639:639:639)) + (PORT datac (613:613:613) (666:666:666)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1222:1222:1222) (1224:1224:1224)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (537:537:537) (568:568:568)) + (PORT ena (1237:1237:1237) (1220:1220:1220)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (950:950:950) (978:978:978)) + (PORT ena (1426:1426:1426) (1409:1409:1409)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (950:950:950) (976:976:976)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (248:248:248) (316:316:316)) + (PORT datab (1080:1080:1080) (1115:1115:1115)) + (PORT datad (355:355:355) (415:415:415)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT asdata (1773:1773:1773) (1846:1846:1846)) + (PORT ena (961:961:961) (970:970:970)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT asdata (1773:1773:1773) (1845:1845:1845)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (330:330:330)) + (PORT datab (244:244:244) (292:292:292)) + (PORT datad (211:211:211) (244:244:244)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1770:1770:1770) (1824:1824:1824)) + (PORT ena (1243:1243:1243) (1273:1273:1273)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1253:1253:1253)) + (PORT datab (675:675:675) (717:717:717)) + (PORT datad (833:833:833) (842:842:842)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1772:1772:1772) (1824:1824:1824)) + (PORT ena (1168:1168:1168) (1161:1161:1161)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (456:456:456)) + (PORT datab (195:195:195) (234:234:234)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1712:1712:1712) (1752:1752:1752)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1111:1111:1111) (1133:1133:1133)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (260:260:260) (327:327:327)) + (PORT datab (242:242:242) (325:325:325)) + (PORT datad (1377:1377:1377) (1480:1480:1480)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (953:953:953) (981:981:981)) + (PORT ena (1147:1147:1147) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (953:953:953) (981:981:981)) + (PORT ena (1248:1248:1248) (1262:1262:1262)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (661:661:661)) + (PORT datab (942:942:942) (999:999:999)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (849:849:849)) + (PORT datab (643:643:643) (660:660:660)) + (PORT datac (593:593:593) (636:636:636)) + (PORT datad (620:620:620) (630:630:630)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1220:1220:1220) (1238:1238:1238)) + (PORT ena (923:923:923) (907:907:907)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1221:1221:1221) (1239:1239:1239)) + (PORT ena (984:984:984) (983:983:983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (459:459:459)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datad (417:417:417) (449:449:449)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (699:699:699)) + (PORT datab (864:864:864) (869:869:869)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (896:896:896)) + (PORT datab (400:400:400) (430:430:430)) + (PORT datac (1133:1133:1133) (1187:1187:1187)) + (PORT datad (666:666:666) (703:703:703)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1465:1465:1465) (1521:1521:1521)) + (PORT datab (675:675:675) (709:709:709)) + (PORT datad (326:326:326) (344:344:344)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (635:635:635)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datad (606:606:606) (629:629:629)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (894:894:894)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1210:1210:1210) (1264:1264:1264)) + (PORT datad (217:217:217) (253:253:253)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[5\]) + (DELAY + (ABSOLUTE + (PORT dataa (1110:1110:1110) (1140:1140:1140)) + (PORT datad (625:625:625) (641:641:641)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1592:1592:1592) (1568:1568:1568)) + (PORT ena (2023:2023:2023) (2039:2039:2039)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1147:1147:1147) (1181:1181:1181)) + (PORT datab (1473:1473:1473) (1524:1524:1524)) + (PORT datac (1184:1184:1184) (1245:1245:1245)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (623:623:623)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (624:624:624) (671:671:671)) + (PORT datad (181:181:181) (212:212:212)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1466:1466:1466) (1490:1490:1490)) + (PORT ena (1426:1426:1426) (1409:1409:1409)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1462:1462:1462) (1486:1486:1486)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (308:308:308)) + (PORT datab (1080:1080:1080) (1120:1120:1120)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1220:1220:1220) (1250:1250:1250)) + (PORT ena (984:984:984) (983:983:983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1220:1220:1220) (1249:1249:1249)) + (PORT ena (923:923:923) (907:907:907)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (463:463:463)) + (PORT datab (449:449:449) (477:477:477)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1192:1192:1192) (1211:1211:1211)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1274:1274:1274) (1361:1361:1361)) + (PORT datab (1009:1009:1009) (1055:1055:1055)) + (PORT datad (895:895:895) (946:946:946)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1870:1870:1870) (1916:1916:1916)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (259:259:259) (322:322:322)) + (PORT datab (1137:1137:1137) (1215:1215:1215)) + (PORT datad (855:855:855) (880:880:880)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT asdata (970:970:970) (997:997:997)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (958:958:958) (996:996:996)) + (PORT ena (1275:1275:1275) (1314:1314:1314)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (1150:1150:1150) (1226:1226:1226)) + (PORT datab (725:725:725) (775:775:775)) + (PORT datad (1020:1020:1020) (1061:1061:1061)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (958:958:958) (999:999:999)) + (PORT ena (1248:1248:1248) (1256:1256:1256)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1712:1712:1712) (1752:1752:1752)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (1178:1178:1178) (1252:1252:1252)) + (PORT datab (676:676:676) (740:740:740)) + (PORT datad (656:656:656) (714:714:714)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (692:692:692)) + (PORT datab (643:643:643) (692:692:692)) + (PORT datac (572:572:572) (583:583:583)) + (PORT datad (312:312:312) (330:330:330)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1247:1247:1247) (1278:1278:1278)) + (PORT ena (1147:1147:1147) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (640:640:640) (678:678:678)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1248:1248:1248) (1262:1262:1262)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (660:660:660)) + (PORT datab (942:942:942) (998:998:998)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (649:649:649)) + (PORT datab (327:327:327) (355:355:355)) + (PORT datac (341:341:341) (363:363:363)) + (PORT datad (335:335:335) (355:355:355)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (685:685:685)) + (PORT datab (701:701:701) (738:738:738)) + (PORT datac (1136:1136:1136) (1185:1185:1185)) + (PORT datad (522:522:522) (540:540:540)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (848:848:848) (860:860:860)) + (PORT ena (1237:1237:1237) (1220:1220:1220)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1468:1468:1468) (1518:1518:1518)) + (PORT datab (384:384:384) (417:417:417)) + (PORT datad (643:643:643) (665:665:665)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1252:1252:1252) (1240:1240:1240)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (706:706:706) (734:734:734)) + (PORT datab (332:332:332) (360:360:360)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (874:874:874)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (1197:1197:1197) (1251:1251:1251)) + (PORT datad (383:383:383) (403:403:403)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[6\]) + (DELAY + (ABSOLUTE + (PORT datab (802:802:802) (828:828:828)) + (PORT datad (1064:1064:1064) (1089:1089:1089)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1592:1592:1592) (1568:1568:1568)) + (PORT ena (2023:2023:2023) (2039:2039:2039)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (275:275:275)) + (PORT datab (876:876:876) (905:905:905)) + (PORT datac (623:623:623) (669:669:669)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (251:251:251)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (579:579:579) (585:585:585)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (1246:1246:1246) (1247:1247:1247)) + (PORT datab (907:907:907) (936:936:936)) + (PORT datac (385:385:385) (451:451:451)) + (PORT datad (914:914:914) (972:972:972)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (894:894:894) (915:915:915)) + (PORT ena (1203:1203:1203) (1189:1189:1189)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (694:694:694)) + (PORT datab (622:622:622) (668:668:668)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1185:1185:1185) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (608:608:608) (648:648:648)) + (PORT datad (418:418:418) (490:490:490)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (406:406:406)) + (PORT datab (403:403:403) (433:433:433)) + (PORT datac (434:434:434) (479:479:479)) + (PORT datad (1502:1502:1502) (1569:1569:1569)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (656:656:656)) + (PORT datab (234:234:234) (278:278:278)) + (PORT datac (550:550:550) (571:571:571)) + (PORT datad (1321:1321:1321) (1374:1374:1374)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (909:909:909)) + (PORT datab (873:873:873) (928:928:928)) + (PORT datac (632:632:632) (677:677:677)) + (PORT datad (805:805:805) (833:833:833)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1808:1808:1808) (1853:1853:1853)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (572:572:572) (589:589:589)) + (PORT datad (220:220:220) (259:259:259)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (912:912:912)) + (PORT datad (809:809:809) (836:836:836)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (247:247:247)) + (PORT datab (1225:1225:1225) (1265:1265:1265)) + (PORT datac (878:878:878) (918:918:918)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (900:900:900)) + (PORT datab (1164:1164:1164) (1207:1207:1207)) + (PORT datac (1156:1156:1156) (1177:1177:1177)) + (PORT datad (612:612:612) (661:661:661)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1200:1200:1200) (1256:1256:1256)) + (PORT datab (676:676:676) (714:714:714)) + (PORT datad (1092:1092:1092) (1117:1117:1117)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (1354:1354:1354) (1395:1395:1395)) + (PORT ena (1263:1263:1263) (1252:1252:1252)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|db\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1299:1299:1299) (1381:1381:1381)) + (PORT datab (920:920:920) (933:933:933)) + (PORT datad (1369:1369:1369) (1414:1414:1414)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (1193:1193:1193) (1215:1215:1215)) + (PORT ena (1426:1426:1426) (1409:1409:1409)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1187:1187:1187) (1217:1217:1217)) + (PORT ena (984:984:984) (983:983:983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1189:1189:1189) (1217:1217:1217)) + (PORT ena (923:923:923) (907:907:907)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (464:464:464)) + (PORT datab (450:450:450) (488:488:488)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (798:798:798) (832:832:832)) + (PORT datab (631:631:631) (666:666:666)) + (PORT datad (614:614:614) (639:639:639)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1168:1168:1168) (1161:1161:1161)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT asdata (992:992:992) (1028:1028:1028)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT asdata (990:990:990) (1027:1027:1027)) + (PORT ena (961:961:961) (970:970:970)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (459:459:459)) + (PORT datab (245:245:245) (293:293:293)) + (PORT datad (209:209:209) (240:240:240)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1181:1181:1181) (1196:1196:1196)) + (PORT ena (1712:1712:1712) (1752:1752:1752)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1178:1178:1178) (1193:1193:1193)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (264:264:264) (330:330:330)) + (PORT datab (1409:1409:1409) (1523:1523:1523)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (605:605:605) (642:642:642)) + (PORT datac (377:377:377) (418:418:418)) + (PORT datad (312:312:312) (331:331:331)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (676:676:676)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datac (522:522:522) (536:536:536)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1068:1068:1068) (1068:1068:1068)) + (PORT datab (1183:1183:1183) (1199:1199:1199)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (660:660:660) (693:693:693)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1154:1154:1154) (1163:1163:1163)) + (PORT ena (1237:1237:1237) (1220:1220:1220)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1467:1467:1467) (1517:1517:1517)) + (PORT datab (1185:1185:1185) (1225:1225:1225)) + (PORT datad (651:651:651) (673:673:673)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1252:1252:1252) (1240:1240:1240)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (370:370:370)) + (PORT datac (665:665:665) (694:694:694)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (420:420:420) (444:444:444)) + (PORT datab (220:220:220) (257:257:257)) + (PORT datac (1193:1193:1193) (1246:1246:1246)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[0\]) + (DELAY + (ABSOLUTE + (PORT datac (880:880:880) (936:936:936)) + (PORT datad (786:786:786) (788:788:788)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (1783:1783:1783) (1814:1814:1814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) + (DELAY + (ABSOLUTE + (PORT dataa (1451:1451:1451) (1493:1493:1493)) + (PORT datab (1095:1095:1095) (1151:1151:1151)) + (PORT datac (670:670:670) (690:690:690)) + (PORT datad (1103:1103:1103) (1138:1138:1138)) + (IOPATH dataa combout (350:350:350) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (746:746:746)) + (PORT datab (1400:1400:1400) (1451:1451:1451)) + (PORT datac (177:177:177) (214:214:214)) + (PORT datad (1354:1354:1354) (1397:1397:1397)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1252:1252:1252) (1240:1240:1240)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1457:1457:1457) (1516:1516:1516)) + (PORT ena (984:984:984) (983:983:983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1460:1460:1460) (1519:1519:1519)) + (PORT ena (923:923:923) (907:907:907)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (462:462:462)) + (PORT datab (449:449:449) (476:476:476)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (989:989:989) (1030:1030:1030)) + (PORT ena (1248:1248:1248) (1256:1256:1256)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1552:1552:1552)) + (PORT asdata (1378:1378:1378) (1437:1437:1437)) + (PORT ena (841:841:841) (847:847:847)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1254:1254:1254)) + (PORT datab (678:678:678) (743:743:743)) + (PORT datad (876:876:876) (941:941:941)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT asdata (1476:1476:1476) (1497:1497:1497)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1423:1423:1423) (1461:1461:1461)) + (PORT ena (1243:1243:1243) (1273:1273:1273)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (688:688:688) (768:768:768)) + (PORT datab (677:677:677) (714:714:714)) + (PORT datad (632:632:632) (658:658:658)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1422:1422:1422) (1461:1461:1461)) + (PORT ena (1168:1168:1168) (1161:1161:1161)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (461:461:461)) + (PORT datab (195:195:195) (234:234:234)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (911:911:911) (922:922:922)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (965:965:965)) + (PORT datab (1338:1338:1338) (1383:1383:1383)) + (PORT datac (840:840:840) (853:853:853)) + (PORT datad (840:840:840) (891:891:891)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (375:375:375)) + (PORT datab (619:619:619) (654:654:654)) + (PORT datad (319:319:319) (337:337:337)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT asdata (931:931:931) (962:962:962)) + (PORT ena (1426:1426:1426) (1409:1409:1409)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (587:587:587) (620:620:620)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (318:318:318)) + (PORT datab (1080:1080:1080) (1113:1113:1113)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1220:1220:1220) (1247:1247:1247)) + (PORT ena (1147:1147:1147) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (641:641:641) (675:675:675)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1248:1248:1248) (1262:1262:1262)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (665:665:665)) + (PORT datab (940:940:940) (1003:1003:1003)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (525:525:525) (543:543:543)) + (PORT datab (371:371:371) (391:391:391)) + (PORT datac (833:833:833) (839:839:839)) + (PORT datad (313:313:313) (322:322:322)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (814:814:814) (843:843:843)) + (PORT datab (573:573:573) (588:588:588)) + (PORT datac (1136:1136:1136) (1189:1189:1189)) + (PORT datad (665:665:665) (698:698:698)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (850:850:850) (858:858:858)) + (PORT ena (1237:1237:1237) (1220:1220:1220)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1467:1467:1467) (1517:1517:1517)) + (PORT datab (384:384:384) (414:414:414)) + (PORT datad (644:644:644) (664:664:664)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (707:707:707) (735:735:735)) + (PORT datac (217:217:217) (294:294:294)) + (PORT datad (334:334:334) (353:353:353)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (446:446:446)) + (PORT datab (1227:1227:1227) (1282:1282:1282)) + (PORT datac (178:178:178) (215:215:215)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (1340:1340:1340) (1359:1359:1359)) + (PORT datad (533:533:533) (544:544:544)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (565:565:565) (575:575:575)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1592:1592:1592) (1568:1568:1568)) + (PORT ena (2023:2023:2023) (2039:2039:2039)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (680:680:680) (745:745:745)) + (PORT datab (1138:1138:1138) (1179:1179:1179)) + (PORT datac (669:669:669) (689:689:689)) + (PORT datad (1408:1408:1408) (1445:1445:1445)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (1399:1399:1399) (1450:1450:1450)) + (PORT datac (1371:1371:1371) (1414:1414:1414)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (678:678:678)) + (PORT datab (615:615:615) (637:637:637)) + (PORT datac (592:592:592) (659:659:659)) + (PORT datad (667:667:667) (730:730:730)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (1239:1239:1239) (1295:1295:1295)) + (PORT datac (880:880:880) (914:914:914)) + (PORT datad (215:215:215) (249:249:249)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (368:368:368)) + (PORT datab (707:707:707) (740:740:740)) + (PORT datac (1132:1132:1132) (1184:1184:1184)) + (PORT datad (367:367:367) (391:391:391)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (630:630:630)) + (PORT datab (412:412:412) (440:440:440)) + (PORT datac (542:542:542) (555:555:555)) + (PORT datad (611:611:611) (637:637:637)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (274:274:274)) + (PORT datab (1115:1115:1115) (1142:1142:1142)) + (PORT datac (844:844:844) (866:866:866)) + (PORT datad (341:341:341) (362:362:362)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (246:246:246) (300:300:300)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (572:572:572) (590:590:590)) + (PORT datad (193:193:193) (218:218:218)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (744:744:744) (833:833:833)) + (PORT datac (206:206:206) (244:244:244)) + (PORT datad (220:220:220) (248:248:248)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (945:945:945)) + (PORT datab (674:674:674) (710:710:710)) + (PORT datac (1356:1356:1356) (1400:1400:1400)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT asdata (889:889:889) (895:895:895)) + (PORT ena (1615:1615:1615) (1626:1626:1626)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (979:979:979)) + (PORT datab (1586:1586:1586) (1671:1671:1671)) + (PORT datac (857:857:857) (920:920:920)) + (PORT datad (419:419:419) (492:492:492)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (873:873:873)) + (PORT datab (262:262:262) (317:317:317)) + (PORT datac (849:849:849) (911:911:911)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (874:874:874)) + (PORT datab (880:880:880) (945:945:945)) + (PORT datad (741:741:741) (783:783:783)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (1309:1309:1309) (1365:1365:1365)) + (PORT datac (209:209:209) (249:249:249)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (999:999:999)) + (PORT datab (1075:1075:1075) (1142:1142:1142)) + (PORT datac (885:885:885) (962:962:962)) + (PORT datad (648:648:648) (680:680:680)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (726:726:726)) + (PORT datab (844:844:844) (863:863:863)) + (PORT datac (626:626:626) (661:661:661)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (724:724:724)) + (PORT datab (849:849:849) (909:909:909)) + (PORT datac (819:819:819) (834:834:834)) + (PORT datad (635:635:635) (671:671:671)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (625:625:625) (665:665:665)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (821:821:821) (834:834:834)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (458:458:458) (536:536:536)) + (PORT datab (592:592:592) (622:622:622)) + (PORT datac (651:651:651) (713:713:713)) + (PORT datad (832:832:832) (855:855:855)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (387:387:387)) + (PORT datac (200:200:200) (235:235:235)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~1) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (390:390:390)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (344:344:344) (373:373:373)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (719:719:719)) + (PORT datab (857:857:857) (902:902:902)) + (PORT datac (2037:2037:2037) (2075:2075:2075)) + (PORT datad (827:827:827) (920:920:920)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (953:953:953) (1017:1017:1017)) + (PORT datac (663:663:663) (701:701:701)) + (PORT datad (629:629:629) (658:658:658)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1608:1608:1608) (1638:1638:1638)) + (PORT datab (724:724:724) (761:761:761)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (970:970:970) (1003:1003:1003)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (450:450:450) (514:514:514)) + (PORT datab (266:266:266) (322:322:322)) + (PORT datad (605:605:605) (629:629:629)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (647:647:647)) + (PORT datab (587:587:587) (595:595:595)) + (PORT datac (850:850:850) (906:906:906)) + (PORT datad (176:176:176) (203:203:203)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (594:594:594)) + (PORT datab (227:227:227) (269:269:269)) + (PORT datac (843:843:843) (914:914:914)) + (PORT datad (777:777:777) (827:827:827)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (685:685:685) (729:729:729)) + (PORT datab (1152:1152:1152) (1160:1160:1160)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (538:538:538) (551:551:551)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1856:1856:1856) (1889:1889:1889)) + (PORT datab (205:205:205) (246:246:246)) + (PORT datac (885:885:885) (932:932:932)) + (PORT datad (330:330:330) (354:354:354)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1105:1105:1105) (1134:1134:1134)) + (PORT datab (1396:1396:1396) (1456:1456:1456)) + (PORT datac (796:796:796) (811:811:811)) + (PORT datad (563:563:563) (577:577:577)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (801:801:801) (823:823:823)) + (PORT datab (363:363:363) (394:394:394)) + (PORT datac (1051:1051:1051) (1079:1079:1079)) + (PORT datad (1041:1041:1041) (1076:1076:1076)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (268:268:268)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (601:601:601) (617:617:617)) + (PORT datad (589:589:589) (602:602:602)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (990:990:990)) + (PORT datab (932:932:932) (968:968:968)) + (PORT datac (1207:1207:1207) (1265:1265:1265)) + (PORT datad (620:620:620) (652:652:652)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (228:228:228) (269:269:269)) + (PORT datac (859:859:859) (877:877:877)) + (PORT datad (619:619:619) (659:659:659)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~14) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (288:288:288)) + (PORT datab (1534:1534:1534) (1581:1581:1581)) + (PORT datac (1206:1206:1206) (1250:1250:1250)) + (PORT datad (685:685:685) (739:739:739)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~13) + (DELAY + (ABSOLUTE + (PORT datac (186:186:186) (225:225:225)) + (PORT datad (191:191:191) (224:224:224)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~15) + (DELAY + (ABSOLUTE + (PORT dataa (800:800:800) (827:827:827)) + (PORT datab (362:362:362) (398:398:398)) + (PORT datac (521:521:521) (537:537:537)) + (PORT datad (812:812:812) (823:823:823)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~16) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (663:663:663)) + (PORT datab (666:666:666) (681:681:681)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (640:640:640)) + (PORT datab (1418:1418:1418) (1463:1463:1463)) + (PORT datac (1454:1454:1454) (1487:1487:1487)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1202:1202:1202) (1281:1281:1281)) + (PORT datab (1419:1419:1419) (1462:1462:1462)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (831:831:831) (848:848:848)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1013:1013:1013)) + (PORT datab (1181:1181:1181) (1227:1227:1227)) + (PORT datac (632:632:632) (648:648:648)) + (PORT datad (1362:1362:1362) (1411:1411:1411)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_set\~0) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (848:848:848)) + (PORT datab (1395:1395:1395) (1453:1453:1453)) + (PORT datac (1074:1074:1074) (1096:1096:1096)) + (PORT datad (1683:1683:1683) (1743:1743:1743)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M2T1_2) + (DELAY + (ABSOLUTE + (PORT dataa (1811:1811:1811) (1879:1879:1879)) + (PORT datab (676:676:676) (715:715:715)) + (PORT datac (1045:1045:1045) (1109:1109:1109)) + (PORT datad (333:333:333) (359:359:359)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (875:875:875)) + (PORT datab (631:631:631) (658:658:658)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (617:617:617) (665:665:665)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (570:570:570)) + (PORT datab (641:641:641) (662:662:662)) + (PORT datac (570:570:570) (588:588:588)) + (PORT datad (321:321:321) (344:344:344)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (946:946:946)) + (PORT datab (1101:1101:1101) (1148:1148:1148)) + (PORT datac (813:813:813) (870:870:870)) + (PORT datad (589:589:589) (601:601:601)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (943:943:943)) + (PORT datab (440:440:440) (502:502:502)) + (PORT datac (322:322:322) (346:346:346)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) + (DELAY + (ABSOLUTE + (PORT datab (956:956:956) (1019:1019:1019)) + (PORT datac (686:686:686) (722:722:722)) + (PORT datad (935:935:935) (962:962:962)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (710:710:710)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (616:616:616) (639:639:639)) + (PORT datad (1569:1569:1569) (1593:1593:1593)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (879:879:879)) + (PORT datab (204:204:204) (245:245:245)) + (PORT datac (222:222:222) (303:303:303)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (880:880:880)) + (PORT datab (350:350:350) (384:384:384)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1571:1571:1571) (1597:1597:1597)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1404:1404:1404) (1572:1572:1572)) + (PORT datab (2576:2576:2576) (2768:2768:2768)) + (PORT datac (1211:1211:1211) (1292:1292:1292)) + (PORT datad (1321:1321:1321) (1487:1487:1487)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) + (DELAY + (ABSOLUTE + (PORT dataa (402:402:402) (436:436:436)) + (PORT datab (642:642:642) (698:698:698)) + (PORT datac (1721:1721:1721) (1770:1770:1770)) + (PORT datad (842:842:842) (847:847:847)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (688:688:688)) + (PORT datab (673:673:673) (705:705:705)) + (PORT datad (1121:1121:1121) (1149:1149:1149)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1852:1852:1852) (1960:1960:1960)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (811:811:811) (834:834:834)) + (PORT datad (1186:1186:1186) (1218:1218:1218)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1152:1152:1152)) + (PORT datab (850:850:850) (888:888:888)) + (PORT datac (1161:1161:1161) (1194:1194:1194)) + (PORT datad (1113:1113:1113) (1135:1135:1135)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (340:340:340)) + (PORT datab (260:260:260) (342:342:342)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (853:853:853) (853:853:853)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) + (DELAY + (ABSOLUTE + (PORT dataa (993:993:993) (1071:1071:1071)) + (PORT datab (877:877:877) (903:903:903)) + (PORT datac (1043:1043:1043) (1136:1136:1136)) + (PORT datad (1269:1269:1269) (1356:1356:1356)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) + (DELAY + (ABSOLUTE + (PORT dataa (240:240:240) (283:283:283)) + (PORT datab (1397:1397:1397) (1493:1493:1493)) + (PORT datac (1951:1951:1951) (2029:2029:2029)) + (PORT datad (909:909:909) (935:935:935)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (255:255:255)) + (PORT datab (994:994:994) (1065:1065:1065)) + (PORT datac (1181:1181:1181) (1238:1238:1238)) + (PORT datad (1433:1433:1433) (1519:1519:1519)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1149:1149:1149) (1166:1166:1166)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (638:638:638) (669:669:669)) + (PORT datad (883:883:883) (915:915:915)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (689:689:689)) + (PORT datab (1238:1238:1238) (1272:1272:1272)) + (PORT datac (185:185:185) (224:224:224)) + (PORT datad (633:633:633) (665:665:665)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (665:665:665)) + (PORT datab (628:628:628) (640:640:640)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (320:320:320) (341:341:341)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal64\~0) + (DELAY + (ABSOLUTE + (PORT datac (962:962:962) (1026:1026:1026)) + (PORT datad (841:841:841) (860:860:860)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~1) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (629:629:629) (639:639:639)) + (PORT datac (207:207:207) (246:246:246)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (941:941:941)) + (PORT datab (1982:1982:1982) (2090:2090:2090)) + (PORT datac (1348:1348:1348) (1372:1372:1372)) + (PORT datad (2100:2100:2100) (2296:2296:2296)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (906:906:906)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (217:217:217) (260:260:260)) + (PORT datad (196:196:196) (229:229:229)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (914:914:914)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (1205:1205:1205) (1266:1266:1266)) + (PORT datad (904:904:904) (932:932:932)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (256:256:256)) + (PORT datab (1175:1175:1175) (1240:1240:1240)) + (PORT datad (184:184:184) (215:215:215)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1245:1245:1245) (1307:1307:1307)) + (PORT datab (684:684:684) (724:724:724)) + (PORT datac (794:794:794) (837:837:837)) + (PORT datad (1662:1662:1662) (1693:1693:1693)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (607:607:607)) + (PORT datab (815:815:815) (829:829:829)) + (PORT datac (585:585:585) (610:610:610)) + (PORT datad (651:651:651) (668:668:668)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (673:673:673) (690:690:690)) + (PORT datac (346:346:346) (370:370:370)) + (PORT datad (619:619:619) (643:643:643)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1355:1355:1355) (1407:1407:1407)) + (PORT datab (927:927:927) (984:984:984)) + (PORT datac (1048:1048:1048) (1096:1096:1096)) + (PORT datad (1421:1421:1421) (1444:1444:1444)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (401:401:401)) + (PORT datab (629:629:629) (655:655:655)) + (PORT datac (191:191:191) (224:224:224)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (693:693:693) (730:730:730)) + (PORT datab (988:988:988) (1020:1020:1020)) + (PORT datac (2018:2018:2018) (2126:2126:2126)) + (PORT datad (326:326:326) (345:345:345)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) + (DELAY + (ABSOLUTE + (PORT datab (806:806:806) (826:826:826)) + (PORT datac (215:215:215) (257:257:257)) + (PORT datad (831:831:831) (857:857:857)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (345:345:345) (376:376:376)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (613:613:613) (625:625:625)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_cf) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (648:648:648)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (575:575:575) (577:577:577)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1117:1117:1117) (1153:1153:1153)) + (PORT datab (1198:1198:1198) (1239:1239:1239)) + (PORT datac (1173:1173:1173) (1228:1228:1228)) + (PORT datad (1368:1368:1368) (1397:1397:1397)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1134:1134:1134) (1151:1151:1151)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (202:202:202) (239:239:239)) + (PORT datad (528:528:528) (546:546:546)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) + (DELAY + (ABSOLUTE + (PORT datab (847:847:847) (854:854:854)) + (PORT datac (1082:1082:1082) (1133:1133:1133)) + (PORT datad (828:828:828) (834:834:834)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (829:829:829)) + (PORT datab (897:897:897) (933:933:933)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~9) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (965:965:965)) + (PORT datab (912:912:912) (924:924:924)) + (PORT datac (1409:1409:1409) (1449:1449:1449)) + (PORT datad (873:873:873) (900:900:900)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1222:1222:1222) (1258:1258:1258)) + (PORT datab (887:887:887) (920:920:920)) + (PORT datac (1132:1132:1132) (1158:1158:1158)) + (PORT datad (950:950:950) (979:979:979)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1201:1201:1201) (1284:1284:1284)) + (PORT datab (1418:1418:1418) (1466:1466:1466)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (532:532:532) (548:548:548)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (702:702:702)) + (PORT datab (652:652:652) (733:733:733)) + (PORT datac (1060:1060:1060) (1092:1092:1092)) + (PORT datad (543:543:543) (547:547:547)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (722:722:722) (746:746:746)) + (PORT datab (1346:1346:1346) (1366:1366:1366)) + (PORT datac (956:956:956) (1016:1016:1016)) + (PORT datad (374:374:374) (392:392:392)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (252:252:252)) + (PORT datab (1175:1175:1175) (1216:1216:1216)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (590:590:590) (618:618:618)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (606:606:606)) + (PORT datab (829:829:829) (843:843:843)) + (PORT datac (563:563:563) (578:578:578)) + (PORT datad (562:562:562) (578:578:578)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1024:1024:1024) (1052:1052:1052)) + (PORT ena (984:984:984) (983:983:983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1024:1024:1024) (1053:1053:1053)) + (PORT ena (923:923:923) (907:907:907)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (464:464:464)) + (PORT datab (450:450:450) (485:485:485)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1198:1198:1198) (1257:1257:1257)) + (PORT datab (852:852:852) (879:879:879)) + (PORT datad (594:594:594) (619:619:619)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1191:1191:1191) (1216:1216:1216)) + (PORT ena (1248:1248:1248) (1256:1256:1256)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1010:1010:1010) (1041:1041:1041)) + (PORT ena (1712:1712:1712) (1752:1752:1752)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (1012:1012:1012) (1044:1044:1044)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (264:264:264) (329:329:329)) + (PORT datab (1408:1408:1408) (1522:1522:1522)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (681:681:681) (743:743:743)) + (PORT datad (608:608:608) (631:631:631)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT asdata (969:969:969) (995:995:995)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1189:1189:1189) (1215:1215:1215)) + (PORT ena (1275:1275:1275) (1314:1314:1314)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (787:787:787)) + (PORT datab (725:725:725) (775:775:775)) + (PORT datad (1020:1020:1020) (1061:1061:1061)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1197:1197:1197) (1218:1218:1218)) + (PORT ena (1147:1147:1147) (1143:1143:1143)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (1195:1195:1195) (1219:1219:1219)) + (PORT ena (1248:1248:1248) (1262:1262:1262)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (667:667:667)) + (PORT datab (947:947:947) (1004:1004:1004)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1168:1168:1168) (1161:1161:1161)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (697:697:697)) + (PORT datab (636:636:636) (670:670:670)) + (PORT datac (376:376:376) (420:420:420)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (811:811:811) (832:832:832)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (638:638:638) (670:670:670)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1182:1182:1182) (1199:1199:1199)) + (PORT datac (1095:1095:1095) (1092:1092:1092)) + (PORT datad (659:659:659) (693:693:693)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1466:1466:1466) (1517:1517:1517)) + (PORT datab (670:670:670) (708:708:708)) + (PORT datad (839:839:839) (834:834:834)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (420:420:420) (480:480:480)) + (PORT datac (666:666:666) (693:693:693)) + (PORT datad (331:331:331) (347:347:347)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (422:422:422) (511:511:511)) + (PORT datad (201:201:201) (229:229:229)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (591:591:591)) + (PORT datab (244:244:244) (291:291:291)) + (PORT datac (1211:1211:1211) (1265:1265:1265)) + (PORT datad (625:625:625) (637:637:637)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[4\]) + (DELAY + (ABSOLUTE + (PORT dataa (1104:1104:1104) (1133:1133:1133)) + (PORT datad (860:860:860) (861:861:861)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1592:1592:1592) (1568:1568:1568)) + (PORT ena (2023:2023:2023) (2039:2039:2039)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) + (DELAY + (ABSOLUTE + (PORT dataa (419:419:419) (509:509:509)) + (PORT datab (392:392:392) (466:466:466)) + (PORT datac (243:243:243) (322:322:322)) + (PORT datad (237:237:237) (305:305:305)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) + (DELAY + (ABSOLUTE + (PORT dataa (455:455:455) (527:527:527)) + (PORT datab (420:420:420) (490:490:490)) + (PORT datac (392:392:392) (467:467:467)) + (PORT datad (239:239:239) (308:308:308)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1314:1314:1314) (1365:1365:1365)) + (PORT datab (705:705:705) (774:774:774)) + (PORT datac (594:594:594) (664:664:664)) + (PORT datad (239:239:239) (309:309:309)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) + (DELAY + (ABSOLUTE + (PORT dataa (425:425:425) (509:509:509)) + (PORT datab (411:411:411) (493:493:493)) + (PORT datac (550:550:550) (609:609:609)) + (PORT datad (376:376:376) (439:439:439)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (895:895:895)) + (PORT datab (822:822:822) (844:844:844)) + (PORT datac (609:609:609) (631:631:631)) + (PORT datad (629:629:629) (662:662:662)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1022:1022:1022) (1069:1069:1069)) + (PORT datab (684:684:684) (720:720:720)) + (PORT datad (623:623:623) (638:638:638)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1574:1574:1574) (1553:1553:1553)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (964:964:964) (1023:1023:1023)) + (PORT datab (637:637:637) (662:662:662)) + (PORT datac (843:843:843) (877:877:877)) + (PORT datad (636:636:636) (678:678:678)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal79\~0) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (631:631:631)) + (PORT datab (2626:2626:2626) (2719:2719:2719)) + (PORT datac (2090:2090:2090) (2263:2263:2263)) + (PORT datad (1434:1434:1434) (1452:1452:1452)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (581:581:581) (604:604:604)) + (PORT datab (608:608:608) (677:677:677)) + (PORT datad (1145:1145:1145) (1180:1180:1180)) + (IOPATH dataa combout (301:301:301) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (446:446:446)) + (PORT datac (721:721:721) (815:815:815)) + (PORT datad (268:268:268) (348:348:348)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1240:1240:1240) (1269:1269:1269)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1554:1554:1554) (1545:1545:1545)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (1364:1364:1364) (1421:1421:1421)) + (PORT datac (853:853:853) (901:901:901)) + (PORT datad (232:232:232) (309:309:309)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) + (DELAY + (ABSOLUTE + (PORT dataa (260:260:260) (352:352:352)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (983:983:983) (1029:1029:1029)) + (PORT datad (837:837:837) (875:875:875)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1021:1021:1021) (1068:1068:1068)) + (PORT datab (1361:1361:1361) (1418:1418:1418)) + (PORT datac (607:607:607) (631:631:631)) + (PORT datad (920:920:920) (974:974:974)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (914:914:914)) + (PORT datab (641:641:641) (700:700:700)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (636:636:636) (677:677:677)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1022:1022:1022) (1066:1066:1066)) + (PORT datab (2171:2171:2171) (2355:2355:2355)) + (PORT datac (1335:1335:1335) (1387:1387:1387)) + (PORT datad (1335:1335:1335) (1492:1492:1492)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1026:1026:1026) (1071:1071:1071)) + (PORT datab (932:932:932) (993:993:993)) + (PORT datac (607:607:607) (627:627:627)) + (PORT datad (837:837:837) (870:870:870)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (872:872:872) (918:918:918)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (636:636:636) (681:681:681)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (387:387:387)) + (PORT datab (258:258:258) (300:300:300)) + (PORT datac (364:364:364) (389:389:389)) + (PORT datad (575:575:575) (588:588:588)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1867:1867:1867) (1883:1883:1883)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (414:414:414)) + (PORT datab (355:355:355) (391:391:391)) + (PORT datac (321:321:321) (346:346:346)) + (PORT datad (193:193:193) (218:218:218)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out) + (DELAY + (ABSOLUTE + (PORT datab (1247:1247:1247) (1295:1295:1295)) + (PORT datad (788:788:788) (792:792:792)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (509:509:509) (518:518:518)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (473:473:473)) + (PORT datab (966:966:966) (1019:1019:1019)) + (PORT datac (957:957:957) (996:996:996)) + (PORT datad (930:930:930) (961:961:961)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) + (DELAY + (ABSOLUTE + (PORT dataa (961:961:961) (1008:1008:1008)) + (PORT datab (792:792:792) (810:810:810)) + (PORT datac (831:831:831) (846:846:846)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) + (DELAY + (ABSOLUTE + (PORT clk (1512:1512:1512) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1210:1210:1210) (1277:1277:1277)) + (PORT datab (1010:1010:1010) (1070:1070:1070)) + (PORT datac (1149:1149:1149) (1202:1202:1202)) + (PORT datad (1136:1136:1136) (1189:1189:1189)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (701:701:701)) + (PORT datab (228:228:228) (269:269:269)) + (PORT datac (538:538:538) (560:560:560)) + (PORT datad (348:348:348) (372:372:372)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) + (DELAY + (ABSOLUTE + (PORT dataa (843:843:843) (866:866:866)) + (PORT datab (626:626:626) (642:642:642)) + (PORT datac (556:556:556) (572:572:572)) + (PORT datad (542:542:542) (555:555:555)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11) + (DELAY + (ABSOLUTE + (PORT datab (1147:1147:1147) (1156:1156:1156)) + (PORT datac (312:312:312) (331:331:331)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (662:662:662)) + (PORT datab (1297:1297:1297) (1354:1354:1354)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (820:820:820) (839:839:839)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (699:699:699)) + (PORT datab (941:941:941) (1002:1002:1002)) + (PORT datac (1172:1172:1172) (1234:1234:1234)) + (PORT datad (786:786:786) (778:778:778)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (827:827:827)) + (PORT datab (677:677:677) (738:738:738)) + (PORT datac (656:656:656) (722:722:722)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) + (DELAY + (ABSOLUTE + (PORT dataa (679:679:679) (727:727:727)) + (PORT datab (986:986:986) (1058:1058:1058)) + (PORT datad (504:504:504) (504:504:504)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|flags_cond_true) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1310:1310:1310) (1360:1360:1360)) + (PORT datab (995:995:995) (1071:1071:1071)) + (PORT datac (1112:1112:1112) (1137:1137:1137)) + (PORT datad (1570:1570:1570) (1618:1618:1618)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1476:1476:1476) (1520:1520:1520)) + (PORT datab (1155:1155:1155) (1181:1181:1181)) + (PORT datac (1087:1087:1087) (1097:1097:1097)) + (PORT datad (600:600:600) (614:614:614)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (667:667:667)) + (PORT datab (227:227:227) (267:267:267)) + (PORT datac (613:613:613) (637:637:637)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) + (DELAY + (ABSOLUTE + (PORT dataa (963:963:963) (1037:1037:1037)) + (PORT datac (957:957:957) (1023:1023:1023)) + (PORT datad (1214:1214:1214) (1280:1280:1280)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (692:692:692)) + (PORT datab (1444:1444:1444) (1500:1500:1500)) + (PORT datac (590:590:590) (630:630:630)) + (PORT datad (582:582:582) (612:612:612)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (752:752:752) (788:788:788)) + (PORT ena (1203:1203:1203) (1189:1189:1189)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (690:690:690)) + (PORT datab (622:622:622) (668:668:668)) + (PORT datad (598:598:598) (635:635:635)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1185:1185:1185) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (581:581:581)) + (PORT datab (592:592:592) (627:627:627)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (474:474:474) (523:523:523)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1498:1498:1498) (1562:1562:1562)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[11\]) + (DELAY + (ABSOLUTE + (PORT datac (880:880:880) (938:938:938)) + (PORT datad (349:349:349) (365:365:365)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1580:1580:1580) (1560:1560:1560)) + (PORT ena (1783:1783:1783) (1814:1814:1814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) + (DELAY + (ABSOLUTE + (PORT datac (415:415:415) (481:481:481)) + (PORT datad (341:341:341) (363:363:363)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1176:1176:1176) (1262:1262:1262)) + (PORT datab (390:390:390) (410:410:410)) + (PORT datad (553:553:553) (555:555:555)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -29643,12 +31064,12 @@ (INSTANCE z80_\|execute_\|ctl_apin_mux2\~0) (DELAY (ABSOLUTE - (PORT dataa (949:949:949) (1028:1028:1028)) - (PORT datab (994:994:994) (1080:1080:1080)) - (PORT datac (1875:1875:1875) (2047:2047:2047)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (1382:1382:1382) (1568:1568:1568)) + (PORT datac (1328:1328:1328) (1469:1469:1469)) + (PORT datad (2533:2533:2533) (2621:2621:2621)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -29657,13 +31078,13 @@ (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~2) (DELAY (ABSOLUTE - (PORT dataa (1686:1686:1686) (1827:1827:1827)) - (PORT datab (974:974:974) (1024:1024:1024)) - (PORT datac (941:941:941) (1003:1003:1003)) - (PORT datad (1201:1201:1201) (1259:1259:1259)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1134:1134:1134) (1163:1163:1163)) + (PORT datab (924:924:924) (979:979:979)) + (PORT datac (820:820:820) (846:846:846)) + (PORT datad (1655:1655:1655) (1830:1830:1830)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -29673,653 +31094,13 @@ (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~3) (DELAY (ABSOLUTE - (PORT dataa (948:948:948) (1027:1027:1027)) - (PORT datab (994:994:994) (1080:1080:1080)) - (PORT datac (1875:1875:1875) (2047:2047:2047)) - (PORT datad (622:622:622) (660:660:660)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (603:603:603) (689:689:689)) - (PORT sload (1125:1125:1125) (1169:1169:1169)) - (PORT ena (1155:1155:1155) (1129:1129:1129)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[13\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1195:1195:1195) (1254:1254:1254)) - (PORT datad (2019:2019:2019) (2140:2140:2140)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1794:1794:1794) (1807:1807:1807)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datad (320:320:320) (334:334:334)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (590:590:590) (668:668:668)) - (PORT sload (1125:1125:1125) (1169:1169:1169)) - (PORT ena (1155:1155:1155) (1129:1129:1129)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[14\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (2045:2045:2045) (2178:2178:2178)) - (PORT datad (1147:1147:1147) (1202:1202:1202)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1796:1796:1796) (1810:1810:1810)) - (PORT datab (337:337:337) (371:371:371)) - (PORT datad (554:554:554) (561:561:561)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (577:577:577) (658:658:658)) - (PORT sload (1125:1125:1125) (1169:1169:1169)) - (PORT ena (1155:1155:1155) (1129:1129:1129)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[15\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (1641:1641:1641) (1729:1729:1729)) - (PORT datac (1584:1584:1584) (1634:1634:1634)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (725:725:725)) - (PORT datab (261:261:261) (314:314:314)) - (PORT datac (366:366:366) (404:404:404)) - (PORT datad (1304:1304:1304) (1296:1296:1296)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (2037:2037:2037) (2174:2174:2174)) - (PORT datac (1153:1153:1153) (1208:1208:1208)) - (PORT datad (1144:1144:1144) (1203:1203:1203)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (971:971:971)) - (PORT datad (1987:1987:1987) (2083:2083:2083)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (854:854:854) (879:879:879)) - (PORT datab (373:373:373) (396:396:396)) - (PORT datad (334:334:334) (343:343:343)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1128:1128:1128) (1174:1174:1174)) - (PORT sload (1213:1213:1213) (1283:1283:1283)) - (PORT ena (1456:1456:1456) (1440:1440:1440)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1793:1793:1793) (1909:1909:1909)) - (PORT datad (678:678:678) (733:733:733)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (855:855:855) (880:880:880)) - (PORT datab (604:604:604) (620:620:620)) - (PORT datad (532:532:532) (544:544:544)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (992:992:992) (1045:1045:1045)) - (PORT sload (1213:1213:1213) (1283:1283:1283)) - (PORT ena (1456:1456:1456) (1440:1440:1440)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) - (DELAY - (ABSOLUTE - (PORT datac (1749:1749:1749) (1862:1862:1862)) - (PORT datad (642:642:642) (699:699:699)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (887:887:887)) - (PORT datab (535:535:535) (551:551:551)) - (PORT datad (339:339:339) (355:355:355)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (751:751:751) (807:807:807)) - (PORT sload (1213:1213:1213) (1283:1283:1283)) - (PORT ena (1456:1456:1456) (1440:1440:1440)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) - (DELAY - (ABSOLUTE - (PORT datac (1754:1754:1754) (1872:1872:1872)) - (PORT datad (367:367:367) (429:429:429)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (853:853:853) (880:880:880)) - (PORT datab (534:534:534) (559:559:559)) - (PORT datad (339:339:339) (357:357:357)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (979:979:979) (1031:1031:1031)) - (PORT sload (1213:1213:1213) (1283:1283:1283)) - (PORT ena (1456:1456:1456) (1440:1440:1440)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) - (DELAY - (ABSOLUTE - (PORT datac (1758:1758:1758) (1874:1874:1874)) - (PORT datad (652:652:652) (710:710:710)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1351:1351:1351) (1385:1385:1385)) - (PORT datab (337:337:337) (371:371:371)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1019:1019:1019) (1078:1078:1078)) - (PORT sload (1150:1150:1150) (1218:1218:1218)) - (PORT ena (1176:1176:1176) (1166:1166:1166)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) - (DELAY - (ABSOLUTE - (PORT datab (2021:2021:2021) (2124:2124:2124)) - (PORT datac (676:676:676) (743:743:743)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datad (1323:1323:1323) (1343:1343:1343)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1156:1156:1156) (1209:1209:1209)) - (PORT sload (1150:1150:1150) (1218:1218:1218)) - (PORT ena (1176:1176:1176) (1166:1166:1166)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) - (DELAY - (ABSOLUTE - (PORT datab (696:696:696) (759:759:759)) - (PORT datac (1750:1750:1750) (1863:1863:1863)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1354:1354:1354) (1387:1387:1387)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1639:1639:1639) (1657:1657:1657)) - (PORT sload (1150:1150:1150) (1218:1218:1218)) - (PORT ena (1176:1176:1176) (1166:1166:1166)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) - (DELAY - (ABSOLUTE - (PORT datac (1748:1748:1748) (1867:1867:1867)) - (PORT datad (927:927:927) (1010:1010:1010)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (380:380:380)) - (PORT datab (1361:1361:1361) (1369:1369:1369)) - (PORT datad (196:196:196) (222:222:222)) + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1914:1914:1914) (2085:2085:2085)) + (PORT datac (2116:2116:2116) (2227:2227:2227)) + (PORT datad (1650:1650:1650) (1834:1834:1834)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (597:597:597) (678:678:678)) - (PORT sload (1150:1150:1150) (1218:1218:1218)) - (PORT ena (1176:1176:1176) (1166:1166:1166)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) - (DELAY - (ABSOLUTE - (PORT datab (948:948:948) (1009:1009:1009)) - (PORT datad (2008:2008:2008) (2130:2130:2130)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1391:1391:1391) (1422:1422:1422)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datad (552:552:552) (561:561:561)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (591:591:591) (677:677:677)) - (PORT sload (1117:1117:1117) (1168:1168:1168)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) - (DELAY - (ABSOLUTE - (PORT datac (1757:1757:1757) (1868:1868:1868)) - (PORT datad (678:678:678) (737:737:737)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (567:567:567) (585:585:585)) - (PORT datad (1365:1365:1365) (1379:1379:1379)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (580:580:580) (668:668:668)) - (PORT sload (1117:1117:1117) (1168:1168:1168)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[10\]\~24) - (DELAY - (ABSOLUTE - (PORT datac (910:910:910) (972:972:972)) - (PORT datad (1442:1442:1442) (1565:1565:1565)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (197:197:197) (234:234:234)) - (PORT datad (1362:1362:1362) (1374:1374:1374)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -30329,11 +31110,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT clk (1529:1529:1529) (1534:1534:1534)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (913:913:913) (972:972:972)) - (PORT sload (1117:1117:1117) (1168:1168:1168)) - (PORT ena (811:811:811) (804:804:804)) + (PORT asdata (1184:1184:1184) (1229:1229:1229)) + (PORT sload (1432:1432:1432) (1514:1514:1514)) + (PORT ena (1459:1459:1459) (1480:1480:1480)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -30349,37 +31130,37 @@ (INSTANCE z80_\|address_pins_\|abus\[11\]\~19) (DELAY (ABSOLUTE - (PORT dataa (942:942:942) (1010:1010:1010)) - (PORT datad (1442:1442:1442) (1566:1566:1566)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT datac (1399:1399:1399) (1483:1483:1483)) + (PORT datad (1955:1955:1955) (2153:2153:2153)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) (DELAY (ABSOLUTE - (PORT dataa (340:340:340) (375:375:375)) - (PORT datab (816:816:816) (834:834:834)) - (PORT datad (1561:1561:1561) (1571:1571:1571)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (1180:1180:1180) (1258:1258:1258)) + (PORT datab (195:195:195) (234:234:234)) + (PORT datad (566:566:566) (578:578:578)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) (DELAY (ABSOLUTE (PORT clk (1529:1529:1529) (1534:1534:1534)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (583:583:583) (667:667:667)) - (PORT sload (1125:1125:1125) (1169:1169:1169)) - (PORT ena (1155:1155:1155) (1129:1129:1129)) + (PORT asdata (753:753:753) (819:819:819)) + (PORT sload (1432:1432:1432) (1514:1514:1514)) + (PORT ena (1459:1459:1459) (1480:1480:1480)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -30392,206 +31173,205 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[12\]\~21) + (INSTANCE z80_\|address_pins_\|abus\[10\]\~20) (DELAY (ABSOLUTE - (PORT dataa (1791:1791:1791) (1903:1903:1903)) - (PORT datad (854:854:854) (913:913:913)) + (PORT dataa (2315:2315:2315) (2530:2530:2530)) + (PORT datad (1404:1404:1404) (1520:1520:1520)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~19) (DELAY (ABSOLUTE - (PORT d[0] (1010:1010:1010) (1062:1062:1062)) - (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT dataa (303:303:303) (420:420:420)) + (PORT datac (915:915:915) (973:973:973)) + (PORT datad (643:643:643) (704:704:704)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1009:1009:1009) (1047:1047:1047)) - (PORT d[1] (2076:2076:2076) (2305:2305:2305)) - (PORT d[2] (1463:1463:1463) (1514:1514:1514)) - (PORT d[3] (2867:2867:2867) (3072:3072:3072)) - (PORT d[4] (2625:2625:2625) (2841:2841:2841)) - (PORT d[5] (3152:3152:3152) (3353:3353:3353)) - (PORT d[6] (1368:1368:1368) (1453:1453:1453)) - (PORT d[7] (2906:2906:2906) (3079:3079:3079)) - (PORT d[8] (997:997:997) (1014:1014:1014)) - (PORT d[9] (1597:1597:1597) (1654:1654:1654)) - (PORT d[10] (1607:1607:1607) (1695:1695:1695)) - (PORT d[11] (2235:2235:2235) (2380:2380:2380)) - (PORT d[12] (1610:1610:1610) (1712:1712:1712)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (958:958:958) (934:934:934)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1883:1883:1883)) - (PORT d[0] (1472:1472:1472) (1458:1458:1458)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1816:1816:1816) (1842:1842:1842)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1896:1896:1896) (1918:1918:1918)) - (PORT asdata (2035:2035:2035) (2085:2085:2085)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT asdata (1451:1451:1451) (1488:1488:1488)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~48) (DELAY (ABSOLUTE - (PORT dataa (697:697:697) (725:725:725)) - (PORT datab (262:262:262) (316:316:316)) - (PORT datac (367:367:367) (405:405:405)) - (PORT datad (1303:1303:1303) (1300:1300:1300)) + (PORT dataa (617:617:617) (640:640:640)) + (PORT datab (1304:1304:1304) (1358:1358:1358)) + (PORT datac (728:728:728) (812:812:812)) + (PORT datad (618:618:618) (638:638:638)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (436:436:436)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datad (187:187:187) (218:218:218)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (716:716:716)) + (PORT datab (2772:2772:2772) (2956:2956:2956)) + (PORT datac (648:648:648) (682:682:682)) + (PORT datad (637:637:637) (706:706:706)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (276:276:276) (367:367:367)) + (PORT datab (955:955:955) (1021:1021:1021)) + (PORT datac (1004:1004:1004) (1065:1065:1065)) + (PORT datad (262:262:262) (340:340:340)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1065:1065:1065) (1138:1138:1138)) + (PORT datac (266:266:266) (360:360:360)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (299:299:299) (419:419:419)) + (PORT datac (911:911:911) (974:974:974)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1228:1228:1228) (1254:1254:1254)) + (PORT datac (699:699:699) (766:766:766)) + (PORT datad (614:614:614) (688:688:688)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~3) + (DELAY + (ABSOLUTE + (PORT dataa (786:786:786) (869:869:869)) + (PORT datab (336:336:336) (364:364:364)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|shifted) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~62) + (DELAY + (ABSOLUTE + (PORT datab (772:772:772) (854:854:854)) + (PORT datac (461:461:461) (534:534:534)) + (PORT datad (928:928:928) (988:988:988)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1002:1002:1002) (1071:1071:1071)) + (PORT datab (656:656:656) (730:730:730)) + (PORT datac (702:702:702) (766:766:766)) + (PORT datad (1186:1186:1186) (1205:1205:1205)) (IOPATH dataa combout (303:303:303) (299:299:299)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -30601,208 +31381,909 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~63) (DELAY (ABSOLUTE - (PORT datab (2042:2042:2042) (2178:2178:2178)) - (PORT datac (1154:1154:1154) (1211:1211:1211)) - (PORT datad (1145:1145:1145) (1206:1206:1206)) + (PORT dataa (1000:1000:1000) (1062:1062:1062)) + (PORT datab (770:770:770) (851:851:851)) + (PORT datac (697:697:697) (772:772:772)) + (PORT datad (969:969:969) (1035:1035:1035)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (748:748:748) (838:838:838)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (259:259:259)) + (PORT datab (562:562:562) (579:579:579)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1520:1520:1520)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datad (1121:1121:1121) (1187:1187:1187)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (895:895:895) (951:951:951)) + (PORT sload (1199:1199:1199) (1277:1277:1277)) + (PORT ena (1447:1447:1447) (1469:1469:1469)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[15\]\~21) + (DELAY + (ABSOLUTE + (PORT datac (1681:1681:1681) (1850:1850:1850)) + (PORT datad (2616:2616:2616) (2812:2812:2812)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (350:350:350) (377:377:377)) + (PORT datad (1120:1120:1120) (1184:1184:1184)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (928:928:928) (977:977:977)) + (PORT sload (1199:1199:1199) (1277:1277:1277)) + (PORT ena (1447:1447:1447) (1469:1469:1469)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[14\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (2421:2421:2421) (2631:2631:2631)) + (PORT datad (1663:1663:1663) (1788:1788:1788)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (1293:1293:1293) (1369:1369:1369)) + (PORT datac (707:707:707) (797:797:797)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (871:871:871)) + (PORT datab (699:699:699) (763:763:763)) + (PORT datac (704:704:704) (770:770:770)) + (PORT datad (183:183:183) (213:213:213)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT datac (680:680:680) (750:750:750)) + (PORT datad (740:740:740) (823:823:823)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (817:817:817)) + (PORT datab (1292:1292:1292) (1364:1364:1364)) + (PORT datac (707:707:707) (793:793:793)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (213:213:213) (256:256:256)) + (PORT datac (762:762:762) (842:842:842)) + (PORT datad (206:206:206) (236:236:236)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (298:298:298) (396:396:396)) + (PORT datac (848:848:848) (867:867:867)) + (PORT datad (709:709:709) (783:783:783)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (757:757:757)) + (PORT datac (984:984:984) (1047:1047:1047)) + (PORT datad (652:652:652) (732:732:732)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (942:942:942)) + (PORT datab (605:605:605) (646:646:646)) + (PORT datad (184:184:184) (214:214:214)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1511:1511:1511) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1538:1538:1538)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (712:712:712)) + (PORT datab (1468:1468:1468) (1492:1492:1492)) + (PORT datac (912:912:912) (969:969:969)) + (PORT datad (362:362:362) (421:421:421)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (220:220:220) (258:258:258)) + (PORT datad (1120:1120:1120) (1184:1184:1184)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (726:726:726) (799:799:799)) + (PORT sload (1199:1199:1199) (1277:1277:1277)) + (PORT ena (1447:1447:1447) (1469:1469:1469)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[12\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (1811:1811:1811) (1928:1928:1928)) + (PORT datac (2265:2265:2265) (2463:2463:2463)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (397:397:397)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datad (1124:1124:1124) (1188:1188:1188)) + (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (741:741:741) (815:815:815)) + (PORT sload (1199:1199:1199) (1277:1277:1277)) + (PORT ena (1447:1447:1447) (1469:1469:1469)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (436:436:436)) + (PORT datab (764:764:764) (853:853:853)) + (PORT datac (695:695:695) (784:784:784)) + (PORT datad (346:346:346) (371:371:371)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~54) (DELAY (ABSOLUTE - (PORT d[0] (991:991:991) (1045:1045:1045)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1010:1010:1010) (1048:1048:1048)) - (PORT d[1] (2092:2092:2092) (2316:2316:2316)) - (PORT d[2] (3345:3345:3345) (3458:3458:3458)) - (PORT d[3] (2859:2859:2859) (3062:3062:3062)) - (PORT d[4] (2566:2566:2566) (2775:2775:2775)) - (PORT d[5] (3169:3169:3169) (3393:3393:3393)) - (PORT d[6] (1618:1618:1618) (1695:1695:1695)) - (PORT d[7] (2898:2898:2898) (3057:3057:3057)) - (PORT d[8] (1024:1024:1024) (1046:1046:1046)) - (PORT d[9] (3241:3241:3241) (3372:3372:3372)) - (PORT d[10] (1642:1642:1642) (1735:1735:1735)) - (PORT d[11] (1916:1916:1916) (2070:2070:2070)) - (PORT d[12] (1870:1870:1870) (1971:1971:1971)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (950:950:950) (925:925:925)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1881:1881:1881)) - (PORT d[0] (1713:1713:1713) (1683:1683:1683)) + (PORT datab (426:426:426) (500:500:500)) + (PORT datac (745:745:745) (821:821:821)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~55) (DELAY (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1840:1840:1840)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1003:1003:1003)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + (PORT dataa (211:211:211) (259:259:259)) + (PORT datab (769:769:769) (850:850:850)) + (PORT datad (176:176:176) (203:203:203)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT asdata (1470:1470:1470) (1518:1518:1518)) + (PORT clk (1506:1506:1506) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1546:1546:1546) (1539:1539:1539)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~1) + (DELAY + (ABSOLUTE + (PORT datab (1971:1971:1971) (2134:2134:2134)) + (PORT datac (2268:2268:2268) (2463:2463:2463)) + (PORT datad (668:668:668) (730:730:730)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~127) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (1011:1011:1011)) + (PORT datab (983:983:983) (1055:1055:1055)) + (PORT datad (204:204:204) (233:233:233)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (1032:1032:1032) (1104:1104:1104)) + (PORT datab (287:287:287) (378:378:378)) + (PORT datac (245:245:245) (328:328:328)) + (PORT datad (709:709:709) (788:788:788)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~128) + (DELAY + (ABSOLUTE + (PORT dataa (1066:1066:1066) (1139:1139:1139)) + (PORT datab (956:956:956) (1026:1026:1026)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (436:436:436)) + (PORT datab (631:631:631) (655:655:655)) + (PORT datad (794:794:794) (817:817:817)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (230:230:230) (272:272:272)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (634:634:634) (705:705:705)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT datac (2534:2534:2534) (2773:2773:2773)) + (PORT datad (1184:1184:1184) (1290:1290:1290)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (736:736:736) (825:825:825)) + (PORT datab (932:932:932) (1013:1013:1013)) + (PORT datac (754:754:754) (837:837:837)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (992:992:992)) + (PORT datab (738:738:738) (804:804:804)) + (PORT datac (695:695:695) (782:782:782)) + (PORT datad (355:355:355) (387:387:387)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (217:217:217) (263:263:263)) + (PORT datac (471:471:471) (550:550:550)) + (PORT datad (633:633:633) (650:650:650)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~46) + (DELAY + (ABSOLUTE + (PORT datab (500:500:500) (572:572:572)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1504:1504:1504) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (728:728:728) (813:813:813)) + (PORT datad (750:750:750) (828:828:828)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (441:441:441)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datad (188:188:188) (220:220:220)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1176:1176:1176) (1258:1258:1258)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datad (319:319:319) (337:337:337)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (736:736:736) (808:808:808)) + (PORT sload (1432:1432:1432) (1514:1514:1514)) + (PORT ena (1459:1459:1459) (1480:1480:1480)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (2312:2312:2312) (2526:2526:2526)) + (PORT datad (1425:1425:1425) (1538:1538:1538)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1176:1176:1176) (1257:1257:1257)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT asdata (706:706:706) (770:770:770)) + (PORT clk (1529:1529:1529) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (734:734:734) (795:795:795)) + (PORT sload (1432:1432:1432) (1514:1514:1514)) + (PORT ena (1459:1459:1459) (1480:1480:1480)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (931:931:931) (1029:1029:1029)) + (PORT datad (2391:2391:2391) (2584:2584:2584)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (785:785:785)) + (PORT datab (676:676:676) (757:757:757)) + (PORT datac (673:673:673) (715:715:715)) + (PORT datad (1494:1494:1494) (1586:1586:1586)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (2355:2355:2355) (2578:2578:2578)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1533:1533:1533)) + (PORT asdata (569:569:569) (649:649:649)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) (TIMINGCHECK (HOLD asdata (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (232:232:232) (306:306:306)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|control_pins_\|pin_nIORQ\~1) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (916:916:916)) + (PORT datab (249:249:249) (333:333:333)) + (PORT datac (994:994:994) (1049:1049:1049)) + (PORT datad (230:230:230) (303:303:303)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2634:2634:2634) (2764:2764:2764)) + (PORT datab (1939:1939:1939) (2080:2080:2080)) + (PORT datac (2770:2770:2770) (3002:3002:3002)) + (PORT datad (2212:2212:2212) (2284:2284:2284)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[13\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (1973:1973:1973) (2138:2138:2138)) + (PORT datac (2265:2265:2265) (2462:2462:2462)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ExtRamWE\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2634:2634:2634) (2769:2769:2769)) + (PORT datab (1937:1937:1937) (2082:2082:2082)) + (PORT datac (2770:2770:2770) (3003:3003:3003)) + (PORT datad (2214:2214:2214) (2287:2287:2287)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (700:700:700) (726:726:726)) - (PORT datab (266:266:266) (319:319:319)) - (PORT datac (371:371:371) (404:404:404)) - (PORT datad (1304:1304:1304) (1295:1295:1295)) + (PORT dataa (409:409:409) (462:462:462)) + (PORT datab (1257:1257:1257) (1295:1295:1295)) + (PORT datac (1233:1233:1233) (1265:1265:1265)) + (PORT datad (1391:1391:1391) (1417:1417:1417)) (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -30815,21 +32296,2740 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) (DELAY (ABSOLUTE - (PORT datab (2038:2038:2038) (2171:2171:2171)) - (PORT datac (1153:1153:1153) (1206:1206:1206)) - (PORT datad (1143:1143:1143) (1202:1202:1202)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (1921:1921:1921) (2116:2116:2116)) + (PORT datac (1982:1982:1982) (2198:2198:2198)) + (PORT datad (1426:1426:1426) (1533:1533:1533)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (253:253:253)) + (PORT datab (616:616:616) (630:630:630)) + (PORT datad (908:908:908) (944:944:944)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (995:995:995) (1050:1050:1050)) + (PORT sload (1199:1199:1199) (1276:1276:1276)) + (PORT ena (1212:1212:1212) (1237:1237:1237)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (2422:2422:2422) (2631:2631:2631)) + (PORT datac (1069:1069:1069) (1151:1151:1151)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1695:1695:1695) (1773:1773:1773)) + (PORT datad (325:325:325) (351:351:351)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (938:938:938) (1005:1005:1005)) + (PORT sload (1638:1638:1638) (1687:1687:1687)) + (PORT ena (1450:1450:1450) (1447:1447:1447)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1175:1175:1175) (1227:1227:1227)) + (PORT datad (2391:2391:2391) (2584:2584:2584)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (891:891:891)) + (PORT datab (1716:1716:1716) (1784:1784:1784)) + (PORT datad (875:875:875) (908:908:908)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (1270:1270:1270) (1328:1328:1328)) + (PORT sload (1357:1357:1357) (1408:1408:1408)) + (PORT ena (1406:1406:1406) (1406:1406:1406)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (264:264:264) (345:345:345)) + (PORT datad (2385:2385:2385) (2578:2578:2578)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (267:267:267)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datad (1658:1658:1658) (1733:1733:1733)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (899:899:899) (959:959:959)) + (PORT sload (1638:1638:1638) (1687:1687:1687)) + (PORT ena (1450:1450:1450) (1447:1447:1447)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (282:282:282) (364:364:364)) + (PORT datad (377:377:377) (439:439:439)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1695:1695:1695) (1769:1769:1769)) + (PORT datad (195:195:195) (219:219:219)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (959:959:959) (1008:1008:1008)) + (PORT sload (1638:1638:1638) (1687:1687:1687)) + (PORT ena (1450:1450:1450) (1447:1447:1447)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) + (DELAY + (ABSOLUTE + (PORT datac (1237:1237:1237) (1358:1358:1358)) + (PORT datad (2381:2381:2381) (2572:2572:2572)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (561:561:561)) + (PORT datab (1692:1692:1692) (1769:1769:1769)) + (PORT datad (316:316:316) (329:329:329)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1542:1542:1542) (1543:1543:1543)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (588:588:588) (666:666:666)) + (PORT sload (1638:1638:1638) (1687:1687:1687)) + (PORT ena (1450:1450:1450) (1447:1447:1447)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) + (DELAY + (ABSOLUTE + (PORT datac (1495:1495:1495) (1601:1601:1601)) + (PORT datad (2387:2387:2387) (2578:2578:2578)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1071:1071:1071) (1094:1094:1094)) + (PORT datab (898:898:898) (948:948:948)) + (PORT datad (1691:1691:1691) (1747:1747:1747)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (1266:1266:1266) (1347:1347:1347)) + (PORT sload (1357:1357:1357) (1408:1408:1408)) + (PORT ena (1406:1406:1406) (1406:1406:1406)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (2419:2419:2419) (2625:2625:2625)) + (PORT datac (245:245:245) (324:324:324)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1325:1325:1325) (1393:1393:1393)) + (PORT clk (1847:1847:1847) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2362:2362:2362) (2570:2570:2570)) + (PORT d[1] (2582:2582:2582) (2663:2663:2663)) + (PORT d[2] (1885:1885:1885) (2005:2005:2005)) + (PORT d[3] (1262:1262:1262) (1338:1338:1338)) + (PORT d[4] (2266:2266:2266) (2355:2355:2355)) + (PORT d[5] (1286:1286:1286) (1366:1366:1366)) + (PORT d[6] (1452:1452:1452) (1480:1480:1480)) + (PORT d[7] (2355:2355:2355) (2491:2491:2491)) + (PORT d[8] (2239:2239:2239) (2395:2395:2395)) + (PORT d[9] (1053:1053:1053) (1110:1110:1110)) + (PORT d[10] (1026:1026:1026) (1074:1074:1074)) + (PORT d[11] (1436:1436:1436) (1501:1501:1501)) + (PORT d[12] (756:756:756) (816:816:816)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1782:1782:1782) (1767:1767:1767)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (1825:1825:1825) (1809:1809:1809)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1807:1807:1807) (1834:1834:1834)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (992:992:992) (997:997:997)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1887:1887:1887) (1911:1911:1911)) + (PORT asdata (2020:2020:2020) (2056:2056:2056)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1760:1760:1760) (1806:1806:1806)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (974:974:974) (1013:1013:1013)) + (PORT datab (895:895:895) (947:947:947)) + (PORT datac (1141:1141:1141) (1200:1200:1200)) + (PORT datad (964:964:964) (1019:1019:1019)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1919:1919:1919) (2115:2115:2115)) + (PORT datac (1982:1982:1982) (2200:2200:2200)) + (PORT datad (1422:1422:1422) (1531:1531:1531)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1512:1512:1512) (1551:1551:1551)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1938:1938:1938) (2080:2080:2080)) + (PORT d[1] (2501:2501:2501) (2527:2527:2527)) + (PORT d[2] (2588:2588:2588) (2765:2765:2765)) + (PORT d[3] (1139:1139:1139) (1178:1178:1178)) + (PORT d[4] (2415:2415:2415) (2565:2565:2565)) + (PORT d[5] (3170:3170:3170) (3226:3226:3226)) + (PORT d[6] (2192:2192:2192) (2289:2289:2289)) + (PORT d[7] (1851:1851:1851) (1867:1867:1867)) + (PORT d[8] (2510:2510:2510) (2632:2632:2632)) + (PORT d[9] (1705:1705:1705) (1750:1750:1750)) + (PORT d[10] (2512:2512:2512) (2611:2611:2611)) + (PORT d[11] (4013:4013:4013) (4323:4323:4323)) + (PORT d[12] (2512:2512:2512) (2564:2564:2564)) + (PORT clk (1847:1847:1847) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2002:2002:2002) (1964:1964:1964)) + (PORT clk (1847:1847:1847) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT d[0] (2197:2197:2197) (2152:2152:2152)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1836:1836:1836)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1000:1000:1000)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (462:462:462)) + (PORT datab (1257:1257:1257) (1300:1300:1300)) + (PORT datac (1234:1234:1234) (1270:1270:1270)) + (PORT datad (1392:1392:1392) (1420:1420:1420)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1920:1920:1920) (2115:2115:2115)) + (PORT datac (1982:1982:1982) (2197:2197:2197)) + (PORT datad (1425:1425:1425) (1529:1529:1529)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (852:852:852) (854:854:854)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2917:2917:2917) (3108:3108:3108)) + (PORT d[1] (3323:3323:3323) (3498:3498:3498)) + (PORT d[2] (1499:1499:1499) (1573:1573:1573)) + (PORT d[3] (3966:3966:3966) (4139:4139:4139)) + (PORT d[4] (2897:2897:2897) (3086:3086:3086)) + (PORT d[5] (4427:4427:4427) (4564:4564:4564)) + (PORT d[6] (2208:2208:2208) (2294:2294:2294)) + (PORT d[7] (3987:3987:3987) (4071:4071:4071)) + (PORT d[8] (1521:1521:1521) (1551:1551:1551)) + (PORT d[9] (2130:2130:2130) (2218:2218:2218)) + (PORT d[10] (2303:2303:2303) (2371:2371:2371)) + (PORT d[11] (3139:3139:3139) (3345:3345:3345)) + (PORT d[12] (4131:4131:4131) (4403:4403:4403)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1928:1928:1928) (1901:1901:1901)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (2721:2721:2721) (2738:2738:2738)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1492:1492:1492) (1564:1564:1564)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (944:944:944) (997:997:997)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (411:411:411) (465:465:465)) + (PORT datab (1252:1252:1252) (1298:1298:1298)) + (PORT datac (1232:1232:1232) (1268:1268:1268)) + (PORT datad (1391:1391:1391) (1418:1418:1418)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1915:1915:1915) (2111:2111:2111)) + (PORT datac (1984:1984:1984) (2198:2198:2198)) + (PORT datad (1420:1420:1420) (1527:1527:1527)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1308:1308:1308) (1374:1374:1374)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2112:2112:2112) (2310:2310:2310)) + (PORT d[1] (2254:2254:2254) (2334:2334:2334)) + (PORT d[2] (1596:1596:1596) (1699:1699:1699)) + (PORT d[3] (2501:2501:2501) (2593:2593:2593)) + (PORT d[4] (2291:2291:2291) (2367:2367:2367)) + (PORT d[5] (1576:1576:1576) (1652:1652:1652)) + (PORT d[6] (1720:1720:1720) (1763:1763:1763)) + (PORT d[7] (2216:2216:2216) (2273:2273:2273)) + (PORT d[8] (2483:2483:2483) (2655:2655:2655)) + (PORT d[9] (1067:1067:1067) (1146:1146:1146)) + (PORT d[10] (1734:1734:1734) (1816:1816:1816)) + (PORT d[11] (1425:1425:1425) (1474:1474:1474)) + (PORT d[12] (1019:1019:1019) (1090:1090:1090)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1513:1513:1513) (1529:1529:1529)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT d[0] (2023:2023:2023) (2001:2001:2001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (1095:1095:1095) (1125:1125:1125)) + (PORT datab (1546:1546:1546) (1595:1595:1595)) + (PORT datac (1417:1417:1417) (1491:1491:1491)) + (PORT datad (1479:1479:1479) (1560:1560:1560)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1299:1299:1299) (1351:1351:1351)) + (PORT datab (1832:1832:1832) (1977:1977:1977)) + (PORT datac (1662:1662:1662) (1715:1715:1715)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (463:463:463)) + (PORT datab (1250:1250:1250) (1293:1293:1293)) + (PORT datac (1232:1232:1232) (1265:1265:1265)) + (PORT datad (1387:1387:1387) (1415:1415:1415)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE CLOCK_50\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (154:154:154) (138:138:138)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\~0) + (DELAY + (ABSOLUTE + (PORT dataa (446:446:446) (541:541:541)) + (PORT datab (973:973:973) (1044:1044:1044)) + (PORT datac (711:711:711) (774:774:774)) + (PORT datad (740:740:740) (796:796:796)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1552:1552:1552)) + (PORT asdata (996:996:996) (1046:1046:1046)) + (PORT ena (817:817:817) (814:814:814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (885:885:885) (926:926:926)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1552:1552:1552)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (817:817:817) (814:814:814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT datac (911:911:911) (966:966:966)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1552:1552:1552)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (817:817:817) (814:814:814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~0) + (DELAY + (ABSOLUTE + (PORT datac (915:915:915) (971:971:971)) + (PORT datad (883:883:883) (943:943:943)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1552:1552:1552)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (817:817:817) (814:814:814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (953:953:953) (1011:1011:1011)) + (PORT datab (911:911:911) (982:982:982)) + (PORT datad (876:876:876) (933:933:933)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1552:1552:1552)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (817:817:817) (814:814:814)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1271:1271:1271) (1341:1341:1341)) + (PORT datab (629:629:629) (682:682:682)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (744:744:744) (808:808:808)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~4) + (DELAY + (ABSOLUTE + (PORT dataa (679:679:679) (756:756:756)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~6) + (DELAY + (ABSOLUTE + (PORT datab (941:941:941) (983:983:983)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (946:946:946) (928:928:928)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~8) + (DELAY + (ABSOLUTE + (PORT dataa (952:952:952) (1009:1009:1009)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (946:946:946) (928:928:928)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~10) + (DELAY + (ABSOLUTE + (PORT datab (959:959:959) (1008:1008:1008)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (946:946:946) (928:928:928)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~12) + (DELAY + (ABSOLUTE + (PORT dataa (710:710:710) (781:781:781)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (960:960:960) (1021:1021:1021)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[8\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (447:447:447) (541:541:541)) + (PORT datab (970:970:970) (1040:1040:1040)) + (PORT datac (712:712:712) (775:775:775)) + (PORT datad (738:738:738) (793:793:793)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (980:980:980) (984:984:984)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1125:1125:1125) (1173:1173:1173)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (955:955:955) (1015:1015:1015)) + (PORT datac (181:181:181) (217:217:217)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (980:980:980) (984:984:984)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (446:446:446) (542:542:542)) + (PORT datab (979:979:979) (1050:1050:1050)) + (PORT datac (707:707:707) (769:769:769)) + (PORT datad (744:744:744) (801:801:801)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (375:375:375)) + (PORT datab (378:378:378) (404:404:404)) + (PORT datad (742:742:742) (802:802:802)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1552:1552:1552)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT datac (920:920:920) (981:981:981)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (980:980:980) (984:984:984)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (954:954:954) (1014:1014:1014)) + (PORT datac (182:182:182) (220:220:220)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1540:1540:1540) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (980:980:980) (984:984:984)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1277:1277:1277) (1338:1338:1338)) + (PORT clk (1855:1855:1855) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2788:2788:2788) (2939:2939:2939)) + (PORT d[1] (2965:2965:2965) (3112:3112:3112)) + (PORT d[2] (1934:1934:1934) (2074:2074:2074)) + (PORT d[3] (2167:2167:2167) (2291:2291:2291)) + (PORT d[4] (2059:2059:2059) (2183:2183:2183)) + (PORT d[5] (1870:1870:1870) (1973:1973:1973)) + (PORT d[6] (2323:2323:2323) (2459:2459:2459)) + (PORT d[7] (1899:1899:1899) (1971:1971:1971)) + (PORT d[8] (3189:3189:3189) (3291:3291:3291)) + (PORT d[9] (2017:2017:2017) (2163:2163:2163)) + (PORT d[10] (3596:3596:3596) (3781:3781:3781)) + (PORT d[11] (2378:2378:2378) (2513:2513:2513)) + (PORT d[12] (1977:1977:1977) (2130:2130:2130)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1790:1790:1790) (1802:1802:1802)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1883:1883:1883)) + (PORT d[0] (3272:3272:3272) (3205:3205:3205)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1808:1808:1808)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1867:1867:1867) (1911:1911:1911)) + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4490:4490:4490) (4600:4600:4600)) + (PORT d[1] (4410:4410:4410) (4523:4523:4523)) + (PORT d[2] (4538:4538:4538) (4602:4602:4602)) + (PORT d[3] (4281:4281:4281) (4370:4370:4370)) + (PORT d[4] (4381:4381:4381) (4456:4456:4456)) + (PORT d[5] (4418:4418:4418) (4548:4548:4548)) + (PORT d[6] (4415:4415:4415) (4506:4506:4506)) + (PORT d[7] (4377:4377:4377) (4507:4507:4507)) + (PORT d[8] (4645:4645:4645) (4750:4750:4750)) + (PORT d[9] (4429:4429:4429) (4513:4513:4513)) + (PORT d[10] (4448:4448:4448) (4509:4509:4509)) + (PORT d[11] (4414:4414:4414) (4551:4551:4551)) + (PORT d[12] (4365:4365:4365) (4449:4449:4449)) + (PORT clk (1816:1816:1816) (1810:1810:1810)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1810:1810:1810)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1452:1452:1452) (1517:1517:1517)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (218:218:218) (288:288:288)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1166:1166:1166) (1252:1252:1252)) + (PORT datab (1269:1269:1269) (1318:1318:1318)) + (PORT datac (1435:1435:1435) (1491:1491:1491)) + (PORT datad (1131:1131:1131) (1204:1204:1204)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1222:1222:1222) (1232:1232:1232)) + (PORT clk (1846:1846:1846) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3085:3085:3085) (3257:3257:3257)) + (PORT d[1] (2119:2119:2119) (2225:2225:2225)) + (PORT d[2] (1627:1627:1627) (1738:1738:1738)) + (PORT d[3] (1538:1538:1538) (1637:1637:1637)) + (PORT d[4] (2666:2666:2666) (2815:2815:2815)) + (PORT d[5] (1574:1574:1574) (1655:1655:1655)) + (PORT d[6] (2028:2028:2028) (2134:2134:2134)) + (PORT d[7] (1881:1881:1881) (1932:1932:1932)) + (PORT d[8] (3473:3473:3473) (3592:3592:3592)) + (PORT d[9] (1702:1702:1702) (1822:1822:1822)) + (PORT d[10] (1648:1648:1648) (1760:1760:1760)) + (PORT d[11] (1603:1603:1603) (1685:1685:1685)) + (PORT d[12] (1677:1677:1677) (1804:1804:1804)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1434:1434:1434) (1404:1404:1404)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1875:1875:1875)) + (PORT d[0] (2896:2896:2896) (2932:2932:2932)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1801:1801:1801) (1800:1800:1800)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1527:1527:1527) (1568:1568:1568)) + (PORT clk (1811:1811:1811) (1806:1806:1806)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4450:4450:4450) (4537:4537:4537)) + (PORT d[1] (4347:4347:4347) (4424:4424:4424)) + (PORT d[2] (4406:4406:4406) (4467:4467:4467)) + (PORT d[3] (4294:4294:4294) (4374:4374:4374)) + (PORT d[4] (4350:4350:4350) (4425:4425:4425)) + (PORT d[5] (4369:4369:4369) (4474:4474:4474)) + (PORT d[6] (4390:4390:4390) (4426:4426:4426)) + (PORT d[7] (4335:4335:4335) (4462:4462:4462)) + (PORT d[8] (4444:4444:4444) (4576:4576:4576)) + (PORT d[9] (4472:4472:4472) (4577:4577:4577)) + (PORT d[10] (4487:4487:4487) (4606:4606:4606)) + (PORT d[11] (4466:4466:4466) (4582:4582:4582)) + (PORT d[12] (4367:4367:4367) (4452:4452:4452)) + (PORT clk (1807:1807:1807) (1802:1802:1802)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1806:1806:1806)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3185:3185:3185) (3417:3417:3417)) + (PORT d[1] (3332:3332:3332) (3484:3484:3484)) + (PORT d[2] (1430:1430:1430) (1497:1497:1497)) + (PORT d[3] (3934:3934:3934) (4092:4092:4092)) + (PORT d[4] (2918:2918:2918) (3104:3104:3104)) + (PORT d[5] (4421:4421:4421) (4553:4553:4553)) + (PORT d[6] (2796:2796:2796) (2911:2911:2911)) + (PORT d[7] (1726:1726:1726) (1774:1774:1774)) + (PORT d[8] (1980:1980:1980) (2009:2009:2009)) + (PORT d[9] (2141:2141:2141) (2210:2210:2210)) + (PORT d[10] (2312:2312:2312) (2391:2391:2391)) + (PORT d[11] (3101:3101:3101) (3331:3331:3331)) + (PORT d[12] (4277:4277:4277) (4540:4540:4540)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1882:1882:1882)) + (PORT d[0] (1940:1940:1940) (1958:1958:1958)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (1021:1021:1021)) + (PORT datab (305:305:305) (397:397:397)) + (PORT datac (887:887:887) (916:916:916)) + (PORT datad (1045:1045:1045) (1066:1066:1066)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1950:1950:1950) (2052:2052:2052)) + (PORT d[1] (2560:2560:2560) (2687:2687:2687)) + (PORT d[2] (2359:2359:2359) (2509:2509:2509)) + (PORT d[3] (3005:3005:3005) (3111:3111:3111)) + (PORT d[4] (2278:2278:2278) (2362:2362:2362)) + (PORT d[5] (3097:3097:3097) (3185:3185:3185)) + (PORT d[6] (2841:2841:2841) (2965:2965:2965)) + (PORT d[7] (3148:3148:3148) (3225:3225:3225)) + (PORT d[8] (2385:2385:2385) (2466:2466:2466)) + (PORT d[9] (3043:3043:3043) (3176:3176:3176)) + (PORT d[10] (2289:2289:2289) (2338:2338:2338)) + (PORT d[11] (2469:2469:2469) (2631:2631:2631)) + (PORT d[12] (3226:3226:3226) (3408:3408:3408)) + (PORT clk (1868:1868:1868) (1894:1894:1894)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1868:1868:1868) (1894:1894:1894)) + (PORT d[0] (2959:2959:2959) (2871:2871:2871)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1831:1831:1831) (1857:1857:1857)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1020:1020:1020)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (1095:1095:1095) (1122:1122:1122)) + (PORT datab (1468:1468:1468) (1531:1531:1531)) + (PORT datac (178:178:178) (214:214:214)) + (PORT datad (1667:1667:1667) (1758:1758:1758)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1164:1164:1164) (1231:1231:1231)) + (PORT datab (307:307:307) (400:400:400)) + (PORT datac (180:180:180) (216:216:216)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~119) + (DELAY + (ABSOLUTE + (PORT dataa (1416:1416:1416) (1483:1483:1483)) + (PORT datab (2298:2298:2298) (2535:2535:2535)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1231:1231:1231) (1308:1308:1308)) + (PORT datab (635:635:635) (668:668:668)) + (PORT datac (844:844:844) (889:889:889)) + (PORT datad (327:327:327) (350:350:350)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (2195:2195:2195) (2276:2276:2276)) + (PORT datab (637:637:637) (668:668:668)) + (PORT datac (1697:1697:1697) (1792:1792:1792)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (1431:1431:1431) (1450:1450:1450)) + (PORT datac (1093:1093:1093) (1122:1122:1122)) + (PORT datad (344:344:344) (358:358:358)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1131:1131:1131) (1163:1163:1163)) + (PORT datab (1474:1474:1474) (1564:1564:1564)) + (PORT datac (2114:2114:2114) (2227:2227:2227)) + (PORT datad (1651:1651:1651) (1831:1831:1831)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) + (DELAY + (ABSOLUTE + (PORT dataa (1685:1685:1685) (1762:1762:1762)) + (PORT datab (537:537:537) (564:564:564)) + (PORT datac (1014:1014:1014) (1023:1023:1023)) + (PORT datad (1124:1124:1124) (1159:1159:1159)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1155:1155:1155) (1140:1140:1140)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1129:1129:1129) (1166:1166:1166)) + (PORT datab (245:245:245) (289:289:289)) + (PORT datac (847:847:847) (855:855:855)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (253:253:253)) + (PORT datac (1091:1091:1091) (1119:1119:1119)) + (PORT datad (224:224:224) (259:259:259)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (470:470:470)) + (PORT datab (253:253:253) (303:303:303)) + (PORT datac (340:340:340) (362:362:362)) + (PORT datad (217:217:217) (254:254:254)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|ir_\|opcode\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (621:621:621) (634:634:634)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1154:1154:1154) (1207:1207:1207)) + (PORT datab (2915:2915:2915) (2999:2999:2999)) + (PORT datac (1369:1369:1369) (1427:1427:1427)) + (PORT datad (800:800:800) (850:850:850)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1591:1591:1591) (1568:1568:1568)) + (PORT ena (2213:2213:2213) (2213:2213:2213)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1858:1858:1858) (1939:1939:1939)) + (PORT datab (1661:1661:1661) (1809:1809:1809)) + (PORT datac (1723:1723:1723) (1805:1805:1805)) + (PORT datad (882:882:882) (900:900:900)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (711:711:711)) + (PORT datab (826:826:826) (874:874:874)) + (PORT datac (346:346:346) (370:370:370)) + (PORT datad (611:611:611) (623:623:623)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (896:896:896) (958:958:958)) + (PORT datab (1170:1170:1170) (1229:1229:1229)) + (PORT datac (1138:1138:1138) (1178:1178:1178)) + (PORT datad (1161:1161:1161) (1197:1197:1197)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (377:377:377)) + (PORT datab (218:218:218) (257:257:257)) + (PORT datac (867:867:867) (893:893:893)) + (PORT datad (217:217:217) (253:253:253)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (892:892:892)) + (PORT datac (794:794:794) (839:839:839)) + (PORT datad (815:815:815) (833:833:833)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (954:954:954)) + (PORT datab (902:902:902) (931:931:931)) + (PORT datac (806:806:806) (822:822:822)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (639:639:639)) + (PORT datab (1166:1166:1166) (1208:1208:1208)) + (PORT datac (909:909:909) (953:953:953)) + (PORT datad (585:585:585) (613:613:613)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (1349:1349:1349) (1369:1369:1369)) + (PORT datac (628:628:628) (663:663:663)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[6\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (830:830:830) (884:884:884)) + (PORT datab (668:668:668) (707:707:707)) + (PORT datac (825:825:825) (860:860:860)) + (PORT datad (819:819:819) (837:837:837)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (855:855:855)) + (PORT datac (354:354:354) (381:381:381)) + (PORT datad (849:849:849) (871:871:871)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (950:950:950)) + (PORT datab (637:637:637) (657:657:657)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (594:594:594) (606:606:606)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1124:1124:1124) (1160:1160:1160)) + (PORT datab (246:246:246) (293:293:293)) + (PORT datad (1182:1182:1182) (1220:1220:1220)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1184:1184:1184) (1228:1228:1228)) + (PORT d[0] (1316:1316:1316) (1375:1375:1375)) (PORT clk (1845:1845:1845) (1873:1873:1873)) ) ) @@ -30842,19 +35042,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3973:3973:3973) (4187:4187:4187)) - (PORT d[1] (1695:1695:1695) (1858:1858:1858)) - (PORT d[2] (3329:3329:3329) (3462:3462:3462)) - (PORT d[3] (2153:2153:2153) (2276:2276:2276)) - (PORT d[4] (2142:2142:2142) (2252:2252:2252)) - (PORT d[5] (1659:1659:1659) (1777:1777:1777)) - (PORT d[6] (1754:1754:1754) (1804:1804:1804)) - (PORT d[7] (3063:3063:3063) (3210:3210:3210)) - (PORT d[8] (3317:3317:3317) (3546:3546:3546)) - (PORT d[9] (1753:1753:1753) (1814:1814:1814)) - (PORT d[10] (3216:3216:3216) (3426:3426:3426)) - (PORT d[11] (2090:2090:2090) (2212:2212:2212)) - (PORT d[12] (1771:1771:1771) (1834:1834:1834)) + (PORT d[0] (2397:2397:2397) (2589:2589:2589)) + (PORT d[1] (2605:2605:2605) (2682:2682:2682)) + (PORT d[2] (1244:1244:1244) (1312:1312:1312)) + (PORT d[3] (1263:1263:1263) (1323:1323:1323)) + (PORT d[4] (2021:2021:2021) (2110:2110:2110)) + (PORT d[5] (1254:1254:1254) (1323:1323:1323)) + (PORT d[6] (1478:1478:1478) (1511:1511:1511)) + (PORT d[7] (2356:2356:2356) (2492:2492:2492)) + (PORT d[8] (2505:2505:2505) (2668:2668:2668)) + (PORT d[9] (775:775:775) (840:840:840)) + (PORT d[10] (1752:1752:1752) (1831:1831:1831)) + (PORT d[11] (1174:1174:1174) (1217:1217:1217)) + (PORT d[12] (728:728:728) (783:783:783)) (PORT clk (1842:1842:1842) (1869:1869:1869)) ) ) @@ -30867,7 +35067,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2235:2235:2235) (2268:2268:2268)) + (PORT d[0] (1797:1797:1797) (1781:1781:1781)) (PORT clk (1842:1842:1842) (1869:1869:1869)) ) ) @@ -30881,7 +35081,7 @@ (DELAY (ABSOLUTE (PORT clk (1845:1845:1845) (1873:1873:1873)) - (PORT d[0] (2962:2962:2962) (3024:3024:3024)) + (PORT d[0] (1825:1825:1825) (1808:1808:1808)) ) ) ) @@ -30978,48 +35178,308 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~90) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (602:602:602) (616:616:616)) - (PORT datab (976:976:976) (1039:1039:1039)) - (PORT datac (828:828:828) (832:832:832)) - (PORT datad (1142:1142:1142) (1222:1222:1222)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT d[0] (961:961:961) (961:961:961)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2420:2420:2420) (2630:2630:2630)) + (PORT d[1] (1241:1241:1241) (1313:1313:1313)) + (PORT d[2] (1662:1662:1662) (1741:1741:1741)) + (PORT d[3] (1596:1596:1596) (1691:1691:1691)) + (PORT d[4] (2978:2978:2978) (3155:3155:3155)) + (PORT d[5] (1264:1264:1264) (1317:1317:1317)) + (PORT d[6] (1560:1560:1560) (1657:1657:1657)) + (PORT d[7] (1291:1291:1291) (1338:1338:1338)) + (PORT d[8] (1256:1256:1256) (1319:1319:1319)) + (PORT d[9] (1080:1080:1080) (1170:1170:1170)) + (PORT d[10] (1071:1071:1071) (1158:1158:1158)) + (PORT d[11] (2213:2213:2213) (2338:2338:2338)) + (PORT d[12] (1088:1088:1088) (1179:1179:1179)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1220:1220:1220) (1163:1163:1163)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2327:2327:2327) (2302:2302:2302)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) (DELAY (ABSOLUTE - (PORT dataa (700:700:700) (731:731:731)) - (PORT datab (265:265:265) (319:319:319)) - (PORT datac (371:371:371) (408:408:408)) - (PORT datad (1303:1303:1303) (1299:1299:1299)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) (DELAY (ABSOLUTE - (PORT datab (2046:2046:2046) (2179:2179:2179)) - (PORT datac (1157:1157:1157) (1209:1209:1209)) - (PORT datad (1148:1148:1148) (1203:1203:1203)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1310:1310:1310) (1368:1368:1368)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2700:2700:2700) (2899:2899:2899)) + (PORT d[1] (2882:2882:2882) (2995:2995:2995)) + (PORT d[2] (1236:1236:1236) (1287:1287:1287)) + (PORT d[3] (979:979:979) (1033:1033:1033)) + (PORT d[4] (2053:2053:2053) (2138:2138:2138)) + (PORT d[5] (951:951:951) (1003:1003:1003)) + (PORT d[6] (1440:1440:1440) (1451:1451:1451)) + (PORT d[7] (2650:2650:2650) (2803:2803:2803)) + (PORT d[8] (2518:2518:2518) (2699:2699:2699)) + (PORT d[9] (743:743:743) (798:798:798)) + (PORT d[10] (755:755:755) (811:811:811)) + (PORT d[11] (2821:2821:2821) (3003:3003:3003)) + (PORT d[12] (715:715:715) (752:752:752)) + (PORT clk (1838:1838:1838) (1865:1865:1865)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1241:1241:1241) (1217:1217:1217)) + (PORT clk (1838:1838:1838) (1865:1865:1865)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1869:1869:1869)) + (PORT d[0] (1450:1450:1450) (1417:1417:1417)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1801:1801:1801) (1828:1828:1828)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (986:986:986) (991:991:991)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) @@ -31028,8 +35488,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1196:1196:1196) (1209:1209:1209)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (677:677:677) (699:699:699)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) ) ) (TIMINGCHECK @@ -31041,20 +35501,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (4200:4200:4200) (4456:4456:4456)) - (PORT d[1] (2340:2340:2340) (2537:2537:2537)) - (PORT d[2] (3231:3231:3231) (3326:3326:3326)) - (PORT d[3] (2575:2575:2575) (2761:2761:2761)) - (PORT d[4] (2559:2559:2559) (2766:2766:2766)) - (PORT d[5] (2828:2828:2828) (3008:3008:3008)) - (PORT d[6] (1911:1911:1911) (2053:2053:2053)) - (PORT d[7] (2601:2601:2601) (2739:2739:2739)) - (PORT d[8] (3332:3332:3332) (3618:3618:3618)) - (PORT d[9] (2924:2924:2924) (3075:3075:3075)) - (PORT d[10] (5088:5088:5088) (5359:5359:5359)) - (PORT d[11] (1899:1899:1899) (2034:2034:2034)) - (PORT d[12] (2169:2169:2169) (2292:2292:2292)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) + (PORT d[0] (2669:2669:2669) (2901:2901:2901)) + (PORT d[1] (1288:1288:1288) (1360:1360:1360)) + (PORT d[2] (1665:1665:1665) (1743:1743:1743)) + (PORT d[3] (1565:1565:1565) (1640:1640:1640)) + (PORT d[4] (2970:2970:2970) (3148:3148:3148)) + (PORT d[5] (1271:1271:1271) (1329:1329:1329)) + (PORT d[6] (1509:1509:1509) (1602:1602:1602)) + (PORT d[7] (1615:1615:1615) (1649:1649:1649)) + (PORT d[8] (1553:1553:1553) (1653:1653:1653)) + (PORT d[9] (1383:1383:1383) (1478:1478:1478)) + (PORT d[10] (1335:1335:1335) (1424:1424:1424)) + (PORT d[11] (1876:1876:1876) (1999:1999:1999)) + (PORT d[12] (1381:1381:1381) (1486:1486:1486)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) (TIMINGCHECK @@ -31066,8 +35526,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2009:2009:2009) (1965:1965:1965)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) + (PORT d[0] (1236:1236:1236) (1214:1214:1214)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) (TIMINGCHECK @@ -31079,8 +35539,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1854:1854:1854) (1881:1881:1881)) - (PORT d[0] (2224:2224:2224) (2198:2198:2198)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (2701:2701:2701) (2725:2725:2725)) ) ) ) @@ -31089,7 +35549,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -31099,7 +35559,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -31109,7 +35569,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -31119,7 +35579,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -31129,7 +35589,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1814:1814:1814) (1840:1840:1840)) + (PORT clk (1811:1811:1811) (1838:1838:1838)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -31143,7 +35603,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (999:999:999) (1003:1003:1003)) + (PORT clk (996:996:996) (1001:1001:1001)) ) ) ) @@ -31152,7 +35612,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) + (PORT clk (997:997:997) (1002:1002:1002)) ) ) ) @@ -31161,7 +35621,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) + (PORT clk (997:997:997) (1002:1002:1002)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -31171,536 +35631,49 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) + (PORT clk (997:997:997) (1002:1002:1002)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~91) + (INSTANCE D\[6\]\~103) (DELAY (ABSOLUTE - (PORT dataa (837:837:837) (859:859:859)) - (PORT datab (1432:1432:1432) (1519:1519:1519)) - (PORT datac (318:318:318) (339:339:339)) - (PORT datad (1100:1100:1100) (1101:1101:1101)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (698:698:698) (723:723:723)) - (PORT datab (257:257:257) (310:310:310)) - (PORT datac (364:364:364) (402:402:402)) - (PORT datad (1304:1304:1304) (1295:1295:1295)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE CLOCK_50\~inputclkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (154:154:154) (138:138:138)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1044:1044:1044) (1098:1098:1098)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1253:1253:1253) (1340:1340:1340)) - (PORT datab (987:987:987) (1065:1065:1065)) - (PORT datac (971:971:971) (1042:1042:1042)) - (PORT datad (277:277:277) (361:361:361)) + (PORT dataa (1456:1456:1456) (1532:1532:1532)) + (PORT datab (1228:1228:1228) (1286:1286:1286)) + (PORT datad (1444:1444:1444) (1432:1432:1432)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT asdata (1205:1205:1205) (1280:1280:1280)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT datac (896:896:896) (972:972:972)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~0) - (DELAY - (ABSOLUTE - (PORT datac (891:891:891) (968:968:968)) - (PORT datad (1442:1442:1442) (1493:1493:1493)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (1008:1008:1008)) - (PORT datac (1383:1383:1383) (1458:1458:1458)) - (PORT datad (1442:1442:1442) (1493:1493:1493)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (779:779:779)) - (PORT datab (721:721:721) (803:803:803)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~2) - (DELAY - (ABSOLUTE - (PORT datab (644:644:644) (722:722:722)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~4) - (DELAY - (ABSOLUTE - (PORT datab (706:706:706) (772:772:772)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~6) - (DELAY - (ABSOLUTE - (PORT datab (682:682:682) (766:766:766)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~8) - (DELAY - (ABSOLUTE - (PORT dataa (700:700:700) (788:788:788)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~10) - (DELAY - (ABSOLUTE - (PORT dataa (980:980:980) (1052:1052:1052)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~12) - (DELAY - (ABSOLUTE - (PORT datab (694:694:694) (766:766:766)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector6\~0) - (DELAY - (ABSOLUTE - (PORT datab (610:610:610) (638:638:638)) - (PORT datac (561:561:561) (582:582:582)) - (PORT datad (957:957:957) (1029:1029:1029)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[9\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1254:1254:1254) (1344:1344:1344)) - (PORT datab (987:987:987) (1066:1066:1066)) - (PORT datac (976:976:976) (1049:1049:1049)) - (PORT datad (282:282:282) (366:366:366)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (820:820:820) (826:826:826)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~14) - (DELAY - (ABSOLUTE - (PORT datad (708:708:708) (780:780:780)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (677:677:677)) - (PORT datac (792:792:792) (807:807:807)) - (PORT datad (957:957:957) (1033:1033:1033)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (820:820:820) (826:826:826)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1251:1251:1251) (1338:1338:1338)) - (PORT datab (981:981:981) (1058:1058:1058)) - (PORT datac (980:980:980) (1051:1051:1051)) - (PORT datad (285:285:285) (369:369:369)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (644:644:644)) - (PORT datab (1014:1014:1014) (1089:1089:1089)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector3\~0) + (INSTANCE D\[6\]\~104) (DELAY (ABSOLUTE - (PORT datab (613:613:613) (639:639:639)) - (PORT datad (958:958:958) (1031:1031:1031)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (820:820:820) (826:826:826)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector2\~0) - (DELAY - (ABSOLUTE - (PORT datac (618:618:618) (638:638:638)) - (PORT datad (957:957:957) (1029:1029:1029)) + (PORT dataa (1513:1513:1513) (1583:1583:1583)) + (PORT datab (1831:1831:1831) (1977:1977:1977)) + (PORT datac (1437:1437:1437) (1482:1482:1482)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (820:820:820) (826:826:826)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1548:1548:1548) (1620:1620:1620)) - (PORT clk (1864:1864:1864) (1891:1891:1891)) + (PORT d[0] (1260:1260:1260) (1277:1277:1277)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) ) ) (TIMINGCHECK @@ -31712,20 +35685,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2599:2599:2599) (2697:2697:2697)) - (PORT d[1] (2358:2358:2358) (2589:2589:2589)) - (PORT d[2] (2326:2326:2326) (2476:2476:2476)) - (PORT d[3] (1990:1990:1990) (2063:2063:2063)) - (PORT d[4] (2926:2926:2926) (3182:3182:3182)) - (PORT d[5] (2089:2089:2089) (2294:2294:2294)) - (PORT d[6] (1566:1566:1566) (1667:1667:1667)) - (PORT d[7] (1626:1626:1626) (1711:1711:1711)) - (PORT d[8] (2773:2773:2773) (3020:3020:3020)) - (PORT d[9] (2077:2077:2077) (2186:2186:2186)) - (PORT d[10] (2124:2124:2124) (2247:2247:2247)) - (PORT d[11] (3187:3187:3187) (3328:3328:3328)) - (PORT d[12] (2201:2201:2201) (2298:2298:2298)) - (PORT clk (1861:1861:1861) (1887:1887:1887)) + (PORT d[0] (2793:2793:2793) (2950:2950:2950)) + (PORT d[1] (1830:1830:1830) (1942:1942:1942)) + (PORT d[2] (1907:1907:1907) (2035:2035:2035)) + (PORT d[3] (2153:2153:2153) (2289:2289:2289)) + (PORT d[4] (2370:2370:2370) (2502:2502:2502)) + (PORT d[5] (1869:1869:1869) (1972:1972:1972)) + (PORT d[6] (2343:2343:2343) (2464:2464:2464)) + (PORT d[7] (2215:2215:2215) (2277:2277:2277)) + (PORT d[8] (3168:3168:3168) (3268:3268:3268)) + (PORT d[9] (1739:1739:1739) (1883:1883:1883)) + (PORT d[10] (1634:1634:1634) (1763:1763:1763)) + (PORT d[11] (2386:2386:2386) (2535:2535:2535)) + (PORT d[12] (2455:2455:2455) (2610:2610:2610)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) ) ) (TIMINGCHECK @@ -31737,8 +35710,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2768:2768:2768) (2740:2740:2740)) - (PORT clk (1861:1861:1861) (1887:1887:1887)) + (PORT d[0] (1782:1782:1782) (1793:1793:1793)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) ) ) (TIMINGCHECK @@ -31750,8 +35723,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1864:1864:1864) (1891:1891:1891)) - (PORT d[0] (2876:2876:2876) (2827:2827:2827)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (PORT d[0] (3271:3271:3271) (3211:3211:3211)) ) ) ) @@ -31760,7 +35733,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -31770,7 +35743,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -31780,7 +35753,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -31790,7 +35763,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -31800,7 +35773,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1819:1819:1819) (1816:1816:1816)) + (PORT clk (1807:1807:1807) (1805:1805:1805)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -31814,8 +35787,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2147:2147:2147) (2193:2193:2193)) - (PORT clk (1829:1829:1829) (1822:1822:1822)) + (PORT d[0] (1887:1887:1887) (1934:1934:1934)) + (PORT clk (1817:1817:1817) (1811:1811:1811)) ) ) (TIMINGCHECK @@ -31827,20 +35800,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4636:4636:4636) (4688:4688:4688)) - (PORT d[1] (4395:4395:4395) (4383:4383:4383)) - (PORT d[2] (4558:4558:4558) (4624:4624:4624)) - (PORT d[3] (4721:4721:4721) (4720:4720:4720)) - (PORT d[4] (4265:4265:4265) (4262:4262:4262)) - (PORT d[5] (4417:4417:4417) (4355:4355:4355)) - (PORT d[6] (4638:4638:4638) (4708:4708:4708)) - (PORT d[7] (4394:4394:4394) (4343:4343:4343)) - (PORT d[8] (4731:4731:4731) (4705:4705:4705)) - (PORT d[9] (4601:4601:4601) (4791:4791:4791)) - (PORT d[10] (4436:4436:4436) (4445:4445:4445)) - (PORT d[11] (4654:4654:4654) (4682:4682:4682)) - (PORT d[12] (4454:4454:4454) (4466:4466:4466)) - (PORT clk (1825:1825:1825) (1818:1818:1818)) + (PORT d[0] (4443:4443:4443) (4548:4548:4548)) + (PORT d[1] (4421:4421:4421) (4559:4559:4559)) + (PORT d[2] (4547:4547:4547) (4625:4625:4625)) + (PORT d[3] (4250:4250:4250) (4323:4323:4323)) + (PORT d[4] (4357:4357:4357) (4435:4435:4435)) + (PORT d[5] (4381:4381:4381) (4503:4503:4503)) + (PORT d[6] (4351:4351:4351) (4470:4470:4470)) + (PORT d[7] (4377:4377:4377) (4506:4506:4506)) + (PORT d[8] (4630:4630:4630) (4748:4748:4748)) + (PORT d[9] (4422:4422:4422) (4527:4527:4527)) + (PORT d[10] (4416:4416:4416) (4515:4515:4515)) + (PORT d[11] (4442:4442:4442) (4583:4583:4583)) + (PORT d[12] (4386:4386:4386) (4473:4473:4473)) + (PORT clk (1813:1813:1813) (1807:1807:1807)) ) ) (TIMINGCHECK @@ -31852,7 +35825,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1829:1829:1829) (1822:1822:1822)) + (PORT clk (1817:1817:1817) (1811:1811:1811)) ) ) ) @@ -31861,7 +35834,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1830:1830:1830) (1823:1823:1823)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -31871,7 +35844,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1830:1830:1830) (1823:1823:1823)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) ) ) @@ -31881,7 +35854,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1830:1830:1830) (1823:1823:1823)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -31891,7 +35864,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1830:1830:1830) (1823:1823:1823)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -31901,7 +35874,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) (DELAY (ABSOLUTE - (PORT clk (1821:1821:1821) (1818:1818:1818)) + (PORT clk (1809:1809:1809) (1807:1807:1807)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -31910,67 +35883,13 @@ (HOLD d (posedge clk) (159:159:159)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1203:1203:1203) (1298:1298:1298)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1923:1923:1923) (1947:1947:1947)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT asdata (1724:1724:1724) (1774:1774:1774)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (726:726:726)) - (PORT datab (262:262:262) (315:315:315)) - (PORT datac (366:366:366) (405:405:405)) - (PORT datad (1303:1303:1303) (1300:1300:1300)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1513:1513:1513) (1593:1593:1593)) - (PORT clk (1857:1857:1857) (1885:1885:1885)) + (PORT d[0] (1228:1228:1228) (1270:1270:1270)) + (PORT clk (1849:1849:1849) (1877:1877:1877)) ) ) (TIMINGCHECK @@ -31982,20 +35901,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2905:2905:2905) (3002:3002:3002)) - (PORT d[1] (2381:2381:2381) (2621:2621:2621)) - (PORT d[2] (1221:1221:1221) (1275:1275:1275)) - (PORT d[3] (2017:2017:2017) (2080:2080:2080)) - (PORT d[4] (2910:2910:2910) (3179:3179:3179)) - (PORT d[5] (2405:2405:2405) (2631:2631:2631)) - (PORT d[6] (1533:1533:1533) (1608:1608:1608)) - (PORT d[7] (1282:1282:1282) (1365:1365:1365)) - (PORT d[8] (1697:1697:1697) (1794:1794:1794)) - (PORT d[9] (1564:1564:1564) (1639:1639:1639)) - (PORT d[10] (2164:2164:2164) (2311:2311:2311)) - (PORT d[11] (3205:3205:3205) (3345:3345:3345)) - (PORT d[12] (1922:1922:1922) (2027:2027:2027)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (2794:2794:2794) (2951:2951:2951)) + (PORT d[1] (1828:1828:1828) (1938:1938:1938)) + (PORT d[2] (2259:2259:2259) (2395:2395:2395)) + (PORT d[3] (2157:2157:2157) (2295:2295:2295)) + (PORT d[4] (2357:2357:2357) (2500:2500:2500)) + (PORT d[5] (1865:1865:1865) (1964:1964:1964)) + (PORT d[6] (1845:1845:1845) (1965:1965:1965)) + (PORT d[7] (1871:1871:1871) (1918:1918:1918)) + (PORT d[8] (3142:3142:3142) (3254:3254:3254)) + (PORT d[9] (1716:1716:1716) (1858:1858:1858)) + (PORT d[10] (3925:3925:3925) (4111:4111:4111)) + (PORT d[11] (2389:2389:2389) (2540:2540:2540)) + (PORT d[12] (1686:1686:1686) (1819:1819:1819)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) ) ) (TIMINGCHECK @@ -32007,8 +35926,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2709:2709:2709) (2650:2650:2650)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (1704:1704:1704) (1656:1656:1656)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) ) ) (TIMINGCHECK @@ -32020,8 +35939,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1857:1857:1857) (1885:1885:1885)) - (PORT d[0] (3090:3090:3090) (3120:3120:3120)) + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (PORT d[0] (2935:2935:2935) (2984:2984:2984)) ) ) ) @@ -32030,7 +35949,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -32040,7 +35959,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -32050,7 +35969,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -32060,7 +35979,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -32070,7 +35989,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1812:1812:1812) (1810:1810:1810)) + (PORT clk (1804:1804:1804) (1802:1802:1802)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -32084,8 +36003,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2167:2167:2167) (2208:2208:2208)) - (PORT clk (1822:1822:1822) (1816:1816:1816)) + (PORT d[0] (1853:1853:1853) (1917:1917:1917)) + (PORT clk (1814:1814:1814) (1808:1808:1808)) ) ) (TIMINGCHECK @@ -32097,20 +36016,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4624:4624:4624) (4660:4660:4660)) - (PORT d[1] (4162:4162:4162) (4152:4152:4152)) - (PORT d[2] (4263:4263:4263) (4325:4325:4325)) - (PORT d[3] (4486:4486:4486) (4524:4524:4524)) - (PORT d[4] (4333:4333:4333) (4346:4346:4346)) - (PORT d[5] (4356:4356:4356) (4399:4399:4399)) - (PORT d[6] (4459:4459:4459) (4542:4542:4542)) - (PORT d[7] (4161:4161:4161) (4129:4129:4129)) - (PORT d[8] (4409:4409:4409) (4389:4389:4389)) - (PORT d[9] (4581:4581:4581) (4772:4772:4772)) - (PORT d[10] (4418:4418:4418) (4409:4409:4409)) - (PORT d[11] (4535:4535:4535) (4594:4594:4594)) - (PORT d[12] (4450:4450:4450) (4459:4459:4459)) - (PORT clk (1818:1818:1818) (1812:1812:1812)) + (PORT d[0] (4455:4455:4455) (4544:4544:4544)) + (PORT d[1] (4366:4366:4366) (4482:4482:4482)) + (PORT d[2] (4416:4416:4416) (4497:4497:4497)) + (PORT d[3] (4264:4264:4264) (4327:4327:4327)) + (PORT d[4] (4354:4354:4354) (4419:4419:4419)) + (PORT d[5] (4403:4403:4403) (4526:4526:4526)) + (PORT d[6] (4425:4425:4425) (4522:4522:4522)) + (PORT d[7] (4346:4346:4346) (4468:4468:4468)) + (PORT d[8] (4655:4655:4655) (4776:4776:4776)) + (PORT d[9] (4485:4485:4485) (4573:4573:4573)) + (PORT d[10] (4462:4462:4462) (4577:4577:4577)) + (PORT d[11] (4470:4470:4470) (4590:4590:4590)) + (PORT d[12] (4386:4386:4386) (4471:4471:4471)) + (PORT clk (1810:1810:1810) (1804:1804:1804)) ) ) (TIMINGCHECK @@ -32122,7 +36041,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1822:1822:1822) (1816:1816:1816)) + (PORT clk (1814:1814:1814) (1808:1808:1808)) ) ) ) @@ -32131,7 +36050,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) + (PORT clk (1815:1815:1815) (1809:1809:1809)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -32141,7 +36060,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) + (PORT clk (1815:1815:1815) (1809:1809:1809)) ) ) ) @@ -32150,7 +36069,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) + (PORT clk (1815:1815:1815) (1809:1809:1809)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -32160,7 +36079,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) + (PORT clk (1815:1815:1815) (1809:1809:1809)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -32170,20 +36089,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2533:2533:2533) (2623:2623:2623)) - (PORT d[1] (2220:2220:2220) (2418:2418:2418)) - (PORT d[2] (2325:2325:2325) (2498:2498:2498)) - (PORT d[3] (2178:2178:2178) (2338:2338:2338)) - (PORT d[4] (2896:2896:2896) (3148:3148:3148)) - (PORT d[5] (2277:2277:2277) (2465:2465:2465)) - (PORT d[6] (1866:1866:1866) (1991:1991:1991)) - (PORT d[7] (2226:2226:2226) (2303:2303:2303)) - (PORT d[8] (2742:2742:2742) (2980:2980:2980)) - (PORT d[9] (1744:1744:1744) (1855:1855:1855)) - (PORT d[10] (1754:1754:1754) (1834:1834:1834)) - (PORT d[11] (3116:3116:3116) (3240:3240:3240)) - (PORT d[12] (1285:1285:1285) (1359:1359:1359)) - (PORT clk (1869:1869:1869) (1894:1894:1894)) + (PORT d[0] (2492:2492:2492) (2622:2622:2622)) + (PORT d[1] (2647:2647:2647) (2790:2790:2790)) + (PORT d[2] (2231:2231:2231) (2391:2391:2391)) + (PORT d[3] (2097:2097:2097) (2237:2237:2237)) + (PORT d[4] (1753:1753:1753) (1859:1859:1859)) + (PORT d[5] (2146:2146:2146) (2271:2271:2271)) + (PORT d[6] (2408:2408:2408) (2553:2553:2553)) + (PORT d[7] (3417:3417:3417) (3493:3493:3493)) + (PORT d[8] (2875:2875:2875) (2972:2972:2972)) + (PORT d[9] (2055:2055:2055) (2224:2224:2224)) + (PORT d[10] (1917:1917:1917) (2062:2062:2062)) + (PORT d[11] (2114:2114:2114) (2235:2235:2235)) + (PORT d[12] (2265:2265:2265) (2423:2423:2423)) + (PORT clk (1859:1859:1859) (1884:1884:1884)) ) ) (TIMINGCHECK @@ -32195,8 +36114,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1869:1869:1869) (1894:1894:1894)) - (PORT d[0] (2187:2187:2187) (2254:2254:2254)) + (PORT clk (1859:1859:1859) (1884:1884:1884)) + (PORT d[0] (2593:2593:2593) (2672:2672:2672)) ) ) ) @@ -32205,7 +36124,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1870:1870:1870) (1895:1895:1895)) + (PORT clk (1860:1860:1860) (1885:1885:1885)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -32215,7 +36134,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1832:1832:1832) (1857:1857:1857)) + (PORT clk (1822:1822:1822) (1847:1847:1847)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -32229,7 +36148,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1017:1017:1017) (1020:1020:1020)) + (PORT clk (1007:1007:1007) (1010:1010:1010)) ) ) ) @@ -32238,7 +36157,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) + (PORT clk (1008:1008:1008) (1011:1011:1011)) ) ) ) @@ -32247,7 +36166,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) + (PORT clk (1008:1008:1008) (1011:1011:1011)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -32257,22 +36176,22 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) + (PORT clk (1008:1008:1008) (1011:1011:1011)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~87) + (INSTANCE D\[6\]\~100) (DELAY (ABSOLUTE - (PORT dataa (1348:1348:1348) (1400:1400:1400)) - (PORT datab (276:276:276) (364:364:364)) - (PORT datac (1381:1381:1381) (1421:1421:1421)) - (PORT datad (1657:1657:1657) (1684:1684:1684)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1168:1168:1168) (1225:1225:1225)) + (PORT datab (307:307:307) (399:399:399)) + (PORT datac (1148:1148:1148) (1222:1222:1222)) + (PORT datad (1447:1447:1447) (1525:1525:1525)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32283,20 +36202,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3643:3643:3643) (3885:3885:3885)) - (PORT d[1] (2602:2602:2602) (2837:2837:2837)) - (PORT d[2] (2449:2449:2449) (2542:2542:2542)) - (PORT d[3] (2141:2141:2141) (2296:2296:2296)) - (PORT d[4] (2227:2227:2227) (2405:2405:2405)) - (PORT d[5] (2065:2065:2065) (2249:2249:2249)) - (PORT d[6] (1926:1926:1926) (2066:2066:2066)) - (PORT d[7] (1993:1993:1993) (2107:2107:2107)) - (PORT d[8] (2992:2992:2992) (3233:3233:3233)) - (PORT d[9] (2617:2617:2617) (2763:2763:2763)) - (PORT d[10] (4742:4742:4742) (4968:4968:4968)) - (PORT d[11] (2083:2083:2083) (2222:2222:2222)) - (PORT d[12] (2446:2446:2446) (2592:2592:2592)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (1960:1960:1960) (2070:2070:2070)) + (PORT d[1] (3002:3002:3002) (3172:3172:3172)) + (PORT d[2] (2265:2265:2265) (2363:2363:2363)) + (PORT d[3] (3641:3641:3641) (3796:3796:3796)) + (PORT d[4] (2594:2594:2594) (2773:2773:2773)) + (PORT d[5] (4146:4146:4146) (4262:4262:4262)) + (PORT d[6] (2765:2765:2765) (2873:2873:2873)) + (PORT d[7] (3716:3716:3716) (3795:3795:3795)) + (PORT d[8] (2020:2020:2020) (2071:2071:2071)) + (PORT d[9] (2145:2145:2145) (2236:2236:2236)) + (PORT d[10] (2368:2368:2368) (2463:2463:2463)) + (PORT d[11] (2810:2810:2810) (2995:2995:2995)) + (PORT d[12] (3841:3841:3841) (4091:4091:4091)) + (PORT clk (1854:1854:1854) (1880:1880:1880)) ) ) (TIMINGCHECK @@ -32308,8 +36227,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (3176:3176:3176) (3088:3088:3088)) + (PORT clk (1854:1854:1854) (1880:1880:1880)) + (PORT d[0] (2266:2266:2266) (2242:2242:2242)) ) ) ) @@ -32318,7 +36237,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) + (PORT clk (1855:1855:1855) (1881:1881:1881)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -32328,7 +36247,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) + (PORT clk (1817:1817:1817) (1843:1843:1843)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -32342,7 +36261,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) + (PORT clk (1002:1002:1002) (1006:1006:1006)) ) ) ) @@ -32351,7 +36270,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) + (PORT clk (1003:1003:1003) (1007:1007:1007)) ) ) ) @@ -32360,7 +36279,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) + (PORT clk (1003:1003:1003) (1007:1007:1007)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -32370,38 +36289,22 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) + (PORT clk (1003:1003:1003) (1007:1007:1007)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~88) + (INSTANCE D\[6\]\~101) (DELAY (ABSOLUTE - (PORT dataa (1285:1285:1285) (1292:1292:1292)) - (PORT datab (1157:1157:1157) (1165:1165:1165)) - (PORT datac (1614:1614:1614) (1636:1636:1636)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (1434:1434:1434) (1498:1498:1498)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (624:624:624) (685:685:685)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (1307:1307:1307) (1342:1342:1342)) + (PORT datab (1229:1229:1229) (1288:1288:1288)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (1047:1047:1047) (1066:1066:1066)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32409,16 +36312,32 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~111) + (INSTANCE D\[6\]\~102) (DELAY (ABSOLUTE - (PORT dataa (642:642:642) (683:683:683)) - (PORT datab (2010:2010:2010) (2117:2117:2117)) - (PORT datac (918:918:918) (1000:1000:1000)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1163:1163:1163) (1237:1237:1237)) + (PORT datab (309:309:309) (401:401:401)) + (PORT datac (180:180:180) (215:215:215)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~127) + (DELAY + (ABSOLUTE + (PORT dataa (1415:1415:1415) (1483:1483:1483)) + (PORT datab (2298:2298:2298) (2535:2535:2535)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -32434,29 +36353,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~86) + (INSTANCE D\[6\]\~99) (DELAY (ABSOLUTE - (PORT dataa (909:909:909) (967:967:967)) - (PORT datac (1544:1544:1544) (1682:1682:1682)) - (PORT datad (1984:1984:1984) (2079:2079:2079)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (1221:1221:1221) (1330:1330:1330)) + (PORT datac (2534:2534:2534) (2774:2774:2774)) + (PORT datad (1462:1462:1462) (1583:1583:1583)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~100) + (INSTANCE D\[6\]\~114) (DELAY (ABSOLUTE - (PORT dataa (952:952:952) (1002:1002:1002)) - (PORT datab (1379:1379:1379) (1383:1383:1383)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (1558:1558:1558) (1597:1597:1597)) + (PORT datab (435:435:435) (477:477:477)) + (PORT datac (597:597:597) (599:599:599)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32464,16 +36383,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~101) + (INSTANCE D\[6\]\~115) (DELAY (ABSOLUTE - (PORT dataa (947:947:947) (995:995:995)) - (PORT datab (894:894:894) (965:965:965)) - (PORT datac (1645:1645:1645) (1669:1669:1669)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (2243:2243:2243) (2321:2321:2321)) + (PORT datab (436:436:436) (477:477:477)) + (PORT datac (1209:1209:1209) (1322:1322:1322)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -32483,10 +36402,10 @@ (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) (DELAY (ABSOLUTE - (PORT dataa (275:275:275) (336:336:336)) - (PORT datab (1389:1389:1389) (1429:1429:1429)) - (PORT datac (938:938:938) (1004:1004:1004)) - (PORT datad (830:830:830) (833:833:833)) + (PORT dataa (1886:1886:1886) (1930:1930:1930)) + (PORT datab (426:426:426) (464:464:464)) + (PORT datac (349:349:349) (377:377:377)) + (PORT datad (1129:1129:1129) (1163:1163:1163)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -32494,44 +36413,12 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1684:1684:1684) (1826:1826:1826)) - (PORT datab (754:754:754) (857:857:857)) - (PORT datac (961:961:961) (1023:1023:1023)) - (PORT datad (1204:1204:1204) (1263:1263:1263)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) - (DELAY - (ABSOLUTE - (PORT dataa (971:971:971) (1041:1041:1041)) - (PORT datab (973:973:973) (1033:1033:1033)) - (PORT datac (961:961:961) (1024:1024:1024)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|data_pins_\|dout\[6\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT clk (1527:1527:1527) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) (PORT ena (841:841:841) (846:846:846)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -32548,37 +36435,11 @@ (DELAY (ABSOLUTE (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (1178:1178:1178) (1226:1226:1226)) - (PORT datac (224:224:224) (273:273:273)) - (PORT datad (210:210:210) (243:243:243)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|ir_\|opcode\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (195:195:195) (219:219:219)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1107:1107:1107) (1191:1191:1191)) - (PORT datab (909:909:909) (972:972:972)) - (PORT datac (661:661:661) (712:712:712)) - (PORT datad (375:375:375) (392:392:392)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT datab (252:252:252) (303:303:303)) + (PORT datac (575:575:575) (628:628:628)) + (PORT datad (216:216:216) (251:251:251)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32589,74 +36450,28 @@ (INSTANCE z80_\|ir_\|opcode\[6\]) (DELAY (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1557:1557:1557)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (694:694:694) (717:717:717)) + (PORT clrn (1577:1577:1577) (1558:1558:1558)) + (PORT ena (1917:1917:1917) (1918:1918:1918)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~0) + (INSTANCE z80_\|pla_decode_\|Equal13\~0) (DELAY (ABSOLUTE - (PORT datac (1703:1703:1703) (1754:1754:1754)) - (PORT datad (1223:1223:1223) (1322:1322:1322)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1499:1499:1499) (1573:1573:1573)) - (PORT datab (2298:2298:2298) (2366:2366:2366)) - (PORT datac (2132:2132:2132) (2282:2282:2282)) - (PORT datad (1454:1454:1454) (1538:1538:1538)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~2) - (DELAY - (ABSOLUTE - (PORT dataa (450:450:450) (502:502:502)) - (PORT datab (1649:1649:1649) (1644:1644:1644)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (1095:1095:1095) (1127:1127:1127)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) - (DELAY - (ABSOLUTE - (PORT dataa (1962:1962:1962) (2070:2070:2070)) - (PORT datab (1125:1125:1125) (1133:1133:1133)) - (PORT datac (2059:2059:2059) (2181:2181:2181)) - (PORT datad (179:179:179) (207:207:207)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (779:779:779) (847:847:847)) + (PORT datac (1845:1845:1845) (1972:1972:1972)) + (PORT datad (1691:1691:1691) (1766:1766:1766)) + (IOPATH dataa combout (303:303:303) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32664,14 +36479,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~15) + (INSTANCE z80_\|pla_decode_\|Equal38\~2) (DELAY (ABSOLUTE - (PORT dataa (1180:1180:1180) (1214:1214:1214)) - (PORT datab (292:292:292) (354:354:354)) - (PORT datac (259:259:259) (316:316:316)) - (PORT datad (245:245:245) (290:290:290)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (1757:1757:1757) (1850:1850:1850)) + (PORT datab (1655:1655:1655) (1806:1806:1806)) + (PORT datac (1039:1039:1039) (1104:1104:1104)) + (PORT datad (1816:1816:1816) (1892:1892:1892)) + (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -32680,15 +36495,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~16) + (INSTANCE z80_\|interrupts_\|iff1\~0) (DELAY (ABSOLUTE - (PORT dataa (1130:1130:1130) (1202:1202:1202)) - (PORT datab (1172:1172:1172) (1221:1221:1221)) - (PORT datac (419:419:419) (491:491:491)) - (PORT datad (660:660:660) (723:723:723)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (583:583:583) (608:608:608)) + (PORT datab (263:263:263) (345:345:345)) + (PORT datac (614:614:614) (677:677:677)) + (PORT datad (1147:1147:1147) (1181:1181:1181)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32696,43 +36511,171 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~17) + (INSTANCE z80_\|interrupts_\|iff1\~1) (DELAY (ABSOLUTE - (PORT dataa (952:952:952) (1002:1002:1002)) - (PORT datac (1667:1667:1667) (1748:1748:1748)) - (PORT datad (900:900:900) (923:923:923)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1670:1670:1670) (1698:1698:1698)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (366:366:366) (433:433:433)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~18) + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT datab (201:201:201) (240:240:240)) - (PORT datac (891:891:891) (913:913:913)) - (PORT datad (244:244:244) (286:286:286)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (760:760:760) (855:855:855)) + (PORT datad (307:307:307) (414:414:414)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|iff1) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1224:1224:1224) (1228:1228:1228)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (883:883:883)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (1149:1149:1149) (1212:1212:1212)) + (PORT datad (1552:1552:1552) (1679:1679:1679)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|int_armed) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1552:1552:1552)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|DFFE_inst44) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT asdata (1861:1861:1861) (1999:1999:1999)) + (PORT clrn (1590:1590:1590) (1567:1567:1567)) + (PORT ena (993:993:993) (1000:1000:1000)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|in_halt\~0) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (459:459:459)) + (PORT datab (294:294:294) (388:388:388)) + (PORT datad (252:252:252) (326:326:326)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~19) + (INSTANCE z80_\|pla_decode_\|Equal77\~1) (DELAY (ABSOLUTE - (PORT dataa (369:369:369) (390:390:390)) - (PORT datab (631:631:631) (659:659:659)) - (PORT datac (1160:1160:1160) (1204:1204:1204)) - (PORT datad (606:606:606) (623:623:623)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (2306:2306:2306) (2453:2453:2453)) + (PORT datab (1239:1239:1239) (1285:1285:1285)) + (PORT datac (1152:1152:1152) (1203:1203:1203)) + (PORT datad (1219:1219:1219) (1229:1229:1229)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|in_halt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (248:248:248)) + (PORT datab (703:703:703) (722:722:722)) + (PORT datad (905:905:905) (936:936:936)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|in_halt) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1590:1590:1590) (1567:1567:1567)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1544:1544:1544) (1649:1649:1649)) + (PORT datab (634:634:634) (661:661:661)) + (PORT datac (1250:1250:1250) (1279:1279:1279)) + (PORT datad (632:632:632) (654:654:654)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32740,14 +36683,222 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~20) + (INSTANCE z80_\|execute_\|fMRead\~35) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (999:999:999) (1032:1032:1032)) - (PORT datac (582:582:582) (614:614:614)) - (PORT datad (221:221:221) (263:263:263)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT dataa (220:220:220) (270:270:270)) + (PORT datab (218:218:218) (257:257:257)) + (PORT datac (590:590:590) (610:610:610)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (949:949:949)) + (PORT datab (631:631:631) (656:656:656)) + (PORT datac (835:835:835) (860:860:860)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (935:935:935)) + (PORT datab (1457:1457:1457) (1548:1548:1548)) + (PORT datac (589:589:589) (657:657:657)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (716:716:716)) + (PORT datab (861:861:861) (893:893:893)) + (PORT datac (854:854:854) (895:895:895)) + (PORT datad (1006:1006:1006) (1056:1056:1056)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1114:1114:1114) (1204:1204:1204)) + (PORT datab (1249:1249:1249) (1294:1294:1294)) + (PORT datac (1289:1289:1289) (1340:1340:1340)) + (PORT datad (1967:1967:1967) (2036:2036:2036)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (945:945:945)) + (PORT datab (1896:1896:1896) (1915:1915:1915)) + (PORT datac (1165:1165:1165) (1201:1201:1201)) + (PORT datad (827:827:827) (850:850:850)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~31) + (DELAY + (ABSOLUTE + (PORT dataa (453:453:453) (492:492:492)) + (PORT datab (1030:1030:1030) (1095:1095:1095)) + (PORT datac (1325:1325:1325) (1379:1379:1379)) + (PORT datad (1076:1076:1076) (1126:1126:1126)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (171:171:171) (202:202:202)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~37) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (677:677:677)) + (PORT datab (1463:1463:1463) (1517:1517:1517)) + (PORT datac (1482:1482:1482) (1554:1554:1554)) + (PORT datad (1619:1619:1619) (1692:1692:1692)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (660:660:660)) + (PORT datab (216:216:216) (261:261:261)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~24) + (DELAY + (ABSOLUTE + (PORT dataa (2969:2969:2969) (3039:3039:3039)) + (PORT datab (641:641:641) (702:702:702)) + (PORT datac (613:613:613) (625:625:625)) + (PORT datad (215:215:215) (241:241:241)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~25) + (DELAY + (ABSOLUTE + (PORT dataa (428:428:428) (478:478:478)) + (PORT datab (895:895:895) (922:922:922)) + (PORT datac (1121:1121:1121) (1142:1142:1142)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (645:645:645)) + (PORT datab (644:644:644) (686:686:686)) + (PORT datac (188:188:188) (228:228:228)) + (PORT datad (1149:1149:1149) (1174:1174:1174)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1159:1159:1159) (1207:1207:1207)) + (PORT datab (916:916:916) (951:951:951)) + (PORT datac (188:188:188) (231:231:231)) + (PORT datad (1147:1147:1147) (1187:1187:1187)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -32756,15 +36907,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~24) + (INSTANCE z80_\|execute_\|fMRead\~12) (DELAY (ABSOLUTE - (PORT dataa (1300:1300:1300) (1351:1351:1351)) - (PORT datab (940:940:940) (958:958:958)) - (PORT datac (1822:1822:1822) (1884:1884:1884)) - (PORT datad (931:931:931) (981:981:981)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (870:870:870) (921:921:921)) + (PORT datab (1617:1617:1617) (1648:1648:1648)) + (PORT datac (1115:1115:1115) (1177:1177:1177)) + (PORT datad (1411:1411:1411) (1437:1437:1437)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (886:886:886) (911:911:911)) + (PORT datac (648:648:648) (694:694:694)) + (PORT datad (1181:1181:1181) (1217:1217:1217)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (944:944:944)) + (PORT datab (1282:1282:1282) (1314:1314:1314)) + (PORT datac (648:648:648) (693:693:693)) + (PORT datad (1402:1402:1402) (1434:1434:1434)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32772,14 +36955,334 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~25) + (INSTANCE z80_\|execute_\|fMRead\~15) (DELAY (ABSOLUTE - (PORT dataa (647:647:647) (673:673:673)) - (PORT datab (255:255:255) (313:313:313)) - (PORT datac (175:175:175) (209:209:209)) - (PORT datad (945:945:945) (988:988:988)) + (PORT dataa (1449:1449:1449) (1502:1502:1502)) + (PORT datab (1085:1085:1085) (1133:1133:1133)) + (PORT datac (651:651:651) (687:687:687)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (966:966:966) (1015:1015:1015)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (257:257:257)) + (PORT datab (654:654:654) (703:703:703)) + (PORT datac (610:610:610) (654:654:654)) + (PORT datad (624:624:624) (633:633:633)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1183:1183:1183)) + (PORT datab (954:954:954) (995:995:995)) + (PORT datac (602:602:602) (625:625:625)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~36) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (952:952:952)) + (PORT datab (673:673:673) (691:691:691)) + (PORT datac (958:958:958) (973:973:973)) + (PORT datad (1082:1082:1082) (1103:1103:1103)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re) + (DELAY + (ABSOLUTE + (PORT datab (1455:1455:1455) (1545:1545:1545)) + (PORT datac (1016:1016:1016) (1022:1022:1022)) + (PORT datad (509:509:509) (525:525:525)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~103) + (DELAY + (ABSOLUTE + (PORT dataa (497:497:497) (577:577:577)) + (PORT datac (977:977:977) (1064:1064:1064)) + (PORT datad (614:614:614) (684:684:684)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (774:774:774) (853:853:853)) + (PORT datac (679:679:679) (730:730:730)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (431:431:431)) + (PORT datab (763:763:763) (849:849:849)) + (PORT datac (702:702:702) (763:763:763)) + (PORT datad (193:193:193) (229:229:229)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (870:870:870)) + (PORT datab (200:200:200) (238:238:238)) + (PORT datad (591:591:591) (603:603:603)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (730:730:730) (820:820:820)) + (PORT datac (935:935:935) (1021:1021:1021)) + (PORT datad (904:904:904) (975:975:975)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (781:781:781) (879:879:879)) + (PORT datab (652:652:652) (684:684:684)) + (PORT datac (896:896:896) (981:981:981)) + (PORT datad (267:267:267) (345:345:345)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (283:283:283) (376:376:376)) + (PORT datab (931:931:931) (1011:1011:1011)) + (PORT datac (928:928:928) (989:989:989)) + (PORT datad (753:753:753) (839:839:839)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~129) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (1020:1020:1020)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~1) + (DELAY + (ABSOLUTE + (PORT datab (789:789:789) (873:873:873)) + (PORT datac (683:683:683) (751:751:751)) + (PORT datad (735:735:735) (817:817:817)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~105) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (412:412:412)) + (PORT datab (740:740:740) (807:807:807)) + (PORT datac (888:888:888) (952:952:952)) + (PORT datad (199:199:199) (235:235:235)) (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (399:399:399)) + (PORT datab (624:624:624) (685:685:685)) + (PORT datac (677:677:677) (727:727:727)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~130) + (DELAY + (ABSOLUTE + (PORT dataa (786:786:786) (870:870:870)) + (PORT datab (416:416:416) (496:496:496)) + (PORT datad (936:936:936) (1016:1016:1016)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) + (DELAY + (ABSOLUTE + (PORT dataa (1227:1227:1227) (1254:1254:1254)) + (PORT datab (632:632:632) (647:647:647)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (1268:1268:1268) (1342:1342:1342)) + (PORT datab (242:242:242) (324:324:324)) + (PORT datac (882:882:882) (907:907:907)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -32788,79 +37291,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~39) (DELAY (ABSOLUTE - (PORT dataa (361:361:361) (501:501:501)) - (PORT datab (1351:1351:1351) (1413:1413:1413)) - (PORT datac (1147:1147:1147) (1181:1181:1181)) - (PORT datad (1196:1196:1196) (1243:1243:1243)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1065:1065:1065) (1137:1137:1137)) + (PORT datac (848:848:848) (867:867:867)) + (PORT datad (708:708:708) (782:782:782)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~100) (DELAY (ABSOLUTE - (PORT dataa (556:556:556) (578:578:578)) - (PORT datab (623:623:623) (651:651:651)) - (PORT datac (663:663:663) (695:695:695)) - (PORT datad (679:679:679) (697:697:697)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_yf) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (702:702:702)) - (PORT datab (900:900:900) (949:949:949)) - (PORT datac (666:666:666) (693:693:693)) - (PORT datad (888:888:888) (905:905:905)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (740:740:740) (830:830:830)) + (PORT datac (1262:1262:1262) (1334:1334:1334)) + (PORT datad (969:969:969) (1032:1032:1032)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~14) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) (DELAY (ABSOLUTE - (PORT dataa (969:969:969) (987:987:987)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (948:948:948) (982:982:982)) - (PORT datad (864:864:864) (880:880:880)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (1060:1060:1060) (1130:1130:1130)) + (PORT datac (759:759:759) (838:838:838)) + (PORT datad (189:189:189) (222:222:222)) + (IOPATH dataa combout (303:303:303) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32868,15 +37335,60 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~15) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~99) (DELAY (ABSOLUTE - (PORT dataa (685:685:685) (717:717:717)) - (PORT datab (1197:1197:1197) (1212:1212:1212)) - (PORT datac (1119:1119:1119) (1150:1150:1150)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (772:772:772) (855:855:855)) + (PORT datac (971:971:971) (1051:1051:1051)) + (PORT datad (645:645:645) (724:724:724)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (948:948:948)) + (PORT datab (888:888:888) (920:920:920)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1548:1548:1548) (1540:1540:1540)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~97) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (395:395:395)) + (PORT datab (1062:1062:1062) (1131:1131:1131)) + (PORT datac (708:708:708) (773:773:773)) + (PORT datad (190:190:190) (222:222:222)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -32884,671 +37396,383 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~107) + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~98) (DELAY (ABSOLUTE - (PORT dataa (1749:1749:1749) (1858:1858:1858)) - (PORT datab (1231:1231:1231) (1298:1298:1298)) - (PORT datac (1559:1559:1559) (1700:1700:1700)) - (PORT datad (1126:1126:1126) (1171:1171:1171)) + (PORT dataa (998:998:998) (1087:1087:1087)) + (PORT datab (920:920:920) (962:962:962)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1548:1548:1548) (1540:1540:1540)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (1168:1168:1168) (1214:1214:1214)) + (PORT datab (714:714:714) (771:771:771)) + (PORT datac (214:214:214) (291:291:291)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~108) + (DELAY + (ABSOLUTE + (PORT dataa (1236:1236:1236) (1327:1327:1327)) + (PORT datac (984:984:984) (1047:1047:1047)) + (PORT datad (651:651:651) (732:732:732)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~109) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (256:256:256)) + (PORT datab (229:229:229) (271:271:271)) + (PORT datac (705:705:705) (774:774:774)) + (PORT datad (204:204:204) (235:235:235)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~110) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (257:257:257)) + (PORT datab (923:923:923) (952:952:952)) + (PORT datad (573:573:573) (604:604:604)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1511:1511:1511) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1538:1538:1538)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~111) + (DELAY + (ABSOLUTE + (PORT dataa (1064:1064:1064) (1138:1138:1138)) + (PORT datab (420:420:420) (502:502:502)) + (PORT datac (998:998:998) (1056:1056:1056)) + (PORT datad (603:603:603) (663:663:663)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~112) + (DELAY + (ABSOLUTE + (PORT dataa (302:302:302) (404:404:404)) + (PORT datab (201:201:201) (240:240:240)) + (PORT datac (665:665:665) (729:729:729)) + (PORT datad (635:635:635) (652:652:652)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~132) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (907:907:907)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datad (711:711:711) (785:785:785)) (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~133) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (663:663:663)) + (PORT datab (759:759:759) (844:844:844)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1511:1511:1511) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1538:1538:1538)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (328:328:328)) + (PORT datab (909:909:909) (965:965:965)) + (PORT datac (217:217:217) (293:293:293)) + (PORT datad (1398:1398:1398) (1439:1439:1439)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~94) + (DELAY + (ABSOLUTE + (PORT dataa (1235:1235:1235) (1327:1327:1327)) + (PORT datab (1300:1300:1300) (1375:1375:1375)) + (PORT datac (685:685:685) (784:784:784)) + (PORT datad (717:717:717) (806:806:806)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (1235:1235:1235) (1326:1326:1326)) + (PORT datac (985:985:985) (1050:1050:1050)) + (PORT datad (653:653:653) (736:736:736)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~95) + (DELAY + (ABSOLUTE + (PORT dataa (1042:1042:1042) (1125:1125:1125)) + (PORT datab (948:948:948) (1016:1016:1016)) + (PORT datac (900:900:900) (914:914:914)) + (PORT datad (729:729:729) (803:803:803)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) (DELAY (ABSOLUTE - (PORT d[0] (1190:1190:1190) (1230:1230:1230)) - (PORT clk (1845:1845:1845) (1873:1873:1873)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (208:208:208) (249:249:249)) + (PORT datad (619:619:619) (630:630:630)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1511:1511:1511) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1538:1538:1538)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) + (HOLD d (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~91) (DELAY (ABSOLUTE - (PORT d[0] (3686:3686:3686) (3900:3900:3900)) - (PORT d[1] (1735:1735:1735) (1904:1904:1904)) - (PORT d[2] (3045:3045:3045) (3164:3164:3164)) - (PORT d[3] (1901:1901:1901) (2003:2003:2003)) - (PORT d[4] (2206:2206:2206) (2342:2342:2342)) - (PORT d[5] (2677:2677:2677) (2865:2865:2865)) - (PORT d[6] (2060:2060:2060) (2133:2133:2133)) - (PORT d[7] (2769:2769:2769) (2894:2894:2894)) - (PORT d[8] (3033:3033:3033) (3241:3241:3241)) - (PORT d[9] (2831:2831:2831) (2926:2926:2926)) - (PORT d[10] (3516:3516:3516) (3751:3751:3751)) - (PORT d[11] (1807:1807:1807) (1907:1907:1907)) - (PORT d[12] (2081:2081:2081) (2168:2168:2168)) - (PORT clk (1842:1842:1842) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1939:1939:1939) (1956:1956:1956)) - (PORT clk (1842:1842:1842) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1873:1873:1873)) - (PORT d[0] (2676:2676:2676) (2715:2715:2715)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1805:1805:1805) (1832:1832:1832)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (990:990:990) (995:995:995)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1180:1180:1180) (1209:1209:1209)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3984:3984:3984) (4216:4216:4216)) - (PORT d[1] (1704:1704:1704) (1855:1855:1855)) - (PORT d[2] (3307:3307:3307) (3443:3443:3443)) - (PORT d[3] (1880:1880:1880) (1997:1997:1997)) - (PORT d[4] (1863:1863:1863) (1963:1963:1963)) - (PORT d[5] (1643:1643:1643) (1769:1769:1769)) - (PORT d[6] (1761:1761:1761) (1817:1817:1817)) - (PORT d[7] (3056:3056:3056) (3189:3189:3189)) - (PORT d[8] (3324:3324:3324) (3551:3551:3551)) - (PORT d[9] (2869:2869:2869) (2985:2985:2985)) - (PORT d[10] (3454:3454:3454) (3652:3652:3652)) - (PORT d[11] (1540:1540:1540) (1618:1618:1618)) - (PORT d[12] (1726:1726:1726) (1787:1787:1787)) - (PORT clk (1840:1840:1840) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1932:1932:1932) (1890:1890:1890)) - (PORT clk (1840:1840:1840) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1871:1871:1871)) - (PORT d[0] (2406:2406:2406) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1803:1803:1803) (1830:1830:1830)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (988:988:988) (993:993:993)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1218:1218:1218) (1268:1268:1268)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3686:3686:3686) (3901:3901:3901)) - (PORT d[1] (1692:1692:1692) (1858:1858:1858)) - (PORT d[2] (2977:2977:2977) (3118:3118:3118)) - (PORT d[3] (2124:2124:2124) (2230:2230:2230)) - (PORT d[4] (2237:2237:2237) (2352:2352:2352)) - (PORT d[5] (2684:2684:2684) (2875:2875:2875)) - (PORT d[6] (1801:1801:1801) (1880:1880:1880)) - (PORT d[7] (2772:2772:2772) (2901:2901:2901)) - (PORT d[8] (3346:3346:3346) (3575:3575:3575)) - (PORT d[9] (2889:2889:2889) (3004:3004:3004)) - (PORT d[10] (3484:3484:3484) (3709:3709:3709)) - (PORT d[11] (1816:1816:1816) (1924:1924:1924)) - (PORT d[12] (2023:2023:2023) (2090:2090:2090)) - (PORT clk (1840:1840:1840) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1889:1889:1889) (1883:1883:1883)) - (PORT clk (1840:1840:1840) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1871:1871:1871)) - (PORT d[0] (2482:2482:2482) (2488:2488:2488)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1803:1803:1803) (1830:1830:1830)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (988:988:988) (993:993:993)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + (PORT dataa (509:509:509) (588:588:588)) + (PORT datab (887:887:887) (942:942:942)) + (PORT datac (616:616:616) (637:637:637)) + (PORT datad (190:190:190) (222:222:222)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~4) + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~92) (DELAY (ABSOLUTE - (PORT dataa (1446:1446:1446) (1499:1499:1499)) - (PORT datab (1431:1431:1431) (1517:1517:1517)) - (PORT datac (1141:1141:1141) (1132:1132:1132)) - (PORT datad (1111:1111:1111) (1136:1136:1136)) + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (973:973:973) (1052:1052:1052)) + (PORT datad (462:462:462) (533:533:533)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) (DELAY (ABSOLUTE - (PORT d[0] (1272:1272:1272) (1326:1326:1326)) - (PORT clk (1855:1855:1855) (1883:1883:1883)) + (PORT clk (1504:1504:1504) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) + (HOLD d (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~72) (DELAY (ABSOLUTE - (PORT d[0] (2887:2887:2887) (3004:3004:3004)) - (PORT d[1] (2662:2662:2662) (2916:2916:2916)) - (PORT d[2] (1218:1218:1218) (1257:1257:1257)) - (PORT d[3] (1701:1701:1701) (1750:1750:1750)) - (PORT d[4] (2885:2885:2885) (3119:3119:3119)) - (PORT d[5] (2382:2382:2382) (2607:2607:2607)) - (PORT d[6] (1263:1263:1263) (1339:1339:1339)) - (PORT d[7] (1323:1323:1323) (1404:1404:1404)) - (PORT d[8] (1739:1739:1739) (1814:1814:1814)) - (PORT d[9] (1262:1262:1262) (1335:1335:1335)) - (PORT d[10] (2409:2409:2409) (2560:2560:2560)) - (PORT d[11] (3166:3166:3166) (3381:3381:3381)) - (PORT d[12] (2205:2205:2205) (2307:2307:2307)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1501:1501:1501) (1496:1496:1496)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (PORT d[0] (2128:2128:2128) (2120:2120:2120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1842:1842:1842)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + (PORT dataa (711:711:711) (751:751:751)) + (PORT datab (240:240:240) (322:322:322)) + (PORT datac (2427:2427:2427) (2603:2603:2603)) + (PORT datad (882:882:882) (935:935:935)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) + (INSTANCE D\[3\]\~76) (DELAY (ABSOLUTE - (PORT dataa (1130:1130:1130) (1175:1175:1175)) - (PORT datab (1704:1704:1704) (1781:1781:1781)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1426:1426:1426) (1482:1482:1482)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (888:888:888) (920:920:920)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (344:344:344) (365:365:365)) + (PORT datad (615:615:615) (626:626:626)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~122) + (DELAY + (ABSOLUTE + (PORT dataa (1105:1105:1105) (1131:1131:1131)) + (PORT datab (1259:1259:1259) (1374:1374:1374)) + (PORT datac (2575:2575:2575) (2806:2806:2806)) + (PORT datad (635:635:635) (671:671:671)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1607:1607:1607) (1720:1720:1720)) - (PORT clk (1852:1852:1852) (1880:1880:1880)) + (PORT d[0] (1120:1120:1120) (1113:1113:1113)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) ) ) (TIMINGCHECK @@ -33557,307 +37781,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3186:3186:3186) (3300:3300:3300)) - (PORT d[1] (2007:2007:2007) (2188:2188:2188)) - (PORT d[2] (2193:2193:2193) (2290:2290:2290)) - (PORT d[3] (1861:1861:1861) (1989:1989:1989)) - (PORT d[4] (2485:2485:2485) (2606:2606:2606)) - (PORT d[5] (2236:2236:2236) (2402:2402:2402)) - (PORT d[6] (1711:1711:1711) (1755:1755:1755)) - (PORT d[7] (1687:1687:1687) (1776:1776:1776)) - (PORT d[8] (2608:2608:2608) (2791:2791:2791)) - (PORT d[9] (1955:1955:1955) (2077:2077:2077)) - (PORT d[10] (2011:2011:2011) (2111:2111:2111)) - (PORT d[11] (2425:2425:2425) (2555:2555:2555)) - (PORT d[12] (2552:2552:2552) (2625:2625:2625)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2563:2563:2563) (2536:2536:2536)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (PORT d[0] (3968:3968:3968) (4054:4054:4054)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1805:1805:1805)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1738:1738:1738) (1727:1727:1727)) - (PORT clk (1817:1817:1817) (1811:1811:1811)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4391:4391:4391) (4458:4458:4458)) - (PORT d[1] (4215:4215:4215) (4261:4261:4261)) - (PORT d[2] (4322:4322:4322) (4388:4388:4388)) - (PORT d[3] (4683:4683:4683) (4718:4718:4718)) - (PORT d[4] (4355:4355:4355) (4366:4366:4366)) - (PORT d[5] (4618:4618:4618) (4672:4672:4672)) - (PORT d[6] (4745:4745:4745) (4781:4781:4781)) - (PORT d[7] (4330:4330:4330) (4399:4399:4399)) - (PORT d[8] (4420:4420:4420) (4455:4455:4455)) - (PORT d[9] (4477:4477:4477) (4721:4721:4721)) - (PORT d[10] (4604:4604:4604) (4600:4600:4600)) - (PORT d[11] (4406:4406:4406) (4437:4437:4437)) - (PORT d[12] (4503:4503:4503) (4638:4638:4638)) - (PORT clk (1813:1813:1813) (1807:1807:1807)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1817:1817:1817) (1811:1811:1811)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2857:2857:2857) (2972:2972:2972)) - (PORT d[1] (1730:1730:1730) (1897:1897:1897)) - (PORT d[2] (1950:1950:1950) (2070:2070:2070)) - (PORT d[3] (1897:1897:1897) (2023:2023:2023)) - (PORT d[4] (2739:2739:2739) (2895:2895:2895)) - (PORT d[5] (2232:2232:2232) (2412:2412:2412)) - (PORT d[6] (1964:1964:1964) (2031:2031:2031)) - (PORT d[7] (2136:2136:2136) (2268:2268:2268)) - (PORT d[8] (2383:2383:2383) (2561:2561:2561)) - (PORT d[9] (1973:1973:1973) (2079:2079:2079)) - (PORT d[10] (1681:1681:1681) (1740:1740:1740)) - (PORT d[11] (2036:2036:2036) (2101:2101:2101)) - (PORT d[12] (2509:2509:2509) (2578:2578:2578)) - (PORT clk (1857:1857:1857) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1882:1882:1882)) - (PORT d[0] (2716:2716:2716) (2794:2794:2794)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3922:3922:3922) (4160:4160:4160)) - (PORT d[1] (2875:2875:2875) (3108:3108:3108)) - (PORT d[2] (2719:2719:2719) (2815:2815:2815)) - (PORT d[3] (2274:2274:2274) (2436:2436:2436)) - (PORT d[4] (2511:2511:2511) (2691:2691:2691)) - (PORT d[5] (2520:2520:2520) (2696:2696:2696)) - (PORT d[6] (1898:1898:1898) (2018:2018:2018)) - (PORT d[7] (2284:2284:2284) (2398:2398:2398)) - (PORT d[8] (3090:3090:3090) (3363:3363:3363)) - (PORT d[9] (2691:2691:2691) (2835:2835:2835)) - (PORT d[10] (4531:4531:4531) (4774:4774:4774)) - (PORT d[11] (1925:1925:1925) (2083:2083:2083)) - (PORT d[12] (2422:2422:2422) (2553:2553:2553)) + (PORT d[0] (2540:2540:2540) (2718:2718:2718)) + (PORT d[1] (3611:3611:3611) (3828:3828:3828)) + (PORT d[2] (2390:2390:2390) (2485:2485:2485)) + (PORT d[3] (4294:4294:4294) (4502:4502:4502)) + (PORT d[4] (3192:3192:3192) (3431:3431:3431)) + (PORT d[5] (4755:4755:4755) (4922:4922:4922)) + (PORT d[6] (2539:2539:2539) (2642:2642:2642)) + (PORT d[7] (1407:1407:1407) (1444:1444:1444)) + (PORT d[8] (2834:2834:2834) (2992:2992:2992)) + (PORT d[9] (1811:1811:1811) (1840:1840:1840)) + (PORT d[10] (1723:1723:1723) (1759:1759:1759)) + (PORT d[11] (3413:3413:3413) (3683:3683:3683)) + (PORT d[12] (4600:4600:4600) (4890:4890:4890)) (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) @@ -33867,27 +37806,70 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) (DELAY (ABSOLUTE + (PORT d[0] (1678:1678:1678) (1622:1622:1622)) (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (3644:3644:3644) (3567:3567:3567)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (2247:2247:2247) (2230:2230:2230)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1820:1820:1820) (1846:1846:1846)) @@ -33901,7 +37883,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1005:1005:1005) (1009:1009:1009)) @@ -33910,7 +37892,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -33919,7 +37901,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -33929,7 +37911,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -33938,12 +37920,28 @@ ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~79) (DELAY (ABSOLUTE - (PORT d[0] (1502:1502:1502) (1566:1566:1566)) - (PORT clk (1869:1869:1869) (1895:1895:1895)) + (PORT dataa (1166:1166:1166) (1276:1276:1276)) + (PORT datab (667:667:667) (705:705:705)) + (PORT datac (1386:1386:1386) (1467:1467:1467)) + (PORT datad (1101:1101:1101) (1113:1113:1113)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1145:1145:1145) (1137:1137:1137)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) ) ) (TIMINGCHECK @@ -33952,23 +37950,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2818:2818:2818) (2896:2896:2896)) - (PORT d[1] (2077:2077:2077) (2294:2294:2294)) - (PORT d[2] (2223:2223:2223) (2370:2370:2370)) - (PORT d[3] (2274:2274:2274) (2375:2375:2375)) - (PORT d[4] (2928:2928:2928) (3204:3204:3204)) - (PORT d[5] (2379:2379:2379) (2550:2550:2550)) - (PORT d[6] (1572:1572:1572) (1678:1678:1678)) - (PORT d[7] (1564:1564:1564) (1666:1666:1666)) - (PORT d[8] (2761:2761:2761) (2991:2991:2991)) - (PORT d[9] (2092:2092:2092) (2225:2225:2225)) - (PORT d[10] (1872:1872:1872) (1997:1997:1997)) - (PORT d[11] (2890:2890:2890) (3011:3011:3011)) - (PORT d[12] (1605:1605:1605) (1686:1686:1686)) - (PORT clk (1866:1866:1866) (1891:1891:1891)) + (PORT d[0] (1692:1692:1692) (1821:1821:1821)) + (PORT d[1] (2831:2831:2831) (2904:2904:2904)) + (PORT d[2] (2412:2412:2412) (2479:2479:2479)) + (PORT d[3] (4272:4272:4272) (4479:4479:4479)) + (PORT d[4] (990:990:990) (1023:1023:1023)) + (PORT d[5] (2242:2242:2242) (2271:2271:2271)) + (PORT d[6] (2540:2540:2540) (2643:2643:2643)) + (PORT d[7] (1371:1371:1371) (1386:1386:1386)) + (PORT d[8] (2806:2806:2806) (2960:2960:2960)) + (PORT d[9] (1487:1487:1487) (1517:1517:1517)) + (PORT d[10] (1989:1989:1989) (2026:2026:2026)) + (PORT d[11] (3414:3414:3414) (3684:3684:3684)) + (PORT d[12] (4681:4681:4681) (4989:4989:4989)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) ) ) (TIMINGCHECK @@ -33977,11 +37975,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2511:2511:2511) (2509:2509:2509)) - (PORT clk (1866:1866:1866) (1891:1891:1891)) + (PORT d[0] (2538:2538:2538) (2548:2548:2548)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) ) ) (TIMINGCHECK @@ -33990,17 +37988,4629 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1869:1869:1869) (1895:1895:1895)) - (PORT d[0] (2908:2908:2908) (2850:2850:2850)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT d[0] (2226:2226:2226) (2231:2231:2231)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (743:743:743) (772:772:772)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3064:3064:3064) (3319:3319:3319)) + (PORT d[1] (1624:1624:1624) (1726:1726:1726)) + (PORT d[2] (1003:1003:1003) (1056:1056:1056)) + (PORT d[3] (954:954:954) (1004:1004:1004)) + (PORT d[4] (3267:3267:3267) (3445:3445:3445)) + (PORT d[5] (969:969:969) (999:999:999)) + (PORT d[6] (1577:1577:1577) (1697:1697:1697)) + (PORT d[7] (987:987:987) (1009:1009:1009)) + (PORT d[8] (1275:1275:1275) (1343:1343:1343)) + (PORT d[9] (1064:1064:1064) (1130:1130:1130)) + (PORT d[10] (1030:1030:1030) (1088:1088:1088)) + (PORT d[11] (2187:2187:2187) (2344:2344:2344)) + (PORT d[12] (1076:1076:1076) (1160:1160:1160)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (956:956:956) (917:917:917)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (2993:2993:2993) (3045:3045:3045)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (997:997:997) (1025:1025:1025)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3012:3012:3012) (3251:3251:3251)) + (PORT d[1] (1609:1609:1609) (1697:1697:1697)) + (PORT d[2] (983:983:983) (1016:1016:1016)) + (PORT d[3] (961:961:961) (994:994:994)) + (PORT d[4] (1434:1434:1434) (1457:1457:1457)) + (PORT d[5] (948:948:948) (977:977:977)) + (PORT d[6] (1862:1862:1862) (1998:1998:1998)) + (PORT d[7] (940:940:940) (959:959:959)) + (PORT d[8] (1274:1274:1274) (1339:1339:1339)) + (PORT d[9] (752:752:752) (813:813:813)) + (PORT d[10] (755:755:755) (815:815:815)) + (PORT d[11] (2517:2517:2517) (2676:2676:2676)) + (PORT d[12] (773:773:773) (837:837:837)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (682:682:682) (624:624:624)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT d[0] (1782:1782:1782) (1777:1777:1777)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2263:2263:2263) (2427:2427:2427)) + (PORT d[1] (2806:2806:2806) (2855:2855:2855)) + (PORT d[2] (2405:2405:2405) (2483:2483:2483)) + (PORT d[3] (4558:4558:4558) (4765:4765:4765)) + (PORT d[4] (1002:1002:1002) (1050:1050:1050)) + (PORT d[5] (2195:2195:2195) (2238:2238:2238)) + (PORT d[6] (924:924:924) (944:944:944)) + (PORT d[7] (1330:1330:1330) (1332:1332:1332)) + (PORT d[8] (2826:2826:2826) (2976:2976:2976)) + (PORT d[9] (1473:1473:1473) (1523:1523:1523)) + (PORT d[10] (1998:1998:1998) (2047:2047:2047)) + (PORT d[11] (3718:3718:3718) (4008:4008:4008)) + (PORT d[12] (4709:4709:4709) (5022:5022:5022)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1880:1880:1880)) + (PORT d[0] (1305:1305:1305) (1337:1337:1337)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (1966:1966:1966) (2027:2027:2027)) + (PORT datab (1520:1520:1520) (1598:1598:1598)) + (PORT datac (885:885:885) (908:908:908)) + (PORT datad (1061:1061:1061) (1077:1077:1077)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~80) + (DELAY + (ABSOLUTE + (PORT datab (915:915:915) (934:934:934)) + (PORT datac (1386:1386:1386) (1466:1466:1466)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (1493:1493:1493) (1589:1589:1589)) + (PORT datab (1130:1130:1130) (1152:1152:1152)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (1801:1801:1801) (1899:1899:1899)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1438:1438:1438) (1489:1489:1489)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2489:2489:2489) (2600:2600:2600)) + (PORT d[1] (2698:2698:2698) (2838:2838:2838)) + (PORT d[2] (2572:2572:2572) (2698:2698:2698)) + (PORT d[3] (3356:3356:3356) (3488:3488:3488)) + (PORT d[4] (2297:2297:2297) (2449:2449:2449)) + (PORT d[5] (3794:3794:3794) (3901:3901:3901)) + (PORT d[6] (2564:2564:2564) (2676:2676:2676)) + (PORT d[7] (3403:3403:3403) (3457:3457:3457)) + (PORT d[8] (2931:2931:2931) (3032:3032:3032)) + (PORT d[9] (2737:2737:2737) (2834:2834:2834)) + (PORT d[10] (2604:2604:2604) (2714:2714:2714)) + (PORT d[11] (2512:2512:2512) (2702:2702:2702)) + (PORT d[12] (3523:3523:3523) (3743:3743:3743)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2846:2846:2846) (2893:2893:2893)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (3535:3535:3535) (3484:3484:3484)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1813:1813:1813)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2458:2458:2458) (2451:2451:2451)) + (PORT clk (1825:1825:1825) (1819:1819:1819)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4479:4479:4479) (4514:4514:4514)) + (PORT d[1] (4465:4465:4465) (4517:4517:4517)) + (PORT d[2] (4544:4544:4544) (4551:4551:4551)) + (PORT d[3] (4403:4403:4403) (4415:4415:4415)) + (PORT d[4] (4292:4292:4292) (4432:4432:4432)) + (PORT d[5] (4375:4375:4375) (4440:4440:4440)) + (PORT d[6] (4446:4446:4446) (4486:4486:4486)) + (PORT d[7] (4358:4358:4358) (4399:4399:4399)) + (PORT d[8] (4409:4409:4409) (4489:4489:4489)) + (PORT d[9] (4419:4419:4419) (4498:4498:4498)) + (PORT d[10] (4270:4270:4270) (4305:4305:4305)) + (PORT d[11] (4393:4393:4393) (4493:4493:4493)) + (PORT d[12] (4247:4247:4247) (4253:4253:4253)) + (PORT clk (1821:1821:1821) (1815:1815:1815)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1819:1819:1819)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1815:1815:1815)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~124) + (DELAY + (ABSOLUTE + (PORT dataa (2618:2618:2618) (2852:2852:2852)) + (PORT datab (2469:2469:2469) (2595:2595:2595)) + (PORT datac (1575:1575:1575) (1686:1686:1686)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1395:1395:1395) (1438:1438:1438)) + (PORT clk (1855:1855:1855) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1950:1950:1950) (2069:2069:2069)) + (PORT d[1] (3022:3022:3022) (3167:3167:3167)) + (PORT d[2] (1806:1806:1806) (1910:1910:1910)) + (PORT d[3] (3658:3658:3658) (3808:3808:3808)) + (PORT d[4] (2619:2619:2619) (2778:2778:2778)) + (PORT d[5] (4118:4118:4118) (4230:4230:4230)) + (PORT d[6] (2735:2735:2735) (2827:2827:2827)) + (PORT d[7] (1984:1984:1984) (2046:2046:2046)) + (PORT d[8] (1994:1994:1994) (2040:2040:2040)) + (PORT d[9] (2437:2437:2437) (2548:2548:2548)) + (PORT d[10] (2646:2646:2646) (2757:2757:2757)) + (PORT d[11] (2789:2789:2789) (2994:2994:2994)) + (PORT d[12] (4582:4582:4582) (4832:4832:4832)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1561:1561:1561) (1515:1515:1515)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1883:1883:1883)) + (PORT d[0] (3203:3203:3203) (3240:3240:3240)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1808:1808:1808)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2190:2190:2190) (2181:2181:2181)) + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4546:4546:4546) (4580:4580:4580)) + (PORT d[1] (4461:4461:4461) (4513:4513:4513)) + (PORT d[2] (4466:4466:4466) (4476:4476:4476)) + (PORT d[3] (4422:4422:4422) (4460:4460:4460)) + (PORT d[4] (4363:4363:4363) (4523:4523:4523)) + (PORT d[5] (4348:4348:4348) (4415:4415:4415)) + (PORT d[6] (4445:4445:4445) (4467:4467:4467)) + (PORT d[7] (4345:4345:4345) (4449:4449:4449)) + (PORT d[8] (4480:4480:4480) (4560:4560:4560)) + (PORT d[9] (4577:4577:4577) (4641:4641:4641)) + (PORT d[10] (4311:4311:4311) (4390:4390:4390)) + (PORT d[11] (4436:4436:4436) (4532:4532:4532)) + (PORT d[12] (4251:4251:4251) (4274:4274:4274)) + (PORT clk (1816:1816:1816) (1810:1810:1810)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2469:2469:2469) (2602:2602:2602)) + (PORT d[1] (2377:2377:2377) (2524:2524:2524)) + (PORT d[2] (2274:2274:2274) (2431:2431:2431)) + (PORT d[3] (2180:2180:2180) (2330:2330:2330)) + (PORT d[4] (2086:2086:2086) (2172:2172:2172)) + (PORT d[5] (2417:2417:2417) (2540:2540:2540)) + (PORT d[6] (2442:2442:2442) (2606:2606:2606)) + (PORT d[7] (3149:3149:3149) (3211:3211:3211)) + (PORT d[8] (2864:2864:2864) (2942:2942:2942)) + (PORT d[9] (2362:2362:2362) (2550:2550:2550)) + (PORT d[10] (3296:3296:3296) (3440:3440:3440)) + (PORT d[11] (2098:2098:2098) (2200:2200:2200)) + (PORT d[12] (2283:2283:2283) (2461:2461:2461)) + (PORT clk (1859:1859:1859) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (PORT d[0] (2575:2575:2575) (2667:2667:2667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1848:1848:1848)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1007:1007:1007) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1012:1012:1012)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1012:1012:1012)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1012:1012:1012)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~123) + (DELAY + (ABSOLUTE + (PORT dataa (2613:2613:2613) (2845:2845:2845)) + (PORT datab (2470:2470:2470) (2597:2597:2597)) + (PORT datac (1305:1305:1305) (1374:1374:1374)) + (PORT datad (1662:1662:1662) (1719:1719:1719)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (1252:1252:1252) (1292:1292:1292)) + (PORT datab (741:741:741) (851:851:851)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (1965:1965:1965) (2023:2023:2023)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~108) + (DELAY + (ABSOLUTE + (PORT dataa (1550:1550:1550) (1580:1580:1580)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~109) + (DELAY + (ABSOLUTE + (PORT dataa (2783:2783:2783) (2886:2886:2886)) + (PORT datab (938:938:938) (1032:1032:1032)) + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (1506:1506:1506) (1530:1530:1530)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (297:297:297)) + (PORT datab (859:859:859) (885:885:885)) + (PORT datac (623:623:623) (656:656:656)) + (PORT datad (1129:1129:1129) (1160:1160:1160)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (420:420:420) (450:450:450)) + (PORT datac (363:363:363) (431:431:431)) + (PORT datad (386:386:386) (412:412:412)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1294:1294:1294) (1315:1315:1315)) + (PORT datab (372:372:372) (397:397:397)) + (PORT datac (825:825:825) (876:876:876)) + (PORT datad (567:567:567) (578:578:578)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1558:1558:1558)) + (PORT ena (1940:1940:1940) (1962:1962:1962)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2251:2251:2251) (2328:2328:2328)) + (PORT datac (1575:1575:1575) (1707:1707:1707)) + (PORT datad (1688:1688:1688) (1747:1747:1747)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (897:897:897)) + (PORT datab (1870:1870:1870) (1946:1946:1946)) + (PORT datac (1151:1151:1151) (1176:1176:1176)) + (PORT datad (624:624:624) (661:661:661)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (678:678:678)) + (PORT datab (204:204:204) (246:246:246)) + (PORT datac (1170:1170:1170) (1209:1209:1209)) + (PORT datad (844:844:844) (899:899:899)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (458:458:458)) + (PORT datab (603:603:603) (621:621:621)) + (PORT datad (1132:1132:1132) (1160:1160:1160)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1500:1500:1500) (1546:1546:1546)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2373:2373:2373) (2567:2567:2567)) + (PORT d[1] (2551:2551:2551) (2651:2651:2651)) + (PORT d[2] (1549:1549:1549) (1634:1634:1634)) + (PORT d[3] (1265:1265:1265) (1340:1340:1340)) + (PORT d[4] (2004:2004:2004) (2083:2083:2083)) + (PORT d[5] (1260:1260:1260) (1335:1335:1335)) + (PORT d[6] (1712:1712:1712) (1742:1742:1742)) + (PORT d[7] (2350:2350:2350) (2481:2481:2481)) + (PORT d[8] (2475:2475:2475) (2633:2633:2633)) + (PORT d[9] (1038:1038:1038) (1095:1095:1095)) + (PORT d[10] (1743:1743:1743) (1843:1843:1843)) + (PORT d[11] (1460:1460:1460) (1528:1528:1528)) + (PORT d[12] (1011:1011:1011) (1068:1068:1068)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1776:1776:1776) (1775:1775:1775)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT d[0] (2106:2106:2106) (2095:2095:2095)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1472:1472:1472) (1514:1514:1514)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2336:2336:2336) (2510:2510:2510)) + (PORT d[1] (1981:1981:1981) (2064:2064:2064)) + (PORT d[2] (1851:1851:1851) (1954:1954:1954)) + (PORT d[3] (2217:2217:2217) (2311:2311:2311)) + (PORT d[4] (2028:2028:2028) (2096:2096:2096)) + (PORT d[5] (1586:1586:1586) (1680:1680:1680)) + (PORT d[6] (1724:1724:1724) (1771:1771:1771)) + (PORT d[7] (2272:2272:2272) (2376:2376:2376)) + (PORT d[8] (2487:2487:2487) (2660:2660:2660)) + (PORT d[9] (1183:1183:1183) (1248:1248:1248)) + (PORT d[10] (1648:1648:1648) (1719:1719:1719)) + (PORT d[11] (1194:1194:1194) (1243:1243:1243)) + (PORT d[12] (1050:1050:1050) (1129:1129:1129)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1540:1540:1540) (1561:1561:1561)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (1987:1987:1987) (1984:1984:1984)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (914:914:914) (933:933:933)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2902:2902:2902) (3119:3119:3119)) + (PORT d[1] (3573:3573:3573) (3763:3763:3763)) + (PORT d[2] (1956:1956:1956) (2034:2034:2034)) + (PORT d[3] (3972:3972:3972) (4152:4152:4152)) + (PORT d[4] (3177:3177:3177) (3389:3389:3389)) + (PORT d[5] (4728:4728:4728) (4845:4845:4845)) + (PORT d[6] (2221:2221:2221) (2292:2292:2292)) + (PORT d[7] (1688:1688:1688) (1718:1718:1718)) + (PORT d[8] (3114:3114:3114) (3291:3291:3291)) + (PORT d[9] (1819:1819:1819) (1883:1883:1883)) + (PORT d[10] (2034:2034:2034) (2098:2098:2098)) + (PORT d[11] (3078:3078:3078) (3310:3310:3310)) + (PORT d[12] (4587:4587:4587) (4856:4856:4856)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2278:2278:2278) (2264:2264:2264)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (2520:2520:2520) (2539:2539:2539)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1187:1187:1187) (1212:1212:1212)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2569:2569:2569) (2756:2756:2756)) + (PORT d[1] (3637:3637:3637) (3813:3813:3813)) + (PORT d[2] (2109:2109:2109) (2190:2190:2190)) + (PORT d[3] (4259:4259:4259) (4451:4451:4451)) + (PORT d[4] (3209:3209:3209) (3444:3444:3444)) + (PORT d[5] (4699:4699:4699) (4855:4855:4855)) + (PORT d[6] (2574:2574:2574) (2667:2667:2667)) + (PORT d[7] (1420:1420:1420) (1439:1439:1439)) + (PORT d[8] (3134:3134:3134) (3310:3310:3310)) + (PORT d[9] (1832:1832:1832) (1888:1888:1888)) + (PORT d[10] (2003:2003:2003) (2057:2057:2057)) + (PORT d[11] (3398:3398:3398) (3651:3651:3651)) + (PORT d[12] (4571:4571:4571) (4836:4836:4836)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1591:1591:1591) (1527:1527:1527)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (2499:2499:2499) (2455:2455:2455)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (844:844:844)) + (PORT datab (1180:1180:1180) (1276:1276:1276)) + (PORT datac (1196:1196:1196) (1251:1251:1251)) + (PORT datad (1097:1097:1097) (1132:1132:1132)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1234:1234:1234) (1290:1290:1290)) + (PORT datab (1272:1272:1272) (1332:1332:1332)) + (PORT datac (1738:1738:1738) (1814:1814:1814)) + (PORT datad (313:313:313) (331:331:331)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~97) + (DELAY + (ABSOLUTE + (PORT dataa (2634:2634:2634) (2764:2764:2764)) + (PORT datab (1940:1940:1940) (2085:2085:2085)) + (PORT datac (2774:2774:2774) (3006:3006:3006)) + (PORT datad (2211:2211:2211) (2282:2282:2282)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1585:1585:1585) (1668:1668:1668)) + (PORT clk (1858:1858:1858) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3186:3186:3186) (3418:3418:3418)) + (PORT d[1] (3339:3339:3339) (3475:3475:3475)) + (PORT d[2] (2251:2251:2251) (2357:2357:2357)) + (PORT d[3] (3642:3642:3642) (3797:3797:3797)) + (PORT d[4] (2928:2928:2928) (3138:3138:3138)) + (PORT d[5] (4390:4390:4390) (4507:4507:4507)) + (PORT d[6] (1780:1780:1780) (1859:1859:1859)) + (PORT d[7] (1974:1974:1974) (2019:2019:2019)) + (PORT d[8] (2011:2011:2011) (2055:2055:2055)) + (PORT d[9] (2117:2117:2117) (2203:2203:2203)) + (PORT d[10] (2341:2341:2341) (2430:2430:2430)) + (PORT d[11] (2795:2795:2795) (3008:3008:3008)) + (PORT d[12] (4293:4293:4293) (4549:4549:4549)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1653:1653:1653) (1635:1635:1635)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT d[0] (2870:2870:2870) (2886:2886:2886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1813:1813:1813) (1811:1811:1811)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2178:2178:2178) (2158:2158:2158)) + (PORT clk (1823:1823:1823) (1817:1817:1817)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4523:4523:4523) (4579:4579:4579)) + (PORT d[1] (4471:4471:4471) (4537:4537:4537)) + (PORT d[2] (4520:4520:4520) (4549:4549:4549)) + (PORT d[3] (4434:4434:4434) (4448:4448:4448)) + (PORT d[4] (4399:4399:4399) (4562:4562:4562)) + (PORT d[5] (4336:4336:4336) (4388:4388:4388)) + (PORT d[6] (4419:4419:4419) (4461:4461:4461)) + (PORT d[7] (4386:4386:4386) (4436:4436:4436)) + (PORT d[8] (4545:4545:4545) (4646:4646:4646)) + (PORT d[9] (4542:4542:4542) (4602:4602:4602)) + (PORT d[10] (4589:4589:4589) (4649:4649:4649)) + (PORT d[11] (4439:4439:4439) (4545:4545:4545)) + (PORT d[12] (4288:4288:4288) (4293:4293:4293)) + (PORT clk (1819:1819:1819) (1813:1813:1813)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1818:1818:1818)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1682:1682:1682) (1815:1815:1815)) + (PORT d[1] (1648:1648:1648) (1686:1686:1686)) + (PORT d[2] (2268:2268:2268) (2431:2431:2431)) + (PORT d[3] (1863:1863:1863) (1918:1918:1918)) + (PORT d[4] (2378:2378:2378) (2506:2506:2506)) + (PORT d[5] (2549:2549:2549) (2590:2590:2590)) + (PORT d[6] (1990:1990:1990) (2063:2063:2063)) + (PORT d[7] (2031:2031:2031) (2099:2099:2099)) + (PORT d[8] (2125:2125:2125) (2219:2219:2219)) + (PORT d[9] (2009:2009:2009) (2078:2078:2078)) + (PORT d[10] (1655:1655:1655) (1716:1716:1716)) + (PORT d[11] (4351:4351:4351) (4669:4669:4669)) + (PORT d[12] (2155:2155:2155) (2206:2206:2206)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1882:1882:1882)) + (PORT d[0] (2116:2116:2116) (2085:2085:2085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1562:1562:1562) (1663:1663:1663)) + (PORT clk (1857:1857:1857) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1624:1624:1624) (1739:1739:1739)) + (PORT d[1] (2987:2987:2987) (3136:3136:3136)) + (PORT d[2] (2558:2558:2558) (2693:2693:2693)) + (PORT d[3] (3334:3334:3334) (3467:3467:3467)) + (PORT d[4] (2606:2606:2606) (2786:2786:2786)) + (PORT d[5] (3822:3822:3822) (3934:3934:3934)) + (PORT d[6] (2246:2246:2246) (2338:2338:2338)) + (PORT d[7] (3413:3413:3413) (3468:3468:3468)) + (PORT d[8] (2931:2931:2931) (3033:3033:3033)) + (PORT d[9] (2477:2477:2477) (2573:2573:2573)) + (PORT d[10] (2626:2626:2626) (2737:2737:2737)) + (PORT d[11] (2491:2491:2491) (2679:2679:2679)) + (PORT d[12] (4641:4641:4641) (4882:4882:4882)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2847:2847:2847) (2894:2894:2894)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1885:1885:1885)) + (PORT d[0] (3233:3233:3233) (3186:3186:3186)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1810:1810:1810)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1943:1943:1943) (1936:1936:1936)) + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4480:4480:4480) (4505:4505:4505)) + (PORT d[1] (4433:4433:4433) (4489:4489:4489)) + (PORT d[2] (4515:4515:4515) (4513:4513:4513)) + (PORT d[3] (4207:4207:4207) (4267:4267:4267)) + (PORT d[4] (4326:4326:4326) (4470:4470:4470)) + (PORT d[5] (4354:4354:4354) (4405:4405:4405)) + (PORT d[6] (4409:4409:4409) (4469:4469:4469)) + (PORT d[7] (4149:4149:4149) (4196:4196:4196)) + (PORT d[8] (4390:4390:4390) (4446:4446:4446)) + (PORT d[9] (4387:4387:4387) (4446:4446:4446)) + (PORT d[10] (4288:4288:4288) (4373:4373:4373)) + (PORT d[11] (4468:4468:4468) (4585:4585:4585)) + (PORT d[12] (4406:4406:4406) (4382:4382:4382)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1812:1812:1812)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1665:1665:1665) (1779:1779:1779)) + (PORT d[1] (2703:2703:2703) (2833:2833:2833)) + (PORT d[2] (2113:2113:2113) (2246:2246:2246)) + (PORT d[3] (3328:3328:3328) (3453:3453:3453)) + (PORT d[4] (2296:2296:2296) (2448:2448:2448)) + (PORT d[5] (3758:3758:3758) (3880:3880:3880)) + (PORT d[6] (2543:2543:2543) (2630:2630:2630)) + (PORT d[7] (3441:3441:3441) (3488:3488:3488)) + (PORT d[8] (2926:2926:2926) (3023:3023:3023)) + (PORT d[9] (2768:2768:2768) (2881:2881:2881)) + (PORT d[10] (2335:2335:2335) (2395:2395:2395)) + (PORT d[11] (2478:2478:2478) (2654:2654:2654)) + (PORT d[12] (3520:3520:3520) (3735:3735:3735)) + (PORT clk (1861:1861:1861) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1887:1887:1887)) + (PORT d[0] (2653:2653:2653) (2588:2588:2588)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1824:1824:1824) (1850:1850:1850)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1009:1009:1009) (1013:1013:1013)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1010:1010:1010) (1014:1014:1014)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1010:1010:1010) (1014:1014:1014)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1010:1010:1010) (1014:1014:1014)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1215:1215:1215) (1288:1288:1288)) + (PORT datab (724:724:724) (782:782:782)) + (PORT datac (1333:1333:1333) (1353:1353:1353)) + (PORT datad (1400:1400:1400) (1484:1484:1484)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (765:765:765)) + (PORT datab (1092:1092:1092) (1091:1091:1091)) + (PORT datac (1528:1528:1528) (1658:1658:1658)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~116) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (256:256:256)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (973:973:973) (999:999:999)) + (PORT datad (615:615:615) (641:641:641)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~117) + (DELAY + (ABSOLUTE + (PORT dataa (1229:1229:1229) (1241:1241:1241)) + (PORT datab (2477:2477:2477) (2583:2583:2583)) + (PORT datac (1187:1187:1187) (1273:1273:1273)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (398:398:398)) + (PORT datab (431:431:431) (467:467:467)) + (PORT datac (1157:1157:1157) (1229:1229:1229)) + (PORT datad (1131:1131:1131) (1158:1158:1158)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (420:420:420) (454:454:454)) + (PORT datac (594:594:594) (602:602:602)) + (PORT datad (240:240:240) (310:310:310)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (675:675:675) (698:698:698)) + (PORT clrn (1577:1577:1577) (1558:1558:1558)) + (PORT ena (1917:1917:1917) (1918:1918:1918)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~0) + (DELAY + (ABSOLUTE + (PORT datac (1095:1095:1095) (1167:1167:1167)) + (PORT datad (1964:1964:1964) (2035:2035:2035)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2561:2561:2561) (2630:2630:2630)) + (PORT datab (2099:2099:2099) (2235:2235:2235)) + (PORT datac (2435:2435:2435) (2634:2634:2634)) + (PORT datad (1838:1838:1838) (1932:1932:1932)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1616:1616:1616) (1664:1664:1664)) + (PORT datab (568:568:568) (584:584:584)) + (PORT datac (848:848:848) (863:863:863)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) + (DELAY + (ABSOLUTE + (PORT dataa (677:677:677) (699:699:699)) + (PORT datab (856:856:856) (930:930:930)) + (PORT datac (1457:1457:1457) (1472:1472:1472)) + (PORT datad (1160:1160:1160) (1214:1214:1214)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2288:2288:2288) (2394:2394:2394)) + (PORT datab (2179:2179:2179) (2358:2358:2358)) + (PORT datac (1178:1178:1178) (1292:1292:1292)) + (PORT datad (819:819:819) (892:892:892)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instCB) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1565:1565:1565) (1545:1545:1545)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~0) + (DELAY + (ABSOLUTE + (PORT dataa (786:786:786) (855:855:855)) + (PORT datab (770:770:770) (837:837:837)) + (PORT datac (1830:1830:1830) (1968:1968:1968)) + (PORT datad (1686:1686:1686) (1757:1757:1757)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (1012:1012:1012)) + (PORT datab (1179:1179:1179) (1247:1247:1247)) + (PORT datac (1905:1905:1905) (1971:1971:1971)) + (PORT datad (1431:1431:1431) (1464:1464:1464)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im1) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (929:929:929) (946:946:946)) + (PORT clrn (1577:1577:1577) (1557:1557:1557)) + (PORT ena (968:968:968) (972:972:972)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (674:674:674)) + (PORT datab (968:968:968) (1029:1029:1029)) + (PORT datad (359:359:359) (423:423:423)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (959:959:959)) + (PORT datab (989:989:989) (1031:1031:1031)) + (PORT datac (617:617:617) (643:643:643)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (674:674:674)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (1172:1172:1172) (1212:1212:1212)) + (PORT datad (839:839:839) (895:895:895)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1508:1508:1508) (1611:1611:1611)) + (PORT datab (1253:1253:1253) (1278:1278:1278)) + (PORT datac (1153:1153:1153) (1183:1183:1183)) + (PORT datad (1488:1488:1488) (1524:1524:1524)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (677:677:677)) + (PORT datab (1453:1453:1453) (1487:1487:1487)) + (PORT datac (508:508:508) (517:517:517)) + (PORT datad (952:952:952) (989:989:989)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) + (DELAY + (ABSOLUTE + (PORT datac (901:901:901) (942:942:942)) + (PORT datad (617:617:617) (659:659:659)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (256:256:256)) + (PORT datab (382:382:382) (410:410:410)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (525:525:525) (533:533:533)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (1019:1019:1019)) + (PORT datab (931:931:931) (1012:1012:1012)) + (PORT datac (252:252:252) (337:337:337)) + (PORT datad (268:268:268) (347:347:347)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~1) + (DELAY + (ABSOLUTE + (PORT datac (738:738:738) (815:815:815)) + (PORT datad (1023:1023:1023) (1090:1090:1090)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (437:437:437)) + (PORT datab (337:337:337) (366:366:366)) + (PORT datac (734:734:734) (821:821:821)) + (PORT datad (581:581:581) (597:597:597)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (771:771:771) (850:850:850)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1506:1506:1506) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1546:1546:1546) (1539:1539:1539)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (301:301:301) (418:418:418)) + (PORT datab (680:680:680) (747:747:747)) + (PORT datac (912:912:912) (975:975:975)) + (PORT datad (946:946:946) (1019:1019:1019)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (838:838:838)) + (PORT datab (771:771:771) (853:853:853)) + (PORT datac (697:697:697) (771:771:771)) + (PORT datad (966:966:966) (1032:1032:1032)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~85) + (DELAY + (ABSOLUTE + (PORT datab (1063:1063:1063) (1128:1128:1128)) + (PORT datad (184:184:184) (213:213:213)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (684:684:684)) + (PORT datab (225:225:225) (273:273:273)) + (PORT datac (710:710:710) (772:772:772)) + (PORT datad (520:520:520) (531:531:531)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (376:376:376)) + (PORT datab (775:775:775) (855:855:855)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1506:1506:1506) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1546:1546:1546) (1539:1539:1539)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (328:328:328)) + (PORT datab (947:947:947) (978:978:978)) + (PORT datac (785:785:785) (819:819:819)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (497:497:497) (573:573:573)) + (PORT datab (1005:1005:1005) (1093:1093:1093)) + (PORT datac (669:669:669) (725:725:725)) + (PORT datad (618:618:618) (686:686:686)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (497:497:497) (573:573:573)) + (PORT datac (755:755:755) (829:829:829)) + (PORT datad (392:392:392) (458:458:458)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1043:1043:1043) (1127:1127:1127)) + (PORT datac (901:901:901) (915:915:915)) + (PORT datad (729:729:729) (803:803:803)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (246:246:246)) + (PORT datab (201:201:201) (240:240:240)) + (PORT datad (576:576:576) (586:586:586)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (620:620:620)) + (PORT datab (1063:1063:1063) (1128:1128:1128)) + (PORT datac (731:731:731) (807:807:807)) + (PORT datad (184:184:184) (213:213:213)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (259:259:259)) + (PORT datab (559:559:559) (578:578:578)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1520:1520:1520)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (233:233:233) (282:282:282)) + (PORT datab (228:228:228) (268:268:268)) + (PORT datac (931:931:931) (977:977:977)) + (PORT datad (617:617:617) (661:661:661)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (718:718:718) (817:817:817)) + (PORT datab (1016:1016:1016) (1083:1083:1083)) + (PORT datac (962:962:962) (1040:1040:1040)) + (PORT datad (577:577:577) (602:602:602)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (1292:1292:1292) (1396:1396:1396)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1509:1509:1509) (1524:1524:1524)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1550:1550:1550) (1542:1542:1542)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~68) + (DELAY + (ABSOLUTE + (PORT datab (644:644:644) (706:706:706)) + (PORT datac (1000:1000:1000) (1060:1060:1060)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (735:735:735) (825:825:825)) + (PORT datab (970:970:970) (1056:1056:1056)) + (PORT datac (753:753:753) (841:841:841)) + (PORT datad (904:904:904) (978:978:978)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~69) + (DELAY + (ABSOLUTE + (PORT dataa (506:506:506) (584:584:584)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (937:937:937) (1017:1017:1017)) + (PORT datad (192:192:192) (225:225:225)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (905:905:905)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datac (606:606:606) (617:617:617)) + (PORT datad (714:714:714) (785:785:785)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (425:425:425) (501:501:501)) + (PORT datac (745:745:745) (823:823:823)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1065:1065:1065) (1137:1137:1137)) + (PORT datab (593:593:593) (663:663:663)) + (PORT datac (1004:1004:1004) (1060:1060:1060)) + (PORT datad (609:609:609) (666:666:666)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~71) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (688:688:688)) + (PORT datab (750:750:750) (829:829:829)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (262:262:262) (341:341:341)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (245:245:245)) + (PORT datab (744:744:744) (816:816:816)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1542:1542:1542) (1535:1535:1535)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1478:1478:1478) (1551:1551:1551)) + (PORT datac (2279:2279:2279) (2486:2486:2486)) + (PORT datad (872:872:872) (942:942:942)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (718:718:718) (814:814:814)) + (PORT datac (962:962:962) (1038:1038:1038)) + (PORT datad (578:578:578) (600:600:600)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (1295:1295:1295) (1399:1399:1399)) + (PORT datab (1016:1016:1016) (1082:1082:1082)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1509:1509:1509) (1524:1524:1524)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1550:1550:1550) (1542:1542:1542)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (436:436:436)) + (PORT datab (739:739:739) (806:806:806)) + (PORT datac (888:888:888) (956:956:956)) + (PORT datad (198:198:198) (235:235:235)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (1294:1294:1294) (1399:1399:1399)) + (PORT datab (957:957:957) (996:996:996)) + (PORT datad (592:592:592) (615:615:615)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1509:1509:1509) (1524:1524:1524)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1550:1550:1550) (1542:1542:1542)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (276:276:276)) + (PORT datab (2799:2799:2799) (3004:3004:3004)) + (PORT datac (215:215:215) (290:290:290)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (221:221:221) (261:261:261)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (931:931:931)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (2354:2354:2354) (2577:2577:2577)) + (PORT datad (621:621:621) (631:631:631)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1207:1207:1207) (1245:1245:1245)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2687:2687:2687) (2899:2899:2899)) + (PORT d[1] (2871:2871:2871) (2966:2966:2966)) + (PORT d[2] (1020:1020:1020) (1070:1070:1070)) + (PORT d[3] (974:974:974) (1029:1029:1029)) + (PORT d[4] (2049:2049:2049) (2146:2146:2146)) + (PORT d[5] (972:972:972) (1026:1026:1026)) + (PORT d[6] (1699:1699:1699) (1745:1745:1745)) + (PORT d[7] (2654:2654:2654) (2813:2813:2813)) + (PORT d[8] (2491:2491:2491) (2668:2668:2668)) + (PORT d[9] (756:756:756) (799:799:799)) + (PORT d[10] (747:747:747) (789:789:789)) + (PORT d[11] (2820:2820:2820) (3002:3002:3002)) + (PORT d[12] (430:430:430) (463:463:463)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1529:1529:1529) (1497:1497:1497)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1871:1871:1871)) + (PORT d[0] (1469:1469:1469) (1447:1447:1447)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1830:1830:1830)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (988:988:988) (993:993:993)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (947:947:947) (971:971:971)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3042:3042:3042) (3290:3290:3290)) + (PORT d[1] (1608:1608:1608) (1696:1696:1696)) + (PORT d[2] (994:994:994) (1040:1040:1040)) + (PORT d[3] (946:946:946) (995:995:995)) + (PORT d[4] (1164:1164:1164) (1193:1193:1193)) + (PORT d[5] (957:957:957) (1004:1004:1004)) + (PORT d[6] (1556:1556:1556) (1674:1674:1674)) + (PORT d[7] (976:976:976) (1018:1018:1018)) + (PORT d[8] (1289:1289:1289) (1377:1377:1377)) + (PORT d[9] (775:775:775) (838:838:838)) + (PORT d[10] (729:729:729) (784:784:784)) + (PORT d[11] (2477:2477:2477) (2650:2650:2650)) + (PORT d[12] (1069:1069:1069) (1134:1134:1134)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (940:940:940) (896:896:896)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (2042:2042:2042) (2033:2033:2033)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1001:1001:1001) (1045:1045:1045)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3024:3024:3024) (3251:3251:3251)) + (PORT d[1] (1903:1903:1903) (2000:2000:2000)) + (PORT d[2] (1280:1280:1280) (1322:1322:1322)) + (PORT d[3] (1267:1267:1267) (1318:1318:1318)) + (PORT d[4] (1471:1471:1471) (1527:1527:1527)) + (PORT d[5] (661:661:661) (688:688:688)) + (PORT d[6] (1836:1836:1836) (1967:1967:1967)) + (PORT d[7] (2929:2929:2929) (3085:3085:3085)) + (PORT d[8] (1275:1275:1275) (1340:1340:1340)) + (PORT d[9] (1006:1006:1006) (1059:1059:1059)) + (PORT d[10] (723:723:723) (773:773:773)) + (PORT d[11] (2518:2518:2518) (2677:2677:2677)) + (PORT d[12] (772:772:772) (836:836:836)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (942:942:942) (897:897:897)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT d[0] (1808:1808:1808) (1808:1808:1808)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (1055:1055:1055) (1145:1145:1145)) + (PORT datab (960:960:960) (1036:1036:1036)) + (PORT datac (887:887:887) (907:907:907)) + (PORT datad (932:932:932) (969:969:969)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1406:1406:1406) (1432:1432:1432)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2471:2471:2471) (2605:2605:2605)) + (PORT d[1] (2523:2523:2523) (2576:2576:2576)) + (PORT d[2] (2567:2567:2567) (2747:2747:2747)) + (PORT d[3] (4593:4593:4593) (4820:4820:4820)) + (PORT d[4] (2930:2930:2930) (3056:3056:3056)) + (PORT d[5] (3148:3148:3148) (3203:3203:3203)) + (PORT d[6] (1481:1481:1481) (1477:1477:1477)) + (PORT d[7] (1396:1396:1396) (1430:1430:1430)) + (PORT d[8] (2490:2490:2490) (2615:2615:2615)) + (PORT d[9] (1697:1697:1697) (1729:1729:1729)) + (PORT d[10] (2540:2540:2540) (2643:2643:2643)) + (PORT d[11] (3702:3702:3702) (3993:3993:3993)) + (PORT d[12] (2490:2490:2490) (2565:2565:2565)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1996:1996:1996) (1955:1955:1955)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (1950:1950:1950) (1919:1919:1919)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (1203:1203:1203) (1219:1219:1219)) + (PORT datab (1550:1550:1550) (1670:1670:1670)) + (PORT datac (349:349:349) (375:375:375)) + (PORT datad (1314:1314:1314) (1366:1366:1366)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1584:1584:1584) (1654:1654:1654)) + (PORT clk (1860:1860:1860) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2492:2492:2492) (2623:2623:2623)) + (PORT d[1] (2117:2117:2117) (2250:2250:2250)) + (PORT d[2] (2413:2413:2413) (2548:2548:2548)) + (PORT d[3] (2100:2100:2100) (2226:2226:2226)) + (PORT d[4] (2068:2068:2068) (2175:2175:2175)) + (PORT d[5] (2319:2319:2319) (2438:2438:2438)) + (PORT d[6] (2333:2333:2333) (2448:2448:2448)) + (PORT d[7] (3448:3448:3448) (3532:3532:3532)) + (PORT d[8] (2854:2854:2854) (2949:2949:2949)) + (PORT d[9] (2032:2032:2032) (2198:2198:2198)) + (PORT d[10] (3609:3609:3609) (3784:3784:3784)) + (PORT d[11] (2147:2147:2147) (2282:2282:2282)) + (PORT d[12] (1982:1982:1982) (2139:2139:2139)) + (PORT clk (1857:1857:1857) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1972:1972:1972) (1939:1939:1939)) + (PORT clk (1857:1857:1857) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1886:1886:1886)) + (PORT d[0] (3223:3223:3223) (3296:3296:3296)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1811:1811:1811)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2151:2151:2151) (2201:2201:2201)) + (PORT clk (1825:1825:1825) (1817:1817:1817)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4343:4343:4343) (4403:4403:4403)) + (PORT d[1] (4498:4498:4498) (4585:4585:4585)) + (PORT d[2] (4548:4548:4548) (4611:4611:4611)) + (PORT d[3] (4307:4307:4307) (4402:4402:4402)) + (PORT d[4] (4392:4392:4392) (4483:4483:4483)) + (PORT d[5] (4431:4431:4431) (4542:4542:4542)) + (PORT d[6] (4555:4555:4555) (4660:4660:4660)) + (PORT d[7] (4287:4287:4287) (4335:4335:4335)) + (PORT d[8] (4389:4389:4389) (4493:4493:4493)) + (PORT d[9] (4480:4480:4480) (4525:4525:4525)) + (PORT d[10] (4429:4429:4429) (4529:4529:4529)) + (PORT d[11] (4427:4427:4427) (4554:4554:4554)) + (PORT d[12] (4332:4332:4332) (4318:4318:4318)) + (PORT clk (1821:1821:1821) (1813:1813:1813)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1817:1817:1817)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1818:1818:1818)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1818:1818:1818)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1978:1978:1978) (2105:2105:2105)) + (PORT d[1] (2195:2195:2195) (2216:2216:2216)) + (PORT d[2] (2233:2233:2233) (2405:2405:2405)) + (PORT d[3] (1730:1730:1730) (1765:1765:1765)) + (PORT d[4] (2301:2301:2301) (2429:2429:2429)) + (PORT d[5] (2806:2806:2806) (2865:2865:2865)) + (PORT d[6] (1746:1746:1746) (1828:1828:1828)) + (PORT d[7] (1972:1972:1972) (2011:2011:2011)) + (PORT d[8] (2183:2183:2183) (2302:2302:2302)) + (PORT d[9] (2006:2006:2006) (2072:2072:2072)) + (PORT d[10] (2505:2505:2505) (2578:2578:2578)) + (PORT d[11] (4321:4321:4321) (4631:4631:4631)) + (PORT d[12] (2164:2164:2164) (2232:2232:2232)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1880:1880:1880)) + (PORT d[0] (2147:2147:2147) (2137:2137:2137)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (978:978:978)) + (PORT datab (772:772:772) (880:880:880)) + (PORT datac (1200:1200:1200) (1239:1239:1239)) + (PORT datad (1667:1667:1667) (1720:1720:1720)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1483:1483:1483) (1518:1518:1518)) + (PORT clk (1869:1869:1869) (1895:1895:1895)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2205:2205:2205) (2306:2306:2306)) + (PORT d[1] (2632:2632:2632) (2785:2785:2785)) + (PORT d[2] (2362:2362:2362) (2492:2492:2492)) + (PORT d[3] (3051:3051:3051) (3158:3158:3158)) + (PORT d[4] (2271:2271:2271) (2411:2411:2411)) + (PORT d[5] (3452:3452:3452) (3554:3554:3554)) + (PORT d[6] (2543:2543:2543) (2661:2661:2661)) + (PORT d[7] (2952:2952:2952) (3038:3038:3038)) + (PORT d[8] (2643:2643:2643) (2727:2727:2727)) + (PORT d[9] (2971:2971:2971) (3112:3112:3112)) + (PORT d[10] (2322:2322:2322) (2378:2378:2378)) + (PORT d[11] (2215:2215:2215) (2364:2364:2364)) + (PORT d[12] (3539:3539:3539) (3735:3735:3735)) + (PORT clk (1866:1866:1866) (1891:1891:1891)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2575:2575:2575) (2593:2593:2593)) + (PORT clk (1866:1866:1866) (1891:1891:1891)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (PORT d[0] (3571:3571:3571) (3500:3500:3500)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1870:1870:1870) (1896:1896:1896)) @@ -34010,7 +42620,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1870:1870:1870) (1896:1896:1896)) @@ -34020,7 +42630,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1870:1870:1870) (1896:1896:1896)) @@ -34030,7 +42640,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1870:1870:1870) (1896:1896:1896)) @@ -34040,7 +42650,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1824:1824:1824) (1820:1820:1820)) @@ -34054,10 +42664,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2487:2487:2487) (2567:2567:2567)) + (PORT d[0] (2190:2190:2190) (2175:2175:2175)) (PORT clk (1834:1834:1834) (1826:1826:1826)) ) ) @@ -34067,22 +42677,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4515:4515:4515) (4502:4502:4502)) - (PORT d[1] (4098:4098:4098) (4096:4096:4096)) - (PORT d[2] (4387:4387:4387) (4416:4416:4416)) - (PORT d[3] (4466:4466:4466) (4494:4494:4494)) - (PORT d[4] (4550:4550:4550) (4547:4547:4547)) - (PORT d[5] (4395:4395:4395) (4433:4433:4433)) - (PORT d[6] (4601:4601:4601) (4650:4650:4650)) - (PORT d[7] (4160:4160:4160) (4143:4143:4143)) - (PORT d[8] (4661:4661:4661) (4689:4689:4689)) - (PORT d[9] (4502:4502:4502) (4695:4695:4695)) - (PORT d[10] (4622:4622:4622) (4632:4632:4632)) - (PORT d[11] (4398:4398:4398) (4428:4428:4428)) - (PORT d[12] (4464:4464:4464) (4487:4487:4487)) + (PORT d[0] (4505:4505:4505) (4525:4525:4525)) + (PORT d[1] (4469:4469:4469) (4501:4501:4501)) + (PORT d[2] (4469:4469:4469) (4476:4476:4476)) + (PORT d[3] (4421:4421:4421) (4437:4437:4437)) + (PORT d[4] (4275:4275:4275) (4372:4372:4372)) + (PORT d[5] (4447:4447:4447) (4521:4521:4521)) + (PORT d[6] (4240:4240:4240) (4335:4335:4335)) + (PORT d[7] (4388:4388:4388) (4448:4448:4448)) + (PORT d[8] (4382:4382:4382) (4489:4489:4489)) + (PORT d[9] (4346:4346:4346) (4404:4404:4404)) + (PORT d[10] (4279:4279:4279) (4347:4347:4347)) + (PORT d[11] (4488:4488:4488) (4529:4529:4529)) + (PORT d[12] (4294:4294:4294) (4294:4294:4294)) (PORT clk (1830:1830:1830) (1822:1822:1822)) ) ) @@ -34092,7 +42702,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1834:1834:1834) (1826:1826:1826)) @@ -34101,7 +42711,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) (DELAY (ABSOLUTE (PORT clk (1835:1835:1835) (1827:1827:1827)) @@ -34111,7 +42721,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1835:1835:1835) (1827:1827:1827)) @@ -34121,7 +42731,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1835:1835:1835) (1827:1827:1827)) @@ -34131,7 +42741,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1835:1835:1835) (1827:1827:1827)) @@ -34141,7 +42751,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) (DELAY (ABSOLUTE (PORT clk (1826:1826:1826) (1822:1822:1822)) @@ -34154,103 +42764,204 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~0) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT dataa (1428:1428:1428) (1500:1500:1500)) - (PORT datab (969:969:969) (1047:1047:1047)) - (PORT datac (1170:1170:1170) (1197:1197:1197)) - (PORT datad (1685:1685:1685) (1714:1714:1714)) + (PORT d[0] (2240:2240:2240) (2401:2401:2401)) + (PORT d[1] (1094:1094:1094) (1093:1093:1093)) + (PORT d[2] (2654:2654:2654) (2732:2732:2732)) + (PORT d[3] (4596:4596:4596) (4810:4810:4810)) + (PORT d[4] (1006:1006:1006) (1054:1054:1054)) + (PORT d[5] (2205:2205:2205) (2223:2223:2223)) + (PORT d[6] (2849:2849:2849) (2950:2950:2950)) + (PORT d[7] (1412:1412:1412) (1409:1409:1409)) + (PORT d[8] (2768:2768:2768) (2898:2898:2898)) + (PORT d[9] (1486:1486:1486) (1518:1518:1518)) + (PORT d[10] (2026:2026:2026) (2083:2083:2083)) + (PORT d[11] (3734:3734:3734) (3998:3998:3998)) + (PORT d[12] (1704:1704:1704) (1711:1711:1711)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1879:1879:1879)) + (PORT d[0] (1336:1336:1336) (1345:1345:1345)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1816:1816:1816) (1842:1842:1842)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1001:1001:1001) (1005:1005:1005)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (1157:1157:1157) (1202:1202:1202)) + (PORT datab (947:947:947) (970:970:970)) + (PORT datac (998:998:998) (1057:1057:1057)) + (PORT datad (183:183:183) (213:213:213)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (772:772:772) (884:884:884)) + (PORT datac (1893:1893:1893) (1938:1938:1938)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~120) + (DELAY + (ABSOLUTE + (PORT dataa (1727:1727:1727) (1787:1787:1787)) + (PORT datab (3006:3006:3006) (3258:3258:3258)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (966:966:966)) + (PORT datab (902:902:902) (924:924:924)) + (PORT datac (1649:1649:1649) (1666:1666:1666)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (1188:1188:1188) (1288:1288:1288)) + (PORT datab (2963:2963:2963) (3072:3072:3072)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (1441:1441:1441) (1491:1491:1491)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (1194:1194:1194) (1194:1194:1194)) + (PORT datab (424:424:424) (459:459:459)) + (PORT datac (371:371:371) (400:400:400)) + (PORT datad (1127:1127:1127) (1155:1155:1155)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1516:1516:1516) (1602:1602:1602)) - (PORT datab (970:970:970) (1048:1048:1048)) - (PORT datac (1706:1706:1706) (1767:1767:1767)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (246:246:246)) - (PORT datab (1206:1206:1206) (1299:1299:1299)) - (PORT datac (1658:1658:1658) (1693:1693:1693)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (1382:1382:1382) (1395:1395:1395)) - (PORT datab (1382:1382:1382) (1409:1409:1409)) - (PORT datac (842:842:842) (919:919:919)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~99) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (832:832:832)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) - (DELAY - (ABSOLUTE - (PORT dataa (972:972:972) (1043:1043:1043)) - (PORT datab (1039:1039:1039) (1071:1071:1071)) - (PORT datac (240:240:240) (293:293:293)) - (PORT datad (948:948:948) (984:984:984)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[5\]) + (INSTANCE z80_\|data_pins_\|dout\[0\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT clk (1527:1527:1527) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) (PORT ena (841:841:841) (846:846:846)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -34263,43 +42974,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~14) + (INSTANCE z80_\|bus_control_\|db\[0\]\~16) (DELAY (ABSOLUTE - (PORT datab (707:707:707) (729:729:729)) - (PORT datac (235:235:235) (309:309:309)) - (PORT datad (359:359:359) (384:384:384)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (253:253:253) (299:299:299)) + (PORT datac (220:220:220) (264:264:264)) + (PORT datad (2132:2132:2132) (2201:2201:2201)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~15) + (INSTANCE z80_\|bus_control_\|db\[0\]\~17) (DELAY (ABSOLUTE - (PORT dataa (980:980:980) (1004:1004:1004)) - (PORT datab (917:917:917) (967:967:967)) - (PORT datac (825:825:825) (825:825:825)) - (PORT datad (891:891:891) (919:919:919)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (1434:1434:1434) (1471:1471:1471)) + (PORT datac (1092:1092:1092) (1123:1123:1123)) + (PORT datad (217:217:217) (254:254:254)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[5\]) + (INSTANCE z80_\|ir_\|opcode\[0\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT asdata (598:598:598) (653:653:653)) - (PORT clrn (1571:1571:1571) (1550:1550:1550)) - (PORT ena (1479:1479:1479) (1488:1488:1488)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (714:714:714) (741:741:741)) + (PORT clrn (1577:1577:1577) (1558:1558:1558)) + (PORT ena (1917:1917:1917) (1918:1918:1918)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -34311,29 +43022,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) + (INSTANCE z80_\|pla_decode_\|Equal3\~2) (DELAY (ABSOLUTE - (PORT dataa (1209:1209:1209) (1333:1333:1333)) - (PORT datab (857:857:857) (877:877:877)) - (PORT datac (862:862:862) (884:884:884)) - (PORT datad (1897:1897:1897) (1952:1952:1952)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1683:1683:1683) (1793:1793:1793)) + (PORT datab (1366:1366:1366) (1396:1396:1396)) + (PORT datac (208:208:208) (251:251:251)) + (PORT datad (1331:1331:1331) (1338:1338:1338)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2302:2302:2302) (2437:2437:2437)) + (PORT datab (2181:2181:2181) (2361:2361:2361)) + (PORT datac (2247:2247:2247) (2350:2350:2350)) + (PORT datad (365:365:365) (398:398:398)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_inst4) + (INSTANCE z80_\|decode_state_\|DFFE_instIY1) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) + (PORT clk (1516:1516:1516) (1529:1529:1529)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1586:1586:1586) (1563:1563:1563)) - (PORT ena (820:820:820) (825:825:825)) + (PORT clrn (1565:1565:1565) (1545:1545:1545)) + (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -34348,166 +43075,24 @@ (INSTANCE z80_\|decode_state_\|use_ixiy) (DELAY (ABSOLUTE - (PORT dataa (974:974:974) (1072:1072:1072)) - (PORT datac (930:930:930) (1012:1012:1012)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1192:1192:1192) (1230:1230:1230)) - (PORT datab (998:998:998) (1107:1107:1107)) - (PORT datac (657:657:657) (721:721:721)) - (PORT datad (1243:1243:1243) (1329:1329:1329)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datac (996:996:996) (1081:1081:1081)) + (PORT datad (1502:1502:1502) (1553:1553:1553)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~34) + (INSTANCE z80_\|execute_\|ixy_d\~12) (DELAY (ABSOLUTE - (PORT dataa (888:888:888) (915:915:915)) - (PORT datab (667:667:667) (679:679:679)) - (PORT datac (904:904:904) (934:934:934)) - (PORT datad (360:360:360) (382:382:382)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1168:1168:1168) (1211:1211:1211)) - (PORT datab (1607:1607:1607) (1625:1625:1625)) - (PORT datac (614:614:614) (646:646:646)) - (PORT datad (1081:1081:1081) (1126:1126:1126)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1255:1255:1255) (1363:1363:1363)) - (PORT datab (469:469:469) (523:523:523)) - (PORT datac (1707:1707:1707) (1763:1763:1763)) - (PORT datad (264:264:264) (317:317:317)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (441:441:441)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (1072:1072:1072) (1108:1108:1108)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1172:1172:1172) (1212:1212:1212)) - (PORT datab (568:568:568) (599:599:599)) - (PORT datac (1103:1103:1103) (1115:1115:1115)) - (PORT datad (317:317:317) (336:336:336)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (898:898:898)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (590:590:590) (597:597:597)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (903:903:903) (948:948:948)) + (PORT datab (1697:1697:1697) (1728:1728:1728)) + (PORT datac (1067:1067:1067) (1109:1109:1109)) + (PORT datad (812:812:812) (861:861:861)) (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (275:275:275)) - (PORT datab (645:645:645) (670:670:670)) - (PORT datac (194:194:194) (238:238:238)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (914:914:914)) - (PORT datab (1115:1115:1115) (1147:1147:1147)) - (PORT datac (1402:1402:1402) (1464:1464:1464)) - (PORT datad (899:899:899) (942:942:942)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (895:895:895)) - (PORT datab (939:939:939) (994:994:994)) - (PORT datac (959:959:959) (1031:1031:1031)) - (PORT datad (1113:1113:1113) (1143:1143:1143)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -34515,15 +43100,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~9) + (INSTANCE z80_\|execute_\|ixy_d\~13) (DELAY (ABSOLUTE - (PORT dataa (889:889:889) (916:916:916)) - (PORT datab (876:876:876) (896:896:896)) - (PORT datac (1106:1106:1106) (1134:1134:1134)) - (PORT datad (326:326:326) (350:350:350)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (PORT dataa (624:624:624) (662:662:662)) + (PORT datab (1244:1244:1244) (1274:1274:1274)) + (PORT datad (871:871:871) (916:916:916)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1085:1085:1085) (1153:1153:1153)) + (PORT datab (609:609:609) (654:654:654)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (597:597:597) (613:613:613)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (719:719:719)) + (PORT datab (700:700:700) (775:775:775)) + (PORT datac (1424:1424:1424) (1508:1508:1508)) + (PORT datad (601:601:601) (661:661:661)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1203:1203:1203) (1234:1234:1234)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (610:610:610) (637:637:637)) + (PORT datad (772:772:772) (823:823:823)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -34531,14 +43162,62 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~11) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) (DELAY (ABSOLUTE - (PORT dataa (1572:1572:1572) (1664:1664:1664)) - (PORT datab (205:205:205) (245:245:245)) - (PORT datac (1885:1885:1885) (1936:1936:1936)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) + (PORT dataa (1245:1245:1245) (1333:1333:1333)) + (PORT datab (390:390:390) (423:423:423)) + (PORT datac (956:956:956) (1024:1024:1024)) + (PORT datad (1355:1355:1355) (1444:1444:1444)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1284:1284:1284)) + (PORT datab (1539:1539:1539) (1640:1640:1640)) + (PORT datac (578:578:578) (588:588:588)) + (PORT datad (863:863:863) (880:880:880)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1381:1381:1381) (1463:1463:1463)) + (PORT datab (2126:2126:2126) (2263:2263:2263)) + (PORT datac (1615:1615:1615) (1658:1658:1658)) + (PORT datad (695:695:695) (742:742:742)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (724:724:724) (791:791:791)) + (PORT datab (649:649:649) (670:670:670)) + (PORT datac (1593:1593:1593) (1630:1630:1630)) + (PORT datad (1465:1465:1465) (1570:1570:1570)) + (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -34547,62 +43226,76 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~12) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) (DELAY (ABSOLUTE - (PORT dataa (1126:1126:1126) (1249:1249:1249)) - (PORT datab (997:997:997) (1061:1061:1061)) - (PORT datac (1628:1628:1628) (1678:1678:1678)) - (PORT datad (1161:1161:1161) (1198:1198:1198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1424:1424:1424) (1425:1425:1425)) - (PORT datab (1116:1116:1116) (1146:1146:1146)) - (PORT datac (1040:1040:1040) (1082:1082:1082)) - (PORT datad (337:337:337) (357:357:357)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (594:594:594) (614:614:614)) + (PORT dataa (1163:1163:1163) (1216:1216:1216)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (181:181:181) (210:210:210)) (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~20) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) (DELAY (ABSOLUTE - (PORT dataa (631:631:631) (644:644:644)) - (PORT datab (1041:1041:1041) (1082:1082:1082)) - (PORT datac (571:571:571) (588:588:588)) - (PORT datad (598:598:598) (647:647:647)) - (IOPATH dataa combout (325:325:325) (320:320:320)) + (PORT dataa (217:217:217) (266:266:266)) + (PORT datab (627:627:627) (678:678:678)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (349:349:349) (364:364:364)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~9) + (DELAY + (ABSOLUTE + (PORT datab (874:874:874) (925:925:925)) + (PORT datac (570:570:570) (586:586:586)) + (PORT datad (809:809:809) (832:832:832)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (621:621:621)) + (PORT datab (601:601:601) (620:620:620)) + (PORT datac (899:899:899) (936:936:936)) + (PORT datad (809:809:809) (837:837:837)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (297:297:297)) + (PORT datab (874:874:874) (928:928:928)) + (PORT datac (650:650:650) (693:693:693)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -34611,15 +43304,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~48) + (INSTANCE z80_\|alu_control_\|db\[1\]\~25) (DELAY (ABSOLUTE - (PORT dataa (886:886:886) (933:933:933)) - (PORT datab (1205:1205:1205) (1227:1227:1227)) - (PORT datac (1512:1512:1512) (1585:1585:1585)) - (PORT datad (674:674:674) (712:712:712)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (1079:1079:1079) (1133:1133:1133)) + (PORT datab (1173:1173:1173) (1212:1212:1212)) + (PORT datac (1315:1315:1315) (1328:1328:1328)) + (PORT datad (1358:1358:1358) (1425:1425:1425)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -34627,15 +43320,316 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~22) + (INSTANCE z80_\|alu_control_\|db\[1\]\~26) (DELAY (ABSOLUTE - (PORT dataa (1353:1353:1353) (1383:1383:1383)) - (PORT datab (852:852:852) (880:880:880)) - (PORT datac (1075:1075:1075) (1109:1109:1109)) - (PORT datad (195:195:195) (220:220:220)) + (PORT dataa (645:645:645) (661:661:661)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (851:851:851) (873:873:873)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (649:649:649)) + (PORT datac (630:630:630) (662:662:662)) + (PORT datad (838:838:838) (858:858:858)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (883:883:883) (909:909:909)) + (PORT datad (177:177:177) (203:203:203)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (910:910:910)) + (PORT datab (1157:1157:1157) (1201:1201:1201)) + (PORT datad (384:384:384) (414:414:414)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (498:498:498) (573:573:573)) + (PORT datac (751:751:751) (825:825:825)) + (PORT datad (387:387:387) (454:454:454)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (764:764:764)) + (PORT datac (977:977:977) (1063:1063:1063)) + (PORT datad (614:614:614) (686:686:686)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (247:247:247)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datad (578:578:578) (587:587:587)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1508:1508:1508) (1522:1522:1522)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (774:774:774) (851:851:851)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1506:1506:1506) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1546:1546:1546) (1539:1539:1539)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~0) + (DELAY + (ABSOLUTE + (PORT datab (1813:1813:1813) (1930:1930:1930)) + (PORT datac (2265:2265:2265) (2466:2466:2466)) + (PORT datad (915:915:915) (970:970:970)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (305:305:305) (422:422:422)) + (PORT datab (682:682:682) (750:750:750)) + (PORT datac (916:916:916) (978:978:978)) + (PORT datad (948:948:948) (1021:1021:1021)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (792:792:792)) + (PORT datab (793:793:793) (875:875:875)) + (PORT datac (1034:1034:1034) (1097:1097:1097)) + (PORT datad (738:738:738) (822:822:822)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~0) + (DELAY + (ABSOLUTE + (PORT dataa (716:716:716) (796:796:796)) + (PORT datab (792:792:792) (873:873:873)) + (PORT datac (1031:1031:1031) (1096:1096:1096)) + (PORT datad (735:735:735) (819:819:819)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (278:278:278)) + (PORT datab (1063:1063:1063) (1131:1131:1131)) + (PORT datac (1262:1262:1262) (1333:1333:1333)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) + (DELAY + (ABSOLUTE + (PORT dataa (738:738:738) (816:816:816)) + (PORT datab (1297:1297:1297) (1371:1371:1371)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (174:174:174) (201:201:201)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (741:741:741) (812:812:812)) + (PORT datab (607:607:607) (611:611:611)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1547:1547:1547) (1540:1540:1540)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (748:748:748) (837:837:837)) + (PORT datab (726:726:726) (804:804:804)) + (PORT datac (739:739:739) (817:817:817)) + (PORT datad (1023:1023:1023) (1086:1086:1086)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (995:995:995) (1074:1074:1074)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (522:522:522) (541:541:541)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (1062:1062:1062) (1126:1126:1126)) + (PORT datac (461:461:461) (535:535:535)) + (PORT datad (928:928:928) (988:988:988)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -34643,30 +43637,136 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~21) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~35) (DELAY (ABSOLUTE - (PORT dataa (870:870:870) (942:942:942)) - (PORT datab (941:941:941) (1018:1018:1018)) - (PORT datac (1551:1551:1551) (1591:1591:1591)) - (PORT datad (1215:1215:1215) (1217:1217:1217)) - (IOPATH dataa combout (301:301:301) (299:299:299)) + (PORT dataa (202:202:202) (246:246:246)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1520:1520:1520)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (988:988:988)) + (PORT datab (945:945:945) (1001:1001:1001)) + (PORT datac (641:641:641) (696:696:696)) + (PORT datad (1431:1431:1431) (1449:1449:1449)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (281:281:281)) + (PORT datab (921:921:921) (969:969:969)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~23) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~16) (DELAY (ABSOLUTE - (PORT dataa (867:867:867) (909:909:909)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (806:806:806) (819:819:819)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (350:350:350) (366:366:366)) + (PORT dataa (511:511:511) (591:591:591)) + (PORT datab (930:930:930) (1017:1017:1017)) + (PORT datac (753:753:753) (840:840:840)) + (PORT datad (703:703:703) (775:775:775)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (258:258:258)) + (PORT datab (652:652:652) (674:674:674)) + (PORT datac (937:937:937) (1024:1024:1024)) + (PORT datad (888:888:888) (925:925:925)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (500:500:500) (572:572:572)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1504:1504:1504) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (594:594:594)) + (PORT datab (970:970:970) (1057:1057:1057)) + (PORT datac (753:753:753) (842:842:842)) + (PORT datad (702:702:702) (779:779:779)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -34675,79 +43775,168 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~26) + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~13) (DELAY (ABSOLUTE - (PORT dataa (2068:2068:2068) (2159:2159:2159)) - (PORT datab (1202:1202:1202) (1215:1215:1215)) - (PORT datac (1137:1137:1137) (1179:1179:1179)) - (PORT datad (1150:1150:1150) (1187:1187:1187)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (2504:2504:2504) (2616:2616:2616)) - (PORT datab (576:576:576) (586:586:586)) - (PORT datac (193:193:193) (227:227:227)) - (PORT datad (981:981:981) (1012:1012:1012)) - (IOPATH dataa combout (304:304:304) (299:299:299)) + (PORT dataa (733:733:733) (820:820:820)) + (PORT datab (1305:1305:1305) (1362:1362:1362)) + (PORT datac (732:732:732) (817:817:817)) + (PORT datad (312:312:312) (329:329:329)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~27) + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~10) (DELAY (ABSOLUTE - (PORT dataa (1663:1663:1663) (1697:1697:1697)) - (PORT datab (833:833:833) (893:893:893)) - (PORT datac (1036:1036:1036) (1091:1091:1091)) - (PORT datad (770:770:770) (816:816:816)) - (IOPATH dataa combout (327:327:327) (347:347:347)) + (PORT datab (767:767:767) (847:847:847)) + (PORT datac (462:462:462) (540:540:540)) + (PORT datad (925:925:925) (984:984:984)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~33) + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) (DELAY (ABSOLUTE - (PORT dataa (1031:1031:1031) (1043:1043:1043)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (819:819:819) (869:869:869)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (642:642:642) (674:674:674)) + (PORT datab (336:336:336) (366:366:366)) + (PORT datad (175:175:175) (202:202:202)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1520:1520:1520)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (724:724:724)) + (PORT datab (669:669:669) (741:741:741)) + (PORT datac (672:672:672) (714:714:714)) + (PORT datad (1494:1494:1494) (1585:1585:1585)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~35) + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~25) (DELAY (ABSOLUTE - (PORT dataa (865:865:865) (888:888:888)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (821:821:821) (872:872:872)) - (PORT datad (195:195:195) (219:219:219)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT datab (1299:1299:1299) (1375:1375:1375)) + (PORT datac (685:685:685) (784:784:784)) + (PORT datad (717:717:717) (806:806:806)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1291:1291:1291) (1397:1397:1397)) + (PORT datab (659:659:659) (682:682:682)) + (PORT datad (593:593:593) (616:616:616)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1509:1509:1509) (1524:1524:1524)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1550:1550:1550) (1542:1542:1542)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1293:1293:1293) (1401:1401:1401)) + (PORT datab (1016:1016:1016) (1083:1083:1083)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1509:1509:1509) (1524:1524:1524)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1550:1550:1550) (1542:1542:1542)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (277:277:277)) + (PORT datab (2798:2798:2798) (3000:3000:3000)) + (PORT datac (216:216:216) (292:292:292)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -34755,178 +43944,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re) + (INSTANCE D\[1\]\~34) (DELAY (ABSOLUTE - (PORT datab (974:974:974) (1035:1035:1035)) - (PORT datac (964:964:964) (1026:1026:1026)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (2352:2352:2352) (2576:2576:2576)) + (PORT datad (570:570:570) (582:582:582)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1008:1008:1008) (1080:1080:1080)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1191:1191:1191) (1224:1224:1224)) - (PORT d[1] (2415:2415:2415) (2649:2649:2649)) - (PORT d[2] (1758:1758:1758) (1803:1803:1803)) - (PORT d[3] (1013:1013:1013) (1063:1063:1063)) - (PORT d[4] (2608:2608:2608) (2826:2826:2826)) - (PORT d[5] (3496:3496:3496) (3699:3699:3699)) - (PORT d[6] (1026:1026:1026) (1099:1099:1099)) - (PORT d[7] (3197:3197:3197) (3375:3375:3375)) - (PORT d[8] (1246:1246:1246) (1270:1270:1270)) - (PORT d[9] (1026:1026:1026) (1088:1088:1088)) - (PORT d[10] (1315:1315:1315) (1388:1388:1388)) - (PORT d[11] (2503:2503:2503) (2659:2659:2659)) - (PORT d[12] (1307:1307:1307) (1387:1387:1387)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (944:944:944) (900:900:900)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (1721:1721:1721) (1677:1677:1677)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (708:708:708) (754:754:754)) - (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (1278:1278:1278) (1317:1317:1317)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) ) ) (TIMINGCHECK @@ -34938,20 +43976,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (966:966:966) (1010:1010:1010)) - (PORT d[1] (2966:2966:2966) (3237:3237:3237)) - (PORT d[2] (1238:1238:1238) (1256:1256:1256)) - (PORT d[3] (1302:1302:1302) (1383:1383:1383)) - (PORT d[4] (2581:2581:2581) (2796:2796:2796)) - (PORT d[5] (2980:2980:2980) (3208:3208:3208)) - (PORT d[6] (692:692:692) (727:727:727)) - (PORT d[7] (705:705:705) (744:744:744)) - (PORT d[8] (1011:1011:1011) (1032:1032:1032)) - (PORT d[9] (717:717:717) (757:757:757)) - (PORT d[10] (1036:1036:1036) (1102:1102:1102)) - (PORT d[11] (2544:2544:2544) (2757:2757:2757)) - (PORT d[12] (1267:1267:1267) (1319:1319:1319)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (2420:2420:2420) (2614:2614:2614)) + (PORT d[1] (2542:2542:2542) (2641:2641:2641)) + (PORT d[2] (1265:1265:1265) (1333:1333:1333)) + (PORT d[3] (1256:1256:1256) (1301:1301:1301)) + (PORT d[4] (2037:2037:2037) (2116:2116:2116)) + (PORT d[5] (1268:1268:1268) (1326:1326:1326)) + (PORT d[6] (1448:1448:1448) (1473:1473:1473)) + (PORT d[7] (2668:2668:2668) (2814:2814:2814)) + (PORT d[8] (2486:2486:2486) (2658:2658:2658)) + (PORT d[9] (774:774:774) (839:839:839)) + (PORT d[10] (732:732:732) (787:787:787)) + (PORT d[11] (1198:1198:1198) (1240:1240:1240)) + (PORT d[12] (723:723:723) (773:773:773)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) ) ) (TIMINGCHECK @@ -34963,8 +44001,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (967:967:967) (945:945:945)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (1249:1249:1249) (1220:1220:1220)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) ) ) (TIMINGCHECK @@ -34976,8 +44014,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1860:1860:1860) (1888:1888:1888)) - (PORT d[0] (2089:2089:2089) (2073:2073:2073)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + (PORT d[0] (1711:1711:1711) (1677:1677:1677)) ) ) ) @@ -34986,7 +44024,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1844:1844:1844) (1872:1872:1872)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -34996,7 +44034,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1844:1844:1844) (1872:1872:1872)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -35006,7 +44044,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1844:1844:1844) (1872:1872:1872)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -35016,7 +44054,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) + (PORT clk (1844:1844:1844) (1872:1872:1872)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -35026,7 +44064,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1820:1820:1820) (1847:1847:1847)) + (PORT clk (1803:1803:1803) (1830:1830:1830)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -35040,7 +44078,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1005:1005:1005) (1010:1010:1010)) + (PORT clk (988:988:988) (993:993:993)) ) ) ) @@ -35049,7 +44087,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) + (PORT clk (989:989:989) (994:994:994)) ) ) ) @@ -35058,7 +44096,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) + (PORT clk (989:989:989) (994:994:994)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -35068,24 +44106,161 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) + (PORT clk (989:989:989) (994:994:994)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~0) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (682:682:682) (752:752:752)) - (PORT datab (688:688:688) (754:754:754)) - (PORT datac (786:786:786) (795:795:795)) - (PORT datad (864:864:864) (896:896:896)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT d[0] (1001:1001:1001) (1024:1024:1024)) + (PORT clk (1847:1847:1847) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2737:2737:2737) (2961:2961:2961)) + (PORT d[1] (1936:1936:1936) (2018:2018:2018)) + (PORT d[2] (998:998:998) (1029:1029:1029)) + (PORT d[3] (969:969:969) (994:994:994)) + (PORT d[4] (1425:1425:1425) (1469:1469:1469)) + (PORT d[5] (958:958:958) (992:992:992)) + (PORT d[6] (1158:1158:1158) (1170:1170:1170)) + (PORT d[7] (2950:2950:2950) (3104:3104:3104)) + (PORT d[8] (1588:1588:1588) (1675:1675:1675)) + (PORT d[9] (737:737:737) (777:777:777)) + (PORT d[10] (715:715:715) (752:752:752)) + (PORT d[11] (2487:2487:2487) (2667:2667:2667)) + (PORT d[12] (760:760:760) (814:814:814)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (948:948:948) (922:922:922)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (3281:3281:3281) (3342:3342:3342)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1807:1807:1807) (1834:1834:1834)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (992:992:992) (997:997:997)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) @@ -35094,7 +44269,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (700:700:700) (744:744:744)) + (PORT d[0] (1192:1192:1192) (1163:1163:1163)) (PORT clk (1860:1860:1860) (1887:1887:1887)) ) ) @@ -35107,19 +44282,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3167:3167:3167) (3303:3303:3303)) - (PORT d[1] (2937:2937:2937) (3208:3208:3208)) - (PORT d[2] (967:967:967) (987:987:987)) - (PORT d[3] (1341:1341:1341) (1401:1401:1401)) - (PORT d[4] (2612:2612:2612) (2843:2843:2843)) - (PORT d[5] (2651:2651:2651) (2894:2894:2894)) - (PORT d[6] (960:960:960) (1001:1001:1001)) - (PORT d[7] (1270:1270:1270) (1343:1343:1343)) - (PORT d[8] (1442:1442:1442) (1513:1513:1513)) - (PORT d[9] (971:971:971) (1019:1019:1019)) - (PORT d[10] (1031:1031:1031) (1057:1057:1057)) - (PORT d[11] (2872:2872:2872) (3095:3095:3095)) - (PORT d[12] (969:969:969) (1020:1020:1020)) + (PORT d[0] (2546:2546:2546) (2729:2729:2729)) + (PORT d[1] (3618:3618:3618) (3824:3824:3824)) + (PORT d[2] (2381:2381:2381) (2458:2458:2458)) + (PORT d[3] (4288:4288:4288) (4492:4492:4492)) + (PORT d[4] (3170:3170:3170) (3405:3405:3405)) + (PORT d[5] (4727:4727:4727) (4889:4889:4889)) + (PORT d[6] (2532:2532:2532) (2627:2627:2627)) + (PORT d[7] (1392:1392:1392) (1407:1407:1407)) + (PORT d[8] (3122:3122:3122) (3282:3282:3282)) + (PORT d[9] (1802:1802:1802) (1840:1840:1840)) + (PORT d[10] (1997:1997:1997) (2034:2034:2034)) + (PORT d[11] (3401:3401:3401) (3659:3659:3659)) + (PORT d[12] (4693:4693:4693) (4992:4992:4992)) (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) @@ -35132,7 +44307,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1245:1245:1245) (1221:1221:1221)) + (PORT d[0] (1888:1888:1888) (1943:1943:1943)) (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) @@ -35146,7 +44321,7 @@ (DELAY (ABSOLUTE (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (2049:2049:2049) (2003:2003:2003)) + (PORT d[0] (2445:2445:2445) (2405:2405:2405)) ) ) ) @@ -35242,170 +44417,17 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (743:743:743) (772:772:772)) - (PORT clk (1859:1859:1859) (1886:1886:1886)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3188:3188:3188) (3327:3327:3327)) - (PORT d[1] (2678:2678:2678) (2951:2951:2951)) - (PORT d[2] (1298:1298:1298) (1309:1309:1309)) - (PORT d[3] (1348:1348:1348) (1402:1402:1402)) - (PORT d[4] (2616:2616:2616) (2850:2850:2850)) - (PORT d[5] (2675:2675:2675) (2903:2903:2903)) - (PORT d[6] (1230:1230:1230) (1289:1289:1289)) - (PORT d[7] (1132:1132:1132) (1148:1148:1148)) - (PORT d[8] (1470:1470:1470) (1552:1552:1552)) - (PORT d[9] (1550:1550:1550) (1617:1617:1617)) - (PORT d[10] (724:724:724) (767:767:767)) - (PORT d[11] (2854:2854:2854) (3086:3086:3086)) - (PORT d[12] (971:971:971) (1034:1034:1034)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1229:1229:1229) (1208:1208:1208)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1886:1886:1886)) - (PORT d[0] (1822:1822:1822) (1811:1811:1811)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) + (INSTANCE D\[1\]\~38) (DELAY (ABSOLUTE - (PORT dataa (1242:1242:1242) (1299:1299:1299)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (968:968:968) (1003:1003:1003)) - (PORT datad (1089:1089:1089) (1119:1119:1119)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (983:983:983) (1077:1077:1077)) + (PORT datab (1231:1231:1231) (1326:1326:1326)) + (PORT datac (912:912:912) (954:954:954)) + (PORT datad (1090:1090:1090) (1094:1094:1094)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -35413,11 +44435,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (746:746:746) (776:776:776)) - (PORT clk (1853:1853:1853) (1881:1881:1881)) + (PORT d[0] (1370:1370:1370) (1410:1410:1410)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) ) ) (TIMINGCHECK @@ -35426,23 +44448,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2906:2906:2906) (3003:3003:3003)) - (PORT d[1] (2374:2374:2374) (2624:2624:2624)) - (PORT d[2] (1590:1590:1590) (1604:1604:1604)) - (PORT d[3] (1983:1983:1983) (2059:2059:2059)) - (PORT d[4] (2920:2920:2920) (3176:3176:3176)) - (PORT d[5] (2692:2692:2692) (2903:2903:2903)) - (PORT d[6] (1267:1267:1267) (1350:1350:1350)) - (PORT d[7] (1307:1307:1307) (1395:1395:1395)) - (PORT d[8] (1742:1742:1742) (1842:1842:1842)) - (PORT d[9] (1557:1557:1557) (1621:1621:1621)) - (PORT d[10] (2161:2161:2161) (2306:2306:2306)) - (PORT d[11] (3233:3233:3233) (3375:3375:3375)) - (PORT d[12] (1281:1281:1281) (1357:1357:1357)) - (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT d[0] (2461:2461:2461) (2613:2613:2613)) + (PORT d[1] (2479:2479:2479) (2511:2511:2511)) + (PORT d[2] (2577:2577:2577) (2775:2775:2775)) + (PORT d[3] (1707:1707:1707) (1744:1744:1744)) + (PORT d[4] (2415:2415:2415) (2564:2564:2564)) + (PORT d[5] (3183:3183:3183) (3261:3261:3261)) + (PORT d[6] (2218:2218:2218) (2320:2320:2320)) + (PORT d[7] (1719:1719:1719) (1754:1754:1754)) + (PORT d[8] (2452:2452:2452) (2554:2554:2554)) + (PORT d[9] (1710:1710:1710) (1761:1761:1761)) + (PORT d[10] (2530:2530:2530) (2628:2628:2628)) + (PORT d[11] (4031:4031:4031) (4326:4326:4326)) + (PORT d[12] (2475:2475:2475) (2545:2545:2545)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) ) ) (TIMINGCHECK @@ -35451,11 +44473,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2941:2941:2941) (2895:2895:2895)) - (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT d[0] (2002:2002:2002) (1964:1964:1964)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) ) ) (TIMINGCHECK @@ -35464,60 +44486,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (PORT d[0] (3092:3092:3092) (3136:3136:3136)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2204:2204:2204) (2160:2160:2160)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) + (PORT clk (1853:1853:1853) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) + (PORT clk (1853:1853:1853) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) + (PORT clk (1853:1853:1853) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) + (PORT clk (1853:1853:1853) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1808:1808:1808) (1806:1806:1806)) + (PORT clk (1812:1812:1812) (1838:1838:1838)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -35528,281 +44550,55 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (2118:2118:2118) (2165:2165:2165)) - (PORT clk (1818:1818:1818) (1812:1812:1812)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4374:4374:4374) (4418:4418:4418)) - (PORT d[1] (4140:4140:4140) (4128:4128:4128)) - (PORT d[2] (4277:4277:4277) (4327:4327:4327)) - (PORT d[3] (4389:4389:4389) (4374:4374:4374)) - (PORT d[4] (4369:4369:4369) (4385:4385:4385)) - (PORT d[5] (4402:4402:4402) (4357:4357:4357)) - (PORT d[6] (4635:4635:4635) (4717:4717:4717)) - (PORT d[7] (4444:4444:4444) (4393:4393:4393)) - (PORT d[8] (4445:4445:4445) (4433:4433:4433)) - (PORT d[9] (4508:4508:4508) (4699:4699:4699)) - (PORT d[10] (4409:4409:4409) (4440:4440:4440)) - (PORT d[11] (4509:4509:4509) (4563:4563:4563)) - (PORT d[12] (4429:4429:4429) (4547:4547:4547)) - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) + (PORT clk (997:997:997) (1001:1001:1001)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + (PORT clk (998:998:998) (1002:1002:1002)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) + (PORT clk (998:998:998) (1002:1002:1002)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) + (PORT clk (998:998:998) (1002:1002:1002)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~39) (DELAY (ABSOLUTE - (PORT d[0] (2570:2570:2570) (2648:2648:2648)) - (PORT d[1] (2033:2033:2033) (2232:2232:2232)) - (PORT d[2] (2324:2324:2324) (2498:2498:2498)) - (PORT d[3] (2521:2521:2521) (2687:2687:2687)) - (PORT d[4] (2940:2940:2940) (3191:3191:3191)) - (PORT d[5] (2266:2266:2266) (2447:2447:2447)) - (PORT d[6] (1866:1866:1866) (1990:1990:1990)) - (PORT d[7] (2543:2543:2543) (2628:2628:2628)) - (PORT d[8] (2767:2767:2767) (2988:2988:2988)) - (PORT d[9] (1759:1759:1759) (1863:1863:1863)) - (PORT d[10] (1515:1515:1515) (1609:1609:1609)) - (PORT d[11] (3453:3453:3453) (3586:3586:3586)) - (PORT d[12] (1542:1542:1542) (1649:1649:1649)) - (PORT clk (1868:1868:1868) (1894:1894:1894)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1868:1868:1868) (1894:1894:1894)) - (PORT d[0] (2191:2191:2191) (2247:2247:2247)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1895:1895:1895)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1831:1831:1831) (1857:1857:1857)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1016:1016:1016) (1020:1020:1020)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1021:1021:1021)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1511:1511:1511) (1554:1554:1554)) - (PORT d[1] (2684:2684:2684) (2948:2948:2948)) - (PORT d[2] (989:989:989) (1036:1036:1036)) - (PORT d[3] (1684:1684:1684) (1752:1752:1752)) - (PORT d[4] (2594:2594:2594) (2826:2826:2826)) - (PORT d[5] (2711:2711:2711) (2920:2920:2920)) - (PORT d[6] (973:973:973) (1031:1031:1031)) - (PORT d[7] (964:964:964) (1018:1018:1018)) - (PORT d[8] (1426:1426:1426) (1505:1505:1505)) - (PORT d[9] (1567:1567:1567) (1660:1660:1660)) - (PORT d[10] (2478:2478:2478) (2623:2623:2623)) - (PORT d[11] (2885:2885:2885) (3126:3126:3126)) - (PORT d[12] (1271:1271:1271) (1324:1324:1324)) - (PORT clk (1855:1855:1855) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (PORT d[0] (872:872:872) (859:859:859)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + (PORT dataa (1520:1520:1520) (1636:1636:1636)) + (PORT datab (1198:1198:1198) (1226:1226:1226)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1384:1384:1384) (1422:1422:1422)) + (IOPATH dataa combout (341:341:341) (320:320:320)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -35811,8 +44607,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (926:926:926) (931:931:931)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (1498:1498:1498) (1529:1529:1529)) + (PORT clk (1866:1866:1866) (1893:1893:1893)) ) ) (TIMINGCHECK @@ -35824,20 +44620,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3174:3174:3174) (3295:3295:3295)) - (PORT d[1] (2670:2670:2670) (2938:2938:2938)) - (PORT d[2] (1591:1591:1591) (1604:1604:1604)) - (PORT d[3] (1700:1700:1700) (1749:1749:1749)) - (PORT d[4] (2908:2908:2908) (3176:3176:3176)) - (PORT d[5] (2711:2711:2711) (2920:2920:2920)) - (PORT d[6] (974:974:974) (1032:1032:1032)) - (PORT d[7] (1544:1544:1544) (1607:1607:1607)) - (PORT d[8] (3051:3051:3051) (3314:3314:3314)) - (PORT d[9] (996:996:996) (1062:1062:1062)) - (PORT d[10] (2482:2482:2482) (2620:2620:2620)) - (PORT d[11] (2859:2859:2859) (3096:3096:3096)) - (PORT d[12] (2233:2233:2233) (2338:2338:2338)) - (PORT clk (1854:1854:1854) (1880:1880:1880)) + (PORT d[0] (2502:2502:2502) (2600:2600:2600)) + (PORT d[1] (2280:2280:2280) (2376:2376:2376)) + (PORT d[2] (2063:2063:2063) (2187:2187:2187)) + (PORT d[3] (3319:3319:3319) (3431:3431:3431)) + (PORT d[4] (2302:2302:2302) (2458:2458:2458)) + (PORT d[5] (3776:3776:3776) (3885:3885:3885)) + (PORT d[6] (2525:2525:2525) (2638:2638:2638)) + (PORT d[7] (2494:2494:2494) (2555:2555:2555)) + (PORT d[8] (2947:2947:2947) (3049:3049:3049)) + (PORT d[9] (2749:2749:2749) (2863:2863:2863)) + (PORT d[10] (2929:2929:2929) (3041:3041:3041)) + (PORT d[11] (2742:2742:2742) (2907:2907:2907)) + (PORT d[12] (3512:3512:3512) (3716:3716:3716)) + (PORT clk (1863:1863:1863) (1889:1889:1889)) ) ) (TIMINGCHECK @@ -35849,8 +44645,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3083:3083:3083) (3081:3081:3081)) - (PORT clk (1854:1854:1854) (1880:1880:1880)) + (PORT d[0] (2834:2834:2834) (2862:2862:2862)) + (PORT clk (1863:1863:1863) (1889:1889:1889)) ) ) (TIMINGCHECK @@ -35862,8 +44658,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (PORT d[0] (1803:1803:1803) (1787:1787:1787)) + (PORT clk (1866:1866:1866) (1893:1893:1893)) + (PORT d[0] (3571:3571:3571) (3500:3500:3500)) ) ) ) @@ -35872,7 +44668,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) + (PORT clk (1867:1867:1867) (1894:1894:1894)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -35882,7 +44678,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) + (PORT clk (1867:1867:1867) (1894:1894:1894)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -35892,7 +44688,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) + (PORT clk (1867:1867:1867) (1894:1894:1894)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -35902,7 +44698,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) + (PORT clk (1867:1867:1867) (1894:1894:1894)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -35912,7 +44708,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1812:1812:1812) (1809:1809:1809)) + (PORT clk (1821:1821:1821) (1818:1818:1818)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -35926,8 +44722,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2405:2405:2405) (2433:2433:2433)) - (PORT clk (1822:1822:1822) (1815:1815:1815)) + (PORT d[0] (2189:2189:2189) (2175:2175:2175)) + (PORT clk (1831:1831:1831) (1824:1824:1824)) ) ) (TIMINGCHECK @@ -35939,20 +44735,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4622:4622:4622) (4649:4649:4649)) - (PORT d[1] (4242:4242:4242) (4320:4320:4320)) - (PORT d[2] (4251:4251:4251) (4295:4295:4295)) - (PORT d[3] (4399:4399:4399) (4422:4422:4422)) - (PORT d[4] (4340:4340:4340) (4354:4354:4354)) - (PORT d[5] (4534:4534:4534) (4546:4546:4546)) - (PORT d[6] (4731:4731:4731) (4801:4801:4801)) - (PORT d[7] (4488:4488:4488) (4531:4531:4531)) - (PORT d[8] (4436:4436:4436) (4436:4436:4436)) - (PORT d[9] (4525:4525:4525) (4711:4711:4711)) - (PORT d[10] (4473:4473:4473) (4495:4495:4495)) - (PORT d[11] (4414:4414:4414) (4386:4386:4386)) - (PORT d[12] (4391:4391:4391) (4381:4381:4381)) - (PORT clk (1818:1818:1818) (1811:1811:1811)) + (PORT d[0] (4520:4520:4520) (4545:4545:4545)) + (PORT d[1] (4445:4445:4445) (4516:4516:4516)) + (PORT d[2] (4525:4525:4525) (4596:4596:4596)) + (PORT d[3] (4398:4398:4398) (4408:4408:4408)) + (PORT d[4] (4281:4281:4281) (4404:4404:4404)) + (PORT d[5] (4393:4393:4393) (4465:4465:4465)) + (PORT d[6] (4259:4259:4259) (4355:4355:4355)) + (PORT d[7] (4414:4414:4414) (4478:4478:4478)) + (PORT d[8] (4545:4545:4545) (4666:4666:4666)) + (PORT d[9] (4382:4382:4382) (4434:4434:4434)) + (PORT d[10] (4247:4247:4247) (4300:4300:4300)) + (PORT d[11] (4433:4433:4433) (4558:4558:4558)) + (PORT d[12] (4266:4266:4266) (4271:4271:4271)) + (PORT clk (1827:1827:1827) (1820:1820:1820)) ) ) (TIMINGCHECK @@ -35964,7 +44760,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1822:1822:1822) (1815:1815:1815)) + (PORT clk (1831:1831:1831) (1824:1824:1824)) ) ) ) @@ -35973,7 +44769,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) + (PORT clk (1832:1832:1832) (1825:1825:1825)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -35983,7 +44779,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) + (PORT clk (1832:1832:1832) (1825:1825:1825)) (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) ) ) @@ -35993,7 +44789,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) + (PORT clk (1832:1832:1832) (1825:1825:1825)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -36003,7 +44799,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) + (PORT clk (1832:1832:1832) (1825:1825:1825)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -36013,7 +44809,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) (DELAY (ABSOLUTE - (PORT clk (1814:1814:1814) (1811:1811:1811)) + (PORT clk (1823:1823:1823) (1820:1820:1820)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -36022,3309 +44818,24 @@ (HOLD d (posedge clk) (159:159:159)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (731:731:731)) - (PORT datab (1192:1192:1192) (1240:1240:1240)) - (PORT datac (825:825:825) (833:833:833)) - (PORT datad (890:890:890) (911:911:911)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1189:1189:1189) (1198:1198:1198)) - (PORT datab (1192:1192:1192) (1240:1240:1240)) - (PORT datac (1509:1509:1509) (1586:1586:1586)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~103) - (DELAY - (ABSOLUTE - (PORT dataa (1738:1738:1738) (1846:1846:1846)) - (PORT datab (1412:1412:1412) (1506:1506:1506)) - (PORT datac (648:648:648) (701:701:701)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_DAT\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (479:479:479) (732:732:732)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE reset\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (842:842:842) (859:859:859)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) - (DELAY - (ABSOLUTE - (PORT dataa (282:282:282) (386:386:386)) - (PORT datab (291:291:291) (382:382:382)) - (PORT datad (245:245:245) (325:325:325)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE PS2_CLK\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (479:479:479) (732:732:732)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (3358:3358:3358) (3700:3700:3700)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (225:225:225) (297:297:297)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (227:227:227) (302:302:302)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (239:239:239) (309:309:309)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (342:342:342)) - (PORT datab (250:250:250) (335:335:335)) - (PORT datac (380:380:380) (441:441:441)) - (PORT datad (225:225:225) (298:298:298)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (227:227:227) (299:299:299)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (228:228:228) (301:301:301)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (226:226:226) (298:298:298)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (252:252:252) (337:337:337)) - (PORT datac (225:225:225) (305:305:305)) - (PORT datad (227:227:227) (299:299:299)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (226:226:226) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) - (DELAY - (ABSOLUTE - (PORT datab (208:208:208) (249:249:249)) - (PORT datad (227:227:227) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) - (DELAY - (ABSOLUTE - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (218:218:218) (295:295:295)) - (PORT datad (224:224:224) (296:296:296)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|clk_edge) - (DELAY - (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1562:1562:1562)) - (PORT ena (2016:2016:2016) (2055:2055:2055)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) - (DELAY - (ABSOLUTE - (PORT dataa (282:282:282) (387:387:387)) - (PORT datab (292:292:292) (383:383:383)) - (PORT datad (240:240:240) (317:317:317)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1562:1562:1562)) - (PORT ena (2016:2016:2016) (2055:2055:2055)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) - (DELAY - (ABSOLUTE - (PORT dataa (279:279:279) (382:382:382)) - (PORT datab (278:278:278) (373:373:373)) - (PORT datad (242:242:242) (321:321:321)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1562:1562:1562)) - (PORT ena (2016:2016:2016) (2055:2055:2055)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (480:480:480)) - (PORT datab (279:279:279) (374:374:374)) - (PORT datad (243:243:243) (322:322:322)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1562:1562:1562)) - (PORT ena (2016:2016:2016) (2055:2055:2055)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|always1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (275:275:275) (377:377:377)) - (PORT datab (288:288:288) (377:377:377)) - (PORT datac (3414:3414:3414) (3775:3775:3775)) - (PORT datad (251:251:251) (331:331:331)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT datab (289:289:289) (380:380:380)) - (PORT datac (247:247:247) (341:341:341)) - (PORT datad (248:248:248) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (264:264:264) (354:354:354)) - (PORT datac (1368:1368:1368) (1427:1427:1427)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT asdata (3957:3957:3957) (4311:4311:4311)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (1226:1226:1226) (1215:1215:1215)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT asdata (560:560:560) (634:634:634)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (1226:1226:1226) (1215:1215:1215)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT asdata (602:602:602) (685:685:685)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (1226:1226:1226) (1215:1215:1215)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT asdata (588:588:588) (665:665:665)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (1226:1226:1226) (1215:1215:1215)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT asdata (958:958:958) (1010:1010:1010)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT asdata (960:960:960) (1018:1018:1018)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (1226:1226:1226) (1215:1215:1215)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT asdata (951:951:951) (1014:1014:1014)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT asdata (761:761:761) (840:840:840)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT asdata (791:791:791) (867:867:867)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (990:990:990) (1075:1075:1075)) - (PORT datab (675:675:675) (742:742:742)) - (PORT datac (757:757:757) (876:876:876)) - (PORT datad (781:781:781) (888:888:888)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1415:1415:1415) (1549:1549:1549)) - (PORT datab (937:937:937) (1037:1037:1037)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (763:763:763) (875:875:875)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|extended\~0) - (DELAY - (ABSOLUTE - (PORT datab (1062:1062:1062) (1155:1155:1155)) - (PORT datad (785:785:785) (795:795:795)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (664:664:664) (722:722:722)) - (PORT datab (288:288:288) (378:378:378)) - (PORT datad (833:833:833) (880:880:880)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (741:741:741) (827:827:827)) - (PORT datab (669:669:669) (749:749:749)) - (PORT datac (655:655:655) (721:721:721)) - (PORT datad (438:438:438) (511:511:511)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) - (DELAY - (ABSOLUTE - (PORT datab (668:668:668) (736:736:736)) - (PORT datac (345:345:345) (369:369:369)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (255:255:255)) - (PORT datab (3434:3434:3434) (3812:3812:3812)) - (PORT datac (1368:1368:1368) (1428:1428:1428)) - (PORT datad (358:358:358) (390:390:390)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1562:1562:1562)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|extended) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1764:1764:1764) (1796:1796:1796)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (758:758:758)) - (PORT datab (664:664:664) (692:692:692)) - (PORT datac (260:260:260) (346:346:346)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (553:553:553)) - (PORT datac (1367:1367:1367) (1453:1453:1453)) - (PORT datad (841:841:841) (864:864:864)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1265:1265:1265)) - (PORT datac (641:641:641) (670:670:670)) - (PORT datad (910:910:910) (977:977:977)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~0) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (426:426:426)) - (PORT datac (615:615:615) (667:667:667)) - (PORT datad (726:726:726) (803:803:803)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|released\~0) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (736:736:736)) - (PORT datab (663:663:663) (694:694:694)) - (PORT datad (1337:1337:1337) (1379:1379:1379)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|released) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) - (DELAY - (ABSOLUTE - (PORT dataa (488:488:488) (568:568:568)) - (PORT datab (663:663:663) (740:740:740)) - (PORT datac (606:606:606) (673:673:673)) - (PORT datad (259:259:259) (336:336:336)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~2) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (247:247:247)) - (PORT datac (416:416:416) (498:498:498)) - (PORT datad (651:651:651) (725:725:725)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~3) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (616:616:616)) - (PORT datab (428:428:428) (507:507:507)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|shifted) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (744:744:744) (848:848:848)) - (PORT datab (984:984:984) (1072:1072:1072)) - (PORT datad (962:962:962) (1042:1042:1042)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT datab (751:751:751) (858:858:858)) - (PORT datac (739:739:739) (840:840:840)) - (PORT datad (729:729:729) (835:835:835)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (394:394:394)) - (PORT datab (201:201:201) (241:241:241)) - (PORT datad (175:175:175) (202:202:202)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT datab (963:963:963) (1041:1041:1041)) - (PORT datad (729:729:729) (834:834:834)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (740:740:740) (827:827:827)) - (PORT datab (290:290:290) (378:378:378)) - (PORT datac (649:649:649) (725:725:725)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~32) - (DELAY - (ABSOLUTE - (PORT datab (655:655:655) (729:729:729)) - (PORT datac (395:395:395) (471:471:471)) - (PORT datad (657:657:657) (716:716:716)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (418:418:418)) - (PORT datab (223:223:223) (270:270:270)) - (PORT datac (658:658:658) (723:723:723)) - (PORT datad (433:433:433) (507:507:507)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (269:269:269)) - (PORT datab (622:622:622) (671:671:671)) - (PORT datad (962:962:962) (1038:1038:1038)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1160:1160:1160) (1230:1230:1230)) - (PORT datab (241:241:241) (321:321:321)) - (PORT datac (215:215:215) (291:291:291)) - (PORT datad (548:548:548) (570:570:570)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (969:969:969) (1044:1044:1044)) - (PORT datac (902:902:902) (995:995:995)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1413:1413:1413) (1549:1549:1549)) - (PORT datab (696:696:696) (729:729:729)) - (PORT datac (959:959:959) (1041:1041:1041)) - (PORT datad (190:190:190) (224:224:224)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT datab (981:981:981) (1070:1070:1070)) - (PORT datac (721:721:721) (830:830:830)) - (PORT datad (729:729:729) (838:838:838)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (908:908:908)) - (PORT datab (667:667:667) (685:685:685)) - (PORT datad (496:496:496) (512:512:512)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1414:1414:1414) (1542:1542:1542)) - (PORT datab (213:213:213) (258:258:258)) - (PORT datac (667:667:667) (692:692:692)) - (PORT datad (766:766:766) (872:872:872)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (716:716:716) (818:818:818)) - (PORT datab (363:363:363) (394:394:394)) - (PORT datac (717:717:717) (819:819:819)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1555:1555:1555) (1666:1666:1666)) - (PORT datab (982:982:982) (1037:1037:1037)) - (PORT datad (518:518:518) (530:530:530)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~0) - (DELAY - (ABSOLUTE - (PORT datab (1469:1469:1469) (1606:1606:1606)) - (PORT datac (912:912:912) (975:975:975)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (425:425:425) (503:503:503)) - (PORT datac (1117:1117:1117) (1170:1170:1170)) - (PORT datad (651:651:651) (723:723:723)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (693:693:693) (776:776:776)) - (PORT datab (412:412:412) (493:493:493)) - (PORT datac (606:606:606) (674:674:674)) - (PORT datad (261:261:261) (340:340:340)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (490:490:490) (569:569:569)) - (PORT datab (664:664:664) (741:741:741)) - (PORT datac (497:497:497) (515:515:515)) - (PORT datad (655:655:655) (724:724:724)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (615:615:615)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (768:768:768)) - (PORT datab (1230:1230:1230) (1291:1291:1291)) - (PORT datac (443:443:443) (506:506:506)) - (PORT datad (1066:1066:1066) (1109:1109:1109)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (752:752:752) (844:844:844)) - (PORT datab (1400:1400:1400) (1489:1489:1489)) - (PORT datac (917:917:917) (988:988:988)) - (PORT datad (854:854:854) (921:921:921)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (279:279:279)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (739:739:739) (839:839:839)) - (PORT datad (1547:1547:1547) (1637:1637:1637)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (523:523:523) (533:533:533)) - (PORT datad (944:944:944) (998:998:998)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (670:670:670) (729:729:729)) - (PORT datab (1120:1120:1120) (1195:1195:1195)) - (PORT datac (633:633:633) (694:694:694)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (687:687:687) (745:745:745)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (195:195:195) (228:228:228)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (484:484:484) (550:550:550)) - (PORT datab (1228:1228:1228) (1291:1291:1291)) - (PORT datac (741:741:741) (842:842:842)) - (PORT datad (842:842:842) (867:867:867)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (875:875:875)) - (PORT datab (913:913:913) (986:986:986)) - (PORT datac (1115:1115:1115) (1162:1162:1162)) - (PORT datad (710:710:710) (791:791:791)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (325:325:325)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (395:395:395)) - (PORT datac (700:700:700) (784:784:784)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (776:776:776) (868:868:868)) - (PORT datab (912:912:912) (984:984:984)) - (PORT datac (659:659:659) (735:735:735)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (710:710:710)) - (PORT datab (496:496:496) (580:580:580)) - (PORT datac (396:396:396) (470:470:470)) - (PORT datad (601:601:601) (643:643:643)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (937:937:937)) - (PORT datab (941:941:941) (1038:1038:1038)) - (PORT datac (758:758:758) (878:878:878)) - (PORT datad (764:764:764) (871:871:871)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) - (DELAY - (ABSOLUTE - (PORT dataa (820:820:820) (932:932:932)) - (PORT datab (788:788:788) (904:904:904)) - (PORT datad (763:763:763) (876:876:876)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) - (DELAY - (ABSOLUTE - (PORT dataa (824:824:824) (935:935:935)) - (PORT datab (938:938:938) (1037:1037:1037)) - (PORT datac (757:757:757) (875:875:875)) - (PORT datad (764:764:764) (875:875:875)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~7) - (DELAY - (ABSOLUTE - (PORT dataa (232:232:232) (279:279:279)) - (PORT datab (941:941:941) (1039:1039:1039)) - (PORT datac (311:311:311) (337:337:337)) - (PORT datad (1387:1387:1387) (1504:1504:1504)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1416:1416:1416) (1544:1544:1544)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (932:932:932) (1003:1003:1003)) - (PORT datad (517:517:517) (528:528:528)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (398:398:398)) - (PORT datab (274:274:274) (359:359:359)) - (PORT datad (604:604:604) (617:617:617)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1387:1387:1387) (1447:1447:1447)) - (PORT datab (411:411:411) (471:471:471)) - (PORT datac (1375:1375:1375) (1408:1408:1408)) - (PORT datad (583:583:583) (631:631:631)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (804:804:804)) - (PORT datab (3348:3348:3348) (3488:3488:3488)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1705:1705:1705) (1713:1713:1713)) - (PORT datab (1225:1225:1225) (1301:1301:1301)) - (PORT datac (636:636:636) (675:675:675)) - (PORT datad (1144:1144:1144) (1160:1160:1160)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1504:1504:1504) (1628:1628:1628)) - (PORT datab (1226:1226:1226) (1302:1302:1302)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1240:1240:1240) (1368:1368:1368)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1042:1042:1042)) - (PORT datab (636:636:636) (676:676:676)) - (PORT datac (240:240:240) (293:293:293)) - (PORT datad (1667:1667:1667) (1728:1728:1728)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT datab (912:912:912) (931:931:931)) - (PORT datac (945:945:945) (986:986:986)) - (PORT datad (219:219:219) (254:254:254)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (310:310:310)) - (PORT datab (705:705:705) (769:769:769)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (208:208:208) (240:240:240)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|ir_\|opcode\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (195:195:195) (220:220:220)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1557:1557:1557)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (284:284:284) (380:380:380)) - (PORT datac (903:903:903) (966:966:966)) - (PORT datad (928:928:928) (982:982:982)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1410:1410:1410) (1521:1521:1521)) - (PORT datab (897:897:897) (911:911:911)) - (PORT datac (924:924:924) (1011:1011:1011)) - (PORT datad (876:876:876) (894:894:894)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1572:1572:1572) (1710:1710:1710)) - (PORT datab (2337:2337:2337) (2410:2410:2410)) - (PORT datac (671:671:671) (718:718:718)) - (PORT datad (2748:2748:2748) (2873:2873:2873)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (232:232:232) (283:283:283)) - (PORT datac (195:195:195) (238:238:238)) - (PORT datad (371:371:371) (399:399:399)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (658:658:658)) - (PORT datab (427:427:427) (471:471:471)) - (PORT datac (543:543:543) (559:559:559)) - (PORT datad (1164:1164:1164) (1218:1218:1218)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1490:1490:1490) (1592:1592:1592)) - (PORT datab (438:438:438) (474:474:474)) - (PORT datac (943:943:943) (994:994:994)) - (PORT datad (211:211:211) (243:243:243)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) - (DELAY - (ABSOLUTE - (PORT dataa (974:974:974) (1047:1047:1047)) - (PORT datab (1110:1110:1110) (1179:1179:1179)) - (PORT datac (1261:1261:1261) (1313:1313:1313)) - (PORT datad (1359:1359:1359) (1384:1384:1384)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1101:1101:1101) (1122:1122:1122)) - (PORT datab (961:961:961) (1050:1050:1050)) - (PORT datac (1264:1264:1264) (1310:1310:1310)) - (PORT datad (1206:1206:1206) (1270:1270:1270)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1505:1505:1505) (1526:1526:1526)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (868:868:868) (865:865:865)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1606:1606:1606) (1627:1627:1627)) - (PORT datab (831:831:831) (859:859:859)) - (PORT datad (1029:1029:1029) (1028:1028:1028)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1568:1568:1568) (1597:1597:1597)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (643:643:643) (684:684:684)) - (PORT datad (555:555:555) (558:558:558)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (650:650:650)) - (PORT datab (552:552:552) (565:565:565)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (372:372:372) (397:397:397)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~21) - (DELAY - (ABSOLUTE - (PORT dataa (2257:2257:2257) (2337:2337:2337)) - (PORT datab (1549:1549:1549) (1673:1673:1673)) - (PORT datac (902:902:902) (922:922:922)) - (PORT datad (1165:1165:1165) (1178:1178:1178)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) - (DELAY - (ABSOLUTE - (PORT datab (230:230:230) (277:277:277)) - (PORT datac (343:343:343) (365:365:365)) - (PORT datad (369:369:369) (394:394:394)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1298:1298:1298) (1395:1395:1395)) - (PORT datab (927:927:927) (974:974:974)) - (PORT datac (1940:1940:1940) (2070:2070:2070)) - (PORT datad (2052:2052:2052) (2214:2214:2214)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) - (DELAY - (ABSOLUTE - (PORT dataa (855:855:855) (906:906:906)) - (PORT datab (230:230:230) (277:277:277)) - (PORT datac (196:196:196) (240:240:240)) - (PORT datad (370:370:370) (394:394:394)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1167:1167:1167)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (222:222:222) (268:268:268)) - (PORT datac (200:200:200) (236:236:236)) - (PORT datad (223:223:223) (250:250:250)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1938:1938:1938) (2062:2062:2062)) - (PORT datab (2594:2594:2594) (2695:2695:2695)) - (PORT datad (1436:1436:1436) (1528:1528:1528)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (720:720:720)) - (PORT datab (699:699:699) (758:758:758)) - (PORT datac (1095:1095:1095) (1090:1090:1090)) - (PORT datad (644:644:644) (692:692:692)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (611:611:611) (632:632:632)) - (PORT datad (777:777:777) (789:789:789)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (890:890:890)) - (PORT datab (332:332:332) (362:362:362)) - (PORT datac (372:372:372) (397:397:397)) - (PORT datad (604:604:604) (626:626:626)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1811:1811:1811) (1903:1903:1903)) - (PORT datab (921:921:921) (989:989:989)) - (PORT datac (923:923:923) (1008:1008:1008)) - (PORT datad (436:436:436) (468:468:468)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (966:966:966)) - (PORT datac (902:902:902) (921:921:921)) - (PORT datad (1383:1383:1383) (1455:1455:1455)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (418:418:418) (444:444:444)) - (PORT datac (192:192:192) (225:225:225)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1154:1154:1154) (1242:1242:1242)) - (PORT datab (196:196:196) (236:236:236)) - (PORT datac (593:593:593) (604:604:604)) - (PORT datad (376:376:376) (396:396:396)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1240:1240:1240)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datad (877:877:877) (932:932:932)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) - (DELAY - (ABSOLUTE - (PORT dataa (2446:2446:2446) (2535:2535:2535)) - (PORT datab (1615:1615:1615) (1728:1728:1728)) - (PORT datac (1769:1769:1769) (1897:1897:1897)) - (PORT datad (1666:1666:1666) (1684:1684:1684)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1432:1432:1432) (1515:1515:1515)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (1052:1052:1052) (1100:1100:1100)) - (PORT datad (1335:1335:1335) (1356:1356:1356)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1121:1121:1121) (1241:1241:1241)) - (PORT datac (884:884:884) (939:939:939)) - (PORT datad (957:957:957) (1022:1022:1022)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (935:935:935)) - (PORT datab (944:944:944) (1021:1021:1021)) - (PORT datac (588:588:588) (603:603:603)) - (PORT datad (537:537:537) (536:536:536)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (838:838:838) (860:860:860)) - (PORT datac (169:169:169) (202:202:202)) - (PORT datad (195:195:195) (228:228:228)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1156:1156:1156) (1255:1255:1255)) - (PORT datab (257:257:257) (345:345:345)) - (PORT datac (214:214:214) (290:290:290)) - (PORT datad (580:580:580) (615:615:615)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~20) - (DELAY - (ABSOLUTE - (PORT dataa (572:572:572) (607:607:607)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (590:590:590) (613:613:613)) - (PORT datad (600:600:600) (615:615:615)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1561:1561:1561) (1706:1706:1706)) - (PORT datab (2568:2568:2568) (2670:2670:2670)) - (PORT datac (1057:1057:1057) (1083:1083:1083)) - (PORT datad (862:862:862) (898:898:898)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1089:1089:1089) (1120:1120:1120)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1186:1186:1186) (1228:1228:1228)) - (PORT datad (564:564:564) (579:579:579)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (920:920:920)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (237:237:237) (278:278:278)) - (PORT datad (594:594:594) (611:611:611)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) - (DELAY - (ABSOLUTE - (PORT dataa (948:948:948) (1036:1036:1036)) - (PORT datab (263:263:263) (310:310:310)) - (PORT datac (1393:1393:1393) (1475:1475:1475)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) - (DELAY - (ABSOLUTE - (PORT dataa (923:923:923) (950:950:950)) - (PORT datab (1129:1129:1129) (1199:1199:1199)) - (PORT datac (889:889:889) (932:932:932)) - (PORT datad (1015:1015:1015) (1011:1011:1011)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_set\~0) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (514:514:514)) - (PORT datab (896:896:896) (914:914:914)) - (PORT datac (922:922:922) (1007:1007:1007)) - (PORT datad (405:405:405) (434:434:434)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) - (DELAY - (ABSOLUTE - (PORT datab (1062:1062:1062) (1088:1088:1088)) - (PORT datac (208:208:208) (250:250:250)) - (PORT datad (209:209:209) (241:241:241)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~9) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (524:524:524) (539:539:539)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_cf) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (240:240:240)) - (PORT datab (594:594:594) (613:613:613)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (567:567:567) (592:592:592)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (746:746:746)) - (PORT datab (661:661:661) (721:721:721)) - (PORT datac (883:883:883) (903:903:903)) - (PORT datad (893:893:893) (916:916:916)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (1154:1154:1154) (1188:1188:1188)) - (PORT datad (629:629:629) (643:643:643)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (408:408:408)) - (PORT datab (644:644:644) (678:678:678)) - (PORT datac (871:871:871) (896:896:896)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (701:701:701) (721:721:721)) - (PORT datab (956:956:956) (981:981:981)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (217:217:217) (250:250:250)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (688:688:688) (772:772:772)) - (PORT datac (1115:1115:1115) (1160:1160:1160)) - (PORT datad (739:739:739) (827:827:827)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (785:785:785) (871:871:871)) - (PORT datab (725:725:725) (810:810:810)) - (PORT datac (1118:1118:1118) (1161:1161:1161)) - (PORT datad (711:711:711) (788:788:788)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (915:915:915) (989:989:989)) - (PORT datac (1116:1116:1116) (1162:1162:1162)) - (PORT datad (329:329:329) (349:349:349)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (212:212:212) (261:261:261)) - (PORT datab (199:199:199) (239:239:239)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (727:727:727) (814:814:814)) - (PORT datab (981:981:981) (1068:1068:1068)) - (PORT datac (722:722:722) (831:831:831)) - (PORT datad (729:729:729) (835:835:835)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (903:903:903)) - (PORT datab (736:736:736) (834:834:834)) - (PORT datac (710:710:710) (811:811:811)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (390:390:390)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datad (338:338:338) (357:357:357)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1159:1159:1159) (1230:1230:1230)) - (PORT datab (724:724:724) (793:793:793)) - (PORT datac (214:214:214) (291:291:291)) - (PORT datad (550:550:550) (572:572:572)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (949:949:949) (1028:1028:1028)) - (PORT datab (779:779:779) (879:879:879)) - (PORT datac (1365:1365:1365) (1458:1458:1458)) - (PORT datad (1189:1189:1189) (1251:1251:1251)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~76) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (382:382:382)) - (PORT datab (281:281:281) (364:364:364)) - (PORT datac (928:928:928) (975:975:975)) - (PORT datad (1494:1494:1494) (1585:1585:1585)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~73) - (DELAY - (ABSOLUTE - (PORT datac (740:740:740) (842:842:842)) - (PORT datad (1190:1190:1190) (1255:1255:1255)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (782:782:782) (872:872:872)) - (PORT datab (728:728:728) (815:815:815)) - (PORT datac (884:884:884) (953:953:953)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (751:751:751) (844:844:844)) - (PORT datab (1502:1502:1502) (1605:1605:1605)) - (PORT datac (916:916:916) (991:991:991)) - (PORT datad (852:852:852) (919:919:919)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~74) - (DELAY - (ABSOLUTE - (PORT dataa (588:588:588) (610:610:610)) - (PORT datab (344:344:344) (369:369:369)) - (PORT datac (1366:1366:1366) (1452:1452:1452)) - (PORT datad (1547:1547:1547) (1637:1637:1637)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (245:245:245)) - (PORT datab (201:201:201) (241:241:241)) - (PORT datac (448:448:448) (513:513:513)) - (PORT datad (841:841:841) (864:864:864)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (556:556:556) (571:571:571)) - (PORT datab (335:335:335) (364:364:364)) - (PORT datad (736:736:736) (824:824:824)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (758:758:758) (862:862:862)) - (PORT datab (729:729:729) (828:828:828)) - (PORT datac (335:335:335) (363:363:363)) - (PORT datad (1132:1132:1132) (1201:1201:1201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~72) - (DELAY - (ABSOLUTE - (PORT datab (199:199:199) (239:239:239)) - (PORT datad (718:718:718) (814:814:814)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (455:455:455)) - (PORT datab (1124:1124:1124) (1199:1199:1199)) - (PORT datac (636:636:636) (698:698:698)) - (PORT datad (629:629:629) (680:680:680)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (1557:1557:1557) (1665:1665:1665)) - (PORT datab (981:981:981) (1035:1035:1035)) - (PORT datad (515:515:515) (529:529:529)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (489:489:489) (569:569:569)) - (PORT datac (607:607:607) (672:672:672)) - (PORT datad (260:260:260) (335:335:335)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (404:404:404) (428:428:428)) - (PORT datab (848:848:848) (850:850:850)) - (PORT datad (734:734:734) (821:821:821)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~1) - (DELAY - (ABSOLUTE - (PORT datab (1472:1472:1472) (1607:1607:1607)) - (PORT datac (347:347:347) (411:411:411)) - (PORT datad (901:901:901) (962:962:962)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (220:220:220) (260:260:260)) - (PORT datac (215:215:215) (291:291:291)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~1) - (DELAY - (ABSOLUTE - (PORT datac (1076:1076:1076) (1171:1171:1171)) - (PORT datad (1031:1031:1031) (1115:1115:1115)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (1413:1413:1413) (1543:1543:1543)) - (PORT datab (788:788:788) (903:903:903)) - (PORT datac (960:960:960) (1037:1037:1037)) - (PORT datad (777:777:777) (882:882:882)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (256:256:256)) - (PORT datab (675:675:675) (704:704:704)) - (PORT datac (604:604:604) (622:622:622)) - (PORT datad (901:901:901) (976:976:976)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~92) - (DELAY - (ABSOLUTE - (PORT datab (968:968:968) (1057:1057:1057)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~63) - (DELAY - (ABSOLUTE - (PORT datac (654:654:654) (724:724:724)) - (PORT datad (637:637:637) (707:707:707)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) - (DELAY - (ABSOLUTE - (PORT datab (654:654:654) (726:726:726)) - (PORT datac (693:693:693) (782:782:782)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (258:258:258)) - (PORT datab (473:473:473) (549:549:549)) - (PORT datac (637:637:637) (704:704:704)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~132) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (277:277:277)) - (PORT datab (665:665:665) (741:741:741)) - (PORT datad (650:650:650) (727:727:727)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (926:926:926)) - (PORT datab (223:223:223) (262:262:262)) - (PORT datac (337:337:337) (360:360:360)) - (PORT datad (543:543:543) (562:562:562)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (815:815:815) (820:820:820)) - (PORT datad (946:946:946) (995:995:995)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1387:1387:1387) (1444:1444:1444)) - (PORT datab (598:598:598) (652:652:652)) - (PORT datac (1375:1375:1375) (1406:1406:1406)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (804:804:804)) - (PORT datab (3349:3349:3349) (3490:3490:3490)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (891:891:891) (902:902:902)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1236:1236:1236) (1280:1280:1280)) - (PORT d[1] (983:983:983) (1045:1045:1045)) - (PORT d[2] (962:962:962) (977:977:977)) - (PORT d[3] (1021:1021:1021) (1074:1074:1074)) - (PORT d[4] (2601:2601:2601) (2818:2818:2818)) - (PORT d[5] (1028:1028:1028) (1063:1063:1063)) - (PORT d[6] (994:994:994) (1056:1056:1056)) - (PORT d[7] (954:954:954) (1016:1016:1016)) - (PORT d[8] (1046:1046:1046) (1093:1093:1093)) - (PORT d[9] (998:998:998) (1055:1055:1055)) - (PORT d[10] (1047:1047:1047) (1121:1121:1121)) - (PORT d[11] (2576:2576:2576) (2762:2762:2762)) - (PORT d[12] (1307:1307:1307) (1386:1386:1386)) + (PORT d[0] (1902:1902:1902) (2025:2025:2025)) + (PORT d[1] (1666:1666:1666) (1705:1705:1705)) + (PORT d[2] (1974:1974:1974) (2139:2139:2139)) + (PORT d[3] (1912:1912:1912) (1969:1969:1969)) + (PORT d[4] (2671:2671:2671) (2790:2790:2790)) + (PORT d[5] (2298:2298:2298) (2357:2357:2357)) + (PORT d[6] (1731:1731:1731) (1793:1793:1793)) + (PORT d[7] (2013:2013:2013) (2076:2076:2076)) + (PORT d[8] (1842:1842:1842) (1934:1934:1934)) + (PORT d[9] (2037:2037:2037) (2110:2110:2110)) + (PORT d[10] (1682:1682:1682) (1747:1747:1747)) + (PORT d[11] (4325:4325:4325) (4639:4639:4639)) + (PORT d[12] (1649:1649:1649) (1703:1703:1703)) (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) @@ -39334,70 +44845,27 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) (DELAY (ABSOLUTE - (PORT d[0] (951:951:951) (911:911:911)) (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (1484:1484:1484) (1455:1455:1455)) + (PORT d[0] (1818:1818:1818) (1849:1849:1849)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) + (PORT clk (1858:1858:1858) (1884:1884:1884)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1820:1820:1820) (1846:1846:1846)) @@ -39411,7 +44879,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1005:1005:1005) (1009:1009:1009)) @@ -39420,7 +44888,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -39429,7 +44897,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -39439,7 +44907,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1010:1010:1010)) @@ -39449,729 +44917,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (980:980:980) (991:991:991)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (706:706:706) (727:727:727)) - (PORT d[1] (2392:2392:2392) (2624:2624:2624)) - (PORT d[2] (1503:1503:1503) (1540:1540:1540)) - (PORT d[3] (981:981:981) (1040:1040:1040)) - (PORT d[4] (2591:2591:2591) (2807:2807:2807)) - (PORT d[5] (3468:3468:3468) (3668:3668:3668)) - (PORT d[6] (1271:1271:1271) (1334:1334:1334)) - (PORT d[7] (3191:3191:3191) (3366:3366:3366)) - (PORT d[8] (691:691:691) (713:713:713)) - (PORT d[9] (1603:1603:1603) (1661:1661:1661)) - (PORT d[10] (1346:1346:1346) (1434:1434:1434)) - (PORT d[11] (2230:2230:2230) (2413:2413:2413)) - (PORT d[12] (1570:1570:1570) (1649:1649:1649)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (671:671:671) (627:627:627)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (1485:1485:1485) (1441:1441:1441)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1101:1101:1101) (1111:1111:1111)) - (PORT clk (1859:1859:1859) (1886:1886:1886)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (986:986:986) (1014:1014:1014)) - (PORT d[1] (3450:3450:3450) (3742:3742:3742)) - (PORT d[2] (1249:1249:1249) (1290:1290:1290)) - (PORT d[3] (1284:1284:1284) (1331:1331:1331)) - (PORT d[4] (2575:2575:2575) (2806:2806:2806)) - (PORT d[5] (3485:3485:3485) (3709:3709:3709)) - (PORT d[6] (1317:1317:1317) (1415:1415:1415)) - (PORT d[7] (1218:1218:1218) (1279:1279:1279)) - (PORT d[8] (1003:1003:1003) (1027:1027:1027)) - (PORT d[9] (1567:1567:1567) (1623:1623:1623)) - (PORT d[10] (1356:1356:1356) (1454:1454:1454)) - (PORT d[11] (2251:2251:2251) (2436:2436:2436)) - (PORT d[12] (1606:1606:1606) (1702:1702:1702)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (963:963:963) (919:919:919)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1886:1886:1886)) - (PORT d[0] (1702:1702:1702) (1655:1655:1655)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (409:409:409)) - (PORT datab (686:686:686) (752:752:752)) - (PORT datac (651:651:651) (716:716:716)) - (PORT datad (645:645:645) (655:655:655)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1183:1183:1183) (1208:1208:1208)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3642:3642:3642) (3824:3824:3824)) - (PORT d[1] (1366:1366:1366) (1493:1493:1493)) - (PORT d[2] (2003:2003:2003) (2099:2099:2099)) - (PORT d[3] (2459:2459:2459) (2585:2585:2585)) - (PORT d[4] (2200:2200:2200) (2332:2332:2332)) - (PORT d[5] (1345:1345:1345) (1450:1450:1450)) - (PORT d[6] (1456:1456:1456) (1487:1487:1487)) - (PORT d[7] (3346:3346:3346) (3494:3494:3494)) - (PORT d[8] (3607:3607:3607) (3856:3856:3856)) - (PORT d[9] (3167:3167:3167) (3306:3306:3306)) - (PORT d[10] (3154:3154:3154) (3327:3327:3327)) - (PORT d[11] (1793:1793:1793) (1891:1891:1891)) - (PORT d[12] (1416:1416:1416) (1454:1454:1454)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1620:1620:1620) (1580:1580:1580)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (PORT d[0] (2766:2766:2766) (2809:2809:2809)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1837:1837:1837)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (1047:1047:1047) (1075:1075:1075)) - (PORT datab (1410:1410:1410) (1504:1504:1504)) - (PORT datac (532:532:532) (545:545:545)) - (PORT datad (1173:1173:1173) (1173:1173:1173)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1641:1641:1641) (1729:1729:1729)) - (PORT clk (1857:1857:1857) (1885:1885:1885)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2872:2872:2872) (2966:2966:2966)) - (PORT d[1] (2017:2017:2017) (2182:2182:2182)) - (PORT d[2] (1954:1954:1954) (2061:2061:2061)) - (PORT d[3] (1897:1897:1897) (2022:2022:2022)) - (PORT d[4] (3021:3021:3021) (3172:3172:3172)) - (PORT d[5] (2229:2229:2229) (2391:2391:2391)) - (PORT d[6] (1711:1711:1711) (1774:1774:1774)) - (PORT d[7] (2133:2133:2133) (2250:2250:2250)) - (PORT d[8] (2427:2427:2427) (2610:2610:2610)) - (PORT d[9] (1679:1679:1679) (1785:1785:1785)) - (PORT d[10] (1442:1442:1442) (1508:1508:1508)) - (PORT d[11] (1723:1723:1723) (1780:1780:1780)) - (PORT d[12] (2286:2286:2286) (2347:2347:2347)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2567:2567:2567) (2620:2620:2620)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1885:1885:1885)) - (PORT d[0] (3733:3733:3733) (3648:3648:3648)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1810:1810:1810)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2034:2034:2034) (2028:2028:2028)) - (PORT clk (1822:1822:1822) (1816:1816:1816)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4393:4393:4393) (4461:4461:4461)) - (PORT d[1] (4131:4131:4131) (4181:4181:4181)) - (PORT d[2] (4247:4247:4247) (4323:4323:4323)) - (PORT d[3] (4546:4546:4546) (4614:4614:4614)) - (PORT d[4] (4322:4322:4322) (4309:4309:4309)) - (PORT d[5] (4617:4617:4617) (4651:4651:4651)) - (PORT d[6] (4408:4408:4408) (4485:4485:4485)) - (PORT d[7] (4302:4302:4302) (4274:4274:4274)) - (PORT d[8] (4572:4572:4572) (4637:4637:4637)) - (PORT d[9] (4446:4446:4446) (4691:4691:4691)) - (PORT d[10] (4705:4705:4705) (4743:4743:4743)) - (PORT d[11] (4358:4358:4358) (4390:4390:4390)) - (PORT d[12] (4507:4507:4507) (4645:4645:4645)) - (PORT clk (1818:1818:1818) (1812:1812:1812)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1816:1816:1816)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1812:1812:1812)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2840:2840:2840) (2949:2949:2949)) - (PORT d[1] (1732:1732:1732) (1897:1897:1897)) - (PORT d[2] (1932:1932:1932) (2053:2053:2053)) - (PORT d[3] (1899:1899:1899) (2019:2019:2019)) - (PORT d[4] (2772:2772:2772) (2916:2916:2916)) - (PORT d[5] (2232:2232:2232) (2415:2415:2415)) - (PORT d[6] (2007:2007:2007) (2069:2069:2069)) - (PORT d[7] (2130:2130:2130) (2260:2260:2260)) - (PORT d[8] (2390:2390:2390) (2571:2571:2571)) - (PORT d[9] (1959:1959:1959) (2082:2082:2082)) - (PORT d[10] (1985:1985:1985) (2067:2067:2067)) - (PORT d[11] (2017:2017:2017) (2091:2091:2091)) - (PORT d[12] (2566:2566:2566) (2656:2656:2656)) + (PORT d[0] (2479:2479:2479) (2628:2628:2628)) + (PORT d[1] (2661:2661:2661) (2805:2805:2805)) + (PORT d[2] (2218:2218:2218) (2383:2383:2383)) + (PORT d[3] (2113:2113:2113) (2258:2258:2258)) + (PORT d[4] (2079:2079:2079) (2164:2164:2164)) + (PORT d[5] (2439:2439:2439) (2558:2558:2558)) + (PORT d[6] (2443:2443:2443) (2606:2606:2606)) + (PORT d[7] (3431:3431:3431) (3496:3496:3496)) + (PORT d[8] (2846:2846:2846) (2932:2932:2932)) + (PORT d[9] (2326:2326:2326) (2495:2495:2495)) + (PORT d[10] (3304:3304:3304) (3449:3449:3449)) + (PORT d[11] (2127:2127:2127) (2238:2238:2238)) + (PORT d[12] (2274:2274:2274) (2444:2444:2444)) (PORT clk (1859:1859:1859) (1884:1884:1884)) ) ) @@ -40181,17 +44942,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1859:1859:1859) (1884:1884:1884)) - (PORT d[0] (2730:2730:2730) (2796:2796:2796)) + (PORT d[0] (2586:2586:2586) (2674:2674:2674)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1860:1860:1860) (1885:1885:1885)) @@ -40201,7 +44962,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1822:1822:1822) (1847:1847:1847)) @@ -40215,7 +44976,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1007:1007:1007) (1010:1010:1010)) @@ -40224,7 +44985,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1008:1008:1008) (1011:1011:1011)) @@ -40233,7 +44994,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1008:1008:1008) (1011:1011:1011)) @@ -40243,7 +45004,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1008:1008:1008) (1011:1011:1011)) @@ -40253,11 +45014,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1622:1622:1622) (1706:1706:1706)) - (PORT clk (1855:1855:1855) (1883:1883:1883)) + (PORT d[0] (1617:1617:1617) (1708:1708:1708)) + (PORT clk (1857:1857:1857) (1885:1885:1885)) ) ) (TIMINGCHECK @@ -40266,23 +45027,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2870:2870:2870) (2964:2964:2964)) - (PORT d[1] (2048:2048:2048) (2231:2231:2231)) - (PORT d[2] (1893:1893:1893) (1990:1990:1990)) - (PORT d[3] (1883:1883:1883) (2014:2014:2014)) - (PORT d[4] (3037:3037:3037) (3174:3174:3174)) - (PORT d[5] (1957:1957:1957) (2122:2122:2122)) - (PORT d[6] (1728:1728:1728) (1783:1783:1783)) - (PORT d[7] (1821:1821:1821) (1856:1856:1856)) - (PORT d[8] (2421:2421:2421) (2612:2612:2612)) - (PORT d[9] (1968:1968:1968) (2080:2080:2080)) - (PORT d[10] (2002:2002:2002) (2089:2089:2089)) - (PORT d[11] (2528:2528:2528) (2597:2597:2597)) - (PORT d[12] (2240:2240:2240) (2309:2309:2309)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2779:2779:2779) (2918:2918:2918)) + (PORT d[1] (2949:2949:2949) (3110:3110:3110)) + (PORT d[2] (1977:1977:1977) (2112:2112:2112)) + (PORT d[3] (1867:1867:1867) (1994:1994:1994)) + (PORT d[4] (2099:2099:2099) (2223:2223:2223)) + (PORT d[5] (2640:2640:2640) (2717:2717:2717)) + (PORT d[6] (2148:2148:2148) (2291:2291:2291)) + (PORT d[7] (3421:3421:3421) (3502:3502:3502)) + (PORT d[8] (3155:3155:3155) (3258:3258:3258)) + (PORT d[9] (2282:2282:2282) (2439:2439:2439)) + (PORT d[10] (1914:1914:1914) (2041:2041:2041)) + (PORT d[11] (2100:2100:2100) (2231:2231:2231)) + (PORT d[12] (2417:2417:2417) (2564:2564:2564)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) ) ) (TIMINGCHECK @@ -40291,11 +45052,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2519:2519:2519) (2503:2503:2503)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2032:2032:2032) (1996:1996:1996)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) ) ) (TIMINGCHECK @@ -40304,60 +45065,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (PORT d[0] (3674:3674:3674) (3756:3756:3756)) + (PORT clk (1857:1857:1857) (1885:1885:1885)) + (PORT d[0] (3200:3200:3200) (3274:3274:3274)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) + (PORT clk (1858:1858:1858) (1886:1886:1886)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) + (PORT clk (1858:1858:1858) (1886:1886:1886)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) + (PORT clk (1858:1858:1858) (1886:1886:1886)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) + (PORT clk (1858:1858:1858) (1886:1886:1886)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1810:1810:1810) (1808:1808:1808)) + (PORT clk (1812:1812:1812) (1810:1810:1810)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -40368,11 +45129,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2034:2034:2034) (2023:2023:2023)) - (PORT clk (1820:1820:1820) (1814:1814:1814)) + (PORT d[0] (2121:2121:2121) (2166:2166:2166)) + (PORT clk (1822:1822:1822) (1816:1816:1816)) ) ) (TIMINGCHECK @@ -40381,23 +45142,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4437:4437:4437) (4508:4508:4508)) - (PORT d[1] (4211:4211:4211) (4251:4251:4251)) - (PORT d[2] (4278:4278:4278) (4341:4341:4341)) - (PORT d[3] (4543:4543:4543) (4609:4609:4609)) - (PORT d[4] (4346:4346:4346) (4342:4342:4342)) - (PORT d[5] (4610:4610:4610) (4641:4641:4641)) - (PORT d[6] (4708:4708:4708) (4757:4757:4757)) - (PORT d[7] (4312:4312:4312) (4268:4268:4268)) - (PORT d[8] (4489:4489:4489) (4504:4504:4504)) - (PORT d[9] (4453:4453:4453) (4722:4722:4722)) - (PORT d[10] (4622:4622:4622) (4654:4654:4654)) - (PORT d[11] (4366:4366:4366) (4392:4392:4392)) - (PORT d[12] (4506:4506:4506) (4645:4645:4645)) - (PORT clk (1816:1816:1816) (1810:1810:1810)) + (PORT d[0] (4469:4469:4469) (4578:4578:4578)) + (PORT d[1] (4411:4411:4411) (4529:4529:4529)) + (PORT d[2] (4405:4405:4405) (4501:4501:4501)) + (PORT d[3] (4285:4285:4285) (4378:4378:4378)) + (PORT d[4] (4390:4390:4390) (4479:4479:4479)) + (PORT d[5] (4452:4452:4452) (4565:4565:4565)) + (PORT d[6] (4355:4355:4355) (4476:4476:4476)) + (PORT d[7] (4330:4330:4330) (4373:4373:4373)) + (PORT d[8] (4626:4626:4626) (4732:4732:4732)) + (PORT d[9] (4460:4460:4460) (4519:4519:4519)) + (PORT d[10] (4392:4392:4392) (4490:4490:4490)) + (PORT d[11] (4393:4393:4393) (4515:4515:4515)) + (PORT d[12] (4353:4353:4353) (4336:4336:4336)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) ) ) (TIMINGCHECK @@ -40406,206 +45167,109 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1820:1820:1820) (1814:1814:1814)) + (PORT clk (1822:1822:1822) (1816:1816:1816)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) + (PORT clk (1823:1823:1823) (1817:1817:1817)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) + (PORT clk (1823:1823:1823) (1817:1817:1817)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) + (PORT clk (1823:1823:1823) (1817:1817:1817)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) + (PORT clk (1823:1823:1823) (1817:1817:1817)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~52) + (INSTANCE D\[1\]\~35) (DELAY (ABSOLUTE - (PORT dataa (1206:1206:1206) (1287:1287:1287)) - (PORT datab (1437:1437:1437) (1489:1489:1489)) - (PORT datac (1126:1126:1126) (1177:1177:1177)) - (PORT datad (1429:1429:1429) (1485:1485:1485)) + (PORT dataa (931:931:931) (978:978:978)) + (PORT datab (772:772:772) (879:879:879)) + (PORT datac (1450:1450:1450) (1528:1528:1528)) + (PORT datad (1149:1149:1149) (1208:1208:1208)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~36) (DELAY (ABSOLUTE - (PORT d[0] (3633:3633:3633) (3814:3814:3814)) - (PORT d[1] (2642:2642:2642) (2867:2867:2867)) - (PORT d[2] (1648:1648:1648) (1726:1726:1726)) - (PORT d[3] (2160:2160:2160) (2263:2263:2263)) - (PORT d[4] (2162:2162:2162) (2254:2254:2254)) - (PORT d[5] (1662:1662:1662) (1786:1786:1786)) - (PORT d[6] (1132:1132:1132) (1171:1171:1171)) - (PORT d[7] (1160:1160:1160) (1190:1190:1190)) - (PORT d[8] (2171:2171:2171) (2353:2353:2353)) - (PORT d[9] (2266:2266:2266) (2413:2413:2413)) - (PORT d[10] (2562:2562:2562) (2693:2693:2693)) - (PORT d[11] (915:915:915) (961:961:961)) - (PORT d[12] (1750:1750:1750) (1775:1775:1775)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1874:1874:1874)) - (PORT d[0] (3453:3453:3453) (3330:3330:3330)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1837:1837:1837)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + (PORT dataa (1069:1069:1069) (1095:1095:1095)) + (PORT datab (1028:1028:1028) (1086:1086:1086)) + (PORT datac (1634:1634:1634) (1682:1682:1682)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~53) + (INSTANCE D\[1\]\~37) (DELAY (ABSOLUTE - (PORT dataa (1208:1208:1208) (1217:1217:1217)) - (PORT datab (1079:1079:1079) (1088:1088:1088)) - (PORT datac (181:181:181) (219:219:219)) - (PORT datad (1384:1384:1384) (1408:1408:1408)) + (PORT dataa (751:751:751) (855:855:855)) + (PORT datab (1736:1736:1736) (1857:1857:1857)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (182:182:182) (212:212:212)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~54) + (INSTANCE D\[1\]\~118) (DELAY (ABSOLUTE - (PORT dataa (1502:1502:1502) (1614:1614:1614)) - (PORT datab (951:951:951) (1007:1007:1007)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~106) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (778:778:778)) - (PORT datab (1164:1164:1164) (1255:1255:1255)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (174:174:174) (198:198:198)) + (PORT dataa (1727:1727:1727) (1788:1788:1788)) + (PORT datab (3006:3006:3006) (3259:3259:3259)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (175:175:175) (201:201:201)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -40615,45 +45279,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~57) + (INSTANCE D\[1\]\~40) (DELAY (ABSOLUTE - (PORT dataa (1972:1972:1972) (2064:2064:2064)) - (PORT datab (1148:1148:1148) (1200:1200:1200)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (843:843:843) (868:868:868)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (933:933:933) (952:952:952)) + (PORT datab (904:904:904) (927:927:927)) + (PORT datac (1645:1645:1645) (1661:1661:1661)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~58) + (INSTANCE D\[1\]\~41) (DELAY (ABSOLUTE - (PORT dataa (1975:1975:1975) (2066:2066:2066)) - (PORT datab (647:647:647) (708:708:708)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1634:1634:1634) (1673:1673:1673)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1165:1165:1165) (1251:1251:1251)) + (PORT datab (1465:1465:1465) (1529:1529:1529)) + (PORT datac (3210:3210:3210) (3305:3305:3305)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) (DELAY (ABSOLUTE - (PORT dataa (977:977:977) (1044:1044:1044)) - (PORT datab (918:918:918) (964:964:964)) - (PORT datac (244:244:244) (297:297:297)) - (PORT datad (1588:1588:1588) (1606:1606:1606)) + (PORT dataa (932:932:932) (991:991:991)) + (PORT datab (424:424:424) (459:459:459)) + (PORT datac (194:194:194) (228:228:228)) + (PORT datad (1128:1128:1128) (1155:1155:1155)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -40663,10 +45327,10 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[0\]) + (INSTANCE z80_\|data_pins_\|dout\[1\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT clk (1527:1527:1527) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) (PORT ena (841:841:841) (846:846:846)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -40679,28 +45343,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~16) + (INSTANCE z80_\|bus_control_\|db\[1\]\~11) (DELAY (ABSOLUTE - (PORT datab (393:393:393) (423:423:423)) - (PORT datac (407:407:407) (468:468:468)) - (PORT datad (674:674:674) (692:692:692)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (981:981:981) (1004:1004:1004)) - (PORT datab (1377:1377:1377) (1376:1376:1376)) - (PORT datac (889:889:889) (939:939:939)) - (PORT datad (892:892:892) (894:894:894)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (266:266:266) (349:349:349)) + (PORT datac (596:596:596) (602:602:602)) + (PORT datad (384:384:384) (411:411:411)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -40709,31 +45359,81 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[0\]) + (INSTANCE z80_\|ir_\|opcode\[1\]) (DELAY (ABSOLUTE - (PORT clk (1519:1519:1519) (1532:1532:1532)) - (PORT asdata (1523:1523:1523) (1555:1555:1555)) - (PORT clrn (1576:1576:1576) (1555:1555:1555)) - (PORT ena (1506:1506:1506) (1484:1484:1484)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1577:1577:1577) (1558:1558:1558)) + (PORT ena (1917:1917:1917) (1918:1918:1918)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal63\~0) + (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) (DELAY (ABSOLUTE - (PORT dataa (1988:1988:1988) (2128:2128:2128)) - (PORT datab (1534:1534:1534) (1633:1633:1633)) - (PORT datac (227:227:227) (272:272:272)) - (PORT datad (1108:1108:1108) (1149:1149:1149)) + (PORT dataa (1600:1600:1600) (1731:1731:1731)) + (PORT datab (1942:1942:1942) (2048:2048:2048)) + (PORT datac (365:365:365) (407:407:407)) + (PORT datad (1162:1162:1162) (1219:1219:1219)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instED) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1565:1565:1565) (1545:1545:1545)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (778:778:778) (849:849:849)) + (PORT datab (767:767:767) (837:837:837)) + (PORT datac (1838:1838:1838) (1974:1974:1974)) + (PORT datad (1691:1691:1691) (1759:1759:1759)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2118:2118:2118) (2286:2286:2286)) + (PORT datab (1408:1408:1408) (1515:1515:1515)) + (PORT datac (1119:1119:1119) (1147:1147:1147)) + (PORT datad (878:878:878) (904:904:904)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -40743,15 +45443,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) (DELAY (ABSOLUTE - (PORT dataa (1494:1494:1494) (1599:1599:1599)) - (PORT datab (1480:1480:1480) (1588:1588:1588)) - (PORT datac (1844:1844:1844) (1910:1910:1910)) - (PORT datad (400:400:400) (434:434:434)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (1624:1624:1624) (1656:1656:1656)) + (PORT datab (641:641:641) (673:673:673)) + (PORT datac (1029:1029:1029) (1091:1091:1091)) + (PORT datad (2619:2619:2619) (2695:2695:2695)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -40759,29 +45459,47 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) (DELAY (ABSOLUTE - (PORT dataa (357:357:357) (496:496:496)) - (PORT datab (712:712:712) (746:746:746)) - (PORT datac (1434:1434:1434) (1535:1535:1535)) - (PORT datad (1300:1300:1300) (1393:1393:1393)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1812:1812:1812) (1882:1882:1882)) + (PORT datab (1076:1076:1076) (1143:1143:1143)) + (PORT datac (829:829:829) (850:850:850)) + (PORT datad (2598:2598:2598) (2658:2658:2658)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~10) + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) (DELAY (ABSOLUTE - (PORT dataa (684:684:684) (734:734:734)) - (PORT datac (1154:1154:1154) (1186:1186:1186)) - (PORT datad (918:918:918) (942:942:942)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (877:877:877) (938:938:938)) + (PORT datab (1059:1059:1059) (1129:1129:1129)) + (PORT datac (1832:1832:1832) (1913:1913:1913)) + (PORT datad (626:626:626) (665:665:665)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1622:1622:1622) (1655:1655:1655)) + (PORT datab (2274:2274:2274) (2434:2434:2434)) + (PORT datac (617:617:617) (675:675:675)) + (PORT datad (986:986:986) (1083:1083:1083)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -40789,304 +45507,60 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~11) + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) (DELAY (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (661:661:661) (720:720:720)) - (PORT datac (871:871:871) (900:900:900)) + (PORT dataa (708:708:708) (768:768:768)) + (PORT datab (947:947:947) (968:968:968)) + (PORT datac (1488:1488:1488) (1481:1481:1481)) + (PORT datad (637:637:637) (690:690:690)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (625:625:625) (645:645:645)) + (PORT datab (1172:1172:1172) (1176:1176:1176)) + (PORT datac (553:553:553) (580:580:580)) + (PORT datad (640:640:640) (656:656:656)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (173:173:173) (197:197:197)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (530:530:530) (558:558:558)) - (PORT datab (903:903:903) (932:932:932)) - (PORT datac (591:591:591) (604:604:604)) - (PORT datad (1156:1156:1156) (1185:1185:1185)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (673:673:673)) - (PORT datab (955:955:955) (981:981:981)) - (PORT datac (646:646:646) (694:694:694)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (897:897:897) (931:931:931)) - (PORT datab (243:243:243) (291:291:291)) - (PORT datac (626:626:626) (680:680:680)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~119) - (DELAY - (ABSOLUTE - (PORT dataa (757:757:757) (859:859:859)) - (PORT datab (722:722:722) (821:821:821)) - (PORT datac (1142:1142:1142) (1227:1227:1227)) - (PORT datad (912:912:912) (978:978:978)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~120) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (707:707:707)) - (PORT datab (345:345:345) (371:371:371)) - (PORT datac (711:711:711) (812:812:812)) - (PORT datad (733:733:733) (834:834:834)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~95) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (904:904:904)) - (PORT datac (708:708:708) (801:801:801)) - (PORT datad (1136:1136:1136) (1221:1221:1221)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~121) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (243:243:243)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~117) - (DELAY - (ABSOLUTE - (PORT dataa (444:444:444) (535:535:535)) - (PORT datab (659:659:659) (735:735:735)) - (PORT datad (723:723:723) (804:804:804)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~136) - (DELAY - (ABSOLUTE - (PORT dataa (563:563:563) (585:585:585)) - (PORT datab (451:451:451) (519:519:519)) - (PORT datad (651:651:651) (723:723:723)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~130) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (763:763:763)) - (PORT datab (663:663:663) (692:692:692)) - (PORT datad (833:833:833) (881:881:881)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~118) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (905:905:905)) - (PORT datab (628:628:628) (650:650:650)) - (PORT datad (616:616:616) (634:634:634)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (894:894:894) (906:906:906)) - (PORT datab (874:874:874) (902:902:902)) - (PORT datac (610:610:610) (671:671:671)) - (PORT datad (657:657:657) (708:708:708)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~126) (DELAY (ABSOLUTE - (PORT dataa (822:822:822) (934:934:934)) - (PORT datab (697:697:697) (727:727:727)) - (PORT datac (960:960:960) (1039:1039:1039)) - (PORT datad (1384:1384:1384) (1501:1501:1501)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~128) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1046:1046:1046)) - (PORT datab (788:788:788) (902:902:902)) - (PORT datac (903:903:903) (997:997:997)) - (PORT datad (767:767:767) (878:878:878)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~129) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (385:385:385)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datad (904:904:904) (977:977:977)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~127) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (636:636:636)) - (PORT datab (964:964:964) (1050:1050:1050)) - (PORT datad (568:568:568) (584:584:584)) + (PORT dataa (210:210:210) (257:257:257)) + (PORT datab (501:501:501) (575:575:575)) + (PORT datad (632:632:632) (650:650:650)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -41099,9 +45573,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) + (PORT clk (1504:1504:1504) (1518:1518:1518)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -41110,46 +45584,16 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1590:1590:1590) (1687:1687:1687)) - (PORT datac (744:744:744) (848:848:848)) - (PORT datad (713:713:713) (799:799:799)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (730:730:730)) - (PORT datab (1231:1231:1231) (1291:1291:1291)) - (PORT datac (920:920:920) (989:989:989)) - (PORT datad (331:331:331) (350:350:350)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~125) (DELAY (ABSOLUTE - (PORT dataa (210:210:210) (260:260:260)) - (PORT datab (965:965:965) (1053:1053:1053)) - (PORT datad (361:361:361) (388:388:388)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (PORT dataa (330:330:330) (441:441:441)) + (PORT datab (383:383:383) (413:413:413)) + (PORT datad (188:188:188) (221:221:221)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -41160,9 +45604,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) + (PORT clk (1505:1505:1505) (1519:1519:1519)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -41173,30 +45617,77 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~79) + (INSTANCE D\[4\]\~88) (DELAY (ABSOLUTE - (PORT dataa (1349:1349:1349) (1392:1392:1392)) - (PORT datab (1223:1223:1223) (1278:1278:1278)) - (PORT datac (216:216:216) (293:293:293)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (415:415:415) (477:477:477)) + (PORT datab (947:947:947) (1001:1001:1001)) + (PORT datac (849:849:849) (861:861:861)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~120) + (DELAY + (ABSOLUTE + (PORT dataa (515:515:515) (595:595:595)) + (PORT datab (932:932:932) (1014:1014:1014)) + (PORT datac (754:754:754) (837:837:837)) + (PORT datad (707:707:707) (775:775:775)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~121) + (DELAY + (ABSOLUTE + (PORT dataa (679:679:679) (702:702:702)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (456:456:456) (525:525:525)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1504:1504:1504) (1518:1518:1518)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~122) (DELAY (ABSOLUTE - (PORT dataa (447:447:447) (536:536:536)) - (PORT datab (659:659:659) (734:734:734)) - (PORT datad (725:725:725) (804:804:804)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datab (785:785:785) (866:866:866)) + (PORT datac (1271:1271:1271) (1329:1329:1329)) + (PORT datad (241:241:241) (310:310:310)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -41206,10 +45697,10 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~123) (DELAY (ABSOLUTE - (PORT dataa (585:585:585) (608:608:608)) - (PORT datab (728:728:728) (826:826:826)) - (PORT datac (1546:1546:1546) (1656:1656:1656)) - (PORT datad (580:580:580) (596:596:596)) + (PORT dataa (730:730:730) (818:818:818)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (729:729:729) (816:816:816)) + (PORT datad (620:620:620) (641:641:641)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -41222,11 +45713,11 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~124) (DELAY (ABSOLUTE - (PORT dataa (656:656:656) (689:689:689)) - (PORT datab (745:745:745) (852:852:852)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (PORT dataa (504:504:504) (578:578:578)) + (PORT datab (1381:1381:1381) (1376:1376:1376)) + (PORT datad (316:316:316) (326:326:326)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -41237,9 +45728,86 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1505:1505:1505) (1520:1520:1520)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (1270:1270:1270) (1344:1344:1344)) + (PORT datab (912:912:912) (941:941:941)) + (PORT datac (606:606:606) (657:657:657)) + (PORT datad (645:645:645) (700:700:700)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~115) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (755:755:755)) + (PORT datab (722:722:722) (807:807:807)) + (PORT datac (1231:1231:1231) (1295:1295:1295)) + (PORT datad (1207:1207:1207) (1281:1281:1281)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~116) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (647:647:647)) + (PORT datab (754:754:754) (844:844:844)) + (PORT datac (685:685:685) (783:783:783)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~117) + (DELAY + (ABSOLUTE + (PORT datab (207:207:207) (249:249:249)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1511:1511:1511) (1525:1525:1525)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1538:1538:1538)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -41253,10 +45821,26 @@ (INSTANCE ula_\|zx_keyboard_\|key_row\~3) (DELAY (ABSOLUTE - (PORT datab (1510:1510:1510) (1603:1603:1603)) - (PORT datac (869:869:869) (961:961:961)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (2314:2314:2314) (2533:2533:2533)) + (PORT datab (1430:1430:1430) (1559:1559:1559)) + (PORT datad (666:666:666) (718:718:718)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~118) + (DELAY + (ABSOLUTE + (PORT dataa (298:298:298) (401:401:401)) + (PORT datab (954:954:954) (1025:1025:1025)) + (PORT datac (1000:1000:1000) (1060:1060:1060)) + (PORT datad (711:711:711) (787:787:787)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -41264,60 +45848,60 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~80) + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~131) (DELAY (ABSOLUTE - (PORT dataa (377:377:377) (453:453:453)) - (PORT datab (632:632:632) (659:659:659)) - (PORT datac (1349:1349:1349) (1408:1408:1408)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~111) - (DELAY - (ABSOLUTE - (PORT dataa (793:793:793) (903:903:903)) - (PORT datac (702:702:702) (794:794:794)) - (PORT datad (1130:1130:1130) (1214:1214:1214)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~97) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1266:1266:1266)) - (PORT datab (724:724:724) (824:824:824)) - (PORT datac (642:642:642) (670:670:670)) - (PORT datad (909:909:909) (977:977:977)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~116) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (411:411:411)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datad (183:183:183) (213:213:213)) + (PORT dataa (1064:1064:1064) (1139:1139:1139)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (259:259:259) (337:337:337)) (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~119) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (440:440:440)) + (PORT datab (631:631:631) (657:657:657)) + (PORT datad (832:832:832) (834:834:834)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1505:1505:1505) (1519:1519:1519)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1545:1545:1545) (1537:1537:1537)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~114) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (259:259:259)) + (PORT datab (653:653:653) (667:667:667)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -41328,9 +45912,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1511:1511:1511) (1525:1525:1525)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (PORT clrn (1545:1545:1545) (1538:1538:1538)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -41341,14 +45925,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~115) + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~113) (DELAY (ABSOLUTE - (PORT dataa (585:585:585) (605:605:605)) - (PORT datab (363:363:363) (394:394:394)) - (PORT datad (717:717:717) (811:811:811)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (787:787:787) (871:871:871)) + (PORT datab (612:612:612) (637:637:637)) + (PORT datad (589:589:589) (605:605:605)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -41359,9 +45943,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1508:1508:1508) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1543:1543:1543) (1536:1536:1536)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -41372,658 +45956,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~77) + (INSTANCE D\[4\]\~85) (DELAY (ABSOLUTE - (PORT dataa (1136:1136:1136) (1168:1168:1168)) - (PORT datab (1142:1142:1142) (1214:1214:1214)) - (PORT datac (639:639:639) (698:698:698)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (1616:1616:1616) (1662:1662:1662)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3349:3349:3349) (3565:3565:3565)) - (PORT d[1] (1605:1605:1605) (1743:1743:1743)) - (PORT d[2] (2398:2398:2398) (2522:2522:2522)) - (PORT d[3] (1878:1878:1878) (1993:1993:1993)) - (PORT d[4] (1904:1904:1904) (2011:2011:2011)) - (PORT d[5] (2072:2072:2072) (2262:2262:2262)) - (PORT d[6] (2267:2267:2267) (2352:2352:2352)) - (PORT d[7] (2156:2156:2156) (2268:2268:2268)) - (PORT d[8] (2927:2927:2927) (3117:3117:3117)) - (PORT d[9] (2257:2257:2257) (2323:2323:2323)) - (PORT d[10] (4015:4015:4015) (4256:4256:4256)) - (PORT d[11] (1788:1788:1788) (1883:1883:1883)) - (PORT d[12] (2324:2324:2324) (2423:2423:2423)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (2435:2435:2435) (2530:2530:2530)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1496:1496:1496) (1570:1570:1570)) - (PORT clk (1848:1848:1848) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3471:3471:3471) (3598:3598:3598)) - (PORT d[1] (1681:1681:1681) (1841:1841:1841)) - (PORT d[2] (1803:1803:1803) (1868:1868:1868)) - (PORT d[3] (2137:2137:2137) (2245:2245:2245)) - (PORT d[4] (2206:2206:2206) (2306:2306:2306)) - (PORT d[5] (1648:1648:1648) (1787:1787:1787)) - (PORT d[6] (1447:1447:1447) (1468:1468:1468)) - (PORT d[7] (1455:1455:1455) (1504:1504:1504)) - (PORT d[8] (2907:2907:2907) (3106:3106:3106)) - (PORT d[9] (2261:2261:2261) (2404:2404:2404)) - (PORT d[10] (2303:2303:2303) (2432:2432:2432)) - (PORT d[11] (2139:2139:2139) (2251:2251:2251)) - (PORT d[12] (2022:2022:2022) (2077:2077:2077)) - (PORT clk (1845:1845:1845) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2862:2862:2862) (2854:2854:2854)) - (PORT clk (1845:1845:1845) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (PORT d[0] (4272:4272:4272) (4376:4376:4376)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1803:1803:1803) (1801:1801:1801)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1739:1739:1739) (1715:1715:1715)) - (PORT clk (1813:1813:1813) (1807:1807:1807)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4403:4403:4403) (4442:4442:4442)) - (PORT d[1] (4232:4232:4232) (4305:4305:4305)) - (PORT d[2] (4291:4291:4291) (4336:4336:4336)) - (PORT d[3] (4528:4528:4528) (4564:4564:4564)) - (PORT d[4] (4637:4637:4637) (4664:4664:4664)) - (PORT d[5] (4315:4315:4315) (4358:4358:4358)) - (PORT d[6] (4706:4706:4706) (4798:4798:4798)) - (PORT d[7] (4277:4277:4277) (4349:4349:4349)) - (PORT d[8] (4511:4511:4511) (4526:4526:4526)) - (PORT d[9] (4469:4469:4469) (4738:4738:4738)) - (PORT d[10] (4368:4368:4368) (4407:4407:4407)) - (PORT d[11] (4392:4392:4392) (4374:4374:4374)) - (PORT d[12] (4337:4337:4337) (4342:4342:4342)) - (PORT clk (1809:1809:1809) (1803:1803:1803)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1813:1813:1813) (1807:1807:1807)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4186:4186:4186) (4425:4425:4425)) - (PORT d[1] (2884:2884:2884) (3131:3131:3131)) - (PORT d[2] (2708:2708:2708) (2819:2819:2819)) - (PORT d[3] (2283:2283:2283) (2458:2458:2458)) - (PORT d[4] (2517:2517:2517) (2710:2710:2710)) - (PORT d[5] (2529:2529:2529) (2722:2722:2722)) - (PORT d[6] (1890:1890:1890) (2008:2008:2008)) - (PORT d[7] (2314:2314:2314) (2443:2443:2443)) - (PORT d[8] (3115:3115:3115) (3376:3376:3376)) - (PORT d[9] (2627:2627:2627) (2762:2762:2762)) - (PORT d[10] (4822:4822:4822) (5078:5078:5078)) - (PORT d[11] (1897:1897:1897) (2050:2050:2050)) - (PORT d[12] (2209:2209:2209) (2354:2354:2354)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1882:1882:1882)) - (PORT d[0] (3638:3638:3638) (3555:3555:3555)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1555:1555:1555) (1647:1647:1647)) - (PORT clk (1849:1849:1849) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3013:3013:3013) (3193:3193:3193)) - (PORT d[1] (2314:2314:2314) (2501:2501:2501)) - (PORT d[2] (2182:2182:2182) (2293:2293:2293)) - (PORT d[3] (1900:1900:1900) (2029:2029:2029)) - (PORT d[4] (2430:2430:2430) (2538:2538:2538)) - (PORT d[5] (1950:1950:1950) (2108:2108:2108)) - (PORT d[6] (1747:1747:1747) (1762:1762:1762)) - (PORT d[7] (2376:2376:2376) (2506:2506:2506)) - (PORT d[8] (2895:2895:2895) (3077:3077:3077)) - (PORT d[9] (1983:1983:1983) (2113:2113:2113)) - (PORT d[10] (2017:2017:2017) (2125:2125:2125)) - (PORT d[11] (2437:2437:2437) (2546:2546:2546)) - (PORT d[12] (2561:2561:2561) (2626:2626:2626)) - (PORT clk (1846:1846:1846) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2577:2577:2577) (2632:2632:2632)) - (PORT clk (1846:1846:1846) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (PORT d[0] (4055:4055:4055) (3952:3952:3952)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1804:1804:1804) (1802:1802:1802)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2048:2048:2048) (2021:2021:2021)) - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4402:4402:4402) (4453:4453:4453)) - (PORT d[1] (4222:4222:4222) (4285:4285:4285)) - (PORT d[2] (4296:4296:4296) (4356:4356:4356)) - (PORT d[3] (4467:4467:4467) (4510:4510:4510)) - (PORT d[4] (4361:4361:4361) (4378:4378:4378)) - (PORT d[5] (4645:4645:4645) (4676:4676:4676)) - (PORT d[6] (4445:4445:4445) (4533:4533:4533)) - (PORT d[7] (4329:4329:4329) (4398:4398:4398)) - (PORT d[8] (4517:4517:4517) (4536:4536:4536)) - (PORT d[9] (4456:4456:4456) (4702:4702:4702)) - (PORT d[10] (4317:4317:4317) (4323:4323:4323)) - (PORT d[11] (4684:4684:4684) (4714:4714:4714)) - (PORT d[12] (4438:4438:4438) (4553:4553:4553)) - (PORT clk (1810:1810:1810) (1804:1804:1804)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1806:1806:1806) (1804:1804:1804)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1163:1163:1163) (1219:1219:1219)) - (PORT datab (947:947:947) (1002:1002:1002)) - (PORT datac (1385:1385:1385) (1418:1418:1418)) - (PORT datad (1436:1436:1436) (1475:1475:1475)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (711:711:711) (751:751:751)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datac (2427:2427:2427) (2603:2603:2603)) + (PORT datad (633:633:633) (684:684:684)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -42031,476 +45972,33 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~1) + (INSTANCE D\[4\]\~86) (DELAY (ABSOLUTE - (PORT dataa (1314:1314:1314) (1369:1369:1369)) - (PORT datab (951:951:951) (1008:1008:1008)) - (PORT datac (1440:1440:1440) (1502:1502:1502)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (592:592:592) (622:622:622)) + (PORT datab (2465:2465:2465) (2646:2646:2646)) + (PORT datac (928:928:928) (975:975:975)) + (PORT datad (597:597:597) (633:633:633)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~89) (DELAY (ABSOLUTE - (PORT d[0] (901:901:901) (939:939:939)) - (PORT clk (1851:1851:1851) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3349:3349:3349) (3527:3527:3527)) - (PORT d[1] (1734:1734:1734) (1904:1904:1904)) - (PORT d[2] (1993:1993:1993) (2068:2068:2068)) - (PORT d[3] (2163:2163:2163) (2257:2257:2257)) - (PORT d[4] (1834:1834:1834) (1918:1918:1918)) - (PORT d[5] (1363:1363:1363) (1460:1460:1460)) - (PORT d[6] (1449:1449:1449) (1474:1474:1474)) - (PORT d[7] (3354:3354:3354) (3503:3503:3503)) - (PORT d[8] (2447:2447:2447) (2653:2653:2653)) - (PORT d[9] (3517:3517:3517) (3682:3682:3682)) - (PORT d[10] (2917:2917:2917) (3102:3102:3102)) - (PORT d[11] (1485:1485:1485) (1553:1553:1553)) - (PORT d[12] (1460:1460:1460) (1502:1502:1502)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3345:3345:3345) (3355:3355:3355)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (1944:1944:1944) (1906:1906:1906)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1470:1470:1470) (1515:1515:1515)) - (PORT clk (1841:1841:1841) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3671:3671:3671) (3886:3886:3886)) - (PORT d[1] (1690:1690:1690) (1854:1854:1854)) - (PORT d[2] (3275:3275:3275) (3430:3430:3430)) - (PORT d[3] (2158:2158:2158) (2262:2262:2262)) - (PORT d[4] (2542:2542:2542) (2676:2676:2676)) - (PORT d[5] (1672:1672:1672) (1804:1804:1804)) - (PORT d[6] (1797:1797:1797) (1871:1871:1871)) - (PORT d[7] (1692:1692:1692) (1762:1762:1762)) - (PORT d[8] (3323:3323:3323) (3550:3550:3550)) - (PORT d[9] (2846:2846:2846) (2959:2959:2959)) - (PORT d[10] (3476:3476:3476) (3688:3688:3688)) - (PORT d[11] (1790:1790:1790) (1894:1894:1894)) - (PORT d[12] (1727:1727:1727) (1788:1788:1788)) - (PORT clk (1838:1838:1838) (1865:1865:1865)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1941:1941:1941) (1913:1913:1913)) - (PORT clk (1838:1838:1838) (1865:1865:1865)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1869:1869:1869)) - (PORT d[0] (2779:2779:2779) (2775:2775:2775)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1801:1801:1801) (1828:1828:1828)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (986:986:986) (991:991:991)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (987:987:987) (992:992:992)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (987:987:987) (992:992:992)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (987:987:987) (992:992:992)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1247:1247:1247) (1305:1305:1305)) - (PORT clk (1851:1851:1851) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3351:3351:3351) (3542:3542:3542)) - (PORT d[1] (1331:1331:1331) (1442:1442:1442)) - (PORT d[2] (1949:1949:1949) (2052:2052:2052)) - (PORT d[3] (1549:1549:1549) (1617:1617:1617)) - (PORT d[4] (1868:1868:1868) (1957:1957:1957)) - (PORT d[5] (1641:1641:1641) (1721:1721:1721)) - (PORT d[6] (1178:1178:1178) (1228:1228:1228)) - (PORT d[7] (1451:1451:1451) (1507:1507:1507)) - (PORT d[8] (2507:2507:2507) (2697:2697:2697)) - (PORT d[9] (3505:3505:3505) (3649:3649:3649)) - (PORT d[10] (2878:2878:2878) (3044:3044:3044)) - (PORT d[11] (1237:1237:1237) (1307:1307:1307)) - (PORT d[12] (1108:1108:1108) (1125:1125:1125)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2872:2872:2872) (2909:2909:2909)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (3248:3248:3248) (3325:3325:3325)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + (PORT dataa (1158:1158:1158) (1204:1204:1204)) + (PORT datab (1206:1206:1206) (1216:1216:1216)) + (PORT datac (3269:3269:3269) (3535:3535:3535)) + (PORT datad (596:596:596) (633:633:633)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -42509,8 +46007,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1750:1750:1750) (1835:1835:1835)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT d[0] (1025:1025:1025) (1033:1033:1033)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) ) ) (TIMINGCHECK @@ -42522,20 +46020,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3365:3365:3365) (3581:3581:3581)) - (PORT d[1] (1702:1702:1702) (1864:1864:1864)) - (PORT d[2] (2694:2694:2694) (2816:2816:2816)) - (PORT d[3] (2143:2143:2143) (2257:2257:2257)) - (PORT d[4] (2191:2191:2191) (2314:2314:2314)) - (PORT d[5] (2392:2392:2392) (2607:2607:2607)) - (PORT d[6] (2106:2106:2106) (2209:2209:2209)) - (PORT d[7] (2467:2467:2467) (2597:2597:2597)) - (PORT d[8] (3036:3036:3036) (3248:3248:3248)) - (PORT d[9] (2577:2577:2577) (2669:2669:2669)) - (PORT d[10] (3785:3785:3785) (4034:4034:4034)) - (PORT d[11] (1778:1778:1778) (1856:1856:1856)) - (PORT d[12] (2315:2315:2315) (2396:2396:2396)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) + (PORT d[0] (3329:3329:3329) (3586:3586:3586)) + (PORT d[1] (1573:1573:1573) (1649:1649:1649)) + (PORT d[2] (1037:1037:1037) (1080:1080:1080)) + (PORT d[3] (1599:1599:1599) (1696:1696:1696)) + (PORT d[4] (2959:2959:2959) (3149:3149:3149)) + (PORT d[5] (970:970:970) (999:999:999)) + (PORT d[6] (1576:1576:1576) (1694:1694:1694)) + (PORT d[7] (1281:1281:1281) (1303:1303:1303)) + (PORT d[8] (1219:1219:1219) (1280:1280:1280)) + (PORT d[9] (1098:1098:1098) (1184:1184:1184)) + (PORT d[10] (1037:1037:1037) (1112:1112:1112)) + (PORT d[11] (2217:2217:2217) (2342:2342:2342)) + (PORT d[12] (1083:1083:1083) (1173:1173:1173)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) (TIMINGCHECK @@ -42547,8 +46045,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2267:2267:2267) (2265:2265:2265)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) + (PORT d[0] (1196:1196:1196) (1145:1145:1145)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) (TIMINGCHECK @@ -42560,8 +46058,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (PORT d[0] (2685:2685:2685) (2695:2695:2695)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (2363:2363:2363) (2340:2340:2340)) ) ) ) @@ -42570,7 +46068,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -42580,7 +46078,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -42590,7 +46088,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -42600,7 +46098,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -42610,7 +46108,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1810:1810:1810) (1837:1837:1837)) + (PORT clk (1811:1811:1811) (1838:1838:1838)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -42624,7 +46122,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) + (PORT clk (996:996:996) (1001:1001:1001)) ) ) ) @@ -42633,7 +46131,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) + (PORT clk (997:997:997) (1002:1002:1002)) ) ) ) @@ -42642,7 +46140,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) + (PORT clk (997:997:997) (1002:1002:1002)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -42650,6 +46148,312 @@ (CELL (CELLTYPE "cycloneive_ram_pulse_generator") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1004:1004:1004) (1015:1015:1015)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3337:3337:3337) (3609:3609:3609)) + (PORT d[1] (1306:1306:1306) (1388:1388:1388)) + (PORT d[2] (1698:1698:1698) (1789:1789:1789)) + (PORT d[3] (1595:1595:1595) (1675:1675:1675)) + (PORT d[4] (2970:2970:2970) (3138:3138:3138)) + (PORT d[5] (1270:1270:1270) (1328:1328:1328)) + (PORT d[6] (1305:1305:1305) (1402:1402:1402)) + (PORT d[7] (1331:1331:1331) (1362:1362:1362)) + (PORT d[8] (1550:1550:1550) (1637:1637:1637)) + (PORT d[9] (1103:1103:1103) (1195:1195:1195)) + (PORT d[10] (1045:1045:1045) (1128:1128:1128)) + (PORT d[11] (2177:2177:2177) (2321:2321:2321)) + (PORT d[12] (1373:1373:1373) (1464:1464:1464)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1223:1223:1223) (1198:1198:1198)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2348:2348:2348) (2353:2353:2353)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (930:930:930) (956:956:956)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2672:2672:2672) (2905:2905:2905)) + (PORT d[1] (1536:1536:1536) (1605:1605:1605)) + (PORT d[2] (1356:1356:1356) (1434:1434:1434)) + (PORT d[3] (1321:1321:1321) (1406:1406:1406)) + (PORT d[4] (2655:2655:2655) (2825:2825:2825)) + (PORT d[5] (1588:1588:1588) (1655:1655:1655)) + (PORT d[6] (1518:1518:1518) (1625:1625:1625)) + (PORT d[7] (1580:1580:1580) (1612:1612:1612)) + (PORT d[8] (1535:1535:1535) (1634:1634:1634)) + (PORT d[9] (1648:1648:1648) (1754:1754:1754)) + (PORT d[10] (1343:1343:1343) (1445:1445:1445)) + (PORT d[11] (1880:1880:1880) (2005:2005:2005)) + (PORT d[12] (1391:1391:1391) (1503:1503:1503)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1260:1260:1260) (1255:1255:1255)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT d[0] (2386:2386:2386) (2419:2419:2419)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1001:1001:1001)) @@ -42659,46 +46463,826 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~2) + (INSTANCE D\[4\]\~93) (DELAY (ABSOLUTE - (PORT dataa (1829:1829:1829) (1854:1854:1854)) - (PORT datab (1177:1177:1177) (1181:1181:1181)) - (PORT datad (1696:1696:1696) (1748:1748:1748)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (904:904:904) (927:927:927)) + (PORT datab (1237:1237:1237) (1338:1338:1338)) + (PORT datad (912:912:912) (935:935:935)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~3) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (1465:1465:1465) (1535:1535:1535)) - (PORT datab (1484:1484:1484) (1501:1501:1501)) - (PORT datac (2124:2124:2124) (2189:2189:2189)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT d[0] (1378:1378:1378) (1455:1455:1455)) + (PORT clk (1845:1845:1845) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2978:2978:2978) (3192:3192:3192)) + (PORT d[1] (2894:2894:2894) (2985:2985:2985)) + (PORT d[2] (1003:1003:1003) (1051:1051:1051)) + (PORT d[3] (1298:1298:1298) (1337:1337:1337)) + (PORT d[4] (2072:2072:2072) (2172:2172:2172)) + (PORT d[5] (945:945:945) (991:991:991)) + (PORT d[6] (1183:1183:1183) (1217:1217:1217)) + (PORT d[7] (2655:2655:2655) (2814:2814:2814)) + (PORT d[8] (1565:1565:1565) (1650:1650:1650)) + (PORT d[9] (437:437:437) (473:473:473)) + (PORT d[10] (428:428:428) (460:460:460)) + (PORT d[11] (2780:2780:2780) (2977:2977:2977)) + (PORT d[12] (751:751:751) (792:792:792)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1248:1248:1248) (1217:1217:1217)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1873:1873:1873)) + (PORT d[0] (1747:1747:1747) (1726:1726:1726)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1805:1805:1805) (1832:1832:1832)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (990:990:990) (995:995:995)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~94) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (999:999:999)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1205:1205:1205) (1303:1303:1303)) + (PORT datad (1455:1455:1455) (1474:1474:1474)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~109) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (680:680:680) (777:777:777)) - (PORT datab (1164:1164:1164) (1255:1255:1255)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (173:173:173) (197:197:197)) + (PORT d[0] (1196:1196:1196) (1180:1180:1180)) + (PORT clk (1848:1848:1848) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3089:3089:3089) (3264:3264:3264)) + (PORT d[1] (2104:2104:2104) (2210:2210:2210)) + (PORT d[2] (1617:1617:1617) (1719:1719:1719)) + (PORT d[3] (1520:1520:1520) (1615:1615:1615)) + (PORT d[4] (2696:2696:2696) (2843:2843:2843)) + (PORT d[5] (1573:1573:1573) (1654:1654:1654)) + (PORT d[6] (1510:1510:1510) (1578:1578:1578)) + (PORT d[7] (1930:1930:1930) (1965:1965:1965)) + (PORT d[8] (3501:3501:3501) (3625:3625:3625)) + (PORT d[9] (1426:1426:1426) (1546:1546:1546)) + (PORT d[10] (1668:1668:1668) (1771:1771:1771)) + (PORT d[11] (1859:1859:1859) (1961:1961:1961)) + (PORT d[12] (1669:1669:1669) (1783:1783:1783)) + (PORT clk (1845:1845:1845) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1494:1494:1494) (1487:1487:1487)) + (PORT clk (1845:1845:1845) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (PORT d[0] (2934:2934:2934) (2899:2899:2899)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1801:1801:1801)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1828:1828:1828) (1871:1871:1871)) + (PORT clk (1813:1813:1813) (1807:1807:1807)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4466:4466:4466) (4538:4538:4538)) + (PORT d[1] (4377:4377:4377) (4452:4452:4452)) + (PORT d[2] (4406:4406:4406) (4485:4485:4485)) + (PORT d[3] (4268:4268:4268) (4360:4360:4360)) + (PORT d[4] (4331:4331:4331) (4392:4392:4392)) + (PORT d[5] (4400:4400:4400) (4521:4521:4521)) + (PORT d[6] (4441:4441:4441) (4502:4502:4502)) + (PORT d[7] (4358:4358:4358) (4460:4460:4460)) + (PORT d[8] (4443:4443:4443) (4575:4575:4575)) + (PORT d[9] (4525:4525:4525) (4647:4647:4647)) + (PORT d[10] (4496:4496:4496) (4633:4633:4633)) + (PORT d[11] (4458:4458:4458) (4561:4561:4561)) + (PORT d[12] (4363:4363:4363) (4422:4422:4422)) + (PORT clk (1809:1809:1809) (1803:1803:1803)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1813:1813:1813) (1807:1807:1807)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1805:1805:1805) (1803:1803:1803)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1223:1223:1223) (1232:1232:1232)) + (PORT clk (1849:1849:1849) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3089:3089:3089) (3264:3264:3264)) + (PORT d[1] (1541:1541:1541) (1607:1607:1607)) + (PORT d[2] (1629:1629:1629) (1719:1719:1719)) + (PORT d[3] (1525:1525:1525) (1604:1604:1604)) + (PORT d[4] (2654:2654:2654) (2816:2816:2816)) + (PORT d[5] (1569:1569:1569) (1645:1645:1645)) + (PORT d[6] (1544:1544:1544) (1658:1658:1658)) + (PORT d[7] (1663:1663:1663) (1702:1702:1702)) + (PORT d[8] (1535:1535:1535) (1635:1635:1635)) + (PORT d[9] (1398:1398:1398) (1514:1514:1514)) + (PORT d[10] (1375:1375:1375) (1487:1487:1487)) + (PORT d[11] (1846:1846:1846) (1959:1959:1959)) + (PORT d[12] (1391:1391:1391) (1504:1504:1504)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1426:1426:1426) (1391:1391:1391)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (PORT d[0] (2602:2602:2602) (2625:2625:2625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1804:1804:1804) (1802:1802:1802)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1838:1838:1838) (1888:1888:1888)) + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4461:4461:4461) (4563:4563:4563)) + (PORT d[1] (4338:4338:4338) (4416:4416:4416)) + (PORT d[2] (4451:4451:4451) (4534:4534:4534)) + (PORT d[3] (4291:4291:4291) (4385:4385:4385)) + (PORT d[4] (4329:4329:4329) (4390:4390:4390)) + (PORT d[5] (4364:4364:4364) (4463:4463:4463)) + (PORT d[6] (4404:4404:4404) (4467:4467:4467)) + (PORT d[7] (4337:4337:4337) (4441:4441:4441)) + (PORT d[8] (4412:4412:4412) (4536:4536:4536)) + (PORT d[9] (4443:4443:4443) (4552:4552:4552)) + (PORT d[10] (4533:4533:4533) (4643:4643:4643)) + (PORT d[11] (4480:4480:4480) (4587:4587:4587)) + (PORT d[12] (4342:4342:4342) (4404:4404:4404)) + (PORT clk (1810:1810:1810) (1804:1804:1804)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2135:2135:2135) (2270:2270:2270)) + (PORT d[1] (2360:2360:2360) (2503:2503:2503)) + (PORT d[2] (2439:2439:2439) (2591:2591:2591)) + (PORT d[3] (2316:2316:2316) (2447:2447:2447)) + (PORT d[4] (2038:2038:2038) (2142:2142:2142)) + (PORT d[5] (2419:2419:2419) (2559:2559:2559)) + (PORT d[6] (2470:2470:2470) (2638:2638:2638)) + (PORT d[7] (2535:2535:2535) (2601:2601:2601)) + (PORT d[8] (2536:2536:2536) (2603:2603:2603)) + (PORT d[9] (2337:2337:2337) (2521:2521:2521)) + (PORT d[10] (3019:3019:3019) (3165:3165:3165)) + (PORT d[11] (2078:2078:2078) (2172:2172:2172)) + (PORT d[12] (2284:2284:2284) (2462:2462:2462)) + (PORT clk (1860:1860:1860) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1886:1886:1886)) + (PORT d[0] (2624:2624:2624) (2721:2721:2721)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1849:1849:1849)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1012:1012:1012)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1009:1009:1009) (1013:1013:1013)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1009:1009:1009) (1013:1013:1013)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1009:1009:1009) (1013:1013:1013)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (1215:1215:1215) (1289:1289:1289)) + (PORT datab (720:720:720) (782:782:782)) + (PORT datac (933:933:933) (942:942:942)) + (PORT datad (1202:1202:1202) (1232:1232:1232)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2194:2194:2194) (2311:2311:2311)) + (PORT d[1] (2390:2390:2390) (2538:2538:2538)) + (PORT d[2] (2577:2577:2577) (2693:2693:2693)) + (PORT d[3] (3028:3028:3028) (3132:3132:3132)) + (PORT d[4] (1942:1942:1942) (2079:2079:2079)) + (PORT d[5] (3464:3464:3464) (3577:3577:3577)) + (PORT d[6] (2798:2798:2798) (2911:2911:2911)) + (PORT d[7] (3363:3363:3363) (3428:3428:3428)) + (PORT d[8] (2099:2099:2099) (2185:2185:2185)) + (PORT d[9] (3054:3054:3054) (3173:3173:3173)) + (PORT d[10] (2331:2331:2331) (2396:2396:2396)) + (PORT d[11] (2463:2463:2463) (2612:2612:2612)) + (PORT d[12] (3239:3239:3239) (3438:3438:3438)) + (PORT clk (1867:1867:1867) (1892:1892:1892)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1892:1892:1892)) + (PORT d[0] (2930:2930:2930) (2859:2859:2859)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1868:1868:1868) (1893:1893:1893)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1855:1855:1855)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1015:1015:1015) (1018:1018:1018)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1019:1019:1019)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1019:1019:1019)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1019:1019:1019)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~91) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (931:931:931)) + (PORT datab (1317:1317:1317) (1343:1343:1343)) + (PORT datac (180:180:180) (216:216:216)) + (PORT datad (1569:1569:1569) (1584:1584:1584)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -42706,32 +47290,64 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~97) + (INSTANCE D\[4\]\~92) (DELAY (ABSOLUTE - (PORT dataa (887:887:887) (916:916:916)) - (PORT datab (1551:1551:1551) (1605:1605:1605)) - (PORT datac (1462:1462:1462) (1538:1538:1538)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (975:975:975) (990:990:990)) + (PORT datab (721:721:721) (781:781:781)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (312:312:312) (330:330:330)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~98) + (INSTANCE D\[4\]\~125) (DELAY (ABSOLUTE - (PORT dataa (1168:1168:1168) (1244:1244:1244)) - (PORT datab (1665:1665:1665) (1708:1708:1708)) - (PORT datac (1463:1463:1463) (1538:1538:1538)) - (PORT datad (173:173:173) (198:198:198)) + (PORT dataa (2570:2570:2570) (2815:2815:2815)) + (PORT datab (1396:1396:1396) (1468:1468:1468)) + (PORT datac (570:570:570) (585:585:585)) + (PORT datad (318:318:318) (337:337:337)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~110) + (DELAY + (ABSOLUTE + (PORT dataa (916:916:916) (976:976:976)) + (PORT datab (920:920:920) (940:940:940)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (632:632:632) (657:657:657)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~111) + (DELAY + (ABSOLUTE + (PORT dataa (2246:2246:2246) (2318:2318:2318)) + (PORT datab (436:436:436) (473:473:473)) + (PORT datac (194:194:194) (228:228:228)) + (PORT datad (1262:1262:1262) (1331:1331:1331)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -42741,13 +47357,13 @@ (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) (DELAY (ABSOLUTE - (PORT dataa (970:970:970) (1037:1037:1037)) - (PORT datab (1506:1506:1506) (1524:1524:1524)) - (PORT datac (236:236:236) (289:289:289)) - (PORT datad (1153:1153:1153) (1165:1165:1165)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1678:1678:1678) (1784:1784:1784)) + (PORT datab (426:426:426) (465:465:465)) + (PORT datac (536:536:536) (545:545:545)) + (PORT datad (1131:1131:1131) (1161:1161:1161)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -42757,7 +47373,7 @@ (INSTANCE z80_\|data_pins_\|dout\[4\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT clk (1527:1527:1527) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) (PORT ena (841:841:841) (846:846:846)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -42773,11 +47389,11 @@ (INSTANCE z80_\|bus_control_\|db\[4\]\~18) (DELAY (ABSOLUTE - (PORT dataa (395:395:395) (471:471:471)) - (PORT datab (388:388:388) (422:422:422)) - (PORT datad (671:671:671) (693:693:693)) + (PORT dataa (264:264:264) (351:351:351)) + (PORT datab (420:420:420) (454:454:454)) + (PORT datad (386:386:386) (415:415:415)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -42787,13 +47403,13 @@ (INSTANCE z80_\|bus_control_\|db\[4\]\~19) (DELAY (ABSOLUTE - (PORT dataa (981:981:981) (1007:1007:1007)) - (PORT datab (922:922:922) (965:965:965)) - (PORT datac (888:888:888) (938:938:938)) - (PORT datad (898:898:898) (913:913:913)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1128:1128:1128) (1161:1161:1161)) + (PORT datab (335:335:335) (364:364:364)) + (PORT datac (525:525:525) (531:531:531)) + (PORT datad (218:218:218) (250:250:250)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -42803,244 +47419,10 @@ (INSTANCE z80_\|ir_\|opcode\[4\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1550:1550:1550)) - (PORT ena (1479:1479:1479) (1488:1488:1488)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~0) - (DELAY - (ABSOLUTE - (PORT datac (1440:1440:1440) (1546:1546:1546)) - (PORT datad (1464:1464:1464) (1552:1552:1552)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1381:1381:1381) (1434:1434:1434)) - (PORT datab (981:981:981) (1038:1038:1038)) - (PORT datac (1636:1636:1636) (1757:1757:1757)) - (PORT datad (1217:1217:1217) (1298:1298:1298)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1286:1286:1286) (1367:1367:1367)) - (PORT datab (1528:1528:1528) (1599:1599:1599)) - (PORT datac (821:821:821) (830:830:830)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~3) - (DELAY - (ABSOLUTE - (PORT datab (1536:1536:1536) (1647:1647:1647)) - (PORT datac (1349:1349:1349) (1441:1441:1441)) - (PORT datad (2442:2442:2442) (2633:2633:2633)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (915:915:915)) - (PORT datab (925:925:925) (953:953:953)) - (PORT datac (1717:1717:1717) (1764:1764:1764)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (455:455:455)) - (PORT datab (1184:1184:1184) (1238:1238:1238)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (360:360:360) (383:383:383)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~11) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (953:953:953)) - (PORT datab (618:618:618) (660:660:660)) - (PORT datac (888:888:888) (936:936:936)) - (PORT datad (892:892:892) (905:905:905)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~12) - (DELAY - (ABSOLUTE - (PORT dataa (2004:2004:2004) (2054:2054:2054)) - (PORT datab (1141:1141:1141) (1140:1140:1140)) - (PORT datac (850:850:850) (856:856:856)) - (PORT datad (641:641:641) (681:681:681)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~13) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (243:243:243)) - (PORT datab (596:596:596) (607:607:607)) - (PORT datac (532:532:532) (546:546:546)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1573:1573:1573) (1667:1667:1667)) - (PORT datab (881:881:881) (895:895:895)) - (PORT datac (1465:1465:1465) (1505:1505:1505)) - (PORT datad (1073:1073:1073) (1063:1063:1063)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~15) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (652:652:652)) - (PORT datab (877:877:877) (906:906:906)) - (PORT datac (864:864:864) (874:874:874)) - (PORT datad (1193:1193:1193) (1249:1249:1249)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (219:219:219) (289:289:289)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mwr) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|mwr_wr) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT asdata (567:567:567) (645:645:645)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (903:903:903) (914:914:914)) + (PORT clrn (1578:1578:1578) (1558:1558:1558)) + (PORT ena (1940:1940:1940) (1962:1962:1962)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -43052,683 +47434,200 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) + (INSTANCE z80_\|pla_decode_\|Equal32\~0) (DELAY (ABSOLUTE - (PORT dataa (870:870:870) (890:890:890)) - (PORT datab (351:351:351) (390:390:390)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT datac (1946:1946:1946) (2006:2006:2006)) + (PORT datad (2593:2593:2593) (2646:2646:2646)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~84) + (INSTANCE z80_\|pla_decode_\|Equal36\~0) (DELAY (ABSOLUTE - (PORT dataa (1754:1754:1754) (1854:1854:1854)) - (PORT datab (1594:1594:1594) (1729:1729:1729)) - (PORT datac (1191:1191:1191) (1256:1256:1256)) - (PORT datad (1224:1224:1224) (1308:1308:1308)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (890:890:890) (951:951:951)) + (PORT datab (684:684:684) (704:704:704)) + (PORT datac (2073:2073:2073) (2242:2242:2242)) + (PORT datad (1433:1433:1433) (1451:1451:1451)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (288:288:288)) + (PORT datab (911:911:911) (925:925:925)) + (PORT datac (1751:1751:1751) (1844:1844:1844)) + (PORT datad (635:635:635) (684:684:684)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (699:699:699)) + (PORT datab (388:388:388) (432:432:432)) + (PORT datac (1409:1409:1409) (1477:1477:1477)) + (PORT datad (351:351:351) (382:382:382)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2309:2309:2309) (2429:2429:2429)) + (PORT datab (1622:1622:1622) (1658:1658:1658)) + (PORT datac (1347:1347:1347) (1529:1529:1529)) + (PORT datad (1271:1271:1271) (1279:1279:1279)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) (DELAY (ABSOLUTE - (PORT d[0] (1170:1170:1170) (1220:1220:1220)) - (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT asdata (1203:1203:1203) (1245:1245:1245)) + (PORT clrn (1590:1590:1590) (1567:1567:1567)) + (PORT ena (993:993:993) (1000:1000:1000)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) (DELAY (ABSOLUTE - (PORT d[0] (4199:4199:4199) (4456:4456:4456)) - (PORT d[1] (2869:2869:2869) (3121:3121:3121)) - (PORT d[2] (3253:3253:3253) (3349:3349:3349)) - (PORT d[3] (2536:2536:2536) (2717:2717:2717)) - (PORT d[4] (2232:2232:2232) (2420:2420:2420)) - (PORT d[5] (2568:2568:2568) (2749:2749:2749)) - (PORT d[6] (1862:1862:1862) (1979:1979:1979)) - (PORT d[7] (2324:2324:2324) (2461:2461:2461)) - (PORT d[8] (3106:3106:3106) (3383:3383:3383)) - (PORT d[9] (2915:2915:2915) (3048:3048:3048)) - (PORT d[10] (4807:4807:4807) (5077:5077:5077)) - (PORT d[11] (2186:2186:2186) (2342:2342:2342)) - (PORT d[12] (2200:2200:2200) (2338:2338:2338)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1968:1968:1968) (1944:1944:1944)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1883:1883:1883)) - (PORT d[0] (2326:2326:2326) (2304:2304:2304)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1816:1816:1816) (1842:1842:1842)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1193:1193:1193) (1222:1222:1222)) - (PORT clk (1858:1858:1858) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4194:4194:4194) (4449:4449:4449)) - (PORT d[1] (2891:2891:2891) (3144:3144:3144)) - (PORT d[2] (2764:2764:2764) (2858:2858:2858)) - (PORT d[3] (2536:2536:2536) (2713:2713:2713)) - (PORT d[4] (2253:2253:2253) (2443:2443:2443)) - (PORT d[5] (2541:2541:2541) (2717:2717:2717)) - (PORT d[6] (1898:1898:1898) (2008:2008:2008)) - (PORT d[7] (2297:2297:2297) (2428:2428:2428)) - (PORT d[8] (3124:3124:3124) (3401:3401:3401)) - (PORT d[9] (2609:2609:2609) (2741:2741:2741)) - (PORT d[10] (4803:4803:4803) (5068:5068:5068)) - (PORT d[11] (1891:1891:1891) (2036:2036:2036)) - (PORT d[12] (2208:2208:2208) (2353:2353:2353)) - (PORT clk (1855:1855:1855) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2383:2383:2383) (2365:2365:2365)) - (PORT clk (1855:1855:1855) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (PORT d[0] (2857:2857:2857) (2839:2839:2839)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1843:1843:1843)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (880:880:880) (918:918:918)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1334:1334:1334) (1380:1380:1380)) - (PORT d[1] (2044:2044:2044) (2248:2248:2248)) - (PORT d[2] (3016:3016:3016) (3126:3126:3126)) - (PORT d[3] (2584:2584:2584) (2783:2783:2783)) - (PORT d[4] (2569:2569:2569) (2761:2761:2761)) - (PORT d[5] (2836:2836:2836) (3029:3029:3029)) - (PORT d[6] (1949:1949:1949) (2075:2075:2075)) - (PORT d[7] (2609:2609:2609) (2760:2760:2760)) - (PORT d[8] (3388:3388:3388) (3680:3680:3680)) - (PORT d[9] (2935:2935:2935) (3067:3067:3067)) - (PORT d[10] (5109:5109:5109) (5374:5374:5374)) - (PORT d[11] (1927:1927:1927) (2066:2066:2066)) - (PORT d[12] (1910:1910:1910) (2033:2033:2033)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1228:1228:1228) (1223:1223:1223)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1879:1879:1879)) - (PORT d[0] (2528:2528:2528) (2496:2496:2496)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + (PORT dataa (685:685:685) (746:746:746)) + (PORT datab (925:925:925) (959:959:959)) + (PORT datac (1056:1056:1056) (1099:1099:1099)) + (PORT datad (1179:1179:1179) (1228:1228:1228)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~6) + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) (DELAY (ABSOLUTE - (PORT dataa (1430:1430:1430) (1510:1510:1510)) - (PORT datab (977:977:977) (1037:1037:1037)) - (PORT datac (1084:1084:1084) (1106:1106:1106)) - (PORT datad (833:833:833) (863:863:863)) + (PORT dataa (846:846:846) (868:868:868)) + (PORT datab (1152:1152:1152) (1165:1165:1165)) + (PORT datac (1037:1037:1037) (1033:1033:1033)) + (PORT datad (823:823:823) (844:844:844)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_yf) (DELAY (ABSOLUTE - (PORT d[0] (1183:1183:1183) (1216:1216:1216)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~15) (DELAY (ABSOLUTE - (PORT d[0] (3355:3355:3355) (3572:3572:3572)) - (PORT d[1] (1697:1697:1697) (1865:1865:1865)) - (PORT d[2] (2991:2991:2991) (3133:3133:3133)) - (PORT d[3] (2197:2197:2197) (2290:2290:2290)) - (PORT d[4] (2502:2502:2502) (2653:2653:2653)) - (PORT d[5] (2405:2405:2405) (2601:2601:2601)) - (PORT d[6] (2102:2102:2102) (2200:2200:2200)) - (PORT d[7] (2478:2478:2478) (2588:2588:2588)) - (PORT d[8] (3018:3018:3018) (3244:3244:3244)) - (PORT d[9] (2534:2534:2534) (2624:2624:2624)) - (PORT d[10] (3776:3776:3776) (4011:4011:4011)) - (PORT d[11] (1726:1726:1726) (1804:1804:1804)) - (PORT d[12] (2323:2323:2323) (2409:2409:2409)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2206:2206:2206) (2199:2199:2199)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (PORT d[0] (2749:2749:2749) (2715:2715:2715)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1809:1809:1809) (1835:1835:1835)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + (PORT dataa (604:604:604) (648:648:648)) + (PORT datab (1173:1173:1173) (1220:1220:1220)) + (PORT datac (656:656:656) (717:717:717)) + (PORT datad (590:590:590) (621:621:621)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) + (INSTANCE z80_\|alu_control_\|db\[5\]\~16) (DELAY (ABSOLUTE - (PORT dataa (1449:1449:1449) (1499:1499:1499)) - (PORT datab (1154:1154:1154) (1180:1180:1180)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1425:1425:1425) (1425:1425:1425)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (843:843:843) (895:895:895)) + (PORT datab (619:619:619) (657:657:657)) + (PORT datac (1400:1400:1400) (1464:1464:1464)) + (PORT datad (616:616:616) (628:628:628)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (248:248:248)) + (PORT datab (1116:1116:1116) (1138:1138:1138)) + (PORT datac (843:843:843) (863:863:863)) + (PORT datad (202:202:202) (229:229:229)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1785:1785:1785) (1834:1834:1834)) + (PORT d[0] (1475:1475:1475) (1500:1500:1500)) (PORT clk (1844:1844:1844) (1873:1873:1873)) ) ) @@ -43738,22 +47637,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3330:3330:3330) (3510:3510:3510)) - (PORT d[1] (2345:2345:2345) (2548:2548:2548)) - (PORT d[2] (2224:2224:2224) (2307:2307:2307)) - (PORT d[3] (1895:1895:1895) (2026:2026:2026)) - (PORT d[4] (2445:2445:2445) (2553:2553:2553)) - (PORT d[5] (1968:1968:1968) (2118:2118:2118)) - (PORT d[6] (1422:1422:1422) (1463:1463:1463)) - (PORT d[7] (1469:1469:1469) (1501:1501:1501)) - (PORT d[8] (2903:2903:2903) (3100:3100:3100)) - (PORT d[9] (1984:1984:1984) (2114:2114:2114)) - (PORT d[10] (1991:1991:1991) (2095:2095:2095)) - (PORT d[11] (1441:1441:1441) (1479:1479:1479)) - (PORT d[12] (2020:2020:2020) (2065:2065:2065)) + (PORT d[0] (3077:3077:3077) (3235:3235:3235)) + (PORT d[1] (1841:1841:1841) (1953:1953:1953)) + (PORT d[2] (1661:1661:1661) (1762:1762:1762)) + (PORT d[3] (2157:2157:2157) (2296:2296:2296)) + (PORT d[4] (2379:2379:2379) (2508:2508:2508)) + (PORT d[5] (2076:2076:2076) (2143:2143:2143)) + (PORT d[6] (1866:1866:1866) (1988:1988:1988)) + (PORT d[7] (1974:1974:1974) (2008:2008:2008)) + (PORT d[8] (3446:3446:3446) (3559:3559:3559)) + (PORT d[9] (1737:1737:1737) (1876:1876:1876)) + (PORT d[10] (3876:3876:3876) (4076:4076:4076)) + (PORT d[11] (2655:2655:2655) (2799:2799:2799)) + (PORT d[12] (2471:2471:2471) (2621:2621:2621)) (PORT clk (1841:1841:1841) (1869:1869:1869)) ) ) @@ -43763,10 +47662,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2835:2835:2835) (2823:2823:2823)) + (PORT d[0] (2338:2338:2338) (2292:2292:2292)) (PORT clk (1841:1841:1841) (1869:1869:1869)) ) ) @@ -43776,17 +47675,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1844:1844:1844) (1873:1873:1873)) - (PORT d[0] (3960:3960:3960) (4062:4062:4062)) + (PORT d[0] (2885:2885:2885) (2929:2929:2929)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1845:1845:1845) (1874:1874:1874)) @@ -43796,7 +47695,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1845:1845:1845) (1874:1874:1874)) @@ -43806,7 +47705,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1845:1845:1845) (1874:1874:1874)) @@ -43816,7 +47715,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1845:1845:1845) (1874:1874:1874)) @@ -43826,7 +47725,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1799:1799:1799) (1798:1798:1798)) @@ -43840,10 +47739,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1198:1198:1198) (1181:1181:1181)) + (PORT d[0] (1821:1821:1821) (1865:1865:1865)) (PORT clk (1809:1809:1809) (1804:1804:1804)) ) ) @@ -43853,22 +47752,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4418:4418:4418) (4468:4468:4468)) - (PORT d[1] (4222:4222:4222) (4280:4280:4280)) - (PORT d[2] (4287:4287:4287) (4334:4334:4334)) - (PORT d[3] (4530:4530:4530) (4580:4580:4580)) - (PORT d[4] (4340:4340:4340) (4354:4354:4354)) - (PORT d[5] (4359:4359:4359) (4381:4381:4381)) - (PORT d[6] (4659:4659:4659) (4748:4748:4748)) - (PORT d[7] (4373:4373:4373) (4445:4445:4445)) - (PORT d[8] (4529:4529:4529) (4546:4546:4546)) - (PORT d[9] (4710:4710:4710) (4968:4968:4968)) - (PORT d[10] (4380:4380:4380) (4418:4418:4418)) - (PORT d[11] (4364:4364:4364) (4385:4385:4385)) - (PORT d[12] (4681:4681:4681) (4658:4658:4658)) + (PORT d[0] (4361:4361:4361) (4440:4440:4440)) + (PORT d[1] (4289:4289:4289) (4412:4412:4412)) + (PORT d[2] (4396:4396:4396) (4476:4476:4476)) + (PORT d[3] (4255:4255:4255) (4328:4328:4328)) + (PORT d[4] (4433:4433:4433) (4506:4506:4506)) + (PORT d[5] (4377:4377:4377) (4495:4495:4495)) + (PORT d[6] (4340:4340:4340) (4393:4393:4393)) + (PORT d[7] (4339:4339:4339) (4447:4447:4447)) + (PORT d[8] (4420:4420:4420) (4484:4484:4484)) + (PORT d[9] (4471:4471:4471) (4559:4559:4559)) + (PORT d[10] (4423:4423:4423) (4538:4538:4538)) + (PORT d[11] (4470:4470:4470) (4589:4589:4589)) + (PORT d[12] (4307:4307:4307) (4348:4348:4348)) (PORT clk (1805:1805:1805) (1800:1800:1800)) ) ) @@ -43878,7 +47777,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1809:1809:1809) (1804:1804:1804)) @@ -43887,7 +47786,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) (DELAY (ABSOLUTE (PORT clk (1810:1810:1810) (1805:1805:1805)) @@ -43897,7 +47796,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1810:1810:1810) (1805:1805:1805)) @@ -43906,7 +47805,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1810:1810:1810) (1805:1805:1805)) @@ -43916,7 +47815,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1810:1810:1810) (1805:1805:1805)) @@ -43926,23 +47825,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2604:2604:2604) (2682:2682:2682)) - (PORT d[1] (2063:2063:2063) (2283:2283:2283)) - (PORT d[2] (2289:2289:2289) (2441:2441:2441)) - (PORT d[3] (2285:2285:2285) (2377:2377:2377)) - (PORT d[4] (2950:2950:2950) (3220:3220:3220)) - (PORT d[5] (2075:2075:2075) (2260:2260:2260)) - (PORT d[6] (1854:1854:1854) (1963:1963:1963)) - (PORT d[7] (2555:2555:2555) (2658:2658:2658)) - (PORT d[8] (2752:2752:2752) (3006:3006:3006)) - (PORT d[9] (1553:1553:1553) (1673:1673:1673)) - (PORT d[10] (1845:1845:1845) (1962:1962:1962)) - (PORT d[11] (2882:2882:2882) (3002:3002:3002)) - (PORT d[12] (1537:1537:1537) (1640:1640:1640)) - (PORT clk (1867:1867:1867) (1892:1892:1892)) + (PORT d[0] (1663:1663:1663) (1779:1779:1779)) + (PORT d[1] (2732:2732:2732) (2838:2838:2838)) + (PORT d[2] (2573:2573:2573) (2708:2708:2708)) + (PORT d[3] (2470:2470:2470) (2584:2584:2584)) + (PORT d[4] (2444:2444:2444) (2531:2531:2531)) + (PORT d[5] (2902:2902:2902) (3012:3012:3012)) + (PORT d[6] (2795:2795:2795) (2926:2926:2926)) + (PORT d[7] (3199:3199:3199) (3295:3295:3295)) + (PORT d[8] (2328:2328:2328) (2401:2401:2401)) + (PORT d[9] (3071:3071:3071) (3209:3209:3209)) + (PORT d[10] (2336:2336:2336) (2406:2406:2406)) + (PORT d[11] (2497:2497:2497) (2660:2660:2660)) + (PORT d[12] (2947:2947:2947) (3126:3126:3126)) + (PORT clk (1869:1869:1869) (1894:1894:1894)) ) ) (TIMINGCHECK @@ -43951,30 +47850,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1867:1867:1867) (1892:1892:1892)) - (PORT d[0] (2184:2184:2184) (2245:2245:2245)) + (PORT clk (1869:1869:1869) (1894:1894:1894)) + (PORT d[0] (2872:2872:2872) (2960:2960:2960)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1868:1868:1868) (1893:1893:1893)) + (PORT clk (1870:1870:1870) (1895:1895:1895)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1830:1830:1830) (1855:1855:1855)) + (PORT clk (1832:1832:1832) (1857:1857:1857)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -43985,60 +47884,418 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1015:1015:1015) (1018:1018:1018)) + (PORT clk (1017:1017:1017) (1020:1020:1020)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1016:1016:1016) (1019:1019:1019)) + (PORT clk (1018:1018:1018) (1021:1021:1021)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1016:1016:1016) (1019:1019:1019)) + (PORT clk (1018:1018:1018) (1021:1021:1021)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1016:1016:1016) (1019:1019:1019)) + (PORT clk (1018:1018:1018) (1021:1021:1021)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3543:3543:3543) (3733:3733:3733)) - (PORT d[1] (1715:1715:1715) (1880:1880:1880)) - (PORT d[2] (2685:2685:2685) (2807:2807:2807)) - (PORT d[3] (2133:2133:2133) (2228:2228:2228)) - (PORT d[4] (1902:1902:1902) (2026:2026:2026)) - (PORT d[5] (2379:2379:2379) (2573:2573:2573)) - (PORT d[6] (2329:2329:2329) (2418:2418:2418)) - (PORT d[7] (2458:2458:2458) (2570:2570:2570)) - (PORT d[8] (2691:2691:2691) (2888:2888:2888)) - (PORT d[9] (2519:2519:2519) (2590:2590:2590)) - (PORT d[10] (3815:3815:3815) (4071:4071:4071)) - (PORT d[11] (1813:1813:1813) (1894:1894:1894)) - (PORT d[12] (2372:2372:2372) (2459:2459:2459)) + (PORT d[0] (1398:1398:1398) (1419:1419:1419)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1941:1941:1941) (2052:2052:2052)) + (PORT d[1] (3029:3029:3029) (3163:3163:3163)) + (PORT d[2] (1746:1746:1746) (1840:1840:1840)) + (PORT d[3] (3627:3627:3627) (3762:3762:3762)) + (PORT d[4] (2618:2618:2618) (2777:2777:2777)) + (PORT d[5] (4105:4105:4105) (4233:4233:4233)) + (PORT d[6] (2302:2302:2302) (2398:2398:2398)) + (PORT d[7] (3712:3712:3712) (3787:3787:3787)) + (PORT d[8] (1894:1894:1894) (1995:1995:1995)) + (PORT d[9] (2469:2469:2469) (2541:2541:2541)) + (PORT d[10] (2650:2650:2650) (2739:2739:2739)) + (PORT d[11] (2800:2800:2800) (3007:3007:3007)) + (PORT d[12] (4296:4296:4296) (4557:4557:4557)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3119:3119:3119) (3165:3165:3165)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (PORT d[0] (3232:3232:3232) (3186:3186:3186)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1808:1808:1808) (1806:1806:1806)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2181:2181:2181) (2164:2164:2164)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4392:4392:4392) (4469:4469:4469)) + (PORT d[1] (4472:4472:4472) (4532:4532:4532)) + (PORT d[2] (4387:4387:4387) (4471:4471:4471)) + (PORT d[3] (4388:4388:4388) (4400:4400:4400)) + (PORT d[4] (4258:4258:4258) (4352:4352:4352)) + (PORT d[5] (4349:4349:4349) (4405:4405:4405)) + (PORT d[6] (4400:4400:4400) (4441:4441:4441)) + (PORT d[7] (4176:4176:4176) (4227:4227:4227)) + (PORT d[8] (4465:4465:4465) (4525:4525:4525)) + (PORT d[9] (4604:4604:4604) (4650:4650:4650)) + (PORT d[10] (4270:4270:4270) (4329:4329:4329)) + (PORT d[11] (4396:4396:4396) (4516:4516:4516)) + (PORT d[12] (4242:4242:4242) (4248:4248:4248)) + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1808:1808:1808)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1707:1707:1707) (1838:1838:1838)) + (PORT d[1] (1389:1389:1389) (1409:1409:1409)) + (PORT d[2] (2239:2239:2239) (2416:2416:2416)) + (PORT d[3] (1717:1717:1717) (1771:1771:1771)) + (PORT d[4] (2431:2431:2431) (2579:2579:2579)) + (PORT d[5] (2815:2815:2815) (2865:2865:2865)) + (PORT d[6] (1980:1980:1980) (2073:2073:2073)) + (PORT d[7] (1698:1698:1698) (1754:1754:1754)) + (PORT d[8] (2198:2198:2198) (2300:2300:2300)) + (PORT d[9] (1738:1738:1738) (1793:1793:1793)) + (PORT d[10] (2522:2522:2522) (2606:2606:2606)) + (PORT d[11] (4027:4027:4027) (4320:4320:4320)) + (PORT d[12] (1372:1372:1372) (1411:1411:1411)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1877:1877:1877)) + (PORT d[0] (2104:2104:2104) (2139:2139:2139)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1840:1840:1840)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (999:999:999) (1003:1003:1003)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1215:1215:1215) (1290:1290:1290)) + (PORT datab (725:725:725) (787:787:787)) + (PORT datac (1356:1356:1356) (1394:1394:1394)) + (PORT datad (1654:1654:1654) (1694:1694:1694)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1212:1212:1212) (1241:1241:1241)) + (PORT datab (720:720:720) (781:781:781)) + (PORT datac (1876:1876:1876) (1912:1912:1912)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1300:1300:1300) (1346:1346:1346)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2285:2285:2285) (2467:2467:2467)) + (PORT d[1] (2246:2246:2246) (2325:2325:2325)) + (PORT d[2] (1845:1845:1845) (1951:1951:1951)) + (PORT d[3] (2514:2514:2514) (2600:2600:2600)) + (PORT d[4] (2048:2048:2048) (2130:2130:2130)) + (PORT d[5] (1563:1563:1563) (1637:1637:1637)) + (PORT d[6] (1751:1751:1751) (1801:1801:1801)) + (PORT d[7] (2365:2365:2365) (2488:2488:2488)) + (PORT d[8] (2486:2486:2486) (2660:2660:2660)) + (PORT d[9] (1246:1246:1246) (1313:1313:1313)) + (PORT d[10] (1642:1642:1642) (1713:1713:1713)) + (PORT d[11] (1161:1161:1161) (1207:1207:1207)) + (PORT d[12] (1023:1023:1023) (1096:1096:1096)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -44048,27 +48305,70 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) (DELAY (ABSOLUTE + (PORT d[0] (1539:1539:1539) (1561:1561:1561)) (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (2529:2529:2529) (2434:2434:2434)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (2040:2040:2040) (2017:2017:2017)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1811:1811:1811) (1838:1838:1838)) @@ -44082,7 +48382,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1001:1001:1001)) @@ -44091,7 +48391,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1002:1002:1002)) @@ -44100,7 +48400,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1002:1002:1002)) @@ -44110,7 +48410,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1002:1002:1002)) @@ -44120,10 +48420,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1649:1649:1649) (1736:1736:1736)) + (PORT d[0] (1174:1174:1174) (1169:1169:1169)) (PORT clk (1860:1860:1860) (1888:1888:1888)) ) ) @@ -44133,22 +48433,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2915:2915:2915) (3030:3030:3030)) - (PORT d[1] (2366:2366:2366) (2611:2611:2611)) - (PORT d[2] (2597:2597:2597) (2777:2777:2777)) - (PORT d[3] (2017:2017:2017) (2075:2075:2075)) - (PORT d[4] (2919:2919:2919) (3173:3173:3173)) - (PORT d[5] (2370:2370:2370) (2578:2578:2578)) - (PORT d[6] (1866:1866:1866) (1962:1962:1962)) - (PORT d[7] (1642:1642:1642) (1751:1751:1751)) - (PORT d[8] (3027:3027:3027) (3282:3282:3282)) - (PORT d[9] (1219:1219:1219) (1304:1304:1304)) - (PORT d[10] (2155:2155:2155) (2296:2296:2296)) - (PORT d[11] (3694:3694:3694) (3833:3833:3833)) - (PORT d[12] (1894:1894:1894) (1995:1995:1995)) + (PORT d[0] (2884:2884:2884) (3084:3084:3084)) + (PORT d[1] (3296:3296:3296) (3485:3485:3485)) + (PORT d[2] (1967:1967:1967) (2035:2035:2035)) + (PORT d[3] (3971:3971:3971) (4151:4151:4151)) + (PORT d[4] (2885:2885:2885) (3085:3085:3085)) + (PORT d[5] (4454:4454:4454) (4597:4597:4597)) + (PORT d[6] (2220:2220:2220) (2291:2291:2291)) + (PORT d[7] (1721:1721:1721) (1766:1766:1766)) + (PORT d[8] (3141:3141:3141) (3324:3324:3324)) + (PORT d[9] (1847:1847:1847) (1916:1916:1916)) + (PORT d[10] (2061:2061:2061) (2130:2130:2130)) + (PORT d[11] (3118:3118:3118) (3322:3322:3322)) + (PORT d[12] (4307:4307:4307) (4577:4577:4577)) (PORT clk (1857:1857:1857) (1884:1884:1884)) ) ) @@ -44158,10 +48458,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2802:2802:2802) (2787:2787:2787)) + (PORT d[0] (1635:1635:1635) (1573:1573:1573)) (PORT clk (1857:1857:1857) (1884:1884:1884)) ) ) @@ -44171,17 +48471,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1860:1860:1860) (1888:1888:1888)) - (PORT d[0] (3138:3138:3138) (3102:3102:3102)) + (PORT d[0] (2528:2528:2528) (2508:2508:2508)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1861:1861:1861) (1889:1889:1889)) @@ -44191,7 +48491,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1861:1861:1861) (1889:1889:1889)) @@ -44201,7 +48501,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1861:1861:1861) (1889:1889:1889)) @@ -44211,7 +48511,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1861:1861:1861) (1889:1889:1889)) @@ -44221,2180 +48521,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1813:1813:1813)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2176:2176:2176) (2231:2231:2231)) - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4610:4610:4610) (4658:4658:4658)) - (PORT d[1] (4157:4157:4157) (4160:4160:4160)) - (PORT d[2] (4196:4196:4196) (4284:4284:4284)) - (PORT d[3] (4718:4718:4718) (4716:4716:4716)) - (PORT d[4] (4356:4356:4356) (4386:4386:4386)) - (PORT d[5] (4428:4428:4428) (4381:4381:4381)) - (PORT d[6] (4640:4640:4640) (4703:4703:4703)) - (PORT d[7] (4181:4181:4181) (4140:4140:4140)) - (PORT d[8] (4708:4708:4708) (4720:4720:4720)) - (PORT d[9] (4594:4594:4594) (4806:4806:4806)) - (PORT d[10] (4407:4407:4407) (4422:4422:4422)) - (PORT d[11] (4504:4504:4504) (4555:4555:4555)) - (PORT d[12] (4480:4480:4480) (4497:4497:4497)) - (PORT clk (1821:1821:1821) (1815:1815:1815)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1817:1817:1817) (1815:1815:1815)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1424:1424:1424) (1496:1496:1496)) - (PORT datab (973:973:973) (1052:1052:1052)) - (PORT datac (1431:1431:1431) (1467:1467:1467)) - (PORT datad (1389:1389:1389) (1443:1443:1443)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1500:1500:1500) (1615:1615:1615)) - (PORT datab (972:972:972) (1051:1051:1051)) - (PORT datac (1456:1456:1456) (1510:1510:1510)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~112) - (DELAY - (ABSOLUTE - (PORT dataa (1480:1480:1480) (1579:1579:1579)) - (PORT datab (1206:1206:1206) (1296:1296:1296)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~94) - (DELAY - (ABSOLUTE - (PORT dataa (1382:1382:1382) (1396:1396:1396)) - (PORT datab (885:885:885) (963:963:963)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1346:1346:1346) (1371:1371:1371)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~102) - (DELAY - (ABSOLUTE - (PORT datac (191:191:191) (224:224:224)) - (PORT datad (781:781:781) (792:792:792)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) - (DELAY - (ABSOLUTE - (PORT dataa (968:968:968) (1025:1025:1025)) - (PORT datab (229:229:229) (272:272:272)) - (PORT datac (239:239:239) (287:287:287)) - (PORT datad (858:858:858) (899:899:899)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (1164:1164:1164) (1192:1192:1192)) - (PORT datac (942:942:942) (1003:1003:1003)) - (PORT datad (367:367:367) (390:390:390)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (267:267:267) (355:355:355)) - (PORT datab (711:711:711) (731:731:731)) - (PORT datac (879:879:879) (883:883:883)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1535:1535:1535)) - (PORT asdata (546:546:546) (581:581:581)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1501:1501:1501) (1488:1488:1488)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~0) - (DELAY - (ABSOLUTE - (PORT dataa (711:711:711) (814:814:814)) - (PORT datab (1235:1235:1235) (1355:1355:1355)) - (PORT datac (985:985:985) (1064:1064:1064)) - (PORT datad (1322:1322:1322) (1437:1437:1437)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (690:690:690) (756:756:756)) - (PORT datab (994:994:994) (1104:1104:1104)) - (PORT datac (1148:1148:1148) (1191:1191:1191)) - (PORT datad (1194:1194:1194) (1254:1254:1254)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (717:717:717) (780:780:780)) - (PORT datab (376:376:376) (417:417:417)) - (PORT datac (1100:1100:1100) (1123:1123:1123)) - (PORT datad (1740:1740:1740) (1811:1811:1811)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (999:999:999) (1037:1037:1037)) - (PORT datab (1148:1148:1148) (1181:1181:1181)) - (PORT datac (1118:1118:1118) (1156:1156:1156)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1747:1747:1747) (1768:1768:1768)) - (PORT datab (1063:1063:1063) (1181:1181:1181)) - (PORT datac (1205:1205:1205) (1277:1277:1277)) - (PORT datad (1152:1152:1152) (1188:1188:1188)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1745:1745:1745) (1764:1764:1764)) - (PORT datab (372:372:372) (420:420:420)) - (PORT datac (1499:1499:1499) (1632:1632:1632)) - (PORT datad (1111:1111:1111) (1140:1140:1140)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (232:232:232) (279:279:279)) - (PORT datab (1037:1037:1037) (1088:1088:1088)) - (PORT datac (1095:1095:1095) (1134:1134:1134)) - (PORT datad (1073:1073:1073) (1110:1110:1110)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (880:880:880) (904:904:904)) - (PORT datab (1509:1509:1509) (1569:1569:1569)) - (PORT datac (829:829:829) (848:848:848)) - (PORT datad (860:860:860) (875:875:875)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~50) - (DELAY - (ABSOLUTE - (PORT datac (1078:1078:1078) (1174:1174:1174)) - (PORT datad (1031:1031:1031) (1116:1116:1116)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (403:403:403) (436:436:436)) - (PORT datab (968:968:968) (1056:1056:1056)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (280:280:280)) - (PORT datab (775:775:775) (874:874:874)) - (PORT datac (1366:1366:1366) (1453:1453:1453)) - (PORT datad (1546:1546:1546) (1637:1637:1637)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (379:379:379)) - (PORT datab (222:222:222) (260:260:260)) - (PORT datad (739:739:739) (824:824:824)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (2308:2308:2308) (2488:2488:2488)) - (PORT datab (241:241:241) (322:322:322)) - (PORT datac (574:574:574) (621:621:621)) - (PORT datad (1325:1325:1325) (1345:1345:1345)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~57) - (DELAY - (ABSOLUTE - (PORT datab (965:965:965) (1048:1048:1048)) - (PORT datad (728:728:728) (839:839:839)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (622:622:622) (672:672:672)) - (PORT datad (961:961:961) (1040:1040:1040)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (489:489:489) (568:568:568)) - (PORT datab (664:664:664) (740:740:740)) - (PORT datac (606:606:606) (671:671:671)) - (PORT datad (721:721:721) (799:799:799)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~131) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (538:538:538)) - (PORT datab (342:342:342) (377:377:377)) - (PORT datad (260:260:260) (338:338:338)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (908:908:908)) - (PORT datab (1091:1091:1091) (1095:1095:1095)) - (PORT datad (617:617:617) (636:636:636)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1224:1224:1224)) - (PORT datab (240:240:240) (321:321:321)) - (PORT datac (568:568:568) (626:626:626)) - (PORT datad (553:553:553) (572:572:572)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~53) - (DELAY - (ABSOLUTE - (PORT datac (1077:1077:1077) (1170:1170:1170)) - (PORT datad (1031:1031:1031) (1112:1112:1112)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (227:227:227) (285:285:285)) - (PORT datab (390:390:390) (410:410:410)) - (PORT datac (918:918:918) (988:988:988)) - (PORT datad (328:328:328) (348:348:348)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~56) - (DELAY - (ABSOLUTE - (PORT datab (969:969:969) (1059:1059:1059)) - (PORT datad (338:338:338) (357:357:357)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (406:406:406) (439:439:439)) - (PORT datab (969:969:969) (1059:1059:1059)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (330:330:330)) - (PORT datab (242:242:242) (324:324:324)) - (PORT datac (559:559:559) (587:587:587)) - (PORT datad (556:556:556) (572:572:572)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (963:963:963) (1040:1040:1040)) - (PORT datab (793:793:793) (911:911:911)) - (PORT datac (907:907:907) (1000:1000:1000)) - (PORT datad (764:764:764) (871:871:871)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (395:395:395)) - (PORT datab (737:737:737) (825:825:825)) - (PORT datad (589:589:589) (600:600:600)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (213:213:213) (262:262:262)) - (PORT datab (201:201:201) (241:241:241)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) - (DELAY - (ABSOLUTE - (PORT datac (244:244:244) (324:324:324)) - (PORT datad (831:831:831) (879:879:879)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (764:764:764)) - (PORT datab (349:349:349) (382:382:382)) - (PORT datac (658:658:658) (727:727:727)) - (PORT datad (638:638:638) (705:705:705)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (257:257:257)) - (PORT datab (471:471:471) (546:546:546)) - (PORT datac (352:352:352) (381:381:381)) - (PORT datad (197:197:197) (232:232:232)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (734:734:734) (824:824:824)) - (PORT datab (493:493:493) (577:577:577)) - (PORT datac (572:572:572) (608:608:608)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (747:747:747) (849:849:849)) - (PORT datab (773:773:773) (872:872:872)) - (PORT datad (959:959:959) (1036:1036:1036)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (370:370:370)) - (PORT datad (635:635:635) (675:675:675)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1664:1664:1664) (1689:1689:1689)) - (PORT datab (618:618:618) (678:678:678)) - (PORT datac (1058:1058:1058) (1128:1128:1128)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (634:634:634) (655:655:655)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (589:589:589) (603:603:603)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~104) - (DELAY - (ABSOLUTE - (PORT datab (1233:1233:1233) (1299:1299:1299)) - (PORT datac (655:655:655) (738:738:738)) - (PORT datad (1395:1395:1395) (1412:1412:1412)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (947:947:947) (974:974:974)) - (PORT clk (1850:1850:1850) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1333:1333:1333) (1379:1379:1379)) - (PORT d[1] (1965:1965:1965) (2168:2168:2168)) - (PORT d[2] (3064:3064:3064) (3182:3182:3182)) - (PORT d[3] (2837:2837:2837) (3038:3038:3038)) - (PORT d[4] (2548:2548:2548) (2738:2738:2738)) - (PORT d[5] (2841:2841:2841) (3039:3039:3039)) - (PORT d[6] (1923:1923:1923) (2045:2045:2045)) - (PORT d[7] (2590:2590:2590) (2742:2742:2742)) - (PORT d[8] (3415:3415:3415) (3712:3712:3712)) - (PORT d[9] (1607:1607:1607) (1686:1686:1686)) - (PORT d[10] (5088:5088:5088) (5355:5355:5355)) - (PORT d[11] (1909:1909:1909) (2057:2057:2057)) - (PORT d[12] (1909:1909:1909) (2032:2032:2032)) - (PORT clk (1847:1847:1847) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1221:1221:1221) (1217:1217:1217)) - (PORT clk (1847:1847:1847) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (PORT d[0] (2517:2517:2517) (2474:2474:2474)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1836:1836:1836)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1000:1000:1000)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1000:1000:1000)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (704:704:704) (727:727:727)) - (PORT clk (1858:1858:1858) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1274:1274:1274) (1301:1301:1301)) - (PORT d[1] (2099:2099:2099) (2330:2330:2330)) - (PORT d[2] (1248:1248:1248) (1286:1286:1286)) - (PORT d[3] (1307:1307:1307) (1357:1357:1357)) - (PORT d[4] (2610:2610:2610) (2833:2833:2833)) - (PORT d[5] (3471:3471:3471) (3676:3676:3676)) - (PORT d[6] (1323:1323:1323) (1420:1420:1420)) - (PORT d[7] (2887:2887:2887) (3061:3061:3061)) - (PORT d[8] (985:985:985) (1023:1023:1023)) - (PORT d[9] (1296:1296:1296) (1359:1359:1359)) - (PORT d[10] (1357:1357:1357) (1455:1455:1455)) - (PORT d[11] (2476:2476:2476) (2609:2609:2609)) - (PORT d[12] (1610:1610:1610) (1711:1711:1711)) - (PORT clk (1855:1855:1855) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (979:979:979) (953:953:953)) - (PORT clk (1855:1855:1855) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (PORT d[0] (1492:1492:1492) (1460:1460:1460)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1843:1843:1843)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (947:947:947) (973:973:973)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1343:1343:1343) (1413:1413:1413)) - (PORT d[1] (3163:3163:3163) (3436:3436:3436)) - (PORT d[2] (3532:3532:3532) (3625:3625:3625)) - (PORT d[3] (2837:2837:2837) (3043:3043:3043)) - (PORT d[4] (2558:2558:2558) (2781:2781:2781)) - (PORT d[5] (2869:2869:2869) (3072:3072:3072)) - (PORT d[6] (1676:1676:1676) (1759:1759:1759)) - (PORT d[7] (1505:1505:1505) (1586:1586:1586)) - (PORT d[8] (3442:3442:3442) (3720:3720:3720)) - (PORT d[9] (3231:3231:3231) (3382:3382:3382)) - (PORT d[10] (5089:5089:5089) (5374:5374:5374)) - (PORT d[11] (1942:1942:1942) (2100:2100:2100)) - (PORT d[12] (1901:1901:1901) (2017:2017:2017)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1717:1717:1717) (1648:1648:1648)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1879:1879:1879)) - (PORT d[0] (2052:2052:2052) (2017:2017:2017)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1152:1152:1152) (1168:1168:1168)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3672:3672:3672) (3852:3852:3852)) - (PORT d[1] (1686:1686:1686) (1851:1851:1851)) - (PORT d[2] (1971:1971:1971) (2046:2046:2046)) - (PORT d[3] (2163:2163:2163) (2263:2263:2263)) - (PORT d[4] (2177:2177:2177) (2306:2306:2306)) - (PORT d[5] (1373:1373:1373) (1485:1485:1485)) - (PORT d[6] (1492:1492:1492) (1541:1541:1541)) - (PORT d[7] (1731:1731:1731) (1802:1802:1802)) - (PORT d[8] (3606:3606:3606) (3855:3855:3855)) - (PORT d[9] (3144:3144:3144) (3281:3281:3281)) - (PORT d[10] (3176:3176:3176) (3363:3363:3363)) - (PORT d[11] (2072:2072:2072) (2195:2195:2195)) - (PORT d[12] (1417:1417:1417) (1455:1455:1455)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1662:1662:1662) (1645:1645:1645)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (PORT d[0] (2686:2686:2686) (2681:2681:2681)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1809:1809:1809) (1835:1835:1835)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (980:980:980) (1035:1035:1035)) - (PORT datab (1190:1190:1190) (1238:1238:1238)) - (PORT datac (820:820:820) (836:836:836)) - (PORT datad (1047:1047:1047) (1047:1047:1047)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1175:1175:1175) (1168:1168:1168)) - (PORT datab (1602:1602:1602) (1692:1692:1692)) - (PORT datac (1163:1163:1163) (1158:1158:1158)) - (PORT datad (312:312:312) (328:328:328)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3036:3036:3036) (3209:3209:3209)) - (PORT d[1] (2901:2901:2901) (3127:3127:3127)) - (PORT d[2] (1663:1663:1663) (1761:1761:1761)) - (PORT d[3] (1512:1512:1512) (1583:1583:1583)) - (PORT d[4] (1858:1858:1858) (1967:1967:1967)) - (PORT d[5] (1341:1341:1341) (1451:1451:1451)) - (PORT d[6] (1141:1141:1141) (1162:1162:1162)) - (PORT d[7] (1474:1474:1474) (1532:1532:1532)) - (PORT d[8] (2472:2472:2472) (2678:2678:2678)) - (PORT d[9] (3827:3827:3827) (3998:3998:3998)) - (PORT d[10] (2576:2576:2576) (2725:2725:2725)) - (PORT d[11] (1801:1801:1801) (1882:1882:1882)) - (PORT d[12] (2041:2041:2041) (2064:2064:2064)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1875:1875:1875)) - (PORT d[0] (1267:1267:1267) (1274:1274:1274)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1634:1634:1634) (1680:1680:1680)) - (PORT clk (1866:1866:1866) (1893:1893:1893)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2598:2598:2598) (2696:2696:2696)) - (PORT d[1] (2070:2070:2070) (2298:2298:2298)) - (PORT d[2] (2574:2574:2574) (2730:2730:2730)) - (PORT d[3] (2266:2266:2266) (2351:2351:2351)) - (PORT d[4] (2949:2949:2949) (3214:3214:3214)) - (PORT d[5] (2088:2088:2088) (2293:2293:2293)) - (PORT d[6] (1571:1571:1571) (1677:1677:1677)) - (PORT d[7] (2825:2825:2825) (2918:2918:2918)) - (PORT d[8] (2797:2797:2797) (3045:3045:3045)) - (PORT d[9] (2076:2076:2076) (2185:2185:2185)) - (PORT d[10] (1851:1851:1851) (1973:1973:1973)) - (PORT d[11] (3686:3686:3686) (3803:3803:3803)) - (PORT d[12] (1884:1884:1884) (1967:1967:1967)) - (PORT clk (1863:1863:1863) (1889:1889:1889)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3175:3175:3175) (3145:3145:3145)) - (PORT clk (1863:1863:1863) (1889:1889:1889)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1866:1866:1866) (1893:1893:1893)) - (PORT d[0] (2870:2870:2870) (2913:2913:2913)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1818:1818:1818)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2160:2160:2160) (2219:2219:2219)) - (PORT clk (1831:1831:1831) (1824:1824:1824)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4537:4537:4537) (4504:4504:4504)) - (PORT d[1] (4325:4325:4325) (4356:4356:4356)) - (PORT d[2] (4543:4543:4543) (4609:4609:4609)) - (PORT d[3] (4478:4478:4478) (4499:4499:4499)) - (PORT d[4] (4324:4324:4324) (4305:4305:4305)) - (PORT d[5] (4367:4367:4367) (4410:4410:4410)) - (PORT d[6] (4631:4631:4631) (4697:4697:4697)) - (PORT d[7] (4151:4151:4151) (4116:4116:4116)) - (PORT d[8] (4445:4445:4445) (4476:4476:4476)) - (PORT d[9] (4629:4629:4629) (4823:4823:4823)) - (PORT d[10] (4475:4475:4475) (4482:4482:4482)) - (PORT d[11] (4668:4668:4668) (4671:4671:4671)) - (PORT d[12] (4491:4491:4491) (4515:4515:4515)) - (PORT clk (1827:1827:1827) (1820:1820:1820)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1831:1831:1831) (1824:1824:1824)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1345:1345:1345) (1398:1398:1398)) - (PORT datab (279:279:279) (367:367:367)) - (PORT datac (1350:1350:1350) (1376:1376:1376)) - (PORT datad (1465:1465:1465) (1526:1526:1526)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1584:1584:1584) (1645:1645:1645)) - (PORT clk (1870:1870:1870) (1897:1897:1897)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2320:2320:2320) (2387:2387:2387)) - (PORT d[1] (2054:2054:2054) (2261:2261:2261)) - (PORT d[2] (2320:2320:2320) (2490:2490:2490)) - (PORT d[3] (2275:2275:2275) (2437:2437:2437)) - (PORT d[4] (2932:2932:2932) (3188:3188:3188)) - (PORT d[5] (2382:2382:2382) (2576:2576:2576)) - (PORT d[6] (1862:1862:1862) (1984:1984:1984)) - (PORT d[7] (2524:2524:2524) (2619:2619:2619)) - (PORT d[8] (3132:3132:3132) (3396:3396:3396)) - (PORT d[9] (1782:1782:1782) (1897:1897:1897)) - (PORT d[10] (1810:1810:1810) (1908:1908:1908)) - (PORT d[11] (2927:2927:2927) (3048:3048:3048)) - (PORT d[12] (1876:1876:1876) (1989:1989:1989)) - (PORT clk (1867:1867:1867) (1893:1893:1893)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2203:2203:2203) (2195:2195:2195)) - (PORT clk (1867:1867:1867) (1893:1893:1893)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1897:1897:1897)) - (PORT d[0] (3171:3171:3171) (3110:3110:3110)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1822:1822:1822)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2476:2476:2476) (2528:2528:2528)) - (PORT clk (1835:1835:1835) (1828:1828:1828)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4504:4504:4504) (4508:4508:4508)) - (PORT d[1] (4109:4109:4109) (4118:4118:4118)) - (PORT d[2] (4505:4505:4505) (4547:4547:4547)) - (PORT d[3] (4566:4566:4566) (4624:4624:4624)) - (PORT d[4] (4563:4563:4563) (4541:4541:4541)) - (PORT d[5] (4668:4668:4668) (4705:4705:4705)) - (PORT d[6] (4650:4650:4650) (4703:4703:4703)) - (PORT d[7] (4197:4197:4197) (4161:4161:4161)) - (PORT d[8] (4693:4693:4693) (4743:4743:4743)) - (PORT d[9] (4535:4535:4535) (4748:4748:4748)) - (PORT d[10] (4537:4537:4537) (4522:4522:4522)) - (PORT d[11] (4499:4499:4499) (4551:4551:4551)) - (PORT d[12] (4595:4595:4595) (4623:4623:4623)) - (PORT clk (1831:1831:1831) (1824:1824:1824)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1828:1828:1828)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1827:1827:1827) (1824:1824:1824)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (987:987:987) (1035:1035:1035)) - (PORT d[1] (989:989:989) (1045:1045:1045)) - (PORT d[2] (1232:1232:1232) (1248:1248:1248)) - (PORT d[3] (1325:1325:1325) (1386:1386:1386)) - (PORT d[4] (2598:2598:2598) (2808:2808:2808)) - (PORT d[5] (2981:2981:2981) (3208:3208:3208)) - (PORT d[6] (983:983:983) (1027:1027:1027)) - (PORT d[7] (1279:1279:1279) (1356:1356:1356)) - (PORT d[8] (1032:1032:1032) (1055:1055:1055)) - (PORT d[9] (975:975:975) (1020:1020:1020)) - (PORT d[10] (1319:1319:1319) (1384:1384:1384)) - (PORT d[11] (2558:2558:2558) (2742:2742:2742)) - (PORT d[12] (1296:1296:1296) (1368:1368:1368)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (PORT d[0] (574:574:574) (581:581:581)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1820:1820:1820) (1847:1847:1847)) @@ -46408,7 +48535,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1005:1005:1005) (1010:1010:1010)) @@ -46417,7 +48544,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1011:1011:1011)) @@ -46426,7 +48553,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1011:1011:1011)) @@ -46436,7 +48563,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1011:1011:1011)) @@ -46445,63 +48572,353 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~41) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (1284:1284:1284) (1294:1294:1294)) - (PORT datab (865:865:865) (914:914:914)) - (PORT datac (861:861:861) (866:866:866)) - (PORT datad (181:181:181) (211:211:211)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT d[0] (1400:1400:1400) (1441:1441:1441)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2235:2235:2235) (2389:2389:2389)) + (PORT d[1] (1122:1122:1122) (1125:1125:1125)) + (PORT d[2] (2684:2684:2684) (2759:2759:2759)) + (PORT d[3] (4593:4593:4593) (4819:4819:4819)) + (PORT d[4] (965:965:965) (1020:1020:1020)) + (PORT d[5] (1653:1653:1653) (1677:1677:1677)) + (PORT d[6] (1443:1443:1443) (1505:1505:1505)) + (PORT d[7] (1417:1417:1417) (1425:1425:1425)) + (PORT d[8] (2517:2517:2517) (2647:2647:2647)) + (PORT d[9] (1142:1142:1142) (1167:1167:1167)) + (PORT d[10] (2053:2053:2053) (2116:2116:2116)) + (PORT d[11] (3735:3735:3735) (3999:3999:3999)) + (PORT d[12] (2464:2464:2464) (2535:2535:2535)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2814:2814:2814) (2818:2818:2818)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (1909:1909:1909) (1894:1894:1894)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1840:1840:1840)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (999:999:999) (1003:1003:1003)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (885:885:885)) + (PORT datab (1257:1257:1257) (1321:1321:1321)) + (PORT datac (1457:1457:1457) (1543:1543:1543)) + (PORT datad (1415:1415:1415) (1470:1470:1470)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~42) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (255:255:255)) - (PORT datab (282:282:282) (370:370:370)) - (PORT datac (1627:1627:1627) (1645:1645:1645)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT d[0] (1461:1461:1461) (1498:1498:1498)) + (PORT clk (1856:1856:1856) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1675:1675:1675) (1799:1799:1799)) + (PORT d[1] (2219:2219:2219) (2269:2269:2269)) + (PORT d[2] (2260:2260:2260) (2441:2441:2441)) + (PORT d[3] (1737:1737:1737) (1761:1761:1761)) + (PORT d[4] (2421:2421:2421) (2555:2555:2555)) + (PORT d[5] (2836:2836:2836) (2889:2889:2889)) + (PORT d[6] (2028:2028:2028) (2126:2126:2126)) + (PORT d[7] (1728:1728:1728) (1790:1790:1790)) + (PORT d[8] (2170:2170:2170) (2268:2268:2268)) + (PORT d[9] (1998:1998:1998) (2050:2050:2050)) + (PORT d[10] (2212:2212:2212) (2291:2291:2291)) + (PORT d[11] (4313:4313:4313) (4609:4609:4609)) + (PORT d[12] (2203:2203:2203) (2259:2259:2259)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1909:1909:1909) (1957:1957:1957)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT d[0] (1899:1899:1899) (1859:1859:1859)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1816:1816:1816) (1842:1842:1842)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1001:1001:1001) (1005:1005:1005)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~105) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~1) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (928:928:928) (981:981:981)) - (PORT datac (1193:1193:1193) (1255:1255:1255)) - (PORT datad (572:572:572) (583:583:583)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (410:410:410)) - (PORT datab (234:234:234) (278:278:278)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (183:183:183) (212:212:212)) + (PORT dataa (1194:1194:1194) (1262:1262:1262)) + (PORT datab (1708:1708:1708) (1802:1802:1802)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (1682:1682:1682) (1783:1783:1783)) (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~112) + (DELAY + (ABSOLUTE + (PORT dataa (1742:1742:1742) (1794:1794:1794)) + (PORT datab (667:667:667) (692:692:692)) + (PORT datac (628:628:628) (640:640:640)) + (PORT datad (319:319:319) (340:340:340)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -46510,44 +48927,44 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~46) + (INSTANCE D\[5\]\~113) (DELAY (ABSOLUTE - (PORT dataa (415:415:415) (501:501:501)) - (PORT datab (234:234:234) (278:278:278)) - (PORT datac (1139:1139:1139) (1183:1183:1183)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (2496:2496:2496) (2561:2561:2561)) + (PORT datab (700:700:700) (722:722:722)) + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (1174:1174:1174) (1248:1248:1248)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) (DELAY (ABSOLUTE - (PORT dataa (978:978:978) (1031:1031:1031)) - (PORT datab (648:648:648) (673:673:673)) - (PORT datac (597:597:597) (612:612:612)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (664:664:664) (690:690:690)) + (PORT datab (1158:1158:1158) (1194:1194:1194)) + (PORT datac (219:219:219) (257:257:257)) + (PORT datad (1559:1559:1559) (1584:1584:1584)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[2\]) + (INSTANCE z80_\|data_pins_\|dout\[5\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1530:1530:1530)) + (PORT clk (1527:1527:1527) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1245:1245:1245) (1226:1226:1226)) + (PORT ena (841:841:841) (846:846:846)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -46558,43 +48975,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~12) + (INSTANCE z80_\|bus_control_\|db\[5\]\~14) (DELAY (ABSOLUTE - (PORT datab (920:920:920) (962:962:962)) - (PORT datac (944:944:944) (990:990:990)) - (PORT datad (218:218:218) (253:253:253)) + (PORT datab (431:431:431) (490:490:490)) + (PORT datac (218:218:218) (263:263:263)) + (PORT datad (227:227:227) (264:264:264)) (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~13) + (INSTANCE z80_\|bus_control_\|db\[5\]\~15) (DELAY (ABSOLUTE - (PORT dataa (439:439:439) (507:507:507)) - (PORT datab (236:236:236) (280:280:280)) - (PORT datac (225:225:225) (274:274:274)) - (PORT datad (173:173:173) (199:199:199)) + (PORT dataa (873:873:873) (882:882:882)) + (PORT datab (592:592:592) (613:613:613)) + (PORT datac (532:532:532) (547:547:547)) + (PORT datad (1104:1104:1104) (1122:1122:1122)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[2\]) + (INSTANCE z80_\|ir_\|opcode\[5\]) (DELAY (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1557:1557:1557)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) + (PORT clrn (1578:1578:1578) (1558:1558:1558)) + (PORT ena (1940:1940:1940) (1962:1962:1962)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -46606,27 +49023,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~1) + (INSTANCE z80_\|execute_\|ctl_mRead\~11) (DELAY (ABSOLUTE - (PORT datac (1460:1460:1460) (1533:1533:1533)) - (PORT datad (2264:2264:2264) (2327:2327:2327)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (944:944:944) (975:975:975)) - (PORT datab (940:940:940) (997:997:997)) - (PORT datac (1637:1637:1637) (1758:1758:1758)) - (PORT datad (1220:1220:1220) (1303:1303:1303)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (2126:2126:2126) (2295:2295:2295)) + (PORT datab (2009:2009:2009) (2098:2098:2098)) + (PORT datac (1374:1374:1374) (1481:1481:1481)) + (PORT datad (877:877:877) (904:904:904)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -46634,63 +49039,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~2) + (INSTANCE z80_\|execute_\|setM1\~46) (DELAY (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (198:198:198) (235:235:235)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~3) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (859:859:859)) - (PORT datab (2054:2054:2054) (2187:2187:2187)) - (PORT datac (1260:1260:1260) (1358:1358:1358)) - (PORT datad (1087:1087:1087) (1084:1084:1084)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (1669:1669:1669) (1678:1678:1678)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) - (DELAY - (ABSOLUTE - (PORT dataa (1217:1217:1217) (1308:1308:1308)) - (PORT datab (2052:2052:2052) (2184:2184:2184)) - (PORT datac (1270:1270:1270) (1384:1384:1384)) - (PORT datad (1880:1880:1880) (1934:1934:1934)) + (PORT dataa (1208:1208:1208) (1251:1251:1251)) + (PORT datab (660:660:660) (700:700:700)) + (PORT datac (1413:1413:1413) (1458:1458:1458)) + (PORT datad (334:334:334) (357:357:357)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -46699,29 +49054,183 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~40) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1587:1587:1587) (1563:1563:1563)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + (PORT datac (1029:1029:1029) (1089:1089:1089)) + (PORT datad (603:603:603) (614:614:614)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) + (INSTANCE z80_\|execute_\|nextM\~5) (DELAY (ABSOLUTE - (PORT datab (252:252:252) (337:337:337)) - (PORT datad (226:226:226) (299:299:299)) + (PORT dataa (220:220:220) (263:263:263)) + (PORT datab (1871:1871:1871) (1947:1947:1947)) + (PORT datac (195:195:195) (228:228:228)) + (PORT datad (1085:1085:1085) (1121:1121:1121)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1202:1202:1202) (1239:1239:1239)) + (PORT datab (230:230:230) (272:272:272)) + (PORT datac (611:611:611) (641:641:641)) + (PORT datad (596:596:596) (616:616:616)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1281:1281:1281) (1354:1354:1354)) + (PORT datab (757:757:757) (812:812:812)) + (PORT datac (1936:1936:1936) (1953:1953:1953)) + (PORT datad (827:827:827) (852:852:852)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~9) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (683:683:683)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (1472:1472:1472) (1542:1542:1542)) + (PORT datad (632:632:632) (697:697:697)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1686:1686:1686) (1728:1728:1728)) + (PORT datab (924:924:924) (949:949:949)) + (PORT datac (1405:1405:1405) (1437:1437:1437)) + (PORT datad (869:869:869) (884:884:884)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~8) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (692:692:692)) + (PORT datab (1323:1323:1323) (1377:1377:1377)) + (PORT datac (213:213:213) (245:245:245)) + (PORT datad (1699:1699:1699) (1713:1713:1713)) + (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~12) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (267:267:267)) + (PORT datab (658:658:658) (707:707:707)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~15) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (890:890:890)) + (PORT datab (2358:2358:2358) (2453:2453:2453)) + (PORT datac (1473:1473:1473) (1589:1589:1589)) + (PORT datad (1034:1034:1034) (1093:1093:1093)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~13) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (941:941:941)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~14) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (247:247:247)) + (PORT datab (588:588:588) (602:602:602)) + (PORT datac (587:587:587) (646:646:646)) + (PORT datad (1400:1400:1400) (1419:1419:1419)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|ena_M) + (DELAY + (ABSOLUTE + (PORT datac (679:679:679) (727:727:727)) + (PORT datad (889:889:889) (908:908:908)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -46731,10 +49240,10 @@ (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT clk (1525:1525:1525) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT ena (1243:1243:1243) (1234:1234:1234)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -46749,9 +49258,9 @@ (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) (DELAY (ABSOLUTE - (PORT dataa (267:267:267) (353:353:353)) - (PORT datac (1094:1094:1094) (1135:1135:1135)) - (PORT datad (1105:1105:1105) (1151:1151:1151)) + (PORT dataa (698:698:698) (774:774:774)) + (PORT datac (683:683:683) (724:724:724)) + (PORT datad (890:890:890) (904:904:904)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -46763,10 +49272,10 @@ (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT clk (1525:1525:1525) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT ena (1243:1243:1243) (1234:1234:1234)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -46778,40 +49287,692 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|x3) + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) (DELAY (ABSOLUTE - (PORT dataa (2393:2393:2393) (2551:2551:2551)) - (PORT datac (239:239:239) (317:317:317)) - (PORT datad (1364:1364:1364) (1506:1506:1506)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (266:266:266) (354:354:354)) + (PORT datac (685:685:685) (725:725:725)) + (PORT datad (891:891:891) (904:904:904)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) + (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) (DELAY (ABSOLUTE - (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT clk (1525:1525:1525) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1883:1883:1883) (1869:1869:1869)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT ena (1243:1243:1243) (1234:1234:1234)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT inclk[0] (1583:1583:1583) (1637:1637:1637)) + (PORT dataa (267:267:267) (355:355:355)) + (PORT datac (680:680:680) (727:727:727)) + (PORT datad (893:893:893) (910:910:910)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT ena (1243:1243:1243) (1234:1234:1234)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~9) + (DELAY + (ABSOLUTE + (PORT datac (695:695:695) (789:789:789)) + (PORT datad (2317:2317:2317) (2438:2438:2438)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1194:1194:1194) (1283:1283:1283)) + (PORT datab (1491:1491:1491) (1605:1605:1605)) + (PORT datac (1593:1593:1593) (1631:1631:1631)) + (PORT datad (953:953:953) (980:980:980)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~54) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1176:1176:1176)) + (PORT datab (662:662:662) (691:691:691)) + (PORT datac (1163:1163:1163) (1238:1238:1238)) + (PORT datad (898:898:898) (985:985:985)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~25) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (689:689:689)) + (PORT datab (1319:1319:1319) (1372:1372:1372)) + (PORT datac (624:624:624) (642:642:642)) + (PORT datad (866:866:866) (881:881:881)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1220:1220:1220) (1259:1259:1259)) + (PORT datab (974:974:974) (1000:1000:1000)) + (PORT datac (255:255:255) (313:313:313)) + (PORT datad (1134:1134:1134) (1181:1181:1181)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1200:1200:1200) (1254:1254:1254)) + (PORT datab (606:606:606) (649:649:649)) + (PORT datac (872:872:872) (901:901:901)) + (PORT datad (807:807:807) (862:862:862)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~22) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (1002:1002:1002)) + (PORT datab (1460:1460:1460) (1527:1527:1527)) + (PORT datac (2859:2859:2859) (2966:2966:2966)) + (PORT datad (229:229:229) (304:304:304)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~55) + (DELAY + (ABSOLUTE + (PORT dataa (1419:1419:1419) (1546:1546:1546)) + (PORT datab (1084:1084:1084) (1106:1106:1106)) + (PORT datac (1238:1238:1238) (1330:1330:1330)) + (PORT datad (2052:2052:2052) (2171:2171:2171)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1120:1120:1120) (1150:1150:1150)) + (PORT datab (384:384:384) (410:410:410)) + (PORT datac (820:820:820) (894:894:894)) + (PORT datad (1655:1655:1655) (1717:1717:1717)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~24) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (927:927:927) (989:989:989)) + (PORT datac (864:864:864) (890:890:890)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~28) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (570:570:570)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (611:611:611) (630:630:630)) + (PORT datad (875:875:875) (908:908:908)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1084:1084:1084) (1172:1172:1172)) + (PORT datab (1952:1952:1952) (2000:2000:2000)) + (PORT datac (939:939:939) (1020:1020:1020)) + (PORT datad (1208:1208:1208) (1249:1249:1249)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1722:1722:1722) (1767:1767:1767)) + (PORT datab (2033:2033:2033) (2073:2073:2073)) + (PORT datac (1628:1628:1628) (1671:1671:1671)) + (PORT datad (1597:1597:1597) (1619:1619:1619)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~29) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (886:886:886)) + (PORT datab (832:832:832) (896:896:896)) + (PORT datac (869:869:869) (939:939:939)) + (PORT datad (1271:1271:1271) (1354:1354:1354)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1178:1178:1178) (1190:1190:1190)) + (PORT datab (884:884:884) (932:932:932)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1296:1296:1296) (1353:1353:1353)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~32) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (942:942:942)) + (PORT datab (1536:1536:1536) (1590:1590:1590)) + (PORT datac (1141:1141:1141) (1163:1163:1163)) + (PORT datad (1571:1571:1571) (1615:1615:1615)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~34) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (883:883:883)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (845:845:845) (843:843:843)) + (PORT datad (1659:1659:1659) (1685:1685:1685)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~20) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (988:988:988)) + (PORT datab (261:261:261) (343:343:343)) + (PORT datac (1656:1656:1656) (1675:1675:1675)) + (PORT datad (928:928:928) (961:961:961)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1199:1199:1199) (1254:1254:1254)) + (PORT datab (1283:1283:1283) (1356:1356:1356)) + (PORT datac (899:899:899) (912:912:912)) + (PORT datad (812:812:812) (861:861:861)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~35) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~15) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (662:662:662)) + (PORT datab (1239:1239:1239) (1284:1284:1284)) + (PORT datac (1420:1420:1420) (1516:1516:1516)) + (PORT datad (610:610:610) (633:633:633)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~14) + (DELAY + (ABSOLUTE + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (607:607:607) (632:632:632)) + (PORT datad (1915:1915:1915) (1966:1966:1966)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1167:1167:1167) (1219:1219:1219)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1354:1354:1354) (1355:1355:1355)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1152:1152:1152) (1228:1228:1228)) + (PORT datab (1143:1143:1143) (1197:1197:1197)) + (PORT datac (1388:1388:1388) (1456:1456:1456)) + (PORT datad (1311:1311:1311) (1375:1375:1375)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1124:1124:1124) (1140:1140:1140)) + (PORT datab (1614:1614:1614) (1768:1768:1768)) + (PORT datac (1340:1340:1340) (1376:1376:1376)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (938:938:938)) + (PORT datab (1149:1149:1149) (1249:1249:1249)) + (PORT datac (666:666:666) (774:774:774)) + (PORT datad (876:876:876) (897:897:897)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~9) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (949:949:949)) + (PORT datac (1502:1502:1502) (1602:1602:1602)) + (PORT datad (838:838:838) (846:846:846)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~13) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (262:262:262)) + (PORT datab (1193:1193:1193) (1237:1237:1237)) + (PORT datac (1207:1207:1207) (1228:1228:1228)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~18) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (979:979:979)) + (PORT datab (685:685:685) (706:706:706)) + (PORT datac (179:179:179) (214:214:214)) + (PORT datad (1969:1969:1969) (2022:2022:2022)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~19) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (970:970:970)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1488:1488:1488) (1575:1575:1575)) + (PORT datad (633:633:633) (645:645:645)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1108:1108:1108) (1166:1166:1166)) + (PORT datab (1111:1111:1111) (1226:1226:1226)) + (PORT datac (565:565:565) (580:580:580)) + (PORT datad (818:818:818) (823:823:823)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~42) + (DELAY + (ABSOLUTE + (PORT dataa (1729:1729:1729) (1815:1815:1815)) + (PORT datab (1999:1999:1999) (2067:2067:2067)) + (PORT datac (939:939:939) (999:999:999)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1000:1000:1000) (1047:1047:1047)) + (PORT datab (1000:1000:1000) (1036:1036:1036)) + (PORT datac (170:170:170) (201:201:201)) + (PORT datad (937:937:937) (978:978:978)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1471:1471:1471) (1555:1555:1555)) + (PORT datab (1379:1379:1379) (1419:1419:1419)) + (PORT datac (1473:1473:1473) (1586:1586:1586)) + (PORT datad (591:591:591) (624:624:624)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~51) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (215:215:215) (260:260:260)) + (PORT datac (192:192:192) (226:226:226)) + (PORT datad (346:346:346) (362:362:362)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) + (DELAY + (ABSOLUTE + (PORT datab (266:266:266) (349:349:349)) + (PORT datac (680:680:680) (726:726:726)) + (PORT datad (894:894:894) (909:909:909)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|T6) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT ena (1243:1243:1243) (1234:1234:1234)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~52) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (915:915:915) (992:992:992)) + (PORT datac (1353:1353:1353) (1387:1387:1387)) + (PORT datad (360:360:360) (381:381:381)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~53) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (652:652:652)) + (PORT datab (1116:1116:1116) (1149:1149:1149)) + (PORT datac (905:905:905) (992:992:992)) + (PORT datad (546:546:546) (553:553:553)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) + (DELAY + (ABSOLUTE + (PORT datab (705:705:705) (765:765:765)) + (PORT datad (895:895:895) (911:911:911)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -46820,9 +49981,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M1_ff) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT clk (1525:1525:1525) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -46836,11 +49997,11 @@ (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (1130:1130:1130) (1176:1176:1176)) - (PORT datab (283:283:283) (372:372:372)) - (PORT datad (1106:1106:1106) (1160:1160:1160)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (PORT dataa (661:661:661) (724:724:724)) + (PORT datab (720:720:720) (764:764:764)) + (PORT datad (890:890:890) (904:904:904)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -46849,3104 +50010,29 @@ (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~3) - (DELAY - (ABSOLUTE - (PORT datac (1051:1051:1051) (1164:1164:1164)) - (PORT datad (2030:2030:2030) (2123:2123:2123)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1463:1463:1463) (1520:1520:1520)) - (PORT datab (853:853:853) (881:881:881)) - (PORT datac (791:791:791) (801:801:801)) - (PORT datad (672:672:672) (691:691:691)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~8) - (DELAY - (ABSOLUTE - (PORT dataa (996:996:996) (1076:1076:1076)) - (PORT datab (661:661:661) (685:685:685)) - (PORT datac (956:956:956) (1008:1008:1008)) - (PORT datad (2243:2243:2243) (2327:2327:2327)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~9) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (910:910:910)) - (PORT datab (847:847:847) (857:857:857)) - (PORT datac (945:945:945) (997:997:997)) - (PORT datad (402:402:402) (435:435:435)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~10) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (725:725:725)) - (PORT datab (334:334:334) (363:363:363)) - (PORT datac (1475:1475:1475) (1542:1542:1542)) - (PORT datad (2078:2078:2078) (2128:2128:2128)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~12) - (DELAY - (ABSOLUTE - (PORT dataa (402:402:402) (429:429:429)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~15) - (DELAY - (ABSOLUTE - (PORT dataa (2002:2002:2002) (2100:2100:2100)) - (PORT datab (880:880:880) (891:891:891)) - (PORT datac (1448:1448:1448) (1504:1504:1504)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~6) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (277:277:277)) - (PORT datab (236:236:236) (281:281:281)) - (PORT datac (354:354:354) (382:382:382)) - (PORT datad (1061:1061:1061) (1062:1062:1062)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~7) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (279:279:279)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (989:989:989) (1043:1043:1043)) - (PORT datad (780:780:780) (803:803:803)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~13) - (DELAY - (ABSOLUTE - (PORT datab (1104:1104:1104) (1138:1138:1138)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (316:316:316) (336:336:336)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~39) - (DELAY - (ABSOLUTE - (PORT datac (766:766:766) (771:771:771)) - (PORT datad (608:608:608) (623:623:623)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~5) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (252:252:252)) - (PORT datab (2053:2053:2053) (2084:2084:2084)) - (PORT datac (618:618:618) (675:675:675)) - (PORT datad (334:334:334) (341:341:341)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~14) - (DELAY - (ABSOLUTE - (PORT dataa (834:834:834) (843:843:843)) - (PORT datab (877:877:877) (909:909:909)) - (PORT datac (1022:1022:1022) (1035:1035:1035)) - (PORT datad (538:538:538) (551:551:551)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT datab (273:273:273) (358:358:358)) - (PORT datac (1093:1093:1093) (1130:1130:1130)) - (PORT datad (1107:1107:1107) (1155:1155:1155)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (1123:1123:1123) (1157:1157:1157)) - (PORT datac (246:246:246) (327:327:327)) - (PORT datad (1110:1110:1110) (1159:1159:1159)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) - (DELAY - (ABSOLUTE - (PORT datab (265:265:265) (348:348:348)) - (PORT datac (1077:1077:1077) (1114:1114:1114)) - (PORT datad (1111:1111:1111) (1161:1161:1161)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|T6) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~13) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (637:637:637)) - (PORT datab (872:872:872) (895:895:895)) - (PORT datac (589:589:589) (612:612:612)) - (PORT datad (914:914:914) (960:960:960)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1005:1005:1005) (1115:1115:1115)) - (PORT datab (1187:1187:1187) (1258:1258:1258)) - (PORT datac (655:655:655) (715:715:715)) - (PORT datad (1245:1245:1245) (1328:1328:1328)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~12) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (719:719:719)) - (PORT datab (1671:1671:1671) (1704:1704:1704)) - (PORT datac (864:864:864) (890:890:890)) - (PORT datad (857:857:857) (896:896:896)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~14) - (DELAY - (ABSOLUTE - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (631:631:631) (681:681:681)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~41) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (442:442:442)) - (PORT datac (1069:1069:1069) (1104:1104:1104)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~42) - (DELAY - (ABSOLUTE - (PORT dataa (937:937:937) (992:992:992)) - (PORT datab (1106:1106:1106) (1172:1172:1172)) - (PORT datac (411:411:411) (452:452:452)) - (PORT datad (2503:2503:2503) (2629:2629:2629)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~43) - (DELAY - (ABSOLUTE - (PORT dataa (2006:2006:2006) (2147:2147:2147)) - (PORT datab (771:771:771) (831:831:831)) - (PORT datac (960:960:960) (989:989:989)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~44) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (941:941:941)) - (PORT datab (355:355:355) (391:391:391)) - (PORT datac (202:202:202) (239:239:239)) - (PORT datad (759:759:759) (760:760:760)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~50) - (DELAY - (ABSOLUTE - (PORT dataa (377:377:377) (403:403:403)) - (PORT datab (1048:1048:1048) (1080:1080:1080)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (1303:1303:1303) (1325:1325:1325)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1188:1188:1188)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (200:200:200) (237:237:237)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~6) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (871:871:871)) - (PORT datab (1589:1589:1589) (1720:1720:1720)) - (PORT datac (636:636:636) (653:653:653)) - (PORT datad (1694:1694:1694) (1790:1790:1790)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~7) - (DELAY - (ABSOLUTE - (PORT datab (867:867:867) (913:913:913)) - (PORT datac (893:893:893) (946:946:946)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1439:1439:1439) (1482:1482:1482)) - (PORT datab (885:885:885) (895:895:895)) - (PORT datac (878:878:878) (926:926:926)) - (PORT datad (632:632:632) (642:642:642)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1493:1493:1493) (1600:1600:1600)) - (PORT datab (1951:1951:1951) (2023:2023:2023)) - (PORT datac (1350:1350:1350) (1424:1424:1424)) - (PORT datad (1111:1111:1111) (1134:1134:1134)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~10) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (1125:1125:1125) (1164:1164:1164)) - (PORT datac (514:514:514) (525:525:525)) - (PORT datad (639:639:639) (676:676:676)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~11) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1215:1215:1215) (1255:1255:1255)) - (PORT datac (1013:1013:1013) (1058:1058:1058)) - (PORT datad (342:342:342) (364:364:364)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~17) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (655:655:655)) - (PORT datab (1046:1046:1046) (1078:1078:1078)) - (PORT datac (2017:2017:2017) (2052:2052:2052)) - (PORT datad (621:621:621) (635:635:635)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~31) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (662:662:662)) - (PORT datab (914:914:914) (975:975:975)) - (PORT datac (1817:1817:1817) (1894:1894:1894)) - (PORT datad (898:898:898) (912:912:912)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~28) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (403:403:403)) - (PORT datab (1223:1223:1223) (1259:1259:1259)) - (PORT datac (1402:1402:1402) (1465:1465:1465)) - (PORT datad (856:856:856) (854:854:854)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~30) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (886:886:886)) - (PORT datab (916:916:916) (944:944:944)) - (PORT datac (906:906:906) (930:930:930)) - (PORT datad (843:843:843) (882:882:882)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~32) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (960:960:960)) - (PORT datab (360:360:360) (395:395:395)) - (PORT datac (859:859:859) (902:902:902)) - (PORT datad (1107:1107:1107) (1120:1120:1120)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~33) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (602:602:602)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (896:896:896) (935:935:935)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1215:1215:1215)) - (PORT datac (627:627:627) (650:650:650)) - (PORT datad (1592:1592:1592) (1700:1700:1700)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~26) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (906:906:906)) - (PORT datab (1566:1566:1566) (1611:1611:1611)) - (PORT datac (868:868:868) (891:891:891)) - (PORT datad (1122:1122:1122) (1151:1151:1151)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~24) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (723:723:723)) - (PORT datab (660:660:660) (684:684:684)) - (PORT datac (2018:2018:2018) (1985:1985:1985)) - (PORT datad (954:954:954) (1028:1028:1028)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~27) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (643:643:643) (693:693:693)) - (PORT datad (661:661:661) (727:727:727)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~22) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (949:949:949)) - (PORT datab (904:904:904) (924:924:924)) - (PORT datac (888:888:888) (932:932:932)) - (PORT datad (623:623:623) (628:628:628)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1744:1744:1744) (1869:1869:1869)) - (PORT datab (1550:1550:1550) (1688:1688:1688)) - (PORT datac (1209:1209:1209) (1285:1285:1285)) - (PORT datad (1505:1505:1505) (1539:1539:1539)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~53) - (DELAY - (ABSOLUTE - (PORT dataa (965:965:965) (1045:1045:1045)) - (PORT datab (936:936:936) (1009:1009:1009)) - (PORT datac (649:649:649) (669:669:669)) - (PORT datad (1286:1286:1286) (1339:1339:1339)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~23) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (240:240:240)) - (PORT datab (363:363:363) (396:396:396)) - (PORT datac (1524:1524:1524) (1571:1571:1571)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~18) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (412:412:412)) - (PORT datab (990:990:990) (1020:1020:1020)) - (PORT datac (1523:1523:1523) (1602:1602:1602)) - (PORT datad (193:193:193) (219:219:219)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~19) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (644:644:644)) - (PORT datab (693:693:693) (758:758:758)) - (PORT datac (646:646:646) (704:704:704)) - (PORT datad (1320:1320:1320) (1419:1419:1419)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~20) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (675:675:675)) - (PORT datab (1180:1180:1180) (1218:1218:1218)) - (PORT datac (868:868:868) (922:922:922)) - (PORT datad (604:604:604) (625:625:625)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~34) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (649:649:649)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (309:309:309) (334:334:334)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~52) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (312:312:312) (330:330:330)) - (PORT datad (970:970:970) (1032:1032:1032)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1167:1167:1167)) - (PORT datac (245:245:245) (326:326:326)) - (PORT datad (1111:1111:1111) (1159:1159:1159)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) - (DELAY - (ABSOLUTE - (PORT datac (984:984:984) (1073:1073:1073)) - (PORT datad (1348:1348:1348) (1490:1490:1490)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~0) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (497:497:497)) - (PORT datac (1177:1177:1177) (1261:1261:1261)) - (PORT datad (272:272:272) (353:353:353)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~1) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (697:697:697)) - (PORT datab (1593:1593:1593) (1628:1628:1628)) - (PORT datad (638:638:638) (679:679:679)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|in_halt) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1532:1532:1532)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1555:1555:1555)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (991:991:991) (1049:1049:1049)) - (PORT datab (1153:1153:1153) (1214:1214:1214)) - (PORT datac (671:671:671) (718:718:718)) - (PORT datad (624:624:624) (674:674:674)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1120:1120:1120) (1227:1227:1227)) - (PORT datab (994:994:994) (1058:1058:1058)) - (PORT datac (1165:1165:1165) (1211:1211:1211)) - (PORT datad (879:879:879) (933:933:933)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (401:401:401) (432:432:432)) - (PORT datab (689:689:689) (742:742:742)) - (PORT datac (882:882:882) (943:943:943)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) - (DELAY - (ABSOLUTE - (PORT datac (1080:1080:1080) (1100:1100:1100)) - (PORT datad (647:647:647) (663:663:663)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (954:954:954) (979:979:979)) - (PORT datac (638:638:638) (653:653:653)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (254:254:254) (309:309:309)) - (PORT datac (944:944:944) (985:985:985)) - (PORT datad (335:335:335) (356:356:356)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~93) - (DELAY - (ABSOLUTE - (PORT dataa (227:227:227) (285:285:285)) - (PORT datab (780:780:780) (881:881:881)) - (PORT datac (1368:1368:1368) (1458:1458:1458)) - (PORT datad (562:562:562) (568:568:568)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~94) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (659:659:659)) - (PORT datab (733:733:733) (831:831:831)) - (PORT datad (718:718:718) (812:812:812)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) - (DELAY - (ABSOLUTE - (PORT dataa (741:741:741) (849:849:849)) - (PORT datab (1176:1176:1176) (1266:1266:1266)) - (PORT datac (727:727:727) (821:821:821)) - (PORT datad (735:735:735) (837:837:837)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~98) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datab (208:208:208) (251:251:251)) - (PORT datad (184:184:184) (213:213:213)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (1136:1136:1136) (1168:1168:1168)) - (PORT datab (1145:1145:1145) (1215:1215:1215)) - (PORT datac (215:215:215) (292:292:292)) - (PORT datad (361:361:361) (417:417:417)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~99) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (873:873:873)) - (PORT datab (729:729:729) (817:817:817)) - (PORT datac (885:885:885) (954:954:954)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~100) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (378:378:378)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datad (735:735:735) (822:822:822)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (745:745:745) (850:850:850)) - (PORT datab (987:987:987) (1082:1082:1082)) - (PORT datad (938:938:938) (1011:1011:1011)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) - (DELAY - (ABSOLUTE - (PORT dataa (743:743:743) (852:852:852)) - (PORT datab (723:723:723) (826:826:826)) - (PORT datac (1146:1146:1146) (1231:1231:1231)) - (PORT datad (910:910:910) (977:977:977)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~133) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (704:704:704)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (728:728:728) (824:824:824)) - (PORT datad (731:731:731) (831:831:831)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~103) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datad (322:322:322) (345:345:345)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (622:622:622)) - (PORT datab (422:422:422) (485:485:485)) - (PORT datac (556:556:556) (585:585:585)) - (PORT datad (616:616:616) (671:671:671)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (816:816:816)) - (PORT datab (729:729:729) (827:827:827)) - (PORT datac (720:720:720) (822:822:822)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~105) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (245:245:245)) - (PORT datab (367:367:367) (395:395:395)) - (PORT datad (718:718:718) (814:814:814)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) - (DELAY - (ABSOLUTE - (PORT dataa (1414:1414:1414) (1548:1548:1548)) - (PORT datab (216:216:216) (261:261:261)) - (PORT datac (959:959:959) (1039:1039:1039)) - (PORT datad (204:204:204) (234:234:234)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (732:732:732) (817:817:817)) - (PORT datab (665:665:665) (745:745:745)) - (PORT datac (658:658:658) (727:727:727)) - (PORT datad (433:433:433) (505:505:505)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (279:279:279)) - (PORT datab (412:412:412) (492:492:492)) - (PORT datac (628:628:628) (701:701:701)) - (PORT datad (406:406:406) (471:471:471)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~134) - (DELAY - (ABSOLUTE - (PORT dataa (377:377:377) (399:399:399)) - (PORT datab (380:380:380) (403:403:403)) - (PORT datad (833:833:833) (879:879:879)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) - (DELAY - (ABSOLUTE - (PORT dataa (740:740:740) (824:824:824)) - (PORT datab (602:602:602) (630:630:630)) - (PORT datac (616:616:616) (675:675:675)) - (PORT datad (531:531:531) (537:537:537)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~135) - (DELAY - (ABSOLUTE - (PORT dataa (737:737:737) (827:827:827)) - (PORT datab (274:274:274) (360:360:360)) - (PORT datad (1094:1094:1094) (1148:1148:1148)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~108) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (245:245:245)) - (PORT datab (365:365:365) (407:407:407)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (330:330:330)) - (PORT datab (1198:1198:1198) (1264:1264:1264)) - (PORT datac (618:618:618) (676:676:676)) - (PORT datad (777:777:777) (790:790:790)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~112) - (DELAY - (ABSOLUTE - (PORT dataa (853:853:853) (877:877:877)) - (PORT datab (222:222:222) (269:269:269)) - (PORT datac (638:638:638) (702:702:702)) - (PORT datad (324:324:324) (344:344:344)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~113) - (DELAY - (ABSOLUTE - (PORT dataa (734:734:734) (817:817:817)) - (PORT datab (201:201:201) (241:241:241)) - (PORT datac (569:569:569) (605:605:605)) - (PORT datad (464:464:464) (535:535:535)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~114) - (DELAY - (ABSOLUTE - (PORT datab (562:562:562) (582:582:582)) - (PORT datad (867:867:867) (872:872:872)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1568:1568:1568) (1563:1563:1563)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~109) - (DELAY - (ABSOLUTE - (PORT dataa (740:740:740) (820:820:820)) - (PORT datab (654:654:654) (726:726:726)) - (PORT datac (638:638:638) (703:703:703)) - (PORT datad (802:802:802) (842:842:842)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (736:736:736) (822:822:822)) - (PORT datab (225:225:225) (273:273:273)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (638:638:638) (709:709:709)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~137) - (DELAY - (ABSOLUTE - (PORT dataa (734:734:734) (821:821:821)) - (PORT datab (334:334:334) (362:362:362)) - (PORT datad (340:340:340) (370:370:370)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~138) - (DELAY - (ABSOLUTE - (PORT dataa (1042:1042:1042) (1147:1147:1147)) - (PORT datab (671:671:671) (712:712:712)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~2) - (DELAY - (ABSOLUTE - (PORT datab (1402:1402:1402) (1455:1455:1455)) - (PORT datac (1615:1615:1615) (1701:1701:1701)) - (PORT datad (1189:1189:1189) (1294:1294:1294)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (277:277:277)) - (PORT datab (1199:1199:1199) (1232:1232:1232)) - (PORT datac (1173:1173:1173) (1255:1255:1255)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (1123:1123:1123) (1183:1183:1183)) - (PORT datab (3290:3290:3290) (3477:3477:3477)) - (PORT datac (1148:1148:1148) (1200:1200:1200)) - (PORT datad (561:561:561) (572:572:572)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1048:1048:1048) (1087:1087:1087)) - (PORT clk (1847:1847:1847) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3996:3996:3996) (4212:4212:4212)) - (PORT d[1] (1700:1700:1700) (1852:1852:1852)) - (PORT d[2] (1685:1685:1685) (1760:1760:1760)) - (PORT d[3] (1880:1880:1880) (1986:1986:1986)) - (PORT d[4] (2151:2151:2151) (2275:2275:2275)) - (PORT d[5] (1351:1351:1351) (1462:1462:1462)) - (PORT d[6] (1496:1496:1496) (1550:1550:1550)) - (PORT d[7] (3357:3357:3357) (3515:3515:3515)) - (PORT d[8] (3629:3629:3629) (3880:3880:3880)) - (PORT d[9] (1469:1469:1469) (1530:1530:1530)) - (PORT d[10] (3184:3184:3184) (3384:3384:3384)) - (PORT d[11] (2096:2096:2096) (2225:2225:2225)) - (PORT d[12] (1735:1735:1735) (1780:1780:1780)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2569:2569:2569) (2625:2625:2625)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1875:1875:1875)) - (PORT d[0] (2985:2985:2985) (3047:3047:3047)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1834:1834:1834)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (992:992:992) (997:997:997)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (672:672:672) (698:698:698)) - (PORT clk (1851:1851:1851) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3032:3032:3032) (3215:3215:3215)) - (PORT d[1] (1378:1378:1378) (1491:1491:1491)) - (PORT d[2] (2016:2016:2016) (2093:2093:2093)) - (PORT d[3] (2186:2186:2186) (2283:2283:2283)) - (PORT d[4] (1556:1556:1556) (1641:1641:1641)) - (PORT d[5] (1392:1392:1392) (1479:1479:1479)) - (PORT d[6] (1191:1191:1191) (1221:1221:1221)) - (PORT d[7] (3356:3356:3356) (3523:3523:3523)) - (PORT d[8] (2486:2486:2486) (2673:2673:2673)) - (PORT d[9] (3482:3482:3482) (3624:3624:3624)) - (PORT d[10] (2885:2885:2885) (3060:3060:3060)) - (PORT d[11] (1777:1777:1777) (1854:1854:1854)) - (PORT d[12] (1425:1425:1425) (1448:1448:1448)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1966:1966:1966) (1924:1924:1924)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (2989:2989:2989) (2983:2983:2983)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (988:988:988) (1034:1034:1034)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3012:3012:3012) (3174:3174:3174)) - (PORT d[1] (1364:1364:1364) (1477:1477:1477)) - (PORT d[2] (1640:1640:1640) (1735:1735:1735)) - (PORT d[3] (1512:1512:1512) (1577:1577:1577)) - (PORT d[4] (1911:1911:1911) (1988:1988:1988)) - (PORT d[5] (1627:1627:1627) (1743:1743:1743)) - (PORT d[6] (1358:1358:1358) (1370:1370:1370)) - (PORT d[7] (1444:1444:1444) (1493:1493:1493)) - (PORT d[8] (2152:2152:2152) (2337:2337:2337)) - (PORT d[9] (3818:3818:3818) (3964:3964:3964)) - (PORT d[10] (2602:2602:2602) (2756:2756:2756)) - (PORT d[11] (1824:1824:1824) (1907:1907:1907)) - (PORT d[12] (2034:2034:2034) (2077:2077:2077)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1660:1660:1660) (1642:1642:1642)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1879:1879:1879)) - (PORT d[0] (2201:2201:2201) (2225:2225:2225)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (653:653:653)) - (PORT datab (1345:1345:1345) (1422:1422:1422)) - (PORT datac (885:885:885) (921:921:921)) - (PORT datad (1162:1162:1162) (1219:1219:1219)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1287:1287:1287) (1355:1355:1355)) - (PORT clk (1847:1847:1847) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3658:3658:3658) (3886:3886:3886)) - (PORT d[1] (1696:1696:1696) (1864:1864:1864)) - (PORT d[2] (3022:3022:3022) (3145:3145:3145)) - (PORT d[3] (2178:2178:2178) (2273:2273:2273)) - (PORT d[4] (2261:2261:2261) (2381:2381:2381)) - (PORT d[5] (2406:2406:2406) (2602:2602:2602)) - (PORT d[6] (2067:2067:2067) (2147:2147:2147)) - (PORT d[7] (2761:2761:2761) (2873:2873:2873)) - (PORT d[8] (3032:3032:3032) (3240:3240:3240)) - (PORT d[9] (2561:2561:2561) (2657:2657:2657)) - (PORT d[10] (3754:3754:3754) (3977:3977:3977)) - (PORT d[11] (1812:1812:1812) (1889:1889:1889)) - (PORT d[12] (2036:2036:2036) (2121:2121:2121)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2791:2791:2791) (2784:2784:2784)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1875:1875:1875)) - (PORT d[0] (2736:2736:2736) (2702:2702:2702)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1834:1834:1834)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (992:992:992) (997:997:997)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (1203:1203:1203) (1271:1271:1271)) - (PORT datab (935:935:935) (963:963:963)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1431:1431:1431) (1479:1479:1479)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3642:3642:3642) (3806:3806:3806)) - (PORT d[1] (2601:2601:2601) (2824:2824:2824)) - (PORT d[2] (1657:1657:1657) (1747:1747:1747)) - (PORT d[3] (2161:2161:2161) (2264:2264:2264)) - (PORT d[4] (1866:1866:1866) (1940:1940:1940)) - (PORT d[5] (1348:1348:1348) (1465:1465:1465)) - (PORT d[6] (1148:1148:1148) (1176:1176:1176)) - (PORT d[7] (1458:1458:1458) (1492:1492:1492)) - (PORT d[8] (2173:2173:2173) (2360:2360:2360)) - (PORT d[9] (3841:3841:3841) (3989:3989:3989)) - (PORT d[10] (2571:2571:2571) (2714:2714:2714)) - (PORT d[11] (2100:2100:2100) (2188:2188:2188)) - (PORT d[12] (2024:2024:2024) (2056:2056:2056)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (3353:3353:3353) (3478:3478:3478)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1472:1472:1472) (1543:1543:1543)) - (PORT clk (1846:1846:1846) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3349:3349:3349) (3537:3537:3537)) - (PORT d[1] (2304:2304:2304) (2505:2505:2505)) - (PORT d[2] (2195:2195:2195) (2287:2287:2287)) - (PORT d[3] (1835:1835:1835) (1941:1941:1941)) - (PORT d[4] (2157:2157:2157) (2255:2255:2255)) - (PORT d[5] (1649:1649:1649) (1788:1788:1788)) - (PORT d[6] (1483:1483:1483) (1506:1506:1506)) - (PORT d[7] (1491:1491:1491) (1524:1524:1524)) - (PORT d[8] (2907:2907:2907) (3105:3105:3105)) - (PORT d[9] (2279:2279:2279) (2414:2414:2414)) - (PORT d[10] (2285:2285:2285) (2382:2382:2382)) - (PORT d[11] (2475:2475:2475) (2611:2611:2611)) - (PORT d[12] (1976:1976:1976) (2027:2027:2027)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2840:2840:2840) (2830:2830:2830)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (PORT d[0] (3982:3982:3982) (4087:4087:4087)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1801:1801:1801) (1800:1800:1800)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2301:2301:2301) (2290:2290:2290)) - (PORT clk (1811:1811:1811) (1806:1806:1806)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4340:4340:4340) (4420:4420:4420)) - (PORT d[1] (4239:4239:4239) (4282:4282:4282)) - (PORT d[2] (4257:4257:4257) (4315:4315:4315)) - (PORT d[3] (4538:4538:4538) (4588:4588:4588)) - (PORT d[4] (4287:4287:4287) (4306:4306:4306)) - (PORT d[5] (4351:4351:4351) (4371:4371:4371)) - (PORT d[6] (4481:4481:4481) (4572:4572:4572)) - (PORT d[7] (4342:4342:4342) (4398:4398:4398)) - (PORT d[8] (4597:4597:4597) (4592:4592:4592)) - (PORT d[9] (4469:4469:4469) (4739:4739:4739)) - (PORT d[10] (4352:4352:4352) (4394:4394:4394)) - (PORT d[11] (4350:4350:4350) (4370:4370:4370)) - (PORT d[12] (4626:4626:4626) (4608:4608:4608)) - (PORT clk (1807:1807:1807) (1802:1802:1802)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1806:1806:1806)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (886:886:886) (944:944:944)) - (PORT datab (1682:1682:1682) (1751:1751:1751)) - (PORT datac (910:910:910) (950:950:950)) - (PORT datad (1193:1193:1193) (1243:1243:1243)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3603:3603:3603) (3780:3780:3780)) - (PORT d[1] (2612:2612:2612) (2820:2820:2820)) - (PORT d[2] (1542:1542:1542) (1613:1613:1613)) - (PORT d[3] (2126:2126:2126) (2248:2248:2248)) - (PORT d[4] (2158:2158:2158) (2252:2252:2252)) - (PORT d[5] (1643:1643:1643) (1776:1776:1776)) - (PORT d[6] (1395:1395:1395) (1417:1417:1417)) - (PORT d[7] (1473:1473:1473) (1509:1509:1509)) - (PORT d[8] (2157:2157:2157) (2322:2322:2322)) - (PORT d[9] (2292:2292:2292) (2444:2444:2444)) - (PORT d[10] (2276:2276:2276) (2402:2402:2402)) - (PORT d[11] (2115:2115:2115) (2225:2225:2225)) - (PORT d[12] (2288:2288:2288) (2338:2338:2338)) - (PORT clk (1846:1846:1846) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1873:1873:1873)) - (PORT d[0] (3448:3448:3448) (3327:3327:3327)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1809:1809:1809) (1836:1836:1836)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (276:276:276)) - (PORT datab (906:906:906) (941:941:941)) - (PORT datac (1129:1129:1129) (1177:1177:1177)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1549:1549:1549) (1631:1631:1631)) - (PORT clk (1862:1862:1862) (1888:1888:1888)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2520:2520:2520) (2617:2617:2617)) - (PORT d[1] (1962:1962:1962) (2122:2122:2122)) - (PORT d[2] (1955:1955:1955) (2077:2077:2077)) - (PORT d[3] (1876:1876:1876) (2000:2000:2000)) - (PORT d[4] (2723:2723:2723) (2864:2864:2864)) - (PORT d[5] (2232:2232:2232) (2416:2416:2416)) - (PORT d[6] (2043:2043:2043) (2115:2115:2115)) - (PORT d[7] (2404:2404:2404) (2531:2531:2531)) - (PORT d[8] (2398:2398:2398) (2577:2577:2577)) - (PORT d[9] (1996:1996:1996) (2101:2101:2101)) - (PORT d[10] (1691:1691:1691) (1769:1769:1769)) - (PORT d[11] (2047:2047:2047) (2128:2128:2128)) - (PORT d[12] (2520:2520:2520) (2605:2605:2605)) - (PORT clk (1859:1859:1859) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2655:2655:2655) (2640:2640:2640)) - (PORT clk (1859:1859:1859) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1862:1862:1862) (1888:1888:1888)) - (PORT d[0] (3407:3407:3407) (3339:3339:3339)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1863:1863:1863) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1863:1863:1863) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1863:1863:1863) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1863:1863:1863) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1817:1817:1817) (1813:1813:1813)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2066:2066:2066) (2077:2077:2077)) - (PORT clk (1827:1827:1827) (1819:1819:1819)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4618:4618:4618) (4692:4692:4692)) - (PORT d[1] (4233:4233:4233) (4271:4271:4271)) - (PORT d[2] (4532:4532:4532) (4592:4592:4592)) - (PORT d[3] (4449:4449:4449) (4489:4489:4489)) - (PORT d[4] (4330:4330:4330) (4336:4336:4336)) - (PORT d[5] (4590:4590:4590) (4607:4607:4607)) - (PORT d[6] (4724:4724:4724) (4801:4801:4801)) - (PORT d[7] (4565:4565:4565) (4613:4613:4613)) - (PORT d[8] (4569:4569:4569) (4629:4629:4629)) - (PORT d[9] (4484:4484:4484) (4751:4751:4751)) - (PORT d[10] (4377:4377:4377) (4395:4395:4395)) - (PORT d[11] (4636:4636:4636) (4682:4682:4682)) - (PORT d[12] (4604:4604:4604) (4754:4754:4754)) - (PORT clk (1823:1823:1823) (1815:1815:1815)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1827:1827:1827) (1819:1819:1819)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1828:1828:1828) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1828:1828:1828) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1828:1828:1828) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1828:1828:1828) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1815:1815:1815)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (946:946:946)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (1482:1482:1482) (1521:1521:1521)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~108) - (DELAY - (ABSOLUTE - (PORT dataa (1613:1613:1613) (1669:1669:1669)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1616:1616:1616) (1701:1701:1701)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~95) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (257:257:257)) - (PORT datab (1399:1399:1399) (1458:1458:1458)) - (PORT datac (1325:1325:1325) (1390:1390:1390)) - (PORT datad (341:341:341) (359:359:359)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~96) - (DELAY - (ABSOLUTE - (PORT dataa (1628:1628:1628) (1657:1657:1657)) - (PORT datab (1397:1397:1397) (1455:1455:1455)) - (PORT datac (1102:1102:1102) (1179:1179:1179)) - (PORT datad (313:313:313) (331:331:331)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) - (DELAY - (ABSOLUTE - (PORT dataa (975:975:975) (1040:1040:1040)) - (PORT datab (1658:1658:1658) (1724:1724:1724)) - (PORT datac (239:239:239) (291:291:291)) - (PORT datad (875:875:875) (896:896:896)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (310:310:310)) - (PORT datab (660:660:660) (727:727:727)) - (PORT datad (213:213:213) (248:248:248)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (984:984:984) (1009:1009:1009)) - (PORT datab (906:906:906) (952:952:952)) - (PORT datac (884:884:884) (932:932:932)) - (PORT datad (924:924:924) (947:947:947)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[3\]) (DELAY (ABSOLUTE (PORT clk (1525:1525:1525) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1550:1550:1550)) - (PORT ena (1479:1479:1479) (1488:1488:1488)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~4) + (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) (DELAY (ABSOLUTE - (PORT dataa (1465:1465:1465) (1561:1561:1561)) - (PORT datab (1173:1173:1173) (1201:1201:1201)) - (PORT datac (1193:1193:1193) (1280:1280:1280)) - (PORT datad (1406:1406:1406) (1444:1444:1444)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (982:982:982) (1081:1081:1081)) + (PORT datac (1243:1243:1243) (1342:1342:1342)) + (PORT datad (957:957:957) (1051:1051:1051)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -49956,12 +50042,12 @@ (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) (DELAY (ABSOLUTE - (PORT dataa (894:894:894) (970:970:970)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datac (896:896:896) (900:900:900)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (1482:1482:1482) (1540:1540:1540)) + (PORT datad (1185:1185:1185) (1227:1227:1227)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -49970,9 +50056,9 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1391:1391:1391) (1424:1424:1424)) - (PORT datab (630:630:630) (671:671:671)) - (PORT datad (180:180:180) (209:209:209)) + (PORT dataa (1177:1177:1177) (1260:1260:1260)) + (PORT datab (837:837:837) (857:857:857)) + (PORT datad (173:173:173) (199:199:199)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -49984,11 +50070,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT clk (1529:1529:1529) (1534:1534:1534)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (580:580:580) (654:654:654)) - (PORT sload (1117:1117:1117) (1168:1168:1168)) - (PORT ena (811:811:811) (804:804:804)) + (PORT asdata (707:707:707) (769:769:769)) + (PORT sload (1432:1432:1432) (1514:1514:1514)) + (PORT ena (1459:1459:1459) (1480:1480:1480)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -50001,29 +50087,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~59) + (INSTANCE D\[0\]\~66) (DELAY (ABSOLUTE - (PORT dataa (884:884:884) (914:914:914)) - (PORT datab (1147:1147:1147) (1200:1200:1200)) - (PORT datac (179:179:179) (216:216:216)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT datab (902:902:902) (924:924:924)) + (PORT datac (872:872:872) (926:926:926)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~60) + (INSTANCE D\[0\]\~67) (DELAY (ABSOLUTE - (PORT dataa (948:948:948) (996:996:996)) - (PORT datab (642:642:642) (701:701:701)) - (PORT datac (1642:1642:1642) (1669:1669:1669)) - (PORT datad (329:329:329) (345:345:345)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (2781:2781:2781) (2888:2888:2888)) + (PORT datab (1476:1476:1476) (1559:1559:1559)) + (PORT datac (1480:1480:1480) (1521:1521:1521)) + (PORT datad (308:308:308) (323:323:323)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50031,13 +50117,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~61) + (INSTANCE D\[0\]\~121) (DELAY (ABSOLUTE - (PORT dataa (1445:1445:1445) (1468:1468:1468)) - (PORT datac (831:831:831) (845:845:845)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT dataa (2634:2634:2634) (2765:2765:2765)) + (PORT datab (1935:1935:1935) (2079:2079:2079)) + (PORT datac (2771:2771:2771) (3001:3001:3001)) + (PORT datad (2441:2441:2441) (2545:2545:2545)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~68) + (DELAY + (ABSOLUTE + (PORT datab (669:669:669) (709:709:709)) + (PORT datac (1085:1085:1085) (1132:1132:1132)) + (PORT datad (350:350:350) (367:367:367)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50045,13 +50147,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~62) + (INSTANCE D\[1\]\~69) (DELAY (ABSOLUTE - (PORT dataa (1402:1402:1402) (1476:1476:1476)) - (PORT datab (940:940:940) (1026:1026:1026)) - (PORT datac (962:962:962) (1081:1081:1081)) - (PORT datad (173:173:173) (198:198:198)) + (PORT dataa (2782:2782:2782) (2888:2888:2888)) + (PORT datab (949:949:949) (1041:1041:1041)) + (PORT datac (1479:1479:1479) (1520:1520:1520)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~70) + (DELAY + (ABSOLUTE + (PORT datab (1161:1161:1161) (1224:1224:1224)) + (PORT datac (844:844:844) (887:887:887)) + (PORT datad (326:326:326) (348:348:348)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (2196:2196:2196) (2279:2279:2279)) + (PORT datab (635:635:635) (666:666:666)) + (PORT datac (1696:1696:1696) (1794:1794:1794)) + (PORT datad (173:173:173) (199:199:199)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -50061,13 +50193,73 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~63) + (INSTANCE D\[3\]\~83) (DELAY (ABSOLUTE - (PORT dataa (365:365:365) (413:413:413)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT dataa (2780:2780:2780) (2885:2885:2885)) + (PORT datac (912:912:912) (1002:1002:1002)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (409:409:409)) + (PORT datab (946:946:946) (982:982:982)) + (PORT datac (332:332:332) (348:348:348)) + (PORT datad (334:334:334) (351:351:351)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~95) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (978:978:978)) + (PORT datab (917:917:917) (942:942:942)) + (PORT datac (181:181:181) (218:218:218)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~96) + (DELAY + (ABSOLUTE + (PORT dataa (1289:1289:1289) (1374:1374:1374)) + (PORT datab (436:436:436) (474:474:474)) + (PORT datac (2209:2209:2209) (2279:2279:2279)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~126) + (DELAY + (ABSOLUTE + (PORT dataa (1874:1874:1874) (1923:1923:1923)) + (PORT datab (3091:3091:3091) (3312:3312:3312)) + (PORT datac (627:627:627) (639:639:639)) + (PORT datad (321:321:321) (343:343:343)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50075,12 +50267,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~64) + (INSTANCE D\[5\]\~98) (DELAY (ABSOLUTE - (PORT dataa (414:414:414) (500:500:500)) - (PORT datab (233:233:233) (277:277:277)) - (PORT datac (1139:1139:1139) (1183:1183:1183)) + (PORT dataa (1201:1201:1201) (1291:1291:1291)) + (PORT datab (672:672:672) (697:697:697)) + (PORT datac (2459:2459:2459) (2525:2525:2525)) (PORT datad (174:174:174) (200:200:200)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (381:381:381) (380:380:380)) @@ -50091,72 +50283,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~75) + (INSTANCE D\[6\]\~105) (DELAY (ABSOLUTE - (PORT dataa (211:211:211) (260:260:260)) - (PORT datac (1325:1325:1325) (1392:1392:1392)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (1121:1121:1121) (1209:1209:1209)) - (PORT datab (1140:1140:1140) (1196:1196:1196)) - (PORT datac (1527:1527:1527) (1561:1561:1561)) - (PORT datad (328:328:328) (343:343:343)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (917:917:917)) - (PORT datab (1549:1549:1549) (1602:1602:1602)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (952:952:952) (1002:1002:1002)) - (PORT datab (1444:1444:1444) (1508:1508:1508)) - (PORT datac (1641:1641:1641) (1667:1667:1667)) - (PORT datad (330:330:330) (348:348:348)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~92) - (DELAY - (ABSOLUTE - (PORT datab (1379:1379:1379) (1383:1383:1383)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (180:180:180) (207:207:207)) + (PORT datab (873:873:873) (921:921:921)) + (PORT datac (364:364:364) (389:389:389)) + (PORT datad (349:349:349) (365:365:365)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -50165,15 +50297,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~93) + (INSTANCE D\[6\]\~106) (DELAY (ABSOLUTE - (PORT dataa (948:948:948) (1000:1000:1000)) - (PORT datab (894:894:894) (967:967:967)) - (PORT datac (1642:1642:1642) (1672:1672:1672)) + (PORT dataa (1214:1214:1214) (1328:1328:1328)) + (PORT datab (636:636:636) (664:664:664)) + (PORT datac (2169:2169:2169) (2244:2244:2244)) (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~128) + (DELAY + (ABSOLUTE + (PORT dataa (2802:2802:2802) (3046:3046:3046)) + (PORT datab (2034:2034:2034) (2097:2097:2097)) + (PORT datac (180:180:180) (219:219:219)) + (PORT datad (615:615:615) (641:641:641)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~107) + (DELAY + (ABSOLUTE + (PORT dataa (1207:1207:1207) (1304:1304:1304)) + (PORT datab (2479:2479:2479) (2586:2586:2586)) + (PORT datac (346:346:346) (370:370:370)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) + (DELAY + (ABSOLUTE + (PORT datab (249:249:249) (333:333:333)) + (PORT datac (857:857:857) (879:879:879)) + (PORT datad (230:230:230) (303:303:303)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50184,11 +50362,11 @@ (INSTANCE z80_\|nM1_int\~3) (DELAY (ABSOLUTE - (PORT datab (1365:1365:1365) (1505:1505:1505)) - (PORT datac (2335:2335:2335) (2467:2467:2467)) - (PORT datad (554:554:554) (564:564:564)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (706:706:706) (760:760:760)) + (PORT datac (668:668:668) (739:739:739)) + (PORT datad (617:617:617) (675:675:675)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50198,10 +50376,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_16) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) + (PORT clk (1525:1525:1525) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT ena (1243:1243:1243) (1234:1234:1234)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50216,7 +50394,7 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17\~feeder) (DELAY (ABSOLUTE - (PORT datad (242:242:242) (312:312:312)) + (PORT datad (673:673:673) (730:730:730)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50226,10 +50404,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17) (DELAY (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1530:1530:1530)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) + (PORT clrn (1581:1581:1581) (1557:1557:1557)) + (PORT ena (1253:1253:1253) (1263:1263:1263)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50244,10 +50422,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_mreq_ff2) (DELAY (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT asdata (565:565:565) (644:644:644)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) + (PORT clk (1532:1532:1532) (1530:1530:1530)) + (PORT asdata (569:569:569) (648:648:648)) + (PORT clrn (1581:1581:1581) (1557:1557:1557)) + (PORT ena (1253:1253:1253) (1263:1263:1263)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50262,9 +50440,9 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~0) (DELAY (ABSOLUTE - (PORT dataa (251:251:251) (340:340:340)) - (PORT datab (251:251:251) (335:335:335)) - (PORT datad (216:216:216) (283:283:283)) + (PORT dataa (915:915:915) (998:998:998)) + (PORT datab (253:253:253) (338:338:338)) + (PORT datad (224:224:224) (295:295:295)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -50277,12 +50455,13 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~1) (DELAY (ABSOLUTE - (PORT dataa (912:912:912) (985:985:985)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datad (182:182:182) (211:211:211)) + (PORT dataa (249:249:249) (340:340:340)) + (PORT datab (259:259:259) (348:348:348)) + (PORT datac (174:174:174) (207:207:207)) + (PORT datad (180:180:180) (210:210:210)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50310,9 +50489,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[0\]) (DELAY (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) + (PORT clk (1911:1911:1911) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50326,8 +50505,8 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (345:345:345)) - (PORT datab (251:251:251) (337:337:337)) + (PORT dataa (406:406:406) (480:480:480)) + (PORT datab (251:251:251) (336:336:336)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datab combout (344:344:344) (369:369:369)) @@ -50341,9 +50520,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) + (PORT clk (1911:1911:1911) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50357,7 +50536,7 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]\~7) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (343:343:343)) + (PORT dataa (253:253:253) (344:344:344)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -50371,9 +50550,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) + (PORT clk (1911:1911:1911) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50387,9 +50566,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[3\]\~9) (DELAY (ABSOLUTE - (PORT datab (252:252:252) (338:338:338)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (254:254:254) (346:346:346)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -50401,66 +50580,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) + (PORT clk (1911:1911:1911) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) - (DELAY - (ABSOLUTE - (PORT datab (251:251:251) (337:337:337)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT datad (226:226:226) (299:299:299)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50474,8 +50596,8 @@ (INSTANCE ula_\|i2c_loader_\|WideAnd0\~0) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (343:343:343)) - (PORT datab (253:253:253) (339:339:339)) + (PORT dataa (252:252:252) (342:342:342)) + (PORT datab (264:264:264) (347:347:347)) (PORT datac (223:223:223) (302:302:302)) (PORT datad (225:225:225) (297:297:297)) (IOPATH dataa combout (324:324:324) (328:328:328)) @@ -50485,29 +50607,104 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (338:338:338)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) + (DELAY + (ABSOLUTE + (PORT datad (226:226:226) (298:298:298)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|WideAnd0) (DELAY (ABSOLUTE - (PORT datab (250:250:250) (334:334:334)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (225:225:225) (296:296:296)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (202:202:202) (242:242:242)) + (PORT datac (224:224:224) (305:305:305)) + (PORT datad (225:225:225) (295:295:295)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|scl_out\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1547:1547:1547)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1560:1560:1560)) + (PORT ena (1023:1023:1023) (976:976:976)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2c_loader_\|state\.Idle) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) + (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) - (PORT ena (1428:1428:1428) (1403:1403:1403)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (1502:1502:1502) (1473:1473:1473)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50522,7 +50719,7 @@ (INSTANCE ula_\|i2c_loader_\|phase\~0) (DELAY (ABSOLUTE - (PORT datad (245:245:245) (317:317:317)) + (PORT datad (410:410:410) (477:477:477)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50533,10 +50730,10 @@ (INSTANCE ula_\|i2c_loader_\|phase\[0\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) + (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) - (PORT ena (1428:1428:1428) (1403:1403:1403)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (1502:1502:1502) (1473:1473:1473)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50551,8 +50748,8 @@ (INSTANCE ula_\|i2c_loader_\|phase\~1) (DELAY (ABSOLUTE - (PORT datab (333:333:333) (440:440:440)) - (PORT datad (247:247:247) (319:319:319)) + (PORT datab (453:453:453) (522:522:522)) + (PORT datad (395:395:395) (465:465:465)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -50562,12 +50759,146 @@ (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2c_loader_\|phase\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (PORT ena (881:881:881) (820:820:820)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|Mux42\~0) + (DELAY + (ABSOLUTE + (PORT datab (455:455:455) (531:531:531)) + (PORT datac (266:266:266) (353:353:353)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbyte\~0) + (DELAY + (ABSOLUTE + (PORT datab (471:471:471) (542:542:542)) + (PORT datac (574:574:574) (630:630:630)) + (PORT datad (871:871:871) (934:934:934)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~4) + (DELAY + (ABSOLUTE + (PORT datad (701:701:701) (764:764:764)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbyte\~4) + (DELAY + (ABSOLUTE + (PORT dataa (420:420:420) (494:494:494)) + (PORT datab (652:652:652) (716:716:716)) + (PORT datad (718:718:718) (781:781:781)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) (DELAY (ABSOLUTE (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) - (PORT ena (1428:1428:1428) (1403:1403:1403)) + (PORT clrn (1566:1566:1566) (1560:1560:1560)) + (PORT ena (820:820:820) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (469:469:469) (541:541:541)) + (PORT datac (593:593:593) (652:652:652)) + (PORT datad (281:281:281) (362:362:362)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (247:247:247)) + (PORT datab (605:605:605) (665:665:665)) + (PORT datac (628:628:628) (682:682:682)) + (PORT datad (856:856:856) (911:911:911)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (687:687:687)) + (PORT datab (642:642:642) (659:659:659)) + (PORT datac (634:634:634) (701:701:701)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1904:1904:1904) (1924:1924:1924)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1568:1568:1568) (1561:1561:1561)) + (PORT ena (1204:1204:1204) (1189:1189:1189)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50582,31 +50913,69 @@ (INSTANCE ula_\|i2c_loader_\|nbit\~5) (DELAY (ABSOLUTE - (PORT dataa (636:636:636) (709:709:709)) + (PORT dataa (739:739:739) (807:807:807)) + (PORT datad (388:388:388) (450:450:450)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) (DELAY (ABSOLUTE - (PORT datab (307:307:307) (404:404:404)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT clk (1534:1534:1534) (1548:1548:1548)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1568:1568:1568) (1561:1561:1561)) + (PORT ena (1235:1235:1235) (1239:1239:1239)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (344:344:344)) + (PORT datab (262:262:262) (351:351:351)) + (PORT datad (381:381:381) (445:445:445)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|Mux42\~0) + (INSTANCE ula_\|i2c_loader_\|state\~27) (DELAY (ABSOLUTE - (PORT datac (700:700:700) (774:774:774)) - (PORT datad (677:677:677) (746:746:746)) + (PORT datab (456:456:456) (528:528:528)) + (PORT datac (269:269:269) (358:358:358)) + (PORT datad (668:668:668) (706:706:706)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~24) + (DELAY + (ABSOLUTE + (PORT datab (473:473:473) (541:541:541)) + (PORT datac (595:595:595) (653:653:653)) + (PORT datad (282:282:282) (363:363:363)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50614,28 +50983,174 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\~4) + (INSTANCE ula_\|i2c_loader_\|state\~26) (DELAY (ABSOLUTE - (PORT dataa (286:286:286) (381:381:381)) - (PORT datab (336:336:336) (443:443:443)) - (PORT datad (634:634:634) (704:704:704)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT datab (457:457:457) (530:530:530)) + (PORT datac (268:268:268) (356:356:356)) + (PORT datad (336:336:336) (359:359:359)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) + (DELAY + (ABSOLUTE + (PORT datab (200:200:200) (239:239:239)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Data) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (688:688:688) (708:708:708)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT sload (875:875:875) (1000:1000:1000)) + (PORT ena (1502:1502:1502) (1473:1473:1473)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~0) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (809:809:809)) + (PORT datab (260:260:260) (350:350:350)) + (PORT datad (384:384:384) (449:449:449)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1548:1548:1548)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1568:1568:1568) (1561:1561:1561)) + (PORT ena (1235:1235:1235) (1239:1239:1239)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (344:344:344)) + (PORT datab (407:407:407) (482:482:482)) + (PORT datac (887:887:887) (938:938:938)) + (PORT datad (236:236:236) (314:314:314)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) + (DELAY + (ABSOLUTE + (PORT dataa (273:273:273) (364:364:364)) + (PORT datab (308:308:308) (401:401:401)) + (PORT datac (572:572:572) (628:628:628)) + (PORT datad (619:619:619) (673:673:673)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (690:690:690)) + (PORT datab (661:661:661) (732:732:732)) + (PORT datac (627:627:627) (680:680:680)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (667:667:667)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datad (857:857:857) (913:913:913)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Ack) + (DELAY + (ABSOLUTE + (PORT clk (1927:1927:1927) (1950:1950:1950)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~7) (DELAY (ABSOLUTE - (PORT datab (290:290:290) (381:381:381)) - (PORT datac (578:578:578) (623:623:623)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datac (668:668:668) (736:736:736)) + (PORT datad (436:436:436) (501:501:501)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -50653,13 +51168,13 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (284:284:284) (379:379:379)) - (PORT datab (272:272:272) (359:359:359)) - (PORT datac (301:301:301) (403:403:403)) - (PORT datad (516:516:516) (513:513:513)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (418:418:418) (494:494:494)) + (PORT datab (754:754:754) (826:826:826)) + (PORT datac (239:239:239) (316:316:316)) + (PORT datad (508:508:508) (502:502:502)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50669,13 +51184,13 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~2) (DELAY (ABSOLUTE - (PORT dataa (662:662:662) (747:747:747)) - (PORT datab (653:653:653) (670:670:670)) - (PORT datac (172:172:172) (206:206:206)) + (PORT dataa (347:347:347) (376:376:376)) + (PORT datab (646:646:646) (667:667:667)) + (PORT datac (618:618:618) (676:676:676)) (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50685,30 +51200,30 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~3) (DELAY (ABSOLUTE - (PORT datab (835:835:835) (857:857:857)) - (PORT datac (423:423:423) (492:492:492)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (633:633:633) (712:712:712)) + (PORT datab (626:626:626) (641:641:641)) + (PORT datad (174:174:174) (201:201:201)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) + (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]) (DELAY (ABSOLUTE (PORT clk (1532:1532:1532) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) + (PORT asdata (689:689:689) (712:712:712)) + (PORT clrn (1566:1566:1566) (1560:1560:1560)) (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -50717,12 +51232,12 @@ (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) (DELAY (ABSOLUTE - (PORT dataa (677:677:677) (755:755:755)) - (PORT datab (713:713:713) (770:770:770)) - (PORT datac (253:253:253) (337:337:337)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (471:471:471) (540:540:540)) + (PORT datac (593:593:593) (650:650:650)) + (PORT datad (278:278:278) (360:360:360)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -50731,11 +51246,11 @@ (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) (DELAY (ABSOLUTE - (PORT dataa (596:596:596) (620:620:620)) - (PORT datab (263:263:263) (314:314:314)) - (PORT datad (341:341:341) (360:360:360)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (PORT dataa (663:663:663) (689:689:689)) + (PORT datab (639:639:639) (655:655:655)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50746,9 +51261,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Stop) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1927:1927:1927) (1950:1950:1950)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50759,15 +51274,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) (DELAY (ABSOLUTE - (PORT dataa (291:291:291) (389:389:389)) - (PORT datab (261:261:261) (350:350:350)) - (PORT datac (232:232:232) (318:318:318)) - (PORT datad (567:567:567) (616:616:616)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (272:272:272) (362:362:362)) + (PORT datab (886:886:886) (951:951:951)) + (PORT datac (804:804:804) (848:848:848)) + (PORT datad (872:872:872) (930:930:930)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50775,112 +51290,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~0) + (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) (DELAY (ABSOLUTE - (PORT dataa (637:637:637) (710:710:710)) - (PORT datab (267:267:267) (356:356:356)) - (PORT datad (234:234:234) (311:311:311)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT datab (296:296:296) (389:389:389)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT ena (1191:1191:1191) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~0) - (DELAY - (ABSOLUTE - (PORT dataa (259:259:259) (351:351:351)) - (PORT datab (249:249:249) (335:335:335)) - (PORT datac (602:602:602) (665:665:665)) - (PORT datad (238:238:238) (316:316:316)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (399:399:399)) - (PORT datab (370:370:370) (392:392:392)) - (PORT datac (920:920:920) (977:977:977)) - (PORT datad (327:327:327) (351:351:351)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (247:247:247)) - (PORT datab (562:562:562) (591:591:591)) - (PORT datad (443:443:443) (515:515:515)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Ack) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (285:285:285) (380:380:380)) - (PORT datab (272:272:272) (356:356:356)) - (PORT datac (302:302:302) (404:404:404)) - (PORT datad (517:517:517) (510:510:510)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (596:596:596) (655:655:655)) + (PORT datab (936:936:936) (980:980:980)) + (PORT datac (623:623:623) (676:676:676)) + (PORT datad (708:708:708) (690:690:690)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50890,13 +51321,13 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~18) (DELAY (ABSOLUTE - (PORT dataa (416:416:416) (489:489:489)) - (PORT datab (587:587:587) (640:640:640)) - (PORT datac (850:850:850) (859:859:859)) - (PORT datad (309:309:309) (325:325:325)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (604:604:604) (640:640:640)) + (PORT datab (457:457:457) (514:514:514)) + (PORT datac (786:786:786) (833:833:833)) + (PORT datad (176:176:176) (203:203:203)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50906,12 +51337,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1898:1898:1898) (1914:1914:1914)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1124:1124:1124) (1148:1148:1148)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sload (1067:1067:1067) (1036:1036:1036)) - (PORT ena (794:794:794) (792:792:792)) + (PORT asdata (2650:2650:2650) (2671:2671:2671)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT sload (1538:1538:1538) (1516:1516:1516)) + (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50928,7 +51359,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]\~10) (DELAY (ABSOLUTE - (PORT datab (297:297:297) (392:392:392)) + (PORT datab (293:293:293) (394:394:394)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -50942,12 +51373,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1898:1898:1898) (1914:1914:1914)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1125:1125:1125) (1149:1149:1149)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sload (1067:1067:1067) (1036:1036:1036)) - (PORT ena (794:794:794) (792:792:792)) + (PORT asdata (2650:2650:2650) (2671:2671:2671)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT sload (1538:1538:1538) (1516:1516:1516)) + (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50964,9 +51395,9 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]\~12) (DELAY (ABSOLUTE - (PORT datab (288:288:288) (380:380:380)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (300:300:300) (412:412:412)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -50978,11 +51409,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1898:1898:1898) (1914:1914:1914)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sload (1067:1067:1067) (1036:1036:1036)) - (PORT ena (794:794:794) (792:792:792)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT sload (1538:1538:1538) (1516:1516:1516)) + (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50999,7 +51430,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]\~14) (DELAY (ABSOLUTE - (PORT datab (306:306:306) (403:403:403)) + (PORT datab (299:299:299) (395:395:395)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -51013,12 +51444,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1898:1898:1898) (1914:1914:1914)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1125:1125:1125) (1150:1150:1150)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sload (1067:1067:1067) (1036:1036:1036)) - (PORT ena (794:794:794) (792:792:792)) + (PORT asdata (2652:2652:2652) (2668:2668:2668)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT sload (1538:1538:1538) (1516:1516:1516)) + (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51035,29 +51466,13 @@ (INSTANCE ula_\|i2c_loader_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (426:426:426) (508:508:508)) - (PORT datab (298:298:298) (392:392:392)) - (PORT datac (277:277:277) (365:365:365)) - (PORT datad (279:279:279) (363:363:363)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (798:798:798)) - (PORT datab (261:261:261) (350:350:350)) - (PORT datac (704:704:704) (778:778:778)) - (PORT datad (260:260:260) (337:337:337)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (430:430:430) (520:520:520)) + (PORT datab (294:294:294) (394:394:394)) + (PORT datac (269:269:269) (375:375:375)) + (PORT datad (277:277:277) (359:359:359)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51067,7 +51482,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]\~16) (DELAY (ABSOLUTE - (PORT dataa (308:308:308) (413:413:413)) + (PORT dataa (298:298:298) (405:405:405)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -51078,11 +51493,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1898:1898:1898) (1914:1914:1914)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sload (1067:1067:1067) (1036:1036:1036)) - (PORT ena (794:794:794) (792:792:792)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT sload (1538:1538:1538) (1516:1516:1516)) + (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51096,29 +51511,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~3) (DELAY (ABSOLUTE - (PORT datab (622:622:622) (640:640:640)) - (PORT datac (335:335:335) (357:357:357)) - (PORT datad (658:658:658) (710:710:710)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~2) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (267:267:267)) - (PORT datab (286:286:286) (376:376:376)) - (PORT datac (231:231:231) (314:314:314)) - (PORT datad (487:487:487) (489:489:489)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (349:349:349) (374:374:374)) + (PORT datad (401:401:401) (464:464:464)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51126,15 +51525,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) + (INSTANCE ula_\|i2c_loader_\|scl_out\~0) (DELAY (ABSOLUTE - (PORT dataa (345:345:345) (374:374:374)) - (PORT datab (266:266:266) (320:320:320)) - (PORT datac (261:261:261) (352:352:352)) - (PORT datad (421:421:421) (491:491:491)) + (PORT dataa (409:409:409) (485:485:485)) + (PORT datab (477:477:477) (546:546:546)) + (PORT datad (869:869:869) (920:920:920)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~4) + (DELAY + (ABSOLUTE + (PORT dataa (553:553:553) (572:572:572)) + (PORT datab (273:273:273) (357:357:357)) + (PORT datac (255:255:255) (340:340:340)) + (PORT datad (668:668:668) (704:704:704)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~5) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (432:432:432) (515:515:515)) + (PORT datac (261:261:261) (346:346:346)) + (PORT datad (220:220:220) (258:258:258)) (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51142,14 +51571,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~3) + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~6) (DELAY (ABSOLUTE - (PORT dataa (343:343:343) (380:380:380)) - (PORT datab (590:590:590) (613:613:613)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (910:910:910) (941:941:941)) + (PORT datab (630:630:630) (649:649:649)) + (PORT datad (173:173:173) (200:200:200)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51160,9 +51589,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51176,11 +51605,11 @@ (INSTANCE ula_\|i2c_loader_\|state\~25) (DELAY (ABSOLUTE - (PORT dataa (264:264:264) (356:356:356)) - (PORT datab (267:267:267) (321:321:321)) - (PORT datad (419:419:419) (488:488:488)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT dataa (249:249:249) (302:302:302)) + (PORT datab (274:274:274) (359:359:359)) + (PORT datad (405:405:405) (476:476:476)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51189,277 +51618,12 @@ (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2c_loader_\|state\.Start) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1192:1192:1192) (1154:1154:1154)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbyte\~0) - (DELAY - (ABSOLUTE - (PORT datab (330:330:330) (437:437:437)) - (PORT datad (630:630:630) (700:700:700)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) - (PORT ena (820:820:820) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (749:749:749)) - (PORT datac (684:684:684) (733:733:733)) - (PORT datad (441:441:441) (514:514:514)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1033:1033:1033) (1086:1086:1086)) - (PORT datab (486:486:486) (561:561:561)) - (PORT datac (255:255:255) (338:338:338)) - (PORT datad (669:669:669) (726:726:726)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (590:590:590) (648:648:648)) - (PORT datad (326:326:326) (348:348:348)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (387:387:387)) - (PORT datab (262:262:262) (314:314:314)) - (PORT datac (556:556:556) (578:578:578)) - (PORT datad (424:424:424) (491:491:491)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1900:1900:1900) (1919:1919:1919)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT ena (1160:1160:1160) (1135:1135:1135)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~6) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (707:707:707)) - (PORT datad (241:241:241) (319:319:319)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) (DELAY (ABSOLUTE (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT ena (1191:1191:1191) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~1) - (DELAY - (ABSOLUTE - (PORT dataa (260:260:260) (355:355:355)) - (PORT datab (252:252:252) (338:338:338)) - (PORT datad (241:241:241) (319:319:319)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~27) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (793:793:793)) - (PORT datac (701:701:701) (775:775:775)) - (PORT datad (486:486:486) (488:488:488)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~24) - (DELAY - (ABSOLUTE - (PORT dataa (677:677:677) (753:753:753)) - (PORT datab (714:714:714) (770:770:770)) - (PORT datac (251:251:251) (332:332:332)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~26) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (798:798:798)) - (PORT datac (702:702:702) (777:777:777)) - (PORT datad (347:347:347) (368:368:368)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (248:248:248)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Data) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (578:578:578) (625:625:625)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT sload (875:875:875) (1003:1003:1003)) - (PORT ena (1192:1192:1192) (1154:1154:1154)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|scl_out\~0) - (DELAY - (ABSOLUTE - (PORT datab (288:288:288) (379:379:379)) - (PORT datac (607:607:607) (657:657:657)) - (PORT datad (233:233:233) (310:310:310)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|scl_out\~_Duplicate_1) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) - (PORT ena (1428:1428:1428) (1403:1403:1403)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (1502:1502:1502) (1473:1473:1473)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51474,12 +51638,12 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~1) (DELAY (ABSOLUTE - (PORT dataa (661:661:661) (746:746:746)) - (PORT datab (330:330:330) (435:435:435)) - (PORT datac (260:260:260) (348:348:348)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (246:246:246) (333:333:333)) + (PORT datab (701:701:701) (768:768:768)) + (PORT datac (620:620:620) (679:679:679)) + (PORT datad (717:717:717) (779:779:779)) + (IOPATH dataa combout (341:341:341) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51490,11 +51654,11 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~2) (DELAY (ABSOLUTE - (PORT dataa (650:650:650) (670:670:670)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datad (630:630:630) (699:699:699)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (202:202:202) (247:247:247)) + (PORT datac (617:617:617) (676:676:676)) + (PORT datad (204:204:204) (234:234:234)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51506,8 +51670,8 @@ (ABSOLUTE (PORT clk (1473:1473:1473) (1495:1495:1495)) (PORT d (958:958:958) (1002:1002:1002)) - (PORT aload (1710:1710:1710) (1775:1775:1775)) - (PORT ena (885:885:885) (884:884:884)) + (PORT aload (1697:1697:1697) (1760:1760:1760)) + (PORT ena (723:723:723) (714:714:714)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) (IOPATH (posedge aload) q (513:513:513) (508:508:508)) ) @@ -51526,8 +51690,8 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) - (PORT ena (1428:1428:1428) (1403:1403:1403)) + (PORT clrn (1566:1566:1566) (1560:1560:1560)) + (PORT ena (1023:1023:1023) (976:976:976)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51537,29 +51701,29 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) - (DELAY - (ABSOLUTE - (PORT datac (887:887:887) (940:940:940)) - (PORT datad (610:610:610) (673:673:673)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|Mux35\~0) (DELAY (ABSOLUTE - (PORT dataa (442:442:442) (520:520:520)) - (PORT datab (457:457:457) (520:520:520)) - (PORT datac (391:391:391) (449:449:449)) - (PORT datad (395:395:395) (456:456:456)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT dataa (431:431:431) (516:516:516)) + (PORT datab (290:290:290) (389:389:389)) + (PORT datac (264:264:264) (368:368:368)) + (PORT datad (275:275:275) (353:353:353)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) + (DELAY + (ABSOLUTE + (PORT datac (616:616:616) (672:672:672)) + (PORT datad (868:868:868) (917:917:917)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51567,56 +51731,76 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) (DELAY (ABSOLUTE - (PORT dataa (306:306:306) (409:409:409)) - (PORT datab (298:298:298) (389:389:389)) - (PORT datac (278:278:278) (370:370:370)) - (PORT datad (262:262:262) (338:338:338)) + (PORT dataa (433:433:433) (517:517:517)) + (PORT datab (292:292:292) (393:393:393)) + (PORT datac (276:276:276) (370:370:370)) + (PORT datad (273:273:273) (355:355:355)) (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) (DELAY (ABSOLUTE - (PORT datac (274:274:274) (369:369:369)) - (PORT datad (260:260:260) (337:337:337)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (302:302:302) (419:419:419)) + (PORT datab (584:584:584) (592:592:592)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (269:269:269) (349:349:349)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) (DELAY (ABSOLUTE - (PORT dataa (203:203:203) (248:248:248)) - (PORT datab (307:307:307) (404:404:404)) - (PORT datac (278:278:278) (370:370:370)) - (PORT datad (198:198:198) (224:224:224)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (303:303:303) (418:418:418)) + (PORT datab (294:294:294) (385:385:385)) + (PORT datac (278:278:278) (369:369:369)) + (PORT datad (274:274:274) (355:355:355)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~24) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) (DELAY (ABSOLUTE - (PORT datab (456:456:456) (520:520:520)) - (PORT datac (890:890:890) (943:943:943)) - (PORT datad (414:414:414) (478:478:478)) + (PORT dataa (557:557:557) (586:586:586)) + (PORT datab (293:293:293) (393:393:393)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (269:269:269) (349:349:349)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (493:493:493) (580:580:580)) + (PORT datac (679:679:679) (744:744:744)) + (PORT datad (662:662:662) (723:723:723)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -51628,11 +51812,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~6) (DELAY (ABSOLUTE - (PORT dataa (707:707:707) (795:795:795)) - (PORT datac (702:702:702) (777:777:777)) - (PORT datad (261:261:261) (341:341:341)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (280:280:280) (368:368:368)) + (PORT datac (265:265:265) (353:353:353)) + (PORT datad (417:417:417) (491:491:491)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51642,13 +51826,13 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~7) (DELAY (ABSOLUTE - (PORT dataa (294:294:294) (393:393:393)) - (PORT datab (263:263:263) (313:313:313)) - (PORT datac (173:173:173) (205:205:205)) - (PORT datad (350:350:350) (370:370:370)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (365:365:365) (400:400:400)) + (PORT datac (264:264:264) (352:352:352)) + (PORT datad (215:215:215) (253:253:253)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51658,11 +51842,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~8) (DELAY (ABSOLUTE - (PORT datab (447:447:447) (530:530:530)) - (PORT datac (557:557:557) (581:581:581)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (910:910:910) (936:936:936)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datad (410:410:410) (480:480:480)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51672,11 +51856,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sclr (1104:1104:1104) (1198:1198:1198)) - (PORT ena (1397:1397:1397) (1366:1366:1366)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT sclr (1298:1298:1298) (1370:1370:1370)) + (PORT ena (949:949:949) (938:938:938)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51689,46 +51873,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~24) (DELAY (ABSOLUTE - (PORT dataa (305:305:305) (408:408:408)) - (PORT datab (305:305:305) (398:398:398)) - (PORT datac (278:278:278) (369:369:369)) - (PORT datad (262:262:262) (338:338:338)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (397:397:397)) - (PORT datab (373:373:373) (401:401:401)) - (PORT datac (390:390:390) (448:448:448)) - (PORT datad (413:413:413) (480:480:480)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (334:334:334)) - (PORT datac (893:893:893) (946:946:946)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (629:629:629) (656:656:656)) + (PORT datac (457:457:457) (542:542:542)) + (PORT datad (219:219:219) (289:289:289)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51738,13 +51890,13 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~10) (DELAY (ABSOLUTE - (PORT dataa (712:712:712) (775:775:775)) - (PORT datab (482:482:482) (560:560:560)) - (PORT datac (588:588:588) (650:650:650)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (428:428:428) (516:516:516)) + (PORT datab (365:365:365) (396:396:396)) + (PORT datac (266:266:266) (352:352:352)) + (PORT datad (420:420:420) (487:487:487)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51754,13 +51906,27 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~11) (DELAY (ABSOLUTE - (PORT dataa (1032:1032:1032) (1083:1083:1083)) - (PORT datab (561:561:561) (587:587:587)) - (PORT datac (921:921:921) (976:976:976)) + (PORT dataa (247:247:247) (300:300:300)) + (PORT datab (281:281:281) (369:369:369)) + (PORT datac (258:258:258) (346:346:346)) (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (940:940:940)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datad (409:409:409) (478:478:478)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51770,10 +51936,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT ena (1207:1207:1207) (1188:1188:1188)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (961:961:961) (968:968:968)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51785,45 +51951,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) (DELAY (ABSOLUTE - (PORT dataa (305:305:305) (410:410:410)) - (PORT datab (303:303:303) (399:399:399)) - (PORT datac (274:274:274) (364:364:364)) - (PORT datad (268:268:268) (349:349:349)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) - (DELAY - (ABSOLUTE - (PORT dataa (445:445:445) (522:522:522)) - (PORT datab (419:419:419) (491:491:491)) - (PORT datac (308:308:308) (330:330:330)) - (PORT datad (197:197:197) (222:222:222)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (337:337:337)) - (PORT datac (886:886:886) (938:938:938)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (304:304:304) (307:307:307)) + (PORT dataa (632:632:632) (649:649:649)) + (PORT datac (456:456:456) (542:542:542)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51834,10 +51968,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[2\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT ena (1207:1207:1207) (1188:1188:1188)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (961:961:961) (968:968:968)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51849,13 +51983,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) (DELAY (ABSOLUTE - (PORT dataa (424:424:424) (505:505:505)) - (PORT datab (298:298:298) (389:389:389)) - (PORT datac (273:273:273) (368:368:368)) - (PORT datad (278:278:278) (358:358:358)) + (PORT dataa (302:302:302) (418:418:418)) + (PORT datab (293:293:293) (393:393:393)) + (PORT datac (277:277:277) (370:370:370)) + (PORT datad (274:274:274) (355:355:355)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -51865,31 +51999,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) (DELAY (ABSOLUTE - (PORT dataa (441:441:441) (526:526:526)) - (PORT datab (454:454:454) (519:519:519)) - (PORT datac (501:501:501) (509:509:509)) - (PORT datad (352:352:352) (369:369:369)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (304:304:304) (418:418:418)) + (PORT datac (279:279:279) (373:373:373)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (625:625:625)) + (PORT datab (349:349:349) (382:382:382)) + (PORT datac (681:681:681) (740:740:740)) + (PORT datad (662:662:662) (720:720:720)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~27) (DELAY (ABSOLUTE - (PORT dataa (639:639:639) (715:715:715)) - (PORT datab (244:244:244) (327:327:327)) - (PORT datac (888:888:888) (940:940:940)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (247:247:247) (334:334:334)) + (PORT datab (831:831:831) (881:881:881)) + (PORT datac (460:460:460) (539:539:539)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51900,10 +52046,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT ena (1207:1207:1207) (1188:1188:1188)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (961:961:961) (968:968:968)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51915,16 +52061,48 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~25) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (679:679:679) (734:734:734)) - (PORT datac (620:620:620) (667:667:667)) - (PORT datad (364:364:364) (423:423:423)) + (PORT dataa (303:303:303) (418:418:418)) + (PORT datab (295:295:295) (395:395:395)) + (PORT datac (277:277:277) (371:371:371)) + (PORT datad (270:270:270) (351:351:351)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) + (DELAY + (ABSOLUTE + (PORT dataa (687:687:687) (761:761:761)) + (PORT datab (657:657:657) (669:669:669)) + (PORT datac (679:679:679) (740:740:740)) + (PORT datad (329:329:329) (349:349:349)) (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (335:335:335)) + (PORT datab (832:832:832) (884:884:884)) + (PORT datac (457:457:457) (542:542:542)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51934,10 +52112,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[4\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT ena (1410:1410:1410) (1399:1399:1399)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (961:961:961) (968:968:968)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51949,12 +52127,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~12) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) (DELAY (ABSOLUTE - (PORT dataa (544:544:544) (558:558:558)) - (PORT datab (488:488:488) (559:559:559)) - (PORT datad (364:364:364) (420:420:420)) + (PORT dataa (640:640:640) (656:656:656)) + (PORT datab (622:622:622) (686:686:686)) + (PORT datad (360:360:360) (411:411:411)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -51966,11 +52144,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1530:1530:1530) (1543:1543:1543)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT sload (1203:1203:1203) (1299:1299:1299)) - (PORT ena (812:812:812) (805:805:805)) + (PORT clrn (1564:1564:1564) (1556:1556:1556)) + (PORT sload (1218:1218:1218) (1319:1319:1319)) + (PORT ena (1180:1180:1180) (1175:1175:1175)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51987,11 +52165,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~9) (DELAY (ABSOLUTE - (PORT datab (642:642:642) (706:706:706)) - (PORT datac (893:893:893) (946:946:946)) - (PORT datad (198:198:198) (224:224:224)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (637:637:637) (656:656:656)) + (PORT datac (454:454:454) (537:537:537)) + (PORT datad (386:386:386) (445:445:445)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52001,11 +52179,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sclr (1104:1104:1104) (1198:1198:1198)) - (PORT ena (1207:1207:1207) (1188:1188:1188)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT sclr (1298:1298:1298) (1370:1370:1370)) + (PORT ena (961:961:961) (968:968:968)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52021,8 +52199,8 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]\~5) (DELAY (ABSOLUTE - (PORT datac (887:887:887) (939:939:939)) - (PORT datad (218:218:218) (287:287:287)) + (PORT datac (461:461:461) (545:545:545)) + (PORT datad (221:221:221) (290:290:290)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52033,11 +52211,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sclr (1104:1104:1104) (1198:1198:1198)) - (PORT ena (1397:1397:1397) (1366:1366:1366)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT sclr (1298:1298:1298) (1370:1370:1370)) + (PORT ena (949:949:949) (938:938:938)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52053,12 +52231,12 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~0) (DELAY (ABSOLUTE - (PORT dataa (683:683:683) (742:742:742)) - (PORT datab (416:416:416) (490:490:490)) - (PORT datac (558:558:558) (607:607:607)) - (PORT datad (384:384:384) (444:444:444)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (674:674:674) (733:733:733)) + (PORT datab (883:883:883) (952:952:952)) + (PORT datac (406:406:406) (468:468:468)) + (PORT datad (869:869:869) (932:932:932)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52069,13 +52247,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~1) (DELAY (ABSOLUTE - (PORT dataa (537:537:537) (561:561:561)) - (PORT datab (327:327:327) (433:433:433)) - (PORT datac (345:345:345) (368:368:368)) - (PORT datad (517:517:517) (510:510:510)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (342:342:342) (381:381:381)) + (PORT datab (755:755:755) (824:824:824)) + (PORT datac (195:195:195) (229:229:229)) + (PORT datad (507:507:507) (501:501:501)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52085,10 +52263,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~2) (DELAY (ABSOLUTE - (PORT dataa (254:254:254) (345:345:345)) - (PORT datab (329:329:329) (434:434:434)) - (PORT datac (260:260:260) (345:345:345)) - (PORT datad (181:181:181) (208:208:208)) + (PORT dataa (253:253:253) (345:345:345)) + (PORT datab (758:758:758) (822:822:822)) + (PORT datac (668:668:668) (731:731:731)) + (PORT datad (181:181:181) (209:209:209)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -52101,10 +52279,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~3) (DELAY (ABSOLUTE - (PORT dataa (255:255:255) (348:348:348)) - (PORT datab (324:324:324) (431:431:431)) - (PORT datac (261:261:261) (346:346:346)) - (PORT datad (180:180:180) (208:208:208)) + (PORT dataa (254:254:254) (345:345:345)) + (PORT datab (758:758:758) (822:822:822)) + (PORT datac (668:668:668) (732:732:732)) + (PORT datad (181:181:181) (209:209:209)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -52117,10 +52295,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~4) (DELAY (ABSOLUTE - (PORT dataa (663:663:663) (743:743:743)) - (PORT datab (802:802:802) (828:828:828)) + (PORT dataa (830:830:830) (894:894:894)) + (PORT datab (231:231:231) (274:274:274)) (PORT datac (173:173:173) (206:206:206)) - (PORT datad (175:175:175) (201:201:201)) + (PORT datad (175:175:175) (200:200:200)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -52135,8 +52313,8 @@ (ABSOLUTE (PORT clk (1475:1475:1475) (1497:1497:1497)) (PORT d (691:691:691) (730:730:730)) - (PORT aload (1726:1726:1726) (1792:1792:1792)) - (PORT ena (1272:1272:1272) (1294:1294:1294)) + (PORT aload (1698:1698:1698) (1763:1763:1763)) + (PORT ena (942:942:942) (938:938:938)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) (IOPATH (posedge aload) q (513:513:513) (508:508:508)) ) @@ -52148,6 +52326,2173 @@ (HOLD ena (posedge clk) (101:101:101)) ) ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2334:2334:2334) (2334:2334:2334)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1890:1890:1890) (1874:1874:1874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux38\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1565:1565:1565) (1641:1641:1641)) + (PORT datab (1300:1300:1300) (1343:1343:1343)) + (PORT datad (181:181:181) (212:212:212)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rd_pending) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (248:248:248) (334:334:334)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[3\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (256:256:256)) + (PORT datab (969:969:969) (1051:1051:1051)) + (PORT datac (661:661:661) (684:684:684)) + (PORT datad (1347:1347:1347) (1447:1447:1447)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (671:671:671) (734:734:734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (248:248:248) (333:333:333)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (671:671:671) (734:734:734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[2\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (249:249:249) (335:335:335)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (671:671:671) (734:734:734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[3\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (343:343:343)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (671:671:671) (734:734:734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[4\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (336:336:336)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (671:671:671) (734:734:734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[5\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (345:345:345)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (671:671:671) (734:734:734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[6\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (343:343:343)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (671:671:671) (734:734:734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[7\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (338:338:338)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (671:671:671) (734:734:734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (343:343:343)) + (PORT datab (251:251:251) (335:335:335)) + (PORT datac (223:223:223) (303:303:303)) + (PORT datad (225:225:225) (298:298:298)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[8\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (338:338:338)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (671:671:671) (734:734:734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (255:255:255) (347:347:347)) + (PORT datab (254:254:254) (340:340:340)) + (PORT datac (226:226:226) (306:306:306)) + (PORT datad (228:228:228) (300:300:300)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.rf_counter\[9\]\~30) + (DELAY + (ABSOLUTE + (PORT datad (226:226:226) (299:299:299)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_counter\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT sclr (671:671:671) (734:734:734)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sclr (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (374:374:374)) + (PORT datab (252:252:252) (336:336:336)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (225:225:225) (296:296:296)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~8) + (DELAY + (ABSOLUTE + (PORT datab (1384:1384:1384) (1487:1487:1487)) + (PORT datac (941:941:941) (1018:1018:1018)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (259:259:259)) + (PORT datab (688:688:688) (717:717:717)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.rf_pending) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (774:774:774) (867:867:867)) + (PORT datab (765:765:765) (851:851:851)) + (PORT datac (642:642:642) (726:726:726)) + (PORT datad (862:862:862) (889:889:889)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (928:928:928)) + (PORT datab (1028:1028:1028) (1104:1104:1104)) + (PORT datac (1269:1269:1269) (1392:1392:1392)) + (PORT datad (571:571:571) (585:585:585)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (928:928:928)) + (PORT datab (1028:1028:1028) (1103:1103:1103)) + (PORT datac (1269:1269:1269) (1391:1391:1391)) + (PORT datad (571:571:571) (585:585:585)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux4\~3) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (687:687:687)) + (PORT datab (305:305:305) (398:398:398)) + (PORT datad (604:604:604) (636:636:636)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.act_row\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1303:1303:1303) (1433:1433:1433)) + (PORT datab (1067:1067:1067) (1184:1184:1184)) + (PORT datac (1412:1412:1412) (1458:1458:1458)) + (PORT datad (995:995:995) (1084:1084:1084)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~2) + (DELAY + (ABSOLUTE + (PORT datac (264:264:264) (345:345:345)) + (PORT datad (285:285:285) (364:364:364)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.act_row\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (364:364:364) (399:399:399)) + (PORT datac (1029:1029:1029) (1132:1132:1132)) + (PORT datad (996:996:996) (1087:1087:1087)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1547:1547:1547)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (966:966:966) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1547:1547:1547)) + (PORT asdata (1576:1576:1576) (1606:1606:1606)) + (PORT ena (966:966:966) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.act_row\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1215:1215:1215) (1258:1258:1258)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1547:1547:1547)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (966:966:966) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal7\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1264:1264:1264) (1305:1305:1305)) + (PORT datab (1250:1250:1250) (1293:1293:1293)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1547:1547:1547)) + (PORT asdata (1323:1323:1323) (1390:1390:1390)) + (PORT ena (966:966:966) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.act_row\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1547:1547:1547)) + (PORT asdata (3043:3043:3043) (3212:3212:3212)) + (PORT ena (966:966:966) (964:964:964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2732:2732:2732) (2911:2911:2911)) + (PORT datab (1007:1007:1007) (1081:1081:1081)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal7\~2) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (468:468:468)) + (PORT datab (252:252:252) (337:337:337)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (183:183:183) (213:213:213)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1442:1442:1442) (1496:1496:1496)) + (PORT datab (1034:1034:1034) (1124:1124:1124)) + (PORT datac (1028:1028:1028) (1131:1131:1131)) + (PORT datad (1030:1030:1030) (1145:1145:1145)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1281:1281:1281) (1388:1388:1388)) + (PORT datac (582:582:582) (600:600:600)) + (PORT datad (340:340:340) (361:361:361)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux39\~2) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (253:253:253)) + (PORT datab (661:661:661) (681:681:681)) + (PORT datad (1354:1354:1354) (1381:1381:1381)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.wr_pending) + (DELAY + (ABSOLUTE + (PORT clk (1528:1528:1528) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~8) + (DELAY + (ABSOLUTE + (PORT datac (1172:1172:1172) (1258:1258:1258)) + (PORT datad (1054:1054:1054) (1165:1165:1165)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~9) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (522:522:522)) + (PORT datab (614:614:614) (638:638:638)) + (PORT datac (668:668:668) (744:744:744)) + (PORT datad (286:286:286) (365:365:365)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1283:1283:1283) (1389:1389:1389)) + (PORT datab (311:311:311) (401:401:401)) + (PORT datac (195:195:195) (229:229:229)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~4) + (DELAY + (ABSOLUTE + (PORT datab (692:692:692) (771:771:771)) + (PORT datac (580:580:580) (597:597:597)) + (PORT datad (1249:1249:1249) (1337:1337:1337)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1279:1279:1279) (1385:1385:1385)) + (PORT datac (1172:1172:1172) (1258:1258:1258)) + (PORT datad (1055:1055:1055) (1166:1166:1166)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~5) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (969:969:969) (1043:1043:1043)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (988:988:988)) + (PORT datac (793:793:793) (832:832:832)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (291:291:291) (388:388:388)) + (PORT datab (724:724:724) (811:811:811)) + (PORT datac (201:201:201) (238:238:238)) + (PORT datad (738:738:738) (805:805:805)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (283:283:283) (378:378:378)) + (PORT datab (299:299:299) (395:395:395)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (739:739:739) (807:807:807)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux6\~6) + (DELAY + (ABSOLUTE + (PORT datab (304:304:304) (399:399:399)) + (PORT datac (605:605:605) (644:644:644)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1305:1305:1305) (1435:1435:1435)) + (PORT datac (1028:1028:1028) (1132:1132:1132)) + (PORT datad (990:990:990) (1085:1085:1085)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~2) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (628:628:628)) + (PORT datab (1461:1461:1461) (1510:1510:1510)) + (PORT datac (668:668:668) (746:746:746)) + (PORT datad (1051:1051:1051) (1164:1164:1164)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~3) + (DELAY + (ABSOLUTE + (PORT datab (828:828:828) (934:934:934)) + (PORT datac (781:781:781) (892:892:892)) + (PORT datad (869:869:869) (909:909:909)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~3) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (1007:1007:1007)) + (PORT datab (297:297:297) (391:391:391)) + (PORT datad (739:739:739) (802:802:802)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~4) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (247:247:247)) + (PORT datab (297:297:297) (388:388:388)) + (PORT datac (870:870:870) (951:951:951)) + (PORT datad (275:275:275) (355:355:355)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~5) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (963:963:963)) + (PORT datab (300:300:300) (396:396:396)) + (PORT datac (690:690:690) (777:777:777)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~0) + (DELAY + (ABSOLUTE + (PORT datab (992:992:992) (1065:1065:1065)) + (PORT datac (1256:1256:1256) (1350:1350:1350)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~7) + (DELAY + (ABSOLUTE + (PORT datac (1261:1261:1261) (1385:1385:1385)) + (PORT datad (986:986:986) (1059:1059:1059)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~10) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (958:958:958)) + (PORT datab (995:995:995) (1070:1070:1070)) + (PORT datac (1256:1256:1256) (1357:1357:1357)) + (PORT datad (685:685:685) (768:768:768)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~1) + (DELAY + (ABSOLUTE + (PORT dataa (421:421:421) (450:450:450)) + (PORT datab (382:382:382) (407:407:407)) + (PORT datac (1029:1029:1029) (1106:1106:1106)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~6) + (DELAY + (ABSOLUTE + (PORT dataa (796:796:796) (830:830:830)) + (PORT datab (344:344:344) (369:369:369)) + (PORT datac (259:259:259) (349:349:349)) + (PORT datad (838:838:838) (843:843:843)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (401:401:401)) + (PORT datab (1287:1287:1287) (1386:1386:1386)) + (PORT datac (961:961:961) (1031:1031:1031)) + (PORT datad (347:347:347) (368:368:368)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~10) + (DELAY + (ABSOLUTE + (PORT dataa (777:777:777) (870:870:870)) + (PORT datab (765:765:765) (853:853:853)) + (PORT datac (766:766:766) (877:877:877)) + (PORT datad (675:675:675) (776:776:776)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~3) + (DELAY + (ABSOLUTE + (PORT dataa (801:801:801) (923:923:923)) + (PORT datab (1024:1024:1024) (1102:1102:1102)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~4) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (389:389:389)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datac (1262:1262:1262) (1383:1383:1383)) + (PORT datad (711:711:711) (805:805:805)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~7) + (DELAY + (ABSOLUTE + (PORT dataa (290:290:290) (388:388:388)) + (PORT datab (775:775:775) (845:845:845)) + (PORT datac (870:870:870) (953:953:953)) + (PORT datad (889:889:889) (964:964:964)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~8) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (378:378:378)) + (PORT datab (297:297:297) (392:392:392)) + (PORT datac (689:689:689) (775:775:775)) + (PORT datad (275:275:275) (357:357:357)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~5) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (1011:1011:1011)) + (PORT datab (726:726:726) (812:812:812)) + (PORT datac (796:796:796) (836:836:836)) + (PORT datad (274:274:274) (354:354:354)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~6) + (DELAY + (ABSOLUTE + (PORT dataa (431:431:431) (511:511:511)) + (PORT datab (229:229:229) (271:271:271)) + (PORT datac (631:631:631) (672:672:672)) + (PORT datad (914:914:914) (945:945:945)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux5\~9) + (DELAY + (ABSOLUTE + (PORT dataa (284:284:284) (379:379:379)) + (PORT datab (669:669:669) (707:707:707)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~2) + (DELAY + (ABSOLUTE + (PORT datab (1023:1023:1023) (1112:1112:1112)) + (PORT datac (948:948:948) (1070:1070:1070)) + (PORT datad (994:994:994) (1080:1080:1080)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~3) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (396:396:396)) + (PORT datab (1264:1264:1264) (1347:1347:1347)) + (PORT datac (1576:1576:1576) (1655:1655:1655)) + (PORT datad (1570:1570:1570) (1693:1693:1693)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1366:1366:1366) (1517:1517:1517)) + (PORT datab (1478:1478:1478) (1602:1602:1602)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1253:1253:1253) (1313:1313:1313)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~10) + (DELAY + (ABSOLUTE + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (1172:1172:1172) (1258:1258:1258)) + (PORT datad (1055:1055:1055) (1165:1165:1165)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.init_counter\[0\]\~0) + (DELAY + (ABSOLUTE + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1561:1561:1561)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~1) + (DELAY + (ABSOLUTE + (PORT datab (734:734:734) (825:825:825)) + (IOPATH datab cout (446:446:446) (318:318:318)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (282:282:282) (364:364:364)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (264:264:264) (351:351:351)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (437:437:437) (497:497:497)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.init_counter\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (345:345:345) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1553:1553:1553)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (265:265:265) (353:353:353)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (265:265:265) (353:353:353)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~12) + (DELAY + (ABSOLUTE + (PORT datab (264:264:264) (347:347:347)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~14) + (DELAY + (ABSOLUTE + (PORT datab (284:284:284) (367:367:367)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~16) + (DELAY + (ABSOLUTE + (PORT datab (264:264:264) (347:347:347)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~18) + (DELAY + (ABSOLUTE + (PORT datab (264:264:264) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~20) + (DELAY + (ABSOLUTE + (PORT dataa (266:266:266) (352:352:352)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (496:496:496)) + (PORT datab (447:447:447) (515:515:515)) + (PORT datac (387:387:387) (456:456:456)) + (PORT datad (407:407:407) (472:472:472)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT datab (449:449:449) (514:514:514)) + (PORT datac (416:416:416) (481:481:481)) + (PORT datad (244:244:244) (315:315:315)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~22) + (DELAY + (ABSOLUTE + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~24) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (341:341:341)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~26) + (DELAY + (ABSOLUTE + (PORT datab (249:249:249) (333:333:333)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Add1\~28) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (344:344:344)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.init_counter\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1554:1554:1554)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (345:345:345)) + (PORT datab (252:252:252) (337:337:337)) + (PORT datac (224:224:224) (306:306:306)) + (PORT datad (227:227:227) (299:299:299)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (353:353:353) (381:381:381)) + (PORT datad (388:388:388) (451:451:451)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~11) + (DELAY + (ABSOLUTE + (PORT dataa (744:744:744) (865:865:865)) + (PORT datab (304:304:304) (399:399:399)) + (PORT datad (752:752:752) (835:835:835)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~12) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (608:608:608)) + (PORT datab (662:662:662) (714:714:714)) + (PORT datac (1575:1575:1575) (1693:1693:1693)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1512:1512:1512) (1632:1632:1632)) + (PORT datab (1378:1378:1378) (1503:1503:1503)) + (PORT datac (566:566:566) (574:574:574)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (341:341:341) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1278:1278:1278) (1384:1384:1384)) + (PORT datab (1463:1463:1463) (1512:1512:1512)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (862:862:862) (878:878:878)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1217:1217:1217) (1339:1339:1339)) + (PORT datab (975:975:975) (1056:1056:1056)) + (PORT datac (968:968:968) (1042:1042:1042)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux8\~2) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (811:811:811)) + (PORT datac (1118:1118:1118) (1180:1180:1180)) + (PORT datad (873:873:873) (903:903:903)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1534:1534:1534) (1551:1551:1551)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux72\~0) + (DELAY + (ABSOLUTE + (PORT datab (3068:3068:3068) (3183:3183:3183)) + (PORT datac (902:902:902) (1002:1002:1002)) + (PORT datad (278:278:278) (362:362:362)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux72\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1025:1025:1025) (1085:1085:1085)) + (PORT datab (3069:3069:3069) (3185:3185:3185)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (360:360:360) (379:379:379)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux84\~0) + (DELAY + (ABSOLUTE + (PORT datac (252:252:252) (338:338:338)) + (PORT datad (739:739:739) (806:806:806)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux84\~1) + (DELAY + (ABSOLUTE + (PORT dataa (429:429:429) (511:511:511)) + (PORT datab (303:303:303) (398:398:398)) + (PORT datac (261:261:261) (351:351:351)) + (PORT datad (171:171:171) (197:197:197)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux3\~0) + (DELAY + (ABSOLUTE + (PORT datab (3069:3069:3069) (3191:3191:3191)) + (PORT datac (1141:1141:1141) (1223:1223:1223)) + (PORT datad (280:280:280) (365:365:365)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1024:1024:1024) (1092:1092:1092)) + (PORT datab (3070:3070:3070) (3193:3193:3193)) + (PORT datac (312:312:312) (331:331:331)) + (PORT datad (343:343:343) (365:365:365)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux2\~0) + (DELAY + (ABSOLUTE + (PORT datab (3070:3070:3070) (3185:3185:3185)) + (PORT datac (1121:1121:1121) (1216:1216:1216)) + (PORT datad (283:283:283) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1027:1027:1027) (1093:1093:1093)) + (PORT datab (3073:3073:3073) (3192:3192:3192)) + (PORT datac (347:347:347) (370:370:370)) + (PORT datad (628:628:628) (674:674:674)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux1\~0) + (DELAY + (ABSOLUTE + (PORT datab (3073:3073:3073) (3191:3191:3191)) + (PORT datac (1123:1123:1123) (1214:1214:1214)) + (PORT datad (280:280:280) (360:360:360)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1024:1024:1024) (1093:1093:1093)) + (PORT datab (3064:3064:3064) (3191:3191:3191)) + (PORT datac (609:609:609) (617:617:617)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT datab (3064:3064:3064) (3190:3190:3190)) + (PORT datac (972:972:972) (1042:1042:1042)) + (PORT datad (282:282:282) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1027:1027:1027) (1093:1093:1093)) + (PORT datab (3072:3072:3072) (3191:3191:3191)) + (PORT datac (312:312:312) (340:340:340)) + (PORT datad (608:608:608) (655:655:655)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux73\~0) + (DELAY + (ABSOLUTE + (PORT datab (3066:3066:3066) (3187:3187:3187)) + (PORT datac (1488:1488:1488) (1592:1592:1592)) + (PORT datad (279:279:279) (362:362:362)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux73\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1024:1024:1024) (1090:1090:1090)) + (PORT datab (3063:3063:3063) (3193:3193:3193)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (611:611:611) (659:659:659)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux74\~0) + (DELAY + (ABSOLUTE + (PORT datab (3072:3072:3072) (3189:3189:3189)) + (PORT datac (922:922:922) (1010:1010:1010)) + (PORT datad (277:277:277) (361:361:361)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux74\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1025:1025:1025) (1085:1085:1085)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (3027:3027:3027) (3147:3147:3147)) + (PORT datad (635:635:635) (683:683:683)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux75\~0) + (DELAY + (ABSOLUTE + (PORT datac (1505:1505:1505) (1638:1638:1638)) + (PORT datad (1359:1359:1359) (1405:1405:1405)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|mclk_r\~0) @@ -52162,9 +54507,9 @@ (INSTANCE ula_\|i2s_intf_\|mclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1921:1921:1921) (1947:1947:1947)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1564:1564:1564) (1556:1556:1556)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52179,8 +54524,8 @@ (DELAY (ABSOLUTE (PORT clk (1506:1506:1506) (1528:1528:1528)) - (PORT d (2379:2379:2379) (2282:2282:2282)) - (PORT clrn (1763:1763:1763) (1815:1815:1815)) + (PORT d (976:976:976) (1002:1002:1002)) + (PORT clrn (1750:1750:1750) (1800:1800:1800)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -52195,8 +54540,8 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~1) (DELAY (ABSOLUTE - (PORT dataa (697:697:697) (777:777:777)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (684:684:684) (751:751:751)) + (IOPATH datab cout (446:446:446) (318:318:318)) ) ) ) @@ -52219,10 +54564,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~2) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (277:277:277)) - (PORT datac (174:174:174) (208:208:208)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (210:210:210) (240:240:240)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -52231,9 +54576,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1895:1895:1895) (1917:1917:1917)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1563:1563:1563) (1555:1555:1555)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52247,7 +54592,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~4) (DELAY (ABSOLUTE - (PORT dataa (398:398:398) (479:479:479)) + (PORT dataa (399:399:399) (480:480:480)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52261,8 +54606,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]\~8) (DELAY (ABSOLUTE - (PORT datad (328:328:328) (343:343:343)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (315:315:315) (334:334:334)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -52271,9 +54616,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1915:1915:1915)) + (PORT clk (1895:1895:1895) (1918:1918:1918)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1568:1568:1568)) + (PORT clrn (1564:1564:1564) (1555:1555:1555)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52287,9 +54632,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~6) (DELAY (ABSOLUTE - (PORT datab (391:391:391) (458:458:458)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (435:435:435) (503:503:503)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52301,8 +54646,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]\~7) (DELAY (ABSOLUTE - (PORT datac (345:345:345) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datad (557:557:557) (571:571:571)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -52311,9 +54656,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1921:1921:1921) (1947:1947:1947)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1564:1564:1564) (1556:1556:1556)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52327,7 +54672,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~8) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (337:337:337)) + (PORT datab (252:252:252) (338:338:338)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52341,10 +54686,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~1) (DELAY (ABSOLUTE - (PORT dataa (231:231:231) (281:281:281)) - (PORT datac (172:172:172) (204:204:204)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datad (209:209:209) (240:240:240)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -52353,9 +54698,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1895:1895:1895) (1917:1917:1917)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1563:1563:1563) (1555:1555:1555)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52369,9 +54714,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~10) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (337:337:337)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (438:438:438) (505:505:505)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52383,7 +54728,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]\~6) (DELAY (ABSOLUTE - (PORT datad (175:175:175) (201:201:201)) + (PORT datad (314:314:314) (330:330:330)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52393,9 +54738,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1895:1895:1895) (1918:1918:1918)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1564:1564:1564) (1555:1555:1555)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52409,10 +54754,10 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (400:400:400) (481:481:481)) - (PORT datab (252:252:252) (338:338:338)) - (PORT datac (365:365:365) (427:427:427)) - (PORT datad (227:227:227) (300:300:300)) + (PORT dataa (398:398:398) (480:480:480)) + (PORT datab (250:250:250) (336:336:336)) + (PORT datac (395:395:395) (461:461:461)) + (PORT datad (394:394:394) (457:457:457)) (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -52425,9 +54770,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~12) (DELAY (ABSOLUTE - (PORT dataa (427:427:427) (491:491:491)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (426:426:426) (495:495:495)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52439,7 +54784,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]\~5) (DELAY (ABSOLUTE - (PORT datad (338:338:338) (357:357:357)) + (PORT datad (330:330:330) (348:348:348)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52449,9 +54794,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1895:1895:1895) (1918:1918:1918)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1564:1564:1564) (1555:1555:1555)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52465,7 +54810,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~14) (DELAY (ABSOLUTE - (PORT dataa (438:438:438) (507:507:507)) + (PORT dataa (396:396:396) (477:477:477)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52479,8 +54824,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]\~4) (DELAY (ABSOLUTE - (PORT datad (333:333:333) (348:348:348)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (335:335:335) (357:357:357)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -52489,9 +54834,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1915:1915:1915)) + (PORT clk (1895:1895:1895) (1918:1918:1918)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1568:1568:1568)) + (PORT clrn (1564:1564:1564) (1555:1555:1555)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52505,9 +54850,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~16) (DELAY (ABSOLUTE - (PORT dataa (396:396:396) (467:467:467)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (253:253:253) (338:338:338)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52519,10 +54864,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~0) (DELAY (ABSOLUTE - (PORT datab (376:376:376) (401:401:401)) - (PORT datac (380:380:380) (411:411:411)) + (PORT datab (201:201:201) (240:240:240)) + (PORT datad (210:210:210) (241:241:241)) (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -52531,9 +54876,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[8\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1895:1895:1895) (1917:1917:1917)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1563:1563:1563) (1555:1555:1555)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52547,7 +54892,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~18) (DELAY (ABSOLUTE - (PORT datad (383:383:383) (442:442:442)) + (PORT datad (383:383:383) (441:441:441)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -52558,8 +54903,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]\~3) (DELAY (ABSOLUTE - (PORT datad (337:337:337) (357:357:357)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (343:343:343) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -52568,9 +54913,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1893:1893:1893) (1916:1916:1916)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1562:1562:1562) (1554:1554:1554)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52584,13 +54929,13 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (397:397:397) (468:468:468)) - (PORT datab (423:423:423) (484:484:484)) - (PORT datac (392:392:392) (453:453:453)) - (PORT datad (393:393:393) (454:454:454)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (398:398:398) (478:478:478)) + (PORT datab (422:422:422) (482:482:482)) + (PORT datac (222:222:222) (301:301:301)) + (PORT datad (393:393:393) (456:456:456)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52600,10 +54945,10 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (249:249:249) (333:333:333)) - (PORT datac (664:664:664) (736:736:736)) - (PORT datad (176:176:176) (202:202:202)) + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (248:248:248) (333:333:333)) + (PORT datac (317:317:317) (336:336:336)) + (PORT datad (650:650:650) (712:712:712)) (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -52611,30 +54956,20 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2feeder) - (DELAY - (ABSOLUTE - (PORT datad (198:198:198) (224:224:224)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT asdata (535:535:535) (565:565:565)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL @@ -52642,8 +54977,8 @@ (INSTANCE ula_\|i2s_intf_\|lrclk_r\~0) (DELAY (ABSOLUTE - (PORT datab (905:905:905) (938:938:938)) - (PORT datad (233:233:233) (308:308:308)) + (PORT datab (962:962:962) (999:999:999)) + (PORT datad (231:231:231) (304:304:304)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52655,8 +54990,8 @@ (DELAY (ABSOLUTE (PORT clk (1505:1505:1505) (1526:1526:1526)) - (PORT d (2289:2289:2289) (2450:2450:2450)) - (PORT clrn (1761:1761:1761) (1813:1813:1813)) + (PORT d (1379:1379:1379) (1433:1433:1433)) + (PORT clrn (1748:1748:1748) (1798:1798:1798)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -52672,8 +55007,8 @@ (DELAY (ABSOLUTE (PORT clk (1505:1505:1505) (1527:1527:1527)) - (PORT d (2528:2528:2528) (2663:2663:2663)) - (PORT clrn (1762:1762:1762) (1814:1814:1814)) + (PORT d (1386:1386:1386) (1428:1428:1428)) + (PORT clrn (1749:1749:1749) (1799:1799:1799)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -52683,25 +55018,66 @@ (HOLD d (posedge clk) (97:97:97)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~18) + (DELAY + (ABSOLUTE + (PORT dataa (426:426:426) (458:458:458)) + (PORT datab (965:965:965) (1004:1004:1004)) + (PORT datad (217:217:217) (253:253:253)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]\~5) (DELAY (ABSOLUTE - (PORT datab (248:248:248) (334:334:334)) + (PORT datab (252:252:252) (337:337:337)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1feeder) + (DELAY + (ABSOLUTE + (PORT datac (193:193:193) (226:226:226)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52715,12 +55091,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~15) (DELAY (ABSOLUTE - (PORT datab (235:235:235) (283:283:283)) - (PORT datac (873:873:873) (896:896:896)) - (PORT datad (241:241:241) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (913:913:913) (945:945:945)) + (PORT datab (277:277:277) (369:369:369)) + (PORT datac (204:204:204) (241:241:241)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -52729,11 +55105,11 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2714:2714:2714) (2746:2746:2746)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (PORT sload (1479:1479:1479) (1529:1529:1529)) + (PORT asdata (570:570:570) (611:611:611)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) + (PORT sload (1495:1495:1495) (1558:1558:1558)) (PORT ena (790:790:790) (783:783:783)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -52751,7 +55127,7 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]\~7) (DELAY (ABSOLUTE - (PORT datab (248:248:248) (333:333:333)) + (PORT datab (251:251:251) (337:337:337)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52765,11 +55141,11 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2713:2713:2713) (2746:2746:2746)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (PORT sload (1479:1479:1479) (1529:1529:1529)) + (PORT asdata (570:570:570) (612:612:612)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) + (PORT sload (1495:1495:1495) (1558:1558:1558)) (PORT ena (790:790:790) (783:783:783)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -52787,7 +55163,7 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]\~9) (DELAY (ABSOLUTE - (PORT datab (250:250:250) (335:335:335)) + (PORT datab (252:252:252) (338:338:338)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52801,11 +55177,11 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2711:2711:2711) (2744:2744:2744)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (PORT sload (1479:1479:1479) (1529:1529:1529)) + (PORT asdata (567:567:567) (608:608:608)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) + (PORT sload (1495:1495:1495) (1558:1558:1558)) (PORT ena (790:790:790) (783:783:783)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -52823,9 +55199,9 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]\~11) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (343:343:343)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (264:264:264) (348:348:348)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52837,11 +55213,44 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2711:2711:2711) (2744:2744:2744)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (PORT sload (1479:1479:1479) (1529:1529:1529)) + (PORT asdata (568:568:568) (608:608:608)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) + (PORT sload (1495:1495:1495) (1558:1558:1558)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (366:366:366)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (568:568:568) (610:610:610)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) + (PORT sload (1495:1495:1495) (1558:1558:1558)) (PORT ena (790:790:790) (783:783:783)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -52859,56 +55268,39 @@ (INSTANCE ula_\|i2s_intf_\|LessThan0\~0) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (343:343:343)) - (PORT datab (252:252:252) (338:338:338)) - (PORT datac (223:223:223) (303:303:303)) - (PORT datad (227:227:227) (299:299:299)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (409:409:409) (479:479:479)) + (PORT datab (251:251:251) (335:335:335)) + (PORT datac (223:223:223) (301:301:301)) + (PORT datad (225:225:225) (296:296:296)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]\~1) (DELAY (ABSOLUTE - (PORT datab (269:269:269) (360:360:360)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH cin combout (455:455:455) (437:437:437)) + (PORT dataa (384:384:384) (461:461:461)) + (PORT datab (551:551:551) (565:565:565)) + (PORT datac (238:238:238) (326:326:326)) + (PORT datad (188:188:188) (220:220:220)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2710:2710:2710) (2743:2743:2743)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (PORT sload (1479:1479:1479) (1529:1529:1529)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|Add2\~7) (DELAY (ABSOLUTE - (PORT dataa (467:467:467) (538:538:538)) + (PORT dataa (415:415:415) (507:507:507)) (IOPATH dataa cout (436:436:436) (315:315:315)) ) ) @@ -52918,9 +55310,9 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~8) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (344:344:344)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (252:252:252) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52932,13 +55324,13 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~20) (DELAY (ABSOLUTE - (PORT dataa (470:470:470) (540:540:540)) - (PORT datab (903:903:903) (940:940:940)) - (PORT datac (205:205:205) (243:243:243)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (417:417:417) (505:505:505)) + (PORT datab (966:966:966) (1004:1004:1004)) + (PORT datac (318:318:318) (335:335:335)) + (PORT datad (217:217:217) (252:252:252)) (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52948,9 +55340,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52964,9 +55356,9 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~10) (DELAY (ABSOLUTE - (PORT dataa (399:399:399) (472:472:472)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (573:573:573) (642:642:642)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52978,12 +55370,12 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~17) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (284:284:284)) - (PORT datab (234:234:234) (285:285:285)) - (PORT datac (875:875:875) (898:898:898)) - (PORT datad (338:338:338) (359:359:359)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (427:427:427) (459:459:459)) + (PORT datab (962:962:962) (1006:1006:1006)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (331:331:331) (353:353:353)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52994,9 +55386,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53010,7 +55402,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~12) (DELAY (ABSOLUTE - (PORT datab (253:253:253) (339:339:339)) + (PORT datab (251:251:251) (335:335:335)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53024,12 +55416,12 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~19) (DELAY (ABSOLUTE - (PORT dataa (471:471:471) (539:539:539)) - (PORT datab (906:906:906) (939:939:939)) - (PORT datac (206:206:206) (243:243:243)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (419:419:419) (509:509:509)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (879:879:879) (891:891:891)) + (PORT datad (219:219:219) (255:255:255)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53040,9 +55432,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53056,7 +55448,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~14) (DELAY (ABSOLUTE - (PORT datad (362:362:362) (417:417:417)) + (PORT datad (227:227:227) (301:301:301)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -53067,12 +55459,12 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~16) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (285:285:285)) - (PORT datab (235:235:235) (288:288:288)) - (PORT datac (875:875:875) (900:900:900)) - (PORT datad (339:339:339) (359:359:359)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (426:426:426) (457:457:457)) + (PORT datab (965:965:965) (1004:1004:1004)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (333:333:333) (353:353:353)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53083,9 +55475,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53099,72 +55491,25 @@ (INSTANCE ula_\|i2s_intf_\|Equal1\~0) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (345:345:345)) - (PORT datab (253:253:253) (339:339:339)) - (PORT datac (368:368:368) (430:430:430)) - (PORT datad (361:361:361) (415:415:415)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (266:266:266) (353:353:353)) - (PORT datab (217:217:217) (263:263:263)) - (PORT datac (241:241:241) (328:328:328)) - (PORT datad (373:373:373) (399:399:399)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (251:251:251) (339:339:339)) + (PORT datab (249:249:249) (333:333:333)) + (PORT datac (223:223:223) (302:302:302)) + (PORT datad (549:549:549) (606:606:606)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~18) - (DELAY - (ABSOLUTE - (PORT dataa (908:908:908) (938:938:938)) - (PORT datab (235:235:235) (286:286:286)) - (PORT datad (375:375:375) (401:401:401)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|Equal1\~1) (DELAY (ABSOLUTE - (PORT datac (382:382:382) (450:450:450)) - (PORT datad (371:371:371) (396:396:396)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (246:246:246) (293:293:293)) + (PORT datad (391:391:391) (462:462:462)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53174,10 +55519,10 @@ (INSTANCE ula_\|i2s_intf_\|bclk_r\~0) (DELAY (ABSOLUTE - (PORT datab (216:216:216) (262:262:262)) - (PORT datac (239:239:239) (326:326:326)) - (PORT datad (238:238:238) (316:316:316)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (216:216:216) (267:267:267)) + (PORT datac (241:241:241) (330:330:330)) + (PORT datad (251:251:251) (332:332:332)) + (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53188,12 +55533,13 @@ (INSTANCE ula_\|i2s_intf_\|bclk_r\~1) (DELAY (ABSOLUTE - (PORT dataa (226:226:226) (283:283:283)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datad (869:869:869) (882:882:882)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (546:546:546) (569:569:569)) + (PORT datab (276:276:276) (367:367:367)) + (PORT datac (881:881:881) (906:906:906)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53204,8 +55550,8 @@ (DELAY (ABSOLUTE (PORT clk (1504:1504:1504) (1526:1526:1526)) - (PORT d (2278:2278:2278) (2430:2430:2430)) - (PORT clrn (1761:1761:1761) (1813:1813:1813)) + (PORT d (1492:1492:1492) (1572:1572:1572)) + (PORT clrn (1748:1748:1748) (1798:1798:1798)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -53220,7 +55566,7 @@ (INSTANCE ula_\|pcm_outl\[13\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (861:861:861) (917:917:917)) + (PORT datad (931:931:931) (990:990:990)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53230,12 +55576,12 @@ (INSTANCE ula_\|always0\~2) (DELAY (ABSOLUTE - (PORT dataa (1754:1754:1754) (1860:1860:1860)) - (PORT datab (1594:1594:1594) (1730:1730:1730)) - (PORT datac (1193:1193:1193) (1255:1255:1255)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (1869:1869:1869) (2024:2024:2024)) + (PORT datac (3075:3075:3075) (3301:3301:3301)) + (PORT datad (2569:2569:2569) (2679:2679:2679)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -53244,13 +55590,13 @@ (INSTANCE ula_\|always0\~3) (DELAY (ABSOLUTE - (PORT dataa (686:686:686) (777:777:777)) - (PORT datab (1248:1248:1248) (1347:1347:1347)) - (PORT datac (1200:1200:1200) (1266:1266:1266)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (2571:2571:2571) (2819:2819:2819)) + (PORT datab (1226:1226:1226) (1334:1334:1334)) + (PORT datac (2100:2100:2100) (2229:2229:2229)) + (PORT datad (1093:1093:1093) (1082:1082:1082)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53262,7 +55608,7 @@ (ABSOLUTE (PORT clk (1522:1522:1522) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2002:2002:2002) (1998:1998:1998)) + (PORT ena (997:997:997) (1007:1007:1007)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -53276,12 +55622,12 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~19) (DELAY (ABSOLUTE - (PORT dataa (225:225:225) (279:279:279)) - (PORT datab (216:216:216) (259:259:259)) - (PORT datac (241:241:241) (328:328:328)) - (PORT datad (239:239:239) (317:317:317)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (551:551:551) (575:575:575)) + (PORT datab (279:279:279) (373:373:373)) + (PORT datac (242:242:242) (331:331:331)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53301,11 +55647,11 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~20) (DELAY (ABSOLUTE - (PORT dataa (1354:1354:1354) (1417:1417:1417)) - (PORT datab (1297:1297:1297) (1385:1385:1385)) - (PORT datad (764:764:764) (757:757:757)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) + (PORT dataa (985:985:985) (1054:1054:1054)) + (PORT datab (567:567:567) (582:582:582)) + (PORT datad (752:752:752) (742:742:742)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53316,9 +55662,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (1877:1877:1877) (1887:1887:1887)) + (PORT clk (1908:1908:1908) (1928:1928:1928)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53332,24 +55678,24 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~18) (DELAY (ABSOLUTE - (PORT datab (244:244:244) (327:327:327)) - (PORT datad (1250:1250:1250) (1334:1334:1334)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datac (928:928:928) (981:981:981)) + (PORT datad (220:220:220) (290:290:290)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~2) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]\~2) (DELAY (ABSOLUTE - (PORT datab (234:234:234) (283:283:283)) - (PORT datac (872:872:872) (895:895:895)) - (PORT datad (240:240:240) (318:318:318)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (911:911:911) (946:946:946)) + (PORT datab (278:278:278) (373:373:373)) + (PORT datac (202:202:202) (239:239:239)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -53358,10 +55704,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53376,9 +55722,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~17) (DELAY (ABSOLUTE - (PORT datac (216:216:216) (293:293:293)) - (PORT datad (1250:1250:1250) (1341:1341:1341)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datac (945:945:945) (999:999:999)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53388,10 +55734,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[2\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53406,10 +55752,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~16) (DELAY (ABSOLUTE - (PORT datab (245:245:245) (328:328:328)) - (PORT datad (1259:1259:1259) (1340:1340:1340)) + (PORT datab (245:245:245) (329:329:329)) + (PORT datac (941:941:941) (995:995:995)) (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -53418,10 +55764,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[3\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53436,9 +55782,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~15) (DELAY (ABSOLUTE - (PORT datab (246:246:246) (330:330:330)) - (PORT datad (1269:1269:1269) (1352:1352:1352)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datac (925:925:925) (991:991:991)) + (PORT datad (219:219:219) (287:287:287)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53448,10 +55794,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53466,10 +55812,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~14) (DELAY (ABSOLUTE - (PORT datab (245:245:245) (328:328:328)) - (PORT datad (1270:1270:1270) (1351:1351:1351)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (248:248:248) (336:336:336)) + (PORT datac (946:946:946) (1001:1001:1001)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -53478,10 +55824,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53496,9 +55842,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~13) (DELAY (ABSOLUTE - (PORT dataa (247:247:247) (335:335:335)) - (PORT datad (1261:1261:1261) (1348:1348:1348)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT datac (939:939:939) (985:985:985)) + (PORT datad (219:219:219) (289:289:289)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53508,10 +55854,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53526,9 +55872,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~12) (DELAY (ABSOLUTE - (PORT datab (245:245:245) (328:328:328)) - (PORT datad (1246:1246:1246) (1335:1335:1335)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datac (946:946:946) (1005:1005:1005)) + (PORT datad (219:219:219) (287:287:287)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53538,10 +55884,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53556,10 +55902,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~11) (DELAY (ABSOLUTE - (PORT datac (216:216:216) (292:292:292)) - (PORT datad (1248:1248:1248) (1334:1334:1334)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (244:244:244) (327:327:327)) + (PORT datac (949:949:949) (1004:1004:1004)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -53568,10 +55914,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53586,9 +55932,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~10) (DELAY (ABSOLUTE - (PORT datab (244:244:244) (327:327:327)) - (PORT datad (1249:1249:1249) (1344:1344:1344)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datac (948:948:948) (1006:1006:1006)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53598,10 +55944,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[9\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53616,10 +55962,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~9) (DELAY (ABSOLUTE - (PORT datac (218:218:218) (296:296:296)) - (PORT datad (1269:1269:1269) (1350:1350:1350)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (245:245:245) (328:328:328)) + (PORT datac (947:947:947) (1002:1002:1002)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -53628,10 +55974,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[10\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53646,9 +55992,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~8) (DELAY (ABSOLUTE - (PORT dataa (246:246:246) (334:334:334)) - (PORT datad (1268:1268:1268) (1351:1351:1351)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT datac (950:950:950) (1004:1004:1004)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53658,10 +56004,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[11\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53676,9 +56022,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~7) (DELAY (ABSOLUTE - (PORT datab (244:244:244) (327:327:327)) - (PORT datad (1265:1265:1265) (1355:1355:1355)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datac (927:927:927) (980:980:980)) + (PORT datad (221:221:221) (291:291:291)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53688,10 +56034,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[12\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53706,9 +56052,9 @@ (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1406:1406:1406) (1457:1457:1457)) - (PORT datab (896:896:896) (935:935:935)) - (PORT datad (232:232:232) (306:306:306)) + (PORT dataa (462:462:462) (530:530:530)) + (PORT datab (964:964:964) (1007:1007:1007)) + (PORT datad (235:235:235) (310:310:310)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -53721,9 +56067,9 @@ (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53737,9 +56083,9 @@ (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1405:1405:1405) (1456:1456:1456)) - (PORT datab (896:896:896) (934:934:934)) - (PORT datad (232:232:232) (306:306:306)) + (PORT dataa (462:462:462) (530:530:530)) + (PORT datab (964:964:964) (1006:1006:1006)) + (PORT datad (234:234:234) (310:310:310)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -53752,9 +56098,9 @@ (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53768,9 +56114,9 @@ (INSTANCE ula_\|pcm_outr\~0) (DELAY (ABSOLUTE - (PORT datac (218:218:218) (296:296:296)) - (PORT datad (219:219:219) (289:289:289)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (246:246:246) (334:334:334)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53780,9 +56126,9 @@ (INSTANCE ula_\|pcm_outl\[12\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT clk (1527:1527:1527) (1539:1539:1539)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2116:2116:2116) (2146:2146:2146)) + (PORT ena (2947:2947:2947) (2964:2964:2964)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -53796,11 +56142,11 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~6) (DELAY (ABSOLUTE - (PORT datab (1303:1303:1303) (1391:1391:1391)) - (PORT datac (218:218:218) (295:295:295)) - (PORT datad (1337:1337:1337) (1421:1421:1421)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (247:247:247) (335:335:335)) + (PORT datac (938:938:938) (987:987:987)) + (PORT datad (368:368:368) (428:428:428)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53810,10 +56156,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[13\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53828,10 +56174,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~5) (DELAY (ABSOLUTE - (PORT datab (1222:1222:1222) (1334:1334:1334)) - (PORT datac (217:217:217) (292:292:292)) - (PORT datad (1267:1267:1267) (1356:1356:1356)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT datab (1401:1401:1401) (1507:1507:1507)) + (PORT datac (929:929:929) (981:981:981)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53842,10 +56188,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[14\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53855,14 +56201,24 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|pcm_outl\[14\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (595:595:595) (610:610:610)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|pcm_outl\[14\]) (DELAY (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2262:2262:2262) (2235:2235:2235)) + (PORT ena (997:997:997) (1007:1007:1007)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -53876,9 +56232,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~4) (DELAY (ABSOLUTE - (PORT dataa (1212:1212:1212) (1296:1296:1296)) - (PORT datac (981:981:981) (1087:1087:1087)) - (PORT datad (656:656:656) (680:680:680)) + (PORT dataa (266:266:266) (354:354:354)) + (PORT datac (926:926:926) (989:989:989)) + (PORT datad (1495:1495:1495) (1587:1587:1587)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53890,10 +56246,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[15\]) (DELAY (ABSOLUTE - (PORT clk (1895:1895:1895) (1927:1927:1927)) + (PORT clk (1545:1545:1545) (1561:1561:1561)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1569:1569:1569)) - (PORT ena (1154:1154:1154) (1136:1136:1136)) + (PORT clrn (1569:1569:1569) (1561:1561:1561)) + (PORT ena (1385:1385:1385) (1360:1360:1360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53908,9 +56264,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~3) (DELAY (ABSOLUTE - (PORT datac (216:216:216) (293:293:293)) - (PORT datad (656:656:656) (683:683:683)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (619:619:619) (640:640:640)) + (PORT datad (664:664:664) (716:716:716)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53920,10 +56276,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[16\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1541:1541:1541)) + (PORT clk (1907:1907:1907) (1932:1932:1932)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1569:1569:1569)) - (PORT ena (1190:1190:1190) (1184:1184:1184)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1437:1437:1437) (1422:1422:1422)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53938,9 +56294,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~0) (DELAY (ABSOLUTE - (PORT datab (243:243:243) (325:325:325)) - (PORT datad (652:652:652) (681:681:681)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datab (615:615:615) (638:638:638)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53951,9 +56307,9 @@ (DELAY (ABSOLUTE (PORT clk (1508:1508:1508) (1530:1530:1530)) - (PORT d (1487:1487:1487) (1588:1588:1588)) - (PORT clrn (1765:1765:1765) (1817:1817:1817)) - (PORT ena (1717:1717:1717) (1806:1806:1806)) + (PORT d (1138:1138:1138) (1176:1176:1176)) + (PORT clrn (1752:1752:1752) (1802:1802:1802)) + (PORT ena (867:867:867) (864:864:864)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -53967,106 +56323,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan2\~0) + (INSTANCE ula_\|border\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (291:291:291) (381:381:381)) - (PORT datab (270:270:270) (353:353:353)) - (PORT datac (262:262:262) (341:341:341)) - (PORT datad (244:244:244) (316:316:316)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (263:263:263) (348:348:348)) - (PORT datab (260:260:260) (342:342:342)) - (PORT datac (255:255:255) (332:332:332)) - (PORT datad (237:237:237) (307:307:307)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (457:457:457) (540:540:540)) - (PORT datab (270:270:270) (354:354:354)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (356:356:356) (374:374:374)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (291:291:291) (383:383:383)) - (PORT datab (241:241:241) (280:280:280)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (271:271:271) (361:361:361)) - (PORT datab (261:261:261) (343:343:343)) - (PORT datad (247:247:247) (320:320:320)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|disp_enable\~0) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (410:410:410) (484:484:484)) - (PORT datad (659:659:659) (717:717:717)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|disp_enable\~1) - (DELAY - (ABSOLUTE - (PORT dataa (211:211:211) (260:260:260)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datad (348:348:348) (371:371:371)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT datad (1169:1169:1169) (1173:1173:1173)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54076,28 +56336,44 @@ (INSTANCE ula_\|border\[1\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) - (PORT asdata (537:537:537) (568:568:568)) - (PORT ena (2116:2116:2116) (2146:2146:2146)) + (PORT clk (1533:1533:1533) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1802:1802:1802) (1799:1799:1799)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (371:371:371)) + (PORT datab (261:261:261) (342:342:342)) + (PORT datac (234:234:234) (309:309:309)) + (PORT datad (236:236:236) (304:304:304)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|LessThan6\~1) (DELAY (ABSOLUTE - (PORT dataa (453:453:453) (541:541:541)) - (PORT datab (461:461:461) (551:551:551)) - (PORT datac (424:424:424) (504:504:504)) - (PORT datad (416:416:416) (444:444:444)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (284:284:284) (371:371:371)) + (PORT datab (282:282:282) (365:365:365)) + (PORT datac (395:395:395) (452:452:452)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54108,11 +56384,11 @@ (INSTANCE ula_\|video_\|LessThan4\~0) (DELAY (ABSOLUTE - (PORT dataa (271:271:271) (361:361:361)) - (PORT datab (273:273:273) (358:358:358)) + (PORT dataa (446:446:446) (511:511:511)) + (PORT datab (270:270:270) (355:355:355)) (PORT datad (236:236:236) (304:304:304)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54123,13 +56399,13 @@ (INSTANCE ula_\|video_\|screen_en\~0) (DELAY (ABSOLUTE - (PORT dataa (446:446:446) (522:522:522)) - (PORT datab (461:461:461) (542:542:542)) - (PORT datac (543:543:543) (561:561:561)) - (PORT datad (646:646:646) (718:718:718)) + (PORT dataa (412:412:412) (506:506:506)) + (PORT datab (678:678:678) (734:734:734)) + (PORT datac (607:607:607) (669:669:669)) + (PORT datad (515:515:515) (528:528:528)) (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54139,9 +56415,9 @@ (INSTANCE ula_\|video_\|screen_en\~1) (DELAY (ABSOLUTE - (PORT dataa (683:683:683) (744:744:744)) - (PORT datab (483:483:483) (561:561:561)) - (PORT datac (172:172:172) (205:205:205)) + (PORT dataa (279:279:279) (371:371:371)) + (PORT datab (288:288:288) (373:373:373)) + (PORT datac (344:344:344) (366:366:366)) (PORT datad (174:174:174) (199:199:199)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (336:336:336) (325:325:325)) @@ -54152,10 +56428,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) + (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1472:1472:1472) (1505:1505:1505)) + (PORT datad (897:897:897) (930:930:930)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54165,25 +56441,25 @@ (INSTANCE ula_\|video_\|Decoder0\~1) (DELAY (ABSOLUTE - (PORT dataa (1252:1252:1252) (1343:1343:1343)) - (PORT datab (984:984:984) (1066:1066:1066)) - (PORT datac (973:973:973) (1043:1043:1043)) - (PORT datad (280:280:280) (364:364:364)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (445:445:445) (545:545:545)) + (PORT datab (978:978:978) (1051:1051:1051)) + (PORT datac (708:708:708) (773:773:773)) + (PORT datad (743:743:743) (801:801:801)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]) + (INSTANCE ula_\|video_\|attr_prefetch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) + (PORT clk (1912:1912:1912) (1935:1935:1935)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) + (PORT ena (1216:1216:1216) (1204:1204:1204)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54197,10 +56473,10 @@ (INSTANCE ula_\|video_\|Decoder0\~0) (DELAY (ABSOLUTE - (PORT dataa (1252:1252:1252) (1342:1342:1342)) - (PORT datab (985:985:985) (1065:1065:1065)) - (PORT datac (974:974:974) (1042:1042:1042)) - (PORT datad (280:280:280) (364:364:364)) + (PORT dataa (443:443:443) (543:543:543)) + (PORT datab (973:973:973) (1046:1046:1046)) + (PORT datac (708:708:708) (775:775:775)) + (PORT datad (740:740:740) (796:796:796)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -54208,98 +56484,14 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1788:1788:1788) (1847:1847:1847)) - (PORT ena (1421:1421:1421) (1414:1414:1414)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1546:1546:1546) (1544:1544:1544)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1012:1012:1012) (1085:1085:1085)) - (PORT ena (1421:1421:1421) (1414:1414:1414)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1196:1196:1196) (1239:1239:1239)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|attr\[7\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (1010:1010:1010) (1078:1078:1078)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (1142:1142:1142) (1195:1195:1195)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54313,9 +56505,10 @@ (INSTANCE ula_\|video_\|frame\[0\]\~12) (DELAY (ABSOLUTE - (PORT dataa (620:620:620) (643:643:643)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT datab (1176:1176:1176) (1194:1194:1194)) + (PORT datad (226:226:226) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -54324,13 +56517,13 @@ (INSTANCE ula_\|video_\|frame\[0\]) (DELAY (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1878:1878:1878) (1891:1891:1891)) + (PORT asdata (517:517:517) (548:548:548)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL @@ -54338,8 +56531,8 @@ (INSTANCE ula_\|video_\|frame\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (613:613:613) (667:667:667)) - (PORT datab (243:243:243) (325:325:325)) + (PORT dataa (389:389:389) (459:459:459)) + (PORT datab (251:251:251) (336:336:336)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datab combout (344:344:344) (369:369:369)) @@ -54353,9 +56546,9 @@ (INSTANCE ula_\|video_\|frame\[1\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT clk (1538:1538:1538) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1236:1236:1236) (1237:1237:1237)) + (PORT ena (1765:1765:1765) (1740:1740:1740)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54369,9 +56562,9 @@ (INSTANCE ula_\|video_\|frame\[2\]\~6) (DELAY (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (243:243:243) (326:326:326)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -54383,9 +56576,9 @@ (INSTANCE ula_\|video_\|frame\[2\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT clk (1538:1538:1538) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1236:1236:1236) (1237:1237:1237)) + (PORT ena (1765:1765:1765) (1740:1740:1740)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54399,7 +56592,7 @@ (INSTANCE ula_\|video_\|frame\[3\]\~8) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (324:324:324)) + (PORT datab (243:243:243) (326:326:326)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -54413,9 +56606,9 @@ (INSTANCE ula_\|video_\|frame\[3\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT clk (1538:1538:1538) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1236:1236:1236) (1237:1237:1237)) + (PORT ena (1765:1765:1765) (1740:1740:1740)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54429,8 +56622,8 @@ (INSTANCE ula_\|video_\|frame\[4\]\~10) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (353:353:353)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT datad (380:380:380) (439:439:439)) + (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) ) @@ -54440,14 +56633,14 @@ (INSTANCE ula_\|video_\|frame\[4\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1236:1236:1236) (1237:1237:1237)) + (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT asdata (661:661:661) (675:675:675)) + (PORT ena (1765:1765:1765) (1740:1740:1740)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -54456,7 +56649,7 @@ (INSTANCE ula_\|video_\|inverted) (DELAY (ABSOLUTE - (PORT datad (372:372:372) (423:423:423)) + (PORT datad (663:663:663) (721:721:721)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54467,7 +56660,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1154:1154:1154) (1160:1160:1160)) + (PORT datad (1069:1069:1069) (1058:1058:1058)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54477,13 +56670,13 @@ (INSTANCE ula_\|video_\|Decoder0\~2) (DELAY (ABSOLUTE - (PORT dataa (1252:1252:1252) (1340:1340:1340)) - (PORT datab (986:986:986) (1064:1064:1064)) - (PORT datac (973:973:973) (1044:1044:1044)) - (PORT datad (279:279:279) (363:363:363)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (444:444:444) (543:543:543)) + (PORT datab (975:975:975) (1047:1047:1047)) + (PORT datac (710:710:710) (775:775:775)) + (PORT datad (742:742:742) (800:800:800)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54493,9 +56686,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1883:1883:1883) (1894:1894:1894)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1217:1217:1217) (1218:1218:1218)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54504,29 +56697,19 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (609:609:609) (678:678:678)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits\[6\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (1321:1321:1321) (1397:1397:1397)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -54535,7 +56718,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1545:1545:1545) (1541:1541:1541)) + (PORT datad (1432:1432:1432) (1427:1427:1427)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54545,9 +56728,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1883:1883:1883) (1894:1894:1894)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1217:1217:1217) (1218:1218:1218)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54561,9 +56744,9 @@ (INSTANCE ula_\|video_\|bits\[4\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (997:997:997) (1070:1070:1070)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (973:973:973) (1033:1033:1033)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54577,7 +56760,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (937:937:937) (955:955:955)) + (PORT datad (933:933:933) (975:975:975)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54587,9 +56770,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1883:1883:1883) (1894:1894:1894)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1217:1217:1217) (1218:1218:1218)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54603,7 +56786,7 @@ (INSTANCE ula_\|video_\|bits\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (651:651:651) (725:725:725)) + (PORT datad (650:650:650) (704:704:704)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54613,9 +56796,9 @@ (INSTANCE ula_\|video_\|bits\[5\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54629,7 +56812,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1201:1201:1201) (1243:1243:1243)) + (PORT datad (894:894:894) (929:929:929)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54639,9 +56822,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1883:1883:1883) (1894:1894:1894)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1217:1217:1217) (1218:1218:1218)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54655,9 +56838,9 @@ (INSTANCE ula_\|video_\|bits\[7\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (1216:1216:1216) (1295:1295:1295)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (991:991:991) (1050:1050:1050)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54671,11 +56854,11 @@ (INSTANCE ula_\|video_\|Mux0\~0) (DELAY (ABSOLUTE - (PORT dataa (385:385:385) (460:460:460)) - (PORT datab (288:288:288) (377:377:377)) - (PORT datad (636:636:636) (698:698:698)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (306:306:306) (408:408:408)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (378:378:378) (431:431:431)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54686,9 +56869,9 @@ (INSTANCE ula_\|video_\|Mux0\~1) (DELAY (ABSOLUTE - (PORT dataa (244:244:244) (330:330:330)) - (PORT datab (287:287:287) (374:374:374)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (304:304:304) (404:404:404)) + (PORT datab (243:243:243) (325:325:325)) + (PORT datad (173:173:173) (198:198:198)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -54701,7 +56884,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (883:883:883) (890:890:890)) + (PORT datad (1044:1044:1044) (1032:1032:1032)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54711,9 +56894,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1883:1883:1883) (1894:1894:1894)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1217:1217:1217) (1218:1218:1218)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54727,7 +56910,7 @@ (INSTANCE ula_\|video_\|bits\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (640:640:640) (711:711:711)) + (PORT datad (645:645:645) (702:702:702)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54737,9 +56920,9 @@ (INSTANCE ula_\|video_\|bits\[2\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54753,7 +56936,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1463:1463:1463) (1429:1429:1429)) + (PORT datad (910:910:910) (917:917:917)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54763,9 +56946,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1883:1883:1883) (1894:1894:1894)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1217:1217:1217) (1218:1218:1218)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54779,9 +56962,9 @@ (INSTANCE ula_\|video_\|bits\[0\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (978:978:978) (1047:1047:1047)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (1488:1488:1488) (1559:1559:1559)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54795,7 +56978,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1470:1470:1470) (1502:1502:1502)) + (PORT datad (645:645:645) (655:655:655)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54805,9 +56988,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1883:1883:1883) (1894:1894:1894)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1217:1217:1217) (1218:1218:1218)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54821,7 +57004,7 @@ (INSTANCE ula_\|video_\|bits\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (642:642:642) (704:704:704)) + (PORT datad (643:643:643) (702:702:702)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54831,9 +57014,9 @@ (INSTANCE ula_\|video_\|bits\[1\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54847,7 +57030,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1276:1276:1276) (1241:1241:1241)) + (PORT datad (925:925:925) (942:942:942)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54857,9 +57040,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1883:1883:1883) (1894:1894:1894)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1217:1217:1217) (1218:1218:1218)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54873,9 +57056,9 @@ (INSTANCE ula_\|video_\|bits\[3\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (1448:1448:1448) (1474:1474:1474)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (1153:1153:1153) (1205:1205:1205)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54889,11 +57072,11 @@ (INSTANCE ula_\|video_\|Mux0\~2) (DELAY (ABSOLUTE - (PORT dataa (242:242:242) (328:328:328)) - (PORT datab (286:286:286) (373:373:373)) - (PORT datad (633:633:633) (694:694:694)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (309:309:309) (409:409:409)) + (PORT datab (243:243:243) (325:325:325)) + (PORT datad (381:381:381) (435:435:435)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54904,9 +57087,9 @@ (INSTANCE ula_\|video_\|Mux0\~3) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (329:329:329)) - (PORT datab (287:287:287) (377:377:377)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (309:309:309) (409:409:409)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (172:172:172) (197:197:197)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -54916,44 +57099,217 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|cindex\[1\]\~0) + (INSTANCE ula_\|video_\|cindex\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (401:401:401) (477:477:477)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (173:173:173) (206:206:206)) + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (200:200:200) (239:239:239)) (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (337:337:337) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1431:1431:1431) (1427:1427:1427)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1912:1912:1912) (1935:1935:1935)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1216:1216:1216) (1204:1204:1204)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (999:999:999) (1058:1058:1058)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (645:645:645) (655:655:655)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1912:1912:1912) (1935:1935:1935)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1216:1216:1216) (1204:1204:1204)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (998:998:998) (1057:1057:1057)) + (PORT ena (1452:1452:1452) (1445:1445:1445)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|cindex\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (245:245:245) (332:332:332)) - (PORT datad (347:347:347) (363:363:363)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT dataa (216:216:216) (266:266:266)) + (PORT datad (351:351:351) (406:406:406)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (411:411:411) (501:501:501)) + (PORT datab (289:289:289) (374:374:374)) + (PORT datac (249:249:249) (334:334:334)) + (PORT datad (264:264:264) (337:337:337)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (705:705:705)) + (PORT datab (467:467:467) (530:530:530)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (350:350:350) (372:372:372)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (504:504:504)) + (PORT datab (468:468:468) (533:533:533)) + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (348:348:348) (370:370:370)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (262:262:262) (348:348:348)) + (PORT datad (248:248:248) (321:321:321)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|disp_enable\~0) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (727:727:727)) + (PORT datab (261:261:261) (343:343:343)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|disp_enable\~1) + (DELAY + (ABSOLUTE + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (511:511:511) (525:525:525)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|VGA_R\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (398:398:398) (453:453:453)) - (PORT datab (1490:1490:1490) (1585:1585:1585)) - (PORT datac (235:235:235) (278:278:278)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (1435:1435:1435) (1539:1539:1539)) + (PORT datab (236:236:236) (279:279:279)) + (PORT datac (325:325:325) (348:348:348)) + (PORT datad (204:204:204) (234:234:234)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54964,7 +57320,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1157:1157:1157) (1161:1161:1161)) + (PORT datad (1068:1068:1068) (1056:1056:1056)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54974,9 +57330,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) + (PORT clk (1912:1912:1912) (1935:1935:1935)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) + (PORT ena (1216:1216:1216) (1204:1204:1204)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54990,9 +57346,9 @@ (INSTANCE ula_\|video_\|attr\[6\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1216:1216:1216) (1269:1269:1269)) - (PORT ena (1638:1638:1638) (1616:1616:1616)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (970:970:970) (1019:1019:1019)) + (PORT ena (1289:1289:1289) (1289:1289:1289)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55006,11 +57362,11 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (212:212:212) (261:261:261)) - (PORT datab (208:208:208) (249:249:249)) - (PORT datad (348:348:348) (371:371:371)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (365:365:365) (395:395:395)) + (PORT datab (1103:1103:1103) (1116:1116:1116)) + (PORT datad (184:184:184) (213:213:213)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55021,11 +57377,21 @@ (INSTANCE ula_\|video_\|VGA_R\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (269:269:269) (322:322:322)) - (PORT datac (391:391:391) (430:430:430)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (362:362:362) (395:395:395)) + (PORT datab (237:237:237) (282:282:282)) + (PORT datac (325:325:325) (348:348:348)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|border\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1310:1310:1310) (1352:1352:1352)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55035,35 +57401,9 @@ (INSTANCE ula_\|border\[2\]) (DELAY (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT asdata (956:956:956) (977:977:977)) - (PORT ena (812:812:812) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (884:884:884) (889:889:889)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) + (PORT clk (1527:1527:1527) (1540:1540:1540)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) + (PORT ena (1944:1944:1944) (1933:1933:1933)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55072,28 +57412,12 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (1208:1208:1208) (1265:1265:1265)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|attr_prefetch\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (935:935:935) (952:952:952)) + (PORT datad (930:930:930) (973:973:973)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55103,9 +57427,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) + (PORT clk (1912:1912:1912) (1935:1935:1935)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) + (PORT ena (1216:1216:1216) (1204:1204:1204)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55119,9 +57443,51 @@ (INSTANCE ula_\|video_\|attr\[5\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (993:993:993) (1051:1051:1051)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (1010:1010:1010) (1067:1067:1067)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1045:1045:1045) (1032:1032:1032)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1912:1912:1912) (1935:1935:1935)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1216:1216:1216) (1204:1204:1204)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (1430:1430:1430) (1470:1470:1470)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55135,9 +57501,9 @@ (INSTANCE ula_\|video_\|cindex\[2\]\~2) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (324:324:324)) - (PORT datad (203:203:203) (232:232:232)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (217:217:217) (269:269:269)) + (PORT datad (218:218:218) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55148,10 +57514,10 @@ (INSTANCE ula_\|video_\|VGA_G\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (2313:2313:2313) (2480:2480:2480)) - (PORT datab (411:411:411) (449:449:449)) - (PORT datac (384:384:384) (420:420:420)) - (PORT datad (547:547:547) (557:557:557)) + (PORT dataa (230:230:230) (275:275:275)) + (PORT datab (240:240:240) (285:285:285)) + (PORT datac (859:859:859) (931:931:931)) + (PORT datad (318:318:318) (335:335:335)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -55164,11 +57530,21 @@ (INSTANCE ula_\|video_\|VGA_G\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (636:636:636) (662:662:662)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datad (378:378:378) (398:398:398)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (360:360:360) (394:394:394)) + (PORT datac (603:603:603) (618:618:618)) + (PORT datad (315:315:315) (331:331:331)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|border\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (578:578:578) (598:598:598)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55178,9 +57554,51 @@ (INSTANCE ula_\|border\[0\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) - (PORT asdata (1466:1466:1466) (1519:1519:1519)) - (PORT ena (2116:2116:2116) (2146:2146:2146)) + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1726:1726:1726) (1702:1702:1702)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (912:912:912) (918:918:918)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1912:1912:1912) (1935:1935:1935)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1216:1216:1216) (1204:1204:1204)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (973:973:973) (1033:1033:1033)) + (PORT ena (1452:1452:1452) (1445:1445:1445)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55189,64 +57607,12 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1462:1462:1462) (1430:1430:1430)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (839:839:839) (888:888:888)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1421:1421:1421) (1414:1414:1414)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|attr_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1276:1276:1276) (1242:1242:1242)) + (PORT datad (929:929:929) (945:945:945)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55256,9 +57622,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) + (PORT clk (1912:1912:1912) (1935:1935:1935)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) + (PORT ena (1216:1216:1216) (1204:1204:1204)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55272,9 +57638,9 @@ (INSTANCE ula_\|video_\|attr\[3\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (965:965:965) (1040:1040:1040)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1541:1541:1541) (1553:1553:1553)) + (PORT asdata (974:974:974) (1030:1030:1030)) + (PORT ena (1227:1227:1227) (1206:1206:1206)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55288,8 +57654,8 @@ (INSTANCE ula_\|video_\|cindex\[0\]\~3) (DELAY (ABSOLUTE - (PORT datab (384:384:384) (459:459:459)) - (PORT datad (204:204:204) (232:232:232)) + (PORT datab (379:379:379) (445:445:445)) + (PORT datad (187:187:187) (222:222:222)) (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -55301,13 +57667,13 @@ (INSTANCE ula_\|video_\|VGA_B\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (399:399:399) (453:453:453)) - (PORT datab (1662:1662:1662) (1745:1745:1745)) - (PORT datac (233:233:233) (279:279:279)) - (PORT datad (334:334:334) (354:354:354)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1720:1720:1720) (1842:1842:1842)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (364:364:364) (389:389:389)) + (PORT datad (369:369:369) (393:393:393)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55317,11 +57683,11 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~2) (DELAY (ABSOLUTE - (PORT dataa (269:269:269) (323:323:323)) - (PORT datac (391:391:391) (429:429:429)) - (PORT datad (340:340:340) (359:359:359)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (358:358:358) (393:393:393)) + (PORT datab (348:348:348) (385:385:385)) + (PORT datad (371:371:371) (397:397:397)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55331,11 +57697,11 @@ (INSTANCE ula_\|video_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (681:681:681) (753:753:753)) - (PORT datab (282:282:282) (364:364:364)) - (PORT datad (645:645:645) (715:715:715)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (895:895:895) (960:960:960)) + (PORT datac (851:851:851) (897:897:897)) + (PORT datad (1129:1129:1129) (1171:1171:1171)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55345,7 +57711,7 @@ (INSTANCE ula_\|video_\|VGA_HS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT clk (1540:1540:1540) (1552:1552:1552)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -55359,9 +57725,9 @@ (INSTANCE ula_\|video_\|Selector0\~0) (DELAY (ABSOLUTE - (PORT dataa (1030:1030:1030) (1035:1035:1035)) - (PORT datab (228:228:228) (270:270:270)) - (PORT datad (571:571:571) (575:575:575)) + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (401:401:401) (435:435:435)) + (PORT datad (362:362:362) (380:380:380)) (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -55375,7 +57741,7 @@ (DELAY (ABSOLUTE (PORT clk (1509:1509:1509) (1531:1531:1531)) - (PORT d (1715:1715:1715) (1721:1721:1721)) + (PORT d (2297:2297:2297) (2325:2325:2325)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -55389,7 +57755,7 @@ (INSTANCE ula_\|video_\|VGA_VS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) + (PORT clk (1541:1541:1541) (1552:1552:1552)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -55403,11 +57769,11 @@ (INSTANCE ula_\|video_\|Selector1\~0) (DELAY (ABSOLUTE - (PORT dataa (620:620:620) (642:642:642)) - (PORT datab (1174:1174:1174) (1179:1179:1179)) - (PORT datad (691:691:691) (762:762:762)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (284:284:284) (381:381:381)) + (PORT datab (527:527:527) (549:549:549)) + (PORT datad (1470:1470:1470) (1488:1488:1488)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55419,7 +57785,7 @@ (DELAY (ABSOLUTE (PORT clk (1507:1507:1507) (1529:1529:1529)) - (PORT d (1805:1805:1805) (1839:1839:1839)) + (PORT d (1566:1566:1566) (1671:1671:1671)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -55433,7 +57799,7 @@ (INSTANCE z80_\|memory_ifc_\|q1\~feeder) (DELAY (ABSOLUTE - (PORT datad (620:620:620) (667:667:667)) + (PORT datad (252:252:252) (325:325:325)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55443,10 +57809,10 @@ (INSTANCE z80_\|memory_ifc_\|q1) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1553:1553:1553)) + (PORT clk (1525:1525:1525) (1541:1541:1541)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (1483:1483:1483) (1473:1473:1473)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT ena (1243:1243:1243) (1234:1234:1234)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55461,10 +57827,10 @@ (INSTANCE z80_\|memory_ifc_\|q2) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1553:1553:1553)) - (PORT asdata (560:560:560) (634:634:634)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (1483:1483:1483) (1473:1473:1473)) + (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT asdata (558:558:558) (632:632:632)) + (PORT clrn (1582:1582:1582) (1558:1558:1558)) + (PORT ena (1243:1243:1243) (1234:1234:1234)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55479,7 +57845,7 @@ (INSTANCE z80_\|memory_ifc_\|nRFSH_out\~0) (DELAY (ABSOLUTE - (PORT datad (621:621:621) (666:666:666)) + (PORT datad (252:252:252) (324:324:324)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55490,8 +57856,8 @@ (INSTANCE z80_\|memory_ifc_\|nM1_out) (DELAY (ABSOLUTE - (PORT datac (1282:1282:1282) (1346:1346:1346)) - (PORT datad (621:621:621) (669:669:669)) + (PORT datac (1472:1472:1472) (1513:1513:1513)) + (PORT datad (250:250:250) (324:324:324)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55502,10 +57868,10 @@ (INSTANCE ula_\|beep\~0) (DELAY (ABSOLUTE - (PORT datab (1714:1714:1714) (1839:1839:1839)) - (PORT datac (3217:3217:3217) (3502:3502:3502)) - (PORT datad (1247:1247:1247) (1342:1342:1342)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (973:973:973) (1037:1037:1037)) + (PORT datac (3465:3465:3465) (3837:3837:3837)) + (PORT datad (596:596:596) (610:610:610)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55516,9 +57882,9 @@ (INSTANCE ula_\|beep) (DELAY (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT clk (1522:1522:1522) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2564:2564:2564) (2572:2572:2572)) + (PORT ena (997:997:997) (1007:1007:1007)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55527,4 +57893,2294 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux26\~4) + (DELAY + (ABSOLUTE + (PORT dataa (2317:2317:2317) (2532:2532:2532)) + (PORT datab (938:938:938) (974:974:974)) + (PORT datad (1425:1425:1425) (1536:1536:1536)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT datac (989:989:989) (1111:1111:1111)) + (PORT datad (1785:1785:1785) (1929:1929:1929)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (953:953:953)) + (PORT datab (830:830:830) (930:930:930)) + (PORT datac (782:782:782) (889:889:889)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (292:292:292) (378:378:378)) + (PORT datac (585:585:585) (604:604:604)) + (PORT datad (284:284:284) (364:364:364)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1030:1030:1030) (1121:1121:1121)) + (PORT datab (1035:1035:1035) (1089:1089:1089)) + (PORT datac (1056:1056:1056) (1136:1136:1136)) + (PORT datad (599:599:599) (611:611:611)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1315:1315:1315) (1427:1427:1427)) + (PORT datab (1874:1874:1874) (2002:2002:2002)) + (PORT datac (992:992:992) (1110:1110:1110)) + (PORT datad (778:778:778) (811:811:811)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (1299:1299:1299) (1369:1369:1369)) + (PORT datac (1841:1841:1841) (1973:1973:1973)) + (PORT datad (995:995:995) (1099:1099:1099)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (958:958:958)) + (PORT datab (829:829:829) (935:935:935)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (181:181:181) (211:211:211)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1316:1316:1316) (1427:1427:1427)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.bank\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1539:1539:1539)) + (PORT d (1777:1777:1777) (1875:1875:1875)) + (PORT ena (1774:1774:1774) (1775:1775:1775)) + (IOPATH (posedge clk) q (586:586:586) (589:589:589)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (82:82:82)) + (SETUP ena (posedge clk) (82:82:82)) + (HOLD d (posedge clk) (97:97:97)) + (HOLD ena (posedge clk) (97:97:97)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux25\~4) + (DELAY + (ABSOLUTE + (PORT dataa (2317:2317:2317) (2534:2534:2534)) + (PORT datab (1431:1431:1431) (1561:1561:1561)) + (PORT datad (913:913:913) (939:939:939)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.bank\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1540:1540:1540)) + (PORT d (2321:2321:2321) (2432:2432:2432)) + (PORT ena (1597:1597:1597) (1608:1608:1608)) + (IOPATH (posedge clk) q (586:586:586) (589:589:589)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (82:82:82)) + (SETUP ena (posedge clk) (82:82:82)) + (HOLD d (posedge clk) (97:97:97)) + (HOLD ena (posedge clk) (97:97:97)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1066:1066:1066) (1202:1202:1202)) + (PORT datab (1024:1024:1024) (1113:1113:1113)) + (PORT datac (1152:1152:1152) (1196:1196:1196)) + (PORT datad (994:994:994) (1081:1081:1081)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~0) + (DELAY + (ABSOLUTE + (PORT datab (1399:1399:1399) (1527:1527:1527)) + (PORT datac (1575:1575:1575) (1656:1656:1656)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~7) + (DELAY + (ABSOLUTE + (PORT datab (1709:1709:1709) (1882:1882:1882)) + (PORT datac (221:221:221) (300:300:300)) + (PORT datad (2617:2617:2617) (2813:2813:2813)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (704:704:704) (772:772:772)) + (PORT datab (201:201:201) (240:240:240)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (183:183:183) (213:213:213)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1307:1307:1307) (1422:1422:1422)) + (PORT datab (1474:1474:1474) (1580:1580:1580)) + (PORT datac (1576:1576:1576) (1657:1657:1657)) + (PORT datad (1362:1362:1362) (1488:1488:1488)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1306:1306:1306) (1421:1421:1421)) + (PORT datab (1020:1020:1020) (1139:1139:1139)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (189:189:189) (219:219:219)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1090:1090:1090) (1128:1128:1128)) + (PORT datab (215:215:215) (260:260:260)) + (PORT datac (1032:1032:1032) (1159:1159:1159)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux71\~4) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (171:171:171) (202:202:202)) + (PORT datad (996:996:996) (1103:1103:1103)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.dq_masks\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1537:1537:1537)) + (PORT d (1467:1467:1467) (1545:1545:1545)) + (IOPATH (posedge clk) q (586:586:586) (589:589:589)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (82:82:82)) + (HOLD d (posedge clk) (97:97:97)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.dq_masks\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1537:1537:1537)) + (PORT d (1454:1454:1454) (1530:1530:1530)) + (IOPATH (posedge clk) q (586:586:586) (589:589:589)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (82:82:82)) + (HOLD d (posedge clk) (97:97:97)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.bank\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT datac (1570:1570:1570) (1649:1649:1649)) + (PORT datad (996:996:996) (1103:1103:1103)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~3) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (399:399:399)) + (PORT datab (1477:1477:1477) (1604:1604:1604)) + (PORT datac (1329:1329:1329) (1470:1470:1470)) + (PORT datad (353:353:353) (368:368:368)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~5) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (521:521:521)) + (PORT datab (698:698:698) (778:778:778)) + (PORT datac (586:586:586) (604:604:604)) + (PORT datad (285:285:285) (364:364:364)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~4) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (378:378:378)) + (PORT datab (1370:1370:1370) (1466:1466:1466)) + (PORT datac (882:882:882) (893:893:893)) + (PORT datad (1440:1440:1440) (1565:1565:1565)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1366:1366:1366) (1518:1518:1518)) + (PORT datab (1371:1371:1371) (1460:1460:1460)) + (PORT datac (881:881:881) (891:891:891)) + (PORT datad (1253:1253:1253) (1312:1312:1312)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (870:870:870)) + (PORT datab (302:302:302) (394:394:394)) + (PORT datac (631:631:631) (680:680:680)) + (PORT datad (754:754:754) (832:832:832)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~2) + (DELAY + (ABSOLUTE + (PORT datab (449:449:449) (513:513:513)) + (PORT datac (415:415:415) (481:481:481)) + (PORT datad (588:588:588) (645:645:645)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~3) + (DELAY + (ABSOLUTE + (PORT dataa (420:420:420) (498:498:498)) + (PORT datab (272:272:272) (357:357:357)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (425:425:425) (483:483:483)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|process_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (418:418:418) (497:497:497)) + (PORT datab (450:450:450) (516:516:516)) + (PORT datac (353:353:353) (381:381:381)) + (PORT datad (411:411:411) (473:473:473)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~4) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (423:423:423) (493:493:493)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (683:683:683) (766:766:766)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1426:1426:1426) (1547:1547:1547)) + (PORT datab (1604:1604:1604) (1732:1732:1732)) + (PORT datac (1336:1336:1336) (1427:1427:1427)) + (PORT datad (332:332:332) (354:354:354)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux7\~0) + (DELAY + (ABSOLUTE + (PORT datab (1369:1369:1369) (1466:1466:1466)) + (PORT datad (1568:1568:1568) (1695:1695:1695)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~6) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (423:423:423)) + (PORT datab (643:643:643) (685:685:685)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux9\~7) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (1269:1269:1269) (1350:1350:1350)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1498:1498:1498) (1529:1529:1529)) + (PORT d (1472:1472:1472) (1557:1557:1557)) + (IOPATH (posedge clk) q (617:617:617) (612:612:612)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (80:80:80)) + (HOLD d (posedge clk) (101:101:101)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~11) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1112:1112:1112)) + (PORT datab (1023:1023:1023) (1115:1115:1115)) + (PORT datac (1152:1152:1152) (1199:1199:1199)) + (PORT datad (995:995:995) (1083:1083:1083)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1063:1063:1063) (1201:1201:1201)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (1060:1060:1060) (1092:1092:1092)) + (PORT datad (968:968:968) (1089:1089:1089)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1306:1306:1306) (1421:1421:1421)) + (PORT datab (1399:1399:1399) (1528:1528:1528)) + (PORT datac (948:948:948) (1069:1069:1069)) + (PORT datad (635:635:635) (671:671:671)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1062:1062:1062) (1202:1202:1202)) + (PORT datab (1398:1398:1398) (1531:1531:1531)) + (PORT datac (948:948:948) (1074:1074:1074)) + (PORT datad (968:968:968) (1089:1089:1089)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~8) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (1021:1021:1021) (1144:1144:1144)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux10\~9) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1498:1498:1498) (1529:1529:1529)) + (PORT d (1253:1253:1253) (1356:1356:1356)) + (IOPATH (posedge clk) q (617:617:617) (612:612:612)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (80:80:80)) + (HOLD d (posedge clk) (101:101:101)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ena_reg") + (INSTANCE sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl_e_DRAM_CLK.extena0_reg) + (DELAY + (ABSOLUTE + (PORT d (288:288:288) (259:259:259)) + (PORT clk (0:0:0) (0:0:0)) + (IOPATH (posedge clk) q (166:166:166) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (94:94:94)) + (HOLD d (posedge clk) (83:83:83)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ena_reg") + (INSTANCE sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl_e_DRAM_CLK.extena1_reg) + (DELAY + (ABSOLUTE + (PORT d (0:0:0) (0:0:0)) + (PORT clk (0:0:0) (0:0:0)) + (IOPATH (posedge clk) q (281:281:281) (258:258:258)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (94:94:94)) + (HOLD d (posedge clk) (83:83:83)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~2) + (DELAY + (ABSOLUTE + (PORT dataa (743:743:743) (861:861:861)) + (PORT datab (780:780:780) (870:870:870)) + (PORT datad (273:273:273) (356:356:356)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1511:1511:1511) (1631:1631:1631)) + (PORT datab (655:655:655) (707:707:707)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1409:1409:1409) (1518:1518:1518)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1360:1360:1360) (1508:1508:1508)) + (PORT datab (1372:1372:1372) (1466:1466:1466)) + (PORT datac (626:626:626) (666:666:666)) + (PORT datad (323:323:323) (345:345:345)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1359:1359:1359) (1509:1509:1509)) + (PORT datab (1372:1372:1372) (1466:1466:1466)) + (PORT datac (1581:1581:1581) (1661:1661:1661)) + (PORT datad (1257:1257:1257) (1317:1317:1317)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~6) + (DELAY + (ABSOLUTE + (PORT dataa (985:985:985) (1116:1116:1116)) + (PORT datab (1024:1024:1024) (1143:1143:1143)) + (PORT datac (1035:1035:1035) (1162:1162:1162)) + (PORT datad (971:971:971) (1090:1090:1090)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~7) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (960:960:960)) + (PORT datab (829:829:829) (930:930:930)) + (PORT datac (783:783:783) (893:893:893)) + (PORT datad (313:313:313) (331:331:331)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1426:1426:1426) (1549:1549:1549)) + (PORT datab (1264:1264:1264) (1350:1350:1350)) + (PORT datac (883:883:883) (894:894:894)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux11\~8) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (597:597:597) (604:604:604)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.state\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1495:1495:1495) (1520:1520:1520)) + (PORT d (1809:1809:1809) (1935:1935:1935)) + (IOPATH (posedge clk) q (617:617:617) (612:612:612)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (80:80:80)) + (HOLD d (posedge clk) (101:101:101)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~2) + (DELAY + (ABSOLUTE + (PORT dataa (776:776:776) (869:869:869)) + (PORT datab (765:765:765) (852:852:852)) + (PORT datac (764:764:764) (877:877:877)) + (PORT datad (860:860:860) (888:888:888)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (3061:3061:3061) (3225:3225:3225)) + (PORT datab (612:612:612) (668:668:668)) + (PORT datac (1038:1038:1038) (1141:1141:1141)) + (PORT datad (632:632:632) (661:661:661)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (632:632:632)) + (PORT datab (993:993:993) (1068:1068:1068)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1359:1359:1359) (1510:1510:1510)) + (PORT datab (1269:1269:1269) (1353:1353:1353)) + (PORT datac (1581:1581:1581) (1661:1661:1661)) + (PORT datad (1441:1441:1441) (1561:1561:1561)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1367:1367:1367) (1518:1518:1518)) + (PORT datab (1264:1264:1264) (1346:1346:1346)) + (PORT datac (1575:1575:1575) (1654:1654:1654)) + (PORT datad (1444:1444:1444) (1567:1567:1567)) + (IOPATH dataa combout (337:337:337) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~5) + (DELAY + (ABSOLUTE + (PORT datab (1371:1371:1371) (1460:1460:1460)) + (PORT datac (175:175:175) (208:208:208)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[0\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1560:1560:1560)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (523:523:523) (557:557:557)) + (PORT sload (1639:1639:1639) (1751:1751:1751)) + (PORT ena (1247:1247:1247) (1254:1254:1254)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~3) + (DELAY + (ABSOLUTE + (PORT dataa (3061:3061:3061) (3223:3223:3223)) + (PORT datab (613:613:613) (668:668:668)) + (PORT datac (380:380:380) (405:405:405)) + (PORT datad (632:632:632) (657:657:657)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux24\~4) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (956:956:956)) + (PORT datab (614:614:614) (671:671:671)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1100:1100:1100) (1185:1185:1185)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[0\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT datab (1063:1063:1063) (1134:1134:1134)) + (PORT datac (179:179:179) (214:214:214)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1497:1497:1497) (1522:1522:1522)) + (PORT d (2000:2000:2000) (2102:2102:2102)) + (PORT ena (1672:1672:1672) (1717:1717:1717)) + (IOPATH (posedge clk) q (617:617:617) (612:612:612)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (80:80:80)) + (SETUP ena (posedge clk) (80:80:80)) + (HOLD d (posedge clk) (101:101:101)) + (HOLD ena (posedge clk) (101:101:101)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~_Duplicate_1feeder) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (257:257:257)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1030:1030:1030) (1137:1137:1137)) + (PORT datab (251:251:251) (337:337:337)) + (PORT datac (1288:1288:1288) (1347:1347:1347)) + (PORT datad (333:333:333) (361:361:361)) + (IOPATH dataa combout (301:301:301) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Equal5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (748:748:748) (867:867:867)) + (PORT datab (780:780:780) (874:874:874)) + (PORT datac (627:627:627) (678:678:678)) + (PORT datad (275:275:275) (357:357:357)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1030:1030:1030) (1138:1138:1138)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (957:957:957) (1041:1041:1041)) + (PORT datad (864:864:864) (898:898:898)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1033:1033:1033) (1138:1138:1138)) + (PORT datab (1067:1067:1067) (1184:1184:1184)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (886:886:886) (884:884:884)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1284:1284:1284) (1361:1361:1361)) + (PORT datab (1090:1090:1090) (1165:1165:1165)) + (PORT datac (1257:1257:1257) (1368:1368:1368)) + (PORT datad (1000:1000:1000) (1053:1053:1053)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[1\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (523:523:523) (558:558:558)) + (PORT sload (1747:1747:1747) (1674:1674:1674)) + (PORT ena (1291:1291:1291) (1292:1292:1292)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1311:1311:1311) (1441:1441:1441)) + (PORT datab (360:360:360) (395:395:395)) + (PORT datac (957:957:957) (1039:1039:1039)) + (PORT datad (989:989:989) (1074:1074:1074)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1312:1312:1312) (1442:1442:1442)) + (PORT datac (518:518:518) (537:537:537)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1308:1308:1308) (1440:1440:1440)) + (PORT datab (2607:2607:2607) (2785:2785:2785)) + (PORT datac (1734:1734:1734) (1812:1812:1812)) + (PORT datad (991:991:991) (1080:1080:1080)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (335:335:335)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[1\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (258:258:258)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (1028:1028:1028) (1131:1131:1131)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1540:1540:1540)) + (PORT d (1503:1503:1503) (1609:1609:1609)) + (PORT ena (1911:1911:1911) (1938:1938:1938)) + (IOPATH (posedge clk) q (586:586:586) (589:589:589)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (82:82:82)) + (SETUP ena (posedge clk) (82:82:82)) + (HOLD d (posedge clk) (97:97:97)) + (HOLD ena (posedge clk) (97:97:97)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1304:1304:1304) (1437:1437:1437)) + (PORT datab (1036:1036:1036) (1094:1094:1094)) + (PORT datac (1028:1028:1028) (1133:1133:1133)) + (PORT datad (990:990:990) (1085:1085:1085)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT datab (1036:1036:1036) (1091:1091:1091)) + (PORT datad (1280:1280:1280) (1394:1394:1394)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux21\~0) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (287:287:287)) + (PORT datab (1062:1062:1062) (1180:1180:1180)) + (PORT datac (314:314:314) (333:333:333)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux22\~0) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (748:748:748)) + (PORT datab (220:220:220) (260:260:260)) + (PORT datac (879:879:879) (894:894:894)) + (PORT datad (635:635:635) (660:660:660)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1813:1813:1813) (1972:1972:1972)) + (PORT datab (1021:1021:1021) (1144:1144:1144)) + (PORT datac (781:781:781) (894:894:894)) + (PORT datad (790:790:790) (895:895:895)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (816:816:816) (925:925:925)) + (PORT datac (1840:1840:1840) (1973:1973:1973)) + (PORT datad (994:994:994) (1103:1103:1103)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (953:953:953)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datac (1841:1841:1841) (1971:1971:1971)) + (PORT datad (1238:1238:1238) (1284:1284:1284)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1315:1315:1315) (1427:1427:1427)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (1396:1396:1396) (1469:1469:1469)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1812:1812:1812) (1971:1971:1971)) + (PORT datab (1021:1021:1021) (1141:1141:1141)) + (PORT datac (782:782:782) (892:892:892)) + (PORT datad (790:790:790) (893:893:893)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (954:954:954)) + (PORT datab (199:199:199) (236:236:236)) + (PORT datac (1395:1395:1395) (1469:1469:1469)) + (PORT datad (994:994:994) (1100:1100:1100)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (265:265:265)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1233:1233:1233) (1279:1279:1279)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[3\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datac (988:988:988) (1107:1107:1107)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1540:1540:1540)) + (PORT d (1841:1841:1841) (1973:1973:1973)) + (PORT ena (1809:1809:1809) (1846:1846:1846)) + (IOPATH (posedge clk) q (586:586:586) (589:589:589)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (82:82:82)) + (SETUP ena (posedge clk) (82:82:82)) + (HOLD d (posedge clk) (97:97:97)) + (HOLD ena (posedge clk) (97:97:97)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux21\~1) + (DELAY + (ABSOLUTE + (PORT dataa (696:696:696) (743:743:743)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (194:194:194) (226:226:226)) + (PORT datad (638:638:638) (663:663:663)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1539:1539:1539)) + (PORT d (1556:1556:1556) (1651:1651:1651)) + (PORT ena (1611:1611:1611) (1629:1629:1629)) + (IOPATH (posedge clk) q (586:586:586) (589:589:589)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (82:82:82)) + (SETUP ena (posedge clk) (82:82:82)) + (HOLD d (posedge clk) (97:97:97)) + (HOLD ena (posedge clk) (97:97:97)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~4) + (DELAY + (ABSOLUTE + (PORT dataa (748:748:748) (867:867:867)) + (PORT datab (781:781:781) (871:871:871)) + (PORT datad (273:273:273) (355:355:355)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1010:1010:1010) (1114:1114:1114)) + (PORT datab (2651:2651:2651) (2850:2850:2850)) + (PORT datac (1684:1684:1684) (1854:1854:1854)) + (PORT datad (931:931:931) (983:983:983)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux23\~7) + (DELAY + (ABSOLUTE + (PORT dataa (799:799:799) (926:926:926)) + (PORT datab (897:897:897) (930:930:930)) + (PORT datac (1265:1265:1265) (1390:1390:1390)) + (PORT datad (820:820:820) (839:839:839)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1032:1032:1032) (1126:1126:1126)) + (PORT datab (959:959:959) (1003:1003:1003)) + (PORT datac (1256:1256:1256) (1370:1370:1370)) + (PORT datad (1256:1256:1256) (1321:1321:1321)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1285:1285:1285) (1370:1370:1370)) + (PORT datab (658:658:658) (687:687:687)) + (PORT datac (589:589:589) (593:593:593)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1285:1285:1285) (1362:1362:1362)) + (PORT datab (660:660:660) (691:691:691)) + (PORT datac (588:588:588) (590:590:590)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH dataa combout (341:341:341) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~11) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (492:492:492)) + (PORT datab (904:904:904) (946:946:946)) + (PORT datac (312:312:312) (339:339:339)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[4\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1561:1561:1561)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (684:684:684) (700:700:700)) + (PORT sload (1665:1665:1665) (1784:1784:1784)) + (PORT ena (980:980:980) (972:972:972)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~12) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (813:813:813)) + (PORT datab (2069:2069:2069) (2248:2248:2248)) + (PORT datac (2283:2283:2283) (2471:2471:2471)) + (PORT datad (867:867:867) (902:902:902)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~5) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (654:654:654) (706:706:706)) + (PORT datac (1578:1578:1578) (1695:1695:1695)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux20\~6) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (658:658:658)) + (PORT datab (905:905:905) (948:948:948)) + (PORT datac (994:994:994) (1085:1085:1085)) + (PORT datad (378:378:378) (448:448:448)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[4\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1283:1283:1283) (1363:1363:1363)) + (PORT datab (616:616:616) (667:667:667)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[4\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT datab (1089:1089:1089) (1165:1165:1165)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1542:1542:1542)) + (PORT d (1700:1700:1700) (1761:1761:1761)) + (PORT ena (2295:2295:2295) (2346:2346:2346)) + (IOPATH (posedge clk) q (586:586:586) (589:589:589)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (82:82:82)) + (SETUP ena (posedge clk) (82:82:82)) + (HOLD d (posedge clk) (97:97:97)) + (HOLD ena (posedge clk) (97:97:97)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~1) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (869:869:869)) + (PORT datab (781:781:781) (872:872:872)) + (PORT datac (630:630:630) (679:679:679)) + (PORT datad (274:274:274) (354:354:354)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1285:1285:1285) (1367:1367:1367)) + (PORT datac (589:589:589) (593:593:593)) + (PORT datad (598:598:598) (611:611:611)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1289:1289:1289) (1364:1364:1364)) + (PORT datab (1055:1055:1055) (1148:1148:1148)) + (PORT datac (1259:1259:1259) (1369:1369:1369)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1285:1285:1285) (1371:1371:1371)) + (PORT datab (1057:1057:1057) (1150:1150:1150)) + (PORT datac (1257:1257:1257) (1371:1371:1371)) + (PORT datad (181:181:181) (211:211:211)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1377:1377:1377) (1426:1426:1426)) + (PORT datab (404:404:404) (482:482:482)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[5\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1561:1561:1561)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (524:524:524) (559:559:559)) + (PORT sload (1665:1665:1665) (1784:1784:1784)) + (PORT ena (980:980:980) (972:972:972)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~2) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (889:889:889) (939:939:939)) + (PORT datac (1575:1575:1575) (1696:1696:1696)) + (PORT datad (635:635:635) (714:714:714)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux19\~3) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (656:656:656)) + (PORT datab (1058:1058:1058) (1148:1148:1148)) + (PORT datac (1348:1348:1348) (1386:1386:1386)) + (PORT datad (380:380:380) (445:445:445)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[5\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1290:1290:1290) (1371:1371:1371)) + (PORT datab (642:642:642) (688:688:688)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[5\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (1091:1091:1091) (1170:1170:1170)) + (PORT datac (181:181:181) (218:218:218)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1539:1539:1539)) + (PORT d (1443:1443:1443) (1520:1520:1520)) + (PORT ena (2198:2198:2198) (2202:2202:2202)) + (IOPATH (posedge clk) q (586:586:586) (589:589:589)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (82:82:82)) + (SETUP ena (posedge clk) (82:82:82)) + (HOLD d (posedge clk) (97:97:97)) + (HOLD ena (posedge clk) (97:97:97)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux18\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2415:2415:2415) (2626:2626:2626)) + (PORT datac (1237:1237:1237) (1358:1358:1358)) + (PORT datad (667:667:667) (699:699:699)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1539:1539:1539)) + (PORT d (1527:1527:1527) (1623:1623:1623)) + (PORT ena (1611:1611:1611) (1629:1629:1629)) + (IOPATH (posedge clk) q (586:586:586) (589:589:589)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (82:82:82)) + (SETUP ena (posedge clk) (82:82:82)) + (HOLD d (posedge clk) (97:97:97)) + (HOLD ena (posedge clk) (97:97:97)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2411:2411:2411) (2624:2624:2624)) + (PORT datac (1497:1497:1497) (1597:1597:1597)) + (PORT datad (667:667:667) (698:698:698)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1537:1537:1537)) + (PORT d (1993:1993:1993) (2101:2101:2101)) + (PORT ena (1609:1609:1609) (1676:1676:1676)) + (IOPATH (posedge clk) q (586:586:586) (589:589:589)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (82:82:82)) + (SETUP ena (posedge clk) (82:82:82)) + (HOLD d (posedge clk) (97:97:97)) + (HOLD ena (posedge clk) (97:97:97)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux16\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2422:2422:2422) (2635:2635:2635)) + (PORT datac (243:243:243) (322:322:322)) + (PORT datad (667:667:667) (698:698:698)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1495:1495:1495) (1520:1520:1520)) + (PORT d (2142:2142:2142) (2266:2266:2266)) + (PORT ena (1415:1415:1415) (1456:1456:1456)) + (IOPATH (posedge clk) q (617:617:617) (612:612:612)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (80:80:80)) + (SETUP ena (posedge clk) (80:80:80)) + (HOLD d (posedge clk) (101:101:101)) + (HOLD ena (posedge clk) (101:101:101)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux15\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2424:2424:2424) (2635:2635:2635)) + (PORT datab (933:933:933) (1032:1032:1032)) + (PORT datad (667:667:667) (702:702:702)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1497:1497:1497) (1522:1522:1522)) + (PORT d (2142:2142:2142) (2261:2261:2261)) + (PORT ena (1453:1453:1453) (1505:1505:1505)) + (IOPATH (posedge clk) q (617:617:617) (612:612:612)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (80:80:80)) + (SETUP ena (posedge clk) (80:80:80)) + (HOLD d (posedge clk) (101:101:101)) + (HOLD ena (posedge clk) (101:101:101)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (737:737:737)) + (PORT datab (711:711:711) (800:800:800)) + (PORT datac (1260:1260:1260) (1352:1352:1352)) + (PORT datad (181:181:181) (207:207:207)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~1) + (DELAY + (ABSOLUTE + (PORT dataa (686:686:686) (729:729:729)) + (PORT datab (407:407:407) (478:478:478)) + (PORT datac (1035:1035:1035) (1137:1137:1137)) + (PORT datad (627:627:627) (654:654:654)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[10\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (993:993:993) (1068:1068:1068)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[10\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1560:1560:1560)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (523:523:523) (557:557:557)) + (PORT sload (1639:1639:1639) (1751:1751:1751)) + (PORT ena (1247:1247:1247) (1254:1254:1254)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|n\~4) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (923:923:923)) + (PORT datab (406:406:406) (476:476:476)) + (PORT datac (676:676:676) (747:747:747)) + (PORT datad (675:675:675) (725:725:725)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~2) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (740:740:740)) + (PORT datab (712:712:712) (801:801:801)) + (PORT datac (1257:1257:1257) (1357:1357:1357)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux14\~3) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (406:406:406) (474:474:474)) + (PORT datac (381:381:381) (407:407:407)) + (PORT datad (632:632:632) (657:657:657)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[10\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT datab (1064:1064:1064) (1139:1139:1139)) + (PORT datac (181:181:181) (217:217:217)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1488:1488:1488) (1513:1513:1513)) + (PORT d (1458:1458:1458) (1539:1539:1539)) + (PORT ena (1669:1669:1669) (1698:1698:1698)) + (IOPATH (posedge clk) q (617:617:617) (612:612:612)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (80:80:80)) + (SETUP ena (posedge clk) (80:80:80)) + (HOLD d (posedge clk) (101:101:101)) + (HOLD ena (posedge clk) (101:101:101)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (766:766:766) (848:848:848)) + (PORT datac (1262:1262:1262) (1381:1381:1381)) + (PORT datad (735:735:735) (822:822:822)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1000:1000:1000) (1091:1091:1091)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (225:225:225) (305:305:305)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (341:341:341) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_2feeder) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (266:266:266)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_2) + (DELAY + (ABSOLUTE + (PORT clk (1536:1536:1536) (1559:1559:1559)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (530:530:530) (570:570:570)) + (PORT sload (1322:1322:1322) (1457:1457:1457)) + (PORT ena (1290:1290:1290) (1318:1318:1318)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~10) + (DELAY + (ABSOLUTE + (PORT datab (249:249:249) (334:334:334)) + (PORT datac (768:768:768) (884:884:884)) + (PORT datad (677:677:677) (777:777:777)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|Mux13\~6) + (DELAY + (ABSOLUTE + (PORT dataa (793:793:793) (920:920:920)) + (PORT datab (895:895:895) (926:926:926)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (818:818:818) (836:836:836)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (270:270:270)) + (PORT datab (737:737:737) (847:847:847)) + (PORT datac (189:189:189) (231:231:231)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1502:1502:1502) (1530:1530:1530)) + (PORT d (1252:1252:1252) (1354:1354:1354)) + (PORT ena (1396:1396:1396) (1412:1412:1412)) + (IOPATH (posedge clk) q (617:617:617) (612:612:612)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (80:80:80)) + (SETUP ena (posedge clk) (80:80:80)) + (HOLD d (posedge clk) (101:101:101)) + (HOLD ena (posedge clk) (101:101:101)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_1SLOAD_MUX) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (267:267:267)) + (PORT datab (738:738:738) (843:843:843)) + (PORT datac (187:187:187) (229:229:229)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_\|r\.address\[11\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1493:1493:1493) (1518:1518:1518)) + (PORT d (1706:1706:1706) (1798:1798:1798)) + (PORT ena (1700:1700:1700) (1737:1737:1737)) + (IOPATH (posedge clk) q (617:617:617) (612:612:612)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (80:80:80)) + (SETUP ena (posedge clk) (80:80:80)) + (HOLD d (posedge clk) (101:101:101)) + (HOLD ena (posedge clk) (101:101:101)) + ) + ) ) diff --git a/spectrum.qsf b/spectrum.qsf index 09136a5..e4cc034 100644 --- a/spectrum.qsf +++ b/spectrum.qsf @@ -462,4 +462,6 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to buzzer_out set_location_assignment PIN_B6 -to raw_loader_in set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to raw_loader_in set_global_assignment -name QIP_FILE ram_video.qip +set_global_assignment -name VHDL_FILE sdram.vhdl +set_global_assignment -name QIP_FILE sdram_clk_gen.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/spectrum.sv b/spectrum.sv index 2ed0853..5dd3e68 100644 --- a/spectrum.sv +++ b/spectrum.sv @@ -19,7 +19,18 @@ module spectrum(output wire[7:0] LED, input wire[3:0] SW, // 0 = ROM selection, 1 = enable/disable interrupts, 2 = turbo speed output wire[33:0] GPIO_1, // Exports CPU chip pins, output wire buzzer_out, - input wire raw_loader_in + input wire raw_loader_in, + output wire[1:0] DRAM_BA, + output wire[1:0] DRAM_DQM, + output wire DRAM_RAS_N, + output wire DRAM_CAS_N, + output wire DRAM_CKE, + output wire DRAM_CLK, + output wire DRAM_WE_N, + output wire DRAM_CS_N, + inout wire[15:0] DRAM_DQ, + output wire[12:0] DRAM_ADDR + ); `default_nettype none @@ -103,6 +114,7 @@ begin 2'b00: D[7:0] = rom_data; 2'b01: D[7:0] = ram0_data; 2'b1?: D[7:0] = ram1_data; +// 2'b1?: D[7:0] = sdram_out_data[7:0]; endcase end // ---------------------------------- IO read ---------------------------------- @@ -169,6 +181,68 @@ ram32 ram1( .wren(ExtRamWE) ); + +// +// SDRAM for 128K +// + +wire[31:0] sdram_out_data; +wire sdram_out_valid; +wire sdram_read_request; +wire sdram_write_request; + +assign sdram_read_request = nIORQ == 1 && nRD == 0 && nWR == 1; +assign sdram_write_request = ExtRamWE; + +sdram_controller sdram_( + .CLOCK_50(CLOCK_50), + .DRAM_ADDR(DRAM_ADDR), + .DRAM_BA(DRAM_BA), + .DRAM_CAS_N(DRAM_CAS_N), + .DRAM_CKE(DRAM_CKE), + .DRAM_CLK(DRAM_CLK), + .DRAM_CS_N(DRAM_CS_N), + .DRAM_DQ(DRAM_DQ), + .DRAM_DQM(DRAM_DQM), + .DRAM_RAS_N(DRAM_RAS_N), + .DRAM_WE_N(DRAM_WE_N), + + .address({8'd0, A}), + .req_read(sdram_read_request), + .req_write(sdram_write_request), + .data_out(sdram_out_data), + .data_out_valid(sdram_out_valid), + .data_in({24'd0, D[7:0]}) +); + +/* +entity sdram_controller is + PORT ( + CLOCK_50 : IN STD_LOGIC; + + -- Signals to/from the SDRAM chip + DRAM_ADDR : OUT STD_LOGIC_VECTOR (12 downto 0); + DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0); + DRAM_CAS_N : OUT STD_LOGIC; + DRAM_CKE : OUT STD_LOGIC; + DRAM_CLK : OUT STD_LOGIC; + DRAM_CS_N : OUT STD_LOGIC; + DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0); + DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0); + DRAM_RAS_N : OUT STD_LOGIC; + DRAM_WE_N : OUT STD_LOGIC; + + --- Inputs from rest of the system + address : IN STD_LOGIC_VECTOR (23 downto 0); + req_read : IN STD_LOGIC; + req_write : IN STD_LOGIC; + data_out : OUT STD_LOGIC_VECTOR (31 downto 0); + data_out_valid : OUT STD_LOGIC; + data_in : IN STD_LOGIC_VECTOR (31 downto 0) + ); +end entity; +*/ + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // Instantiate ULA //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~